[ { "path": "IR/README.txt", "content": "IR.pde -- Arduino code for IR that sends the first request repeatedly, and waits for a listening Tamagotchi\r\nIR2.pde -- Arduino code for IR that waits for the first request, and responds (Tamagotchi intiates interaction)" }, { "path": "IR/ir.pde", "content": "#define BIT_IS_SET(i, bits) (1 << i & bits)\r\n\r\n// LED connected to digital pin 13\r\nconst int LED_PIN = 13;\r\n// Width of a pulse, in microseconds\r\nconst int PULSE_WIDTH = 2300;\r\n// # of bytes per command\r\nconst int COMMAND_LENGTH = 4; \r\n\r\n//const int REQUEST[] = {0xac, 0, 0xde, 0xde, 2, 0xd, 5, 0x18, 0, 0, 0x14, 0x00, 0, 0, 0x10, 0, 2, 0, 0, 0xff, 1, 0xff, 0xff, 0x55};\r\n//const int RC[] = {0xac, 0x1a, 0xdd, 0xdd, 1, 2, 0, 0x3d, 0};\r\nint conf[9];\r\nint r[24];\r\n\r\n#include \r\n // choose the pin for the LED\r\nint inputPin = 2; // choose the input pin (for a pushbutton)\r\nint val = 0; // variable for reading the pin status\r\nint count;\r\nboolean done = false;\r\n\r\n void suck( int sig ){\r\n while(digitalRead(inputPin) == sig){ \r\n }\r\n \r\n }\r\n \r\n int decodebuf( int* b){\r\n int a = 0;\r\n for( int i = 0; i < 8; i++){\r\n if( b[i] != 1 &&b[i] != 2 &&b[i] != 3){\r\n Serial.println(\"I've fallen and i can't get up\");\r\n Serial.println(b[i]);\r\n }\r\n if( b[i] == 3)\r\n b[i] = 2;\r\n a = a + ((b[i] - 1) << i);\r\n }\r\n return a;\r\n }\r\n \r\n void getser(void){\r\n //while(Serial.available()){\r\n boolean gr = false;\r\n boolean gc = false;\r\n while(true){\r\n if(!Serial.available())\r\n continue;\r\n byte c = Serial.read();\r\n //Serial.println(c);\r\n if( c == 'R' ){\r\n for( int i = 0; i < 24; i++)\r\n {\r\n while(!Serial.available());\r\n r[i] = Serial.read();\r\n //Serial.println(Serial.read());\r\n }\r\n gr = true;\r\n Serial.println(\"read request\");\r\n \r\n }\r\n \r\n if( c == 'C' )\r\n {\r\n for( int i = 0; i < 9; i++)\r\n {\r\n //conf[i] = Serial.read();\r\n while(!Serial.available());\r\n conf[i] = Serial.read();\r\n //Serial.println(Serial.read());\r\n }\r\n Serial.println(\"read conf\");\r\n gc = true;\r\n }\r\n if (gr && gc)\r\n break;\r\n }\r\n //}\r\n }\r\nboolean dec(void){\r\n // int i = 0;\r\n\r\n// getser();\r\n int time;\r\n int diff, hi, lo;\r\n //char buf[9];\r\n int buf[400];\r\n int cycles = 0;\r\n int c;\r\n char obuf[12];\r\n int i;\r\n //char out = 0xf0;\r\n // for(i = 0; i < 7; i ++ ) {\r\n time = millis();\r\n while(digitalRead(inputPin) == HIGH ){ \r\n if( millis() - time > 5000){\r\n return false;\r\n }\r\n }\r\n time = millis();\r\n \r\n while(digitalRead(inputPin) == LOW){\r\n\r\n }\r\n diff = millis() - time;\r\n time = millis();\r\n if( diff > 8 && diff < 12){\r\n \r\n //while(digitalRead(inputPin) == LOW ){ \r\n //}\r\n time = millis();\r\n while(digitalRead(inputPin) == HIGH ){ \r\n }\r\n diff = millis() - time;\r\n if( diff < 0){\r\n Serial.println(\"NEG\");\r\n } \r\n if( diff > 1 && diff < 6){ \r\n // Serial.println(\"HIT \");\r\n // Serial.println(diff);\r\n // Serial.println( diff);\r\n cycles = 0; \r\n i = 0;\r\n while(true){\r\n // suck(HIGH);\r\n cycles++;\r\n time = micros();\r\n suck(LOW);\r\n lo = micros() - time;\r\n \r\n time = micros();\r\n if( lo > 1000){\r\n // Serial.println(\"SMALL LO\");\r\n // Serial.println(lo);\r\n // Serial.println(cycles);\r\n //cycles = 0;\r\n break;\r\n }\r\n suck(HIGH);\r\n hi = micros() - time;\r\n time = micros();\r\n buf[i] = hi/lo;\r\n i++;\r\n }\r\n Serial.println(\"DETECTED\");\r\n cycles = cycles/8;\r\n for( i = 0; i < cycles; i++){ \r\n c = decodebuf( buf + 8*i );\r\n sprintf( obuf, \"%x \", c);\r\n //for( i = 0; i < 16; i++){\r\n Serial.print(obuf);\r\n }\r\n cycles = 0;\r\n return true;\r\n //}\r\n }\r\n }\r\n else{\r\n \r\n\r\n }\r\n }\r\n\r\nvoid setup()\r\n{\r\n pinMode(LED_PIN, OUTPUT);\r\n Serial.begin(9600); // declare LED as output\r\n pinMode(inputPin, INPUT); \r\n // getser();\r\n //size(400, 300); \r\n\r\n // set inital background:\r\n// background(0);\r\n\r\n\r\n}\r\n\r\n/* Modulate pin at 39 kHz for give number of microseconds */\r\nvoid off(int pin, int time) {\r\n static const int period = 25;\r\n // found wait_time by measuring with oscilloscope\r\n// static const int wait_time = 12; \r\n\r\n for (time = time/period; time > 0; time--) {\r\n digitalWrite(pin, HIGH);\r\n delayMicroseconds(9);\r\n digitalWrite(pin, LOW);\r\n delayMicroseconds(9);\r\n }\r\n}\r\n\r\n\r\n\r\n/* Leave pin off for time (given in microseconds) */\r\nvoid on(int pin, int time) {\r\n digitalWrite(pin, LOW);\r\n delayMicroseconds(time);\r\n}\r\n\r\n/* Send a byte over the IR LED */\r\nvoid send_byte(int bits) {\r\n for (int i = 0; i < 8; i++)\r\n {\r\n if (BIT_IS_SET(i, bits)) {\r\n off(LED_PIN, 500);\r\n on(LED_PIN, 1270); \r\n\r\n \r\n\r\n } else {\r\n \r\n off(LED_PIN, 500);\r\n on(LED_PIN, 675);\r\n \r\n\r\n\r\n }\r\n }\r\n}\r\n\r\n/* Send a full command */\r\nvoid command(const int bytes[], int len) {\r\n \r\nint sum = 0;\r\n for (int i = 0; i < len -1; i++) {\r\n send_byte(bytes[i]);\r\n sum = sum + bytes[i];\r\n }\r\n send_byte(sum%256);\r\n off(LED_PIN, 1200); //check if not working\r\n on(LED_PIN, 0);\r\n}\r\n\r\n\r\nvoid loop()\r\n{\r\n\r\n if(!done){\r\n getser();\r\n done = true;\r\n } \r\n\r\n while (Serial.available() > 0) {\r\n Serial.write(Serial.read());\r\n }\r\n\r\n while(!dec()){\r\n off(LED_PIN, 9500);\r\n on(LED_PIN, 2500);\r\n command(r, 24);\r\n }\r\n \r\n do{\r\n off(LED_PIN, 9500);\r\n on(LED_PIN, 2500);\r\n command(conf, 9);\r\n }while(!dec());\r\n// delay(10000);\r\n// dec();\r\n}\r\n" }, { "path": "IR/ir2.pde", "content": "/* Control a Lutron Maestro light dimmer */\r\n#define BIT_IS_SET(i, bits) (1 << i & bits)\r\n\r\n// LED connected to digital pin 13\r\nconst int LED_PIN = 13;\r\n// Width of a pulse, in microseconds\r\nconst int PULSE_WIDTH = 2300;\r\n// # of bytes per command\r\nconst int COMMAND_LENGTH = 4; \r\n\r\nvolatile int REQUEST[] = {0xac, 1, 0x24, 0xd7, 0x0a, 1, 0x0e, 0x09, 0x05, 0x01, 0x03, 0x88, 0x00, 0x01, 0x33, 0xc0, 0x0b, 0, 0, 0xff, 1, 0xff, 0xff, 0x55};\r\n\r\nvolatile int RC[] = {0xac, 0x0b, 0x24, 0xd7, 0x00, 0x47, 0x0, 0x17, 0x5a };\r\nint conf[9];\r\nint r[24];\r\nvolatile int bounce = 0;\r\n\r\n#include \r\n // choose the pin for the LED\r\nint inputPin = 2; // choose the input pin (for a pushbutton)\r\nint val = 0; // variable for reading the pin status\r\nint count;\r\nvolatile int b = 0x47;\r\nboolean done = false;\r\n\r\n void suck( int sig ){\r\n while(digitalRead(inputPin) == sig){ \r\n }\r\n \r\n }\r\n \r\n int decodebuf( int* b){\r\n int a = 0;\r\n for( int i = 0; i < 8; i++){\r\n if( b[i] != 1 &&b[i] != 2 &&b[i] != 3){\r\n Serial.println(\"I've fallen and i can't get up\");\r\n Serial.println(b[i]);\r\n }\r\n if( b[i] == 3)\r\n b[i] = 2;\r\n a = a + ((b[i] - 1) << i);\r\n }\r\n return a;\r\n }\r\n \r\n void getser(void){\r\n //while(Serial.available()){\r\n boolean gr = false;\r\n boolean gc = false;\r\n while(true){\r\n if(!Serial.available())\r\n continue;\r\n byte c = Serial.read();\r\n //Serial.println(c);\r\n if( c == 'R' ){\r\n for( int i = 0; i < 24; i++)\r\n {\r\n while(!Serial.available());\r\n r[i] = Serial.read();\r\n //Serial.println(Serial.read());\r\n }\r\n gr = true;\r\n Serial.println(\"read request\");\r\n \r\n }\r\n \r\n if( c == 'C' )\r\n {\r\n for( int i = 0; i < 9; i++)\r\n {\r\n //conf[i] = Serial.read();\r\n while(!Serial.available());\r\n conf[i] = Serial.read();\r\n //Serial.println(Serial.read());\r\n }\r\n Serial.println(\"read conf\");\r\n gc = true;\r\n }\r\n if (gr && gc)\r\n break;\r\n }\r\n //}\r\n }\r\nboolean dec(void){\r\n // int i = 0;\r\n\r\n// getser();\r\n int time;\r\n int diff, hi, lo;\r\n //char buf[9];\r\n int buf[400];\r\n int cycles = 0;\r\n int c;\r\n char obuf[12];\r\n int i;\r\n //char out = 0xf0;\r\n // for(i = 0; i < 7; i ++ ) {\r\n time = millis();\r\n while(digitalRead(inputPin) == HIGH ){ \r\n if( millis() - time > 5000){\r\n return false;\r\n }\r\n }\r\n time = millis();\r\n \r\n while(digitalRead(inputPin) == LOW){\r\n\r\n }\r\n diff = millis() - time;\r\n time = millis();\r\n if( diff > 8 && diff < 12){\r\n \r\n //while(digitalRead(inputPin) == LOW ){ \r\n //}\r\n time = millis();\r\n while(digitalRead(inputPin) == HIGH ){ \r\n }\r\n diff = millis() - time;\r\n if( diff < 0){\r\n Serial.println(\"NEG\");\r\n } \r\n if( diff > 1 && diff < 6){ \r\n // Serial.println(\"HIT \");\r\n // Serial.println(diff);\r\n // Serial.println( diff);\r\n cycles = 0; \r\n i = 0;\r\n while(true){\r\n // suck(HIGH);\r\n cycles++;\r\n time = micros();\r\n suck(LOW);\r\n lo = micros() - time;\r\n \r\n time = micros();\r\n if( lo > 1000){\r\n // Serial.println(\"SMALL LO\");\r\n // Serial.println(lo);\r\n // Serial.println(cycles);\r\n //cycles = 0;\r\n break;\r\n }\r\n suck(HIGH);\r\n hi = micros() - time;\r\n time = micros();\r\n buf[i] = hi/lo;\r\n i++;\r\n }\r\n Serial.println(\"DETECTED\");\r\n cycles = cycles/8;\r\n for( i = 0; i < cycles; i++){ \r\n c = decodebuf( buf + 8*i );\r\n sprintf( obuf, \"%x \", c);\r\n \r\n //for( i = 0; i < 16; i++){\r\n Serial.print(obuf);\r\n }\r\n cycles = 0;\r\n return true;\r\n }\r\n }\r\n else{\r\n \r\n return false;\r\n }\r\n }\r\n\r\nvoid setup()\r\n{\r\n pinMode(LED_PIN, OUTPUT);\r\n Serial.begin(9600); // declare LED as output\r\n pinMode(inputPin, INPUT); \r\n // pinMode(5, INPUT);\r\n // attachInterrupt(1, blink, FALLING);\r\n // getser();\r\n //size(400, 300); \r\n\r\n // set inital background:\r\n// background(0);\r\n\r\n\r\n}\r\n\r\n/* Modulate pin at 39 kHz for give number of microseconds */\r\nvoid off(int pin, int time) {\r\n static const int period = 25;\r\n // found wait_time by measuring with oscilloscope\r\n// static const int wait_time = 12; \r\n\r\n for (time = time/period; time > 0; time--) {\r\n digitalWrite(pin, HIGH);\r\n delayMicroseconds(9);\r\n digitalWrite(pin, LOW);\r\n delayMicroseconds(9);\r\n }\r\n}\r\n\r\n\r\n\r\n/* Leave pin off for time (given in microseconds) */\r\nvoid on(int pin, int time) {\r\n digitalWrite(pin, LOW);\r\n delayMicroseconds(time);\r\n}\r\n\r\n/* Send a byte over the IR LED */\r\nvoid send_byte(int bits) {\r\n for (int i = 0; i < 8; i++)\r\n {\r\n if (BIT_IS_SET(i, bits)) {\r\n off(LED_PIN, 500);\r\n on(LED_PIN, 1270); \r\n\r\n \r\n\r\n } else {\r\n \r\n off(LED_PIN, 500);\r\n on(LED_PIN, 675);\r\n \r\n\r\n\r\n }\r\n }\r\n}\r\n\r\n/* Send a full command */\r\nvoid command(volatile int bytes[], int len) {\r\n \r\nint sum = 0;\r\n for (int i = 0; i < len -1; i++) {\r\n send_byte(bytes[i]);\r\n sum = sum + bytes[i];\r\n }\r\n send_byte(sum%256);\r\n off(LED_PIN, 1200); //check if not working\r\n on(LED_PIN, 0);\r\n}\r\n\r\n\r\nvoid loop()\r\n{\r\n\r\n /*if(!done){\r\n getser();\r\n done = true;\r\n } */ \r\n\r\n\r\n\r\nwhile(!dec()){}\r\n\r\n //if( digitalRead( 5 ) == HIGH)\r\n\r\n do{\r\n off(LED_PIN, 9500);\r\n on(LED_PIN, 2500);\r\n command(REQUEST, 24);\r\n }while(!dec());\r\n \r\n do{\r\n off(LED_PIN, 9500);\r\n on(LED_PIN, 2500);\r\n command(RC, 9);\r\n }while(!dec());\r\n// delay(10000);\r\n// dec();\r\n}\r\n\r\n\r\n // Serial.println(\"yes, i do enjoy being interrupted\" );\r\n\r\n\r\n" }, { "path": "README", "content": "Repository for Tamagotchi hacking code!\r\n\r\nDirectories:\r\n\r\n\t/demos/ - Discovery board demos\r\n\t/devtools/ - Tamagotchi development tools\r\n\t/die/ - Photos of the Tamagotchi chip/die\r\n\t/dissasembler/ - GeneralPlus binary dissasembler\r\n\t/figure/ - Dumps and code from Tamagotchi figures\r\n\t/figure-simulator/ - Chipkit Uno figure simulator\r\n\t/figure-simulator-discovery/ - STM32F4 Discovery board figure simulator\r\n\t/imageformats/ - Tamagotchi image format converters\r\n\t/IR/ - IR code\r\n\r\nQuestions? Comments? Contributions? \r\n\r\nContact: natashenka@kwartzlab.ca / @natashenka" }, { "path": "RFIDler/tama.py", "content": "import RFIDler\r\nimport sys\r\nimport time\r\n\r\npacket1 = [0xf0, 0, 0x0f, 1, 0, 0x2e, 0x25, 0, 2 , 0x80, 2, 0x7, 8, 0x01, 0x8, 0x1a, 0x1a, 0x1a]\r\n\t\r\npacket2 = [0xf0, int(sys.argv[2]), 5, 1, int(sys.argv[2]), 0x2e, 0x25, 0x1] \r\n\r\n\r\ndef send_byte(b):\r\n\r\n\ti = 0;\r\n\r\n\tresult, data= rfidler.command(\"CLOCKH 125000\")\r\n\ttime.sleep(0.540/1000);\r\n\tresult, data= rfidler.command(\"STOP\")\r\n\ti = 7\r\n\t#print \"send\"\r\n\twhile(i>=0):\r\n\t\tif (1):\r\n\r\n\r\n\t\t\tresult, data= rfidler.command(\"STOP\")\r\n\t\t\ttime.sleep(1.650/1000);\r\n\t\t\tresult, data= rfidler.command(\"CLOCKH 125000\")\r\n\t\t\ttime.sleep(0.150/1000);\r\n\t\telse:\r\n\r\n\t\t\tresult, data= rfidler.command(\"STOP\")\r\n\t\t\ttime.sleep(0.270/1000);\r\n\t\t\tresult, data= rfidler.command(\"CLOCKH 125000\")\r\n\t\t\ttime.sleep(0.150/1000);\r\n\t\t\r\n\t\ti = i - 1\r\n\t\r\n\tresult, data= rfidler.command(\"STOP\");\r\n\ttime.sleep(0.210/1000);\r\n\r\n\r\ndef toBinary(n):\r\n # print n\r\n# print ''.join(str(1 & int(n) >> i) for i in range(8)[::-1])\r\n return ''.join(str(1 & int(n) >> i) for i in range(8)[::-1])\r\n\r\nport= sys.argv[1]\r\nrfidler= RFIDler.RFIDler()\r\nresult, reason= rfidler.connect(port)\r\n\r\nif not result:\r\n\tprint 'Warning - could not open serial port:', reason\r\n\r\nfor i in range(6, 7):\r\n\ts = \"\"\r\n\tn = 0\r\n\tfirst = False\r\n\tfor item in packet1:\r\n\t\tif (first==False):\r\n\t\t\tfirst = True\r\n\t\telse:\r\n\t\t\tn = n + item\r\n\t\ts = s + toBinary(item)\r\n\ts = s + toBinary(n&0xff)\r\n\r\n\r\n\r\n\tresult, data= rfidler.command(\"PWM2 800 0 0 19 19 10 0 0 1 100 20 1 75 20\");\r\n\ttime.sleep(.1)\r\n\tresult, data= rfidler.command(\"RWD2 \" + s);\r\n\r\n\tprint len(s)\r\n\r\n\ts = \"\"\r\n\r\n\r\n\tn = 0\r\n\tfirst = False\r\n\tpacket2[1] = i\r\n\tpacket2[4] = i\r\n\tfor item in packet2:\r\n\t\tif (first==False):\r\n\t\t\tfirst = True\r\n\t\telse:\r\n\t\t\tn = n + item\r\n\t\ts = s + toBinary(item)\r\n\ts = s + toBinary(n&0xff)\r\n\tprint len(s)\r\n\r\n\tprint result\r\n\tprint data\r\n\ttime.sleep(0.1)\r\n\tresult, data= rfidler.command(\"RWD2 \" + s);\r\n\r\n\tprint result\r\n\tprint data\r\n\t\r\n\ttime.sleep(2)\r\n\tprint i\r\n\r\n\r\n\r\n\r\n\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/LCD.c", "content": "//-----------------------------------------------------------------------------\r\n// This code is licensed to you under the terms of the GNU GPL, version 2 or,\r\n// at your option, any later version. See the LICENSE.txt file for the text of\r\n// the license.\r\n//-----------------------------------------------------------------------------\r\n// LCD code\r\n//-----------------------------------------------------------------------------\r\n\r\n#include \"proxmark3.h\"\r\n#include \"apps.h\"\r\n#include \"LCD.h\"\r\n#include \"fonts.h\"\r\n\r\nvoid LCDSend(unsigned int data)\r\n{\r\n\t// 9th bit set for data, clear for command\r\n\twhile ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TXEMPTY) == 0);\t// wait for the transfer to complete\r\n\t// For clarity's sake we pass data with 9th bit clear and commands with 9th\r\n\t// bit set since they're implemented as defines, se we need to invert bit\r\n\tAT91C_BASE_SPI->SPI_TDR = data^0x100;\t\t\t\t\t\t\t// Send the data/command\r\n}\r\n\r\nvoid LCDSetXY(unsigned char x, unsigned char y)\r\n{\r\n\tLCDSend(PPASET);\t\t\t// page start/end ram\r\n\tLCDSend(y);\t\t\t\t\t// Start Page to display to\r\n\tLCDSend(131);\t\t\t\t// End Page to display to\r\n\r\n\tLCDSend(PCASET);\t\t\t// column start/end ram\r\n\tLCDSend(x);\t\t\t\t\t// Start Column to display to\r\n\tLCDSend(131);\t\t\t\t// End Column to display to\r\n}\r\n\r\nvoid LCDSetPixel(unsigned char x, unsigned char y, unsigned char color)\r\n{\r\n\tLCDSetXY(x,y);\t\t\t\t// Set position\r\n\tLCDSend(PRAMWR);\t\t\t// Now write the pixel to the display\r\n\tLCDSend(color);\t\t\t\t// Write the data in the specified Color\r\n}\r\n\r\nvoid LCDFill (unsigned char xs,unsigned char ys,unsigned char width,unsigned char height, unsigned char color)\r\n{\r\n unsigned char i,j;\r\n\r\n for (i=0;i < height;i++)\t// Number of horizontal lines\r\n {\r\n\t\tLCDSetXY(xs,ys+i);\t\t// Goto start of fill area (Top Left)\r\n\t\tLCDSend(PRAMWR);\t\t// Write to display\r\n\r\n\t\tfor (j=0;j < width;j++)\t// pixels per line\r\n\t\t\tLCDSend(color);\r\n }\r\n}\r\n\r\nvoid LCDString (char *lcd_string, const char *font_style,unsigned char x, unsigned char y, unsigned char fcolor, unsigned char bcolor)\r\n{\r\n\tunsigned int i;\r\n\tunsigned char mask=0, px, py, xme, yme, offset;\r\n\tconst char *data;\r\n\r\n\tdata = font_style;\t\t\t// point to the start of the font table\r\n\r\n\txme = *data;\t\t\t\t// get font x width\r\n\tdata++;\r\n\tyme = *data;\t\t\t\t// get font y length\r\n\tdata++;\r\n\toffset = *data;\t\t\t\t// get data bytes per font\r\n\r\n\tdo\r\n\t{\r\n\t\t// point to data in table to be loaded\r\n\t\tdata = (font_style + offset) + (offset * (int)(*lcd_string - 32));\r\n\r\n\t\tfor (i=0;i < yme;i++) {\r\n\t\t\tmask |=0x80;\r\n\r\n\t\t\tfor (px=x; px < (x + xme); px++) {\r\n\t\t\t\tpy= y + i;\r\n\r\n\t\t\t\tif (*data & mask)\tLCDSetPixel (px,py,fcolor);\r\n\t\t\t\telse\t\t\t\tLCDSetPixel (px,py,bcolor);\r\n\r\n\t\t\t\tmask>>=1;\r\n\t\t\t}\r\n\t\t\tdata++;\r\n\t\t}\r\n\t\tx+=xme;\r\n\r\n\t\tlcd_string++;\t\t\t\t\t\t// next character in string\r\n\r\n\t} while(*lcd_string !='\\0');\t\t\t// keep spitting chars out until end of string\r\n}\r\n\r\nvoid LCDReset(void)\r\n{\r\n\tLED_A_ON();\r\n\tSetupSpi(SPI_LCD_MODE);\r\n\tLOW(GPIO_LRST);\r\n\tSpinDelay(100);\r\n\r\n\tHIGH(GPIO_LRST);\r\n\tSpinDelay(100);\r\n\tLED_A_OFF();\r\n}\r\n\r\nvoid LCDInit(void)\r\n{\r\n\tint i;\r\n\r\n\tLCDReset();\r\n\r\n\tLCDSend(PSWRESET);\t\t\t// software reset\r\n\tSpinDelay(100);\r\n\tLCDSend(PSLEEPOUT);\t\t\t// exit sleep mode\r\n\tLCDSend(PBSTRON);\t\t\t// booster on\r\n\tLCDSend(PDISPON);\t\t\t// display on\r\n\tLCDSend(PNORON);\t\t\t// normal on\r\n\tLCDSend(PMADCTL);\t\t\t// rotate display 180 deg\r\n\tLCDSend(0xC0);\r\n\r\n\tLCDSend(PCOLMOD);\t\t\t// color mode\r\n\tLCDSend(0x02);\t\t\t\t// 8bpp color mode\r\n\r\n LCDSend(PSETCON);\t\t\t// set contrast\r\n LCDSend(0xDC);\r\n\r\n\t// clear display\r\n LCDSetXY(0,0);\r\n\tLCDSend(PRAMWR);\t\t\t// Write to display\r\n\ti=LCD_XRES*LCD_YRES;\r\n\twhile(i--) LCDSend(WHITE);\r\n \r\n // test text on different colored backgrounds\r\n\tLCDString(\" The quick brown fox \",\t(char *)&FONT6x8,1,1+8*0,WHITE ,BLACK );\r\n\tLCDString(\" jumped over the \",\t(char *)&FONT6x8,1,1+8*1,BLACK ,WHITE );\r\n\tLCDString(\" lazy dog. \",\t(char *)&FONT6x8,1,1+8*2,YELLOW ,RED );\r\n\tLCDString(\" AaBbCcDdEeFfGgHhIiJj \",\t(char *)&FONT6x8,1,1+8*3,RED ,GREEN );\r\n\tLCDString(\" KkLlMmNnOoPpQqRrSsTt \",\t(char *)&FONT6x8,1,1+8*4,MAGENTA,BLUE );\r\n\tLCDString(\"UuVvWwXxYyZz0123456789\",\t(char *)&FONT6x8,1,1+8*5,BLUE ,YELLOW);\r\n\tLCDString(\"`-=[]_;',./~!@#$%^&*()\",\t(char *)&FONT6x8,1,1+8*6,BLACK ,CYAN );\r\n\tLCDString(\" _+{}|:\\\\\\\"<>? \",(char *)&FONT6x8,1,1+8*7,BLUE ,MAGENTA);\r\n \r\n\t// color bands\r\n\tLCDFill(0, 1+8* 8, 132, 8, BLACK);\r\n\tLCDFill(0, 1+8* 9, 132, 8, WHITE);\r\n\tLCDFill(0, 1+8*10, 132, 8, RED);\r\n\tLCDFill(0, 1+8*11, 132, 8, GREEN);\r\n\tLCDFill(0, 1+8*12, 132, 8, BLUE);\r\n\tLCDFill(0, 1+8*13, 132, 8, YELLOW);\r\n\tLCDFill(0, 1+8*14, 132, 8, CYAN);\r\n\tLCDFill(0, 1+8*15, 132, 8, MAGENTA);\r\n\r\n}\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/LCD.h", "content": "//-----------------------------------------------------------------------------\r\n// This code is licensed to you under the terms of the GNU GPL, version 2 or,\r\n// at your option, any later version. See the LICENSE.txt file for the text of\r\n// the license.\r\n//-----------------------------------------------------------------------------\r\n// LCD code\r\n//-----------------------------------------------------------------------------\r\n\r\n#ifndef __LCD_H\r\n#define __LCD_H\r\n\r\n// The resolution of the LCD\r\n#define LCD_XRES\t132\r\n#define LCD_YRES\t132\r\n\r\n// 8bpp Color Mode - Some basic colors defined for ease of use\r\n// remember 8bpp color = 3xRed, 3xGreen & 2xBlue bits\r\n// organised as RRRGGGBB\r\n\r\n#define BLACK\t\t0x00\r\n#define BLUE\t\t0x03\r\n#define GREEN\t\t0x1C\r\n#define CYAN\t\t0x1F\r\n#define RED\t\t\t0xE0\r\n#define MAGENTA\t\t0xE3\r\n#define YELLOW\t\t0xFC\r\n#define WHITE\t\t0xFF\r\n\r\n// EPSON LCD command set\r\n#define ECASET\t\t0x115\r\n#define EPWRCTR\t\t0x120\r\n#define ENOP\t\t0x125\r\n#define ERAMWR\t\t0x15C\r\n#define ERAMRD\t\t0x15D\r\n#define EPASET\t\t0x175\r\n#define EEPSRRD1\t0x17C\r\n#define EEPSRRD2\t0x17D\r\n#define EVOLCTR\t\t0x181\r\n#define ETMPGRD\t\t0x182\r\n#define ESLPOUT\t\t0x194\r\n#define ESLPIN\t\t0x195\r\n#define EDISNOR\t\t0x1A6\r\n#define EDISINV\t\t0x1A7\r\n#define EPTLIN\t\t0x1A8\r\n#define EPTLOUT\t\t0x1A9\r\n#define EASCSET\t\t0x1AA\r\n#define ESCSTART\t0x1AB\r\n#define EDISOFF\t\t0x1AE\r\n#define EDISON\t\t0x1AF\r\n#define ECOMSCN\t\t0x1BB\r\n#define EDATCTL\t\t0x1BC\r\n#define EDISCTL\t\t0x1CA\r\n#define EEPCOUT\t\t0x1CC\r\n#define EEPCTIN\t\t0x1CD\r\n#define ERGBSET8\t0x1CE\r\n#define EOSCON\t\t0x1D1\r\n#define EOSCOFF\t\t0x1D2\r\n#define EVOLUP\t\t0x1D6\r\n#define EVOLDOWN\t0x1D7\r\n#define ERMWIN\t\t0x1E0\r\n#define ERMWOUT\t\t0x1EE\r\n#define EEPMWR\t\t0x1FC\r\n#define EEPMRD\t\t0x1FD\r\n\r\n// PHILIPS LCD command set\r\n#define PNOP\t\t0x100\r\n#define PSWRESET\t0x101\r\n#define PBSTROFF\t0x102\r\n#define PBSTRON\t\t0x103\r\n#define PRDDIDIF\t0x104\r\n#define PRDDST\t\t0x109\r\n#define PSLEEPIN\t0x110\r\n#define PSLEEPOUT\t0x111\r\n#define PPTLON\t\t0x112\r\n#define PNORON\t\t0x113\r\n#define PINVOFF\t\t0x120\r\n#define PINVON\t\t0x121\r\n#define PDALO\t\t0x122\r\n#define PDAL\t\t0x123\r\n#define PSETCON\t\t0x125\r\n#define PDISPOFF\t0x128\r\n#define PDISPON\t\t0x129\r\n#define PCASET\t\t0x12A\r\n#define PPASET\t\t0x12B\r\n#define PRAMWR\t\t0x12C\r\n#define PRGBSET\t\t0x12D\r\n#define PPTLAR\t\t0x130\r\n#define PVSCRDEF\t0x133\r\n#define PTEOFF\t\t0x134\r\n#define PTEON\t\t0x135\r\n#define PMADCTL\t\t0x136\r\n#define PSEP\t\t0x137\r\n#define PIDMOFF\t\t0x138\r\n#define PIDMON\t\t0x139\r\n#define PCOLMOD\t\t0x13A\r\n#define PSETVOP\t\t0x1B0\r\n#define PBRS\t\t0x1B4\r\n#define PTRS\t\t0x1B6\r\n#define PFINV\t\t0x1B9\r\n#define PDOR\t\t0x1BA\r\n#define PTCDFE\t\t0x1BD\r\n#define PTCVOPE\t\t0x1BF\r\n#define PEC\t\t\t0x1C0\r\n#define PSETMUL\t\t0x1C2\r\n#define PTCVOPAB\t0x1C3\r\n#define PTCVOPCD\t0x1C4\r\n#define PTCDF\t\t0x1C5\r\n#define PDF8C\t\t0x1C6\r\n#define PSETBS\t\t0x1C7\r\n#define PRDTEMP\t\t0x1C8\r\n#define PNLI\t\t0x1C9\r\n#define PRDID1\t\t0x1DA\r\n#define PRDID2\t\t0x1DB\r\n#define PRDID3\t\t0x1DC\r\n#define PSFD\t\t0x1EF\r\n#define PECM\t\t0x1F0\r\n\r\nvoid LCDSend(unsigned int data);\r\nvoid LCDInit(void);\r\nvoid LCDReset(void);\r\nvoid LCDSetXY(unsigned char x, unsigned char y);\r\nvoid LCDSetPixel(unsigned char x, unsigned char y, unsigned char color);\r\nvoid LCDString (char *lcd_string, const char *font_style,unsigned char x, unsigned char y, unsigned char fcolor, unsigned char bcolor);\r\nvoid LCDFill (unsigned char xs,unsigned char ys,unsigned char width,unsigned char height, unsigned char color);\r\n\r\n#endif\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/Makefile", "content": "#-----------------------------------------------------------------------------\r\n# This code is licensed to you under the terms of the GNU GPL, version 2 or,\r\n# at your option, any later version. See the LICENSE.txt file for the text of\r\n# the license.\r\n#-----------------------------------------------------------------------------\r\n# Makefile for armsrc, see ../common/Makefile.common for common settings\r\n#-----------------------------------------------------------------------------\r\n\r\nAPP_INCLUDES = apps.h\r\n\r\n#remove one of the following defines and comment out the relevant line\r\n#in the next section to remove that particular feature from compilation \r\nAPP_CFLAGS\t= -DWITH_LF -DWITH_ISO15693 -DWITH_ISO14443a -DWITH_ISO14443b -DWITH_ICLASS -DWITH_LEGICRF -DWITH_HITAG\r\n#-DWITH_LCD \r\n\r\n#SRC_LCD = fonts.c LCD.c\r\nSRC_LF = lfops.c hitag2.c\r\nSRC_ISO15693 = iso15693.c iso15693tools.c \r\nSRC_ISO14443a = epa.c iso14443a.c mifareutil.c mifarecmd.c mifaresniff.c\r\nSRC_ISO14443b = iso14443.c\r\nSRC_CRAPTO1 = crapto1.c crypto1.c\r\n\r\nTHUMBSRC = start.c \\\r\n\t$(SRC_LCD) \\\r\n\t$(SRC_ISO15693) \\\r\n\t$(SRC_LF) \\\r\n\tappmain.c printf.c \\\r\n\tutil.c \\\r\n\tstring.c \\\r\n\tusb_cdc.c \\\r\n\tcmd.c\r\n\r\n# These are to be compiled in ARM mode\r\nARMSRC = fpgaloader.c \\\r\n\tlegicrf.c \\\r\n\tiso14443crc.c \\\r\n\tcrc16.c \\\r\n\t$(SRC_ISO14443a) \\\r\n\t$(SRC_ISO14443b) \\\r\n\t$(SRC_CRAPTO1) \\\r\n\tlegic_prng.c \\\r\n\ticlass.c \\\r\n\tcrc.c\r\n\r\n# stdint.h provided locally until GCC 4.5 becomes C99 compliant\r\nAPP_CFLAGS += -I.\r\n\r\n# Do not move this inclusion before the definition of {THUMB,ASM,ARM}SRC\r\ninclude ../common/Makefile.common\r\n\r\nOBJS = $(OBJDIR)/osimage.s19 $(OBJDIR)/fpgaimage.s19\r\n\r\nall: $(OBJS)\r\n\r\n$(OBJDIR)/fpga.o: fpga.bit\r\n\t$(OBJCOPY) -O elf32-littlearm -I binary -B arm --redefine-sym _binary____fpga_fpga_bit_start=_binary_fpga_bit_start --redefine-sym _binary____fpga_fpga_bit_end=_binary_fpga_bit_end --prefix-sections=fpga_bit $^ $@\r\n\r\n$(OBJDIR)/fullimage.elf: $(VERSIONOBJ) $(OBJDIR)/fpga.o $(THUMBOBJ) $(ARMOBJ)\r\n\t$(CC) $(LDFLAGS) -Wl,-T,ldscript,-Map,$(patsubst %.elf,%.map,$@) -o $@ $^ $(LIBS)\r\n\r\n$(OBJDIR)/fpgaimage.elf: $(OBJDIR)/fullimage.elf\r\n\t$(OBJCOPY) -F elf32-littlearm --only-section .fpgaimage $^ $@ \r\n\r\n$(OBJDIR)/osimage.elf: $(OBJDIR)/fullimage.elf\r\n\t$(OBJCOPY) -F elf32-littlearm --remove-section .fpgaimage $^ $@\r\n\r\ntarbin: $(OBJS)\r\n\t$(TAR) $(TARFLAGS) ../proxmark3-$(platform)-bin.tar $(OBJS:%=armsrc/%) $(OBJS:%.s19=armsrc/%.elf)\r\n\r\n\r\nclean:\r\n\t$(DELETE) $(OBJDIR)$(PATHSEP)*.o\r\n\t$(DELETE) $(OBJDIR)$(PATHSEP)*.elf\r\n\t$(DELETE) $(OBJDIR)$(PATHSEP)*.s19\r\n\t$(DELETE) $(OBJDIR)$(PATHSEP)*.map\r\n\t$(DELETE) $(OBJDIR)$(PATHSEP)*.d\r\n\t$(DELETE) version.c\r\n\r\n.PHONY: all clean help\r\nhelp:\r\n\t@echo Multi-OS Makefile, you are running on $(DETECTED_OS)\r\n\t@echo Possible targets:\r\n\t@echo +\tall - Make both:\r\n\t@echo +\t$(OBJDIR)/osimage.s19 - The OS image\r\n\t@echo +\t$(OBJDIR)/fpgaimage.s19 - The FPGA image\r\n\t@echo +\tclean - Clean $(OBJDIR)\r\n\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/appmain.c", "content": "//-----------------------------------------------------------------------------\r\n// Jonathan Westhues, Mar 2006\r\n// Edits by Gerhard de Koning Gans, Sep 2007 (##)\r\n//\r\n// This code is licensed to you under the terms of the GNU GPL, version 2 or,\r\n// at your option, any later version. See the LICENSE.txt file for the text of\r\n// the license.\r\n//-----------------------------------------------------------------------------\r\n// The main application code. This is the first thing called after start.c\r\n// executes.\r\n//-----------------------------------------------------------------------------\r\n\r\n#include \"usb_cdc.h\"\r\n#include \"cmd.h\"\r\n\r\n#include \"proxmark3.h\"\r\n#include \"apps.h\"\r\n#include \"util.h\"\r\n#include \"printf.h\"\r\n#include \"string.h\"\r\n\r\n#include \r\n\r\n#include \"legicrf.h\"\r\n#include \r\n\r\n#ifdef WITH_LCD\r\n #include \"LCD.h\"\r\n#endif\r\n\r\n#define abs(x) ( ((x)<0) ? -(x) : (x) )\r\n\r\n//=============================================================================\r\n// A buffer where we can queue things up to be sent through the FPGA, for\r\n// any purpose (fake tag, as reader, whatever). We go MSB first, since that\r\n// is the order in which they go out on the wire.\r\n//=============================================================================\r\n\r\nuint8_t ToSend[512];\r\nint ToSendMax;\r\nstatic int ToSendBit;\r\nstruct common_area common_area __attribute__((section(\".commonarea\")));\r\n\r\nvoid BufferClear(void)\r\n{\r\n\tmemset(BigBuf,0,sizeof(BigBuf));\r\n\tDbprintf(\"Buffer cleared (%i bytes)\",sizeof(BigBuf));\r\n}\r\n\r\nvoid ToSendReset(void)\r\n{\r\n\tToSendMax = -1;\r\n\tToSendBit = 8;\r\n}\r\n\r\nvoid ToSendStuffBit(int b)\r\n{\r\n\tif(ToSendBit >= 8) {\r\n\t\tToSendMax++;\r\n\t\tToSend[ToSendMax] = 0;\r\n\t\tToSendBit = 0;\r\n\t}\r\n\r\n\tif(b) {\r\n\t\tToSend[ToSendMax] |= (1 << (7 - ToSendBit));\r\n\t}\r\n\r\n\tToSendBit++;\r\n\r\n\tif(ToSendBit >= sizeof(ToSend)) {\r\n\t\tToSendBit = 0;\r\n\t\tDbpString(\"ToSendStuffBit overflowed!\");\r\n\t}\r\n}\r\n\r\n//=============================================================================\r\n// Debug print functions, to go out over USB, to the usual PC-side client.\r\n//=============================================================================\r\n\r\nvoid DbpString(char *str)\r\n{\r\n byte_t len = strlen(str);\r\n cmd_send(CMD_DEBUG_PRINT_STRING,len,0,0,(byte_t*)str,len);\r\n//\t/* this holds up stuff unless we're connected to usb */\r\n//\tif (!UsbConnected())\r\n//\t\treturn;\r\n//\r\n//\tUsbCommand c;\r\n//\tc.cmd = CMD_DEBUG_PRINT_STRING;\r\n//\tc.arg[0] = strlen(str);\r\n//\tif(c.arg[0] > sizeof(c.d.asBytes)) {\r\n//\t\tc.arg[0] = sizeof(c.d.asBytes);\r\n//\t}\r\n//\tmemcpy(c.d.asBytes, str, c.arg[0]);\r\n//\r\n//\tUsbSendPacket((uint8_t *)&c, sizeof(c));\r\n//\t// TODO fix USB so stupid things like this aren't req'd\r\n//\tSpinDelay(50);\r\n}\r\n\r\n#if 0\r\nvoid DbpIntegers(int x1, int x2, int x3)\r\n{\r\n cmd_send(CMD_DEBUG_PRINT_INTEGERS,x1,x2,x3,0,0);\r\n//\t/* this holds up stuff unless we're connected to usb */\r\n//\tif (!UsbConnected())\r\n//\t\treturn;\r\n//\r\n//\tUsbCommand c;\r\n//\tc.cmd = CMD_DEBUG_PRINT_INTEGERS;\r\n//\tc.arg[0] = x1;\r\n//\tc.arg[1] = x2;\r\n//\tc.arg[2] = x3;\r\n//\r\n//\tUsbSendPacket((uint8_t *)&c, sizeof(c));\r\n//\t// XXX\r\n//\tSpinDelay(50);\r\n}\r\n#endif\r\n\r\nvoid Dbprintf(const char *fmt, ...) {\r\n// should probably limit size here; oh well, let's just use a big buffer\r\n\tchar output_string[128];\r\n\tva_list ap;\r\n\r\n\tva_start(ap, fmt);\r\n\tkvsprintf(fmt, output_string, 10, ap);\r\n\tva_end(ap);\r\n\r\n\tDbpString(output_string);\r\n}\r\n\r\n// prints HEX & ASCII\r\nvoid Dbhexdump(int len, uint8_t *d, bool bAsci) {\r\n\tint l=0,i;\r\n\tchar ascii[9];\r\n \r\n\twhile (len>0) {\r\n\t\tif (len>8) l=8;\r\n\t\telse l=len;\r\n\t\t\r\n\t\tmemcpy(ascii,d,l);\r\n\t\tascii[l]=0;\r\n\t\t\r\n\t\t// filter safe ascii\r\n\t\tfor (i=0;i126) ascii[i]='.';\r\n \r\n\t\tif (bAsci) {\r\n\t\t\tDbprintf(\"%-8s %*D\",ascii,l,d,\" \");\r\n\t\t} else {\r\n\t\t\tDbprintf(\"%*D\",l,d,\" \");\r\n\t\t}\r\n \r\n\t\tlen-=8;\r\n\t\td+=8;\t\t\r\n\t}\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// Read an ADC channel and block till it completes, then return the result\r\n// in ADC units (0 to 1023). Also a routine to average 32 samples and\r\n// return that.\r\n//-----------------------------------------------------------------------------\r\nstatic int ReadAdc(int ch)\r\n{\r\n\tuint32_t d;\r\n\r\n\tAT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;\r\n\tAT91C_BASE_ADC->ADC_MR =\r\n\t\tADC_MODE_PRESCALE(32) |\r\n\t\tADC_MODE_STARTUP_TIME(16) |\r\n\t\tADC_MODE_SAMPLE_HOLD_TIME(8);\r\n\tAT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ch);\r\n\r\n\tAT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;\r\n\twhile(!(AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ch)))\r\n\t\t;\r\n\td = AT91C_BASE_ADC->ADC_CDR[ch];\r\n\r\n\treturn d;\r\n}\r\n\r\nint AvgAdc(int ch) // was static - merlok\r\n{\r\n\tint i;\r\n\tint a = 0;\r\n\r\n\tfor(i = 0; i < 32; i++) {\r\n\t\ta += ReadAdc(ch);\r\n\t}\r\n\r\n\treturn (a + 15) >> 5;\r\n}\r\n\r\nvoid MeasureAntennaTuning(void)\r\n{\r\n\tuint8_t *dest = (uint8_t *)BigBuf+FREE_BUFFER_OFFSET;\r\n\tint i, adcval = 0, peak = 0, peakv = 0, peakf = 0; //ptr = 0 \r\n\tint vLf125 = 0, vLf134 = 0, vHf = 0;\t// in mV\r\n\r\n//\tUsbCommand c;\r\n\r\n LED_B_ON();\r\n\tDbpString(\"Measuring antenna characteristics, please wait...\");\r\n\tmemset(dest,0,sizeof(FREE_BUFFER_SIZE));\r\n\r\n/*\r\n * Sweeps the useful LF range of the proxmark from\r\n * 46.8kHz (divisor=255) to 600kHz (divisor=19) and\r\n * read the voltage in the antenna, the result left\r\n * in the buffer is a graph which should clearly show\r\n * the resonating frequency of your LF antenna\r\n * ( hopefully around 95 if it is tuned to 125kHz!)\r\n */\r\n \r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r\n\tfor (i=255; i>19; i--) {\r\n WDT_HIT();\r\n\t\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, i);\r\n\t\tSpinDelay(20);\r\n\t\t// Vref = 3.3V, and a 10000:240 voltage divider on the input\r\n\t\t// can measure voltages up to 137500 mV\r\n\t\tadcval = ((137500 * AvgAdc(ADC_CHAN_LF)) >> 10);\r\n\t\tif (i==95) \tvLf125 = adcval; // voltage at 125Khz\r\n\t\tif (i==89) \tvLf134 = adcval; // voltage at 134Khz\r\n\r\n\t\tdest[i] = adcval>>8; // scale int to fit in byte for graphing purposes\r\n\t\tif(dest[i] > peak) {\r\n\t\t\tpeakv = adcval;\r\n\t\t\tpeak = dest[i];\r\n\t\t\tpeakf = i;\r\n\t\t\t//ptr = i;\r\n\t\t}\r\n\t}\r\n\r\n LED_A_ON();\r\n\t// Let the FPGA drive the high-frequency antenna around 13.56 MHz.\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR);\r\n\tSpinDelay(20);\r\n\t// Vref = 3300mV, and an 10:1 voltage divider on the input\r\n\t// can measure voltages up to 33000 mV\r\n\tvHf = (33000 * AvgAdc(ADC_CHAN_HF)) >> 10;\r\n\r\n//\tc.cmd = CMD_MEASURED_ANTENNA_TUNING;\r\n//\tc.arg[0] = (vLf125 << 0) | (vLf134 << 16);\r\n//\tc.arg[1] = vHf;\r\n//\tc.arg[2] = peakf | (peakv << 16);\r\n\r\n DbpString(\"Measuring complete, sending report back to host\");\r\n cmd_send(CMD_MEASURED_ANTENNA_TUNING,vLf125|(vLf134<<16),vHf,peakf|(peakv<<16),0,0);\r\n//\tUsbSendPacket((uint8_t *)&c, sizeof(c));\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n LED_A_OFF();\r\n LED_B_OFF();\r\n return;\r\n}\r\n\r\nvoid MeasureAntennaTuningHf(void)\r\n{\r\n\tint vHf = 0;\t// in mV\r\n\r\n\tDbpString(\"Measuring HF antenna, press button to exit\");\r\n\r\n\tfor (;;) {\r\n\t\t// Let the FPGA drive the high-frequency antenna around 13.56 MHz.\r\n\t\tFpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR);\r\n\t\tSpinDelay(20);\r\n\t\t// Vref = 3300mV, and an 10:1 voltage divider on the input\r\n\t\t// can measure voltages up to 33000 mV\r\n\t\tvHf = (33000 * AvgAdc(ADC_CHAN_HF)) >> 10;\r\n\r\n\t\tDbprintf(\"%d mV\",vHf);\r\n\t\tif (BUTTON_PRESS()) break;\r\n\t}\r\n\tDbpString(\"cancelled\");\r\n}\r\n\r\n\r\nvoid SimulateTagHfListen(void)\r\n{\r\n\tuint8_t *dest = (uint8_t *)BigBuf+FREE_BUFFER_OFFSET;\r\n\tuint8_t v = 0;\r\n\tint i;\r\n\tint p = 0;\r\n\r\n\t// We're using this mode just so that I can test it out; the simulated\r\n\t// tag mode would work just as well and be simpler.\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ | FPGA_HF_READER_RX_XCORR_SNOOP);\r\n\r\n\t// We need to listen to the high-frequency, peak-detected path.\r\n\tSetAdcMuxFor(GPIO_MUXSEL_HIPKD);\r\n\r\n\tFpgaSetupSsc();\r\n\r\n\ti = 0;\r\n\tfor(;;) {\r\n\t\tif(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r\n\t\t\tAT91C_BASE_SSC->SSC_THR = 0xff;\r\n\t\t}\r\n\t\tif(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r\n\t\t\tuint8_t r = (uint8_t)AT91C_BASE_SSC->SSC_RHR;\r\n\r\n\t\t\tv <<= 1;\r\n\t\t\tif(r & 1) {\r\n\t\t\t\tv |= 1;\r\n\t\t\t}\r\n\t\t\tp++;\r\n\r\n\t\t\tif(p >= 8) {\r\n\t\t\t\tdest[i] = v;\r\n\t\t\t\tv = 0;\r\n\t\t\t\tp = 0;\r\n\t\t\t\ti++;\r\n\r\n\t\t\t\tif(i >= FREE_BUFFER_SIZE) {\r\n\t\t\t\t\tbreak;\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t}\r\n\t}\r\n\tDbpString(\"simulate tag (now type bitsamples)\");\r\n}\r\n\r\nvoid ReadMem(int addr)\r\n{\r\n\tconst uint8_t *data = ((uint8_t *)addr);\r\n\r\n\tDbprintf(\"%x: %02x %02x %02x %02x %02x %02x %02x %02x\",\r\n\t\taddr, data[0], data[1], data[2], data[3], data[4], data[5], data[6], data[7]);\r\n}\r\n\r\n/* osimage version information is linked in */\r\nextern struct version_information version_information;\r\n/* bootrom version information is pointed to from _bootphase1_version_pointer */\r\nextern char *_bootphase1_version_pointer, _flash_start, _flash_end;\r\nvoid SendVersion(void)\r\n{\r\n\tchar temp[48]; /* Limited data payload in USB packets */\r\n\tDbpString(\"Prox/RFID mark3 RFID instrument\");\r\n\r\n\t/* Try to find the bootrom version information. Expect to find a pointer at\r\n\t * symbol _bootphase1_version_pointer, perform slight sanity checks on the\r\n\t * pointer, then use it.\r\n\t */\r\n\tchar *bootrom_version = *(char**)&_bootphase1_version_pointer;\r\n\tif( bootrom_version < &_flash_start || bootrom_version >= &_flash_end ) {\r\n\t\tDbpString(\"bootrom version information appears invalid\");\r\n\t} else {\r\n\t\tFormatVersionInformation(temp, sizeof(temp), \"bootrom: \", bootrom_version);\r\n\t\tDbpString(temp);\r\n\t}\r\n\r\n\tFormatVersionInformation(temp, sizeof(temp), \"os: \", &version_information);\r\n\tDbpString(temp);\r\n\r\n\tFpgaGatherVersion(temp, sizeof(temp));\r\n\tDbpString(temp);\r\n}\r\n\r\n#ifdef WITH_LF\r\n// samy's sniff and repeat routine\r\nvoid SamyRun()\r\n{\r\n\tDbpString(\"Stand-alone mode! No PC necessary.\");\r\n\r\n\t// 3 possible options? no just 2 for now\r\n#define OPTS 2\r\n\r\n\tint high[OPTS], low[OPTS];\r\n\r\n\t// Oooh pretty -- notify user we're in elite samy mode now\r\n\tLED(LED_RED,\t200);\r\n\tLED(LED_ORANGE, 200);\r\n\tLED(LED_GREEN,\t200);\r\n\tLED(LED_ORANGE, 200);\r\n\tLED(LED_RED,\t200);\r\n\tLED(LED_ORANGE, 200);\r\n\tLED(LED_GREEN,\t200);\r\n\tLED(LED_ORANGE, 200);\r\n\tLED(LED_RED,\t200);\r\n\r\n\tint selected = 0;\r\n\tint playing = 0;\r\n\r\n\t// Turn on selected LED\r\n\tLED(selected + 1, 0);\r\n\r\n\tfor (;;)\r\n\t{\r\n//\t\tUsbPoll(FALSE);\r\n\t\tusb_poll();\r\n WDT_HIT();\r\n\r\n\t\t// Was our button held down or pressed?\r\n\t\tint button_pressed = BUTTON_HELD(1000);\r\n\t\tSpinDelay(300);\r\n\r\n\t\t// Button was held for a second, begin recording\r\n\t\tif (button_pressed > 0)\r\n\t\t{\r\n\t\t\tLEDsoff();\r\n\t\t\tLED(selected + 1, 0);\r\n\t\t\tLED(LED_RED2, 0);\r\n\r\n\t\t\t// record\r\n\t\t\tDbpString(\"Starting recording\");\r\n\r\n\t\t\t// wait for button to be released\r\n\t\t\twhile(BUTTON_PRESS())\r\n\t\t\t\tWDT_HIT();\r\n\r\n\t\t\t/* need this delay to prevent catching some weird data */\r\n\t\t\tSpinDelay(500);\r\n\r\n\t\t\tCmdHIDdemodFSK(1, &high[selected], &low[selected], 0);\r\n\t\t\tDbprintf(\"Recorded %x %x %x\", selected, high[selected], low[selected]);\r\n\r\n\t\t\tLEDsoff();\r\n\t\t\tLED(selected + 1, 0);\r\n\t\t\t// Finished recording\r\n\r\n\t\t\t// If we were previously playing, set playing off\r\n\t\t\t// so next button push begins playing what we recorded\r\n\t\t\tplaying = 0;\r\n\t\t}\r\n\r\n\t\t// Change where to record (or begin playing)\r\n\t\telse if (button_pressed)\r\n\t\t{\r\n\t\t\t// Next option if we were previously playing\r\n\t\t\tif (playing)\r\n\t\t\t\tselected = (selected + 1) % OPTS;\r\n\t\t\tplaying = !playing;\r\n\r\n\t\t\tLEDsoff();\r\n\t\t\tLED(selected + 1, 0);\r\n\r\n\t\t\t// Begin transmitting\r\n\t\t\tif (playing)\r\n\t\t\t{\r\n\t\t\t\tLED(LED_GREEN, 0);\r\n\t\t\t\tDbpString(\"Playing\");\r\n\t\t\t\t// wait for button to be released\r\n\t\t\t\twhile(BUTTON_PRESS())\r\n\t\t\t\t\tWDT_HIT();\r\n\t\t\t\tDbprintf(\"%x %x %x\", selected, high[selected], low[selected]);\r\n\t\t\t\tCmdHIDsimTAG(high[selected], low[selected], 0);\r\n\t\t\t\tDbpString(\"Done playing\");\r\n\t\t\t\tif (BUTTON_HELD(1000) > 0)\r\n\t\t\t\t\t{\r\n\t\t\t\t\tDbpString(\"Exiting\");\r\n\t\t\t\t\tLEDsoff();\r\n\t\t\t\t\treturn;\r\n\t\t\t\t\t}\r\n\r\n\t\t\t\t/* We pressed a button so ignore it here with a delay */\r\n\t\t\t\tSpinDelay(300);\r\n\r\n\t\t\t\t// when done, we're done playing, move to next option\r\n\t\t\t\tselected = (selected + 1) % OPTS;\r\n\t\t\t\tplaying = !playing;\r\n\t\t\t\tLEDsoff();\r\n\t\t\t\tLED(selected + 1, 0);\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t\twhile(BUTTON_PRESS())\r\n\t\t\t\t\tWDT_HIT();\r\n\t\t}\r\n\t}\r\n}\r\n#endif\r\n\r\n/*\r\nOBJECTIVE\r\nListen and detect an external reader. Determine the best location\r\nfor the antenna.\r\n\r\nINSTRUCTIONS:\r\nInside the ListenReaderField() function, there is two mode.\r\nBy default, when you call the function, you will enter mode 1.\r\nIf you press the PM3 button one time, you will enter mode 2.\r\nIf you press the PM3 button a second time, you will exit the function.\r\n\r\nDESCRIPTION OF MODE 1:\r\nThis mode just listens for an external reader field and lights up green\r\nfor HF and/or red for LF. This is the original mode of the detectreader\r\nfunction.\r\n\r\nDESCRIPTION OF MODE 2:\r\nThis mode will visually represent, using the LEDs, the actual strength of the\r\ncurrent compared to the maximum current detected. Basically, once you know\r\nwhat kind of external reader is present, it will help you spot the best location to place\r\nyour antenna. You will probably not get some good results if there is a LF and a HF reader\r\nat the same place! :-)\r\n\r\nLIGHT SCHEME USED:\r\n*/\r\nstatic const char LIGHT_SCHEME[] = {\r\n\t\t0x0, /* ---- | No field detected */\r\n\t\t0x1, /* X--- | 14% of maximum current detected */\r\n\t\t0x2, /* -X-- | 29% of maximum current detected */\r\n\t\t0x4, /* --X- | 43% of maximum current detected */\r\n\t\t0x8, /* ---X | 57% of maximum current detected */\r\n\t\t0xC, /* --XX | 71% of maximum current detected */\r\n\t\t0xE, /* -XXX | 86% of maximum current detected */\r\n\t\t0xF, /* XXXX | 100% of maximum current detected */\r\n};\r\nstatic const int LIGHT_LEN = sizeof(LIGHT_SCHEME)/sizeof(LIGHT_SCHEME[0]);\r\n\r\nvoid ListenReaderField(int limit)\r\n{\r\n\tint lf_av, lf_av_new, lf_baseline= 0, lf_count= 0, lf_max;\r\n\tint hf_av, hf_av_new, hf_baseline= 0, hf_count= 0, hf_max;\r\n\tint mode=1, display_val, display_max, i;\r\n\r\n#define LF_ONLY\t\t1\r\n#define HF_ONLY\t\t2\r\n\r\n\tLEDsoff();\r\n\r\n\tlf_av=lf_max=ReadAdc(ADC_CHAN_LF);\r\n\r\n\tif(limit != HF_ONLY) {\r\n\t\tDbprintf(\"LF 125/134 Baseline: %d\", lf_av);\r\n\t\tlf_baseline = lf_av;\r\n\t}\r\n\r\n\thf_av=hf_max=ReadAdc(ADC_CHAN_HF);\r\n\r\n\tif (limit != LF_ONLY) {\r\n\t\tDbprintf(\"HF 13.56 Baseline: %d\", hf_av);\r\n\t\thf_baseline = hf_av;\r\n\t}\r\n\r\n\tfor(;;) {\r\n\t\tif (BUTTON_PRESS()) {\r\n\t\t\tSpinDelay(500);\r\n\t\t\tswitch (mode) {\r\n\t\t\t\tcase 1:\r\n\t\t\t\t\tmode=2;\r\n\t\t\t\t\tDbpString(\"Signal Strength Mode\");\r\n\t\t\t\t\tbreak;\r\n\t\t\t\tcase 2:\r\n\t\t\t\tdefault:\r\n\t\t\t\t\tDbpString(\"Stopped\");\r\n\t\t\t\t\tLEDsoff();\r\n\t\t\t\t\treturn;\r\n\t\t\t\t\tbreak;\r\n\t\t\t}\r\n\t\t}\r\n\t\tWDT_HIT();\r\n\r\n\t\tif (limit != HF_ONLY) {\r\n\t\t\tif(mode==1) {\r\n\t\t\t\tif (abs(lf_av - lf_baseline) > 10) LED_D_ON();\r\n\t\t\t\telse LED_D_OFF();\r\n\t\t\t}\r\n\r\n\t\t\t++lf_count;\r\n\t\t\tlf_av_new= ReadAdc(ADC_CHAN_LF);\r\n\t\t\t// see if there's a significant change\r\n\t\t\tif(abs(lf_av - lf_av_new) > 10) {\r\n\t\t\t\tDbprintf(\"LF 125/134 Field Change: %x %x %x\", lf_av, lf_av_new, lf_count);\r\n\t\t\t\tlf_av = lf_av_new;\r\n\t\t\t\tif (lf_av > lf_max)\r\n\t\t\t\t\tlf_max = lf_av;\r\n\t\t\t\tlf_count= 0;\r\n\t\t\t}\r\n\t\t}\r\n\r\n\t\tif (limit != LF_ONLY) {\r\n\t\t\tif (mode == 1){\r\n\t\t\t\tif (abs(hf_av - hf_baseline) > 10) LED_B_ON();\r\n\t\t\t\telse LED_B_OFF();\r\n\t\t\t}\r\n\r\n\t\t\t++hf_count;\r\n\t\t\thf_av_new= ReadAdc(ADC_CHAN_HF);\r\n\t\t\t// see if there's a significant change\r\n\t\t\tif(abs(hf_av - hf_av_new) > 10) {\r\n\t\t\t\tDbprintf(\"HF 13.56 Field Change: %x %x %x\", hf_av, hf_av_new, hf_count);\r\n\t\t\t\thf_av = hf_av_new;\r\n\t\t\t\tif (hf_av > hf_max)\r\n\t\t\t\t\thf_max = hf_av;\r\n\t\t\t\thf_count= 0;\r\n\t\t\t}\r\n\t\t}\r\n\r\n\t\tif(mode == 2) {\r\n\t\t\tif (limit == LF_ONLY) {\r\n\t\t\t\tdisplay_val = lf_av;\r\n\t\t\t\tdisplay_max = lf_max;\r\n\t\t\t} else if (limit == HF_ONLY) {\r\n\t\t\t\tdisplay_val = hf_av;\r\n\t\t\t\tdisplay_max = hf_max;\r\n\t\t\t} else { /* Pick one at random */\r\n\t\t\t\tif( (hf_max - hf_baseline) > (lf_max - lf_baseline) ) {\r\n\t\t\t\t\tdisplay_val = hf_av;\r\n\t\t\t\t\tdisplay_max = hf_max;\r\n\t\t\t\t} else {\r\n\t\t\t\t\tdisplay_val = lf_av;\r\n\t\t\t\t\tdisplay_max = lf_max;\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\tfor (i=0; i= ((display_max/LIGHT_LEN)*i) && display_val <= ((display_max/LIGHT_LEN)*(i+1))) {\r\n\t\t\t\t\tif (LIGHT_SCHEME[i] & 0x1) LED_C_ON(); else LED_C_OFF();\r\n\t\t\t\t\tif (LIGHT_SCHEME[i] & 0x2) LED_A_ON(); else LED_A_OFF();\r\n\t\t\t\t\tif (LIGHT_SCHEME[i] & 0x4) LED_B_ON(); else LED_B_OFF();\r\n\t\t\t\t\tif (LIGHT_SCHEME[i] & 0x8) LED_D_ON(); else LED_D_OFF();\r\n\t\t\t\t\tbreak;\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t}\r\n\t}\r\n}\r\n\r\nvoid UsbPacketReceived(uint8_t *packet, int len)\r\n{\r\n\tUsbCommand *c = (UsbCommand *)packet;\r\n\r\n// Dbprintf(\"received %d bytes, with command: 0x%04x and args: %d %d %d\",len,c->cmd,c->arg[0],c->arg[1],c->arg[2]);\r\n \r\n\tswitch(c->cmd) {\r\n#ifdef WITH_LF\r\n\t\tcase CMD_ACQUIRE_RAW_ADC_SAMPLES_125K:\r\n\t\t\tAcquireRawAdcSamples125k(c->arg[0]);\r\n\t\t\tcmd_send(CMD_ACK,0,0,0,0,0);\r\n\t\t\tbreak;\r\n\t\tcase CMD_MOD_THEN_ACQUIRE_RAW_ADC_SAMPLES_125K:\r\n\t\t\tModThenAcquireRawAdcSamples125k(c->arg[0],c->arg[1],c->arg[2],c->d.asBytes);\r\n\t\t\tbreak;\r\n\t\tcase CMD_HID_DEMOD_FSK:\r\n\t\t\tCmdHIDdemodFSK(0, 0, 0, 1);\t\t\t\t\t// Demodulate HID tag\r\n\t\t\tbreak;\r\n\t\tcase CMD_HID_SIM_TAG:\r\n\t\t\tCmdHIDsimTAG(c->arg[0], c->arg[1], 1);\t\t\t\t\t// Simulate HID tag by ID\r\n\t\t\tbreak;\r\n case CMD_HID_CLONE_TAG: // Clone HID tag by ID to T55x7\r\n\t\t\tCopyHIDtoT55x7(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes[0]);\r\n\t\t\tbreak;\r\n\t\tcase CMD_EM410X_WRITE_TAG:\r\n\t\t\tWriteEM410x(c->arg[0], c->arg[1], c->arg[2]);\r\n\t\t\tbreak;\r\n\t\tcase CMD_READ_TI_TYPE:\r\n\t\t\tReadTItag();\r\n\t\t\tbreak;\r\n\t\tcase CMD_WRITE_TI_TYPE:\r\n\t\t\tWriteTItag(c->arg[0],c->arg[1],c->arg[2]);\r\n\t\t\tbreak;\r\n\t\tcase CMD_SIMULATE_TAG_125K:\r\n\t\t\tLED_A_ON();\r\n\t\t\tSimulateTagLowFrequency(c->arg[0], c->arg[1], 1);\r\n\t\t\tLED_A_OFF();\r\n\t\t\tbreak;\r\n\t\tcase CMD_LF_SIMULATE_BIDIR:\r\n\t\t\tSimulateTagLowFrequencyBidir(c->arg[0], c->arg[1]);\r\n\t\t\tbreak;\r\n\t\tcase CMD_INDALA_CLONE_TAG:\t\t\t\t\t// Clone Indala 64-bit tag by UID to T55x7\r\n\t\t\tCopyIndala64toT55x7(c->arg[0], c->arg[1]);\t\t\t\t\t\r\n\t\t\tbreak;\r\n\t\tcase CMD_INDALA_CLONE_TAG_L:\t\t\t\t\t// Clone Indala 224-bit tag by UID to T55x7\r\n\t\t\tCopyIndala224toT55x7(c->d.asDwords[0], c->d.asDwords[1], c->d.asDwords[2], c->d.asDwords[3], c->d.asDwords[4], c->d.asDwords[5], c->d.asDwords[6]);\r\n\t\t\tbreak;\r\n\t\tcase CMD_T55XX_READ_BLOCK:\r\n\t\t\tT55xxReadBlock(c->arg[1], c->arg[2],c->d.asBytes[0]);\r\n\t\t\tbreak;\r\n\t\tcase CMD_T55XX_WRITE_BLOCK:\r\n\t\t\tT55xxWriteBlock(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes[0]);\r\n\t\t\tbreak;\r\n\t\tcase CMD_T55XX_READ_TRACE: // Clone HID tag by ID to T55x7\r\n\t\t\tT55xxReadTrace();\r\n\t\t\tbreak;\r\n\t\tcase CMD_PCF7931_READ: // Read PCF7931 tag\r\n\t\t\tReadPCF7931();\r\n\t\t\tcmd_send(CMD_ACK,0,0,0,0,0);\r\n// \tUsbSendPacket((uint8_t*)&ack, sizeof(ack));\r\n\t\t\tbreak;\r\n\t\tcase CMD_EM4X_READ_WORD:\r\n\t\t\tEM4xReadWord(c->arg[1], c->arg[2],c->d.asBytes[0]);\r\n\t\t\tbreak;\r\n\t\tcase CMD_EM4X_WRITE_WORD:\r\n\t\t\tEM4xWriteWord(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes[0]);\r\n\t\t\tbreak;\r\n#endif\r\n\r\n#ifdef WITH_HITAG\r\n\t\tcase CMD_SNOOP_HITAG: // Eavesdrop Hitag tag, args = type\r\n\t\t\tSnoopHitag(c->arg[0]);\r\n\t\t\tbreak;\r\n\t\tcase CMD_SIMULATE_HITAG: // Simulate Hitag tag, args = memory content\r\n\t\t\tSimulateHitagTag((bool)c->arg[0],(byte_t*)c->d.asBytes);\r\n\t\t\tbreak;\r\n\t\tcase CMD_READER_HITAG: // Reader for Hitag tags, args = type and function\r\n\t\t\tReaderHitag((hitag_function)c->arg[0],(hitag_data*)c->d.asBytes);\r\n\t\t\tbreak;\r\n#endif\r\n \r\n#ifdef WITH_ISO15693\r\n\t\tcase CMD_ACQUIRE_RAW_ADC_SAMPLES_ISO_15693:\r\n\t\t\tAcquireRawAdcSamplesIso15693();\r\n\t\t\tbreak;\r\n\t\tcase CMD_RECORD_RAW_ADC_SAMPLES_ISO_15693:\r\n\t\t\tRecordRawAdcSamplesIso15693();\r\n\t\t\tbreak;\r\n\t\t\t\r\n\t\tcase CMD_ISO_15693_COMMAND:\r\n\t\t\tDirectTag15693Command(c->arg[0],c->arg[1],c->arg[2],c->d.asBytes);\r\n\t\t\tbreak;\r\n\t\t\t\t\t\r\n\t\tcase CMD_ISO_15693_FIND_AFI:\r\n\t\t\tBruteforceIso15693Afi(c->arg[0]);\r\n\t\t\tbreak;\t\r\n\t\t\t\r\n\t\tcase CMD_ISO_15693_DEBUG:\r\n\t\t\tSetDebugIso15693(c->arg[0]);\r\n\t\t\tbreak;\r\n\r\n\t\tcase CMD_READER_ISO_15693:\r\n\t\t\tReaderIso15693(c->arg[0]);\r\n\t\t\tbreak;\r\n\t\tcase CMD_SIMTAG_ISO_15693:\r\n\t\t\tSimTagIso15693(c->arg[0]);\r\n\t\t\tbreak;\r\n#endif\r\n\r\n#ifdef WITH_LEGICRF\r\n\t\tcase CMD_SIMULATE_TAG_LEGIC_RF:\r\n\t\t\tLegicRfSimulate(c->arg[0], c->arg[1], c->arg[2]);\r\n\t\t\tbreak;\r\n\r\n\t\tcase CMD_WRITER_LEGIC_RF:\r\n\t\t\tLegicRfWriter(c->arg[1], c->arg[0]);\r\n\t\t\tbreak;\r\n\r\n\t\tcase CMD_READER_LEGIC_RF:\r\n\t\t\tLegicRfReader(c->arg[0], c->arg[1]);\r\n\t\t\tbreak;\r\n#endif\r\n\r\n#ifdef WITH_ISO14443b\r\n\t\tcase CMD_ACQUIRE_RAW_ADC_SAMPLES_ISO_14443:\r\n\t\t\tAcquireRawAdcSamplesIso14443(c->arg[0]);\r\n\t\t\tbreak;\r\n\t\tcase CMD_READ_SRI512_TAG:\r\n\t\t\tReadSRI512Iso14443(c->arg[0]);\r\n\t\t\tbreak;\r\n\t\tcase CMD_READ_SRIX4K_TAG:\r\n\t\t\tReadSRIX4KIso14443(c->arg[0]);\r\n\t\t\tbreak;\r\n\t\tcase CMD_SNOOP_ISO_14443:\r\n\t\t\tSnoopIso14443();\r\n\t\t\tbreak;\r\n\t\tcase CMD_SIMULATE_TAG_ISO_14443:\r\n\t\t\tSimulateIso14443Tag();\r\n\t\t\tbreak;\r\n#endif\r\n\r\n#ifdef WITH_ISO14443a\r\n\t\tcase CMD_SNOOP_ISO_14443a:\r\n\t\t\tSnoopIso14443a(c->arg[0]);\r\n\t\t\tbreak;\r\n\t\tcase CMD_READER_ISO_14443a:\r\n\t\t\tReaderIso14443a(c);\r\n\t\t\tbreak;\r\n\t\tcase CMD_SIMULATE_TAG_ISO_14443a:\r\n\t\t\tSimulateIso14443aTag(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes); // ## Simulate iso14443a tag - pass tag type & UID\r\n\t\t\tbreak;\r\n\t\tcase CMD_EPA_PACE_COLLECT_NONCE:\r\n\t\t\tEPA_PACE_Collect_Nonce(c);\r\n\t\t\tbreak;\r\n\t\t\t\r\n\t\tcase CMD_READER_MIFARE:\r\n ReaderMifare(c->arg[0]);\r\n\t\t\tbreak;\r\n\t\tcase CMD_MIFARE_READBL:\r\n\t\t\tMifareReadBlock(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes);\r\n\t\t\tbreak;\r\n\t\tcase CMD_MIFARE_READSC:\r\n\t\t\tMifareReadSector(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes);\r\n\t\t\tbreak;\r\n\t\tcase CMD_MIFARE_WRITEBL:\r\n\t\t\tMifareWriteBlock(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes);\r\n\t\t\tbreak;\r\n\t\tcase CMD_MIFARE_NESTED:\r\n\t\t\tMifareNested(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes);\r\n\t\t\tbreak;\r\n\t\tcase CMD_MIFARE_CHKKEYS:\r\n\t\t\tMifareChkKeys(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes);\r\n\t\t\tbreak;\r\n\t\tcase CMD_SIMULATE_MIFARE_CARD:\r\n\t\t\tMifare1ksim(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes);\r\n\t\t\tbreak;\r\n\t\t\r\n\t\t// emulator\r\n\t\tcase CMD_MIFARE_SET_DBGMODE:\r\n\t\t\tMifareSetDbgLvl(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes);\r\n\t\t\tbreak;\r\n\t\tcase CMD_MIFARE_EML_MEMCLR:\r\n\t\t\tMifareEMemClr(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes);\r\n\t\t\tbreak;\r\n\t\tcase CMD_MIFARE_EML_MEMSET:\r\n\t\t\tMifareEMemSet(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes);\r\n\t\t\tbreak;\r\n\t\tcase CMD_MIFARE_EML_MEMGET:\r\n\t\t\tMifareEMemGet(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes);\r\n\t\t\tbreak;\r\n\t\tcase CMD_MIFARE_EML_CARDLOAD:\r\n\t\t\tMifareECardLoad(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes);\r\n\t\t\tbreak;\r\n\t\t\t\r\n\t\t// Work with \"magic Chinese\" card\r\n\t\tcase CMD_MIFARE_EML_CSETBLOCK:\r\n\t\t\tMifareCSetBlock(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes);\r\n\t\t\tbreak;\r\n\t\tcase CMD_MIFARE_EML_CGETBLOCK:\r\n\t\t\tMifareCGetBlock(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes);\r\n\t\t\tbreak;\r\n\t\t\t\r\n\t\t// mifare sniffer\r\n\t\tcase CMD_MIFARE_SNIFFER:\r\n\t\t\tSniffMifare(c->arg[0]);\r\n\t\t\tbreak;\r\n#endif\r\n\r\n#ifdef WITH_ICLASS\r\n\t\t// Makes use of ISO14443a FPGA Firmware\r\n\t\tcase CMD_SNOOP_ICLASS:\r\n\t\t\tSnoopIClass();\r\n\t\t\tbreak;\r\n\t\tcase CMD_SIMULATE_TAG_ICLASS:\r\n\t\t\tSimulateIClass(c->arg[0], c->d.asBytes);\r\n\t\t\tbreak;\r\n\t\tcase CMD_READER_ICLASS:\r\n\t\t\tReaderIClass(c->arg[0]);\r\n\t\t\tbreak;\r\n#endif\r\n\r\n\t\tcase CMD_SIMULATE_TAG_HF_LISTEN:\r\n\t\t\tSimulateTagHfListen();\r\n\t\t\tbreak;\r\n\r\n\t\tcase CMD_BUFF_CLEAR:\r\n\t\t\tBufferClear();\r\n\t\t\tbreak;\r\n\r\n\t\tcase CMD_MEASURE_ANTENNA_TUNING:\r\n\t\t\tMeasureAntennaTuning();\r\n\t\t\tbreak;\r\n\r\n\t\tcase CMD_MEASURE_ANTENNA_TUNING_HF:\r\n\t\t\tMeasureAntennaTuningHf();\r\n\t\t\tbreak;\r\n\r\n\t\tcase CMD_LISTEN_READER_FIELD:\r\n\t\t\tListenReaderField(c->arg[0]);\r\n\t\t\tbreak;\r\n\r\n\t\tcase CMD_FPGA_MAJOR_MODE_OFF:\t\t// ## FPGA Control\r\n\t\t\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\t\t\tSpinDelay(200);\r\n\t\t\tLED_D_OFF(); // LED D indicates field ON or OFF\r\n\t\t\tbreak;\r\n\r\n\t\tcase CMD_DOWNLOAD_RAW_ADC_SAMPLES_125K:\r\n//\t\t\tUsbCommand n;\r\n//\t\t\tif(c->cmd == CMD_DOWNLOAD_RAW_ADC_SAMPLES_125K) {\r\n//\t\t\t\tn.cmd = CMD_DOWNLOADED_RAW_ADC_SAMPLES_125K;\r\n//\t\t\t} else {\r\n//\t\t\t\tn.cmd = CMD_DOWNLOADED_RAW_BITS_TI_TYPE;\r\n//\t\t\t}\r\n//\t\t\tn.arg[0] = c->arg[0];\r\n //\t\t\tmemcpy(n.d.asBytes, BigBuf+c->arg[0], 48); // 12*sizeof(uint32_t)\r\n //\t\t\tLED_B_ON();\r\n // usb_write((uint8_t *)&n, sizeof(n));\r\n //\t\t\tUsbSendPacket((uint8_t *)&n, sizeof(n));\r\n //\t\t\tLED_B_OFF();\r\n\r\n\t\t\tLED_B_ON();\r\n\t\t\tfor(size_t i=0; iarg[1]; i += USB_CMD_DATA_SIZE) {\r\n\t\t\t\tsize_t len = MIN((c->arg[1] - i),USB_CMD_DATA_SIZE);\r\n\t\t\t\tcmd_send(CMD_DOWNLOADED_RAW_ADC_SAMPLES_125K,i,len,0,((byte_t*)BigBuf)+c->arg[0]+i,len);\r\n\t\t\t}\r\n\t\t\t// Trigger a finish downloading signal with an ACK frame\r\n\t\t\tcmd_send(CMD_ACK,0,0,0,0,0);\r\n\t\t\tLED_B_OFF();\r\n\t\t\tbreak;\r\n\r\n\t\tcase CMD_DOWNLOADED_SIM_SAMPLES_125K: {\r\n\t\t\tuint8_t *b = (uint8_t *)BigBuf;\r\n\t\t\tmemcpy(b+c->arg[0], c->d.asBytes, 48);\r\n\t\t\t//Dbprintf(\"copied 48 bytes to %i\",b+c->arg[0]);\r\n//\t\t\tUsbSendPacket((uint8_t*)&ack, sizeof(ack));\r\n\t\t\tcmd_send(CMD_ACK,0,0,0,0,0);\r\n\t\t\tbreak;\r\n\t\t}\t\r\n\t\tcase CMD_READ_MEM:\r\n\t\t\tReadMem(c->arg[0]);\r\n\t\t\tbreak;\r\n\r\n\t\tcase CMD_SET_LF_DIVISOR:\r\n\t\t\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, c->arg[0]);\r\n\t\t\tbreak;\r\n\r\n\t\tcase CMD_SET_ADC_MUX:\r\n\t\t\tswitch(c->arg[0]) {\r\n\t\t\t\tcase 0: SetAdcMuxFor(GPIO_MUXSEL_LOPKD); break;\r\n\t\t\t\tcase 1: SetAdcMuxFor(GPIO_MUXSEL_LORAW); break;\r\n\t\t\t\tcase 2: SetAdcMuxFor(GPIO_MUXSEL_HIPKD); break;\r\n\t\t\t\tcase 3: SetAdcMuxFor(GPIO_MUXSEL_HIRAW); break;\r\n\t\t\t}\r\n\t\t\tbreak;\r\n\r\n\t\tcase CMD_VERSION:\r\n\t\t\tSendVersion();\r\n\t\t\tbreak;\r\n\r\n#ifdef WITH_LCD\r\n\t\tcase CMD_LCD_RESET:\r\n\t\t\tLCDReset();\r\n\t\t\tbreak;\r\n\t\tcase CMD_LCD:\r\n\t\t\tLCDSend(c->arg[0]);\r\n\t\t\tbreak;\r\n#endif\r\n\t\tcase CMD_SETUP_WRITE:\r\n\t\tcase CMD_FINISH_WRITE:\r\n\t\tcase CMD_HARDWARE_RESET:\r\n\t\t\tusb_disable();\r\n\t\t\tSpinDelay(1000);\r\n\t\t\tSpinDelay(1000);\r\n\t\t\tAT91C_BASE_RSTC->RSTC_RCR = RST_CONTROL_KEY | AT91C_RSTC_PROCRST;\r\n\t\t\tfor(;;) {\r\n\t\t\t\t// We're going to reset, and the bootrom will take control.\r\n\t\t\t}\r\n\t\t\tbreak;\r\n\r\n\t\tcase CMD_START_FLASH:\r\n\t\t\tif(common_area.flags.bootrom_present) {\r\n\t\t\t\tcommon_area.command = COMMON_AREA_COMMAND_ENTER_FLASH_MODE;\r\n\t\t\t}\r\n\t\t\tusb_disable();\r\n\t\t\tAT91C_BASE_RSTC->RSTC_RCR = RST_CONTROL_KEY | AT91C_RSTC_PROCRST;\r\n\t\t\tfor(;;);\r\n\t\t\tbreak;\r\n\r\n\t\tcase CMD_DEVICE_INFO: {\r\n\t\t\tuint32_t dev_info = DEVICE_INFO_FLAG_OSIMAGE_PRESENT | DEVICE_INFO_FLAG_CURRENT_MODE_OS;\r\n\t\t\tif(common_area.flags.bootrom_present) dev_info |= DEVICE_INFO_FLAG_BOOTROM_PRESENT;\r\n//\t\t\tUsbSendPacket((uint8_t*)&c, sizeof(c));\r\n\t\t\tcmd_send(CMD_DEVICE_INFO,dev_info,0,0,0,0);\t\r\n\t\t\tbreak;\r\n\t\t}\r\n\t\tdefault:\r\n\t\t\tDbprintf(\"%s: 0x%04x\",\"unknown command:\",c->cmd);\r\n\t\t\tbreak;\r\n\t}\r\n}\r\n\r\nvoid __attribute__((noreturn)) AppMain(void)\r\n{\r\n\tSpinDelay(100);\r\n\r\n\tif(common_area.magic != COMMON_AREA_MAGIC || common_area.version != 1) {\r\n\t\t/* Initialize common area */\r\n\t\tmemset(&common_area, 0, sizeof(common_area));\r\n\t\tcommon_area.magic = COMMON_AREA_MAGIC;\r\n\t\tcommon_area.version = 1;\r\n\t}\r\n\tcommon_area.flags.osimage_present = 1;\r\n\r\n\tLED_D_OFF();\r\n\tLED_C_OFF();\r\n\tLED_B_OFF();\r\n\tLED_A_OFF();\r\n\r\n // Init USB device`\r\n usb_enable();\r\n//\tUsbStart();\r\n\r\n\t// The FPGA gets its clock from us from PCK0 output, so set that up.\r\n\tAT91C_BASE_PIOA->PIO_BSR = GPIO_PCK0;\r\n\tAT91C_BASE_PIOA->PIO_PDR = GPIO_PCK0;\r\n\tAT91C_BASE_PMC->PMC_SCER = AT91C_PMC_PCK0;\r\n\t// PCK0 is PLL clock / 4 = 96Mhz / 4 = 24Mhz\r\n\tAT91C_BASE_PMC->PMC_PCKR[0] = AT91C_PMC_CSS_PLL_CLK |\r\n\t\tAT91C_PMC_PRES_CLK_4;\r\n\tAT91C_BASE_PIOA->PIO_OER = GPIO_PCK0;\r\n\r\n\t// Reset SPI\r\n\tAT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST;\r\n\t// Reset SSC\r\n\tAT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;\r\n\r\n\t// Load the FPGA image, which we have stored in our flash.\r\n\tFpgaDownloadAndGo();\r\n\r\n\tStartTickCount();\r\n \t\r\n#ifdef WITH_LCD\r\n\tLCDInit();\r\n#endif\r\n\r\n byte_t rx[sizeof(UsbCommand)];\r\n\tsize_t rx_len;\r\n \r\n\tfor(;;) {\r\n if (usb_poll()) {\r\n rx_len = usb_read(rx,sizeof(UsbCommand));\r\n if (rx_len) {\r\n UsbPacketReceived(rx,rx_len);\r\n }\r\n }\r\n//\t\tUsbPoll(FALSE);\r\n\r\n\t\tWDT_HIT();\r\n\r\n#ifdef WITH_LF\r\n\t\tif (BUTTON_HELD(1000) > 0)\r\n\t\t\tSamyRun();\r\n#endif\r\n\t}\r\n}\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/apps.h", "content": "//-----------------------------------------------------------------------------\r\n// Jonathan Westhues, Aug 2005\r\n// Gerhard de Koning Gans, April 2008, May 2011\r\n//\r\n// This code is licensed to you under the terms of the GNU GPL, version 2 or,\r\n// at your option, any later version. See the LICENSE.txt file for the text of\r\n// the license.\r\n//-----------------------------------------------------------------------------\r\n// Definitions internal to the app source.\r\n//-----------------------------------------------------------------------------\r\n\r\n#ifndef __APPS_H\r\n#define __APPS_H\r\n\r\n#include \r\n#include \r\n#include \"common.h\"\r\n#include \"hitag2.h\"\r\n#include \"mifare.h\"\r\n\r\n// The large multi-purpose buffer, typically used to hold A/D samples,\r\n// maybe processed in some way.\r\nuint8_t BigBuf[40000];\r\n// BIG CHANGE - UNDERSTAND THIS BEFORE WE COMMIT\r\n#define TRACE_OFFSET 0\r\n#define TRACE_SIZE 3000\r\n#define RECV_CMD_OFFSET 3032\r\n#define RECV_CMD_SIZE 64\r\n#define RECV_RES_OFFSET 3096\r\n#define RECV_RES_SIZE 64\r\n#define DMA_BUFFER_OFFSET 3160\r\n#define DMA_BUFFER_SIZE 4096\r\n#define FREE_BUFFER_OFFSET 7256\r\n#define FREE_BUFFER_SIZE 2744\r\n\r\nextern const uint8_t OddByteParity[256];\r\nextern uint8_t *trace; // = (uint8_t *) BigBuf;\r\nextern int traceLen; // = 0;\r\nextern int rsamples; // = 0;\r\nextern int tracing; // = TRUE;\r\nextern uint8_t trigger;\r\n\r\n// This may be used (sparingly) to declare a function to be copied to\r\n// and executed from RAM\r\n#define RAMFUNC __attribute((long_call, section(\".ramfunc\")))\r\n\r\n/// appmain.h\r\nvoid ReadMem(int addr);\r\nvoid __attribute__((noreturn)) AppMain(void);\r\nvoid SamyRun(void);\r\n//void DbpIntegers(int a, int b, int c);\r\nvoid DbpString(char *str);\r\nvoid Dbprintf(const char *fmt, ...);\r\nvoid Dbhexdump(int len, uint8_t *d, bool bAsci);\r\n\r\nint AvgAdc(int ch);\r\n\r\nvoid ToSendStuffBit(int b);\r\nvoid ToSendReset(void);\r\nvoid ListenReaderField(int limit);\r\nvoid AcquireRawAdcSamples125k(int at134khz);\r\nvoid DoAcquisition125k(void);\r\nextern int ToSendMax;\r\nextern uint8_t ToSend[];\r\nextern uint8_t BigBuf[];\r\n\r\n/// fpga.h\r\nvoid FpgaSendCommand(uint16_t cmd, uint16_t v);\r\nvoid FpgaWriteConfWord(uint8_t v);\r\nvoid FpgaDownloadAndGo(void);\r\nvoid FpgaGatherVersion(char *dst, int len);\r\nvoid FpgaSetupSsc(void);\r\nvoid SetupSpi(int mode);\r\nbool FpgaSetupSscDma(uint8_t *buf, int len);\r\n#define FpgaDisableSscDma(void)\tAT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;\r\n#define FpgaEnableSscDma(void) AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN;\r\nvoid SetAdcMuxFor(uint32_t whichGpio);\r\n\r\n// Definitions for the FPGA commands.\r\n#define FPGA_CMD_SET_CONFREG\t\t\t\t\t\t(1<<12)\r\n#define FPGA_CMD_SET_DIVISOR\t\t\t\t\t\t(2<<12)\r\n// Definitions for the FPGA configuration word.\r\n#define FPGA_MAJOR_MODE_LF_READER\t\t\t\t\t(0<<5)\r\n#define FPGA_MAJOR_MODE_LF_EDGE_DETECT\t\t\t\t(1<<5)\r\n#define FPGA_MAJOR_MODE_HF_READER_TX\t\t\t\t(2<<5)\r\n#define FPGA_MAJOR_MODE_HF_READER_RX_XCORR\t\t\t(3<<5)\r\n#define FPGA_MAJOR_MODE_HF_SIMULATOR\t\t\t\t(4<<5)\r\n#define FPGA_MAJOR_MODE_HF_ISO14443A\t\t\t\t(5<<5)\r\n#define FPGA_MAJOR_MODE_LF_PASSTHRU\t\t\t\t\t(6<<5)\r\n#define FPGA_MAJOR_MODE_OFF\t\t\t\t\t\t\t(7<<5)\r\n// Options for LF_EDGE_DETECT\r\n#define FPGA_LF_EDGE_DETECT_READER_FIELD \t\t\t(1<<0)\r\n// Options for the HF reader, tx to tag\r\n#define FPGA_HF_READER_TX_SHALLOW_MOD\t\t\t\t(1<<0)\r\n// Options for the HF reader, correlating against rx from tag\r\n#define FPGA_HF_READER_RX_XCORR_848_KHZ\t\t\t\t(1<<0)\r\n#define FPGA_HF_READER_RX_XCORR_SNOOP\t\t\t\t(1<<1)\r\n#define FPGA_HF_READER_RX_XCORR_QUARTER_FREQ\t\t(1<<2)\r\n// Options for the HF simulated tag, how to modulate\r\n#define FPGA_HF_SIMULATOR_NO_MODULATION\t\t\t\t(0<<0)\r\n#define FPGA_HF_SIMULATOR_MODULATE_BPSK\t\t\t\t(1<<0)\r\n#define FPGA_HF_SIMULATOR_MODULATE_212K\t\t\t\t(2<<0)\r\n// Options for ISO14443A\r\n#define FPGA_HF_ISO14443A_SNIFFER\t\t\t\t\t(0<<0)\r\n#define FPGA_HF_ISO14443A_TAGSIM_LISTEN\t\t\t\t(1<<0)\r\n#define FPGA_HF_ISO14443A_TAGSIM_MOD\t\t\t\t(2<<0)\r\n#define FPGA_HF_ISO14443A_READER_LISTEN\t\t\t\t(3<<0)\r\n#define FPGA_HF_ISO14443A_READER_MOD\t\t\t\t(4<<0)\r\n\r\n/// lfops.h\r\nvoid AcquireRawAdcSamples125k(int at134khz);\r\nvoid ModThenAcquireRawAdcSamples125k(int delay_off,int period_0,int period_1,uint8_t *command);\r\nvoid ReadTItag(void);\r\nvoid WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc);\r\nvoid AcquireTiType(void);\r\nvoid AcquireRawBitsTI(void);\r\nvoid SimulateTagLowFrequency(int period, int gap, int ledcontrol);\r\nvoid CmdHIDsimTAG(int hi, int lo, int ledcontrol);\r\nvoid CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol);\r\nvoid SimulateTagLowFrequencyBidir(int divisor, int max_bitlen);\r\nvoid CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT); // Clone an HID card to T5557/T5567\r\nvoid WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo);\r\nvoid CopyIndala64toT55x7(int hi, int lo); // Clone Indala 64-bit tag by UID to T55x7\r\nvoid CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7); // Clone Indala 224-bit tag by UID to T55x7\r\nvoid T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode);\r\nvoid T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode );\r\nvoid T55xxReadTrace(void);\r\nint DemodPCF7931(uint8_t **outBlocks);\r\nint IsBlock0PCF7931(uint8_t *Block);\r\nint IsBlock1PCF7931(uint8_t *Block);\r\nvoid ReadPCF7931();\r\nvoid EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode);\r\nvoid EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode);\r\n\r\n/// iso14443.h\r\nvoid SimulateIso14443Tag(void);\r\nvoid AcquireRawAdcSamplesIso14443(uint32_t parameter);\r\nvoid ReadSRI512Iso14443(uint32_t parameter);\r\nvoid ReadSRIX4KIso14443(uint32_t parameter);\r\nvoid ReadSTMemoryIso14443(uint32_t parameter,uint32_t dwLast);\r\nvoid RAMFUNC SnoopIso14443(void);\r\n\r\n/// iso14443a.h\r\nvoid RAMFUNC SnoopIso14443a(uint8_t param);\r\nvoid SimulateIso14443aTag(int tagType, int uid_1st, int uid_2nd, byte_t* data);\r\nvoid ReaderIso14443a(UsbCommand * c);\r\n// Also used in iclass.c\r\nint RAMFUNC LogTrace(const uint8_t * btBytes, int iLen, int iSamples, uint32_t dwParity, int bReader);\r\nuint32_t GetParity(const uint8_t * pbtCmd, int iLen);\r\nvoid iso14a_set_trigger(bool enable);\r\nvoid iso14a_clear_trace();\r\nvoid iso14a_set_tracing(bool enable);\r\nvoid RAMFUNC SniffMifare(uint8_t param);\r\n\r\n/// epa.h\r\nvoid EPA_PACE_Collect_Nonce(UsbCommand * c);\r\n\r\n// mifarecmd.h\r\nvoid ReaderMifare(bool first_try);\r\nvoid MifareReadBlock(uint8_t arg0, uint8_t arg1, uint8_t arg2, uint8_t *data);\r\nvoid MifareReadSector(uint8_t arg0, uint8_t arg1, uint8_t arg2, uint8_t *datain);\r\nvoid MifareWriteBlock(uint8_t arg0, uint8_t arg1, uint8_t arg2, uint8_t *datain);\r\nvoid MifareNested(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain);\r\nvoid MifareChkKeys(uint8_t arg0, uint8_t arg1, uint8_t arg2, uint8_t *datain);\r\nvoid Mifare1ksim(uint8_t arg0, uint8_t arg1, uint8_t arg2, uint8_t *datain);\r\nvoid MifareSetDbgLvl(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain);\r\nvoid MifareEMemClr(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain);\r\nvoid MifareEMemSet(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain);\r\nvoid MifareEMemGet(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain);\r\nvoid MifareECardLoad(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain);\r\nvoid MifareCSetBlock(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain); // Work with \"magic Chinese\" card\r\nvoid MifareCGetBlock(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain);\r\n\r\n/// iso15693.h\r\nvoid RecordRawAdcSamplesIso15693(void);\r\nvoid AcquireRawAdcSamplesIso15693(void);\r\nvoid ReaderIso15693(uint32_t parameter);\t// Simulate an ISO15693 reader - greg\r\nvoid SimTagIso15693(uint32_t parameter);\t// simulate an ISO15693 tag - greg\r\nvoid BruteforceIso15693Afi(uint32_t speed); // find an AFI of a tag - atrox\r\nvoid DirectTag15693Command(uint32_t datalen,uint32_t speed, uint32_t recv, uint8_t data[]); // send arbitrary commands from CLI - atrox \r\nvoid SetDebugIso15693(uint32_t flag);\r\n\r\n/// iclass.h\r\nvoid RAMFUNC SnoopIClass(void);\r\nvoid SimulateIClass(uint8_t arg0, uint8_t *datain);\r\nvoid ReaderIClass(uint8_t arg0);\r\n\r\n// hitag2.h\r\nvoid SnoopHitag(uint32_t type);\r\nvoid SimulateHitagTag(bool tag_mem_supplied, byte_t* data);\r\nvoid ReaderHitag(hitag_function htf, hitag_data* htd);\r\n\r\n// cmd.h\r\nbool cmd_receive(UsbCommand* cmd);\r\nbool cmd_send(uint32_t cmd, uint32_t arg0, uint32_t arg1, uint32_t arg2, void* data, size_t len);\r\n\r\n/// util.h\r\n\r\n#endif\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/crapto1.c", "content": "/* crapto1.c\r\n\r\n This program is free software; you can redistribute it and/or\r\n modify it under the terms of the GNU General Public License\r\n as published by the Free Software Foundation; either version 2\r\n of the License, or (at your option) any later version.\r\n\r\n This program is distributed in the hope that it will be useful,\r\n but WITHOUT ANY WARRANTY; without even the implied warranty of\r\n MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r\n GNU General Public License for more details.\r\n\r\n You should have received a copy of the GNU General Public License\r\n along with this program; if not, write to the Free Software\r\n Foundation, Inc., 51 Franklin Street, Fifth Floor,\r\n Boston, MA 02110-1301, US$\r\n\r\n Copyright (C) 2008-2008 bla \r\n*/\r\n#include \"crapto1.h\"\r\n#include \r\n\r\n#if !defined LOWMEM && defined __GNUC__\r\nstatic uint8_t filterlut[1 << 20];\r\nstatic void __attribute__((constructor)) fill_lut()\r\n{\r\n uint32_t i;\r\n for(i = 0; i < 1 << 20; ++i)\r\n filterlut[i] = filter(i);\r\n}\r\n#define filter(x) (filterlut[(x) & 0xfffff])\r\n#endif\r\n\r\nstatic void quicksort(uint32_t* const start, uint32_t* const stop)\r\n{\r\n\tuint32_t *it = start + 1, *rit = stop;\r\n\r\n\tif(it > rit)\r\n\t\treturn;\r\n\r\n\twhile(it < rit)\r\n\t\tif(*it <= *start)\r\n\t\t\t++it;\r\n\t\telse if(*rit > *start)\r\n\t\t\t--rit;\r\n\t\telse\r\n\t\t\t*it ^= (*it ^= *rit, *rit ^= *it);\r\n\r\n\tif(*rit >= *start)\r\n\t\t--rit;\r\n\tif(rit != start)\r\n\t\t*rit ^= (*rit ^= *start, *start ^= *rit);\r\n\r\n\tquicksort(start, rit - 1);\r\n\tquicksort(rit + 1, stop);\r\n}\r\n/** binsearch\r\n * Binary search for the first occurence of *stop's MSB in sorted [start,stop]\r\n */\r\nstatic inline uint32_t* binsearch(uint32_t *start, uint32_t *stop)\r\n{\r\n\tuint32_t mid, val = *stop & 0xff000000;\r\n\twhile(start != stop)\r\n\t\tif(start[mid = (stop - start) >> 1] > val)\r\n\t\t\tstop = &start[mid];\r\n\t\telse\r\n\t\t\tstart += mid + 1;\r\n\r\n\treturn start;\r\n}\r\n\r\n/** update_contribution\r\n * helper, calculates the partial linear feedback contributions and puts in MSB\r\n */\r\nstatic inline void\r\nupdate_contribution(uint32_t *item, const uint32_t mask1, const uint32_t mask2)\r\n{\r\n\tuint32_t p = *item >> 25;\r\n\r\n\tp = p << 1 | parity(*item & mask1);\r\n\tp = p << 1 | parity(*item & mask2);\r\n\t*item = p << 24 | (*item & 0xffffff);\r\n}\r\n\r\n/** extend_table\r\n * using a bit of the keystream extend the table of possible lfsr states\r\n */\r\nstatic inline void\r\nextend_table(uint32_t *tbl, uint32_t **end, int bit, int m1, int m2, uint32_t in)\r\n{\r\n\tin <<= 24;\r\n\tfor(*tbl <<= 1; tbl <= *end; *++tbl <<= 1)\r\n\t\tif(filter(*tbl) ^ filter(*tbl | 1)) {\r\n\t\t\t*tbl |= filter(*tbl) ^ bit;\r\n\t\t\tupdate_contribution(tbl, m1, m2);\r\n\t\t\t*tbl ^= in;\r\n\t\t} else if(filter(*tbl) == bit) {\r\n\t\t\t*++*end = tbl[1];\r\n\t\t\ttbl[1] = tbl[0] | 1;\r\n\t\t\tupdate_contribution(tbl, m1, m2);\r\n\t\t\t*tbl++ ^= in;\r\n\t\t\tupdate_contribution(tbl, m1, m2);\r\n\t\t\t*tbl ^= in;\r\n\t\t} else\r\n\t\t\t*tbl-- = *(*end)--;\r\n}\r\n/** extend_table_simple\r\n * using a bit of the keystream extend the table of possible lfsr states\r\n */\r\nstatic inline void extend_table_simple(uint32_t *tbl, uint32_t **end, int bit)\r\n{\r\n\tfor(*tbl <<= 1; tbl <= *end; *++tbl <<= 1)\r\n\t\tif(filter(*tbl) ^ filter(*tbl | 1))\r\n\t\t\t*tbl |= filter(*tbl) ^ bit;\r\n\t\telse if(filter(*tbl) == bit) {\r\n\t\t\t*++*end = *++tbl;\r\n\t\t\t*tbl = tbl[-1] | 1;\r\n\t\t} else\r\n\t\t\t*tbl-- = *(*end)--;\r\n}\r\n/** recover\r\n * recursively narrow down the search space, 4 bits of keystream at a time\r\n */\r\nstatic struct Crypto1State*\r\nrecover(uint32_t *o_head, uint32_t *o_tail, uint32_t oks,\r\n\tuint32_t *e_head, uint32_t *e_tail, uint32_t eks, int rem,\r\n\tstruct Crypto1State *sl, uint32_t in)\r\n{\r\n\tuint32_t *o, *e, i;\r\n\r\n\tif(rem == -1) {\r\n\t\tfor(e = e_head; e <= e_tail; ++e) {\r\n\t\t\t*e = *e << 1 ^ parity(*e & LF_POLY_EVEN) ^ !!(in & 4);\r\n\t\t\tfor(o = o_head; o <= o_tail; ++o, ++sl) {\r\n\t\t\t\tsl->even = *o;\r\n\t\t\t\tsl->odd = *e ^ parity(*o & LF_POLY_ODD);\r\n\t\t\t\tsl[1].odd = sl[1].even = 0;\r\n\t\t\t}\r\n\t\t}\r\n\t\treturn sl;\r\n\t}\r\n\r\n\tfor(i = 0; i < 4 && rem--; i++) {\r\n\t\toks >>= 1;\r\n\t\teks >>= 1;\r\n\t\tin >>= 2;\r\n\t\textend_table(o_head, &o_tail, oks & 1, LF_POLY_EVEN << 1 | 1,\r\n\t\t\t LF_POLY_ODD << 1, 0);\r\n\t\tif(o_head > o_tail)\r\n\t\t\treturn sl;\r\n\r\n\t\textend_table(e_head, &e_tail, eks & 1, LF_POLY_ODD,\r\n\t\t\t LF_POLY_EVEN << 1 | 1, in & 3);\r\n\t\tif(e_head > e_tail)\r\n\t\t\treturn sl;\r\n\t}\r\n\r\n\tquicksort(o_head, o_tail);\r\n\tquicksort(e_head, e_tail);\r\n\r\n\twhile(o_tail >= o_head && e_tail >= e_head)\r\n\t\tif(((*o_tail ^ *e_tail) >> 24) == 0) {\r\n\t\t\to_tail = binsearch(o_head, o = o_tail);\r\n\t\t\te_tail = binsearch(e_head, e = e_tail);\r\n\t\t\tsl = recover(o_tail--, o, oks,\r\n\t\t\t\t e_tail--, e, eks, rem, sl, in);\r\n\t\t}\r\n\t\telse if(*o_tail > *e_tail)\r\n\t\t\to_tail = binsearch(o_head, o_tail) - 1;\r\n\t\telse\r\n\t\t\te_tail = binsearch(e_head, e_tail) - 1;\r\n\r\n\treturn sl;\r\n}\r\n/** lfsr_recovery\r\n * recover the state of the lfsr given 32 bits of the keystream\r\n * additionally you can use the in parameter to specify the value\r\n * that was fed into the lfsr at the time the keystream was generated\r\n */\r\nstruct Crypto1State* lfsr_recovery32(uint32_t ks2, uint32_t in)\r\n{\r\n\tstruct Crypto1State *statelist;\r\n\tuint32_t *odd_head = 0, *odd_tail = 0, oks = 0;\r\n\tuint32_t *even_head = 0, *even_tail = 0, eks = 0;\r\n\tint i;\r\n\r\n\tfor(i = 31; i >= 0; i -= 2)\r\n\t\toks = oks << 1 | BEBIT(ks2, i);\r\n\tfor(i = 30; i >= 0; i -= 2)\r\n\t\teks = eks << 1 | BEBIT(ks2, i);\r\n\r\n\todd_head = odd_tail = malloc(sizeof(uint32_t) << 21);\r\n\teven_head = even_tail = malloc(sizeof(uint32_t) << 21);\r\n\tstatelist = malloc(sizeof(struct Crypto1State) << 18);\r\n\tif(!odd_tail-- || !even_tail-- || !statelist) {\r\n\t\tfree(statelist);\r\n\t\tstatelist = 0;\r\n\t\tgoto out;\r\n\t}\r\n\r\n\tstatelist->odd = statelist->even = 0;\r\n\r\n\tfor(i = 1 << 20; i >= 0; --i) {\r\n\t\tif(filter(i) == (oks & 1))\r\n\t\t\t*++odd_tail = i;\r\n\t\tif(filter(i) == (eks & 1))\r\n\t\t\t*++even_tail = i;\r\n\t}\r\n\r\n\tfor(i = 0; i < 4; i++) {\r\n\t\textend_table_simple(odd_head, &odd_tail, (oks >>= 1) & 1);\r\n\t\textend_table_simple(even_head, &even_tail, (eks >>= 1) & 1);\r\n\t}\r\n\r\n\tin = (in >> 16 & 0xff) | (in << 16) | (in & 0xff00);\r\n\trecover(odd_head, odd_tail, oks,\r\n\t\teven_head, even_tail, eks, 11, statelist, in << 1);\r\n\r\nout:\r\n\tfree(odd_head);\r\n\tfree(even_head);\r\n\treturn statelist;\r\n}\r\n\r\nstatic const uint32_t S1[] = { 0x62141, 0x310A0, 0x18850, 0x0C428, 0x06214,\r\n\t0x0310A, 0x85E30, 0xC69AD, 0x634D6, 0xB5CDE, 0xDE8DA, 0x6F46D, 0xB3C83,\r\n\t0x59E41, 0xA8995, 0xD027F, 0x6813F, 0x3409F, 0x9E6FA};\r\nstatic const uint32_t S2[] = { 0x3A557B00, 0x5D2ABD80, 0x2E955EC0, 0x174AAF60,\r\n\t0x0BA557B0, 0x05D2ABD8, 0x0449DE68, 0x048464B0, 0x42423258, 0x278192A8,\r\n\t0x156042D0, 0x0AB02168, 0x43F89B30, 0x61FC4D98, 0x765EAD48, 0x7D8FDD20,\r\n\t0x7EC7EE90, 0x7F63F748, 0x79117020};\r\nstatic const uint32_t T1[] = {\r\n\t0x4F37D, 0x279BE, 0x97A6A, 0x4BD35, 0x25E9A, 0x12F4D, 0x097A6, 0x80D66,\r\n\t0xC4006, 0x62003, 0xB56B4, 0x5AB5A, 0xA9318, 0xD0F39, 0x6879C, 0xB057B,\r\n\t0x582BD, 0x2C15E, 0x160AF, 0x8F6E2, 0xC3DC4, 0xE5857, 0x72C2B, 0x39615,\r\n\t0x98DBF, 0xC806A, 0xE0680, 0x70340, 0x381A0, 0x98665, 0x4C332, 0xA272C};\r\nstatic const uint32_t T2[] = { 0x3C88B810, 0x5E445C08, 0x2982A580, 0x14C152C0,\r\n\t0x4A60A960, 0x253054B0, 0x52982A58, 0x2FEC9EA8, 0x1156C4D0, 0x08AB6268,\r\n\t0x42F53AB0, 0x217A9D58, 0x161DC528, 0x0DAE6910, 0x46D73488, 0x25CB11C0,\r\n\t0x52E588E0, 0x6972C470, 0x34B96238, 0x5CFC3A98, 0x28DE96C8, 0x12CFC0E0,\r\n\t0x4967E070, 0x64B3F038, 0x74F97398, 0x7CDC3248, 0x38CE92A0, 0x1C674950,\r\n\t0x0E33A4A8, 0x01B959D0, 0x40DCACE8, 0x26CEDDF0};\r\nstatic const uint32_t C1[] = { 0x846B5, 0x4235A, 0x211AD};\r\nstatic const uint32_t C2[] = { 0x1A822E0, 0x21A822E0, 0x21A822E0};\r\n/** Reverse 64 bits of keystream into possible cipher states\r\n * Variation mentioned in the paper. Somewhat optimized version\r\n */\r\nstruct Crypto1State* lfsr_recovery64(uint32_t ks2, uint32_t ks3)\r\n{\r\n\tstruct Crypto1State *statelist, *sl;\r\n\tuint8_t oks[32], eks[32], hi[32];\r\n\tuint32_t low = 0, win = 0;\r\n\tuint32_t *tail, table[1 << 16];\r\n\tint i, j;\r\n\r\n\tsl = statelist = malloc(sizeof(struct Crypto1State) << 4);\r\n\tif(!sl)\r\n\t\treturn 0;\r\n\tsl->odd = sl->even = 0;\r\n\r\n\tfor(i = 30; i >= 0; i -= 2) {\r\n\t\toks[i >> 1] = BEBIT(ks2, i);\r\n\t\toks[16 + (i >> 1)] = BEBIT(ks3, i);\r\n\t}\r\n\tfor(i = 31; i >= 0; i -= 2) {\r\n\t\teks[i >> 1] = BEBIT(ks2, i);\r\n\t\teks[16 + (i >> 1)] = BEBIT(ks3, i);\r\n\t}\r\n\r\n\tfor(i = 0xfffff; i >= 0; --i) {\r\n\t\tif (filter(i) != oks[0])\r\n\t\t\tcontinue;\r\n\r\n\t\t*(tail = table) = i;\r\n\t\tfor(j = 1; tail >= table && j < 29; ++j)\r\n\t\t\textend_table_simple(table, &tail, oks[j]);\r\n\r\n\t\tif(tail < table)\r\n\t\t\tcontinue;\r\n\r\n\t\tfor(j = 0; j < 19; ++j)\r\n\t\t\tlow = low << 1 | parity(i & S1[j]);\r\n\t\tfor(j = 0; j < 32; ++j)\r\n\t\t\thi[j] = parity(i & T1[j]);\r\n\r\n\t\tfor(; tail >= table; --tail) {\r\n\t\t\tfor(j = 0; j < 3; ++j) {\r\n\t\t\t\t*tail = *tail << 1;\r\n\t\t\t\t*tail |= parity((i & C1[j]) ^ (*tail & C2[j]));\r\n\t\t\t\tif(filter(*tail) != oks[29 + j])\r\n\t\t\t\t\tgoto continue2;\r\n\t\t\t}\r\n\r\n\t\t\tfor(j = 0; j < 19; ++j)\r\n\t\t\t\twin = win << 1 | parity(*tail & S2[j]);\r\n\r\n\t\t\twin ^= low;\r\n\t\t\tfor(j = 0; j < 32; ++j) {\r\n\t\t\t\twin = win << 1 ^ hi[j] ^ parity(*tail & T2[j]);\r\n\t\t\t\tif(filter(win) != eks[j])\r\n\t\t\t\t\tgoto continue2;\r\n\t\t\t}\r\n\r\n\t\t\t*tail = *tail << 1 | parity(LF_POLY_EVEN & *tail);\r\n\t\t\tsl->odd = *tail ^ parity(LF_POLY_ODD & win);\r\n\t\t\tsl->even = win;\r\n\t\t\t++sl;\r\n\t\t\tsl->odd = sl->even = 0;\r\n\t\t\tcontinue2:;\r\n\t\t}\r\n\t}\r\n\treturn statelist;\r\n}\r\n\r\n/** lfsr_rollback_bit\r\n * Rollback the shift register in order to get previous states\r\n */\r\nuint8_t lfsr_rollback_bit(struct Crypto1State *s, uint32_t in, int fb)\r\n{\r\n\tint out;\r\n\tuint8_t ret;\r\n\r\n\ts->odd &= 0xffffff;\r\n\ts->odd ^= (s->odd ^= s->even, s->even ^= s->odd);\r\n\r\n\tout = s->even & 1;\r\n\tout ^= LF_POLY_EVEN & (s->even >>= 1);\r\n\tout ^= LF_POLY_ODD & s->odd;\r\n\tout ^= !!in;\r\n\tout ^= (ret = filter(s->odd)) & !!fb;\r\n\r\n\ts->even |= parity(out) << 23;\r\n\treturn ret;\r\n}\r\n/** lfsr_rollback_byte\r\n * Rollback the shift register in order to get previous states\r\n */\r\nuint8_t lfsr_rollback_byte(struct Crypto1State *s, uint32_t in, int fb)\r\n{\r\n\tint i, ret = 0;\r\n\tfor (i = 7; i >= 0; --i)\r\n\t\tret |= lfsr_rollback_bit(s, BIT(in, i), fb) << i;\r\n\treturn ret;\r\n}\r\n/** lfsr_rollback_word\r\n * Rollback the shift register in order to get previous states\r\n */\r\nuint32_t lfsr_rollback_word(struct Crypto1State *s, uint32_t in, int fb)\r\n{\r\n\tint i;\r\n\tuint32_t ret = 0;\r\n\tfor (i = 31; i >= 0; --i)\r\n\t\tret |= lfsr_rollback_bit(s, BEBIT(in, i), fb) << (i ^ 24);\r\n\treturn ret;\r\n}\r\n\r\n/** nonce_distance\r\n * x,y valid tag nonces, then prng_successor(x, nonce_distance(x, y)) = y\r\n */\r\nstatic uint16_t *dist = 0;\r\nint nonce_distance(uint32_t from, uint32_t to)\r\n{\r\n\tuint16_t x, i;\r\n\tif(!dist) {\r\n\t\tdist = malloc(2 << 16);\r\n\t\tif(!dist)\r\n\t\t\treturn -1;\r\n\t\tfor (x = i = 1; i; ++i) {\r\n\t\t\tdist[(x & 0xff) << 8 | x >> 8] = i;\r\n\t\t\tx = x >> 1 | (x ^ x >> 2 ^ x >> 3 ^ x >> 5) << 15;\r\n\t\t}\r\n\t}\r\n\treturn (65535 + dist[to >> 16] - dist[from >> 16]) % 65535;\r\n}\r\n\r\n\r\nstatic uint32_t fastfwd[2][8] = {\r\n\t{ 0, 0x4BC53, 0xECB1, 0x450E2, 0x25E29, 0x6E27A, 0x2B298, 0x60ECB},\r\n\t{ 0, 0x1D962, 0x4BC53, 0x56531, 0xECB1, 0x135D3, 0x450E2, 0x58980}};\r\n/** lfsr_prefix_ks\r\n *\r\n * Is an exported helper function from the common prefix attack\r\n * Described in the \"dark side\" paper. It returns an -1 terminated array\r\n * of possible partial(21 bit) secret state.\r\n * The required keystream(ks) needs to contain the keystream that was used to\r\n * encrypt the NACK which is observed when varying only the 3 last bits of Nr\r\n * only correct iff [NR_3] ^ NR_3 does not depend on Nr_3\r\n */\r\nuint32_t *lfsr_prefix_ks(uint8_t ks[8], int isodd)\r\n{\r\n\tuint32_t c, entry, *candidates = malloc(4 << 10);\r\n\tint i, size = 0, good;\r\n\r\n\tif(!candidates)\r\n\t\treturn 0;\r\n\r\n\tfor(i = 0; i < 1 << 21; ++i) {\r\n\t\tfor(c = 0, good = 1; good && c < 8; ++c) {\r\n\t\t\tentry = i ^ fastfwd[isodd][c];\r\n\t\t\tgood &= (BIT(ks[c], isodd) == filter(entry >> 1));\r\n\t\t\tgood &= (BIT(ks[c], isodd + 2) == filter(entry));\r\n\t\t}\r\n\t\tif(good)\r\n\t\t\tcandidates[size++] = i;\r\n\t}\r\n\r\n\tcandidates[size] = -1;\r\n\r\n\treturn candidates;\r\n}\r\n\r\n/** check_pfx_parity\r\n * helper function which eliminates possible secret states using parity bits\r\n */\r\nstatic struct Crypto1State*\r\ncheck_pfx_parity(uint32_t prefix, uint32_t rresp, uint8_t parities[8][8],\r\n \tuint32_t odd, uint32_t even, struct Crypto1State* sl)\r\n{\r\n\tuint32_t ks1, nr, ks2, rr, ks3, c, good = 1;\r\n\r\n\tfor(c = 0; good && c < 8; ++c) {\r\n\t\tsl->odd = odd ^ fastfwd[1][c];\r\n\t\tsl->even = even ^ fastfwd[0][c];\r\n\r\n\t\tlfsr_rollback_bit(sl, 0, 0);\r\n\t\tlfsr_rollback_bit(sl, 0, 0);\r\n\r\n\t\tks3 = lfsr_rollback_bit(sl, 0, 0);\r\n\t\tks2 = lfsr_rollback_word(sl, 0, 0);\r\n\t\tks1 = lfsr_rollback_word(sl, prefix | c << 5, 1);\r\n\r\n\t\tnr = ks1 ^ (prefix | c << 5);\r\n\t\trr = ks2 ^ rresp;\r\n\r\n\t\tgood &= parity(nr & 0x000000ff) ^ parities[c][3] ^ BIT(ks2, 24);\r\n\t\tgood &= parity(rr & 0xff000000) ^ parities[c][4] ^ BIT(ks2, 16);\r\n\t\tgood &= parity(rr & 0x00ff0000) ^ parities[c][5] ^ BIT(ks2, 8);\r\n\t\tgood &= parity(rr & 0x0000ff00) ^ parities[c][6] ^ BIT(ks2, 0);\r\n\t\tgood &= parity(rr & 0x000000ff) ^ parities[c][7] ^ ks3;\r\n\t}\r\n\r\n\treturn sl + good;\r\n} \r\n\r\n\r\n/** lfsr_common_prefix\r\n * Implentation of the common prefix attack.\r\n */\r\nstruct Crypto1State*\r\nlfsr_common_prefix(uint32_t pfx, uint32_t rr, uint8_t ks[8], uint8_t par[8][8])\r\n{\r\n\tstruct Crypto1State *statelist, *s;\r\n\tuint32_t *odd, *even, *o, *e, top;\r\n\r\n\todd = lfsr_prefix_ks(ks, 1);\r\n\teven = lfsr_prefix_ks(ks, 0);\r\n\r\n\ts = statelist = malloc((sizeof *statelist) << 20);\r\n\tif(!s || !odd || !even) {\r\n\t\tfree(statelist);\r\n\t\tstatelist = 0;\r\n goto out;\r\n\t}\r\n\r\n\tfor(o = odd; *o + 1; ++o)\r\n\t\tfor(e = even; *e + 1; ++e)\r\n\t\t\tfor(top = 0; top < 64; ++top) {\r\n\t\t\t\t*o += 1 << 21;\r\n\t\t\t\t*e += (!(top & 7) + 1) << 21;\r\n\t\t\t\ts = check_pfx_parity(pfx, rr, par, *o, *e, s);\r\n\t\t\t}\r\n\r\n\ts->odd = s->even = 0;\r\nout:\r\n\tfree(odd);\r\n\tfree(even);\r\n\treturn statelist;\r\n}\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/crapto1.h", "content": "/* crapto1.h\n\n This program is free software; you can redistribute it and/or\n modify it under the terms of the GNU General Public License\n as published by the Free Software Foundation; either version 2\n of the License, or (at your option) any later version.\n\n This program is distributed in the hope that it will be useful,\n but WITHOUT ANY WARRANTY; without even the implied warranty of\n MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n GNU General Public License for more details.\n\n You should have received a copy of the GNU General Public License\n along with this program; if not, write to the Free Software\n Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,\n MA 02110-1301, US$\n\n Copyright (C) 2008-2008 bla \n*/\n#ifndef CRAPTO1_INCLUDED\n#define CRAPTO1_INCLUDED\n#include \n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nstruct Crypto1State {uint32_t odd, even;};\nvoid crypto1_create(struct Crypto1State *s, uint64_t key);\nvoid crypto1_destroy(struct Crypto1State*);\nvoid crypto1_get_lfsr(struct Crypto1State*, uint64_t*);\nuint8_t crypto1_bit(struct Crypto1State*, uint8_t, int);\nuint8_t crypto1_byte(struct Crypto1State*, uint8_t, int);\nuint32_t crypto1_word(struct Crypto1State*, uint32_t, int);\nuint32_t prng_successor(uint32_t x, uint32_t n);\n\nstruct Crypto1State* lfsr_recovery32(uint32_t ks2, uint32_t in);\nstruct Crypto1State* lfsr_recovery64(uint32_t ks2, uint32_t ks3);\nuint32_t *lfsr_prefix_ks(uint8_t ks[8], int isodd);\nstruct Crypto1State*\nlfsr_common_prefix(uint32_t pfx, uint32_t rr, uint8_t ks[8], uint8_t par[8][8]);\n\nuint8_t lfsr_rollback_bit(struct Crypto1State* s, uint32_t in, int fb);\nuint8_t lfsr_rollback_byte(struct Crypto1State* s, uint32_t in, int fb);\nuint32_t lfsr_rollback_word(struct Crypto1State* s, uint32_t in, int fb);\nint nonce_distance(uint32_t from, uint32_t to);\n#define FOREACH_VALID_NONCE(N, FILTER, FSIZE)\\\n\tuint32_t __n = 0,__M = 0, N = 0;\\\n\tint __i;\\\n\tfor(; __n < 1 << 16; N = prng_successor(__M = ++__n, 16))\\\n\t\tfor(__i = FSIZE - 1; __i >= 0; __i--)\\\n\t\t\tif(BIT(FILTER, __i) ^ parity(__M & 0xFF01))\\\n\t\t\t\tbreak;\\\n\t\t\telse if(__i)\\\n\t\t\t\t__M = prng_successor(__M, (__i == 7) ? 48 : 8);\\\n\t\t\telse \n\n#define LF_POLY_ODD (0x29CE5C)\n#define LF_POLY_EVEN (0x870804)\n#define BIT(x, n) ((x) >> (n) & 1)\n#define BEBIT(x, n) BIT(x, (n) ^ 24)\nstatic inline int parity(uint32_t x)\n{\n#if !defined __i386__ || !defined __GNUC__\n\tx ^= x >> 16;\n\tx ^= x >> 8;\n\tx ^= x >> 4;\n\treturn BIT(0x6996, x & 0xf);\n#else\n asm( \"movl %1, %%eax\\n\"\n\t\t\"mov %%ax, %%cx\\n\"\n\t\t\"shrl $0x10, %%eax\\n\"\n\t\t\"xor %%ax, %%cx\\n\"\n \"xor %%ch, %%cl\\n\"\n \"setpo %%al\\n\"\n \"movzx %%al, %0\\n\": \"=r\"(x) : \"r\"(x): \"eax\",\"ecx\");\n\treturn x;\n#endif\n}\nstatic inline int filter(uint32_t const x)\n{\n\tuint32_t f;\n\n\tf = 0xf22c0 >> (x & 0xf) & 16;\n\tf |= 0x6c9c0 >> (x >> 4 & 0xf) & 8;\n\tf |= 0x3c8b0 >> (x >> 8 & 0xf) & 4;\n\tf |= 0x1e458 >> (x >> 12 & 0xf) & 2;\n\tf |= 0x0d938 >> (x >> 16 & 0xf) & 1;\n\treturn BIT(0xEC57E80A, f);\n}\n#ifdef __cplusplus\n}\n#endif\n#endif\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/crypto1.c", "content": "/* crypto1.c\n\n This program is free software; you can redistribute it and/or\n modify it under the terms of the GNU General Public License\n as published by the Free Software Foundation; either version 2\n of the License, or (at your option) any later version.\n\n This program is distributed in the hope that it will be useful,\n but WITHOUT ANY WARRANTY; without even the implied warranty of\n MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n GNU General Public License for more details.\n\n You should have received a copy of the GNU General Public License\n along with this program; if not, write to the Free Software\n Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,\n MA 02110-1301, US\n\n Copyright (C) 2008-2008 bla \n*/\n#include \"crapto1.h\"\n#include \n\n#define SWAPENDIAN(x)\\\n\t(x = (x >> 8 & 0xff00ff) | (x & 0xff00ff) << 8, x = x >> 16 | x << 16)\n\nvoid crypto1_create(struct Crypto1State *s, uint64_t key)\n{\n//\tstruct Crypto1State *s = malloc(sizeof(*s));\n\tint i;\n\n\tfor(i = 47;s && i > 0; i -= 2) {\n\t\ts->odd = s->odd << 1 | BIT(key, (i - 1) ^ 7);\n\t\ts->even = s->even << 1 | BIT(key, i ^ 7);\n\t}\n\treturn;\n}\nvoid crypto1_destroy(struct Crypto1State *state)\n{\n//\tfree(state);\n state->odd = 0;\n state->even = 0;\n}\nvoid crypto1_get_lfsr(struct Crypto1State *state, uint64_t *lfsr)\n{\n\tint i;\n\tfor(*lfsr = 0, i = 23; i >= 0; --i) {\n\t\t*lfsr = *lfsr << 1 | BIT(state->odd, i ^ 3);\n\t\t*lfsr = *lfsr << 1 | BIT(state->even, i ^ 3);\n\t}\n}\nuint8_t crypto1_bit(struct Crypto1State *s, uint8_t in, int is_encrypted)\n{\n\tuint32_t feedin;\n\tuint8_t ret = filter(s->odd);\n\n\tfeedin = ret & !!is_encrypted;\n\tfeedin ^= !!in;\n\tfeedin ^= LF_POLY_ODD & s->odd;\n\tfeedin ^= LF_POLY_EVEN & s->even;\n\ts->even = s->even << 1 | parity(feedin);\n\n\ts->odd ^= (s->odd ^= s->even, s->even ^= s->odd);\n\n\treturn ret;\n}\nuint8_t crypto1_byte(struct Crypto1State *s, uint8_t in, int is_encrypted)\n{\n\tuint8_t i, ret = 0;\n\n\tfor (i = 0; i < 8; ++i)\n\t\tret |= crypto1_bit(s, BIT(in, i), is_encrypted) << i;\n\n\treturn ret;\n}\nuint32_t crypto1_word(struct Crypto1State *s, uint32_t in, int is_encrypted)\n{\n\tuint32_t i, ret = 0;\n\n\tfor (i = 0; i < 32; ++i)\n\t\tret |= crypto1_bit(s, BEBIT(in, i), is_encrypted) << (i ^ 24);\n\n\treturn ret;\n}\n\n/* prng_successor\n * helper used to obscure the keystream during authentication\n */\nuint32_t prng_successor(uint32_t x, uint32_t n)\n{\n\tSWAPENDIAN(x);\n\twhile(n--)\n\t\tx = x >> 1 | (x >> 16 ^ x >> 18 ^ x >> 19 ^ x >> 21) << 31;\n\n\treturn SWAPENDIAN(x);\n}\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/epa.c", "content": "//-----------------------------------------------------------------------------\n// Frederik Möllers - August 2012\n//\n// This code is licensed to you under the terms of the GNU GPL, version 2 or,\n// at your option, any later version. See the LICENSE.txt file for the text of\n// the license.\n//-----------------------------------------------------------------------------\n// Routines to support the German eletronic \"Personalausweis\" (ID card)\n// Note that the functions which do not implement USB commands do NOT initialize\n// the card (with iso14443a_select_card etc.). If You want to use these\n// functions, You need to do the setup before calling them!\n//-----------------------------------------------------------------------------\n\n#include \"iso14443a.h\"\n#include \"epa.h\"\n#include \"cmd.h\"\n\n// Protocol and Parameter Selection Request\n// use regular (1x) speed in both directions\n// CRC is already included\nstatic const uint8_t pps[] = {0xD0, 0x11, 0x00, 0x52, 0xA6};\n\n// APDUs for communication with German Identification Card\n\n// General Authenticate (request encrypted nonce) WITHOUT the Le at the end\nstatic const uint8_t apdu_general_authenticate_pace_get_nonce[] = {\n\t0x10, // CLA\n\t0x86, // INS\n\t0x00, // P1\n\t0x00, // P2\n\t0x02, // Lc\n\t0x7C, // Type: Dynamic Authentication Data\n\t0x00, // Length: 0 bytes\n};\n\n// MSE: Set AT (only CLA, INS, P1 and P2)\nstatic const uint8_t apdu_mse_set_at_start[] = {\n\t0x00, // CLA\n\t0x22, // INS\n\t0xC1, // P1\n\t0xA4, // P2\n};\n\n// SELECT BINARY with the ID for EF.CardAccess\nstatic const uint8_t apdu_select_binary_cardaccess[] = {\n\t0x00, // CLA\n\t0xA4, // INS\n\t0x02, // P1\n\t0x0C, // P2\n\t0x02, // Lc\n\t0x01, // ID\n\t0x1C // ID\n};\n\n// READ BINARY\nstatic const uint8_t apdu_read_binary[] = {\n\t0x00, // CLA\n\t0xB0, // INS\n\t0x00, // P1\n\t0x00, // P2\n\t0x38 // Le\n};\n\n\n// the leading bytes of a PACE OID\nstatic const uint8_t oid_pace_start[] = {\n 0x04, // itu-t, identified-organization\n 0x00, // etsi\n 0x7F, // reserved\n 0x00, // etsi-identified-organization\n 0x07, // bsi-de\n 0x02, // protocols\n 0x02, // smartcard\n 0x04 // id-PACE\n};\n\n//-----------------------------------------------------------------------------\n// Closes the communication channel and turns off the field\n//-----------------------------------------------------------------------------\nvoid EPA_Finish()\n{\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\n\tLEDsoff();\n}\n\n//-----------------------------------------------------------------------------\n// Parses DER encoded data, e.g. from EF.CardAccess and fills out the given\n// structs. If a pointer is 0, it is ignored.\n// The function returns 0 on success and if an error occured, it returns the\n// offset where it occured.\n//\n// TODO: This function can access memory outside of the given data if the DER\n// encoding is broken\n// TODO: Support skipping elements with a length > 0x7F\n// TODO: Support OIDs with a length > 7F\n// TODO: Support elements with long tags (tag is longer than 1 byte)\n// TODO: Support proprietary PACE domain parameters\n//-----------------------------------------------------------------------------\nsize_t EPA_Parse_CardAccess(uint8_t *data,\n size_t length,\n pace_version_info_t *pace_info)\n{\n\tsize_t index = 0;\n\t\n\twhile (index <= length - 2) {\n\t\t// determine type of element\n\t\t// SET or SEQUENCE\n\t\tif (data[index] == 0x31 || data[index] == 0x30) {\n\t\t\t// enter the set (skip tag + length)\n\t\t\tindex += 2;\n\t\t\t// extended length\n\t\t\tif ((data[index - 1] & 0x80) != 0) {\n\t\t\t\tindex += (data[index] & 0x7F);\n\t\t\t}\n\t\t}\n\t\t// OID\n\t\telse if (data[index] == 0x06) {\n\t\t\t// is this a PACE OID?\n\t\t\tif (data[index + 1] == 0x0A // length matches\n\t\t\t && memcmp(data + index + 2,\n\t\t\t oid_pace_start,\n\t\t\t sizeof(oid_pace_start)) == 0 // content matches\n\t\t\t && pace_info != NULL)\n\t\t\t{\n\t\t\t\t// first, clear the pace_info struct\n\t\t\t\tmemset(pace_info, 0, sizeof(pace_version_info_t));\n\t\t\t\tmemcpy(pace_info->oid, data + index + 2, sizeof(pace_info->oid));\n\t\t\t\t// a PACE OID is followed by the version\n\t\t\t\tindex += data[index + 1] + 2;\n\t\t\t\tif (data[index] == 02 && data[index + 1] == 01) {\n\t\t\t\t\tpace_info->version = data[index + 2];\n\t\t\t\t\tindex += 3;\n\t\t\t\t}\n\t\t\t\telse {\n\t\t\t\t\treturn index;\n\t\t\t\t}\n\t\t\t\t// after that there might(!) be the parameter ID\n\t\t\t\tif (data[index] == 02 && data[index + 1] == 01) {\n\t\t\t\t\tpace_info->parameter_id = data[index + 2];\n\t\t\t\t\tindex += 3;\n\t\t\t\t}\n\t\t\t}\n\t\t\telse {\n\t\t\t\t// skip this OID\n\t\t\t\tindex += 2 + data[index + 1];\n\t\t\t}\n\t\t}\n\t\t// if the length is 0, something is wrong\n\t\t// TODO: This needs to be extended to support long tags\n\t\telse if (data[index + 1] == 0) {\n\t\t\treturn index;\n\t\t}\n\t\telse {\n\t\t\t// skip this part\n\t\t\t// TODO: This needs to be extended to support long tags\n\t\t\t// TODO: This needs to be extended to support unknown elements with\n\t\t\t// a size > 0x7F\n\t\t\tindex += 2 + data[index + 1];\n\t\t}\n\t}\n\t\n\t// TODO: We should check whether we reached the end in error, but for that\n\t// we need a better parser (e.g. with states like IN_SET or IN_PACE_INFO)\n\treturn 0;\n}\n\n//-----------------------------------------------------------------------------\n// Read the file EF.CardAccess and save it into a buffer (at most max_length bytes)\n// Returns -1 on failure or the length of the data on success\n// TODO: for the moment this sends only 1 APDU regardless of the requested length\n//-----------------------------------------------------------------------------\nint EPA_Read_CardAccess(uint8_t *buffer, size_t max_length)\n{\n\t// the response APDU of the card\n\t// since the card doesn't always care for the expected length we send it,\n\t// we reserve 262 bytes here just to be safe (256-byte APDU + SW + ISO frame)\n\tuint8_t response_apdu[262];\n\tint rapdu_length = 0;\n\t\n\t// select the file EF.CardAccess\n\trapdu_length = iso14_apdu((uint8_t *)apdu_select_binary_cardaccess,\n\t sizeof(apdu_select_binary_cardaccess),\n\t response_apdu);\n\tif (rapdu_length != 6\n\t || response_apdu[rapdu_length - 4] != 0x90\n\t || response_apdu[rapdu_length - 3] != 0x00)\n\t{\n\t\treturn -1;\n\t}\n\t\n\t// read the file\n\trapdu_length = iso14_apdu((uint8_t *)apdu_read_binary,\n\t sizeof(apdu_read_binary),\n\t response_apdu);\n\tif (rapdu_length <= 6\n\t || response_apdu[rapdu_length - 4] != 0x90\n\t || response_apdu[rapdu_length - 3] != 0x00)\n\t{\n\t\treturn -1;\n\t}\n\t\n\t// copy the content into the buffer\n\t// length of data available: apdu_length - 4 (ISO frame) - 2 (SW)\n\tsize_t to_copy = rapdu_length - 6;\n\tto_copy = to_copy < max_length ? to_copy : max_length;\n\tmemcpy(buffer, response_apdu+2, to_copy);\n\treturn to_copy;\n}\n\n//-----------------------------------------------------------------------------\n// Abort helper function for EPA_PACE_Collect_Nonce\n// sets relevant data in ack, sends the response\n//-----------------------------------------------------------------------------\nstatic void EPA_PACE_Collect_Nonce_Abort(uint8_t step, int func_return)\n{\n//\t// step in which the failure occured\n//\tack->arg[0] = step;\n//\t// last return code\n//\tack->arg[1] = func_return;\n\n\t// power down the field\n\tEPA_Finish();\n\t\n\t// send the USB packet\n cmd_send(CMD_ACK,step,func_return,0,0,0);\n//UsbSendPacket((void *)ack, sizeof(UsbCommand));\n}\n\n//-----------------------------------------------------------------------------\n// Acquire one encrypted PACE nonce\n//-----------------------------------------------------------------------------\nvoid EPA_PACE_Collect_Nonce(UsbCommand *c)\n{\n\t/*\n\t * ack layout:\n\t * \targ:\n\t * \t\t1. element\n\t * step where the error occured or 0 if no error occured\n * 2. element\n * return code of the last executed function\n\t * \td:\n\t * \t\tEncrypted nonce\n\t */\n\n\t// return value of a function\n\tint func_return;\n\n//\t// initialize ack with 0s\n//\tmemset(ack->arg, 0, 12);\n//\tmemset(ack->d.asBytes, 0, 48);\n\t\n\t// set up communication\n\tfunc_return = EPA_Setup();\n\tif (func_return != 0) {\n\t\tEPA_PACE_Collect_Nonce_Abort(1, func_return);\n\t\treturn;\n\t}\n\n\t// increase the timeout (at least some cards really do need this!)\n\tiso14a_set_timeout(0x0002FFFF);\n\t\n\t// read the CardAccess file\n\t// this array will hold the CardAccess file\n\tuint8_t card_access[256] = {0};\n\tint card_access_length = EPA_Read_CardAccess(card_access, 256);\n\t// the response has to be at least this big to hold the OID\n\tif (card_access_length < 18) {\n\t\tEPA_PACE_Collect_Nonce_Abort(2, card_access_length);\n\t\treturn;\n\t}\n\n\t// this will hold the PACE info of the card\n\tpace_version_info_t pace_version_info;\n\t// search for the PACE OID\n\tfunc_return = EPA_Parse_CardAccess(card_access,\n\t card_access_length,\n\t &pace_version_info);\n\tif (func_return != 0 || pace_version_info.version == 0) {\n\t\tEPA_PACE_Collect_Nonce_Abort(3, func_return);\n\t\treturn;\n\t}\n\t\n\t// initiate the PACE protocol\n\t// use the CAN for the password since that doesn't change\n\tfunc_return = EPA_PACE_MSE_Set_AT(pace_version_info, 2);\n\t\n\t// now get the nonce\n\tuint8_t nonce[256] = {0};\n\tuint8_t requested_size = (uint8_t)c->arg[0];\n\tfunc_return = EPA_PACE_Get_Nonce(requested_size, nonce);\n\t// check if the command succeeded\n\tif (func_return < 0)\n\t{\n\t\tEPA_PACE_Collect_Nonce_Abort(4, func_return);\n\t\treturn;\n\t}\n \n // all done, return\n\tEPA_Finish();\n\t\n\t// save received information\n//\tack->arg[1] = func_return;\n//\tmemcpy(ack->d.asBytes, nonce, func_return);\n//\tUsbSendPacket((void *)ack, sizeof(UsbCommand));\n cmd_send(CMD_ACK,0,func_return,0,nonce,func_return);\n}\n\n//-----------------------------------------------------------------------------\n// Performs the \"Get Nonce\" step of the PACE protocol and saves the returned\n// nonce. The caller is responsible for allocating enough memory to store the\n// nonce. Note that the returned size might be less or than or greater than the\n// requested size!\n// Returns the actual size of the nonce on success or a less-than-zero error\n// code on failure.\n//-----------------------------------------------------------------------------\nint EPA_PACE_Get_Nonce(uint8_t requested_length, uint8_t *nonce)\n{\n\t// build the APDU\n\tuint8_t apdu[sizeof(apdu_general_authenticate_pace_get_nonce) + 1];\n\t// copy the constant part\n\tmemcpy(apdu,\n\t apdu_general_authenticate_pace_get_nonce,\n\t sizeof(apdu_general_authenticate_pace_get_nonce));\n\t// append Le (requested length + 2 due to tag/length taking 2 bytes) in RAPDU\n\tapdu[sizeof(apdu_general_authenticate_pace_get_nonce)] = requested_length + 4;\n\t\n\t// send it\n\tuint8_t response_apdu[262];\n\tint send_return = iso14_apdu(apdu,\n\t sizeof(apdu),\n\t response_apdu);\n\t// check if the command succeeded\n\tif (send_return < 6\n\t\t|| response_apdu[send_return - 4] != 0x90\n\t\t|| response_apdu[send_return - 3] != 0x00)\n\t{\n\t\treturn -1;\n\t}\n\t\n\t// if there is no nonce in the RAPDU, return here\n\tif (send_return < 10)\n\t{\n\t\t// no error\n\t\treturn 0;\n\t}\n\t// get the actual length of the nonce\n\tuint8_t nonce_length = response_apdu[5];\n\tif (nonce_length > send_return - 10)\n\t{\n\t\tnonce_length = send_return - 10;\n\t}\n\t// copy the nonce\n\tmemcpy(nonce, response_apdu + 6, nonce_length);\n\t\n\treturn nonce_length;\n}\n\n//-----------------------------------------------------------------------------\n// Initializes the PACE protocol by performing the \"MSE: Set AT\" step\n// Returns 0 on success or a non-zero error code on failure\n//-----------------------------------------------------------------------------\nint EPA_PACE_MSE_Set_AT(pace_version_info_t pace_version_info, uint8_t password)\n{\n\t// create the MSE: Set AT APDU\n\tuint8_t apdu[23];\n\t// the minimum length (will be increased as more data is added)\n\tsize_t apdu_length = 20;\n\t// copy the constant part\n\tmemcpy(apdu,\n\t apdu_mse_set_at_start,\n\t sizeof(apdu_mse_set_at_start));\n\t// type: OID\n\tapdu[5] = 0x80;\n\t// length of the OID\n\tapdu[6] = sizeof(pace_version_info.oid);\n\t// copy the OID\n\tmemcpy(apdu + 7,\n\t pace_version_info.oid,\n\t sizeof(pace_version_info.oid));\n\t// type: password\n\tapdu[17] = 0x83;\n\t// length: 1\n\tapdu[18] = 1;\n\t// password\n\tapdu[19] = password;\n\t// if standardized domain parameters are used, copy the ID\n\tif (pace_version_info.parameter_id != 0) {\n\t\tapdu_length += 3;\n\t\t// type: domain parameter\n\t\tapdu[20] = 0x84;\n\t\t// length: 1\n\t\tapdu[21] = 1;\n\t\t// copy the parameter ID\n\t\tapdu[22] = pace_version_info.parameter_id;\n\t}\n\t// now set Lc to the actual length\n\tapdu[4] = apdu_length - 5;\n\t// send it\n\tuint8_t response_apdu[6];\n\tint send_return = iso14_apdu(apdu,\n\t apdu_length,\n\t response_apdu);\n\t// check if the command succeeded\n\tif (send_return != 6\n\t\t|| response_apdu[send_return - 4] != 0x90\n\t\t|| response_apdu[send_return - 3] != 0x00)\n\t{\n\t\treturn 1;\n\t}\n\treturn 0;\n}\n\n//-----------------------------------------------------------------------------\n// Set up a communication channel (Card Select, PPS)\n// Returns 0 on success or a non-zero error code on failure\n//-----------------------------------------------------------------------------\nint EPA_Setup()\n{\n\t// return code\n\tint return_code = 0;\n\t// card UID\n\tuint8_t uid[8];\n\t// card select information\n\tiso14a_card_select_t card_select_info;\n\t// power up the field\n\tiso14443a_setup();\n\n\t// select the card\n\treturn_code = iso14443a_select_card(uid, &card_select_info, NULL);\n\tif (return_code != 1) {\n\t\treturn 1;\n\t}\n\n\t// send the PPS request\n\tReaderTransmit((uint8_t *)pps, sizeof(pps));\n\tuint8_t pps_response[3];\n\treturn_code = ReaderReceive(pps_response);\n\tif (return_code != 3 || pps_response[0] != 0xD0) {\n\t\treturn return_code == 0 ? 2 : return_code;\n\t}\n\t\n\treturn 0;\n}" }, { "path": "TamagotchiFriends/proxmark/armsrc/epa.h", "content": "//-----------------------------------------------------------------------------\n// Frederik Möllers - August 2012\n//\n// This code is licensed to you under the terms of the GNU GPL, version 2 or,\n// at your option, any later version. See the LICENSE.txt file for the text of\n// the license.\n//-----------------------------------------------------------------------------\n// Routines to support the German eletronic \"Personalausweis\" (ID card)\n//-----------------------------------------------------------------------------\n\n#ifndef __EPA_H\n#define __EPA_H\n\n// this struct is used by EPA_Parse_CardAccess and contains info about the\n// PACE protocol supported by the chip\ntypedef struct {\n\tuint8_t oid[10];\n\tuint8_t version;\n\tuint8_t parameter_id;\n} pace_version_info_t;\n\n// note: EPA_PACE_GetNonce is declared in apps.h\n\n// general functions\nvoid EPA_Finish();\nsize_t EPA_Parse_CardAccess(uint8_t *data,\n size_t length,\n pace_version_info_t *pace_info);\nint EPA_Read_CardAccess(uint8_t *buffer, size_t max_length);\nint EPA_Setup();\n\n// PACE related functions\nint EPA_PACE_MSE_Set_AT(pace_version_info_t pace_version_info, uint8_t password);\nint EPA_PACE_Get_Nonce(uint8_t requested_length, uint8_t *nonce);\n\n#endif /* __EPA_H */" }, { "path": "TamagotchiFriends/proxmark/armsrc/fonts.c", "content": "//-----------------------------------------------------------------------------\r\n// This code is licensed to you under the terms of the GNU GPL, version 2 or,\r\n// at your option, any later version. See the LICENSE.txt file for the text of\r\n// the license.\r\n//-----------------------------------------------------------------------------\r\n// Fonts for the LCD\r\n//-----------------------------------------------------------------------------\r\n\r\nconst char FONT6x8[97][8] = {\r\n\t{0x06,0x08,0x08,0x00,0x00,0x00,0x00,0x00},\t// columns, rows, bytes per char\r\n\t{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},\t// space\r\n\t{0x20,0x20,0x20,0x20,0x20,0x00,0x20,0x00},\t// !\r\n\t{0x50,0x50,0x50,0x00,0x00,0x00,0x00,0x00},\t// \"\r\n\t{0x50,0x50,0xF8,0x50,0xF8,0x50,0x50,0x00},\t// #\r\n\t{0x20,0x78,0xA0,0x70,0x28,0xF0,0x20,0x00},\t// $\r\n\t{0xC0,0xC8,0x10,0x20,0x40,0x98,0x18,0x00},\t// %\r\n\t{0x40,0xA0,0xA0,0x40,0xA8,0x90,0x68,0x00},\t// &\r\n\t{0x30,0x30,0x20,0x40,0x00,0x00,0x00,0x00},\t// '\r\n\t{0x10,0x20,0x40,0x40,0x40,0x20,0x10,0x00},\t// (\r\n\t{0x40,0x20,0x10,0x10,0x10,0x20,0x40,0x00},\t// )\r\n\t{0x00,0x20,0xA8,0x70,0x70,0xA8,0x20,0x00},\t// *\r\n\t{0x00,0x20,0x20,0xF8,0x20,0x20,0x00,0x00},\t// +\r\n\t{0x00,0x00,0x00,0x00,0x30,0x30,0x20,0x40},\t// ,\r\n\t{0x00,0x00,0x00,0xF8,0x00,0x00,0x00,0x00},\t// -\r\n\t{0x00,0x00,0x00,0x00,0x00,0x30,0x30,0x00},\t// .\r\n\t{0x00,0x08,0x10,0x20,0x40,0x80,0x00,0x00},\t// /\r\n\t{0x70,0x88,0x88,0xA8,0x88,0x88,0x70,0x00},\t// 0\r\n\t{0x20,0x60,0x20,0x20,0x20,0x20,0x70,0x00},\t// 1\r\n\t{0x70,0x88,0x08,0x70,0x80,0x80,0xF8,0x00},\t// 2\r\n\t{0xF8,0x08,0x10,0x30,0x08,0x88,0x70,0x00},\t// 3\r\n\t{0x10,0x30,0x50,0x90,0xF8,0x10,0x10,0x00},\t// 4\r\n\t{0xF8,0x80,0xF0,0x08,0x08,0x88,0x70,0x00},\t// 5\r\n\t{0x38,0x40,0x80,0xF0,0x88,0x88,0x70,0x00},\t// 6\r\n\t{0xF8,0x08,0x08,0x10,0x20,0x40,0x80,0x00},\t// 7\r\n\t{0x70,0x88,0x88,0x70,0x88,0x88,0x70,0x00},\t// 8\r\n\t{0x70,0x88,0x88,0x78,0x08,0x10,0xE0,0x00},\t// 9\r\n\t{0x00,0x00,0x20,0x00,0x20,0x00,0x00,0x00},\t// :\r\n\t{0x00,0x00,0x20,0x00,0x20,0x20,0x40,0x00},\t// ;\r\n\t{0x08,0x10,0x20,0x40,0x20,0x10,0x08,0x00},\t// <\r\n\t{0x00,0x00,0xF8,0x00,0xF8,0x00,0x00,0x00},\t// =\r\n\t{0x40,0x20,0x10,0x08,0x10,0x20,0x40,0x00},\t// >\r\n\t{0x70,0x88,0x08,0x30,0x20,0x00,0x20,0x00},\t// ?\r\n\t{0x70,0x88,0xA8,0xB8,0xB0,0x80,0x78,0x00},\t// @\r\n\t{0x20,0x50,0x88,0x88,0xF8,0x88,0x88,0x00},\t// A\r\n\t{0xF0,0x88,0x88,0xF0,0x88,0x88,0xF0,0x00},\t// B\r\n\t{0x70,0x88,0x80,0x80,0x80,0x88,0x70,0x00},\t// C\r\n\t{0xF0,0x88,0x88,0x88,0x88,0x88,0xF0,0x00},\t// D\r\n\t{0xF8,0x80,0x80,0xF0,0x80,0x80,0xF8,0x00},\t// E\r\n\t{0xF8,0x80,0x80,0xF0,0x80,0x80,0x80,0x00},\t// F\r\n\t{0x78,0x88,0x80,0x80,0x98,0x88,0x78,0x00},\t// G\r\n\t{0x88,0x88,0x88,0xF8,0x88,0x88,0x88,0x00},\t// H\r\n\t{0x70,0x20,0x20,0x20,0x20,0x20,0x70,0x00},\t// I\r\n\t{0x38,0x10,0x10,0x10,0x10,0x90,0x60,0x00},\t// J\r\n\t{0x88,0x90,0xA0,0xC0,0xA0,0x90,0x88,0x00},\t// K\r\n\t{0x80,0x80,0x80,0x80,0x80,0x80,0xF8,0x00},\t// L\r\n\t{0x88,0xD8,0xA8,0xA8,0xA8,0x88,0x88,0x00},\t// M\r\n\t{0x88,0x88,0xC8,0xA8,0x98,0x88,0x88,0x00},\t// N\r\n\t{0x70,0x88,0x88,0x88,0x88,0x88,0x70,0x00},\t// O\r\n\t{0xF0,0x88,0x88,0xF0,0x80,0x80,0x80,0x00},\t// P\r\n\t{0x70,0x88,0x88,0x88,0xA8,0x90,0x68,0x00},\t// Q\r\n\t{0xF0,0x88,0x88,0xF0,0xA0,0x90,0x88,0x00},\t// R\r\n\t{0x70,0x88,0x80,0x70,0x08,0x88,0x70,0x00},\t// S\r\n\t{0xF8,0xA8,0x20,0x20,0x20,0x20,0x20,0x00},\t// T\r\n\t{0x88,0x88,0x88,0x88,0x88,0x88,0x70,0x00},\t// U\r\n\t{0x88,0x88,0x88,0x88,0x88,0x50,0x20,0x00},\t// V\r\n\t{0x88,0x88,0x88,0xA8,0xA8,0xA8,0x50,0x00},\t// W\r\n\t{0x88,0x88,0x50,0x20,0x50,0x88,0x88,0x00},\t// X\r\n\t{0x88,0x88,0x50,0x20,0x20,0x20,0x20,0x00},\t// Y\r\n\t{0xF8,0x08,0x10,0x70,0x40,0x80,0xF8,0x00},\t// Z\r\n\t{0x78,0x40,0x40,0x40,0x40,0x40,0x78,0x00},\t// [\r\n\t{0x00,0x80,0x40,0x20,0x10,0x08,0x00,0x00},\t// backslash\r\n\t{0x78,0x08,0x08,0x08,0x08,0x08,0x78,0x00},\t// ]\r\n\t{0x20,0x50,0x88,0x00,0x00,0x00,0x00,0x00},\t// ^\r\n\t{0x00,0x00,0x00,0x00,0x00,0x00,0xF8,0x00},\t// _\r\n\t{0x60,0x60,0x20,0x10,0x00,0x00,0x00,0x00},\t// `\r\n\t{0x00,0x00,0x60,0x10,0x70,0x90,0x78,0x00},\t// a\r\n\t{0x80,0x80,0xB0,0xC8,0x88,0xC8,0xB0,0x00},\t// b\r\n\t{0x00,0x00,0x70,0x88,0x80,0x88,0x70,0x00},\t// c\r\n\t{0x08,0x08,0x68,0x98,0x88,0x98,0x68,0x00},\t// d\r\n\t{0x00,0x00,0x70,0x88,0xF8,0x80,0x70,0x00},\t// e\r\n\t{0x10,0x28,0x20,0x70,0x20,0x20,0x20,0x00},\t// f\r\n\t{0x00,0x00,0x70,0x98,0x98,0x68,0x08,0x70},\t// g\r\n\t{0x80,0x80,0xB0,0xC8,0x88,0x88,0x88,0x00},\t// h\r\n\t{0x20,0x00,0x60,0x20,0x20,0x20,0x70,0x00},\t// i\r\n\t{0x10,0x00,0x10,0x10,0x10,0x90,0x60,0x00},\t// j\r\n\t{0x80,0x80,0x90,0xA0,0xC0,0xA0,0x90,0x00},\t// k\r\n\t{0x60,0x20,0x20,0x20,0x20,0x20,0x70,0x00},\t// l\r\n\t{0x00,0x00,0xD0,0xA8,0xA8,0xA8,0xA8,0x00},\t// m\r\n\t{0x00,0x00,0xB0,0xC8,0x88,0x88,0x88,0x00},\t// n\r\n\t{0x00,0x00,0x70,0x88,0x88,0x88,0x70,0x00},\t// o\r\n\t{0x00,0x00,0xB0,0xC8,0xC8,0xB0,0x80,0x80},\t// p\r\n\t{0x00,0x00,0x68,0x98,0x98,0x68,0x08,0x08},\t// q\r\n\t{0x00,0x00,0xB0,0xC8,0x80,0x80,0x80,0x00},\t// r\r\n\t{0x00,0x00,0x78,0x80,0x70,0x08,0xF0,0x00},\t// s\r\n\t{0x20,0x20,0xF8,0x20,0x20,0x28,0x10,0x00},\t// t\r\n\t{0x00,0x00,0x88,0x88,0x88,0x98,0x68,0x00},\t// u\r\n\t{0x00,0x00,0x88,0x88,0x88,0x50,0x20,0x00},\t// v\r\n\t{0x00,0x00,0x88,0x88,0xA8,0xA8,0x50,0x00},\t// w\r\n\t{0x00,0x00,0x88,0x50,0x20,0x50,0x88,0x00},\t// x\r\n\t{0x00,0x00,0x88,0x88,0x78,0x08,0x88,0x70},\t// y\r\n\t{0x00,0x00,0xF8,0x10,0x20,0x40,0xF8,0x00},\t// z\r\n\t{0x10,0x20,0x20,0x40,0x20,0x20,0x10,0x00},\t// {\r\n\t{0x20,0x20,0x20,0x00,0x20,0x20,0x20,0x00},\t// |\r\n\t{0x40,0x20,0x20,0x10,0x20,0x20,0x40,0x00},\t// }\r\n\t{0x40,0xA8,0x10,0x00,0x00,0x00,0x00,0x00},\t// ~\r\n\t{0x70,0xD8,0xD8,0x70,0x00,0x00,0x00,0x00}\t// DEL\r\n};\r\n/*\r\nconst char FONT8x8F[97][8] = {\r\n\t{0x08,0x08,0x08,0x00,0x00,0x00,0x00,0x00},\t// columns, rows, bytes per char\r\n\t{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},\t// space\r\n\t{0x30,0x78,0x78,0x30,0x30,0x00,0x30,0x00},\t// !\r\n\t{0x6C,0x6C,0x6C,0x00,0x00,0x00,0x00,0x00},\t// \"\r\n\t{0x6C,0x6C,0xFE,0x6C,0xFE,0x6C,0x6C,0x00},\t// #\r\n\t{0x18,0x3E,0x60,0x3C,0x06,0x7C,0x18,0x00},\t// $\r\n\t{0x00,0x63,0x66,0x0C,0x18,0x33,0x63,0x00},\t// %\r\n\t{0x1C,0x36,0x1C,0x3B,0x6E,0x66,0x3B,0x00},\t// &\r\n\t{0x30,0x30,0x60,0x00,0x00,0x00,0x00,0x00},\t// '\r\n\t{0x0C,0x18,0x30,0x30,0x30,0x18,0x0C,0x00},\t// (\r\n\t{0x30,0x18,0x0C,0x0C,0x0C,0x18,0x30,0x00},\t// )\r\n\t{0x00,0x66,0x3C,0xFF,0x3C,0x66,0x00,0x00},\t// *\r\n\t{0x00,0x30,0x30,0xFC,0x30,0x30,0x00,0x00},\t// +\r\n\t{0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x30},\t// ,\r\n\t{0x00,0x00,0x00,0x7E,0x00,0x00,0x00,0x00},\t// -\r\n\t{0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00},\t// .\r\n\t{0x03,0x06,0x0C,0x18,0x30,0x60,0x40,0x00},\t// /\r\n\t{0x3E,0x63,0x63,0x6B,0x63,0x63,0x3E,0x00},\t// 0\r\n\t{0x18,0x38,0x58,0x18,0x18,0x18,0x7E,0x00},\t// 1\r\n\t{0x3C,0x66,0x06,0x1C,0x30,0x66,0x7E,0x00},\t// 2\r\n\t{0x3C,0x66,0x06,0x1C,0x06,0x66,0x3C,0x00},\t// 3\r\n\t{0x0E,0x1E,0x36,0x66,0x7F,0x06,0x0F,0x00},\t// 4\r\n\t{0x7E,0x60,0x7C,0x06,0x06,0x66,0x3C,0x00},\t// 5\r\n\t{0x1C,0x30,0x60,0x7C,0x66,0x66,0x3C,0x00},\t// 6\r\n\t{0x7E,0x66,0x06,0x0C,0x18,0x18,0x18,0x00},\t// 7\r\n\t{0x3C,0x66,0x66,0x3C,0x66,0x66,0x3C,0x00},\t// 8\r\n\t{0x3C,0x66,0x66,0x3E,0x06,0x0C,0x38,0x00},\t// 9\r\n\t{0x00,0x18,0x18,0x00,0x00,0x18,0x18,0x00},\t// :\r\n\t{0x00,0x18,0x18,0x00,0x00,0x18,0x18,0x30},\t// ;\r\n\t{0x0C,0x18,0x30,0x60,0x30,0x18,0x0C,0x00},\t// <\r\n\t{0x00,0x00,0x7E,0x00,0x00,0x7E,0x00,0x00},\t// =\r\n\t{0x30,0x18,0x0C,0x06,0x0C,0x18,0x30,0x00},\t// >\r\n\t{0x3C,0x66,0x06,0x0C,0x18,0x00,0x18,0x00},\t// ?\r\n\t{0x3E,0x63,0x6F,0x69,0x6F,0x60,0x3E,0x00},\t// @\r\n\t{0x18,0x3C,0x66,0x66,0x7E,0x66,0x66,0x00},\t// A\r\n\t{0x7E,0x33,0x33,0x3E,0x33,0x33,0x7E,0x00},\t// B\r\n\t{0x1E,0x33,0x60,0x60,0x60,0x33,0x1E,0x00},\t// C\r\n\t{0x7C,0x36,0x33,0x33,0x33,0x36,0x7C,0x00},\t// D\r\n\t{0x7F,0x31,0x34,0x3C,0x34,0x31,0x7F,0x00},\t// E\r\n\t{0x7F,0x31,0x34,0x3C,0x34,0x30,0x78,0x00},\t// F\r\n\t{0x1E,0x33,0x60,0x60,0x67,0x33,0x1F,0x00},\t// G\r\n\t{0x66,0x66,0x66,0x7E,0x66,0x66,0x66,0x00},\t// H\r\n\t{0x3C,0x18,0x18,0x18,0x18,0x18,0x3C,0x00},\t// I\r\n\t{0x0F,0x06,0x06,0x06,0x66,0x66,0x3C,0x00},\t// J\r\n\t{0x73,0x33,0x36,0x3C,0x36,0x33,0x73,0x00},\t// K\r\n\t{0x78,0x30,0x30,0x30,0x31,0x33,0x7F,0x00},\t// L\r\n\t{0x63,0x77,0x7F,0x7F,0x6B,0x63,0x63,0x00},\t// M\r\n\t{0x63,0x73,0x7B,0x6F,0x67,0x63,0x63,0x00},\t// N\r\n\t{0x3E,0x63,0x63,0x63,0x63,0x63,0x3E,0x00},\t// O\r\n\t{0x7E,0x33,0x33,0x3E,0x30,0x30,0x78,0x00},\t// P\r\n\t{0x3C,0x66,0x66,0x66,0x6E,0x3C,0x0E,0x00},\t// Q\r\n\t{0x7E,0x33,0x33,0x3E,0x36,0x33,0x73,0x00},\t// R\r\n\t{0x3C,0x66,0x30,0x18,0x0C,0x66,0x3C,0x00},\t// S\r\n\t{0x7E,0x5A,0x18,0x18,0x18,0x18,0x3C,0x00},\t// T\r\n\t{0x66,0x66,0x66,0x66,0x66,0x66,0x7E,0x00},\t// U\r\n\t{0x66,0x66,0x66,0x66,0x66,0x3C,0x18,0x00},\t// V\r\n\t{0x63,0x63,0x63,0x6B,0x7F,0x77,0x63,0x00},\t// W\r\n\t{0x63,0x63,0x36,0x1C,0x1C,0x36,0x63,0x00},\t// X\r\n\t{0x66,0x66,0x66,0x3C,0x18,0x18,0x3C,0x00},\t// Y\r\n\t{0x7F,0x63,0x46,0x0C,0x19,0x33,0x7F,0x00},\t// Z\r\n\t{0x3C,0x30,0x30,0x30,0x30,0x30,0x3C,0x00},\t// [\r\n\t{0x60,0x30,0x18,0x0C,0x06,0x03,0x01,0x00},\t// backslash\r\n\t{0x3C,0x0C,0x0C,0x0C,0x0C,0x0C,0x3C,0x00},\t// ]\r\n\t{0x08,0x1C,0x36,0x63,0x00,0x00,0x00,0x00},\t// ^\r\n\t{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF},\t// _\r\n\t{0x18,0x18,0x0C,0x00,0x00,0x00,0x00,0x00},\t// `\r\n\t{0x00,0x00,0x3C,0x06,0x3E,0x66,0x3B,0x00},\t// a\r\n\t{0x70,0x30,0x3E,0x33,0x33,0x33,0x6E,0x00},\t// b\r\n\t{0x00,0x00,0x3C,0x66,0x60,0x66,0x3C,0x00},\t// c\r\n\t{0x0E,0x06,0x3E,0x66,0x66,0x66,0x3B,0x00},\t// d\r\n\t{0x00,0x00,0x3C,0x66,0x7E,0x60,0x3C,0x00},\t// e\r\n\t{0x1C,0x36,0x30,0x78,0x30,0x30,0x78,0x00},\t// f\r\n\t{0x00,0x00,0x3B,0x66,0x66,0x3E,0x06,0x7C},\t// g\r\n\t{0x70,0x30,0x36,0x3B,0x33,0x33,0x73,0x00},\t// h\r\n\t{0x18,0x00,0x38,0x18,0x18,0x18,0x3C,0x00},\t// i\r\n\t{0x06,0x00,0x06,0x06,0x06,0x66,0x66,0x3C},\t// j\r\n\t{0x70,0x30,0x33,0x36,0x3C,0x36,0x73,0x00},\t// k\r\n\t{0x38,0x18,0x18,0x18,0x18,0x18,0x3C,0x00},\t// l\r\n\t{0x00,0x00,0x66,0x7F,0x7F,0x6B,0x63,0x00},\t// m\r\n\t{0x00,0x00,0x7C,0x66,0x66,0x66,0x66,0x00},\t// n\r\n\t{0x00,0x00,0x3C,0x66,0x66,0x66,0x3C,0x00},\t// o\r\n\t{0x00,0x00,0x6E,0x33,0x33,0x3E,0x30,0x78},\t// p\r\n\t{0x00,0x00,0x3B,0x66,0x66,0x3E,0x06,0x0F},\t// q\r\n\t{0x00,0x00,0x6E,0x3B,0x33,0x30,0x78,0x00},\t// r\r\n\t{0x00,0x00,0x3E,0x60,0x3C,0x06,0x7C,0x00},\t// s\r\n\t{0x08,0x18,0x3E,0x18,0x18,0x1A,0x0C,0x00},\t// t\r\n\t{0x00,0x00,0x66,0x66,0x66,0x66,0x3B,0x00},\t// u\r\n\t{0x00,0x00,0x66,0x66,0x66,0x3C,0x18,0x00},\t// v\r\n\t{0x00,0x00,0x63,0x6B,0x7F,0x7F,0x36,0x00},\t// w\r\n\t{0x00,0x00,0x63,0x36,0x1C,0x36,0x63,0x00},\t// x\r\n\t{0x00,0x00,0x66,0x66,0x66,0x3E,0x06,0x7C},\t// y\r\n\t{0x00,0x00,0x7E,0x4C,0x18,0x32,0x7E,0x00},\t// z\r\n\t{0x0E,0x18,0x18,0x70,0x18,0x18,0x0E,0x00},\t// {\r\n\t{0x0C,0x0C,0x0C,0x00,0x0C,0x0C,0x0C,0x00},\t// |\r\n\t{0x70,0x18,0x18,0x0E,0x18,0x18,0x70,0x00},\t// }\r\n\t{0x3B,0x6E,0x00,0x00,0x00,0x00,0x00,0x00},\t// ~\r\n\t{0x1C,0x36,0x36,0x1C,0x00,0x00,0x00,0x00}\t// DEL\r\n};\r\n\r\nconst char FONT8x16[97][16] = {\r\n\t{0x08,0x10,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},\t// columns, rows, bytes per char\r\n\t{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},\t// space\r\n\t{0x00,0x00,0x18,0x3C,0x3C,0x3C,0x18,0x18,0x18,0x00,0x18,0x18,0x00,0x00,0x00,0x00},\t// !\r\n\t{0x00,0x63,0x63,0x63,0x22,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},\t// \"\r\n\t{0x00,0x00,0x00,0x36,0x36,0x7F,0x36,0x36,0x36,0x7F,0x36,0x36,0x00,0x00,0x00,0x00},\t// #\r\n\t{0x0C,0x0C,0x3E,0x63,0x61,0x60,0x3E,0x03,0x03,0x43,0x63,0x3E,0x0C,0x0C,0x00,0x00},\t// $\r\n\t{0x00,0x00,0x00,0x00,0x00,0x61,0x63,0x06,0x0C,0x18,0x33,0x63,0x00,0x00,0x00,0x00},\t// %\r\n\t{0x00,0x00,0x00,0x1C,0x36,0x36,0x1C,0x3B,0x6E,0x66,0x66,0x3B,0x00,0x00,0x00,0x00},\t// &\r\n\t{0x00,0x30,0x30,0x30,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},\t// '\r\n\t{0x00,0x00,0x0C,0x18,0x18,0x30,0x30,0x30,0x30,0x18,0x18,0x0C,0x00,0x00,0x00,0x00},\t// (\r\n\t{0x00,0x00,0x18,0x0C,0x0C,0x06,0x06,0x06,0x06,0x0C,0x0C,0x18,0x00,0x00,0x00,0x00},\t// )\r\n\t{0x00,0x00,0x00,0x00,0x42,0x66,0x3C,0xFF,0x3C,0x66,0x42,0x00,0x00,0x00,0x00,0x00},\t// *\r\n\t{0x00,0x00,0x00,0x00,0x18,0x18,0x18,0xFF,0x18,0x18,0x18,0x00,0x00,0x00,0x00,0x00},\t// +\r\n\t{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x18,0x30,0x00,0x00},\t// ,\r\n\t{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},\t// -\r\n\t{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x00},\t// .\r\n\t{0x00,0x00,0x01,0x03,0x07,0x0E,0x1C,0x38,0x70,0xE0,0xC0,0x80,0x00,0x00,0x00,0x00},\t// /\r\n\t{0x00,0x00,0x3E,0x63,0x63,0x63,0x6B,0x6B,0x63,0x63,0x63,0x3E,0x00,0x00,0x00,0x00},\t// 0\r\n\t{0x00,0x00,0x0C,0x1C,0x3C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x3F,0x00,0x00,0x00,0x00},\t// 1\r\n\t{0x00,0x00,0x3E,0x63,0x03,0x06,0x0C,0x18,0x30,0x61,0x63,0x7F,0x00,0x00,0x00,0x00},\t// 2\r\n\t{0x00,0x00,0x3E,0x63,0x03,0x03,0x1E,0x03,0x03,0x03,0x63,0x3E,0x00,0x00,0x00,0x00},\t// 3\r\n\t{0x00,0x00,0x06,0x0E,0x1E,0x36,0x66,0x66,0x7F,0x06,0x06,0x0F,0x00,0x00,0x00,0x00},\t// 4\r\n\t{0x00,0x00,0x7F,0x60,0x60,0x60,0x7E,0x03,0x03,0x63,0x73,0x3E,0x00,0x00,0x00,0x00},\t// 5\r\n\t{0x00,0x00,0x1C,0x30,0x60,0x60,0x7E,0x63,0x63,0x63,0x63,0x3E,0x00,0x00,0x00,0x00},\t// 6\r\n\t{0x00,0x00,0x7F,0x63,0x03,0x06,0x06,0x0C,0x0C,0x18,0x18,0x18,0x00,0x00,0x00,0x00},\t// 7\r\n\t{0x00,0x00,0x3E,0x63,0x63,0x63,0x3E,0x63,0x63,0x63,0x63,0x3E,0x00,0x00,0x00,0x00},\t// 8\r\n\t{0x00,0x00,0x3E,0x63,0x63,0x63,0x63,0x3F,0x03,0x03,0x06,0x3C,0x00,0x00,0x00,0x00},\t// 9\r\n\t{0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x00},\t// :\r\n\t{0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x18,0x18,0x18,0x30,0x00,0x00},\t// ;\r\n\t{0x00,0x00,0x00,0x06,0x0C,0x18,0x30,0x60,0x30,0x18,0x0C,0x06,0x00,0x00,0x00,0x00},\t// <\r\n\t{0x00,0x00,0x00,0x00,0x00,0x00,0x7E,0x00,0x00,0x7E,0x00,0x00,0x00,0x00,0x00,0x00},\t// =\r\n\t{0x00,0x00,0x00,0x60,0x30,0x18,0x0C,0x06,0x0C,0x18,0x30,0x60,0x00,0x00,0x00,0x00},\t// >\r\n\t{0x00,0x00,0x3E,0x63,0x63,0x06,0x0C,0x0C,0x0C,0x00,0x0C,0x0C,0x00,0x00,0x00,0x00},\t// ?\r\n\t{0x00,0x00,0x3E,0x63,0x63,0x6F,0x6B,0x6B,0x6E,0x60,0x60,0x3E,0x00,0x00,0x00,0x00},\t// @\r\n\t{0x00,0x00,0x08,0x1C,0x36,0x63,0x63,0x63,0x7F,0x63,0x63,0x63,0x00,0x00,0x00,0x00},\t// A\r\n\t{0x00,0x00,0x7E,0x33,0x33,0x33,0x3E,0x33,0x33,0x33,0x33,0x7E,0x00,0x00,0x00,0x00},\t// B\r\n\t{0x00,0x00,0x1E,0x33,0x61,0x60,0x60,0x60,0x60,0x61,0x33,0x1E,0x00,0x00,0x00,0x00},\t// C\r\n\t{0x00,0x00,0x7C,0x36,0x33,0x33,0x33,0x33,0x33,0x33,0x36,0x7C,0x00,0x00,0x00,0x00},\t// D\r\n\t{0x00,0x00,0x7F,0x33,0x31,0x34,0x3C,0x34,0x30,0x31,0x33,0x7F,0x00,0x00,0x00,0x00},\t// E\r\n\t{0x00,0x00,0x7F,0x33,0x31,0x34,0x3C,0x34,0x30,0x30,0x30,0x78,0x00,0x00,0x00,0x00},\t// F\r\n\t{0x00,0x00,0x1E,0x33,0x61,0x60,0x60,0x6F,0x63,0x63,0x37,0x1D,0x00,0x00,0x00,0x00},\t// G\r\n\t{0x00,0x00,0x63,0x63,0x63,0x63,0x7F,0x63,0x63,0x63,0x63,0x63,0x00,0x00,0x00,0x00},\t// H\r\n\t{0x00,0x00,0x3C,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x3C,0x00,0x00,0x00,0x00},\t// I\r\n\t{0x00,0x00,0x0F,0x06,0x06,0x06,0x06,0x06,0x06,0x66,0x66,0x3C,0x00,0x00,0x00,0x00},\t// J\r\n\t{0x00,0x00,0x73,0x33,0x36,0x36,0x3C,0x36,0x36,0x33,0x33,0x73,0x00,0x00,0x00,0x00},\t// K\r\n\t{0x00,0x00,0x78,0x30,0x30,0x30,0x30,0x30,0x30,0x31,0x33,0x7F,0x00,0x00,0x00,0x00},\t// L\r\n\t{0x00,0x00,0x63,0x77,0x7F,0x6B,0x63,0x63,0x63,0x63,0x63,0x63,0x00,0x00,0x00,0x00},\t// M\r\n\t{0x00,0x00,0x63,0x63,0x73,0x7B,0x7F,0x6F,0x67,0x63,0x63,0x63,0x00,0x00,0x00,0x00},\t// N\r\n\t{0x00,0x00,0x1C,0x36,0x63,0x63,0x63,0x63,0x63,0x63,0x36,0x1C,0x00,0x00,0x00,0x00},\t// O\r\n\t{0x00,0x00,0x7E,0x33,0x33,0x33,0x3E,0x30,0x30,0x30,0x30,0x78,0x00,0x00,0x00,0x00},\t// P\r\n\t{0x00,0x00,0x3E,0x63,0x63,0x63,0x63,0x63,0x63,0x6B,0x6F,0x3E,0x06,0x07,0x00,0x00},\t// Q\r\n\t{0x00,0x00,0x7E,0x33,0x33,0x33,0x3E,0x36,0x36,0x33,0x33,0x73,0x00,0x00,0x00,0x00},\t// R\r\n\t{0x00,0x00,0x3E,0x63,0x63,0x30,0x1C,0x06,0x03,0x63,0x63,0x3E,0x00,0x00,0x00,0x00},\t// S\r\n\t{0x00,0x00,0xFF,0xDB,0x99,0x18,0x18,0x18,0x18,0x18,0x18,0x3C,0x00,0x00,0x00,0x00},\t// T\r\n\t{0x00,0x00,0x63,0x63,0x63,0x63,0x63,0x63,0x63,0x63,0x63,0x3E,0x00,0x00,0x00,0x00},\t// U\r\n\t{0x00,0x00,0x63,0x63,0x63,0x63,0x63,0x63,0x63,0x36,0x1C,0x08,0x00,0x00,0x00,0x00},\t// V\r\n\t{0x00,0x00,0x63,0x63,0x63,0x63,0x63,0x6B,0x6B,0x7F,0x36,0x36,0x00,0x00,0x00,0x00},\t// W\r\n\t{0x00,0x00,0xC3,0xC3,0x66,0x3C,0x18,0x18,0x3C,0x66,0xC3,0xC3,0x00,0x00,0x00,0x00},\t// X\r\n\t{0x00,0x00,0xC3,0xC3,0xC3,0x66,0x3C,0x18,0x18,0x18,0x18,0x3C,0x00,0x00,0x00,0x00},\t// Y\r\n\t{0x00,0x00,0x7F,0x63,0x43,0x06,0x0C,0x18,0x30,0x61,0x63,0x7F,0x00,0x00,0x00,0x00},\t// Z\r\n\t{0x00,0x00,0x3C,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x3C,0x00,0x00,0x00,0x00},\t// [\r\n\t{0x00,0x00,0x80,0xC0,0xE0,0x70,0x38,0x1C,0x0E,0x07,0x03,0x01,0x00,0x00,0x00,0x00},\t// backslash\r\n\t{0x00,0x00,0x3C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x3C,0x00,0x00,0x00,0x00},\t// ]\r\n\t{0x08,0x1C,0x36,0x63,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},\t// ^\r\n\t{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00},\t// _\r\n\t{0x18,0x18,0x0C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},\t// `\r\n\t{0x00,0x00,0x00,0x00,0x00,0x3C,0x46,0x06,0x3E,0x66,0x66,0x3B,0x00,0x00,0x00,0x00},\t// a\r\n\t{0x00,0x00,0x70,0x30,0x30,0x3C,0x36,0x33,0x33,0x33,0x33,0x6E,0x00,0x00,0x00,0x00},\t// b\r\n\t{0x00,0x00,0x00,0x00,0x00,0x3E,0x63,0x60,0x60,0x60,0x63,0x3E,0x00,0x00,0x00,0x00},\t// c\r\n\t{0x00,0x00,0x0E,0x06,0x06,0x1E,0x36,0x66,0x66,0x66,0x66,0x3B,0x00,0x00,0x00,0x00},\t// d\r\n\t{0x00,0x00,0x00,0x00,0x00,0x3E,0x63,0x63,0x7E,0x60,0x63,0x3E,0x00,0x00,0x00,0x00},\t// e\r\n\t{0x00,0x00,0x1C,0x36,0x32,0x30,0x7C,0x30,0x30,0x30,0x30,0x78,0x00,0x00,0x00,0x00},\t// f\r\n\t{0x00,0x00,0x00,0x00,0x00,0x3B,0x66,0x66,0x66,0x66,0x3E,0x06,0x66,0x3C,0x00,0x00},\t// g\r\n\t{0x00,0x00,0x70,0x30,0x30,0x36,0x3B,0x33,0x33,0x33,0x33,0x73,0x00,0x00,0x00,0x00},\t// h\r\n\t{0x00,0x00,0x0C,0x0C,0x00,0x1C,0x0C,0x0C,0x0C,0x0C,0x0C,0x1E,0x00,0x00,0x00,0x00},\t// i\r\n\t{0x00,0x00,0x06,0x06,0x00,0x0E,0x06,0x06,0x06,0x06,0x06,0x66,0x66,0x3C,0x00,0x00},\t// j\r\n\t{0x00,0x00,0x70,0x30,0x30,0x33,0x33,0x36,0x3C,0x36,0x33,0x73,0x00,0x00,0x00,0x00},\t// k\r\n\t{0x00,0x00,0x1C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x1E,0x00,0x00,0x00,0x00},\t// l\r\n\t{0x00,0x00,0x00,0x00,0x00,0x6E,0x7F,0x6B,0x6B,0x6B,0x6B,0x6B,0x00,0x00,0x00,0x00},\t// m\r\n\t{0x00,0x00,0x00,0x00,0x00,0x6E,0x33,0x33,0x33,0x33,0x33,0x33,0x00,0x00,0x00,0x00},\t// n\r\n\t{0x00,0x00,0x00,0x00,0x00,0x3E,0x63,0x63,0x63,0x63,0x63,0x3E,0x00,0x00,0x00,0x00},\t// o\r\n\t{0x00,0x00,0x00,0x00,0x00,0x6E,0x33,0x33,0x33,0x33,0x3E,0x30,0x30,0x78,0x00,0x00},\t// p\r\n\t{0x00,0x00,0x00,0x00,0x00,0x3B,0x66,0x66,0x66,0x66,0x3E,0x06,0x06,0x0F,0x00,0x00},\t// q\r\n\t{0x00,0x00,0x00,0x00,0x00,0x6E,0x3B,0x33,0x30,0x30,0x30,0x78,0x00,0x00,0x00,0x00},\t// r\r\n\t{0x00,0x00,0x00,0x00,0x00,0x3E,0x63,0x38,0x0E,0x03,0x63,0x3E,0x00,0x00,0x00,0x00},\t// s\r\n\t{0x00,0x00,0x08,0x18,0x18,0x7E,0x18,0x18,0x18,0x18,0x1B,0x0E,0x00,0x00,0x00,0x00},\t// t\r\n\t{0x00,0x00,0x00,0x00,0x00,0x66,0x66,0x66,0x66,0x66,0x66,0x3B,0x00,0x00,0x00,0x00},\t// u\r\n\t{0x00,0x00,0x00,0x00,0x00,0x63,0x63,0x36,0x36,0x1C,0x1C,0x08,0x00,0x00,0x00,0x00},\t// v\r\n\t{0x00,0x00,0x00,0x00,0x00,0x63,0x63,0x63,0x6B,0x6B,0x7F,0x36,0x00,0x00,0x00,0x00},\t// w\r\n\t{0x00,0x00,0x00,0x00,0x00,0x63,0x36,0x1C,0x1C,0x1C,0x36,0x63,0x00,0x00,0x00,0x00},\t// x\r\n\t{0x00,0x00,0x00,0x00,0x00,0x63,0x63,0x63,0x63,0x63,0x3F,0x03,0x06,0x3C,0x00,0x00},\t// y\r\n\t{0x00,0x00,0x00,0x00,0x00,0x7F,0x66,0x0C,0x18,0x30,0x63,0x7F,0x00,0x00,0x00,0x00},\t// z\r\n\t{0x00,0x00,0x0E,0x18,0x18,0x18,0x70,0x18,0x18,0x18,0x18,0x0E,0x00,0x00,0x00,0x00},\t// {\r\n\t{0x00,0x00,0x18,0x18,0x18,0x18,0x18,0x00,0x18,0x18,0x18,0x18,0x18,0x00,0x00,0x00},\t// |\r\n\t{0x00,0x00,0x70,0x18,0x18,0x18,0x0E,0x18,0x18,0x18,0x18,0x70,0x00,0x00,0x00,0x00},\t// }\r\n\t{0x00,0x00,0x3B,0x6E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},\t// ~\r\n\t{0x00,0x70,0xD8,0xD8,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}\t// DEL\r\n};\r\n*/\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/fonts.h", "content": "//-----------------------------------------------------------------------------\r\n// This code is licensed to you under the terms of the GNU GPL, version 2 or,\r\n// at your option, any later version. See the LICENSE.txt file for the text of\r\n// the license.\r\n//-----------------------------------------------------------------------------\r\n// Fonts for the LCD\r\n//-----------------------------------------------------------------------------\r\n\r\n#ifndef __FONTS_H\r\n#define __FONTS_H\r\n\r\nextern const char FONT6x8[97][8];\r\nextern const char FONT8x8F[97][8];\r\nextern const char FONT8x16[97][16];\r\n\r\n#endif\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/fpgaloader.c", "content": "//-----------------------------------------------------------------------------\r\n// Jonathan Westhues, April 2006\r\n//\r\n// This code is licensed to you under the terms of the GNU GPL, version 2 or,\r\n// at your option, any later version. See the LICENSE.txt file for the text of\r\n// the license.\r\n//-----------------------------------------------------------------------------\r\n// Routines to load the FPGA image, and then to configure the FPGA's major\r\n// mode once it is configured.\r\n//-----------------------------------------------------------------------------\r\n\r\n#include \"proxmark3.h\"\r\n#include \"apps.h\"\r\n#include \"util.h\"\r\n#include \"string.h\"\r\n\r\n//-----------------------------------------------------------------------------\r\n// Set up the Serial Peripheral Interface as master\r\n// Used to write the FPGA config word\r\n// May also be used to write to other SPI attached devices like an LCD\r\n//-----------------------------------------------------------------------------\r\nvoid SetupSpi(int mode)\r\n{\r\n\t// PA10 -> SPI_NCS2 chip select (LCD)\r\n\t// PA11 -> SPI_NCS0 chip select (FPGA)\r\n\t// PA12 -> SPI_MISO Master-In Slave-Out\r\n\t// PA13 -> SPI_MOSI Master-Out Slave-In\r\n\t// PA14 -> SPI_SPCK Serial Clock\r\n\r\n\t// Disable PIO control of the following pins, allows use by the SPI peripheral\r\n\tAT91C_BASE_PIOA->PIO_PDR =\r\n\t\tGPIO_NCS0\t|\r\n\t\tGPIO_NCS2 \t|\r\n\t\tGPIO_MISO\t|\r\n\t\tGPIO_MOSI\t|\r\n\t\tGPIO_SPCK;\r\n\r\n\tAT91C_BASE_PIOA->PIO_ASR =\r\n\t\tGPIO_NCS0\t|\r\n\t\tGPIO_MISO\t|\r\n\t\tGPIO_MOSI\t|\r\n\t\tGPIO_SPCK;\r\n\r\n\tAT91C_BASE_PIOA->PIO_BSR = GPIO_NCS2;\r\n\r\n\t//enable the SPI Peripheral clock\r\n\tAT91C_BASE_PMC->PMC_PCER = (1<SPI_CR = AT91C_SPI_SPIEN;\r\n\r\n\tswitch (mode) {\r\n\t\tcase SPI_FPGA_MODE:\r\n\t\t\tAT91C_BASE_SPI->SPI_MR =\r\n\t\t\t\t( 0 << 24)\t|\t// Delay between chip selects (take default: 6 MCK periods)\r\n\t\t\t\t(14 << 16)\t|\t// Peripheral Chip Select (selects FPGA SPI_NCS0 or PA11)\r\n\t\t\t\t( 0 << 7)\t|\t// Local Loopback Disabled\r\n\t\t\t\t( 1 << 4)\t|\t// Mode Fault Detection disabled\r\n\t\t\t\t( 0 << 2)\t|\t// Chip selects connected directly to peripheral\r\n\t\t\t\t( 0 << 1) \t|\t// Fixed Peripheral Select\r\n\t\t\t\t( 1 << 0);\t\t// Master Mode\r\n\t\t\tAT91C_BASE_SPI->SPI_CSR[0] =\r\n\t\t\t\t( 1 << 24)\t|\t// Delay between Consecutive Transfers (32 MCK periods)\r\n\t\t\t\t( 1 << 16)\t|\t// Delay Before SPCK (1 MCK period)\r\n\t\t\t\t( 6 << 8)\t|\t// Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud\r\n\t\t\t\t( 8 << 4)\t|\t// Bits per Transfer (16 bits)\r\n\t\t\t\t( 0 << 3)\t|\t// Chip Select inactive after transfer\r\n\t\t\t\t( 1 << 1)\t|\t// Clock Phase data captured on leading edge, changes on following edge\r\n\t\t\t\t( 0 << 0);\t\t// Clock Polarity inactive state is logic 0\r\n\t\t\tbreak;\r\n\t\tcase SPI_LCD_MODE:\r\n\t\t\tAT91C_BASE_SPI->SPI_MR =\r\n\t\t\t\t( 0 << 24)\t|\t// Delay between chip selects (take default: 6 MCK periods)\r\n\t\t\t\t(11 << 16)\t|\t// Peripheral Chip Select (selects LCD SPI_NCS2 or PA10)\r\n\t\t\t\t( 0 << 7)\t|\t// Local Loopback Disabled\r\n\t\t\t\t( 1 << 4)\t|\t// Mode Fault Detection disabled\r\n\t\t\t\t( 0 << 2)\t|\t// Chip selects connected directly to peripheral\r\n\t\t\t\t( 0 << 1) \t|\t// Fixed Peripheral Select\r\n\t\t\t\t( 1 << 0);\t\t// Master Mode\r\n\t\t\tAT91C_BASE_SPI->SPI_CSR[2] =\r\n\t\t\t\t( 1 << 24)\t|\t// Delay between Consecutive Transfers (32 MCK periods)\r\n\t\t\t\t( 1 << 16)\t|\t// Delay Before SPCK (1 MCK period)\r\n\t\t\t\t( 6 << 8)\t|\t// Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud\r\n\t\t\t\t( 1 << 4)\t|\t// Bits per Transfer (9 bits)\r\n\t\t\t\t( 0 << 3)\t|\t// Chip Select inactive after transfer\r\n\t\t\t\t( 1 << 1)\t|\t// Clock Phase data captured on leading edge, changes on following edge\r\n\t\t\t\t( 0 << 0);\t\t// Clock Polarity inactive state is logic 0\r\n\t\t\tbreak;\r\n\t\tdefault:\t\t\t\t// Disable SPI\r\n\t\t\tAT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIDIS;\r\n\t\t\tbreak;\r\n\t}\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// Set up the synchronous serial port, with the one set of options that we\r\n// always use when we are talking to the FPGA. Both RX and TX are enabled.\r\n//-----------------------------------------------------------------------------\r\nvoid FpgaSetupSsc(void)\r\n{\r\n\t// First configure the GPIOs, and get ourselves a clock.\r\n\tAT91C_BASE_PIOA->PIO_ASR =\r\n\t\tGPIO_SSC_FRAME\t|\r\n\t\tGPIO_SSC_DIN\t|\r\n\t\tGPIO_SSC_DOUT\t|\r\n\t\tGPIO_SSC_CLK;\r\n\tAT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;\r\n\r\n\tAT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_SSC);\r\n\r\n\t// Now set up the SSC proper, starting from a known state.\r\n\tAT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;\r\n\r\n\t// RX clock comes from TX clock, RX starts when TX starts, data changes\r\n\t// on RX clock rising edge, sampled on falling edge\r\n\tAT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);\r\n\r\n\t// 8 bits per transfer, no loopback, MSB first, 1 transfer per sync\r\n\t// pulse, no output sync, start on positive-going edge of sync\r\n\tAT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) |\tAT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);\r\n\r\n\t// clock comes from TK pin, no clock output, outputs change on falling\r\n\t// edge of TK, start on rising edge of TF\r\n\tAT91C_BASE_SSC->SSC_TCMR = SSC_CLOCK_MODE_SELECT(2) |\tSSC_CLOCK_MODE_START(5);\r\n\r\n\t// tx framing is the same as the rx framing\r\n\tAT91C_BASE_SSC->SSC_TFMR = AT91C_BASE_SSC->SSC_RFMR;\r\n\r\n\tAT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// Set up DMA to receive samples from the FPGA. We will use the PDC, with\r\n// a single buffer as a circular buffer (so that we just chain back to\r\n// ourselves, not to another buffer). The stuff to manipulate those buffers\r\n// is in apps.h, because it should be inlined, for speed.\r\n//-----------------------------------------------------------------------------\r\nbool FpgaSetupSscDma(uint8_t *buf, int len)\r\n{\r\n\tif (buf == NULL) {\r\n return false;\r\n }\r\n\r\n\tAT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;\r\n\tAT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) buf;\r\n\tAT91C_BASE_PDC_SSC->PDC_RCR = len;\r\n\tAT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) buf;\r\n\tAT91C_BASE_PDC_SSC->PDC_RNCR = len;\r\n\tAT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN;\r\n \r\n return true;\r\n}\r\n\r\nstatic void DownloadFPGA_byte(unsigned char w)\r\n{\r\n#define SEND_BIT(x) { if(w & (1<PIO_OER = GPIO_FPGA_ON;\r\n\tAT91C_BASE_PIOA->PIO_PER = GPIO_FPGA_ON;\r\n\tHIGH(GPIO_FPGA_ON);\t\t// ensure everything is powered on\r\n\r\n\tSpinDelay(50);\r\n\r\n\tLED_D_ON();\r\n\r\n\t// These pins are inputs\r\n AT91C_BASE_PIOA->PIO_ODR =\r\n \tGPIO_FPGA_NINIT |\r\n \tGPIO_FPGA_DONE;\r\n\t// PIO controls the following pins\r\n AT91C_BASE_PIOA->PIO_PER =\r\n \tGPIO_FPGA_NINIT |\r\n \tGPIO_FPGA_DONE;\r\n\t// Enable pull-ups\r\n\tAT91C_BASE_PIOA->PIO_PPUER =\r\n\t\tGPIO_FPGA_NINIT |\r\n\t\tGPIO_FPGA_DONE;\r\n\r\n\t// setup initial logic state\r\n\tHIGH(GPIO_FPGA_NPROGRAM);\r\n\tLOW(GPIO_FPGA_CCLK);\r\n\tLOW(GPIO_FPGA_DIN);\r\n\t// These pins are outputs\r\n\tAT91C_BASE_PIOA->PIO_OER =\r\n\t\tGPIO_FPGA_NPROGRAM\t|\r\n\t\tGPIO_FPGA_CCLK\t\t|\r\n\t\tGPIO_FPGA_DIN;\r\n\r\n\t// enter FPGA configuration mode\r\n\tLOW(GPIO_FPGA_NPROGRAM);\r\n\tSpinDelay(50);\r\n\tHIGH(GPIO_FPGA_NPROGRAM);\r\n\r\n\ti=100000;\r\n\t// wait for FPGA ready to accept data signal\r\n\twhile ((i) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_NINIT ) ) ) {\r\n\t\ti--;\r\n\t}\r\n\r\n\t// crude error indicator, leave both red LEDs on and return\r\n\tif (i==0){\r\n\t\tLED_C_ON();\r\n\t\tLED_D_ON();\r\n\t\treturn;\r\n\t}\r\n\r\n\tif(bytereversal) {\r\n\t\t/* This is only supported for uint32_t aligned images */\r\n\t\tif( ((int)FpgaImage % sizeof(uint32_t)) == 0 ) {\r\n\t\t\ti=0;\r\n\t\t\twhile(FpgaImageLen-->0)\r\n\t\t\t\tDownloadFPGA_byte(FpgaImage[(i++)^0x3]);\r\n\t\t\t/* Explanation of the magic in the above line:\r\n\t\t\t * i^0x3 inverts the lower two bits of the integer i, counting backwards\r\n\t\t\t * for each 4 byte increment. The generated sequence of (i++)^3 is\r\n\t\t\t * 3 2 1 0 7 6 5 4 11 10 9 8 15 14 13 12 etc. pp.\r\n\t\t\t */\r\n\t\t}\r\n\t} else {\r\n\t\twhile(FpgaImageLen-->0)\r\n\t\t\tDownloadFPGA_byte(*FpgaImage++);\r\n\t}\r\n\r\n\t// continue to clock FPGA until ready signal goes high\r\n\ti=100000;\r\n\twhile ( (i--) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_DONE ) ) ) {\r\n\t\tHIGH(GPIO_FPGA_CCLK);\r\n\t\tLOW(GPIO_FPGA_CCLK);\r\n\t}\r\n\t// crude error indicator, leave both red LEDs on and return\r\n\tif (i==0){\r\n\t\tLED_C_ON();\r\n\t\tLED_D_ON();\r\n\t\treturn;\r\n\t}\r\n\tLED_D_OFF();\r\n}\r\n\r\nstatic char *bitparse_headers_start;\r\nstatic char *bitparse_bitstream_end;\r\nstatic int bitparse_initialized;\r\n/* Simple Xilinx .bit parser. The file starts with the fixed opaque byte sequence\r\n * 00 09 0f f0 0f f0 0f f0 0f f0 00 00 01\r\n * After that the format is 1 byte section type (ASCII character), 2 byte length\r\n * (big endian), bytes content. Except for section 'e' which has 4 bytes\r\n * length.\r\n */\r\nstatic const char _bitparse_fixed_header[] = {0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x00, 0x00, 0x01};\r\nstatic int bitparse_init(void * start_address, void *end_address)\r\n{\r\n\tbitparse_initialized = 0;\r\n\r\n\tif(memcmp(_bitparse_fixed_header, start_address, sizeof(_bitparse_fixed_header)) != 0) {\r\n\t\treturn 0; /* Not matched */\r\n\t} else {\r\n\t\tbitparse_headers_start= ((char*)start_address) + sizeof(_bitparse_fixed_header);\r\n\t\tbitparse_bitstream_end= (char*)end_address;\r\n\t\tbitparse_initialized = 1;\r\n\t\treturn 1;\r\n\t}\r\n}\r\n\r\nint bitparse_find_section(char section_name, char **section_start, unsigned int *section_length)\r\n{\r\n\tchar *pos = bitparse_headers_start;\r\n\tint result = 0;\r\n\r\n\tif(!bitparse_initialized) return 0;\r\n\r\n\twhile(pos < bitparse_bitstream_end) {\r\n\t\tchar current_name = *pos++;\r\n\t\tunsigned int current_length = 0;\r\n\t\tif(current_name < 'a' || current_name > 'e') {\r\n\t\t\t/* Strange section name, abort */\r\n\t\t\tbreak;\r\n\t\t}\r\n\t\tcurrent_length = 0;\r\n\t\tswitch(current_name) {\r\n\t\tcase 'e':\r\n\t\t\t/* Four byte length field */\r\n\t\t\tcurrent_length += (*pos++) << 24;\r\n\t\t\tcurrent_length += (*pos++) << 16;\r\n\t\tdefault: /* Fall through, two byte length field */\r\n\t\t\tcurrent_length += (*pos++) << 8;\r\n\t\t\tcurrent_length += (*pos++) << 0;\r\n\t\t}\r\n\r\n\t\tif(current_name != 'e' && current_length > 255) {\r\n\t\t\t/* Maybe a parse error */\r\n\t\t\tbreak;\r\n\t\t}\r\n\r\n\t\tif(current_name == section_name) {\r\n\t\t\t/* Found it */\r\n\t\t\t*section_start = pos;\r\n\t\t\t*section_length = current_length;\r\n\t\t\tresult = 1;\r\n\t\t\tbreak;\r\n\t\t}\r\n\r\n\t\tpos += current_length; /* Skip section */\r\n\t}\r\n\r\n\treturn result;\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// Find out which FPGA image format is stored in flash, then call DownloadFPGA\r\n// with the right parameters to download the image\r\n//-----------------------------------------------------------------------------\r\nextern char _binary_fpga_bit_start, _binary_fpga_bit_end;\r\nvoid FpgaDownloadAndGo(void)\r\n{\r\n\t/* Check for the new flash image format: Should have the .bit file at &_binary_fpga_bit_start\r\n\t */\r\n\tif(bitparse_init(&_binary_fpga_bit_start, &_binary_fpga_bit_end)) {\r\n\t\t/* Successfully initialized the .bit parser. Find the 'e' section and\r\n\t\t * send its contents to the FPGA.\r\n\t\t */\r\n\t\tchar *bitstream_start;\r\n\t\tunsigned int bitstream_length;\r\n\t\tif(bitparse_find_section('e', &bitstream_start, &bitstream_length)) {\r\n\t\t\tDownloadFPGA(bitstream_start, bitstream_length, 0);\r\n\r\n\t\t\treturn; /* All done */\r\n\t\t}\r\n\t}\r\n\r\n\t/* Fallback for the old flash image format: Check for the magic marker 0xFFFFFFFF\r\n\t * 0xAA995566 at address 0x102000. This is raw bitstream with a size of 336,768 bits\r\n\t * = 10,524 uint32_t, stored as uint32_t e.g. little-endian in memory, but each DWORD\r\n\t * is still to be transmitted in MSBit first order. Set the invert flag to indicate\r\n\t * that the DownloadFPGA function should invert every 4 byte sequence when doing\r\n\t * the bytewise download.\r\n\t */\r\n\tif( *(uint32_t*)0x102000 == 0xFFFFFFFF && *(uint32_t*)0x102004 == 0xAA995566 )\r\n\t\tDownloadFPGA((char*)0x102000, 10524*4, 1);\r\n}\r\n\r\nvoid FpgaGatherVersion(char *dst, int len)\r\n{\r\n\tchar *fpga_info;\r\n\tunsigned int fpga_info_len;\r\n\tdst[0] = 0;\r\n\tif(!bitparse_find_section('e', &fpga_info, &fpga_info_len)) {\r\n\t\tstrncat(dst, \"FPGA image: legacy image without version information\", len-1);\r\n\t} else {\r\n\t\tstrncat(dst, \"FPGA image built\", len-1);\r\n\t\t/* USB packets only have 48 bytes data payload, so be terse */\r\n#if 0\r\n\t\tif(bitparse_find_section('a', &fpga_info, &fpga_info_len) && fpga_info[fpga_info_len-1] == 0 ) {\r\n\t\t\tstrncat(dst, \" from \", len-1);\r\n\t\t\tstrncat(dst, fpga_info, len-1);\r\n\t\t}\r\n\t\tif(bitparse_find_section('b', &fpga_info, &fpga_info_len) && fpga_info[fpga_info_len-1] == 0 ) {\r\n\t\t\tstrncat(dst, \" for \", len-1);\r\n\t\t\tstrncat(dst, fpga_info, len-1);\r\n\t\t}\r\n#endif\r\n\t\tif(bitparse_find_section('c', &fpga_info, &fpga_info_len) && fpga_info[fpga_info_len-1] == 0 ) {\r\n\t\t\tstrncat(dst, \" on \", len-1);\r\n\t\t\tstrncat(dst, fpga_info, len-1);\r\n\t\t}\r\n\t\tif(bitparse_find_section('d', &fpga_info, &fpga_info_len) && fpga_info[fpga_info_len-1] == 0 ) {\r\n\t\t\tstrncat(dst, \" at \", len-1);\r\n\t\t\tstrncat(dst, fpga_info, len-1);\r\n\t\t}\r\n\t}\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// Send a 16 bit command/data pair to the FPGA.\r\n// The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0\r\n// where C is the 4 bit command and D is the 12 bit data\r\n//-----------------------------------------------------------------------------\r\nvoid FpgaSendCommand(uint16_t cmd, uint16_t v)\r\n{\r\n\tSetupSpi(SPI_FPGA_MODE);\r\n\twhile ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TXEMPTY) == 0);\t\t// wait for the transfer to complete\r\n\tAT91C_BASE_SPI->SPI_TDR = AT91C_SPI_LASTXFER | cmd | v;\t\t// send the data\r\n}\r\n//-----------------------------------------------------------------------------\r\n// Write the FPGA setup word (that determines what mode the logic is in, read\r\n// vs. clone vs. etc.). This is now a special case of FpgaSendCommand() to\r\n// avoid changing this function's occurence everywhere in the source code.\r\n//-----------------------------------------------------------------------------\r\nvoid FpgaWriteConfWord(uint8_t v)\r\n{\r\n\tFpgaSendCommand(FPGA_CMD_SET_CONFREG, v);\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// Set up the CMOS switches that mux the ADC: four switches, independently\r\n// closable, but should only close one at a time. Not an FPGA thing, but\r\n// the samples from the ADC always flow through the FPGA.\r\n//-----------------------------------------------------------------------------\r\nvoid SetAdcMuxFor(uint32_t whichGpio)\r\n{\r\n\tAT91C_BASE_PIOA->PIO_OER =\r\n\t\tGPIO_MUXSEL_HIPKD |\r\n\t\tGPIO_MUXSEL_LOPKD |\r\n\t\tGPIO_MUXSEL_LORAW |\r\n\t\tGPIO_MUXSEL_HIRAW;\r\n\r\n\tAT91C_BASE_PIOA->PIO_PER =\r\n\t\tGPIO_MUXSEL_HIPKD |\r\n\t\tGPIO_MUXSEL_LOPKD |\r\n\t\tGPIO_MUXSEL_LORAW |\r\n\t\tGPIO_MUXSEL_HIRAW;\r\n\r\n\tLOW(GPIO_MUXSEL_HIPKD);\r\n\tLOW(GPIO_MUXSEL_HIRAW);\r\n\tLOW(GPIO_MUXSEL_LORAW);\r\n\tLOW(GPIO_MUXSEL_LOPKD);\r\n\r\n\tHIGH(whichGpio);\r\n}\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/hitag2.c", "content": "//-----------------------------------------------------------------------------\r\n// This code is licensed to you under the terms of the GNU GPL, version 2 or,\r\n// at your option, any later version. See the LICENSE.txt file for the text of\r\n// the license.\r\n//-----------------------------------------------------------------------------\r\n// Hitag2 emulation (preliminary test version)\r\n//\r\n// (c) 2009 Henryk Plötz \r\n//-----------------------------------------------------------------------------\r\n// Hitag2 complete rewrite of the code\r\n// - Fixed modulation/encoding issues\r\n// - Rewrote code for transponder emulation\r\n// - Added snooping of transponder communication\r\n// - Added reader functionality\r\n//\r\n// (c) 2012 Roel Verdult\r\n//-----------------------------------------------------------------------------\r\n\r\n#include \"proxmark3.h\"\r\n#include \"apps.h\"\r\n#include \"util.h\"\r\n#include \"hitag2.h\"\r\n#include \"string.h\"\r\n\r\nstatic bool bQuiet;\r\n\r\nbool bCrypto;\r\nbool bAuthenticating;\r\nbool bPwd;\r\nbool bSuccessful;\r\n\r\nint LogTraceHitag(const uint8_t * btBytes, int iBits, int iSamples, uint32_t dwParity, int bReader)\r\n{\r\n // Return when trace is full\r\n if (traceLen >= TRACE_SIZE) return FALSE;\r\n \r\n // Trace the random, i'm curious\r\n rsamples += iSamples;\r\n trace[traceLen++] = ((rsamples >> 0) & 0xff);\r\n trace[traceLen++] = ((rsamples >> 8) & 0xff);\r\n trace[traceLen++] = ((rsamples >> 16) & 0xff);\r\n trace[traceLen++] = ((rsamples >> 24) & 0xff);\r\n if (!bReader) {\r\n trace[traceLen - 1] |= 0x80;\r\n }\r\n trace[traceLen++] = ((dwParity >> 0) & 0xff);\r\n trace[traceLen++] = ((dwParity >> 8) & 0xff);\r\n trace[traceLen++] = ((dwParity >> 16) & 0xff);\r\n trace[traceLen++] = ((dwParity >> 24) & 0xff);\r\n trace[traceLen++] = iBits;\r\n memcpy(trace + traceLen, btBytes, nbytes(iBits));\r\n traceLen += nbytes(iBits);\r\n return TRUE;\r\n}\r\n\r\nstruct hitag2_tag {\r\n\tuint32_t uid;\r\n\tenum {\r\n\t\tTAG_STATE_RESET = 0x01, // Just powered up, awaiting GetSnr\r\n\t\tTAG_STATE_ACTIVATING = 0x02 , // In activation phase (password mode), sent UID, awaiting reader password\r\n\t\tTAG_STATE_ACTIVATED = 0x03, // Activation complete, awaiting read/write commands\r\n\t\tTAG_STATE_WRITING = 0x04, // In write command, awaiting sector contents to be written\r\n\t} state;\r\n\tunsigned int active_sector;\r\n\tbyte_t crypto_active;\r\n\tuint64_t cs;\r\n\tbyte_t sectors[12][4];\r\n};\r\n\r\nstatic struct hitag2_tag tag = {\r\n .state = TAG_STATE_RESET,\r\n .sectors = { // Password mode: | Crypto mode:\r\n [0] = { 0x02, 0x4e, 0x02, 0x20}, // UID | UID\r\n [1] = { 0x4d, 0x49, 0x4b, 0x52}, // Password RWD | 32 bit LSB key\r\n [2] = { 0x20, 0xf0, 0x4f, 0x4e}, // Reserved | 16 bit MSB key, 16 bit reserved\r\n [3] = { 0x0e, 0xaa, 0x48, 0x54}, // Configuration, password TAG | Configuration, password TAG\r\n [4] = { 0x46, 0x5f, 0x4f, 0x4b}, // Data: F_OK\r\n [5] = { 0x55, 0x55, 0x55, 0x55}, // Data: UUUU\r\n [6] = { 0xaa, 0xaa, 0xaa, 0xaa}, // Data: ....\r\n [7] = { 0x55, 0x55, 0x55, 0x55}, // Data: UUUU\r\n [8] = { 0x00, 0x00, 0x00, 0x00}, // RSK Low\r\n [9] = { 0x00, 0x00, 0x00, 0x00}, // RSK High\r\n [10] = { 0x00, 0x00, 0x00, 0x00}, // RCF\r\n [11] = { 0x00, 0x00, 0x00, 0x00}, // SYNC\r\n },\r\n};\r\n\r\n//#define TRACE_LENGTH 3000\r\n//uint8_t *trace = (uint8_t *) BigBuf;\r\n//int traceLen = 0;\r\n//int rsamples = 0;\r\n\r\n#define AUTH_TABLE_OFFSET FREE_BUFFER_OFFSET\r\n#define AUTH_TABLE_LENGTH FREE_BUFFER_SIZE\r\nbyte_t* auth_table = (byte_t *)BigBuf+AUTH_TABLE_OFFSET;\r\nsize_t auth_table_pos = 0;\r\nsize_t auth_table_len = AUTH_TABLE_LENGTH;\r\n\r\nbyte_t password[4];\r\nbyte_t NrAr[8];\r\nbyte_t key[8];\r\nuint64_t cipher_state;\r\n\r\n/* Following is a modified version of cryptolib.com/ciphers/hitag2/ */\r\n// Software optimized 48-bit Philips/NXP Mifare Hitag2 PCF7936/46/47/52 stream cipher algorithm by I.C. Wiener 2006-2007.\r\n// For educational purposes only.\r\n// No warranties or guarantees of any kind.\r\n// This code is released into the public domain by its author.\r\n\r\n// Basic macros:\r\n\r\n#define u8\t\t\t\tuint8_t\r\n#define u32\t\t\t\tuint32_t\r\n#define u64\t\t\t\tuint64_t\r\n#define rev8(x)\t\t\t((((x)>>7)&1)+((((x)>>6)&1)<<1)+((((x)>>5)&1)<<2)+((((x)>>4)&1)<<3)+((((x)>>3)&1)<<4)+((((x)>>2)&1)<<5)+((((x)>>1)&1)<<6)+(((x)&1)<<7))\r\n#define rev16(x)\t\t(rev8 (x)+(rev8 (x>> 8)<< 8))\r\n#define rev32(x)\t\t(rev16(x)+(rev16(x>>16)<<16))\r\n#define rev64(x)\t\t(rev32(x)+(rev32(x>>32)<<32))\r\n#define bit(x,n)\t\t(((x)>>(n))&1)\r\n#define bit32(x,n)\t\t((((x)[(n)>>5])>>((n)))&1)\r\n#define inv32(x,i,n)\t((x)[(i)>>5]^=((u32)(n))<<((i)&31))\r\n#define rotl64(x, n)\t((((u64)(x))<<((n)&63))+(((u64)(x))>>((0-(n))&63)))\r\n\r\n// Single bit Hitag2 functions:\r\n\r\n#define i4(x,a,b,c,d)\t((u32)((((x)>>(a))&1)+(((x)>>(b))&1)*2+(((x)>>(c))&1)*4+(((x)>>(d))&1)*8))\r\n\r\nstatic const u32 ht2_f4a = 0x2C79;\t\t// 0010 1100 0111 1001\r\nstatic const u32 ht2_f4b = 0x6671;\t\t// 0110 0110 0111 0001\r\nstatic const u32 ht2_f5c = 0x7907287B;\t// 0111 1001 0000 0111 0010 1000 0111 1011\r\n\r\nstatic u32 _f20 (const u64 x)\r\n{\r\n\tu32\t\t\t\t\ti5;\r\n\r\n\ti5 = ((ht2_f4a >> i4 (x, 1, 2, 4, 5)) & 1)* 1\r\n\t + ((ht2_f4b >> i4 (x, 7,11,13,14)) & 1)* 2\r\n\t + ((ht2_f4b >> i4 (x,16,20,22,25)) & 1)* 4\r\n\t + ((ht2_f4b >> i4 (x,27,28,30,32)) & 1)* 8\r\n\t + ((ht2_f4a >> i4 (x,33,42,43,45)) & 1)*16;\r\n\r\n\treturn (ht2_f5c >> i5) & 1;\r\n}\r\n\r\nstatic u64 _hitag2_init (const u64 key, const u32 serial, const u32 IV)\r\n{\r\n\tu32\t\t\t\t\ti;\r\n\tu64\t\t\t\t\tx = ((key & 0xFFFF) << 32) + serial;\r\n\r\n\tfor (i = 0; i < 32; i++)\r\n\t{\r\n\t\tx >>= 1;\r\n\t\tx += (u64) (_f20 (x) ^ (((IV >> i) ^ (key >> (i+16))) & 1)) << 47;\r\n\t}\r\n\treturn x;\r\n}\r\n\r\nstatic u64 _hitag2_round (u64 *state)\r\n{\r\n\tu64\t\t\t\t\tx = *state;\r\n\r\n\tx = (x >> 1) +\r\n\t ((((x >> 0) ^ (x >> 2) ^ (x >> 3) ^ (x >> 6)\r\n\t ^ (x >> 7) ^ (x >> 8) ^ (x >> 16) ^ (x >> 22)\r\n\t ^ (x >> 23) ^ (x >> 26) ^ (x >> 30) ^ (x >> 41)\r\n\t ^ (x >> 42) ^ (x >> 43) ^ (x >> 46) ^ (x >> 47)) & 1) << 47);\r\n\r\n\t*state = x;\r\n\treturn _f20 (x);\r\n}\r\n\r\nstatic u32 _hitag2_byte (u64 * x)\r\n{\r\n\tu32\t\t\t\t\ti, c;\r\n\r\n\tfor (i = 0, c = 0; i < 8; i++) c += (u32) _hitag2_round (x) << (i^7);\r\n\treturn c;\r\n}\r\n\r\nint hitag2_reset(void)\r\n{\r\n\ttag.state = TAG_STATE_RESET;\r\n\ttag.crypto_active = 0;\r\n\treturn 0;\r\n}\r\n\r\nint hitag2_init(void)\r\n{\r\n//\tmemcpy(&tag, &resetdata, sizeof(tag));\r\n\thitag2_reset();\r\n\treturn 0;\r\n}\r\n\r\nstatic void hitag2_cipher_reset(struct hitag2_tag *tag, const byte_t *iv)\r\n{\r\n\tuint64_t key = ((uint64_t)tag->sectors[2][2]) |\r\n ((uint64_t)tag->sectors[2][3] << 8) |\r\n ((uint64_t)tag->sectors[1][0] << 16) |\r\n ((uint64_t)tag->sectors[1][1] << 24) |\r\n ((uint64_t)tag->sectors[1][2] << 32) |\r\n ((uint64_t)tag->sectors[1][3] << 40);\r\n\tuint32_t uid = ((uint32_t)tag->sectors[0][0]) |\r\n ((uint32_t)tag->sectors[0][1] << 8) |\r\n ((uint32_t)tag->sectors[0][2] << 16) |\r\n ((uint32_t)tag->sectors[0][3] << 24);\r\n\tuint32_t iv_ = (((uint32_t)(iv[0]))) |\r\n\t\t\t(((uint32_t)(iv[1])) << 8) |\r\n\t\t\t(((uint32_t)(iv[2])) << 16) |\r\n\t\t\t(((uint32_t)(iv[3])) << 24);\r\n\ttag->cs = _hitag2_init(rev64(key), rev32(uid), rev32(iv_));\r\n}\r\n\r\nstatic int hitag2_cipher_authenticate(uint64_t* cs, const byte_t *authenticator_is)\r\n{\r\n\tbyte_t authenticator_should[4];\r\n\tauthenticator_should[0] = ~_hitag2_byte(cs);\r\n\tauthenticator_should[1] = ~_hitag2_byte(cs);\r\n\tauthenticator_should[2] = ~_hitag2_byte(cs);\r\n\tauthenticator_should[3] = ~_hitag2_byte(cs);\r\n\treturn (memcmp(authenticator_should, authenticator_is, 4) == 0);\r\n}\r\n\r\nstatic int hitag2_cipher_transcrypt(uint64_t* cs, byte_t *data, unsigned int bytes, unsigned int bits)\r\n{\r\n\tint i;\r\n\tfor(i=0; i 36 */\r\n#define HITAG_T_LOW\t\t8 /* T_LOW should be 4..10 */\r\n#define HITAG_T_0_MIN 15 /* T[0] should be 18..22 */\r\n#define HITAG_T_1_MIN 25 /* T[1] should be 26..30 */\r\n//#define HITAG_T_EOF 40 /* T_EOF should be > 36 */\r\n#define HITAG_T_EOF 80\t /* T_EOF should be > 36 */\r\n#define HITAG_T_WAIT_1 200 /* T_wresp should be 199..206 */\r\n#define HITAG_T_WAIT_2 90 /* T_wresp should be 199..206 */\r\n#define HITAG_T_WAIT_MAX 300 /* bit more than HITAG_T_WAIT_1 + HITAG_T_WAIT_2 */\r\n\r\n#define HITAG_T_TAG_ONE_HALF_PERIOD\t\t\t10\r\n#define HITAG_T_TAG_TWO_HALF_PERIOD\t\t\t25\r\n#define HITAG_T_TAG_THREE_HALF_PERIOD\t\t41 \r\n#define HITAG_T_TAG_FOUR_HALF_PERIOD 57 \r\n\r\n#define HITAG_T_TAG_HALF_PERIOD\t\t\t\t\t16\r\n#define HITAG_T_TAG_FULL_PERIOD\t\t\t\t\t32\r\n\r\n#define HITAG_T_TAG_CAPTURE_ONE_HALF\t\t13\r\n#define HITAG_T_TAG_CAPTURE_TWO_HALF\t\t25\r\n#define HITAG_T_TAG_CAPTURE_THREE_HALF\t41 \r\n#define HITAG_T_TAG_CAPTURE_FOUR_HALF 57 \r\n\r\n\r\nstatic void hitag_send_bit(int bit) {\r\n\tLED_A_ON();\r\n\t// Reset clock for the next bit \r\n\tAT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;\r\n\t\r\n\t// Fixed modulation, earlier proxmark version used inverted signal\r\n\tif(bit == 0) {\r\n\t\t// Manchester: Unloaded, then loaded |__--|\r\n\t\tLOW(GPIO_SSC_DOUT);\r\n\t\twhile(AT91C_BASE_TC0->TC_CV < T0*HITAG_T_TAG_HALF_PERIOD);\r\n\t\tHIGH(GPIO_SSC_DOUT);\r\n\t\twhile(AT91C_BASE_TC0->TC_CV < T0*HITAG_T_TAG_FULL_PERIOD);\r\n\t} else {\r\n\t\t// Manchester: Loaded, then unloaded |--__|\r\n\t\tHIGH(GPIO_SSC_DOUT);\r\n\t\twhile(AT91C_BASE_TC0->TC_CV < T0*HITAG_T_TAG_HALF_PERIOD);\r\n\t\tLOW(GPIO_SSC_DOUT);\r\n\t\twhile(AT91C_BASE_TC0->TC_CV < T0*HITAG_T_TAG_FULL_PERIOD);\r\n\t}\r\n\tLED_A_OFF();\r\n}\r\n\r\nstatic void hitag_send_frame(const byte_t* frame, size_t frame_len)\r\n{\r\n\t// Send start of frame\r\n\tfor(size_t i=0; i<5; i++) {\r\n\t\thitag_send_bit(1);\r\n\t}\r\n\r\n\t// Send the content of the frame\r\n\tfor(size_t i=0; i> (7-(i%8)))&1);\r\n\t}\r\n\r\n\t// Drop the modulation\r\n\tLOW(GPIO_SSC_DOUT);\r\n}\r\n\r\nvoid hitag2_handle_reader_command(byte_t* rx, const size_t rxlen, byte_t* tx, size_t* txlen)\r\n{\r\n\tbyte_t rx_air[HITAG_FRAME_LEN];\r\n\t\r\n\t// Copy the (original) received frame how it is send over the air\r\n\tmemcpy(rx_air,rx,nbytes(rxlen));\r\n\r\n\tif(tag.crypto_active) {\r\n\t\thitag2_cipher_transcrypt(&(tag.cs),rx,rxlen/8,rxlen%8);\r\n\t}\r\n\t\r\n\t// Reset the transmission frame length \r\n\t*txlen = 0;\r\n\t\r\n\t// Try to find out which command was send by selecting on length (in bits)\r\n\tswitch (rxlen) {\r\n\t\t// Received 11000 from the reader, request for UID, send UID \r\n\t\tcase 05: {\r\n\t\t\t// Always send over the air in the clear plaintext mode\r\n\t\t\tif(rx_air[0] != 0xC0) {\r\n\t\t\t\t// Unknown frame ?\r\n\t\t\t\treturn;\r\n\t\t\t}\r\n\t\t\t*txlen = 32;\r\n\t\t\tmemcpy(tx,tag.sectors[0],4);\r\n\t\t\ttag.crypto_active = 0;\r\n\t\t}\r\n\t\tbreak;\r\n\r\n\t\t// Read/Write command: ..xx x..y yy with yyy == ~xxx, xxx is sector number \r\n\t\tcase 10: {\r\n\t\t\tunsigned int sector = (~( ((rx[0]<<2)&0x04) | ((rx[1]>>6)&0x03) ) & 0x07);\r\n\t\t\t// Verify complement of sector index\r\n\t\t\tif(sector != ((rx[0]>>3)&0x07)) {\r\n\t\t\t\t//DbpString(\"Transmission error (read/write)\");\r\n\t\t\t\treturn;\r\n\t\t\t}\r\n\r\n\t\t\tswitch (rx[0] & 0xC6) {\r\n\t\t\t\t// Read command: 11xx x00y\r\n\t\t\t\tcase 0xC0:\r\n\t\t\t\t\tmemcpy(tx,tag.sectors[sector],4);\r\n\t\t\t\t\t*txlen = 32;\r\n\t\t\t\tbreak;\r\n\t\t\t\t\t\r\n\t\t\t\t // Inverted Read command: 01xx x10y\r\n\t\t\t\tcase 0x44:\r\n\t\t\t\t\tfor (size_t i=0; i<4; i++) {\r\n\t\t\t\t\t\ttx[i] = tag.sectors[sector][i] ^ 0xff;\r\n\t\t\t\t\t}\r\n\t\t\t\t\t*txlen = 32;\r\n\t\t\t\tbreak;\r\n\r\n\t\t\t\t// Write command: 10xx x01y\r\n\t\t\t\tcase 0x82:\r\n\t\t\t\t\t// Prepare write, acknowledge by repeating command\r\n\t\t\t\t\tmemcpy(tx,rx,nbytes(rxlen));\r\n\t\t\t\t\t*txlen = rxlen;\r\n\t\t\t\t\ttag.active_sector = sector;\r\n\t\t\t\t\ttag.state=TAG_STATE_WRITING;\r\n\t\t\t\tbreak;\r\n\t\t\t\t\r\n\t\t\t\t// Unknown command\r\n\t\t\t\tdefault:\r\n\t\t\t\t\tDbprintf(\"Uknown command: %02x %02x\",rx[0],rx[1]);\r\n\t\t\t\t\treturn;\r\n\t\t\t\tbreak;\r\n\t\t\t}\r\n\t\t}\r\n\t\tbreak;\r\n\r\n\t\t// Writing data or Reader password\r\n\t\tcase 32: {\r\n\t\t\tif(tag.state == TAG_STATE_WRITING) {\r\n\t\t\t\t// These are the sector contents to be written. We don't have to do anything else.\r\n\t\t\t\tmemcpy(tag.sectors[tag.active_sector],rx,nbytes(rxlen));\r\n\t\t\t\ttag.state=TAG_STATE_RESET;\r\n\t\t\t\treturn;\r\n\t\t\t} else {\r\n\t\t\t\t// Received RWD password, respond with configuration and our password\r\n\t\t\t\tif(memcmp(rx,tag.sectors[1],4) != 0) {\r\n\t\t\t\t\tDbpString(\"Reader password is wrong\");\r\n\t\t\t\t\treturn;\r\n\t\t\t\t}\r\n\t\t\t\t*txlen = 32;\r\n\t\t\t\tmemcpy(tx,tag.sectors[3],4);\r\n\t\t\t}\r\n\t\t}\r\n\t\tbreak;\r\n\r\n\t\t// Received RWD authentication challenge and respnse\r\n\t\tcase 64: {\r\n\t\t\t// Store the authentication attempt\r\n\t\t\tif (auth_table_len < (AUTH_TABLE_LENGTH-8)) {\r\n\t\t\t\tmemcpy(auth_table+auth_table_len,rx,8);\r\n\t\t\t\tauth_table_len += 8;\r\n\t\t\t}\r\n\r\n\t\t\t// Reset the cipher state\r\n\t\t\thitag2_cipher_reset(&tag,rx);\r\n\t\t\t// Check if the authentication was correct\r\n\t\t\tif(!hitag2_cipher_authenticate(&(tag.cs),rx+4)) {\r\n\t\t\t\t// The reader failed to authenticate, do nothing\r\n\t\t\t\tDbprintf(\"auth: %02x%02x%02x%02x%02x%02x%02x%02x Failed!\",rx[0],rx[1],rx[2],rx[3],rx[4],rx[5],rx[6],rx[7]);\r\n\t\t\t\treturn;\r\n\t\t\t}\r\n\t\t\t// Succesful, but commented out reporting back to the Host, this may delay to much.\r\n\t\t\t// Dbprintf(\"auth: %02x%02x%02x%02x%02x%02x%02x%02x OK!\",rx[0],rx[1],rx[2],rx[3],rx[4],rx[5],rx[6],rx[7]);\r\n\r\n\t\t\t// Activate encryption algorithm for all further communication\r\n\t\t\ttag.crypto_active = 1;\r\n\r\n\t\t\t// Use the tag password as response\r\n\t\t\tmemcpy(tx,tag.sectors[3],4);\r\n\t\t\t*txlen = 32;\r\n\t\t}\r\n\t\tbreak;\r\n\t}\r\n\r\n//\tLogTraceHitag(rx,rxlen,0,0,false);\r\n//\tLogTraceHitag(tx,*txlen,0,0,true);\r\n\t\r\n\tif(tag.crypto_active) {\r\n\t\thitag2_cipher_transcrypt(&(tag.cs), tx, *txlen/8, *txlen%8);\r\n\t}\r\n}\r\n\r\nstatic void hitag_reader_send_bit(int bit) {\r\n\tLED_A_ON();\r\n\t// Reset clock for the next bit \r\n\tAT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;\r\n\t\r\n\t// Binary puls length modulation (BPLM) is used to encode the data stream\r\n\t// This means that a transmission of a one takes longer than that of a zero\r\n\t\r\n\t// Enable modulation, which means, drop the the field\r\n\tHIGH(GPIO_SSC_DOUT);\r\n\t\r\n\t// Wait for 4-10 times the carrier period\r\n\twhile(AT91C_BASE_TC0->TC_CV < T0*6);\r\n\t//\tSpinDelayUs(8*8);\r\n\t\r\n\t// Disable modulation, just activates the field again\r\n\tLOW(GPIO_SSC_DOUT);\r\n\t\r\n\tif(bit == 0) {\r\n\t\t// Zero bit: |_-|\r\n\t\twhile(AT91C_BASE_TC0->TC_CV < T0*22);\r\n\t\t//\t\tSpinDelayUs(16*8);\r\n\t} else {\r\n\t\t// One bit: |_--|\r\n\t\twhile(AT91C_BASE_TC0->TC_CV < T0*28);\r\n\t\t//\t\tSpinDelayUs(22*8);\r\n\t}\r\n\tLED_A_OFF();\r\n}\r\n\r\nstatic void hitag_reader_send_frame(const byte_t* frame, size_t frame_len)\r\n{\r\n\t// Send the content of the frame\r\n\tfor(size_t i=0; i> (7-(i%8)))&1);\r\n\t}\r\n\t// Send EOF \r\n\tAT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;\r\n\t// Enable modulation, which means, drop the the field\r\n\tHIGH(GPIO_SSC_DOUT);\r\n\t// Wait for 4-10 times the carrier period\r\n\twhile(AT91C_BASE_TC0->TC_CV < T0*6);\r\n\t// Disable modulation, just activates the field again\r\n\tLOW(GPIO_SSC_DOUT);\r\n}\r\n\r\nsize_t blocknr;\r\n\r\nbool hitag2_password(byte_t* rx, const size_t rxlen, byte_t* tx, size_t* txlen) {\r\n\t// Reset the transmission frame length\r\n\t*txlen = 0;\r\n\t\r\n\t// Try to find out which command was send by selecting on length (in bits)\r\n\tswitch (rxlen) {\r\n\t\t// No answer, try to resurrect\r\n\t\tcase 0: {\r\n\t\t\t// Stop if there is no answer (after sending password)\r\n\t\t\tif (bPwd) {\r\n\t\t\t\tDbpString(\"Password failed!\");\r\n\t\t\t\treturn false;\r\n\t\t\t}\r\n\t\t\t*txlen = 5;\r\n\t\t\tmemcpy(tx,\"\\xc0\",nbytes(*txlen));\r\n\t\t} break;\r\n\t\t\t\r\n\t\t// Received UID, tag password\r\n\t\tcase 32: {\r\n\t\t\tif (!bPwd) {\r\n\t\t\t\t*txlen = 32;\r\n\t\t\t\tmemcpy(tx,password,4);\r\n\t\t\t\tbPwd = true;\r\n memcpy(tag.sectors[blocknr],rx,4);\r\n blocknr++;\r\n\t\t\t} else {\r\n\t\t\t\t\r\n\t\t\tif(blocknr == 1){\r\n\t\t\t\t//store password in block1, the TAG answers with Block3, but we need the password in memory\r\n\t\t\t\tmemcpy(tag.sectors[blocknr],tx,4);\r\n\t\t\t}else{\r\n\t\t\t\tmemcpy(tag.sectors[blocknr],rx,4);\r\n\t\t\t}\r\n\t\t\t\r\n\t\t\tblocknr++;\r\n\t\t\tif (blocknr > 7) {\r\n\t\t\t DbpString(\"Read succesful!\");\r\n bSuccessful = true;\r\n\t\t\t return false;\r\n\t\t\t}\r\n\t\t\t*txlen = 10;\r\n\t\t\ttx[0] = 0xc0 | (blocknr << 3) | ((blocknr^7) >> 2);\r\n\t\t\ttx[1] = ((blocknr^7) << 6);\r\n\t\t\t}\r\n\t\t} break;\r\n\t\t\t\r\n\t\t// Unexpected response\r\n default: {\r\n\t\t\tDbprintf(\"Uknown frame length: %d\",rxlen);\r\n\t\t\treturn false;\r\n\t\t} break;\r\n\t}\r\n\treturn true;\r\n}\r\n\r\nbool hitag2_crypto(byte_t* rx, const size_t rxlen, byte_t* tx, size_t* txlen) {\r\n\t// Reset the transmission frame length\r\n\t*txlen = 0;\r\n\t\r\n if(bCrypto) {\r\n\t\thitag2_cipher_transcrypt(&cipher_state,rx,rxlen/8,rxlen%8);\r\n\t}\r\n\r\n\t// Try to find out which command was send by selecting on length (in bits)\r\n\tswitch (rxlen) {\r\n // No answer, try to resurrect\r\n\t\tcase 0: {\r\n\t\t\t// Stop if there is no answer while we are in crypto mode (after sending NrAr)\r\n\t\t\tif (bCrypto) {\r\n // Failed during authentication\r\n if (bAuthenticating) {\r\n DbpString(\"Authentication failed!\");\r\n return false;\r\n } else {\r\n // Failed reading a block, could be (read/write) locked, skip block and re-authenticate\r\n if (blocknr == 1) {\r\n // Write the low part of the key in memory\r\n memcpy(tag.sectors[1],key+2,4);\r\n } else if (blocknr == 2) {\r\n // Write the high part of the key in memory\r\n tag.sectors[2][0] = 0x00;\r\n tag.sectors[2][1] = 0x00;\r\n tag.sectors[2][2] = key[0];\r\n tag.sectors[2][3] = key[1];\r\n } else {\r\n // Just put zero's in the memory (of the unreadable block)\r\n memset(tag.sectors[blocknr],0x00,4);\r\n }\r\n blocknr++;\r\n bCrypto = false;\r\n }\r\n\t\t\t} else {\r\n *txlen = 5;\r\n memcpy(tx,\"\\xc0\",nbytes(*txlen));\r\n }\r\n\t\t} break;\r\n\t\t\t\r\n // Received UID, crypto tag answer\r\n\t\tcase 32: {\r\n\t\t\tif (!bCrypto) {\r\n uint64_t ui64key = key[0] | ((uint64_t)key[1]) << 8 | ((uint64_t)key[2]) << 16 | ((uint64_t)key[3]) << 24 | ((uint64_t)key[4]) << 32 | ((uint64_t)key[5]) << 40;\r\n uint32_t ui32uid = rx[0] | ((uint32_t)rx[1]) << 8 | ((uint32_t)rx[2]) << 16 | ((uint32_t)rx[3]) << 24;\r\n cipher_state = _hitag2_init(rev64(ui64key), rev32(ui32uid), 0);\r\n memset(tx,0x00,4);\r\n memset(tx+4,0xff,4);\r\n hitag2_cipher_transcrypt(&cipher_state,tx+4,4,0);\r\n\t\t\t\t*txlen = 64;\r\n\t\t\t\tbCrypto = true;\r\n bAuthenticating = true;\r\n\t\t\t} else {\r\n // Check if we received answer tag (at)\r\n if (bAuthenticating) {\r\n bAuthenticating = false;\r\n } else {\r\n // Store the received block\r\n memcpy(tag.sectors[blocknr],rx,4);\r\n blocknr++;\r\n }\r\n if (blocknr > 7) {\r\n DbpString(\"Read succesful!\");\r\n bSuccessful = true;\r\n return false;\r\n }\r\n *txlen = 10;\r\n tx[0] = 0xc0 | (blocknr << 3) | ((blocknr^7) >> 2);\r\n tx[1] = ((blocknr^7) << 6);\r\n\t\t\t}\r\n\t\t} break;\r\n\t\t\t\r\n // Unexpected response\r\n\t\tdefault: {\r\n\t\t\tDbprintf(\"Uknown frame length: %d\",rxlen);\r\n\t\t\treturn false;\r\n\t\t} break;\r\n\t}\r\n\t\r\n \r\n if(bCrypto) {\r\n // We have to return now to avoid double encryption\r\n if (!bAuthenticating) {\r\n hitag2_cipher_transcrypt(&cipher_state,tx,*txlen/8,*txlen%8);\r\n }\r\n\t}\r\n\r\n\treturn true;\r\n}\r\n\r\n\r\nbool hitag2_authenticate(byte_t* rx, const size_t rxlen, byte_t* tx, size_t* txlen) {\r\n\t// Reset the transmission frame length \r\n\t*txlen = 0;\r\n\t\r\n\t// Try to find out which command was send by selecting on length (in bits)\r\n\tswitch (rxlen) {\r\n\t\t// No answer, try to resurrect\r\n\t\tcase 0: {\r\n\t\t\t// Stop if there is no answer while we are in crypto mode (after sending NrAr)\r\n\t\t\tif (bCrypto) {\r\n\t\t\t\tDbpString(\"Authentication failed!\");\r\n\t\t\t\treturn false;\r\n\t\t\t}\r\n\t\t\t*txlen = 5;\r\n\t\t\tmemcpy(tx,\"\\xc0\",nbytes(*txlen));\r\n\t\t} break;\r\n\t\t\t\r\n\t\t// Received UID, crypto tag answer\r\n\t\tcase 32: {\r\n\t\t\tif (!bCrypto) {\r\n\t\t\t\t*txlen = 64;\r\n\t\t\t\tmemcpy(tx,NrAr,8);\r\n\t\t\t\tbCrypto = true;\r\n\t\t\t} else {\r\n\t\t\t\tDbpString(\"Authentication succesful!\");\r\n\t\t\t\t// We are done... for now\r\n\t\t\t\treturn false;\r\n\t\t\t}\r\n\t\t} break;\r\n\t\t\t\r\n\t\t// Unexpected response\r\n\t\tdefault: {\r\n\t\t\tDbprintf(\"Uknown frame length: %d\",rxlen);\r\n\t\t\treturn false;\r\n\t\t} break;\r\n\t}\r\n\t\r\n\treturn true;\r\n}\r\n\r\nbool hitag2_test_auth_attempts(byte_t* rx, const size_t rxlen, byte_t* tx, size_t* txlen) {\r\n\t// Reset the transmission frame length \r\n\t*txlen = 0;\r\n\t\r\n\t// Try to find out which command was send by selecting on length (in bits)\r\n\tswitch (rxlen) {\r\n\t\t\t// No answer, try to resurrect\r\n\t\tcase 0: {\r\n\t\t\t// Stop if there is no answer while we are in crypto mode (after sending NrAr)\r\n\t\t\tif (bCrypto) {\r\n\t\t\t\tDbprintf(\"auth: %02x%02x%02x%02x%02x%02x%02x%02x Failed, removed entry!\",NrAr[0],NrAr[1],NrAr[2],NrAr[3],NrAr[4],NrAr[5],NrAr[6],NrAr[7]);\r\n\r\n // Removing failed entry from authentiations table\r\n memcpy(auth_table+auth_table_pos,auth_table+auth_table_pos+8,8);\r\n auth_table_len -= 8;\r\n\r\n // Return if we reached the end of the authentiactions table\r\n\t\t\t\tbCrypto = false;\r\n\t\t\t\tif (auth_table_pos == auth_table_len) {\r\n\t\t\t\t\treturn false;\r\n\t\t\t\t}\r\n \r\n // Copy the next authentication attempt in row (at the same position, b/c we removed last failed entry)\r\n\t\t\t\tmemcpy(NrAr,auth_table+auth_table_pos,8);\r\n\t\t\t}\r\n\t\t\t*txlen = 5;\r\n\t\t\tmemcpy(tx,\"\\xc0\",nbytes(*txlen));\r\n\t\t}\tbreak;\r\n\t\t\t\r\n\t\t\t// Received UID, crypto tag answer, or read block response\r\n\t\tcase 32: {\r\n\t\t\tif (!bCrypto) {\r\n\t\t\t\t*txlen = 64;\r\n\t\t\t\tmemcpy(tx,NrAr,8);\r\n\t\t\t\tbCrypto = true;\r\n\t\t\t} else {\r\n\t\t\t\tDbprintf(\"auth: %02x%02x%02x%02x%02x%02x%02x%02x OK\",NrAr[0],NrAr[1],NrAr[2],NrAr[3],NrAr[4],NrAr[5],NrAr[6],NrAr[7]);\r\n\t\t\t\tbCrypto = false;\r\n\t\t\t\tif ((auth_table_pos+8) == auth_table_len) {\r\n\t\t\t\t\treturn false;\r\n\t\t\t\t}\r\n\t\t\t\tauth_table_pos += 8;\r\n\t\t\t\tmemcpy(NrAr,auth_table+auth_table_pos,8);\r\n\t\t\t}\r\n\t\t} break;\r\n\t\t\t\r\n\t\tdefault: {\r\n\t\t\tDbprintf(\"Uknown frame length: %d\",rxlen);\r\n\t\t\treturn false;\r\n\t\t} break;\r\n\t}\r\n\t\r\n\treturn true;\r\n}\r\n\r\nvoid SnoopHitag(uint32_t type) {\r\n\tint frame_count;\r\n\tint response;\r\n\tint overflow;\r\n\tbool rising_edge;\r\n\tbool reader_frame;\r\n\tint lastbit;\r\n\tbool bSkip;\r\n\tint tag_sof;\r\n\tbyte_t rx[HITAG_FRAME_LEN];\r\n\tsize_t rxlen=0;\r\n\t\r\n\t// Clean up trace and prepare it for storing frames\r\n\tiso14a_set_tracing(TRUE);\r\n\tiso14a_clear_trace();\r\n\r\n\tauth_table_len = 0;\r\n\tauth_table_pos = 0;\r\n\tmemset(auth_table, 0x00, AUTH_TABLE_LENGTH);\r\n\t\r\n\tDbpString(\"Starting Hitag2 snoop\");\r\n\tLED_D_ON();\r\n\t\r\n\t// Set up eavesdropping mode, frequency divisor which will drive the FPGA\r\n\t// and analog mux selection.\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);\r\n\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r\n\tSetAdcMuxFor(GPIO_MUXSEL_LOPKD);\r\n\tRELAY_OFF();\r\n\t\r\n\t// Configure output pin that is connected to the FPGA (for modulating)\r\n\tAT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r\n\tAT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;\r\n\r\n\t// Disable modulation, we are going to eavesdrop, not modulate ;)\r\n\tLOW(GPIO_SSC_DOUT);\r\n\t\r\n\t// Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the reader frames\r\n\tAT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);\r\n\tAT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;\r\n\t\r\n // Disable timer during configuration\t\r\n\tAT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;\r\n\t\r\n\t// Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,\r\n\t// external trigger rising edge, load RA on rising edge of TIOA.\r\n\tuint32_t t1_channel_mode = AT91C_TC_CLKS_TIMER_DIV1_CLOCK | AT91C_TC_ETRGEDG_BOTH | AT91C_TC_ABETRG | AT91C_TC_LDRA_BOTH;\r\n\tAT91C_BASE_TC1->TC_CMR = t1_channel_mode;\r\n\t\r\n\t// Enable and reset counter\r\n\tAT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;\r\n\t\r\n\t// Reset the received frame, frame count and timing info\r\n\tmemset(rx,0x00,sizeof(rx));\r\n\tframe_count = 0;\r\n\tresponse = 0;\r\n\toverflow = 0;\r\n\treader_frame = false;\r\n\tlastbit = 1;\r\n\tbSkip = true;\r\n\ttag_sof = 4;\r\n\t\r\n\twhile(!BUTTON_PRESS()) {\r\n\t\t// Watchdog hit\r\n\t\tWDT_HIT();\r\n\t\t\r\n\t\t// Receive frame, watch for at most T0*EOF periods\r\n\t\twhile (AT91C_BASE_TC1->TC_CV < T0*HITAG_T_EOF) {\r\n\t\t\t// Check if rising edge in modulation is detected\r\n\t\t\tif(AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) {\r\n\t\t\t\t// Retrieve the new timing values \r\n\t\t\t\tint ra = (AT91C_BASE_TC1->TC_RA/T0);\r\n\t\t\t\t\r\n\t\t\t\t// Find out if we are dealing with a rising or falling edge\r\n\t\t\t\trising_edge = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME) > 0;\r\n\r\n\t\t\t\t// Shorter periods will only happen with reader frames\r\n\t\t\t\tif (!reader_frame && rising_edge && ra < HITAG_T_TAG_CAPTURE_ONE_HALF) {\r\n\t\t\t\t\t// Switch from tag to reader capture\r\n\t\t\t\t\tLED_C_OFF();\r\n\t\t\t\t\treader_frame = true;\r\n\t\t\t\t\tmemset(rx,0x00,sizeof(rx));\r\n\t\t\t\t\trxlen = 0;\r\n\t\t\t\t}\r\n\t\t\t\t\r\n\t\t\t\t// Only handle if reader frame and rising edge, or tag frame and falling edge\r\n\t\t\t\tif (reader_frame != rising_edge) {\r\n\t\t\t\t overflow += ra;\r\n\t\t\t\t\tcontinue;\r\n\t\t\t\t}\r\n\t\t\t\t\r\n\t\t\t\t// Add the buffered timing values of earlier captured edges which were skipped\r\n\t\t\t\tra += overflow;\r\n\t\t\t\toverflow = 0;\r\n\t\t\t\t\r\n\t\t\t\tif (reader_frame) {\r\n\t\t\t\t\tLED_B_ON();\r\n\t\t\t\t\t// Capture reader frame\r\n\t\t\t\t\tif(ra >= HITAG_T_STOP) {\r\n\t\t\t\t\t\tif (rxlen != 0) {\r\n\t\t\t\t\t\t\t//DbpString(\"wierd0?\");\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\t// Capture the T0 periods that have passed since last communication or field drop (reset)\r\n\t\t\t\t\t\tresponse = (ra - HITAG_T_LOW);\r\n\t\t\t\t\t} else if(ra >= HITAG_T_1_MIN ) {\r\n\t\t\t\t\t\t// '1' bit \r\n\t\t\t\t\t\trx[rxlen / 8] |= 1 << (7-(rxlen%8));\r\n\t\t\t\t\t\trxlen++;\r\n\t\t\t\t\t} else if(ra >= HITAG_T_0_MIN) {\r\n\t\t\t\t\t\t// '0' bit \r\n\t\t\t\t\t\trx[rxlen / 8] |= 0 << (7-(rxlen%8));\r\n\t\t\t\t\t\trxlen++;\r\n\t\t\t\t\t} else {\r\n\t\t\t\t\t\t// Ignore wierd value, is to small to mean anything\r\n\t\t\t\t\t}\r\n\t\t\t\t} else {\r\n\t\t\t\t\tLED_C_ON();\r\n\t\t\t\t\t// Capture tag frame (manchester decoding using only falling edges)\r\n\t\t\t\t\tif(ra >= HITAG_T_EOF) {\r\n\t\t\t\t\t\tif (rxlen != 0) {\r\n\t\t\t\t\t\t\t//DbpString(\"wierd1?\");\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\t// Capture the T0 periods that have passed since last communication or field drop (reset)\r\n\t\t\t\t\t\t// We always recieve a 'one' first, which has the falling edge after a half period |-_|\r\n\t\t\t\t\t\tresponse = ra-HITAG_T_TAG_HALF_PERIOD;\r\n\t\t\t\t\t} else if(ra >= HITAG_T_TAG_CAPTURE_FOUR_HALF) {\r\n\t\t\t\t\t\t// Manchester coding example |-_|_-|-_| (101)\r\n\t\t\t\t\t\trx[rxlen / 8] |= 0 << (7-(rxlen%8));\r\n\t\t\t\t\t\trxlen++;\r\n\t\t\t\t\t\trx[rxlen / 8] |= 1 << (7-(rxlen%8));\r\n\t\t\t\t\t\trxlen++;\r\n\t\t\t\t\t} else if(ra >= HITAG_T_TAG_CAPTURE_THREE_HALF) {\r\n\t\t\t\t\t\t// Manchester coding example |_-|...|_-|-_| (0...01)\r\n\t\t\t\t\t\trx[rxlen / 8] |= 0 << (7-(rxlen%8));\r\n\t\t\t\t\t\trxlen++;\r\n\t\t\t\t\t\t// We have to skip this half period at start and add the 'one' the second time \r\n\t\t\t\t\t\tif (!bSkip) {\r\n\t\t\t\t\t\t\trx[rxlen / 8] |= 1 << (7-(rxlen%8));\r\n\t\t\t\t\t\t\trxlen++;\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\tlastbit = !lastbit;\r\n\t\t\t\t\t\tbSkip = !bSkip;\r\n\t\t\t\t\t} else if(ra >= HITAG_T_TAG_CAPTURE_TWO_HALF) {\r\n\t\t\t\t\t\t// Manchester coding example |_-|_-| (00) or |-_|-_| (11)\r\n\t\t\t\t\t\tif (tag_sof) {\r\n\t\t\t\t\t\t\t// Ignore bits that are transmitted during SOF\r\n\t\t\t\t\t\t\ttag_sof--;\r\n\t\t\t\t\t\t} else {\r\n\t\t\t\t\t\t\t// bit is same as last bit\r\n\t\t\t\t\t\t\trx[rxlen / 8] |= lastbit << (7-(rxlen%8));\r\n\t\t\t\t\t\t\trxlen++;\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t} else {\r\n\t\t\t\t\t\t// Ignore wierd value, is to small to mean anything\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t}\r\n\t\t\r\n\t\t// Check if frame was captured\r\n\t\tif(rxlen > 0) {\r\n\t\t\tframe_count++;\r\n\t\t\tif (!LogTraceHitag(rx,rxlen,response,0,reader_frame)) {\r\n\t\t\t\tDbpString(\"Trace full\");\r\n\t\t\t\tbreak;\r\n\t\t\t}\r\n\r\n\t\t\t// Check if we recognize a valid authentication attempt\r\n\t\t\tif (nbytes(rxlen) == 8) {\r\n\t\t\t\t// Store the authentication attempt\r\n\t\t\t\tif (auth_table_len < (AUTH_TABLE_LENGTH-8)) {\r\n\t\t\t\t\tmemcpy(auth_table+auth_table_len,rx,8);\r\n\t\t\t\t\tauth_table_len += 8;\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\t\r\n\t\t\t// Reset the received frame and response timing info\r\n\t\t\tmemset(rx,0x00,sizeof(rx));\r\n\t\t\tresponse = 0;\r\n\t\t\treader_frame = false;\r\n\t\t\tlastbit = 1;\r\n\t\t\tbSkip = true;\r\n\t\t\ttag_sof = 4;\r\n\t\t\toverflow = 0;\r\n\t\t\t\r\n\t\t\tLED_B_OFF();\r\n\t\t\tLED_C_OFF();\r\n\t\t} else {\r\n\t\t\t// Save the timer overflow, will be 0 when frame was received\r\n\t\t\toverflow += (AT91C_BASE_TC1->TC_CV/T0);\r\n\t\t}\r\n\t\t// Reset the frame length\r\n\t\trxlen = 0;\r\n\t\t// Reset the timer to restart while-loop that receives frames\r\n\t\tAT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG;\r\n\t}\r\n LED_A_ON();\r\n\tLED_B_OFF();\r\n\tLED_C_OFF();\r\n\tLED_D_OFF();\r\n\tAT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;\r\n AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n LED_A_OFF();\r\n\t\r\n//\tDbprintf(\"frame received: %d\",frame_count);\r\n//\tDbprintf(\"Authentication Attempts: %d\",(auth_table_len/8));\r\n//\tDbpString(\"All done\");\r\n}\r\n\r\nvoid SimulateHitagTag(bool tag_mem_supplied, byte_t* data) {\r\n\tint frame_count;\r\n\tint response;\r\n\tint overflow;\r\n\tbyte_t rx[HITAG_FRAME_LEN];\r\n\tsize_t rxlen=0;\r\n\tbyte_t tx[HITAG_FRAME_LEN];\r\n\tsize_t txlen=0;\r\n\tbool bQuitTraceFull = false;\r\n\tbQuiet = false;\r\n\t\r\n\t// Clean up trace and prepare it for storing frames\r\n iso14a_set_tracing(TRUE);\r\n iso14a_clear_trace();\r\n\tauth_table_len = 0;\r\n\tauth_table_pos = 0;\r\n\tmemset(auth_table, 0x00, AUTH_TABLE_LENGTH);\r\n\r\n\tDbpString(\"Starting Hitag2 simulation\");\r\n\tLED_D_ON();\r\n\thitag2_init();\r\n\t\r\n\tif (tag_mem_supplied) {\r\n\t\tDbpString(\"Loading hitag2 memory...\");\r\n\t\tmemcpy((byte_t*)tag.sectors,data,48);\r\n\t}\r\n\r\n\tuint32_t block = 0;\r\n\tfor (size_t i=0; i<12; i++) {\r\n\t\tfor (size_t j=0; j<4; j++) {\r\n\t\t\tblock <<= 8;\r\n\t\t\tblock |= tag.sectors[i][j];\r\n\t\t}\r\n\t\tDbprintf(\"| %d | %08x |\",i,block);\r\n\t}\r\n\t\r\n\t// Set up simulator mode, frequency divisor which will drive the FPGA\r\n\t// and analog mux selection.\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);\r\n\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r\n\tSetAdcMuxFor(GPIO_MUXSEL_LOPKD);\r\n\tRELAY_OFF();\r\n\r\n\t// Configure output pin that is connected to the FPGA (for modulating)\r\n\tAT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r\n\tAT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;\r\n\r\n\t// Disable modulation at default, which means release resistance\r\n\tLOW(GPIO_SSC_DOUT);\r\n\t\r\n\t// Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering\r\n\tAT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0);\r\n\t\r\n\t// Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the reader frames\r\n\tAT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);\r\n\tAT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;\r\n\t\r\n // Disable timer during configuration\t\r\n\tAT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;\r\n\r\n\t// Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,\r\n\t// external trigger rising edge, load RA on rising edge of TIOA.\r\n\tAT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK | AT91C_TC_ETRGEDG_RISING | AT91C_TC_ABETRG | AT91C_TC_LDRA_RISING;\r\n\t\r\n\t// Enable and reset counter\r\n\tAT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;\r\n\r\n\t// Reset the received frame, frame count and timing info\r\n\tmemset(rx,0x00,sizeof(rx));\r\n\tframe_count = 0;\r\n\tresponse = 0;\r\n\toverflow = 0;\r\n\t\r\n\twhile(!BUTTON_PRESS()) {\r\n\t\t// Watchdog hit\r\n\t\tWDT_HIT();\r\n\t\t\r\n\t\t// Receive frame, watch for at most T0*EOF periods\r\n\t\twhile (AT91C_BASE_TC1->TC_CV < T0*HITAG_T_EOF) {\r\n\t\t\t// Check if rising edge in modulation is detected\r\n\t\t\tif(AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) {\r\n\t\t\t\t// Retrieve the new timing values \r\n\t\t\t\tint ra = (AT91C_BASE_TC1->TC_RA/T0) + overflow;\r\n\t\t\t\toverflow = 0;\r\n\r\n\t\t\t\t// Reset timer every frame, we have to capture the last edge for timing\r\n\t\t\t\tAT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;\r\n\t\t\t\t\r\n\t\t\t\tLED_B_ON();\r\n\t\t\t\t\r\n\t\t\t\t// Capture reader frame\r\n\t\t\t\tif(ra >= HITAG_T_STOP) {\r\n\t\t\t\t\tif (rxlen != 0) {\r\n\t\t\t\t\t\t//DbpString(\"wierd0?\");\r\n\t\t\t\t\t}\r\n\t\t\t\t\t// Capture the T0 periods that have passed since last communication or field drop (reset)\r\n\t\t\t\t\tresponse = (ra - HITAG_T_LOW);\r\n\t\t\t\t} else if(ra >= HITAG_T_1_MIN ) {\r\n\t\t\t\t\t// '1' bit \r\n\t\t\t\t\trx[rxlen / 8] |= 1 << (7-(rxlen%8));\r\n\t\t\t\t\trxlen++;\r\n\t\t\t\t} else if(ra >= HITAG_T_0_MIN) {\r\n\t\t\t\t\t// '0' bit \r\n\t\t\t\t\trx[rxlen / 8] |= 0 << (7-(rxlen%8));\r\n\t\t\t\t\trxlen++;\r\n\t\t\t\t} else {\r\n\t\t\t\t\t// Ignore wierd value, is to small to mean anything\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t}\r\n\t\t\r\n\t\t// Check if frame was captured\r\n\t\tif(rxlen > 4) {\r\n\t\t\tframe_count++;\r\n\t\t\tif (!bQuiet) {\r\n\t\t\t\tif (!LogTraceHitag(rx,rxlen,response,0,true)) {\r\n\t\t\t\t\tDbpString(\"Trace full\");\r\n\t\t\t\t\tif (bQuitTraceFull) {\r\n\t\t\t\t\t\tbreak;\r\n\t\t\t\t\t} else {\r\n\t\t\t\t\t\tbQuiet = true;\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\t\r\n\t\t\t// Disable timer 1 with external trigger to avoid triggers during our own modulation\r\n\t\t\tAT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;\r\n\r\n\t\t\t// Process the incoming frame (rx) and prepare the outgoing frame (tx)\r\n\t\t\thitag2_handle_reader_command(rx,rxlen,tx,&txlen);\r\n\t\t\t\r\n\t\t\t// Wait for HITAG_T_WAIT_1 carrier periods after the last reader bit,\r\n\t\t\t// not that since the clock counts since the rising edge, but T_Wait1 is\r\n\t\t\t// with respect to the falling edge, we need to wait actually (T_Wait1 - T_Low)\r\n\t\t\t// periods. The gap time T_Low varies (4..10). All timer values are in \r\n\t\t\t// terms of T0 units\r\n\t\t\twhile(AT91C_BASE_TC0->TC_CV < T0*(HITAG_T_WAIT_1-HITAG_T_LOW));\r\n\r\n\t\t\t// Send and store the tag answer (if there is any)\r\n\t\t\tif (txlen) {\r\n\t\t\t\t// Transmit the tag frame\r\n\t\t\t\thitag_send_frame(tx,txlen);\r\n\t\t\t\t// Store the frame in the trace\r\n\t\t\t\tif (!bQuiet) {\r\n\t\t\t\t\tif (!LogTraceHitag(tx,txlen,0,0,false)) {\r\n\t\t\t\t\t\tDbpString(\"Trace full\");\r\n\t\t\t\t\t\tif (bQuitTraceFull) {\r\n\t\t\t\t\t\t\tbreak;\r\n\t\t\t\t\t\t} else {\r\n\t\t\t\t\t\t\tbQuiet = true;\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\t\r\n\t\t\t// Reset the received frame and response timing info\r\n\t\t\tmemset(rx,0x00,sizeof(rx));\r\n\t\t\tresponse = 0;\r\n\t\t\t\r\n\t\t\t// Enable and reset external trigger in timer for capturing future frames\r\n\t\t\tAT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;\r\n\t\t\tLED_B_OFF();\r\n\t\t}\r\n\t\t// Reset the frame length\r\n\t\trxlen = 0;\r\n\t\t// Save the timer overflow, will be 0 when frame was received\r\n\t\toverflow += (AT91C_BASE_TC1->TC_CV/T0);\r\n\t\t// Reset the timer to restart while-loop that receives frames\r\n\t\tAT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG;\r\n\t}\r\n\tLED_B_OFF();\r\n\tLED_D_OFF();\r\n\tAT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;\r\n\tAT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n//\tDbprintf(\"frame received: %d\",frame_count);\r\n//\tDbprintf(\"Authentication Attempts: %d\",(auth_table_len/8));\r\n//\tDbpString(\"All done\");\r\n}\r\n\r\nvoid ReaderHitag(hitag_function htf, hitag_data* htd) {\r\n\tint frame_count;\r\n\tint response;\r\n\tbyte_t rx[HITAG_FRAME_LEN];\r\n\tsize_t rxlen=0;\r\n\tbyte_t txbuf[HITAG_FRAME_LEN];\r\n\tbyte_t* tx = txbuf;\r\n\tsize_t txlen=0;\r\n\tint lastbit;\r\n\tbool bSkip;\r\n\tint reset_sof; \r\n\tint tag_sof;\r\n\tint t_wait = HITAG_T_WAIT_MAX;\r\n\tbool bStop;\r\n\tbool bQuitTraceFull = false;\r\n \r\n // Reset the return status\r\n bSuccessful = false;\r\n \r\n\t// Clean up trace and prepare it for storing frames\r\n iso14a_set_tracing(TRUE);\r\n iso14a_clear_trace();\r\n\tDbpString(\"Starting Hitag reader family\");\r\n\r\n\t// Check configuration\r\n\tswitch(htf) {\r\n\t\tcase RHT2F_PASSWORD: {\r\n Dbprintf(\"List identifier in password mode\");\r\n\t\t\tmemcpy(password,htd->pwd.password,4);\r\n blocknr = 0;\r\n\t\t\tbQuitTraceFull = false;\r\n\t\t\tbQuiet = false;\r\n\t\t\tbPwd = false;\r\n\t\t} break;\r\n \r\n\t\tcase RHT2F_AUTHENTICATE: {\r\n\t\t\tDbpString(\"Authenticating using nr,ar pair:\");\r\n\t\t\tmemcpy(NrAr,htd->auth.NrAr,8);\r\n\t\t\tDbhexdump(8,NrAr,false);\r\n\t\t\tbQuiet = false;\r\n\t\t\tbCrypto = false;\r\n bAuthenticating = false;\r\n\t\t\tbQuitTraceFull = true;\r\n\t\t} break;\r\n \r\n\t\tcase RHT2F_CRYPTO: {\r\n\t\t\tDbpString(\"Authenticating using key:\");\r\n\t\t\tmemcpy(key,htd->crypto.key,6);\r\n\t\t\tDbhexdump(6,key,false);\r\n blocknr = 0;\r\n\t\t\tbQuiet = false;\r\n\t\t\tbCrypto = false;\r\n bAuthenticating = false;\r\n\t\t\tbQuitTraceFull = true;\r\n\t\t} break;\r\n\r\n\t\tcase RHT2F_TEST_AUTH_ATTEMPTS: {\r\n\t\t\tDbprintf(\"Testing %d authentication attempts\",(auth_table_len/8));\r\n\t\t\tauth_table_pos = 0;\r\n\t\t\tmemcpy(NrAr,auth_table,8);\r\n\t\t\tbQuitTraceFull = false;\r\n\t\t\tbQuiet = false;\r\n\t\t\tbCrypto = false;\r\n\t\t} break;\r\n\t\t\t\r\n\t\tdefault: {\r\n\t\t\tDbprintf(\"Error, unknown function: %d\",htf);\r\n\t\t\treturn;\r\n\t\t} break;\r\n\t}\r\n\t\r\n\tLED_D_ON();\r\n\thitag2_init();\r\n\t\r\n\t// Configure output and enable pin that is connected to the FPGA (for modulating)\r\n\tAT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r\n\tAT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;\r\n\t\r\n\t// Set fpga in edge detect with reader field, we can modulate as reader now\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);\r\n\r\n\t// Set Frequency divisor which will drive the FPGA and analog mux selection\r\n\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r\n\tSetAdcMuxFor(GPIO_MUXSEL_LOPKD);\r\n\tRELAY_OFF();\r\n\r\n\t// Disable modulation at default, which means enable the field\r\n\tLOW(GPIO_SSC_DOUT);\r\n\r\n\t// Give it a bit of time for the resonant antenna to settle.\r\n\tSpinDelay(30);\r\n\t\r\n\t// Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering\r\n\tAT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0);\r\n\r\n\t// Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the tag frames\r\n\tAT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);\r\n\tAT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;\r\n\t\r\n // Disable timer during configuration\t\r\n\tAT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;\r\n\t\r\n\t// Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,\r\n\t// external trigger rising edge, load RA on falling edge of TIOA.\r\n\tAT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK | AT91C_TC_ETRGEDG_FALLING | AT91C_TC_ABETRG | AT91C_TC_LDRA_FALLING;\r\n\t\r\n\t// Enable and reset counters\r\n\tAT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;\r\n\tAT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;\r\n\r\n\t// Reset the received frame, frame count and timing info\r\n\tframe_count = 0;\r\n\tresponse = 0;\r\n\tlastbit = 1;\r\n\tbStop = false;\r\n\r\n // Tag specific configuration settings (sof, timings, etc.)\r\n if (htf < 10){\r\n // hitagS settings\r\n reset_sof = 1;\r\n t_wait = 200;\r\n DbpString(\"Configured for hitagS reader\");\r\n } else if (htf < 20) {\r\n // hitag1 settings\r\n reset_sof = 1;\r\n t_wait = 200;\r\n DbpString(\"Configured for hitag1 reader\");\r\n } else if (htf < 30) {\r\n // hitag2 settings\r\n reset_sof = 4;\r\n t_wait = HITAG_T_WAIT_2;\r\n DbpString(\"Configured for hitag2 reader\");\r\n\t} else {\r\n Dbprintf(\"Error, unknown hitag reader type: %d\",htf);\r\n return;\r\n }\r\n\t\t\r\n\twhile(!bStop && !BUTTON_PRESS()) {\r\n\t\t// Watchdog hit\r\n\t\tWDT_HIT();\r\n\t\t\r\n\t\t// Check if frame was captured and store it\r\n\t\tif(rxlen > 0) {\r\n\t\t\tframe_count++;\r\n\t\t\tif (!bQuiet) {\r\n\t\t\t\tif (!LogTraceHitag(rx,rxlen,response,0,false)) {\r\n\t\t\t\t\tDbpString(\"Trace full\");\r\n\t\t\t\t\tif (bQuitTraceFull) {\r\n\t\t\t\t\t\tbreak;\r\n\t\t\t\t\t} else {\r\n\t\t\t\t\t\tbQuiet = true;\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t}\r\n\t\t\r\n\t\t// By default reset the transmission buffer\r\n\t\ttx = txbuf;\r\n\t\tswitch(htf) {\r\n\t\t\tcase RHT2F_PASSWORD: {\r\n\t\t\t\tbStop = !hitag2_password(rx,rxlen,tx,&txlen);\r\n\t\t\t} break;\r\n\t\t\tcase RHT2F_AUTHENTICATE: {\r\n\t\t\t\tbStop = !hitag2_authenticate(rx,rxlen,tx,&txlen);\r\n\t\t\t} break;\r\n\t\t\tcase RHT2F_CRYPTO: {\r\n\t\t\t\tbStop = !hitag2_crypto(rx,rxlen,tx,&txlen);\r\n\t\t\t} break;\r\n\t\t\tcase RHT2F_TEST_AUTH_ATTEMPTS: {\r\n\t\t\t\tbStop = !hitag2_test_auth_attempts(rx,rxlen,tx,&txlen);\r\n\t\t\t} break;\r\n\t\t\tdefault: {\r\n\t\t\t\tDbprintf(\"Error, unknown function: %d\",htf);\r\n\t\t\t\treturn;\r\n\t\t\t} break;\r\n\t\t}\r\n\t\t\r\n\t\t// Send and store the reader command\r\n\t\t// Disable timer 1 with external trigger to avoid triggers during our own modulation\r\n\t\tAT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;\r\n\t\t\t\r\n\t\t// Wait for HITAG_T_WAIT_2 carrier periods after the last tag bit before transmitting,\r\n\t\t// Since the clock counts since the last falling edge, a 'one' means that the\r\n\t\t// falling edge occured halfway the period. with respect to this falling edge,\r\n\t\t// we need to wait (T_Wait2 + half_tag_period) when the last was a 'one'.\r\n\t\t// All timer values are in terms of T0 units\r\n\t\twhile(AT91C_BASE_TC0->TC_CV < T0*(t_wait+(HITAG_T_TAG_HALF_PERIOD*lastbit)));\r\n\t\t\r\n\t\t// Transmit the reader frame\r\n\t\thitag_reader_send_frame(tx,txlen);\r\n\r\n\t\t// Enable and reset external trigger in timer for capturing future frames\r\n\t\tAT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;\r\n\r\n\t\t// Add transmitted frame to total count\r\n\t\tif(txlen > 0) {\r\n\t\t\tframe_count++;\r\n\t\t\tif (!bQuiet) {\r\n\t\t\t\t// Store the frame in the trace\r\n\t\t\t\tif (!LogTraceHitag(tx,txlen,HITAG_T_WAIT_2,0,true)) {\r\n\t\t\t\t\tif (bQuitTraceFull) {\r\n\t\t\t\t\t\tbreak;\r\n\t\t\t\t\t} else {\r\n\t\t\t\t\t\tbQuiet = true;\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t}\r\n\t\t\t\t\r\n\t\t// Reset values for receiving frames\r\n\t\tmemset(rx,0x00,sizeof(rx));\r\n\t\trxlen = 0;\r\n\t\tlastbit = 1;\r\n\t\tbSkip = true;\r\n\t\ttag_sof = reset_sof;\r\n\t\tresponse = 0;\r\n\t\t\r\n\t\t// Receive frame, watch for at most T0*EOF periods\r\n\t\twhile (AT91C_BASE_TC1->TC_CV < T0*HITAG_T_WAIT_MAX) {\r\n\t\t\t// Check if falling edge in tag modulation is detected\r\n\t\t\tif(AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) {\r\n\t\t\t\t// Retrieve the new timing values \r\n\t\t\t\tint ra = (AT91C_BASE_TC1->TC_RA/T0);\r\n\t\t\t\t\r\n\t\t\t\t// Reset timer every frame, we have to capture the last edge for timing\r\n\t\t\t\tAT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;\r\n\t\t\t\t\r\n\t\t\t\tLED_B_ON();\r\n\t\t\t\t\r\n\t\t\t\t// Capture tag frame (manchester decoding using only falling edges)\r\n\t\t\t\tif(ra >= HITAG_T_EOF) {\r\n\t\t\t\t\tif (rxlen != 0) {\r\n\t\t\t\t\t\t//DbpString(\"wierd1?\");\r\n\t\t\t\t\t}\r\n\t\t\t\t\t// Capture the T0 periods that have passed since last communication or field drop (reset)\r\n\t\t\t\t\t// We always recieve a 'one' first, which has the falling edge after a half period |-_|\r\n\t\t\t\t\tresponse = ra-HITAG_T_TAG_HALF_PERIOD;\r\n\t\t\t\t} else if(ra >= HITAG_T_TAG_CAPTURE_FOUR_HALF) {\r\n\t\t\t\t\t// Manchester coding example |-_|_-|-_| (101)\r\n\t\t\t\t\trx[rxlen / 8] |= 0 << (7-(rxlen%8));\r\n\t\t\t\t\trxlen++;\r\n\t\t\t\t\trx[rxlen / 8] |= 1 << (7-(rxlen%8));\r\n\t\t\t\t\trxlen++;\r\n\t\t\t\t} else if(ra >= HITAG_T_TAG_CAPTURE_THREE_HALF) {\r\n\t\t\t\t\t// Manchester coding example |_-|...|_-|-_| (0...01)\r\n\t\t\t\t\trx[rxlen / 8] |= 0 << (7-(rxlen%8));\r\n\t\t\t\t\trxlen++;\r\n\t\t\t\t\t// We have to skip this half period at start and add the 'one' the second time \r\n\t\t\t\t\tif (!bSkip) {\r\n\t\t\t\t\t\trx[rxlen / 8] |= 1 << (7-(rxlen%8));\r\n\t\t\t\t\t\trxlen++;\r\n\t\t\t\t\t}\r\n\t\t\t\t\tlastbit = !lastbit;\r\n\t\t\t\t\tbSkip = !bSkip;\r\n\t\t\t\t} else if(ra >= HITAG_T_TAG_CAPTURE_TWO_HALF) {\r\n\t\t\t\t\t// Manchester coding example |_-|_-| (00) or |-_|-_| (11)\r\n\t\t\t\t\tif (tag_sof) {\r\n\t\t\t\t\t\t// Ignore bits that are transmitted during SOF\r\n\t\t\t\t\t\ttag_sof--;\r\n\t\t\t\t\t} else {\r\n\t\t\t\t\t\t// bit is same as last bit\r\n\t\t\t\t\t\trx[rxlen / 8] |= lastbit << (7-(rxlen%8));\r\n\t\t\t\t\t\trxlen++;\r\n\t\t\t\t\t}\r\n\t\t\t\t} else {\r\n\t\t\t\t\t// Ignore wierd value, is to small to mean anything\r\n\t\t\t\t}\r\n\t\t\t}\r\n\r\n\t\t\t// We can break this loop if we received the last bit from a frame\r\n\t\t\tif (AT91C_BASE_TC1->TC_CV > T0*HITAG_T_EOF) {\r\n\t\t\t\tif (rxlen>0) break;\r\n\t\t\t}\r\n\t\t}\r\n\t}\r\n\tLED_B_OFF();\r\n\tLED_D_OFF();\r\n\tAT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;\r\n\tAT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\tDbprintf(\"frame received: %d\",frame_count);\r\n DbpString(\"All done\");\r\n cmd_send(CMD_ACK,bSuccessful,0,0,(byte_t*)tag.sectors,48);\r\n}\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/iclass.c", "content": "//-----------------------------------------------------------------------------\n// Gerhard de Koning Gans - May 2008\n// Hagen Fritsch - June 2010\n// Gerhard de Koning Gans - May 2011\n// Gerhard de Koning Gans - June 2012 - Added iClass card and reader emulation\n//\n// This code is licensed to you under the terms of the GNU GPL, version 2 or,\n// at your option, any later version. See the LICENSE.txt file for the text of\n// the license.\n//-----------------------------------------------------------------------------\n// Routines to support iClass.\n//-----------------------------------------------------------------------------\n// Based on ISO14443a implementation. Still in experimental phase.\n// Contribution made during a security research at Radboud University Nijmegen\n// \n// Please feel free to contribute and extend iClass support!!\n//-----------------------------------------------------------------------------\n//\n// FIX:\n// ====\n// We still have sometimes a demodulation error when snooping iClass communication.\n// The resulting trace of a read-block-03 command may look something like this:\n//\n// + 22279: : 0c 03 e8 01 \n//\n// ...with an incorrect answer...\n//\n// + 85: 0: TAG ff! ff! ff! ff! ff! ff! ff! ff! bb 33 bb 00 01! 0e! 04! bb !crc\n//\n// We still left the error signalling bytes in the traces like 0xbb\n//\n// A correct trace should look like this:\n//\n// + 21112: : 0c 03 e8 01 \n// + 85: 0: TAG ff ff ff ff ff ff ff ff ea f5 \n//\n//-----------------------------------------------------------------------------\n\n#include \"proxmark3.h\"\n#include \"apps.h\"\n#include \"util.h\"\n#include \"string.h\"\n#include \"common.h\"\n// Needed for CRC in emulation mode;\n// same construction as in ISO 14443;\n// different initial value (CRC_ICLASS)\n#include \"iso14443crc.h\"\n\nstatic int timeout = 4096;\n\n// CARD TO READER\n// Sequence D: 11110000 modulation with subcarrier during first half\n// Sequence E: 00001111 modulation with subcarrier during second half\n// Sequence F: 00000000 no modulation with subcarrier\n// READER TO CARD\n// Sequence X: 00001100 drop after half a period\n// Sequence Y: 00000000 no drop\n// Sequence Z: 11000000 drop at start\n#define\tSEC_X 0x0c\n#define\tSEC_Y 0x00\n#define\tSEC_Z 0xc0\n\nstatic int SendIClassAnswer(uint8_t *resp, int respLen, int delay);\n\n//-----------------------------------------------------------------------------\n// The software UART that receives commands from the reader, and its state\n// variables.\n//-----------------------------------------------------------------------------\nstatic struct {\n enum {\n STATE_UNSYNCD,\n STATE_START_OF_COMMUNICATION,\n\tSTATE_RECEIVING\n } state;\n uint16_t shiftReg;\n int bitCnt;\n int byteCnt;\n int byteCntMax;\n int posCnt;\n int nOutOfCnt;\n int OutOfCnt;\n int syncBit;\n int parityBits;\n int samples;\n int highCnt;\n int swapper;\n int counter;\n int bitBuffer;\n int dropPosition;\n uint8_t *output;\n} Uart;\n\nstatic RAMFUNC int OutOfNDecoding(int bit)\n{\n\t//int error = 0;\n\tint bitright;\n\n\tif(!Uart.bitBuffer) {\n\t\tUart.bitBuffer = bit ^ 0xFF0;\n\t\treturn FALSE;\n\t}\n\telse {\n\t\tUart.bitBuffer <<= 4;\n\t\tUart.bitBuffer ^= bit;\n\t}\n\t\n\t/*if(Uart.swapper) {\n\t\tUart.output[Uart.byteCnt] = Uart.bitBuffer & 0xFF;\n\t\tUart.byteCnt++;\n\t\tUart.swapper = 0;\n\t\tif(Uart.byteCnt > 15) { return TRUE; }\n\t}\n\telse {\n\t\tUart.swapper = 1;\n\t}*/\n\n\tif(Uart.state != STATE_UNSYNCD) {\n\t\tUart.posCnt++;\n\n\t\tif((Uart.bitBuffer & Uart.syncBit) ^ Uart.syncBit) {\n\t\t\tbit = 0x00;\n\t\t}\n\t\telse {\n\t\t\tbit = 0x01;\n\t\t}\n\t\tif(((Uart.bitBuffer << 1) & Uart.syncBit) ^ Uart.syncBit) {\n\t\t\tbitright = 0x00;\n\t\t}\n\t\telse {\n\t\t\tbitright = 0x01;\n\t\t}\n\t\tif(bit != bitright) { bit = bitright; }\n\n\t\t\n\t\t// So, now we only have to deal with *bit*, lets see...\n\t\tif(Uart.posCnt == 1) {\n\t\t\t// measurement first half bitperiod\n\t\t\tif(!bit) {\n\t\t\t\t// Drop in first half means that we are either seeing\n\t\t\t\t// an SOF or an EOF.\n\n\t\t\t\tif(Uart.nOutOfCnt == 1) {\n\t\t\t\t\t// End of Communication\n\t\t\t\t\tUart.state = STATE_UNSYNCD;\n\t\t\t\t\tUart.highCnt = 0;\n\t\t\t\t\tif(Uart.byteCnt == 0) {\n\t\t\t\t\t\t// Its not straightforward to show single EOFs\n\t\t\t\t\t\t// So just leave it and do not return TRUE\n\t\t\t\t\t\tUart.output[Uart.byteCnt] = 0xf0;\n\t\t\t\t\t\tUart.byteCnt++;\n\n\t\t\t\t\t\t// Calculate the parity bit for the client...\n\t\t\t\t\t\tUart.parityBits = 1;\n\t\t\t\t\t}\n\t\t\t\t\telse {\n\t\t\t\t\t\treturn TRUE;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse if(Uart.state != STATE_START_OF_COMMUNICATION) {\n\t\t\t\t\t// When not part of SOF or EOF, it is an error\n\t\t\t\t\tUart.state = STATE_UNSYNCD;\n\t\t\t\t\tUart.highCnt = 0;\n\t\t\t\t\t//error = 4;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\telse {\n\t\t\t// measurement second half bitperiod\n\t\t\t// Count the bitslot we are in... (ISO 15693)\n\t\t\tUart.nOutOfCnt++;\n\t\t\t\n\t\t\tif(!bit) {\n\t\t\t\tif(Uart.dropPosition) {\n\t\t\t\t\tif(Uart.state == STATE_START_OF_COMMUNICATION) {\n\t\t\t\t\t\t//error = 1;\n\t\t\t\t\t}\n\t\t\t\t\telse {\n\t\t\t\t\t\t//error = 7;\n\t\t\t\t\t}\n\t\t\t\t\t// It is an error if we already have seen a drop in current frame\n\t\t\t\t\tUart.state = STATE_UNSYNCD;\n\t\t\t\t\tUart.highCnt = 0;\n\t\t\t\t}\n\t\t\t\telse {\n\t\t\t\t\tUart.dropPosition = Uart.nOutOfCnt;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tUart.posCnt = 0;\n\n\t\t\t\n\t\t\tif(Uart.nOutOfCnt == Uart.OutOfCnt && Uart.OutOfCnt == 4) {\n\t\t\t\tUart.nOutOfCnt = 0;\n\t\t\t\t\n\t\t\t\tif(Uart.state == STATE_START_OF_COMMUNICATION) {\n\t\t\t\t\tif(Uart.dropPosition == 4) {\n\t\t\t\t\t\tUart.state = STATE_RECEIVING;\n\t\t\t\t\t\tUart.OutOfCnt = 256;\n\t\t\t\t\t}\n\t\t\t\t\telse if(Uart.dropPosition == 3) {\n\t\t\t\t\t\tUart.state = STATE_RECEIVING;\n\t\t\t\t\t\tUart.OutOfCnt = 4;\n\t\t\t\t\t\t//Uart.output[Uart.byteCnt] = 0xdd;\n\t\t\t\t\t\t//Uart.byteCnt++;\n\t\t\t\t\t}\n\t\t\t\t\telse {\n\t\t\t\t\t\tUart.state = STATE_UNSYNCD;\n\t\t\t\t\t\tUart.highCnt = 0;\n\t\t\t\t\t}\n\t\t\t\t\tUart.dropPosition = 0;\n\t\t\t\t}\n\t\t\t\telse {\n\t\t\t\t\t// RECEIVING DATA\n\t\t\t\t\t// 1 out of 4\n\t\t\t\t\tif(!Uart.dropPosition) {\n\t\t\t\t\t\tUart.state = STATE_UNSYNCD;\n\t\t\t\t\t\tUart.highCnt = 0;\n\t\t\t\t\t\t//error = 9;\n\t\t\t\t\t}\n\t\t\t\t\telse {\n\t\t\t\t\t\tUart.shiftReg >>= 2;\n\t\t\t\t\t\t\n\t\t\t\t\t\t// Swap bit order\n\t\t\t\t\t\tUart.dropPosition--;\n\t\t\t\t\t\t//if(Uart.dropPosition == 1) { Uart.dropPosition = 2; }\n\t\t\t\t\t\t//else if(Uart.dropPosition == 2) { Uart.dropPosition = 1; }\n\t\t\t\t\t\t\n\t\t\t\t\t\tUart.shiftReg ^= ((Uart.dropPosition & 0x03) << 6);\n\t\t\t\t\t\tUart.bitCnt += 2;\n\t\t\t\t\t\tUart.dropPosition = 0;\n\n\t\t\t\t\t\tif(Uart.bitCnt == 8) {\n\t\t\t\t\t\t\tUart.output[Uart.byteCnt] = (Uart.shiftReg & 0xff);\n\t\t\t\t\t\t\tUart.byteCnt++;\n\n\t\t\t\t\t\t\t// Calculate the parity bit for the client...\n\t\t\t\t\t\t\tUart.parityBits <<= 1;\n\t\t\t\t\t\t\tUart.parityBits ^= OddByteParity[(Uart.shiftReg & 0xff)];\n\n\t\t\t\t\t\t\tUart.bitCnt = 0;\n\t\t\t\t\t\t\tUart.shiftReg = 0;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\telse if(Uart.nOutOfCnt == Uart.OutOfCnt) {\n\t\t\t\t// RECEIVING DATA\n\t\t\t\t// 1 out of 256\n\t\t\t\tif(!Uart.dropPosition) {\n\t\t\t\t\tUart.state = STATE_UNSYNCD;\n\t\t\t\t\tUart.highCnt = 0;\n\t\t\t\t\t//error = 3;\n\t\t\t\t}\n\t\t\t\telse {\n\t\t\t\t\tUart.dropPosition--;\n\t\t\t\t\tUart.output[Uart.byteCnt] = (Uart.dropPosition & 0xff);\n\t\t\t\t\tUart.byteCnt++;\n\n\t\t\t\t\t// Calculate the parity bit for the client...\n\t\t\t\t\tUart.parityBits <<= 1;\n\t\t\t\t\tUart.parityBits ^= OddByteParity[(Uart.dropPosition & 0xff)];\n\n\t\t\t\t\tUart.bitCnt = 0;\n\t\t\t\t\tUart.shiftReg = 0;\n\t\t\t\t\tUart.nOutOfCnt = 0;\n\t\t\t\t\tUart.dropPosition = 0;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/*if(error) {\n\t\t\t\tUart.output[Uart.byteCnt] = 0xAA;\n\t\t\t\tUart.byteCnt++;\n\t\t\t\tUart.output[Uart.byteCnt] = error & 0xFF;\n\t\t\t\tUart.byteCnt++;\n\t\t\t\tUart.output[Uart.byteCnt] = 0xAA;\n\t\t\t\tUart.byteCnt++;\n\t\t\t\tUart.output[Uart.byteCnt] = (Uart.bitBuffer >> 8) & 0xFF;\n\t\t\t\tUart.byteCnt++;\n\t\t\t\tUart.output[Uart.byteCnt] = Uart.bitBuffer & 0xFF;\n\t\t\t\tUart.byteCnt++;\n\t\t\t\tUart.output[Uart.byteCnt] = (Uart.syncBit >> 3) & 0xFF;\n\t\t\t\tUart.byteCnt++;\n\t\t\t\tUart.output[Uart.byteCnt] = 0xAA;\n\t\t\t\tUart.byteCnt++;\n\t\t\t\treturn TRUE;\n\t\t\t}*/\n\t\t}\n\n\t}\n\telse {\n\t\tbit = Uart.bitBuffer & 0xf0;\n\t\tbit >>= 4;\n\t\tbit ^= 0x0F; // drops become 1s ;-)\n\t\tif(bit) {\n\t\t\t// should have been high or at least (4 * 128) / fc\n\t\t\t// according to ISO this should be at least (9 * 128 + 20) / fc\n\t\t\tif(Uart.highCnt == 8) {\n\t\t\t\t// we went low, so this could be start of communication\n\t\t\t\t// it turns out to be safer to choose a less significant\n\t\t\t\t// syncbit... so we check whether the neighbour also represents the drop\n\t\t\t\tUart.posCnt = 1; // apparently we are busy with our first half bit period\n\t\t\t\tUart.syncBit = bit & 8;\n\t\t\t\tUart.samples = 3;\n\t\t\t\tif(!Uart.syncBit)\t{ Uart.syncBit = bit & 4; Uart.samples = 2; }\n\t\t\t\telse if(bit & 4)\t{ Uart.syncBit = bit & 4; Uart.samples = 2; bit <<= 2; }\n\t\t\t\tif(!Uart.syncBit)\t{ Uart.syncBit = bit & 2; Uart.samples = 1; }\n\t\t\t\telse if(bit & 2)\t{ Uart.syncBit = bit & 2; Uart.samples = 1; bit <<= 1; }\n\t\t\t\tif(!Uart.syncBit)\t{ Uart.syncBit = bit & 1; Uart.samples = 0;\n\t\t\t\t\tif(Uart.syncBit && (Uart.bitBuffer & 8)) {\n\t\t\t\t\t\tUart.syncBit = 8;\n\n\t\t\t\t\t\t// the first half bit period is expected in next sample\n\t\t\t\t\t\tUart.posCnt = 0;\n\t\t\t\t\t\tUart.samples = 3;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse if(bit & 1)\t{ Uart.syncBit = bit & 1; Uart.samples = 0; }\n\n\t\t\t\tUart.syncBit <<= 4;\n\t\t\t\tUart.state = STATE_START_OF_COMMUNICATION;\n\t\t\t\tUart.bitCnt = 0;\n\t\t\t\tUart.byteCnt = 0;\n\t\t\t\tUart.parityBits = 0;\n\t\t\t\tUart.nOutOfCnt = 0;\n\t\t\t\tUart.OutOfCnt = 4; // Start at 1/4, could switch to 1/256\n\t\t\t\tUart.dropPosition = 0;\n\t\t\t\tUart.shiftReg = 0;\n\t\t\t\t//error = 0;\n\t\t\t}\n\t\t\telse {\n\t\t\t\tUart.highCnt = 0;\n\t\t\t}\n\t\t}\n\t\telse {\n\t\t\tif(Uart.highCnt < 8) {\n\t\t\t\tUart.highCnt++;\n\t\t\t}\n\t\t}\n\t}\n\n return FALSE;\n}\n\n//=============================================================================\n// Manchester\n//=============================================================================\n\nstatic struct {\n enum {\n DEMOD_UNSYNCD,\n\t\tDEMOD_START_OF_COMMUNICATION,\n\t\tDEMOD_START_OF_COMMUNICATION2,\n\t\tDEMOD_START_OF_COMMUNICATION3,\n\t\tDEMOD_SOF_COMPLETE,\n\t\tDEMOD_MANCHESTER_D,\n\t\tDEMOD_MANCHESTER_E,\n\t\tDEMOD_END_OF_COMMUNICATION,\n\t\tDEMOD_END_OF_COMMUNICATION2,\n\t\tDEMOD_MANCHESTER_F,\n DEMOD_ERROR_WAIT\n } state;\n int bitCount;\n int posCount;\n\tint syncBit;\n\tint parityBits;\n uint16_t shiftReg;\n\tint buffer;\n\tint buffer2;\n\tint\tbuffer3;\n\tint buff;\n\tint samples;\n int len;\n\tenum {\n\t\tSUB_NONE,\n\t\tSUB_FIRST_HALF,\n\t\tSUB_SECOND_HALF,\n\t\tSUB_BOTH\n\t}\t\tsub;\n uint8_t *output;\n} Demod;\n\nstatic RAMFUNC int ManchesterDecoding(int v)\n{\n\tint bit;\n\tint modulation;\n\tint error = 0;\n\n\tbit = Demod.buffer;\n\tDemod.buffer = Demod.buffer2;\n\tDemod.buffer2 = Demod.buffer3;\n\tDemod.buffer3 = v;\n\n\tif(Demod.buff < 3) {\n\t\tDemod.buff++;\n\t\treturn FALSE;\n\t}\n\n\tif(Demod.state==DEMOD_UNSYNCD) {\n\t\tDemod.output[Demod.len] = 0xfa;\n\t\tDemod.syncBit = 0;\n\t\t//Demod.samples = 0;\n\t\tDemod.posCount = 1;\t\t// This is the first half bit period, so after syncing handle the second part\n\n\t\tif(bit & 0x08) {\n\t\t\tDemod.syncBit = 0x08;\n\t\t}\n\n\t\tif(bit & 0x04) {\n\t\t\tif(Demod.syncBit) {\n\t\t\t\tbit <<= 4;\n\t\t\t}\n\t\t\tDemod.syncBit = 0x04;\n\t\t}\n\n\t\tif(bit & 0x02) {\n\t\t\tif(Demod.syncBit) {\n\t\t\t\tbit <<= 2;\n\t\t\t}\n\t\t\tDemod.syncBit = 0x02;\n\t\t}\n\n\t\tif(bit & 0x01 && Demod.syncBit) {\n\t\t\tDemod.syncBit = 0x01;\n\t\t}\n\t\t\n\t\tif(Demod.syncBit) {\n\t\t\tDemod.len = 0;\n\t\t\tDemod.state = DEMOD_START_OF_COMMUNICATION;\n\t\t\tDemod.sub = SUB_FIRST_HALF;\n\t\t\tDemod.bitCount = 0;\n\t\t\tDemod.shiftReg = 0;\n\t\t\tDemod.parityBits = 0;\n\t\t\tDemod.samples = 0;\n\t\t\tif(Demod.posCount) {\n\t\t\t\t//if(trigger) LED_A_OFF(); // Not useful in this case...\n\t\t\t\tswitch(Demod.syncBit) {\n\t\t\t\t\tcase 0x08: Demod.samples = 3; break;\n\t\t\t\t\tcase 0x04: Demod.samples = 2; break;\n\t\t\t\t\tcase 0x02: Demod.samples = 1; break;\n\t\t\t\t\tcase 0x01: Demod.samples = 0; break;\n\t\t\t\t}\n\t\t\t\t// SOF must be long burst... otherwise stay unsynced!!!\n\t\t\t\tif(!(Demod.buffer & Demod.syncBit) || !(Demod.buffer2 & Demod.syncBit)) {\n\t\t\t\t\tDemod.state = DEMOD_UNSYNCD;\n\t\t\t\t}\n\t\t\t}\n\t\t\telse {\n\t\t\t\t// SOF must be long burst... otherwise stay unsynced!!!\n\t\t\t\tif(!(Demod.buffer2 & Demod.syncBit) || !(Demod.buffer3 & Demod.syncBit)) {\n\t\t\t\t\tDemod.state = DEMOD_UNSYNCD;\n\t\t\t\t\terror = 0x88;\n\t\t\t\t}\n\n\t\t\t}\n\t\t\terror = 0;\n\n\t\t}\n\t}\n\telse {\n\t\tmodulation = bit & Demod.syncBit;\n\t\tmodulation |= ((bit << 1) ^ ((Demod.buffer & 0x08) >> 3)) & Demod.syncBit;\n\t\t//modulation = ((bit << 1) ^ ((Demod.buffer & 0x08) >> 3)) & Demod.syncBit;\n\n\t\tDemod.samples += 4;\n\n\t\tif(Demod.posCount==0) {\n\t\t\tDemod.posCount = 1;\n\t\t\tif(modulation) {\n\t\t\t\tDemod.sub = SUB_FIRST_HALF;\n\t\t\t}\n\t\t\telse {\n\t\t\t\tDemod.sub = SUB_NONE;\n\t\t\t}\n\t\t}\n\t\telse {\n\t\t\tDemod.posCount = 0;\n\t\t\t/*(modulation && (Demod.sub == SUB_FIRST_HALF)) {\n\t\t\t\tif(Demod.state!=DEMOD_ERROR_WAIT) {\n\t\t\t\t\tDemod.state = DEMOD_ERROR_WAIT;\n\t\t\t\t\tDemod.output[Demod.len] = 0xaa;\n\t\t\t\t\terror = 0x01;\n\t\t\t\t}\n\t\t\t}*/\n\t\t\t//else if(modulation) {\n\t\t\tif(modulation) {\n\t\t\t\tif(Demod.sub == SUB_FIRST_HALF) {\n\t\t\t\t\tDemod.sub = SUB_BOTH;\n\t\t\t\t}\n\t\t\t\telse {\n\t\t\t\t\tDemod.sub = SUB_SECOND_HALF;\n\t\t\t\t}\n\t\t\t}\n\t\t\telse if(Demod.sub == SUB_NONE) {\n\t\t\t\tif(Demod.state == DEMOD_SOF_COMPLETE) {\n\t\t\t\t\tDemod.output[Demod.len] = 0x0f;\n\t\t\t\t\tDemod.len++;\n\t\t\t\t\tDemod.parityBits <<= 1;\n\t\t\t\t\tDemod.parityBits ^= OddByteParity[0x0f];\n\t\t\t\t\tDemod.state = DEMOD_UNSYNCD;\n//\t\t\t\t\terror = 0x0f;\n\t\t\t\t\treturn TRUE;\n\t\t\t\t}\n\t\t\t\telse {\n\t\t\t\t\tDemod.state = DEMOD_ERROR_WAIT;\n\t\t\t\t\terror = 0x33;\n\t\t\t\t}\n\t\t\t\t/*if(Demod.state!=DEMOD_ERROR_WAIT) {\n\t\t\t\t\tDemod.state = DEMOD_ERROR_WAIT;\n\t\t\t\t\tDemod.output[Demod.len] = 0xaa;\n\t\t\t\t\terror = 0x01;\n\t\t\t\t}*/\n\t\t\t}\n\n\t\t\tswitch(Demod.state) {\n\t\t\t\tcase DEMOD_START_OF_COMMUNICATION:\n\t\t\t\t\tif(Demod.sub == SUB_BOTH) {\n\t\t\t\t\t\t//Demod.state = DEMOD_MANCHESTER_D;\n\t\t\t\t\t\tDemod.state = DEMOD_START_OF_COMMUNICATION2;\n\t\t\t\t\t\tDemod.posCount = 1;\n\t\t\t\t\t\tDemod.sub = SUB_NONE;\n\t\t\t\t\t}\n\t\t\t\t\telse {\n\t\t\t\t\t\tDemod.output[Demod.len] = 0xab;\n\t\t\t\t\t\tDemod.state = DEMOD_ERROR_WAIT;\n\t\t\t\t\t\terror = 0xd2;\n\t\t\t\t\t}\n\t\t\t\t\tbreak;\n\t\t\t\tcase DEMOD_START_OF_COMMUNICATION2:\n\t\t\t\t\tif(Demod.sub == SUB_SECOND_HALF) {\n\t\t\t\t\t\tDemod.state = DEMOD_START_OF_COMMUNICATION3;\n\t\t\t\t\t}\n\t\t\t\t\telse {\n\t\t\t\t\t\tDemod.output[Demod.len] = 0xab;\n\t\t\t\t\t\tDemod.state = DEMOD_ERROR_WAIT;\n\t\t\t\t\t\terror = 0xd3;\n\t\t\t\t\t}\n\t\t\t\t\tbreak;\n\t\t\t\tcase DEMOD_START_OF_COMMUNICATION3:\n\t\t\t\t\tif(Demod.sub == SUB_SECOND_HALF) {\n//\t\t\t\t\t\tDemod.state = DEMOD_MANCHESTER_D;\n\t\t\t\t\t\tDemod.state = DEMOD_SOF_COMPLETE;\n\t\t\t\t\t\t//Demod.output[Demod.len] = Demod.syncBit & 0xFF;\n\t\t\t\t\t\t//Demod.len++;\n\t\t\t\t\t}\n\t\t\t\t\telse {\n\t\t\t\t\t\tDemod.output[Demod.len] = 0xab;\n\t\t\t\t\t\tDemod.state = DEMOD_ERROR_WAIT;\n\t\t\t\t\t\terror = 0xd4;\n\t\t\t\t\t}\n\t\t\t\t\tbreak;\n\t\t\t\tcase DEMOD_SOF_COMPLETE:\n\t\t\t\tcase DEMOD_MANCHESTER_D:\n\t\t\t\tcase DEMOD_MANCHESTER_E:\n\t\t\t\t\t// OPPOSITE FROM ISO14443 - 11110000 = 0 (1 in 14443)\n\t\t\t\t\t// 00001111 = 1 (0 in 14443)\n\t\t\t\t\tif(Demod.sub == SUB_SECOND_HALF) { // SUB_FIRST_HALF\n\t\t\t\t\t\tDemod.bitCount++;\n\t\t\t\t\t\tDemod.shiftReg = (Demod.shiftReg >> 1) ^ 0x100;\n\t\t\t\t\t\tDemod.state = DEMOD_MANCHESTER_D;\n\t\t\t\t\t}\n\t\t\t\t\telse if(Demod.sub == SUB_FIRST_HALF) { // SUB_SECOND_HALF\n\t\t\t\t\t\tDemod.bitCount++;\n\t\t\t\t\t\tDemod.shiftReg >>= 1;\n\t\t\t\t\t\tDemod.state = DEMOD_MANCHESTER_E;\n\t\t\t\t\t}\n\t\t\t\t\telse if(Demod.sub == SUB_BOTH) {\n\t\t\t\t\t\tDemod.state = DEMOD_MANCHESTER_F;\n\t\t\t\t\t}\n\t\t\t\t\telse {\n\t\t\t\t\t\tDemod.state = DEMOD_ERROR_WAIT;\n\t\t\t\t\t\terror = 0x55;\n\t\t\t\t\t}\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase DEMOD_MANCHESTER_F:\n\t\t\t\t\t// Tag response does not need to be a complete byte!\n\t\t\t\t\tif(Demod.len > 0 || Demod.bitCount > 0) {\n\t\t\t\t\t\tif(Demod.bitCount > 1) { // was > 0, do not interpret last closing bit, is part of EOF\n\t\t\t\t\t\t\tDemod.shiftReg >>= (9 - Demod.bitCount);\n\t\t\t\t\t\t\tDemod.output[Demod.len] = Demod.shiftReg & 0xff;\n\t\t\t\t\t\t\tDemod.len++;\n\t\t\t\t\t\t\t// No parity bit, so just shift a 0\n\t\t\t\t\t\t\tDemod.parityBits <<= 1;\n\t\t\t\t\t\t}\n\n\t\t\t\t\t\tDemod.state = DEMOD_UNSYNCD;\n\t\t\t\t\t\treturn TRUE;\n\t\t\t\t\t}\n\t\t\t\t\telse {\n\t\t\t\t\t\tDemod.output[Demod.len] = 0xad;\n\t\t\t\t\t\tDemod.state = DEMOD_ERROR_WAIT;\n\t\t\t\t\t\terror = 0x03;\n\t\t\t\t\t}\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase DEMOD_ERROR_WAIT:\n\t\t\t\t\tDemod.state = DEMOD_UNSYNCD;\n\t\t\t\t\tbreak;\n\n\t\t\t\tdefault:\n\t\t\t\t\tDemod.output[Demod.len] = 0xdd;\n\t\t\t\t\tDemod.state = DEMOD_UNSYNCD;\n\t\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\t/*if(Demod.bitCount>=9) {\n\t\t\t\tDemod.output[Demod.len] = Demod.shiftReg & 0xff;\n\t\t\t\tDemod.len++;\n\n\t\t\t\tDemod.parityBits <<= 1;\n\t\t\t\tDemod.parityBits ^= ((Demod.shiftReg >> 8) & 0x01);\n\n\t\t\t\tDemod.bitCount = 0;\n\t\t\t\tDemod.shiftReg = 0;\n\t\t\t}*/\n\t\t\tif(Demod.bitCount>=8) {\n\t\t\t\tDemod.shiftReg >>= 1;\n\t\t\t\tDemod.output[Demod.len] = (Demod.shiftReg & 0xff);\n\t\t\t\tDemod.len++;\n\n\t\t\t\t// FOR ISO15639 PARITY NOT SEND OTA, JUST CALCULATE IT FOR THE CLIENT\n\t\t\t\tDemod.parityBits <<= 1;\n\t\t\t\tDemod.parityBits ^= OddByteParity[(Demod.shiftReg & 0xff)];\n\n\t\t\t\tDemod.bitCount = 0;\n\t\t\t\tDemod.shiftReg = 0;\n\t\t\t}\n\n\t\t\tif(error) {\n\t\t\t\tDemod.output[Demod.len] = 0xBB;\n\t\t\t\tDemod.len++;\n\t\t\t\tDemod.output[Demod.len] = error & 0xFF;\n\t\t\t\tDemod.len++;\n\t\t\t\tDemod.output[Demod.len] = 0xBB;\n\t\t\t\tDemod.len++;\n\t\t\t\tDemod.output[Demod.len] = bit & 0xFF;\n\t\t\t\tDemod.len++;\n\t\t\t\tDemod.output[Demod.len] = Demod.buffer & 0xFF;\n\t\t\t\tDemod.len++;\n\t\t\t\t// Look harder ;-)\n\t\t\t\tDemod.output[Demod.len] = Demod.buffer2 & 0xFF;\n\t\t\t\tDemod.len++;\n\t\t\t\tDemod.output[Demod.len] = Demod.syncBit & 0xFF;\n\t\t\t\tDemod.len++;\n\t\t\t\tDemod.output[Demod.len] = 0xBB;\n\t\t\t\tDemod.len++;\n\t\t\t\treturn TRUE;\n\t\t\t}\n\n\t\t}\n\n\t} // end (state != UNSYNCED)\n\n return FALSE;\n}\n\n//=============================================================================\n// Finally, a `sniffer' for iClass communication\n// Both sides of communication!\n//=============================================================================\n\n//-----------------------------------------------------------------------------\n// Record the sequence of commands sent by the reader to the tag, with\n// triggering so that we start recording at the point that the tag is moved\n// near the reader.\n//-----------------------------------------------------------------------------\nvoid RAMFUNC SnoopIClass(void)\n{\n// DEFINED ABOVE\n// #define RECV_CMD_OFFSET 3032\n// #define RECV_RES_OFFSET 3096\n// #define DMA_BUFFER_OFFSET 3160\n// #define DMA_BUFFER_SIZE 4096\n// #define TRACE_SIZE 3000\n\n // We won't start recording the frames that we acquire until we trigger;\n // a good trigger condition to get started is probably when we see a\n // response from the tag.\n //int triggered = FALSE; // FALSE to wait first for card\n\n // The command (reader -> tag) that we're receiving.\n\t// The length of a received command will in most cases be no more than 18 bytes.\n\t// So 32 should be enough!\n uint8_t *receivedCmd = (((uint8_t *)BigBuf) + RECV_CMD_OFFSET);\n // The response (tag -> reader) that we're receiving.\n uint8_t *receivedResponse = (((uint8_t *)BigBuf) + RECV_RES_OFFSET);\n\n // As we receive stuff, we copy it from receivedCmd or receivedResponse\n // into trace, along with its length and other annotations.\n //uint8_t *trace = (uint8_t *)BigBuf;\n \n // reset traceLen to 0\n iso14a_set_tracing(TRUE);\n iso14a_clear_trace();\n iso14a_set_trigger(FALSE);\n\n // The DMA buffer, used to stream samples from the FPGA\n int8_t *dmaBuf = ((int8_t *)BigBuf) + DMA_BUFFER_OFFSET;\n int lastRxCounter;\n int8_t *upTo;\n int smpl;\n int maxBehindBy = 0;\n\n // Count of samples received so far, so that we can include timing\n // information in the trace buffer.\n int samples = 0;\n rsamples = 0;\n\n memset(trace, 0x44, RECV_CMD_OFFSET);\n\n // Set up the demodulator for tag -> reader responses.\n Demod.output = receivedResponse;\n Demod.len = 0;\n Demod.state = DEMOD_UNSYNCD;\n\n // Setup for the DMA.\n FpgaSetupSsc();\n upTo = dmaBuf;\n lastRxCounter = DMA_BUFFER_SIZE;\n FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);\n\n // And the reader -> tag commands\n memset(&Uart, 0, sizeof(Uart));\n Uart.output = receivedCmd;\n Uart.byteCntMax = 32; // was 100 (greg)////////////////////////////////////////////////////////////////////////\n Uart.state = STATE_UNSYNCD;\n\n // And put the FPGA in the appropriate mode\n // Signal field is off with the appropriate LED\n LED_D_OFF();\n FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_SNIFFER);\n SetAdcMuxFor(GPIO_MUXSEL_HIPKD);\n\n int div = 0;\n //int div2 = 0;\n int decbyte = 0;\n int decbyter = 0;\n\n // And now we loop, receiving samples.\n for(;;) {\n LED_A_ON();\n WDT_HIT();\n int behindBy = (lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) &\n (DMA_BUFFER_SIZE-1);\n if(behindBy > maxBehindBy) {\n maxBehindBy = behindBy;\n if(behindBy > 400) {\n Dbprintf(\"blew circular buffer! behindBy=0x%x\", behindBy);\n goto done;\n }\n }\n if(behindBy < 1) continue;\n\n\tLED_A_OFF();\n smpl = upTo[0];\n upTo++;\n lastRxCounter -= 1;\n if(upTo - dmaBuf > DMA_BUFFER_SIZE) {\n upTo -= DMA_BUFFER_SIZE;\n lastRxCounter += DMA_BUFFER_SIZE;\n AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;\n AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;\n }\n\n //samples += 4;\n\tsamples += 1;\n\t//div2++;\t\n\n\t//if(div2 > 3) {\n\t\t//div2 = 0;\n\t//decbyte ^= ((smpl & 0x01) << (3 - div));\n\t//decbyte ^= (((smpl & 0x01) | ((smpl & 0x02) >> 1)) << (3 - div)); // better already...\n\t//decbyte ^= (((smpl & 0x01) | ((smpl & 0x02) >> 1) | ((smpl & 0x04) >> 2)) << (3 - div)); // even better...\n\tif(smpl & 0xF) {\n\t\tdecbyte ^= (1 << (3 - div));\n\t}\n\t//decbyte ^= (MajorityNibble[(smpl & 0x0F)] << (3 - div));\n\t\n\t// FOR READER SIDE COMMUMICATION...\n\t//decbyte ^= ((smpl & 0x10) << (3 - div));\n\tdecbyter <<= 2;\n\tdecbyter ^= (smpl & 0x30);\n\n\tdiv++;\n\t\n\tif((div + 1) % 2 == 0) {\n\t\tsmpl = decbyter;\t\n\t\tif(OutOfNDecoding((smpl & 0xF0) >> 4)) {\n\t\t rsamples = samples - Uart.samples;\n\t\t LED_C_ON();\n\t\t //if(triggered) {\n\t\t\ttrace[traceLen++] = ((rsamples >> 0) & 0xff);\n\t\t\ttrace[traceLen++] = ((rsamples >> 8) & 0xff);\n\t\t\ttrace[traceLen++] = ((rsamples >> 16) & 0xff);\n\t\t\ttrace[traceLen++] = ((rsamples >> 24) & 0xff);\n\t\t\ttrace[traceLen++] = ((Uart.parityBits >> 0) & 0xff);\n\t\t\ttrace[traceLen++] = ((Uart.parityBits >> 8) & 0xff);\n\t\t\ttrace[traceLen++] = ((Uart.parityBits >> 16) & 0xff);\n\t\t\ttrace[traceLen++] = ((Uart.parityBits >> 24) & 0xff);\n\t\t\ttrace[traceLen++] = Uart.byteCnt;\n\t\t\tmemcpy(trace+traceLen, receivedCmd, Uart.byteCnt);\n\t\t\ttraceLen += Uart.byteCnt;\n\t\t\tif(traceLen > TRACE_SIZE) break;\n\t\t //}\n\t\t /* And ready to receive another command. */\n\t\t Uart.state = STATE_UNSYNCD;\n\t\t /* And also reset the demod code, which might have been */\n\t\t /* false-triggered by the commands from the reader. */\n\t\t Demod.state = DEMOD_UNSYNCD;\n\t\t LED_B_OFF();\n\t\t Uart.byteCnt = 0;\n\t\t}\n\t\tdecbyter = 0;\n\t}\n\n\tif(div > 3) {\n\t\tsmpl = decbyte;\n\t\tif(ManchesterDecoding(smpl & 0x0F)) {\n\t\t rsamples = samples - Demod.samples;\n\t\t LED_B_ON();\n\n\t\t // timestamp, as a count of samples\n\t\t trace[traceLen++] = ((rsamples >> 0) & 0xff);\n\t\t trace[traceLen++] = ((rsamples >> 8) & 0xff);\n\t\t trace[traceLen++] = ((rsamples >> 16) & 0xff);\n\t\t trace[traceLen++] = 0x80 | ((rsamples >> 24) & 0xff);\n\t\t trace[traceLen++] = ((Demod.parityBits >> 0) & 0xff);\n\t\t trace[traceLen++] = ((Demod.parityBits >> 8) & 0xff);\n\t\t trace[traceLen++] = ((Demod.parityBits >> 16) & 0xff);\n\t\t trace[traceLen++] = ((Demod.parityBits >> 24) & 0xff);\n\t\t // length\n\t\t trace[traceLen++] = Demod.len;\n\t\t memcpy(trace+traceLen, receivedResponse, Demod.len);\n\t\t traceLen += Demod.len;\n\t\t if(traceLen > TRACE_SIZE) break;\n\n\t\t //triggered = TRUE;\n\n\t\t // And ready to receive another response.\n\t\t memset(&Demod, 0, sizeof(Demod));\n\t\t Demod.output = receivedResponse;\n\t\t Demod.state = DEMOD_UNSYNCD;\n\t\t LED_C_OFF();\n\t\t}\n\t\t\n\t\tdiv = 0;\n\t\tdecbyte = 0x00;\n\t}\n\t//}\n\n if(BUTTON_PRESS()) {\n DbpString(\"cancelled_a\");\n goto done;\n }\n }\n\n DbpString(\"COMMAND FINISHED\");\n\n Dbprintf(\"%x %x %x\", maxBehindBy, Uart.state, Uart.byteCnt);\n Dbprintf(\"%x %x %x\", Uart.byteCntMax, traceLen, (int)Uart.output[0]);\n\ndone:\n AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;\n Dbprintf(\"%x %x %x\", maxBehindBy, Uart.state, Uart.byteCnt);\n Dbprintf(\"%x %x %x\", Uart.byteCntMax, traceLen, (int)Uart.output[0]);\n LED_A_OFF();\n LED_B_OFF();\n LED_C_OFF();\n LED_D_OFF();\n}\n\nvoid rotateCSN(uint8_t* originalCSN, uint8_t* rotatedCSN) {\n\tint i; \n\tfor(i = 0; i < 8; i++) {\n\t\trotatedCSN[i] = (originalCSN[i] >> 3) | (originalCSN[(i+1)%8] << 5);\n\t}\n}\n\n//-----------------------------------------------------------------------------\n// Wait for commands from reader\n// Stop when button is pressed\n// Or return TRUE when command is captured\n//-----------------------------------------------------------------------------\nstatic int GetIClassCommandFromReader(uint8_t *received, int *len, int maxLen)\n{\n // Set FPGA mode to \"simulated ISO 14443 tag\", no modulation (listen\n // only, since we are receiving, not transmitting).\n // Signal field is off with the appropriate LED\n LED_D_OFF();\n FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);\n\n // Now run a `software UART' on the stream of incoming samples.\n Uart.output = received;\n Uart.byteCntMax = maxLen;\n Uart.state = STATE_UNSYNCD;\n\n for(;;) {\n WDT_HIT();\n\n if(BUTTON_PRESS()) return FALSE;\n\n if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\n AT91C_BASE_SSC->SSC_THR = 0x00;\n }\n if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\n uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;\n\t\t\t/*if(OutOfNDecoding((b & 0xf0) >> 4)) {\n\t\t\t\t*len = Uart.byteCnt;\n\t\t\t\treturn TRUE;\n\t\t\t}*/\n\t\t\tif(OutOfNDecoding(b & 0x0f)) {\n\t\t\t\t*len = Uart.byteCnt;\n\t\t\t\treturn TRUE;\n\t\t\t}\n }\n }\n}\n\n\n//-----------------------------------------------------------------------------\n// Prepare tag messages\n//-----------------------------------------------------------------------------\nstatic void CodeIClassTagAnswer(const uint8_t *cmd, int len)\n{\n\tint i;\n\n\tToSendReset();\n\n\t// Send SOF\n\tToSend[++ToSendMax] = 0x00;\n\tToSend[++ToSendMax] = 0x00;\n\tToSend[++ToSendMax] = 0x00;\n\tToSend[++ToSendMax] = 0xff;\n\tToSend[++ToSendMax] = 0xff;\n\tToSend[++ToSendMax] = 0xff;\n\tToSend[++ToSendMax] = 0x00;\n\tToSend[++ToSendMax] = 0xff;\n\n\tfor(i = 0; i < len; i++) {\n\t\tint j;\n\t\tuint8_t b = cmd[i];\n\n\t\t// Data bits\n\t\tfor(j = 0; j < 8; j++) {\n\t\t\tif(b & 1) {\n\t\t\t\tToSend[++ToSendMax] = 0x00;\n\t\t\t\tToSend[++ToSendMax] = 0xff;\n\t\t\t} else {\n\t\t\t\tToSend[++ToSendMax] = 0xff;\n\t\t\t\tToSend[++ToSendMax] = 0x00;\n\t\t\t}\n\t\t\tb >>= 1;\n\t\t}\n\t}\n\n\t// Send EOF\n\tToSend[++ToSendMax] = 0xff;\n\tToSend[++ToSendMax] = 0x00;\n\tToSend[++ToSendMax] = 0xff;\n\tToSend[++ToSendMax] = 0xff;\n\tToSend[++ToSendMax] = 0xff;\n\tToSend[++ToSendMax] = 0x00;\n\tToSend[++ToSendMax] = 0x00;\n\tToSend[++ToSendMax] = 0x00;\n\n\t// Convert from last byte pos to length\n\tToSendMax++;\n}\n\n// Only SOF \nstatic void CodeIClassTagSOF()\n{\n\tToSendReset();\n\n\t// Send SOF\n\tToSend[++ToSendMax] = 0x00;\n\tToSend[++ToSendMax] = 0x00;\n\tToSend[++ToSendMax] = 0x00;\n\tToSend[++ToSendMax] = 0xff;\n\tToSend[++ToSendMax] = 0xff;\n\tToSend[++ToSendMax] = 0xff;\n\tToSend[++ToSendMax] = 0x00;\n\tToSend[++ToSendMax] = 0xff;\n\t\n\t// Convert from last byte pos to length\n\tToSendMax++;\n}\n\n//-----------------------------------------------------------------------------\n// Simulate iClass Card\n// Only CSN (Card Serial Number)\n// \n//-----------------------------------------------------------------------------\nvoid SimulateIClass(uint8_t arg0, uint8_t *datain)\n{\n\tuint8_t simType = arg0;\n\n // Enable and clear the trace\n\ttracing = TRUE;\n\ttraceLen = 0;\n memset(trace, 0x44, TRACE_SIZE);\n\n\t// CSN followed by two CRC bytes\n\tuint8_t response2[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };\n\tuint8_t response3[] = { 0x03, 0x1f, 0xec, 0x8a, 0xf7, 0xff, 0x12, 0xe0, 0x00, 0x00 };\n\n\t// e-Purse\n\tuint8_t response4[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };\n\n\tif(simType == 0) {\n\t\t// Use the CSN from commandline\n\t\tmemcpy(response3, datain, 8);\n\t}\n\n\t// Construct anticollision-CSN\n\trotateCSN(response3,response2);\n\n\t// Compute CRC on both CSNs\n\tComputeCrc14443(CRC_ICLASS, response2, 8, &response2[8], &response2[9]);\n\tComputeCrc14443(CRC_ICLASS, response3, 8, &response3[8], &response3[9]);\n\n\t// Reader 0a\n\t// Tag 0f\n\t// Reader 0c\n\t// Tag anticoll. CSN\n\t// Reader 81 anticoll. CSN\n\t// Tag CSN\n\n\tuint8_t *resp;\n\tint respLen;\n\tuint8_t* respdata = NULL;\n\tint respsize = 0;\n\tuint8_t sof = 0x0f;\n\n\t// Respond SOF -- takes 8 bytes\n\tuint8_t *resp1 = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET);\n\tint resp1Len;\n\n\t// Anticollision CSN (rotated CSN)\n\t// 176: Takes 16 bytes for SOF/EOF and 10 * 16 = 160 bytes (2 bytes/bit)\n\tuint8_t *resp2 = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET + 10);\n\tint resp2Len;\n\n\t// CSN\n\t// 176: Takes 16 bytes for SOF/EOF and 10 * 16 = 160 bytes (2 bytes/bit)\n\tuint8_t *resp3 = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET + 190);\n\tint resp3Len;\n\n\t// e-Purse\n\t// 144: Takes 16 bytes for SOF/EOF and 8 * 16 = 128 bytes (2 bytes/bit)\n\tuint8_t *resp4 = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET + 370);\n\tint resp4Len;\n\n\t// + 1720..\n uint8_t *receivedCmd = (((uint8_t *)BigBuf) + RECV_CMD_OFFSET);\n\tmemset(receivedCmd, 0x44, RECV_CMD_SIZE);\n\tint len;\n\n\t// Prepare card messages\n\tToSendMax = 0;\n\n\t// First card answer: SOF\n\tCodeIClassTagSOF();\n\tmemcpy(resp1, ToSend, ToSendMax); resp1Len = ToSendMax;\n\n\t// Anticollision CSN\n\tCodeIClassTagAnswer(response2, sizeof(response2));\n\tmemcpy(resp2, ToSend, ToSendMax); resp2Len = ToSendMax;\n\n\t// CSN\n\tCodeIClassTagAnswer(response3, sizeof(response3));\n\tmemcpy(resp3, ToSend, ToSendMax); resp3Len = ToSendMax;\n\n\t// e-Purse\n\tCodeIClassTagAnswer(response4, sizeof(response4));\n\tmemcpy(resp4, ToSend, ToSendMax); resp4Len = ToSendMax;\n\n\t// We need to listen to the high-frequency, peak-detected path.\n\tSetAdcMuxFor(GPIO_MUXSEL_HIPKD);\n\tFpgaSetupSsc();\n\n\t// To control where we are in the protocol\n\tint cmdsRecvd = 0;\n\n\tLED_A_ON();\n\tfor(;;) {\n\t\tLED_B_OFF();\n\t\tif(!GetIClassCommandFromReader(receivedCmd, &len, 100)) {\n\t\t\tDbpString(\"button press\");\n\t\t\tbreak;\n\t\t}\n\n\t\t// Okay, look at the command now.\n\t\tif(receivedCmd[0] == 0x0a) {\n\t\t\t// Reader in anticollission phase\n\t\t\tresp = resp1; respLen = resp1Len; //order = 1;\n\t\t\trespdata = &sof;\n\t\t\trespsize = sizeof(sof);\n\t\t\t//resp = resp2; respLen = resp2Len; order = 2;\n\t\t\t//DbpString(\"Hello request from reader:\");\n\t\t} else if(receivedCmd[0] == 0x0c) {\n\t\t\t// Reader asks for anticollission CSN\n\t\t\tresp = resp2; respLen = resp2Len; //order = 2;\n\t\t\trespdata = response2;\n\t\t\trespsize = sizeof(response2);\n\t\t\t//DbpString(\"Reader requests anticollission CSN:\");\n\t\t} else if(receivedCmd[0] == 0x81) {\n\t\t\t// Reader selects anticollission CSN.\n\t\t\t// Tag sends the corresponding real CSN\n\t\t\tresp = resp3; respLen = resp3Len; //order = 3;\n\t\t\trespdata = response3;\n\t\t\trespsize = sizeof(response3);\n\t\t\t//DbpString(\"Reader selects anticollission CSN:\");\n\t\t} else if(receivedCmd[0] == 0x88) {\n\t\t\t// Read e-purse (88 02)\n\t\t\tresp = resp4; respLen = resp4Len; //order = 4;\n\t\t\trespdata = response4;\n\t\t\trespsize = sizeof(response4);\n\t\t\tLED_B_ON();\n\t\t} else if(receivedCmd[0] == 0x05) {\n\t\t\t// Reader random and reader MAC!!!\n\t\t\t// Lets store this ;-)\n/*\n\t\t\tDbprintf(\" CSN: %02x %02x %02x %02x %02x %02x %02x %02x\",\n\t\t\tresponse3[0], response3[1], response3[2],\n\t\t\tresponse3[3], response3[4], response3[5],\n\t\t\tresponse3[6], response3[7]);\n*/\t\t\t\n\t\t\tDbprintf(\"READER AUTH (len=%02d): %02x %02x %02x %02x %02x %02x %02x %02x %02x\",\n\t\t\tlen,\n\t\t\treceivedCmd[0], receivedCmd[1], receivedCmd[2],\n\t\t\treceivedCmd[3], receivedCmd[4], receivedCmd[5],\n\t\t\treceivedCmd[6], receivedCmd[7], receivedCmd[8]);\n\n\t\t\t// Do not respond\n\t\t\t// We do not know what to answer, so lets keep quit\n\t\t\tresp = resp1; respLen = 0; //order = 5;\n\t\t\trespdata = NULL;\n\t\t\trespsize = 0;\n\t\t} else if(receivedCmd[0] == 0x00 && len == 1) {\n\t\t\t// Reader ends the session\n\t\t\tresp = resp1; respLen = 0; //order = 0;\n\t\t\trespdata = NULL;\n\t\t\trespsize = 0;\n\t\t} else {\n\t\t\t// Never seen this command before\n\t\t\tDbprintf(\"Unknown command received from reader (len=%d): %x %x %x %x %x %x %x %x %x\",\n\t\t\tlen,\n\t\t\treceivedCmd[0], receivedCmd[1], receivedCmd[2],\n\t\t\treceivedCmd[3], receivedCmd[4], receivedCmd[5],\n\t\t\treceivedCmd[6], receivedCmd[7], receivedCmd[8]);\n\t\t\t// Do not respond\n\t\t\tresp = resp1; respLen = 0; //order = 0;\n\t\t\trespdata = NULL;\n\t\t\trespsize = 0;\n\t\t}\n\n\t\tif(cmdsRecvd > 999) {\n\t\t\tDbpString(\"1000 commands later...\");\n\t\t\tbreak;\n\t\t}\n\t\telse {\n\t\t\tcmdsRecvd++;\n\t\t}\n\n\t\tif(respLen > 0) {\n\t\t\tSendIClassAnswer(resp, respLen, 21);\n\t\t}\n\t\t\n\t\tif (tracing) {\n\t\t\tLogTrace(receivedCmd,len, 0, Uart.parityBits, TRUE);\n\t\t\tif (respdata != NULL) {\n\t\t\t\tLogTrace(respdata,respsize, 0, SwapBits(GetParity(respdata,respsize),respsize), FALSE);\n\t\t\t}\n\t\t\tif(traceLen > TRACE_SIZE) {\n\t\t\t\tDbpString(\"Trace full\");\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tmemset(receivedCmd, 0x44, RECV_CMD_SIZE);\n\t}\n\n\tDbprintf(\"%x\", cmdsRecvd);\n\tLED_A_OFF();\n\tLED_B_OFF();\n}\n\nstatic int SendIClassAnswer(uint8_t *resp, int respLen, int delay)\n{\n\tint i = 0, u = 0, d = 0;\n\tuint8_t b = 0;\n\t// return 0;\n\t// Modulate Manchester\n\t// FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD424);\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);\n\tAT91C_BASE_SSC->SSC_THR = 0x00;\n\tFpgaSetupSsc();\n\t\n\t// send cycle\n\tfor(;;) {\n\t\tif(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\n\t\t\tvolatile uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;\n\t\t\t(void)b;\n\t\t}\n\t\tif(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\n\t\t\tif(d < delay) {\n\t\t\t\tb = 0x00;\n\t\t\t\td++;\n\t\t\t}\n\t\t\telse if(i >= respLen) {\n\t\t\t\tb = 0x00;\n\t\t\t\tu++;\n\t\t\t} else {\n\t\t\t\tb = resp[i];\n\t\t\t\tu++;\n\t\t\t\tif(u > 1) { i++; u = 0; }\n\t\t\t}\n\t\t\tAT91C_BASE_SSC->SSC_THR = b;\n\n\t\t\tif(u > 4) break;\n\t\t}\n\t\tif(BUTTON_PRESS()) {\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/// THE READER CODE\n\n//-----------------------------------------------------------------------------\n// Transmit the command (to the tag) that was placed in ToSend[].\n//-----------------------------------------------------------------------------\nstatic void TransmitIClassCommand(const uint8_t *cmd, int len, int *samples, int *wait)\n{\n int c;\n\n FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);\n AT91C_BASE_SSC->SSC_THR = 0x00;\n FpgaSetupSsc();\n\n if (wait)\n if(*wait < 10)\n *wait = 10;\n\n for(c = 0; c < *wait;) {\n if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\n AT91C_BASE_SSC->SSC_THR = 0x00;\t\t// For exact timing!\n c++;\n }\n if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\n volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;\n (void)r;\n }\n WDT_HIT();\n }\n\n uint8_t sendbyte;\n bool firstpart = TRUE;\n c = 0;\n for(;;) {\n if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\n\n // DOUBLE THE SAMPLES!\n if(firstpart) {\n\tsendbyte = (cmd[c] & 0xf0) | (cmd[c] >> 4); \n }\n else {\n\tsendbyte = (cmd[c] & 0x0f) | (cmd[c] << 4);\n c++;\n }\n if(sendbyte == 0xff) {\n\tsendbyte = 0xfe;\n }\n AT91C_BASE_SSC->SSC_THR = sendbyte;\n firstpart = !firstpart;\n\n if(c >= len) {\n break;\n }\n }\n if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\n volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;\n (void)r;\n }\n WDT_HIT();\n }\n if (samples) *samples = (c + *wait) << 3;\n}\n\n\n//-----------------------------------------------------------------------------\n// Prepare iClass reader command to send to FPGA\n//-----------------------------------------------------------------------------\nvoid CodeIClassCommand(const uint8_t * cmd, int len)\n{\n int i, j, k;\n uint8_t b;\n\n ToSendReset();\n\n // Start of Communication: 1 out of 4\n ToSend[++ToSendMax] = 0xf0;\n ToSend[++ToSendMax] = 0x00;\n ToSend[++ToSendMax] = 0x0f;\n ToSend[++ToSendMax] = 0x00;\n\n // Modulate the bytes \n for (i = 0; i < len; i++) {\n b = cmd[i];\n for(j = 0; j < 4; j++) {\n for(k = 0; k < 4; k++) {\n\tif(k == (b & 3)) {\n\t ToSend[++ToSendMax] = 0x0f;\n\t}\n\telse {\n\t ToSend[++ToSendMax] = 0x00;\n\t}\n }\n b >>= 2;\n }\n }\n\n // End of Communication\n ToSend[++ToSendMax] = 0x00;\n ToSend[++ToSendMax] = 0x00;\n ToSend[++ToSendMax] = 0xf0;\n ToSend[++ToSendMax] = 0x00;\n\n // Convert from last character reference to length\n ToSendMax++;\n}\n\nvoid ReaderTransmitIClass(uint8_t* frame, int len)\n{\n int wait = 0;\n int samples = 0;\n int par = 0;\n\n // This is tied to other size changes\n // \tuint8_t* frame_addr = ((uint8_t*)BigBuf) + 2024;\n CodeIClassCommand(frame,len);\n\n // Select the card\n TransmitIClassCommand(ToSend, ToSendMax, &samples, &wait);\n if(trigger)\n \tLED_A_ON();\n\n // Store reader command in buffer\n if (tracing) LogTrace(frame,len,0,par,TRUE);\n}\n\n//-----------------------------------------------------------------------------\n// Wait a certain time for tag response\n// If a response is captured return TRUE\n// If it takes too long return FALSE\n//-----------------------------------------------------------------------------\nstatic int GetIClassAnswer(uint8_t *receivedResponse, int maxLen, int *samples, int *elapsed) //uint8_t *buffer\n{\n\t// buffer needs to be 512 bytes\n\tint c;\n\n\t// Set FPGA mode to \"reader listen mode\", no modulation (listen\n\t// only, since we are receiving, not transmitting).\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);\n\n\t// Now get the answer from the card\n\tDemod.output = receivedResponse;\n\tDemod.len = 0;\n\tDemod.state = DEMOD_UNSYNCD;\n\n\tuint8_t b;\n\tif (elapsed) *elapsed = 0;\n\n\tbool skip = FALSE;\n\n\tc = 0;\n\tfor(;;) {\n\t\tWDT_HIT();\n\n\t if(BUTTON_PRESS()) return FALSE;\n\n\t\tif(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\n\t\t\tAT91C_BASE_SSC->SSC_THR = 0x00; // To make use of exact timing of next command from reader!!\n\t\t\tif (elapsed) (*elapsed)++;\n\t\t}\n\t\tif(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\n\t\t\tif(c < timeout) { c++; } else { return FALSE; }\n\t\t\tb = (uint8_t)AT91C_BASE_SSC->SSC_RHR;\n\t\t\tskip = !skip;\n\t\t\tif(skip) continue;\n\t\t\t/*if(ManchesterDecoding((b>>4) & 0xf)) {\n\t\t\t\t*samples = ((c - 1) << 3) + 4;\n\t\t\t\treturn TRUE;\n\t\t\t}*/\n\t\t\tif(ManchesterDecoding(b & 0x0f)) {\n\t\t\t\t*samples = c << 3;\n\t\t\t\treturn TRUE;\n\t\t\t}\n\t\t}\n\t}\n}\n\nint ReaderReceiveIClass(uint8_t* receivedAnswer)\n{\n int samples = 0;\n if (!GetIClassAnswer(receivedAnswer,160,&samples,0)) return FALSE;\n if (tracing) LogTrace(receivedAnswer,Demod.len,samples,Demod.parityBits,FALSE);\n if(samples == 0) return FALSE;\n return Demod.len;\n}\n\n// Reader iClass Anticollission\nvoid ReaderIClass(uint8_t arg0) {\n\tuint8_t act_all[] = { 0x0a };\n\tuint8_t identify[] = { 0x0c };\n\tuint8_t select[] = { 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };\n\n\tuint8_t* resp = (((uint8_t *)BigBuf) + 3560);\t// was 3560 - tied to other size changes\n\n\t// Reset trace buffer\n \tmemset(trace, 0x44, RECV_CMD_OFFSET);\n\ttraceLen = 0;\n\n\t// Setup SSC\n\tFpgaSetupSsc();\n\t// Start from off (no field generated)\n\t// Signal field is off with the appropriate LED\n\tLED_D_OFF();\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\n\tSpinDelay(200);\n\n\tSetAdcMuxFor(GPIO_MUXSEL_HIPKD);\n\n\t// Now give it time to spin up.\n\t// Signal field is on with the appropriate LED\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);\n\tSpinDelay(200);\n\n\tLED_A_ON();\n\n\tfor(;;) {\n\t\n\t\tif(traceLen > TRACE_SIZE) {\n\t\t\tDbpString(\"Trace full\");\n\t\t\tbreak;\n\t\t}\n\t\t\n\t\tif (BUTTON_PRESS()) break;\n\n\t\t// Send act_all\n\t\tReaderTransmitIClass(act_all, 1);\n\t\t// Card present?\n\t\tif(ReaderReceiveIClass(resp)) {\n\t\t\tReaderTransmitIClass(identify, 1);\n\t\t\tif(ReaderReceiveIClass(resp) == 10) {\n\t\t\t\t// Select card \n\t\t\t\tmemcpy(&select[1],resp,8);\n\t\t\t\tReaderTransmitIClass(select, sizeof(select));\n\n\t\t\t\tif(ReaderReceiveIClass(resp) == 10) {\n\t\t\t\t\tDbprintf(\" Selected CSN: %02x %02x %02x %02x %02x %02x %02x %02x\",\n\t\t\t\t\tresp[0], resp[1], resp[2],\n\t\t\t\t\tresp[3], resp[4], resp[5],\n\t\t\t\t\tresp[6], resp[7]);\n\t\t\t\t}\n\t\t\t\t// Card selected, whats next... ;-)\n\t\t\t}\n\t\t}\n\t\tWDT_HIT();\n\t}\n\t\n\tLED_A_OFF();\n}\n\n\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/iso14443.c", "content": "//-----------------------------------------------------------------------------\r\n// Jonathan Westhues, split Nov 2006\r\n//\r\n// This code is licensed to you under the terms of the GNU GPL, version 2 or,\r\n// at your option, any later version. See the LICENSE.txt file for the text of\r\n// the license.\r\n//-----------------------------------------------------------------------------\r\n// Routines to support ISO 14443. This includes both the reader software and\r\n// the `fake tag' modes. At the moment only the Type B modulation is\r\n// supported.\r\n//-----------------------------------------------------------------------------\r\n\r\n#include \"proxmark3.h\"\r\n#include \"apps.h\"\r\n#include \"util.h\"\r\n#include \"string.h\"\r\n\r\n#include \"iso14443crc.h\"\r\n\r\n//static void GetSamplesFor14443(int weTx, int n);\r\n\r\n#define DEMOD_TRACE_SIZE 4096\r\n#define READER_TAG_BUFFER_SIZE 2048\r\n#define TAG_READER_BUFFER_SIZE 2048\r\n#define DEMOD_DMA_BUFFER_SIZE 1024\r\n\r\n//=============================================================================\r\n// An ISO 14443 Type B tag. We listen for commands from the reader, using\r\n// a UART kind of thing that's implemented in software. When we get a\r\n// frame (i.e., a group of bytes between SOF and EOF), we check the CRC.\r\n// If it's good, then we can do something appropriate with it, and send\r\n// a response.\r\n//=============================================================================\r\n\r\n//-----------------------------------------------------------------------------\r\n// Code up a string of octets at layer 2 (including CRC, we don't generate\r\n// that here) so that they can be transmitted to the reader. Doesn't transmit\r\n// them yet, just leaves them ready to send in ToSend[].\r\n//-----------------------------------------------------------------------------\r\nstatic void CodeIso14443bAsTag(const uint8_t *cmd, int len)\r\n{\r\n int i;\r\n\r\n ToSendReset();\r\n\r\n // Transmit a burst of ones, as the initial thing that lets the\r\n // reader get phase sync. This (TR1) must be > 80/fs, per spec,\r\n // but tag that I've tried (a Paypass) exceeds that by a fair bit,\r\n // so I will too.\r\n for(i = 0; i < 20; i++) {\r\n ToSendStuffBit(1);\r\n ToSendStuffBit(1);\r\n ToSendStuffBit(1);\r\n ToSendStuffBit(1);\r\n }\r\n\r\n // Send SOF.\r\n for(i = 0; i < 10; i++) {\r\n ToSendStuffBit(0);\r\n ToSendStuffBit(0);\r\n ToSendStuffBit(0);\r\n ToSendStuffBit(0);\r\n }\r\n for(i = 0; i < 2; i++) {\r\n ToSendStuffBit(1);\r\n ToSendStuffBit(1);\r\n ToSendStuffBit(1);\r\n ToSendStuffBit(1);\r\n }\r\n\r\n for(i = 0; i < len; i++) {\r\n int j;\r\n uint8_t b = cmd[i];\r\n\r\n // Start bit\r\n ToSendStuffBit(0);\r\n ToSendStuffBit(0);\r\n ToSendStuffBit(0);\r\n ToSendStuffBit(0);\r\n\r\n // Data bits\r\n for(j = 0; j < 8; j++) {\r\n if(b & 1) {\r\n ToSendStuffBit(1);\r\n ToSendStuffBit(1);\r\n ToSendStuffBit(1);\r\n ToSendStuffBit(1);\r\n } else {\r\n ToSendStuffBit(0);\r\n ToSendStuffBit(0);\r\n ToSendStuffBit(0);\r\n ToSendStuffBit(0);\r\n }\r\n b >>= 1;\r\n }\r\n\r\n // Stop bit\r\n ToSendStuffBit(1);\r\n ToSendStuffBit(1);\r\n ToSendStuffBit(1);\r\n ToSendStuffBit(1);\r\n }\r\n\r\n // Send SOF.\r\n for(i = 0; i < 10; i++) {\r\n ToSendStuffBit(0);\r\n ToSendStuffBit(0);\r\n ToSendStuffBit(0);\r\n ToSendStuffBit(0);\r\n }\r\n for(i = 0; i < 10; i++) {\r\n ToSendStuffBit(1);\r\n ToSendStuffBit(1);\r\n ToSendStuffBit(1);\r\n ToSendStuffBit(1);\r\n }\r\n\r\n // Convert from last byte pos to length\r\n ToSendMax++;\r\n\r\n // Add a few more for slop\r\n ToSendMax += 2;\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// The software UART that receives commands from the reader, and its state\r\n// variables.\r\n//-----------------------------------------------------------------------------\r\nstatic struct {\r\n enum {\r\n STATE_UNSYNCD,\r\n STATE_GOT_FALLING_EDGE_OF_SOF,\r\n STATE_AWAITING_START_BIT,\r\n STATE_RECEIVING_DATA,\r\n STATE_ERROR_WAIT\r\n } state;\r\n uint16_t shiftReg;\r\n int bitCnt;\r\n int byteCnt;\r\n int byteCntMax;\r\n int posCnt;\r\n uint8_t *output;\r\n} Uart;\r\n\r\n/* Receive & handle a bit coming from the reader.\r\n *\r\n * LED handling:\r\n * LED A -> ON once we have received the SOF and are expecting the rest.\r\n * LED A -> OFF once we have received EOF or are in error state or unsynced\r\n *\r\n * Returns: true if we received a EOF\r\n * false if we are still waiting for some more\r\n */\r\nstatic int Handle14443UartBit(int bit)\r\n{\r\n switch(Uart.state) {\r\n case STATE_UNSYNCD:\r\n \tLED_A_OFF();\r\n if(!bit) {\r\n // we went low, so this could be the beginning\r\n // of an SOF\r\n Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF;\r\n Uart.posCnt = 0;\r\n Uart.bitCnt = 0;\r\n }\r\n break;\r\n\r\n case STATE_GOT_FALLING_EDGE_OF_SOF:\r\n Uart.posCnt++;\r\n if(Uart.posCnt == 2) {\r\n if(bit) {\r\n if(Uart.bitCnt >= 10) {\r\n // we've seen enough consecutive\r\n // zeros that it's a valid SOF\r\n Uart.posCnt = 0;\r\n Uart.byteCnt = 0;\r\n Uart.state = STATE_AWAITING_START_BIT;\r\n LED_A_ON(); // Indicate we got a valid SOF\r\n } else {\r\n // didn't stay down long enough\r\n // before going high, error\r\n Uart.state = STATE_ERROR_WAIT;\r\n }\r\n } else {\r\n // do nothing, keep waiting\r\n }\r\n Uart.bitCnt++;\r\n }\r\n if(Uart.posCnt >= 4) Uart.posCnt = 0;\r\n if(Uart.bitCnt > 14) {\r\n // Give up if we see too many zeros without\r\n // a one, too.\r\n Uart.state = STATE_ERROR_WAIT;\r\n }\r\n break;\r\n\r\n case STATE_AWAITING_START_BIT:\r\n Uart.posCnt++;\r\n if(bit) {\r\n if(Uart.posCnt > 25) {\r\n // stayed high for too long between\r\n // characters, error\r\n Uart.state = STATE_ERROR_WAIT;\r\n }\r\n } else {\r\n // falling edge, this starts the data byte\r\n Uart.posCnt = 0;\r\n Uart.bitCnt = 0;\r\n Uart.shiftReg = 0;\r\n Uart.state = STATE_RECEIVING_DATA;\r\n LED_A_ON(); // Indicate we're receiving\r\n }\r\n break;\r\n\r\n case STATE_RECEIVING_DATA:\r\n Uart.posCnt++;\r\n if(Uart.posCnt == 2) {\r\n // time to sample a bit\r\n Uart.shiftReg >>= 1;\r\n if(bit) {\r\n Uart.shiftReg |= 0x200;\r\n }\r\n Uart.bitCnt++;\r\n }\r\n if(Uart.posCnt >= 4) {\r\n Uart.posCnt = 0;\r\n }\r\n if(Uart.bitCnt == 10) {\r\n if((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001))\r\n {\r\n // this is a data byte, with correct\r\n // start and stop bits\r\n Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff;\r\n Uart.byteCnt++;\r\n\r\n if(Uart.byteCnt >= Uart.byteCntMax) {\r\n // Buffer overflowed, give up\r\n Uart.posCnt = 0;\r\n Uart.state = STATE_ERROR_WAIT;\r\n } else {\r\n // so get the next byte now\r\n Uart.posCnt = 0;\r\n Uart.state = STATE_AWAITING_START_BIT;\r\n }\r\n } else if(Uart.shiftReg == 0x000) {\r\n // this is an EOF byte\r\n \tLED_A_OFF(); // Finished receiving\r\n return TRUE;\r\n } else {\r\n // this is an error\r\n Uart.posCnt = 0;\r\n Uart.state = STATE_ERROR_WAIT;\r\n }\r\n }\r\n break;\r\n\r\n case STATE_ERROR_WAIT:\r\n // We're all screwed up, so wait a little while\r\n // for whatever went wrong to finish, and then\r\n // start over.\r\n Uart.posCnt++;\r\n if(Uart.posCnt > 10) {\r\n Uart.state = STATE_UNSYNCD;\r\n }\r\n break;\r\n\r\n default:\r\n Uart.state = STATE_UNSYNCD;\r\n break;\r\n }\r\n\r\n if (Uart.state == STATE_ERROR_WAIT) LED_A_OFF(); // Error\r\n\r\n return FALSE;\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// Receive a command (from the reader to us, where we are the simulated tag),\r\n// and store it in the given buffer, up to the given maximum length. Keeps\r\n// spinning, waiting for a well-framed command, until either we get one\r\n// (returns TRUE) or someone presses the pushbutton on the board (FALSE).\r\n//\r\n// Assume that we're called with the SSC (to the FPGA) and ADC path set\r\n// correctly.\r\n//-----------------------------------------------------------------------------\r\nstatic int GetIso14443CommandFromReader(uint8_t *received, int *len, int maxLen)\r\n{\r\n uint8_t mask;\r\n int i, bit;\r\n\r\n // Set FPGA mode to \"simulated ISO 14443 tag\", no modulation (listen\r\n // only, since we are receiving, not transmitting).\r\n // Signal field is off with the appropriate LED\r\n LED_D_OFF();\r\n FpgaWriteConfWord(\r\n \tFPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_NO_MODULATION);\r\n\r\n\r\n // Now run a `software UART' on the stream of incoming samples.\r\n Uart.output = received;\r\n Uart.byteCntMax = maxLen;\r\n Uart.state = STATE_UNSYNCD;\r\n\r\n for(;;) {\r\n WDT_HIT();\r\n\r\n if(BUTTON_PRESS()) return FALSE;\r\n\r\n if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r\n AT91C_BASE_SSC->SSC_THR = 0x00;\r\n }\r\n if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r\n uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;\r\n\r\n mask = 0x80;\r\n for(i = 0; i < 8; i++, mask >>= 1) {\r\n bit = (b & mask);\r\n if(Handle14443UartBit(bit)) {\r\n *len = Uart.byteCnt;\r\n return TRUE;\r\n }\r\n }\r\n }\r\n }\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// Main loop of simulated tag: receive commands from reader, decide what\r\n// response to send, and send it.\r\n//-----------------------------------------------------------------------------\r\nvoid SimulateIso14443Tag(void)\r\n{\r\n static const uint8_t cmd1[] = { 0x05, 0x00, 0x08, 0x39, 0x73 };\r\n static const uint8_t response1[] = {\r\n 0x50, 0x82, 0x0d, 0xe1, 0x74, 0x20, 0x38, 0x19, 0x22,\r\n 0x00, 0x21, 0x85, 0x5e, 0xd7\r\n };\r\n\r\n uint8_t *resp;\r\n int respLen;\r\n\r\n uint8_t *resp1 = (((uint8_t *)BigBuf) + 800);\r\n int resp1Len;\r\n\r\n uint8_t *receivedCmd = (uint8_t *)BigBuf;\r\n int len;\r\n\r\n int i;\r\n\r\n int cmdsRecvd = 0;\r\n\r\n memset(receivedCmd, 0x44, 400);\r\n\r\n CodeIso14443bAsTag(response1, sizeof(response1));\r\n memcpy(resp1, ToSend, ToSendMax); resp1Len = ToSendMax;\r\n\r\n // We need to listen to the high-frequency, peak-detected path.\r\n SetAdcMuxFor(GPIO_MUXSEL_HIPKD);\r\n FpgaSetupSsc();\r\n\r\n cmdsRecvd = 0;\r\n\r\n for(;;) {\r\n uint8_t b1, b2;\r\n\r\n if(!GetIso14443CommandFromReader(receivedCmd, &len, 100)) {\r\n\t\tDbprintf(\"button pressed, received %d commands\", cmdsRecvd);\r\n\t\tbreak;\r\n }\r\n\r\n // Good, look at the command now.\r\n\r\n if(len == sizeof(cmd1) && memcmp(receivedCmd, cmd1, len)==0) {\r\n resp = resp1; respLen = resp1Len;\r\n } else {\r\n Dbprintf(\"new cmd from reader: len=%d, cmdsRecvd=%d\", len, cmdsRecvd);\r\n // And print whether the CRC fails, just for good measure\r\n ComputeCrc14443(CRC_14443_B, receivedCmd, len-2, &b1, &b2);\r\n if(b1 != receivedCmd[len-2] || b2 != receivedCmd[len-1]) {\r\n // Not so good, try again.\r\n DbpString(\"+++CRC fail\");\r\n } else {\r\n DbpString(\"CRC passes\");\r\n }\r\n break;\r\n }\r\n\r\n memset(receivedCmd, 0x44, 32);\r\n\r\n cmdsRecvd++;\r\n\r\n if(cmdsRecvd > 0x30) {\r\n DbpString(\"many commands later...\");\r\n break;\r\n }\r\n\r\n if(respLen <= 0) continue;\r\n\r\n // Modulate BPSK\r\n // Signal field is off with the appropriate LED\r\n LED_D_OFF();\r\n FpgaWriteConfWord(\r\n \tFPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_BPSK);\r\n AT91C_BASE_SSC->SSC_THR = 0xff;\r\n FpgaSetupSsc();\r\n\r\n // Transmit the response.\r\n i = 0;\r\n for(;;) {\r\n if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r\n uint8_t b = resp[i];\r\n\r\n AT91C_BASE_SSC->SSC_THR = b;\r\n\r\n i++;\r\n if(i > respLen) {\r\n break;\r\n }\r\n }\r\n if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r\n volatile uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;\r\n (void)b;\r\n }\r\n }\r\n }\r\n}\r\n\r\n//=============================================================================\r\n// An ISO 14443 Type B reader. We take layer two commands, code them\r\n// appropriately, and then send them to the tag. We then listen for the\r\n// tag's response, which we leave in the buffer to be demodulated on the\r\n// PC side.\r\n//=============================================================================\r\n\r\nstatic struct {\r\n enum {\r\n DEMOD_UNSYNCD,\r\n DEMOD_PHASE_REF_TRAINING,\r\n DEMOD_AWAITING_FALLING_EDGE_OF_SOF,\r\n DEMOD_GOT_FALLING_EDGE_OF_SOF,\r\n DEMOD_AWAITING_START_BIT,\r\n DEMOD_RECEIVING_DATA,\r\n DEMOD_ERROR_WAIT\r\n } state;\r\n int bitCount;\r\n int posCount;\r\n int thisBit;\r\n int metric;\r\n int metricN;\r\n uint16_t shiftReg;\r\n uint8_t *output;\r\n int len;\r\n int sumI;\r\n int sumQ;\r\n} Demod;\r\n\r\n/*\r\n * Handles reception of a bit from the tag\r\n *\r\n * LED handling:\r\n * LED C -> ON once we have received the SOF and are expecting the rest.\r\n * LED C -> OFF once we have received EOF or are unsynced\r\n *\r\n * Returns: true if we received a EOF\r\n * false if we are still waiting for some more\r\n *\r\n */\r\nstatic RAMFUNC int Handle14443SamplesDemod(int ci, int cq)\r\n{\r\n int v;\r\n\r\n // The soft decision on the bit uses an estimate of just the\r\n // quadrant of the reference angle, not the exact angle.\r\n#define MAKE_SOFT_DECISION() { \\\r\n if(Demod.sumI > 0) { \\\r\n v = ci; \\\r\n } else { \\\r\n v = -ci; \\\r\n } \\\r\n if(Demod.sumQ > 0) { \\\r\n v += cq; \\\r\n } else { \\\r\n v -= cq; \\\r\n } \\\r\n }\r\n\r\n switch(Demod.state) {\r\n case DEMOD_UNSYNCD:\r\n v = ci;\r\n if(v < 0) v = -v;\r\n if(cq > 0) {\r\n v += cq;\r\n } else {\r\n v -= cq;\r\n }\r\n if(v > 40) {\r\n Demod.posCount = 0;\r\n Demod.state = DEMOD_PHASE_REF_TRAINING;\r\n Demod.sumI = 0;\r\n Demod.sumQ = 0;\r\n }\r\n break;\r\n\r\n case DEMOD_PHASE_REF_TRAINING:\r\n if(Demod.posCount < 8) {\r\n Demod.sumI += ci;\r\n Demod.sumQ += cq;\r\n } else if(Demod.posCount > 100) {\r\n // error, waited too long\r\n Demod.state = DEMOD_UNSYNCD;\r\n } else {\r\n MAKE_SOFT_DECISION();\r\n if(v < 0) {\r\n Demod.state = DEMOD_AWAITING_FALLING_EDGE_OF_SOF;\r\n Demod.posCount = 0;\r\n }\r\n }\r\n Demod.posCount++;\r\n break;\r\n\r\n case DEMOD_AWAITING_FALLING_EDGE_OF_SOF:\r\n MAKE_SOFT_DECISION();\r\n if(v < 0) {\r\n Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF;\r\n Demod.posCount = 0;\r\n } else {\r\n if(Demod.posCount > 100) {\r\n Demod.state = DEMOD_UNSYNCD;\r\n }\r\n }\r\n Demod.posCount++;\r\n break;\r\n\r\n case DEMOD_GOT_FALLING_EDGE_OF_SOF:\r\n MAKE_SOFT_DECISION();\r\n if(v > 0) {\r\n if(Demod.posCount < 12) {\r\n Demod.state = DEMOD_UNSYNCD;\r\n } else {\r\n \tLED_C_ON(); // Got SOF\r\n Demod.state = DEMOD_AWAITING_START_BIT;\r\n Demod.posCount = 0;\r\n Demod.len = 0;\r\n Demod.metricN = 0;\r\n Demod.metric = 0;\r\n }\r\n } else {\r\n if(Demod.posCount > 100) {\r\n Demod.state = DEMOD_UNSYNCD;\r\n }\r\n }\r\n Demod.posCount++;\r\n break;\r\n\r\n case DEMOD_AWAITING_START_BIT:\r\n MAKE_SOFT_DECISION();\r\n if(v > 0) {\r\n if(Demod.posCount > 10) {\r\n Demod.state = DEMOD_UNSYNCD;\r\n }\r\n } else {\r\n Demod.bitCount = 0;\r\n Demod.posCount = 1;\r\n Demod.thisBit = v;\r\n Demod.shiftReg = 0;\r\n Demod.state = DEMOD_RECEIVING_DATA;\r\n }\r\n break;\r\n\r\n case DEMOD_RECEIVING_DATA:\r\n MAKE_SOFT_DECISION();\r\n if(Demod.posCount == 0) {\r\n Demod.thisBit = v;\r\n Demod.posCount = 1;\r\n } else {\r\n Demod.thisBit += v;\r\n\r\n if(Demod.thisBit > 0) {\r\n Demod.metric += Demod.thisBit;\r\n } else {\r\n Demod.metric -= Demod.thisBit;\r\n }\r\n (Demod.metricN)++;\r\n\r\n Demod.shiftReg >>= 1;\r\n if(Demod.thisBit > 0) {\r\n Demod.shiftReg |= 0x200;\r\n }\r\n\r\n Demod.bitCount++;\r\n if(Demod.bitCount == 10) {\r\n uint16_t s = Demod.shiftReg;\r\n if((s & 0x200) && !(s & 0x001)) {\r\n uint8_t b = (s >> 1);\r\n Demod.output[Demod.len] = b;\r\n Demod.len++;\r\n Demod.state = DEMOD_AWAITING_START_BIT;\r\n } else if(s == 0x000) {\r\n // This is EOF\r\n \tLED_C_OFF();\r\n return TRUE;\r\n Demod.state = DEMOD_UNSYNCD;\r\n } else {\r\n Demod.state = DEMOD_UNSYNCD;\r\n }\r\n }\r\n Demod.posCount = 0;\r\n }\r\n break;\r\n\r\n default:\r\n Demod.state = DEMOD_UNSYNCD;\r\n break;\r\n }\r\n\r\n if (Demod.state == DEMOD_UNSYNCD) LED_C_OFF(); // Not synchronized...\r\n return FALSE;\r\n}\r\n\r\n/*\r\n * Demodulate the samples we received from the tag\r\n * weTx: set to 'TRUE' if we behave like a reader\r\n * set to 'FALSE' if we behave like a snooper\r\n * quiet: set to 'TRUE' to disable debug output\r\n */\r\nstatic void GetSamplesFor14443Demod(int weTx, int n, int quiet)\r\n{\r\n int max = 0;\r\n int gotFrame = FALSE;\r\n\r\n//# define DMA_BUFFER_SIZE 8\r\n int8_t *dmaBuf;\r\n\r\n int lastRxCounter;\r\n int8_t *upTo;\r\n\r\n int ci, cq;\r\n\r\n int samples = 0;\r\n\r\n // Clear out the state of the \"UART\" that receives from the tag.\r\n memset(BigBuf, 0x44, 400);\r\n Demod.output = (uint8_t *)BigBuf;\r\n Demod.len = 0;\r\n Demod.state = DEMOD_UNSYNCD;\r\n\r\n // And the UART that receives from the reader\r\n Uart.output = (((uint8_t *)BigBuf) + 1024);\r\n Uart.byteCntMax = 100;\r\n Uart.state = STATE_UNSYNCD;\r\n\r\n // Setup for the DMA.\r\n dmaBuf = (int8_t *)(BigBuf + 32);\r\n upTo = dmaBuf;\r\n lastRxCounter = DEMOD_DMA_BUFFER_SIZE;\r\n FpgaSetupSscDma((uint8_t *)dmaBuf, DEMOD_DMA_BUFFER_SIZE);\r\n\r\n // Signal field is ON with the appropriate LED:\r\n\tif (weTx) LED_D_ON(); else LED_D_OFF();\r\n // And put the FPGA in the appropriate mode\r\n FpgaWriteConfWord(\r\n \tFPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ |\r\n \t(weTx ? 0 : FPGA_HF_READER_RX_XCORR_SNOOP));\r\n\r\n for(;;) {\r\n int behindBy = lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR;\r\n if(behindBy > max) max = behindBy;\r\n\r\n while(((lastRxCounter-AT91C_BASE_PDC_SSC->PDC_RCR) & (DEMOD_DMA_BUFFER_SIZE-1))\r\n > 2)\r\n {\r\n ci = upTo[0];\r\n cq = upTo[1];\r\n upTo += 2;\r\n if(upTo - dmaBuf > DEMOD_DMA_BUFFER_SIZE) {\r\n upTo -= DEMOD_DMA_BUFFER_SIZE;\r\n AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;\r\n AT91C_BASE_PDC_SSC->PDC_RNCR = DEMOD_DMA_BUFFER_SIZE;\r\n }\r\n lastRxCounter -= 2;\r\n if(lastRxCounter <= 0) {\r\n lastRxCounter += DEMOD_DMA_BUFFER_SIZE;\r\n }\r\n\r\n samples += 2;\r\n\r\n Handle14443UartBit(1);\r\n Handle14443UartBit(1);\r\n\r\n if(Handle14443SamplesDemod(ci, cq)) {\r\n gotFrame = 1;\r\n }\r\n }\r\n\r\n if(samples > 2000) {\r\n break;\r\n }\r\n }\r\n AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;\r\n if (!quiet) Dbprintf(\"%x %x %x\", max, gotFrame, Demod.len);\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// Read the tag's response. We just receive a stream of slightly-processed\r\n// samples from the FPGA, which we will later do some signal processing on,\r\n// to get the bits.\r\n//-----------------------------------------------------------------------------\r\n/*static void GetSamplesFor14443(int weTx, int n)\r\n{\r\n uint8_t *dest = (uint8_t *)BigBuf;\r\n int c;\r\n\r\n FpgaWriteConfWord(\r\n \tFPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ |\r\n \t(weTx ? 0 : FPGA_HF_READER_RX_XCORR_SNOOP));\r\n\r\n c = 0;\r\n for(;;) {\r\n if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r\n AT91C_BASE_SSC->SSC_THR = 0x43;\r\n }\r\n if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r\n int8_t b;\r\n b = (int8_t)AT91C_BASE_SSC->SSC_RHR;\r\n\r\n dest[c++] = (uint8_t)b;\r\n\r\n if(c >= n) {\r\n break;\r\n }\r\n }\r\n }\r\n}*/\r\n\r\n//-----------------------------------------------------------------------------\r\n// Transmit the command (to the tag) that was placed in ToSend[].\r\n//-----------------------------------------------------------------------------\r\nstatic void TransmitFor14443(void)\r\n{\r\n int c;\r\n\r\n FpgaSetupSsc();\r\n\r\n while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r\n AT91C_BASE_SSC->SSC_THR = 0xff;\r\n }\r\n\r\n // Signal field is ON with the appropriate Red LED\r\n\tLED_D_ON();\r\n\t// Signal we are transmitting with the Green LED\r\n\tLED_B_ON();\r\n\tFpgaWriteConfWord(\r\n \tFPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);\r\n\r\n for(c = 0; c < 10;) {\r\n if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r\n AT91C_BASE_SSC->SSC_THR = 0xff;\r\n c++;\r\n }\r\n if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r\n volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;\r\n (void)r;\r\n }\r\n WDT_HIT();\r\n }\r\n\r\n c = 0;\r\n for(;;) {\r\n if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r\n AT91C_BASE_SSC->SSC_THR = ToSend[c];\r\n c++;\r\n if(c >= ToSendMax) {\r\n break;\r\n }\r\n }\r\n if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r\n volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;\r\n (void)r;\r\n }\r\n WDT_HIT();\r\n }\r\n LED_B_OFF(); // Finished sending\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// Code a layer 2 command (string of octets, including CRC) into ToSend[],\r\n// so that it is ready to transmit to the tag using TransmitFor14443().\r\n//-----------------------------------------------------------------------------\r\nvoid CodeIso14443bAsReader(const uint8_t *cmd, int len)\r\n{\r\n int i, j;\r\n uint8_t b;\r\n\r\n ToSendReset();\r\n\r\n // Establish initial reference level\r\n for(i = 0; i < 40; i++) {\r\n ToSendStuffBit(1);\r\n }\r\n // Send SOF\r\n for(i = 0; i < 10; i++) {\r\n ToSendStuffBit(0);\r\n }\r\n\r\n for(i = 0; i < len; i++) {\r\n // Stop bits/EGT\r\n ToSendStuffBit(1);\r\n ToSendStuffBit(1);\r\n // Start bit\r\n ToSendStuffBit(0);\r\n // Data bits\r\n b = cmd[i];\r\n for(j = 0; j < 8; j++) {\r\n if(b & 1) {\r\n ToSendStuffBit(1);\r\n } else {\r\n ToSendStuffBit(0);\r\n }\r\n b >>= 1;\r\n }\r\n }\r\n // Send EOF\r\n ToSendStuffBit(1);\r\n for(i = 0; i < 10; i++) {\r\n ToSendStuffBit(0);\r\n }\r\n for(i = 0; i < 8; i++) {\r\n ToSendStuffBit(1);\r\n }\r\n\r\n // And then a little more, to make sure that the last character makes\r\n // it out before we switch to rx mode.\r\n for(i = 0; i < 24; i++) {\r\n ToSendStuffBit(1);\r\n }\r\n\r\n // Convert from last character reference to length\r\n ToSendMax++;\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// Read an ISO 14443 tag. We send it some set of commands, and record the\r\n// responses.\r\n// The command name is misleading, it actually decodes the reponse in HEX\r\n// into the output buffer (read the result using hexsamples, not hisamples)\r\n//-----------------------------------------------------------------------------\r\nvoid AcquireRawAdcSamplesIso14443(uint32_t parameter)\r\n{\r\n uint8_t cmd1[] = { 0x05, 0x00, 0x08, 0x39, 0x73 };\r\n\r\n // Make sure that we start from off, since the tags are stateful;\r\n // confusing things will happen if we don't reset them between reads.\r\n FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n LED_D_OFF();\r\n SpinDelay(200);\r\n\r\n SetAdcMuxFor(GPIO_MUXSEL_HIPKD);\r\n FpgaSetupSsc();\r\n\r\n // Now give it time to spin up.\r\n // Signal field is on with the appropriate LED\r\n LED_D_ON();\r\n FpgaWriteConfWord(\r\n \tFPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ);\r\n SpinDelay(200);\r\n\r\n CodeIso14443bAsReader(cmd1, sizeof(cmd1));\r\n TransmitFor14443();\r\n// LED_A_ON();\r\n GetSamplesFor14443Demod(TRUE, 2000, FALSE);\r\n// LED_A_OFF();\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// Read a SRI512 ISO 14443 tag.\r\n//\r\n// SRI512 tags are just simple memory tags, here we're looking at making a dump\r\n// of the contents of the memory. No anticollision algorithm is done, we assume\r\n// we have a single tag in the field.\r\n//\r\n// I tried to be systematic and check every answer of the tag, every CRC, etc...\r\n//-----------------------------------------------------------------------------\r\nvoid ReadSRI512Iso14443(uint32_t parameter)\r\n{\r\n ReadSTMemoryIso14443(parameter,0x0F);\r\n}\r\nvoid ReadSRIX4KIso14443(uint32_t parameter)\r\n{\r\n ReadSTMemoryIso14443(parameter,0x7F);\r\n}\r\n\r\nvoid ReadSTMemoryIso14443(uint32_t parameter,uint32_t dwLast)\r\n{\r\n uint8_t i = 0x00;\r\n\r\n // Make sure that we start from off, since the tags are stateful;\r\n // confusing things will happen if we don't reset them between reads.\r\n LED_D_OFF();\r\n FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n SpinDelay(200);\r\n\r\n SetAdcMuxFor(GPIO_MUXSEL_HIPKD);\r\n FpgaSetupSsc();\r\n\r\n // Now give it time to spin up.\r\n // Signal field is on with the appropriate LED\r\n LED_D_ON();\r\n FpgaWriteConfWord(\r\n \tFPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ);\r\n SpinDelay(200);\r\n\r\n // First command: wake up the tag using the INITIATE command\r\n uint8_t cmd1[] = { 0x06, 0x00, 0x97, 0x5b};\r\n CodeIso14443bAsReader(cmd1, sizeof(cmd1));\r\n TransmitFor14443();\r\n// LED_A_ON();\r\n GetSamplesFor14443Demod(TRUE, 2000,TRUE);\r\n// LED_A_OFF();\r\n\r\n if (Demod.len == 0) {\r\n\tDbpString(\"No response from tag\");\r\n\treturn;\r\n } else {\r\n\tDbprintf(\"Randomly generated UID from tag (+ 2 byte CRC): %x %x %x\",\r\n\t\tDemod.output[0], Demod.output[1],Demod.output[2]);\r\n }\r\n // There is a response, SELECT the uid\r\n DbpString(\"Now SELECT tag:\");\r\n cmd1[0] = 0x0E; // 0x0E is SELECT\r\n cmd1[1] = Demod.output[0];\r\n ComputeCrc14443(CRC_14443_B, cmd1, 2, &cmd1[2], &cmd1[3]);\r\n CodeIso14443bAsReader(cmd1, sizeof(cmd1));\r\n TransmitFor14443();\r\n// LED_A_ON();\r\n GetSamplesFor14443Demod(TRUE, 2000,TRUE);\r\n// LED_A_OFF();\r\n if (Demod.len != 3) {\r\n\tDbprintf(\"Expected 3 bytes from tag, got %d\", Demod.len);\r\n\treturn;\r\n }\r\n // Check the CRC of the answer:\r\n ComputeCrc14443(CRC_14443_B, Demod.output, 1 , &cmd1[2], &cmd1[3]);\r\n if(cmd1[2] != Demod.output[1] || cmd1[3] != Demod.output[2]) {\r\n\tDbpString(\"CRC Error reading select response.\");\r\n\treturn;\r\n }\r\n // Check response from the tag: should be the same UID as the command we just sent:\r\n if (cmd1[1] != Demod.output[0]) {\r\n\tDbprintf(\"Bad response to SELECT from Tag, aborting: %x %x\", cmd1[1], Demod.output[0]);\r\n\treturn;\r\n }\r\n // Tag is now selected,\r\n // First get the tag's UID:\r\n cmd1[0] = 0x0B;\r\n ComputeCrc14443(CRC_14443_B, cmd1, 1 , &cmd1[1], &cmd1[2]);\r\n CodeIso14443bAsReader(cmd1, 3); // Only first three bytes for this one\r\n TransmitFor14443();\r\n// LED_A_ON();\r\n GetSamplesFor14443Demod(TRUE, 2000,TRUE);\r\n// LED_A_OFF();\r\n if (Demod.len != 10) {\r\n\tDbprintf(\"Expected 10 bytes from tag, got %d\", Demod.len);\r\n\treturn;\r\n }\r\n // The check the CRC of the answer (use cmd1 as temporary variable):\r\n ComputeCrc14443(CRC_14443_B, Demod.output, 8, &cmd1[2], &cmd1[3]);\r\n if(cmd1[2] != Demod.output[8] || cmd1[3] != Demod.output[9]) {\r\n\tDbprintf(\"CRC Error reading block! - Below: expected, got %x %x\",\r\n\t\t(cmd1[2]<<8)+cmd1[3], (Demod.output[8]<<8)+Demod.output[9]);\r\n\t// Do not return;, let's go on... (we should retry, maybe ?)\r\n }\r\n Dbprintf(\"Tag UID (64 bits): %08x %08x\",\r\n\t(Demod.output[7]<<24) + (Demod.output[6]<<16) + (Demod.output[5]<<8) + Demod.output[4],\r\n\t(Demod.output[3]<<24) + (Demod.output[2]<<16) + (Demod.output[1]<<8) + Demod.output[0]);\r\n\r\n // Now loop to read all 16 blocks, address from 0 to 15\r\n DbpString(\"Tag memory dump, block 0 to 15\");\r\n cmd1[0] = 0x08;\r\n i = 0x00;\r\n dwLast++;\r\n for (;;) {\r\n if (i == dwLast) {\r\n\t\t DbpString(\"System area block (0xff):\");\r\n\t\t i = 0xff;\r\n\t }\r\n\t cmd1[1] = i;\r\n\t ComputeCrc14443(CRC_14443_B, cmd1, 2, &cmd1[2], &cmd1[3]);\r\n\t CodeIso14443bAsReader(cmd1, sizeof(cmd1));\r\n\t TransmitFor14443();\r\n//\t LED_A_ON();\r\n\t GetSamplesFor14443Demod(TRUE, 2000,TRUE);\r\n//\t LED_A_OFF();\r\n\t if (Demod.len != 6) { // Check if we got an answer from the tag\r\n\t\tDbpString(\"Expected 6 bytes from tag, got less...\");\r\n\t\treturn;\r\n\t }\r\n\t // The check the CRC of the answer (use cmd1 as temporary variable):\r\n\t ComputeCrc14443(CRC_14443_B, Demod.output, 4, &cmd1[2], &cmd1[3]);\r\n if(cmd1[2] != Demod.output[4] || cmd1[3] != Demod.output[5]) {\r\n\t\tDbprintf(\"CRC Error reading block! - Below: expected, got %x %x\",\r\n\t\t\t(cmd1[2]<<8)+cmd1[3], (Demod.output[4]<<8)+Demod.output[5]);\r\n\t\t// Do not return;, let's go on... (we should retry, maybe ?)\r\n\t }\r\n\t // Now print out the memory location:\r\n\t Dbprintf(\"Address=%x, Contents=%x, CRC=%x\", i,\r\n\t\t(Demod.output[3]<<24) + (Demod.output[2]<<16) + (Demod.output[1]<<8) + Demod.output[0],\r\n\t\t(Demod.output[4]<<8)+Demod.output[5]);\r\n\t if (i == 0xff) {\r\n\t\tbreak;\r\n\t }\r\n\t i++;\r\n }\r\n}\r\n\r\n\r\n//=============================================================================\r\n// Finally, the `sniffer' combines elements from both the reader and\r\n// simulated tag, to show both sides of the conversation.\r\n//=============================================================================\r\n\r\n//-----------------------------------------------------------------------------\r\n// Record the sequence of commands sent by the reader to the tag, with\r\n// triggering so that we start recording at the point that the tag is moved\r\n// near the reader.\r\n//-----------------------------------------------------------------------------\r\n/*\r\n * Memory usage for this function, (within BigBuf)\r\n * 0-4095 : Demodulated samples receive (4096 bytes) - DEMOD_TRACE_SIZE\r\n * 4096-6143 : Last Received command, 2048 bytes (reader->tag) - READER_TAG_BUFFER_SIZE\r\n * 6144-8191 : Last Received command, 2048 bytes(tag->reader) - TAG_READER_BUFFER_SIZE\r\n * 8192-9215 : DMA Buffer, 1024 bytes (samples) - DEMOD_DMA_BUFFER_SIZE\r\n */\r\nvoid RAMFUNC SnoopIso14443(void)\r\n{\r\n // We won't start recording the frames that we acquire until we trigger;\r\n // a good trigger condition to get started is probably when we see a\r\n // response from the tag.\r\n int triggered = TRUE;\r\n\r\n // The command (reader -> tag) that we're working on receiving.\r\n uint8_t *receivedCmd = (uint8_t *)(BigBuf) + DEMOD_TRACE_SIZE;\r\n // The response (tag -> reader) that we're working on receiving.\r\n uint8_t *receivedResponse = (uint8_t *)(BigBuf) + DEMOD_TRACE_SIZE + READER_TAG_BUFFER_SIZE;\r\n\r\n // As we receive stuff, we copy it from receivedCmd or receivedResponse\r\n // into trace, along with its length and other annotations.\r\n uint8_t *trace = (uint8_t *)BigBuf;\r\n int traceLen = 0;\r\n\r\n // The DMA buffer, used to stream samples from the FPGA.\r\n int8_t *dmaBuf = (int8_t *)(BigBuf) + DEMOD_TRACE_SIZE + READER_TAG_BUFFER_SIZE + TAG_READER_BUFFER_SIZE;\r\n int lastRxCounter;\r\n int8_t *upTo;\r\n int ci, cq;\r\n int maxBehindBy = 0;\r\n\r\n // Count of samples received so far, so that we can include timing\r\n // information in the trace buffer.\r\n int samples = 0;\r\n\r\n // Initialize the trace buffer\r\n memset(trace, 0x44, DEMOD_TRACE_SIZE);\r\n\r\n // Set up the demodulator for tag -> reader responses.\r\n Demod.output = receivedResponse;\r\n Demod.len = 0;\r\n Demod.state = DEMOD_UNSYNCD;\r\n\r\n // And the reader -> tag commands\r\n memset(&Uart, 0, sizeof(Uart));\r\n Uart.output = receivedCmd;\r\n Uart.byteCntMax = 100;\r\n Uart.state = STATE_UNSYNCD;\r\n\r\n\t// Print some debug information about the buffer sizes\r\n\tDbprintf(\"Snooping buffers initialized:\");\r\n\tDbprintf(\" Trace: %i bytes\", DEMOD_TRACE_SIZE);\r\n\tDbprintf(\" Reader -> tag: %i bytes\", READER_TAG_BUFFER_SIZE);\r\n\tDbprintf(\" tag -> Reader: %i bytes\", TAG_READER_BUFFER_SIZE);\r\n\tDbprintf(\" DMA: %i bytes\", DEMOD_DMA_BUFFER_SIZE);\r\n\r\n\r\n // And put the FPGA in the appropriate mode\r\n // Signal field is off with the appropriate LED\r\n LED_D_OFF();\r\n FpgaWriteConfWord(\r\n \tFPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ |\r\n \tFPGA_HF_READER_RX_XCORR_SNOOP);\r\n SetAdcMuxFor(GPIO_MUXSEL_HIPKD);\r\n\r\n // Setup for the DMA.\r\n FpgaSetupSsc();\r\n upTo = dmaBuf;\r\n lastRxCounter = DEMOD_DMA_BUFFER_SIZE;\r\n FpgaSetupSscDma((uint8_t *)dmaBuf, DEMOD_DMA_BUFFER_SIZE);\r\n\t\t\r\n LED_A_ON();\r\n\t\t\r\n // And now we loop, receiving samples.\r\n for(;;) {\r\n \tint behindBy = (lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) &\r\n (DEMOD_DMA_BUFFER_SIZE-1);\r\n if(behindBy > maxBehindBy) {\r\n maxBehindBy = behindBy;\r\n if(behindBy > (DEMOD_DMA_BUFFER_SIZE-2)) { // TODO: understand whether we can increase/decrease as we want or not?\r\n Dbprintf(\"blew circular buffer! behindBy=0x%x\", behindBy);\r\n goto done;\r\n }\r\n }\r\n if(behindBy < 2) continue;\r\n\r\n ci = upTo[0];\r\n cq = upTo[1];\r\n upTo += 2;\r\n lastRxCounter -= 2;\r\n if(upTo - dmaBuf > DEMOD_DMA_BUFFER_SIZE) {\r\n upTo -= DEMOD_DMA_BUFFER_SIZE;\r\n lastRxCounter += DEMOD_DMA_BUFFER_SIZE;\r\n AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;\r\n AT91C_BASE_PDC_SSC->PDC_RNCR = DEMOD_DMA_BUFFER_SIZE;\r\n }\r\n\r\n samples += 2;\r\n\r\n#define HANDLE_BIT_IF_BODY \\\r\n if(triggered) { \\\r\n trace[traceLen++] = ((samples >> 0) & 0xff); \\\r\n trace[traceLen++] = ((samples >> 8) & 0xff); \\\r\n trace[traceLen++] = ((samples >> 16) & 0xff); \\\r\n trace[traceLen++] = ((samples >> 24) & 0xff); \\\r\n trace[traceLen++] = 0; \\\r\n trace[traceLen++] = 0; \\\r\n trace[traceLen++] = 0; \\\r\n trace[traceLen++] = 0; \\\r\n trace[traceLen++] = Uart.byteCnt; \\\r\n memcpy(trace+traceLen, receivedCmd, Uart.byteCnt); \\\r\n traceLen += Uart.byteCnt; \\\r\n if(traceLen > 1000) break; \\\r\n } \\\r\n /* And ready to receive another command. */ \\\r\n memset(&Uart, 0, sizeof(Uart)); \\\r\n Uart.output = receivedCmd; \\\r\n Uart.byteCntMax = 100; \\\r\n Uart.state = STATE_UNSYNCD; \\\r\n /* And also reset the demod code, which might have been */ \\\r\n /* false-triggered by the commands from the reader. */ \\\r\n memset(&Demod, 0, sizeof(Demod)); \\\r\n Demod.output = receivedResponse; \\\r\n Demod.state = DEMOD_UNSYNCD; \\\r\n\r\n if(Handle14443UartBit(ci & 1)) {\r\n HANDLE_BIT_IF_BODY\r\n }\r\n if(Handle14443UartBit(cq & 1)) {\r\n HANDLE_BIT_IF_BODY\r\n }\r\n\r\n if(Handle14443SamplesDemod(ci, cq)) {\r\n // timestamp, as a count of samples\r\n trace[traceLen++] = ((samples >> 0) & 0xff);\r\n trace[traceLen++] = ((samples >> 8) & 0xff);\r\n trace[traceLen++] = ((samples >> 16) & 0xff);\r\n trace[traceLen++] = 0x80 | ((samples >> 24) & 0xff);\r\n // correlation metric (~signal strength estimate)\r\n if(Demod.metricN != 0) {\r\n Demod.metric /= Demod.metricN;\r\n }\r\n trace[traceLen++] = ((Demod.metric >> 0) & 0xff);\r\n trace[traceLen++] = ((Demod.metric >> 8) & 0xff);\r\n trace[traceLen++] = ((Demod.metric >> 16) & 0xff);\r\n trace[traceLen++] = ((Demod.metric >> 24) & 0xff);\r\n // length\r\n trace[traceLen++] = Demod.len;\r\n memcpy(trace+traceLen, receivedResponse, Demod.len);\r\n traceLen += Demod.len;\r\n if(traceLen > DEMOD_TRACE_SIZE) {\r\n\t\t\t\tDbpString(\"Reached trace limit\");\r\n\t\t\t\tgoto done;\r\n\t\t\t}\r\n\r\n triggered = TRUE;\r\n LED_A_OFF();\r\n LED_B_ON();\r\n\r\n // And ready to receive another response.\r\n memset(&Demod, 0, sizeof(Demod));\r\n Demod.output = receivedResponse;\r\n Demod.state = DEMOD_UNSYNCD;\r\n }\r\n\t\tWDT_HIT();\r\n\r\n if(BUTTON_PRESS()) {\r\n DbpString(\"cancelled\");\r\n goto done;\r\n }\r\n }\r\n\r\ndone:\r\n\tLED_A_OFF();\r\n\tLED_B_OFF();\r\n\tLED_C_OFF();\r\n AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;\r\n\tDbpString(\"Snoop statistics:\");\r\n Dbprintf(\" Max behind by: %i\", maxBehindBy);\r\n\tDbprintf(\" Uart State: %x\", Uart.state);\r\n\tDbprintf(\" Uart ByteCnt: %i\", Uart.byteCnt);\r\n\tDbprintf(\" Uart ByteCntMax: %i\", Uart.byteCntMax);\r\n\tDbprintf(\" Trace length: %i\", traceLen);\r\n}\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/iso14443a.c", "content": "//-----------------------------------------------------------------------------\r\n// Merlok - June 2011, 2012\r\n// Gerhard de Koning Gans - May 2008\r\n// Hagen Fritsch - June 2010\r\n//\r\n// This code is licensed to you under the terms of the GNU GPL, version 2 or,\r\n// at your option, any later version. See the LICENSE.txt file for the text of\r\n// the license.\r\n//-----------------------------------------------------------------------------\r\n// Routines to support ISO 14443 type A.\r\n//-----------------------------------------------------------------------------\r\n\r\n#include \"proxmark3.h\"\r\n#include \"apps.h\"\r\n#include \"util.h\"\r\n#include \"string.h\"\r\n#include \"cmd.h\"\r\n\r\n#include \"iso14443crc.h\"\r\n#include \"iso14443a.h\"\r\n#include \"crapto1.h\"\r\n#include \"mifareutil.h\"\r\n\r\nstatic uint32_t iso14a_timeout;\r\nuint8_t *trace = (uint8_t *) BigBuf+TRACE_OFFSET;\r\nint traceLen = 0;\r\nint rsamples = 0;\r\nint tracing = TRUE;\r\nuint8_t trigger = 0;\r\n// the block number for the ISO14443-4 PCB\r\nstatic uint8_t iso14_pcb_blocknum = 0;\r\n\r\n// CARD TO READER - manchester\r\n// Sequence D: 11110000 modulation with subcarrier during first half\r\n// Sequence E: 00001111 modulation with subcarrier during second half\r\n// Sequence F: 00000000 no modulation with subcarrier\r\n// READER TO CARD - miller\r\n// Sequence X: 00001100 drop after half a period\r\n// Sequence Y: 00000000 no drop\r\n// Sequence Z: 11000000 drop at start\r\n#define\tSEC_D 0xf0\r\n#define\tSEC_E 0x0f\r\n#define\tSEC_F 0x00\r\n#define\tSEC_X 0x0c\r\n#define\tSEC_Y 0x00\r\n#define\tSEC_Z 0xc0\r\n\r\nconst uint8_t OddByteParity[256] = {\r\n 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,\r\n 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,\r\n 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,\r\n 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,\r\n 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,\r\n 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,\r\n 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,\r\n 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,\r\n 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,\r\n 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,\r\n 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,\r\n 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,\r\n 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,\r\n 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,\r\n 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,\r\n 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1\r\n};\r\n\r\n\r\nvoid iso14a_set_trigger(bool enable) {\r\n\ttrigger = enable;\r\n}\r\n\r\nvoid iso14a_clear_trace() {\r\n memset(trace, 0x44, TRACE_SIZE);\r\n\ttraceLen = 0;\r\n}\r\n\r\nvoid iso14a_set_tracing(bool enable) {\r\n\ttracing = enable;\r\n}\r\n\r\nvoid iso14a_set_timeout(uint32_t timeout) {\r\n\tiso14a_timeout = timeout;\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// Generate the parity value for a byte sequence\r\n//\r\n//-----------------------------------------------------------------------------\r\nbyte_t oddparity (const byte_t bt)\r\n{\r\n return OddByteParity[bt];\r\n}\r\n\r\nuint32_t GetParity(const uint8_t * pbtCmd, int iLen)\r\n{\r\n int i;\r\n uint32_t dwPar = 0;\r\n\r\n // Generate the encrypted data\r\n for (i = 0; i < iLen; i++) {\r\n // Save the encrypted parity bit\r\n dwPar |= ((OddByteParity[pbtCmd[i]]) << i);\r\n }\r\n return dwPar;\r\n}\r\n\r\nvoid AppendCrc14443a(uint8_t* data, int len)\r\n{\r\n ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1);\r\n}\r\n\r\n// The function LogTrace() is also used by the iClass implementation in iClass.c\r\nint RAMFUNC LogTrace(const uint8_t * btBytes, int iLen, int iSamples, uint32_t dwParity, int bReader)\r\n{\r\n // Return when trace is full\r\n if (traceLen >= TRACE_SIZE) return FALSE;\r\n\r\n // Trace the random, i'm curious\r\n rsamples += iSamples;\r\n trace[traceLen++] = ((rsamples >> 0) & 0xff);\r\n trace[traceLen++] = ((rsamples >> 8) & 0xff);\r\n trace[traceLen++] = ((rsamples >> 16) & 0xff);\r\n trace[traceLen++] = ((rsamples >> 24) & 0xff);\r\n if (!bReader) {\r\n trace[traceLen - 1] |= 0x80;\r\n }\r\n trace[traceLen++] = ((dwParity >> 0) & 0xff);\r\n trace[traceLen++] = ((dwParity >> 8) & 0xff);\r\n trace[traceLen++] = ((dwParity >> 16) & 0xff);\r\n trace[traceLen++] = ((dwParity >> 24) & 0xff);\r\n trace[traceLen++] = iLen;\r\n memcpy(trace + traceLen, btBytes, iLen);\r\n traceLen += iLen;\r\n return TRUE;\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// The software UART that receives commands from the reader, and its state\r\n// variables.\r\n//-----------------------------------------------------------------------------\r\nstatic tUart Uart;\r\n\r\nstatic RAMFUNC int MillerDecoding(int bit)\r\n{\r\n\t//int error = 0;\r\n\tint bitright;\r\n\r\n\tif(!Uart.bitBuffer) {\r\n\t\tUart.bitBuffer = bit ^ 0xFF0;\r\n\t\treturn FALSE;\r\n\t}\r\n\telse {\r\n\t\tUart.bitBuffer <<= 4;\r\n\t\tUart.bitBuffer ^= bit;\r\n\t}\r\n\r\n\tint EOC = FALSE;\r\n\r\n\tif(Uart.state != STATE_UNSYNCD) {\r\n\t\tUart.posCnt++;\r\n\r\n\t\tif((Uart.bitBuffer & Uart.syncBit) ^ Uart.syncBit) {\r\n\t\t\tbit = 0x00;\r\n\t\t}\r\n\t\telse {\r\n\t\t\tbit = 0x01;\r\n\t\t}\r\n\t\tif(((Uart.bitBuffer << 1) & Uart.syncBit) ^ Uart.syncBit) {\r\n\t\t\tbitright = 0x00;\r\n\t\t}\r\n\t\telse {\r\n\t\t\tbitright = 0x01;\r\n\t\t}\r\n\t\tif(bit != bitright) { bit = bitright; }\r\n\r\n\t\tif(Uart.posCnt == 1) {\r\n\t\t\t// measurement first half bitperiod\r\n\t\t\tif(!bit) {\r\n\t\t\t\tUart.drop = DROP_FIRST_HALF;\r\n\t\t\t}\r\n\t\t}\r\n\t\telse {\r\n\t\t\t// measurement second half bitperiod\r\n\t\t\tif(!bit & (Uart.drop == DROP_NONE)) {\r\n\t\t\t\tUart.drop = DROP_SECOND_HALF;\r\n\t\t\t}\r\n\t\t\telse if(!bit) {\r\n\t\t\t\t// measured a drop in first and second half\r\n\t\t\t\t// which should not be possible\r\n\t\t\t\tUart.state = STATE_ERROR_WAIT;\r\n\t\t\t\t//error = 0x01;\r\n\t\t\t}\r\n\r\n\t\t\tUart.posCnt = 0;\r\n\r\n\t\t\tswitch(Uart.state) {\r\n\t\t\t\tcase STATE_START_OF_COMMUNICATION:\r\n\t\t\t\t\tUart.shiftReg = 0;\r\n\t\t\t\t\tif(Uart.drop == DROP_SECOND_HALF) {\r\n\t\t\t\t\t\t// error, should not happen in SOC\r\n\t\t\t\t\t\tUart.state = STATE_ERROR_WAIT;\r\n\t\t\t\t\t\t//error = 0x02;\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse {\r\n\t\t\t\t\t\t// correct SOC\r\n\t\t\t\t\t\tUart.state = STATE_MILLER_Z;\r\n\t\t\t\t\t}\r\n\t\t\t\t\tbreak;\r\n\r\n\t\t\t\tcase STATE_MILLER_Z:\r\n\t\t\t\t\tUart.bitCnt++;\r\n\t\t\t\t\tUart.shiftReg >>= 1;\r\n\t\t\t\t\tif(Uart.drop == DROP_NONE) {\r\n\t\t\t\t\t\t// logic '0' followed by sequence Y\r\n\t\t\t\t\t\t// end of communication\r\n\t\t\t\t\t\tUart.state = STATE_UNSYNCD;\r\n\t\t\t\t\t\tEOC = TRUE;\r\n\t\t\t\t\t}\r\n\t\t\t\t\t// if(Uart.drop == DROP_FIRST_HALF) {\r\n\t\t\t\t\t// \tUart.state = STATE_MILLER_Z; stay the same\r\n\t\t\t\t\t// \twe see a logic '0' }\r\n\t\t\t\t\tif(Uart.drop == DROP_SECOND_HALF) {\r\n\t\t\t\t\t\t// we see a logic '1'\r\n\t\t\t\t\t\tUart.shiftReg |= 0x100;\r\n\t\t\t\t\t\tUart.state = STATE_MILLER_X;\r\n\t\t\t\t\t}\r\n\t\t\t\t\tbreak;\r\n\r\n\t\t\t\tcase STATE_MILLER_X:\r\n\t\t\t\t\tUart.shiftReg >>= 1;\r\n\t\t\t\t\tif(Uart.drop == DROP_NONE) {\r\n\t\t\t\t\t\t// sequence Y, we see a '0'\r\n\t\t\t\t\t\tUart.state = STATE_MILLER_Y;\r\n\t\t\t\t\t\tUart.bitCnt++;\r\n\t\t\t\t\t}\r\n\t\t\t\t\tif(Uart.drop == DROP_FIRST_HALF) {\r\n\t\t\t\t\t\t// Would be STATE_MILLER_Z\r\n\t\t\t\t\t\t// but Z does not follow X, so error\r\n\t\t\t\t\t\tUart.state = STATE_ERROR_WAIT;\r\n\t\t\t\t\t\t//error = 0x03;\r\n\t\t\t\t\t}\r\n\t\t\t\t\tif(Uart.drop == DROP_SECOND_HALF) {\r\n\t\t\t\t\t\t// We see a '1' and stay in state X\r\n\t\t\t\t\t\tUart.shiftReg |= 0x100;\r\n\t\t\t\t\t\tUart.bitCnt++;\r\n\t\t\t\t\t}\r\n\t\t\t\t\tbreak;\r\n\r\n\t\t\t\tcase STATE_MILLER_Y:\r\n\t\t\t\t\tUart.bitCnt++;\r\n\t\t\t\t\tUart.shiftReg >>= 1;\r\n\t\t\t\t\tif(Uart.drop == DROP_NONE) {\r\n\t\t\t\t\t\t// logic '0' followed by sequence Y\r\n\t\t\t\t\t\t// end of communication\r\n\t\t\t\t\t\tUart.state = STATE_UNSYNCD;\r\n\t\t\t\t\t\tEOC = TRUE;\r\n\t\t\t\t\t}\r\n\t\t\t\t\tif(Uart.drop == DROP_FIRST_HALF) {\r\n\t\t\t\t\t\t// we see a '0'\r\n\t\t\t\t\t\tUart.state = STATE_MILLER_Z;\r\n\t\t\t\t\t}\r\n\t\t\t\t\tif(Uart.drop == DROP_SECOND_HALF) {\r\n\t\t\t\t\t\t// We see a '1' and go to state X\r\n\t\t\t\t\t\tUart.shiftReg |= 0x100;\r\n\t\t\t\t\t\tUart.state = STATE_MILLER_X;\r\n\t\t\t\t\t}\r\n\t\t\t\t\tbreak;\r\n\r\n\t\t\t\tcase STATE_ERROR_WAIT:\r\n\t\t\t\t\t// That went wrong. Now wait for at least two bit periods\r\n\t\t\t\t\t// and try to sync again\r\n\t\t\t\t\tif(Uart.drop == DROP_NONE) {\r\n\t\t\t\t\t\tUart.highCnt = 6;\r\n\t\t\t\t\t\tUart.state = STATE_UNSYNCD;\r\n\t\t\t\t\t}\r\n\t\t\t\t\tbreak;\r\n\r\n\t\t\t\tdefault:\r\n\t\t\t\t\tUart.state = STATE_UNSYNCD;\r\n\t\t\t\t\tUart.highCnt = 0;\r\n\t\t\t\t\tbreak;\r\n\t\t\t}\r\n\r\n\t\t\tUart.drop = DROP_NONE;\r\n\r\n\t\t\t// should have received at least one whole byte...\r\n\t\t\tif((Uart.bitCnt == 2) && EOC && (Uart.byteCnt > 0)) {\r\n\t\t\t\treturn TRUE;\r\n\t\t\t}\r\n\r\n\t\t\tif(Uart.bitCnt == 9) {\r\n\t\t\t\tUart.output[Uart.byteCnt] = (Uart.shiftReg & 0xff);\r\n\t\t\t\tUart.byteCnt++;\r\n\r\n\t\t\t\tUart.parityBits <<= 1;\r\n\t\t\t\tUart.parityBits ^= ((Uart.shiftReg >> 8) & 0x01);\r\n\r\n\t\t\t\tif(EOC) {\r\n\t\t\t\t\t// when End of Communication received and\r\n\t\t\t\t\t// all data bits processed..\r\n\t\t\t\t\treturn TRUE;\r\n\t\t\t\t}\r\n\t\t\t\tUart.bitCnt = 0;\r\n\t\t\t}\r\n\r\n\t\t\t/*if(error) {\r\n\t\t\t\tUart.output[Uart.byteCnt] = 0xAA;\r\n\t\t\t\tUart.byteCnt++;\r\n\t\t\t\tUart.output[Uart.byteCnt] = error & 0xFF;\r\n\t\t\t\tUart.byteCnt++;\r\n\t\t\t\tUart.output[Uart.byteCnt] = 0xAA;\r\n\t\t\t\tUart.byteCnt++;\r\n\t\t\t\tUart.output[Uart.byteCnt] = (Uart.bitBuffer >> 8) & 0xFF;\r\n\t\t\t\tUart.byteCnt++;\r\n\t\t\t\tUart.output[Uart.byteCnt] = Uart.bitBuffer & 0xFF;\r\n\t\t\t\tUart.byteCnt++;\r\n\t\t\t\tUart.output[Uart.byteCnt] = (Uart.syncBit >> 3) & 0xFF;\r\n\t\t\t\tUart.byteCnt++;\r\n\t\t\t\tUart.output[Uart.byteCnt] = 0xAA;\r\n\t\t\t\tUart.byteCnt++;\r\n\t\t\t\treturn TRUE;\r\n\t\t\t}*/\r\n\t\t}\r\n\r\n\t}\r\n\telse {\r\n\t\tbit = Uart.bitBuffer & 0xf0;\r\n\t\tbit >>= 4;\r\n\t\tbit ^= 0x0F;\r\n\t\tif(bit) {\r\n\t\t\t// should have been high or at least (4 * 128) / fc\r\n\t\t\t// according to ISO this should be at least (9 * 128 + 20) / fc\r\n\t\t\tif(Uart.highCnt == 8) {\r\n\t\t\t\t// we went low, so this could be start of communication\r\n\t\t\t\t// it turns out to be safer to choose a less significant\r\n\t\t\t\t// syncbit... so we check whether the neighbour also represents the drop\r\n\t\t\t\tUart.posCnt = 1; // apparently we are busy with our first half bit period\r\n\t\t\t\tUart.syncBit = bit & 8;\r\n\t\t\t\tUart.samples = 3;\r\n\t\t\t\tif(!Uart.syncBit)\t{ Uart.syncBit = bit & 4; Uart.samples = 2; }\r\n\t\t\t\telse if(bit & 4)\t{ Uart.syncBit = bit & 4; Uart.samples = 2; bit <<= 2; }\r\n\t\t\t\tif(!Uart.syncBit)\t{ Uart.syncBit = bit & 2; Uart.samples = 1; }\r\n\t\t\t\telse if(bit & 2)\t{ Uart.syncBit = bit & 2; Uart.samples = 1; bit <<= 1; }\r\n\t\t\t\tif(!Uart.syncBit)\t{ Uart.syncBit = bit & 1; Uart.samples = 0;\r\n\t\t\t\t\tif(Uart.syncBit && (Uart.bitBuffer & 8)) {\r\n\t\t\t\t\t\tUart.syncBit = 8;\r\n\r\n\t\t\t\t\t\t// the first half bit period is expected in next sample\r\n\t\t\t\t\t\tUart.posCnt = 0;\r\n\t\t\t\t\t\tUart.samples = 3;\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\telse if(bit & 1)\t{ Uart.syncBit = bit & 1; Uart.samples = 0; }\r\n\r\n\t\t\t\tUart.syncBit <<= 4;\r\n\t\t\t\tUart.state = STATE_START_OF_COMMUNICATION;\r\n\t\t\t\tUart.drop = DROP_FIRST_HALF;\r\n\t\t\t\tUart.bitCnt = 0;\r\n\t\t\t\tUart.byteCnt = 0;\r\n\t\t\t\tUart.parityBits = 0;\r\n\t\t\t\t//error = 0;\r\n\t\t\t}\r\n\t\t\telse {\r\n\t\t\t\tUart.highCnt = 0;\r\n\t\t\t}\r\n\t\t}\r\n\t\telse {\r\n\t\t\tif(Uart.highCnt < 8) {\r\n\t\t\t\tUart.highCnt++;\r\n\t\t\t}\r\n\t\t}\r\n\t}\r\n\r\n return FALSE;\r\n}\r\n\r\n//=============================================================================\r\n// ISO 14443 Type A - Manchester\r\n//=============================================================================\r\nstatic tDemod Demod;\r\n\r\nstatic RAMFUNC int ManchesterDecoding(int v)\r\n{\r\n\tint bit;\r\n\tint modulation;\r\n\t//int error = 0;\r\n\r\n\tif(!Demod.buff) {\r\n\t\tDemod.buff = 1;\r\n\t\tDemod.buffer = v;\r\n\t\treturn FALSE;\r\n\t}\r\n\telse {\r\n\t\tbit = Demod.buffer;\r\n\t\tDemod.buffer = v;\r\n\t}\r\n\r\n\tif(Demod.state==DEMOD_UNSYNCD) {\r\n\t\tDemod.output[Demod.len] = 0xfa;\r\n\t\tDemod.syncBit = 0;\r\n\t\t//Demod.samples = 0;\r\n\t\tDemod.posCount = 1;\t\t// This is the first half bit period, so after syncing handle the second part\r\n\r\n\t\tif(bit & 0x08) {\r\n\t\t\tDemod.syncBit = 0x08;\r\n\t\t}\r\n\r\n\t\tif(bit & 0x04) {\r\n\t\t\tif(Demod.syncBit) {\r\n\t\t\t\tbit <<= 4;\r\n\t\t\t}\r\n\t\t\tDemod.syncBit = 0x04;\r\n\t\t}\r\n\r\n\t\tif(bit & 0x02) {\r\n\t\t\tif(Demod.syncBit) {\r\n\t\t\t\tbit <<= 2;\r\n\t\t\t}\r\n\t\t\tDemod.syncBit = 0x02;\r\n\t\t}\r\n\r\n\t\tif(bit & 0x01 && Demod.syncBit) {\r\n\t\t\tDemod.syncBit = 0x01;\r\n\t\t}\r\n\t\t\r\n\t\tif(Demod.syncBit) {\r\n\t\t\tDemod.len = 0;\r\n\t\t\tDemod.state = DEMOD_START_OF_COMMUNICATION;\r\n\t\t\tDemod.sub = SUB_FIRST_HALF;\r\n\t\t\tDemod.bitCount = 0;\r\n\t\t\tDemod.shiftReg = 0;\r\n\t\t\tDemod.parityBits = 0;\r\n\t\t\tDemod.samples = 0;\r\n\t\t\tif(Demod.posCount) {\r\n\t\t\t\tif(trigger) LED_A_OFF();\r\n\t\t\t\tswitch(Demod.syncBit) {\r\n\t\t\t\t\tcase 0x08: Demod.samples = 3; break;\r\n\t\t\t\t\tcase 0x04: Demod.samples = 2; break;\r\n\t\t\t\t\tcase 0x02: Demod.samples = 1; break;\r\n\t\t\t\t\tcase 0x01: Demod.samples = 0; break;\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\t//error = 0;\r\n\t\t}\r\n\t}\r\n\telse {\r\n\t\t//modulation = bit & Demod.syncBit;\r\n\t\tmodulation = ((bit << 1) ^ ((Demod.buffer & 0x08) >> 3)) & Demod.syncBit;\r\n\r\n\t\tDemod.samples += 4;\r\n\r\n\t\tif(Demod.posCount==0) {\r\n\t\t\tDemod.posCount = 1;\r\n\t\t\tif(modulation) {\r\n\t\t\t\tDemod.sub = SUB_FIRST_HALF;\r\n\t\t\t}\r\n\t\t\telse {\r\n\t\t\t\tDemod.sub = SUB_NONE;\r\n\t\t\t}\r\n\t\t}\r\n\t\telse {\r\n\t\t\tDemod.posCount = 0;\r\n\t\t\tif(modulation && (Demod.sub == SUB_FIRST_HALF)) {\r\n\t\t\t\tif(Demod.state!=DEMOD_ERROR_WAIT) {\r\n\t\t\t\t\tDemod.state = DEMOD_ERROR_WAIT;\r\n\t\t\t\t\tDemod.output[Demod.len] = 0xaa;\r\n\t\t\t\t\t//error = 0x01;\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\telse if(modulation) {\r\n\t\t\t\tDemod.sub = SUB_SECOND_HALF;\r\n\t\t\t}\r\n\r\n\t\t\tswitch(Demod.state) {\r\n\t\t\t\tcase DEMOD_START_OF_COMMUNICATION:\r\n\t\t\t\t\tif(Demod.sub == SUB_FIRST_HALF) {\r\n\t\t\t\t\t\tDemod.state = DEMOD_MANCHESTER_D;\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse {\r\n\t\t\t\t\t\tDemod.output[Demod.len] = 0xab;\r\n\t\t\t\t\t\tDemod.state = DEMOD_ERROR_WAIT;\r\n\t\t\t\t\t\t//error = 0x02;\r\n\t\t\t\t\t}\r\n\t\t\t\t\tbreak;\r\n\r\n\t\t\t\tcase DEMOD_MANCHESTER_D:\r\n\t\t\t\tcase DEMOD_MANCHESTER_E:\r\n\t\t\t\t\tif(Demod.sub == SUB_FIRST_HALF) {\r\n\t\t\t\t\t\tDemod.bitCount++;\r\n\t\t\t\t\t\tDemod.shiftReg = (Demod.shiftReg >> 1) ^ 0x100;\r\n\t\t\t\t\t\tDemod.state = DEMOD_MANCHESTER_D;\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse if(Demod.sub == SUB_SECOND_HALF) {\r\n\t\t\t\t\t\tDemod.bitCount++;\r\n\t\t\t\t\t\tDemod.shiftReg >>= 1;\r\n\t\t\t\t\t\tDemod.state = DEMOD_MANCHESTER_E;\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse {\r\n\t\t\t\t\t\tDemod.state = DEMOD_MANCHESTER_F;\r\n\t\t\t\t\t}\r\n\t\t\t\t\tbreak;\r\n\r\n\t\t\t\tcase DEMOD_MANCHESTER_F:\r\n\t\t\t\t\t// Tag response does not need to be a complete byte!\r\n\t\t\t\t\tif(Demod.len > 0 || Demod.bitCount > 0) {\r\n\t\t\t\t\t\tif(Demod.bitCount > 0) {\r\n\t\t\t\t\t\t\tDemod.shiftReg >>= (9 - Demod.bitCount);\r\n\t\t\t\t\t\t\tDemod.output[Demod.len] = Demod.shiftReg & 0xff;\r\n\t\t\t\t\t\t\tDemod.len++;\r\n\t\t\t\t\t\t\t// No parity bit, so just shift a 0\r\n\t\t\t\t\t\t\tDemod.parityBits <<= 1;\r\n\t\t\t\t\t\t}\r\n\r\n\t\t\t\t\t\tDemod.state = DEMOD_UNSYNCD;\r\n\t\t\t\t\t\treturn TRUE;\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse {\r\n\t\t\t\t\t\tDemod.output[Demod.len] = 0xad;\r\n\t\t\t\t\t\tDemod.state = DEMOD_ERROR_WAIT;\r\n\t\t\t\t\t\t//error = 0x03;\r\n\t\t\t\t\t}\r\n\t\t\t\t\tbreak;\r\n\r\n\t\t\t\tcase DEMOD_ERROR_WAIT:\r\n\t\t\t\t\tDemod.state = DEMOD_UNSYNCD;\r\n\t\t\t\t\tbreak;\r\n\r\n\t\t\t\tdefault:\r\n\t\t\t\t\tDemod.output[Demod.len] = 0xdd;\r\n\t\t\t\t\tDemod.state = DEMOD_UNSYNCD;\r\n\t\t\t\t\tbreak;\r\n\t\t\t}\r\n\r\n\t\t\tif(Demod.bitCount>=9) {\r\n\t\t\t\tDemod.output[Demod.len] = Demod.shiftReg & 0xff;\r\n\t\t\t\tDemod.len++;\r\n\r\n\t\t\t\tDemod.parityBits <<= 1;\r\n\t\t\t\tDemod.parityBits ^= ((Demod.shiftReg >> 8) & 0x01);\r\n\r\n\t\t\t\tDemod.bitCount = 0;\r\n\t\t\t\tDemod.shiftReg = 0;\r\n\t\t\t}\r\n\r\n\t\t\t/*if(error) {\r\n\t\t\t\tDemod.output[Demod.len] = 0xBB;\r\n\t\t\t\tDemod.len++;\r\n\t\t\t\tDemod.output[Demod.len] = error & 0xFF;\r\n\t\t\t\tDemod.len++;\r\n\t\t\t\tDemod.output[Demod.len] = 0xBB;\r\n\t\t\t\tDemod.len++;\r\n\t\t\t\tDemod.output[Demod.len] = bit & 0xFF;\r\n\t\t\t\tDemod.len++;\r\n\t\t\t\tDemod.output[Demod.len] = Demod.buffer & 0xFF;\r\n\t\t\t\tDemod.len++;\r\n\t\t\t\tDemod.output[Demod.len] = Demod.syncBit & 0xFF;\r\n\t\t\t\tDemod.len++;\r\n\t\t\t\tDemod.output[Demod.len] = 0xBB;\r\n\t\t\t\tDemod.len++;\r\n\t\t\t\treturn TRUE;\r\n\t\t\t}*/\r\n\r\n\t\t}\r\n\r\n\t} // end (state != UNSYNCED)\r\n\r\n return FALSE;\r\n}\r\n\r\n//=============================================================================\r\n// Finally, a `sniffer' for ISO 14443 Type A\r\n// Both sides of communication!\r\n//=============================================================================\r\n\r\n//-----------------------------------------------------------------------------\r\n// Record the sequence of commands sent by the reader to the tag, with\r\n// triggering so that we start recording at the point that the tag is moved\r\n// near the reader.\r\n//-----------------------------------------------------------------------------\r\nvoid RAMFUNC SnoopIso14443a(uint8_t param) {\r\n\t// param:\r\n\t// bit 0 - trigger from first card answer\r\n\t// bit 1 - trigger from first reader 7-bit request\r\n\t\r\n\tLEDsoff();\r\n\t// init trace buffer\r\n iso14a_clear_trace();\r\n\r\n\t// We won't start recording the frames that we acquire until we trigger;\r\n\t// a good trigger condition to get started is probably when we see a\r\n\t// response from the tag.\r\n\t// triggered == FALSE -- to wait first for card\r\n\tint triggered = !(param & 0x03); \r\n\r\n\t// The command (reader -> tag) that we're receiving.\r\n\t// The length of a received command will in most cases be no more than 18 bytes.\r\n\t// So 32 should be enough!\r\n\tuint8_t *receivedCmd = (((uint8_t *)BigBuf) + RECV_CMD_OFFSET);\r\n\t// The response (tag -> reader) that we're receiving.\r\n\tuint8_t *receivedResponse = (((uint8_t *)BigBuf) + RECV_RES_OFFSET);\r\n\r\n\t// As we receive stuff, we copy it from receivedCmd or receivedResponse\r\n\t// into trace, along with its length and other annotations.\r\n\t//uint8_t *trace = (uint8_t *)BigBuf;\r\n\t\r\n\t// The DMA buffer, used to stream samples from the FPGA\r\n\tint8_t *dmaBuf = ((int8_t *)BigBuf) + DMA_BUFFER_OFFSET;\r\n\tint8_t *data = dmaBuf;\r\n\tint maxDataLen = 0;\r\n\tint dataLen = 0;\r\n\r\n\t// Set up the demodulator for tag -> reader responses.\r\n\tDemod.output = receivedResponse;\r\n\tDemod.len = 0;\r\n\tDemod.state = DEMOD_UNSYNCD;\r\n\r\n\t// Set up the demodulator for the reader -> tag commands\r\n\tmemset(&Uart, 0, sizeof(Uart));\r\n\tUart.output = receivedCmd;\r\n\tUart.byteCntMax = 32; // was 100 (greg)//////////////////\r\n\tUart.state = STATE_UNSYNCD;\r\n\r\n\t// Setup for the DMA.\r\n\tFpgaSetupSsc();\r\n\tFpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);\r\n\r\n\t// And put the FPGA in the appropriate mode\r\n\t// Signal field is off with the appropriate LED\r\n\tLED_D_OFF();\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_SNIFFER);\r\n\tSetAdcMuxFor(GPIO_MUXSEL_HIPKD);\r\n\r\n\t// Count of samples received so far, so that we can include timing\r\n\t// information in the trace buffer.\r\n\trsamples = 0;\r\n\t// And now we loop, receiving samples.\r\n\twhile(true) {\r\n\t\tif(BUTTON_PRESS()) {\r\n\t\t\tDbpString(\"cancelled by button\");\r\n\t\t\tgoto done;\r\n\t\t}\r\n\r\n\t\tLED_A_ON();\r\n\t\tWDT_HIT();\r\n\r\n\t\tint register readBufDataP = data - dmaBuf;\r\n\t\tint register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR;\r\n\t\tif (readBufDataP <= dmaBufDataP){\r\n\t\t\tdataLen = dmaBufDataP - readBufDataP;\r\n\t\t} else {\r\n\t\t\tdataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP + 1;\r\n\t\t}\r\n\t\t// test for length of buffer\r\n\t\tif(dataLen > maxDataLen) {\r\n\t\t\tmaxDataLen = dataLen;\r\n\t\t\tif(dataLen > 400) {\r\n\t\t\t\tDbprintf(\"blew circular buffer! dataLen=0x%x\", dataLen);\r\n\t\t\t\tgoto done;\r\n\t\t\t}\r\n\t\t}\r\n\t\tif(dataLen < 1) continue;\r\n\r\n\t\t// primary buffer was stopped( <-- we lost data!\r\n\t\tif (!AT91C_BASE_PDC_SSC->PDC_RCR) {\r\n\t\t\tAT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;\r\n\t\t\tAT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;\r\n\t\t}\r\n\t\t// secondary buffer sets as primary, secondary buffer was stopped\r\n\t\tif (!AT91C_BASE_PDC_SSC->PDC_RNCR) {\r\n\t\t\tAT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;\r\n\t\t\tAT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;\r\n\t\t}\r\n\r\n\t\tLED_A_OFF();\r\n\t\t\r\n\t\trsamples += 4;\r\n\t\tif(MillerDecoding((data[0] & 0xF0) >> 4)) {\r\n\t\t\tLED_C_ON();\r\n\r\n\t\t\t// check - if there is a short 7bit request from reader\r\n\t\t\tif ((!triggered) && (param & 0x02) && (Uart.byteCnt == 1) && (Uart.bitCnt = 9)) triggered = TRUE;\r\n\r\n\t\t\tif(triggered) {\r\n\t\t\t\tif (!LogTrace(receivedCmd, Uart.byteCnt, 0 - Uart.samples, Uart.parityBits, TRUE)) break;\r\n\t\t\t}\r\n\t\t\t/* And ready to receive another command. */\r\n\t\t\tUart.state = STATE_UNSYNCD;\r\n\t\t\t/* And also reset the demod code, which might have been */\r\n\t\t\t/* false-triggered by the commands from the reader. */\r\n\t\t\tDemod.state = DEMOD_UNSYNCD;\r\n\t\t\tLED_B_OFF();\r\n\t\t}\r\n\r\n\t\tif(ManchesterDecoding(data[0] & 0x0F)) {\r\n\t\t\tLED_B_ON();\r\n\r\n\t\t\tif (!LogTrace(receivedResponse, Demod.len, 0 - Demod.samples, Demod.parityBits, FALSE)) break;\r\n\r\n\t\t\tif ((!triggered) && (param & 0x01)) triggered = TRUE;\r\n\r\n\t\t\t// And ready to receive another response.\r\n\t\t\tmemset(&Demod, 0, sizeof(Demod));\r\n\t\t\tDemod.output = receivedResponse;\r\n\t\t\tDemod.state = DEMOD_UNSYNCD;\r\n\t\t\tLED_C_OFF();\r\n\t\t}\r\n\r\n\t\tdata++;\r\n\t\tif(data > dmaBuf + DMA_BUFFER_SIZE) {\r\n\t\t\tdata = dmaBuf;\r\n\t\t}\r\n\t} // main cycle\r\n\r\n\tDbpString(\"COMMAND FINISHED\");\r\n\r\ndone:\r\n\tAT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;\r\n\tDbprintf(\"maxDataLen=%x, Uart.state=%x, Uart.byteCnt=%x\", maxDataLen, Uart.state, Uart.byteCnt);\r\n\tDbprintf(\"Uart.byteCntMax=%x, traceLen=%x, Uart.output[0]=%08x\", Uart.byteCntMax, traceLen, (int)Uart.output[0]);\r\n\tLEDsoff();\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// Prepare tag messages\r\n//-----------------------------------------------------------------------------\r\nstatic void CodeIso14443aAsTagPar(const uint8_t *cmd, int len, uint32_t dwParity)\r\n{\r\n\tint i;\r\n\r\n\tToSendReset();\r\n\r\n\t// Correction bit, might be removed when not needed\r\n\tToSendStuffBit(0);\r\n\tToSendStuffBit(0);\r\n\tToSendStuffBit(0);\r\n\tToSendStuffBit(0);\r\n\tToSendStuffBit(1); // 1\r\n\tToSendStuffBit(0);\r\n\tToSendStuffBit(0);\r\n\tToSendStuffBit(0);\r\n\t\r\n\t// Send startbit\r\n\tToSend[++ToSendMax] = SEC_D;\r\n\r\n\tfor(i = 0; i < len; i++) {\r\n\t\tint j;\r\n\t\tuint8_t b = cmd[i];\r\n\r\n\t\t// Data bits\r\n\t\tfor(j = 0; j < 8; j++) {\r\n\t\t\tif(b & 1) {\r\n\t\t\t\tToSend[++ToSendMax] = SEC_D;\r\n\t\t\t} else {\r\n\t\t\t\tToSend[++ToSendMax] = SEC_E;\r\n\t\t\t}\r\n\t\t\tb >>= 1;\r\n\t\t}\r\n\r\n\t\t// Get the parity bit\r\n\t\tif ((dwParity >> i) & 0x01) {\r\n\t\t\tToSend[++ToSendMax] = SEC_D;\r\n\t\t} else {\r\n\t\t\tToSend[++ToSendMax] = SEC_E;\r\n\t\t}\r\n\t}\r\n\r\n\t// Send stopbit\r\n\tToSend[++ToSendMax] = SEC_F;\r\n\r\n\t// Convert from last byte pos to length\r\n\tToSendMax++;\r\n}\r\n\r\nstatic void CodeIso14443aAsTag(const uint8_t *cmd, int len){\r\n\tCodeIso14443aAsTagPar(cmd, len, GetParity(cmd, len));\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// This is to send a NACK kind of answer, its only 3 bits, I know it should be 4\r\n//-----------------------------------------------------------------------------\r\nstatic void CodeStrangeAnswerAsTag()\r\n{\r\n\tint i;\r\n\r\n ToSendReset();\r\n\r\n\t// Correction bit, might be removed when not needed\r\n\tToSendStuffBit(0);\r\n\tToSendStuffBit(0);\r\n\tToSendStuffBit(0);\r\n\tToSendStuffBit(0);\r\n\tToSendStuffBit(1); // 1\r\n\tToSendStuffBit(0);\r\n\tToSendStuffBit(0);\r\n\tToSendStuffBit(0);\r\n\r\n\t// Send startbit\r\n\tToSend[++ToSendMax] = SEC_D;\r\n\r\n\t// 0\r\n\tToSend[++ToSendMax] = SEC_E;\r\n\r\n\t// 0\r\n\tToSend[++ToSendMax] = SEC_E;\r\n\r\n\t// 1\r\n\tToSend[++ToSendMax] = SEC_D;\r\n\r\n // Send stopbit\r\n\tToSend[++ToSendMax] = SEC_F;\r\n\r\n\t// Flush the buffer in FPGA!!\r\n\tfor(i = 0; i < 5; i++) {\r\n\t\tToSend[++ToSendMax] = SEC_F;\r\n\t}\r\n\r\n // Convert from last byte pos to length\r\n ToSendMax++;\r\n}\r\n\r\nstatic void Code4bitAnswerAsTag(uint8_t cmd)\r\n{\r\n\tint i;\r\n\r\n ToSendReset();\r\n\r\n\t// Correction bit, might be removed when not needed\r\n\tToSendStuffBit(0);\r\n\tToSendStuffBit(0);\r\n\tToSendStuffBit(0);\r\n\tToSendStuffBit(0);\r\n\tToSendStuffBit(1); // 1\r\n\tToSendStuffBit(0);\r\n\tToSendStuffBit(0);\r\n\tToSendStuffBit(0);\r\n\r\n\t// Send startbit\r\n\tToSend[++ToSendMax] = SEC_D;\r\n\r\n\tuint8_t b = cmd;\r\n\tfor(i = 0; i < 4; i++) {\r\n\t\tif(b & 1) {\r\n\t\t\tToSend[++ToSendMax] = SEC_D;\r\n\t\t} else {\r\n\t\t\tToSend[++ToSendMax] = SEC_E;\r\n\t\t}\r\n\t\tb >>= 1;\r\n\t}\r\n\r\n\t// Send stopbit\r\n\tToSend[++ToSendMax] = SEC_F;\r\n\r\n\t// Flush the buffer in FPGA!!\r\n\tfor(i = 0; i < 5; i++) {\r\n\t\tToSend[++ToSendMax] = SEC_F;\r\n\t}\r\n\r\n // Convert from last byte pos to length\r\n ToSendMax++;\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// Wait for commands from reader\r\n// Stop when button is pressed\r\n// Or return TRUE when command is captured\r\n//-----------------------------------------------------------------------------\r\nstatic int GetIso14443aCommandFromReader(uint8_t *received, int *len, int maxLen)\r\n{\r\n // Set FPGA mode to \"simulated ISO 14443 tag\", no modulation (listen\r\n // only, since we are receiving, not transmitting).\r\n // Signal field is off with the appropriate LED\r\n LED_D_OFF();\r\n FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);\r\n\r\n // Now run a `software UART' on the stream of incoming samples.\r\n Uart.output = received;\r\n Uart.byteCntMax = maxLen;\r\n Uart.state = STATE_UNSYNCD;\r\n\r\n for(;;) {\r\n WDT_HIT();\r\n\r\n if(BUTTON_PRESS()) return FALSE;\r\n\r\n if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r\n AT91C_BASE_SSC->SSC_THR = 0x00;\r\n }\r\n if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r\n uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;\r\n\t\t\tif(MillerDecoding((b & 0xf0) >> 4)) {\r\n\t\t\t\t*len = Uart.byteCnt;\r\n\t\t\t\treturn TRUE;\r\n\t\t\t}\r\n\t\t\tif(MillerDecoding(b & 0x0f)) {\r\n\t\t\t\t*len = Uart.byteCnt;\r\n\t\t\t\treturn TRUE;\r\n\t\t\t}\r\n }\r\n }\r\n}\r\n\r\nstatic int EmSendCmd14443aRaw(uint8_t *resp, int respLen, int correctionNeeded);\r\nint EmSend4bitEx(uint8_t resp, int correctionNeeded);\r\nint EmSend4bit(uint8_t resp);\r\nint EmSendCmdExPar(uint8_t *resp, int respLen, int correctionNeeded, uint32_t par);\r\nint EmSendCmdExPar(uint8_t *resp, int respLen, int correctionNeeded, uint32_t par);\r\nint EmSendCmdEx(uint8_t *resp, int respLen, int correctionNeeded);\r\nint EmSendCmd(uint8_t *resp, int respLen);\r\nint EmSendCmdPar(uint8_t *resp, int respLen, uint32_t par);\r\n\r\n//-----------------------------------------------------------------------------\r\n// Main loop of simulated tag: receive commands from reader, decide what\r\n// response to send, and send it.\r\n//-----------------------------------------------------------------------------\r\nvoid SimulateIso14443aTag(int tagType, int uid_1st, int uid_2nd, byte_t* data)\r\n{\r\n // Enable and clear the trace\r\n\ttracing = TRUE;\r\n iso14a_clear_trace();\r\n\r\n\t// This function contains the tag emulation\r\n\tuint8_t sak;\r\n\r\n\t// The first response contains the ATQA (note: bytes are transmitted in reverse order).\r\n\tuint8_t response1[2];\r\n\t\r\n\tswitch (tagType) {\r\n\t\tcase 1: { // MIFARE Classic\r\n\t\t\t// Says: I am Mifare 1k - original line\r\n\t\t\tresponse1[0] = 0x04;\r\n\t\t\tresponse1[1] = 0x00;\r\n\t\t\tsak = 0x08;\r\n\t\t} break;\r\n\t\tcase 2: { // MIFARE Ultralight\r\n\t\t\t// Says: I am a stupid memory tag, no crypto\r\n\t\t\tresponse1[0] = 0x04;\r\n\t\t\tresponse1[1] = 0x00;\r\n\t\t\tsak = 0x00;\r\n\t\t} break;\r\n\t\tcase 3: { // MIFARE DESFire\r\n\t\t\t// Says: I am a DESFire tag, ph33r me\r\n\t\t\tresponse1[0] = 0x04;\r\n\t\t\tresponse1[1] = 0x03;\r\n\t\t\tsak = 0x20;\r\n\t\t} break;\r\n\t\tcase 4: { // ISO/IEC 14443-4\r\n\t\t\t// Says: I am a javacard (JCOP)\r\n\t\t\tresponse1[0] = 0x04;\r\n\t\t\tresponse1[1] = 0x00;\r\n\t\t\tsak = 0x28;\r\n\t\t} break;\r\n\t\tdefault: {\r\n\t\t\tDbprintf(\"Error: unkown tagtype (%d)\",tagType);\r\n\t\t\treturn;\r\n\t\t} break;\r\n\t}\r\n\t\r\n\t// The second response contains the (mandatory) first 24 bits of the UID\r\n\tuint8_t response2[5];\r\n\r\n\t// Check if the uid uses the (optional) part\r\n\tuint8_t response2a[5];\r\n\tif (uid_2nd) {\r\n\t\tresponse2[0] = 0x88;\r\n\t\tnum_to_bytes(uid_1st,3,response2+1);\r\n\t\tnum_to_bytes(uid_2nd,4,response2a);\r\n\t\tresponse2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3];\r\n\r\n\t\t// Configure the ATQA and SAK accordingly\r\n\t\tresponse1[0] |= 0x40;\r\n\t\tsak |= 0x04;\r\n\t} else {\r\n\t\tnum_to_bytes(uid_1st,4,response2);\r\n\t\t// Configure the ATQA and SAK accordingly\r\n\t\tresponse1[0] &= 0xBF;\r\n\t\tsak &= 0xFB;\r\n\t}\r\n\r\n\t// Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.\r\n\tresponse2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3];\r\n\r\n\t// Prepare the mandatory SAK (for 4 and 7 byte UID)\r\n\tuint8_t response3[3];\r\n\tresponse3[0] = sak;\r\n\tComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]);\r\n\r\n\t// Prepare the optional second SAK (for 7 byte UID), drop the cascade bit\r\n\tuint8_t response3a[3];\r\n\tresponse3a[0] = sak & 0xFB;\r\n\tComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]);\r\n\r\n\tuint8_t response5[] = { 0x00, 0x00, 0x00, 0x00 }; // Very random tag nonce\r\n\tuint8_t response6[] = { 0x03, 0x3B, 0x00, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS\r\n\tComputeCrc14443(CRC_14443_A, response6, 3, &response6[3], &response6[4]);\r\n\r\n\tuint8_t *resp = NULL;\r\n\tint respLen;\r\n\r\n // Longest possible response will be 16 bytes + 2 CRC = 18 bytes\r\n\t// This will need\r\n\t// 144 data bits (18 * 8)\r\n\t// 18 parity bits\r\n\t// 2 Start and stop\r\n\t// 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)\r\n\t// 1 just for the case\r\n\t// ----------- +\r\n\t// 166\r\n\t//\r\n\t// 166 bytes, since every bit that needs to be send costs us a byte\r\n\t//\r\n\r\n\t// Respond with card type\r\n\tuint8_t *resp1 = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET);\r\n\tint resp1Len;\r\n\r\n\t// Anticollision cascade1 - respond with uid\r\n\tuint8_t *resp2 = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET + 166);\r\n\tint resp2Len;\r\n\r\n\t// Anticollision cascade2 - respond with 2nd half of uid if asked\r\n\t// we're only going to be asked if we set the 1st byte of the UID (during cascade1) to 0x88\r\n\tuint8_t *resp2a = (((uint8_t *)BigBuf) + 1140);\r\n\tint resp2aLen;\r\n\r\n\t// Acknowledge select - cascade 1\r\n\tuint8_t *resp3 = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET + (166*2));\r\n\tint resp3Len;\r\n\r\n\t// Acknowledge select - cascade 2\r\n\tuint8_t *resp3a = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET + (166*3));\r\n\tint resp3aLen;\r\n\r\n\t// Response to a read request - not implemented atm\r\n\tuint8_t *resp4 = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET + (166*4));\r\n//\tint resp4Len;\r\n\r\n\t// Authenticate response - nonce\r\n\tuint8_t *resp5 = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET + (166*5));\r\n\tint resp5Len;\r\n\r\n\t// Authenticate response - nonce\r\n\tuint8_t *resp6 = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET + (166*6));\r\n\tint resp6Len;\r\n\r\n\tuint8_t *receivedCmd = (((uint8_t *)BigBuf) + RECV_CMD_OFFSET);\r\n\tint len;\r\n\r\n\t// To control where we are in the protocol\r\n\tint order = 0;\r\n\tint lastorder;\r\n\r\n\t// Just to allow some checks\r\n\tint happened = 0;\r\n\tint happened2 = 0;\r\n\r\n\tint cmdsRecvd = 0;\r\n\tuint8_t* respdata = NULL;\r\n\tint respsize = 0;\r\n//\tuint8_t nack = 0x04;\r\n\r\n\tmemset(receivedCmd, 0x44, RECV_CMD_SIZE);\r\n\r\n\t// Prepare the responses of the anticollision phase\r\n\t// there will be not enough time to do this at the moment the reader sends it REQA\r\n\r\n\t// Answer to request\r\n\tCodeIso14443aAsTag(response1, sizeof(response1));\r\n\tmemcpy(resp1, ToSend, ToSendMax); resp1Len = ToSendMax;\r\n\r\n\t// Send our UID (cascade 1)\r\n\tCodeIso14443aAsTag(response2, sizeof(response2));\r\n\tmemcpy(resp2, ToSend, ToSendMax); resp2Len = ToSendMax;\r\n\r\n\t// Answer to select (cascade1)\r\n\tCodeIso14443aAsTag(response3, sizeof(response3));\r\n\tmemcpy(resp3, ToSend, ToSendMax); resp3Len = ToSendMax;\r\n\r\n\t// Send the cascade 2 2nd part of the uid\r\n\tCodeIso14443aAsTag(response2a, sizeof(response2a));\r\n\tmemcpy(resp2a, ToSend, ToSendMax); resp2aLen = ToSendMax;\r\n\r\n\t// Answer to select (cascade 2)\r\n\tCodeIso14443aAsTag(response3a, sizeof(response3a));\r\n\tmemcpy(resp3a, ToSend, ToSendMax); resp3aLen = ToSendMax;\r\n\r\n\t// Strange answer is an example of rare message size (3 bits)\r\n\tCodeStrangeAnswerAsTag();\r\n\tmemcpy(resp4, ToSend, ToSendMax);// resp4Len = ToSendMax;\r\n\r\n\t// Authentication answer (random nonce)\r\n\tCodeIso14443aAsTag(response5, sizeof(response5));\r\n\tmemcpy(resp5, ToSend, ToSendMax); resp5Len = ToSendMax;\r\n\r\n\t// dummy ATS (pseudo-ATR), answer to RATS\r\n\tCodeIso14443aAsTag(response6, sizeof(response6));\r\n\tmemcpy(resp6, ToSend, ToSendMax); resp6Len = ToSendMax;\r\n\r\n\t// We need to listen to the high-frequency, peak-detected path.\r\n\tSetAdcMuxFor(GPIO_MUXSEL_HIPKD);\r\n\tFpgaSetupSsc();\r\n\r\n\tcmdsRecvd = 0;\r\n\r\n\tLED_A_ON();\r\n\tfor(;;) {\r\n\t\r\n\t\tif(!GetIso14443aCommandFromReader(receivedCmd, &len, RECV_CMD_SIZE)) {\r\n\t\t\tDbpString(\"button press\");\r\n\t\t\tbreak;\r\n\t\t}\r\n \r\n if (tracing) {\r\n\t\t\tLogTrace(receivedCmd,len, 0, Uart.parityBits, TRUE);\r\n }\r\n \r\n\t\t// doob - added loads of debug strings so we can see what the reader is saying to us during the sim as hi14alist is not populated\r\n\t\t// Okay, look at the command now.\r\n\t\tlastorder = order;\r\n\t\tif(receivedCmd[0] == 0x26) { // Received a REQUEST\r\n\t\t\tresp = resp1; respLen = resp1Len; order = 1;\r\n\t\t\trespdata = response1;\r\n\t\t\trespsize = sizeof(response1);\r\n\t\t} else if(receivedCmd[0] == 0x52) { // Received a WAKEUP\r\n\t\t\tresp = resp1; respLen = resp1Len; order = 6;\r\n\t\t\trespdata = response1;\r\n\t\t\trespsize = sizeof(response1);\r\n\t\t} else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x93) {\t// Received request for UID (cascade 1)\r\n\t\t\tresp = resp2; respLen = resp2Len; order = 2;\r\n\t\t\trespdata = response2;\r\n\t\t\trespsize = sizeof(response2);\r\n\t\t} else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x95) { // Received request for UID (cascade 2)\r\n\t\t\tresp = resp2a; respLen = resp2aLen; order = 20;\r\n\t\t\trespdata = response2a;\r\n\t\t\trespsize = sizeof(response2a);\r\n\t\t} else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x93) {\t// Received a SELECT (cascade 1)\r\n\t\t\tresp = resp3; respLen = resp3Len; order = 3;\r\n\t\t\trespdata = response3;\r\n\t\t\trespsize = sizeof(response3);\r\n\t\t} else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x95) {\t// Received a SELECT (cascade 2)\r\n\t\t\tresp = resp3a; respLen = resp3aLen; order = 30;\r\n\t\t\trespdata = response3a;\r\n\t\t\trespsize = sizeof(response3a);\r\n\t\t} else if(receivedCmd[0] == 0x30) {\t// Received a (plain) READ\r\n//\t\t\tresp = resp4; respLen = resp4Len; order = 4; // Do nothing\r\n//\t\t\trespdata = &nack;\r\n//\t\t\trespsize = sizeof(nack); // 4-bit answer\r\n EmSendCmdEx(data+(4*receivedCmd[0]),16,false);\r\n\t\t\tDbprintf(\"Read request from reader: %x %x\",receivedCmd[0],receivedCmd[1]);\r\n // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below\r\n respLen = 0;\r\n\t\t} else if(receivedCmd[0] == 0x50) {\t// Received a HALT\r\n//\t\t\tDbpString(\"Reader requested we HALT!:\");\r\n\t\t\t// Do not respond\r\n\t\t\tresp = resp1; respLen = 0; order = 0;\r\n\t\t\trespdata = NULL;\r\n\t\t\trespsize = 0;\r\n\t\t} else if(receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61) {\t// Received an authentication request\r\n\t\t\tresp = resp5; respLen = resp5Len; order = 7;\r\n\t\t\trespdata = response5;\r\n\t\t\trespsize = sizeof(response5);\r\n\t\t} else if(receivedCmd[0] == 0xE0) {\t// Received a RATS request\r\n\t\t\tresp = resp6; respLen = resp6Len; order = 70;\r\n\t\t\trespdata = response6;\r\n\t\t\trespsize = sizeof(response6);\r\n\t\t} else {\r\n if (order == 7 && len ==8) {\r\n uint32_t nr = bytes_to_num(receivedCmd,4);\r\n uint32_t ar = bytes_to_num(receivedCmd+4,4);\r\n Dbprintf(\"Auth attempt {nr}{ar}: %08x %08x\",nr,ar);\r\n } else {\r\n // Never seen this command before\r\n Dbprintf(\"Received unknown command (len=%d):\",len);\r\n Dbhexdump(len,receivedCmd,false);\r\n }\r\n // Do not respond\r\n resp = resp1; respLen = 0; order = 0;\r\n respdata = NULL;\r\n respsize = 0;\r\n\t\t}\r\n\r\n\t\t// Count number of wakeups received after a halt\r\n\t\tif(order == 6 && lastorder == 5) { happened++; }\r\n\r\n\t\t// Count number of other messages after a halt\r\n\t\tif(order != 6 && lastorder == 5) { happened2++; }\r\n\r\n\t\t// Look at last parity bit to determine timing of answer\r\n\t\tif((Uart.parityBits & 0x01) || receivedCmd[0] == 0x52) {\r\n\t\t\t// 1236, so correction bit needed\r\n\t\t\t//i = 0;\r\n\t\t}\r\n\r\n\t\tif(cmdsRecvd > 999) {\r\n\t\t\tDbpString(\"1000 commands later...\");\r\n\t\t\tbreak;\r\n\t\t} else {\r\n\t\t\tcmdsRecvd++;\r\n\t\t}\r\n\r\n\t\tif(respLen > 0) {\r\n\t\t\tEmSendCmd14443aRaw(resp, respLen, receivedCmd[0] == 0x52);\r\n\t\t}\r\n\t\t\r\n\t\tif (tracing) {\r\n\t\t\tif (respdata != NULL) {\r\n\t\t\t\tLogTrace(respdata,respsize, 0, SwapBits(GetParity(respdata,respsize),respsize), FALSE);\r\n\t\t\t}\r\n\t\t\tif(traceLen > TRACE_SIZE) {\r\n\t\t\t\tDbpString(\"Trace full\");\r\n\t\t\t\tbreak;\r\n\t\t\t}\r\n\t\t}\r\n\r\n\t\tmemset(receivedCmd, 0x44, RECV_CMD_SIZE);\r\n }\r\n\r\n\tDbprintf(\"%x %x %x\", happened, happened2, cmdsRecvd);\r\n\tLED_A_OFF();\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// Transmit the command (to the tag) that was placed in ToSend[].\r\n//-----------------------------------------------------------------------------\r\nstatic void TransmitFor14443a(const uint8_t *cmd, int len, int *samples, int *wait)\r\n{\r\n int c;\r\n\r\n FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);\r\n\r\n\tif (wait)\r\n if(*wait < 10)\r\n *wait = 10;\r\n\r\n for(c = 0; c < *wait;) {\r\n if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r\n AT91C_BASE_SSC->SSC_THR = 0x00;\t\t// For exact timing!\r\n c++;\r\n }\r\n if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r\n volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;\r\n (void)r;\r\n }\r\n WDT_HIT();\r\n }\r\n\r\n c = 0;\r\n for(;;) {\r\n if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r\n AT91C_BASE_SSC->SSC_THR = cmd[c];\r\n c++;\r\n if(c >= len) {\r\n break;\r\n }\r\n }\r\n if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r\n volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;\r\n (void)r;\r\n }\r\n WDT_HIT();\r\n }\r\n\tif (samples) *samples = (c + *wait) << 3;\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// Prepare reader command (in bits, support short frames) to send to FPGA\r\n//-----------------------------------------------------------------------------\r\nvoid CodeIso14443aBitsAsReaderPar(const uint8_t * cmd, int bits, uint32_t dwParity)\r\n{\r\n int i, j;\r\n int last;\r\n uint8_t b;\r\n\r\n ToSendReset();\r\n\r\n // Start of Communication (Seq. Z)\r\n ToSend[++ToSendMax] = SEC_Z;\r\n last = 0;\r\n\r\n size_t bytecount = nbytes(bits);\r\n // Generate send structure for the data bits\r\n for (i = 0; i < bytecount; i++) {\r\n // Get the current byte to send\r\n b = cmd[i];\r\n size_t bitsleft = MIN((bits-(i*8)),8);\r\n\r\n for (j = 0; j < bitsleft; j++) {\r\n if (b & 1) {\r\n // Sequence X\r\n \t ToSend[++ToSendMax] = SEC_X;\r\n last = 1;\r\n } else {\r\n if (last == 0) {\r\n // Sequence Z\r\n \tToSend[++ToSendMax] = SEC_Z;\r\n } else {\r\n // Sequence Y\r\n \tToSend[++ToSendMax] = SEC_Y;\r\n last = 0;\r\n }\r\n }\r\n b >>= 1;\r\n }\r\n\r\n // Only transmit (last) parity bit if we transmitted a complete byte\r\n if (j == 8) {\r\n // Get the parity bit\r\n if ((dwParity >> i) & 0x01) {\r\n // Sequence X\r\n ToSend[++ToSendMax] = SEC_X;\r\n last = 1;\r\n } else {\r\n if (last == 0) {\r\n // Sequence Z\r\n ToSend[++ToSendMax] = SEC_Z;\r\n } else {\r\n // Sequence Y\r\n ToSend[++ToSendMax] = SEC_Y;\r\n last = 0;\r\n }\r\n }\r\n }\r\n }\r\n\r\n // End of Communication\r\n if (last == 0) {\r\n // Sequence Z\r\n\t ToSend[++ToSendMax] = SEC_Z;\r\n } else {\r\n // Sequence Y\r\n\t ToSend[++ToSendMax] = SEC_Y;\r\n last = 0;\r\n }\r\n // Sequence Y\r\n ToSend[++ToSendMax] = SEC_Y;\r\n\r\n // Just to be sure!\r\n ToSend[++ToSendMax] = SEC_Y;\r\n ToSend[++ToSendMax] = SEC_Y;\r\n ToSend[++ToSendMax] = SEC_Y;\r\n\r\n // Convert from last character reference to length\r\n ToSendMax++;\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// Prepare reader command to send to FPGA\r\n//-----------------------------------------------------------------------------\r\nvoid CodeIso14443aAsReaderPar(const uint8_t * cmd, int len, uint32_t dwParity)\r\n{\r\n CodeIso14443aBitsAsReaderPar(cmd,len*8,dwParity);\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// Wait for commands from reader\r\n// Stop when button is pressed (return 1) or field was gone (return 2)\r\n// Or return 0 when command is captured\r\n//-----------------------------------------------------------------------------\r\nstatic int EmGetCmd(uint8_t *received, int *len, int maxLen)\r\n{\r\n\t*len = 0;\r\n\r\n\tuint32_t timer = 0, vtime = 0;\r\n\tint analogCnt = 0;\r\n\tint analogAVG = 0;\r\n\r\n\t// Set FPGA mode to \"simulated ISO 14443 tag\", no modulation (listen\r\n\t// only, since we are receiving, not transmitting).\r\n\t// Signal field is off with the appropriate LED\r\n\tLED_D_OFF();\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);\r\n\r\n\t// Set ADC to read field strength\r\n\tAT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;\r\n\tAT91C_BASE_ADC->ADC_MR =\r\n\t\t\t\tADC_MODE_PRESCALE(32) |\r\n\t\t\t\tADC_MODE_STARTUP_TIME(16) |\r\n\t\t\t\tADC_MODE_SAMPLE_HOLD_TIME(8);\r\n\tAT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF);\r\n\t// start ADC\r\n\tAT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;\r\n\t\r\n\t// Now run a 'software UART' on the stream of incoming samples.\r\n\tUart.output = received;\r\n\tUart.byteCntMax = maxLen;\r\n\tUart.state = STATE_UNSYNCD;\r\n\r\n\tfor(;;) {\r\n\t\tWDT_HIT();\r\n\r\n\t\tif (BUTTON_PRESS()) return 1;\r\n\r\n\t\t// test if the field exists\r\n\t\tif (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) {\r\n\t\t\tanalogCnt++;\r\n\t\t\tanalogAVG += AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF];\r\n\t\t\tAT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;\r\n\t\t\tif (analogCnt >= 32) {\r\n\t\t\t\tif ((33000 * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) {\r\n\t\t\t\t\tvtime = GetTickCount();\r\n\t\t\t\t\tif (!timer) timer = vtime;\r\n\t\t\t\t\t// 50ms no field --> card to idle state\r\n\t\t\t\t\tif (vtime - timer > 50) return 2;\r\n\t\t\t\t} else\r\n\t\t\t\t\tif (timer) timer = 0;\r\n\t\t\t\tanalogCnt = 0;\r\n\t\t\t\tanalogAVG = 0;\r\n\t\t\t}\r\n\t\t}\r\n\t\t// transmit none\r\n\t\tif(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r\n\t\t\tAT91C_BASE_SSC->SSC_THR = 0x00;\r\n\t\t}\r\n\t\t// receive and test the miller decoding\r\n\t\tif(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r\n\t\t\tvolatile uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;\r\n\t\t\tif(MillerDecoding((b & 0xf0) >> 4)) {\r\n\t\t\t\t*len = Uart.byteCnt;\r\n\t\t\t\tif (tracing) LogTrace(received, *len, GetDeltaCountUS(), Uart.parityBits, TRUE);\r\n\t\t\t\treturn 0;\r\n\t\t\t}\r\n\t\t\tif(MillerDecoding(b & 0x0f)) {\r\n\t\t\t\t*len = Uart.byteCnt;\r\n\t\t\t\tif (tracing) LogTrace(received, *len, GetDeltaCountUS(), Uart.parityBits, TRUE);\r\n\t\t\t\treturn 0;\r\n\t\t\t}\r\n\t\t}\r\n\t}\r\n}\r\n\r\nstatic int EmSendCmd14443aRaw(uint8_t *resp, int respLen, int correctionNeeded)\r\n{\r\n\tint i, u = 0;\r\n\tuint8_t b = 0;\r\n\r\n\t// Modulate Manchester\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);\r\n\tAT91C_BASE_SSC->SSC_THR = 0x00;\r\n\tFpgaSetupSsc();\r\n\t\r\n\t// include correction bit\r\n\ti = 1;\r\n\tif((Uart.parityBits & 0x01) || correctionNeeded) {\r\n\t\t// 1236, so correction bit needed\r\n\t\ti = 0;\r\n\t}\r\n\t\r\n\t// send cycle\r\n\tfor(;;) {\r\n\t\tif(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r\n\t\t\tvolatile uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;\r\n\t\t\t(void)b;\r\n\t\t}\r\n\t\tif(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r\n\t\t\tif(i > respLen) {\r\n\t\t\t\tb = 0xff; // was 0x00\r\n\t\t\t\tu++;\r\n\t\t\t} else {\r\n\t\t\t\tb = resp[i];\r\n\t\t\t\ti++;\r\n\t\t\t}\r\n\t\t\tAT91C_BASE_SSC->SSC_THR = b;\r\n\r\n\t\t\tif(u > 4) break;\r\n\t\t}\r\n\t\tif(BUTTON_PRESS()) {\r\n\t\t\tbreak;\r\n\t\t}\r\n\t}\r\n\r\n\treturn 0;\r\n}\r\n\r\nint EmSend4bitEx(uint8_t resp, int correctionNeeded){\r\n Code4bitAnswerAsTag(resp);\r\n\tint res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);\r\n if (tracing) LogTrace(&resp, 1, GetDeltaCountUS(), GetParity(&resp, 1), FALSE);\r\n\treturn res;\r\n}\r\n\r\nint EmSend4bit(uint8_t resp){\r\n\treturn EmSend4bitEx(resp, 0);\r\n}\r\n\r\nint EmSendCmdExPar(uint8_t *resp, int respLen, int correctionNeeded, uint32_t par){\r\n CodeIso14443aAsTagPar(resp, respLen, par);\r\n\tint res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);\r\n if (tracing) LogTrace(resp, respLen, GetDeltaCountUS(), par, FALSE);\r\n\treturn res;\r\n}\r\n\r\nint EmSendCmdEx(uint8_t *resp, int respLen, int correctionNeeded){\r\n\treturn EmSendCmdExPar(resp, respLen, correctionNeeded, GetParity(resp, respLen));\r\n}\r\n\r\nint EmSendCmd(uint8_t *resp, int respLen){\r\n\treturn EmSendCmdExPar(resp, respLen, 0, GetParity(resp, respLen));\r\n}\r\n\r\nint EmSendCmdPar(uint8_t *resp, int respLen, uint32_t par){\r\n\treturn EmSendCmdExPar(resp, respLen, 0, par);\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// Wait a certain time for tag response\r\n// If a response is captured return TRUE\r\n// If it takes to long return FALSE\r\n//-----------------------------------------------------------------------------\r\nstatic int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, int maxLen, int *samples, int *elapsed) //uint8_t *buffer\r\n{\r\n\t// buffer needs to be 512 bytes\r\n\tint c;\r\n\r\n\t// Set FPGA mode to \"reader listen mode\", no modulation (listen\r\n\t// only, since we are receiving, not transmitting).\r\n\t// Signal field is on with the appropriate LED\r\n\tLED_D_ON();\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);\r\n\t\r\n\t// Now get the answer from the card\r\n\tDemod.output = receivedResponse;\r\n\tDemod.len = 0;\r\n\tDemod.state = DEMOD_UNSYNCD;\r\n\r\n\tuint8_t b;\r\n\tif (elapsed) *elapsed = 0;\r\n\r\n\tc = 0;\r\n\tfor(;;) {\r\n\t\tWDT_HIT();\r\n\r\n\t\tif(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r\n\t\t\tAT91C_BASE_SSC->SSC_THR = 0x00; // To make use of exact timing of next command from reader!!\r\n\t\t\tif (elapsed) (*elapsed)++;\r\n\t\t}\r\n\t\tif(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r\n\t\t\tif(c < iso14a_timeout) { c++; } else { return FALSE; }\r\n\t\t\tb = (uint8_t)AT91C_BASE_SSC->SSC_RHR;\r\n\t\t\tif(ManchesterDecoding((b>>4) & 0xf)) {\r\n\t\t\t\t*samples = ((c - 1) << 3) + 4;\r\n\t\t\t\treturn TRUE;\r\n\t\t\t}\r\n\t\t\tif(ManchesterDecoding(b & 0x0f)) {\r\n\t\t\t\t*samples = c << 3;\r\n\t\t\t\treturn TRUE;\r\n\t\t\t}\r\n\t\t}\r\n\t}\r\n}\r\n\r\nvoid ReaderTransmitBitsPar(uint8_t* frame, int bits, uint32_t par)\r\n{\r\n int wait = 0;\r\n int samples = 0;\r\n \r\n // This is tied to other size changes\r\n // \tuint8_t* frame_addr = ((uint8_t*)BigBuf) + 2024;\r\n CodeIso14443aBitsAsReaderPar(frame,bits,par);\r\n \r\n // Select the card\r\n TransmitFor14443a(ToSend, ToSendMax, &samples, &wait);\r\n if(trigger)\r\n \tLED_A_ON();\r\n \r\n // Store reader command in buffer\r\n if (tracing) LogTrace(frame,nbytes(bits),0,par,TRUE);\r\n}\r\n\r\nvoid ReaderTransmitPar(uint8_t* frame, int len, uint32_t par)\r\n{\r\n ReaderTransmitBitsPar(frame,len*8,par);\r\n}\r\n\r\nvoid ReaderTransmit(uint8_t* frame, int len)\r\n{\r\n // Generate parity and redirect\r\n ReaderTransmitBitsPar(frame,len*8,GetParity(frame,len));\r\n}\r\n\r\nint ReaderReceive(uint8_t* receivedAnswer)\r\n{\r\n int samples = 0;\r\n if (!GetIso14443aAnswerFromTag(receivedAnswer,160,&samples,0)) return FALSE;\r\n if (tracing) LogTrace(receivedAnswer,Demod.len,samples,Demod.parityBits,FALSE);\r\n if(samples == 0) return FALSE;\r\n return Demod.len;\r\n}\r\n\r\nint ReaderReceivePar(uint8_t* receivedAnswer, uint32_t * parptr)\r\n{\r\n int samples = 0;\r\n if (!GetIso14443aAnswerFromTag(receivedAnswer,160,&samples,0)) return FALSE;\r\n if (tracing) LogTrace(receivedAnswer,Demod.len,samples,Demod.parityBits,FALSE);\r\n\t*parptr = Demod.parityBits;\r\n if(samples == 0) return FALSE;\r\n return Demod.len;\r\n}\r\n\r\n/* performs iso14443a anticolision procedure\r\n * fills the uid pointer unless NULL\r\n * fills resp_data unless NULL */\r\nint iso14443a_select_card(byte_t* uid_ptr, iso14a_card_select_t* p_hi14a_card, uint32_t* cuid_ptr) {\r\n uint8_t wupa[] = { 0x52 }; // 0x26 - REQA 0x52 - WAKE-UP\r\n uint8_t sel_all[] = { 0x93,0x20 };\r\n uint8_t sel_uid[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };\r\n uint8_t rats[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0\r\n uint8_t* resp = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET);\t// was 3560 - tied to other size changes\r\n byte_t uid_resp[4];\r\n size_t uid_resp_len;\r\n\r\n uint8_t sak = 0x04; // cascade uid\r\n int cascade_level = 0;\r\n int len;\r\n\t \r\n // Broadcast for a card, WUPA (0x52) will force response from all cards in the field\r\n ReaderTransmitBitsPar(wupa,7,0);\r\n // Receive the ATQA\r\n if(!ReaderReceive(resp)) return 0;\r\n// Dbprintf(\"atqa: %02x %02x\",resp[0],resp[1]);\r\n\r\n if(p_hi14a_card) {\r\n memcpy(p_hi14a_card->atqa, resp, 2);\r\n p_hi14a_card->uidlen = 0;\r\n memset(p_hi14a_card->uid,0,10);\r\n }\r\n\t\r\n // clear uid\r\n if (uid_ptr) {\r\n memset(uid_ptr,0,10);\r\n }\r\n\r\n // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in\r\n // which case we need to make a cascade 2 request and select - this is a long UID\r\n // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.\r\n for(; sak & 0x04; cascade_level++) {\r\n // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)\r\n sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2;\r\n\r\n // SELECT_ALL\r\n ReaderTransmit(sel_all,sizeof(sel_all));\r\n if (!ReaderReceive(resp)) return 0;\r\n \r\n // First backup the current uid\r\n memcpy(uid_resp,resp,4);\r\n uid_resp_len = 4;\r\n // Dbprintf(\"uid: %02x %02x %02x %02x\",uid_resp[0],uid_resp[1],uid_resp[2],uid_resp[3]);\r\n \r\n\t\t// calculate crypto UID\r\n\t\tif(cuid_ptr) {\r\n *cuid_ptr = bytes_to_num(uid_resp, 4);\r\n }\r\n\r\n // Construct SELECT UID command\r\n\t\tmemcpy(sel_uid+2,resp,5);\r\n AppendCrc14443a(sel_uid,7);\r\n ReaderTransmit(sel_uid,sizeof(sel_uid));\r\n\r\n // Receive the SAK\r\n if (!ReaderReceive(resp)) return 0;\r\n sak = resp[0];\r\n\r\n // Test if more parts of the uid are comming\r\n if ((sak & 0x04) && uid_resp[0] == 0x88) {\r\n // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:\r\n // http://www.nxp.com/documents/application_note/AN10927.pdf\r\n memcpy(uid_resp, uid_resp + 1, 3);\r\n uid_resp_len = 3;\r\n }\r\n \r\n if(uid_ptr) {\r\n memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len);\r\n }\r\n \r\n if(p_hi14a_card) {\r\n memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len);\r\n p_hi14a_card->uidlen += uid_resp_len;\r\n }\r\n }\r\n\r\n if(p_hi14a_card) {\r\n p_hi14a_card->sak = sak;\r\n p_hi14a_card->ats_len = 0;\r\n }\r\n\r\n if( (sak & 0x20) == 0) {\r\n return 2; // non iso14443a compliant tag\r\n }\r\n\r\n // Request for answer to select\r\n AppendCrc14443a(rats, 2);\r\n ReaderTransmit(rats, sizeof(rats));\r\n\r\n if (!(len = ReaderReceive(resp))) return 0;\r\n\r\n if(p_hi14a_card) {\r\n memcpy(p_hi14a_card->ats, resp, sizeof(p_hi14a_card->ats));\r\n p_hi14a_card->ats_len = len;\r\n }\r\n\t\r\n // reset the PCB block number\r\n iso14_pcb_blocknum = 0;\r\n return 1;\r\n}\r\n\r\nvoid iso14443a_setup() {\r\n // Set up the synchronous serial port\r\n FpgaSetupSsc();\r\n\t// Start from off (no field generated)\r\n\t// Signal field is off with the appropriate LED\r\n\tLED_D_OFF();\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\tSpinDelay(50);\r\n\r\n\tSetAdcMuxFor(GPIO_MUXSEL_HIPKD);\r\n\r\n\t// Now give it time to spin up.\r\n\t// Signal field is on with the appropriate LED\r\n\tLED_D_ON();\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);\r\n\tSpinDelay(50);\r\n\r\n\tiso14a_timeout = 2048; //default\r\n}\r\n\r\nint iso14_apdu(uint8_t * cmd, size_t cmd_len, void * data) {\r\n\tuint8_t real_cmd[cmd_len+4];\r\n\treal_cmd[0] = 0x0a; //I-Block\r\n\t// put block number into the PCB\r\n\treal_cmd[0] |= iso14_pcb_blocknum;\r\n\treal_cmd[1] = 0x00; //CID: 0 //FIXME: allow multiple selected cards\r\n\tmemcpy(real_cmd+2, cmd, cmd_len);\r\n\tAppendCrc14443a(real_cmd,cmd_len+2);\r\n \r\n\tReaderTransmit(real_cmd, cmd_len+4);\r\n\tsize_t len = ReaderReceive(data);\r\n\tuint8_t * data_bytes = (uint8_t *) data;\r\n\tif (!len)\r\n\t\treturn 0; //DATA LINK ERROR\r\n\t// if we received an I- or R(ACK)-Block with a block number equal to the\r\n\t// current block number, toggle the current block number\r\n\telse if (len >= 4 // PCB+CID+CRC = 4 bytes\r\n\t && ((data_bytes[0] & 0xC0) == 0 // I-Block\r\n\t || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0\r\n\t && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers\r\n\t{\r\n\t\tiso14_pcb_blocknum ^= 1;\r\n\t}\r\n\r\n\treturn len;\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// Read an ISO 14443a tag. Send out commands and store answers.\r\n//\r\n//-----------------------------------------------------------------------------\r\nvoid ReaderIso14443a(UsbCommand * c)\r\n{\r\n\tiso14a_command_t param = c->arg[0];\r\n\tuint8_t * cmd = c->d.asBytes;\r\n\tsize_t len = c->arg[1];\r\n uint32_t arg0 = 0;\r\n byte_t buf[USB_CMD_DATA_SIZE];\r\n \r\n iso14a_clear_trace();\r\n iso14a_set_tracing(true);\r\n\r\n\tif(param & ISO14A_REQUEST_TRIGGER) {\r\n iso14a_set_trigger(1);\r\n }\r\n\r\n\tif(param & ISO14A_CONNECT) {\r\n\t\tiso14443a_setup();\r\n\t\targ0 = iso14443a_select_card(NULL,(iso14a_card_select_t*)buf,NULL);\r\n\t\tcmd_send(CMD_ACK,arg0,0,0,buf,sizeof(iso14a_card_select_t));\r\n// UsbSendPacket((void *)ack, sizeof(UsbCommand));\r\n\t}\r\n\r\n\tif(param & ISO14A_SET_TIMEOUT) {\r\n\t\tiso14a_timeout = c->arg[2];\r\n\t}\r\n\r\n\tif(param & ISO14A_SET_TIMEOUT) {\r\n\t\tiso14a_timeout = c->arg[2];\r\n\t}\r\n\r\n\tif(param & ISO14A_APDU) {\r\n\t\targ0 = iso14_apdu(cmd, len, buf);\r\n\t\tcmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));\r\n//\t\tUsbSendPacket((void *)ack, sizeof(UsbCommand));\r\n\t}\r\n\r\n\tif(param & ISO14A_RAW) {\r\n\t\tif(param & ISO14A_APPEND_CRC) {\r\n\t\t\tAppendCrc14443a(cmd,len);\r\n\t\t\tlen += 2;\r\n\t\t}\r\n\t\tReaderTransmit(cmd,len);\r\n\t\targ0 = ReaderReceive(buf);\r\n//\t\tUsbSendPacket((void *)ack, sizeof(UsbCommand));\r\n cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));\r\n\t}\r\n\r\n\tif(param & ISO14A_REQUEST_TRIGGER) {\r\n iso14a_set_trigger(0);\r\n }\r\n\r\n\tif(param & ISO14A_NO_DISCONNECT) {\r\n\t\treturn;\r\n }\r\n\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\tLEDsoff();\r\n}\r\n\r\n\r\n// prepare the Mifare AUTH transfer with an added necessary delay.\r\nvoid PrepareDelayedAuthTransfer(uint8_t* frame, int len, uint16_t delay)\r\n{\r\n\tCodeIso14443aBitsAsReaderPar(frame, len*8, GetParity(frame,len));\r\n\r\n\tuint8_t bitmask = 0;\r\n\tuint8_t bits_to_shift = 0;\r\n\tuint8_t bits_shifted = 0;\r\n\t\r\n\tif (delay) {\r\n\t\tfor (uint16_t i = 0; i < delay; i++) {\r\n\t\t\tbitmask |= (0x01 << i);\r\n\t\t}\r\n\t\tToSend[++ToSendMax] = 0x00;\r\n\t\tfor (uint16_t i = 0; i < ToSendMax; i++) {\r\n\t\t\tbits_to_shift = ToSend[i] & bitmask;\r\n\t\t\tToSend[i] = ToSend[i] >> delay;\r\n\t\t\tToSend[i] = ToSend[i] | (bits_shifted << (8 - delay));\r\n\t\t\tbits_shifted = bits_to_shift;\r\n\t\t}\r\n\t}\r\n}\r\n\r\n\r\n\r\n// Determine the distance between two nonces.\r\n// Assume that the difference is small, but we don't know which is first.\r\n// Therefore try in alternating directions.\r\nint32_t dist_nt(uint32_t nt1, uint32_t nt2) {\r\n\r\n\tuint16_t i;\r\n\tuint32_t nttmp1, nttmp2;\r\n\r\n\tif (nt1 == nt2) return 0;\r\n\r\n\tnttmp1 = nt1;\r\n\tnttmp2 = nt2;\r\n\t\r\n\tfor (i = 1; i < 32768; i++) {\r\n\t\tnttmp1 = prng_successor(nttmp1, 1);\r\n\t\tif (nttmp1 == nt2) return i;\r\n\t\tnttmp2 = prng_successor(nttmp2, 1);\r\n\t\t\tif (nttmp2 == nt1) return -i;\r\n\t\t}\r\n\t\r\n\treturn(-99999); // either nt1 or nt2 are invalid nonces\r\n}\r\n\r\n\r\n//-----------------------------------------------------------------------------\r\n// Recover several bits of the cypher stream. This implements (first stages of)\r\n// the algorithm described in \"The Dark Side of Security by Obscurity and\r\n// Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime\"\r\n// (article by Nicolas T. Courtois, 2009)\r\n//-----------------------------------------------------------------------------\r\nvoid ReaderMifare(bool first_try)\r\n{\r\n\t// Mifare AUTH\r\n\tuint8_t mf_auth[] = { 0x60,0x00,0xf5,0x7b };\r\n\tuint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };\r\n\tstatic uint8_t mf_nr_ar3;\r\n\r\n\tuint8_t* receivedAnswer = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET);\r\n\ttraceLen = 0;\r\n\ttracing = false;\r\n\r\n\tbyte_t nt_diff = 0;\r\n\tbyte_t par = 0;\r\n\t//byte_t par_mask = 0xff;\r\n\tstatic byte_t par_low = 0;\r\n\tbool led_on = TRUE;\r\n\tuint8_t uid[10];\r\n\tuint32_t cuid;\r\n\r\n\tuint32_t nt, previous_nt;\r\n\tstatic uint32_t nt_attacked = 0;\r\n\tbyte_t par_list[8] = {0,0,0,0,0,0,0,0};\r\n\tbyte_t ks_list[8] = {0,0,0,0,0,0,0,0};\r\n\r\n\tstatic uint32_t sync_time;\r\n\tstatic uint32_t sync_cycles;\r\n\tint catch_up_cycles = 0;\r\n\tint last_catch_up = 0;\r\n\tuint16_t consecutive_resyncs = 0;\r\n\tint isOK = 0;\r\n\r\n\r\n\r\n\tif (first_try) { \r\n\t\tStartCountMifare();\r\n\t\tmf_nr_ar3 = 0;\r\n\t\tiso14443a_setup();\r\n\t\tFpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN); // resets some FPGA internal registers\r\n\t\twhile((GetCountMifare() & 0xffff0000) != 0x10000);\t\t// wait for counter to reset and \"warm up\" \r\n\t\twhile(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME); \t\t// wait for ssp_frame to be low\r\n\t\twhile(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME)); \t// sync on rising edge of ssp_frame\r\n\t\tsync_time = GetCountMifare();\r\n\t\tsync_cycles = 65536;\t\t\t\t\t\t\t\t\t// theory: Mifare Classic's random generator repeats every 2^16 cycles (and so do the nonces).\r\n\t\tnt_attacked = 0;\r\n\t\tnt = 0;\r\n\t\tpar = 0;\r\n\t}\r\n\telse {\r\n\t\t// we were unsuccessful on a previous call. Try another READER nonce (first 3 parity bits remain the same)\r\n\t\t// nt_attacked = prng_successor(nt_attacked, 1);\r\n\t\tmf_nr_ar3++;\r\n\t\tmf_nr_ar[3] = mf_nr_ar3;\r\n\t\tpar = par_low;\r\n\t}\r\n\r\n\tLED_A_ON();\r\n\tLED_B_OFF();\r\n\tLED_C_OFF();\r\n\t\r\n \r\n\tfor(uint16_t i = 0; TRUE; i++) {\r\n\t\t\r\n\t\tWDT_HIT();\r\n\r\n\t\t// Test if the action was cancelled\r\n\t\tif(BUTTON_PRESS()) {\r\n\t\t\tbreak;\r\n\t\t}\r\n\t\t\r\n\t\tLED_C_ON();\r\n\r\n\t\tif(!iso14443a_select_card(uid, NULL, &cuid)) {\r\n\t\t\tcontinue;\r\n\t\t}\r\n\r\n\t\t//keep the card active\r\n\t\tFpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);\r\n\r\n\t\tPrepareDelayedAuthTransfer(mf_auth, sizeof(mf_auth), (sync_cycles + catch_up_cycles) & 0x00000007);\r\n\r\n\t\tsync_time = sync_time + ((sync_cycles + catch_up_cycles) & 0xfffffff8);\r\n\t\tcatch_up_cycles = 0;\r\n\r\n\t\t// if we missed the sync time already, advance to the next nonce repeat\r\n\t\twhile(GetCountMifare() > sync_time) {\r\n\t\t\tsync_time = sync_time + (sync_cycles & 0xfffffff8);\r\n\t\t}\r\n\r\n\t\t// now sync. After syncing, the following Classic Auth will return the same tag nonce (mostly)\r\n\t\twhile(GetCountMifare() < sync_time);\r\n\t\t\r\n\t\t// Transmit MIFARE_CLASSIC_AUTH\r\n\t\tint samples = 0;\r\n\t\tint wait = 0;\r\n\t\tTransmitFor14443a(ToSend, ToSendMax, &samples, &wait);\r\n\r\n\t\t// Receive the (4 Byte) \"random\" nonce\r\n\t\tif (!ReaderReceive(receivedAnswer)) {\r\n\t\t\tcontinue;\r\n\t\t }\r\n\r\n \r\n\t\tprevious_nt = nt;\r\n\t\tnt = bytes_to_num(receivedAnswer, 4);\r\n\r\n\t\t// Transmit reader nonce with fake par\r\n\t\tReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par);\r\n\r\n\t\tif (first_try && previous_nt && !nt_attacked) { // we didn't calibrate our clock yet\r\n\t\t\tint nt_distance = dist_nt(previous_nt, nt);\r\n\t\t\tif (nt_distance == 0) {\r\n\t\t\t\tnt_attacked = nt;\r\n\t\t\t}\r\n\t\t\telse {\r\n\t\t\t\tif (nt_distance == -99999) { // invalid nonce received, try again\r\n\t\t\t\t\tcontinue;\r\n\t\t\t\t}\r\n\t\t\t\tsync_cycles = (sync_cycles - nt_distance);\r\n//\t\t\t\tDbprintf(\"calibrating in cycle %d. nt_distance=%d, Sync_cycles: %d\\n\", i, nt_distance, sync_cycles);\r\n\t\t\t\tcontinue;\r\n\t\t\t}\r\n\t\t}\r\n\r\n\t\tif ((nt != nt_attacked) && nt_attacked) { \t// we somehow lost sync. Try to catch up again...\r\n\t\t\tcatch_up_cycles = -dist_nt(nt_attacked, nt);\r\n\t\t\tif (catch_up_cycles == 99999) {\t\t\t// invalid nonce received. Don't resync on that one.\r\n\t\t\t\tcatch_up_cycles = 0;\r\n\t\t\t\tcontinue;\r\n\t\t\t}\r\n\t\t\tif (catch_up_cycles == last_catch_up) {\r\n\t\t\t\tconsecutive_resyncs++;\r\n\t\t\t}\r\n\t\t\telse {\r\n\t\t\t\tlast_catch_up = catch_up_cycles;\r\n\t\t\t consecutive_resyncs = 0;\r\n\t\t\t}\r\n\t\t\tif (consecutive_resyncs < 3) {\r\n\t\t\t\tDbprintf(\"Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\\n\", i, -catch_up_cycles, consecutive_resyncs);\r\n\t\t\t}\r\n\t\t\telse {\t\r\n\t\t\t\tsync_cycles = sync_cycles + catch_up_cycles;\r\n\t\t\t\tDbprintf(\"Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\\n\", i, -catch_up_cycles, sync_cycles);\r\n\t\t\t}\r\n\t\t\tcontinue;\r\n\t\t}\r\n \r\n\t\tconsecutive_resyncs = 0;\r\n\t\t\r\n\t\t// Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding\r\n\t\tif (ReaderReceive(receivedAnswer))\r\n\t\t{\r\n\t\t\tcatch_up_cycles = 8; \t// the PRNG doesn't run during data transfers. 4 Bit = 8 cycles\r\n\t\r\n\t\t\tif (nt_diff == 0)\r\n\t\t\t{\r\n\t\t\t\tpar_low = par & 0x07; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change\r\n\t\t\t}\r\n\r\n\t\t\tled_on = !led_on;\r\n\t\t\tif(led_on) LED_B_ON(); else LED_B_OFF();\r\n\r\n\t\t\tpar_list[nt_diff] = par;\r\n\t\t\tks_list[nt_diff] = receivedAnswer[0] ^ 0x05;\r\n\r\n\t\t\t// Test if the information is complete\r\n\t\t\tif (nt_diff == 0x07) {\r\n\t\t\t\tisOK = 1;\r\n\t\t\t\tbreak;\r\n\t\t\t}\r\n\r\n\t\t\tnt_diff = (nt_diff + 1) & 0x07;\r\n\t\t\tmf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5);\r\n\t\t\tpar = par_low;\r\n\t\t} else {\r\n\t\t\tif (nt_diff == 0 && first_try)\r\n\t\t\t{\r\n\t\t\t\tpar++;\r\n\t\t\t} else {\r\n\t\t\t\tpar = (((par >> 3) + 1) << 3) | par_low;\r\n\t\t\t}\r\n\t\t}\r\n\t}\r\n\r\n\tLogTrace((const uint8_t *)&nt, 4, 0, GetParity((const uint8_t *)&nt, 4), TRUE);\r\n\tLogTrace(par_list, 8, 0, GetParity(par_list, 8), TRUE);\r\n\tLogTrace(ks_list, 8, 0, GetParity(ks_list, 8), TRUE);\r\n\r\n\tmf_nr_ar[3] &= 0x1F;\r\n\t\r\n\tbyte_t buf[28];\r\n\tmemcpy(buf + 0, uid, 4);\r\n\tnum_to_bytes(nt, 4, buf + 4);\r\n\tmemcpy(buf + 8, par_list, 8);\r\n\tmemcpy(buf + 16, ks_list, 8);\r\n\tmemcpy(buf + 24, mf_nr_ar, 4);\r\n\t\t\r\n\tcmd_send(CMD_ACK,isOK,0,0,buf,28);\r\n\r\n\t// Thats it...\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\tLEDsoff();\r\n\ttracing = TRUE;\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// MIFARE 1K simulate. \r\n// \r\n//-----------------------------------------------------------------------------\r\nvoid Mifare1ksim(uint8_t arg0, uint8_t arg1, uint8_t arg2, uint8_t *datain)\r\n{\r\n\tint cardSTATE = MFEMUL_NOFIELD;\r\n\tint _7BUID = 0;\r\n\tint vHf = 0;\t// in mV\r\n\t//int nextCycleTimeout = 0;\r\n\tint res;\r\n//\tuint32_t timer = 0;\r\n\tuint32_t selTimer = 0;\r\n\tuint32_t authTimer = 0;\r\n\tuint32_t par = 0;\r\n\tint len = 0;\r\n\tuint8_t cardWRBL = 0;\r\n\tuint8_t cardAUTHSC = 0;\r\n\tuint8_t cardAUTHKEY = 0xff; // no authentication\r\n\t//uint32_t cardRn = 0;\r\n\tuint32_t cardRr = 0;\r\n\tuint32_t cuid = 0;\r\n\t//uint32_t rn_enc = 0;\r\n\tuint32_t ans = 0;\r\n\tuint32_t cardINTREG = 0;\r\n\tuint8_t cardINTBLOCK = 0;\r\n\tstruct Crypto1State mpcs = {0, 0};\r\n\tstruct Crypto1State *pcs;\r\n\tpcs = &mpcs;\r\n\t\r\n\tuint8_t* receivedCmd = eml_get_bigbufptr_recbuf();\r\n\tuint8_t *response = eml_get_bigbufptr_sendbuf();\r\n\t\r\n\tstatic uint8_t rATQA[] = {0x04, 0x00}; // Mifare classic 1k 4BUID\r\n\r\n\tstatic uint8_t rUIDBCC1[] = {0xde, 0xad, 0xbe, 0xaf, 0x62}; \r\n\tstatic uint8_t rUIDBCC2[] = {0xde, 0xad, 0xbe, 0xaf, 0x62}; // !!!\r\n\t\t\r\n\tstatic uint8_t rSAK[] = {0x08, 0xb6, 0xdd};\r\n\tstatic uint8_t rSAK1[] = {0x04, 0xda, 0x17};\r\n\r\n\tstatic uint8_t rAUTH_NT[] = {0x01, 0x02, 0x03, 0x04};\r\n//\tstatic uint8_t rAUTH_NT[] = {0x1a, 0xac, 0xff, 0x4f};\r\n\tstatic uint8_t rAUTH_AT[] = {0x00, 0x00, 0x00, 0x00};\r\n\r\n\t// clear trace\r\n\ttraceLen = 0;\r\n\ttracing = true;\r\n\r\n // Authenticate response - nonce\r\n\tuint32_t nonce = bytes_to_num(rAUTH_NT, 4);\r\n\t\r\n\t// get UID from emul memory\r\n\temlGetMemBt(receivedCmd, 7, 1);\r\n\t_7BUID = !(receivedCmd[0] == 0x00);\r\n\tif (!_7BUID) { // ---------- 4BUID\r\n\t\trATQA[0] = 0x04;\r\n\r\n\t\temlGetMemBt(rUIDBCC1, 0, 4);\r\n\t\trUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];\r\n\t} else { // ---------- 7BUID\r\n\t\trATQA[0] = 0x44;\r\n\r\n\t\trUIDBCC1[0] = 0x88;\r\n\t\temlGetMemBt(&rUIDBCC1[1], 0, 3);\r\n\t\trUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];\r\n\t\temlGetMemBt(rUIDBCC2, 3, 4);\r\n\t\trUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];\r\n\t}\r\n\r\n// --------------------------------------\ttest area\r\n\r\n// --------------------------------------\tEND test area\r\n\t// start mkseconds counter\r\n\tStartCountUS();\r\n\r\n\t// We need to listen to the high-frequency, peak-detected path.\r\n\tSetAdcMuxFor(GPIO_MUXSEL_HIPKD);\r\n\tFpgaSetupSsc();\r\n\r\n FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);\r\n\tSpinDelay(200);\r\n\r\n\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Started. 7buid=%d\", _7BUID);\r\n\t// calibrate mkseconds counter\r\n\tGetDeltaCountUS();\r\n\twhile (true) {\r\n\t\tWDT_HIT();\r\n\r\n\t\tif(BUTTON_PRESS()) {\r\n\t\t\tbreak;\r\n\t\t}\r\n\r\n\t\t// find reader field\r\n\t\t// Vref = 3300mV, and an 10:1 voltage divider on the input\r\n\t\t// can measure voltages up to 33000 mV\r\n\t\tif (cardSTATE == MFEMUL_NOFIELD) {\r\n\t\t\tvHf = (33000 * AvgAdc(ADC_CHAN_HF)) >> 10;\r\n\t\t\tif (vHf > MF_MINFIELDV) {\r\n\t\t\t\tcardSTATE_TO_IDLE();\r\n\t\t\t\tLED_A_ON();\r\n\t\t\t}\r\n\t\t} \r\n\r\n\t\tif (cardSTATE != MFEMUL_NOFIELD) {\r\n\t\t\tres = EmGetCmd(receivedCmd, &len, RECV_CMD_SIZE); // (+ nextCycleTimeout)\r\n\t\t\tif (res == 2) {\r\n\t\t\t\tcardSTATE = MFEMUL_NOFIELD;\r\n\t\t\t\tLEDsoff();\r\n\t\t\t\tcontinue;\r\n\t\t\t}\r\n\t\t\tif(res) break;\r\n\t\t}\r\n\t\t\r\n\t\t//nextCycleTimeout = 0;\r\n\t\t\r\n//\t\tif (len) Dbprintf(\"len:%d cmd: %02x %02x %02x %02x\", len, receivedCmd[0], receivedCmd[1], receivedCmd[2], receivedCmd[3]);\r\n\r\n\t\tif (len != 4 && cardSTATE != MFEMUL_NOFIELD) { // len != 4 <---- speed up the code 4 authentication\r\n\t\t\t// REQ or WUP request in ANY state and WUP in HALTED state\r\n\t\t\tif (len == 1 && ((receivedCmd[0] == 0x26 && cardSTATE != MFEMUL_HALTED) || receivedCmd[0] == 0x52)) {\r\n\t\t\t\tselTimer = GetTickCount();\r\n\t\t\t\tEmSendCmdEx(rATQA, sizeof(rATQA), (receivedCmd[0] == 0x52));\r\n\t\t\t\tcardSTATE = MFEMUL_SELECT1;\r\n\r\n\t\t\t\t// init crypto block\r\n\t\t\t\tLED_B_OFF();\r\n\t\t\t\tLED_C_OFF();\r\n\t\t\t\tcrypto1_destroy(pcs);\r\n\t\t\t\tcardAUTHKEY = 0xff;\r\n\t\t\t}\r\n\t\t}\r\n\t\t\r\n\t\tswitch (cardSTATE) {\r\n\t\t\tcase MFEMUL_NOFIELD:{\r\n\t\t\t\tbreak;\r\n\t\t\t}\r\n\t\t\tcase MFEMUL_HALTED:{\r\n\t\t\t\tbreak;\r\n\t\t\t}\r\n\t\t\tcase MFEMUL_IDLE:{\r\n\t\t\t\tbreak;\r\n\t\t\t}\r\n\t\t\tcase MFEMUL_SELECT1:{\r\n\t\t\t\t// select all\r\n\t\t\t\tif (len == 2 && (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x20)) {\r\n\t\t\t\t\tEmSendCmd(rUIDBCC1, sizeof(rUIDBCC1));\r\n\t\t\t\t\tbreak;\r\n\t\t\t\t}\r\n\r\n\t\t\t\t// select card\r\n\t\t\t\tif (len == 9 && \r\n\t\t\t\t\t\t(receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC1, 4) == 0)) {\r\n\t\t\t\t\tif (!_7BUID) \r\n\t\t\t\t\t\tEmSendCmd(rSAK, sizeof(rSAK));\r\n\t\t\t\t\telse\r\n\t\t\t\t\t\tEmSendCmd(rSAK1, sizeof(rSAK1));\r\n\r\n\t\t\t\t\tcuid = bytes_to_num(rUIDBCC1, 4);\r\n\t\t\t\t\tif (!_7BUID) {\r\n\t\t\t\t\t\tcardSTATE = MFEMUL_WORK;\r\n\t\t\t\t\t\tLED_B_ON();\r\n\t\t\t\t\t\tif (MF_DBGLEVEL >= 4)\tDbprintf(\"--> WORK. anticol1 time: %d\", GetTickCount() - selTimer);\r\n\t\t\t\t\t\tbreak;\r\n\t\t\t\t\t} else {\r\n\t\t\t\t\t\tcardSTATE = MFEMUL_SELECT2;\r\n\t\t\t\t\t\tbreak;\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\t\r\n\t\t\t\tbreak;\r\n\t\t\t}\r\n\t\t\tcase MFEMUL_SELECT2:{\r\n\t\t\t\tif (!len) break;\r\n\t\t\t\r\n\t\t\t\tif (len == 2 && (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x20)) {\r\n\t\t\t\t\tEmSendCmd(rUIDBCC2, sizeof(rUIDBCC2));\r\n\t\t\t\t\tbreak;\r\n\t\t\t\t}\r\n\r\n\t\t\t\t// select 2 card\r\n\t\t\t\tif (len == 9 && \r\n\t\t\t\t\t\t(receivedCmd[0] == 0x95 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC2, 4) == 0)) {\r\n\t\t\t\t\tEmSendCmd(rSAK, sizeof(rSAK));\r\n\r\n\t\t\t\t\tcuid = bytes_to_num(rUIDBCC2, 4);\r\n\t\t\t\t\tcardSTATE = MFEMUL_WORK;\r\n\t\t\t\t\tLED_B_ON();\r\n\t\t\t\t\tif (MF_DBGLEVEL >= 4)\tDbprintf(\"--> WORK. anticol2 time: %d\", GetTickCount() - selTimer);\r\n\t\t\t\t\tbreak;\r\n\t\t\t\t}\r\n\t\t\t\t\r\n\t\t\t\t// i guess there is a command). go into the work state.\r\n\t\t\t\tif (len != 4) break;\r\n\t\t\t\tcardSTATE = MFEMUL_WORK;\r\n\t\t\t\tgoto lbWORK;\r\n\t\t\t}\r\n\t\t\tcase MFEMUL_AUTH1:{\r\n\t\t\t\tif (len == 8) {\r\n\t\t\t\t\t// --- crypto\r\n\t\t\t\t\t//rn_enc = bytes_to_num(receivedCmd, 4);\r\n\t\t\t\t\t//cardRn = rn_enc ^ crypto1_word(pcs, rn_enc , 1);\r\n\t\t\t\t\tcardRr = bytes_to_num(&receivedCmd[4], 4) ^ crypto1_word(pcs, 0, 0);\r\n\t\t\t\t\t// test if auth OK\r\n\t\t\t\t\tif (cardRr != prng_successor(nonce, 64)){\r\n\t\t\t\t\t\tif (MF_DBGLEVEL >= 4)\tDbprintf(\"AUTH FAILED. cardRr=%08x, succ=%08x\", cardRr, prng_successor(nonce, 64));\r\n\t\t\t\t\t\tcardSTATE_TO_IDLE();\r\n\t\t\t\t\t\tbreak;\r\n\t\t\t\t\t}\r\n\t\t\t\t\tans = prng_successor(nonce, 96) ^ crypto1_word(pcs, 0, 0);\r\n\t\t\t\t\tnum_to_bytes(ans, 4, rAUTH_AT);\r\n\t\t\t\t\t// --- crypto\r\n\t\t\t\t\tEmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));\r\n\t\t\t\t\tcardSTATE = MFEMUL_AUTH2;\r\n\t\t\t\t} else {\r\n\t\t\t\t\tcardSTATE_TO_IDLE();\r\n\t\t\t\t}\r\n\t\t\t\tif (cardSTATE != MFEMUL_AUTH2) break;\r\n\t\t\t}\r\n\t\t\tcase MFEMUL_AUTH2:{\r\n\t\t\t\tLED_C_ON();\r\n\t\t\t\tcardSTATE = MFEMUL_WORK;\r\n\t\t\t\tif (MF_DBGLEVEL >= 4)\tDbprintf(\"AUTH COMPLETED. sec=%d, key=%d time=%d\", cardAUTHSC, cardAUTHKEY, GetTickCount() - authTimer);\r\n\t\t\t\tbreak;\r\n\t\t\t}\r\n\t\t\tcase MFEMUL_WORK:{\r\nlbWORK:\tif (len == 0) break;\r\n\t\t\t\t\r\n\t\t\t\tif (cardAUTHKEY == 0xff) {\r\n\t\t\t\t\t// first authentication\r\n\t\t\t\t\tif (len == 4 && (receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61)) {\r\n\t\t\t\t\t\tauthTimer = GetTickCount();\r\n\r\n\t\t\t\t\t\tcardAUTHSC = receivedCmd[1] / 4; // received block num\r\n\t\t\t\t\t\tcardAUTHKEY = receivedCmd[0] - 0x60;\r\n\r\n\t\t\t\t\t\t// --- crypto\r\n\t\t\t\t\t\tcrypto1_create(pcs, emlGetKey(cardAUTHSC, cardAUTHKEY));\r\n\t\t\t\t\t\tans = nonce ^ crypto1_word(pcs, cuid ^ nonce, 0); \r\n\t\t\t\t\t\tnum_to_bytes(nonce, 4, rAUTH_AT);\r\n\t\t\t\t\t\tEmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));\r\n\t\t\t\t\t\t// --- crypto\r\n\t\t\t\t\t\t\r\n// last working revision \r\n//\t\t\t\t\t\tEmSendCmd14443aRaw(resp1, resp1Len, 0);\r\n//\t\t\t\t\t\tLogTrace(NULL, 0, GetDeltaCountUS(), 0, true);\r\n\r\n\t\t\t\t\t\tcardSTATE = MFEMUL_AUTH1;\r\n\t\t\t\t\t\t//nextCycleTimeout = 10;\r\n\t\t\t\t\t\tbreak;\r\n\t\t\t\t\t}\r\n\t\t\t\t} else {\r\n\t\t\t\t\t// decrypt seqence\r\n\t\t\t\t\tmf_crypto1_decrypt(pcs, receivedCmd, len);\r\n\t\t\t\t\t\r\n\t\t\t\t\t// nested authentication\r\n\t\t\t\t\tif (len == 4 && (receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61)) {\r\n\t\t\t\t\t\tauthTimer = GetTickCount();\r\n\r\n\t\t\t\t\t\tcardAUTHSC = receivedCmd[1] / 4; // received block num\r\n\t\t\t\t\t\tcardAUTHKEY = receivedCmd[0] - 0x60;\r\n\r\n\t\t\t\t\t\t// --- crypto\r\n\t\t\t\t\t\tcrypto1_create(pcs, emlGetKey(cardAUTHSC, cardAUTHKEY));\r\n\t\t\t\t\t\tans = nonce ^ crypto1_word(pcs, cuid ^ nonce, 0); \r\n\t\t\t\t\t\tnum_to_bytes(ans, 4, rAUTH_AT);\r\n\t\t\t\t\t\tEmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));\r\n\t\t\t\t\t\t// --- crypto\r\n\r\n\t\t\t\t\t\tcardSTATE = MFEMUL_AUTH1;\r\n\t\t\t\t\t\t//nextCycleTimeout = 10;\r\n\t\t\t\t\t\tbreak;\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\t\r\n\t\t\t\t// rule 13 of 7.5.3. in ISO 14443-4. chaining shall be continued\r\n\t\t\t\t// BUT... ACK --> NACK\r\n\t\t\t\tif (len == 1 && receivedCmd[0] == CARD_ACK) {\r\n\t\t\t\t\tEmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));\r\n\t\t\t\t\tbreak;\r\n\t\t\t\t}\r\n\t\t\t\t\r\n\t\t\t\t// rule 12 of 7.5.3. in ISO 14443-4. R(NAK) --> R(ACK)\r\n\t\t\t\tif (len == 1 && receivedCmd[0] == CARD_NACK_NA) {\r\n\t\t\t\t\tEmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));\r\n\t\t\t\t\tbreak;\r\n\t\t\t\t}\r\n\t\t\t\t\r\n\t\t\t\t// read block\r\n\t\t\t\tif (len == 4 && receivedCmd[0] == 0x30) {\r\n\t\t\t\t\tif (receivedCmd[1] >= 16 * 4 || receivedCmd[1] / 4 != cardAUTHSC) {\r\n\t\t\t\t\t\tEmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));\r\n\t\t\t\t\t\tbreak;\r\n\t\t\t\t\t}\r\n\t\t\t\t\temlGetMem(response, receivedCmd[1], 1);\r\n\t\t\t\t\tAppendCrc14443a(response, 16);\r\n\t\t\t\t\tmf_crypto1_encrypt(pcs, response, 18, &par);\r\n\t\t\t\t\tEmSendCmdPar(response, 18, par);\r\n\t\t\t\t\tbreak;\r\n\t\t\t\t}\r\n\t\t\t\t\r\n\t\t\t\t// write block\r\n\t\t\t\tif (len == 4 && receivedCmd[0] == 0xA0) {\r\n\t\t\t\t\tif (receivedCmd[1] >= 16 * 4 || receivedCmd[1] / 4 != cardAUTHSC) {\r\n\t\t\t\t\t\tEmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));\r\n\t\t\t\t\t\tbreak;\r\n\t\t\t\t\t}\r\n\t\t\t\t\tEmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));\r\n\t\t\t\t\t//nextCycleTimeout = 50;\r\n\t\t\t\t\tcardSTATE = MFEMUL_WRITEBL2;\r\n\t\t\t\t\tcardWRBL = receivedCmd[1];\r\n\t\t\t\t\tbreak;\r\n\t\t\t\t}\r\n\t\t\t\r\n\t\t\t\t// works with cardINTREG\r\n\t\t\t\t\r\n\t\t\t\t// increment, decrement, restore\r\n\t\t\t\tif (len == 4 && (receivedCmd[0] == 0xC0 || receivedCmd[0] == 0xC1 || receivedCmd[0] == 0xC2)) {\r\n\t\t\t\t\tif (receivedCmd[1] >= 16 * 4 || \r\n\t\t\t\t\t\t\treceivedCmd[1] / 4 != cardAUTHSC || \r\n\t\t\t\t\t\t\temlCheckValBl(receivedCmd[1])) {\r\n\t\t\t\t\t\tEmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));\r\n\t\t\t\t\t\tbreak;\r\n\t\t\t\t\t}\r\n\t\t\t\t\tEmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));\r\n\t\t\t\t\tif (receivedCmd[0] == 0xC1)\r\n\t\t\t\t\t\tcardSTATE = MFEMUL_INTREG_INC;\r\n\t\t\t\t\tif (receivedCmd[0] == 0xC0)\r\n\t\t\t\t\t\tcardSTATE = MFEMUL_INTREG_DEC;\r\n\t\t\t\t\tif (receivedCmd[0] == 0xC2)\r\n\t\t\t\t\t\tcardSTATE = MFEMUL_INTREG_REST;\r\n\t\t\t\t\tcardWRBL = receivedCmd[1];\r\n\t\t\t\t\t\r\n\t\t\t\t\tbreak;\r\n\t\t\t\t}\r\n\t\t\t\t\r\n\r\n\t\t\t\t// transfer\r\n\t\t\t\tif (len == 4 && receivedCmd[0] == 0xB0) {\r\n\t\t\t\t\tif (receivedCmd[1] >= 16 * 4 || receivedCmd[1] / 4 != cardAUTHSC) {\r\n\t\t\t\t\t\tEmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));\r\n\t\t\t\t\t\tbreak;\r\n\t\t\t\t\t}\r\n\t\t\t\t\t\r\n\t\t\t\t\tif (emlSetValBl(cardINTREG, cardINTBLOCK, receivedCmd[1]))\r\n\t\t\t\t\t\tEmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));\r\n\t\t\t\t\telse\r\n\t\t\t\t\t\tEmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));\r\n\t\t\t\t\t\t\r\n\t\t\t\t\tbreak;\r\n\t\t\t\t}\r\n\r\n\t\t\t\t// halt\r\n\t\t\t\tif (len == 4 && (receivedCmd[0] == 0x50 && receivedCmd[1] == 0x00)) {\r\n\t\t\t\t\tLED_B_OFF();\r\n\t\t\t\t\tLED_C_OFF();\r\n\t\t\t\t\tcardSTATE = MFEMUL_HALTED;\r\n\t\t\t\t\tif (MF_DBGLEVEL >= 4)\tDbprintf(\"--> HALTED. Selected time: %d ms\", GetTickCount() - selTimer);\r\n\t\t\t\t\tbreak;\r\n\t\t\t\t}\r\n\t\t\t\t\r\n\t\t\t\t// command not allowed\r\n\t\t\t\tif (len == 4) {\r\n\t\t\t\t\tEmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));\r\n\t\t\t\t\tbreak;\r\n\t\t\t\t}\r\n\r\n\t\t\t\t// case break\r\n\t\t\t\tbreak;\r\n\t\t\t}\r\n\t\t\tcase MFEMUL_WRITEBL2:{\r\n\t\t\t\tif (len == 18){\r\n\t\t\t\t\tmf_crypto1_decrypt(pcs, receivedCmd, len);\r\n\t\t\t\t\temlSetMem(receivedCmd, cardWRBL, 1);\r\n\t\t\t\t\tEmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));\r\n\t\t\t\t\tcardSTATE = MFEMUL_WORK;\r\n\t\t\t\t\tbreak;\r\n\t\t\t\t} else {\r\n\t\t\t\t\tcardSTATE_TO_IDLE();\r\n\t\t\t\t\tbreak;\r\n\t\t\t\t}\r\n\t\t\t\tbreak;\r\n\t\t\t}\r\n\t\t\t\r\n\t\t\tcase MFEMUL_INTREG_INC:{\r\n\t\t\t\tmf_crypto1_decrypt(pcs, receivedCmd, len);\r\n\t\t\t\tmemcpy(&ans, receivedCmd, 4);\r\n\t\t\t\tif (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {\r\n\t\t\t\t\tEmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));\r\n\t\t\t\t\tcardSTATE_TO_IDLE();\r\n\t\t\t\t\tbreak;\r\n\t\t\t\t}\r\n\t\t\t\tcardINTREG = cardINTREG + ans;\r\n\t\t\t\tcardSTATE = MFEMUL_WORK;\r\n\t\t\t\tbreak;\r\n\t\t\t}\r\n\t\t\tcase MFEMUL_INTREG_DEC:{\r\n\t\t\t\tmf_crypto1_decrypt(pcs, receivedCmd, len);\r\n\t\t\t\tmemcpy(&ans, receivedCmd, 4);\r\n\t\t\t\tif (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {\r\n\t\t\t\t\tEmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));\r\n\t\t\t\t\tcardSTATE_TO_IDLE();\r\n\t\t\t\t\tbreak;\r\n\t\t\t\t}\r\n\t\t\t\tcardINTREG = cardINTREG - ans;\r\n\t\t\t\tcardSTATE = MFEMUL_WORK;\r\n\t\t\t\tbreak;\r\n\t\t\t}\r\n\t\t\tcase MFEMUL_INTREG_REST:{\r\n\t\t\t\tmf_crypto1_decrypt(pcs, receivedCmd, len);\r\n\t\t\t\tmemcpy(&ans, receivedCmd, 4);\r\n\t\t\t\tif (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {\r\n\t\t\t\t\tEmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));\r\n\t\t\t\t\tcardSTATE_TO_IDLE();\r\n\t\t\t\t\tbreak;\r\n\t\t\t\t}\r\n\t\t\t\tcardSTATE = MFEMUL_WORK;\r\n\t\t\t\tbreak;\r\n\t\t\t}\r\n\t\t}\r\n\t}\r\n\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\tLEDsoff();\r\n\r\n\t// add trace trailer\r\n\tmemset(rAUTH_NT, 0x44, 4);\r\n\tLogTrace(rAUTH_NT, 4, 0, 0, TRUE);\r\n\r\n\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Emulator stopped. Tracing: %d trace length: %d \",\ttracing, traceLen);\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// MIFARE sniffer. \r\n// \r\n//-----------------------------------------------------------------------------\r\nvoid RAMFUNC SniffMifare(uint8_t param) {\r\n\t// param:\r\n\t// bit 0 - trigger from first card answer\r\n\t// bit 1 - trigger from first reader 7-bit request\r\n\r\n\t// C(red) A(yellow) B(green)\r\n\tLEDsoff();\r\n\t// init trace buffer\r\n iso14a_clear_trace();\r\n\r\n\t// The command (reader -> tag) that we're receiving.\r\n\t// The length of a received command will in most cases be no more than 18 bytes.\r\n\t// So 32 should be enough!\r\n\tuint8_t *receivedCmd = (((uint8_t *)BigBuf) + RECV_CMD_OFFSET);\r\n\t// The response (tag -> reader) that we're receiving.\r\n\tuint8_t *receivedResponse = (((uint8_t *)BigBuf) + RECV_RES_OFFSET);\r\n\r\n\t// As we receive stuff, we copy it from receivedCmd or receivedResponse\r\n\t// into trace, along with its length and other annotations.\r\n\t//uint8_t *trace = (uint8_t *)BigBuf;\r\n\t\r\n\t// The DMA buffer, used to stream samples from the FPGA\r\n\tint8_t *dmaBuf = ((int8_t *)BigBuf) + DMA_BUFFER_OFFSET;\r\n\tint8_t *data = dmaBuf;\r\n\tint maxDataLen = 0;\r\n\tint dataLen = 0;\r\n\r\n\t// Set up the demodulator for tag -> reader responses.\r\n\tDemod.output = receivedResponse;\r\n\tDemod.len = 0;\r\n\tDemod.state = DEMOD_UNSYNCD;\r\n\r\n\t// Set up the demodulator for the reader -> tag commands\r\n\tmemset(&Uart, 0, sizeof(Uart));\r\n\tUart.output = receivedCmd;\r\n\tUart.byteCntMax = 32; // was 100 (greg)//////////////////\r\n\tUart.state = STATE_UNSYNCD;\r\n\r\n\t// Setup for the DMA.\r\n\tFpgaSetupSsc();\r\n\tFpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);\r\n\r\n\t// And put the FPGA in the appropriate mode\r\n\t// Signal field is off with the appropriate LED\r\n\tLED_D_OFF();\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_SNIFFER);\r\n\tSetAdcMuxFor(GPIO_MUXSEL_HIPKD);\r\n\t\r\n\t// init sniffer\r\n\tMfSniffInit();\r\n\tint sniffCounter = 0;\r\n\r\n\t// And now we loop, receiving samples.\r\n\twhile(true) {\r\n\t\tif(BUTTON_PRESS()) {\r\n\t\t\tDbpString(\"cancelled by button\");\r\n\t\t\tgoto done;\r\n\t\t}\r\n\r\n\t\tLED_A_ON();\r\n\t\tWDT_HIT();\r\n\t\t\r\n\t\tif (++sniffCounter > 65) {\r\n\t\t\tif (MfSniffSend(2000)) {\r\n\t\t\t\tFpgaEnableSscDma();\r\n\t\t\t}\r\n\t\t\tsniffCounter = 0;\r\n\t\t}\r\n\r\n\t\tint register readBufDataP = data - dmaBuf;\r\n\t\tint register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR;\r\n\t\tif (readBufDataP <= dmaBufDataP){\r\n\t\t\tdataLen = dmaBufDataP - readBufDataP;\r\n\t\t} else {\r\n\t\t\tdataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP + 1;\r\n\t\t}\r\n\t\t// test for length of buffer\r\n\t\tif(dataLen > maxDataLen) {\r\n\t\t\tmaxDataLen = dataLen;\r\n\t\t\tif(dataLen > 400) {\r\n\t\t\t\tDbprintf(\"blew circular buffer! dataLen=0x%x\", dataLen);\r\n\t\t\t\tgoto done;\r\n\t\t\t}\r\n\t\t}\r\n\t\tif(dataLen < 1) continue;\r\n\r\n\t\t// primary buffer was stopped( <-- we lost data!\r\n\t\tif (!AT91C_BASE_PDC_SSC->PDC_RCR) {\r\n\t\t\tAT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;\r\n\t\t\tAT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;\r\n\t\t\tDbprintf(\"RxEmpty ERROR!!! data length:%d\", dataLen); // temporary\r\n\t\t}\r\n\t\t// secondary buffer sets as primary, secondary buffer was stopped\r\n\t\tif (!AT91C_BASE_PDC_SSC->PDC_RNCR) {\r\n\t\t\tAT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;\r\n\t\t\tAT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;\r\n\t\t}\r\n\r\n\t\tLED_A_OFF();\r\n\t\t\r\n\t\tif(MillerDecoding((data[0] & 0xF0) >> 4)) {\r\n\t\t\tLED_C_INV();\r\n\t\t\t// check - if there is a short 7bit request from reader\r\n\t\t\tif (MfSniffLogic(receivedCmd, Uart.byteCnt, Uart.parityBits, Uart.bitCnt, TRUE)) break;\r\n\r\n\t\t\t/* And ready to receive another command. */\r\n\t\t\tUart.state = STATE_UNSYNCD;\r\n\t\t\t\r\n\t\t\t/* And also reset the demod code */\r\n\t\t\tDemod.state = DEMOD_UNSYNCD;\r\n\t\t}\r\n\r\n\t\tif(ManchesterDecoding(data[0] & 0x0F)) {\r\n\t\t\tLED_C_INV();\r\n\r\n\t\t\tif (MfSniffLogic(receivedResponse, Demod.len, Demod.parityBits, Demod.bitCount, FALSE)) break;\r\n\r\n\t\t\t// And ready to receive another response.\r\n\t\t\tmemset(&Demod, 0, sizeof(Demod));\r\n\t\t\tDemod.output = receivedResponse;\r\n\t\t\tDemod.state = DEMOD_UNSYNCD;\r\n\r\n\t\t\t/* And also reset the uart code */\r\n\t\t\tUart.state = STATE_UNSYNCD;\r\n\t\t}\r\n\r\n\t\tdata++;\r\n\t\tif(data > dmaBuf + DMA_BUFFER_SIZE) {\r\n\t\t\tdata = dmaBuf;\r\n\t\t}\r\n\t} // main cycle\r\n\r\n\tDbpString(\"COMMAND FINISHED\");\r\n\r\ndone:\r\n\tFpgaDisableSscDma();\r\n\tMfSniffEnd();\r\n\t\r\n\tDbprintf(\"maxDataLen=%x, Uart.state=%x, Uart.byteCnt=%x Uart.byteCntMax=%x\", maxDataLen, Uart.state, Uart.byteCnt, Uart.byteCntMax);\r\n\tLEDsoff();\r\n}\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/iso14443a.h", "content": "//-----------------------------------------------------------------------------\n// Merlok - June 2011\n// Gerhard de Koning Gans - May 2008\n// Hagen Fritsch - June 2010\n//\n// This code is licensed to you under the terms of the GNU GPL, version 2 or,\n// at your option, any later version. See the LICENSE.txt file for the text of\n// the license.\n//-----------------------------------------------------------------------------\n// Routines to support ISO 14443 type A.\n//-----------------------------------------------------------------------------\n\n#ifndef __ISO14443A_H\n#define __ISO14443A_H\n#include \"common.h\"\n#include \"mifaresniff.h\"\n\n// mifare reader over DMA buffer (SnoopIso14443a())!!!\n#define MIFARE_BUFF_OFFSET 3560 // \\/ \\/ \\/\n// card emulator memory\n#define EML_RESPONSES 4000\n#define CARD_MEMORY 6000\n#define CARD_MEMORY_LEN 4096\n\ntypedef struct nestedVector { uint32_t nt, ks1; } nestedVector;\n\ntypedef struct {\n\tenum {\n\t\tDEMOD_UNSYNCD,\n\t\tDEMOD_START_OF_COMMUNICATION,\n\t\tDEMOD_MANCHESTER_D,\n\t\tDEMOD_MANCHESTER_E,\n\t\tDEMOD_MANCHESTER_F,\n\t\tDEMOD_ERROR_WAIT\n\t} state;\n\tint bitCount;\n\tint posCount;\n\tint syncBit;\n\tint parityBits;\n\tuint16_t shiftReg;\n\tint buffer;\n\tint buff;\n\tint samples;\n\tint len;\n\tenum {\n\t\tSUB_NONE,\n\t\tSUB_FIRST_HALF,\n\t\tSUB_SECOND_HALF\n\t}\t\tsub;\n\tuint8_t *output;\n} tDemod;\n\ntypedef struct {\n\tenum {\n\t\tSTATE_UNSYNCD,\n\t\tSTATE_START_OF_COMMUNICATION,\n\t\tSTATE_MILLER_X,\n\t\tSTATE_MILLER_Y,\n\t\tSTATE_MILLER_Z,\n\t\tSTATE_ERROR_WAIT\n\t\t}\t\tstate;\n\t\tuint16_t shiftReg;\n\t\tint\tbitCnt;\n\t\tint\tbyteCnt;\n\t\tint\tbyteCntMax;\n\t\tint\tposCnt;\n\t\tint\tsyncBit;\n\t\tint\tparityBits;\n\t\tint\tsamples;\n\t\tint\thighCnt;\n\t\tint\tbitBuffer;\n\tenum {\n\t\tDROP_NONE,\n\t\tDROP_FIRST_HALF,\n\t\tDROP_SECOND_HALF\n\t}\t\tdrop;\n uint8_t *output;\n} tUart;\n\n\nextern byte_t oddparity (const byte_t bt);\nextern uint32_t GetParity(const uint8_t * pbtCmd, int iLen);\nextern void AppendCrc14443a(uint8_t* data, int len);\n\nextern void ReaderTransmit(uint8_t* frame, int len);\nextern void ReaderTransmitBitsPar(uint8_t* frame, int bits, uint32_t par);\nextern void ReaderTransmitPar(uint8_t* frame, int len, uint32_t par);\nextern int ReaderReceive(uint8_t* receivedAnswer);\nextern int ReaderReceivePar(uint8_t* receivedAnswer, uint32_t * parptr);\n\nextern void iso14443a_setup();\nextern int iso14_apdu(uint8_t * cmd, size_t cmd_len, void * data);\nextern int iso14443a_select_card(uint8_t * uid_ptr, iso14a_card_select_t * resp_data, uint32_t * cuid_ptr);\nextern void iso14a_set_trigger(bool enable);\nextern void iso14a_set_timeout(uint32_t timeout);\n\nextern void iso14a_clear_tracelen();\nextern void iso14a_set_tracing(bool enable);\n\n#endif /* __ISO14443A_H */\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/iso15693.c", "content": "//-----------------------------------------------------------------------------\r\n// Jonathan Westhues, split Nov 2006\r\n// Modified by Greg Jones, Jan 2009\r\n// Modified by Adrian Dabrowski \"atrox\", Mar-Sept 2010,Oct 2011\r\n//\r\n// This code is licensed to you under the terms of the GNU GPL, version 2 or,\r\n// at your option, any later version. See the LICENSE.txt file for the text of\r\n// the license.\r\n//-----------------------------------------------------------------------------\r\n// Routines to support ISO 15693. This includes both the reader software and\r\n// the `fake tag' modes, but at the moment I've implemented only the reader\r\n// stuff, and that barely.\r\n// Modified to perform modulation onboard in arm rather than on PC\r\n// Also added additional reader commands (SELECT, READ etc.)\r\n//-----------------------------------------------------------------------------\r\n// The ISO 15693 describes two transmission modes from reader to tag, and 4 \r\n// transmission modes from tag to reader. As of Mar 2010 this code only \r\n// supports one of each: \"1of4\" mode from reader to tag, and the highspeed \r\n// variant with one subcarrier from card to reader.\r\n// As long, as the card fully support ISO 15693 this is no problem, since the \r\n// reader chooses both data rates, but some non-standard tags do not. Further for \r\n// the simulation to work, we will need to support all data rates.\r\n//\r\n// VCD (reader) -> VICC (tag)\r\n// 1 out of 256:\r\n// \tdata rate: 1,66 kbit/s (fc/8192) \r\n// \tused for long range\r\n// 1 out of 4:\r\n// \tdata rate: 26,48 kbit/s (fc/512)\r\n//\tused for short range, high speed\r\n// \r\n// VICC (tag) -> VCD (reader)\r\n// Modulation:\r\n//\t\tASK / one subcarrier (423,75 khz)\r\n//\t\tFSK / two subcarriers (423,75 khz && 484,28 khz)\r\n// Data Rates / Modes:\r\n// \tlow ASK: 6,62 kbit/s\r\n// \tlow FSK: 6.67 kbit/s\r\n// \thigh ASK: 26,48 kbit/s\r\n// \thigh FSK: 26,69 kbit/s\r\n//-----------------------------------------------------------------------------\r\n// added \"1 out of 256\" mode (for VCD->PICC) - atrox 20100911\r\n\r\n\r\n// Random Remarks:\r\n// *) UID is always used \"transmission order\" (LSB), which is reverse to display order\r\n\r\n// TODO / BUGS / ISSUES:\r\n// *) writing to tags takes longer: we miss the answer from the tag in most cases\r\n// -> tweak the read-timeout times\r\n// *) signal decoding from the card is still a bit shaky. \r\n// *) signal decoding is unable to detect collissions.\r\n// *) add anti-collission support for inventory-commands \r\n// *) read security status of a block\r\n// *) sniffing and simulation do only support one transmission mode. need to support \r\n//\t\tall 8 transmission combinations\r\n//\t*) remove or refactor code under \"depricated\"\r\n// *) document all the functions\r\n\r\n\r\n#include \"proxmark3.h\"\r\n#include \"util.h\"\r\n#include \"apps.h\"\r\n#include \"string.h\"\r\n#include \"iso15693tools.h\"\r\n#include \"cmd.h\"\r\n\r\n#define arraylen(x) (sizeof(x)/sizeof((x)[0]))\r\n\r\n///////////////////////////////////////////////////////////////////////\r\n// ISO 15693 Part 2 - Air Interface\r\n// This section basicly contains transmission and receiving of bits\r\n///////////////////////////////////////////////////////////////////////\r\n\r\n#define FrameSOF Iso15693FrameSOF\r\n#define Logic0 Iso15693Logic0\r\n#define Logic1 Iso15693Logic1\r\n#define FrameEOF Iso15693FrameEOF\r\n\r\n#define Crc(data,datalen) Iso15693Crc(data,datalen)\r\n#define AddCrc(data,datalen) Iso15693AddCrc(data,datalen)\r\n#define sprintUID(target,uid)\tIso15693sprintUID(target,uid)\r\n\r\nint DEBUG=0;\r\n\r\n\r\n// ---------------------------\r\n// Signal Processing \r\n// ---------------------------\r\n\r\n// prepare data using \"1 out of 4\" code for later transmission\r\n// resulting data rate is 26,48 kbit/s (fc/512)\r\n// cmd ... data\r\n// n ... length of data\r\nstatic void CodeIso15693AsReader(uint8_t *cmd, int n)\r\n{\r\n\tint i, j;\r\n\r\n\tToSendReset();\r\n\r\n\t// Give it a bit of slack at the beginning\r\n\tfor(i = 0; i < 24; i++) {\r\n\t\tToSendStuffBit(1);\r\n\t}\r\n\r\n\t// SOF for 1of4\r\n\tToSendStuffBit(0);\r\n\tToSendStuffBit(1);\r\n\tToSendStuffBit(1);\r\n\tToSendStuffBit(1);\r\n\tToSendStuffBit(1);\r\n\tToSendStuffBit(0);\r\n\tToSendStuffBit(1);\r\n\tToSendStuffBit(1);\r\n\tfor(i = 0; i < n; i++) {\r\n\t\tfor(j = 0; j < 8; j += 2) {\r\n\t\t\tint these = (cmd[i] >> j) & 3;\r\n\t\t\tswitch(these) {\r\n\t\t\t\tcase 0:\r\n\t\t\t\t\tToSendStuffBit(1);\r\n\t\t\t\t\tToSendStuffBit(0);\r\n\t\t\t\t\tToSendStuffBit(1);\r\n\t\t\t\t\tToSendStuffBit(1);\r\n\t\t\t\t\tToSendStuffBit(1);\r\n\t\t\t\t\tToSendStuffBit(1);\r\n\t\t\t\t\tToSendStuffBit(1);\r\n\t\t\t\t\tToSendStuffBit(1);\r\n\t\t\t\t\tbreak;\r\n\t\t\t\tcase 1:\r\n\t\t\t\t\tToSendStuffBit(1);\r\n\t\t\t\t\tToSendStuffBit(1);\r\n\t\t\t\t\tToSendStuffBit(1);\r\n\t\t\t\t\tToSendStuffBit(0);\r\n\t\t\t\t\tToSendStuffBit(1);\r\n\t\t\t\t\tToSendStuffBit(1);\r\n\t\t\t\t\tToSendStuffBit(1);\r\n\t\t\t\t\tToSendStuffBit(1);\r\n\t\t\t\t\tbreak;\r\n\t\t\t\tcase 2:\r\n\t\t\t\t\tToSendStuffBit(1);\r\n\t\t\t\t\tToSendStuffBit(1);\r\n\t\t\t\t\tToSendStuffBit(1);\r\n\t\t\t\t\tToSendStuffBit(1);\r\n\t\t\t\t\tToSendStuffBit(1);\r\n\t\t\t\t\tToSendStuffBit(0);\r\n\t\t\t\t\tToSendStuffBit(1);\r\n\t\t\t\t\tToSendStuffBit(1);\r\n\t\t\t\t\tbreak;\r\n\t\t\t\tcase 3:\r\n\t\t\t\t\tToSendStuffBit(1);\r\n\t\t\t\t\tToSendStuffBit(1);\r\n\t\t\t\t\tToSendStuffBit(1);\r\n\t\t\t\t\tToSendStuffBit(1);\r\n\t\t\t\t\tToSendStuffBit(1);\r\n\t\t\t\t\tToSendStuffBit(1);\r\n\t\t\t\t\tToSendStuffBit(1);\r\n\t\t\t\t\tToSendStuffBit(0);\r\n\t\t\t\t\tbreak;\r\n\t\t\t}\r\n\t\t}\r\n\t}\r\n\t// EOF\r\n\tToSendStuffBit(1);\r\n\tToSendStuffBit(1);\r\n\tToSendStuffBit(0);\r\n\tToSendStuffBit(1);\r\n\r\n\t// And slack at the end, too.\r\n\tfor(i = 0; i < 24; i++) {\r\n\t\tToSendStuffBit(1);\r\n\t}\r\n}\r\n\r\n// encode data using \"1 out of 256\" sheme\r\n// data rate is 1,66 kbit/s (fc/8192) \r\n// is designed for more robust communication over longer distances\r\nstatic void CodeIso15693AsReader256(uint8_t *cmd, int n)\r\n{\r\n\tint i, j;\r\n\r\n\tToSendReset();\r\n\r\n\t// Give it a bit of slack at the beginning\r\n\tfor(i = 0; i < 24; i++) {\r\n\t\tToSendStuffBit(1);\r\n\t}\r\n\r\n\t// SOF for 1of256\r\n\tToSendStuffBit(0);\r\n\tToSendStuffBit(1);\r\n\tToSendStuffBit(1);\r\n\tToSendStuffBit(1);\r\n\tToSendStuffBit(1);\r\n\tToSendStuffBit(1);\r\n\tToSendStuffBit(1);\r\n\tToSendStuffBit(0);\r\n\t\r\n\tfor(i = 0; i < n; i++) {\r\n\t\tfor (j = 0; j<=255; j++) {\r\n\t\t\tif (cmd[i]==j) {\r\n\t\t\t\tToSendStuffBit(1);\r\n\t\t\t\tToSendStuffBit(0);\r\n\t\t\t} else {\r\n\t\t\t\tToSendStuffBit(1);\r\n\t\t\t\tToSendStuffBit(1);\r\n\t\t\t}\t\t\t\r\n\t\t}\t\r\n\t}\r\n\t// EOF\r\n\tToSendStuffBit(1);\r\n\tToSendStuffBit(1);\r\n\tToSendStuffBit(0);\r\n\tToSendStuffBit(1);\r\n\r\n\t// And slack at the end, too.\r\n\tfor(i = 0; i < 24; i++) {\r\n\t\tToSendStuffBit(1);\r\n\t}\r\n}\r\n\r\n\r\n// Transmit the command (to the tag) that was placed in ToSend[].\r\nstatic void TransmitTo15693Tag(const uint8_t *cmd, int len, int *samples, int *wait)\r\n{\r\n int c;\r\n\r\n// FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX);\r\n\tif(*wait < 10) { *wait = 10; }\r\n\r\n// for(c = 0; c < *wait;) {\r\n// if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r\n// AT91C_BASE_SSC->SSC_THR = 0x00;\t\t// For exact timing!\r\n// c++;\r\n// }\r\n// if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r\n// volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;\r\n// (void)r;\r\n// }\r\n// WDT_HIT();\r\n// }\r\n\r\n c = 0;\r\n for(;;) {\r\n if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r\n AT91C_BASE_SSC->SSC_THR = cmd[c];\r\n c++;\r\n if(c >= len) {\r\n break;\r\n }\r\n }\r\n if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r\n volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;\r\n (void)r;\r\n }\r\n WDT_HIT();\r\n }\r\n\t*samples = (c + *wait) << 3;\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// Transmit the command (to the reader) that was placed in ToSend[].\r\n//-----------------------------------------------------------------------------\r\nstatic void TransmitTo15693Reader(const uint8_t *cmd, int len, int *samples, int *wait)\r\n{\r\n int c;\r\n\r\n//\tFpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX);\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR);\t// No requirement to energise my coils\r\n\tif(*wait < 10) { *wait = 10; }\r\n\r\n c = 0;\r\n for(;;) {\r\n if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r\n AT91C_BASE_SSC->SSC_THR = cmd[c];\r\n c++;\r\n if(c >= len) {\r\n break;\r\n }\r\n }\r\n if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r\n volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;\r\n (void)r;\r\n }\r\n WDT_HIT();\r\n }\r\n\t*samples = (c + *wait) << 3;\r\n}\r\n\r\n\r\n// Read from Tag\r\n// Parameters:\r\n//\t\treceivedResponse\r\n//\t\tmaxLen\r\n//\t\tsamples\r\n//\t\telapsed\r\n// returns: \r\n//\t\tnumber of decoded bytes\r\nstatic int GetIso15693AnswerFromTag(uint8_t *receivedResponse, int maxLen, int *samples, int *elapsed)\r\n{\r\n\tint c = 0;\r\n\tuint8_t *dest = (uint8_t *)BigBuf;\r\n\tint getNext = 0;\r\n\r\n\tint8_t prev = 0;\r\n\r\n// NOW READ RESPONSE\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR);\r\n\t//spindelay(60);\t// greg - experiment to get rid of some of the 0 byte/failed reads\r\n\tc = 0;\r\n\tgetNext = FALSE;\r\n\tfor(;;) {\r\n\t\tif(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r\n\t\t\tAT91C_BASE_SSC->SSC_THR = 0x43;\r\n\t\t}\r\n\t\tif(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r\n\t\t\tint8_t b;\r\n\t\t\tb = (int8_t)AT91C_BASE_SSC->SSC_RHR;\r\n\r\n\t\t\t// The samples are correlations against I and Q versions of the\r\n\t\t\t// tone that the tag AM-modulates, so every other sample is I,\r\n\t\t\t// every other is Q. We just want power, so abs(I) + abs(Q) is\r\n\t\t\t// close to what we want.\r\n\t\t\tif(getNext) {\r\n\t\t\t\tint8_t r;\r\n\r\n\t\t\t\tif(b < 0) {\r\n\t\t\t\t\tr = -b;\r\n\t\t\t\t} else {\r\n\t\t\t\t\tr = b;\r\n\t\t\t\t}\r\n\t\t\t\tif(prev < 0) {\r\n\t\t\t\t\tr -= prev;\r\n\t\t\t\t} else {\r\n\t\t\t\t\tr += prev;\r\n\t\t\t\t}\r\n\r\n\t\t\t\tdest[c++] = (uint8_t)r;\r\n\r\n\t\t\t\tif(c >= 2000) {\r\n\t\t\t\t\tbreak;\r\n\t\t\t\t}\r\n\t\t\t} else {\r\n\t\t\t\tprev = b;\r\n\t\t\t}\r\n\r\n\t\t\tgetNext = !getNext;\r\n\t\t}\r\n\t}\r\n\r\n\t//////////////////////////////////////////\r\n\t/////////// DEMODULATE ///////////////////\r\n\t//////////////////////////////////////////\r\n\r\n\tint i, j;\r\n\tint max = 0, maxPos=0;\r\n\r\n\tint skip = 4;\r\n\r\n\t//\tif(GraphTraceLen < 1000) return;\t// THIS CHECKS FOR A BUFFER TO SMALL\r\n\r\n\t// First, correlate for SOF\r\n\tfor(i = 0; i < 100; i++) {\r\n\t\tint corr = 0;\r\n\t\tfor(j = 0; j < arraylen(FrameSOF); j += skip) {\r\n\t\t\tcorr += FrameSOF[j]*dest[i+(j/skip)];\r\n\t\t}\r\n\t\tif(corr > max) {\r\n\t\t\tmax = corr;\r\n\t\t\tmaxPos = i;\r\n\t\t}\r\n\t}\r\n\t//\tDbpString(\"SOF at %d, correlation %d\", maxPos,max/(arraylen(FrameSOF)/skip));\r\n\r\n\tint k = 0; // this will be our return value\r\n\r\n\t// greg - If correlation is less than 1 then there's little point in continuing\r\n\tif ((max/(arraylen(FrameSOF)/skip)) >= 1)\r\n\t{\r\n\r\n\t\ti = maxPos + arraylen(FrameSOF)/skip;\r\n\t\r\n\t\tuint8_t outBuf[20];\r\n\t\tmemset(outBuf, 0, sizeof(outBuf));\r\n\t\tuint8_t mask = 0x01;\r\n\t\tfor(;;) {\r\n\t\t\tint corr0 = 0, corr1 = 0, corrEOF = 0;\r\n\t\t\tfor(j = 0; j < arraylen(Logic0); j += skip) {\r\n\t\t\t\tcorr0 += Logic0[j]*dest[i+(j/skip)];\r\n\t\t\t}\r\n\t\t\tfor(j = 0; j < arraylen(Logic1); j += skip) {\r\n\t\t\t\tcorr1 += Logic1[j]*dest[i+(j/skip)];\r\n\t\t\t}\r\n\t\t\tfor(j = 0; j < arraylen(FrameEOF); j += skip) {\r\n\t\t\t\tcorrEOF += FrameEOF[j]*dest[i+(j/skip)];\r\n\t\t\t}\r\n\t\t\t// Even things out by the length of the target waveform.\r\n\t\t\tcorr0 *= 4;\r\n\t\t\tcorr1 *= 4;\r\n\t\r\n\t\t\tif(corrEOF > corr1 && corrEOF > corr0) {\r\n\t//\t\t\tDbpString(\"EOF at %d\", i);\r\n\t\t\t\tbreak;\r\n\t\t\t} else if(corr1 > corr0) {\r\n\t\t\t\ti += arraylen(Logic1)/skip;\r\n\t\t\t\toutBuf[k] |= mask;\r\n\t\t\t} else {\r\n\t\t\t\ti += arraylen(Logic0)/skip;\r\n\t\t\t}\r\n\t\t\tmask <<= 1;\r\n\t\t\tif(mask == 0) {\r\n\t\t\t\tk++;\r\n\t\t\t\tmask = 0x01;\r\n\t\t\t}\r\n\t\t\tif((i+(int)arraylen(FrameEOF)) >= 2000) {\r\n\t\t\t\tDbpString(\"ran off end!\");\r\n\t\t\t\tbreak;\r\n\t\t\t}\r\n\t\t}\r\n\t\tif(mask != 0x01) { // this happens, when we miss the EOF\r\n\t\t\t// TODO: for some reason this happens quite often\r\n\t\t\tif (DEBUG) Dbprintf(\"error, uneven octet! (extra bits!) mask=%02x\", mask);\r\n\t\t\tif (mask<0x08) k--; // discard the last uneven octet;\r\n\t\t\t// 0x08 is an assumption - but works quite often\r\n\t\t}\r\n\t//\tuint8_t str1 [8];\r\n\t//\titoa(k,str1);\r\n\t//\tstrncat(str1,\" octets read\",8);\r\n\t\r\n\t//\tDbpString( str1); // DbpString(\"%d octets\", k);\r\n\t\r\n\t//\tfor(i = 0; i < k; i+=3) {\r\n\t//\t\t//DbpString(\"# %2d: %02x \", i, outBuf[i]);\r\n\t//\t\tDbpIntegers(outBuf[i],outBuf[i+1],outBuf[i+2]);\r\n\t//\t}\r\n\t\r\n\t\tfor(i = 0; i < k; i++) {\r\n\t\t\treceivedResponse[i] = outBuf[i];\r\n\t\t}\r\n\t} // \"end if correlation > 0\" \t(max/(arraylen(FrameSOF)/skip))\r\n\treturn k; // return the number of bytes demodulated\r\n\r\n///\tDbpString(\"CRC=%04x\", Iso15693Crc(outBuf, k-2));\r\n\r\n}\r\n\r\n\r\n// Now the GetISO15693 message from sniffing command\r\nstatic int GetIso15693AnswerFromSniff(uint8_t *receivedResponse, int maxLen, int *samples, int *elapsed)\r\n{\r\n\tint c = 0;\r\n\tuint8_t *dest = (uint8_t *)BigBuf;\r\n\tint getNext = 0;\r\n\r\n\tint8_t prev = 0;\r\n\r\n// NOW READ RESPONSE\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR);\r\n\t//spindelay(60);\t// greg - experiment to get rid of some of the 0 byte/failed reads\r\n\tc = 0;\r\n\tgetNext = FALSE;\r\n\tfor(;;) {\r\n\t\tif(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r\n\t\t\tAT91C_BASE_SSC->SSC_THR = 0x43;\r\n\t\t}\r\n\t\tif(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r\n\t\t\tint8_t b;\r\n\t\t\tb = (int8_t)AT91C_BASE_SSC->SSC_RHR;\r\n\r\n\t\t\t// The samples are correlations against I and Q versions of the\r\n\t\t\t// tone that the tag AM-modulates, so every other sample is I,\r\n\t\t\t// every other is Q. We just want power, so abs(I) + abs(Q) is\r\n\t\t\t// close to what we want.\r\n\t\t\tif(getNext) {\r\n\t\t\t\tint8_t r;\r\n\r\n\t\t\t\tif(b < 0) {\r\n\t\t\t\t\tr = -b;\r\n\t\t\t\t} else {\r\n\t\t\t\t\tr = b;\r\n\t\t\t\t}\r\n\t\t\t\tif(prev < 0) {\r\n\t\t\t\t\tr -= prev;\r\n\t\t\t\t} else {\r\n\t\t\t\t\tr += prev;\r\n\t\t\t\t}\r\n\r\n\t\t\t\tdest[c++] = (uint8_t)r;\r\n\r\n\t\t\t\tif(c >= 20000) {\r\n\t\t\t\t\tbreak;\r\n\t\t\t\t}\r\n\t\t\t} else {\r\n\t\t\t\tprev = b;\r\n\t\t\t}\r\n\r\n\t\t\tgetNext = !getNext;\r\n\t\t}\r\n\t}\r\n\r\n\t//////////////////////////////////////////\r\n\t/////////// DEMODULATE ///////////////////\r\n\t//////////////////////////////////////////\r\n\r\n\tint i, j;\r\n\tint max = 0, maxPos=0;\r\n\r\n\tint skip = 4;\r\n\r\n//\tif(GraphTraceLen < 1000) return;\t// THIS CHECKS FOR A BUFFER TO SMALL\r\n\r\n\t// First, correlate for SOF\r\n\tfor(i = 0; i < 19000; i++) {\r\n\t\tint corr = 0;\r\n\t\tfor(j = 0; j < arraylen(FrameSOF); j += skip) {\r\n\t\t\tcorr += FrameSOF[j]*dest[i+(j/skip)];\r\n\t\t}\r\n\t\tif(corr > max) {\r\n\t\t\tmax = corr;\r\n\t\t\tmaxPos = i;\r\n\t\t}\r\n\t}\r\n//\tDbpString(\"SOF at %d, correlation %d\", maxPos,max/(arraylen(FrameSOF)/skip));\r\n\r\n\tint k = 0; // this will be our return value\r\n\r\n\t// greg - If correlation is less than 1 then there's little point in continuing\r\n\tif ((max/(arraylen(FrameSOF)/skip)) >= 1)\t// THIS SHOULD BE 1\r\n\t{\r\n\t\r\n\t\ti = maxPos + arraylen(FrameSOF)/skip;\r\n\t\r\n\t\tuint8_t outBuf[20];\r\n\t\tmemset(outBuf, 0, sizeof(outBuf));\r\n\t\tuint8_t mask = 0x01;\r\n\t\tfor(;;) {\r\n\t\t\tint corr0 = 0, corr1 = 0, corrEOF = 0;\r\n\t\t\tfor(j = 0; j < arraylen(Logic0); j += skip) {\r\n\t\t\t\tcorr0 += Logic0[j]*dest[i+(j/skip)];\r\n\t\t\t}\r\n\t\t\tfor(j = 0; j < arraylen(Logic1); j += skip) {\r\n\t\t\t\tcorr1 += Logic1[j]*dest[i+(j/skip)];\r\n\t\t\t}\r\n\t\t\tfor(j = 0; j < arraylen(FrameEOF); j += skip) {\r\n\t\t\t\tcorrEOF += FrameEOF[j]*dest[i+(j/skip)];\r\n\t\t\t}\r\n\t\t\t// Even things out by the length of the target waveform.\r\n\t\t\tcorr0 *= 4;\r\n\t\t\tcorr1 *= 4;\r\n\t\r\n\t\t\tif(corrEOF > corr1 && corrEOF > corr0) {\r\n\t//\t\t\tDbpString(\"EOF at %d\", i);\r\n\t\t\t\tbreak;\r\n\t\t\t} else if(corr1 > corr0) {\r\n\t\t\t\ti += arraylen(Logic1)/skip;\r\n\t\t\t\toutBuf[k] |= mask;\r\n\t\t\t} else {\r\n\t\t\t\ti += arraylen(Logic0)/skip;\r\n\t\t\t}\r\n\t\t\tmask <<= 1;\r\n\t\t\tif(mask == 0) {\r\n\t\t\t\tk++;\r\n\t\t\t\tmask = 0x01;\r\n\t\t\t}\r\n\t\t\tif((i+(int)arraylen(FrameEOF)) >= 2000) {\r\n\t\t\t\tDbpString(\"ran off end!\");\r\n\t\t\t\tbreak;\r\n\t\t\t}\r\n\t\t}\r\n\t\tif(mask != 0x01) {\r\n\t\t\tDbpString(\"sniff: error, uneven octet! (discard extra bits!)\");\r\n\t///\t\tDbpString(\" mask=%02x\", mask);\r\n\t\t}\r\n\t//\tuint8_t str1 [8];\r\n\t//\titoa(k,str1);\r\n\t//\tstrncat(str1,\" octets read\",8);\r\n\t\r\n\t//\tDbpString( str1); // DbpString(\"%d octets\", k);\r\n\t\r\n\t//\tfor(i = 0; i < k; i+=3) {\r\n\t//\t\t//DbpString(\"# %2d: %02x \", i, outBuf[i]);\r\n\t//\t\tDbpIntegers(outBuf[i],outBuf[i+1],outBuf[i+2]);\r\n\t//\t}\r\n\t\r\n\t\tfor(i = 0; i < k; i++) {\r\n\t\t\treceivedResponse[i] = outBuf[i];\r\n\t\t}\r\n\t} // \"end if correlation > 0\" \t(max/(arraylen(FrameSOF)/skip))\r\n\treturn k; // return the number of bytes demodulated\r\n\r\n///\tDbpString(\"CRC=%04x\", Iso15693Crc(outBuf, k-2));\r\n}\r\n\r\n\r\nstatic void BuildIdentifyRequest(void);\r\n//-----------------------------------------------------------------------------\r\n// Start to read an ISO 15693 tag. We send an identify request, then wait\r\n// for the response. The response is not demodulated, just left in the buffer\r\n// so that it can be downloaded to a PC and processed there.\r\n//-----------------------------------------------------------------------------\r\nvoid AcquireRawAdcSamplesIso15693(void)\r\n{\r\n\tint c = 0;\r\n\tuint8_t *dest = (uint8_t *)BigBuf;\r\n\tint getNext = 0;\r\n\r\n\tint8_t prev = 0;\r\n\r\n\tBuildIdentifyRequest();\r\n\r\n\tSetAdcMuxFor(GPIO_MUXSEL_HIPKD);\r\n\r\n\t// Give the tags time to energize\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR);\r\n\tSpinDelay(100);\r\n\r\n\t// Now send the command\r\n\tFpgaSetupSsc();\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX);\r\n\r\n\tc = 0;\r\n\tfor(;;) {\r\n\t\tif(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r\n\t\t\tAT91C_BASE_SSC->SSC_THR = ToSend[c];\r\n\t\t\tc++;\r\n\t\t\tif(c == ToSendMax+3) {\r\n\t\t\t\tbreak;\r\n\t\t\t}\r\n\t\t}\r\n\t\tif(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r\n\t\t\tvolatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;\r\n\t\t\t(void)r;\r\n\t\t}\r\n\t\tWDT_HIT();\r\n\t}\r\n\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR);\r\n\r\n\tc = 0;\r\n\tgetNext = FALSE;\r\n\tfor(;;) {\r\n\t\tif(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r\n\t\t\tAT91C_BASE_SSC->SSC_THR = 0x43;\r\n\t\t}\r\n\t\tif(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r\n\t\t\tint8_t b;\r\n\t\t\tb = (int8_t)AT91C_BASE_SSC->SSC_RHR;\r\n\r\n\t\t\t// The samples are correlations against I and Q versions of the\r\n\t\t\t// tone that the tag AM-modulates, so every other sample is I,\r\n\t\t\t// every other is Q. We just want power, so abs(I) + abs(Q) is\r\n\t\t\t// close to what we want.\r\n\t\t\tif(getNext) {\r\n\t\t\t\tint8_t r;\r\n\r\n\t\t\t\tif(b < 0) {\r\n\t\t\t\t\tr = -b;\r\n\t\t\t\t} else {\r\n\t\t\t\t\tr = b;\r\n\t\t\t\t}\r\n\t\t\t\tif(prev < 0) {\r\n\t\t\t\t\tr -= prev;\r\n\t\t\t\t} else {\r\n\t\t\t\t\tr += prev;\r\n\t\t\t\t}\r\n\r\n\t\t\t\tdest[c++] = (uint8_t)r;\r\n\r\n\t\t\t\tif(c >= 2000) {\r\n\t\t\t\t\tbreak;\r\n\t\t\t\t}\r\n\t\t\t} else {\r\n\t\t\t\tprev = b;\r\n\t\t\t}\r\n\r\n\t\t\tgetNext = !getNext;\r\n\t\t}\r\n\t}\r\n}\r\n\r\n\r\nvoid RecordRawAdcSamplesIso15693(void)\r\n{\r\n\tint c = 0;\r\n\tuint8_t *dest = (uint8_t *)BigBuf;\r\n\tint getNext = 0;\r\n\r\n\tint8_t prev = 0;\r\n\r\n\t// Setup SSC\r\n\tFpgaSetupSsc();\r\n\r\n\t// Start from off (no field generated)\r\n \tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n \tSpinDelay(200);\r\n\r\n\tSetAdcMuxFor(GPIO_MUXSEL_HIPKD);\r\n\r\n\tSpinDelay(100);\r\n\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR);\r\n\r\n\tc = 0;\r\n\tgetNext = FALSE;\r\n\tfor(;;) {\r\n\t\tif(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r\n\t\t\tAT91C_BASE_SSC->SSC_THR = 0x43;\r\n\t\t}\r\n\t\tif(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r\n\t\t\tint8_t b;\r\n\t\t\tb = (int8_t)AT91C_BASE_SSC->SSC_RHR;\r\n\r\n\t\t\t// The samples are correlations against I and Q versions of the\r\n\t\t\t// tone that the tag AM-modulates, so every other sample is I,\r\n\t\t\t// every other is Q. We just want power, so abs(I) + abs(Q) is\r\n\t\t\t// close to what we want.\r\n\t\t\tif(getNext) {\r\n\t\t\t\tint8_t r;\r\n\r\n\t\t\t\tif(b < 0) {\r\n\t\t\t\t\tr = -b;\r\n\t\t\t\t} else {\r\n\t\t\t\t\tr = b;\r\n\t\t\t\t}\r\n\t\t\t\tif(prev < 0) {\r\n\t\t\t\t\tr -= prev;\r\n\t\t\t\t} else {\r\n\t\t\t\t\tr += prev;\r\n\t\t\t\t}\r\n\r\n\t\t\t\tdest[c++] = (uint8_t)r;\r\n\r\n\t\t\t\tif(c >= 7000) {\r\n\t\t\t\t\tbreak;\r\n\t\t\t\t}\r\n\t\t\t} else {\r\n\t\t\t\tprev = b;\r\n\t\t\t}\r\n\r\n\t\t\tgetNext = !getNext;\r\n\t\t\tWDT_HIT();\r\n\t\t}\r\n\t}\r\n\tDbprintf(\"fin record\");\r\n}\r\n\r\n\r\n// Initialize the proxmark as iso15k reader \r\n// (this might produces glitches that confuse some tags\r\nvoid Iso15693InitReader() {\r\n\tLED_A_ON();\r\n\tLED_B_ON();\r\n\tLED_C_OFF();\r\n\tLED_D_OFF();\r\n\t\r\n\t// Setup SSC\r\n\t// FpgaSetupSsc();\r\n\r\n\t// Start from off (no field generated)\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\tSpinDelay(10);\r\n\r\n\tSetAdcMuxFor(GPIO_MUXSEL_HIPKD);\r\n\tFpgaSetupSsc();\r\n\r\n\t// Give the tags time to energize\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR);\r\n\tSpinDelay(250);\r\n\r\n\tLED_A_ON();\r\n\tLED_B_OFF();\r\n\tLED_C_OFF();\r\n\tLED_D_OFF();\r\n}\r\n\r\n///////////////////////////////////////////////////////////////////////\r\n// ISO 15693 Part 3 - Air Interface\r\n// This section basicly contains transmission and receiving of bits\r\n///////////////////////////////////////////////////////////////////////\r\n\r\n// Encode (into the ToSend buffers) an identify request, which is the first\r\n// thing that you must send to a tag to get a response.\r\nstatic void BuildIdentifyRequest(void)\r\n{\r\n\tuint8_t cmd[5];\r\n\r\n\tuint16_t crc;\r\n\t// one sub-carrier, inventory, 1 slot, fast rate\r\n\t// AFI is at bit 5 (1<<4) when doing an INVENTORY\r\n\tcmd[0] = (1 << 2) | (1 << 5) | (1 << 1);\r\n\t// inventory command code\r\n\tcmd[1] = 0x01;\r\n\t// no mask\r\n\tcmd[2] = 0x00;\r\n\t//Now the CRC\r\n\tcrc = Crc(cmd, 3);\r\n\tcmd[3] = crc & 0xff;\r\n\tcmd[4] = crc >> 8;\r\n\r\n\tCodeIso15693AsReader(cmd, sizeof(cmd));\r\n}\r\n\r\n// uid is in transmission order (which is reverse of display order)\r\nstatic void BuildReadBlockRequest(uint8_t *uid, uint8_t blockNumber )\r\n{\r\n\tuint8_t cmd[13];\r\n\r\n\tuint16_t crc;\r\n\t// If we set the Option_Flag in this request, the VICC will respond with the secuirty status of the block\r\n\t// followed by teh block data\r\n\t// one sub-carrier, inventory, 1 slot, fast rate\r\n\tcmd[0] = (1 << 6)| (1 << 5) | (1 << 1); // no SELECT bit, ADDR bit, OPTION bit\r\n\t// READ BLOCK command code\r\n\tcmd[1] = 0x20;\r\n\t// UID may be optionally specified here\r\n\t// 64-bit UID\r\n\tcmd[2] = uid[0];\r\n\tcmd[3] = uid[1];\r\n\tcmd[4] = uid[2];\r\n\tcmd[5] = uid[3];\r\n\tcmd[6] = uid[4];\r\n\tcmd[7] = uid[5];\r\n\tcmd[8] = uid[6];\r\n\tcmd[9] = uid[7]; // 0xe0; // always e0 (not exactly unique)\r\n\t// Block number to read\r\n\tcmd[10] = blockNumber;//0x00;\r\n\t//Now the CRC\r\n\tcrc = Crc(cmd, 11); // the crc needs to be calculated over 12 bytes\r\n\tcmd[11] = crc & 0xff;\r\n\tcmd[12] = crc >> 8;\r\n\r\n\tCodeIso15693AsReader(cmd, sizeof(cmd));\r\n}\r\n\r\n// Now the VICC>VCD responses when we are simulating a tag\r\n static void BuildInventoryResponse(void)\r\n{\r\n\tuint8_t cmd[12];\r\n\r\n\tuint16_t crc;\r\n\t// one sub-carrier, inventory, 1 slot, fast rate\r\n\t// AFI is at bit 5 (1<<4) when doing an INVENTORY\r\n\tcmd[0] = 0; //(1 << 2) | (1 << 5) | (1 << 1);\r\n\tcmd[1] = 0;\r\n\t// 64-bit UID\r\n\tcmd[2] = 0x32;\r\n\tcmd[3]= 0x4b;\r\n\tcmd[4] = 0x03;\r\n\tcmd[5] = 0x01;\r\n\tcmd[6] = 0x00;\r\n\tcmd[7] = 0x10;\r\n\tcmd[8] = 0x05;\r\n\tcmd[9]= 0xe0;\r\n\t//Now the CRC\r\n\tcrc = Crc(cmd, 10);\r\n\tcmd[10] = crc & 0xff;\r\n\tcmd[11] = crc >> 8;\r\n\r\n\tCodeIso15693AsReader(cmd, sizeof(cmd));\r\n}\r\n\r\n// Universal Method for sending to and recv bytes from a tag\r\n// \tinit ... should we initialize the reader?\r\n// \tspeed ... 0 low speed, 1 hi speed \r\n// \t**recv will return you a pointer to the received data\r\n// \tIf you do not need the answer use NULL for *recv[] \r\n//\treturn: lenght of received data\r\nint SendDataTag(uint8_t *send, int sendlen, int init, int speed, uint8_t **recv) {\r\n\r\n\tint samples = 0;\r\n\tint tsamples = 0;\r\n\tint wait = 0;\r\n\tint elapsed = 0;\r\n\t\r\n\tLED_A_ON();\r\n\tLED_B_ON();\r\n\tLED_C_OFF();\r\n\tLED_D_OFF();\r\n\t\r\n\tint answerLen=0;\r\n\tuint8_t *answer = (((uint8_t *)BigBuf) + 3660);\r\n\tif (recv!=NULL) memset(BigBuf + 3660, 0, 100);\r\n\r\n\tif (init) Iso15693InitReader();\r\n\t\r\n\tif (!speed) {\r\n\t\t// low speed (1 out of 256)\r\n\t\tCodeIso15693AsReader256(send, sendlen);\r\n\t} else {\r\n\t\t// high speed (1 out of 4)\r\n\t\tCodeIso15693AsReader(send, sendlen);\r\n\t}\r\n\t\r\n\tLED_A_ON();\r\n\tLED_B_OFF();\r\n\t\r\n\tTransmitTo15693Tag(ToSend,ToSendMax,&tsamples, &wait);\t\r\n\t// Now wait for a response\r\n\tif (recv!=NULL) {\r\n\t\tLED_A_OFF();\r\n\t\tLED_B_ON();\r\n\t\tanswerLen = GetIso15693AnswerFromTag(answer, 100, &samples, &elapsed) ;\t\r\n\t\t*recv=answer;\r\n\t}\r\n\r\n\tLED_A_OFF();\r\n\tLED_B_OFF();\r\n\tLED_C_OFF();\r\n\tLED_D_OFF();\r\n\t\r\n\treturn answerLen;\r\n}\r\n\r\n\r\n// --------------------------------------------------------------------\r\n// Debug Functions \r\n// --------------------------------------------------------------------\r\n\r\n// Decodes a message from a tag and displays its metadata and content\r\n#define DBD15STATLEN 48\r\nvoid DbdecodeIso15693Answer(int len, uint8_t *d) {\r\n\tchar status[DBD15STATLEN+1]={0};\r\n\tuint16_t crc;\r\n\r\n\tif (len>3) {\r\n\t\tif (d[0]&(1<<3)) \r\n\t\t\tstrncat(status,\"ProtExt \",DBD15STATLEN);\r\n\t\tif (d[0]&1) { \r\n\t\t\t// error\r\n\t\t\tstrncat(status,\"Error \",DBD15STATLEN);\r\n\t\t\tswitch (d[1]) {\r\n\t\t\t\tcase 0x01: \r\n\t\t\t\t\tstrncat(status,\"01:notSupp\",DBD15STATLEN);\r\n\t\t\t\t\tbreak;\r\n\t\t\t\tcase 0x02: \r\n\t\t\t\t\tstrncat(status,\"02:notRecog\",DBD15STATLEN);\r\n\t\t\t\t\tbreak;\r\n\t\t\t\tcase 0x03: \r\n\t\t\t\t\tstrncat(status,\"03:optNotSupp\",DBD15STATLEN);\r\n\t\t\t\t\tbreak;\r\n\t\t\t\tcase 0x0f: \r\n\t\t\t\t\tstrncat(status,\"0f:noInfo\",DBD15STATLEN);\r\n\t\t\t\t\tbreak;\r\n\t\t\t\tcase 0x10: \r\n\t\t\t\t\tstrncat(status,\"10:dontExist\",DBD15STATLEN);\r\n\t\t\t\t\tbreak;\r\n\t\t\t\tcase 0x11: \r\n\t\t\t\t\tstrncat(status,\"11:lockAgain\",DBD15STATLEN);\r\n\t\t\t\t\tbreak;\r\n\t\t\t\tcase 0x12: \r\n\t\t\t\t\tstrncat(status,\"12:locked\",DBD15STATLEN);\r\n\t\t\t\t\tbreak;\r\n\t\t\t\tcase 0x13: \r\n\t\t\t\t\tstrncat(status,\"13:progErr\",DBD15STATLEN);\r\n\t\t\t\t\tbreak;\r\n\t\t\t\tcase 0x14: \r\n\t\t\t\t\tstrncat(status,\"14:lockErr\",DBD15STATLEN);\r\n\t\t\t\t\tbreak;\r\n\t\t\t\tdefault:\r\n\t\t\t\t\tstrncat(status,\"unknownErr\",DBD15STATLEN);\r\n\t\t\t}\r\n\t\t\tstrncat(status,\" \",DBD15STATLEN);\r\n\t\t} else {\r\n\t\t\tstrncat(status,\"NoErr \",DBD15STATLEN);\r\n\t\t}\r\n\t\t\t\r\n\t\tcrc=Crc(d,len-2);\r\n\t\tif ( (( crc & 0xff ) == d[len-2]) && (( crc >> 8 ) == d[len-1]) ) \r\n\t\t\tstrncat(status,\"CrcOK\",DBD15STATLEN);\r\n\t\telse\r\n\t\t\tstrncat(status,\"CrcFail!\",DBD15STATLEN); \r\n\r\n\t\tDbprintf(\"%s\",status);\r\n\t}\r\n}\r\n\r\n\r\n\r\n///////////////////////////////////////////////////////////////////////\r\n// Functions called via USB/Client\r\n///////////////////////////////////////////////////////////////////////\r\n\r\nvoid SetDebugIso15693(uint32_t debug) {\r\n\tDEBUG=debug;\r\n\tDbprintf(\"Iso15693 Debug is now %s\",DEBUG?\"on\":\"off\");\r\n\treturn;\r\n}\r\n\r\n\r\n\r\n//-----------------------------------------------------------------------------\r\n// Simulate an ISO15693 reader, perform anti-collision and then attempt to read a sector\r\n// all demodulation performed in arm rather than host. - greg\r\n//-----------------------------------------------------------------------------\r\nvoid ReaderIso15693(uint32_t parameter)\r\n{\r\n\tLED_A_ON();\r\n\tLED_B_ON();\r\n\tLED_C_OFF();\r\n\tLED_D_OFF();\r\n\r\n//DbpString(parameter);\r\n\r\n\t//uint8_t *answer0 = (((uint8_t *)BigBuf) + 3560); // allow 100 bytes per reponse (way too much)\r\n\tuint8_t *answer1 = (((uint8_t *)BigBuf) + 3660); //\r\n\tuint8_t *answer2 = (((uint8_t *)BigBuf) + 3760);\r\n\tuint8_t *answer3 = (((uint8_t *)BigBuf) + 3860);\r\n\t//uint8_t *TagUID= (((uint8_t *)BigBuf) + 3960);\t\t// where we hold the uid for hi15reader\r\n//\tint answerLen0 = 0;\r\n\tint answerLen1 = 0;\r\n\tint answerLen2 = 0;\r\n\tint answerLen3 = 0;\r\n\tint i=0; // counter\r\n\r\n\t// Blank arrays\r\n\tmemset(BigBuf + 3660, 0, 300);\r\n\r\n\t// Setup SSC\r\n\tFpgaSetupSsc();\r\n\r\n\t// Start from off (no field generated)\r\n \tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n \tSpinDelay(200);\r\n\r\n\tSetAdcMuxFor(GPIO_MUXSEL_HIPKD);\r\n\tFpgaSetupSsc();\r\n\r\n\t// Give the tags time to energize\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR);\r\n\tSpinDelay(200);\r\n\r\n\tLED_A_ON();\r\n\tLED_B_OFF();\r\n\tLED_C_OFF();\r\n\tLED_D_OFF();\r\n\r\n\tint samples = 0;\r\n\tint tsamples = 0;\r\n\tint wait = 0;\r\n\tint elapsed = 0;\r\n\r\n\t// FIRST WE RUN AN INVENTORY TO GET THE TAG UID\r\n\t// THIS MEANS WE CAN PRE-BUILD REQUESTS TO SAVE CPU TIME\r\n\t uint8_t TagUID[8] = {0, 0, 0, 0, 0, 0, 0, 0};\t\t// where we hold the uid for hi15reader\r\n\r\n//\tBuildIdentifyRequest();\r\n//\t//TransmitTo15693Tag(ToSend,ToSendMax+3,&tsamples, &wait);\r\n//\tTransmitTo15693Tag(ToSend,ToSendMax,&tsamples, &wait);\t// No longer ToSendMax+3\r\n//\t// Now wait for a response\r\n//\tresponseLen0 = GetIso15693AnswerFromTag(receivedAnswer0, 100, &samples, &elapsed) ;\r\n//\tif (responseLen0 >=12) // we should do a better check than this\r\n//\t{\r\n//\t\t// really we should check it is a valid mesg\r\n//\t\t// but for now just grab what we think is the uid\r\n//\t\tTagUID[0] = receivedAnswer0[2];\r\n//\t\tTagUID[1] = receivedAnswer0[3];\r\n//\t\tTagUID[2] = receivedAnswer0[4];\r\n//\t\tTagUID[3] = receivedAnswer0[5];\r\n//\t\tTagUID[4] = receivedAnswer0[6];\r\n//\t\tTagUID[5] = receivedAnswer0[7];\r\n//\t\tTagUID[6] = receivedAnswer0[8]; // IC Manufacturer code\r\n//\tDbpIntegers(TagUID[6],TagUID[5],TagUID[4]);\r\n//}\r\n\r\n\t// Now send the IDENTIFY command\r\n\tBuildIdentifyRequest();\r\n\t//TransmitTo15693Tag(ToSend,ToSendMax+3,&tsamples, &wait);\r\n\tTransmitTo15693Tag(ToSend,ToSendMax,&tsamples, &wait);\t// No longer ToSendMax+3\r\n\t// Now wait for a response\r\n\tanswerLen1 = GetIso15693AnswerFromTag(answer1, 100, &samples, &elapsed) ;\r\n\r\n\tif (answerLen1 >=12) // we should do a better check than this\r\n\t{\r\n\r\n\t\tTagUID[0] = answer1[2];\r\n\t\tTagUID[1] = answer1[3];\r\n\t\tTagUID[2] = answer1[4];\r\n\t\tTagUID[3] = answer1[5];\r\n\t\tTagUID[4] = answer1[6];\r\n\t\tTagUID[5] = answer1[7];\r\n\t\tTagUID[6] = answer1[8]; // IC Manufacturer code\r\n\t\tTagUID[7] = answer1[9]; // always E0\r\n\r\n\t\t// Now send the SELECT command\r\n\t\t// since the SELECT command is optional, we should not rely on it.\r\n////\t\t\t\tBuildSelectRequest(TagUID);\r\n//\t\tTransmitTo15693Tag(ToSend,ToSendMax,&tsamples, &wait);\t// No longer ToSendMax+3\r\n\t\t// Now wait for a response\r\n///\t\tanswerLen2 = GetIso15693AnswerFromTag(answer2, 100, &samples, &elapsed);\r\n\r\n\t\t// Now send the MULTI READ command\r\n//\t\tBuildArbitraryRequest(*TagUID,parameter);\r\n///\t\tBuildArbitraryCustomRequest(TagUID,parameter);\r\n//\t\tBuildReadBlockRequest(*TagUID,parameter);\r\n//\t\tBuildSysInfoRequest(*TagUID);\r\n\t\t//TransmitTo15693Tag(ToSend,ToSendMax+3,&tsamples, &wait);\r\n///\t\tTransmitTo15693Tag(ToSend,ToSendMax,&tsamples, &wait);\t// No longer ToSendMax+3\r\n\t\t// Now wait for a response\r\n///\t\tanswerLen3 = GetIso15693AnswerFromTag(answer3, 100, &samples, &elapsed) ;\r\n\r\n\t}\r\n\r\n\tDbprintf(\"%d octets read from IDENTIFY request:\", answerLen1);\r\n\tDbdecodeIso15693Answer(answerLen1,answer1);\r\n\tDbhexdump(answerLen1,answer1,true);\r\n\r\n\t// UID is reverse\r\n\tif (answerLen1>=12) \r\n\t\t//Dbprintf(\"UID = %*D\",8,TagUID,\" \");\r\n\t\tDbprintf(\"UID = %02hX%02hX%02hX%02hX%02hX%02hX%02hX%02hX\",TagUID[7],TagUID[6],TagUID[5],\r\n\t\t\tTagUID[4],TagUID[3],TagUID[2],TagUID[1],TagUID[0]);\r\n\r\n\r\n\tDbprintf(\"%d octets read from SELECT request:\", answerLen2);\r\n\tDbdecodeIso15693Answer(answerLen2,answer2);\r\n\tDbhexdump(answerLen2,answer2,true);\r\n\r\n\tDbprintf(\"%d octets read from XXX request:\", answerLen3);\r\n\tDbdecodeIso15693Answer(answerLen3,answer3);\r\n\tDbhexdump(answerLen3,answer3,true);\r\n\r\n \r\n\t// read all pages\r\n\tif (answerLen1>=12 && DEBUG) {\r\n\t\ti=0;\t\t\t\r\n\t\twhile (i<32) { // sanity check, assume max 32 pages\r\n\t\t\tBuildReadBlockRequest(TagUID,i);\r\n\t TransmitTo15693Tag(ToSend,ToSendMax,&tsamples, &wait); \r\n answerLen2 = GetIso15693AnswerFromTag(answer2, 100, &samples, &elapsed);\r\n\t\t\tif (answerLen2>0) {\r\n\t\t\t\tDbprintf(\"READ SINGLE BLOCK %d returned %d octets:\",i,answerLen2);\r\n\t\t\t\tDbdecodeIso15693Answer(answerLen2,answer2);\r\n\t\t\t\tDbhexdump(answerLen2,answer2,true);\r\n\t\t\t\tif ( *((uint32_t*) answer2) == 0x07160101 ) break; // exit on NoPageErr \r\n\t\t\t} \r\n\t\t\ti++;\r\n\t\t} \r\n\t}\r\n\r\n//\tstr2[0]=0;\r\n//\tfor(i = 0; i < responseLen3; i++) {\r\n//\t\titoa(str1,receivedAnswer3[i]);\r\n//\t\tstrncat(str2,str1,8);\r\n//\t}\r\n//\tDbpString(str2);\r\n\r\n\tLED_A_OFF();\r\n\tLED_B_OFF();\r\n\tLED_C_OFF();\r\n\tLED_D_OFF();\r\n}\r\n\r\n// Simulate an ISO15693 TAG, perform anti-collision and then print any reader commands\r\n// all demodulation performed in arm rather than host. - greg\r\nvoid SimTagIso15693(uint32_t parameter)\r\n{\r\n\tLED_A_ON();\r\n\tLED_B_ON();\r\n\tLED_C_OFF();\r\n\tLED_D_OFF();\r\n\r\n\tuint8_t *answer1 = (((uint8_t *)BigBuf) + 3660); //\r\n\tint answerLen1 = 0;\r\n\r\n\t// Blank arrays\r\n\tmemset(answer1, 0, 100);\r\n\r\n\t// Setup SSC\r\n\tFpgaSetupSsc();\r\n\r\n\t// Start from off (no field generated)\r\n \tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n \tSpinDelay(200);\r\n\r\n\tSetAdcMuxFor(GPIO_MUXSEL_HIPKD);\r\n\tFpgaSetupSsc();\r\n\r\n\t// Give the tags time to energize\r\n//\tFpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR);\t// NO GOOD FOR SIM TAG!!!!\r\n\tSpinDelay(200);\r\n\r\n\tLED_A_OFF();\r\n\tLED_B_OFF();\r\n\tLED_C_ON();\r\n\tLED_D_OFF();\r\n\r\n\tint samples = 0;\r\n\tint tsamples = 0;\r\n\tint wait = 0;\r\n\tint elapsed = 0;\r\n\r\n\tanswerLen1 = GetIso15693AnswerFromSniff(answer1, 100, &samples, &elapsed) ;\r\n\r\n\tif (answerLen1 >=1) // we should do a better check than this\r\n\t{\r\n\t\t// Build a suitable reponse to the reader INVENTORY cocmmand\r\n\t\tBuildInventoryResponse();\r\n\t\tTransmitTo15693Reader(ToSend,ToSendMax, &tsamples, &wait);\r\n\t}\r\n\r\n\tDbprintf(\"%d octets read from reader command: %x %x %x %x %x %x %x %x %x\", answerLen1,\r\n\t\tanswer1[0], answer1[1], answer1[2],\r\n\t\tanswer1[3], answer1[4], answer1[5],\r\n\t\tanswer1[6], answer1[7], answer1[8]);\r\n\r\n\tLED_A_OFF();\r\n\tLED_B_OFF();\r\n\tLED_C_OFF();\r\n\tLED_D_OFF();\r\n}\r\n\r\n\r\n// Since there is no standardized way of reading the AFI out of a tag, we will brute force it\r\n// (some manufactures offer a way to read the AFI, though)\r\nvoid BruteforceIso15693Afi(uint32_t speed) \r\n{\t\r\n\tuint8_t data[20];\r\n\tuint8_t *recv=data;\r\n\tint datalen=0, recvlen=0;\r\n\t\t\r\n\tIso15693InitReader();\r\n\t\r\n\t// first without AFI\r\n\t// Tags should respond wihtout AFI and with AFI=0 even when AFI is active\r\n\t\r\n\tdata[0]=ISO15_REQ_SUBCARRIER_SINGLE | ISO15_REQ_DATARATE_HIGH | \r\n\t ISO15_REQ_INVENTORY | ISO15_REQINV_SLOT1;\r\n\tdata[1]=ISO15_CMD_INVENTORY;\r\n\tdata[2]=0; // mask length\r\n\tdatalen=AddCrc(data,3);\r\n\trecvlen=SendDataTag(data,datalen,0,speed,&recv);\r\n\tWDT_HIT();\r\n\tif (recvlen>=12) {\r\n\t\tDbprintf(\"NoAFI UID=%s\",sprintUID(NULL,&recv[2]));\r\n\t}\r\n\t\r\n\t// now with AFI\r\n\t\r\n\tdata[0]=ISO15_REQ_SUBCARRIER_SINGLE | ISO15_REQ_DATARATE_HIGH | \r\n\t ISO15_REQ_INVENTORY | ISO15_REQINV_AFI | ISO15_REQINV_SLOT1;\r\n\tdata[1]=ISO15_CMD_INVENTORY;\r\n\tdata[2]=0; // AFI\r\n\tdata[3]=0; // mask length\r\n\t\r\n\tfor (int i=0;i<256;i++) {\r\n\t\tdata[2]=i & 0xFF;\r\n\t\tdatalen=AddCrc(data,4);\r\n\t\trecvlen=SendDataTag(data,datalen,0,speed,&recv);\r\n\t\tWDT_HIT();\r\n\t\tif (recvlen>=12) {\r\n\t\t\tDbprintf(\"AFI=%i UID=%s\",i,sprintUID(NULL,&recv[2]));\r\n\t\t}\r\n\t}\t\r\n\tDbprintf(\"AFI Bruteforcing done.\");\r\n\t\r\n}\r\n\r\n// Allows to directly send commands to the tag via the client\r\nvoid DirectTag15693Command(uint32_t datalen,uint32_t speed, uint32_t recv, uint8_t data[]) {\r\n\r\n\tint recvlen=0;\r\n\tuint8_t *recvbuf=(uint8_t *)BigBuf;\r\n//\tUsbCommand n;\r\n\t\r\n\tif (DEBUG) {\r\n\t\tDbprintf(\"SEND\");\r\n\t\tDbhexdump(datalen,data,true);\r\n\t}\r\n\t\r\n\trecvlen=SendDataTag(data,datalen,1,speed,(recv?&recvbuf:NULL));\r\n\r\n\tif (recv) { \r\n//\t\tn.cmd=/* CMD_ISO_15693_COMMAND_DONE */ CMD_ACK;\r\n//\t\tn.arg[0]=recvlen>48?48:recvlen;\r\n//\t\tmemcpy(n.d.asBytes, recvbuf, 48);\r\n\t\tLED_B_ON();\r\n cmd_send(CMD_ACK,recvlen>48?48:recvlen,0,0,recvbuf,48);\r\n//\t\tUsbSendPacket((uint8_t *)&n, sizeof(n));\r\n\t\tLED_B_OFF();\t\r\n\t\t\r\n\t\tif (DEBUG) {\r\n\t\t\tDbprintf(\"RECV\");\r\n\t\t\tDbdecodeIso15693Answer(recvlen,recvbuf); \r\n\t\t\tDbhexdump(recvlen,recvbuf,true);\r\n\t\t}\r\n\t}\r\n\r\n}\r\n\r\n\r\n\r\n\r\n// --------------------------------------------------------------------\r\n// -- Misc & deprecated functions\r\n// --------------------------------------------------------------------\r\n\r\n/*\r\n\r\n// do not use; has a fix UID\r\nstatic void __attribute__((unused)) BuildSysInfoRequest(uint8_t *uid)\r\n{\r\n\tuint8_t cmd[12];\r\n\r\n\tuint16_t crc;\r\n\t// If we set the Option_Flag in this request, the VICC will respond with the secuirty status of the block\r\n\t// followed by teh block data\r\n\t// one sub-carrier, inventory, 1 slot, fast rate\r\n\tcmd[0] = (1 << 5) | (1 << 1); // no SELECT bit\r\n\t// System Information command code\r\n\tcmd[1] = 0x2B;\r\n\t// UID may be optionally specified here\r\n\t// 64-bit UID\r\n\tcmd[2] = 0x32;\r\n\tcmd[3]= 0x4b;\r\n\tcmd[4] = 0x03;\r\n\tcmd[5] = 0x01;\r\n\tcmd[6] = 0x00;\r\n\tcmd[7] = 0x10;\r\n\tcmd[8] = 0x05;\r\n\tcmd[9]= 0xe0; // always e0 (not exactly unique)\r\n\t//Now the CRC\r\n\tcrc = Crc(cmd, 10); // the crc needs to be calculated over 2 bytes\r\n\tcmd[10] = crc & 0xff;\r\n\tcmd[11] = crc >> 8;\r\n\r\n\tCodeIso15693AsReader(cmd, sizeof(cmd));\r\n}\r\n\r\n\r\n// do not use; has a fix UID\r\nstatic void __attribute__((unused)) BuildReadMultiBlockRequest(uint8_t *uid)\r\n{\r\n\tuint8_t cmd[14];\r\n\r\n\tuint16_t crc;\r\n\t// If we set the Option_Flag in this request, the VICC will respond with the secuirty status of the block\r\n\t// followed by teh block data\r\n\t// one sub-carrier, inventory, 1 slot, fast rate\r\n\tcmd[0] = (1 << 5) | (1 << 1); // no SELECT bit\r\n\t// READ Multi BLOCK command code\r\n\tcmd[1] = 0x23;\r\n\t// UID may be optionally specified here\r\n\t// 64-bit UID\r\n\tcmd[2] = 0x32;\r\n\tcmd[3]= 0x4b;\r\n\tcmd[4] = 0x03;\r\n\tcmd[5] = 0x01;\r\n\tcmd[6] = 0x00;\r\n\tcmd[7] = 0x10;\r\n\tcmd[8] = 0x05;\r\n\tcmd[9]= 0xe0; // always e0 (not exactly unique)\r\n\t// First Block number to read\r\n\tcmd[10] = 0x00;\r\n\t// Number of Blocks to read\r\n\tcmd[11] = 0x2f; // read quite a few\r\n\t//Now the CRC\r\n\tcrc = Crc(cmd, 12); // the crc needs to be calculated over 2 bytes\r\n\tcmd[12] = crc & 0xff;\r\n\tcmd[13] = crc >> 8;\r\n\r\n\tCodeIso15693AsReader(cmd, sizeof(cmd));\r\n}\r\n\r\n// do not use; has a fix UID\r\nstatic void __attribute__((unused)) BuildArbitraryRequest(uint8_t *uid,uint8_t CmdCode)\r\n{\r\n\tuint8_t cmd[14];\r\n\r\n\tuint16_t crc;\r\n\t// If we set the Option_Flag in this request, the VICC will respond with the secuirty status of the block\r\n\t// followed by teh block data\r\n\t// one sub-carrier, inventory, 1 slot, fast rate\r\n\tcmd[0] = (1 << 5) | (1 << 1); // no SELECT bit\r\n\t// READ BLOCK command code\r\n\tcmd[1] = CmdCode;\r\n\t// UID may be optionally specified here\r\n\t// 64-bit UID\r\n\tcmd[2] = 0x32;\r\n\tcmd[3]= 0x4b;\r\n\tcmd[4] = 0x03;\r\n\tcmd[5] = 0x01;\r\n\tcmd[6] = 0x00;\r\n\tcmd[7] = 0x10;\r\n\tcmd[8] = 0x05;\r\n\tcmd[9]= 0xe0; // always e0 (not exactly unique)\r\n\t// Parameter\r\n\tcmd[10] = 0x00;\r\n\tcmd[11] = 0x0a;\r\n\r\n//\tcmd[12] = 0x00;\r\n//\tcmd[13] = 0x00;\t//Now the CRC\r\n\tcrc = Crc(cmd, 12); // the crc needs to be calculated over 2 bytes\r\n\tcmd[12] = crc & 0xff;\r\n\tcmd[13] = crc >> 8;\r\n\r\n\tCodeIso15693AsReader(cmd, sizeof(cmd));\r\n}\r\n\r\n// do not use; has a fix UID\r\nstatic void __attribute__((unused)) BuildArbitraryCustomRequest(uint8_t uid[], uint8_t CmdCode)\r\n{\r\n\tuint8_t cmd[14];\r\n\r\n\tuint16_t crc;\r\n\t// If we set the Option_Flag in this request, the VICC will respond with the secuirty status of the block\r\n\t// followed by teh block data\r\n\t// one sub-carrier, inventory, 1 slot, fast rate\r\n\tcmd[0] = (1 << 5) | (1 << 1); // no SELECT bit\r\n\t// READ BLOCK command code\r\n\tcmd[1] = CmdCode;\r\n\t// UID may be optionally specified here\r\n\t// 64-bit UID\r\n\tcmd[2] = 0x32;\r\n\tcmd[3]= 0x4b;\r\n\tcmd[4] = 0x03;\r\n\tcmd[5] = 0x01;\r\n\tcmd[6] = 0x00;\r\n\tcmd[7] = 0x10;\r\n\tcmd[8] = 0x05;\r\n\tcmd[9]= 0xe0; // always e0 (not exactly unique)\r\n\t// Parameter\r\n\tcmd[10] = 0x05; // for custom codes this must be manufcturer code\r\n\tcmd[11] = 0x00;\r\n\r\n//\tcmd[12] = 0x00;\r\n//\tcmd[13] = 0x00;\t//Now the CRC\r\n\tcrc = Crc(cmd, 12); // the crc needs to be calculated over 2 bytes\r\n\tcmd[12] = crc & 0xff;\r\n\tcmd[13] = crc >> 8;\r\n\r\n\tCodeIso15693AsReader(cmd, sizeof(cmd));\r\n}\r\n\r\n\r\n\r\n\r\n*/\r\n\r\n\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/ldscript", "content": "/*\r\n-----------------------------------------------------------------------------\r\n This code is licensed to you under the terms of the GNU GPL, version 2 or,\r\n at your option, any later version. See the LICENSE.txt file for the text of\r\n the license.\r\n-----------------------------------------------------------------------------\r\n Linker script for the ARM binary\r\n-----------------------------------------------------------------------------\r\n*/\r\nINCLUDE ../common/ldscript.common\r\n\r\nPHDRS\r\n{\r\n\tfpgaimage PT_LOAD FLAGS(4);\r\n\ttext PT_LOAD;\r\n\tdata PT_LOAD;\r\n\tbss PT_LOAD;\r\n}\r\n\r\nENTRY(Vector)\r\nSECTIONS\r\n{\r\n\t.fpgaimage : {\r\n\t\t*(fpga_bit.data)\r\n\t} >fpgaimage :fpgaimage\r\n\r\n\t.start : {\r\n\t\t*(.startos)\r\n\t} >osimage :text\r\n\r\n\t.text : {\r\n\t\t*(.text)\r\n\t\t*(.text.*)\r\n\t\t*(.eh_frame)\r\n\t\t*(.glue_7)\r\n\t\t*(.glue_7t)\r\n\t} >osimage :text\r\n\r\n\t.rodata : {\r\n\t\t*(.rodata)\r\n\t\t*(.rodata.*)\r\n\t\tKEEP(*(.version_information))\r\n\t} >osimage :text\r\n\r\n\t. = ALIGN(4);\r\n\r\n\t.data : {\r\n\t\t*(.data)\r\n\t\t*(.data.*)\r\n\t\t*(.ramfunc)\r\n\t\t. = ALIGN(4);\r\n\t} >ram AT>osimage :data\r\n\r\n\t__data_src_start__ = LOADADDR(.data);\r\n\t__data_start__ = ADDR(.data);\r\n\t__data_end__ = __data_start__ + SIZEOF(.data);\r\n\t\r\n\t.bss : {\r\n\t\t__bss_start__ = .; \r\n\t\t*(.bss)\r\n\t\t*(.bss.*) \r\n\t\t. = ALIGN(4);\r\n\t\t__bss_end__ = .;\r\n\t} >ram AT>ram :bss\r\n\r\n\t.commonarea (NOLOAD) : {\r\n\t\t*(.commonarea)\r\n\t} >commonarea :NONE\r\n}\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/legicrf.c", "content": "//-----------------------------------------------------------------------------\r\n// (c) 2009 Henryk Plötz \r\n//\r\n// This code is licensed to you under the terms of the GNU GPL, version 2 or,\r\n// at your option, any later version. See the LICENSE.txt file for the text of\r\n// the license.\r\n//-----------------------------------------------------------------------------\r\n// LEGIC RF simulation code\r\n//-----------------------------------------------------------------------------\r\n\r\n#include \"proxmark3.h\"\r\n#include \"apps.h\"\r\n#include \"util.h\"\r\n#include \"string.h\"\r\n\r\n#include \"legicrf.h\"\r\n#include \"legic_prng.h\"\r\n#include \"crc.h\"\r\n\r\nstatic struct legic_frame {\r\n\tint bits;\r\n\tuint32_t data;\r\n} current_frame;\r\n\r\nstatic enum {\r\n STATE_DISCON,\r\n STATE_IV,\r\n STATE_CON,\r\n} legic_state;\r\n\r\nstatic crc_t legic_crc;\r\nstatic int legic_read_count;\r\nstatic uint32_t legic_prng_bc;\r\nstatic uint32_t legic_prng_iv;\r\n\r\nstatic int legic_phase_drift;\r\nstatic int legic_frame_drift;\r\nstatic int legic_reqresp_drift;\r\n\r\nAT91PS_TC timer;\r\nAT91PS_TC prng_timer;\r\n\r\nstatic void setup_timer(void)\r\n{\r\n\t/* Set up Timer 1 to use for measuring time between pulses. Since we're bit-banging\r\n\t * this it won't be terribly accurate but should be good enough.\r\n\t */\r\n\tAT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);\r\n\ttimer = AT91C_BASE_TC1;\r\n\ttimer->TC_CCR = AT91C_TC_CLKDIS;\r\n\ttimer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK;\r\n\ttimer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;\r\n\r\n\t/* \r\n * Set up Timer 2 to use for measuring time between frames in \r\n * tag simulation mode. Runs 4x faster as Timer 1\r\n\t */\r\n AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC2);\r\n prng_timer = AT91C_BASE_TC2;\r\n prng_timer->TC_CCR = AT91C_TC_CLKDIS;\r\n\tprng_timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV2_CLOCK;\r\n prng_timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;\r\n}\r\n\r\n/* At TIMER_CLOCK3 (MCK/32) */\r\n#define\tRWD_TIME_1 150 /* RWD_TIME_PAUSE off, 80us on = 100us */\r\n#define RWD_TIME_0 90 /* RWD_TIME_PAUSE off, 40us on = 60us */\r\n#define RWD_TIME_PAUSE 30 /* 20us */\r\n#define RWD_TIME_FUZZ 20 /* rather generous 13us, since the peak detector + hysteresis fuzz quite a bit */\r\n#define TAG_TIME_BIT 150 /* 100us for every bit */\r\n#define TAG_TIME_WAIT 490 /* time from RWD frame end to tag frame start, experimentally determined */\r\n\r\n#define SIM_DIVISOR 586 /* prng_time/SIM_DIVISOR count prng needs to be forwared */\r\n#define SIM_SHIFT 900 /* prng_time+SIM_SHIFT shift of delayed start */\r\n\r\n#define SESSION_IV 0x55\r\n#define OFFSET_LOG 1024\r\n\r\n#define FUZZ_EQUAL(value, target, fuzz) ((value) > ((target)-(fuzz)) && (value) < ((target)+(fuzz)))\r\n\r\n/* Generate Keystream */\r\nstatic uint32_t get_key_stream(int skip, int count)\r\n{\r\n uint32_t key=0; int i;\r\n\r\n /* Use int to enlarge timer tc to 32bit */\r\n legic_prng_bc += prng_timer->TC_CV;\r\n prng_timer->TC_CCR = AT91C_TC_SWTRG;\r\n\r\n /* If skip == -1, forward prng time based */\r\n if(skip == -1) {\r\n i = (legic_prng_bc+SIM_SHIFT)/SIM_DIVISOR; /* Calculate Cycles based on timer */\r\n i -= legic_prng_count(); /* substract cycles of finished frames */\r\n i -= count; /* substract current frame length, rewidn to bedinning */\r\n legic_prng_forward(i);\r\n } else {\r\n legic_prng_forward(skip);\r\n }\r\n\r\n /* Write Time Data into LOG */\r\n if(count == 6) { i = -1; } else { i = legic_read_count; }\r\n ((uint8_t*)BigBuf)[OFFSET_LOG+128+i] = legic_prng_count();\r\n ((uint8_t*)BigBuf)[OFFSET_LOG+256+i*4] = (legic_prng_bc >> 0) & 0xff;\r\n ((uint8_t*)BigBuf)[OFFSET_LOG+256+i*4+1] = (legic_prng_bc >> 8) & 0xff;\r\n ((uint8_t*)BigBuf)[OFFSET_LOG+256+i*4+2] = (legic_prng_bc >>16) & 0xff;\r\n ((uint8_t*)BigBuf)[OFFSET_LOG+256+i*4+3] = (legic_prng_bc >>24) & 0xff;\r\n ((uint8_t*)BigBuf)[OFFSET_LOG+384+i] = count;\r\n\r\n /* Generate KeyStream */\r\n for(i=0; iPIO_CODR = GPIO_SSC_DOUT;\r\n AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r\n AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;\r\n \r\n /* Use time to crypt frame */\r\n if(crypt) {\r\n legic_prng_forward(2); /* TAG_TIME_WAIT -> shift by 2 */\r\n int i; int key = 0;\r\n for(i=0; iTC_CV < (TAG_TIME_WAIT - 30)) ;\r\n \r\n int i;\r\n for(i=0; iTC_CV + TAG_TIME_BIT;\r\n int bit = response & 1;\r\n response = response >> 1;\r\n if(bit) {\r\n AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT;\r\n } else {\r\n AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;\r\n }\r\n while(timer->TC_CV < nextbit) ;\r\n }\r\n AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;\r\n}\r\n\r\n/* Send a frame in reader mode, the FPGA must have been set up by\r\n * LegicRfReader\r\n */\r\nstatic void frame_send_rwd(uint32_t data, int bits)\r\n{\r\n\t/* Start clock */\r\n\ttimer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;\r\n\twhile(timer->TC_CV > 1) ; /* Wait till the clock has reset */\r\n\r\n\tint i;\r\n\tfor(i=0; iTC_CV;\r\n\t\tint pause_end = starttime + RWD_TIME_PAUSE, bit_end;\r\n\t\tint bit = data & 1;\r\n\t\tdata = data >> 1;\r\n\r\n\t\tif(bit ^ legic_prng_get_bit()) {\r\n\t\t\tbit_end = starttime + RWD_TIME_1;\r\n\t\t} else {\r\n\t\t\tbit_end = starttime + RWD_TIME_0;\r\n\t\t}\r\n\r\n\t\t/* RWD_TIME_PAUSE time off, then some time on, so that the complete bit time is\r\n\t\t * RWD_TIME_x, where x is the bit to be transmitted */\r\n\t\tAT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;\r\n\t\twhile(timer->TC_CV < pause_end) ;\r\n\t\tAT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT;\r\n\t\tlegic_prng_forward(1); /* bit duration is longest. use this time to forward the lfsr */\r\n\r\n\t\twhile(timer->TC_CV < bit_end) ;\r\n\t}\r\n\r\n\t{\r\n\t\t/* One final pause to mark the end of the frame */\r\n\t\tint pause_end = timer->TC_CV + RWD_TIME_PAUSE;\r\n\t\tAT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;\r\n\t\twhile(timer->TC_CV < pause_end) ;\r\n\t\tAT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT;\r\n\t}\r\n\r\n\t/* Reset the timer, to measure time until the start of the tag frame */\r\n\ttimer->TC_CCR = AT91C_TC_SWTRG;\r\n\twhile(timer->TC_CV > 1) ; /* Wait till the clock has reset */\r\n}\r\n\r\n/* Receive a frame from the card in reader emulation mode, the FPGA and\r\n * timer must have been set up by LegicRfReader and frame_send_rwd.\r\n *\r\n * The LEGIC RF protocol from card to reader does not include explicit\r\n * frame start/stop information or length information. The reader must\r\n * know beforehand how many bits it wants to receive. (Notably: a card\r\n * sending a stream of 0-bits is indistinguishable from no card present.)\r\n *\r\n * Receive methodology: There is a fancy correlator in hi_read_rx_xcorr, but\r\n * I'm not smart enough to use it. Instead I have patched hi_read_tx to output\r\n * the ADC signal with hysteresis on SSP_DIN. Bit-bang that signal and look\r\n * for edges. Count the edges in each bit interval. If they are approximately\r\n * 0 this was a 0-bit, if they are approximately equal to the number of edges\r\n * expected for a 212kHz subcarrier, this was a 1-bit. For timing we use the\r\n * timer that's still running from frame_send_rwd in order to get a synchronization\r\n * with the frame that we just sent.\r\n *\r\n * FIXME: Because we're relying on the hysteresis to just do the right thing\r\n * the range is severely reduced (and you'll probably also need a good antenna).\r\n * So this should be fixed some time in the future for a proper receiver.\r\n */\r\nstatic void frame_receive_rwd(struct legic_frame * const f, int bits, int crypt)\r\n{\r\n\tuint32_t the_bit = 1; /* Use a bitmask to save on shifts */\r\n\tuint32_t data=0;\r\n\tint i, old_level=0, edges=0;\r\n\tint next_bit_at = TAG_TIME_WAIT;\r\n\t\r\n\tif(bits > 32) {\r\n\t\tbits = 32;\r\n }\r\n\r\n\tAT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;\r\n\tAT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;\r\n\r\n\t/* we have some time now, precompute the cipher\r\n * since we cannot compute it on the fly while reading */\r\n\tlegic_prng_forward(2);\r\n\r\n\tif(crypt)\r\n\t{\r\n\t\tfor(i=0; iTC_CV < next_bit_at) ;\r\n\r\n\tnext_bit_at += TAG_TIME_BIT;\r\n\r\n\tfor(i=0; iTC_CV < next_bit_at) {\r\n\t\t\tint level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);\r\n\t\t\tif(level != old_level)\r\n\t\t\t\tedges++;\r\n\t\t\told_level = level;\r\n\t\t}\r\n\t\tnext_bit_at += TAG_TIME_BIT;\r\n\t\t\r\n\t\tif(edges > 20 && edges < 60) { /* expected are 42 edges */\r\n\t\t\tdata ^= the_bit;\r\n\t\t}\r\n\t\tthe_bit <<= 1;\r\n\t}\r\n\r\n\tf->data = data;\r\n\tf->bits = bits;\r\n\r\n\t/* Reset the timer, to synchronize the next frame */\r\n\ttimer->TC_CCR = AT91C_TC_SWTRG;\r\n\twhile(timer->TC_CV > 1) ; /* Wait till the clock has reset */\r\n}\r\n\r\nstatic void frame_append_bit(struct legic_frame * const f, int bit)\r\n{\r\n if(f->bits >= 31) {\r\n return; /* Overflow, won't happen */\r\n }\r\n f->data |= (bit<bits);\r\n f->bits++;\r\n}\r\n\r\nstatic void frame_clean(struct legic_frame * const f)\r\n{\r\n\tf->data = 0;\r\n\tf->bits = 0;\r\n}\r\n\r\nstatic uint32_t perform_setup_phase_rwd(int iv)\r\n{\r\n\r\n\t/* Switch on carrier and let the tag charge for 1ms */\r\n\tAT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT;\r\n\tSpinDelay(1);\r\n\r\n\tlegic_prng_init(0); /* no keystream yet */\r\n\tframe_send_rwd(iv, 7);\r\n\tlegic_prng_init(iv);\r\n\r\n\tframe_clean(¤t_frame);\r\n\tframe_receive_rwd(¤t_frame, 6, 1);\r\n\tlegic_prng_forward(1); /* we wait anyways */\r\n\twhile(timer->TC_CV < 387) ; /* ~ 258us */\r\n\tframe_send_rwd(0x19, 6);\r\n\r\n\treturn current_frame.data;\r\n}\r\n\r\nstatic void LegicCommonInit(void) {\r\n\tSetAdcMuxFor(GPIO_MUXSEL_HIPKD);\r\n\tFpgaSetupSsc();\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX);\r\n\r\n\t/* Bitbang the transmitter */\r\n\tAT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;\r\n\tAT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r\n\tAT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;\r\n\r\n\tsetup_timer();\r\n\r\n\tcrc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);\r\n}\r\n\r\nstatic void switch_off_tag_rwd(void)\r\n{\r\n\t/* Switch off carrier, make sure tag is reset */\r\n\tAT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;\r\n\tSpinDelay(10);\r\n\r\n\tWDT_HIT();\r\n}\r\n/* calculate crc for a legic command */\r\nstatic int LegicCRC(int byte_index, int value, int cmd_sz) {\r\n\tcrc_clear(&legic_crc);\r\n\tcrc_update(&legic_crc, 1, 1); /* CMD_READ */\r\n\tcrc_update(&legic_crc, byte_index, cmd_sz-1);\r\n\tcrc_update(&legic_crc, value, 8);\r\n\treturn crc_finish(&legic_crc);\r\n}\r\n\r\nint legic_read_byte(int byte_index, int cmd_sz) {\r\n\tint byte;\r\n\r\n\tlegic_prng_forward(4); /* we wait anyways */\r\n\twhile(timer->TC_CV < 387) ; /* ~ 258us + 100us*delay */\r\n\r\n\tframe_send_rwd(1 | (byte_index << 1), cmd_sz);\r\n\tframe_clean(¤t_frame);\r\n\r\n\tframe_receive_rwd(¤t_frame, 12, 1);\r\n\r\n\tbyte = current_frame.data & 0xff;\r\n\tif( LegicCRC(byte_index, byte, cmd_sz) != (current_frame.data >> 8) ) {\r\n\t\tDbprintf(\"!!! crc mismatch: expected %x but got %x !!!\", \r\n LegicCRC(byte_index, current_frame.data & 0xff, cmd_sz), current_frame.data >> 8);\r\n\t\treturn -1;\r\n\t}\r\n\r\n\treturn byte;\r\n}\r\n\r\n/* legic_write_byte() is not included, however it's trivial to implement\r\n * and here are some hints on what remains to be done:\r\n *\r\n * * assemble a write_cmd_frame with crc and send it\r\n * * wait until the tag sends back an ACK ('1' bit unencrypted)\r\n * * forward the prng based on the timing\r\n */\r\nint legic_write_byte(int byte, int addr, int addr_sz) {\r\n //do not write UID, CRC, DCF\r\n if(addr <= 0x06) { \r\n\t\treturn 0;\r\n\t}\r\n\r\n\t//== send write command ==============================\r\n\tcrc_clear(&legic_crc);\r\n\tcrc_update(&legic_crc, 0, 1); /* CMD_WRITE */\r\n\tcrc_update(&legic_crc, addr, addr_sz);\r\n\tcrc_update(&legic_crc, byte, 8);\r\n\r\n\tuint32_t crc = crc_finish(&legic_crc);\r\n\tuint32_t cmd = ((crc <<(addr_sz+1+8)) //CRC\r\n |(byte <<(addr_sz+1)) //Data\r\n |(addr <<1) //Address\r\n |(0x00 <<0)); //CMD = W\r\n uint32_t cmd_sz = addr_sz+1+8+4; //crc+data+cmd\r\n\r\n legic_prng_forward(2); /* we wait anyways */\r\n while(timer->TC_CV < 387) ; /* ~ 258us */\r\n\tframe_send_rwd(cmd, cmd_sz);\r\n\r\n\t//== wait for ack ====================================\r\n int t, old_level=0, edges=0;\r\n int next_bit_at =0;\r\n\twhile(timer->TC_CV < 387) ; /* ~ 258us */\r\n for(t=0; t<80; t++) {\r\n edges = 0;\r\n\t\tnext_bit_at += TAG_TIME_BIT;\r\n while(timer->TC_CV < next_bit_at) {\r\n int level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);\r\n if(level != old_level) {\r\n edges++;\r\n\t\t\t}\r\n old_level = level;\r\n }\r\n if(edges > 20 && edges < 60) { /* expected are 42 edges */\r\n\t\t\tint t = timer->TC_CV;\r\n\t\t\tint c = t/TAG_TIME_BIT;\r\n\t\t\ttimer->TC_CCR = AT91C_TC_SWTRG;\r\n\t\t\twhile(timer->TC_CV > 1) ; /* Wait till the clock has reset */\r\n\t\t\tlegic_prng_forward(c);\r\n \treturn 0;\r\n }\r\n }\r\n timer->TC_CCR = AT91C_TC_SWTRG;\r\n while(timer->TC_CV > 1) ; /* Wait till the clock has reset */\r\n\treturn -1;\r\n}\r\n\r\nint LegicRfReader(int offset, int bytes) {\r\n\tint byte_index=0, cmd_sz=0, card_sz=0;\r\n\r\n\tLegicCommonInit();\r\n\r\n\tmemset(BigBuf, 0, 1024);\r\n\r\n\tDbpString(\"setting up legic card\");\r\n\tuint32_t tag_type = perform_setup_phase_rwd(SESSION_IV);\r\n\tswitch_off_tag_rwd(); //we lose to mutch time with dprintf\r\n\tswitch(tag_type) {\r\n\t\tcase 0x1d:\r\n\t\t\tDbpString(\"MIM 256 card found, reading card ...\");\r\n cmd_sz = 9;\r\n\t\t\tcard_sz = 256;\r\n\t\t\tbreak;\r\n\t\tcase 0x3d:\r\n\t\t\tDbpString(\"MIM 1024 card found, reading card ...\");\r\n cmd_sz = 11;\r\n\t\t\tcard_sz = 1024;\r\n\t\t\tbreak;\r\n\t\tdefault:\r\n\t\t\tDbprintf(\"Unknown card format: %x\",tag_type);\r\n\t\t\treturn -1;\r\n\t}\r\n\tif(bytes == -1) {\r\n\t\tbytes = card_sz;\r\n\t}\r\n\tif(bytes+offset >= card_sz) {\r\n\t\tbytes = card_sz-offset;\r\n\t}\r\n\r\n\tperform_setup_phase_rwd(SESSION_IV);\r\n\r\n\tLED_B_ON();\r\n\twhile(byte_index < bytes) {\r\n\t\tint r = legic_read_byte(byte_index+offset, cmd_sz);\r\n\t\tif(r == -1 ||BUTTON_PRESS()) {\r\n \tDbpString(\"operation aborted\");\r\n \t\t\tswitch_off_tag_rwd();\r\n\t LED_B_OFF();\r\n \t\tLED_C_OFF();\r\n\t return -1;\r\n\t\t}\r\n\t\t((uint8_t*)BigBuf)[byte_index] = r;\r\n WDT_HIT();\r\n\t\tbyte_index++;\r\n\t\tif(byte_index & 0x10) LED_C_ON(); else LED_C_OFF();\r\n\t}\r\n\tLED_B_OFF();\r\n LED_C_OFF();\r\n\tswitch_off_tag_rwd();\r\n\tDbprintf(\"Card read, use 'hf legic decode' or\");\r\n Dbprintf(\"'data hexsamples %d' to view results\", (bytes+7) & ~7);\r\n return 0;\r\n}\r\n\r\nvoid LegicRfWriter(int bytes, int offset) {\r\n\tint byte_index=0, addr_sz=0;\r\n\t\r\n\tLegicCommonInit();\r\n\t\r\n\tDbpString(\"setting up legic card\");\r\n\tuint32_t tag_type = perform_setup_phase_rwd(SESSION_IV);\r\n\tswitch_off_tag_rwd();\r\n\tswitch(tag_type) {\r\n\t\tcase 0x1d:\r\n\t\t\tif(offset+bytes > 0x100) {\r\n\t\t\t\tDbprintf(\"Error: can not write to 0x%03.3x on MIM 256\", offset+bytes);\r\n\t\t\t\treturn;\r\n\t\t\t}\r\n\t\t\taddr_sz = 8;\r\n\t\t\tDbprintf(\"MIM 256 card found, writing 0x%02.2x - 0x%02.2x ...\", offset, offset+bytes);\r\n\t\t\tbreak;\r\n\t\tcase 0x3d:\r\n\t\t\tif(offset+bytes > 0x400) {\r\n \t\tDbprintf(\"Error: can not write to 0x%03.3x on MIM 1024\", offset+bytes);\r\n \t\treturn;\r\n \t}\r\n\t\t\taddr_sz = 10;\r\n\t\t\tDbprintf(\"MIM 1024 card found, writing 0x%03.3x - 0x%03.3x ...\", offset, offset+bytes);\r\n\t\t\tbreak;\r\n\t\tdefault:\r\n\t\t\tDbprintf(\"No or unknown card found, aborting\");\r\n return;\r\n\t}\r\n\r\n LED_B_ON();\r\n\tperform_setup_phase_rwd(SESSION_IV);\r\n legic_prng_forward(2);\r\n\twhile(byte_index < bytes) {\r\n\t\tint r = legic_write_byte(((uint8_t*)BigBuf)[byte_index+offset], byte_index+offset, addr_sz);\r\n\t\tif((r != 0) || BUTTON_PRESS()) {\r\n\t\t\tDbprintf(\"operation aborted @ 0x%03.3x\", byte_index);\r\n\t\t\tswitch_off_tag_rwd();\r\n\t\t\tLED_B_OFF();\r\n\t\t\tLED_C_OFF();\r\n\t\t\treturn;\r\n\t\t}\r\n WDT_HIT();\r\n\t\tbyte_index++;\r\n if(byte_index & 0x10) LED_C_ON(); else LED_C_OFF();\r\n\t}\r\n LED_B_OFF();\r\n LED_C_OFF();\r\n DbpString(\"write successful\");\r\n}\r\n\r\nint timestamp;\r\n\r\n/* Handle (whether to respond) a frame in tag mode */\r\nstatic void frame_handle_tag(struct legic_frame const * const f)\r\n{\r\n /* First Part of Handshake (IV) */\r\n if(f->bits == 7) {\r\n if(f->data == SESSION_IV) {\r\n LED_C_ON();\r\n prng_timer->TC_CCR = AT91C_TC_SWTRG;\r\n legic_prng_init(f->data);\r\n frame_send_tag(0x3d, 6, 1); /* 0x3d^0x26 = 0x1b */\r\n legic_state = STATE_IV;\r\n legic_read_count = 0;\r\n legic_prng_bc = 0;\r\n legic_prng_iv = f->data;\r\n \r\n /* TIMEOUT */\r\n timer->TC_CCR = AT91C_TC_SWTRG;\r\n while(timer->TC_CV > 1);\r\n while(timer->TC_CV < 280);\r\n return;\r\n } else if((prng_timer->TC_CV % 50) > 40) {\r\n legic_prng_init(f->data);\r\n frame_send_tag(0x3d, 6, 1);\r\n SpinDelay(20);\r\n return;\r\n }\r\n }\r\n\r\n /* 0x19==??? */\r\n if(legic_state == STATE_IV) {\r\n if((f->bits == 6) && (f->data == (0x19 ^ get_key_stream(1, 6)))) {\r\n legic_state = STATE_CON;\r\n\r\n /* TIMEOUT */\r\n timer->TC_CCR = AT91C_TC_SWTRG;\r\n while(timer->TC_CV > 1);\r\n while(timer->TC_CV < 200);\r\n return;\r\n } else {\r\n legic_state = STATE_DISCON;\r\n LED_C_OFF();\r\n Dbprintf(\"0x19 - Frame: %03.3x\", f->data);\r\n return;\r\n }\r\n }\r\n\r\n /* Read */\r\n if(f->bits == 11) {\r\n if(legic_state == STATE_CON) {\r\n int key = get_key_stream(-1, 11); //legic_phase_drift, 11);\r\n int addr = f->data ^ key; addr = addr >> 1;\r\n int data = ((uint8_t*)BigBuf)[addr];\r\n int hash = LegicCRC(addr, data, 11) << 8;\r\n ((uint8_t*)BigBuf)[OFFSET_LOG+legic_read_count] = (uint8_t)addr;\r\n legic_read_count++;\r\n\r\n //Dbprintf(\"Data:%03.3x, key:%03.3x, addr: %03.3x, read_c:%u\", f->data, key, addr, read_c);\r\n legic_prng_forward(legic_reqresp_drift);\r\n\r\n frame_send_tag(hash | data, 12, 1);\r\n\r\n /* SHORT TIMEOUT */\r\n timer->TC_CCR = AT91C_TC_SWTRG;\r\n while(timer->TC_CV > 1);\r\n legic_prng_forward(legic_frame_drift);\r\n while(timer->TC_CV < 180);\r\n return;\r\n }\r\n }\r\n\r\n /* Write */\r\n if(f->bits == 23) {\r\n int key = get_key_stream(-1, 23); //legic_frame_drift, 23);\r\n int addr = f->data ^ key; addr = addr >> 1; addr = addr & 0x3ff;\r\n int data = f->data ^ key; data = data >> 11; data = data & 0xff;\r\n\r\n /* write command */\r\n legic_state = STATE_DISCON;\r\n LED_C_OFF();\r\n Dbprintf(\"write - addr: %x, data: %x\", addr, data);\r\n return;\r\n }\r\n\r\n if(legic_state != STATE_DISCON) {\r\n Dbprintf(\"Unexpected: sz:%u, Data:%03.3x, State:%u, Count:%u\", f->bits, f->data, legic_state, legic_read_count);\r\n int i;\r\n Dbprintf(\"IV: %03.3x\", legic_prng_iv);\r\n for(i = 0; iPIO_ODR = GPIO_SSC_DIN;\r\n AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;\r\n \r\n setup_timer();\r\n crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);\r\n \r\n int old_level = 0;\r\n int active = 0;\r\n legic_state = STATE_DISCON;\r\n\r\n LED_B_ON();\r\n DbpString(\"Starting Legic emulator, press button to end\");\r\n while(!BUTTON_PRESS()) {\r\n int level = !!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);\r\n int time = timer->TC_CV;\r\n \r\n if(level != old_level) {\r\n if(level == 1) {\r\n timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;\r\n if(FUZZ_EQUAL(time, RWD_TIME_1, RWD_TIME_FUZZ)) {\r\n /* 1 bit */\r\n emit(1);\r\n active = 1;\r\n LED_A_ON();\r\n } else if(FUZZ_EQUAL(time, RWD_TIME_0, RWD_TIME_FUZZ)) {\r\n /* 0 bit */\r\n emit(0);\r\n active = 1;\r\n LED_A_ON();\r\n } else if(active) {\r\n /* invalid */\r\n emit(-1);\r\n active = 0;\r\n LED_A_OFF();\r\n }\r\n }\r\n }\r\n\r\n if(time >= (RWD_TIME_1+RWD_TIME_FUZZ) && active) {\r\n /* Frame end */\r\n emit(-1);\r\n active = 0;\r\n LED_A_OFF();\r\n }\r\n \r\n if(time >= (20*RWD_TIME_1) && (timer->TC_SR & AT91C_TC_CLKSTA)) {\r\n timer->TC_CCR = AT91C_TC_CLKDIS;\r\n }\r\n \r\n old_level = level;\r\n WDT_HIT();\r\n }\r\n DbpString(\"Stopped\");\r\n LED_B_OFF();\r\n LED_A_OFF();\r\n LED_C_OFF();\r\n}\r\n\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/legicrf.h", "content": "//-----------------------------------------------------------------------------\r\n// (c) 2009 Henryk Plötz \r\n//\r\n// This code is licensed to you under the terms of the GNU GPL, version 2 or,\r\n// at your option, any later version. See the LICENSE.txt file for the text of\r\n// the license.\r\n//-----------------------------------------------------------------------------\r\n// LEGIC RF emulation public interface\r\n//-----------------------------------------------------------------------------\r\n\r\n#ifndef __LEGICRF_H\r\n#define __LEGICRF_H\r\n\r\nextern void LegicRfSimulate(int phase, int frame, int reqresp);\r\nextern int LegicRfReader(int bytes, int offset);\r\nextern void LegicRfWriter(int bytes, int offset);\r\n\r\n#endif /* __LEGICRF_H */\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/lfops.c", "content": "//-----------------------------------------------------------------------------\r\n// This code is licensed to you under the terms of the GNU GPL, version 2 or,\r\n// at your option, any later version. See the LICENSE.txt file for the text of\r\n// the license.\r\n//-----------------------------------------------------------------------------\r\n// Miscellaneous routines for low frequency tag operations.\r\n// Tags supported here so far are Texas Instruments (TI), HID\r\n// Also routines for raw mode reading/simulating of LF waveform\r\n//-----------------------------------------------------------------------------\r\n\r\n#include \"proxmark3.h\"\r\n#include \"apps.h\"\r\n#include \"util.h\"\r\n#include \"hitag2.h\"\r\n#include \"crc16.h\"\r\n#include \"string.h\"\r\n\r\nvolatile unsigned long timer0_millis = 0; \r\nvoid AcquireRawAdcSamples125k(int at134khz)\r\n\r\n\r\n{\r\n\r\n\r\n\tif (at134khz)\r\n\t\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r\n\telse\r\n\t\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 94); //125Khz\r\n\r\n\tAcquireTiType();\r\n}\r\n\r\n\r\n\r\n// split into two routines so we can avoid timing issues after sending commands //\r\nvoid DoAcquisition125k(void)\r\n{\r\n\tuint8_t *dest = (uint8_t *)BigBuf;\r\n\tint n = sizeof(BigBuf);\r\n\tint i;\r\n\r\n\tmemset(dest, 0, n);\r\n\ti = 0;\r\n\tfor(;;) {\r\n\t\tif (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {\r\n\t\t\tAT91C_BASE_SSC->SSC_THR = 0x43;\r\n\t\t\tLED_D_ON();\r\n\t\t}\r\n\t\tif (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {\r\n\t\t\tdest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;\r\n\t\t\ti++;\r\n\t\t\tLED_D_OFF();\r\n\t\t\tif (i >= n) break;\r\n\t\t}\r\n\t}\r\n\tDbprintf(\"buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...\",\r\n\t\t\tdest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);\r\n}\r\n\r\nvoid ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)\r\n{\r\n\tint at134khz;\r\n\r\n\t/* Make sure the tag is reset */\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\tSpinDelay(2500);\r\n\r\n\t// see if 'h' was specified\r\n\tif (command[strlen((char *) command) - 1] == 'h')\r\n\t\tat134khz = TRUE;\r\n\telse\r\n\t\tat134khz = FALSE;\r\n\r\n\tif (at134khz)\r\n\t\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r\n\telse\r\n\t\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r\n\r\n\t////FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r\n\r\n\t// Give it a bit of time for the resonant antenna to settle.\r\n\tSpinDelay(50);\r\n\t// And a little more time for the tag to fully power up\r\n\tSpinDelay(2000);\r\n\r\n\t// Now set up the SSC to get the ADC samples that are now streaming at us.\r\n\tFpgaSetupSsc();\r\n\r\n\t// now modulate the reader field\r\n\twhile(*command != '\\0' && *command != ' ') {\r\n\t\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\t\tLED_D_OFF();\r\n\t\tSpinDelayUs(delay_off);\r\n\t\tif (at134khz)\r\n\t\t\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r\n\t\telse\r\n\t\t\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r\n\r\n\t\t////FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r\n\t\tLED_D_ON();\r\n\t\tif(*(command++) == '0')\r\n\t\t\tSpinDelayUs(period_0);\r\n\t\telse\r\n\t\t\tSpinDelayUs(period_1);\r\n\t}\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\tLED_D_OFF();\r\n\tSpinDelayUs(delay_off);\r\n\tif (at134khz)\r\n\t\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r\n\telse\r\n\t\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r\n\r\n\t////FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r\n\r\n\t// now do the read\r\n\tDoAcquisition125k();\r\n}\r\n\r\n/* blank r/w tag data stream\r\n...0000000000000000 01111111\r\n1010101010101010101010101010101010101010101010101010101010101010\r\n0011010010100001\r\n01111111\r\n101010101010101[0]000...\r\n\r\n[5555fe852c5555555555555555fe0000]\r\n*/\r\nvoid ReadTItag(void)\r\n{\r\n\t// some hardcoded initial params\r\n\t// when we read a TI tag we sample the zerocross line at 2Mhz\r\n\t// TI tags modulate a 1 as 16 cycles of 123.2Khz\r\n\t// TI tags modulate a 0 as 16 cycles of 134.2Khz\r\n\t#define FSAMPLE 2000000\r\n\t#define FREQLO 123200\r\n\t#define FREQHI 134200\r\n\r\n\tsigned char *dest = (signed char *)BigBuf;\r\n\tint n = sizeof(BigBuf);\r\n//\tint *dest = GraphBuffer;\r\n//\tint n = GraphTraceLen;\r\n\r\n\t// 128 bit shift register [shift3:shift2:shift1:shift0]\r\n\tuint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;\r\n\r\n\tint i, cycles=0, samples=0;\r\n\t// how many sample points fit in 16 cycles of each frequency\r\n\tuint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;\r\n\t// when to tell if we're close enough to one freq or another\r\n\tuint32_t threshold = (sampleslo - sampleshi + 1)>>1;\r\n\r\n\t// TI tags charge at 134.2Khz\r\n\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 94); //134.8Khz\r\n\r\n\t// Place FPGA in passthrough mode, in this mode the CROSS_LO line\r\n\t// connects to SSP_DIN and the SSP_DOUT logic level controls\r\n\t// whether we're modulating the antenna (high)\r\n\t// or listening to the antenna (low)\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);\r\n\r\n\t// get TI tag data into the buffer\r\n\tAcquireTiType();\r\n\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\r\n\tfor (i=0; i0) ) {\r\n\t\t\tcycles++;\r\n\t\t\t// after 16 cycles, measure the frequency\r\n\t\t\tif (cycles>15) {\r\n\t\t\t\tcycles=0;\r\n\t\t\t\tsamples=i-samples; // number of samples in these 16 cycles\r\n\r\n\t\t\t\t// TI bits are coming to us lsb first so shift them\r\n\t\t\t\t// right through our 128 bit right shift register\r\n\t\t\t shift0 = (shift0>>1) | (shift1 << 31);\r\n\t\t\t shift1 = (shift1>>1) | (shift2 << 31);\r\n\t\t\t shift2 = (shift2>>1) | (shift3 << 31);\r\n\t\t\t shift3 >>= 1;\r\n\r\n\t\t\t\t// check if the cycles fall close to the number\r\n\t\t\t\t// expected for either the low or high frequency\r\n\t\t\t\tif ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {\r\n\t\t\t\t\t// low frequency represents a 1\r\n\t\t\t\t\tshift3 |= (1<<31);\r\n\t\t\t\t} else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {\r\n\t\t\t\t\t// high frequency represents a 0\r\n\t\t\t\t} else {\r\n\t\t\t\t\t// probably detected a gay waveform or noise\r\n\t\t\t\t\t// use this as gaydar or discard shift register and start again\r\n\t\t\t\t\tshift3 = shift2 = shift1 = shift0 = 0;\r\n\t\t\t\t}\r\n\t\t\t\tsamples = i;\r\n\r\n\t\t\t\t// for each bit we receive, test if we've detected a valid tag\r\n\r\n\t\t\t\t// if we see 17 zeroes followed by 6 ones, we might have a tag\r\n\t\t\t\t// remember the bits are backwards\r\n\t\t\t\tif ( ((shift0 & 0x7fffff) == 0x7e0000) ) {\r\n\t\t\t\t\t// if start and end bytes match, we have a tag so break out of the loop\r\n\t\t\t\t\tif ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {\r\n\t\t\t\t\t\tcycles = 0xF0B; //use this as a flag (ugly but whatever)\r\n\t\t\t\t\t\tbreak;\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t}\r\n\t}\r\n\r\n\t// if flag is set we have a tag\r\n\tif (cycles!=0xF0B) {\r\n\t\tDbpString(\"Info: No valid tag detected.\");\r\n\t} else {\r\n\t // put 64 bit data into shift1 and shift0\r\n\t shift0 = (shift0>>24) | (shift1 << 8);\r\n\t shift1 = (shift1>>24) | (shift2 << 8);\r\n\r\n\t\t// align 16 bit crc into lower half of shift2\r\n\t shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;\r\n\r\n\t\t// if r/w tag, check ident match\r\n\t\tif ( shift3&(1<<15) ) {\r\n\t\t\tDbpString(\"Info: TI tag is rewriteable\");\r\n\t\t\t// only 15 bits compare, last bit of ident is not valid\r\n\t\t\tif ( ((shift3>>16)^shift0)&0x7fff ) {\r\n\t\t\t\tDbpString(\"Error: Ident mismatch!\");\r\n\t\t\t} else {\r\n\t\t\t\tDbpString(\"Info: TI tag ident is valid\");\r\n\t\t\t}\r\n\t\t} else {\r\n\t\t\tDbpString(\"Info: TI tag is readonly\");\r\n\t\t}\r\n\r\n\t\t// WARNING the order of the bytes in which we calc crc below needs checking\r\n\t\t// i'm 99% sure the crc algorithm is correct, but it may need to eat the\r\n\t\t// bytes in reverse or something\r\n\t\t// calculate CRC\r\n\t\tuint32_t crc=0;\r\n\r\n\t \tcrc = update_crc16(crc, (shift0)&0xff);\r\n\t\tcrc = update_crc16(crc, (shift0>>8)&0xff);\r\n\t\tcrc = update_crc16(crc, (shift0>>16)&0xff);\r\n\t\tcrc = update_crc16(crc, (shift0>>24)&0xff);\r\n\t\tcrc = update_crc16(crc, (shift1)&0xff);\r\n\t\tcrc = update_crc16(crc, (shift1>>8)&0xff);\r\n\t\tcrc = update_crc16(crc, (shift1>>16)&0xff);\r\n\t\tcrc = update_crc16(crc, (shift1>>24)&0xff);\r\n\r\n\t\tDbprintf(\"Info: Tag data: %x%08x, crc=%x\",\r\n\t\t\t(unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);\r\n\t\tif (crc != (shift2&0xffff)) {\r\n\t\t\tDbprintf(\"Error: CRC mismatch, expected %x\", (unsigned int)crc);\r\n\t\t} else {\r\n\t\t\tDbpString(\"Info: CRC is good\");\r\n\t\t}\r\n\t}\r\n}\r\n\r\nvoid WriteTIbyte(uint8_t b)\r\n{\r\n\tint i = 0;\r\n\t//prolog\r\n\r\n\t\t\r\n\t//SpinDelayUs(1000);\r\n\t// modulate antenna\r\n\tHIGH(GPIO_SSC_DOUT);\r\n\tSpinDelayUs(540);\r\n\tLOW(GPIO_SSC_DOUT);\r\n\t// modulate 8 bits out to the antenna\r\n\tfor (i=7; i>=0; i--)\r\n\t{\r\n\t\tif (b&(1<PIO_PDR = GPIO_SSC_DIN;\r\n\tAT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;\r\n\r\n\t// steal this pin from the SSP and use it to control the modulation\r\n\tAT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;\r\n\tAT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r\n\r\n\tAT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;\r\n\tAT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;\r\n\r\n\t// Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long\r\n\t// 48/2 = 24 MHz clock must be divided by 12\r\n\tAT91C_BASE_SSC->SSC_CMR = 12;\r\n\r\n\tAT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);\r\n\tAT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;\r\n\tAT91C_BASE_SSC->SSC_TCMR = 0;\r\n\tAT91C_BASE_SSC->SSC_TFMR = 0;\r\n\r\n\t\r\n\r\n\t// modulate antenna\r\n\t//HIGH(GPIO_SSC_DOUT);\r\n\r\n\t// Charge TI tag for 50ms.\r\n\tSpinDelay(50);\r\n\r\n\t// stop modulating antenna and listen\r\n\t//LED_A_ON();\r\n\tLOW(GPIO_SSC_DOUT);\r\n\t//ti = GetTickCount();\n\r\n\t//SpinDelay(1000);\n\r\n\t//ti = GetTickCount() - ti;\n\t\r\n\t//Dbprintf(\"timer(1s): %d t=%d\", ti, GetTickCount());\r\n\t//LED_A_OFF();\t\r\n\tLED_D_ON();\r\n\ti = 0;\r\n\tti = GetTickCount();\n\r\n\tfor(;;) {\r\n\t\tif(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {\r\n\t\t\tBigBuf[i] = AT91C_BASE_SSC->SSC_RHR;\t// store 32 bit values in buffer\r\n\t\t\ti++; if(i >= 40000) break;\r\n\t\t}\r\n\t\tWDT_HIT();\r\n\t}\r\n\tti = GetTickCount() - ti;\n\t\r\n\tDbprintf(\"timer(1s): %d t=%d\", ti, GetTickCount());\r\n\tLED_D_OFF();\r\n\t// return stolen pin to SSP\r\n\tAT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;\r\n\tAT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;\r\n\r\n}\r\n\r\n// arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc\r\n// if crc provided, it will be written with the data verbatim (even if bogus)\r\n// if not provided a valid crc will be computed from the data and written.\r\nvoid WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)\r\n{\r\n\tint i, sum;\r\n\tsum = 0x23 + idhi + idlo;\r\n\t//if(crc == 0) {\r\n\t //\tcrc = update_crc16(crc, (idlo)&0xff);\r\n\t//\tcrc = update_crc16(crc, (idlo>>8)&0xff);\r\n\t//\tcrc = update_crc16(crc, (idlo>>16)&0xff);\r\n\t//\tcrc = update_crc16(crc, (idlo>>24)&0xff);\r\n\t//\tcrc = update_crc16(crc, (idhi)&0xff);\r\n\t//\tcrc = update_crc16(crc, (idhi>>8)&0xff);\r\n\t//\tcrc = update_crc16(crc, (idhi>>16)&0xff);\r\n\t//\tcrc = update_crc16(crc, (idhi>>24)&0xff);\r\n\t//}\r\n\t//Dbprintf(\"Writing to tag: %x%08x, crc=%x\",\r\n\t//\t(unsigned int) idhi, (unsigned int) idlo, crc);\r\n\r\n\t// TI tags charge at 134.2Khz //88 is 125\r\n\t\r\n\r\n\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 94); //134.8Khz\r\n\t// Place FPGA in passthrough mode, in this mode the CROSS_LO line\r\n\t// connects to SSP_DIN and the SSP_DOUT logic level controls\r\n\t// whether we're modulating the antenna (high)\r\n\t// or listening to the antenna (low)\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);\r\n\tLED_A_ON();\r\n\r\n\t// steal this pin from the SSP and use it to control the modulation\r\n\tAT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;\r\n\tAT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r\n\r\n\t// writing algorithm:\r\n\t// a high bit consists of a field off for 1ms and field on for 1ms\r\n\t// a low bit consists of a field off for 0.3ms and field on for 1.7ms\r\n\t// initiate a charge time of 50ms (field on) then immediately start writing bits\r\n\t// start by writing 0xBB (keyword) and 0xEB (password)\r\n\t// then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)\r\n\t// finally end with 0x0300 (write frame)\r\n\t// all data is sent lsb firts\r\n\t// finish with 15ms programming time\r\n\r\n\t// modulate antenna\r\n\t//HIGH(GPIO_SSC_DOUT);\r\n\t//SpinDelay(10000);\t// charge time\r\n\tfor(i = 0; i < 10; i++){\r\n\tWriteTIbyte(0xf0);\r\n\tWriteTIbyte(0x01); \r\n\tWriteTIbyte( 0x0f );\r\n\tWriteTIbyte(0x01);\r\n\tWriteTIbyte(0x01);\r\n \r\n\tWriteTIbyte(0x0F);\r\n\tWriteTIbyte(0x0B); \r\n\tWriteTIbyte( 0x00 );\r\n\tWriteTIbyte(0x06);\r\n\tWriteTIbyte(0x80);\r\n\r\n\tWriteTIbyte(0x02);\r\n\tWriteTIbyte(0x08); \r\n\tWriteTIbyte( 0x01 );\r\n\tWriteTIbyte(0x08);\r\n\tWriteTIbyte(0x1a);\r\n\r\n\tWriteTIbyte(0x1a);\r\n\tWriteTIbyte(0x1a); \r\n\tWriteTIbyte( 0x1a );\r\n\tWriteTIbyte( 0x2d );\t\r\n\r\n\r\n\t//LOW(GPIO_SSC_DOUT);\r\n\tSpinDelay(100);\r\n\t\r\n\tWriteTIbyte(0xf0);\r\n\tWriteTIbyte(0x07); \r\n\tWriteTIbyte( 0x05 );\r\n\tWriteTIbyte(0x01);\r\n\tWriteTIbyte(0x07);\r\n \r\n\tWriteTIbyte(0x0f);\r\n\tWriteTIbyte(idhi); \r\n\tWriteTIbyte( idlo );\r\n\tWriteTIbyte( sum & 0xFF );\r\n\t\r\n\r\n\tSpinDelay(1000);\r\n\t}\r\n\r\n\r\n\tLED_A_OFF();\r\n\r\n\t// get TI tag data into the buffer\r\n\t//AcquireTiType();\r\n\r\n\t//FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\tDbpString(\"Done\");\r\n}\r\n\r\nvoid SimulateTagLowFrequency(int period, int gap, int ledcontrol)\r\n{\r\n\tint i;\r\n\tuint8_t *tab = (uint8_t *)BigBuf;\r\n \r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);\r\n \r\n\tAT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;\r\n \r\n\tAT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r\n\tAT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;\r\n \r\n#define SHORT_COIL()\tLOW(GPIO_SSC_DOUT)\r\n#define OPEN_COIL()\t\tHIGH(GPIO_SSC_DOUT)\r\n \r\n\ti = 0;\r\n\tfor(;;) {\r\n\t\twhile(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {\r\n\t\t\tif(BUTTON_PRESS()) {\r\n\t\t\t\tDbpString(\"Stopped\");\r\n\t\t\t\treturn;\r\n\t\t\t}\r\n\t\t\tWDT_HIT();\r\n\t\t}\r\n \r\n\t\tif (ledcontrol)\r\n\t\t\tLED_D_ON();\r\n \r\n\t\tif(tab[i])\r\n\t\t\tOPEN_COIL();\r\n\t\telse\r\n\t\t\tSHORT_COIL();\r\n \r\n\t\tif (ledcontrol)\r\n\t\t\tLED_D_OFF();\r\n \r\n\t\twhile(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {\r\n\t\t\tif(BUTTON_PRESS()) {\r\n\t\t\t\tDbpString(\"Stopped\");\r\n\t\t\t\treturn;\r\n\t\t\t}\r\n\t\t\tWDT_HIT();\r\n\t\t}\r\n \r\n\t\ti++;\r\n\t\tif(i == period) {\r\n\t\t\ti = 0;\r\n\t\t\tif (gap) {\r\n\t\t\t\tSHORT_COIL();\r\n\t\t\t\tSpinDelayUs(gap);\r\n\t\t\t}\r\n\t\t}\r\n\t}\r\n}\r\n\r\n#define DEBUG_FRAME_CONTENTS 1\r\nvoid SimulateTagLowFrequencyBidir(int divisor, int t0)\r\n{\r\n}\r\n\r\n// compose fc/8 fc/10 waveform\r\nstatic void fc(int c, int *n) {\r\n\tuint8_t *dest = (uint8_t *)BigBuf;\r\n\tint idx;\r\n\r\n\t// for when we want an fc8 pattern every 4 logical bits\r\n\tif(c==0) {\r\n\t\tdest[((*n)++)]=1;\r\n\t\tdest[((*n)++)]=1;\r\n\t\tdest[((*n)++)]=0;\r\n\t\tdest[((*n)++)]=0;\r\n\t\tdest[((*n)++)]=0;\r\n\t\tdest[((*n)++)]=0;\r\n\t\tdest[((*n)++)]=0;\r\n\t\tdest[((*n)++)]=0;\r\n\t}\r\n\t//\tan fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples\r\n\tif(c==8) {\r\n\t\tfor (idx=0; idx<6; idx++) {\r\n\t\t\tdest[((*n)++)]=1;\r\n\t\t\tdest[((*n)++)]=1;\r\n\t\t\tdest[((*n)++)]=0;\r\n\t\t\tdest[((*n)++)]=0;\r\n\t\t\tdest[((*n)++)]=0;\r\n\t\t\tdest[((*n)++)]=0;\r\n\t\t\tdest[((*n)++)]=0;\r\n\t\t\tdest[((*n)++)]=0;\r\n\t\t}\r\n\t}\r\n\r\n\t//\tan fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples\r\n\tif(c==10) {\r\n\t\tfor (idx=0; idx<5; idx++) {\r\n\t\t\tdest[((*n)++)]=1;\r\n\t\t\tdest[((*n)++)]=1;\r\n\t\t\tdest[((*n)++)]=1;\r\n\t\t\tdest[((*n)++)]=0;\r\n\t\t\tdest[((*n)++)]=0;\r\n\t\t\tdest[((*n)++)]=0;\r\n\t\t\tdest[((*n)++)]=0;\r\n\t\t\tdest[((*n)++)]=0;\r\n\t\t\tdest[((*n)++)]=0;\r\n\t\t\tdest[((*n)++)]=0;\r\n\t\t}\r\n\t}\r\n}\r\n\r\n// prepare a waveform pattern in the buffer based on the ID given then\r\n// simulate a HID tag until the button is pressed\r\nvoid CmdHIDsimTAG(int hi, int lo, int ledcontrol)\r\n{\r\n\tint n=0, i=0;\r\n\t/*\r\n\t HID tag bitstream format\r\n\t The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits\r\n\t A 1 bit is represented as 6 fc8 and 5 fc10 patterns\r\n\t A 0 bit is represented as 5 fc10 and 6 fc8 patterns\r\n\t A fc8 is inserted before every 4 bits\r\n\t A special start of frame pattern is used consisting a0b0 where a and b are neither 0\r\n\t nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)\r\n\t*/\r\n\r\n\tif (hi>0xFFF) {\r\n\t\tDbpString(\"Tags can only have 44 bits.\");\r\n\t\treturn;\r\n\t}\r\n\tfc(0,&n);\r\n\t// special start of frame marker containing invalid bit sequences\r\n\tfc(8, &n);\tfc(8, &n);\t// invalid\r\n\tfc(8, &n);\tfc(10, &n); // logical 0\r\n\tfc(10, &n);\tfc(10, &n); // invalid\r\n\tfc(8, &n);\tfc(10, &n); // logical 0\r\n\r\n\tWDT_HIT();\r\n\t// manchester encode bits 43 to 32\r\n\tfor (i=11; i>=0; i--) {\r\n\t\tif ((i%4)==3) fc(0,&n);\r\n\t\tif ((hi>>i)&1) {\r\n\t\t\tfc(10, &n);\tfc(8, &n);\t\t// low-high transition\r\n\t\t} else {\r\n\t\t\tfc(8, &n);\tfc(10, &n);\t\t// high-low transition\r\n\t\t}\r\n\t}\r\n\r\n\tWDT_HIT();\r\n\t// manchester encode bits 31 to 0\r\n\tfor (i=31; i>=0; i--) {\r\n\t\tif ((i%4)==3) fc(0,&n);\r\n\t\tif ((lo>>i)&1) {\r\n\t\t\tfc(10, &n);\tfc(8, &n);\t\t// low-high transition\r\n\t\t} else {\r\n\t\t\tfc(8, &n);\tfc(10, &n);\t\t// high-low transition\r\n\t\t}\r\n\t}\r\n\r\n\tif (ledcontrol)\r\n\t\tLED_A_ON();\r\n\tSimulateTagLowFrequency(n, 0, ledcontrol);\r\n\r\n\tif (ledcontrol)\r\n\t\tLED_A_OFF();\r\n}\r\n\r\n\r\n// loop to capture raw HID waveform then FSK demodulate the TAG ID from it\r\nvoid CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)\r\n{\r\n\tuint8_t *dest = (uint8_t *)BigBuf;\r\n\tint m=0, n=0, i=0, idx=0, found=0, lastval=0;\r\n uint32_t hi2=0, hi=0, lo=0;\r\n\r\n\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r\n\t//FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r\n\r\n\t// Connect the A/D to the peak-detected low-frequency path.\r\n\tSetAdcMuxFor(GPIO_MUXSEL_LOPKD);\r\n\r\n\t// Give it a bit of time for the resonant antenna to settle.\r\n\tSpinDelay(50);\r\n\r\n\t// Now set up the SSC to get the ADC samples that are now streaming at us.\r\n\tFpgaSetupSsc();\r\n\r\n\tfor(;;) {\r\n\t\tWDT_HIT();\r\n\t\tif (ledcontrol)\r\n\t\t\tLED_A_ON();\r\n\t\tif(BUTTON_PRESS()) {\r\n\t\t\tDbpString(\"Stopped\");\r\n\t\t\tif (ledcontrol)\r\n\t\t\t\tLED_A_OFF();\r\n\t\t\treturn;\r\n\t\t}\r\n\r\n\t\ti = 0;\r\n\t\tm = sizeof(BigBuf);\r\n\t\tmemset(dest,128,m);\r\n\t\tfor(;;) {\r\n\t\t\tif(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r\n\t\t\t\tAT91C_BASE_SSC->SSC_THR = 0x43;\r\n\t\t\t\tif (ledcontrol)\r\n\t\t\t\t\tLED_D_ON();\r\n\t\t\t}\r\n\t\t\tif(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r\n\t\t\t\tdest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;\r\n\t\t\t\t// we don't care about actual value, only if it's more or less than a\r\n\t\t\t\t// threshold essentially we capture zero crossings for later analysis\r\n\t\t\t\tif(dest[i] < 127) dest[i] = 0; else dest[i] = 1;\r\n\t\t\t\ti++;\r\n\t\t\t\tif (ledcontrol)\r\n\t\t\t\t\tLED_D_OFF();\r\n\t\t\t\tif(i >= m) {\r\n\t\t\t\t\tbreak;\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t}\r\n\r\n\t\t// FSK demodulator\r\n\r\n\t\t// sync to first lo-hi transition\r\n\t\tfor( idx=1; idx>1) & 0xFFFF);\r\n }\r\n else {\r\n Dbprintf(\"TAG ID: %x%08x (%d)\",\r\n (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);\r\n }\r\n\t\t\t\t\t/* if we're only looking for one tag */\r\n\t\t\t\t\tif (findone)\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t*high = hi;\r\n\t\t\t\t\t\t*low = lo;\r\n\t\t\t\t\t\treturn;\r\n\t\t\t\t\t}\r\n hi2=0;\r\n\t\t\t\t\thi=0;\r\n\t\t\t\t\tlo=0;\r\n\t\t\t\t\tfound=0;\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\tif (found) {\r\n\t\t\t\tif (dest[idx] && (!dest[idx+1]) ) {\r\n hi2=(hi2<<1)|(hi>>31);\r\n\t\t\t\t\thi=(hi<<1)|(lo>>31);\r\n\t\t\t\t\tlo=(lo<<1)|0;\r\n\t\t\t\t} else if ( (!dest[idx]) && dest[idx+1]) {\r\n hi2=(hi2<<1)|(hi>>31);\r\n\t\t\t\t\thi=(hi<<1)|(lo>>31);\r\n\t\t\t\t\tlo=(lo<<1)|1;\r\n\t\t\t\t} else {\r\n\t\t\t\t\tfound=0;\r\n hi2=0;\r\n\t\t\t\t\thi=0;\r\n\t\t\t\t\tlo=0;\r\n\t\t\t\t}\r\n\t\t\t\tidx++;\r\n\t\t\t}\r\n\t\t\tif ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) )\r\n\t\t\t{\r\n\t\t\t\tfound=1;\r\n\t\t\t\tidx+=6;\r\n\t\t\t\tif (found && (hi|lo)) {\r\n if (hi2 != 0){\r\n Dbprintf(\"TAG ID: %x%08x%08x (%d)\",\r\n (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);\r\n }\r\n else {\r\n Dbprintf(\"TAG ID: %x%08x (%d)\",\r\n (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);\r\n }\r\n\t\t\t\t\t/* if we're only looking for one tag */\r\n\t\t\t\t\tif (findone)\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t*high = hi;\r\n\t\t\t\t\t\t*low = lo;\r\n\t\t\t\t\t\treturn;\r\n\t\t\t\t\t}\r\n hi2=0;\r\n\t\t\t\t\thi=0;\r\n\t\t\t\t\tlo=0;\r\n\t\t\t\t\tfound=0;\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t}\r\n\t\tWDT_HIT();\r\n\t}\r\n}\r\n\r\n/*------------------------------\r\n * T5555/T5557/T5567 routines\r\n *------------------------------\r\n */\r\n\r\n/* T55x7 configuration register definitions */\r\n#define T55x7_POR_DELAY\t\t\t0x00000001\r\n#define T55x7_ST_TERMINATOR\t\t0x00000008\r\n#define T55x7_PWD\t\t\t0x00000010\r\n#define T55x7_MAXBLOCK_SHIFT\t\t5\r\n#define T55x7_AOR\t\t\t0x00000200\r\n#define T55x7_PSKCF_RF_2\t\t0\r\n#define T55x7_PSKCF_RF_4\t\t0x00000400\r\n#define T55x7_PSKCF_RF_8\t\t0x00000800\r\n#define T55x7_MODULATION_DIRECT\t\t0\r\n#define T55x7_MODULATION_PSK1\t\t0x00001000\r\n#define T55x7_MODULATION_PSK2\t\t0x00002000\r\n#define T55x7_MODULATION_PSK3\t\t0x00003000\r\n#define T55x7_MODULATION_FSK1\t\t0x00004000\r\n#define T55x7_MODULATION_FSK2\t\t0x00005000\r\n#define T55x7_MODULATION_FSK1a\t\t0x00006000\r\n#define T55x7_MODULATION_FSK2a\t\t0x00007000\r\n#define T55x7_MODULATION_MANCHESTER\t0x00008000\r\n#define T55x7_MODULATION_BIPHASE\t0x00010000\r\n#define T55x7_BITRATE_RF_8\t\t0\r\n#define T55x7_BITRATE_RF_16\t\t0x00040000\r\n#define T55x7_BITRATE_RF_32\t\t0x00080000\r\n#define T55x7_BITRATE_RF_40\t\t0x000C0000\r\n#define T55x7_BITRATE_RF_50\t\t0x00100000\r\n#define T55x7_BITRATE_RF_64\t\t0x00140000\r\n#define T55x7_BITRATE_RF_100\t\t0x00180000\r\n#define T55x7_BITRATE_RF_128\t\t0x001C0000\r\n\r\n/* T5555 (Q5) configuration register definitions */\r\n#define T5555_ST_TERMINATOR\t\t0x00000001\r\n#define T5555_MAXBLOCK_SHIFT\t\t0x00000001\r\n#define T5555_MODULATION_MANCHESTER\t0\r\n#define T5555_MODULATION_PSK1\t\t0x00000010\r\n#define T5555_MODULATION_PSK2\t\t0x00000020\r\n#define T5555_MODULATION_PSK3\t\t0x00000030\r\n#define T5555_MODULATION_FSK1\t\t0x00000040\r\n#define T5555_MODULATION_FSK2\t\t0x00000050\r\n#define T5555_MODULATION_BIPHASE\t0x00000060\r\n#define T5555_MODULATION_DIRECT\t\t0x00000070\r\n#define T5555_INVERT_OUTPUT\t\t0x00000080\r\n#define T5555_PSK_RF_2\t\t\t0\r\n#define T5555_PSK_RF_4\t\t\t0x00000100\r\n#define T5555_PSK_RF_8\t\t\t0x00000200\r\n#define T5555_USE_PWD\t\t\t0x00000400\r\n#define T5555_USE_AOR\t\t\t0x00000800\r\n#define T5555_BITRATE_SHIFT\t\t12\r\n#define T5555_FAST_WRITE\t\t0x00004000\r\n#define T5555_PAGE_SELECT\t\t0x00008000\r\n\r\n/*\r\n * Relevant times in microsecond\r\n * To compensate antenna falling times shorten the write times\r\n * and enlarge the gap ones.\r\n */\r\n#define START_GAP 250\r\n#define WRITE_GAP 160\r\n#define WRITE_0 144 // 192\r\n#define WRITE_1 400 // 432 for T55x7; 448 for E5550\r\n\r\n// Write one bit to card\r\nvoid T55xxWriteBit(int bit)\r\n{\r\n\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r\n\t//FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r\n\tif (bit == 0)\r\n\t\tSpinDelayUs(WRITE_0);\r\n\telse\r\n\t\tSpinDelayUs(WRITE_1);\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\tSpinDelayUs(WRITE_GAP);\r\n}\r\n\r\n// Write one card block in page 0, no lock\r\nvoid T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)\r\n{\r\n\tunsigned int i;\r\n\r\n\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r\n\t//FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r\n\r\n\t// Give it a bit of time for the resonant antenna to settle.\r\n\t// And for the tag to fully power up\r\n\tSpinDelay(150);\r\n\r\n\t// Now start writting\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\tSpinDelayUs(START_GAP);\r\n\r\n\t// Opcode\r\n\tT55xxWriteBit(1);\r\n\tT55xxWriteBit(0); //Page 0\r\n if (PwdMode == 1){\r\n // Pwd\r\n for (i = 0x80000000; i != 0; i >>= 1)\r\n T55xxWriteBit(Pwd & i);\r\n }\r\n\t// Lock bit\r\n\tT55xxWriteBit(0);\r\n\r\n\t// Data\r\n\tfor (i = 0x80000000; i != 0; i >>= 1)\r\n\t\tT55xxWriteBit(Data & i);\r\n\r\n\t// Block\r\n\tfor (i = 0x04; i != 0; i >>= 1)\r\n\t\tT55xxWriteBit(Block & i);\r\n\r\n\t// Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,\r\n\t// so wait a little more)\r\n\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r\n\t//FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r\n\tSpinDelay(20);\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n}\r\n\r\n// Read one card block in page 0\r\nvoid T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)\r\n{\r\n\tuint8_t *dest = (uint8_t *)BigBuf;\r\n\tint m=0, i=0;\r\n \r\n\tm = sizeof(BigBuf);\r\n // Clear destination buffer before sending the command\r\n\tmemset(dest, 128, m);\r\n\t// Connect the A/D to the peak-detected low-frequency path.\r\n\tSetAdcMuxFor(GPIO_MUXSEL_LOPKD);\r\n\t// Now set up the SSC to get the ADC samples that are now streaming at us.\r\n\tFpgaSetupSsc();\r\n \r\n\tLED_D_ON();\r\n\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r\n\t//FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r\n \r\n\t// Give it a bit of time for the resonant antenna to settle.\r\n\t// And for the tag to fully power up\r\n\tSpinDelay(150);\r\n \r\n\t// Now start writting\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\tSpinDelayUs(START_GAP);\r\n \r\n\t// Opcode\r\n\tT55xxWriteBit(1);\r\n\tT55xxWriteBit(0); //Page 0\r\n\tif (PwdMode == 1){\r\n\t\t// Pwd\r\n\t\tfor (i = 0x80000000; i != 0; i >>= 1)\r\n\t\t\tT55xxWriteBit(Pwd & i);\r\n\t}\r\n\t// Lock bit\r\n\tT55xxWriteBit(0);\r\n\t// Block\r\n\tfor (i = 0x04; i != 0; i >>= 1)\r\n\t\tT55xxWriteBit(Block & i);\r\n \r\n // Turn field on to read the response\r\n\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r\n\t//FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r\n \r\n\t// Now do the acquisition\r\n\ti = 0;\r\n\tfor(;;) {\r\n\t\tif (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {\r\n\t\t\tAT91C_BASE_SSC->SSC_THR = 0x43;\r\n\t\t}\r\n\t\tif (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {\r\n\t\t\tdest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;\r\n\t\t\t// we don't care about actual value, only if it's more or less than a\r\n\t\t\t// threshold essentially we capture zero crossings for later analysis\r\n //\t\t\tif(dest[i] < 127) dest[i] = 0; else dest[i] = 1;\r\n\t\t\ti++;\r\n\t\t\tif (i >= m) break;\r\n\t\t}\r\n\t}\r\n \r\n FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off\r\n\tLED_D_OFF();\r\n\tDbpString(\"DONE!\");\r\n}\r\n\r\n// Read card traceability data (page 1)\r\nvoid T55xxReadTrace(void){\r\n\tuint8_t *dest = (uint8_t *)BigBuf;\r\n\tint m=0, i=0;\r\n \r\n\tm = sizeof(BigBuf);\r\n // Clear destination buffer before sending the command\r\n\tmemset(dest, 128, m);\r\n\t// Connect the A/D to the peak-detected low-frequency path.\r\n\tSetAdcMuxFor(GPIO_MUXSEL_LOPKD);\r\n\t// Now set up the SSC to get the ADC samples that are now streaming at us.\r\n\tFpgaSetupSsc();\r\n \r\n\tLED_D_ON();\r\n\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r\n\t//FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r\n \r\n\t// Give it a bit of time for the resonant antenna to settle.\r\n\t// And for the tag to fully power up\r\n\tSpinDelay(150);\r\n \r\n\t// Now start writting\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\tSpinDelayUs(START_GAP);\r\n \r\n\t// Opcode\r\n\tT55xxWriteBit(1);\r\n\tT55xxWriteBit(1); //Page 1\r\n \r\n // Turn field on to read the response\r\n\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r\n\t//FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r\n \r\n\t// Now do the acquisition\r\n\ti = 0;\r\n\tfor(;;) {\r\n\t\tif (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {\r\n\t\t\tAT91C_BASE_SSC->SSC_THR = 0x43;\r\n\t\t}\r\n\t\tif (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {\r\n\t\t\tdest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;\r\n\t\t\ti++;\r\n\t\t\tif (i >= m) break;\r\n\t\t}\r\n\t}\r\n \r\n FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off\r\n\tLED_D_OFF();\r\n\tDbpString(\"DONE!\");\r\n}\r\n\r\n/*-------------- Cloning routines -----------*/\r\n// Copy HID id to card and setup block 0 config\r\nvoid CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)\r\n{\r\n\tint data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format\r\n\tint last_block = 0;\r\n \r\n if (longFMT){\r\n\t // Ensure no more than 84 bits supplied\r\n\t if (hi2>0xFFFFF) {\r\n\t\t DbpString(\"Tags can only have 84 bits.\");\r\n\t\t return;\r\n\t }\r\n // Build the 6 data blocks for supplied 84bit ID\r\n last_block = 6;\r\n data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)\r\n\t for (int i=0;i<4;i++) {\r\n\t\t if (hi2 & (1<<(19-i)))\r\n\t\t\t data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10\r\n\t\t else\r\n\t\t\t data1 |= (1<<((3-i)*2)); // 0 -> 01\r\n\t }\r\n \r\n \tdata2 = 0;\r\n \tfor (int i=0;i<16;i++) {\r\n \t\tif (hi2 & (1<<(15-i)))\r\n \t\t\tdata2 |= (1<<(((15-i)*2)+1)); // 1 -> 10\r\n \t\telse\r\n \t\t\tdata2 |= (1<<((15-i)*2)); // 0 -> 01\r\n }\r\n \r\n \tdata3 = 0;\r\n \tfor (int i=0;i<16;i++) {\r\n \t\tif (hi & (1<<(31-i)))\r\n \t\t\tdata3 |= (1<<(((15-i)*2)+1)); // 1 -> 10\r\n \t\telse\r\n \t\t\tdata3 |= (1<<((15-i)*2)); // 0 -> 01\r\n \t}\r\n \r\n \tdata4 = 0;\r\n \tfor (int i=0;i<16;i++) {\r\n \t\tif (hi & (1<<(15-i)))\r\n \t\t\tdata4 |= (1<<(((15-i)*2)+1)); // 1 -> 10\r\n \t\telse\r\n \t\t\tdata4 |= (1<<((15-i)*2)); // 0 -> 01\r\n }\r\n \r\n \tdata5 = 0;\r\n \tfor (int i=0;i<16;i++) {\r\n \t\tif (lo & (1<<(31-i)))\r\n \t\t\tdata5 |= (1<<(((15-i)*2)+1)); // 1 -> 10\r\n \t\telse\r\n \t\t\tdata5 |= (1<<((15-i)*2)); // 0 -> 01\r\n \t}\r\n \r\n \tdata6 = 0;\r\n \tfor (int i=0;i<16;i++) {\r\n \t\tif (lo & (1<<(15-i)))\r\n \t\t\tdata6 |= (1<<(((15-i)*2)+1)); // 1 -> 10\r\n \t\telse\r\n \t\t\tdata6 |= (1<<((15-i)*2)); // 0 -> 01\r\n }\r\n }\r\n else {\r\n\t // Ensure no more than 44 bits supplied\r\n\t if (hi>0xFFF) {\r\n\t\t DbpString(\"Tags can only have 44 bits.\");\r\n\t\t return;\r\n\t }\r\n \r\n \t// Build the 3 data blocks for supplied 44bit ID\r\n \tlast_block = 3;\r\n \t\r\n \tdata1 = 0x1D000000; // load preamble\r\n \r\n for (int i=0;i<12;i++) {\r\n if (hi & (1<<(11-i)))\r\n data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10\r\n else\r\n data1 |= (1<<((11-i)*2)); // 0 -> 01\r\n }\r\n \r\n \tdata2 = 0;\r\n \tfor (int i=0;i<16;i++) {\r\n \t\tif (lo & (1<<(31-i)))\r\n \t\t\tdata2 |= (1<<(((15-i)*2)+1)); // 1 -> 10\r\n \t\telse\r\n \t\t\tdata2 |= (1<<((15-i)*2)); // 0 -> 01\r\n \t}\r\n \r\n \tdata3 = 0;\r\n \tfor (int i=0;i<16;i++) {\r\n \t\tif (lo & (1<<(15-i)))\r\n \t\t\tdata3 |= (1<<(((15-i)*2)+1)); // 1 -> 10\r\n \t\telse\r\n \t\t\tdata3 |= (1<<((15-i)*2)); // 0 -> 01\r\n \t}\r\n }\r\n \r\n\tLED_D_ON();\r\n\t// Program the data blocks for supplied ID\r\n\t// and the block 0 for HID format\r\n\tT55xxWriteBlock(data1,1,0,0);\r\n\tT55xxWriteBlock(data2,2,0,0);\r\n\tT55xxWriteBlock(data3,3,0,0);\r\n\t\r\n\tif (longFMT) { // if long format there are 6 blocks\r\n\t T55xxWriteBlock(data4,4,0,0);\r\n\t T55xxWriteBlock(data5,5,0,0);\r\n\t T55xxWriteBlock(data6,6,0,0);\r\n }\r\n \r\n\t// Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)\r\n\tT55xxWriteBlock(T55x7_BITRATE_RF_50 |\r\n T55x7_MODULATION_FSK2a |\r\n last_block << T55x7_MAXBLOCK_SHIFT,\r\n 0,0,0);\r\n \r\n\tLED_D_OFF();\r\n\t\r\n\tDbpString(\"DONE!\");\r\n}\r\n\r\n// Define 9bit header for EM410x tags\r\n#define EM410X_HEADER\t\t0x1FF\r\n#define EM410X_ID_LENGTH\t40\r\n\r\nvoid WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)\r\n{\r\n\tint i, id_bit;\r\n\tuint64_t id = EM410X_HEADER;\r\n\tuint64_t rev_id = 0;\t// reversed ID\r\n\tint c_parity[4];\t// column parity\r\n\tint r_parity = 0;\t// row parity\r\n\tuint32_t clock = 0;\r\n\r\n\t// Reverse ID bits given as parameter (for simpler operations)\r\n\tfor (i = 0; i < EM410X_ID_LENGTH; ++i) {\r\n\t\tif (i < 32) {\r\n\t\t\trev_id = (rev_id << 1) | (id_lo & 1);\r\n\t\t\tid_lo >>= 1;\r\n\t\t} else {\r\n\t\t\trev_id = (rev_id << 1) | (id_hi & 1);\r\n\t\t\tid_hi >>= 1;\r\n\t\t}\r\n\t}\r\n\r\n\tfor (i = 0; i < EM410X_ID_LENGTH; ++i) {\r\n\t\tid_bit = rev_id & 1;\r\n\r\n\t\tif (i % 4 == 0) {\r\n\t\t\t// Don't write row parity bit at start of parsing\r\n\t\t\tif (i)\r\n\t\t\t\tid = (id << 1) | r_parity;\r\n\t\t\t// Start counting parity for new row\r\n\t\t\tr_parity = id_bit;\r\n\t\t} else {\r\n\t\t\t// Count row parity\r\n\t\t\tr_parity ^= id_bit;\r\n\t\t}\r\n\r\n\t\t// First elements in column?\r\n\t\tif (i < 4)\r\n\t\t\t// Fill out first elements\r\n\t\t\tc_parity[i] = id_bit;\r\n\t\telse\r\n\t\t\t// Count column parity\r\n\t\t\tc_parity[i % 4] ^= id_bit;\r\n\r\n\t\t// Insert ID bit\r\n\t\tid = (id << 1) | id_bit;\r\n\t\trev_id >>= 1;\r\n\t}\r\n\r\n\t// Insert parity bit of last row\r\n\tid = (id << 1) | r_parity;\r\n\r\n\t// Fill out column parity at the end of tag\r\n\tfor (i = 0; i < 4; ++i)\r\n\t\tid = (id << 1) | c_parity[i];\r\n\r\n\t// Add stop bit\r\n\tid <<= 1;\r\n\r\n\tDbprintf(\"Started writing %s tag ...\", card ? \"T55x7\":\"T5555\");\r\n\tLED_D_ON();\r\n\r\n\t// Write EM410x ID\r\n\tT55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);\r\n\tT55xxWriteBlock((uint32_t)id, 2, 0, 0);\r\n\r\n\t// Config for EM410x (RF/64, Manchester, Maxblock=2)\r\n\tif (card) {\r\n\t\t// Clock rate is stored in bits 8-15 of the card value\r\n\t\tclock = (card & 0xFF00) >> 8;\r\n\t\tDbprintf(\"Clock rate: %d\", clock);\r\n\t\tswitch (clock)\r\n\t\t{\r\n\t\t\tcase 32:\r\n\t\t\t\tclock = T55x7_BITRATE_RF_32;\r\n\t\t\t\tbreak;\r\n\t\t\tcase 16:\r\n\t\t\t\tclock = T55x7_BITRATE_RF_16;\r\n\t\t\t\tbreak;\r\n\t\t\tcase 0:\r\n\t\t\t\t// A value of 0 is assumed to be 64 for backwards-compatibility\r\n\t\t\t\t// Fall through...\r\n\t\t\tcase 64:\r\n\t\t\t\tclock = T55x7_BITRATE_RF_64;\r\n\t\t\t\tbreak; \r\n\t\t\tdefault:\r\n\t\t\t\tDbprintf(\"Invalid clock rate: %d\", clock);\r\n\t\t\t\treturn;\r\n\t\t}\r\n\r\n\t\t// Writing configuration for T55x7 tag\r\n\t\tT55xxWriteBlock(clock\t |\r\n\t\t\t\tT55x7_MODULATION_MANCHESTER |\r\n\t\t\t\t2 << T55x7_MAXBLOCK_SHIFT,\r\n\t\t\t\t0, 0, 0);\r\n }\r\n\telse\r\n\t\t// Writing configuration for T5555(Q5) tag\r\n\t\tT55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |\r\n\t\t\t\tT5555_MODULATION_MANCHESTER |\r\n\t\t\t\t2 << T5555_MAXBLOCK_SHIFT,\r\n\t\t\t\t0, 0, 0);\r\n\r\n\tLED_D_OFF();\r\n\tDbprintf(\"Tag %s written with 0x%08x%08x\\n\", card ? \"T55x7\":\"T5555\",\r\n\t\t\t\t\t(uint32_t)(id >> 32), (uint32_t)id);\r\n}\r\n\r\n// Clone Indala 64-bit tag by UID to T55x7\r\nvoid CopyIndala64toT55x7(int hi, int lo)\r\n{\r\n\r\n\t//Program the 2 data blocks for supplied 64bit UID\r\n\t// and the block 0 for Indala64 format\r\n\tT55xxWriteBlock(hi,1,0,0);\r\n\tT55xxWriteBlock(lo,2,0,0);\r\n\t//Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)\r\n\tT55xxWriteBlock(T55x7_BITRATE_RF_32 |\r\n\t\t\tT55x7_MODULATION_PSK1 |\r\n\t\t\t2 << T55x7_MAXBLOCK_SHIFT,\r\n\t\t\t0, 0, 0);\r\n\t//Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)\r\n//\tT5567WriteBlock(0x603E1042,0);\r\n\r\n\tDbpString(\"DONE!\");\r\n\r\n}\t\r\n\r\nvoid CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)\r\n{\r\n\r\n\t//Program the 7 data blocks for supplied 224bit UID\r\n\t// and the block 0 for Indala224 format\r\n\tT55xxWriteBlock(uid1,1,0,0);\r\n\tT55xxWriteBlock(uid2,2,0,0);\r\n\tT55xxWriteBlock(uid3,3,0,0);\r\n\tT55xxWriteBlock(uid4,4,0,0);\r\n\tT55xxWriteBlock(uid5,5,0,0);\r\n\tT55xxWriteBlock(uid6,6,0,0);\r\n\tT55xxWriteBlock(uid7,7,0,0);\r\n\t//Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)\r\n\tT55xxWriteBlock(T55x7_BITRATE_RF_32 |\r\n\t\t\tT55x7_MODULATION_PSK1 |\r\n\t\t\t7 << T55x7_MAXBLOCK_SHIFT,\r\n\t\t\t0,0,0);\r\n\t//Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)\r\n//\tT5567WriteBlock(0x603E10E2,0);\r\n\r\n\tDbpString(\"DONE!\");\r\n\r\n}\r\n\r\n\r\n#define abs(x) ( ((x)<0) ? -(x) : (x) )\r\n#define max(x,y) ( x GraphBuffer[0]) {\r\n while(i < GraphTraceLen) {\r\n if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)\r\n break;\r\n i++;\r\n }\r\n dir = 0;\r\n\t}\r\n\telse {\r\n while(i < GraphTraceLen) {\r\n if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)\r\n break;\r\n i++;\r\n }\r\n dir = 1;\r\n\t}\r\n\t\r\n\tlastval = i++;\r\n\thalf_switch = 0;\r\n\tpmc = 0;\r\n\tblock_done = 0;\r\n\t\r\n\tfor (bitidx = 0; i < GraphTraceLen; i++)\r\n\t{\r\n if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))\r\n {\r\n lc = i - lastval;\r\n lastval = i;\r\n \r\n // Switch depending on lc length:\r\n // Tolerance is 1/8 of clock rate (arbitrary)\r\n if (abs(lc-clock/4) < tolerance) {\r\n // 16T0\r\n if((i - pmc) == lc) { /* 16T0 was previous one */\r\n /* It's a PMC ! */\r\n i += (128+127+16+32+33+16)-1;\r\n lastval = i;\r\n pmc = 0;\r\n block_done = 1;\r\n }\r\n else {\r\n pmc = i;\r\n }\r\n } else if (abs(lc-clock/2) < tolerance) {\r\n // 32TO\r\n if((i - pmc) == lc) { /* 16T0 was previous one */\r\n /* It's a PMC ! */\r\n i += (128+127+16+32+33)-1;\r\n lastval = i;\r\n pmc = 0;\r\n block_done = 1;\r\n }\r\n else if(half_switch == 1) {\r\n BitStream[bitidx++] = 0;\r\n half_switch = 0;\r\n }\r\n else\r\n half_switch++;\r\n } else if (abs(lc-clock) < tolerance) {\r\n // 64TO\r\n BitStream[bitidx++] = 1;\r\n } else {\r\n // Error\r\n warnings++;\r\n if (warnings > 10)\r\n {\r\n Dbprintf(\"Error: too many detection errors, aborting.\");\r\n return 0;\r\n }\r\n }\r\n \r\n if(block_done == 1) {\r\n if(bitidx == 128) {\r\n for(j=0; j<16; j++) {\r\n Blocks[num_blocks][j] = 128*BitStream[j*8+7]+\r\n 64*BitStream[j*8+6]+\r\n 32*BitStream[j*8+5]+\r\n 16*BitStream[j*8+4]+\r\n 8*BitStream[j*8+3]+\r\n 4*BitStream[j*8+2]+\r\n 2*BitStream[j*8+1]+\r\n BitStream[j*8];\r\n }\r\n num_blocks++;\r\n }\r\n bitidx = 0;\r\n block_done = 0;\r\n half_switch = 0;\r\n }\r\n if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;\r\n else dir = 1;\r\n }\r\n if(bitidx==255)\r\n bitidx=0;\r\n warnings = 0;\r\n if(num_blocks == 4) break;\r\n\t}\r\n\tmemcpy(outBlocks, Blocks, 16*num_blocks);\r\n\treturn num_blocks;\r\n}\r\n\r\nint IsBlock0PCF7931(uint8_t *Block) {\r\n\t// Assume RFU means 0 :)\r\n\tif((memcmp(Block, \"\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x01\", 8) == 0) && memcmp(Block+9, \"\\x00\\x00\\x00\\x00\\x00\\x00\\x00\", 7) == 0) // PAC enabled\r\n return 1;\r\n\tif((memcmp(Block+9, \"\\x00\\x00\\x00\\x00\\x00\\x00\\x00\", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?\r\n return 1;\r\n\treturn 0;\r\n}\r\n\r\nint IsBlock1PCF7931(uint8_t *Block) {\r\n\t// Assume RFU means 0 :)\r\n\tif(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)\r\n if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)\r\n return 1;\r\n\t\r\n\treturn 0;\r\n}\r\n\r\n#define ALLOC 16\r\n\r\nvoid ReadPCF7931() {\r\n\tuint8_t Blocks[8][17];\r\n\tuint8_t tmpBlocks[4][16];\r\n\tint i, j, ind, ind2, n;\r\n\tint num_blocks = 0;\r\n\tint max_blocks = 8;\r\n\tint ident = 0;\r\n\tint error = 0;\r\n\tint tries = 0;\r\n\t\r\n\tmemset(Blocks, 0, 8*17*sizeof(uint8_t));\r\n\t\r\n\tdo {\r\n memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));\r\n n = DemodPCF7931((uint8_t**)tmpBlocks);\r\n if(!n)\r\n error++;\r\n if(error==10 && num_blocks == 0) {\r\n Dbprintf(\"Error, no tag or bad tag\");\r\n return;\r\n }\r\n else if (tries==20 || error==10) {\r\n Dbprintf(\"Error reading the tag\");\r\n Dbprintf(\"Here is the partial content\");\r\n goto end;\r\n }\r\n \r\n for(i=0; i= 0; ind--,ind2--) {\r\n if(ind2 < 0)\r\n ind2 = max_blocks;\r\n if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found\r\n // Dbprintf(\"Tmp %d -> Block %d\", ind, ind2);\r\n memcpy(Blocks[ind2], tmpBlocks[ind], 16);\r\n Blocks[ind2][ALLOC] = 1;\r\n num_blocks++;\r\n if(num_blocks == max_blocks) goto end;\r\n }\r\n }\r\n for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {\r\n if(ind2 > max_blocks)\r\n ind2 = 0;\r\n if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found\r\n // Dbprintf(\"Tmp %d -> Block %d\", ind, ind2);\r\n memcpy(Blocks[ind2], tmpBlocks[ind], 16);\r\n Blocks[ind2][ALLOC] = 1;\r\n num_blocks++;\r\n if(num_blocks == max_blocks) goto end;\r\n }\r\n }\r\n }\r\n }\r\n }\r\n }\r\n }\r\n tries++;\r\n if (BUTTON_PRESS()) return;\r\n\t} while (num_blocks != max_blocks);\r\nend:\r\n\tDbprintf(\"-----------------------------------------\");\r\n\tDbprintf(\"Memory content:\");\r\n\tDbprintf(\"-----------------------------------------\");\r\n\tfor(i=0; i\", i);\r\n\t}\r\n\tDbprintf(\"-----------------------------------------\");\r\n\t\r\n\treturn ;\r\n}\r\n\r\n\r\n//-----------------------------------\r\n// EM4469 / EM4305 routines\r\n//-----------------------------------\r\n#define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored\r\n#define FWD_CMD_WRITE 0xA\r\n#define FWD_CMD_READ 0x9\r\n#define FWD_CMD_DISABLE 0x5\r\n\r\n\r\nuint8_t forwardLink_data[64]; //array of forwarded bits\r\nuint8_t * forward_ptr; //ptr for forward message preparation\r\nuint8_t fwd_bit_sz; //forwardlink bit counter\r\nuint8_t * fwd_write_ptr; //forwardlink bit pointer\r\n\r\n//====================================================================\r\n// prepares command bits\r\n// see EM4469 spec\r\n//====================================================================\r\n//--------------------------------------------------------------------\r\nuint8_t Prepare_Cmd( uint8_t cmd ) {\r\n //--------------------------------------------------------------------\r\n \r\n *forward_ptr++ = 0; //start bit\r\n *forward_ptr++ = 0; //second pause for 4050 code\r\n \r\n *forward_ptr++ = cmd;\r\n cmd >>= 1;\r\n *forward_ptr++ = cmd;\r\n cmd >>= 1;\r\n *forward_ptr++ = cmd;\r\n cmd >>= 1;\r\n *forward_ptr++ = cmd;\r\n \r\n return 6; //return number of emited bits\r\n}\r\n\r\n//====================================================================\r\n// prepares address bits\r\n// see EM4469 spec\r\n//====================================================================\r\n\r\n//--------------------------------------------------------------------\r\nuint8_t Prepare_Addr( uint8_t addr ) {\r\n //--------------------------------------------------------------------\r\n \r\n register uint8_t line_parity;\r\n \r\n uint8_t i;\r\n line_parity = 0;\r\n for(i=0;i<6;i++) {\r\n *forward_ptr++ = addr;\r\n line_parity ^= addr;\r\n addr >>= 1;\r\n }\r\n \r\n *forward_ptr++ = (line_parity & 1);\r\n \r\n return 7; //return number of emited bits\r\n}\r\n\r\n//====================================================================\r\n// prepares data bits intreleaved with parity bits\r\n// see EM4469 spec\r\n//====================================================================\r\n\r\n//--------------------------------------------------------------------\r\nuint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {\r\n //--------------------------------------------------------------------\r\n \r\n register uint8_t line_parity;\r\n register uint8_t column_parity;\r\n register uint8_t i, j;\r\n register uint16_t data;\r\n \r\n data = data_low;\r\n column_parity = 0;\r\n \r\n for(i=0; i<4; i++) {\r\n line_parity = 0;\r\n for(j=0; j<8; j++) {\r\n line_parity ^= data;\r\n column_parity ^= (data & 1) << j;\r\n *forward_ptr++ = data;\r\n data >>= 1;\r\n }\r\n *forward_ptr++ = line_parity;\r\n if(i == 1)\r\n data = data_hi;\r\n }\r\n \r\n for(j=0; j<8; j++) {\r\n *forward_ptr++ = column_parity;\r\n column_parity >>= 1;\r\n }\r\n *forward_ptr = 0;\r\n \r\n return 45; //return number of emited bits\r\n}\r\n\r\n//====================================================================\r\n// Forward Link send function\r\n// Requires: forwarLink_data filled with valid bits (1 bit per byte)\r\n// fwd_bit_count set with number of bits to be sent\r\n//====================================================================\r\nvoid SendForward(uint8_t fwd_bit_count) {\r\n \r\n fwd_write_ptr = forwardLink_data;\r\n fwd_bit_sz = fwd_bit_count;\r\n \r\n LED_D_ON();\r\n \r\n //Field on\r\n FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r\n //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r\n \r\n // Give it a bit of time for the resonant antenna to settle.\r\n // And for the tag to fully power up\r\n SpinDelay(150);\r\n \r\n // force 1st mod pulse (start gap must be longer for 4305)\r\n fwd_bit_sz--; //prepare next bit modulation\r\n fwd_write_ptr++;\r\n FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off\r\n SpinDelayUs(55*8); //55 cycles off (8us each)for 4305\r\n FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r\n //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);//field on\r\n SpinDelayUs(16*8); //16 cycles on (8us each)\r\n \r\n // now start writting\r\n while(fwd_bit_sz-- > 0) { //prepare next bit modulation\r\n if(((*fwd_write_ptr++) & 1) == 1)\r\n SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)\r\n else {\r\n //These timings work for 4469/4269/4305 (with the 55*8 above)\r\n FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off\r\n SpinDelayUs(23*8); //16-4 cycles off (8us each)\r\n FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r\n //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);//field on\r\n SpinDelayUs(9*8); //16 cycles on (8us each)\r\n }\r\n }\r\n}\r\n\r\nvoid EM4xLogin(uint32_t Password) {\r\n \r\n uint8_t fwd_bit_count;\r\n \r\n forward_ptr = forwardLink_data;\r\n fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );\r\n fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );\r\n \r\n SendForward(fwd_bit_count);\r\n \r\n //Wait for command to complete\r\n SpinDelay(20);\r\n \r\n}\r\n\r\nvoid EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {\r\n \r\n uint8_t fwd_bit_count;\r\n uint8_t *dest = (uint8_t *)BigBuf;\r\n int m=0, i=0;\r\n \r\n //If password mode do login\r\n if (PwdMode == 1) EM4xLogin(Pwd);\r\n \r\n forward_ptr = forwardLink_data;\r\n fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );\r\n fwd_bit_count += Prepare_Addr( Address );\r\n \r\n m = sizeof(BigBuf);\r\n // Clear destination buffer before sending the command\r\n memset(dest, 128, m);\r\n // Connect the A/D to the peak-detected low-frequency path.\r\n SetAdcMuxFor(GPIO_MUXSEL_LOPKD);\r\n // Now set up the SSC to get the ADC samples that are now streaming at us.\r\n FpgaSetupSsc();\r\n \r\n SendForward(fwd_bit_count);\r\n \r\n // Now do the acquisition\r\n i = 0;\r\n for(;;) {\r\n if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {\r\n AT91C_BASE_SSC->SSC_THR = 0x43;\r\n }\r\n if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {\r\n dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;\r\n i++;\r\n if (i >= m) break;\r\n }\r\n }\r\n FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off\r\n LED_D_OFF();\r\n}\r\n\r\nvoid EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {\r\n \r\n uint8_t fwd_bit_count;\r\n \r\n //If password mode do login\r\n if (PwdMode == 1) EM4xLogin(Pwd);\r\n \r\n forward_ptr = forwardLink_data;\r\n fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );\r\n fwd_bit_count += Prepare_Addr( Address );\r\n fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );\r\n \r\n SendForward(fwd_bit_count);\r\n \r\n //Wait for write to complete\r\n SpinDelay(20);\r\n FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off\r\n LED_D_OFF();\r\n}\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/lfops_rcv_works.txt", "content": "//-----------------------------------------------------------------------------\r\n// This code is licensed to you under the terms of the GNU GPL, version 2 or,\r\n// at your option, any later version. See the LICENSE.txt file for the text of\r\n// the license.\r\n//-----------------------------------------------------------------------------\r\n// Miscellaneous routines for low frequency tag operations.\r\n// Tags supported here so far are Texas Instruments (TI), HID\r\n// Also routines for raw mode reading/simulating of LF waveform\r\n//-----------------------------------------------------------------------------\r\n\r\n#include \"proxmark3.h\"\r\n#include \"apps.h\"\r\n#include \"util.h\"\r\n#include \"hitag2.h\"\r\n#include \"crc16.h\"\r\n#include \"string.h\"\r\n\r\nvolatile unsigned long timer0_millis = 0; \r\nvoid AcquireRawAdcSamples125k(int at134khz)\r\n\r\n\r\n{\r\n\r\n\r\n\tif (at134khz)\r\n\t\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r\n\telse\r\n\t\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 94); //125Khz\r\n\r\n\tAcquireTiType();\r\n}\r\n\r\n\r\n\r\n// split into two routines so we can avoid timing issues after sending commands //\r\nvoid DoAcquisition125k(void)\r\n{\r\n\tuint8_t *dest = (uint8_t *)BigBuf;\r\n\tint n = sizeof(BigBuf);\r\n\tint i;\r\n\r\n\tmemset(dest, 0, n);\r\n\ti = 0;\r\n\tfor(;;) {\r\n\t\tif (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {\r\n\t\t\tAT91C_BASE_SSC->SSC_THR = 0x43;\r\n\t\t\tLED_D_ON();\r\n\t\t}\r\n\t\tif (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {\r\n\t\t\tdest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;\r\n\t\t\ti++;\r\n\t\t\tLED_D_OFF();\r\n\t\t\tif (i >= n) break;\r\n\t\t}\r\n\t}\r\n\tDbprintf(\"buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...\",\r\n\t\t\tdest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);\r\n}\r\n\r\nvoid ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)\r\n{\r\n\tint at134khz;\r\n\r\n\t/* Make sure the tag is reset */\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\tSpinDelay(2500);\r\n\r\n\t// see if 'h' was specified\r\n\tif (command[strlen((char *) command) - 1] == 'h')\r\n\t\tat134khz = TRUE;\r\n\telse\r\n\t\tat134khz = FALSE;\r\n\r\n\tif (at134khz)\r\n\t\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r\n\telse\r\n\t\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r\n\r\n\t////FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r\n\r\n\t// Give it a bit of time for the resonant antenna to settle.\r\n\tSpinDelay(50);\r\n\t// And a little more time for the tag to fully power up\r\n\tSpinDelay(2000);\r\n\r\n\t// Now set up the SSC to get the ADC samples that are now streaming at us.\r\n\tFpgaSetupSsc();\r\n\r\n\t// now modulate the reader field\r\n\twhile(*command != '\\0' && *command != ' ') {\r\n\t\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\t\tLED_D_OFF();\r\n\t\tSpinDelayUs(delay_off);\r\n\t\tif (at134khz)\r\n\t\t\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r\n\t\telse\r\n\t\t\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r\n\r\n\t\t////FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r\n\t\tLED_D_ON();\r\n\t\tif(*(command++) == '0')\r\n\t\t\tSpinDelayUs(period_0);\r\n\t\telse\r\n\t\t\tSpinDelayUs(period_1);\r\n\t}\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\tLED_D_OFF();\r\n\tSpinDelayUs(delay_off);\r\n\tif (at134khz)\r\n\t\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r\n\telse\r\n\t\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r\n\r\n\t////FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r\n\r\n\t// now do the read\r\n\tDoAcquisition125k();\r\n}\r\n\r\n/* blank r/w tag data stream\r\n...0000000000000000 01111111\r\n1010101010101010101010101010101010101010101010101010101010101010\r\n0011010010100001\r\n01111111\r\n101010101010101[0]000...\r\n\r\n[5555fe852c5555555555555555fe0000]\r\n*/\r\nvoid ReadTItag(void)\r\n{\r\n\t// some hardcoded initial params\r\n\t// when we read a TI tag we sample the zerocross line at 2Mhz\r\n\t// TI tags modulate a 1 as 16 cycles of 123.2Khz\r\n\t// TI tags modulate a 0 as 16 cycles of 134.2Khz\r\n\t#define FSAMPLE 2000000\r\n\t#define FREQLO 123200\r\n\t#define FREQHI 134200\r\n\r\n\tsigned char *dest = (signed char *)BigBuf;\r\n\tint n = sizeof(BigBuf);\r\n//\tint *dest = GraphBuffer;\r\n//\tint n = GraphTraceLen;\r\n\r\n\t// 128 bit shift register [shift3:shift2:shift1:shift0]\r\n\tuint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;\r\n\r\n\tint i, cycles=0, samples=0;\r\n\t// how many sample points fit in 16 cycles of each frequency\r\n\tuint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;\r\n\t// when to tell if we're close enough to one freq or another\r\n\tuint32_t threshold = (sampleslo - sampleshi + 1)>>1;\r\n\r\n\t// TI tags charge at 134.2Khz\r\n\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 94); //134.8Khz\r\n\r\n\t// Place FPGA in passthrough mode, in this mode the CROSS_LO line\r\n\t// connects to SSP_DIN and the SSP_DOUT logic level controls\r\n\t// whether we're modulating the antenna (high)\r\n\t// or listening to the antenna (low)\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);\r\n\r\n\t// get TI tag data into the buffer\r\n\tAcquireTiType();\r\n\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\r\n\tfor (i=0; i0) ) {\r\n\t\t\tcycles++;\r\n\t\t\t// after 16 cycles, measure the frequency\r\n\t\t\tif (cycles>15) {\r\n\t\t\t\tcycles=0;\r\n\t\t\t\tsamples=i-samples; // number of samples in these 16 cycles\r\n\r\n\t\t\t\t// TI bits are coming to us lsb first so shift them\r\n\t\t\t\t// right through our 128 bit right shift register\r\n\t\t\t shift0 = (shift0>>1) | (shift1 << 31);\r\n\t\t\t shift1 = (shift1>>1) | (shift2 << 31);\r\n\t\t\t shift2 = (shift2>>1) | (shift3 << 31);\r\n\t\t\t shift3 >>= 1;\r\n\r\n\t\t\t\t// check if the cycles fall close to the number\r\n\t\t\t\t// expected for either the low or high frequency\r\n\t\t\t\tif ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {\r\n\t\t\t\t\t// low frequency represents a 1\r\n\t\t\t\t\tshift3 |= (1<<31);\r\n\t\t\t\t} else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {\r\n\t\t\t\t\t// high frequency represents a 0\r\n\t\t\t\t} else {\r\n\t\t\t\t\t// probably detected a gay waveform or noise\r\n\t\t\t\t\t// use this as gaydar or discard shift register and start again\r\n\t\t\t\t\tshift3 = shift2 = shift1 = shift0 = 0;\r\n\t\t\t\t}\r\n\t\t\t\tsamples = i;\r\n\r\n\t\t\t\t// for each bit we receive, test if we've detected a valid tag\r\n\r\n\t\t\t\t// if we see 17 zeroes followed by 6 ones, we might have a tag\r\n\t\t\t\t// remember the bits are backwards\r\n\t\t\t\tif ( ((shift0 & 0x7fffff) == 0x7e0000) ) {\r\n\t\t\t\t\t// if start and end bytes match, we have a tag so break out of the loop\r\n\t\t\t\t\tif ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {\r\n\t\t\t\t\t\tcycles = 0xF0B; //use this as a flag (ugly but whatever)\r\n\t\t\t\t\t\tbreak;\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t}\r\n\t}\r\n\r\n\t// if flag is set we have a tag\r\n\tif (cycles!=0xF0B) {\r\n\t\tDbpString(\"Info: No valid tag detected.\");\r\n\t} else {\r\n\t // put 64 bit data into shift1 and shift0\r\n\t shift0 = (shift0>>24) | (shift1 << 8);\r\n\t shift1 = (shift1>>24) | (shift2 << 8);\r\n\r\n\t\t// align 16 bit crc into lower half of shift2\r\n\t shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;\r\n\r\n\t\t// if r/w tag, check ident match\r\n\t\tif ( shift3&(1<<15) ) {\r\n\t\t\tDbpString(\"Info: TI tag is rewriteable\");\r\n\t\t\t// only 15 bits compare, last bit of ident is not valid\r\n\t\t\tif ( ((shift3>>16)^shift0)&0x7fff ) {\r\n\t\t\t\tDbpString(\"Error: Ident mismatch!\");\r\n\t\t\t} else {\r\n\t\t\t\tDbpString(\"Info: TI tag ident is valid\");\r\n\t\t\t}\r\n\t\t} else {\r\n\t\t\tDbpString(\"Info: TI tag is readonly\");\r\n\t\t}\r\n\r\n\t\t// WARNING the order of the bytes in which we calc crc below needs checking\r\n\t\t// i'm 99% sure the crc algorithm is correct, but it may need to eat the\r\n\t\t// bytes in reverse or something\r\n\t\t// calculate CRC\r\n\t\tuint32_t crc=0;\r\n\r\n\t \tcrc = update_crc16(crc, (shift0)&0xff);\r\n\t\tcrc = update_crc16(crc, (shift0>>8)&0xff);\r\n\t\tcrc = update_crc16(crc, (shift0>>16)&0xff);\r\n\t\tcrc = update_crc16(crc, (shift0>>24)&0xff);\r\n\t\tcrc = update_crc16(crc, (shift1)&0xff);\r\n\t\tcrc = update_crc16(crc, (shift1>>8)&0xff);\r\n\t\tcrc = update_crc16(crc, (shift1>>16)&0xff);\r\n\t\tcrc = update_crc16(crc, (shift1>>24)&0xff);\r\n\r\n\t\tDbprintf(\"Info: Tag data: %x%08x, crc=%x\",\r\n\t\t\t(unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);\r\n\t\tif (crc != (shift2&0xffff)) {\r\n\t\t\tDbprintf(\"Error: CRC mismatch, expected %x\", (unsigned int)crc);\r\n\t\t} else {\r\n\t\t\tDbpString(\"Info: CRC is good\");\r\n\t\t}\r\n\t}\r\n}\r\n\r\nvoid WriteTIbyte(uint8_t b)\r\n{\r\n\tint i = 0;\r\n\t//prolog\r\n\r\n\t\t\r\n\t//SpinDelayUs(1000);\r\n\t// modulate antenna\r\n\tHIGH(GPIO_SSC_DOUT);\r\n\tSpinDelayUs(540);\r\n\tLOW(GPIO_SSC_DOUT);\r\n\t// modulate 8 bits out to the antenna\r\n\tfor (i=7; i>=0; i--)\r\n\t{\r\n\t\tif (b&(1<PIO_PDR = GPIO_SSC_DIN;\r\n\tAT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;\r\n\r\n\t// steal this pin from the SSP and use it to control the modulation\r\n\tAT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;\r\n\tAT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r\n\r\n\tAT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;\r\n\tAT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;\r\n\r\n\t// Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long\r\n\t// 48/2 = 24 MHz clock must be divided by 12\r\n\tAT91C_BASE_SSC->SSC_CMR = 12;\r\n\r\n\tAT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);\r\n\tAT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;\r\n\tAT91C_BASE_SSC->SSC_TCMR = 0;\r\n\tAT91C_BASE_SSC->SSC_TFMR = 0;\r\n\r\n\t\r\n\r\n\t// modulate antenna\r\n\t//HIGH(GPIO_SSC_DOUT);\r\n\r\n\t// Charge TI tag for 50ms.\r\n\tSpinDelay(50);\r\n\r\n\t// stop modulating antenna and listen\r\n\t//LED_A_ON();\r\n\tLOW(GPIO_SSC_DOUT);\r\n\t//ti = GetTickCount();\n\r\n\t//SpinDelay(1000);\n\r\n\t//ti = GetTickCount() - ti;\n\t\r\n\t//Dbprintf(\"timer(1s): %d t=%d\", ti, GetTickCount());\r\n\t//LED_A_OFF();\t\r\n\tLED_D_ON();\r\n\ti = 0;\r\n\tti = GetTickCount();\n\r\n\tfor(;;) {\r\n\t\tif(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {\r\n\t\t\tBigBuf[i] = AT91C_BASE_SSC->SSC_RHR;\t// store 32 bit values in buffer\r\n\t\t\ti++; if(i >= 40000) break;\r\n\t\t}\r\n\t\tWDT_HIT();\r\n\t}\r\n\tti = GetTickCount() - ti;\n\t\r\n\tDbprintf(\"timer(1s): %d t=%d\", ti, GetTickCount());\r\n\tLED_D_OFF();\r\n\t// return stolen pin to SSP\r\n\tAT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;\r\n\tAT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;\r\n\r\n}\r\n\r\n// arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc\r\n// if crc provided, it will be written with the data verbatim (even if bogus)\r\n// if not provided a valid crc will be computed from the data and written.\r\nvoid WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)\r\n{\r\n\tint i;\r\n\t//if(crc == 0) {\r\n\t //\tcrc = update_crc16(crc, (idlo)&0xff);\r\n\t//\tcrc = update_crc16(crc, (idlo>>8)&0xff);\r\n\t//\tcrc = update_crc16(crc, (idlo>>16)&0xff);\r\n\t//\tcrc = update_crc16(crc, (idlo>>24)&0xff);\r\n\t//\tcrc = update_crc16(crc, (idhi)&0xff);\r\n\t//\tcrc = update_crc16(crc, (idhi>>8)&0xff);\r\n\t//\tcrc = update_crc16(crc, (idhi>>16)&0xff);\r\n\t//\tcrc = update_crc16(crc, (idhi>>24)&0xff);\r\n\t//}\r\n\t//Dbprintf(\"Writing to tag: %x%08x, crc=%x\",\r\n\t//\t(unsigned int) idhi, (unsigned int) idlo, crc);\r\n\r\n\t// TI tags charge at 134.2Khz //88 is 125\r\n\t\r\n\r\n\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 94); //134.8Khz\r\n\t// Place FPGA in passthrough mode, in this mode the CROSS_LO line\r\n\t// connects to SSP_DIN and the SSP_DOUT logic level controls\r\n\t// whether we're modulating the antenna (high)\r\n\t// or listening to the antenna (low)\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);\r\n\tLED_A_ON();\r\n\r\n\t// steal this pin from the SSP and use it to control the modulation\r\n\tAT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;\r\n\tAT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r\n\r\n\t// writing algorithm:\r\n\t// a high bit consists of a field off for 1ms and field on for 1ms\r\n\t// a low bit consists of a field off for 0.3ms and field on for 1.7ms\r\n\t// initiate a charge time of 50ms (field on) then immediately start writing bits\r\n\t// start by writing 0xBB (keyword) and 0xEB (password)\r\n\t// then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)\r\n\t// finally end with 0x0300 (write frame)\r\n\t// all data is sent lsb firts\r\n\t// finish with 15ms programming time\r\n\r\n\t// modulate antenna\r\n\t//HIGH(GPIO_SSC_DOUT);\r\n\t//SpinDelay(10000);\t// charge time\r\n\tfor(i = 0; i < 10; i++){\r\n\tWriteTIbyte(0xf0);\r\n\tWriteTIbyte(0x00); \r\n\tWriteTIbyte( 0x0f );\r\n\tWriteTIbyte(0x01);\r\n\tWriteTIbyte(0x00);\r\n \r\n\tWriteTIbyte(0x07);\r\n\tWriteTIbyte(0x2d); \r\n\tWriteTIbyte( 0x00 );\r\n\tWriteTIbyte(0x09);\r\n\tWriteTIbyte(0x00);\r\n\r\n\tWriteTIbyte(0x01);\r\n\tWriteTIbyte(0x0B); \r\n\tWriteTIbyte( 0x08 );\r\n\tWriteTIbyte(0x0D);\r\n\tWriteTIbyte(0x0A);\r\n\r\n\tWriteTIbyte(0x18);\r\n\tWriteTIbyte(0x1a); \r\n\tWriteTIbyte( 0x1a );\r\n\tWriteTIbyte( 0xc4 );\t\r\n\r\n\r\n\t//LOW(GPIO_SSC_DOUT);\r\n\tSpinDelay(100);\r\n\t\r\n\tWriteTIbyte(0xf0);\r\n\tWriteTIbyte(0x06); \r\n\tWriteTIbyte( 0x04 );\r\n\tWriteTIbyte(0x01);\r\n\tWriteTIbyte(0x06);\r\n \r\n\tWriteTIbyte(0x07);\r\n\tWriteTIbyte(0x2d); \r\n\tWriteTIbyte( 0x45 );\r\n\t\r\n\r\n\tSpinDelay(1000);\r\n\t}\r\n\r\n\r\n\tLED_A_OFF();\r\n\r\n\t// get TI tag data into the buffer\r\n\t//AcquireTiType();\r\n\r\n\t//FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\tDbpString(\"Done\");\r\n}\r\n\r\nvoid SimulateTagLowFrequency(int period, int gap, int ledcontrol)\r\n{\r\n\tint i;\r\n\tuint8_t *tab = (uint8_t *)BigBuf;\r\n \r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);\r\n \r\n\tAT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;\r\n \r\n\tAT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r\n\tAT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;\r\n \r\n#define SHORT_COIL()\tLOW(GPIO_SSC_DOUT)\r\n#define OPEN_COIL()\t\tHIGH(GPIO_SSC_DOUT)\r\n \r\n\ti = 0;\r\n\tfor(;;) {\r\n\t\twhile(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {\r\n\t\t\tif(BUTTON_PRESS()) {\r\n\t\t\t\tDbpString(\"Stopped\");\r\n\t\t\t\treturn;\r\n\t\t\t}\r\n\t\t\tWDT_HIT();\r\n\t\t}\r\n \r\n\t\tif (ledcontrol)\r\n\t\t\tLED_D_ON();\r\n \r\n\t\tif(tab[i])\r\n\t\t\tOPEN_COIL();\r\n\t\telse\r\n\t\t\tSHORT_COIL();\r\n \r\n\t\tif (ledcontrol)\r\n\t\t\tLED_D_OFF();\r\n \r\n\t\twhile(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {\r\n\t\t\tif(BUTTON_PRESS()) {\r\n\t\t\t\tDbpString(\"Stopped\");\r\n\t\t\t\treturn;\r\n\t\t\t}\r\n\t\t\tWDT_HIT();\r\n\t\t}\r\n \r\n\t\ti++;\r\n\t\tif(i == period) {\r\n\t\t\ti = 0;\r\n\t\t\tif (gap) {\r\n\t\t\t\tSHORT_COIL();\r\n\t\t\t\tSpinDelayUs(gap);\r\n\t\t\t}\r\n\t\t}\r\n\t}\r\n}\r\n\r\n#define DEBUG_FRAME_CONTENTS 1\r\nvoid SimulateTagLowFrequencyBidir(int divisor, int t0)\r\n{\r\n}\r\n\r\n// compose fc/8 fc/10 waveform\r\nstatic void fc(int c, int *n) {\r\n\tuint8_t *dest = (uint8_t *)BigBuf;\r\n\tint idx;\r\n\r\n\t// for when we want an fc8 pattern every 4 logical bits\r\n\tif(c==0) {\r\n\t\tdest[((*n)++)]=1;\r\n\t\tdest[((*n)++)]=1;\r\n\t\tdest[((*n)++)]=0;\r\n\t\tdest[((*n)++)]=0;\r\n\t\tdest[((*n)++)]=0;\r\n\t\tdest[((*n)++)]=0;\r\n\t\tdest[((*n)++)]=0;\r\n\t\tdest[((*n)++)]=0;\r\n\t}\r\n\t//\tan fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples\r\n\tif(c==8) {\r\n\t\tfor (idx=0; idx<6; idx++) {\r\n\t\t\tdest[((*n)++)]=1;\r\n\t\t\tdest[((*n)++)]=1;\r\n\t\t\tdest[((*n)++)]=0;\r\n\t\t\tdest[((*n)++)]=0;\r\n\t\t\tdest[((*n)++)]=0;\r\n\t\t\tdest[((*n)++)]=0;\r\n\t\t\tdest[((*n)++)]=0;\r\n\t\t\tdest[((*n)++)]=0;\r\n\t\t}\r\n\t}\r\n\r\n\t//\tan fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples\r\n\tif(c==10) {\r\n\t\tfor (idx=0; idx<5; idx++) {\r\n\t\t\tdest[((*n)++)]=1;\r\n\t\t\tdest[((*n)++)]=1;\r\n\t\t\tdest[((*n)++)]=1;\r\n\t\t\tdest[((*n)++)]=0;\r\n\t\t\tdest[((*n)++)]=0;\r\n\t\t\tdest[((*n)++)]=0;\r\n\t\t\tdest[((*n)++)]=0;\r\n\t\t\tdest[((*n)++)]=0;\r\n\t\t\tdest[((*n)++)]=0;\r\n\t\t\tdest[((*n)++)]=0;\r\n\t\t}\r\n\t}\r\n}\r\n\r\n// prepare a waveform pattern in the buffer based on the ID given then\r\n// simulate a HID tag until the button is pressed\r\nvoid CmdHIDsimTAG(int hi, int lo, int ledcontrol)\r\n{\r\n\tint n=0, i=0;\r\n\t/*\r\n\t HID tag bitstream format\r\n\t The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits\r\n\t A 1 bit is represented as 6 fc8 and 5 fc10 patterns\r\n\t A 0 bit is represented as 5 fc10 and 6 fc8 patterns\r\n\t A fc8 is inserted before every 4 bits\r\n\t A special start of frame pattern is used consisting a0b0 where a and b are neither 0\r\n\t nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)\r\n\t*/\r\n\r\n\tif (hi>0xFFF) {\r\n\t\tDbpString(\"Tags can only have 44 bits.\");\r\n\t\treturn;\r\n\t}\r\n\tfc(0,&n);\r\n\t// special start of frame marker containing invalid bit sequences\r\n\tfc(8, &n);\tfc(8, &n);\t// invalid\r\n\tfc(8, &n);\tfc(10, &n); // logical 0\r\n\tfc(10, &n);\tfc(10, &n); // invalid\r\n\tfc(8, &n);\tfc(10, &n); // logical 0\r\n\r\n\tWDT_HIT();\r\n\t// manchester encode bits 43 to 32\r\n\tfor (i=11; i>=0; i--) {\r\n\t\tif ((i%4)==3) fc(0,&n);\r\n\t\tif ((hi>>i)&1) {\r\n\t\t\tfc(10, &n);\tfc(8, &n);\t\t// low-high transition\r\n\t\t} else {\r\n\t\t\tfc(8, &n);\tfc(10, &n);\t\t// high-low transition\r\n\t\t}\r\n\t}\r\n\r\n\tWDT_HIT();\r\n\t// manchester encode bits 31 to 0\r\n\tfor (i=31; i>=0; i--) {\r\n\t\tif ((i%4)==3) fc(0,&n);\r\n\t\tif ((lo>>i)&1) {\r\n\t\t\tfc(10, &n);\tfc(8, &n);\t\t// low-high transition\r\n\t\t} else {\r\n\t\t\tfc(8, &n);\tfc(10, &n);\t\t// high-low transition\r\n\t\t}\r\n\t}\r\n\r\n\tif (ledcontrol)\r\n\t\tLED_A_ON();\r\n\tSimulateTagLowFrequency(n, 0, ledcontrol);\r\n\r\n\tif (ledcontrol)\r\n\t\tLED_A_OFF();\r\n}\r\n\r\n\r\n// loop to capture raw HID waveform then FSK demodulate the TAG ID from it\r\nvoid CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)\r\n{\r\n\tuint8_t *dest = (uint8_t *)BigBuf;\r\n\tint m=0, n=0, i=0, idx=0, found=0, lastval=0;\r\n uint32_t hi2=0, hi=0, lo=0;\r\n\r\n\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r\n\t//FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r\n\r\n\t// Connect the A/D to the peak-detected low-frequency path.\r\n\tSetAdcMuxFor(GPIO_MUXSEL_LOPKD);\r\n\r\n\t// Give it a bit of time for the resonant antenna to settle.\r\n\tSpinDelay(50);\r\n\r\n\t// Now set up the SSC to get the ADC samples that are now streaming at us.\r\n\tFpgaSetupSsc();\r\n\r\n\tfor(;;) {\r\n\t\tWDT_HIT();\r\n\t\tif (ledcontrol)\r\n\t\t\tLED_A_ON();\r\n\t\tif(BUTTON_PRESS()) {\r\n\t\t\tDbpString(\"Stopped\");\r\n\t\t\tif (ledcontrol)\r\n\t\t\t\tLED_A_OFF();\r\n\t\t\treturn;\r\n\t\t}\r\n\r\n\t\ti = 0;\r\n\t\tm = sizeof(BigBuf);\r\n\t\tmemset(dest,128,m);\r\n\t\tfor(;;) {\r\n\t\t\tif(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r\n\t\t\t\tAT91C_BASE_SSC->SSC_THR = 0x43;\r\n\t\t\t\tif (ledcontrol)\r\n\t\t\t\t\tLED_D_ON();\r\n\t\t\t}\r\n\t\t\tif(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r\n\t\t\t\tdest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;\r\n\t\t\t\t// we don't care about actual value, only if it's more or less than a\r\n\t\t\t\t// threshold essentially we capture zero crossings for later analysis\r\n\t\t\t\tif(dest[i] < 127) dest[i] = 0; else dest[i] = 1;\r\n\t\t\t\ti++;\r\n\t\t\t\tif (ledcontrol)\r\n\t\t\t\t\tLED_D_OFF();\r\n\t\t\t\tif(i >= m) {\r\n\t\t\t\t\tbreak;\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t}\r\n\r\n\t\t// FSK demodulator\r\n\r\n\t\t// sync to first lo-hi transition\r\n\t\tfor( idx=1; idx>1) & 0xFFFF);\r\n }\r\n else {\r\n Dbprintf(\"TAG ID: %x%08x (%d)\",\r\n (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);\r\n }\r\n\t\t\t\t\t/* if we're only looking for one tag */\r\n\t\t\t\t\tif (findone)\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t*high = hi;\r\n\t\t\t\t\t\t*low = lo;\r\n\t\t\t\t\t\treturn;\r\n\t\t\t\t\t}\r\n hi2=0;\r\n\t\t\t\t\thi=0;\r\n\t\t\t\t\tlo=0;\r\n\t\t\t\t\tfound=0;\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\tif (found) {\r\n\t\t\t\tif (dest[idx] && (!dest[idx+1]) ) {\r\n hi2=(hi2<<1)|(hi>>31);\r\n\t\t\t\t\thi=(hi<<1)|(lo>>31);\r\n\t\t\t\t\tlo=(lo<<1)|0;\r\n\t\t\t\t} else if ( (!dest[idx]) && dest[idx+1]) {\r\n hi2=(hi2<<1)|(hi>>31);\r\n\t\t\t\t\thi=(hi<<1)|(lo>>31);\r\n\t\t\t\t\tlo=(lo<<1)|1;\r\n\t\t\t\t} else {\r\n\t\t\t\t\tfound=0;\r\n hi2=0;\r\n\t\t\t\t\thi=0;\r\n\t\t\t\t\tlo=0;\r\n\t\t\t\t}\r\n\t\t\t\tidx++;\r\n\t\t\t}\r\n\t\t\tif ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) )\r\n\t\t\t{\r\n\t\t\t\tfound=1;\r\n\t\t\t\tidx+=6;\r\n\t\t\t\tif (found && (hi|lo)) {\r\n if (hi2 != 0){\r\n Dbprintf(\"TAG ID: %x%08x%08x (%d)\",\r\n (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);\r\n }\r\n else {\r\n Dbprintf(\"TAG ID: %x%08x (%d)\",\r\n (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);\r\n }\r\n\t\t\t\t\t/* if we're only looking for one tag */\r\n\t\t\t\t\tif (findone)\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t*high = hi;\r\n\t\t\t\t\t\t*low = lo;\r\n\t\t\t\t\t\treturn;\r\n\t\t\t\t\t}\r\n hi2=0;\r\n\t\t\t\t\thi=0;\r\n\t\t\t\t\tlo=0;\r\n\t\t\t\t\tfound=0;\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t}\r\n\t\tWDT_HIT();\r\n\t}\r\n}\r\n\r\n/*------------------------------\r\n * T5555/T5557/T5567 routines\r\n *------------------------------\r\n */\r\n\r\n/* T55x7 configuration register definitions */\r\n#define T55x7_POR_DELAY\t\t\t0x00000001\r\n#define T55x7_ST_TERMINATOR\t\t0x00000008\r\n#define T55x7_PWD\t\t\t0x00000010\r\n#define T55x7_MAXBLOCK_SHIFT\t\t5\r\n#define T55x7_AOR\t\t\t0x00000200\r\n#define T55x7_PSKCF_RF_2\t\t0\r\n#define T55x7_PSKCF_RF_4\t\t0x00000400\r\n#define T55x7_PSKCF_RF_8\t\t0x00000800\r\n#define T55x7_MODULATION_DIRECT\t\t0\r\n#define T55x7_MODULATION_PSK1\t\t0x00001000\r\n#define T55x7_MODULATION_PSK2\t\t0x00002000\r\n#define T55x7_MODULATION_PSK3\t\t0x00003000\r\n#define T55x7_MODULATION_FSK1\t\t0x00004000\r\n#define T55x7_MODULATION_FSK2\t\t0x00005000\r\n#define T55x7_MODULATION_FSK1a\t\t0x00006000\r\n#define T55x7_MODULATION_FSK2a\t\t0x00007000\r\n#define T55x7_MODULATION_MANCHESTER\t0x00008000\r\n#define T55x7_MODULATION_BIPHASE\t0x00010000\r\n#define T55x7_BITRATE_RF_8\t\t0\r\n#define T55x7_BITRATE_RF_16\t\t0x00040000\r\n#define T55x7_BITRATE_RF_32\t\t0x00080000\r\n#define T55x7_BITRATE_RF_40\t\t0x000C0000\r\n#define T55x7_BITRATE_RF_50\t\t0x00100000\r\n#define T55x7_BITRATE_RF_64\t\t0x00140000\r\n#define T55x7_BITRATE_RF_100\t\t0x00180000\r\n#define T55x7_BITRATE_RF_128\t\t0x001C0000\r\n\r\n/* T5555 (Q5) configuration register definitions */\r\n#define T5555_ST_TERMINATOR\t\t0x00000001\r\n#define T5555_MAXBLOCK_SHIFT\t\t0x00000001\r\n#define T5555_MODULATION_MANCHESTER\t0\r\n#define T5555_MODULATION_PSK1\t\t0x00000010\r\n#define T5555_MODULATION_PSK2\t\t0x00000020\r\n#define T5555_MODULATION_PSK3\t\t0x00000030\r\n#define T5555_MODULATION_FSK1\t\t0x00000040\r\n#define T5555_MODULATION_FSK2\t\t0x00000050\r\n#define T5555_MODULATION_BIPHASE\t0x00000060\r\n#define T5555_MODULATION_DIRECT\t\t0x00000070\r\n#define T5555_INVERT_OUTPUT\t\t0x00000080\r\n#define T5555_PSK_RF_2\t\t\t0\r\n#define T5555_PSK_RF_4\t\t\t0x00000100\r\n#define T5555_PSK_RF_8\t\t\t0x00000200\r\n#define T5555_USE_PWD\t\t\t0x00000400\r\n#define T5555_USE_AOR\t\t\t0x00000800\r\n#define T5555_BITRATE_SHIFT\t\t12\r\n#define T5555_FAST_WRITE\t\t0x00004000\r\n#define T5555_PAGE_SELECT\t\t0x00008000\r\n\r\n/*\r\n * Relevant times in microsecond\r\n * To compensate antenna falling times shorten the write times\r\n * and enlarge the gap ones.\r\n */\r\n#define START_GAP 250\r\n#define WRITE_GAP 160\r\n#define WRITE_0 144 // 192\r\n#define WRITE_1 400 // 432 for T55x7; 448 for E5550\r\n\r\n// Write one bit to card\r\nvoid T55xxWriteBit(int bit)\r\n{\r\n\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r\n\t//FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r\n\tif (bit == 0)\r\n\t\tSpinDelayUs(WRITE_0);\r\n\telse\r\n\t\tSpinDelayUs(WRITE_1);\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\tSpinDelayUs(WRITE_GAP);\r\n}\r\n\r\n// Write one card block in page 0, no lock\r\nvoid T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)\r\n{\r\n\tunsigned int i;\r\n\r\n\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r\n\t//FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r\n\r\n\t// Give it a bit of time for the resonant antenna to settle.\r\n\t// And for the tag to fully power up\r\n\tSpinDelay(150);\r\n\r\n\t// Now start writting\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\tSpinDelayUs(START_GAP);\r\n\r\n\t// Opcode\r\n\tT55xxWriteBit(1);\r\n\tT55xxWriteBit(0); //Page 0\r\n if (PwdMode == 1){\r\n // Pwd\r\n for (i = 0x80000000; i != 0; i >>= 1)\r\n T55xxWriteBit(Pwd & i);\r\n }\r\n\t// Lock bit\r\n\tT55xxWriteBit(0);\r\n\r\n\t// Data\r\n\tfor (i = 0x80000000; i != 0; i >>= 1)\r\n\t\tT55xxWriteBit(Data & i);\r\n\r\n\t// Block\r\n\tfor (i = 0x04; i != 0; i >>= 1)\r\n\t\tT55xxWriteBit(Block & i);\r\n\r\n\t// Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,\r\n\t// so wait a little more)\r\n\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r\n\t//FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r\n\tSpinDelay(20);\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n}\r\n\r\n// Read one card block in page 0\r\nvoid T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)\r\n{\r\n\tuint8_t *dest = (uint8_t *)BigBuf;\r\n\tint m=0, i=0;\r\n \r\n\tm = sizeof(BigBuf);\r\n // Clear destination buffer before sending the command\r\n\tmemset(dest, 128, m);\r\n\t// Connect the A/D to the peak-detected low-frequency path.\r\n\tSetAdcMuxFor(GPIO_MUXSEL_LOPKD);\r\n\t// Now set up the SSC to get the ADC samples that are now streaming at us.\r\n\tFpgaSetupSsc();\r\n \r\n\tLED_D_ON();\r\n\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r\n\t//FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r\n \r\n\t// Give it a bit of time for the resonant antenna to settle.\r\n\t// And for the tag to fully power up\r\n\tSpinDelay(150);\r\n \r\n\t// Now start writting\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\tSpinDelayUs(START_GAP);\r\n \r\n\t// Opcode\r\n\tT55xxWriteBit(1);\r\n\tT55xxWriteBit(0); //Page 0\r\n\tif (PwdMode == 1){\r\n\t\t// Pwd\r\n\t\tfor (i = 0x80000000; i != 0; i >>= 1)\r\n\t\t\tT55xxWriteBit(Pwd & i);\r\n\t}\r\n\t// Lock bit\r\n\tT55xxWriteBit(0);\r\n\t// Block\r\n\tfor (i = 0x04; i != 0; i >>= 1)\r\n\t\tT55xxWriteBit(Block & i);\r\n \r\n // Turn field on to read the response\r\n\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r\n\t//FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r\n \r\n\t// Now do the acquisition\r\n\ti = 0;\r\n\tfor(;;) {\r\n\t\tif (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {\r\n\t\t\tAT91C_BASE_SSC->SSC_THR = 0x43;\r\n\t\t}\r\n\t\tif (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {\r\n\t\t\tdest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;\r\n\t\t\t// we don't care about actual value, only if it's more or less than a\r\n\t\t\t// threshold essentially we capture zero crossings for later analysis\r\n //\t\t\tif(dest[i] < 127) dest[i] = 0; else dest[i] = 1;\r\n\t\t\ti++;\r\n\t\t\tif (i >= m) break;\r\n\t\t}\r\n\t}\r\n \r\n FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off\r\n\tLED_D_OFF();\r\n\tDbpString(\"DONE!\");\r\n}\r\n\r\n// Read card traceability data (page 1)\r\nvoid T55xxReadTrace(void){\r\n\tuint8_t *dest = (uint8_t *)BigBuf;\r\n\tint m=0, i=0;\r\n \r\n\tm = sizeof(BigBuf);\r\n // Clear destination buffer before sending the command\r\n\tmemset(dest, 128, m);\r\n\t// Connect the A/D to the peak-detected low-frequency path.\r\n\tSetAdcMuxFor(GPIO_MUXSEL_LOPKD);\r\n\t// Now set up the SSC to get the ADC samples that are now streaming at us.\r\n\tFpgaSetupSsc();\r\n \r\n\tLED_D_ON();\r\n\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r\n\t//FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r\n \r\n\t// Give it a bit of time for the resonant antenna to settle.\r\n\t// And for the tag to fully power up\r\n\tSpinDelay(150);\r\n \r\n\t// Now start writting\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\tSpinDelayUs(START_GAP);\r\n \r\n\t// Opcode\r\n\tT55xxWriteBit(1);\r\n\tT55xxWriteBit(1); //Page 1\r\n \r\n // Turn field on to read the response\r\n\tFpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r\n\t//FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r\n \r\n\t// Now do the acquisition\r\n\ti = 0;\r\n\tfor(;;) {\r\n\t\tif (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {\r\n\t\t\tAT91C_BASE_SSC->SSC_THR = 0x43;\r\n\t\t}\r\n\t\tif (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {\r\n\t\t\tdest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;\r\n\t\t\ti++;\r\n\t\t\tif (i >= m) break;\r\n\t\t}\r\n\t}\r\n \r\n FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off\r\n\tLED_D_OFF();\r\n\tDbpString(\"DONE!\");\r\n}\r\n\r\n/*-------------- Cloning routines -----------*/\r\n// Copy HID id to card and setup block 0 config\r\nvoid CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)\r\n{\r\n\tint data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format\r\n\tint last_block = 0;\r\n \r\n if (longFMT){\r\n\t // Ensure no more than 84 bits supplied\r\n\t if (hi2>0xFFFFF) {\r\n\t\t DbpString(\"Tags can only have 84 bits.\");\r\n\t\t return;\r\n\t }\r\n // Build the 6 data blocks for supplied 84bit ID\r\n last_block = 6;\r\n data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)\r\n\t for (int i=0;i<4;i++) {\r\n\t\t if (hi2 & (1<<(19-i)))\r\n\t\t\t data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10\r\n\t\t else\r\n\t\t\t data1 |= (1<<((3-i)*2)); // 0 -> 01\r\n\t }\r\n \r\n \tdata2 = 0;\r\n \tfor (int i=0;i<16;i++) {\r\n \t\tif (hi2 & (1<<(15-i)))\r\n \t\t\tdata2 |= (1<<(((15-i)*2)+1)); // 1 -> 10\r\n \t\telse\r\n \t\t\tdata2 |= (1<<((15-i)*2)); // 0 -> 01\r\n }\r\n \r\n \tdata3 = 0;\r\n \tfor (int i=0;i<16;i++) {\r\n \t\tif (hi & (1<<(31-i)))\r\n \t\t\tdata3 |= (1<<(((15-i)*2)+1)); // 1 -> 10\r\n \t\telse\r\n \t\t\tdata3 |= (1<<((15-i)*2)); // 0 -> 01\r\n \t}\r\n \r\n \tdata4 = 0;\r\n \tfor (int i=0;i<16;i++) {\r\n \t\tif (hi & (1<<(15-i)))\r\n \t\t\tdata4 |= (1<<(((15-i)*2)+1)); // 1 -> 10\r\n \t\telse\r\n \t\t\tdata4 |= (1<<((15-i)*2)); // 0 -> 01\r\n }\r\n \r\n \tdata5 = 0;\r\n \tfor (int i=0;i<16;i++) {\r\n \t\tif (lo & (1<<(31-i)))\r\n \t\t\tdata5 |= (1<<(((15-i)*2)+1)); // 1 -> 10\r\n \t\telse\r\n \t\t\tdata5 |= (1<<((15-i)*2)); // 0 -> 01\r\n \t}\r\n \r\n \tdata6 = 0;\r\n \tfor (int i=0;i<16;i++) {\r\n \t\tif (lo & (1<<(15-i)))\r\n \t\t\tdata6 |= (1<<(((15-i)*2)+1)); // 1 -> 10\r\n \t\telse\r\n \t\t\tdata6 |= (1<<((15-i)*2)); // 0 -> 01\r\n }\r\n }\r\n else {\r\n\t // Ensure no more than 44 bits supplied\r\n\t if (hi>0xFFF) {\r\n\t\t DbpString(\"Tags can only have 44 bits.\");\r\n\t\t return;\r\n\t }\r\n \r\n \t// Build the 3 data blocks for supplied 44bit ID\r\n \tlast_block = 3;\r\n \t\r\n \tdata1 = 0x1D000000; // load preamble\r\n \r\n for (int i=0;i<12;i++) {\r\n if (hi & (1<<(11-i)))\r\n data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10\r\n else\r\n data1 |= (1<<((11-i)*2)); // 0 -> 01\r\n }\r\n \r\n \tdata2 = 0;\r\n \tfor (int i=0;i<16;i++) {\r\n \t\tif (lo & (1<<(31-i)))\r\n \t\t\tdata2 |= (1<<(((15-i)*2)+1)); // 1 -> 10\r\n \t\telse\r\n \t\t\tdata2 |= (1<<((15-i)*2)); // 0 -> 01\r\n \t}\r\n \r\n \tdata3 = 0;\r\n \tfor (int i=0;i<16;i++) {\r\n \t\tif (lo & (1<<(15-i)))\r\n \t\t\tdata3 |= (1<<(((15-i)*2)+1)); // 1 -> 10\r\n \t\telse\r\n \t\t\tdata3 |= (1<<((15-i)*2)); // 0 -> 01\r\n \t}\r\n }\r\n \r\n\tLED_D_ON();\r\n\t// Program the data blocks for supplied ID\r\n\t// and the block 0 for HID format\r\n\tT55xxWriteBlock(data1,1,0,0);\r\n\tT55xxWriteBlock(data2,2,0,0);\r\n\tT55xxWriteBlock(data3,3,0,0);\r\n\t\r\n\tif (longFMT) { // if long format there are 6 blocks\r\n\t T55xxWriteBlock(data4,4,0,0);\r\n\t T55xxWriteBlock(data5,5,0,0);\r\n\t T55xxWriteBlock(data6,6,0,0);\r\n }\r\n \r\n\t// Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)\r\n\tT55xxWriteBlock(T55x7_BITRATE_RF_50 |\r\n T55x7_MODULATION_FSK2a |\r\n last_block << T55x7_MAXBLOCK_SHIFT,\r\n 0,0,0);\r\n \r\n\tLED_D_OFF();\r\n\t\r\n\tDbpString(\"DONE!\");\r\n}\r\n\r\n// Define 9bit header for EM410x tags\r\n#define EM410X_HEADER\t\t0x1FF\r\n#define EM410X_ID_LENGTH\t40\r\n\r\nvoid WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)\r\n{\r\n\tint i, id_bit;\r\n\tuint64_t id = EM410X_HEADER;\r\n\tuint64_t rev_id = 0;\t// reversed ID\r\n\tint c_parity[4];\t// column parity\r\n\tint r_parity = 0;\t// row parity\r\n\tuint32_t clock = 0;\r\n\r\n\t// Reverse ID bits given as parameter (for simpler operations)\r\n\tfor (i = 0; i < EM410X_ID_LENGTH; ++i) {\r\n\t\tif (i < 32) {\r\n\t\t\trev_id = (rev_id << 1) | (id_lo & 1);\r\n\t\t\tid_lo >>= 1;\r\n\t\t} else {\r\n\t\t\trev_id = (rev_id << 1) | (id_hi & 1);\r\n\t\t\tid_hi >>= 1;\r\n\t\t}\r\n\t}\r\n\r\n\tfor (i = 0; i < EM410X_ID_LENGTH; ++i) {\r\n\t\tid_bit = rev_id & 1;\r\n\r\n\t\tif (i % 4 == 0) {\r\n\t\t\t// Don't write row parity bit at start of parsing\r\n\t\t\tif (i)\r\n\t\t\t\tid = (id << 1) | r_parity;\r\n\t\t\t// Start counting parity for new row\r\n\t\t\tr_parity = id_bit;\r\n\t\t} else {\r\n\t\t\t// Count row parity\r\n\t\t\tr_parity ^= id_bit;\r\n\t\t}\r\n\r\n\t\t// First elements in column?\r\n\t\tif (i < 4)\r\n\t\t\t// Fill out first elements\r\n\t\t\tc_parity[i] = id_bit;\r\n\t\telse\r\n\t\t\t// Count column parity\r\n\t\t\tc_parity[i % 4] ^= id_bit;\r\n\r\n\t\t// Insert ID bit\r\n\t\tid = (id << 1) | id_bit;\r\n\t\trev_id >>= 1;\r\n\t}\r\n\r\n\t// Insert parity bit of last row\r\n\tid = (id << 1) | r_parity;\r\n\r\n\t// Fill out column parity at the end of tag\r\n\tfor (i = 0; i < 4; ++i)\r\n\t\tid = (id << 1) | c_parity[i];\r\n\r\n\t// Add stop bit\r\n\tid <<= 1;\r\n\r\n\tDbprintf(\"Started writing %s tag ...\", card ? \"T55x7\":\"T5555\");\r\n\tLED_D_ON();\r\n\r\n\t// Write EM410x ID\r\n\tT55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);\r\n\tT55xxWriteBlock((uint32_t)id, 2, 0, 0);\r\n\r\n\t// Config for EM410x (RF/64, Manchester, Maxblock=2)\r\n\tif (card) {\r\n\t\t// Clock rate is stored in bits 8-15 of the card value\r\n\t\tclock = (card & 0xFF00) >> 8;\r\n\t\tDbprintf(\"Clock rate: %d\", clock);\r\n\t\tswitch (clock)\r\n\t\t{\r\n\t\t\tcase 32:\r\n\t\t\t\tclock = T55x7_BITRATE_RF_32;\r\n\t\t\t\tbreak;\r\n\t\t\tcase 16:\r\n\t\t\t\tclock = T55x7_BITRATE_RF_16;\r\n\t\t\t\tbreak;\r\n\t\t\tcase 0:\r\n\t\t\t\t// A value of 0 is assumed to be 64 for backwards-compatibility\r\n\t\t\t\t// Fall through...\r\n\t\t\tcase 64:\r\n\t\t\t\tclock = T55x7_BITRATE_RF_64;\r\n\t\t\t\tbreak; \r\n\t\t\tdefault:\r\n\t\t\t\tDbprintf(\"Invalid clock rate: %d\", clock);\r\n\t\t\t\treturn;\r\n\t\t}\r\n\r\n\t\t// Writing configuration for T55x7 tag\r\n\t\tT55xxWriteBlock(clock\t |\r\n\t\t\t\tT55x7_MODULATION_MANCHESTER |\r\n\t\t\t\t2 << T55x7_MAXBLOCK_SHIFT,\r\n\t\t\t\t0, 0, 0);\r\n }\r\n\telse\r\n\t\t// Writing configuration for T5555(Q5) tag\r\n\t\tT55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |\r\n\t\t\t\tT5555_MODULATION_MANCHESTER |\r\n\t\t\t\t2 << T5555_MAXBLOCK_SHIFT,\r\n\t\t\t\t0, 0, 0);\r\n\r\n\tLED_D_OFF();\r\n\tDbprintf(\"Tag %s written with 0x%08x%08x\\n\", card ? \"T55x7\":\"T5555\",\r\n\t\t\t\t\t(uint32_t)(id >> 32), (uint32_t)id);\r\n}\r\n\r\n// Clone Indala 64-bit tag by UID to T55x7\r\nvoid CopyIndala64toT55x7(int hi, int lo)\r\n{\r\n\r\n\t//Program the 2 data blocks for supplied 64bit UID\r\n\t// and the block 0 for Indala64 format\r\n\tT55xxWriteBlock(hi,1,0,0);\r\n\tT55xxWriteBlock(lo,2,0,0);\r\n\t//Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)\r\n\tT55xxWriteBlock(T55x7_BITRATE_RF_32 |\r\n\t\t\tT55x7_MODULATION_PSK1 |\r\n\t\t\t2 << T55x7_MAXBLOCK_SHIFT,\r\n\t\t\t0, 0, 0);\r\n\t//Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)\r\n//\tT5567WriteBlock(0x603E1042,0);\r\n\r\n\tDbpString(\"DONE!\");\r\n\r\n}\t\r\n\r\nvoid CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)\r\n{\r\n\r\n\t//Program the 7 data blocks for supplied 224bit UID\r\n\t// and the block 0 for Indala224 format\r\n\tT55xxWriteBlock(uid1,1,0,0);\r\n\tT55xxWriteBlock(uid2,2,0,0);\r\n\tT55xxWriteBlock(uid3,3,0,0);\r\n\tT55xxWriteBlock(uid4,4,0,0);\r\n\tT55xxWriteBlock(uid5,5,0,0);\r\n\tT55xxWriteBlock(uid6,6,0,0);\r\n\tT55xxWriteBlock(uid7,7,0,0);\r\n\t//Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)\r\n\tT55xxWriteBlock(T55x7_BITRATE_RF_32 |\r\n\t\t\tT55x7_MODULATION_PSK1 |\r\n\t\t\t7 << T55x7_MAXBLOCK_SHIFT,\r\n\t\t\t0,0,0);\r\n\t//Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)\r\n//\tT5567WriteBlock(0x603E10E2,0);\r\n\r\n\tDbpString(\"DONE!\");\r\n\r\n}\r\n\r\n\r\n#define abs(x) ( ((x)<0) ? -(x) : (x) )\r\n#define max(x,y) ( x GraphBuffer[0]) {\r\n while(i < GraphTraceLen) {\r\n if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)\r\n break;\r\n i++;\r\n }\r\n dir = 0;\r\n\t}\r\n\telse {\r\n while(i < GraphTraceLen) {\r\n if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)\r\n break;\r\n i++;\r\n }\r\n dir = 1;\r\n\t}\r\n\t\r\n\tlastval = i++;\r\n\thalf_switch = 0;\r\n\tpmc = 0;\r\n\tblock_done = 0;\r\n\t\r\n\tfor (bitidx = 0; i < GraphTraceLen; i++)\r\n\t{\r\n if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))\r\n {\r\n lc = i - lastval;\r\n lastval = i;\r\n \r\n // Switch depending on lc length:\r\n // Tolerance is 1/8 of clock rate (arbitrary)\r\n if (abs(lc-clock/4) < tolerance) {\r\n // 16T0\r\n if((i - pmc) == lc) { /* 16T0 was previous one */\r\n /* It's a PMC ! */\r\n i += (128+127+16+32+33+16)-1;\r\n lastval = i;\r\n pmc = 0;\r\n block_done = 1;\r\n }\r\n else {\r\n pmc = i;\r\n }\r\n } else if (abs(lc-clock/2) < tolerance) {\r\n // 32TO\r\n if((i - pmc) == lc) { /* 16T0 was previous one */\r\n /* It's a PMC ! */\r\n i += (128+127+16+32+33)-1;\r\n lastval = i;\r\n pmc = 0;\r\n block_done = 1;\r\n }\r\n else if(half_switch == 1) {\r\n BitStream[bitidx++] = 0;\r\n half_switch = 0;\r\n }\r\n else\r\n half_switch++;\r\n } else if (abs(lc-clock) < tolerance) {\r\n // 64TO\r\n BitStream[bitidx++] = 1;\r\n } else {\r\n // Error\r\n warnings++;\r\n if (warnings > 10)\r\n {\r\n Dbprintf(\"Error: too many detection errors, aborting.\");\r\n return 0;\r\n }\r\n }\r\n \r\n if(block_done == 1) {\r\n if(bitidx == 128) {\r\n for(j=0; j<16; j++) {\r\n Blocks[num_blocks][j] = 128*BitStream[j*8+7]+\r\n 64*BitStream[j*8+6]+\r\n 32*BitStream[j*8+5]+\r\n 16*BitStream[j*8+4]+\r\n 8*BitStream[j*8+3]+\r\n 4*BitStream[j*8+2]+\r\n 2*BitStream[j*8+1]+\r\n BitStream[j*8];\r\n }\r\n num_blocks++;\r\n }\r\n bitidx = 0;\r\n block_done = 0;\r\n half_switch = 0;\r\n }\r\n if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;\r\n else dir = 1;\r\n }\r\n if(bitidx==255)\r\n bitidx=0;\r\n warnings = 0;\r\n if(num_blocks == 4) break;\r\n\t}\r\n\tmemcpy(outBlocks, Blocks, 16*num_blocks);\r\n\treturn num_blocks;\r\n}\r\n\r\nint IsBlock0PCF7931(uint8_t *Block) {\r\n\t// Assume RFU means 0 :)\r\n\tif((memcmp(Block, \"\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x01\", 8) == 0) && memcmp(Block+9, \"\\x00\\x00\\x00\\x00\\x00\\x00\\x00\", 7) == 0) // PAC enabled\r\n return 1;\r\n\tif((memcmp(Block+9, \"\\x00\\x00\\x00\\x00\\x00\\x00\\x00\", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?\r\n return 1;\r\n\treturn 0;\r\n}\r\n\r\nint IsBlock1PCF7931(uint8_t *Block) {\r\n\t// Assume RFU means 0 :)\r\n\tif(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)\r\n if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)\r\n return 1;\r\n\t\r\n\treturn 0;\r\n}\r\n\r\n#define ALLOC 16\r\n\r\nvoid ReadPCF7931() {\r\n\tuint8_t Blocks[8][17];\r\n\tuint8_t tmpBlocks[4][16];\r\n\tint i, j, ind, ind2, n;\r\n\tint num_blocks = 0;\r\n\tint max_blocks = 8;\r\n\tint ident = 0;\r\n\tint error = 0;\r\n\tint tries = 0;\r\n\t\r\n\tmemset(Blocks, 0, 8*17*sizeof(uint8_t));\r\n\t\r\n\tdo {\r\n memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));\r\n n = DemodPCF7931((uint8_t**)tmpBlocks);\r\n if(!n)\r\n error++;\r\n if(error==10 && num_blocks == 0) {\r\n Dbprintf(\"Error, no tag or bad tag\");\r\n return;\r\n }\r\n else if (tries==20 || error==10) {\r\n Dbprintf(\"Error reading the tag\");\r\n Dbprintf(\"Here is the partial content\");\r\n goto end;\r\n }\r\n \r\n for(i=0; i= 0; ind--,ind2--) {\r\n if(ind2 < 0)\r\n ind2 = max_blocks;\r\n if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found\r\n // Dbprintf(\"Tmp %d -> Block %d\", ind, ind2);\r\n memcpy(Blocks[ind2], tmpBlocks[ind], 16);\r\n Blocks[ind2][ALLOC] = 1;\r\n num_blocks++;\r\n if(num_blocks == max_blocks) goto end;\r\n }\r\n }\r\n for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {\r\n if(ind2 > max_blocks)\r\n ind2 = 0;\r\n if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found\r\n // Dbprintf(\"Tmp %d -> Block %d\", ind, ind2);\r\n memcpy(Blocks[ind2], tmpBlocks[ind], 16);\r\n Blocks[ind2][ALLOC] = 1;\r\n num_blocks++;\r\n if(num_blocks == max_blocks) goto end;\r\n }\r\n }\r\n }\r\n }\r\n }\r\n }\r\n }\r\n tries++;\r\n if (BUTTON_PRESS()) return;\r\n\t} while (num_blocks != max_blocks);\r\nend:\r\n\tDbprintf(\"-----------------------------------------\");\r\n\tDbprintf(\"Memory content:\");\r\n\tDbprintf(\"-----------------------------------------\");\r\n\tfor(i=0; i\", i);\r\n\t}\r\n\tDbprintf(\"-----------------------------------------\");\r\n\t\r\n\treturn ;\r\n}\r\n\r\n\r\n//-----------------------------------\r\n// EM4469 / EM4305 routines\r\n//-----------------------------------\r\n#define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored\r\n#define FWD_CMD_WRITE 0xA\r\n#define FWD_CMD_READ 0x9\r\n#define FWD_CMD_DISABLE 0x5\r\n\r\n\r\nuint8_t forwardLink_data[64]; //array of forwarded bits\r\nuint8_t * forward_ptr; //ptr for forward message preparation\r\nuint8_t fwd_bit_sz; //forwardlink bit counter\r\nuint8_t * fwd_write_ptr; //forwardlink bit pointer\r\n\r\n//====================================================================\r\n// prepares command bits\r\n// see EM4469 spec\r\n//====================================================================\r\n//--------------------------------------------------------------------\r\nuint8_t Prepare_Cmd( uint8_t cmd ) {\r\n //--------------------------------------------------------------------\r\n \r\n *forward_ptr++ = 0; //start bit\r\n *forward_ptr++ = 0; //second pause for 4050 code\r\n \r\n *forward_ptr++ = cmd;\r\n cmd >>= 1;\r\n *forward_ptr++ = cmd;\r\n cmd >>= 1;\r\n *forward_ptr++ = cmd;\r\n cmd >>= 1;\r\n *forward_ptr++ = cmd;\r\n \r\n return 6; //return number of emited bits\r\n}\r\n\r\n//====================================================================\r\n// prepares address bits\r\n// see EM4469 spec\r\n//====================================================================\r\n\r\n//--------------------------------------------------------------------\r\nuint8_t Prepare_Addr( uint8_t addr ) {\r\n //--------------------------------------------------------------------\r\n \r\n register uint8_t line_parity;\r\n \r\n uint8_t i;\r\n line_parity = 0;\r\n for(i=0;i<6;i++) {\r\n *forward_ptr++ = addr;\r\n line_parity ^= addr;\r\n addr >>= 1;\r\n }\r\n \r\n *forward_ptr++ = (line_parity & 1);\r\n \r\n return 7; //return number of emited bits\r\n}\r\n\r\n//====================================================================\r\n// prepares data bits intreleaved with parity bits\r\n// see EM4469 spec\r\n//====================================================================\r\n\r\n//--------------------------------------------------------------------\r\nuint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {\r\n //--------------------------------------------------------------------\r\n \r\n register uint8_t line_parity;\r\n register uint8_t column_parity;\r\n register uint8_t i, j;\r\n register uint16_t data;\r\n \r\n data = data_low;\r\n column_parity = 0;\r\n \r\n for(i=0; i<4; i++) {\r\n line_parity = 0;\r\n for(j=0; j<8; j++) {\r\n line_parity ^= data;\r\n column_parity ^= (data & 1) << j;\r\n *forward_ptr++ = data;\r\n data >>= 1;\r\n }\r\n *forward_ptr++ = line_parity;\r\n if(i == 1)\r\n data = data_hi;\r\n }\r\n \r\n for(j=0; j<8; j++) {\r\n *forward_ptr++ = column_parity;\r\n column_parity >>= 1;\r\n }\r\n *forward_ptr = 0;\r\n \r\n return 45; //return number of emited bits\r\n}\r\n\r\n//====================================================================\r\n// Forward Link send function\r\n// Requires: forwarLink_data filled with valid bits (1 bit per byte)\r\n// fwd_bit_count set with number of bits to be sent\r\n//====================================================================\r\nvoid SendForward(uint8_t fwd_bit_count) {\r\n \r\n fwd_write_ptr = forwardLink_data;\r\n fwd_bit_sz = fwd_bit_count;\r\n \r\n LED_D_ON();\r\n \r\n //Field on\r\n FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r\n //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r\n \r\n // Give it a bit of time for the resonant antenna to settle.\r\n // And for the tag to fully power up\r\n SpinDelay(150);\r\n \r\n // force 1st mod pulse (start gap must be longer for 4305)\r\n fwd_bit_sz--; //prepare next bit modulation\r\n fwd_write_ptr++;\r\n FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off\r\n SpinDelayUs(55*8); //55 cycles off (8us each)for 4305\r\n FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r\n //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);//field on\r\n SpinDelayUs(16*8); //16 cycles on (8us each)\r\n \r\n // now start writting\r\n while(fwd_bit_sz-- > 0) { //prepare next bit modulation\r\n if(((*fwd_write_ptr++) & 1) == 1)\r\n SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)\r\n else {\r\n //These timings work for 4469/4269/4305 (with the 55*8 above)\r\n FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off\r\n SpinDelayUs(23*8); //16-4 cycles off (8us each)\r\n FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r\n //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);//field on\r\n SpinDelayUs(9*8); //16 cycles on (8us each)\r\n }\r\n }\r\n}\r\n\r\nvoid EM4xLogin(uint32_t Password) {\r\n \r\n uint8_t fwd_bit_count;\r\n \r\n forward_ptr = forwardLink_data;\r\n fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );\r\n fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );\r\n \r\n SendForward(fwd_bit_count);\r\n \r\n //Wait for command to complete\r\n SpinDelay(20);\r\n \r\n}\r\n\r\nvoid EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {\r\n \r\n uint8_t fwd_bit_count;\r\n uint8_t *dest = (uint8_t *)BigBuf;\r\n int m=0, i=0;\r\n \r\n //If password mode do login\r\n if (PwdMode == 1) EM4xLogin(Pwd);\r\n \r\n forward_ptr = forwardLink_data;\r\n fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );\r\n fwd_bit_count += Prepare_Addr( Address );\r\n \r\n m = sizeof(BigBuf);\r\n // Clear destination buffer before sending the command\r\n memset(dest, 128, m);\r\n // Connect the A/D to the peak-detected low-frequency path.\r\n SetAdcMuxFor(GPIO_MUXSEL_LOPKD);\r\n // Now set up the SSC to get the ADC samples that are now streaming at us.\r\n FpgaSetupSsc();\r\n \r\n SendForward(fwd_bit_count);\r\n \r\n // Now do the acquisition\r\n i = 0;\r\n for(;;) {\r\n if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {\r\n AT91C_BASE_SSC->SSC_THR = 0x43;\r\n }\r\n if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {\r\n dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;\r\n i++;\r\n if (i >= m) break;\r\n }\r\n }\r\n FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off\r\n LED_D_OFF();\r\n}\r\n\r\nvoid EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {\r\n \r\n uint8_t fwd_bit_count;\r\n \r\n //If password mode do login\r\n if (PwdMode == 1) EM4xLogin(Pwd);\r\n \r\n forward_ptr = forwardLink_data;\r\n fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );\r\n fwd_bit_count += Prepare_Addr( Address );\r\n fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );\r\n \r\n SendForward(fwd_bit_count);\r\n \r\n //Wait for write to complete\r\n SpinDelay(20);\r\n FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off\r\n LED_D_OFF();\r\n}\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/mifarecmd.c", "content": "//-----------------------------------------------------------------------------\r\n// Merlok - June 2011, 2012\r\n// Gerhard de Koning Gans - May 2008\r\n// Hagen Fritsch - June 2010\r\n//\r\n// This code is licensed to you under the terms of the GNU GPL, version 2 or,\r\n// at your option, any later version. See the LICENSE.txt file for the text of\r\n// the license.\r\n//-----------------------------------------------------------------------------\r\n// Routines to support ISO 14443 type A.\r\n//-----------------------------------------------------------------------------\r\n\r\n#include \"mifarecmd.h\"\r\n#include \"apps.h\"\r\n\r\n//-----------------------------------------------------------------------------\r\n// Select, Authenticaate, Read an MIFARE tag. \r\n// read block\r\n//-----------------------------------------------------------------------------\r\nvoid MifareReadBlock(uint8_t arg0, uint8_t arg1, uint8_t arg2, uint8_t *datain)\r\n{\r\n // params\r\n\tuint8_t blockNo = arg0;\r\n\tuint8_t keyType = arg1;\r\n\tuint64_t ui64Key = 0;\r\n\tui64Key = bytes_to_num(datain, 6);\r\n\t\r\n\t// variables\r\n\tbyte_t isOK = 0;\r\n\tbyte_t dataoutbuf[16];\r\n\tuint8_t uid[10];\r\n\tuint32_t cuid;\r\n\tstruct Crypto1State mpcs = {0, 0};\r\n\tstruct Crypto1State *pcs;\r\n\tpcs = &mpcs;\r\n\r\n\t// clear trace\r\n\tiso14a_clear_trace();\r\n//\tiso14a_set_tracing(false);\r\n\r\n\tiso14443a_setup();\r\n\r\n\tLED_A_ON();\r\n\tLED_B_OFF();\r\n\tLED_C_OFF();\r\n\r\n\twhile (true) {\r\n\t\tif(!iso14443a_select_card(uid, NULL, &cuid)) {\r\n\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Can't select card\");\r\n\t\t\tbreak;\r\n\t\t};\r\n\r\n\t\tif(mifare_classic_auth(pcs, cuid, blockNo, keyType, ui64Key, AUTH_FIRST)) {\r\n\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Auth error\");\r\n\t\t\tbreak;\r\n\t\t};\r\n\t\t\r\n\t\tif(mifare_classic_readblock(pcs, cuid, blockNo, dataoutbuf)) {\r\n\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Read block error\");\r\n\t\t\tbreak;\r\n\t\t};\r\n\r\n\t\tif(mifare_classic_halt(pcs, cuid)) {\r\n\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Halt error\");\r\n\t\t\tbreak;\r\n\t\t};\r\n\t\t\r\n\t\tisOK = 1;\r\n\t\tbreak;\r\n\t}\r\n\t\r\n\t// ----------------------------- crypto1 destroy\r\n\tcrypto1_destroy(pcs);\r\n\t\r\n\tif (MF_DBGLEVEL >= 2)\tDbpString(\"READ BLOCK FINISHED\");\r\n\r\n\t// add trace trailer\r\n\tmemset(uid, 0x44, 4);\r\n\tLogTrace(uid, 4, 0, 0, TRUE);\r\n\r\n//\tUsbCommand ack = {CMD_ACK, {isOK, 0, 0}};\r\n//\tmemcpy(ack.d.asBytes, dataoutbuf, 16);\r\n\t\r\n\tLED_B_ON();\r\n cmd_send(CMD_ACK,isOK,0,0,dataoutbuf,16);\r\n//\tUsbSendPacket((uint8_t *)&ack, sizeof(UsbCommand));\r\n\tLED_B_OFF();\r\n\r\n\r\n // Thats it...\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\tLEDsoff();\r\n// iso14a_set_tracing(TRUE);\r\n\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// Select, Authenticaate, Read an MIFARE tag. \r\n// read sector (data = 4 x 16 bytes = 64 bytes)\r\n//-----------------------------------------------------------------------------\r\nvoid MifareReadSector(uint8_t arg0, uint8_t arg1, uint8_t arg2, uint8_t *datain)\r\n{\r\n // params\r\n\tuint8_t sectorNo = arg0;\r\n\tuint8_t keyType = arg1;\r\n\tuint64_t ui64Key = 0;\r\n\tui64Key = bytes_to_num(datain, 6);\r\n\t\r\n\t// variables\r\n\tbyte_t isOK = 0;\r\n\tbyte_t dataoutbuf[16 * 4];\r\n\tuint8_t uid[10];\r\n\tuint32_t cuid;\r\n\tstruct Crypto1State mpcs = {0, 0};\r\n\tstruct Crypto1State *pcs;\r\n\tpcs = &mpcs;\r\n\r\n\t// clear trace\r\n\tiso14a_clear_trace();\r\n//\tiso14a_set_tracing(false);\r\n\r\n\tiso14443a_setup();\r\n\r\n\tLED_A_ON();\r\n\tLED_B_OFF();\r\n\tLED_C_OFF();\r\n\r\n\twhile (true) {\r\n\t\tif(!iso14443a_select_card(uid, NULL, &cuid)) {\r\n\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Can't select card\");\r\n\t\t\tbreak;\r\n\t\t};\r\n\r\n\t\tif(mifare_classic_auth(pcs, cuid, sectorNo * 4, keyType, ui64Key, AUTH_FIRST)) {\r\n\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Auth error\");\r\n\t\t\tbreak;\r\n\t\t};\r\n\t\t\r\n\t\tif(mifare_classic_readblock(pcs, cuid, sectorNo * 4 + 0, dataoutbuf + 16 * 0)) {\r\n\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Read block 0 error\");\r\n\t\t\tbreak;\r\n\t\t};\r\n\t\tif(mifare_classic_readblock(pcs, cuid, sectorNo * 4 + 1, dataoutbuf + 16 * 1)) {\r\n\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Read block 1 error\");\r\n\t\t\tbreak;\r\n\t\t};\r\n\t\tif(mifare_classic_readblock(pcs, cuid, sectorNo * 4 + 2, dataoutbuf + 16 * 2)) {\r\n\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Read block 2 error\");\r\n\t\t\tbreak;\r\n\t\t};\r\n\t\tif(mifare_classic_readblock(pcs, cuid, sectorNo * 4 + 3, dataoutbuf + 16 * 3)) {\r\n\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Read block 3 error\");\r\n\t\t\tbreak;\r\n\t\t};\r\n\t\t\r\n\t\tif(mifare_classic_halt(pcs, cuid)) {\r\n\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Halt error\");\r\n\t\t\tbreak;\r\n\t\t};\r\n\r\n\t\tisOK = 1;\r\n\t\tbreak;\r\n\t}\r\n\t\r\n\t// ----------------------------- crypto1 destroy\r\n\tcrypto1_destroy(pcs);\r\n\t\r\n\tif (MF_DBGLEVEL >= 2) DbpString(\"READ SECTOR FINISHED\");\r\n\r\n\t// add trace trailer\r\n\tmemset(uid, 0x44, 4);\r\n\tLogTrace(uid, 4, 0, 0, TRUE);\r\n\r\n//\tUsbCommand ack = {CMD_ACK, {isOK, 0, 0}};\r\n//\tmemcpy(ack.d.asBytes, dataoutbuf, 16 * 2);\r\n\t\r\n\tLED_B_ON();\r\n cmd_send(CMD_ACK,isOK,0,0,dataoutbuf,32);\r\n//\tUsbSendPacket((uint8_t *)&ack, sizeof(UsbCommand));\r\n//\tSpinDelay(100);\r\n\t\r\n//\tmemcpy(ack.d.asBytes, dataoutbuf + 16 * 2, 16 * 2);\r\n//\tUsbSendPacket((uint8_t *)&ack, sizeof(UsbCommand));\r\n cmd_send(CMD_ACK,isOK,0,0,dataoutbuf+32, 32);\r\n\tLED_B_OFF();\r\n\r\n\t// Thats it...\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\tLEDsoff();\r\n// iso14a_set_tracing(TRUE);\r\n\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// Select, Authenticaate, Read an MIFARE tag. \r\n// read block\r\n//-----------------------------------------------------------------------------\r\nvoid MifareWriteBlock(uint8_t arg0, uint8_t arg1, uint8_t arg2, uint8_t *datain)\r\n{\r\n\t// params\r\n\tuint8_t blockNo = arg0;\r\n\tuint8_t keyType = arg1;\r\n\tuint64_t ui64Key = 0;\r\n\tbyte_t blockdata[16];\r\n\r\n\tui64Key = bytes_to_num(datain, 6);\r\n\tmemcpy(blockdata, datain + 10, 16);\r\n\t\r\n\t// variables\r\n\tbyte_t isOK = 0;\r\n\tuint8_t uid[10];\r\n\tuint32_t cuid;\r\n\tstruct Crypto1State mpcs = {0, 0};\r\n\tstruct Crypto1State *pcs;\r\n\tpcs = &mpcs;\r\n\r\n\t// clear trace\r\n\tiso14a_clear_trace();\r\n// iso14a_set_tracing(false);\r\n\r\n\tiso14443a_setup();\r\n\r\n\tLED_A_ON();\r\n\tLED_B_OFF();\r\n\tLED_C_OFF();\r\n\r\n\twhile (true) {\r\n\t\t\tif(!iso14443a_select_card(uid, NULL, &cuid)) {\r\n\t\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Can't select card\");\r\n\t\t\tbreak;\r\n\t\t};\r\n\r\n\t\tif(mifare_classic_auth(pcs, cuid, blockNo, keyType, ui64Key, AUTH_FIRST)) {\r\n\t\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Auth error\");\r\n\t\t\tbreak;\r\n\t\t};\r\n\t\t\r\n\t\tif(mifare_classic_writeblock(pcs, cuid, blockNo, blockdata)) {\r\n\t\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Write block error\");\r\n\t\t\tbreak;\r\n\t\t};\r\n\r\n\t\tif(mifare_classic_halt(pcs, cuid)) {\r\n\t\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Halt error\");\r\n\t\t\tbreak;\r\n\t\t};\r\n\t\t\r\n\t\tisOK = 1;\r\n\t\tbreak;\r\n\t}\r\n\t\r\n\t// ----------------------------- crypto1 destroy\r\n\tcrypto1_destroy(pcs);\r\n\t\r\n\tif (MF_DBGLEVEL >= 2)\tDbpString(\"WRITE BLOCK FINISHED\");\r\n\r\n\t// add trace trailer\r\n\tmemset(uid, 0x44, 4);\r\n\tLogTrace(uid, 4, 0, 0, TRUE);\r\n\r\n//\tUsbCommand ack = {CMD_ACK, {isOK, 0, 0}};\r\n\t\r\n\tLED_B_ON();\r\n cmd_send(CMD_ACK,isOK,0,0,0,0);\r\n//\tUsbSendPacket((uint8_t *)&ack, sizeof(UsbCommand));\r\n\tLED_B_OFF();\r\n\r\n\r\n\t// Thats it...\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\tLEDsoff();\r\n// iso14a_set_tracing(TRUE);\r\n\r\n}\r\n\r\n// Return 1 if the nonce is invalid else return 0\r\nint valid_nonce(uint32_t Nt, uint32_t NtEnc, uint32_t Ks1, byte_t * parity) {\r\n\treturn ((oddparity((Nt >> 24) & 0xFF) == ((parity[0]) ^ oddparity((NtEnc >> 24) & 0xFF) ^ BIT(Ks1,16))) & \\\r\n\t(oddparity((Nt >> 16) & 0xFF) == ((parity[1]) ^ oddparity((NtEnc >> 16) & 0xFF) ^ BIT(Ks1,8))) & \\\r\n\t(oddparity((Nt >> 8) & 0xFF) == ((parity[2]) ^ oddparity((NtEnc >> 8) & 0xFF) ^ BIT(Ks1,0)))) ? 1 : 0;\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// MIFARE nested authentication. \r\n// \r\n//-----------------------------------------------------------------------------\r\nvoid MifareNested(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain)\r\n{\r\n\t// params\r\n\tuint8_t blockNo = arg0;\r\n\tuint8_t keyType = arg1;\r\n\tuint8_t targetBlockNo = arg2 & 0xff;\r\n\tuint8_t targetKeyType = (arg2 >> 8) & 0xff;\r\n\tuint64_t ui64Key = 0;\r\n\r\n\tui64Key = bytes_to_num(datain, 6);\r\n\t\r\n\t// variables\r\n\tint rtr, i, j, m, len;\r\n\tint davg, dmin, dmax;\r\n\tuint8_t uid[10];\r\n\tuint32_t cuid, nt1, nt2, nttmp, nttest, par, ks1;\r\n\tuint8_t par_array[4];\r\n\tnestedVector nvector[NES_MAX_INFO + 1][11];\r\n\tint nvectorcount[NES_MAX_INFO + 1];\r\n\tint ncount = 0;\r\n\tstruct Crypto1State mpcs = {0, 0};\r\n\tstruct Crypto1State *pcs;\r\n\tpcs = &mpcs;\r\n\tuint8_t* receivedAnswer = mifare_get_bigbufptr();\r\n\r\n\t//init\r\n\tfor (i = 0; i < NES_MAX_INFO + 1; i++) nvectorcount[i] = 11; // 11 - empty block;\r\n\t\r\n\t// clear trace\r\n\tiso14a_clear_trace();\r\n iso14a_set_tracing(false);\r\n\t\r\n\tiso14443a_setup();\r\n\r\n\tLED_A_ON();\r\n\tLED_B_ON();\r\n\tLED_C_OFF();\r\n\r\n FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n SpinDelay(200);\r\n\t\r\n\tdavg = dmax = 0;\r\n\tdmin = 2000;\r\n\r\n\t// test nonce distance\r\n\tfor (rtr = 0; rtr < 10; rtr++) {\r\n FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n SpinDelay(100);\r\n FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);\r\n\r\n // Test if the action was cancelled\r\n if(BUTTON_PRESS()) {\r\n break;\r\n }\r\n\r\n\t\tif(!iso14443a_select_card(uid, NULL, &cuid)) {\r\n\t\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Can't select card\");\r\n\t\t\tbreak;\r\n\t\t};\r\n\t\t\r\n\t\tif(mifare_classic_authex(pcs, cuid, blockNo, keyType, ui64Key, AUTH_FIRST, &nt1)) {\r\n\t\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Auth1 error\");\r\n\t\t\tbreak;\r\n\t\t};\r\n\r\n\t\tif(mifare_classic_authex(pcs, cuid, blockNo, keyType, ui64Key, AUTH_NESTED, &nt2)) {\r\n\t\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Auth2 error\");\r\n\t\t\tbreak;\r\n\t\t};\r\n\t\t\r\n\t\tnttmp = prng_successor(nt1, 500);\r\n\t\tfor (i = 501; i < 2000; i++) {\r\n\t\t\tnttmp = prng_successor(nttmp, 1);\r\n\t\t\tif (nttmp == nt2) break;\r\n\t\t}\r\n\t\t\r\n\t\tif (i != 2000) {\r\n\t\t\tdavg += i;\r\n\t\t\tif (dmin > i) dmin = i;\r\n\t\t\tif (dmax < i) dmax = i;\r\n\t\t\tif (MF_DBGLEVEL >= 4)\tDbprintf(\"r=%d nt1=%08x nt2=%08x distance=%d\", rtr, nt1, nt2, i);\r\n\t\t}\r\n\t}\r\n\t\r\n\tif (rtr == 0)\treturn;\r\n\r\n\tdavg = davg / rtr;\r\n\tif (MF_DBGLEVEL >= 3)\tDbprintf(\"distance: min=%d max=%d avg=%d\", dmin, dmax, davg);\r\n\r\n\tLED_B_OFF();\r\n\r\n// -------------------------------------------------------------------------------------------------\t\r\n\t\r\n\tLED_C_ON();\r\n\r\n\t// get crypted nonces for target sector\r\n\tfor (rtr = 0; rtr < NS_RETRIES_GETNONCE; rtr++) {\r\n\tif (MF_DBGLEVEL >= 4)\t\t\tDbprintf(\"------------------------------\");\r\n\r\n\t\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n SpinDelay(100);\r\n FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);\r\n\r\n // Test if the action was cancelled\r\n if(BUTTON_PRESS()) {\r\n break;\r\n }\r\n\r\n\t\tif(!iso14443a_select_card(uid, NULL, &cuid)) {\r\n\t\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Can't select card\");\r\n\t\t\tbreak;\r\n\t\t};\r\n\t\t\r\n\t\tif(mifare_classic_authex(pcs, cuid, blockNo, keyType, ui64Key, AUTH_FIRST, &nt1)) {\r\n\t\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Auth1 error\");\r\n\t\t\tbreak;\r\n\t\t};\r\n\r\n\t\t// nested authentication\r\n\t\tlen = mifare_sendcmd_shortex(pcs, AUTH_NESTED, 0x60 + (targetKeyType & 0x01), targetBlockNo, receivedAnswer, &par);\r\n\t\tif (len != 4) {\r\n\t\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Auth2 error len=%d\", len);\r\n\t\t\tbreak;\r\n\t\t};\r\n\t\r\n\t\tnt2 = bytes_to_num(receivedAnswer, 4);\t\t\r\n\t\tif (MF_DBGLEVEL >= 4)\tDbprintf(\"r=%d nt1=%08x nt2enc=%08x nt2par=%08x\", rtr, nt1, nt2, par);\r\n\t\t\r\n\t\t// Parity validity check\r\n\t\tfor (i = 0; i < 4; i++) {\r\n\t\t\tpar_array[i] = (oddparity(receivedAnswer[i]) != ((par & 0x08) >> 3));\r\n\t\t\tpar = par << 1;\r\n\t\t}\r\n\t\t\r\n\t\tncount = 0;\r\n\t\tnttest = prng_successor(nt1, dmin - NS_TOLERANCE);\r\n\t\tfor (m = dmin - NS_TOLERANCE + 1; m < dmax + NS_TOLERANCE; m++) {\r\n\t\t\tnttest = prng_successor(nttest, 1);\r\n\t\t\tks1 = nt2 ^ nttest;\r\n\r\n\t\t\tif (valid_nonce(nttest, nt2, ks1, par_array) && (ncount < 11)){\r\n\t\t\t\t\r\n\t\t\t\tnvector[NES_MAX_INFO][ncount].nt = nttest;\r\n\t\t\t\tnvector[NES_MAX_INFO][ncount].ks1 = ks1;\r\n\t\t\t\tncount++;\r\n\t\t\t\tnvectorcount[NES_MAX_INFO] = ncount;\r\n\t\t\t\tif (MF_DBGLEVEL >= 4)\tDbprintf(\"valid m=%d ks1=%08x nttest=%08x\", m, ks1, nttest);\r\n\t\t\t}\r\n\r\n\t\t}\r\n\t\t\r\n\t\t// select vector with length less than got\r\n\t\tif (nvectorcount[NES_MAX_INFO] != 0) {\r\n\t\t\tm = NES_MAX_INFO;\r\n\t\t\t\r\n\t\t\tfor (i = 0; i < NES_MAX_INFO; i++)\r\n\t\t\t\tif (nvectorcount[i] > 10) {\r\n\t\t\t\t\tm = i;\r\n\t\t\t\t\tbreak;\r\n\t\t\t\t}\r\n\t\t\t\t\r\n\t\t\tif (m == NES_MAX_INFO)\r\n\t\t\t\tfor (i = 0; i < NES_MAX_INFO; i++)\r\n\t\t\t\t\tif (nvectorcount[NES_MAX_INFO] < nvectorcount[i]) {\r\n\t\t\t\t\t\tm = i;\r\n\t\t\t\t\t\tbreak;\r\n\t\t\t\t\t}\r\n\t\t\t\t\t\r\n\t\t\tif (m != NES_MAX_INFO) {\r\n\t\t\t\tfor (i = 0; i < nvectorcount[m]; i++) {\r\n\t\t\t\t\tnvector[m][i] = nvector[NES_MAX_INFO][i];\r\n\t\t\t\t}\r\n\t\t\t\tnvectorcount[m] = nvectorcount[NES_MAX_INFO];\r\n\t\t\t}\r\n\t\t}\r\n\t}\r\n\r\n\tLED_C_OFF();\r\n\t\r\n\t// ----------------------------- crypto1 destroy\r\n\tcrypto1_destroy(pcs);\r\n\t\r\n\t// add trace trailer\r\n\tmemset(uid, 0x44, 4);\r\n\tLogTrace(uid, 4, 0, 0, TRUE);\r\n\r\n// UsbCommand ack = {CMD_ACK, {0, 0, 0}};\r\n\r\n\tfor (i = 0; i < NES_MAX_INFO; i++) {\r\n\t\tif (nvectorcount[i] > 10) continue;\r\n\t\t\r\n\t\tfor (j = 0; j < nvectorcount[i]; j += 5) {\r\n\t\t\tncount = nvectorcount[i] - j;\r\n\t\t\tif (ncount > 5) ncount = 5; \r\n\r\n//\t\t\tack.arg[0] = 0; // isEOF = 0\r\n//\t\t\tack.arg[1] = ncount;\r\n//\t\t\tack.arg[2] = targetBlockNo + (targetKeyType * 0x100);\r\n//\t\t\tmemset(ack.d.asBytes, 0x00, sizeof(ack.d.asBytes));\r\n\t\t\t\r\n byte_t buf[48];\r\n memset(buf, 0x00, sizeof(buf));\r\n\t\t\tmemcpy(buf, &cuid, 4);\r\n\t\t\tfor (m = 0; m < ncount; m++) {\r\n\t\t\t\tmemcpy(buf + 8 + m * 8 + 0, &nvector[i][m + j].nt, 4);\r\n\t\t\t\tmemcpy(buf + 8 + m * 8 + 4, &nvector[i][m + j].ks1, 4);\r\n\t\t\t}\r\n\t\r\n\t\t\tLED_B_ON();\r\n cmd_send(CMD_ACK,0,ncount,targetBlockNo + (targetKeyType * 0x100),buf,48);\r\n//\t\t\tUsbSendPacket((uint8_t *)&ack, sizeof(UsbCommand));\r\n\t\t\tLED_B_OFF();\r\n\t\t}\r\n\t}\r\n\r\n\t// finalize list\r\n//\tack.arg[0] = 1; // isEOF = 1\r\n//\tack.arg[1] = 0;\r\n//\tack.arg[2] = 0;\r\n//\tmemset(ack.d.asBytes, 0x00, sizeof(ack.d.asBytes));\r\n\t\r\n\tLED_B_ON();\r\n//\tUsbSendPacket((uint8_t *)&ack, sizeof(UsbCommand));\r\n cmd_send(CMD_ACK,1,0,0,0,0);\r\n\tLED_B_OFF();\r\n\r\n\tif (MF_DBGLEVEL >= 4)\tDbpString(\"NESTED FINISHED\");\r\n\r\n\t// Thats it...\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\tLEDsoff();\r\n\t\r\n iso14a_set_tracing(TRUE);\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// MIFARE check keys. key count up to 8. \r\n// \r\n//-----------------------------------------------------------------------------\r\nvoid MifareChkKeys(uint8_t arg0, uint8_t arg1, uint8_t arg2, uint8_t *datain)\r\n{\r\n // params\r\n\tuint8_t blockNo = arg0;\r\n\tuint8_t keyType = arg1;\r\n\tuint8_t keyCount = arg2;\r\n\tuint64_t ui64Key = 0;\r\n\t\r\n\t// variables\r\n\tint i;\r\n\tbyte_t isOK = 0;\r\n\tuint8_t uid[10];\r\n\tuint32_t cuid;\r\n\tstruct Crypto1State mpcs = {0, 0};\r\n\tstruct Crypto1State *pcs;\r\n\tpcs = &mpcs;\r\n\t\r\n\t// clear debug level\r\n\tint OLD_MF_DBGLEVEL = MF_DBGLEVEL;\t\r\n\tMF_DBGLEVEL = MF_DBG_NONE;\r\n\t\r\n\t// clear trace\r\n\tiso14a_clear_trace();\r\n iso14a_set_tracing(TRUE);\r\n\r\n\tiso14443a_setup();\r\n\r\n\tLED_A_ON();\r\n\tLED_B_OFF();\r\n\tLED_C_OFF();\r\n\r\n\tSpinDelay(300);\r\n\tfor (i = 0; i < keyCount; i++) {\r\n\t\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n SpinDelay(100);\r\n FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);\r\n\r\n\t\tif(!iso14443a_select_card(uid, NULL, &cuid)) {\r\n\t\t\tif (OLD_MF_DBGLEVEL >= 1)\tDbprintf(\"Can't select card\");\r\n\t\t\tbreak;\r\n\t\t};\r\n\r\n\t\tui64Key = bytes_to_num(datain + i * 6, 6);\r\n\t\tif(mifare_classic_auth(pcs, cuid, blockNo, keyType, ui64Key, AUTH_FIRST)) {\r\n\t\t\tcontinue;\r\n\t\t};\r\n\t\t\r\n\t\tisOK = 1;\r\n\t\tbreak;\r\n\t}\r\n\t\r\n\t// ----------------------------- crypto1 destroy\r\n\tcrypto1_destroy(pcs);\r\n\t\r\n\t// add trace trailer\r\n\tmemset(uid, 0x44, 4);\r\n\tLogTrace(uid, 4, 0, 0, TRUE);\r\n\r\n//\tUsbCommand ack = {CMD_ACK, {isOK, 0, 0}};\r\n//\tif (isOK) memcpy(ack.d.asBytes, datain + i * 6, 6);\r\n\t\r\n\tLED_B_ON();\r\n cmd_send(CMD_ACK,isOK,0,0,datain + i * 6,6);\r\n//\tUsbSendPacket((uint8_t *)&ack, sizeof(UsbCommand));\r\n\tLED_B_OFF();\r\n\r\n // Thats it...\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\tLEDsoff();\r\n\r\n\t// restore debug level\r\n\tMF_DBGLEVEL = OLD_MF_DBGLEVEL;\t\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// MIFARE commands set debug level\r\n// \r\n//-----------------------------------------------------------------------------\r\nvoid MifareSetDbgLvl(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain){\r\n\tMF_DBGLEVEL = arg0;\r\n\tDbprintf(\"Debug level: %d\", MF_DBGLEVEL);\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// Work with emulator memory\r\n// \r\n//-----------------------------------------------------------------------------\r\nvoid MifareEMemClr(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain){\r\n\temlClearMem();\r\n}\r\n\r\nvoid MifareEMemSet(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain){\r\n\temlSetMem(datain, arg0, arg1); // data, block num, blocks count\r\n}\r\n\r\nvoid MifareEMemGet(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain){\r\n//\tUsbCommand ack = {CMD_ACK, {arg0, arg1, 0}};\r\n\r\n byte_t buf[48];\r\n\temlGetMem(buf, arg0, arg1); // data, block num, blocks count\r\n\r\n\tLED_B_ON();\r\n cmd_send(CMD_ACK,arg0,arg1,0,buf,48);\r\n//\tUsbSendPacket((uint8_t *)&ack, sizeof(UsbCommand));\r\n\tLED_B_OFF();\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// Load a card into the emulator memory\r\n// \r\n//-----------------------------------------------------------------------------\r\nvoid MifareECardLoad(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain){\r\n\tint i;\r\n\tuint8_t sectorNo = 0;\r\n\tuint8_t keyType = arg1;\r\n\tuint64_t ui64Key = 0;\r\n\tuint32_t cuid;\r\n\tstruct Crypto1State mpcs = {0, 0};\r\n\tstruct Crypto1State *pcs;\r\n\tpcs = &mpcs;\r\n\r\n\t// variables\r\n\tbyte_t dataoutbuf[16];\r\n\tbyte_t dataoutbuf2[16];\r\n\tuint8_t uid[10];\r\n\r\n\t// clear trace\r\n\tiso14a_clear_trace();\r\n\tiso14a_set_tracing(false);\r\n\t\r\n\tiso14443a_setup();\r\n\r\n\tLED_A_ON();\r\n\tLED_B_OFF();\r\n\tLED_C_OFF();\r\n\t\r\n\twhile (true) {\r\n\t\tif(!iso14443a_select_card(uid, NULL, &cuid)) {\r\n\t\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Can't select card\");\r\n\t\t\tbreak;\r\n\t\t};\r\n\t\t\r\n\t\tfor (i = 0; i < 16; i++) {\r\n\t\t\tsectorNo = i;\r\n\t\t\tui64Key = emlGetKey(sectorNo, keyType);\r\n\t\r\n\t\t\tif (!i){\r\n\t\t\t\tif(mifare_classic_auth(pcs, cuid, sectorNo * 4, keyType, ui64Key, AUTH_FIRST)) {\r\n\t\t\t\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Sector[%d]. Auth error\", i);\r\n\t\t\t\t\tbreak;\r\n\t\t\t\t}\r\n\t\t\t} else {\r\n\t\t\t\tif(mifare_classic_auth(pcs, cuid, sectorNo * 4, keyType, ui64Key, AUTH_NESTED)) {\r\n\t\t\t\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Sector[%d]. Auth nested error\", i);\r\n\t\t\t\t\tbreak;\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\r\n\t\t\tif(mifare_classic_readblock(pcs, cuid, sectorNo * 4 + 0, dataoutbuf)) {\r\n\t\t\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Read block 0 error\");\r\n\t\t\t\tbreak;\r\n\t\t\t};\r\n\t\t\temlSetMem(dataoutbuf, sectorNo * 4 + 0, 1);\r\n\t\t\t\r\n\t\t\tif(mifare_classic_readblock(pcs, cuid, sectorNo * 4 + 1, dataoutbuf)) {\r\n\t\t\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Read block 1 error\");\r\n\t\t\t\tbreak;\r\n\t\t\t};\r\n\t\t\temlSetMem(dataoutbuf, sectorNo * 4 + 1, 1);\r\n\r\n\t\t\tif(mifare_classic_readblock(pcs, cuid, sectorNo * 4 + 2, dataoutbuf)) {\r\n\t\t\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Read block 2 error\");\r\n\t\t\t\tbreak;\r\n\t\t\t};\r\n\t\t\temlSetMem(dataoutbuf, sectorNo * 4 + 2, 1);\r\n\r\n\t\t\t// get block 3 bytes 6-9\r\n\t\t\tif(mifare_classic_readblock(pcs, cuid, sectorNo * 4 + 3, dataoutbuf)) {\r\n\t\t\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Read block 3 error\");\r\n\t\t\t\tbreak;\r\n\t\t\t};\r\n\t\t\temlGetMem(dataoutbuf2, sectorNo * 4 + 3, 1);\r\n\t\t\tmemcpy(&dataoutbuf2[6], &dataoutbuf[6], 4);\r\n\t\t\temlSetMem(dataoutbuf2, sectorNo * 4 + 3, 1);\r\n\t\t}\r\n\r\n\t\tif(mifare_classic_halt(pcs, cuid)) {\r\n\t\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Halt error\");\r\n\t\t\tbreak;\r\n\t\t};\r\n\t\t\r\n\t\tbreak;\r\n\t}\t\r\n\r\n\t// ----------------------------- crypto1 destroy\r\n\tcrypto1_destroy(pcs);\r\n\r\n\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\tLEDsoff();\r\n\t\r\n\tif (MF_DBGLEVEL >= 2) DbpString(\"EMUL FILL SECTORS FINISHED\");\r\n\r\n\t// add trace trailer\r\n\tmemset(uid, 0x44, 4);\r\n\tLogTrace(uid, 4, 0, 0, TRUE);\r\n}\r\n\r\n//-----------------------------------------------------------------------------\r\n// MIFARE 1k emulator\r\n// \r\n//-----------------------------------------------------------------------------\r\n\r\n\r\n//-----------------------------------------------------------------------------\r\n// Work with \"magic Chinese\" card (email him: ouyangweidaxian@live.cn)\r\n// \r\n//-----------------------------------------------------------------------------\r\nvoid MifareCSetBlock(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain){\r\n \r\n // params\r\n\tuint8_t needWipe = arg0;\r\n\t// bit 0 - need get UID\r\n\t// bit 1 - need wupC\r\n\t// bit 2 - need HALT after sequence\r\n\t// bit 3 - need init FPGA and field before sequence\r\n\t// bit 4 - need reset FPGA and LED\r\n\tuint8_t workFlags = arg1;\r\n\tuint8_t blockNo = arg2;\r\n\t\r\n\t// card commands\r\n\tuint8_t wupC1[] = { 0x40 }; \r\n\tuint8_t wupC2[] = { 0x43 }; \r\n\tuint8_t wipeC[] = { 0x41 }; \r\n\t\r\n\t// variables\r\n\tbyte_t isOK = 0;\r\n\tuint8_t uid[10];\r\n\tuint8_t d_block[18];\r\n\tuint32_t cuid;\r\n\t\r\n\tmemset(uid, 0x00, 10);\r\n\tuint8_t* receivedAnswer = mifare_get_bigbufptr();\r\n\t\r\n\tif (workFlags & 0x08) {\r\n\t\t// clear trace\r\n\t\tiso14a_clear_trace();\r\n\t\tiso14a_set_tracing(TRUE);\r\n\r\n\t\tiso14443a_setup();\r\n\r\n\t\tLED_A_ON();\r\n\t\tLED_B_OFF();\r\n\t\tLED_C_OFF();\r\n\t\r\n\t\tSpinDelay(300);\r\n\t\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\t\tSpinDelay(100);\r\n\t\tFpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);\r\n\t}\r\n\r\n\twhile (true) {\r\n\t\t// get UID from chip\r\n\t\tif (workFlags & 0x01) {\r\n\t\t\tif(!iso14443a_select_card(uid, NULL, &cuid)) {\r\n\t\t\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Can't select card\");\r\n\t\t\t\tbreak;\r\n\t\t\t};\r\n\r\n\t\t\tif(mifare_classic_halt(NULL, cuid)) {\r\n\t\t\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Halt error\");\r\n\t\t\t\tbreak;\r\n\t\t\t};\r\n\t\t};\r\n\t\r\n\t\t// reset chip\r\n\t\tif (needWipe){\r\n ReaderTransmitBitsPar(wupC1,7,0);\r\n\t\t\tif(!ReaderReceive(receivedAnswer) || (receivedAnswer[0] != 0x0a)) {\r\n\t\t\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"wupC1 error\");\r\n\t\t\t\tbreak;\r\n\t\t\t};\r\n\r\n\t\t\tReaderTransmit(wipeC, sizeof(wipeC));\r\n\t\t\tif(!ReaderReceive(receivedAnswer) || (receivedAnswer[0] != 0x0a)) {\r\n\t\t\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"wipeC error\");\r\n\t\t\t\tbreak;\r\n\t\t\t};\r\n\r\n\t\t\tif(mifare_classic_halt(NULL, cuid)) {\r\n\t\t\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Halt error\");\r\n\t\t\t\tbreak;\r\n\t\t\t};\r\n\t\t};\t\r\n\r\n\t\t// write block\r\n\t\tif (workFlags & 0x02) {\r\n ReaderTransmitBitsPar(wupC1,7,0);\r\n\t\t\tif(!ReaderReceive(receivedAnswer) || (receivedAnswer[0] != 0x0a)) {\r\n\t\t\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"wupC1 error\");\r\n\t\t\t\tbreak;\r\n\t\t\t};\r\n\r\n\t\t\tReaderTransmit(wupC2, sizeof(wupC2));\r\n\t\t\tif(!ReaderReceive(receivedAnswer) || (receivedAnswer[0] != 0x0a)) {\r\n\t\t\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"wupC2 error\");\r\n\t\t\t\tbreak;\r\n\t\t\t};\r\n\t\t}\r\n\r\n\t\tif ((mifare_sendcmd_short(NULL, 0, 0xA0, blockNo, receivedAnswer) != 1) || (receivedAnswer[0] != 0x0a)) {\r\n\t\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"write block send command error\");\r\n\t\t\tbreak;\r\n\t\t};\r\n\t\r\n\t\tmemcpy(d_block, datain, 16);\r\n\t\tAppendCrc14443a(d_block, 16);\r\n\t\r\n\t\tReaderTransmit(d_block, sizeof(d_block));\r\n\t\tif ((ReaderReceive(receivedAnswer) != 1) || (receivedAnswer[0] != 0x0a)) {\r\n\t\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"write block send data error\");\r\n\t\t\tbreak;\r\n\t\t};\t\r\n\t\r\n\t\tif (workFlags & 0x04) {\r\n\t\t\tif (mifare_classic_halt(NULL, cuid)) {\r\n\t\t\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Halt error\");\r\n\t\t\t\tbreak;\r\n\t\t\t};\r\n\t\t}\r\n\t\t\r\n\t\tisOK = 1;\r\n\t\tbreak;\r\n\t}\r\n\t\r\n//\tUsbCommand ack = {CMD_ACK, {isOK, 0, 0}};\r\n//\tif (isOK) memcpy(ack.d.asBytes, uid, 4);\r\n\t\r\n\t// add trace trailer\r\n\t/**\r\n\t*\tRemoved by Martin, the uid is overwritten with 0x44, \r\n\t*\twhich can 't be intended. \r\n\t*\r\n\t*\tmemset(uid, 0x44, 4);\r\n\t*\tLogTrace(uid, 4, 0, 0, TRUE);\r\n\t**/\r\n\t\r\n\r\n\tLED_B_ON();\r\n cmd_send(CMD_ACK,isOK,0,0,uid,4);\r\n//\tUsbSendPacket((uint8_t *)&ack, sizeof(UsbCommand));\r\n\tLED_B_OFF();\r\n\r\n\tif ((workFlags & 0x10) || (!isOK)) {\r\n\t\t// Thats it...\r\n\t\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\t\tLEDsoff();\r\n\t}\r\n}\r\n\r\nvoid MifareCGetBlock(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain){\r\n \r\n // params\r\n\t// bit 1 - need wupC\r\n\t// bit 2 - need HALT after sequence\r\n\t// bit 3 - need init FPGA and field before sequence\r\n\t// bit 4 - need reset FPGA and LED\r\n\tuint8_t workFlags = arg0;\r\n\tuint8_t blockNo = arg2;\r\n\t\r\n\t// card commands\r\n\tuint8_t wupC1[] = { 0x40 }; \r\n\tuint8_t wupC2[] = { 0x43 }; \r\n\t\r\n\t// variables\r\n\tbyte_t isOK = 0;\r\n\tuint8_t data[18];\r\n\tuint32_t cuid = 0;\r\n\t\r\n\tmemset(data, 0x00, 18);\r\n\tuint8_t* receivedAnswer = mifare_get_bigbufptr();\r\n\t\r\n\tif (workFlags & 0x08) {\r\n\t\t// clear trace\r\n\t\tiso14a_clear_trace();\r\n\t\tiso14a_set_tracing(TRUE);\r\n\r\n\t\tiso14443a_setup();\r\n\r\n\t\tLED_A_ON();\r\n\t\tLED_B_OFF();\r\n\t\tLED_C_OFF();\r\n\t\r\n\t\tSpinDelay(300);\r\n\t\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\t\tSpinDelay(100);\r\n\t\tFpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);\r\n\t}\r\n\r\n\twhile (true) {\r\n\t\tif (workFlags & 0x02) {\r\n ReaderTransmitBitsPar(wupC1,7,0);\r\n\t\t\tif(!ReaderReceive(receivedAnswer) || (receivedAnswer[0] != 0x0a)) {\r\n\t\t\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"wupC1 error\");\r\n\t\t\t\tbreak;\r\n\t\t\t};\r\n\r\n\t\t\tReaderTransmit(wupC2, sizeof(wupC2));\r\n\t\t\tif(!ReaderReceive(receivedAnswer) || (receivedAnswer[0] != 0x0a)) {\r\n\t\t\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"wupC2 error\");\r\n\t\t\t\tbreak;\r\n\t\t\t};\r\n\t\t}\r\n\r\n\t\t// read block\r\n\t\tif ((mifare_sendcmd_short(NULL, 0, 0x30, blockNo, receivedAnswer) != 18)) {\r\n\t\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"read block send command error\");\r\n\t\t\tbreak;\r\n\t\t};\r\n\t\tmemcpy(data, receivedAnswer, 18);\r\n\t\t\r\n\t\tif (workFlags & 0x04) {\r\n\t\t\tif (mifare_classic_halt(NULL, cuid)) {\r\n\t\t\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Halt error\");\r\n\t\t\t\tbreak;\r\n\t\t\t};\r\n\t\t}\r\n\t\t\r\n\t\tisOK = 1;\r\n\t\tbreak;\r\n\t}\r\n\t\r\n//\tUsbCommand ack = {CMD_ACK, {isOK, 0, 0}};\r\n//\tif (isOK) memcpy(ack.d.asBytes, data, 18);\r\n\t\r\n\t// add trace trailer\r\n\t/*\r\n\t* Removed by Martin, this piece of overwrites the 'data' variable \r\n\t* which is sent two lines down, and is obviously not correct. \r\n\t* \r\n\t* memset(data, 0x44, 4);\r\n\t* LogTrace(data, 4, 0, 0, TRUE);\r\n\t*/\r\n\tLED_B_ON();\r\n cmd_send(CMD_ACK,isOK,0,0,data,18);\r\n//\tUsbSendPacket((uint8_t *)&ack, sizeof(UsbCommand));\r\n\tLED_B_OFF();\r\n\r\n\tif ((workFlags & 0x10) || (!isOK)) {\r\n\t\t// Thats it...\r\n\t\tFpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r\n\t\tLEDsoff();\r\n\t}\r\n}\r\n\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/mifarecmd.h", "content": "//-----------------------------------------------------------------------------\r\n// Merlok - June 2011\r\n// Gerhard de Koning Gans - May 2008\r\n// Hagen Fritsch - June 2010\r\n//\r\n// This code is licensed to you under the terms of the GNU GPL, version 2 or,\r\n// at your option, any later version. See the LICENSE.txt file for the text of\r\n// the license.\r\n//-----------------------------------------------------------------------------\r\n// Routines to support ISO 14443 type A.\r\n//-----------------------------------------------------------------------------\r\n\r\n#ifndef __MIFARECMD_H\r\n#define __MIFARECMD_H\r\n\r\n#include \"proxmark3.h\"\r\n#include \"apps.h\"\r\n#include \"util.h\"\r\n#include \"string.h\"\r\n\r\n#include \"iso14443crc.h\"\r\n#include \"iso14443a.h\"\r\n#include \"crapto1.h\"\r\n#include \"mifareutil.h\"\r\n#include \"common.h\"\r\n\r\n\r\n#endif" }, { "path": "TamagotchiFriends/proxmark/armsrc/mifaresniff.c", "content": "//-----------------------------------------------------------------------------\r\n// Merlok - 2012\r\n//\r\n// This code is licensed to you under the terms of the GNU GPL, version 2 or,\r\n// at your option, any later version. See the LICENSE.txt file for the text of\r\n// the license.\r\n//-----------------------------------------------------------------------------\r\n// Routines to support mifare classic sniffer.\r\n//-----------------------------------------------------------------------------\r\n\r\n#include \"mifaresniff.h\"\r\n#include \"apps.h\"\r\n\r\nstatic int sniffState = SNF_INIT;\r\nstatic uint8_t sniffUIDType;\r\nstatic uint8_t sniffUID[8];\r\nstatic uint8_t sniffATQA[2];\r\nstatic uint8_t sniffSAK;\r\nstatic uint8_t sniffBuf[16];\r\nstatic int timerData = 0;\r\n\r\n\r\nint MfSniffInit(void){\r\n\trsamples = 0;\r\n\tmemset(sniffUID, 0x00, 8);\r\n\tmemset(sniffATQA, 0x00, 2);\r\n\tsniffSAK = 0;\r\n\tsniffUIDType = SNF_UID_4;\r\n\r\n\treturn 0;\r\n}\r\n\r\nint MfSniffEnd(void){\r\n//\tUsbCommand ack = {CMD_ACK, {0, 0, 0}};\r\n\r\n\tLED_B_ON();\r\n cmd_send(CMD_ACK,0,0,0,0,0);\r\n//\tUsbSendPacket((uint8_t *)&ack, sizeof(UsbCommand));\r\n\tLED_B_OFF();\r\n\r\n\treturn 0;\r\n}\r\n\r\nint RAMFUNC MfSniffLogic(const uint8_t * data, int len, uint32_t parity, int bitCnt, int reader) {\r\n\r\n\tif ((len == 1) && (bitCnt = 9) && (data[0] > 0x0F)) { \r\n\t\tsniffState = SNF_INIT;\r\n\t}\r\n\r\n\tswitch (sniffState) {\r\n\t\tcase SNF_INIT:{\r\n\t\t\tif ((reader) && (len == 1) && (bitCnt == 9) && ((data[0] == 0x26) || (data[0] == 0x52))) { \r\n\t\t\t\tsniffUIDType = SNF_UID_4;\r\n\t\t\t\tmemset(sniffUID, 0x00, 8);\r\n\t\t\t\tmemset(sniffATQA, 0x00, 2);\r\n\t\t\t\tsniffSAK = 0;\r\n\r\n\t\t\t\tsniffState = SNF_WUPREQ;\r\n\t\t\t}\r\n\t\t\tbreak;\r\n\t\t}\r\n\t\tcase SNF_WUPREQ:{\r\n\t\t\tif ((!reader) && (len == 2)) { \r\n\t\t\t\tmemcpy(sniffATQA, data, 2);\r\n\r\n\t\t\t\tsniffState = SNF_ATQA;\r\n\t\t\t}\r\n\t\t\tbreak;\r\n\t\t}\r\n\t\tcase SNF_ATQA:{\r\n\t\t\tif ((reader) && (len == 2) && (data[0] == 0x93) && (data[1] == 0x20)) { \r\n\t\t\t\tsniffState = SNF_ANTICOL1;\r\n\t\t\t}\r\n\t\t\tbreak;\r\n\t\t}\r\n\t\tcase SNF_ANTICOL1:{\r\n\t\t\tif ((!reader) && (len == 5) && ((data[0] ^ data[1] ^ data[2] ^ data[3]) == data[4])) { \r\n\t\t\t\tmemcpy(sniffUID + 3, data, 4);\r\n\t\t\t\r\n\t\t\t\tsniffState = SNF_UID1;\r\n\t\t\t}\r\n\t\t\tbreak;\r\n\t\t}\r\n\t\tcase SNF_UID1:{\r\n\t\t\tif ((reader) && (len == 9) && (data[0] == 0x93) && (data[1] == 0x70) && (CheckCrc14443(CRC_14443_A, data, 9))) { \r\n\t\t\t\tsniffState = SNF_SAK;\r\n\t\t\t}\r\n\t\t\tbreak;\r\n\t\t}\r\n\t\tcase SNF_SAK:{\r\n\t\t\tif ((!reader) && (len == 3) && (CheckCrc14443(CRC_14443_A, data, 3))) { \r\n\t\t\t\tsniffSAK = data[0];\r\n\t\t\t\tif (sniffUID[3] == 0x88) {\r\n\t\t\t\t\tsniffState = SNF_ANTICOL2;\r\n\t\t\t\t} else {\r\n\t\t\t\t\tsniffState = SNF_CARD_IDLE;\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\tbreak;\r\n\t\t}\r\n\t\tcase SNF_ANTICOL2:{\r\n\t\t\tif ((!reader) && (len == 5) && ((data[0] ^ data[1] ^ data[2] ^ data[3]) == data[4])) { \r\n\t\t\t\tmemcpy(sniffUID, data, 4);\r\n\t\t\t\tsniffUIDType = SNF_UID_7;\r\n\t\t\t\r\n\t\t\t\tsniffState = SNF_UID2;\r\n\t\t}\r\n\t\t\tbreak;\r\n\t\t}\r\n\t\tcase SNF_UID2:{\r\n\t\t\tif ((reader) && (len == 9) && (data[0] == 0x95) && (data[1] == 0x70) && (CheckCrc14443(CRC_14443_A, data, 9))) { \r\n\t\t\t\tsniffState = SNF_SAK;\r\n\tDbprintf(\"SNF_SAK\");\t\t\t\t\r\n\t\t\t}\r\n\t\t\tbreak;\r\n\t\t}\r\n\t\tcase SNF_CARD_IDLE:{\r\n\t\t\tsniffBuf[0] = 0xFF;\r\n\t\t\tsniffBuf[1] = 0xFF;\r\n\t\t\tmemcpy(sniffBuf + 2, sniffUID, 7);\r\n\t\t\tmemcpy(sniffBuf + 9, sniffATQA, 2);\r\n\t\t\tsniffBuf[11] = sniffSAK;\r\n\t\t\tsniffBuf[12] = 0xFF;\r\n\t\t\tsniffBuf[13] = 0xFF;\r\n\t\t\tLogTrace(sniffBuf, 14, 0, parity, true);\r\n\t\t\ttimerData = GetTickCount();\r\n\t\t}\r\n\t\tcase SNF_CARD_CMD:{\r\n\t\t\tLogTrace(data, len, 0, parity, true);\r\n\r\n\t\t\tsniffState = SNF_CARD_RESP;\r\n\t\t\ttimerData = GetTickCount();\r\n\t\t\tbreak;\r\n\t\t}\r\n\t\tcase SNF_CARD_RESP:{\r\n\t\t\tLogTrace(data, len, 0, parity, false);\r\n\r\n\t\t\tsniffState = SNF_CARD_CMD;\r\n\t\t\ttimerData = GetTickCount();\r\n\t\t\tbreak;\r\n\t\t}\r\n\t\r\n\t\tdefault:\r\n\t\t\tsniffState = SNF_INIT;\r\n\t\tbreak;\r\n\t}\r\n\r\n\treturn 0;\r\n}\r\n\r\nint RAMFUNC MfSniffSend(int maxTimeoutMs) {\r\n\tif (traceLen && (timerData + maxTimeoutMs < GetTickCount())) {\r\n\t\treturn intMfSniffSend();\r\n\t}\r\n\treturn 0;\r\n}\r\n\r\n// internal seding function. not a RAMFUNC.\r\nint intMfSniffSend() {\r\n\t\r\n\tint pckSize = 0;\r\n\tint pckLen = traceLen;\r\n\tint pckNum = 0;\r\n\t\r\n\tif (!traceLen) return 0;\r\n\r\n\tFpgaDisableSscDma();\r\n\r\n\twhile (pckLen > 0) {\r\n\t\tpckSize = MIN(32, pckLen);\r\n//\t\tUsbCommand ack = {CMD_ACK, {1, pckSize, pckNum}};\r\n//\t\tmemcpy(ack.d.asBytes, trace + traceLen - pckLen, pckSize);\r\n\t\r\n\t\tLED_B_ON();\r\n cmd_send(CMD_ACK,1,pckSize,pckNum,trace + traceLen - pckLen,pckSize);\r\n//\t\tUsbSendPacket((uint8_t *)&ack, sizeof(UsbCommand));\r\n//\t\tSpinDelay(20);\r\n\t\tLED_B_OFF();\r\n\r\n\t\tpckLen -= pckSize;\r\n\t\tpckNum++;\r\n\t}\r\n\r\n//\tUsbCommand ack = {CMD_ACK, {2, 0, 0}};\r\n\r\n\tLED_B_ON();\r\n cmd_send(CMD_ACK,2,0,0,0,0);\r\n//\tUsbSendPacket((uint8_t *)&ack, sizeof(UsbCommand));\r\n\tLED_B_OFF();\r\n\r\n\ttraceLen = 0;\r\n\tmemset(trace, 0x44, TRACE_SIZE);\r\n\t\r\n\treturn 1;\r\n}\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/mifaresniff.h", "content": "//-----------------------------------------------------------------------------\r\n// Merlok - June 2012\r\n//\r\n// This code is licensed to you under the terms of the GNU GPL, version 2 or,\r\n// at your option, any later version. See the LICENSE.txt file for the text of\r\n// the license.\r\n//-----------------------------------------------------------------------------\r\n// Routines to support mifare classic sniffer.\r\n//-----------------------------------------------------------------------------\r\n\r\n#ifndef __MIFARESNIFF_H\r\n#define __MIFARESNIFF_H\r\n\r\n#include \"proxmark3.h\"\r\n#include \"apps.h\"\r\n#include \"util.h\"\r\n#include \"string.h\"\r\n\r\n#include \"iso14443crc.h\"\r\n#include \"iso14443a.h\"\r\n#include \"crapto1.h\"\r\n#include \"mifareutil.h\"\r\n#include \"common.h\"\r\n\r\n#define SNF_INIT\t\t\t\t0\r\n#define SNF_NO_FIELD\t\t1\r\n#define SNF_WUPREQ\t\t\t2\r\n#define SNF_ATQA\t\t\t\t3\r\n#define SNF_ANTICOL1\t\t4\r\n#define SNF_UID1\t\t\t\t5\r\n#define SNF_ANTICOL2\t\t6\r\n#define SNF_UID2\t\t\t\t7\r\n#define SNF_SAK\t\t\t\t\t8\r\n#define SNF_CARD_IDLE\t\t9\r\n#define SNF_CARD_CMD\t\t10\r\n#define SNF_CARD_RESP\t\t11\r\n\r\n#define SNF_UID_4\t\t\t\t0\r\n#define SNF_UID_7\t\t\t\t0\r\n\r\nint MfSniffInit(void);\r\nint RAMFUNC MfSniffLogic(const uint8_t * data, int len, uint32_t parity, int bitCnt, int reader);\r\nint RAMFUNC MfSniffSend(int maxTimeoutMs);\r\nint intMfSniffSend();\r\nint MfSniffEnd(void);\r\n\r\n#endif" }, { "path": "TamagotchiFriends/proxmark/armsrc/mifareutil.c", "content": "//-----------------------------------------------------------------------------\r\n// Merlok, May 2011, 2012\r\n// Many authors, whom made it possible\r\n//\r\n// This code is licensed to you under the terms of the GNU GPL, version 2 or,\r\n// at your option, any later version. See the LICENSE.txt file for the text of\r\n// the license.\r\n//-----------------------------------------------------------------------------\r\n// Work with mifare cards.\r\n//-----------------------------------------------------------------------------\r\n\r\n#include \"proxmark3.h\"\r\n#include \"apps.h\"\r\n#include \"util.h\"\r\n#include \"string.h\"\r\n\r\n#include \"iso14443crc.h\"\r\n#include \"iso14443a.h\"\r\n#include \"crapto1.h\"\r\n#include \"mifareutil.h\"\r\n\r\nint MF_DBGLEVEL = MF_DBG_ALL;\r\n\r\n// memory management\r\nuint8_t* mifare_get_bigbufptr(void) {\r\n\treturn (((uint8_t *)BigBuf) + MIFARE_BUFF_OFFSET);\t// was 3560 - tied to other size changes\r\n}\r\nuint8_t* eml_get_bigbufptr_sendbuf(void) {\r\n\treturn (((uint8_t *)BigBuf) + RECV_CMD_OFFSET);\t\r\n}\r\nuint8_t* eml_get_bigbufptr_recbuf(void) {\r\n\treturn (((uint8_t *)BigBuf) + MIFARE_BUFF_OFFSET);\r\n}\r\nuint8_t* eml_get_bigbufptr_cardmem(void) {\r\n\treturn (((uint8_t *)BigBuf) + CARD_MEMORY);\r\n}\r\n\r\n// crypto1 helpers\r\nvoid mf_crypto1_decrypt(struct Crypto1State *pcs, uint8_t *data, int len){\r\n\tuint8_t\tbt = 0;\r\n\tint i;\r\n\t\r\n\tif (len != 1) {\r\n\t\tfor (i = 0; i < len; i++)\r\n\t\t\tdata[i] = crypto1_byte(pcs, 0x00, 0) ^ data[i];\r\n\t} else {\r\n\t\tbt = 0;\r\n\t\tfor (i = 0; i < 4; i++)\r\n\t\t\tbt |= (crypto1_bit(pcs, 0, 0) ^ BIT(data[0], i)) << i;\r\n\t\t\t\t\r\n\t\tdata[0] = bt;\r\n\t}\r\n\treturn;\r\n}\r\n\r\nvoid mf_crypto1_encrypt(struct Crypto1State *pcs, uint8_t *data, int len, uint32_t *par) {\r\n\tuint8_t bt = 0;\r\n\tint i;\r\n\tuint32_t mltpl = 1 << (len - 1); // for len=18 it=0x20000\r\n\t*par = 0;\r\n\tfor (i = 0; i < len; i++) {\r\n\t\tbt = data[i];\r\n\t\tdata[i] = crypto1_byte(pcs, 0x00, 0) ^ data[i];\r\n\t\t*par = (*par >> 1) | ( ((filter(pcs->odd) ^ oddparity(bt)) & 0x01) * mltpl );\r\n\t}\t\r\n\treturn;\r\n}\r\n\r\nuint8_t mf_crypto1_encrypt4bit(struct Crypto1State *pcs, uint8_t data) {\r\n\tuint8_t bt = 0;\r\n\tint i;\r\n\r\n\tfor (i = 0; i < 4; i++)\r\n\t\tbt |= (crypto1_bit(pcs, 0, 0) ^ BIT(data, i)) << i;\r\n\t\t\r\n\treturn bt;\r\n}\r\n\r\n// send commands\r\nint mifare_sendcmd_short(struct Crypto1State *pcs, uint8_t crypted, uint8_t cmd, uint8_t data, uint8_t* answer)\r\n{\r\n\treturn mifare_sendcmd_shortex(pcs, crypted, cmd, data, answer, NULL);\r\n}\r\n\r\nint mifare_sendcmd_shortex(struct Crypto1State *pcs, uint8_t crypted, uint8_t cmd, uint8_t data, uint8_t* answer, uint32_t * parptr)\r\n{\r\n\tuint8_t dcmd[4], ecmd[4];\r\n\tuint32_t pos, par, res;\r\n\r\n\tdcmd[0] = cmd;\r\n\tdcmd[1] = data;\r\n\tAppendCrc14443a(dcmd, 2);\r\n\t\r\n\tmemcpy(ecmd, dcmd, sizeof(dcmd));\r\n\t\r\n\tif (crypted) {\r\n\t\tpar = 0;\r\n\t\tfor (pos = 0; pos < 4; pos++)\r\n\t\t{\r\n\t\t\tecmd[pos] = crypto1_byte(pcs, 0x00, 0) ^ dcmd[pos];\r\n\t\t\tpar = (par >> 1) | ( ((filter(pcs->odd) ^ oddparity(dcmd[pos])) & 0x01) * 0x08 );\r\n\t\t}\t\r\n\r\n\t\tReaderTransmitPar(ecmd, sizeof(ecmd), par);\r\n\r\n\t} else {\r\n\t\tReaderTransmit(dcmd, sizeof(dcmd));\r\n\t}\r\n\r\n\tint len = ReaderReceivePar(answer, &par);\r\n\t\r\n\tif (parptr) *parptr = par;\r\n\r\n\tif (crypted == CRYPT_ALL) {\r\n\t\tif (len == 1) {\r\n\t\t\tres = 0;\r\n\t\t\tfor (pos = 0; pos < 4; pos++)\r\n\t\t\t\tres |= (crypto1_bit(pcs, 0, 0) ^ BIT(answer[0], pos)) << pos;\r\n\t\t\t\t\r\n\t\t\tanswer[0] = res;\r\n\t\t\t\r\n\t\t} else {\r\n\t\t\tfor (pos = 0; pos < len; pos++)\r\n\t\t\t{\r\n\t\t\t\tanswer[pos] = crypto1_byte(pcs, 0x00, 0) ^ answer[pos];\r\n\t\t\t}\r\n\t\t}\r\n\t}\r\n\t\r\n\treturn len;\r\n}\r\n\r\n// mifare commands\r\nint mifare_classic_auth(struct Crypto1State *pcs, uint32_t uid, uint8_t blockNo, uint8_t keyType, uint64_t ui64Key, uint64_t isNested) \r\n{\r\n\treturn mifare_classic_authex(pcs, uid, blockNo, keyType, ui64Key, isNested, NULL);\r\n}\r\n\r\nint mifare_classic_authex(struct Crypto1State *pcs, uint32_t uid, uint8_t blockNo, uint8_t keyType, uint64_t ui64Key, uint64_t isNested, uint32_t * ntptr) \r\n{\r\n\t// variables\r\n\tint len;\t\r\n\tuint32_t pos;\r\n\tuint8_t tmp4[4];\r\n\tbyte_t par = 0;\r\n\tbyte_t ar[4];\r\n\tuint32_t nt, ntpp; // Supplied tag nonce\r\n\t\r\n\tuint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };\r\n\tuint8_t* receivedAnswer = mifare_get_bigbufptr();\r\n\r\n\t// Transmit MIFARE_CLASSIC_AUTH\r\n\tlen = mifare_sendcmd_short(pcs, isNested, 0x60 + (keyType & 0x01), blockNo, receivedAnswer);\r\n if (MF_DBGLEVEL >= 4)\tDbprintf(\"rand nonce len: %x\", len); \r\n\tif (len != 4) return 1;\r\n\t\r\n\tar[0] = 0x55;\r\n\tar[1] = 0x41;\r\n\tar[2] = 0x49;\r\n\tar[3] = 0x92; \r\n\t\r\n\t// Save the tag nonce (nt)\r\n\tnt = bytes_to_num(receivedAnswer, 4);\r\n\r\n\t// ----------------------------- crypto1 create\r\n\tif (isNested)\r\n\t\tcrypto1_destroy(pcs);\r\n\r\n\t// Init cipher with key\r\n\tcrypto1_create(pcs, ui64Key);\r\n\r\n\tif (isNested == AUTH_NESTED) {\r\n\t\t// decrypt nt with help of new key \r\n\t\tnt = crypto1_word(pcs, nt ^ uid, 1) ^ nt;\r\n\t} else {\r\n\t\t// Load (plain) uid^nt into the cipher\r\n\t\tcrypto1_word(pcs, nt ^ uid, 0);\r\n\t}\r\n\r\n\t// some statistic\r\n\tif (!ntptr && (MF_DBGLEVEL >= 3))\r\n\t\tDbprintf(\"auth uid: %08x nt: %08x\", uid, nt); \r\n\t\r\n\t// save Nt\r\n\tif (ntptr)\r\n\t\t*ntptr = nt;\r\n\r\n\tpar = 0;\r\n\t// Generate (encrypted) nr+parity by loading it into the cipher (Nr)\r\n\tfor (pos = 0; pos < 4; pos++)\r\n\t{\r\n\t\tmf_nr_ar[pos] = crypto1_byte(pcs, ar[pos], 0) ^ ar[pos];\r\n\t\tpar = (par >> 1) | ( ((filter(pcs->odd) ^ oddparity(ar[pos])) & 0x01) * 0x80 );\r\n\t}\t\r\n\t\t\r\n\t// Skip 32 bits in pseudo random generator\r\n\tnt = prng_successor(nt,32);\r\n\r\n\t// ar+parity\r\n\tfor (pos = 4; pos < 8; pos++)\r\n\t{\r\n\t\tnt = prng_successor(nt,8);\r\n\t\tmf_nr_ar[pos] = crypto1_byte(pcs,0x00,0) ^ (nt & 0xff);\r\n\t\tpar = (par >> 1)| ( ((filter(pcs->odd) ^ oddparity(nt & 0xff)) & 0x01) * 0x80 );\r\n\t}\t\r\n\t\t\r\n\t// Transmit reader nonce and reader answer\r\n\tReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par);\r\n\r\n\t// Receive 4 bit answer\r\n\tlen = ReaderReceive(receivedAnswer);\r\n\tif (!len)\r\n\t{\r\n\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Authentication failed. Card timeout.\");\r\n\t\treturn 2;\r\n\t}\r\n\t\r\n\tmemcpy(tmp4, receivedAnswer, 4);\r\n\tntpp = prng_successor(nt, 32) ^ crypto1_word(pcs, 0,0);\r\n\t\r\n\tif (ntpp != bytes_to_num(tmp4, 4)) {\r\n\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Authentication failed. Error card response.\");\r\n\t\treturn 3;\r\n\t}\r\n\r\n\treturn 0;\r\n}\r\n\r\nint mifare_classic_readblock(struct Crypto1State *pcs, uint32_t uid, uint8_t blockNo, uint8_t *blockData) \r\n{\r\n\t// variables\r\n\tint len;\t\r\n\tuint8_t\tbt[2];\r\n\t\r\n\tuint8_t* receivedAnswer = mifare_get_bigbufptr();\r\n\t\r\n\t// command MIFARE_CLASSIC_READBLOCK\r\n\tlen = mifare_sendcmd_short(pcs, 1, 0x30, blockNo, receivedAnswer);\r\n\tif (len == 1) {\r\n\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Cmd Error: %02x\", receivedAnswer[0]); \r\n\t\treturn 1;\r\n\t}\r\n\tif (len != 18) {\r\n\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Cmd Error: card timeout. len: %x\", len); \r\n\t\treturn 2;\r\n\t}\r\n\r\n\tmemcpy(bt, receivedAnswer + 16, 2);\r\n\tAppendCrc14443a(receivedAnswer, 16);\r\n\tif (bt[0] != receivedAnswer[16] || bt[1] != receivedAnswer[17]) {\r\n\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Cmd CRC response error.\"); \r\n\t\treturn 3;\r\n\t}\r\n\t\r\n\tmemcpy(blockData, receivedAnswer, 16);\r\n\treturn 0;\r\n}\r\n\r\nint mifare_classic_writeblock(struct Crypto1State *pcs, uint32_t uid, uint8_t blockNo, uint8_t *blockData) \r\n{\r\n\t// variables\r\n\tint len, i;\t\r\n\tuint32_t pos;\r\n\tuint32_t par = 0;\r\n\tbyte_t res;\r\n\t\r\n\tuint8_t d_block[18], d_block_enc[18];\r\n\tuint8_t* receivedAnswer = mifare_get_bigbufptr();\r\n\t\r\n\t// command MIFARE_CLASSIC_WRITEBLOCK\r\n\tlen = mifare_sendcmd_short(pcs, 1, 0xA0, blockNo, receivedAnswer);\r\n\r\n\tif ((len != 1) || (receivedAnswer[0] != 0x0A)) { // 0x0a - ACK\r\n\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Cmd Error: %02x\", receivedAnswer[0]); \r\n\t\treturn 1;\r\n\t}\r\n\t\r\n\tmemcpy(d_block, blockData, 16);\r\n\tAppendCrc14443a(d_block, 16);\r\n\t\r\n\t// crypto\r\n\tpar = 0;\r\n\tfor (pos = 0; pos < 18; pos++)\r\n\t{\r\n\t\td_block_enc[pos] = crypto1_byte(pcs, 0x00, 0) ^ d_block[pos];\r\n\t\tpar = (par >> 1) | ( ((filter(pcs->odd) ^ oddparity(d_block[pos])) & 0x01) * 0x20000 );\r\n\t}\t\r\n\r\n\tReaderTransmitPar(d_block_enc, sizeof(d_block_enc), par);\r\n\r\n\t// Receive the response\r\n\tlen = ReaderReceive(receivedAnswer);\t\r\n\r\n\tres = 0;\r\n\tfor (i = 0; i < 4; i++)\r\n\t\tres |= (crypto1_bit(pcs, 0, 0) ^ BIT(receivedAnswer[0], i)) << i;\r\n\r\n\tif ((len != 1) || (res != 0x0A)) {\r\n\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"Cmd send data2 Error: %02x\", res); \r\n\t\treturn 2;\r\n\t}\r\n\t\r\n\treturn 0;\r\n}\r\n\r\nint mifare_classic_halt(struct Crypto1State *pcs, uint32_t uid) \r\n{\r\n\t// variables\r\n\tint len;\t\r\n\t\r\n\t// Mifare HALT\r\n\tuint8_t* receivedAnswer = mifare_get_bigbufptr();\r\n\r\n\tlen = mifare_sendcmd_short(pcs, pcs == NULL ? 0:1, 0x50, 0x00, receivedAnswer);\r\n\tif (len != 0) {\r\n\t\tif (MF_DBGLEVEL >= 1)\tDbprintf(\"halt error. response len: %x\", len); \r\n\t\treturn 1;\r\n\t}\r\n\r\n\treturn 0;\r\n}\r\n\r\n// work with emulator memory\r\nvoid emlSetMem(uint8_t *data, int blockNum, int blocksCount) {\r\n\tuint8_t* emCARD = eml_get_bigbufptr_cardmem();\r\n\t\r\n\tmemcpy(emCARD + blockNum * 16, data, blocksCount * 16);\r\n}\r\n\r\nvoid emlGetMem(uint8_t *data, int blockNum, int blocksCount) {\r\n\tuint8_t* emCARD = eml_get_bigbufptr_cardmem();\r\n\t\r\n\tmemcpy(data, emCARD + blockNum * 16, blocksCount * 16);\r\n}\r\n\r\nvoid emlGetMemBt(uint8_t *data, int bytePtr, int byteCount) {\r\n\tuint8_t* emCARD = eml_get_bigbufptr_cardmem();\r\n\t\r\n\tmemcpy(data, emCARD + bytePtr, byteCount);\r\n}\r\n\r\nint emlCheckValBl(int blockNum) {\r\n\tuint8_t* emCARD = eml_get_bigbufptr_cardmem();\r\n\tuint8_t* data = emCARD + blockNum * 16;\r\n\r\n\tif ((data[0] != (data[4] ^ 0xff)) || (data[0] != data[8]) ||\r\n\t\t\t(data[1] != (data[5] ^ 0xff)) || (data[1] != data[9]) ||\r\n\t\t\t(data[2] != (data[6] ^ 0xff)) || (data[2] != data[10]) ||\r\n\t\t\t(data[3] != (data[7] ^ 0xff)) || (data[3] != data[11]) ||\r\n\t\t\t(data[12] != (data[13] ^ 0xff)) || (data[12] != data[14]) ||\r\n\t\t\t(data[12] != (data[15] ^ 0xff))\r\n\t\t ) \r\n\t\treturn 1;\r\n\treturn 0;\r\n}\r\n\r\nint emlGetValBl(uint32_t *blReg, uint8_t *blBlock, int blockNum) {\r\n\tuint8_t* emCARD = eml_get_bigbufptr_cardmem();\r\n\tuint8_t* data = emCARD + blockNum * 16;\r\n\t\r\n\tif (emlCheckValBl(blockNum)) {\r\n\t\treturn 1;\r\n\t}\r\n\t\r\n\tmemcpy(blReg, data, 4);\r\n\t*blBlock = data[12];\r\n\t\r\n\treturn 0;\r\n}\r\n\r\nint emlSetValBl(uint32_t blReg, uint8_t blBlock, int blockNum) {\r\n\tuint8_t* emCARD = eml_get_bigbufptr_cardmem();\r\n\tuint8_t* data = emCARD + blockNum * 16;\r\n\t\r\n\tmemcpy(data + 0, &blReg, 4);\r\n\tmemcpy(data + 8, &blReg, 4);\r\n\tblReg = blReg ^ 0xffffffff;\r\n\tmemcpy(data + 4, &blReg, 4);\r\n\t\r\n\tdata[12] = blBlock;\r\n\tdata[13] = blBlock ^ 0xff;\r\n\tdata[14] = blBlock;\r\n\tdata[15] = blBlock ^ 0xff;\r\n\t\r\n\treturn 0;\r\n}\r\n\r\nuint64_t emlGetKey(int sectorNum, int keyType) {\r\n\tuint8_t key[6];\r\n\tuint8_t* emCARD = eml_get_bigbufptr_cardmem();\r\n\t\r\n\tmemcpy(key, emCARD + 3 * 16 + sectorNum * 4 * 16 + keyType * 10, 6);\r\n\treturn bytes_to_num(key, 6);\r\n}\r\n\r\nvoid emlClearMem(void) {\r\n\tint b;\r\n\t\r\n\tconst uint8_t trailer[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07, 0x80, 0x69, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\r\n\tconst uint8_t uid[] = {0xe6, 0x84, 0x87, 0xf3, 0x16, 0x88, 0x04, 0x00, 0x46, 0x8e, 0x45, 0x55, 0x4d, 0x70, 0x41, 0x04};\r\n\tuint8_t* emCARD = eml_get_bigbufptr_cardmem();\r\n\t\r\n\tmemset(emCARD, 0, CARD_MEMORY_LEN);\r\n\t\r\n\t// fill sectors trailer data\r\n\tfor(b = 3; b < 256; b<127?(b+=4):(b+=16)) {\r\n\t\temlSetMem((uint8_t *)trailer, b , 1);\r\n\t}\t\r\n\r\n\t// uid\r\n\temlSetMem((uint8_t *)uid, 0, 1);\r\n\treturn;\r\n}\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/mifareutil.h", "content": "//-----------------------------------------------------------------------------\r\n// Merlok, May 2011\r\n// Many authors, that makes it possible\r\n//\r\n// This code is licensed to you under the terms of the GNU GPL, version 2 or,\r\n// at your option, any later version. See the LICENSE.txt file for the text of\r\n// the license.\r\n//-----------------------------------------------------------------------------\r\n// code for work with mifare cards.\r\n//-----------------------------------------------------------------------------\r\n\r\n#ifndef __MIFAREUTIL_H\r\n#define __MIFAREUTIL_H\r\n\r\n// mifare authentication\r\n#define CRYPT_NONE 0\r\n#define CRYPT_ALL 1\r\n#define CRYPT_REQUEST 2\r\n#define AUTH_FIRST 0\r\n#define AUTH_NESTED 2\r\n\r\n// mifare 4bit card answers\r\n#define CARD_ACK 0x0A // 1010 - ACK\r\n#define CARD_NACK_NA 0x04 // 0100 - NACK, not allowed (command not allowed)\r\n#define CARD_NACK_TR 0x05 // 0101 - NACK, transmission error\r\n\r\n// reader voltage field detector\r\n#define MF_MINFIELDV 4000\r\n\r\n// debug\r\n// 0 - no debug messages 1 - error messages 2 - all messages 4 - extended debug mode\r\n#define MF_DBG_NONE 0\r\n#define MF_DBG_ERROR 1\r\n#define MF_DBG_ALL 2\r\n#define MF_DBG_EXTENDED 4\r\n\r\nextern int MF_DBGLEVEL;\r\n\r\n//mifare nested\r\n#define MEM_CHUNK 10000\r\n#define TRY_KEYS 50\r\n#define NS_TOLERANCE 10 // [distance avg-value, distance avg+value]\r\n#define NS_RETRIES_GETNONCE 15\r\n#define NES_MAX_INFO 5\r\n\r\n//mifare emulator states\r\n#define MFEMUL_NOFIELD 0\r\n#define MFEMUL_IDLE 1\r\n#define MFEMUL_SELECT1 2\r\n#define MFEMUL_SELECT2 3\r\n#define MFEMUL_AUTH1 4\r\n#define MFEMUL_AUTH2 5\r\n#define MFEMUL_WORK\t 6\r\n#define MFEMUL_WRITEBL2 7\r\n#define MFEMUL_INTREG_INC 8\r\n#define MFEMUL_INTREG_DEC 9\r\n#define MFEMUL_INTREG_REST 10\r\n#define MFEMUL_HALTED 11\r\n\r\n#define cardSTATE_TO_IDLE() cardSTATE = MFEMUL_IDLE; LED_B_OFF(); LED_C_OFF();\r\n\r\n//functions\r\nuint8_t* mifare_get_bigbufptr(void);\r\nint mifare_sendcmd_short(struct Crypto1State *pcs, uint8_t crypted, uint8_t cmd, uint8_t data, uint8_t* answer);\r\nint mifare_sendcmd_shortex(struct Crypto1State *pcs, uint8_t crypted, uint8_t cmd, uint8_t data, uint8_t* answer, uint32_t * parptr);\r\n\r\nint mifare_classic_auth(struct Crypto1State *pcs, uint32_t uid, \\\r\n\t\t\t\t\t\t\t\t\t\t\t\tuint8_t blockNo, uint8_t keyType, uint64_t ui64Key, uint64_t isNested);\r\nint mifare_classic_authex(struct Crypto1State *pcs, uint32_t uid, \\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\tuint8_t blockNo, uint8_t keyType, uint64_t ui64Key, uint64_t isNested, uint32_t * ntptr);\r\nint mifare_classic_readblock(struct Crypto1State *pcs, uint32_t uid, uint8_t blockNo, uint8_t *blockData); \r\nint mifare_classic_writeblock(struct Crypto1State *pcs, uint32_t uid, uint8_t blockNo, uint8_t *blockData);\r\nint mifare_classic_halt(struct Crypto1State *pcs, uint32_t uid); \r\n\r\n// crypto functions\r\nvoid mf_crypto1_decrypt(struct Crypto1State *pcs, uint8_t *receivedCmd, int len);\r\nvoid mf_crypto1_encrypt(struct Crypto1State *pcs, uint8_t *data, int len, uint32_t *par);\r\nuint8_t mf_crypto1_encrypt4bit(struct Crypto1State *pcs, uint8_t data);\r\n\r\n// memory management\r\nuint8_t* mifare_get_bigbufptr(void);\r\nuint8_t* eml_get_bigbufptr_sendbuf(void);\r\nuint8_t* eml_get_bigbufptr_recbuf(void);\r\n\r\n// emulator functions\r\nvoid emlClearMem(void);\r\nvoid emlSetMem(uint8_t *data, int blockNum, int blocksCount);\r\nvoid emlGetMem(uint8_t *data, int blockNum, int blocksCount);\r\nvoid emlGetMemBt(uint8_t *data, int bytePtr, int byteCount);\r\nuint64_t emlGetKey(int sectorNum, int keyType);\r\nint emlGetValBl(uint32_t *blReg, uint8_t *blBlock, int blockNum);\r\nint emlSetValBl(uint32_t blReg, uint8_t blBlock, int blockNum);\r\nint emlCheckValBl(int blockNum);\r\n\r\n#endif" }, { "path": "TamagotchiFriends/proxmark/armsrc/obj/appmain.d", "content": "obj/appmain.d obj/appmain.o: appmain.c ../common/usb_cdc.h \\\r\n ../include/common.h stdint.h ../include/at91sam7s512.h ../common/cmd.h \\\r\n ../include/usb_cmd.h ../common/usb_cdc.h ../include/proxmark3.h \\\r\n ../include/at91sam7s512.h ../include/config_gpio.h apps.h \\\r\n ../include/hitag2.h ../include/mifare.h ../include/common.h util.h \\\r\n printf.h string.h legicrf.h\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/obj/cmd.d", "content": "obj/cmd.d obj/cmd.o: ../common/cmd.c ../common/cmd.h ../include/common.h \\\r\n stdint.h ../include/at91sam7s512.h ../include/usb_cmd.h \\\r\n ../common/usb_cdc.h string.h ../include/proxmark3.h \\\r\n ../include/at91sam7s512.h ../include/config_gpio.h\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/obj/crapto1.d", "content": "obj/crapto1.d obj/crapto1.o: crapto1.c crapto1.h stdint.h\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/obj/crc.d", "content": "obj/crc.d obj/crc.o: ../common/crc.c ../include/crc.h stdint.h\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/obj/crc16.d", "content": "obj/crc16.d obj/crc16.o: ../common/crc16.c ../common/crc16.h\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/obj/crypto1.d", "content": "obj/crypto1.d obj/crypto1.o: crypto1.c crapto1.h stdint.h\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/obj/epa.d", "content": "obj/epa.d obj/epa.o: epa.c iso14443a.h ../include/common.h stdint.h \\\r\n ../include/at91sam7s512.h mifaresniff.h ../include/proxmark3.h \\\r\n ../include/at91sam7s512.h ../include/config_gpio.h ../include/usb_cmd.h \\\r\n apps.h ../include/hitag2.h ../include/mifare.h ../include/common.h \\\r\n util.h string.h ../common/iso14443crc.h crapto1.h mifareutil.h epa.h \\\r\n ../common/cmd.h ../common/usb_cdc.h\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/obj/fpgaimage.s19", "content": "S01400006F626A2F66706761696D6167652E733139D5\r\nS3150000200000090FF00FF00FF00FF000000161001053\r\nS31500002010667067612D706C616365642E6E63640023\r\nS3150000202062000A3273333076713130300063000B50\r\nS31500002030323031322F20312F2036006400093135FD\r\nS315000020403A32373A353600650000A470FFFFFFFFCD\r\nS31500002050AA99556630008001000000073001600132\r\nS31500002060000000083001200100803F2D3000C00133\r\nS31500002070000000003000800100000009300020014F\r\nS315000020800000000030008001000000013000400028\r\nS315000020905000246300121000000000000000000041\r\nS315000020A0000000000000000000000000000000002A\r\nS315000020B00000048000000000001210000000000074\r\nS315000020C0000000000000000000000000000000000A\r\nS315000020D0000000000000048000000000090300006A\r\nS315000020E000000000000000000000000000000000EA\r\nS315000020F0000000000000000000004080000000001A\r\nS3150000210000020000000000000000000000000000C7\r\nS315000021100000000000000000000000000000008039\r\nS315000021200000000000120000000000000000000097\r\nS315000021300000000000000000000000000000000099\r\nS31500002140000004A0000000000012000000000000D3\r\nS315000021500000000000000000000000000000000079\r\nS315000021600000000000000480000000000012400093\r\nS315000021700000000000000000000000000000000059\r\nS315000021800000000000000000000004E00000000065\r\nS31500002190F6100060001800060001800060001900BB\r\nS315000021A0068003800068003B800E8007203F842065\r\nS315000021B000000000C001FA40E7803FC20CD0833621\r\nS315000021C0007F0033C00CF1033C01CE8033E00CE20B\r\nS315000021D002300070000000008010E8808B802EF036\r\nS315000021E00894022600B7C02BF008F7021D428202AF\r\nS315000021F022C008610A200430000000008805C800DB\r\nS31500002200A1002C600A92820400BB4222C40830025C\r\nS315000022100C00828022C0082002220170000000000B\r\nS31500002220C015AA008B802EC00AA0822C84B3002A77\r\nS31500002230C108B0020C008A8022C80820023004605F\r\nS31500002240000000000015EA20EBE03E800E98012415\r\nS3150000225000FB0230C02CD8032C008A8032C02CA090\r\nS315000022600310047000000000E001B804FF003FC046\r\nS315000022700D990BFE28FF003FC00F9903FC00FE00DE\r\nS31500002280BFE00FE003F80060000000004010A80067\r\nS31500002290DB02328C0FB4832400FB0032C00F100324\r\nS315000022A02C00CA0C32C00CA1031004200000000050\r\nS315000022B0C8052A008B0020900326022700BFC037DE\r\nS315000022C0DC4B90223C00CA0020C028E402320040C9\r\nS315000022D000000000E00568809300A0C11314468743\r\nS315000022E000B3D820C00B10020C008A0024C00828B6\r\nS315000022F0027900500000000020011A048F8021E0BE\r\nS315000023000B59029620BF9065E40B58021E4096902A\r\nS31500002310A5E4086C024800400000000048082C6054\r\nS31500002320D02030480B310B8C04F300B0C00F1003E3\r\nS315000023300C00C21036C02C200B5202000000000018\r\nS31500002340400DBC50FE003FC007E1437C00FF453F07\r\nS31500002350C00FD903FC12EE143BC00FE103900260DC\r\nS3150000236000000000A855EC08F8003E990F8003AC69\r\nS3150000237000FBA0B2F82CB2032C02CB0132522CA2E5\r\nS31500002380832A00700000000048119400B6002DC298\r\nS315000023908B50431C08B74021DA0870823DC0860185\r\nS315000023A061C008640212046000000000C0009E20A4\r\nS315000023B0B4886DE00B2802D600B3A024E0083802EA\r\nS315000023C01E11878021E0086802300020000000000E\r\nS315000023D04814EC00B2082CD80BAF020600B3002458\r\nS315000023E0C00838022C0580E022E088200212043062\r\nS315000023F000000000E805B840FE403E800FE403EA16\r\nS3150000240020FA0036800CAA0B2800CEC1A2A00CE050\r\nS315000024100B3A0460000000004800E000F8002E04BB\r\nS315000024200F8003E000F8043A000F0003E000F81004\r\nS315000024303E044F0003D20030000000000800E4080C\r\nS31500002440D9223EF04F98032440C9003E500B90031A\r\nS315000024502400C90032E80C9003020430000000009A\r\nS315000024608044678089832E420B9802870089402E1C\r\nS31500002470480990022500C900226088908AA00010B1\r\nS31500002480000000001805260099002E400B95022436\r\nS315000024902089086E404B90222502810022408890B8\r\nS315000024A002060040000000000814050081002C40D0\r\nS315000024B00B1402A40081002C4009140204008100C0\r\nS315000024C0204008100282010000000000B80D6000E4\r\nS315000024D0D8003E200B88132002C8803E200F880BB0\r\nS315000024E02200C000B0002C02832E03500000000022\r\nS315000024F09815F614FD003E500FDC03F400F9403F3A\r\nS31500002500500FDC03E5A0ED28BE4A0FD283E6067025\r\nS31500002510000000001801F400CD00B3406CD0032485\r\nS3150000252000B90032400F9803A410C90032400C9441\r\nS3150000253003060070000000003810E000880022004A\r\nS315000025408C800A2018B00237000B8502228288A1EF\r\nS31500002550222888C8020E0430000000000805C400C6\r\nS31500002560890028400818420400BD0021400B1002D3\r\nS3150000257014209508A14228500202017000000000B4\r\nS315000025801815A4808B802A428890022400B5002763\r\nS31500002590400B900284009D00214000D0020604609A\r\nS315000025A000000000A014A782C1E03A700C98032630\r\nS315000025B040F900B2400F900B2400D98032600C9095\r\nS315000025C00B280470000000002800A400F90036441F\r\nS315000025D00E9273EC00F9003E400F90036400E92070\r\nS315000025E03E500F9003CA0060000000002810A200B1\r\nS315000025F0F8003C120C82432000FC0032000F00035E\r\nS31500002600E000C80032000CC0030A042000000000ED\r\nS3150000261028043820BEC00FB208E64A2A20BA003E77\r\nS31500002620B80BA000E8008A0022800AE80A8A004067\r\nS315000026300000000028056C00B1222CC0B8A00206DC\r\nS3150000264000B00020284B3000CE008B8020C00AA8A6\r\nS31500002650220A00500000000020011C04B5402D8015\r\nS315000026600850021400BE002DC00B7002DD0086402B\r\nS3150000267023C02A2082A800400000000028081E006F\r\nS31500002680F5803CE00CE8031A00F58031E00F788312\r\nS31500002690FA02CF80B1600E78032A02000000000023\r\nS315000026A0081DA400F9003E800F9003E8B0FB003E31\r\nS315000026B0C00FB303E802FA003C402FB003C2066025\r\nS315000026C0000000004005FE00FC903FE40FF81B3EB2\r\nS315000026D010CC8033E00CF8033600CD8033E00FC811\r\nS315000026E02300007000000000A8119400B4102D0E05\r\nS315000026F00BD2021C00861421D0087102140084102B\r\nS3150000270021C04BC0022A04600000000000009800AF\r\nS31500002710B4112DD01B50421000810020C008700259\r\nS3150000272010008D0021420B5802000020000000001E\r\nS315000027306014E200B0802C800B90020240830020DF\r\nS31500002740C008B0020000881020400B1002080430B8\r\nS3150000275000000000A815A480F9083EF00F8A0324A3\r\nS3150000276002C90232C00CF0022C00CB8030A00FA0B0\r\nS315000027700B2A0460000000008000E100F9442E806E\r\nS315000027800F9043E000FB403EC00FB003CC00FA00C0\r\nS315000027903E900FA003E00030000000000110F4009E\r\nS315000027A0CFC033010FD0833840FD00B3C00FF00314\r\nS315000027B02800CF0833000CF003004430000000006E\r\nS315000027C08104622083C02A200B988A2000BB402205\r\nS315000027D0D04BB00A38028E01A31108700A204010AF\r\nS315000027E000000000800566008B0222A20B98022CD6\r\nS315000027F020B10822E00BB002240089002282088062\r\nS3150000280002200040000000000800000083002800AD\r\nS315000028100B10020000BB0020C00B30020400800039\r\nS31500002820228008800202010000000000000860000B\r\nS31500002830CB0032000F90032000F90232C00F700760\r\nS315000028402000C90032008C900300035000000000F5\r\nS31500002850A00DF002FF003F000FD023D000FF003F85\r\nS31500002860C00FF003F000F4003F000FD003E806703D\r\nS3150000287000000000C005FC00CF0033000D580336F1\r\nS3150000288004FC8033200CF0031A02CF0833E80CE96D\r\nS3150000289003300070000000008010EC648A5A222089\r\nS315000028A00B98036200B8002248089D02AC208BC03A\r\nS315000028B035D508E902200430000000008805CC80E8\r\nS315000028C0A02420200B300A0400B100204208100288\r\nS315000028D02C80830020CA08200A2201700000000014\r\nS315000028E0C015AC00A90822200B90006220B9000296\r\nS315000028F040089002AC008B0026C0282002300460FD\r\nS31500002900000000004015EC08CC4032000D100122FA\r\nS3150000291000F9A032602C71030880CB0032C00CA0F5\r\nS315000029200B10047000000000E001AC005020BFC096\r\nS3150000293003D043F000FDC03F040F9803FE80FB0068\r\nS315000029403DC00FA003F90060000000004010AC007D\r\nS31500002950CB5032000FB2032820F9443E400C9003BE\r\nS315000029602D00CB0032C14CA00B100420000000004B\r\nS31500002970C8053C008B80222C0B9E0A2900B9102E1C\r\nS31500002980414D91022C00878023C04AE00A32004064\r\nS3150000299000000000E0056C10000020E00B14028F20\r\nS315000029A040B8502E4008140A0C00838020C008202E\r\nS315000029B0027800500000000020011E008480216182\r\nS315000029C00B59029E00B4902F600978023E02879848\r\nS315000029D021E00A69024800400000000048080C4057\r\nS315000029E08320B0C40F31038C00F1103C000C30037F\r\nS315000029F00C44C300B0C00C200352020000000000CB\r\nS31500002A00401DBC10FF003FC00FD1037C407D113D2F\r\nS31500002A10400FF103FC00FF003FC40FE00390066087\r\nS31500002A2000000000A805EC00E80032800F90132E8D\r\nS31500002A3000C98032400F10032C00FB1032C80C2353\r\nS31500002A40032A00700000000048119D00B400A1C4D4\r\nS31500002A500B50035C008D0021400B70021400B78000\r\nS31500002A602BC20D610A12046000000000C0009E80A7\r\nS31500002A70B780A1E00B78021F00858021600B7802E9\r\nS31500002A801F00B38061E408EA027000200000000025\r\nS31500002A904814CC00B34020D90B10024D0082882088\r\nS31500002AA0800B301A0600B30028C0292002520410F9\r\nS31500002AB000000000E815A800FE00B2804F20023991\r\nS31500002AC002CE60B3980F20031A00FA0032800CE0A1\r\nS31500002AD0037A0460000000004800E000F818BE1009\r\nS31500002AE00F8413E000F8003E020F8003E000F800B8\r\nS31500002AF03C000F8003920030000000000810E40044\r\nS31500002B00F19032C00F90132420F9803E400C9C4374\r\nS31500002B102400C120B240AC900B020430000000003B\r\nS31500002B2080046400B90022600B9602A500B9D02C7F\r\nS31500002B30400A9C02240089003240089002200010BE\r\nS31500002B400000000018052400B900A2440B912224BD\r\nS31500002B5060B9402EC0189402240089002240281033\r\nS31500002B60020600400000000008040500B1402040B5\r\nS31500002B704B10028400B1442E500A100225009328FF\r\nS31500002B80204608120202010000000000B80D620093\r\nS31500002B90F08032A04F80022000F8003E000C880B27\r\nS31500002BA02002C82032100C83032E035000000000C0\r\nS31500002BB0981DE700FDC03E504F5003D400FD843FF2\r\nS31500002BC0600BD403F600E9013A49039303E6067065\r\nS31500002BD0000000001805E400FD80B3C083500334F4\r\nS31500002BE000FD0432404CD8132504ED0232400C900F\r\nS31500002BF053061270000000003810E000BAE222000E\r\nS31500002C000B80022000B800A0800D800A2A008801EF\r\nS31500002C1036000880020E0030000000000805C400DF\r\nS31500002C20B14820610B104A0400B100224108140289\r\nS31500002C300400A100204008100202017000000000FC\r\nS31500002C401811A400B90022618B98022C00BB002247\r\nS31500002C504009980224008900264008901206046064\r\nS31500002C6000000000A011E400F9C0B2600F180324B0\r\nS31500002C7040F96030700C90032400E90032402C903B\r\nS31500002C800B280470000000002801A400F9203E4033\r\nS31500002C904B9003E600F9203E640F1003E400F100B8\r\nS31500002CA03C402F9003CA0060000000002810A000DE\r\nS31500002CB0E840B2020F81832080C8483E102C88036A\r\nS31500002CC0E000F8003E012C80030A0420000000000A\r\nS31500002CD028052800BA0023988BE813F800DE882E12\r\nS31500002CE08008E002E800BE202E8008A0020A1040FC\r\nS31500002CF00000000028054C01BB0060D00338060F19\r\nS31500002D00008A022CC0083102EC00B3082CC008B0BF\r\nS31500002D10028A005000000000A0011C41B50021807D\r\nS31500002D208B7016DF1097042DC8087002DC00B50002\r\nS31500002D302DC008700228004000000000A8081E8070\r\nS31500002D40E19431A00F78031E00C6803DF00C780395\r\nS31500002D50DE00F6803CF00CF80BAA00000000000034\r\nS31500002D60081DAC08FB60BE804FB003C404F9013EE9\r\nS31500002D70C84FB003FE00FA003ECA0FB783C2146004\r\nS31500002D80000000000005FE01FF9033E10CF8033E51\r\nS31500002D9000F79013F00CF903FE00FE8033E08CF888\r\nS31500002DA04300007000000000A8119C00B53021848B\r\nS31500002DB00872035C40B51035C80D7002DC00B61011\r\nS31500002DC021C00D70022A04600000000000009C0073\r\nS31500002DD0B580A10208F0021C00BE1023C0087002D4\r\nS31500002DE0DC00B60021C4083002000020000000000C\r\nS31500002DF02014CC00BB4020A00811064500B02024BA\r\nS31500002E00D4093002ED00B20020C009300A080430AF\r\nS31500002E1000000000A815BC00FB0032F00C98032D42\r\nS31500002E2000F88033F408B003FC40FA0033C00CF01D\r\nS31500002E30032A0460000000008000EC00F9083C084A\r\nS31500002E400F9003EC00F8103EC00FB803EC40FA00F8\r\nS31500002E503EC00F3003E00030000000000110FC000F\r\nS31500002E60FD0033C00CF003FAA0CE0033C00FF00310\r\nS31500002E70FC02C20033C00CF0130044300000000016\r\nS31500002E8081046C00BF0022200AB802C10480802A97\r\nS31500002E90C00BB802FC048AC8A2C028B00A20501091\r\nS31500002EA00000000080052C00BB0022B0499882EC8F\r\nS31500002EB0008B8022C00B9802EC008A8020C008B0EC\r\nS31500002EC0022000400000000008040C00B100A00031\r\nS31500002ED00B1032EC00890028C00B1802CC008200CF\r\nS31500002EE020C008300202010000000000000D6C0046\r\nS31500002EF0F50032000DB013E802CB0133C00FA0037A\r\nS31500002F00EC00CA0031C00CF02300035000000000A2\r\nS31500002F10A01DFC00FF00BD000E4003FC00FD013DAE\r\nS31500002F20C00FF003FC00FE003FC08FF003E8067000\r\nS31500002F3000000000C001D480C7803DE00CD083367D\r\nS31500002F4000C78033E00CF8039E00CC803DE00CD82F\r\nS31500002F5003300070000000008010E6008B842EE035\r\nS31500002F60409C02220088802A200888022600AA01A6\r\nS31500002F702EE00CB002200430000000008805E4407A\r\nS31500002F8081002CC00210420C00A10020400810460F\r\nS31500002F90000082006EC0B8B002220170000000007E\r\nS31500002FA0C015A6048A802ED06A98022800AA002A94\r\nS31500002FB08048A0022800AA002EF009B00230046062\r\nS31500002FC0000000004011E600C9803EF08E1C03059B\r\nS31500002FD080EB0032C02CB00A2C02CA003E700C30C6\r\nS31500002FE00B10047000000000E001BC01FF083FC4A4\r\nS31500002FF00D8083F002DC003F000FC0437400FC40EC\r\nS315000030003F400ED403F80060000000004010A540C9\r\nS31500003010C900B2C80C90036D00C98032600C9801DB\r\nS31500003020E040CA803E548CB003D00420000000006B\r\nS31500003030C8050F01DAC820F8188C03280082403032\r\nS31500003040900D20080818DA002C600ABB02F2004036\r\nS3150000305000000000E005449283C120D00811024020\r\nS315000030600A820824821924820E0082002C62093406\r\nS3150000307002F800500000000020013A40878023E05B\r\nS3150000308018781216008580616009590217509690CB\r\nS315000030902F640B7802C800400000000048080900B1\r\nS315000030A0832030C428200B4800C04074100D050B47\r\nS315000030B08000C0003C408D1023D2020000000000BA\r\nS315000030C04019B810FE003FC40BE103DC40FF009539\r\nS315000030D0C00F7103BA04FE043F404EF003D00660F1\r\nS315000030E000000000A805E400CB0032C00FB803C002\r\nS315000030F002CA003C810C20032C00CA0030402CB0D0\r\nS3150000310003EA00700000000048119C00870021C0FF\r\nS315000031100B7052140085002D400A50029400860060\r\nS315000031202100087002D2046000000000C000960072\r\nS315000031308F8001300B28029A0094846D2018480273\r\nS3150000314012008E806360187802F0002000000000F4\r\nS315000031504814CF02820120510B2D020C0093002C43\r\nS31500003160C04A3032880280806050181002D3043082\r\nS3150000317000000000E815B980CE88B3B00FE103A8BF\r\nS315000031800292003E800CA0012800CE8031840CA261\r\nS3150000319003FA0460000000004800E120F8003E0841\r\nS315000031A08F8003B000EC003F000FC003F000F85022\r\nS315000031B0BE102F8403D20030000000000810E44344\r\nS315000031C0C90032410C9223E400C900324008902322\r\nS315000031D02400C90036680C9803C2043000000000C1\r\nS315000031E080044701812020700A9C02C402892020A5\r\nS315000031F0484D10034402814022620A9E02E00010FC\r\nS3150000320000000000180524348900A24408B086F4A2\r\nS31500003210018D0023400AD00234008900264008911F\r\nS3150000322002C600400000000008042400810020C0FF\r\nS315000032300A1002F4008500A1400B501254108100C0\r\nS3150000324022410A1002C2010000000000B80D62000F\r\nS31500003250880022000C8803E011C80032000E80139B\r\nS315000032603002CA5436000C8003EE03500000000002\r\nS31500003270981DD508F5023F400FD421E400D9003E41\r\nS31500003280404D9043C400F5803F410FD283E606705F\r\nS31500003290000000001801F400DD0013400CD003E428\r\nS315000032A000C10030400F1003C400C94033C02CD009\r\nS315000032B003C60070000000003810E8008A045600BB\r\nS315000032C00C8012E000880022000B800278008881C2\r\nS315000032D02280488002CE0430000000000805C400A9\r\nS315000032E099000260081842C400850429400B500664\r\nS315000032F0D402A90060C0081002C2017000000000DC\r\nS315000033001815A6008B022660089202E4028D802B17\r\nS31500003310604BD802F604A9012240889002C60460D8\r\nS3150000332000000000A015E500D90222408C9403C6D7\r\nS3150000333000C9803A600F9803C700E980B2400C913B\r\nS3150000334003E804700000000028018408F9203E40CC\r\nS31500003350AE9003E480F904B6410F90036410DB904D\r\nS315000033603E420F9003CA0060000000002810A00033\r\nS31500003370C8007E040F8003E000CC0033000CC00BB5\r\nS315000033803102C80932102C82030A04200000000012\r\nS3150000339028053A0A865025800BE202E800820016CC\r\nS315000033A08000A00368000209A18008E8020A004024\r\nS315000033B0000000002805424083C02C380B0482C060\r\nS315000033C0098014200428000040008040248009342D\r\nS315000033D0220A005000000000A001100086082DC03F\r\nS315000033E01B5022D002870025E00878025C00860088\r\nS315000033F025C009788228004000000000A8081E00A9\r\nS31500003400C6802D600F6803D210C58031600C48035A\r\nS315000034105204CC8035E00DF80B2A020000000000B3\r\nS31500003420081D8000FA0036400F8003C0007A003E77\r\nS31500003430804FB00BEC00FA6838C00EB003C20660CD\r\nS31500003440000000000005F200FC8033600FC803D2C4\r\nS3150000345010C69031A00C4803F208CD902DE408C8A0\r\nS315000034600B00007000000000A8119920B60021C4CE\r\nS315000034700B4102D040853021480872021C0087307B\r\nS315000034802D8D2846022A00600000000000009C00E6\r\nS31500003490B40821400B4002F1208F4067D058C40287\r\nS315000034A03040A5092DC00940220000200000000080\r\nS315000034B02014C880B240A0420B0602C0008000243F\r\nS315000034C0000830064C00A3802CD1091802080430ED\r\nS315000034D000000000A815A000F0C022000F8003E144\r\nS315000034E00088C0363008BC032E00EC803CD01DB0EE\r\nS315000034F0832A0460000000008000E800FA003E40D5\r\nS315000035000F9823E000FB803AE00F8C03A28018405E\r\nS315000035103EC04EB003E00030000000000110FA404B\r\nS31500003520FC08B3410FE003D000CD0033400CF0039C\r\nS315000035307E80CD803F8209FA03C04430000000003F\r\nS3150000354081046900BA8222E00B8042E000820020FA\r\nS31500003550800800420110DD192EF22C8402E0401092\r\nS315000035600000000080052000B88022600B8002E089\r\nS31500003570008A00628008B6022D008A002EE03A809A\r\nS3150000358002E000400000000008040800B20120C06C\r\nS315000035900B0002E00289002240088002000092002F\r\nS315000035A02EC00A2002C2050000000000000D6800BF\r\nS315000035B0F80232404B8043E0008B0032C00CB0036F\r\nS315000035C02C00CB003EC00E0003C0015000000000DE\r\nS315000035D0A01DF800F6003F400FC003F000FC003FBE\r\nS315000035E0000FC003D008FF003F000CC003E80470C2\r\nS315000035F000000000C005F820FC0033E00CF00336A4\r\nS3150000360000FF8031A00CF2033C04CFA431C20CEBC6\r\nS3150000361003300070000000008010C910B8D022E00E\r\nS3150000362008B0436A00BB8022A008BC02AC008F50E1\r\nS3150000363037D20DEF02200430000000008805C2A03A\r\nS31500003640BA0422C008B2820408BA00200028340254\r\nS315000036508000832820C84820422301700000000013\r\nS31500003660C015A010BA8022C008B8026F14BB002291\r\nS315000036700008B002A020830026C009A00230046022\r\nS31500003680000000004015E200F8C0B2D88CF0832597\r\nS3150000369000FB40B2800C3003AB10CB0032C00CA84C\r\nS315000036A00310047000000000E001BB00FC003FC0F6\r\nS315000036B00BB003FC101F903FA80FB003E840FB00BF\r\nS315000036C07FC00FE103F80060000000004010A46016\r\nS315000036D0CA08F2D90FB0036500FA403E810CB01358\r\nS315000036E00404CB00B0C00C2003100420000000002E\r\nS315000036F0C8052700830060D80B30022D00B31C2CB0\r\nS315000037009008F10164008F0023C008A00232004037\r\nS3150000371000000000E0054E00805420D10B30024529\r\nS315000037202191C02C882834020010830020C0482034\r\nS31500003730223800500000000020011E408C8021A08D\r\nS315000037400B58021A01B7802DA208781A50408780BC\r\nS3150000375023E05868020800400000000048080800FE\r\nS31500003760C02020C00F30034440F3503C001C3003FF\r\nS315000037700C42C30030C00CA003120200000000007F\r\nS31500003780401DB810F4001FD00FD003FC007F053F8A\r\nS31500003790040FF103FC08FF003FD06FE003D0066082\r\nS315000037A000000000A805E600CA0032C00FE003E0F2\r\nS315000037B000F9003E180FB0036000FB2072C80CA38E\r\nS315000037C0032A00700000000048118C00860421C006\r\nS315000037D00B7002D000B6012D044B72021000B3101C\r\nS315000037E0A1C00D608A12046000000000C0009F00A6\r\nS315000037F0868021E00B6892D201B7802D220B390218\r\nS315000038001E00B7B121E4496A023000200000000022\r\nS315000038104814CE00828820C30B3002C080B3022C2D\r\nS31500003820200B30020D00B30022C00928021204301A\r\nS3150000383000000000E815BA008EA032800FE043FBBE\r\nS3150000384080FE003E800FA00B3800FA0032804D4803\r\nS31500003850033A0460000000004800E202F840BE118E\r\nS315000038608F8823E100F8003E000F8003A020F004BB\r\nS315000038703E000F8103D20030000000000810E50072\r\nS31500003880F10032F00F9003E400F90832F04F18030C\r\nS315000038900400C90032400E8003020430000000001C\r\nS315000038A080046400B90022400B9042E521B1D82281\r\nS315000038B0680B90022400C90022400D9002200010DF\r\nS315000038C00000000018052500BB08A2400B9012E47A\r\nS315000038D004B90022400B910624009900A2400A90E8\r\nS315000038E0020600400000000008040500B10020C0E8\r\nS315000038F08B1402C400B90020400B10024402811848\r\nS31500003900204429930A02010000000000B80D62005D\r\nS31500003910F88032004B8843E000B80032000F828BFB\r\nS3150000392021C0D840301A0E82832E035000000000BA\r\nS31500003930981DF708F5403E400FDC03F400FD00BE7D\r\nS31500003940400F9003B4C0F9203F480F4203E60670CB\r\nS31500003950000000001805F400C50033400C9A03E48B\r\nS3150000396000F9003D404F9002A400F90032400C924D\r\nS315000039708B060070000000003810E000880122006D\r\nS31500003980288502E800B8012E000B80022800B80244\r\nS3150000399034004D84020E0430000000000805CC01FE\r\nS315000039A081006040081002C400B1002C400B1002D8\r\nS315000039B08400B100204008100202017000000000DF\r\nS315000039C01811A4208900E242089002EC00B9402EAA\r\nS315000039D0480B90022480B901264009920206046031\r\nS315000039E000000000A015E440C90830500C9003E523\r\nS315000039F000F9103E404F900BA500F90032410090AF\r\nS31500003A000B2804700000000028018602F1903E4059\r\nS31500003A100F9003EC00FB823E400F3003E400F900F8\r\nS31500003A203E400F100BCA0060000000002810A18065\r\nS31500003A30C84036100F80032111F8803E000C800329\r\nS31500003A40E102C80030002C80030A042000000000B8\r\nS31500003A50280538008E002BB80BA0022900FA202F6B\r\nS31500003A608028A802E8008A0022800DE0020A0040B1\r\nS31500003A700000000028054D00930024D80B30020CEE\r\nS31500003A8020B0802CC0082586CC008B0020C02A30B0\r\nS31500003A90020A005000000000A0011C0097006DC043\r\nS31500003AA00BF8021C11A7042DE0087006DEC0872063\r\nS31500003AB021C009720228004000000000A8083E024A\r\nS31500003AC0D78035E00F78031E00B7803DE00C680311\r\nS31500003AD0CE08C3C0B1E80EFC0B2A020000000000AD\r\nS31500003AE0081DAC00EB003A800F310BECB4FB6C3ECA\r\nS31500003AF0C00FB403EC00FB683EC20FB6C3C206603B\r\nS31500003B00000000000005FA00B7A431240CF803DE1B\r\nS31500003B1040CC9233E00FEC213E00FF8033E30CF8FB\r\nS31500003B204300007000000000A8119000B72021801B\r\nS31500003B30087202DC40D61829C80B61035C00B70086\r\nS31500003B4021C00D71022A04600000000000009C40A4\r\nS31500003B50B73121C00A7012FC01870221C01B400246\r\nS31500003B605C00B70021C408300200002000000000FD\r\nS31500003B702014CC00B300E09008B802CC2892C028EC\r\nS31500003B80C00B00066C00B30020C0093002080430E8\r\nS31500003B9000000000A815A400F140B2800EF182EFEB\r\nS31500003BA000C80030410F800B7C00FF00B3C008FA4C\r\nS31500003BB00B2A0460000000008000EF00FB403E92EC\r\nS31500003BC00FB013EE00F9203ED00F9403EC00FB0477\r\nS31500003BD03EC00FB003E00030000000000110F3000B\r\nS31500003BE0FD2AB3610CF0033C01CF001FC00C00039B\r\nS31500003BF03C00CB0032C00CF00B004430000000004B\r\nS31500003C0081046E04BA80200208B0020C10A9702E3E\r\nS31500003C10B00A9C82AC00AB002AC00FB00220401054\r\nS31500003C200000000080052100B940260909B0022CD9\r\nS31500003C300088002E7008B1222C00830020C00830B6\r\nS31500003C40422000400000000008040000BB00A480E1\r\nS31500003C500930022810A3002EC00A30068C00A300EB\r\nS31500003C6028C02B300A02010000000000000D600091\r\nS31500003C70F900B6404DB00B2C008B043EC00C9003EF\r\nS31500003C802C00CF0033C00CF00300035000000000EE\r\nS31500003C90A01DFC00FE003B000CF003FC00F7003FFB\r\nS31500003CA0800FD003FC00FF003FC00FF003E8067052\r\nS31500003CB000000000C005FE00CC8233A00EC803B68B\r\nS31500003CC000F7803FE00FF803FA00CC403FA008D889\r\nS31500003CD00370007000000000C010C800880120A01A\r\nS31500003CE08898022E00BB802EE00BB802EA00A900DD\r\nS31500003CF02EE108900220043000000000C805ECA068\r\nS31500003D00802822802010068600B3802CE00B380223\r\nS31500003D10C80082202CC008800262017000000000EA\r\nS31500003D20C015AB00A88A208008800A2C00BB002E94\r\nS31500003D30C00BB002EA00AA226E4408B20230046048\r\nS31500003D40000000004015E600C980B2800C8043A642\r\nS31500003D5000F9003E40079003EC00C8403EF08C1886\r\nS31500003D600350047000000000E001B010DD003F8049\r\nS31500003D702DD003FC40FD003F400FD003FC00FA02AB\r\nS31500003D803F600FD003F80060000000004410A5005B\r\nS31500003D90EB003EA02C91032400F92032480F920339\r\nS31500003DA0EC00F870B2D00F80031004200000000071\r\nS31500003DB0D80507000B412EA08805022F50B94022D6\r\nS31500003DC0400B9602CE00BA4020600BB7023200408C\r\nS31500003DD000000000E00540402A812C88200802CB24\r\nS31500003DE000B24020B00B2402C040B04004C50B30E6\r\nS31500003DF00238005000000000A001130086C22FA068\r\nS31500003E0088580AD220BE8021A04B6802D200B78013\r\nS31500003E1025600B5802080040000000004808080012\r\nS31500003E20E0193C802C1203C800F200B0820722037E\r\nS31500003E30C000F15034D00FA00B12020000000000A9\r\nS31500003E40401DB845FC103F804F40033040FE103FF8\r\nS31500003E50840FE013F200FF063B440FF403D0066024\r\nS31500003E6000000000A805E000FB003E804F0009AA04\r\nS31500003E7000C08032000C80132410F9003EE00CB420\r\nS31500003E8003EA007000000000C8119000B7042D80FE\r\nS31500003E900B500A1000840021000840021404B700E9\r\nS31500003EA02D40485002D204600000000080009600B9\r\nS31500003EB0B7C02DA00B5806BA009C80232009C80263\r\nS31500003EC01608B5C02FE2186902F0002000000000B5\r\nS31500003ED04814C544B2002C800B000A00009400214F\r\nS31500003EE0000940021410B3802C70483042D20430CE\r\nS31500003EF000000000E815B800F6C03E800F2003A8B9\r\nS31500003F0002DA00B0802D200B2800FE002F802CA0A6\r\nS31500003F1003FB0460000000004800E000F8083E00D3\r\nS31500003F200FC403F100E8003E100E8403E204F80813\r\nS31500003F303E000F8003D20030000000000810E42885\r\nS31500003F40F90636400F9C136600F9003E44089903B3\r\nS31500003F502400F90036620F9003C20430000000000E\r\nS31500003F6080046780B9C022520B988A2740B9002E78\r\nS31500003F70600896022410B94022400BB042E00010BF\r\nS31500003F800000000018052600B98826400B90027430\r\nS31500003F9000BD002F401AD0023600B14026440B90D7\r\nS31500003FA002C600400000000008040500B940204099\r\nS31500003FB00B50021C09B5002F40BAD00A1608B128CA\r\nS31500003FC020400B1002C2010000000000B80D600086\r\nS31500003FD0F80036000F80036000F8003E800E802354\r\nS31500003FE03000F82036010F8003EE03500000000079\r\nS31500003FF0981DF604FD803E400F9003C400F9003C76\r\nS31500004000400D1003E400FD283D400F9083E6067046\r\nS31500004010000000001805E400FD003E400C5003249B\r\nS3150000402000CF0032C00FB003F404F9023F408F9472\r\nS3150000403002C60070000000003810E800B8002C002E\r\nS3150000404028A0022000880022010B8002F000B8019F\r\nS315000040502E000B8802CE0430000000004805C40183\r\nS31500004060B1802F410A504A3400850021401B50027E\r\nS31500004070D400B1016C408B1202C201700000000036\r\nS315000040801815A400B9006D402A9002340089002357\r\nS31500004090400BD002E400B9006E440B9002C60460E7\r\nS315000040A000000000A015E600F9003E400E90032433\r\nS315000040B002C900B2400F9003E400F9603E584F94E5\r\nS315000040C083E80470000000006801AC40F9903E40AF\r\nS315000040D00D9003E400F9003E400F9043E400FB24FA\r\nS315000040E03E600F9203CA0060000000002810A04046\r\nS315000040F0F8103F000EC40B3000FC003F000FC00359\r\nS31500004100E000F80832148F8C030A04200000000037\r\nS3150000411028052900BE422E800828020800B2022E79\r\nS31500004120800BA002E810BA0022A10BA0020A0040F0\r\nS315000041300000000028054620B3A12C1822680211B1\r\nS3150000414080B0602D380B4802C200B04024400B18E6\r\nS31500004150020A005000000000A0011C00B5062F80D6\r\nS3150000416008C0921000B5002D020B4082D100B78026\r\nS3150000417025C00B7C0228004000000000A8081200A1\r\nS31500004180F5803D604E48031200F4803D200F481331\r\nS31500004190DE00F08035E00FD80B2A02000000000098\r\nS315000041A0081DA830F8023EC00F9003EC08F9003E47\r\nS315000041B0C00FB003EC00FB22BAC00FFC43C206607E\r\nS315000041C0000000000005FE40FE8431600E49033603\r\nS315000041D000C59033E00CE8033200ECC03DE50CCCA2\r\nS315000041E003C0007000000000A8119C00BC4421C858\r\nS315000041F00843021400840021C008640210048710DA\r\nS315000042002DC40A7012EA0460000000000000941138\r\nS31500004210B710234048C00634009D0063C008E00282\r\nS315000042203C0084002F44184002C00020000000001B\r\nS315000042302014C910B00200C000148A4A0090000081\r\nS3150000424000481002040083202CE00A3E02C8043015\r\nS3150000425000000000A815A500F252B24004942308FD\r\nS3150000426020D80030001C10032002EA402CC24CF07B\r\nS3150000427082EA0460000000008000ED00F8003ED0F5\r\nS315000042800F9003A880E9003E000F9403E000FB10A6\r\nS315000042903E420FA403E00030000000000110FC20A5\r\nS315000042A0FD0137404CDC033B00CC0033000CD0034F\r\nS315000042B03C00CFA03FF00CF802C0443000000000E4\r\nS315000042C080046E30B88222D82A0E02240081002291\r\nS315000042D0C008A4020C008BA02EE188AB02E04010BF\r\nS315000042E00000000080052C40A98124400890022C83\r\nS315000042F00089002AC008B00220008B000EC008808A\r\nS3150000430022E000400000000008040C08B90022C0AA\r\nS315000043102A90022C0188002AC008B00220008300DF\r\nS315000043202EC0080002C2010000000000000D6C0053\r\nS31500004330E90036402C90032C00C9003AC00CB003AB\r\nS315000043402C00CB047EC00C8027C003500000000068\r\nS31500004350A01DFC10FC003FC00FC003D000FC0035C0\r\nS31500004360000F40035400FF003F414FC003E80670B2\r\nS3150000437000000000C005F080F78033A00FD803725C\r\nS3150000438000CC8033810CE0033000CC0033500C6845\r\nS3150000439003300070000000008010A100BB8022A046\r\nS315000043A00BA00220082800228008A0022201888093\r\nS315000043B022480AB803600430000000008804CB20BD\r\nS315000043C0B10220000BB01244000002A08048204237\r\nS315000043D00400820020400830022201700000000024\r\nS315000043E0C011A840B90322028B80120012A810A2A5\r\nS315000043F08008201224008A0820428AB08270046055\r\nS31500004400000000000015E000F3E0B2B10F00036108\r\nS3150000441020C80133810CB0032200884032540CB40A\r\nS315000044200B00047000000000E001A200FFA83FA4FA\r\nS315000044300FF003F000FC803D806FF00BE040F400CD\r\nS31500004440BE600FF003B80060000000004010AC0032\r\nS31500004450CB4032100FA013A002F84036800CB003F8\r\nS315000044602402CA403E500CB5031004200000000090\r\nS31500004470C8052C048B0036008B90222080D80023A0\r\nS315000044808008B00204008A002E40083402B20040C0\r\nS3150000449000000000E0014400828020C48B100284EA\r\nS315000044A000BBE12080882006098181022C80683AC1\r\nS315000044B0463800500000000020011E088F98652035\r\nS315000044C00BE8021242BE9821A008280218488580EF\r\nS315000044D02DA4087802880040000000004808004229\r\nS315000044E0C21030C40F3003A402F150B6800C200B6A\r\nS315000044F00C44C3007C840C3203120200000000004E\r\nS31500004500401DB800FF142F040F4013F002D4513F92\r\nS31500004510802FE021FC80EF103FA40FF003D006604F\r\nS3150000452000000000A805E400F38432C00F8023A435\r\nS3150000453000E80336818FB0132A08C98032800C3216\r\nS31500004540032A00700000000048111C00B704211463\r\nS315000045500B700210408E0021800B30101812810261\r\nS31500004560208008710352046000000000C00096001D\r\nS31500004570BF8021E80BE8029204A488A1A04B7840F2\r\nS315000045804E04878061A008F8023000200000000079\r\nS315000045904814CD00B3C820000B141201068AA020CF\r\nS315000045A0800BB4224C00830020800836025204306F\r\nS315000045B000000000E815B800FE00B2800FE402A873\r\nS315000045C040AA8033800FA02368008A00B3802C2481\r\nS315000045D0433A0460000000004800E020F8103E0066\r\nS315000045E00F8483E000F8403A000F80ABA000F84447\r\nS315000045F03F000F8403D20030000000000810E400E2\r\nS31500004600F9803E500F900B2C00DBC2B2400C9A0191\r\nS315000046102600F90036400CB00B0204300000000002\r\nS3150000462080046400B9F22EE00B960A250089C020AA\r\nS3150000463040089C022440E9602E408A98022000101F\r\nS315000046400000000018052400B9002E404B1002049B\r\nS3150000465020990022400A9406B500BD10294108920F\r\nS31500004660820600400000000008040500B1002C404E\r\nS315000046700B140A05000140224D0A14021400A5017C\r\nS315000046800D44CA100202010000000000B80D6200CD\r\nS31500004690F8003E004B800B0008DA00322A2E800B11\r\nS315000046A0A004F80013100C80032E03700000000015\r\nS315000046B0981DFF04FD023E400F5803E608F9803FAF\r\nS315000046C0480D9E036501F9403E584F9003E606707B\r\nS315000046D0000000001801E400F10030400F9403E5EB\r\nS315000046E000E9003A780CD0033400C90032408D50FE\r\nS315000046F003C60070000000003810E000B800B600E5\r\nS315000047000B8A02020284A0AA3808800A28108800B0\r\nS3150000471028000A8002CE0430000000000805C4000C\r\nS31500004720B90020400BD212D40025082044081002FC\r\nS315000047304C0091002040093002C2017000000000C8\r\nS315000047401815A400B90026600B900234008D002ACB\r\nS3150000475040281002640099002A408A9442C60460E8\r\nS3150000476000000000A014A740F90032400F9803E5AE\r\nS3150000477082E9903A400C90016500D18132402D903B\r\nS3150000478003E80430000000002800A400FB907A40F3\r\nS315000047900F9203E400F9803C400F9003A420EB2025\r\nS315000047A03E404F9003CA0020000000002810210060\r\nS315000047B0F80032004C800B2100CC0032010C820341\r\nS315000047C00102C8003E000C8C0B0A04200000000009\r\nS315000047D028042800B200A2800A280228068E00B605\r\nS315000047E08008E40238008AC02F8008E00A0A000028\r\nS315000047F00000000028040C00B34820009A300A2C60\r\nS31500004800008A0020C0CA3042890080302E800830DD\r\nS31500004810020A00500000000020011C40B5002320C1\r\nS315000048200A70821400A600A7C00A70021E00A40027\r\nS315000048300D800878120800400000000028081E803D\r\nS31500004840F59031200EE8031A00C58011E02E000312\r\nS315000048508C00C5813DA42C58030202000000000014\r\nS31500004860081DAC00F9413E1087A003E000D9003CCA\r\nS31500004870C0098001EC00D9403E880FB003C2066033\r\nS31500004880000000004005FE00CF8033310FD9031E23\r\nS3150000489000CE8033E04CF8233E00FCC03FA20C68FB\r\nS315000048A00350047000000000A801BC008540210AE6\r\nS315000048B00BD3821480460129C028F0071C00B400DF\r\nS315000048C02F800F7102AA06600000000000009C0005\r\nS315000048D0850025004B40123810158025C00940027E\r\nS315000048E01C00B6002D900870020000200000000099\r\nS315000048F06014CC008160A4300B8402001089C02EA5\r\nS31500004900C009800A0C00B2002E800B308290003065\r\nS3150000491000000000A815BC00C94036100FB9032DD1\r\nS31500004920019AE027C00D90022400FA003F900C3453\r\nS3150000493003220060000000008000CE00F9003A80EB\r\nS315000049400FB003E401FA003AC02E90038400FA4047\r\nS315000049503EA00FB013E00030000000000110FC0084\r\nS31500004960CDA033220FE0033820CD0832C00CE80B6F\r\nS315000049703C00C70033800CF003004030000000000C\r\nS3150000498081046C0881C222000BE00230028D0037E0\r\nS31500004990C008A4932E00DB00368088B002284010A1\r\nS315000049A00000000080052C00890022080B90020CF4\r\nS315000049B0018A0022C00882126E108919628008B826\r\nS315000049C0022000500000000008040C0409042080A6\r\nS315000049D01B10020401820064C01800020E00910040\r\nS315000049E024802838020B00000000000000042C0080\r\nS315000049F0C900A2004B800A2800C10032C008B003DB\r\nS31500004A002C04CB00B3800CB00B0002100000000099\r\nS31500004A10A019FC00F4023F000BC003F000FD003FAC\r\nS31500004A20C02FF002FC087F003B808FF003E907707F\r\nS31500004A3000000000C005F200FD2433E00C78033EC0\r\nS31500004A4000FF803FE00FF803FA00DC8037A00FDCA0\r\nS31500004A5007300070000000008010E210B16020E016\r\nS31500004A6088B8022E00BB802EE00BB802EA08BB080D\r\nS31500004A70A0C00B9002200430000000008805CC0482\r\nS31500004A80B01CA2E108B8020C00B3802CC00B3002A7\r\nS31500004A90CC00B32024C00B32166201700000000067\r\nS31500004AA0C015A800B28820C008B0022E00BB002E98\r\nS31500004AB0E00BB802EC00BB0422C04BB010700460DF\r\nS31500004AC0000000004015E240F98132C02C900B280E\r\nS31500004AD000F9003E800FA003E000DB5036F08F8027\r\nS31500004AE00050047000000000E001B000FD003FC06F\r\nS31500004AF02FD003F810FD003F800FE083F000FD8209\r\nS31500004B003FD00BE003B80060000000004010AC008E\r\nS31500004B10FB2036E00E900B2800F9083E840FA00318\r\nS31500004B20E400FA4032C00C9203D0042000000000DA\r\nS31500004B30C8052800BAC222F10814022A00B9402E7C\r\nS31500004B40800BAC02E420BB0022F008B482F20040E5\r\nS31500004B5000000000E0054000B11024984A208206BB\r\nS31500004B6080B2402C420B1C02CA00BB0020E608980B\r\nS31500004B7002F800500000000020011200B58023A0BA\r\nS31500004B8028E8021601B6802D600B5882DA00B6803E\r\nS31500004B9021E0085802C80040000000004808040050\r\nS31500004BA0F20034800E20030420F2003C400F100374\r\nS31500004BB0CC00F100B0C02C3003D20200000000008F\r\nS31500004BC0401DB000FF003F840FE003F440FE103F9D\r\nS31500004BD0440FD103FE00F7007F400FF403D00660B8\r\nS31500004BE000000000A805E000F10036800F8001C239\r\nS31500004BF000C08032000880030200C30032D20F8258\r\nS31500004C00032A007000000000481191C0B500218001\r\nS31500004C10034012D000840021010840021004A701BD\r\nS31500004C2021C10B620352046000000000C040969050\r\nS31500004C30BFC025A00B4802F2008C80232009C802C1\r\nS31500004C4016008F8021E00BD14630002000000000C6\r\nS31500004C504814C010B30020800B0006C0008000205E\r\nS31500004C60000900020410B01120C00B3202120430F9\r\nS31500004C7000000000E815A800F60236810FA003E840\r\nS31500004C8002CA00B0802D200B2800C69030A00FAEBF\r\nS31500004C90063A0460000000004800E000F8483E00C4\r\nS31500004CA00F8003E200F8003E304E8803F000E80073\r\nS31500004CB0BE340F8003D20030000000000810E4006C\r\nS31500004CC0F9803A410F9003E600F9007E440C920306\r\nS31500004CD02600F90032E00C9003C204300000000008\r\nS31500004CE080046C00B95022420B9006E640B9002EB3\r\nS31500004CF0700894022400B90036542ABC03E0001060\r\nS31500004D000000000018052580B9002A400BD002F4E7\r\nS31500004D1020BD002F4008D0023440BB0022C00896B8\r\nS31500004D2002C600400000000008040408BB40204002\r\nS31500004D300B5042D400B5002FC028F00A1405B10468\r\nS31500004D402640081402C2010000000000B80D6000F1\r\nS31500004D50F8803A000FA002E000F8002E000C800355\r\nS31500004D603000F80032808C8003EE03500000000013\r\nS31500004D70981DEC00FFC43E400F9003E400F9003C90\r\nS31500004D80400F1003E400FD283E4A0F1803A70670E3\r\nS31500004D90000000001801F400F9023A400CB003C408\r\nS31500004DA004FB0022400F9003FC00FD0033400391FA\r\nS31500004DB003C60070000000003810E000B804600070\r\nS31500004DC0488042E000B80022000B8002F800B800DC\r\nS31500004DD022800B8A02CE0430000000000805C400C1\r\nS31500004DE0B1012B40185002D4083D0021400B50025F\r\nS31500004DF0D400B10020400B1002C201700000000078\r\nS31500004E001815A404B9002140089002F400B9002343\r\nS31500004E10400BD002E400B90222400BB002C6046087\r\nS31500004E2000000000A015E400F9C02A402C9003E41D\r\nS31500004E3000F100B2400F9003E400F160B2500F9908\r\nS31500004E4083E00470000000002801A500F390BE4036\r\nS31500004E500F9023E400F9003E400F9003E428F92464\r\nS31500004E601E44059803CA0060000000002810A080B8\r\nS31500004E70C8813B0004C013F002EC003F000FC08362\r\nS31500004E80A140F84032100C84230A042000000000E0\r\nS31500004E9028052B00AA83228428A002E8008A003A6B\r\nS31500004EA0800BA412E800BE0023A028A0020A00403E\r\nS31500004EB0000000002805430082802800596642D180\r\nS31500004EC08082602D380B4C024000B20020C8183199\r\nS31500004ED00A0A005000000000A0011300AC40238025\r\nS31500004EE0096012F200870029020B4080D808B62418\r\nS31500004EF021F118580228004000000000A8081600FA\r\nS31500004F00C68A39600D6803D200C6803D200F48036B\r\nS31500004F101A00FEA0B3A00CF8072A02000000000049\r\nS31500004F20081D8424F2603EC02EB003EC00DB003E78\r\nS31500004F30C00FB002E000FA907E804FEC03C206601C\r\nS31500004F40000000000005F202C7B023640DF823F646\r\nS31500004F5000FF803FE00FF803FE00FE8473688FFCBD\r\nS31500004F6043C0007000000000A8119000851821CCF5\r\nS31500004F70087002D400B6002DC00B7002DC00B61318\r\nS31500004F8021420B7202EA0460000000000000B0003B\r\nS31500004F908F20A740897002D400B7002DC00B700285\r\nS31500004FA0D420BE0021090B7002C0002000000000C2\r\nS31500004FB02014C084834024C0082002C800B2042CF8\r\nS31500004FC0000B0002C400B2C020404B2902C80430C6\r\nS31500004FD000000000A815A000C9C036402DA003E8B7\r\nS31500004FE000BA003E000F8002E800FE1832F00BE027\r\nS31500004FF003EA0460000000008000E000F8003AD0F8\r\nS315000050000FA003E800FB013E000F8003E880FA00D2\r\nS315000050103EC80F8003E00030000000000110F08061\r\nS31500005020FD993B400CE003F880FE003F000FC003F3\r\nS31500005030F200CE003FA80FF003C04430000000008D\r\nS3150000504081046084BBE022D848B002E610FB002E43\r\nS31500005050C00BB002C2408A002E200EE002E04010D3\r\nS315000050600000000080012800B302284048B042EC4E\r\nS3150000507000BB002EC00BB002EC008A002E500BA025\r\nS3150000508022E000400000000008040804B00062C0EE\r\nS31500005090083002CC00A2002CC00B3002EC008200CB\r\nS315000050A02C000B2002C2010000000000000D600071\r\nS315000050B0FB0138402CB023EC05BB023EC00FB00309\r\nS315000050C0E402CA003E800FB003C003500000000097\r\nS315000050D0A01DD004FF00BFC00FE003F000FE003F9C\r\nS315000050E0000FC003F400F6003F004EE003E8027034\r\nS315000050F000000000C005FC80CF8033A00FC8031657\r\nS3150000510000CC0033A00CF8037600EF0033C80DF096\r\nS3150000511003F00070000000008010EF408B2402A016\r\nS315000051200B98122C008A80226008B822A2008B00FD\r\nS3150000513023CA08BC02E00430000000008805CC0049\r\nS31500005140820820004B000224008200208048304262\r\nS315000051506C00A00024CC093402A2017000000000FB\r\nS31500005160C015AC008B80A2200B900220008A002282\r\nS31500005170E008B022AA00884026C008B000F004600B\r\nS31500005180000000004015EC00CB8032300F1B0326D8\r\nS3150000519080CC8032B80CB0034700EAC036C00DB0F0\r\nS315000051A003D0047000000000E001BC02FE003FC016\r\nS315000051B00FD003F040FAA03FC00FF243F000F21008\r\nS315000051C0BAC02FF003F80060000000004010AE00E7\r\nS315000051D0FA0036000CB003E500EB00B2800FBC030A\r\nS315000051E0ED20F80430C02EB003D0042000000000EB\r\nS315000051F0C8051D00B3482290089002C10083822092\r\nS31500005200C80B20022300B82023C008FC02F200408D\r\nS3150000521000000000E0054C80B3802488281902C2F3\r\nS3150000522080A28020A00B1002C740B00020C02A3AFE\r\nS3150000523022F800500000000020011E00BFD021E02F\r\nS31500005240085A12DA0186C021B40B79021200B48121\r\nS3150000525021E0087802C800400000000048080C0061\r\nS31500005260F20034C20C3003C0B0E218B0840F34032D\r\nS31500005270CD80F300B0C82E3083D2020000000000BB\r\nS31500005280401DBC00F7003DC40FD253F802FE103F8C\r\nS31500005290840F7043F800FF003FC08FF003D0066014\r\nS315000052A000000000A805EC00FB003A000F184320A0\r\nS315000052B0A0CE003EE00CB6432600D90072C80CB062\r\nS315000052C0032A00700000000048119C00B40021C0B1\r\nS315000052D00B5002100086002D8008708290008D0011\r\nS315000052E0B0D408700212046000000000C0009E41A5\r\nS315000052F0B6C029600BF886120497802DF0096C025F\r\nS315000053001E00978021E089794A30002000000000C5\r\nS315000053104814CC00B18020E00B18460A4093402C7C\r\nS31500005320B8093C028C608B4122C00930021204305D\r\nS3150000533000000000E815A800FEC03BB80FE40B29EA\r\nS3150000534006DE403FA02D2C073B00DE0032802DA05C\r\nS31500005350033A0460000000004800E000F8403E12F6\r\nS315000053600F8203E182E8243E010E8087E100F808FF\r\nS315000053703A000E8003D20030000000000810E480DE\r\nS31500005380F90836404F9003EC0009A13E400FBA03DE\r\nS31500005390A700F9A032402C1A0302043000000000D6\r\nS315000053A080046400B10122600B9052C50089A02ED2\r\nS315000053B0600B94422400B9812240089C0220001010\r\nS315000053C00000000018052400B92026C40B9802A48A\r\nS315000053D000A9042E605B9082A400B90022400894C4\r\nS315000053E0020601000000000008040400B940244041\r\nS315000053F00B1842C500A1002C401B101A0C00B10965\r\nS31500005400A05088100202010000000000B80D6200E2\r\nS31500005410FA0036800F8003A808E8803E000F80025D\r\nS31500005420A000F880B2202C828B2E025000000000D3\r\nS31500005430981DE500F586BB400FD003CE029D403D8A\r\nS31500005440400F1013D400FD893E700F1003E606705E\r\nS31500005450000000001805F4007D0035400C1013F420\r\nS3150000546010CDA03D400CD0030400FD4032402D90ED\r\nS3150000547003060070000000003810E000BA002200A9\r\nS31500005480088012E00088042E00088002A800B88078\r\nS31500005490200008800A0E0430000000000805C40041\r\nS315000054A0B1002640081012C40081402C400810228A\r\nS315000054B00400B10020400910020201700000000043\r\nS315000054C01815A400BB00224828B042E40889002E23\r\nS315000054D044089102A604B9412040089002060460DF\r\nS315000054E000000000A015E400F90036520C9023C518\r\nS315000054F000C9203C402C90C32400F980B2400D9096\r\nS3150000550003280470000000002801A420F9003E4092\r\nS315000055100FB203E70AF9A03E420F9003EC00F12018\r\nS315000055203E408F3003CA0060000000002810A00033\r\nS31500005530F82132108C81032000E8013E002C8603FE\r\nS31500005540A000E80132012C8203CA042000000000FA\r\nS3150000555028053A00B60921800AA80238408E502F45\r\nS31500005560A208644368608A04228008AC02CA00402C\r\nS315000055700000000028054E40B2C020400826020C5C\r\nS315000055800083802CC008301A8800A18020C008083B\r\nS3150000559002CA005000000000A0011C00B60023C093\r\nS315000055A00AC8021C0185402D800870225A008740D7\r\nS315000055B021C8085082E8004000000000A8081E002C\r\nS315000055C0F78021E00C58133E02C7803D600C48036B\r\nS315000055D09A20E380B1E90C7883EA0200000000001B\r\nS315000055E0081DAC04F200BEC00FB61BEC00F8003E6E\r\nS315000055F0800F2003E980FB003ED40FB003C2066093\r\nS31500005600000000000005FE00C6803F604FFC033E20\r\nS3150000561090F79033200F62033A00D78033F00DE8FD\r\nS315000056200300007000000000A8119800862001C841\r\nS315000056300B50021C00B60409008B600298008720FC\r\nS3150000564037C0087403EA04600000000000009C00F4\r\nS3150000565086012DC28BD1025C84BF0221000BC102E0\r\nS315000056601800970421C40960020000200000000011\r\nS315000056702014C808829020F20B38824C08B2902081\r\nS31500005680281B2A028940830026C0082002C804304D\r\nS3150000569000000000A815A400CA403E600FB2036CCB\r\nS315000056A004FA00B2980F26032A00DD0033C02D80CD\r\nS315000056B0032A0460000000008000E400FA003ED0E7\r\nS315000056C00F940BA548F8403E800FA403E800F300B2\r\nS315000056D03EC00F9003E00030000000000110E4011E\r\nS315000056E0FC08B3C04CEA13FE280F003F000FE0038E\r\nS315000056F0B820EF00B3C00C9043C044300000000057\r\nS3150000570081046601B8C4208208A402C12088A026AC\r\nS31500005710A04EAC0208648F0022C008B502E040101B\r\nS315000057200000000080052E04B280224028B002E866\r\nS3150000573080A9842EB00BA882E800AB0022C008A086\r\nS3150000574002E000400000000008040804B00028C081\r\nS31500005750081042C002A0002C800A200248008300E4\r\nS3150000576020C0083002C2010000000000000D6C00DD\r\nS31500005770B800B2C00C9003E810EB003E000FA00B7F\r\nS31500005780E800EB0133C02C9003C00350000000007A\r\nS31500005790A01DF000FC00B780057003F008DE00379E\r\nS315000057A0810EE0439400FF003FC00FF003E806704F\r\nS315000057B000000000C005F200FE8031200FC8033053\r\nS315000057C002CD003FC80DD803D200DC80F92088C87E\r\nS315000057D003300070000000008010E608EA8022E036\r\nS315000057E00B82822F0081542AC028B0222C04BB01D0\r\nS315000057F022C10D8002200430000000008805C0147C\r\nS31500005800B20000200B20020C40890024D008300290\r\nS315000058104C00BB0022C018000622017000000000E8\r\nS31500005820C015A440BA0822E00B88822E008B4028BF\r\nS31500005830C0083002AC003A8022E0098000300460E3\r\nS31500005840000000004015E300F88032A00F9C0A23F8\r\nS3150000585000C80036B20CB9036C00F30120F308A8A7\r\nS315000058600B10047000000000E001B408EDC03FC05A\r\nS315000058700FF003E400FCA03ED00FF0237A40FF00B7\r\nS3150000588027800FEC03F80060000000004010A0081D\r\nS31500005890FA4432C00EB003E700E84036C02CB0032D\r\nS315000058A0A400DB613EC20D8003D00420000000008E\r\nS315000058B0C805240CB20022E808B902C608820123F2\r\nS315000058C0C048B0022E808B083EC20D8902F200400D\r\nS315000058D000000000E0054980B000200208BC02C4B8\r\nS315000058E000A30020401837028D80A3C40CD008887E\r\nS315000058F002F800500000000020011200BD90232491\r\nS315000059002978A2DE02879021601878023600A780E7\r\nS315000059102FE0094886C8004000000000480808003B\r\nS31500005920F208B0840C3002CC00A100B0400CB003E9\r\nS315000059308800F3003C800C0103D202000000000046\r\nS31500005940401DB000F6003FC40EF003FC00FF003B14\r\nS31500005950540FF103FC02DF003BC00FC003D006600A\r\nS3150000596000000000A805E8C0F880320004B003E497\r\nS31500005970007B0036500DB003EC01CA0036C00BA008\r\nS3150000598003EA00700000000048119040B5002100B5\r\nS31500005990087002DC00B7002168087002DC0287008C\r\nS315000059A061C10B6002D2046000000000C0009A8052\r\nS315000059B0B68027F0087802DE00B5802564097802F3\r\nS315000059C0DE00AF8621E00B6802F000200000000038\r\nS315000059D04814C004B270A4F008B802CE00BB40223E\r\nS315000059E05809B802C060A281A0B40B2802D20430C4\r\nS315000059F000000000E815A804FEC435A42CE483FAD0\r\nS31500005A0080FE4036800DA883DA00EE8437948BEA58\r\nS31500005A1003FA0460000000004800E008F8003A00BD\r\nS31500005A200F84A3E000F8203E000E8003E00058300B\r\nS31500005A303E000F8003D20030000000000810E40092\r\nS31500005A40C9403E400C90034600C9A032E84C9A0378\r\nS31500005A502400C98032400C9203C2043000000000CA\r\nS31500005A6080044C0A89802E40089E022440D9802258\r\nS31500005A70620890022760818020504E9002E000105C\r\nS31500005A800000000018012C0089016E600898026C65\r\nS31500005A9000890822401890062C028B10A25008900C\r\nS31500005AA002C60040000000000804040883016C40A0\r\nS31500005AB028140204008160205A08140A250089402F\r\nS31500005AC022500B3002C2010000000000B80D600039\r\nS31500005AD0C8003E014C800362028080B0082C80031F\r\nS31500005AE00000C80032000C8003EE035000000000E6\r\nS31500005AF0981DE400F5013D400FD803F500FD913EE9\r\nS31500005B00600FD803F600F5803F600ED283E606707C\r\nS31500005B10000000001805E400FD0003400FD003F468\r\nS31500005B2000F90432400C90036404C90230400CD0E2\r\nS31500005B3003060070000000003810E000B800A20064\r\nS31500005B400B8002E000B800A0000880020000880078\r\nS31500005B5063012880020E0430000000000805C4001E\r\nS31500005B60B90060401B1002C400B500214008504235\r\nS31500005B705402A50021400810020201700000000036\r\nS31500005B801815A400B90822D80B9002E500B9102315\r\nS31500005B90420850021400A72021448890020604609F\r\nS31500005BA000000000A015E400F14032600F9803E405\r\nS31500005BB040F90032400C980364C0E94822520818A4\r\nS31500005BC00B280470000000002801A400F9203E40C4\r\nS31500005BD00F9903E400F1003C402F9103E604D980BD\r\nS31500005BE0BE600F9C03CA0060000000002810A000E1\r\nS31500005BF0F80C3E318F8803E000C8103A100EC083BF\r\nS31500005C00B010EC2033041881C3CA04200000000041\r\nS31500005C1028053840BE812F820BE022E8008A8022C8\r\nS31500005C209008A0022A008AC0A3A01AE802CA00406F\r\nS31500005C300000000028054000B2402CE00B2002CEF8\r\nS31500005C4000830028C80A3C028E00230020C00920D9\r\nS31500005C5002CA005000000000A0011000B4402D80D0\r\nS31500005C600B4002C700870021C008408210208440F4\r\nS31500005C7023000A7002E8004000000000A808120095\r\nS31500005C80F4843DE00F4803D602CF8039E00EF803D6\r\nS31500005C909E00EF8071E00D7843EA020000000000EC\r\nS31500005CA0081DA020FA003E814F8003E400FB003E61\r\nS31500005CB0C00F8003E000F8007E000FB003C206604C\r\nS31500005CC0000000000005F600FE803FE00FF903FE2D\r\nS31500005CD000CF8037E00DF8033E00C7A073E08CF9D3\r\nS31500005CE00300007000000000A8119004B4422D8447\r\nS31500005CF00B5082DC00DF0023C40840023000842001\r\nS31500005D006308087102AA0460000000000000940005\r\nS31500005D10B4102DD20B5002D4008500258009D00284\r\nS31500005D2094008D3469E068F00280002000000000D5\r\nS31500005D302014C180B2402C200B1802C5008180209F\r\nS31500005D40800828122904828820100810028804304E\r\nS31500005D5000000000A815A320FB403C400F8803ED7F\r\nS31500005D60828B2034D005BA02AC92CB22BAF0001056\r\nS31500005D7003AA0460000000008000E104F9403E919F\r\nS31500005D800F9003E408FB403EC80F800BE100F84289\r\nS31500005D902E0D0F9001E00030000000000110F00011\r\nS31500005DA0CD9833410CD003E420F60033400CF003C9\r\nS31500005DB03820EF003384CFD02300443000000000A9\r\nS31500005DC08104418A83C022B02A9802E400BA0022E4\r\nS31500005DD0600D800225008040A2400B9002A040107A\r\nS31500005DE0000000008005200089002260088882ECFF\r\nS31500005DF000BB0822C40820822C20AA0022420B984D\r\nS31500005E00822000400000000008042000890020C015\r\nS31500005E10081002CC009300A2C009100A00008900F5\r\nS31500005E2020800B900282010000000000000D60003F\r\nS31500005E308800B2400C9003E400F80032000C8007A2\r\nS31500005E402008E80032000FB00300035000000000F5\r\nS31500005E50A01DF000FC003F400FD023F4007C003F63\r\nS31500005E6000057003FC007F023FC00F5003E8067078\r\nS31500005E7000000000C005FC88FF0035200CE80BF68A\r\nS31500005E8000DC0033200D78031200C4813F208CC84B\r\nS31500005E9003300070000000008010EC60BFC02221BB\r\nS31500005EA00032CA242889942A2008B843A610A8805C\r\nS31500005EB02E600A8802A00430000000008805CC800D\r\nS31500005EC0B31026400802128C10B10022800930025D\r\nS31500005ED0620080002E8008A80222017000000000E7\r\nS31500005EE0C015AC00BB04224028B8022C80A980AAA9\r\nS31500005EF0A0009802AC00A9002E000AA102B004601E\r\nS31500005F00000000004015EC00FB0034240C8813A5AB\r\nS31500005F1002F8C032320DB8034000C8203C000C180D\r\nS31500005F202310047000000000E001BC00FF003FA049\r\nS31500005F304FF00BF600D100BF000FF003F050FE103B\r\nS31500005F403FC00FC003F80060000000004010AC0422\r\nS31500005F50F30432400C80172D02C90032000CB8033E\r\nS31500005F602040C84232C00F9003D004200000000039\r\nS31500005F70C8053C80BF0022C008BC0A2E00092020AC\r\nS31500005F80000D0D22A8008B8836C80B8A02F200404D\r\nS31500005F9000000000E0054C00B300A0800891C22478\r\nS31500005FA0C2004C28928A30020A00830020000B00AF\r\nS31500005FB002F800500000000020011E00B3842320D8\r\nS31500005FC02849021E06858021A01B7902B6008E8014\r\nS31500005FD025700B5802C800400000000048080C005D\r\nS31500005FE0B30230900C040A2C04C140B8800E310371\r\nS31500005FF00802C30030840F2003D202000000000014\r\nS31500006000401DBC00FF083F0203E01BFC027D123D61\r\nS31500006010800DD101FC40FF403F030FF803D006601E\r\nS3150000602000000000A805EC00CB6032D80F901B24BE\r\nS3150000603008C00530000CB0032F80C9203E0A0BB003\r\nS3150000604003EA00700000000048119C80832821C4E8\r\nS315000060500B60021000C70021000A700295408640BE\r\nS315000060602DC8097502D2046000000000C0008E40F1\r\nS31500006070878021E00BD8023F089680212009D8228C\r\nS315000060803E0085A22DE80B7A02F0002000000000F9\r\nS315000060904814EC01830020F28BA8022F0483882089\r\nS315000060A0560B04128C0083802CC0093B42D204306C\r\nS315000060B000000000E815A800CA0032B80FEB03394B\r\nS315000060C000DEE0B3B00DE6032902CA883E940FA8AD\r\nS315000060D003FA0460000000004800E006F000BE007D\r\nS315000060E00F8043E10AF8403E008E8603E120F84027\r\nS315000060F03E00078403D20030000000000810E600CE\r\nS31500006100C900F2400F9003E420E19032400E901354\r\nS315000061102400F9003E400F9903C20430000000003D\r\nS3150000612080046600890022F80B962A260089C02082\r\nS3150000613048081203ED24BBD82EC00BB002E00010B5\r\nS315000061400000000018052440898022440B9202EECC\r\nS3150000615025A94022401A90022400B9002E400B9037\r\nS3150000616082C60040000000000804050281002040AD\r\nS315000061700B140205018100A240081002C400B104FC\r\nS315000061802C404B1002C2010000000000B80D620056\r\nS31500006190C88222000F800BE002E88032000E8003E6\r\nS315000061A02000F8023E000F8003EE035000000000BE\r\nS315000061B0981DF700F9403E400F5802DE047D403F2F\r\nS315000061C0404F5001C400F9003E400F9003E60670B0\r\nS315000061D0000000001801D400CD00164007D003F4DB\r\nS315000061E000CD0413400ED0016410F9003EC00F909C\r\nS315000061F043C60070000000003810E00088003281BD\r\nS315000062000B206220088A0022800A80022000BA0041\r\nS315000062102E008B8000CE0430000000000805C4006C\r\nS3150000622081002440093002C400810222C00A100203\r\nS315000062300400B1002C408B1000C201700000000069\r\nS3150000624018158400890026400B1012245A89808272\r\nS31500006250448A96022400B9002E461B9002C60460AA\r\nS3150000626000000000A015E402C90436500D9413E6A0\r\nS3150000627002C140306046940B2440F9007E505F987E\r\nS3150000628003E80470000000002801A400F1003A4071\r\nS315000062900F9A0BE400F9003E600F9023E600F90028\r\nS315000062A07E400F9203CA0060000000002810A00084\r\nS315000062B0E80032100F84A3E302D84032120C824366\r\nS315000062C02000F84036000F8003CA042000000000BA\r\nS315000062D0280528008A08A2860BE00A38008E0037B7\r\nS315000062E080086C93EB10BA402EB80BA502CA00408A\r\nS315000062F00000000028054600A38020C01B304A6E1F\r\nS3150000630050931028C00A18060C80B32024E80B38D6\r\nS3150000631002CA005000000000A0013C288301A1C071\r\nS315000063200B70021C0582002DC01AD026D420350021\r\nS315000063302D400B5422E8004000000000A8081E80F3\r\nS31500006340E58021A00F780B7200D48039E02E580327\r\nS315000063501A40F69035E20F7803EA020000000000CA\r\nS31500006360081DAD24F9003E8A0FB00BE408F800B40E\r\nS31500006370C00D1003E000FA203E480FB403C20660C9\r\nS31500006380000000000005DE20CD8203E40FFB03DEE3\r\nS3150000639010DF8035610C58033E00FF803FA00EFCE5\r\nS315000063A003C0107000000000A8119C008520B1C237\r\nS315000063B00BE3121402E66021080F50021420B540C8\r\nS315000063C02D900B5002EA04600000000000009400CB\r\nS315000063D0850221408B7386B0028601274008D002D1\r\nS315000063E01800B6102D820B4802C0002000000000E5\r\nS315000063F02014CC00810024400BB0022480A0002091\r\nS31500006400500B14024200B2002C881B0402C8043050\r\nS3150000641000000000A815BC00C30032400FB803A45A\r\nS3150000642080CA84B6510C1C032C40FB403EE11EA4DE\r\nS3150000643003EA0460000000008000E400FB013A402B\r\nS315000064400FB403A502FA303E120EBC83AD00F9501C\r\nS315000064503E101F8003E00030000000000110DC0049\r\nS31500006460D90033100FF08BB004F200374002D0038E\r\nS315000064703E00FD283FC44FF093C0443000000000AA\r\nS3150000648081046C40A900A2000BB8A227008A8020D4\r\nS315000064902008BC03ED00B9C02E300BB082E04010DE\r\nS315000064A00000000080052C00990022900B9102222A\r\nS315000064B02ABA80A6700AB8862180BA002E418BA01F\r\nS315000064C002E000400000000008040C00A10020804B\r\nS315000064D00B30020401820022000AB026C001B0007F\r\nS315000064E00C000B0002C2010000000000000D7C0041\r\nS315000064F0D90022000FB00B2002FA0436400EB0037A\r\nS315000065002000F8001E400F8003C00350000000006A\r\nS31500006510A01DF400FD002F000FF003F404FC003F63\r\nS31500006520400DE003F000FC003F000FC023E80670BA\r\nS3150000653000000000C005FC08CF00B3640C482330FF\r\nS3150000654060FC1833000CC0033000CF8033E00FE04E\r\nS315000065500330007000000000C010F4608F6022C09D\r\nS315000065600898020180B960224828200221008B0089\r\nS3150000657020C00BA00220003000000000C805CC801F\r\nS31500006580811D20C00810120401B20020022810024A\r\nS315000065900C40810020C08BA0022201700000000088\r\nS315000065A0C0158402890022C00898022400B301287D\r\nS315000065B0C248B10207008301A2C14BA002300460A9\r\nS315000065C0000000000015F400C50032C40C9C022B2C\r\nS315000065D028F818B2800C8C032E00CB8022E00FE046\r\nS315000065E00B00007000000000E001BC02F9003FC093\r\nS315000065F00FF003F900FD0136040FD80BF402FFA0DB\r\nS315000066003FE40FA083F80460000000004010A422BD\r\nS31500006610EB1832C00EB4232C60CA013EC02CA40372\r\nS315000066202D00DB003AC08CA02310042000000000DF\r\nS31500006630D8012E008B80A2DC8C300A26108B502EBF\r\nS31500006640E008B00224008B042250086402320040A5\r\nS3150000665000000000E0054C02B30422D00A10020339\r\nS315000066600090116C2208800A0400930028F2082981\r\nS315000066700230000000000000F80116229790A1E009\r\nS3150000668008D902120295822D2208580236008F84FC\r\nS3150000669021E74868060800000000000048082C8032\r\nS315000066A0F110B2C40E14030400D2023CC88C2403B9\r\nS315000066B00C00D30038C42C20031206000000000092\r\nS315000066C0401DB602ED903FC00CD003FD00EF513FD8\r\nS315000066D0C00FF103DC00F7003FC40FE013D0062023\r\nS315000066E000000000A805E422C90D32C10FB003293D\r\nS315000066F000F880B2208C8003EC02CB48B2CA0CA111\r\nS315000067000302007000000000C8119C008100A1C0B7\r\nS315000067100B70029C00B2002000085022DC00A7008B\r\nS3150000672021C008E0035200600000000080008600DF\r\nS31500006730878021E20BF8021A21B5C021E0486822C1\r\nS31500006740CE00878821E008680208102000000000BB\r\nS315000067504814CC12839022E00B38828E91B30060ED\r\nS31500006760F2683C02CE00AB8120E00820025A0430D9\r\nS3150000677000000000E815AA02CE00B2A00FE48228AD\r\nS3150000678004FAC2339804ED83F960CA0030A028E009\r\nS31500006790033A0020000000004800C140F0003E001F\r\nS315000067A00F8003E008B8643E110F0003E000F80014\r\nS315000067B03E040F8043D20420000000000810E68249\r\nS315000067C0C990B2680C9C032C80FB143E404F90236A\r\nS315000067D02400CBA032C00C98030204200000000065\r\nS315000067E0800467108980A2600818022490B9402EA0\r\nS315000067F0640B900A2500898022500815022000109B\r\nS3150000680000000000180524008900224009900A248F\r\nS3150000681000B9002E400B9002050289002250089410\r\nS31500006820020600400000000008040D048340A0504A\r\nS315000068300990020480B3202CC84B12020480810008\r\nS31500006840224028928202110000000000B80D620268\r\nS31500006850C88032802D80032340F8D03E340F880351\r\nS315000068602200C000B0000C870B2E0750000000006D\r\nS31500006870981DF7007DC03F600E5003E640F9900F6B\r\nS31500006880640FD383F4E0F9283E4A0FD803EE06706E\r\nS31500006890000000009805F702DDC037404CD0032405\r\nS315000068A000C90032401C94032500C91032440CDA9A\r\nS315000068B003CE0070000000003800E3C088C4220048\r\nS315000068C0088002200088002200288A0A2282888006\r\nS315000068D02320280002C60430000000004805C4003A\r\nS315000068E09960264008904A040081012060085022E1\r\nS315000068F016008520A148081402D2002000000000DE\r\nS3150000690018158C0089202260689402040281602296\r\nS3150000691048489402140085002144189002C60420B9\r\nS3150000692000000000A015E400D90034400C14032632\r\nS3150000693020C900B2600898032608C90022600C909E\r\nS3150000694023E80020000000006801A420F90A3E4068\r\nS315000069500F9203ED00FB003EC20F1A03E640F9A0BA\r\nS315000069603E400F9003DA0420000000002810A0002B\r\nS31500006970C800B2000E8001E100F84830000F8043E5\r\nS315000069802000C80033000C80030A04200000000029\r\nS315000069902805390086C0A3B208A002E880BAA02262\r\nS315000069A0800BA0022A008A00238008E402820000ED\r\nS315000069B00000000028054D02828420080A1102CF3B\r\nS315000069C084B3C0A0F00B38020E02830020A0093E5B\r\nS315000069D00202005000000000A01114028608218067\r\nS315000069E0085002D400B70021420B74021C20870015\r\nS315000069F02190097C0288044000000000A8003E00A7\r\nS31500006A00CE8433200E7803DE40F38431E00FF80B9A\r\nS31500006A103A00CD80B3E02D78030A020000000000A2\r\nS31500006A200815A400F8003E000FB003E800FB203E66\r\nS31500006A30080FB003E802F9003EC00EB003C20460BE\r\nS31500006A40000000004005FA00DC8033E00059033EF8\r\nS31500006A5002CFC13FF08CD802B600C78133200CC8E4\r\nS31500006A600B18002000000000A81190008C1021C017\r\nS31500006A70085022182084002D8008D2823480871086\r\nS31500006A8023042840036A0420000000000800980040\r\nS31500006A909400234008D00A0C00A4102D4008540688\r\nS31500006AA090008D002D6009C002400020000000000B\r\nS31500006AB06014C24083002020481C820B20A0C02CFA\r\nS31500006AC0102810028000A9002E4419200A50042024\r\nS31500006AD000000000B815AC02DA00B2480C98822912\r\nS31500006AE004E8212EB808A003AE82CAA03EA009B0D1\r\nS31500006AF0036B0060000000008000C402FA003ED074\r\nS31500006B00AF9003E0005B003C920FA0016C001A40BE\r\nS31500006B10B2800EB403E80430000000008010F400D8\r\nS31500006B20CE0033C00FF0033640FF4A3E688CE003C8\r\nS31500006B305800DC0233C004F000C1443000000000FD\r\nS31500006B4080047A108400A2B00B30022380BB402E52\r\nS31500006B500088E02238008C40A3C0088102E0401083\r\nS31500006B600000000080052880880122F10B90022495\r\nS31500006B7000B8412ED009008264049A0C62000A8093\r\nS31500006B8086E000500000000008040002800020C0DB\r\nS31500006B900B900A0000B0002C8028000A0400920026\r\nS31500006BA020003A1012C2000000000000800D4010C4\r\nS31500006BB0C80432C00F90032400F8003E400D804305\r\nS31500006BC06002D80032408E8003C002100000000030\r\nS31500006BD0A01DFC00FF003D800FD003F000FC013F2C\r\nS31500006BE0001FC003F000EC003F400D4003E80670B4\r\nS31500006BF000000000C005FE00FC803F200EF80310D8\r\nS31500006C0080FE801F600FD8033CC0DF003FC90CF038\r\nS31500006C1003300070000000008010EE00B8810E20E6\r\nS31500006C2008B8222B40BA812E200BA802BDC0CB800B\r\nS31500006C302FC408F412B00430000000008805CC0010\r\nS31500006C40B0842E000A30128010B2002C400B1002C5\r\nS31500006C500C0883002CC008340232017000000000CA\r\nS31500006C60C015AC00B8812E02889002AA00BA082E80\r\nS31500006C70200B880AAC008B002EC008B002B004605E\r\nS31500006C80000000004015EC00F8803C400E2403A3F1\r\nS31500006C9084FA041E680F18032C00CF003EC02CB0E7\r\nS31500006CA00300047000000000E001BC40FC023FE469\r\nS31500006CB08FF9237808FE0A3F400FF003EC02FF002D\r\nS31500006CC03FC00F3003F80060000000004010AE0027\r\nS31500006CD0F80036000FAC03E900CAC03ED64FB0C379\r\nS31500006CE08C02CB103EC00CB0031004200000000044\r\nS31500006CF0C8052C00B84822808BB002EE0088802E92\r\nS31500006D00900BB0023C008F802FC028F02236004046\r\nS31500006D1000000000E0054400B0A024800B3000CA4B\r\nS31500006D204102402C700B31028C1293802EC0083029\r\nS31500006D300A3A00500000000020011E10B48521A16F\r\nS31500006D400B7E02DE0086802D200B68021E40178017\r\nS31500006D502CE40878023C00400000000048080C00C3\r\nS31500006D60F10034C40F3403C040C2103C410F31035C\r\nS31500006D708C00D3003CC00C3003120200000000005F\r\nS31500006D80401DBC00F5003FC10FF203FC02FF003FAF\r\nS31500006D90C00F6103FC006F003FC00FF103D0066017\r\nS31500006DA000000000A805CF80C2803A500F3C8368DF\r\nS31500006DB000FA013E400FB003ECC0EB0232C80CB241\r\nS31500006DC0032A00700000000048119C40840021CC7A\r\nS31500006DD00B70221C00B6002D400B7002FCC0870011\r\nS31500006DE035DB283682B2046000000000C000BE0019\r\nS31500006DF0848829640BF8825A00B6C02DE00B78020D\r\nS31500006E00DE00A78028E0087802600020000000006D\r\nS31500006E104814CC0280C820D20B34060E41B182241D\r\nS31500006E20E00B3502CC0083002EC008B002D204303D\r\nS31500006E3000000000E815A800CE403AB00FA1037884\r\nS31500006E4000FE803FA04F6403E800EA003A800CA0F1\r\nS31500006E500B7A0460000000004800E010F8003E04D1\r\nS31500006E600F8003E000F8043E148F8201C002F80090\r\nS31500006E7036000F8003920030000000000810EF007B\r\nS31500006E80F9003E500FB023E420F98032620F9003E0\r\nS31500006E902400D10036400C900202043000000000AD\r\nS31500006EA080046600B9002EF20B9402E400B1802241\r\nS31500006EB0680B9002240089402240089002200010AE\r\nS31500006EC00000000018052400B9C02E40099182E494\r\nS31500006ED000B91822440B90022400995126400890CC\r\nS31500006EE0068600400000000008040400B1002C41A2\r\nS31500006EF00B1002C400B902A0400B900005008108E7\r\nS31500006F00205028100682010000000000B80D600025\r\nS31500006F10F8043E000D8003E200F80032004F800BBB\r\nS31500006F202200D82236202C880BAE03500000000029\r\nS31500006F30981DE400FD003EC00F9043F500FD003FA4\r\nS31500006F40408FD003E700F1003E504F9483660670F1\r\nS31500006F50000000001805CC00FD003E410FD023F4D0\r\nS31500006F6004CD003F404C50036400C98832500C9455\r\nS31500006F7003260070000000003810E000B8002E0064\r\nS31500006F800B8002E0008A002E000880420000884044\r\nS31500006F90A2200888020E0430000000000805C40084\r\nS31500006FA0B1002C400B3002C60081002A40081002B6\r\nS31500006FB04400A100204018100212017000000000D9\r\nS31500006FC01815A404B9642E404B9016E44A89022E83\r\nS31500006FD0500890020400A9002240089002060460AE\r\nS31500006FE000000000A015E600F9403E501F9813C5AA\r\nS31500006FF000C94138402C10036402E90032402C904D\r\nS315000070000B280470000000002801AC40F9883E41BE\r\nS315000070101F9CB3E600F9243E680F9283E400D30078\r\nS315000070203C400F1003DA0060000000002810A000AA\r\nS31500007030C84136104F8013E088F8483E004F800B59\r\nS315000070402000C800B2004C800B0A0420000000009B\r\nS3150000705028012A228E8022880FE042FB00BE422FA2\r\nS31500007060A08BE80228005A01228008A0020A0040EC\r\nS315000070700000000028054E00825024F20B1022CE9C\r\nS3150000708001B3402C620B14020C00832020C029306F\r\nS31500007090020A005000000000A0011E00848421C0E6\r\nS315000070A00A5022DC20B7006D820BE4021C0091001E\r\nS315000070B021C009701228004000000000A8081E2008\r\nS315000070C0C68035E00B5803DE00F5803DE00F58031F\r\nS315000070D01EC0C78830E00DF8032A02000000000039\r\nS315000070E0081DAD80F2003EC00F8003EC00F9003EA3\r\nS315000070F0000FA003ED80FB603EC00EB043C20660E9\r\nS31500007100000000000005FE00FE8037F08F580B3EA1\r\nS3150000711044F79033E00F78037E20CE803FE00CF8F2\r\nS315000071200310007000000000A8119C80B61221C553\r\nS315000071300B64021D04B61121800B42037C008400FF\r\nS315000071402DC00870022A04600000000000409C2840\r\nS31500007150BE0021000B70021C01B510E1400BF006C9\r\nS315000071605C0286002DC0087002440020000000006A\r\nS315000071702014CC00B203A0040B2C020C00B081201A\r\nS31500007180100B04024C0082002CC008300658043054\r\nS3150000719000000000A815AE00F22032200FB7232E03\r\nS315000071A020FBC830E00F34037C08CB003FC02CF036\r\nS315000071B0036E0460000000008000EC00FA403A0014\r\nS315000071C00FA003EC80F94D3EB20F8503AC00F90029\r\nS315000071D03CC00F3003A00030000000000110FE008C\r\nS315000071E0FE0437400FF103DE40CC003F642CFA83E7\r\nS315000071F01C00DCA13EC00CB003A40430000000005B\r\nS3150000720081046608BAA022408BB862ED00D8802EB1\r\nS31500007210200884022C0888C22FC008F00220001023\r\nS315000072200000000080012C48BA8026950B9002E8E9\r\nS31500007230008BC02ED008A08A2C009B402EC008B020\r\nS3150000724006A000400000000008440C10B300608057\r\nS315000072500B0002C00090002C808810020C008100F8\r\nS315000072602CC008300602010000000000000D6C0072\r\nS31500007270FA00B6000F9003E804C8003E408CA00355\r\nS315000072803C00D8013EC02CB003A003500000000013\r\nS31500007290A01DFC00F6003F000FC023F000FC023FDB\r\nS315000072A0400FD003FC08FC023FC00FF003E8067055\r\nS315000072B000000000C005FE00C58033080CF0033C4A\r\nS315000072C000CF003F210C48033200CC803F204FC046\r\nS315000072D003700070000000008010CC008B002200BC\r\nS315000072E00880022000A00026E048B80A2E048B0081\r\nS315000072F02CC00BB502200430000000008805EC000D\r\nS3150000730083002011083002000083002EC0081002FE\r\nS31500007310080093002CC00B90026201700000000070\r\nS31500007320C015AC40830020084881022C00A809261D\r\nS315000073300008A0022500B8406E484BB080300460BB\r\nS31500007340000000000015CE00CB8032600CF0033C3C\r\nS3150000735008CF003C000CAC032C00DA003EE04F9056\r\nS315000073600350047000000000E001BC06FF11BF409E\r\nS315000073700FC00BD008FC983FE40FDC03F000CD00F3\r\nS315000073803FE00FF083F80060000000004010AC0101\r\nS31500007390CB0036500CB013E002CB4032D48CB6038F\r\nS315000073A02500C9C83E828CB403D00420000000002A\r\nS315000073B0C8052C008B0022C0088002EC00888802D9\r\nS315000073C0210D000208008A840EC0483C02F20040EB\r\nS315000073D000000000E0054C8083002480088002CC79\r\nS315000073E000800020D2083D22060001420CF4401421\r\nS315000073F002F8005000000000600116008F9021A0E6\r\nS31500007400087802D2018780212089C9021A00868065\r\nS315000074102DA0087882C800400000000048080C0033\r\nS31500007420830036902C0403E004C020B0080C20032F\r\nS315000074300C22C2113CC02C1003D202000000000036\r\nS31500007440401DB402FF042FD0CBF003FC48FF003DE3\r\nS31500007450C00FD003D000FD003FC00FF003D0066080\r\nS3150000746000000000A805EC00FB0032C00F80432C92\r\nS3150000747002C800B0C00C90030A00CB007A408C9082\r\nS31500007480036A00700000000048119C00BF00A14084\r\nS315000074900B70021000A300290008600A140084087B\r\nS315000074A02DC008700212046000000000C0009600A3\r\nS315000074B0B78021A00B4812421C04862120084C0AE2\r\nS315000074C0322084802BE2293806700020000000005C\r\nS315000074D04814E400BB8020D00B301A6C10830028BF\r\nS315000074E0C00838020C0083102C1009320012043038\r\nS315000074F000000000E815A800FA8032800FA002689C\r\nS3150000750000CA0032802C28032A00CA0039B04DE296\r\nS31500007510237A0460000000004800E048F8103C0CA4\r\nS315000075200FC003B000FC003F000FC003F002FC4098\r\nS315000075303E020C8003D20030000000000810E40078\r\nS31500007540D9A032C00C90032408C10132640D900307\r\nS315000075506420F9803E682C98030204300000000085\r\nS315000075608004640089C4225048942225108900347E\r\nS315000075707008980A2600B9D82E68089C0A200010C0\r\nS315000075800000000018052400994122500810863595\r\nS31500007590008D0023C209F1027480BD002EC00812BE\r\nS315000075A00206004000000000080405008140205843\r\nS315000075B03856021582856025400850021400B50031\r\nS315000075C02E4018128202010000000000B80D600073\r\nS315000075D0D800B2200C080B2200C88032000DA00390\r\nS315000075E06000FC513E140CA7032E0350000000005F\r\nS315000075F09809F600FD801E64079923E644F9913E3A\r\nS31500007600400F1000E400F9803D600FD803E60670D5\r\nS31500007610000000009805E400811032401C9E83267D\r\nS3150000762000C99833402CD0233400CD0033400FD00E\r\nS3150000763003060070000000003810E28088A0A2A0B7\r\nS31500007640288E020A828CC022000880022000880050\r\nS31500007650220009800A0E0430000000000805D4202C\r\nS315000076608500214208520215308520A24108100AE1\r\nS315000076702400810128600B10060201700000000042\r\nS31500007680181584108500214048D01A144885032215\r\nS31500007690420890C2248281402A40C99006060460AE\r\nS315000076A000000000A015E402C9803240089023249F\r\nS315000076B000C90022400C90030400C9503A400F92C2\r\nS315000076C003280470000000002801A480F9203E442D\r\nS315000076D00F100BE400F9003E650F9003E600F980F9\r\nS315000076E0B6520F9203CA0060000000002810A001E5\r\nS315000076F0C80032000C80032002CC0032140C800338\r\nS315000077002000F86132002C8001CA0420000000002D\r\nS31500007710280528018A00228008A04228108E02210E\r\nS31500007720802D6C022A80BE8023B000E182CA004010\r\nS315000077300000000028054E088301A0E08838420EAC\r\nS3150000774000828020C088360A0E04B3C084F008BCCC\r\nS3150000775002CA005000000000A00119008F0021D0CD\r\nS315000077600874021C208642218009D4021C00B50838\r\nS3150000777025E2087002E8004000000000A8083E026A\r\nS31500007780848033A02CE80B1A04CE80B1A00C7803B9\r\nS315000077901E04FF8037604C7843EA020000000000B8\r\nS315000077A0081DA800F8043E800FA003E800FA003C7C\r\nS315000077B0000F1001EC00F9003A400FB003C206605A\r\nS315000077C0000000004005F600FF803F600FD803363A\r\nS315000077D000CC8031E00CF843FE00FFA03FE00FF83C\r\nS315000077E003C0007000000000A8119010B7002D42E1\r\nS315000077F00B518A1404A4052106285422DC10B5086E\r\nS315000078002DC40B7592EA046000000000000094008D\r\nS31500007810B4082D100B000210009080218008710220\r\nS31500007820DC60B7222D400B7002C000200000000073\r\nS315000078306814C200B0002C000B04120100B0B02086\r\nS3150000784012281806CD80B2406CA20B0402C8043080\r\nS3150000785000000000B815AC20FB003EC00FBD032E93\r\nS3150000786080DB40B0B02C3483ED00FAC03EB20F840A\r\nS3150000787003EA0460000000008000E808FB003CC149\r\nS315000078800F3003CC20EB403E900F9603EC00B8205F\r\nS315000078903E900F8013E00030000000008010FC00D6\r\nS315000078A0FC007F800CE0032800C70033008CFC033B\r\nS315000078B07C00FE1133240FC183C044300000000059\r\nS315000078C081007800BC002F8008E0037808DF4022A2\r\nS315000078D0320890032E00B18122000B8C02E040108A\r\nS315000078E00000000080012410BB012E4008901224E5\r\nS315000078F000890822A108B0026C80BA0822900B8089\r\nS3150000790002E000400000000008040001B3006C40E3\r\nS3150000791028100244029100A0002810020C00B800B2\r\nS31500007920A0401B2002C2010000000000800D640080\r\nS31500007930F8002E000C800B2000C90132002C902389\r\nS315000079406C00F80032000F9003C0035000000000E6\r\nS31500007950A01DF000FC001F000FC003F008FD003F53\r\nS31500007960000FC023B400FC003F000FC003E8067000\r\nS3150000797000000000C001FE00CF103BE40CD203184B\r\nS31500007980C0CC8033E00CF9033E40CFC033E02CF886\r\nS3150000799003300070000000008010EC028744A0C095\r\nS315000079A04817823880A02028C028B0022C848B205B\r\nS315000079B028CB08B08A200430000000008805CCA03F\r\nS315000079C083602A8808100208C0A00822C20832066E\r\nS315000079D00C8083A020C81A3002220170000000002B\r\nS315000079E0C0158C008B0122A1A89082080028002ACD\r\nS315000079F0C008B4020C608B0028C00A340230046050\r\nS31500007A00000000004011EC80CB0038B04CAD0B28D4\r\nS31500007A1000E80032E80CB5032F18CB0032EC06B8AC\r\nS31500007A200310047000000000E001BC00FF003F806E\r\nS31500007A300FF043F800FC103DC80FF803FC10FF9050\r\nS31500007A403FC00DF113F80060000000004010AC01CB\r\nS31500007A50C30032900CB0032800C82032C00CB0031B\r\nS31500007A602C00FB0032C00CB40B10042000000000F8\r\nS31500007A70C8052C048F01E2A808B003780088C03638\r\nS31500007A80C00DB0012C00BB0022C008B0023200407D\r\nS31500007A9000000000E0054C018300208008901208D9\r\nS31500007AA08028C020C008B0020C00BB0020C02330D4\r\nS31500007AB0027800500000000020011E0087A5212446\r\nS31500007AC01858067A02A48925E00978021E40B78074\r\nS31500007AD021E00B78024800400000000048080C0036\r\nS31500007AE08300A0940C300B0800E00030C04CB009B5\r\nS31500007AF00C44FB00B0C00FB00352020000000000AF\r\nS31500007B00401D9C00FF201F8427F103F8405C003FC6\r\nS31500007B10C007F013FC50FF003FC00CF8039006604E\r\nS31500007B2000000000A805EF80CB30B2804CB20328DD\r\nS31500007B3000E08832C00FB01B2E00CB0032C00CB064\r\nS31500007B40032A007000000000481198408F08218128\r\nS31500007B504820CB48C0A40029C00B700A3C0087000F\r\nS31500007B6021C0A8700A92046000000000C0009E00B8\r\nS31500007B70878021A0087C021AC0AC8025E00B780221\r\nS31500007B809E01978021E088680230002000000000F6\r\nS31500007B904814CC068B00209088B0024802A2012D22\r\nS31500007BA0200BC89213009410212008C702920430BB\r\nS31500007BB000000000E815A800CA00B1802CA0031838\r\nS31500007BC002EA8836A20FA403AB83DA0032A80CAC13\r\nS31500007BD0033A0460000000004800E080F8003E0818\r\nS31500007BE00F809BE004F8003A090F8143E080E880AB\r\nS31500007BF0BE200F8013D20030000000000810EC00F9\r\nS31500007C00F90032400DBA132400CB003E400C90011F\r\nS31500007C102400F90032402C900302043000000000DA\r\nS31500007C2080046504B9012250089802240089402E78\r\nS31500007C30400890122400B9002240489003600010CA\r\nS31500007C400000000018052420B900225009900224E3\r\nS31500007C500289402D4008D002B405B500214008D065\r\nS31500007C60020600400000000008040500B340225050\r\nS31500007C70081402250081406D5028540A9500B5402D\r\nS31500007C80A15008540242010000000000B80D400057\r\nS31500007C90F880B0004D880B2208C8022E000C0003A5\r\nS31500007CA0A000F00030000C40032E0350000000003E\r\nS31500007CB0981DE60CF9C11F608B9C23F700B9803E26\r\nS31500007CC0600FB8036600B9803E600F9803E6067041\r\nS31500007CD0000000001805F400C9003AC00C90032407\r\nS31500007CE004C90032400F9003A404C90532410C9028\r\nS31500007CF003060070000000003810E2808880A22889\r\nS31500007D00280A02A2008C84A2800B800208008A0046\r\nS31500007D1028000880020E0430000000000805C42078\r\nS31500007D20852829420850821420A50820400B1002FD\r\nS31500007D308400A1002040181002020170000000001B\r\nS31500007D40181184208D0161400878829400A50022D4\r\nS31500007D50480B1002A600A1002A4008900206046003\r\nS31500007D6000000000A015E402C900BA5C4C90032490\r\nS31500007D7002690032500F9403A400E9403242249273\r\nS31500007D8003280470000000002801A400F1003E60F2\r\nS31500007D900F902BE400D9203E400F9C036402D9C00B\r\nS31500007DA03E688F920BCA0060000000002810A101F7\r\nS31500007DB0C8023E104D800B2002CC0032102C8003EE\r\nS31500007DC0E000D840B2100C84030A04200000000032\r\nS31500007DD028052800AA002E8008A0022A00DE01221B\r\nS31500007DE0800DA000E8088A00228048A00A0A004008\r\nS31500007DF0000000002805440083046CC00930120C02\r\nS31500007E0000228060C0083042EC10130022C00BB084\r\nS31500007E10060A005000000000A0013410A7006F40C1\r\nS31500007E200870061820B64021EC497000DC00871463\r\nS31500007E3021C80B730628004000000000A8081200A5\r\nS31500007E4086803DA10D58033E00EF80B3E82C7A03EF\r\nS31500007E50DE80DF8031F82FFA032A020000000000DE\r\nS31500007E60081D80003A003C000F9003E800DB023E4C\r\nS31500007E70DA07B413EC60FB403ED00CB403C20660D4\r\nS31500007E80000000000005F602CF8031E00DF8033651\r\nS31500007E9000E48033E00CFC833EC0CFC033F00CFC22\r\nS31500007EA00300007000000000A81194408F012141DA\r\nS31500007EB00870221008840221C80DF0423C428F004F\r\nS31500007EC023C008F1022A04600000000000009000B0\r\nS31500007ED0860023860811021402BD8023C1087002A1\r\nS31500007EE01C91A71021C0287082000020000000000D\r\nS31500007EF02014C0208A00620008100200029980A0A7\r\nS31500007F00F009B0028F47A34022D418380208043083\r\nS31500007F1000000000A815A500C90032E00CA42B2C17\r\nS31500007F2004FA24B3F20CFE4B3D40EF48B3F02CF8B4\r\nS31500007F304B2A0460000000008000E400F9063E4081\r\nS31500007F40AE2403E800EA003EC00FB0036C005B00FD\r\nS31500007F503EC10FB013E00030000000000110F00039\r\nS31500007F60CC0037802CC0830C04CF0032C20FF089BE\r\nS31500007F703C10CF08B3C200F00300443000000000FC\r\nS31500007F80810470088C81230028C40A38048F0036C7\r\nS31500007F90C00BB0122C028B0122C008B00220401088\r\nS31500007FA00000000080050400892022C018A01A24C1\r\nS31500007FB000880022C00BB0028C00830022C00A3069\r\nS31500007FC00220004000000000080404008100204157\r\nS31500007FD02820020003800024C00B30428C0283005C\r\nS31500007FE020C10A300A02010000000000000D400016\r\nS31500007FF0C80132802C8023240AC90133C00FF00344\r\nS31500008000BC00CF0433C02EF0030003500000000074\r\nS31500008010A019F000FC003F000FC003F000FD003F78\r\nS31500008020C00FF0037C00FF003FC00DF003E80670B0\r\nS3150000803000000000C005F080F48033000D6813B026\r\nS3150000804028FE2137040FD003F208CC013F010CD0E3\r\nS3150000805023700070000000008010E1A0B880A01A14\r\nS3150000806008B8020128B200A2900B90526800820064\r\nS315000080702E00089002200430000000008805C44944\r\nS31500008080B000001009B0028080BA6A244D0B30029D\r\nS31500008090E800A0012C4018100262017000000000E8\r\nS315000080A0C015A440B880220008B0022000BA002201\r\nS315000080B0CA03B0026800AB222C400810823004606C\r\nS315000080C0000000004015E180F0CC32280DB603A573\r\nS315000080D000F20136000FD803CA02E8C83F2008D5CF\r\nS315000080E00350047000000000E001B000FC003F30C7\r\nS315000080F00FF003F688FE003FA00F9103FB02DD8020\r\nS315000081003E050F9803F80060000000004010A5002F\r\nS31500008110F80C30140CB8136403CA0832580FA203C3\r\nS31500008120A800FA403B400D96031004200000000012\r\nS31500008130C8052D00B8C022C008380228688EC022A3\r\nS31500008140E00BA80228003B0022400D90823200403E\r\nS3150000815000000000E00549C0B001A0D20830124B73\r\nS315000081600882C120340B3C008800B1002880082C0E\r\nS315000081700A3800500000000020011A80BC8021E06F\r\nS315000081800878021A08869821A04B78861A40B5907E\r\nS3150000819021A00969120800400000000048080C40B0\r\nS315000081A0F20830C10C320348848200B0400F32031B\r\nS315000081B08800F20038C00C21031202000000000003\r\nS315000081C0401DBCC0FE003F400FF003F400FE083F18\r\nS315000081D0840FF013F800FF043FC40FE903D00660D4\r\nS315000081E000000000A805E880C00032C80F300B6F01\r\nS315000081F008D2033A100CF0030800E800328004A805\r\nS31500008200032A007000000000481184308400218396\r\nS315000082100B71020C288620214208700A180485007A\r\nS31500008220218028200212046000000000C0009A0489\r\nS315000082308E8221E20B78221E008EA029E0092802F8\r\nS315000082403B04A68060E028680230002000000000A1\r\nS315000082504814CE808322A0E00B30820E408200209C\r\nS31500008260F00920820A0083C0A2C00820421204300E\r\nS3150000827000000000E815A882CE4432810F240328AE\r\nS3150000828016CE023AA43D64033A00EE1832800CE0A2\r\nS315000082900B3A0460000000004800E100F8003E02CE\r\nS315000082A00F8003A080E8003C144E8403E000F00039\r\nS315000082B07E000FC003D20030000000000810EE80E0\r\nS315000082C0D90036E00FB0136E00F92032E80C902B7F\r\nS315000082D02400E9003240AC9002C2043000000000E5\r\nS315000082E08004648081C022520B900A2760B184A268\r\nS315000082F07008904225008940A250889042E0001004\r\nS315000083000000000018050404998226480B900A6CA8\r\nS3150000831000B90022500896020500A908225008D08C\r\nS3150000832002C6004000000000080404808180204846\r\nS315000083300B10020481BB2020481892020400A120E1\r\nS315000083402148685200C2010000000000B80D6340D9\r\nS31500008350D80036340F80036340F8D030342C8D0BB0\r\nS315000083602000E08032200CC803EE0350000000001D\r\nS31500008370981DE640FF003EE40F9003E640FD903E68\r\nS31500008380E44FF903F4B0DD383E4E0F9383E60670F2\r\nS31500008390000000001805E400FD003E400FD00B244D\r\nS315000083A010C9043E400FD8432440C910327A0498BD\r\nS315000083B003060070000000003810E000B8002E0030\r\nS315000083C00B8002200080002E000B0002228288A073\r\nS315000083D0A2B828C8120E0430000000000805C40028\r\nS315000083E0B3022C400B18020E0081002C400B140225\r\nS315000083F014008500214808568A020170000000001A\r\nS315000084001815A408B9102E410B9002060089002EFB\r\nS31500008410400B104204808D80214008500206046003\r\nS3150000842000000000A015E424F9852E700B9013249B\r\nS3150000843002C9003E700F9C432600C90832500C90BA\r\nS3150000844003280470000000002801AF00F9003EC8B0\r\nS315000084500F9003EC00FB003EC88F9C1BE604F10066\r\nS315000084603E400F9003CA0060000000002810A18063\r\nS31500008470F800B2000F80032200F80832180C84833B\r\nS315000084802000E84032102CC0030A0420000000003F\r\nS3150000849028052900BE5022920B61022800BA6222EA\r\nS315000084A08008E0436A008A00228008E0020A004051\r\nS315000084B00000000028054F00B30020C80B34020C52\r\nS315000084C008B3C120D48831020E00A38024E0082816\r\nS315000084D0020A005000000000A0011420BF8021C045\r\nS315000084E08B70021001B78021E00870025C30874073\r\nS315000084F025C208640228004000000000A8081E00EB\r\nS31500008500F78021E40F78031E20F788B0602C7803EB\r\nS315000085103A00EE80B4A00CE80B2A0200000000002E\r\nS31500008520081DAC00F3003E400F300BE000F9063E9C\r\nS31500008530800FB003E804FA003A800FA003C2066079\r\nS31500008540000000000005FF00FF80336084E803FEA2\r\nS3150000855010FC8133B10BFB0B3600CD8237600CC8A3\r\nS3150000856001C0007000000000A8119800B7002104A7\r\nS31500008570286442DD409700A19809750234408D2099\r\nS315000085806140084002EA0460000000000000980014\r\nS31500008590B7102180086402D000B50021C00B72021A\r\nS315000085A0500084406500084902C000200000000019\r\nS315000085B02014C920B100A000082002C0809100202C\r\nS315000085C090098042400080002000088802C80430DC\r\nS315000085D000000000A815A920F14032A40C3023EDBC\r\nS315000085E000F30432D00F80036C02CBA036C02CBC43\r\nS315000085F003EA0460000000008000C400F9403E4425\r\nS315000086000F9403CC40DA403E150D8003AC40FB04CA\r\nS315000086103EC01FB583E00030000000000110F400EA\r\nS31500008620CD0833E00FF8033000D800B3420CC10385\r\nS31500008630B800FE0034800CF01380443000000000C7\r\nS315000086408104644889C8225D0B980A230888802221\r\nS3150000865001088C0A3800BE002F8008F40220401062\r\nS315000086600000000080052020898022800BB2122C99\r\nS31500008670408A282060088002A408B9002E4008908D\r\nS3150000868082A00040000000000804000280002000D4\r\nS315000086900B10020C028A00200008000A0400B10038\r\nS315000086A02C4028100202010000000000000D6000AE\r\nS315000086B0C900B0800FB0032000C800B2402C3003C0\r\nS315000086C0A000F80036000C90038003500000000064\r\nS315000086D0A01DF000F5011F000FD002F000FC003FC6\r\nS315000086E0000FC003F000FC013F000FD023E8067026\r\nS315000086F000000000C005FA00C7813F610EF803FCC8\r\nS3150000870040C4803F210CC8033200FF3033CE0C48F2\r\nS3150000871003F00070000000008010EA008B802E40FD\r\nS31500008720289802EDD0A8802E2008B8022200BF703B\r\nS3150000873023D8089802E00430000000008805C00233\r\nS3150000874083002C420A0002CC0880002E408880025A\r\nS315000087500000B30420C0082002E2017000000000FF\r\nS31500008760C011A0008B122E4408B002EC01A9200E05\r\nS315000087704808B0122000B30022C1089002F004603D\r\nS31500008780000000004011EC80CB083E700EB003ECF8\r\nS3150000879000CB813CA00C00072000FB0132C02C80DE\r\nS315000087A003D0047000000000E001BC0CFF803F60B5\r\nS315000087B00FFC03FC00FD803FA10FC003FA81FB0004\r\nS315000087C03EC05FE003F80060000000004010A50016\r\nS315000087D0FB20B2580D80072C10CA0072400FB00360\r\nS315000087E0E408FB00B2C02CB0031004200000000017\r\nS315000087F0C8050540BB80224208B0073C00C90002FC\r\nS31500008800400EBA02EC00BF0037C048B00372004009\r\nS3150000881000000000E0054E00B14022F04930026C35\r\nS3150000882000800868090B0A12CC00A30022C0880049\r\nS31500008830063800500000000020011E20B59865E4AF\r\nS315000088400858061EC18E80A9600A7846D680B7846D\r\nS3150000885025E008D80648004000000000480804004B\r\nS31500008860B11032C00D00126C82C00028840F0303C1\r\nS31500008870C940F30030C02C200312020000000000A3\r\nS31500008880401DB400FD100BC00F7003FC80FF503775\r\nS31500008890F00FF903F2C0FF103FC40FD003D00660FB\r\nS315000088A000000000A805EE00C18032802C9A032C3F\r\nS315000088B000EB403E900D8283EE88CB3032CC8C8329\r\nS315000088C083EA00700000000048119C00D504238054\r\nS315000088D00870821C8087602DD90B4012DCA083149F\r\nS315000088E028CC086002D2046000000000C000A60088\r\nS315000088F0858021A00858021E40A6802DAA097F0265\r\nS31500008900FEC087A021E8087A02F0002000000000DF\r\nS315000089104814C43090042290482C0A2C00A3C02C82\r\nS31500008920C00B3802CD008301AAC0283402D204301D\r\nS3150000893000000000E815A800CA50B2900CAD8328CC\r\nS3150000894010EA223EA00DAC03EB22CA0032806CA9CD\r\nS3150000895003FA0460000000004800F010F8003F0829\r\nS315000089600F8400E01618003E01038013E080F0003B\r\nS315000089703E008F8103D20030000000000810E600A0\r\nS31500008980F9003E400CB003E410C9A83E680F908081\r\nS31500008990E600F90112400C9803C204300000000002\r\nS315000089A080046780B9902E72489902E4128B802E5B\r\nS315000089B0E00BB002ED00B900A2402ABD02E00010B3\r\nS315000089C00000000018053440BD012FC808B002E4BD\r\nS315000089D00289022EC00B9002E464B9002A40089472\r\nS315000089E002C600400000000008041400B7002D5025\r\nS315000089F0283042C50481802CC00B1002C414B14338\r\nS31500008A0088504A1002C2010000000000B80D600044\r\nS31500008A10F8023F000C8023C200C8013E000F80030D\r\nS31500008A20E000F8843A200C8003EE035000000000BA\r\nS31500008A30981DE400B9003E612F1003E704F9003EDB\r\nS31500008A4040039013C404F9C036700F9003E6067015\r\nS31500008A50000000001805F400CD003F400ED003E4EE\r\nS31500008A6000C9003E410F9003E400F90032410C902A\r\nS31500008A7003C60070000000003810E01288002E00C7\r\nS31500008A8088A002C000A8042E800B8002E004B80073\r\nS31500008A90A2000FA002CE0430000000000805C400AA\r\nS31500008AA0A1002C400A1006C40081002C408B18023D\r\nS31500008AB0CC00B1002840281002C20170000000005E\r\nS31500008AC01815A600A9402E40089006E400A9000E3D\r\nS31500008AD0400B9206EC00B10028400B9802C60460D9\r\nS31500008AE000000000A015E400E9413E402E9803E492\r\nS31500008AF000C9601E705F9003E590F9003A400C9043\r\nS31500008B0003E80470000000002801A404D9003E40D8\r\nS31500008B100F9403C402F9003E500F9007E400F900D9\r\nS31500008B20B6400F9003CA0060000000002810A200A3\r\nS31500008B30D8203A000C8003A000C8403E000F8003F6\r\nS31500008B40E104F800B2000C8203CA04200000000011\r\nS31500008B50280518800EC027B80AE002E8008AF42625\r\nS31500008B60A80BA4226940BA00028008A402CA0040E9\r\nS31500008B70000000002805420090922AF2080E048C9C\r\nS31500008B800283C02CC00B3F02CC00B30420C048387F\r\nS31500008B9042CA005000000000A00110008600258097\r\nS31500008BA00A4082DC81870025805B60025C04B73066\r\nS31500008BB021CC087082E8004000000000A8081200DE\r\nS31500008BC0D6813BE02C48039F40C4803D614F7843EB\r\nS31500008BD0DE00FF8A33E02C7803EA02000000000082\r\nS31500008BE0081D8000FA0036800F8003EC00F9403E35\r\nS31500008BF0100FA0036DA0FB213EDA2FB683C20660DC\r\nS31500008C00000000000005D600C680B3A02C48037EF5\r\nS31500008C1090DFD03FF00FFC03F600FF8033E02CE836\r\nS31500008C2003C0007000000000A81190008600230712\r\nS31500008C300840835C0096002D800B5502D448B7127D\r\nS31500008C4021C80D6002EA04600000000000009100E7\r\nS31500008C508600210008E0029C8496046D640B78026D\r\nS31500008C60D200B70020C0184002C00020000000005B\r\nS31500008C702014C80483002212082402CC10920C6C23\r\nS31500008C80030B1606C204BB0020C1390002C804301B\r\nS31500008C9000000000A8158080C20032F0AC8403BC3E\r\nS31500008CA000DB803ED00F9C03E800FF0033C00C9C25\r\nS31500008CB003EA0460000000008000E002FA083E803B\r\nS31500008CC00F80016C003B103ED0038103E840FB049B\r\nS31500008CD03EC10F9183E00030000000000110F0005B\r\nS31500008CE0DE0133C00CC083DC00CC233FA00FD801CB\r\nS31500008CF0F240FB0031C00CE903C044300000000024\r\nS31500008D00810462008A002AE0888E02EC0289002E25\r\nS31500008D10A80B8D02E304BB0436C008AC02E0401089\r\nS31500008D2000000000800526009A8022A2088802EC36\r\nS31500008D300089002E448BA002EC00BB0222C04890A2\r\nS31500008D40C2E0004000000000080400008200280085\r\nS31500008D50280006CC0480002C401B0002CC04B30083\r\nS31500008D60A4C0081002C2010000000000000D60004F\r\nS31500008D70DA0232808C9012FC02C8003E000FA0037B\r\nS31500008D80E000FF0133C0248003C003500000000050\r\nS31500008D90A01DF004FF000F800FD023FC04FC003F51\r\nS31500008DA0000FC003F000FF003FC00FC003E80670CD\r\nS31500008DB000000000C001D884DC0133080BC203B4F4\r\nS31500008DC000DF003FC00FF0031200F48033200FC80D\r\nS31500008DD00330007000000000C010E92088C0208029\r\nS31500008DE0082042240088802E010B80022C00BB0044\r\nS31500008DF020C00BB002B0043000000000C805C8C097\r\nS31500008E00914420110B0102884493002C000B300280\r\nS31500008E100800BB0124000B100232017000000000A4\r\nS31500008E20C015A8208904228208A08A280088002E5E\r\nS31500008E30C00380822400B80226C40B2002B004605E\r\nS31500008E40000000000015F900DC1033100FC403B455\r\nS31500008E5002DF483FC007F00B2C00F8E036F20FB0F7\r\nS31500008E600300047000000000F001B800F8843F80A1\r\nS31500008E700FE003F402F8403F010F8903F000FF20E2\r\nS31500008E803B200FC403F80060000000004010A9203A\r\nS31500008E90D90032100C84032820CB103A000C34037E\r\nS31500008EA02400CB0032C20CA00310042000000000F6\r\nS31500008EB0D8052900812122A808AB022A808800361D\r\nS31500008EC0C00880022808800022000892137600401D\r\nS31500008ED000000000E0056D009280A2400894422741\r\nS31500008EE002800020C00A00020480832420C00828D3\r\nS31500008EF0823A005000000000F0011E02868421E044\r\nS31500008F003878021600878024200A78023A118C905D\r\nS31500008F1001200858027C00400000000048080C00B0\r\nS31500008F20D30030480C10032800C00420000E020BAA\r\nS31500008F300C02401110C82CB0031202000000000001\r\nS31500008F40401DAC40FB003EC00FB103EA40FB1036AB\r\nS31500008F50C00DB003E0407B103E000F8403D00660D6\r\nS31500008F6000000000A805EE10CA003A404C90032409\r\nS31500008F7000D88032C02C800B2800CB8432204C9045\r\nS31500008F80432A027000000000C8118C00860020C031\r\nS31500008F900830021402A3002900087002340284017A\r\nS31500008FA021C00860023200600000000080009E00C0\r\nS31500008FB087802D600858021A029480202009080232\r\nS31500008FC052008480212008C80E20002000000000E6\r\nS31500008FD04814CC00830024C008B0022800A3002A4D\r\nS31500008FE0C049B0124C44830020F2083C821204307F\r\nS31500008FF000000000E815A802CA003E802CA00B382D\r\nS3150000900006DA00B2800DA00B4800CA00B2B02C2CC4\r\nS31500009010033A0460000000004800E000F0003A1146\r\nS315000090200F8003F000FC003B000EC043B020FC00A4\r\nS315000090303F040FC503D20030000000000810E60010\r\nS31500009040F9A032400D9003640279203E682C9A0301\r\nS315000090502408C9003E400F900B02043000000000B7\r\nS3150000906080046500B98022580890122400D9802E09\r\nS3150000907060089812240089002E400B9002201010E0\r\nS315000090800000000018012480BD00214009D01A7498\r\nS3150000909000B9042F4018D0063C008D002F400BD09D\r\nS315000090A0820600400000000008040D00B501614082\r\nS315000090B00850021402B5202D4808522234028500B9\r\nS315000090C02D408BD00202010000000000B80D6200A6\r\nS315000090D0F880B2342D8D435340F8803E342C8D0BEE\r\nS315000090E02144C0503C140FC5032E0150000000005F\r\nS315000090F0981DE700F1402E700B9C13E704D9103E33\r\nS31500009100644F9913E604F9803E600F3803E6047055\r\nS31500009110000000009855F680FDA432780E9E0327C5\r\nS3150000912020C98032620C98832500C94032400D90D8\r\nS315000091300A260070000000003810E140BA402228DC\r\nS315000091400888423300A85020B0080E8202008A80A8\r\nS31500009150222008CA820E0430000000004805C40020\r\nS31500009160B11421500A540214008100214208500211\r\nS3150000917014008500234A0950021201700000000005\r\nS315000091801815A400B900224008D0023400A9002016\r\nS31500009190C4087002148085802340085002060460CB\r\nS315000091A000000000A005E400F940B2404E900B26F6\r\nS315000091B082C90012409C90032602C940B0400D941B\r\nS315000091C003280470000000006801A410F9003C4068\r\nS315000091D02F100BE440F300BE402F900BE400F90083\r\nS315000091E03E400F9003DA0060000000002800A00057\r\nS315000091F0D850B2000D80033110C81032014C8003E4\r\nS315000092002000C80032010CC0030A04200000000040\r\nS3150000921028053A208680228008A00238008A00228B\r\nS315000092208008A0022A008A00228008E0020A004084\r\nS315000092300000000028054480920020C00930022A60\r\nS31500009240008381A8C028304A0E02838020E00828C7\r\nS31500009250020A005000000000A00112008600214012\r\nS315000092600840021822870069C0087002182086404C\r\nS31500009270219008640228004000000000A8080A00A7\r\nS31500009280D28430A04D380B0A02C38039600C5803D3\r\nS315000092901E00CF80B3E02CF80B2A0200000000006D\r\nS315000092A0081DA800FA001E000F8003E800FB003628\r\nS315000092B0400F9003E800FA003E800FB003C206603C\r\nS315000092C0000000004005FE00FE8033E00FF803B208\r\nS315000092D000CFC03FE00CF8033600CD8031600DC8EA\r\nS315000092E003D0007000000000A8119800B6102346B5\r\nS315000092F048418A100087082DC428F00230608C107F\r\nS31500009300A104084102EA0460000000001000980071\r\nS31500009310B600A1800A7002922287102C4008510ADA\r\nS31500009320140085002340095802C0002000000000F8\r\nS315000093306814C808B2002200088002010083402C8D\r\nS3150000934050081402430080802200081806D8043012\r\nS3150000935000000000A815A400FA0032E00EB843ACE5\r\nS3150000936040CBC53EBD2CAF032D42CB4832CC0DA41D\r\nS3150000937083EA0460000000009000E000FA003E402E\r\nS315000093800E8003EC02FB203E900F2403A810FA2067\r\nS315000093903E800FA203E00030000000008010F806B7\r\nS315000093A0CA223F802CF00B2C02FF00310024C003A0\r\nS315000093B0BC00DF0037C00CF003E004300000000002\r\nS315000093C0800449808A802F0048C0023D2083903760\r\nS315000093D01008C4123800BE002F8008F002E000100A\r\nS315000093E00000000080052C008A002EC038B0420420\r\nS315000093F002BB042A800AA006A400B9012E400880F8\r\nS3150000940002E000400000000008040C0082002C402E\r\nS31500009410080002040083002C800A20420004300069\r\nS315000094202C00280002C2010000000000800D6C0024\r\nS31500009430CA003E800C30132402FB003A010E800B5A\r\nS31500009440A400D90036400C9003E003500000000051\r\nS31500009450A019FC00FC003F000FC003F402FD013719\r\nS31500009460000DC003F000DC003F000FD003E80670DB\r\nS3150000947000000000C005F200FC803F208FE8177254\r\nS3150000948000FD9033200CF0033210FC803F200FF2D9\r\nS3150000949003300070000000008010E200B8802E202B\r\nS315000094A08BA802E200B12022200AF90A2200E980F4\r\nS315000094B02EE00BF902200430000000008805C000F1\r\nS315000094C0B3022C000B20028400B120200088300259\r\nS315000094D0C000B0002C000B300262017000000000DA\r\nS315000094E0C015A400BB002EC00BA002E000B300A272\r\nS315000094F0420AB0026040A8202EC203B00270046087\r\nS31500009500000000004015E200F8023EC00FA0036212\r\nS3150000951000FA00302004B003E000FA223E100FB03B\r\nS315000095200B50047000000000E001B288FD903FC0BF\r\nS315000095300FE022FF10FF423FB00F7003B000FF00A4\r\nS315000095403FA90F3003B80060000000004010A800DB\r\nS31500009550F8003E004FA013E400FB0032100FB203E8\r\nS315000095602D00F8003E100FB003100420000000008C\r\nS31500009570C8052C00B9042ED40BA802EC00BB00AA27\r\nS31500009580C00BF2022E00B8802E880BF0023200408B\r\nS3150000959000000000E0054C00B0042C200B2102CA9C\r\nS315000095A000B30020C08B34000E04B0C82C000B3072\r\nS315000095B0023800500000000020011A00B4902D204F\r\nS315000095C00B6802D200B790A9240B38021E20B5887A\r\nS315000095D02D600B78020800400000000048080D00CE\r\nS315000095E0F3003C020F2003CC20F10030C00F300303\r\nS315000095F00900F3001C004F300B12020000000000AF\r\nS31500009600401DBC20FF803FE00FE001F0407F003F9F\r\nS31500009610400FF10BFA60FF023F660FF503D00660BC\r\nS3150000962000000000A805E700EA803AC00F282328BA\r\nS3150000963080CA0030E80CB6032788CAE132E00CB5D0\r\nS31500009640032A00700000000048119040877021CA6C\r\nS315000096500B60035D40DF0021820A76A29440C76951\r\nS3150000966029CC0A700212046000000000C000BE800F\r\nS31500009670AEA829240B68063F00978823F0087A02D3\r\nS315000096803E209F8023EA083A0230002000000000B6\r\nS315000096904814CC00830220F48B20024E809340A015\r\nS315000096A0E00A30028C80830028E80A300212043077\r\nS315000096B000000000E815AA00EA013A908FE00329AD\r\nS315000096C000DE0032804CA0232B02DA8832800CA008\r\nS315000096D00B3A0460000000004800E040F8403E00FD\r\nS315000096E0078003E000F8203E100F0003E100E800C9\r\nS315000096F03E000F0003D20030000000000810E40016\r\nS31500009700F9C87E460F9103E508C90032E40F9A2393\r\nS315000097102400F9003E480F900302043000000000C8\r\nS3150000972080046D00BB006EE00B9202CF00A9002200\r\nS31500009730700B94016D08BB002EC80B9003600010DF\r\nS315000097400000000018052400B9002E400B9002E42A\r\nS3150000975022A100A2420B94022401B9000E408B9074\r\nS31500009760020600400000000008040C00B3002C4074\r\nS315000097700B1002E400A14020400310004401B10494\r\nS315000097802C408B100242010000000000B80D600062\r\nS31500009790F8002E000F8003E000C80022000F8803A7\r\nS315000097A02800F8003E004F880B2E035000000000F2\r\nS315000097B0981DC410F1003E400FD001C4005D803EEC\r\nS315000097C040071401C400F3023C400F9403E6067000\r\nS315000097D0000000001805E400F9003C400FD0032407\r\nS315000097E000F90032400F90032400F9023E400F902A\r\nS315000097F003060070000000003810E000BA002E00DA\r\nS315000098008B80022800B80022008B8002A808B802CC\r\nS315000098102E000B80020E0430000000000805C40074\r\nS31500009820B1010C400B90020400B100E0C00B1042E5\r\nS315000098300400B3002C408B100A02017000000000E7\r\nS315000098401815A440B9202E400B90022408B9102206\r\nS31500009850500BB006A400BB002E400B90020604601D\r\nS3150000986000000000A015E520F9003E780F900B25BA\r\nS3150000987000F9E032504F90032500F9C03E400F90AA\r\nS3150000988003280470000000002801A408F9003E68BF\r\nS315000098900F9003E408F9003EC00F3003E700F9C05B\r\nS315000098A03E400F9003CA0060000000002810A00090\r\nS315000098B0F8003E100D8003E080F840B2000F8803E8\r\nS315000098C0212038603E000F00030A0420000000003B\r\nS315000098D028052B00BA802EB0086A02E900BA0022D9\r\nS315000098E0808BA20A2B00BA422E800BA0034A0040AE\r\nS315000098F00000000028054F80B3A02CFC092602CCEE\r\nS3150000990000BB0064D80B38024C01B3002CF80B30B6\r\nS31500009910020A005000000000A0011D00B7402FA061\r\nS31500009920086002DC00BF0225C00B20025420B500EF\r\nS315000099302DC20B300268004000000000A8081E007F\r\nS31500009940F7803D600D7803DE00F78025E40F78038D\r\nS315000099505E00F7903DE40F78032A02000000000045\r\nS31500009960081DACA0FB483E9A0FB003E5A0F3403AB1\r\nS31500009970D00F9003A500F9403E500FB003C2066019\r\nS31500009980000000000005FA00FE803FE00FC803FE5D\r\nS3150000999000CFC833A40CDC033B00FF803F200FF848\r\nS315000099A003C0007000000000A8119800B6002DC981\r\nS315000099B08B4002DC00D70035800862035900B400F2\r\nS315000099C02D100B70026A0460000000000000980071\r\nS315000099D0B5802D610B5002F8008F082140494006E2\r\nS315000099E01E00B7002DF00B7002C000200000000022\r\nS315000099F02014C820B10A2CE60B1022C1009B482473\r\nS31500009A00440900024C00B00C2C600B3002480430B4\r\nS31500009A1000000000A815AD00FB003EE00FA003E12A\r\nS31500009A2000CF8032402DB0012C00FA027EC80FB064\r\nS31500009A3003EA0460000000008000ED00FB403E9059\r\nS31500009A408FA003E960FB003E520E3003E500FA40AA\r\nS31500009A503ED00F3003E00030000000000110FA0095\r\nS31500009A60FE003F400FF0073200FF04B3A00FD403FF\r\nS31500009A703880FEA03F800FF0030044300000000055\r\nS31500009A8081046800BA002E800B38022100BB002238\r\nS31500009A90A00BAC022000BA002E000BB00220401032\r\nS31500009AA00000000080052460BA402EB00BB80264A6\r\nS31500009AB060BB00220A0BA0022008B9002E000BB0E2\r\nS31500009AC0022000400000000008040400B2002C80C0\r\nS31500009AD00BB80A0C00B30020001B00020000B00007\r\nS31500009AE02C000B300A02010000000000000D60008F\r\nS31500009AF0F8023E000FB0232000FF0032000F900353\r\nS31500009B002000F9003E800FB0030003500000000063\r\nS31500009B10A01DF000FC043F000FD003D000F7003D6D\r\nS31500009B20000F402BF000BC003F000FF003E806706A\r\nS31500009B300000000000C541037040DC1037040DC171\r\nS31500009B40037040DC1037040DC1017040DC1037048F\r\nS31500009B500DC031000000000000C5440571015C40E5\r\nS31500009B60571015C40571015440571015C4057100EE\r\nS31500009B704840571015C03150000000000080020117\r\nS31500009B802080482012080482012080482012080400\r\nS31500009B908201208048201208048020000000000076\r\nS31500009BA00080000060005800160005800160005823\r\nS31500009BB00016000500056000500006000580200024\r\nS31500009BC00000000000C5480572015C80572015C8DA\r\nS31500009BD00572015C80572015C80572005480552017\r\nS31500009BE015C031500000000000C54000600018009C\r\nS31500009BF00600018000600018000600018000604138\r\nS31500009C0018000600018031000000000000C548046D\r\nS31500009C102201088042201088042201088042201078\r\nS31500009C2080042001088042201080310000000000DE\r\nS31500009C3000C54A05428150A05428150A05428150A4\r\nS31500009C40A0542815020140C150B0542C15003150C3\r\nS31500009C500000000000800C01530055C01530054C73\r\nS31500009C6001530055C01574054C01570040C0113012\r\nS31500009C7004402000000000000080000040001000AA\r\nS31500009C80040001000040001000040001080060000C\r\nS31500009C9000000100004121000000000000C5600234\r\nS31500009CA00800820020800820020800820020840824\r\nS31500009CB02002280582002180084131500000000062\r\nS31500009CC000C5400560015900560015800560015920\r\nS31500009CD00056401580076401480056001580310083\r\nS31500009CE00000000000C540036000D80036000D806B\r\nS31500009CF0036000D80016000588016002D8007600CF\r\nS31500009D000D8031000000000000C5420430810C20A7\r\nS31500009D10430810C20430810C20430810C30430806D\r\nS31500009D200C20430810C031500000000000800000E5\r\nS31500009D3030000C00030000C00030000C00030000DF\r\nS31500009D40C01032000C00030000C02000000000001C\r\nS31500009D500080020130804C20130804C20130804C80\r\nS31500009D6020130804C20532C04C20530804C020103A\r\nS31500009D700000000000C54205608158205608158283\r\nS31500009D800560815820560815830560C0582056087E\r\nS31500009D90158011500000000000C5420020800820F8\r\nS31500009DA0020800820020800820020800820030811C\r\nS31500009DB018200208008031000000000000C542049F\r\nS31500009DC06081182046081182046081182046081117\r\nS31500009DD082043481092046481180310000000000C9\r\nS31500009DE000C5600558015600558015600558015696\r\nS31500009DF00055801560011801420015801140315050\r\nS31500009E00000000000080060141805060141805061D\r\nS31500009E1001418050601418050601518054601418E1\r\nS31500009E2005002000000000000080020100804020A4\r\nS31500009E3010080402010080402050085402010480EA\r\nS31500009E4041211048040020000000000000C5460320\r\nS31500009E505180D46035180D46035180D46035180DF5\r\nS31500009E6046025181946035180D40315000000000C3\r\nS31500009E7000C5460571815C60571815C60171815C85\r\nS31500009E8060571815C60771815C60571811C011001C\r\nS31500009E9000000000004546037180DC6037180DC6DF\r\nS31500009EA0037180DC6037180DC6017180DC603718DD\r\nS31500009EB01DC01100000000000045460571815C6070\r\nS31500009EC0571815C60571815C60571815C614318080\r\nS31500009ED01C60571814C01150000000000000020159\r\nS31500009EE0208048201208048201208048201208049D\r\nS31500009EF0820170804C2012080580000000000000DE\r\nS31500009F0000000601618058601618058601618058B8\r\nS31500009F1060161805860561805860161815800000C1\r\nS31500009F20000000000045400570015C00570015C0A8\r\nS31500009F300570015C00530014C00570004C0057000A\r\nS31500009F4015C0115000000000004542006080182036\r\nS31500009F5006080182006080182002080082006081E5\r\nS31500009F60082006080180110000000000004142049C\r\nS31500009F70208108204208108204208108204608110A\r\nS31500009F808204208118204208108011000000000081\r\nS31500009F900045420540815020540815020540815075\r\nS31500009FA030550C15420140C154205408050011508B\r\nS31500009FB0000000000000430150C05430150C05435A\r\nS31500009FC00150C05430150C05430152805420150829\r\nS31500009FD0054000000000000000000800420010805C\r\nS31500009FE0042001080042001000040001080040009F\r\nS31500009FF01880062001000000000000000045420213\r\nS3150000A000008080202008080202008080A020280806\r\nS3150000A0100202008180202008080011500000000084\r\nS3150000A020004540056001580056001580056000583F\r\nS3150000A0300056001580076001580056001580110073\r\nS3150000A0400000000000C540036000D80036000D8007\r\nS3150000A050036000D80076000D80015000D80036005D\r\nS3150000A0600D800000000000000000000430010C001C\r\nS3150000A070430010C00430010C00630010C0046000EF\r\nS3150000A0800C00430010C000000000000000000000AB\r\nS3150000A09030000C40030000C00030000C000300003C\r\nS3150000A0A0D00024000800030000C0000000000000EB\r\nS3150000A0B00000050131404C50131404C50131404CD9\r\nS3150000A0C050131404C50531004C40131004C00000A1\r\nS3150000A0D0000000000000230568C15A30568C15A305\r\nS3150000A0E00568C15A30568C15A30568C05A30568C7F\r\nS3150000A0F0158000000000000000000000200008405D\r\nS3150000A1000200008000200008800220009000240148\r\nS3150000A1100800020000800000000000000000084463\r\nS3150000A12062111880462111884462111804460111F3\r\nS3150000A1308844601118844621118000000000000048\r\nS3150000A1400000004550115414550115404550115456\r\nS3150000A15004150115404150115404550111400000E9\r\nS3150000A16000000000000008214208508214208508E3\r\nS3150000A17020420850821520854821420C5082142026\r\nS3150000A180850000000000000000000A01028040A0D7\r\nS3150000A1901028040A01028040A00028040A01028057\r\nS3150000A1A040A01028040000000000000000000C037E\r\nS3150000A1B05300D4C035300D4C035300D4C0213009B0\r\nS3150000A1C04C035301D4C035300D40000000000000A0\r\nS3150000A1D00000080972015C80572015C80572015CF1\r\nS3150000A1E080572015C80772015C80572015C00000F3\r\nS3150000A1F0000000000000231848C61031848C61233B\r\nS3150000A2001848C61031840C61231040C01230848C6B\r\nS3150000A210210000000000000000003FFF4FFFD3FFB9\r\nS3150000A220F4FFFD3FFF4FFFD3FFF4FFFD3FFF4FFF5E\r\nS3150000A230D3FFF4FFFD000000000000000000000056\r\nS3150000A2400000000000000000000000000000000008\r\nS3150000A25000000000000000000000000000000000F8\r\nS3150000A26000002CDB0B36C3EDB0B36C2CDB0B36C217\r\nS3150000A270CDB0B36C2CDB0B36C2CDB0B36C00000096\r\nS3150000A280000000000000333C4CCF13F3C4CCF13384\r\nS3150000A2903C4CCF1333C4CCF1333C4CCF1333C4CC3A\r\nS3150000A2A0F10000000000000000003B7E4EDF93B787\r\nS3150000A2B0E4EDF93B7E4EDF9237E48DF93B7848C6F4\r\nS3150000A2C013B1E4EC79000000000000000000010278\r\nS3150000A2D070409C10270409C10270409C1027040995\r\nS3150000A2E0C10270409C10271409C000000000000045\r\nS3150000A2F00000040571015C40571015C40571015C2E\r\nS3150000A30040571015C40571015C40571015C0000078\r\nS3150000A310000000000000020120804820120804828C\r\nS3150000A3200120804820120804820120804820120063\r\nS3150000A330048000000000000000000000600018001B\r\nS3150000A3400600018000600018000600018000600021\r\nS3150000A350180006000180000000000000000008044C\r\nS3150000A36072011C80472011C80472011C804720110D\r\nS3150000A370C80472011C80472811C0000000000000BC\r\nS3150000A3800000000060001800060001800060001850\r\nS3150000A3900006000180006000180006000180000031\r\nS3150000A3A000000000000008042201088042201088F6\r\nS3150000A3B0042201088042201088042201088042609D\r\nS3150000A3C0108000000000000000002A044A8112A04C\r\nS3150000A3D044A8112A044A8112A044A8112A044A81D9\r\nS3150000A3E012A044A8110000000000000008C00C00E4\r\nS3150000A3F0530014C00530014C00530014C005300151\r\nS3150000A4004C00530014C0053001401000000000004D\r\nS3150000A41000C00000400010000400010000400010D1\r\nS3150000A420000400010000400010000440010030005C\r\nS3150000A4300000000008C04002000080002000080064\r\nS3150000A44002000080002000080002000080002000BA\r\nS3150000A450080030000000000008C040046001180039\r\nS3150000A4604600118004600118004600118004600156\r\nS3150000A4701800460011803000000000001001400264\r\nS3150000A48060009800260009800260009800260009F6\r\nS3150000A490800260009800260009820000000000008B\r\nS3150000A4A04045420430810C20430810C20430810C20\r\nS3150000A4B020430810C20430810C20430810C01150FC\r\nS3150000A4C0000000004000000030000C00030000C047\r\nS3150000A4D00030000C00030000C00030000C00030038\r\nS3150000A4E000C00000000000004000020030800C2088\r\nS3150000A4F0030800C20030800C20030800C200308030\r\nS3150000A5000C20030800C00000000000004045420483\r\nS3150000A51060811820460811820460811820460811BF\r\nS3150000A5208204608118204608118011500000000046\r\nS3150000A5304001420020800820020800820020800896\r\nS3150000A5402002080082002080082002080080000007\r\nS3150000A5500000000050014204608118204608118264\r\nS3150000A560046081182046081182046081182046087C\r\nS3150000A5701180000000000000404540045001140016\r\nS3150000A58045001140045001140045001140045001DB\r\nS3150000A590140045001142115000000000480006005A\r\nS3150000A5A04180106004180106004180106004180103\r\nS3150000A5B00600418010600418010000000000000041\r\nS3150000A5C0480002010080402010080402010080407B\r\nS3150000A5D0201008040201008040201008040000003A\r\nS3150000A5E000000000404546035180D46035180D46F2\r\nS3150000A5F0035180D46035180D46035180D460351858\r\nS3150000A6000D401150000000000001460471811C60DD\r\nS3150000A610471811C60471811C60471811C604718160\r\nS3150000A6201C60471811C000000000000040014602EF\r\nS3150000A63071809C60271809C60271809C60271809E2\r\nS3150000A640C60671809C60271809C000000000000043\r\nS3150000A6505045460571815C60571815C60571815CC9\r\nS3150000A66060571815C60571815C60571815C21150E0\r\nS3150000A67000000000400002012080482012080482E9\r\nS3150000A68001208048201208048201208048201208F8\r\nS3150000A6900480000000000000400006006180186190\r\nS3150000A6A0061801860061801860061801860461801C\r\nS3150000A6B018600618018000000000000000456004D4\r\nS3150000A6C078011E00478011E00478011E00478011C2\r\nS3150000A6D0E00078011E00478011C011500000000004\r\nS3150000A6E04001420060801820060801820060801840\r\nS3150000A6F020060801820060801820060801800000FC\r\nS3150000A7000000000040014204208108204208108217\r\nS3150000A7100420810820420810820020810820420877\r\nS3150000A72010800000000000004045420440811020D7\r\nS3150000A730440811020440811020440811020040819F\r\nS3150000A74010204408110011500000000040000300D2\r\nS3150000A75050C01430050C01430050C01430050C01E4\r\nS3150000A760430050C01430050C0140000000000000FA\r\nS3150000A770400008004200108004200108004200103A\r\nS3150000A780800420010800420010800420010000001F\r\nS3150000A7900000000040454202008080202008080298\r\nS3150000A7A00200808020200808020200808020200805\r\nS3150000A7B0080011500000000040014004600118002C\r\nS3150000A7C00600118004600118004600118004600133\r\nS3150000A7D01800460011800000000000004001400201\r\nS3150000A7E06000980026000980026000980026001983\r\nS3150000A7F0800260009800260009800000000000002A\r\nS3150000A8004045600438010E00438010E00438010E14\r\nS3150000A81000438010E00438010E00438010C0115040\r\nS3150000A820000000005000010030400C10030400C17D\r\nS3150000A8300030400C10030400C10030400C1003042B\r\nS3150000A84000C00000000000004000050031400C5030\r\nS3150000A850031400C50031400C50031410C5003140EC\r\nS3150000A8600C50031400C200000000000040454304E1\r\nS3150000A87060C11830460C11830460C11830460C01C3\r\nS3150000A880830460C11830460C11801150000000008E\r\nS3150000A890400140002000080002000080002000085F\r\nS3150000A8A00002000080002000080002000080000076\r\nS3150000A8B000000000400148446211188446211188B6\r\nS3150000A8C04462111884462101884462111884462185\r\nS3150000A8D0118000000000000040454044501114045F\r\nS3150000A8E045011140445011140445010140445011E2\r\nS3150000A8F014044501114011500000000040000820DA\r\nS3150000A9004208108204208108204208108204208117\r\nS3150000A9100820420810820420010000000000000008\r\nS3150000A92000000A01028040A01028040A110280409B\r\nS3150000A930A01028040A01028040A01028040000008C\r\nS3150000A9400000000040454D035340D4D035340D4D32\r\nS3150000A950035340D4D035340D4D035340D4D0353451\r\nS3150000A9600D401150000000004001480472001C8098\r\nS3150000A970472011C80472011C80472011C8047201C7\r\nS3150000A9801C80472011C000000000000000002318B2\r\nS3150000A99048C61231848C61231848C61231848C61F2\r\nS3150000A9A0231848C61231848C4100000000000000C4\r\nS3150000A9B000003FFF4FFFD3FFF4FFFD3FFF4FFFD3E4\r\nS3150000A9C0FFF4FFFD3FFF4FFFD3FFF4FFFD00000044\r\nS3150000A9D00000000000000000000000000000000071\r\nS3150000A9E00000000000000000000000000000000061\r\nS3150000A9F0000000000000000000002CDB0B36C2CD7A\r\nS3150000AA00B0B36C2CDB0B36C2CDB0B36C2CDB0B3683\r\nS3150000AA10C2CDB0B37D000000000000000000333C52\r\nS3150000AA204CCF1333C4CCF1333C4CCF1333C4CCF1ED\r\nS3150000AA30333C4CCF1333C4CCFD00000000000000B3\r\nS3150000AA4000003B7E4EDF93B7E4EDF93B7E4EDF938D\r\nS3150000AA50B7E4EDF93B7E4EDF93B7E4EDF900000075\r\nS3150000AA60000000000000028400A10028400A100235\r\nS3150000AA708400A10028400A10028400A10028400A90\r\nS3150000AA801CC0000000000000000008040001008057\r\nS3150000AA904020100804020100804020100804020132\r\nS3150000AAA0008040201000000000000000000000842C\r\nS3150000AAB000210008400210008400210008402210F6\r\nS3150000AAC008840221008840221000000000000000D7\r\nS3150000AAD00000000400010000400010000400010016\r\nS3150000AAE00040001000040001000040001CC00000EF\r\nS3150000AAF000000000000008800220008800220008F4\r\nS3150000AB00800220000800020000800020CC0800021D\r\nS3150000AB100000000000000000080002000080002085\r\nS3150000AB2000080002000080002000080002000080EB\r\nS3150000AB300020000800020000000000000800088055\r\nS3150000AB4002200088002200088002200088002200DF\r\nS3150000AB500880022000880022000200000000000099\r\nS3150000AB600800080002000080002000080002000023\r\nS3150000AB708000200008000200CC80002000020000B7\r\nS3150000AB800000000008000A8402A100A8402A100A5A\r\nS3150000AB908402A100A8402A100A8402A100A8402A23\r\nS3150000ABA010020000000000000800080402010080F6\r\nS3150000ABB04020100804020100804020100804020111\r\nS3150000ABC00080402010020000000000000800008401\r\nS3150000ABD000210008400210008400210008400210F5\r\nS3150000ABE0008400210008400210020000000000005E\r\nS3150000ABF0081000040001CC0073001CC0073001CC13\r\nS3150000AC000073001CC0073001CC0073001CC2040096\r\nS3150000AC100000000008000084002100084002100027\r\nS3150000AC20840021000840021000840021CC08400264\r\nS3150000AC301CC200000000000000000200008000208E\r\nS3150000AC4000080002000080002000080002000081C9\r\nS3150000AC500020000810000000000000000000008036\r\nS3150000AC60002000080002000080002000080002000A\r\nS3150000AC700080002100080002100000000000000013\r\nS3150000AC80001080000000000000000000000000002E\r\nS3150000AC900000000000000000000000000CC00420BE\r\nS3150000ACA0000000000000000000000000000000009E\r\nS3150000ACB0000000000000000000000000000000008E\r\nS3150000ACC000000000000000003C3C00000000000006\r\nS3150000ACD0000000000000000000000000000000006E\r\nS3150000ACE000000000000F0F00000000000000000040\r\nS3150000ACF0000000000000000000000000000000004E\r\nS3150000AD00000000000000000000000000000000003D\r\nS3150000AD10000000000000000000000000000000002D\r\nS3150000AD20000000000000000000000000000000001D\r\nS3150000AD30000000000000000000000000000000000D\r\nS3150000AD4000000000000000000000000000000000FD\r\nS3150000AD50000000000000000000003FFFFFFFC000F1\r\nS3150000AD600000003FFFFFFFC0000000003FFFFFFFA5\r\nS3150000AD70C0000000000000000000000000003FFFCF\r\nS3150000AD80FFFFC0000000003FFFFFFFC00000000003\r\nS3150000AD903FFFFFFFC00000000000000000000000B1\r\nS3150000ADA000003FFFFFFFC0000000003FFFFFFFC0A5\r\nS3150000ADB0000000003FFFFFFFC00000000000000091\r\nS3150000ADC00000000000003FFFFFFFC0000000003F42\r\nS3150000ADD0FFFFFFC0000000003FFFFFFFC0000000B4\r\nS3150000ADE0000000000000000000003FFFFFFFC00061\r\nS3150000ADF00000003FFFFFFFC0000000003FFFFFFF15\r\nS3150000AE00C0000000000000000000000000003FFF3E\r\nS3150000AE10FFFFC0000000003FFFFFFFC00000000072\r\nS3150000AE203FFFFFFFC0000000000000000000000020\r\nS3150000AE300000028400A10028400A10028400A1003C\r\nS3150000AE4028400A10028400A10028400A10000000D1\r\nS3150000AE500000000000000004000100004000100097\r\nS3150000AE600400010000400010000400010000400042\r\nS3150000AE70100000000000000000000084002100080F\r\nS3150000AE8040021000840021000840021000840021C6\r\nS3150000AE90000840021000000000000000000000044E\r\nS3150000AEA000010000400010000400010000400010F6\r\nS3150000AEB00004000100004000100000000000000037\r\nS3150000AEC0000008800220008800220CC880022000B2\r\nS3150000AED0880022000880022000880022000000006E\r\nS3150000AEE000000000080002000080002000080002A8\r\nS3150000AEF000008000200008000200008000200008FA\r\nS3150000AF0000020000000000000800088002200088FF\r\nS3150000AF10002200088002200088002200088002200B\r\nS3150000AF20008800220002000000000000080008005F\r\nS3150000AF300200008000200CC80002000080002000F3\r\nS3150000AF40080002000080002000020000000000004F\r\nS3150000AF5008000A8402A1CCA8402A100A8402A10093\r\nS3150000AF60A8402A100A8732A100A8732A10020000FE\r\nS3150000AF7000000000080008040201008040201008BC\r\nS3150000AF8004020100804020100804020100804020D5\r\nS3150000AF9010020000000000000800008400200008E5\r\nS3150000AFA040021000840021000840021000800021A9\r\nS3150000AFB00008400210020000000000000810000710\r\nS3150000AFC03001000073001CC0073001CC0073001C68\r\nS3150000AFD0C0040001CC0073001CC204000000000085\r\nS3150000AFE008000084002100084002100084002100AF\r\nS3150000AFF008400210008400210008400210020000F0\r\nS3150000B000000000000000020000800020000800028E\r\nS3150000B01000008000200008000200008000200008D8\r\nS3150000B0200000000000000000000000800020000872\r\nS3150000B03000020000800020000800020000800020BE\r\nS3150000B0400008000200000000000000000010800060\r\nS3150000B05000000000000000000000000000000000EA\r\nS3150000B06000000000000000000000042000000000B6\r\nS3150000B07000000000000000000000000000000000CA\r\nS3150000B08000000000000000000000000000000000BA\r\nS3150000B090000000003C3C0000000000000000000032\r\nS3150000B0A0000000000000000000000000000000009A\r\nS3150000B0B0000F0F000000000000000000000000006C\r\nS3150000B0C0000000000000000000000000000000007A\r\nS3150000B0D0000000000000000000000000000000006A\r\nS3150000B0E0000000000000000000000000000000005A\r\nS3150000B0F0000000000000000000000000000000004A\r\nS3150000B1000000000000000000000000000000000039\r\nS3150000B1100000000000000000000000000000000029\r\nS3150000B1200000000000003FFFFFFFC0000000003FDE\r\nS3150000B130FFFFFFC0000000003FFFFFFFC000000050\r\nS3150000B140000000000000000000003FFFFFFFC000FD\r\nS3150000B1500000003FFFFFFFC0000000003FFFFFFFB1\r\nS3150000B160C0000000000000000000000000003FFFDB\r\nS3150000B170FFFFC0000000003FFFFFFFC0000000000F\r\nS3150000B1803FFFFFFFC00000000000000000000000BD\r\nS3150000B19000003FFFFFFFC0000000003FFFFFFFC0B1\r\nS3150000B1A0000000003FFFFFFFC0000000000000009D\r\nS3150000B1B00000000000003FFFFFFFC0000000003F4E\r\nS3150000B1C0FFFFFFC0000000003FFFFFFFC0000000C0\r\nS3150000B1D0000000000000000000003FFFFFFFC0006D\r\nS3150000B1E00000003FFFFFFFC0000000003FFFFFFF21\r\nS3150000B1F0C000000000000000000000000000000089\r\nS3150000B2000000000000000000000000000000000038\r\nS3150000B2100000000000000000000000000000000028\r\nS3150000B220300020010200000030004249000000000A\r\nS3150000B2300000000000000000000000000000000008\r\nS3150000B24000000000000000000000000000000000F8\r\nS3150000B25000000000000000000000000000000000E8\r\nS3150000B26000000000000000000000000000000000D8\r\nS3150000B27000000000000000000000000000000000C8\r\nS3150000B28000000000000000000000000000000000B8\r\nS3150000B29000000000000000000000000000000000A8\r\nS3150000B2A00000000000000000000000000000000098\r\nS3150000B2B00000000000000000000000000000000088\r\nS3150000B2C00000000000000000000000000000000078\r\nS3150000B2D00000000000000000000000000000000068\r\nS3150000B2E00000000000000000000000000000000058\r\nS3150000B2F00000000000000000000000000000000048\r\nS3150000B3000000000000000000000000000000000037\r\nS3150000B3100000000000000000000000000000000027\r\nS3150000B3200000000000000000000000000000000017\r\nS3150000B3300000000000000000000000000000000007\r\nS3150000B34000000000000000000000000000000000F7\r\nS3150000B35000000000000000000000000000000000E7\r\nS3150000B36000000000000000000000000000000000D7\r\nS3150000B37000000000000000000000000000000000C7\r\nS3150000B38000000000000000000000000000000000B7\r\nS3150000B39000000000000000000000000000000000A7\r\nS3150000B3A00000000000000000000000000000000097\r\nS3150000B3B00000000000000000000000000000000087\r\nS3150000B3C00000000000000000000000000000000077\r\nS3150000B3D00000000000000000000000000000000067\r\nS3150000B3E00000000000000000000000000000000057\r\nS3150000B3F00000000000000000000000000000000047\r\nS3150000B4000000000000000000000000000000000036\r\nS3150000B4100000000000000000000000000000000026\r\nS3150000B4200000000000000000000000000000000016\r\nS3150000B4300000000000000000000000000000000006\r\nS3150000B44000000000000000000000000000000000F6\r\nS3150000B45000000000000000000000000000000000E6\r\nS3150000B46000000000000000000000000000000000D6\r\nS3150000B47000000000000000000000000000000000C6\r\nS3150000B48000000000000000000000000000000000B6\r\nS3150000B49000000000000000000000000000000000A6\r\nS3150000B4A00000000000000000000000000000000096\r\nS3150000B4B00000000000000000000000000000000086\r\nS3150000B4C00000000000000000000000000000000076\r\nS3150000B4D00000000000000000000000000000000066\r\nS3150000B4E00000000000000000000000000000000056\r\nS3150000B4F00000000000000000000000000000000046\r\nS3150000B5000000000000000000000000000000000035\r\nS3150000B5100000000000000000000000000000000025\r\nS3150000B5200000000000000000000000000000000015\r\nS3150000B5300000000000000000000000000000000005\r\nS3150000B54000000000000000000000000000000000F5\r\nS3150000B55000000000000000000000000000000000E5\r\nS3150000B56000000000000000000000000000000000D5\r\nS3150000B57000000000000000000000000000000000C5\r\nS3150000B58000000000000000000000000000000000B5\r\nS3150000B59000000000000000000000000000000000A5\r\nS3150000B5A00000000000000000000000000000000095\r\nS3150000B5B00000000000000000000000000000000085\r\nS3150000B5C00000000000000000000000000000000075\r\nS3150000B5D00000000000000000000000000000000065\r\nS3150000B5E00000000000000000000000000000000055\r\nS3150000B5F00000000000000000000000000000000045\r\nS3150000B6000000000000000000000000000000000034\r\nS3150000B6100000000000000000000000000000000024\r\nS3150000B6200000000000000000000000000000000014\r\nS3150000B6300000000000000000000000000000000004\r\nS3150000B64000000000000000000000000000000000F4\r\nS3150000B65000000000000000000000000000000000E4\r\nS3150000B66000000000000000000000000000000000D4\r\nS3150000B67000000000000000000000000000000000C4\r\nS3150000B68000000000000000000000000000000000B4\r\nS3150000B69000000000000000000000000000000000A4\r\nS3150000B6A00000000000000000000000000000000094\r\nS3150000B6B00000000000000000000000000000000084\r\nS3150000B6C00000000000000000000000000000000074\r\nS3150000B6D00000000000000000000000000000000064\r\nS3150000B6E00000000000000000000000000000000054\r\nS3150000B6F00000000000000000000000000000000044\r\nS3150000B7000000000000000000000000000000000033\r\nS3150000B7100000000000000000000000000000000023\r\nS3150000B7200000000000000000000000000000000013\r\nS3150000B7300000000000000000000000000000000003\r\nS3150000B74000000000000000000000000000000000F3\r\nS3150000B75000000000000000000000000000000000E3\r\nS3150000B76000000000000000000000000000000000D3\r\nS3150000B77000000000000000000000000000000000C3\r\nS3150000B78000000000000000000000000000000000B3\r\nS3150000B79000000000000000000000000000000000A3\r\nS3150000B7A00000000000000000000000000000000093\r\nS3150000B7B00000000000000000000000000000000083\r\nS3150000B7C00000000000000000000000000000000073\r\nS3150000B7D00000000000000000000000000000000063\r\nS3150000B7E00000000000000000000000000000000053\r\nS3150000B7F00000000000000000000000000000000043\r\nS3150000B8000000000000000000000000000000000032\r\nS3150000B8100000000000000000000000000000000022\r\nS3150000B8200000000000000000000000000000000012\r\nS3150000B8300000000000000000000000000000000002\r\nS3150000B84000000000000000000000000000000000F2\r\nS3150000B85000000000000000000000000000000000E2\r\nS3150000B86000000000000000000000000000000000D2\r\nS3150000B87000000000000000000000000000000000C2\r\nS3150000B88000000000000000000000000000000000B2\r\nS3150000B89000000000000000000000000000000000A2\r\nS3150000B8A00000000000000000000000000000000092\r\nS3150000B8B00000000000000000000000000000000082\r\nS3150000B8C00000000000000000000000000000000072\r\nS3150000B8D00000000000000000000000000000000062\r\nS3150000B8E00000000000000000000000000000000052\r\nS3150000B8F00000000000000000000000000000000042\r\nS3150000B9000000000000000000000000000000000031\r\nS3150000B9100000000000000000000000000000000021\r\nS3150000B9200000000000000000000000000000000011\r\nS3150000B9300000000000000000000000000000000001\r\nS3150000B94000000000000000000000000000000000F1\r\nS3150000B95000000000000000000000000000000000E1\r\nS3150000B96000000000000000000000000000000000D1\r\nS3150000B97000000000000000000000000000000000C1\r\nS3150000B98000000000000000000000000000000000B1\r\nS3150000B99000000000000000000000000000000000A1\r\nS3150000B9A00000000000000000000000000000000091\r\nS3150000B9B00000000000000000000000000000000081\r\nS3150000B9C00000000000000000000000000000000071\r\nS3150000B9D00000000000000000000000000000000061\r\nS3150000B9E00000000000000000000000000000000051\r\nS3150000B9F00000000000000000000000000000000041\r\nS3150000BA000000000000000000000000000000000030\r\nS3150000BA100000000000000000000000000000000020\r\nS3150000BA200000000000000000000000000000000010\r\nS3150000BA300000000000000000000000000000000000\r\nS3150000BA4000000000000000000000000000000000F0\r\nS3150000BA5000000000000000000000000000000000E0\r\nS3150000BA6000000000000000000000000000000000D0\r\nS3150000BA7000000000000000000000000000000000C0\r\nS3150000BA8000000000000000000000000000000000B0\r\nS3150000BA9000000000000000000000000000000000A0\r\nS3150000BAA00000000000000000000000000000000090\r\nS3150000BAB00000000000000000000000000000000080\r\nS3150000BAC00000000000000000000000000000000070\r\nS3150000BAD00000000000000000000000000000000060\r\nS3150000BAE00000000000000000000000000000000050\r\nS3150000BAF00000000000000000000000000000000040\r\nS3150000BB00000000000000000000000000000000002F\r\nS3150000BB10000000000000000000000000000000001F\r\nS3150000BB20000000000000000000000000000000000F\r\nS3150000BB3000000000000000000000000000000000FF\r\nS3150000BB4000000000000000000000000000000000EF\r\nS3150000BB5030002001020200003000424000000000D8\r\nS3150000BB6000000000000000000000000000000000CF\r\nS3150000BB7000000000000000000000000000000000BF\r\nS3150000BB8000000000000000000000000000000000AF\r\nS3150000BB90000000000000000000000000000000009F\r\nS3150000BBA0000000000000000000000000000000008F\r\nS3150000BBB0000000000000000000000000000000007F\r\nS3150000BBC0000000000000000000000000000000006F\r\nS3150000BBD0000000000000000000000000000000005F\r\nS3150000BBE0000000000000000000000000000000004F\r\nS3150000BBF0000000000000000000000000000000003F\r\nS3150000BC00000000000000000000000000000000002E\r\nS3150000BC10000000000000000000000000000000001E\r\nS3150000BC20000000000000000000000000000000000E\r\nS3150000BC3000000000000000000000000000000000FE\r\nS3150000BC4000000000000000000000000000000000EE\r\nS3150000BC5000000000000000000000000000000000DE\r\nS3150000BC6000000000000000000000000000000000CE\r\nS3150000BC7000000000000000000000000000000000BE\r\nS3150000BC8000000000000000000000000000000000AE\r\nS3150000BC90000000000000000000000000000000009E\r\nS3150000BCA0000000000000000000000000000000008E\r\nS3150000BCB0000000000000000000000000000000007E\r\nS3150000BCC0000000000000000000000000000000006E\r\nS3150000BCD0000000000000000000000000000000005E\r\nS3150000BCE0000000000000000000000000000000004E\r\nS3150000BCF0000000000000000000000000000000003E\r\nS3150000BD00000000000000000000000000000000002D\r\nS3150000BD10000000000000000000000000000000001D\r\nS3150000BD20000000000000000000000000000000000D\r\nS3150000BD3000000000000000000000000000000000FD\r\nS3150000BD4000000000000000000000000000000000ED\r\nS3150000BD5000000000000000000000000000000000DD\r\nS3150000BD6000000000000000000000000000000000CD\r\nS3150000BD7000000000000000000000000000000000BD\r\nS3150000BD8000000000000000000000000000000000AD\r\nS3150000BD90000000000000000000000000000000009D\r\nS3150000BDA0000000000000000000000000000000008D\r\nS3150000BDB0000000000000000000000000000000007D\r\nS3150000BDC0000000000000000000000000000000006D\r\nS3150000BDD0000000000000000000000000000000005D\r\nS3150000BDE0000000000000000000000000000000004D\r\nS3150000BDF0000000000000000000000000000000003D\r\nS3150000BE00000000000000000000000000000000002C\r\nS3150000BE10000000000000000000000000000000001C\r\nS3150000BE20000000000000000000000000000000000C\r\nS3150000BE3000000000000000000000000000000000FC\r\nS3150000BE4000000000000000000000000000000000EC\r\nS3150000BE5000000000000000000000000000000000DC\r\nS3150000BE6000000000000000000000000000000000CC\r\nS3150000BE7000000000000000000000000000000000BC\r\nS3150000BE8000000000000000000000000000000000AC\r\nS3150000BE90000000000000000000000000000000009C\r\nS3150000BEA0000000000000000000000000000000008C\r\nS3150000BEB0000000000000000000000000000000007C\r\nS3150000BEC0000000000000000000000000000000006C\r\nS3150000BED0000000000000000000000000000000005C\r\nS3150000BEE0000000000000000000000000000000004C\r\nS3150000BEF0000000000000000000000000000000003C\r\nS3150000BF00000000000000000000000000000000002B\r\nS3150000BF10000000000000000000000000000000001B\r\nS3150000BF20000000000000000000000000000000000B\r\nS3150000BF3000000000000000000000000000000000FB\r\nS3150000BF4000000000000000000000000000000000EB\r\nS3150000BF5000000000000000000000000000000000DB\r\nS3150000BF6000000000000000000000000000000000CB\r\nS3150000BF7000000000000000000000000000000000BB\r\nS3150000BF8000000000000000000000000000000000AB\r\nS3150000BF90000000000000000000000000000000009B\r\nS3150000BFA0000000000000000000000000000000008B\r\nS3150000BFB0000000000000000000000000000000007B\r\nS3150000BFC0000000000000000000000000000000006B\r\nS3150000BFD0000000000000000000000000000000005B\r\nS3150000BFE0000000000000000000000000000000004B\r\nS3150000BFF0000000000000000000000000000000003B\r\nS3150000C000000000000000000000000000000000002A\r\nS3150000C010000000000000000000000000000000001A\r\nS3150000C020000000000000000000000000000000000A\r\nS3150000C03000000000000000000000000000000000FA\r\nS3150000C04000000000000000000000000000000000EA\r\nS3150000C05000000000000000000000000000000000DA\r\nS3150000C06000000000000000000000000000000000CA\r\nS3150000C07000000000000000000000000000000000BA\r\nS3150000C08000000000000000000000000000000000AA\r\nS3150000C090000000000000000000000000000000009A\r\nS3150000C0A0000000000000000000000000000000008A\r\nS3150000C0B0000000000000000000000000000000007A\r\nS3150000C0C0000000000000000000000000000000006A\r\nS3150000C0D0000000000000000000000000000000005A\r\nS3150000C0E0000000000000000000000000000000004A\r\nS3150000C0F0000000000000000000000000000000003A\r\nS3150000C1000000000000000000000000000000000029\r\nS3150000C1100000000000000000000000000000000019\r\nS3150000C1200000000000000000000000000000000009\r\nS3150000C13000000000000000000000000000000000F9\r\nS3150000C14000000000000000000000000000000000E9\r\nS3150000C15000000000000000000000000000000000D9\r\nS3150000C16000000000000000000000000000000000C9\r\nS3150000C17000000000000000000000000000000000B9\r\nS3150000C18000000000000000000000000000000000A9\r\nS3150000C1900000000000000000000000000000000099\r\nS3150000C1A00000000000000000000000000000000089\r\nS3150000C1B00000000000000000000000000000000079\r\nS3150000C1C00000000000000000000000000000000069\r\nS3150000C1D00000000000000000000000000000000059\r\nS3150000C1E00000000000000000000000000000000049\r\nS3150000C1F00000000000000000000000000000000039\r\nS3150000C2000000000000000000000000000000000028\r\nS3150000C2100000000000000000000000000000000018\r\nS3150000C2200000000000000000000000000000000008\r\nS3150000C23000000000000000000000000000000000F8\r\nS3150000C24000000000000000000000000000000000E8\r\nS3150000C25000000000000000000000000000000000D8\r\nS3150000C26000000000000000000000000000000000C8\r\nS3150000C27000000000000000000000000000000000B8\r\nS3150000C28000000000000000000000000000000000A8\r\nS3150000C2900000000000000000000000000000000098\r\nS3150000C2A00000000000000000000000000000000088\r\nS3150000C2B00000000000000000000000000000000078\r\nS3150000C2C00000000000000000000000000000000068\r\nS3150000C2D00000000000000000000000000000000058\r\nS3150000C2E00000000000000000000000000000000048\r\nS3150000C2F00000000000000000000000000000000038\r\nS3150000C3000000000000000000000000000000000027\r\nS3150000C3100000000000000000000000000000000017\r\nS3150000C3200000000000000000000000000000000007\r\nS3150000C33000000000000000000000000000000000F7\r\nS3150000C34000000000000000000000000000000000E7\r\nS3150000C35000000000000000000000000000000000D7\r\nS3150000C36000000000000000000000000000000000C7\r\nS3150000C37000000000000000000000000000000000B7\r\nS3150000C38000000000000000000000000000000000A7\r\nS3150000C3900000000000000000000000000000000097\r\nS3150000C3A00000000000000000000000000000000087\r\nS3150000C3B00000000000000000000000000000000077\r\nS3150000C3C00000000000000000000000000000000067\r\nS3150000C3D00000000000000000000000000000000057\r\nS3150000C3E00000000000000000000000000000000047\r\nS3150000C3F00000000000000000000000000000000037\r\nS3150000C4000000000000000000000000000000000026\r\nS3150000C4100000000000000000000000000000000016\r\nS3150000C4200000000000000000000000000000000006\r\nS3150000C43000000000000000000000000000000000F6\r\nS3150000C44000000000000000000000000000000000E6\r\nS3150000C45000000000000000000000000030000001A5\r\nS3150000C46000005BBE30008001000000033000400980\r\nS3150000C47000000000000000000000000000000000B6\r\nS3150000C48000000000000000000000000000000000A6\r\nS3150000C4900000000030008001000000053000A0010F\r\nS3150000C4A000000000300000010000C17D0000000017\r\nS3110000C4B00000000000000000000000007A\r\nS70500110001E8\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/obj/fpgaloader.d", "content": "obj/fpgaloader.d obj/fpgaloader.o: fpgaloader.c ../include/proxmark3.h \\\r\n ../include/at91sam7s512.h ../include/config_gpio.h ../include/usb_cmd.h \\\r\n stdint.h apps.h ../include/common.h ../include/at91sam7s512.h \\\r\n ../include/hitag2.h ../include/mifare.h ../include/common.h util.h \\\r\n string.h\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/obj/hitag2.d", "content": "obj/hitag2.d obj/hitag2.o: hitag2.c ../include/proxmark3.h \\\r\n ../include/at91sam7s512.h ../include/config_gpio.h ../include/usb_cmd.h \\\r\n stdint.h apps.h ../include/common.h ../include/at91sam7s512.h \\\r\n ../include/hitag2.h ../include/mifare.h ../include/common.h util.h \\\r\n string.h\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/obj/iclass.d", "content": "obj/iclass.d obj/iclass.o: iclass.c ../include/proxmark3.h \\\r\n ../include/at91sam7s512.h ../include/config_gpio.h ../include/usb_cmd.h \\\r\n stdint.h apps.h ../include/common.h ../include/at91sam7s512.h \\\r\n ../include/hitag2.h ../include/mifare.h ../include/common.h util.h \\\r\n string.h ../common/iso14443crc.h\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/obj/iso14443.d", "content": "obj/iso14443.d obj/iso14443.o: iso14443.c ../include/proxmark3.h \\\r\n ../include/at91sam7s512.h ../include/config_gpio.h ../include/usb_cmd.h \\\r\n stdint.h apps.h ../include/common.h ../include/at91sam7s512.h \\\r\n ../include/hitag2.h ../include/mifare.h ../include/common.h util.h \\\r\n string.h ../common/iso14443crc.h\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/obj/iso14443a.d", "content": "obj/iso14443a.d obj/iso14443a.o: iso14443a.c ../include/proxmark3.h \\\r\n ../include/at91sam7s512.h ../include/config_gpio.h ../include/usb_cmd.h \\\r\n stdint.h apps.h ../include/common.h ../include/at91sam7s512.h \\\r\n ../include/hitag2.h ../include/mifare.h ../include/common.h util.h \\\r\n string.h ../common/cmd.h ../common/usb_cdc.h ../common/iso14443crc.h \\\r\n iso14443a.h mifaresniff.h crapto1.h mifareutil.h\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/obj/iso14443crc.d", "content": "obj/iso14443crc.d obj/iso14443crc.o: ../common/iso14443crc.c \\\r\n ../common/iso14443crc.h ../include/common.h stdint.h \\\r\n ../include/at91sam7s512.h\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/obj/iso15693.d", "content": "obj/iso15693.d obj/iso15693.o: iso15693.c ../include/proxmark3.h \\\r\n ../include/at91sam7s512.h ../include/config_gpio.h ../include/usb_cmd.h \\\r\n stdint.h util.h ../include/common.h ../include/at91sam7s512.h apps.h \\\r\n ../include/hitag2.h ../include/mifare.h ../include/common.h string.h \\\r\n ../common/iso15693tools.h ../common/cmd.h ../common/usb_cdc.h\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/obj/iso15693tools.d", "content": "obj/iso15693tools.d obj/iso15693tools.o: ../common/iso15693tools.c \\\r\n ../include/proxmark3.h ../include/at91sam7s512.h \\\r\n ../include/config_gpio.h ../include/usb_cmd.h stdint.h\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/obj/legic_prng.d", "content": "obj/legic_prng.d obj/legic_prng.o: ../common/legic_prng.c \\\r\n ../include/legic_prng.h stdint.h\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/obj/legicrf.d", "content": "obj/legicrf.d obj/legicrf.o: legicrf.c ../include/proxmark3.h \\\r\n ../include/at91sam7s512.h ../include/config_gpio.h ../include/usb_cmd.h \\\r\n stdint.h apps.h ../include/common.h ../include/at91sam7s512.h \\\r\n ../include/hitag2.h ../include/mifare.h ../include/common.h util.h \\\r\n string.h legicrf.h ../include/legic_prng.h ../include/crc.h\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/obj/lfops.d", "content": "obj/lfops.d obj/lfops.o: lfops.c ../include/proxmark3.h \\\r\n ../include/at91sam7s512.h ../include/config_gpio.h ../include/usb_cmd.h \\\r\n stdint.h apps.h ../include/common.h ../include/at91sam7s512.h \\\r\n ../include/hitag2.h ../include/mifare.h ../include/common.h util.h \\\r\n ../common/crc16.h string.h\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/obj/mifarecmd.d", "content": "obj/mifarecmd.d obj/mifarecmd.o: mifarecmd.c mifarecmd.h \\\r\n ../include/proxmark3.h ../include/at91sam7s512.h \\\r\n ../include/config_gpio.h ../include/usb_cmd.h stdint.h apps.h \\\r\n ../include/common.h ../include/at91sam7s512.h ../include/hitag2.h \\\r\n ../include/mifare.h ../include/common.h util.h string.h \\\r\n ../common/iso14443crc.h iso14443a.h mifaresniff.h crapto1.h mifareutil.h\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/obj/mifaresniff.d", "content": "obj/mifaresniff.d obj/mifaresniff.o: mifaresniff.c mifaresniff.h \\\r\n ../include/proxmark3.h ../include/at91sam7s512.h \\\r\n ../include/config_gpio.h ../include/usb_cmd.h stdint.h apps.h \\\r\n ../include/common.h ../include/at91sam7s512.h ../include/hitag2.h \\\r\n ../include/mifare.h ../include/common.h util.h string.h \\\r\n ../common/iso14443crc.h iso14443a.h crapto1.h mifareutil.h\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/obj/mifareutil.d", "content": "obj/mifareutil.d obj/mifareutil.o: mifareutil.c ../include/proxmark3.h \\\r\n ../include/at91sam7s512.h ../include/config_gpio.h ../include/usb_cmd.h \\\r\n stdint.h apps.h ../include/common.h ../include/at91sam7s512.h \\\r\n ../include/hitag2.h ../include/mifare.h ../include/common.h util.h \\\r\n string.h ../common/iso14443crc.h iso14443a.h mifaresniff.h crapto1.h \\\r\n mifareutil.h\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/obj/osimage.s19", "content": "S01200006F626A2F6F73696D6167652E73313993\r\nS3150001000008B50B4B0B495A1E581C00238A4202D2D3\r\nS315000100101370031CF6E7084A08499A188A4204D263\r\nS315000100200749C95C01331170F5E706F0D1F9C046FD\r\nS31500010030392A2000142C200000002000382A200034\r\nS30900010040A5271200D7\r\nS31500010048F7B5071C019104F04DFC18240120013C69\r\nS3150001005804F065FC002CF9D1201C04F060FC012099\r\nS3150001006804F05DFC012004F05AFC012004F057FC61\r\nS31500010078012004F054FC201C04F051FC012004F07A\r\nS315000100884EFC012004F04BFC3E1C019AF31B9342E3\r\nS3150001009866DA0025347803232C411C40022C2BD028\r\nS315000100A89C4240D0012C10D0012004F038FC0020DD\r\nS315000100B804F035FC012004F032FC012004F02FFC89\r\nS315000100C8012004F02CFC012026E0201C04F027FC6A\r\nS315000100D8201C04F024FC201C04F021FC002004F060\r\nS315000100E81EFC201C04F01BFC201C04F018FC201C20\r\nS315000100F804F015FC201C2CE0012004F010FC012062\r\nS3150001010804F00DFC012004F00AFC012004F007FCB0\r\nS31500010118012004F004FC002004F001FC012004F095\r\nS31500010128FEFB012015E0012004F0F9FB012004F093\r\nS31500010138F6FB012004F0F3FB012004F0F0FB01209B\r\nS3150001014804F0EDFB012004F0EAFB012004F0E7FBD3\r\nS315000101580020023504F0E3FB082D9BD1013694E714\r\nS31500010168012004F0DCFB012004F0D9FB002004F097\r\nS31500010178D6FB012004F0D3FB18240120013C04F02E\r\nS31500010188CEFB002CF9D1F7BC01BC004707B52623E5\r\nS315000101986A4613700123537068460023032193703E\r\nS315000101A800F09AFE6B46D870000A18710521684658\r\nS315000101B8FFF746FF03B001BC0047F0B58DB00490C8\r\nS315000101C8602010F095FA0022151C101C624B196C60\r\nS315000101D8CC0701D5432159621B6CDF06F6D55E4B68\r\nS315000101E8196A0B061B0E002D16D01C0602D54B42AA\r\nS315000101F81B061B0E99180906090E140602D59B1A29\r\nS315000102081906090E554B1954554B441C9C4205DDDC\r\nS315000102180026301C311C1BE0041C00E0131C0122C3\r\nS3150001022855401540201C1A1CD0E794104B4D0C194B\r\nS315000102382C5D4C4D97007D596C4304321B19402A9D\r\nS31500010248F3D1834207DC031C0131642905D0181C4C\r\nS3150001025800231A1CE9E70E1CF6E700240F2B75D9B3\r\nS3150001026807A8211C142206F0CDFE10360125002709\r\nS3150001027803973B1C9A103949B2188A5C3A499F0080\r\nS3150001028879584A430398043380180390102BF1D107\r\nS31500010298002102910B1C9A009446304F9A10B2180D\r\nS315000102A8B95C314F60464037C7590A1C7A430299EF\r\nS315000102B8043389180291102BEDD100231A1C9700DB\r\nS315000102C8059726489710F119415C28480191059927\r\nS315000102D808580199844667464F430432DB19402A78\r\nS315000102E8EDD1039A029F9000B9008B4202DD834249\r\nS315000102F808DD13E0814205DD07AB1A5D2A430436A2\r\nS315000103081A5500E004366D062D0E01D1013401257A\r\nS31500010318174B9E42ABDD174804F0F0FA012D0CD0BD\r\nS31500010328154B1B68002B03D01448291C04F02CFB21\r\nS3150001033800230722AA425B41E41A0023A34205DAF5\r\nS3150001034807AA9A5C049FFA540133F7E7201C0DB0FB\r\nS31500010358F0BC02BC0847C0460040FDFF142C200033\r\nS31500010368CF070000D8081200D8091200580A12004F\r\nS315000103788F070000A50D1200382A2000B20D1200C1\r\nS3150001038873B5141C061C40200D1C10F0B1F9206829\r\nS31500010398092801DC0A23236000230E4A116CC807C9\r\nS315000103A805D50D49C95C01335162B3420ADA126CAB\r\nS315000103B8D10603D5074A126A0192019A0749084AE2\r\nS315000103C81160EAE722689B18DB002B6073BC01BC4D\r\nS315000103D80047C0460040FDFFCCC82000010000A52B\r\nS315000103E840FDFFFF73B5FFF7D1FE8020000310F033\r\nS315000103F837F9602010F07CF9642006F0FDFC10F056\r\nS3150001040869F9402010F074F9254B18680023033068\r\nS31500010418244A116C141CCD0705D52349C95C01333F\r\nS31500010428516283420AD0126CD60603D51D4A126A56\r\nS315000104380192019A1D491E4A1160E9E7602010F0F0\r\nS3150001044857F90022101C151C236CD90702D5154B28\r\nS3150001045843215962236CDE06F6D5124B196A0B063F\r\nS315000104681B0E002814D01E0602D54B421B061B0E76\r\nS3150001047899180906090E160602D59B1A1906090EB8\r\nS315000104880C4E71550C496B1C8B4206DC1D1C00E099\r\nS315000104981A1C012358401840D6E773BC01BC004713\r\nS315000104A8CCCA20000040FDFFCCC82000010000A5F1\r\nS315000104B840FDFFFF142C2000CF07000038B510F0CF\r\nS315000104C809F9E02010F014F9C82006F095FC8020FF\r\nS315000104D8000310F0C5F8642006F08EFC602010F0C9\r\nS315000104E807F90022101C141C184B196CCD0701D5ED\r\nS315000104F8432159621B6CD906F6D5144B196A0B06AA\r\nS315000105081B0E002814D01D0602D54B421B061B0ED6\r\nS3150001051899180906090E150602D59B1A1906090E18\r\nS315000105280B4D29550B49631C8B4209DC1C1C00E049\r\nS315000105381A1C0123584018400749084B1960D3E78C\r\nS31500010548074804F021FA38BC01BC00470040FDFF0A\r\nS31500010558142C2000571B0000010000A540FDFFFFD9\r\nS31500010568DF0D1200F8B5124C0127802680250423D9\r\nS31500010578BE40AD002763E02026636563636310F020\r\nS31500010588B7F80A2006F038FC8020000310F068F856\r\nS3150001059810F0A0F8602010F0ABF8FA2006F02CFC59\r\nS315000105A804232763666365636363F8BC01BC00477C\r\nS315000105B800F4FFFFF0B54D4C85B001911E1C0021DA\r\nS315000105C8012302910391236380235B002363802324\r\nS315000105D89B00151C0A9A63630423071C63638A42FA\r\nS315000105E803D04348642206F00DFD002D01D0FFF724\r\nS315000105F8B9FF002E4ED104F075F918250120013DE9\r\nS3150001060804F08DF9002DF9D1281C04F088F9012090\r\nS3150001061804F085F9012004F082F9012004F07FF93C\r\nS31500010628012004F07CF9012004F079F9012004F095\r\nS3150001063876F9281C04F073F93E1C019AF31B9342C0\r\nS3150001064814DA002533780120AB4203D104F067F9A7\r\nS31500010658002002E004F063F9012004F060F9013595\r\nS3150001066880235B009D42EDD10136E6E7012004F0C7\r\nS3150001067856F9012004F053F9002004F050F901203D\r\nS3150001068804F04DF918250120013D04F048F9002D23\r\nS31500010698F9D103E0381C0199FFF7D2FC012780261E\r\nS315000106A8BE402763134B666302A9186803AAFFF7BE\r\nS315000106B867FE0A9B0D4D002B08D06F632E630C4D08\r\nS315000106C8281CFFF77AFD0A9A156000E00A980123AB\r\nS315000106D8636380235B00636380239B006363042356\r\nS315000106E8636305B0F0BC02BC0847C04600F4FFFFCF\r\nS315000106F8603A2000CCCA200070B58EB0051C0C1CCF\r\nS3150001070801A80021312206F07DFC032D5EDD267845\r\nS31500010718330703D501A82F4906F0B2FC01A8F30750\r\nS3150001072834D52D4906F0ACFC60780138132826D853\r\nS315000107380FF01AFE0A0D102525252525252525251F\r\nS3150001074825251316191C1F2201A8244919E001A8F9\r\nS31500010758234916E001A8234913E001A8224910E01C\r\nS3150001076801A822490DE001A821490AE001A8214969\r\nS3150001077807E001A8204904E001A8204901E0204931\r\nS3150001078801A806F07DFC01A81E4900E01E4906F0F5\r\nS3150001079877FC201CA91E00F09FFB6419A21E127883\r\nS315000107A803061B0E934209D1013C000A2378000473\r\nS315000107B8000C834202D101A8144901E0144901A899\r\nS315000107C806F05EFC134801A904F0DEF80EB070BC11\r\nS315000107D801BC0047EA0D1200F30D1200FA0D1200D2\r\nS315000107E8050E1200110E12001F0E1200290E12001C\r\nS315000107F8360E1200430E12004D0E1200580E12004C\r\nS31500010808630E1200851712006E0E1200750E120085\r\nS315000108187B0E12009E0E120008B5064B18600028C2\r\nS3150001082801D0054900E00549054804F0ADF808BCC2\r\nS3150001083801BC0047382A20008D141200840E1200CC\r\nS31500010848880E1200F0B58022794D01278026BE4018\r\nS31500010858784C920004232F632E636A63962295B01F\r\nS315000108680021BA406B63201C06F0CCFB0FF032FF67\r\nS31500010878E0200FF03DFFC82006F0BEFA80200003F5\r\nS315000108880FF0EEFE0FF026FF60200FF031FFC820B3\r\nS3150001089806F0B2FA8022920004232F636E630027C2\r\nS315000108A86A636B630E970F97FFF770FC624B0EA98D\r\nS315000108B818680FAAFFF764FD201CFFF77EFC061EC9\r\nS315000108C80B2E0FDDA278E3780D9222790C930B9209\r\nS315000108D86379A2790A930992E379227A08930792AE\r\nS315000108E8647A07E00797089709970A970B970C9771\r\nS315000108F80D973C1C5148311C04F046F84D4D301CEF\r\nS31500010908291CFFF7F9FE301C291C012204F062F8A4\r\nS315000109180B2E0FDD099B0A9A00930B9B01920293FA\r\nS315000109280C9A0D9B039204934548211C079A089B30\r\nS3150001093804F02AF84348002104F026F8424D002025\r\nS31500010948291CFFF7D9FE0122291C002004F042F8D0\r\nS3150001095864353E48002104F017F80020291CFFF7EA\r\nS31500010968CBFE0020291C012204F034F80B2E0EDCE4\r\nS315000109782F4A0123536380235B00536380239B0023\r\nS3150001098853630423536315B0F0BC01BC0047304BD5\r\nS315000109981B68002BECD0002610AD62232B70202398\r\nS315000109A86B700D9B0C9AAB700B9BEA702B710A9AB4\r\nS315000109B8099B6A71AB71089A079B281C0B21EA717E\r\nS315000109C82B726C72AE7200F087FAE872000A28730D\r\nS315000109D80D21281CFFF734FB174B0EA918680FAA1F\r\nS315000109E8FFF7CEFC184D281CFFF7E7FB071E03DCB3\r\nS315000109F80136202ED0D1BBE73A1C1648311C03F02C\r\nS31500010A08C3FF381C291CFFF777FE0122381C291C55\r\nS31500010A1803F0E0FF6A782B7812021A43AB781B04BD\r\nS31500010A281A43EB781B061A430B4B9A42E0D19FE710\r\nS31500010A3800F4FFFF603A2000CCCA2000A10E120084\r\nS31500010A48C70E1200F60E1200C43A20001A0F120041\r\nS31500010A58382A20003B0F120001011607F0B5AC4CED\r\nS31500010A68012780268025BE40AD000420642295B06A\r\nS31500010A7800212763266365636063A64806F0C2FA08\r\nS31500010A880FF028FEE0200FF033FEC82006F0B4F977\r\nS31500010A98802000030FF0E4FD0FF01CFEC82006F0CD\r\nS31500010AA8ABF90421676360206663256361630FF010\r\nS31500010AB81FFE0022161C101C974B196CCC0701D57A\r\nS31500010AC8432159621B6CDF06F6D5934B196A0B064F\r\nS31500010AD81B0E002E16D01C0602D54B421B061B0EFA\r\nS31500010AE899180906090E140602D59B1A1906090E44\r\nS31500010AF88A4D8B4B441C29549C4205DD00200C90E1\r\nS31500010B08011C23E0041C00E0131C01225640164078\r\nS31500010B18201C1A1CD0E79600B446804F96108E19F1\r\nS31500010B28BF5D804C0B9767463E590B9FB446664698\r\nS31500010B387E4304329B19402AEDD10C9A934208DC74\r\nS31500010B48131C794A0131914205D00C9300231A1CD2\r\nS31500010B58E1E7081CF5E700260F2B00D8ABE01030BB\r\nS31500010B680FAC0B90311C201C142206F04BFA0127FE\r\nS31500010B7800230C930B999A108A1868498A5C6B4969\r\nS31500010B88980041584A430C98043380180C90102B4E\r\nS31500010B98F0D100218C460B1C9A000B980D929910E6\r\nS31500010BA85E4A4118515C61480A910D9940300858CE\r\nS31500010BB80A990A1C424304339444102BECD10022AF\r\nS31500010BC809920B98911041185448405C0A9058486C\r\nS31500010BD893001B580A98011C5943099B04325B1858\r\nS31500010BE80993402AEDD10C98820009986346990029\r\nS31500010BF8884201DD904214DC0B9B04330B93181CCD\r\nS31500010C08914203DD0FAB9A5D3A439A557B061F0E57\r\nS31500010C1801D101360127474B9842A9DD464803F021\r\nS31500010C286DFE012F02D0454803F068FE0023B3424A\r\nS31500010C3808DA3A4F42480FA9FA18595C1218117086\r\nS31500010C480133F4E7002E36D03223A3704B23E37029\r\nS31500010C5803232371012363711023E37105230027FD\r\nS31500010C682372201CE0230A21637227706770A7711B\r\nS31500010C7800F032F9A072000AE0720C21201CFFF77D\r\nS31500010C88DFF9304B80201C680FF032FD22490B6CCE\r\nS31500010C98DA0705D52C4BDA5D01374A62A7420ADA2B\r\nS31500010CA81D48036CD90602D5036A0F930F9B274A81\r\nS31500010CB8274B1A60EAE7224B2649EA5C695C264B10\r\nS31500010CC8EB5C00912549695C0191E5210901695CA3\r\nS31500010CD802912349695C03912249695C049122497D\r\nS31500010CE8695C05912149695C21480691311C03F02B\r\nS31500010CF84BFE074A0123536380235B00536380231A\r\nS31500010D089B0053630423536315B0F0BC01BC004731\r\nS31500010D1800F4FFFF603A20000040FDFF142C20007C\r\nS31500010D281F4E0000D8081200384A0000D8091200E0\r\nS31500010D38580A12008F070000A50D1200640F120051\r\nS31500010D484C0E0000CCCA2000CCC82000010000A52A\r\nS31500010D5840FDFFFF4E0E00004D0E00004F0E000035\r\nS31500010D68510E0000520E0000530E0000540E0000F2\r\nS31500010D78960F1200F0B589B003AC061C0294FFF772\r\nS31500010D88F1FB26232370002501230321201C637010\r\nS31500010D98A57000F0C1F802AF011C2A1C331C00978C\r\nS31500010DA8201CFFF707FC1D4A1D4B13600B2808DDA5\r\nS31500010DB80299281C023100F0BCF8011C194803F0FD\r\nS31500010DC8E3FD36232370002501236370E5700421B2\r\nS31500010DD8201CA57000F0A0F80022011C331C009706\r\nS31500010DE8201CFFF7E7FB0E4A0C4B1A600B2809DD9E\r\nS31500010DF802990020023100F09CF8291C021C0A48BD\r\nS31500010E0803F0C2FD802301355B009D42DFD107480F\r\nS31500010E1803F0BAFD09B0F0BC01BC004740FDFFFF75\r\nS31500010E28010000A5D50F1200E20F1200F00F120003\r\nS31500010E38F0B51E1C234B87B00593234B141C1A6867\r\nS31500010E48051C03911F1C002A07D0204803F09CFDAE\r\nS31500010E58281C311C012203F0BDFD00239C4200D051\r\nS31500010E6805AB0093291C301C0122039BFFF7A2FB4B\r\nS31500010E78051C002C22D0164C80235B0023633023EB\r\nS31500010E88011E994200DD191C059A00920022019360\r\nS31500010E98FF20131C06F0F6FB80235B0063633B68A7\r\nS31500010EA8002B0BD00B4803F06FFD281C0599FFF7A3\r\nS31500010EB823FC281C0599012203F08CFD07B0F0BC20\r\nS31500010EC801BC0047142C2000382A20000710120004\r\nS31500010ED800F4FFFF0C10120030B50D4B021C141A5A\r\nS31500010EE88C420EDA14786340082401251D405B08FC\r\nS31500010EF8002D01D0074D6B40013C002CF5D1013284\r\nS31500010F08EDE7DB431804000C30BC02BC0847C046B9\r\nS31500010F18FFFF00000884000038B50C1C051CFFF70C\r\nS31500010F28DBFF28552D19000A6870A01C38BC02BCC5\r\nS31500010F38084710B5041C86B0002800D10B4C487927\r\nS31500010F48CA798B79009008790190C87802908878D7\r\nS31500010F580390487804900978201C0591044905F006\r\nS31500010F682CFE201C06B010BC02BC08473C2A2000F7\r\nS31500010F78CD0E12000000000030B5002822D10A6803\r\nS31500010F88531C0B60454B01249C540A6815190D60C6\r\nS31500010F989C540A6814190C6098540A68541C0C600D\r\nS31500010FA898540A68541C0C6098540A68541C0C60BE\r\nS31500010FB898540A68541C0C6098540A68541C0C60AE\r\nS31500010FC8985467E008282DD106200A68531C0B603F\r\nS31500010FD8324B01249C540A6815190D609C540A6801\r\nS31500010FE814190C60D418002222700C68651CE418C8\r\nS31500010FF80D6022700C68651CE4180D6022700C687F\r\nS31500011008651CE4180D6022700C68651CE4180D60F7\r\nS3150001101822700C680138651CE3180D601A7090423D\r\nS31500011028D3D137E00A2835D105200C68631C0B603B\r\nS315000110381A4B01221A550C68A5180D601A550C6829\r\nS31500011048A5180D601A550A68541C0C60D41800229C\r\nS3150001105822700C68651CE4180D6022700C68651C0A\r\nS31500011068E4180D6022700C68651CE4180D60227086\r\nS315000110780C68651CE4180D6022700C68651CE41880\r\nS315000110880D6022700C680138651CE3180D601A7032\r\nS315000110989042CAD130BC01BC0047C046142C20007E\r\nS315000110A810B5194C86B0201C0021184A05F0AAFF74\r\nS315000110B80023201C164A116CCC0704D54321516222\r\nS315000110C8144904240C63126CD106F3D5104A126A2A\r\nS315000110D8C254104A042151630C4A01339342E9D19F\r\nS315000110E8C478017842788378009404790194447924\r\nS315000110F8029484790394C0790490074803F044FC68\r\nS3150001110806B010BC01BC0047142C2000409C00000E\r\nS315000111180040FDFF00F4FFFF11101200F7B5071C90\r\nS31500011128E0201C1C009101920FF0E2FA2B4805F011\r\nS3150001113863FE201C05F084FF201801380378682B0C\r\nS3150001114844D18020800158210FF0F2FA012532207E\r\nS3150001115805F052FEFA20C00005F04EFE0FF0BAFA6D\r\nS315000111682378202293431E4EE020002B1AD00FF03D\r\nS31500011178BFFA0423381C736305F014FE802080012E\r\nS315000111885821002D00D15F210FF0D2FA04233363D1\r\nS315000111982378302B01D1009800E0019805F002FE72\r\nS315000111A80134DDE70FF0A4FA0423381C736305F054\r\nS315000111B8F9FD802080015821002D00D15F210FF013\r\nS315000111C8B7FAFFF76DFFF7BC01BC00478020800125\r\nS315000111D85F210FF0ADFA0025B9E7C046C409000042\r\nS315000111E800F4FFFFF8B5134C8025AD02071C8720D4\r\nS315000111F82563800005F0D6FD6563072580263B1C1F\r\nS31500011208B6022B416663DA0701D50B4801E0872050\r\nS31500011218400005F0C7FD2663962005F0C3FD013D94\r\nS31500011228ECD280239B026363D22005F0BBFDF8BC98\r\nS3150001123801BC004700F4FFFF8A020000F7B5C02091\r\nS315000112480FF056FA0021254A254805F0DBFE254D03\r\nS315000112588023DB026B60244C2B6780278023BF0227\r\nS315000112681B022F602F6123600223FF3323600C23A7\r\nS31500011278636000269F23266132206361A661E661C9\r\nS3150001128805F0BAFD04236F632B63184F01F072FB57\r\nS3150001129813490190236CDA0606D5134B1B6A8B5545\r\nS315000112A8134B01369E4203DC124A134B1A60F1E7CF\r\nS315000112B801F060FB019BC41A01F05CFB211C021CB6\r\nS315000112C80E4803F061FB04236B6380239B026B606A\r\nS315000112D8C023DB022B67F7BC01BC0047409C00001A\r\nS315000112E8142C200000F4FFFF0040FDFF85002000BC\r\nS315000112F83F9C0000010000A540FDFFFF4D101200B4\r\nS3150001130808B5002803D080208001582102E08020FA\r\nS3150001131880015E210FF00CFAFFF790FF08BC01BCB3\r\nS315000113280047F7B580205E2180010FF001FAC02041\r\nS315000113380FF0DEF9FFF782FFE0200FF0D9F9002060\r\nS31500011348011C051C021C061C031C041C4A4FEF1930\r\nS3150001135801973F787F2F32D9019F7F783F063F1645\r\nS31500011368002F2CDD01310F2929DDF10752080A4327\r\nS315000113787608D9070E435B08E1070B436408281A68\r\nS31500011388F8280CD90E21FF31884204D90022161CEF\r\nS31500011398131C141C05E0802109060C4301E0E3280F\r\nS315000113A8F4D95002FC21400AC903884205D1200A12\r\nS315000113B8170C78400106090E0AD0281C00212F4F68\r\nS315000113C80135BD42C2D12E48814201D02D484DE09A\r\nS315000113D8120E35021543360E1A02164322021B0E49\r\nS315000113E8171C1F4323040AD5240C27486C4003F015\r\nS315000113F885FA640401D0254802E0254800E025481D\r\nS3150001140803F07CFA2906090E00200FF0D5F9290AFE\r\nS315000114180906090E0FF0D0F9290C0906090E0FF075\r\nS31500011428CBF9290E0FF0C8F93106090E0FF0C4F9E8\r\nS31500011438310A0906090E0FF0BFF9310C0906090E22\r\nS315000114480FF0BAF9310E0FF0B7F93F043F0C041C3F\r\nS31500011458311C11482A1C3B1C03F096FABC4204D0E5\r\nS315000114680E48211C03F090FA02E00D4803F046FAF3\r\nS31500011478F7BC01BC0047C046142C20003F9C000065\r\nS315000114880B0F0000601012007D1012009910120057\r\nS31500011498B0101200CC101200E5101200041112004F\r\nS315000114A825111200F7B50B1C23331B18061C8020C7\r\nS315000114B880010D1C5E2101933B4F0FF039F9C020C5\r\nS315000114C80FF016F901233B6380239B023B603B61C6\r\nS315000114D80A24F020FFF786FE0120FFF783FE0F207E\r\nS315000114E8FFF780FE0120FFF77DFE0120FFF77AFE58\r\nS315000114F80F20FFF777FE0B20FFF774FE0020FFF79A\r\nS3150001150871FE0620FFF76EFE8020FFF76BFE0220B4\r\nS31500011518FFF768FE0820FFF765FE0120FFF762FE68\r\nS315000115280820FFF75FFE1A20FFF75CFE1A20FFF777\r\nS3150001153859FE1A20FFF756FE1A20FFF753FE2D20F3\r\nS31500011548FFF750FE642005F057FCF020FFF74AFE2E\r\nS315000115580720FFF747FE0520FFF744FE0120FFF7A6\r\nS3150001156841FE0720FFF73EFE0F20FFF73BFE300640\r\nS31500011578000EFFF737FE2806000EFFF733FE019B24\r\nS315000115881806000EFFF72EFEFA208000013C05F032\r\nS3150001159833FC002C9DD101237B63044803F0AEF98B\r\nS315000115A8F7BC01BC0047C04600F4FFFF3711120023\r\nS315000115B8F7B501902020264D0F1C161C0FF098F840\r\nS315000115C8C0239B022B6080239B022B6180235B0235\r\nS315000115D86B610024EA6B1E4BD1030CD4DB6B190239\r\nS315000115E805D41C4803F08AF9F7BC01BC00471A4A1E\r\nS315000115F81A4B1A60EEE7002E01D004221A63184B23\r\nS315000116081A5D80239B02002A01D02B6300E06B63DD\r\nS31500011618002E08D004236B6305E0DB6B1A02E0D5C4\r\nS315000116280D4A0E4B1A60E96B80225202084B0A409A\r\nS31500011638F3D1019901348C42CCD1141C002FC9D0A5\r\nS31500011648802292025A63381C05F0ACFBC2E7C046F9\r\nS3150001165800F4FFFF3C111200010000A540FDFFFF49\r\nS31500011668142C20007047F0B5404B85B0061C0020AD\r\nS315000116780191151C03909E4203DD3D4803F03EF996\r\nS3150001168870E003A9FFF778FC082003A9FFF774FCAB\r\nS31500011698082003A9FFF770FC082003A9FFF76CFCD3\r\nS315000116A80A2003A9FFF768FC0A2003A9FFF764FCCF\r\nS315000116B80A2003A9FFF760FC082003A9FFF75CFCD1\r\nS315000116C80A2003A9FFF758FC2A4F2B4B3B600B2432\r\nS315000116D803232340032B03D1002003A9FFF74CFC66\r\nS315000116E8331C2341DA0705D50A2003A9FFF744FC71\r\nS315000116F8082004E0082003A9FFF73EFC0A2003A9F5\r\nS31500011708FFF73AFC013CE3D21B4B3B601F24032342\r\nS315000117182340032B03D1002003A9FFF72DFC019BCE\r\nS315000117282341DA0705D50A2003A9FFF725FC082076\r\nS3150001173804E0082003A9FFF71FFC0A2003A9FFF705\r\nS315000117481BFC013CE3D2002D02D00C4B01221A638B\r\nS31500011758039800212A1CFFF72BFF002D02D0074B07\r\nS3150001176801225A6305B0F0BC01BC0047FF0F000017\r\nS315000117784411120040FDFFFF010000A500F4FFFF20\r\nS31500011788F0B58BB004908020089180015F21099201\r\nS3150001179807930EF0CDFF8020400300240EF060FF72\r\nS315000117A8322005F029FB0EF095FF02940394059467\r\nS315000117B8271CB54BB54807990360B54D002901D0DB\r\nS315000117C801232B63EB6B1A020AD4B24803F096F88D\r\nS315000117D8079B002B00D152E1AD4B01225A634EE122\r\nS315000117E8AD488021AD4A05F00DFC0023AC4A116CC9\r\nS315000117F8C80706D5432151620799002901D004215A\r\nS315000118082963126CD006F1D5A54A126AA2481206B6\r\nS31500011818120E19180A707E2A01D8002200E0012248\r\nS315000118280A7007990133002901D004226A639B498A\r\nS315000118388B42DBD1027843789A4200D20127934B37\r\nS31500011848914A00201A6006900123934A9818451E6A\r\nS315000118582D78007885420ED20698DF1B3F0682183E\r\nS315000118683F0E17700120082F00D900201070069A24\r\nS31500011878013206921F1C01338B42E6D18348824B03\r\nS31500011888854E036000253778281C013E824B069950\r\nS31500011898F31A01338B4234DA73780130BB422DD007\r\nS315000118A837780621002F00D105210EF049FF0428BB\r\nS315000118B822D8794B0EF058FD0303060C15005F5527\r\nS315000118C8013519E05F5531786A1C9954023513E0E0\r\nS315000118D85F553078591C48553178AA1C99540335F7\r\nS315000118E80AE05F5531785A1C51553078991C48558C\r\nS315000118F83178EA1C995404357378002001361F1C87\r\nS31500011908C4E7614A614B1A600026AB1F9E4200DBA1\r\nS31500011918B1E0614B9A5D002A34D05A1C925D002AC7\r\nS3150001192830D09A1C925D002A2CD0DA1C925D002ACE\r\nS3150001193828D11A1D925D002A24D105339B5D002BFF\r\nS3150001194820D1029B03980343063623431ED063081E\r\nS315000119581B041B0C002807D0009352480399029ACE\r\nS31500011968231C03F011F804E04F480299221C03F0E6\r\nS315000119780BF80499002938D0029A089B09981A602D\r\nS3150001198804607CE00599002933D002E00122059222\r\nS315000119981C1C414B9A5D01339B5D002A0DD0002B1F\r\nS315000119A81BD102990398CA0F43001A4303924B00AD\r\nS315000119B8E20F1A430292640015E0002B0FD0039A36\r\nS315000119C802985300C20F1A4303924300E20F1A43C7\r\nS315000119D86400012302921C4305E0002400E01C1C5C\r\nS315000119E8029403940594013603E0049C029403943B\r\nS315000119F80594294B9A5D002A3BD05A1C925D002A10\r\nS31500011A0837D09A1C925D002A33D0DA1C925D002ADF\r\nS31500011A182FD11A1D925D002A2BD105339B5D002B10\r\nS31500011A2827D1029B063623431AD0630803991B0460\r\nS31500011A381B0C002906D000931A48029A231C02F0AF\r\nS31500011A48A3FF04E018480299221C02F09DFF049A9C\r\nS31500011A58002A0AD0029B0898099903600C600EE0D7\r\nS31500011A6801221C1C0293059203E0049C0294039430\r\nS31500011A780594013649E7044B0448036099E60BB01F\r\nS31500011A88F0BC01BC0047C046010000A540FDFFFFB0\r\nS31500011A9800F4FFFF3C111200142C2000409C0000AA\r\nS31500011AA80040FDFF601112007811120010B5041CE8\r\nS31500011AB8802080015F210EF03BFE9020002C01D092\r\nS31500011AC8C820400005F06EF9E0200EF011FEA020B6\r\nS31500011AD805F068F910BC01BC0047F7B5071C802062\r\nS31500011AE880010E1C5F211C1C01920EF021FE96201E\r\nS31500011AF805F082F9E0200EF0FBFDFA2005F052F917\r\nS31500011B080120FFF7D3FF0020FFF7D0FF012C06D0F5\r\nS31500011B1800208025FFF7CAFF20242D060BE080252B\r\nS31500011B2820242D060198013C2840FFF7BFFF6D08C8\r\nS31500011B38002CF7D1ECE7381C2840013CFFF7B6FF2B\r\nS31500011B486D08002CF7D103240425301C2840013CDC\r\nS31500011B58FFF7ACFF6D08002CF7D180205F218001CB\r\nS31500011B680EF0E6FD142005F047F9E0200EF0C0FD61\r\nS31500011B78F7BC01BC0047F7B52E4D00900191171C23\r\nS31500011B8880212D4A281C05F03DFA802040032B4C64\r\nS31500011B980EF066FD04260EF09DFD80205F21800172\r\nS31500011BA826630EF0C5FD962005F026F9E0200EF015\r\nS31500011BB89FFDFA2005F0F6F80120FFF777FF0020D0\r\nS31500011BC8FFF774FF012F07D18024240601982040CE\r\nS31500011BD8FFF76CFF6410F9E70020FFF767FF03259D\r\nS31500011BE80098013D3040FFF761FF7610002DF7D1CF\r\nS31500011BF8802080015F210EF09BFD114B1A6CD107E5\r\nS31500011C0801D543225A621B6CDA06F6D50C4B0949F3\r\nS31500011C181B6A4B55084B01359D42EED1E0200EF06B\r\nS31500011C2867FD04236363074802F068FEF7BC01BC3D\r\nS31500011C380047C046142C2000409C000000F4FFFF1A\r\nS31500011C480040FDFF8C11120038B5224D224A802131\r\nS31500011C58281C05F0D7F980204003204C0EF000FD22\r\nS31500011C680EF038FD0423802023635F2180010EF0E6\r\nS31500011C785FFD962005F0C0F8E0200EF039FDFA2048\r\nS31500011C8805F090F80120FFF711FF0120FFF70EFF7D\r\nS31500011C98802080015F210EF04BFD0023104A116C54\r\nS31500011CA8C80701D543215162126CD106F6D50C4AF3\r\nS31500011CB8126AEA54084A01339342EFD1E0200EF042\r\nS31500011CC817FD04236363074802F018FE38BC01BCFC\r\nS31500011CD80047C046142C2000409C000000F4FFFF7A\r\nS31500011CE80040FDFF8C111200F0B587B0041C944624\r\nS31500011CF80593002B79D0754B984216D8020301D467\r\nS31500011D08734B00E0734B1020660300D5202018435F\r\nS31500011D180423A70300D5082318430123E20300D5AA\r\nS31500011D280223184300250F2301E06B48C8E001226E\r\nS31500011D38171C9F405E003C4200D0B618B2401543BE\r\nS31500011D48013BF4D20F2300241F1C01221037161C55\r\nS31500011D58BE40371C5E00394200D0B618B240144363\r\nS31500011D68013BF1D2002702970F230122171C9F403E\r\nS31500011D785E00394205D0029FB618B2401743029752\r\nS31500011D8803E0B240029E16430296013BEDD20027BC\r\nS31500011D9803970F231E1C01221036111CB1400E1C7D\r\nS31500011DA867465900374205D0039E89188A4016436B\r\nS31500011DB8039603E0039F8A4017430397013BE9D241\r\nS31500011DC80F23002601225F00111C019799406746DF\r\nS31500011DD80F4202D00199891800E001998A401643F9\r\nS31500011DE8013BEFD20627049735E03C4B994201D9CE\r\nS31500011DF83B4865E0E8200B2340050122151C9D4060\r\nS31500011E085C00294200D0A418A2401043013BF4D239\r\nS31500011E180F2300251C1C01221034161CA6406746F8\r\nS31500011E285900374200D089188A401543013BF1D23F\r\nS31500011E380F2300240122161C9E406746590037428B\r\nS31500011E4800D089188A401443013BF3D2032604962D\r\nS31500011E58002603960296234F00220421131C396398\r\nS31500011E680121FFF73AFE0022131C281C0221FFF765\r\nS31500011E7834FE0022131C201C0321FFF72EFE059AAF\r\nS31500011E88002A11D00022131C02980421FFF725FE0F\r\nS31500011E980022131C03980521FFF71FFE0022301CA0\r\nS31500011EA80621131CFFF719FE049E0F480021730132\r\nS31500011EB818430A1C0B1CFFF710FE04237B630B480F\r\nS31500011EC802F01CFD07B0F0BC01BC0047FFFF0F0084\r\nS31500011ED840A9961D80A9961D92111200FF0F0000B8\r\nS31500011EE84411120000F4FFFF007010008C1112005B\r\nS31500011EF8F0B589B002900C1C002600270023301C7F\r\nS31500011F08391C0125801979411F2B05DC15402E1C2A\r\nS31500011F1806430F1C520804E025402E1C06430F1CDD\r\nS31500011F2864080133282BEAD100215A4D584C0091F7\r\nS31500011F380123009833409C4680070DD1009A002A58\r\nS31500011F480FD0221C2B1CC81712196B410C1C051C1F\r\nS31500011F5814431D43614600E059400098032805DCF7\r\nS31500011F6800E0191C009A930062460AE000980323D0\r\nS31500011F7803409B0010226846D21812586046019207\r\nS31500011F884240103368461A50221C2B1C12196B4109\r\nS31500011F981D1C64467B081443FA071F1C009B9446C4\r\nS31500011FA801337208664616430093282BC0D1221CBA\r\nS31500011FB82B1CC81712196B410C1C051C14431D4315\r\nS31500011FC80021221C2B1C12196B41102464186D4622\r\nS31500011FD86059C617041C351C043114431D431029C6\r\nS31500011FE8EFD1029824196D41002801D02A4900E051\r\nS31500011FF82A492B482B4F02F0C7FC002204233B63D6\r\nS31500012008281C131C0121FFF768FD0022131C201C44\r\nS315000120180221FFF762FD029A002A20D01604360E25\r\nS315000120282148311C02F0B0FC102E12D002D8002E25\r\nS3150001203804D006E0202E09D0402E02D1A0235B034E\r\nS3150001204809E01A48311C02F09FFC1BE080231B03A0\r\nS3150001205801E08023DB0216480021184301E01548F8\r\nS3150001206802990B1C0A1CFFF738FD04237B63029BAC\r\nS31500012078002B01D0084900E008490F482A1C231CF7\r\nS3150001208802F082FC09B0F0BC01BC0047C046C0465C\r\nS31500012098FF01000000000000AE111200B411120089\r\nS315000120A8BA11120000F4FFFFD5111200E411120053\r\nS315000120B84080000004F00100FB111200002210B557\r\nS315000120C8131C0C1C0121FFF708FD0022201C131C00\r\nS315000120D80221FFF702FD00210A1C0B1C0448FFF729\r\nS315000120E8FCFC044802F00AFC10BC01BC0047C046CF\r\nS315000120F8401008008C11120070B5151C00220E1C28\r\nS315000121081C1C0121131CFFF7E8FC0022301C131CC0\r\nS315000121180221FFF7E2FC0022281C131C0321FFF70A\r\nS31500012128DCFC0022201C131C0421FFF7D6FC00222C\r\nS315000121380498131C0521FFF7D0FC00220598131CEF\r\nS315000121480621FFF7CAFC00220698131C0721FFF790\r\nS31500012158C4FC00210A1C0B1C0448FFF7BEFC0448FA\r\nS3150001216802F0CCFB70BC01BC0047C046E010080079\r\nS315000121788C111200F0B5E5B003900020FFF7C0F806\r\nS315000121885F4B59781A7891420DD90221581802786D\r\nS3150001219801380078904201D3C02A12DC594A01312C\r\nS315000121A89142F3D10DE002215818027801380078DE\r\nS315000121B8904201D83F2A06DD524A01319142F3D1B4\r\nS315000121C801E0002500E00125002400944B1C201C99\r\nS315000121D8221C4D4FBB4200DD87E04C4EF75C02974F\r\nS315000121E8371C0137B446FF5C029E0197BE4203D9EC\r\nS315000121F8012D01D1C02F07DC029F019EB74265D28E\r\nS31500012208002D62D13F2E61DC591A0D1C103D0F2994\r\nS3150001221801DC10256D1A072D05DC1D1A181C8D42C7\r\nS3150001222849D160330BE00D1C203D1F2901DC202517\r\nS315000122386D1A072D10DC1D1A8D4204D15033FF3358\r\nS31500012248802A35D113E0009F012F4BD1002624A9FE\r\nS315000122588E54013200962EE04039CD17491969404E\r\nS31500012268072928DC012524A98D54521923E02101C7\r\nS3150001227804AD681824AA0021D57996796D00AD199F\r\nS3150001228856796D00AD1916796D00AD19D6786D00C0\r\nS31500012298AD1996786D00AD1956786D00AD19167899\r\nS315000122A86D00AD194554013108321029E4D10134C4\r\nS315000122B800200090021C654601356646F15CEF5C1C\r\nS315000122C800258F426D41191C00E00125FF277F4239\r\nS315000122D8BF187E1EB74102977F423A40042C04D0AC\r\nS315000122E8013376E701270097E5E72201039804A958\r\nS315000122F804F07CFE201C65B0F0BC02BC0847C04651\r\nS31500012308142C2000409C00003F9C0000132C200048\r\nS3150001231870B5124E0822311C041C04F07FFE251CE0\r\nS315000123280935002808D1311C0931281C072204F077\r\nS3150001233875FE012300280DD0311C0931281C0722FE\r\nS3150001234804F06CFE002801D0002303E0E379002B9A\r\nS31500012358FAD10123181C70BC02BC0847580B12009D\r\nS31500012368827A031C0020824211D1DA7A82420ED186\r\nS315000123781A7B82420BD15A7B824208D1997B7F22F2\r\nS315000123880A40092A03DCDB7B09229A42404170474D\r\nS31500012398F0B5C9B00021882226A804F033FE002230\r\nS315000123A815210823149113920F93151C171C00214C\r\nS315000123B8402216A804F026FE16A8FFF7DBFE13999D\r\nS315000123C843424341C918119013910A2900D092E05A\r\nS315000123D8002F01D1AB488BE0AB4802F0D5FAAB48E8\r\nS315000123E802F0D2FA49E0002D00D1B3E000231093A0\r\nS315000123F8109B11998B4200DB36E1109916AA0B0145\r\nS31500012408A349D2181592101C1131102204F006FEA8\r\nS31500012418002800D124E100231293129A1121514375\r\nS3150001242826AB59180B7C012B00D012E11598102206\r\nS3150001243804F0F4FD002800D00BE1109D129C013D2B\r\nS31500012448013C002D00DADFE0611C00D10F9C11264A\r\nS31500012458664326AA9619337C002B00D0D2E016AB28\r\nS315000124682901C918301C102204F0C0FD0123337458\r\nS315000124780F99FF188F4200D0C4E0864E301C02F037\r\nS3150001248883FA854802F080FA301C02F07DFA26AC00\r\nS3150001249800250F998D422ADA237C012B20D1E07879\r\nS315000124A821786278A378009020790190607902906A\r\nS315000124B8A0790390E0790490207A0590607A0690D5\r\nS315000124C8A07A0790E07A0890207B0990607B0A90B1\r\nS315000124D8A07B0B90E07B0C90704802F055FA03E064\r\nS315000124E86F48291C02F050FA01351134D1E7301C26\r\nS315000124F802F04AFAC2E0149A013A1492002A00D16B\r\nS315000125086AE716AC0026119A964200DB6BE7E0787B\r\nS3150001251821786278A37800902079019060790290F9\r\nS31500012528A0790390E0790490207A0590607A069064\r\nS31500012538A07A0790E07A0890207B0990607B0A9040\r\nS31500012548A07B0B90E07B0C90564802F01DFA0136F1\r\nS315000125581034D8E71AAE2C1C119B9C4200DB84E090\r\nS31500012568301C1038FFF7D4FE611C1091002846D0A4\r\nS31500012578119B013B9C4242DA301CFFF7F1FE002811\r\nS315000125883DD026AD16AA21015118281C102204F0A7\r\nS315000125982DFD109B16AA1F016846D1190126102286\r\nS315000125A8A9302E7404F022FD6B469A33E97F9A7F8F\r\nS315000125B8DE777F230B40934200DA131C01333A4836\r\nS315000125C8191C0F9302F0E0F96E46A51CBA360227CC\r\nS315000125D8A54249D011996B1A5A1E93415B421D4077\r\nS315000125E8A54241D0290116AA5118301C102204F01F\r\nS315000125F8FDFC01233374ED18FF181136E8E7109C2A\r\nS315000126081036A9E7013D1BE7109D129C0135119A69\r\nS31500012618013495421DD00F99E20FCB17A1425341C0\r\nS315000126285B421C401126664326AA9619337C002B69\r\nS315000126380DD116AB2901C918301C102204F0D6FC9D\r\nS31500012648012333740F99FF188F4200D115E701351D\r\nS31500012658DDE7129B0F99013312938B4200DADCE610\r\nS31500012668109A01321092C3E60125104BDB6B1A0250\r\nS3150001267804D50F9B9F4200D099E6FEE649B0F0BC0F\r\nS3150001268801BC00471B121200341212004A12120032\r\nS31500012698580B1200D1121200FB1212006C12120012\r\nS315000126A80B13120066121200BC12120000F4FFFF8F\r\nS315000126B8104B1A68511C10B51960002111701A685F\r\nS315000126C8541C1C6011701A68511C196010701A6824\r\nS315000126D84008511C196010701A684008511C19608D\r\nS315000126E810701A684008511C19601070062010BC39\r\nS315000126F802BC084798C8200030B5062300210B4ABA\r\nS315000127081468013B651C1B061560414020701B0EB1\r\nS315000127184008002BF3D11368581C106001221140A0\r\nS315000127280720197030BC02BC0847C04698C820006B\r\nS31500012738F7B500220191131C00210D1C0126064044\r\nS315000127488E407340174E37680097BC460127BC4434\r\nS31500012758674604063760009F240E1B060131654053\r\nS315000127681B0E3C7040080829E8D131684C1C3460BE\r\nS315000127780D70012A00D1019801321206120E042A9F\r\nS31500012788DAD108223168013A481C12063060120E65\r\nS315000127980B705B08002AF5D133682D201A70FEBC30\r\nS315000127A802BC084798C8200038B5214D214B224C58\r\nS315000127B82B60224B0422207080201A635F2180013E\r\nS315000127C80DF0B6FF962004F017FB2378013B237022\r\nS315000127D82B68E02001332B600DF08AFFDC204000D6\r\nS315000127E804F0E0FA802080015F210DF0A1FF80202E\r\nS315000127F804F0D8FA23785A1E2270002B15D02B68BC\r\nS315000128085A1C2A601B78DA0702D580204000EFE7B8\r\nS31500012818E0200DF06DFFB82004F0C4FA8020800195\r\nS315000128285F210DF085FF4820E2E738BC01BC00476F\r\nS3150001283894C8200054C820009CC8200000F4FFFF5B\r\nS3150001284838B50C4A0C4B041C0C201A60FFF730FFF4\r\nS31500012858051C2004210C000CFFF76AFF401900062D\r\nS31500012868000EFFF7A1FF142004F0C6FA38BC01BC1C\r\nS315000128780047C04654C8200098C8200038B5051C32\r\nS31500012888012A02D1081CFFF7DBFF1B4B1B4A092053\r\nS315000128981A60FFF70DFF041C281CFFF72DFF184DC2\r\nS315000128A88021184A0419281C04F0ACFB2406802050\r\nS315000128B84003240E0DF0D4FE0DF00CFF201CFFF78B\r\nS315000128C873FF0023104A116CC80701D543215162D1\r\nS315000128D8126CD106F6D50C4A126AEA54094A013332\r\nS315000128E89342EFD1E0200DF003FF084B04225A630F\r\nS315000128F838BC01BC0047C04698C8200054C820000F\r\nS31500012908142C2000409C00000040FDFF00F4FFFF4E\r\nS3150001291870B5051C0E1C012B02D1101CFFF790FF88\r\nS31500012928114A124B0A201A60FFF7C2FE041C301C1A\r\nS31500012938FFF7E2FE04192804290C000CFFF7F8FE3C\r\nS315000129482406240E20180006000EFFF72DFF14207A\r\nS3150001295804F052FAE0200DF0CBFE054B04225A632F\r\nS3150001296870BC01BC0047C04654C8200098C8200066\r\nS3150001297800F4FFFF3847C0460123F7B54E0B1E404A\r\nS31500012988CC0A9E401C4034198A0A9C401A40A21857\r\nS315000129984D08464C9A401D405519221CEA408E00A6\r\nS315000129A8151C0F1C820F1F4032431A409F400E010F\r\nS315000129B8BF18020F32431A409F404E01BF18C20E7C\r\nS315000129C832431A409F40BF18394A161CFE401D4023\r\nS315000129D8371C9D401F40CE01EF19450E35431D405A\r\nS315000129E89D4001958D02AC466646850D35432E1CE4\r\nS315000129F8019D1E40AE199E400196050D0E033543F5\r\nS31500012A082E1C019D1E40AE199E400196050C0E0412\r\nS31500012A1835432E1C019D1E40AE19151CF5402E1C72\r\nS31500012A289F401E40BE19850B8F043D439E401D40A5\r\nS31500012A3801966F00CE04450B35431D407F194D05A0\r\nS31500012A48AC466646C50A35431D409F407F194D066B\r\nS31500012A58AC466646C50935439F401D407D19EA4087\r\nS31500012A68019D1A40AE18CD0642092A431A400F079E\r\nS31500012A78550002093A431A408F07AD1882083A43AE\r\nS31500012A889D401A40C907D840AA1808439A401840D9\r\nS31500012A981018C440201C9E401840064C3018C440EB\r\nS31500012AA8201C1840FEBC02BC0847C046792C000011\r\nS31500012AB8716600007B280779F0B5050487B0002404\r\nS31500012AC8039005912D0C101C211C049300196941D2\r\nS31500012AD8CB0746081E434F08391C301CFFF74CFF2D\r\nS31500012AE8221C051C1032039805990DF0B5FE049BAE\r\nS31500012AF8E3405840012318404540ED030023019562\r\nS31500012B08009300980199013480197941202CDFD16D\r\nS31500012B1807B0F0BC04BC10474168F8B50468CD0796\r\nS31500012B2862082A43A7088D074E072F43E508354350\r\nS31500012B386F408E06A509674035437D404E06E70975\r\nS31500012B4837436F40260A0D062E437E40250C0F0497\r\nS31500012B583D437540A70D8E0237436F40E60D4D0282\r\nS31500012B682E437E40A50E8F013D437540A40F8E006E\r\nS31500012B7834434F0A6C407C408F0A7C40CF0A7C4024\r\nS31500012B888F0B7C40CE0B4B08211C01257140294037\r\nS31500012B980024CF03261C92197B4102604360191C4D\r\nS31500012BA8101CFFF7E9FE211CF8BC04BC104770B5E0\r\nS31500012BB80024061C251C301CFFF7AEFF07236B40BB\r\nS31500012BC8984001352418082DF5D1201C70BC02BC8B\r\nS31500012BD80847F0B585B00290019103921D1C0C1CA3\r\nS31500012BE88E18B44207D002982778FFF7E0FF4740CE\r\nS31500012BF827700134F5E70724671BBC420DD0019AFB\r\nS31500012C08039B0298D5182E78FFF786FF221C0DF034\r\nS31500012C187BFD46402E70013CEFE7002005B0F0BC75\r\nS31500012C2802BC0847114B012210B51A63104A042148\r\nS31500012C381160802189020F4C00280DD15963106952\r\nS31500012C48A042FCD9196310690B498842FBD90122B4\r\nS31500012C585A6310BC01BC004719631069A042FCD92C\r\nS31500012C685963106904498842FBD9F0E700F4FFFF6C\r\nS31500012C780000FAFFFF0B0000FF170000F7B5334C01\r\nS31500012C880D1C276832490090944600208F425ADC71\r\nS31500012C9830490868021C62440A60101C01922E4AD7\r\nS31500012CA87E1C2660061C1068C6552068471C2760CE\r\nS31500012CB80F6816683F1237542068471C27600F684B\r\nS31500012CC816683F1437542068471C2760C978176867\r\nS31500012CD839540898002808D12168166801397118ED\r\nS31500012CE80F78802040423843087021681768481CCD\r\nS31500012CF820607B5421681668481C2060180A7054A5\r\nS31500012D0821681768481C2060180C78542168481CEB\r\nS31500012D18206010681B0E43542368591C21601168F2\r\nS31500012D28CD5417682268281CBF1803F055FF00996F\r\nS31500012D38021C381C04F05AF9281C266803F04CFFBB\r\nS31500012D48861926600120FEBC02BC0847142B200008\r\nS31500012D58B70B0000182B200060002000024B002052\r\nS31500012D6801221A71187370470000200008B5FFF791\r\nS31500012D78F5FF002008BC02BC0847F0B5ADB00E90BF\r\nS31500012D88081C0F930C1C149203F026FF27AD021C96\r\nS31500012D980E99281C04F02AF94E4B1A7B002A07D0F3\r\nS31500012DA8181C07231030E20823400E99FFF711FF7C\r\nS31500012DB80F98002606600A2C19D002D8052C06D0D1\r\nS31500012DC8E8E3202C5CD0402C00D189E0E2E32B78A3\r\nS31500012DD8C02B00D0EBE30F9C3E492023236018311A\r\nS31500012DE81498042204F002F93A4D2E73D2E30E9D8B\r\nS31500012DF829786A78880004279309384018430723F5\r\nS31500012E081D1C8543C80803409D4200D0CFE33923E2\r\nS31500012E18081C98430006030E822B1FD0C02B05D031\r\nS31500012E28442B29D12B4BAD005D190BE029490635F9\r\nS31500012E38AD00491914983A1C04F0D8F80F9C2023C0\r\nS31500012E482360A7E3AB191B7E149CDB43A35501360C\r\nS31500012E58042EF7D10F9D20232B609BE3201C03F042\r\nS31500012E68BBFE0E99021C149804F0C0F8194B0F9E6C\r\nS31500012E7834609D601F718DE3174801F085FD96E367\r\nS31500012E88144D2B79042B10D1AE68201C351C114E1C\r\nS31500012E9803F0A2FE0635AD007519021C0E99281C11\r\nS31500012EA804F0A4F80123337181E30A490E981C3111\r\nS31500012EB8042204F0B3F8002803D0084801F01EFDE7\r\nS31500012EC875E30F9D03492C6024311498042204F0FC\r\nS31500012ED88DF85FE3000020001E131200381312005C\r\nS31500012EE8FA4EFB4BB06C984209D8F16C08220818C7\r\nS31500012EF80E9904F07BF8B26C131C0833B364F34DD6\r\nS31500012F08F44C2B7FE27F1B0412021A432B1C03335A\r\nS31500012F18DB7F1A436B7F1B061A43AB7FED7FEB4EB4\r\nS31500012F282D021D439446B37E727E1B0412021A4378\r\nS31500012F38337E1A43F37E0E9C1B061A430C92A37822\r\nS31500012F4862781B0412021A4323781A43E3781B0694\r\nS31500012F5860461A430D92C301FF221A4000230B93C0\r\nS31500012F68C1096B0666460A921943EC09760E18944E\r\nS31500012F780A1C01240A980B991596224066460023D5\r\nS31500012F8812184B41A806B10901430E1C2640002719\r\nS31500012F98B6197F4192197B41A809664619907109AC\r\nS31500012FA8E806014321408E00002792197B416809F2\r\nS31500012FB866461A903109280701432140CE000027A9\r\nS31500012FC8B6185F416246D108EB0821401C930A01F5\r\nS31500012FD8002392197B416646B10821404E0100271C\r\nS31500012FE86146B6185F4128094B086A081B902340B9\r\nS31500012FF8A8081D901E9298010021321C3B1C6646AA\r\nS3150001300812184B4110921193B10BAB0419430A1CC8\r\nS31500013018760BE9040E43A80B690B264022400023D0\r\nS3150001302892185B411F902091B000002180185941E8\r\nS3150001303862466B04D60B1E43321C224000238018BD\r\nS31500013048594162462B05160B1E4326402B0B21932D\r\nS31500013058F20000238018594162466B05D60A1E43C1\r\nS315000130682640EB0A22933201002380185941624611\r\nS31500013078AB05960A1E432640AB0A23937201002329\r\nS31500013088801859416246EB05560A1E4326406B0ACB\r\nS315000130982493B201002312184B4160462906060AF9\r\nS315000130A80E43F601290AFF20259130400021801898\r\nS315000130B85941060E02020B021098119933438018E2\r\nS315000130C85941624610901191AB02910D6046194320\r\nS315000130D80A1C460DE9020E43264022400023921897\r\nS315000130E85B41B00000218018594162466B02D60D3A\r\nS315000130F81E43321C2240002312184B416046290305\r\nS31500013108060D0E432640F000002112184B41604679\r\nS315000131186903C60C0E4326403001002112184B41A3\r\nS315000131286046A903860C0E43264070010021121839\r\nS315000131384B416046E903460C0E432640B001002187\r\nS315000131486646801859412A04330C1343DB01FF26CE\r\nS3150001315800271E40021C0B1C92197B4166461692DB\r\nS315000131681793B10FAB0019430A1C760FE9000E43FA\r\nS315000131783B1C2640224092185B41391CB00080183E\r\nS31500013188594162466B00D60F1E43321C3B1C224036\r\nS3150001319812184B4160462901060F0E432640391C79\r\nS315000131A8F00012184B4160466901C60E0E432640CF\r\nS315000131B8391C300112184B416046A901860E0E438F\r\nS315000131C82640391C700180185941EA01159B161CC5\r\nS315000131D81E43264012923B1CB201664612184B4109\r\nS315000131E82802310E0143C901FF260E400027101C93\r\nS315000131F8191C80197941060E02020B0216981799B5\r\nS31500013208334380185941060C02040B04109811998E\r\nS31500013218334380185941199E1A9B2640234000279B\r\nS3150001322810901191B6197F419800002180197941B2\r\nS31500013238189E0027264036184F411B992140CA007F\r\nS315000132481C990023214092197B410E010027B618CB\r\nS315000132585F411D9B234058010021801979411E9E1B\r\nS315000132682640B2010023129E12184B41FF21002766\r\nS315000132780E40101C191C8019794112901391209E39\r\nS315000132881F98391C26402040001849413B1CB200B2\r\nS3150001329812184B41E80B391C80185941219B2340D0\r\nS315000132A8DE00229B00272340801979411E01239BBA\r\nS315000132B800272340801979415E01249B002723407A\r\nS315000132C8801979419E01002706E0C04600002000CA\r\nS315000132D8AF0A00000400200036184F412599FF2047\r\nS315000132E8CB011840002136184F41129D31026B1847\r\nS315000132F8109811990022801859410C9A1090119131\r\nS31500013308FF23D1010C9D1940D3092340CA18AB09E3\r\nS315000133182340A340D2186B0923409B00D2182B09DE\r\nS315000133282340DB00D218EB08A90823401B012140E2\r\nS31500013338D2184901521869082140890152186B0BA4\r\nS31500013348A90B21402340A1409B00CB18E90B214042\r\nS3150001335859182B0B2340DB00C918EB0A23401B0124\r\nS31500013368C918AB0A23405B01680AC91820402B0A11\r\nS31500013378FF268001DB0109183340CB181B02D3183D\r\nS31500013388A90D6A0D21402240A14092008A18E90D33\r\nS31500013398214051182A0D2240D2008918EA0CA80C9E\r\nS315000133A8224012012040891840010918680C2A0C8C\r\nS315000133B820408001D201091832408A18A80F690FE6\r\nS315000133C8204021408900A0404018E90F4018290FE4\r\nS315000133D82140C9004018E90E214009014018291C5D\r\nS315000133E8AD0E25406D01490E401921400C9D8901FC\r\nS315000133F84118280EC001304009180E020D98961979\r\nS3150001340836049E19C101FF22C30911402340CA1877\r\nS3150001341883092340A340D218430923409B00D218AD\r\nS3150001342803092340DB00D218C308810823401B0186\r\nS315000134382140D218490152184108214089015218E0\r\nS31500013448430B810B21402340A1409B00CB18C10BA4\r\nS3150001345821405918030B2340DB00C918C30A23402E\r\nS315000134681B01C918830A0D9D2340400A5B012040B0\r\nS31500013478C91880012B0A0918DB01FF200340CB1864\r\nS315000134881B02D318A90D6A0D21402240A1409200C2\r\nS315000134988A18E90D214051182A0D2240D2008918AF\r\nS315000134A8EA0CA80C2240120120408918400109188B\r\nS315000134B8680C2A0C20408001FF25D20109182A40F0\r\nS315000134C88A180D99880F490F0D9D204021408900C2\r\nS315000134D8A0404018E90F4018290F2140C90040189B\r\nS315000134E8E90E2140AD0E0901254040186D0140192C\r\nS315000134F80D9D690E214089014118280EC001FF253D\r\nS3150001350828400918090251180904321C5B18109839\r\nS315000135181199FFF7D1FA284E30617161274E0C36A1\r\nS31500013528301CFFF744FB26ADC0432870301CFFF75B\r\nS315000135383EFBC0436870301CFFF739FBC043A870D7\r\nS31500013548301CFFF734FB0E99C043E8700431281C80\r\nS31500013558042203F063FD002811D00E9CE07821783F\r\nS315000135686278A37800902079019060790290A07919\r\nS315000135780390E0790490124801F006FA17E00E4D1F\r\nS31500013588291C2431149804222C7303F02FFD0F9E55\r\nS31500013598202333600848037B002B08D00F9C23683F\r\nS315000135A80721DA0810300B401499FFF712FB2DB0EA\r\nS315000135B8F0BC01BC0047C046000020000400200002\r\nS315000135C851131200F7B500240190161C1F1C1C602C\r\nS315000135D8A14202D0202913D059E0304B1B78002B89\r\nS315000135E803D02F4801F08AF93DE00520386003F041\r\nS315000135F8F3FA2C49021C301C03F0F8FC01204AE0BE\r\nS31500013608264A1378284C002B14D13960301C2749D7\r\nS31500013618042203F0EBFC2568254AA81D01261F4B49\r\nS315000136288000101801990422AD191E7003F0DEFC02\r\nS315000136382560E3E72568012D03D11D48311C1C309F\r\nS3150001364804E0A81D1A4B80000199181804220135B7\r\nS3150001365803F0CCFC2560072D07D9164801F04EF971\r\nS31500013668154B01221A70002015E00A233B602368D6\r\nS315000136784020DA0040421043072253409908031CB0\r\nS315000136880B43337023685A4092017270B6E70B48B0\r\nS3150001369801F07AF9201CFEBC02BC0847B9C8200013\r\nS315000136A88013120091131200BCC82000A0C8200084\r\nS315000136B80000200093131200B8C82000A3131200BB\r\nS315000136C8F0B59BB00893089E00233360264B0392FE\r\nS315000136D81A78041C0D1C002A06D00723CA080B40B9\r\nS315000136E82248211CFFF775FA002D02D0202D4BD058\r\nS315000136F811E31D4E3378002B2AD01D4B1B78002B66\r\nS3150001370803D01C4801F0FAF81DE31B4E34681B4828\r\nS31500013718012C06D11A49042202311C3003F066FC39\r\nS3150001372810E0022C0BD1431CDD77831CDD77144B8B\r\nS3150001373819785B78C21C0430D177C37702E0A31DE0\r\nS315000137489B00C550084D0134002334602B70E8E214\r\nS31500013758089E0520306003F03FFA0A49021C0398C7\r\nS3150001376803F044FCDDE2C046C0C82000B0C8200012\r\nS31500013778C9C82000BB131200BCC8200000002000E5\r\nS31500013788C1C8200091131200FB4D2D780195002D1B\r\nS3150001379800D08FE2F94B59789A780902120411433D\r\nS315000137A81A781143DA785D79120611431A792D02CE\r\nS315000137B81543A37862781B0412021A4323781A4325\r\nS315000137C8E3788C4666461B0660461A43490EF301A2\r\nS315000137D8FF261E4009916B06C109019F19430292F2\r\nS315000137E8EA0901240C920A1C3B1C224092197B41CE\r\nS315000137F86646A806B10901430E1C019F2640B61963\r\nS315000138087F4192197B41A80966460D907109E80620\r\nS31500013818014321408E00002792197B4168096646BB\r\nS315000138280E903109280701432140CE000027B6181A\r\nS315000138385F416246D108EB08214010930A01002333\r\nS3150001384892197B416646B10821404E01002761461F\r\nS31500013858B6185F4128094B086A080F902340A80843\r\nS315000138681190129298010021321C3B1C12184B41EF\r\nS31500013878664604920593AA04B30B1343A80B019950\r\nS315000138881390181C2040021C0B1C12184B41760B76\r\nS31500013898E9040E432640690B1491B00000218018F3\r\nS315000138A8594162466B04D60B1E43321C019B2240CA\r\nS315000138B88018594162462B05160B1E4326402B0BD1\r\nS315000138C8F200159300238018594162466B05D60A02\r\nS315000138D81E432640EB0A32011693002380185941EC\r\nS315000138E86246AB05960A1E432640AB0A7201179338\r\nS315000138F80023801859416246EB05560A1E432640A5\r\nS315000139086B0A1893B201002312184B416046290627\r\nS31500013918060A0E43290A1991F6010199FF2030403A\r\nS3150001392880185941060E02020B0204980599334381\r\nS3150001393880185941624604900591AB02910D604683\r\nS3150001394819430A1C460DE902019B0E4326402240F3\r\nS3150001395892185B41B00000218018594162466B02FA\r\nS31500013968D60D1E43321C019B224012184B4160465C\r\nS315000139782903060D0E432640F000002112184B417B\r\nS3150001398860466903C60C0E43264030010021121811\r\nS315000139984B416046A903860C0E432640700100215F\r\nS315000139A812184B416046E903460C0E432640B00106\r\nS315000139B800216646801859412A04330C1343019F96\r\nS315000139C8DB01FF261E40021C0B1C92197B41664631\r\nS315000139D80A920B93B10FAB0019430A1C760FE90043\r\nS315000139E80E433B1C2640224092185B41B000002141\r\nS315000139F88018594162466B00D60F1E43321C3B1C88\r\nS31500013A08224012184B4160462901060F0E432640F3\r\nS31500013A18F000002112184B4160466901C60E0E439B\r\nS31500013A2826403001002112184B416046A901860E35\r\nS31500013A380E4326407001002180185941EA01099B6D\r\nS31500013A48161C1E43264006920023B201664612182A\r\nS31500013A584B412802310E0143019FC901FF260E4041\r\nS31500013A68101C191C80197941060E02020B020A98CC\r\nS31500013A780B99334380185941060C02040B04049828\r\nS31500013A8805993343801859410D9E0E9B019F23408A\r\nS31500013A98264004900591B6197F41980000218019A6\r\nS31500013AA879410C9E019F264036184F410F992140B6\r\nS31500013AB8CA0010990023214092197B410E01002763\r\nS31500013AC8B6185F41119B234058010021801979419D\r\nS31500013AD8129E2640B2010023069E12184B41019FF1\r\nS31500013AE8FF210E40101C191C801979410690079177\r\nS31500013AF8149E1398391C2640204000184941B200EB\r\nS31500013B08002312184B41E80B391C80185941159BA3\r\nS31500013B182340DE00169B00272340801979411E01A8\r\nS31500013B28179B00272340801979415E01189B0027BE\r\nS31500013B382340801979419E01002736184F4119996A\r\nS31500013B48FF20CB010199184036184F41069D02986E\r\nS31500013B583102019A049E059F6B18B6185F41C1018F\r\nS31500013B68FF22C30911402340CA1883092340A340F1\r\nS31500013B78D2184309234003E0C0C82000C1C8200069\r\nS31500013B889B00D21803092340DB00D218C308810819\r\nS31500013B9823401B012140D2184901521841082140EE\r\nS31500013BA889015218430B810B21402340A1409B00F8\r\nS31500013BB8CB18C10B21405918030B2340DB00C91848\r\nS31500013BC8C30A23401B01C918830A029D2340400AE0\r\nS31500013BD85B012040C91880012B0A0918DB01FF2067\r\nS31500013BE80340CB181B02D318A90D6A0D21402240A8\r\nS31500013BF8A14092008A18E90D214051182A0D224048\r\nS31500013C08D2008918EA0CA80C224012012040891812\r\nS31500013C1840010918680C2A0C20408001FF25D201B1\r\nS31500013C2809182A408A180299880F490F029D2040CF\r\nS31500013C3821408900A0404018E90F4018290F21406A\r\nS31500013C48C9004018E90E214009014018A90E214072\r\nS31500013C586D0E490125404018AD014019029D290EF6\r\nS31500013C68C901FF25294041180902521812049A1858\r\nS31500013C78301C019B391CFEF71FFF354E04223060AC\r\nS31500013C8871600199039803F0BDF9039D0435281C59\r\nS31500013C98FF21042203F0B6F9301C291C019B0422DA\r\nS31500013CA8FEF797FF089E402333602A4D2A4B2C7056\r\nS31500013CB81C7036E0284B1A78284D002A02D00022BB\r\nS31500013CC81A700AE02E68264BB01D80001818211CB0\r\nS31500013CD80422013603F08AF92E602E68072E06D9CA\r\nS31500013CE8204800F00BFE204B01221A7017E0089EAF\r\nS31500013CF80A2333602B684020DA004042104307222A\r\nS31500013D0853409908039E031C0B4333702B685A4092\r\nS31500013D189201727005E01548291C00F035FE002550\r\nS31500013D2811E00C4B1B780125002B0CD00A4B1B7894\r\nS31500013D38002B08D1089E33680721DA0804480B408E\r\nS31500013D480399FEF746FF281C1BB0F0BC02BC0847C6\r\nS31500013D58B0C82000C0C82000C9C82000BCC82000BF\r\nS31500013D680000200093131200B8C82000A313120004\r\nS31500013D7870B500250C1C161C1D60A94202D020290D\r\nS31500013D8814D025E0164A1278002A04D0154800F006\r\nS31500013D98B5FD201C20E00520186002F01DFF124920\r\nS31500013DA8021C301C03F022F9012015E00C4C227884\r\nS31500013DB8002A09D140221A60301C0C49082203F056\r\nS31500013DC815F90120207007E0094800F097FD02E087\r\nS31500013DD8084800F0D9FD281C70BC02BC0847C0463B\r\nS31500013DE8C0C82000BB13120091131200A4C82000FA\r\nS31500013DF8D2131200A3131200F0B5002589B006915B\r\nS31500013E0807921E1C1D60A94202D0202938D067E0FE\r\nS31500013E1838480378002B2BD0374CE0782178627824\r\nS31500013E28A37800902079019060790290A079039097\r\nS31500013E38E0790490314800F0A7FD314D314FEB6C24\r\nS31500013E483968581808315918082203F0CFF8069B23\r\nS31500013E582849AA6C0B703B68083AAA64934201D1B7\r\nS31500013E68002042E0E96C201CC918082203F0BEF8BC\r\nS31500013E780520306002F0B0FE2349021C07982BE0AA\r\nS31500013E881C4F3B781C4C002B09D140233360079803\r\nS31500013E98211C082203F0AAF80120387025E0E078F1\r\nS31500013EA821786278A3780090207901906079029050\r\nS31500013EB8A0790390E0790490144800F065FD114952\r\nS31500013EC80F4A0B68906C08333D708342C8D00B606B\r\nS31500013ED8D16C201CC918082203F088F8012004E0D7\r\nS31500013EE80B48069900F050FD281C09B0F0BC02BC2D\r\nS31500013EF80847C046C0C82000A4C82000EC13120019\r\nS31500013F0800002000502A2000911312002A141200E2\r\nS31500013F18A3131200F0B501208FB00CF0E5FB0CF0ED\r\nS31500013F2887FC994B994A0025D86C994E291C15602E\r\nS31500013F38984A9D64042703F065F88024964800F0A2\r\nS31500013F48DDFCA401376320200CF0D2FB201C5F2185\r\nS31500013F580CF0EEFB802040030CF082FB80239B04CF\r\nS31500013F68736380239B023361336073638B4B1C61DC\r\nS31500013F7880238B4C1B02736702232360894B636082\r\nS31500013F880523236009A8291C142203F03BF8012004\r\nS31500013F9804900790069505972F1CF36B190200D418\r\nS31500013FA8DAE0814A814B1A6000247D4B804A1969FF\r\nS31500013FB8914200D991E01A6A9106F6D55869C0214D\r\nS31500013FC80CF004FCF36B0122DB0B2D18134003954F\r\nS31500013FD8002F0FD1002B2FD00C280DDC6C4B802223\r\nS31500013FE892005A63391C09A814223C1C03F00AF8EA\r\nS31500013FF8012703E0012B01D0039DD6E780235B004F\r\nS315000140083363039B232B02DD083B06934BE003989E\r\nS3150001401818280BDD0721A1430120E20809AB8840D6\r\nS31500014028011C985C0143995401343CE0039900252D\r\nS315000140380E29BADD0134B8E78023039A9B0033635E\r\nS315000140484F2A02DD103A06920FE0039B382B0EDD4C\r\nS31500014058611C07208843CA08011C012009AB884056\r\nS31500014068011C985C0143995402343D1C9DE7039950\r\nS3150001407828291ADD049A631C002A0BD107209843C4\r\nS31500014088D908031C012009AA9840031C505C034364\r\nS315000140985354A31C079841424141079104990122AF\r\nS315000140A8514004911C1C00257FE7039A3D1C182AE0\r\nS315000140B800DC7AE7059B002B02D0013B059374E7E8\r\nS315000140C807980721A143E20809AB8840011C985CBF\r\nS315000140D8014399540134059D67E7002C33D00097B5\r\nS315000140E809A8211C069A0023FEF7C8FD002803D15A\r\nS315000140F8304800F003FC2FE0201C02F06DFD021E83\r\nS31500014108082A0CD1204C2C4BA06C984207D8E16C9C\r\nS31500014118081809A902F06AFFA36C0833A3641422DC\r\nS3150001412809A8002102F06EFF80235B0073638023D8\r\nS315000141389B007363002701230422059204930793C6\r\nS315000141483D1C069704E01869C0210CF03FFB2D18A9\r\nS3150001415813480423036020E701248023A340346322\r\nS31500014168736380239B0073630D4A042373630223DD\r\nS315000141781360124AE02013600CF0BAFA74630FB0A8\r\nS31500014188F0BC01BC0047C04600002000502A2000B0\r\nS3150001419800F4FFFFB80A00005414120000FCFFFFE8\r\nS315000141A84000FAFF00070300010000A540FDFFFFDC\r\nS315000141B8FF3B00006A141200AF0A00000000FAFF74\r\nS315000141C8F0B58A4E91B00024029001200F1C059487\r\nS315000141D834710CF089FA0CF02BFB854D211C854AAC\r\nS315000141E8E86CAC64346002F00DFF834C834800F040\r\nS315000141F885FB04232363FEF7B1FD0298002808D046\r\nS315000142087F4800F07BFB281C1830391C302202F04D\r\nS31500014218EDFE0026371CB200AA180023D118097E24\r\nS315000142283F0201330F43042BF8D1311C75483A1C60\r\nS31500014238013600F0A9FB0C2EEDD18025AD01202019\r\nS315000142480CF056FA281C5F210CF072FA8020400304\r\nS315000142580CF006FA80239B04636380239B02236187\r\nS31500014268802223606363684B52011A611D618023B2\r\nS31500014278664D1B02636702232B60654B6B60052342\r\nS3150001428800212B6006A8142202F0BCFE002102912F\r\nS315000142980F1C2E1CE26B584B100200D495E05D4AA8\r\nS315000142A85D4B1A60002531695C4A584B914226D804\r\nS315000142B81A6A9006F7D55869C0210CF087FA584B47\r\nS315000142C8029905221A6080235B00081823632328B4\r\nS315000142D802DD071C083F0FE018280ADD0722AA435A\r\nS315000142E80121EB08914006A80A1CC15C0A43C25485\r\nS315000142F801E00E2800DD013500210291D3E7042DE6\r\nS3150001430859D93A4A1379002B0ED101200090291C5C\r\nS3150001431806A83A1CFEF7B2FC002805D1414800F070\r\nS31500014328EDFA324901220A710223336006A8291CD3\r\nS315000143380BAA05ABFEF721FD394B1A693A4B9A428E\r\nS31500014348FAD9059B0393002B2AD005250120013DA7\r\nS31500014358FEF768FC002DF9D1EB080BAFFB5C0720D3\r\nS31500014368A8430341181C01210840FEF75BFC039A88\r\nS3150001437801359542F0D180231C489B02636303797A\r\nS31500014388002B0DD10093381C05991A1CFEF776FCF3\r\nS31500014398002805D1234800F0B1FA144901220A710F\r\nS315000143A806A80021142202F02DFE0523336080237E\r\nS315000143B85B00636300273069C0210CF007FA029B92\r\nS315000143C81B1802930423336064E7802252005A6360\r\nS315000143D804225A63124A02233360E02013600CF068\r\nS315000143E887F911B0F0BC01BC0047C046502A20002D\r\nS315000143F800002000B80A000000F4FFFF751412003F\r\nS3150001440890141200A914120000FCFFFF4000FAFFE5\r\nS3150001441800050100010000A540FDFFFFFF3B00006C\r\nS315000144280000FAFF6A141200FF8F0000F0B5D34AA4\r\nS3150001443899B00023039001200C1C0D9313700CF006\r\nS3150001444853F90CF0F5F9CE4800F058FA03981538E7\r\nS31500014458042800D9E4E00BF087FF03142CE3460097\r\nS31500014468C84800F091FA0422C748211C02F0BEFD93\r\nS31500014478C64A00231360C64A1371C64A06931370C7\r\nS3150001448843E0C54800F03AFAC44D211C0822281C0D\r\nS3150001449802F0ACFD08200022291C00F09BFABC4A58\r\nS315000144A800231371BE4A1370BE4A01201370069089\r\nS315000144B82BE0BD4800F022FABC4D211C0622281C1F\r\nS315000144C802F094FD291C0022062000F083FAAF4A67\r\nS315000144D800231360AE4A1371B14A1370B14A012120\r\nS315000144E81370069111E0B24EB26CB248D10800F0D1\r\nS315000144F84BFAA74D0024F16CA84808222C6002F05B\r\nS3150001450875FDA74B2C711C700694AB4C04268025AF\r\nS31500014518AD0226638027FEF721FCBF012561212014\r\nS3150001452825600CF0E5F85F21381C0CF001F98020B4\r\nS3150001453840030CF095F880239B0463631E20656392\r\nS3150001454802F05AFC9D4B802252011A611F61802399\r\nS315000145581B0263679A4B02221A609A4A9A4D5A605D\r\nS3150001456805222A601A60039B092B0CD8974800F08C\r\nS31500014578C5F9C82001210B900A910026012205924E\r\nS31500014588089604963FE0039B132B01D89048EEE763\r\nS31500014598039A1D2A06D88F4800F0B0F95A230B93BF\r\nS315000145A80A96EAE78C483CE004232B6080239B02A9\r\nS315000145B8236328699042FCD9814863630523036014\r\nS315000145C8002900D0A4E00EA80021142202F01AFD49\r\nS315000145D80A9B012000260993079005900896784BB7\r\nS315000145E87E4A196991420BD81A6A910600D5A7E045\r\nS315000145F873490A69F0239B019A42F0D9002EEED03D\r\nS31500014608002F00D02BE1E36B1A0200D427E1744A8C\r\nS31500014618744B1A60002E08D10398153804281DD941\r\nS315000146287148039900F0B0F938E1594F04983B797C\r\nS3150001463801300490002BEFD100930EA8311C089A83\r\nS31500014648FEF71CFB0028E7D1684800F057F90699E0\r\nS31500014658002900D003E101233B71DDE70BF07AFE67\r\nS31500014668030A11E018000EA8311C13AA0DABFEF7B8\r\nS31500014678A9FF13E00EA8311C13AA0DABFFF778FBAF\r\nS315000146880CE00EA8311C13AA0DABFFF719F805E0CB\r\nS315000146980EA8311C13AA0DABFFF7AEFB0123584038\r\nS315000146A80706474A059802230B9913600301CB189D\r\nS315000146B8C02253433F0E2A699A42FCD30D9900231F\r\nS315000146C84B4A8B4200D16FE7D80813AE365C0720F8\r\nS315000146D898430641301C012630400590266304267E\r\nS315000146E82E608026B602266328699042FCD9059A6F\r\nS315000146F86663002A04D128693E4A9042FBD903E041\r\nS3150001470828693D4A9042FBD9012262639B18D7E783\r\nS315000147181F4E049A337901320492002B00D052E7D6\r\nS31500014728012000905A2213A8FEF7A8FA002800D003\r\nS3150001473849E70699002900D091E00122327142E742\r\nS315000147485869C0210CF042F804232B6080235B00D2\r\nS3150001475823634F2802DD1038089049E738284DDDD4\r\nS31500014768711C07208843CA08011C01200EAB88402A\r\nS31500014778011C985C01439954023639E7B8C82000F0\r\nS31500014788B7141200D4141200A0C82000BCC8200017\r\nS31500014798502A2000B9C82000F5141200A4C8200028\r\nS315000147A8C0C82000C9C8200016151200C1C82000BB\r\nS315000147B8000020003015120000F4FFFF00FCFFFF87\r\nS315000147C84000FAFF000602000000FAFF6F1512000A\r\nS315000147D88C151200A9151200C6151200FFE000007B\r\nS315000147E8010000A540FDFFFF531512006A141200CF\r\nS315000147F87F0400007F100000FF140000282819DD3F\r\nS31500014808079A731C002A0BD107209843D908031C61\r\nS3150001481801200EAA9840031C505C03435354B31C51\r\nS31500014828059901220798514011405040059107907A\r\nS315000148381E1CDDE6182800DCDAE60999002902D0F3\r\nS3150001484801390991D4E605980721B143F2080EAB5F\r\nS315000148588840011C985C014399540136C8E68023B7\r\nS315000148685B0063630F4804236363022303602B60C1\r\nS31500014878E0200BF03DFF04990B4800F085F80B4842\r\nS3150001488800F03CF80A4B19780A4B183300930022BA\r\nS3150001489830230193FF20131C02F0F4FE19B0F0BC7B\r\nS315000148A801BC00474000FAFFEB151200FE15120085\r\nS315000148B8B8C8200000002000084B094901221A60E7\r\nS315000148C85960824002211A611960D9691142FCD0E6\r\nS315000148D8024B0C308000C0587047C0460080FDFF6F\r\nS315000148E800201008034B012252421A60024B08228B\r\nS315000148F81A607047CCCA2000582A200013B5041C38\r\nS3150001490802F09EFB0106090E002280200094019107\r\nS31500014918131C400002F0B6FE13BC01BC0047154B40\r\nS315000149281A6810B5072A07DD134A1168134C0131B5\r\nS315000149381160002262541A6000280BD01C680E4AC6\r\nS315000149480720001B12680D4901248440201C8C5C39\r\nS31500014958204388541A680A4901328A4201D81A60E2\r\nS3150001496804E0002207481A60FFF7C8FF10BC01BC23\r\nS315000149780047C046582A2000CCCA2000CCC82000CF\r\nS31500014988FF010000071612000FB400B5A3B024AB4F\r\nS3150001499804CB02A9101C0A22019301F08DFD02A87D\r\nS315000149A8FFF7ACFF23B008BC04B0184710B5064C96\r\nS315000149B80021221C054802F025FB0548211CFFF7AA\r\nS315000149C8E3FF10BC01BC0047409C0000142C2000EA\r\nS315000149D822161200F0B58BB0039004910592041CBF\r\nS315000149E8049B039A9E18361B002C29DD251E082DCB\r\nS315000149F800DD082507AF381C311C2A1C02F0F6FA1F\r\nS31500014A0800237B5507A95A5C203A1206120E5E2A24\r\nS31500014A1801D92E225A540133AB42F3DB059A0A4BCC\r\nS31500014A28002A06D0009309482A1C331CFFF7ACFF5D\r\nS31500014A3804E00748291C321CFFF7A6FF083CCFE70C\r\nS31500014A480BB0F0BC01BC0047851712003C161200DA\r\nS31500014A584116120070B5061C20250024301CFFF7EC\r\nS31500014A682BFF013D2418002DF8D10F34601170BCBD\r\nS31500014A7802BC0847F0B58023364C5B0087B0236338\r\nS31500014A883548FFF73BFF002104223448002502F090\r\nS31500014A98B9FA00200BF02CFE0595039504952F1CF9\r\nS31500014AA8FF262F4A2F4B310480201A60090C8001FA\r\nS31500014AB80BF03EFE142002F09FF90420FFF7CAFF0F\r\nS31500014AC8294C4443A4125F2E03D0592E02D1251C2A\r\nS31500014AD800E00594254A2648B218231212181370C5\r\nS31500014AE81B061B0EBB4202DC049C3B1C00E0039622\r\nS31500014AF8013E132E02D004941F1CD2E71549012644\r\nS31500014B080E6360200BF0F4FD142002F075F9052000\r\nS31500014B18FFF7A0FF071C1748FFF7F0FE059A2904BF\r\nS31500014B281143154A57430398230403430020009071\r\nS31500014B3801908220BA12C00002F0A4FDE0200BF019\r\nS31500014B48D7FD04498023B3404E634B6307B0F0BCDD\r\nS31500014B5801BC004700F4FFFF451612006C4820000F\r\nS31500014B68010000A540FDFFFF1C190200142C2000BE\r\nS31500014B78581C000077161200E880000008B50E4898\r\nS31500014B88FFF7BCFE60200BF0B3FD142002F034F9E8\r\nS31500014B980520FFF75FFF0949414309488912FFF7D5\r\nS31500014BA8F3FE084BDB6B1A02ECD40748FFF7A6FEA7\r\nS31500014BB808BC01BC0047C046A7161200E8800000E1\r\nS31500014BC8D216120000F4FFFFD816120038B563207A\r\nS31500014BD80BF08EFD802000030BF042FD0BF07AFDF1\r\nS31500014BE80023191C1A1C1148046CE50701D5FF247A\r\nS31500014BF84462006CC406F6D50C48046A52060120C4\r\nS31500014C08120E044200D002430133072BEBDD084B99\r\nS31500014C185A54084B0131994201DC0023E2E7064860\r\nS31500014C28FFF76CFE38BC01BC0047C0460040FDFFDB\r\nS31500014C386C482000B70A0000E21612007FB5011C75\r\nS31500014C480278437880780090C878019008790290B4\r\nS31500014C584879039088790490C87905900248FFF746\r\nS31500014C6893FE07B001BC00470517120000B51448AA\r\nS31500014C788DB0FFF743FE134B134A1B68934202D3C9\r\nS31500014C88124A934201D3124805E068463021114A77\r\nS31500014C9802F0F8F86846FFF731FE0F4A0F4B6846EF\r\nS31500014CA8302102F0EFF86846FFF728FE6846302102\r\nS31500014CB80BF004FD6846FFF721FE0DB001BC004765\r\nS31500014CC831171200FC01100000001000000014004A\r\nS31500014CD8511712007D171200871712007727120045\r\nS31500014CE8F0B55A4887B0FFF709FE0120C82102F03E\r\nS31500014CF88CF80220C82102F088F80420C82102F0A5\r\nS31500014D0884F80220C82102F080F80120C82102F0A7\r\nS31500014D187CF80220C82102F078F80420C82102F0A4\r\nS31500014D2874F80220C82102F070F80120C82102F0A7\r\nS31500014D386CF80120002102F068F80024444D454F23\r\nS31500014D4802F0E8FBFA202F60800001F0E7FF061C5D\r\nS31500014D589620400002F050F8002E2DDD661C01F069\r\nS31500014D6873FF301C002102F050F80820002102F0E0\r\nS31500014D784CF83948FFF7C2FD384BDB6B190201D4F1\r\nS31500014D882F60F9E7FA20400002F036F8A50002AADA\r\nS31500014D9804AF511901207A190023FCF7F1FC082305\r\nS31500014DA85B1969465A582E48EB59211CFFF7ECFD49\r\nS31500014DB801F04AFF301C45E0002EBFD0661C01F009\r\nS31500014DC843FF301C002102F020F80420002102F0E4\r\nS31500014DD81CF82448FFF792FD204BDB6B1A0201D41D\r\nS31500014DE82F60F9E7A500082369465B195B5804AFEC\r\nS31500014DF81A1C01931C48EB59211CFFF7C5FD082114\r\nS31500014E0849196A468858E9590022FCF72CFC1748C3\r\nS31500014E18FFF774FDFA20800001F080FF002808DD05\r\nS31500014E281348FFF76BFD01F00FFF07B0F0BC01BC9B\r\nS31500014E380047962001244000344001F0DDFF01F0CF\r\nS31500014E4803FF601C002101F0E0FF77E78C171200D1\r\nS31500014E5840FDFFFF010000A5AF17120000F4FFFF98\r\nS31500014E68C2171200D4171200FD231200DC17120014\r\nS31500014E78E9171200F0B589B0019001F0E5FE0420AA\r\nS31500014E88FFF71AFD0199061C00200690022904D095\r\nS31500014E986948311CFFF778FD06960520FFF70CFDDA\r\nS31500014EA8019B002200900792012B05D063480099C7\r\nS31500014EB8FFF76AFD0098079000990022049102966F\r\nS31500014EC80392059201255E4CE36B180213D4FA206E\r\nS31500014ED8400001F091FF012D04D15A48FFF70EFD5C\r\nS31500014EE8022508E05848FFF709FD01F0ADFE09B0B3\r\nS31500014EF8F0BC01BC0047554A554B01991A60022975\r\nS31500014F0829D0012D0AD1069BF21AD0171218424050\r\nS31500014F1804230A2A01DD236300E06363059904205B\r\nS31500014F2801310591FFF7C8FC331ADA179B18071CDC\r\nS31500014F3853400A2B0CDD059B4648311C3A1CFFF7EA\r\nS31500014F4823FD029BBB4200DA0297002005903E1C16\r\nS31500014F58019901293DD0012D0CD1009B07981A1AF8\r\nS31500014F68D117521880234A405B000A2A01DD2363C0\r\nS31500014F7800E06363039A052001320392FFF79CFC64\r\nS31500014F88071C0098C31BD9175B184B400A2B0CDD6D\r\nS31500014F983A1C31480099039BFFF7F6FC049ABA427A\r\nS31500014FA800DA0497002300970393022D01D0012507\r\nS31500014FB889E7019801280ED0022807D00499079A93\r\nS31500014FC802988B1A0699421A934204DD049A009BA9\r\nS31500014FD803E0022DEBD1029A331CD117490F8A1827\r\nS31500014FE8D210101C0021851AAB421FDB83421DDC3F\r\nS31500014FF81A4B5B5C80229200D80701D5226300E038\r\nS3150001500862630122990701D5226300E06263802267\r\nS315000150185200580701D5226300E06263042219078A\r\nS3150001502802D5226302254EE76263FBE70131801848\r\nS315000150380829D8D1F6E7C046F11712000918120057\r\nS3150001504800F4FFFF1F1812003C111200010000A511\r\nS3150001505840FDFFFF34181200561812007A0B120091\r\nS31500015068F0B54678037836021E4383781B041E433F\r\nS31500015078C37845791B061E4303792D021D4383799F\r\nS315000150881B041D43C3791B061D43DF4B89B0041C52\r\nS315000150989E4203D1002D01D100F0D6FE301C291CF9\r\nS315000150A8C44BC34A0BF054FB0130012800D946E230\r\nS315000150B8D64B9E4203D1002D01D100F083FD301C51\r\nS315000150C8291CBD4ABD4B0BF043FB0130012800D911\r\nS315000150D8E9E0CF4B9E4203D1002D01D100F024FD1A\r\nS315000150E8301C291CB64AB74B0BF032FB013001289C\r\nS315000150F852D8301C291C042200230BF029FB01304D\r\nS31500015108012818D8301C291C032200230BF020FB88\r\nS31500015118013001D001F01FF9331C2B4301D101F0F5\r\nS3150001512834F9012E01D001F03AF9002D01D101F02F\r\nS3150001513812F901F034F90623FF339E4203D1002DFB\r\nS3150001514801D101F040F8301C291C9F4A9F4B0BF0F6\r\nS31500015158FFFA0130012809D8052E01D001F01FF9FF\r\nS31500015168002D01D101F005F901F019F983235B003E\r\nS315000151789E4203D1002D01D101F0A3F80823FF3384\r\nS315000151889E4201D001F00BF9002D01D001F007F97B\r\nS31500015198FFF76CFD01F009F99E4B9E4203D1002DE4\r\nS315000151A801D101F07CF8301C291C894A894B0BF086\r\nS315000151B8CFFA013001284AD8974B9E4203D1002DD8\r\nS315000151C801D100F03CFC301C291C834A834B0BF0AF\r\nS315000151D8BFFA0130012824D8904B9E4201D001F034\r\nS315000151E8DEF8002D01D001F0DAF8607A237A0002A0\r\nS315000151F81843A37A1B041843E37A617C1B061843F8\r\nS31500015208237C09021943A37C1B041943E37C627EB0\r\nS315000152181B061943237E12021A43FCF743F901F0D0\r\nS31500015228C4F87F4B9E4203D1002D01D100F014FC36\r\nS315000152387C4B9E4201D001F0B2F8002D01D001F05D\r\nS31500015248AEF8794E80235B00336300F0FDFF774BA0\r\nS315000152589E4203D1002D01D100F022FC301C291CED\r\nS315000152685F4A604B0BF074FA013001D100F08EFCF5\r\nS3150001527883239B009E4203D1002D01D100F018FC27\r\nS315000152886B4B9E4201D001F08AF8002D01D001F046\r\nS3150001529886F8617A237A09028020194380010BF086\r\nS315000152A847FA01F082F8634B9E4203D1002D01D1E2\r\nS315000152B800F069FD301C291C4B4A4C4B0BF048FA8F\r\nS315000152C80130012800D9BDE05B4B9E4203D1002D78\r\nS315000152D801D100F08EFC301C291C454A454B0BF0C8\r\nS315000152E837FA013001283AD8277AA17AE27A842353\r\nS315000152F804970691677A07929B009E4203D1002D77\r\nS3150001530801D100F0EEFB301C291C3B4A3B4B0BF04C\r\nS315000153181FFA0130012801D800F0EEFF617C237CD9\r\nS3150001532809021943A37C1B041943E37C627E1B060D\r\nS31500015338049E1943237E3F02120237431A43069EEF\r\nS31500015348A37E30041B0438431A43079FE37E3D06B8\r\nS315000153581B0628431A43FCF7CBFD01F026F88523E3\r\nS315000153689B009E4203D1002D01D100F0D0FC301CD8\r\nS31500015378291C234A234B0BF0EBF9013001D100F02C\r\nS315000153884FFC2E4B9E4203D1002D01D100F0D8FCD3\r\nS315000153982B4B9E4201D001F002F8002D01D000F0FE\r\nS315000153A8FEFFFCF751FC01F000F8C046C046C046B6\r\nS315000153B813030000000000000E02000000000000B8\r\nS315000153C802020000000000000501000000000000C4\r\nS315000153D809020000000000000502000000000000AC\r\nS315000153E80B02000000000000170200000000000088\r\nS315000153F81202000000000000100200000000000078\r\nS315000154081402000000000000130300000E02000051\r\nS315000154180202000009020000050200000302000062\r\nS31500015428060200000702000000F4FFFF0B0200005D\r\nS315000154380D0200001702000012020000150200000A\r\nS3150001544816020000D84B9E4203D1002D01D100F06F\r\nS315000154587FFD301C291CC14BBF4A0BF079F901307D\r\nS3150001546801282FD8D14B9E4203D1002D01D100F03E\r\nS31500015478A5FC301C291CBA4ABA4B0BF069F9013054\r\nS3150001548801D100F08BFCC0239B009E4203D1002D65\r\nS3150001549801D100F0D6FCC64B9E4201D000F07FFF39\r\nS315000154A8002D01D000F07BFF607A237A00021843B1\r\nS315000154B8A37A1B041843E37A1B0618430BF0DAF8A0\r\nS315000154C800F073FFC4239B009E4203D1002D01D136\r\nS315000154D800F0EAFC301C291CA34AA44B0BF038F94E\r\nS315000154E80130012817D8C1239B009E4201D000F044\r\nS315000154F856FF002D01D000F052FF607A237A000290\r\nS315000155081843A37A1B041843E37A1B0618430BF0C6\r\nS31500015518BFF800F04AFFA74B9E4203D1002D01D1E7\r\nS3150001552800F0CFFCA44B9E4201D000F038FF002DBD\r\nS3150001553801D000F034FFFAF7C1FF00F036FF8023EF\r\nS31500015548DB009E4203D1002D01D100F03FFE301C45\r\nS31500015558291C874A874B0BF0FBF80130012800D933\r\nS3150001556848E1964B9E4203D1002D01D100F000FD82\r\nS31500015578301C291C804A814B0BF0EAF801300128BE\r\nS3150001558869D88F4B9E4203D1002D01D100F03DFC15\r\nS31500015598301C291C7A4A7B4B0BF0DAF801300128BA\r\nS315000155A825D8884B9E4203D1002D01D100F06FFC0E\r\nS315000155B8DC239B009E4203D1002D01D100F018FC8B\r\nS315000155C8814B9E4201D000F0EAFE002D01D000F089\r\nS315000155D8E6FE607A237A00021843A37A1B0418436D\r\nS315000155E8E37A1B061843FBF7C5FB00F0DEFEE02352\r\nS315000155F89B009E4203D1002D01D100F0E1FD301C34\r\nS31500015608291C614A614B0BF0A3F8013001280FD818\r\nS315000156186E4B9E4201D000F0C2FE002D01D000F073\r\nS31500015628BEFE211C207A2031FEF700FF00F0BDFEE8\r\nS31500015638674B9E4203D1002D01D100F096FC654BC4\r\nS315000156489E4201D000F0ABFE002D01D000F0A7FE6E\r\nS31500015658614B00F0ACFD614B9E4203D1002D01D197\r\nS3150001566800F05DFC301C291C494A4A4B0BF070F8C6\r\nS315000156780130012839D85A4B9E4203D1002D01D158\r\nS3150001568800F079FC301C291C434A444B0BF060F8A6\r\nS31500015698013001D100F073FC524B9E4203D1002D1B\r\nS315000156A801D100F01BFCE2239B009E4201D000F0D1\r\nS315000156B876FE002D01D000F072FE607A237A000290\r\nS315000156C81843A37A1B041843E37A617C1B06184323\r\nS315000156D8237C09021943A37C1B041943E37C1B069B\r\nS315000156E819430BF047F800F060FE3F4B9E4203D189\r\nS315000156F8002D01D100F05AFD301C291C284A294BDE\r\nS315000157080BF026F8013001280DD8384B9E4201D0FE\r\nS3150001571800F045FE002D01D000F041FE201C0BF0E3\r\nS315000157281BF800F042FE324B9E4203D1002D01D1F7\r\nS3150001573800F040FDE5239B009E4201D000F02FFEBC\r\nS31500015748002D01D000F02BFE207A0BF089F800F02D\r\nS315000157582CFEC046C046C0460303000000000000F8\r\nS3150001576819020000000000001003000000000000FC\r\nS315000157780004000000000000830300000000000090\r\nS315000157887103000000000000800300000000000013\r\nS3150001579889030000000000008503000000000000E6\r\nS315000157A89203000000000000030300001902000034\r\nS315000157B80103000011030000120300008303000027\r\nS315000157C871030000160300001503000072030000B0\r\nS315000157D881030000820300008C1620008903000063\r\nS315000157E88503000087030000920300008A03000076\r\nS315000157F893030000DA4B9E4203D1002D01D100F03C\r\nS31500015808AFFC301C291CCB4BC94A0AF0A1FF013059\r\nS31500015818012872D8C023DB009E4203D1002D01D195\r\nS3150001582800F012FC301C291CC34AC44B0AF090FF35\r\nS31500015838013001281CD88423DB009E4203D1002DA8\r\nS3150001584801D100F0C6FCA023DB009E4203D1002D46\r\nS3150001585801D100F0CBFCC34B9E4201D000F09FFD65\r\nS31500015868002D01D000F09BFDFFF788F900F09DFDA2\r\nS31500015878BD4B9E4203D1002D01D100F02BFC301CFB\r\nS31500015888291CAF4AAF4B0AF063FF013001D100F082\r\nS31500015898FEFBB64B9E4203D1002D01D100F03DFC23\r\nS315000158A8B34B9E4201D000F07AFD002D01D000F0E5\r\nS315000158B876FD607A237A00021843A37A1B041843FB\r\nS315000158C8E37A617C1B061843237C09021943A37CEE\r\nS315000158D81B041943E37C627E1B061943237E1202CD\r\nS315000158E81A43A37E1B041A43E37E1B061A43231C91\r\nS315000158F820330AF043FF00F058FDC423DB009E4223\r\nS3150001590802D1002D00D177E3301C291C8E4A8F4B1A\r\nS315000159180AF01EFF013001286FD8C223DB009E4220\r\nS3150001592802D1002D00D187E3301C291C884A894BF6\r\nS315000159380AF00EFF013001282CD88E4B9E4201D069\r\nS3150001594800F02DFD002D01D000F029FD607A237AA3\r\nS3150001595800021843A37A1B041843E37A617C1B06E9\r\nS315000159681843237C09021943A37C1B041943E37CCE\r\nS31500015978627E1B061943237E12021A43A37E1B0469\r\nS315000159881A43E37E1B061A43231C20330AF02CFF15\r\nS3150001599800F00BFD784B9E4202D1002D00D111E398\r\nS315000159A8764B9E4201D000F0FAFC002D01D000F0A2\r\nS315000159B8F6FC607A237A00021843A37A1B0418437B\r\nS315000159C8E37A617C1B061843237C09021943A37CED\r\nS315000159D81B041943E37C627E1B061943237E1202CC\r\nS315000159E81A43A37E1B041A43E37E1B061A43231C90\r\nS315000159F820330AF0DDFE00F0D8FC614B9E4202D14D\r\nS31500015A08002D00D108E3301C291C534A534B0AF0D8\r\nS31500015A189FFE013000D1F7E25A4B9E4202D1002D7A\r\nS31500015A2800D101E3C623DB009E4201D000F0B7FC9A\r\nS31500015A38002D01D000F0B3FC207A534BB3E3607A12\r\nS31500015A48237A00021843A37A1B041843E37A1B0638\r\nS31500015A581843FBF755FC98E1607A237A000218434C\r\nS31500015A68A37A1B041843E37A617C1B061843237C3B\r\nS31500015A7809021943A37C1B041943E37C627E1B06B6\r\nS31500015A881943237E12021A43A37E1B041A43E37E9B\r\nS31500015A981B061A43231C2033FBF740FB00F085FC49\r\nS31500015AA8281C291C2A1C0123FBF76AFE00F07DFC31\r\nS31500015AB8607A237A00021843A37A1B041843E37A0F\r\nS31500015AC8617C1B061843237C09021943A37C1B042A\r\nS31500015AD81943E37C1B0619430122FBF7C4FD00F0B9\r\nS31500015AE864FC617C237C09021943A37C1B041943CA\r\nS31500015AF8E37C627E1B06049E1943237E3F02120243\r\nS31500015B0837431A43069EA37E30041B0438431A43BF\r\nS31500015B18079FE37E3D061B0601341A432843E37FAC\r\nS31500015B28FCF7E2F800F041FCFBF7FBFB00F03DFC5B\r\nS31500015B380506000000000000000600000000000045\r\nS31500015B480206000000000000200600000000000018\r\nS31500015B5810060000000000002206000000000000F8\r\nS31500015B680506000001040000020600000306000005\r\nS31500015B7804060000060600001106000012060000D1\r\nS31500015B8822060000230600005C0C2000EF4E0125CA\r\nS31500015B983563607A237A00021843A37A1B041843F3\r\nS31500015BA8E37A617C1B061843237C09021943A37C0B\r\nS31500015BB81B041943E37C1B0619432A1CFBF7F8FC53\r\nS31500015BC87563F2E3607A237A00021843A37A1B0409\r\nS31500015BD81843E37A617C1B061843237C090219439F\r\nS31500015BE8A37C1B041943E37C1B061943FBF73AFD07\r\nS31500015BF8DBE3607A237A00021843A37A1B0418436D\r\nS31500015C08E37A617C1B061843237C09021943A37CAA\r\nS31500015C181B041943E37C1B061943FCF74FFAC4E33B\r\nS31500015C28A21CD07F631CDB7F00021843E31CDB7FC9\r\nS31500015C381B041843231DDB7FA21D1B06D17F1843B6\r\nS31500015C48631DDB7F09021943E31DDB7F1B0419432F\r\nS31500015C58231C0833DB7F1B0619432332231C1278C6\r\nS31500015C6828331B7812021A43231C2A331B781B0478\r\nS31500015C781A43231C2B331B781B061A43231C2C336C\r\nS31500015C881D7801331B781B022B43251C2E352D78D5\r\nS31500015C982D042B43251C2F352D782D062B43251C2A\r\nS31500015CA830352E7801352D782D023543261C3236AE\r\nS31500015CB8367836043543261C333636783606354368\r\nS31500015CC80095251C34352E7801352D782D0235435E\r\nS31500015CD8261C3636367836043543261C373636784A\r\nS31500015CE8360635430195251C38352E7801352D782C\r\nS31500015CF82D023543261C3A3636783B342478360449\r\nS31500015D08354324062C430294FCF7F6F94DE3607CEF\r\nS31500015D18237C00021843A37C1B041843E37C617EA1\r\nS31500015D281B061843237E09021943A37E1B04194344\r\nS31500015D38E37E01341B061943E27FFBF71CFF34E3BC\r\nS31500015D48607A237A00021843A37A1B041843E37A7C\r\nS31500015D58617C1B061843237C09021943A37C1B0497\r\nS31500015D681943E37C627E1B061943237E12021A43FA\r\nS31500015D78A37E1B041A43E37E01341B061A43E37F01\r\nS31500015D88FBF7ABFE11E3FCF703FB00950195FF203A\r\nS31500015D98291C2A1C2B1C01F075FC06E3617E237E57\r\nS31500015DA809021943A37E1B041943E37E207C1B06C3\r\nS31500015DB801341943E27FFCF761FDF6E2607A237A42\r\nS31500015DC800021843A37A1B041843E37A627E1B0672\r\nS31500015DD81843237E12021A43A37E1B041A43E37E49\r\nS31500015DE8217C1B0601341A43E37FFCF791FDDCE2B3\r\nS31500015DF8607A237A00021843A37A1B041843E37ACC\r\nS31500015E081B061843FEF786F8CFE2607A237A00026A\r\nS31500015E181843A37A1B041843E37A1B061843637BCA\r\nS31500015E28227B1B021343A27B12041343E27B120655\r\nS31500015E3813431843211C431E98412031FEF7C0F92C\r\nS31500015E48B3E2FAF7CFFAB0E2037A407A00021843CE\r\nS31500015E58A37A1B041843E37A617C1B061843237C47\r\nS31500015E6809021943A37C1B041943E37C627E1B06C2\r\nS31500015E781943237E12021A43A37E1B041A43E37EA7\r\nS31500015E881B061A43231C2033FAF7D2FF8DE2607AE8\r\nS31500015E98237A00021843A37A1B041843E37A1B06E4\r\nS31500015EA81843FAF7B9FC80E2607A237A00021843AC\r\nS31500015EB8A37A1B041843E37A1B061843FAF7C2FCB4\r\nS31500015EC873E2607A237A00021843A37A1B04184303\r\nS31500015ED8E37A1B061843FAF7C1FD66E2607A237A6C\r\nS31500015EE800021843A37A1B041843E37A617C1B0654\r\nS31500015EF81843237C09021943A37C1B041943E37C39\r\nS31500015F08627E1B061943237E12021A43A37E1B04D3\r\nS31500015F181A43E37E1B061A430AF086FC45E2607CB7\r\nS31500015F28237C00021843A37C1B041843E37C617A93\r\nS31500015F381B061843237A09021943A37A1B0419433A\r\nS31500015F48E37A1B0619430AF05DFC2EE200F4FFFF13\r\nS31500015F58607A237A00021843A37A1B041843E37A6A\r\nS31500015F681B0618430AF08AFC1FE20AF0AFFB1CE283\r\nS31500015F78207ADD4B17E1201C0AF048FC15E2607A0D\r\nS31500015F88237A00021843A37A1B041843E37A617C37\r\nS31500015F981B061843237C09021943A37C1B041943D6\r\nS31500015FA8E37C627E1B061943237E12021A43A37EF3\r\nS31500015FB81B041A43E37E1B061A43231C20330AF0EB\r\nS31500015FC809FCF2E1607A237A00021843A37A1B04DA\r\nS31500015FD81843E37A1B061843637B227B1B02134390\r\nS31500015FE8A27B12041343E27B120613431843431E92\r\nS31500015FF898410AF099FBD8E1231C207A217C227E5C\r\nS3150001600820330AF07DFBD0E1231C207A217C227EF5\r\nS3150001601820330AF057FBC8E1231C207A217C227E13\r\nS3150001602820330AF0AFFBC0E1231C207A217C227EB3\r\nS3150001603820330AF081FBB8E1231C207A217C227ED9\r\nS3150001604820330AF017FCB0E1607A237A000218437C\r\nS31500016058A37A1B041843E37A617C1B061843237C45\r\nS3150001606809021943A37C1B041943E37C627E1B06C0\r\nS315000160781943237E12021A43A37E1B041A43E37EA5\r\nS315000160881B061A43231C20330AF036FB8DE1607A7E\r\nS31500016098237A00021843A37A1B041843E37A617C26\r\nS315000160A81B061843237C09021943A37C1B041943C5\r\nS315000160B8E37C627E1B061943237E12021A43A37EE2\r\nS315000160C81B041A43E37E1B061A43231C20330AF0DA\r\nS315000160D8D5FA6AE1607A237A00021843A37A1B0487\r\nS315000160E81843E37A617C1B061843237C090219438A\r\nS315000160F8A37C1B041943E37C627E1B061943237E9A\r\nS3150001610812021A43A37E1B041A43E37E1B061A4393\r\nS31500016118231C20330AF06CFB47E1607A237A0002DC\r\nS315000161281843A37A1B041843E37A617C1B061843B8\r\nS31500016138237C09021943A37C1B041943E37C627E71\r\nS315000161481B061943237E12021A43A37E1B041A4314\r\nS31500016158E37E1B061A43231C20330AF061FB24E164\r\nS31500016168607A237A00021843A37A1B041843E37A58\r\nS31500016178617C1B061843237C09021943A37C1B0473\r\nS315000161881943E37C627E1B061943237E12021A43D6\r\nS31500016198A37E1B041A43E37E1B061A43231C2033E2\r\nS315000161A80AF056FB01E100F085F9FEE04F4B00F0DD\r\nS315000161B881F9FAE0211C207A20310AF049FAF4E043\r\nS315000161C8FEF704FDF1E0FEF7F1FBEEE0FEF752FC07\r\nS315000161D8EBE0607A237A00021843A37A1B0418437A\r\nS315000161E8E37A1B061843FEF745FEDEE0E0200AF0D7\r\nS315000161F87FFAC82000F000FE3D4B04225A63D4E022\r\nS31500016208049E059F021C0B1C921BBB41002B36D119\r\nS31500016218802189008A4232D8637A217A1B020B438C\r\nS31500016228A17A09040B43E17A09060B433149EB18B4\r\nS315000162385B1882200093291C01928000002301F03B\r\nS3150001624821FA8027BF00ED19637C227C1B021343C8\r\nS31500016258A27C12041343E27C1206101C1843637DC8\r\nS31500016268227D1B021343A27D12041343E27D12060B\r\nS315000162780021134305910495191EC1D102E0194B5A\r\nS31500016288174AC9E7A842BBD8009301931A1CFF20F5\r\nS3150001629801F0F8F9164E80235B00736385E0607A96\r\nS315000162A8237A00021843A37A1B041843E37A1B06D0\r\nS315000162B81843104B211CC0182031302200F096FEDD\r\nS315000162C863E5607A237A00021843A37A1B0418430C\r\nS315000162D8E37A1B061843FEF7B1FC66E0C046C046E2\r\nS315000162E80002000000000000780920006424200054\r\nS315000162F800F4FFFF142C2000637B049E227B3F02DF\r\nS315000163081B0237431343069EA27B35041204079EDC\r\nS315000163181343E27B3D43370612063D4313430320ED\r\nS3150001632800212A1C0AF014FA01303ED0032D3CD86C\r\nS31500016338281C0AF019F80205080B8020400307E01B\r\nS315000163488020C00304E08020000301E08020800350\r\nS315000163580AF086F929E000F017FFFA20800000F01C\r\nS315000163684BFDFA20800000F047FD124A124B1A60D5\r\nS31500016378FEE7124B9A79D70701D501225A7100F027\r\nS3150001638803FF0C4A0C4B1A60FEE70C4A917901226D\r\nS3150001639811400A3100930193181C1A1CFBE40848A2\r\nS315000163A80849321C2B1CFEF7EFFA09B0F0BC01BCF8\r\nS315000163B80047C046010000A500FDFFFFE0FF2000E1\r\nS315000163C8761812008118120030B5314C6420A544A4\r\nS315000163D800F012FD2F4C6278237812021A43A37833\r\nS315000163E81B041A43E3781B061A432B4B9A4202D124\r\nS315000163F82379012B0ED0201C00210F2200F002FE6A\r\nS31500016408502323704D2363703323A3704323E37012\r\nS3150001641801232371A37902221343A3711F4C042379\r\nS31500016428636380239340802563636D00012365635D\r\nS31500016438636300F0BBFE1A4A40230B21636763605E\r\nS31500016448156011642361174B80221A60164B1202DC\r\nS315000164581A600AF001F900F069FD01F05BF80028FD\r\nS3150001646809D088218900684601F066F8011E02D024\r\nS315000164786846FEF7F5FD0D4A0D4BFA201A608000B5\r\nS3150001648800F04CFC0028E8DDFEF72AFCE5E7C046EB\r\nS31500016498DCFDFFFFE0FF2000504D334300F4FFFF12\r\nS315000164A800FCFFFF0000FEFF0040FDFF010000A504\r\nS315000164B840FDFFFF1847C046F0B59DB007900F9203\r\nS315000164C81C1C002801D1A94D07950F9B023B222BC5\r\nS315000164D801D90A260F9600230493079D08951F1CC8\r\nS315000164E8CA1AD619079A58428446151C654408984B\r\nS315000164F8EA5D0130252A08D066468D19EA55013725\r\nS31500016508002A00D149E30890EAE7049D002DF3D15A\r\nS3150001651820250B95049D0E97029611950D951095BC\r\nS315000165280A950695099503950C95059501952B1CD4\r\nS315000165382A1C411C07910178081C2338572800D9C1\r\nS3150001654845E209F01BFF580044026A00440244026E\r\nS31500016558440244026F006400440267009C0044023E\r\nS315000165685B0061006100610061006100610061001A\r\nS3150001657861006100440244024402440244024402A6\r\nS315000165884402440244024402080144024402440209\r\nS3150001659844024402440244024402440244024402BC\r\nS315000165A844024402440244024402440244024402AC\r\nS315000165B8E5014402440244024402440244024402FC\r\nS315000165C8440244029E0001011402440244024402A8\r\nS315000165D84501140250014402530144025A01EA01D9\r\nS315000165E87A01850187018D01DE01E1014402440238\r\nS315000165F8EF011702E70101200C9003E0002B03D1FC\r\nS3150001660830210B91079894E7009100211DE00121A3\r\nS315000166180391F7E701200590F4E7029D252301364A\r\nS315000166282B708FE0211D2068002B0BD101900C1CCB\r\nS315000166380028E7DA05980121814305910199494224\r\nS315000166480191DFE711900C1C19E00A208446081C09\r\nS315000166586146414300980918079800780090302050\r\nS31500016668404284460098844460463039092803D854\r\nS31500016678079801300790E8E7002BE1D01191012333\r\nS31500016688C0E76368256801951D780393002213AB5B\r\nS315000166980595019F1A7008340133381C05991D1C8C\r\nS315000166A80AF052F8324B5B5C381C2B7005990AF0DC\r\nS315000166B88DF86B1C071EF0D1331C0E9E0298321AF8\r\nS315000166C82878D7181E1C002803D01870013D0133FD\r\nS315000166D8F3E7019D002D02D13B1C311CFDE6039A0F\r\nS315000166E801321378002B27D0013B01259D402B1C35\r\nS315000166F8019D511C1D4216D03C23002800D02C2395\r\nS3150001670833707B1CF01BC0187D4284465019C05C4F\r\nS31500016718D11BC918202803DD7519E8540133F1E79F\r\nS315000167286646012005E00B78202B01D90131FAE7ED\r\nS315000167383B1C1F1C0A1CD4E7331C0028CCD03E2264\r\nS315000167481A7001360137C7E72068029D013628709D\r\nS3150001675801370434C0E76368019D2268029308344F\r\nS31500016768002D0CD11025019509E0C046921812009A\r\nS31500016778820B120001996546059F01950E1C019829\r\nS31500016788019D8446012040428444002DA4D01178FD\r\nS31500016798BA4B0909595C317015780F2028401B5CE2\r\nS315000167A8B11C73706046BE1C059601320028E2D002\r\nS315000167B83B1C9D1C029805957E42CD1BED18801940\r\nS315000167C80195C55C002DD5D08E19F5540133F0E736\r\nS315000167D80699002902D10121069113E700210691A4\r\nS315000167E8012109910EE701210A910BE7002A01D13E\r\nS315000167F8012207E70125002204E70A99231D00293A\r\nS3150001680818D1002D04D02268F917176051600FE0DE\r\nS31500016818002A0FD10D9A002A0CD1069D002D02D00F\r\nS315000168282268178004E00999002903D022681770A5\r\nS315000168381C1C51E722681760FAE7019800214542B6\r\nS31500016848454110220C95231D256803910292A0E16A\r\nS315000168580125D7E6039B002B00D08EE00F985FE059\r\nS31500016868226804340292002A01D1854D029500203E\r\nS31500016878002B08D1029800F0E3FB07E0029D2B5C90\r\nS31500016888002B03D0013011998842F7DB019D2B1AA1\r\nS31500016898059D002D08D1002B06DD321CF11807E0F5\r\nS315000168A8FF180123161C5B42391803913A1C05E0AF\r\nS315000168B88A42F5D00B9D15700132F9E7039DAA426C\r\nS315000168C80AD079428C4602990D1C6544AD5CB444E4\r\nS315000168D861468D540132F1E72F1C059D3618002DAE\r\nS315000168E800D1F9E6002B00DCF6E6321CF0188242EC\r\nS315000168F803D00B9E16700132F9E70398161CC718C8\r\nS31500016908EAE6012110917DE6002303930A2007E0B8\r\nS31500016918012108E001210D9174E600230393082063\r\nS31500016928029003E000211023039102930A99231D83\r\nS3150001693800291AD1002D05D0072307349C43231CAF\r\nS31500016948083312E0109D231D002D0ED1002A0CD10B\r\nS315000169580D99002909D1069A002A01D0258818E13E\r\nS31500016968099D002D01D0257813E1256811E10A203A\r\nS31500016978029004E01021029101E00F9B02930A990B\r\nS31500016988002902D02568043438E0002D06D0E31D1D\r\nS31500016998072293431C1C08341D682FE0109D231DF4\r\nS315000169A8002D01D1002A01D025680EE00D99256830\r\nS315000169B800290AD1069A002A02D02D042D1404E0D2\r\nS315000169C80999002901D02D062D0E1C1C16E00E9ED4\r\nS315000169D8029D0899AA1B0E9D7342D6194A1B079D4B\r\nS315000169E8D219954207D90899029DCA18D25DEB18A2\r\nS315000169F8DA550137EBE7012504956DE6002D00DB35\r\nS31500016A08C3E000220123039208936D4268460022DF\r\nS31500016A1813AB4D301A7009900A950A98029909F034\r\nS31500016A2893FE099A154B039806925B5C00280BD0D6\r\nS31500016A381A1C613A1206120E002119209042494188\r\nS31500016A4849015B1A1B061B0E09990A980B700299D4\r\nS31500016A5809F0BCFE099A01320A9009920028DCD194\r\nS31500016A68069B0C9813AA9A1A00280FD0002D0DD050\r\nS31500016A780299082906D1013208E0C046820B1200A4\r\nS31500016A889E181200029B102B00D102320898059914\r\nS31500016A981218002917D10B9B302B14D00198002806\r\nS31500016AA811D0801A019000280DDD331C31188B4254\r\nS31500016AB803D00B9E1E700133F9E71E1C01230198B2\r\nS31500016AC85B4201933F18089B391C002B03D02D23E9\r\nS31500016AD83370013101360C98002812D0002D10D0E0\r\nS31500016AE8029D082D04D1302333700131013608E0A7\r\nS31500016AF8029D102D05D1302333707823737002312E\r\nS31500016B080236059D002D02D1019D002D02D1B44604\r\nS31500016B18301C13E0019DAD1A0195002DF7DD331CDC\r\nS31500016B287019834203D00B9E1E700133F9E7019D4C\r\nS31500016B381E1C01235B4249190193E8E76346CD1AF6\r\nS31500016B482D1802952F1C069D2B78061C002B05D0A7\r\nS31500016B58069E013E037006960130EFE7059D002D5E\r\nS31500016B6800D1B9E5019D002D00D1B5E5AA1A002A83\r\nS31500016B7800DCB1E58318984203D00B9E06700130FC\r\nS31500016B88F9E7061C02988718A6E5002003900890E5\r\nS31500016B983CE700211C1C089138E7381C1DB0F0BCE5\r\nS31500016BA802BC084710B5041C131C081C0A22211C28\r\nS31500016BB8FFF782FC10BC02BC08470EB403B503AB51\r\nS31500016BC804CB011C101C0A220193FFF775FC02B0C5\r\nS31500016BD808BC03B01847C046072303405A1E934111\r\nS31500016BE8C0081818704730B50022131C8B4209DA01\r\nS31500016BF8051CDD4001242C404D1EED1AAC406240B7\r\nS31500016C080133F3E7101C30BC02BC084710B5013A42\r\nS31500016C1805D30C069854000A2043090AF7E710BC65\r\nS31500016C2801BC004730B54218031C0020011C9342E1\r\nS31500016C3807D01D78040E09020002284321430133B7\r\nS31500016C48F5E730BC04BC1047054B01225A63802284\r\nS31500016C5852005A63802292005A6304225A6370478B\r\nS31500016C6800F4FFFFF0B5002803D0234941438912F8\r\nS31500016C7800E02249224E8024F36B240400201C40A4\r\nS31500016C88844235D11F4B01225A601F4A0A231360D9\r\nS31500016C981E4B54609360D3681B041B0CD068802577\r\nS31500016CA80004000C2D04002C0FD1F76B2F4206D0DF\r\nS31500016CB8154BDB681B041B0C012415490EE05D18F6\r\nS31500016CC82D042D0CA84209D10CE0F46B2C420BD0F3\r\nS31500016CD85C182404240CA04208D001240D4D0E484A\r\nS31500016CE80560DBE7012003E0022000E001204042C5\r\nS31500016CF8F0BC02BC0847C04680BB00001BB70000B9\r\nS31500016D0800F4FFFF00C0FCFF00C2FCFFFFFF00000C\r\nS31500016D188D5B0000010000A540FDFFFF70B500284E\r\nS31500016D2803D0184D4543AD1200E0174D174B80228D\r\nS31500016D38D96B120400200A401E1C82421ED1144B34\r\nS31500016D4801215960134B0A2119605A60124A9A6047\r\nS31500016D58DA681204120CDC68F16B2404240C0802AC\r\nS31500016D6808D451190904090C8C4206D00B480C4960\r\nS31500016D780860F0E70120404200E0012070BC02BC37\r\nS31500016D880847C04680BB00001BB7000000F4FFFFA0\r\nS31500016D9800C0FCFF00C2FCFFFFFF0000010000A5C8\r\nS31500016DA840FDFFFF302358430E4B012210B55A60B0\r\nS31500016DB80D4B0A221A6000225A600C4A9A60DA6858\r\nS31500016DC812048012120CDC68111824040904240C1C\r\nS31500016DD8090C8C4203D0064C06490C60F3E710BC3B\r\nS31500016DE801BC004700C0FCFF00C2FCFFFFFF00001A\r\nS31500016DF8010000A540FDFFFF08B5FA239B00584393\r\nS31500016E08FFF7D0FF08BC01BC0047F8B50126031CF3\r\nS31500016E18064003D080201A4A8000106302251D40CF\r\nS31500016E2802D0174A0120106304241C4003D0802095\r\nS31500016E38134A4000106308271F4002D0104B042252\r\nS31500016E481A63002918D0081CFFF7D6FF002E03D0B5\r\nS31500016E5880220B4B92005A63002D02D0084B012267\r\nS31500016E685A63002C03D08022054B52005A63002F27\r\nS31500016E7802D0034B04225A63F8BC01BC0047C04642\r\nS31500016E8800F4FFFF70B51E1C0D1C00230370111CB6\r\nS31500016E982A1C041C00F0DDF87278337812021A43B2\r\nS31500016EA8B3781B041A43F3781B061A43184B9A4204\r\nS31500016EB802D0201C174925E03379012B02D0201C6A\r\nS31500016EC815491FE07379002B02D1201C134919E0DB\r\nS31500016ED8F11D201C2A1C00F0BCF8B379002B02D145\r\nS31500016EE8201C0F4903E0022B04D10E49201C2A1C41\r\nS31500016EF800F0AFF80C49201C2A1C00F0AAF8311C36\r\nS31500016F081031201C2A1C00F0A4F870BC01BC0047F3\r\nS31500016F18504D3356A5181200C9181200EC18120064\r\nS31500016F280E1912001719120085171200014A024B91\r\nS31500016F381A6070471D00040020FDFFFF0E4BE0227A\r\nS31500016F481969D2010A431A610C4B1A1CC432192158\r\nS31500016F5811600B4A0220C021186009025A600122F9\r\nS31500016F685A61D96107490860062048601A600A60B3\r\nS31500016F7880310A607047C04600FCFFFF0000FAFF37\r\nS31500016F8802C046004000FAFF114BE022D20110B5BB\r\nS31500016F981A61104B1A1CC432262111600E490F4A78\r\nS31500016FA802240C604A600422CA610D4A1C60002052\r\nS31500016FB85A6001225A61D8610A4804600A4C446041\r\nS31500016FC81A600A60803102600A6010BC01BC004781\r\nS31500016FD800FCFFFF0000FAFF4000FAFF409118008D\r\nS31500016FE8058006008000FAFF0780000010B500231F\r\nS31500016FF8D41A002C03DDCC5CC4540133F8E710BC69\r\nS3150001700802BC084710B5031C8418E41A002C02DDDB\r\nS3150001701819700133F8E710BC02BC084730B50023E4\r\nS31500017028D41A002C08DDC55C0133CC18013C247840\r\nS31500017038A542F5D0281B00E0002030BC02BC084759\r\nS31500017048021C031C1978981A002901D00133F9E7A3\r\nS31500017058704770B5041C0D1C161CFFF7F1FF0023C1\r\nS31500017068B34206D0EA5C002A03D02118CA54013378\r\nS31500017078F6E7E31800221A54201C70BC02BC084724\r\nS3150001708838B5041C0D1CFFF7DBFF0023EA5C002A58\r\nS3150001709803D02118CA540133F8E7E3181A54201CFF\r\nS315000170A838BC02BC084710B5041CFFF7C9FF231CEE\r\nS315000170B801381A1B824206DA1A78215C19702254A1\r\nS315000170C801330138F5E710BC01BC0047F7B5C21713\r\nS315000170D8861801900C1C56400025301C0A2109F01F\r\nS315000170E845FB631930311970301C0A2109F028FB58\r\nS315000170F86F1C061E01D03D1CEFE7019A3B1C002AB6\r\nS3150001710802DA2D22E254AF1C0023E355201CFFF7B7\r\nS31500017118CAFFF7BC01BC004737B5141E082C00D9B5\r\nS3150001712808240B19994203D00D7801310565F9E751\r\nS31500017138056B01231D4204D1036B10252B43036301\r\nS315000171480AE0056B9D430563036BDD07FCD4F3E792\r\nS31500017158019D01231D4209D1036B0193019D022360\r\nS315000171681D42F5D0026B9A4302630AE0121BD4D181\r\nS31500017178026B1A4205D0026B9A430263036BDA0764\r\nS31500017188FCD437BC01BC0047064B802252045A6125\r\nS31500017198054B1B688022D9695201114200D01A6237\r\nS315000171A87047C04600F4FFFF50002000104B37B56A\r\nS315000171B8D968802252050A43DA600E4B0E4D8022A9\r\nS315000171C880241A60640412011A612C602C616C63B4\r\nS315000171D8FFF7DAFF00230193019A084B9A4202D876\r\nS315000171E8019B0133F7E72C632C6137BC01BC0047CF\r\nS315000171F820FCFFFF00FCFFFF00F4FFFFFFFF0F006D\r\nS31500017208036B102213430363026B01231A42FBD05B\r\nS31500017218026B9A430263036BDA07FCD47047036B6C\r\nS31500017228202213430363036B1A07FCD5036B282239\r\nS3150001723893430363026B28231A42FBD17047F0B5C7\r\nS31500017248974E3068036B85B05A0700D424E1036D65\r\nS31500017258056D046D026DFF210C4012021443019560\r\nS31500017268026D056D0A402D022A43056D2940056DFB\r\nS315000172782D0229432404120409040093240C120C38\r\nS31500017288090C1B0604D4056B0427BD43056307E0F7\r\nS31500017298056B80273D430563056B2F06FCD5F2E791\r\nS315000172A8036B04251D40FBD1019FFF231F403F02AD\r\nS315000172B80197009F1F40019B3B437A4FBB4200D178\r\nS315000172C8E5E017DC802149008B4200D1E2E009DCC8\r\nS315000172D8812B00D181E0822B00D182E0802B00D066\r\nS315000172E8D8E07AE0812149008B4200D1A6E000DB93\r\nS315000172F8D0E0CCE088273F01BB426BD00CDCA0254F\r\nS31500017308ED00AB423FD0D025ED00AB4219D066491E\r\nS315000173188B4200D0BEE083E0644A934200D1A6E0E6\r\nS3150001732804DC90221201934238D0B3E0604A9342BA\r\nS3150001733800D1A4E05F4A934200D0ABE05E4B5C709B\r\nS31500017348A5E080235B009C4205D11222914200D818\r\nS315000173580A1C5A4998E080239B009C4206D1432285\r\nS31500017368914200D80A1C554912318DE0C0239B0071\r\nS315000173781C409C4200D08DE01A22914200D80A1C7A\r\nS315000173884E49553180E0FFF73BFF802233685200B2\r\nS3150001739822439A60621E94415C607DE0464B1C70F4\r\nS315000173A8FFF72EFF62426241336802218A1A5A6048\r\nS315000173B8002C01D082252D0200225D63944201D062\r\nS315000173C8862212029A630022944201D0872212026F\r\nS315000173D8DA6361E03849012256E069460E310D80CB\r\nS315000173E81CE069460F2344680E31134002220D80C2\r\nS315000173F8144209D0032B07D80C3393401C58012398\r\nS31500017408E40BA3430B803FE044680122144241D0B8\r\nS31500017418002B3FD1036BDB0B9A430A80022233E030\r\nS31500017428002C37D10F231A40531E1B041B0C022BA9\r\nS3150001743830D80C3292000023135028E0002C29D1B1\r\nS315000174480F231A40531E1B041B0C022B22D8012A98\r\nS3150001745803D182231B02436319E0022A03D186233F\r\nS315000174681B02836313E085231B02C3630FE0026BD0\r\nS3150001747802231A42FBD0026B9A43026307E00822F1\r\nS31500017488914200D80A1C311DFFF746FE04E0FFF7BA\r\nS31500017498B7FE01E0FFF7C3FE05B0F0BC01BC00472B\r\nS315000174A85000200001030000020300002120000013\r\nS315000174B8A121000021220000602A2000A70B12004A\r\nS315000174C8124B07B51B68DA690192019980225201AC\r\nS315000174D811420CD01A62012252429A6200229A6221\r\nS315000174E8802252009A60802212021A6306E00199EC\r\nS315000174F80122114202D01A62FFF7A1FE044B187845\r\nS31500017508431E984103B002BC0847C04650002000FC\r\nS31500017518602A200008B5FFF7D3FF002806D0054BDF\r\nS315000175281A681B7B506B1840431E984108BC02BC65\r\nS315000175380847C04650002000F7B580231A4F9B0123\r\nS3150001754801903C7B00930E1C0025002E26D0FFF7E8\r\nS31500017558B7FF002822D03A68536B234219D0516BE2\r\nS31500017568331C090CB14201D2536B1B0CF61A5B1979\r\nS315000175789D4205D03A680199526D4A550135F7E79A\r\nS315000175883B685A6BA2435A63022C01D1402400E09E\r\nS315000175980224009B013B0093002BD6D1281C3C7387\r\nS315000175A8FEBC02BC0847C0465000200070B5061C48\r\nS315000175B80C1E01D100204BE0FFF782FF0028F9D00D\r\nS315000175C8231E3F2B00D93F23234D2A68E41A301C7A\r\nS315000175D8F318984203D0017801309165F9E7061C42\r\nS315000175E82B689A6B10210A439A63002C24D0231E18\r\nS315000175F83F2B00D93F232A68E41A301CF318984216\r\nS3150001760803D0017801309165F9E7061C2B68996B5F\r\nS315000176180122114205D1FFF753FF0028F6D1201C9C\r\nS3150001762816E0996B914399639A6BD107FCD4D7E716\r\nS31500017638FFF746FF0028BDD02B68996B012211423E\r\nS31500017648F6D0996B914399639A6BD107FCD4B1E74C\r\nS3150001765870BC02BC0847C0465000200010B5041C87\r\nS31500017668FFF758FF002808D08821201C8900FFF75A\r\nS3150001767863FF034A83185842584110BC02BC0847A5\r\nS31500017688E0FDFFFFF0B51B4CA5448F9F00256E4614\r\nS315000176980024AC5588260135B600B542F7D10090CD\r\nS315000176A88E98019402910394049205940693079483\r\nS315000176B8A0420CD1882168468900FFF777FF43422B\r\nS315000176C8584189239B009D44F0BC02BC0847002F02\r\nS315000176D8F0D080233A1C9B009F4200D91A1C002334\r\nS315000176E88E9E00ACE118F05C20310133087093429C\r\nS315000176F8F6D3DFE7DCFDFFFF0030E0E3800010E3AF\r\nS315000177080121A0E3CF2B0315CB2B03050222A0E30E\r\nS31500017718CF2B03E50010E0E3CB2B03E5400010E394\r\nS315000177280131A0E3CF3B0115CB3B01050030E0E376\r\nS31500017738CF2B03E5200010E3CB2B03E50121A0E3C2\r\nS31500017748CF2B0315CB2B03050222A0E3CF2B03E591\r\nS315000177580010E0E3CB2B03E5100010E30131A0E3B1\r\nS31500017768CF3B0115CB3B01050030E0E3CF2B03E509\r\nS31500017778080010E3CB2B03E50121A0E3CF2B03156A\r\nS31500017788CB2B03050222A0E3CF2B03E50010E0E390\r\nS31500017798CB2B03E5040010E30131A0E3CF3B011530\r\nS315000177A8CB3B01050030E0E3CF2B03E5020010E3F4\r\nS315000177B8CB2B03E50121A0E3CF2B0315CB2B030527\r\nS315000177C80222A0E3CF2B03E50010E0E3CB2B03E570\r\nS315000177D8010010E30131A0E3CF3B0115CB3B0105C5\r\nS315000177E80030E0E3CF2B03E5CB2B03E51EFF2FE1AA\r\nS315000177F8F0412DE90133A0E30040E0E3EF3B04E566\r\nS315000178080050A0E1FF3B04E53200A0E3CF3B04E5CD\r\nS315000178180170A0E10280A0E1FD2300EB0430A0E3A2\r\nS31500017828CF3B04E508319FE50162A0E3EB3B04E5A4\r\nS31500017838FF3B04E59B3B04E50232A0E3CF6B04E57D\r\nS31500017848CB3B04E50131A0E3CB3B04E50732A0E3DA\r\nS31500017858EF3B04E53200A0E3CB6B04E5EC2300EB38\r\nS31500017868CF6B04E5CC009FE50030E0E3C32B13E5BD\r\nS31500017878100012E30900001A010050E2F9FFFF1A8D\r\nS31500017888010000EA000052E32400001A022CA0E3DA\r\nS31500017898CF2B03E50420A0E3CF2B03E5220000EA62\r\nS315000178A8000058E30540A0010C00000A033015E268\r\nS315000178B80100000A7C209FE5160000EA072063E024\r\nS315000178C8000052E3FAFFFFDA014083E2033023E2C4\r\nS315000178D80300D5E787FFFFEB0430A0E1F6FFFFEAD7\r\nS315000178E8073085E0033064E0000053E3F0FFFFDA78\r\nS315000178F80100D4E47FFFFFEBF8FFFFEA0030E0E385\r\nS31500017908C31B13E5020311E3DDFFFF1A0212A0E30D\r\nS31500017918CF1B03E5CB1B03E5012052E2F6FFFF2A45\r\nS315000179280420A0E30030E0E3CB2B03E5F041BDE8FA\r\nS315000179381EFF2FE110000008A08601000030E0E3D9\r\nS315000179481F2BA0E3FB2B03E51E2BA0E38F2B03E5DF\r\nS31500017958012BA0E38B2B03E52020A0E3EF2303E50E\r\nS31500017968000050E31F3AE0E30120A0E3FF2F03E5FF\r\nS315000179780600000A020050E10900001A2C209FE5C2\r\nS31500017988FB2F03E528209FE5C72F03E51EFF2FE1FF\r\nS3150001799820209FE5FB2F03E51C209FE5CF2F03E55C\r\nS315000179A81EFF2FE10220A0E3FF2F03E51EFF2FE1B3\r\nS315000179B811000B001206010111000E0082060101D9\r\nS315000179C80030E0E31E29A0E38F2B03E50228A0E39C\r\nS315000179D8FB2B03E5012CA0E3EF2303E52B3AE0E3B8\r\nS315000179E80229A0E3FF2F03E520209FE58710A0E3E6\r\nS315000179F8EF2F03E5EB1F03E514109FE5E71F03E5EA\r\nS31500017A08EB1F13E5E31F03E5FF2F03E51EFF2FE138\r\nS31500017A180101000002050000000050E31EFF2F01CE\r\nS31500017A282B3AE0E30220A0E3DF2E03E5FF0E03E590\r\nS31500017A38FB1E03E5EF0E03E50100A0E3EB1E03E5DC\r\nS31500017A48DF0E03E51EFF2FE194C09FE5F0002DE947\r\nS31500017A5818009CE8000054E308609C151D00000A04\r\nS31500017A68060053E11B00002A00C0D3E561404CE241\r\nS31500017A78FF4004E2040054E31600008A65005CE353\r\nS31500017A88034083020250D3050130D3050140831216\r\nS31500017A98033CA0010170D4E5053883000030A0132A\r\nS31500017AA8025084E20040D4E5033087E0043483E0E1\r\nS31500017AB865005CE3FF0053130600008A00005CE1E1\r\nS31500017AC8005081050100A003003082050200000A6A\r\nS31500017AD8033085E0E1FFFFEA0000A0E3F000BDE81E\r\nS31500017AE81EFF2FE1642A200037402DE98C409FE5CF\r\nS31500017AF80030A0E388009FE588109FE50D20A0E3EC\r\nS31500017B08043084E5202300EB005050E20D00001AF2\r\nS31500017B1874309FE5003084E570309FE56500A0E389\r\nS31500017B28083084E50D10A0E10130A0E304208DE2C0\r\nS31500017B38043084E5C3FFFFEB000050E303009D1802\r\nS31500017B480520A0110900001A44009FE5003090E5C0\r\nS31500017B58010073E30600001A042090E534309FE51E\r\nS31500017B68030052E10200001A2C109FE50120A0E350\r\nS31500017B781EFFFFEB0CD08DE23040BDE81EFF2FE162\r\nS31500017B88642A2000160C1200002010000D20100097\r\nS31500017B98BCC4100000201000665599AA70A4000004\r\nS31500017BA873402DE90030A0E30040A0E10150A0E1B7\r\nS31500017BB80030C0E50D10A0E16500A0E304208DE2C8\r\nS31500017BC8A0FFFFEB000050E3015045E20400A0E1ED\r\nS31500017BD8B8109F052800000AB4109FE50520A0E10A\r\nS31500017BE8EC2200EB6300A0E30D10A0E104208DE276\r\nS31500017BF894FFFFEB000050E30D00000A00609DE5CD\r\nS31500017C0804309DE5033086E0013053E5000053E377\r\nS31500017C180700001A7C109FE50520A0E10400A0E1F9\r\nS31500017C28DC2200EB0400A0E10610A0E10520A0E19A\r\nS31500017C38D82200EB6400A0E30D10A0E104208DE238\r\nS31500017C4880FFFFEB000050E30D00000A00609DE590\r\nS31500017C5804309DE5033086E0013053E5000053E327\r\nS31500017C680700001A30109FE50400A0E10520A0E1F5\r\nS31500017C78C82200EB0400A0E10610A0E10520A0E15E\r\nS31500017C88C42200EB08D08DE27040BDE81EFF2FE14B\r\nS31500017C982019120055191200661912006B191200E3\r\nS31500017CA838402DE90040A0E10000A0E30150A0E121\r\nS31500017CB821FFFFEB1F3AE0E3EF2F13E5020C12E376\r\nS31500017CC8FBFFFF0A015485E3044085E1F34F03E511\r\nS31500017CD83840BDE81EFF2FE10010A0E1010AA0E32C\r\nS31500017CE8EEFFFFEA0030E0E31E27A0E3EF2B03E5F2\r\nS31500017CF8FF2B03E50227A0E3CB2B03E50226A0E32E\r\nS31500017D08CB2B03E50125A0E3CB2B03E50126A0E355\r\nS31500017D18CB2B03E5CF0B03E51EFF2FE10000E0E3C4\r\nS31500017D28023AA0E3EF3300E544209FE544309FE59E\r\nS31500017D380510A0E3002083E501C9A0E35F3AE0E36B\r\nS31500017D480220A0E3BF2F03E5BB2F03E5BF1F03E511\r\nS31500017D58EFC300E520C09FE520009FE500C080E550\r\nS31500017D687F2F03E50120A0E37B2F03E57F1F03E5B2\r\nS31500017D781EFF2FE14000FAFFD0CA20008000FAFF5B\r\nS31500017D88D8CA2000F0472DE9D4409FE5003094E594\r\nS31500017D980520A0E3002083E50050A0E10180A0E1D1\r\nS31500017DA8102093E5010052E3FCFFFF8A0060A0E37F\r\nS31500017DB8080056E1003094E5180000AA107093E512\r\nS31500017DC84A1E00EB01A005E20030E0E30228A0E329\r\nS31500017DD800005AE1CB2B03E5001094E51E9087E2DB\r\nS31500017DE8A550A0E1967087125A708702102091E576\r\nS31500017DF8090052E1FCFFFF3A0228A0E3CF2B03E575\r\nS31500017E080100A0E31D1E00EB002094E5103092E569\r\nS31500017E18070053E1FCFFFF3A016086E2E3FFFFEA50\r\nS31500017E28101093E50020E0E30208A0E3CB0B02E57E\r\nS31500017E381E1081E2100093E5010050E1FCFFFF3AB4\r\nS31500017E480218A0E3CF1B02E50420A0E3002083E586\r\nS31500017E58102093E5010052E3FCFFFF8AF047BDE8D5\r\nS31500017E681EFF2FE1D0CA2000F8402DE950409FE5BA\r\nS31500017E780070A0E10400A0E10150A0E10260A0E1C8\r\nS31500017E88212100EB0110A0E30400A0E10120A0E1FB\r\nS31500017E980C2100EB0400A0E10710A0E1012046E255\r\nS31500017EA8082100EB0400A0E10510A0E10820A0E3E9\r\nS31500017EB8042100EB0400A0E11F2100EBF840BDE816\r\nS31500017EC81EFF2FE1702A200007402DE90207A0E3D3\r\nS31500017ED883FFFFEBB9FEFFEB4000A0E37DFFFFEB5D\r\nS31500017EE80030E0E30228A0E3CB2B03E5EF2B03E503\r\nS31500017EF8FF2B03E588FFFFEB0030A0E300308DE59B\r\nS31500017F0818009FE50410A0E30C20A0E30530A0E3C8\r\nS31500017F18022100EB0CD08DE204E09DE41EFF2FE167\r\nS31500017F28702A200010402DE90238A0E30040E0E362\r\nS31500017F38CB3B04E50A00A0E3352200EB08309FE5B8\r\nS31500017F48BF3204E51040BDE81EFF2FE1010000A580\r\nS31500017F58E0309FE570402DE90150A0E1001093E55E\r\nS31500017F68D4309FE510C091E5182093E5010070E330\r\nS31500017F7802208CE004C0A0E3182083E500C081E557\r\nS31500017F880360A0E10600001AE10F82E2AC109FE54A\r\nS31500017F98FE2000EB0040A0E1D01D00EB040060E0EC\r\nS31500017FA8000065E0B51D00EB060055E31C4096157B\r\nS31500017FB80040E003C91D00EB84109FE5183096E5E3\r\nS31500017FC80400C1E7050D84E2121D41E20031C1E753\r\nS31500017FD80021A0E16C009FE5052C42E223C4A0E143\r\nS31500017FE800C0C2E723C8A0E1010080E200C0C2E7E1\r\nS31500017FF8233CA0E1010080E2161D81E20030C2E7C0\r\nS315000180080150C4E70040A0E30460A0E1050054E183\r\nS31500018018050000AAB51D00EB106486E10100A0E386\r\nS31500018028961D00EB014084E2F7FFFFEA0600A0E196\r\nS315000180387040BDE81EFF2FE1D8CA2000702A200033\r\nS315000180484A0200009430200015312000F8402DE93D\r\nS315000180580127A0E30030E0E3EB2B03E5200050E322\r\nS315000180680060A0B12060A0A3FF2B03E50200A0E3F6\r\nS31500018078821D00EB0050A0E30540A0E1060055E192\r\nS31500018088050000AA991D00EB104584E10100A0E353\r\nS315000180987A1D00EB015085E2F7FFFFEA9C309FE568\r\nS315000180A8003093E5101093E594209FE5020051E115\r\nS315000180B8FBFFFF9A0000A0E30020A0E101C0A0E3B6\r\nS315000180C8060052E1130000AA9670A0E3920707E0A2\r\nS315000180D80010A0E30A7D87E2105093E5070055E1F9\r\nS315000180E80600002A0050E0E3C35B15E5015705E2E7\r\nS315000180F8000055E1011081120500A0E1F5FFFFEA34\r\nS31500018108151041E2260051E30C402490012082E239\r\nS315000181188CC0A0E1E9FFFFEA28209FE5244082E51B\r\nS31500018128206082E50420A0E3002083E5102093E582\r\nS31500018138010052E3FCFFFF8AF840BDE81EFF2FE16C\r\nS31500018148D0CA2000E9010000702A20000228A0E315\r\nS315000181580030E0E310402DE90100A0E3CF2B03E551\r\nS31500018168AB2100EB0000A0E33A1D00EB0710A0E3EA\r\nS315000181785500A0E302FFFFEB50409FE55500A0E341\r\nS31500018188341D00EB0030A0E30600A0E3243084E5AB\r\nS31500018198203084E5ACFFFFEB0100A0E3371D00EBBF\r\nS315000181A82C309FE5001093E5102091E524309FE5DA\r\nS315000181B8030052E1FBFFFF9A1900A0E30610A0E3B2\r\nS315000181C8EFFEFFEB240094E51040BDE81EFF2FE10A\r\nS315000181D8702A2000D0CA200082010000F8402DE94B\r\nS315000181E80228A0E30030E0E3CB2B03E50070A0E111\r\nS315000181F8EF2B03E50200A0E3FF2B03E50160A0E1F5\r\nS315000182081E1D00EB0040A0E30450A0E1060055E165\r\nS31500018218050000AA351D00EB104584E10100A0E325\r\nS31500018228161D00EB015085E2F7FFFFEA70309FE566\r\nS31500018238074024E00448A0E1002093E52448A0E192\r\nS31500018248103092E5730F53E3FCFFFF3A0030A0E3C9\r\nS31500018258060053E10D0000AA011004E210C092E5E0\r\nS31500018268000051E30208A0E30010E0E3CF0B01157B\r\nS31500018278CB0B010596C08CE2A440A0E1101092E553\r\nS315000182880C0051E1FCFFFF3A013083E2EFFFFFEA00\r\nS315000182980030E0E30228A0E3CB2B03E5F840BDE874\r\nS315000182A81EFF2FE1D0CA2000F7432DE92C639FE575\r\nS315000182B8205096E5070055E30640A0E12D00001A77\r\nS315000182C8247096E5550057E314339FE51B00001A01\r\nS315000182D8003093E5021CA0E30020E0E30440A0E39C\r\nS315000182E8CF1B02E50700A0E1004083E5D91C00EB9E\r\nS315000182F83D00A0E30610A0E3B7FFFFEB0130A0E3C2\r\nS315000183082830C6E50030A0E31C3086E5183086E53E\r\nS31500018318243096E52C3086E5C8329FE5003093E592\r\nS31500018328004083E5102093E5010052E3FCFFFF8A34\r\nS31500018338102093E5460F52E3FCFFFF3AA40000EA3A\r\nS31500018348003093E53210A0E3100093E54C2000EBD2\r\nS31500018358280051E30700009AFF0007E2BD1C00EB65\r\nS315000183683D00A0E30610A0E39BFFFFEB1400A0E38A\r\nS31500018378272100EB960000EA2830D4E5010053E3F3\r\nS3150001838858629FE51E00001A060055E31300001AFD\r\nS315000183980300A0E10510A0E1247096E5EBFEFFEBD2\r\nS315000183A8190020E2000057E10C00001A0230A0E390\r\nS315000183B82830C6E52C329FE5003093E50420A0E37A\r\nS315000183C8002083E5102093E5010052E3FCFFFF8AB4\r\nS315000183D8102093E5C70052E3FCFFFF9A7C0000EAF0\r\nS315000183E80030A0E32830C4E5022CA0E30030E0E326\r\nS315000183F8CB2B03E5F0019FE5241094E5FD2000EB66\r\nS31500018408730000EA0B0055E32900001A020053E342\r\nS315000184183A00001A0510A0E10000E0E3CBFEFFEBED\r\nS31500018428243096E5C4919FE5030020E0C070D9E7A2\r\nS31500018438C080A0E10520A0E10710A0E10800A0E1A5\r\nS3150001844888FEFFEB1C3096E50050A0E1019B89E20E\r\nS315000184580980C3E7300096E5013083E2057487E1B8\r\nS315000184681C3086E5851C00EB0708A0E10C10A0E38B\r\nS315000184782008A0E158FFFFEB68219FE5003092E54F\r\nS315000184880410A0E3001083E50250A0E1102093E553\r\nS31500018498010052E3FCFFFF8A340094E5771C00EBE8\r\nS315000184A8002095E5103092E5B30053E3FCFFFF9AEF\r\nS315000184B8470000EA170055E31000001A0510A0E16D\r\nS315000184C80000E0E3A1FEFFEB243096E5030020E07F\r\nS315000184D80030A0E32830C6E5022CA0E30030E0E333\r\nS315000184E8CB2B03E5801AA0E1A025A0E1211BA0E181\r\nS315000184F8FC009FE5FF2002E2BE2000EB340000EA03\r\nS31500018508000053E30800001A0030A0E30A00A0E3C4\r\nS315000185182830C4E51C3084E5BD2000EB022CA0E31D\r\nS315000185280030E0E3CB2B03E5290000EA1C2094E5A3\r\nS3150001853800208DE50510A0E1B8009FE5242094E50B\r\nS31500018548AC2000EBB0009FE52C1094E5A92000EBC8\r\nS31500018558A8609FE50050A0E31C3094E5030055E1AF\r\nS31500018568050000AA0510A0E194009FE50120F6E5A3\r\nS31500018578A02000EB015085E2F6FFFFEA6C509FE56B\r\nS315000185880070E0E30560A0E11C3094E5030057E1C3\r\nS31500018598045085E2016086E2DAFFFFAAFA34D5E5DE\r\nS315000185A8F914D5E5F824D5E50338A0E1013483E1CA\r\nS315000185B8FBC4D5E5023083E148009FE57E14D6E584\r\nS315000185C87E25D6E50C3C83E18A2000EB017087E223\r\nS315000185D8ECFFFFEA0CD08DE2F043BDE81EFF2FE168\r\nS315000185E8702A2000D8CA2000D0CA200070191200AB\r\nS315000185F8142C200085191200A0191200D319120093\r\nS3150001860813302000DE191200F419120024309FE5F8\r\nS31500018618202093E51E0052E31EFF2FC1241093E587\r\nS315000186280100A0E3101281E1002082E0241083E515\r\nS31500018638202083E51EFF2FE1702A2000F8402DE94E\r\nS315000186480060A0E10400A0E30150A0E10B1C00EBCF\r\nS315000186588C309FE5001093E5102091E584309FE565\r\nS31500018668030052E1FBFFFF9A8600A0E178409FE5EF\r\nS315000186780510A0E1010080E3C1FDFFEB0030A0E396\r\nS315000186880C00A0E3243084E5203084E56EFEFFEB80\r\nS315000186982470D4E50600A0E10710A0E10520A0E1B9\r\nS315000186A8F0FDFFEB241094E5210450E10700A00139\r\nS315000186B80900000AFF1001E20520A0E10600A0E179\r\nS315000186C8E8FDFFEB242094E50010A0E12224A0E1B7\r\nS315000186D818009FE5472000EB0000E0E3F840BDE8FD\r\nS315000186E81EFF2FE1D0CA200082010000702A200057\r\nS315000186F81B1A1200060051E3F0412DE90060A0E1C2\r\nS315000187080150A0E10240A0E14A0000DA38019FE5E4\r\nS31500018718FD1E00EB30019FE50010A0E30120A0E358\r\nS31500018728E81E00EB0510A0E10420A0E118019FE571\r\nS31500018738E41E00EB0610A0E10820A0E308019FE56E\r\nS31500018748E01E00EB00019FE5FB1E00EB013084E211\r\nS315000187581663A0E1855086E1096084E2105685E139\r\nS315000187680200A0E3C51B00EBE0309FE5001093E58E\r\nS315000187780D4084E20380A0E1D4309FE5102091E505\r\nS31500018788030052E10370A0E1FAFFFF9A0410A0E189\r\nS315000187980500A0E17AFDFFEB004098E5103094E56D\r\nS315000187A8070053E1FCFFFF9A0030A0E30310A0E1A4\r\nS315000187B8963083E20020A0E3100094E5030050E11F\r\nS315000187C80600002A0000E0E3C30B10E5010700E2FA\r\nS315000187D8010050E1012082120010A0E1F5FFFFEA35\r\nS315000187E8152042E2260052E30900008A100094E5AA\r\nS315000187F89610A0E32A1F00EB0430A0E3003084E5BD\r\nS31500018808103094E5010053E3FCFFFF8A9B1B00EB44\r\nS31500018818080000EA3C209FE5020053E1E3FFFF1A46\r\nS315000188280430A0E3003084E5103094E5010053E3F9\r\nS31500018838FCFFFF8A010000EA0000A0E3000000EA4D\r\nS315000188480000E0E3F041BDE81EFF2FE1702A200099\r\nS31500018858D0CA200082010000E02E0000F8402DE970\r\nS315000188680060A0E10140A0E196FDFFEB0010A0E346\r\nS31500018878012BA0E33C019FE5EE1F00EB38019FE5C4\r\nS31500018888841F00EB30FEFFEB0050A0E1A4FDFFEBD7\r\nS315000188981D0055E30600000A3D0055E30900001ACC\r\nS315000188A818019FE57B1F00EB0B70A0E3013BA0E3DA\r\nS315000188B8090000EA08019FE5761F00EB0970A0E3AD\r\nS315000188C8013CA0E3040000EAF8009FE50510A0E1D9\r\nS315000188D8C81F00EB0000E0E3340000EA010074E37E\r\nS315000188E80340A001062084E0030052E1034066A08C\r\nS315000188F815FEFFEB012CA0E30030E0E3CF2B03E5E7\r\nS315000189080050A0E3040055E11B0000AA060085E01B\r\nS315000189180710A0E148FFFFEB010070E30300000A1E\r\nS315000189280030E0E3C32B13E5020512E30800001A41\r\nS3150001893894009FE5571F00EB79FDFFEB0000E0E38C\r\nS31500018948013CA0E3CB3B00E5023CA0E3CB3B00E5C1\r\nS31500018958160000EA5C209FE50200C5E76C209FE54A\r\nS31500018968015085E2BF2203E5100015E3022CA0E3BE\r\nS31500018978CF2B0315CB2B0305E1FFFFEA0030E0E31C\r\nS31500018988012CA0E3CB2B03E5022CA0E3CB2B03E5BB\r\nS3150001899863FDFFEB38009FE5961F00EB071084E2A5\r\nS315000189A830009FE50710C1E3921F00EB0000A0E32A\r\nS315000189B8F840BDE81EFF2FE1142C2000481A1200CA\r\nS315000189C8831A12005E1A1200A91A1200C11A12009D\r\nS315000189D8010000A5D31A1200F71A1200F8402DE972\r\nS315000189E80150A0E10060A0E136FDFFEB40019FE5E3\r\nS315000189F8281F00EBD4FDFFEB0040A0E148FDFFEB8B\r\nS31500018A081D0054E30200000A3D0054E30900000A70\r\nS31500018A18140000EA062085E0010C52E314019FC503\r\nS31500018A28080000CA10019FE50510A0E1711F00EBBF\r\nS31500018A380870A0E30E0000EA062085E0010B52E368\r\nS31500018A48030000DAF4009FE50210A0E1691F00EBBC\r\nS31500018A58350000EAE8009FE50510A0E1651F00EB77\r\nS31500018A680A70A0E3020000EAD8009FE5611F00EB47\r\nS31500018A782D0000EA012CA0E30030E0E3CF2B03E54B\r\nS31500018A88B1FDFFEB0200A0E3FC1A00EB0040A0E3F6\r\nS31500018A98060054E11D0000AAAC309FE5033085E0CD\r\nS31500018AA80400D3E7051084E00720A0E110FFFFEBDF\r\nS31500018AB8000050E30900000A90009FE50410A0E1B8\r\nS31500018AC84C1F00EB16FDFFEB0030E0E3012CA0E3A1\r\nS31500018AD8CB2B03E5022CA0E3CB2B03E5120000EA1E\r\nS31500018AE80030E0E3C32B13E5020512E3F1FFFF0AA9\r\nS31500018AF85C209FE5014084E2BF2203E5100014E3F0\r\nS31500018B08022CA0E3CF2B0315CB2B0305DFFFFFEACE\r\nS31500018B180030E0E3012CA0E3CB2B03E5022CA0E314\r\nS31500018B28CB2B03E52C009FE5DA1E00EBF840BDE8E8\r\nS31500018B381EFF2FE1481A12001C1B1200481B1200C7\r\nS31500018B487C1B1200A91B1200DE1B1200142C20002C\r\nS31500018B58011C1200010000A51E1C1200F7432DE995\r\nS31500018B68000050E30150A0E10260A0E10040A0B37B\r\nS31500018B780C0000AA060054E17F0000CA5500A0E3D4\r\nS31500018B88B41A00EB0400A0E10510A0E1EFFCFFEB2D\r\nS31500018B980410A0E10020A0E1E8019FE5151F00EB04\r\nS31500018BA8014084E2F2FFFFEADC419FE5380084E5F3\r\nS31500018BB80207A0E3341084E5302084E548FCFFEB86\r\nS31500018BC87EFBFFEB8200A0E342FCFFEB0060E0E3E3\r\nS31500018BD80137A0E30050A0E3EB3B06E5FF3B06E5C2\r\nS31500018BE84DFCFFEB0C20A0E30400A0E10410A0E378\r\nS31500018BF80530A0E300508DE5C81D00EB013CA0E35C\r\nS31500018C082850C4E584019FE5CF3B06E5A11E00EB8C\r\nS31500018C180530A0E10520A0E10050E0E3C31B15E5FE\r\nS31500018C28020511E34C00000AC36B15E560919FE547\r\nS31500018C382669A0E1016006E2001099E5020056E105\r\nS31500018C48107091E52500000A010056E32300001A79\r\nS31500018C580520A0E3002081E5832047E2260052E3B0\r\nS31500018C680300008A68FEFFEBCF6B05E50630A0E13D\r\nS31500018C781A0000EA472047E2260052E30800008A64\r\nS31500018C88203094E51E0053E3FC209FD5013083D2A2\r\nS31500018C98203082D50130A0E30020E0E3CF3B02E596\r\nS31500018CA80E0000EA000053E30C00000A203094E5A8\r\nS31500018CB8040053E3D0509FE50080A0E379FDFFCB84\r\nS31500018CC8D0209FE50030E0E3248085E5208085E516\r\nS31500018CD8BF2203E50120A0E3CB2B03E50030A0E387\r\nS31500018CE8A90057E30020A0D3012003C2000052E3E4\r\nS31500018CF80C00000A203094E5040053E388509FE5F0\r\nS31500018D080080A0E367FDFFCB88209FE50030E0E304\r\nS31500018D18248085E5208085E5BF2203E50120A0E3BF\r\nS31500018D28CB2B03E50030A0E36C209FE5020057E159\r\nS31500018D38040000DA002099E5201092E5010811E304\r\nS31500018D480210A0130010821548109FE50020E0E3E9\r\nS31500018D58BF1202E50620A0E1AEFFFFEA3C009FE54F\r\nS31500018D684C1E00EB013CA0E3CB3B05E50130A0E33B\r\nS31500018D78CB3B05E5023CA0E3CB3B05E50CD08DE2F8\r\nS31500018D88F043BDE81EFF2FE12F1C1200702A2000B8\r\nS31500018D98411C1200D0CA2000010000A5B70B000033\r\nS31500018DA83C11120004402DE500C8A0E12CC8A0E141\r\nS31500018DB8022081E00140D1E404402CE0FF4004E2B6\r\nS31500018DC8044224E0FF4004E22CC4A0E124C22CE0C2\r\nS31500018DD804C48CE1020051E184C12CE0F4FFFF1ABE\r\nS31500018DE824209FE5020050E10CC0E0010CC8A00157\r\nS31500018DF82CC8A00100C0C3E504309DE52CC4A0E140\r\nS31500018E0800C0C3E504409DE41EFF2FE1FFFF0000FB\r\nS31500018E1830402DE9020052E314D04DE20150A0E1A1\r\nS31500018E280240A0E10F0000DA0F308DE200308DE537\r\nS31500018E38022042E20E308DE2044085E0D8FFFFEBC6\r\nS31500018E480E20DDE5023054E5030052E10500001A63\r\nS31500018E580F00DDE5013054E5033050E0000073E210\r\nS31500018E680300B0E0000000EA0000A0E314D08DE2A0\r\nS31500018E783040BDE81EFF2FE1001021E0FF2001E28E\r\nS31500018E880030A0E30810A0E302C023E001001CE3C0\r\nS31500018E98A330A0E1011041E2213B23120118A0E110\r\nS31500018EA8083023122118B0E1A220A0E1F5FFFF1A2C\r\nS31500018EB8200423E01EFF2FE108402DE9E000A0E38E\r\nS31500018EC884FBFFEB3D1E00EB0840BDE81EFF2FE1CA\r\nS31500018ED837402DE90050A0E10140A0E1F5FFFFEB85\r\nS31500018EE80030A0E300308DE504308DE50510A0E1E2\r\nS31500018EF80420A0E1FF00A0E3F71D00EB0CD08DE2F2\r\nS31500018F083040BDE81EFF2FE1F84F2DE90050A0E1E2\r\nS31500018F180180A0E10260A0E10040A0E3023048E23E\r\nS31500018F28030054E14300008A0430D5E7302043E2C8\r\nS31500018F38FF2002E2010052E30700008A023084E2C0\r\nS31500018F48044085E0D120D4E1000052E30320D5B7DF\r\nS31500018F587F2002B2023083B0340000EA060053E3F0\r\nS31500018F682C00001A019084E20970D5E70A0057E33C\r\nS31500018F7802B084E22500001A0BA085E0C8109FE51F\r\nS31500018F880A00A0E10820A0E3FF1D00EB001050E253\r\nS31500018F981E00001A000056E31C00000A0C20A0E37C\r\nS31500018FA80600A0E1231E00EB0720A0E10600A0E1D0\r\nS31500018FB80A10A0E1AB1D00EB0920D5E7042082E0E9\r\nS31500018FC8020082E20030D5E7020053E31C00001AD2\r\nS31500018FD802C085E00330DCE5010053E31800001AFE\r\nS31500018FE80430DCE50A30C6E5053082E20310D5E730\r\nS31500018FF8020051E30D00001A0610DCE5010051E3F9\r\nS315000190080730DC050B30C60508308202070000EA86\r\nS3150001901807308BE0050000EA043085E00130D3E52E\r\nS31500019028000053E30500000A024084E2033084E0AD\r\nS315000190380340A0E1B8FFFFEA0000A0E3000000EA50\r\nS315000190480400A0E1F84FBDE81EFF2FE1230C120032\r\nS3150001905830402DE943DF4DE20050A0E10140A0E197\r\nS3150001906894009FE50710A0E30D20A0E1160600EB8A\r\nS31500019078060050E30100000A0000E0E31B0000EAD5\r\nS315000190880230DDE5900053E3FAFFFF1A0330DDE510\r\nS31500019098000053E3F7FFFF1A60009FE50510A0E300\r\nS315000190A80D20A0E1080600EB060050E3F1FFFFDA08\r\nS315000190B8423F8DE2002083E00C1152E5900051E316\r\nS315000190C8ECFFFF1A0B2152E5000052E3E9FFFF1AF4\r\nS315000190D8063040E2040053E10340A0310500A0E157\r\nS315000190E802108DE20420A0E15E1D00EB0400A0E160\r\nS315000190F843DF8DE23040BDE81EFF2FE12B0C120045\r\nS31500019108320C120030402DE945DF4DE20040A0E166\r\nS315000191180720A0E30150A0E10D00A0E184109FE51E\r\nS31500019128501D00EB0810A0E3044084E20D00A0E105\r\nS3150001913801208DE00740CDE5E30500EB050050E38E\r\nS31500019148130000DA113E8DE2002083E00C1152E58E\r\nS31500019158900051E30E00001A0B4152E5000054E35A\r\nS315000191680B00001A090050E30A0000DA0D40DDE59C\r\nS31500019178092040E2040052E10A4040D2FF4004D2ED\r\nS315000191880500A0E10E108DE20420A0E1351D00EBDB\r\nS31500019198000000EA0040E0E30400A0E145DF8DE2BB\r\nS315000191A83040BDE81EFF2FE1370C120070402DE953\r\nS315000191B830D04DE204408DE2070084E8A4109FE513\r\nS315000191C80420A0E318008DE20360A0E10F50DDE55D\r\nS315000191D8241D00EB0410A0E17F30E0E30A20A0E3A0\r\nS315000191E81F008DE21D30CDE51E20CDE51D1D00EBCE\r\nS315000191F8000055E37C30E0E32930CDE50120A0E30A\r\nS315000192087B30E0131710A0131410A0032C30CD15D2\r\nS315000192182D20CD152A20CDE5053041E218008DE235\r\nS3150001922810208DE22E50CD152B60CDE51C30CDE5F5\r\nS31500019238A50500EB060050E30600001A1230DDE52D\r\nS31500019248900053E30300001A1300DDE5000090E2E5\r\nS315000192580100A013000000EA0100A0E330D08DE26E\r\nS315000192687040BDE81EFF2FE13E0C120004E02DE51B\r\nS3150001927849DF4DE27E0500EB08008DE210108DE214\r\nS315000192880020A0E3E10400EB010050E30100A01374\r\nS315000192980D00001A3C009FE50510A0E3890400EBC8\r\nS315000192A804008DE2900400EB030050E30400001A69\r\nS315000192B80400DDE5D00050E30300A0130000A0037D\r\nS315000192C8010000EA000050E30200A00349DF8DE235\r\nS315000192D804E09DE41EFF2FE1420C120070402DE9C7\r\nS315000192E886DF4DE20060A0E1DFFFFFEB004050E2C0\r\nS315000192F80100A0130410A0112700001AC8009FE559\r\nS315000193082D0100EB0410A0E1012CA0E318008DE269\r\nS31500019318481D00EB011CA0E318008DE24BFFFFEB93\r\nS31500019328110050E30010A0E10200A0D31A0000DAF0\r\nS315000193380C408DE218008DE20420A0E1F1FEFFEB5E\r\nS31500019348005050E20200001A1630DDE5000053E332\r\nS315000193580200001A0300A0E30510A0E10E0000EACE\r\nS31500019368070094E80230A0E3464F8DE28EFFFFEB3B\r\nS315000193780510A0E1012CA0E30400A0E12D1D00EBDE\r\nS315000193880800D6E50410A0E15DFFFFEB006050E29E\r\nS31500019398030000AA0400A0E30610A0E1CBFEFFEB40\r\nS315000193A8060000EAC3FEFFEB50008DE8FF00A0E3CC\r\nS315000193B80510A0E10620A0E10530A0E1C61C00EBDE\r\nS315000193C886DF8DE27040BDE81EFF2FE1FFFF020038\r\nS315000193D8F7402DE90050A0E1A200A0E30270A0E148\r\nS315000193E80160A0E10040A0E33AFAFFEB2B3AE0E383\r\nS315000193F8DB4F03E571F9FFEB84309FE5183093E500\r\nS31500019408013003E2033097E10030A0130130A003D5\r\nS315000194180420A0E12BCAE0E3BF1F1CE5100011E3FD\r\nS31500019428DF1F1C15FF1001120710CD150710DD15DA\r\nS315000194382B1AE0E3BF1F11E5010011E30800000A3A\r\nS31500019448060053E103C0D5D7012082C2FFC0A0C3DD\r\nS31500019458013083D22B1AE0E3040052E3DBCF01E5A6\r\nS31500019468030000CA0010E0E3C31B11E5020511E37E\r\nS31500019478E7FFFF1A0000A0E30CD08DE2F040BDE83B\r\nS315000194881EFF2FE1AC2A2000F84F2DE901A0A0E12B\r\nS3150001949802B0A0E10090A0E19C1C00EB0000A0E353\r\nS315000194A8771C00EB0000A0E3751C00EB0000A0E3AD\r\nS315000194B8731C00EB0000A0E3711C00EB0100A0E3A4\r\nS315000194C86F1C00EB0000A0E36D1C00EBA8609FE594\r\nS315000194D80000A0E36A1C00EB0000A0E3681C00EB97\r\nS315000194E8002096E594309FE5012082E20F10E0E323\r\nS315000194F8002086E50210C3E700C0A0E30A005CE18C\r\nS31500019508150000AA004096E50C80D9E7015084E2CF\r\nS315000195180870A0E3010018E30F20E0130F20A00351\r\nS31500019528017057E20520C3E7A880A0E1015085E252\r\nS31500019538F7FFFF1A3B2CA0E13C509FE5010012E31F\r\nS31500019548094084E20F20E0130F20A003004085E5BF\r\nS315000195580420C3E701C08CE2E7FFFFEA002096E595\r\nS315000195680010A0E3023083E00110C3E5022082E285\r\nS31500019578002086E5F84FBDE81EFF2FE1CCCA200082\r\nS31500019588CCC8200073402DE90240A0E10060A0E1AB\r\nS31500019598A400A0E30150A0E1CEF9FFEB000054E3DB\r\nS315000195A80300000A003094E5090053E30A30A0D30A\r\nS315000195B8003084D50030A0E3002094E5020053E191\r\nS315000195C80F0000AA2B2AE0E3BF1F12E5010011E3F1\r\nS315000195D80010A013DB1F0215BF2F12E501308312FD\r\nS315000195E8100012E32B2AE013DF2F121500208D1528\r\nS315000195F880109FE500209D150020E0E3BF1202E5DB\r\nS31500019608ECFFFFEA0030A0E32B2AE0E3BF1F12E5D7\r\nS31500019618010011E30500000A5C109FE50110D3E77C\r\nS31500019628013083E2060053E1DB1F02E5090000AAC7\r\nS315000196382B2AE0E3BF1F12E5100011E3DF2F1215F5\r\nS3150001964804208D152C109FE504209D150020E0E3CC\r\nS31500019658BF1202E5EBFFFFEA000055E3002094156F\r\nS31500019668023083108331A0110030851508D08DE2B0\r\nS315000196787040BDE81EFF2FE1010000A5CCC82000FF\r\nS31500019688F8432DE90420A0E30030E0E30040A0E11F\r\nS31500019698CF2B03E5A300A0E30150A0E18DF9FFEB71\r\nS315000196A8B0309FE55C4083E50040A0E3544083E584\r\nS315000196B83040C3E50390A0E19C209FE50030E0E33C\r\nS315000196C8BF2203E52B2AE0E3BF3F12E5010013E3BE\r\nS315000196D80030A013DB3F0215BF3F12E5100013E36C\r\nS315000196E8F4FFFF0A643099E5030054E11600002AE5\r\nS315000196F82B3AE0E3DF8F13E5FF0008E22002A0E141\r\nS3150001970858709FE50FE0A0E117FF2FE1000050E335\r\nS31500019718016084E28441A011044084120040851549\r\nS315000197280700001A0F0008E20FE0A0E117FF2FE17A\r\nS31500019738000050E30640A001DEFFFF0A8661A0E1B2\r\nS31500019748006085E50100A0E3000000EA0000A0E34F\r\nS31500019758F843BDE81EFF2FE1AC2A2000010000A551\r\nS31500019768B804200004309FE56000C3E51EFF2FE121\r\nS31500019778AC2A200008402DE920309FE520209FE5EE\r\nS31500019788000093E54410A0E32A1C00EB14309FE582\r\nS315000197980020A0E3682083E50840BDE81EFF2FE10D\r\nS315000197A860002000B80B0000AC2A200004309FE5B9\r\nS315000197B8040083E51EFF2FE16000200004309FE5C9\r\nS315000197C8640083E51EFF2FE1AC2A200004309FE5E3\r\nS315000197D80000D3E71EFF2FE1470C120004402DE5D8\r\nS315000197E80020A0E30230A0E1010053E1050000AA30\r\nS315000197F803C0D0E718409FE50CC0D4E71C2382E1DB\r\nS31500019808013083E2F7FFFFEA0200A0E104409DE48C\r\nS315000198181EFF2FE1470C120038402DE90050A0E148\r\nS315000198280140A0E1ECFFFFEB0410A0E10020A0E15C\r\nS315000198380500A0E13840BDE812FFFFEA07402DE91F\r\nS315000198480120A0E1011081E20030A0E1011080E0D1\r\nS3150001985800108DE514009FE50310A0E1023083E0B6\r\nS315000198684FFDFFEB0CD08DE204E09DE41EFF2FE1D6\r\nS3150001987863630000F74F2DE944519FE50180A0E19C\r\nS315000198880090A0E104208DE5A01B00EB003095E5D2\r\nS3150001989830619FE5013083E23F20E0E30800A0E163\r\nS315000198A80320C6E7003085E5AC1B00EB00C0A0E34A\r\nS315000198B80C40A0E10520A0E10630A0E1000054E13A\r\nS315000198C82C00000A84A1A0E1001092E508A06AE034\r\nS315000198D80470D9E708005AE308A0A0A3016081E251\r\nS315000198E80050A0E30A0055E10D00000A01B017E295\r\nS315000198F80CC0A01306C0C31701C0A0130400001AA8\r\nS3150001990800005CE33FB0E00306B0C30706B0C31727\r\nS315000199180BC0A011A770A0E1015085E2016086E2A3\r\nS31500019928EFFFFFEA057081E0080055E390609FE5C7\r\nS31500019938007082E50D00001A04709DE53754A0E118\r\nS31500019948091081E2015015E2001086E50CC0A0134A\r\nS3150001995801C0C31701C0A0130400001A00005CE38C\r\nS315000199683F50E0030150C3070150C31705C0A011BA\r\nS31500019978014084E2D0FFFFEA001092E5011081E27E\r\nS31500019988001082E500005CE33F00E0030000A0133D\r\nS315000199980100C3E7000092E50010A0E3003083E070\r\nS315000199A8050080E20110C3E50210C3E50310C3E513\r\nS315000199B80410C3E5000082E50CD08DE2F04FBDE846\r\nS315000199C81EFF2FE1CCCA2000CCC820008111A0E1DE\r\nS315000199D8A7FFFFEA7F402DE90150A0E10F00CDE581\r\nS315000199E80040A0E1491B00EB0000A0E3241B00EBAB\r\nS315000199F80000A0E3221B00EB0000A0E3201B00EB04\r\nS31500019A080000A0E31E1B00EB0100A0E31C1B00EBFA\r\nS31500019A180000A0E31A1B00EB0000A0E3181B00EBF3\r\nS31500019A280000A0E3161B00EBD0209FE5000092E59D\r\nS31500019A38CCC09FE5010080E20F30E0E30030CCE7BF\r\nS31500019A4801E080E20430A0E3010014E30F10E01303\r\nS31500019A580F10A003013053E20E10CCE7A440A0E199\r\nS31500019A6801E08EE2F7FFFF1A050080E20030CCE73D\r\nS31500019A780130A0E300108CE00040A0E30340C1E7F9\r\nS31500019A88013083E2060053E3F9FFFF1A061080E26C\r\nS31500019A98001082E568009FE50520A0E14BFEFFEB7B\r\nS31500019AA860309FE5043093E5040053E10050A0E1DE\r\nS31500019AB80E00000A50309FE50FE0A0E113FF2FE1E9\r\nS31500019AC80110A0E30060A0E10F008DE242FFFFEB69\r\nS31500019AD800408DE50030A0E10110A0E30F008DE202\r\nS31500019AE80620A0E124C09FE50FE0A0E11CFF2FE1BD\r\nS31500019AF80500A0E110D08DE27040BDE81EFF2FE100\r\nS31500019B08CCCA2000CCC8200060002000B900200083\r\nS31500019B18140820000010A0E3ADFFFFEAF7402DE985\r\nS31500019B280270A0E10320A0E10060A0E10150A0E1DC\r\nS31500019B380340A0E153FEFFEB60309FE50720A0E15B\r\nS31500019B48001093E558009FE520FEFFEB54309FE592\r\nS31500019B58043093E5000053E30070A0E10B00000A0E\r\nS31500019B6844309FE50FE0A0E113FF2FE10030A0E3A9\r\nS31500019B780020A0E100308DE50600A0E10510A0E176\r\nS31500019B880430A0E124C09FE50FE0A0E11CFF2FE10E\r\nS31500019B980700A0E10CD08DE2F040BDE81EFF2FE1E1\r\nS31500019BA8CCCA2000CCC8200060002000B9002000E3\r\nS31500019BB81408200070402DE90050A0E10140A0E101\r\nS31500019BC80260A0E104FFFFEB0410A0E10030A0E170\r\nS31500019BD80620A0E10500A0E17040BDE8CEFFFFEA3E\r\nS31500019BE8F04F2DE95CD04DE22C308DE578379FE5B5\r\nS31500019BF80040A0E10250A0E10120A0E3042083E592\r\nS31500019C080160A0E1DAFEFFEB013044E2030053E311\r\nS31500019C1803F19F971A0000EA309C1100489C110035\r\nS31500019C285C9C1100749C11000430A0E33030CDE532\r\nS31500019C380030A0E33130CDE50840A0E3140000EA86\r\nS31500019C480430A0E30040A0E33030CDE53140CDE556\r\nS31500019C580F0000EA0430A0E33030CDE50330A0E37D\r\nS31500019C683130CDE52040A0E3090000EA0430A0E345\r\nS31500019C783030CDE50030A0E33130CDE52840A0E312\r\nS31500019C88030000EAE4069FE50410A0E1D91A00EBF7\r\nS31500019C98B20100EA000055E30600A0E1C61FA0E1F3\r\nS31500019CA81600000A7730E0E34030CDE50320A0E353\r\nS31500019CB841308DE2C81A00EB0420A0E348308DE25A\r\nS31500019CC80500A0E1C51FA0E1C31A00EB4920DDE5A7\r\nS31500019CD84830DDE5033022E04A20DDE5023023E0A5\r\nS31500019CE84B20DDE5023023E04C30CDE53030DDE5B3\r\nS31500019CF8403083E33030CDE5044084E3060000EAD2\r\nS31500019D0840308DE20420A0E3B31A00EB3030DDE5E4\r\nS31500019D184030C3E33030CDE5FB4004E24120DDE5C8\r\nS31500019D284030DDE5033022E04220DDE558808DE252\r\nS31500019D38023023E04320DDE5244068E5023023E0D4\r\nS31500019D484430CDE50120A0E3023088E258708DE267\r\nS31500019D5800308DE518069FE5023088E00810A0E17D\r\nS31500019D680440C4E30EFCFFEB204067E50120A0E3B5\r\nS31500019D78023087E200308DE5F4059FE5023087E081\r\nS31500019D880710A0E10040A0E305FCFFEBE4159FE501\r\nS31500019D980520A0E350008DE23C408DE5311A00EB29\r\nS31500019DA850208DE20210A0E154308DE20320A0E399\r\nS31500019DB800308DE5B8059FE5023081E0F8FBFFEB41\r\nS31500019DC8B4659FE54020A0E34410A0E3AC059FE5F8\r\nS31500019DD8981A00EB30008DE20210A0E38DFEFFEB2E\r\nS31500019DE89C559FE500C096E50510A0E10C20A0E171\r\nS31500019DF890059FE510C08DE51A1A00EB40008DE22B\r\nS31500019E080510A0E383FEFFEB00C096E50510A0E16F\r\nS31500019E180C20A0E170059FE514C08DE5111A00EB31\r\nS31500019E280800A0E10310A0E37AFEFFEB00C096E567\r\nS31500019E380510A0E10C20A0E150059FE518C08DE5AD\r\nS31500019E48081A00EB48008DE20510A0E371FEFFEB4E\r\nS31500019E5800C096E50510A0E10C20A0E130059FE5BC\r\nS31500019E681CC08DE5FF1900EB0700A0E10310A0E374\r\nS31500019E7868FEFFEB00C096E50510A0E10C20A0E105\r\nS31500019E8810059FE520C08DE5F61900EB1F1A00EBBA\r\nS31500019E980400A0E1FA1900EB0400A0E1F81900EBAF\r\nS31500019EA80400A0E1F61900EB0400A0E1F41900EBA7\r\nS31500019EB80100A0E3F21900EB0400A0E1F01900EBA0\r\nS31500019EC80400A0E1EE1900EB0400A0E1EC1900EB97\r\nS31500019ED8002096E50F10E0E3023085E00F00A0E3CD\r\nS31500019EE8052082E20110C3E50200C3E50300C3E5CC\r\nS31500019EF80410C3E50240C5E70130A0E3021085E07E\r\nS31500019F080040A0E30340C1E7013083E2060053E3C2\r\nS31500019F18F9FFFF1A062082E264149FE578049FE59B\r\nS31500019F28002086E5CF1900EB3C008DE20410A0E382\r\nS31500019F3838FEFFEB00C096E544149FE50C20A0E12E\r\nS31500019F4858049FE524C08DE5C61900EB50008DE243\r\nS31500019F580510A0E32FFEFFEB006096E520149FE5B0\r\nS31500019F680620A0E138049FE528608DE5BD1900EBC0\r\nS31500019F780207A0E35AF7FFEB90F6FFEB0120A0E3F7\r\nS31500019F880030E0E3CF2B03E50450A0E10490A0E103\r\nS31500019F9804B0A0E104A0A0E10470A0E10460A0E17E\r\nS31500019FA80420A0E30030E0E3CB2B03E5A100A0E306\r\nS31500019FB848F7FFEBEC339FE5C0239FE52C2083E5AB\r\nS31500019FC84020A0E30C2083E50020A0E30020C3E5A0\r\nS31500019FD8D4239FE50030E0E3BF2203E5C33B13E545\r\nS31500019FE8020513E3D300000A2B3AE0E3BF2F13E57A\r\nS31500019FF8010012E30020A013DB2F0315BF3F13E571\r\nS3150001A008100013E3F1FFFF0A2B3AE0E3DF3F13E504\r\nS3150001A018FF0003E20C308DE52002A0E18C839FE569\r\nS3150001A0280FE0A0E118FF2FE1000050E30C309DE599\r\nS3150001A0380400001A0F0003E20FE0A0E118FF2FE168\r\nS3150001A048000050E3E1FFFF0A58339FE5088093E5D6\r\nS3150001A05814339FE5043093E5000053E30900000A31\r\nS3150001A0680130A0E300308DE538339FE50C039FE509\r\nS3150001A0780810A0E10020A0E3183093E530C39FE55E\r\nS3150001A0880FE0A0E11CFF2FE128239FE5D83BD2E58D\r\nS3150001A098260053E34300000A520053E34600000A30\r\nS3150001A0A8D92BD2E5200052E30400001A930053E3AA\r\nS3150001A0B84600000A950053E30600001A490000EA23\r\nS3150001A0C8700052E30300001A930053E34B00000AA1\r\nS3150001A0D8950053E34F00000A300053E30C00001AC1\r\nS3150001A0E82CC09DE51010A0E3C0008CE20020A0E37F\r\nS3150001A0F8AFFEFFEBBC329FE5BC029FE5D81BD3E55B\r\nS3150001A108D92BD3E5BB1900EB0780A0E10010A0E32A\r\nS3150001A118510000EA500053E31C00000A602043E2A4\r\nS3150001A128FF2002E2010052E34000009AE00053E3F7\r\nS3150001A1384400000A070057E30D00001A080058E317\r\nS3150001A1480B00001A34029FE50410A0E3C51900EBC1\r\nS3150001A1580410A0E30040A0E160029FE5C11900EBED\r\nS3150001A1680410A0E10020A0E154029FE5A11900EB2B\r\nS3150001A178060000EA4C029FE50810A0E19D1900EBD4\r\nS3150001A1880800A0E1F4119FE50020A0E3841900EB83\r\nS3150001A1980040A0E30450A0E10480A0E10410A0E17E\r\nS3150001A1A8E0619FE52C0000EA10109DE50240A0E35E\r\nS3150001A1B830508DE20180A0E3F8FFFFEA10109DE51B\r\nS3150001A1C80240A0E330508DE20680A0E3F3FFFFEAE8\r\nS3150001A1D814109DE50540A0E340508DE20280A0E3FE\r\nS3150001A1E8A4619FE51C0000EA1C109DE50540A0E35B\r\nS3150001A1F848508DE21480A0E394619FE5160000EAB9\r\nS3150001A2080340A0E318109DE534508DE20480A0E1D7\r\nS3150001A21878619FE5100000EA20109DE50340A0E360\r\nS3150001A22838508DE21E80A0E368619FE50A0000EAC6\r\nS3150001A23824109DE50440A0E33C508DE20780A0E38D\r\nS3150001A24858619FE5040000EA28109DE550619FE5E5\r\nS3150001A2580540A0E350508DE24680A0E3052057E271\r\nS3150001A268003072E20230B3E0060058E305005703F6\r\nS3150001A27801A08A02060058E30030A0030130031248\r\nS3150001A288000053E301B08B12FA0F59E338019F0519\r\nS3150001A2982900000A000051E3019089E2060000DA6C\r\nS3150001A2A810319FE5D82BD3E5523052E2002073E2F4\r\nS3150001A2B80600A0E10320B2E044FCFFEBA8309FE5CD\r\nS3150001A2C8043093E5000053E31400000A000055E347\r\nS3150001A2D80C00000A0410A0E10500A0E13EFDFFEB19\r\nS3150001A2E80410A0E1561900EB0020A0E30030A0E11C\r\nS3150001A2F800208DE50500A0E10410A0E1B0C09FE5AE\r\nS3150001A3080FE0A0E11CFF2FE198309FE5682093E557\r\nS3150001A318B8309FE5030052E1B4009FC5060000CAA4\r\nS3150001A32858009FE54410A0E34020A0E3411900EB43\r\nS3150001A3380870A0E119FFFFEA98009FE5D51800EB20\r\nS3150001A3480B20A0E10930A0E18C009FE50A10A0E1ED\r\nS3150001A358281900EB0120A0E30030E0E3CB2B03E54D\r\nS3150001A3685CD08DE2F04FBDE81EFF2FE160002000B2\r\nS3150001A378191D120063630000470D1200CCCA2000A4\r\nS3150001A388EC372000CCC820006C4820001249200078\r\nS3150001A398B8492000883020005E4A2000044B20007E\r\nS3150001A3A8AA4B2000504C2000AC2A2000010000A531\r\nS3150001A3B8F400200014082000142C2000341D12007B\r\nS3150001A3C8F0372000541D1200751D1200981D120049\r\nS3150001A3D8B80B00006A141200AF1D1200FD2312000B\r\nS3150001A3E870402DE90050A0E10140A0E1FAFCFFEB25\r\nS3150001A3F80410A0E10030A0E10020A0E30500A0E1DF\r\nS3150001A4087040BDE8C4FDFFEA0230A0E10020A0E3E8\r\nS3150001A418C1FDFFEAF0402DE914D04DE200C0A0E3EA\r\nS3150001A42810408DE204C024E50060A0E10170A0E1BE\r\nS3150001A4380250A0E108C08DE50DFDFFEB6C309FE5EC\r\nS3150001A44808208DE2000093E50410A0E14CFCFFEB27\r\nS3150001A4585C309FE56030D3E5000053E30030E0133C\r\nS3150001A4680120A013CF2B031548309FE5043093E54F\r\nS3150001A478000053E30A00000A0700A0E1B71800EB41\r\nS3150001A4880130A0E30010A0E100308DE50600A0E14F\r\nS3150001A4980020A0E30530A0E11CC09FE50FE0A0E184\r\nS3150001A4A81CFF2FE114D08DE2F040BDE81EFF2FE11D\r\nS3150001A4B8CCCA2000AC2A2000600020001408200025\r\nS3150001A4C88111A0E1D2FFFFEA38402DE90050A0E151\r\nS3150001A4D80140A0E1C0FCFFEB8411A0E10020A0E14E\r\nS3150001A4E80500A0E13840BDE8C9FFFFEA30402DE983\r\nS3150001A4F814D04DE20040A0E310108DE2044021E59E\r\nS3150001A5080050A0E15DFCFFEB040050E10100001AD8\r\nS3150001A5180000A0E3110000EA4C309FE5043093E502\r\nS3150001A528000053E30800000A40309FE500408DE52E\r\nS3150001A5380500A0E1541093E50C209DE5403093E514\r\nS3150001A5482CC09FE50FE0A0E11CFF2FE10C309DE533\r\nS3150001A558000053E3EDFFFF0A10309FE5540093E531\r\nS3150001A56814D08DE23040BDE81EFF2FE160002000C7\r\nS3150001A578AC2A200014082000F0402DE914D04DE241\r\nS3150001A5880050A0E30160A0E110108DE2045021E51E\r\nS3150001A5980070A0E139FCFFEB050050E10100001A4B\r\nS3150001A5A80000A0E3130000EA54309FE5043093E568\r\nS3150001A5B8000053E34C409FE50700000A00508DE573\r\nS3150001A5C80700A0E1541094E50C209DE5403094E580\r\nS3150001A5D834C09FE50FE0A0E11CFF2FE1403094E570\r\nS3150001A5E8003086E50C309DE5000053E3EBFFFF0ADA\r\nS3150001A5F810309FE5540093E514D08DE2F040BDE894\r\nS3150001A6081EFF2FE160002000AC2A2000140820005C\r\nS3150001A618F0472DE920D04DE25230A0E30090A0E1A9\r\nS3150001A6280140A0E102A0A0E128129FE50220A0E3D3\r\nS3150001A63808008DE20430CDE50A1800EB18129FE5F3\r\nS3150001A6480920A0E314008DE2061800EB0C129FE521\r\nS3150001A6580420A0E30C008DE2021800EB04008DE251\r\nS3150001A6680710A0E30020A0E369FFFFEBF0019FE5D7\r\nS3150001A6789DFFFFEB000050E30100001A0000A0E374\r\nS3150001A688710000EA000054E30800000AD0119FE5B2\r\nS3150001A6980220A0E30B0084E2F21700EB0010A0E30E\r\nS3150001A6A80A10C4E50400A0E10A20A0E3611800EB42\r\nS3150001A6B8000059E30900A0110010A0130A20A013F5\r\nS3150001A6C85C18001B9380A0E30070A0E30450A0E38C\r\nS3150001A6D8043015E24100000A08008DE20210A0E3E9\r\nS3150001A6E80880CDE51480CDE576FFFFEB70019FE587\r\nS3150001A6F87DFFFFEB000050E3DFFFFF0A10008DE24C\r\nS3150001A7085C119FE50420A0E3D61700EB00005AE38D\r\nS3150001A7180300000A10008DE20410A0E3511800EBB3\r\nS3150001A72800008AE50520A0E334119FE516008DE2B5\r\nS3150001A738CC1700EB14008DE20710A0E33EFCFFEBFB\r\nS3150001A74814008DE20910A0E35EFFFFEB10019FE5FF\r\nS3150001A75865FFFFEB000050E3C7FFFF0A04319FE5E1\r\nS3150001A76804219FE50350D2E7040015E30800000A17\r\nS3150001A7781030DDE5880053E30500001A10008DE26C\r\nS3150001A788011080E20320A0E3B61700EB0360A0E303\r\nS3150001A798000000EA0460A0E3000059E307008910FD\r\nS3150001A7A810108D120620A011AE17001B000054E3ED\r\nS3150001A7B80600000A0620A0E1070084E010108DE2D9\r\nS3150001A7C8A81700EB0A30D4E5036086E00A60C4E501\r\nS3150001A7D8028088E2037087E2FF8008E2BBFFFFEA96\r\nS3150001A7E8000054E30D50C4150E30C415200015E3BE\r\nS3150001A7F80200A0031400000A0C008DE20210A0E377\r\nS3150001A8080DFCFFEB0C008DE20410A0E32DFFFFEB1E\r\nS3150001A8184C009FE534FFFFEB005050E296FFFF0A1C\r\nS3150001A828000054E30400000A0F0084E230109FE59B\r\nS3150001A838012CA0E38B1700EB0E50C4E52C309FE5E5\r\nS3150001A8480020A0E37020C3E50100A0E320D08DE23B\r\nS3150001A858F047BDE81EFF2FE14C0D12004E0D120008\r\nS3150001A868570D12006C482000581C0000142C2000BB\r\nS3150001A878AC2A200038402DE90040E0E30450A0E36B\r\nS3150001A8884EF4FFEBCB5B04E5E000A0E311F5FFEB2B\r\nS3150001A8983200A0E3DE1700EB0207A0E310F5FFEB99\r\nS3150001A8A8CF5B04E5A400A0E30AF5FFEB3200A0E3C1\r\nS3150001A8B8D71700EB0C309FE5022BA0E3642083E554\r\nS3150001A8C83840BDE81EFF2FE1AC2A2000F0482DE9EB\r\nS3150001A8D80250A0E1A8609FE50B2081E20720C2E3B0\r\nS3150001A8E814B08DE202D04DE07020D6E50A2082E34D\r\nS3150001A8F80030A0E10140A0E10020CDE50020A0E361\r\nS3150001A908047081E20120CDE50310A0E10420A0E155\r\nS3150001A91802008DE2531700EB0D00A0E1021084E25C\r\nS3150001A928C5FBFFEB0D00A0E10710A0E1E5FEFFEB7B\r\nS3150001A9380500A0E1ECFEFFEB000050E30D00000A64\r\nS3150001A948030050E30B00009A0030D5E5C00013E37D\r\nS3150001A9580200000AD02003E2800052E30500001A33\r\nS3150001A9687020D6E5013003E2030052E110309F055D\r\nS3150001A978012022027020C30514D04BE2F048BDE83D\r\nS3150001A9881EFF2FE1AC2A2000F0472DE90830D0E55B\r\nS3150001A9980980D0E5088483E10A30D0E5038888E197\r\nS3150001A9A80B30D0E51160D0E5038C88E11030D0E595\r\nS3150001A9B8066483E11230D0E5036886E11330D0E5F9\r\nS3150001A9C882DF4DE2036C86E10040A0E1207080E25F\r\nS3150001A9D867FBFFEB48219FE5FF5008E20130A0E342\r\nS3150001A9E8108018E2043082E538219F156030C215BF\r\nS3150001A9F8010015E30690A0E10D00000A9CFFFFEB9C\r\nS3150001AA0808A08DE20000A0E30A10A0E10020A0E161\r\nS3150001AA18FEFEFFEB10319FE50020A0E30010A0E148\r\nS3150001AA2804308DE500A08DE5FF00A0E30230A0E12A\r\nS3150001AA38291700EB400015E30800000A1830D4E591\r\nS3150001AA481920D4E5022483E11A30D4E5032882E1EA\r\nS3150001AA581B30D4E5032C82E1C8309FE5642083E5E9\r\nS3150001AA68040015E30C00000A08408DE20610A0E177\r\nS3150001AA780420A0E10700A0E193FFFFEB023CA0E35D\r\nS3150001AA880020A0E30010A0E104308DE500408DE52B\r\nS3150001AA98FF00A0E30230A0E10F1700EB080015E361\r\nS3150001AAA81300000A200015E30300000A0700A0E1CD\r\nS3150001AAB80610A0E160FBFFEB029086E20910A0E117\r\nS3150001AAC80700A0E108408DE27EFEFFEB0400A0E14D\r\nS3150001AAD885FEFFEB023CA0E30020A0E30010A0E105\r\nS3150001AAE804308DE500408DE5FF00A0E30230A0E1CA\r\nS3150001AAF8F91600EB000058E328309F150020A01333\r\nS3150001AB086020C315020015E30200001AE000A0E365\r\nS3150001AB1870F4FFEB291700EB82DF8DE2F047BDE801\r\nS3150001AB281EFF2FE160002000AC2A20000F01000063\r\nS3150001AB3870402DE90240A0E10060A0E10150A0E1CA\r\nS3150001AB4825FBFFEB8511A0E10020A0E10600A0E1AD\r\nS3150001AB5847FBFFEB000054E30030A0130310A011DC\r\nS3150001AB681A00000A0328A0E1220854E10120A08363\r\nS3150001AB781213818102308380FF100182F8FFFF8A58\r\nS3150001AB8850309FE5002093E54CC09FE5012082E205\r\nS3150001AB98002083E50030A0E30230CCE70300A0E102\r\nS3150001ABA8020053E1090000AA086064E21006A0E168\r\nS3150001ABB80350DCE7550480E10300CCE7013083E26A\r\nS3150001ABC80338A0E12338A0E1010005E0F3FFFFEA1D\r\nS3150001ABD87040BDE81EFF2FE1CCCA2000CCC820007A\r\nS3150001ABE8010050E1F0412DE90070A0E10180A0E1EA\r\nS3150001ABF80000A0031700000A0160A0E10750A0E1C8\r\nS3150001AC080140A0E3020914E31100001A0500A0E1BE\r\nS3150001AC180110A0E3791200EB080050E10050A0E111\r\nS3150001AC280400A0010B00000A0600A0E10110A0E340\r\nS3150001AC38721200EB070050E10060A0E10000640217\r\nS3150001AC480400000A014084E20448A0E12448A0E186\r\nS3150001AC58EBFFFFEA04009FE5F041BDE81EFF2FE187\r\nS3150001AC686179FEFFF04F2DE96CD04DE200B0A0E10D\r\nS3150001AC7800159FE518008DE20420A0E3791600EB84\r\nS3150001AC880050A0E3F0449FE5F0349FE505005BE141\r\nS3150001AC9828508DE52C508DE5685084E5045083E5F0\r\nS3150001ACA830508DE534508DE538508DE53C508DE5B5\r\nS3150001ACB81C00000A981600EB7150C4E5ECFEFFEB88\r\nS3150001ACC8A100A0E303F4FFEBB4549FE50FE0A0E174\r\nS3150001ACD815FF2FE12008A0E10008A0E1010850E3D3\r\nS3150001ACE8F8FFFF1A0030E0E3C33B13E5020913E35B\r\nS3150001ACF8FBFFFF1A0030E0E3C33B13E5020913E348\r\nS3150001AD08FBFFFF0A0FE0A0E115FF2FE10060A0E3BA\r\nS3150001AD180138A0E3740084E5783084E57C6084E535\r\nS3150001AD2820608DE5050000EA7130D4E5013083E243\r\nS3150001AD38FF3003E27130C4E52B30CDE58060D4E500\r\nS3150001AD480030E0E30190A0E3012CA0E3CF9B03E5EB\r\nS3150001AD580070A0E3CB2B03E5022CA0E3CB2B03E584\r\nS3150001AD6814708DE510908DE50780A0E107A0A0E19C\r\nS3150001AD780750A0E10C249FE50030E0E3BF2203E57C\r\nS3150001AD88C32B13E5022512E2AE00000A022CA0E34A\r\nS3150001AD98CF2B03E540008DE20010A0E31C208DE2D5\r\nS3150001ADA81AFEFFEB000050E3EE00000AA400A0E340\r\nS3150001ADB8C8F3FFEB782094E502208AE018008DE2BB\r\nS3150001ADC80410A0E3072002E258FFFFEB783094E570\r\nS3150001ADD803C08AE0743094E507C0CCE303C08CE075\r\nS3150001ADE874C084E598939FE50FE0A0E119FF2FE170\r\nS3150001ADF8742094E5020050E17C139FE509A0A0E1C7\r\nS3150001AE08783091850730C383022083807420818539\r\nS3150001AE18F3FFFF8A0FE0A0E11AFF2FE1742094E502\r\nS3150001AE28020050E150939FE5F9FFFF3A0020A0E3A5\r\nS3150001AE3824208DE54C208DE54C239FE524108DE2D9\r\nS3150001AE48000092E54C208DE2CDF9FFEB3C039FE52E\r\nS3150001AE58A5FDFFEB000050E300A0A001C100000A18\r\nS3150001AE6820C09DE524039FE50410A0E30CC08DE5F1\r\nS3150001AE787C1600EB0620A0E120008DE54010A0E33A\r\nS3150001AE8828008DE262FDFFEB0CC09DE500005CE346\r\nS3150001AE980020A00301200B12000052E30F00000A54\r\nS3150001AEA87CA099E500005AE30C00001A0C00A0E109\r\nS3150001AEB820109DE549FFFFEB000050E320209D058A\r\nS3150001AEC87C2089050500000AC4129FE5010050E1AE\r\nS3150001AED8781099150100601078008915A10000EA1B\r\nS3150001AEE820109DE57C0094E5000051E188229FE54C\r\nS3150001AEF82300000A000050E32100000A0C208DE51A\r\nS3150001AF0836FFFFEB8C329FE500A060E203005AE1B1\r\nS3150001AF1800E0A0E10C209DE500A0A0039100000A35\r\nS3150001AF2814109DE501005AE10080A0130400001ADF\r\nS3150001AF38018088E20888A0E12888A0E1020058E398\r\nS3150001AF480600008A50029FE50710A0E10E20A0E145\r\nS3150001AF580830A0E1271600EB14A08DE5810000EA70\r\nS3150001AF68783092E514109DE5033081E0783082E56A\r\nS3150001AF7828029FE50710A0E10E20A0E11D1600EBAF\r\nS3150001AF88780000EA04029FE557FDFFEB000050E355\r\nS3150001AF981C00000A10209DE5000055E30730060253\r\nS3150001AFA88030C405012032E210208DE50030E0E34F\r\nS3150001AFB8012CA0E368108DE2CF2B0315CB2B0305DB\r\nS3150001AFC8053081E0D8219FE5D8119FE50220D1E718\r\nS3150001AFD8070055E3052022E2386043E5302043E5C2\r\nS3150001AFE81A00000A2B30DDE5015085E2075005E21B\r\nS3150001AFF81F3003E2853283E12B30CDE58060D4E54D\r\nS3150001B00808A0A0E30D0000EA000055E300C0A01364\r\nS3150001B01801C00B0200005CE3F86006028030D4052B\r\nS3150001B02808608602016086120050A011036086013D\r\nS3150001B038FF60061205A0A011FF6006020CA0A00180\r\nS3150001B0480080A0E3470000EA0280A0E1000000EAD0\r\nS3150001B0580180A0E320008DE20410A0E3DEF9FFEBF6\r\nS3150001B0680140A0E30030A0E13C719FE530608DE22C\r\nS3150001B0780020A0E300408DE520008DE20410A0E346\r\nS3150001B0880FE0A0E117FF2FE10600A0E10810A0E3F9\r\nS3150001B098D1F9FFEB38508DE20030A0E10020A0E3A2\r\nS3150001B0A800408DE50600A0E10810A0E30FE0A0E14D\r\nS3150001B0B817FF2FE10500A0E10810A0E3C6F9FFEB91\r\nS3150001B0C800408DE50030A0E10810A0E30500A0E1ED\r\nS3150001B0D80020A0E30FE0A0E117FF2FE12B30DDE50B\r\nS3150001B0E81F3003E22B30CDE540309DE54C708DE2F3\r\nS3150001B0F80420A0E34C308DE520009DE5023087E071\r\nS3150001B1080010A0E3B41500EB030096E854308DE275\r\nS3150001B118030083E8030095E85C308DE2030083E8C9\r\nS3150001B12828309DE50020A0E364308DE51C30A0E3BE\r\nS3150001B1380810A0E104308DE500708DE50230A0E12C\r\nS3150001B148FF00A0E3641500EBE000A0E3E1F2FFEBEA\r\nS3150001B1589A1500EB24309FE5044083E56CD08DE217\r\nS3150001B168F04FBDE81EFF2FE1017087E20778A0E1E5\r\nS3150001B1782778A0E1FEFEFFEA5B0D1200AC2A20004B\r\nS3150001B18860002000D5002000010000A5CCCA2000DF\r\nS3150001B1986C4820006179FEFF9F860100BC1D1200E4\r\nS3150001B1A81A1E1200581C0000142C20001408200036\r\nS3150001B1B8F04F2DE90060A0E344D04DE22C608DE507\r\nS3150001B1C830608DE534608DE52A60CDE538608DE522\r\nS3150001B1D83C608DE5350300EB0040A0E1300300EB50\r\nS3150001B1E8BC5B9FE5BC3B9FE51C008DE50170A0E3B8\r\nS3150001B1F8080085E20410A0E3686083E5047085E52C\r\nS3150001B208981500EB0710A0E324008DE500A0A0E146\r\nS3150001B2180720A0E10400A0E1810500EB0030D4E598\r\nS3150001B228063053E00130A013060053E114308DE5D2\r\nS3150001B2380D00001A0420A0E30310A0E10E0085E228\r\nS3150001B2480C20C5E5760500EB0F20D5E50E30D5E5D2\r\nS3150001B258033022E01020D5E5023023E01120D5E5A0\r\nS3150001B268023023E01230C5E51B0000EA4430A0E3B2\r\nS3150001B2780C30C5E50F0085E27730E0E30610A0E162\r\nS3150001B2880320A0E30E30C5E5650500EB0F20D5E5E3\r\nS3150001B2980E30D5E5033022E01020D5E5023023E053\r\nS3150001B2A81120D5E5130085E2023023E00310A0E35F\r\nS3150001B2B80420A0E31230C5E5590500EB1420D5E5B5\r\nS3150001B2C81330D5E5033022E01520D5E5023023E019\r\nS3150001B2D81620D5E5023023E01730C5E5F31400EB57\r\nS3150001B2E80207A0E37EF2FFEBB4F1FFEBA100A0E3B6\r\nS3150001B2F878F2FFEBC800A0E3451500EBA83A9FE5F5\r\nS3150001B308003093E5000053E3A00A9FC514109DC5BC\r\nS3150001B318381500CB0080A0E3943A9FE50FE0A0E141\r\nS3150001B32813FF2FE120808DE518808DE5FF90A0E3BE\r\nS3150001B3380870A0E108B0A0E10850A0E1743A9FE5C1\r\nS3150001B3480060E0E3BF3206E5C33B16E5020513E3F9\r\nS3150001B3582100000A000055E33A00001A0500A0E39F\r\nS3150001B368CF1400EB503A9FE5930000E04035A0E189\r\nS3150001B378FA0E53E3F0FFFFDA013CA0E3CB3B06E507\r\nS3150001B3880150A0E3023CA0E3CB3B06E5CF5B06E513\r\nS3150001B3982C0000EA272AE0E3E30F12E5200010E378\r\nS3150001B3A83F00001A2B2AE0E3BF0F12E5010010E364\r\nS3150001B3B80000A013DB0F0215BF2F12E5100012E3E0\r\nS3150001B3C85200001AEC099FE50020E0E3BF0202E5FE\r\nS3150001B3D8C32B12E5020512E3EDFFFF1AC0499FE5EB\r\nS3150001B3E8E000A0E33BF2FFEBF41400EB4410A0E30A\r\nS3150001B3F80420A0E3080084E20E1500EB0130A0E367\r\nS3150001B4080020A0E300308DE5080084E20230A0E1C7\r\nS3150001B4180410A0E3A4C99FE50FE0A0E11CFF2FE1FA\r\nS3150001B42884399FE5003093E5000053E3590200DAB9\r\nS3150001B43870399FE588099FE5041094E5682093E52E\r\nS3150001B448EC1400EB530200EA0420A0E30030E0E329\r\nS3150001B458CB2B03E5A100A0E31EF2FFEB273AE0E3BD\r\nS3150001B4680120A0E3FF2F03E558299FE5FB2F03E5FC\r\nS3150001B4782020A0E3EF2F03E50220A0E3FF2F03E539\r\nS3150001B48820299FE54030A0E30C3082E50030A0E397\r\nS3150001B4982C4082E50030C2E50310A0E10360A0E17B\r\nS3150001B4A8C7FFFFEABB0F12E5011081E2003083E016\r\nS3150001B4B81F0051E30200A0E3FF0F02E5B8FFFFDA20\r\nS3150001B4C80300A0E1F61300EBEC389FE5930000E0DA\r\nS3150001B4D8FA0950E30030A0A30310A0A10360A0A1BC\r\nS3150001B4E8AFFFFFAAE0389FE50FE0A0E113FF2FE1C8\r\nS3150001B4F8000056E30060A001000066E0320050E358\r\nS3150001B5083200008A0030A0E30310A0E1A4FFFFEA9D\r\nS3150001B5182B2AE0E3DF2F12E5FF2002E22B20CDE5FF\r\nS3150001B528A8289FE52B00DDE50C108DE510208DE59B\r\nS3150001B53808308DE52002A0E10FE0A0E112FF2FE11E\r\nS3150001B5480C108DE2000050E3060091E808309DE5F5\r\nS3150001B5580900001A2B00DDE50C108DE508308DE594\r\nS3150001B5680F0000E20FE0A0E112FF2FE1000050E317\r\nS3150001B5780C109DE508309DE591FFFF0A20289FE5FF\r\nS3150001B588042092E51C389FE5000052E3086093E524\r\nS3150001B5981100000A08308DE514289FE50FE0A0E1A7\r\nS3150001B5A812FF2FE10110A0E300108DE508309DE59B\r\nS3150001B5B80020A0E10610A0E10400A0E1183093E5FF\r\nS3150001B5C8F8C79FE50FE0A0E11CFF2FE1020000EAA2\r\nS3150001B5D87A1400EB0050A0E357FFFFEA040056E394\r\nS3150001B5E81E00000A010056E31C00001A0030D4E5CB\r\nS3150001B5F8260053E30200001A0B0055E30200001A65\r\nS3150001B6084DFFFFEA520053E31400001AB8379FE5CD\r\nS3150001B6180FE0A0E113FF2FE10020D4E5523052E2FA\r\nS3150001B628002073E20320B2E018008DE50210A0E3C2\r\nS3150001B6389C079FE55EF9FFEB0030E0E3012CA0E3F0\r\nS3150001B648CB2B03E5022CA0E3CB2B03E538008DE2D7\r\nS3150001B658630F00EBFF90A0E30250A0E336FFFFEA79\r\nS3150001B668022045E20030E0E3080052E302F19F9729\r\nS3150001B67831FFFFEAA0B6110078B711004CB81100E6\r\nS3150001B68800B9110044B91100A0BA1100DCBA1100C1\r\nS3150001B69824BB110070BB1100020056E30700001A13\r\nS3150001B6A80030D4E5930053E323FFFF1A0130D4E5B4\r\nS3150001B6B8200053E31C079F051FFFFF1A360000EA07\r\nS3150001B6C8090056E31CFFFF1A0030D4E5930053E343\r\nS3150001B6D819FFFF1A0130D4E5700053E316FFFF1A6C\r\nS3150001B6E8020084E2EC169FE50420A0E3261400EB91\r\nS3150001B6F8000050E310FFFF1A14209DE5000052E3F5\r\nS3150001B708D4069F05D4069F150310A0E333FBFFEB70\r\nS3150001B718C0069FE50410A0E3521400EB14309DE522\r\nS3150001B728000053E30080A0E10350A01302FFFF1AB3\r\nS3150001B7380030E0E3012CA0E3CF2B03E568369FE553\r\nS3150001B748003093E5030053E3010000CA0650A0E365\r\nS3150001B758F9FEFFEA70369FE50FE0A0E113FF2FE13E\r\nS3150001B76818209DE5001062E074069FE52F0000EAA7\r\nS3150001B778000056E3F0FEFF0A020056E30900001A2C\r\nS3150001B7880030D4E5950053E3EBFEFF1A0130D4E50A\r\nS3150001B798200053E3E8FEFF1A48069FE50510A0E3DB\r\nS3150001B7A80EFBFFEBE4FEFFEA090056E32100001A4F\r\nS3150001B7B80030D4E5950053E3DFFEFF1A0130D4E5E6\r\nS3150001B7C8700053E3DCFEFF1A020084E214169FE5BB\r\nS3150001B7D80420A0E3EC1300EB000050E3D6FEFF1AA9\r\nS3150001B7E80310A0E3F0059FE5FCFAFFEBF4059FE5DE\r\nS3150001B7F80410A0E31B1400EB0030E0E3012CA0E3E6\r\nS3150001B808CF2B03E5A0359FE5003093E5030053E30D\r\nS3150001B8180080A0E1CCFFFFDAAC359FE50FE0A0E19F\r\nS3150001B82813FF2FE118309DE5001063E0B8059FE589\r\nS3150001B838F01300EBC4FFFFEA040056E36B00000AAD\r\nS3150001B848BDFEFFEA080056E3D900001A040084E2A7\r\nS3150001B8580410A0E3031400EB0010A0E30120A0E10B\r\nS3150001B8680050A0E138008DE2510F00EB4010A0E333\r\nS3150001B878055020E00A00A0E1600F00EB000055E149\r\nS3150001B8880B00000A20359FE5003093E5030053E3DA\r\nS3150001B898C60000DA0A00A0E14010A0E3570F00EB4A\r\nS3150001B8A80510A0E10020A0E140059FE5D11300EBBA\r\nS3150001B8B8BE0000EA6010A0E30A00A0E14F0F00EB0A\r\nS3150001B8C80010A0E30120A0E10050A0E138008DE2BC\r\nS3150001B8D8370F00EB0010A0E3050020E00420A0E3E9\r\nS3150001B8E80C359FE530008DE5BB1300EB00059FE5A0\r\nS3150001B8F80410A0E3B9FAFFEB0030E0E3022CA0E361\r\nS3150001B908CF2B03E5A0349FE5003093E5030053E30D\r\nS3150001B9188DFFFFDAB0349FE50FE0A0E113FF2FE1B9\r\nS3150001B92820209DE50710A0E1003062E0C4049FE5F0\r\nS3150001B9380920A0E1AF1300EB83FFFFEA000056E3FD\r\nS3150001B9487DFEFF0AFF0059E32A00001A040056E3A8\r\nS3150001B9589D00001A0030D4E5603043E2FF3003E26F\r\nS3150001B968010053E3A000008A5C349FE50FE0A0E1E3\r\nS3150001B97813FF2FE10090D4E50170D4E5609049E208\r\nS3150001B9882771A0E1FF9009E220008DE50910A0E1E9\r\nS3150001B9980700A0E1170400EB0130A0E10020A0E1B7\r\nS3150001B9A838008DE2710E00EB0A1028E00020A0E3B2\r\nS3150001B9B838008DE2FE0E00EB24209DE50A0020E00A\r\nS3150001B9C80030A0E30310A0E130008DE520349FE5A7\r\nS3150001B9D80200A0E10420A0E37F1300EB10049FE519\r\nS3150001B9E80410A0E37DFAFFEB0450A0E352FEFFEA40\r\nS3150001B9F8FF0059E3D6FFFF0A38008DE20410A0E1E3\r\nS3150001BA080620A0E12F0100EB040056E36E00001AA0\r\nS3150001BA180030D4E5603043E2FF3003E2010053E32E\r\nS3150001BA287100008AA0339FE50FE0A0E113FF2FE123\r\nS3150001BA380090D4E50170D4E5609049E22771A0E150\r\nS3150001BA48FF9009E220008DE50910A0E10700A0E1B9\r\nS3150001BA58E80300EB0130A0E10020A0E138008DE207\r\nS3150001BA68420E00EB0A1028E00020A0E338008DE220\r\nS3150001BA78CF0E00EB0010A0E30A0020E00620A0E1AB\r\nS3150001BA886C339FE530008DE5531300EB60039FE5AA\r\nS3150001BA980610A0E1D2FFFFEA120056E34400001A9D\r\nS3150001BAA838008DE20410A0E10620A0E1050100EBB3\r\nS3150001BAB80400A0E10B10A0E10120A0E3460300EB7E\r\nS3150001BAC838008DE20A10A0E3490100EB10F8FFEBFC\r\nS3150001BAD81DFFFFEA38008DE20410A0E10620A0E16F\r\nS3150001BAE8F80000EB0410A0E10420A0E330008DE289\r\nS3150001BAF8DC1200EB34008DE22A108DE20B20A0E166\r\nS3150001BB08860300EB000050E32400001A30208DE282\r\nS3150001BB180C0092E8033082E0100000EA38008DE25A\r\nS3150001BB280410A0E10620A0E1E60000EB0410A0E164\r\nS3150001BB380420A0E330008DE2CA1200EB0B20A0E13D\r\nS3150001BB4834008DE22A108DE2740300EB000050E305\r\nS3150001BB5830309D0534209D05023063000F00001A20\r\nS3150001BB6834308DE5F8FEFFEA38008DE20410A0E1D5\r\nS3150001BB780620A0E1D30000EB0410A0E10420A0E315\r\nS3150001BB8830008DE2B71200EB34008DE22A108DE207\r\nS3150001BB980B20A0E1610300EB000050E3EAFEFF0A77\r\nS3150001BBA80410A0E338008DE2110100EBD8F7FFEB92\r\nS3150001BBB80030E0E3012CA0E3CB2B03E5022CA0E344\r\nS3150001BBC8CB2B03E50150A0E3DBFDFFEA010056E3B9\r\nS3150001BBD8DDFEFF1A0030D4E50A0053E30800000A27\r\nS3150001BBE8040053E3D8FEFF1AB4FFFFEA0030D4E598\r\nS3150001BBF8300053E31700001A0110D4E53F0051E362\r\nS3150001BC080200009A38008DE20410A0E3ADFFFFEAB6\r\nS3150001BC18210157E1FAFFFF1A1C009DE50120A0E367\r\nS3150001BC28F70200EB1C009DE51010A0E302F7FFEBFD\r\nS3150001BC3838008DE21C109DE51220A0E32C308DE220\r\nS3150001BC48C30000EB1C009DE51210A0E32C209DE526\r\nS3150001BC58ECF9FFEBBCFEFFEAA00053E30B00001A68\r\nS3150001BC680130D4E53F0053E3E5FFFF8A230157E19D\r\nS3150001BC78E3FFFF1A0A10A0E338008DE2DC0000EBAF\r\nS3150001BC88A3F7FFEB0750A0E301B0D4E5AAFDFFEA4D\r\nS3150001BC98402083E2FF2002E2020052E31900008AF3\r\nS3150001BCA80100D4E53F0050E3D5FFFF8A2061A0E1FA\r\nS3150001BCB8070056E1D2FFFF1AE00200EB000050E34D\r\nS3150001BCC8CFFFFF1A0A10A0E338008DE2C80000EB87\r\nS3150001BCD88FF7FFEB0050D4E5C10055E30850A003E8\r\nS3150001BCE80500000AC00055E30950A0030200000A36\r\nS3150001BCF8C20055E30A50A0030650A01301B0D4E5CB\r\nS3150001BD080670A0E18CFDFFEAB00053E30A00001AB1\r\nS3150001BD180120D4E53F0052E3B9FFFF8A220157E12A\r\nS3150001BD28B7FFFF1A34009DE52A10DDE5100300EB85\r\nS3150001BD38000050E361FFFF0AB1FFFFEA500053E339\r\nS3150001BD48AFFFFF1A0130D4E5000053E3ACFFFF1A39\r\nS3150001BD580030E0E3012CA0E3CB2B03E5022CA0E3A2\r\nS3150001BD68CB2B03E540309FE5003093E5030053E311\r\nS3150001BD78060000DA50309FE50FE0A0E113FF2FE13E\r\nS3150001BD8818309DE5001063E06C009FE5991200EB01\r\nS3150001BD980B50A0E368FDFFEA44D08DE2F04FBDE801\r\nS3150001BDA81EFF2FE160002000AC2A20008000200041\r\nS3150001BDB8841E1200B9002000010000A5E8800000D9\r\nS3150001BDC8140820003A1F12000020100885002000E0\r\nS3150001BDD8F40020006C0020006E002000780020008E\r\nS3150001BDE87B002000961E120073002000B21E12006E\r\nS3150001BDF8CE1E12002D2B2000F21E1200191F120052\r\nS3150001BE0878209FE50F3000E25233A0E12012A0E12D\r\nS3150001BE186C209FE50F1001E25211A0E164C09FE575\r\nS3150001BE282024A0E10F2002E25C22A0E1081001E231\r\nS3150001BE38042002E2103003E2022081E1032082E1BC\r\nS3150001BE4844109FE52036A0E10F3003E25133A0E10B\r\nS3150001BE58023003E2032082E12008A0E12C309FE5AD\r\nS3150001BE680F0000E25330A0E1013003E2030082E152\r\nS3150001BE781C309FE53300A0E1010000E21EFF2FE11F\r\nS3150001BE88C0220F00C0C90600B0C8030058E401006B\r\nS3150001BE9838D900000AE857EC00009FE51EFF2FE19C\r\nS3150001BEA8FC39200000009FE51EFF2FE1EC3720003A\r\nS3150001BEB800009FE51EFF2FE1FC39200000009FE5E9\r\nS3150001BEC81EFF2FE184432000010052E3F8402DE9CB\r\nS3150001BED80070A0E10150A0E10260A0E10040A0E3EA\r\nS3150001BEE80A00000A060054E1170000AA0010A0E3A0\r\nS3150001BEF80700A0E10120A0E19A0D00EB0430D5E787\r\nS3150001BF08030020E00400C5E7014084E2F4FFFFEAEC\r\nS3150001BF180460A0E10010A0E30700A0E10120A0E170\r\nS3150001BF28490D00EB0030D5E55334A0E1013003E2B9\r\nS3150001BF38000023E0106486E1014084E2040054E332\r\nS3150001BF48FF6006E2F2FFFF1A0060C5E5F840BDE8AA\r\nS3150001BF581EFF2FE1F74F2DE90350A0E10190A0E361\r\nS3150001BF68013042E21993A0E10030A0E3003085E5F3\r\nS3150001BF780060A0E10180A0E10270A0E10140A0E11A\r\nS3150001BF88043068E0070053E1160000AA0010A0E398\r\nS3150001BF980120A0E10600A0E100A0D4E5710D00EBA7\r\nS3150001BFA80130D4E4030020E0010044E5000096E5F1\r\nS3150001BFB892FFFFEB0030A0E10A00A0E100B095E591\r\nS3150001BFC804308DE500F6FFEB04309DE5030020E023\r\nS3150001BFD8013000E2990303E0ABB0A0E10BB083E1C5\r\nS3150001BFE800B085E5E5FFFFEA0CD08DE2F04FBDE82C\r\nS3150001BFF81EFF2FE1F8402DE90040A0E30070A0E103\r\nS3150001C0080160A0E10450A0E10010A0E30700A0E14F\r\nS3150001C0180120A0E10C0D00EB5634A0E1013003E24A\r\nS3150001C028000023E0105485E1014084E2040054E352\r\nS3150001C038FF5005E2F3FFFF1A0500A0E1F840BDE84D\r\nS3150001C0481EFF2FE1F04F2DE91CD04DE20C708DE259\r\nS3150001C0580190A0E10060A0E10210A0E30700A0E1C1\r\nS3150001C0680D30CDE540509DE50C20CDE5F2F5FFEB11\r\nS3150001C0780C309DE5000059E310308DE51D00000ADE\r\nS3150001C0880040A0E314408DE50010A0E30120A0E1E3\r\nS3150001C0980600A0E1330D00EB04B0D7E714309DE5A7\r\nS3150001C0A800002BE010808DE20800C4E7000096E549\r\nS3150001C0B8A3A0A0E151FFFFEB0020A0E10B00A0E146\r\nS3150001C0C804208DE5C0F5FFEB04209DE5020020E084\r\nS3150001C0D8012000E2014084E282218AE1040054E35E\r\nS3150001C0E814208DE5E7FFFF1A0800A0E10410A0E17E\r\nS3150001C0F8F2F8FFEB020000EA0700A0E10410A0E352\r\nS3150001C108F0F8FFEB14108DE20500A0E119F9FFEB39\r\nS3150001C11844109DE5000051E314309D15003081154A\r\nS3150001C128010059E30080A0E11D00001A010050E357\r\nS3150001C1380040A0130F00001A0070A0E30740A0E119\r\nS3150001C1480010A0E30600A0E10120A0E1BE0C00EB6F\r\nS3150001C1580030D5E55334A0E1013003E2000023E0C5\r\nS3150001C168107487E1014084E2040054E3F3FFFF1AE7\r\nS3150001C1780070C5E50A0000EA080054E10800000A53\r\nS3150001C1880010A0E30600A0E10120A0E1F50C00EBF8\r\nS3150001C1980430D5E7030020E00400C5E7014084E246\r\nS3150001C1A8F4FFFFEA0800A0E11CD08DE2F04FBDE8DC\r\nS3150001C1B81EFF2FE107402DE910C09DE500C08DE562\r\nS3150001C1C800C0A0E304C08DE59DFFFFEB0CD08DE216\r\nS3150001C1D804E09DE41EFF2FE1F04F2DE91CD04DE24E\r\nS3150001C1E802C0A0E148508DE2300095E888229FE51B\r\nS3150001C1F8013003E201A0A0E10010A0E310108DE5D3\r\nS3150001C20814108DE500208DE5FF1004E2602083E21D\r\nS3150001C2180C30A0E10060A0E150909DE5E4FFFFEB42\r\nS3150001C22858829FE5003098E5030053E30070A0E1CA\r\nS3150001C2384C029FC50710A0C16E1100CB040057E33D\r\nS3150001C2480100A0138900001A5530A0E30C30CDE592\r\nS3150001C2584130A0E30D30CDE54930A0E30E30CDE500\r\nS3150001C2680710A0E16D30E0E30C029FE50F30CDE544\r\nS3150001C2787C1100EB053094E10070A0E10600A011E5\r\nS3150001C288570C001B0600A0E140308DE20C0093E834\r\nS3150001C298360C00EB000055E3020054030600A0E14A\r\nS3150001C2A80A1027E00300001A0120A0E3C00C00EBE6\r\nS3150001C2B8007027E0010000EA0020A0E3BC0C00EBB7\r\nS3150001C2C8000059E3007089150500001A003098E549\r\nS3150001C2D8020053E3AC019FC50A10A0C10720A0C103\r\nS3150001C2E8441100CB0050A0E30540A0E10C308DE2DB\r\nS3150001C2F803A0D4E70020A0E30A10A0E10600A0E10C\r\nS3150001C308980C00EB10908DE200002AE00900C4E7C2\r\nS3150001C318000096E5B9FEFFEB00B0A0E10A00A0E136\r\nS3150001C32829F5FFEB0B0020E001B000E27F30E0E3E6\r\nS3150001C338930B0BE0014084E2A5508BE1040054E322\r\nS3150001C348FF5005E2E8FFFF1A0700A0E12010A0E36D\r\nS3150001C358AA0C00EB0070A0E10700A0E10810A0E319\r\nS3150001C368A60C00EB0010A0E30120A0E10070A0E1FB\r\nS3150001C3780600A0E17B0C00EBFFA007E200002AE023\r\nS3150001C3880400C9E7000096E59CFEFFEB00B0A0E1BA\r\nS3150001C3980A00A0E10CF5FFEB0B0020E001B000E27A\r\nS3150001C3A87F30E0E3930B0BE0014084E2A5508BE17B\r\nS3150001C3B8080054E3FF5005E2E6FFFF1A0900A0E171\r\nS3150001C3C80410A0E10520A0E13CF8FFEBA8009FE5D9\r\nS3150001C3D845F8FFEB000050E30500001A003098E528\r\nS3150001C3E8000053E31E0000DA9C009FE5011100EBF3\r\nS3150001C3F81B0000EA0420A0E37C109FE508008DE2FB\r\nS3150001C408981000EB2010A0E30700A0E17B0C00EBDD\r\nS3150001C4180010A0E30120A0E10040A0E10600A0E190\r\nS3150001C428630C00EB0410A0E30050A0E108008DE2C4\r\nS3150001C4380C1100EB042025E00030A0E3010053E1D4\r\nS3150001C448000052010000A0030800000A003098E528\r\nS3150001C458000053E3040000DA30009FE5E51000EB25\r\nS3150001C468010000EA0200A0E3000000EA0300A0E3DD\r\nS3150001C4781CD08DE2F04FBDE81EFF2FE1FC392000EC\r\nS3150001C48880002000CC1F1200DF1F1200F71F1200C8\r\nS3150001C4981C20120030402DE91CD04DE228508DE2B7\r\nS3150001C4A8300095E830008DE830508DE2300095E88F\r\nS3150001C4B800C0A0E308408DE50C508DE510C08DE560\r\nS3150001C4C844FFFFEB1CD08DE23040BDE81EFF2FE193\r\nS3150001C4D8F3412DE9F4509FE502C0A0E10360A0E114\r\nS3150001C4E800508DE50110A0E33020A0E30C30A0E157\r\nS3150001C4F82FFFFFEB010050E30040A0E10800001AFE\r\nS3150001C508CC309FE5003093E5000053E3270000DABD\r\nS3150001C518C0309FE5C0009FE5E81DD3E5B51000EBE7\r\nS3150001C528220000EA120050E30700000AA0309FE546\r\nS3150001C538003093E5000053E31E0000DA9C009FE5F6\r\nS3150001C5480410A0E1AB1000EB1A0000EA84409FE555\r\nS3150001C5580500A0E11010A0E3F88DD4E5F97DD4E536\r\nS3150001C568B5F4FFEBF83DD4E5080053E10200001AE3\r\nS3150001C578F93DD4E5070053E10600000A50309FE56E\r\nS3150001C588003093E5000053E30C0000DA50009FE504\r\nS3150001C598981000EB090000EA0600A0E10510A0E1E9\r\nS3150001C5A81020A0E32F1000EB0000A0E3040000EA2E\r\nS3150001C5B80400A0E1020000EA0200A0E3000000EA8C\r\nS3150001C5C80300A0E308D08DE2F041BDE81EFF2FE18C\r\nS3150001C5D8FC39200080002000142C2000482012007D\r\nS3150001C5E85820120079201200F04F2DE90340A0E1EE\r\nS3150001C5F874319FE502C0A0E134D04DE200308DE5EB\r\nS3150001C6080110A0E3A020A0E30C30A0E10060A0E1A6\r\nS3150001C618E7FEFFEB010050E30300001A4C819FE59A\r\nS3150001C628E83DD8E50A0053E30800000A40319FE5D2\r\nS3150001C638003093E5000053E3450000DA2C319FE50D\r\nS3150001C64830019FE5E81DD3E56A1000EB400000EADA\r\nS3150001C65808708DE20410A0E11020A0E30700A0E114\r\nS3150001C668001000EB0700A0E11010A0E372F4FFEB45\r\nS3150001C6780050A0E30540A0E10010A0E30120A0E1DD\r\nS3150001C6880600A0E1B70B00EB04A0D7E71C908DE2EA\r\nS3150001C69800002AE00900C4E7000096E5D7FDFFEB94\r\nS3150001C6A800B0A0E10A00A0E147F4FFEB014084E2F3\r\nS3150001C6B80B0020E0A550A0E101B000E2120054E30E\r\nS3150001C6C88B5885E1EBFFFF1A0410A0E10520A0E1D4\r\nS3150001C6D80900A0E179F7FFEB8C009FE582F7FFEBF4\r\nS3150001C6E80040A0E30070A0E10450A0E10010A0E31F\r\nS3150001C6F80600A0E10120A0E1530B00EBE83DD8E5D7\r\nS3150001C7085335A0E1013003E2000023E0104584E13E\r\nS3150001C718015085E2040055E3FF4004E2F2FFFF1AE7\r\nS3150001C728010057E30A0054030000A0030100A01307\r\nS3150001C7380A00000A38309FE5003093E5000053E30C\r\nS3150001C748050000DA30009FE50410A0E1291000EB8E\r\nS3150001C758010000EA0100A0E3000000EA0200A0E3EC\r\nS3150001C76834D08DE2F04FBDE81EFF2FE1FC392000E1\r\nS3150001C778142C20008000200048201200912012006D\r\nS3150001C78807402DE944309FE5001090E200308DE521\r\nS3150001C7980110A0135020A0E30030A0E384FEFFEBB4\r\nS3150001C7A8001050E20100A0010500000A20309FE5B3\r\nS3150001C7B8003093E5000053E318009FC50D1000CB28\r\nS3150001C7C80100A0E30CD08DE204E09DE41EFF2FE1F9\r\nS3150001C7D8FC39200080002000AC20120008402DE919\r\nS3150001C7E80030A0E114009FE50222A0E1010280E0E9\r\nS3150001C7F80310A0E19B0F00EB0840BDE81EFF2FE1E7\r\nS3150001C8088443200008402DE910309FE50222A0E16B\r\nS3150001C818011283E0930F00EB0840BDE81EFF2FE1EC\r\nS3150001C8288443200008402DE90C309FE5011083E080\r\nS3150001C8388C0F00EB0840BDE81EFF2FE18443200062\r\nS3150001C848D4209FE5003282E00410D3E50022D2E726\r\nS3150001C8580110E0E1FF1001E2010052E12C00001A8B\r\nS3150001C8680810D3E5020051E12900001A0510D3E5A5\r\nS3150001C8780120D3E50110E0E1FF1001E2010052E1D8\r\nS3150001C8882300001A0910D3E5020051E12000001A1D\r\nS3150001C8980610D3E50220D3E50110E0E1FF1001E21D\r\nS3150001C8A8010052E11A00001A0A10D3E5020051E10B\r\nS3150001C8B81700001A0710D3E50320D3E50110E0E1BC\r\nS3150001C8C8FF1001E2010052E11100001A0B10D3E535\r\nS3150001C8D8020051E10E00001A0D10D3E50C20D3E534\r\nS3150001C8E80110E0E1FF1001E2010052E10800001A1F\r\nS3150001C8F80E10D3E5020051E10500001A0F00D3E539\r\nS3150001C9080000E0E1FF0000E2000052E00100A01390\r\nS3150001C9181EFF2FE10100A0E31EFF2FE18443200043\r\nS3150001C928F8402DE90070A0E10200A0E10160A0E154\r\nS3150001C9380250A0E1C1FFFFEB004050E20140A01305\r\nS3150001C9480700001A24309FE5055283E00700A0E19D\r\nS3150001C9580510A0E10420A0E3420F00EB0C30D5E559\r\nS3150001C9680030C6E50400A0E1F840BDE81EFF2FE14E\r\nS3150001C97884432000F7402DE974409FE508508DE275\r\nS3150001C988040025E5024284E00470A0E30160A0E109\r\nS3150001C9980720A0E10510A0E10400A0E1310F00EB9A\r\nS3150001C9A80510A0E10720A0E1080084E22D0F00EBA5\r\nS3150001C9B804309DE5070084E00330E0E10510A0E1BD\r\nS3150001C9C80720A0E104308DE5260F00EB0630E0E1F3\r\nS3150001C9D8FF3003E20000A0E30C60C4E50D30C4E5B6\r\nS3150001C9E80E60C4E50F30C4E50CD08DE2F040BDE819\r\nS3150001C9F81EFF2FE18443200013402DE90A30A0E3EE\r\nS3150001CA080003A0E1930121E028309FE50640A0E359\r\nS3150001CA18011083E00420A0E10D00A0E1110F00EB55\r\nS3150001CA280D00A0E10410A0E18E0F00EB08D08DE205\r\nS3150001CA381040BDE81EFF2FE1B443200010402DE948\r\nS3150001CA4820D04DE270109FE51020A0E30D00A0E173\r\nS3150001CA58040F00EB64109FE51020A0E310008DE29F\r\nS3150001CA68000F00EB58009FE50010A0E3012AA0E3A0\r\nS3150001CA78700F00EB0340A0E30410A0E10D00A0E154\r\nS3150001CA880120A0E354FFFFEB7E0054E3044084D267\r\nS3150001CA98F8FFFFDA104084E2FF0054E3F5FFFFDAFE\r\nS3150001CAA810108DE21020A0E314009FE5ED0E00EBB7\r\nS3150001CAB820D08DE21040BDE81EFF2FE15F0D120068\r\nS3150001CAC86F0D120084432000F04F2DE900A0A0E16C\r\nS3150001CAD844D04DE20300A0E101B0A0E10610A0E3B5\r\nS3150001CAE8600F00EB0070A0E30040A0E10150A0E157\r\nS3150001CAF81C708DE520708DE50190A0E31CF3FFEB1A\r\nS3150001CB085BF7FFEB0030E0E3012CA0E3CF9B03E5E5\r\nS3150001CB18CB2B03E5022CA0E3CB2B03E524008DE206\r\nS3150001CB280710A0E118208DE2B8F6FFEB003050E2BD\r\nS3150001CB3858619FE530808DE20700001A002096E5CE\r\nS3150001CB48070052E1010000CA0070A0E32C0000EAC8\r\nS3150001CB583C019FE514308DE5270000EA0020A0E39B\r\nS3150001CB680030A0E308208DE50C308DE530008DE816\r\nS3150001CB781C008DE218109DE50A20A0E10B30A0E10A\r\nS3150001CB8843FEFFEB005050E20500000A003096E52F\r\nS3150001CB98000053E3EBFFFFDAF8009FE5150F00EB02\r\nS3150001CBA8170000EA1C008DE218109DE50A20A0E195\r\nS3150001CBB80830A0E145FEFFEB004050E20400000A00\r\nS3150001CBC8003096E5000053E3CC009FC50A0000CA71\r\nS3150001CBD8DCFFFFEA1C008DE218109DE5E7FEFFEB7E\r\nS3150001CBE8000050E30970A0010500000A003096E52F\r\nS3150001CBF8000053E3D3FFFFDAA0009FE5FD0E00EB2B\r\nS3150001CC08D0FFFFEA1C008DE2F50900EB003096E53E\r\nS3150001CC18010053E388009FC59E0E00CB84309FE533\r\nS3150001CC280020A0E324308DE50130A0E378C09FE51C\r\nS3150001CC3800308DE524008DE20230A0E10410A0E366\r\nS3150001CC480FE0A0E11CFF2FE10040E0E30020A0E394\r\nS3150001CC58015CA0E31030A0E3CF5B04E50710A0E177\r\nS3150001CC6804308DE500808DE50230A0E1FF00A0E3E8\r\nS3150001CC78990E00EBE000A0E3CB5B04E515ECFFEBB6\r\nS3150001CC88CE0E00EB44D08DE2F04FBDE81EFF2FE13A\r\nS3150001CC9880002000C920120072221200DB20120037\r\nS3150001CCA8EC201200F72012004444444414082000E2\r\nS3150001CCB8F04F2DE90080A0E174D04DE20300A0E118\r\nS3150001CCC801B0A0E10610A0E3E60E00EB0090A0E398\r\nS3150001CCD80040A0E10150A0E11C908DE520908DE572\r\nS3150001CCE801A0A0E3A2F2FFEBE1F6FFEB0030E0E3DF\r\nS3150001CCF8012CA0E3CFAB03E5CB2B03E5022CA0E384\r\nS3150001CD08CB2B03E524008DE20910A0E118208DE262\r\nS3150001CD183EF6FFEB003050E21C629FE530708DE273\r\nS3150001CD280700001A002096E5090052E1010000CA31\r\nS3150001CD380090A0E3550000EA00029FE514308DE556\r\nS3150001CD48500000EA0881A0E10020A0E30030A0E33A\r\nS3150001CD58FF8008E208208DE50C308DE530008DE86E\r\nS3150001CD681C008DE218109DE50820A0E10B30A0E11A\r\nS3150001CD78C7FDFFEB004050E20500000A003096E5CA\r\nS3150001CD88000053E3E9FFFFDAB4019FE5990E00EBD2\r\nS3150001CD983E0000EA1C008DE218109DE50820A0E17E\r\nS3150001CDA80730A0E1C9FDFFEB005050E20400000A7C\r\nS3150001CDB8003096E5000053E388019FC5310000CA9B\r\nS3150001CDC8DAFFFFEA012088E2FF2002E21C008DE279\r\nS3150001CDD818109DE5103087E2BCFDFFEB004050E2DC\r\nS3150001CDE80400000A003096E5000053E358019FC588\r\nS3150001CDF8240000CACDFFFFEA022088E21C008DE26A\r\nS3150001CE0818109DE5FE2002E2203087E2AFFDFFEB18\r\nS3150001CE18005050E20400000A003096E5000053E392\r\nS3150001CE2828019FC5170000CAC0FFFFEA038088E2F0\r\nS3150001CE38FF2008E21C008DE218109DE5303087E2DC\r\nS3150001CE48A2FDFFEB004050E20400000A003096E51F\r\nS3150001CE58000053E3F8009FC50A0000CAB3FFFFEAC2\r\nS3150001CE681C008DE218109DE544FEFFEB000050E31F\r\nS3150001CE780A90A0010500000A003096E5000053E378\r\nS3150001CE88AAFFFFDACC009FE55A0E00EBA7FFFFEADF\r\nS3150001CE981C008DE2520900EB003096E5010053E3D0\r\nS3150001CEA8B4009FC5FB0D00CBB0309FE50020A0E381\r\nS3150001CEB824308DE50130A0E3A4C09FE500308DE55F\r\nS3150001CEC824008DE20230A0E10410A0E30FE0A0E106\r\nS3150001CED81CFF2FE12060A0E30040E0E3015CA0E332\r\nS3150001CEE80020A0E3CF5B04E50910A0E100708DE501\r\nS3150001CEF80230A0E104608DE5FF00A0E3F60D00EB2A\r\nS3150001CF08067087E00020A0E30910A0E10230A0E145\r\nS3150001CF1800708DE504608DE5FF00A0E3EE0D00EBE2\r\nS3150001CF28E000A0E3CB5B04E56AEBFFEB230E00EB25\r\nS3150001CF3874D08DE2F04FBDE81EFF2FE1800020007E\r\nS3150001CF48C9201200722212000B2112001E211200A2\r\nS3150001CF583121120044211200EC201200572112003F\r\nS3150001CF684444444414082000F04F2DE90090A0E100\r\nS3150001CF783CD04DE20300A0E101A0A0E10610A0E328\r\nS3150001CF880360A0E1370E00EB0070A0E31020A0E3D8\r\nS3150001CF980040A0E10150A0E128008DE20A1086E2D6\r\nS3150001CFA8B00D00EB0180A0E314708DE518708DE5D6\r\nS3150001CFB8EFF1FFEB2EF6FFEB0030E0E3012CA0E3E7\r\nS3150001CFC8CF8B03E5CB2B03E5022CA0E3CB2B03E5A3\r\nS3150001CFD81C008DE20710A0E110208DE28BF5FFEB16\r\nS3150001CFE800B050E244619FE50500001A003096E55D\r\nS3150001CFF8070053E138019FC5110000CA0040A0E3AC\r\nS3150001D008280000EA30008DE80050A0E30040A0E3C4\r\nS3150001D01808408DE50C508DE514008DE210109DE554\r\nS3150001D0280920A0E10A30A0E119FDFFEB005050E20A\r\nS3150001D0380500000A003096E5000053E3EEFFFFDA2B\r\nS3150001D048F0009FE5EB0D00EBEBFFFFEA14008DE224\r\nS3150001D05810109DE50920A0E128308DE261FDFFEB66\r\nS3150001D068004050E20400000A003096E5000053E350\r\nS3150001D078C4009FC5F2FFFFCADFFFFFEA14008DE275\r\nS3150001D08810109DE5BDFDFFEB000050E30840A0012F\r\nS3150001D0980400000A003096E5000053E3D6FFFFDAE4\r\nS3150001D0A898009FE5D30D00EB14008DE2CC0800EB48\r\nS3150001D0B8003096E5010053E384009FC5750D00CB4A\r\nS3150001D0C880309FE50020A0E31C308DE50130A0E308\r\nS3150001D0D874C09FE500308DE51C008DE20230A0E1A9\r\nS3150001D0E80410A0E30FE0A0E11CFF2FE10050E0E3EC\r\nS3150001D0F80020A0E3016CA0E3CF6B05E50410A0E1D5\r\nS3150001D10800208DE504208DE50230A0E1FF00A0E3B3\r\nS3150001D118710D00EBE000A0E3CB6B05E5EDEAFFEB53\r\nS3150001D128A60D00EB3CD08DE2F04FBDE81EFF2FE1C6\r\nS3150001D13880002000C9201200722212006C21120000\r\nS3150001D148EC2012007E2112004444444414082000B5\r\nS3150001D158F0472DE90070A0E1200CA0E10150A0E103\r\nS3150001D1680240A0E10360A0E197F1FFEB00A0A0E176\r\nS3150001D178250CA0E10090D6E593F1FFEB090020E02C\r\nS3150001D1888487A0E1FF9000E2A89F29E009305AE0D0\r\nS3150001D1982708A0E1009073E2FF0000E20390B9E0DE\r\nS3150001D1A889F1FFEB00A0A0E12508A0E1FF0000E25C\r\nS3150001D1B80180D6E584F1FFEB080020E0FF8000E25C\r\nS3150001D1C82704A0E1843BA0E1FF0000E2A38F28E049\r\nS3150001D1D87DF1FFEB0070A0E12504A0E1FF0000E26C\r\nS3150001D1E80260D6E578F1FFEB060020E0014004E293\r\nS3150001D1F8FF0000E208005AE10080A013018009023D\r\nS3150001D208040020E0000057E10000A0130100080215\r\nS3150001D218F047BDE81EFF2FE1F04F2DE9FF0000E2C0\r\nS3150001D228ADDF4DE2FF1001E21C008DE528108DE50A\r\nS3150001D2380300A0E10610A0E302B0A0E1890D00EB0E\r\nS3150001D2480040A0E320008DE524108DE544408DE5DE\r\nS3150001D25848408DE50FFBFFEB0B30A0E358308DE519\r\nS3150001D2685C308DE560308DE564308DE568308DE59F\r\nS3150001D2786C308DE500A0A0E13DF1FFEB0400A0E1D3\r\nS3150001D28849F1FFEB7AF5FFEB0030E0E30120A0E37B\r\nS3150001D298CF2B03E5012CA0E3CF2B03E5022CA0E35A\r\nS3150001D2A8CB2B03E5E000A0E38AEAFFEBC800A0E385\r\nS3150001D2B8570D00EB7D5EA0E30470A0E10460A0E1D8\r\nS3150001D2C8E000A0E383EAFFEB6400A0E3500D00EB66\r\nS3150001D2D8A400A0E37FEAFFEB0030E0E3C33B13E5DC\r\nS3150001D2E8020513E35900000A4C008DE20010A0E381\r\nS3150001D2F830208DE2C5F4FFEB000050E30500001A6B\r\nS3150001D30818369FE5003093E5000053E310069FC5E4\r\nS3150001D318150000CA4D0000EA20308DE20C0093E8A2\r\nS3150001D3280C008DE80020A0E30030A0E308208DE57D\r\nS3150001D3380C308DE534308DE210308DE544008DE2F8\r\nS3150001D34830109DE51C209DE528309DE5A1FBFFEBEE\r\nS3150001D358000050E30600000AC0359FE5003093E55A\r\nS3150001D368000053E3390000DAB8059FE5210D00EB0B\r\nS3150001D378360000EA20308DE20C0093E80C008DE8B7\r\nS3150001D3880220A0E30030A0E308208DE50C308DE5EE\r\nS3150001D39838308DE210308DE544008DE230109DE580\r\nS3150001D3A81C209DE528309DE58AFBFFEB000050E334\r\nS3150001D3B80500000A64359FE5003093E5000053E354\r\nS3150001D3C864059FC5E8FFFFCA200000EA34009DE511\r\nS3150001D3D87D1FA0E3890800EB50859FE50030A0E199\r\nS3150001D3E80300A0E10110A0E3840800EB38209DE5C5\r\nS3150001D3F8020050E10030A0E10300000A018088E242\r\nS3150001D4087D0E58E3F5FFFF1A0C0000EA0C259FE58F\r\nS3150001D418002092E5080055E10850A0A1080054E152\r\nS3150001D4280840A0B1030052E3087087E000808DC56B\r\nS3150001D438FC049FC50610A0C134209DC5ED0C00CB88\r\nS3150001D448016086E20A0056E39CFFFF1A010000EA22\r\nS3150001D458000056E32E01000AC0349FE5003093E52B\r\nS3150001D468020053E3070000DA0610A0E10700A0E175\r\nS3150001D4780B0C00EB0510A0E10030A0E10420A0E1AF\r\nS3150001D488B0049FE5DB0C00EB2B34A0E12C308DE5D5\r\nS3150001D498012CA0E30030E0E3CB2B03E5022CA0E34B\r\nS3150001D4A8CF2B03E50080A0E370649FE5003096E585\r\nS3150001D4B8030053E380049FC5CE0C00CBE000A0E334\r\nS3150001D4C804EAFFEB6400A0E3D10C00EBA400A0E39F\r\nS3150001D4D800EAFFEB0030E0E3C33B13E5020513E383\r\nS3150001D4E89200000A4C008DE20010A0E330208DE284\r\nS3150001D4F846F4FFEB000050E30400001A003096E5FD\r\nS3150001D508000053E318049FC5150000CA870000EA06\r\nS3150001D51820308DE20C0093E80C008DE80020A0E392\r\nS3150001D5280030A0E308208DE50C308DE534308DE21E\r\nS3150001D53810308DE544008DE230109DE51C209DE5F7\r\nS3150001D54828309DE523FBFFEB000050E30600000AA7\r\nS3150001D558C8339FE5003093E5000053E3730000DA12\r\nS3150001D568C0039FE5A30C00EB700000EA2C309DE593\r\nS3150001D5783C108DE2012003E204108DE5FF300BE239\r\nS3150001D5880210A0E300A08DE544008DE2602082E24E\r\nS3150001D598ABFAFFEB040050E30010A0E17C639FE5C2\r\nS3150001D5A80500000A003096E5000053E35F0000DA43\r\nS3150001D5B888039FE58F0C00EB5C0000EA0A00A0E1F6\r\nS3150001D5C8A80C00EB002096E5030052E30030A0E129\r\nS3150001D5D838008DE5050000DA3C209DE560039FE5EE\r\nS3150001D5E800208DE50810A0E134209DE5810C00EBB3\r\nS3150001D5F80060A0E30600DAE773F0FFEB3C309DE537\r\nS3150001D608082003E2A20150E10010A0030110A013B3\r\nS3150001D61840208DE20210C6E7016086E28330A0E170\r\nS3150001D628040056E33C308DE5F1FFFF1A34009DE511\r\nS3150001D6380A1045E2F10700EB099045E20060A0E116\r\nS3150001D6480070A0E3093084E2090053E11F0000BA23\r\nS3150001D6580600A0E10110A0E3E80700EB38109DE5FC\r\nS3150001D66801C020E00C20A0E140308DE218C08DE514\r\nS3150001D6780060A0E1B5FEFFEB000050E318C09DE590\r\nS3150001D6881000000A0A0057E30E0000CA373087E285\r\nS3150001D6982B0E8DE2833180E0106203E50CC203E5AF\r\nS3150001D6A878329FE5003093E5017087E2030053E382\r\nS3150001D6B86C708DE58C029FC50910A0C10C20A0C114\r\nS3150001D6C80630A0C14B0C00CB019089E2DCFFFFEAD2\r\nS3150001D6D86CE09DE500005EE31100000A0030A0E35E\r\nS3150001D6E858208DE2032192E70A0052E3770000CA27\r\nS3150001D6F8013083E2050053E3F8FFFF1A0030A0E387\r\nS3150001D70858208DE2032192E702005EE16F0000BA1C\r\nS3150001D718013083E2050053E3F8FFFF1A000000EA2F\r\nS3150001D72800E080E5018088E20F0058E35DFFFF1AFB\r\nS3150001D738022CA0E30030E0E3CB2B03E544008DE2A5\r\nS3150001D748270700EB00329FE50020A0E34C308DE56A\r\nS3150001D7580130A0E300308DE54C008DE20230A0E1F6\r\nS3150001D7680410A0E3E4C19FE50FE0A0E11CFF2FE14F\r\nS3150001D7782C209DE5FFB00BE2FF3002E203B48BE0FB\r\nS3150001D7880040A0E358308DE2048193E70A0058E38C\r\nS3150001D7980BA0A0D39A0403D00050A0D31C308DD57A\r\nS3150001D7A8120000DA014084E2050054E3F4FFFF1A8F\r\nS3150001D7B8300000EA01CCA0E30070E0E33030A0E3DA\r\nS3150001D7C8CFCB07E5FF00A0E304308DE500908DE59A\r\nS3150001D7D80010A0E30620A0E10B30A0E118C08DE5FA\r\nS3150001D7E8BD0B00EB18C09DE5CBCB07E5055085E2DF\r\nS3150001D7F8080055E1EAFFFFAA70908DE23020A0E308\r\nS3150001D8080900A0E10010A0E30A0C00EB30309DE509\r\nS3150001D8181C009DE5086065E070308DE5A0208DE26D\r\nS3150001D828003085E0050056E30560A0A378708DE217\r\nS3150001D83883A182E000C0A0E306005CE1DCFFFFAA49\r\nS3150001D8480A10A0E10700A0E10420A0E318C08DE5B5\r\nS3150001D858840B00EB040087E204108AE20420A0E3AB\r\nS3150001D868800B00EB18C09DE5087087E201C08CE2C9\r\nS3150001D87808A08AE2EFFFFFEA0020A0E30040E0E308\r\nS3150001D888015CA0E3CF5B04E50230A0E100208DE551\r\nS3150001D89804208DE5FF00A0E30110A0E38E0B00EB49\r\nS3150001D8A8CB5B04E574309FE5003093E5030053E351\r\nS3150001D8B89C009FC5770B00CBE000A0E305E9FFEBD1\r\nS3150001D8C8BE0B00EB0100A0E3B7EFFFEB100000EA87\r\nS3150001D8D85870A0E3930707E0A0208DE200C0A0E3FB\r\nS3150001D8E82B0E8DE2031180E0960F41E2581211E5E5\r\nS3150001D8F801005CE189FFFFAA6E1F82E2030091E83D\r\nS3150001D908076082E0030086E801C08CE2082082E213\r\nS3150001D918F2FFFFEAADDF8DE2F04FBDE81EFF2FE112\r\nS3150001D92880002000C9201200932112009F211200B5\r\nS3150001D938F5010000AB211200CE211200DC12120003\r\nS3150001D948ED2112000022120026221200444444440A\r\nS3150001D9581408200046221200F04F2DE974719FE544\r\nS3150001D9682CD04DE20040A0E30280A0E10360A0E1D3\r\nS3150001D97801A0A0E10090A0E1005097E514408DE5D3\r\nS3150001D98818408DE5004087E579EFFFEB0100A0E33C\r\nS3150001D99885EFFFEBB6F3FFEB0030E0E30120A0E3F0\r\nS3150001D9A8CF2B03E5012CA0E3CB2B03E5022CA0E347\r\nS3150001D9B8CB2B03E54B0FA0E3950B00EB080054E1D5\r\nS3150001D9C80D0000AAE000A0E3C2E8FFEB6400A0E3B3\r\nS3150001D9D88F0B00EBA400A0E3BEE8FFEB1C008DE271\r\nS3150001D9E80010A0E310208DE208F3FFEB00B050E22F\r\nS3150001D9F80600001A000055E3010000CA0080A0E3F2\r\nS3150001DA08130000EAD0009FE57A0B00EBFAFFFFEA64\r\nS3150001DA180610A0E3916420E0920B00EB0020A0E33E\r\nS3150001DA280030A0E303008DE808208DE50C308DE574\r\nS3150001DA3814008DE210109DE50920A0E10A30A0E14D\r\nS3150001DA4893FAFFEB000050E301408412DAFFFF1A54\r\nS3150001DA580180A0E314008DE2610600EB7C309FE5AE\r\nS3150001DA680020A0E31C308DE50130A0E370C09FE5DE\r\nS3150001DA7800308DE51C008DE20230A0E10410A0E320\r\nS3150001DA880FE0A0E11CFF2FE10630A0E3936424E038\r\nS3150001DA980020A0E30090E0E301ACA0E3CFAB09E5E9\r\nS3150001DAA80810A0E104308DE500408DE50230A0E1C3\r\nS3150001DAB8FF00A0E3080B00EBE000A0E3CBAB09E510\r\nS3150001DAC884E8FFEB3D0B00EB005087E52CD08DE297\r\nS3150001DAD8F04FBDE81EFF2FE180002000C92012008B\r\nS3150001DAE8444444441408200008402DE914309FE5B5\r\nS3150001DAF80010A0E1000083E50C009FE53D0B00EB5B\r\nS3150001DB080840BDE81EFF2FE18000200056221200C2\r\nS3150001DB1808402DE9C8FBFFEB0840BDE81EFF2FE1D1\r\nS3150001DB2808402DE900C0A0E10120A0E10300A0E121\r\nS3150001DB380C10A0E128FBFFEB0840BDE81EFF2FE112\r\nS3150001DB48F0412DE938D04DE20070A0E10160A0E175\r\nS3150001DB5808808DE20800A0E10710A0E10620A0E1F7\r\nS3150001DB6827FBFFEB0040E0E3015CA0E33030A0E3D4\r\nS3150001DB78CF5B04E50710A0E104308DE500808DE553\r\nS3150001DB880620A0E10030A0E3FF00A0E3D20A00EBE3\r\nS3150001DB98CB5B04E538D08DE2F041BDE81EFF2FE1ED\r\nS3150001DBA8F0432DE90060A0E34CD04DE20190A0E1DD\r\nS3150001DBB814608DE518608DE5EDEEFFEB0600A0E13A\r\nS3150001DBC8F9EEFFEB2AF3FFEB0030E0E30120A0E3D7\r\nS3150001DBD8CF2B03E5012CA0E3CB2B03E5022CA0E315\r\nS3150001DBE8CB2B03E51C008DE20610A0E110208DE287\r\nS3150001DBF886F2FFEB060050E10500001AA4329FE504\r\nS3150001DC08003093E5060053E19C029FC58C0000CACB\r\nS3150001DC188C0000EAFF9009E20670A0E10700A0E186\r\nS3150001DC280910A0E173FBFFEB000057E303008DE841\r\nS3150001DC38FF8006E21000001A0020A0E30030A0E3EE\r\nS3150001DC4808208DE50C308DE514008DE210109DE558\r\nS3150001DC580820A0E10930A0E10DFAFFEB000050E32E\r\nS3150001DC681800000A3C329FE5003093E5000053E3B3\r\nS3150001DC7838029FC5100000CA670000EA0240A0E307\r\nS3150001DC880050A0E308408DE50C508DE514008DE2A7\r\nS3150001DC9810109DE50820A0E10930A0E1FCF9FFEB91\r\nS3150001DCA8000050E30700000AF8319FE5003093E5CC\r\nS3150001DCB8000053E3580000DAF4019FE50710A0E1DC\r\nS3150001DCC8CC0A00EB540000EA14008DE210109DE521\r\nS3150001DCD80820A0E128308DE2FCF9FFEB000050E3B3\r\nS3150001DCE80500000ABC319FE5003093E5000053E3C7\r\nS3150001DCF8C0019FC5350000CA470000EA28008DE229\r\nS3150001DD080610A0E10120A0E3B3FAFFEB012088E2A7\r\nS3150001DD18FF2002E214008DE210109DE528308DE205\r\nS3150001DD28EAF9FFEB000050E30500000A74319FE5AC\r\nS3150001DD38003093E5000053E37C019FC5230000CA28\r\nS3150001DD48350000EA28008DE2011086E20120A0E3F1\r\nS3150001DD58A1FAFFEB022088E2FF2002E214008DE21D\r\nS3150001DD6810109DE528308DE2D8F9FFEB000050E34D\r\nS3150001DD780500000A2C319FE5003093E5000053E3C6\r\nS3150001DD8838019FC5110000CA230000EA28008DE268\r\nS3150001DD98021086E20120A0E3038088E28EFAFFEBF7\r\nS3150001DDA8FF2008E214008DE210109DE528308DE26F\r\nS3150001DDB8C6F9FFEB000050E30600000AE4309FE5D0\r\nS3150001DDC8003093E5000053E3130000DAF0009FE505\r\nS3150001DDD8880A00EB100000EA034086E238008DE26B\r\nS3150001DDE80410A0E10120A0E385FAFFEB2E108DE2D5\r\nS3150001DDF80420A0E33E008DE21A0A00EB017087E2D7\r\nS3150001DE0838008DE20410A0E10120A0E372FAFFEBCD\r\nS3150001DE18100057E3046086E27FFFFF1A14008DE2C3\r\nS3150001DE2810109DE555FAFFEB000050E30500000AC6\r\nS3150001DE3870309FE5003093E5000053E3010000DAF6\r\nS3150001DE4880009FE56B0A00EB14008DE2640500EB88\r\nS3150001DE58E000A0E39FE7FFEB580A00EB44309FE59B\r\nS3150001DE68003093E5010053E35C009FC5090A00CB26\r\nS3150001DE7858309FE50020A0E31C308DE50130A0E372\r\nS3150001DE8800308DE51C008DE20410A0E30230A0E10C\r\nS3150001DE983CC09FE50FE0A0E11CFF2FE14CD08DE2CD\r\nS3150001DEA8F043BDE81EFF2FE180002000C9201200C3\r\nS3150001DEB8662212007D2212000B2112001E21120079\r\nS3150001DEC83121120044211200EC2012009B2212007B\r\nS3150001DED84444444414082000F0472DE90380A0E196\r\nS3150001DEE838D04DE24030A0E30830CDE518608DE228\r\nS3150001DEF84330A0E30170A0E10C30CDE50010A0E3AA\r\nS3150001DF084130A0E30290A0E1FFA000E20A20A0E3CD\r\nS3150001DF180600A0E11030CDE5460A00EBDDF7FFEB80\r\nS3150001DF28080017E30040A0E1FF5007E21200000ACB\r\nS3150001DF380FEEFFEB0100A0E31BEEFFEB4CF2FFEB4C\r\nS3150001DF4800C0E0E30130A0E3CF3B0CE5013CA0E3D0\r\nS3150001DF58CB3B0CE5023CA0E3CB3B0CE54B0FA0E326\r\nS3150001DF682B0A00EBE000A0E35AE7FFEB6400A0E30D\r\nS3150001DF78270A00EBA400A0E356E7FFEB010015E32F\r\nS3150001DF881800000A0600A0E10010A0E314208DE2A3\r\nS3150001DF989EF1FFEB007050E20500001A78329FE50A\r\nS3150001DFA8003093E5000053E370029FC50A0000CADA\r\nS3150001DFB80A0000EA0000A0E314109DE5EFF9FFEB63\r\nS3150001DFC8000050E30700000A4C329FE5003093E554\r\nS3150001DFD8000053E3010000DA44029FE5050A00EB5D\r\nS3150001DFE80040A0E3760000EA00005AE32500000A93\r\nS3150001DFF808008DE20710A0E30020A0E304F1FFEB7F\r\nS3150001E0080400A0E138F1FFEB000050E30200000A2A\r\nS3150001E0180030D4E50A0053E30500000AF8319FE50C\r\nS3150001E028003093E5000053E3F8019FC5EAFFFFCAF4\r\nS3150001E038EAFFFFEA10008DE20110A0E321F1FFEBF0\r\nS3150001E0480400A0E128F1FFEB000050E30200000AFA\r\nS3150001E0580030D4E50A0053E30500000AB8319FE50C\r\nS3150001E068003093E5000053E3BC019FC5DAFFFFCA00\r\nS3150001E078DAFFFFEA0000A0E314109DE5BFF9FFEB04\r\nS3150001E088000050E3CFFFFF1A020015E31A00000A49\r\nS3150001E09808008DE20710A0E30020A0E3DCF0FFEB07\r\nS3150001E0A80400A0E110F1FFEB000050E3DAFFFF0ADC\r\nS3150001E0B80030D4E50A0053E3D7FFFF1A0C008DE2BE\r\nS3150001E0C80110A0E3FFF0FFEB0400A0E106F1FFEB6E\r\nS3150001E0D8000050E30200000A0030D4E50A0053E3C9\r\nS3150001E0E80500000A30319FE5003093E5000053E34F\r\nS3150001E0F838019FC5B8FFFFCAB8FFFFEA0000A0E3D1\r\nS3150001E108FF3009E200408DE50010A0E1A020A0E360\r\nS3150001E11827F8FFEB010050E30200001A0030D4E5AE\r\nS3150001E1280A0053E30500000AEC309FE5003093E549\r\nS3150001E138000053E3F8009FC5A7FFFFCAA7FFFFEA40\r\nS3150001E1481020A0E30810A0E124008DE2450900EBA8\r\nS3150001E15824008DE21010A0E3B7EDFFEB24008DE259\r\nS3150001E1681210A0E3D7F0FFEB0400A0E1DEF0FFEB0D\r\nS3150001E178010050E30200001A0030D4E50A0053E317\r\nS3150001E1880500000A90309FE5003093E5000053E34F\r\nS3150001E198A0009FC590FFFFCA90FFFFEA040015E3A0\r\nS3150001E1A80100001A0140A0E3050000EA0000A0E30F\r\nS3150001E1B814109DE571F9FFEB000050E3F8FFFF0A23\r\nS3150001E1C880FFFFEA0070E0E3018CA0E30430A0E3DE\r\nS3150001E1D80020A0E3CF8B07E5FF00A0E304308DE51F\r\nS3150001E1E800608DE50410A0E10230A0E13A0900EBD8\r\nS3150001E1F8100015E3CB8B07E50100001A000054E374\r\nS3150001E2080200001AE000A0E3B2E6FFEB6B0900EB9F\r\nS3150001E21838D08DE2F047BDE81EFF2FE180002000CF\r\nS3150001E228C9201200EC201200B6221200C2221200E6\r\nS3150001E238CE221200DA221200F9221200F0412DE94B\r\nS3150001E24828D04DE24030A0E314608DE20070A0E1D1\r\nS3150001E2580C30CDE50010A0E34330A0E30280A0E135\r\nS3150001E2680600A0E11220A0E31030CDE5710900EB0C\r\nS3150001E27808F7FFEB080017E30040A0E1FF5007E2AB\r\nS3150001E2881200000A3AEDFFEB0100A0E346EDFFEBB1\r\nS3150001E29877F1FFEB0010E0E30130A0E3CF3B01E5A6\r\nS3150001E2A8013CA0E3CB3B01E5023CA0E3CB3B01E506\r\nS3150001E2B84B0FA0E3560900EBE000A0E385E6FFEB70\r\nS3150001E2C86400A0E3520900EBA400A0E381E6FFEB9A\r\nS3150001E2D8020015E32000000A0C008DE20710A0E3F6\r\nS3150001E2E80020A0E34AF0FFEB0400A0E17EF0FFEB7B\r\nS3150001E2F8000050E30200000A0030D4E50A0053E3A7\r\nS3150001E3080500000A30319FE5003093E5000053E32C\r\nS3150001E31828019FC5300000CA300000EA10008DE2CE\r\nS3150001E3280110A0E367F0FFEB0400A0E16EF0FFEB3C\r\nS3150001E338000050E30200000A0030D4E50A0053E366\r\nS3150001E3480500000AF0309FE5003093E5000053E32D\r\nS3150001E358EC009FC5200000CA200000EA0000A0E3E7\r\nS3150001E3683020A0E3FF3008E200408DE50010A0E16F\r\nS3150001E3788FF7FFEB120050E30020A0E10500000A29\r\nS3150001E388B4309FE5003093E5000053E3B4009FC520\r\nS3150001E398110000CA110000EA0600A0E10410A0E17C\r\nS3150001E3A8B00800EB040015E30100001A0140A0E3E0\r\nS3150001E3B80B0000EA0000A0E30010A0E1EFF8FFEB74\r\nS3150001E3C8000050E3F8FFFF0A6C309FE5003093E543\r\nS3150001E3D8000053E3010000DA6C009FE5050900EB34\r\nS3150001E3E80040A0E30070E0E3018CA0E31230A0E353\r\nS3150001E3F80020A0E3CF8B07E5FF00A0E304308DE5FD\r\nS3150001E40800608DE50410A0E10230A0E1B20800EB3E\r\nS3150001E418100015E3CB8B07E50100001A000054E351\r\nS3150001E4280200001AE000A0E32AE6FFEBE30800EB8E\r\nS3150001E43828D08DE2F041BDE81EFF2FE180002000C3\r\nS3150001E448B6221200CE22120015231200EC20120069\r\nS3150001E45838402DE934509FE50040A0E330309FE570\r\nS3150001E4680500A0E10410A0E10820A0E3004083E52F\r\nS3150001E478F00800EB0400A0E10840C5E50940C5E540\r\nS3150001E4880A40C5E50B40C5E53840BDE81EFF2FE14A\r\nS3150001E498342B2000182B200073402DE90040A0E3FF\r\nS3150001E4A80050E0E3016CA0E3CF6B05E50410A0E1A1\r\nS3150001E4B800408DE504408DE50420A0E10430A0E18B\r\nS3150001E4C8FF00A0E3840800EB0400A0E1CB6B05E59F\r\nS3150001E4D808D08DE27040BDE81EFF2FE1F3472DE914\r\nS3150001E4E8C4A09FE500409AE5000054E30400A0019A\r\nS3150001E4F82A00000A0220A0E32B3AE0E3DF2E03E517\r\nS3150001E5080070A0E3000054E30050E0E3016CA0E3CF\r\nS3150001E51898909FE5110000DACF6B05E500309AE582\r\nS3150001E528002099E5033064E0200054E30480A0B19B\r\nS3150001E5382080A0A3033082E008018DE8FF00A0E354\r\nS3150001E5480730A0E10110A0E30820A0E1620800EB72\r\nS3150001E558044068E0CB6B05E5017087E2E8FFFFEA56\r\nS3150001E5680040A0E3CF6B05E50210A0E30420A0E17B\r\nS3150001E5780430A0E100408DE504408DE5FF00A0E3ED\r\nS3150001E588550800EBCB6B05E5000099E54410A0E3BF\r\nS3150001E5981C209FE500408AE5A60800EB0100A0E3E0\r\nS3150001E5A808D08DE2F047BDE81EFF2FE1142B2000AD\r\nS3150001E5B860002000B80B00001C329FE50020D3E55F\r\nS3150001E5C8040052E302F19F977A0000EAE8E5110098\r\nS3150001E5D808E6110088E61100D0E611009CE7110053\r\nS3150001E5E80120A0E30010E0E3000050E3CB2B01E596\r\nS3150001E5F80020C30510008305040083056F0000EAA7\r\nS3150001E608101093E5011081E2020051E3C8219FE54C\r\nS3150001E618101083E50F00001A000050E30A00000AF3\r\nS3150001E628040092E5090050E30000A0C30010C2C52A\r\nS3150001E638100082C5080082C50110A0C30020E0C3EE\r\nS3150001E6480410A0D3CF1B02C50010C2D5042093E540\r\nS3150001E658012082E2042083E5102093E5030052E3BA\r\nS3150001E66874219FC50010A0C3101082C5042093E52C\r\nS3150001E6780E0052E30410A0C34B0000CA4F0000EA83\r\nS3150001E688101093E5000050E3011081E248219FE54F\r\nS3150001E698101083E50200000A190051E3470000DA69\r\nS3150001E6A8390000EA0310A0E30010C2E5100082E574\r\nS3150001E6B8040082E5B200C2E10110A0E30020E0E314\r\nS3150001E6C8CF1B02E53D0000EA101093E5011081E237\r\nS3150001E6D8020051E300219FE5101083E50800001AA6\r\nS3150001E6E8B210D2E1000050E3A110A0E1021C81138F\r\nS3150001E6F8B210C2E1042093E5012082E2042083E5F9\r\nS3150001E708020000EA030051E30010A0C3101082C5FD\r\nS3150001E718041093E50A0051E3BC209FE52700001A7F\r\nS3150001E728B210D2E1B4009FE5000001E0020C50E30B\r\nS3150001E7380D00001A080092E514C092E5A110A0E1A7\r\nS3150001E7480010CCE7081092E50C0092E5011081E271\r\nS3150001E758000051E1081082E50010A0E3101082E5DF\r\nS3150001E7680210A0B3110000BA070000EA000051E345\r\nS3150001E7780010A013101082150300001A0100A0E36F\r\nS3150001E7880030E0E3CB0B03E51EFF2FE10410A0E305\r\nS3150001E798060000EA102093E5012082E20A0052E30E\r\nS3150001E7A8102083E5050000DA0010A0E328209FE584\r\nS3150001E7B80010C2E5010000EA0020A0E30020C3E53D\r\nS3150001E7C80030D3E5040053E30120A0030030E00341\r\nS3150001E7D8CB2B03050000A0E31EFF2FE1582B2000D9\r\nS3150001E7E80102000013402DE974E4FFEB2B2AE0E354\r\nS3150001E7F8BF3F12E5014013E2FF30A013DB3F0215CC\r\nS3150001E808F9FFFF1A0020E0E30430A0E3CF3B02E55D\r\nS3150001E818013CA0E3CF3B02E54100A0E32DE5FFEB78\r\nS3150001E8280430A0E12B2AE0E3BF1F12E5010011E342\r\nS3150001E838FF10A013DB1F0215BF2F12E5013083124B\r\nS3150001E848100012E32B2AE013DF2F121500208D1575\r\nS3150001E85884109FE500209D150020E0E3090053E39D\r\nS3150001E868BF1202E5EEFFFFDA70309FE5000093E57F\r\nS3150001E8780030A0E32B2AE0E3BF1F12E5010011E3F4\r\nS3150001E8880500000A58109FE50310D1E7013083E21D\r\nS3150001E898000053E1DB1F02E5090000AA2B2AE0E389\r\nS3150001E8A8BF1F12E5100011E3DF2F121504208D1585\r\nS3150001E8B824109FE504209D150020E0E3BF1202E520\r\nS3150001E8C8EBFFFFEA012CA0E30030E0E3CB2B03E5E5\r\nS3150001E8D808D08DE21040BDE81EFF2FE1010000A51A\r\nS3150001E8E8CCCA2000CCC82000F74F2DE948519FE536\r\nS3150001E8F848419FE5192EA0E34410A0E30070A0E16A\r\nS3150001E9080500A0E1CB0700EB013B85E20060A0E32F\r\nS3150001E918143084E5011BA0E36430A0E3200085E2FE\r\nS3150001E9280C3084E5345084E5386084E51860C4E524\r\nS3150001E9380060C4E537E4FFEB0030E0E30420A0E320\r\nS3150001E948CF2B03E56100A0E3E2E4FFEB203085E28B\r\nS3150001E95801CBA0E30680A0E10690A0E103B0A0E107\r\nS3150001E9682B2AE0E3FB2E12E50C2062E0020059E1B6\r\nS3150001E9780290A0B12B0AE0E3FB2E10E50C2062E021\r\nS3150001E988022BA0E1020552E31E00009A025083E21F\r\nS3150001E99805E06BE0010B5EE3FF5F43C2D020D3E1E4\r\nS3150001E9A8D110D3E102A04CE2013BA0C3025045C2FB\r\nS3150001E9B8EF5E00C5EB3E00C500005AE3FFCF8CD2DF\r\nS3150001E9C80100A0E302A08CD206008DE8F9FEFFEB58\r\nS3150001E9D80100A0E3F7FEFFEB04209DE560309FE50B\r\nS3150001E9E80200A0E100109DE50FE0A0E113FF2FE171\r\nS3150001E9F8000050E3026086E20180A0130530A0E121\r\nS3150001EA080AC0A0E1DAFFFFEA7D0E56E3D3FFFFDA7B\r\nS3150001EA180230A0E3000057E3DF3E00E524009F052E\r\nS3150001EA280910A0010820A001383094057107000BD0\r\nS3150001EA380CD08DE2F04FBDE81EFF2FE1142C20000B\r\nS3150001EA48582B200068132000FD231200F0432DE9FE\r\nS3150001EA584410A0E314D04DE2192EA0E3AC039FE5C0\r\nS3150001EA68740700EB290700EB1440A0E30100A0E3BB\r\nS3150001EA78030700EB0100A0E3010700EB0100A0E397\r\nS3150001EA88FF0600EB0100A0E3FD0600EB014054E29E\r\nS3150001EA98F5FFFF1A0A40A0E30000A0E3F80600EB21\r\nS3150001EAA80000A0E3F60600EB0000A0E3F40600EB85\r\nS3150001EAB80000A0E3F20600EB014054E2F5FFFF1A5D\r\nS3150001EAC80100A0E3EE0600EB0100A0E3EC0600EB73\r\nS3150001EAD80100A0E3EA0600EB0100A0E3E80600EB6B\r\nS3150001EAE80100A0E3E60600EB0100A0E3E40600EB63\r\nS3150001EAF80100A0E3E20600EB0100A0E3E00600EB5B\r\nS3150001EB080C339FE50000A0E30350D4E7DC0600EBD5\r\nS3150001EB180000A0E3DA0600EB0000A0E3D80600EB4C\r\nS3150001EB280000A0E3D60600EB0870A0E3016015E239\r\nS3150001EB380700000A0100A0E3D10600EB0100A0E3EB\r\nS3150001EB48CF0600EB0100A0E3CD0600EB0100A0E330\r\nS3150001EB58060000EA0600A0E1C90600EB0600A0E1EE\r\nS3150001EB68C70600EB0600A0E1C50600EB0600A0E11A\r\nS3150001EB78C30600EB017057E2A550A0E1EAFFFF1AB0\r\nS3150001EB880100A0E3BE0600EB0100A0E3BC0600EB12\r\nS3150001EB980100A0E3BA0600EB014084E20100A0E30C\r\nS3150001EBA8B70600EB0E0054E3D4FFFF1A0A40A0E3B0\r\nS3150001EBB80000A0E3B20600EB0000A0E3B00600EBFC\r\nS3150001EBC80000A0E3AE0600EB0000A0E3AC0600EBF4\r\nS3150001EBD8014054E2F5FFFF1A0A50A0E30100A0E341\r\nS3150001EBE8A70600EB0100A0E3A50600EB0100A0E3E0\r\nS3150001EBF8A30600EB0100A0E3A10600EB015055E2D4\r\nS3150001EC08F5FFFF1A0C329FE5006093E5036086E283\r\nS3150001EC1804129FE50620A0E100029FE5006083E556\r\nS3150001EC28900600EB0207A0E32DE4FFEB63E3FFEB9D\r\nS3150001EC380030E0E30420A0E3CB2B03E58000A0E34A\r\nS3150001EC4824E4FFEBD8419FE5C0319FE5143084E504\r\nS3150001EC586430A0E30C3084E50030A0E30030C4E55D\r\nS3150001EC68C0219FE50030E0E3BF2203E5C33B13E57E\r\nS3150001EC78020513E35F00000A2B3AE0E3BF2F13E511\r\nS3150001EC88010012E30020A013DB2F0315BF3F13E594\r\nS3150001EC98100013E3F1FFFF0A2B3AE0E3DF9F13E5C8\r\nS3150001ECA80870A0E3FF9009E28080A0E3090008E06C\r\nS3150001ECB840FEFFEB000050E30300000A084094E51C\r\nS3150001ECC8050054E30400000A120000EA017057E245\r\nS3150001ECD8A880A0E1F4FFFF1AE0FFFFEA2C019FE5F7\r\nS3150001ECE844119FE50420A0E1A70600EB007050E25D\r\nS3150001ECF80800001A14019FE54410A0E32020A0E3B0\r\nS3150001ED08015085E2CB0600EB310055E31B00001AE2\r\nS3150001ED1818019FE5170000EA14019FE50410A0E118\r\nS3150001ED280520A0E1B30600EB0E308DE200308DE53B\r\nS3150001ED38D8109FE5022044E20D308DE2F4009FE5EC\r\nS3150001ED4817E8FFEBF0309FE50D10DDE50320D4E76A\r\nS3150001ED58020051E10400001A013083E20E20DDE5CC\r\nS3150001ED680330D4E7030052E10100000ACC009FE515\r\nS3150001ED78000000EAC8009FE5460600EB200000EA0D\r\nS3150001ED88000056E3A9FFFFDA0420A0E30030E0E320\r\nS3150001ED98CB2B03E58100A0E3CEE3FFEBFF20A0E345\r\nS3150001EDA82B3AE0E3DB2F03E504E3FFEB0700A0E1E1\r\nS3150001EDB82B3AE0E3BF2F13E5010012E30500000A31\r\nS3150001EDC858209FE50220D0E7010080E2060050E1C5\r\nS3150001EDD8DB2F03E595FFFFCA2B3AE0E3BF2F13E5C7\r\nS3150001EDE8100012E3DF3F1315FF3003120F30CD1564\r\nS3150001EDF80F30DD15EDFFFFEA48009FE50510A0E19C\r\nS3150001EE087C0600EB14D08DE2F043BDE81EFF2FE12E\r\nS3150001EE18142C20007F0D1200CCCA2000CCC820007B\r\nS3150001EE28342F2000582B2000010000A58D0D12005B\r\nS3150001EE387C2312003B231200FFFF0000122C200046\r\nS3150001EE48652312007123120093231200F0412DE964\r\nS3150001EE580080A0E10170A0E12C0600EB2840A0E3A8\r\nS3150001EE680100A0E3060600EB014054E2FBFFFF1A8E\r\nS3150001EE780A40A0E30000A0E3010600EB014054E2CA\r\nS3150001EE88FBFFFF1A070054E10100A0E30E0000AAE8\r\nS3150001EE98FB0500EB0100A0E3F90500EB0000A0E388\r\nS3150001EEA8F70500EB0450D8E70860A0E3010015E276\r\nS3150001EEB80100A013F20500EB016056E2A550A0E19E\r\nS3150001EEC8F9FFFF1A014084E2EDFFFFEAEC0500EBCA\r\nS3150001EED80A40A0E30000A0E3E90500EB014054E283\r\nS3150001EEE8FBFFFF1A0840A0E30100A0E3E40500EBDD\r\nS3150001EEF8014054E2FBFFFF1A1840A0E30100A0E31A\r\nS3150001EF08DF0500EB014054E2FBFFFF1A10309FE5D5\r\nS3150001EF18002093E5012082E2002083E5F041BDE867\r\nS3150001EF281EFF2FE1CCCA200073402DE90540A0E35E\r\nS3150001EF380420A0E164109FE50D00A0E1C90500EBDE\r\nS3150001EF480050E0E30460A0E3E000A0E361E3FFEB27\r\nS3150001EF58CB6B05E5C800A0E32D0600EB0207A0E38D\r\nS3150001EF685FE3FFEB95E2FFEBCF6B05E56100A0E3FD\r\nS3150001EF7858E3FFEBC800A0E3250600EB0D00A0E16E\r\nS3150001EF880410A0E1B0FFFFEB15FEFFEB0000A0E3C4\r\nS3150001EF9854FEFFEB08D08DE27040BDE81EFF2FE15D\r\nS3150001EFA8920D1200F0432DE90460A0E30040E0E36E\r\nS3150001EFB814D04DE2CB6B04E5E000A0E30190A0E19B\r\nS3150001EFC844E3FFEBC800A0E3110600EB0207A0E348\r\nS3150001EFD843E3FFEB79E2FFEBCF6B04E56100A0E3C6\r\nS3150001EFE83CE3FFEBC800A0E3090600EB0620A0E11D\r\nS3150001EFF828139FE50C008DE29A0500EB20439FE557\r\nS3150001F0080C008DE20610A0E18FFFFFEBF4FDFFEB8C\r\nS3150001F0180100A0E333FEFFEB383094E5000053E32B\r\nS3150001F0280450A0E1FC029F053000000A343094E543\r\nS3150001F038F4029FE50010D3E50120D3E50230D3E5BC\r\nS3150001F048EC0500EBE4029FE5920500EB0E30A0E328\r\nS3150001F0580C30CDE5343094E50030D3E50E708DE201\r\nS3150001F0680D30CDE50F808DE20C308DE20220A0E354\r\nS3150001F0780310A0E1B8029FE50730A0E100808DE505\r\nS3150001F08847E7FFEB0610A0E10C008DE26EFFFFEBF0\r\nS3150001F098D3FDFFEB0100A0E312FEFFEB386094E518\r\nS3150001F0A8030056E38C029F150610A0112A00001AC8\r\nS3150001F0B800808DE50120A0E3341094E50730A0E136\r\nS3150001F0C86C029FE536E7FFEB343094E50E10DDE57B\r\nS3150001F0D80120D3E5020051E10300001A0F10DDE516\r\nS3150001F0E80220D3E5020051E10200000A48029FE529\r\nS3150001F0F8680500EB860000EA0D10DDE50020D3E582\r\nS3150001F108020051E10200000A30029FE5B90500EB51\r\nS3150001F1187F0000EA0120A0E30C108DE20B30A0E38A\r\nS3150001F1280C30CDE508029FE5023081E000708DE5DF\r\nS3150001F1381BE7FFEB0610A0E10C008DE242FFFFEB97\r\nS3150001F148A7FDFFEB0100A0E3E6FDFFEB381094E510\r\nS3150001F1580A0051E30200000AE4019FE5A50500EB58\r\nS3150001F1686B0000EA00808DE50820A0E3341094E5E1\r\nS3150001F1780730A0E1B8019FE509E7FFEB343094E5D4\r\nS3150001F1880EC0DDE50820D3E502005CE10F10DDE5E0\r\nS3150001F1980930D3E50100001A030051E10300000A12\r\nS3150001F1A8A0019FE50C1481E0022483E0910500EBA0\r\nS3150001F1B8343095E506C0D3E50720D3E50CC8A0E1B0\r\nS3150001F1C802CC8CE00520D3E502C48CE00220D3E50D\r\nS3150001F1D80300D3E50228A0E1002C82E00100D3E573\r\nS3150001F1E80410D3E50030D3E5002482E0032082E051\r\nS3150001F1F854019FE501108CE07E0500EB4C019FE56B\r\nS3150001F208240500EB0830A0E30C30CDE5019089E236\r\nS3150001F2180040A0E3090054E10200001A30019FE50D\r\nS3150001F2281C0500EBFF40A0E30CC08DE20E708DE2D9\r\nS3150001F2380F808DE20C10A0E10730A0E10220A0E3C7\r\nS3150001F248EC009FE500808DE50D40CDE5D4E6FFEBAA\r\nS3150001F2580C008DE20410A0E3FBFEFFEB60FDFFEB63\r\nS3150001F2680100A0E39FFDFFEB383095E5060053E367\r\nS3150001F278AC609FE5DC009F159CFFFF1A00808DE5B9\r\nS3150001F2880420A0E3341096E50730A0E1A0009FE52D\r\nS3150001F298C3E6FFEB343096E50EC0DDE50420D3E581\r\nS3150001F2A802005CE10F10DDE50530D3E50100001A27\r\nS3150001F2B8030051E10300000A88009FE50C1481E070\r\nS3150001F2C8022483E04B0500EB340095E502E0D0E526\r\nS3150001F2D80330D0E50EE8A0E103EC8EE00130D0E57D\r\nS3150001F2E80020D0E503E48EE004C0D0E50530D0E582\r\nS3150001F2F80410A0E160009FE502208EE00C3483E053\r\nS3150001F3083C0500EBFF0054E301408412FF40041260\r\nS3150001F318BFFFFF1A14D08DE2F043BDE81EFF2FE1AF\r\nS3150001F328970D1200582B2000B8231200CD23120086\r\nS3150001F33806241200FFFF00001624120038241200CA\r\nS3150001F3485B2412008C241200AF241200E52412005B\r\nS3150001F35802251200212512003B2512006225120002\r\nS3150001F3680F10A0E30EFFFFEA7F10A0E30CFFFFEAF0\r\nS3150001F378F8402DE90060A0E10240A0E10350A0E1B8\r\nS3150001F3882F70A0E3000056E300005713120000DABD\r\nS3150001F398012047E2072022E20400A0E10510A0E1CE\r\nS3150001F3A8920400EB003096E5010000E2830080E15B\r\nS3150001F3B8000086E5072027E20400A0E10510A0E188\r\nS3150001F3C88A0400EB043096E5010000E2830080E13F\r\nS3150001F3D8040086E5027047E2E9FFFFEAF840BDE866\r\nS3150001F3E81EFF2FE10030A0E3003080E5043080E500\r\nS3150001F3F81EFF2FE170002DE900C090E5044090E55D\r\nS3150001F4080020A0E30030A0E31700A0E3035020E2A8\r\nS3150001F4183C65A0E13455A0E1022092E0016006E2D4\r\nS3150001F428062082E10330A3E0022092E00330A3E044\r\nS3150001F438015005E2010050E2052082E1F2FFFF2AB0\r\nS3150001F4480C0081E87000BDE81EFF2FE1003090E551\r\nS3150001F45870002DE9E8409FE500C0A0E10F0003E236\r\nS3150001F4685440A0E12352A0E1D8009FE50F5005E2E0\r\nS3150001F4785055A0E1D0609FE52304A0E10F0000E20A\r\nS3150001F4885600A0E1085005E2040000E2104004E23B\r\nS3150001F498000085E1040080E1B0509FE52346A0E124\r\nS3150001F4A80F4004E25544A0E1024004E2040080E171\r\nS3150001F4B89C509FE52348A0E10F4004E25544A0E192\r\nS3150001F4C8014004E2040080E188409FE53400A0E1A0\r\nS3150001F4D804609CE580509FE580409FE5055006E065\r\nS3150001F4E8044003E0044025E0010000E2000052E385\r\nS3150001F4F80020A00301200012000051E30410A0011E\r\nS3150001F50801108413024021E0244824E0244424E025\r\nS3150001F518244224E048209FE50F4004E25244A0E13A\r\nS3150001F528014004E2866084E1033026E0066023E0B8\r\nS3150001F538033026E004608CE500308CE57000BDE8F8\r\nS3150001F5481EFF2FE1C0220F00C0C90600B0C8030084\r\nS3150001F55858E4010038D900000AE857EC0408870086\r\nS3150001F5685CCE290096690000F0412DE90040A0E330\r\nS3150001F5780070A0E10180A0E10260A0E10450A0E1D1\r\nS3150001F5885814A0E10700A0E1011001E20620A0E15C\r\nS3150001F598ADFFFFEB100485E1014084E2080054E366\r\nS3150001F5A8FF5000E2F5FFFF1A0500A0E1F041BDE8B2\r\nS3150001F5B81EFF2FE1F8432DE90040A0E30080A0E1FA\r\nS3150001F5C80190A0E10270A0E10450A0E1186025E2D3\r\nS3150001F5D83916A0E10800A0E1011001E20720A0E127\r\nS3150001F5E899FFFFEB015085E2200055E3104684E1BF\r\nS3150001F5F8F5FFFF1A0400A0E1F843BDE81EFF2FE15D\r\nS3150001F6082024A0E1FF34C0E3FF2CC2E3FF3CC3E39F\r\nS3150001F618033482E16338A0E1011051E20600003AA1\r\nS3150001F6282328A0E1232922E0A32922E0A32A22E014\r\nS3150001F638822FA0E1A33082E1F6FFFFEA2324A0E1AD\r\nS3150001F648FF04C3E3FF2CC2E3FF0CC0E3000482E11D\r\nS3150001F6586008A0E11EFF2FE11C309FE50020A0E312\r\nS3150001F668020050E10000C3E58000A01101008013EB\r\nS3150001F678042083E50100C3E51EFF2FE1DCCA200053\r\nS3150001F68854109FE5043091E5033080E0043081E5AC\r\nS3150001F6980020D1E50130D1E5010050E20B00003A26\r\nS3150001F6A822C322E0A220A0E10C2382E1A3C1A0E1AA\r\nS3150001F6B823C12CE00CC023E0A3C32CE0A330A0E1B6\r\nS3150001F6C88C3383E1FF2002E2FF3003E2F1FFFFEA18\r\nS3150001F6D80020C1E50130C1E51EFF2FE1DCCA20008B\r\nS3150001F6E804309FE5040093E51EFF2FE1DCCA2000E4\r\nS3150001F6F830209FE50030D2E52301A0E1831DA0E17A\r\nS3150001F708020000E2A10F80E1043003E2030080E178\r\nS3150001F7180120D2E5070060E2FF0000E25200A0E105\r\nS3150001F728010000E21EFF2FE1DCCA2000F8432DE9A3\r\nS3150001F738DC409FE50180A0E10070A0E1F30300EB46\r\nS3150001F748001094E5CC309FE500C0A0E3012083E0DA\r\nS3150001F7580050E0E301C0C2E502C0C2E503C0C2E54C\r\nS3150001F7680450C2E50550C2E50650C2E507C0C2E528\r\nS3150001F778082081E2002084E50250C3E708005CE125\r\nS3150001F788130000AA001094E50C50D7E7022081E285\r\nS3150001F798022083E00860A0E3019015E20000E0E39F\r\nS3150001F7A80090A013019042150000C2150100420500\r\nS3150001F7B80090C205016056E2A550A0E1022082E24E\r\nS3150001F7C8F4FFFF1A101081E2001084E501C08CE2F3\r\nS3150001F7D8E9FFFFEA000094E50010E0E3003083E06A\r\nS3150001F7E80020A0E30110C3E50220C3E50310C3E529\r\nS3150001F7F80410C3E50510C3E50620C3E50720C3E5E4\r\nS3150001F8080820C3E5090080E2000084E5F843BDE865\r\nS3150001F8181EFF2FE1CCCA2000CCC8200004402DE5EC\r\nS3150001F8280030A0E3012083E207C002E20C40D0E7E2\r\nS3150001F83803C0D0E7ACC1A0E184C28CE1080052E361\r\nS3150001F84803C0C1E70230A011F5FFFF1A04409DE489\r\nS3150001F8581EFF2FE114359FE5F04F2DE90120A0E3A6\r\nS3150001F868002083E508359FE50040A0E3004083E5D5\r\nS3150001F87800359FE55CD04DE20060A0E1F8249FE5E4\r\nS3150001F888000093E50150A0E14410A0E3E90300EB71\r\nS3150001F8980410A0E10A20A0E340008DE2E50300EB95\r\nS3150001F8A84C008DE2D4149FE50A20A0E36D0300EB1A\r\nS3150001F8B8040056E138408DE53C408DE54C008D024B\r\nS3150001F8C80510A0010820A0036603000B4C008DE279\r\nS3150001F8D840108DE2D0FFFFEB40208DE20210A0E13F\r\nS3150001F8E849308DE20820A0E300308DE590049FE5BC\r\nS3150001F8F8023081E02AE5FFEB4CC08DE20820A0E347\r\nS3150001F90855308DE20C10A0E178449FE500308DE575\r\nS3150001F9186C049FE502308CE021E5FFEB0070A0E363\r\nS3150001F9280F30A0E34410A0E34020A0E358049FE56C\r\nS3150001F93858649FE53630CDE5BE0300EB007084E5DB\r\nS3150001F948720300EB009094E5093086E0099089E29C\r\nS3150001F9580050E0E30920A0E10610A0E130049FE58C\r\nS3150001F9680170C3E50270C3E50370C3E50450C3E53E\r\nS3150001F9780550C3E50650C3E50770C3E50850C3E55E\r\nS3150001F988009084E5370300EB40008DE20A10A0E3FE\r\nS3150001F99865FFFFEB00C094E50610A0E10C20A0E18D\r\nS3150001F9A8F0039FE52CC08DE52E0300EB4C008DE29C\r\nS3150001F9B80A10A0E35CFFFFEB00A094E50610A0E1A6\r\nS3150001F9C80A20A0E1D0039FE5260300EB38008DE26B\r\nS3150001F9D80810A0E354FFFFEB00B094E50610A0E180\r\nS3150001F9E80B20A0E1B4039FE51E0300EB0207A0E389\r\nS3150001F9F8BBE0FFEBF1DFFFEB0130A0E3CF3B05E511\r\nS3150001FA080030E0E3012CA0E3CB2B03E50420A0E3BF\r\nS3150001FA18CB2B03E5A100A0E3AEE0FFEB80439FE516\r\nS3150001FA2864339FE53C3084E56430A0E30C3084E51B\r\nS3150001FA380030A0E30030C4E568239FE50030E0E329\r\nS3150001FA48BF2203E5C33B13E5020513E3BA00000A27\r\nS3150001FA582B3AE0E3BF2F13E5010012E30020A013C0\r\nS3150001FA68DB2F0315BF3F13E5100013E3F1FFFF0A70\r\nS3150001FA782B3AE0E3DF0F13E52C339FE50F0000E295\r\nS3150001FA880FE0A0E113FF2FE1000050E3E9FFFF0AB1\r\nS3150001FA9818139FE5D82BD1E50A0052E3088094E5AF\r\nS3150001FAA83900000A0C0052E33B00000A810052E3C8\r\nS3150001FAB83E00000A880052E30700001A0030E0E31E\r\nS3150001FAC8012CA0E3CF2B03E50B60A0E10840A0E3DE\r\nS3150001FAD838508DE2C4329FE53C0000EA050052E346\r\nS3150001FAE81000001ADA0BD1E5D93BD1E500008DE506\r\nS3150001FAF8DB0BD1E504008DE5DC0BD1E508008DE5CE\r\nS3150001FB08DD0BD1E50C008DE5DE0BD1E510008DE5A9\r\nS3150001FB18DF0BD1E514008DE5E01BD1E590029FE5E9\r\nS3150001FB2818108DE5140000EA000052E30200001ADD\r\nS3150001FB38010058E30240A0012100000ADA0BD1E5D1\r\nS3150001FB48D93BD1E500008DE5DB0BD1E504008DE558\r\nS3150001FB58DC0BD1E508008DE5DD0BD1E50C008DE563\r\nS3150001FB68DE0BD1E510008DE5DF0BD1E514008DE53F\r\nS3150001FB78E01BD1E53C029FE518108DE50810A0E1D0\r\nS3150001FB881C0300EB0040A0E30D0000EA0960A0E1B8\r\nS3150001FB980140A0E336508DE20B0000EA2C609DE59A\r\nS3150001FBA80A40A0E340508DE2E8319FE5070000EAEC\r\nS3150001FBB80A60A0E10A40A0E34C508DE2D8319FE5E6\r\nS3150001FBC8020000EA0450A0E10460A0E1C0319FE50B\r\nS3150001FBD8FA0F57E3E0019F055800000A000056E3B3\r\nS3150001FBE8017087E2040000CA80319FE5003093E581\r\nS3150001FBF8000053E32D00001A4A0000EAA200A0E320\r\nS3150001FC0824308DE533E0FFEB0010A0E32B2AE0E377\r\nS3150001FC18DB1F02E528108DE568DFFFEB28109DE55F\r\nS3150001FC2824309DE50120A0E10100A0E12BCAE0E313\r\nS3150001FC38BFEF1CE510001EE3DFCF1C15FFC00C1239\r\nS3150001FC4837C0CD1537C0DD152BCAE0E3BFCF1CE59C\r\nS3150001FC5801001CE31000000A140051E3011081D2CF\r\nS3150001FC68020000DA060050E1020000BA012082E231\r\nS3150001FC7800C0A0E3040000EA000052E300C0D3E795\r\nS3150001FC880020A013010080120120A0032BEAE0E363\r\nS3150001FC98040052E3DBCF0EE5D2FFFFCA00C0E0E362\r\nS3150001FCA8C3CB1CE502051CE3DFFFFF1ACDFFFFEA04\r\nS3150001FCB80130A0E300308DE5E4309FE5C8009FE5FB\r\nS3150001FCC80810A0E10020A0E3203093E5EC609FE551\r\nS3150001FCD80FE0A0E116FF2FE1000055E30B00000A33\r\nS3150001FCE80410A0E10500A0E1BBE6FFEB0410A0E1CA\r\nS3150001FCF8D30200EB0020A0E30030A0E100208DE54F\r\nS3150001FD080500A0E10410A0E10FE0A0E116FF2FE134\r\nS3150001FD185C309FE5002093E55C309FE5030052E1E6\r\nS3150001FD289C009FC5050000CA4410A0E34020A0E33B\r\nS3150001FD3854009FE5BF0200EB30FFFFEA84009FE510\r\nS3150001FD48540200EB80009FE50710A0E1A90200EB31\r\nS3150001FD580030E0E30120A0E3CB2B03E5012CA0E36F\r\nS3150001FD68CB2B03E55CD08DE2F04FBDE81EFF2FE1FA\r\nS3150001FD7864002000142B200060002000B80B00004E\r\nS3150001FD889B0D120012E00000CCCA2000EC372000BF\r\nS3150001FD98CCC820006C482000764820002A4920005B\r\nS3150001FDA8DE4920009C2B2000010000A5901B2000A5\r\nS3150001FDB8142C2000AD261200F2261200981D1200FE\r\nS3150001FDC8140820006A141200AF1D12009D191200B2\r\nS3150001FDD8F0472DE90090A0E101A0A0E14B0200EB5C\r\nS3150001FDE8C0309FE5C0209FE5000093E50FC0E0E322\r\nS3150001FDF8001082E001C0C1E50F40A0E300C0A0E306\r\nS3150001FE0802C0C1E50340C1E5041080E2001083E5A4\r\nS3150001FE1801C0C2E70A005CE1160000AA007093E57A\r\nS3150001FE280C80D9E7016087E2111087E20650A0E14C\r\nS3150001FE380040A0E3030008E2000054E1014084E227\r\nS3150001FE480F00A0030000A013040054E30500C2E755\r\nS3150001FE58015085E2F6FFFF1A046086E2010056E1C9\r\nS3150001FE682881A0E1F0FFFF1A107087E2007083E590\r\nS3150001FE7801C08CE2E6FFFFEA000093E50010A0E36B\r\nS3150001FE88002082E00FC0E0E30110C2E50210C2E5DE\r\nS3150001FE9803C0C2E50410C2E5050080E2000083E55F\r\nS3150001FEA8F047BDE81EFF2FE1CCCA2000CCC82000D0\r\nS3150001FEB8F0402DE914D04DE20140A0E10050A0E147\r\nS3150001FEC8C2FFFFEB38319FE5A400A0E3006093E58C\r\nS3150001FED80070A0E37FDFFFEB2B3AE0E3DB7F03E56E\r\nS3150001FEE8B6DEFFEB0730A0E12B2AE0E3BF1F12E5E0\r\nS3150001FEF8010011E30010A013DB1F0215BF2F12E545\r\nS3150001FF0801308312100012E32B2AE013DF2F12159A\r\nS3150001FF1808208D15EC109FE508209D150020E0E3CB\r\nS3150001FF28090053E3BF1202E5EEFFFFDA01C0A0E3C1\r\nS3150001FF380030A0E32B2AE0E3BF2F12E5010012E30C\r\nS3150001FF480F00000AC0209FE50320D2E700005CE30A\r\nS3150001FF580F100202022281010F10C21322228111FF\r\nS3150001FF68FF20020201308302FF0052E3FE20A003B4\r\nS3150001FF782B1AE0E3060053E1DB2F01E501C02CE271\r\nS3150001FF88090000AA2B2AE0E3BF1F12E5100011E3BE\r\nS3150001FF98DF2F12150C208D1568109FE50C209D1575\r\nS3150001FFA80020E0E3BF1202E5E1FFFFEA5C309FE5CE\r\nS3150001FFB80030D3E5000053E30030E0130120A0131D\r\nS3150001FFC8CF2B031548309FE5003093E5000053E336\r\nS3150001FFD80800000A0130A0E30020A0E300308DE507\r\nS3150001FFE80500A0E10410A0E10230A0E124C09FE5CC\r\nS3150001FFF80FE0A0E11CFF2FE114D08DE2F040BDE82F\r\nS315000200081EFF2FE1CCCA2000010000A5CCC82000A3\r\nS315000200180C2B2000640020001408200073402DE9F0\r\nS315000200280060A0E1A300A0E32ADFFFEBD4209FE54E\r\nS315000200380030A0E3746082E56C3082E54030C2E5A8\r\nS315000200480340A0E10250A0E1BC109FE50020E0E3D6\r\nS31500020058BF1202E5C32B12E5020512E32500000AC8\r\nS315000200682B2AE0E3BF1F12E5010011E30010A013DB\r\nS31500020078DB1F0215BF2F12E5100012E3F1FFFF0A7C\r\nS31500020088010A54E31B0000AA2B2AE0E3000053E30B\r\nS31500020098014084E2DF0F12E50130A003E9FFFF0AFF\r\nS315000200A80F0000E264309FE50FE0A0E113FF2FE1A5\r\nS315000200B8000050E30030A001E2FFFF0A50309FE53E\r\nS315000200C8003093E5000053E38421A0E10700000A0B\r\nS315000200D80030A0E300308DE50600A0E16C1095E53E\r\nS315000200E8503095E52CC09FE50FE0A0E11CFF2FE1FB\r\nS315000200F86C0095E5000000EA0000A0E308D08DE256\r\nS315000201087040BDE81EFF2FE19C2B2000010000A5D0\r\nS31500020118201F2000640020001408200030402DE92A\r\nS315000201280A30A0E334D04DE21C30CDE50010A0E33E\r\nS315000201380C30A0E30920A0E324008DE22030CDE5AF\r\nS31500020148BC0100EB7E30E0E32430CDE550319FE57B\r\nS315000201584410A0E34C219FE5000093E548419FE542\r\nS31500020168B40100EB0030A0E3003084E50050E0E380\r\nS3150002017812DEFFEB0430A0E3CB3B05E5E000A0E38B\r\nS31500020188D4DEFFEBC800A0E3A10100EB0207A0E35F\r\nS31500020198D3DEFFEBA400A0E3CEDEFFEBC800A0E3AC\r\nS315000201A89B0100EB0130A0E3CF3B05E5002094E577\r\nS315000201B8F8309FE5030052E1020000DAF0009FE5FD\r\nS315000201C8340100EB300000EA0030E0E3C33B13E5FC\r\nS315000201D8020513E32C00000A1C008DE20110A0E3BD\r\nS315000201E832FFFFEBCC009FE58BFFFFEB000050E3ED\r\nS315000201F82100000A20008DE20110A0E32BFFFFEB8D\r\nS31500020208B0009FE584FFFFEB0A0050E31A00001ACC\r\nS315000202180820A0E39C109FE525008DE2110100EB62\r\nS3150002022824008DE20910A0E320FFFFEB84009FE57E\r\nS3150002023879FFFFEB0A0050E30F00001A78009FE5EA\r\nS31500020248EBCDD0E5E81DD0E5E92DD0E5EA3DD0E5D0\r\nS3150002025800C08DE5ECCDD0E504C08DE5EDCDD0E549\r\nS3150002026808C08DE5EECDD0E50CC08DE5EF0DD0E5E5\r\nS3150002027810008DE544009FE55E0100EB40209FE5F6\r\nS315000202880030E0E3BF2203E5C7FFFFEA0120A0E34F\r\nS315000202980030E0E3CB2B03E534D08DE23040BDE8F5\r\nS315000202A81EFF2FE160002000D80B0000142B20004F\r\nS315000202B8B80B00006A141200FC392000142C200026\r\nS315000202C83C271200010000A504402DE50030A0E3FA\r\nS315000202D8020053E10A0000AA004090E5A4C0A0E18A\r\nS315000202E8044021E0010014E30840901500C080E5AF\r\nS315000202F804C02C1000C08015A110A0E1013083E2D1\r\nS31500020308F2FFFFEA04409DE41EFF2FE1142090E568\r\nS315000203180C3090E5033002E0003080E51EFF2FE145\r\nS315000203280E0080E900309DE5103080E50030E0E3FC\r\nS315000203381311E0E1141080E5F3FFFFEA102090E5BF\r\nS31500020348003090E5140090E5032022E0000002E068\r\nS315000203581EFF2FE102B471464908490009564900B1\r\nS315000203688E4402BC7047C04602B471464908490029\r\nS31500020378095C49008E4402BC7047C04603B4714604\r\nS31500020388490840004900095A49008E4403BC70478F\r\nS31500020398012051E21EFF2F013600003A010050E10A\r\nS315000203A82200009A020011E12300000A0E0211E35C\r\nS315000203B88111A0010830A0030130A013010251E304\r\nS315000203C8000051310112A0310332A031FAFFFF3A7F\r\nS315000203D8020151E3000051318110A0318330A0316E\r\nS315000203E8FAFFFF3A0020A0E3010050E10100402095\r\nS315000203F803208221A10050E1A1004020A3208221EE\r\nS31500020408210150E12101402023218221A10150E14D\r\nS31500020418A1014020A3218221000050E32332B0111A\r\nS315000204282112A011EFFFFF1A0200A0E11EFF2FE121\r\nS315000204380100A0030000A0131EFF2FE1010851E3EB\r\nS315000204482118A0211020A0230020A033010C51E37B\r\nS315000204582114A02108208222100051E32112A02192\r\nS3150002046804208222040051E303208282A120829082\r\nS315000204783002A0E11EFF2FE1000050E30000E01366\r\nS31500020488590000EA000051E3FAFFFF0A03402DE98A\r\nS31500020498BEFFFFEB0640BDE8920003E0031041E011\r\nS315000204A81EFF2FE1000051E34300000A01C020E0CD\r\nS315000204B800106142012051E22700000A0030B0E133\r\nS315000204C800306042010053E12600009A020011E161\r\nS315000204D82800000A0E0211E38111A0010820A003D8\r\nS315000204E80120A013010251E3030051310112A03188\r\nS315000204F80222A031FAFFFF3A020151E30300513109\r\nS315000205088110A0318220A031FAFFFF3A0000A0E351\r\nS31500020518010053E10130432002008021A10053E18A\r\nS31500020528A1304320A2008021210153E12131432039\r\nS3150002053822018021A10153E1A1314320A201802198\r\nS31500020548000053E32222B0112112A011EFFFFF1A75\r\nS3150002055800005CE3000060421EFF2FE100003CE160\r\nS31500020568000060421EFF2FE10000A033CC0FA0015D\r\nS31500020578010080031EFF2FE1010851E32118A02183\r\nS315000205881020A0230020A033010C51E32114A0213E\r\nS3150002059808208222100051E32112A021042082227F\r\nS315000205A8040051E303208282A120829000005CE3CA\r\nS315000205B83302A0E1000060421EFF2FE1000050E373\r\nS315000205C80201E0C30201A0B3070000EA000051E3FA\r\nS315000205D8F9FFFF0A03402DE9B3FFFFEB0640BDE82A\r\nS315000205E8920003E0031041E01EFF2FE11EFF2FE1F8\r\nS315000205F8203052E220C062E23002A0413103A0510B\r\nS31500020608110C80413112A0E11EFF2FE1203052E287\r\nS3150002061820C062E21112A0411013A051301C814180\r\nS315000206281002A0E11EFF2FE1030051E10000E033B2\r\nS315000206380100A0831EFF2F11020050E10000E033E3\r\nS315000206480100A0830000A0031EFF2FE100000000A6\r\nS315000206587847C0467EFCFFEA7847C04621DDFFEAB6\r\nS315000206687847C0469EDDFFEA00C09FE51CFF2FE1E2\r\nS31500020678F56F11007847C0462AFAFFEA7847C0465E\r\nS3150002068822F5FFEA00C09FE51CFF2FE1274911006A\r\nS315000206987847C04633FBFFEA00C09FE51CFF2FE1FF\r\nS315000206A80549110000C09FE51CFF2FE15D4A1100B4\r\nS315000206B800C09FE51CFF2FE1456F11007847C04631\r\nS315000206C836DDFFEA7847C04678F1FFEA7847C04642\r\nS315000206D8DDF8FFEA7847C046B8DCFFEA00C09FE5C6\r\nS315000206E81CFF2FE18D7611007847C0462EE4FFEAFB\r\nS315000206F87847C04677DDFFEA7847C046F9F4FFEA4D\r\nS315000207087847C046EFF0FFEA7847C046BEFFFFEAE1\r\nS3150002071800C09FE51CFF2FE1ED48110000C09FE5D0\r\nS315000207281CFF2FE1916F11007847C0464CE9FFEA9A\r\nS315000207387847C04659DDFFEA7847C04685F4FFEA9E\r\nS315000207487847C04656FFFFEA7847C0464CFFFFEA9D\r\nS315000207587847C046B3FFFFEA7847C046DEE2FFEABB\r\nS3150002076800C09FE51CFF2FE1E16B11007847C046E8\r\nS3150002077895FFFFEA7847C04637E0FFEA7847C04662\r\nS3150002078806F5FFEA7847C046F6F1FFEA00C09FE59C\r\nS315000207981CFF2FE12570110000C09FE51CFF2FE109\r\nS315000207A85B70110000C09FE51CFF2FE1DD491100B7\r\nS315000207B87847C04697F2FFEA7847C046ADE1FFEAB6\r\nS315000207C800C09FE51CFF2FE1516C11007847C04617\r\nS315000207D8EEFEFFEA7847C04600E5FFEA00C09FE55D\r\nS315000207E81CFF2FE1156C11007847C04692F6FFEA06\r\nS315000207F87847C046C9F4FFEA00C09FE51CFF2FE10F\r\nS31500020808914911007847C04673E0FFEA7847C04627\r\nS315000208185CE8FFEA00C09FE51CFF2FE1016E1100AC\r\nS315000208287847C046C5F4FFEA7847C046CAE0FFEAF9\r\nS315000208387847C046CEE3FFEA00C09FE51CFF2FE1DA\r\nS315000208480D70110000C09FE51CFF2FE1EF6B110030\r\nS315000208587847C0469FF5FFEA7847C04663FFFFEA36\r\nS315000208687847C0462CFEFFEA00C09FE51CFF2FE131\r\nS315000208782D6C11007847C0464CEAFFEA7847C04615\r\nS31500020888B6FAFFEA000000000000000000000000BF\r\nS315000208980000000000000000000000000000000048\r\nS315000208A80000000000000000000000000000000038\r\nS315000208B80000000000000000000000000000000028\r\nS315000208C80000000000000000000000000000000018\r\nS315000208D8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF18\r\nS315000208E8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF08\r\nS315000208F8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8\r\nS31500020908FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE7\r\nS31500020918FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD7\r\nS31500020928FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC7\r\nS3150002093801000000010000000100000001000000A3\r\nS315000209480100000001000000010000000100000093\r\nS315000209580100000001000000010000000100000083\r\nS315000209680100000001000000010000000100000073\r\nS315000209780100000001000000010000000100000063\r\nS315000209880100000001000000010000000100000053\r\nS31500020998FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF57\r\nS315000209A8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF47\r\nS315000209B80100000001000000010000000100000023\r\nS315000209C80100000001000000010000000100000013\r\nS315000209D80100000001000000010000000100000003\r\nS315000209E801000000010000000100000001000000F3\r\nS315000209F8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7\r\nS31500020A08FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE6\r\nS31500020A18FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD6\r\nS31500020A28FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC6\r\nS31500020A3801000000010000000100000001000000A2\r\nS31500020A480100000001000000010000000100000092\r\nS31500020A580100000001000000010000000100000082\r\nS31500020A680100000001000000010000000100000072\r\nS31500020A78FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF76\r\nS31500020A88FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF66\r\nS31500020A980100000001000000010000000100000042\r\nS31500020AA80100000001000000010000000100000032\r\nS31500020AB80100000001000000010000000100000022\r\nS31500020AC80100000001000000010000000100000012\r\nS31500020AD80100000001000000010000000100000002\r\nS31500020AE801000000010000000100000001000000F2\r\nS31500020AF8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6\r\nS31500020B08FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE5\r\nS31500020B18FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD5\r\nS31500020B28FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC5\r\nS31500020B38FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB5\r\nS31500020B48FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA5\r\nS31500020B580000000000000001000000000000000084\r\nS31500020B680000000000000000000000000000000075\r\nS31500020B78000000010204080C0E0F303132333435FE\r\nS31500020B88363738396162636465666768696A6B6CA9\r\nS31500020B986D6E6F707172737475767778797A0012E2\r\nS31500020BA8011001020000082D2D4D50010001000020\r\nS31500020BB80109024300020100C00009040000010203\r\nS31500020BC80200000524001001042402000524060080\r\nS31500020BD8010524010001070583030800FF09040132\r\nS31500020BE800020A000000070501024000000705820C\r\nS31500020BF8024000001A03700072006F0078006D0050\r\nS31500020C08610072006B002E006F0072006700000917\r\nS31500020C180FF00FF00FF00FF000000104007F00073D\r\nS31500020C2802020400A4020C02011C00B000003810E3\r\nS31500020C38860000027C000022C1A4D0110052A6013F\r\nS31500020C48000001000101000001010001000001008D\r\nS31500020C58010100010000010100000100010100007C\r\nS31500020C68010100010000010100000100010100016B\r\nS31500020C78000001000101000001010001000001005D\r\nS31500020C88010100010000010100000100010100014B\r\nS31500020C98000001000101000001010001000001013C\r\nS31500020CA8000001000101000001010001000001002D\r\nS31500020CB8010100010000010100000100010100001C\r\nS31500020CC8010100010000010100000100010100010B\r\nS31500020CD800000100010100000101000100000101FC\r\nS31500020CE800000100010100000101000100000100ED\r\nS31500020CF801010001000001010000010001010001DB\r\nS31500020D0800000100010100000101000100000100CC\r\nS31500020D1801010001000001010000010001010000BB\r\nS31500020D2801010001000001010000010001010001AA\r\nS31500020D380000010001010000010100010000010399\r\nS31500020D483B0000009320937000000000000000E0C2\r\nS31500020D588000006000F57BFFFFFFFFFFFFFF0780B3\r\nS31500020D6869FFFFFFFFFFFFE68487F3168804004644\r\nS31500020D788E45554D70410450820DE1742038192272\r\nS31500020D880021855ED7050008397305000839730600\r\nS31500020D9800975B031FEC8AF7FF12E0000072616E90\r\nS31500020DA8206F666620656E6421006572726F722C0A\r\nS31500020DB820756E6576656E206F63746574212028CA\r\nS31500020DC8657874726120626974732129206D617372\r\nS31500020DD86B3D253032780066696E207265636F72E4\r\nS31500020DE8640050726F7445787420004572726F728F\r\nS31500020DF8200030313A6E6F74537570700030323A93\r\nS31500020E086E6F745265636F670030333A6F70744E53\r\nS31500020E186F74537570700030663A6E6F496E666FFE\r\nS31500020E280031303A646F6E744578697374003131F3\r\nS31500020E383A6C6F636B416761696E0031323A6C6F67\r\nS31500020E48636B65640031333A70726F67457272007C\r\nS31500020E5831343A6C6F636B45727200756E6B6E6FE6\r\nS31500020E68776E457272004E6F457272200043726346\r\nS31500020E784F4B004372634661696C21006F666600D8\r\nS31500020E8849736F313536393320446562756720698F\r\nS31500020E9873206E6F77202573002564206F6374654F\r\nS31500020EA8747320726561642066726F6D20494445C9\r\nS31500020EB84E5449465920726571756573743A0055E0\r\nS31500020EC84944203D20253032685825303268582555\r\nS31500020ED830326858253032685825303268582530FD\r\nS31500020EE832685825303268582530326858002564E9\r\nS31500020EF8206F637465747320726561642066726F0D\r\nS31500020F086D2053454C45435420726571756573745B\r\nS31500020F183A002564206F6374657473207265616490\r\nS31500020F282066726F6D205858582072657175657300\r\nS31500020F38743A00524541442053494E474C45204293\r\nS31500020F484C4F434B2025642072657475726E656436\r\nS31500020F58202564206F63746574733A00736E69663C\r\nS31500020F68663A206572726F722C20756E6576656EAA\r\nS31500020F78206F6374657421202864697363617264DF\r\nS31500020F882065787472612062697473212900256468\r\nS31500020F98206F637465747320726561642066726F6C\r\nS31500020FA86D2072656164657220636F6D6D616E6432\r\nS31500020FB83A20257820257820257820257820257836\r\nS31500020FC8202578202578202578202578004E6F411F\r\nS31500020FD84649205549443D2573004146493D256900\r\nS31500020FE8205549443D25730041464920427275748D\r\nS31500020FF865666F7263696E6720646F6E652E00534D\r\nS31500021008454E44005245435600627566666572202F\r\nS3150002101873616D706C65733A2025303278202530FD\r\nS315000210283278202530327820253032782025303221\r\nS3150002103878202530327820253032782025303278CB\r\nS31500021048202E2E2E0074696D6572283173293A2076\r\nS31500021058256420743D256400496E666F3A204E6FFA\r\nS315000210682076616C696420746167206465746563BF\r\nS315000210787465642E00496E666F3A2054492074617D\r\nS3150002108867206973207265777269746561626C6537\r\nS31500021098004572726F723A204964656E74206D69F2\r\nS315000210A8736D617463682100496E666F3A2054490C\r\nS315000210B820746167206964656E742069732076619D\r\nS315000210C86C696400496E666F3A20544920746167F8\r\nS315000210D820697320726561646F6E6C7900496E6669\r\nS315000210E86F3A2054616720646174613A2025782535\r\nS315000210F83038782C206372633D2578004572726F0A\r\nS31500021108723A20435243206D69736D617463682C89\r\nS3150002111820657870656374656420257800496E6673\r\nS315000211286F3A2043524320697320676F6F64004405\r\nS315000211386F6E650053746F707065640054616773EF\r\nS315000211482063616E206F6E6C792068617665203443\r\nS315000211583420626974732E005441472049443A2068\r\nS3150002116825782530387825303878202825642900CE\r\nS315000211785441472049443A20257825303878202892\r\nS3150002118825642900444F4E45210054616773206344\r\nS31500021198616E206F6E6C792068617665203834201E\r\nS315000211A8626974732E0054353578370054353535EF\r\nS315000211B83500537461727465642077726974696E56\r\nS315000211C86720257320746167202E2E2E00436C6FCC\r\nS315000211D8636B20726174653A20256400496E7661F4\r\nS315000211E86C696420636C6F636B20726174653A2064\r\nS315000211F825640054616720257320777269747465C3\r\nS315000212086E2077697468203078253038782530382A\r\nS31500021218780A004572726F722C206E6F20746167AD\r\nS31500021228206F722062616420746167004572726F72\r\nS31500021238722072656164696E6720746865207461DC\r\nS315000212486700486572652069732074686520706155\r\nS31500021258727469616C20636F6E74656E74002864BB\r\nS3150002126862672920253032782025303278202530C9\r\nS3150002127832782025303278202530327820253032CF\r\nS315000212887820253032782025303278202530327879\r\nS3150002129820253032782025303278202530327820C1\r\nS315000212A825303278202530327820253032782025AC\r\nS315000212B8303278002864626729204D617820626C92\r\nS315000212C86F636B733A202564002D2D2D2D2D2D2D40\r\nS315000212D82D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2E\r\nS315000212E82D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D1E\r\nS315000212F82D2D004D656D6F727920636F6E74656E64\r\nS31500021308743A003C6D697373696E6720626C6F6329\r\nS315000213186B2025643E00556B6E6F776E20636F6D8A\r\nS315000213286D616E643A202530327820253032780095\r\nS315000213385265616465722070617373776F72642097\r\nS3150002134869732077726F6E6700617574683A202533\r\nS315000213583032782530327825303278253032782581\r\nS315000213683032782530327825303278253032782076\r\nS315000213784661696C6564210050617373776F7264A4\r\nS31500021388206661696C65642100C00052656164204B\r\nS3150002139873756363657366756C2100556B6E6F773B\r\nS315000213A86E206672616D65206C656E6774683A2098\r\nS315000213B825640041757468656E7469636174696F42\r\nS315000213C86E206661696C6564210041757468656E94\r\nS315000213D87469636174696F6E207375636365736696\r\nS315000213E8756C2100617574683A202530327825308B\r\nS315000213F832782530327825303278253032782530E1\r\nS3150002140832782530327825303278204661696C6523\r\nS31500021418642C2072656D6F76656420656E747279C8\r\nS315000214282100617574683A20253032782530327881\r\nS3150002143825303278253032782530327825303278A0\r\nS315000214482530327825303278204F4B00537461723A\r\nS3150002145874696E672048697461673220736E6F6FAC\r\nS31500021468700054726163652066756C6C0053746112\r\nS315000214787274696E67204869746167322073696D90\r\nS31500021488756C6174696F6E004C6F6164696E672072\r\nS31500021498686974616732206D656D6F72792E2E2EBA\r\nS315000214A8007C202564207C2025303878207C005357\r\nS315000214B874617274696E672048697461672072651F\r\nS315000214C8616465722066616D696C79004C69737432\r\nS315000214D8206964656E74696669657220696E207032\r\nS315000214E8617373776F7264206D6F646500417574FA\r\nS315000214F868656E7469636174696E67207573696E6F\r\nS3150002150867206E722C617220706169723A004175A9\r\nS315000215187468656E7469636174696E672075736948\r\nS315000215286E67206B65793A0054657374696E672035\r\nS3150002153825642061757468656E7469636174696F80\r\nS315000215486E20617474656D707473004572726F7281\r\nS315000215582C20756E6B6E6F776E2066756E63746976\r\nS315000215686F6E3A20256400436F6E66696775726509\r\nS315000215786420666F722068697461675320726561B8\r\nS3150002158864657200436F6E66696775726564206684\r\nS315000215986F72206869746167312072656164657269\r\nS315000215A800436F6E6669677572656420666F72209E\r\nS315000215B86869746167322072656164657200457292\r\nS315000215C8726F722C20756E6B6E6F776E20686974F7\r\nS315000215D861672072656164657220747970653A2064\r\nS315000215E82564006672616D65207265636569766554\r\nS315000215F8643A20256400416C6C20646F6E65005461\r\nS315000216086F53656E645374756666426974206F76A5\r\nS315000216186572666C6F7765642100427566666572E7\r\nS3150002162820636C6561726564202825692062797475\r\nS3150002163865732900252D387320252A44004D6561D6\r\nS31500021648737572696E6720616E74656E6E6120636A\r\nS3150002165868617261637465726973746963732C2055\r\nS31500021668706C6561736520776169742E2E2E004D44\r\nS315000216786561737572696E6720636F6D706C6574E8\r\nS31500021688652C2073656E64696E67207265706F7269\r\nS3150002169874206261636B20746F20686F7374004DE7\r\nS315000216A86561737572696E6720484620616E746556\r\nS315000216B86E6E612C20707265737320627574746F16\r\nS315000216C86E20746F2065786974002564206D560053\r\nS315000216D863616E63656C6C65640073696D756C61D4\r\nS315000216E874652074616720286E6F77207479706537\r\nS315000216F82062697473616D706C6573290025783A86\r\nS31500021708202530327820253032782025303278204C\r\nS315000217182530327820253032782025303278202537\r\nS3150002172830327820253032780050726F782F524640\r\nS315000217384944206D61726B33205246494420696ED2\r\nS31500021748737472756D656E7400626F6F74726F6D05\r\nS315000217582076657273696F6E20696E666F726D6147\r\nS3150002176874696F6E206170706561727320696E7636\r\nS31500021778616C696400626F6F74726F6D3A20006FF4\r\nS31500021788733A20005374616E642D616C6F6E652026\r\nS315000217986D6F646521204E6F205043206E65636528\r\nS315000217A873736172792E005374617274696E67205D\r\nS315000217B87265636F7264696E67005265636F7264FD\r\nS315000217C8656420257820257820257800506C617973\r\nS315000217D8696E6700446F6E6520706C6179696E6721\r\nS315000217E80045786974696E67004C46203132352F98\r\nS315000217F831333420426173656C696E653A2025641B\r\nS315000218080048462031332E353620426173656C69AD\r\nS315000218186E653A202564005369676E616C205374BD\r\nS3150002182872656E677468204D6F6465004C46203198\r\nS3150002183832352F313334204669656C64204368613A\r\nS315000218486E67653A2025782025782025780048464F\r\nS315000218582031332E3536204669656C64204368612B\r\nS315000218686E67653A20257820257820257800257325\r\nS315000218783A2030782530347800756E6B6E6F776E45\r\nS3150002188820636F6D6D616E643A0028666D74206E12\r\nS31500021898756C6C290A00286E756C6C29004D697383\r\nS315000218A873696E672F496E76616C69642076657214\r\nS315000218B873696F6E20696E666F726D6174696F6E99\r\nS315000218C80056657273696F6E20696E666F726D6116\r\nS315000218D874696F6E206E6F7420756E6465727374A8\r\nS315000218E86F6F640056657273696F6E20696E666FF4\r\nS315000218F8726D6174696F6E206E6F742061766169AC\r\nS315000219086C61626C65002D756E636C65616E002D87\r\nS3150002191873757370656374004650474120696D613B\r\nS3150002192867653A206C656761637920696D616765E9\r\nS3150002193820776974686F75742076657273696F6E3D\r\nS3150002194820696E666F726D6174696F6E00465047E4\r\nS315000219584120696D616765206275696C7400206F44\r\nS315000219686E2000206174200030783139202D2046FF\r\nS3150002197872616D653A202530332E337800777269A5\r\nS315000219887465202D20616464723A2025782C2064BF\r\nS315000219986174613A20257800556E657870656374BE\r\nS315000219A865643A20737A3A25752C20446174613A43\r\nS315000219B82530332E33782C2053746174653A257595\r\nS315000219C82C20436F756E743A25750049563A2025C0\r\nS315000219D830332E33780052656164204E623A2025F0\r\nS315000219E8752C20416464723A202575004379636C2C\r\nS315000219F865733A2025752C204672616D65204C6503\r\nS31500021A086E6774683A2025752C2054696D653A20EC\r\nS31500021A1825750021212120637263206D69736D612A\r\nS31500021A287463683A206578706563746564202578FE\r\nS31500021A382062757420676F74202578202121210081\r\nS31500021A4873657474696E67207570206C656769635F\r\nS31500021A582063617264004D494D2032353620636138\r\nS31500021A68726420666F756E642C2072656164696E95\r\nS31500021A78672063617264202E2E2E004D494D203157\r\nS31500021A88303234206361726420666F756E642C206E\r\nS31500021A9872656164696E672063617264202E2E2EF8\r\nS31500021AA800556E6B6E6F776E206361726420666F87\r\nS31500021AB8726D61743A202578006F70657261746977\r\nS31500021AC86F6E2061626F727465640043617264208E\r\nS31500021AD8726561642C2075736520276866206C65BB\r\nS31500021AE8676963206465636F646527206F720027E0\r\nS31500021AF8646174612068657873616D706C657320C2\r\nS31500021B0825642720746F2076696577207265737558\r\nS31500021B186C7473004572726F723A2063616E206E3E\r\nS31500021B286F7420777269746520746F203078253057\r\nS31500021B38332E3378206F6E204D494D2032353600CC\r\nS31500021B484D494D20323536206361726420666F75C1\r\nS31500021B586E642C2077726974696E67203078253036\r\nS31500021B68322E3278202D2030782530322E327820C7\r\nS31500021B782E2E2E004572726F723A2063616E206EA7\r\nS31500021B886F7420777269746520746F2030782530F7\r\nS31500021B98332E3378206F6E204D494D203130323442\r\nS31500021BA8004D494D2031303234206361726420661B\r\nS31500021BB86F756E642C2077726974696E6720307847\r\nS31500021BC82530332E3378202D2030782530332E33A6\r\nS31500021BD878202E2E2E004E6F206F7220756E6B6E39\r\nS31500021BE86F776E206361726420666F756E642C204F\r\nS31500021BF861626F7274696E67006F7065726174698B\r\nS31500021C086F6E2061626F7274656420402030782599\r\nS31500021C1830332E337800777269746520737563637F\r\nS31500021C2865737366756C00693D25752C206B65793D\r\nS31500021C3820307825332E3378005374617274696EB6\r\nS31500021C4867204C6567696320656D756C61746F7290\r\nS31500021C582C20707265737320627574746F6E2074AB\r\nS31500021C686F20656E640063616E63656C6C656420E3\r\nS31500021C78627920627574746F6E00626C6577206390\r\nS31500021C88697263756C617220627566666572212077\r\nS31500021C98646174614C656E3D3078257800434F4D1A\r\nS31500021CA84D414E442046494E4953484544006D61CC\r\nS31500021CB878446174614C656E3D25782C20556172B5\r\nS31500021CC8742E73746174653D25782C20556172747F\r\nS31500021CD82E62797465436E743D2578005561727477\r\nS31500021CE82E62797465436E744D61783D25782C2091\r\nS31500021CF874726163654C656E3D25782C2055617258\r\nS31500021D08742E6F75747075745B305D3D2530387846\r\nS31500021D18004572726F723A20756E6B6F776E207419\r\nS31500021D2861677479706520282564290052656164A3\r\nS31500021D3820726571756573742066726F6D2072659F\r\nS31500021D48616465723A2025782025780041757468A1\r\nS31500021D5820617474656D7074207B6E727D7B61720E\r\nS31500021D687D3A202530387820253038780052656348\r\nS31500021D78656976656420756E6B6E6F776E20636F24\r\nS31500021D886D6D616E6420286C656E3D2564293A0086\r\nS31500021D983130303020636F6D6D616E6473206C6113\r\nS31500021DA87465722E2E2E00627574746F6E207072B0\r\nS31500021DB8657373004C6F73742073796E6320696E52\r\nS31500021DC8206379636C652025642E206E745F6469CE\r\nS31500021DD87374616E63653D25642E20436F6E736569\r\nS31500021DE863757469766520526573796E6373203DEF\r\nS31500021DF82025642E20547279696E67206F6E6520DD\r\nS31500021E0874696D652063617463682075702E2E2E61\r\nS31500021E180A004C6F73742073796E6320696E2063AF\r\nS31500021E2879636C6520256420666F72207468652064\r\nS31500021E38666F757274682074696D6520636F6E7358\r\nS31500021E48656375746976656C7920286E745F646952\r\nS31500021E587374616E6365203D202564292E204164D2\r\nS31500021E686A757374696E672073796E635F637963E3\r\nS31500021E786C657320746F2025642E0A005374617290\r\nS31500021E887465642E2037627569643D2564002D2DBC\r\nS31500021E983E20574F524B2E20616E7469636F6C3128\r\nS31500021EA82074696D653A202564002D2D3E20574F12\r\nS31500021EB8524B2E20616E7469636F6C322074696DA1\r\nS31500021EC8653A2025640041555448204641494C4507\r\nS31500021ED8442E206361726452723D253038782C2074\r\nS31500021EE8737563633D25303878004155544820435D\r\nS31500021EF84F4D504C455445442E207365633D256429\r\nS31500021F082C206B65793D25642074696D653D2564D1\r\nS31500021F18002D2D3E2048414C5445442E2053656CD5\r\nS31500021F2865637465642074696D653A202564206D5D\r\nS31500021F387300456D756C61746F722073746F70707F\r\nS31500021F4865642E2054726163696E673A202564209F\r\nS31500021F58207472616365206C656E6774683A202521\r\nS31500021F686420005278456D707479204552524F525A\r\nS31500021F782121212064617461206C656E6774683A58\r\nS31500021F882564006D6178446174614C656E3D2578FF\r\nS31500021F982C20556172742E73746174653D25782CF4\r\nS31500021FA820556172742E62797465436E743D257884\r\nS31500021FB820556172742E62797465436E744D617828\r\nS31500021FC83D25780072616E64206E6F6E6365206CC3\r\nS31500021FD8656E3A2025780061757468207569643AD9\r\nS31500021FE82025303878206E743A202530387800411A\r\nS31500021FF8757468656E7469636174696F6E2066616B\r\nS31500022008696C65642E20436172642074696D656F1C\r\nS3150002201875742E0041757468656E746963617469B6\r\nS315000220286F6E206661696C65642E204572726F72E6\r\nS31500022038206361726420726573706F6E73652E0019\r\nS31500022048436D64204572726F723A202530327800E9\r\nS31500022058436D64204572726F723A2063617264201E\r\nS3150002206874696D656F75742E206C656E3A202578D5\r\nS3150002207800436D642043524320726573706F6E731A\r\nS3150002208865206572726F722E00436D642073656EE9\r\nS3150002209864206461746132204572726F723A202537\r\nS315000220A83032780068616C74206572726F722E2005\r\nS315000220B8726573706F6E7365206C656E3A2025784B\r\nS315000220C80043616E27742073656C656374206361CF\r\nS315000220D87264005265616420626C6F636B2065727C\r\nS315000220E8726F720048616C74206572726F72005268\r\nS315000220F845414420424C4F434B2046494E4953489A\r\nS315000221084544005265616420626C6F636B2030201F\r\nS315000221186572726F72005265616420626C6F636BDE\r\nS315000221282031206572726F72005265616420626C9A\r\nS315000221386F636B2032206572726F7200526561643A\r\nS3150002214820626C6F636B2033206572726F72005265\r\nS3150002215845414420534543544F522046494E49531C\r\nS3150002216848454400577269746520626C6F636B2038\r\nS315000221786572726F7200575249544520424C4F435A\r\nS315000221884B2046494E4953484544004175746831C7\r\nS31500022198206572726F7200417574683220657272B8\r\nS315000221A86F7200723D2564206E74313D2530387891\r\nS315000221B8206E74323D253038782064697374616EF6\r\nS315000221C863653D25640064697374616E63653A20CC\r\nS315000221D86D696E3D2564206D61783D2564206176C2\r\nS315000221E8673D2564004175746832206572726F72A4\r\nS315000221F8206C656E3D256400723D2564206E74313F\r\nS315000222083D25303878206E7432656E633D25303848\r\nS3150002221878206E74327061723D25303878007661A6\r\nS315000222286C6964206D3D2564206B73313D25303819\r\nS3150002223878206E74746573743D25303878004E457F\r\nS31500022248535445442046494E49534845440044653B\r\nS31500022258627567206C6576656C3A2025640053655D\r\nS3150002226863746F725B25645D2E2041757468206500\r\nS3150002227872726F7200536563746F725B25645D2EAA\r\nS315000222882041757468206E65737465642065727280\r\nS315000222986F7200454D554C2046494C4C20534543D8\r\nS315000222A8544F52532046494E495348454400777580\r\nS315000222B8704331206572726F7200776970654320C8\r\nS315000222C86572726F72007775704332206572726F2B\r\nS315000222D87200777269746520626C6F636B2073652E\r\nS315000222E86E6420636F6D6D616E64206572726F72C3\r\nS315000222F800777269746520626C6F636B2073656E12\r\nS31500022308642064617461206572726F72007265611D\r\nS315000223186420626C6F636B2073656E6420636F6DF5\r\nS315000223286D616E64206572726F7200534E465F531A\r\nS31500022338414B006E657720636D642066726F6D206F\r\nS315000223487265616465723A206C656E3D25642C205F\r\nS31500022358636D647352656376643D2564002B2B2B8B\r\nS31500022368435243206661696C00435243207061738D\r\nS31500022378736573006D616E7920636F6D6D616E644E\r\nS3150002238873206C617465722E2E2E00627574746FDA\r\nS315000223986E20707265737365642C20726563656955\r\nS315000223A876656420256420636F6D6D616E647300C3\r\nS315000223B84E6F20726573706F6E73652066726F6DED\r\nS315000223C8207461670052616E646F6D6C792067656F\r\nS315000223D86E657261746564205549442066726F6D34\r\nS315000223E82074616720282B20322062797465204385\r\nS315000223F85243293A202578202578202578004E6FE1\r\nS31500022408772053454C454354207461673A00457812\r\nS315000224187065637465642033206279746573206617\r\nS31500022428726F6D207461672C20676F7420256400B3\r\nS31500022438435243204572726F722072656164696EF7\r\nS31500022448672073656C65637420726573706F6E734B\r\nS31500022458652E0042616420726573706F6E73652023\r\nS31500022468746F2053454C4543542066726F6D205451\r\nS3150002247861672C2061626F7274696E673A202578EB\r\nS3150002248820257800457870656374656420313020AC\r\nS3150002249862797465732066726F6D207461672C2089\r\nS315000224A8676F7420256400435243204572726F7227\r\nS315000224B82072656164696E6720626C6F636B2120A6\r\nS315000224C82D2042656C6F773A20657870656374656E\r\nS315000224D8642C20676F74202578202578005461675C\r\nS315000224E820554944202836342062697473293A20D3\r\nS315000224F825303878202530387800546167206D6594\r\nS315000225086D6F72792064756D702C20626C6F636BC7\r\nS31500022518203020746F2031350053797374656D202D\r\nS315000225286172656120626C6F636B2028307866661B\r\nS31500022538293A0045787065637465642036206279A5\r\nS315000225487465732066726F6D207461672C20676FDD\r\nS3150002255874206C6573732E2E2E0041646472657343\r\nS31500022568733D25782C20436F6E74656E74733D2512\r\nS31500022578782C204352433D257800536E6F6F70695D\r\nS315000225886E67206275666665727320696E6974691C\r\nS31500022598616C697A65643A00202054726163653A0F\r\nS315000225A8202569206279746573002020526561646A\r\nS315000225B86572202D3E207461673A2025692062796A\r\nS315000225C8746573002020746167202D3E2052656170\r\nS315000225D86465723A20256920627974657300202041\r\nS315000225E8444D413A20256920627974657300626C0C\r\nS315000225F865772063697263756C61722062756666B7\r\nS3150002260865722120626568696E6442793D30782573\r\nS315000226187800526561636865642074726163652037\r\nS315000226286C696D697400536E6F6F70207374617490\r\nS315000226386973746963733A0020204D617820626574\r\nS3150002264868696E642062793A2025690020205561FE\r\nS3150002265872742053746174653A20257800202055D7\r\nS315000226686172742042797465436E743A2025690052\r\nS315000226782020556172742042797465436E744D61E7\r\nS31500022688783A2025690020205472616365206C65BA\r\nS315000226986E6774683A2025690063616E63656C6CBF\r\nS315000226A865645F610052454144455220415554488C\r\nS315000226B820286C656E3D25303264293A2025303251\r\nS315000226C87820253032782025303278202530327825\r\nS315000226D8202530327820253032782025303278206D\r\nS315000226E825303278202530327800556E6B6E6F773A\r\nS315000226F86E20636F6D6D616E6420726563656976BF\r\nS3150002270865642066726F6D20726561646572202841\r\nS315000227186C656E3D2564293A202578202578202582\r\nS315000227287820257820257820257820257820257870\r\nS3150002273820257800202020202053656C6563746567\r\nS31500022748642043534E3A2025303278202530327899\r\nS3150002275820253032782025303278202530327820EC\r\nS3150002276825303278202530327820253032780050CC\r\nS315000227784D335601010073766E2037353600003226\r\nS315000227883031342D30332D30312032303A33343A29\r\nS3120002279834330000000000000000000000C5\r\nS315001227A5000000000100000000000000000000000B\r\nS315001227B50000000000000000024E02204D494B5257\r\nS315001227C520F04F4E0EAA4854465F4F4B5555555558\r\nS315001227D5AAAAAAAA555555550000000000000000E0\r\nS315001227E50000000000000000B80A00006C48200036\r\nS315001227F50000FBFF00C201000000080002000000F5\r\nS31500122805142C200001000000010203040400DEADB1\r\nS31500122815BEAF62DEADBEAF6208B6DD04DA170000E2\r\nS3150012282502000000014B98687047C04620FDFFFF65\r\nS31500122835074B10B51C69074B0F21186902F0A6FC48\r\nS315001228450A235843E403001910BC02BC0847C046C4\r\nS315001228554000FAFF0000FAFF08B5FFF7E9FF044B3F\r\nS315001228651968021C1A60401A08BC02BC0847C04601\r\nS315001228755C2A2000054A064B10691B690004184399\r\nS3150012288503041B0C01D11069000470478000FAFF7E\r\nS315001228950000FAFFB8239FE500C0A0E1240092E5E7\r\nS315001228A5000050E3FFCE2C0204402DE50230A0E1D4\r\nS315001228B524C08205E400000A00C22CE00000D2E51D\r\nS315001228C5000050E324C082E59200000A140092E546\r\nS315001228D5101092E58C00C0E1011081E2010070E250\r\nS315001228E50000A033010051E3101082E50400001A1E\r\nS315001228F5000050E32810C205D300000A0000A0E329\r\nS31500122905D10000EA2820D2E5010020E2FF0000E20C\r\nS31500122915000052E30020A01301200002000052E33A\r\nS315001229250220A0132820C3150200001A000050E346\r\nS315001229350520A0130020C3150010D3E50020A0E33F\r\nS31500122945011041E2102083E5040051E301F19F973E\r\nS315001229554D0000EAC8012000640220001C02200076\r\nS31500122965E4012000CC022000B220C3E12820D3E5E1\r\nS31500122975020052E3D8129FE50520A0033800001A7B\r\nS315001229851D0000EA042093E5012082E2B200D3E19C\r\nS31500122995042083E52820D3E5A000A0E1000052E338\r\nS315001229A5AC129FE5B200C3E10F00001A0020A0E3A6\r\nS315001229B50020C3E50100A0E3360000EA042093E5F2\r\nS315001229C5012082E2B200D3E1042083E52820D3E573\r\nS315001229D5A000A0E1000052E374129FE5B200C3E124\r\nS315001229E5F1FFFF0A010052E31D00000A020052E33D\r\nS315001229F52700001A010C80E3B200C1E10020C1E5EF\r\nS31500122A05230000EAB210D3E12800D3E5A110A0E114\r\nS31500122A15000050E338229FE5B210C3E10500001A03\r\nS31500122A250310A0E30010C2E5041092E5011081E23D\r\nS31500122A35041082E5170000EA010050E30510A00311\r\nS31500122A450010C2051200000A020050E3011C8103A0\r\nS31500122A55B210C201041092050110810204108205FA\r\nS31500122A650B0000EA0420A0E3E3FFFFEA2800D3E502\r\nS31500122A75000050E3D8219FE50500001A0610A0E3D1\r\nS31500122A85201082E50000C2E5020000EA0020C3E537\r\nS31500122A95202083E50000A0E30010A0E32810C3E57B\r\nS31500122AA5043093E5020053E3A4219FE50600001ABC\r\nS31500122AB5010050E16400000A083092E5010053E175\r\nS31500122AC5600000DA0100A0E35F0000EA090053E3A3\r\nS31500122AD589FFFF1A083092E52C1092E5B2C0D2E1B1\r\nS31500122AE503C0C1E7083092E5013083E2083082E57A\r\nS31500122AF5B230D2E1181092E52334A0E1013003E297\r\nS31500122B05813083E1000050E3183082E50400820526\r\nS31500122B154D00000AEAFFFFEAF0100CE24112A0E1AD\r\nS31500122B250F1031E24200000A204092E5080054E3F4\r\nS31500122B35200082154400001A0120A0E3102083E527\r\nS31500122B45082001E20300A0E3000052E3142083E506\r\nS31500122B551C0083E5042001E2142083050220A0034C\r\nS31500122B651C2083050400000A000052E31420831575\r\nS31500122B750220A0131112A0111C208315140093E52F\r\nS31500122B85000050E3C8209FE5020001E21400820509\r\nS31500122B950100A0031C0082050400000A000050E390\r\nS31500122BA5140082150100A0131110A0111C00821524\r\nS31500122BB5140093E5000050E394209FE5011001E20D\r\nS31500122BC50A00001A000051E3141082E51C0082E582\r\nS31500122BD50C00000A08001CE30A00000A0810A0E30C\r\nS31500122BE5141082E5100082E50310A0E3040000EA42\r\nS31500122BF5000051E30300000A0110A0E3141082E558\r\nS31500122C050010A0E31C1082E5142093E50222A0E130\r\nS31500122C150000A0E3142083E50120A0E30020C3E50C\r\nS31500122C252820C3E5040083E5080083E5180083E53B\r\nS31500122C35050000EA203092E5070053E32EFFFFCA8E\r\nS31500122C45013083E2203082E50100A0E104409DE4D3\r\nS31500122C551EFF2FE1AC2A200050239FE504402DE5E7\r\nS31500122C650040A0E14C0092E5000050E30230A0E1DD\r\nS31500122C750130A0034C30820548408205C900000A7E\r\nS31500122C8530C0D2E500005CE3481092E5484082E583\r\nS31500122C953C00001A5C0092E5542092E50540E0E3FB\r\nS31500122CA50240C0E7080011E30120A0E3382083E5BE\r\nS31500122CB50820A0133CC083E53C208315040011E3CC\r\nS31500122CC50400000A3C2093E5000052E30420A0E329\r\nS31500122CD53C2083E50112A011020011E30400000A4B\r\nS31500122CE53C2093E5000052E30220A0E33C2083E555\r\nS31500122CF50111A011010011E30400000A3C2093E51D\r\nS31500122D05000052E3A4229F150110A0133C10821550\r\nS31500122D153C0093E5000050E390229FE5A000000ACF\r\nS31500122D250010A0E301C0A0E3541082E530C0C2E54D\r\nS31500122D3558C0C2E5341082E5B414C2E1401082E5EA\r\nS31500122D45501082E56020D2E5010052E10020E01321\r\nS31500122D55CBCB0215040050E30700000A080050E326\r\nS31500122D650300000A020050E38D00001A0120A0E3B9\r\nS31500122D75020000EA0320A0E3000000EA0220A0E315\r\nS31500122D85502083E5860000EA3C0092E5084004E2FD\r\nS31500122D958110A0E1A41181E1001001E0500092E535\r\nS31500122DA5040080E2500082E5380092E5000050E307\r\nS31500122DB50500001A001091E20130A0E30110A013DC\r\nS31500122DC5383082E55810C2E5760000EA0020A0E305\r\nS31500122DD5020051E1382083E50C00000A5820D3E59C\r\nS31500122DE5010052E30220A0135820C3150700001A4A\r\nS31500122DF505005CE30500000A0520A0E33020C3E5C3\r\nS31500122E055C1093E5542093E55500E0E30200C1E713\r\nS31500122E153020D3E5012042E2040052E302F19F97E6\r\nS31500122E25440000EA98062000EC062000EC06200075\r\nS31500122E35B8062000A80720005810D3E56C219FE597\r\nS31500122E45010051E35C0092155410921554C0E0131B\r\nS31500122E550900001A170000EA541093E5000051E321\r\nS31500122E6548219FE51F0000CA340092E5000050E391\r\nS31500122E751C0000CA5C0092E552C0E0E301C0C0E73F\r\nS31500122E850510A0E33010C2E5300000EA5810D3E56C\r\nS31500122E95010051E314219FE50800001A341092E54A\r\nS31500122EA5011081E2341082E5B414D2E1A110A0E139\r\nS31500122EB5011C21E2B414C2E10210A0E3F0FFFFEAFD\r\nS31500122EC5020051E334109205011081023410820575\r\nS31500122ED5B414D201A110A001B414C2010410A01396\r\nS31500122EE50310A003E6FFFFEA34C093E500005CE396\r\nS31500122EF5B8209FE50B0000DAB404D2E109C06CE2F2\r\nS31500122F05500CA0E15CC092E5B404C2E10100CCE725\r\nS31500122F15541092E5011081E2541082E5401092E5B3\r\nS31500122F258110A0E1401082E50020A0E33020C3E520\r\nS31500122F350100A0E31B0000EA5C1093E5542093E51B\r\nS31500122F452200E0E30200C1E70020A0E33020C3E53A\r\nS31500122F55343093E5080053E350209FE5100000DA5C\r\nS31500122F65543092E5B404D2E15C1092E50300C1E750\r\nS31500122F75543092E5013083E2543082E5B434D2E11D\r\nS31500122F85401092E52334A0E1013003E20000A0E3EC\r\nS31500122F95813083E1403082E5340082E5B404C2E132\r\nS31500122FA5000000EA0000A0E304409DE41EFF2FE1A5\r\nS31500122FB5AC2A2000F8402DE94C419FE50150A0E1CD\r\nS31500122FC5686094E544119FE5010056E10070A0E1A1\r\nS31500122FD50000A0C34A0000CA6C1094E530C19FE5F3\r\nS31500122FE5012082E000109CE5010086E2680084E576\r\nS31500122FF56C2084E50620C1E7682094E5010082E28B\r\nS31500123005680084E56C0094E500109CE54004A0E197\r\nS315001230150200C1E7682094E5010082E2680084E5B2\r\nS3150012302500109CE5FE06D4E10200C1E7682094E58E\r\nS31500123035010082E2680084E500109CE56F00D4E584\r\nS315001230450200C1E718209DE5000052E30600001AAA\r\nS31500123055681094E500009CE5011041E20120D0E7D5\r\nS31500123065822CE0E1A22CE0E10120C0E7682094E57C\r\nS3150012307500109CE5010082E2680084E50230C1E792\r\nS31500123085682094E500109CE5010082E2680084E55B\r\nS315001230952304A0E10200C1E7682094E500109CE52F\r\nS315001230A5010082E2680084E52308A0E10200C1E777\r\nS315001230B5682094E500109CE5010082E2233CA0E11C\r\nS315001230C5680084E50230C1E7683094E500209CE586\r\nS315001230D5011083E2681084E50350C2E7683094E56F\r\nS315001230E500009CE50520A0E1030080E00710A0E1A1\r\nS315001230F5300800EB683094E5055083E0685084E5A6\r\nS315001231050100A0E3F840BDE81EFF2FE1AC2A20001E\r\nS31500123115B70B000060002000F04F2DE9B0429FE585\r\nS3150012312514D04DE20050A0E3A8629FE50090A0E1FD\r\nS315001231351D0800EB7863FCEB030019E30510A0E10B\r\nS315001231453020A0E30400A0E10070A0130170A003D3\r\nS31500123155545084E53050C4E55C6084E50F0800EBF5\r\nS31500123165403046E22C3084E52030A0E30C3084E56D\r\nS31500123175FC5BFCEB011AA0E3400086E20F5CFCEB5C\r\nS315001231850420A0E30030E0E3CB2B03E5A000A0E387\r\nS31500123195BA5CFCEB0207A0E3BB5CFCEB0580A0E185\r\nS315001231A56C5084E5405086E206B0A0E105A0A0E188\r\nS315001231B50030E0E3C32B13E5020512E318029F055F\r\nS315001231C57000000A0120A0E3CF2B03E5A52482E2B5\r\nS315001231D5BF2203E52B3AE0E3FB3E13E505606AE001\r\nS315001231E5013A63E2030056E1016A66C2036086C0CC\r\nS315001231F5036066D0016086C2080056E1070000DA50\r\nS31500123205190E56E3040000DAD0019FE50610A0E177\r\nS31500123215DA0700EB0680A0E15B0000EA0680A0E172\r\nS31500123225000056E3E1FFFFDA2B3AE0E3FB2E13E546\r\nS31500123235000052E3012AA003FFAE0305FB2E030588\r\nS315001232452B3AE0E3EB2E13E5000052E3012AA00325\r\nS31500123255EFAE0305EB2E03050030E0E30120A0E3F4\r\nS31500123265CB2B03E56C2094E50000D5E5042082E21C\r\nS315001232752002A0E10C308DE56C2084E584FDFFEB80\r\nS31500123285000050E348619FE50C309DE51000000AE9\r\nS31500123295022CA0E3000057E3CF2B03E52E00001AFC\r\nS315001232A5020019E30400000A083096E5010053E30B\r\nS315001232B50930A003043086052700000A0030A0E372\r\nS315001232C50030C4E53030C4E5012CA0E30030E0E35C\r\nS315001232D5CB2B03E50000D5E50F0000E25DFEFFEB03\r\nS315001232E5000050E31700000A012CA0E30030E0E3CA\r\nS315001232F5CF2B03E5502094E50030A0E300308DE591\r\nS31500123305D0009FE5541094E5002062E2403094E522\r\nS3150012331527FFFFEB000050E31900000A000057E3F0\r\nS315001233253020A0E3B8009FE50010A0E30170090262\r\nS315001233350170A013990700EB022CA0E30030E0E31D\r\nS315001233455CB084E5CB2B03E598309FE5015085E209\r\nS31500123355030055E1015A438294FFFFEA1C2094E5C6\r\nS315001233650170A0E300708DE57C009FE5081094E5D9\r\nS31500123375002062E2183094E50DFFFFEB000050E3E2\r\nS31500123385CDFFFF1A64009FE5810700EB0220A0E33B\r\nS315001233952B3AE0E3DF2E03E50810A0E10020D4E581\r\nS315001233A5083094E548009FE5740700EB2C3094E548\r\nS315001233B540009FE50C1094E5682094E50030D3E5AE\r\nS315001233C56E0700EB780700EB14D08DE2F04FBDE8DF\r\nS315001233D51EFF2FE1AC2A20002C3820006E1C12008D\r\nS315001233E5821C1200DC2A20006C482000EC372000D3\r\nS315001233F5A51C1200B61C1200E41C1200F74F2DE98B\r\nS3150012340598429FE598529FE50070A0E3660700EB88\r\nS31500123415C162FCEB3020A0E30710A0E10400A0E195\r\nS315001234255C5084E5547084E53070C4E55B0700EBA7\r\nS31500123435403045E22C3084E52030A0E30C3084E59B\r\nS31500123445485BFCEB011AA0E3400085E25B5BFCEBF3\r\nS315001234550420A0E30030E0E3CB2B03E5A000A0E3B4\r\nS31500123465065CFCEB0207A0E3075CFCEBE175FCEBE3\r\nS31500123475405085E20780A0E10590A0E10030E0E327\r\nS31500123485C32B13E5020512E318029F057300000A02\r\nS315001234950160A0E310229FE5067087E0410057E31D\r\nS315001234A5CF6B03E5BF2203E5080000DAFC319FE581\r\nS315001234B57D0EA0E30FE0A0E113FF2FE1000050E31C\r\nS315001234C52B3AE013DF6E03150070A0130070A001EE\r\nS315001234D52B3AE0E3FB3E13E5056069E0013A63E248\r\nS315001234E5030056E1016A66C2036086C0036066D0B0\r\nS315001234F5016086C2080056E1070000DA190E56E386\r\nS31500123505040000DAA8019FE50610A0E11B0700EBEF\r\nS315001235150680A0E1520000EA0680A0E1000056E30B\r\nS31500123525D5FFFFDA2B3AE0E3FB2E13E5000052E353\r\nS315001235350500001A012AA0E3FF9E03E574019FE523\r\nS31500123545FB2E03E50610A0E10C0700EB2B3AE0E390\r\nS31500123555EB2E13E5000052E3012AA003EF9E0305A5\r\nS315001235650060E0E3EB2E03050130A0E3CB3B06E555\r\nS315001235750000D5E52002A0E1C5FCFFEB000050E3F3\r\nS315001235851200000AC73B16E5020C13E3023CA0E340\r\nS31500123595CF3B0605CB3B06150130A0E300308DE582\r\nS315001235A514019FE5081094E5182094E5043094E576\r\nS315001235B508C19FE50FE0A0E11CFF2FE1000050E3D3\r\nS315001235C5D8609FE52400001A0000C6E53000C6E55E\r\nS315001235D50000D5E50F0000E29EFDFFEB000050E36B\r\nS315001235E51800000A0030E0E3C72B13E5020C12E3BC\r\nS315001235F5022CA0E3CF2B0305CB2B0315A0A09FE529\r\nS315001236050030A0E300308DE50A00A0E1541094E5E0\r\nS31500123615402094E5343094E5A0C09FE50FE0A0E183\r\nS315001236251CFF2FE100B050E270609FE50A00001AF8\r\nS31500123635300086E20B10A0E13020A0E3D70600EB9E\r\nS315001236455CA086E500B0C6E574309FE5015085E2BB\r\nS31500123655030055E1015A438287FFFFEA64009FE59D\r\nS31500123665CB0600EB0220A0E32B3AE0E3DF2E03E5BF\r\nS315001236757275FCEB0C3094E50020D4E500308DE52F\r\nS3150012368544009FE50810A0E1083094E5BB0600EB5F\r\nS31500123695C50600EB0CD08DE2F04FBDE81EFF2FE1FB\r\nS315001236A5AC2A20002C3820006E1C1200010000A541\r\nS315001236B518132000821C12006B1F1200EC37200013\r\nS315001236C5300F20006C482000A51C12008B1F12001B\r\nS315001236D5F3412DE90160A0E1010056E30050A0E196\r\nS315001236E50280A0E120109DE5A0439FE50400001A83\r\nS315001236F50030D0E50F0053E30030A0830C308485EB\r\nS315001237050930A0E30C2094E50B0052E302F19F97D2\r\nS31500123715D80000EAA40F2000D812200004102000B9\r\nS315001237252810200064102000B01020004C11200033\r\nS31500123735A011200004112000001220007012200092\r\nS315001237459C122000001091E20110A013010056E30D\r\nS315001237550010A013000051E3C800000A090053E344\r\nS31500123765C600001A0030D5E5260053E3520053135E\r\nS31500123775C200001A0050A0E310039FE50510A0E150\r\nS315001237850820A0E30B50C4E5840600EB00339FE541\r\nS315001237950850C4E50A50C4E50150C3E50230A0E35A\r\nS315001237A5B50000EA020056E300005103B300001A01\r\nS315001237B5DC029FE50510A0E10220A0E37D0600EBE1\r\nS315001237C50330A0E3AC0000EA020056E2006070E2A4\r\nS315001237D50060B6E0000051E30060A003000056E366\r\nS315001237E5A600000A0030D5E5930053E3A300001A9C\r\nS315001237F50130D5E5200053E30430A0039F00001ADB\r\nS315001238059D0000EA050056E3000051039B00001ACD\r\nS315001238150120D5E50030D5E5033022E00220D5E5B5\r\nS315001238250310D5E5023023E00420D5E5013023E067\r\nS31500123835030052E19100001A58029FE50510A0E116\r\nS315001238450420A0E35B0600EB0530A0E38A0000EA3C\r\nS31500123855092056E2006072E20260B6E0000051E30A\r\nS315001238650060A003000056E38400000A0030D5E587\r\nS31500123875930053E38100001A0130D5E5700053E336\r\nS315001238857E00001A10029FE50510A0E10920A0E3AB\r\nS31500123895485FFCEB000050E30830A0137600001ACF\r\nS315001238A5760000EA030056E3000051037300001A7E\r\nS315001238B5E4019FE50510A0E10320A0E33D5FFCEBC3\r\nS315001238C5000050E36D00000A0020D5E50A20C4E584\r\nS315001238D50320D4E5B4319FE5880052E30620A00300\r\nS315001238E50920A0130C2083E5640000EA050056E3BF\r\nS315001238F5000051036100001A0120D5E50030D5E517\r\nS31500123905033022E00220D5E50310D5E5023023E087\r\nS315001239150420D5E5013023E0030052E15700001AD1\r\nS3150012392568019FE50510A0E10420A0E3210600EB3E\r\nS315001239350030A0E30B30C4E50730A0E34E0000EAE1\r\nS31500123945093056E2006073E20360B6E0000051E307\r\nS315001239550060A003000056E34800000A0030D5E5D2\r\nS31500123965950053E34500001A0130D5E5700053E37F\r\nS315001239754200001A20019FE50510A0E10920A0E3E7\r\nS315001239850C5FFCEB000050E33C00000A0830A0E394\r\nS3150012399508019FE50C3084E5F80500EB370000EACF\r\nS315001239A5FC009FE50070E0E3121040E20720A0E359\r\nS315001239B51070C4E51170C4E5FE0500EBE4009FE541\r\nS315001239C50220A0E3111040E2FA0500EB0A30D4E515\r\nS315001239D51B30C4E50130A0E300308DE50E10A0E3DF\r\nS315001239E50020A0E30830A0E1BCC09FE5BC009FE51E\r\nS315001239F51C70C4E51D70C4E50FE0A0E11CFF2FE1A4\r\nS31500123A05AC309FE50FE0A0E113FF2FE1200084E51E\r\nS31500123A150130A0E300308DE50500A0E10830A0E1F4\r\nS31500123A250610A0E10020A0E37CC09FE50FE0A0E10F\r\nS31500123A351CFF2FE10B30A0E3080000EA0020A0E3EB\r\nS31500123A450830A0E100208DE50500A0E10610A0E1F1\r\nS31500123A5554C09FE50FE0A0E11CFF2FE10A30A0E359\r\nS31500123A650C3084E548309FE50FE0A0E113FF2FE106\r\nS31500123A75200084E5010000EA0030A0E30C3084E55D\r\nS31500123A850000A0E308D08DE2F041BDE81EFF2FE14C\r\nS31500123A95342B20003C2B2000372B200063630000BB\r\nS31500123AA533231200462B20004D2B2000140820002C\r\nS31500123AB5442B2000850020003C309FE5003093E51D\r\nS31500123AC5000053E310402DE90800000A2C309FE54B\r\nS31500123AD5204093E528309FE5044080E00FE0A0E101\r\nS31500123AE513FF2FE1000054E11040BD386474FC3A0F\r\nS31500123AF50000A0E31040BDE81EFF2FE1142B2000A5\r\nS31500123B05342B20008500200014339FE51820D3E5B9\r\nS31500123B15050052E302F19F97B80000EA94132000BC\r\nS31500123B25CC13200030142000841420000815200020\r\nS31500123B3564152000000050E3000060B2000051E356\r\nS31500123B45011080C0001061D0280051E3AD0000DAE3\r\nS31500123B550020A0E30110A0E3202083E51810C3E599\r\nS31500123B653C2083E5402083E5A60000EA20C093E5C4\r\nS31500123B7507005CE3A8229FE5060000CA3CC092E551\r\nS31500123B8500008CE03C0082E5400092E5011080E0E1\r\nS31500123B95401082E5400000EA64005CE30010A0C311\r\nS31500123BA51D0000CA3C2092E5000052E3402093E531\r\nS31500123BB5000060D2000052E3010080C0000061D00F\r\nS31500123BC5000050E30220A0B3330000AA090000EA60\r\nS31500123BD53C2093E5000052E3402093E5000060D2B5\r\nS31500123BE5000052E3010080C0000061D0000050E3DE\r\nS31500123BF5040000AA0320A0E31820C3E50020A0E3D1\r\nS31500123C05202083E5240000EA202093E5640052E390\r\nS31500123C15210000DA08229FE50010A0E31810C2E57C\r\nS31500123C251D0000EA3C2093E5000052E3402093E58F\r\nS31500123C35000060D2000052E3010080C0000061D08E\r\nS31500123C45000050E3110000DA201093E50B0051E352\r\nS31500123C55CC219FE5020000CA0020A0E31820C3E587\r\nS31500123C650D0000EA0010E0E3020CA0E3CF0B01E51C\r\nS31500123C750410A0E31810C2E50010A0E3201082E597\r\nS31500123C85381082E52C1082E5281082E5020000EA3A\r\nS31500123C95202093E5640052E3EEFFFFCA202093E548\r\nS31500123CA5012082E2530000EA3C2093E5000052E32C\r\nS31500123CB5402093E5000060D2000052E3010080C067\r\nS31500123CC5000061D0000050E3050000DA202093E5DC\r\nS31500123CD50A0052E348219FC50010A0C31810C2C599\r\nS31500123CE5480000EA0020A0E30110A0E31C2083E5AA\r\nS31500123CF5B023C3E1201083E5240083E50520A0E364\r\nS31500123D053F0000EA3C2093E5000052E3402093E58C\r\nS31500123D15000060D2000052E3010080C0000061D0AD\r\nS31500123D25201093E5000051E3F4209FE50110A0034E\r\nS31500123D3524008205201082053200000A241092E51D\r\nS31500123D45011080E0280092E5000051E3010080C0D1\r\nS31500123D55000061D0280082E52C0093E5010080E27F\r\nS31500123D65000051E3241082E52C0083E51C1093E52F\r\nS31500123D75B003D3E1A8209FE5A000A0E1011081E2DE\r\nS31500123D85020C80C30A0051E3B003C2E11C1083E59D\r\nS31500123D958C209FE51600001AB013D2E184009FE528\r\nS31500123DA5000001E0020C50E30800001A380092E503\r\nS31500123DB534C092E5A110A0E10010CCE7381092E5C7\r\nS31500123DC5011081E2381082E50410A0E3070000EA2B\r\nS31500123DD5000051E30010A0130400001A022CA0E300\r\nS31500123DE50030E0E3CB2B03E50100A0E31EFF2FE134\r\nS31500123DF51810C2E50020A0E3202083E5010000EAA1\r\nS31500123E050020A0E31820C3E51800D3E5000050E30F\r\nS31500123E15022CA0030030E003CB2B03050000A013F0\r\nS31500123E251EFF2FE1582B200001020000F04F2DE94D\r\nS31500123E35A4449FE51CD04DE20050A0E39C749FE577\r\nS31500123E454410A0E3012AA0E394049FE5D30400EBF2\r\nS31500123E551820A0E30510A0E10400A0E1347084E562\r\nS31500123E65385084E51850C4E5CC0400EB023B47E212\r\nS31500123E75143084E56C049FE56430A0E30C3084E5C8\r\nS31500123E85BE0400EB60049FE5011AA0E3BB0400EB38\r\nS31500123E9558049FE5021BA0E3B80400EB50049FE506\r\nS31500123EA5021BA0E3B50400EB011BA0E344049FE546\r\nS31500123EB5B20400EB0040E0E30430A0E3CB3B04E59B\r\nS31500123EC56300A0E36D59FCEB0207A0E36E59FCEB08\r\nS31500123ED5A458FCEB020B87E2011BA0E3B758FCEBD7\r\nS31500123EE50130A0E3CF3B04E508508DE5027B87E25E\r\nS31500123EF501ABA0E30540A0E12B3AE0E3FB6E13E527\r\nS31500123F050A6066E0066BA0E108309DE5266BA0E126\r\nS31500123F15030056E1080000DADC339FE5030056E19B\r\nS31500123F250400001AD4039FE50610A0E1930400EBE2\r\nS31500123F3508608DE5C90000EA08608DE5010056E3C3\r\nS31500123F45ECFFFFDAD030D7E10C308DE50130D7E53D\r\nS31500123F5510308DE5D130D7E1A4239FE514308DE5D8\r\nS31500123F65023087E2032062E0010B52E30000D7E537\r\nS31500123F75FF7F47C22B3AE0C3027047C2012BA0C38B\r\nS31500123F85FFAF8AC2EF7E03C5010000E2EB2E03C521\r\nS31500123F9502A04AD20370A0D102A08AC26F73FCEBAB\r\nS31500123FA5000050E3025085E22F00000A30639FE5B8\r\nS31500123FB54524A0E1013086E20650C4E70320C4E792\r\nS31500123FC5023086E24528A0E10320C4E7033086E2E3\r\nS31500123FD5252CA0E10320C4E70090A0E3043086E275\r\nS31500123FE50390C4E7F0829FE5053086E20390C4E7A5\r\nS31500123FF5063086E20390C4E708B098E5073086E2F4\r\nS315001240050390C4E7082086E2093084E202B0C4E7C9\r\nS31500124015030086E0011A86E20B20A0E100308DE549\r\nS31500124025640400EB00309DE50B4083E0FA0F54E380\r\nS315001240358A0000CA0910A0E11820A0E30800A0E131\r\nS31500124045560400EB013A86E2143088E5180088E238\r\nS315001240556430A0E30910A0E12C20A0E3066B86E2EA\r\nS315001240650C3088E54D0400EB346088E510309DE58B\r\nS31500124075010003E23973FCEB000050E32F00000A3E\r\nS315001240855C629FE54524A0E1013086E20650C4E74D\r\nS315001240950320C4E7023086E24528A0E10320C4E7DF\r\nS315001240A5033086E2252CA0E10320C4E70090A0E3A5\r\nS315001240B5043086E20390C4E7053086E20390C4E72E\r\nS315001240C514829FE5063086E20390C4E7073086E23E\r\nS315001240D50390C4E7083098E509C084E2082086E211\r\nS315001240E501BA86E20230C4E70C0086E00320A0E19D\r\nS315001240F50B10A0E108108DE82E0400EB08109DE8C0\r\nS3150012410503408CE0FA0F54E3540000CA0910A0E1EB\r\nS315001241151820A0E30800A0E1200400EB066B86E256\r\nS315001241256430A0E3180088E20910A0E12C20A0E370\r\nS3150012413514B088E50C3088E5180400EB346088E580\r\nS315001241450C009DE514109DE56EFEFFEB000050E395\r\nS315001241553A00000A88619FE54524A0E1013086E20E\r\nS3150012416574819FE50650C4E70320C4E7023086E250\r\nS315001241754528A0E10320C4E72C1098E5253CA0E1CB\r\nS31500124185833CE0E1A33CE0E1032086E2000051E333\r\nS315001241950230C4E704B084E20630A0E10400000A46\r\nS315001241A5280098E500608DE5A77AFCEB00309DE5C1\r\nS315001241B5280088E5281098E548219FE54104A0E1E5\r\nS315001241C50B10C6E7388098E50200C4E741C8A0E19E\r\nS315001241D5010082E204619FE500C0C4E7211CA0E14B\r\nS315001241E5020082E209B084E2032082E20010C4E7EB\r\nS315001241F50280C4E70B0083E00610A0E10820A0E1C7\r\nS3150012420508408BE0EB0300EB010A54E3C8909FE5E7\r\nS31500124215F4009FC5100000CA0030E0E30120A0E3B8\r\nS31500124225CB2B03E5012CA0E3CF2B03E5180089E27E\r\nS315001242350010A0E32C20A0E3D80300EB346089E537\r\nS31500124245C8209FE50030E0E3BF2203E5C33B13E533\r\nS31500124255020513E327FFFF1AB4009FE5CC0300EB13\r\nS315001242650030E0E30120A0E3CB2B03E5012CA0E30C\r\nS31500124275CB2B03E5022CA0E3CB2B03E50220A0E30F\r\nS315001242852B3AE0E3DF2E03E54C509FE584009FE5CC\r\nS31500124295BF0300EB08109DE57C009FE5B70300EB15\r\nS315001242A50010D5E574009FE5B40300EB081095E5FB\r\nS315001242B56C009FE5B10300EB0C1095E564009FE5D4\r\nS315001242C5AE0300EB60009FE50410A0E1AB0300EB23\r\nS315001242D51CD08DE2F04FBDE81EFF2FE1582B2000B2\r\nS315001242E514442000142C200082251200A025120049\r\nS315001242F5B2251200CC251200E6251200FF03000096\r\nS31500124305F6251200144C2000192C20001A2612002C\r\nS31500124315010000A5D81612002E26120040261200FC\r\nS315001243255426120065261200782612008E261200D1\r\nS3150012433580339FE5341093E5000051E3FF0E20020A\r\nS3150012434504402DE50320A0E134008305D600000ABA\r\nS3150012435500C0D3E5010220E000005CE3340083E5EA\r\nS315001243658000000A1C1093E5104093E58000C1E118\r\nS31500124375014084E2010070E20000A033010054E31B\r\nS31500124385104083E51900001A000050E30100000AE7\r\nS315001243950010A0E3C40000EA141093E5010051E3EE\r\nS315001243A50D00001A082093E5000052E30000C3E54C\r\nS315001243B5280083E5BC00001A3C0093E50FC0E0E334\r\nS315001243C500C0C0E5080093E5010080E2201083E5F0\r\nS315001243D5080083E50210A0E1B30000EA01005CE3E0\r\nS315001243E5EAFFFF0A0000C3E5280083E55B0000EA41\r\nS315001243F5141093E5000050E3011081E2141083E5D1\r\nS315001244050400001A383093E5000053E30000C21584\r\nS31500124415280082153810820518C092E50000A0E31F\r\nS315001244250C0051E18C329FE5100082E5D7FFFF1A89\r\nS31500124435040051E33100001A00C0D3E501005CE324\r\nS31500124445140083E50F00001A38C093E504005CE3F7\r\nS315001244550210A0030010C305011CA0030500000AE3\r\nS3150012446503005CE30000C315280083150200001A39\r\nS315001244750200A0E30000C3E5181083E50010A0E3CF\r\nS31500124485381082E5880000EA381093E5000051E3FA\r\nS315001244951D00000A011041E2B220D3E10113A0E189\r\nS315001244A5FF1001E2221121E0042093E5022082E2A7\r\nS315001244B5080052E3B210C3E1042083E5380083E510\r\nS315001244C5B2FFFF1A082093E53CC093E50210CCE72C\r\nS315001244D5082093E5012082E2DC119FE5082083E599\r\nS315001244E50220D3E50220D1E7201093E5812022E0B0\r\nS315001244F5202083E5040083E5B200C3E1170000EA34\r\nS31500124505381093E5000051E30200001A0010C3E5C6\r\nS31500124515281083E5640000EA082093E53CC093E57C\r\nS31500124525011041E2381083E50210CCE7082093E525\r\nS31500124535012082E280119FE5082083E53820D3E524\r\nS315001245450220D1E7201093E5812022E0202083E581\r\nS31500124555040083E5B200C3E1140083E5380083E560\r\nS315001245650010A0E1500000EAF01000E24112A0E1AD\r\nS315001245750F1031E24700000A284093E5080054E37C\r\nS3150012458528C083150C10A0114700001A0130A0E3AC\r\nS31500124595103082E5083001E203C0A0E3000053E3C0\r\nS315001245A51C3082E524C082E5043001E21C30820506\r\nS315001245B50230A003243082050400000A000053E3EA\r\nS315001245C51C3082150230A0131113A0112430821546\r\nS315001245D51CC092E500005CE3D8309FE502C001E2FB\r\nS315001245E51CC0830501C0A00324C083050400000A6C\r\nS315001245F500005CE31CC0831501C0A013111CA01199\r\nS3150012460524C083151CC092E500005CE3A4309FE527\r\nS31500124615011001E20A00001A000051E31C1083E59D\r\nS3150012462524C083E50C00000A080010E30A00000AFC\r\nS315001246350810A0E31C1083E510C083E50310A0E360\r\nS31500124645040000EA000051E30300000A0110A0E38A\r\nS315001246551C1083E50010A0E3241083E51C3092E5B7\r\nS315001246650332A0E11C3082E50130A0E30010A0E37D\r\nS315001246750030C2E50430A0E3041082E5081082E595\r\nS31500124685201082E5141082E5183082E5381082E58D\r\nS31500124695B210C2E1040000EA282093E5070052E3AE\r\nS315001246A53AFFFFCA012082E2282083E50100A0E134\r\nS315001246B504409DE41EFF2FE19C2B2000470C12009F\r\nS315001246C534259FE530002DE9603092E5600082E5DC\r\nS315001246D5640092E5581082E2021091E8020050E356\r\nS315001246E5010080D25C3082E558C082E50230A0E135\r\nS315001246F5640082D5250000DA4050D2E5000055E364\r\nS315001247054000001A740092E56C2092E505C0E0E3BC\r\nS3150012471502C0C0E7080011E30120A0E3482083E5A3\r\nS315001247250820A0134C5083E54C208315040011E391\r\nS315001247350400000A4C2093E5000052E30420A0E38E\r\nS315001247454C2083E50112A011020011E30400000AB0\r\nS315001247554C2093E5000052E30220A0E34C2083E5AA\r\nS315001247650111A011010011E30400000A4C2093E582\r\nS31500124775000052E380249F150110A0134C108215D8\r\nS315001247854C1093E5000051E36C249FE50100001AD5\r\nS315001247950000A0E3160100EA0000A0E301C0A0E3B1\r\nS315001247A5040051E36C0082E5440082E5B405C2E1DA\r\nS315001247B5500082E540C0C2E570C0C2E50200A00302\r\nS315001247C50500000A080051E30300A0030200000ACF\r\nS315001247D502C051E200007CE20C00B0E0680082E5FE\r\nS315001247E5582093E5020011E10300000A08249FE50B\r\nS315001247F55C2092E5020011E1E4FFFF1A0000A0E336\r\nS315001248054000C3E5FA0000EA8100A0E108C00CE207\r\nS31500124815ACC180E1680092E5040080E2680082E599\r\nS31500124825480092E54C4092E501C08CE1000050E348\r\nS3150012483504C00CE00500001A00C09CE20130A0E39A\r\nS3150012484501C0A013483082E570C0C2E5E80000EA4F\r\nS315001248550000A0E300005CE1480082E57040D2E565\r\nS315001248650400000A010054E30320A0030220A0134A\r\nS315001248757020C3E5150000EA000054E31200001A81\r\nS31500124885040055E30A20A0134020C3153300A013D4\r\nS315001248950E00001A6C3092E5741092E50F00A0E333\r\nS315001248A50300C1E76C3092E5013083E26C3082E594\r\nS315001248B548339FE5501092E50F30D3E5813023E05A\r\nS315001248C5503082E54040C2E5C80000EA0C00A0E17E\r\nS315001248D54020D3E5012042E2090052E302F19F97F7\r\nS315001248E5770000EA6C212000B8212000EC21200077\r\nS315001248F528222000282220002822200024232000F6\r\nS3150012490524232000A02220003423200070C0D3E5E2\r\nS3150012491503005CE3E0229FE50600001A02C0A0E34D\r\nS3150012492540C0C2E501C0A0E348C082E500C0A0E3CD\r\nS3150012493570C0C2E5680000EA6C0092E574C092E5A3\r\nS315001249455440E0E30040CCE70A00A0E34000C2E58C\r\nS31500124955D200A0E3600000EA70C0D3E502005CE372\r\nS3150012496594229FE503C0A0030C00000A6C0092E591\r\nS3150012497574C092E55440E0E30040CCE70A00A0E398\r\nS315001249854000C2E5D300A0E3530000EA70C0D3E5A8\r\nS3150012499502005CE360229FE50200001A04C0A0E350\r\nS315001249A540C0C2E54C0000EA6C0092E574C092E57F\r\nS315001249B55440E0E30040CCE70A00A0E34000C2E51C\r\nS315001249C5D400A0E3440000EA70C0D3E502005CE31C\r\nS315001249D524229FE50800001A44C092E501C08CE224\r\nS315001249E544C082E5B4C5D2E1ACC0A0E101CC2CE24B\r\nS315001249F5B4C5C2E105C0A0E3E8FFFFEA01005CE326\r\nS31500124A050700001A44C092E501C08CE244C082E553\r\nS31500124A15B4C5D2E1ACC0A0E1B4C5C2E106C0A0E3FB\r\nS31500124A25DEFFFFEA03005CE309C0A003DBFFFF0A12\r\nS31500124A350A00A0E34000C2E55500A0E3260000EAFD\r\nS31500124A456C0093E5000050E3AC219FE5020000CA15\r\nS31500124A5544C092E500005CE3120000DA44C093E517\r\nS31500124A6501005CE390219FE50B0000DAB415D2E153\r\nS31500124A7509C06CE2511CA0E174C092E5B415C2E1FD\r\nS31500124A850010CCE76C1092E5011081E26C1082E5FC\r\nS31500124A95501092E58110A0E1501082E50020A0E3A6\r\nS31500124AA54020C3E5510000EA74C092E55240E0E3A6\r\nS31500124AB50040CCE70A00A0E34000C2E50300A0E3EC\r\nS31500124AC5050000EA74C093E56C2093E52240E0E305\r\nS31500124AD50240CCE70020A0E34020C3E544C093E59D\r\nS31500124AE507005CE310219FE5110000DAB4C5D2E197\r\nS31500124AF56C4092E5745092E5ACC0A0E1B4C5C2E132\r\nS31500124B0504C0C5E76CC092E501C08CE2EC409FE596\r\nS31500124B156CC082E554C0D2E50CC0D4E7504092E58C\r\nS31500124B2584C02CE050C082E500C0A0E344C082E5F3\r\nS31500124B35B4C5C2E1000050E314FFFF0A6CC093E549\r\nS31500124B45744093E54420E0E30C20C4E76CC093E57A\r\nS31500124B55744093E501C08CE26CC083E50C00C4E792\r\nS31500124B656C0093E574C093E5010080E26C0083E561\r\nS31500124B750020CCE76C0093E574C093E5010080E252\r\nS31500124B856C0083E50010CCE76C1093E5740093E591\r\nS31500124B9558C093E5011081E26C1083E501C0C0E7A8\r\nS31500124BA56C1093E5740093E55CC093E5011081E200\r\nS31500124BB56C1083E501C0C0E76C1093E5740093E5AC\r\nS31500124BC54CC093E5011081E26C1083E501C0C0E784\r\nS31500124BD56C1093E5740093E5011081E26C1083E580\r\nS31500124BE50120C0E76C2093E5012082E26C2083E563\r\nS31500124BF50100A0E33000BDE81EFF2FE19C2B20002B\r\nS31500124C05470C1200F74F2DE90100A0E3D05CFCEB2F\r\nS31500124C15C15CFCEB0000A0E3BB5CFCEB28359FE511\r\nS31500124C250050A0E3005083E520359FE520459FE51A\r\nS31500124C3520659FE5000093E51C259FE54410A0E33A\r\nS31500124C45560100EB746084E56C5084E54050C4E56A\r\nS31500124C554455FCEB400086E2011AA0E35755FCEBDE\r\nS31500124C650510A0E14020A0E30400A0E14B0100EBF2\r\nS31500124C752030A0E30C3084E50420A0E30030E0E305\r\nS31500124C85406046E23C6084E5A000A0E3CB2B03E539\r\nS31500124C95FA55FCEB0207A0E3FB55FCEB04508DE538\r\nS31500124CA50570A0E105B0A0E10580A0E1806086E26D\r\nS31500124CB5019AA0E30030E0E30120A0E3CF2B03E540\r\nS31500124CC5A52482E2BF2203E52B2AE0E3FB4E12E579\r\nS31500124CD5094064E0044AA0E1244AA0E1080054E12F\r\nS31500124CE5060000DA190E54E3070000DA6C049FE594\r\nS31500124CF50410A0E1210100EB0480A0E1F60000EA10\r\nS31500124D05000054E3EAFFFF0A000000EA0480A0E16E\r\nS31500124D150120A0E3CB2B03E50630A0E10120D3E465\r\nS31500124D253C149FE5031061E0010A51E3FF6E46C28A\r\nS31500124D352B3AE0C3011AA0C30F6046C2EF6E03C534\r\nS31500124D450360A0D1EB1E03C504309DE5FF9E89C203\r\nS31500124D55013083E2019049D20F9089C20F0012E306\r\nS31500124D650110A01304308DE503306B121173271051\r\nS31500124D75302002E201A08BE201B01BE2055122E0CE\r\nS31500124D855C00001AF00005E22002A0E167FDFFEBC8\r\nS31500124D95000050E30050A0015600000AB0539FE5EB\r\nS31500124DA504309DE5240095E59C239FE5030060E00C\r\nS31500124DB500C0E0E3023CA0E3A8439FE5000082E5BC\r\nS31500124DC5CF3B0CE5001094E580339FE501E081E2C7\r\nS31500124DD500E084E500E093E50100CEE7001094E5D6\r\nS31500124DE5010081E2000084E5000092E500E093E50A\r\nS31500124DF54004A0E10100CEE7001094E5010081E22E\r\nS31500124E05000084E500E093E5F200D2E10100CEE769\r\nS31500124E15001094E500E093E50320D2E5010081E256\r\nS31500124E25000084E50120CEE7002094E5010082E228\r\nS31500124E35000084E5001093E5200095E50200C1E720\r\nS31500124E45002094E5010082E2000084E5200095E544\r\nS31500124E55001093E54004A0E10200C1E7002094E5A5\r\nS31500124E65010082E2001093E5000084E5F202D5E125\r\nS31500124E750200C1E7002094E5010082E2000084E504\r\nS31500124E85001093E52300D5E50200C1E7002094E55D\r\nS31500124E95010082E2001093E5000084E5080095E51D\r\nS31500124EA50200C1E7000093E5003094E5082095E578\r\nS31500124EB5030080E0B0129FE500C08DE5BD0000EB52\r\nS31500124EC5002094E5083095E5033082E09C229FE5A3\r\nS31500124ED5020053E1003084E500C09DE56F0000CA6B\r\nS31500124EE5013CA0E300B0C5E540B0C5E5CB3B0CE5FA\r\nS31500124EF508B085E50B50A0E103005AE35F0000DA1E\r\nS31500124F050F0007E2EDFDFFEB000050E30070A00174\r\nS31500124F155900000A38B29FE504309DE568009BE505\r\nS31500124F2524229FE5030060E00070E0E3013CA0E364\r\nS31500124F3530429FE5000082E5CF3B07E50C329FE53F\r\nS31500124F45001094E500C093E501E081E200E084E5F6\r\nS31500124F550100CCE7001094E501C081E200C084E5AA\r\nS31500124F6500C092E5000093E54CC4A0E101C0C0E77C\r\nS31500124F75001094E501C081E200C084E5000093E5C6\r\nS31500124F85F2C0D2E101C0C0E70320D2E5001094E5D4\r\nS31500124F95000093E5822CE0E101C081E2A22CE0E15A\r\nS31500124FA500C084E50120C0E7002094E5010082E2F5\r\nS31500124FB5000084E5001093E550009BE50200C1E769\r\nS31500124FC5002094E5010082E2000084E550009BE58D\r\nS31500124FD5001093E54004A0E10200C1E7002094E524\r\nS31500124FE5010082E2001093E5000084E5F205DBE19B\r\nS31500124FF50200C1E7002094E5010082E2000084E583\r\nS31500125005001093E55300DBE50200C1E7002094E5A5\r\nS31500125015010082E2001093E5000084E56C009BE531\r\nS315001250250200C1E72CA19FE5000093E5003094E547\r\nS315001250356C209BE5030080E00A10A0E15D0000EB01\r\nS31500125045002094E56C309BE5033082E01C219FE538\r\nS31500125055020053E1003084E5100000CA40008BE2DD\r\nS315001250650010A0E33820A0E34C0000EB023CA0E3BD\r\nS3150012507574A08BE5CB3B07E50070A0E307A0A0E182\r\nS315001250850030E0E3C33B13E5020513E30AB0A011B2\r\nS3150012509507FFFF1AD8009FE53D0000EB0E0000EA58\r\nS315001250A5AC409FE5CC009FE5390000EBC8009FE5B3\r\nS315001250B50810A0E10020D4E5083094E52F0000EB96\r\nS315001250C53C3094E59C209FE5AC009FE50C1094E5D9\r\nS315001250D5002092E50030D3E5280000EB0220A0E37C\r\nS315001250E52B3AE0E368409FE5DF2E03E50810A0E1C1\r\nS315001250F50020D4E5083094E57C009FE51F0000EBFF\r\nS315001251053C3094E55C209FE56C009FE50C1094E518\r\nS31500125115002092E50030D3E5180000EB0030E0E3FD\r\nS315001251250120A0E3CB2B03E5012CA0E3CB2B03E552\r\nS31500125135022CA0E3CB2B03E50420A0E3CB2B03E53E\r\nS315001251450CD08DE2F04FBDE81EFF2FE1182B200083\r\nS31500125155600020009C2B20002C382000D80B000064\r\nS31500125165F62512006C382000142B2000EC3720008F\r\nS31500125175B80B0000A1261200A51C1200FD23120071\r\nS3150012518500C09FE51CFF2FE1914911007847C046E3\r\nS315001251956876FCEA00C09FE51CFF2FE10549110060\r\nS315001251A500C09FE51CFF2FE10D70110000C09FE5A1\r\nS315001251B51CFF2FE1516C110000C09FE51CFF2FE16A\r\nS315001251C5F56F11000000000000000000000000004D\r\nS30D001251D50000000000000000BA\r\nS70500110001E8\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/obj/printf.d", "content": "obj/printf.d obj/printf.o: printf.c printf.h util.h stdint.h \\\r\n ../include/common.h ../include/at91sam7s512.h string.h\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/obj/start.d", "content": "obj/start.d obj/start.o: start.c ../include/proxmark3.h \\\r\n ../include/at91sam7s512.h ../include/config_gpio.h ../include/usb_cmd.h \\\r\n stdint.h apps.h ../include/common.h ../include/at91sam7s512.h \\\r\n ../include/hitag2.h ../include/mifare.h ../include/common.h\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/obj/string.d", "content": "obj/string.d obj/string.o: string.c string.h stdint.h\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/obj/usb_cdc.d", "content": "obj/usb_cdc.d obj/usb_cdc.o: ../common/usb_cdc.c ../common/usb_cdc.h \\\r\n ../include/common.h stdint.h ../include/at91sam7s512.h \\\r\n ../include/config_gpio.h\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/obj/util.d", "content": "obj/util.d obj/util.o: util.c ../include/proxmark3.h \\\r\n ../include/at91sam7s512.h ../include/config_gpio.h ../include/usb_cmd.h \\\r\n stdint.h util.h ../include/common.h ../include/at91sam7s512.h string.h\r\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/printf.c", "content": "/*-\n * Copyright (c) 1986, 1988, 1991, 1993\n *\tThe Regents of the University of California. All rights reserved.\n * (c) UNIX System Laboratories, Inc.\n * All or some portions of this file are derived from material licensed\n * to the University of California by American Telephone and Telegraph\n * Co. or Unix System Laboratories, Inc. and are reproduced herein with\n * the permission of UNIX System Laboratories, Inc.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * 4. Neither the name of the University nor the names of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n *\t@(#)subr_prf.c\t8.3 (Berkeley) 1/21/94\n */\n\n#include \n#include \n#include \"printf.h\"\n#include \"util.h\"\n#include \"string.h\"\n\ntypedef uint32_t uintmax_t;\ntypedef int32_t intmax_t;\n\ntypedef unsigned char u_char;\ntypedef unsigned int u_int;\ntypedef unsigned long u_long;\ntypedef unsigned short u_short;\ntypedef unsigned long long u_quad_t;\ntypedef long long quad_t;\n\ntypedef int ssize_t;\n\n#define NBBY 8 /* number of bits in a byte */\n\nchar const hex2ascii_data[] = \"0123456789abcdefghijklmnopqrstuvwxyz\";\n#define hex2ascii(hex) (hex2ascii_data[hex])\n#define toupper(c) ((c) - 0x20 * (((c) >= 'a') && ((c) <= 'z')))\n\n/* Max number conversion buffer length: a u_quad_t in base 2, plus NUL byte. */\n#define MAXNBUF\t(sizeof(intmax_t) * NBBY + 1)\n\n/*\n * Put a NUL-terminated ASCII number (base <= 36) in a buffer in reverse\n * order; return an optional length and a pointer to the last character\n * written in the buffer (i.e., the first character of the string).\n * The buffer pointed to by `nbuf' must have length >= MAXNBUF.\n */\nstatic char *\nksprintn(char *nbuf, uintmax_t num, int base, int *lenp, int upper)\n{\n\tchar *p, c;\n\n\tp = nbuf;\n\t*p = '\\0';\n\tdo {\n\t\tc = hex2ascii(num % base);\n\t\t*++p = upper ? toupper(c) : c;\n\t} while (num /= base);\n\tif (lenp)\n\t\t*lenp = p - nbuf;\n\treturn (p);\n}\n\n/*\n * Scaled down version of printf(3).\n *\n * Two additional formats:\n *\n * The format %b is supported to decode error registers.\n * Its usage is:\n *\n *\tprintf(\"reg=%b\\n\", regval, \"*\");\n *\n * where is the output base expressed as a control character, e.g.\n * \\10 gives octal; \\20 gives hex. Each arg is a sequence of characters,\n * the first of which gives the bit number to be inspected (origin 1), and\n * the next characters (up to a control character, i.e. a character <= 32),\n * give the name of the register. Thus:\n *\n *\tkvprintf(\"reg=%b\\n\", 3, \"\\10\\2BITTWO\\1BITONE\\n\");\n *\n * would produce output:\n *\n *\treg=3\n *\n * XXX: %D -- Hexdump, takes pointer and separator string:\n *\t\t(\"%6D\", ptr, \":\") -> XX:XX:XX:XX:XX:XX\n *\t\t(\"%*D\", len, ptr, \" \" -> XX XX XX XX ...\n */\nint\nkvsprintf(char const *fmt, void *arg, int radix, va_list ap)\n{\n#define PCHAR(c) {int cc=(c); *d++ = cc; retval++; }\n\tchar nbuf[MAXNBUF];\n\tchar *d;\n\tconst char *p, *percent, *q;\n\tu_char *up;\n\tint ch, n;\n\tuintmax_t num;\n\tint base, lflag, qflag, tmp, width, ladjust, sharpflag, neg, sign, dot;\n\tint cflag, hflag, jflag, tflag, zflag;\n\tint dwidth, upper;\n\tchar padc;\n\tint stop = 0, retval = 0;\n\n\tnum = 0;\n\td = (char *) arg;\n\n\tif (fmt == NULL)\n\t\tfmt = \"(fmt null)\\n\";\n\n\tif (radix < 2 || radix > 36)\n\t\tradix = 10;\n\n\tfor (;;) {\n\t\tpadc = ' ';\n\t\twidth = 0;\n\t\twhile ((ch = (u_char)*fmt++) != '%' || stop) {\n\t\t\tPCHAR(ch);\n\t\t\tif (ch == '\\0')\n\t\t\t\treturn (retval);\n\t\t}\n\t\tpercent = fmt - 1;\n\t\tqflag = 0; lflag = 0; ladjust = 0; sharpflag = 0; neg = 0;\n\t\tsign = 0; dot = 0; dwidth = 0; upper = 0;\n\t\tcflag = 0; hflag = 0; jflag = 0; tflag = 0; zflag = 0;\nreswitch:\tswitch (ch = (u_char)*fmt++) {\n\t\tcase '.':\n\t\t\tdot = 1;\n\t\t\tgoto reswitch;\n\t\tcase '#':\n\t\t\tsharpflag = 1;\n\t\t\tgoto reswitch;\n\t\tcase '+':\n\t\t\tsign = 1;\n\t\t\tgoto reswitch;\n\t\tcase '-':\n\t\t\tladjust = 1;\n\t\t\tgoto reswitch;\n\t\tcase '%':\n\t\t\tPCHAR(ch);\n\t\t\tbreak;\n\t\tcase '*':\n\t\t\tif (!dot) {\n\t\t\t\twidth = va_arg(ap, int);\n\t\t\t\tif (width < 0) {\n\t\t\t\t\tladjust = !ladjust;\n\t\t\t\t\twidth = -width;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tdwidth = va_arg(ap, int);\n\t\t\t}\n\t\t\tgoto reswitch;\n\t\tcase '0':\n\t\t\tif (!dot) {\n\t\t\t\tpadc = '0';\n\t\t\t\tgoto reswitch;\n\t\t\t}\n\t\tcase '1': case '2': case '3': case '4':\n\t\tcase '5': case '6': case '7': case '8': case '9':\n\t\t\t\tfor (n = 0;; ++fmt) {\n\t\t\t\t\tn = n * 10 + ch - '0';\n\t\t\t\t\tch = *fmt;\n\t\t\t\t\tif (ch < '0' || ch > '9')\n\t\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\tif (dot)\n\t\t\t\tdwidth = n;\n\t\t\telse\n\t\t\t\twidth = n;\n\t\t\tgoto reswitch;\n\t\tcase 'b':\n\t\t\tnum = (u_int)va_arg(ap, int);\n\t\t\tp = va_arg(ap, char *);\n\t\t\tfor (q = ksprintn(nbuf, num, *p++, NULL, 0); *q;)\n\t\t\t\tPCHAR(*q--);\n\n\t\t\tif (num == 0)\n\t\t\t\tbreak;\n\n\t\t\tfor (tmp = 0; *p;) {\n\t\t\t\tn = *p++;\n\t\t\t\tif (num & (1 << (n - 1))) {\n\t\t\t\t\tPCHAR(tmp ? ',' : '<');\n\t\t\t\t\tfor (; (n = *p) > ' '; ++p)\n\t\t\t\t\t\tPCHAR(n);\n\t\t\t\t\ttmp = 1;\n\t\t\t\t} else\n\t\t\t\t\tfor (; *p > ' '; ++p)\n\t\t\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tif (tmp)\n\t\t\t\tPCHAR('>');\n\t\t\tbreak;\n\t\tcase 'c':\n\t\t\tPCHAR(va_arg(ap, int));\n\t\t\tbreak;\n\t\tcase 'D':\n\t\t\tup = va_arg(ap, u_char *);\n\t\t\tp = va_arg(ap, char *);\n\t\t\tif (!width)\n\t\t\t\twidth = 16;\n\t\t\twhile(width--) {\n\t\t\t\tPCHAR(hex2ascii(*up >> 4));\n\t\t\t\tPCHAR(hex2ascii(*up & 0x0f));\n\t\t\t\tup++;\n\t\t\t\tif (width)\n\t\t\t\t\tfor (q=p;*q;q++)\n\t\t\t\t\t\tPCHAR(*q);\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 'd':\n\t\tcase 'i':\n\t\t\tbase = 10;\n\t\t\tsign = 1;\n\t\t\tgoto handle_sign;\n\t\tcase 'h':\n\t\t\tif (hflag) {\n\t\t\t\thflag = 0;\n\t\t\t\tcflag = 1;\n\t\t\t} else\n\t\t\t\thflag = 1;\n\t\t\tgoto reswitch;\n\t\tcase 'j':\n\t\t\tjflag = 1;\n\t\t\tgoto reswitch;\n\t\tcase 'l':\n\t\t\tif (lflag) {\n\t\t\t\tlflag = 0;\n\t\t\t\tqflag = 1;\n\t\t\t} else\n\t\t\t\tlflag = 1;\n\t\t\tgoto reswitch;\n\t\tcase 'n':\n\t\t\tif (jflag)\n\t\t\t\t*(va_arg(ap, intmax_t *)) = retval;\n\t\t\telse if (qflag)\n\t\t\t\t*(va_arg(ap, quad_t *)) = retval;\n\t\t\telse if (lflag)\n\t\t\t\t*(va_arg(ap, long *)) = retval;\n\t\t\telse if (zflag)\n\t\t\t\t*(va_arg(ap, size_t *)) = retval;\n\t\t\telse if (hflag)\n\t\t\t\t*(va_arg(ap, short *)) = retval;\n\t\t\telse if (cflag)\n\t\t\t\t*(va_arg(ap, char *)) = retval;\n\t\t\telse\n\t\t\t\t*(va_arg(ap, int *)) = retval;\n\t\t\tbreak;\n\t\tcase 'o':\n\t\t\tbase = 8;\n\t\t\tgoto handle_nosign;\n\t\tcase 'p':\n\t\t\tbase = 16;\n\t\t\tsharpflag = (width == 0);\n\t\t\tsign = 0;\n\t\t\tnum = (uintptr_t)va_arg(ap, void *);\n\t\t\tgoto number;\n\t\tcase 'q':\n\t\t\tqflag = 1;\n\t\t\tgoto reswitch;\n\t\tcase 'r':\n\t\t\tbase = radix;\n\t\t\tif (sign)\n\t\t\t\tgoto handle_sign;\n\t\t\tgoto handle_nosign;\n\t\tcase 's':\n\t\t\tp = va_arg(ap, char *);\n\t\t\tif (p == NULL)\n\t\t\t\tp = \"(null)\";\n\t\t\tif (!dot)\n\t\t\t\tn = strlen (p);\n\t\t\telse\n\t\t\t\tfor (n = 0; n < dwidth && p[n]; n++)\n\t\t\t\t\tcontinue;\n\n\t\t\twidth -= n;\n\n\t\t\tif (!ladjust && width > 0)\n\t\t\t\twhile (width--)\n\t\t\t\t\tPCHAR(padc);\n\t\t\twhile (n--)\n\t\t\t\tPCHAR(*p++);\n\t\t\tif (ladjust && width > 0)\n\t\t\t\twhile (width--)\n\t\t\t\t\tPCHAR(padc);\n\t\t\tbreak;\n\t\tcase 't':\n\t\t\ttflag = 1;\n\t\t\tgoto reswitch;\n\t\tcase 'u':\n\t\t\tbase = 10;\n\t\t\tgoto handle_nosign;\n\t\tcase 'X':\n\t\t\tupper = 1;\n\t\tcase 'x':\n\t\t\tbase = 16;\n\t\t\tgoto handle_nosign;\n\t\tcase 'y':\n\t\t\tbase = 16;\n\t\t\tsign = 1;\n\t\t\tgoto handle_sign;\n\t\tcase 'z':\n\t\t\tzflag = 1;\n\t\t\tgoto reswitch;\nhandle_nosign:\n\t\t\tsign = 0;\n\t\t\tif (jflag)\n\t\t\t\tnum = va_arg(ap, uintmax_t);\n\t\t\telse if (qflag)\n\t\t\t\tnum = va_arg(ap, u_quad_t);\n\t\t\telse if (tflag)\n\t\t\t\tnum = va_arg(ap, ptrdiff_t);\n\t\t\telse if (lflag)\n\t\t\t\tnum = va_arg(ap, u_long);\n\t\t\telse if (zflag)\n\t\t\t\tnum = va_arg(ap, size_t);\n\t\t\telse if (hflag)\n\t\t\t\tnum = (u_short)va_arg(ap, int);\n\t\t\telse if (cflag)\n\t\t\t\tnum = (u_char)va_arg(ap, int);\n\t\t\telse\n\t\t\t\tnum = va_arg(ap, u_int);\n\t\t\tgoto number;\nhandle_sign:\n\t\t\tif (jflag)\n\t\t\t\tnum = va_arg(ap, intmax_t);\n\t\t\telse if (qflag)\n\t\t\t\tnum = va_arg(ap, quad_t);\n\t\t\telse if (tflag)\n\t\t\t\tnum = va_arg(ap, ptrdiff_t);\n\t\t\telse if (lflag)\n\t\t\t\tnum = va_arg(ap, long);\n\t\t\telse if (zflag)\n\t\t\t\tnum = va_arg(ap, ssize_t);\n\t\t\telse if (hflag)\n\t\t\t\tnum = (short)va_arg(ap, int);\n\t\t\telse if (cflag)\n\t\t\t\tnum = (char)va_arg(ap, int);\n\t\t\telse\n\t\t\t\tnum = va_arg(ap, int);\nnumber:\n\t\t\tif (sign && (intmax_t)num < 0) {\n\t\t\t\tneg = 1;\n\t\t\t\tnum = -(intmax_t)num;\n\t\t\t}\n\t\t\tp = ksprintn(nbuf, num, base, &tmp, upper);\n\t\t\tif (sharpflag && num != 0) {\n\t\t\t\tif (base == 8)\n\t\t\t\t\ttmp++;\n\t\t\t\telse if (base == 16)\n\t\t\t\t\ttmp += 2;\n\t\t\t}\n\t\t\tif (neg)\n\t\t\t\ttmp++;\n\n\t\t\tif (!ladjust && padc != '0' && width\n\t\t\t && (width -= tmp) > 0)\n\t\t\t\twhile (width--)\n\t\t\t\t\tPCHAR(padc);\n\t\t\tif (neg)\n\t\t\t\tPCHAR('-');\n\t\t\tif (sharpflag && num != 0) {\n\t\t\t\tif (base == 8) {\n\t\t\t\t\tPCHAR('0');\n\t\t\t\t} else if (base == 16) {\n\t\t\t\t\tPCHAR('0');\n\t\t\t\t\tPCHAR('x');\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (!ladjust && width && (width -= tmp) > 0)\n\t\t\t\twhile (width--)\n\t\t\t\t\tPCHAR(padc);\n\n\t\t\twhile (*p)\n\t\t\t\tPCHAR(*p--);\n\n\t\t\tif (ladjust && width && (width -= tmp) > 0)\n\t\t\t\twhile (width--)\n\t\t\t\t\tPCHAR(padc);\n\n\t\t\tbreak;\n\t\tdefault:\n\t\t\twhile (percent < fmt)\n\t\t\t\tPCHAR(*percent++);\n\t\t\t/*\n\t\t\t * Since we ignore an formatting argument it is no\n\t\t\t * longer safe to obey the remaining formatting\n\t\t\t * arguments as the arguments will no longer match\n\t\t\t * the format specs.\n\t\t\t */\n\t\t\tstop = 1;\n\t\t\tbreak;\n\t\t}\n\t}\n\tPCHAR(0);\n\treturn retval;\n#undef PCHAR\n}\n\nint vsprintf(char *dest, const char *fmt, va_list ap)\n{\n\treturn kvsprintf(fmt, dest, 10, ap);\n}\n\nint\nsprintf(char *dest, const char *fmt, ...)\n{\n\t/* http://www.pagetable.com/?p=298 */\n\tint retval;\n\tva_list ap;\n\n\tva_start(ap, fmt);\n\tretval = kvsprintf(fmt, dest, 10, ap);\n\tva_end(ap);\n\treturn retval;\n}\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/printf.h", "content": "//-----------------------------------------------------------------------------\n// Copyright (C) 2010 Hector Martin \"marcan\" \n//\n// This code is licensed to you under the terms of the GNU GPL, version 2 or,\n// at your option, any later version. See the LICENSE.txt file for the text of\n// the license.\n//-----------------------------------------------------------------------------\n// Common *printf() functions\n//-----------------------------------------------------------------------------\n\n#ifndef __PRINTF_H\n#define __PRINTF_H\n\n#include \n\nint kvsprintf(const char *format, void *arg, int radix, va_list ap) __attribute__ ((format (printf, 1, 0)));\nint vsprintf(char *str, const char *format, va_list ap) __attribute__ ((format (printf, 2, 0)));\nint sprintf(char *str, const char *format, ...) __attribute__ ((format (printf, 2, 3)));\n\n#endif\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/start.c", "content": "//-----------------------------------------------------------------------------\n// Jonathan Westhues, Mar 2006\n//\n// This code is licensed to you under the terms of the GNU GPL, version 2 or,\n// at your option, any later version. See the LICENSE.txt file for the text of\n// the license.\n//-----------------------------------------------------------------------------\n// Just vector to AppMain(). This is in its own file so that I can place it\n// with the linker script.\n//-----------------------------------------------------------------------------\n\n#include \"proxmark3.h\"\n#include \"apps.h\"\n\nextern char __data_start__, __data_src_start__, __data_end__, __bss_start__, __bss_end__;\nvoid __attribute__((section(\".startos\"))) Vector(void)\n{\n\t/* Stack should have been set up by the bootloader */\n\tchar *src, *dst, *end;\n\n\t/* Set up (that is: clear) BSS. */\n\tdst = &__bss_start__;\n\tend = &__bss_end__;\n\twhile(dst < end) *dst++ = 0;\n\n\t/* Set up data segment: Copy from flash to ram */\n\tsrc = &__data_src_start__;\n\tdst = &__data_start__;\n\tend = &__data_end__;\n\twhile(dst < end) *dst++ = *src++;\n\n\tAppMain();\n}\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/stdint.h", "content": "//-----------------------------------------------------------------------------\n// Copyright (C) 2010 Hector Martin \"marcan\" \n//\n// This code is licensed to you under the terms of the GNU GPL, version 2 or,\n// at your option, any later version. See the LICENSE.txt file for the text of\n// the license.\n//-----------------------------------------------------------------------------\n// Replacement stdint.h because GCC doesn't come with it yet (C99)\n//-----------------------------------------------------------------------------\n\n#ifndef __STDINT_H\n#define __STDINT_H\n\ntypedef signed char\t\t\t\tint8_t;\ntypedef short int\t\t\t\tint16_t;\ntypedef int\t\t\t\t\t\tint32_t;\ntypedef long long int\t\t\tint64_t;\n\ntypedef unsigned char\t\t\tuint8_t;\ntypedef unsigned short int\t\tuint16_t;\ntypedef unsigned int\t\t\tuint32_t;\ntypedef unsigned long long int\tuint64_t;\n\ntypedef int\t\t\t\t\t\tintptr_t;\ntypedef unsigned int\t\t\tuintptr_t;\n\n#endif /* __STDINT_H */\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/string.c", "content": "//-----------------------------------------------------------------------------\n// Jonathan Westhues, Sept 2005\n//\n// This code is licensed to you under the terms of the GNU GPL, version 2 or,\n// at your option, any later version. See the LICENSE.txt file for the text of\n// the license.\n//-----------------------------------------------------------------------------\n// Common string.h functions\n//-----------------------------------------------------------------------------\n\n#include \"string.h\"\n#include \n\nvoid *memcpy(void *dest, const void *src, int len)\n{\n\tuint8_t *d = dest;\n\tconst uint8_t *s = src;\n\twhile((len--) > 0) {\n\t\t*d = *s;\n\t\td++;\n\t\ts++;\n\t}\n\treturn dest;\n}\n\nvoid *memset(void *dest, int c, int len)\n{\n\tuint8_t *d = dest;\n\twhile((len--) > 0) {\n\t\t*d = c;\n\t\td++;\n\t}\n\treturn dest;\n}\n\nint memcmp(const void *av, const void *bv, int len)\n{\n\tconst uint8_t *a = av;\n\tconst uint8_t *b = bv;\n\n\twhile((len--) > 0) {\n\t\tif(*a != *b) {\n\t\t\treturn *a - *b;\n\t\t}\n\t\ta++;\n\t\tb++;\n\t}\n\treturn 0;\n}\n\nint strlen(const char *str)\n{\n\tint l = 0;\n\twhile(*str) {\n\t\tl++;\n\t\tstr++;\n\t}\n\treturn l;\n}\n\nchar* strncat(char *dest, const char *src, unsigned int n)\n{\n\tunsigned int dest_len = strlen(dest);\n\tunsigned int i;\n\n\tfor (i = 0 ; i < n && src[i] != '\\0' ; i++)\n\t\tdest[dest_len + i] = src[i];\n\tdest[dest_len + i] = '\\0';\n\n\treturn dest;\n}\n\nchar* strcat(char *dest, const char *src)\n{\n\tunsigned int dest_len = strlen(dest);\n\tunsigned int i;\n\n\tfor (i = 0 ; src[i] != '\\0' ; i++)\n\t\tdest[dest_len + i] = src[i];\n\tdest[dest_len + i] = '\\0';\n\n\treturn dest;\n}\n////////////////////////////////////////// code to do 'itoa'\n\n/* reverse: reverse string s in place */\nvoid strreverse(char s[])\n{\n int c, i, j;\n\n for (i = 0, j = strlen(s)-1; i 0); /* delete it */\n if (sign < 0)\n s[i++] = '-';\n s[i] = '\\0';\n strreverse(s);\n}\n\n//////////////////////////////////////// END 'itoa' CODE\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/string.h", "content": "//-----------------------------------------------------------------------------\n// Jonathan Westhues, Aug 2005\n// Copyright (C) 2010 Hector Martin \"marcan\" \n//\n// This code is licensed to you under the terms of the GNU GPL, version 2 or,\n// at your option, any later version. See the LICENSE.txt file for the text of\n// the license.\n//-----------------------------------------------------------------------------\n// Common string.h functions\n//-----------------------------------------------------------------------------\n\n#ifndef __STRING_H\n#define __STRING_H\n\nint strlen(const char *str);\nvoid *memcpy(void *dest, const void *src, int len);\nvoid *memset(void *dest, int c, int len);\nint memcmp(const void *av, const void *bv, int len);\nchar *strncat(char *dest, const char *src, unsigned int n);\nchar *strcat(char *dest, const char *src);\nvoid strreverse(char s[]);\nvoid itoa(int n, char s[]);\n\n\n#endif /* __STRING_H */\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/util.c", "content": "//-----------------------------------------------------------------------------\n// Jonathan Westhues, Sept 2005\n//\n// This code is licensed to you under the terms of the GNU GPL, version 2 or,\n// at your option, any later version. See the LICENSE.txt file for the text of\n// the license.\n//-----------------------------------------------------------------------------\n// Utility functions used in many places, not specific to any piece of code.\n//-----------------------------------------------------------------------------\n\n#include \"proxmark3.h\"\n#include \"util.h\"\n#include \"string.h\"\n\nsize_t nbytes(size_t nbits) {\n\treturn (nbits/8)+((nbits%8)>0);\n}\n\nuint32_t SwapBits(uint32_t value, int nrbits) {\n\tint i;\n\tuint32_t newvalue = 0;\n\tfor(i = 0; i < nrbits; i++) {\n\t\tnewvalue ^= ((value >> i) & 1) << (nrbits - 1 - i);\n\t}\n\treturn newvalue;\n}\n\nvoid num_to_bytes(uint64_t n, size_t len, uint8_t* dest)\n{\n\twhile (len--) {\n\t\tdest[len] = (uint8_t) n;\n\t\tn >>= 8;\n\t}\n}\n\nuint64_t bytes_to_num(uint8_t* src, size_t len)\n{\n\tuint64_t num = 0;\n\twhile (len--)\n\t{\n\t\tnum = (num << 8) | (*src);\n\t\tsrc++;\n\t}\n\treturn num;\n}\n\nvoid LEDsoff()\n{\n\tLED_A_OFF();\n\tLED_B_OFF();\n\tLED_C_OFF();\n\tLED_D_OFF();\n}\n\n// LEDs: R(C) O(A) G(B) -- R(D) [1, 2, 4 and 8]\nvoid LED(int led, int ms)\n{\n\tif (led & LED_RED)\n\t\tLED_C_ON();\n\tif (led & LED_ORANGE)\n\t\tLED_A_ON();\n\tif (led & LED_GREEN)\n\t\tLED_B_ON();\n\tif (led & LED_RED2)\n\t\tLED_D_ON();\n\n\tif (!ms)\n\t\treturn;\n\n\tSpinDelay(ms);\n\n\tif (led & LED_RED)\n\t\tLED_C_OFF();\n\tif (led & LED_ORANGE)\n\t\tLED_A_OFF();\n\tif (led & LED_GREEN)\n\t\tLED_B_OFF();\n\tif (led & LED_RED2)\n\t\tLED_D_OFF();\n}\n\n\n// Determine if a button is double clicked, single clicked,\n// not clicked, or held down (for ms || 1sec)\n// In general, don't use this function unless you expect a\n// double click, otherwise it will waste 500ms -- use BUTTON_HELD instead\nint BUTTON_CLICKED(int ms)\n{\n\t// Up to 500ms in between clicks to mean a double click\n\tint ticks = (48000 * (ms ? ms : 1000)) >> 10;\n\n\t// If we're not even pressed, forget about it!\n\tif (!BUTTON_PRESS())\n\t\treturn BUTTON_NO_CLICK;\n\n\t// Borrow a PWM unit for my real-time clock\n\tAT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);\n\t// 48 MHz / 1024 gives 46.875 kHz\n\tAT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);\n\tAT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;\n\tAT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;\n\n\tuint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;\n\n\tint letoff = 0;\n\tfor(;;)\n\t{\n\t\tuint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;\n\n\t\t// We haven't let off the button yet\n\t\tif (!letoff)\n\t\t{\n\t\t\t// We just let it off!\n\t\t\tif (!BUTTON_PRESS())\n\t\t\t{\n\t\t\t\tletoff = 1;\n\n\t\t\t\t// reset our timer for 500ms\n\t\t\t\tstart = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;\n\t\t\t\tticks = (48000 * (500)) >> 10;\n\t\t\t}\n\n\t\t\t// Still haven't let it off\n\t\t\telse\n\t\t\t\t// Have we held down a full second?\n\t\t\t\tif (now == (uint16_t)(start + ticks))\n\t\t\t\t\treturn BUTTON_HOLD;\n\t\t}\n\n\t\t// We already let off, did we click again?\n\t\telse\n\t\t\t// Sweet, double click!\n\t\t\tif (BUTTON_PRESS())\n\t\t\t\treturn BUTTON_DOUBLE_CLICK;\n\n\t\t\t// Have we ran out of time to double click?\n\t\t\telse\n\t\t\t\tif (now == (uint16_t)(start + ticks))\n\t\t\t\t\t// At least we did a single click\n\t\t\t\t\treturn BUTTON_SINGLE_CLICK;\n\n\t\tWDT_HIT();\n\t}\n\n\t// We should never get here\n\treturn BUTTON_ERROR;\n}\n\n// Determine if a button is held down\nint BUTTON_HELD(int ms)\n{\n\t// If button is held for one second\n\tint ticks = (48000 * (ms ? ms : 1000)) >> 10;\n\n\t// If we're not even pressed, forget about it!\n\tif (!BUTTON_PRESS())\n\t\treturn BUTTON_NO_CLICK;\n\n\t// Borrow a PWM unit for my real-time clock\n\tAT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);\n\t// 48 MHz / 1024 gives 46.875 kHz\n\tAT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);\n\tAT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;\n\tAT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;\n\n\tuint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;\n\n\tfor(;;)\n\t{\n\t\tuint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;\n\n\t\t// As soon as our button let go, we didn't hold long enough\n\t\tif (!BUTTON_PRESS())\n\t\t\treturn BUTTON_SINGLE_CLICK;\n\n\t\t// Have we waited the full second?\n\t\telse\n\t\t\tif (now == (uint16_t)(start + ticks))\n\t\t\t\treturn BUTTON_HOLD;\n\n\t\tWDT_HIT();\n\t}\n\n\t// We should never get here\n\treturn BUTTON_ERROR;\n}\n\n// attempt at high resolution microsecond timer\n// beware: timer counts in 21.3uS increments (1024/48Mhz)\nvoid SpinDelayUs(int us)\n{\n\tint ticks = (48*us) >> 10;\n\n\t// Borrow a PWM unit for my real-time clock\n\tAT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);\n\t// 48 MHz / 1024 gives 46.875 kHz\n\tAT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);\n\tAT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;\n\tAT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;\n\n\tuint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;\n\n\tfor(;;) {\n\t\tuint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;\n\t\tif (now == (uint16_t)(start + ticks))\n\t\t\treturn;\n\n\t\tWDT_HIT();\n\t}\n}\n\nvoid SpinDelay(int ms)\n{\n // convert to uS and call microsecond delay function\n\tSpinDelayUs(ms*1000);\n}\n\n/* Similar to FpgaGatherVersion this formats stored version information\n * into a string representation. It takes a pointer to the struct version_information,\n * verifies the magic properties, then stores a formatted string, prefixed by\n * prefix in dst.\n */\nvoid FormatVersionInformation(char *dst, int len, const char *prefix, void *version_information)\n{\n\tstruct version_information *v = (struct version_information*)version_information;\n\tdst[0] = 0;\n\tstrncat(dst, prefix, len);\n\tif(v->magic != VERSION_INFORMATION_MAGIC) {\n\t\tstrncat(dst, \"Missing/Invalid version information\", len);\n\t\treturn;\n\t}\n\tif(v->versionversion != 1) {\n\t\tstrncat(dst, \"Version information not understood\", len);\n\t\treturn;\n\t}\n\tif(!v->present) {\n\t\tstrncat(dst, \"Version information not available\", len);\n\t\treturn;\n\t}\n\n\tstrncat(dst, v->svnversion, len);\n\tif(v->clean == 0) {\n\t\tstrncat(dst, \"-unclean\", len);\n\t} else if(v->clean == 2) {\n\t\tstrncat(dst, \"-suspect\", len);\n\t}\n\n\tstrncat(dst, \" \", len);\n\tstrncat(dst, v->buildtime, len);\n}\n\n// -------------------------------------------------------------------------\n// timer lib\n// -------------------------------------------------------------------------\n// test procedure:\n//\n//\tti = GetTickCount();\n//\tSpinDelay(1000);\n//\tti = GetTickCount() - ti;\n//\tDbprintf(\"timer(1s): %d t=%d\", ti, GetTickCount());\n\nvoid StartTickCount()\n{\n// must be 0x40, but on my cpu - included divider is optimal\n// 0x20 - 1 ms / bit \n// 0x40 - 2 ms / bit\n\n\tAT91C_BASE_RTTC->RTTC_RTMR = AT91C_RTTC_RTTRST + 0x001D; // was 0x003B\n}\n\n/*\n* Get the current count.\n*/\nuint32_t RAMFUNC GetTickCount(){\n\treturn AT91C_BASE_RTTC->RTTC_RTVR;// was * 2;\n}\n\n// -------------------------------------------------------------------------\n// microseconds timer \n// -------------------------------------------------------------------------\nvoid StartCountUS()\n{\n\tAT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);\n//\tAT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC1XC1S_TIOA0;\n\tAT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;\n\n\t// fast clock\n\tAT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable\n\tAT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tAT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tAT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;\n\tAT91C_BASE_TC0->TC_RA = 1;\n\tAT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000\n\t\n\tAT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable \n\tAT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0\n\t\n\tAT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;\n\tAT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;\n\tAT91C_BASE_TCB->TCB_BCR = 1;\n\t}\n\nuint32_t RAMFUNC GetCountUS(){\n\treturn (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV / 15) * 10);\n}\n\nstatic uint32_t GlobalUsCounter = 0;\n\nuint32_t RAMFUNC GetDeltaCountUS(){\n\tuint32_t g_cnt = GetCountUS();\n\tuint32_t g_res = g_cnt - GlobalUsCounter;\n\tGlobalUsCounter = g_cnt;\n\treturn g_res;\n}\n\n\n// -------------------------------------------------------------------------\n// Mifare timer. Uses ssp_clk from FPGA \n// -------------------------------------------------------------------------\nvoid StartCountMifare()\n{\n\tAT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1) | (1 << AT91C_ID_TC2); // Enable Clock to all timers\n\tAT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1 \t\t// XC0 Clock = TIOA1\n\t\t\t\t\t\t\t| AT91C_TCB_TC1XC1S_NONE \t\t// XC1 Clock = none\n\t\t\t\t\t\t\t| AT91C_TCB_TC2XC2S_TIOA0;\t\t// XC2 Clock = TIOA0\n\n\t// configure TC1 to create a short pulse on TIOA1 when a rising edge on TIOB1 (= ssp_clk from FPGA) occurs:\n\tAT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; \t\t\t\t// disable TC1\n\tAT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK // TC1 Clock = MCK(48MHz)/2 = 24MHz\n\t\t\t\t\t\t\t| AT91C_TC_CPCSTOP\t\t\t\t// Stop clock on RC compare\n\t\t\t\t\t\t\t| AT91C_TC_EEVTEDG_RISING\t\t// Trigger on rising edge of Event\n\t\t\t\t\t\t\t| AT91C_TC_EEVT_TIOB\t\t\t// Event-Source: TIOB1 (= ssc_clk from FPGA = 13,56MHz / 16)\n\t\t\t\t\t\t\t| AT91C_TC_ENETRG\t\t\t\t// Enable external trigger event\n\t\t\t\t\t\t\t| AT91C_TC_WAVESEL_UP\t \t\t// Upmode without automatic trigger on RC compare\n\t\t\t\t\t\t\t| AT91C_TC_WAVE \t\t\t\t// Waveform Mode\n\t\t\t\t\t\t\t| AT91C_TC_AEEVT_SET \t\t\t// Set TIOA1 on external event\n\t\t\t\t\t\t\t| AT91C_TC_ACPC_CLEAR; \t\t\t// Clear TIOA1 on RC Compare\n\tAT91C_BASE_TC1->TC_RC = 0x04; \t\t\t\t\t\t\t// RC Compare value = 0x04\n\n\t// use TC0 to count TIOA1 pulses\n\tAT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; \t\t\t\t// disable TC0 \n\tAT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_XC0\t \t\t\t// TC0 clock = XC0 clock = TIOA1\n\t\t\t\t\t\t\t| AT91C_TC_WAVE \t\t\t\t// Waveform Mode\n\t\t\t\t\t\t\t| AT91C_TC_WAVESEL_UP\t \t\t// just count\n\t\t\t\t\t\t\t| AT91C_TC_ACPA_CLEAR \t\t\t// Clear TIOA0 on RA Compare\n\t\t\t\t\t\t\t| AT91C_TC_ACPC_SET; \t\t\t// Set TIOA0 on RC Compare\n\tAT91C_BASE_TC0->TC_RA = 1;\t\t\t\t\t\t\t\t// RA Compare value = 1; pulse width to TC2\n\tAT91C_BASE_TC0->TC_RC = 0; \t\t\t\t\t\t\t\t// RC Compare value = 0; increment TC2 on overflow\n\n\t// use TC2 to count TIOA0 pulses (giving us a 32bit counter (TC0/TC2) clocked by ssp_clk)\n\tAT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKDIS; \t\t\t\t// disable TC2 \n\tAT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_XC2\t \t\t\t// TC2 clock = XC2 clock = TIOA0\n\t\t\t\t\t\t\t| AT91C_TC_WAVE \t\t\t\t// Waveform Mode\n\t\t\t\t\t\t\t| AT91C_TC_WAVESEL_UP;\t \t\t// just count\n\t\n\t\n\tAT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;\t\t\t\t// enable TC0\n\tAT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;\t\t\t\t// enable TC1\n\tAT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN;\t\t\t\t// enable TC2\n\tAT91C_BASE_TCB->TCB_BCR = 1;\t\t\t\t\t\t\t// assert Sync (set all timers to 0 on next active clock edge)\n}\n\n\nuint32_t RAMFUNC GetCountMifare(){\n\tuint32_t tmp_count;\n\ttmp_count = (AT91C_BASE_TC2->TC_CV << 16) | AT91C_BASE_TC0->TC_CV;\n\tif ((tmp_count & 0xffff) == 0) { //small chance that we may have missed an increment in TC2\n\t\treturn (AT91C_BASE_TC2->TC_CV << 16);\n\t} \n\telse {\n\t\treturn tmp_count;\n\t}\n}\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/util.h", "content": "//-----------------------------------------------------------------------------\n// Jonathan Westhues, Aug 2005\n//\n// This code is licensed to you under the terms of the GNU GPL, version 2 or,\n// at your option, any later version. See the LICENSE.txt file for the text of\n// the license.\n//-----------------------------------------------------------------------------\n// Utility functions used in many places, not specific to any piece of code.\n//-----------------------------------------------------------------------------\n\n#ifndef __UTIL_H\n#define __UTIL_H\n\n#include \n#include \n#include \n\n#define BYTEx(x, n) (((x) >> (n * 8)) & 0xff )\n\n#define LED_RED 1\n#define LED_ORANGE 2\n#define LED_GREEN 4\n#define LED_RED2 8\n#define BUTTON_HOLD 1\n#define BUTTON_NO_CLICK 0\n#define BUTTON_SINGLE_CLICK -1\n#define BUTTON_DOUBLE_CLICK -2\n#define BUTTON_ERROR -99\n\nsize_t nbytes(size_t nbits);\nuint32_t SwapBits(uint32_t value, int nrbits);\nvoid num_to_bytes(uint64_t n, size_t len, uint8_t* dest);\nuint64_t bytes_to_num(uint8_t* src, size_t len);\n\nvoid SpinDelay(int ms);\nvoid SpinDelayUs(int us);\nvoid LED(int led, int ms);\nvoid LEDsoff();\nint BUTTON_CLICKED(int ms);\nint BUTTON_HELD(int ms);\nvoid FormatVersionInformation(char *dst, int len, const char *prefix, void *version_information);\n\nvoid StartTickCount();\nuint32_t RAMFUNC GetTickCount();\n\nvoid StartCountUS();\nuint32_t RAMFUNC GetCountUS();\nuint32_t RAMFUNC GetDeltaCountUS();\n\nvoid StartCountMifare();\nuint32_t RAMFUNC GetCountMifare();\n\n#endif\n" }, { "path": "TamagotchiFriends/proxmark/armsrc/version.c", "content": "#include \"proxmark3.h\"\r\n/* Generated file, do not edit */\r\nconst struct version_information __attribute__((section(\".version_information\"))) version_information = {\r\n\tVERSION_INFORMATION_MAGIC,\r\n\t1,\r\n\t1,\r\n\t0,\r\n\t\"svn 756\",\r\n\t\"2014-03-01 20:34:43\",\r\n};\r\n" }, { "path": "TamagotchiOn/tasmgotchi/demos/waitforbutton/myassembly.txt", "content": "PUSH {R4-R8,LR}\nSUB SP, SP, #0x20\nMOV R0, #9\nLDR R3, =(set_image_mode+1)\nMOV LR, PC\nBX R3 ;\nMOV R5, #0x40 ; '@'\nSTR R5, [SP]\nMOV R3, R5\nMOV R2, #0\nLDR R1, =violetchi\nMOV R0, R2\nLDR R4, =(show_game_image+1)\nMOV LR, PC\nBX R4 ; show_game_image\nLDR R1, =pressa\nMOV R0, #1\nMOV R5, #0x40 ; '@'\nSTR R5, [SP]\nMOV R3, R5\nMOV R2, #0\nLDR R4, =(show_game_image+1)\nMOV LR, PC\nBX R4 ; show_game_image\nMOV R1, #1\nMOV R0, #0x1000\nLDR R3, =(wait_for_button+1)\nMOV LR, PC\nBX R3 ; sub_20000932\nMOV\t\tR7, R0\nCMP R0, #1\nMOV LR, PC\nBEQ pass\nCMP R7, #1\nMOV LR, PC\nBNE\t\tlose\nMOV R5, #0x40 ; '@'\nSTR R5, [SP]\nMOV R3, R5\nMOV R2, #0\nMOV R0, #1\nLDR R1, =pressb\nLDR R4, =(show_game_image+1)\nMOV LR, PC\nBX R4 ; show_game_image\nMOV R1, #2\nMOV R0, #0x1000\nLDR R3, =(wait_for_button+1)\nMOV LR, PC\nBX R3 ; sub_20000932\nMOV\t\tR7, R0\nCMP R0, #1\nMOV LR, PC\nBEQ pass\nCMP R7, #1\nMOV LR, PC\nBNE\t\tlose\nMOV R5, #0x40 ; '@'\nSTR R5, [SP]\nMOV R3, R5\nMOV R2, #0\nMOV R0, #1\nLDR R1, =pressc\nLDR R4, =(show_game_image+1)\nMOV LR, PC\nBX R4 ; show_game_image\nMOV R1, #4\nMOV R0, #0x1000\nLDR R3, =(wait_for_button+1)\nMOV LR, PC\nBX R3 ; sub_20000932\nMOV\t\tR7, R0\nCMP R0, #1\nMOV LR, PC\nBEQ pass\nCMP R7, #1\nMOV LR, PC\nBNE\t\tlose\nB\t\tend\nlose:\nPUSH {R4-R8,LR} \nMOV R5, #0x40\nSTR R5, [SP]\nMOV R3, R5\nMOV R2, #0\nLDR R1, =ximg\nMOV R0, #1\nLDR R4, =(show_game_image+1)\nMOV LR, PC\nBX R4 ; show_game_image\nMOV R1, #7\nMOV R0, #0x300\nLDR R3, =(wait_for_button+1)\nMOV LR, PC\nBX R3 ; sub_20000932 \nPOP {R4-R8,LR}\nBX LR\npass:\nPUSH {R4-R8,LR}\nMOV R5, #0x40\nSTR R5, [SP]\nMOV R3, R5\nMOV R2, #0\nLDR R1, =check\nMOV R0, #1\nLDR R4, =(show_game_image+1)\nMOV LR, PC\nBX R4 ; show_game_image\nMOV R1, #7\nMOV R0, #0x500\nLDR R3, =(wait_for_button+1)\nMOV LR, PC\nBX R3 ; sub_20000932 \nPOP {R4-R8,LR}\nBX LR\nend: \nADD SP, SP, #0x20 ;\nPOP {R4-R8,LR}\nMOV\t\tR0, #3\nBX LR\n" }, { "path": "TamagotchiOn/tasmgotchi/demos/waitforbutton/myimages.txt", "content": "violetchi\t/home/natashenka/Documents/violetchi_tama.bmp\ncheck\t\t/home/natashenka/Documents/check.bmp\nximg\t\t/home/natashenka/Documents/x.bmp\npressa\t\t/home/natashenka/Documents/pressa.bmp\npressb\t\t/home/natashenka/Documents/pressb.bmp\npressc\t\t/home/natashenka/Documents/pressc.bmp\n\n" }, { "path": "TamagotchiOn/tasmgotchi/makegame.py", "content": "import sys\ntry:\n\timport armasm\nexcept:\n\tprint \"armasm is required https://github.com/stephanh42/armasm\"\ntry:\n\timport Image\nexcept:\n\tprint \"PIL is required\"\nfrom sets import Set\n\nif len(sys.argv) < 4:\n\tprint \"makegame.py assembly image_listing outfile\"\n\n\nf = open(\"gametemp\", 'rb')\ngtemp = f.read()\nf.close()\n\nindex = 0x3690\ngtemp = gtemp[:index]\nimport random\n\ndef addimage(path):\n\tglobal gtemp, index\n\tim = Image.open(path)\n\tpx = im.load() \n\ts = Set()\n\n\tfor y in range(0, im.height):\n\t\tfor x in range(0, im.width):\n\t\t\ts.add(px[x,y])\n\tif len(s) > 16:\n\t\tprint \"image\" + path + \" has too many colors\"\n\t\texit()\n\twhile len(s) != 15:\n\t\ts.add((random.randrange(0, 255), 0, 0))\n\n\timg = \"\"\n\timg = img + chr(im.width) + chr(im.height) # add width and height\n\timg = img + chr(len(s)&0xff) + chr(len(s)>>8)\n\timg = img + \"\\x01\\xff\"\n\n\tclist = []\n\tj = 0\n\tfor item in s:\n\t\tclist.append(item)\n\t\tb = item[0]/8\n\t\tr = item[2]/8\n\t\tg = item[1]/4\n\n\t\tb1 = (r <<3) + (g >> 3)\n\t\tb2 = ((g& 7) << 5) + b\n\t\tprint \"index\", j, hex(b1), hex(b2), item\n\t\tj = j + 1\n\t\timg = img + chr(b1) + chr(b2)\n\n\tp = \"\"\n\tfor y in range(0, im.height):\n\t\tfor x in range(0, im.width):\n\t\t\t#print px[x,y]\n\t\t\tv = clist.index(px[x,y])\n\t\t\tif v > 16:\n\t\t\t\tprint v\n\t\t\t\texit()\n\t\t\tp = p + chr(v)\n\n\tt = \"\"\n\n\ti = 0\n\tprint \"p\", len(p)\n\tpad = False\n\tlasfull = 0\n\tif im.width %2 != 0:\n\t\tpad = True\n\t\tlastfull = im.width/2*2\n\t\tif(lastfull %2!=0):\n\t\t\tprint \"error\"\n\t\t\texit()\n\twhile i < len(p)-1:\n\t#print hex(ord(p[i]))\n\t#print hex(ord(p[i+1]))\n\t#print(hex(ord(p[i]) + (ord(p[i+1])<<4)))\n\t\tif pad:\n\t\t\tif i % im.width == lastfull:\n\t\t\t\tt = t + chr(ord(p[i]) + 0)\n\t\t\t\ti = i + 1\t\n\t\t\telse:\n\t\t\t\tt = t + chr(ord(p[i]) + (ord(p[i+1])<<4))\n\t\t\t\ti = i + 2\t\n\t\telse:\n\t\t\tt = t + chr(ord(p[i]) + (ord(p[i+1])<<4))\n\n\t\t\ti = i + 2\n\timg = img + t\n\told_index = len(gtemp)\n\tgtemp = gtemp + img\n\t\n\n\tif len(gtemp)%4 !=0:\n\t\tindex = index + (4-index%4)\n\t\twhile len(gtemp) %4 != 0:\n\t\t\tgtemp = gtemp + '\\x00' \n\treturn 0x207F0000+ old_index\n\n\n\n\n\nftable = {\"show_game_image\": 0x200008FE, \"set_image_mode\" : 0x20003B0E, \"set_mem_0\": 0x2000074E, \"sub_20000A36\" : 0x20000A36, \"wait_for_button\" : 0x20000932, \"set_option_1\" : 0x20000454, \"set_option_2\": 0x20000460, \"set_option_3\": 0x20000448, \"check_option_1\": 0x20000430, \"check_option_2\": 0x2000043C, \"check_option_3\": 0x20000424}\nitable = {}\n\nf = open(sys.argv[2], 'r')\nimages = f.readlines()\nf.close()\n\nfor item in images:\n\ti = item.split()\n\tif len(i) == 0:\n\t\tcontinue\n\tif(len(i) !=2):\n\t\tprint \"error splitting image\"\n\t\texit()\n\tname = i[0]\n\tloc = i[1]\n\taddr = addimage(loc)\n # print \"image at\", hex(addr)\n\titable[name] = addr\n\nf = open(sys.argv[1])\nassembly = f.read()\nf.close()\n\nfor item in ftable:\n\t#print item\n\tassembly = assembly.replace(\"(\" + item + \"+1)\", hex(ftable[item]+1))\n\nfor item in ftable:\n\t#print item\n\tassembly = assembly.replace(item, hex(ftable[item]))\n\nfor item in itable:\n\t#print item\n\tassembly = assembly.replace(item, hex(itable[item]))\n\n#print assembly\n\ncompiled = armasm.asm(\"str -> i\", assembly)\ncode = compiled.__armasm_code__\ncode_index = 0x336c\ncstr = \"\"\nfor i in range(0, len(code)):\n\tnum = code[i]\n\tcstr = cstr + chr(num&0xff) + chr((num&0xff00)>>8) + chr((num&0xff0000)>>16) + chr((num&0xff000000)>>24)\n\nprint hex(code_index+len(cstr))\ngtemp = gtemp[:code_index] + cstr + gtemp[code_index+len(cstr):]\ngamelen = len(gtemp)\ngls = chr((gamelen &0xff000000)>>24)+chr((gamelen &0xff0000)>>16)+chr((gamelen &0xff00)>>8)+chr(gamelen &0xff)\ngtemp = gtemp[:72]+gls+gtemp[76:]\n\n\nf = open(sys.argv[3], 'wb')\nf.write(gtemp)\nf.close()\n\n\n\n\n\n\n\n\n\n\n\n" }, { "path": "codedump/README.txt", "content": "Code Dump Files\r\n\r\nbinbits -- First 0x100 bytes of Tama code in binary\r\ndecode.py -- SPI decoding code (not used)\r\nfirst100.txt -- First 0x100 bytes of Tama code dissasembled\r\nGPTestProgram -- GeneralPlus test program\r\nimages -- Tamagotchi images from ROM\r\nin.txt -- Code execution POC\r\nports.txt -- Known GPLB52640A ports so far. Please contribute\r\n/rompages -- The pages of the ROM\r\n\r\nQuestions? Comments? Contributions? \r\n\r\nContact: natashenka@kwartzlab.ca / @natashenka" }, { "path": "codedump/decode.py", "content": "f = open(\"c.csv\", 'r')\r\no = open(\"c.bin\", 'w')\r\n\r\nl = f.readlines()\r\nbegin = True\r\nstate = 1\r\nval = 0\r\ncount = 8\r\nc = 0\r\nfor item in l:\r\n\tc = c + 1\r\n\titem = item[item.find(\",\")+1:]\r\n\titem = item[:item.find(\",\")]\r\n\tif state == 1:\r\n\t\tif item!= \"0\":\r\n\t\t\tprint \"error1 \" + item + \" \" + str(c)\r\n\t\tstate = 2\r\n\telif state == 2:\r\n\t\tif item!= \"1\":\r\n\t\t\tprint \"error2 \" + item + \" \" + str(c)\r\n\t\t\tstate = 2\r\n\t\telse:\r\n\t\t\tstate = 3\r\n\telif state == 3:\r\n\t\tif item == \"0\":\r\n\t\t\tval = val << 1\r\n\t\t\tstate = 2\r\n\t\telse:\r\n\t\t\tval = (val << 1) | 1\r\n\t\t\tstate = 1\r\n\t\tcount = count - 1\r\n\t\tif count == 0:\r\n\t\t\tcount = 8\r\n\t\t\to.write(chr(val))\r\n\t\t\tval = 0\r\n\t\t" }, { "path": "codedump/first100.txt", "content": " * = 0000\r\n0000 78 SEI\r\n0001 A2 FF LDX #$FF\r\n0003 9A TXS\r\n0004 A9 FF LDA #$FF\r\n0006 8D 04 30 STA $3004 //I have no idea what port this is, but I'm sure setting it to ff is a great idea\r\n0009 A9 82 LDA #$82\r\n000B 8D 01 30 STA $3001 //This is clock control. Gotta keep those clocks under control\r\n000E A9 80 LDA #$80\r\n0010 8D 02 30 STA $3002 // This port controls the 32 k oscillator\r\n0013 A9 00 LDA #$00\r\n0015 8D 40 30 STA $3040 //LCD Setup\r\n0018 A9 03 LDA #$03\r\n001A 8D 4A 30 STA $304A //Not sure what this does (possible LCD related)\r\n001D A9 10 LDA #$10\r\n001F 8D 11 30 STA $3011 //make p0 out and rest in (weird, p0 is in by startup)\r\n0022 A9 88 LDA #$88\r\n0024 8D 10 30 STA $3010 //Port A config\r\n0027 A9 1F LDA #$1F\r\n0029 85 20 STA $20 //wonder what is here?\r\n002B 8D 12 30 STA $3012 // data\r\n002E A9 00 LDA #$00\r\n0030 8D 13 30 STA $3013 // strobe\r\n0033 A9 7E LDA #$7E\r\n0035 8D 15 30 STA $3015 // possibly io for port b\r\n0038 A9 01 LDA #$01\r\n003A 8D 14 30 STA $3014 // possible config for port b\r\n003D A9 07 LDA #$07\r\n003F 85 21 STA $21 // not sure what this is either\r\n0041 8D 16 30 STA $3016 //port b data?\r\n0044 A2 00 LDX #$00\r\n0046 A9 00 LDA #$00\r\n0048 95 00 STA $00,X\r\n004A E8 INX\r\n004B D0 FB BNE $0048 // zero RAM i guess\r\n004D A2 00 LDX #$00\r\n004F A9 00 LDA #$00\r\n0051 85 48 STA $48 // more mystery addresses\r\n0053 A9 01 LDA #$01\r\n0055 85 49 STA $49 //here too\r\n0057 A9 00 LDA #$00\r\n0059 85 4A STA $4A // and here\r\n005B A9 06 LDA #$06\r\n005D 85 4B STA $4B // and here\r\n005F A5 48 LDA $48\r\n0061 C5 4A CMP $4A\r\n0063 D0 06 BNE $006B\r\n0065 A5 49 LDA $49\r\n0067 C5 4B CMP $4B\r\n0069 F0 0D BEQ $0078\r\n006B A9 00 LDA #$00\r\n006D 81 48 STA ($48,X)\r\n006F E6 48 INC $48\r\n0071 D0 02 BNE $0075\r\n0073 E6 49 INC $49\r\n0075 4C 5F CC JMP $CC5F\r\n0078 A2 00 LDX #$00\r\n007A A9 00 LDA #$00\r\n007C 85 48 STA $48\r\n007E A9 10 LDA #$10\r\n0080 85 49 STA $49\r\n0082 A9 00 LDA #$00\r\n0084 85 4A STA $4A\r\n0086 A9 12 LDA #$12\r\n0088 85 4B STA $4B\r\n008A A5 48 LDA $48\r\n008C C5 4A CMP $4A\r\n008E D0 06 BNE $0096\r\n0090 A5 49 LDA $49\r\n0092 C5 4B CMP $4B\r\n0094 F0 0D BEQ $00A3\r\n0096 A9 00 LDA #$00\r\n0098 81 48 STA ($48,X)\r\n009A E6 48 INC $48\r\n009C D0 02 BNE $00A0\r\n009E E6 49 INC $49\r\n00A0 4C 8A CC JMP $CC8A\r\n00A3 A9 10 LDA #$10\r\n00A5 8D 11 30 STA $3011\r\n00A8 A9 88 LDA #$88\r\n00AA 8D 10 30 STA $3010\r\n00AD A9 1F LDA #$1F\r\n00AF 85 20 STA $20\r\n00B1 8D 12 30 STA $3012\r\n00B4 A9 00 LDA #$00\r\n00B6 8D 13 30 STA $3013\r\n00B9 A9 7E LDA #$7E\r\n00BB 8D 15 30 STA $3015\r\n00BE A9 01 LDA #$01\r\n00C0 8D 14 30 STA $3014\r\n00C3 A9 07 LDA #$07\r\n00C5 85 21 STA $21\r\n00C7 8D 16 30 STA $3016\r\n00CA A0 00 LDY #$00\r\n00CC 20 60 D4 JSR $D460\r\n00CF 20 60 D4 JSR $D460\r\n00D2 20 60 D4 JSR $D460\r\n00D5 20 60 D4 JSR $D460\r\n00D8 20 60 D4 JSR $D460\r\n00DB 20 60 D4 JSR $D460\r\n00DE 20 60 D4 JSR $D460\r\n00E1 20 60 D4 JSR $D460\r\n00E4 88 DEY\r\n00E5 D0 E5 BNE $00CC\r\n00E7 20 09 E2 JSR $E209\r\n00EA C9 07 CMP #$07\r\n00EC D0 07 BNE $00F5\r\n00EE A9 41 LDA #$41\r\n00F0 85 22 STA $22\r\n00F2 4C 94 CD JMP $CD94\r\n00F5 A9 0E LDA #$0E\r\n00F7 85 3A STA $3A\r\n00F9 A9 83 LDA #$83\r\n00FB 85 26 STA $26\r\n00FD A9 B3 LDA #$B3\r\n00FF 85 00 STA $00\r\n0101 .END\r\n0013 A9 00 LDA #$00\r\n0015 8D 40 30 STA $3040\r\n0018 A9 03 LDA #$03\r\n001A 8D 4A 30 STA $304A\r\n001D A9 10 LDA #$10\r\n001F 8D 11 30 STA $3011\r\n0022 A9 88 LDA #$88\r\n0024 8D 10 30 STA $3010\r\n0027 A9 1F LDA #$1F\r\n0029 85 20 STA $20\r\n002B 8D 12 30 STA $3012\r\n002E A9 00 LDA #$00\r\n0030 8D 13 30 STA $3013\r\n0033 A9 7E LDA #$7E\r\n0035 8D 15 30 STA $3015\r\n0038 A9 01 LDA #$01\r\n003A 8D 14 30 STA $3014\r\n003D A9 07 LDA #$07\r\n003F 85 21 STA $21\r\n0041 8D 16 30 STA $3016\r\n0044 A2 00 LDX #$00\r\n0046 A9 00 LDA #$00\r\n0048 95 00 STA $00,X\r\n004A E8 INX\r\n004B D0 FB BNE $0048\r\n004D A2 00 LDX #$00\r\n004F A9 00 LDA #$00\r\n0051 85 48 STA $48\r\n0053 A9 01 LDA #$01\r\n0055 85 49 STA $49\r\n0057 A9 00 LDA #$00\r\n0059 85 4A STA $4A\r\n005B A9 06 LDA #$06\r\n005D 85 4B STA $4B\r\n005F A5 48 LDA $48\r\n0061 C5 4A CMP $4A\r\n0063 D0 06 BNE $006B\r\n0065 A5 49 LDA $49\r\n0067 C5 4B CMP $4B\r\n0069 F0 0D BEQ $0078\r\n006B A9 00 LDA #$00\r\n006D 81 48 STA ($48,X)\r\n006F E6 48 INC $48\r\n0071 D0 02 BNE $0075\r\n0073 E6 49 INC $49\r\n0075 4C 5F CC JMP $CC5F\r\n0078 A2 00 LDX #$00\r\n007A A9 00 LDA #$00\r\n007C 85 48 STA $48\r\n007E A9 10 LDA #$10\r\n0080 85 49 STA $49\r\n0082 A9 00 LDA #$00\r\n0084 85 4A STA $4A\r\n0086 A9 12 LDA #$12\r\n0088 85 4B STA $4B\r\n008A A5 48 LDA $48\r\n008C C5 4A CMP $4A\r\n008E D0 06 BNE $0096\r\n0090 A5 49 LDA $49\r\n0092 C5 4B CMP $4B\r\n0094 F0 0D BEQ $00A3\r\n0096 A9 00 LDA #$00\r\n0098 81 48 STA ($48,X)\r\n009A E6 48 INC $48\r\n009C D0 02 BNE $00A0\r\n009E E6 49 INC $49\r\n00A0 4C 8A CC JMP $CC8A\r\n00A3 A9 10 LDA #$10\r\n00A5 8D 11 30 STA $3011\r\n00A8 A9 88 LDA #$88\r\n00AA 8D 10 30 STA $3010\r\n00AD A9 1F LDA #$1F\r\n00AF 85 20 STA $20\r\n00B1 8D 12 30 STA $3012\r\n00B4 A9 00 LDA #$00\r\n00B6 8D 13 30 STA $3013\r\n00B9 A9 7E LDA #$7E\r\n00BB 8D 15 30 STA $3015\r\n00BE A9 01 LDA #$01\r\n00C0 8D 14 30 STA $3014\r\n00C3 A9 07 LDA #$07\r\n00C5 85 21 STA $21\r\n00C7 8D 16 30 STA $3016\r\n00CA A0 00 LDY #$00\r\n00CC 20 60 D4 JSR $D460\r\n00CF 20 60 D4 JSR $D460\r\n00D2 20 60 D4 JSR $D460\r\n00D5 20 60 D4 JSR $D460\r\n00D8 20 60 D4 JSR $D460\r\n00DB 20 60 D4 JSR $D460\r\n00DE 20 60 D4 JSR $D460\r\n00E1 20 60 D4 JSR $D460\r\n00E4 88 DEY\r\n00E5 D0 E5 BNE $00CC\r\n00E7 20 09 E2 JSR $E209\r\n00EA C9 07 CMP #$07\r\n00EC D0 07 BNE $00F5\r\n00EE A9 41 LDA #$41\r\n00F0 85 22 STA $22\r\n00F2 4C 94 CD JMP $CD94\r\n00F5 A9 0E LDA #$0E\r\n00F7 85 3A STA $3A\r\n00F9 A9 83 LDA #$83\r\n00FB 85 26 STA $26\r\n00FD A9 B3 LDA #$B3\r\n00FF 85 00 STA $00\r\n0101 .END\r\n000E A9 80 LDA #$80\r\n0010 8D 02 30 STA $3002\r\n0013 A9 00 LDA #$00\r\n0015 8D 40 30 STA $3040\r\n0018 A9 03 LDA #$03\r\n001A 8D 4A 30 STA $304A\r\n001D A9 10 LDA #$10\r\n001F 8D 11 30 STA $3011\r\n0022 A9 88 LDA #$88\r\n0024 8D 10 30 STA $3010\r\n0027 A9 1F LDA #$1F\r\n0029 85 20 STA $20\r\n002B 8D 12 30 STA $3012\r\n002E A9 00 LDA #$00\r\n0030 8D 13 30 STA $3013\r\n0033 A9 7E LDA #$7E\r\n0035 8D 15 30 STA $3015\r\n0038 A9 01 LDA #$01\r\n003A 8D 14 30 STA $3014\r\n003D A9 07 LDA #$07\r\n003F 85 21 STA $21\r\n0041 8D 16 30 STA $3016\r\n0044 A2 00 LDX #$00\r\n0046 A9 00 LDA #$00\r\n0048 95 00 STA $00,X\r\n004A E8 INX\r\n004B D0 FB BNE $0048\r\n004D A2 00 LDX #$00\r\n004F A9 00 LDA #$00\r\n0051 85 48 STA $48\r\n0053 A9 01 LDA #$01\r\n0055 85 49 STA $49\r\n0057 A9 00 LDA #$00\r\n0059 85 4A STA $4A\r\n005B A9 06 LDA #$06\r\n005D 85 4B STA $4B\r\n005F A5 48 LDA $48\r\n0061 C5 4A CMP $4A\r\n0063 D0 06 BNE $006B\r\n0065 A5 49 LDA $49\r\n0067 C5 4B CMP $4B\r\n0069 F0 0D BEQ $0078\r\n006B A9 00 LDA #$00\r\n006D 81 48 STA ($48,X)\r\n006F E6 48 INC $48\r\n0071 D0 02 BNE $0075\r\n0073 E6 49 INC $49\r\n0075 4C 5F CC JMP $CC5F\r\n0078 A2 00 LDX #$00\r\n007A A9 00 LDA #$00\r\n007C 85 48 STA $48\r\n007E A9 10 LDA #$10\r\n0080 85 49 STA $49\r\n0082 A9 00 LDA #$00\r\n0084 85 4A STA $4A\r\n0086 A9 12 LDA #$12\r\n0088 85 4B STA $4B\r\n008A A5 48 LDA $48\r\n008C C5 4A CMP $4A\r\n008E D0 06 BNE $0096\r\n0090 A5 49 LDA $49\r\n0092 C5 4B CMP $4B\r\n0094 F0 0D BEQ $00A3\r\n0096 A9 00 LDA #$00\r\n0098 81 48 STA ($48,X)\r\n009A E6 48 INC $48\r\n009C D0 02 BNE $00A0\r\n009E E6 49 INC $49\r\n00A0 4C 8A CC JMP $CC8A\r\n00A3 A9 10 LDA #$10\r\n00A5 8D 11 30 STA $3011\r\n00A8 A9 88 LDA #$88\r\n00AA 8D 10 30 STA $3010\r\n00AD A9 1F LDA #$1F\r\n00AF 85 20 STA $20\r\n00B1 8D 12 30 STA $3012\r\n00B4 A9 00 LDA #$00\r\n00B6 8D 13 30 STA $3013\r\n00B9 A9 7E LDA #$7E\r\n00BB 8D 15 30 STA $3015\r\n00BE A9 01 LDA #$01\r\n00C0 8D 14 30 STA $3014\r\n00C3 A9 07 LDA #$07\r\n00C5 85 21 STA $21\r\n00C7 8D 16 30 STA $3016\r\n00CA A0 00 LDY #$00\r\n00CC 20 60 D4 JSR $D460\r\n00CF 20 60 D4 JSR $D460\r\n00D2 20 60 D4 JSR $D460\r\n00D5 20 60 D4 JSR $D460\r\n00D8 20 60 D4 JSR $D460\r\n00DB 20 60 D4 JSR $D460\r\n00DE 20 60 D4 JSR $D460\r\n00E1 20 60 D4 JSR $D460\r\n00E4 88 DEY\r\n00E5 D0 E5 BNE $00CC\r\n00E7 20 09 E2 JSR $E209\r\n00EA C9 07 CMP #$07\r\n00EC D0 07 BNE $00F5\r\n00EE A9 41 LDA #$41\r\n00F0 85 22 STA $22\r\n00F2 4C 94 CD JMP $CD94\r\n00F5 A9 0E LDA #$0E\r\n00F7 85 3A STA $3A\r\n00F9 A9 83 LDA #$83\r\n00FB 85 26 STA $26\r\n00FD A9 B3 LDA #$B3\r\n00FF 85 00 STA $00\r\n0101 .END" }, { "path": "codedump/ports.txt", "content": "Port\tFunction\t\t\t\t\tSource\r\n \r\n3000\tROM page\t\t\t\t\tTamagotchi ROM dump (tested)\r\n3001\tClock Control\t\t\t\t\tData sheet\r\n3002\tOsc Control\t\t\t\t\tApplication note 16\r\n3007\tWakeup Control\t\t\t\t\tApplication note 16\r\n3010\tPort A Config\t\t\t\t\tApplication note 16\r\n3011\tPort A Dir\t\t\t\t\tApplication note 16\r\n3012\tPort A Data\t\t\t\t\tApplication note 16\r\n3013\tPort A Pull\t\t\t\t\tApplication note 16\r\n3014\tPort B Config\t\t\t\t\tTamagotchi ROM dump\r\n3015\tPort B Dir\t\t\t\t\tTamagotchi ROM dump\r\n3016\tPort B Data\t\t\t\t\tTamagotchi ROM dump\r\n303e\tSeg 0-Seg7\t\t\t\t\tConfirmation sheet\r\n303f\tSeg8-seg15\t\t\t\t\tConfirmation sheet\r\n3040\tLCD Setup\t\t\t\t\tApplication note 16\r\n3041\tLCD Setup 2\t\t\t\t\tApplication note 16\r\n3042\tLCD Clock 1\t\t\t\t\tApplication note 16\r\n3043\tLCD Clock 2\t\t\t\t\tApplication note 16\r\n3044\tLCD Seg Num\t\t\t\t\tApplication note 16\r\n3045\tLCD Com Num\t\t\t\t\tApplication note 16\r\n3047\tLCD Buffer Control\t\t\t\tApplication note 16\r\n3049\tLCD Pump\t\t\t\t\tApplication note 16" }, { "path": "codedump/tf/eeprom5cd/eeprom5cd.ino", "content": " #include //I2C library\n\n byte somedata[]= { 0x0, 0xaa, 0x55, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, \n\n\n 0x32, 0x17, 0x2, 0x1, 0x2, 0x1, 0xa, 0x0, 0x1a, 0x0, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, //300\n 0x20, 0x5, 0x6, 0x10, 0x1, 0xff, 0x01, 0x02, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, //310\n 0x77, 0x77, 0x77, 0x77, 0x77, 0x5, 0x4, 0x6, 0x77, 0x077, 0x55, 0xff, 0x77, 0x77, 0x77, 0x77, //320\n 0xff, 0xff, 0x40, 0xea, 0xea, 0xea, 0xea, 0xea, 0xea, 0xea, 0xea, 0xea, 0xea, 0xea, 0xea, 0xea, //330 \n 0xea, 0x78, 0xa9, 0xff, 0x8d, 0x11, 0x30, 0x8d, 0x09, 0x11, 0x8d, 0xc5, 0x00, 0x8d, 0xc6, 0x00, //340\n 0xa2, 0x08, 0xb1, 0xc5, 0x0a, 0xa0, 0x01, 0x90, 0x02, 0xa0, 0x03, 0xd0, 0x04, 0xea, 0xea, 0xea, //350 330 is jump\n 0xea, 0xea, 0x8c, 0x12, 0x30, 0xa0, 0x00, 0x8c, 0x12, 0x30, 0xca, 0xd0, 0xe7, 0xee, 0xc5, 0x00, 0xd0, 0xde, 0xee, 0xc6, 0x00, //360 34b load\n 0xd0, 0xd9, 0xa9, 0x17, 0x8d, 0x00, 0x30, 0xd0, 0xd2, 0xc, 0x38, 0x03, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, //370\n 0xe, 0xd, 0x13, 0x7, 0xa, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,\n 0x2f, 0x2e, 0x31, 0x1f, 0x21, 0xff, 0xff, 0xff, 0xff, 0x3b, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1f, 0x29, 0x5, 0x0, 0x2, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x3, 0xdd, 0xdd, 0xdd, 0xdd, 0xf, 0xb, 0xff, 0x2, 0x8, 0x1, 0x8, 0xf0, 0xaa, 0x1a, 0x1a, 0x1, 0x1, 0x2, 0x3, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1f, 0x29, 0x0, 0x2, 0x1a, 0xff, 0x1a, 0x1a, 0x1a, 0x1a, 0x13, 0xdd, 0x8, 0x12, 0x1a, 0x8, 0x12, 0x1a, 0x0, 0x1a, 0x13, 0x4, 0x12, 0x13, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x1a, 0x2, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x1a, 0x2, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x1a, 0x2, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x1a, 0x2, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };\n \n\n void i2c_eeprom_write_byte( int deviceaddress, unsigned int eeaddress, byte data ) {\n int rdata = data;\n Wire.beginTransmission(deviceaddress);\n Wire.write((int)(eeaddress >> 8)); // MSB\n Wire.write((int)(eeaddress & 0xFF)); // LSB\n Wire.write(rdata);\n Wire.endTransmission();\n }\n\n // WARNING: address is a page address, 6-bit end will wrap around\n // also, data can be maximum of about 30 bytes, because the Wire library has a buffer of 32 bytes\n void i2c_eeprom_write_page( int deviceaddress, unsigned int eeaddresspage, byte* data, byte length ) {\n Wire.beginTransmission(deviceaddress);\n Wire.write((int)(eeaddresspage >> 8)); // MSB\n Wire.write((int)(eeaddresspage & 0xFF)); // LSB\n byte c;\n for ( c = 0; c < length; c++)\n Wire.write(data[c]);\n Wire.endTransmission();\n }\n\n byte i2c_eeprom_read_byte( int deviceaddress, unsigned int eeaddress ) {\n byte rdata = 0xFF;\n Wire.beginTransmission(deviceaddress);\n Wire.write((int)(eeaddress >> 8)); // MSB\n Wire.write((int)(eeaddress & 0xFF)); // LSB\n Wire.endTransmission();\n Wire.requestFrom(deviceaddress,1);\n if (Wire.available()) rdata = Wire.read();\n return rdata;\n }\n\n // maybe let's not read more than 30 or 32 bytes at a time!\n void i2c_eeprom_read_buffer( int deviceaddress, unsigned int eeaddress, byte *buffer, int length ) {\n Wire.beginTransmission(deviceaddress);\n Wire.write((int)(eeaddress >> 8)); // MSB\n Wire.write((int)(eeaddress & 0xFF)); // LSB\n Wire.endTransmission();\n Wire.requestFrom(deviceaddress,length);\n int c = 0;\n for ( c = 0; c < length; c++ )\n if (Wire.available()) buffer[c] = Wire.read();\n }\n\n\n\n\n void setup() \n {\n \n int i;\n Wire.begin(); // initialise the connection\n\n delay(5000);\n for(i = 0; i < 200; i++){\n Serial.print(i);\n i2c_eeprom_write_byte(0x50, i, somedata[i]);\n \n delay(10);\n }\n Serial.begin(9600);\n Serial.print(sizeof(somedata));\n delay(5000);\n // i2c_eeprom_write_byte(0x50, 0x20, 0xaa );\n //i2c_eeprom_write_page(0x50, 0, (byte *)somedata, sizeof(somedata)); // write to EEPROM \n\n //add a small delay\n\n Serial.println(\"Hello, Natalie\");\n Serial.println(\"Memory written\");\n }\n\n void loop() \n {\n Serial.begin(9600);\n Wire.begin();\n int addr=0; //first address\n int i;\n byte b = i2c_eeprom_read_byte(0x50, 0); // access the first address from the memory\n\n for (i = 0; i < 4000; i++) \n {\n Serial.print(b, HEX); //print content to serial port\n Serial.print(\" \");\n addr++; //increase address\n b = i2c_eeprom_read_byte(0x50, addr); //access an address from the memory\n }\n Serial.println(\" \");\n delay(2000);\n\n while(true){} }\n \n \n \n \n \n \r\n" }, { "path": "codedump/tf/glitch2/glitch2.ino", "content": "/*\n Blink\n Turns on an LED on for one second, then off for one second, repeatedly.\n \n This example code is in the public domain.\n */\n \n// Pin 13 has an LED connected on most Arduino boards.\n// give it a name:\nint led = 13;\n\n// the setup routine runs once when you press reset:\nvoid setup() { \n // initialize the digital pin as an output.\n pinMode(led, OUTPUT);\n digitalWrite(led, HIGH); \n delay(10000); \n\n}\n\n// the loop routine runs over and over again forever:\nvoid loop() {\n // turn the LED on (HIGH is the voltage level)\n digitalWrite(led, HIGH); \n delay(1000); // wait for a second\n // digitalWrite(led, LOW); // turn the LED off by making the voltage LOW\n\n for(int i = 0; i < 35; i++){\n digitalWrite(led, HIGH);\n delay(5); \n digitalWrite(led, LOW); \n delay(5); \n }\n digitalWrite(led, HIGH);\n while(true){}\n\n\n}\r\n" }, { "path": "demos/README", "content": "Figure simulator demos\r\n\r\nfacemain.c -- displays a picture \r\nnataliemain.c -- displays an animation\r\nnsdemomain.c -- displays static image\r\nharlemshake -- makes Tamagotchi do the Harlem Shake (figure image)\r\nmafd -- makes Tamagotchi play \"Mad World\" (figure image)\r\n\r\nQuestions? Comments? Contributions? \r\n\r\nContact: natashenka@kwartzlab.ca / @natashenka" }, { "path": "demos/facemain.c", "content": "/**\r\n ******************************************************************************\r\n * @file main.c\r\n * @author MCD Application Team\r\n * @version V1.0.0\r\n * @date 19-September-2011\r\n * @brief Main program body\r\n ******************************************************************************\r\n * @attention\r\n *\r\n * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r\n * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r\n * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r\n * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r\n * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r\n * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r\n *\r\n *

© COPYRIGHT 2011 STMicroelectronics

\r\n ******************************************************************************\r\n */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n//#include \"main.h\"\r\n#include \"stm32f4_discovery.h\"\r\n//#include \"stm32f4xx_it.c\"\r\nuint8_t flag;\r\n//#include \r\n/** @addtogroup STM32F4-Discovery_Demo\r\n * @{\r\n */\r\nint i;\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n\r\n\r\n//#define CLK GPIO_Pin_11\r\n//#define ADDRESS GPIO_Pin_10\r\n//#define E GPIO_Pin_9\r\nEXTI_InitTypeDef EXTI_InitStructure;\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n\r\n\r\n//uint32_t a = 0;\r\n//int i;\r\nint index;\r\nint started = 0;\r\n/* Private function prototypes -----------------------------------------------*/\r\n\r\nGPIO_InitTypeDef GPIO_InitStructure;\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\nvoid EXTILine0_Config(void)\r\n{\r\n\r\n GPIO_InitTypeDef GPIO_InitStructure;\r\n NVIC_InitTypeDef NVIC_InitStructure;\r\n\r\n /* Enable GPIOA clock */\r\n RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);\r\n /* Enable SYSCFG clock */\r\n RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);\r\n\r\n /* Configure PA0 pin as input floating */\r\n GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r\n GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;\r\n GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;\r\n GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;\r\n GPIO_Init(GPIOA, &GPIO_InitStructure);\r\n\r\n GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r\n GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r\n GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;\r\n GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1;\r\n GPIO_Init(GPIOA, &GPIO_InitStructure);\r\n\r\n /* Connect EXTI Line0 to PA0 pin */\r\n SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOA, EXTI_PinSource0);\r\n\r\n /* Configure EXTI Line0 */\r\n EXTI_InitStructure.EXTI_Line = EXTI_Line0;\r\n EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;\r\n EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;\r\n EXTI_InitStructure.EXTI_LineCmd = ENABLE;\r\n EXTI_Init(&EXTI_InitStructure);\r\n\r\n /* Enable and set EXTI Line0 Interrupt to the lowest priority */\r\n NVIC_InitStructure.NVIC_IRQChannel = EXTI0_IRQn;\r\n NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x01;\r\n NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x01;\r\n NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r\n NVIC_Init(&NVIC_InitStructure);\r\n\r\n SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOA, EXTI_PinSource1);\r\n\r\n /* Configure EXTI Line0 */\r\n EXTI_InitStructure.EXTI_Line = EXTI_Line1;\r\n EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;\r\n EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;\r\n EXTI_InitStructure.EXTI_LineCmd = ENABLE;\r\n EXTI_Init(&EXTI_InitStructure);\r\n\r\n /* Enable and set EXTI Line0 Interrupt to the lowest priority */\r\n NVIC_InitStructure.NVIC_IRQChannel = EXTI1_IRQn;\r\n NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x02;\r\n NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x01;\r\n NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r\n NVIC_Init(&NVIC_InitStructure);\r\n\r\n\r\n\r\n}\r\n\r\nint loops = 0;\r\nint hit = 0;\r\nint q;\r\nint as[2000];\r\nint read = 1;\r\nuint32_t a = 0;\r\nint acount = 0;\r\nuint8_t val;\r\nuint8_t c;\r\n\r\nuint8_t *vs[8];\r\nuint8_t v1[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0x29, 0xc0, 0xff, 0xca, 0x9f, 0x28, 0xc0, 0xff, 0xca, 0xa7, 0x67, 0xc0, 0xff, 0xda, 0xa8, 0xa7, 0xc0, 0xff, 0xda, 0xaa, 0xa3, 0xc0, 0xff, 0x2a, 0xaa, 0x9f, 0xc0, 0xff, 0x69, 0xaa, 0x8f, 0xc0, 0xff, 0x65, 0xaa, 0x8f, 0xc0, 0xfc, 0xa4, 0xaa, 0x7f, 0xc0, 0xfd, 0xa0, 0xaa, 0x7f, 0xc0, 0xf2, 0xa3, 0x6a, 0x7f, 0xc0, 0xf2, 0x9f, 0x6a, 0x3f, 0xc0, 0xfa, 0x8f, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0};\r\nuint8_t v2[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0x6a, 0x7f, 0xc0, 0xff, 0xfd, 0xaa, 0x3f, 0xc0, 0xff, 0xf2, 0xaa, 0x3f, 0xc0, 0xff, 0xf6, 0xa9, 0xff, 0xc0, 0xff, 0xda, 0xa9, 0xff, 0xc0, 0xff, 0x2a, 0xa9, 0xff, 0xc0, 0xff, 0x6a, 0xa8, 0xff, 0xc0, 0xfc, 0xa4, 0xa8, 0xff, 0xc0, 0xfd, 0xa0, 0xa7, 0xff, 0xc0, 0xf2, 0x91, 0xa7, 0xff, 0xc0, 0xfa, 0x82, 0xa7, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0};\r\nuint8_t v3[] = { 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfa, 0xaa, 0xab, 0xc0, 0xff, 0xfa, 0xaa, 0xaf, 0xc0, 0xff, 0xfa, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xea, 0xbf, 0xff, 0xc0, 0xff, 0xea, 0xff, 0xff, 0xc0, 0xff, 0xea, 0xff, 0xff, 0xc0, 0xff, 0xaa, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0};\r\n\r\nuint8_t v4[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xaa, 0xff, 0xc0, 0xff, 0xff, 0xab, 0xff, 0xc0, 0xff, 0xfe, 0xab, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xff, 0xff, 0xc0, 0xff, 0xea, 0xff, 0xff, 0xc0, 0xff, 0xeb, 0xff, 0xff, 0xc0, 0xff, 0xeb, 0xff, 0xff, 0xc0, 0xff, 0xab, 0xea, 0xff, 0xc0, 0xff, 0xaa, 0xaa, 0xff, 0xc0, 0xff, 0xaa, 0xaa, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0 };\r\nuint8_t v5[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xea, 0xff, 0xc0, 0xff, 0xff, 0xea, 0xff, 0xc0, 0xff, 0xff, 0xeb, 0xff, 0xc0, 0xff, 0xff, 0xeb, 0xff, 0xc0, 0xff, 0xff, 0xab, 0xff, 0xc0, 0xff, 0xff, 0xaf, 0xff, 0xc0, 0xff, 0xff, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xbf, 0xff, 0xc0, 0xff, 0xfe, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0};\r\n\r\nuint8_t v6[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xaa, 0xaa, 0xc0, 0xff, 0xff, 0xaa, 0xaa, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfa, 0xaa, 0xff, 0xc0, 0xff, 0xfa, 0xab, 0xff, 0xc0, 0xff, 0xfa, 0xff, 0xff, 0xc0, 0xff, 0xea, 0xff, 0xff, 0xc0, 0xff, 0xea, 0xff, 0xff, 0xc0, 0xff, 0xea, 0xab, 0xff, 0xc0, 0xff, 0xaa, 0xab, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0};\r\nuint8_t v7[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xeb, 0xff, 0xc0, 0xff, 0xff, 0xab, 0xff, 0xc0, 0xff, 0xfe, 0xab, 0xff, 0xc0, 0xfe, 0xaa, 0xaa, 0xab, 0xc0, 0xff, 0xaa, 0xaa, 0xbf, 0xc0, 0xff, 0xea, 0xab, 0xff, 0xc0, 0xff, 0xea, 0xab, 0xff, 0xc0, 0xff, 0xaa, 0xab, 0xff, 0xc0, 0xff, 0xaf, 0xab, 0xff, 0xc0, 0xfe, 0xff, 0xeb, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0};\r\n\r\nuint8_t v[] =\r\n{ 0x0a, 0xaa, 0x55, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0-f\r\n 0x00, 0xaa, 0x55, 0x03, 0x03, 0x03, 0x00, 0x00, 0x10, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //10-f\r\n 0x40, 0x00, 0x00, 0xc4, 0x00, 0x00, 0xdc, 0x00, 0x00, 0x0f, 0x01, 0x00, 0x91, 0x01, 0x00, 0x0d, //20\r\n 0x02, 0x00, 0x89, 0x02, 0x00, 0xd1, 0x02, 0x00, 0x1f, 0x06, 0x00, 0x67, 0x0f, 0x00, 0x67, 0x0f,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //40\r\n 0x41, 0x12, 0x00, 0xa7, 0x12, 0x00, 0x0d, 0x13, 0x00, 0x73, 0x13, 0x00, 0xd9, 0x13, 0x00, 0x3f,\r\n 0x14, 0x00, 0xa5, 0x14, 0x00, 0x0b, 0x15, 0x00, 0x71, 0x15, 0x00, 0xd7, 0x15, 0x00, 0x3d, 0x16,\r\n 0x00, 0xa3, 0x16, 0x00, 0x09, 0x17, 0x00, 0x6f, 0x17, 0x00, 0xd5, 0x17, 0x00, 0x3b, 0x18, 0x00,\r\n 0xa1, 0x18, 0x00, 0x07, 0x19, 0x00, 0x6d, 0x19, 0x00, 0xd3, 0x19, 0x00, 0x39, 0x1a, 0x00, 0x9f, //80\r\n 0x1a, 0x00, 0x05, 0x1b, 0x00, 0x6b, 0x1b, 0x00, 0xd1, 0x1b, 0x00, 0x37, 0x1c, 0x00, 0x9d, 0x1c, //90\r\n 0x00, 0x13, 0x1e, 0x00, 0x89, 0x1f, 0x00, 0xff, 0x20, 0x00, 0x75, 0x22, 0x00, 0xeb, 0x23, 0x00,\r\n 0x61, 0x25, 0x00, 0xd7, 0x26, 0x00, 0x4d, 0x28, 0x00, 0xeb, 0x28, 0x00, 0x89, 0x29, 0x00, 0x64, //b0\r\n 0x2a, 0x00, 0xa2, 0x2a, 0x00, 0xe0, 0x2a, 0x00, 0x1e, 0x2b, 0x00, 0x5c, 0x2b, 0x00, 0xce, 0x00, //c0\r\n 0x00, 0xce, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x44, 0x12, 0x34, 0x30, 0x1f,// max:0x50, 0x20, //d0\r\n\r\n\r\n 0x2a, 0xaa, 0xaa, 0xaa, 0xa8, 0x1, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x2a, 0xaa, 0xaa, 0xaa, 0xa8, 0x0, 0x6a, 0xaa, 0xaa, 0xaa, 0xa9, 0x0, 0x2a, 0xaa, 0xaa, 0xaa, 0xa9, 0x0, 0x2a, 0xaa, 0xaa, 0xa0, 0x0, 0x0, 0x2a, 0xaa, 0xaa, 0xaa, 0xa9, 0x0, 0xa, 0x6a, 0xa8, 0x0, 0x0, 0x0, 0x2a, 0xaa, 0xaa, 0xaa, 0xa9, 0x0, 0x0, 0x2a, 0xaa, 0x0, 0x0, 0x0, 0x2a, 0xaa, 0xaa, 0xaa, 0xa8, 0x0, 0x0, 0x4, 0x0, 0x0, 0x0, 0x0, 0x2a, 0xaa, 0xaa, 0xaa, 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2a, 0xaa, 0xaa, 0xaa, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2a, 0xaa, 0xa4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2a, 0xaa, 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6a, 0xaa, 0x40, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6a, 0xaa, 0x40, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xaa, 0xaa, 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xaa, 0xaa, 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xaa, 0xaa, 0x80, 0x0, 0x0, 0x0, 0x0, 0x10, 0x0, 0x0, 0x0, 0x0, 0xaa, 0xaa, 0x90, 0x0, 0x0, 0x0, 0x0, 0x10, 0x0, 0x0, 0x0, 0x0, 0xaa, 0xaa, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x10, 0x0, 0x0, 0x0, 0x1, 0xaa, 0xaa, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x20, 0x0, 0x0, 0x0, 0x1, 0xaa, 0xaa, 0xa4, 0x0, 0x0, 0x0, 0x1a, 0xa0, 0x0, 0x0, 0x0, 0x2, 0xaa, 0xaa, 0xa8, 0x0, 0x0, 0x0, 0x11, 0x0, 0x0, 0x0, 0x0, 0x2, 0xaa, 0xaa, 0xa8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, 0xaa, 0xaa, 0xaa, 0x0, 0x0, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, 0xaa, 0xaa, 0xaa, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0x6a, 0xaa, 0xaa, 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1a, 0x2a, 0xaa, 0xaa, 0x80, 0x0, 0x0, 0x0, 0x0, 0xa4, 0x0, 0x0, 0x2a, 0x2a, 0xaa, 0xaa, 0xa0, 0x4, 0x2a, 0xaa, 0xaa, 0xa9, 0x0, 0x0, 0x6a, 0x2a, 0xaa, 0xaa, 0xa4, 0xa, 0xaa, 0xaa, 0xa9, 0x0, 0x0, 0x0, 0xaa, 0x2a, 0xaa, 0xaa, 0xa8, 0x0, 0x1a, 0xaa, 0x80, 0x0, 0x0, 0x1, 0xaa, 0x1a, 0xaa, 0xaa, 0xaa, 0x0, 0xa, 0xaa, 0x80, 0x0, 0x0, 0x2, 0xaa, 0xa, 0xaa, 0xaa, 0xaa, 0x80, 0xa, 0xaa, 0x90, 0x0, 0x0, 0x6, 0xaa, 0xa, 0xaa, 0xaa, 0xaa, 0x90, 0x1, 0xaa, 0xa4, 0x0, 0x0, 0x1a, 0xaa, 0x8a, 0xaa, 0x86, 0xa8, 0x24, 0x0, 0xaa, 0x50, 0x0, 0x0, 0x6a, 0xaa,\r\n\r\n\r\n\r\n // 0x0, 0xcf, 0xff, 0x0, 0x0, 0x0, 0x0, 0xcf, 0xff, 0x0, 0x0, 0x0, 0x0,\r\n // 0xcf, 0xff, 0x0, 0x0, 0xc, 0xff, 0xff, 0xff, 0x0, 0x0, 0xff, 0xff,\r\n // 0xff, 0xff, 0x0, 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n //0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n // 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n // 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0x0, 0x0, 0x0, 0x0, 0xC0, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF,\r\n 0x00, 0x00, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF,\r\n 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFA, 0xAA,\r\n 0xAB, 0xC0, 0xFF, 0xE5, 0x55, 0x5A, 0xC0, 0x00, 0xE5, 0x55, 0x5A, 0xC0, 0xFF, 0x95, 0x55, 0x66,\r\n 0xC0, 0xFF, 0xAA, 0xAA, 0xA6, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x8A, 0x28, 0x26, 0xC0,\r\n 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x8A, 0x28, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF,\r\n 0x80, 0x00, 0x26, 0xC0, 0xFF, 0xAA, 0xAA, 0xAB, 0xC0, 0x11, 0x15, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0,\r\n\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0x00, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF,\r\n 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFA, 0xAA, 0xAB, 0xC0, 0xFF, 0xE5, 0x55,\r\n 0x5A, 0xC0, 0xFF, 0xE5, 0x55, 0x5A, 0xC0, 0xFF, 0x95, 0x55, 0x66, 0xC0, 0xFF, 0xAA, 0xAA, 0xA6,\r\n 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x8A, 0x28, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0,\r\n 0xFF, 0x8A, 0x28, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF,\r\n 0xAA, 0xAA, 0xAB, 0xC0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};// 0x70, 0x2c, 0x00, 0x82, 0x2c, 0x00, 0x90, 0x2c, 0x00, 0x9e, 0x2c, 0x00, 0xb0, 0x2c, 0x00, 0xc2, 0x2c, 0x00, 0xd4, 0x2c, 0x00, 0xe6, 0x2c, 0x00, 0xe9, 0x2c, 0x00, 0x1b, 0x2d, 0x00, 0x4d, 0x2d, 0x00, 0x7f, 0x2d, 0x00, 0xb1, 0x2d, 0x00, 0xe3, 0x2d, 0x00, 0x15, 0x2e, 0x00, 0x27, 0x2e, 0x00, 0x39, 0x2e, 0x00, 0x4b, 0x2e, 0x00, 0x6c, 0x2e, 0x00, 0x73, 0x2e, 0x00, 0xb5, 0x2e, 0x00, 0xf7, 0x2e, 0x00, 0x21, 0x2f, 0x00, 0x5f, 0x2f, 0x00, 0xc1, 0x2f, 0x00, 0x02, 0x00, 0x06, 0x03, 0x04, 0x09, 0x0a, 0x05, 0x08, 0x07, 0x00, 0x00, 0x58, 0x00, 0x00, 0x32, 0x00, 0x00, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x10, 0x00, 0x00, 0x08, 0x00, 0x00, 0x50, 0x04, 0x00, 0x30, 0x02, 0x00, 0x20, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00, 0x50, 0x08, 0x00, 0x50, 0x11, 0x00, 0x00, 0x00, 0x28, 0x00, 0x40, 0x15, 0x00, 0x60, 0x12, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x45, 0x00, 0x00, 0x35, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x22, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00, 0x22, 0x00, 0x00, 0x13, 0x00, 0x01, 0x00, 0x02, 0x00, 0x50, 0x01, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x04, 0xff, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x02, 0xff, 0x01, 0x01, 0x00, 0x1e, 0x01, 0x00, 0x03, 0xff, 0x01, 0x01, 0x00, 0x2d, 0x01, 0x00, 0x04, 0xfe, 0x01, 0x01, 0x00, 0x3c, 0x01, 0x00, 0x05, 0xfe, 0x01, 0x01, 0x00, 0x4b, 0x02, 0x00, 0x06, 0xfe, 0x02, 0x02, 0x00, 0x5a, 0x02, 0x00, 0x07, 0xfd, 0x02, 0x02, 0x00, 0x63, 0x02, 0x00, 0x08, 0xfd, 0x02, 0x02, 0x00, 0x64, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0x00, 0x02, 0x04, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x02, 0xff, 0x01, 0x01, 0x00, 0x0f, 0x01, 0x00, 0x03, 0xff, 0x01, 0x01, 0x00, 0x19, 0x01, 0x00, 0x04, 0xfe, 0x01, 0x01, 0x00, 0x23, 0x01, 0x00, 0x05, 0xfe, 0x01, 0x02, 0x00, 0x2d, 0x02, 0x00, 0x06, 0xfe, 0x02, 0x02, 0x00, 0x37, 0x02, 0x00, 0x07, 0xfd, 0x02, 0x02, 0x00, 0x40, 0x02, 0x00, 0x08, 0xfd, 0x02, 0x02, 0x00, 0x41, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xc4, 0x2f, 0x00, 0xff, 0xff, 0xff, 0x06, 0x30, 0x00, 0x48, 0x30, 0x00, 0x8a, 0x30, 0x00, 0xcc, 0x30, 0x00, 0x0e, 0x31, 0x00, 0x50, 0x31, 0x00, 0x92, 0x31, 0x00, 0xd4, 0x31, 0x00, 0x16, 0x32, 0x00, 0xff, 0xff, 0xff, 0x58, 0x32, 0x00, 0xff, 0xff, 0xff, 0xba, 0x32, 0x00, 0x1c, 0x33, 0x00, 0x7e, 0x33, 0x00, 0xe0, 0x33, 0x00, 0x42, 0x34, 0x00, 0xa4, 0x34, 0x00, 0x06, 0x35, 0x00, 0x68, 0x35, 0x00, 0xca, 0x35, 0x00, 0xff, 0xff, 0xff, 0x2c, 0x36, 0x00, 0x3e, 0x36, 0x00, 0x80, 0x36, 0x00, 0xc2, 0x36, 0x00, 0x04, 0x37, 0x00, 0x46, 0x37, 0x00, 0x88, 0x37, 0x00, 0xca, 0x37, 0x00, 0x24, 0x38, 0x00, 0x9d, 0x38, 0x00, 0xf9, 0x38, 0x00, 0x7d, 0x39, 0x00, 0xd7, 0x39, 0x00, 0x50, 0x3a, 0x00, 0xac, 0x3a, 0x00, 0x30, 0x3b, 0x00, 0x72, 0x3b, 0x00, 0xb4, 0x3b, 0x00, 0xf6, 0x3b, 0x00, 0x38, 0x3c, 0x00, 0x7a, 0x3c, 0x00, 0xbc, 0x3c, 0x00, 0xfe, 0x3c, 0x00, 0x40, 0x3d, 0x00, 0x3a, 0x3e, 0x00, 0x34, 0x3f, 0x00, 0x2e, 0x40, 0x00, 0x28, 0x41, 0x00, 0x22, 0x42, 0x00, 0x98, 0x43, 0x00, 0xea, 0x43, 0x00, 0x3c, 0x44, 0x00, 0x8e, 0x44, 0x00, 0xe0, 0x44, 0x00, 0x32, 0x45, 0x00, 0x84, 0x45, 0x00, 0x7e, 0x46, 0x00, 0x78, 0x47, 0x00, 0xba, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0x76, 0x48, 0x00, 0xf0, 0x48, 0x00, 0x6a, 0x49, 0x00, 0xe4, 0x49, 0x00, 0x5e, 0x4a, 0x00, 0xd8, 0x4a, 0x00, 0x52, 0x4b, 0x00, 0xcc, 0x4b, 0x00, 0x46, 0x4c, 0x00, 0xc0, 0x4c, 0x00, 0x3a, 0x4d, 0x00, 0xb4, 0x4d, 0x00, 0x2e, 0x4e, 0x00, 0xa8, 0x4e, 0x00, 0x22, 0x4f, 0x00, 0x9c, 0x4f, 0x00, 0x16, 0x50, 0x00, 0x90, 0x50, 0x00, 0x0a, 0x51, 0x00, 0x84, 0x51, 0x00, 0xfe, 0x51, 0x00, 0x78, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0x6c, 0x53, 0x00, 0xe6, 0x53, 0x00, 0x60, 0x54, 0x00, 0xda, 0x54, 0x00, 0x54, 0x55, 0x00, 0xce, 0x55, 0x00, 0x48, 0x56, 0x00, 0xc2, 0x56, 0x00, 0x3c, 0x57, 0x00, 0xb6, 0x57, 0x00, 0x30, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0x24, 0x59, 0x00, 0x9e, 0x59, 0x00, 0x18, 0x5a, 0x00, 0x92, 0x5a, 0x00, 0x0c, 0x5b, 0x00, 0x86, 0x5b, 0x00, 0x00, 0x5c, 0x00, 0x7a, 0x5c, 0x00, 0xf4, 0x5c, 0x00, 0x6e, 0x5d, 0x00, 0xe8, 0x5d, 0x00, 0x62, 0x5e, 0x00, 0xdc, 0x5e, 0x00, 0x56, 0x5f, 0x00, 0xd0, 0x5f, 0x00, 0x4a, 0x60, 0x00, 0xc4, 0x60, 0x00, 0x3e, 0x61, 0x00, 0xb8, 0x61, 0x00, 0x32, 0x62, 0x00, 0xac, 0x62, 0x00, 0x26, 0x63, 0x00, 0xa0, 0x63, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x94, 0x64, 0x00, 0x0e, 0x65, 0x00, 0x88, 0x65, 0x00, 0x02, 0x66, 0x00, 0x7c, 0x66, 0x00, 0xf6, 0x66, 0x00, 0x70, 0x67, 0x00, 0xea, 0x67, 0x00, 0x64, 0x68, 0x00, 0xde, 0x68, 0x00, 0x58, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0x4c, 0x6a, 0x00, 0xc6, 0x6a, 0x00, 0x40, 0x6b, 0x00, 0xba, 0x6b, 0x00, 0x34, 0x6c, 0x00, 0xae, 0x6c, 0x00, 0x28, 0x6d, 0x00, 0xa2, 0x6d, 0x00, 0x1c, 0x6e, 0x00, 0x96, 0x6e, 0x00, 0x10, 0x6f, 0x00, 0x8a, 0x6f, 0x00, 0x04, 0x70, 0x00, 0x7e, 0x70, 0x00, 0xf8, 0x70, 0x00, 0x72, 0x71, 0x00, 0xec, 0x71, 0x00, 0x66, 0x72, 0x00, 0xe0, 0x72, 0x00, 0x5a, 0x73, 0x00, 0xd4, 0x73, 0x00, 0x4e, 0x74, 0x00, 0xc8, 0x74, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0xbc, 0x75, 0x00, 0x36, 0x76, 0x00, 0xb0, 0x76, 0x00, 0x2a, 0x77, 0x00, 0xa4, 0x77, 0x00, 0x1e, 0x78, 0x00, 0x98, 0x78, 0x00, 0x12, 0x79, 0x00, 0x8c, 0x79, 0x00, 0x06, 0x7a, 0x00, 0x80, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0x74, 0x7b, 0x00, 0xe2, 0x7b, 0x00, 0x50, 0x7c, 0x00, 0xbe, 0x7c, 0x00, 0x2c, 0x7d, 0x00, 0x9a, 0x7d, 0x00, 0x08, 0x7e, 0x00, 0x76, 0x7e, 0x00, 0xe4, 0x7e, 0x00, 0x52, 0x7f, 0x00, 0xc0, 0x7f, 0x00, 0x2e, 0x80, 0x00, 0x9c, 0x80, 0x00, 0x0a, 0x81, 0x00, 0x78, 0x81, 0x00, 0xe6, 0x81, 0x00, 0x54, 0x82, 0x00, 0xc2, 0x82, 0x00, 0x30, 0x83, 0x00, 0x9e, 0x83, 0x00, 0x0c, 0x84, 0x00, 0x7a, 0x84, 0x00, 0xe8, 0x84, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0xc4, 0x85, 0x00, 0x32, 0x86, 0x00, 0xa0, 0x86, 0x00, 0x0e, 0x87, 0x00, 0x7c, 0x87, 0x00, 0xea, 0x87, 0x00, 0x58, 0x88, 0x00, 0xc6, 0x88, 0x00, 0x34, 0x89, 0x00, 0xa2, 0x89, 0x00, 0x10, 0x8a, 0x00, 0x7e, 0x8a, 0x00, 0xec, 0x8a, 0x00, 0x2e, 0x8b, 0x00, 0xac, 0x8b, 0x00, 0x2a, 0x8c, 0x00, 0xa8, 0x8c, 0x00, 0x26, 0x8d, 0x00, 0xa4, 0x8d, 0x00, 0x22, 0x8e, 0x00, 0xa0, 0x8e, 0x00, 0x1e, 0x8f, 0x00, 0x60, 0x8f, 0x00, 0xa2, 0x8f, 0x00, 0xe4, 0x8f, 0x00, 0x13, 0x90, 0x00, 0x42, 0x90, 0x00, 0x65, 0x90, 0x00, 0x88, 0x90, 0x00, 0xab, 0x90, 0x00, 0xce, 0x90, 0x00, 0xf1, 0x90, 0x00, 0x57, 0x91, 0x00, 0xbd, 0x91, 0x00, 0x23, 0x92, 0x00, 0x89, 0x92, 0x00, 0xef, 0x92, 0x00, 0x55, 0x93, 0x00, 0xbb, 0x93, 0x00, 0x21, 0x94, 0x00, 0x87, 0x94, 0x00, 0xed, 0x94, 0x00, 0x53, 0x95, 0x00, 0xb9, 0x95, 0x00, 0x1f, 0x96, 0x00, 0x85, 0x96, 0x00, 0xeb, 0x96, 0x00, 0x51, 0x97, 0x00, 0xb7, 0x97, 0x00, 0x1d, 0x98, 0x00, 0x83, 0x98, 0x00, 0xe9, 0x98, 0x00, 0x4f, 0x99, 0x00, 0xb5, 0x99, 0x00, 0x1b, 0x9a, 0x00, 0x81, 0x9a, 0x00, 0xe7, 0x9a, 0x00, 0x4d, 0x9b, 0x00, 0xb3, 0x9b, 0x00, 0x19, 0x9c, 0x00, 0x7f, 0x9c, 0x00, 0xe5, 0x9c, 0x00, 0x4b, 0x9d, 0x00, 0xb1, 0x9d, 0x00, 0x17, 0x9e, 0x00, 0x7d, 0x9e, 0x00, 0xe3, 0x9e, 0x00, 0x49, 0x9f, 0x00, 0xaf, 0x9f, 0x00, 0x15, 0xa0, 0x00, 0x7b, 0xa0, 0x00, 0xe1, 0xa0, 0x00, 0x47, 0xa1, 0x00, 0xad, 0xa1, 0x00, 0x13, 0xa2, 0x00, 0x79, 0xa2, 0x00, 0xdf, 0xa2, 0x00, 0x45, 0xa3, 0x00, 0xab, 0xa3, 0x00, 0x11, 0xa4, 0x00, 0x77, 0xa4, 0x00, 0xdd, 0xa4, 0x00, 0x43, 0xa5, 0x00, 0xa9, 0xa5, 0x00, 0x0f, 0xa6, 0x00, 0x75, 0xa6, 0x00, 0xdb, 0xa6, 0x00, 0x41, 0xa7, 0x00, 0xa7, 0xa7, 0x00, 0x0d, 0xa8, 0x00, 0x73, 0xa8, 0x00, 0xd9, 0xa8, 0x00, 0x3f, 0xa9, 0x00, 0xa5, 0xa9, 0x00, 0x0b, 0xaa, 0x00, 0x71, 0xaa, 0x00, 0xd7, 0xaa, 0x00, 0x3d, 0xab, 0x00, 0xa3, 0xab, 0x00, 0x09, 0xac, 0x00, 0x6f, 0xac, 0x00, 0xd5, 0xac, 0x00, 0x3b, 0xad, 0x00, 0xa1, 0xad, 0x00, 0x07, 0xae, 0x00, 0x6d, 0xae, 0x00, 0xd3, 0xae, 0x00, 0x39, 0xaf, 0x00, 0x9f, 0xaf, 0x00, 0x05, 0xb0, 0x00, 0x6b, 0xb0, 0x00, 0xd1, 0xb0, 0x00, 0x37, 0xb1, 0x00, 0x9d, 0xb1, 0x00, 0x03, 0xb2, 0x00, 0x69, 0xb2, 0x00, 0xcf, 0xb2, 0x00, 0x35, 0xb3, 0x00, 0x9b, 0xb3, 0x00, 0x01, 0xb4, 0x00, 0x67, 0xb4, 0x00, 0xcd, 0xb4, 0x00, 0x33, 0xb5, 0x00, 0x99, 0xb5, 0x00, 0xff, 0xb5, 0x00, 0x65, 0xb6, 0x00, 0xcb, 0xb6, 0x00, 0x31, 0xb7, 0x00, 0x97, 0xb7, 0x00, 0xfd, 0xb7, 0x00, 0x63, 0xb8, 0x00, 0xc9, 0xb8, 0x00, 0x2f, 0xb9, 0x00, 0x95, 0xb9, 0x00, 0xfb, 0xb9, 0x00, 0x61, 0xba, 0x00, 0xc7, 0xba, 0x00, 0x2d, 0xbb, 0x00, 0x93, 0xbb, 0x00, 0xf9, 0xbb, 0x00, 0x5f, 0xbc, 0x00, 0xc5, 0xbc, 0x00, 0x2b, 0xbd, 0x00, 0x91, 0xbd, 0x00, 0xf7, 0xbd, 0x00, 0x5d, 0xbe, 0x00, 0xc3, 0xbe, 0x00, 0x29, 0xbf, 0x00, 0x8f, 0xbf, 0x00, 0xf5, 0xbf, 0x00, 0x5b, 0xc0, 0x00, 0xc1, 0xc0, 0x00, 0x27, 0xc1, 0x00, 0x8d, 0xc1, 0x00, 0xf3, 0xc1, 0x00, 0x59, 0xc2, 0x00, 0xbf, 0xc2, 0x00, 0x25, 0xc3, 0x00, 0x8b, 0xc3, 0x00, 0xf1, 0xc3, 0x00, 0x57, 0xc4, 0x00, 0xbd, 0xc4, 0x00, 0x23, 0xc5, 0x00, 0x89, 0xc5, 0x00, 0xef, 0xc5, 0x00, 0x55, 0xc6, 0x00, 0xbb, 0xc6, 0x00, 0x21, 0xc7, 0x00, 0x87, 0xc7, 0x00, 0xed, 0xc7, 0x00, 0x53, 0xc8, 0x00, 0xb9, 0xc8, 0x00, 0x1f, 0xc9, 0x00, 0x85, 0xc9, 0x00, 0xeb, 0xc9, 0x00, 0x51, 0xca, 0x00, 0xb7, 0xca, 0x00, 0x1d, 0xcb, 0x00, 0x83, 0xcb, 0x00, 0xe9, 0xcb, 0x00, 0x4f, 0xcc, 0x00, 0xb5, 0xcc, 0x00, 0x1b, 0xcd, 0x00, 0x81, 0xcd, 0x00, 0xe7, 0xcd, 0x00, 0x4d, 0xce, 0x00, 0xb3, 0xce, 0x00, 0x19, 0xcf, 0x00, 0x7f, 0xcf, 0x00, 0xe5, 0xcf, 0x00, 0x4b, 0xd0, 0x00, 0xb1, 0xd0, 0x00, 0x17, 0xd1, 0x00, 0x7d, 0xd1, 0x00, 0xe3, 0xd1, 0x00, 0x49, 0xd2, 0x00, 0xaf, 0xd2, 0x00, 0x15, 0xd3, 0x00, 0x7b, 0xd3, 0x00, 0xe1, 0xd3, 0x00, 0x47, 0xd4, 0x00, 0xad, 0xd4, 0x00, 0x13, 0xd5, 0x00, 0x79, 0xd5, 0x00, 0xdf, 0xd5, 0x00, 0x45, 0xd6, 0x00, 0xab, 0xd6, 0x00, 0x11, 0xd7, 0x00, 0x77, 0xd7, 0x00, 0xdd, 0xd7, 0x00, 0x43, 0xd8, 0x00, 0xa9, 0xd8, 0x00, 0x0f, 0xd9, 0x00, 0x75, 0xd9, 0x00, 0xdb, 0xd9, 0x00, 0x41, 0xda, 0x00, 0xa7, 0xda, 0x00, 0x0d, 0xdb, 0x00, 0x73, 0xdb, 0x00, 0xd9, 0xdb, 0x00, 0x3f, 0xdc, 0x00, 0xa5, 0xdc, 0x00, 0x0b, 0xdd, 0x00, 0x71, 0xdd, 0x00, 0xd7, 0xdd, 0x00, 0x3d, 0xde, 0x00, 0xa3, 0xde, 0x00, 0x09, 0xdf, 0x00, 0x6f, 0xdf, 0x00, 0xd5, 0xdf, 0x00, 0x3b, 0xe0, 0x00, 0xa1, 0xe0, 0x00, 0x07, 0xe1, 0x00, 0x6d, 0xe1, 0x00, 0xd3, 0xe1, 0x00, 0x39, 0xe2, 0x00, 0x9f, 0xe2, 0x00, 0x05, 0xe3, 0x00, 0x6b, 0xe3, 0x00, 0xd1, 0xe3, 0x00, 0x37, 0xe4, 0x00, 0x9d, 0xe4, 0x00, 0x03, 0xe5, 0x00, 0x69, 0xe5, 0x00, 0xcf, 0xe5, 0x00, 0x35, 0xe6, 0x00, 0x9b, 0xe6, 0x00, 0x01, 0xe7, 0x00, 0x67, 0xe7, 0x00, 0xcd, 0xe7, 0x00, 0x33, 0xe8, 0x00, 0x99, 0xe8, 0x00, 0xff, 0xe8, 0x00, 0x65, 0xe9, 0x00, 0xcb, 0xe9, 0x00, 0x31, 0xea, 0x00, 0x97, 0xea, 0x00, 0xfd, 0xea, 0x00, 0x63, 0xeb, 0x00, 0xc9, 0xeb, 0x00, 0x2f, 0xec, 0x00, 0x95, 0xec, 0x00, 0xfb, 0xec, 0x00, 0x61, 0xed, 0x00, 0xc7, 0xed, 0x00, 0x2d, 0xee, 0x00, 0x93, 0xee, 0x00, 0xf9, 0xee, 0x00, 0x5f, 0xef, 0x00, 0xc5, 0xef, 0x00, 0x2b, 0xf0, 0x00, 0x91, 0xf0, 0x00, 0xf7, 0xf0, 0x00, 0x5d, 0xf1, 0x00, 0xc3, 0xf1, 0x00, 0x29, 0xf2, 0x00, 0x8f, 0xf2, 0x00, 0xf5, 0xf2, 0x00, 0x5b, 0xf3, 0x00, 0xc1, 0xf3, 0x00, 0x27, 0xf4, 0x00, 0x8d, 0xf4, 0x00, 0xf3, 0xf4, 0x00, 0x59, 0xf5, 0x00, 0xbf, 0xf5, 0x00, 0x25, 0xf6, 0x00, 0x8b, 0xf6, 0x00, 0xf1, 0xf6, 0x00, 0x57, 0xf7, 0x00, 0xbd, 0xf7, 0x00, 0x23, 0xf8, 0x00, 0x89, 0xf8, 0x00, 0xef, 0xf8, 0x00, 0x55, 0xf9, 0x00, 0xbb, 0xf9, 0x00, 0x21, 0xfa, 0x00, 0x87, 0xfa, 0x00, 0xed, 0xfa, 0x00, 0x53, 0xfb, 0x00, 0xb9, 0xfb, 0x00, 0x1f, 0xfc, 0x00, 0x85, 0xfc, 0x00, 0xeb, 0xfc, 0x00, 0x51, 0xfd, 0x00, 0xb7, 0xfd, 0x00, 0x1d, 0xfe, 0x00, 0x83, 0xfe, 0x00, 0xe9, 0xfe, 0x00, 0x4f, 0xff, 0x00, 0xb5, 0xff, 0x00, 0x1b, 0x00, 0x01, 0x81, 0x00, 0x01, 0xe7, 0x00, 0x01, 0x4d, 0x01, 0x01, 0xb3, 0x01, 0x01, 0x19, 0x02, 0x01, 0x7f, 0x02, 0x01, 0xe5, 0x02, 0x01, 0x4b, 0x03, 0x01, 0xb1, 0x03, 0x01, 0x17, 0x04, 0x01, 0x7d, 0x04, 0x01, 0xe3, 0x04, 0x01, 0x49, 0x05, 0x01, 0xaf, 0x05, 0x01, 0x15, 0x06, 0x01, 0x7b, 0x06, 0x01, 0xe1, 0x06, 0x01, 0x47, 0x07, 0x01, 0xad, 0x07, 0x01, 0x13, 0x08, 0x01, 0x79, 0x08, 0x01, 0xdf, 0x08, 0x01, 0x45, 0x09, 0x01, 0xab, 0x09, 0x01, 0x11, 0x0a, 0x01, 0x77, 0x0a, 0x01, 0xdd, 0x0a, 0x01, 0x43, 0x0b, 0x01, 0xa9, 0x0b, 0x01, 0x0f, 0x0c, 0x01, 0x75, 0x0c, 0x01, 0xdb, 0x0c, 0x01, 0x41, 0x0d, 0x01, 0xa7, 0x0d, 0x01, 0x0d, 0x0e, 0x01, 0x73, 0x0e, 0x01, 0xd9, 0x0e, 0x01, 0x3f, 0x0f, 0x01, 0xa5, 0x0f, 0x01, 0x0b, 0x10, 0x01, 0x71, 0x10, 0x01, 0xd7, 0x10, 0x01, 0x3d, 0x11, 0x01, 0xa3, 0x11, 0x01, 0x09, 0x12, 0x01, 0x6f, 0x12, 0x01, 0xd5, 0x12, 0x01, 0x3b, 0x13, 0x01, 0xa1, 0x13, 0x01, 0x07, 0x14, 0x01, 0x6d, 0x14, 0x01, 0xd3, 0x14, 0x01, 0x39, 0x15, 0x01, 0x9f, 0x15, 0x01, 0x05, 0x16, 0x01, 0x6b, 0x16, 0x01, 0xd1, 0x16, 0x01, 0x37, 0x17, 0x01, 0x9d, 0x17, 0x01, 0x03, 0x18, 0x01, 0x69, 0x18, 0x01, 0xcf, 0x18, 0x01, 0x35, 0x19, 0x01, 0x9b, 0x19, 0x01, 0x01, 0x1a, 0x01, 0x67, 0x1a, 0x01, 0xcd, 0x1a, 0x01, 0x33, 0x1b, 0x01, 0x99, 0x1b, 0x01, 0xff, 0x1b, 0x01, 0x65, 0x1c, 0x01, 0xcb, 0x1c, 0x01, 0x31, 0x1d, 0x01, 0x97, 0x1d, 0x01, 0xfd, 0x1d, 0x01, 0x63, 0x1e, 0x01, 0xc9, 0x1e, 0x01, 0x2f, 0x1f, 0x01, 0x95, 0x1f, 0x01, 0xfb, 0x1f, 0x01, 0x61, 0x20, 0x01, 0xc7, 0x20, 0x01, 0x2d, 0x21, 0x01, 0x93, 0x21, 0x01, 0xf9, 0x21, 0x01, 0x5f, 0x22, 0x01, 0xc5, 0x22, 0x01, 0x2b, 0x23, 0x01, 0x91, 0x23, 0x01, 0xf7, 0x23, 0x01, 0x5d, 0x24, 0x01, 0xc3, 0x24, 0x01, 0x29, 0x25, 0x01, 0x8f, 0x25, 0x01, 0xf5, 0x25, 0x01, 0x5b, 0x26, 0x01, 0xc1, 0x26, 0x01, 0x27, 0x27, 0x01, 0x8d, 0x27, 0x01, 0xf3, 0x27, 0x01, 0x59, 0x28, 0x01, 0xbf, 0x28, 0x01, 0x25, 0x29, 0x01, 0x8b, 0x29, 0x01, 0xf1, 0x29, 0x01, 0x57, 0x2a, 0x01, 0xbd, 0x2a, 0x01, 0x23, 0x2b, 0x01, 0x89, 0x2b, 0x01, 0xef, 0x2b, 0x01, 0x55, 0x2c, 0x01, 0xbb, 0x2c, 0x01, 0x21, 0x2d, 0x01, 0x87, 0x2d, 0x01, 0xed, 0x2d, 0x01, 0x53, 0x2e, 0x01, 0xb9, 0x2e, 0x01, 0x1f, 0x2f, 0x01, 0x85, 0x2f, 0x01, 0xeb, 0x2f, 0x01, 0x51, 0x30, 0x01, 0xb7, 0x30, 0x01, 0x1d, 0x31, 0x01, 0x83, 0x31, 0x01, 0xe9, 0x31, 0x01, 0x4f, 0x32, 0x01, 0xb5, 0x32, 0x01, 0x1b, 0x33, 0x01, 0x81, 0x33, 0x01, 0xe7, 0x33, 0x01, 0x4d, 0x34, 0x01, 0xb3, 0x34, 0x01, 0x19, 0x35, 0x01, 0x7f, 0x35, 0x01, 0xe5, 0x35, 0x01, 0x4b, 0x36, 0x01, 0xb1, 0x36, 0x01, 0x17, 0x37, 0x01, 0x7d, 0x37, 0x01, 0xe3, 0x37, 0x01, 0x49, 0x38, 0x01, 0xaf, 0x38, 0x01, 0x15, 0x39, 0x01, 0x7b, 0x39, 0x01, 0xe1, 0x39, 0x01, 0x47, 0x3a, 0x01, 0xad, 0x3a, 0x01, 0x13, 0x3b, 0x01, 0x79, 0x3b, 0x01, 0xdf, 0x3b, 0x01, 0x45, 0x3c, 0x01, 0xab, 0x3c, 0x01, 0x11, 0x3d, 0x01, 0x77, 0x3d, 0x01, 0xdd, 0x3d, 0x01, 0x43, 0x3e, 0x01, 0xa9, 0x3e, 0x01, 0x0f, 0x3f, 0x01, 0x75, 0x3f, 0x01, 0xdb, 0x3f, 0x01, 0x41, 0x40, 0x01, 0xa7, 0x40, 0x01, 0x0d, 0x41, 0x01, 0x73, 0x41, 0x01, 0xd9, 0x41, 0x01, 0x3f, 0x42, 0x01, 0xa5, 0x42, 0x01, 0x0b, 0x43, 0x01, 0x71, 0x43, 0x01, 0xd7, 0x43, 0x01, 0x3d, 0x44, 0x01, 0xa3, 0x44, 0x01, 0x09, 0x45, 0x01, 0x6f, 0x45, 0x01, 0xd5, 0x45, 0x01, 0x3b, 0x46, 0x01, 0xa1, 0x46, 0x01, 0x07, 0x47, 0x01, 0x6d, 0x47, 0x01, 0xd3, 0x47, 0x01, 0x39, 0x48, 0x01, 0x9f, 0x48, 0x01, 0x05, 0x49, 0x01, 0x6b, 0x49, 0x01, 0xd1, 0x49, 0x01, 0x37, 0x4a, 0x01, 0x9d, 0x4a, 0x01, 0x03, 0x4b, 0x01, 0x69, 0x4b, 0x01, 0xcf, 0x4b, 0x01, 0x35, 0x4c, 0x01, 0x9b, 0x4c, 0x01, 0x01, 0x4d, 0x01, 0x67, 0x4d, 0x01, 0xcd, 0x4d, 0x01, 0x33, 0x4e, 0x01, 0x99, 0x4e, 0x01, 0xff, 0x4e, 0x01, 0x65, 0x4f, 0x01, 0xcb, 0x4f, 0x01, 0x31, 0x50, 0x01, 0x97, 0x50, 0x01, 0xfd, 0x50, 0x01, 0x63, 0x51, 0x01, 0xc9, 0x51, 0x01, 0x2f, 0x52, 0x01, 0x95, 0x52, 0x01, 0xfb, 0x52, 0x01, 0x61, 0x53, 0x01, 0xc7, 0x53, 0x01, 0x2d, 0x54, 0x01, 0x93, 0x54, 0x01, 0xf9, 0x54, 0x01, 0x5f, 0x55, 0x01, 0xc5, 0x55, 0x01, 0x2b, 0x56, 0x01, 0x91, 0x56, 0x01, 0xf7, 0x56, 0x01, 0x5d, 0x57, 0x01, 0xc3, 0x57, 0x01, 0x29, 0x58, 0x01, 0x8f, 0x58, 0x01, 0xf5, 0x58, 0x01, 0x5b, 0x59, 0x01, 0xc1, 0x59, 0x01, 0x27, 0x5a, 0x01, 0x8d, 0x5a, 0x01, 0xf3, 0x5a, 0x01, 0x59, 0x5b, 0x01, 0xbf, 0x5b, 0x01, 0x25, 0x5c, 0x01, 0x8b, 0x5c, 0x01, 0xf1, 0x5c, 0x01, 0x57, 0x5d, 0x01, 0xbd, 0x5d, 0x01, 0x23, 0x5e, 0x01, 0x89, 0x5e, 0x01, 0xef, 0x5e, 0x01, 0x55, 0x5f, 0x01, 0xbb, 0x5f, 0x01, 0x21, 0x60, 0x01, 0x87, 0x60, 0x01, 0xed, 0x60, 0x01, 0x53, 0x61, 0x01, 0xb9, 0x61, 0x01, 0x1f, 0x62, 0x01, 0x85, 0x62, 0x01, 0xeb, 0x62, 0x01, 0x51, 0x63, 0x01, 0xb7, 0x63, 0x01, 0x1d, 0x64, 0x01, 0x83, 0x64, 0x01, 0xe9, 0x64, 0x01, 0x4f, 0x65, 0x01, 0xb5, 0x65, 0x01, 0x1b, 0x66, 0x01, 0x81, 0x66, 0x01, 0xe7, 0x66, 0x01, 0x4d, 0x67, 0x01, 0xb3, 0x67, 0x01, 0x19, 0x68, 0x01, 0x7f, 0x68, 0x01, 0xe5, 0x68, 0x01, 0x4b, 0x69, 0x01, 0xb1, 0x69, 0x01, 0x17, 0x6a, 0x01, 0x7d, 0x6a, 0x01, 0xe3, 0x6a, 0x01, 0x49, 0x6b, 0x01, 0xaf, 0x6b, 0x01, 0x15, 0x6c, 0x01, 0x7b, 0x6c, 0x01, 0xe1, 0x6c, 0x01, 0x47, 0x6d, 0x01, 0xad, 0x6d, 0x01, 0x13, 0x6e, 0x01, 0x79, 0x6e, 0x01, 0xdf, 0x6e, 0x01, 0x45, 0x6f, 0x01, 0xab, 0x6f, 0x01, 0x11, 0x70, 0x01, 0x77, 0x70, 0x01, 0xdd, 0x70, 0x01, 0x43, 0x71, 0x01, 0xa9, 0x71, 0x01, 0x0f, 0x72, 0x01, 0x75, 0x72, 0x01, 0xdb, 0x72, 0x01, 0x41, 0x73, 0x01, 0xa7, 0x73, 0x01, 0x0d, 0x74, 0x01, 0x73, 0x74, 0x01, 0xd9, 0x74, 0x01, 0x3f, 0x75, 0x01, 0xa5, 0x75, 0x01, 0x0b, 0x76, 0x01, 0x71, 0x76, 0x01, 0xd7, 0x76, 0x01, 0x3d, 0x77, 0x01, 0xa3, 0x77, 0x01, 0x09, 0x78, 0x01, 0x6f, 0x78, 0x01, 0xd5, 0x78, 0x01, 0x3b, 0x79, 0x01, 0xa1, 0x79, 0x01, 0x07, 0x7a, 0x01, 0x6d, 0x7a, 0x01, 0xd3, 0x7a, 0x01, 0x39, 0x7b, 0x01, 0x9f, 0x7b, 0x01, 0x05, 0x7c, 0x01, 0x6b, 0x7c, 0x01, 0xd1, 0x7c, 0x01, 0x37, 0x7d, 0x01, 0x9d, 0x7d, 0x01, 0x03, 0x7e, 0x01, 0x69, 0x7e, 0x01, 0xcf, 0x7e, 0x01, 0x35, 0x7f, 0x01, 0x9b, 0x7f, 0x01, 0x01, 0x80, 0x01, 0x67, 0x80, 0x01, 0xcd, 0x80, 0x01, 0x33, 0x81, 0x01, 0x99, 0x81, 0x01, 0xff, 0x81, 0x01, 0x65, 0x82, 0x01, 0xcb, 0x82, 0x01, 0x31, 0x83, 0x01, 0x97, 0x83, 0x01, 0xfd, 0x83, 0x01, 0x63, 0x84, 0x01, 0xc9, 0x84, 0x01, 0x2f, 0x85, 0x01, 0x95, 0x85, 0x01, 0xfb, 0x85, 0x01, 0x61, 0x86, 0x01, 0xc7, 0x86, 0x01, 0x2d, 0x87, 0x01, 0x93, 0x87, 0x01, 0xf9, 0x87, 0x01, 0x5f, 0x88, 0x01, 0xc5, 0x88, 0x01, 0x2b, 0x89, 0x01, 0x91, 0x89, 0x01, 0xf7, 0x89, 0x01, 0x5d, 0x8a, 0x01, 0xc3, 0x8a, 0x01, 0x29, 0x8b, 0x01, 0x8f, 0x8b, 0x01, 0xf5, 0x8b, 0x01, 0x5b, 0x8c, 0x01, 0xc1, 0x8c, 0x01, 0x27, 0x8d, 0x01, 0x8d, 0x8d, 0x01, 0xf3, 0x8d, 0x01, 0x59, 0x8e, 0x01, 0xbf, 0x8e, 0x01, 0x25, 0x8f, 0x01, 0x8b, 0x8f, 0x01, 0xf1, 0x8f, 0x01, 0x57, 0x90, 0x01, 0xbd, 0x90, 0x01, 0x23, 0x91, 0x01, 0x89, 0x91, 0x01, 0xef, 0x91, 0x01, 0x55, 0x92, 0x01, 0xbb, 0x92, 0x01, 0x21, 0x93, 0x01, 0x87, 0x93, 0x01, 0xed, 0x93, 0x01, 0x53, 0x94, 0x01, 0xb9, 0x94, 0x01, 0x1f, 0x95, 0x01, 0x85, 0x95, 0x01, 0xeb, 0x95, 0x01, 0x51, 0x96, 0x01, 0xb7, 0x96, 0x01, 0x1d, 0x97, 0x01, 0x83, 0x97, 0x01, 0xe9, 0x97, 0x01, 0x4f, 0x98, 0x01, 0xb5, 0x98, 0x01, 0x1b, 0x99, 0x01, 0x81, 0x99, 0x01, 0xe7, 0x99, 0x01, 0x4d, 0x9a, 0x01, 0xb3, 0x9a, 0x01, 0x19, 0x9b, 0x01, 0x7f, 0x9b, 0x01, 0xe5, 0x9b, 0x01, 0x4b, 0x9c, 0x01, 0xb1, 0x9c, 0x01, 0x17, 0x9d, 0x01, 0x7d, 0x9d, 0x01, 0xe3, 0x9d, 0x01, 0x49, 0x9e, 0x01, 0xaf, 0x9e, 0x01, 0x15, 0x9f, 0x01, 0x7b, 0x9f, 0x01, 0xe1, 0x9f, 0x01, 0x47, 0xa0, 0x01, 0xad, 0xa0, 0x01, 0x13, 0xa1, 0x01, 0x79, 0xa1, 0x01, 0xdf, 0xa1, 0x01, 0x45, 0xa2, 0x01, 0xab, 0xa2, 0x01, 0x11, 0xa3, 0x01, 0x77, 0xa3, 0x01, 0xdd, 0xa3, 0x01, 0x43, 0xa4, 0x01, 0xa9, 0xa4, 0x01, 0x0f, 0xa5, 0x01, 0x75, 0xa5, 0x01, 0xdb, 0xa5, 0x01, 0x41, 0xa6, 0x01, 0xa7, 0xa6, 0x01, 0x0d, 0xa7, 0x01, 0x73, 0xa7, 0x01, 0xd9, 0xa7, 0x01, 0x3f, 0xa8, 0x01, 0xa5, 0xa8, 0x01, 0x0b, 0xa9, 0x01, 0x71, 0xa9, 0x01, 0xd7, 0xa9, 0x01, 0x3d, 0xaa, 0x01, 0xa3, 0xaa, 0x01, 0x09, 0xab, 0x01, 0x6f, 0xab, 0x01, 0xd5, 0xab, 0x01, 0x3b, 0xac, 0x01, 0xa1, 0xac, 0x01, 0x07, 0xad, 0x01, 0x6d, 0xad, 0x01, 0xd3, 0xad, 0x01, 0x39, 0xae, 0x01, 0x9f, 0xae, 0x01, 0x05, 0xaf, 0x01, 0x6b, 0xaf, 0x01, 0xd1, 0xaf, 0x01, 0x37, 0xb0, 0x01, 0x9d, 0xb0, 0x01, 0x03, 0xb1, 0x01, 0x69, 0xb1, 0x01, 0xcf, 0xb1, 0x01, 0x35, 0xb2, 0x01, 0x9b, 0xb2, 0x01, 0x01, 0xb3, 0x01, 0x67, 0xb3, 0x01, 0xcd, 0xb3, 0x01, 0x33, 0xb4, 0x01, 0x99, 0xb4, 0x01, 0xff, 0xb4, 0x01, 0x65, 0xb5, 0x01, 0xcb, 0xb5, 0x01, 0x31, 0xb6, 0x01, 0x97, 0xb6, 0x01, 0xfd, 0xb6, 0x01, 0x63, 0xb7, 0x01, 0xc9, 0xb7, 0x01, 0x2f, 0xb8, 0x01, 0x95, 0xb8, 0x01, 0xfb, 0xb8, 0x01, 0x61, 0xb9, 0x01, 0xc7, 0xb9, 0x01, 0x2d, 0xba, 0x01, 0x93, 0xba, 0x01, 0xf9, 0xba, 0x01, 0x5f, 0xbb, 0x01, 0xc5, 0xbb, 0x01, 0x2b, 0xbc, 0x01, 0x91, 0xbc, 0x01, 0xf7, 0xbc, 0x01, 0x5d, 0xbd, 0x01, 0xc3, 0xbd, 0x01, 0x29, 0xbe, 0x01, 0x8f, 0xbe, 0x01, 0xf5, 0xbe, 0x01, 0x5b, 0xbf, 0x01, 0xc1, 0xbf, 0x01, 0x27, 0xc0, 0x01, 0x8d, 0xc0, 0x01, 0xf3, 0xc0, 0x01, 0x59, 0xc1, 0x01, 0xbf, 0xc1, 0x01, 0x25, 0xc2, 0x01, 0x8b, 0xc2, 0x01, 0xf1, 0xc2, 0x01, 0x57, 0xc3, 0x01, 0xbd, 0xc3, 0x01, 0x23, 0xc4, 0x01, 0x89, 0xc4, 0x01, 0xef, 0xc4, 0x01, 0x55, 0xc5, 0x01, 0xbb, 0xc5, 0x01, 0x21, 0xc6, 0x01, 0x87, 0xc6, 0x01, 0xed, 0xc6, 0x01, 0x53, 0xc7, 0x01, 0xb9, 0xc7, 0x01, 0x1f, 0xc8, 0x01, 0x85, 0xc8, 0x01, 0xeb, 0xc8, 0x01, 0x51, 0xc9, 0x01, 0xb7, 0xc9, 0x01, 0x1d, 0xca, 0x01, 0x83, 0xca, 0x01, 0xe9, 0xca, 0x01, 0x4f, 0xcb, 0x01, 0xb5, 0xcb, 0x01, 0x1b, 0xcc, 0x01, 0x1f, 0x04, 0x07, 0x04, 0x04, 0x02, 0x03, 0x10, 0x00, 0x00, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x0a, 0x06, 0x00, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x10, 0x00, 0x00, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x1f, 0x00, 0x08, 0x00, 0x06, 0x00, 0x03, 0x0a, 0x06, 0x00, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x1e, 0x0b, 0x06, 0x04, 0x04, 0x03, 0x04, 0x0c, 0x04, 0x00, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x13, 0xf8, 0x01, 0x87, 0xf9, 0x01, 0x87, 0xf9, 0x01, 0x35, 0xee, 0x01, 0xa9, 0xf2, 0x01, 0xa9, 0xf2, 0x01, 0x35, 0xee, 0x01, 0xa9, 0xf2, 0x01, 0xa9, 0xf2, 0x01, 0x1e, 0x04, 0x0b, 0x04, 0x08, 0x02, 0x06, 0x04, 0x06, 0x06, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x18, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x0a, 0x06, 0x00, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x08, 0x04, 0x04, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0xb7, 0x11, 0x02, 0x21, 0x17, 0x02, 0x09, 0x1d, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x03, 0x05, 0x08, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0x7c, 0x00, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x73, 0x30, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xf0, 0x3c, 0x03, 0x55, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0xff, 0x00, 0x03, 0x55, 0x55, 0xff, 0x00, 0x3d, 0x55, 0x55, 0xff, 0x00, 0xcd, 0x55, 0x55, 0xcf, 0xff, 0x0d, 0x55, 0x55, 0x73, 0x30, 0x3d, 0x55, 0x55, 0x73, 0xf0, 0xf5, 0x55, 0x55, 0x73, 0xf0, 0x35, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x7f, 0x55, 0x57, 0xff, 0x55, 0xff, 0xd5, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x0f, 0x00, 0xf0, 0xd5, 0x57, 0x30, 0xc3, 0x0c, 0xd5, 0x57, 0x00, 0x3c, 0x00, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x57, 0x3f, 0xff, 0xfc, 0xd5, 0x57, 0xf0, 0xc3, 0x0f, 0xd5, 0x55, 0x73, 0xff, 0xcd, 0x55, 0x55, 0xc3, 0xff, 0xc3, 0x55, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x03, 0x00, 0xc0, 0xd5, 0x57, 0x0c, 0x00, 0x30, 0xd5, 0x57, 0x00, 0x3c, 0x00, 0xd5, 0x55, 0xc0, 0xff, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x3f, 0x0f, 0xc3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x00, 0xf0, 0x0d, 0x55, 0x55, 0xff, 0x0f, 0xf5, 0x55, 0x57, 0x33, 0xfc, 0xcd, 0x55, 0x57, 0xf3, 0xfc, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x30, 0x00, 0x0c, 0xd5, 0x57, 0x0c, 0x00, 0x30, 0xd5, 0x57, 0x00, 0xff, 0x00, 0xd5, 0x5f, 0x03, 0xff, 0xc0, 0xf5, 0x5c, 0xc3, 0xff, 0xc3, 0x35, 0x5f, 0x3f, 0xff, 0xfc, 0xf5, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0xc3, 0xff, 0xc3, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x7f, 0x55, 0x57, 0xff, 0x55, 0xff, 0xd5, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x03, 0x00, 0xc0, 0xd5, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x30, 0x3c, 0x0c, 0xd5, 0x55, 0xcc, 0x3c, 0x33, 0xd5, 0x55, 0xcc, 0x3c, 0x33, 0x55, 0x55, 0xc3, 0xc3, 0xc3, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xd7, 0xf5, 0x55, 0x55, 0x5f, 0x55, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x5c, 0x3f, 0xff, 0xc3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x55, 0xff, 0xff, 0xf5, 0x55, 0x55, 0xc0, 0x00, 0x35, 0x55, 0x57, 0x30, 0x00, 0xcd, 0x55, 0x57, 0xf0, 0x00, 0xfd, 0x55, 0x55, 0x70, 0x00, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0x55, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0x70, 0x00, 0x3d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x70, 0x0c, 0xd5, 0x55, 0x57, 0xc0, 0xfc, 0xd5, 0x55, 0x55, 0xf0, 0x3f, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0x57, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0x70, 0x00, 0x3d, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x30, 0xcd, 0x55, 0x55, 0xfc, 0x3f, 0xf5, 0x55, 0x55, 0x70, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x70, 0x3f, 0xf5, 0x55, 0x55, 0xc0, 0x0f, 0xf5, 0x55, 0x7f, 0xc0, 0x0f, 0xf5, 0x5f, 0xc0, 0xc0, 0x0f, 0x55, 0x5f, 0xc0, 0xc0, 0xcf, 0xd5, 0x55, 0xc0, 0xc0, 0xcf, 0xd5, 0x57, 0xc0, 0x3c, 0xcf, 0xf5, 0x5f, 0xfc, 0x03, 0x0f, 0xf5, 0x5f, 0xff, 0xff, 0xf7, 0xd5, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x3c, 0x03, 0xc3, 0x55, 0x5c, 0xc3, 0x0c, 0x33, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0xc3, 0x0c, 0x33, 0x55, 0x57, 0x30, 0xf0, 0xcc, 0xd5, 0x55, 0xff, 0xff, 0xf0, 0xd5, 0x55, 0x73, 0x0c, 0x03, 0x55, 0x55, 0xcc, 0xfc, 0x0d, 0x55, 0x55, 0xfc, 0xff, 0x0d, 0x55, 0x55, 0x5c, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x55, 0xf5, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x00, 0xc3, 0x00, 0xd5, 0x57, 0x3f, 0xc3, 0xfc, 0xd5, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x5c, 0xcc, 0x35, 0x55, 0x55, 0x73, 0xff, 0xcd, 0x55, 0x55, 0x70, 0xfc, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xc0, 0x30, 0x03, 0x55, 0x55, 0xc0, 0xc0, 0x03, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xfc, 0x00, 0x03, 0x55, 0x55, 0xff, 0x03, 0xc3, 0x55, 0x55, 0x7f, 0x03, 0x3d, 0x55, 0x55, 0x5f, 0xff, 0x35, 0x55, 0x55, 0x5c, 0xcc, 0x0d, 0x55, 0x55, 0x57, 0x3c, 0x03, 0x55, 0x55, 0x57, 0x3c, 0x3f, 0x55, 0x55, 0x57, 0xff, 0xf5, 0x55, 0x55, 0x55, 0x7d, 0xfd, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0x7f, 0x55, 0x55, 0x55, 0xff, 0xff, 0xd5, 0x55, 0x55, 0xff, 0xff, 0xd5, 0x55, 0x55, 0xff, 0x00, 0x35, 0x55, 0x57, 0xf0, 0x00, 0x3d, 0x55, 0x57, 0xc0, 0x03, 0x03, 0x55, 0x57, 0x00, 0x3c, 0x03, 0x55, 0x57, 0x00, 0x00, 0x0f, 0x55, 0x57, 0x00, 0x00, 0x35, 0x55, 0x57, 0xc0, 0x03, 0xd5, 0x55, 0x55, 0x7f, 0xff, 0x55, 0x55, 0x55, 0xc0, 0xcf, 0x55, 0x55, 0x57, 0x30, 0xfd, 0x55, 0x55, 0x57, 0xf0, 0xfd, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x7d, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xf5, 0x55, 0x55, 0x5f, 0xfd, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0x00, 0x0d, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x0f, 0xc3, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0x70, 0x00, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x5c, 0x3c, 0xd5, 0x55, 0x55, 0x5f, 0x0f, 0xd5, 0x55, 0x55, 0x5c, 0xff, 0xd5, 0x55, 0x55, 0x70, 0x0f, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3c, 0x0f, 0x55, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0xc0, 0x00, 0xff, 0x55, 0x55, 0xc0, 0xf0, 0xff, 0x55, 0x55, 0x70, 0xcc, 0xfd, 0x55, 0x55, 0x5f, 0xcf, 0xd5, 0x55, 0x55, 0x5c, 0xcc, 0xd5, 0x55, 0x55, 0x5c, 0x3f, 0xd5, 0x55, 0x55, 0x5c, 0x0f, 0xd5, 0x55, 0x55, 0x70, 0x0f, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x55, 0xfd, 0x55, 0x55, 0x7f, 0xdf, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0xc3, 0x55, 0x55, 0xcc, 0x00, 0x03, 0x55, 0x55, 0x73, 0x00, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x73, 0x30, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0x7f, 0x55, 0x55, 0xff, 0xd5, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0xd5, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0x70, 0x00, 0x03, 0x55, 0x55, 0xc3, 0x00, 0x30, 0xd5, 0x55, 0xcc, 0xc0, 0xcc, 0xd5, 0x55, 0xc3, 0x00, 0x30, 0xd5, 0x57, 0xc0, 0x3f, 0x00, 0xd5, 0x57, 0x30, 0xff, 0xc3, 0x55, 0x55, 0xcf, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xc3, 0xfc, 0x03, 0x55, 0x55, 0xc3, 0xfc, 0x3c, 0xd5, 0x55, 0x7f, 0xfc, 0x37, 0xd5, 0x55, 0x5f, 0x7f, 0xd5, 0x55, 0x55, 0x55, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x3c, 0x03, 0xc3, 0x55, 0x5c, 0xf3, 0x0f, 0x33, 0x55, 0x5c, 0xff, 0x0f, 0xf3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x0f, 0xf0, 0x0d, 0x55, 0x55, 0xfc, 0x3f, 0xf5, 0x55, 0x55, 0xc3, 0xcc, 0x3d, 0x55, 0x55, 0x70, 0xfc, 0xf3, 0x55, 0x55, 0x70, 0xfc, 0xdf, 0x55, 0x55, 0x7f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xcd, 0x55, 0x5f, 0xff, 0xff, 0xfd, 0x55, 0x7f, 0xff, 0xff, 0xd5, 0x55, 0x70, 0x00, 0x03, 0xd5, 0x55, 0xff, 0xff, 0xfc, 0xd5, 0x55, 0xc0, 0x00, 0x0f, 0xd5, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0x7c, 0x00, 0x0c, 0xd5, 0x55, 0x5f, 0xff, 0xf0, 0x35, 0x55, 0x7f, 0x3f, 0xfc, 0x0d, 0x55, 0x7f, 0x3f, 0xfc, 0x0d, 0x55, 0x70, 0x00, 0x3c, 0x0d, 0x55, 0x7f, 0xff, 0xf0, 0x0d, 0x55, 0x5f, 0xff, 0xdf, 0xf5, 0x55, 0x7f, 0xdf, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0x55, 0x55, 0x55, 0x57, 0x35, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0xff, 0xff, 0x55, 0x55, 0x5f, 0xff, 0xff, 0x55, 0x55, 0x70, 0x00, 0x0f, 0x55, 0x55, 0x7f, 0xff, 0xf3, 0xfd, 0x55, 0xc0, 0x00, 0x0c, 0xc3, 0x55, 0xc0, 0x00, 0x03, 0xc3, 0x55, 0xc0, 0x00, 0x03, 0x03, 0x55, 0xf0, 0x03, 0x03, 0xc3, 0x55, 0xc3, 0xc0, 0x0f, 0xc3, 0x55, 0xc3, 0xc0, 0x3f, 0x0d, 0x55, 0x7f, 0xff, 0xfc, 0x35, 0x5d, 0xff, 0x3f, 0xf3, 0xd5, 0x5f, 0x00, 0x00, 0xfd, 0x55, 0x5f, 0xff, 0xff, 0x3d, 0x55, 0x55, 0xff, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xff, 0x55, 0x55, 0x7f, 0xff, 0xff, 0xd5, 0x55, 0xf0, 0x00, 0x03, 0xf5, 0x55, 0xcf, 0xff, 0xfc, 0xf5, 0x55, 0xf0, 0x00, 0x03, 0xff, 0x57, 0x0f, 0xc0, 0xfc, 0xf3, 0x57, 0x33, 0xc3, 0x3c, 0xdf, 0x57, 0x33, 0xc3, 0x3c, 0xd5, 0x57, 0x0f, 0xc0, 0xfc, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x35, 0x55, 0xff, 0xff, 0xfc, 0x0d, 0x57, 0xff, 0xcf, 0xf3, 0x0d, 0x5c, 0xff, 0xcf, 0xff, 0x0d, 0x57, 0x70, 0x00, 0x0c, 0x0d, 0x55, 0x7f, 0xff, 0xf7, 0xf5, 0x55, 0x57, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xf7, 0xfd, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xff, 0xf5, 0x55, 0x70, 0x00, 0xff, 0xff, 0x55, 0x7f, 0xfc, 0x03, 0xf3, 0x55, 0xf0, 0xff, 0xf0, 0xdf, 0x55, 0xf0, 0xf3, 0x0f, 0xd5, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xff, 0xf0, 0x33, 0x55, 0x57, 0x3f, 0xc0, 0xff, 0xd5, 0x57, 0xcf, 0xff, 0xfc, 0x35, 0x55, 0xff, 0x3f, 0xfc, 0x0d, 0x55, 0x7f, 0x3f, 0xf0, 0x0d, 0x55, 0x7f, 0x3f, 0xf0, 0x0d, 0x55, 0x70, 0x00, 0xf0, 0x0d, 0x55, 0x5f, 0xff, 0xdf, 0xf5, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x55, 0xf7, 0xd5, 0x55, 0x30, 0x1f, 0x01, 0x55, 0x40, 0x00, 0x00, 0x00, 0x15, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x11, 0x41, 0x50, 0x00, 0x00, 0x15, 0x55, 0x55, 0x54, 0x04, 0x10, 0x01, 0x55, 0x41, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa1, 0x14, 0x15, 0x54, 0x01, 0x11, 0x45, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa5, 0x54, 0x15, 0x54, 0x01, 0x55, 0x45, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa1, 0x14, 0x44, 0x11, 0x55, 0x55, 0x55, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x15, 0x40, 0x01, 0x55, 0x11, 0x56, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x95, 0x40, 0x01, 0x55, 0x55, 0x56, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x95, 0x55, 0x55, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x55, 0x50, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x01, 0x50, 0x55, 0x50, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x15, 0x55, 0x55, 0x54, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x02, 0x55, 0x55, 0x55, 0x00, 0x04, 0x00, 0x80, 0x28, 0x00, 0x00, 0xa0, 0x02, 0x01, 0x15, 0x55, 0x10, 0x04, 0x55, 0x80, 0x28, 0x00, 0x00, 0xa0, 0x02, 0x01, 0x15, 0x55, 0x01, 0x55, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x02, 0x55, 0x55, 0x55, 0x01, 0x01, 0x00, 0x80, 0xaa, 0xaa, 0xaa, 0xa8, 0x02, 0x00, 0x04, 0x01, 0x01, 0x55, 0x00, 0x82, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x04, 0x01, 0x00, 0x41, 0x00, 0x82, 0xaa, 0xaa, 0xaa, 0xaa, 0x02, 0x00, 0x04, 0x01, 0x55, 0x5a, 0xa5, 0x80, 0x95, 0x95, 0x80, 0x00, 0x02, 0x55, 0x54, 0x01, 0x00, 0x25, 0x58, 0x80, 0x95, 0x95, 0x85, 0x54, 0x0a, 0xaa, 0xa8, 0x01, 0x00, 0x26, 0x98, 0x80, 0x95, 0x95, 0x85, 0x54, 0x08, 0x00, 0x09, 0x55, 0x00, 0x25, 0x58, 0x80, 0x95, 0x95, 0xaa, 0xaa, 0x08, 0x88, 0x88, 0x00, 0x00, 0x20, 0x08, 0x95, 0x95, 0x95, 0x80, 0x02, 0x58, 0x88, 0x88, 0x00, 0xaa, 0xa0, 0x0a, 0x95, 0x95, 0x95, 0x80, 0x02, 0x58, 0x00, 0x0a, 0xaa, 0x04, 0x20, 0x08, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa9, 0x55, 0x58, 0x00, 0x00, 0x0a, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xaa, 0xa9, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0x42, 0x82, 0x20, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa6, 0x86, 0x26, 0x62, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x45, 0x86, 0x24, 0xa4, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xa4, 0xa1, 0x61, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x61, 0x40, 0xa2, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0xaa, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa9, 0x55, 0x69, 0x55, 0x6a, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x9a, 0xa9, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x59, 0x59, 0x6a, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x98, 0x49, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x95, 0x55, 0xaa, 0x95, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa5, 0x56, 0xaa, 0x40, 0x68, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa8, 0x0a, 0xa5, 0x55, 0x58, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa9, 0x5a, 0xa5, 0x55, 0x58, 0x00, 0x95, 0x5a, 0x69, 0xa5, 0x56, 0x02, 0xa5, 0x96, 0xa9, 0x69, 0x68, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x96, 0x5a, 0x69, 0xa5, 0x96, 0x54, 0x54, 0x54, 0x54, 0x54, 0x55, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x54, 0x54, 0x54, 0x54, 0x54, 0x55, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x30, 0x1f, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x15, 0x00, 0x00, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x55, 0x00, 0x01, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x40, 0x51, 0x55, 0x55, 0x15, 0x54, 0x00, 0x00, 0x15, 0x54, 0x55, 0x55, 0x45, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x40, 0x00, 0x44, 0x11, 0x10, 0x11, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x44, 0x04, 0x44, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x40, 0x00, 0x44, 0x15, 0x05, 0x41, 0x50, 0x05, 0x55, 0x55, 0x50, 0x05, 0x41, 0x50, 0x54, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x50, 0x40, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x50, 0x40, 0x01, 0x00, 0x01, 0x00, 0x17, 0xfc, 0x3f, 0xfc, 0x00, 0x43, 0xff, 0xc0, 0x01, 0x00, 0x01, 0x00, 0x1f, 0xf4, 0xff, 0xd4, 0x00, 0x4f, 0xfc, 0x40, 0x01, 0x55, 0x55, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x40, 0x01, 0x11, 0x11, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x40, 0x01, 0x00, 0x01, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xc0, 0x01, 0x05, 0x41, 0x00, 0xf0, 0xfc, 0x03, 0xff, 0xff, 0x00, 0x00, 0xc0, 0x01, 0x05, 0x41, 0x00, 0xf0, 0xf3, 0x0c, 0x71, 0xc7, 0x33, 0x30, 0xc0, 0xaa, 0xaa, 0xaa, 0xaa, 0xf0, 0xf3, 0x0d, 0x75, 0xd7, 0x33, 0x30, 0xea, 0x55, 0x55, 0x55, 0x55, 0xf0, 0xfc, 0x0d, 0x34, 0xd3, 0x33, 0x30, 0xd5, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x0d, 0x34, 0xc3, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x03, 0xff, 0xff, 0xaa, 0xaa, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 0xc0, 0x00, 0xfc, 0x0f, 0xc0, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x3a, 0xbf, 0xfa, 0xab, 0xff, 0xbf, 0xfb, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0xff, 0xff, 0xcf, 0xfc, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf0, 0x03, 0xff, 0x3f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xc0, 0x00, 0xfc, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x55, 0x51, 0x55, 0x55, 0x15, 0x54, 0x00, 0x00, 0x15, 0x10, 0x00, 0x00, 0x40, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x40, 0x11, 0x10, 0x11, 0x10, 0x04, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x40, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x15, 0x55, 0x55, 0x40, 0x15, 0x05, 0x41, 0x50, 0x05, 0x55, 0x55, 0x50, 0x00, 0x00, 0x00, 0x00, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf5, 0xff, 0xf0, 0x00, 0x0f, 0xff, 0x00, 0x50, 0x50, 0x50, 0x50, 0x3f, 0xc3, 0xff, 0x00, 0x14, 0x3f, 0xf4, 0x14, 0x55, 0x50, 0x55, 0x50, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x54, 0x55, 0x50, 0x55, 0x50, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x54, 0x55, 0x55, 0x55, 0x53, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x54, 0x40, 0x10, 0x40, 0x13, 0xc3, 0xf0, 0x0f, 0xff, 0xfc, 0x00, 0x03, 0x04, 0x50, 0x50, 0x50, 0x53, 0xc3, 0xcc, 0x31, 0xc7, 0x1c, 0xcc, 0xc3, 0x14, 0x40, 0x10, 0x40, 0x13, 0xc3, 0xcc, 0x35, 0xd7, 0x5c, 0xcc, 0xc3, 0x04, 0xaa, 0xaa, 0xaa, 0xab, 0xc3, 0xf0, 0x34, 0xd3, 0x4c, 0xcc, 0xc3, 0xaa, 0x55, 0x55, 0x55, 0x57, 0x00, 0x00, 0x34, 0xd3, 0x0c, 0x00, 0x03, 0x55, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x0f, 0xff, 0xfe, 0xaa, 0xab, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x3f, 0x00, 0x03, 0xf0, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xea, 0xff, 0xea, 0xaf, 0xfe, 0xff, 0xec, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf3, 0xff, 0xff, 0x3f, 0xf3, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x0f, 0xfc, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x03, 0xf0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xfd, 0x7d, 0x7f, 0x5d, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x5d, 0xd5, 0xd7, 0x75, 0xdd, 0xd5, 0x55, 0x55, 0x55, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x30, 0xcc, 0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0xc0, 0xff, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xc0, 0xc3, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0x3f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xfc, 0x3f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x03, 0xc0, 0x30, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0xf3, 0xff, 0xff, 0xcf, 0x00, 0x00, 0x0f, 0xf0, 0x70, 0x0f, 0x55, 0x55, 0xc3, 0x0c, 0x30, 0xc3, 0x55, 0x55, 0xf0, 0x0d, 0xc3, 0x30, 0xd5, 0xff, 0x7c, 0xcf, 0xf3, 0x3d, 0xff, 0x57, 0x0c, 0xc3, 0xc0, 0x3f, 0x5f, 0x03, 0x57, 0xcf, 0xf3, 0xd5, 0xc0, 0xf5, 0xfc, 0x03, 0xc0, 0x30, 0xdc, 0x0d, 0x5f, 0xff, 0xff, 0xf5, 0x70, 0x37, 0x0c, 0x03, 0x7f, 0xff, 0x5f, 0xf5, 0x5f, 0x55, 0x55, 0xf5, 0x5f, 0xf5, 0xff, 0xfd, 0x30, 0x1f, 0xa4, 0x00, 0xa4, 0x01, 0x90, 0x00, 0x64, 0x06, 0x40, 0x1a, 0x00, 0x16, 0xa9, 0x40, 0x09, 0x00, 0x40, 0x00, 0x10, 0x01, 0x00, 0x60, 0x01, 0x6a, 0x2a, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xaa, 0x00, 0xa5, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x01, 0x6a, 0x80, 0x00, 0x01, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x30, 0xc0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x00, 0x05, 0x94, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x15, 0x56, 0xa5, 0x55, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x15, 0x40, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x29, 0x50, 0x15, 0x68, 0x00, 0x40, 0x07, 0xf0, 0x0f, 0xc0, 0x10, 0x00, 0x0a, 0xa5, 0x6a, 0x80, 0x01, 0x00, 0x1f, 0xfc, 0x3f, 0xf0, 0x04, 0x00, 0x00, 0xaa, 0xa8, 0x00, 0x15, 0x00, 0x1f, 0xff, 0xff, 0xf0, 0x05, 0x40, 0x00, 0x0a, 0xa0, 0x00, 0x04, 0x00, 0x5c, 0x00, 0x00, 0x30, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xf0, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xc0, 0x33, 0x00, 0x00, 0xcc, 0x03, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x30, 0x03, 0xc0, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x0c, 0x30, 0x03, 0xc0, 0x0c, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x3c, 0x03, 0xc0, 0x3c, 0xff, 0xc0, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0xc3, 0xff, 0xff, 0xc3, 0x00, 0x00, 0x0f, 0xf0, 0x30, 0x0c, 0x00, 0x00, 0xcc, 0x30, 0x0c, 0x33, 0x00, 0x00, 0x30, 0x0c, 0xc3, 0x0f, 0x00, 0x00, 0x3f, 0x3f, 0xfc, 0xfc, 0x00, 0x00, 0xf0, 0xc3, 0xc0, 0x30, 0xc0, 0x00, 0x03, 0x3f, 0xfc, 0xc0, 0x00, 0x03, 0x0c, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0xfc, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x3f, 0xfc, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x30, 0x30, 0xc0, 0x00, 0x00, 0x3c, 0x3c, 0x00, 0x00, 0x03, 0x0c, 0x0c, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x0c, 0x30, 0x00, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xfd, 0x7d, 0x7f, 0x5d, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x5d, 0xd5, 0xd7, 0x75, 0xdd, 0xd5, 0x55, 0x55, 0x55, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x30, 0xcc, 0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0xc0, 0xff, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xc0, 0xc3, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x70, 0x0f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xf0, 0x0d, 0xc3, 0x30, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x0c, 0xc3, 0xc0, 0x3f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfc, 0x03, 0xc0, 0x30, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x0c, 0x03, 0x7f, 0xff, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xfd, 0x30, 0x1f, 0xa4, 0x00, 0xa4, 0x01, 0x90, 0x00, 0x64, 0x06, 0x40, 0x1a, 0x00, 0x16, 0xa9, 0x40, 0x09, 0x00, 0x40, 0x00, 0x10, 0x01, 0x00, 0x60, 0x01, 0x6a, 0x2a, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xaa, 0x00, 0xa5, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x01, 0x6a, 0x80, 0x00, 0x01, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x30, 0xc0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x00, 0x05, 0x94, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x15, 0x56, 0xa5, 0x55, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x15, 0x40, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x29, 0x50, 0x15, 0x68, 0x00, 0x40, 0x04, 0x00, 0x04, 0x00, 0x10, 0x00, 0x0a, 0xa5, 0x6a, 0x80, 0x01, 0x00, 0x14, 0x00, 0x05, 0x00, 0x04, 0x00, 0x00, 0xaa, 0xa8, 0x00, 0x15, 0x00, 0x15, 0x00, 0x15, 0x00, 0x05, 0x40, 0x00, 0x0a, 0xa0, 0x00, 0x04, 0x00, 0x54, 0x00, 0x05, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x30, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0c, 0xc3, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xc3, 0xc0, 0x30, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x30, 0x30, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x0c, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xfc, 0x00, 0xc3, 0x0f, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xc3, 0x00, 0xc3, 0x30, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xcc, 0xc3, 0x00, 0xff, 0x30, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xfc, 0x00, 0xc3, 0x30, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xc0, 0x00, 0xc3, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x3f, 0x0f, 0xcf, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0xcc, 0x0c, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0xcf, 0xcf, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0x0f, 0xcf, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x30, 0xcc, 0x33, 0x0c, 0xfc, 0xfc, 0x00, 0x00, 0xc0, 0x00, 0x00, 0xc3, 0x30, 0xcf, 0x33, 0xcc, 0xc0, 0xc3, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc3, 0x30, 0xcc, 0xf3, 0x3c, 0xfc, 0xc3, 0x00, 0x00, 0xfc, 0x00, 0x00, 0xfc, 0x30, 0xcc, 0x33, 0x0c, 0xc0, 0xfc, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc3, 0x0f, 0x0c, 0x33, 0x0c, 0xfc, 0xc3, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x1f, 0x05, 0x55, 0x55, 0x55, 0x55, 0x55, 0x54, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x05, 0x54, 0x55, 0x45, 0x51, 0x10, 0x00, 0x04, 0x04, 0x55, 0x44, 0x51, 0x11, 0x55, 0x44, 0x04, 0x44, 0x44, 0x51, 0x11, 0x00, 0x44, 0x04, 0x44, 0x44, 0x51, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x00, 0x00, 0x00, 0x05, 0x41, 0x10, 0x00, 0x00, 0x00, 0x00, 0x04, 0x41, 0x10, 0x00, 0x00, 0x10, 0x55, 0x05, 0x41, 0x10, 0x54, 0x00, 0x55, 0x45, 0x10, 0x11, 0x11, 0x01, 0x40, 0x55, 0x54, 0x10, 0x11, 0x11, 0x00, 0x10, 0x55, 0x54, 0x15, 0x51, 0x11, 0x41, 0x11, 0x51, 0x10, 0x04, 0x41, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x50, 0x50, 0x00, 0x00, 0x10, 0x01, 0x10, 0x55, 0x50, 0x55, 0x00, 0x55, 0x01, 0x10, 0x44, 0x51, 0x00, 0x51, 0x00, 0x41, 0x10, 0x40, 0x11, 0x04, 0x41, 0x11, 0x41, 0x10, 0x15, 0x41, 0x00, 0x41, 0x00, 0x41, 0x10, 0x10, 0x41, 0x00, 0x40, 0x41, 0x01, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x55, 0x55, 0x55, 0x55, 0x55, 0x41, 0x10, 0x40, 0x00, 0x00, 0x00, 0x00, 0x41, 0x10, 0x55, 0x55, 0x55, 0x55, 0x55, 0x41, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x15, 0x50, 0x00, 0x00, 0x00, 0x01, 0x55, 0x12, 0x0c, 0x57, 0xf5, 0x7d, 0x55, 0x50, 0x5f, 0xfd, 0xff, 0x55, 0x50, 0x5f, 0xff, 0xff, 0x55, 0x50, 0x5f, 0xff, 0xff, 0xd5, 0x50, 0x7c, 0x00, 0x00, 0xd5, 0x50, 0x70, 0x0f, 0xc3, 0xd5, 0x50, 0x70, 0x33, 0xc3, 0xd5, 0x50, 0x70, 0x33, 0xc3, 0xd5, 0x50, 0x70, 0x0f, 0xc3, 0xd5, 0x50, 0x5c, 0x00, 0x0f, 0x55, 0x50, 0x57, 0xff, 0xfd, 0x55, 0x50, 0x5c, 0x3c, 0x33, 0x55, 0x50, 0x12, 0x0c, 0x55, 0xfd, 0x5f, 0x55, 0x50, 0x57, 0xff, 0x7f, 0xd5, 0x50, 0x57, 0xff, 0xff, 0xd5, 0x50, 0x57, 0xff, 0xff, 0xf5, 0x50, 0x5f, 0x00, 0x00, 0x35, 0x50, 0x5c, 0x03, 0xc0, 0x35, 0x50, 0x5c, 0x0c, 0x30, 0xf5, 0x50, 0x5c, 0x00, 0x00, 0x35, 0x50, 0x5c, 0x0c, 0x0f, 0xf5, 0x50, 0x57, 0x33, 0x0f, 0xd5, 0x50, 0x55, 0xf3, 0xff, 0x35, 0x50, 0x55, 0xc3, 0xc3, 0xf5, 0x50, 0x12, 0x0c, 0x5f, 0xd5, 0x7f, 0xff, 0xf0, 0x7f, 0xf5, 0xff, 0x00, 0x30, 0x7f, 0xff, 0xff, 0x00, 0x30, 0x7f, 0xff, 0xff, 0x00, 0x30, 0x70, 0x00, 0x03, 0x00, 0x30, 0xc3, 0xf0, 0x3f, 0x00, 0x30, 0xcc, 0xf0, 0xcf, 0x00, 0x30, 0xcc, 0xf0, 0xcf, 0x00, 0x30, 0xc3, 0xf0, 0x3f, 0xff, 0xf0, 0x70, 0x0f, 0x00, 0xcd, 0x50, 0x5f, 0xff, 0xff, 0x35, 0x50, 0x70, 0x30, 0x3c, 0xd5, 0x50, 0x12, 0x0c, 0x55, 0xfd, 0x57, 0xd5, 0x50, 0x57, 0xff, 0xdf, 0xf5, 0x50, 0x57, 0xff, 0xff, 0xfd, 0x50, 0x55, 0xff, 0xff, 0xfd, 0x50, 0x57, 0xc0, 0x00, 0x0d, 0x50, 0x57, 0x00, 0x00, 0x0d, 0x50, 0x57, 0x00, 0x00, 0x0d, 0x50, 0x57, 0x0f, 0xf0, 0x0d, 0x50, 0x57, 0x00, 0x00, 0xcd, 0x50, 0x55, 0xc0, 0x03, 0x35, 0x50, 0x55, 0x7f, 0xff, 0xd5, 0x50, 0x55, 0xc3, 0xc3, 0xd5, 0x50, 0x12, 0x0c, 0x57, 0xf5, 0x5f, 0xd5, 0x50, 0x5f, 0xfd, 0x7f, 0xf5, 0x50, 0x5f, 0xff, 0xff, 0xf5, 0x50, 0x5f, 0xff, 0xff, 0xf5, 0x50, 0x5c, 0x00, 0x00, 0x35, 0x50, 0x70, 0x00, 0x00, 0x0d, 0x50, 0x70, 0x30, 0x0c, 0x0d, 0x50, 0x70, 0xc0, 0x03, 0x0d, 0x50, 0x70, 0x03, 0xc0, 0x0d, 0x50, 0x5c, 0x0f, 0xf0, 0x35, 0x50, 0x57, 0xff, 0xff, 0xd5, 0x50, 0x55, 0xcc, 0x33, 0x55, 0x50, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfa, 0xaa, 0xab, 0xc0, 0xff, 0xe5, 0x55, 0x5a, 0xc0, 0xff, 0xe5, 0x55, 0x5a, 0xc0, 0xff, 0x95, 0x55, 0x66, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0xaa, 0xaa, 0xab, 0xc0, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfe, 0xaa, 0xaa, 0xc0, 0xff, 0xfe, 0x55, 0x56, 0xc0, 0xff, 0xfe, 0x55, 0x56, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xea, 0xaa, 0xaa, 0xc0, 0xff, 0xea, 0xaa, 0xaa, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0xaa, 0xaa, 0xab, 0xc0, 0x08, 0x08, 0x7f, 0xf5, 0xff, 0xfd, 0xc3, 0x0d, 0xff, 0xfd, 0xff, 0xfd, 0xfc, 0xfd, 0x7f, 0xf5, 0x77, 0x75, 0x10, 0x03, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xc0, 0x03, 0x03, 0xff, 0xff, 0xff, 0xff, 0x10, 0x03, 0x55, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x03, 0x55, 0x55, 0xff, 0xff, 0x55, 0x08, 0x08, 0x55, 0x75, 0x55, 0x75, 0x55, 0x75, 0x5f, 0x75, 0x70, 0xf5, 0x70, 0xd5, 0x5f, 0x55, 0x55, 0x55, 0x08, 0x08, 0x55, 0x75, 0x55, 0x75, 0x55, 0x75, 0x5f, 0x75, 0x7f, 0xf5, 0x7f, 0xd5, 0x5f, 0x55, 0x55, 0x55, 0x08, 0x08, 0x55, 0xd5, 0x55, 0xf5, 0x55, 0xfd, 0x7d, 0xdd, 0xff, 0xd5, 0xff, 0x55, 0x7d, 0x55, 0x55, 0x55, 0x08, 0x08, 0x5f, 0xfd, 0x5d, 0x5d, 0x5d, 0x5d, 0x5d, 0x5d, 0xfd, 0xfd, 0xfd, 0xfd, 0xf5, 0xf5, 0x55, 0x55, 0x01, 0x01, 0x00, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x7f, 0xfd, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x5f, 0xfd, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x7f, 0xfd, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x5f, 0xfd, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x7f, 0xfd, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0x03, 0x5f, 0xfd, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x08, 0x08, 0x50, 0x05, 0x43, 0xc1, 0x00, 0x00, 0x30, 0xcc, 0x33, 0x0c, 0x00, 0x00, 0x43, 0xc1, 0x50, 0x05, 0x08, 0x08, 0xc0, 0x03, 0x33, 0xcc, 0x00, 0x30, 0x33, 0x0c, 0x30, 0xcc, 0x0c, 0x00, 0x33, 0xcc, 0xc0, 0x03, 0x08, 0x08, 0x57, 0xd5, 0x5c, 0x35, 0x5c, 0x35, 0xdc, 0x37, 0xd7, 0xd7, 0xdf, 0xf7, 0xfd, 0x7f, 0xf7, 0xdf, 0x04, 0x1f, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x02, 0x05, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0x06, 0x20, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0x20, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf7, 0xff, 0x5f, 0x5f, 0xd7, 0xff, 0x75, 0x5d, 0x55, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x57, 0xd5, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x55, 0x75, 0x75, 0x7f, 0xdf, 0xd5, 0x75, 0x75, 0x55, 0x75, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x55, 0x5f, 0xd5, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x08, 0x7f, 0x5f, 0x57, 0xd7, 0x57, 0xd5, 0x75, 0xdd, 0x77, 0x57, 0xdf, 0x75, 0xdd, 0x77, 0x57, 0xd7, 0x75, 0xdf, 0xf7, 0x55, 0x7d, 0x5f, 0x5d, 0x77, 0xf7, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x0c, 0x7f, 0x5f, 0x5d, 0x5d, 0xfd, 0xd5, 0x75, 0xdf, 0x7d, 0xd5, 0xdf, 0x75, 0xdf, 0xfd, 0xfd, 0xd7, 0x7f, 0xdd, 0xdd, 0xd5, 0x7f, 0x75, 0xdd, 0x5d, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7d, 0x75, 0x77, 0xf7, 0xf5, 0xd7, 0x75, 0x77, 0x57, 0x5d, 0xd7, 0x5d, 0xd7, 0xf7, 0x5d, 0xd7, 0x5d, 0xd7, 0x57, 0xf5, 0x7d, 0x57, 0x57, 0xf7, 0x5d, 0x55, 0x55, 0x55, 0x55, 0x55, 0x20, 0x0c, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xff, 0x55, 0xc3, 0x7d, 0x55, 0x55, 0x55, 0x70, 0x00, 0xd5, 0x70, 0xff, 0x55, 0x55, 0x55, 0xc0, 0x00, 0x35, 0x7c, 0x3f, 0xd5, 0x55, 0x57, 0x00, 0x03, 0x0d, 0x5f, 0xff, 0xff, 0xff, 0xfc, 0x03, 0x00, 0x0d, 0x70, 0x00, 0x03, 0xc0, 0x00, 0x00, 0x3f, 0xfd, 0x7f, 0xff, 0xfc, 0x30, 0x00, 0x00, 0xc0, 0x03, 0xc0, 0x00, 0x03, 0x30, 0x00, 0x03, 0x0f, 0xfc, 0xc0, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc0, 0x03, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x01, 0x01, 0x00, 0x10, 0x10, 0x55, 0x7d, 0x55, 0xf5, 0x55, 0xc3, 0x57, 0x0d, 0x55, 0xc0, 0xdc, 0x0d, 0x55, 0x70, 0xdc, 0x3d, 0x55, 0x5c, 0x30, 0x35, 0x55, 0x70, 0x00, 0xd5, 0x55, 0xc3, 0xfc, 0xd5, 0x55, 0xcf, 0xff, 0x35, 0x57, 0x0f, 0xff, 0x35, 0x57, 0x00, 0xfc, 0x35, 0x57, 0xc0 };\r\n//uint8_t v[] = { 0x0a, 0xaa, 0x55, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x55, 0x03, 0x03, 0x03, 0x00, 0x00, 0x10, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0xc4, 0x00, 0x00, 0xdc, 0x00, 0x00, 0x0f, 0x01, 0x00, 0x91, 0x01, 0x00, 0x0d, 0x02, 0x00, 0x89, 0x02, 0x00, 0xd1, 0x02, 0x00, 0x1f, 0x06, 0x00, 0x67, 0x0f, 0x00, 0x67, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x12, 0x00, 0xa7, 0x12, 0x00, 0x0d, 0x13, 0x00, 0x73, 0x13, 0x00, 0xd9, 0x13, 0x00, 0x3f, 0x14, 0x00, 0xa5, 0x14, 0x00, 0x0b, 0x15, 0x00, 0x71, 0x15, 0x00, 0xd7, 0x15, 0x00, 0x3d, 0x16, 0x00, 0xa3, 0x16, 0x00, 0x09, 0x17, 0x00, 0x6f, 0x17, 0x00, 0xd5, 0x17, 0x00, 0x3b, 0x18, 0x00, 0xa1, 0x18, 0x00, 0x07, 0x19, 0x00, 0x6d, 0x19, 0x00, 0xd3, 0x19, 0x00, 0x39, 0x1a, 0x00, 0x9f, 0x1a, 0x00, 0x05, 0x1b, 0x00, 0x6b, 0x1b, 0x00, 0xd1, 0x1b, 0x00, 0x37, 0x1c, 0x00, 0x9d, 0x1c, 0x00, 0x13, 0x1e, 0x00, 0x89, 0x1f, 0x00, 0xff, 0x20, 0x00, 0x75, 0x22, 0x00, 0xeb, 0x23, 0x00, 0x61, 0x25, 0x00, 0xd7, 0x26, 0x00, 0x4d, 0x28, 0x00, 0xeb, 0x28, 0x00, 0x89, 0x29, 0x00, 0x64, 0x2a, 0x00, 0xa2, 0x2a, 0x00, 0xe0, 0x2a, 0x00, 0x1e, 0x2b, 0x00, 0x5c, 0x2b, 0x00, 0xce, 0x00, 0x00, 0xf1, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x44, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};// 0x70, 0x2c, 0x00, 0x82, 0x2c, 0x00, 0x90, 0x2c, 0x00, 0x9e, 0x2c, 0x00, 0xb0, 0x2c, 0x00, 0xc2, 0x2c, 0x00, 0xd4, 0x2c, 0x00, 0xe6, 0x2c, 0x00, 0xe9, 0x2c, 0x00, 0x1b, 0x2d, 0x00, 0x4d, 0x2d, 0x00, 0x7f, 0x2d, 0x00, 0xb1, 0x2d, 0x00, 0xe3, 0x2d, 0x00, 0x15, 0x2e, 0x00, 0x27, 0x2e, 0x00, 0x39, 0x2e, 0x00, 0x4b, 0x2e, 0x00, 0x6c, 0x2e, 0x00, 0x73, 0x2e, 0x00, 0xb5, 0x2e, 0x00, 0xf7, 0x2e, 0x00, 0x21, 0x2f, 0x00, 0x5f, 0x2f, 0x00, 0xc1, 0x2f, 0x00, 0x02, 0x00, 0x06, 0x03, 0x04, 0x09, 0x0a, 0x05, 0x08, 0x07, 0x00, 0x00, 0x58, 0x00, 0x00, 0x32, 0x00, 0x00, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x10, 0x00, 0x00, 0x08, 0x00, 0x00, 0x50, 0x04, 0x00, 0x30, 0x02, 0x00, 0x20, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00, 0x50, 0x08, 0x00, 0x50, 0x11, 0x00, 0x00, 0x00, 0x28, 0x00, 0x40, 0x15, 0x00, 0x60, 0x12, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x45, 0x00, 0x00, 0x35, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x22, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00, 0x22, 0x00, 0x00, 0x13, 0x00, 0x01, 0x00, 0x02, 0x00, 0x50, 0x01, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x04, 0xff, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x02, 0xff, 0x01, 0x01, 0x00, 0x1e, 0x01, 0x00, 0x03, 0xff, 0x01, 0x01, 0x00, 0x2d, 0x01, 0x00, 0x04, 0xfe, 0x01, 0x01, 0x00, 0x3c, 0x01, 0x00, 0x05, 0xfe, 0x01, 0x01, 0x00, 0x4b, 0x02, 0x00, 0x06, 0xfe, 0x02, 0x02, 0x00, 0x5a, 0x02, 0x00, 0x07, 0xfd, 0x02, 0x02, 0x00, 0x63, 0x02, 0x00, 0x08, 0xfd, 0x02, 0x02, 0x00, 0x64, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0x00, 0x02, 0x04, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x02, 0xff, 0x01, 0x01, 0x00, 0x0f, 0x01, 0x00, 0x03, 0xff, 0x01, 0x01, 0x00, 0x19, 0x01, 0x00, 0x04, 0xfe, 0x01, 0x01, 0x00, 0x23, 0x01, 0x00, 0x05, 0xfe, 0x01, 0x02, 0x00, 0x2d, 0x02, 0x00, 0x06, 0xfe, 0x02, 0x02, 0x00, 0x37, 0x02, 0x00, 0x07, 0xfd, 0x02, 0x02, 0x00, 0x40, 0x02, 0x00, 0x08, 0xfd, 0x02, 0x02, 0x00, 0x41, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xc4, 0x2f, 0x00, 0xff, 0xff, 0xff, 0x06, 0x30, 0x00, 0x48, 0x30, 0x00, 0x8a, 0x30, 0x00, 0xcc, 0x30, 0x00, 0x0e, 0x31, 0x00, 0x50, 0x31, 0x00, 0x92, 0x31, 0x00, 0xd4, 0x31, 0x00, 0x16, 0x32, 0x00, 0xff, 0xff, 0xff, 0x58, 0x32, 0x00, 0xff, 0xff, 0xff, 0xba, 0x32, 0x00, 0x1c, 0x33, 0x00, 0x7e, 0x33, 0x00, 0xe0, 0x33, 0x00, 0x42, 0x34, 0x00, 0xa4, 0x34, 0x00, 0x06, 0x35, 0x00, 0x68, 0x35, 0x00, 0xca, 0x35, 0x00, 0xff, 0xff, 0xff, 0x2c, 0x36, 0x00, 0x3e, 0x36, 0x00, 0x80, 0x36, 0x00, 0xc2, 0x36, 0x00, 0x04, 0x37, 0x00, 0x46, 0x37, 0x00, 0x88, 0x37, 0x00, 0xca, 0x37, 0x00, 0x24, 0x38, 0x00, 0x9d, 0x38, 0x00, 0xf9, 0x38, 0x00, 0x7d, 0x39, 0x00, 0xd7, 0x39, 0x00, 0x50, 0x3a, 0x00, 0xac, 0x3a, 0x00, 0x30, 0x3b, 0x00, 0x72, 0x3b, 0x00, 0xb4, 0x3b, 0x00, 0xf6, 0x3b, 0x00, 0x38, 0x3c, 0x00, 0x7a, 0x3c, 0x00, 0xbc, 0x3c, 0x00, 0xfe, 0x3c, 0x00, 0x40, 0x3d, 0x00, 0x3a, 0x3e, 0x00, 0x34, 0x3f, 0x00, 0x2e, 0x40, 0x00, 0x28, 0x41, 0x00, 0x22, 0x42, 0x00, 0x98, 0x43, 0x00, 0xea, 0x43, 0x00, 0x3c, 0x44, 0x00, 0x8e, 0x44, 0x00, 0xe0, 0x44, 0x00, 0x32, 0x45, 0x00, 0x84, 0x45, 0x00, 0x7e, 0x46, 0x00, 0x78, 0x47, 0x00, 0xba, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0x76, 0x48, 0x00, 0xf0, 0x48, 0x00, 0x6a, 0x49, 0x00, 0xe4, 0x49, 0x00, 0x5e, 0x4a, 0x00, 0xd8, 0x4a, 0x00, 0x52, 0x4b, 0x00, 0xcc, 0x4b, 0x00, 0x46, 0x4c, 0x00, 0xc0, 0x4c, 0x00, 0x3a, 0x4d, 0x00, 0xb4, 0x4d, 0x00, 0x2e, 0x4e, 0x00, 0xa8, 0x4e, 0x00, 0x22, 0x4f, 0x00, 0x9c, 0x4f, 0x00, 0x16, 0x50, 0x00, 0x90, 0x50, 0x00, 0x0a, 0x51, 0x00, 0x84, 0x51, 0x00, 0xfe, 0x51, 0x00, 0x78, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0x6c, 0x53, 0x00, 0xe6, 0x53, 0x00, 0x60, 0x54, 0x00, 0xda, 0x54, 0x00, 0x54, 0x55, 0x00, 0xce, 0x55, 0x00, 0x48, 0x56, 0x00, 0xc2, 0x56, 0x00, 0x3c, 0x57, 0x00, 0xb6, 0x57, 0x00, 0x30, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0x24, 0x59, 0x00, 0x9e, 0x59, 0x00, 0x18, 0x5a, 0x00, 0x92, 0x5a, 0x00, 0x0c, 0x5b, 0x00, 0x86, 0x5b, 0x00, 0x00, 0x5c, 0x00, 0x7a, 0x5c, 0x00, 0xf4, 0x5c, 0x00, 0x6e, 0x5d, 0x00, 0xe8, 0x5d, 0x00, 0x62, 0x5e, 0x00, 0xdc, 0x5e, 0x00, 0x56, 0x5f, 0x00, 0xd0, 0x5f, 0x00, 0x4a, 0x60, 0x00, 0xc4, 0x60, 0x00, 0x3e, 0x61, 0x00, 0xb8, 0x61, 0x00, 0x32, 0x62, 0x00, 0xac, 0x62, 0x00, 0x26, 0x63, 0x00, 0xa0, 0x63, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x94, 0x64, 0x00, 0x0e, 0x65, 0x00, 0x88, 0x65, 0x00, 0x02, 0x66, 0x00, 0x7c, 0x66, 0x00, 0xf6, 0x66, 0x00, 0x70, 0x67, 0x00, 0xea, 0x67, 0x00, 0x64, 0x68, 0x00, 0xde, 0x68, 0x00, 0x58, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0x4c, 0x6a, 0x00, 0xc6, 0x6a, 0x00, 0x40, 0x6b, 0x00, 0xba, 0x6b, 0x00, 0x34, 0x6c, 0x00, 0xae, 0x6c, 0x00, 0x28, 0x6d, 0x00, 0xa2, 0x6d, 0x00, 0x1c, 0x6e, 0x00, 0x96, 0x6e, 0x00, 0x10, 0x6f, 0x00, 0x8a, 0x6f, 0x00, 0x04, 0x70, 0x00, 0x7e, 0x70, 0x00, 0xf8, 0x70, 0x00, 0x72, 0x71, 0x00, 0xec, 0x71, 0x00, 0x66, 0x72, 0x00, 0xe0, 0x72, 0x00, 0x5a, 0x73, 0x00, 0xd4, 0x73, 0x00, 0x4e, 0x74, 0x00, 0xc8, 0x74, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0xbc, 0x75, 0x00, 0x36, 0x76, 0x00, 0xb0, 0x76, 0x00, 0x2a, 0x77, 0x00, 0xa4, 0x77, 0x00, 0x1e, 0x78, 0x00, 0x98, 0x78, 0x00, 0x12, 0x79, 0x00, 0x8c, 0x79, 0x00, 0x06, 0x7a, 0x00, 0x80, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0x74, 0x7b, 0x00, 0xe2, 0x7b, 0x00, 0x50, 0x7c, 0x00, 0xbe, 0x7c, 0x00, 0x2c, 0x7d, 0x00, 0x9a, 0x7d, 0x00, 0x08, 0x7e, 0x00, 0x76, 0x7e, 0x00, 0xe4, 0x7e, 0x00, 0x52, 0x7f, 0x00, 0xc0, 0x7f, 0x00, 0x2e, 0x80, 0x00, 0x9c, 0x80, 0x00, 0x0a, 0x81, 0x00, 0x78, 0x81, 0x00, 0xe6, 0x81, 0x00, 0x54, 0x82, 0x00, 0xc2, 0x82, 0x00, 0x30, 0x83, 0x00, 0x9e, 0x83, 0x00, 0x0c, 0x84, 0x00, 0x7a, 0x84, 0x00, 0xe8, 0x84, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0xc4, 0x85, 0x00, 0x32, 0x86, 0x00, 0xa0, 0x86, 0x00, 0x0e, 0x87, 0x00, 0x7c, 0x87, 0x00, 0xea, 0x87, 0x00, 0x58, 0x88, 0x00, 0xc6, 0x88, 0x00, 0x34, 0x89, 0x00, 0xa2, 0x89, 0x00, 0x10, 0x8a, 0x00, 0x7e, 0x8a, 0x00, 0xec, 0x8a, 0x00, 0x2e, 0x8b, 0x00, 0xac, 0x8b, 0x00, 0x2a, 0x8c, 0x00, 0xa8, 0x8c, 0x00, 0x26, 0x8d, 0x00, 0xa4, 0x8d, 0x00, 0x22, 0x8e, 0x00, 0xa0, 0x8e, 0x00, 0x1e, 0x8f, 0x00, 0x60, 0x8f, 0x00, 0xa2, 0x8f, 0x00, 0xe4, 0x8f, 0x00, 0x13, 0x90, 0x00, 0x42, 0x90, 0x00, 0x65, 0x90, 0x00, 0x88, 0x90, 0x00, 0xab, 0x90, 0x00, 0xce, 0x90, 0x00, 0xf1, 0x90, 0x00, 0x57, 0x91, 0x00, 0xbd, 0x91, 0x00, 0x23, 0x92, 0x00, 0x89, 0x92, 0x00, 0xef, 0x92, 0x00, 0x55, 0x93, 0x00, 0xbb, 0x93, 0x00, 0x21, 0x94, 0x00, 0x87, 0x94, 0x00, 0xed, 0x94, 0x00, 0x53, 0x95, 0x00, 0xb9, 0x95, 0x00, 0x1f, 0x96, 0x00, 0x85, 0x96, 0x00, 0xeb, 0x96, 0x00, 0x51, 0x97, 0x00, 0xb7, 0x97, 0x00, 0x1d, 0x98, 0x00, 0x83, 0x98, 0x00, 0xe9, 0x98, 0x00, 0x4f, 0x99, 0x00, 0xb5, 0x99, 0x00, 0x1b, 0x9a, 0x00, 0x81, 0x9a, 0x00, 0xe7, 0x9a, 0x00, 0x4d, 0x9b, 0x00, 0xb3, 0x9b, 0x00, 0x19, 0x9c, 0x00, 0x7f, 0x9c, 0x00, 0xe5, 0x9c, 0x00, 0x4b, 0x9d, 0x00, 0xb1, 0x9d, 0x00, 0x17, 0x9e, 0x00, 0x7d, 0x9e, 0x00, 0xe3, 0x9e, 0x00, 0x49, 0x9f, 0x00, 0xaf, 0x9f, 0x00, 0x15, 0xa0, 0x00, 0x7b, 0xa0, 0x00, 0xe1, 0xa0, 0x00, 0x47, 0xa1, 0x00, 0xad, 0xa1, 0x00, 0x13, 0xa2, 0x00, 0x79, 0xa2, 0x00, 0xdf, 0xa2, 0x00, 0x45, 0xa3, 0x00, 0xab, 0xa3, 0x00, 0x11, 0xa4, 0x00, 0x77, 0xa4, 0x00, 0xdd, 0xa4, 0x00, 0x43, 0xa5, 0x00, 0xa9, 0xa5, 0x00, 0x0f, 0xa6, 0x00, 0x75, 0xa6, 0x00, 0xdb, 0xa6, 0x00, 0x41, 0xa7, 0x00, 0xa7, 0xa7, 0x00, 0x0d, 0xa8, 0x00, 0x73, 0xa8, 0x00, 0xd9, 0xa8, 0x00, 0x3f, 0xa9, 0x00, 0xa5, 0xa9, 0x00, 0x0b, 0xaa, 0x00, 0x71, 0xaa, 0x00, 0xd7, 0xaa, 0x00, 0x3d, 0xab, 0x00, 0xa3, 0xab, 0x00, 0x09, 0xac, 0x00, 0x6f, 0xac, 0x00, 0xd5, 0xac, 0x00, 0x3b, 0xad, 0x00, 0xa1, 0xad, 0x00, 0x07, 0xae, 0x00, 0x6d, 0xae, 0x00, 0xd3, 0xae, 0x00, 0x39, 0xaf, 0x00, 0x9f, 0xaf, 0x00, 0x05, 0xb0, 0x00, 0x6b, 0xb0, 0x00, 0xd1, 0xb0, 0x00, 0x37, 0xb1, 0x00, 0x9d, 0xb1, 0x00, 0x03, 0xb2, 0x00, 0x69, 0xb2, 0x00, 0xcf, 0xb2, 0x00, 0x35, 0xb3, 0x00, 0x9b, 0xb3, 0x00, 0x01, 0xb4, 0x00, 0x67, 0xb4, 0x00, 0xcd, 0xb4, 0x00, 0x33, 0xb5, 0x00, 0x99, 0xb5, 0x00, 0xff, 0xb5, 0x00, 0x65, 0xb6, 0x00, 0xcb, 0xb6, 0x00, 0x31, 0xb7, 0x00, 0x97, 0xb7, 0x00, 0xfd, 0xb7, 0x00, 0x63, 0xb8, 0x00, 0xc9, 0xb8, 0x00, 0x2f, 0xb9, 0x00, 0x95, 0xb9, 0x00, 0xfb, 0xb9, 0x00, 0x61, 0xba, 0x00, 0xc7, 0xba, 0x00, 0x2d, 0xbb, 0x00, 0x93, 0xbb, 0x00, 0xf9, 0xbb, 0x00, 0x5f, 0xbc, 0x00, 0xc5, 0xbc, 0x00, 0x2b, 0xbd, 0x00, 0x91, 0xbd, 0x00, 0xf7, 0xbd, 0x00, 0x5d, 0xbe, 0x00, 0xc3, 0xbe, 0x00, 0x29, 0xbf, 0x00, 0x8f, 0xbf, 0x00, 0xf5, 0xbf, 0x00, 0x5b, 0xc0, 0x00, 0xc1, 0xc0, 0x00, 0x27, 0xc1, 0x00, 0x8d, 0xc1, 0x00, 0xf3, 0xc1, 0x00, 0x59, 0xc2, 0x00, 0xbf, 0xc2, 0x00, 0x25, 0xc3, 0x00, 0x8b, 0xc3, 0x00, 0xf1, 0xc3, 0x00, 0x57, 0xc4, 0x00, 0xbd, 0xc4, 0x00, 0x23, 0xc5, 0x00, 0x89, 0xc5, 0x00, 0xef, 0xc5, 0x00, 0x55, 0xc6, 0x00, 0xbb, 0xc6, 0x00, 0x21, 0xc7, 0x00, 0x87, 0xc7, 0x00, 0xed, 0xc7, 0x00, 0x53, 0xc8, 0x00, 0xb9, 0xc8, 0x00, 0x1f, 0xc9, 0x00, 0x85, 0xc9, 0x00, 0xeb, 0xc9, 0x00, 0x51, 0xca, 0x00, 0xb7, 0xca, 0x00, 0x1d, 0xcb, 0x00, 0x83, 0xcb, 0x00, 0xe9, 0xcb, 0x00, 0x4f, 0xcc, 0x00, 0xb5, 0xcc, 0x00, 0x1b, 0xcd, 0x00, 0x81, 0xcd, 0x00, 0xe7, 0xcd, 0x00, 0x4d, 0xce, 0x00, 0xb3, 0xce, 0x00, 0x19, 0xcf, 0x00, 0x7f, 0xcf, 0x00, 0xe5, 0xcf, 0x00, 0x4b, 0xd0, 0x00, 0xb1, 0xd0, 0x00, 0x17, 0xd1, 0x00, 0x7d, 0xd1, 0x00, 0xe3, 0xd1, 0x00, 0x49, 0xd2, 0x00, 0xaf, 0xd2, 0x00, 0x15, 0xd3, 0x00, 0x7b, 0xd3, 0x00, 0xe1, 0xd3, 0x00, 0x47, 0xd4, 0x00, 0xad, 0xd4, 0x00, 0x13, 0xd5, 0x00, 0x79, 0xd5, 0x00, 0xdf, 0xd5, 0x00, 0x45, 0xd6, 0x00, 0xab, 0xd6, 0x00, 0x11, 0xd7, 0x00, 0x77, 0xd7, 0x00, 0xdd, 0xd7, 0x00, 0x43, 0xd8, 0x00, 0xa9, 0xd8, 0x00, 0x0f, 0xd9, 0x00, 0x75, 0xd9, 0x00, 0xdb, 0xd9, 0x00, 0x41, 0xda, 0x00, 0xa7, 0xda, 0x00, 0x0d, 0xdb, 0x00, 0x73, 0xdb, 0x00, 0xd9, 0xdb, 0x00, 0x3f, 0xdc, 0x00, 0xa5, 0xdc, 0x00, 0x0b, 0xdd, 0x00, 0x71, 0xdd, 0x00, 0xd7, 0xdd, 0x00, 0x3d, 0xde, 0x00, 0xa3, 0xde, 0x00, 0x09, 0xdf, 0x00, 0x6f, 0xdf, 0x00, 0xd5, 0xdf, 0x00, 0x3b, 0xe0, 0x00, 0xa1, 0xe0, 0x00, 0x07, 0xe1, 0x00, 0x6d, 0xe1, 0x00, 0xd3, 0xe1, 0x00, 0x39, 0xe2, 0x00, 0x9f, 0xe2, 0x00, 0x05, 0xe3, 0x00, 0x6b, 0xe3, 0x00, 0xd1, 0xe3, 0x00, 0x37, 0xe4, 0x00, 0x9d, 0xe4, 0x00, 0x03, 0xe5, 0x00, 0x69, 0xe5, 0x00, 0xcf, 0xe5, 0x00, 0x35, 0xe6, 0x00, 0x9b, 0xe6, 0x00, 0x01, 0xe7, 0x00, 0x67, 0xe7, 0x00, 0xcd, 0xe7, 0x00, 0x33, 0xe8, 0x00, 0x99, 0xe8, 0x00, 0xff, 0xe8, 0x00, 0x65, 0xe9, 0x00, 0xcb, 0xe9, 0x00, 0x31, 0xea, 0x00, 0x97, 0xea, 0x00, 0xfd, 0xea, 0x00, 0x63, 0xeb, 0x00, 0xc9, 0xeb, 0x00, 0x2f, 0xec, 0x00, 0x95, 0xec, 0x00, 0xfb, 0xec, 0x00, 0x61, 0xed, 0x00, 0xc7, 0xed, 0x00, 0x2d, 0xee, 0x00, 0x93, 0xee, 0x00, 0xf9, 0xee, 0x00, 0x5f, 0xef, 0x00, 0xc5, 0xef, 0x00, 0x2b, 0xf0, 0x00, 0x91, 0xf0, 0x00, 0xf7, 0xf0, 0x00, 0x5d, 0xf1, 0x00, 0xc3, 0xf1, 0x00, 0x29, 0xf2, 0x00, 0x8f, 0xf2, 0x00, 0xf5, 0xf2, 0x00, 0x5b, 0xf3, 0x00, 0xc1, 0xf3, 0x00, 0x27, 0xf4, 0x00, 0x8d, 0xf4, 0x00, 0xf3, 0xf4, 0x00, 0x59, 0xf5, 0x00, 0xbf, 0xf5, 0x00, 0x25, 0xf6, 0x00, 0x8b, 0xf6, 0x00, 0xf1, 0xf6, 0x00, 0x57, 0xf7, 0x00, 0xbd, 0xf7, 0x00, 0x23, 0xf8, 0x00, 0x89, 0xf8, 0x00, 0xef, 0xf8, 0x00, 0x55, 0xf9, 0x00, 0xbb, 0xf9, 0x00, 0x21, 0xfa, 0x00, 0x87, 0xfa, 0x00, 0xed, 0xfa, 0x00, 0x53, 0xfb, 0x00, 0xb9, 0xfb, 0x00, 0x1f, 0xfc, 0x00, 0x85, 0xfc, 0x00, 0xeb, 0xfc, 0x00, 0x51, 0xfd, 0x00, 0xb7, 0xfd, 0x00, 0x1d, 0xfe, 0x00, 0x83, 0xfe, 0x00, 0xe9, 0xfe, 0x00, 0x4f, 0xff, 0x00, 0xb5, 0xff, 0x00, 0x1b, 0x00, 0x01, 0x81, 0x00, 0x01, 0xe7, 0x00, 0x01, 0x4d, 0x01, 0x01, 0xb3, 0x01, 0x01, 0x19, 0x02, 0x01, 0x7f, 0x02, 0x01, 0xe5, 0x02, 0x01, 0x4b, 0x03, 0x01, 0xb1, 0x03, 0x01, 0x17, 0x04, 0x01, 0x7d, 0x04, 0x01, 0xe3, 0x04, 0x01, 0x49, 0x05, 0x01, 0xaf, 0x05, 0x01, 0x15, 0x06, 0x01, 0x7b, 0x06, 0x01, 0xe1, 0x06, 0x01, 0x47, 0x07, 0x01, 0xad, 0x07, 0x01, 0x13, 0x08, 0x01, 0x79, 0x08, 0x01, 0xdf, 0x08, 0x01, 0x45, 0x09, 0x01, 0xab, 0x09, 0x01, 0x11, 0x0a, 0x01, 0x77, 0x0a, 0x01, 0xdd, 0x0a, 0x01, 0x43, 0x0b, 0x01, 0xa9, 0x0b, 0x01, 0x0f, 0x0c, 0x01, 0x75, 0x0c, 0x01, 0xdb, 0x0c, 0x01, 0x41, 0x0d, 0x01, 0xa7, 0x0d, 0x01, 0x0d, 0x0e, 0x01, 0x73, 0x0e, 0x01, 0xd9, 0x0e, 0x01, 0x3f, 0x0f, 0x01, 0xa5, 0x0f, 0x01, 0x0b, 0x10, 0x01, 0x71, 0x10, 0x01, 0xd7, 0x10, 0x01, 0x3d, 0x11, 0x01, 0xa3, 0x11, 0x01, 0x09, 0x12, 0x01, 0x6f, 0x12, 0x01, 0xd5, 0x12, 0x01, 0x3b, 0x13, 0x01, 0xa1, 0x13, 0x01, 0x07, 0x14, 0x01, 0x6d, 0x14, 0x01, 0xd3, 0x14, 0x01, 0x39, 0x15, 0x01, 0x9f, 0x15, 0x01, 0x05, 0x16, 0x01, 0x6b, 0x16, 0x01, 0xd1, 0x16, 0x01, 0x37, 0x17, 0x01, 0x9d, 0x17, 0x01, 0x03, 0x18, 0x01, 0x69, 0x18, 0x01, 0xcf, 0x18, 0x01, 0x35, 0x19, 0x01, 0x9b, 0x19, 0x01, 0x01, 0x1a, 0x01, 0x67, 0x1a, 0x01, 0xcd, 0x1a, 0x01, 0x33, 0x1b, 0x01, 0x99, 0x1b, 0x01, 0xff, 0x1b, 0x01, 0x65, 0x1c, 0x01, 0xcb, 0x1c, 0x01, 0x31, 0x1d, 0x01, 0x97, 0x1d, 0x01, 0xfd, 0x1d, 0x01, 0x63, 0x1e, 0x01, 0xc9, 0x1e, 0x01, 0x2f, 0x1f, 0x01, 0x95, 0x1f, 0x01, 0xfb, 0x1f, 0x01, 0x61, 0x20, 0x01, 0xc7, 0x20, 0x01, 0x2d, 0x21, 0x01, 0x93, 0x21, 0x01, 0xf9, 0x21, 0x01, 0x5f, 0x22, 0x01, 0xc5, 0x22, 0x01, 0x2b, 0x23, 0x01, 0x91, 0x23, 0x01, 0xf7, 0x23, 0x01, 0x5d, 0x24, 0x01, 0xc3, 0x24, 0x01, 0x29, 0x25, 0x01, 0x8f, 0x25, 0x01, 0xf5, 0x25, 0x01, 0x5b, 0x26, 0x01, 0xc1, 0x26, 0x01, 0x27, 0x27, 0x01, 0x8d, 0x27, 0x01, 0xf3, 0x27, 0x01, 0x59, 0x28, 0x01, 0xbf, 0x28, 0x01, 0x25, 0x29, 0x01, 0x8b, 0x29, 0x01, 0xf1, 0x29, 0x01, 0x57, 0x2a, 0x01, 0xbd, 0x2a, 0x01, 0x23, 0x2b, 0x01, 0x89, 0x2b, 0x01, 0xef, 0x2b, 0x01, 0x55, 0x2c, 0x01, 0xbb, 0x2c, 0x01, 0x21, 0x2d, 0x01, 0x87, 0x2d, 0x01, 0xed, 0x2d, 0x01, 0x53, 0x2e, 0x01, 0xb9, 0x2e, 0x01, 0x1f, 0x2f, 0x01, 0x85, 0x2f, 0x01, 0xeb, 0x2f, 0x01, 0x51, 0x30, 0x01, 0xb7, 0x30, 0x01, 0x1d, 0x31, 0x01, 0x83, 0x31, 0x01, 0xe9, 0x31, 0x01, 0x4f, 0x32, 0x01, 0xb5, 0x32, 0x01, 0x1b, 0x33, 0x01, 0x81, 0x33, 0x01, 0xe7, 0x33, 0x01, 0x4d, 0x34, 0x01, 0xb3, 0x34, 0x01, 0x19, 0x35, 0x01, 0x7f, 0x35, 0x01, 0xe5, 0x35, 0x01, 0x4b, 0x36, 0x01, 0xb1, 0x36, 0x01, 0x17, 0x37, 0x01, 0x7d, 0x37, 0x01, 0xe3, 0x37, 0x01, 0x49, 0x38, 0x01, 0xaf, 0x38, 0x01, 0x15, 0x39, 0x01, 0x7b, 0x39, 0x01, 0xe1, 0x39, 0x01, 0x47, 0x3a, 0x01, 0xad, 0x3a, 0x01, 0x13, 0x3b, 0x01, 0x79, 0x3b, 0x01, 0xdf, 0x3b, 0x01, 0x45, 0x3c, 0x01, 0xab, 0x3c, 0x01, 0x11, 0x3d, 0x01, 0x77, 0x3d, 0x01, 0xdd, 0x3d, 0x01, 0x43, 0x3e, 0x01, 0xa9, 0x3e, 0x01, 0x0f, 0x3f, 0x01, 0x75, 0x3f, 0x01, 0xdb, 0x3f, 0x01, 0x41, 0x40, 0x01, 0xa7, 0x40, 0x01, 0x0d, 0x41, 0x01, 0x73, 0x41, 0x01, 0xd9, 0x41, 0x01, 0x3f, 0x42, 0x01, 0xa5, 0x42, 0x01, 0x0b, 0x43, 0x01, 0x71, 0x43, 0x01, 0xd7, 0x43, 0x01, 0x3d, 0x44, 0x01, 0xa3, 0x44, 0x01, 0x09, 0x45, 0x01, 0x6f, 0x45, 0x01, 0xd5, 0x45, 0x01, 0x3b, 0x46, 0x01, 0xa1, 0x46, 0x01, 0x07, 0x47, 0x01, 0x6d, 0x47, 0x01, 0xd3, 0x47, 0x01, 0x39, 0x48, 0x01, 0x9f, 0x48, 0x01, 0x05, 0x49, 0x01, 0x6b, 0x49, 0x01, 0xd1, 0x49, 0x01, 0x37, 0x4a, 0x01, 0x9d, 0x4a, 0x01, 0x03, 0x4b, 0x01, 0x69, 0x4b, 0x01, 0xcf, 0x4b, 0x01, 0x35, 0x4c, 0x01, 0x9b, 0x4c, 0x01, 0x01, 0x4d, 0x01, 0x67, 0x4d, 0x01, 0xcd, 0x4d, 0x01, 0x33, 0x4e, 0x01, 0x99, 0x4e, 0x01, 0xff, 0x4e, 0x01, 0x65, 0x4f, 0x01, 0xcb, 0x4f, 0x01, 0x31, 0x50, 0x01, 0x97, 0x50, 0x01, 0xfd, 0x50, 0x01, 0x63, 0x51, 0x01, 0xc9, 0x51, 0x01, 0x2f, 0x52, 0x01, 0x95, 0x52, 0x01, 0xfb, 0x52, 0x01, 0x61, 0x53, 0x01, 0xc7, 0x53, 0x01, 0x2d, 0x54, 0x01, 0x93, 0x54, 0x01, 0xf9, 0x54, 0x01, 0x5f, 0x55, 0x01, 0xc5, 0x55, 0x01, 0x2b, 0x56, 0x01, 0x91, 0x56, 0x01, 0xf7, 0x56, 0x01, 0x5d, 0x57, 0x01, 0xc3, 0x57, 0x01, 0x29, 0x58, 0x01, 0x8f, 0x58, 0x01, 0xf5, 0x58, 0x01, 0x5b, 0x59, 0x01, 0xc1, 0x59, 0x01, 0x27, 0x5a, 0x01, 0x8d, 0x5a, 0x01, 0xf3, 0x5a, 0x01, 0x59, 0x5b, 0x01, 0xbf, 0x5b, 0x01, 0x25, 0x5c, 0x01, 0x8b, 0x5c, 0x01, 0xf1, 0x5c, 0x01, 0x57, 0x5d, 0x01, 0xbd, 0x5d, 0x01, 0x23, 0x5e, 0x01, 0x89, 0x5e, 0x01, 0xef, 0x5e, 0x01, 0x55, 0x5f, 0x01, 0xbb, 0x5f, 0x01, 0x21, 0x60, 0x01, 0x87, 0x60, 0x01, 0xed, 0x60, 0x01, 0x53, 0x61, 0x01, 0xb9, 0x61, 0x01, 0x1f, 0x62, 0x01, 0x85, 0x62, 0x01, 0xeb, 0x62, 0x01, 0x51, 0x63, 0x01, 0xb7, 0x63, 0x01, 0x1d, 0x64, 0x01, 0x83, 0x64, 0x01, 0xe9, 0x64, 0x01, 0x4f, 0x65, 0x01, 0xb5, 0x65, 0x01, 0x1b, 0x66, 0x01, 0x81, 0x66, 0x01, 0xe7, 0x66, 0x01, 0x4d, 0x67, 0x01, 0xb3, 0x67, 0x01, 0x19, 0x68, 0x01, 0x7f, 0x68, 0x01, 0xe5, 0x68, 0x01, 0x4b, 0x69, 0x01, 0xb1, 0x69, 0x01, 0x17, 0x6a, 0x01, 0x7d, 0x6a, 0x01, 0xe3, 0x6a, 0x01, 0x49, 0x6b, 0x01, 0xaf, 0x6b, 0x01, 0x15, 0x6c, 0x01, 0x7b, 0x6c, 0x01, 0xe1, 0x6c, 0x01, 0x47, 0x6d, 0x01, 0xad, 0x6d, 0x01, 0x13, 0x6e, 0x01, 0x79, 0x6e, 0x01, 0xdf, 0x6e, 0x01, 0x45, 0x6f, 0x01, 0xab, 0x6f, 0x01, 0x11, 0x70, 0x01, 0x77, 0x70, 0x01, 0xdd, 0x70, 0x01, 0x43, 0x71, 0x01, 0xa9, 0x71, 0x01, 0x0f, 0x72, 0x01, 0x75, 0x72, 0x01, 0xdb, 0x72, 0x01, 0x41, 0x73, 0x01, 0xa7, 0x73, 0x01, 0x0d, 0x74, 0x01, 0x73, 0x74, 0x01, 0xd9, 0x74, 0x01, 0x3f, 0x75, 0x01, 0xa5, 0x75, 0x01, 0x0b, 0x76, 0x01, 0x71, 0x76, 0x01, 0xd7, 0x76, 0x01, 0x3d, 0x77, 0x01, 0xa3, 0x77, 0x01, 0x09, 0x78, 0x01, 0x6f, 0x78, 0x01, 0xd5, 0x78, 0x01, 0x3b, 0x79, 0x01, 0xa1, 0x79, 0x01, 0x07, 0x7a, 0x01, 0x6d, 0x7a, 0x01, 0xd3, 0x7a, 0x01, 0x39, 0x7b, 0x01, 0x9f, 0x7b, 0x01, 0x05, 0x7c, 0x01, 0x6b, 0x7c, 0x01, 0xd1, 0x7c, 0x01, 0x37, 0x7d, 0x01, 0x9d, 0x7d, 0x01, 0x03, 0x7e, 0x01, 0x69, 0x7e, 0x01, 0xcf, 0x7e, 0x01, 0x35, 0x7f, 0x01, 0x9b, 0x7f, 0x01, 0x01, 0x80, 0x01, 0x67, 0x80, 0x01, 0xcd, 0x80, 0x01, 0x33, 0x81, 0x01, 0x99, 0x81, 0x01, 0xff, 0x81, 0x01, 0x65, 0x82, 0x01, 0xcb, 0x82, 0x01, 0x31, 0x83, 0x01, 0x97, 0x83, 0x01, 0xfd, 0x83, 0x01, 0x63, 0x84, 0x01, 0xc9, 0x84, 0x01, 0x2f, 0x85, 0x01, 0x95, 0x85, 0x01, 0xfb, 0x85, 0x01, 0x61, 0x86, 0x01, 0xc7, 0x86, 0x01, 0x2d, 0x87, 0x01, 0x93, 0x87, 0x01, 0xf9, 0x87, 0x01, 0x5f, 0x88, 0x01, 0xc5, 0x88, 0x01, 0x2b, 0x89, 0x01, 0x91, 0x89, 0x01, 0xf7, 0x89, 0x01, 0x5d, 0x8a, 0x01, 0xc3, 0x8a, 0x01, 0x29, 0x8b, 0x01, 0x8f, 0x8b, 0x01, 0xf5, 0x8b, 0x01, 0x5b, 0x8c, 0x01, 0xc1, 0x8c, 0x01, 0x27, 0x8d, 0x01, 0x8d, 0x8d, 0x01, 0xf3, 0x8d, 0x01, 0x59, 0x8e, 0x01, 0xbf, 0x8e, 0x01, 0x25, 0x8f, 0x01, 0x8b, 0x8f, 0x01, 0xf1, 0x8f, 0x01, 0x57, 0x90, 0x01, 0xbd, 0x90, 0x01, 0x23, 0x91, 0x01, 0x89, 0x91, 0x01, 0xef, 0x91, 0x01, 0x55, 0x92, 0x01, 0xbb, 0x92, 0x01, 0x21, 0x93, 0x01, 0x87, 0x93, 0x01, 0xed, 0x93, 0x01, 0x53, 0x94, 0x01, 0xb9, 0x94, 0x01, 0x1f, 0x95, 0x01, 0x85, 0x95, 0x01, 0xeb, 0x95, 0x01, 0x51, 0x96, 0x01, 0xb7, 0x96, 0x01, 0x1d, 0x97, 0x01, 0x83, 0x97, 0x01, 0xe9, 0x97, 0x01, 0x4f, 0x98, 0x01, 0xb5, 0x98, 0x01, 0x1b, 0x99, 0x01, 0x81, 0x99, 0x01, 0xe7, 0x99, 0x01, 0x4d, 0x9a, 0x01, 0xb3, 0x9a, 0x01, 0x19, 0x9b, 0x01, 0x7f, 0x9b, 0x01, 0xe5, 0x9b, 0x01, 0x4b, 0x9c, 0x01, 0xb1, 0x9c, 0x01, 0x17, 0x9d, 0x01, 0x7d, 0x9d, 0x01, 0xe3, 0x9d, 0x01, 0x49, 0x9e, 0x01, 0xaf, 0x9e, 0x01, 0x15, 0x9f, 0x01, 0x7b, 0x9f, 0x01, 0xe1, 0x9f, 0x01, 0x47, 0xa0, 0x01, 0xad, 0xa0, 0x01, 0x13, 0xa1, 0x01, 0x79, 0xa1, 0x01, 0xdf, 0xa1, 0x01, 0x45, 0xa2, 0x01, 0xab, 0xa2, 0x01, 0x11, 0xa3, 0x01, 0x77, 0xa3, 0x01, 0xdd, 0xa3, 0x01, 0x43, 0xa4, 0x01, 0xa9, 0xa4, 0x01, 0x0f, 0xa5, 0x01, 0x75, 0xa5, 0x01, 0xdb, 0xa5, 0x01, 0x41, 0xa6, 0x01, 0xa7, 0xa6, 0x01, 0x0d, 0xa7, 0x01, 0x73, 0xa7, 0x01, 0xd9, 0xa7, 0x01, 0x3f, 0xa8, 0x01, 0xa5, 0xa8, 0x01, 0x0b, 0xa9, 0x01, 0x71, 0xa9, 0x01, 0xd7, 0xa9, 0x01, 0x3d, 0xaa, 0x01, 0xa3, 0xaa, 0x01, 0x09, 0xab, 0x01, 0x6f, 0xab, 0x01, 0xd5, 0xab, 0x01, 0x3b, 0xac, 0x01, 0xa1, 0xac, 0x01, 0x07, 0xad, 0x01, 0x6d, 0xad, 0x01, 0xd3, 0xad, 0x01, 0x39, 0xae, 0x01, 0x9f, 0xae, 0x01, 0x05, 0xaf, 0x01, 0x6b, 0xaf, 0x01, 0xd1, 0xaf, 0x01, 0x37, 0xb0, 0x01, 0x9d, 0xb0, 0x01, 0x03, 0xb1, 0x01, 0x69, 0xb1, 0x01, 0xcf, 0xb1, 0x01, 0x35, 0xb2, 0x01, 0x9b, 0xb2, 0x01, 0x01, 0xb3, 0x01, 0x67, 0xb3, 0x01, 0xcd, 0xb3, 0x01, 0x33, 0xb4, 0x01, 0x99, 0xb4, 0x01, 0xff, 0xb4, 0x01, 0x65, 0xb5, 0x01, 0xcb, 0xb5, 0x01, 0x31, 0xb6, 0x01, 0x97, 0xb6, 0x01, 0xfd, 0xb6, 0x01, 0x63, 0xb7, 0x01, 0xc9, 0xb7, 0x01, 0x2f, 0xb8, 0x01, 0x95, 0xb8, 0x01, 0xfb, 0xb8, 0x01, 0x61, 0xb9, 0x01, 0xc7, 0xb9, 0x01, 0x2d, 0xba, 0x01, 0x93, 0xba, 0x01, 0xf9, 0xba, 0x01, 0x5f, 0xbb, 0x01, 0xc5, 0xbb, 0x01, 0x2b, 0xbc, 0x01, 0x91, 0xbc, 0x01, 0xf7, 0xbc, 0x01, 0x5d, 0xbd, 0x01, 0xc3, 0xbd, 0x01, 0x29, 0xbe, 0x01, 0x8f, 0xbe, 0x01, 0xf5, 0xbe, 0x01, 0x5b, 0xbf, 0x01, 0xc1, 0xbf, 0x01, 0x27, 0xc0, 0x01, 0x8d, 0xc0, 0x01, 0xf3, 0xc0, 0x01, 0x59, 0xc1, 0x01, 0xbf, 0xc1, 0x01, 0x25, 0xc2, 0x01, 0x8b, 0xc2, 0x01, 0xf1, 0xc2, 0x01, 0x57, 0xc3, 0x01, 0xbd, 0xc3, 0x01, 0x23, 0xc4, 0x01, 0x89, 0xc4, 0x01, 0xef, 0xc4, 0x01, 0x55, 0xc5, 0x01, 0xbb, 0xc5, 0x01, 0x21, 0xc6, 0x01, 0x87, 0xc6, 0x01, 0xed, 0xc6, 0x01, 0x53, 0xc7, 0x01, 0xb9, 0xc7, 0x01, 0x1f, 0xc8, 0x01, 0x85, 0xc8, 0x01, 0xeb, 0xc8, 0x01, 0x51, 0xc9, 0x01, 0xb7, 0xc9, 0x01, 0x1d, 0xca, 0x01, 0x83, 0xca, 0x01, 0xe9, 0xca, 0x01, 0x4f, 0xcb, 0x01, 0xb5, 0xcb, 0x01, 0x1b, 0xcc, 0x01, 0x1f, 0x04, 0x07, 0x04, 0x04, 0x02, 0x03, 0x10, 0x00, 0x00, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x0a, 0x06, 0x00, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x10, 0x00, 0x00, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x1f, 0x00, 0x08, 0x00, 0x06, 0x00, 0x03, 0x0a, 0x06, 0x00, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x1e, 0x0b, 0x06, 0x04, 0x04, 0x03, 0x04, 0x0c, 0x04, 0x00, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x13, 0xf8, 0x01, 0x87, 0xf9, 0x01, 0x87, 0xf9, 0x01, 0x35, 0xee, 0x01, 0xa9, 0xf2, 0x01, 0xa9, 0xf2, 0x01, 0x35, 0xee, 0x01, 0xa9, 0xf2, 0x01, 0xa9, 0xf2, 0x01, 0x1e, 0x04, 0x0b, 0x04, 0x08, 0x02, 0x06, 0x04, 0x06, 0x06, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x18, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x0a, 0x06, 0x00, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x08, 0x04, 0x04, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0xb7, 0x11, 0x02, 0x21, 0x17, 0x02, 0x09, 0x1d, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x03, 0x05, 0x08, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0x7c, 0x00, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x73, 0x30, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xf0, 0x3c, 0x03, 0x55, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0xff, 0x00, 0x03, 0x55, 0x55, 0xff, 0x00, 0x3d, 0x55, 0x55, 0xff, 0x00, 0xcd, 0x55, 0x55, 0xcf, 0xff, 0x0d, 0x55, 0x55, 0x73, 0x30, 0x3d, 0x55, 0x55, 0x73, 0xf0, 0xf5, 0x55, 0x55, 0x73, 0xf0, 0x35, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x7f, 0x55, 0x57, 0xff, 0x55, 0xff, 0xd5, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x0f, 0x00, 0xf0, 0xd5, 0x57, 0x30, 0xc3, 0x0c, 0xd5, 0x57, 0x00, 0x3c, 0x00, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x57, 0x3f, 0xff, 0xfc, 0xd5, 0x57, 0xf0, 0xc3, 0x0f, 0xd5, 0x55, 0x73, 0xff, 0xcd, 0x55, 0x55, 0xc3, 0xff, 0xc3, 0x55, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x03, 0x00, 0xc0, 0xd5, 0x57, 0x0c, 0x00, 0x30, 0xd5, 0x57, 0x00, 0x3c, 0x00, 0xd5, 0x55, 0xc0, 0xff, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x3f, 0x0f, 0xc3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x00, 0xf0, 0x0d, 0x55, 0x55, 0xff, 0x0f, 0xf5, 0x55, 0x57, 0x33, 0xfc, 0xcd, 0x55, 0x57, 0xf3, 0xfc, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x30, 0x00, 0x0c, 0xd5, 0x57, 0x0c, 0x00, 0x30, 0xd5, 0x57, 0x00, 0xff, 0x00, 0xd5, 0x5f, 0x03, 0xff, 0xc0, 0xf5, 0x5c, 0xc3, 0xff, 0xc3, 0x35, 0x5f, 0x3f, 0xff, 0xfc, 0xf5, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0xc3, 0xff, 0xc3, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x7f, 0x55, 0x57, 0xff, 0x55, 0xff, 0xd5, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x03, 0x00, 0xc0, 0xd5, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x30, 0x3c, 0x0c, 0xd5, 0x55, 0xcc, 0x3c, 0x33, 0xd5, 0x55, 0xcc, 0x3c, 0x33, 0x55, 0x55, 0xc3, 0xc3, 0xc3, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xd7, 0xf5, 0x55, 0x55, 0x5f, 0x55, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x5c, 0x3f, 0xff, 0xc3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x55, 0xff, 0xff, 0xf5, 0x55, 0x55, 0xc0, 0x00, 0x35, 0x55, 0x57, 0x30, 0x00, 0xcd, 0x55, 0x57, 0xf0, 0x00, 0xfd, 0x55, 0x55, 0x70, 0x00, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0x55, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0x70, 0x00, 0x3d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x70, 0x0c, 0xd5, 0x55, 0x57, 0xc0, 0xfc, 0xd5, 0x55, 0x55, 0xf0, 0x3f, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0x57, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0x70, 0x00, 0x3d, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x30, 0xcd, 0x55, 0x55, 0xfc, 0x3f, 0xf5, 0x55, 0x55, 0x70, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x70, 0x3f, 0xf5, 0x55, 0x55, 0xc0, 0x0f, 0xf5, 0x55, 0x7f, 0xc0, 0x0f, 0xf5, 0x5f, 0xc0, 0xc0, 0x0f, 0x55, 0x5f, 0xc0, 0xc0, 0xcf, 0xd5, 0x55, 0xc0, 0xc0, 0xcf, 0xd5, 0x57, 0xc0, 0x3c, 0xcf, 0xf5, 0x5f, 0xfc, 0x03, 0x0f, 0xf5, 0x5f, 0xff, 0xff, 0xf7, 0xd5, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x3c, 0x03, 0xc3, 0x55, 0x5c, 0xc3, 0x0c, 0x33, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0xc3, 0x0c, 0x33, 0x55, 0x57, 0x30, 0xf0, 0xcc, 0xd5, 0x55, 0xff, 0xff, 0xf0, 0xd5, 0x55, 0x73, 0x0c, 0x03, 0x55, 0x55, 0xcc, 0xfc, 0x0d, 0x55, 0x55, 0xfc, 0xff, 0x0d, 0x55, 0x55, 0x5c, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x55, 0xf5, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x00, 0xc3, 0x00, 0xd5, 0x57, 0x3f, 0xc3, 0xfc, 0xd5, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x5c, 0xcc, 0x35, 0x55, 0x55, 0x73, 0xff, 0xcd, 0x55, 0x55, 0x70, 0xfc, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xc0, 0x30, 0x03, 0x55, 0x55, 0xc0, 0xc0, 0x03, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xfc, 0x00, 0x03, 0x55, 0x55, 0xff, 0x03, 0xc3, 0x55, 0x55, 0x7f, 0x03, 0x3d, 0x55, 0x55, 0x5f, 0xff, 0x35, 0x55, 0x55, 0x5c, 0xcc, 0x0d, 0x55, 0x55, 0x57, 0x3c, 0x03, 0x55, 0x55, 0x57, 0x3c, 0x3f, 0x55, 0x55, 0x57, 0xff, 0xf5, 0x55, 0x55, 0x55, 0x7d, 0xfd, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0x7f, 0x55, 0x55, 0x55, 0xff, 0xff, 0xd5, 0x55, 0x55, 0xff, 0xff, 0xd5, 0x55, 0x55, 0xff, 0x00, 0x35, 0x55, 0x57, 0xf0, 0x00, 0x3d, 0x55, 0x57, 0xc0, 0x03, 0x03, 0x55, 0x57, 0x00, 0x3c, 0x03, 0x55, 0x57, 0x00, 0x00, 0x0f, 0x55, 0x57, 0x00, 0x00, 0x35, 0x55, 0x57, 0xc0, 0x03, 0xd5, 0x55, 0x55, 0x7f, 0xff, 0x55, 0x55, 0x55, 0xc0, 0xcf, 0x55, 0x55, 0x57, 0x30, 0xfd, 0x55, 0x55, 0x57, 0xf0, 0xfd, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x7d, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xf5, 0x55, 0x55, 0x5f, 0xfd, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0x00, 0x0d, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x0f, 0xc3, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0x70, 0x00, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x5c, 0x3c, 0xd5, 0x55, 0x55, 0x5f, 0x0f, 0xd5, 0x55, 0x55, 0x5c, 0xff, 0xd5, 0x55, 0x55, 0x70, 0x0f, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3c, 0x0f, 0x55, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0xc0, 0x00, 0xff, 0x55, 0x55, 0xc0, 0xf0, 0xff, 0x55, 0x55, 0x70, 0xcc, 0xfd, 0x55, 0x55, 0x5f, 0xcf, 0xd5, 0x55, 0x55, 0x5c, 0xcc, 0xd5, 0x55, 0x55, 0x5c, 0x3f, 0xd5, 0x55, 0x55, 0x5c, 0x0f, 0xd5, 0x55, 0x55, 0x70, 0x0f, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x55, 0xfd, 0x55, 0x55, 0x7f, 0xdf, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0xc3, 0x55, 0x55, 0xcc, 0x00, 0x03, 0x55, 0x55, 0x73, 0x00, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x73, 0x30, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0x7f, 0x55, 0x55, 0xff, 0xd5, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0xd5, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0x70, 0x00, 0x03, 0x55, 0x55, 0xc3, 0x00, 0x30, 0xd5, 0x55, 0xcc, 0xc0, 0xcc, 0xd5, 0x55, 0xc3, 0x00, 0x30, 0xd5, 0x57, 0xc0, 0x3f, 0x00, 0xd5, 0x57, 0x30, 0xff, 0xc3, 0x55, 0x55, 0xcf, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xc3, 0xfc, 0x03, 0x55, 0x55, 0xc3, 0xfc, 0x3c, 0xd5, 0x55, 0x7f, 0xfc, 0x37, 0xd5, 0x55, 0x5f, 0x7f, 0xd5, 0x55, 0x55, 0x55, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x3c, 0x03, 0xc3, 0x55, 0x5c, 0xf3, 0x0f, 0x33, 0x55, 0x5c, 0xff, 0x0f, 0xf3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x0f, 0xf0, 0x0d, 0x55, 0x55, 0xfc, 0x3f, 0xf5, 0x55, 0x55, 0xc3, 0xcc, 0x3d, 0x55, 0x55, 0x70, 0xfc, 0xf3, 0x55, 0x55, 0x70, 0xfc, 0xdf, 0x55, 0x55, 0x7f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xcd, 0x55, 0x5f, 0xff, 0xff, 0xfd, 0x55, 0x7f, 0xff, 0xff, 0xd5, 0x55, 0x70, 0x00, 0x03, 0xd5, 0x55, 0xff, 0xff, 0xfc, 0xd5, 0x55, 0xc0, 0x00, 0x0f, 0xd5, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0x7c, 0x00, 0x0c, 0xd5, 0x55, 0x5f, 0xff, 0xf0, 0x35, 0x55, 0x7f, 0x3f, 0xfc, 0x0d, 0x55, 0x7f, 0x3f, 0xfc, 0x0d, 0x55, 0x70, 0x00, 0x3c, 0x0d, 0x55, 0x7f, 0xff, 0xf0, 0x0d, 0x55, 0x5f, 0xff, 0xdf, 0xf5, 0x55, 0x7f, 0xdf, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0x55, 0x55, 0x55, 0x57, 0x35, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0xff, 0xff, 0x55, 0x55, 0x5f, 0xff, 0xff, 0x55, 0x55, 0x70, 0x00, 0x0f, 0x55, 0x55, 0x7f, 0xff, 0xf3, 0xfd, 0x55, 0xc0, 0x00, 0x0c, 0xc3, 0x55, 0xc0, 0x00, 0x03, 0xc3, 0x55, 0xc0, 0x00, 0x03, 0x03, 0x55, 0xf0, 0x03, 0x03, 0xc3, 0x55, 0xc3, 0xc0, 0x0f, 0xc3, 0x55, 0xc3, 0xc0, 0x3f, 0x0d, 0x55, 0x7f, 0xff, 0xfc, 0x35, 0x5d, 0xff, 0x3f, 0xf3, 0xd5, 0x5f, 0x00, 0x00, 0xfd, 0x55, 0x5f, 0xff, 0xff, 0x3d, 0x55, 0x55, 0xff, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xff, 0x55, 0x55, 0x7f, 0xff, 0xff, 0xd5, 0x55, 0xf0, 0x00, 0x03, 0xf5, 0x55, 0xcf, 0xff, 0xfc, 0xf5, 0x55, 0xf0, 0x00, 0x03, 0xff, 0x57, 0x0f, 0xc0, 0xfc, 0xf3, 0x57, 0x33, 0xc3, 0x3c, 0xdf, 0x57, 0x33, 0xc3, 0x3c, 0xd5, 0x57, 0x0f, 0xc0, 0xfc, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x35, 0x55, 0xff, 0xff, 0xfc, 0x0d, 0x57, 0xff, 0xcf, 0xf3, 0x0d, 0x5c, 0xff, 0xcf, 0xff, 0x0d, 0x57, 0x70, 0x00, 0x0c, 0x0d, 0x55, 0x7f, 0xff, 0xf7, 0xf5, 0x55, 0x57, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xf7, 0xfd, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xff, 0xf5, 0x55, 0x70, 0x00, 0xff, 0xff, 0x55, 0x7f, 0xfc, 0x03, 0xf3, 0x55, 0xf0, 0xff, 0xf0, 0xdf, 0x55, 0xf0, 0xf3, 0x0f, 0xd5, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xff, 0xf0, 0x33, 0x55, 0x57, 0x3f, 0xc0, 0xff, 0xd5, 0x57, 0xcf, 0xff, 0xfc, 0x35, 0x55, 0xff, 0x3f, 0xfc, 0x0d, 0x55, 0x7f, 0x3f, 0xf0, 0x0d, 0x55, 0x7f, 0x3f, 0xf0, 0x0d, 0x55, 0x70, 0x00, 0xf0, 0x0d, 0x55, 0x5f, 0xff, 0xdf, 0xf5, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x55, 0xf7, 0xd5, 0x55, 0x30, 0x1f, 0x01, 0x55, 0x40, 0x00, 0x00, 0x00, 0x15, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x11, 0x41, 0x50, 0x00, 0x00, 0x15, 0x55, 0x55, 0x54, 0x04, 0x10, 0x01, 0x55, 0x41, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa1, 0x14, 0x15, 0x54, 0x01, 0x11, 0x45, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa5, 0x54, 0x15, 0x54, 0x01, 0x55, 0x45, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa1, 0x14, 0x44, 0x11, 0x55, 0x55, 0x55, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x15, 0x40, 0x01, 0x55, 0x11, 0x56, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x95, 0x40, 0x01, 0x55, 0x55, 0x56, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x95, 0x55, 0x55, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x55, 0x50, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x01, 0x50, 0x55, 0x50, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x15, 0x55, 0x55, 0x54, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x02, 0x55, 0x55, 0x55, 0x00, 0x04, 0x00, 0x80, 0x28, 0x00, 0x00, 0xa0, 0x02, 0x01, 0x15, 0x55, 0x10, 0x04, 0x55, 0x80, 0x28, 0x00, 0x00, 0xa0, 0x02, 0x01, 0x15, 0x55, 0x01, 0x55, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x02, 0x55, 0x55, 0x55, 0x01, 0x01, 0x00, 0x80, 0xaa, 0xaa, 0xaa, 0xa8, 0x02, 0x00, 0x04, 0x01, 0x01, 0x55, 0x00, 0x82, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x04, 0x01, 0x00, 0x41, 0x00, 0x82, 0xaa, 0xaa, 0xaa, 0xaa, 0x02, 0x00, 0x04, 0x01, 0x55, 0x5a, 0xa5, 0x80, 0x95, 0x95, 0x80, 0x00, 0x02, 0x55, 0x54, 0x01, 0x00, 0x25, 0x58, 0x80, 0x95, 0x95, 0x85, 0x54, 0x0a, 0xaa, 0xa8, 0x01, 0x00, 0x26, 0x98, 0x80, 0x95, 0x95, 0x85, 0x54, 0x08, 0x00, 0x09, 0x55, 0x00, 0x25, 0x58, 0x80, 0x95, 0x95, 0xaa, 0xaa, 0x08, 0x88, 0x88, 0x00, 0x00, 0x20, 0x08, 0x95, 0x95, 0x95, 0x80, 0x02, 0x58, 0x88, 0x88, 0x00, 0xaa, 0xa0, 0x0a, 0x95, 0x95, 0x95, 0x80, 0x02, 0x58, 0x00, 0x0a, 0xaa, 0x04, 0x20, 0x08, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa9, 0x55, 0x58, 0x00, 0x00, 0x0a, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xaa, 0xa9, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0x42, 0x82, 0x20, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa6, 0x86, 0x26, 0x62, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x45, 0x86, 0x24, 0xa4, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xa4, 0xa1, 0x61, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x61, 0x40, 0xa2, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0xaa, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa9, 0x55, 0x69, 0x55, 0x6a, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x9a, 0xa9, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x59, 0x59, 0x6a, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x98, 0x49, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x95, 0x55, 0xaa, 0x95, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa5, 0x56, 0xaa, 0x40, 0x68, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa8, 0x0a, 0xa5, 0x55, 0x58, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa9, 0x5a, 0xa5, 0x55, 0x58, 0x00, 0x95, 0x5a, 0x69, 0xa5, 0x56, 0x02, 0xa5, 0x96, 0xa9, 0x69, 0x68, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x96, 0x5a, 0x69, 0xa5, 0x96, 0x54, 0x54, 0x54, 0x54, 0x54, 0x55, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x54, 0x54, 0x54, 0x54, 0x54, 0x55, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x30, 0x1f, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x15, 0x00, 0x00, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x55, 0x00, 0x01, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x40, 0x51, 0x55, 0x55, 0x15, 0x54, 0x00, 0x00, 0x15, 0x54, 0x55, 0x55, 0x45, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x40, 0x00, 0x44, 0x11, 0x10, 0x11, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x44, 0x04, 0x44, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x40, 0x00, 0x44, 0x15, 0x05, 0x41, 0x50, 0x05, 0x55, 0x55, 0x50, 0x05, 0x41, 0x50, 0x54, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x50, 0x40, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x50, 0x40, 0x01, 0x00, 0x01, 0x00, 0x17, 0xfc, 0x3f, 0xfc, 0x00, 0x43, 0xff, 0xc0, 0x01, 0x00, 0x01, 0x00, 0x1f, 0xf4, 0xff, 0xd4, 0x00, 0x4f, 0xfc, 0x40, 0x01, 0x55, 0x55, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x40, 0x01, 0x11, 0x11, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x40, 0x01, 0x00, 0x01, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xc0, 0x01, 0x05, 0x41, 0x00, 0xf0, 0xfc, 0x03, 0xff, 0xff, 0x00, 0x00, 0xc0, 0x01, 0x05, 0x41, 0x00, 0xf0, 0xf3, 0x0c, 0x71, 0xc7, 0x33, 0x30, 0xc0, 0xaa, 0xaa, 0xaa, 0xaa, 0xf0, 0xf3, 0x0d, 0x75, 0xd7, 0x33, 0x30, 0xea, 0x55, 0x55, 0x55, 0x55, 0xf0, 0xfc, 0x0d, 0x34, 0xd3, 0x33, 0x30, 0xd5, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x0d, 0x34, 0xc3, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x03, 0xff, 0xff, 0xaa, 0xaa, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 0xc0, 0x00, 0xfc, 0x0f, 0xc0, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x3a, 0xbf, 0xfa, 0xab, 0xff, 0xbf, 0xfb, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0xff, 0xff, 0xcf, 0xfc, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf0, 0x03, 0xff, 0x3f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xc0, 0x00, 0xfc, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x55, 0x51, 0x55, 0x55, 0x15, 0x54, 0x00, 0x00, 0x15, 0x10, 0x00, 0x00, 0x40, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x40, 0x11, 0x10, 0x11, 0x10, 0x04, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x40, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x15, 0x55, 0x55, 0x40, 0x15, 0x05, 0x41, 0x50, 0x05, 0x55, 0x55, 0x50, 0x00, 0x00, 0x00, 0x00, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf5, 0xff, 0xf0, 0x00, 0x0f, 0xff, 0x00, 0x50, 0x50, 0x50, 0x50, 0x3f, 0xc3, 0xff, 0x00, 0x14, 0x3f, 0xf4, 0x14, 0x55, 0x50, 0x55, 0x50, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x54, 0x55, 0x50, 0x55, 0x50, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x54, 0x55, 0x55, 0x55, 0x53, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x54, 0x40, 0x10, 0x40, 0x13, 0xc3, 0xf0, 0x0f, 0xff, 0xfc, 0x00, 0x03, 0x04, 0x50, 0x50, 0x50, 0x53, 0xc3, 0xcc, 0x31, 0xc7, 0x1c, 0xcc, 0xc3, 0x14, 0x40, 0x10, 0x40, 0x13, 0xc3, 0xcc, 0x35, 0xd7, 0x5c, 0xcc, 0xc3, 0x04, 0xaa, 0xaa, 0xaa, 0xab, 0xc3, 0xf0, 0x34, 0xd3, 0x4c, 0xcc, 0xc3, 0xaa, 0x55, 0x55, 0x55, 0x57, 0x00, 0x00, 0x34, 0xd3, 0x0c, 0x00, 0x03, 0x55, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x0f, 0xff, 0xfe, 0xaa, 0xab, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x3f, 0x00, 0x03, 0xf0, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xea, 0xff, 0xea, 0xaf, 0xfe, 0xff, 0xec, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf3, 0xff, 0xff, 0x3f, 0xf3, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x0f, 0xfc, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x03, 0xf0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xfd, 0x7d, 0x7f, 0x5d, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x5d, 0xd5, 0xd7, 0x75, 0xdd, 0xd5, 0x55, 0x55, 0x55, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x30, 0xcc, 0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0xc0, 0xff, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xc0, 0xc3, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0x3f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xfc, 0x3f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x03, 0xc0, 0x30, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0xf3, 0xff, 0xff, 0xcf, 0x00, 0x00, 0x0f, 0xf0, 0x70, 0x0f, 0x55, 0x55, 0xc3, 0x0c, 0x30, 0xc3, 0x55, 0x55, 0xf0, 0x0d, 0xc3, 0x30, 0xd5, 0xff, 0x7c, 0xcf, 0xf3, 0x3d, 0xff, 0x57, 0x0c, 0xc3, 0xc0, 0x3f, 0x5f, 0x03, 0x57, 0xcf, 0xf3, 0xd5, 0xc0, 0xf5, 0xfc, 0x03, 0xc0, 0x30, 0xdc, 0x0d, 0x5f, 0xff, 0xff, 0xf5, 0x70, 0x37, 0x0c, 0x03, 0x7f, 0xff, 0x5f, 0xf5, 0x5f, 0x55, 0x55, 0xf5, 0x5f, 0xf5, 0xff, 0xfd, 0x30, 0x1f, 0xa4, 0x00, 0xa4, 0x01, 0x90, 0x00, 0x64, 0x06, 0x40, 0x1a, 0x00, 0x16, 0xa9, 0x40, 0x09, 0x00, 0x40, 0x00, 0x10, 0x01, 0x00, 0x60, 0x01, 0x6a, 0x2a, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xaa, 0x00, 0xa5, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x01, 0x6a, 0x80, 0x00, 0x01, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x30, 0xc0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x00, 0x05, 0x94, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x15, 0x56, 0xa5, 0x55, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x15, 0x40, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x29, 0x50, 0x15, 0x68, 0x00, 0x40, 0x07, 0xf0, 0x0f, 0xc0, 0x10, 0x00, 0x0a, 0xa5, 0x6a, 0x80, 0x01, 0x00, 0x1f, 0xfc, 0x3f, 0xf0, 0x04, 0x00, 0x00, 0xaa, 0xa8, 0x00, 0x15, 0x00, 0x1f, 0xff, 0xff, 0xf0, 0x05, 0x40, 0x00, 0x0a, 0xa0, 0x00, 0x04, 0x00, 0x5c, 0x00, 0x00, 0x30, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xf0, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xc0, 0x33, 0x00, 0x00, 0xcc, 0x03, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x30, 0x03, 0xc0, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x0c, 0x30, 0x03, 0xc0, 0x0c, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x3c, 0x03, 0xc0, 0x3c, 0xff, 0xc0, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0xc3, 0xff, 0xff, 0xc3, 0x00, 0x00, 0x0f, 0xf0, 0x30, 0x0c, 0x00, 0x00, 0xcc, 0x30, 0x0c, 0x33, 0x00, 0x00, 0x30, 0x0c, 0xc3, 0x0f, 0x00, 0x00, 0x3f, 0x3f, 0xfc, 0xfc, 0x00, 0x00, 0xf0, 0xc3, 0xc0, 0x30, 0xc0, 0x00, 0x03, 0x3f, 0xfc, 0xc0, 0x00, 0x03, 0x0c, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0xfc, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x3f, 0xfc, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x30, 0x30, 0xc0, 0x00, 0x00, 0x3c, 0x3c, 0x00, 0x00, 0x03, 0x0c, 0x0c, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x0c, 0x30, 0x00, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xfd, 0x7d, 0x7f, 0x5d, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x5d, 0xd5, 0xd7, 0x75, 0xdd, 0xd5, 0x55, 0x55, 0x55, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x30, 0xcc, 0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0xc0, 0xff, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xc0, 0xc3, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x70, 0x0f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xf0, 0x0d, 0xc3, 0x30, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x0c, 0xc3, 0xc0, 0x3f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfc, 0x03, 0xc0, 0x30, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x0c, 0x03, 0x7f, 0xff, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xfd, 0x30, 0x1f, 0xa4, 0x00, 0xa4, 0x01, 0x90, 0x00, 0x64, 0x06, 0x40, 0x1a, 0x00, 0x16, 0xa9, 0x40, 0x09, 0x00, 0x40, 0x00, 0x10, 0x01, 0x00, 0x60, 0x01, 0x6a, 0x2a, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xaa, 0x00, 0xa5, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x01, 0x6a, 0x80, 0x00, 0x01, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x30, 0xc0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x00, 0x05, 0x94, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x15, 0x56, 0xa5, 0x55, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x15, 0x40, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x29, 0x50, 0x15, 0x68, 0x00, 0x40, 0x04, 0x00, 0x04, 0x00, 0x10, 0x00, 0x0a, 0xa5, 0x6a, 0x80, 0x01, 0x00, 0x14, 0x00, 0x05, 0x00, 0x04, 0x00, 0x00, 0xaa, 0xa8, 0x00, 0x15, 0x00, 0x15, 0x00, 0x15, 0x00, 0x05, 0x40, 0x00, 0x0a, 0xa0, 0x00, 0x04, 0x00, 0x54, 0x00, 0x05, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x30, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0c, 0xc3, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xc3, 0xc0, 0x30, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x30, 0x30, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x0c, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xfc, 0x00, 0xc3, 0x0f, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xc3, 0x00, 0xc3, 0x30, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xcc, 0xc3, 0x00, 0xff, 0x30, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xfc, 0x00, 0xc3, 0x30, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xc0, 0x00, 0xc3, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x3f, 0x0f, 0xcf, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0xcc, 0x0c, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0xcf, 0xcf, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0x0f, 0xcf, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x30, 0xcc, 0x33, 0x0c, 0xfc, 0xfc, 0x00, 0x00, 0xc0, 0x00, 0x00, 0xc3, 0x30, 0xcf, 0x33, 0xcc, 0xc0, 0xc3, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc3, 0x30, 0xcc, 0xf3, 0x3c, 0xfc, 0xc3, 0x00, 0x00, 0xfc, 0x00, 0x00, 0xfc, 0x30, 0xcc, 0x33, 0x0c, 0xc0, 0xfc, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc3, 0x0f, 0x0c, 0x33, 0x0c, 0xfc, 0xc3, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x1f, 0x05, 0x55, 0x55, 0x55, 0x55, 0x55, 0x54, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x05, 0x54, 0x55, 0x45, 0x51, 0x10, 0x00, 0x04, 0x04, 0x55, 0x44, 0x51, 0x11, 0x55, 0x44, 0x04, 0x44, 0x44, 0x51, 0x11, 0x00, 0x44, 0x04, 0x44, 0x44, 0x51, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x00, 0x00, 0x00, 0x05, 0x41, 0x10, 0x00, 0x00, 0x00, 0x00, 0x04, 0x41, 0x10, 0x00, 0x00, 0x10, 0x55, 0x05, 0x41, 0x10, 0x54, 0x00, 0x55, 0x45, 0x10, 0x11, 0x11, 0x01, 0x40, 0x55, 0x54, 0x10, 0x11, 0x11, 0x00, 0x10, 0x55, 0x54, 0x15, 0x51, 0x11, 0x41, 0x11, 0x51, 0x10, 0x04, 0x41, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x50, 0x50, 0x00, 0x00, 0x10, 0x01, 0x10, 0x55, 0x50, 0x55, 0x00, 0x55, 0x01, 0x10, 0x44, 0x51, 0x00, 0x51, 0x00, 0x41, 0x10, 0x40, 0x11, 0x04, 0x41, 0x11, 0x41, 0x10, 0x15, 0x41, 0x00, 0x41, 0x00, 0x41, 0x10, 0x10, 0x41, 0x00, 0x40, 0x41, 0x01, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x55, 0x55, 0x55, 0x55, 0x55, 0x41, 0x10, 0x40, 0x00, 0x00, 0x00, 0x00, 0x41, 0x10, 0x55, 0x55, 0x55, 0x55, 0x55, 0x41, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x15, 0x50, 0x00, 0x00, 0x00, 0x01, 0x55, 0x12, 0x0c, 0x57, 0xf5, 0x7d, 0x55, 0x50, 0x5f, 0xfd, 0xff, 0x55, 0x50, 0x5f, 0xff, 0xff, 0x55, 0x50, 0x5f, 0xff, 0xff, 0xd5, 0x50, 0x7c, 0x00, 0x00, 0xd5, 0x50, 0x70, 0x0f, 0xc3, 0xd5, 0x50, 0x70, 0x33, 0xc3, 0xd5, 0x50, 0x70, 0x33, 0xc3, 0xd5, 0x50, 0x70, 0x0f, 0xc3, 0xd5, 0x50, 0x5c, 0x00, 0x0f, 0x55, 0x50, 0x57, 0xff, 0xfd, 0x55, 0x50, 0x5c, 0x3c, 0x33, 0x55, 0x50, 0x12, 0x0c, 0x55, 0xfd, 0x5f, 0x55, 0x50, 0x57, 0xff, 0x7f, 0xd5, 0x50, 0x57, 0xff, 0xff, 0xd5, 0x50, 0x57, 0xff, 0xff, 0xf5, 0x50, 0x5f, 0x00, 0x00, 0x35, 0x50, 0x5c, 0x03, 0xc0, 0x35, 0x50, 0x5c, 0x0c, 0x30, 0xf5, 0x50, 0x5c, 0x00, 0x00, 0x35, 0x50, 0x5c, 0x0c, 0x0f, 0xf5, 0x50, 0x57, 0x33, 0x0f, 0xd5, 0x50, 0x55, 0xf3, 0xff, 0x35, 0x50, 0x55, 0xc3, 0xc3, 0xf5, 0x50, 0x12, 0x0c, 0x5f, 0xd5, 0x7f, 0xff, 0xf0, 0x7f, 0xf5, 0xff, 0x00, 0x30, 0x7f, 0xff, 0xff, 0x00, 0x30, 0x7f, 0xff, 0xff, 0x00, 0x30, 0x70, 0x00, 0x03, 0x00, 0x30, 0xc3, 0xf0, 0x3f, 0x00, 0x30, 0xcc, 0xf0, 0xcf, 0x00, 0x30, 0xcc, 0xf0, 0xcf, 0x00, 0x30, 0xc3, 0xf0, 0x3f, 0xff, 0xf0, 0x70, 0x0f, 0x00, 0xcd, 0x50, 0x5f, 0xff, 0xff, 0x35, 0x50, 0x70, 0x30, 0x3c, 0xd5, 0x50, 0x12, 0x0c, 0x55, 0xfd, 0x57, 0xd5, 0x50, 0x57, 0xff, 0xdf, 0xf5, 0x50, 0x57, 0xff, 0xff, 0xfd, 0x50, 0x55, 0xff, 0xff, 0xfd, 0x50, 0x57, 0xc0, 0x00, 0x0d, 0x50, 0x57, 0x00, 0x00, 0x0d, 0x50, 0x57, 0x00, 0x00, 0x0d, 0x50, 0x57, 0x0f, 0xf0, 0x0d, 0x50, 0x57, 0x00, 0x00, 0xcd, 0x50, 0x55, 0xc0, 0x03, 0x35, 0x50, 0x55, 0x7f, 0xff, 0xd5, 0x50, 0x55, 0xc3, 0xc3, 0xd5, 0x50, 0x12, 0x0c, 0x57, 0xf5, 0x5f, 0xd5, 0x50, 0x5f, 0xfd, 0x7f, 0xf5, 0x50, 0x5f, 0xff, 0xff, 0xf5, 0x50, 0x5f, 0xff, 0xff, 0xf5, 0x50, 0x5c, 0x00, 0x00, 0x35, 0x50, 0x70, 0x00, 0x00, 0x0d, 0x50, 0x70, 0x30, 0x0c, 0x0d, 0x50, 0x70, 0xc0, 0x03, 0x0d, 0x50, 0x70, 0x03, 0xc0, 0x0d, 0x50, 0x5c, 0x0f, 0xf0, 0x35, 0x50, 0x57, 0xff, 0xff, 0xd5, 0x50, 0x55, 0xcc, 0x33, 0x55, 0x50, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfa, 0xaa, 0xab, 0xc0, 0xff, 0xe5, 0x55, 0x5a, 0xc0, 0xff, 0xe5, 0x55, 0x5a, 0xc0, 0xff, 0x95, 0x55, 0x66, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0xaa, 0xaa, 0xab, 0xc0, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfe, 0xaa, 0xaa, 0xc0, 0xff, 0xfe, 0x55, 0x56, 0xc0, 0xff, 0xfe, 0x55, 0x56, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xea, 0xaa, 0xaa, 0xc0, 0xff, 0xea, 0xaa, 0xaa, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0xaa, 0xaa, 0xab, 0xc0, 0x08, 0x08, 0x7f, 0xf5, 0xff, 0xfd, 0xc3, 0x0d, 0xff, 0xfd, 0xff, 0xfd, 0xfc, 0xfd, 0x7f, 0xf5, 0x77, 0x75, 0x10, 0x03, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xc0, 0x03, 0x03, 0xff, 0xff, 0xff, 0xff, 0x10, 0x03, 0x55, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x03, 0x55, 0x55, 0xff, 0xff, 0x55, 0x08, 0x08, 0x55, 0x75, 0x55, 0x75, 0x55, 0x75, 0x5f, 0x75, 0x70, 0xf5, 0x70, 0xd5, 0x5f, 0x55, 0x55, 0x55, 0x08, 0x08, 0x55, 0x75, 0x55, 0x75, 0x55, 0x75, 0x5f, 0x75, 0x7f, 0xf5, 0x7f, 0xd5, 0x5f, 0x55, 0x55, 0x55, 0x08, 0x08, 0x55, 0xd5, 0x55, 0xf5, 0x55, 0xfd, 0x7d, 0xdd, 0xff, 0xd5, 0xff, 0x55, 0x7d, 0x55, 0x55, 0x55, 0x08, 0x08, 0x5f, 0xfd, 0x5d, 0x5d, 0x5d, 0x5d, 0x5d, 0x5d, 0xfd, 0xfd, 0xfd, 0xfd, 0xf5, 0xf5, 0x55, 0x55, 0x01, 0x01, 0x00, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x7f, 0xfd, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x5f, 0xfd, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x7f, 0xfd, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x5f, 0xfd, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x7f, 0xfd, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0x03, 0x5f, 0xfd, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x08, 0x08, 0x50, 0x05, 0x43, 0xc1, 0x00, 0x00, 0x30, 0xcc, 0x33, 0x0c, 0x00, 0x00, 0x43, 0xc1, 0x50, 0x05, 0x08, 0x08, 0xc0, 0x03, 0x33, 0xcc, 0x00, 0x30, 0x33, 0x0c, 0x30, 0xcc, 0x0c, 0x00, 0x33, 0xcc, 0xc0, 0x03, 0x08, 0x08, 0x57, 0xd5, 0x5c, 0x35, 0x5c, 0x35, 0xdc, 0x37, 0xd7, 0xd7, 0xdf, 0xf7, 0xfd, 0x7f, 0xf7, 0xdf, 0x04, 0x1f, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x02, 0x05, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0x06, 0x20, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0x20, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf7, 0xff, 0x5f, 0x5f, 0xd7, 0xff, 0x75, 0x5d, 0x55, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x57, 0xd5, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x55, 0x75, 0x75, 0x7f, 0xdf, 0xd5, 0x75, 0x75, 0x55, 0x75, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x55, 0x5f, 0xd5, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x08, 0x7f, 0x5f, 0x57, 0xd7, 0x57, 0xd5, 0x75, 0xdd, 0x77, 0x57, 0xdf, 0x75, 0xdd, 0x77, 0x57, 0xd7, 0x75, 0xdf, 0xf7, 0x55, 0x7d, 0x5f, 0x5d, 0x77, 0xf7, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x0c, 0x7f, 0x5f, 0x5d, 0x5d, 0xfd, 0xd5, 0x75, 0xdf, 0x7d, 0xd5, 0xdf, 0x75, 0xdf, 0xfd, 0xfd, 0xd7, 0x7f, 0xdd, 0xdd, 0xd5, 0x7f, 0x75, 0xdd, 0x5d, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7d, 0x75, 0x77, 0xf7, 0xf5, 0xd7, 0x75, 0x77, 0x57, 0x5d, 0xd7, 0x5d, 0xd7, 0xf7, 0x5d, 0xd7, 0x5d, 0xd7, 0x57, 0xf5, 0x7d, 0x57, 0x57, 0xf7, 0x5d, 0x55, 0x55, 0x55, 0x55, 0x55, 0x20, 0x0c, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xff, 0x55, 0xc3, 0x7d, 0x55, 0x55, 0x55, 0x70, 0x00, 0xd5, 0x70, 0xff, 0x55, 0x55, 0x55, 0xc0, 0x00, 0x35, 0x7c, 0x3f, 0xd5, 0x55, 0x57, 0x00, 0x03, 0x0d, 0x5f, 0xff, 0xff, 0xff, 0xfc, 0x03, 0x00, 0x0d, 0x70, 0x00, 0x03, 0xc0, 0x00, 0x00, 0x3f, 0xfd, 0x7f, 0xff, 0xfc, 0x30, 0x00, 0x00, 0xc0, 0x03, 0xc0, 0x00, 0x03, 0x30, 0x00, 0x03, 0x0f, 0xfc, 0xc0, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc0, 0x03, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x01, 0x01, 0x00, 0x10, 0x10, 0x55, 0x7d, 0x55, 0xf5, 0x55, 0xc3, 0x57, 0x0d, 0x55, 0xc0, 0xdc, 0x0d, 0x55, 0x70, 0xdc, 0x3d, 0x55, 0x5c, 0x30, 0x35, 0x55, 0x70, 0x00, 0xd5, 0x55, 0xc3, 0xfc, 0xd5, 0x55, 0xcf, 0xff, 0x35, 0x57, 0x0f, 0xff, 0x35, 0x57, 0x00, 0xfc, 0x35, 0x57, 0xc0 };\r\n\r\n\r\nvoid EXTI0_IRQHandler() {\r\n\r\n\t//GPIO_SetBits(GPIOB, GPIO_Pin_14);\r\n //if (EXTI_GetITStatus(EXTI_Line0) != RESET) {\r\n if(started){\r\n \tif(read){\r\n\r\n \t\tread = 2;\r\n \t}\r\n \tread = 1;\r\n \t//GPIO_SetBits(GPIOB, GPIO_Pin_14);\r\n \ta = 0;\r\n \tacount = 0;\r\n //\tas[loops++] = a;\r\n \t//as[loops++] = acount;\r\n \tas[loops++] = hit;\r\n \thit = 0;\r\n\r\n\r\n }\r\n EXTI_ClearITPendingBit(EXTI_Line0);\r\n //}\r\n\t//GPIO_ResetBits(GPIOB, GPIO_Pin_14);\r\n}\r\n\r\nvoid EXTI1_IRQHandler() {\r\n\t//hit++;\r\n\t//if (EXTI_GetITStatus(EXTI_Line1) != RESET) {\r\n\r\n \tif(read){\r\n\r\n \t//\ta = a << 1;\r\n \t//\tGPIO_SetBits(GPIOB, GPIO_Pin_15);\r\n \t\t// a = a | (GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_8));\r\n\r\n \t\t(GPIOD->IDR & GPIO_Pin_8) ? (a = ((a << 1)|1) ) : (a <<= 1);\r\n\r\n \t\t//GPIO_ResetBits(GPIOB, GPIO_Pin_15);\r\n \t\tacount++;\r\n\t\t//\t if(acount > 32){\r\n\r\n\t\t\t//\t\t GPIO_SetBits(GPIOD, GPIO_Pin_15);\r\n\t\t\t\t// }\r\n\r\n \t\tif (acount ==32){\r\n \t\t\tread = 0;\r\n\r\n \t\t\t //if((a & 0xff000000) != 0x03000000){\r\n\r\n \t\t\t\t//\t GPIO_SetBits(GPIOD, GPIO_Pin_14);\r\n \t\t\t\t// }\r\n\r\n \t\t\tas[loops++] = a;\r\n\r\n \t\t\t a = 0xffffff & a;\r\n\r\n \t\t\t// index = (loops % 800) / 100;\r\n \t\t\t/* if(loops > 100){\r\n \t\t\t\t loops = 0;\r\n \t\t\t\t index++;\r\n \t\t\t\t if (index > 7)\r\n \t\t\t\t\t index = 0;\r\n \t\t\t }\r\n \t\t\tfor(i = 0; i < 105; i++){\r\n\r\n \t\t\t\tv[0xe0 + i] = vs[index][i];\r\n \t\t\t}*/\r\n\r\n\r\n \t\t\tval = v[a++];\r\n\r\n \t\t//\tas[loops++] = val;\r\n \t\t//\tas[loops++] = val;\r\n \t\t\tc = 0x80;\r\n \t\t\tif(val&c){\r\n \t\t\t\t\t\t GPIO_SetBits(GPIOD, GPIO_Pin_4);\r\n \t\t\t \t\t }else{\r\n \t\t\t \t\t\t GPIO_ResetBits(GPIOD, GPIO_Pin_4);\r\n\r\n \t\t\t \t\t }\r\n\r\n \t\t\t \t\t c = c >> 1;\r\n \t\t\t \t\t started = 1;\r\n \t\t}\r\n\r\n \t}else{\r\n \t\t if(val&c){\r\n \t\t\t GPIOD->BSRRL = GPIO_Pin_4;\r\n \t\t }else{\r\n \t\t\t GPIOD->BSRRH = GPIO_Pin_4;\r\n\r\n \t\t }\r\n\r\n \t\t c = c >> 1;\r\n \t\t if(c==0){\r\n \t\t\t c = 0x80;\r\n \t\t\t val = v[a++];\r\n \t\t\t // as[loops++] = val;\r\n\r\n \t\t }\r\n \t\t //as[loops++] = 2;\r\n \t}\r\n\r\n \tEXTI_ClearITPendingBit(EXTI_Line1);\r\n\r\n //}\r\n\r\n\r\n}\r\n\r\n\r\n\r\n\r\n/**\r\n * @brief Main program.\r\n * @param None\r\n * @retval None\r\n */\r\nuint32_t getAddress();\r\n\r\n\r\nint main(void)\r\n{\r\n RCC_ClocksTypeDef RCC_Clocks;\r\n\r\n int l = 0;\r\n\r\n /* Initialize LEDs and User_Button on STM32F4-Discovery --------------------*/\r\n\r\n RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE);\r\n RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE);\r\n /* SysTick end of count event each 10ms */\r\n // RCC_GetClocksFreq(&RCC_Clocks);\r\n // SysTick_Config(RCC_Clocks.HCLK_Frequency / 100);\r\n\r\n GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_8 ;\r\n GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r\n GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r\n GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;\r\n GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r\n GPIO_Init(GPIOD, &GPIO_InitStructure);\r\n\r\n GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;\r\n GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r\n GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r\n GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;\r\n GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;\r\n GPIO_Init(GPIOD, &GPIO_InitStructure);\r\n\r\n GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_13| GPIO_Pin_14| GPIO_Pin_15;\r\n GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;\r\n GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r\n GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;\r\n GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r\n GPIO_Init(GPIOD, &GPIO_InitStructure);\r\n\r\n\r\n GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14 | GPIO_Pin_15;\r\n GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;\r\n GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r\n GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;\r\n GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r\n GPIO_Init(GPIOB, &GPIO_InitStructure);\r\n\r\n\r\n EXTILine0_Config();\r\n GPIO_SetBits(GPIOD, GPIO_Pin_12);\r\n // GPIO_SetBits(GPIOD, GPIO_Pin_14);\r\n// GPIO_SetBits(GPIOD, GPIO_Pin_12);\r\n // GPIO_ResetBits(GPIOB, GPIO_Pin_14);\r\n //GPIO_SetBits(GPIOB, GPIO_Pin_14);\r\n vs[0] = v1;\r\n vs[1] = v2;\r\n vs[2] = v3;\r\n vs[3] = v2;\r\n vs[4] = v4;\r\n vs[5] = v5;\r\n vs[6] = v6;\r\n vs[7] = v7;\r\n while(1){\r\n\r\n\t// GPIO_SetBits(GPIOB, GPIO_Pin_14);\r\n\t // GPIO_ResetBits(GPIOB, GPIO_Pin_14);\r\n\r\n\t // printf(\"here\");\r\n/*\t uint32_t a, j;\r\n\t uint8_t t, c, i;\r\n\t flag = 1;\r\n\t if(started)\r\n\t \t while(GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_0)){\r\n\t \t\t l++;\r\n\t \t }\r\n\r\n\t a = getAddress();\r\n\t // if(a < 0 || a > 200){\r\n\r\n\t\t// GPIO_SetBits(GPIOD, GPIO_Pin_14);\r\n\t //}\r\n\t started = 1;\r\n\t while(flag){\r\n\t t = v[a];\r\n\t c = 0x80;\r\n\t for( i = 0; (i < 8); i++){\r\n//\tif(a > 200){\r\n\r\n\t//\tloops++;\r\n//\t}\r\n\r\n\t if(t&c){\r\n\t\t GPIO_SetBits(GPIOD, GPIO_Pin_4);\r\n\t }else{\r\n\t\t GPIO_ResetBits(GPIOD, GPIO_Pin_4);\r\n\r\n\t }\r\n\r\n\t // if(!flag)\r\n\t \t//\t\t break;\r\n\t c = c >> 1;\r\n\t// q = ;\r\n\t// while((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)== Bit_RESET) && (GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_9) == Bit_RESET)){}\r\n\t // while(GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11) && (GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_9) == Bit_RESET) ){}\r\n//\t l = 0;\r\n\t //while((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)== Bit_SET) && flag ){}\r\n\t// as[loops++] = q;\r\n\t // q = 0;\r\n\t while((!GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)) && flag ){\r\n\r\n\r\n\t }\r\n\r\n\r\n\t//\t if((l++ % 100) == 99){\r\n\t\t//\t if((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_9) != Bit_RESET))\r\n\t//\t\t\t break;\r\n//\t\t }\r\n\r\n\t // as[loops++] = q;\r\n\t \t// q = 0;\r\n\r\n\r\n\r\n\t// l = 0;\r\n\t while(GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)){\r\n\t\t //q++;\r\n\t }\r\n\r\n\t //as[loops++] = q;\r\n\r\n\t//\t\t if((l++ % 100) == 99){\r\n\t\t//\t\t\t if((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_9) != Bit_RESET))\r\n\t\t\t//\t\t\t break;\r\n\t\t\t//\t }\r\n//\r\n\t// for(j=0; j < 1000000; j++){\r\n\r\n\t // }\r\n\t // }\r\n\r\n\t // if(flag)\r\n\t\t// loop++;\r\n\r\n\t }\r\n\t a++;\r\n\t }\r\n\r\n\r\n\t // as[loops++] = a;\r\n\r\n*/\r\n\r\n}\r\n\r\n}\r\n\r\nuint32_t getAddress(){\r\n\tuint32_t a, i;\r\n\t\ta = 0;\r\n\t\t for(i = 0; i < 32; i++){\r\n\r\n\r\n\t\t while(GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)== Bit_RESET){}\r\n\t\t //a++;\r\n\t\t a = a << 1;\r\n\t\t a = a + (GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_10)? 1:0);\r\n\r\n\t\t // if(i!=31)\r\n\t\t\t while(GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)){}\r\n\t }\r\n\r\n\t\t if((a & 0xff000000) != 0x03000000){\r\n\r\n\t\t\t// GPIO_SetBits(GPIOD, GPIO_Pin_15);\r\n\t\t }\r\n\r\n\t//\t as[loops++] = a;\r\n\t\t return a & 0x00ffffff;\r\n\r\n\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n\r\n/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "demos/nataliemain.c", "content": "/**\r\n ******************************************************************************\r\n * @file main.c\r\n * @author MCD Application Team\r\n * @version V1.0.0\r\n * @date 19-September-2011\r\n * @brief Main program body\r\n ******************************************************************************\r\n * @attention\r\n *\r\n * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r\n * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r\n * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r\n * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r\n * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r\n * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r\n *\r\n *

© COPYRIGHT 2011 STMicroelectronics

\r\n ******************************************************************************\r\n */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n//#include \"main.h\"\r\n#include \"stm32f4_discovery.h\"\r\n//#include \"stm32f4xx_it.c\"\r\nuint8_t flag;\r\n//#include \r\n/** @addtogroup STM32F4-Discovery_Demo\r\n * @{\r\n */\r\nint i;\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n\r\n\r\n//#define CLK GPIO_Pin_11\r\n//#define ADDRESS GPIO_Pin_10\r\n//#define E GPIO_Pin_9\r\nEXTI_InitTypeDef EXTI_InitStructure;\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n\r\n\r\n//uint32_t a = 0;\r\n//int i;\r\nint index;\r\nint started = 0;\r\n/* Private function prototypes -----------------------------------------------*/\r\n\r\nGPIO_InitTypeDef GPIO_InitStructure;\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\nvoid EXTILine0_Config(void)\r\n{\r\n\r\n GPIO_InitTypeDef GPIO_InitStructure;\r\n NVIC_InitTypeDef NVIC_InitStructure;\r\n\r\n /* Enable GPIOA clock */\r\n RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);\r\n /* Enable SYSCFG clock */\r\n RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);\r\n\r\n /* Configure PA0 pin as input floating */\r\n GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r\n GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;\r\n GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;\r\n GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;\r\n GPIO_Init(GPIOA, &GPIO_InitStructure);\r\n\r\n GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r\n GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r\n GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;\r\n GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1;\r\n GPIO_Init(GPIOA, &GPIO_InitStructure);\r\n\r\n /* Connect EXTI Line0 to PA0 pin */\r\n SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOA, EXTI_PinSource0);\r\n\r\n /* Configure EXTI Line0 */\r\n EXTI_InitStructure.EXTI_Line = EXTI_Line0;\r\n EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;\r\n EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;\r\n EXTI_InitStructure.EXTI_LineCmd = ENABLE;\r\n EXTI_Init(&EXTI_InitStructure);\r\n\r\n /* Enable and set EXTI Line0 Interrupt to the lowest priority */\r\n NVIC_InitStructure.NVIC_IRQChannel = EXTI0_IRQn;\r\n NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x01;\r\n NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x01;\r\n NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r\n NVIC_Init(&NVIC_InitStructure);\r\n\r\n SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOA, EXTI_PinSource1);\r\n\r\n /* Configure EXTI Line0 */\r\n EXTI_InitStructure.EXTI_Line = EXTI_Line1;\r\n EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;\r\n EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;\r\n EXTI_InitStructure.EXTI_LineCmd = ENABLE;\r\n EXTI_Init(&EXTI_InitStructure);\r\n\r\n /* Enable and set EXTI Line0 Interrupt to the lowest priority */\r\n NVIC_InitStructure.NVIC_IRQChannel = EXTI1_IRQn;\r\n NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x02;\r\n NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x01;\r\n NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r\n NVIC_Init(&NVIC_InitStructure);\r\n\r\n\r\n\r\n}\r\n\r\nint loops = 0;\r\nint hit = 0;\r\nint q;\r\nint as[2000];\r\nint read = 1;\r\nuint32_t a = 0;\r\nint acount = 0;\r\nuint8_t val;\r\nuint8_t c;\r\n\r\nuint8_t *vs[8];\r\nuint8_t v1[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0x29, 0xc0, 0xff, 0xca, 0x9f, 0x28, 0xc0, 0xff, 0xca, 0xa7, 0x67, 0xc0, 0xff, 0xda, 0xa8, 0xa7, 0xc0, 0xff, 0xda, 0xaa, 0xa3, 0xc0, 0xff, 0x2a, 0xaa, 0x9f, 0xc0, 0xff, 0x69, 0xaa, 0x8f, 0xc0, 0xff, 0x65, 0xaa, 0x8f, 0xc0, 0xfc, 0xa4, 0xaa, 0x7f, 0xc0, 0xfd, 0xa0, 0xaa, 0x7f, 0xc0, 0xf2, 0xa3, 0x6a, 0x7f, 0xc0, 0xf2, 0x9f, 0x6a, 0x3f, 0xc0, 0xfa, 0x8f, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0};\r\nuint8_t v2[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0x6a, 0x7f, 0xc0, 0xff, 0xfd, 0xaa, 0x3f, 0xc0, 0xff, 0xf2, 0xaa, 0x3f, 0xc0, 0xff, 0xf6, 0xa9, 0xff, 0xc0, 0xff, 0xda, 0xa9, 0xff, 0xc0, 0xff, 0x2a, 0xa9, 0xff, 0xc0, 0xff, 0x6a, 0xa8, 0xff, 0xc0, 0xfc, 0xa4, 0xa8, 0xff, 0xc0, 0xfd, 0xa0, 0xa7, 0xff, 0xc0, 0xf2, 0x91, 0xa7, 0xff, 0xc0, 0xfa, 0x82, 0xa7, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0};\r\nuint8_t v3[] = { 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfa, 0xaa, 0xab, 0xc0, 0xff, 0xfa, 0xaa, 0xaf, 0xc0, 0xff, 0xfa, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xea, 0xbf, 0xff, 0xc0, 0xff, 0xea, 0xff, 0xff, 0xc0, 0xff, 0xea, 0xff, 0xff, 0xc0, 0xff, 0xaa, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0};\r\n\r\nuint8_t v4[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xaa, 0xff, 0xc0, 0xff, 0xff, 0xab, 0xff, 0xc0, 0xff, 0xfe, 0xab, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xff, 0xff, 0xc0, 0xff, 0xea, 0xff, 0xff, 0xc0, 0xff, 0xeb, 0xff, 0xff, 0xc0, 0xff, 0xeb, 0xff, 0xff, 0xc0, 0xff, 0xab, 0xea, 0xff, 0xc0, 0xff, 0xaa, 0xaa, 0xff, 0xc0, 0xff, 0xaa, 0xaa, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0 };\r\nuint8_t v5[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xea, 0xff, 0xc0, 0xff, 0xff, 0xea, 0xff, 0xc0, 0xff, 0xff, 0xeb, 0xff, 0xc0, 0xff, 0xff, 0xeb, 0xff, 0xc0, 0xff, 0xff, 0xab, 0xff, 0xc0, 0xff, 0xff, 0xaf, 0xff, 0xc0, 0xff, 0xff, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xbf, 0xff, 0xc0, 0xff, 0xfe, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0};\r\n\r\nuint8_t v6[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xaa, 0xaa, 0xc0, 0xff, 0xff, 0xaa, 0xaa, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfa, 0xaa, 0xff, 0xc0, 0xff, 0xfa, 0xab, 0xff, 0xc0, 0xff, 0xfa, 0xff, 0xff, 0xc0, 0xff, 0xea, 0xff, 0xff, 0xc0, 0xff, 0xea, 0xff, 0xff, 0xc0, 0xff, 0xea, 0xab, 0xff, 0xc0, 0xff, 0xaa, 0xab, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0};\r\nuint8_t v7[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xeb, 0xff, 0xc0, 0xff, 0xff, 0xab, 0xff, 0xc0, 0xff, 0xfe, 0xab, 0xff, 0xc0, 0xfe, 0xaa, 0xaa, 0xab, 0xc0, 0xff, 0xaa, 0xaa, 0xbf, 0xc0, 0xff, 0xea, 0xab, 0xff, 0xc0, 0xff, 0xea, 0xab, 0xff, 0xc0, 0xff, 0xaa, 0xab, 0xff, 0xc0, 0xff, 0xaf, 0xab, 0xff, 0xc0, 0xfe, 0xff, 0xeb, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0};\r\n\r\nuint8_t v[] =\r\n{ 0x0a, 0xaa, 0x55, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0-f\r\n 0x00, 0xaa, 0x55, 0x03, 0x03, 0x03, 0x00, 0x00, 0x10, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //10-f\r\n 0x40, 0x00, 0x00, 0xc4, 0x00, 0x00, 0xdc, 0x00, 0x00, 0x0f, 0x01, 0x00, 0x91, 0x01, 0x00, 0x0d, //20\r\n 0x02, 0x00, 0x89, 0x02, 0x00, 0xd1, 0x02, 0x00, 0x1f, 0x06, 0x00, 0x67, 0x0f, 0x00, 0x67, 0x0f,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //40\r\n 0x41, 0x12, 0x00, 0xa7, 0x12, 0x00, 0x0d, 0x13, 0x00, 0x73, 0x13, 0x00, 0xd9, 0x13, 0x00, 0x3f,\r\n 0x14, 0x00, 0xa5, 0x14, 0x00, 0x0b, 0x15, 0x00, 0x71, 0x15, 0x00, 0xd7, 0x15, 0x00, 0x3d, 0x16,\r\n 0x00, 0xa3, 0x16, 0x00, 0x09, 0x17, 0x00, 0x6f, 0x17, 0x00, 0xd5, 0x17, 0x00, 0x3b, 0x18, 0x00,\r\n 0xa1, 0x18, 0x00, 0x07, 0x19, 0x00, 0x6d, 0x19, 0x00, 0xd3, 0x19, 0x00, 0x39, 0x1a, 0x00, 0x9f, //80\r\n 0x1a, 0x00, 0x05, 0x1b, 0x00, 0x6b, 0x1b, 0x00, 0xd1, 0x1b, 0x00, 0x37, 0x1c, 0x00, 0x9d, 0x1c, //90\r\n 0x00, 0x13, 0x1e, 0x00, 0x89, 0x1f, 0x00, 0xff, 0x20, 0x00, 0x75, 0x22, 0x00, 0xeb, 0x23, 0x00,\r\n 0x61, 0x25, 0x00, 0xd7, 0x26, 0x00, 0x4d, 0x28, 0x00, 0xeb, 0x28, 0x00, 0x89, 0x29, 0x00, 0x64, //b0\r\n 0x2a, 0x00, 0xa2, 0x2a, 0x00, 0xe0, 0x2a, 0x00, 0x1e, 0x2b, 0x00, 0x5c, 0x2b, 0x00, 0xce, 0x00, //c0\r\n 0x00, 0xce, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x44, 0x12, 0x34, 0x11, 0x15, //d0\r\n 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xaa, 0xa, 0xa0, 0x0, 0x0, 0x2a, 0x81, 0x80, 0x0, 0x0, 0x1a, 0x91, 0x80, 0x0, 0x0, 0x15, 0xa5, 0x80, 0x0, 0x0, 0x14, 0xa9, 0x80, 0x0, 0x0, 0x14, 0x2a, 0x80, 0x0, 0x0, 0x28, 0xa, 0x80, 0x0, 0x0, 0xaa, 0x2, 0x80, 0x0, 0x0, 0x0, 0x0, 0xa, 0xa9, 0x0, 0x0, 0x0, 0x1a, 0x19, 0x0, 0x0, 0x0, 0x2a, 0x9, 0x0, 0x0, 0x0, 0x1a, 0xa4, 0x0, 0x0, 0x0, 0x2, 0xa9, 0x0, 0x0, 0x0, 0x24, 0x2a, 0x0, 0x0, 0x0, 0x28, 0x29, 0x0, 0x0, 0x0, 0x2a, 0xa8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,\r\n\r\n\r\n\r\n // 0x0, 0xcf, 0xff, 0x0, 0x0, 0x0, 0x0, 0xcf, 0xff, 0x0, 0x0, 0x0, 0x0,\r\n // 0xcf, 0xff, 0x0, 0x0, 0xc, 0xff, 0xff, 0xff, 0x0, 0x0, 0xff, 0xff,\r\n // 0xff, 0xff, 0x0, 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n //0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n // 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n // 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0x0, 0x0, 0x0, 0x0, 0xC0, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF,\r\n 0x00, 0x00, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF,\r\n 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFA, 0xAA,\r\n 0xAB, 0xC0, 0xFF, 0xE5, 0x55, 0x5A, 0xC0, 0x00, 0xE5, 0x55, 0x5A, 0xC0, 0xFF, 0x95, 0x55, 0x66,\r\n 0xC0, 0xFF, 0xAA, 0xAA, 0xA6, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x8A, 0x28, 0x26, 0xC0,\r\n 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x8A, 0x28, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF,\r\n 0x80, 0x00, 0x26, 0xC0, 0xFF, 0xAA, 0xAA, 0xAB, 0xC0, 0x11, 0x15, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0,\r\n\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0x00, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF,\r\n 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFA, 0xAA, 0xAB, 0xC0, 0xFF, 0xE5, 0x55,\r\n 0x5A, 0xC0, 0xFF, 0xE5, 0x55, 0x5A, 0xC0, 0xFF, 0x95, 0x55, 0x66, 0xC0, 0xFF, 0xAA, 0xAA, 0xA6,\r\n 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x8A, 0x28, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0,\r\n 0xFF, 0x8A, 0x28, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF,\r\n 0xAA, 0xAA, 0xAB, 0xC0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};// 0x70, 0x2c, 0x00, 0x82, 0x2c, 0x00, 0x90, 0x2c, 0x00, 0x9e, 0x2c, 0x00, 0xb0, 0x2c, 0x00, 0xc2, 0x2c, 0x00, 0xd4, 0x2c, 0x00, 0xe6, 0x2c, 0x00, 0xe9, 0x2c, 0x00, 0x1b, 0x2d, 0x00, 0x4d, 0x2d, 0x00, 0x7f, 0x2d, 0x00, 0xb1, 0x2d, 0x00, 0xe3, 0x2d, 0x00, 0x15, 0x2e, 0x00, 0x27, 0x2e, 0x00, 0x39, 0x2e, 0x00, 0x4b, 0x2e, 0x00, 0x6c, 0x2e, 0x00, 0x73, 0x2e, 0x00, 0xb5, 0x2e, 0x00, 0xf7, 0x2e, 0x00, 0x21, 0x2f, 0x00, 0x5f, 0x2f, 0x00, 0xc1, 0x2f, 0x00, 0x02, 0x00, 0x06, 0x03, 0x04, 0x09, 0x0a, 0x05, 0x08, 0x07, 0x00, 0x00, 0x58, 0x00, 0x00, 0x32, 0x00, 0x00, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x10, 0x00, 0x00, 0x08, 0x00, 0x00, 0x50, 0x04, 0x00, 0x30, 0x02, 0x00, 0x20, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00, 0x50, 0x08, 0x00, 0x50, 0x11, 0x00, 0x00, 0x00, 0x28, 0x00, 0x40, 0x15, 0x00, 0x60, 0x12, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x45, 0x00, 0x00, 0x35, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x22, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00, 0x22, 0x00, 0x00, 0x13, 0x00, 0x01, 0x00, 0x02, 0x00, 0x50, 0x01, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x04, 0xff, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x02, 0xff, 0x01, 0x01, 0x00, 0x1e, 0x01, 0x00, 0x03, 0xff, 0x01, 0x01, 0x00, 0x2d, 0x01, 0x00, 0x04, 0xfe, 0x01, 0x01, 0x00, 0x3c, 0x01, 0x00, 0x05, 0xfe, 0x01, 0x01, 0x00, 0x4b, 0x02, 0x00, 0x06, 0xfe, 0x02, 0x02, 0x00, 0x5a, 0x02, 0x00, 0x07, 0xfd, 0x02, 0x02, 0x00, 0x63, 0x02, 0x00, 0x08, 0xfd, 0x02, 0x02, 0x00, 0x64, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0x00, 0x02, 0x04, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x02, 0xff, 0x01, 0x01, 0x00, 0x0f, 0x01, 0x00, 0x03, 0xff, 0x01, 0x01, 0x00, 0x19, 0x01, 0x00, 0x04, 0xfe, 0x01, 0x01, 0x00, 0x23, 0x01, 0x00, 0x05, 0xfe, 0x01, 0x02, 0x00, 0x2d, 0x02, 0x00, 0x06, 0xfe, 0x02, 0x02, 0x00, 0x37, 0x02, 0x00, 0x07, 0xfd, 0x02, 0x02, 0x00, 0x40, 0x02, 0x00, 0x08, 0xfd, 0x02, 0x02, 0x00, 0x41, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xc4, 0x2f, 0x00, 0xff, 0xff, 0xff, 0x06, 0x30, 0x00, 0x48, 0x30, 0x00, 0x8a, 0x30, 0x00, 0xcc, 0x30, 0x00, 0x0e, 0x31, 0x00, 0x50, 0x31, 0x00, 0x92, 0x31, 0x00, 0xd4, 0x31, 0x00, 0x16, 0x32, 0x00, 0xff, 0xff, 0xff, 0x58, 0x32, 0x00, 0xff, 0xff, 0xff, 0xba, 0x32, 0x00, 0x1c, 0x33, 0x00, 0x7e, 0x33, 0x00, 0xe0, 0x33, 0x00, 0x42, 0x34, 0x00, 0xa4, 0x34, 0x00, 0x06, 0x35, 0x00, 0x68, 0x35, 0x00, 0xca, 0x35, 0x00, 0xff, 0xff, 0xff, 0x2c, 0x36, 0x00, 0x3e, 0x36, 0x00, 0x80, 0x36, 0x00, 0xc2, 0x36, 0x00, 0x04, 0x37, 0x00, 0x46, 0x37, 0x00, 0x88, 0x37, 0x00, 0xca, 0x37, 0x00, 0x24, 0x38, 0x00, 0x9d, 0x38, 0x00, 0xf9, 0x38, 0x00, 0x7d, 0x39, 0x00, 0xd7, 0x39, 0x00, 0x50, 0x3a, 0x00, 0xac, 0x3a, 0x00, 0x30, 0x3b, 0x00, 0x72, 0x3b, 0x00, 0xb4, 0x3b, 0x00, 0xf6, 0x3b, 0x00, 0x38, 0x3c, 0x00, 0x7a, 0x3c, 0x00, 0xbc, 0x3c, 0x00, 0xfe, 0x3c, 0x00, 0x40, 0x3d, 0x00, 0x3a, 0x3e, 0x00, 0x34, 0x3f, 0x00, 0x2e, 0x40, 0x00, 0x28, 0x41, 0x00, 0x22, 0x42, 0x00, 0x98, 0x43, 0x00, 0xea, 0x43, 0x00, 0x3c, 0x44, 0x00, 0x8e, 0x44, 0x00, 0xe0, 0x44, 0x00, 0x32, 0x45, 0x00, 0x84, 0x45, 0x00, 0x7e, 0x46, 0x00, 0x78, 0x47, 0x00, 0xba, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0x76, 0x48, 0x00, 0xf0, 0x48, 0x00, 0x6a, 0x49, 0x00, 0xe4, 0x49, 0x00, 0x5e, 0x4a, 0x00, 0xd8, 0x4a, 0x00, 0x52, 0x4b, 0x00, 0xcc, 0x4b, 0x00, 0x46, 0x4c, 0x00, 0xc0, 0x4c, 0x00, 0x3a, 0x4d, 0x00, 0xb4, 0x4d, 0x00, 0x2e, 0x4e, 0x00, 0xa8, 0x4e, 0x00, 0x22, 0x4f, 0x00, 0x9c, 0x4f, 0x00, 0x16, 0x50, 0x00, 0x90, 0x50, 0x00, 0x0a, 0x51, 0x00, 0x84, 0x51, 0x00, 0xfe, 0x51, 0x00, 0x78, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0x6c, 0x53, 0x00, 0xe6, 0x53, 0x00, 0x60, 0x54, 0x00, 0xda, 0x54, 0x00, 0x54, 0x55, 0x00, 0xce, 0x55, 0x00, 0x48, 0x56, 0x00, 0xc2, 0x56, 0x00, 0x3c, 0x57, 0x00, 0xb6, 0x57, 0x00, 0x30, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0x24, 0x59, 0x00, 0x9e, 0x59, 0x00, 0x18, 0x5a, 0x00, 0x92, 0x5a, 0x00, 0x0c, 0x5b, 0x00, 0x86, 0x5b, 0x00, 0x00, 0x5c, 0x00, 0x7a, 0x5c, 0x00, 0xf4, 0x5c, 0x00, 0x6e, 0x5d, 0x00, 0xe8, 0x5d, 0x00, 0x62, 0x5e, 0x00, 0xdc, 0x5e, 0x00, 0x56, 0x5f, 0x00, 0xd0, 0x5f, 0x00, 0x4a, 0x60, 0x00, 0xc4, 0x60, 0x00, 0x3e, 0x61, 0x00, 0xb8, 0x61, 0x00, 0x32, 0x62, 0x00, 0xac, 0x62, 0x00, 0x26, 0x63, 0x00, 0xa0, 0x63, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x94, 0x64, 0x00, 0x0e, 0x65, 0x00, 0x88, 0x65, 0x00, 0x02, 0x66, 0x00, 0x7c, 0x66, 0x00, 0xf6, 0x66, 0x00, 0x70, 0x67, 0x00, 0xea, 0x67, 0x00, 0x64, 0x68, 0x00, 0xde, 0x68, 0x00, 0x58, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0x4c, 0x6a, 0x00, 0xc6, 0x6a, 0x00, 0x40, 0x6b, 0x00, 0xba, 0x6b, 0x00, 0x34, 0x6c, 0x00, 0xae, 0x6c, 0x00, 0x28, 0x6d, 0x00, 0xa2, 0x6d, 0x00, 0x1c, 0x6e, 0x00, 0x96, 0x6e, 0x00, 0x10, 0x6f, 0x00, 0x8a, 0x6f, 0x00, 0x04, 0x70, 0x00, 0x7e, 0x70, 0x00, 0xf8, 0x70, 0x00, 0x72, 0x71, 0x00, 0xec, 0x71, 0x00, 0x66, 0x72, 0x00, 0xe0, 0x72, 0x00, 0x5a, 0x73, 0x00, 0xd4, 0x73, 0x00, 0x4e, 0x74, 0x00, 0xc8, 0x74, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0xbc, 0x75, 0x00, 0x36, 0x76, 0x00, 0xb0, 0x76, 0x00, 0x2a, 0x77, 0x00, 0xa4, 0x77, 0x00, 0x1e, 0x78, 0x00, 0x98, 0x78, 0x00, 0x12, 0x79, 0x00, 0x8c, 0x79, 0x00, 0x06, 0x7a, 0x00, 0x80, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0x74, 0x7b, 0x00, 0xe2, 0x7b, 0x00, 0x50, 0x7c, 0x00, 0xbe, 0x7c, 0x00, 0x2c, 0x7d, 0x00, 0x9a, 0x7d, 0x00, 0x08, 0x7e, 0x00, 0x76, 0x7e, 0x00, 0xe4, 0x7e, 0x00, 0x52, 0x7f, 0x00, 0xc0, 0x7f, 0x00, 0x2e, 0x80, 0x00, 0x9c, 0x80, 0x00, 0x0a, 0x81, 0x00, 0x78, 0x81, 0x00, 0xe6, 0x81, 0x00, 0x54, 0x82, 0x00, 0xc2, 0x82, 0x00, 0x30, 0x83, 0x00, 0x9e, 0x83, 0x00, 0x0c, 0x84, 0x00, 0x7a, 0x84, 0x00, 0xe8, 0x84, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0xc4, 0x85, 0x00, 0x32, 0x86, 0x00, 0xa0, 0x86, 0x00, 0x0e, 0x87, 0x00, 0x7c, 0x87, 0x00, 0xea, 0x87, 0x00, 0x58, 0x88, 0x00, 0xc6, 0x88, 0x00, 0x34, 0x89, 0x00, 0xa2, 0x89, 0x00, 0x10, 0x8a, 0x00, 0x7e, 0x8a, 0x00, 0xec, 0x8a, 0x00, 0x2e, 0x8b, 0x00, 0xac, 0x8b, 0x00, 0x2a, 0x8c, 0x00, 0xa8, 0x8c, 0x00, 0x26, 0x8d, 0x00, 0xa4, 0x8d, 0x00, 0x22, 0x8e, 0x00, 0xa0, 0x8e, 0x00, 0x1e, 0x8f, 0x00, 0x60, 0x8f, 0x00, 0xa2, 0x8f, 0x00, 0xe4, 0x8f, 0x00, 0x13, 0x90, 0x00, 0x42, 0x90, 0x00, 0x65, 0x90, 0x00, 0x88, 0x90, 0x00, 0xab, 0x90, 0x00, 0xce, 0x90, 0x00, 0xf1, 0x90, 0x00, 0x57, 0x91, 0x00, 0xbd, 0x91, 0x00, 0x23, 0x92, 0x00, 0x89, 0x92, 0x00, 0xef, 0x92, 0x00, 0x55, 0x93, 0x00, 0xbb, 0x93, 0x00, 0x21, 0x94, 0x00, 0x87, 0x94, 0x00, 0xed, 0x94, 0x00, 0x53, 0x95, 0x00, 0xb9, 0x95, 0x00, 0x1f, 0x96, 0x00, 0x85, 0x96, 0x00, 0xeb, 0x96, 0x00, 0x51, 0x97, 0x00, 0xb7, 0x97, 0x00, 0x1d, 0x98, 0x00, 0x83, 0x98, 0x00, 0xe9, 0x98, 0x00, 0x4f, 0x99, 0x00, 0xb5, 0x99, 0x00, 0x1b, 0x9a, 0x00, 0x81, 0x9a, 0x00, 0xe7, 0x9a, 0x00, 0x4d, 0x9b, 0x00, 0xb3, 0x9b, 0x00, 0x19, 0x9c, 0x00, 0x7f, 0x9c, 0x00, 0xe5, 0x9c, 0x00, 0x4b, 0x9d, 0x00, 0xb1, 0x9d, 0x00, 0x17, 0x9e, 0x00, 0x7d, 0x9e, 0x00, 0xe3, 0x9e, 0x00, 0x49, 0x9f, 0x00, 0xaf, 0x9f, 0x00, 0x15, 0xa0, 0x00, 0x7b, 0xa0, 0x00, 0xe1, 0xa0, 0x00, 0x47, 0xa1, 0x00, 0xad, 0xa1, 0x00, 0x13, 0xa2, 0x00, 0x79, 0xa2, 0x00, 0xdf, 0xa2, 0x00, 0x45, 0xa3, 0x00, 0xab, 0xa3, 0x00, 0x11, 0xa4, 0x00, 0x77, 0xa4, 0x00, 0xdd, 0xa4, 0x00, 0x43, 0xa5, 0x00, 0xa9, 0xa5, 0x00, 0x0f, 0xa6, 0x00, 0x75, 0xa6, 0x00, 0xdb, 0xa6, 0x00, 0x41, 0xa7, 0x00, 0xa7, 0xa7, 0x00, 0x0d, 0xa8, 0x00, 0x73, 0xa8, 0x00, 0xd9, 0xa8, 0x00, 0x3f, 0xa9, 0x00, 0xa5, 0xa9, 0x00, 0x0b, 0xaa, 0x00, 0x71, 0xaa, 0x00, 0xd7, 0xaa, 0x00, 0x3d, 0xab, 0x00, 0xa3, 0xab, 0x00, 0x09, 0xac, 0x00, 0x6f, 0xac, 0x00, 0xd5, 0xac, 0x00, 0x3b, 0xad, 0x00, 0xa1, 0xad, 0x00, 0x07, 0xae, 0x00, 0x6d, 0xae, 0x00, 0xd3, 0xae, 0x00, 0x39, 0xaf, 0x00, 0x9f, 0xaf, 0x00, 0x05, 0xb0, 0x00, 0x6b, 0xb0, 0x00, 0xd1, 0xb0, 0x00, 0x37, 0xb1, 0x00, 0x9d, 0xb1, 0x00, 0x03, 0xb2, 0x00, 0x69, 0xb2, 0x00, 0xcf, 0xb2, 0x00, 0x35, 0xb3, 0x00, 0x9b, 0xb3, 0x00, 0x01, 0xb4, 0x00, 0x67, 0xb4, 0x00, 0xcd, 0xb4, 0x00, 0x33, 0xb5, 0x00, 0x99, 0xb5, 0x00, 0xff, 0xb5, 0x00, 0x65, 0xb6, 0x00, 0xcb, 0xb6, 0x00, 0x31, 0xb7, 0x00, 0x97, 0xb7, 0x00, 0xfd, 0xb7, 0x00, 0x63, 0xb8, 0x00, 0xc9, 0xb8, 0x00, 0x2f, 0xb9, 0x00, 0x95, 0xb9, 0x00, 0xfb, 0xb9, 0x00, 0x61, 0xba, 0x00, 0xc7, 0xba, 0x00, 0x2d, 0xbb, 0x00, 0x93, 0xbb, 0x00, 0xf9, 0xbb, 0x00, 0x5f, 0xbc, 0x00, 0xc5, 0xbc, 0x00, 0x2b, 0xbd, 0x00, 0x91, 0xbd, 0x00, 0xf7, 0xbd, 0x00, 0x5d, 0xbe, 0x00, 0xc3, 0xbe, 0x00, 0x29, 0xbf, 0x00, 0x8f, 0xbf, 0x00, 0xf5, 0xbf, 0x00, 0x5b, 0xc0, 0x00, 0xc1, 0xc0, 0x00, 0x27, 0xc1, 0x00, 0x8d, 0xc1, 0x00, 0xf3, 0xc1, 0x00, 0x59, 0xc2, 0x00, 0xbf, 0xc2, 0x00, 0x25, 0xc3, 0x00, 0x8b, 0xc3, 0x00, 0xf1, 0xc3, 0x00, 0x57, 0xc4, 0x00, 0xbd, 0xc4, 0x00, 0x23, 0xc5, 0x00, 0x89, 0xc5, 0x00, 0xef, 0xc5, 0x00, 0x55, 0xc6, 0x00, 0xbb, 0xc6, 0x00, 0x21, 0xc7, 0x00, 0x87, 0xc7, 0x00, 0xed, 0xc7, 0x00, 0x53, 0xc8, 0x00, 0xb9, 0xc8, 0x00, 0x1f, 0xc9, 0x00, 0x85, 0xc9, 0x00, 0xeb, 0xc9, 0x00, 0x51, 0xca, 0x00, 0xb7, 0xca, 0x00, 0x1d, 0xcb, 0x00, 0x83, 0xcb, 0x00, 0xe9, 0xcb, 0x00, 0x4f, 0xcc, 0x00, 0xb5, 0xcc, 0x00, 0x1b, 0xcd, 0x00, 0x81, 0xcd, 0x00, 0xe7, 0xcd, 0x00, 0x4d, 0xce, 0x00, 0xb3, 0xce, 0x00, 0x19, 0xcf, 0x00, 0x7f, 0xcf, 0x00, 0xe5, 0xcf, 0x00, 0x4b, 0xd0, 0x00, 0xb1, 0xd0, 0x00, 0x17, 0xd1, 0x00, 0x7d, 0xd1, 0x00, 0xe3, 0xd1, 0x00, 0x49, 0xd2, 0x00, 0xaf, 0xd2, 0x00, 0x15, 0xd3, 0x00, 0x7b, 0xd3, 0x00, 0xe1, 0xd3, 0x00, 0x47, 0xd4, 0x00, 0xad, 0xd4, 0x00, 0x13, 0xd5, 0x00, 0x79, 0xd5, 0x00, 0xdf, 0xd5, 0x00, 0x45, 0xd6, 0x00, 0xab, 0xd6, 0x00, 0x11, 0xd7, 0x00, 0x77, 0xd7, 0x00, 0xdd, 0xd7, 0x00, 0x43, 0xd8, 0x00, 0xa9, 0xd8, 0x00, 0x0f, 0xd9, 0x00, 0x75, 0xd9, 0x00, 0xdb, 0xd9, 0x00, 0x41, 0xda, 0x00, 0xa7, 0xda, 0x00, 0x0d, 0xdb, 0x00, 0x73, 0xdb, 0x00, 0xd9, 0xdb, 0x00, 0x3f, 0xdc, 0x00, 0xa5, 0xdc, 0x00, 0x0b, 0xdd, 0x00, 0x71, 0xdd, 0x00, 0xd7, 0xdd, 0x00, 0x3d, 0xde, 0x00, 0xa3, 0xde, 0x00, 0x09, 0xdf, 0x00, 0x6f, 0xdf, 0x00, 0xd5, 0xdf, 0x00, 0x3b, 0xe0, 0x00, 0xa1, 0xe0, 0x00, 0x07, 0xe1, 0x00, 0x6d, 0xe1, 0x00, 0xd3, 0xe1, 0x00, 0x39, 0xe2, 0x00, 0x9f, 0xe2, 0x00, 0x05, 0xe3, 0x00, 0x6b, 0xe3, 0x00, 0xd1, 0xe3, 0x00, 0x37, 0xe4, 0x00, 0x9d, 0xe4, 0x00, 0x03, 0xe5, 0x00, 0x69, 0xe5, 0x00, 0xcf, 0xe5, 0x00, 0x35, 0xe6, 0x00, 0x9b, 0xe6, 0x00, 0x01, 0xe7, 0x00, 0x67, 0xe7, 0x00, 0xcd, 0xe7, 0x00, 0x33, 0xe8, 0x00, 0x99, 0xe8, 0x00, 0xff, 0xe8, 0x00, 0x65, 0xe9, 0x00, 0xcb, 0xe9, 0x00, 0x31, 0xea, 0x00, 0x97, 0xea, 0x00, 0xfd, 0xea, 0x00, 0x63, 0xeb, 0x00, 0xc9, 0xeb, 0x00, 0x2f, 0xec, 0x00, 0x95, 0xec, 0x00, 0xfb, 0xec, 0x00, 0x61, 0xed, 0x00, 0xc7, 0xed, 0x00, 0x2d, 0xee, 0x00, 0x93, 0xee, 0x00, 0xf9, 0xee, 0x00, 0x5f, 0xef, 0x00, 0xc5, 0xef, 0x00, 0x2b, 0xf0, 0x00, 0x91, 0xf0, 0x00, 0xf7, 0xf0, 0x00, 0x5d, 0xf1, 0x00, 0xc3, 0xf1, 0x00, 0x29, 0xf2, 0x00, 0x8f, 0xf2, 0x00, 0xf5, 0xf2, 0x00, 0x5b, 0xf3, 0x00, 0xc1, 0xf3, 0x00, 0x27, 0xf4, 0x00, 0x8d, 0xf4, 0x00, 0xf3, 0xf4, 0x00, 0x59, 0xf5, 0x00, 0xbf, 0xf5, 0x00, 0x25, 0xf6, 0x00, 0x8b, 0xf6, 0x00, 0xf1, 0xf6, 0x00, 0x57, 0xf7, 0x00, 0xbd, 0xf7, 0x00, 0x23, 0xf8, 0x00, 0x89, 0xf8, 0x00, 0xef, 0xf8, 0x00, 0x55, 0xf9, 0x00, 0xbb, 0xf9, 0x00, 0x21, 0xfa, 0x00, 0x87, 0xfa, 0x00, 0xed, 0xfa, 0x00, 0x53, 0xfb, 0x00, 0xb9, 0xfb, 0x00, 0x1f, 0xfc, 0x00, 0x85, 0xfc, 0x00, 0xeb, 0xfc, 0x00, 0x51, 0xfd, 0x00, 0xb7, 0xfd, 0x00, 0x1d, 0xfe, 0x00, 0x83, 0xfe, 0x00, 0xe9, 0xfe, 0x00, 0x4f, 0xff, 0x00, 0xb5, 0xff, 0x00, 0x1b, 0x00, 0x01, 0x81, 0x00, 0x01, 0xe7, 0x00, 0x01, 0x4d, 0x01, 0x01, 0xb3, 0x01, 0x01, 0x19, 0x02, 0x01, 0x7f, 0x02, 0x01, 0xe5, 0x02, 0x01, 0x4b, 0x03, 0x01, 0xb1, 0x03, 0x01, 0x17, 0x04, 0x01, 0x7d, 0x04, 0x01, 0xe3, 0x04, 0x01, 0x49, 0x05, 0x01, 0xaf, 0x05, 0x01, 0x15, 0x06, 0x01, 0x7b, 0x06, 0x01, 0xe1, 0x06, 0x01, 0x47, 0x07, 0x01, 0xad, 0x07, 0x01, 0x13, 0x08, 0x01, 0x79, 0x08, 0x01, 0xdf, 0x08, 0x01, 0x45, 0x09, 0x01, 0xab, 0x09, 0x01, 0x11, 0x0a, 0x01, 0x77, 0x0a, 0x01, 0xdd, 0x0a, 0x01, 0x43, 0x0b, 0x01, 0xa9, 0x0b, 0x01, 0x0f, 0x0c, 0x01, 0x75, 0x0c, 0x01, 0xdb, 0x0c, 0x01, 0x41, 0x0d, 0x01, 0xa7, 0x0d, 0x01, 0x0d, 0x0e, 0x01, 0x73, 0x0e, 0x01, 0xd9, 0x0e, 0x01, 0x3f, 0x0f, 0x01, 0xa5, 0x0f, 0x01, 0x0b, 0x10, 0x01, 0x71, 0x10, 0x01, 0xd7, 0x10, 0x01, 0x3d, 0x11, 0x01, 0xa3, 0x11, 0x01, 0x09, 0x12, 0x01, 0x6f, 0x12, 0x01, 0xd5, 0x12, 0x01, 0x3b, 0x13, 0x01, 0xa1, 0x13, 0x01, 0x07, 0x14, 0x01, 0x6d, 0x14, 0x01, 0xd3, 0x14, 0x01, 0x39, 0x15, 0x01, 0x9f, 0x15, 0x01, 0x05, 0x16, 0x01, 0x6b, 0x16, 0x01, 0xd1, 0x16, 0x01, 0x37, 0x17, 0x01, 0x9d, 0x17, 0x01, 0x03, 0x18, 0x01, 0x69, 0x18, 0x01, 0xcf, 0x18, 0x01, 0x35, 0x19, 0x01, 0x9b, 0x19, 0x01, 0x01, 0x1a, 0x01, 0x67, 0x1a, 0x01, 0xcd, 0x1a, 0x01, 0x33, 0x1b, 0x01, 0x99, 0x1b, 0x01, 0xff, 0x1b, 0x01, 0x65, 0x1c, 0x01, 0xcb, 0x1c, 0x01, 0x31, 0x1d, 0x01, 0x97, 0x1d, 0x01, 0xfd, 0x1d, 0x01, 0x63, 0x1e, 0x01, 0xc9, 0x1e, 0x01, 0x2f, 0x1f, 0x01, 0x95, 0x1f, 0x01, 0xfb, 0x1f, 0x01, 0x61, 0x20, 0x01, 0xc7, 0x20, 0x01, 0x2d, 0x21, 0x01, 0x93, 0x21, 0x01, 0xf9, 0x21, 0x01, 0x5f, 0x22, 0x01, 0xc5, 0x22, 0x01, 0x2b, 0x23, 0x01, 0x91, 0x23, 0x01, 0xf7, 0x23, 0x01, 0x5d, 0x24, 0x01, 0xc3, 0x24, 0x01, 0x29, 0x25, 0x01, 0x8f, 0x25, 0x01, 0xf5, 0x25, 0x01, 0x5b, 0x26, 0x01, 0xc1, 0x26, 0x01, 0x27, 0x27, 0x01, 0x8d, 0x27, 0x01, 0xf3, 0x27, 0x01, 0x59, 0x28, 0x01, 0xbf, 0x28, 0x01, 0x25, 0x29, 0x01, 0x8b, 0x29, 0x01, 0xf1, 0x29, 0x01, 0x57, 0x2a, 0x01, 0xbd, 0x2a, 0x01, 0x23, 0x2b, 0x01, 0x89, 0x2b, 0x01, 0xef, 0x2b, 0x01, 0x55, 0x2c, 0x01, 0xbb, 0x2c, 0x01, 0x21, 0x2d, 0x01, 0x87, 0x2d, 0x01, 0xed, 0x2d, 0x01, 0x53, 0x2e, 0x01, 0xb9, 0x2e, 0x01, 0x1f, 0x2f, 0x01, 0x85, 0x2f, 0x01, 0xeb, 0x2f, 0x01, 0x51, 0x30, 0x01, 0xb7, 0x30, 0x01, 0x1d, 0x31, 0x01, 0x83, 0x31, 0x01, 0xe9, 0x31, 0x01, 0x4f, 0x32, 0x01, 0xb5, 0x32, 0x01, 0x1b, 0x33, 0x01, 0x81, 0x33, 0x01, 0xe7, 0x33, 0x01, 0x4d, 0x34, 0x01, 0xb3, 0x34, 0x01, 0x19, 0x35, 0x01, 0x7f, 0x35, 0x01, 0xe5, 0x35, 0x01, 0x4b, 0x36, 0x01, 0xb1, 0x36, 0x01, 0x17, 0x37, 0x01, 0x7d, 0x37, 0x01, 0xe3, 0x37, 0x01, 0x49, 0x38, 0x01, 0xaf, 0x38, 0x01, 0x15, 0x39, 0x01, 0x7b, 0x39, 0x01, 0xe1, 0x39, 0x01, 0x47, 0x3a, 0x01, 0xad, 0x3a, 0x01, 0x13, 0x3b, 0x01, 0x79, 0x3b, 0x01, 0xdf, 0x3b, 0x01, 0x45, 0x3c, 0x01, 0xab, 0x3c, 0x01, 0x11, 0x3d, 0x01, 0x77, 0x3d, 0x01, 0xdd, 0x3d, 0x01, 0x43, 0x3e, 0x01, 0xa9, 0x3e, 0x01, 0x0f, 0x3f, 0x01, 0x75, 0x3f, 0x01, 0xdb, 0x3f, 0x01, 0x41, 0x40, 0x01, 0xa7, 0x40, 0x01, 0x0d, 0x41, 0x01, 0x73, 0x41, 0x01, 0xd9, 0x41, 0x01, 0x3f, 0x42, 0x01, 0xa5, 0x42, 0x01, 0x0b, 0x43, 0x01, 0x71, 0x43, 0x01, 0xd7, 0x43, 0x01, 0x3d, 0x44, 0x01, 0xa3, 0x44, 0x01, 0x09, 0x45, 0x01, 0x6f, 0x45, 0x01, 0xd5, 0x45, 0x01, 0x3b, 0x46, 0x01, 0xa1, 0x46, 0x01, 0x07, 0x47, 0x01, 0x6d, 0x47, 0x01, 0xd3, 0x47, 0x01, 0x39, 0x48, 0x01, 0x9f, 0x48, 0x01, 0x05, 0x49, 0x01, 0x6b, 0x49, 0x01, 0xd1, 0x49, 0x01, 0x37, 0x4a, 0x01, 0x9d, 0x4a, 0x01, 0x03, 0x4b, 0x01, 0x69, 0x4b, 0x01, 0xcf, 0x4b, 0x01, 0x35, 0x4c, 0x01, 0x9b, 0x4c, 0x01, 0x01, 0x4d, 0x01, 0x67, 0x4d, 0x01, 0xcd, 0x4d, 0x01, 0x33, 0x4e, 0x01, 0x99, 0x4e, 0x01, 0xff, 0x4e, 0x01, 0x65, 0x4f, 0x01, 0xcb, 0x4f, 0x01, 0x31, 0x50, 0x01, 0x97, 0x50, 0x01, 0xfd, 0x50, 0x01, 0x63, 0x51, 0x01, 0xc9, 0x51, 0x01, 0x2f, 0x52, 0x01, 0x95, 0x52, 0x01, 0xfb, 0x52, 0x01, 0x61, 0x53, 0x01, 0xc7, 0x53, 0x01, 0x2d, 0x54, 0x01, 0x93, 0x54, 0x01, 0xf9, 0x54, 0x01, 0x5f, 0x55, 0x01, 0xc5, 0x55, 0x01, 0x2b, 0x56, 0x01, 0x91, 0x56, 0x01, 0xf7, 0x56, 0x01, 0x5d, 0x57, 0x01, 0xc3, 0x57, 0x01, 0x29, 0x58, 0x01, 0x8f, 0x58, 0x01, 0xf5, 0x58, 0x01, 0x5b, 0x59, 0x01, 0xc1, 0x59, 0x01, 0x27, 0x5a, 0x01, 0x8d, 0x5a, 0x01, 0xf3, 0x5a, 0x01, 0x59, 0x5b, 0x01, 0xbf, 0x5b, 0x01, 0x25, 0x5c, 0x01, 0x8b, 0x5c, 0x01, 0xf1, 0x5c, 0x01, 0x57, 0x5d, 0x01, 0xbd, 0x5d, 0x01, 0x23, 0x5e, 0x01, 0x89, 0x5e, 0x01, 0xef, 0x5e, 0x01, 0x55, 0x5f, 0x01, 0xbb, 0x5f, 0x01, 0x21, 0x60, 0x01, 0x87, 0x60, 0x01, 0xed, 0x60, 0x01, 0x53, 0x61, 0x01, 0xb9, 0x61, 0x01, 0x1f, 0x62, 0x01, 0x85, 0x62, 0x01, 0xeb, 0x62, 0x01, 0x51, 0x63, 0x01, 0xb7, 0x63, 0x01, 0x1d, 0x64, 0x01, 0x83, 0x64, 0x01, 0xe9, 0x64, 0x01, 0x4f, 0x65, 0x01, 0xb5, 0x65, 0x01, 0x1b, 0x66, 0x01, 0x81, 0x66, 0x01, 0xe7, 0x66, 0x01, 0x4d, 0x67, 0x01, 0xb3, 0x67, 0x01, 0x19, 0x68, 0x01, 0x7f, 0x68, 0x01, 0xe5, 0x68, 0x01, 0x4b, 0x69, 0x01, 0xb1, 0x69, 0x01, 0x17, 0x6a, 0x01, 0x7d, 0x6a, 0x01, 0xe3, 0x6a, 0x01, 0x49, 0x6b, 0x01, 0xaf, 0x6b, 0x01, 0x15, 0x6c, 0x01, 0x7b, 0x6c, 0x01, 0xe1, 0x6c, 0x01, 0x47, 0x6d, 0x01, 0xad, 0x6d, 0x01, 0x13, 0x6e, 0x01, 0x79, 0x6e, 0x01, 0xdf, 0x6e, 0x01, 0x45, 0x6f, 0x01, 0xab, 0x6f, 0x01, 0x11, 0x70, 0x01, 0x77, 0x70, 0x01, 0xdd, 0x70, 0x01, 0x43, 0x71, 0x01, 0xa9, 0x71, 0x01, 0x0f, 0x72, 0x01, 0x75, 0x72, 0x01, 0xdb, 0x72, 0x01, 0x41, 0x73, 0x01, 0xa7, 0x73, 0x01, 0x0d, 0x74, 0x01, 0x73, 0x74, 0x01, 0xd9, 0x74, 0x01, 0x3f, 0x75, 0x01, 0xa5, 0x75, 0x01, 0x0b, 0x76, 0x01, 0x71, 0x76, 0x01, 0xd7, 0x76, 0x01, 0x3d, 0x77, 0x01, 0xa3, 0x77, 0x01, 0x09, 0x78, 0x01, 0x6f, 0x78, 0x01, 0xd5, 0x78, 0x01, 0x3b, 0x79, 0x01, 0xa1, 0x79, 0x01, 0x07, 0x7a, 0x01, 0x6d, 0x7a, 0x01, 0xd3, 0x7a, 0x01, 0x39, 0x7b, 0x01, 0x9f, 0x7b, 0x01, 0x05, 0x7c, 0x01, 0x6b, 0x7c, 0x01, 0xd1, 0x7c, 0x01, 0x37, 0x7d, 0x01, 0x9d, 0x7d, 0x01, 0x03, 0x7e, 0x01, 0x69, 0x7e, 0x01, 0xcf, 0x7e, 0x01, 0x35, 0x7f, 0x01, 0x9b, 0x7f, 0x01, 0x01, 0x80, 0x01, 0x67, 0x80, 0x01, 0xcd, 0x80, 0x01, 0x33, 0x81, 0x01, 0x99, 0x81, 0x01, 0xff, 0x81, 0x01, 0x65, 0x82, 0x01, 0xcb, 0x82, 0x01, 0x31, 0x83, 0x01, 0x97, 0x83, 0x01, 0xfd, 0x83, 0x01, 0x63, 0x84, 0x01, 0xc9, 0x84, 0x01, 0x2f, 0x85, 0x01, 0x95, 0x85, 0x01, 0xfb, 0x85, 0x01, 0x61, 0x86, 0x01, 0xc7, 0x86, 0x01, 0x2d, 0x87, 0x01, 0x93, 0x87, 0x01, 0xf9, 0x87, 0x01, 0x5f, 0x88, 0x01, 0xc5, 0x88, 0x01, 0x2b, 0x89, 0x01, 0x91, 0x89, 0x01, 0xf7, 0x89, 0x01, 0x5d, 0x8a, 0x01, 0xc3, 0x8a, 0x01, 0x29, 0x8b, 0x01, 0x8f, 0x8b, 0x01, 0xf5, 0x8b, 0x01, 0x5b, 0x8c, 0x01, 0xc1, 0x8c, 0x01, 0x27, 0x8d, 0x01, 0x8d, 0x8d, 0x01, 0xf3, 0x8d, 0x01, 0x59, 0x8e, 0x01, 0xbf, 0x8e, 0x01, 0x25, 0x8f, 0x01, 0x8b, 0x8f, 0x01, 0xf1, 0x8f, 0x01, 0x57, 0x90, 0x01, 0xbd, 0x90, 0x01, 0x23, 0x91, 0x01, 0x89, 0x91, 0x01, 0xef, 0x91, 0x01, 0x55, 0x92, 0x01, 0xbb, 0x92, 0x01, 0x21, 0x93, 0x01, 0x87, 0x93, 0x01, 0xed, 0x93, 0x01, 0x53, 0x94, 0x01, 0xb9, 0x94, 0x01, 0x1f, 0x95, 0x01, 0x85, 0x95, 0x01, 0xeb, 0x95, 0x01, 0x51, 0x96, 0x01, 0xb7, 0x96, 0x01, 0x1d, 0x97, 0x01, 0x83, 0x97, 0x01, 0xe9, 0x97, 0x01, 0x4f, 0x98, 0x01, 0xb5, 0x98, 0x01, 0x1b, 0x99, 0x01, 0x81, 0x99, 0x01, 0xe7, 0x99, 0x01, 0x4d, 0x9a, 0x01, 0xb3, 0x9a, 0x01, 0x19, 0x9b, 0x01, 0x7f, 0x9b, 0x01, 0xe5, 0x9b, 0x01, 0x4b, 0x9c, 0x01, 0xb1, 0x9c, 0x01, 0x17, 0x9d, 0x01, 0x7d, 0x9d, 0x01, 0xe3, 0x9d, 0x01, 0x49, 0x9e, 0x01, 0xaf, 0x9e, 0x01, 0x15, 0x9f, 0x01, 0x7b, 0x9f, 0x01, 0xe1, 0x9f, 0x01, 0x47, 0xa0, 0x01, 0xad, 0xa0, 0x01, 0x13, 0xa1, 0x01, 0x79, 0xa1, 0x01, 0xdf, 0xa1, 0x01, 0x45, 0xa2, 0x01, 0xab, 0xa2, 0x01, 0x11, 0xa3, 0x01, 0x77, 0xa3, 0x01, 0xdd, 0xa3, 0x01, 0x43, 0xa4, 0x01, 0xa9, 0xa4, 0x01, 0x0f, 0xa5, 0x01, 0x75, 0xa5, 0x01, 0xdb, 0xa5, 0x01, 0x41, 0xa6, 0x01, 0xa7, 0xa6, 0x01, 0x0d, 0xa7, 0x01, 0x73, 0xa7, 0x01, 0xd9, 0xa7, 0x01, 0x3f, 0xa8, 0x01, 0xa5, 0xa8, 0x01, 0x0b, 0xa9, 0x01, 0x71, 0xa9, 0x01, 0xd7, 0xa9, 0x01, 0x3d, 0xaa, 0x01, 0xa3, 0xaa, 0x01, 0x09, 0xab, 0x01, 0x6f, 0xab, 0x01, 0xd5, 0xab, 0x01, 0x3b, 0xac, 0x01, 0xa1, 0xac, 0x01, 0x07, 0xad, 0x01, 0x6d, 0xad, 0x01, 0xd3, 0xad, 0x01, 0x39, 0xae, 0x01, 0x9f, 0xae, 0x01, 0x05, 0xaf, 0x01, 0x6b, 0xaf, 0x01, 0xd1, 0xaf, 0x01, 0x37, 0xb0, 0x01, 0x9d, 0xb0, 0x01, 0x03, 0xb1, 0x01, 0x69, 0xb1, 0x01, 0xcf, 0xb1, 0x01, 0x35, 0xb2, 0x01, 0x9b, 0xb2, 0x01, 0x01, 0xb3, 0x01, 0x67, 0xb3, 0x01, 0xcd, 0xb3, 0x01, 0x33, 0xb4, 0x01, 0x99, 0xb4, 0x01, 0xff, 0xb4, 0x01, 0x65, 0xb5, 0x01, 0xcb, 0xb5, 0x01, 0x31, 0xb6, 0x01, 0x97, 0xb6, 0x01, 0xfd, 0xb6, 0x01, 0x63, 0xb7, 0x01, 0xc9, 0xb7, 0x01, 0x2f, 0xb8, 0x01, 0x95, 0xb8, 0x01, 0xfb, 0xb8, 0x01, 0x61, 0xb9, 0x01, 0xc7, 0xb9, 0x01, 0x2d, 0xba, 0x01, 0x93, 0xba, 0x01, 0xf9, 0xba, 0x01, 0x5f, 0xbb, 0x01, 0xc5, 0xbb, 0x01, 0x2b, 0xbc, 0x01, 0x91, 0xbc, 0x01, 0xf7, 0xbc, 0x01, 0x5d, 0xbd, 0x01, 0xc3, 0xbd, 0x01, 0x29, 0xbe, 0x01, 0x8f, 0xbe, 0x01, 0xf5, 0xbe, 0x01, 0x5b, 0xbf, 0x01, 0xc1, 0xbf, 0x01, 0x27, 0xc0, 0x01, 0x8d, 0xc0, 0x01, 0xf3, 0xc0, 0x01, 0x59, 0xc1, 0x01, 0xbf, 0xc1, 0x01, 0x25, 0xc2, 0x01, 0x8b, 0xc2, 0x01, 0xf1, 0xc2, 0x01, 0x57, 0xc3, 0x01, 0xbd, 0xc3, 0x01, 0x23, 0xc4, 0x01, 0x89, 0xc4, 0x01, 0xef, 0xc4, 0x01, 0x55, 0xc5, 0x01, 0xbb, 0xc5, 0x01, 0x21, 0xc6, 0x01, 0x87, 0xc6, 0x01, 0xed, 0xc6, 0x01, 0x53, 0xc7, 0x01, 0xb9, 0xc7, 0x01, 0x1f, 0xc8, 0x01, 0x85, 0xc8, 0x01, 0xeb, 0xc8, 0x01, 0x51, 0xc9, 0x01, 0xb7, 0xc9, 0x01, 0x1d, 0xca, 0x01, 0x83, 0xca, 0x01, 0xe9, 0xca, 0x01, 0x4f, 0xcb, 0x01, 0xb5, 0xcb, 0x01, 0x1b, 0xcc, 0x01, 0x1f, 0x04, 0x07, 0x04, 0x04, 0x02, 0x03, 0x10, 0x00, 0x00, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x0a, 0x06, 0x00, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x10, 0x00, 0x00, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x1f, 0x00, 0x08, 0x00, 0x06, 0x00, 0x03, 0x0a, 0x06, 0x00, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x1e, 0x0b, 0x06, 0x04, 0x04, 0x03, 0x04, 0x0c, 0x04, 0x00, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x13, 0xf8, 0x01, 0x87, 0xf9, 0x01, 0x87, 0xf9, 0x01, 0x35, 0xee, 0x01, 0xa9, 0xf2, 0x01, 0xa9, 0xf2, 0x01, 0x35, 0xee, 0x01, 0xa9, 0xf2, 0x01, 0xa9, 0xf2, 0x01, 0x1e, 0x04, 0x0b, 0x04, 0x08, 0x02, 0x06, 0x04, 0x06, 0x06, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x18, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x0a, 0x06, 0x00, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x08, 0x04, 0x04, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0xb7, 0x11, 0x02, 0x21, 0x17, 0x02, 0x09, 0x1d, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x03, 0x05, 0x08, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0x7c, 0x00, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x73, 0x30, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xf0, 0x3c, 0x03, 0x55, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0xff, 0x00, 0x03, 0x55, 0x55, 0xff, 0x00, 0x3d, 0x55, 0x55, 0xff, 0x00, 0xcd, 0x55, 0x55, 0xcf, 0xff, 0x0d, 0x55, 0x55, 0x73, 0x30, 0x3d, 0x55, 0x55, 0x73, 0xf0, 0xf5, 0x55, 0x55, 0x73, 0xf0, 0x35, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x7f, 0x55, 0x57, 0xff, 0x55, 0xff, 0xd5, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x0f, 0x00, 0xf0, 0xd5, 0x57, 0x30, 0xc3, 0x0c, 0xd5, 0x57, 0x00, 0x3c, 0x00, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x57, 0x3f, 0xff, 0xfc, 0xd5, 0x57, 0xf0, 0xc3, 0x0f, 0xd5, 0x55, 0x73, 0xff, 0xcd, 0x55, 0x55, 0xc3, 0xff, 0xc3, 0x55, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x03, 0x00, 0xc0, 0xd5, 0x57, 0x0c, 0x00, 0x30, 0xd5, 0x57, 0x00, 0x3c, 0x00, 0xd5, 0x55, 0xc0, 0xff, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x3f, 0x0f, 0xc3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x00, 0xf0, 0x0d, 0x55, 0x55, 0xff, 0x0f, 0xf5, 0x55, 0x57, 0x33, 0xfc, 0xcd, 0x55, 0x57, 0xf3, 0xfc, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x30, 0x00, 0x0c, 0xd5, 0x57, 0x0c, 0x00, 0x30, 0xd5, 0x57, 0x00, 0xff, 0x00, 0xd5, 0x5f, 0x03, 0xff, 0xc0, 0xf5, 0x5c, 0xc3, 0xff, 0xc3, 0x35, 0x5f, 0x3f, 0xff, 0xfc, 0xf5, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0xc3, 0xff, 0xc3, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x7f, 0x55, 0x57, 0xff, 0x55, 0xff, 0xd5, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x03, 0x00, 0xc0, 0xd5, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x30, 0x3c, 0x0c, 0xd5, 0x55, 0xcc, 0x3c, 0x33, 0xd5, 0x55, 0xcc, 0x3c, 0x33, 0x55, 0x55, 0xc3, 0xc3, 0xc3, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xd7, 0xf5, 0x55, 0x55, 0x5f, 0x55, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x5c, 0x3f, 0xff, 0xc3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x55, 0xff, 0xff, 0xf5, 0x55, 0x55, 0xc0, 0x00, 0x35, 0x55, 0x57, 0x30, 0x00, 0xcd, 0x55, 0x57, 0xf0, 0x00, 0xfd, 0x55, 0x55, 0x70, 0x00, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0x55, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0x70, 0x00, 0x3d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x70, 0x0c, 0xd5, 0x55, 0x57, 0xc0, 0xfc, 0xd5, 0x55, 0x55, 0xf0, 0x3f, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0x57, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0x70, 0x00, 0x3d, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x30, 0xcd, 0x55, 0x55, 0xfc, 0x3f, 0xf5, 0x55, 0x55, 0x70, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x70, 0x3f, 0xf5, 0x55, 0x55, 0xc0, 0x0f, 0xf5, 0x55, 0x7f, 0xc0, 0x0f, 0xf5, 0x5f, 0xc0, 0xc0, 0x0f, 0x55, 0x5f, 0xc0, 0xc0, 0xcf, 0xd5, 0x55, 0xc0, 0xc0, 0xcf, 0xd5, 0x57, 0xc0, 0x3c, 0xcf, 0xf5, 0x5f, 0xfc, 0x03, 0x0f, 0xf5, 0x5f, 0xff, 0xff, 0xf7, 0xd5, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x3c, 0x03, 0xc3, 0x55, 0x5c, 0xc3, 0x0c, 0x33, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0xc3, 0x0c, 0x33, 0x55, 0x57, 0x30, 0xf0, 0xcc, 0xd5, 0x55, 0xff, 0xff, 0xf0, 0xd5, 0x55, 0x73, 0x0c, 0x03, 0x55, 0x55, 0xcc, 0xfc, 0x0d, 0x55, 0x55, 0xfc, 0xff, 0x0d, 0x55, 0x55, 0x5c, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x55, 0xf5, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x00, 0xc3, 0x00, 0xd5, 0x57, 0x3f, 0xc3, 0xfc, 0xd5, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x5c, 0xcc, 0x35, 0x55, 0x55, 0x73, 0xff, 0xcd, 0x55, 0x55, 0x70, 0xfc, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xc0, 0x30, 0x03, 0x55, 0x55, 0xc0, 0xc0, 0x03, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xfc, 0x00, 0x03, 0x55, 0x55, 0xff, 0x03, 0xc3, 0x55, 0x55, 0x7f, 0x03, 0x3d, 0x55, 0x55, 0x5f, 0xff, 0x35, 0x55, 0x55, 0x5c, 0xcc, 0x0d, 0x55, 0x55, 0x57, 0x3c, 0x03, 0x55, 0x55, 0x57, 0x3c, 0x3f, 0x55, 0x55, 0x57, 0xff, 0xf5, 0x55, 0x55, 0x55, 0x7d, 0xfd, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0x7f, 0x55, 0x55, 0x55, 0xff, 0xff, 0xd5, 0x55, 0x55, 0xff, 0xff, 0xd5, 0x55, 0x55, 0xff, 0x00, 0x35, 0x55, 0x57, 0xf0, 0x00, 0x3d, 0x55, 0x57, 0xc0, 0x03, 0x03, 0x55, 0x57, 0x00, 0x3c, 0x03, 0x55, 0x57, 0x00, 0x00, 0x0f, 0x55, 0x57, 0x00, 0x00, 0x35, 0x55, 0x57, 0xc0, 0x03, 0xd5, 0x55, 0x55, 0x7f, 0xff, 0x55, 0x55, 0x55, 0xc0, 0xcf, 0x55, 0x55, 0x57, 0x30, 0xfd, 0x55, 0x55, 0x57, 0xf0, 0xfd, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x7d, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xf5, 0x55, 0x55, 0x5f, 0xfd, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0x00, 0x0d, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x0f, 0xc3, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0x70, 0x00, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x5c, 0x3c, 0xd5, 0x55, 0x55, 0x5f, 0x0f, 0xd5, 0x55, 0x55, 0x5c, 0xff, 0xd5, 0x55, 0x55, 0x70, 0x0f, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3c, 0x0f, 0x55, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0xc0, 0x00, 0xff, 0x55, 0x55, 0xc0, 0xf0, 0xff, 0x55, 0x55, 0x70, 0xcc, 0xfd, 0x55, 0x55, 0x5f, 0xcf, 0xd5, 0x55, 0x55, 0x5c, 0xcc, 0xd5, 0x55, 0x55, 0x5c, 0x3f, 0xd5, 0x55, 0x55, 0x5c, 0x0f, 0xd5, 0x55, 0x55, 0x70, 0x0f, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x55, 0xfd, 0x55, 0x55, 0x7f, 0xdf, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0xc3, 0x55, 0x55, 0xcc, 0x00, 0x03, 0x55, 0x55, 0x73, 0x00, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x73, 0x30, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0x7f, 0x55, 0x55, 0xff, 0xd5, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0xd5, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0x70, 0x00, 0x03, 0x55, 0x55, 0xc3, 0x00, 0x30, 0xd5, 0x55, 0xcc, 0xc0, 0xcc, 0xd5, 0x55, 0xc3, 0x00, 0x30, 0xd5, 0x57, 0xc0, 0x3f, 0x00, 0xd5, 0x57, 0x30, 0xff, 0xc3, 0x55, 0x55, 0xcf, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xc3, 0xfc, 0x03, 0x55, 0x55, 0xc3, 0xfc, 0x3c, 0xd5, 0x55, 0x7f, 0xfc, 0x37, 0xd5, 0x55, 0x5f, 0x7f, 0xd5, 0x55, 0x55, 0x55, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x3c, 0x03, 0xc3, 0x55, 0x5c, 0xf3, 0x0f, 0x33, 0x55, 0x5c, 0xff, 0x0f, 0xf3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x0f, 0xf0, 0x0d, 0x55, 0x55, 0xfc, 0x3f, 0xf5, 0x55, 0x55, 0xc3, 0xcc, 0x3d, 0x55, 0x55, 0x70, 0xfc, 0xf3, 0x55, 0x55, 0x70, 0xfc, 0xdf, 0x55, 0x55, 0x7f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xcd, 0x55, 0x5f, 0xff, 0xff, 0xfd, 0x55, 0x7f, 0xff, 0xff, 0xd5, 0x55, 0x70, 0x00, 0x03, 0xd5, 0x55, 0xff, 0xff, 0xfc, 0xd5, 0x55, 0xc0, 0x00, 0x0f, 0xd5, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0x7c, 0x00, 0x0c, 0xd5, 0x55, 0x5f, 0xff, 0xf0, 0x35, 0x55, 0x7f, 0x3f, 0xfc, 0x0d, 0x55, 0x7f, 0x3f, 0xfc, 0x0d, 0x55, 0x70, 0x00, 0x3c, 0x0d, 0x55, 0x7f, 0xff, 0xf0, 0x0d, 0x55, 0x5f, 0xff, 0xdf, 0xf5, 0x55, 0x7f, 0xdf, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0x55, 0x55, 0x55, 0x57, 0x35, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0xff, 0xff, 0x55, 0x55, 0x5f, 0xff, 0xff, 0x55, 0x55, 0x70, 0x00, 0x0f, 0x55, 0x55, 0x7f, 0xff, 0xf3, 0xfd, 0x55, 0xc0, 0x00, 0x0c, 0xc3, 0x55, 0xc0, 0x00, 0x03, 0xc3, 0x55, 0xc0, 0x00, 0x03, 0x03, 0x55, 0xf0, 0x03, 0x03, 0xc3, 0x55, 0xc3, 0xc0, 0x0f, 0xc3, 0x55, 0xc3, 0xc0, 0x3f, 0x0d, 0x55, 0x7f, 0xff, 0xfc, 0x35, 0x5d, 0xff, 0x3f, 0xf3, 0xd5, 0x5f, 0x00, 0x00, 0xfd, 0x55, 0x5f, 0xff, 0xff, 0x3d, 0x55, 0x55, 0xff, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xff, 0x55, 0x55, 0x7f, 0xff, 0xff, 0xd5, 0x55, 0xf0, 0x00, 0x03, 0xf5, 0x55, 0xcf, 0xff, 0xfc, 0xf5, 0x55, 0xf0, 0x00, 0x03, 0xff, 0x57, 0x0f, 0xc0, 0xfc, 0xf3, 0x57, 0x33, 0xc3, 0x3c, 0xdf, 0x57, 0x33, 0xc3, 0x3c, 0xd5, 0x57, 0x0f, 0xc0, 0xfc, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x35, 0x55, 0xff, 0xff, 0xfc, 0x0d, 0x57, 0xff, 0xcf, 0xf3, 0x0d, 0x5c, 0xff, 0xcf, 0xff, 0x0d, 0x57, 0x70, 0x00, 0x0c, 0x0d, 0x55, 0x7f, 0xff, 0xf7, 0xf5, 0x55, 0x57, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xf7, 0xfd, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xff, 0xf5, 0x55, 0x70, 0x00, 0xff, 0xff, 0x55, 0x7f, 0xfc, 0x03, 0xf3, 0x55, 0xf0, 0xff, 0xf0, 0xdf, 0x55, 0xf0, 0xf3, 0x0f, 0xd5, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xff, 0xf0, 0x33, 0x55, 0x57, 0x3f, 0xc0, 0xff, 0xd5, 0x57, 0xcf, 0xff, 0xfc, 0x35, 0x55, 0xff, 0x3f, 0xfc, 0x0d, 0x55, 0x7f, 0x3f, 0xf0, 0x0d, 0x55, 0x7f, 0x3f, 0xf0, 0x0d, 0x55, 0x70, 0x00, 0xf0, 0x0d, 0x55, 0x5f, 0xff, 0xdf, 0xf5, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x55, 0xf7, 0xd5, 0x55, 0x30, 0x1f, 0x01, 0x55, 0x40, 0x00, 0x00, 0x00, 0x15, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x11, 0x41, 0x50, 0x00, 0x00, 0x15, 0x55, 0x55, 0x54, 0x04, 0x10, 0x01, 0x55, 0x41, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa1, 0x14, 0x15, 0x54, 0x01, 0x11, 0x45, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa5, 0x54, 0x15, 0x54, 0x01, 0x55, 0x45, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa1, 0x14, 0x44, 0x11, 0x55, 0x55, 0x55, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x15, 0x40, 0x01, 0x55, 0x11, 0x56, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x95, 0x40, 0x01, 0x55, 0x55, 0x56, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x95, 0x55, 0x55, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x55, 0x50, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x01, 0x50, 0x55, 0x50, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x15, 0x55, 0x55, 0x54, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x02, 0x55, 0x55, 0x55, 0x00, 0x04, 0x00, 0x80, 0x28, 0x00, 0x00, 0xa0, 0x02, 0x01, 0x15, 0x55, 0x10, 0x04, 0x55, 0x80, 0x28, 0x00, 0x00, 0xa0, 0x02, 0x01, 0x15, 0x55, 0x01, 0x55, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x02, 0x55, 0x55, 0x55, 0x01, 0x01, 0x00, 0x80, 0xaa, 0xaa, 0xaa, 0xa8, 0x02, 0x00, 0x04, 0x01, 0x01, 0x55, 0x00, 0x82, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x04, 0x01, 0x00, 0x41, 0x00, 0x82, 0xaa, 0xaa, 0xaa, 0xaa, 0x02, 0x00, 0x04, 0x01, 0x55, 0x5a, 0xa5, 0x80, 0x95, 0x95, 0x80, 0x00, 0x02, 0x55, 0x54, 0x01, 0x00, 0x25, 0x58, 0x80, 0x95, 0x95, 0x85, 0x54, 0x0a, 0xaa, 0xa8, 0x01, 0x00, 0x26, 0x98, 0x80, 0x95, 0x95, 0x85, 0x54, 0x08, 0x00, 0x09, 0x55, 0x00, 0x25, 0x58, 0x80, 0x95, 0x95, 0xaa, 0xaa, 0x08, 0x88, 0x88, 0x00, 0x00, 0x20, 0x08, 0x95, 0x95, 0x95, 0x80, 0x02, 0x58, 0x88, 0x88, 0x00, 0xaa, 0xa0, 0x0a, 0x95, 0x95, 0x95, 0x80, 0x02, 0x58, 0x00, 0x0a, 0xaa, 0x04, 0x20, 0x08, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa9, 0x55, 0x58, 0x00, 0x00, 0x0a, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xaa, 0xa9, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0x42, 0x82, 0x20, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa6, 0x86, 0x26, 0x62, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x45, 0x86, 0x24, 0xa4, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xa4, 0xa1, 0x61, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x61, 0x40, 0xa2, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0xaa, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa9, 0x55, 0x69, 0x55, 0x6a, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x9a, 0xa9, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x59, 0x59, 0x6a, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x98, 0x49, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x95, 0x55, 0xaa, 0x95, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa5, 0x56, 0xaa, 0x40, 0x68, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa8, 0x0a, 0xa5, 0x55, 0x58, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa9, 0x5a, 0xa5, 0x55, 0x58, 0x00, 0x95, 0x5a, 0x69, 0xa5, 0x56, 0x02, 0xa5, 0x96, 0xa9, 0x69, 0x68, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x96, 0x5a, 0x69, 0xa5, 0x96, 0x54, 0x54, 0x54, 0x54, 0x54, 0x55, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x54, 0x54, 0x54, 0x54, 0x54, 0x55, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x30, 0x1f, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x15, 0x00, 0x00, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x55, 0x00, 0x01, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x40, 0x51, 0x55, 0x55, 0x15, 0x54, 0x00, 0x00, 0x15, 0x54, 0x55, 0x55, 0x45, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x40, 0x00, 0x44, 0x11, 0x10, 0x11, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x44, 0x04, 0x44, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x40, 0x00, 0x44, 0x15, 0x05, 0x41, 0x50, 0x05, 0x55, 0x55, 0x50, 0x05, 0x41, 0x50, 0x54, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x50, 0x40, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x50, 0x40, 0x01, 0x00, 0x01, 0x00, 0x17, 0xfc, 0x3f, 0xfc, 0x00, 0x43, 0xff, 0xc0, 0x01, 0x00, 0x01, 0x00, 0x1f, 0xf4, 0xff, 0xd4, 0x00, 0x4f, 0xfc, 0x40, 0x01, 0x55, 0x55, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x40, 0x01, 0x11, 0x11, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x40, 0x01, 0x00, 0x01, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xc0, 0x01, 0x05, 0x41, 0x00, 0xf0, 0xfc, 0x03, 0xff, 0xff, 0x00, 0x00, 0xc0, 0x01, 0x05, 0x41, 0x00, 0xf0, 0xf3, 0x0c, 0x71, 0xc7, 0x33, 0x30, 0xc0, 0xaa, 0xaa, 0xaa, 0xaa, 0xf0, 0xf3, 0x0d, 0x75, 0xd7, 0x33, 0x30, 0xea, 0x55, 0x55, 0x55, 0x55, 0xf0, 0xfc, 0x0d, 0x34, 0xd3, 0x33, 0x30, 0xd5, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x0d, 0x34, 0xc3, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x03, 0xff, 0xff, 0xaa, 0xaa, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 0xc0, 0x00, 0xfc, 0x0f, 0xc0, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x3a, 0xbf, 0xfa, 0xab, 0xff, 0xbf, 0xfb, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0xff, 0xff, 0xcf, 0xfc, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf0, 0x03, 0xff, 0x3f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xc0, 0x00, 0xfc, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x55, 0x51, 0x55, 0x55, 0x15, 0x54, 0x00, 0x00, 0x15, 0x10, 0x00, 0x00, 0x40, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x40, 0x11, 0x10, 0x11, 0x10, 0x04, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x40, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x15, 0x55, 0x55, 0x40, 0x15, 0x05, 0x41, 0x50, 0x05, 0x55, 0x55, 0x50, 0x00, 0x00, 0x00, 0x00, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf5, 0xff, 0xf0, 0x00, 0x0f, 0xff, 0x00, 0x50, 0x50, 0x50, 0x50, 0x3f, 0xc3, 0xff, 0x00, 0x14, 0x3f, 0xf4, 0x14, 0x55, 0x50, 0x55, 0x50, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x54, 0x55, 0x50, 0x55, 0x50, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x54, 0x55, 0x55, 0x55, 0x53, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x54, 0x40, 0x10, 0x40, 0x13, 0xc3, 0xf0, 0x0f, 0xff, 0xfc, 0x00, 0x03, 0x04, 0x50, 0x50, 0x50, 0x53, 0xc3, 0xcc, 0x31, 0xc7, 0x1c, 0xcc, 0xc3, 0x14, 0x40, 0x10, 0x40, 0x13, 0xc3, 0xcc, 0x35, 0xd7, 0x5c, 0xcc, 0xc3, 0x04, 0xaa, 0xaa, 0xaa, 0xab, 0xc3, 0xf0, 0x34, 0xd3, 0x4c, 0xcc, 0xc3, 0xaa, 0x55, 0x55, 0x55, 0x57, 0x00, 0x00, 0x34, 0xd3, 0x0c, 0x00, 0x03, 0x55, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x0f, 0xff, 0xfe, 0xaa, 0xab, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x3f, 0x00, 0x03, 0xf0, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xea, 0xff, 0xea, 0xaf, 0xfe, 0xff, 0xec, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf3, 0xff, 0xff, 0x3f, 0xf3, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x0f, 0xfc, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x03, 0xf0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xfd, 0x7d, 0x7f, 0x5d, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x5d, 0xd5, 0xd7, 0x75, 0xdd, 0xd5, 0x55, 0x55, 0x55, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x30, 0xcc, 0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0xc0, 0xff, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xc0, 0xc3, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0x3f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xfc, 0x3f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x03, 0xc0, 0x30, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0xf3, 0xff, 0xff, 0xcf, 0x00, 0x00, 0x0f, 0xf0, 0x70, 0x0f, 0x55, 0x55, 0xc3, 0x0c, 0x30, 0xc3, 0x55, 0x55, 0xf0, 0x0d, 0xc3, 0x30, 0xd5, 0xff, 0x7c, 0xcf, 0xf3, 0x3d, 0xff, 0x57, 0x0c, 0xc3, 0xc0, 0x3f, 0x5f, 0x03, 0x57, 0xcf, 0xf3, 0xd5, 0xc0, 0xf5, 0xfc, 0x03, 0xc0, 0x30, 0xdc, 0x0d, 0x5f, 0xff, 0xff, 0xf5, 0x70, 0x37, 0x0c, 0x03, 0x7f, 0xff, 0x5f, 0xf5, 0x5f, 0x55, 0x55, 0xf5, 0x5f, 0xf5, 0xff, 0xfd, 0x30, 0x1f, 0xa4, 0x00, 0xa4, 0x01, 0x90, 0x00, 0x64, 0x06, 0x40, 0x1a, 0x00, 0x16, 0xa9, 0x40, 0x09, 0x00, 0x40, 0x00, 0x10, 0x01, 0x00, 0x60, 0x01, 0x6a, 0x2a, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xaa, 0x00, 0xa5, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x01, 0x6a, 0x80, 0x00, 0x01, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x30, 0xc0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x00, 0x05, 0x94, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x15, 0x56, 0xa5, 0x55, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x15, 0x40, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x29, 0x50, 0x15, 0x68, 0x00, 0x40, 0x07, 0xf0, 0x0f, 0xc0, 0x10, 0x00, 0x0a, 0xa5, 0x6a, 0x80, 0x01, 0x00, 0x1f, 0xfc, 0x3f, 0xf0, 0x04, 0x00, 0x00, 0xaa, 0xa8, 0x00, 0x15, 0x00, 0x1f, 0xff, 0xff, 0xf0, 0x05, 0x40, 0x00, 0x0a, 0xa0, 0x00, 0x04, 0x00, 0x5c, 0x00, 0x00, 0x30, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xf0, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xc0, 0x33, 0x00, 0x00, 0xcc, 0x03, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x30, 0x03, 0xc0, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x0c, 0x30, 0x03, 0xc0, 0x0c, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x3c, 0x03, 0xc0, 0x3c, 0xff, 0xc0, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0xc3, 0xff, 0xff, 0xc3, 0x00, 0x00, 0x0f, 0xf0, 0x30, 0x0c, 0x00, 0x00, 0xcc, 0x30, 0x0c, 0x33, 0x00, 0x00, 0x30, 0x0c, 0xc3, 0x0f, 0x00, 0x00, 0x3f, 0x3f, 0xfc, 0xfc, 0x00, 0x00, 0xf0, 0xc3, 0xc0, 0x30, 0xc0, 0x00, 0x03, 0x3f, 0xfc, 0xc0, 0x00, 0x03, 0x0c, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0xfc, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x3f, 0xfc, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x30, 0x30, 0xc0, 0x00, 0x00, 0x3c, 0x3c, 0x00, 0x00, 0x03, 0x0c, 0x0c, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x0c, 0x30, 0x00, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xfd, 0x7d, 0x7f, 0x5d, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x5d, 0xd5, 0xd7, 0x75, 0xdd, 0xd5, 0x55, 0x55, 0x55, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x30, 0xcc, 0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0xc0, 0xff, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xc0, 0xc3, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x70, 0x0f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xf0, 0x0d, 0xc3, 0x30, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x0c, 0xc3, 0xc0, 0x3f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfc, 0x03, 0xc0, 0x30, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x0c, 0x03, 0x7f, 0xff, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xfd, 0x30, 0x1f, 0xa4, 0x00, 0xa4, 0x01, 0x90, 0x00, 0x64, 0x06, 0x40, 0x1a, 0x00, 0x16, 0xa9, 0x40, 0x09, 0x00, 0x40, 0x00, 0x10, 0x01, 0x00, 0x60, 0x01, 0x6a, 0x2a, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xaa, 0x00, 0xa5, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x01, 0x6a, 0x80, 0x00, 0x01, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x30, 0xc0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x00, 0x05, 0x94, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x15, 0x56, 0xa5, 0x55, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x15, 0x40, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x29, 0x50, 0x15, 0x68, 0x00, 0x40, 0x04, 0x00, 0x04, 0x00, 0x10, 0x00, 0x0a, 0xa5, 0x6a, 0x80, 0x01, 0x00, 0x14, 0x00, 0x05, 0x00, 0x04, 0x00, 0x00, 0xaa, 0xa8, 0x00, 0x15, 0x00, 0x15, 0x00, 0x15, 0x00, 0x05, 0x40, 0x00, 0x0a, 0xa0, 0x00, 0x04, 0x00, 0x54, 0x00, 0x05, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x30, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0c, 0xc3, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xc3, 0xc0, 0x30, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x30, 0x30, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x0c, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xfc, 0x00, 0xc3, 0x0f, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xc3, 0x00, 0xc3, 0x30, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xcc, 0xc3, 0x00, 0xff, 0x30, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xfc, 0x00, 0xc3, 0x30, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xc0, 0x00, 0xc3, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x3f, 0x0f, 0xcf, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0xcc, 0x0c, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0xcf, 0xcf, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0x0f, 0xcf, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x30, 0xcc, 0x33, 0x0c, 0xfc, 0xfc, 0x00, 0x00, 0xc0, 0x00, 0x00, 0xc3, 0x30, 0xcf, 0x33, 0xcc, 0xc0, 0xc3, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc3, 0x30, 0xcc, 0xf3, 0x3c, 0xfc, 0xc3, 0x00, 0x00, 0xfc, 0x00, 0x00, 0xfc, 0x30, 0xcc, 0x33, 0x0c, 0xc0, 0xfc, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc3, 0x0f, 0x0c, 0x33, 0x0c, 0xfc, 0xc3, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x1f, 0x05, 0x55, 0x55, 0x55, 0x55, 0x55, 0x54, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x05, 0x54, 0x55, 0x45, 0x51, 0x10, 0x00, 0x04, 0x04, 0x55, 0x44, 0x51, 0x11, 0x55, 0x44, 0x04, 0x44, 0x44, 0x51, 0x11, 0x00, 0x44, 0x04, 0x44, 0x44, 0x51, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x00, 0x00, 0x00, 0x05, 0x41, 0x10, 0x00, 0x00, 0x00, 0x00, 0x04, 0x41, 0x10, 0x00, 0x00, 0x10, 0x55, 0x05, 0x41, 0x10, 0x54, 0x00, 0x55, 0x45, 0x10, 0x11, 0x11, 0x01, 0x40, 0x55, 0x54, 0x10, 0x11, 0x11, 0x00, 0x10, 0x55, 0x54, 0x15, 0x51, 0x11, 0x41, 0x11, 0x51, 0x10, 0x04, 0x41, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x50, 0x50, 0x00, 0x00, 0x10, 0x01, 0x10, 0x55, 0x50, 0x55, 0x00, 0x55, 0x01, 0x10, 0x44, 0x51, 0x00, 0x51, 0x00, 0x41, 0x10, 0x40, 0x11, 0x04, 0x41, 0x11, 0x41, 0x10, 0x15, 0x41, 0x00, 0x41, 0x00, 0x41, 0x10, 0x10, 0x41, 0x00, 0x40, 0x41, 0x01, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x55, 0x55, 0x55, 0x55, 0x55, 0x41, 0x10, 0x40, 0x00, 0x00, 0x00, 0x00, 0x41, 0x10, 0x55, 0x55, 0x55, 0x55, 0x55, 0x41, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x15, 0x50, 0x00, 0x00, 0x00, 0x01, 0x55, 0x12, 0x0c, 0x57, 0xf5, 0x7d, 0x55, 0x50, 0x5f, 0xfd, 0xff, 0x55, 0x50, 0x5f, 0xff, 0xff, 0x55, 0x50, 0x5f, 0xff, 0xff, 0xd5, 0x50, 0x7c, 0x00, 0x00, 0xd5, 0x50, 0x70, 0x0f, 0xc3, 0xd5, 0x50, 0x70, 0x33, 0xc3, 0xd5, 0x50, 0x70, 0x33, 0xc3, 0xd5, 0x50, 0x70, 0x0f, 0xc3, 0xd5, 0x50, 0x5c, 0x00, 0x0f, 0x55, 0x50, 0x57, 0xff, 0xfd, 0x55, 0x50, 0x5c, 0x3c, 0x33, 0x55, 0x50, 0x12, 0x0c, 0x55, 0xfd, 0x5f, 0x55, 0x50, 0x57, 0xff, 0x7f, 0xd5, 0x50, 0x57, 0xff, 0xff, 0xd5, 0x50, 0x57, 0xff, 0xff, 0xf5, 0x50, 0x5f, 0x00, 0x00, 0x35, 0x50, 0x5c, 0x03, 0xc0, 0x35, 0x50, 0x5c, 0x0c, 0x30, 0xf5, 0x50, 0x5c, 0x00, 0x00, 0x35, 0x50, 0x5c, 0x0c, 0x0f, 0xf5, 0x50, 0x57, 0x33, 0x0f, 0xd5, 0x50, 0x55, 0xf3, 0xff, 0x35, 0x50, 0x55, 0xc3, 0xc3, 0xf5, 0x50, 0x12, 0x0c, 0x5f, 0xd5, 0x7f, 0xff, 0xf0, 0x7f, 0xf5, 0xff, 0x00, 0x30, 0x7f, 0xff, 0xff, 0x00, 0x30, 0x7f, 0xff, 0xff, 0x00, 0x30, 0x70, 0x00, 0x03, 0x00, 0x30, 0xc3, 0xf0, 0x3f, 0x00, 0x30, 0xcc, 0xf0, 0xcf, 0x00, 0x30, 0xcc, 0xf0, 0xcf, 0x00, 0x30, 0xc3, 0xf0, 0x3f, 0xff, 0xf0, 0x70, 0x0f, 0x00, 0xcd, 0x50, 0x5f, 0xff, 0xff, 0x35, 0x50, 0x70, 0x30, 0x3c, 0xd5, 0x50, 0x12, 0x0c, 0x55, 0xfd, 0x57, 0xd5, 0x50, 0x57, 0xff, 0xdf, 0xf5, 0x50, 0x57, 0xff, 0xff, 0xfd, 0x50, 0x55, 0xff, 0xff, 0xfd, 0x50, 0x57, 0xc0, 0x00, 0x0d, 0x50, 0x57, 0x00, 0x00, 0x0d, 0x50, 0x57, 0x00, 0x00, 0x0d, 0x50, 0x57, 0x0f, 0xf0, 0x0d, 0x50, 0x57, 0x00, 0x00, 0xcd, 0x50, 0x55, 0xc0, 0x03, 0x35, 0x50, 0x55, 0x7f, 0xff, 0xd5, 0x50, 0x55, 0xc3, 0xc3, 0xd5, 0x50, 0x12, 0x0c, 0x57, 0xf5, 0x5f, 0xd5, 0x50, 0x5f, 0xfd, 0x7f, 0xf5, 0x50, 0x5f, 0xff, 0xff, 0xf5, 0x50, 0x5f, 0xff, 0xff, 0xf5, 0x50, 0x5c, 0x00, 0x00, 0x35, 0x50, 0x70, 0x00, 0x00, 0x0d, 0x50, 0x70, 0x30, 0x0c, 0x0d, 0x50, 0x70, 0xc0, 0x03, 0x0d, 0x50, 0x70, 0x03, 0xc0, 0x0d, 0x50, 0x5c, 0x0f, 0xf0, 0x35, 0x50, 0x57, 0xff, 0xff, 0xd5, 0x50, 0x55, 0xcc, 0x33, 0x55, 0x50, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfa, 0xaa, 0xab, 0xc0, 0xff, 0xe5, 0x55, 0x5a, 0xc0, 0xff, 0xe5, 0x55, 0x5a, 0xc0, 0xff, 0x95, 0x55, 0x66, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0xaa, 0xaa, 0xab, 0xc0, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfe, 0xaa, 0xaa, 0xc0, 0xff, 0xfe, 0x55, 0x56, 0xc0, 0xff, 0xfe, 0x55, 0x56, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xea, 0xaa, 0xaa, 0xc0, 0xff, 0xea, 0xaa, 0xaa, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0xaa, 0xaa, 0xab, 0xc0, 0x08, 0x08, 0x7f, 0xf5, 0xff, 0xfd, 0xc3, 0x0d, 0xff, 0xfd, 0xff, 0xfd, 0xfc, 0xfd, 0x7f, 0xf5, 0x77, 0x75, 0x10, 0x03, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xc0, 0x03, 0x03, 0xff, 0xff, 0xff, 0xff, 0x10, 0x03, 0x55, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x03, 0x55, 0x55, 0xff, 0xff, 0x55, 0x08, 0x08, 0x55, 0x75, 0x55, 0x75, 0x55, 0x75, 0x5f, 0x75, 0x70, 0xf5, 0x70, 0xd5, 0x5f, 0x55, 0x55, 0x55, 0x08, 0x08, 0x55, 0x75, 0x55, 0x75, 0x55, 0x75, 0x5f, 0x75, 0x7f, 0xf5, 0x7f, 0xd5, 0x5f, 0x55, 0x55, 0x55, 0x08, 0x08, 0x55, 0xd5, 0x55, 0xf5, 0x55, 0xfd, 0x7d, 0xdd, 0xff, 0xd5, 0xff, 0x55, 0x7d, 0x55, 0x55, 0x55, 0x08, 0x08, 0x5f, 0xfd, 0x5d, 0x5d, 0x5d, 0x5d, 0x5d, 0x5d, 0xfd, 0xfd, 0xfd, 0xfd, 0xf5, 0xf5, 0x55, 0x55, 0x01, 0x01, 0x00, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x7f, 0xfd, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x5f, 0xfd, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x7f, 0xfd, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x5f, 0xfd, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x7f, 0xfd, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0x03, 0x5f, 0xfd, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x08, 0x08, 0x50, 0x05, 0x43, 0xc1, 0x00, 0x00, 0x30, 0xcc, 0x33, 0x0c, 0x00, 0x00, 0x43, 0xc1, 0x50, 0x05, 0x08, 0x08, 0xc0, 0x03, 0x33, 0xcc, 0x00, 0x30, 0x33, 0x0c, 0x30, 0xcc, 0x0c, 0x00, 0x33, 0xcc, 0xc0, 0x03, 0x08, 0x08, 0x57, 0xd5, 0x5c, 0x35, 0x5c, 0x35, 0xdc, 0x37, 0xd7, 0xd7, 0xdf, 0xf7, 0xfd, 0x7f, 0xf7, 0xdf, 0x04, 0x1f, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x02, 0x05, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0x06, 0x20, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0x20, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf7, 0xff, 0x5f, 0x5f, 0xd7, 0xff, 0x75, 0x5d, 0x55, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x57, 0xd5, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x55, 0x75, 0x75, 0x7f, 0xdf, 0xd5, 0x75, 0x75, 0x55, 0x75, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x55, 0x5f, 0xd5, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x08, 0x7f, 0x5f, 0x57, 0xd7, 0x57, 0xd5, 0x75, 0xdd, 0x77, 0x57, 0xdf, 0x75, 0xdd, 0x77, 0x57, 0xd7, 0x75, 0xdf, 0xf7, 0x55, 0x7d, 0x5f, 0x5d, 0x77, 0xf7, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x0c, 0x7f, 0x5f, 0x5d, 0x5d, 0xfd, 0xd5, 0x75, 0xdf, 0x7d, 0xd5, 0xdf, 0x75, 0xdf, 0xfd, 0xfd, 0xd7, 0x7f, 0xdd, 0xdd, 0xd5, 0x7f, 0x75, 0xdd, 0x5d, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7d, 0x75, 0x77, 0xf7, 0xf5, 0xd7, 0x75, 0x77, 0x57, 0x5d, 0xd7, 0x5d, 0xd7, 0xf7, 0x5d, 0xd7, 0x5d, 0xd7, 0x57, 0xf5, 0x7d, 0x57, 0x57, 0xf7, 0x5d, 0x55, 0x55, 0x55, 0x55, 0x55, 0x20, 0x0c, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xff, 0x55, 0xc3, 0x7d, 0x55, 0x55, 0x55, 0x70, 0x00, 0xd5, 0x70, 0xff, 0x55, 0x55, 0x55, 0xc0, 0x00, 0x35, 0x7c, 0x3f, 0xd5, 0x55, 0x57, 0x00, 0x03, 0x0d, 0x5f, 0xff, 0xff, 0xff, 0xfc, 0x03, 0x00, 0x0d, 0x70, 0x00, 0x03, 0xc0, 0x00, 0x00, 0x3f, 0xfd, 0x7f, 0xff, 0xfc, 0x30, 0x00, 0x00, 0xc0, 0x03, 0xc0, 0x00, 0x03, 0x30, 0x00, 0x03, 0x0f, 0xfc, 0xc0, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc0, 0x03, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x01, 0x01, 0x00, 0x10, 0x10, 0x55, 0x7d, 0x55, 0xf5, 0x55, 0xc3, 0x57, 0x0d, 0x55, 0xc0, 0xdc, 0x0d, 0x55, 0x70, 0xdc, 0x3d, 0x55, 0x5c, 0x30, 0x35, 0x55, 0x70, 0x00, 0xd5, 0x55, 0xc3, 0xfc, 0xd5, 0x55, 0xcf, 0xff, 0x35, 0x57, 0x0f, 0xff, 0x35, 0x57, 0x00, 0xfc, 0x35, 0x57, 0xc0 };\r\n//uint8_t v[] = { 0x0a, 0xaa, 0x55, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x55, 0x03, 0x03, 0x03, 0x00, 0x00, 0x10, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0xc4, 0x00, 0x00, 0xdc, 0x00, 0x00, 0x0f, 0x01, 0x00, 0x91, 0x01, 0x00, 0x0d, 0x02, 0x00, 0x89, 0x02, 0x00, 0xd1, 0x02, 0x00, 0x1f, 0x06, 0x00, 0x67, 0x0f, 0x00, 0x67, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x12, 0x00, 0xa7, 0x12, 0x00, 0x0d, 0x13, 0x00, 0x73, 0x13, 0x00, 0xd9, 0x13, 0x00, 0x3f, 0x14, 0x00, 0xa5, 0x14, 0x00, 0x0b, 0x15, 0x00, 0x71, 0x15, 0x00, 0xd7, 0x15, 0x00, 0x3d, 0x16, 0x00, 0xa3, 0x16, 0x00, 0x09, 0x17, 0x00, 0x6f, 0x17, 0x00, 0xd5, 0x17, 0x00, 0x3b, 0x18, 0x00, 0xa1, 0x18, 0x00, 0x07, 0x19, 0x00, 0x6d, 0x19, 0x00, 0xd3, 0x19, 0x00, 0x39, 0x1a, 0x00, 0x9f, 0x1a, 0x00, 0x05, 0x1b, 0x00, 0x6b, 0x1b, 0x00, 0xd1, 0x1b, 0x00, 0x37, 0x1c, 0x00, 0x9d, 0x1c, 0x00, 0x13, 0x1e, 0x00, 0x89, 0x1f, 0x00, 0xff, 0x20, 0x00, 0x75, 0x22, 0x00, 0xeb, 0x23, 0x00, 0x61, 0x25, 0x00, 0xd7, 0x26, 0x00, 0x4d, 0x28, 0x00, 0xeb, 0x28, 0x00, 0x89, 0x29, 0x00, 0x64, 0x2a, 0x00, 0xa2, 0x2a, 0x00, 0xe0, 0x2a, 0x00, 0x1e, 0x2b, 0x00, 0x5c, 0x2b, 0x00, 0xce, 0x00, 0x00, 0xf1, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x44, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};// 0x70, 0x2c, 0x00, 0x82, 0x2c, 0x00, 0x90, 0x2c, 0x00, 0x9e, 0x2c, 0x00, 0xb0, 0x2c, 0x00, 0xc2, 0x2c, 0x00, 0xd4, 0x2c, 0x00, 0xe6, 0x2c, 0x00, 0xe9, 0x2c, 0x00, 0x1b, 0x2d, 0x00, 0x4d, 0x2d, 0x00, 0x7f, 0x2d, 0x00, 0xb1, 0x2d, 0x00, 0xe3, 0x2d, 0x00, 0x15, 0x2e, 0x00, 0x27, 0x2e, 0x00, 0x39, 0x2e, 0x00, 0x4b, 0x2e, 0x00, 0x6c, 0x2e, 0x00, 0x73, 0x2e, 0x00, 0xb5, 0x2e, 0x00, 0xf7, 0x2e, 0x00, 0x21, 0x2f, 0x00, 0x5f, 0x2f, 0x00, 0xc1, 0x2f, 0x00, 0x02, 0x00, 0x06, 0x03, 0x04, 0x09, 0x0a, 0x05, 0x08, 0x07, 0x00, 0x00, 0x58, 0x00, 0x00, 0x32, 0x00, 0x00, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x10, 0x00, 0x00, 0x08, 0x00, 0x00, 0x50, 0x04, 0x00, 0x30, 0x02, 0x00, 0x20, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00, 0x50, 0x08, 0x00, 0x50, 0x11, 0x00, 0x00, 0x00, 0x28, 0x00, 0x40, 0x15, 0x00, 0x60, 0x12, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x45, 0x00, 0x00, 0x35, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x22, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00, 0x22, 0x00, 0x00, 0x13, 0x00, 0x01, 0x00, 0x02, 0x00, 0x50, 0x01, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x04, 0xff, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x02, 0xff, 0x01, 0x01, 0x00, 0x1e, 0x01, 0x00, 0x03, 0xff, 0x01, 0x01, 0x00, 0x2d, 0x01, 0x00, 0x04, 0xfe, 0x01, 0x01, 0x00, 0x3c, 0x01, 0x00, 0x05, 0xfe, 0x01, 0x01, 0x00, 0x4b, 0x02, 0x00, 0x06, 0xfe, 0x02, 0x02, 0x00, 0x5a, 0x02, 0x00, 0x07, 0xfd, 0x02, 0x02, 0x00, 0x63, 0x02, 0x00, 0x08, 0xfd, 0x02, 0x02, 0x00, 0x64, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0x00, 0x02, 0x04, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x02, 0xff, 0x01, 0x01, 0x00, 0x0f, 0x01, 0x00, 0x03, 0xff, 0x01, 0x01, 0x00, 0x19, 0x01, 0x00, 0x04, 0xfe, 0x01, 0x01, 0x00, 0x23, 0x01, 0x00, 0x05, 0xfe, 0x01, 0x02, 0x00, 0x2d, 0x02, 0x00, 0x06, 0xfe, 0x02, 0x02, 0x00, 0x37, 0x02, 0x00, 0x07, 0xfd, 0x02, 0x02, 0x00, 0x40, 0x02, 0x00, 0x08, 0xfd, 0x02, 0x02, 0x00, 0x41, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xc4, 0x2f, 0x00, 0xff, 0xff, 0xff, 0x06, 0x30, 0x00, 0x48, 0x30, 0x00, 0x8a, 0x30, 0x00, 0xcc, 0x30, 0x00, 0x0e, 0x31, 0x00, 0x50, 0x31, 0x00, 0x92, 0x31, 0x00, 0xd4, 0x31, 0x00, 0x16, 0x32, 0x00, 0xff, 0xff, 0xff, 0x58, 0x32, 0x00, 0xff, 0xff, 0xff, 0xba, 0x32, 0x00, 0x1c, 0x33, 0x00, 0x7e, 0x33, 0x00, 0xe0, 0x33, 0x00, 0x42, 0x34, 0x00, 0xa4, 0x34, 0x00, 0x06, 0x35, 0x00, 0x68, 0x35, 0x00, 0xca, 0x35, 0x00, 0xff, 0xff, 0xff, 0x2c, 0x36, 0x00, 0x3e, 0x36, 0x00, 0x80, 0x36, 0x00, 0xc2, 0x36, 0x00, 0x04, 0x37, 0x00, 0x46, 0x37, 0x00, 0x88, 0x37, 0x00, 0xca, 0x37, 0x00, 0x24, 0x38, 0x00, 0x9d, 0x38, 0x00, 0xf9, 0x38, 0x00, 0x7d, 0x39, 0x00, 0xd7, 0x39, 0x00, 0x50, 0x3a, 0x00, 0xac, 0x3a, 0x00, 0x30, 0x3b, 0x00, 0x72, 0x3b, 0x00, 0xb4, 0x3b, 0x00, 0xf6, 0x3b, 0x00, 0x38, 0x3c, 0x00, 0x7a, 0x3c, 0x00, 0xbc, 0x3c, 0x00, 0xfe, 0x3c, 0x00, 0x40, 0x3d, 0x00, 0x3a, 0x3e, 0x00, 0x34, 0x3f, 0x00, 0x2e, 0x40, 0x00, 0x28, 0x41, 0x00, 0x22, 0x42, 0x00, 0x98, 0x43, 0x00, 0xea, 0x43, 0x00, 0x3c, 0x44, 0x00, 0x8e, 0x44, 0x00, 0xe0, 0x44, 0x00, 0x32, 0x45, 0x00, 0x84, 0x45, 0x00, 0x7e, 0x46, 0x00, 0x78, 0x47, 0x00, 0xba, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0x76, 0x48, 0x00, 0xf0, 0x48, 0x00, 0x6a, 0x49, 0x00, 0xe4, 0x49, 0x00, 0x5e, 0x4a, 0x00, 0xd8, 0x4a, 0x00, 0x52, 0x4b, 0x00, 0xcc, 0x4b, 0x00, 0x46, 0x4c, 0x00, 0xc0, 0x4c, 0x00, 0x3a, 0x4d, 0x00, 0xb4, 0x4d, 0x00, 0x2e, 0x4e, 0x00, 0xa8, 0x4e, 0x00, 0x22, 0x4f, 0x00, 0x9c, 0x4f, 0x00, 0x16, 0x50, 0x00, 0x90, 0x50, 0x00, 0x0a, 0x51, 0x00, 0x84, 0x51, 0x00, 0xfe, 0x51, 0x00, 0x78, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0x6c, 0x53, 0x00, 0xe6, 0x53, 0x00, 0x60, 0x54, 0x00, 0xda, 0x54, 0x00, 0x54, 0x55, 0x00, 0xce, 0x55, 0x00, 0x48, 0x56, 0x00, 0xc2, 0x56, 0x00, 0x3c, 0x57, 0x00, 0xb6, 0x57, 0x00, 0x30, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0x24, 0x59, 0x00, 0x9e, 0x59, 0x00, 0x18, 0x5a, 0x00, 0x92, 0x5a, 0x00, 0x0c, 0x5b, 0x00, 0x86, 0x5b, 0x00, 0x00, 0x5c, 0x00, 0x7a, 0x5c, 0x00, 0xf4, 0x5c, 0x00, 0x6e, 0x5d, 0x00, 0xe8, 0x5d, 0x00, 0x62, 0x5e, 0x00, 0xdc, 0x5e, 0x00, 0x56, 0x5f, 0x00, 0xd0, 0x5f, 0x00, 0x4a, 0x60, 0x00, 0xc4, 0x60, 0x00, 0x3e, 0x61, 0x00, 0xb8, 0x61, 0x00, 0x32, 0x62, 0x00, 0xac, 0x62, 0x00, 0x26, 0x63, 0x00, 0xa0, 0x63, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x94, 0x64, 0x00, 0x0e, 0x65, 0x00, 0x88, 0x65, 0x00, 0x02, 0x66, 0x00, 0x7c, 0x66, 0x00, 0xf6, 0x66, 0x00, 0x70, 0x67, 0x00, 0xea, 0x67, 0x00, 0x64, 0x68, 0x00, 0xde, 0x68, 0x00, 0x58, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0x4c, 0x6a, 0x00, 0xc6, 0x6a, 0x00, 0x40, 0x6b, 0x00, 0xba, 0x6b, 0x00, 0x34, 0x6c, 0x00, 0xae, 0x6c, 0x00, 0x28, 0x6d, 0x00, 0xa2, 0x6d, 0x00, 0x1c, 0x6e, 0x00, 0x96, 0x6e, 0x00, 0x10, 0x6f, 0x00, 0x8a, 0x6f, 0x00, 0x04, 0x70, 0x00, 0x7e, 0x70, 0x00, 0xf8, 0x70, 0x00, 0x72, 0x71, 0x00, 0xec, 0x71, 0x00, 0x66, 0x72, 0x00, 0xe0, 0x72, 0x00, 0x5a, 0x73, 0x00, 0xd4, 0x73, 0x00, 0x4e, 0x74, 0x00, 0xc8, 0x74, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0xbc, 0x75, 0x00, 0x36, 0x76, 0x00, 0xb0, 0x76, 0x00, 0x2a, 0x77, 0x00, 0xa4, 0x77, 0x00, 0x1e, 0x78, 0x00, 0x98, 0x78, 0x00, 0x12, 0x79, 0x00, 0x8c, 0x79, 0x00, 0x06, 0x7a, 0x00, 0x80, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0x74, 0x7b, 0x00, 0xe2, 0x7b, 0x00, 0x50, 0x7c, 0x00, 0xbe, 0x7c, 0x00, 0x2c, 0x7d, 0x00, 0x9a, 0x7d, 0x00, 0x08, 0x7e, 0x00, 0x76, 0x7e, 0x00, 0xe4, 0x7e, 0x00, 0x52, 0x7f, 0x00, 0xc0, 0x7f, 0x00, 0x2e, 0x80, 0x00, 0x9c, 0x80, 0x00, 0x0a, 0x81, 0x00, 0x78, 0x81, 0x00, 0xe6, 0x81, 0x00, 0x54, 0x82, 0x00, 0xc2, 0x82, 0x00, 0x30, 0x83, 0x00, 0x9e, 0x83, 0x00, 0x0c, 0x84, 0x00, 0x7a, 0x84, 0x00, 0xe8, 0x84, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0xc4, 0x85, 0x00, 0x32, 0x86, 0x00, 0xa0, 0x86, 0x00, 0x0e, 0x87, 0x00, 0x7c, 0x87, 0x00, 0xea, 0x87, 0x00, 0x58, 0x88, 0x00, 0xc6, 0x88, 0x00, 0x34, 0x89, 0x00, 0xa2, 0x89, 0x00, 0x10, 0x8a, 0x00, 0x7e, 0x8a, 0x00, 0xec, 0x8a, 0x00, 0x2e, 0x8b, 0x00, 0xac, 0x8b, 0x00, 0x2a, 0x8c, 0x00, 0xa8, 0x8c, 0x00, 0x26, 0x8d, 0x00, 0xa4, 0x8d, 0x00, 0x22, 0x8e, 0x00, 0xa0, 0x8e, 0x00, 0x1e, 0x8f, 0x00, 0x60, 0x8f, 0x00, 0xa2, 0x8f, 0x00, 0xe4, 0x8f, 0x00, 0x13, 0x90, 0x00, 0x42, 0x90, 0x00, 0x65, 0x90, 0x00, 0x88, 0x90, 0x00, 0xab, 0x90, 0x00, 0xce, 0x90, 0x00, 0xf1, 0x90, 0x00, 0x57, 0x91, 0x00, 0xbd, 0x91, 0x00, 0x23, 0x92, 0x00, 0x89, 0x92, 0x00, 0xef, 0x92, 0x00, 0x55, 0x93, 0x00, 0xbb, 0x93, 0x00, 0x21, 0x94, 0x00, 0x87, 0x94, 0x00, 0xed, 0x94, 0x00, 0x53, 0x95, 0x00, 0xb9, 0x95, 0x00, 0x1f, 0x96, 0x00, 0x85, 0x96, 0x00, 0xeb, 0x96, 0x00, 0x51, 0x97, 0x00, 0xb7, 0x97, 0x00, 0x1d, 0x98, 0x00, 0x83, 0x98, 0x00, 0xe9, 0x98, 0x00, 0x4f, 0x99, 0x00, 0xb5, 0x99, 0x00, 0x1b, 0x9a, 0x00, 0x81, 0x9a, 0x00, 0xe7, 0x9a, 0x00, 0x4d, 0x9b, 0x00, 0xb3, 0x9b, 0x00, 0x19, 0x9c, 0x00, 0x7f, 0x9c, 0x00, 0xe5, 0x9c, 0x00, 0x4b, 0x9d, 0x00, 0xb1, 0x9d, 0x00, 0x17, 0x9e, 0x00, 0x7d, 0x9e, 0x00, 0xe3, 0x9e, 0x00, 0x49, 0x9f, 0x00, 0xaf, 0x9f, 0x00, 0x15, 0xa0, 0x00, 0x7b, 0xa0, 0x00, 0xe1, 0xa0, 0x00, 0x47, 0xa1, 0x00, 0xad, 0xa1, 0x00, 0x13, 0xa2, 0x00, 0x79, 0xa2, 0x00, 0xdf, 0xa2, 0x00, 0x45, 0xa3, 0x00, 0xab, 0xa3, 0x00, 0x11, 0xa4, 0x00, 0x77, 0xa4, 0x00, 0xdd, 0xa4, 0x00, 0x43, 0xa5, 0x00, 0xa9, 0xa5, 0x00, 0x0f, 0xa6, 0x00, 0x75, 0xa6, 0x00, 0xdb, 0xa6, 0x00, 0x41, 0xa7, 0x00, 0xa7, 0xa7, 0x00, 0x0d, 0xa8, 0x00, 0x73, 0xa8, 0x00, 0xd9, 0xa8, 0x00, 0x3f, 0xa9, 0x00, 0xa5, 0xa9, 0x00, 0x0b, 0xaa, 0x00, 0x71, 0xaa, 0x00, 0xd7, 0xaa, 0x00, 0x3d, 0xab, 0x00, 0xa3, 0xab, 0x00, 0x09, 0xac, 0x00, 0x6f, 0xac, 0x00, 0xd5, 0xac, 0x00, 0x3b, 0xad, 0x00, 0xa1, 0xad, 0x00, 0x07, 0xae, 0x00, 0x6d, 0xae, 0x00, 0xd3, 0xae, 0x00, 0x39, 0xaf, 0x00, 0x9f, 0xaf, 0x00, 0x05, 0xb0, 0x00, 0x6b, 0xb0, 0x00, 0xd1, 0xb0, 0x00, 0x37, 0xb1, 0x00, 0x9d, 0xb1, 0x00, 0x03, 0xb2, 0x00, 0x69, 0xb2, 0x00, 0xcf, 0xb2, 0x00, 0x35, 0xb3, 0x00, 0x9b, 0xb3, 0x00, 0x01, 0xb4, 0x00, 0x67, 0xb4, 0x00, 0xcd, 0xb4, 0x00, 0x33, 0xb5, 0x00, 0x99, 0xb5, 0x00, 0xff, 0xb5, 0x00, 0x65, 0xb6, 0x00, 0xcb, 0xb6, 0x00, 0x31, 0xb7, 0x00, 0x97, 0xb7, 0x00, 0xfd, 0xb7, 0x00, 0x63, 0xb8, 0x00, 0xc9, 0xb8, 0x00, 0x2f, 0xb9, 0x00, 0x95, 0xb9, 0x00, 0xfb, 0xb9, 0x00, 0x61, 0xba, 0x00, 0xc7, 0xba, 0x00, 0x2d, 0xbb, 0x00, 0x93, 0xbb, 0x00, 0xf9, 0xbb, 0x00, 0x5f, 0xbc, 0x00, 0xc5, 0xbc, 0x00, 0x2b, 0xbd, 0x00, 0x91, 0xbd, 0x00, 0xf7, 0xbd, 0x00, 0x5d, 0xbe, 0x00, 0xc3, 0xbe, 0x00, 0x29, 0xbf, 0x00, 0x8f, 0xbf, 0x00, 0xf5, 0xbf, 0x00, 0x5b, 0xc0, 0x00, 0xc1, 0xc0, 0x00, 0x27, 0xc1, 0x00, 0x8d, 0xc1, 0x00, 0xf3, 0xc1, 0x00, 0x59, 0xc2, 0x00, 0xbf, 0xc2, 0x00, 0x25, 0xc3, 0x00, 0x8b, 0xc3, 0x00, 0xf1, 0xc3, 0x00, 0x57, 0xc4, 0x00, 0xbd, 0xc4, 0x00, 0x23, 0xc5, 0x00, 0x89, 0xc5, 0x00, 0xef, 0xc5, 0x00, 0x55, 0xc6, 0x00, 0xbb, 0xc6, 0x00, 0x21, 0xc7, 0x00, 0x87, 0xc7, 0x00, 0xed, 0xc7, 0x00, 0x53, 0xc8, 0x00, 0xb9, 0xc8, 0x00, 0x1f, 0xc9, 0x00, 0x85, 0xc9, 0x00, 0xeb, 0xc9, 0x00, 0x51, 0xca, 0x00, 0xb7, 0xca, 0x00, 0x1d, 0xcb, 0x00, 0x83, 0xcb, 0x00, 0xe9, 0xcb, 0x00, 0x4f, 0xcc, 0x00, 0xb5, 0xcc, 0x00, 0x1b, 0xcd, 0x00, 0x81, 0xcd, 0x00, 0xe7, 0xcd, 0x00, 0x4d, 0xce, 0x00, 0xb3, 0xce, 0x00, 0x19, 0xcf, 0x00, 0x7f, 0xcf, 0x00, 0xe5, 0xcf, 0x00, 0x4b, 0xd0, 0x00, 0xb1, 0xd0, 0x00, 0x17, 0xd1, 0x00, 0x7d, 0xd1, 0x00, 0xe3, 0xd1, 0x00, 0x49, 0xd2, 0x00, 0xaf, 0xd2, 0x00, 0x15, 0xd3, 0x00, 0x7b, 0xd3, 0x00, 0xe1, 0xd3, 0x00, 0x47, 0xd4, 0x00, 0xad, 0xd4, 0x00, 0x13, 0xd5, 0x00, 0x79, 0xd5, 0x00, 0xdf, 0xd5, 0x00, 0x45, 0xd6, 0x00, 0xab, 0xd6, 0x00, 0x11, 0xd7, 0x00, 0x77, 0xd7, 0x00, 0xdd, 0xd7, 0x00, 0x43, 0xd8, 0x00, 0xa9, 0xd8, 0x00, 0x0f, 0xd9, 0x00, 0x75, 0xd9, 0x00, 0xdb, 0xd9, 0x00, 0x41, 0xda, 0x00, 0xa7, 0xda, 0x00, 0x0d, 0xdb, 0x00, 0x73, 0xdb, 0x00, 0xd9, 0xdb, 0x00, 0x3f, 0xdc, 0x00, 0xa5, 0xdc, 0x00, 0x0b, 0xdd, 0x00, 0x71, 0xdd, 0x00, 0xd7, 0xdd, 0x00, 0x3d, 0xde, 0x00, 0xa3, 0xde, 0x00, 0x09, 0xdf, 0x00, 0x6f, 0xdf, 0x00, 0xd5, 0xdf, 0x00, 0x3b, 0xe0, 0x00, 0xa1, 0xe0, 0x00, 0x07, 0xe1, 0x00, 0x6d, 0xe1, 0x00, 0xd3, 0xe1, 0x00, 0x39, 0xe2, 0x00, 0x9f, 0xe2, 0x00, 0x05, 0xe3, 0x00, 0x6b, 0xe3, 0x00, 0xd1, 0xe3, 0x00, 0x37, 0xe4, 0x00, 0x9d, 0xe4, 0x00, 0x03, 0xe5, 0x00, 0x69, 0xe5, 0x00, 0xcf, 0xe5, 0x00, 0x35, 0xe6, 0x00, 0x9b, 0xe6, 0x00, 0x01, 0xe7, 0x00, 0x67, 0xe7, 0x00, 0xcd, 0xe7, 0x00, 0x33, 0xe8, 0x00, 0x99, 0xe8, 0x00, 0xff, 0xe8, 0x00, 0x65, 0xe9, 0x00, 0xcb, 0xe9, 0x00, 0x31, 0xea, 0x00, 0x97, 0xea, 0x00, 0xfd, 0xea, 0x00, 0x63, 0xeb, 0x00, 0xc9, 0xeb, 0x00, 0x2f, 0xec, 0x00, 0x95, 0xec, 0x00, 0xfb, 0xec, 0x00, 0x61, 0xed, 0x00, 0xc7, 0xed, 0x00, 0x2d, 0xee, 0x00, 0x93, 0xee, 0x00, 0xf9, 0xee, 0x00, 0x5f, 0xef, 0x00, 0xc5, 0xef, 0x00, 0x2b, 0xf0, 0x00, 0x91, 0xf0, 0x00, 0xf7, 0xf0, 0x00, 0x5d, 0xf1, 0x00, 0xc3, 0xf1, 0x00, 0x29, 0xf2, 0x00, 0x8f, 0xf2, 0x00, 0xf5, 0xf2, 0x00, 0x5b, 0xf3, 0x00, 0xc1, 0xf3, 0x00, 0x27, 0xf4, 0x00, 0x8d, 0xf4, 0x00, 0xf3, 0xf4, 0x00, 0x59, 0xf5, 0x00, 0xbf, 0xf5, 0x00, 0x25, 0xf6, 0x00, 0x8b, 0xf6, 0x00, 0xf1, 0xf6, 0x00, 0x57, 0xf7, 0x00, 0xbd, 0xf7, 0x00, 0x23, 0xf8, 0x00, 0x89, 0xf8, 0x00, 0xef, 0xf8, 0x00, 0x55, 0xf9, 0x00, 0xbb, 0xf9, 0x00, 0x21, 0xfa, 0x00, 0x87, 0xfa, 0x00, 0xed, 0xfa, 0x00, 0x53, 0xfb, 0x00, 0xb9, 0xfb, 0x00, 0x1f, 0xfc, 0x00, 0x85, 0xfc, 0x00, 0xeb, 0xfc, 0x00, 0x51, 0xfd, 0x00, 0xb7, 0xfd, 0x00, 0x1d, 0xfe, 0x00, 0x83, 0xfe, 0x00, 0xe9, 0xfe, 0x00, 0x4f, 0xff, 0x00, 0xb5, 0xff, 0x00, 0x1b, 0x00, 0x01, 0x81, 0x00, 0x01, 0xe7, 0x00, 0x01, 0x4d, 0x01, 0x01, 0xb3, 0x01, 0x01, 0x19, 0x02, 0x01, 0x7f, 0x02, 0x01, 0xe5, 0x02, 0x01, 0x4b, 0x03, 0x01, 0xb1, 0x03, 0x01, 0x17, 0x04, 0x01, 0x7d, 0x04, 0x01, 0xe3, 0x04, 0x01, 0x49, 0x05, 0x01, 0xaf, 0x05, 0x01, 0x15, 0x06, 0x01, 0x7b, 0x06, 0x01, 0xe1, 0x06, 0x01, 0x47, 0x07, 0x01, 0xad, 0x07, 0x01, 0x13, 0x08, 0x01, 0x79, 0x08, 0x01, 0xdf, 0x08, 0x01, 0x45, 0x09, 0x01, 0xab, 0x09, 0x01, 0x11, 0x0a, 0x01, 0x77, 0x0a, 0x01, 0xdd, 0x0a, 0x01, 0x43, 0x0b, 0x01, 0xa9, 0x0b, 0x01, 0x0f, 0x0c, 0x01, 0x75, 0x0c, 0x01, 0xdb, 0x0c, 0x01, 0x41, 0x0d, 0x01, 0xa7, 0x0d, 0x01, 0x0d, 0x0e, 0x01, 0x73, 0x0e, 0x01, 0xd9, 0x0e, 0x01, 0x3f, 0x0f, 0x01, 0xa5, 0x0f, 0x01, 0x0b, 0x10, 0x01, 0x71, 0x10, 0x01, 0xd7, 0x10, 0x01, 0x3d, 0x11, 0x01, 0xa3, 0x11, 0x01, 0x09, 0x12, 0x01, 0x6f, 0x12, 0x01, 0xd5, 0x12, 0x01, 0x3b, 0x13, 0x01, 0xa1, 0x13, 0x01, 0x07, 0x14, 0x01, 0x6d, 0x14, 0x01, 0xd3, 0x14, 0x01, 0x39, 0x15, 0x01, 0x9f, 0x15, 0x01, 0x05, 0x16, 0x01, 0x6b, 0x16, 0x01, 0xd1, 0x16, 0x01, 0x37, 0x17, 0x01, 0x9d, 0x17, 0x01, 0x03, 0x18, 0x01, 0x69, 0x18, 0x01, 0xcf, 0x18, 0x01, 0x35, 0x19, 0x01, 0x9b, 0x19, 0x01, 0x01, 0x1a, 0x01, 0x67, 0x1a, 0x01, 0xcd, 0x1a, 0x01, 0x33, 0x1b, 0x01, 0x99, 0x1b, 0x01, 0xff, 0x1b, 0x01, 0x65, 0x1c, 0x01, 0xcb, 0x1c, 0x01, 0x31, 0x1d, 0x01, 0x97, 0x1d, 0x01, 0xfd, 0x1d, 0x01, 0x63, 0x1e, 0x01, 0xc9, 0x1e, 0x01, 0x2f, 0x1f, 0x01, 0x95, 0x1f, 0x01, 0xfb, 0x1f, 0x01, 0x61, 0x20, 0x01, 0xc7, 0x20, 0x01, 0x2d, 0x21, 0x01, 0x93, 0x21, 0x01, 0xf9, 0x21, 0x01, 0x5f, 0x22, 0x01, 0xc5, 0x22, 0x01, 0x2b, 0x23, 0x01, 0x91, 0x23, 0x01, 0xf7, 0x23, 0x01, 0x5d, 0x24, 0x01, 0xc3, 0x24, 0x01, 0x29, 0x25, 0x01, 0x8f, 0x25, 0x01, 0xf5, 0x25, 0x01, 0x5b, 0x26, 0x01, 0xc1, 0x26, 0x01, 0x27, 0x27, 0x01, 0x8d, 0x27, 0x01, 0xf3, 0x27, 0x01, 0x59, 0x28, 0x01, 0xbf, 0x28, 0x01, 0x25, 0x29, 0x01, 0x8b, 0x29, 0x01, 0xf1, 0x29, 0x01, 0x57, 0x2a, 0x01, 0xbd, 0x2a, 0x01, 0x23, 0x2b, 0x01, 0x89, 0x2b, 0x01, 0xef, 0x2b, 0x01, 0x55, 0x2c, 0x01, 0xbb, 0x2c, 0x01, 0x21, 0x2d, 0x01, 0x87, 0x2d, 0x01, 0xed, 0x2d, 0x01, 0x53, 0x2e, 0x01, 0xb9, 0x2e, 0x01, 0x1f, 0x2f, 0x01, 0x85, 0x2f, 0x01, 0xeb, 0x2f, 0x01, 0x51, 0x30, 0x01, 0xb7, 0x30, 0x01, 0x1d, 0x31, 0x01, 0x83, 0x31, 0x01, 0xe9, 0x31, 0x01, 0x4f, 0x32, 0x01, 0xb5, 0x32, 0x01, 0x1b, 0x33, 0x01, 0x81, 0x33, 0x01, 0xe7, 0x33, 0x01, 0x4d, 0x34, 0x01, 0xb3, 0x34, 0x01, 0x19, 0x35, 0x01, 0x7f, 0x35, 0x01, 0xe5, 0x35, 0x01, 0x4b, 0x36, 0x01, 0xb1, 0x36, 0x01, 0x17, 0x37, 0x01, 0x7d, 0x37, 0x01, 0xe3, 0x37, 0x01, 0x49, 0x38, 0x01, 0xaf, 0x38, 0x01, 0x15, 0x39, 0x01, 0x7b, 0x39, 0x01, 0xe1, 0x39, 0x01, 0x47, 0x3a, 0x01, 0xad, 0x3a, 0x01, 0x13, 0x3b, 0x01, 0x79, 0x3b, 0x01, 0xdf, 0x3b, 0x01, 0x45, 0x3c, 0x01, 0xab, 0x3c, 0x01, 0x11, 0x3d, 0x01, 0x77, 0x3d, 0x01, 0xdd, 0x3d, 0x01, 0x43, 0x3e, 0x01, 0xa9, 0x3e, 0x01, 0x0f, 0x3f, 0x01, 0x75, 0x3f, 0x01, 0xdb, 0x3f, 0x01, 0x41, 0x40, 0x01, 0xa7, 0x40, 0x01, 0x0d, 0x41, 0x01, 0x73, 0x41, 0x01, 0xd9, 0x41, 0x01, 0x3f, 0x42, 0x01, 0xa5, 0x42, 0x01, 0x0b, 0x43, 0x01, 0x71, 0x43, 0x01, 0xd7, 0x43, 0x01, 0x3d, 0x44, 0x01, 0xa3, 0x44, 0x01, 0x09, 0x45, 0x01, 0x6f, 0x45, 0x01, 0xd5, 0x45, 0x01, 0x3b, 0x46, 0x01, 0xa1, 0x46, 0x01, 0x07, 0x47, 0x01, 0x6d, 0x47, 0x01, 0xd3, 0x47, 0x01, 0x39, 0x48, 0x01, 0x9f, 0x48, 0x01, 0x05, 0x49, 0x01, 0x6b, 0x49, 0x01, 0xd1, 0x49, 0x01, 0x37, 0x4a, 0x01, 0x9d, 0x4a, 0x01, 0x03, 0x4b, 0x01, 0x69, 0x4b, 0x01, 0xcf, 0x4b, 0x01, 0x35, 0x4c, 0x01, 0x9b, 0x4c, 0x01, 0x01, 0x4d, 0x01, 0x67, 0x4d, 0x01, 0xcd, 0x4d, 0x01, 0x33, 0x4e, 0x01, 0x99, 0x4e, 0x01, 0xff, 0x4e, 0x01, 0x65, 0x4f, 0x01, 0xcb, 0x4f, 0x01, 0x31, 0x50, 0x01, 0x97, 0x50, 0x01, 0xfd, 0x50, 0x01, 0x63, 0x51, 0x01, 0xc9, 0x51, 0x01, 0x2f, 0x52, 0x01, 0x95, 0x52, 0x01, 0xfb, 0x52, 0x01, 0x61, 0x53, 0x01, 0xc7, 0x53, 0x01, 0x2d, 0x54, 0x01, 0x93, 0x54, 0x01, 0xf9, 0x54, 0x01, 0x5f, 0x55, 0x01, 0xc5, 0x55, 0x01, 0x2b, 0x56, 0x01, 0x91, 0x56, 0x01, 0xf7, 0x56, 0x01, 0x5d, 0x57, 0x01, 0xc3, 0x57, 0x01, 0x29, 0x58, 0x01, 0x8f, 0x58, 0x01, 0xf5, 0x58, 0x01, 0x5b, 0x59, 0x01, 0xc1, 0x59, 0x01, 0x27, 0x5a, 0x01, 0x8d, 0x5a, 0x01, 0xf3, 0x5a, 0x01, 0x59, 0x5b, 0x01, 0xbf, 0x5b, 0x01, 0x25, 0x5c, 0x01, 0x8b, 0x5c, 0x01, 0xf1, 0x5c, 0x01, 0x57, 0x5d, 0x01, 0xbd, 0x5d, 0x01, 0x23, 0x5e, 0x01, 0x89, 0x5e, 0x01, 0xef, 0x5e, 0x01, 0x55, 0x5f, 0x01, 0xbb, 0x5f, 0x01, 0x21, 0x60, 0x01, 0x87, 0x60, 0x01, 0xed, 0x60, 0x01, 0x53, 0x61, 0x01, 0xb9, 0x61, 0x01, 0x1f, 0x62, 0x01, 0x85, 0x62, 0x01, 0xeb, 0x62, 0x01, 0x51, 0x63, 0x01, 0xb7, 0x63, 0x01, 0x1d, 0x64, 0x01, 0x83, 0x64, 0x01, 0xe9, 0x64, 0x01, 0x4f, 0x65, 0x01, 0xb5, 0x65, 0x01, 0x1b, 0x66, 0x01, 0x81, 0x66, 0x01, 0xe7, 0x66, 0x01, 0x4d, 0x67, 0x01, 0xb3, 0x67, 0x01, 0x19, 0x68, 0x01, 0x7f, 0x68, 0x01, 0xe5, 0x68, 0x01, 0x4b, 0x69, 0x01, 0xb1, 0x69, 0x01, 0x17, 0x6a, 0x01, 0x7d, 0x6a, 0x01, 0xe3, 0x6a, 0x01, 0x49, 0x6b, 0x01, 0xaf, 0x6b, 0x01, 0x15, 0x6c, 0x01, 0x7b, 0x6c, 0x01, 0xe1, 0x6c, 0x01, 0x47, 0x6d, 0x01, 0xad, 0x6d, 0x01, 0x13, 0x6e, 0x01, 0x79, 0x6e, 0x01, 0xdf, 0x6e, 0x01, 0x45, 0x6f, 0x01, 0xab, 0x6f, 0x01, 0x11, 0x70, 0x01, 0x77, 0x70, 0x01, 0xdd, 0x70, 0x01, 0x43, 0x71, 0x01, 0xa9, 0x71, 0x01, 0x0f, 0x72, 0x01, 0x75, 0x72, 0x01, 0xdb, 0x72, 0x01, 0x41, 0x73, 0x01, 0xa7, 0x73, 0x01, 0x0d, 0x74, 0x01, 0x73, 0x74, 0x01, 0xd9, 0x74, 0x01, 0x3f, 0x75, 0x01, 0xa5, 0x75, 0x01, 0x0b, 0x76, 0x01, 0x71, 0x76, 0x01, 0xd7, 0x76, 0x01, 0x3d, 0x77, 0x01, 0xa3, 0x77, 0x01, 0x09, 0x78, 0x01, 0x6f, 0x78, 0x01, 0xd5, 0x78, 0x01, 0x3b, 0x79, 0x01, 0xa1, 0x79, 0x01, 0x07, 0x7a, 0x01, 0x6d, 0x7a, 0x01, 0xd3, 0x7a, 0x01, 0x39, 0x7b, 0x01, 0x9f, 0x7b, 0x01, 0x05, 0x7c, 0x01, 0x6b, 0x7c, 0x01, 0xd1, 0x7c, 0x01, 0x37, 0x7d, 0x01, 0x9d, 0x7d, 0x01, 0x03, 0x7e, 0x01, 0x69, 0x7e, 0x01, 0xcf, 0x7e, 0x01, 0x35, 0x7f, 0x01, 0x9b, 0x7f, 0x01, 0x01, 0x80, 0x01, 0x67, 0x80, 0x01, 0xcd, 0x80, 0x01, 0x33, 0x81, 0x01, 0x99, 0x81, 0x01, 0xff, 0x81, 0x01, 0x65, 0x82, 0x01, 0xcb, 0x82, 0x01, 0x31, 0x83, 0x01, 0x97, 0x83, 0x01, 0xfd, 0x83, 0x01, 0x63, 0x84, 0x01, 0xc9, 0x84, 0x01, 0x2f, 0x85, 0x01, 0x95, 0x85, 0x01, 0xfb, 0x85, 0x01, 0x61, 0x86, 0x01, 0xc7, 0x86, 0x01, 0x2d, 0x87, 0x01, 0x93, 0x87, 0x01, 0xf9, 0x87, 0x01, 0x5f, 0x88, 0x01, 0xc5, 0x88, 0x01, 0x2b, 0x89, 0x01, 0x91, 0x89, 0x01, 0xf7, 0x89, 0x01, 0x5d, 0x8a, 0x01, 0xc3, 0x8a, 0x01, 0x29, 0x8b, 0x01, 0x8f, 0x8b, 0x01, 0xf5, 0x8b, 0x01, 0x5b, 0x8c, 0x01, 0xc1, 0x8c, 0x01, 0x27, 0x8d, 0x01, 0x8d, 0x8d, 0x01, 0xf3, 0x8d, 0x01, 0x59, 0x8e, 0x01, 0xbf, 0x8e, 0x01, 0x25, 0x8f, 0x01, 0x8b, 0x8f, 0x01, 0xf1, 0x8f, 0x01, 0x57, 0x90, 0x01, 0xbd, 0x90, 0x01, 0x23, 0x91, 0x01, 0x89, 0x91, 0x01, 0xef, 0x91, 0x01, 0x55, 0x92, 0x01, 0xbb, 0x92, 0x01, 0x21, 0x93, 0x01, 0x87, 0x93, 0x01, 0xed, 0x93, 0x01, 0x53, 0x94, 0x01, 0xb9, 0x94, 0x01, 0x1f, 0x95, 0x01, 0x85, 0x95, 0x01, 0xeb, 0x95, 0x01, 0x51, 0x96, 0x01, 0xb7, 0x96, 0x01, 0x1d, 0x97, 0x01, 0x83, 0x97, 0x01, 0xe9, 0x97, 0x01, 0x4f, 0x98, 0x01, 0xb5, 0x98, 0x01, 0x1b, 0x99, 0x01, 0x81, 0x99, 0x01, 0xe7, 0x99, 0x01, 0x4d, 0x9a, 0x01, 0xb3, 0x9a, 0x01, 0x19, 0x9b, 0x01, 0x7f, 0x9b, 0x01, 0xe5, 0x9b, 0x01, 0x4b, 0x9c, 0x01, 0xb1, 0x9c, 0x01, 0x17, 0x9d, 0x01, 0x7d, 0x9d, 0x01, 0xe3, 0x9d, 0x01, 0x49, 0x9e, 0x01, 0xaf, 0x9e, 0x01, 0x15, 0x9f, 0x01, 0x7b, 0x9f, 0x01, 0xe1, 0x9f, 0x01, 0x47, 0xa0, 0x01, 0xad, 0xa0, 0x01, 0x13, 0xa1, 0x01, 0x79, 0xa1, 0x01, 0xdf, 0xa1, 0x01, 0x45, 0xa2, 0x01, 0xab, 0xa2, 0x01, 0x11, 0xa3, 0x01, 0x77, 0xa3, 0x01, 0xdd, 0xa3, 0x01, 0x43, 0xa4, 0x01, 0xa9, 0xa4, 0x01, 0x0f, 0xa5, 0x01, 0x75, 0xa5, 0x01, 0xdb, 0xa5, 0x01, 0x41, 0xa6, 0x01, 0xa7, 0xa6, 0x01, 0x0d, 0xa7, 0x01, 0x73, 0xa7, 0x01, 0xd9, 0xa7, 0x01, 0x3f, 0xa8, 0x01, 0xa5, 0xa8, 0x01, 0x0b, 0xa9, 0x01, 0x71, 0xa9, 0x01, 0xd7, 0xa9, 0x01, 0x3d, 0xaa, 0x01, 0xa3, 0xaa, 0x01, 0x09, 0xab, 0x01, 0x6f, 0xab, 0x01, 0xd5, 0xab, 0x01, 0x3b, 0xac, 0x01, 0xa1, 0xac, 0x01, 0x07, 0xad, 0x01, 0x6d, 0xad, 0x01, 0xd3, 0xad, 0x01, 0x39, 0xae, 0x01, 0x9f, 0xae, 0x01, 0x05, 0xaf, 0x01, 0x6b, 0xaf, 0x01, 0xd1, 0xaf, 0x01, 0x37, 0xb0, 0x01, 0x9d, 0xb0, 0x01, 0x03, 0xb1, 0x01, 0x69, 0xb1, 0x01, 0xcf, 0xb1, 0x01, 0x35, 0xb2, 0x01, 0x9b, 0xb2, 0x01, 0x01, 0xb3, 0x01, 0x67, 0xb3, 0x01, 0xcd, 0xb3, 0x01, 0x33, 0xb4, 0x01, 0x99, 0xb4, 0x01, 0xff, 0xb4, 0x01, 0x65, 0xb5, 0x01, 0xcb, 0xb5, 0x01, 0x31, 0xb6, 0x01, 0x97, 0xb6, 0x01, 0xfd, 0xb6, 0x01, 0x63, 0xb7, 0x01, 0xc9, 0xb7, 0x01, 0x2f, 0xb8, 0x01, 0x95, 0xb8, 0x01, 0xfb, 0xb8, 0x01, 0x61, 0xb9, 0x01, 0xc7, 0xb9, 0x01, 0x2d, 0xba, 0x01, 0x93, 0xba, 0x01, 0xf9, 0xba, 0x01, 0x5f, 0xbb, 0x01, 0xc5, 0xbb, 0x01, 0x2b, 0xbc, 0x01, 0x91, 0xbc, 0x01, 0xf7, 0xbc, 0x01, 0x5d, 0xbd, 0x01, 0xc3, 0xbd, 0x01, 0x29, 0xbe, 0x01, 0x8f, 0xbe, 0x01, 0xf5, 0xbe, 0x01, 0x5b, 0xbf, 0x01, 0xc1, 0xbf, 0x01, 0x27, 0xc0, 0x01, 0x8d, 0xc0, 0x01, 0xf3, 0xc0, 0x01, 0x59, 0xc1, 0x01, 0xbf, 0xc1, 0x01, 0x25, 0xc2, 0x01, 0x8b, 0xc2, 0x01, 0xf1, 0xc2, 0x01, 0x57, 0xc3, 0x01, 0xbd, 0xc3, 0x01, 0x23, 0xc4, 0x01, 0x89, 0xc4, 0x01, 0xef, 0xc4, 0x01, 0x55, 0xc5, 0x01, 0xbb, 0xc5, 0x01, 0x21, 0xc6, 0x01, 0x87, 0xc6, 0x01, 0xed, 0xc6, 0x01, 0x53, 0xc7, 0x01, 0xb9, 0xc7, 0x01, 0x1f, 0xc8, 0x01, 0x85, 0xc8, 0x01, 0xeb, 0xc8, 0x01, 0x51, 0xc9, 0x01, 0xb7, 0xc9, 0x01, 0x1d, 0xca, 0x01, 0x83, 0xca, 0x01, 0xe9, 0xca, 0x01, 0x4f, 0xcb, 0x01, 0xb5, 0xcb, 0x01, 0x1b, 0xcc, 0x01, 0x1f, 0x04, 0x07, 0x04, 0x04, 0x02, 0x03, 0x10, 0x00, 0x00, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x0a, 0x06, 0x00, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x10, 0x00, 0x00, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x1f, 0x00, 0x08, 0x00, 0x06, 0x00, 0x03, 0x0a, 0x06, 0x00, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x1e, 0x0b, 0x06, 0x04, 0x04, 0x03, 0x04, 0x0c, 0x04, 0x00, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x13, 0xf8, 0x01, 0x87, 0xf9, 0x01, 0x87, 0xf9, 0x01, 0x35, 0xee, 0x01, 0xa9, 0xf2, 0x01, 0xa9, 0xf2, 0x01, 0x35, 0xee, 0x01, 0xa9, 0xf2, 0x01, 0xa9, 0xf2, 0x01, 0x1e, 0x04, 0x0b, 0x04, 0x08, 0x02, 0x06, 0x04, 0x06, 0x06, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x18, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x0a, 0x06, 0x00, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x08, 0x04, 0x04, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0xb7, 0x11, 0x02, 0x21, 0x17, 0x02, 0x09, 0x1d, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x03, 0x05, 0x08, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0x7c, 0x00, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x73, 0x30, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xf0, 0x3c, 0x03, 0x55, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0xff, 0x00, 0x03, 0x55, 0x55, 0xff, 0x00, 0x3d, 0x55, 0x55, 0xff, 0x00, 0xcd, 0x55, 0x55, 0xcf, 0xff, 0x0d, 0x55, 0x55, 0x73, 0x30, 0x3d, 0x55, 0x55, 0x73, 0xf0, 0xf5, 0x55, 0x55, 0x73, 0xf0, 0x35, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x7f, 0x55, 0x57, 0xff, 0x55, 0xff, 0xd5, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x0f, 0x00, 0xf0, 0xd5, 0x57, 0x30, 0xc3, 0x0c, 0xd5, 0x57, 0x00, 0x3c, 0x00, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x57, 0x3f, 0xff, 0xfc, 0xd5, 0x57, 0xf0, 0xc3, 0x0f, 0xd5, 0x55, 0x73, 0xff, 0xcd, 0x55, 0x55, 0xc3, 0xff, 0xc3, 0x55, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x03, 0x00, 0xc0, 0xd5, 0x57, 0x0c, 0x00, 0x30, 0xd5, 0x57, 0x00, 0x3c, 0x00, 0xd5, 0x55, 0xc0, 0xff, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x3f, 0x0f, 0xc3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x00, 0xf0, 0x0d, 0x55, 0x55, 0xff, 0x0f, 0xf5, 0x55, 0x57, 0x33, 0xfc, 0xcd, 0x55, 0x57, 0xf3, 0xfc, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x30, 0x00, 0x0c, 0xd5, 0x57, 0x0c, 0x00, 0x30, 0xd5, 0x57, 0x00, 0xff, 0x00, 0xd5, 0x5f, 0x03, 0xff, 0xc0, 0xf5, 0x5c, 0xc3, 0xff, 0xc3, 0x35, 0x5f, 0x3f, 0xff, 0xfc, 0xf5, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0xc3, 0xff, 0xc3, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x7f, 0x55, 0x57, 0xff, 0x55, 0xff, 0xd5, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x03, 0x00, 0xc0, 0xd5, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x30, 0x3c, 0x0c, 0xd5, 0x55, 0xcc, 0x3c, 0x33, 0xd5, 0x55, 0xcc, 0x3c, 0x33, 0x55, 0x55, 0xc3, 0xc3, 0xc3, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xd7, 0xf5, 0x55, 0x55, 0x5f, 0x55, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x5c, 0x3f, 0xff, 0xc3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x55, 0xff, 0xff, 0xf5, 0x55, 0x55, 0xc0, 0x00, 0x35, 0x55, 0x57, 0x30, 0x00, 0xcd, 0x55, 0x57, 0xf0, 0x00, 0xfd, 0x55, 0x55, 0x70, 0x00, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0x55, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0x70, 0x00, 0x3d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x70, 0x0c, 0xd5, 0x55, 0x57, 0xc0, 0xfc, 0xd5, 0x55, 0x55, 0xf0, 0x3f, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0x57, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0x70, 0x00, 0x3d, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x30, 0xcd, 0x55, 0x55, 0xfc, 0x3f, 0xf5, 0x55, 0x55, 0x70, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x70, 0x3f, 0xf5, 0x55, 0x55, 0xc0, 0x0f, 0xf5, 0x55, 0x7f, 0xc0, 0x0f, 0xf5, 0x5f, 0xc0, 0xc0, 0x0f, 0x55, 0x5f, 0xc0, 0xc0, 0xcf, 0xd5, 0x55, 0xc0, 0xc0, 0xcf, 0xd5, 0x57, 0xc0, 0x3c, 0xcf, 0xf5, 0x5f, 0xfc, 0x03, 0x0f, 0xf5, 0x5f, 0xff, 0xff, 0xf7, 0xd5, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x3c, 0x03, 0xc3, 0x55, 0x5c, 0xc3, 0x0c, 0x33, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0xc3, 0x0c, 0x33, 0x55, 0x57, 0x30, 0xf0, 0xcc, 0xd5, 0x55, 0xff, 0xff, 0xf0, 0xd5, 0x55, 0x73, 0x0c, 0x03, 0x55, 0x55, 0xcc, 0xfc, 0x0d, 0x55, 0x55, 0xfc, 0xff, 0x0d, 0x55, 0x55, 0x5c, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x55, 0xf5, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x00, 0xc3, 0x00, 0xd5, 0x57, 0x3f, 0xc3, 0xfc, 0xd5, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x5c, 0xcc, 0x35, 0x55, 0x55, 0x73, 0xff, 0xcd, 0x55, 0x55, 0x70, 0xfc, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xc0, 0x30, 0x03, 0x55, 0x55, 0xc0, 0xc0, 0x03, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xfc, 0x00, 0x03, 0x55, 0x55, 0xff, 0x03, 0xc3, 0x55, 0x55, 0x7f, 0x03, 0x3d, 0x55, 0x55, 0x5f, 0xff, 0x35, 0x55, 0x55, 0x5c, 0xcc, 0x0d, 0x55, 0x55, 0x57, 0x3c, 0x03, 0x55, 0x55, 0x57, 0x3c, 0x3f, 0x55, 0x55, 0x57, 0xff, 0xf5, 0x55, 0x55, 0x55, 0x7d, 0xfd, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0x7f, 0x55, 0x55, 0x55, 0xff, 0xff, 0xd5, 0x55, 0x55, 0xff, 0xff, 0xd5, 0x55, 0x55, 0xff, 0x00, 0x35, 0x55, 0x57, 0xf0, 0x00, 0x3d, 0x55, 0x57, 0xc0, 0x03, 0x03, 0x55, 0x57, 0x00, 0x3c, 0x03, 0x55, 0x57, 0x00, 0x00, 0x0f, 0x55, 0x57, 0x00, 0x00, 0x35, 0x55, 0x57, 0xc0, 0x03, 0xd5, 0x55, 0x55, 0x7f, 0xff, 0x55, 0x55, 0x55, 0xc0, 0xcf, 0x55, 0x55, 0x57, 0x30, 0xfd, 0x55, 0x55, 0x57, 0xf0, 0xfd, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x7d, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xf5, 0x55, 0x55, 0x5f, 0xfd, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0x00, 0x0d, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x0f, 0xc3, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0x70, 0x00, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x5c, 0x3c, 0xd5, 0x55, 0x55, 0x5f, 0x0f, 0xd5, 0x55, 0x55, 0x5c, 0xff, 0xd5, 0x55, 0x55, 0x70, 0x0f, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3c, 0x0f, 0x55, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0xc0, 0x00, 0xff, 0x55, 0x55, 0xc0, 0xf0, 0xff, 0x55, 0x55, 0x70, 0xcc, 0xfd, 0x55, 0x55, 0x5f, 0xcf, 0xd5, 0x55, 0x55, 0x5c, 0xcc, 0xd5, 0x55, 0x55, 0x5c, 0x3f, 0xd5, 0x55, 0x55, 0x5c, 0x0f, 0xd5, 0x55, 0x55, 0x70, 0x0f, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x55, 0xfd, 0x55, 0x55, 0x7f, 0xdf, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0xc3, 0x55, 0x55, 0xcc, 0x00, 0x03, 0x55, 0x55, 0x73, 0x00, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x73, 0x30, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0x7f, 0x55, 0x55, 0xff, 0xd5, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0xd5, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0x70, 0x00, 0x03, 0x55, 0x55, 0xc3, 0x00, 0x30, 0xd5, 0x55, 0xcc, 0xc0, 0xcc, 0xd5, 0x55, 0xc3, 0x00, 0x30, 0xd5, 0x57, 0xc0, 0x3f, 0x00, 0xd5, 0x57, 0x30, 0xff, 0xc3, 0x55, 0x55, 0xcf, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xc3, 0xfc, 0x03, 0x55, 0x55, 0xc3, 0xfc, 0x3c, 0xd5, 0x55, 0x7f, 0xfc, 0x37, 0xd5, 0x55, 0x5f, 0x7f, 0xd5, 0x55, 0x55, 0x55, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x3c, 0x03, 0xc3, 0x55, 0x5c, 0xf3, 0x0f, 0x33, 0x55, 0x5c, 0xff, 0x0f, 0xf3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x0f, 0xf0, 0x0d, 0x55, 0x55, 0xfc, 0x3f, 0xf5, 0x55, 0x55, 0xc3, 0xcc, 0x3d, 0x55, 0x55, 0x70, 0xfc, 0xf3, 0x55, 0x55, 0x70, 0xfc, 0xdf, 0x55, 0x55, 0x7f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xcd, 0x55, 0x5f, 0xff, 0xff, 0xfd, 0x55, 0x7f, 0xff, 0xff, 0xd5, 0x55, 0x70, 0x00, 0x03, 0xd5, 0x55, 0xff, 0xff, 0xfc, 0xd5, 0x55, 0xc0, 0x00, 0x0f, 0xd5, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0x7c, 0x00, 0x0c, 0xd5, 0x55, 0x5f, 0xff, 0xf0, 0x35, 0x55, 0x7f, 0x3f, 0xfc, 0x0d, 0x55, 0x7f, 0x3f, 0xfc, 0x0d, 0x55, 0x70, 0x00, 0x3c, 0x0d, 0x55, 0x7f, 0xff, 0xf0, 0x0d, 0x55, 0x5f, 0xff, 0xdf, 0xf5, 0x55, 0x7f, 0xdf, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0x55, 0x55, 0x55, 0x57, 0x35, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0xff, 0xff, 0x55, 0x55, 0x5f, 0xff, 0xff, 0x55, 0x55, 0x70, 0x00, 0x0f, 0x55, 0x55, 0x7f, 0xff, 0xf3, 0xfd, 0x55, 0xc0, 0x00, 0x0c, 0xc3, 0x55, 0xc0, 0x00, 0x03, 0xc3, 0x55, 0xc0, 0x00, 0x03, 0x03, 0x55, 0xf0, 0x03, 0x03, 0xc3, 0x55, 0xc3, 0xc0, 0x0f, 0xc3, 0x55, 0xc3, 0xc0, 0x3f, 0x0d, 0x55, 0x7f, 0xff, 0xfc, 0x35, 0x5d, 0xff, 0x3f, 0xf3, 0xd5, 0x5f, 0x00, 0x00, 0xfd, 0x55, 0x5f, 0xff, 0xff, 0x3d, 0x55, 0x55, 0xff, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xff, 0x55, 0x55, 0x7f, 0xff, 0xff, 0xd5, 0x55, 0xf0, 0x00, 0x03, 0xf5, 0x55, 0xcf, 0xff, 0xfc, 0xf5, 0x55, 0xf0, 0x00, 0x03, 0xff, 0x57, 0x0f, 0xc0, 0xfc, 0xf3, 0x57, 0x33, 0xc3, 0x3c, 0xdf, 0x57, 0x33, 0xc3, 0x3c, 0xd5, 0x57, 0x0f, 0xc0, 0xfc, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x35, 0x55, 0xff, 0xff, 0xfc, 0x0d, 0x57, 0xff, 0xcf, 0xf3, 0x0d, 0x5c, 0xff, 0xcf, 0xff, 0x0d, 0x57, 0x70, 0x00, 0x0c, 0x0d, 0x55, 0x7f, 0xff, 0xf7, 0xf5, 0x55, 0x57, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xf7, 0xfd, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xff, 0xf5, 0x55, 0x70, 0x00, 0xff, 0xff, 0x55, 0x7f, 0xfc, 0x03, 0xf3, 0x55, 0xf0, 0xff, 0xf0, 0xdf, 0x55, 0xf0, 0xf3, 0x0f, 0xd5, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xff, 0xf0, 0x33, 0x55, 0x57, 0x3f, 0xc0, 0xff, 0xd5, 0x57, 0xcf, 0xff, 0xfc, 0x35, 0x55, 0xff, 0x3f, 0xfc, 0x0d, 0x55, 0x7f, 0x3f, 0xf0, 0x0d, 0x55, 0x7f, 0x3f, 0xf0, 0x0d, 0x55, 0x70, 0x00, 0xf0, 0x0d, 0x55, 0x5f, 0xff, 0xdf, 0xf5, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x55, 0xf7, 0xd5, 0x55, 0x30, 0x1f, 0x01, 0x55, 0x40, 0x00, 0x00, 0x00, 0x15, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x11, 0x41, 0x50, 0x00, 0x00, 0x15, 0x55, 0x55, 0x54, 0x04, 0x10, 0x01, 0x55, 0x41, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa1, 0x14, 0x15, 0x54, 0x01, 0x11, 0x45, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa5, 0x54, 0x15, 0x54, 0x01, 0x55, 0x45, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa1, 0x14, 0x44, 0x11, 0x55, 0x55, 0x55, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x15, 0x40, 0x01, 0x55, 0x11, 0x56, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x95, 0x40, 0x01, 0x55, 0x55, 0x56, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x95, 0x55, 0x55, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x55, 0x50, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x01, 0x50, 0x55, 0x50, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x15, 0x55, 0x55, 0x54, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x02, 0x55, 0x55, 0x55, 0x00, 0x04, 0x00, 0x80, 0x28, 0x00, 0x00, 0xa0, 0x02, 0x01, 0x15, 0x55, 0x10, 0x04, 0x55, 0x80, 0x28, 0x00, 0x00, 0xa0, 0x02, 0x01, 0x15, 0x55, 0x01, 0x55, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x02, 0x55, 0x55, 0x55, 0x01, 0x01, 0x00, 0x80, 0xaa, 0xaa, 0xaa, 0xa8, 0x02, 0x00, 0x04, 0x01, 0x01, 0x55, 0x00, 0x82, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x04, 0x01, 0x00, 0x41, 0x00, 0x82, 0xaa, 0xaa, 0xaa, 0xaa, 0x02, 0x00, 0x04, 0x01, 0x55, 0x5a, 0xa5, 0x80, 0x95, 0x95, 0x80, 0x00, 0x02, 0x55, 0x54, 0x01, 0x00, 0x25, 0x58, 0x80, 0x95, 0x95, 0x85, 0x54, 0x0a, 0xaa, 0xa8, 0x01, 0x00, 0x26, 0x98, 0x80, 0x95, 0x95, 0x85, 0x54, 0x08, 0x00, 0x09, 0x55, 0x00, 0x25, 0x58, 0x80, 0x95, 0x95, 0xaa, 0xaa, 0x08, 0x88, 0x88, 0x00, 0x00, 0x20, 0x08, 0x95, 0x95, 0x95, 0x80, 0x02, 0x58, 0x88, 0x88, 0x00, 0xaa, 0xa0, 0x0a, 0x95, 0x95, 0x95, 0x80, 0x02, 0x58, 0x00, 0x0a, 0xaa, 0x04, 0x20, 0x08, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa9, 0x55, 0x58, 0x00, 0x00, 0x0a, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xaa, 0xa9, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0x42, 0x82, 0x20, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa6, 0x86, 0x26, 0x62, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x45, 0x86, 0x24, 0xa4, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xa4, 0xa1, 0x61, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x61, 0x40, 0xa2, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0xaa, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa9, 0x55, 0x69, 0x55, 0x6a, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x9a, 0xa9, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x59, 0x59, 0x6a, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x98, 0x49, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x95, 0x55, 0xaa, 0x95, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa5, 0x56, 0xaa, 0x40, 0x68, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa8, 0x0a, 0xa5, 0x55, 0x58, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa9, 0x5a, 0xa5, 0x55, 0x58, 0x00, 0x95, 0x5a, 0x69, 0xa5, 0x56, 0x02, 0xa5, 0x96, 0xa9, 0x69, 0x68, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x96, 0x5a, 0x69, 0xa5, 0x96, 0x54, 0x54, 0x54, 0x54, 0x54, 0x55, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x54, 0x54, 0x54, 0x54, 0x54, 0x55, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x30, 0x1f, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x15, 0x00, 0x00, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x55, 0x00, 0x01, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x40, 0x51, 0x55, 0x55, 0x15, 0x54, 0x00, 0x00, 0x15, 0x54, 0x55, 0x55, 0x45, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x40, 0x00, 0x44, 0x11, 0x10, 0x11, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x44, 0x04, 0x44, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x40, 0x00, 0x44, 0x15, 0x05, 0x41, 0x50, 0x05, 0x55, 0x55, 0x50, 0x05, 0x41, 0x50, 0x54, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x50, 0x40, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x50, 0x40, 0x01, 0x00, 0x01, 0x00, 0x17, 0xfc, 0x3f, 0xfc, 0x00, 0x43, 0xff, 0xc0, 0x01, 0x00, 0x01, 0x00, 0x1f, 0xf4, 0xff, 0xd4, 0x00, 0x4f, 0xfc, 0x40, 0x01, 0x55, 0x55, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x40, 0x01, 0x11, 0x11, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x40, 0x01, 0x00, 0x01, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xc0, 0x01, 0x05, 0x41, 0x00, 0xf0, 0xfc, 0x03, 0xff, 0xff, 0x00, 0x00, 0xc0, 0x01, 0x05, 0x41, 0x00, 0xf0, 0xf3, 0x0c, 0x71, 0xc7, 0x33, 0x30, 0xc0, 0xaa, 0xaa, 0xaa, 0xaa, 0xf0, 0xf3, 0x0d, 0x75, 0xd7, 0x33, 0x30, 0xea, 0x55, 0x55, 0x55, 0x55, 0xf0, 0xfc, 0x0d, 0x34, 0xd3, 0x33, 0x30, 0xd5, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x0d, 0x34, 0xc3, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x03, 0xff, 0xff, 0xaa, 0xaa, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 0xc0, 0x00, 0xfc, 0x0f, 0xc0, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x3a, 0xbf, 0xfa, 0xab, 0xff, 0xbf, 0xfb, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0xff, 0xff, 0xcf, 0xfc, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf0, 0x03, 0xff, 0x3f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xc0, 0x00, 0xfc, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x55, 0x51, 0x55, 0x55, 0x15, 0x54, 0x00, 0x00, 0x15, 0x10, 0x00, 0x00, 0x40, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x40, 0x11, 0x10, 0x11, 0x10, 0x04, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x40, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x15, 0x55, 0x55, 0x40, 0x15, 0x05, 0x41, 0x50, 0x05, 0x55, 0x55, 0x50, 0x00, 0x00, 0x00, 0x00, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf5, 0xff, 0xf0, 0x00, 0x0f, 0xff, 0x00, 0x50, 0x50, 0x50, 0x50, 0x3f, 0xc3, 0xff, 0x00, 0x14, 0x3f, 0xf4, 0x14, 0x55, 0x50, 0x55, 0x50, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x54, 0x55, 0x50, 0x55, 0x50, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x54, 0x55, 0x55, 0x55, 0x53, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x54, 0x40, 0x10, 0x40, 0x13, 0xc3, 0xf0, 0x0f, 0xff, 0xfc, 0x00, 0x03, 0x04, 0x50, 0x50, 0x50, 0x53, 0xc3, 0xcc, 0x31, 0xc7, 0x1c, 0xcc, 0xc3, 0x14, 0x40, 0x10, 0x40, 0x13, 0xc3, 0xcc, 0x35, 0xd7, 0x5c, 0xcc, 0xc3, 0x04, 0xaa, 0xaa, 0xaa, 0xab, 0xc3, 0xf0, 0x34, 0xd3, 0x4c, 0xcc, 0xc3, 0xaa, 0x55, 0x55, 0x55, 0x57, 0x00, 0x00, 0x34, 0xd3, 0x0c, 0x00, 0x03, 0x55, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x0f, 0xff, 0xfe, 0xaa, 0xab, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x3f, 0x00, 0x03, 0xf0, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xea, 0xff, 0xea, 0xaf, 0xfe, 0xff, 0xec, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf3, 0xff, 0xff, 0x3f, 0xf3, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x0f, 0xfc, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x03, 0xf0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xfd, 0x7d, 0x7f, 0x5d, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x5d, 0xd5, 0xd7, 0x75, 0xdd, 0xd5, 0x55, 0x55, 0x55, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x30, 0xcc, 0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0xc0, 0xff, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xc0, 0xc3, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0x3f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xfc, 0x3f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x03, 0xc0, 0x30, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0xf3, 0xff, 0xff, 0xcf, 0x00, 0x00, 0x0f, 0xf0, 0x70, 0x0f, 0x55, 0x55, 0xc3, 0x0c, 0x30, 0xc3, 0x55, 0x55, 0xf0, 0x0d, 0xc3, 0x30, 0xd5, 0xff, 0x7c, 0xcf, 0xf3, 0x3d, 0xff, 0x57, 0x0c, 0xc3, 0xc0, 0x3f, 0x5f, 0x03, 0x57, 0xcf, 0xf3, 0xd5, 0xc0, 0xf5, 0xfc, 0x03, 0xc0, 0x30, 0xdc, 0x0d, 0x5f, 0xff, 0xff, 0xf5, 0x70, 0x37, 0x0c, 0x03, 0x7f, 0xff, 0x5f, 0xf5, 0x5f, 0x55, 0x55, 0xf5, 0x5f, 0xf5, 0xff, 0xfd, 0x30, 0x1f, 0xa4, 0x00, 0xa4, 0x01, 0x90, 0x00, 0x64, 0x06, 0x40, 0x1a, 0x00, 0x16, 0xa9, 0x40, 0x09, 0x00, 0x40, 0x00, 0x10, 0x01, 0x00, 0x60, 0x01, 0x6a, 0x2a, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xaa, 0x00, 0xa5, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x01, 0x6a, 0x80, 0x00, 0x01, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x30, 0xc0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x00, 0x05, 0x94, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x15, 0x56, 0xa5, 0x55, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x15, 0x40, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x29, 0x50, 0x15, 0x68, 0x00, 0x40, 0x07, 0xf0, 0x0f, 0xc0, 0x10, 0x00, 0x0a, 0xa5, 0x6a, 0x80, 0x01, 0x00, 0x1f, 0xfc, 0x3f, 0xf0, 0x04, 0x00, 0x00, 0xaa, 0xa8, 0x00, 0x15, 0x00, 0x1f, 0xff, 0xff, 0xf0, 0x05, 0x40, 0x00, 0x0a, 0xa0, 0x00, 0x04, 0x00, 0x5c, 0x00, 0x00, 0x30, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xf0, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xc0, 0x33, 0x00, 0x00, 0xcc, 0x03, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x30, 0x03, 0xc0, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x0c, 0x30, 0x03, 0xc0, 0x0c, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x3c, 0x03, 0xc0, 0x3c, 0xff, 0xc0, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0xc3, 0xff, 0xff, 0xc3, 0x00, 0x00, 0x0f, 0xf0, 0x30, 0x0c, 0x00, 0x00, 0xcc, 0x30, 0x0c, 0x33, 0x00, 0x00, 0x30, 0x0c, 0xc3, 0x0f, 0x00, 0x00, 0x3f, 0x3f, 0xfc, 0xfc, 0x00, 0x00, 0xf0, 0xc3, 0xc0, 0x30, 0xc0, 0x00, 0x03, 0x3f, 0xfc, 0xc0, 0x00, 0x03, 0x0c, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0xfc, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x3f, 0xfc, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x30, 0x30, 0xc0, 0x00, 0x00, 0x3c, 0x3c, 0x00, 0x00, 0x03, 0x0c, 0x0c, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x0c, 0x30, 0x00, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xfd, 0x7d, 0x7f, 0x5d, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x5d, 0xd5, 0xd7, 0x75, 0xdd, 0xd5, 0x55, 0x55, 0x55, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x30, 0xcc, 0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0xc0, 0xff, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xc0, 0xc3, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x70, 0x0f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xf0, 0x0d, 0xc3, 0x30, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x0c, 0xc3, 0xc0, 0x3f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfc, 0x03, 0xc0, 0x30, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x0c, 0x03, 0x7f, 0xff, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xfd, 0x30, 0x1f, 0xa4, 0x00, 0xa4, 0x01, 0x90, 0x00, 0x64, 0x06, 0x40, 0x1a, 0x00, 0x16, 0xa9, 0x40, 0x09, 0x00, 0x40, 0x00, 0x10, 0x01, 0x00, 0x60, 0x01, 0x6a, 0x2a, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xaa, 0x00, 0xa5, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x01, 0x6a, 0x80, 0x00, 0x01, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x30, 0xc0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x00, 0x05, 0x94, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x15, 0x56, 0xa5, 0x55, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x15, 0x40, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x29, 0x50, 0x15, 0x68, 0x00, 0x40, 0x04, 0x00, 0x04, 0x00, 0x10, 0x00, 0x0a, 0xa5, 0x6a, 0x80, 0x01, 0x00, 0x14, 0x00, 0x05, 0x00, 0x04, 0x00, 0x00, 0xaa, 0xa8, 0x00, 0x15, 0x00, 0x15, 0x00, 0x15, 0x00, 0x05, 0x40, 0x00, 0x0a, 0xa0, 0x00, 0x04, 0x00, 0x54, 0x00, 0x05, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x30, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0c, 0xc3, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xc3, 0xc0, 0x30, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x30, 0x30, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x0c, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xfc, 0x00, 0xc3, 0x0f, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xc3, 0x00, 0xc3, 0x30, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xcc, 0xc3, 0x00, 0xff, 0x30, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xfc, 0x00, 0xc3, 0x30, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xc0, 0x00, 0xc3, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x3f, 0x0f, 0xcf, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0xcc, 0x0c, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0xcf, 0xcf, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0x0f, 0xcf, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x30, 0xcc, 0x33, 0x0c, 0xfc, 0xfc, 0x00, 0x00, 0xc0, 0x00, 0x00, 0xc3, 0x30, 0xcf, 0x33, 0xcc, 0xc0, 0xc3, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc3, 0x30, 0xcc, 0xf3, 0x3c, 0xfc, 0xc3, 0x00, 0x00, 0xfc, 0x00, 0x00, 0xfc, 0x30, 0xcc, 0x33, 0x0c, 0xc0, 0xfc, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc3, 0x0f, 0x0c, 0x33, 0x0c, 0xfc, 0xc3, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x1f, 0x05, 0x55, 0x55, 0x55, 0x55, 0x55, 0x54, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x05, 0x54, 0x55, 0x45, 0x51, 0x10, 0x00, 0x04, 0x04, 0x55, 0x44, 0x51, 0x11, 0x55, 0x44, 0x04, 0x44, 0x44, 0x51, 0x11, 0x00, 0x44, 0x04, 0x44, 0x44, 0x51, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x00, 0x00, 0x00, 0x05, 0x41, 0x10, 0x00, 0x00, 0x00, 0x00, 0x04, 0x41, 0x10, 0x00, 0x00, 0x10, 0x55, 0x05, 0x41, 0x10, 0x54, 0x00, 0x55, 0x45, 0x10, 0x11, 0x11, 0x01, 0x40, 0x55, 0x54, 0x10, 0x11, 0x11, 0x00, 0x10, 0x55, 0x54, 0x15, 0x51, 0x11, 0x41, 0x11, 0x51, 0x10, 0x04, 0x41, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x50, 0x50, 0x00, 0x00, 0x10, 0x01, 0x10, 0x55, 0x50, 0x55, 0x00, 0x55, 0x01, 0x10, 0x44, 0x51, 0x00, 0x51, 0x00, 0x41, 0x10, 0x40, 0x11, 0x04, 0x41, 0x11, 0x41, 0x10, 0x15, 0x41, 0x00, 0x41, 0x00, 0x41, 0x10, 0x10, 0x41, 0x00, 0x40, 0x41, 0x01, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x55, 0x55, 0x55, 0x55, 0x55, 0x41, 0x10, 0x40, 0x00, 0x00, 0x00, 0x00, 0x41, 0x10, 0x55, 0x55, 0x55, 0x55, 0x55, 0x41, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x15, 0x50, 0x00, 0x00, 0x00, 0x01, 0x55, 0x12, 0x0c, 0x57, 0xf5, 0x7d, 0x55, 0x50, 0x5f, 0xfd, 0xff, 0x55, 0x50, 0x5f, 0xff, 0xff, 0x55, 0x50, 0x5f, 0xff, 0xff, 0xd5, 0x50, 0x7c, 0x00, 0x00, 0xd5, 0x50, 0x70, 0x0f, 0xc3, 0xd5, 0x50, 0x70, 0x33, 0xc3, 0xd5, 0x50, 0x70, 0x33, 0xc3, 0xd5, 0x50, 0x70, 0x0f, 0xc3, 0xd5, 0x50, 0x5c, 0x00, 0x0f, 0x55, 0x50, 0x57, 0xff, 0xfd, 0x55, 0x50, 0x5c, 0x3c, 0x33, 0x55, 0x50, 0x12, 0x0c, 0x55, 0xfd, 0x5f, 0x55, 0x50, 0x57, 0xff, 0x7f, 0xd5, 0x50, 0x57, 0xff, 0xff, 0xd5, 0x50, 0x57, 0xff, 0xff, 0xf5, 0x50, 0x5f, 0x00, 0x00, 0x35, 0x50, 0x5c, 0x03, 0xc0, 0x35, 0x50, 0x5c, 0x0c, 0x30, 0xf5, 0x50, 0x5c, 0x00, 0x00, 0x35, 0x50, 0x5c, 0x0c, 0x0f, 0xf5, 0x50, 0x57, 0x33, 0x0f, 0xd5, 0x50, 0x55, 0xf3, 0xff, 0x35, 0x50, 0x55, 0xc3, 0xc3, 0xf5, 0x50, 0x12, 0x0c, 0x5f, 0xd5, 0x7f, 0xff, 0xf0, 0x7f, 0xf5, 0xff, 0x00, 0x30, 0x7f, 0xff, 0xff, 0x00, 0x30, 0x7f, 0xff, 0xff, 0x00, 0x30, 0x70, 0x00, 0x03, 0x00, 0x30, 0xc3, 0xf0, 0x3f, 0x00, 0x30, 0xcc, 0xf0, 0xcf, 0x00, 0x30, 0xcc, 0xf0, 0xcf, 0x00, 0x30, 0xc3, 0xf0, 0x3f, 0xff, 0xf0, 0x70, 0x0f, 0x00, 0xcd, 0x50, 0x5f, 0xff, 0xff, 0x35, 0x50, 0x70, 0x30, 0x3c, 0xd5, 0x50, 0x12, 0x0c, 0x55, 0xfd, 0x57, 0xd5, 0x50, 0x57, 0xff, 0xdf, 0xf5, 0x50, 0x57, 0xff, 0xff, 0xfd, 0x50, 0x55, 0xff, 0xff, 0xfd, 0x50, 0x57, 0xc0, 0x00, 0x0d, 0x50, 0x57, 0x00, 0x00, 0x0d, 0x50, 0x57, 0x00, 0x00, 0x0d, 0x50, 0x57, 0x0f, 0xf0, 0x0d, 0x50, 0x57, 0x00, 0x00, 0xcd, 0x50, 0x55, 0xc0, 0x03, 0x35, 0x50, 0x55, 0x7f, 0xff, 0xd5, 0x50, 0x55, 0xc3, 0xc3, 0xd5, 0x50, 0x12, 0x0c, 0x57, 0xf5, 0x5f, 0xd5, 0x50, 0x5f, 0xfd, 0x7f, 0xf5, 0x50, 0x5f, 0xff, 0xff, 0xf5, 0x50, 0x5f, 0xff, 0xff, 0xf5, 0x50, 0x5c, 0x00, 0x00, 0x35, 0x50, 0x70, 0x00, 0x00, 0x0d, 0x50, 0x70, 0x30, 0x0c, 0x0d, 0x50, 0x70, 0xc0, 0x03, 0x0d, 0x50, 0x70, 0x03, 0xc0, 0x0d, 0x50, 0x5c, 0x0f, 0xf0, 0x35, 0x50, 0x57, 0xff, 0xff, 0xd5, 0x50, 0x55, 0xcc, 0x33, 0x55, 0x50, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfa, 0xaa, 0xab, 0xc0, 0xff, 0xe5, 0x55, 0x5a, 0xc0, 0xff, 0xe5, 0x55, 0x5a, 0xc0, 0xff, 0x95, 0x55, 0x66, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0xaa, 0xaa, 0xab, 0xc0, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfe, 0xaa, 0xaa, 0xc0, 0xff, 0xfe, 0x55, 0x56, 0xc0, 0xff, 0xfe, 0x55, 0x56, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xea, 0xaa, 0xaa, 0xc0, 0xff, 0xea, 0xaa, 0xaa, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0xaa, 0xaa, 0xab, 0xc0, 0x08, 0x08, 0x7f, 0xf5, 0xff, 0xfd, 0xc3, 0x0d, 0xff, 0xfd, 0xff, 0xfd, 0xfc, 0xfd, 0x7f, 0xf5, 0x77, 0x75, 0x10, 0x03, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xc0, 0x03, 0x03, 0xff, 0xff, 0xff, 0xff, 0x10, 0x03, 0x55, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x03, 0x55, 0x55, 0xff, 0xff, 0x55, 0x08, 0x08, 0x55, 0x75, 0x55, 0x75, 0x55, 0x75, 0x5f, 0x75, 0x70, 0xf5, 0x70, 0xd5, 0x5f, 0x55, 0x55, 0x55, 0x08, 0x08, 0x55, 0x75, 0x55, 0x75, 0x55, 0x75, 0x5f, 0x75, 0x7f, 0xf5, 0x7f, 0xd5, 0x5f, 0x55, 0x55, 0x55, 0x08, 0x08, 0x55, 0xd5, 0x55, 0xf5, 0x55, 0xfd, 0x7d, 0xdd, 0xff, 0xd5, 0xff, 0x55, 0x7d, 0x55, 0x55, 0x55, 0x08, 0x08, 0x5f, 0xfd, 0x5d, 0x5d, 0x5d, 0x5d, 0x5d, 0x5d, 0xfd, 0xfd, 0xfd, 0xfd, 0xf5, 0xf5, 0x55, 0x55, 0x01, 0x01, 0x00, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x7f, 0xfd, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x5f, 0xfd, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x7f, 0xfd, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x5f, 0xfd, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x7f, 0xfd, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0x03, 0x5f, 0xfd, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x08, 0x08, 0x50, 0x05, 0x43, 0xc1, 0x00, 0x00, 0x30, 0xcc, 0x33, 0x0c, 0x00, 0x00, 0x43, 0xc1, 0x50, 0x05, 0x08, 0x08, 0xc0, 0x03, 0x33, 0xcc, 0x00, 0x30, 0x33, 0x0c, 0x30, 0xcc, 0x0c, 0x00, 0x33, 0xcc, 0xc0, 0x03, 0x08, 0x08, 0x57, 0xd5, 0x5c, 0x35, 0x5c, 0x35, 0xdc, 0x37, 0xd7, 0xd7, 0xdf, 0xf7, 0xfd, 0x7f, 0xf7, 0xdf, 0x04, 0x1f, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x02, 0x05, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0x06, 0x20, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0x20, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf7, 0xff, 0x5f, 0x5f, 0xd7, 0xff, 0x75, 0x5d, 0x55, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x57, 0xd5, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x55, 0x75, 0x75, 0x7f, 0xdf, 0xd5, 0x75, 0x75, 0x55, 0x75, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x55, 0x5f, 0xd5, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x08, 0x7f, 0x5f, 0x57, 0xd7, 0x57, 0xd5, 0x75, 0xdd, 0x77, 0x57, 0xdf, 0x75, 0xdd, 0x77, 0x57, 0xd7, 0x75, 0xdf, 0xf7, 0x55, 0x7d, 0x5f, 0x5d, 0x77, 0xf7, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x0c, 0x7f, 0x5f, 0x5d, 0x5d, 0xfd, 0xd5, 0x75, 0xdf, 0x7d, 0xd5, 0xdf, 0x75, 0xdf, 0xfd, 0xfd, 0xd7, 0x7f, 0xdd, 0xdd, 0xd5, 0x7f, 0x75, 0xdd, 0x5d, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7d, 0x75, 0x77, 0xf7, 0xf5, 0xd7, 0x75, 0x77, 0x57, 0x5d, 0xd7, 0x5d, 0xd7, 0xf7, 0x5d, 0xd7, 0x5d, 0xd7, 0x57, 0xf5, 0x7d, 0x57, 0x57, 0xf7, 0x5d, 0x55, 0x55, 0x55, 0x55, 0x55, 0x20, 0x0c, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xff, 0x55, 0xc3, 0x7d, 0x55, 0x55, 0x55, 0x70, 0x00, 0xd5, 0x70, 0xff, 0x55, 0x55, 0x55, 0xc0, 0x00, 0x35, 0x7c, 0x3f, 0xd5, 0x55, 0x57, 0x00, 0x03, 0x0d, 0x5f, 0xff, 0xff, 0xff, 0xfc, 0x03, 0x00, 0x0d, 0x70, 0x00, 0x03, 0xc0, 0x00, 0x00, 0x3f, 0xfd, 0x7f, 0xff, 0xfc, 0x30, 0x00, 0x00, 0xc0, 0x03, 0xc0, 0x00, 0x03, 0x30, 0x00, 0x03, 0x0f, 0xfc, 0xc0, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc0, 0x03, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x01, 0x01, 0x00, 0x10, 0x10, 0x55, 0x7d, 0x55, 0xf5, 0x55, 0xc3, 0x57, 0x0d, 0x55, 0xc0, 0xdc, 0x0d, 0x55, 0x70, 0xdc, 0x3d, 0x55, 0x5c, 0x30, 0x35, 0x55, 0x70, 0x00, 0xd5, 0x55, 0xc3, 0xfc, 0xd5, 0x55, 0xcf, 0xff, 0x35, 0x57, 0x0f, 0xff, 0x35, 0x57, 0x00, 0xfc, 0x35, 0x57, 0xc0 };\r\n\r\n\r\nvoid EXTI0_IRQHandler() {\r\n\r\n\t//GPIO_SetBits(GPIOB, GPIO_Pin_14);\r\n //if (EXTI_GetITStatus(EXTI_Line0) != RESET) {\r\n if(started){\r\n \tif(read){\r\n\r\n \t\tread = 2;\r\n \t}\r\n \tread = 1;\r\n \t//GPIO_SetBits(GPIOB, GPIO_Pin_14);\r\n \ta = 0;\r\n \tacount = 0;\r\n //\tas[loops++] = a;\r\n \t//as[loops++] = acount;\r\n \tas[loops++] = hit;\r\n \thit = 0;\r\n\r\n\r\n }\r\n EXTI_ClearITPendingBit(EXTI_Line0);\r\n //}\r\n\t//GPIO_ResetBits(GPIOB, GPIO_Pin_14);\r\n}\r\n\r\nvoid EXTI1_IRQHandler() {\r\n\t//hit++;\r\n\t//if (EXTI_GetITStatus(EXTI_Line1) != RESET) {\r\n\r\n \tif(read){\r\n\r\n \t//\ta = a << 1;\r\n \t//\tGPIO_SetBits(GPIOB, GPIO_Pin_15);\r\n \t\t// a = a | (GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_8));\r\n\r\n \t\t(GPIOD->IDR & GPIO_Pin_8) ? (a = ((a << 1)|1) ) : (a <<= 1);\r\n\r\n \t\t//GPIO_ResetBits(GPIOB, GPIO_Pin_15);\r\n \t\tacount++;\r\n\t\t//\t if(acount > 32){\r\n\r\n\t\t\t//\t\t GPIO_SetBits(GPIOD, GPIO_Pin_15);\r\n\t\t\t\t// }\r\n\r\n \t\tif (acount ==32){\r\n \t\t\tread = 0;\r\n\r\n \t\t\t //if((a & 0xff000000) != 0x03000000){\r\n\r\n \t\t\t\t//\t GPIO_SetBits(GPIOD, GPIO_Pin_14);\r\n \t\t\t\t// }\r\n\r\n \t\t\tas[loops++] = a;\r\n\r\n \t\t\t a = 0xffffff & a;\r\n\r\n \t\t\t// index = (loops % 800) / 100;\r\n \t\t\t if(loops > 100){\r\n \t\t\t\t loops = 0;\r\n \t\t\t\t index++;\r\n \t\t\t\t if (index > 7)\r\n \t\t\t\t\t index = 0;\r\n \t\t\t }\r\n \t\t\tfor(i = 0; i < 105; i++){\r\n\r\n \t\t\t\tv[0xe0 + i] = vs[index][i];\r\n \t\t\t}\r\n\r\n\r\n \t\t\tval = v[a++];\r\n\r\n \t\t//\tas[loops++] = val;\r\n \t\t//\tas[loops++] = val;\r\n \t\t\tc = 0x80;\r\n \t\t\tif(val&c){\r\n \t\t\t\t\t\t GPIO_SetBits(GPIOD, GPIO_Pin_4);\r\n \t\t\t \t\t }else{\r\n \t\t\t \t\t\t GPIO_ResetBits(GPIOD, GPIO_Pin_4);\r\n\r\n \t\t\t \t\t }\r\n\r\n \t\t\t \t\t c = c >> 1;\r\n \t\t\t \t\t started = 1;\r\n \t\t}\r\n\r\n \t}else{\r\n \t\t if(val&c){\r\n \t\t\t GPIOD->BSRRL = GPIO_Pin_4;\r\n \t\t }else{\r\n \t\t\t GPIOD->BSRRH = GPIO_Pin_4;\r\n\r\n \t\t }\r\n\r\n \t\t c = c >> 1;\r\n \t\t if(c==0){\r\n \t\t\t c = 0x80;\r\n \t\t\t val = v[a++];\r\n \t\t\t // as[loops++] = val;\r\n\r\n \t\t }\r\n \t\t //as[loops++] = 2;\r\n \t}\r\n\r\n \tEXTI_ClearITPendingBit(EXTI_Line1);\r\n\r\n //}\r\n\r\n\r\n}\r\n\r\n\r\n\r\n\r\n/**\r\n * @brief Main program.\r\n * @param None\r\n * @retval None\r\n */\r\nuint32_t getAddress();\r\n\r\n\r\nint main(void)\r\n{\r\n RCC_ClocksTypeDef RCC_Clocks;\r\n\r\n int l = 0;\r\n\r\n /* Initialize LEDs and User_Button on STM32F4-Discovery --------------------*/\r\n\r\n RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE);\r\n RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE);\r\n /* SysTick end of count event each 10ms */\r\n // RCC_GetClocksFreq(&RCC_Clocks);\r\n // SysTick_Config(RCC_Clocks.HCLK_Frequency / 100);\r\n\r\n GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_8 ;\r\n GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r\n GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r\n GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;\r\n GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r\n GPIO_Init(GPIOD, &GPIO_InitStructure);\r\n\r\n GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;\r\n GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r\n GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r\n GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;\r\n GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;\r\n GPIO_Init(GPIOD, &GPIO_InitStructure);\r\n\r\n GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_13| GPIO_Pin_14| GPIO_Pin_15;\r\n GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;\r\n GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r\n GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;\r\n GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r\n GPIO_Init(GPIOD, &GPIO_InitStructure);\r\n\r\n\r\n GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14 | GPIO_Pin_15;\r\n GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;\r\n GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r\n GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;\r\n GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r\n GPIO_Init(GPIOB, &GPIO_InitStructure);\r\n\r\n\r\n EXTILine0_Config();\r\n GPIO_SetBits(GPIOD, GPIO_Pin_12);\r\n // GPIO_SetBits(GPIOD, GPIO_Pin_14);\r\n// GPIO_SetBits(GPIOD, GPIO_Pin_12);\r\n // GPIO_ResetBits(GPIOB, GPIO_Pin_14);\r\n //GPIO_SetBits(GPIOB, GPIO_Pin_14);\r\n vs[0] = v1;\r\n vs[1] = v2;\r\n vs[2] = v3;\r\n vs[3] = v2;\r\n vs[4] = v4;\r\n vs[5] = v5;\r\n vs[6] = v6;\r\n vs[7] = v7;\r\n while(1){\r\n\r\n\t// GPIO_SetBits(GPIOB, GPIO_Pin_14);\r\n\t // GPIO_ResetBits(GPIOB, GPIO_Pin_14);\r\n\r\n\t // printf(\"here\");\r\n/*\t uint32_t a, j;\r\n\t uint8_t t, c, i;\r\n\t flag = 1;\r\n\t if(started)\r\n\t \t while(GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_0)){\r\n\t \t\t l++;\r\n\t \t }\r\n\r\n\t a = getAddress();\r\n\t // if(a < 0 || a > 200){\r\n\r\n\t\t// GPIO_SetBits(GPIOD, GPIO_Pin_14);\r\n\t //}\r\n\t started = 1;\r\n\t while(flag){\r\n\t t = v[a];\r\n\t c = 0x80;\r\n\t for( i = 0; (i < 8); i++){\r\n//\tif(a > 200){\r\n\r\n\t//\tloops++;\r\n//\t}\r\n\r\n\t if(t&c){\r\n\t\t GPIO_SetBits(GPIOD, GPIO_Pin_4);\r\n\t }else{\r\n\t\t GPIO_ResetBits(GPIOD, GPIO_Pin_4);\r\n\r\n\t }\r\n\r\n\t // if(!flag)\r\n\t \t//\t\t break;\r\n\t c = c >> 1;\r\n\t// q = ;\r\n\t// while((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)== Bit_RESET) && (GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_9) == Bit_RESET)){}\r\n\t // while(GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11) && (GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_9) == Bit_RESET) ){}\r\n//\t l = 0;\r\n\t //while((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)== Bit_SET) && flag ){}\r\n\t// as[loops++] = q;\r\n\t // q = 0;\r\n\t while((!GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)) && flag ){\r\n\r\n\r\n\t }\r\n\r\n\r\n\t//\t if((l++ % 100) == 99){\r\n\t\t//\t if((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_9) != Bit_RESET))\r\n\t//\t\t\t break;\r\n//\t\t }\r\n\r\n\t // as[loops++] = q;\r\n\t \t// q = 0;\r\n\r\n\r\n\r\n\t// l = 0;\r\n\t while(GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)){\r\n\t\t //q++;\r\n\t }\r\n\r\n\t //as[loops++] = q;\r\n\r\n\t//\t\t if((l++ % 100) == 99){\r\n\t\t//\t\t\t if((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_9) != Bit_RESET))\r\n\t\t\t//\t\t\t break;\r\n\t\t\t//\t }\r\n//\r\n\t// for(j=0; j < 1000000; j++){\r\n\r\n\t // }\r\n\t // }\r\n\r\n\t // if(flag)\r\n\t\t// loop++;\r\n\r\n\t }\r\n\t a++;\r\n\t }\r\n\r\n\r\n\t // as[loops++] = a;\r\n\r\n*/\r\n\r\n}\r\n\r\n}\r\n\r\nuint32_t getAddress(){\r\n\tuint32_t a, i;\r\n\t\ta = 0;\r\n\t\t for(i = 0; i < 32; i++){\r\n\r\n\r\n\t\t while(GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)== Bit_RESET){}\r\n\t\t //a++;\r\n\t\t a = a << 1;\r\n\t\t a = a + (GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_10)? 1:0);\r\n\r\n\t\t // if(i!=31)\r\n\t\t\t while(GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)){}\r\n\t }\r\n\r\n\t\t if((a & 0xff000000) != 0x03000000){\r\n\r\n\t\t\t// GPIO_SetBits(GPIOD, GPIO_Pin_15);\r\n\t\t }\r\n\r\n\t//\t as[loops++] = a;\r\n\t\t return a & 0x00ffffff;\r\n\r\n\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n\r\n/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "demos/nsdemomain.c", "content": "/**\r\n ******************************************************************************\r\n * @file main.c\r\n * @author MCD Application Team\r\n * @version V1.0.0\r\n * @date 19-September-2011\r\n * @brief Main program body\r\n ******************************************************************************\r\n * @attention\r\n *\r\n * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r\n * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r\n * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r\n * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r\n * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r\n * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r\n *\r\n *

© COPYRIGHT 2011 STMicroelectronics

\r\n ******************************************************************************\r\n */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n//#include \"main.h\"\r\n#include \"stm32f4_discovery.h\"\r\n//#include \"stm32f4xx_it.c\"\r\nuint8_t flag;\r\n//#include \r\n/** @addtogroup STM32F4-Discovery_Demo\r\n * @{\r\n */\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n\r\n\r\n//#define CLK GPIO_Pin_11\r\n//#define ADDRESS GPIO_Pin_10\r\n//#define E GPIO_Pin_9\r\nEXTI_InitTypeDef EXTI_InitStructure;\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n\r\n\r\n//uint32_t a = 0;\r\n//int i;\r\nint started = 0;\r\n/* Private function prototypes -----------------------------------------------*/\r\n\r\nGPIO_InitTypeDef GPIO_InitStructure;\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\nvoid EXTILine0_Config(void)\r\n{\r\n\r\n GPIO_InitTypeDef GPIO_InitStructure;\r\n NVIC_InitTypeDef NVIC_InitStructure;\r\n\r\n /* Enable GPIOA clock */\r\n RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);\r\n /* Enable SYSCFG clock */\r\n RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);\r\n\r\n /* Configure PA0 pin as input floating */\r\n GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r\n GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;\r\n GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;\r\n GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;\r\n GPIO_Init(GPIOA, &GPIO_InitStructure);\r\n\r\n GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r\n GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r\n GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;\r\n GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1;\r\n GPIO_Init(GPIOA, &GPIO_InitStructure);\r\n\r\n /* Connect EXTI Line0 to PA0 pin */\r\n SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOA, EXTI_PinSource0);\r\n\r\n /* Configure EXTI Line0 */\r\n EXTI_InitStructure.EXTI_Line = EXTI_Line0;\r\n EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;\r\n EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;\r\n EXTI_InitStructure.EXTI_LineCmd = ENABLE;\r\n EXTI_Init(&EXTI_InitStructure);\r\n\r\n /* Enable and set EXTI Line0 Interrupt to the lowest priority */\r\n NVIC_InitStructure.NVIC_IRQChannel = EXTI0_IRQn;\r\n NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x01;\r\n NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x01;\r\n NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r\n NVIC_Init(&NVIC_InitStructure);\r\n\r\n SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOA, EXTI_PinSource1);\r\n\r\n /* Configure EXTI Line0 */\r\n EXTI_InitStructure.EXTI_Line = EXTI_Line1;\r\n EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;\r\n EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;\r\n EXTI_InitStructure.EXTI_LineCmd = ENABLE;\r\n EXTI_Init(&EXTI_InitStructure);\r\n\r\n /* Enable and set EXTI Line0 Interrupt to the lowest priority */\r\n NVIC_InitStructure.NVIC_IRQChannel = EXTI1_IRQn;\r\n NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x02;\r\n NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x01;\r\n NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r\n NVIC_Init(&NVIC_InitStructure);\r\n\r\n\r\n\r\n}\r\n\r\nint loops = 0;\r\nint hit = 0;\r\nint q;\r\nint as[2000];\r\nint read = 1;\r\nuint32_t a = 0;\r\nint acount = 0;\r\nuint8_t val;\r\nuint8_t c;\r\n\r\nuint8_t v[] =\r\n{ 0x0a, 0xaa, 0x55, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0-f\r\n 0x00, 0xaa, 0x55, 0x03, 0x03, 0x03, 0x00, 0x00, 0x10, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //10-f\r\n 0x40, 0x00, 0x00, 0xc4, 0x00, 0x00, 0xdc, 0x00, 0x00, 0x0f, 0x01, 0x00, 0x91, 0x01, 0x00, 0x0d, //20\r\n 0x02, 0x00, 0x89, 0x02, 0x00, 0xd1, 0x02, 0x00, 0x1f, 0x06, 0x00, 0x67, 0x0f, 0x00, 0x67, 0x0f,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //40\r\n 0x41, 0x12, 0x00, 0xa7, 0x12, 0x00, 0x0d, 0x13, 0x00, 0x73, 0x13, 0x00, 0xd9, 0x13, 0x00, 0x3f,\r\n 0x14, 0x00, 0xa5, 0x14, 0x00, 0x0b, 0x15, 0x00, 0x71, 0x15, 0x00, 0xd7, 0x15, 0x00, 0x3d, 0x16,\r\n 0x00, 0xa3, 0x16, 0x00, 0x09, 0x17, 0x00, 0x6f, 0x17, 0x00, 0xd5, 0x17, 0x00, 0x3b, 0x18, 0x00,\r\n 0xa1, 0x18, 0x00, 0x07, 0x19, 0x00, 0x6d, 0x19, 0x00, 0xd3, 0x19, 0x00, 0x39, 0x1a, 0x00, 0x9f, //80\r\n 0x1a, 0x00, 0x05, 0x1b, 0x00, 0x6b, 0x1b, 0x00, 0xd1, 0x1b, 0x00, 0x37, 0x1c, 0x00, 0x9d, 0x1c, //90\r\n 0x00, 0x13, 0x1e, 0x00, 0x89, 0x1f, 0x00, 0xff, 0x20, 0x00, 0x75, 0x22, 0x00, 0xeb, 0x23, 0x00,\r\n 0x61, 0x25, 0x00, 0xd7, 0x26, 0x00, 0x4d, 0x28, 0x00, 0xeb, 0x28, 0x00, 0x89, 0x29, 0x00, 0x64, //b0\r\n 0x2a, 0x00, 0xa2, 0x2a, 0x00, 0xe0, 0x2a, 0x00, 0x1e, 0x2b, 0x00, 0x5c, 0x2b, 0x00, 0xce, 0x00, //c0\r\n 0x00, 0xce, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x44, 0x12, 0x34, 0x11, 0x15, //d0\r\n 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xaa, 0xa, 0xa0, 0x0, 0x0, 0x2a, 0x81, 0x80, 0x0, 0x0, 0x1a, 0x91, 0x80, 0x0, 0x0, 0x15, 0xa5, 0x80, 0x0, 0x0, 0x14, 0xa9, 0x80, 0x0, 0x0, 0x14, 0x2a, 0x80, 0x0, 0x0, 0x28, 0xa, 0x80, 0x0, 0x0, 0xaa, 0x2, 0x80, 0x0, 0x0, 0x0, 0x0, 0xa, 0xa9, 0x0, 0x0, 0x0, 0x1a, 0x19, 0x0, 0x0, 0x0, 0x2a, 0x9, 0x0, 0x0, 0x0, 0x1a, 0xa4, 0x0, 0x0, 0x0, 0x2, 0xa9, 0x0, 0x0, 0x0, 0x24, 0x2a, 0x0, 0x0, 0x0, 0x28, 0x29, 0x0, 0x0, 0x0, 0x2a, 0xa8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,\r\n\r\n\r\n\r\n // 0x0, 0xcf, 0xff, 0x0, 0x0, 0x0, 0x0, 0xcf, 0xff, 0x0, 0x0, 0x0, 0x0,\r\n // 0xcf, 0xff, 0x0, 0x0, 0xc, 0xff, 0xff, 0xff, 0x0, 0x0, 0xff, 0xff,\r\n // 0xff, 0xff, 0x0, 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n //0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n // 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n // 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0x0, 0x0, 0x0, 0x0, 0xC0, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF,\r\n 0x00, 0x00, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF,\r\n 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFA, 0xAA,\r\n 0xAB, 0xC0, 0xFF, 0xE5, 0x55, 0x5A, 0xC0, 0x00, 0xE5, 0x55, 0x5A, 0xC0, 0xFF, 0x95, 0x55, 0x66,\r\n 0xC0, 0xFF, 0xAA, 0xAA, 0xA6, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x8A, 0x28, 0x26, 0xC0,\r\n 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x8A, 0x28, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF,\r\n 0x80, 0x00, 0x26, 0xC0, 0xFF, 0xAA, 0xAA, 0xAB, 0xC0, 0x11, 0x15, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0,\r\n\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0x00, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF,\r\n 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFA, 0xAA, 0xAB, 0xC0, 0xFF, 0xE5, 0x55,\r\n 0x5A, 0xC0, 0xFF, 0xE5, 0x55, 0x5A, 0xC0, 0xFF, 0x95, 0x55, 0x66, 0xC0, 0xFF, 0xAA, 0xAA, 0xA6,\r\n 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x8A, 0x28, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0,\r\n 0xFF, 0x8A, 0x28, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF,\r\n 0xAA, 0xAA, 0xAB, 0xC0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};// 0x70, 0x2c, 0x00, 0x82, 0x2c, 0x00, 0x90, 0x2c, 0x00, 0x9e, 0x2c, 0x00, 0xb0, 0x2c, 0x00, 0xc2, 0x2c, 0x00, 0xd4, 0x2c, 0x00, 0xe6, 0x2c, 0x00, 0xe9, 0x2c, 0x00, 0x1b, 0x2d, 0x00, 0x4d, 0x2d, 0x00, 0x7f, 0x2d, 0x00, 0xb1, 0x2d, 0x00, 0xe3, 0x2d, 0x00, 0x15, 0x2e, 0x00, 0x27, 0x2e, 0x00, 0x39, 0x2e, 0x00, 0x4b, 0x2e, 0x00, 0x6c, 0x2e, 0x00, 0x73, 0x2e, 0x00, 0xb5, 0x2e, 0x00, 0xf7, 0x2e, 0x00, 0x21, 0x2f, 0x00, 0x5f, 0x2f, 0x00, 0xc1, 0x2f, 0x00, 0x02, 0x00, 0x06, 0x03, 0x04, 0x09, 0x0a, 0x05, 0x08, 0x07, 0x00, 0x00, 0x58, 0x00, 0x00, 0x32, 0x00, 0x00, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x10, 0x00, 0x00, 0x08, 0x00, 0x00, 0x50, 0x04, 0x00, 0x30, 0x02, 0x00, 0x20, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00, 0x50, 0x08, 0x00, 0x50, 0x11, 0x00, 0x00, 0x00, 0x28, 0x00, 0x40, 0x15, 0x00, 0x60, 0x12, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x45, 0x00, 0x00, 0x35, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x22, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00, 0x22, 0x00, 0x00, 0x13, 0x00, 0x01, 0x00, 0x02, 0x00, 0x50, 0x01, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x04, 0xff, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x02, 0xff, 0x01, 0x01, 0x00, 0x1e, 0x01, 0x00, 0x03, 0xff, 0x01, 0x01, 0x00, 0x2d, 0x01, 0x00, 0x04, 0xfe, 0x01, 0x01, 0x00, 0x3c, 0x01, 0x00, 0x05, 0xfe, 0x01, 0x01, 0x00, 0x4b, 0x02, 0x00, 0x06, 0xfe, 0x02, 0x02, 0x00, 0x5a, 0x02, 0x00, 0x07, 0xfd, 0x02, 0x02, 0x00, 0x63, 0x02, 0x00, 0x08, 0xfd, 0x02, 0x02, 0x00, 0x64, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0x00, 0x02, 0x04, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x02, 0xff, 0x01, 0x01, 0x00, 0x0f, 0x01, 0x00, 0x03, 0xff, 0x01, 0x01, 0x00, 0x19, 0x01, 0x00, 0x04, 0xfe, 0x01, 0x01, 0x00, 0x23, 0x01, 0x00, 0x05, 0xfe, 0x01, 0x02, 0x00, 0x2d, 0x02, 0x00, 0x06, 0xfe, 0x02, 0x02, 0x00, 0x37, 0x02, 0x00, 0x07, 0xfd, 0x02, 0x02, 0x00, 0x40, 0x02, 0x00, 0x08, 0xfd, 0x02, 0x02, 0x00, 0x41, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xc4, 0x2f, 0x00, 0xff, 0xff, 0xff, 0x06, 0x30, 0x00, 0x48, 0x30, 0x00, 0x8a, 0x30, 0x00, 0xcc, 0x30, 0x00, 0x0e, 0x31, 0x00, 0x50, 0x31, 0x00, 0x92, 0x31, 0x00, 0xd4, 0x31, 0x00, 0x16, 0x32, 0x00, 0xff, 0xff, 0xff, 0x58, 0x32, 0x00, 0xff, 0xff, 0xff, 0xba, 0x32, 0x00, 0x1c, 0x33, 0x00, 0x7e, 0x33, 0x00, 0xe0, 0x33, 0x00, 0x42, 0x34, 0x00, 0xa4, 0x34, 0x00, 0x06, 0x35, 0x00, 0x68, 0x35, 0x00, 0xca, 0x35, 0x00, 0xff, 0xff, 0xff, 0x2c, 0x36, 0x00, 0x3e, 0x36, 0x00, 0x80, 0x36, 0x00, 0xc2, 0x36, 0x00, 0x04, 0x37, 0x00, 0x46, 0x37, 0x00, 0x88, 0x37, 0x00, 0xca, 0x37, 0x00, 0x24, 0x38, 0x00, 0x9d, 0x38, 0x00, 0xf9, 0x38, 0x00, 0x7d, 0x39, 0x00, 0xd7, 0x39, 0x00, 0x50, 0x3a, 0x00, 0xac, 0x3a, 0x00, 0x30, 0x3b, 0x00, 0x72, 0x3b, 0x00, 0xb4, 0x3b, 0x00, 0xf6, 0x3b, 0x00, 0x38, 0x3c, 0x00, 0x7a, 0x3c, 0x00, 0xbc, 0x3c, 0x00, 0xfe, 0x3c, 0x00, 0x40, 0x3d, 0x00, 0x3a, 0x3e, 0x00, 0x34, 0x3f, 0x00, 0x2e, 0x40, 0x00, 0x28, 0x41, 0x00, 0x22, 0x42, 0x00, 0x98, 0x43, 0x00, 0xea, 0x43, 0x00, 0x3c, 0x44, 0x00, 0x8e, 0x44, 0x00, 0xe0, 0x44, 0x00, 0x32, 0x45, 0x00, 0x84, 0x45, 0x00, 0x7e, 0x46, 0x00, 0x78, 0x47, 0x00, 0xba, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0x76, 0x48, 0x00, 0xf0, 0x48, 0x00, 0x6a, 0x49, 0x00, 0xe4, 0x49, 0x00, 0x5e, 0x4a, 0x00, 0xd8, 0x4a, 0x00, 0x52, 0x4b, 0x00, 0xcc, 0x4b, 0x00, 0x46, 0x4c, 0x00, 0xc0, 0x4c, 0x00, 0x3a, 0x4d, 0x00, 0xb4, 0x4d, 0x00, 0x2e, 0x4e, 0x00, 0xa8, 0x4e, 0x00, 0x22, 0x4f, 0x00, 0x9c, 0x4f, 0x00, 0x16, 0x50, 0x00, 0x90, 0x50, 0x00, 0x0a, 0x51, 0x00, 0x84, 0x51, 0x00, 0xfe, 0x51, 0x00, 0x78, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0x6c, 0x53, 0x00, 0xe6, 0x53, 0x00, 0x60, 0x54, 0x00, 0xda, 0x54, 0x00, 0x54, 0x55, 0x00, 0xce, 0x55, 0x00, 0x48, 0x56, 0x00, 0xc2, 0x56, 0x00, 0x3c, 0x57, 0x00, 0xb6, 0x57, 0x00, 0x30, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0x24, 0x59, 0x00, 0x9e, 0x59, 0x00, 0x18, 0x5a, 0x00, 0x92, 0x5a, 0x00, 0x0c, 0x5b, 0x00, 0x86, 0x5b, 0x00, 0x00, 0x5c, 0x00, 0x7a, 0x5c, 0x00, 0xf4, 0x5c, 0x00, 0x6e, 0x5d, 0x00, 0xe8, 0x5d, 0x00, 0x62, 0x5e, 0x00, 0xdc, 0x5e, 0x00, 0x56, 0x5f, 0x00, 0xd0, 0x5f, 0x00, 0x4a, 0x60, 0x00, 0xc4, 0x60, 0x00, 0x3e, 0x61, 0x00, 0xb8, 0x61, 0x00, 0x32, 0x62, 0x00, 0xac, 0x62, 0x00, 0x26, 0x63, 0x00, 0xa0, 0x63, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x94, 0x64, 0x00, 0x0e, 0x65, 0x00, 0x88, 0x65, 0x00, 0x02, 0x66, 0x00, 0x7c, 0x66, 0x00, 0xf6, 0x66, 0x00, 0x70, 0x67, 0x00, 0xea, 0x67, 0x00, 0x64, 0x68, 0x00, 0xde, 0x68, 0x00, 0x58, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0x4c, 0x6a, 0x00, 0xc6, 0x6a, 0x00, 0x40, 0x6b, 0x00, 0xba, 0x6b, 0x00, 0x34, 0x6c, 0x00, 0xae, 0x6c, 0x00, 0x28, 0x6d, 0x00, 0xa2, 0x6d, 0x00, 0x1c, 0x6e, 0x00, 0x96, 0x6e, 0x00, 0x10, 0x6f, 0x00, 0x8a, 0x6f, 0x00, 0x04, 0x70, 0x00, 0x7e, 0x70, 0x00, 0xf8, 0x70, 0x00, 0x72, 0x71, 0x00, 0xec, 0x71, 0x00, 0x66, 0x72, 0x00, 0xe0, 0x72, 0x00, 0x5a, 0x73, 0x00, 0xd4, 0x73, 0x00, 0x4e, 0x74, 0x00, 0xc8, 0x74, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0xbc, 0x75, 0x00, 0x36, 0x76, 0x00, 0xb0, 0x76, 0x00, 0x2a, 0x77, 0x00, 0xa4, 0x77, 0x00, 0x1e, 0x78, 0x00, 0x98, 0x78, 0x00, 0x12, 0x79, 0x00, 0x8c, 0x79, 0x00, 0x06, 0x7a, 0x00, 0x80, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0x74, 0x7b, 0x00, 0xe2, 0x7b, 0x00, 0x50, 0x7c, 0x00, 0xbe, 0x7c, 0x00, 0x2c, 0x7d, 0x00, 0x9a, 0x7d, 0x00, 0x08, 0x7e, 0x00, 0x76, 0x7e, 0x00, 0xe4, 0x7e, 0x00, 0x52, 0x7f, 0x00, 0xc0, 0x7f, 0x00, 0x2e, 0x80, 0x00, 0x9c, 0x80, 0x00, 0x0a, 0x81, 0x00, 0x78, 0x81, 0x00, 0xe6, 0x81, 0x00, 0x54, 0x82, 0x00, 0xc2, 0x82, 0x00, 0x30, 0x83, 0x00, 0x9e, 0x83, 0x00, 0x0c, 0x84, 0x00, 0x7a, 0x84, 0x00, 0xe8, 0x84, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0xc4, 0x85, 0x00, 0x32, 0x86, 0x00, 0xa0, 0x86, 0x00, 0x0e, 0x87, 0x00, 0x7c, 0x87, 0x00, 0xea, 0x87, 0x00, 0x58, 0x88, 0x00, 0xc6, 0x88, 0x00, 0x34, 0x89, 0x00, 0xa2, 0x89, 0x00, 0x10, 0x8a, 0x00, 0x7e, 0x8a, 0x00, 0xec, 0x8a, 0x00, 0x2e, 0x8b, 0x00, 0xac, 0x8b, 0x00, 0x2a, 0x8c, 0x00, 0xa8, 0x8c, 0x00, 0x26, 0x8d, 0x00, 0xa4, 0x8d, 0x00, 0x22, 0x8e, 0x00, 0xa0, 0x8e, 0x00, 0x1e, 0x8f, 0x00, 0x60, 0x8f, 0x00, 0xa2, 0x8f, 0x00, 0xe4, 0x8f, 0x00, 0x13, 0x90, 0x00, 0x42, 0x90, 0x00, 0x65, 0x90, 0x00, 0x88, 0x90, 0x00, 0xab, 0x90, 0x00, 0xce, 0x90, 0x00, 0xf1, 0x90, 0x00, 0x57, 0x91, 0x00, 0xbd, 0x91, 0x00, 0x23, 0x92, 0x00, 0x89, 0x92, 0x00, 0xef, 0x92, 0x00, 0x55, 0x93, 0x00, 0xbb, 0x93, 0x00, 0x21, 0x94, 0x00, 0x87, 0x94, 0x00, 0xed, 0x94, 0x00, 0x53, 0x95, 0x00, 0xb9, 0x95, 0x00, 0x1f, 0x96, 0x00, 0x85, 0x96, 0x00, 0xeb, 0x96, 0x00, 0x51, 0x97, 0x00, 0xb7, 0x97, 0x00, 0x1d, 0x98, 0x00, 0x83, 0x98, 0x00, 0xe9, 0x98, 0x00, 0x4f, 0x99, 0x00, 0xb5, 0x99, 0x00, 0x1b, 0x9a, 0x00, 0x81, 0x9a, 0x00, 0xe7, 0x9a, 0x00, 0x4d, 0x9b, 0x00, 0xb3, 0x9b, 0x00, 0x19, 0x9c, 0x00, 0x7f, 0x9c, 0x00, 0xe5, 0x9c, 0x00, 0x4b, 0x9d, 0x00, 0xb1, 0x9d, 0x00, 0x17, 0x9e, 0x00, 0x7d, 0x9e, 0x00, 0xe3, 0x9e, 0x00, 0x49, 0x9f, 0x00, 0xaf, 0x9f, 0x00, 0x15, 0xa0, 0x00, 0x7b, 0xa0, 0x00, 0xe1, 0xa0, 0x00, 0x47, 0xa1, 0x00, 0xad, 0xa1, 0x00, 0x13, 0xa2, 0x00, 0x79, 0xa2, 0x00, 0xdf, 0xa2, 0x00, 0x45, 0xa3, 0x00, 0xab, 0xa3, 0x00, 0x11, 0xa4, 0x00, 0x77, 0xa4, 0x00, 0xdd, 0xa4, 0x00, 0x43, 0xa5, 0x00, 0xa9, 0xa5, 0x00, 0x0f, 0xa6, 0x00, 0x75, 0xa6, 0x00, 0xdb, 0xa6, 0x00, 0x41, 0xa7, 0x00, 0xa7, 0xa7, 0x00, 0x0d, 0xa8, 0x00, 0x73, 0xa8, 0x00, 0xd9, 0xa8, 0x00, 0x3f, 0xa9, 0x00, 0xa5, 0xa9, 0x00, 0x0b, 0xaa, 0x00, 0x71, 0xaa, 0x00, 0xd7, 0xaa, 0x00, 0x3d, 0xab, 0x00, 0xa3, 0xab, 0x00, 0x09, 0xac, 0x00, 0x6f, 0xac, 0x00, 0xd5, 0xac, 0x00, 0x3b, 0xad, 0x00, 0xa1, 0xad, 0x00, 0x07, 0xae, 0x00, 0x6d, 0xae, 0x00, 0xd3, 0xae, 0x00, 0x39, 0xaf, 0x00, 0x9f, 0xaf, 0x00, 0x05, 0xb0, 0x00, 0x6b, 0xb0, 0x00, 0xd1, 0xb0, 0x00, 0x37, 0xb1, 0x00, 0x9d, 0xb1, 0x00, 0x03, 0xb2, 0x00, 0x69, 0xb2, 0x00, 0xcf, 0xb2, 0x00, 0x35, 0xb3, 0x00, 0x9b, 0xb3, 0x00, 0x01, 0xb4, 0x00, 0x67, 0xb4, 0x00, 0xcd, 0xb4, 0x00, 0x33, 0xb5, 0x00, 0x99, 0xb5, 0x00, 0xff, 0xb5, 0x00, 0x65, 0xb6, 0x00, 0xcb, 0xb6, 0x00, 0x31, 0xb7, 0x00, 0x97, 0xb7, 0x00, 0xfd, 0xb7, 0x00, 0x63, 0xb8, 0x00, 0xc9, 0xb8, 0x00, 0x2f, 0xb9, 0x00, 0x95, 0xb9, 0x00, 0xfb, 0xb9, 0x00, 0x61, 0xba, 0x00, 0xc7, 0xba, 0x00, 0x2d, 0xbb, 0x00, 0x93, 0xbb, 0x00, 0xf9, 0xbb, 0x00, 0x5f, 0xbc, 0x00, 0xc5, 0xbc, 0x00, 0x2b, 0xbd, 0x00, 0x91, 0xbd, 0x00, 0xf7, 0xbd, 0x00, 0x5d, 0xbe, 0x00, 0xc3, 0xbe, 0x00, 0x29, 0xbf, 0x00, 0x8f, 0xbf, 0x00, 0xf5, 0xbf, 0x00, 0x5b, 0xc0, 0x00, 0xc1, 0xc0, 0x00, 0x27, 0xc1, 0x00, 0x8d, 0xc1, 0x00, 0xf3, 0xc1, 0x00, 0x59, 0xc2, 0x00, 0xbf, 0xc2, 0x00, 0x25, 0xc3, 0x00, 0x8b, 0xc3, 0x00, 0xf1, 0xc3, 0x00, 0x57, 0xc4, 0x00, 0xbd, 0xc4, 0x00, 0x23, 0xc5, 0x00, 0x89, 0xc5, 0x00, 0xef, 0xc5, 0x00, 0x55, 0xc6, 0x00, 0xbb, 0xc6, 0x00, 0x21, 0xc7, 0x00, 0x87, 0xc7, 0x00, 0xed, 0xc7, 0x00, 0x53, 0xc8, 0x00, 0xb9, 0xc8, 0x00, 0x1f, 0xc9, 0x00, 0x85, 0xc9, 0x00, 0xeb, 0xc9, 0x00, 0x51, 0xca, 0x00, 0xb7, 0xca, 0x00, 0x1d, 0xcb, 0x00, 0x83, 0xcb, 0x00, 0xe9, 0xcb, 0x00, 0x4f, 0xcc, 0x00, 0xb5, 0xcc, 0x00, 0x1b, 0xcd, 0x00, 0x81, 0xcd, 0x00, 0xe7, 0xcd, 0x00, 0x4d, 0xce, 0x00, 0xb3, 0xce, 0x00, 0x19, 0xcf, 0x00, 0x7f, 0xcf, 0x00, 0xe5, 0xcf, 0x00, 0x4b, 0xd0, 0x00, 0xb1, 0xd0, 0x00, 0x17, 0xd1, 0x00, 0x7d, 0xd1, 0x00, 0xe3, 0xd1, 0x00, 0x49, 0xd2, 0x00, 0xaf, 0xd2, 0x00, 0x15, 0xd3, 0x00, 0x7b, 0xd3, 0x00, 0xe1, 0xd3, 0x00, 0x47, 0xd4, 0x00, 0xad, 0xd4, 0x00, 0x13, 0xd5, 0x00, 0x79, 0xd5, 0x00, 0xdf, 0xd5, 0x00, 0x45, 0xd6, 0x00, 0xab, 0xd6, 0x00, 0x11, 0xd7, 0x00, 0x77, 0xd7, 0x00, 0xdd, 0xd7, 0x00, 0x43, 0xd8, 0x00, 0xa9, 0xd8, 0x00, 0x0f, 0xd9, 0x00, 0x75, 0xd9, 0x00, 0xdb, 0xd9, 0x00, 0x41, 0xda, 0x00, 0xa7, 0xda, 0x00, 0x0d, 0xdb, 0x00, 0x73, 0xdb, 0x00, 0xd9, 0xdb, 0x00, 0x3f, 0xdc, 0x00, 0xa5, 0xdc, 0x00, 0x0b, 0xdd, 0x00, 0x71, 0xdd, 0x00, 0xd7, 0xdd, 0x00, 0x3d, 0xde, 0x00, 0xa3, 0xde, 0x00, 0x09, 0xdf, 0x00, 0x6f, 0xdf, 0x00, 0xd5, 0xdf, 0x00, 0x3b, 0xe0, 0x00, 0xa1, 0xe0, 0x00, 0x07, 0xe1, 0x00, 0x6d, 0xe1, 0x00, 0xd3, 0xe1, 0x00, 0x39, 0xe2, 0x00, 0x9f, 0xe2, 0x00, 0x05, 0xe3, 0x00, 0x6b, 0xe3, 0x00, 0xd1, 0xe3, 0x00, 0x37, 0xe4, 0x00, 0x9d, 0xe4, 0x00, 0x03, 0xe5, 0x00, 0x69, 0xe5, 0x00, 0xcf, 0xe5, 0x00, 0x35, 0xe6, 0x00, 0x9b, 0xe6, 0x00, 0x01, 0xe7, 0x00, 0x67, 0xe7, 0x00, 0xcd, 0xe7, 0x00, 0x33, 0xe8, 0x00, 0x99, 0xe8, 0x00, 0xff, 0xe8, 0x00, 0x65, 0xe9, 0x00, 0xcb, 0xe9, 0x00, 0x31, 0xea, 0x00, 0x97, 0xea, 0x00, 0xfd, 0xea, 0x00, 0x63, 0xeb, 0x00, 0xc9, 0xeb, 0x00, 0x2f, 0xec, 0x00, 0x95, 0xec, 0x00, 0xfb, 0xec, 0x00, 0x61, 0xed, 0x00, 0xc7, 0xed, 0x00, 0x2d, 0xee, 0x00, 0x93, 0xee, 0x00, 0xf9, 0xee, 0x00, 0x5f, 0xef, 0x00, 0xc5, 0xef, 0x00, 0x2b, 0xf0, 0x00, 0x91, 0xf0, 0x00, 0xf7, 0xf0, 0x00, 0x5d, 0xf1, 0x00, 0xc3, 0xf1, 0x00, 0x29, 0xf2, 0x00, 0x8f, 0xf2, 0x00, 0xf5, 0xf2, 0x00, 0x5b, 0xf3, 0x00, 0xc1, 0xf3, 0x00, 0x27, 0xf4, 0x00, 0x8d, 0xf4, 0x00, 0xf3, 0xf4, 0x00, 0x59, 0xf5, 0x00, 0xbf, 0xf5, 0x00, 0x25, 0xf6, 0x00, 0x8b, 0xf6, 0x00, 0xf1, 0xf6, 0x00, 0x57, 0xf7, 0x00, 0xbd, 0xf7, 0x00, 0x23, 0xf8, 0x00, 0x89, 0xf8, 0x00, 0xef, 0xf8, 0x00, 0x55, 0xf9, 0x00, 0xbb, 0xf9, 0x00, 0x21, 0xfa, 0x00, 0x87, 0xfa, 0x00, 0xed, 0xfa, 0x00, 0x53, 0xfb, 0x00, 0xb9, 0xfb, 0x00, 0x1f, 0xfc, 0x00, 0x85, 0xfc, 0x00, 0xeb, 0xfc, 0x00, 0x51, 0xfd, 0x00, 0xb7, 0xfd, 0x00, 0x1d, 0xfe, 0x00, 0x83, 0xfe, 0x00, 0xe9, 0xfe, 0x00, 0x4f, 0xff, 0x00, 0xb5, 0xff, 0x00, 0x1b, 0x00, 0x01, 0x81, 0x00, 0x01, 0xe7, 0x00, 0x01, 0x4d, 0x01, 0x01, 0xb3, 0x01, 0x01, 0x19, 0x02, 0x01, 0x7f, 0x02, 0x01, 0xe5, 0x02, 0x01, 0x4b, 0x03, 0x01, 0xb1, 0x03, 0x01, 0x17, 0x04, 0x01, 0x7d, 0x04, 0x01, 0xe3, 0x04, 0x01, 0x49, 0x05, 0x01, 0xaf, 0x05, 0x01, 0x15, 0x06, 0x01, 0x7b, 0x06, 0x01, 0xe1, 0x06, 0x01, 0x47, 0x07, 0x01, 0xad, 0x07, 0x01, 0x13, 0x08, 0x01, 0x79, 0x08, 0x01, 0xdf, 0x08, 0x01, 0x45, 0x09, 0x01, 0xab, 0x09, 0x01, 0x11, 0x0a, 0x01, 0x77, 0x0a, 0x01, 0xdd, 0x0a, 0x01, 0x43, 0x0b, 0x01, 0xa9, 0x0b, 0x01, 0x0f, 0x0c, 0x01, 0x75, 0x0c, 0x01, 0xdb, 0x0c, 0x01, 0x41, 0x0d, 0x01, 0xa7, 0x0d, 0x01, 0x0d, 0x0e, 0x01, 0x73, 0x0e, 0x01, 0xd9, 0x0e, 0x01, 0x3f, 0x0f, 0x01, 0xa5, 0x0f, 0x01, 0x0b, 0x10, 0x01, 0x71, 0x10, 0x01, 0xd7, 0x10, 0x01, 0x3d, 0x11, 0x01, 0xa3, 0x11, 0x01, 0x09, 0x12, 0x01, 0x6f, 0x12, 0x01, 0xd5, 0x12, 0x01, 0x3b, 0x13, 0x01, 0xa1, 0x13, 0x01, 0x07, 0x14, 0x01, 0x6d, 0x14, 0x01, 0xd3, 0x14, 0x01, 0x39, 0x15, 0x01, 0x9f, 0x15, 0x01, 0x05, 0x16, 0x01, 0x6b, 0x16, 0x01, 0xd1, 0x16, 0x01, 0x37, 0x17, 0x01, 0x9d, 0x17, 0x01, 0x03, 0x18, 0x01, 0x69, 0x18, 0x01, 0xcf, 0x18, 0x01, 0x35, 0x19, 0x01, 0x9b, 0x19, 0x01, 0x01, 0x1a, 0x01, 0x67, 0x1a, 0x01, 0xcd, 0x1a, 0x01, 0x33, 0x1b, 0x01, 0x99, 0x1b, 0x01, 0xff, 0x1b, 0x01, 0x65, 0x1c, 0x01, 0xcb, 0x1c, 0x01, 0x31, 0x1d, 0x01, 0x97, 0x1d, 0x01, 0xfd, 0x1d, 0x01, 0x63, 0x1e, 0x01, 0xc9, 0x1e, 0x01, 0x2f, 0x1f, 0x01, 0x95, 0x1f, 0x01, 0xfb, 0x1f, 0x01, 0x61, 0x20, 0x01, 0xc7, 0x20, 0x01, 0x2d, 0x21, 0x01, 0x93, 0x21, 0x01, 0xf9, 0x21, 0x01, 0x5f, 0x22, 0x01, 0xc5, 0x22, 0x01, 0x2b, 0x23, 0x01, 0x91, 0x23, 0x01, 0xf7, 0x23, 0x01, 0x5d, 0x24, 0x01, 0xc3, 0x24, 0x01, 0x29, 0x25, 0x01, 0x8f, 0x25, 0x01, 0xf5, 0x25, 0x01, 0x5b, 0x26, 0x01, 0xc1, 0x26, 0x01, 0x27, 0x27, 0x01, 0x8d, 0x27, 0x01, 0xf3, 0x27, 0x01, 0x59, 0x28, 0x01, 0xbf, 0x28, 0x01, 0x25, 0x29, 0x01, 0x8b, 0x29, 0x01, 0xf1, 0x29, 0x01, 0x57, 0x2a, 0x01, 0xbd, 0x2a, 0x01, 0x23, 0x2b, 0x01, 0x89, 0x2b, 0x01, 0xef, 0x2b, 0x01, 0x55, 0x2c, 0x01, 0xbb, 0x2c, 0x01, 0x21, 0x2d, 0x01, 0x87, 0x2d, 0x01, 0xed, 0x2d, 0x01, 0x53, 0x2e, 0x01, 0xb9, 0x2e, 0x01, 0x1f, 0x2f, 0x01, 0x85, 0x2f, 0x01, 0xeb, 0x2f, 0x01, 0x51, 0x30, 0x01, 0xb7, 0x30, 0x01, 0x1d, 0x31, 0x01, 0x83, 0x31, 0x01, 0xe9, 0x31, 0x01, 0x4f, 0x32, 0x01, 0xb5, 0x32, 0x01, 0x1b, 0x33, 0x01, 0x81, 0x33, 0x01, 0xe7, 0x33, 0x01, 0x4d, 0x34, 0x01, 0xb3, 0x34, 0x01, 0x19, 0x35, 0x01, 0x7f, 0x35, 0x01, 0xe5, 0x35, 0x01, 0x4b, 0x36, 0x01, 0xb1, 0x36, 0x01, 0x17, 0x37, 0x01, 0x7d, 0x37, 0x01, 0xe3, 0x37, 0x01, 0x49, 0x38, 0x01, 0xaf, 0x38, 0x01, 0x15, 0x39, 0x01, 0x7b, 0x39, 0x01, 0xe1, 0x39, 0x01, 0x47, 0x3a, 0x01, 0xad, 0x3a, 0x01, 0x13, 0x3b, 0x01, 0x79, 0x3b, 0x01, 0xdf, 0x3b, 0x01, 0x45, 0x3c, 0x01, 0xab, 0x3c, 0x01, 0x11, 0x3d, 0x01, 0x77, 0x3d, 0x01, 0xdd, 0x3d, 0x01, 0x43, 0x3e, 0x01, 0xa9, 0x3e, 0x01, 0x0f, 0x3f, 0x01, 0x75, 0x3f, 0x01, 0xdb, 0x3f, 0x01, 0x41, 0x40, 0x01, 0xa7, 0x40, 0x01, 0x0d, 0x41, 0x01, 0x73, 0x41, 0x01, 0xd9, 0x41, 0x01, 0x3f, 0x42, 0x01, 0xa5, 0x42, 0x01, 0x0b, 0x43, 0x01, 0x71, 0x43, 0x01, 0xd7, 0x43, 0x01, 0x3d, 0x44, 0x01, 0xa3, 0x44, 0x01, 0x09, 0x45, 0x01, 0x6f, 0x45, 0x01, 0xd5, 0x45, 0x01, 0x3b, 0x46, 0x01, 0xa1, 0x46, 0x01, 0x07, 0x47, 0x01, 0x6d, 0x47, 0x01, 0xd3, 0x47, 0x01, 0x39, 0x48, 0x01, 0x9f, 0x48, 0x01, 0x05, 0x49, 0x01, 0x6b, 0x49, 0x01, 0xd1, 0x49, 0x01, 0x37, 0x4a, 0x01, 0x9d, 0x4a, 0x01, 0x03, 0x4b, 0x01, 0x69, 0x4b, 0x01, 0xcf, 0x4b, 0x01, 0x35, 0x4c, 0x01, 0x9b, 0x4c, 0x01, 0x01, 0x4d, 0x01, 0x67, 0x4d, 0x01, 0xcd, 0x4d, 0x01, 0x33, 0x4e, 0x01, 0x99, 0x4e, 0x01, 0xff, 0x4e, 0x01, 0x65, 0x4f, 0x01, 0xcb, 0x4f, 0x01, 0x31, 0x50, 0x01, 0x97, 0x50, 0x01, 0xfd, 0x50, 0x01, 0x63, 0x51, 0x01, 0xc9, 0x51, 0x01, 0x2f, 0x52, 0x01, 0x95, 0x52, 0x01, 0xfb, 0x52, 0x01, 0x61, 0x53, 0x01, 0xc7, 0x53, 0x01, 0x2d, 0x54, 0x01, 0x93, 0x54, 0x01, 0xf9, 0x54, 0x01, 0x5f, 0x55, 0x01, 0xc5, 0x55, 0x01, 0x2b, 0x56, 0x01, 0x91, 0x56, 0x01, 0xf7, 0x56, 0x01, 0x5d, 0x57, 0x01, 0xc3, 0x57, 0x01, 0x29, 0x58, 0x01, 0x8f, 0x58, 0x01, 0xf5, 0x58, 0x01, 0x5b, 0x59, 0x01, 0xc1, 0x59, 0x01, 0x27, 0x5a, 0x01, 0x8d, 0x5a, 0x01, 0xf3, 0x5a, 0x01, 0x59, 0x5b, 0x01, 0xbf, 0x5b, 0x01, 0x25, 0x5c, 0x01, 0x8b, 0x5c, 0x01, 0xf1, 0x5c, 0x01, 0x57, 0x5d, 0x01, 0xbd, 0x5d, 0x01, 0x23, 0x5e, 0x01, 0x89, 0x5e, 0x01, 0xef, 0x5e, 0x01, 0x55, 0x5f, 0x01, 0xbb, 0x5f, 0x01, 0x21, 0x60, 0x01, 0x87, 0x60, 0x01, 0xed, 0x60, 0x01, 0x53, 0x61, 0x01, 0xb9, 0x61, 0x01, 0x1f, 0x62, 0x01, 0x85, 0x62, 0x01, 0xeb, 0x62, 0x01, 0x51, 0x63, 0x01, 0xb7, 0x63, 0x01, 0x1d, 0x64, 0x01, 0x83, 0x64, 0x01, 0xe9, 0x64, 0x01, 0x4f, 0x65, 0x01, 0xb5, 0x65, 0x01, 0x1b, 0x66, 0x01, 0x81, 0x66, 0x01, 0xe7, 0x66, 0x01, 0x4d, 0x67, 0x01, 0xb3, 0x67, 0x01, 0x19, 0x68, 0x01, 0x7f, 0x68, 0x01, 0xe5, 0x68, 0x01, 0x4b, 0x69, 0x01, 0xb1, 0x69, 0x01, 0x17, 0x6a, 0x01, 0x7d, 0x6a, 0x01, 0xe3, 0x6a, 0x01, 0x49, 0x6b, 0x01, 0xaf, 0x6b, 0x01, 0x15, 0x6c, 0x01, 0x7b, 0x6c, 0x01, 0xe1, 0x6c, 0x01, 0x47, 0x6d, 0x01, 0xad, 0x6d, 0x01, 0x13, 0x6e, 0x01, 0x79, 0x6e, 0x01, 0xdf, 0x6e, 0x01, 0x45, 0x6f, 0x01, 0xab, 0x6f, 0x01, 0x11, 0x70, 0x01, 0x77, 0x70, 0x01, 0xdd, 0x70, 0x01, 0x43, 0x71, 0x01, 0xa9, 0x71, 0x01, 0x0f, 0x72, 0x01, 0x75, 0x72, 0x01, 0xdb, 0x72, 0x01, 0x41, 0x73, 0x01, 0xa7, 0x73, 0x01, 0x0d, 0x74, 0x01, 0x73, 0x74, 0x01, 0xd9, 0x74, 0x01, 0x3f, 0x75, 0x01, 0xa5, 0x75, 0x01, 0x0b, 0x76, 0x01, 0x71, 0x76, 0x01, 0xd7, 0x76, 0x01, 0x3d, 0x77, 0x01, 0xa3, 0x77, 0x01, 0x09, 0x78, 0x01, 0x6f, 0x78, 0x01, 0xd5, 0x78, 0x01, 0x3b, 0x79, 0x01, 0xa1, 0x79, 0x01, 0x07, 0x7a, 0x01, 0x6d, 0x7a, 0x01, 0xd3, 0x7a, 0x01, 0x39, 0x7b, 0x01, 0x9f, 0x7b, 0x01, 0x05, 0x7c, 0x01, 0x6b, 0x7c, 0x01, 0xd1, 0x7c, 0x01, 0x37, 0x7d, 0x01, 0x9d, 0x7d, 0x01, 0x03, 0x7e, 0x01, 0x69, 0x7e, 0x01, 0xcf, 0x7e, 0x01, 0x35, 0x7f, 0x01, 0x9b, 0x7f, 0x01, 0x01, 0x80, 0x01, 0x67, 0x80, 0x01, 0xcd, 0x80, 0x01, 0x33, 0x81, 0x01, 0x99, 0x81, 0x01, 0xff, 0x81, 0x01, 0x65, 0x82, 0x01, 0xcb, 0x82, 0x01, 0x31, 0x83, 0x01, 0x97, 0x83, 0x01, 0xfd, 0x83, 0x01, 0x63, 0x84, 0x01, 0xc9, 0x84, 0x01, 0x2f, 0x85, 0x01, 0x95, 0x85, 0x01, 0xfb, 0x85, 0x01, 0x61, 0x86, 0x01, 0xc7, 0x86, 0x01, 0x2d, 0x87, 0x01, 0x93, 0x87, 0x01, 0xf9, 0x87, 0x01, 0x5f, 0x88, 0x01, 0xc5, 0x88, 0x01, 0x2b, 0x89, 0x01, 0x91, 0x89, 0x01, 0xf7, 0x89, 0x01, 0x5d, 0x8a, 0x01, 0xc3, 0x8a, 0x01, 0x29, 0x8b, 0x01, 0x8f, 0x8b, 0x01, 0xf5, 0x8b, 0x01, 0x5b, 0x8c, 0x01, 0xc1, 0x8c, 0x01, 0x27, 0x8d, 0x01, 0x8d, 0x8d, 0x01, 0xf3, 0x8d, 0x01, 0x59, 0x8e, 0x01, 0xbf, 0x8e, 0x01, 0x25, 0x8f, 0x01, 0x8b, 0x8f, 0x01, 0xf1, 0x8f, 0x01, 0x57, 0x90, 0x01, 0xbd, 0x90, 0x01, 0x23, 0x91, 0x01, 0x89, 0x91, 0x01, 0xef, 0x91, 0x01, 0x55, 0x92, 0x01, 0xbb, 0x92, 0x01, 0x21, 0x93, 0x01, 0x87, 0x93, 0x01, 0xed, 0x93, 0x01, 0x53, 0x94, 0x01, 0xb9, 0x94, 0x01, 0x1f, 0x95, 0x01, 0x85, 0x95, 0x01, 0xeb, 0x95, 0x01, 0x51, 0x96, 0x01, 0xb7, 0x96, 0x01, 0x1d, 0x97, 0x01, 0x83, 0x97, 0x01, 0xe9, 0x97, 0x01, 0x4f, 0x98, 0x01, 0xb5, 0x98, 0x01, 0x1b, 0x99, 0x01, 0x81, 0x99, 0x01, 0xe7, 0x99, 0x01, 0x4d, 0x9a, 0x01, 0xb3, 0x9a, 0x01, 0x19, 0x9b, 0x01, 0x7f, 0x9b, 0x01, 0xe5, 0x9b, 0x01, 0x4b, 0x9c, 0x01, 0xb1, 0x9c, 0x01, 0x17, 0x9d, 0x01, 0x7d, 0x9d, 0x01, 0xe3, 0x9d, 0x01, 0x49, 0x9e, 0x01, 0xaf, 0x9e, 0x01, 0x15, 0x9f, 0x01, 0x7b, 0x9f, 0x01, 0xe1, 0x9f, 0x01, 0x47, 0xa0, 0x01, 0xad, 0xa0, 0x01, 0x13, 0xa1, 0x01, 0x79, 0xa1, 0x01, 0xdf, 0xa1, 0x01, 0x45, 0xa2, 0x01, 0xab, 0xa2, 0x01, 0x11, 0xa3, 0x01, 0x77, 0xa3, 0x01, 0xdd, 0xa3, 0x01, 0x43, 0xa4, 0x01, 0xa9, 0xa4, 0x01, 0x0f, 0xa5, 0x01, 0x75, 0xa5, 0x01, 0xdb, 0xa5, 0x01, 0x41, 0xa6, 0x01, 0xa7, 0xa6, 0x01, 0x0d, 0xa7, 0x01, 0x73, 0xa7, 0x01, 0xd9, 0xa7, 0x01, 0x3f, 0xa8, 0x01, 0xa5, 0xa8, 0x01, 0x0b, 0xa9, 0x01, 0x71, 0xa9, 0x01, 0xd7, 0xa9, 0x01, 0x3d, 0xaa, 0x01, 0xa3, 0xaa, 0x01, 0x09, 0xab, 0x01, 0x6f, 0xab, 0x01, 0xd5, 0xab, 0x01, 0x3b, 0xac, 0x01, 0xa1, 0xac, 0x01, 0x07, 0xad, 0x01, 0x6d, 0xad, 0x01, 0xd3, 0xad, 0x01, 0x39, 0xae, 0x01, 0x9f, 0xae, 0x01, 0x05, 0xaf, 0x01, 0x6b, 0xaf, 0x01, 0xd1, 0xaf, 0x01, 0x37, 0xb0, 0x01, 0x9d, 0xb0, 0x01, 0x03, 0xb1, 0x01, 0x69, 0xb1, 0x01, 0xcf, 0xb1, 0x01, 0x35, 0xb2, 0x01, 0x9b, 0xb2, 0x01, 0x01, 0xb3, 0x01, 0x67, 0xb3, 0x01, 0xcd, 0xb3, 0x01, 0x33, 0xb4, 0x01, 0x99, 0xb4, 0x01, 0xff, 0xb4, 0x01, 0x65, 0xb5, 0x01, 0xcb, 0xb5, 0x01, 0x31, 0xb6, 0x01, 0x97, 0xb6, 0x01, 0xfd, 0xb6, 0x01, 0x63, 0xb7, 0x01, 0xc9, 0xb7, 0x01, 0x2f, 0xb8, 0x01, 0x95, 0xb8, 0x01, 0xfb, 0xb8, 0x01, 0x61, 0xb9, 0x01, 0xc7, 0xb9, 0x01, 0x2d, 0xba, 0x01, 0x93, 0xba, 0x01, 0xf9, 0xba, 0x01, 0x5f, 0xbb, 0x01, 0xc5, 0xbb, 0x01, 0x2b, 0xbc, 0x01, 0x91, 0xbc, 0x01, 0xf7, 0xbc, 0x01, 0x5d, 0xbd, 0x01, 0xc3, 0xbd, 0x01, 0x29, 0xbe, 0x01, 0x8f, 0xbe, 0x01, 0xf5, 0xbe, 0x01, 0x5b, 0xbf, 0x01, 0xc1, 0xbf, 0x01, 0x27, 0xc0, 0x01, 0x8d, 0xc0, 0x01, 0xf3, 0xc0, 0x01, 0x59, 0xc1, 0x01, 0xbf, 0xc1, 0x01, 0x25, 0xc2, 0x01, 0x8b, 0xc2, 0x01, 0xf1, 0xc2, 0x01, 0x57, 0xc3, 0x01, 0xbd, 0xc3, 0x01, 0x23, 0xc4, 0x01, 0x89, 0xc4, 0x01, 0xef, 0xc4, 0x01, 0x55, 0xc5, 0x01, 0xbb, 0xc5, 0x01, 0x21, 0xc6, 0x01, 0x87, 0xc6, 0x01, 0xed, 0xc6, 0x01, 0x53, 0xc7, 0x01, 0xb9, 0xc7, 0x01, 0x1f, 0xc8, 0x01, 0x85, 0xc8, 0x01, 0xeb, 0xc8, 0x01, 0x51, 0xc9, 0x01, 0xb7, 0xc9, 0x01, 0x1d, 0xca, 0x01, 0x83, 0xca, 0x01, 0xe9, 0xca, 0x01, 0x4f, 0xcb, 0x01, 0xb5, 0xcb, 0x01, 0x1b, 0xcc, 0x01, 0x1f, 0x04, 0x07, 0x04, 0x04, 0x02, 0x03, 0x10, 0x00, 0x00, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x0a, 0x06, 0x00, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x10, 0x00, 0x00, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x1f, 0x00, 0x08, 0x00, 0x06, 0x00, 0x03, 0x0a, 0x06, 0x00, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x1e, 0x0b, 0x06, 0x04, 0x04, 0x03, 0x04, 0x0c, 0x04, 0x00, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x13, 0xf8, 0x01, 0x87, 0xf9, 0x01, 0x87, 0xf9, 0x01, 0x35, 0xee, 0x01, 0xa9, 0xf2, 0x01, 0xa9, 0xf2, 0x01, 0x35, 0xee, 0x01, 0xa9, 0xf2, 0x01, 0xa9, 0xf2, 0x01, 0x1e, 0x04, 0x0b, 0x04, 0x08, 0x02, 0x06, 0x04, 0x06, 0x06, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x18, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x0a, 0x06, 0x00, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x08, 0x04, 0x04, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0xb7, 0x11, 0x02, 0x21, 0x17, 0x02, 0x09, 0x1d, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x03, 0x05, 0x08, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0x7c, 0x00, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x73, 0x30, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xf0, 0x3c, 0x03, 0x55, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0xff, 0x00, 0x03, 0x55, 0x55, 0xff, 0x00, 0x3d, 0x55, 0x55, 0xff, 0x00, 0xcd, 0x55, 0x55, 0xcf, 0xff, 0x0d, 0x55, 0x55, 0x73, 0x30, 0x3d, 0x55, 0x55, 0x73, 0xf0, 0xf5, 0x55, 0x55, 0x73, 0xf0, 0x35, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x7f, 0x55, 0x57, 0xff, 0x55, 0xff, 0xd5, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x0f, 0x00, 0xf0, 0xd5, 0x57, 0x30, 0xc3, 0x0c, 0xd5, 0x57, 0x00, 0x3c, 0x00, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x57, 0x3f, 0xff, 0xfc, 0xd5, 0x57, 0xf0, 0xc3, 0x0f, 0xd5, 0x55, 0x73, 0xff, 0xcd, 0x55, 0x55, 0xc3, 0xff, 0xc3, 0x55, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x03, 0x00, 0xc0, 0xd5, 0x57, 0x0c, 0x00, 0x30, 0xd5, 0x57, 0x00, 0x3c, 0x00, 0xd5, 0x55, 0xc0, 0xff, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x3f, 0x0f, 0xc3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x00, 0xf0, 0x0d, 0x55, 0x55, 0xff, 0x0f, 0xf5, 0x55, 0x57, 0x33, 0xfc, 0xcd, 0x55, 0x57, 0xf3, 0xfc, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x30, 0x00, 0x0c, 0xd5, 0x57, 0x0c, 0x00, 0x30, 0xd5, 0x57, 0x00, 0xff, 0x00, 0xd5, 0x5f, 0x03, 0xff, 0xc0, 0xf5, 0x5c, 0xc3, 0xff, 0xc3, 0x35, 0x5f, 0x3f, 0xff, 0xfc, 0xf5, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0xc3, 0xff, 0xc3, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x7f, 0x55, 0x57, 0xff, 0x55, 0xff, 0xd5, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x03, 0x00, 0xc0, 0xd5, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x30, 0x3c, 0x0c, 0xd5, 0x55, 0xcc, 0x3c, 0x33, 0xd5, 0x55, 0xcc, 0x3c, 0x33, 0x55, 0x55, 0xc3, 0xc3, 0xc3, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xd7, 0xf5, 0x55, 0x55, 0x5f, 0x55, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x5c, 0x3f, 0xff, 0xc3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x55, 0xff, 0xff, 0xf5, 0x55, 0x55, 0xc0, 0x00, 0x35, 0x55, 0x57, 0x30, 0x00, 0xcd, 0x55, 0x57, 0xf0, 0x00, 0xfd, 0x55, 0x55, 0x70, 0x00, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0x55, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0x70, 0x00, 0x3d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x70, 0x0c, 0xd5, 0x55, 0x57, 0xc0, 0xfc, 0xd5, 0x55, 0x55, 0xf0, 0x3f, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0x57, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0x70, 0x00, 0x3d, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x30, 0xcd, 0x55, 0x55, 0xfc, 0x3f, 0xf5, 0x55, 0x55, 0x70, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x70, 0x3f, 0xf5, 0x55, 0x55, 0xc0, 0x0f, 0xf5, 0x55, 0x7f, 0xc0, 0x0f, 0xf5, 0x5f, 0xc0, 0xc0, 0x0f, 0x55, 0x5f, 0xc0, 0xc0, 0xcf, 0xd5, 0x55, 0xc0, 0xc0, 0xcf, 0xd5, 0x57, 0xc0, 0x3c, 0xcf, 0xf5, 0x5f, 0xfc, 0x03, 0x0f, 0xf5, 0x5f, 0xff, 0xff, 0xf7, 0xd5, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x3c, 0x03, 0xc3, 0x55, 0x5c, 0xc3, 0x0c, 0x33, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0xc3, 0x0c, 0x33, 0x55, 0x57, 0x30, 0xf0, 0xcc, 0xd5, 0x55, 0xff, 0xff, 0xf0, 0xd5, 0x55, 0x73, 0x0c, 0x03, 0x55, 0x55, 0xcc, 0xfc, 0x0d, 0x55, 0x55, 0xfc, 0xff, 0x0d, 0x55, 0x55, 0x5c, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x55, 0xf5, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x00, 0xc3, 0x00, 0xd5, 0x57, 0x3f, 0xc3, 0xfc, 0xd5, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x5c, 0xcc, 0x35, 0x55, 0x55, 0x73, 0xff, 0xcd, 0x55, 0x55, 0x70, 0xfc, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xc0, 0x30, 0x03, 0x55, 0x55, 0xc0, 0xc0, 0x03, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xfc, 0x00, 0x03, 0x55, 0x55, 0xff, 0x03, 0xc3, 0x55, 0x55, 0x7f, 0x03, 0x3d, 0x55, 0x55, 0x5f, 0xff, 0x35, 0x55, 0x55, 0x5c, 0xcc, 0x0d, 0x55, 0x55, 0x57, 0x3c, 0x03, 0x55, 0x55, 0x57, 0x3c, 0x3f, 0x55, 0x55, 0x57, 0xff, 0xf5, 0x55, 0x55, 0x55, 0x7d, 0xfd, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0x7f, 0x55, 0x55, 0x55, 0xff, 0xff, 0xd5, 0x55, 0x55, 0xff, 0xff, 0xd5, 0x55, 0x55, 0xff, 0x00, 0x35, 0x55, 0x57, 0xf0, 0x00, 0x3d, 0x55, 0x57, 0xc0, 0x03, 0x03, 0x55, 0x57, 0x00, 0x3c, 0x03, 0x55, 0x57, 0x00, 0x00, 0x0f, 0x55, 0x57, 0x00, 0x00, 0x35, 0x55, 0x57, 0xc0, 0x03, 0xd5, 0x55, 0x55, 0x7f, 0xff, 0x55, 0x55, 0x55, 0xc0, 0xcf, 0x55, 0x55, 0x57, 0x30, 0xfd, 0x55, 0x55, 0x57, 0xf0, 0xfd, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x7d, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xf5, 0x55, 0x55, 0x5f, 0xfd, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0x00, 0x0d, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x0f, 0xc3, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0x70, 0x00, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x5c, 0x3c, 0xd5, 0x55, 0x55, 0x5f, 0x0f, 0xd5, 0x55, 0x55, 0x5c, 0xff, 0xd5, 0x55, 0x55, 0x70, 0x0f, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3c, 0x0f, 0x55, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0xc0, 0x00, 0xff, 0x55, 0x55, 0xc0, 0xf0, 0xff, 0x55, 0x55, 0x70, 0xcc, 0xfd, 0x55, 0x55, 0x5f, 0xcf, 0xd5, 0x55, 0x55, 0x5c, 0xcc, 0xd5, 0x55, 0x55, 0x5c, 0x3f, 0xd5, 0x55, 0x55, 0x5c, 0x0f, 0xd5, 0x55, 0x55, 0x70, 0x0f, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x55, 0xfd, 0x55, 0x55, 0x7f, 0xdf, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0xc3, 0x55, 0x55, 0xcc, 0x00, 0x03, 0x55, 0x55, 0x73, 0x00, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x73, 0x30, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0x7f, 0x55, 0x55, 0xff, 0xd5, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0xd5, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0x70, 0x00, 0x03, 0x55, 0x55, 0xc3, 0x00, 0x30, 0xd5, 0x55, 0xcc, 0xc0, 0xcc, 0xd5, 0x55, 0xc3, 0x00, 0x30, 0xd5, 0x57, 0xc0, 0x3f, 0x00, 0xd5, 0x57, 0x30, 0xff, 0xc3, 0x55, 0x55, 0xcf, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xc3, 0xfc, 0x03, 0x55, 0x55, 0xc3, 0xfc, 0x3c, 0xd5, 0x55, 0x7f, 0xfc, 0x37, 0xd5, 0x55, 0x5f, 0x7f, 0xd5, 0x55, 0x55, 0x55, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x3c, 0x03, 0xc3, 0x55, 0x5c, 0xf3, 0x0f, 0x33, 0x55, 0x5c, 0xff, 0x0f, 0xf3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x0f, 0xf0, 0x0d, 0x55, 0x55, 0xfc, 0x3f, 0xf5, 0x55, 0x55, 0xc3, 0xcc, 0x3d, 0x55, 0x55, 0x70, 0xfc, 0xf3, 0x55, 0x55, 0x70, 0xfc, 0xdf, 0x55, 0x55, 0x7f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xcd, 0x55, 0x5f, 0xff, 0xff, 0xfd, 0x55, 0x7f, 0xff, 0xff, 0xd5, 0x55, 0x70, 0x00, 0x03, 0xd5, 0x55, 0xff, 0xff, 0xfc, 0xd5, 0x55, 0xc0, 0x00, 0x0f, 0xd5, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0x7c, 0x00, 0x0c, 0xd5, 0x55, 0x5f, 0xff, 0xf0, 0x35, 0x55, 0x7f, 0x3f, 0xfc, 0x0d, 0x55, 0x7f, 0x3f, 0xfc, 0x0d, 0x55, 0x70, 0x00, 0x3c, 0x0d, 0x55, 0x7f, 0xff, 0xf0, 0x0d, 0x55, 0x5f, 0xff, 0xdf, 0xf5, 0x55, 0x7f, 0xdf, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0x55, 0x55, 0x55, 0x57, 0x35, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0xff, 0xff, 0x55, 0x55, 0x5f, 0xff, 0xff, 0x55, 0x55, 0x70, 0x00, 0x0f, 0x55, 0x55, 0x7f, 0xff, 0xf3, 0xfd, 0x55, 0xc0, 0x00, 0x0c, 0xc3, 0x55, 0xc0, 0x00, 0x03, 0xc3, 0x55, 0xc0, 0x00, 0x03, 0x03, 0x55, 0xf0, 0x03, 0x03, 0xc3, 0x55, 0xc3, 0xc0, 0x0f, 0xc3, 0x55, 0xc3, 0xc0, 0x3f, 0x0d, 0x55, 0x7f, 0xff, 0xfc, 0x35, 0x5d, 0xff, 0x3f, 0xf3, 0xd5, 0x5f, 0x00, 0x00, 0xfd, 0x55, 0x5f, 0xff, 0xff, 0x3d, 0x55, 0x55, 0xff, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xff, 0x55, 0x55, 0x7f, 0xff, 0xff, 0xd5, 0x55, 0xf0, 0x00, 0x03, 0xf5, 0x55, 0xcf, 0xff, 0xfc, 0xf5, 0x55, 0xf0, 0x00, 0x03, 0xff, 0x57, 0x0f, 0xc0, 0xfc, 0xf3, 0x57, 0x33, 0xc3, 0x3c, 0xdf, 0x57, 0x33, 0xc3, 0x3c, 0xd5, 0x57, 0x0f, 0xc0, 0xfc, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x35, 0x55, 0xff, 0xff, 0xfc, 0x0d, 0x57, 0xff, 0xcf, 0xf3, 0x0d, 0x5c, 0xff, 0xcf, 0xff, 0x0d, 0x57, 0x70, 0x00, 0x0c, 0x0d, 0x55, 0x7f, 0xff, 0xf7, 0xf5, 0x55, 0x57, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xf7, 0xfd, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xff, 0xf5, 0x55, 0x70, 0x00, 0xff, 0xff, 0x55, 0x7f, 0xfc, 0x03, 0xf3, 0x55, 0xf0, 0xff, 0xf0, 0xdf, 0x55, 0xf0, 0xf3, 0x0f, 0xd5, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xff, 0xf0, 0x33, 0x55, 0x57, 0x3f, 0xc0, 0xff, 0xd5, 0x57, 0xcf, 0xff, 0xfc, 0x35, 0x55, 0xff, 0x3f, 0xfc, 0x0d, 0x55, 0x7f, 0x3f, 0xf0, 0x0d, 0x55, 0x7f, 0x3f, 0xf0, 0x0d, 0x55, 0x70, 0x00, 0xf0, 0x0d, 0x55, 0x5f, 0xff, 0xdf, 0xf5, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x55, 0xf7, 0xd5, 0x55, 0x30, 0x1f, 0x01, 0x55, 0x40, 0x00, 0x00, 0x00, 0x15, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x11, 0x41, 0x50, 0x00, 0x00, 0x15, 0x55, 0x55, 0x54, 0x04, 0x10, 0x01, 0x55, 0x41, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa1, 0x14, 0x15, 0x54, 0x01, 0x11, 0x45, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa5, 0x54, 0x15, 0x54, 0x01, 0x55, 0x45, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa1, 0x14, 0x44, 0x11, 0x55, 0x55, 0x55, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x15, 0x40, 0x01, 0x55, 0x11, 0x56, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x95, 0x40, 0x01, 0x55, 0x55, 0x56, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x95, 0x55, 0x55, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x55, 0x50, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x01, 0x50, 0x55, 0x50, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x15, 0x55, 0x55, 0x54, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x02, 0x55, 0x55, 0x55, 0x00, 0x04, 0x00, 0x80, 0x28, 0x00, 0x00, 0xa0, 0x02, 0x01, 0x15, 0x55, 0x10, 0x04, 0x55, 0x80, 0x28, 0x00, 0x00, 0xa0, 0x02, 0x01, 0x15, 0x55, 0x01, 0x55, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x02, 0x55, 0x55, 0x55, 0x01, 0x01, 0x00, 0x80, 0xaa, 0xaa, 0xaa, 0xa8, 0x02, 0x00, 0x04, 0x01, 0x01, 0x55, 0x00, 0x82, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x04, 0x01, 0x00, 0x41, 0x00, 0x82, 0xaa, 0xaa, 0xaa, 0xaa, 0x02, 0x00, 0x04, 0x01, 0x55, 0x5a, 0xa5, 0x80, 0x95, 0x95, 0x80, 0x00, 0x02, 0x55, 0x54, 0x01, 0x00, 0x25, 0x58, 0x80, 0x95, 0x95, 0x85, 0x54, 0x0a, 0xaa, 0xa8, 0x01, 0x00, 0x26, 0x98, 0x80, 0x95, 0x95, 0x85, 0x54, 0x08, 0x00, 0x09, 0x55, 0x00, 0x25, 0x58, 0x80, 0x95, 0x95, 0xaa, 0xaa, 0x08, 0x88, 0x88, 0x00, 0x00, 0x20, 0x08, 0x95, 0x95, 0x95, 0x80, 0x02, 0x58, 0x88, 0x88, 0x00, 0xaa, 0xa0, 0x0a, 0x95, 0x95, 0x95, 0x80, 0x02, 0x58, 0x00, 0x0a, 0xaa, 0x04, 0x20, 0x08, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa9, 0x55, 0x58, 0x00, 0x00, 0x0a, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xaa, 0xa9, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0x42, 0x82, 0x20, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa6, 0x86, 0x26, 0x62, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x45, 0x86, 0x24, 0xa4, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xa4, 0xa1, 0x61, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x61, 0x40, 0xa2, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0xaa, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa9, 0x55, 0x69, 0x55, 0x6a, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x9a, 0xa9, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x59, 0x59, 0x6a, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x98, 0x49, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x95, 0x55, 0xaa, 0x95, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa5, 0x56, 0xaa, 0x40, 0x68, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa8, 0x0a, 0xa5, 0x55, 0x58, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa9, 0x5a, 0xa5, 0x55, 0x58, 0x00, 0x95, 0x5a, 0x69, 0xa5, 0x56, 0x02, 0xa5, 0x96, 0xa9, 0x69, 0x68, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x96, 0x5a, 0x69, 0xa5, 0x96, 0x54, 0x54, 0x54, 0x54, 0x54, 0x55, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x54, 0x54, 0x54, 0x54, 0x54, 0x55, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x30, 0x1f, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x15, 0x00, 0x00, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x55, 0x00, 0x01, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x40, 0x51, 0x55, 0x55, 0x15, 0x54, 0x00, 0x00, 0x15, 0x54, 0x55, 0x55, 0x45, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x40, 0x00, 0x44, 0x11, 0x10, 0x11, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x44, 0x04, 0x44, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x40, 0x00, 0x44, 0x15, 0x05, 0x41, 0x50, 0x05, 0x55, 0x55, 0x50, 0x05, 0x41, 0x50, 0x54, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x50, 0x40, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x50, 0x40, 0x01, 0x00, 0x01, 0x00, 0x17, 0xfc, 0x3f, 0xfc, 0x00, 0x43, 0xff, 0xc0, 0x01, 0x00, 0x01, 0x00, 0x1f, 0xf4, 0xff, 0xd4, 0x00, 0x4f, 0xfc, 0x40, 0x01, 0x55, 0x55, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x40, 0x01, 0x11, 0x11, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x40, 0x01, 0x00, 0x01, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xc0, 0x01, 0x05, 0x41, 0x00, 0xf0, 0xfc, 0x03, 0xff, 0xff, 0x00, 0x00, 0xc0, 0x01, 0x05, 0x41, 0x00, 0xf0, 0xf3, 0x0c, 0x71, 0xc7, 0x33, 0x30, 0xc0, 0xaa, 0xaa, 0xaa, 0xaa, 0xf0, 0xf3, 0x0d, 0x75, 0xd7, 0x33, 0x30, 0xea, 0x55, 0x55, 0x55, 0x55, 0xf0, 0xfc, 0x0d, 0x34, 0xd3, 0x33, 0x30, 0xd5, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x0d, 0x34, 0xc3, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x03, 0xff, 0xff, 0xaa, 0xaa, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 0xc0, 0x00, 0xfc, 0x0f, 0xc0, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x3a, 0xbf, 0xfa, 0xab, 0xff, 0xbf, 0xfb, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0xff, 0xff, 0xcf, 0xfc, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf0, 0x03, 0xff, 0x3f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xc0, 0x00, 0xfc, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x55, 0x51, 0x55, 0x55, 0x15, 0x54, 0x00, 0x00, 0x15, 0x10, 0x00, 0x00, 0x40, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x40, 0x11, 0x10, 0x11, 0x10, 0x04, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x40, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x15, 0x55, 0x55, 0x40, 0x15, 0x05, 0x41, 0x50, 0x05, 0x55, 0x55, 0x50, 0x00, 0x00, 0x00, 0x00, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf5, 0xff, 0xf0, 0x00, 0x0f, 0xff, 0x00, 0x50, 0x50, 0x50, 0x50, 0x3f, 0xc3, 0xff, 0x00, 0x14, 0x3f, 0xf4, 0x14, 0x55, 0x50, 0x55, 0x50, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x54, 0x55, 0x50, 0x55, 0x50, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x54, 0x55, 0x55, 0x55, 0x53, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x54, 0x40, 0x10, 0x40, 0x13, 0xc3, 0xf0, 0x0f, 0xff, 0xfc, 0x00, 0x03, 0x04, 0x50, 0x50, 0x50, 0x53, 0xc3, 0xcc, 0x31, 0xc7, 0x1c, 0xcc, 0xc3, 0x14, 0x40, 0x10, 0x40, 0x13, 0xc3, 0xcc, 0x35, 0xd7, 0x5c, 0xcc, 0xc3, 0x04, 0xaa, 0xaa, 0xaa, 0xab, 0xc3, 0xf0, 0x34, 0xd3, 0x4c, 0xcc, 0xc3, 0xaa, 0x55, 0x55, 0x55, 0x57, 0x00, 0x00, 0x34, 0xd3, 0x0c, 0x00, 0x03, 0x55, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x0f, 0xff, 0xfe, 0xaa, 0xab, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x3f, 0x00, 0x03, 0xf0, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xea, 0xff, 0xea, 0xaf, 0xfe, 0xff, 0xec, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf3, 0xff, 0xff, 0x3f, 0xf3, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x0f, 0xfc, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x03, 0xf0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xfd, 0x7d, 0x7f, 0x5d, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x5d, 0xd5, 0xd7, 0x75, 0xdd, 0xd5, 0x55, 0x55, 0x55, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x30, 0xcc, 0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0xc0, 0xff, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xc0, 0xc3, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0x3f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xfc, 0x3f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x03, 0xc0, 0x30, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0xf3, 0xff, 0xff, 0xcf, 0x00, 0x00, 0x0f, 0xf0, 0x70, 0x0f, 0x55, 0x55, 0xc3, 0x0c, 0x30, 0xc3, 0x55, 0x55, 0xf0, 0x0d, 0xc3, 0x30, 0xd5, 0xff, 0x7c, 0xcf, 0xf3, 0x3d, 0xff, 0x57, 0x0c, 0xc3, 0xc0, 0x3f, 0x5f, 0x03, 0x57, 0xcf, 0xf3, 0xd5, 0xc0, 0xf5, 0xfc, 0x03, 0xc0, 0x30, 0xdc, 0x0d, 0x5f, 0xff, 0xff, 0xf5, 0x70, 0x37, 0x0c, 0x03, 0x7f, 0xff, 0x5f, 0xf5, 0x5f, 0x55, 0x55, 0xf5, 0x5f, 0xf5, 0xff, 0xfd, 0x30, 0x1f, 0xa4, 0x00, 0xa4, 0x01, 0x90, 0x00, 0x64, 0x06, 0x40, 0x1a, 0x00, 0x16, 0xa9, 0x40, 0x09, 0x00, 0x40, 0x00, 0x10, 0x01, 0x00, 0x60, 0x01, 0x6a, 0x2a, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xaa, 0x00, 0xa5, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x01, 0x6a, 0x80, 0x00, 0x01, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x30, 0xc0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x00, 0x05, 0x94, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x15, 0x56, 0xa5, 0x55, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x15, 0x40, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x29, 0x50, 0x15, 0x68, 0x00, 0x40, 0x07, 0xf0, 0x0f, 0xc0, 0x10, 0x00, 0x0a, 0xa5, 0x6a, 0x80, 0x01, 0x00, 0x1f, 0xfc, 0x3f, 0xf0, 0x04, 0x00, 0x00, 0xaa, 0xa8, 0x00, 0x15, 0x00, 0x1f, 0xff, 0xff, 0xf0, 0x05, 0x40, 0x00, 0x0a, 0xa0, 0x00, 0x04, 0x00, 0x5c, 0x00, 0x00, 0x30, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xf0, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xc0, 0x33, 0x00, 0x00, 0xcc, 0x03, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x30, 0x03, 0xc0, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x0c, 0x30, 0x03, 0xc0, 0x0c, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x3c, 0x03, 0xc0, 0x3c, 0xff, 0xc0, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0xc3, 0xff, 0xff, 0xc3, 0x00, 0x00, 0x0f, 0xf0, 0x30, 0x0c, 0x00, 0x00, 0xcc, 0x30, 0x0c, 0x33, 0x00, 0x00, 0x30, 0x0c, 0xc3, 0x0f, 0x00, 0x00, 0x3f, 0x3f, 0xfc, 0xfc, 0x00, 0x00, 0xf0, 0xc3, 0xc0, 0x30, 0xc0, 0x00, 0x03, 0x3f, 0xfc, 0xc0, 0x00, 0x03, 0x0c, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0xfc, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x3f, 0xfc, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x30, 0x30, 0xc0, 0x00, 0x00, 0x3c, 0x3c, 0x00, 0x00, 0x03, 0x0c, 0x0c, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x0c, 0x30, 0x00, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xfd, 0x7d, 0x7f, 0x5d, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x5d, 0xd5, 0xd7, 0x75, 0xdd, 0xd5, 0x55, 0x55, 0x55, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x30, 0xcc, 0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0xc0, 0xff, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xc0, 0xc3, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x70, 0x0f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xf0, 0x0d, 0xc3, 0x30, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x0c, 0xc3, 0xc0, 0x3f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfc, 0x03, 0xc0, 0x30, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x0c, 0x03, 0x7f, 0xff, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xfd, 0x30, 0x1f, 0xa4, 0x00, 0xa4, 0x01, 0x90, 0x00, 0x64, 0x06, 0x40, 0x1a, 0x00, 0x16, 0xa9, 0x40, 0x09, 0x00, 0x40, 0x00, 0x10, 0x01, 0x00, 0x60, 0x01, 0x6a, 0x2a, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xaa, 0x00, 0xa5, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x01, 0x6a, 0x80, 0x00, 0x01, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x30, 0xc0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x00, 0x05, 0x94, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x15, 0x56, 0xa5, 0x55, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x15, 0x40, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x29, 0x50, 0x15, 0x68, 0x00, 0x40, 0x04, 0x00, 0x04, 0x00, 0x10, 0x00, 0x0a, 0xa5, 0x6a, 0x80, 0x01, 0x00, 0x14, 0x00, 0x05, 0x00, 0x04, 0x00, 0x00, 0xaa, 0xa8, 0x00, 0x15, 0x00, 0x15, 0x00, 0x15, 0x00, 0x05, 0x40, 0x00, 0x0a, 0xa0, 0x00, 0x04, 0x00, 0x54, 0x00, 0x05, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x30, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0c, 0xc3, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xc3, 0xc0, 0x30, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x30, 0x30, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x0c, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xfc, 0x00, 0xc3, 0x0f, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xc3, 0x00, 0xc3, 0x30, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xcc, 0xc3, 0x00, 0xff, 0x30, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xfc, 0x00, 0xc3, 0x30, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xc0, 0x00, 0xc3, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x3f, 0x0f, 0xcf, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0xcc, 0x0c, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0xcf, 0xcf, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0x0f, 0xcf, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x30, 0xcc, 0x33, 0x0c, 0xfc, 0xfc, 0x00, 0x00, 0xc0, 0x00, 0x00, 0xc3, 0x30, 0xcf, 0x33, 0xcc, 0xc0, 0xc3, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc3, 0x30, 0xcc, 0xf3, 0x3c, 0xfc, 0xc3, 0x00, 0x00, 0xfc, 0x00, 0x00, 0xfc, 0x30, 0xcc, 0x33, 0x0c, 0xc0, 0xfc, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc3, 0x0f, 0x0c, 0x33, 0x0c, 0xfc, 0xc3, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x1f, 0x05, 0x55, 0x55, 0x55, 0x55, 0x55, 0x54, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x05, 0x54, 0x55, 0x45, 0x51, 0x10, 0x00, 0x04, 0x04, 0x55, 0x44, 0x51, 0x11, 0x55, 0x44, 0x04, 0x44, 0x44, 0x51, 0x11, 0x00, 0x44, 0x04, 0x44, 0x44, 0x51, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x00, 0x00, 0x00, 0x05, 0x41, 0x10, 0x00, 0x00, 0x00, 0x00, 0x04, 0x41, 0x10, 0x00, 0x00, 0x10, 0x55, 0x05, 0x41, 0x10, 0x54, 0x00, 0x55, 0x45, 0x10, 0x11, 0x11, 0x01, 0x40, 0x55, 0x54, 0x10, 0x11, 0x11, 0x00, 0x10, 0x55, 0x54, 0x15, 0x51, 0x11, 0x41, 0x11, 0x51, 0x10, 0x04, 0x41, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x50, 0x50, 0x00, 0x00, 0x10, 0x01, 0x10, 0x55, 0x50, 0x55, 0x00, 0x55, 0x01, 0x10, 0x44, 0x51, 0x00, 0x51, 0x00, 0x41, 0x10, 0x40, 0x11, 0x04, 0x41, 0x11, 0x41, 0x10, 0x15, 0x41, 0x00, 0x41, 0x00, 0x41, 0x10, 0x10, 0x41, 0x00, 0x40, 0x41, 0x01, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x55, 0x55, 0x55, 0x55, 0x55, 0x41, 0x10, 0x40, 0x00, 0x00, 0x00, 0x00, 0x41, 0x10, 0x55, 0x55, 0x55, 0x55, 0x55, 0x41, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x15, 0x50, 0x00, 0x00, 0x00, 0x01, 0x55, 0x12, 0x0c, 0x57, 0xf5, 0x7d, 0x55, 0x50, 0x5f, 0xfd, 0xff, 0x55, 0x50, 0x5f, 0xff, 0xff, 0x55, 0x50, 0x5f, 0xff, 0xff, 0xd5, 0x50, 0x7c, 0x00, 0x00, 0xd5, 0x50, 0x70, 0x0f, 0xc3, 0xd5, 0x50, 0x70, 0x33, 0xc3, 0xd5, 0x50, 0x70, 0x33, 0xc3, 0xd5, 0x50, 0x70, 0x0f, 0xc3, 0xd5, 0x50, 0x5c, 0x00, 0x0f, 0x55, 0x50, 0x57, 0xff, 0xfd, 0x55, 0x50, 0x5c, 0x3c, 0x33, 0x55, 0x50, 0x12, 0x0c, 0x55, 0xfd, 0x5f, 0x55, 0x50, 0x57, 0xff, 0x7f, 0xd5, 0x50, 0x57, 0xff, 0xff, 0xd5, 0x50, 0x57, 0xff, 0xff, 0xf5, 0x50, 0x5f, 0x00, 0x00, 0x35, 0x50, 0x5c, 0x03, 0xc0, 0x35, 0x50, 0x5c, 0x0c, 0x30, 0xf5, 0x50, 0x5c, 0x00, 0x00, 0x35, 0x50, 0x5c, 0x0c, 0x0f, 0xf5, 0x50, 0x57, 0x33, 0x0f, 0xd5, 0x50, 0x55, 0xf3, 0xff, 0x35, 0x50, 0x55, 0xc3, 0xc3, 0xf5, 0x50, 0x12, 0x0c, 0x5f, 0xd5, 0x7f, 0xff, 0xf0, 0x7f, 0xf5, 0xff, 0x00, 0x30, 0x7f, 0xff, 0xff, 0x00, 0x30, 0x7f, 0xff, 0xff, 0x00, 0x30, 0x70, 0x00, 0x03, 0x00, 0x30, 0xc3, 0xf0, 0x3f, 0x00, 0x30, 0xcc, 0xf0, 0xcf, 0x00, 0x30, 0xcc, 0xf0, 0xcf, 0x00, 0x30, 0xc3, 0xf0, 0x3f, 0xff, 0xf0, 0x70, 0x0f, 0x00, 0xcd, 0x50, 0x5f, 0xff, 0xff, 0x35, 0x50, 0x70, 0x30, 0x3c, 0xd5, 0x50, 0x12, 0x0c, 0x55, 0xfd, 0x57, 0xd5, 0x50, 0x57, 0xff, 0xdf, 0xf5, 0x50, 0x57, 0xff, 0xff, 0xfd, 0x50, 0x55, 0xff, 0xff, 0xfd, 0x50, 0x57, 0xc0, 0x00, 0x0d, 0x50, 0x57, 0x00, 0x00, 0x0d, 0x50, 0x57, 0x00, 0x00, 0x0d, 0x50, 0x57, 0x0f, 0xf0, 0x0d, 0x50, 0x57, 0x00, 0x00, 0xcd, 0x50, 0x55, 0xc0, 0x03, 0x35, 0x50, 0x55, 0x7f, 0xff, 0xd5, 0x50, 0x55, 0xc3, 0xc3, 0xd5, 0x50, 0x12, 0x0c, 0x57, 0xf5, 0x5f, 0xd5, 0x50, 0x5f, 0xfd, 0x7f, 0xf5, 0x50, 0x5f, 0xff, 0xff, 0xf5, 0x50, 0x5f, 0xff, 0xff, 0xf5, 0x50, 0x5c, 0x00, 0x00, 0x35, 0x50, 0x70, 0x00, 0x00, 0x0d, 0x50, 0x70, 0x30, 0x0c, 0x0d, 0x50, 0x70, 0xc0, 0x03, 0x0d, 0x50, 0x70, 0x03, 0xc0, 0x0d, 0x50, 0x5c, 0x0f, 0xf0, 0x35, 0x50, 0x57, 0xff, 0xff, 0xd5, 0x50, 0x55, 0xcc, 0x33, 0x55, 0x50, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfa, 0xaa, 0xab, 0xc0, 0xff, 0xe5, 0x55, 0x5a, 0xc0, 0xff, 0xe5, 0x55, 0x5a, 0xc0, 0xff, 0x95, 0x55, 0x66, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0xaa, 0xaa, 0xab, 0xc0, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfe, 0xaa, 0xaa, 0xc0, 0xff, 0xfe, 0x55, 0x56, 0xc0, 0xff, 0xfe, 0x55, 0x56, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xea, 0xaa, 0xaa, 0xc0, 0xff, 0xea, 0xaa, 0xaa, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0xaa, 0xaa, 0xab, 0xc0, 0x08, 0x08, 0x7f, 0xf5, 0xff, 0xfd, 0xc3, 0x0d, 0xff, 0xfd, 0xff, 0xfd, 0xfc, 0xfd, 0x7f, 0xf5, 0x77, 0x75, 0x10, 0x03, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xc0, 0x03, 0x03, 0xff, 0xff, 0xff, 0xff, 0x10, 0x03, 0x55, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x03, 0x55, 0x55, 0xff, 0xff, 0x55, 0x08, 0x08, 0x55, 0x75, 0x55, 0x75, 0x55, 0x75, 0x5f, 0x75, 0x70, 0xf5, 0x70, 0xd5, 0x5f, 0x55, 0x55, 0x55, 0x08, 0x08, 0x55, 0x75, 0x55, 0x75, 0x55, 0x75, 0x5f, 0x75, 0x7f, 0xf5, 0x7f, 0xd5, 0x5f, 0x55, 0x55, 0x55, 0x08, 0x08, 0x55, 0xd5, 0x55, 0xf5, 0x55, 0xfd, 0x7d, 0xdd, 0xff, 0xd5, 0xff, 0x55, 0x7d, 0x55, 0x55, 0x55, 0x08, 0x08, 0x5f, 0xfd, 0x5d, 0x5d, 0x5d, 0x5d, 0x5d, 0x5d, 0xfd, 0xfd, 0xfd, 0xfd, 0xf5, 0xf5, 0x55, 0x55, 0x01, 0x01, 0x00, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x7f, 0xfd, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x5f, 0xfd, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x7f, 0xfd, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x5f, 0xfd, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x7f, 0xfd, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0x03, 0x5f, 0xfd, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x08, 0x08, 0x50, 0x05, 0x43, 0xc1, 0x00, 0x00, 0x30, 0xcc, 0x33, 0x0c, 0x00, 0x00, 0x43, 0xc1, 0x50, 0x05, 0x08, 0x08, 0xc0, 0x03, 0x33, 0xcc, 0x00, 0x30, 0x33, 0x0c, 0x30, 0xcc, 0x0c, 0x00, 0x33, 0xcc, 0xc0, 0x03, 0x08, 0x08, 0x57, 0xd5, 0x5c, 0x35, 0x5c, 0x35, 0xdc, 0x37, 0xd7, 0xd7, 0xdf, 0xf7, 0xfd, 0x7f, 0xf7, 0xdf, 0x04, 0x1f, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x02, 0x05, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0x06, 0x20, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0x20, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf7, 0xff, 0x5f, 0x5f, 0xd7, 0xff, 0x75, 0x5d, 0x55, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x57, 0xd5, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x55, 0x75, 0x75, 0x7f, 0xdf, 0xd5, 0x75, 0x75, 0x55, 0x75, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x55, 0x5f, 0xd5, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x08, 0x7f, 0x5f, 0x57, 0xd7, 0x57, 0xd5, 0x75, 0xdd, 0x77, 0x57, 0xdf, 0x75, 0xdd, 0x77, 0x57, 0xd7, 0x75, 0xdf, 0xf7, 0x55, 0x7d, 0x5f, 0x5d, 0x77, 0xf7, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x0c, 0x7f, 0x5f, 0x5d, 0x5d, 0xfd, 0xd5, 0x75, 0xdf, 0x7d, 0xd5, 0xdf, 0x75, 0xdf, 0xfd, 0xfd, 0xd7, 0x7f, 0xdd, 0xdd, 0xd5, 0x7f, 0x75, 0xdd, 0x5d, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7d, 0x75, 0x77, 0xf7, 0xf5, 0xd7, 0x75, 0x77, 0x57, 0x5d, 0xd7, 0x5d, 0xd7, 0xf7, 0x5d, 0xd7, 0x5d, 0xd7, 0x57, 0xf5, 0x7d, 0x57, 0x57, 0xf7, 0x5d, 0x55, 0x55, 0x55, 0x55, 0x55, 0x20, 0x0c, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xff, 0x55, 0xc3, 0x7d, 0x55, 0x55, 0x55, 0x70, 0x00, 0xd5, 0x70, 0xff, 0x55, 0x55, 0x55, 0xc0, 0x00, 0x35, 0x7c, 0x3f, 0xd5, 0x55, 0x57, 0x00, 0x03, 0x0d, 0x5f, 0xff, 0xff, 0xff, 0xfc, 0x03, 0x00, 0x0d, 0x70, 0x00, 0x03, 0xc0, 0x00, 0x00, 0x3f, 0xfd, 0x7f, 0xff, 0xfc, 0x30, 0x00, 0x00, 0xc0, 0x03, 0xc0, 0x00, 0x03, 0x30, 0x00, 0x03, 0x0f, 0xfc, 0xc0, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc0, 0x03, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x01, 0x01, 0x00, 0x10, 0x10, 0x55, 0x7d, 0x55, 0xf5, 0x55, 0xc3, 0x57, 0x0d, 0x55, 0xc0, 0xdc, 0x0d, 0x55, 0x70, 0xdc, 0x3d, 0x55, 0x5c, 0x30, 0x35, 0x55, 0x70, 0x00, 0xd5, 0x55, 0xc3, 0xfc, 0xd5, 0x55, 0xcf, 0xff, 0x35, 0x57, 0x0f, 0xff, 0x35, 0x57, 0x00, 0xfc, 0x35, 0x57, 0xc0 };\r\n//uint8_t v[] = { 0x0a, 0xaa, 0x55, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x55, 0x03, 0x03, 0x03, 0x00, 0x00, 0x10, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0xc4, 0x00, 0x00, 0xdc, 0x00, 0x00, 0x0f, 0x01, 0x00, 0x91, 0x01, 0x00, 0x0d, 0x02, 0x00, 0x89, 0x02, 0x00, 0xd1, 0x02, 0x00, 0x1f, 0x06, 0x00, 0x67, 0x0f, 0x00, 0x67, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x12, 0x00, 0xa7, 0x12, 0x00, 0x0d, 0x13, 0x00, 0x73, 0x13, 0x00, 0xd9, 0x13, 0x00, 0x3f, 0x14, 0x00, 0xa5, 0x14, 0x00, 0x0b, 0x15, 0x00, 0x71, 0x15, 0x00, 0xd7, 0x15, 0x00, 0x3d, 0x16, 0x00, 0xa3, 0x16, 0x00, 0x09, 0x17, 0x00, 0x6f, 0x17, 0x00, 0xd5, 0x17, 0x00, 0x3b, 0x18, 0x00, 0xa1, 0x18, 0x00, 0x07, 0x19, 0x00, 0x6d, 0x19, 0x00, 0xd3, 0x19, 0x00, 0x39, 0x1a, 0x00, 0x9f, 0x1a, 0x00, 0x05, 0x1b, 0x00, 0x6b, 0x1b, 0x00, 0xd1, 0x1b, 0x00, 0x37, 0x1c, 0x00, 0x9d, 0x1c, 0x00, 0x13, 0x1e, 0x00, 0x89, 0x1f, 0x00, 0xff, 0x20, 0x00, 0x75, 0x22, 0x00, 0xeb, 0x23, 0x00, 0x61, 0x25, 0x00, 0xd7, 0x26, 0x00, 0x4d, 0x28, 0x00, 0xeb, 0x28, 0x00, 0x89, 0x29, 0x00, 0x64, 0x2a, 0x00, 0xa2, 0x2a, 0x00, 0xe0, 0x2a, 0x00, 0x1e, 0x2b, 0x00, 0x5c, 0x2b, 0x00, 0xce, 0x00, 0x00, 0xf1, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x44, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};// 0x70, 0x2c, 0x00, 0x82, 0x2c, 0x00, 0x90, 0x2c, 0x00, 0x9e, 0x2c, 0x00, 0xb0, 0x2c, 0x00, 0xc2, 0x2c, 0x00, 0xd4, 0x2c, 0x00, 0xe6, 0x2c, 0x00, 0xe9, 0x2c, 0x00, 0x1b, 0x2d, 0x00, 0x4d, 0x2d, 0x00, 0x7f, 0x2d, 0x00, 0xb1, 0x2d, 0x00, 0xe3, 0x2d, 0x00, 0x15, 0x2e, 0x00, 0x27, 0x2e, 0x00, 0x39, 0x2e, 0x00, 0x4b, 0x2e, 0x00, 0x6c, 0x2e, 0x00, 0x73, 0x2e, 0x00, 0xb5, 0x2e, 0x00, 0xf7, 0x2e, 0x00, 0x21, 0x2f, 0x00, 0x5f, 0x2f, 0x00, 0xc1, 0x2f, 0x00, 0x02, 0x00, 0x06, 0x03, 0x04, 0x09, 0x0a, 0x05, 0x08, 0x07, 0x00, 0x00, 0x58, 0x00, 0x00, 0x32, 0x00, 0x00, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x10, 0x00, 0x00, 0x08, 0x00, 0x00, 0x50, 0x04, 0x00, 0x30, 0x02, 0x00, 0x20, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00, 0x50, 0x08, 0x00, 0x50, 0x11, 0x00, 0x00, 0x00, 0x28, 0x00, 0x40, 0x15, 0x00, 0x60, 0x12, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x45, 0x00, 0x00, 0x35, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x22, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00, 0x22, 0x00, 0x00, 0x13, 0x00, 0x01, 0x00, 0x02, 0x00, 0x50, 0x01, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x04, 0xff, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x02, 0xff, 0x01, 0x01, 0x00, 0x1e, 0x01, 0x00, 0x03, 0xff, 0x01, 0x01, 0x00, 0x2d, 0x01, 0x00, 0x04, 0xfe, 0x01, 0x01, 0x00, 0x3c, 0x01, 0x00, 0x05, 0xfe, 0x01, 0x01, 0x00, 0x4b, 0x02, 0x00, 0x06, 0xfe, 0x02, 0x02, 0x00, 0x5a, 0x02, 0x00, 0x07, 0xfd, 0x02, 0x02, 0x00, 0x63, 0x02, 0x00, 0x08, 0xfd, 0x02, 0x02, 0x00, 0x64, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0x00, 0x02, 0x04, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x02, 0xff, 0x01, 0x01, 0x00, 0x0f, 0x01, 0x00, 0x03, 0xff, 0x01, 0x01, 0x00, 0x19, 0x01, 0x00, 0x04, 0xfe, 0x01, 0x01, 0x00, 0x23, 0x01, 0x00, 0x05, 0xfe, 0x01, 0x02, 0x00, 0x2d, 0x02, 0x00, 0x06, 0xfe, 0x02, 0x02, 0x00, 0x37, 0x02, 0x00, 0x07, 0xfd, 0x02, 0x02, 0x00, 0x40, 0x02, 0x00, 0x08, 0xfd, 0x02, 0x02, 0x00, 0x41, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xc4, 0x2f, 0x00, 0xff, 0xff, 0xff, 0x06, 0x30, 0x00, 0x48, 0x30, 0x00, 0x8a, 0x30, 0x00, 0xcc, 0x30, 0x00, 0x0e, 0x31, 0x00, 0x50, 0x31, 0x00, 0x92, 0x31, 0x00, 0xd4, 0x31, 0x00, 0x16, 0x32, 0x00, 0xff, 0xff, 0xff, 0x58, 0x32, 0x00, 0xff, 0xff, 0xff, 0xba, 0x32, 0x00, 0x1c, 0x33, 0x00, 0x7e, 0x33, 0x00, 0xe0, 0x33, 0x00, 0x42, 0x34, 0x00, 0xa4, 0x34, 0x00, 0x06, 0x35, 0x00, 0x68, 0x35, 0x00, 0xca, 0x35, 0x00, 0xff, 0xff, 0xff, 0x2c, 0x36, 0x00, 0x3e, 0x36, 0x00, 0x80, 0x36, 0x00, 0xc2, 0x36, 0x00, 0x04, 0x37, 0x00, 0x46, 0x37, 0x00, 0x88, 0x37, 0x00, 0xca, 0x37, 0x00, 0x24, 0x38, 0x00, 0x9d, 0x38, 0x00, 0xf9, 0x38, 0x00, 0x7d, 0x39, 0x00, 0xd7, 0x39, 0x00, 0x50, 0x3a, 0x00, 0xac, 0x3a, 0x00, 0x30, 0x3b, 0x00, 0x72, 0x3b, 0x00, 0xb4, 0x3b, 0x00, 0xf6, 0x3b, 0x00, 0x38, 0x3c, 0x00, 0x7a, 0x3c, 0x00, 0xbc, 0x3c, 0x00, 0xfe, 0x3c, 0x00, 0x40, 0x3d, 0x00, 0x3a, 0x3e, 0x00, 0x34, 0x3f, 0x00, 0x2e, 0x40, 0x00, 0x28, 0x41, 0x00, 0x22, 0x42, 0x00, 0x98, 0x43, 0x00, 0xea, 0x43, 0x00, 0x3c, 0x44, 0x00, 0x8e, 0x44, 0x00, 0xe0, 0x44, 0x00, 0x32, 0x45, 0x00, 0x84, 0x45, 0x00, 0x7e, 0x46, 0x00, 0x78, 0x47, 0x00, 0xba, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0x76, 0x48, 0x00, 0xf0, 0x48, 0x00, 0x6a, 0x49, 0x00, 0xe4, 0x49, 0x00, 0x5e, 0x4a, 0x00, 0xd8, 0x4a, 0x00, 0x52, 0x4b, 0x00, 0xcc, 0x4b, 0x00, 0x46, 0x4c, 0x00, 0xc0, 0x4c, 0x00, 0x3a, 0x4d, 0x00, 0xb4, 0x4d, 0x00, 0x2e, 0x4e, 0x00, 0xa8, 0x4e, 0x00, 0x22, 0x4f, 0x00, 0x9c, 0x4f, 0x00, 0x16, 0x50, 0x00, 0x90, 0x50, 0x00, 0x0a, 0x51, 0x00, 0x84, 0x51, 0x00, 0xfe, 0x51, 0x00, 0x78, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0x6c, 0x53, 0x00, 0xe6, 0x53, 0x00, 0x60, 0x54, 0x00, 0xda, 0x54, 0x00, 0x54, 0x55, 0x00, 0xce, 0x55, 0x00, 0x48, 0x56, 0x00, 0xc2, 0x56, 0x00, 0x3c, 0x57, 0x00, 0xb6, 0x57, 0x00, 0x30, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0x24, 0x59, 0x00, 0x9e, 0x59, 0x00, 0x18, 0x5a, 0x00, 0x92, 0x5a, 0x00, 0x0c, 0x5b, 0x00, 0x86, 0x5b, 0x00, 0x00, 0x5c, 0x00, 0x7a, 0x5c, 0x00, 0xf4, 0x5c, 0x00, 0x6e, 0x5d, 0x00, 0xe8, 0x5d, 0x00, 0x62, 0x5e, 0x00, 0xdc, 0x5e, 0x00, 0x56, 0x5f, 0x00, 0xd0, 0x5f, 0x00, 0x4a, 0x60, 0x00, 0xc4, 0x60, 0x00, 0x3e, 0x61, 0x00, 0xb8, 0x61, 0x00, 0x32, 0x62, 0x00, 0xac, 0x62, 0x00, 0x26, 0x63, 0x00, 0xa0, 0x63, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x94, 0x64, 0x00, 0x0e, 0x65, 0x00, 0x88, 0x65, 0x00, 0x02, 0x66, 0x00, 0x7c, 0x66, 0x00, 0xf6, 0x66, 0x00, 0x70, 0x67, 0x00, 0xea, 0x67, 0x00, 0x64, 0x68, 0x00, 0xde, 0x68, 0x00, 0x58, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0x4c, 0x6a, 0x00, 0xc6, 0x6a, 0x00, 0x40, 0x6b, 0x00, 0xba, 0x6b, 0x00, 0x34, 0x6c, 0x00, 0xae, 0x6c, 0x00, 0x28, 0x6d, 0x00, 0xa2, 0x6d, 0x00, 0x1c, 0x6e, 0x00, 0x96, 0x6e, 0x00, 0x10, 0x6f, 0x00, 0x8a, 0x6f, 0x00, 0x04, 0x70, 0x00, 0x7e, 0x70, 0x00, 0xf8, 0x70, 0x00, 0x72, 0x71, 0x00, 0xec, 0x71, 0x00, 0x66, 0x72, 0x00, 0xe0, 0x72, 0x00, 0x5a, 0x73, 0x00, 0xd4, 0x73, 0x00, 0x4e, 0x74, 0x00, 0xc8, 0x74, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0xbc, 0x75, 0x00, 0x36, 0x76, 0x00, 0xb0, 0x76, 0x00, 0x2a, 0x77, 0x00, 0xa4, 0x77, 0x00, 0x1e, 0x78, 0x00, 0x98, 0x78, 0x00, 0x12, 0x79, 0x00, 0x8c, 0x79, 0x00, 0x06, 0x7a, 0x00, 0x80, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0x74, 0x7b, 0x00, 0xe2, 0x7b, 0x00, 0x50, 0x7c, 0x00, 0xbe, 0x7c, 0x00, 0x2c, 0x7d, 0x00, 0x9a, 0x7d, 0x00, 0x08, 0x7e, 0x00, 0x76, 0x7e, 0x00, 0xe4, 0x7e, 0x00, 0x52, 0x7f, 0x00, 0xc0, 0x7f, 0x00, 0x2e, 0x80, 0x00, 0x9c, 0x80, 0x00, 0x0a, 0x81, 0x00, 0x78, 0x81, 0x00, 0xe6, 0x81, 0x00, 0x54, 0x82, 0x00, 0xc2, 0x82, 0x00, 0x30, 0x83, 0x00, 0x9e, 0x83, 0x00, 0x0c, 0x84, 0x00, 0x7a, 0x84, 0x00, 0xe8, 0x84, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0xc4, 0x85, 0x00, 0x32, 0x86, 0x00, 0xa0, 0x86, 0x00, 0x0e, 0x87, 0x00, 0x7c, 0x87, 0x00, 0xea, 0x87, 0x00, 0x58, 0x88, 0x00, 0xc6, 0x88, 0x00, 0x34, 0x89, 0x00, 0xa2, 0x89, 0x00, 0x10, 0x8a, 0x00, 0x7e, 0x8a, 0x00, 0xec, 0x8a, 0x00, 0x2e, 0x8b, 0x00, 0xac, 0x8b, 0x00, 0x2a, 0x8c, 0x00, 0xa8, 0x8c, 0x00, 0x26, 0x8d, 0x00, 0xa4, 0x8d, 0x00, 0x22, 0x8e, 0x00, 0xa0, 0x8e, 0x00, 0x1e, 0x8f, 0x00, 0x60, 0x8f, 0x00, 0xa2, 0x8f, 0x00, 0xe4, 0x8f, 0x00, 0x13, 0x90, 0x00, 0x42, 0x90, 0x00, 0x65, 0x90, 0x00, 0x88, 0x90, 0x00, 0xab, 0x90, 0x00, 0xce, 0x90, 0x00, 0xf1, 0x90, 0x00, 0x57, 0x91, 0x00, 0xbd, 0x91, 0x00, 0x23, 0x92, 0x00, 0x89, 0x92, 0x00, 0xef, 0x92, 0x00, 0x55, 0x93, 0x00, 0xbb, 0x93, 0x00, 0x21, 0x94, 0x00, 0x87, 0x94, 0x00, 0xed, 0x94, 0x00, 0x53, 0x95, 0x00, 0xb9, 0x95, 0x00, 0x1f, 0x96, 0x00, 0x85, 0x96, 0x00, 0xeb, 0x96, 0x00, 0x51, 0x97, 0x00, 0xb7, 0x97, 0x00, 0x1d, 0x98, 0x00, 0x83, 0x98, 0x00, 0xe9, 0x98, 0x00, 0x4f, 0x99, 0x00, 0xb5, 0x99, 0x00, 0x1b, 0x9a, 0x00, 0x81, 0x9a, 0x00, 0xe7, 0x9a, 0x00, 0x4d, 0x9b, 0x00, 0xb3, 0x9b, 0x00, 0x19, 0x9c, 0x00, 0x7f, 0x9c, 0x00, 0xe5, 0x9c, 0x00, 0x4b, 0x9d, 0x00, 0xb1, 0x9d, 0x00, 0x17, 0x9e, 0x00, 0x7d, 0x9e, 0x00, 0xe3, 0x9e, 0x00, 0x49, 0x9f, 0x00, 0xaf, 0x9f, 0x00, 0x15, 0xa0, 0x00, 0x7b, 0xa0, 0x00, 0xe1, 0xa0, 0x00, 0x47, 0xa1, 0x00, 0xad, 0xa1, 0x00, 0x13, 0xa2, 0x00, 0x79, 0xa2, 0x00, 0xdf, 0xa2, 0x00, 0x45, 0xa3, 0x00, 0xab, 0xa3, 0x00, 0x11, 0xa4, 0x00, 0x77, 0xa4, 0x00, 0xdd, 0xa4, 0x00, 0x43, 0xa5, 0x00, 0xa9, 0xa5, 0x00, 0x0f, 0xa6, 0x00, 0x75, 0xa6, 0x00, 0xdb, 0xa6, 0x00, 0x41, 0xa7, 0x00, 0xa7, 0xa7, 0x00, 0x0d, 0xa8, 0x00, 0x73, 0xa8, 0x00, 0xd9, 0xa8, 0x00, 0x3f, 0xa9, 0x00, 0xa5, 0xa9, 0x00, 0x0b, 0xaa, 0x00, 0x71, 0xaa, 0x00, 0xd7, 0xaa, 0x00, 0x3d, 0xab, 0x00, 0xa3, 0xab, 0x00, 0x09, 0xac, 0x00, 0x6f, 0xac, 0x00, 0xd5, 0xac, 0x00, 0x3b, 0xad, 0x00, 0xa1, 0xad, 0x00, 0x07, 0xae, 0x00, 0x6d, 0xae, 0x00, 0xd3, 0xae, 0x00, 0x39, 0xaf, 0x00, 0x9f, 0xaf, 0x00, 0x05, 0xb0, 0x00, 0x6b, 0xb0, 0x00, 0xd1, 0xb0, 0x00, 0x37, 0xb1, 0x00, 0x9d, 0xb1, 0x00, 0x03, 0xb2, 0x00, 0x69, 0xb2, 0x00, 0xcf, 0xb2, 0x00, 0x35, 0xb3, 0x00, 0x9b, 0xb3, 0x00, 0x01, 0xb4, 0x00, 0x67, 0xb4, 0x00, 0xcd, 0xb4, 0x00, 0x33, 0xb5, 0x00, 0x99, 0xb5, 0x00, 0xff, 0xb5, 0x00, 0x65, 0xb6, 0x00, 0xcb, 0xb6, 0x00, 0x31, 0xb7, 0x00, 0x97, 0xb7, 0x00, 0xfd, 0xb7, 0x00, 0x63, 0xb8, 0x00, 0xc9, 0xb8, 0x00, 0x2f, 0xb9, 0x00, 0x95, 0xb9, 0x00, 0xfb, 0xb9, 0x00, 0x61, 0xba, 0x00, 0xc7, 0xba, 0x00, 0x2d, 0xbb, 0x00, 0x93, 0xbb, 0x00, 0xf9, 0xbb, 0x00, 0x5f, 0xbc, 0x00, 0xc5, 0xbc, 0x00, 0x2b, 0xbd, 0x00, 0x91, 0xbd, 0x00, 0xf7, 0xbd, 0x00, 0x5d, 0xbe, 0x00, 0xc3, 0xbe, 0x00, 0x29, 0xbf, 0x00, 0x8f, 0xbf, 0x00, 0xf5, 0xbf, 0x00, 0x5b, 0xc0, 0x00, 0xc1, 0xc0, 0x00, 0x27, 0xc1, 0x00, 0x8d, 0xc1, 0x00, 0xf3, 0xc1, 0x00, 0x59, 0xc2, 0x00, 0xbf, 0xc2, 0x00, 0x25, 0xc3, 0x00, 0x8b, 0xc3, 0x00, 0xf1, 0xc3, 0x00, 0x57, 0xc4, 0x00, 0xbd, 0xc4, 0x00, 0x23, 0xc5, 0x00, 0x89, 0xc5, 0x00, 0xef, 0xc5, 0x00, 0x55, 0xc6, 0x00, 0xbb, 0xc6, 0x00, 0x21, 0xc7, 0x00, 0x87, 0xc7, 0x00, 0xed, 0xc7, 0x00, 0x53, 0xc8, 0x00, 0xb9, 0xc8, 0x00, 0x1f, 0xc9, 0x00, 0x85, 0xc9, 0x00, 0xeb, 0xc9, 0x00, 0x51, 0xca, 0x00, 0xb7, 0xca, 0x00, 0x1d, 0xcb, 0x00, 0x83, 0xcb, 0x00, 0xe9, 0xcb, 0x00, 0x4f, 0xcc, 0x00, 0xb5, 0xcc, 0x00, 0x1b, 0xcd, 0x00, 0x81, 0xcd, 0x00, 0xe7, 0xcd, 0x00, 0x4d, 0xce, 0x00, 0xb3, 0xce, 0x00, 0x19, 0xcf, 0x00, 0x7f, 0xcf, 0x00, 0xe5, 0xcf, 0x00, 0x4b, 0xd0, 0x00, 0xb1, 0xd0, 0x00, 0x17, 0xd1, 0x00, 0x7d, 0xd1, 0x00, 0xe3, 0xd1, 0x00, 0x49, 0xd2, 0x00, 0xaf, 0xd2, 0x00, 0x15, 0xd3, 0x00, 0x7b, 0xd3, 0x00, 0xe1, 0xd3, 0x00, 0x47, 0xd4, 0x00, 0xad, 0xd4, 0x00, 0x13, 0xd5, 0x00, 0x79, 0xd5, 0x00, 0xdf, 0xd5, 0x00, 0x45, 0xd6, 0x00, 0xab, 0xd6, 0x00, 0x11, 0xd7, 0x00, 0x77, 0xd7, 0x00, 0xdd, 0xd7, 0x00, 0x43, 0xd8, 0x00, 0xa9, 0xd8, 0x00, 0x0f, 0xd9, 0x00, 0x75, 0xd9, 0x00, 0xdb, 0xd9, 0x00, 0x41, 0xda, 0x00, 0xa7, 0xda, 0x00, 0x0d, 0xdb, 0x00, 0x73, 0xdb, 0x00, 0xd9, 0xdb, 0x00, 0x3f, 0xdc, 0x00, 0xa5, 0xdc, 0x00, 0x0b, 0xdd, 0x00, 0x71, 0xdd, 0x00, 0xd7, 0xdd, 0x00, 0x3d, 0xde, 0x00, 0xa3, 0xde, 0x00, 0x09, 0xdf, 0x00, 0x6f, 0xdf, 0x00, 0xd5, 0xdf, 0x00, 0x3b, 0xe0, 0x00, 0xa1, 0xe0, 0x00, 0x07, 0xe1, 0x00, 0x6d, 0xe1, 0x00, 0xd3, 0xe1, 0x00, 0x39, 0xe2, 0x00, 0x9f, 0xe2, 0x00, 0x05, 0xe3, 0x00, 0x6b, 0xe3, 0x00, 0xd1, 0xe3, 0x00, 0x37, 0xe4, 0x00, 0x9d, 0xe4, 0x00, 0x03, 0xe5, 0x00, 0x69, 0xe5, 0x00, 0xcf, 0xe5, 0x00, 0x35, 0xe6, 0x00, 0x9b, 0xe6, 0x00, 0x01, 0xe7, 0x00, 0x67, 0xe7, 0x00, 0xcd, 0xe7, 0x00, 0x33, 0xe8, 0x00, 0x99, 0xe8, 0x00, 0xff, 0xe8, 0x00, 0x65, 0xe9, 0x00, 0xcb, 0xe9, 0x00, 0x31, 0xea, 0x00, 0x97, 0xea, 0x00, 0xfd, 0xea, 0x00, 0x63, 0xeb, 0x00, 0xc9, 0xeb, 0x00, 0x2f, 0xec, 0x00, 0x95, 0xec, 0x00, 0xfb, 0xec, 0x00, 0x61, 0xed, 0x00, 0xc7, 0xed, 0x00, 0x2d, 0xee, 0x00, 0x93, 0xee, 0x00, 0xf9, 0xee, 0x00, 0x5f, 0xef, 0x00, 0xc5, 0xef, 0x00, 0x2b, 0xf0, 0x00, 0x91, 0xf0, 0x00, 0xf7, 0xf0, 0x00, 0x5d, 0xf1, 0x00, 0xc3, 0xf1, 0x00, 0x29, 0xf2, 0x00, 0x8f, 0xf2, 0x00, 0xf5, 0xf2, 0x00, 0x5b, 0xf3, 0x00, 0xc1, 0xf3, 0x00, 0x27, 0xf4, 0x00, 0x8d, 0xf4, 0x00, 0xf3, 0xf4, 0x00, 0x59, 0xf5, 0x00, 0xbf, 0xf5, 0x00, 0x25, 0xf6, 0x00, 0x8b, 0xf6, 0x00, 0xf1, 0xf6, 0x00, 0x57, 0xf7, 0x00, 0xbd, 0xf7, 0x00, 0x23, 0xf8, 0x00, 0x89, 0xf8, 0x00, 0xef, 0xf8, 0x00, 0x55, 0xf9, 0x00, 0xbb, 0xf9, 0x00, 0x21, 0xfa, 0x00, 0x87, 0xfa, 0x00, 0xed, 0xfa, 0x00, 0x53, 0xfb, 0x00, 0xb9, 0xfb, 0x00, 0x1f, 0xfc, 0x00, 0x85, 0xfc, 0x00, 0xeb, 0xfc, 0x00, 0x51, 0xfd, 0x00, 0xb7, 0xfd, 0x00, 0x1d, 0xfe, 0x00, 0x83, 0xfe, 0x00, 0xe9, 0xfe, 0x00, 0x4f, 0xff, 0x00, 0xb5, 0xff, 0x00, 0x1b, 0x00, 0x01, 0x81, 0x00, 0x01, 0xe7, 0x00, 0x01, 0x4d, 0x01, 0x01, 0xb3, 0x01, 0x01, 0x19, 0x02, 0x01, 0x7f, 0x02, 0x01, 0xe5, 0x02, 0x01, 0x4b, 0x03, 0x01, 0xb1, 0x03, 0x01, 0x17, 0x04, 0x01, 0x7d, 0x04, 0x01, 0xe3, 0x04, 0x01, 0x49, 0x05, 0x01, 0xaf, 0x05, 0x01, 0x15, 0x06, 0x01, 0x7b, 0x06, 0x01, 0xe1, 0x06, 0x01, 0x47, 0x07, 0x01, 0xad, 0x07, 0x01, 0x13, 0x08, 0x01, 0x79, 0x08, 0x01, 0xdf, 0x08, 0x01, 0x45, 0x09, 0x01, 0xab, 0x09, 0x01, 0x11, 0x0a, 0x01, 0x77, 0x0a, 0x01, 0xdd, 0x0a, 0x01, 0x43, 0x0b, 0x01, 0xa9, 0x0b, 0x01, 0x0f, 0x0c, 0x01, 0x75, 0x0c, 0x01, 0xdb, 0x0c, 0x01, 0x41, 0x0d, 0x01, 0xa7, 0x0d, 0x01, 0x0d, 0x0e, 0x01, 0x73, 0x0e, 0x01, 0xd9, 0x0e, 0x01, 0x3f, 0x0f, 0x01, 0xa5, 0x0f, 0x01, 0x0b, 0x10, 0x01, 0x71, 0x10, 0x01, 0xd7, 0x10, 0x01, 0x3d, 0x11, 0x01, 0xa3, 0x11, 0x01, 0x09, 0x12, 0x01, 0x6f, 0x12, 0x01, 0xd5, 0x12, 0x01, 0x3b, 0x13, 0x01, 0xa1, 0x13, 0x01, 0x07, 0x14, 0x01, 0x6d, 0x14, 0x01, 0xd3, 0x14, 0x01, 0x39, 0x15, 0x01, 0x9f, 0x15, 0x01, 0x05, 0x16, 0x01, 0x6b, 0x16, 0x01, 0xd1, 0x16, 0x01, 0x37, 0x17, 0x01, 0x9d, 0x17, 0x01, 0x03, 0x18, 0x01, 0x69, 0x18, 0x01, 0xcf, 0x18, 0x01, 0x35, 0x19, 0x01, 0x9b, 0x19, 0x01, 0x01, 0x1a, 0x01, 0x67, 0x1a, 0x01, 0xcd, 0x1a, 0x01, 0x33, 0x1b, 0x01, 0x99, 0x1b, 0x01, 0xff, 0x1b, 0x01, 0x65, 0x1c, 0x01, 0xcb, 0x1c, 0x01, 0x31, 0x1d, 0x01, 0x97, 0x1d, 0x01, 0xfd, 0x1d, 0x01, 0x63, 0x1e, 0x01, 0xc9, 0x1e, 0x01, 0x2f, 0x1f, 0x01, 0x95, 0x1f, 0x01, 0xfb, 0x1f, 0x01, 0x61, 0x20, 0x01, 0xc7, 0x20, 0x01, 0x2d, 0x21, 0x01, 0x93, 0x21, 0x01, 0xf9, 0x21, 0x01, 0x5f, 0x22, 0x01, 0xc5, 0x22, 0x01, 0x2b, 0x23, 0x01, 0x91, 0x23, 0x01, 0xf7, 0x23, 0x01, 0x5d, 0x24, 0x01, 0xc3, 0x24, 0x01, 0x29, 0x25, 0x01, 0x8f, 0x25, 0x01, 0xf5, 0x25, 0x01, 0x5b, 0x26, 0x01, 0xc1, 0x26, 0x01, 0x27, 0x27, 0x01, 0x8d, 0x27, 0x01, 0xf3, 0x27, 0x01, 0x59, 0x28, 0x01, 0xbf, 0x28, 0x01, 0x25, 0x29, 0x01, 0x8b, 0x29, 0x01, 0xf1, 0x29, 0x01, 0x57, 0x2a, 0x01, 0xbd, 0x2a, 0x01, 0x23, 0x2b, 0x01, 0x89, 0x2b, 0x01, 0xef, 0x2b, 0x01, 0x55, 0x2c, 0x01, 0xbb, 0x2c, 0x01, 0x21, 0x2d, 0x01, 0x87, 0x2d, 0x01, 0xed, 0x2d, 0x01, 0x53, 0x2e, 0x01, 0xb9, 0x2e, 0x01, 0x1f, 0x2f, 0x01, 0x85, 0x2f, 0x01, 0xeb, 0x2f, 0x01, 0x51, 0x30, 0x01, 0xb7, 0x30, 0x01, 0x1d, 0x31, 0x01, 0x83, 0x31, 0x01, 0xe9, 0x31, 0x01, 0x4f, 0x32, 0x01, 0xb5, 0x32, 0x01, 0x1b, 0x33, 0x01, 0x81, 0x33, 0x01, 0xe7, 0x33, 0x01, 0x4d, 0x34, 0x01, 0xb3, 0x34, 0x01, 0x19, 0x35, 0x01, 0x7f, 0x35, 0x01, 0xe5, 0x35, 0x01, 0x4b, 0x36, 0x01, 0xb1, 0x36, 0x01, 0x17, 0x37, 0x01, 0x7d, 0x37, 0x01, 0xe3, 0x37, 0x01, 0x49, 0x38, 0x01, 0xaf, 0x38, 0x01, 0x15, 0x39, 0x01, 0x7b, 0x39, 0x01, 0xe1, 0x39, 0x01, 0x47, 0x3a, 0x01, 0xad, 0x3a, 0x01, 0x13, 0x3b, 0x01, 0x79, 0x3b, 0x01, 0xdf, 0x3b, 0x01, 0x45, 0x3c, 0x01, 0xab, 0x3c, 0x01, 0x11, 0x3d, 0x01, 0x77, 0x3d, 0x01, 0xdd, 0x3d, 0x01, 0x43, 0x3e, 0x01, 0xa9, 0x3e, 0x01, 0x0f, 0x3f, 0x01, 0x75, 0x3f, 0x01, 0xdb, 0x3f, 0x01, 0x41, 0x40, 0x01, 0xa7, 0x40, 0x01, 0x0d, 0x41, 0x01, 0x73, 0x41, 0x01, 0xd9, 0x41, 0x01, 0x3f, 0x42, 0x01, 0xa5, 0x42, 0x01, 0x0b, 0x43, 0x01, 0x71, 0x43, 0x01, 0xd7, 0x43, 0x01, 0x3d, 0x44, 0x01, 0xa3, 0x44, 0x01, 0x09, 0x45, 0x01, 0x6f, 0x45, 0x01, 0xd5, 0x45, 0x01, 0x3b, 0x46, 0x01, 0xa1, 0x46, 0x01, 0x07, 0x47, 0x01, 0x6d, 0x47, 0x01, 0xd3, 0x47, 0x01, 0x39, 0x48, 0x01, 0x9f, 0x48, 0x01, 0x05, 0x49, 0x01, 0x6b, 0x49, 0x01, 0xd1, 0x49, 0x01, 0x37, 0x4a, 0x01, 0x9d, 0x4a, 0x01, 0x03, 0x4b, 0x01, 0x69, 0x4b, 0x01, 0xcf, 0x4b, 0x01, 0x35, 0x4c, 0x01, 0x9b, 0x4c, 0x01, 0x01, 0x4d, 0x01, 0x67, 0x4d, 0x01, 0xcd, 0x4d, 0x01, 0x33, 0x4e, 0x01, 0x99, 0x4e, 0x01, 0xff, 0x4e, 0x01, 0x65, 0x4f, 0x01, 0xcb, 0x4f, 0x01, 0x31, 0x50, 0x01, 0x97, 0x50, 0x01, 0xfd, 0x50, 0x01, 0x63, 0x51, 0x01, 0xc9, 0x51, 0x01, 0x2f, 0x52, 0x01, 0x95, 0x52, 0x01, 0xfb, 0x52, 0x01, 0x61, 0x53, 0x01, 0xc7, 0x53, 0x01, 0x2d, 0x54, 0x01, 0x93, 0x54, 0x01, 0xf9, 0x54, 0x01, 0x5f, 0x55, 0x01, 0xc5, 0x55, 0x01, 0x2b, 0x56, 0x01, 0x91, 0x56, 0x01, 0xf7, 0x56, 0x01, 0x5d, 0x57, 0x01, 0xc3, 0x57, 0x01, 0x29, 0x58, 0x01, 0x8f, 0x58, 0x01, 0xf5, 0x58, 0x01, 0x5b, 0x59, 0x01, 0xc1, 0x59, 0x01, 0x27, 0x5a, 0x01, 0x8d, 0x5a, 0x01, 0xf3, 0x5a, 0x01, 0x59, 0x5b, 0x01, 0xbf, 0x5b, 0x01, 0x25, 0x5c, 0x01, 0x8b, 0x5c, 0x01, 0xf1, 0x5c, 0x01, 0x57, 0x5d, 0x01, 0xbd, 0x5d, 0x01, 0x23, 0x5e, 0x01, 0x89, 0x5e, 0x01, 0xef, 0x5e, 0x01, 0x55, 0x5f, 0x01, 0xbb, 0x5f, 0x01, 0x21, 0x60, 0x01, 0x87, 0x60, 0x01, 0xed, 0x60, 0x01, 0x53, 0x61, 0x01, 0xb9, 0x61, 0x01, 0x1f, 0x62, 0x01, 0x85, 0x62, 0x01, 0xeb, 0x62, 0x01, 0x51, 0x63, 0x01, 0xb7, 0x63, 0x01, 0x1d, 0x64, 0x01, 0x83, 0x64, 0x01, 0xe9, 0x64, 0x01, 0x4f, 0x65, 0x01, 0xb5, 0x65, 0x01, 0x1b, 0x66, 0x01, 0x81, 0x66, 0x01, 0xe7, 0x66, 0x01, 0x4d, 0x67, 0x01, 0xb3, 0x67, 0x01, 0x19, 0x68, 0x01, 0x7f, 0x68, 0x01, 0xe5, 0x68, 0x01, 0x4b, 0x69, 0x01, 0xb1, 0x69, 0x01, 0x17, 0x6a, 0x01, 0x7d, 0x6a, 0x01, 0xe3, 0x6a, 0x01, 0x49, 0x6b, 0x01, 0xaf, 0x6b, 0x01, 0x15, 0x6c, 0x01, 0x7b, 0x6c, 0x01, 0xe1, 0x6c, 0x01, 0x47, 0x6d, 0x01, 0xad, 0x6d, 0x01, 0x13, 0x6e, 0x01, 0x79, 0x6e, 0x01, 0xdf, 0x6e, 0x01, 0x45, 0x6f, 0x01, 0xab, 0x6f, 0x01, 0x11, 0x70, 0x01, 0x77, 0x70, 0x01, 0xdd, 0x70, 0x01, 0x43, 0x71, 0x01, 0xa9, 0x71, 0x01, 0x0f, 0x72, 0x01, 0x75, 0x72, 0x01, 0xdb, 0x72, 0x01, 0x41, 0x73, 0x01, 0xa7, 0x73, 0x01, 0x0d, 0x74, 0x01, 0x73, 0x74, 0x01, 0xd9, 0x74, 0x01, 0x3f, 0x75, 0x01, 0xa5, 0x75, 0x01, 0x0b, 0x76, 0x01, 0x71, 0x76, 0x01, 0xd7, 0x76, 0x01, 0x3d, 0x77, 0x01, 0xa3, 0x77, 0x01, 0x09, 0x78, 0x01, 0x6f, 0x78, 0x01, 0xd5, 0x78, 0x01, 0x3b, 0x79, 0x01, 0xa1, 0x79, 0x01, 0x07, 0x7a, 0x01, 0x6d, 0x7a, 0x01, 0xd3, 0x7a, 0x01, 0x39, 0x7b, 0x01, 0x9f, 0x7b, 0x01, 0x05, 0x7c, 0x01, 0x6b, 0x7c, 0x01, 0xd1, 0x7c, 0x01, 0x37, 0x7d, 0x01, 0x9d, 0x7d, 0x01, 0x03, 0x7e, 0x01, 0x69, 0x7e, 0x01, 0xcf, 0x7e, 0x01, 0x35, 0x7f, 0x01, 0x9b, 0x7f, 0x01, 0x01, 0x80, 0x01, 0x67, 0x80, 0x01, 0xcd, 0x80, 0x01, 0x33, 0x81, 0x01, 0x99, 0x81, 0x01, 0xff, 0x81, 0x01, 0x65, 0x82, 0x01, 0xcb, 0x82, 0x01, 0x31, 0x83, 0x01, 0x97, 0x83, 0x01, 0xfd, 0x83, 0x01, 0x63, 0x84, 0x01, 0xc9, 0x84, 0x01, 0x2f, 0x85, 0x01, 0x95, 0x85, 0x01, 0xfb, 0x85, 0x01, 0x61, 0x86, 0x01, 0xc7, 0x86, 0x01, 0x2d, 0x87, 0x01, 0x93, 0x87, 0x01, 0xf9, 0x87, 0x01, 0x5f, 0x88, 0x01, 0xc5, 0x88, 0x01, 0x2b, 0x89, 0x01, 0x91, 0x89, 0x01, 0xf7, 0x89, 0x01, 0x5d, 0x8a, 0x01, 0xc3, 0x8a, 0x01, 0x29, 0x8b, 0x01, 0x8f, 0x8b, 0x01, 0xf5, 0x8b, 0x01, 0x5b, 0x8c, 0x01, 0xc1, 0x8c, 0x01, 0x27, 0x8d, 0x01, 0x8d, 0x8d, 0x01, 0xf3, 0x8d, 0x01, 0x59, 0x8e, 0x01, 0xbf, 0x8e, 0x01, 0x25, 0x8f, 0x01, 0x8b, 0x8f, 0x01, 0xf1, 0x8f, 0x01, 0x57, 0x90, 0x01, 0xbd, 0x90, 0x01, 0x23, 0x91, 0x01, 0x89, 0x91, 0x01, 0xef, 0x91, 0x01, 0x55, 0x92, 0x01, 0xbb, 0x92, 0x01, 0x21, 0x93, 0x01, 0x87, 0x93, 0x01, 0xed, 0x93, 0x01, 0x53, 0x94, 0x01, 0xb9, 0x94, 0x01, 0x1f, 0x95, 0x01, 0x85, 0x95, 0x01, 0xeb, 0x95, 0x01, 0x51, 0x96, 0x01, 0xb7, 0x96, 0x01, 0x1d, 0x97, 0x01, 0x83, 0x97, 0x01, 0xe9, 0x97, 0x01, 0x4f, 0x98, 0x01, 0xb5, 0x98, 0x01, 0x1b, 0x99, 0x01, 0x81, 0x99, 0x01, 0xe7, 0x99, 0x01, 0x4d, 0x9a, 0x01, 0xb3, 0x9a, 0x01, 0x19, 0x9b, 0x01, 0x7f, 0x9b, 0x01, 0xe5, 0x9b, 0x01, 0x4b, 0x9c, 0x01, 0xb1, 0x9c, 0x01, 0x17, 0x9d, 0x01, 0x7d, 0x9d, 0x01, 0xe3, 0x9d, 0x01, 0x49, 0x9e, 0x01, 0xaf, 0x9e, 0x01, 0x15, 0x9f, 0x01, 0x7b, 0x9f, 0x01, 0xe1, 0x9f, 0x01, 0x47, 0xa0, 0x01, 0xad, 0xa0, 0x01, 0x13, 0xa1, 0x01, 0x79, 0xa1, 0x01, 0xdf, 0xa1, 0x01, 0x45, 0xa2, 0x01, 0xab, 0xa2, 0x01, 0x11, 0xa3, 0x01, 0x77, 0xa3, 0x01, 0xdd, 0xa3, 0x01, 0x43, 0xa4, 0x01, 0xa9, 0xa4, 0x01, 0x0f, 0xa5, 0x01, 0x75, 0xa5, 0x01, 0xdb, 0xa5, 0x01, 0x41, 0xa6, 0x01, 0xa7, 0xa6, 0x01, 0x0d, 0xa7, 0x01, 0x73, 0xa7, 0x01, 0xd9, 0xa7, 0x01, 0x3f, 0xa8, 0x01, 0xa5, 0xa8, 0x01, 0x0b, 0xa9, 0x01, 0x71, 0xa9, 0x01, 0xd7, 0xa9, 0x01, 0x3d, 0xaa, 0x01, 0xa3, 0xaa, 0x01, 0x09, 0xab, 0x01, 0x6f, 0xab, 0x01, 0xd5, 0xab, 0x01, 0x3b, 0xac, 0x01, 0xa1, 0xac, 0x01, 0x07, 0xad, 0x01, 0x6d, 0xad, 0x01, 0xd3, 0xad, 0x01, 0x39, 0xae, 0x01, 0x9f, 0xae, 0x01, 0x05, 0xaf, 0x01, 0x6b, 0xaf, 0x01, 0xd1, 0xaf, 0x01, 0x37, 0xb0, 0x01, 0x9d, 0xb0, 0x01, 0x03, 0xb1, 0x01, 0x69, 0xb1, 0x01, 0xcf, 0xb1, 0x01, 0x35, 0xb2, 0x01, 0x9b, 0xb2, 0x01, 0x01, 0xb3, 0x01, 0x67, 0xb3, 0x01, 0xcd, 0xb3, 0x01, 0x33, 0xb4, 0x01, 0x99, 0xb4, 0x01, 0xff, 0xb4, 0x01, 0x65, 0xb5, 0x01, 0xcb, 0xb5, 0x01, 0x31, 0xb6, 0x01, 0x97, 0xb6, 0x01, 0xfd, 0xb6, 0x01, 0x63, 0xb7, 0x01, 0xc9, 0xb7, 0x01, 0x2f, 0xb8, 0x01, 0x95, 0xb8, 0x01, 0xfb, 0xb8, 0x01, 0x61, 0xb9, 0x01, 0xc7, 0xb9, 0x01, 0x2d, 0xba, 0x01, 0x93, 0xba, 0x01, 0xf9, 0xba, 0x01, 0x5f, 0xbb, 0x01, 0xc5, 0xbb, 0x01, 0x2b, 0xbc, 0x01, 0x91, 0xbc, 0x01, 0xf7, 0xbc, 0x01, 0x5d, 0xbd, 0x01, 0xc3, 0xbd, 0x01, 0x29, 0xbe, 0x01, 0x8f, 0xbe, 0x01, 0xf5, 0xbe, 0x01, 0x5b, 0xbf, 0x01, 0xc1, 0xbf, 0x01, 0x27, 0xc0, 0x01, 0x8d, 0xc0, 0x01, 0xf3, 0xc0, 0x01, 0x59, 0xc1, 0x01, 0xbf, 0xc1, 0x01, 0x25, 0xc2, 0x01, 0x8b, 0xc2, 0x01, 0xf1, 0xc2, 0x01, 0x57, 0xc3, 0x01, 0xbd, 0xc3, 0x01, 0x23, 0xc4, 0x01, 0x89, 0xc4, 0x01, 0xef, 0xc4, 0x01, 0x55, 0xc5, 0x01, 0xbb, 0xc5, 0x01, 0x21, 0xc6, 0x01, 0x87, 0xc6, 0x01, 0xed, 0xc6, 0x01, 0x53, 0xc7, 0x01, 0xb9, 0xc7, 0x01, 0x1f, 0xc8, 0x01, 0x85, 0xc8, 0x01, 0xeb, 0xc8, 0x01, 0x51, 0xc9, 0x01, 0xb7, 0xc9, 0x01, 0x1d, 0xca, 0x01, 0x83, 0xca, 0x01, 0xe9, 0xca, 0x01, 0x4f, 0xcb, 0x01, 0xb5, 0xcb, 0x01, 0x1b, 0xcc, 0x01, 0x1f, 0x04, 0x07, 0x04, 0x04, 0x02, 0x03, 0x10, 0x00, 0x00, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x0a, 0x06, 0x00, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x10, 0x00, 0x00, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x1f, 0x00, 0x08, 0x00, 0x06, 0x00, 0x03, 0x0a, 0x06, 0x00, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x1e, 0x0b, 0x06, 0x04, 0x04, 0x03, 0x04, 0x0c, 0x04, 0x00, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x13, 0xf8, 0x01, 0x87, 0xf9, 0x01, 0x87, 0xf9, 0x01, 0x35, 0xee, 0x01, 0xa9, 0xf2, 0x01, 0xa9, 0xf2, 0x01, 0x35, 0xee, 0x01, 0xa9, 0xf2, 0x01, 0xa9, 0xf2, 0x01, 0x1e, 0x04, 0x0b, 0x04, 0x08, 0x02, 0x06, 0x04, 0x06, 0x06, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x18, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x0a, 0x06, 0x00, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x08, 0x04, 0x04, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0xb7, 0x11, 0x02, 0x21, 0x17, 0x02, 0x09, 0x1d, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x03, 0x05, 0x08, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0x7c, 0x00, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x73, 0x30, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xf0, 0x3c, 0x03, 0x55, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0xff, 0x00, 0x03, 0x55, 0x55, 0xff, 0x00, 0x3d, 0x55, 0x55, 0xff, 0x00, 0xcd, 0x55, 0x55, 0xcf, 0xff, 0x0d, 0x55, 0x55, 0x73, 0x30, 0x3d, 0x55, 0x55, 0x73, 0xf0, 0xf5, 0x55, 0x55, 0x73, 0xf0, 0x35, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x7f, 0x55, 0x57, 0xff, 0x55, 0xff, 0xd5, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x0f, 0x00, 0xf0, 0xd5, 0x57, 0x30, 0xc3, 0x0c, 0xd5, 0x57, 0x00, 0x3c, 0x00, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x57, 0x3f, 0xff, 0xfc, 0xd5, 0x57, 0xf0, 0xc3, 0x0f, 0xd5, 0x55, 0x73, 0xff, 0xcd, 0x55, 0x55, 0xc3, 0xff, 0xc3, 0x55, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x03, 0x00, 0xc0, 0xd5, 0x57, 0x0c, 0x00, 0x30, 0xd5, 0x57, 0x00, 0x3c, 0x00, 0xd5, 0x55, 0xc0, 0xff, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x3f, 0x0f, 0xc3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x00, 0xf0, 0x0d, 0x55, 0x55, 0xff, 0x0f, 0xf5, 0x55, 0x57, 0x33, 0xfc, 0xcd, 0x55, 0x57, 0xf3, 0xfc, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x30, 0x00, 0x0c, 0xd5, 0x57, 0x0c, 0x00, 0x30, 0xd5, 0x57, 0x00, 0xff, 0x00, 0xd5, 0x5f, 0x03, 0xff, 0xc0, 0xf5, 0x5c, 0xc3, 0xff, 0xc3, 0x35, 0x5f, 0x3f, 0xff, 0xfc, 0xf5, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0xc3, 0xff, 0xc3, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x7f, 0x55, 0x57, 0xff, 0x55, 0xff, 0xd5, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x03, 0x00, 0xc0, 0xd5, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x30, 0x3c, 0x0c, 0xd5, 0x55, 0xcc, 0x3c, 0x33, 0xd5, 0x55, 0xcc, 0x3c, 0x33, 0x55, 0x55, 0xc3, 0xc3, 0xc3, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xd7, 0xf5, 0x55, 0x55, 0x5f, 0x55, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x5c, 0x3f, 0xff, 0xc3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x55, 0xff, 0xff, 0xf5, 0x55, 0x55, 0xc0, 0x00, 0x35, 0x55, 0x57, 0x30, 0x00, 0xcd, 0x55, 0x57, 0xf0, 0x00, 0xfd, 0x55, 0x55, 0x70, 0x00, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0x55, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0x70, 0x00, 0x3d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x70, 0x0c, 0xd5, 0x55, 0x57, 0xc0, 0xfc, 0xd5, 0x55, 0x55, 0xf0, 0x3f, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0x57, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0x70, 0x00, 0x3d, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x30, 0xcd, 0x55, 0x55, 0xfc, 0x3f, 0xf5, 0x55, 0x55, 0x70, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x70, 0x3f, 0xf5, 0x55, 0x55, 0xc0, 0x0f, 0xf5, 0x55, 0x7f, 0xc0, 0x0f, 0xf5, 0x5f, 0xc0, 0xc0, 0x0f, 0x55, 0x5f, 0xc0, 0xc0, 0xcf, 0xd5, 0x55, 0xc0, 0xc0, 0xcf, 0xd5, 0x57, 0xc0, 0x3c, 0xcf, 0xf5, 0x5f, 0xfc, 0x03, 0x0f, 0xf5, 0x5f, 0xff, 0xff, 0xf7, 0xd5, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x3c, 0x03, 0xc3, 0x55, 0x5c, 0xc3, 0x0c, 0x33, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0xc3, 0x0c, 0x33, 0x55, 0x57, 0x30, 0xf0, 0xcc, 0xd5, 0x55, 0xff, 0xff, 0xf0, 0xd5, 0x55, 0x73, 0x0c, 0x03, 0x55, 0x55, 0xcc, 0xfc, 0x0d, 0x55, 0x55, 0xfc, 0xff, 0x0d, 0x55, 0x55, 0x5c, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x55, 0xf5, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x00, 0xc3, 0x00, 0xd5, 0x57, 0x3f, 0xc3, 0xfc, 0xd5, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x5c, 0xcc, 0x35, 0x55, 0x55, 0x73, 0xff, 0xcd, 0x55, 0x55, 0x70, 0xfc, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xc0, 0x30, 0x03, 0x55, 0x55, 0xc0, 0xc0, 0x03, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xfc, 0x00, 0x03, 0x55, 0x55, 0xff, 0x03, 0xc3, 0x55, 0x55, 0x7f, 0x03, 0x3d, 0x55, 0x55, 0x5f, 0xff, 0x35, 0x55, 0x55, 0x5c, 0xcc, 0x0d, 0x55, 0x55, 0x57, 0x3c, 0x03, 0x55, 0x55, 0x57, 0x3c, 0x3f, 0x55, 0x55, 0x57, 0xff, 0xf5, 0x55, 0x55, 0x55, 0x7d, 0xfd, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0x7f, 0x55, 0x55, 0x55, 0xff, 0xff, 0xd5, 0x55, 0x55, 0xff, 0xff, 0xd5, 0x55, 0x55, 0xff, 0x00, 0x35, 0x55, 0x57, 0xf0, 0x00, 0x3d, 0x55, 0x57, 0xc0, 0x03, 0x03, 0x55, 0x57, 0x00, 0x3c, 0x03, 0x55, 0x57, 0x00, 0x00, 0x0f, 0x55, 0x57, 0x00, 0x00, 0x35, 0x55, 0x57, 0xc0, 0x03, 0xd5, 0x55, 0x55, 0x7f, 0xff, 0x55, 0x55, 0x55, 0xc0, 0xcf, 0x55, 0x55, 0x57, 0x30, 0xfd, 0x55, 0x55, 0x57, 0xf0, 0xfd, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x7d, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xf5, 0x55, 0x55, 0x5f, 0xfd, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0x00, 0x0d, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x0f, 0xc3, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0x70, 0x00, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x5c, 0x3c, 0xd5, 0x55, 0x55, 0x5f, 0x0f, 0xd5, 0x55, 0x55, 0x5c, 0xff, 0xd5, 0x55, 0x55, 0x70, 0x0f, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3c, 0x0f, 0x55, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0xc0, 0x00, 0xff, 0x55, 0x55, 0xc0, 0xf0, 0xff, 0x55, 0x55, 0x70, 0xcc, 0xfd, 0x55, 0x55, 0x5f, 0xcf, 0xd5, 0x55, 0x55, 0x5c, 0xcc, 0xd5, 0x55, 0x55, 0x5c, 0x3f, 0xd5, 0x55, 0x55, 0x5c, 0x0f, 0xd5, 0x55, 0x55, 0x70, 0x0f, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x55, 0xfd, 0x55, 0x55, 0x7f, 0xdf, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0xc3, 0x55, 0x55, 0xcc, 0x00, 0x03, 0x55, 0x55, 0x73, 0x00, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x73, 0x30, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0x7f, 0x55, 0x55, 0xff, 0xd5, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0xd5, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0x70, 0x00, 0x03, 0x55, 0x55, 0xc3, 0x00, 0x30, 0xd5, 0x55, 0xcc, 0xc0, 0xcc, 0xd5, 0x55, 0xc3, 0x00, 0x30, 0xd5, 0x57, 0xc0, 0x3f, 0x00, 0xd5, 0x57, 0x30, 0xff, 0xc3, 0x55, 0x55, 0xcf, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xc3, 0xfc, 0x03, 0x55, 0x55, 0xc3, 0xfc, 0x3c, 0xd5, 0x55, 0x7f, 0xfc, 0x37, 0xd5, 0x55, 0x5f, 0x7f, 0xd5, 0x55, 0x55, 0x55, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x3c, 0x03, 0xc3, 0x55, 0x5c, 0xf3, 0x0f, 0x33, 0x55, 0x5c, 0xff, 0x0f, 0xf3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x0f, 0xf0, 0x0d, 0x55, 0x55, 0xfc, 0x3f, 0xf5, 0x55, 0x55, 0xc3, 0xcc, 0x3d, 0x55, 0x55, 0x70, 0xfc, 0xf3, 0x55, 0x55, 0x70, 0xfc, 0xdf, 0x55, 0x55, 0x7f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xcd, 0x55, 0x5f, 0xff, 0xff, 0xfd, 0x55, 0x7f, 0xff, 0xff, 0xd5, 0x55, 0x70, 0x00, 0x03, 0xd5, 0x55, 0xff, 0xff, 0xfc, 0xd5, 0x55, 0xc0, 0x00, 0x0f, 0xd5, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0x7c, 0x00, 0x0c, 0xd5, 0x55, 0x5f, 0xff, 0xf0, 0x35, 0x55, 0x7f, 0x3f, 0xfc, 0x0d, 0x55, 0x7f, 0x3f, 0xfc, 0x0d, 0x55, 0x70, 0x00, 0x3c, 0x0d, 0x55, 0x7f, 0xff, 0xf0, 0x0d, 0x55, 0x5f, 0xff, 0xdf, 0xf5, 0x55, 0x7f, 0xdf, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0x55, 0x55, 0x55, 0x57, 0x35, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0xff, 0xff, 0x55, 0x55, 0x5f, 0xff, 0xff, 0x55, 0x55, 0x70, 0x00, 0x0f, 0x55, 0x55, 0x7f, 0xff, 0xf3, 0xfd, 0x55, 0xc0, 0x00, 0x0c, 0xc3, 0x55, 0xc0, 0x00, 0x03, 0xc3, 0x55, 0xc0, 0x00, 0x03, 0x03, 0x55, 0xf0, 0x03, 0x03, 0xc3, 0x55, 0xc3, 0xc0, 0x0f, 0xc3, 0x55, 0xc3, 0xc0, 0x3f, 0x0d, 0x55, 0x7f, 0xff, 0xfc, 0x35, 0x5d, 0xff, 0x3f, 0xf3, 0xd5, 0x5f, 0x00, 0x00, 0xfd, 0x55, 0x5f, 0xff, 0xff, 0x3d, 0x55, 0x55, 0xff, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xff, 0x55, 0x55, 0x7f, 0xff, 0xff, 0xd5, 0x55, 0xf0, 0x00, 0x03, 0xf5, 0x55, 0xcf, 0xff, 0xfc, 0xf5, 0x55, 0xf0, 0x00, 0x03, 0xff, 0x57, 0x0f, 0xc0, 0xfc, 0xf3, 0x57, 0x33, 0xc3, 0x3c, 0xdf, 0x57, 0x33, 0xc3, 0x3c, 0xd5, 0x57, 0x0f, 0xc0, 0xfc, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x35, 0x55, 0xff, 0xff, 0xfc, 0x0d, 0x57, 0xff, 0xcf, 0xf3, 0x0d, 0x5c, 0xff, 0xcf, 0xff, 0x0d, 0x57, 0x70, 0x00, 0x0c, 0x0d, 0x55, 0x7f, 0xff, 0xf7, 0xf5, 0x55, 0x57, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xf7, 0xfd, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xff, 0xf5, 0x55, 0x70, 0x00, 0xff, 0xff, 0x55, 0x7f, 0xfc, 0x03, 0xf3, 0x55, 0xf0, 0xff, 0xf0, 0xdf, 0x55, 0xf0, 0xf3, 0x0f, 0xd5, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xff, 0xf0, 0x33, 0x55, 0x57, 0x3f, 0xc0, 0xff, 0xd5, 0x57, 0xcf, 0xff, 0xfc, 0x35, 0x55, 0xff, 0x3f, 0xfc, 0x0d, 0x55, 0x7f, 0x3f, 0xf0, 0x0d, 0x55, 0x7f, 0x3f, 0xf0, 0x0d, 0x55, 0x70, 0x00, 0xf0, 0x0d, 0x55, 0x5f, 0xff, 0xdf, 0xf5, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x55, 0xf7, 0xd5, 0x55, 0x30, 0x1f, 0x01, 0x55, 0x40, 0x00, 0x00, 0x00, 0x15, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x11, 0x41, 0x50, 0x00, 0x00, 0x15, 0x55, 0x55, 0x54, 0x04, 0x10, 0x01, 0x55, 0x41, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa1, 0x14, 0x15, 0x54, 0x01, 0x11, 0x45, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa5, 0x54, 0x15, 0x54, 0x01, 0x55, 0x45, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa1, 0x14, 0x44, 0x11, 0x55, 0x55, 0x55, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x15, 0x40, 0x01, 0x55, 0x11, 0x56, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x95, 0x40, 0x01, 0x55, 0x55, 0x56, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x95, 0x55, 0x55, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x55, 0x50, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x01, 0x50, 0x55, 0x50, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x15, 0x55, 0x55, 0x54, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x02, 0x55, 0x55, 0x55, 0x00, 0x04, 0x00, 0x80, 0x28, 0x00, 0x00, 0xa0, 0x02, 0x01, 0x15, 0x55, 0x10, 0x04, 0x55, 0x80, 0x28, 0x00, 0x00, 0xa0, 0x02, 0x01, 0x15, 0x55, 0x01, 0x55, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x02, 0x55, 0x55, 0x55, 0x01, 0x01, 0x00, 0x80, 0xaa, 0xaa, 0xaa, 0xa8, 0x02, 0x00, 0x04, 0x01, 0x01, 0x55, 0x00, 0x82, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x04, 0x01, 0x00, 0x41, 0x00, 0x82, 0xaa, 0xaa, 0xaa, 0xaa, 0x02, 0x00, 0x04, 0x01, 0x55, 0x5a, 0xa5, 0x80, 0x95, 0x95, 0x80, 0x00, 0x02, 0x55, 0x54, 0x01, 0x00, 0x25, 0x58, 0x80, 0x95, 0x95, 0x85, 0x54, 0x0a, 0xaa, 0xa8, 0x01, 0x00, 0x26, 0x98, 0x80, 0x95, 0x95, 0x85, 0x54, 0x08, 0x00, 0x09, 0x55, 0x00, 0x25, 0x58, 0x80, 0x95, 0x95, 0xaa, 0xaa, 0x08, 0x88, 0x88, 0x00, 0x00, 0x20, 0x08, 0x95, 0x95, 0x95, 0x80, 0x02, 0x58, 0x88, 0x88, 0x00, 0xaa, 0xa0, 0x0a, 0x95, 0x95, 0x95, 0x80, 0x02, 0x58, 0x00, 0x0a, 0xaa, 0x04, 0x20, 0x08, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa9, 0x55, 0x58, 0x00, 0x00, 0x0a, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xaa, 0xa9, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0x42, 0x82, 0x20, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa6, 0x86, 0x26, 0x62, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x45, 0x86, 0x24, 0xa4, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xa4, 0xa1, 0x61, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x61, 0x40, 0xa2, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0xaa, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa9, 0x55, 0x69, 0x55, 0x6a, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x9a, 0xa9, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x59, 0x59, 0x6a, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x98, 0x49, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x95, 0x55, 0xaa, 0x95, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa5, 0x56, 0xaa, 0x40, 0x68, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa8, 0x0a, 0xa5, 0x55, 0x58, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa9, 0x5a, 0xa5, 0x55, 0x58, 0x00, 0x95, 0x5a, 0x69, 0xa5, 0x56, 0x02, 0xa5, 0x96, 0xa9, 0x69, 0x68, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x96, 0x5a, 0x69, 0xa5, 0x96, 0x54, 0x54, 0x54, 0x54, 0x54, 0x55, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x54, 0x54, 0x54, 0x54, 0x54, 0x55, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x30, 0x1f, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x15, 0x00, 0x00, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x55, 0x00, 0x01, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x40, 0x51, 0x55, 0x55, 0x15, 0x54, 0x00, 0x00, 0x15, 0x54, 0x55, 0x55, 0x45, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x40, 0x00, 0x44, 0x11, 0x10, 0x11, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x44, 0x04, 0x44, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x40, 0x00, 0x44, 0x15, 0x05, 0x41, 0x50, 0x05, 0x55, 0x55, 0x50, 0x05, 0x41, 0x50, 0x54, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x50, 0x40, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x50, 0x40, 0x01, 0x00, 0x01, 0x00, 0x17, 0xfc, 0x3f, 0xfc, 0x00, 0x43, 0xff, 0xc0, 0x01, 0x00, 0x01, 0x00, 0x1f, 0xf4, 0xff, 0xd4, 0x00, 0x4f, 0xfc, 0x40, 0x01, 0x55, 0x55, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x40, 0x01, 0x11, 0x11, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x40, 0x01, 0x00, 0x01, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xc0, 0x01, 0x05, 0x41, 0x00, 0xf0, 0xfc, 0x03, 0xff, 0xff, 0x00, 0x00, 0xc0, 0x01, 0x05, 0x41, 0x00, 0xf0, 0xf3, 0x0c, 0x71, 0xc7, 0x33, 0x30, 0xc0, 0xaa, 0xaa, 0xaa, 0xaa, 0xf0, 0xf3, 0x0d, 0x75, 0xd7, 0x33, 0x30, 0xea, 0x55, 0x55, 0x55, 0x55, 0xf0, 0xfc, 0x0d, 0x34, 0xd3, 0x33, 0x30, 0xd5, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x0d, 0x34, 0xc3, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x03, 0xff, 0xff, 0xaa, 0xaa, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 0xc0, 0x00, 0xfc, 0x0f, 0xc0, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x3a, 0xbf, 0xfa, 0xab, 0xff, 0xbf, 0xfb, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0xff, 0xff, 0xcf, 0xfc, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf0, 0x03, 0xff, 0x3f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xc0, 0x00, 0xfc, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x55, 0x51, 0x55, 0x55, 0x15, 0x54, 0x00, 0x00, 0x15, 0x10, 0x00, 0x00, 0x40, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x40, 0x11, 0x10, 0x11, 0x10, 0x04, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x40, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x15, 0x55, 0x55, 0x40, 0x15, 0x05, 0x41, 0x50, 0x05, 0x55, 0x55, 0x50, 0x00, 0x00, 0x00, 0x00, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf5, 0xff, 0xf0, 0x00, 0x0f, 0xff, 0x00, 0x50, 0x50, 0x50, 0x50, 0x3f, 0xc3, 0xff, 0x00, 0x14, 0x3f, 0xf4, 0x14, 0x55, 0x50, 0x55, 0x50, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x54, 0x55, 0x50, 0x55, 0x50, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x54, 0x55, 0x55, 0x55, 0x53, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x54, 0x40, 0x10, 0x40, 0x13, 0xc3, 0xf0, 0x0f, 0xff, 0xfc, 0x00, 0x03, 0x04, 0x50, 0x50, 0x50, 0x53, 0xc3, 0xcc, 0x31, 0xc7, 0x1c, 0xcc, 0xc3, 0x14, 0x40, 0x10, 0x40, 0x13, 0xc3, 0xcc, 0x35, 0xd7, 0x5c, 0xcc, 0xc3, 0x04, 0xaa, 0xaa, 0xaa, 0xab, 0xc3, 0xf0, 0x34, 0xd3, 0x4c, 0xcc, 0xc3, 0xaa, 0x55, 0x55, 0x55, 0x57, 0x00, 0x00, 0x34, 0xd3, 0x0c, 0x00, 0x03, 0x55, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x0f, 0xff, 0xfe, 0xaa, 0xab, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x3f, 0x00, 0x03, 0xf0, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xea, 0xff, 0xea, 0xaf, 0xfe, 0xff, 0xec, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf3, 0xff, 0xff, 0x3f, 0xf3, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x0f, 0xfc, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x03, 0xf0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xfd, 0x7d, 0x7f, 0x5d, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x5d, 0xd5, 0xd7, 0x75, 0xdd, 0xd5, 0x55, 0x55, 0x55, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x30, 0xcc, 0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0xc0, 0xff, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xc0, 0xc3, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0x3f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xfc, 0x3f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x03, 0xc0, 0x30, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0xf3, 0xff, 0xff, 0xcf, 0x00, 0x00, 0x0f, 0xf0, 0x70, 0x0f, 0x55, 0x55, 0xc3, 0x0c, 0x30, 0xc3, 0x55, 0x55, 0xf0, 0x0d, 0xc3, 0x30, 0xd5, 0xff, 0x7c, 0xcf, 0xf3, 0x3d, 0xff, 0x57, 0x0c, 0xc3, 0xc0, 0x3f, 0x5f, 0x03, 0x57, 0xcf, 0xf3, 0xd5, 0xc0, 0xf5, 0xfc, 0x03, 0xc0, 0x30, 0xdc, 0x0d, 0x5f, 0xff, 0xff, 0xf5, 0x70, 0x37, 0x0c, 0x03, 0x7f, 0xff, 0x5f, 0xf5, 0x5f, 0x55, 0x55, 0xf5, 0x5f, 0xf5, 0xff, 0xfd, 0x30, 0x1f, 0xa4, 0x00, 0xa4, 0x01, 0x90, 0x00, 0x64, 0x06, 0x40, 0x1a, 0x00, 0x16, 0xa9, 0x40, 0x09, 0x00, 0x40, 0x00, 0x10, 0x01, 0x00, 0x60, 0x01, 0x6a, 0x2a, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xaa, 0x00, 0xa5, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x01, 0x6a, 0x80, 0x00, 0x01, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x30, 0xc0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x00, 0x05, 0x94, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x15, 0x56, 0xa5, 0x55, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x15, 0x40, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x29, 0x50, 0x15, 0x68, 0x00, 0x40, 0x07, 0xf0, 0x0f, 0xc0, 0x10, 0x00, 0x0a, 0xa5, 0x6a, 0x80, 0x01, 0x00, 0x1f, 0xfc, 0x3f, 0xf0, 0x04, 0x00, 0x00, 0xaa, 0xa8, 0x00, 0x15, 0x00, 0x1f, 0xff, 0xff, 0xf0, 0x05, 0x40, 0x00, 0x0a, 0xa0, 0x00, 0x04, 0x00, 0x5c, 0x00, 0x00, 0x30, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xf0, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xc0, 0x33, 0x00, 0x00, 0xcc, 0x03, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x30, 0x03, 0xc0, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x0c, 0x30, 0x03, 0xc0, 0x0c, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x3c, 0x03, 0xc0, 0x3c, 0xff, 0xc0, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0xc3, 0xff, 0xff, 0xc3, 0x00, 0x00, 0x0f, 0xf0, 0x30, 0x0c, 0x00, 0x00, 0xcc, 0x30, 0x0c, 0x33, 0x00, 0x00, 0x30, 0x0c, 0xc3, 0x0f, 0x00, 0x00, 0x3f, 0x3f, 0xfc, 0xfc, 0x00, 0x00, 0xf0, 0xc3, 0xc0, 0x30, 0xc0, 0x00, 0x03, 0x3f, 0xfc, 0xc0, 0x00, 0x03, 0x0c, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0xfc, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x3f, 0xfc, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x30, 0x30, 0xc0, 0x00, 0x00, 0x3c, 0x3c, 0x00, 0x00, 0x03, 0x0c, 0x0c, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x0c, 0x30, 0x00, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xfd, 0x7d, 0x7f, 0x5d, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x5d, 0xd5, 0xd7, 0x75, 0xdd, 0xd5, 0x55, 0x55, 0x55, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x30, 0xcc, 0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0xc0, 0xff, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xc0, 0xc3, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x70, 0x0f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xf0, 0x0d, 0xc3, 0x30, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x0c, 0xc3, 0xc0, 0x3f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfc, 0x03, 0xc0, 0x30, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x0c, 0x03, 0x7f, 0xff, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xfd, 0x30, 0x1f, 0xa4, 0x00, 0xa4, 0x01, 0x90, 0x00, 0x64, 0x06, 0x40, 0x1a, 0x00, 0x16, 0xa9, 0x40, 0x09, 0x00, 0x40, 0x00, 0x10, 0x01, 0x00, 0x60, 0x01, 0x6a, 0x2a, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xaa, 0x00, 0xa5, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x01, 0x6a, 0x80, 0x00, 0x01, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x30, 0xc0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x00, 0x05, 0x94, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x15, 0x56, 0xa5, 0x55, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x15, 0x40, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x29, 0x50, 0x15, 0x68, 0x00, 0x40, 0x04, 0x00, 0x04, 0x00, 0x10, 0x00, 0x0a, 0xa5, 0x6a, 0x80, 0x01, 0x00, 0x14, 0x00, 0x05, 0x00, 0x04, 0x00, 0x00, 0xaa, 0xa8, 0x00, 0x15, 0x00, 0x15, 0x00, 0x15, 0x00, 0x05, 0x40, 0x00, 0x0a, 0xa0, 0x00, 0x04, 0x00, 0x54, 0x00, 0x05, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x30, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0c, 0xc3, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xc3, 0xc0, 0x30, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x30, 0x30, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x0c, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xfc, 0x00, 0xc3, 0x0f, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xc3, 0x00, 0xc3, 0x30, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xcc, 0xc3, 0x00, 0xff, 0x30, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xfc, 0x00, 0xc3, 0x30, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xc0, 0x00, 0xc3, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x3f, 0x0f, 0xcf, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0xcc, 0x0c, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0xcf, 0xcf, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0x0f, 0xcf, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x30, 0xcc, 0x33, 0x0c, 0xfc, 0xfc, 0x00, 0x00, 0xc0, 0x00, 0x00, 0xc3, 0x30, 0xcf, 0x33, 0xcc, 0xc0, 0xc3, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc3, 0x30, 0xcc, 0xf3, 0x3c, 0xfc, 0xc3, 0x00, 0x00, 0xfc, 0x00, 0x00, 0xfc, 0x30, 0xcc, 0x33, 0x0c, 0xc0, 0xfc, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc3, 0x0f, 0x0c, 0x33, 0x0c, 0xfc, 0xc3, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x1f, 0x05, 0x55, 0x55, 0x55, 0x55, 0x55, 0x54, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x05, 0x54, 0x55, 0x45, 0x51, 0x10, 0x00, 0x04, 0x04, 0x55, 0x44, 0x51, 0x11, 0x55, 0x44, 0x04, 0x44, 0x44, 0x51, 0x11, 0x00, 0x44, 0x04, 0x44, 0x44, 0x51, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x00, 0x00, 0x00, 0x05, 0x41, 0x10, 0x00, 0x00, 0x00, 0x00, 0x04, 0x41, 0x10, 0x00, 0x00, 0x10, 0x55, 0x05, 0x41, 0x10, 0x54, 0x00, 0x55, 0x45, 0x10, 0x11, 0x11, 0x01, 0x40, 0x55, 0x54, 0x10, 0x11, 0x11, 0x00, 0x10, 0x55, 0x54, 0x15, 0x51, 0x11, 0x41, 0x11, 0x51, 0x10, 0x04, 0x41, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x50, 0x50, 0x00, 0x00, 0x10, 0x01, 0x10, 0x55, 0x50, 0x55, 0x00, 0x55, 0x01, 0x10, 0x44, 0x51, 0x00, 0x51, 0x00, 0x41, 0x10, 0x40, 0x11, 0x04, 0x41, 0x11, 0x41, 0x10, 0x15, 0x41, 0x00, 0x41, 0x00, 0x41, 0x10, 0x10, 0x41, 0x00, 0x40, 0x41, 0x01, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x55, 0x55, 0x55, 0x55, 0x55, 0x41, 0x10, 0x40, 0x00, 0x00, 0x00, 0x00, 0x41, 0x10, 0x55, 0x55, 0x55, 0x55, 0x55, 0x41, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x15, 0x50, 0x00, 0x00, 0x00, 0x01, 0x55, 0x12, 0x0c, 0x57, 0xf5, 0x7d, 0x55, 0x50, 0x5f, 0xfd, 0xff, 0x55, 0x50, 0x5f, 0xff, 0xff, 0x55, 0x50, 0x5f, 0xff, 0xff, 0xd5, 0x50, 0x7c, 0x00, 0x00, 0xd5, 0x50, 0x70, 0x0f, 0xc3, 0xd5, 0x50, 0x70, 0x33, 0xc3, 0xd5, 0x50, 0x70, 0x33, 0xc3, 0xd5, 0x50, 0x70, 0x0f, 0xc3, 0xd5, 0x50, 0x5c, 0x00, 0x0f, 0x55, 0x50, 0x57, 0xff, 0xfd, 0x55, 0x50, 0x5c, 0x3c, 0x33, 0x55, 0x50, 0x12, 0x0c, 0x55, 0xfd, 0x5f, 0x55, 0x50, 0x57, 0xff, 0x7f, 0xd5, 0x50, 0x57, 0xff, 0xff, 0xd5, 0x50, 0x57, 0xff, 0xff, 0xf5, 0x50, 0x5f, 0x00, 0x00, 0x35, 0x50, 0x5c, 0x03, 0xc0, 0x35, 0x50, 0x5c, 0x0c, 0x30, 0xf5, 0x50, 0x5c, 0x00, 0x00, 0x35, 0x50, 0x5c, 0x0c, 0x0f, 0xf5, 0x50, 0x57, 0x33, 0x0f, 0xd5, 0x50, 0x55, 0xf3, 0xff, 0x35, 0x50, 0x55, 0xc3, 0xc3, 0xf5, 0x50, 0x12, 0x0c, 0x5f, 0xd5, 0x7f, 0xff, 0xf0, 0x7f, 0xf5, 0xff, 0x00, 0x30, 0x7f, 0xff, 0xff, 0x00, 0x30, 0x7f, 0xff, 0xff, 0x00, 0x30, 0x70, 0x00, 0x03, 0x00, 0x30, 0xc3, 0xf0, 0x3f, 0x00, 0x30, 0xcc, 0xf0, 0xcf, 0x00, 0x30, 0xcc, 0xf0, 0xcf, 0x00, 0x30, 0xc3, 0xf0, 0x3f, 0xff, 0xf0, 0x70, 0x0f, 0x00, 0xcd, 0x50, 0x5f, 0xff, 0xff, 0x35, 0x50, 0x70, 0x30, 0x3c, 0xd5, 0x50, 0x12, 0x0c, 0x55, 0xfd, 0x57, 0xd5, 0x50, 0x57, 0xff, 0xdf, 0xf5, 0x50, 0x57, 0xff, 0xff, 0xfd, 0x50, 0x55, 0xff, 0xff, 0xfd, 0x50, 0x57, 0xc0, 0x00, 0x0d, 0x50, 0x57, 0x00, 0x00, 0x0d, 0x50, 0x57, 0x00, 0x00, 0x0d, 0x50, 0x57, 0x0f, 0xf0, 0x0d, 0x50, 0x57, 0x00, 0x00, 0xcd, 0x50, 0x55, 0xc0, 0x03, 0x35, 0x50, 0x55, 0x7f, 0xff, 0xd5, 0x50, 0x55, 0xc3, 0xc3, 0xd5, 0x50, 0x12, 0x0c, 0x57, 0xf5, 0x5f, 0xd5, 0x50, 0x5f, 0xfd, 0x7f, 0xf5, 0x50, 0x5f, 0xff, 0xff, 0xf5, 0x50, 0x5f, 0xff, 0xff, 0xf5, 0x50, 0x5c, 0x00, 0x00, 0x35, 0x50, 0x70, 0x00, 0x00, 0x0d, 0x50, 0x70, 0x30, 0x0c, 0x0d, 0x50, 0x70, 0xc0, 0x03, 0x0d, 0x50, 0x70, 0x03, 0xc0, 0x0d, 0x50, 0x5c, 0x0f, 0xf0, 0x35, 0x50, 0x57, 0xff, 0xff, 0xd5, 0x50, 0x55, 0xcc, 0x33, 0x55, 0x50, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfa, 0xaa, 0xab, 0xc0, 0xff, 0xe5, 0x55, 0x5a, 0xc0, 0xff, 0xe5, 0x55, 0x5a, 0xc0, 0xff, 0x95, 0x55, 0x66, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0xaa, 0xaa, 0xab, 0xc0, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfe, 0xaa, 0xaa, 0xc0, 0xff, 0xfe, 0x55, 0x56, 0xc0, 0xff, 0xfe, 0x55, 0x56, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xea, 0xaa, 0xaa, 0xc0, 0xff, 0xea, 0xaa, 0xaa, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0xaa, 0xaa, 0xab, 0xc0, 0x08, 0x08, 0x7f, 0xf5, 0xff, 0xfd, 0xc3, 0x0d, 0xff, 0xfd, 0xff, 0xfd, 0xfc, 0xfd, 0x7f, 0xf5, 0x77, 0x75, 0x10, 0x03, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xc0, 0x03, 0x03, 0xff, 0xff, 0xff, 0xff, 0x10, 0x03, 0x55, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x03, 0x55, 0x55, 0xff, 0xff, 0x55, 0x08, 0x08, 0x55, 0x75, 0x55, 0x75, 0x55, 0x75, 0x5f, 0x75, 0x70, 0xf5, 0x70, 0xd5, 0x5f, 0x55, 0x55, 0x55, 0x08, 0x08, 0x55, 0x75, 0x55, 0x75, 0x55, 0x75, 0x5f, 0x75, 0x7f, 0xf5, 0x7f, 0xd5, 0x5f, 0x55, 0x55, 0x55, 0x08, 0x08, 0x55, 0xd5, 0x55, 0xf5, 0x55, 0xfd, 0x7d, 0xdd, 0xff, 0xd5, 0xff, 0x55, 0x7d, 0x55, 0x55, 0x55, 0x08, 0x08, 0x5f, 0xfd, 0x5d, 0x5d, 0x5d, 0x5d, 0x5d, 0x5d, 0xfd, 0xfd, 0xfd, 0xfd, 0xf5, 0xf5, 0x55, 0x55, 0x01, 0x01, 0x00, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x7f, 0xfd, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x5f, 0xfd, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x7f, 0xfd, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x5f, 0xfd, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x7f, 0xfd, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0x03, 0x5f, 0xfd, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x08, 0x08, 0x50, 0x05, 0x43, 0xc1, 0x00, 0x00, 0x30, 0xcc, 0x33, 0x0c, 0x00, 0x00, 0x43, 0xc1, 0x50, 0x05, 0x08, 0x08, 0xc0, 0x03, 0x33, 0xcc, 0x00, 0x30, 0x33, 0x0c, 0x30, 0xcc, 0x0c, 0x00, 0x33, 0xcc, 0xc0, 0x03, 0x08, 0x08, 0x57, 0xd5, 0x5c, 0x35, 0x5c, 0x35, 0xdc, 0x37, 0xd7, 0xd7, 0xdf, 0xf7, 0xfd, 0x7f, 0xf7, 0xdf, 0x04, 0x1f, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x02, 0x05, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0x06, 0x20, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0x20, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf7, 0xff, 0x5f, 0x5f, 0xd7, 0xff, 0x75, 0x5d, 0x55, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x57, 0xd5, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x55, 0x75, 0x75, 0x7f, 0xdf, 0xd5, 0x75, 0x75, 0x55, 0x75, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x55, 0x5f, 0xd5, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x08, 0x7f, 0x5f, 0x57, 0xd7, 0x57, 0xd5, 0x75, 0xdd, 0x77, 0x57, 0xdf, 0x75, 0xdd, 0x77, 0x57, 0xd7, 0x75, 0xdf, 0xf7, 0x55, 0x7d, 0x5f, 0x5d, 0x77, 0xf7, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x0c, 0x7f, 0x5f, 0x5d, 0x5d, 0xfd, 0xd5, 0x75, 0xdf, 0x7d, 0xd5, 0xdf, 0x75, 0xdf, 0xfd, 0xfd, 0xd7, 0x7f, 0xdd, 0xdd, 0xd5, 0x7f, 0x75, 0xdd, 0x5d, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7d, 0x75, 0x77, 0xf7, 0xf5, 0xd7, 0x75, 0x77, 0x57, 0x5d, 0xd7, 0x5d, 0xd7, 0xf7, 0x5d, 0xd7, 0x5d, 0xd7, 0x57, 0xf5, 0x7d, 0x57, 0x57, 0xf7, 0x5d, 0x55, 0x55, 0x55, 0x55, 0x55, 0x20, 0x0c, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xff, 0x55, 0xc3, 0x7d, 0x55, 0x55, 0x55, 0x70, 0x00, 0xd5, 0x70, 0xff, 0x55, 0x55, 0x55, 0xc0, 0x00, 0x35, 0x7c, 0x3f, 0xd5, 0x55, 0x57, 0x00, 0x03, 0x0d, 0x5f, 0xff, 0xff, 0xff, 0xfc, 0x03, 0x00, 0x0d, 0x70, 0x00, 0x03, 0xc0, 0x00, 0x00, 0x3f, 0xfd, 0x7f, 0xff, 0xfc, 0x30, 0x00, 0x00, 0xc0, 0x03, 0xc0, 0x00, 0x03, 0x30, 0x00, 0x03, 0x0f, 0xfc, 0xc0, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc0, 0x03, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x01, 0x01, 0x00, 0x10, 0x10, 0x55, 0x7d, 0x55, 0xf5, 0x55, 0xc3, 0x57, 0x0d, 0x55, 0xc0, 0xdc, 0x0d, 0x55, 0x70, 0xdc, 0x3d, 0x55, 0x5c, 0x30, 0x35, 0x55, 0x70, 0x00, 0xd5, 0x55, 0xc3, 0xfc, 0xd5, 0x55, 0xcf, 0xff, 0x35, 0x57, 0x0f, 0xff, 0x35, 0x57, 0x00, 0xfc, 0x35, 0x57, 0xc0 };\r\n\r\n\r\nvoid EXTI0_IRQHandler() {\r\n\r\n\t//GPIO_SetBits(GPIOB, GPIO_Pin_14);\r\n //if (EXTI_GetITStatus(EXTI_Line0) != RESET) {\r\n if(started){\r\n \tif(read){\r\n\r\n \t\tread = 2;\r\n \t}\r\n \tread = 1;\r\n \t//GPIO_SetBits(GPIOB, GPIO_Pin_14);\r\n \ta = 0;\r\n \tacount = 0;\r\n //\tas[loops++] = a;\r\n \t//as[loops++] = acount;\r\n \tas[loops++] = hit;\r\n \thit = 0;\r\n\r\n\r\n }\r\n EXTI_ClearITPendingBit(EXTI_Line0);\r\n //}\r\n\t//GPIO_ResetBits(GPIOB, GPIO_Pin_14);\r\n}\r\n\r\nvoid EXTI1_IRQHandler() {\r\n\t//hit++;\r\n\t//if (EXTI_GetITStatus(EXTI_Line1) != RESET) {\r\n\r\n \tif(read){\r\n\r\n \t//\ta = a << 1;\r\n \t//\tGPIO_SetBits(GPIOB, GPIO_Pin_15);\r\n \t\t// a = a | (GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_8));\r\n\r\n \t\t(GPIOD->IDR & GPIO_Pin_8) ? (a = ((a << 1)|1) ) : (a <<= 1);\r\n\r\n \t\t//GPIO_ResetBits(GPIOB, GPIO_Pin_15);\r\n \t\tacount++;\r\n\t\t//\t if(acount > 32){\r\n\r\n\t\t\t//\t\t GPIO_SetBits(GPIOD, GPIO_Pin_15);\r\n\t\t\t\t// }\r\n\r\n \t\tif (acount ==32){\r\n \t\t\tread = 0;\r\n\r\n \t\t\t //if((a & 0xff000000) != 0x03000000){\r\n\r\n \t\t\t\t//\t GPIO_SetBits(GPIOD, GPIO_Pin_14);\r\n \t\t\t\t// }\r\n\r\n \t\t\tas[loops++] = a;\r\n\r\n \t\t\t a = 0xffffff & a;\r\n\r\n\r\n \t\t\tval = v[a++];\r\n \t\t//\tas[loops++] = val;\r\n \t\t//\tas[loops++] = val;\r\n \t\t\tc = 0x80;\r\n \t\t\tif(val&c){\r\n \t\t\t\t\t\t GPIO_SetBits(GPIOD, GPIO_Pin_4);\r\n \t\t\t \t\t }else{\r\n \t\t\t \t\t\t GPIO_ResetBits(GPIOD, GPIO_Pin_4);\r\n\r\n \t\t\t \t\t }\r\n\r\n \t\t\t \t\t c = c >> 1;\r\n \t\t\t \t\t started = 1;\r\n \t\t}\r\n\r\n \t}else{\r\n \t\t if(val&c){\r\n \t\t\t GPIOD->BSRRL = GPIO_Pin_4;\r\n \t\t }else{\r\n \t\t\t GPIOD->BSRRH = GPIO_Pin_4;\r\n\r\n \t\t }\r\n\r\n \t\t c = c >> 1;\r\n \t\t if(c==0){\r\n \t\t\t c = 0x80;\r\n \t\t\t val = v[a++];\r\n \t\t\t // as[loops++] = val;\r\n\r\n \t\t }\r\n \t\t //as[loops++] = 2;\r\n \t}\r\n\r\n \tEXTI_ClearITPendingBit(EXTI_Line1);\r\n\r\n //}\r\n\r\n\r\n}\r\n\r\n\r\n\r\n\r\n/**\r\n * @brief Main program.\r\n * @param None\r\n * @retval None\r\n */\r\nuint32_t getAddress();\r\n\r\n\r\nint main(void)\r\n{\r\n RCC_ClocksTypeDef RCC_Clocks;\r\n\r\n int l = 0;\r\n\r\n /* Initialize LEDs and User_Button on STM32F4-Discovery --------------------*/\r\n\r\n RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE);\r\n RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE);\r\n /* SysTick end of count event each 10ms */\r\n // RCC_GetClocksFreq(&RCC_Clocks);\r\n // SysTick_Config(RCC_Clocks.HCLK_Frequency / 100);\r\n\r\n GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_8 ;\r\n GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r\n GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r\n GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;\r\n GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r\n GPIO_Init(GPIOD, &GPIO_InitStructure);\r\n\r\n GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;\r\n GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r\n GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r\n GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;\r\n GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;\r\n GPIO_Init(GPIOD, &GPIO_InitStructure);\r\n\r\n GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_13| GPIO_Pin_14| GPIO_Pin_15;\r\n GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;\r\n GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r\n GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;\r\n GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r\n GPIO_Init(GPIOD, &GPIO_InitStructure);\r\n\r\n\r\n GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14 | GPIO_Pin_15;\r\n GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;\r\n GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r\n GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;\r\n GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r\n GPIO_Init(GPIOB, &GPIO_InitStructure);\r\n\r\n\r\n EXTILine0_Config();\r\n GPIO_SetBits(GPIOD, GPIO_Pin_12);\r\n // GPIO_SetBits(GPIOD, GPIO_Pin_14);\r\n// GPIO_SetBits(GPIOD, GPIO_Pin_12);\r\n // GPIO_ResetBits(GPIOB, GPIO_Pin_14);\r\n //GPIO_SetBits(GPIOB, GPIO_Pin_14);\r\n while(1){\r\n\r\n\t// GPIO_SetBits(GPIOB, GPIO_Pin_14);\r\n\t // GPIO_ResetBits(GPIOB, GPIO_Pin_14);\r\n\r\n\t // printf(\"here\");\r\n/*\t uint32_t a, j;\r\n\t uint8_t t, c, i;\r\n\t flag = 1;\r\n\t if(started)\r\n\t \t while(GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_0)){\r\n\t \t\t l++;\r\n\t \t }\r\n\r\n\t a = getAddress();\r\n\t // if(a < 0 || a > 200){\r\n\r\n\t\t// GPIO_SetBits(GPIOD, GPIO_Pin_14);\r\n\t //}\r\n\t started = 1;\r\n\t while(flag){\r\n\t t = v[a];\r\n\t c = 0x80;\r\n\t for( i = 0; (i < 8); i++){\r\n//\tif(a > 200){\r\n\r\n\t//\tloops++;\r\n//\t}\r\n\r\n\t if(t&c){\r\n\t\t GPIO_SetBits(GPIOD, GPIO_Pin_4);\r\n\t }else{\r\n\t\t GPIO_ResetBits(GPIOD, GPIO_Pin_4);\r\n\r\n\t }\r\n\r\n\t // if(!flag)\r\n\t \t//\t\t break;\r\n\t c = c >> 1;\r\n\t// q = ;\r\n\t// while((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)== Bit_RESET) && (GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_9) == Bit_RESET)){}\r\n\t // while(GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11) && (GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_9) == Bit_RESET) ){}\r\n//\t l = 0;\r\n\t //while((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)== Bit_SET) && flag ){}\r\n\t// as[loops++] = q;\r\n\t // q = 0;\r\n\t while((!GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)) && flag ){\r\n\r\n\r\n\t }\r\n\r\n\r\n\t//\t if((l++ % 100) == 99){\r\n\t\t//\t if((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_9) != Bit_RESET))\r\n\t//\t\t\t break;\r\n//\t\t }\r\n\r\n\t // as[loops++] = q;\r\n\t \t// q = 0;\r\n\r\n\r\n\r\n\t// l = 0;\r\n\t while(GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)){\r\n\t\t //q++;\r\n\t }\r\n\r\n\t //as[loops++] = q;\r\n\r\n\t//\t\t if((l++ % 100) == 99){\r\n\t\t//\t\t\t if((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_9) != Bit_RESET))\r\n\t\t\t//\t\t\t break;\r\n\t\t\t//\t }\r\n//\r\n\t// for(j=0; j < 1000000; j++){\r\n\r\n\t // }\r\n\t // }\r\n\r\n\t // if(flag)\r\n\t\t// loop++;\r\n\r\n\t }\r\n\t a++;\r\n\t }\r\n\r\n\r\n\t // as[loops++] = a;\r\n\r\n*/\r\n\r\n}\r\n\r\n}\r\n\r\nuint32_t getAddress(){\r\n\tuint32_t a, i;\r\n\t\ta = 0;\r\n\t\t for(i = 0; i < 32; i++){\r\n\r\n\r\n\t\t while(GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)== Bit_RESET){}\r\n\t\t //a++;\r\n\t\t a = a << 1;\r\n\t\t a = a + (GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_10)? 1:0);\r\n\r\n\t\t // if(i!=31)\r\n\t\t\t while(GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)){}\r\n\t }\r\n\r\n\t\t if((a & 0xff000000) != 0x03000000){\r\n\r\n\t\t\t// GPIO_SetBits(GPIOD, GPIO_Pin_15);\r\n\t\t }\r\n\r\n\t//\t as[loops++] = a;\r\n\t\t return a & 0x00ffffff;\r\n\r\n\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n\r\n/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "devtools/itemmake/README", "content": "Tamagotchi Item Maker!\r\n\r\nMakes a flash image for a Tamagotchi item from a script. See the sample script as an example.\r\n\r\nThe first command in the script must be \"SOUND MULTIPLIER\". This determines how fast or slow notes (sound) plays in your item. I recommend trying it as set, and tweaking the value if audio plays at the wrong speed. Low values are fast and high values are slow.\r\n\r\nThe second command must be \"IMAGE TABLE\". This is a list of images used by the item. The first image must be the image with the text name of the item (which is displayed below it in the shop), and the second image must be the picture of the item. After that, anything goes. Images must be 16-colour bitmaps.\r\n\r\nAfter these two commands, \"IMAGE\" and \"NOTE\" commands are allowed.\r\n\r\nIMAGE commands display an image. The first parameter is the image name (do not include path or extension), and the second parameter is the amount of time the image is to be displayed for.\r\n\r\nThe NOTE command plays a note. The first parameter is the image to display while playing the note, the second parameter is the note (letter name on a scale, no sharps or flats allowed). The final parameter is the length of the note. I recommend using 1 for the shortest note you need and setting the other values relative to this, and then tweaking the sound multiplier to adjust the length of the note.\r\n\r\nTo make the flash image, call:\r\n\r\nitemmake.py scriptfile outputfile\r\n\r\nQuestions? Comments? Contributions? \r\n\r\nContact: natashenka@kwartzlab.ca / @natashenka" }, { "path": "devtools/itemmake/itemmake.py", "content": "import sys\r\nimport Image\r\n\r\ndef tofourbit(a):\r\n\t#print a\r\n\tif ((a > -1) and (a < 1)):\r\n\t\treturn 3;\r\n\tif ((a > 0) and (a < 8)):\r\n\t\treturn 2;\r\n\tif ((a > 7) and (a < 10 )):\r\n\t\treturn 1;\r\n\tif (a > 9):\r\n\t\treturn 0;\r\ndef conv(a):\r\n\r\n\tt = 0;\r\n\tt = t | (tofourbit(ord(a) & 0x0f) << 2)\r\n\tt = t | (tofourbit((ord(a) & 0xf0) >> 4))\r\n\treturn t\r\n\r\ndef getnote(n):\r\n\ta = [\"C\", \"D\", \"E\", \"F\", \"G\", \"A\", \"B\", \"HC\", \"HD\", \"HE\", \"HF\", \"HG\"]\r\n\tq = a.index(str(n))\r\n\treturn q + 0x54\r\n\r\n\r\ndef imconv(path):\r\n\r\n\ts = \"\"\r\n\ttmp = 0\r\n\trol = 0\r\n\tim = Image.open(path)\r\n\r\n\ti = 0\r\n\twidth = im.size[0]\r\n\theight = im.size[1]\r\n\twhile ( i < (width * height) ):\r\n\t\ttmp = 0;\r\n\t\tfor j in range(0, 4):\r\n\t\t\t\r\n\t\t\ttmp = tmp | tofourbit(im.getpixel(((i)%width, (i)/width)))\r\n\t\t\t\r\n\t\t\ti = i + 1\r\n\t\t\tif j != 3:\r\n\t\t\t\ttmp = tmp * 4\r\n\t\t\t#print tmp\r\n\r\n\t\ts = s + chr(tmp)\r\n\t\r\n\t#f = open(\"pic.txt\", 'ab')\r\n\tr = \"\"\r\n\tr = r + chr(width)\r\n\tr = r + chr(height)\r\n\tr = r + s\r\n\treturn r\r\n\r\n\r\nf = open(sys.argv[1], 'r')\r\nscript = f.readlines()\r\nf.close()\r\nf = open(\"template.txt\", 'rb')\r\nt = f.read()\r\nt = bytearray(t)\r\nf.close()\r\nsm = 0\r\nif( script.pop(0).strip(\"\\n\\r\") != \"SOUND MULTIPLIER:\"):\r\n\tprint \"error\"\r\nscript.pop(0)\r\n\r\nsm = int(script.pop(0).strip(\"\\n\\r\"))\r\n\r\nprint sm\r\nscript.pop(0)\r\n\r\nif( script.pop(0).strip(\"\\n\\r\") != \"IMAGE TABLE:\"):\r\n\tprint \"error\"\r\n\r\nscript.pop(0)\r\n\r\ni = script.pop(0).strip(\"\\n\\r\")\r\nimagetable = []\r\n\r\nwhile(i != \"\"):\r\n\timagetable.append(i)\r\n\ti = script.pop(0).strip(\"\\n\\r\")\r\n\r\nimdata = \"\"\r\nimptr = 0x50000\r\nimptrptr = 0x4f1\r\n\r\nt[0x2cc] = imptr & 0xff\r\nt[0x2cd] = (imptr & 0xff00) >> 8\r\nt[0x2ce] = (imptr & 0xff0000) >> 16\r\n\r\nd = imconv(imagetable[0])\r\ntimptr = imptr + len(d)\r\n\r\nt[0x2a8] = timptr & 0xff\r\nt[0x2a9] = (timptr & 0xff00) >> 8\r\nt[0x2aa] = (timptr & 0xff0000) >> 16\r\n\r\nfor item in imagetable:\r\n\td = imconv(item)\r\n\timdata = imdata + d\r\n\tt[imptrptr] = imptr & 0xff\r\n\tt[imptrptr + 1] = (imptr & 0xff00) >> 8\r\n\tt[imptrptr + 2] = (imptr & 0xff0000) >> 16\r\n\timptrptr = imptrptr + 3\r\n\timptr = imptr + len(d)\r\n\r\n\r\n\r\nfor j in range(0, len(imdata)):\r\n\tt[0x50000 + 0x10 + j] = imdata[j]\r\n\r\nftable = []\r\nfor item in imagetable:\r\n\tindex = item.find('.')\r\n\ts = item[:index]\r\n\ts = s[s.rfind('\\\\')+1:]\r\n\tftable.append(s)\r\nprint ftable\r\n\r\ncbuf = \"\"\r\non = True\r\n\r\nwhile on:\r\n\tcommand = script.pop(0).strip(\"\\n\\r\")\r\n\tif(command == \"IMAGE:\"):\r\n\t\tscript.pop(0).strip(\"\\n\\r\")\r\n\t\tim, time = script.pop(0).strip(\"\\n\\r\").split(' ')\r\n\t\tcbuf = cbuf + chr(ftable.index(im) + 0xb1)\r\n\t\tcbuf = cbuf + \"\\x80\\x00\\x00\\x00\" + chr(int(time, 16))\r\n\t\tscript.pop(0).strip(\"\\n\\r\")\r\n\tif(command == \"NOTE:\"):\r\n\t\tscript.pop(0).strip(\"\\n\\r\")\r\n\t\t#print script.pop(0).strip(\"\\n\\r\")\r\n\t\tim, note, time = script.pop(0).strip(\"\\n\\r\").split(' ')\r\n\t\tb = \"\\xfe\\xff\" + chr(getnote(note)) + \"\\x00\\x00\\x00\"\r\n\t\tcbuf = cbuf + chr(ftable.index(im) + 0xb1) + \"\\x80\\x00\\x00\\x00\\x01\"\r\n\t\tb = b + \"\\xb0\\x80\\x00\\x00\\x00\\x03\"\r\n\t\tfor j in range(0, sm * int(time, 16)):\r\n\t\t\tcbuf = cbuf + b\r\n\t\tscript.pop(0).strip(\"\\n\\r\")\r\n\tif(command == \"END\"):\r\n\t\tcbuf = cbuf + \"\\xff\\xff\"\r\n\t\ton = False\r\n\t\r\nfor j in range(0, len(cbuf)):\r\n\tt[0x250c4 + j] = cbuf[j]\r\n\r\nf = open(sys.argv[2], 'wb')\r\nf.write(t)\r\nf.close()\r\n\r\n\t" }, { "path": "devtools/itemmake/samplescript.txt", "content": "SOUND MULTIPLIER:\r\n\r\n2\r\n\r\nIMAGE TABLE:\r\n\r\nC:\\Users\\Natalie\\Pictures\\madworld\\mad.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\madi.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\title.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\tree1.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\tree2.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\tree3.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\treeg1.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\treeg2.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\treeg3.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\windowsit1.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\windowsit2.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\windowsit3.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\windowclose.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\windowclose2.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\win1.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\win0.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\winvc2.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\winvc.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\hands2.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\hands.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\treewin2.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\treewin.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\candle1.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\candle2.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\candle3.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\bday.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\bday2.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\wd6.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\wd1.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\wd2.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\wd3.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\wd4.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\wd5.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\ball2.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\d1.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\d2.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\d3.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\d4.bmp\r\nC:\\Users\\Natalie\\Pictures\\madworld\\ball.bmp\r\n\r\nIMAGE:\r\n\r\ntitle 0x70\r\n\r\nIMAGE:\r\n\r\ntree3 0x20\r\n\r\nIMAGE:\r\n\r\ntree2 0x20\r\n\r\nIMAGE:\r\n\r\ntree1 0x30\r\n\r\nIMAGE:\r\n\r\nwindowsit1 0x20\r\n\r\nIMAGE:\r\n\r\nwindowsit2 0x20\r\n\r\nIMAGE:\r\n\r\nwindowsit3 0x30\r\n\r\nIMAGE:\r\n\r\ntreeg1 0x20\r\n\r\nIMAGE:\r\n\r\ntreeg2 0x20\r\n\r\nIMAGE:\r\n\r\ntreeg3 0x30\r\n\r\n#rif 1 4 repeat start\r\n\r\nNOTE:\r\n\r\nwindowclose D 1\r\n\r\nNOTE:\r\n\r\nwindowclose2 D 1\r\n\r\nNOTE:\r\n\r\nwindowclose F 1\r\n\r\nNOTE:\r\n\r\nwindowclose2 F 1\r\n\r\nNOTE:\r\n\r\nwindowclose D 1\r\n\r\nNOTE:\r\n\r\nwindowclose2 D 1\r\n\r\n\r\nNOTE:\r\n\r\nwindowclose A 1\r\n\r\nNOTE:\r\n\r\nwindowclose2 A 2\r\n\r\nNOTE:\r\n\r\nwindowclose A 2\r\n\r\nNOTE:\r\n\r\nwindowclose2 F 3\r\n\r\nNOTE:\r\n\r\nwindowclose G 1\r\n\r\nNOTE:\r\n\r\nwindowclose2 G 2\r\n\r\nNOTE:\r\n\r\nwindowclose G 2\r\n\r\nNOTE:\r\n\r\nwindowclose2 E 3\r\n\r\nNOTE:\r\n\r\nwindowclose G 1\r\n\r\nNOTE:\r\n\r\nwindowclose2 G 2\r\n\r\nNOTE:\r\n\r\nwindowclose G 2\r\n\r\nNOTE:\r\n\r\nwindowclose2 F 1\r\n\r\nNOTE:\r\n\r\nwindowclose2 E 1\r\n\r\nNOTE:\r\n\r\nwindowclose2 D 3\r\n\r\nNOTE:\r\n\r\nwin0 D 1\r\n\r\nNOTE:\r\n\r\nwin1 D 1\r\n\r\nNOTE:\r\n\r\nwin0 F 1\r\n\r\nNOTE:\r\n\r\nwin1 F 1\r\n\r\nNOTE:\r\n\r\nwin0 D 1\r\n\r\nNOTE:\r\n\r\nwin1 D 1\r\n\r\nNOTE:\r\n\r\nwin0 A 1\r\n\r\nNOTE:\r\n\r\nwin1 A 2\r\n\r\nNOTE:\r\n\r\nwin0 A 2\r\n\r\nNOTE:\r\n\r\nwin1 F 3\r\n\r\nNOTE:\r\n\r\nwin0 G 1\r\n\r\nNOTE:\r\n\r\nwin1 G 2\r\n\r\nNOTE:\r\n\r\nwin0 G 2\r\n\r\nNOTE:\r\n\r\nwin1 E 3\r\n\r\nNOTE:\r\n\r\nwin0 G 1\r\n\r\nNOTE:\r\n\r\nwin1 G 2\r\n\r\nNOTE:\r\n\r\nwin0 G 2\r\n\r\nNOTE:\r\n\r\nwin1 F 1\r\n\r\nNOTE:\r\n\r\nwin0 E 1\r\n\r\nNOTE:\r\n\r\nwin1 D 3\r\n\r\nNOTE:\r\n\r\nwinvc D 1\r\n\r\nNOTE:\r\n\r\nwinvc2 D 1\r\n\r\nNOTE:\r\n\r\nwinvc F 1\r\n\r\nNOTE:\r\n\r\nwinvc2 F 1\r\n\r\nNOTE:\r\n\r\nwinvc D 1\r\n\r\nNOTE:\r\n\r\nwinvc2 D 1\r\n\r\nNOTE:\r\n\r\nwinvc A 1\r\n\r\nNOTE:\r\n\r\nwinvc2 A 2\r\n\r\nNOTE:\r\n\r\nwinvc A 2\r\n\r\nNOTE:\r\n\r\nwinvc2 F 3\r\n\r\nNOTE:\r\n\r\nwinvc G 1\r\n\r\nNOTE:\r\n\r\nwinvc2 G 2\r\n\r\nNOTE:\r\n\r\nwinvc G 2\r\n\r\nNOTE:\r\n\r\nwinvc2 E 3\r\n\r\nNOTE:\r\n\r\nwinvc G 1\r\n\r\nNOTE:\r\n\r\nwinvc2 G 2\r\n\r\nNOTE:\r\n\r\nwinvc G 2\r\n\r\nNOTE:\r\n\r\nwinvc2 F 1\r\n\r\nNOTE:\r\n\r\nwinvc E 1\r\n\r\nNOTE:\r\n\r\nwinvc2 D 3\r\n\r\nNOTE:\r\n\r\nwin0 D 1\r\n\r\nNOTE:\r\n\r\nwin1 D 1\r\n\r\nNOTE:\r\n\r\nwin0 F 1\r\n\r\nNOTE:\r\n\r\nwin1 F 1\r\n\r\nNOTE:\r\n\r\nwin0 D 1\r\n\r\nNOTE:\r\n\r\nwin1 D 1\r\n\r\nNOTE:\r\n\r\nwin0 A 1\r\n\r\nNOTE:\r\n\r\nwin1 A 2\r\n\r\nNOTE:\r\n\r\nwin0 A 2\r\n\r\nNOTE:\r\n\r\nwin1 F 3\r\n\r\nNOTE:\r\n\r\nwin0 G 1\r\n\r\nNOTE:\r\n\r\nwin1 G 2\r\n\r\nNOTE:\r\n\r\nwin0 G 2\r\n\r\nNOTE:\r\n\r\nwin1 E 3\r\n\r\nNOTE:\r\n\r\nwin0 G 1\r\n\r\nNOTE:\r\n\r\nwin1 G 2\r\n\r\nNOTE:\r\n\r\nwin0 G 2\r\n\r\nNOTE:\r\n\r\nwin1 F 1\r\n\r\nNOTE:\r\n\r\nwin0 E 1\r\n\r\nNOTE:\r\n\r\nwin1 D 3\r\n\r\n#rif 1 4 repeat end\r\n\r\nNOTE:\r\n\r\nhands2 D 1\r\n\r\nNOTE:\r\n\r\nhands D 1\r\n\r\nNOTE:\r\n\r\nhands2 F 1\r\n\r\nNOTE:\r\n\r\nhands F 1\r\n\r\nNOTE:\r\n\r\nhands2 A 1\r\n\r\nNOTE:\r\n\r\nhands A 1\r\n\r\nNOTE:\r\n\r\nhands2 B 1\r\n\r\nNOTE:\r\n\r\nhands G 1\r\n\r\nIMAGE:\r\n\r\nhands 6\r\n\r\nNOTE:\r\n\r\nhands2 G 1\r\n\r\nNOTE:\r\n\r\nhands B 1\r\n\r\nNOTE:\r\n\r\nhands2 B 1\r\n\r\nNOTE:\r\n\r\nhands G 1\r\n\r\nNOTE:\r\n\r\nhands2 G 1\r\n\r\nNOTE:\r\n\r\nhands D 1\r\n\r\n#begin\r\n\r\nIMAGE:\r\n\r\nhands2 6\r\n\r\nNOTE:\r\n\r\nhands D 1\r\n\r\nNOTE:\r\n\r\nhands2 F 1\r\n\r\nNOTE:\r\n\r\nhands F 1\r\n\r\nNOTE:\r\n\r\nhands2 A 1\r\n\r\nNOTE:\r\n\r\nhands A 1\r\n\r\nNOTE:\r\n\r\nhands2 B 1\r\n\r\nNOTE:\r\n\r\nhands G 1\r\n\r\nNOTE:\r\n\r\nhands G 1\r\n\r\nNOTE:\r\n\r\nhands2 G 1\r\n\r\nNOTE:\r\n\r\nhands B 1\r\n\r\nNOTE:\r\n\r\nhands2 B 1\r\n\r\nNOTE:\r\n\r\nhands G 1\r\n\r\nNOTE:\r\n\r\nhands2 G 1\r\n\r\nNOTE:\r\n\r\nhands D 1\r\n\r\nNOTE:\r\n\r\nhands2 D 1\r\n\r\nNOTE:\r\n\r\nhands D 1\r\n\r\nNOTE:\r\n\r\nhands2 F 1\r\n\r\nNOTE:\r\n\r\nhands F 1\r\n\r\nNOTE:\r\n\r\nhands2 A 1\r\n\r\nNOTE:\r\n\r\nhands A 1\r\n\r\nNOTE:\r\n\r\nhands2 B 1\r\n\r\nNOTE:\r\n\r\nhands G 1\r\n\r\nIMAGE:\r\n\r\nhands 6\r\n\r\nNOTE:\r\n\r\nhands2 G 1\r\n\r\nNOTE:\r\n\r\nhands B 1\r\n\r\nNOTE:\r\n\r\nhands2 B 1\r\n\r\nNOTE:\r\n\r\nhands G 1\r\n\r\nNOTE:\r\n\r\nhands2 G 1\r\n\r\nNOTE:\r\n\r\nhands D 1\r\n\r\nbegin\r\n\r\nIMAGE:\r\n\r\nhands2 6\r\n\r\nNOTE:\r\n\r\nhands D 1\r\n\r\nNOTE:\r\n\r\nhands2 F 1\r\n\r\nNOTE:\r\n\r\nhands F 1\r\n\r\nNOTE:\r\n\r\nhands2 A 1\r\n\r\nNOTE:\r\n\r\nhands A 1\r\n\r\nNOTE:\r\n\r\nhands2 B 1\r\n\r\nNOTE:\r\n\r\nhands G 1\r\n\r\nNOTE:\r\n\r\nhands G 1\r\n\r\nNOTE:\r\n\r\nhands2 G 1\r\n\r\nNOTE:\r\n\r\nhands B 1\r\n\r\nNOTE:\r\n\r\nhands2 B 1\r\n\r\nNOTE:\r\n\r\nhands G 1\r\n\r\nNOTE:\r\n\r\nhands2 G 1\r\n\r\nNOTE:\r\n\r\nhands D 1\r\n\r\n#mad world start\r\n\r\nIMAGE:\r\n\r\nhands2 15\r\n\r\nNOTE:\r\n\r\ntreewin F 5\r\n\r\nNOTE:\r\n\r\ntreewin2 D 7\r\n\r\nIMAGE:\r\n\r\ntreewin2 15\r\n\r\nNOTE:\r\n\r\nhands F 5\r\n\r\nNOTE:\r\n\r\nhands2 D 7\r\n\r\nIMAGE:\r\n\r\nhands2 15\r\n\r\nNOTE:\r\n\r\ntreewin F 5\r\n\r\nNOTE:\r\n\r\ntreewin2 D 7\r\n\r\nIMAGE:\r\n\r\ntreewin2 15\r\n\r\nNOTE:\r\n\r\nhands F 5\r\n\r\nNOTE:\r\n\r\nhands2 D 7\r\n\r\n#begin part 2\r\n\r\n#rif 1 4 repeat start\r\n\r\nNOTE:\r\n\r\ncandle1 D 1\r\n\r\nNOTE:\r\n\r\ncandle1 D 1\r\n\r\nNOTE:\r\n\r\ncandle1 F 1\r\n\r\nNOTE:\r\n\r\ncandle1 F 1\r\n\r\nNOTE:\r\n\r\ncandle2 D 1\r\n\r\nNOTE:\r\n\r\ncandle2 D 1\r\n\r\n\r\nNOTE:\r\n\r\ncandle2 A 1\r\n\r\nNOTE:\r\n\r\ncandle2 A 2\r\n\r\nNOTE:\r\n\r\ncandle3 A 2\r\n\r\nNOTE:\r\n\r\ncandle3 F 3\r\n\r\nNOTE:\r\n\r\ncandle3 G 1\r\n\r\nNOTE:\r\n\r\ncandle3 G 2\r\n\r\nNOTE:\r\n\r\nbday G 2\r\n\r\nNOTE:\r\n\r\nbday E 3\r\n\r\nNOTE:\r\n\r\nbday G 1\r\n\r\nNOTE:\r\n\r\nbday G 2\r\n\r\nNOTE:\r\n\r\nbday2 G 2\r\n\r\nNOTE:\r\n\r\nbday2 F 1\r\n\r\nNOTE:\r\n\r\nbday2 E 1\r\n\r\nNOTE:\r\n\r\nbday2 D 3\r\n\r\nNOTE:\r\n\r\nwindowclose D 1\r\n\r\nNOTE:\r\n\r\nwindowclose2 D 1\r\n\r\nNOTE:\r\n\r\nwindowclose F 1\r\n\r\nNOTE:\r\n\r\nwindowclose2 F 1\r\n\r\nNOTE:\r\n\r\nwindowclose D 1\r\n\r\nNOTE:\r\n\r\nwindowclose D 1\r\n\r\nNOTE:\r\n\r\nwindowclose2 A 1\r\n\r\nNOTE:\r\n\r\nwindowclose A 2\r\n\r\nNOTE:\r\n\r\nwindowclose2 A 2\r\n\r\nNOTE:\r\n\r\nwindowclose F 3\r\n\r\nNOTE:\r\n\r\nwindowclose2 G 1\r\n\r\nNOTE:\r\n\r\nwindowclose G 2\r\n\r\nNOTE:\r\n\r\nwindowclose2 G 2\r\n\r\nNOTE:\r\n\r\nwindowclose E 3\r\n\r\nNOTE:\r\n\r\nwindowclose G 1\r\n\r\nNOTE:\r\n\r\nwindowclose2 G 2\r\n\r\nNOTE:\r\n\r\nwindowclose G 2\r\n\r\nNOTE:\r\n\r\nwindowclose2 F 1\r\n\r\nNOTE:\r\n\r\nwindowclose E 1\r\n\r\nNOTE:\r\n\r\nwindowclose2 D 3\r\n\r\nNOTE:\r\n\r\nwinvc D 1\r\n\r\nNOTE:\r\n\r\nwinvc2 D 1\r\n\r\nNOTE:\r\n\r\nwinvc F 1\r\n\r\nNOTE:\r\n\r\nwinvc2 F 1\r\n\r\nNOTE:\r\n\r\nwinvc D 1\r\n\r\nNOTE:\r\n\r\nwinvc2 D 1\r\n\r\nNOTE:\r\n\r\nwinvc A 1\r\n\r\nNOTE:\r\n\r\nwinvc2 A 2\r\n\r\nNOTE:\r\n\r\nwinvc A 2\r\n\r\nNOTE:\r\n\r\nwinvc2 F 3\r\n\r\nNOTE:\r\n\r\nwinvc G 1\r\n\r\nNOTE:\r\n\r\nwinvc2 G 2\r\n\r\nNOTE:\r\n\r\nwinvc G 2\r\n\r\nNOTE:\r\n\r\nwinvc2 E 3\r\n\r\nNOTE:\r\n\r\nwinvc G 1\r\n\r\nNOTE:\r\n\r\nwinvc2 G 2\r\n\r\nNOTE:\r\n\r\nwinvc G 2\r\n\r\nNOTE:\r\n\r\nwinvc2 F 1\r\n\r\nNOTE:\r\n\r\nwinvc E 1\r\n\r\nNOTE:\r\n\r\nwinvc2 D 3\r\n\r\nNOTE:\r\n\r\nwindowclose2 D 1\r\n\r\nNOTE:\r\n\r\nwindowclose D 1\r\n\r\nNOTE:\r\n\r\nwindowclose F 1\r\n\r\nNOTE:\r\n\r\nwindowclose2 F 1\r\n\r\nNOTE:\r\n\r\nwindowclose D 1\r\n\r\nNOTE:\r\n\r\nwindowclose2 D 1\r\n\r\nNOTE:\r\n\r\nwindowclose A 1\r\n\r\nNOTE:\r\n\r\nwindowclose2 A 2\r\n\r\nNOTE:\r\n\r\nwindowclose A 2\r\n\r\nNOTE:\r\n\r\nwindowclose2 F 3\r\n\r\nNOTE:\r\n\r\nwindowclose G 1\r\n\r\nNOTE:\r\n\r\nwindowclose2 G 2\r\n\r\nNOTE:\r\n\r\nwindowclose G 2\r\n\r\nNOTE:\r\n\r\nwindowclose2 E 3\r\n\r\nNOTE:\r\n\r\nwindowclose G 1\r\n\r\nNOTE:\r\n\r\nwindowclose2 G 2\r\n\r\nNOTE:\r\n\r\nwindowclose G 2\r\n\r\nNOTE:\r\n\r\nwindowclose2 F 1\r\n\r\nNOTE:\r\n\r\nwindowclose E 1\r\n\r\nNOTE:\r\n\r\nwindowclose2 D 3\r\n\r\n#rif 1 4 repeat end\r\n\r\nNOTE:\r\n\r\nwd1 D 1\r\n\r\nNOTE:\r\n\r\nwd2 D 1\r\n\r\nNOTE:\r\n\r\nwd3 F 1\r\n\r\nNOTE:\r\n\r\nwd4 F 1\r\n\r\nNOTE:\r\n\r\nwd5 A 1\r\n\r\nNOTE:\r\n\r\nwd6 A 1\r\n\r\nNOTE:\r\n\r\nwd1 B 1\r\n\r\nNOTE:\r\n\r\nwd2 G 1\r\n\r\nIMAGE:\r\n\r\nwd3 6\r\n\r\nNOTE:\r\n\r\nwd4 G 1\r\n\r\nNOTE:\r\n\r\nwd5 B 1\r\n\r\nNOTE:\r\n\r\nwd6 B 1\r\n\r\nNOTE:\r\n\r\nwd1 G 1\r\n\r\nNOTE:\r\n\r\nwd2 G 1\r\n\r\nNOTE:\r\n\r\nwd3 D 1\r\n\r\nbegin\r\n\r\nIMAGE:\r\n\r\nwd4 6\r\n\r\nNOTE:\r\n\r\nwd5 D 1\r\n\r\nNOTE:\r\n\r\nwd6 F 1\r\n\r\nNOTE:\r\n\r\nwd1 F 1\r\n\r\nNOTE:\r\n\r\nwd2 A 1\r\n\r\nNOTE:\r\n\r\nwd3 A 1\r\n\r\nNOTE:\r\n\r\nwd4 B 1\r\n\r\nNOTE:\r\n\r\nwd5 G 1\r\n\r\nNOTE:\r\n\r\nwd6 G 1\r\n\r\nNOTE:\r\n\r\nwd1 G 1\r\n\r\nNOTE:\r\n\r\nwd2 B 1\r\n\r\nNOTE:\r\n\r\nwd3 B 1\r\n\r\nNOTE:\r\n\r\nwd4 G 1\r\n\r\nNOTE:\r\n\r\nwd5 G 1\r\n\r\nNOTE:\r\n\r\nwd6 D 1\r\n\r\nNOTE:\r\n\r\nwd1 D 1\r\n\r\nNOTE:\r\n\r\nwd2 D 1\r\n\r\nNOTE:\r\n\r\nwd3 F 1\r\n\r\nNOTE:\r\n\r\nwd4 F 1\r\n\r\nNOTE:\r\n\r\nwd5 A 1\r\n\r\nNOTE:\r\n\r\nwd6 A 1\r\n\r\nNOTE:\r\n\r\nwd1 B 1\r\n\r\nNOTE:\r\n\r\nwd2 G 1\r\n\r\nIMAGE:\r\n\r\nwd3 6\r\n\r\nNOTE:\r\n\r\nwd4 G 1\r\n\r\nNOTE:\r\n\r\nwd5 B 1\r\n\r\nNOTE:\r\n\r\nwd6 B 1\r\n\r\nNOTE:\r\n\r\nwd1 G 1\r\n\r\nNOTE:\r\n\r\nwd2 G 1\r\n\r\nNOTE:\r\n\r\nwd3 D 1\r\n\r\nbegin\r\n\r\nIMAGE:\r\n\r\nwd3 6\r\n\r\nNOTE:\r\n\r\nwd4 D 1\r\n\r\nNOTE:\r\n\r\nwd5 F 1\r\n\r\nNOTE:\r\n\r\nwd6 F 1\r\n\r\nNOTE:\r\n\r\nwd1 A 1\r\n\r\nNOTE:\r\n\r\nwd1 A 1\r\n\r\nNOTE:\r\n\r\nwd2 B 1\r\n\r\nNOTE:\r\n\r\nwd3 G 1\r\n\r\nNOTE:\r\n\r\nwd4 G 1\r\n\r\nNOTE:\r\n\r\nwd5 G 1\r\n\r\nNOTE:\r\n\r\nwd6 B 1\r\n\r\nNOTE:\r\n\r\nwd1 B 1\r\n\r\nNOTE:\r\n\r\nwd2 G 1\r\n\r\nNOTE:\r\n\r\nwd3 G 1\r\n\r\nNOTE:\r\n\r\nwd4 D 1\r\n\r\n#mad world start\r\n\r\nIMAGE:\r\n\r\nwd4 15\r\n\r\nNOTE:\r\n\r\nwd5 F 5\r\n\r\nNOTE:\r\n\r\nwd6 D 7\r\n\r\nIMAGE:\r\n\r\nhands2 15\r\n\r\nNOTE:\r\n\r\nhands F 5\r\n\r\nNOTE:\r\n\r\nhands2 D 7\r\n\r\nIMAGE:\r\n\r\nhands2 15\r\n\r\nNOTE:\r\n\r\nhands F 5\r\n\r\nNOTE:\r\n\r\nhands2 D 7\r\n\r\nIMAGE:\r\n\r\nhands2 15\r\n\r\nNOTE:\r\n\r\nhands F 5\r\n\r\nNOTE:\r\n\r\nhands2 D 7\r\n\r\nIMAGE:\r\n\r\nball 30\r\n\r\nIMAGE:\r\n\r\nball2 30\r\n\r\nIMAGE:\r\n\r\nd1 10\r\n\r\nIMAGE:\r\n\r\nd2 10\r\n\r\nIMAGE:\r\n\r\nd3 10\r\n\r\nIMAGE:\r\n\r\nd4 10\r\n\r\nIMAGE:\r\n\r\nd1 10\r\n\r\nIMAGE:\r\n\r\nd2 10\r\n\r\nIMAGE:\r\n\r\nd3 10\r\n\r\nIMAGE:\r\n\r\nd4 10\r\n\r\nIMAGE:\r\n\r\nd1 10\r\n\r\nIMAGE:\r\n\r\nd2 10\r\n\r\nIMAGE:\r\n\r\nd3 10\r\n\r\nIMAGE:\r\n\r\nd4 10\r\n\r\n#begin end\r\n\r\nNOTE:\r\n\r\nhands2 D 1\r\n\r\nNOTE:\r\n\r\nhands D 1\r\n\r\nNOTE:\r\n\r\nhands2 F 1\r\n\r\nNOTE:\r\n\r\nhands F 1\r\n\r\nNOTE:\r\n\r\nhands2 A 1\r\n\r\nNOTE:\r\n\r\nhands A 1\r\n\r\nNOTE:\r\n\r\nhands2 B 1\r\n\r\nNOTE:\r\n\r\nhands G 1\r\n\r\nIMAGE:\r\n\r\nhands 6\r\n\r\nNOTE:\r\n\r\nhands2 G 1\r\n\r\nNOTE:\r\n\r\nhands B 1\r\n\r\nNOTE:\r\n\r\nhands2 B 1\r\n\r\nNOTE:\r\n\r\nhands G 1\r\n\r\nNOTE:\r\n\r\nhands2 G 1\r\n\r\nNOTE:\r\n\r\nhands D 1\r\n\r\n#begin\r\n\r\nIMAGE:\r\n\r\nhands2 6\r\n\r\nNOTE:\r\n\r\nhands D 1\r\n\r\nNOTE:\r\n\r\nhands2 F 1\r\n\r\nNOTE:\r\n\r\nhands F 1\r\n\r\nNOTE:\r\n\r\nhands2 A 1\r\n\r\nNOTE:\r\n\r\nhands A 1\r\n\r\nNOTE:\r\n\r\nhands2 B 1\r\n\r\nNOTE:\r\n\r\nhands G 1\r\n\r\nNOTE:\r\n\r\nhands G 1\r\n\r\nNOTE:\r\n\r\nhands2 G 1\r\n\r\nNOTE:\r\n\r\nhands B 1\r\n\r\nNOTE:\r\n\r\nhands2 B 1\r\n\r\nNOTE:\r\n\r\nhands G 1\r\n\r\nNOTE:\r\n\r\nhands2 G 1\r\n\r\nNOTE:\r\n\r\nhands D 1\r\n\r\nNOTE:\r\n\r\nhands2 D 1\r\n\r\nNOTE:\r\n\r\nhands D 1\r\n\r\nNOTE:\r\n\r\nhands2 F 1\r\n\r\nNOTE:\r\n\r\nhands F 1\r\n\r\nNOTE:\r\n\r\nhands2 A 1\r\n\r\nNOTE:\r\n\r\nhands A 1\r\n\r\nNOTE:\r\n\r\nhands2 B 1\r\n\r\nNOTE:\r\n\r\nhands G 1\r\n\r\nIMAGE:\r\n\r\nhands 6\r\n\r\nNOTE:\r\n\r\nhands2 G 1\r\n\r\nNOTE:\r\n\r\nhands B 1\r\n\r\nNOTE:\r\n\r\nhands2 B 1\r\n\r\nNOTE:\r\n\r\nhands G 1\r\n\r\nNOTE:\r\n\r\nhands2 G 1\r\n\r\nNOTE:\r\n\r\nhands D 1\r\n\r\nbegin\r\n\r\nIMAGE:\r\n\r\nhands2 6\r\n\r\nNOTE:\r\n\r\nhands D 1\r\n\r\nNOTE:\r\n\r\nhands2 F 1\r\n\r\nNOTE:\r\n\r\nhands F 1\r\n\r\nNOTE:\r\n\r\nhands2 A 1\r\n\r\nNOTE:\r\n\r\nhands A 1\r\n\r\nNOTE:\r\n\r\nhands2 B 1\r\n\r\nNOTE:\r\n\r\nhands G 1\r\n\r\nNOTE:\r\n\r\nhands G 1\r\n\r\nNOTE:\r\n\r\nhands2 G 1\r\n\r\nNOTE:\r\n\r\nhands B 1\r\n\r\nNOTE:\r\n\r\nhands2 B 1\r\n\r\nNOTE:\r\n\r\nhands G 1\r\n\r\nNOTE:\r\n\r\nhands2 G 1\r\n\r\nNOTE:\r\n\r\nhands D 1\r\n\r\n#mad world start\r\n\r\nIMAGE:\r\n\r\nhands2 15\r\n\r\nNOTE:\r\n\r\nhands F 5\r\n\r\nNOTE:\r\n\r\nhands2 D 7\r\n\r\nIMAGE:\r\n\r\nhands 15\r\n\r\nNOTE:\r\n\r\nhands F 5\r\n\r\nNOTE:\r\n\r\nhands2 D 7\r\n\r\nIMAGE:\r\n\r\nwd1 15\r\n\r\nNOTE:\r\n\r\nwd2 F 5\r\n\r\nNOTE:\r\n\r\nwd3 D 7\r\n\r\nIMAGE:\r\n\r\nwd4 15\r\n\r\nNOTE:\r\n\r\nwd5 F 5\r\n\r\nNOTE:\r\n\r\nwd6 D 7\r\n\r\nIMAGE:\r\n\r\ntreeg1 0x20\r\n\r\nIMAGE:\r\n\r\ntreeg2 0x20\r\n\r\nIMAGE:\r\n\r\ntreeg3 0x30\r\n\r\nEND" }, { "path": "die/README", "content": "Repository for Tamagotchi chip photos!\r\n\r\nFiles:\r\n\r\n\tlogo.jpg -- close up of the only logo on the die\r\n\ttamatowntamago.jpg -- high resolution die photo\t\r\n\r\nQuestions? Comments? Contributions? \r\n\r\nContact: namely_audacious@hotmail.com / @natashenka" }, { "path": "disassembler/README", "content": "Very rudimentary script to detect and disassemble GeneralPlus (SunPlus) bytecode in a binary\r\n\r\nDecodes 'standard'(according to GeneralPlus) and 'SunPlus' 6502 bytecode\r\n\r\nbytecode*.txt -- bytecode listings used for disassembly, can be changed in script\r\n\r\n\tbytecode.txt -- default SunPlus bytecode\r\n\tbytecodes.txt -- shrinkage mode\r\n\tbytecoder.txt -- reduce mode\r\n\tbytecoden.txt -- normal mode\r\n\r\ndissa.py -- the script\r\n\r\ntestbinary.bin -- test binary, compiled using FortisIDE\r\n" }, { "path": "disassembler/a.txt", "content": "assembly found, size 61 index 21253\r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 90 149 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 170 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 106 0 \r\nassembly found, size 36 index 21315\r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nassembly found, size 28 index 21352\r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 170 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 106 0 \r\nassembly found, size 43 index 21545\r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nADC (86) 170 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 48 31 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 170 \r\nassembly found, size 28 index 21589\r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 170 \r\nassembly found, size 80 index 21808\r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 90 149 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 48 31 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 170 \r\nassembly found, size 53 index 21889\r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 48 31 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 170 \r\nassembly found, size 35 index 21943\r\nAND (85) 48 31 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 170 \r\nassembly found, size 27 index 21980\r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 170 149 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nSEI (90) \r\nassembly found, size 47 index 22183\r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 90 149 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nSEI (90) \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 96 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 101 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 96 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 101 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 88 \r\nLDY (48) 31 \r\nassembly found, size 31 index 22231\r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nSEI (90) \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 96 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 101 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 96 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 101 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 88 \r\nLDY (48) 31 \r\nassembly found, size 46 index 29611\r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nSBC (127) 255 245 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 48 \r\nADC (31) 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 169 85 \r\nAND (85) 85 169 \r\nAND (85) 85 85 \r\nAND (85) 85 86 \r\nassembly found, size 30 index 29658\r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 85 85 \r\nAND (85) 169 85 \r\nAND (85) 85 169 \r\nAND (85) 85 85 \r\nAND (85) 85 86 \r\nassembly found, size 30 index 32252\r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 32 \r\nORA (4) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 128 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 0 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 48 \r\nBPL (8) 0 \r\nBPL (8) 1 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 0 \r\nassembly found, size 27 index 50273\r\nLDY (48) 31 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nBIT (17) 17 \r\nRTS (18) \r\nSTX (169) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 68 \r\nORA (68) 74 \r\nADC (86) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 17 \r\nBIT (17) 25 \r\nPHA (66) \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nORA (68) 68 \r\nassembly found, size 32 index 50899\r\nBIT (17) 17 \r\nBIT (17) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 170 \r\nassembly found, size 33 index 51270\r\nROL (145) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nassembly found, size 38 index 51634\r\nORA (68) 68 \r\nORA (68) 68 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nassembly found, size 32 index 53778\r\nJSR (16) 1 34 \r\nJSR (16) 1 34 \r\nJSR (16) 1 34 \r\nJSR (16) 1 34 \r\nJSR (16) 1 34 \r\nJSR (16) 1 34 \r\nJSR (16) 1 34 \r\nJSR (16) 1 34 \r\nJSR (16) 1 34 \r\nJSR (16) 1 34 \r\nJSR (16) 1 34 \r\nJSR (16) 1 34 \r\nJSR (16) 1 34 \r\nJSR (16) 1 34 \r\nJSR (16) 1 34 \r\nJSR (16) 1 34 \r\nJSR (16) 1 34 \r\nJSR (16) 1 34 \r\nJSR (16) 1 34 \r\nJSR (16) 1 34 \r\nJSR (16) 1 34 \r\nJSR (16) 1 34 \r\nJSR (16) 1 34 \r\nJSR (16) 85 98 \r\nAND (85) 85 98 \r\nAND (85) 85 98 \r\nAND (85) 85 98 \r\nAND (85) 85 98 \r\nAND (85) 85 98 \r\nAND (85) 85 98 \r\nAND (85) 85 98 \r\nAND (85) 0 170 \r\nassembly found, size 44 index 73396\r\nEOR (14) 13 \r\nAND (85) 85 85 \r\nPLP (80) \r\nAND (85) 85 85 \r\nPLP (80) \r\nAND (85) 85 85 \r\nPLP (80) \r\nADC (95) 85 95 \r\nPLP (80) \r\nADC (95) 255 255 \r\nPLP (80) \r\nADC (95) 255 255 \r\nPLP (80) \r\nADC (95) 255 255 \r\nROL (208) \r\nSBC (127) 63 207 \r\nROL (208) \r\nLDA (124) 15 3 \r\nROL (208) \r\nLDA (124) 192 51 \r\nROL (208) \r\nTAY (112) \r\nEOR (15) 0 \r\nROL (208) \r\nAND (92) 15 3 \r\nPLP (80) \r\nADC (87) 255 253 \r\nPLP (80) \r\nEOR (14) 13 \r\nAND (85) 85 85 \r\nPLP (80) \r\nAND (85) 87 85 \r\nPLP (80) \r\nAND (85) 255 245 \r\nPLP (80) \r\nADC (87) 12 13 \r\nPLP (80) \r\nAND (92) 0 3 \r\nPLP (80) \r\nAND (92) 0 3 \r\nPLP (80) \r\nADC (95) 0 15 \r\nPLP (80) \r\nTAY (112) \r\nassembly found, size 28 index 73487\r\nROL (208) \r\nTAY (112) \r\nASL (192) \r\nLDY (48) 208 \r\nAND (92) 63 195 \r\nPLP (80) \r\nADC (87) 240 253 \r\nPLP (80) \r\nAND (85) 95 85 \r\nPLP (80) \r\nEOR (14) 13 \r\nAND (85) 85 85 \r\nPLP (80) \r\nAND (85) 85 85 \r\nPLP (80) \r\nAND (85) 253 245 \r\nPLP (80) \r\nAND (85) 87 85 \r\nPLP (80) \r\nADC (87) 255 245 \r\nPLP (80) \r\nAND (92) 0 13 \r\nPLP (80) \r\nAND (92) 0 13 \r\nPLP (80) \r\nTAY (112) \r\nASL (192) \r\nLSR (195) 80 112 \r\nassembly found, size 29 index 73641\r\nPLP (80) \r\nADC (95) 0 0 \r\nROL (208) \r\nAND (85) 192 0 \r\nROL (208) \r\nAND (85) 204 48 \r\nROL (208) \r\nAND (85) 192 3 \r\nPLP (80) \r\nADC (87) 15 13 \r\nPLP (80) \r\nADC (95) 255 245 \r\nPLP (80) \r\nEOR (14) 13 \r\nAND (85) 85 85 \r\nPLP (80) \r\nAND (85) 85 85 \r\nPLP (80) \r\nAND (85) 85 85 \r\nPLP (80) \r\nLDA (125) 85 95 \r\nPLP (80) \r\nLSR (195) 127 112 \r\nROL (208) \r\nLSR (195) 192 240 \r\nROL (208) \r\nLDA (124) 0 15 \r\nPLP (80) \r\nTAY (112) \r\nassembly found, size 30 index 74123\r\nROL (208) \r\nCPX (115) 255 252 \r\nROL (208) \r\nLDA (124) 0 3 \r\nROL (208) \r\nTAY (112) \r\nASL (192) \r\nLDY (48) 208 \r\nTAY (112) \r\nEOR (15) 0 \r\nROL (208) \r\nLDA (124) 48 195 \r\nROL (208) \r\nCPX (115) 255 252 \r\nROL (208) \r\nLDA (125) 85 87 \r\nROL (208) \r\nEOR (14) 13 \r\nAND (85) 85 85 \r\nPLP (80) \r\nAND (85) 85 85 \r\nPLP (80) \r\nAND (85) 85 85 \r\nPLP (80) \r\nAND (85) 85 117 \r\nPLP (80) \r\nADC (95) 255 253 \r\nPLP (80) \r\nSBC (127) 255 255 \r\nPLP (80) \r\nassembly found, size 45 index 74785\r\nSBC (63) 60 \r\nROL (208) \r\nASL (192) \r\nASL (192) \r\nASL (192) \r\nROL (208) \r\nLDA (124) 204 207 \r\nPLP (80) \r\nADC (87) 255 245 \r\nPLP (80) \r\nEOR (14) 13 \r\nAND (85) 85 85 \r\nPLP (80) \r\nAND (85) 85 85 \r\nPLP (80) \r\nAND (85) 85 85 \r\nPLP (80) \r\nAND (85) 85 85 \r\nPLP (80) \r\nAND (93) 85 87 \r\nPLP (80) \r\nLDA (125) 255 247 \r\nROL (208) \r\nADC (87) 0 13 \r\nPLP (80) \r\nAND (92) 0 3 \r\nPLP (80) \r\nAND (92) 0 3 \r\nPLP (80) \r\nAND (92) 192 51 \r\nPLP (80) \r\nLDA (124) 15 3 \r\nROL (208) \r\nLSR (195) 255 252 \r\nLDY (48) 255 \r\nAND (85) 95 240 \r\nEOR (14) 13 \r\nAND (85) 85 85 \r\nPLP (80) \r\nAND (85) 253 85 \r\nPLP (80) \r\nADC (95) 63 253 \r\nPLP (80) \r\nSBC (127) 204 255 \r\nPLP (80) \r\nassembly found, size 76 index 75003\r\nROL (208) \r\nLSR (195) 51 48 \r\nROL (208) \r\nSBC (127) 0 63 \r\nPLP (80) \r\nAND (85) 255 213 \r\nPLP (80) \r\nEOR (14) 13 \r\nAND (85) 85 85 \r\nPLP (80) \r\nAND (85) 85 85 \r\nPLP (80) \r\nAND (85) 85 85 \r\nPLP (80) \r\nAND (85) 85 85 \r\nPLP (80) \r\nAND (85) 255 245 \r\nPLP (80) \r\nADC (87) 63 205 \r\nPLP (80) \r\nAND (92) 63 3 \r\nPLP (80) \r\nAND (92) 60 3 \r\nPLP (80) \r\nAND (92) 15 3 \r\nPLP (80) \r\nAND (92) 0 3 \r\nPLP (80) \r\nAND (92) 192 51 \r\nPLP (80) \r\nCPX (115) 15 12 \r\nROL (208) \r\nSBC (127) 255 255 \r\nROL (208) \r\nEOR (14) 13 \r\nAND (85) 85 85 \r\nPLP (80) \r\nAND (85) 85 85 \r\nPLP (80) \r\nAND (85) 85 85 \r\nPLP (80) \r\nAND (85) 85 85 \r\nPLP (80) \r\nAND (85) 127 213 \r\nPLP (80) \r\nSBC (127) 240 255 \r\nROL (208) \r\nTAY (112) \r\nINC (243) 48 208 \r\nCPX (115) 15 12 \r\nROL (208) \r\nAND (92) 0 3 \r\nPLP (80) \r\nAND (92) 0 3 \r\nPLP (80) \r\nAND (92) 192 51 \r\nROL (208) \r\nCPX (115) 15 12 \r\nROL (208) \r\nSBC (127) 255 255 \r\nROL (208) \r\nEOR (14) 13 \r\nAND (85) 85 85 \r\nPLP (80) \r\nAND (85) 95 245 \r\nPLP (80) \r\nAND (85) 240 15 \r\nPLP (80) \r\nADC (87) 48 12 \r\nROL (208) \r\nADC (87) 15 240 \r\nROL (208) \r\nAND (92) 192 3 \r\nLDY (48) 92 \r\nSBC (63) 252 \r\nLDY (48) 95 \r\nassembly found, size 37 index 75080\r\nAND (85) 85 85 \r\nPLP (80) \r\nAND (85) 85 85 \r\nPLP (80) \r\nAND (85) 127 213 \r\nPLP (80) \r\nSBC (127) 240 255 \r\nROL (208) \r\nTAY (112) \r\nINC (243) 48 208 \r\nCPX (115) 15 12 \r\nROL (208) \r\nAND (92) 0 3 \r\nPLP (80) \r\nAND (92) 0 3 \r\nPLP (80) \r\nAND (92) 192 51 \r\nROL (208) \r\nCPX (115) 15 12 \r\nROL (208) \r\nSBC (127) 255 255 \r\nROL (208) \r\nEOR (14) 13 \r\nAND (85) 85 85 \r\nPLP (80) \r\nAND (85) 95 245 \r\nPLP (80) \r\nAND (85) 240 15 \r\nPLP (80) \r\nADC (87) 48 12 \r\nROL (208) \r\nADC (87) 15 240 \r\nROL (208) \r\nAND (92) 192 3 \r\nLDY (48) 92 \r\nSBC (63) 252 \r\nLDY (48) 95 \r\nassembly found, size 42 index 75279\r\nORA (12) 55 \r\nROL (208) \r\nADC (87) 255 245 \r\nPLP (80) \r\nEOR (14) 13 \r\nAND (85) 127 85 \r\nPLP (80) \r\nAND (85) 115 85 \r\nPLP (80) \r\nAND (85) 127 85 \r\nPLP (80) \r\nAND (85) 93 85 \r\nPLP (80) \r\nADC (95) 255 253 \r\nPLP (80) \r\nAND (92) 12 13 \r\nPLP (80) \r\nAND (92) 0 13 \r\nPLP (80) \r\nAND (92) 0 13 \r\nPLP (80) \r\nAND (92) 192 205 \r\nPLP (80) \r\nLDA (124) 63 15 \r\nPLP (80) \r\nSBC (127) 192 255 \r\nPLP (80) \r\nTAY (112) \r\nSBC (63) 3 \r\nPLP (80) \r\nSBC (127) 255 255 \r\nPLP (80) \r\nEOR (14) 13 \r\nADC (87) 255 245 \r\nPLP (80) \r\nADC (95) 243 253 \r\nPLP (80) \r\nSBC (127) 0 63 \r\nPLP (80) \r\nLDA (124) 0 15 \r\nPLP (80) \r\nTAY (112) \r\nassembly found, size 30 index 75361\r\nPLP (80) \r\nSBC (127) 192 255 \r\nPLP (80) \r\nASL (192) \r\nSBC (63) 0 \r\nROL (208) \r\nASL (192) \r\nCPX (51) 48 \r\nROL (208) \r\nLSR (195) 48 255 \r\nPLP (80) \r\nSBC (127) 192 13 \r\nPLP (80) \r\nAND (92) 63 13 \r\nPLP (80) \r\nADC (87) 192 245 \r\nPLP (80) \r\nAND (85) 255 213 \r\nPLP (80) \r\nEOR (14) 13 \r\nAND (85) 85 85 \r\nPLP (80) \r\nAND (85) 117 213 \r\nPLP (80) \r\nADC (95) 127 223 \r\nPLP (80) \r\nSBC (119) 255 253 \r\nROL (208) \r\nADC (87) 255 253 \r\nPLP (80) \r\nassembly found, size 28 index 75433\r\nASL (192) \r\nCPX (51) 112 \r\nAND (92) 63 195 \r\nPLP (80) \r\nADC (87) 240 253 \r\nPLP (80) \r\nAND (85) 95 85 \r\nPLP (80) \r\nEOR (14) 13 \r\nAND (85) 85 85 \r\nPLP (80) \r\nAND (85) 85 85 \r\nPLP (80) \r\nADC (95) 85 125 \r\nPLP (80) \r\nSBC (127) 213 255 \r\nPLP (80) \r\nSBC (127) 247 255 \r\nPLP (80) \r\nADC (95) 255 253 \r\nPLP (80) \r\nSBC (127) 255 255 \r\nPLP (80) \r\nSBC (127) 255 255 \r\nPLP (80) \r\nCPX (115) 255 243 \r\nPLP (80) \r\nTAY (112) \r\nassembly found, size 30 index 75588\r\nORA (12) 48 \r\nLSR (195) 0 12 \r\nLDY (48) 195 \r\nLDY (48) 204 \r\nLDY (48) 127 \r\nASL (192) \r\nSBC (63) 208 \r\nAND (85) 192 53 \r\nPLP (80) \r\nAND (85) 127 213 \r\nPLP (80) \r\nEOR (14) 13 \r\nAND (85) 85 85 \r\nPLP (80) \r\nAND (85) 85 87 \r\nROL (208) \r\nAND (85) 255 247 \r\nROL (208) \r\nADC (87) 255 255 \r\nPLP (80) \r\nADC (95) 255 255 \r\nPLP (80) \r\nADC (95) 0 15 \r\nROL (208) \r\nLDA (124) 0 3 \r\nROL (208) \r\nLDA (124) 0 3 \r\nROL (208) \r\nLDA (124) 192 51 \r\nROL (208) \r\nassembly found, size 101 index 81383\r\nORA (68) 68 \r\nORA (68) 68 \r\nEOR (70) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 17 \r\nRTS (18) \r\nSTX (161) 26 \r\nassembly found, size 50 index 81485\r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 17 \r\nRTS (18) \r\nSTX (161) 26 \r\nassembly found, size 100 index 81761\r\nCLI (74) \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nBVS (26) 170 \r\nROL (145) 17 \r\nBIT (17) 26 \r\nassembly found, size 49 index 81862\r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nBIT (17) 17 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nORA (68) 68 \r\nBVS (26) 170 \r\nROL (145) 17 \r\nBIT (17) 26 \r\n[2, 2, 2, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 2, 2, 1, 2, 2, 3, 3, 2, 2, 2, 2, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 2, 2, 2, 2, 3, 2, 2, 3, 2, 2, 3, 3, 1, 1, 2, 2, 2, 3, 3, 3, 2, 2, 2, 2, 3, 3, 1, 1, 3, 3, 3, 2, 2, 2, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 2, 2, 2, 3, 3, 1, 2, 2, 3, 3, 1, 2, 2, 2, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 2, 2, 3, 3, 1, 2, 2, 3, 3, 1, 1, 2, 2, 2, 3, 3, 3, 2, 2, 1, 1, 1, 2, 2, 3, 3, 3, 2, 2, 2, 2, 3, 2, 2, 3, 1, 1, 1, 1, 1, 1]\r\n[105, 101, 117, 109, 125, 121, 97, 113, 41, 37, 53, 45, 61, 57, 33, 49, 10, 6, 22, 14, 30, 144, 176, 240, 36, 44, 48, 208, 16, 80, 112, 24, 216, 88, 184, 201, 197, 213, 205, 221, 217, 193, 209, 224, 228, 236, 192, 196, 204, 198, 214, 206, 222, 202, 136, 73, 69, 85, 77, 93, 89, 65, 81, 230, 246, 238, 254, 232, 200, 76, 108, 32, 169, 165, 181, 173, 189, 185, 161, 177, 162, 166, 182, 174, 190, 160, 164, 180, 172, 188, 74, 70, 86, 78, 94, 234, 9, 5, 21, 13, 29, 25, 1, 17, 72, 8, 104, 40, 42, 38, 54, 46, 62, 106, 102, 118, 110, 126, 64, 96, 233, 229, 245, 237, 253, 249, 225, 241, 56, 248, 120, 133, 149, 141, 157, 153, 129, 145, 134, 150, 142, 132, 148, 140, 170, 168, 186, 138, 154, 152]\r\n[86, 23, 31, 87, 95, 94, 22, 30, 84, 21, 29, 85, 93, 92, 20, 28, 192, 129, 137, 193, 201, 40, 56, 58, 17, 81, 24, 42, 8, 10, 26, 72, 106, 74, 120, 102, 39, 47, 103, 111, 110, 38, 46, 50, 51, 115, 34, 35, 99, 163, 171, 227, 235, 226, 96, 70, 7, 15, 71, 79, 78, 6, 14, 179, 187, 243, 251, 114, 98, 67, 83, 16, 116, 53, 61, 117, 125, 124, 52, 60, 176, 177, 185, 241, 249, 48, 49, 57, 113, 121, 194, 131, 139, 195, 203, 242, 68, 5, 13, 69, 77, 76, 4, 12, 66, 64, 82, 80, 208, 145, 153, 209, 217, 210, 147, 155, 211, 219, 2, 18, 118, 55, 63, 119, 127, 126, 54, 62, 88, 122, 90, 37, 45, 101, 109, 108, 36, 44, 161, 169, 225, 33, 41, 97, 240, 112, 248, 224, 232, 104]\r\n" }, { "path": "disassembler/bytecode.txt", "content": "001: ADC #dd ADC A,dd 69H 56H 2 2 cpu3 ; immediate\r\n002: ADC aa ADC A,(aa) 65H 17H 2 3 cpu3 ; zero page\r\n003: AND #dd AND A,dd 29H 54H 2 2 cpu3 ; immediate\r\n004: AND aa AND A,(aa) 25H 15H 2 3 cpu3 ; zero page\r\n005: BCC ?? JR NC,?? 90H 28H 2 2 cpu3 ; relative\r\n006: BCS ?? JR C,?? B0H 38H 2 2 cpu3 ; relative\r\n007: BEQ ?? JR Z,?? F0H 3AH 2 2 cpu3 ; relative\r\n008: BIT aa BIT (aa) 24H 11H 2 3 cpu5 ; zero page\r\n009: BIT aaaa BIT (aaaa) 2CH 51H 3 4 cpu5 ; absolute\r\n010: BMI ?? JR M,?? 30H 18H 2 2 cpu3 ; relative\r\n011: BNE ?? JR NZ,?? D0H 2AH 2 2 cpu3 ; relative\r\n012: BPL ?? JR P,?? 10H 08H 2 2 cpu3 ; relative\r\n013: BRK BRK 00H 00H 1 7 cpu3 ; implied\r\n014: BVC ?? JR NOV,?? 50H 0AH 2 2 cpu3 ; relative\r\n015: BVS ?? JR OV,?? 70H 1AH 2 2 cpu3 ; relative\r\n016: CLC CCF 18H 48H 1 2 cpu3 ; implied\r\n017: CLI EI 58H 4AH 1 2 cpu3 ; implied\r\n018: CLV CVF B8H 78H 1 2 cpu3 ; implied\r\n019: CMP #dd CP A,dd C9H 66H 2 2 cpu3 ; immediate\r\n020: CMP aa CP A,(aa) C5H 27H 2 3 cpu3 ; zero page\r\n021: CMP aa,X CP A,(aa+X) D5H 2FH 2 4 cpu3 ;zero page indexed x\r\n022: CPX #dd CP X,dd E0H 32H 2 2 cpu3 ; immediate\r\n023: CPX aa CP X,(aa) E4H 33H 2 3 cpu3 ; zero page\r\n024: DEC aa DEC (aa) C6H A3H 2 5 cpu3 ; zero page\r\n025: DEC aa,X DEC (aa+X) D6H ABH 2 6 cpu5 ;zero page indexed x\r\n026: DEX DEC X CAH E2H 1 2 cpu3 ; implied\r\n027: EOR #dd XOR A,dd 49H 46H 2 2 cpu3 ; immediate\r\n028: EOR aa XOR A,(aa) 45H 07H 2 3 cpu3 ; zero page\r\n029: EOR aa,X XOR A,(aa+X) 55H 0FH 2 4 cpu5 ;zero page indexed x\r\n030: INC aa INC (aa) E6H B3H 2 5 cpu3 ; zero page\r\n031: INX INC X E8H 72H 1 2 cpu3 ; implied\r\n032: JMP aaaa JP aaaa 4CH 43H 3 3 cpu3 ; absolute\r\n033: JMP (aaaa) JP (aaaa) 6CH 53H 3 5 cpu3 ; indirect absolut\r\n034: JSR aaaa CALL aaaa 20H 10H 3 6 cpu3 ; absolute\r\n035: LDA #dd LD A,dd A9H 74H 2 2 cpu3 ; immediate\r\n036: LDA aa LD A,(aa) A5H 35H 2 3 cpu3 ; zero page\r\n037: LDA aa,X LD A,(aa+X) B5H 3DH 2 4 cpu3 ;zero page indexed x\r\n038: LDA aaaa LD A,(aaaa) ADH 75H 3 4 cpu3 ; absolute\r\n039: LDA aaaa,X LD A,(aaaa+X) BDH 7DH 3 4 cpu3 ;absolute indexed x\r\n040: LDA (aa,X) LD A,((aa+X)) A1H 34H 2 6 cpu3 ; indexed indirect x\r\n041: LDX #dd LD X,dd A2H B0H 2 2 cpu3 ; immediate\r\n042: LDX aa LD X,(aa) A6H B1H 2 3 cpu3 ; zero page\r\n043: LDX aaaa LD X,(aaaa) AEH F1H 3 4 cpu5 ; absolute\r\n044: NOP NOP EAH F2H 1 2 cpu3 ; implied\r\n045: ORA #dd OR A,dd 09H 44H 2 2 cpu3 ; immediate\r\n046: ORA aa OR A,(aa) 05H 05H 2 3 cpu3 ; zero page\r\n047: PHA PUSH A 48H 42H 1 3 cpu3 ; implied\r\n048: PHP PUSH F 08H 40H 1 3 cpu3 ; implied\r\n049: PLA POP A 68H 52H 1 4 cpu3 ; implied\r\n050: PLP POP F 28H 50H 1 4 cpu3 ; implied\r\n051: ROL A ROL A 2AH D0H 1 2 cpu3 ; accumulator\r\n052: ROL aa ROL (aa) 26H 91H 2 5 cpu3 ; zero page\r\n053: ROR A ROR A 6AH D2H 1 2 cpu3 ; accumulator\r\n054: ROR aa ROR (aa) 66H 93H 2 5 cpu3 ; zero page\r\n055: RTI RETI 40H 02H 1 6 cpu3 ; implied\r\n056: RTS RET 60H 12H 1 6 cpu3 ; implied\r\n057: SBC #dd SBC A,dd E9H 76H 2 2 cpu3 ; immediate\r\n058: SBC aa SBC A,(aa) E5H 37H 2 3 cpu3 ; zero page\r\n059: SEC SCF 38H 58H 1 2 cpu3 ; implied\r\n060: SEI DI 78H 5AH 1 2 cpu3 ; implied\r\n061: STA aa LD (aa),A 85H 25H 2 3 cpu3 ; zero page\r\n062: STA aa,X LD (aa+X),A 95H 2DH 2 4 cpu3 ;zero page indexed x\r\n063: STA (aa,X) LD ((aa+X)),A 81H 24H 2 6 cpu3 ; indexed indirect x\r\n064: STX aa LD (aa),X 86H A1H 2 3 cpu3 ; zero page\r\n065: STX aaaa LD (aaaa),X 8EH E1H 3 4 cpu3 ; absolute\r\n066: TAX LD X,A AAH F0H 1 2 cpu5 ; implied\r\n067: TSX LD X,SP BAH F8H 1 2 cpu3 ; implied\r\n068: TXA LD A,X 8AH E0H 1 2 cpu5 ; implied\r\n069: TXS LD SP,X 9AH E8H 1 2 cpu3 ; implied" }, { "path": "disassembler/bytecoden.txt", "content": "001: ADC #dd ADC A,dd 69H 56H 2 2 cpu3 ; immediate\r\n002: ADC aa ADC A,(aa) 65H 17H 2 3 cpu3 ; zero page\r\n003: ADC aa,X ADC A,(aa+X) 75H 1FH 2 4 6502 ;zero page indexed x\r\n004: ADC aaaa ADC A,(aaaa) 6DH 57H 3 4 6502 ; absolute\r\n005: ADC aaaa,X ADC A,(aaaa+X) 7DH 5FH 3 4 6502 ;absolute indexed x\r\n006: ADC aaaa,Y ADC A,(aaaa+Y) 79H 5EH 3 4 6502 ;absolute indexed y\r\n007: ADC (aa,X) ADC A,((aa+X)) 61H 16H 2 6 6502 ; indexed indirect x\r\n008: ADC (aa),Y ADC A,((aa)+Y) 71H 1EH 2 5 6502 ; indirect indexed y\r\n009: AND #dd AND A,dd 29H 54H 2 2 cpu3 ; immediate\r\n010: AND aa AND A,(aa) 25H 15H 2 3 cpu3 ; zero page\r\n011: AND aa,X AND A,(aa+X) 35H 1DH 2 4 6502 ;zero page indexed x\r\n012: AND aaaa AND A,(aaaa) 2DH 55H 3 4 6502 ; absolute\r\n013: AND aaaa,X AND A,(aaaa+X) 3DH 5DH 3 4 6502 ;absolute indexed x\r\n014: AND aaaa,Y AND A,(aaaa+Y) 39H 5CH 3 4 6502 ;absolute indexed y\r\n015: AND (aa,X) AND A,((aa+X)) 21H 14H 2 6 6502 ; indexed indirect x\r\n016: AND (aa),Y AND A,((aa)+Y) 31H 1CH 2 5 6502 ; indirect indexed y\r\n017: ASL A ASL A 0AH C0H 1 2 6502 ; accumulator\r\n018: ASL aa ASL (aa) 06H 81H 2 5 6502 ; zero page\r\n019: ASL aa,X ASL (aa+X) 16H 89H 2 6 6502 ;zero page indexed x\r\n020: ASL aaaa ASL (aaaa) 0EH C1H 3 6 6502 ; absolute\r\n021: ASL aaaa,X ASL (aaaa+X) 1EH C9H 3 7 6502 ;absolute indexed x\r\n022: BCC ?? JR NC,?? 90H 28H 2 2 cpu3 ; relative\r\n023: BCS ?? JR C,?? B0H 38H 2 2 cpu3 ; relative\r\n024: BEQ ?? JR Z,?? F0H 3AH 2 2 cpu3 ; relative\r\n025: BIT aa BIT (aa) 24H 11H 2 3 cpu5 ; zero page\r\n026: BIT aaaa BIT (aaaa) 2CH 51H 3 4 cpu5 ; absolute\r\n027: BMI ?? JR M,?? 30H 18H 2 2 cpu3 ; relative\r\n028: BNE ?? JR NZ,?? D0H 2AH 2 2 cpu3 ; relative\r\n029: BPL ?? JR P,?? 10H 08H 2 2 cpu3 ; relative\r\n030: BRK BRK 00H 00H 1 7 cpu3 ; implied\r\n031: BVC ?? JR NOV,?? 50H 0AH 2 2 cpu3 ; relative\r\n032: BVS ?? JR OV,?? 70H 1AH 2 2 cpu3 ; relative\r\n033: CLC CCF 18H 48H 1 2 cpu3 ; implied\r\n034: CLD CDF D8H 6AH 1 2 6502 ; implied\r\n035: CLI EI 58H 4AH 1 2 cpu3 ; implied\r\n036: CLV CVF B8H 78H 1 2 cpu3 ; implied\r\n037: CMP #dd CP A,dd C9H 66H 2 2 cpu3 ; immediate\r\n038: CMP aa CP A,(aa) C5H 27H 2 3 cpu3 ; zero page\r\n039: CMP aa,X CP A,(aa+X) D5H 2FH 2 4 cpu3 ;zero page indexed x\r\n040: CMP aaaa CP A,(aaaa) CDH 67H 3 4 6502 ; absolute\r\n041: CMP aaaa,X CP A,(aaaa+X) DDH 6FH 3 4 6502 ;absolute indexed x\r\n042: CMP aaaa,Y CP A,(aaaa+Y) D9H 6EH 3 4 6502 ;absolute indexed y\r\n043: CMP (aa,X) CP A,((aa+X)) C1H 26H 2 6 6502 ; indexed indirect x\r\n044: CMP (aa),Y CP A,((aa)+Y) D1H 2EH 2 5 6502 ; indirect indexed y\r\n045: CPX #dd CP X,dd E0H 32H 2 2 cpu3 ; immediate\r\n046: CPX aa CP X,(aa) E4H 33H 2 3 cpu3 ; zero page\r\n047: CPX aaaa CP X,(aaaa) ECH 73H 3 4 6502 ; absolute\r\n048: CPY #dd CP Y,dd C0H 22H 2 2 6502 ; immediate\r\n049: CPY aa CP Y,(aa) C4H 23H 2 3 6502 ; zero page\r\n050: CPY aaaa CP Y,(aaaa) CCH 63H 3 4 6502 ; absolute\r\n051: DEC aa DEC (aa) C6H A3H 2 5 cpu3 ; zero page\r\n052: DEC aa,X DEC (aa+X) D6H ABH 2 6 cpu5 ;zero page indexed x\r\n053: DEC aaaa DEC (aaaa) CEH E3H 3 6 6502 ; absolute\r\n054: DEC aaaa,X DEC (aaaa+X) DEH EBH 3 7 6502 ;absolute indexed x\r\n055: DEX DEC X CAH E2H 1 2 cpu3 ; implied\r\n056: DEY DEC Y 88H 60H 1 2 6502 ; implied\r\n057: EOR #dd XOR A,dd 49H 46H 2 2 cpu3 ; immediate\r\n058: EOR aa XOR A,(aa) 45H 07H 2 3 cpu3 ; zero page\r\n059: EOR aa,X XOR A,(aa+X) 55H 0FH 2 4 cpu5 ;zero page indexed x\r\n060: EOR aaaa XOR A,(aaaa) 4DH 47H 3 4 6502 ; absolute\r\n061: EOR aaaa,X XOR A,(aaaa+X) 5DH 4FH 3 4 6502 ;absolute indexed x\r\n062: EOR aaaa,Y XOR A,(aaaa+Y) 59H 4EH 3 4 6502 ;absolute indexed y\r\n063: EOR (aa,X) XOR A,((aa+X)) 41H 06H 2 6 6502 ; indexed indirect x\r\n064: EOR (aa),Y XOR A,((aa)+Y) 51H 0EH 2 5 6502 ; indirect indexed y\r\n065: INC aa INC (aa) E6H B3H 2 5 cpu3 ; zero page\r\n066: INC aa,X INC (aa+X) F6H BBH 2 6 6502 ;zero page indexed x\r\n067: INC aaaa INC (aaaa) EEH F3H 3 6 6502 ; absolute\r\n068: INC aaaa,X INC (aaaa+X) FEH FBH 3 7 6502 ;absolute indexed x\r\n069: INX INC X E8H 72H 1 2 cpu3 ; implied\r\n070: INY INC Y C8H 62H 1 2 6502 ; implied\r\n071: JMP aaaa JP aaaa 4CH 43H 3 3 cpu3 ; absolute\r\n072: JMP (aaaa) JP (aaaa) 6CH 53H 3 5 cpu3 ; indirect absolut\r\n073: JSR aaaa CALL aaaa 20H 10H 3 6 cpu3 ; absolute\r\n074: LDA #dd LD A,dd A9H 74H 2 2 cpu3 ; immediate\r\n075: LDA aa LD A,(aa) A5H 35H 2 3 cpu3 ; zero page\r\n076: LDA aa,X LD A,(aa+X) B5H 3DH 2 4 cpu3 ;zero page indexed x\r\n077: LDA aaaa LD A,(aaaa) ADH 75H 3 4 cpu3 ; absolute\r\n078: LDA aaaa,X LD A,(aaaa+X) BDH 7DH 3 4 cpu3 ;absolute indexed x\r\n079: LDA aaaa,Y LD A,(aaaa+Y) B9H 7CH 3 4 6502 ;absolute indexed y\r\n080: LDA (aa,X) LD A,((aa+X)) A1H 34H 2 6 cpu3 ; indexed indirect x\r\n081: LDA (aa),Y LD A,((aa)+Y) B1H 3CH 2 5 6502 ; indirect indexed y\r\n082: LDX #dd LD X,dd A2H B0H 2 2 cpu3 ; immediate\r\n083: LDX aa LD X,(aa) A6H B1H 2 3 cpu3 ; zero page\r\n084: LDX aa,Y LD X,(aa+Y) B6H B9H 2 4 6502 ;zero page indexed y\r\n085: LDX aaaa LD X,(aaaa) AEH F1H 3 4 cpu5 ; absolute\r\n086: LDX aaaa,Y LD X,(aaaa+Y) BEH F9H 3 4 6502 ;absolute indexed y\r\n087: LDY #dd LD Y,dd A0H 30H 2 2 6502 ; immediate\r\n088: LDY aa LD Y,(aa) A4H 31H 2 3 6502 ; zero page\r\n089: LDY aa,X LD Y,(aa+X) B4H 39H 2 4 6502 ;zero page indexed x\r\n090: LDY aaaa LD Y,(aaaa) ACH 71H 3 4 6502 ; absolute\r\n091: LDY aaaa,X LD Y,(aaaa+X) BCH 79H 3 4 6502 ;absolute indexed x\r\n092: LSR A LSR A 4AH C2H 1 2 6502 ; accumulator\r\n093: LSR aa LSR (aa) 46H 83H 2 5 6502 ; zero page\r\n094: LSR aa,X LSR (aa+X) 56H 8BH 2 6 6502 ;zero page indexed x\r\n095: LSR aaaa LSR (aaaa) 4EH C3H 3 6 6502 ; absolute\r\n096: LSR aaaa,X LSR (aaaa+X) 5EH CBH 3 7 6502 ;absolute indexed x\r\n097: NOP NOP EAH F2H 1 2 cpu3 ; implied\r\n098: ORA #dd OR A,dd 09H 44H 2 2 cpu3 ; immediate\r\n099: ORA aa OR A,(aa) 05H 05H 2 3 cpu3 ; zero page\r\n100: ORA aa,X OR A,(aa+X) 15H 0DH 2 4 6502 ;zero page indexed x\r\n101: ORA aaaa OR A,(aaaa) 0DH 45H 3 4 6502 ; absolute\r\n102: ORA aaaa,X OR A,(aaaa+X) 1DH 4DH 3 4 6502 ;absolute indexed x\r\n103: ORA aaaa,Y OR A,(aaaa+Y) 19H 4CH 3 4 6502 ;absolute indexed y\r\n104: ORA (aa,X) OR A,((aa+X)) 01H 04H 2 6 6502 ; indexed indirect x\r\n105: ORA (aa),Y OR A,((aa)+Y) 11H 0CH 2 5 6502 ; indirect indexed y\r\n106: PHA PUSH A 48H 42H 1 3 cpu3 ; implied\r\n107: PHP PUSH F 08H 40H 1 3 cpu3 ; implied\r\n108: PLA POP A 68H 52H 1 4 cpu3 ; implied\r\n109: PLP POP F 28H 50H 1 4 cpu3 ; implied\r\n110: ROL A ROL A 2AH D0H 1 2 cpu3 ; accumulator\r\n111: ROL aa ROL (aa) 26H 91H 2 5 cpu3 ; zero page\r\n112: ROL aa,X ROL (aa+X) 36H 99H 2 6 6502 ;zero page indexed x\r\n113: ROL aaaa ROL (aaaa) 2EH D1H 3 6 6502 ; absolute\r\n114: ROL aaaa,X ROL (aaaa+X) 3EH D9H 3 7 6502 ;absolute indexed x\r\n115: ROR A ROR A 6AH D2H 1 2 cpu3 ; accumulator\r\n116: ROR aa ROR (aa) 66H 93H 2 5 cpu3 ; zero page\r\n117: ROR aa,X ROR (aa+X) 76H 9BH 2 6 6502 ;zero page indexed x\r\n118: ROR aaaa ROR (aaaa) 6EH D3H 3 6 6502 ; absolute\r\n119: ROR aaaa,X ROR (aaaa+X) 7EH DBH 3 7 6502 ;absolute indexed x\r\n120: RTI RETI 40H 02H 1 6 cpu3 ; implied\r\n121: RTS RET 60H 12H 1 6 cpu3 ; implied\r\n122: SBC #dd SBC A,dd E9H 76H 2 2 cpu3 ; immediate\r\n123: SBC aa SBC A,(aa) E5H 37H 2 3 cpu3 ; zero page\r\n124: SBC aa,X SBC A,(aa+X) F5H 3FH 2 4 6502 ;zero page indexed x\r\n125: SBC aaaa SBC A,(aaaa) EDH 77H 3 4 6502 ; absolute\r\n126: SBC aaaa,X SBC A,(aaaa+X) FDH 7FH 3 4 6502 ;absolute indexed x\r\n127: SBC aaaa,Y SBC A,(aaaa+Y) F9H 7EH 3 4 6502 ;absolute indexed y\r\n128: SBC (aa,X) SBC A,((aa+X)) E1H 36H 2 6 6502 ; indexed indirect x\r\n129: SBC (aa),Y SBC A,((aa)+Y) F1H 3EH 2 5 6502 ; indirect indexed y\r\n130: SEC SCF 38H 58H 1 2 cpu3 ; implied\r\n131: SED SDF F8H 7AH 1 2 6502 ; implied\r\n132: SEI DI 78H 5AH 1 2 cpu3 ; implied\r\n133: STA aa LD (aa),A 85H 25H 2 3 cpu3 ; zero page\r\n134: STA aa,X LD (aa+X),A 95H 2DH 2 4 cpu3 ;zero page indexed x\r\n135: STA aaaa LD (aaaa),A 8DH 65H 3 4 6502 ; absolute\r\n136: STA aaaa,X LD (aaaa+X),A 9DH 6DH 3 5 6502 ;absolute indexed x\r\n137: STA aaaa,Y LD (aaaa+Y),A 99H 6CH 3 5 6502 ;absolute indexed y\r\n138: STA (aa,X) LD ((aa+X)),A 81H 24H 2 6 cpu3 ; indexed indirect x\r\n139: STA (aa),Y LD ((aa)+Y),A 91H 2CH 2 6 6502 ; indirect indexed y\r\n140: STX aa LD (aa),X 86H A1H 2 3 cpu3 ; zero page\r\n141: STX aa,Y LD (aa+Y),X 96H A9H 2 4 6502 ;zero page indexed y\r\n142: STX aaaa LD (aaaa),X 8EH E1H 3 4 cpu3 ; absolute\r\n143: STY aa LD (aa),Y 84H 21H 2 3 6502 ; zero page\r\n144: STY aa,X LD (aa+X),Y 94H 29H 2 4 6502 ;zero page indexed x\r\n145: STY aaaa LD (aaaa),Y 8CH 61H 3 4 6502 ; absolute\r\n146: TAX LD X,A AAH F0H 1 2 cpu5 ; implied\r\n147: TAY LD Y,A A8H 70H 1 2 6502 ; implied\r\n148: TSX LD X,SP BAH F8H 1 2 cpu3 ; implied\r\n149: TXA LD A,X 8AH E0H 1 2 cpu5 ; implied\r\n150: TXS LD SP,X 9AH E8H 1 2 cpu3 ; implied\r\n151: TYA LD A,Y 98H 68H 1 2 6502 ; implied\r\n" }, { "path": "disassembler/bytecoder.txt", "content": " NO: SYNTAX 6502: SYNTAX 2500: 6502 SUN b c type addressing modes\r\n001: ADC #dd ADC A,dd 69H 56H 2 2 cpu3 ; immediate\r\n002: ADC aa ADC A,(aa) 65H 17H 2 3 cpu3 ; zero page\r\n003: AND #dd AND A,dd 29H 54H 2 2 cpu3 ; immediate\r\n004: AND aa AND A,(aa) 25H 15H 2 3 cpu3 ; zero page\r\n005: BCC ?? JR NC,?? 90H 28H 2 2 cpu3 ; relative\r\n006: BCS ?? JR C,?? B0H 38H 2 2 cpu3 ; relative\r\n007: BEQ ?? JR Z,?? F0H 3AH 2 2 cpu3 ; relative\r\n008: BIT aa BIT (aa) 24H 11H 2 3 cpu5 ; zero page\r\n009: BIT aaaa BIT (aaaa) 2CH 51H 3 4 cpu5 ; absolute\r\n010: BMI ?? JR M,?? 30H 18H 2 2 cpu3 ; relative\r\n011: BNE ?? JR NZ,?? D0H 2AH 2 2 cpu3 ; relative\r\n012: BPL ?? JR P,?? 10H 08H 2 2 cpu3 ; relative\r\n013: BRK BRK 00H 00H 1 7 cpu3 ; implied\r\n014: BVC ?? JR NOV,?? 50H 0AH 2 2 cpu3 ; relative\r\n015: BVS ?? JR OV,?? 70H 1AH 2 2 cpu3 ; relative\r\n016: CLC CCF 18H 48H 1 2 cpu3 ; implied\r\n017: CLI EI 58H 4AH 1 2 cpu3 ; implied\r\n018: CLV CVF B8H 78H 1 2 cpu3 ; implied\r\n019: CMP #dd CP A,dd C9H 66H 2 2 cpu3 ; immediate\r\n020: CMP aa CP A,(aa) C5H 27H 2 3 cpu3 ; zero page\r\n021: CMP aa,X CP A,(aa+X) D5H 2FH 2 4 cpu3 ;zero page indexed x\r\n022: CPX #dd CP X,dd E0H 32H 2 2 cpu3 ; immediate\r\n023: CPX aa CP X,(aa) E4H 33H 2 3 cpu3 ; zero page\r\n024: DEC aa DEC (aa) C6H A3H 2 5 cpu3 ; zero page\r\n025: DEC aa,X DEC (aa+X) D6H ABH 2 6 cpu5 ;zero page indexed x\r\n026: DEX DEC X CAH E2H 1 2 cpu3 ; implied\r\n027: EOR #dd XOR A,dd 49H 46H 2 2 cpu3 ; immediate\r\n028: EOR aa XOR A,(aa) 45H 07H 2 3 cpu3 ; zero page\r\n029: EOR aa,X XOR A,(aa+X) 55H 0FH 2 4 cpu5 ;zero page indexed x\r\n030: INC aa INC (aa) E6H B3H 2 5 cpu3 ; zero page\r\n031: INX INC X E8H 72H 1 2 cpu3 ; implied\r\n032: JMP aaaa JP aaaa 4CH 43H 3 3 cpu3 ; absolute\r\n033: JMP (aaaa) JP (aaaa) 6CH 53H 3 5 cpu3 ; indirect absolut\r\n034: JSR aaaa CALL aaaa 20H 10H 3 6 cpu3 ; absolute\r\n035: LDA #dd LD A,dd A9H 74H 2 2 cpu3 ; immediate\r\n036: LDA aa LD A,(aa) A5H 35H 2 3 cpu3 ; zero page\r\n037: LDA aa,X LD A,(aa+X) B5H 3DH 2 4 cpu3 ;zero page indexed x\r\n038: LDA aaaa LD A,(aaaa) ADH 75H 3 4 cpu3 ; absolute\r\n039: LDA aaaa,X LD A,(aaaa+X) BDH 7DH 3 4 cpu3 ;absolute indexed x\r\n040: LDA (aa,X) LD A,((aa+X)) A1H 34H 2 6 cpu3 ; indexed indirect x\r\n041: LDX #dd LD X,dd A2H B0H 2 2 cpu3 ; immediate\r\n042: LDX aa LD X,(aa) A6H B1H 2 3 cpu3 ; zero page\r\n043: LDX aaaa LD X,(aaaa) AEH F1H 3 4 cpu5 ; absolute\r\n044: NOP NOP EAH F2H 1 2 cpu3 ; implied\r\n045: ORA #dd OR A,dd 09H 44H 2 2 cpu3 ; immediate\r\n046: ORA aa OR A,(aa) 05H 05H 2 3 cpu3 ; zero page\r\n047: PHA PUSH A 48H 42H 1 3 cpu3 ; implied\r\n048: PHP PUSH F 08H 40H 1 3 cpu3 ; implied\r\n049: PLA POP A 68H 52H 1 4 cpu3 ; implied\r\n050: PLP POP F 28H 50H 1 4 cpu3 ; implied\r\n051: ROL A ROL A 2AH D0H 1 2 cpu3 ; accumulator\r\n052: ROL aa ROL (aa) 26H 91H 2 5 cpu3 ; zero page\r\n053: ROR A ROR A 6AH D2H 1 2 cpu3 ; accumulator\r\n054: ROR aa ROR (aa) 66H 93H 2 5 cpu3 ; zero page\r\n055: RTI RETI 40H 02H 1 6 cpu3 ; implied\r\n056: RTS RET 60H 12H 1 6 cpu3 ; implied\r\n057: SBC #dd SBC A,dd E9H 76H 2 2 cpu3 ; immediate\r\n058: SBC aa SBC A,(aa) E5H 37H 2 3 cpu3 ; zero page\r\n059: SEC SCF 38H 58H 1 2 cpu3 ; implied\r\n060: SEI DI 78H 5AH 1 2 cpu3 ; implied\r\n061: STA aa LD (aa),A 85H 25H 2 3 cpu3 ; zero page\r\n062: STA aa,X LD (aa+X),A 95H 2DH 2 4 cpu3 ;zero page indexed x\r\n063: STA (aa,X) LD ((aa+X)),A 81H 24H 2 6 cpu3 ; indexed indirect x\r\n064: STX aa LD (aa),X 86H A1H 2 3 cpu3 ; zero page\r\n065: STX aaaa LD (aaaa),X 8EH E1H 3 4 cpu3 ; absolute\r\n066: TAX LD X,A AAH F0H 1 2 cpu5 ; implied\r\n067: TSX LD X,SP BAH F8H 1 2 cpu3 ; implied\r\n068: TXA LD A,X 8AH E0H 1 2 cpu5 ; implied\r\n069: TXS LD SP,X 9AH E8H 1 2 cpu3 ; implied\r\n" }, { "path": "disassembler/bytecodes.txt", "content": " NO: SYNTAX 6502: SYNTAX 2500: 6502 SUN b c type addressing modes\r\n001: ADC #dd ADC A,dd 69H 56H 2 2 cpu3 ; immediate\r\n002: ADC aa ADC A,(aa) 65H 17H 2 3 cpu3 ; zero page\r\n003: AND #dd AND A,dd 29H 54H 2 2 cpu3 ; immediate\r\n004: AND aa AND A,(aa) 25H 15H 2 3 cpu3 ; zero page\r\n005: BCC ?? JR NC,?? 90H 28H 2 2 cpu3 ; relative\r\n006: BCS ?? JR C,?? B0H 38H 2 2 cpu3 ; relative\r\n007: BEQ ?? JR Z,?? F0H 3AH 2 2 cpu3 ; relative\r\n008: BMI ?? JR M,?? 30H 18H 2 2 cpu3 ; relative\r\n009: BNE ?? JR NZ,?? D0H 2AH 2 2 cpu3 ; relative\r\n010: BPL ?? JR P,?? 10H 08H 2 2 cpu3 ; relative\r\n011: BRK BRK 00H 00H 1 7 cpu3 ; implied\r\n012: BVC ?? JR NOV,?? 50H 0AH 2 2 cpu3 ; relative\r\n013: BVS ?? JR OV,?? 70H 1AH 2 2 cpu3 ; relative\r\n014: CLC CCF 18H 48H 1 2 cpu3 ; implied\r\n015: CLI EI 58H 4AH 1 2 cpu3 ; implied\r\n016: CLV CVF B8H 78H 1 2 cpu3 ; implied\r\n017: CMP #dd CP A,dd C9H 66H 2 2 cpu3 ; immediate\r\n018: CMP aa CP A,(aa) C5H 27H 2 3 cpu3 ; zero page\r\n019: CMP aa,X CP A,(aa+X) D5H 2FH 2 4 cpu3 ;zero page indexed x\r\n020: CPX #dd CP X,dd E0H 32H 2 2 cpu3 ; immediate\r\n021: CPX aa CP X,(aa) E4H 33H 2 3 cpu3 ; zero page\r\n022: DEC aa DEC (aa) C6H A3H 2 5 cpu3 ; zero page\r\n023: DEX DEC X CAH E2H 1 2 cpu3 ; implied\r\n024: EOR #dd XOR A,dd 49H 46H 2 2 cpu3 ; immediate\r\n025: EOR aa XOR A,(aa) 45H 07H 2 3 cpu3 ; zero page\r\n026: INC aa INC (aa) E6H B3H 2 5 cpu3 ; zero page\r\n027: INX INC X E8H 72H 1 2 cpu3 ; implied\r\n028: JMP aaaa JP aaaa 4CH 43H 3 3 cpu3 ; absolute\r\n029: JMP (aaaa) JP (aaaa) 6CH 53H 3 5 cpu3 ; indirect absolut\r\n030: JSR aaaa CALL aaaa 20H 10H 3 6 cpu3 ; absolute\r\n031: LDA #dd LD A,dd A9H 74H 2 2 cpu3 ; immediate\r\n032: LDA aa LD A,(aa) A5H 35H 2 3 cpu3 ; zero page\r\n033: LDA aa,X LD A,(aa+X) B5H 3DH 2 4 cpu3 ;zero page indexed x\r\n034: LDA aaaa LD A,(aaaa) ADH 75H 3 4 cpu3 ; absolute\r\n035: LDA aaaa,X LD A,(aaaa+X) BDH 7DH 3 4 cpu3 ;absolute indexed x\r\n036: LDA (aa,X) LD A,((aa+X)) A1H 34H 2 6 cpu3 ; indexed indirect x\r\n037: LDX #dd LD X,dd A2H B0H 2 2 cpu3 ; immediate\r\n038: LDX aa LD X,(aa) A6H B1H 2 3 cpu3 ; zero page\r\n039: NOP NOP EAH F2H 1 2 cpu3 ; implied\r\n040: ORA #dd OR A,dd 09H 44H 2 2 cpu3 ; immediate\r\n041: ORA aa OR A,(aa) 05H 05H 2 3 cpu3 ; zero page\r\n042: PHA PUSH A 48H 42H 1 3 cpu3 ; implied\r\n043: PHP PUSH F 08H 40H 1 3 cpu3 ; implied\r\n044: PLA POP A 68H 52H 1 4 cpu3 ; implied\r\n045: PLP POP F 28H 50H 1 4 cpu3 ; implied\r\n046: ROL A ROL A 2AH D0H 1 2 cpu3 ; accumulator\r\n047: ROL aa ROL (aa) 26H 91H 2 5 cpu3 ; zero page\r\n048: ROR A ROR A 6AH D2H 1 2 cpu3 ; accumulator\r\n049: ROR aa ROR (aa) 66H 93H 2 5 cpu3 ; zero page\r\n050: RTI RETI 40H 02H 1 6 cpu3 ; implied\r\n051: RTS RET 60H 12H 1 6 cpu3 ; implied\r\n052: SBC #dd SBC A,dd E9H 76H 2 2 cpu3 ; immediate\r\n053: SBC aa SBC A,(aa) E5H 37H 2 3 cpu3 ; zero page\r\n054: SEC SCF 38H 58H 1 2 cpu3 ; implied\r\n055: SEI DI 78H 5AH 1 2 cpu3 ; implied\r\n056: STA aa LD (aa),A 85H 25H 2 3 cpu3 ; zero page\r\n057: STA aa,X LD (aa+X),A 95H 2DH 2 4 cpu3 ;zero page indexed x\r\n058: STA (aa,X) LD ((aa+X)),A 81H 24H 2 6 cpu3 ; indexed indirect x\r\n059: STX aa LD (aa),X 86H A1H 2 3 cpu3 ; zero page\r\n060: STX aaaa LD (aaaa),X 8EH E1H 3 4 cpu3 ; absolute\r\n061: TSX LD X,SP BAH F8H 1 2 cpu3 ; implied\r\n062: TXS LD SP,X 9AH E8H 1 2 cpu3 ; implied\r\n" }, { "path": "disassembler/dissa.py", "content": "a = open(\"bytecoden.txt\")\r\n\r\nf = a.read()\r\nf = f[f.find(\"001:\"):]\r\nt = f.split()\r\n\r\nops = []\r\no6502 = []\r\nosun = []\r\nb = []\r\nindex = 0\r\nfor item in t:\r\n\tif (len(item) ==3) and (item[2] == 'H') and (index != 2):\r\n\t\to6502.append(int(item[:2], 16))\r\n\t\tindex = 2\r\n\telif (index == 1):\r\n\t\tops.append(item)\r\n\t\tindex = 57\t\r\n\telif (index == 2):\r\n\t\tosun.append(int(item[:2], 16))\r\n\t\t#print \"added sun\"\r\n\t\tindex = 3\r\n\telif (index == 3):\r\n\t\tb.append(int(item))\r\n\t\tindex = 4\r\n\t\t#print \"added b\"\r\n\telif (item.find(':') != -1):\r\n\t\tindex = 1\r\n\r\n#print len(osun)\r\n#print len(b)\r\n\r\nc = open(\"testbinary.bin\", 'rb')\r\n\r\ncode = c.read()\r\nosun.pop(ops.index(\"BRK\"))\r\nb.pop(ops.index(\"BRK\"))\r\no6502.pop(ops.index(\"BRK\"))\r\nops.pop(ops.index(\"BRK\"))\r\n#osun = o6502 #comment out for standard\r\ni = 0\r\nwhile(i < len(code)):\r\n\tif (osun.count(ord(code[i])) != 0):\r\n\t\trun = 1\r\n\t\t#print \"inner \" + str(i)\r\n\t\tind = b[osun.index(ord(code[i]))]\r\n\t\twhile osun.count(ord(code[i+ ind])) != 0:\r\n\t\t\trun = run + 1\r\n\t\t\tind = ind + b[osun.index(ord(code[i + ind]))]\r\n\t\tif( run > 25):\r\n\t\t\tprint \"assembly found, size \" + str(run) + \" index \" + str(i)\r\n\t\t\ty = 0\r\n\t\t\tfor x in range(0, run):\r\n\t\t\t\tprint ops[osun.index(ord(code[i + y]))],\r\n\t\t\t\tprint \"(\" + str(osun[osun.index(ord(code[i + y]))]) + \")\",\r\n\t\t\t\t#print b[osun.index(ord(code[i + y]))]\r\n\t\t\t\tfor z in range(1, b[osun.index(ord(code[i + y]))]):\r\n\t\t\t\t\tprint str(ord(code[i + y + z])),\r\n\t\t\t\ty = y + b[osun.index(ord(code[i + y]))]\r\n\t\t\t\tprint \" \"\r\n\t\t\ti = i + run\r\n\ti = i + 1\t\t\t\r\n\r\nprint b\t\r\nprint o6502\r\nprint osun\t\r\n" }, { "path": "figure/Arduino/ClientSide/README.txt", "content": "ser.py -- ROM/Flash dump client\r\nserw.py -- Flash write client" }, { "path": "figure/Arduino/ClientSide/ser.py", "content": "import serial\r\nimport time\r\n\r\n#enter your device file\r\narddev = 'COM5'\r\nbaud = 9600\r\n\r\n#setup - if a Serial object can't be created, a SerialException will be raised.\r\nwhile True:\r\n try:\r\n ser = serial.Serial(arddev, baud)\r\n\r\n #break out of while loop when connection is made\r\n break\r\n except serial.SerialException:\r\n print 'waiting for device ' + arddev + ' to be available'\r\n time.sleep(3)\r\n\r\n#read lines from serial device\r\nf = open(\"dump.txt\", 'wb')\r\nwhile True:\r\n \telement = ser.read()\r\n\tf.write(element)\r\n\tf.flush()" }, { "path": "figure/Arduino/ClientSide/serw.py", "content": "import serial\r\nimport time\r\n\r\n#enter your device file\r\narddev = 'COM5'\r\nbaud = 115200\r\n\r\n#setup - if a Serial object can't be created, a SerialException will be raised.\r\nwhile True:\r\n try:\r\n ser = serial.Serial(arddev, baud)\r\n\r\n #break out of while loop when connection is made\r\n break\r\n except serial.SerialException:\r\n print 'waiting for device ' + arddev + ' to be available'\r\n time.sleep(3)\r\n\r\n#read lines from serial device\r\nf = open(\"in.txt\", 'rb')\r\nb = f.read()\r\na = 0;\r\nwhile True:\r\n\tprint ser.readline();\r\n\t#ser.write(chr((a & 0xff0000) >> 16))\r\n\t#ser.write(chr((a & 0xff00) >> 8))\r\n\t#ser.write(chr(a & 0xff))\r\n\t#ser.write('\\x00');\r\n\t#ser.write('\\x00');\r\n\t#ser.write('\\x00');\r\n\tfor i in range(0, 256):\r\n\t\tprint str(ord(b[a +i]))\r\n\t\tser.write(str(ord(b[a +i])) + \"\\n\")\r\n\ta = a + 256\r\n\t#for i in range(0, 4):\r\n\t#\tprint ser.readline()\r\n\tprint \"address\",\r\n\tprint a\t" }, { "path": "figure/Arduino/GeneralPlusRomDump/GeneralPlusRomDump.ino", "content": "#define DATAOUT 11//MOSI\n#define DATAIN 12//MISO \n#define SPICLOCK 13//sck\n#define SLAVESELECT 10//ss\n\n//opcodes\n#define WREN 6\n#define WRDI 4\n#define RDSR 5\n#define WRSR 1\n#define READ 3\n#define WRITE 2\n\nbyte eeprom_output_data;\nbyte eeprom_input_data=0;\nbyte clr;\nint address=0;\nint once = 0;\n//data buffer\nchar buffer [128];\n\nvoid fill_buffer()\n{\n for (int I=0;I<128;I++)\n {\n buffer[I]=I;\n }\n}\n\nchar spi_transfer(volatile char data)\n{\n SPDR = data; // Start the transmission\n while (!(SPSR & (1<>8)); //send MSByte address first\n // spi_transfer((char)(EEPROM_address)); //send LSByte address\n for(j = 0; j < 0x80000; j++){\n // data1 = spi_transfer(0x00);\n //data = spi_transfer(0x00); //get data byte\n //data2 = spi_transfer(0x00); //get data byte\n //data = spi_transfer(0xFF); \n // if( j%16 == 0){\n // Serial.print(\"\\n\");\n // Serial.print(j, HEX);\n // Serial.print( \": \");\n //}\n // delay(50);\n data = spi_transfer(0x00);\n //Serial.print(\"0x\");\n Serial.print((char)data);\n \n //Serial.print(\" \");\n \n } \n digitalWrite(SLAVESELECT,HIGH); //release chip, signal end transfer\n // Serial.print(data,HEX);\n // Serial.print(\" \");k\n // Serial.print(data2,HEX);\n // Serial.print(\" \");\n // Serial.print(data1,HEX);\n // Serial.print(\" \\r\\n\");\n Serial.print(\" \\n DONE\");\n return data;\n}\n\nvoid loop()\n{\n // Serial.print(\"loop 1\\r\\n\");\n if(once == 0)\n eeprom_output_data = read_eeprom(address);\n \n once = 100;\n// Serial.print(\"loop 2\\r\\n\");\n // Serial.print(eeprom_output_data,DEC);\n //Serial.print('\\n',BYTE);\n //address++;\n //if (address == 128)\n //address = 0;\n delay(500); //pause for readability\n \n\n // digitalWrite(SPICLOCK, HIGH);\n // digitalWrite(DATAOUT, HIGH);\n}\n\n\r\n" }, { "path": "figure/Arduino/GeneralPlusRomWrite/GeneralPlusRomWrite.ino", "content": "#define DATAOUT 11//MOSI\n#define DATAIN 12//MISO \n#define SPICLOCK 13//sck\n#define SLAVESELECT 10//ss\n\n//opcodes\n#define WREN 6\n#define WRDI 4\n#define RDSR 5\n#define WRSR 1\n#define READ 3\n#define WRITE 2\n\nbyte eeprom_output_data;\nbyte eeprom_input_data=0;\nbyte clr;\nint address=0;\nlong int once = 0;\n//data buffer\nchar buffer [128];\n\nvoid fill_buffer()\n{\n for (int I=0;I<128;I++)\n {\n buffer[I]=I;\n }\n}\n\nchar spi_transfer(volatile char data)\n{\n SPDR = data; // Start the transmission\n while (!(SPSR & (1<>8)); //send MSByte address first\n // spi_transfer((char)(EEPROM_address)); //send LSByte address\n for(j = 0; j < 0x80000; j++){\n // data1 = spi_transfer(0x00);\n //data = spi_transfer(0x00); //get data byte\n //data2 = spi_transfer(0x00); //get data byte\n //data = spi_transfer(0xFF); \n // if( j%16 == 0){\n // Serial.print(\"\\n\");\n // Serial.print(j, HEX);\n // Serial.print( \": \");\n //}\n // delay(50);\n data = spi_transfer(0x00);\n //Serial.print(\"0x\");\n Serial.print((char)data);\n \n //Serial.print(\" \");\n \n } \n digitalWrite(SLAVESELECT,HIGH); //release chip, signal end transfer\n // Serial.print(data,HEX);\n // Serial.print(\" \");k\n // Serial.print(data2,HEX);\n // Serial.print(\" \");\n // Serial.print(data1,HEX);\n // Serial.print(\" \\r\\n\");\n // Serial.print(\" \\n DONE\");\n return data;\n}\n\nvoid loop()\n{\n long int i;\n byte b[256];\n Serial.println(\"ready\");\n \n for(i = 0; i < 256; i++){\n b[i] = Serial.parseInt();\n }\n // Serial.print(\"loop 1\\r\\n\");\n if((once %256) == 0){\n // eeprom_output_data = read_eeprom(address);\n digitalWrite(SLAVESELECT,LOW);\n spi_transfer(0x06); //transmit read opcode\n digitalWrite(SLAVESELECT,HIGH);\n digitalWrite(SLAVESELECT,LOW);\n spi_transfer(0xd8); \n spi_transfer(once / 256); \n spi_transfer(0x00); \n spi_transfer(0x00);\n digitalWrite(SLAVESELECT,HIGH); \n delay(1000);\n }\n \n\n digitalWrite(SLAVESELECT,LOW);\n spi_transfer(0x06); //transmit read opcode\n digitalWrite(SLAVESELECT,HIGH);\n digitalWrite(SLAVESELECT,LOW);\n spi_transfer(0x2); \n spi_transfer(once / 256); \n spi_transfer(once % 256); \n spi_transfer(0);\n for(i = 0; i < 256; i++){\n spi_transfer(b[i]);\n }\n digitalWrite(SLAVESELECT,HIGH); \n \n once++;\n \n \n \n \n\n \n// once = 100;\n// Serial.print(\"loop 2\\r\\n\");\n // Serial.print(eeprom_output_data,DEC);\n //Serial.print('\\n',BYTE);\n //address++;\n //if (address == 128)\n //address = 0;\n // delay(500); //pause for readability\n \n\n // digitalWrite(SPICLOCK, HIGH);\n // digitalWrite(DATAOUT, HIGH);\n}\n\n\r\n" }, { "path": "figure/Arduino/README.txt", "content": "GeneralPlusRomDump.pde -- Dumps a GeneralPlus Low Power SPI ROM\r\nGeneralPlusRomWrite.pde -- Dumps GeneralPlus SPI Flash\r\nClientSide -- Client side scripts for dumps or writes" }, { "path": "figure/README", "content": "Figure code\r\n\r\n/Arduino -- Arduino code to dump and write memory\r\n/ROMDump -- Actual ROM dumps\r\n/scripts -- Misc scripts\r\n/SignalPulls -- Code to determine when a figure is read" }, { "path": "figure/ROMDump/README", "content": "ROM dumps\r\n\r\n/imgs/ - images extracted from the Memetchi figure dump\r\n/makikoimgs/ - images extracted from a Makiko figure dump\r\n\t- adds.txt contains addresses of images in figure dump\r\n/ROMDump - Memetchi figure dump\r\n/maikio - Makiko figure dump\r\n" }, { "path": "figure/ROMDump/imgs/adds.txt", "content": "20 20\r\nimg 0 at 2884\r\n20 20\r\nimg 1 at 2986\r\n20 20\r\nimg 2 at 3088\r\n20 20\r\nimg 3 at 3190\r\n20 20\r\nimg 4 at 3292\r\n20 20\r\nimg 5 at 3394\r\n20 20\r\nimg 6 at 3496\r\n20 20\r\nimg 7 at 3598\r\n20 20\r\nimg 8 at 3700\r\n20 20\r\nimg 9 at 3802\r\n20 20\r\nimg 10 at 3904\r\n20 20\r\nimg 11 at 4006\r\n20 20\r\nimg 12 at 4108\r\n20 20\r\nimg 13 at 4210\r\n20 20\r\nimg 14 at 4312\r\n20 20\r\nimg 15 at 4414\r\n20 20\r\nimg 16 at 4516\r\n20 20\r\nimg 17 at 4618\r\n20 20\r\nimg 18 at 4720\r\n20 20\r\nimg 19 at 4822\r\n20 20\r\nimg 20 at 4924\r\n20 20\r\nimg 21 at 5026\r\n20 20\r\nimg 22 at 5128\r\n20 20\r\nimg 23 at 5230\r\n20 20\r\nimg 24 at 5332\r\n20 20\r\nimg 25 at 5434\r\n48 31\r\nPadded to 48 by 31\r\nimg 26 at 5808\r\n48 31\r\nPadded to 48 by 31\r\nimg 27 at 6182\r\n48 31\r\nPadded to 48 by 31\r\nimg 28 at 6556\r\n48 31\r\nPadded to 48 by 31\r\nimg 29 at 6930\r\n48 31\r\nPadded to 48 by 31\r\nimg 30 at 7304\r\n48 31\r\nPadded to 48 by 31\r\nimg 31 at 7678\r\n48 31\r\nPadded to 48 by 31\r\nimg 32 at 8052\r\n48 31\r\nPadded to 48 by 31\r\nimg 33 at 8426\r\n48 13\r\nPadded to 48 by 13\r\nimg 34 at 8584\r\n48 13\r\nPadded to 48 by 13\r\nimg 35 at 8742\r\n28 31\r\nPadded to 28 by 31\r\nimg 36 at 8961\r\n18 12\r\nimg 37 at 9023\r\n18 12\r\nimg 38 at 9085\r\n18 12\r\nimg 39 at 9147\r\n18 12\r\nimg 40 at 9209\r\n18 12\r\nimg 41 at 9271\r\n17 21\r\nPadded to 20 by 21\r\nimg 42 at 9378\r\n17 21\r\nPadded to 20 by 21\r\nimg 43 at 9485\r\n32 8\r\nimg 44 at 9551\r\n32 8\r\nimg 45 at 9617\r\n32 8\r\nimg 46 at 9683\r\n32 8\r\nimg 47 at 9749\r\n32 8\r\nimg 48 at 9815\r\n32 8\r\nimg 49 at 9881\r\n8 8\r\nimg 50 at 9899\r\n8 8\r\nimg 51 at 9917\r\n8 8\r\nimg 52 at 9935\r\n8 8\r\nimg 53 at 9953\r\n8 8\r\nimg 54 at 9971\r\n1 1\r\nPadded to 4 by 1\r\nimg 55 at 9974\r\n12 12\r\nimg 56 at 10012\r\n12 12\r\nimg 57 at 10050\r\n12 12\r\nimg 58 at 10088\r\n12 12\r\nimg 59 at 10126\r\n12 12\r\nimg 60 at 10164\r\n12 12\r\nimg 61 at 10202\r\n12 12\r\nimg 62 at 10240\r\n12 12\r\nimg 63 at 10278\r\n12 12\r\nimg 64 at 10316\r\n12 12\r\nimg 65 at 10354\r\n48 31\r\nPadded to 48 by 31\r\nimg 66 at 10728\r\n1 1\r\nPadded to 4 by 1\r\nimg 67 at 10731\r\n16 16\r\nimg 68 at 10797\r\n16 16\r\nimg 69 at 10863\r\n16 16\r\nimg 70 at 10929\r\n16 16\r\nimg 71 at 10995\r\n16 16\r\nimg 72 at 11061\r\n16 16\r\nimg 73 at 11127\r\n16 16\r\nimg 74 at 11193\r\n16 16\r\nimg 75 at 11259\r\n16 16\r\nimg 76 at 11325\r\n16 16\r\nimg 77 at 11391\r\n30 12\r\nimg 78 at 11489\r\n30 12\r\nimg 79 at 11587\r\n30 12\r\nimg 80 at 11685\r\n30 12\r\nimg 81 at 11783\r\n30 12\r\nimg 82 at 11881\r\n30 12\r\nimg 83 at 11979\r\n30 12\r\nimg 84 at 12077\r\n30 12\r\nimg 85 at 12175\r\n30 12\r\nimg 86 at 12273\r\n30 12\r\nimg 87 at 12371\r\n17 25\r\nPadded to 20 by 25\r\nimg 88 at 12498\r\n20 19\r\nPadded to 20 by 19\r\nimg 89 at 12595\r\n20 19\r\nPadded to 20 by 19\r\nimg 90 at 12692\r\n20 19\r\nPadded to 20 by 19\r\nimg 91 at 12789\r\n20 19\r\nPadded to 20 by 19\r\nimg 92 at 12886\r\n20 19\r\nPadded to 20 by 19\r\nimg 93 at 12983\r\n19 18\r\nPadded to 20 by 18\r\nimg 94 at 13075\r\n20 18\r\nPadded to 20 by 18\r\nimg 95 at 13167\r\n20 18\r\nPadded to 20 by 18\r\nimg 96 at 13259\r\n7 31\r\nPadded to 8 by 31\r\nimg 97 at 13323\r\n31 17\r\nPadded to 32 by 17\r\nimg 98 at 13461\r\n48 31\r\nPadded to 48 by 31\r\nimg 99 at 13835\r\n48 31\r\nPadded to 48 by 31\r\nimg 100 at 14209\r\n48 31\r\nPadded to 48 by 31\r\nimg 101 at 14583\r\n48 31\r\nPadded to 48 by 31\r\nimg 102 at 14957\r\n48 22\r\nPadded to 48 by 22\r\nimg 103 at 15223\r\n48 31\r\nPadded to 48 by 31\r\nimg 104 at 15597\r\n48 31\r\nPadded to 48 by 31\r\nimg 105 at 15971\r\n48 31\r\nPadded to 48 by 31\r\nimg 106 at 16345\r\n48 31\r\nPadded to 48 by 31\r\nimg 107 at 16719\r\n48 15\r\nPadded to 48 by 15\r\nimg 108 at 16901\r\n48 15\r\nPadded to 48 by 15\r\nimg 109 at 17083\r\n48 31\r\nPadded to 48 by 31\r\nimg 110 at 17457\r\n48 31\r\nPadded to 48 by 31\r\nimg 111 at 17831\r\n48 3\r\nPadded to 48 by 3\r\nimg 112 at 17869\r\n25 24\r\nimg 113 at 18039\r\n48 6\r\nPadded to 48 by 6\r\nimg 114 at 18113\r\n48 31\r\nPadded to 48 by 31\r\nimg 115 at 18487\r\n48 31\r\nPadded to 48 by 31\r\nimg 116 at 18861\r\n48 31\r\nPadded to 48 by 31\r\nimg 117 at 19235\r\n48 31\r\nPadded to 48 by 31\r\nimg 118 at 19609\r\n48 31\r\nPadded to 48 by 31\r\nimg 119 at 19983\r\n48 31\r\nPadded to 48 by 31\r\nimg 120 at 20357\r\n6 7\r\nPadded to 8 by 7\r\nimg 121 at 20373\r\n7 31\r\nPadded to 8 by 31\r\nimg 122 at 20437\r\n32 31\r\nPadded to 32 by 31\r\nimg 123 at 20687\r\n48 31\r\nPadded to 48 by 31\r\nimg 124 at 21061\r\n48 31\r\nPadded to 48 by 31\r\nimg 125 at 21435\r\n48 31\r\nPadded to 48 by 31\r\nimg 126 at 21809\r\n48 31\r\nPadded to 48 by 31\r\nimg 127 at 22183\r\n48 31\r\nPadded to 48 by 31\r\nimg 128 at 22557\r\n48 31\r\nPadded to 48 by 31\r\nimg 129 at 22931\r\n48 31\r\nPadded to 48 by 31\r\nimg 130 at 23305\r\n48 31\r\nPadded to 48 by 31\r\nimg 131 at 23679\r\n48 31\r\nPadded to 48 by 31\r\nimg 132 at 24053\r\n48 31\r\nPadded to 48 by 31\r\nimg 133 at 24427\r\n48 31\r\nPadded to 48 by 31\r\nimg 134 at 24801\r\n48 31\r\nPadded to 48 by 31\r\nimg 135 at 25175\r\n48 31\r\nPadded to 48 by 31\r\nimg 136 at 25549\r\n48 31\r\nPadded to 48 by 31\r\nimg 137 at 25923\r\n48 31\r\nPadded to 48 by 31\r\nimg 138 at 26297\r\n48 31\r\nPadded to 48 by 31\r\nimg 139 at 26671\r\n48 31\r\nPadded to 48 by 31\r\nimg 140 at 27045\r\n48 31\r\nPadded to 48 by 31\r\nimg 141 at 27419\r\n48 31\r\nPadded to 48 by 31\r\nimg 142 at 27793\r\n48 31\r\nPadded to 48 by 31\r\nimg 143 at 28167\r\n7 31\r\nPadded to 8 by 31\r\nimg 144 at 28231\r\n32 29\r\nPadded to 32 by 29\r\nimg 145 at 28465\r\n32 29\r\nPadded to 32 by 29\r\nimg 146 at 28699\r\n48 31\r\nPadded to 48 by 31\r\nimg 147 at 29073\r\n48 31\r\nPadded to 48 by 31\r\nimg 148 at 29447\r\n48 31\r\nPadded to 48 by 31\r\nimg 149 at 29821\r\n48 31\r\nPadded to 48 by 31\r\nimg 150 at 30195\r\n48 31\r\nPadded to 48 by 31\r\nimg 151 at 30569\r\n48 31\r\nPadded to 48 by 31\r\nimg 152 at 30943\r\n48 31\r\nPadded to 48 by 31\r\nimg 153 at 31317\r\n48 31\r\nPadded to 48 by 31\r\nimg 154 at 31691\r\n48 31\r\nPadded to 48 by 31\r\nimg 155 at 32065\r\n48 8\r\nimg 156 at 32163\r\n48 22\r\nPadded to 48 by 22\r\nimg 157 at 32429\r\n48 22\r\nPadded to 48 by 22\r\nimg 158 at 32695\r\n48 22\r\nPadded to 48 by 22\r\nimg 159 at 32961\r\n48 22\r\nPadded to 48 by 22\r\nimg 160 at 33227\r\n48 7\r\nPadded to 48 by 7\r\nimg 161 at 33313\r\n48 7\r\nPadded to 48 by 7\r\nimg 162 at 33399\r\n48 31\r\nPadded to 48 by 31\r\nimg 163 at 33773\r\n48 31\r\nPadded to 48 by 31\r\nimg 164 at 34147\r\n20 6\r\nPadded to 20 by 6\r\nimg 165 at 34179\r\n48 31\r\nPadded to 48 by 31\r\nimg 166 at 34553\r\n35 26\r\nPadded to 36 by 26\r\nimg 167 at 34789\r\n35 26\r\nPadded to 36 by 26\r\nimg 168 at 35025\r\n16 15\r\nPadded to 16 by 15\r\nimg 169 at 35087\r\n16 15\r\nPadded to 16 by 15\r\nimg 170 at 35149\r\n16 15\r\nPadded to 16 by 15\r\nimg 171 at 35211\r\n16 15\r\nPadded to 16 by 15\r\nimg 172 at 35273\r\n16 15\r\nPadded to 16 by 15\r\nimg 173 at 35335\r\n16 15\r\nPadded to 16 by 15\r\nimg 174 at 35397\r\n16 15\r\nPadded to 16 by 15\r\nimg 175 at 35459\r\n16 15\r\nPadded to 16 by 15\r\nimg 176 at 35521\r\n16 15\r\nPadded to 16 by 15\r\nimg 177 at 35583\r\n16 15\r\nPadded to 16 by 15\r\nimg 178 at 35645\r\n16 15\r\nPadded to 16 by 15\r\nimg 179 at 35707\r\n16 15\r\nPadded to 16 by 15\r\nimg 180 at 35769\r\n16 15\r\nPadded to 16 by 15\r\nimg 181 at 35831\r\n16 15\r\nPadded to 16 by 15\r\nimg 182 at 35893\r\n16 15\r\nPadded to 16 by 15\r\nimg 183 at 35955\r\n16 15\r\nPadded to 16 by 15\r\nimg 184 at 36017\r\n16 15\r\nPadded to 16 by 15\r\nimg 185 at 36079\r\n16 15\r\nPadded to 16 by 15\r\nimg 186 at 36141\r\n16 15\r\nPadded to 16 by 15\r\nimg 187 at 36203\r\n16 15\r\nPadded to 16 by 15\r\nimg 188 at 36265\r\n16 15\r\nPadded to 16 by 15\r\nimg 189 at 36327\r\n16 15\r\nPadded to 16 by 15\r\nimg 190 at 36389\r\n16 15\r\nPadded to 16 by 15\r\nimg 191 at 36451\r\n16 15\r\nPadded to 16 by 15\r\nimg 192 at 36513\r\n16 15\r\nPadded to 16 by 15\r\nimg 193 at 36575\r\n16 15\r\nPadded to 16 by 15\r\nimg 194 at 36637\r\n16 15\r\nPadded to 16 by 15\r\nimg 195 at 36699\r\n16 15\r\nPadded to 16 by 15\r\nimg 196 at 36761\r\n16 15\r\nPadded to 16 by 15\r\nimg 197 at 36823\r\n16 15\r\nPadded to 16 by 15\r\nimg 198 at 36885\r\n16 15\r\nPadded to 16 by 15\r\nimg 199 at 36947\r\n16 15\r\nPadded to 16 by 15\r\nimg 200 at 37009\r\n16 15\r\nPadded to 16 by 15\r\nimg 201 at 37071\r\n16 15\r\nPadded to 16 by 15\r\nimg 202 at 37133\r\n16 15\r\nPadded to 16 by 15\r\nimg 203 at 37195\r\n16 15\r\nPadded to 16 by 15\r\nimg 204 at 37257\r\n24 31\r\nPadded to 24 by 31\r\nimg 205 at 37445\r\n24 15\r\nPadded to 24 by 15\r\nimg 206 at 37537\r\n16 19\r\nPadded to 16 by 19\r\nimg 207 at 37615\r\n30 31\r\nPadded to 32 by 31\r\nimg 208 at 37865\r\n30 31\r\nPadded to 32 by 31\r\nimg 209 at 38115\r\n30 31\r\nPadded to 32 by 31\r\nimg 210 at 38365\r\n30 31\r\nPadded to 32 by 31\r\nimg 211 at 38615\r\n30 31\r\nPadded to 32 by 31\r\nimg 212 at 38865\r\n4 7\r\nPadded to 4 by 7\r\nimg 213 at 38874\r\n4 7\r\nPadded to 4 by 7\r\nimg 214 at 38883\r\n4 7\r\nPadded to 4 by 7\r\nimg 215 at 38892\r\n4 7\r\nPadded to 4 by 7\r\nimg 216 at 38901\r\n48 31\r\nPadded to 48 by 31\r\nimg 217 at 39275\r\n48 31\r\nPadded to 48 by 31\r\nimg 218 at 39649\r\n19 7\r\nPadded to 20 by 7\r\nimg 219 at 39686\r\n13 7\r\nPadded to 16 by 7\r\nimg 220 at 39716\r\n13 7\r\nPadded to 16 by 7\r\nimg 221 at 39746\r\n19 7\r\nPadded to 20 by 7\r\nimg 222 at 39783\r\n48 31\r\nPadded to 48 by 31\r\nimg 223 at 40157\r\n4 4\r\nimg 224 at 40163\r\n7 31\r\nPadded to 8 by 31\r\nimg 225 at 40227\r\n48 31\r\nPadded to 48 by 31\r\nimg 226 at 40601\r\n48 31\r\nPadded to 48 by 31\r\nimg 227 at 40975\r\n48 31\r\nPadded to 48 by 31\r\nimg 228 at 41349\r\n48 31\r\nPadded to 48 by 31\r\nimg 229 at 41723\r\n16 31\r\nPadded to 16 by 31\r\nimg 230 at 41849\r\n16 16\r\nimg 231 at 41915\r\n16 16\r\nimg 232 at 41981\r\n16 16\r\nimg 233 at 42047\r\n16 16\r\nimg 234 at 42113\r\n4 4\r\nimg 235 at 42119\r\n4 4\r\nimg 236 at 42125\r\n48 31\r\nPadded to 48 by 31\r\nimg 237 at 42499\r\n48 31\r\nPadded to 48 by 31\r\nimg 238 at 42873\r\n48 31\r\nPadded to 48 by 31\r\nimg 239 at 43247\r\n48 31\r\nPadded to 48 by 31\r\nimg 240 at 43621\r\n48 31\r\nPadded to 48 by 31\r\nimg 241 at 43995\r\n4 4\r\nimg 242 at 44001\r\n4 4\r\nimg 243 at 44007\r\n4 4\r\nimg 244 at 44013\r\n48 31\r\nPadded to 48 by 31\r\nimg 245 at 44387\r\n48 31\r\nPadded to 48 by 31\r\nimg 246 at 44761\r\n48 8\r\nimg 247 at 44859\r\n16 14\r\nPadded to 16 by 14\r\nimg 248 at 44917\r\n16 14\r\nPadded to 16 by 14\r\nimg 249 at 44975\r\n16 14\r\nPadded to 16 by 14\r\nimg 250 at 45033\r\n16 14\r\nPadded to 16 by 14\r\nimg 251 at 45091\r\n16 14\r\nPadded to 16 by 14\r\nimg 252 at 45149\r\n16 14\r\nPadded to 16 by 14\r\nimg 253 at 45207\r\n16 14\r\nPadded to 16 by 14\r\nimg 254 at 45265\r\n16 14\r\nPadded to 16 by 14\r\nimg 255 at 45323\r\n16 14\r\nPadded to 16 by 14\r\nimg 256 at 45381\r\n48 31\r\nPadded to 48 by 31\r\nimg 257 at 45755\r\n24 31\r\nPadded to 24 by 31\r\nimg 258 at 45943\r\n24 15\r\nPadded to 24 by 15\r\nimg 259 at 46035\r\n16 19\r\nPadded to 16 by 19\r\nimg 260 at 46113\r\n30 31\r\nPadded to 32 by 31\r\nimg 261 at 46363\r\n30 31\r\nPadded to 32 by 31\r\nimg 262 at 46613\r\n30 31\r\nPadded to 32 by 31\r\nimg 263 at 46863\r\n30 31\r\nPadded to 32 by 31\r\nimg 264 at 47113\r\n30 31\r\nPadded to 32 by 31\r\nimg 265 at 47363\r\n4 7\r\nPadded to 4 by 7\r\nimg 266 at 47372\r\n4 7\r\nPadded to 4 by 7\r\nimg 267 at 47381\r\n4 7\r\nPadded to 4 by 7\r\nimg 268 at 47390\r\n4 7\r\nPadded to 4 by 7\r\nimg 269 at 47399\r\n48 31\r\nPadded to 48 by 31\r\nimg 270 at 47773\r\n48 31\r\nPadded to 48 by 31\r\nimg 271 at 48147\r\n19 7\r\nPadded to 20 by 7\r\nimg 272 at 48184\r\n13 7\r\nPadded to 16 by 7\r\nimg 273 at 48214\r\n13 7\r\nPadded to 16 by 7\r\nimg 274 at 48244\r\n19 7\r\nPadded to 20 by 7\r\nimg 275 at 48281\r\n48 31\r\nPadded to 48 by 31\r\nimg 276 at 48655\r\n4 4\r\nimg 277 at 48661\r\n7 31\r\nPadded to 8 by 31\r\nimg 278 at 48725\r\n48 31\r\nPadded to 48 by 31\r\nimg 279 at 49099\r\n48 31\r\nPadded to 48 by 31\r\nimg 280 at 49473\r\n48 31\r\nPadded to 48 by 31\r\nimg 281 at 49847\r\n48 31\r\nPadded to 48 by 31\r\nimg 282 at 50221\r\n48 31\r\nPadded to 48 by 31\r\nimg 283 at 50595\r\n48 31\r\nPadded to 48 by 31\r\nimg 284 at 50969\r\n48 31\r\nPadded to 48 by 31\r\nimg 285 at 51343\r\n16 16\r\nimg 286 at 51409\r\n16 16\r\nimg 287 at 51475\r\n16 16\r\nimg 288 at 51541\r\n16 16\r\nimg 289 at 51607\r\n48 31\r\nPadded to 48 by 31\r\nimg 290 at 51981\r\n48 31\r\nPadded to 48 by 31\r\nimg 291 at 52355\r\n48 31\r\nPadded to 48 by 31\r\nimg 292 at 52729\r\n48 31\r\nPadded to 48 by 31\r\nimg 293 at 53103\r\n48 31\r\nPadded to 48 by 31\r\nimg 294 at 53477\r\n4 4\r\nimg 295 at 53483\r\n4 4\r\nimg 296 at 53489\r\n4 4\r\nimg 297 at 53495\r\n48 31\r\nPadded to 48 by 31\r\nimg 298 at 53869\r\n48 31\r\nPadded to 48 by 31\r\nimg 299 at 54243\r\n48 8\r\nimg 300 at 54341\r\n16 14\r\nPadded to 16 by 14\r\nimg 301 at 54399\r\n16 14\r\nPadded to 16 by 14\r\nimg 302 at 54457\r\n16 14\r\nPadded to 16 by 14\r\nimg 303 at 54515\r\n16 14\r\nPadded to 16 by 14\r\nimg 304 at 54573\r\n16 14\r\nPadded to 16 by 14\r\nimg 305 at 54631\r\n16 14\r\nPadded to 16 by 14\r\nimg 306 at 54689\r\n16 14\r\nPadded to 16 by 14\r\nimg 307 at 54747\r\n16 14\r\nPadded to 16 by 14\r\nimg 308 at 54805\r\n16 14\r\nPadded to 16 by 14\r\nimg 309 at 54863\r\n48 31\r\nPadded to 48 by 31\r\nimg 310 at 55237\r\n24 31\r\nPadded to 24 by 31\r\nimg 311 at 55425\r\n24 15\r\nPadded to 24 by 15\r\nimg 312 at 55517\r\n16 19\r\nPadded to 16 by 19\r\nimg 313 at 55595\r\n30 31\r\nPadded to 32 by 31\r\nimg 314 at 55845\r\n30 31\r\nPadded to 32 by 31\r\nimg 315 at 56095\r\n30 31\r\nPadded to 32 by 31\r\nimg 316 at 56345\r\n30 31\r\nPadded to 32 by 31\r\nimg 317 at 56595\r\n30 31\r\nPadded to 32 by 31\r\nimg 318 at 56845\r\n4 7\r\nPadded to 4 by 7\r\nimg 319 at 56854\r\n4 7\r\nPadded to 4 by 7\r\nimg 320 at 56863\r\n4 7\r\nPadded to 4 by 7\r\nimg 321 at 56872\r\n4 7\r\nPadded to 4 by 7\r\nimg 322 at 56881\r\n48 31\r\nPadded to 48 by 31\r\nimg 323 at 57255\r\n48 31\r\nPadded to 48 by 31\r\nimg 324 at 57629\r\n19 7\r\nPadded to 20 by 7\r\nimg 325 at 57666\r\n13 7\r\nPadded to 16 by 7\r\nimg 326 at 57696\r\n13 7\r\nPadded to 16 by 7\r\nimg 327 at 57726\r\n19 7\r\nPadded to 20 by 7\r\nimg 328 at 57763\r\n48 31\r\nPadded to 48 by 31\r\nimg 329 at 58137\r\n4 4\r\nimg 330 at 58143\r\n7 31\r\nPadded to 8 by 31\r\nimg 331 at 58207\r\n48 31\r\nPadded to 48 by 31\r\nimg 332 at 58581\r\n48 31\r\nPadded to 48 by 31\r\nimg 333 at 58955\r\n48 31\r\nPadded to 48 by 31\r\nimg 334 at 59329\r\n48 31\r\nPadded to 48 by 31\r\nimg 335 at 59703\r\n48 31\r\nPadded to 48 by 31\r\nimg 336 at 60077\r\n48 31\r\nPadded to 48 by 31\r\nimg 337 at 60451\r\n48 31\r\nPadded to 48 by 31\r\nimg 338 at 60825\r\n48 31\r\nPadded to 48 by 31\r\nimg 339 at 61199\r\n48 31\r\nPadded to 48 by 31\r\nimg 340 at 61573\r\n48 31\r\nPadded to 48 by 31\r\nimg 341 at 61947\r\n16 16\r\nimg 342 at 62013\r\n16 16\r\nimg 343 at 62079\r\n16 16\r\nimg 344 at 62145\r\n16 16\r\nimg 345 at 62211\r\n4 4\r\nimg 346 at 62217\r\n4 4\r\nimg 347 at 62223\r\n4 4\r\nimg 348 at 62229\r\n4 4\r\nimg 349 at 62235\r\n4 4\r\nimg 350 at 62241\r\n48 31\r\nPadded to 48 by 31\r\nimg 351 at 62615\r\n48 31\r\nPadded to 48 by 31\r\nimg 352 at 62989\r\n48 8\r\nimg 353 at 63087\r\n16 14\r\nPadded to 16 by 14\r\nimg 354 at 63145\r\n16 14\r\nPadded to 16 by 14\r\nimg 355 at 63203\r\n16 14\r\nPadded to 16 by 14\r\nimg 356 at 63261\r\n16 14\r\nPadded to 16 by 14\r\nimg 357 at 63319\r\n16 14\r\nPadded to 16 by 14\r\nimg 358 at 63377\r\n16 14\r\nPadded to 16 by 14\r\nimg 359 at 63435\r\n16 14\r\nPadded to 16 by 14\r\nimg 360 at 63493\r\n16 14\r\nPadded to 16 by 14\r\nimg 361 at 63551\r\n16 14\r\nPadded to 16 by 14\r\nimg 362 at 63609\r\n48 31\r\nPadded to 48 by 31\r\nimg 363 at 63983\r\n24 31\r\nPadded to 24 by 31\r\nimg 364 at 64171\r\n24 15\r\nPadded to 24 by 15\r\nimg 365 at 64263\r\n16 19\r\nPadded to 16 by 19\r\nimg 366 at 64341\r\n30 31\r\nPadded to 32 by 31\r\nimg 367 at 64591\r\n30 31\r\nPadded to 32 by 31\r\nimg 368 at 64841\r\n30 31\r\nPadded to 32 by 31\r\nimg 369 at 65091\r\n30 31\r\nPadded to 32 by 31\r\nimg 370 at 65341\r\n30 31\r\nPadded to 32 by 31\r\nimg 371 at 65591\r\n4 7\r\nPadded to 4 by 7\r\nimg 372 at 65600\r\n4 7\r\nPadded to 4 by 7\r\nimg 373 at 65609\r\n4 7\r\nPadded to 4 by 7\r\nimg 374 at 65618\r\n4 7\r\nPadded to 4 by 7\r\nimg 375 at 65627\r\n48 31\r\nPadded to 48 by 31\r\nimg 376 at 66001\r\n48 31\r\nPadded to 48 by 31\r\nimg 377 at 66375\r\n19 7\r\nPadded to 20 by 7\r\nimg 378 at 66412\r\n13 7\r\nPadded to 16 by 7\r\nimg 379 at 66442\r\n13 7\r\nPadded to 16 by 7\r\nimg 380 at 66472\r\n19 7\r\nPadded to 20 by 7\r\nimg 381 at 66509\r\n48 31\r\nPadded to 48 by 31\r\nimg 382 at 66883\r\n4 4\r\nimg 383 at 66889\r\n7 31\r\nPadded to 8 by 31\r\nimg 384 at 66953\r\n48 31\r\nPadded to 48 by 31\r\nimg 385 at 67327\r\n48 31\r\nPadded to 48 by 31\r\nimg 386 at 67701\r\n48 31\r\nPadded to 48 by 31\r\nimg 387 at 68075\r\n48 31\r\nPadded to 48 by 31\r\nimg 388 at 68449\r\n48 31\r\nPadded to 48 by 31\r\nimg 389 at 68823\r\n48 31\r\nPadded to 48 by 31\r\nimg 390 at 69197\r\n48 31\r\nPadded to 48 by 31\r\nimg 391 at 69571\r\n48 31\r\nPadded to 48 by 31\r\nimg 392 at 69945\r\n48 31\r\nPadded to 48 by 31\r\nimg 393 at 70319\r\n26 15\r\nPadded to 28 by 15\r\nimg 394 at 70426\r\n24 12\r\nimg 395 at 70500\r\n48 2\r\nPadded to 48 by 2\r\nimg 396 at 70526\r\n48 31\r\nPadded to 48 by 31\r\nimg 397 at 70900\r\n4 4\r\nimg 398 at 70906\r\n4 4\r\nimg 399 at 70912\r\n4 4\r\nimg 400 at 70918\r\n4 4\r\nimg 401 at 70924\r\n4 4\r\nimg 402 at 70930\r\n4 4\r\nimg 403 at 70936\r\n48 31\r\nPadded to 48 by 31\r\nimg 404 at 71310\r\n48 31\r\nPadded to 48 by 31\r\nimg 405 at 71684\r\n48 8\r\nimg 406 at 71782\r\n16 14\r\nPadded to 16 by 14\r\nimg 407 at 71840\r\n16 14\r\nPadded to 16 by 14\r\nimg 408 at 71898\r\n16 14\r\nPadded to 16 by 14\r\nimg 409 at 71956\r\n16 14\r\nPadded to 16 by 14\r\nimg 410 at 72014\r\n16 14\r\nPadded to 16 by 14\r\nimg 411 at 72072\r\n16 14\r\nPadded to 16 by 14\r\nimg 412 at 72130\r\n16 14\r\nPadded to 16 by 14\r\nimg 413 at 72188\r\n16 14\r\nPadded to 16 by 14\r\nimg 414 at 72246\r\n16 14\r\nPadded to 16 by 14\r\nimg 415 at 72304\r\n48 31\r\nPadded to 48 by 31\r\nimg 416 at 72678\r\n14 13\r\nPadded to 16 by 13\r\nimg 417 at 72732\r\n14 13\r\nPadded to 16 by 13\r\nimg 418 at 72786\r\n14 13\r\nPadded to 16 by 13\r\nimg 419 at 72840\r\n14 13\r\nPadded to 16 by 13\r\nimg 420 at 72894\r\n14 13\r\nPadded to 16 by 13\r\nimg 421 at 72948\r\n14 13\r\nPadded to 16 by 13\r\nimg 422 at 73002\r\n14 13\r\nPadded to 16 by 13\r\nimg 423 at 73056\r\n14 13\r\nPadded to 16 by 13\r\nimg 424 at 73110\r\n14 13\r\nPadded to 16 by 13\r\nimg 425 at 73164\r\n14 13\r\nPadded to 16 by 13\r\nimg 426 at 73218\r\n14 13\r\nPadded to 16 by 13\r\nimg 427 at 73272\r\n14 13\r\nPadded to 16 by 13\r\nimg 428 at 73326\r\n14 13\r\nPadded to 16 by 13\r\nimg 429 at 73380\r\n14 13\r\nPadded to 16 by 13\r\nimg 430 at 73434\r\n14 13\r\nPadded to 16 by 13\r\nimg 431 at 73488\r\n14 13\r\nPadded to 16 by 13\r\nimg 432 at 73542\r\n14 13\r\nPadded to 16 by 13\r\nimg 433 at 73596\r\n14 13\r\nPadded to 16 by 13\r\nimg 434 at 73650\r\n14 13\r\nPadded to 16 by 13\r\nimg 435 at 73704\r\n14 13\r\nPadded to 16 by 13\r\nimg 436 at 73758\r\n14 13\r\nPadded to 16 by 13\r\nimg 437 at 73812\r\n14 13\r\nPadded to 16 by 13\r\nimg 438 at 73866\r\n14 13\r\nPadded to 16 by 13\r\nimg 439 at 73920\r\n14 13\r\nPadded to 16 by 13\r\nimg 440 at 73974\r\n14 13\r\nPadded to 16 by 13\r\nimg 441 at 74028\r\n14 13\r\nPadded to 16 by 13\r\nimg 442 at 74082\r\n14 13\r\nPadded to 16 by 13\r\nimg 443 at 74136\r\n14 13\r\nPadded to 16 by 13\r\nimg 444 at 74190\r\n14 13\r\nPadded to 16 by 13\r\nimg 445 at 74244\r\n14 13\r\nPadded to 16 by 13\r\nimg 446 at 74298\r\n14 13\r\nPadded to 16 by 13\r\nimg 447 at 74352\r\n14 13\r\nPadded to 16 by 13\r\nimg 448 at 74406\r\n14 13\r\nPadded to 16 by 13\r\nimg 449 at 74460\r\n14 13\r\nPadded to 16 by 13\r\nimg 450 at 74514\r\n14 13\r\nPadded to 16 by 13\r\nimg 451 at 74568\r\n14 13\r\nPadded to 16 by 13\r\nimg 452 at 74622\r\n14 13\r\nPadded to 16 by 13\r\nimg 453 at 74676\r\n14 13\r\nPadded to 16 by 13\r\nimg 454 at 74730\r\n14 13\r\nPadded to 16 by 13\r\nimg 455 at 74784\r\n14 13\r\nPadded to 16 by 13\r\nimg 456 at 74838\r\n14 13\r\nPadded to 16 by 13\r\nimg 457 at 74892\r\n14 13\r\nPadded to 16 by 13\r\nimg 458 at 74946\r\n14 13\r\nPadded to 16 by 13\r\nimg 459 at 75000\r\n14 13\r\nPadded to 16 by 13\r\nimg 460 at 75054\r\n32 17\r\nPadded to 32 by 17\r\nimg 461 at 75192\r\n32 17\r\nPadded to 32 by 17\r\nimg 462 at 75330\r\n48 31\r\nPadded to 48 by 31\r\nimg 463 at 75704\r\n48 31\r\nPadded to 48 by 31\r\nimg 464 at 76078\r\n45 27\r\nPadded to 48 by 27\r\nimg 465 at 76404\r\n45 27\r\nPadded to 48 by 27\r\nimg 466 at 76730\r\n30 25\r\nPadded to 32 by 25\r\nimg 467 at 76932\r\n30 25\r\nPadded to 32 by 25\r\nimg 468 at 77134\r\n48 31\r\nPadded to 48 by 31\r\nimg 469 at 77508\r\n48 31\r\nPadded to 48 by 31\r\nimg 470 at 77882\r\n48 31\r\nPadded to 48 by 31\r\nimg 471 at 78256\r\n48 31\r\nPadded to 48 by 31\r\nimg 472 at 78630\r\n14 11\r\nPadded to 16 by 11\r\nimg 473 at 78676\r\n48 31\r\nPadded to 48 by 31\r\nimg 474 at 79050\r\n48 31\r\nPadded to 48 by 31\r\nimg 475 at 79424\r\n7 31\r\nPadded to 8 by 31\r\nimg 476 at 79488\r\n22 16\r\nimg 477 at 79586\r\n22 16\r\nimg 478 at 79684\r\n7 31\r\nPadded to 8 by 31\r\nimg 479 at 79748\r\n48 7\r\nPadded to 48 by 7\r\nimg 480 at 79834\r\n48 6\r\nPadded to 48 by 6\r\nimg 481 at 79908\r\n48 6\r\nPadded to 48 by 6\r\nimg 482 at 79982\r\n9 8\r\nimg 483 at 80008\r\n20 23\r\nPadded to 20 by 23\r\nimg 484 at 80125\r\n48 31\r\nPadded to 48 by 31\r\nimg 485 at 80499\r\n48 31\r\nPadded to 48 by 31\r\nimg 486 at 80873\r\n48 31\r\nPadded to 48 by 31\r\nimg 487 at 81247\r\n10 10\r\nPadded to 12 by 10\r\nimg 488 at 81279\r\n10 10\r\nPadded to 12 by 10\r\nimg 489 at 81311\r\n10 12\r\nimg 490 at 81349\r\n10 12\r\nimg 491 at 81387\r\n24 9\r\nPadded to 24 by 9\r\nimg 492 at 81443\r\n28 6\r\nPadded to 28 by 6\r\nimg 493 at 81487\r\n28 6\r\nPadded to 28 by 6\r\nimg 494 at 81531\r\n1 0\r\n" }, { "path": "figure/SignalPulls/README", "content": "Signal Pulls\r\n\r\nempire.txt -- Reads when doing USA tour (the NY tour version)\r\nsignaldecode.py -- takes signal analyzer dump, and converts it to list of read addresses\r\nusatour.txt -- Reads when doing USA tour(Washington DC version)\r\nusatourbuy.txt -- Reads when buying USA tour\r\n\r\n" }, { "path": "figure/SignalPulls/empire.txt", "content": "here\r\nTime [s],Packet ID,MOSI,MISO\r\n\r\nBREAK\r\n1\r\n2a8\r\n2af2\r\n2af4\r\n2af8\r\n2afc\r\n2b00\r\n2b04\r\n2b08\r\n2b0c\r\n2b10\r\n2b14\r\n2b18\r\n2b1c\r\n2b20\r\n2b24\r\n2b28\r\n2b2c\r\n2b30\r\nBREAK\r\n1\r\n2cc\r\n2e06\r\n2e08\r\n2e10\r\n2e18\r\n2e20\r\n2e28\r\n2e30\r\n2e38\r\n2e40\r\n2e48\r\n2e50\r\n2e58\r\n2e60\r\nBREAK\r\n1\r\n927\r\nBREAK\r\n1\r\nd1\r\n24a1\r\n24a3\r\n24a8\r\n24ad\r\n24b2\r\n24b7\r\n24bc\r\n24c1\r\n24c6\r\n24cb\r\n24d0\r\n24d5\r\n24da\r\n24df\r\n24e4\r\n24e9\r\n24ee\r\n24f3\r\n24f8\r\n24fd\r\n2502\r\n2507\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\n162\r\n92e\r\n95b\r\nBREAK\r\n1\r\n24fc2\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\n24fc8\r\nBREAK\r\n1\r\n4b5\r\n9ce2\r\n9ce4\r\n9ce6\r\n9ce8\r\n9cea\r\n9cec\r\n9cee\r\n9cf0\r\n9cf2\r\n9cf4\r\n9cf6\r\n9cf8\r\n9cfa\r\n9cfc\r\n9cfe\r\n9d00\r\n9d02\r\n9d04\r\n9d06\r\n9d08\r\n9d0a\r\n9d0c\r\n9d0e\r\n9d10\r\n9d12\r\n9d14\r\n9d16\r\n9d18\r\n9d1a\r\n9d1c\r\n9d1e\r\n9d20\r\nBREAK\r\n1\r\n24fce\r\nBREAK\r\n1\r\n24fd4\r\nBREAK\r\n1\r\n24fda\r\nBREAK\r\n1\r\n24fe0\r\nBREAK\r\n1\r\n24fe6\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\n24fec\r\nBREAK\r\n1\r\n4b5\r\n9ce2\r\n9ce4\r\n9ce6\r\n9ce8\r\n9cea\r\n9cec\r\n9cee\r\n9cf0\r\n9cf2\r\n9cf4\r\n9cf6\r\n9cf8\r\n9cfa\r\n9cfc\r\n9cfe\r\n9d00\r\n9d02\r\n9d04\r\n9d06\r\n9d08\r\n9d0a\r\n9d0c\r\n9d0e\r\n9d10\r\n9d12\r\n9d14\r\n9d16\r\n9d18\r\n9d1a\r\n9d1c\r\n9d1e\r\n9d20\r\nBREAK\r\n1\r\n24ff2\r\nBREAK\r\n1\r\n24ff8\r\nBREAK\r\n1\r\n24ffe\r\nBREAK\r\n1\r\n25004\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\n2500a\r\nBREAK\r\n1\r\n4b5\r\n9ce2\r\n9ce4\r\n9ce6\r\n9ce8\r\n9cea\r\n9cec\r\n9cee\r\n9cf0\r\n9cf2\r\n9cf4\r\n9cf6\r\n9cf8\r\n9cfa\r\n9cfc\r\n9cfe\r\n9d00\r\n9d02\r\n9d04\r\n9d06\r\n9d08\r\n9d0a\r\n9d0c\r\n9d0e\r\n9d10\r\n9d12\r\n9d14\r\n9d16\r\n9d18\r\n9d1a\r\n9d1c\r\n9d1e\r\n9d20\r\nBREAK\r\n1\r\n25010\r\nBREAK\r\n1\r\n25016\r\nBREAK\r\n1\r\n2501c\r\nBREAK\r\n1\r\n25022\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\n25028\r\nBREAK\r\n1\r\n4b5\r\n9ce2\r\n9ce4\r\n9ce6\r\n9ce8\r\n9cea\r\n9cec\r\n9cee\r\n9cf0\r\n9cf2\r\n9cf4\r\n9cf6\r\n9cf8\r\n9cfa\r\n9cfc\r\n9cfe\r\n9d00\r\n9d02\r\n9d04\r\n9d06\r\n9d08\r\n9d0a\r\n9d0c\r\n9d0e\r\n9d10\r\n9d12\r\n9d14\r\n9d16\r\n9d18\r\n9d1a\r\n9d1c\r\n9d1e\r\n9d20\r\nBREAK\r\n1\r\n2502e\r\nBREAK\r\n1\r\n25034\r\nBREAK\r\n1\r\n2503a\r\nBREAK\r\n1\r\n25040\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\n25046\r\nBREAK\r\n1\r\n4b5\r\n9ce2\r\n9ce4\r\n9ce6\r\n9ce8\r\n9cea\r\n9cec\r\n9cee\r\n9cf0\r\n9cf2\r\n9cf4\r\n9cf6\r\n9cf8\r\n9cfa\r\n9cfc\r\n9cfe\r\n9d00\r\n9d02\r\n9d04\r\n9d06\r\n9d08\r\n9d0a\r\n9d0c\r\n9d0e\r\n9d10\r\n9d12\r\n9d14\r\n9d16\r\n9d18\r\n9d1a\r\n9d1c\r\n9d1e\r\n9d20\r\nBREAK\r\n1\r\n2504c\r\nBREAK\r\n1\r\n25052\r\nBREAK\r\n1\r\n25058\r\nBREAK\r\n1\r\n2505e\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\n25064\r\nBREAK\r\n1\r\n4b5\r\n9ce2\r\n9ce4\r\n9ce6\r\n9ce8\r\n9cea\r\n9cec\r\n9cee\r\n9cf0\r\n9cf2\r\n9cf4\r\n9cf6\r\n9cf8\r\n9cfa\r\n9cfc\r\n9cfe\r\n9d00\r\n9d02\r\n9d04\r\n9d06\r\n9d08\r\n9d0a\r\n9d0c\r\n9d0e\r\n9d10\r\n9d12\r\n9d14\r\n9d16\r\n9d18\r\n9d1a\r\n9d1c\r\n9d1e\r\n9d20\r\nBREAK\r\n1\r\n2506a\r\nBREAK\r\n1\r\n25070\r\nBREAK\r\n1\r\n25076\r\nBREAK\r\n1\r\n2507c\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\n25082\r\nBREAK\r\n1\r\n4b5\r\n9ce2\r\n9ce4\r\n9ce6\r\n9ce8\r\n9cea\r\n9cec\r\n9cee\r\n9cf0\r\n9cf2\r\n9cf4\r\n9cf6\r\n9cf8\r\n9cfa\r\n9cfc\r\n9cfe\r\n9d00\r\n9d02\r\n9d04\r\n9d06\r\n9d08\r\n9d0a\r\n9d0c\r\n9d0e\r\n9d10\r\n9d12\r\n9d14\r\n9d16\r\n9d18\r\n9d1a\r\n9d1c\r\n9d1e\r\n9d20\r\nBREAK\r\n1\r\n25088\r\nBREAK\r\n1\r\n2508e\r\nBREAK\r\n1\r\n25094\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\n2509a\r\nBREAK\r\n1\r\n4b5\r\n9ce2\r\n9ce4\r\n9ce6\r\n9ce8\r\n9cea\r\n9cec\r\n9cee\r\n9cf0\r\n9cf2\r\n9cf4\r\n9cf6\r\n9cf8\r\n9cfa\r\n9cfc\r\n9cfe\r\n9d00\r\n9d02\r\n9d04\r\n9d06\r\n9d08\r\n9d0a\r\n9d0c\r\n9d0e\r\n9d10\r\n9d12\r\n9d14\r\n9d16\r\n9d18\r\n9d1a\r\n9d1c\r\n9d1e\r\n9d20\r\nBREAK\r\n1\r\n250a0\r\nBREAK\r\n1\r\n250a6\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\n250ac\r\nBREAK\r\n1\r\n4b5\r\n9ce2\r\n9ce4\r\n9ce6\r\n9ce8\r\n9cea\r\n9cec\r\n9cee\r\n9cf0\r\n9cf2\r\n9cf4\r\n9cf6\r\n9cf8\r\n9cfa\r\n9cfc\r\n9cfe\r\n9d00\r\n9d02\r\n9d04\r\n9d06\r\n9d08\r\n9d0a\r\n9d0c\r\n9d0e\r\n9d10\r\n9d12\r\n9d14\r\n9d16\r\n9d18\r\n9d1a\r\n9d1c\r\n9d1e\r\n9d20\r\nBREAK\r\n1\r\n250b2\r\nBREAK\r\n1\r\n250b8\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\n250be\r\nBREAK\r\n1\r\n4b5\r\n9ce2\r\n9ce4\r\n9ce6\r\n9ce8\r\n9cea\r\n9cec\r\n9cee\r\n9cf0\r\n9cf2\r\n9cf4\r\n9cf6\r\n9cf8\r\n9cfa\r\n9cfc\r\n9cfe\r\n9d00\r\n9d02\r\n9d04\r\n9d06\r\n9d08\r\n9d0a\r\n9d0c\r\n9d0e\r\n9d10\r\n9d12\r\n9d14\r\n9d16\r\n9d18\r\n9d1a\r\n9d1c\r\n9d1e\r\n9d20\r\nBREAK\r\n1\r\n250c4\r\nBREAK\r\n1\r\n250ca\r\nBREAK\r\n1\r\n250d0\r\nBREAK\r\n1\r\n4f1\r\nabec\r\nabee\r\nabf6\r\nabfa\r\nac02\r\nac06\r\nac0e\r\nac12\r\nac1a\r\nac1e\r\nac26\r\nac2a\r\nac32\r\nac36\r\nac3e\r\nac42\r\nac4a\r\nac4e\r\nac56\r\nac5a\r\nac62\r\nac66\r\nac6e\r\nac72\r\nac7a\r\nac7e\r\nac86\r\nac8a\r\nac92\r\nac96\r\nac9e\r\naca2\r\nacaa\r\nacae\r\nacb6\r\nacba\r\nacc2\r\nacc6\r\nacce\r\nacd2\r\nacda\r\nacde\r\nace6\r\nacea\r\nacf2\r\nacf6\r\nacfe\r\nad02\r\nad0a\r\nad0e\r\nad16\r\nad1a\r\nad22\r\nad26\r\nad2e\r\nad32\r\nad3a\r\nad3e\r\nad46\r\nad4a\r\nad52\r\nad56\r\nad5e\r\nBREAK\r\n1\r\n250d6\r\nBREAK\r\n1\r\n4f1\r\nabec\r\nabee\r\nabf6\r\nabfa\r\nac02\r\nac06\r\nac0e\r\nac12\r\nac1a\r\nac1e\r\nac26\r\nac2a\r\nac32\r\nac36\r\nac3e\r\nac42\r\nac4a\r\nac4e\r\nac56\r\nac5a\r\nac62\r\nac66\r\nac6e\r\nac72\r\nac7a\r\nac7e\r\nac86\r\nac8a\r\nac92\r\nac96\r\nac9e\r\naca2\r\nacaa\r\nacae\r\nacb6\r\nacba\r\nacc2\r\nacc6\r\nacce\r\nacd2\r\nacda\r\nacde\r\nace6\r\nacea\r\nacf2\r\nacf6\r\nacfe\r\nad02\r\nad0a\r\nad0e\r\nad16\r\nad1a\r\nad22\r\nad26\r\nad2e\r\nad32\r\nad3a\r\nad3e\r\nad46\r\nad4a\r\nad52\r\nad56\r\nad5e\r\nBREAK\r\n1\r\n250dc\r\nBREAK\r\n1\r\n250e2\r\nBREAK\r\n1\r\n4f1\r\nabec\r\nabee\r\nabf6\r\nabfa\r\nac02\r\nac06\r\nac0e\r\nac12\r\nac1a\r\nac1e\r\nac26\r\nac2a\r\nac32\r\nac36\r\nac3e\r\nac42\r\nac4a\r\nac4e\r\nac56\r\nac5a\r\nac62\r\nac66\r\nac6e\r\nac72\r\nac7a\r\nac7e\r\nac86\r\nac8a\r\nac92\r\nac96\r\nac9e\r\naca2\r\nacaa\r\nacae\r\nacb6\r\nacba\r\nacc2\r\nacc6\r\nacce\r\nacd2\r\nacda\r\nacde\r\nace6\r\nacea\r\nacf2\r\nacf6\r\nacfe\r\nad02\r\nad0a\r\nad0e\r\nad16\r\nad1a\r\nad22\r\nad26\r\nad2e\r\nad32\r\nad3a\r\nad3e\r\nad46\r\nad4a\r\nad52\r\nad56\r\nad5e\r\nBREAK\r\n1\r\n250e8\r\nBREAK\r\n1\r\n250ee\r\nBREAK\r\n1\r\n4f1\r\nabec\r\nabee\r\nabf6\r\nabfa\r\nac02\r\nac06\r\nac0e\r\nac12\r\nac1a\r\nac1e\r\nac26\r\nac2a\r\nac32\r\nac36\r\nac3e\r\nac42\r\nac4a\r\nac4e\r\nac56\r\nac5a\r\nac62\r\nac66\r\nac6e\r\nac72\r\nac7a\r\nac7e\r\nac86\r\nac8a\r\nac92\r\nac96\r\nac9e\r\naca2\r\nacaa\r\nacae\r\nacb6\r\nacba\r\nacc2\r\nacc6\r\nacce\r\nacd2\r\nacda\r\nacde\r\nace6\r\nacea\r\nacf2\r\nacf6\r\nacfe\r\nad02\r\nad0a\r\nad0e\r\nad16\r\nad1a\r\nad22\r\nad26\r\nad2e\r\nad32\r\nad3a\r\nad3e\r\nad46\r\nad4a\r\nad52\r\nad56\r\nad5e\r\nBREAK\r\n1\r\n250f4\r\nBREAK\r\n1\r\n250fa\r\nBREAK\r\n1\r\n4f1\r\nabec\r\nabee\r\nabf6\r\nabfa\r\nac02\r\nac06\r\nac0e\r\nac12\r\nac1a\r\nac1e\r\nac26\r\nac2a\r\nac32\r\nac36\r\nac3e\r\nac42\r\nac4a\r\nac4e\r\nac56\r\nac5a\r\nac62\r\nac66\r\nac6e\r\nac72\r\nac7a\r\nac7e\r\nac86\r\nac8a\r\nac92\r\nac96\r\nac9e\r\naca2\r\nacaa\r\nacae\r\nacb6\r\nacba\r\nacc2\r\nacc6\r\nacce\r\nacd2\r\nacda\r\nacde\r\nace6\r\nacea\r\nacf2\r\nacf6\r\nacfe\r\nad02\r\nad0a\r\nad0e\r\nad16\r\nad1a\r\nad22\r\nad26\r\nad2e\r\nad32\r\nad3a\r\nad3e\r\nad46\r\nad4a\r\nad52\r\nad56\r\nad5e\r\nBREAK\r\n1\r\n25100\r\nBREAK\r\n1\r\n25106\r\nBREAK\r\n1\r\n4f1\r\nabec\r\nabee\r\nabf6\r\nabfa\r\nac02\r\nac06\r\nac0e\r\nac12\r\nac1a\r\nac1e\r\nac26\r\nac2a\r\nac32\r\nac36\r\nac3e\r\nac42\r\nac4a\r\nac4e\r\nac56\r\nac5a\r\nac62\r\nac66\r\nac6e\r\nac72\r\nac7a\r\nac7e\r\nac86\r\nac8a\r\nac92\r\nac96\r\nac9e\r\naca2\r\nacaa\r\nacae\r\nacb6\r\nacba\r\nacc2\r\nacc6\r\nacce\r\nacd2\r\nacda\r\nacde\r\nace6\r\nacea\r\nacf2\r\nacf6\r\nacfe\r\nad02\r\nad0a\r\nad0e\r\nad16\r\nad1a\r\nad22\r\nad26\r\nad2e\r\nad32\r\nad3a\r\nad3e\r\nad46\r\nad4a\r\nad52\r\nad56\r\nad5e\r\nBREAK\r\n1\r\n2510c\r\nBREAK\r\n1\r\n25112\r\nBREAK\r\n1\r\n4f1\r\nabec\r\nabee\r\nabf6\r\nabfa\r\nac02\r\nac06\r\nac0e\r\nac12\r\nac1a\r\nac1e\r\nac26\r\nac2a\r\nac32\r\nac36\r\nac3e\r\nac42\r\nac4a\r\nac4e\r\nac56\r\nac5a\r\nac62\r\nac66\r\nac6e\r\nac72\r\nac7a\r\nac7e\r\nac86\r\nac8a\r\nac92\r\nac96\r\nac9e\r\naca2\r\nacaa\r\nacae\r\nacb6\r\nacba\r\nacc2\r\nacc6\r\nacce\r\nacd2\r\nacda\r\nacde\r\nace6\r\nacea\r\nacf2\r\nacf6\r\nacfe\r\nad02\r\nad0a\r\nad0e\r\nad16\r\nad1a\r\nad22\r\nad26\r\nad2e\r\nad32\r\nad3a\r\nad3e\r\nad46\r\nad4a\r\nad52\r\nad56\r\nad5e\r\nBREAK\r\n1\r\n25118\r\nBREAK\r\n1\r\n2511e\r\nBREAK\r\n1\r\n4f1\r\nabec\r\nabee\r\nabf6\r\nabfa\r\nac02\r\nac06\r\nac0e\r\nac12\r\nac1a\r\nac1e\r\nac26\r\nac2a\r\nac32\r\nac36\r\nac3e\r\nac42\r\nac4a\r\nac4e\r\nac56\r\nac5a\r\nac62\r\nac66\r\nac6e\r\nac72\r\nac7a\r\nac7e\r\nac86\r\nac8a\r\nac92\r\nac96\r\nac9e\r\naca2\r\nacaa\r\nacae\r\nacb6\r\nacba\r\nacc2\r\nacc6\r\nacce\r\nacd2\r\nacda\r\nacde\r\nace6\r\nacea\r\nacf2\r\nacf6\r\nacfe\r\nad02\r\nad0a\r\nad0e\r\nad16\r\nad1a\r\nad22\r\nad26\r\nad2e\r\nad32\r\nad3a\r\nad3e\r\nad46\r\nad4a\r\nad52\r\nad56\r\nad5e\r\nBREAK\r\n1\r\n25124\r\nBREAK\r\n1\r\n2512a\r\nBREAK\r\n1\r\n4f1\r\nabec\r\nabee\r\nabf6\r\nabfa\r\nac02\r\nac06\r\nac0e\r\nac12\r\nac1a\r\nac1e\r\nac26\r\nac2a\r\nac32\r\nac36\r\nac3e\r\nac42\r\nac4a\r\nac4e\r\nac56\r\nac5a\r\nac62\r\nac66\r\nac6e\r\nac72\r\nac7a\r\nac7e\r\nac86\r\nac8a\r\nac92\r\nac96\r\nac9e\r\naca2\r\nacaa\r\nacae\r\nacb6\r\nacba\r\nacc2\r\nacc6\r\nacce\r\nacd2\r\nacda\r\nacde\r\nace6\r\nacea\r\nacf2\r\nacf6\r\nacfe\r\nad02\r\nad0a\r\nad0e\r\nad16\r\nad1a\r\nad22\r\nad26\r\nad2e\r\nad32\r\nad3a\r\nad3e\r\nad46\r\nad4a\r\nad52\r\nad56\r\nad5e\r\nBREAK\r\n1\r\n25130\r\nBREAK\r\n1\r\n25136\r\nBREAK\r\n1\r\n2513c\r\nBREAK\r\n1\r\n4f1\r\nabec\r\nabee\r\nabf6\r\nabfa\r\nac02\r\nac06\r\nac0e\r\nac12\r\nac1a\r\nac1e\r\nac26\r\nac2a\r\nac32\r\nac36\r\nac3e\r\nac42\r\nac4a\r\nac4e\r\nac56\r\nac5a\r\nac62\r\nac66\r\nac6e\r\nac72\r\nac7a\r\nac7e\r\nac86\r\nac8a\r\nac92\r\nac96\r\nac9e\r\naca2\r\nacaa\r\nacae\r\nacb6\r\nacba\r\nacc2\r\nacc6\r\nacce\r\nacd2\r\nacda\r\nacde\r\nace6\r\nacea\r\nacf2\r\nacf6\r\nacfe\r\nad02\r\nad0a\r\nad0e\r\nad16\r\nad1a\r\nad22\r\nad26\r\nad2e\r\nad32\r\nad3a\r\nad3e\r\nad46\r\nad4a\r\nad52\r\nad56\r\nad5e\r\nBREAK\r\n1\r\n25142\r\nBREAK\r\n1\r\n25148\r\nBREAK\r\n1\r\n4f1\r\nabec\r\nabee\r\nabf6\r\nabfa\r\nac02\r\nac06\r\nac0e\r\nac12\r\nac1a\r\nac1e\r\nac26\r\nac2a\r\nac32\r\nac36\r\nac3e\r\nac42\r\nac4a\r\nac4e\r\nac56\r\nac5a\r\nac62\r\nac66\r\nac6e\r\nac72\r\nac7a\r\nac7e\r\nac86\r\nac8a\r\nac92\r\nac96\r\nac9e\r\naca2\r\nacaa\r\nacae\r\nacb6\r\nacba\r\nacc2\r\nacc6\r\nacce\r\nacd2\r\nacda\r\nacde\r\nace6\r\nacea\r\nacf2\r\nacf6\r\nacfe\r\nad02\r\nad0a\r\nad0e\r\nad16\r\nad1a\r\nad22\r\nad26\r\nad2e\r\nad32\r\nad3a\r\nad3e\r\nad46\r\nad4a\r\nad52\r\nad56\r\nad5e\r\nBREAK\r\n1\r\n2514e\r\nBREAK\r\n1\r\n25154\r\nBREAK\r\n1\r\n2515a\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n25160\r\nBREAK\r\n1\r\n25166\r\nBREAK\r\n1\r\n2516c\r\nBREAK\r\n1\r\n25172\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n25178\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n2517e\r\nBREAK\r\n1\r\n25184\r\nBREAK\r\n1\r\n2518a\r\nBREAK\r\n1\r\n25190\r\nBREAK\r\n1\r\n25196\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n2519c\r\nBREAK\r\n1\r\n4fa\r\naf3a\r\naf54\r\naf58\r\naf5c\r\naf60\r\naf64\r\naf68\r\naf6c\r\naf70\r\nBREAK\r\n1\r\n251a2\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n251a8\r\nBREAK\r\n1\r\n251ae\r\nBREAK\r\n1\r\n251b4\r\nBREAK\r\n1\r\n251ba\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n251c0\r\nBREAK\r\n1\r\n4fa\r\naf3a\r\naf3c\r\naf40\r\naf44\r\naf48\r\naf4c\r\naf50\r\naf54\r\naf58\r\naf5c\r\naf60\r\naf64\r\naf68\r\naf6c\r\naf70\r\nBREAK\r\n1\r\n251c6\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n251cc\r\nBREAK\r\n1\r\n251d2\r\nBREAK\r\n1\r\n251d8\r\nBREAK\r\n1\r\n251de\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n251e4\r\nBREAK\r\n1\r\n4fd\r\naf74\r\naf76\r\naf7a\r\naf7e\r\naf82\r\naf86\r\naf8a\r\naf8e\r\naf92\r\naf96\r\naf9a\r\naf9e\r\nafa2\r\nafa6\r\nafaa\r\nBREAK\r\n1\r\n251ea\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n251f0\r\nBREAK\r\n1\r\n251f6\r\nBREAK\r\n1\r\n251fc\r\nBREAK\r\n1\r\n25202\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n25208\r\nBREAK\r\n1\r\n2520e\r\nBREAK\r\n1\r\n4fd\r\naf74\r\naf76\r\naf7a\r\naf7e\r\naf82\r\naf86\r\naf8a\r\naf8e\r\naf92\r\naf96\r\naf9a\r\naf9e\r\nafa2\r\nafa6\r\nafaa\r\nBREAK\r\n1\r\n25214\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n2521a\r\nBREAK\r\n1\r\n25220\r\nBREAK\r\n1\r\n25226\r\nBREAK\r\n1\r\n2522c\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n25232\r\nBREAK\r\n1\r\n25238\r\nBREAK\r\n1\r\n500\r\nafae\r\nafb0\r\nafb4\r\nafb8\r\nafbc\r\nafc0\r\nafc4\r\nafc8\r\nafcc\r\nafd0\r\nafd4\r\nafd8\r\nafdc\r\nafe0\r\nafe4\r\nBREAK\r\n1\r\n2523e\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n25244\r\nBREAK\r\n1\r\n2524a\r\nBREAK\r\n1\r\n25250\r\nBREAK\r\n1\r\n25256\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n2525c\r\nBREAK\r\n1\r\n25262\r\nBREAK\r\n1\r\n503\r\n0\r\nafe8\r\nafea\r\nafee\r\naff2\r\naff6\r\naffa\r\naffe\r\nb002\r\nb006\r\nb00a\r\nb00e\r\nb012\r\nb016\r\nb01a\r\nb01e\r\nBREAK\r\n1\r\n25268\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n2526e\r\nBREAK\r\n1\r\n25274\r\nBREAK\r\n1\r\n2527a\r\nBREAK\r\n1\r\n25280\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n25286\r\nBREAK\r\n1\r\n2528c\r\nBREAK\r\n1\r\n506\r\nb022\r\nb024\r\nb028\r\nb02c\r\nb030\r\nb034\r\nb038\r\nb03c\r\nb040\r\nb044\r\nb048\r\nb04c\r\nb050\r\nb054\r\nb058\r\nBREAK\r\n1\r\n25292\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n25298\r\nBREAK\r\n1\r\n2529e\r\nBREAK\r\n1\r\n252a4\r\nBREAK\r\n1\r\n252aa\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n252b0\r\nBREAK\r\n1\r\n252b6\r\nBREAK\r\n1\r\n509\r\nb05c\r\nb05e\r\nb062\r\nb066\r\nb06a\r\nb06e\r\nb072\r\nb076\r\nb07a\r\nb07e\r\nb082\r\nb086\r\nb08a\r\nb08e\r\nb092\r\nBREAK\r\n1\r\n252bc\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n252c2\r\nBREAK\r\n1\r\n252c8\r\nBREAK\r\n1\r\n252ce\r\nBREAK\r\n1\r\n252d4\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n252da\r\nBREAK\r\n1\r\n252e0\r\nBREAK\r\n1\r\n50c\r\nb096\r\nb098\r\nb09c\r\nb0a0\r\nb0a4\r\nb0a8\r\nb0ac\r\nb0b0\r\nb0b4\r\nb0b8\r\nb0bc\r\nb0c0\r\nb0c4\r\nb0c8\r\nb0cc\r\nBREAK\r\n1\r\n252e6\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n252ec\r\nBREAK\r\n1\r\n252f2\r\nBREAK\r\n1\r\n252f8\r\nBREAK\r\n1\r\n252fe\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n25304\r\nBREAK\r\n1\r\n2530a\r\nBREAK\r\n1\r\n4fa\r\naf3a\r\naf3c\r\naf40\r\naf44\r\naf48\r\naf4c\r\naf50\r\naf54\r\naf58\r\naf5c\r\naf60\r\naf64\r\naf68\r\naf6c\r\naf70\r\nBREAK\r\n1\r\n25310\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n25316\r\nBREAK\r\n1\r\n2531c\r\nBREAK\r\n1\r\n25322\r\nBREAK\r\n1\r\n25328\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n2532e\r\nBREAK\r\n1\r\n25334\r\nBREAK\r\n1\r\n500\r\nafae\r\nafb0\r\nafb4\r\nafb8\r\nafbc\r\nafc0\r\nafc4\r\nafc8\r\nafcc\r\nafd0\r\nafd4\r\nafd8\r\nafdc\r\nafe0\r\nafe4\r\nBREAK\r\n1\r\n2533a\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n25340\r\nBREAK\r\n1\r\n25346\r\nBREAK\r\n1\r\n2534c\r\nBREAK\r\n1\r\n25352\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n25358\r\nBREAK\r\n1\r\n2535e\r\nBREAK\r\n1\r\n503\r\n0\r\nafe8\r\nafea\r\nafee\r\naff2\r\naff6\r\naffa\r\naffe\r\nb002\r\nb006\r\nb00a\r\nb00e\r\nb012\r\nb016\r\nb01a\r\nb01e\r\nBREAK\r\n1\r\n25364\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n2536a\r\nBREAK\r\n1\r\n25370\r\nBREAK\r\n1\r\n25376\r\nBREAK\r\n1\r\n2537c\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n25382\r\nBREAK\r\n1\r\n25388\r\nBREAK\r\n1\r\n506\r\nb022\r\nb024\r\nb028\r\nb02c\r\nb030\r\nb034\r\nb038\r\nb03c\r\nb040\r\nb044\r\nb048\r\nb04c\r\nb050\r\nb054\r\nb058\r\nBREAK\r\n1\r\n2538e\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n25394\r\nBREAK\r\n1\r\n2539a\r\nBREAK\r\n1\r\n253a0\r\nBREAK\r\n1\r\n253a6\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n253ac\r\nBREAK\r\n1\r\n253b2\r\nBREAK\r\n1\r\n50f\r\nb0d0\r\nb0d2\r\nb0d6\r\nb0da\r\nb0de\r\nb0e2\r\nb0e6\r\nb0ea\r\nb0ee\r\nb0f2\r\nb0f6\r\nb0fa\r\nb0fe\r\nb102\r\nb106\r\nBREAK\r\n1\r\n253b8\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n253be\r\nBREAK\r\n1\r\n253c4\r\nBREAK\r\n1\r\n253ca\r\nBREAK\r\n1\r\n253d0\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n253d6\r\nBREAK\r\n1\r\n253dc\r\nBREAK\r\n1\r\n512\r\nb10a\r\nb10c\r\nb110\r\nb114\r\nb118\r\nb11c\r\nb120\r\nb124\r\nb128\r\nb12c\r\nb130\r\nb134\r\nb138\r\nb13c\r\nb140\r\nBREAK\r\n1\r\n253e2\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n253e8\r\nBREAK\r\n1\r\n253ee\r\nBREAK\r\n1\r\n253f4\r\nBREAK\r\n1\r\n253fa\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n25400\r\nBREAK\r\n1\r\n25406\r\nBREAK\r\n1\r\n50f\r\nb0d0\r\nb0d2\r\nb0d6\r\nb0da\r\nb0de\r\nb0e2\r\nb0e6\r\nb0ea\r\nb0ee\r\nb0f2\r\nb0f6\r\nb0fa\r\nb0fe\r\nb102\r\nb106\r\nBREAK\r\n1\r\n2540c\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n25412\r\nBREAK\r\n1\r\n25418\r\nBREAK\r\n1\r\n2541e\r\nBREAK\r\n1\r\n25424\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n2542a\r\nBREAK\r\n1\r\n25430\r\nBREAK\r\n1\r\n512\r\nb10a\r\nb10c\r\nb110\r\nb114\r\nb118\r\nb11c\r\nb120\r\nb124\r\nb128\r\nb12c\r\nb130\r\nb134\r\nb138\r\nb13c\r\nb140\r\nBREAK\r\n1\r\n25436\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n2543c\r\nBREAK\r\n1\r\n25442\r\nBREAK\r\n1\r\n25448\r\nBREAK\r\n1\r\n2544e\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n25454\r\nBREAK\r\n1\r\n2545a\r\nBREAK\r\n1\r\n50f\r\nb0d0\r\nb0d2\r\nb0d6\r\nb0da\r\nb0de\r\nb0e2\r\nb0e6\r\nb0ea\r\nb0ee\r\nb0f2\r\nb0f6\r\nb0fa\r\nb0fe\r\nb102\r\nb106\r\nBREAK\r\n1\r\n25460\r\nBREAK\r\n1\r\n25466\r\nBREAK\r\n1\r\n515\r\nb144\r\nb146\r\nb14e\r\nb152\r\nb15a\r\nb15e\r\nb166\r\nb16a\r\nb172\r\nb176\r\nb17e\r\nb182\r\nb18a\r\nb18e\r\nb196\r\nb19a\r\nb1a2\r\nb1a6\r\nb1ae\r\nb1b2\r\nb1ba\r\nb1be\r\nb1c6\r\nb1ca\r\nb1d2\r\nb1d6\r\nb1de\r\nb1e2\r\nb1ea\r\nb1ee\r\nb1f6\r\nb1fa\r\nb202\r\nb206\r\nb20e\r\nb212\r\nb21a\r\nb21e\r\nb226\r\nb22a\r\nb232\r\nb236\r\nb23e\r\nb242\r\nb24a\r\nb24e\r\nb256\r\nb25a\r\nb262\r\nb266\r\nb26e\r\nb272\r\nb27a\r\nb27e\r\nb286\r\nb28a\r\nb292\r\nb296\r\nb29e\r\nb2a2\r\nb2aa\r\nb2ae\r\nb2b6\r\nBREAK\r\n1\r\n2546c\r\nBREAK\r\n1\r\n25472\r\nBREAK\r\n1\r\n512\r\nb10a\r\nb10c\r\nb110\r\nb114\r\nb118\r\nb11c\r\nb120\r\nb124\r\nb128\r\nb12c\r\nb130\r\nb134\r\nb138\r\nb13c\r\nb140\r\nBREAK\r\n1\r\n25478\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n2547e\r\nBREAK\r\n1\r\n25484\r\nBREAK\r\n1\r\n2548a\r\nBREAK\r\n1\r\n25490\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n25496\r\nBREAK\r\n1\r\n2549c\r\nBREAK\r\n1\r\n50f\r\nb0d0\r\nb0d2\r\nb0d6\r\nb0da\r\nb0de\r\nb0e2\r\nb0e6\r\nb0ea\r\nb0ee\r\nb0f2\r\nb0f6\r\nb0fa\r\nb0fe\r\nb102\r\nb106\r\nBREAK\r\n1\r\n254a2\r\nBREAK\r\n1\r\n254a8\r\nBREAK\r\n1\r\n515\r\nb144\r\nb146\r\nb14e\r\nb152\r\nb15a\r\nb15e\r\nb166\r\nb16a\r\nb172\r\nb176\r\nb17e\r\nb182\r\nb18a\r\nb18e\r\nb196\r\nb19a\r\nb1a2\r\nb1a6\r\nb1ae\r\nb1b2\r\nb1ba\r\nb1be\r\nb1c6\r\nb1ca\r\nb1d2\r\nb1d6\r\nb1de\r\nb1e2\r\nb1ea\r\nb1ee\r\nb1f6\r\nb1fa\r\nb202\r\nb206\r\nb20e\r\nb212\r\nb21a\r\nb21e\r\nb226\r\nb22a\r\nb232\r\nb236\r\nb23e\r\nb242\r\nb24a\r\nb24e\r\nb256\r\nb25a\r\nb262\r\nb266\r\nb26e\r\nb272\r\nb27a\r\nb27e\r\nb286\r\nb28a\r\nb292\r\nb296\r\nb29e\r\nb2a2\r\nb2aa\r\nb2ae\r\nb2b6\r\nBREAK\r\n1\r\n254ae\r\nBREAK\r\n1\r\n512\r\nb10a\r\nb10c\r\nb110\r\nb114\r\nb118\r\nb11c\r\nb120\r\nb124\r\nb128\r\nb12c\r\nb130\r\nb134\r\nb138\r\nb13c\r\nb140\r\nBREAK\r\n1\r\n254b4\r\nBREAK\r\n1\r\n254ba\r\nBREAK\r\n1\r\n254c0\r\nBREAK\r\n1\r\n254c6\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n254cc\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n254d2\r\nBREAK\r\n1\r\n254d8\r\nBREAK\r\n1\r\n254de\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n254e4\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n254ea\r\nBREAK\r\n1\r\n254f0\r\nBREAK\r\n1\r\n254f6\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n254fc\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n25502\r\nBREAK\r\n1\r\n25508\r\nBREAK\r\n1\r\n2550e\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n25514\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n2551a\r\nBREAK\r\n1\r\n25520\r\nBREAK\r\n1\r\n25526\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n2552c\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n25532\r\nBREAK\r\n1\r\n25538\r\nBREAK\r\n1\r\n2553e\r\nBREAK\r\n1\r\n25544\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n2554a\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n25550\r\nBREAK\r\n1\r\n25556\r\nBREAK\r\n1\r\n2555c\r\nBREAK\r\n1\r\n25562\r\nBREAK\r\n1\r\n25568\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n2556e\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n25574\r\nBREAK\r\n1\r\n2557a\r\nBREAK\r\n1\r\n25580\r\nBREAK\r\n1\r\n25586\r\nBREAK\r\n1\r\n2558c\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n25592\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n25598\r\nBREAK\r\n1\r\n2559e\r\nBREAK\r\n1\r\n255a4\r\nBREAK\r\n1\r\n255aa\r\nBREAK\r\n1\r\n255b0\r\nBREAK\r\n1\r\n255b6\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n255bc\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n255c2\r\nBREAK\r\n1\r\n255c8\r\nBREAK\r\n1\r\n255ce\r\nBREAK\r\n1\r\n255d4\r\nBREAK\r\n1\r\n255da\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n255e0\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n255e6\r\nBREAK\r\n1\r\n255ec\r\nBREAK\r\n1\r\n255f2\r\nBREAK\r\n1\r\n255f8\r\nBREAK\r\n1\r\n255fe\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n25604\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n2560a\r\nBREAK\r\n1\r\n25610\r\nBREAK\r\n1\r\n25616\r\nBREAK\r\n1\r\n2561c\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n25622\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n25628\r\nBREAK\r\n1\r\n2562e\r\nBREAK\r\n1\r\n25634\r\nBREAK\r\n1\r\n2563a\r\nBREAK\r\n1\r\n25640\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n25646\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n2564c\r\nBREAK\r\n1\r\n25652\r\nBREAK\r\n1\r\n25658\r\nBREAK\r\n1\r\n2565e\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n25664\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n2566a\r\nBREAK\r\n1\r\n25670\r\nBREAK\r\n1\r\n25676\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n2567c\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n25682\r\nBREAK\r\n1\r\n25688\r\nBREAK\r\n1\r\n2568e\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n25694\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n2569a\r\nBREAK\r\n1\r\n256a0\r\nBREAK\r\n1\r\n256a6\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n256ac\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n256b2\r\nBREAK\r\n1\r\n256b8\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n256be\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n256c4\r\nBREAK\r\n1\r\n256ca\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n256d0\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n256d6\r\nBREAK\r\n1\r\n256dc\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n256e2\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n256e8\r\nBREAK\r\n1\r\n256ee\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n256f4\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n256fa\r\nBREAK\r\n1\r\n25700\r\nBREAK\r\n1\r\n482\r\n92ee\r\n92f0\r\n92f8\r\n9300\r\n9308\r\n9310\r\n9318\r\n9320\r\n9328\r\n9330\r\n9338\r\nc0008\r\n9340\r\nf00008\r\n9348\r\n8\r\n9350\r\n9358\r\n9360\r\n9368\r\n9370\r\n8\r\n9378\r\n8\r\n9380\r\n8\r\n9388\r\n8\r\n9390\r\n8\r\n9398\r\n8\r\n93a0\r\n8\r\n93a8\r\n8\r\n93b0\r\nc00008\r\n93b8\r\n93c0\r\n93c8\r\n93d0\r\n93d8\r\n93e0\r\nBREAK\r\n1\r\n25706\r\nBREAK\r\n1\r\n47f\r\n92a0\r\n92a2\r\n92a6\r\n92aa\r\n92ae\r\n92b2\r\n92b6\r\n92ba\r\n92be\r\n92c2\r\n92c6\r\n92ca\r\n92ce\r\n92d2\r\n92d6\r\n92da\r\n92de\r\n92e2\r\n92e6\r\n92ea\r\nBREAK\r\n1\r\n2570c\r\nBREAK\r\n1\r\n25712\r\nBREAK\r\n1\r\n482\r\n92ee\r\n92f0\r\n92f8\r\n9300\r\n9308\r\n9310\r\n9318\r\n9320\r\n9328\r\n9330\r\n9338\r\nc0008\r\n9340\r\nf00008\r\n9348\r\n8\r\n9350\r\n9358\r\n9360\r\n9368\r\n9370\r\n8\r\n9378\r\n8\r\n9380\r\n8\r\n9388\r\n8\r\n9390\r\n8\r\n9398\r\n8\r\n93a0\r\n8\r\n93a8\r\n8\r\n93b0\r\nc00008\r\n93b8\r\n93c0\r\n93c8\r\n93d0\r\n93d8\r\n93e0\r\nBREAK\r\n1\r\n25718\r\nBREAK\r\n1\r\n47f\r\n92a0\r\n92a2\r\n92a6\r\n92aa\r\n92ae\r\n92b2\r\n92b6\r\n92ba\r\n92be\r\n92c2\r\n92c6\r\n92ca\r\n92ce\r\n92d2\r\n92d6\r\n92da\r\n92de\r\n92e2\r\n92e6\r\n92ea\r\nBREAK\r\n1\r\n2571e\r\nBREAK\r\n1\r\n25724\r\nBREAK\r\n1\r\n482\r\n92ee\r\n92f0\r\n92f8\r\n9300\r\n9308\r\n9310\r\n9318\r\n9320\r\n9328\r\n9330\r\n9338\r\nc0008\r\n9340\r\nf00008\r\n9348\r\n8\r\n9350\r\n9358\r\n9360\r\n9368\r\n9370\r\n8\r\n9378\r\n8\r\n9380\r\n8\r\n9388\r\n8\r\n9390\r\n8\r\n9398\r\n8\r\n93a0\r\n8\r\n93a8\r\n8\r\n93b0\r\nc00008\r\n93b8\r\n93c0\r\n93c8\r\n93d0\r\n93d8\r\n93e0\r\nBREAK\r\n1\r\n2572a\r\nBREAK\r\n1\r\n47f\r\n92a0\r\n92a2\r\n92a6\r\n92aa\r\n92ae\r\n92b2\r\n92b6\r\n92ba\r\n92be\r\n92c2\r\n92c6\r\n92ca\r\n92ce\r\n92d2\r\n92d6\r\n92da\r\n92de\r\n92e2\r\n92e6\r\n92ea\r\nBREAK\r\n1\r\n25730\r\nBREAK\r\n1\r\n25736\r\nBREAK\r\n1\r\n482\r\n92ee\r\n92f0\r\n92f8\r\n9300\r\n9308\r\n9310\r\n9318\r\n9320\r\n9328\r\n9330\r\n9338\r\nc0008\r\n9340\r\nf00008\r\n9348\r\n8\r\n9350\r\n9358\r\n9360\r\n9368\r\n9370\r\n8\r\n9378\r\n8\r\n9380\r\n8\r\n9388\r\n8\r\n9390\r\n8\r\n9398\r\n8\r\n93a0\r\n8\r\n93a8\r\n8\r\n93b0\r\nc00008\r\n93b8\r\n93c0\r\n93c8\r\n93d0\r\n93d8\r\n93e0\r\nBREAK\r\n1\r\n2573c\r\nBREAK\r\n1\r\n47f\r\n92a0\r\n92a2\r\n92a6\r\n92aa\r\n92ae\r\n92b2\r\n92b6\r\n92ba\r\n92be\r\n92c2\r\n92c6\r\n92ca\r\n92ce\r\n92d2\r\n92d6\r\n92da\r\n92de\r\n92e2\r\n92e6\r\n92ea\r\nBREAK\r\n1\r\n25742\r\nBREAK\r\n1\r\n25748\r\nBREAK\r\n1\r\n491\r\n97d0\r\n97d2\r\n97d3\r\n97d4\r\n97d5\r\n97d6\r\n97d7\r\n97d8\r\nBREAK\r\n1\r\n2574e\r\nBREAK\r\n1\r\n25754\r\nBREAK\r\n1\r\n482\r\n92ee\r\n92f0\r\n92f8\r\n9300\r\n9308\r\n9310\r\n9318\r\n9320\r\n9328\r\n9330\r\n9338\r\nc0008\r\n9340\r\nf00008\r\n9348\r\n8\r\n9350\r\n9358\r\n9360\r\n9368\r\n9370\r\n8\r\n9378\r\n8\r\n9380\r\n8\r\n9388\r\n8\r\n9390\r\n8\r\n9398\r\n8\r\n93a0\r\n8\r\n93a8\r\n8\r\n93b0\r\nc00008\r\n93b8\r\n93c0\r\n93c8\r\n93d0\r\n93d8\r\n93e0\r\nBREAK\r\n1\r\n2575a\r\nBREAK\r\n1\r\n47f\r\n92a0\r\n92a2\r\n92a6\r\n92aa\r\n92ae\r\n92b2\r\n92b6\r\n92ba\r\n92be\r\n92c2\r\n92c6\r\n92ca\r\n92ce\r\n92d2\r\n92d6\r\n92da\r\n92de\r\n92e2\r\n92e6\r\n92ea\r\nBREAK\r\n1\r\n25760\r\nBREAK\r\n1\r\n25766\r\nBREAK\r\n1\r\n494\r\n97d9\r\n97db\r\n97dc\r\n97dd\r\n97de\r\n97df\r\n97e0\r\n97e1\r\nBREAK\r\n1\r\n2576c\r\nBREAK\r\n1\r\n25772\r\nBREAK\r\n1\r\n482\r\n92ee\r\n92f0\r\n92f8\r\n9300\r\n9308\r\n9310\r\n9318\r\n9320\r\n9328\r\n9330\r\n9338\r\nc0008\r\n9340\r\nf00008\r\n9348\r\n8\r\n9350\r\n9358\r\n9360\r\n9368\r\n9370\r\n8\r\n9378\r\n8\r\n9380\r\n8\r\n9388\r\n8\r\n9390\r\n8\r\n9398\r\n8\r\n93a0\r\n8\r\n93a8\r\n8\r\n93b0\r\nc00008\r\n93b8\r\n93c0\r\n93c8\r\n93d0\r\n93d8\r\n93e0\r\nBREAK\r\n1\r\n25778\r\nBREAK\r\n1\r\n47f\r\n92a0\r\n92a2\r\n92a6\r\n92aa\r\n92ae\r\n92b2\r\n92b6\r\n92ba\r\n92be\r\n92c2\r\n92c6\r\n92ca\r\n92ce\r\n92d2\r\n92d6\r\n92da\r\n92de\r\n92e2\r\n92e6\r\n92ea\r\nBREAK\r\n1\r\n2577e\r\nBREAK\r\n1\r\n25784\r\nBREAK\r\n1\r\n497\r\n97e2\r\n97e4\r\n97e5\r\n97e6\r\n97e7\r\n97e8\r\n97e9\r\n97ea\r\nBREAK\r\n1\r\n2578a\r\nBREAK\r\n1\r\n25790\r\nBREAK\r\n1\r\n485\r\n93e8\r\n93ea\r\n93f2\r\n93fa\r\n9402\r\n940a\r\n9412\r\n941a\r\n9422\r\n942a\r\n9432\r\nc0008\r\n943a\r\nf00008\r\n9442\r\n8\r\n944a\r\n9452\r\n945a\r\n9462\r\n946a\r\n8\r\n9472\r\n8\r\n947a\r\n8008\r\n9482\r\na22808\r\n948a\r\n9492\r\n949a\r\n94a2\r\n94aa\r\n94b2\r\n94ba\r\n94c2\r\n94ca\r\n94d2\r\n94da\r\nBREAK\r\n1\r\n25796\r\nBREAK\r\n1\r\n47f\r\n92a0\r\n92a2\r\n92a6\r\n92aa\r\n92ae\r\n92b2\r\n92b6\r\n92ba\r\n92be\r\n92c2\r\n92c6\r\n92ca\r\n92ce\r\n92d2\r\n92d6\r\n92da\r\n92de\r\n92e2\r\n92e6\r\n92ea\r\nBREAK\r\n1\r\n2579c\r\nBREAK\r\n1\r\n257a2\r\nBREAK\r\n1\r\n49a\r\n97eb\r\n97ed\r\n97ee\r\n97ef\r\n97f0\r\n97f1\r\n97f2\r\n97f3\r\nBREAK\r\n1\r\n257a8\r\nBREAK\r\n1\r\n257ae\r\nBREAK\r\n1\r\n488\r\n94e2\r\n94e4\r\n94ec\r\nc0008\r\n94f4\r\nf00008\r\n94fc\r\n8\r\n9504\r\n950c\r\n9514\r\n951c\r\n9524\r\n8\r\n952c\r\n8\r\n9534\r\n8\r\n953c\r\n8\r\n9544\r\n8\r\n954c\r\n8\r\n9554\r\n8\r\n955c\r\n8\r\n9564\r\nc00008\r\n956c\r\n9574\r\n957c\r\n9584\r\n958c\r\n9594\r\n959c\r\n95a4\r\n95ac\r\n95b4\r\n95bc\r\n95c4\r\n95cc\r\n95d4\r\nBREAK\r\n1\r\n257b4\r\nBREAK\r\n1\r\n47f\r\n92a0\r\n92a2\r\n92a6\r\n92aa\r\n92ae\r\n92b2\r\n92b6\r\n92ba\r\n92be\r\n92c2\r\n92c6\r\n92ca\r\n92ce\r\n92d2\r\n92d6\r\n92da\r\n92de\r\n92e2\r\n92e6\r\n92ea\r\nBREAK\r\n1\r\n257ba\r\nBREAK\r\n1\r\n257c0\r\nBREAK\r\n1\r\n48b\r\n95dc\r\n95de\r\n95e6\r\n8\r\n95ee\r\n8\r\n95f6\r\n8\r\n95fe\r\n8\r\n9606\r\n8\r\n960e\r\n8\r\n9616\r\n8\r\n961e\r\n8\r\n9626\r\nc00008\r\n962e\r\n9636\r\n963e\r\n9646\r\n964e\r\n9656\r\n965e\r\n9666\r\n966e\r\n9676\r\n967e\r\n9686\r\n968e\r\n9696\r\n969e\r\n96a6\r\n96ae\r\n96b6\r\n96be\r\n96c6\r\n96ce\r\nBREAK\r\n1\r\n257c6\r\nBREAK\r\n1\r\n47f\r\n92a0\r\n92a2\r\n92a6\r\n92aa\r\n92ae\r\n92b2\r\n92b6\r\n92ba\r\n92be\r\n92c2\r\n92c6\r\n92ca\r\n92ce\r\n92d2\r\n92d6\r\n92da\r\n92de\r\n92e2\r\n92e6\r\n92ea\r\nBREAK\r\n1\r\n257cc\r\nBREAK\r\n1\r\n257d2\r\nBREAK\r\n1\r\n48e\r\n96d6\r\n96d8\r\n96e0\r\n96e8\r\n96f0\r\n96f8\r\n9700\r\n9708\r\n9710\r\n9718\r\n9720\r\n9728\r\n9730\r\n9738\r\n9740\r\n9748\r\n9750\r\n9758\r\n9760\r\n9768\r\n9770\r\n9778\r\n9780\r\n9788\r\n9790\r\n9798\r\n97a0\r\n97a8\r\n97b0\r\n97b8\r\n97c0\r\n97c8\r\nBREAK\r\n1\r\n257d8\r\nBREAK\r\n1\r\n47f\r\n92a0\r\n92a2\r\n92a6\r\n92aa\r\n92ae\r\n92b2\r\n92b6\r\n92ba\r\n92be\r\n92c2\r\n92c6\r\n92ca\r\n92ce\r\n92d2\r\n92d6\r\n92da\r\n92de\r\n92e2\r\n92e6\r\n92ea\r\nBREAK\r\n1\r\n257de\r\nBREAK\r\n1\r\n257e4\r\nBREAK\r\n1\r\n47f\r\n92a0\r\n92a2\r\n92a6\r\n92aa\r\n92ae\r\n92b2\r\n92b6\r\n92ba\r\n92be\r\n92c2\r\n92c6\r\n92ca\r\n92ce\r\n92d2\r\n92d6\r\n92da\r\n92de\r\n92e2\r\n92e6\r\n92ea\r\nBREAK\r\n1\r\n257ea\r\nBREAK\r\n1\r\n257f0\r\nBREAK\r\n1\r\n49d\r\n97f4\r\n97f6\r\n97fe\r\n9802\r\n980a\r\n980e\r\n9816\r\n981a\r\n9822\r\n9826\r\n982e\r\n9832\r\n983a\r\n983e\r\n9846\r\n984a\r\n9852\r\n9856\r\n985e\r\n9862\r\n986a\r\n986e\r\n9876\r\n987a\r\n9882\r\n9886\r\n988e\r\n9892\r\n989a\r\n989e\r\n98a6\r\n98aa\r\n98b2\r\n98b6\r\n98be\r\n98c2\r\n98ca\r\n98ce\r\n98d6\r\n98da\r\n98e2\r\n98e6\r\n98ee\r\n98f2\r\n98fa\r\n98fe\r\n9906\r\n990a\r\n9912\r\n9916\r\n991e\r\n9922\r\n992a\r\n992e\r\n9936\r\n993a\r\n9942\r\n9946\r\n994e\r\n9952\r\n995a\r\n995e\r\n9966\r\nBREAK\r\n1\r\n257f6\r\nBREAK\r\n1\r\n49d\r\n97f4\r\n97f6\r\n97fe\r\n9802\r\n980a\r\n980e\r\n9816\r\n981a\r\n9822\r\n9826\r\n982e\r\n9832\r\n983a\r\n983e\r\n9846\r\n984a\r\n9852\r\n9856\r\n985e\r\n9862\r\n986a\r\n986e\r\n9876\r\n987a\r\n9882\r\n9886\r\n988e\r\n9892\r\n989a\r\n989e\r\n98a6\r\n98aa\r\n98b2\r\n98b6\r\n98be\r\n98c2\r\n98ca\r\n98ce\r\n98d6\r\n98da\r\n98e2\r\n98e6\r\n98ee\r\n98f2\r\n98fa\r\n98fe\r\n9906\r\n990a\r\n9912\r\n9916\r\n991e\r\n9922\r\n992a\r\n992e\r\n9936\r\n993a\r\n9942\r\n9946\r\n994e\r\n9952\r\n995a\r\n995e\r\n9966\r\nBREAK\r\n1\r\n257fc\r\nBREAK\r\n1\r\n4a3\r\n9ae0\r\n9ae5\r\n3009a\r\n9aea\r\n9aef\r\n9af4\r\n9af9\r\n9afe\r\n9b03\r\n0\r\nBREAK\r\n1\r\n25802\r\nBREAK\r\n1\r\n49d\r\n97f4\r\n97f6\r\n97fe\r\n9802\r\n980a\r\n980e\r\n9816\r\n981a\r\n9822\r\n9826\r\n982e\r\n9832\r\n983a\r\n983e\r\n9846\r\n984a\r\n9852\r\n9856\r\n985e\r\n9862\r\n986a\r\n986e\r\n9876\r\n987a\r\n9882\r\n9886\r\n988e\r\n9892\r\n989a\r\n989e\r\n98a6\r\n98aa\r\n98b2\r\n98b6\r\n98be\r\n98c2\r\n98ca\r\n98ce\r\n98d6\r\n98da\r\n98e2\r\n98e6\r\n98ee\r\n98f2\r\n98fa\r\n98fe\r\n9906\r\n990a\r\n9912\r\n9916\r\n991e\r\n9922\r\n992a\r\n992e\r\n9936\r\n993a\r\n9942\r\n9946\r\n994e\r\n9952\r\n995a\r\n995e\r\n9966\r\nBREAK\r\n1\r\n25808\r\nBREAK\r\n1\r\n4a3\r\n9ae0\r\n9ae3\r\n3009a\r\n9ae8\r\n9aed\r\n9af2\r\n9af7\r\n9afc\r\n9b01\r\nBREAK\r\n1\r\n2580e\r\nBREAK\r\n1\r\n49d\r\n97f4\r\n97f6\r\n97fe\r\n9802\r\n980a\r\n980e\r\n9816\r\n981a\r\n9822\r\n9826\r\n982e\r\n9832\r\n983a\r\n983e\r\n9846\r\n984a\r\n9852\r\n9856\r\n985e\r\n9862\r\n986a\r\n986e\r\n9876\r\n987a\r\n9882\r\n9886\r\n988e\r\n9892\r\n989a\r\n989e\r\n98a6\r\n98aa\r\n98b2\r\n98b6\r\n98be\r\n98c2\r\n98ca\r\n98ce\r\n98d6\r\n98da\r\n98e2\r\n98e6\r\n98ee\r\n98f2\r\n98fa\r\n98fe\r\n9906\r\n990a\r\n9912\r\n9916\r\n991e\r\n9922\r\n992a\r\n992e\r\n9936\r\n993a\r\n9942\r\n9946\r\n994e\r\n9952\r\n995a\r\n995e\r\n9966\r\nBREAK\r\n1\r\n25814\r\nBREAK\r\n1\r\n4a3\r\n9ae0\r\n9ae2\r\n3009a\r\n9ae7\r\n9aec\r\n9af1\r\n9af6\r\n9afb\r\n9b00\r\nBREAK\r\n1\r\n2581a\r\nBREAK\r\n1\r\n49d\r\n97f4\r\n97f6\r\n97fe\r\n9802\r\n980a\r\n980e\r\n9816\r\n981a\r\n9822\r\n9826\r\n982e\r\n9832\r\n983a\r\n983e\r\n9846\r\n984a\r\n9852\r\n9856\r\n985e\r\n9862\r\n986a\r\n986e\r\n9876\r\n987a\r\n9882\r\n9886\r\n988e\r\n9892\r\n989a\r\n989e\r\n98a6\r\n98aa\r\n98b2\r\n98b6\r\n98be\r\n98c2\r\n98ca\r\n98ce\r\n98d6\r\n98da\r\n98e2\r\n98e6\r\n98ee\r\n98f2\r\n98fa\r\n98fe\r\n9906\r\n990a\r\n9912\r\n9916\r\n991e\r\n9922\r\n992a\r\n992e\r\n9936\r\n993a\r\n9942\r\n9946\r\n994e\r\n9952\r\n995a\r\n995e\r\n9966\r\nBREAK\r\n1\r\n25820\r\nBREAK\r\n1\r\n4a3\r\n9ae0\r\n9ae2\r\n3009a\r\n9ae7\r\n9aec\r\n9af1\r\n9af6\r\n9afb\r\n9b00\r\nBREAK\r\n1\r\n25826\r\nBREAK\r\n1\r\n49d\r\n97f4\r\n97f6\r\n97fe\r\n9802\r\n980a\r\n980e\r\n9816\r\n981a\r\n9822\r\n9826\r\n982e\r\n9832\r\n983a\r\n983e\r\n9846\r\n984a\r\n9852\r\n9856\r\n985e\r\n9862\r\n986a\r\n986e\r\n9876\r\n987a\r\n9882\r\n9886\r\n988e\r\n9892\r\n989a\r\n989e\r\n98a6\r\n98aa\r\n98b2\r\n98b6\r\n98be\r\n98c2\r\n98ca\r\n98ce\r\n98d6\r\n98da\r\n98e2\r\n98e6\r\n98ee\r\n98f2\r\n98fa\r\n98fe\r\n9906\r\n990a\r\n9912\r\n9916\r\n991e\r\n9922\r\n992a\r\n992e\r\n9936\r\n993a\r\n9942\r\n9946\r\n994e\r\n9952\r\n995a\r\n995e\r\n9966\r\nBREAK\r\n1\r\n2582c\r\nBREAK\r\n1\r\n4a3\r\n9ae0\r\n9ae2\r\n3009a\r\n9ae7\r\n9aec\r\n9af1\r\n9af6\r\n9afb\r\n9b00\r\nBREAK\r\n1\r\n25832\r\nBREAK\r\n1\r\n49d\r\n97f4\r\n97f6\r\n97fe\r\n9802\r\n980a\r\n980e\r\n9816\r\n981a\r\n9822\r\n9826\r\n982e\r\n9832\r\n983a\r\n983e\r\n9846\r\n984a\r\n9852\r\n9856\r\n985e\r\n9862\r\n986a\r\n986e\r\n9876\r\n987a\r\n9882\r\n9886\r\n988e\r\n9892\r\n989a\r\n989e\r\n98a6\r\n98aa\r\n98b2\r\n98b6\r\n98be\r\n98c2\r\n98ca\r\n98ce\r\n98d6\r\n98da\r\n98e2\r\n98e6\r\n98ee\r\n98f2\r\n98fa\r\n98fe\r\n9906\r\n990a\r\n9912\r\n9916\r\n991e\r\n9922\r\n992a\r\n992e\r\n9936\r\n993a\r\n9942\r\n9946\r\n994e\r\n9952\r\n995a\r\n995e\r\n9966\r\nBREAK\r\n1\r\n25838\r\nBREAK\r\n1\r\n4a3\r\n9ae0\r\n9ae2\r\n3009a\r\n9ae7\r\n9aec\r\n9af1\r\n9af6\r\n9afb\r\n9b00\r\nBREAK\r\n1\r\n2583e\r\nBREAK\r\n1\r\n49d\r\n97f4\r\n97f6\r\n97fe\r\n9802\r\n980a\r\n980e\r\n9816\r\n981a\r\n9822\r\n9826\r\n982e\r\n9832\r\n983a\r\n983e\r\n9846\r\n984a\r\n9852\r\n9856\r\n985e\r\n9862\r\n986a\r\n986e\r\n9876\r\n987a\r\n9882\r\n9886\r\n988e\r\n9892\r\n989a\r\n989e\r\n98a6\r\n98aa\r\n98b2\r\n98b6\r\n98be\r\n98c2\r\n98ca\r\n98ce\r\n98d6\r\n98da\r\n98e2\r\n98e6\r\n98ee\r\n98f2\r\n98fa\r\n98fe\r\n9906\r\n990a\r\n9912\r\n9916\r\n991e\r\n9922\r\n992a\r\n992e\r\n9936\r\n993a\r\n9942\r\n9946\r\n994e\r\n9952\r\n995a\r\n995e\r\n9966\r\nBREAK\r\n1\r\n25844\r\nBREAK\r\n1\r\n4a3\r\n9ae0\r\n9ae2\r\n3009a\r\n9ae7\r\n9aec\r\n9af1\r\n9af6\r\n9afb\r\n9b00\r\nBREAK\r\n1\r\n2584a\r\nBREAK\r\n1\r\n49d\r\n97f4\r\n97f6\r\n97fe\r\n9802\r\n980a\r\n980e\r\n9816\r\n981a\r\n9822\r\n9826\r\n982e\r\n9832\r\n983a\r\n983e\r\n9846\r\n984a\r\n9852\r\n9856\r\n985e\r\n9862\r\n986a\r\n986e\r\n9876\r\n987a\r\n9882\r\n9886\r\n988e\r\n9892\r\n989a\r\n989e\r\n98a6\r\n98aa\r\n98b2\r\n98b6\r\n98be\r\n98c2\r\n98ca\r\n98ce\r\n98d6\r\n98da\r\n98e2\r\n98e6\r\n98ee\r\n98f2\r\n98fa\r\n98fe\r\n9906\r\n990a\r\n9912\r\n9916\r\n991e\r\n9922\r\n992a\r\n992e\r\n9936\r\n993a\r\n9942\r\n9946\r\n994e\r\n9952\r\n995a\r\n995e\r\n9966\r\nBREAK\r\n1\r\n25850\r\nBREAK\r\n1\r\n4a3\r\n9ae0\r\n9ae2\r\n3009a\r\n9ae7\r\n9aec\r\n9af1\r\n9af6\r\n9afb\r\n9b00\r\nBREAK\r\n1\r\n25856\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n2585c\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n25862\r\nBREAK\r\n1\r\n4a6\r\n9b05\r\n9b09\r\n9b0d\r\n9b11\r\n9b15\r\n9b19\r\n9b1d\r\n9b21\r\nBREAK\r\n1\r\n25868\r\n100300\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n2586e\r\nBREAK\r\n1\r\n4a6\r\n9b05\r\n9b08\r\n9b0c\r\n9b10\r\n9b14\r\n9b18\r\n9b1c\r\n9b20\r\nBREAK\r\n1\r\n25874\r\n100300\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n2587a\r\nBREAK\r\n1\r\n4a6\r\n9b05\r\n9b07\r\n9b0b\r\n9b0f\r\n9b13\r\n9b17\r\n9b1b\r\n9b1f\r\nBREAK\r\n1\r\n25880\r\n100300\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n25886\r\nBREAK\r\n1\r\n4a6\r\n9b05\r\n9b07\r\n9b0b\r\n9b0f\r\n9b13\r\n9b17\r\n9b1b\r\n9b1f\r\nBREAK\r\n1\r\n2588c\r\n100300\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n25892\r\nBREAK\r\n1\r\n4a6\r\n9b05\r\n9b07\r\n9b0b\r\n9b0f\r\n9b13\r\n9b17\r\n9b1b\r\n9b1f\r\nBREAK\r\n1\r\n25898\r\n100300\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n2589e\r\nBREAK\r\n1\r\n4a6\r\n9b05\r\n9b07\r\n9b0b\r\n9b0f\r\n9b13\r\n9b17\r\n9b1b\r\n9b1f\r\nBREAK\r\n1\r\n258a4\r\n100300\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n258aa\r\nBREAK\r\n1\r\n4a6\r\n9b05\r\n9b07\r\n9b0b\r\n9b0f\r\n9b13\r\n9b17\r\n9b1b\r\n9b1f\r\nBREAK\r\n1\r\n258b0\r\n190300\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n258b6\r\nBREAK\r\n1\r\n4a6\r\n9b05\r\n9b07\r\n9b0b\r\n9b0f\r\n9b13\r\n9b17\r\n9b1b\r\n9b1f\r\nBREAK\r\n1\r\n258bc\r\n260300\r\nBREAK\r\n1\r\n258c2\r\nBREAK\r\n1\r\n4af\r\n9b66\r\n9b68\r\n9b70\r\n9b74\r\n9b7c\r\n9b80\r\n9b88\r\n9b8c\r\n9b94\r\n9b98\r\n9ba0\r\n9ba4\r\n9bac\r\n9bb0\r\n9bb8\r\n9bbc\r\n9bc4\r\n9bc8\r\n9bd0\r\n9bd4\r\n9bdc\r\n9be0\r\n9be8\r\n9bec\r\n9bf4\r\n9bf8\r\n9c00\r\n9c04\r\n9c0c\r\n9c10\r\n9c18\r\n9c1c\r\n9c24\r\n9c28\r\n9c30\r\n9c34\r\n9c3c\r\n9c40\r\n9c48\r\n9c4c\r\n9c54\r\n9c58\r\n9c60\r\n9c64\r\n9c6c\r\n9c70\r\n9c78\r\n9c7c\r\n9c84\r\n9c88\r\n9c90\r\n9c94\r\n9c9c\r\n9ca0\r\n9ca8\r\n9cac\r\n9cb4\r\n9cb8\r\n9cc0\r\n9cc4\r\n9ccc\r\n9cd0\r\n9cd8\r\nBREAK\r\n1\r\n258c8\r\nBREAK\r\n1\r\n4af\r\n9b66\r\n9b68\r\n9b70\r\n9b74\r\n9b7c\r\n9b80\r\n9b88\r\n9b8c\r\n9b94\r\n9b98\r\n9ba0\r\n9ba4\r\n9bac\r\n9bb0\r\n9bb8\r\n9bbc\r\n9bc4\r\n9bc8\r\n9bd0\r\n9bd4\r\n9bdc\r\n9be0\r\n9be8\r\n9bec\r\n9bf4\r\n9bf8\r\n9c00\r\n9c04\r\n9c0c\r\n9c10\r\n9c18\r\n9c1c\r\n9c24\r\n9c28\r\n9c30\r\n9c34\r\n9c3c\r\n9c40\r\n9c48\r\n9c4c\r\n9c54\r\n9c58\r\n9c60\r\n9c64\r\n9c6c\r\n9c70\r\n9c78\r\n9c7c\r\n9c84\r\n9c88\r\n9c90\r\n9c94\r\n9c9c\r\n9ca0\r\n9ca8\r\n9cac\r\n9cb4\r\n9cb8\r\n9cc0\r\n9cc4\r\n9ccc\r\n9cd0\r\n9cd8\r\nBREAK\r\n1\r\n258ce\r\nBREAK\r\n1\r\n258d4\r\nBREAK\r\n1\r\n4b2\r\n9cdc\r\n9cde\r\n9cdf\r\n9ce0\r\n9ce1\r\nBREAK\r\n1\r\n258da\r\nBREAK\r\n1\r\n4af\r\n9b66\r\n9b68\r\n9b70\r\n9b74\r\n9b7c\r\n9b80\r\n9b88\r\n9b8c\r\n9b94\r\n9b98\r\n9ba0\r\n9ba4\r\n9bac\r\n9bb0\r\n9bb8\r\n9bbc\r\n9bc4\r\n9bc8\r\n9bd0\r\n9bd4\r\n9bdc\r\n9be0\r\n9be8\r\n9bec\r\n9bf4\r\n9bf8\r\n9c00\r\n9c04\r\n9c0c\r\n9c10\r\n9c18\r\n9c1c\r\n9c24\r\n9c28\r\n9c30\r\n9c34\r\n9c3c\r\n9c40\r\n9c48\r\n9c4c\r\n9c54\r\n9c58\r\n9c60\r\n9c64\r\n9c6c\r\n9c70\r\n9c78\r\n9c7c\r\n9c84\r\n9c88\r\n9c90\r\n9c94\r\n9c9c\r\n9ca0\r\n9ca8\r\n9cac\r\n9cb4\r\n9cb8\r\n9cc0\r\n9cc4\r\n9ccc\r\n9cd0\r\n9cd8\r\nBREAK\r\n1\r\n258e0\r\nBREAK\r\n1\r\n4af\r\n9b66\r\n9b68\r\n9b70\r\n9b74\r\n9b7c\r\n9b80\r\n9b88\r\n9b8c\r\n9b94\r\n9b98\r\n9ba0\r\n9ba4\r\n9bac\r\n9bb0\r\n9bb8\r\n9bbc\r\n9bc4\r\n9bc8\r\n9bd0\r\n9bd4\r\n9bdc\r\n9be0\r\n9be8\r\n9bec\r\n9bf4\r\n9bf8\r\n9c00\r\n9c04\r\n9c0c\r\n9c10\r\n9c18\r\n9c1c\r\n9c24\r\n9c28\r\n9c30\r\n9c34\r\n9c3c\r\n9c40\r\n9c48\r\n9c4c\r\n9c54\r\n9c58\r\n9c60\r\n9c64\r\n9c6c\r\n9c70\r\n9c78\r\n9c7c\r\n9c84\r\n9c88\r\n9c90\r\n9c94\r\n9c9c\r\n9ca0\r\n9ca8\r\n9cac\r\n9cb4\r\n9cb8\r\n9cc0\r\n9cc4\r\n9ccc\r\n9cd0\r\n9cd8\r\nBREAK\r\n1\r\n258e6\r\nBREAK\r\n1\r\n258ec\r\nBREAK\r\n1\r\n4b2\r\n9cdc\r\n9cde\r\n9cdf\r\n9ce0\r\n9ce1\r\nBREAK\r\n1\r\n258f2\r\nBREAK\r\n1\r\n4af\r\n9b66\r\n9b68\r\n9b70\r\n9b74\r\n9b7c\r\n9b80\r\n9b88\r\n9b8c\r\n9b94\r\n9b98\r\n9ba0\r\n9ba4\r\n9bac\r\n9bb0\r\n9bb8\r\n9bbc\r\n9bc4\r\n9bc8\r\n9bd0\r\n9bd4\r\n9bdc\r\n9be0\r\n9be8\r\n9bec\r\n9bf4\r\n9bf8\r\n9c00\r\n9c04\r\n9c0c\r\n9c10\r\n9c18\r\n9c1c\r\n9c24\r\n9c28\r\n9c30\r\n9c34\r\n9c3c\r\n9c40\r\n9c48\r\n9c4c\r\n9c54\r\n9c58\r\n9c60\r\n9c64\r\n9c6c\r\n9c70\r\n9c78\r\n9c7c\r\n9c84\r\n9c88\r\n9c90\r\n9c94\r\n9c9c\r\n9ca0\r\n9ca8\r\n9cac\r\n9cb4\r\n9cb8\r\n9cc0\r\n9cc4\r\n9ccc\r\n9cd0\r\n9cd8\r\nBREAK\r\n1\r\n258f8\r\nBREAK\r\n1\r\n4af\r\n9b66\r\n9b68\r\n9b70\r\n9b74\r\n9b7c\r\n9b80\r\n9b88\r\n9b8c\r\n9b94\r\n9b98\r\n9ba0\r\n9ba4\r\n9bac\r\n9bb0\r\n9bb8\r\n9bbc\r\n9bc4\r\n9bc8\r\n9bd0\r\n9bd4\r\n9bdc\r\n9be0\r\n9be8\r\n9bec\r\n9bf4\r\n9bf8\r\n9c00\r\n9c04\r\n9c0c\r\n9c10\r\n9c18\r\n9c1c\r\n9c24\r\n9c28\r\n9c30\r\n9c34\r\n9c3c\r\n9c40\r\n9c48\r\n9c4c\r\n9c54\r\n9c58\r\n9c60\r\n9c64\r\n9c6c\r\n9c70\r\n9c78\r\n9c7c\r\n9c84\r\n9c88\r\n9c90\r\n9c94\r\n9c9c\r\n9ca0\r\n9ca8\r\n9cac\r\n9cb4\r\n9cb8\r\n9cc0\r\n9cc4\r\n9ccc\r\n9cd0\r\n9cd8\r\nBREAK\r\n1\r\n258fe\r\nBREAK\r\n1\r\n25904\r\nBREAK\r\n1\r\n4b2\r\n9cdc\r\n9cde\r\n9cdf\r\n9ce0\r\n9ce1\r\nBREAK\r\n1\r\n2590a\r\nBREAK\r\n1\r\n25910\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25916\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n2591c\r\nBREAK\r\n1\r\n25922\r\nBREAK\r\n1\r\n25928\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n2592e\r\nBREAK\r\n1\r\n25934\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n2593a\r\nBREAK\r\n1\r\n25940\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25946\r\nBREAK\r\n1\r\n2594c\r\nBREAK\r\n1\r\n25952\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25958\r\nBREAK\r\n1\r\n2595e\r\nBREAK\r\n1\r\n25964\r\nBREAK\r\n1\r\n2596a\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25970\r\nBREAK\r\n1\r\n25976\r\nBREAK\r\n1\r\n2597c\r\nBREAK\r\n1\r\n25982\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25988\r\nBREAK\r\n1\r\n2598e\r\nBREAK\r\n1\r\n25994\r\nBREAK\r\n1\r\n2599a\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n259a0\r\nBREAK\r\n1\r\n259a6\r\nBREAK\r\n1\r\n259ac\r\nBREAK\r\n1\r\n259b2\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n259b8\r\nBREAK\r\n1\r\n259be\r\nBREAK\r\n1\r\n259c4\r\nBREAK\r\n1\r\n259ca\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n259d0\r\nBREAK\r\n1\r\n259d6\r\nBREAK\r\n1\r\n259dc\r\nBREAK\r\n1\r\n259e2\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n259e8\r\nBREAK\r\n1\r\n259ee\r\nBREAK\r\n1\r\n259f4\r\nBREAK\r\n1\r\n259fa\r\nBREAK\r\n1\r\n25a00\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25a06\r\nBREAK\r\n1\r\n25a0c\r\nBREAK\r\n1\r\n25a12\r\nBREAK\r\n1\r\n25a18\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25a1e\r\nBREAK\r\n1\r\n25a24\r\nBREAK\r\n1\r\n25a2a\r\nBREAK\r\n1\r\n25a30\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25a36\r\nBREAK\r\n1\r\n25a3c\r\nBREAK\r\n1\r\n25a42\r\nBREAK\r\n1\r\n25a48\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25a4e\r\nBREAK\r\n1\r\n25a54\r\nBREAK\r\n1\r\n25a5a\r\nBREAK\r\n1\r\n25a60\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25a66\r\nBREAK\r\n1\r\n25a6c\r\nBREAK\r\n1\r\n25a72\r\nBREAK\r\n1\r\n25a78\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25a7e\r\nBREAK\r\n1\r\n25a84\r\nBREAK\r\n1\r\n25a8a\r\nBREAK\r\n1\r\n25a90\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25a96\r\nBREAK\r\n1\r\n25a9c\r\nBREAK\r\n1\r\n25aa2\r\nBREAK\r\n1\r\n25aa8\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25aae\r\nBREAK\r\n1\r\n25ab4\r\nBREAK\r\n1\r\n25aba\r\nBREAK\r\n1\r\n25ac0\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25ac6\r\nBREAK\r\n1\r\n25acc\r\nBREAK\r\n1\r\n25ad2\r\nBREAK\r\n1\r\n25ad8\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25ade\r\nBREAK\r\n1\r\n25ae4\r\nBREAK\r\n1\r\n25aea\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25af0\r\nBREAK\r\n1\r\n25af6\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25afc\r\nBREAK\r\n1\r\n25b02\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25b08\r\nBREAK\r\n1\r\n25b0e\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25b14\r\nBREAK\r\n1\r\n25b1a\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25b20\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25b26\r\nBREAK\r\n1\r\n25b2c\r\nBREAK\r\n1\r\n25b32\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25b38\r\nBREAK\r\n1\r\n25b3e\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25b44\r\nBREAK\r\n1\r\n25b4a\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25b50\r\nBREAK\r\n1\r\n25b56\r\nBREAK\r\n1\r\n25b5c\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25b62\r\nBREAK\r\n1\r\n25b68\r\nBREAK\r\n1\r\n25b6e\r\nBREAK\r\n1\r\n25b74\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25b7a\r\nBREAK\r\n1\r\n25b80\r\nBREAK\r\n1\r\n25b86\r\nBREAK\r\n1\r\n25b8c\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25b92\r\nBREAK\r\n1\r\n25b98\r\nBREAK\r\n1\r\n25b9e\r\nBREAK\r\n1\r\n25ba4\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25baa\r\nBREAK\r\n1\r\n25bb0\r\nBREAK\r\n1\r\n25bb6\r\nBREAK\r\n1\r\n25bbc\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25bc2\r\nBREAK\r\n1\r\n25bc8\r\nBREAK\r\n1\r\n25bce\r\nBREAK\r\n1\r\n25bd4\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25bda\r\nBREAK\r\n1\r\n25be0\r\nBREAK\r\n1\r\n25be6\r\nBREAK\r\n1\r\n25bec\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25bf2\r\nBREAK\r\n1\r\n25bf8\r\nBREAK\r\n1\r\n25bfe\r\nBREAK\r\n1\r\n25c04\r\nBREAK\r\n1\r\n25c0a\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25c10\r\nBREAK\r\n1\r\n25c16\r\nBREAK\r\n1\r\n25c1c\r\nBREAK\r\n1\r\n25c22\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25c28\r\nBREAK\r\n1\r\n25c2e\r\nBREAK\r\n1\r\n25c34\r\nBREAK\r\n1\r\n25c3a\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25c40\r\nBREAK\r\n1\r\n25c46\r\nBREAK\r\n1\r\n25c4c\r\nBREAK\r\n1\r\n25c52\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25c58\r\nBREAK\r\n1\r\n25c5e\r\nBREAK\r\n1\r\n25c64\r\nBREAK\r\n1\r\n25c6a\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25c70\r\nBREAK\r\n1\r\n25c76\r\nBREAK\r\n1\r\n25c7c\r\nBREAK\r\n1\r\n25c82\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25c88\r\nBREAK\r\n1\r\n25c8e\r\nBREAK\r\n1\r\n25c94\r\nBREAK\r\n1\r\n25c9a\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25ca0\r\nBREAK\r\n1\r\n25ca6\r\nBREAK\r\n1\r\n25cac\r\nBREAK\r\n1\r\n25cb2\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25cb8\r\nBREAK\r\n1\r\n25cbe\r\nBREAK\r\n1\r\n25cc4\r\nBREAK\r\n1\r\n25cca\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25cd0\r\nBREAK\r\n1\r\n25cd6\r\nBREAK\r\n1\r\n25cdc\r\nBREAK\r\n1\r\n25ce2\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25ce8\r\nBREAK\r\n1\r\n25cee\r\nBREAK\r\n1\r\n25cf4\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25cfa\r\nBREAK\r\n1\r\n25d00\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25d06\r\nBREAK\r\n1\r\n25d0c\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25d12\r\nBREAK\r\n1\r\n25d18\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25d1e\r\nBREAK\r\n1\r\n25d24\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25d2a\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25d30\r\nBREAK\r\n1\r\n25d36\r\nBREAK\r\n1\r\n25d3c\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25d42\r\nBREAK\r\n1\r\n25d48\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25d4e\r\nBREAK\r\n1\r\n25d54\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25d5a\r\nBREAK\r\n1\r\n25d60\r\nBREAK\r\n1\r\n25d66\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25d6c\r\nBREAK\r\n1\r\n25d72\r\nBREAK\r\n1\r\n25d78\r\nBREAK\r\n1\r\n25d7e\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25d84\r\nBREAK\r\n1\r\n25d8a\r\nBREAK\r\n1\r\n25d90\r\nBREAK\r\n1\r\n25d96\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25d9c\r\nBREAK\r\n1\r\n25da2\r\nBREAK\r\n1\r\n25da8\r\nBREAK\r\n1\r\n25dae\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25db4\r\nBREAK\r\n1\r\n25dba\r\nBREAK\r\n1\r\n25dc0\r\nBREAK\r\n1\r\n25dc6\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25dcc\r\nBREAK\r\n1\r\n25dd2\r\nBREAK\r\n1\r\n25dd8\r\nBREAK\r\n1\r\n25dde\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25de4\r\nBREAK\r\n1\r\n25dea\r\nBREAK\r\n1\r\n25df0\r\nBREAK\r\n1\r\n25df6\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25dfc\r\nBREAK\r\n1\r\n25e02\r\nBREAK\r\n1\r\n25e08\r\nBREAK\r\n1\r\n25e0e\r\nBREAK\r\n1\r\n25e14\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25e1a\r\nBREAK\r\n1\r\n25e20\r\nBREAK\r\n1\r\n25e26\r\nBREAK\r\n1\r\n25e2c\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25e32\r\nBREAK\r\n1\r\n25e38\r\nBREAK\r\n1\r\n25e3e\r\nBREAK\r\n1\r\n25e44\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25e4a\r\nBREAK\r\n1\r\n25e50\r\nBREAK\r\n1\r\n25e56\r\nBREAK\r\n1\r\n25e5c\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25e62\r\nBREAK\r\n1\r\n25e68\r\nBREAK\r\n1\r\n25e6e\r\nBREAK\r\n1\r\n25e74\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25e7a\r\nBREAK\r\n1\r\n25e80\r\nBREAK\r\n1\r\n25e86\r\nBREAK\r\n1\r\n25e8c\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25e92\r\nBREAK\r\n1\r\n25e98\r\nBREAK\r\n1\r\n25e9e\r\nBREAK\r\n1\r\n25ea4\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25eaa\r\nBREAK\r\n1\r\n25eb0\r\nBREAK\r\n1\r\n25eb6\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25ebc\r\nBREAK\r\n1\r\n25ec2\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25ec8\r\nBREAK\r\n1\r\n25ece\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25ed4\r\nBREAK\r\n1\r\n25eda\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25ee0\r\nBREAK\r\n1\r\n25ee6\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n25eec\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n25ef2\r\nBREAK\r\n1\r\n25ef8\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n25efe\r\nBREAK\r\n1\r\n25f04\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n25f0a\r\nBREAK\r\n1\r\n25f10\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n25f16\r\nBREAK\r\n1\r\n25f1c\r\nBREAK\r\n1\r\n25f22\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n25f28\r\nBREAK\r\n1\r\n25f2e\r\nBREAK\r\n1\r\n25f34\r\nBREAK\r\n1\r\n25f3a\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n25f40\r\nBREAK\r\n1\r\n25f46\r\nBREAK\r\n1\r\n25f4c\r\nBREAK\r\n1\r\n25f52\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n25f58\r\nBREAK\r\n1\r\n25f5e\r\nBREAK\r\n1\r\n25f64\r\nBREAK\r\n1\r\n25f6a\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n25f70\r\nBREAK\r\n1\r\n25f76\r\nBREAK\r\n1\r\n25f7c\r\nBREAK\r\n1\r\n25f82\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n25f88\r\nBREAK\r\n1\r\n25f8e\r\nBREAK\r\n1\r\n25f94\r\nBREAK\r\n1\r\n25f9a\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa67\r\naa6f\r\naa73\r\naa7b\r\naa7f\r\naa87\r\naa8b\r\naa93\r\naa97\r\naa9f\r\naaa3\r\naaab\r\naaaf\r\naab7\r\naabb\r\naac3\r\naac7\r\naacf\r\naad3\r\naadb\r\naadf\r\naae7\r\naaeb\r\naaf3\r\naaf7\r\naaff\r\nab03\r\n0\r\nab0b\r\nab0f\r\nab17\r\nab1b\r\nab23\r\nab27\r\nab2f\r\nab33\r\nab3b\r\nab3f\r\nab47\r\nab4b\r\nab53\r\nab57\r\nab5f\r\nab63\r\nab6b\r\nab6f\r\nab77\r\nab7b\r\nab83\r\nab87\r\nab8f\r\nab93\r\nab9b\r\nab9f\r\naba7\r\nabab\r\nabb3\r\nabb7\r\nabbf\r\nabc3\r\nabcb\r\nabcf\r\nabd7\r\nBREAK\r\n1\r\n25fa0\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n25fa6\r\nBREAK\r\n1\r\n25fac\r\nBREAK\r\n1\r\n25fb2\r\nBREAK\r\n1\r\n25fb8\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa68\r\naa70\r\naa74\r\naa7c\r\naa80\r\naa88\r\naa8c\r\naa94\r\naa98\r\naaa0\r\naaa4\r\naaac\r\naab0\r\naab8\r\naabc\r\naac4\r\naac8\r\naad0\r\naad4\r\naadc\r\naae0\r\naae8\r\naaec\r\naaf4\r\naaf8\r\nab00\r\nab04\r\nab0c\r\nab10\r\nab18\r\nab1c\r\nab24\r\nab28\r\nab30\r\nab34\r\nab3c\r\nab40\r\nab48\r\nab4c\r\nab54\r\nab58\r\nab60\r\nab64\r\nab6c\r\nab70\r\nab78\r\nab7c\r\nab84\r\nab88\r\nab90\r\nab94\r\nab9c\r\naba0\r\naba8\r\nabac\r\nabb4\r\nabb8\r\nabc0\r\nabc4\r\nabcc\r\nabd0\r\nabd8\r\nBREAK\r\n1\r\n25fbe\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n25fc4\r\nBREAK\r\n1\r\n25fca\r\nBREAK\r\n1\r\n25fd0\r\nBREAK\r\n1\r\n25fd6\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa69\r\naa71\r\naa75\r\naa7d\r\naa81\r\naa89\r\naa8d\r\naa95\r\naa99\r\naaa1\r\naaa5\r\naaad\r\naab1\r\naab9\r\naabd\r\naac5\r\naac9\r\naad1\r\naad5\r\naadd\r\naae1\r\naae9\r\naaed\r\naaf5\r\naaf9\r\nab01\r\nab05\r\nab0d\r\nab11\r\nab19\r\nab1d\r\nab25\r\nab29\r\nab31\r\nab35\r\nab3d\r\nab41\r\nab49\r\nab4d\r\nab55\r\nab59\r\nab61\r\nab65\r\nab6d\r\nab71\r\nab79\r\nab7d\r\nab85\r\nab89\r\nab91\r\nab95\r\nab9d\r\naba1\r\naba9\r\nabad\r\nabb5\r\nabb9\r\nabc1\r\nabc5\r\nabcd\r\nabd1\r\nabd9\r\nBREAK\r\n1\r\n25fdc\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n25fe2\r\nBREAK\r\n1\r\n25fe8\r\nBREAK\r\n1\r\n25fee\r\nBREAK\r\n1\r\n25ff4\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa6a\r\naa72\r\naa76\r\naa7e\r\naa82\r\naa8a\r\naa8e\r\naa96\r\naa9a\r\naaa2\r\naaa6\r\naaae\r\naab2\r\naaba\r\naabe\r\naac6\r\naaca\r\naad2\r\naad6\r\naade\r\naae2\r\naaea\r\naaee\r\naaf6\r\naafa\r\nab02\r\nab06\r\nab0e\r\nab12\r\nab1a\r\nab1e\r\nab26\r\nab2a\r\nab32\r\nab36\r\nab3e\r\nab42\r\nab4a\r\nab4e\r\nab56\r\nab5a\r\nab62\r\nab66\r\nab6e\r\nab72\r\nab7a\r\nab7e\r\nab86\r\nab8a\r\nab92\r\nab96\r\nab9e\r\naba2\r\nabaa\r\nabae\r\nabb6\r\nabba\r\nabc2\r\nabc6\r\nabce\r\nabd2\r\nabda\r\nBREAK\r\n1\r\n25ffa\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n26000\r\nBREAK\r\n1\r\n26006\r\nBREAK\r\n1\r\n2600c\r\nBREAK\r\n1\r\n26012\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa6b\r\naa73\r\naa77\r\naa7f\r\naa83\r\naa8b\r\naa8f\r\naa97\r\naa9b\r\naaa3\r\naaa7\r\naaaf\r\naab3\r\naabb\r\naabf\r\naac7\r\naacb\r\naad3\r\naad7\r\naadf\r\naae3\r\naaeb\r\naaef\r\naaf7\r\naafb\r\nab03\r\n0\r\nab07\r\nab0f\r\nab13\r\nab1b\r\nab1f\r\nab27\r\nab2b\r\nab33\r\nab37\r\nab3f\r\nab43\r\nab4b\r\nab4f\r\nab57\r\nab5b\r\nab63\r\nab67\r\nab6f\r\nab73\r\nab7b\r\nab7f\r\nab87\r\nab8b\r\nab93\r\nab97\r\nab9f\r\naba3\r\nabab\r\nabaf\r\nabb7\r\nabbb\r\nabc3\r\nabc7\r\nabcf\r\nabd3\r\nabdb\r\nBREAK\r\n1\r\n26018\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n2601e\r\nBREAK\r\n1\r\n26024\r\nBREAK\r\n1\r\n2602a\r\nBREAK\r\n1\r\n26030\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa6c\r\naa74\r\naa78\r\naa80\r\naa84\r\naa8c\r\naa90\r\naa98\r\naa9c\r\naaa4\r\naaa8\r\naab0\r\naab4\r\naabc\r\naac0\r\naac8\r\naacc\r\naad4\r\naad8\r\naae0\r\naae4\r\naaec\r\naaf0\r\naaf8\r\naafc\r\nab04\r\nab08\r\nab10\r\nab14\r\nab1c\r\nab20\r\nab28\r\nab2c\r\nab34\r\nab38\r\nab40\r\nab44\r\nab4c\r\nab50\r\nab58\r\nab5c\r\nab64\r\nab68\r\nab70\r\nab74\r\nab7c\r\nab80\r\nab88\r\nab8c\r\nab94\r\nab98\r\naba0\r\naba4\r\nabac\r\nabb0\r\nabb8\r\nabbc\r\nabc4\r\nabc8\r\nabd0\r\nabd4\r\nabdc\r\nBREAK\r\n1\r\n26036\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n2603c\r\nBREAK\r\n1\r\n26042\r\nBREAK\r\n1\r\n26048\r\nBREAK\r\n1\r\n2604e\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa6d\r\naa75\r\naa79\r\naa81\r\naa85\r\naa8d\r\naa91\r\naa99\r\naa9d\r\naaa5\r\naaa9\r\naab1\r\naab5\r\naabd\r\naac1\r\naac9\r\naacd\r\naad5\r\naad9\r\naae1\r\naae5\r\naaed\r\naaf1\r\naaf9\r\naafd\r\nab05\r\nab09\r\nab11\r\nab15\r\nab1d\r\nab21\r\nab29\r\nab2d\r\nab35\r\nab39\r\nab41\r\nab45\r\nab4d\r\nab51\r\nab59\r\nab5d\r\nab65\r\nab69\r\nab71\r\nab75\r\nab7d\r\nab81\r\nab89\r\nab8d\r\nab95\r\nab99\r\naba1\r\naba5\r\nabad\r\nabb1\r\nabb9\r\nabbd\r\nabc5\r\nabc9\r\nabd1\r\nabd5\r\nabdd\r\nBREAK\r\n1\r\n26054\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n2605a\r\nBREAK\r\n1\r\n26060\r\nBREAK\r\n1\r\n26066\r\nBREAK\r\n1\r\n2606c\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa6e\r\naa76\r\naa7a\r\naa82\r\naa86\r\naa8e\r\naa92\r\naa9a\r\naa9e\r\naaa6\r\naaaa\r\naab2\r\naab6\r\naabe\r\naac2\r\naaca\r\naace\r\naad6\r\naada\r\naae2\r\naae6\r\naaee\r\naaf2\r\naafa\r\naafe\r\nab06\r\nab0a\r\nab12\r\nab16\r\nab1e\r\nab22\r\nab2a\r\nab2e\r\nab36\r\nab3a\r\nab42\r\nab46\r\nab4e\r\nab52\r\nab5a\r\nab5e\r\nab66\r\nab6a\r\nab72\r\nab76\r\nab7e\r\nab82\r\nab8a\r\nab8e\r\nab96\r\nab9a\r\naba2\r\naba6\r\nabae\r\nabb2\r\nabba\r\nabbe\r\nabc6\r\nabca\r\nabd2\r\nabd6\r\nabde\r\nBREAK\r\n1\r\n26072\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n26078\r\nBREAK\r\n1\r\n2607e\r\nBREAK\r\n1\r\n26084\r\nBREAK\r\n1\r\n2608a\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa6f\r\naa77\r\naa7b\r\naa83\r\naa87\r\naa8f\r\naa93\r\naa9b\r\naa9f\r\naaa7\r\naaab\r\naab3\r\naab7\r\naabf\r\naac3\r\naacb\r\naacf\r\naad7\r\naadb\r\naae3\r\naae7\r\naaef\r\naaf3\r\naafb\r\naaff\r\nab07\r\nab0b\r\nab13\r\nab17\r\nab1f\r\nab23\r\nab2b\r\nab2f\r\nab37\r\nab3b\r\nab43\r\nab47\r\nab4f\r\nab53\r\nab5b\r\nab5f\r\nab67\r\nab6b\r\nab73\r\nab77\r\nab7f\r\nab83\r\nab8b\r\nab8f\r\nab97\r\nab9b\r\naba3\r\naba7\r\nabaf\r\nabb3\r\nabbb\r\nabbf\r\nabc7\r\nabcb\r\nabd3\r\nabd7\r\nabdf\r\nBREAK\r\n1\r\n26090\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n26096\r\nBREAK\r\n1\r\n2609c\r\nBREAK\r\n1\r\n260a2\r\nBREAK\r\n1\r\n260a8\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa70\r\naa78\r\naa7c\r\naa84\r\naa88\r\naa90\r\naa94\r\naa9c\r\naaa0\r\naaa8\r\naaac\r\naab4\r\naab8\r\naac0\r\naac4\r\naacc\r\naad0\r\naad8\r\naadc\r\naae4\r\naae8\r\naaf0\r\naaf4\r\naafc\r\nab00\r\nab08\r\nab0c\r\nab14\r\nab18\r\nab20\r\nab24\r\nab2c\r\nab30\r\nab38\r\nab3c\r\nab44\r\nab48\r\nab50\r\nab54\r\nab5c\r\nab60\r\nab68\r\nab6c\r\nab74\r\nab78\r\nab80\r\nab84\r\nab8c\r\nab90\r\nab98\r\nab9c\r\naba4\r\naba8\r\nabb0\r\nabb4\r\nabbc\r\nabc0\r\nabc8\r\nabcc\r\nabd4\r\nabd8\r\nabe0\r\nBREAK\r\n1\r\n260ae\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n260b4\r\nBREAK\r\n1\r\n260ba\r\nBREAK\r\n1\r\n260c0\r\nBREAK\r\n1\r\n260c6\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa71\r\naa79\r\naa7d\r\naa85\r\naa89\r\naa91\r\naa95\r\naa9d\r\naaa1\r\naaa9\r\naaad\r\naab5\r\naab9\r\naac1\r\naac5\r\naacd\r\naad1\r\naad9\r\naadd\r\naae5\r\naae9\r\naaf1\r\naaf5\r\naafd\r\nab01\r\nab09\r\nab0d\r\nab15\r\nab19\r\nab21\r\nab25\r\nab2d\r\nab31\r\nab39\r\nab3d\r\nab45\r\nab49\r\nab51\r\nab55\r\nab5d\r\nab61\r\nab69\r\nab6d\r\nab75\r\nab79\r\nab81\r\nab85\r\nab8d\r\nab91\r\nab99\r\nab9d\r\naba5\r\naba9\r\nabb1\r\nabb5\r\nabbd\r\nabc1\r\nabc9\r\nabcd\r\nabd5\r\nabd9\r\nabe1\r\nBREAK\r\n1\r\n260cc\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n260d2\r\nBREAK\r\n1\r\n260d8\r\nBREAK\r\n1\r\n260de\r\nBREAK\r\n1\r\n260e4\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n260ea\r\nBREAK\r\n1\r\n260f0\r\nBREAK\r\n1\r\n260f6\r\nBREAK\r\n1\r\n260fc\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n26102\r\nBREAK\r\n1\r\n26108\r\nBREAK\r\n1\r\n2610e\r\nBREAK\r\n1\r\n26114\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n2611a\r\nBREAK\r\n1\r\n26120\r\nBREAK\r\n1\r\n26126\r\nBREAK\r\n1\r\n2612c\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n26132\r\nBREAK\r\n1\r\n26138\r\nBREAK\r\n1\r\n2613e\r\nBREAK\r\n1\r\n26144\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n2614a\r\nBREAK\r\n1\r\n26150\r\nBREAK\r\n1\r\n26156\r\nBREAK\r\n1\r\n2615c\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n26162\r\nBREAK\r\n1\r\n26168\r\nBREAK\r\n1\r\n2616e\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n26174\r\nBREAK\r\n1\r\n2617a\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n26180\r\nBREAK\r\n1\r\n26186\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n2618c\r\nBREAK\r\n1\r\n26192\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n26198\r\nBREAK\r\n1\r\n2619e\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n261a4\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n261aa\r\nBREAK\r\n1\r\n261b0\r\nBREAK\r\n1\r\n261b6\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n261bc\r\nBREAK\r\n1\r\n261c2\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n261c8\r\nBREAK\r\n1\r\n261ce\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n261d4\r\nBREAK\r\n1\r\n261da\r\nBREAK\r\n1\r\n261e0\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n261e6\r\nBREAK\r\n1\r\n261ec\r\nBREAK\r\n1\r\n261f2\r\nBREAK\r\n1\r\n261f8\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n261fe\r\nBREAK\r\n1\r\n26204\r\nBREAK\r\n1\r\n2620a\r\nBREAK\r\n1\r\n26210\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n26216\r\nBREAK\r\n1\r\n2621c\r\nBREAK\r\n1\r\n26222\r\nBREAK\r\n1\r\n26228\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n2622e\r\nBREAK\r\n1\r\n26234\r\nBREAK\r\n1\r\n2623a\r\nBREAK\r\n1\r\n26240\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n26246\r\nBREAK\r\n1\r\n2624c\r\nBREAK\r\n1\r\n26252\r\nBREAK\r\n1\r\n26258\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n2625e\r\nBREAK\r\n1\r\n26264\r\nBREAK\r\n1\r\n2626a\r\nBREAK\r\n1\r\n26270\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n26276\r\nBREAK\r\n1\r\n2627c\r\nBREAK\r\n1\r\n26282\r\nBREAK\r\n1\r\n26288\r\nBREAK\r\n1\r\n2628e\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n26294\r\nBREAK\r\n1\r\n2629a\r\nBREAK\r\n1\r\n262a0\r\nBREAK\r\n1\r\n262a6\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n262ac\r\nBREAK\r\n1\r\n262b2\r\nBREAK\r\n1\r\n262b8\r\nBREAK\r\n1\r\n262be\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n262c4\r\nBREAK\r\n1\r\n262ca\r\nBREAK\r\n1\r\n262d0\r\nBREAK\r\n1\r\n262d6\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n262dc\r\nBREAK\r\n1\r\n262e2\r\nBREAK\r\n1\r\n262e8\r\nBREAK\r\n1\r\n262ee\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n262f4\r\nBREAK\r\n1\r\n262fa\r\nBREAK\r\n1\r\n26300\r\nBREAK\r\n1\r\n26306\r\nBREAK\r\n1\r\n2630c\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n26312\r\nBREAK\r\n1\r\n26318\r\nBREAK\r\n1\r\n2631e\r\nBREAK\r\n1\r\n26324\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n2632a\r\nBREAK\r\n1\r\n26330\r\nBREAK\r\n1\r\n26336\r\nBREAK\r\n1\r\n2633c\r\nBREAK\r\n1\r\n26342\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n26348\r\nBREAK\r\n1\r\n2634e\r\nBREAK\r\n1\r\n26354\r\nBREAK\r\n1\r\n2635a\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n26360\r\nBREAK\r\n1\r\n26366\r\nBREAK\r\n1\r\n2636c\r\nBREAK\r\n1\r\n26372\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n26378\r\nBREAK\r\n1\r\n2637e\r\nBREAK\r\n1\r\n26384\r\nBREAK\r\n1\r\n2638a\r\nBREAK\r\n1\r\n26390\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n26396\r\nBREAK\r\n1\r\n2639c\r\nBREAK\r\n1\r\n263a2\r\nBREAK\r\n1\r\n263a8\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n263ae\r\nBREAK\r\n1\r\n263b4\r\nBREAK\r\n1\r\n263ba\r\nBREAK\r\n1\r\n263c0\r\nBREAK\r\n1\r\n263c6\r\nBREAK\r\n1\r\n263cc\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n263d2\r\nBREAK\r\n1\r\n4a9\r\n9b23\r\n9b25\r\n9b29\r\n9b2d\r\n9b31\r\n9b35\r\n9b39\r\n9b3d\r\nBREAK\r\n1\r\n263d8\r\n200300\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n263de\r\nBREAK\r\n1\r\n4a9\r\n9b23\r\n9b25\r\n9b29\r\n9b2d\r\n9b31\r\n9b35\r\n9b39\r\n9b3d\r\nBREAK\r\n1\r\n263e4\r\n100300\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n263ea\r\nBREAK\r\n1\r\n4a9\r\n9b23\r\n9b25\r\n9b29\r\n9b2d\r\n9b31\r\n9b35\r\n9b39\r\n9b3d\r\nBREAK\r\n1\r\n263f0\r\n100300\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n263f6\r\nBREAK\r\n1\r\n4a9\r\n9b23\r\n9b25\r\n9b29\r\n9b2d\r\n9b31\r\n9b35\r\n9b39\r\n9b3d\r\nBREAK\r\n1\r\n263fc\r\n100300\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n26402\r\nBREAK\r\n1\r\n4ac\r\n9b41\r\n9b43\r\n3009b\r\n9b48\r\n9b4d\r\n9b52\r\n9b57\r\n9b5c\r\n9b61\r\nBREAK\r\n1\r\n26408\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n2640e\r\nBREAK\r\n1\r\n4ac\r\n9b41\r\n9b43\r\n3009b\r\n9b48\r\n9b4d\r\n9b52\r\n9b57\r\n9b5c\r\n9b61\r\nBREAK\r\n1\r\n26414\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n2641a\r\nBREAK\r\n1\r\n4ac\r\n9b41\r\n9b43\r\n3009b\r\n9b48\r\n9b4d\r\n9b52\r\n9b57\r\n9b5c\r\n9b61\r\nBREAK\r\n1\r\n26420\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n26426\r\nBREAK\r\n1\r\n4ac\r\n9b41\r\n9b44\r\n3009b\r\n9b49\r\n9b4e\r\n9b53\r\n9b58\r\n9b5d\r\n9b62\r\nBREAK\r\n1\r\n2642c\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n26432\r\nBREAK\r\n1\r\n4ac\r\n9b41\r\n9b45\r\n3009b\r\n9b4a\r\n9b4f\r\n9b54\r\n9b59\r\n9b5e\r\n9b63\r\nBREAK\r\n1\r\n26438\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n2643e\r\nBREAK\r\n1\r\n4ac\r\n9b41\r\n9b47\r\n3009b\r\n9b4c\r\n9b51\r\n9b56\r\n9b5b\r\n9b60\r\n9b65\r\nBREAK\r\n1\r\n26444\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n2644a\r\nBREAK\r\n1\r\n26450\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n26456\r\nBREAK\r\n1\r\n2645c\r\nBREAK\r\n1\r\n26462\r\nBREAK\r\n1\r\n26468\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n2646e\r\nBREAK\r\n1\r\n26474\r\nBREAK\r\n1\r\n50f\r\nb0d0\r\nb0d2\r\nb0d6\r\nb0da\r\nb0de\r\nb0e2\r\nb0e6\r\nb0ea\r\nb0ee\r\nb0f2\r\nb0f6\r\nb0fa\r\nb0fe\r\nb102\r\nb106\r\nBREAK\r\n1\r\n2647a\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n26480\r\nBREAK\r\n1\r\n26486\r\nBREAK\r\n1\r\n2648c\r\nBREAK\r\n1\r\n26492\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n26498\r\nBREAK\r\n1\r\n2649e\r\nBREAK\r\n1\r\n512\r\nb10a\r\nb10c\r\nb110\r\nb114\r\nb118\r\nb11c\r\nb120\r\nb124\r\nb128\r\nb12c\r\nb130\r\nb134\r\nb138\r\nb13c\r\nb140\r\nBREAK\r\n1\r\n264a4\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n264aa\r\nBREAK\r\n1\r\n264b0\r\nBREAK\r\n1\r\n264b6\r\nBREAK\r\n1\r\n264bc\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n264c2\r\nBREAK\r\n1\r\n264c8\r\nBREAK\r\n1\r\n50f\r\nb0d0\r\nb0d2\r\nb0d6\r\nb0da\r\nb0de\r\nb0e2\r\nb0e6\r\nb0ea\r\nb0ee\r\nb0f2\r\nb0f6\r\nb0fa\r\nb0fe\r\nb102\r\nb106\r\nBREAK\r\n1\r\n264ce\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n264d4\r\nBREAK\r\n1\r\n264da\r\nBREAK\r\n1\r\n264e0\r\nBREAK\r\n1\r\n264e6\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n264ec\r\nBREAK\r\n1\r\n264f2\r\nBREAK\r\n1\r\n512\r\nb10a\r\nb10c\r\nb110\r\nb114\r\nb118\r\nb11c\r\nb120\r\nb124\r\nb128\r\nb12c\r\nb130\r\nb134\r\nb138\r\nb13c\r\nb140\r\nBREAK\r\n1\r\n264f8\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n264fe\r\nBREAK\r\n1\r\n26504\r\nBREAK\r\n1\r\n2650a\r\nBREAK\r\n1\r\n26510\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n26516\r\nBREAK\r\n1\r\n2651c\r\nBREAK\r\n1\r\n500\r\nafae\r\nafb0\r\nafb4\r\nafb8\r\nafbc\r\nafc0\r\nafc4\r\nafc8\r\nafcc\r\nafd0\r\nafd4\r\nafd8\r\nafdc\r\nafe0\r\nafe4\r\nBREAK\r\n1\r\n26522\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n26528\r\nBREAK\r\n1\r\n2652e\r\nBREAK\r\n1\r\n26534\r\nBREAK\r\n1\r\n2653a\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n26540\r\nBREAK\r\n1\r\n26546\r\nBREAK\r\n1\r\n503\r\n0\r\nafe8\r\nafea\r\nafee\r\naff2\r\naff6\r\naffa\r\naffe\r\nb002\r\nb006\r\nb00a\r\nb00e\r\nb012\r\nb016\r\nb01a\r\nb01e\r\nBREAK\r\n1\r\n2654c\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n26552\r\nBREAK\r\n1\r\n26558\r\nBREAK\r\n1\r\n2655e\r\nBREAK\r\n1\r\n26564\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n2656a\r\nBREAK\r\n1\r\n26570\r\nBREAK\r\n1\r\n506\r\nb022\r\nb024\r\nb028\r\nb02c\r\nb030\r\nb034\r\nb038\r\nb03c\r\nb040\r\nb044\r\nb048\r\nb04c\r\nb050\r\nb054\r\nb058\r\nBREAK\r\n1\r\n26576\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n2657c\r\nBREAK\r\n1\r\n26582\r\nBREAK\r\n1\r\n26588\r\nBREAK\r\n1\r\n2658e\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n26594\r\nBREAK\r\n1\r\n2659a\r\nBREAK\r\n1\r\n509\r\nb05c\r\nb05e\r\nb062\r\nb066\r\nb06a\r\nb06e\r\nb072\r\nb076\r\nb07a\r\nb07e\r\nb082\r\nb086\r\nb08a\r\nb08e\r\nb092\r\nBREAK\r\n1\r\n265a0\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n265a6\r\nBREAK\r\n1\r\n265ac\r\nBREAK\r\n1\r\n265b2\r\nBREAK\r\n1\r\n265b8\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n265be\r\nBREAK\r\n1\r\n265c4\r\nBREAK\r\n1\r\n50c\r\nb096\r\nb098\r\nb09c\r\nb0a0\r\nb0a4\r\nb0a8\r\nb0ac\r\nb0b0\r\nb0b4\r\nb0b8\r\nb0bc\r\nb0c0\r\nb0c4\r\nb0c8\r\nb0cc\r\nBREAK\r\n1\r\n265ca\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n265d0\r\nBREAK\r\n1\r\n265d6\r\nBREAK\r\n1\r\n265dc\r\nBREAK\r\n1\r\n265e2\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n265e8\r\nBREAK\r\n1\r\n265ee\r\nBREAK\r\n1\r\n4fa\r\naf3a\r\naf3c\r\naf40\r\naf44\r\naf48\r\naf4c\r\naf50\r\naf54\r\naf58\r\naf5c\r\naf60\r\naf64\r\naf68\r\naf6c\r\naf70\r\nBREAK\r\n1\r\n265f4\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n265fa\r\nBREAK\r\n1\r\n26600\r\nBREAK\r\n1\r\n26606\r\nBREAK\r\n1\r\n2660c\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n26612\r\nBREAK\r\n1\r\n26618\r\nBREAK\r\n1\r\n4fa\r\naf3a\r\naf3c\r\naf40\r\naf44\r\naf48\r\naf4c\r\naf50\r\naf54\r\naf58\r\naf5c\r\naf60\r\naf64\r\naf68\r\naf6c\r\naf70\r\nBREAK\r\n1\r\n2661e\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n26624\r\nBREAK\r\n1\r\n2662a\r\nBREAK\r\n1\r\n26630\r\nBREAK\r\n1\r\n26636\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n2663c\r\nBREAK\r\n1\r\n26642\r\nBREAK\r\n1\r\n4fd\r\naf74\r\naf76\r\naf7a\r\naf7e\r\naf82\r\naf86\r\naf8a\r\naf8e\r\naf92\r\naf96\r\naf9a\r\naf9e\r\nafa2\r\nafa6\r\nafaa\r\nBREAK\r\n1\r\n26648\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n2664e\r\nBREAK\r\n1\r\n26654\r\nBREAK\r\n1\r\n2665a\r\nBREAK\r\n1\r\n26660\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n26666\r\nBREAK\r\n1\r\n2666c\r\nBREAK\r\n1\r\n4fd\r\naf74\r\naf76\r\naf7a\r\naf7e\r\naf82\r\naf86\r\naf8a\r\naf8e\r\naf92\r\naf96\r\naf9a\r\naf9e\r\nafa2\r\nafa6\r\nafaa\r\nBREAK\r\n1\r\n26672\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\n26678\r\nBREAK\r\n1\r\n2667e\r\nBREAK\r\n1\r\n26684\r\nBREAK\r\n1\r\n386\r\n860000\r\n6e06\r\n6e08\r\n6e0a\r\n6e0c\r\n6e0e\r\n6e10\r\n6e12\r\n6e14\r\n6e16\r\n6e18\r\n6e1a\r\n6e1c\r\n6e1e\r\n6e20\r\n6e22\r\n6e24\r\n6e26\r\n6e28\r\n6e2a\r\n6e2c\r\n6e2e\r\n6e30\r\n6e32\r\n6e34\r\n6e36\r\n6e38\r\n6e3a\r\n6e3c\r\n6e3e\r\n6e40\r\n6e42\r\n6e44\r\nBREAK\r\n1\r\n2668a\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\n26690\r\nBREAK\r\n1\r\n26696\r\nBREAK\r\n1\r\n4b5\r\n9ce2\r\n9ce4\r\n9ce6\r\n9ce8\r\n9cea\r\n9cec\r\n9cee\r\n9cf0\r\n9cf2\r\n9cf4\r\n9cf6\r\n9cf8\r\n9cfa\r\n9cfc\r\n9cfe\r\n9d00\r\n9d02\r\n9d04\r\n9d06\r\n9d08\r\n9d0a\r\n9d0c\r\n9d0e\r\n9d10\r\n9d12\r\n9d14\r\n9d16\r\n9d18\r\n9d1a\r\n9d1c\r\n9d1e\r\n9d20\r\nBREAK\r\n1\r\n2669c\r\nBREAK\r\n1\r\n266a2\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\n" }, { "path": "figure/SignalPulls/signaldecode.py", "content": "f = open(\"clock.csv\")\r\nl = []\r\nt = 0\r\nt= f.readline()\r\nprint \"here\"\r\nprint t\r\nwhile(True):\r\n\ttry:\r\n\t\tt= f.readline()\r\n\t\tl.append(t.split(',')[3])\r\n\t\r\n\texcept:\r\n\t\tbreak\r\n\r\nfor i in range(0, len(l)):\r\n\t#print i\r\n\tif int(l[i], 16) == 3:\r\n\r\n\t\t#print \"read\",\r\n\t\ta = (int(l[i+1], 16) << 16 ) | (int(l[i+2], 16) << 8 ) | int(l[i+3], 16)\r\n\t\tif (a == 1):\r\n\t\t\tprint \"BREAK\"\r\n\t\tprint \"%x\" % a" }, { "path": "figure/SignalPulls/usatour.txt", "content": "here\r\nTime [s],Packet ID,MOSI,MISO\r\n\r\nBREAK\r\n1\r\n2a8\r\n2af2//load usa logo\r\n2af4\r\n2af8\r\n2afc\r\n2b00\r\n2b04\r\n2b08\r\n2b0c\r\n2b10\r\n2b14\r\n2b18\r\n2b1c\r\n2b20\r\n2b24\r\n2b28\r\n2b2c\r\n2b30\r\nBREAK\r\n1\r\n2cc\r\n2e06//guess usa name\r\n2e08\r\n2e10\r\n2e18\r\n2e20\r\n2e28\r\n2e30\r\n2e38\r\n2e40\r\n2e48\r\n2e50\r\n2e58\r\n2e60\r\nBREAK\r\n1\r\n927//single byte read (is this a code?)\r\nBREAK\r\n1\r\nd1// image 52 (tiny 2)\r\n24a1\r\n24a3\r\n24a8\r\n24ad\r\n24b2\r\n24b7\r\n24bc\r\n24c1\r\n24c6\r\n24cb\r\n24d0\r\n24d5\r\n24da\r\n24df\r\n24e4\r\n24e9\r\n24ee\r\n24f3\r\n24f8\r\n24fd\r\n2502\r\n2507\r\nBREAK\r\n1\r\nce\r\n2436//open chest\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\n162 //single byte, 01\r\n92e// 3 bytes 04 04 08\r\n95b // 3 bytes b2 4f 02 // pointer to below\r\nBREAK\r\n1\r\n24fc2 // 6 bytes\r\nBREAK\r\n1\r\nce\r\n2436//chest again\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\n24fc8//6 bytes\r\nBREAK\r\n1\r\n4b5\r\n9ce2 //map dot?\r\n9ce4\r\n9ce6\r\n9ce8\r\n9cea\r\n9cec\r\n9cee\r\n9cf0\r\n9cf2\r\n9cf4\r\n9cf6\r\n9cf8\r\n9cfa\r\n9cfc\r\n9cfe\r\n9d00\r\n9d02\r\n9d04\r\n9d06\r\n9d08\r\n9d0a\r\n9d0c\r\n9d0e\r\n9d10\r\n9d12\r\n9d14\r\n9d16\r\n9d18\r\n9d1a\r\n9d1c\r\n9d1e\r\n9d20\r\nBREAK\r\n1\r\n24fce\r\nBREAK\r\n1\r\n24fd4\r\nBREAK\r\n1\r\n24fda\r\nBREAK\r\n1\r\n24fe0\r\nBREAK\r\n1\r\n24fe6\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\n24fec\r\nBREAK\r\n1\r\n4b5\r\n9ce2\r\n9ce4\r\n9ce6\r\n9ce8\r\n9cea\r\n9cec\r\n9cee\r\n9cf0\r\n9cf2\r\n9cf4\r\n9cf6\r\n9cf8\r\n9cfa\r\n9cfc\r\n9cfe\r\n9d00\r\n9d02\r\n9d04\r\n9d06\r\n9d08\r\n9d0a\r\n9d0c\r\n9d0e\r\n9d10\r\n9d12\r\n9d14\r\n9d16\r\n9d18\r\n9d1a\r\n9d1c\r\n9d1e\r\n9d20\r\nBREAK\r\n1\r\n24ff2\r\nBREAK\r\n1\r\n24ff8\r\nBREAK\r\n1\r\n24ffe\r\nBREAK\r\n1\r\n25004\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\n2500a\r\nBREAK\r\n1\r\n4b5\r\n9ce2\r\n9ce4\r\n9ce6\r\n9ce8\r\n9cea\r\n9cec\r\n9cee\r\n9cf0\r\n9cf2\r\n9cf4\r\n9cf6\r\n9cf8\r\n9cfa\r\n9cfc\r\n9cfe\r\n9d00\r\n9d02\r\n9d04\r\n9d06\r\n9d08\r\n9d0a\r\n9d0c\r\n9d0e\r\n9d10\r\n9d12\r\n9d14\r\n9d16\r\n9d18\r\n9d1a\r\n9d1c\r\n9d1e\r\n9d20\r\nBREAK\r\n1\r\n25010\r\nBREAK\r\n1\r\n25016\r\nBREAK\r\n1\r\n2501c\r\nBREAK\r\n1\r\n25022\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\n25028\r\nBREAK\r\n1\r\n4b5\r\n9ce2\r\n9ce4\r\n9ce6\r\n9ce8\r\n9cea\r\n9cec\r\n9cee\r\n9cf0\r\n9cf2\r\n9cf4\r\n9cf6\r\n9cf8\r\n9cfa\r\n9cfc\r\n9cfe\r\n9d00\r\n9d02\r\n9d04\r\n9d06\r\n9d08\r\n9d0a\r\n9d0c\r\n9d0e\r\n9d10\r\n9d12\r\n9d14\r\n9d16\r\n9d18\r\n9d1a\r\n9d1c\r\n9d1e\r\n9d20\r\nBREAK\r\n1\r\n2502e\r\nBREAK\r\n1\r\n25034\r\nBREAK\r\n1\r\n2503a\r\nBREAK\r\n1\r\n25040\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\n25046\r\nBREAK\r\n1\r\n4b5\r\n9ce2\r\n9ce4\r\n9ce6\r\n9ce8\r\n9cea\r\n9cec\r\n9cee\r\n9cf0\r\n9cf2\r\n9cf4\r\n9cf6\r\n9cf8\r\n9cfa\r\n9cfc\r\n9cfe\r\n9d00\r\n9d02\r\n9d04\r\n9d06\r\n9d08\r\n9d0a\r\n9d0c\r\n9d0e\r\n9d10\r\n9d12\r\n9d14\r\n9d16\r\n9d18\r\n9d1a\r\n9d1c\r\n9d1e\r\n9d20\r\nBREAK\r\n1\r\n2504c\r\nBREAK\r\n1\r\n25052\r\nBREAK\r\n1\r\n25058\r\nBREAK\r\n1\r\n2505e\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\n25064\r\nBREAK\r\n1\r\n4b5\r\n9ce2\r\n9ce4\r\n9ce6\r\n9ce8\r\n9cea\r\n9cec\r\n9cee\r\n9cf0\r\n9cf2\r\n9cf4\r\n9cf6\r\n9cf8\r\n9cfa\r\n9cfc\r\n9cfe\r\n9d00\r\n9d02\r\n9d04\r\n9d06\r\n9d08\r\n9d0a\r\n9d0c\r\n9d0e\r\n9d10\r\n9d12\r\n9d14\r\n9d16\r\n9d18\r\n9d1a\r\n9d1c\r\n9d1e\r\n9d20\r\nBREAK\r\n1\r\n2506a\r\nBREAK\r\n1\r\n25070\r\nBREAK\r\n1\r\n25076\r\nBREAK\r\n1\r\n2507c\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\n25082\r\nBREAK\r\n1\r\n4b5\r\n9ce2\r\n9ce4\r\n9ce6\r\n9ce8\r\n9cea\r\n9cec\r\n9cee\r\n9cf0\r\n9cf2\r\n9cf4\r\n9cf6\r\n9cf8\r\n9cfa\r\n9cfc\r\n9cfe\r\n9d00\r\n9d02\r\n9d04\r\n9d06\r\n9d08\r\n9d0a\r\n9d0c\r\n9d0e\r\n9d10\r\n9d12\r\n9d14\r\n9d16\r\n9d18\r\n9d1a\r\n9d1c\r\n9d1e\r\n9d20\r\nBREAK\r\n1\r\n25088\r\nBREAK\r\n1\r\n2508e\r\nBREAK\r\n1\r\n25094\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\n2509a\r\nBREAK\r\n1\r\n4b5\r\n9ce2\r\n9ce4\r\n9ce6\r\n9ce8\r\n9cea\r\n9cec\r\n9cee\r\n9cf0\r\n9cf2\r\n9cf4\r\n9cf6\r\n9cf8\r\n9cfa\r\n9cfc\r\n9cfe\r\n9d00\r\n9d02\r\n9d04\r\n9d06\r\n9d08\r\n9d0a\r\n9d0c\r\n9d0e\r\n9d10\r\n9d12\r\n9d14\r\n9d16\r\n9d18\r\n9d1a\r\n9d1c\r\n9d1e\r\n9d20\r\nBREAK\r\n1\r\n250a0\r\nBREAK\r\n1\r\n250a6\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\n250ac\r\nBREAK\r\n1\r\n4b5\r\n9ce2\r\n9ce4\r\n9ce6\r\n9ce8\r\n9cea\r\n9cec\r\n9cee\r\n9cf0\r\n9cf2\r\n9cf4\r\n9cf6\r\n9cf8\r\n9cfa\r\n9cfc\r\n9cfe\r\n9d00\r\n9d02\r\n9d04\r\n9d06\r\n9d08\r\n9d0a\r\n9d0c\r\n9d0e\r\n9d10\r\n9d12\r\n9d14\r\n9d16\r\n9d18\r\n9d1a\r\n9d1c\r\n9d1e\r\n9d20\r\nBREAK\r\n1\r\n250b2\r\nBREAK\r\n1\r\n250b8\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\n250be\r\nBREAK\r\n1\r\n4b5\r\n9ce2\r\n9ce4\r\n9ce6\r\n9ce8\r\n9cea\r\n9cec\r\n9cee\r\n9cf0\r\n9cf2\r\n9cf4\r\n9cf6\r\n9cf8\r\n9cfa\r\n9cfc\r\n9cfe\r\n9d00\r\n9d02\r\n9d04\r\n9d06\r\n9d08\r\n9d0a\r\n9d0c\r\n9d0e\r\n9d10\r\n9d12\r\n9d14\r\n9d16\r\n9d18\r\n9d1a\r\n9d1c\r\n9d1e\r\n9d20\r\nBREAK\r\n1\r\n250c4\r\nBREAK\r\n1\r\n250ca\r\nBREAK\r\n1\r\n250d0\r\nBREAK\r\n1\r\n4f1\r\nabec//3d tour\r\nabee\r\nabf6\r\nabfa\r\nac02\r\nac06\r\nac0e\r\nac12\r\nac1a\r\nac1e\r\nac26\r\nac2a\r\nac32\r\nac36\r\nac3e\r\nac42\r\nac4a\r\nac4e\r\nac56\r\nac5a\r\nac62\r\nac66\r\nac6e\r\nac72\r\nac7a\r\nac7e\r\nac86\r\nac8a\r\nac92\r\nac96\r\nac9e\r\naca2\r\nacaa\r\nacae\r\nacb6\r\nacba\r\nacc2\r\nacc6\r\nacce\r\nacd2\r\nacda\r\nacde\r\nace6\r\nacea\r\nacf2\r\nacf6\r\nacfe\r\nad02\r\nad0a\r\nad0e\r\nad16\r\nad1a\r\nad22\r\nad26\r\nad2e\r\nad32\r\nad3a\r\nad3e\r\nad46\r\nad4a\r\nad52\r\nad56\r\nad5e\r\nBREAK\r\n1\r\n250d6\r\nBREAK\r\n1\r\n4f1\r\nabec\r\nabee\r\nabf6\r\nabfa\r\nac02\r\nac06\r\nac0e\r\nac12\r\nac1a\r\nac1e\r\nac26\r\nac2a\r\nac32\r\nac36\r\nac3e\r\nac42\r\nac4a\r\nac4e\r\nac56\r\nac5a\r\nac62\r\nac66\r\nac6e\r\nac72\r\nac7a\r\nac7e\r\nac86\r\nac8a\r\nac92\r\nac96\r\nac9e\r\naca2\r\nacaa\r\nacae\r\nacb6\r\nacba\r\nacc2\r\nacc6\r\nacce\r\nacd2\r\nacda\r\nacde\r\nace6\r\nacea\r\nacf2\r\nacf6\r\nacfe\r\nad02\r\nad0a\r\nad0e\r\nad16\r\nad1a\r\nad22\r\nad26\r\nad2e\r\nad32\r\nad3a\r\nad3e\r\nad46\r\nad4a\r\nad52\r\nad56\r\nad5e\r\nBREAK\r\n1\r\n250dc\r\nBREAK\r\n1\r\n250e2\r\nBREAK\r\n1\r\n4f1\r\nabec\r\nabee\r\nabf6\r\nabfa\r\nac02\r\nac06\r\nac0e\r\nac12\r\nac1a\r\nac1e\r\nac26\r\nac2a\r\nac32\r\nac36\r\nac3e\r\nac42\r\nac4a\r\nac4e\r\nac56\r\nac5a\r\nac62\r\nac66\r\nac6e\r\nac72\r\nac7a\r\nac7e\r\nac86\r\nac8a\r\nac92\r\nac96\r\nac9e\r\naca2\r\nacaa\r\nacae\r\nacb6\r\nacba\r\nacc2\r\nacc6\r\nacce\r\nacd2\r\nacda\r\nacde\r\nace6\r\nacea\r\nacf2\r\nacf6\r\nacfe\r\nad02\r\nad0a\r\nad0e\r\nad16\r\nad1a\r\nad22\r\nad26\r\nad2e\r\nad32\r\nad3a\r\nad3e\r\nad46\r\nad4a\r\nad52\r\nad56\r\nad5e\r\nBREAK\r\n1\r\n250e8\r\nBREAK\r\n1\r\n250ee\r\nBREAK\r\n1\r\n4f1\r\nabec\r\nabee\r\nabf6\r\nabfa\r\nac02\r\nac06\r\nac0e\r\nac12\r\nac1a\r\nac1e\r\nac26\r\nac2a\r\nac32\r\nac36\r\nac3e\r\nac42\r\nac4a\r\nac4e\r\nac56\r\nac5a\r\nac62\r\nac66\r\nac6e\r\nac72\r\nac7a\r\nac7e\r\nac86\r\nac8a\r\nac92\r\nac96\r\nac9e\r\naca2\r\nacaa\r\nacae\r\nacb6\r\nacba\r\nacc2\r\nacc6\r\nacce\r\nacd2\r\nacda\r\nacde\r\nace6\r\nacea\r\nacf2\r\nacf6\r\nacfe\r\nad02\r\nad0a\r\nad0e\r\nad16\r\nad1a\r\nad22\r\nad26\r\nad2e\r\nad32\r\nad3a\r\nad3e\r\nad46\r\nad4a\r\nad52\r\nad56\r\nad5e\r\nBREAK\r\n1\r\n250f4\r\nBREAK\r\n1\r\n250fa\r\nBREAK\r\n1\r\n4f1\r\nabec\r\nabee\r\nabf6\r\nabfa\r\nac02\r\nac06\r\nac0e\r\nac12\r\nac1a\r\nac1e\r\nac26\r\nac2a\r\nac32\r\nac36\r\nac3e\r\nac42\r\nac4a\r\nac4e\r\nac56\r\nac5a\r\nac62\r\nac66\r\nac6e\r\nac72\r\nac7a\r\nac7e\r\nac86\r\nac8a\r\nac92\r\nac96\r\nac9e\r\naca2\r\nacaa\r\nacae\r\nacb6\r\nacba\r\nacc2\r\nacc6\r\nacce\r\nacd2\r\nacda\r\nacde\r\nace6\r\nacea\r\nacf2\r\nacf6\r\nacfe\r\nad02\r\nad0a\r\nad0e\r\nad16\r\nad1a\r\nad22\r\nad26\r\nad2e\r\nad32\r\nad3a\r\nad3e\r\nad46\r\nad4a\r\nad52\r\nad56\r\nad5e\r\nBREAK\r\n1\r\n25100\r\nBREAK\r\n1\r\n25106\r\nBREAK\r\n1\r\n4f1\r\nabec\r\nabee\r\nabf6\r\nabfa\r\nac02\r\nac06\r\nac0e\r\nac12\r\nac1a\r\nac1e\r\nac26\r\nac2a\r\nac32\r\nac36\r\nac3e\r\nac42\r\nac4a\r\nac4e\r\nac56\r\nac5a\r\nac62\r\nac66\r\nac6e\r\nac72\r\nac7a\r\nac7e\r\nac86\r\nac8a\r\nac92\r\nac96\r\nac9e\r\naca2\r\nacaa\r\nacae\r\nacb6\r\nacba\r\nacc2\r\nacc6\r\nacce\r\nacd2\r\nacda\r\nacde\r\nace6\r\nacea\r\nacf2\r\nacf6\r\nacfe\r\nad02\r\nad0a\r\nad0e\r\nad16\r\nad1a\r\nad22\r\nad26\r\nad2e\r\nad32\r\nad3a\r\nad3e\r\nad46\r\nad4a\r\nad52\r\nad56\r\nad5e\r\nBREAK\r\n1\r\n2510c\r\nBREAK\r\n1\r\n25112\r\nBREAK\r\n1\r\n4f1\r\nabec\r\nabee\r\nabf6\r\nabfa\r\nac02\r\nac06\r\nac0e\r\nac12\r\nac1a\r\nac1e\r\nac26\r\nac2a\r\nac32\r\nac36\r\nac3e\r\nac42\r\nac4a\r\nac4e\r\nac56\r\nac5a\r\nac62\r\nac66\r\nac6e\r\nac72\r\nac7a\r\nac7e\r\nac86\r\nac8a\r\nac92\r\nac96\r\nac9e\r\naca2\r\nacaa\r\nacae\r\nacb6\r\nacba\r\nacc2\r\nacc6\r\nacce\r\nacd2\r\nacda\r\nacde\r\nace6\r\nacea\r\nacf2\r\nacf6\r\nacfe\r\nad02\r\nad0a\r\nad0e\r\nad16\r\nad1a\r\nad22\r\nad26\r\nad2e\r\nad32\r\nad3a\r\nad3e\r\nad46\r\nad4a\r\nad52\r\nad56\r\nad5e\r\nBREAK\r\n1\r\n25118\r\nBREAK\r\n1\r\n2511e\r\nBREAK\r\n1\r\n4f1\r\nabec\r\nabee\r\nabf6\r\nabfa\r\nac02\r\nac06\r\nac0e\r\nac12\r\nac1a\r\nac1e\r\nac26\r\nac2a\r\nac32\r\nac36\r\nac3e\r\nac42\r\nac4a\r\nac4e\r\nac56\r\nac5a\r\nac62\r\nac66\r\nac6e\r\nac72\r\nac7a\r\nac7e\r\nac86\r\nac8a\r\nac92\r\nac96\r\nac9e\r\naca2\r\nacaa\r\nacae\r\nacb6\r\nacba\r\nacc2\r\nacc6\r\nacce\r\nacd2\r\nacda\r\nacde\r\nace6\r\nacea\r\nacf2\r\nacf6\r\nacfe\r\nad02\r\nad0a\r\nad0e\r\nad16\r\nad1a\r\nad22\r\nad26\r\nad2e\r\nad32\r\nad3a\r\nad3e\r\nad46\r\nad4a\r\nad52\r\nad56\r\nad5e\r\nBREAK\r\n1\r\n25124\r\nBREAK\r\n1\r\n2512a\r\nBREAK\r\n1\r\n4f1\r\nabec\r\nabee\r\nabf6\r\nabfa\r\nac02\r\nac06\r\nac0e\r\nac12\r\nac1a\r\nac1e\r\nac26\r\nac2a\r\nac32\r\nac36\r\nac3e\r\nac42\r\nac4a\r\nac4e\r\nac56\r\nac5a\r\nac62\r\nac66\r\nac6e\r\nac72\r\nac7a\r\nac7e\r\nac86\r\nac8a\r\nac92\r\nac96\r\nac9e\r\naca2\r\nacaa\r\nacae\r\nacb6\r\nacba\r\nacc2\r\nacc6\r\nacce\r\nacd2\r\nacda\r\nacde\r\nace6\r\nacea\r\nacf2\r\nacf6\r\nacfe\r\nad02\r\nad0a\r\nad0e\r\nad16\r\nad1a\r\nad22\r\nad26\r\nad2e\r\nad32\r\nad3a\r\nad3e\r\nad46\r\nad4a\r\nad52\r\nad56\r\nad5e\r\nBREAK\r\n1\r\n25130\r\nBREAK\r\n1\r\n25136\r\nBREAK\r\n1\r\n2513c\r\nBREAK\r\n1\r\n4f1\r\nabec\r\nabee\r\nabf6\r\nabfa\r\nac02\r\nac06\r\nac0e\r\nac12\r\nac1a\r\nac1e\r\nac26\r\nac2a\r\nac32\r\nac36\r\nac3e\r\nac42\r\nac4a\r\nac4e\r\nac56\r\nac5a\r\nac62\r\nac66\r\nac6e\r\nac72\r\nac7a\r\nac7e\r\nac86\r\nac8a\r\nac92\r\nac96\r\nac9e\r\naca2\r\nacaa\r\nacae\r\nacb6\r\nacba\r\nacc2\r\nacc6\r\nacce\r\nacd2\r\nacda\r\nacde\r\nace6\r\nacea\r\nacf2\r\nacf6\r\nacfe\r\nad02\r\nad0a\r\nad0e\r\nad16\r\nad1a\r\nad22\r\nad26\r\nad2e\r\nad32\r\nad3a\r\nad3e\r\nad46\r\nad4a\r\nad52\r\nad56\r\nad5e\r\nBREAK\r\n1\r\n25142\r\nBREAK\r\n1\r\n25148\r\nBREAK\r\n1\r\n4f1\r\nabec\r\nabee\r\nabf6\r\nabfa\r\nac02\r\nac06\r\nac0e\r\nac12\r\nac1a\r\nac1e\r\nac26\r\nac2a\r\nac32\r\nac36\r\nac3e\r\nac42\r\nac4a\r\nac4e\r\nac56\r\nac5a\r\nac62\r\nac66\r\nac6e\r\nac72\r\nac7a\r\nac7e\r\nac86\r\nac8a\r\nac92\r\nac96\r\nac9e\r\naca2\r\nacaa\r\nacae\r\nacb6\r\nacba\r\nacc2\r\nacc6\r\nacce\r\nacd2\r\nacda\r\nacde\r\nace6\r\nacea\r\nacf2\r\nacf6\r\nacfe\r\nad02\r\nad0a\r\nad0e\r\nad16\r\nad1a\r\nad22\r\nad26\r\nad2e\r\nad32\r\nad3a\r\nad3e\r\nad46\r\nad4a\r\nad52\r\nad56\r\nad5e\r\nBREAK\r\n1\r\n2514e\r\nBREAK\r\n1\r\n25154\r\nBREAK\r\n1\r\n2515a\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n25160\r\nBREAK\r\n1\r\n25166\r\nBREAK\r\n1\r\n2516c\r\nBREAK\r\n1\r\n25172\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n25178\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n2517e\r\nBREAK\r\n1\r\n25184\r\nBREAK\r\n1\r\n2518a\r\nBREAK\r\n1\r\n25190\r\nBREAK\r\n1\r\n25196\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n2519c\r\nBREAK\r\n1\r\n4fa\r\naf3a\r\naf54\r\naf58\r\naf5c\r\naf60\r\naf64\r\naf68\r\naf6c\r\naf70\r\nBREAK\r\n1\r\n251a2\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n251a8\r\nBREAK\r\n1\r\n251ae\r\nBREAK\r\n1\r\n251b4\r\nBREAK\r\n1\r\n251ba\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n251c0\r\nBREAK\r\n1\r\n4fa\r\naf3a\r\naf3c\r\naf40\r\naf44\r\naf48\r\naf4c\r\naf50\r\naf54\r\naf58\r\naf5c\r\naf60\r\naf64\r\naf68\r\naf6c\r\naf70\r\nBREAK\r\n1\r\n251c6\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n251cc\r\nBREAK\r\n1\r\n251d2\r\nBREAK\r\n1\r\n251d8\r\nBREAK\r\n1\r\n251de\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n251e4\r\nBREAK\r\n1\r\n4fd\r\naf74\r\naf76\r\naf7a\r\naf7e\r\naf82\r\naf86\r\naf8a\r\naf8e\r\naf92\r\naf96\r\naf9a\r\naf9e\r\nafa2\r\nafa6\r\nafaa\r\nBREAK\r\n1\r\n251ea\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n251f0\r\nBREAK\r\n1\r\n251f6\r\nBREAK\r\n1\r\n251fc\r\nBREAK\r\n1\r\n25202\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n25208\r\nBREAK\r\n1\r\n2520e\r\nBREAK\r\n1\r\n4fd\r\naf74\r\naf76\r\naf7a\r\naf7e\r\naf82\r\naf86\r\naf8a\r\naf8e\r\naf92\r\naf96\r\naf9a\r\naf9e\r\nafa2\r\nafa6\r\nafaa\r\nBREAK\r\n1\r\n25214\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n2521a\r\nBREAK\r\n1\r\n25220\r\nBREAK\r\n1\r\n25226\r\nBREAK\r\n1\r\n2522c\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n25232\r\nBREAK\r\n1\r\n25238\r\nBREAK\r\n1\r\n500\r\nafae\r\nafb0\r\nafb4\r\nafb8\r\nafbc\r\nafc0\r\nafc4\r\nafc8\r\nafcc\r\nafd0\r\nafd4\r\nafd8\r\nafdc\r\nafe0\r\nafe4\r\nBREAK\r\n1\r\n2523e\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n25244\r\nBREAK\r\n1\r\n2524a\r\nBREAK\r\n1\r\n25250\r\nBREAK\r\n1\r\n25256\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n2525c\r\nBREAK\r\n1\r\n25262\r\nBREAK\r\n1\r\n503\r\n0\r\nafe8\r\nafea\r\nafee\r\naff2\r\naff6\r\naffa\r\naffe\r\nb002\r\nb006\r\nb00a\r\nb00e\r\nb012\r\nb016\r\nb01a\r\nb01e\r\nBREAK\r\n1\r\n25268\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n2526e\r\nBREAK\r\n1\r\n25274\r\nBREAK\r\n1\r\n2527a\r\nBREAK\r\n1\r\n25280\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n25286\r\nBREAK\r\n1\r\n2528c\r\nBREAK\r\n1\r\n506\r\nb022\r\nb024\r\nb028\r\nb02c\r\nb030\r\nb034\r\nb038\r\nb03c\r\nb040\r\nb044\r\nb048\r\nb04c\r\nb050\r\nb054\r\nb058\r\nBREAK\r\n1\r\n25292\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n25298\r\nBREAK\r\n1\r\n2529e\r\nBREAK\r\n1\r\n252a4\r\nBREAK\r\n1\r\n252aa\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n252b0\r\nBREAK\r\n1\r\n252b6\r\nBREAK\r\n1\r\n509\r\nb05c\r\nb05e\r\nb062\r\nb066\r\nb06a\r\nb06e\r\nb072\r\nb076\r\nb07a\r\nb07e\r\nb082\r\nb086\r\nb08a\r\nb08e\r\nb092\r\nBREAK\r\n1\r\n252bc\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n252c2\r\nBREAK\r\n1\r\n252c8\r\nBREAK\r\n1\r\n252ce\r\nBREAK\r\n1\r\n252d4\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n252da\r\nBREAK\r\n1\r\n252e0\r\nBREAK\r\n1\r\n50c\r\nb096\r\nb098\r\nb09c\r\nb0a0\r\nb0a4\r\nb0a8\r\nb0ac\r\nb0b0\r\nb0b4\r\nb0b8\r\nb0bc\r\nb0c0\r\nb0c4\r\nb0c8\r\nb0cc\r\nBREAK\r\n1\r\n252e6\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n252ec\r\nBREAK\r\n1\r\n252f2\r\nBREAK\r\n1\r\n252f8\r\nBREAK\r\n1\r\n252fe\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n25304\r\nBREAK\r\n1\r\n2530a\r\nBREAK\r\n1\r\n4fa\r\naf3a\r\naf3c\r\naf40\r\naf44\r\naf48\r\naf4c\r\naf50\r\naf54\r\naf58\r\naf5c\r\naf60\r\naf64\r\naf68\r\naf6c\r\naf70\r\nBREAK\r\n1\r\n25310\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n25316\r\nBREAK\r\n1\r\n2531c\r\nBREAK\r\n1\r\n25322\r\nBREAK\r\n1\r\n25328\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n2532e\r\nBREAK\r\n1\r\n25334\r\nBREAK\r\n1\r\n500\r\nafae\r\nafb0\r\nafb4\r\nafb8\r\nafbc\r\nafc0\r\nafc4\r\nafc8\r\nafcc\r\nafd0\r\nafd4\r\nafd8\r\nafdc\r\nafe0\r\nafe4\r\nBREAK\r\n1\r\n2533a\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n25340\r\nBREAK\r\n1\r\n25346\r\nBREAK\r\n1\r\n2534c\r\nBREAK\r\n1\r\n25352\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n25358\r\nBREAK\r\n1\r\n2535e\r\nBREAK\r\n1\r\n503\r\n0\r\nafe8\r\nafea\r\nafee\r\naff2\r\naff6\r\naffa\r\naffe\r\nb002\r\nb006\r\nb00a\r\nb00e\r\nb012\r\nb016\r\nb01a\r\nb01e\r\nBREAK\r\n1\r\n25364\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n2536a\r\nBREAK\r\n1\r\n25370\r\nBREAK\r\n1\r\n25376\r\nBREAK\r\n1\r\n2537c\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n25382\r\nBREAK\r\n1\r\n25388\r\nBREAK\r\n1\r\n506\r\nb022\r\nb024\r\nb028\r\nb02c\r\nb030\r\nb034\r\nb038\r\nb03c\r\nb040\r\nb044\r\nb048\r\nb04c\r\nb050\r\nb054\r\nb058\r\nBREAK\r\n1\r\n2538e\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n25394\r\nBREAK\r\n1\r\n2539a\r\nBREAK\r\n1\r\n253a0\r\nBREAK\r\n1\r\n253a6\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n253ac\r\nBREAK\r\n1\r\n253b2\r\nBREAK\r\n1\r\n50f\r\nb0d0\r\nb0d2\r\nb0d6\r\nb0da\r\nb0de\r\nb0e2\r\nb0e6\r\nb0ea\r\nb0ee\r\nb0f2\r\nb0f6\r\nb0fa\r\nb0fe\r\nb102\r\nb106\r\nBREAK\r\n1\r\n253b8\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n253be\r\nBREAK\r\n1\r\n253c4\r\nBREAK\r\n1\r\n253ca\r\nBREAK\r\n1\r\n253d0\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n253d6\r\nBREAK\r\n1\r\n253dc\r\nBREAK\r\n1\r\n512\r\nb10a\r\nb10c\r\nb110\r\nb114\r\nb118\r\nb11c\r\nb120\r\nb124\r\nb128\r\nb12c\r\nb130\r\nb134\r\nb138\r\nb13c\r\nb140\r\nBREAK\r\n1\r\n253e2\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n253e8\r\nBREAK\r\n1\r\n253ee\r\nBREAK\r\n1\r\n253f4\r\nBREAK\r\n1\r\n253fa\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n25400\r\nBREAK\r\n1\r\n25406\r\nBREAK\r\n1\r\n50f\r\nb0d0\r\nb0d2\r\nb0d6\r\nb0da\r\nb0de\r\nb0e2\r\nb0e6\r\nb0ea\r\nb0ee\r\nb0f2\r\nb0f6\r\nb0fa\r\nb0fe\r\nb102\r\nb106\r\nBREAK\r\n1\r\n2540c\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n25412\r\nBREAK\r\n1\r\n25418\r\nBREAK\r\n1\r\n2541e\r\nBREAK\r\n1\r\n25424\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n2542a\r\nBREAK\r\n1\r\n25430\r\nBREAK\r\n1\r\n512\r\nb10a\r\nb10c\r\nb110\r\nb114\r\nb118\r\nb11c\r\nb120\r\nb124\r\nb128\r\nb12c\r\nb130\r\nb134\r\nb138\r\nb13c\r\nb140\r\nBREAK\r\n1\r\n25436\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n2543c\r\nBREAK\r\n1\r\n25442\r\nBREAK\r\n1\r\n25448\r\nBREAK\r\n1\r\n2544e\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n25454\r\nBREAK\r\n1\r\n2545a\r\nBREAK\r\n1\r\n50f\r\nb0d0\r\nb0d2\r\nb0d6\r\nb0da\r\nb0de\r\nb0e2\r\nb0e6\r\nb0ea\r\nb0ee\r\nb0f2\r\nb0f6\r\nb0fa\r\nb0fe\r\nb102\r\nb106\r\nBREAK\r\n1\r\n25460\r\nBREAK\r\n1\r\n25466\r\nBREAK\r\n1\r\n515\r\nb144\r\nb146\r\nb14e\r\nb152\r\nb15a\r\nb15e\r\nb166\r\nb16a\r\nb172\r\nb176\r\nb17e\r\nb182\r\nb18a\r\nb18e\r\nb196\r\nb19a\r\nb1a2\r\nb1a6\r\nb1ae\r\nb1b2\r\nb1ba\r\nb1be\r\nb1c6\r\nb1ca\r\nb1d2\r\nb1d6\r\nb1de\r\nb1e2\r\nb1ea\r\nb1ee\r\nb1f6\r\nb1fa\r\nb202\r\nb206\r\nb20e\r\nb212\r\nb21a\r\nb21e\r\nb226\r\nb22a\r\nb232\r\nb236\r\nb23e\r\nb242\r\nb24a\r\nb24e\r\nb256\r\nb25a\r\nb262\r\nb266\r\nb26e\r\nb272\r\nb27a\r\nb27e\r\nb286\r\nb28a\r\nb292\r\nb296\r\nb29e\r\nb2a2\r\nb2aa\r\nb2ae\r\nb2b6\r\nBREAK\r\n1\r\n2546c\r\nBREAK\r\n1\r\n25472\r\nBREAK\r\n1\r\n512\r\nb10a\r\nb10c\r\nb110\r\nb114\r\nb118\r\nb11c\r\nb120\r\nb124\r\nb128\r\nb12c\r\nb130\r\nb134\r\nb138\r\nb13c\r\nb140\r\nBREAK\r\n1\r\n25478\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n2547e\r\nBREAK\r\n1\r\n25484\r\nBREAK\r\n1\r\n2548a\r\nBREAK\r\n1\r\n25490\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n25496\r\nBREAK\r\n1\r\n2549c\r\nBREAK\r\n1\r\n50f\r\nb0d0\r\nb0d2\r\nb0d6\r\nb0da\r\nb0de\r\nb0e2\r\nb0e6\r\nb0ea\r\nb0ee\r\nb0f2\r\nb0f6\r\nb0fa\r\nb0fe\r\nb102\r\nb106\r\nBREAK\r\n1\r\n254a2\r\nBREAK\r\n1\r\n254a8\r\nBREAK\r\n1\r\n515\r\nb144\r\nb146\r\nb14e\r\nb152\r\nb15a\r\nb15e\r\nb166\r\nb16a\r\nb172\r\nb176\r\nb17e\r\nb182\r\nb18a\r\nb18e\r\nb196\r\nb19a\r\nb1a2\r\nb1a6\r\nb1ae\r\nb1b2\r\nb1ba\r\nb1be\r\nb1c6\r\nb1ca\r\nb1d2\r\nb1d6\r\nb1de\r\nb1e2\r\nb1ea\r\nb1ee\r\nb1f6\r\nb1fa\r\nb202\r\nb206\r\nb20e\r\nb212\r\nb21a\r\nb21e\r\nb226\r\nb22a\r\nb232\r\nb236\r\nb23e\r\nb242\r\nb24a\r\nb24e\r\nb256\r\nb25a\r\nb262\r\nb266\r\nb26e\r\nb272\r\nb27a\r\nb27e\r\nb286\r\nb28a\r\nb292\r\nb296\r\nb29e\r\nb2a2\r\nb2aa\r\nb2ae\r\nb2b6\r\nBREAK\r\n1\r\n254ae\r\nBREAK\r\n1\r\n512\r\nb10a\r\nb10c\r\nb110\r\nb114\r\nb118\r\nb11c\r\nb120\r\nb124\r\nb128\r\nb12c\r\nb130\r\nb134\r\nb138\r\nb13c\r\nb140\r\nBREAK\r\n1\r\n254b4\r\nBREAK\r\n1\r\n254ba\r\nBREAK\r\n1\r\n254c0\r\nBREAK\r\n1\r\n254c6\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n254cc\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n254d2\r\nBREAK\r\n1\r\n254d8\r\nBREAK\r\n1\r\n254de\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n254e4\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n254ea\r\nBREAK\r\n1\r\n254f0\r\nBREAK\r\n1\r\n254f6\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n254fc\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n25502\r\nBREAK\r\n1\r\n25508\r\nBREAK\r\n1\r\n2550e\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n25514\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n2551a\r\nBREAK\r\n1\r\n25520\r\nBREAK\r\n1\r\n25526\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n2552c\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n25532\r\nBREAK\r\n1\r\n25538\r\nBREAK\r\n1\r\n2553e\r\nBREAK\r\n1\r\n25544\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n2554a\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n25550\r\nBREAK\r\n1\r\n25556\r\nBREAK\r\n1\r\n2555c\r\nBREAK\r\n1\r\n25562\r\nBREAK\r\n1\r\n25568\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n2556e\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n25574\r\nBREAK\r\n1\r\n2557a\r\nBREAK\r\n1\r\n25580\r\nBREAK\r\n1\r\n25586\r\nBREAK\r\n1\r\n2558c\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n25592\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n25598\r\nBREAK\r\n1\r\n2559e\r\nBREAK\r\n1\r\n255a4\r\nBREAK\r\n1\r\n255aa\r\nBREAK\r\n1\r\n255b0\r\nBREAK\r\n1\r\n255b6\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n255bc\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n255c2\r\nBREAK\r\n1\r\n255c8\r\nBREAK\r\n1\r\n255ce\r\nBREAK\r\n1\r\n255d4\r\nBREAK\r\n1\r\n255da\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n255e0\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n255e6\r\nBREAK\r\n1\r\n255ec\r\nBREAK\r\n1\r\n255f2\r\nBREAK\r\n1\r\n255f8\r\nBREAK\r\n1\r\n255fe\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n25604\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n2560a\r\nBREAK\r\n1\r\n25610\r\nBREAK\r\n1\r\n25616\r\nBREAK\r\n1\r\n2561c\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n25622\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n25628\r\nBREAK\r\n1\r\n2562e\r\nBREAK\r\n1\r\n25634\r\nBREAK\r\n1\r\n2563a\r\nBREAK\r\n1\r\n25640\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n25646\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n2564c\r\nBREAK\r\n1\r\n25652\r\nBREAK\r\n1\r\n25658\r\nBREAK\r\n1\r\n2565e\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n25664\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n2566a\r\nBREAK\r\n1\r\n25670\r\nBREAK\r\n1\r\n25676\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n2567c\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n25682\r\nBREAK\r\n1\r\n25688\r\nBREAK\r\n1\r\n2568e\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n25694\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n2569a\r\nBREAK\r\n1\r\n256a0\r\nBREAK\r\n1\r\n256a6\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n256ac\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n256b2\r\nBREAK\r\n1\r\n256b8\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n256be\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n256c4\r\nBREAK\r\n1\r\n256ca\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n256d0\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n256d6\r\nBREAK\r\n1\r\n256dc\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n256e2\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n256e8\r\nBREAK\r\n1\r\n256ee\r\nBREAK\r\n1\r\n479\r\n9188\r\n918a\r\n9190\r\n30091\r\n9196\r\n30091\r\n919c\r\n30091\r\n91a2\r\n30091\r\n91a8\r\n30091\r\n91ae\r\n30091\r\n91b4\r\n30091\r\n91ba\r\n30091\r\n91c0\r\n30091\r\n91c6\r\n30091\r\n91cc\r\n30091\r\n91d2\r\n30091\r\n91d8\r\n30091\r\n91de\r\n30091\r\n91e4\r\n30091\r\n91ea\r\n30091\r\n91f0\r\n30091\r\n91f6\r\n30091\r\n91fc\r\n30092\r\n9202\r\n30092\r\n9208\r\n30092\r\n920e\r\n30092\r\n9214\r\n30092\r\n921a\r\n30092\r\n9220\r\n30092\r\n9226\r\n30092\r\n922c\r\n30092\r\n9232\r\n30092\r\n9238\r\n30092\r\n923e\r\n30000\r\nBREAK\r\n1\r\n256f4\r\n30000\r\nBREAK\r\n1\r\n47c\r\n9244\r\n9246\r\n924c\r\n9252\r\n9258\r\n925e\r\n9264\r\n926a\r\n9270\r\n9276\r\n927c\r\n9282\r\n9288\r\n928e\r\n9294\r\n929a\r\nBREAK\r\n1\r\n256fa\r\nBREAK\r\n1\r\n25700\r\nBREAK\r\n1\r\n482\r\n92ee\r\n92f0\r\n92f8\r\n9300\r\n9308\r\n9310\r\n9318\r\n9320\r\n9328\r\n9330\r\n9338\r\nc0008\r\n9340\r\nf00008\r\n9348\r\n8\r\n9350\r\n9358\r\n9360\r\n9368\r\n9370\r\n8\r\n9378\r\n8\r\n9380\r\n8\r\n9388\r\n8\r\n9390\r\n8\r\n9398\r\n8\r\n93a0\r\n8\r\n93a8\r\n8\r\n93b0\r\nc00008\r\n93b8\r\n93c0\r\n93c8\r\n93d0\r\n93d8\r\n93e0\r\nBREAK\r\n1\r\n25706\r\nBREAK\r\n1\r\n47f\r\n92a0\r\n92a2\r\n92a6\r\n92aa\r\n92ae\r\n92b2\r\n92b6\r\n92ba\r\n92be\r\n92c2\r\n92c6\r\n92ca\r\n92ce\r\n92d2\r\n92d6\r\n92da\r\n92de\r\n92e2\r\n92e6\r\n92ea\r\nBREAK\r\n1\r\n2570c\r\nBREAK\r\n1\r\n25712\r\nBREAK\r\n1\r\n482\r\n92ee\r\n92f0\r\n92f8\r\n9300\r\n9308\r\n9310\r\n9318\r\n9320\r\n9328\r\n9330\r\n9338\r\nc0008\r\n9340\r\nf00008\r\n9348\r\n8\r\n9350\r\n9358\r\n9360\r\n9368\r\n9370\r\n8\r\n9378\r\n8\r\n9380\r\n8\r\n9388\r\n8\r\n9390\r\n8\r\n9398\r\n8\r\n93a0\r\n8\r\n93a8\r\n8\r\n93b0\r\nc00008\r\n93b8\r\n93c0\r\n93c8\r\n93d0\r\n93d8\r\n93e0\r\nBREAK\r\n1\r\n25718\r\nBREAK\r\n1\r\n47f\r\n92a0\r\n92a2\r\n92a6\r\n92aa\r\n92ae\r\n92b2\r\n92b6\r\n92ba\r\n92be\r\n92c2\r\n92c6\r\n92ca\r\n92ce\r\n92d2\r\n92d6\r\n92da\r\n92de\r\n92e2\r\n92e6\r\n92ea\r\nBREAK\r\n1\r\n2571e\r\nBREAK\r\n1\r\n25724\r\nBREAK\r\n1\r\n482\r\n92ee\r\n92f0\r\n92f8\r\n9300\r\n9308\r\n9310\r\n9318\r\n9320\r\n9328\r\n9330\r\n9338\r\nc0008\r\n9340\r\nf00008\r\n9348\r\n8\r\n9350\r\n9358\r\n9360\r\n9368\r\n9370\r\n8\r\n9378\r\n8\r\n9380\r\n8\r\n9388\r\n8\r\n9390\r\n8\r\n9398\r\n8\r\n93a0\r\n8\r\n93a8\r\n8\r\n93b0\r\nc00008\r\n93b8\r\n93c0\r\n93c8\r\n93d0\r\n93d8\r\n93e0\r\nBREAK\r\n1\r\n2572a\r\nBREAK\r\n1\r\n47f\r\n92a0\r\n92a2\r\n92a6\r\n92aa\r\n92ae\r\n92b2\r\n92b6\r\n92ba\r\n92be\r\n92c2\r\n92c6\r\n92ca\r\n92ce\r\n92d2\r\n92d6\r\n92da\r\n92de\r\n92e2\r\n92e6\r\n92ea\r\nBREAK\r\n1\r\n25730\r\nBREAK\r\n1\r\n25736\r\nBREAK\r\n1\r\n482\r\n92ee\r\n92f0\r\n92f8\r\n9300\r\n9308\r\n9310\r\n9318\r\n9320\r\n9328\r\n9330\r\n9338\r\nc0008\r\n9340\r\nf00008\r\n9348\r\n8\r\n9350\r\n9358\r\n9360\r\n9368\r\n9370\r\n8\r\n9378\r\n8\r\n9380\r\n8\r\n9388\r\n8\r\n9390\r\n8\r\n9398\r\n8\r\n93a0\r\n8\r\n93a8\r\n8\r\n93b0\r\nc00008\r\n93b8\r\n93c0\r\n93c8\r\n93d0\r\n93d8\r\n93e0\r\nBREAK\r\n1\r\n2573c\r\nBREAK\r\n1\r\n47f\r\n92a0\r\n92a2\r\n92a6\r\n92aa\r\n92ae\r\n92b2\r\n92b6\r\n92ba\r\n92be\r\n92c2\r\n92c6\r\n92ca\r\n92ce\r\n92d2\r\n92d6\r\n92da\r\n92de\r\n92e2\r\n92e6\r\n92ea\r\nBREAK\r\n1\r\n25742\r\nBREAK\r\n1\r\n25748\r\nBREAK\r\n1\r\n491\r\n97d0\r\n97d2\r\n97d3\r\n97d4\r\n97d5\r\n97d6\r\n97d7\r\n97d8\r\nBREAK\r\n1\r\n2574e\r\nBREAK\r\n1\r\n25754\r\nBREAK\r\n1\r\n482\r\n92ee\r\n92f0\r\n92f8\r\n9300\r\n9308\r\n9310\r\n9318\r\n9320\r\n9328\r\n9330\r\n9338\r\nc0008\r\n9340\r\nf00008\r\n9348\r\n8\r\n9350\r\n9358\r\n9360\r\n9368\r\n9370\r\n8\r\n9378\r\n8\r\n9380\r\n8\r\n9388\r\n8\r\n9390\r\n8\r\n9398\r\n8\r\n93a0\r\n8\r\n93a8\r\n8\r\n93b0\r\nc00008\r\n93b8\r\n93c0\r\n93c8\r\n93d0\r\n93d8\r\n93e0\r\nBREAK\r\n1\r\n2575a\r\nBREAK\r\n1\r\n47f\r\n92a0\r\n92a2\r\n92a6\r\n92aa\r\n92ae\r\n92b2\r\n92b6\r\n92ba\r\n92be\r\n92c2\r\n92c6\r\n92ca\r\n92ce\r\n92d2\r\n92d6\r\n92da\r\n92de\r\n92e2\r\n92e6\r\n92ea\r\nBREAK\r\n1\r\n25760\r\nBREAK\r\n1\r\n25766\r\nBREAK\r\n1\r\n494\r\n97d9\r\n97db\r\n97dc\r\n97dd\r\n97de\r\n97df\r\n97e0\r\n97e1\r\nBREAK\r\n1\r\n2576c\r\nBREAK\r\n1\r\n25772\r\nBREAK\r\n1\r\n482\r\n92ee\r\n92f0\r\n92f8\r\n9300\r\n9308\r\n9310\r\n9318\r\n9320\r\n9328\r\n9330\r\n9338\r\nc0008\r\n9340\r\nf00008\r\n9348\r\n8\r\n9350\r\n9358\r\n9360\r\n9368\r\n9370\r\n8\r\n9378\r\n8\r\n9380\r\n8\r\n9388\r\n8\r\n9390\r\n8\r\n9398\r\n8\r\n93a0\r\n8\r\n93a8\r\n8\r\n93b0\r\nc00008\r\n93b8\r\n93c0\r\n93c8\r\n93d0\r\n93d8\r\n93e0\r\nBREAK\r\n1\r\n25778\r\nBREAK\r\n1\r\n47f\r\n92a0\r\n92a2\r\n92a6\r\n92aa\r\n92ae\r\n92b2\r\n92b6\r\n92ba\r\n92be\r\n92c2\r\n92c6\r\n92ca\r\n92ce\r\n92d2\r\n92d6\r\n92da\r\n92de\r\n92e2\r\n92e6\r\n92ea\r\nBREAK\r\n1\r\n2577e\r\nBREAK\r\n1\r\n25784\r\nBREAK\r\n1\r\n497\r\n97e2\r\n97e4\r\n97e5\r\n97e6\r\n97e7\r\n97e8\r\n97e9\r\n97ea\r\nBREAK\r\n1\r\n2578a\r\nBREAK\r\n1\r\n25790\r\nBREAK\r\n1\r\n485\r\n93e8\r\n93ea\r\n93f2\r\n93fa\r\n9402\r\n940a\r\n9412\r\n941a\r\n9422\r\n942a\r\n9432\r\nc0008\r\n943a\r\nf00008\r\n9442\r\n8\r\n944a\r\n9452\r\n945a\r\n9462\r\n946a\r\n8\r\n9472\r\n8\r\n947a\r\n8008\r\n9482\r\na22808\r\n948a\r\n9492\r\n949a\r\n94a2\r\n94aa\r\n94b2\r\n94ba\r\n94c2\r\n94ca\r\n94d2\r\n94da\r\nBREAK\r\n1\r\n25796\r\nBREAK\r\n1\r\n47f\r\n92a0\r\n92a2\r\n92a6\r\n92aa\r\n92ae\r\n92b2\r\n92b6\r\n92ba\r\n92be\r\n92c2\r\n92c6\r\n92ca\r\n92ce\r\n92d2\r\n92d6\r\n92da\r\n92de\r\n92e2\r\n92e6\r\n92ea\r\nBREAK\r\n1\r\n2579c\r\nBREAK\r\n1\r\n257a2\r\nBREAK\r\n1\r\n49a\r\n97eb\r\n97ed\r\n97ee\r\n97ef\r\n97f0\r\n97f1\r\n97f2\r\n97f3\r\nBREAK\r\n1\r\n257a8\r\nBREAK\r\n1\r\n257ae\r\nBREAK\r\n1\r\n488\r\n94e2\r\n94e4\r\n94ec\r\nc0008\r\n94f4\r\nf00008\r\n94fc\r\n8\r\n9504\r\n950c\r\n9514\r\n951c\r\n9524\r\n8\r\n952c\r\n8\r\n9534\r\n8\r\n953c\r\n8\r\n9544\r\n8\r\n954c\r\n8\r\n9554\r\n8\r\n955c\r\n8\r\n9564\r\nc00008\r\n956c\r\n9574\r\n957c\r\n9584\r\n958c\r\n9594\r\n959c\r\n95a4\r\n95ac\r\n95b4\r\n95bc\r\n95c4\r\n95cc\r\n95d4\r\nBREAK\r\n1\r\n257b4\r\nBREAK\r\n1\r\n47f\r\n92a0\r\n92a2\r\n92a6\r\n92aa\r\n92ae\r\n92b2\r\n92b6\r\n92ba\r\n92be\r\n92c2\r\n92c6\r\n92ca\r\n92ce\r\n92d2\r\n92d6\r\n92da\r\n92de\r\n92e2\r\n92e6\r\n92ea\r\nBREAK\r\n1\r\n257ba\r\nBREAK\r\n1\r\n257c0\r\nBREAK\r\n1\r\n48b\r\n95dc\r\n95de\r\n95e6\r\n8\r\n95ee\r\n8\r\n95f6\r\n8\r\n95fe\r\n8\r\n9606\r\n8\r\n960e\r\n8\r\n9616\r\n8\r\n961e\r\n8\r\n9626\r\nc00008\r\n962e\r\n9636\r\n963e\r\n9646\r\n964e\r\n9656\r\n965e\r\n9666\r\n966e\r\n9676\r\n967e\r\n9686\r\n968e\r\n9696\r\n969e\r\n96a6\r\n96ae\r\n96b6\r\n96be\r\n96c6\r\n96ce\r\nBREAK\r\n1\r\n257c6\r\nBREAK\r\n1\r\n47f\r\n92a0\r\n92a2\r\n92a6\r\n92aa\r\n92ae\r\n92b2\r\n92b6\r\n92ba\r\n92be\r\n92c2\r\n92c6\r\n92ca\r\n92ce\r\n92d2\r\n92d6\r\n92da\r\n92de\r\n92e2\r\n92e6\r\n92ea\r\nBREAK\r\n1\r\n257cc\r\nBREAK\r\n1\r\n257d2\r\nBREAK\r\n1\r\n48e\r\n96d6\r\n96d8\r\n96e0\r\n96e8\r\n96f0\r\n96f8\r\n9700\r\n9708\r\n9710\r\n9718\r\n9720\r\n9728\r\n9730\r\n9738\r\n9740\r\n9748\r\n9750\r\n9758\r\n9760\r\n9768\r\n9770\r\n9778\r\n9780\r\n9788\r\n9790\r\n9798\r\n97a0\r\n97a8\r\n97b0\r\n97b8\r\n97c0\r\n97c8\r\nBREAK\r\n1\r\n257d8\r\nBREAK\r\n1\r\n47f\r\n92a0\r\n92a2\r\n92a6\r\n92aa\r\n92ae\r\n92b2\r\n92b6\r\n92ba\r\n92be\r\n92c2\r\n92c6\r\n92ca\r\n92ce\r\n92d2\r\n92d6\r\n92da\r\n92de\r\n92e2\r\n92e6\r\n92ea\r\nBREAK\r\n1\r\n257de\r\nBREAK\r\n1\r\n257e4\r\nBREAK\r\n1\r\n47f\r\n92a0\r\n92a2\r\n92a6\r\n92aa\r\n92ae\r\n92b2\r\n92b6\r\n92ba\r\n92be\r\n92c2\r\n92c6\r\n92ca\r\n92ce\r\n92d2\r\n92d6\r\n92da\r\n92de\r\n92e2\r\n92e6\r\n92ea\r\nBREAK\r\n1\r\n257ea\r\nBREAK\r\n1\r\n257f0\r\nBREAK\r\n1\r\n49d\r\n97f4\r\n97f6\r\n97fe\r\n9802\r\n980a\r\n980e\r\n9816\r\n981a\r\n9822\r\n9826\r\n982e\r\n9832\r\n983a\r\n983e\r\n9846\r\n984a\r\n9852\r\n9856\r\n985e\r\n9862\r\n986a\r\n986e\r\n9876\r\n987a\r\n9882\r\n9886\r\n988e\r\n9892\r\n989a\r\n989e\r\n98a6\r\n98aa\r\n98b2\r\n98b6\r\n98be\r\n98c2\r\n98ca\r\n98ce\r\n98d6\r\n98da\r\n98e2\r\n98e6\r\n98ee\r\n98f2\r\n98fa\r\n98fe\r\n9906\r\n990a\r\n9912\r\n9916\r\n991e\r\n9922\r\n992a\r\n992e\r\n9936\r\n993a\r\n9942\r\n9946\r\n994e\r\n9952\r\n995a\r\n995e\r\n9966\r\nBREAK\r\n1\r\n257f6\r\nBREAK\r\n1\r\n49d\r\n97f4\r\n97f6\r\n97fe\r\n9802\r\n980a\r\n980e\r\n9816\r\n981a\r\n9822\r\n9826\r\n982e\r\n9832\r\n983a\r\n983e\r\n9846\r\n984a\r\n9852\r\n9856\r\n985e\r\n9862\r\n986a\r\n986e\r\n9876\r\n987a\r\n9882\r\n9886\r\n988e\r\n9892\r\n989a\r\n989e\r\n98a6\r\n98aa\r\n98b2\r\n98b6\r\n98be\r\n98c2\r\n98ca\r\n98ce\r\n98d6\r\n98da\r\n98e2\r\n98e6\r\n98ee\r\n98f2\r\n98fa\r\n98fe\r\n9906\r\n990a\r\n9912\r\n9916\r\n991e\r\n9922\r\n992a\r\n992e\r\n9936\r\n993a\r\n9942\r\n9946\r\n994e\r\n9952\r\n995a\r\n995e\r\n9966\r\nBREAK\r\n1\r\n257fc\r\nBREAK\r\n1\r\n4a3\r\n9ae0\r\n9ae5\r\n3009a\r\n9aea\r\n9aef\r\n9af4\r\n9af9\r\n9afe\r\n9b03\r\n0\r\nBREAK\r\n1\r\n25802\r\nBREAK\r\n1\r\n49d\r\n97f4\r\n97f6\r\n97fe\r\n9802\r\n980a\r\n980e\r\n9816\r\n981a\r\n9822\r\n9826\r\n982e\r\n9832\r\n983a\r\n983e\r\n9846\r\n984a\r\n9852\r\n9856\r\n985e\r\n9862\r\n986a\r\n986e\r\n9876\r\n987a\r\n9882\r\n9886\r\n988e\r\n9892\r\n989a\r\n989e\r\n98a6\r\n98aa\r\n98b2\r\n98b6\r\n98be\r\n98c2\r\n98ca\r\n98ce\r\n98d6\r\n98da\r\n98e2\r\n98e6\r\n98ee\r\n98f2\r\n98fa\r\n98fe\r\n9906\r\n990a\r\n9912\r\n9916\r\n991e\r\n9922\r\n992a\r\n992e\r\n9936\r\n993a\r\n9942\r\n9946\r\n994e\r\n9952\r\n995a\r\n995e\r\n9966\r\nBREAK\r\n1\r\n25808\r\nBREAK\r\n1\r\n4a3\r\n9ae0\r\n9ae3\r\n3009a\r\n9ae8\r\n9aed\r\n9af2\r\n9af7\r\n9afc\r\n9b01\r\nBREAK\r\n1\r\n2580e\r\nBREAK\r\n1\r\n49d\r\n97f4\r\n97f6\r\n97fe\r\n9802\r\n980a\r\n980e\r\n9816\r\n981a\r\n9822\r\n9826\r\n982e\r\n9832\r\n983a\r\n983e\r\n9846\r\n984a\r\n9852\r\n9856\r\n985e\r\n9862\r\n986a\r\n986e\r\n9876\r\n987a\r\n9882\r\n9886\r\n988e\r\n9892\r\n989a\r\n989e\r\n98a6\r\n98aa\r\n98b2\r\n98b6\r\n98be\r\n98c2\r\n98ca\r\n98ce\r\n98d6\r\n98da\r\n98e2\r\n98e6\r\n98ee\r\n98f2\r\n98fa\r\n98fe\r\n9906\r\n990a\r\n9912\r\n9916\r\n991e\r\n9922\r\n992a\r\n992e\r\n9936\r\n993a\r\n9942\r\n9946\r\n994e\r\n9952\r\n995a\r\n995e\r\n9966\r\nBREAK\r\n1\r\n25814\r\nBREAK\r\n1\r\n4a3\r\n9ae0\r\n9ae2\r\n3009a\r\n9ae7\r\n9aec\r\n9af1\r\n9af6\r\n9afb\r\n9b00\r\nBREAK\r\n1\r\n2581a\r\nBREAK\r\n1\r\n49d\r\n97f4\r\n97f6\r\n97fe\r\n9802\r\n980a\r\n980e\r\n9816\r\n981a\r\n9822\r\n9826\r\n982e\r\n9832\r\n983a\r\n983e\r\n9846\r\n984a\r\n9852\r\n9856\r\n985e\r\n9862\r\n986a\r\n986e\r\n9876\r\n987a\r\n9882\r\n9886\r\n988e\r\n9892\r\n989a\r\n989e\r\n98a6\r\n98aa\r\n98b2\r\n98b6\r\n98be\r\n98c2\r\n98ca\r\n98ce\r\n98d6\r\n98da\r\n98e2\r\n98e6\r\n98ee\r\n98f2\r\n98fa\r\n98fe\r\n9906\r\n990a\r\n9912\r\n9916\r\n991e\r\n9922\r\n992a\r\n992e\r\n9936\r\n993a\r\n9942\r\n9946\r\n994e\r\n9952\r\n995a\r\n995e\r\n9966\r\nBREAK\r\n1\r\n25820\r\nBREAK\r\n1\r\n4a3\r\n9ae0\r\n9ae2\r\n3009a\r\n9ae7\r\n9aec\r\n9af1\r\n9af6\r\n9afb\r\n9b00\r\nBREAK\r\n1\r\n25826\r\nBREAK\r\n1\r\n49d\r\n97f4\r\n97f6\r\n97fe\r\n9802\r\n980a\r\n980e\r\n9816\r\n981a\r\n9822\r\n9826\r\n982e\r\n9832\r\n983a\r\n983e\r\n9846\r\n984a\r\n9852\r\n9856\r\n985e\r\n9862\r\n986a\r\n986e\r\n9876\r\n987a\r\n9882\r\n9886\r\n988e\r\n9892\r\n989a\r\n989e\r\n98a6\r\n98aa\r\n98b2\r\n98b6\r\n98be\r\n98c2\r\n98ca\r\n98ce\r\n98d6\r\n98da\r\n98e2\r\n98e6\r\n98ee\r\n98f2\r\n98fa\r\n98fe\r\n9906\r\n990a\r\n9912\r\n9916\r\n991e\r\n9922\r\n992a\r\n992e\r\n9936\r\n993a\r\n9942\r\n9946\r\n994e\r\n9952\r\n995a\r\n995e\r\n9966\r\nBREAK\r\n1\r\n2582c\r\nBREAK\r\n1\r\n4a3\r\n9ae0\r\n9ae2\r\n3009a\r\n9ae7\r\n9aec\r\n9af1\r\n9af6\r\n9afb\r\n9b00\r\nBREAK\r\n1\r\n25832\r\nBREAK\r\n1\r\n49d\r\n97f4\r\n97f6\r\n97fe\r\n9802\r\n980a\r\n980e\r\n9816\r\n981a\r\n9822\r\n9826\r\n982e\r\n9832\r\n983a\r\n983e\r\n9846\r\n984a\r\n9852\r\n9856\r\n985e\r\n9862\r\n986a\r\n986e\r\n9876\r\n987a\r\n9882\r\n9886\r\n988e\r\n9892\r\n989a\r\n989e\r\n98a6\r\n98aa\r\n98b2\r\n98b6\r\n98be\r\n98c2\r\n98ca\r\n98ce\r\n98d6\r\n98da\r\n98e2\r\n98e6\r\n98ee\r\n98f2\r\n98fa\r\n98fe\r\n9906\r\n990a\r\n9912\r\n9916\r\n991e\r\n9922\r\n992a\r\n992e\r\n9936\r\n993a\r\n9942\r\n9946\r\n994e\r\n9952\r\n995a\r\n995e\r\n9966\r\nBREAK\r\n1\r\n25838\r\nBREAK\r\n1\r\n4a3\r\n9ae0\r\n9ae2\r\n3009a\r\n9ae7\r\n9aec\r\n9af1\r\n9af6\r\n9afb\r\n9b00\r\nBREAK\r\n1\r\n2583e\r\nBREAK\r\n1\r\n49d\r\n97f4\r\n97f6\r\n97fe\r\n9802\r\n980a\r\n980e\r\n9816\r\n981a\r\n9822\r\n9826\r\n982e\r\n9832\r\n983a\r\n983e\r\n9846\r\n984a\r\n9852\r\n9856\r\n985e\r\n9862\r\n986a\r\n986e\r\n9876\r\n987a\r\n9882\r\n9886\r\n988e\r\n9892\r\n989a\r\n989e\r\n98a6\r\n98aa\r\n98b2\r\n98b6\r\n98be\r\n98c2\r\n98ca\r\n98ce\r\n98d6\r\n98da\r\n98e2\r\n98e6\r\n98ee\r\n98f2\r\n98fa\r\n98fe\r\n9906\r\n990a\r\n9912\r\n9916\r\n991e\r\n9922\r\n992a\r\n992e\r\n9936\r\n993a\r\n9942\r\n9946\r\n994e\r\n9952\r\n995a\r\n995e\r\n9966\r\nBREAK\r\n1\r\n25844\r\nBREAK\r\n1\r\n4a3\r\n9ae0\r\n9ae2\r\n3009a\r\n9ae7\r\n9aec\r\n9af1\r\n9af6\r\n9afb\r\n9b00\r\nBREAK\r\n1\r\n2584a\r\nBREAK\r\n1\r\n49d\r\n97f4\r\n97f6\r\n97fe\r\n9802\r\n980a\r\n980e\r\n9816\r\n981a\r\n9822\r\n9826\r\n982e\r\n9832\r\n983a\r\n983e\r\n9846\r\n984a\r\n9852\r\n9856\r\n985e\r\n9862\r\n986a\r\n986e\r\n9876\r\n987a\r\n9882\r\n9886\r\n988e\r\n9892\r\n989a\r\n989e\r\n98a6\r\n98aa\r\n98b2\r\n98b6\r\n98be\r\n98c2\r\n98ca\r\n98ce\r\n98d6\r\n98da\r\n98e2\r\n98e6\r\n98ee\r\n98f2\r\n98fa\r\n98fe\r\n9906\r\n990a\r\n9912\r\n9916\r\n991e\r\n9922\r\n992a\r\n992e\r\n9936\r\n993a\r\n9942\r\n9946\r\n994e\r\n9952\r\n995a\r\n995e\r\n9966\r\nBREAK\r\n1\r\n25850\r\nBREAK\r\n1\r\n4a3\r\n9ae0\r\n9ae2\r\n3009a\r\n9ae7\r\n9aec\r\n9af1\r\n9af6\r\n9afb\r\n9b00\r\nBREAK\r\n1\r\n25856\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n2585c\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n25862\r\nBREAK\r\n1\r\n4a6\r\n9b05\r\n9b09\r\n9b0d\r\n9b11\r\n9b15\r\n9b19\r\n9b1d\r\n9b21\r\nBREAK\r\n1\r\n25868\r\n100300\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n2586e\r\nBREAK\r\n1\r\n4a6\r\n9b05\r\n9b08\r\n9b0c\r\n9b10\r\n9b14\r\n9b18\r\n9b1c\r\n9b20\r\nBREAK\r\n1\r\n25874\r\n100300\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n2587a\r\nBREAK\r\n1\r\n4a6\r\n9b05\r\n9b07\r\n9b0b\r\n9b0f\r\n9b13\r\n9b17\r\n9b1b\r\n9b1f\r\nBREAK\r\n1\r\n25880\r\n100300\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n25886\r\nBREAK\r\n1\r\n4a6\r\n9b05\r\n9b07\r\n9b0b\r\n9b0f\r\n9b13\r\n9b17\r\n9b1b\r\n9b1f\r\nBREAK\r\n1\r\n2588c\r\n100300\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n25892\r\nBREAK\r\n1\r\n4a6\r\n9b05\r\n9b07\r\n9b0b\r\n9b0f\r\n9b13\r\n9b17\r\n9b1b\r\n9b1f\r\nBREAK\r\n1\r\n25898\r\n100300\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n2589e\r\nBREAK\r\n1\r\n4a6\r\n9b05\r\n9b07\r\n9b0b\r\n9b0f\r\n9b13\r\n9b17\r\n9b1b\r\n9b1f\r\nBREAK\r\n1\r\n258a4\r\n100300\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n258aa\r\nBREAK\r\n1\r\n4a6\r\n9b05\r\n9b07\r\n9b0b\r\n9b0f\r\n9b13\r\n9b17\r\n9b1b\r\n9b1f\r\nBREAK\r\n1\r\n258b0\r\n190300\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n258b6\r\nBREAK\r\n1\r\n4a6\r\n9b05\r\n9b07\r\n9b0b\r\n9b0f\r\n9b13\r\n9b17\r\n9b1b\r\n9b1f\r\nBREAK\r\n1\r\n258bc\r\n260300\r\nBREAK\r\n1\r\n258c2\r\nBREAK\r\n1\r\n4af\r\n9b66\r\n9b68\r\n9b70\r\n9b74\r\n9b7c\r\n9b80\r\n9b88\r\n9b8c\r\n9b94\r\n9b98\r\n9ba0\r\n9ba4\r\n9bac\r\n9bb0\r\n9bb8\r\n9bbc\r\n9bc4\r\n9bc8\r\n9bd0\r\n9bd4\r\n9bdc\r\n9be0\r\n9be8\r\n9bec\r\n9bf4\r\n9bf8\r\n9c00\r\n9c04\r\n9c0c\r\n9c10\r\n9c18\r\n9c1c\r\n9c24\r\n9c28\r\n9c30\r\n9c34\r\n9c3c\r\n9c40\r\n9c48\r\n9c4c\r\n9c54\r\n9c58\r\n9c60\r\n9c64\r\n9c6c\r\n9c70\r\n9c78\r\n9c7c\r\n9c84\r\n9c88\r\n9c90\r\n9c94\r\n9c9c\r\n9ca0\r\n9ca8\r\n9cac\r\n9cb4\r\n9cb8\r\n9cc0\r\n9cc4\r\n9ccc\r\n9cd0\r\n9cd8\r\nBREAK\r\n1\r\n258c8\r\nBREAK\r\n1\r\n4af\r\n9b66\r\n9b68\r\n9b70\r\n9b74\r\n9b7c\r\n9b80\r\n9b88\r\n9b8c\r\n9b94\r\n9b98\r\n9ba0\r\n9ba4\r\n9bac\r\n9bb0\r\n9bb8\r\n9bbc\r\n9bc4\r\n9bc8\r\n9bd0\r\n9bd4\r\n9bdc\r\n9be0\r\n9be8\r\n9bec\r\n9bf4\r\n9bf8\r\n9c00\r\n9c04\r\n9c0c\r\n9c10\r\n9c18\r\n9c1c\r\n9c24\r\n9c28\r\n9c30\r\n9c34\r\n9c3c\r\n9c40\r\n9c48\r\n9c4c\r\n9c54\r\n9c58\r\n9c60\r\n9c64\r\n9c6c\r\n9c70\r\n9c78\r\n9c7c\r\n9c84\r\n9c88\r\n9c90\r\n9c94\r\n9c9c\r\n9ca0\r\n9ca8\r\n9cac\r\n9cb4\r\n9cb8\r\n9cc0\r\n9cc4\r\n9ccc\r\n9cd0\r\n9cd8\r\nBREAK\r\n1\r\n258ce\r\nBREAK\r\n1\r\n258d4\r\nBREAK\r\n1\r\n4b2\r\n9cdc\r\n9cde\r\n9cdf\r\n9ce0\r\n9ce1\r\nBREAK\r\n1\r\n258da\r\nBREAK\r\n1\r\n4af\r\n9b66\r\n9b68\r\n9b70\r\n9b74\r\n9b7c\r\n9b80\r\n9b88\r\n9b8c\r\n9b94\r\n9b98\r\n9ba0\r\n9ba4\r\n9bac\r\n9bb0\r\n9bb8\r\n9bbc\r\n9bc4\r\n9bc8\r\n9bd0\r\n9bd4\r\n9bdc\r\n9be0\r\n9be8\r\n9bec\r\n9bf4\r\n9bf8\r\n9c00\r\n9c04\r\n9c0c\r\n9c10\r\n9c18\r\n9c1c\r\n9c24\r\n9c28\r\n9c30\r\n9c34\r\n9c3c\r\n9c40\r\n9c48\r\n9c4c\r\n9c54\r\n9c58\r\n9c60\r\n9c64\r\n9c6c\r\n9c70\r\n9c78\r\n9c7c\r\n9c84\r\n9c88\r\n9c90\r\n9c94\r\n9c9c\r\n9ca0\r\n9ca8\r\n9cac\r\n9cb4\r\n9cb8\r\n9cc0\r\n9cc4\r\n9ccc\r\n9cd0\r\n9cd8\r\nBREAK\r\n1\r\n258e0\r\nBREAK\r\n1\r\n4af\r\n9b66\r\n9b68\r\n9b70\r\n9b74\r\n9b7c\r\n9b80\r\n9b88\r\n9b8c\r\n9b94\r\n9b98\r\n9ba0\r\n9ba4\r\n9bac\r\n9bb0\r\n9bb8\r\n9bbc\r\n9bc4\r\n9bc8\r\n9bd0\r\n9bd4\r\n9bdc\r\n9be0\r\n9be8\r\n9bec\r\n9bf4\r\n9bf8\r\n9c00\r\n9c04\r\n9c0c\r\n9c10\r\n9c18\r\n9c1c\r\n9c24\r\n9c28\r\n9c30\r\n9c34\r\n9c3c\r\n9c40\r\n9c48\r\n9c4c\r\n9c54\r\n9c58\r\n9c60\r\n9c64\r\n9c6c\r\n9c70\r\n9c78\r\n9c7c\r\n9c84\r\n9c88\r\n9c90\r\n9c94\r\n9c9c\r\n9ca0\r\n9ca8\r\n9cac\r\n9cb4\r\n9cb8\r\n9cc0\r\n9cc4\r\n9ccc\r\n9cd0\r\n9cd8\r\nBREAK\r\n1\r\n258e6\r\nBREAK\r\n1\r\n258ec\r\nBREAK\r\n1\r\n4b2\r\n9cdc\r\n9cde\r\n9cdf\r\n9ce0\r\n9ce1\r\nBREAK\r\n1\r\n258f2\r\nBREAK\r\n1\r\n4af\r\n9b66\r\n9b68\r\n9b70\r\n9b74\r\n9b7c\r\n9b80\r\n9b88\r\n9b8c\r\n9b94\r\n9b98\r\n9ba0\r\n9ba4\r\n9bac\r\n9bb0\r\n9bb8\r\n9bbc\r\n9bc4\r\n9bc8\r\n9bd0\r\n9bd4\r\n9bdc\r\n9be0\r\n9be8\r\n9bec\r\n9bf4\r\n9bf8\r\n9c00\r\n9c04\r\n9c0c\r\n9c10\r\n9c18\r\n9c1c\r\n9c24\r\n9c28\r\n9c30\r\n9c34\r\n9c3c\r\n9c40\r\n9c48\r\n9c4c\r\n9c54\r\n9c58\r\n9c60\r\n9c64\r\n9c6c\r\n9c70\r\n9c78\r\n9c7c\r\n9c84\r\n9c88\r\n9c90\r\n9c94\r\n9c9c\r\n9ca0\r\n9ca8\r\n9cac\r\n9cb4\r\n9cb8\r\n9cc0\r\n9cc4\r\n9ccc\r\n9cd0\r\n9cd8\r\nBREAK\r\n1\r\n258f8\r\nBREAK\r\n1\r\n4af\r\n9b66\r\n9b68\r\n9b70\r\n9b74\r\n9b7c\r\n9b80\r\n9b88\r\n9b8c\r\n9b94\r\n9b98\r\n9ba0\r\n9ba4\r\n9bac\r\n9bb0\r\n9bb8\r\n9bbc\r\n9bc4\r\n9bc8\r\n9bd0\r\n9bd4\r\n9bdc\r\n9be0\r\n9be8\r\n9bec\r\n9bf4\r\n9bf8\r\n9c00\r\n9c04\r\n9c0c\r\n9c10\r\n9c18\r\n9c1c\r\n9c24\r\n9c28\r\n9c30\r\n9c34\r\n9c3c\r\n9c40\r\n9c48\r\n9c4c\r\n9c54\r\n9c58\r\n9c60\r\n9c64\r\n9c6c\r\n9c70\r\n9c78\r\n9c7c\r\n9c84\r\n9c88\r\n9c90\r\n9c94\r\n9c9c\r\n9ca0\r\n9ca8\r\n9cac\r\n9cb4\r\n9cb8\r\n9cc0\r\n9cc4\r\n9ccc\r\n9cd0\r\n9cd8\r\nBREAK\r\n1\r\n258fe\r\nBREAK\r\n1\r\n25904\r\nBREAK\r\n1\r\n4b2\r\n9cdc\r\n9cde\r\n9cdf\r\n9ce0\r\n9ce1\r\nBREAK\r\n1\r\n2590a\r\nBREAK\r\n1\r\n25910\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25916\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n2591c\r\nBREAK\r\n1\r\n25922\r\nBREAK\r\n1\r\n25928\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n2592e\r\nBREAK\r\n1\r\n25934\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n2593a\r\nBREAK\r\n1\r\n25940\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25946\r\nBREAK\r\n1\r\n2594c\r\nBREAK\r\n1\r\n25952\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25958\r\nBREAK\r\n1\r\n2595e\r\nBREAK\r\n1\r\n25964\r\nBREAK\r\n1\r\n2596a\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25970\r\nBREAK\r\n1\r\n25976\r\nBREAK\r\n1\r\n2597c\r\nBREAK\r\n1\r\n25982\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25988\r\nBREAK\r\n1\r\n2598e\r\nBREAK\r\n1\r\n25994\r\nBREAK\r\n1\r\n2599a\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n259a0\r\nBREAK\r\n1\r\n259a6\r\nBREAK\r\n1\r\n259ac\r\nBREAK\r\n1\r\n259b2\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n259b8\r\nBREAK\r\n1\r\n259be\r\nBREAK\r\n1\r\n259c4\r\nBREAK\r\n1\r\n259ca\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n259d0\r\nBREAK\r\n1\r\n259d6\r\nBREAK\r\n1\r\n259dc\r\nBREAK\r\n1\r\n259e2\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n259e8\r\nBREAK\r\n1\r\n259ee\r\nBREAK\r\n1\r\n259f4\r\nBREAK\r\n1\r\n259fa\r\nBREAK\r\n1\r\n25a00\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25a06\r\nBREAK\r\n1\r\n25a0c\r\nBREAK\r\n1\r\n25a12\r\nBREAK\r\n1\r\n25a18\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25a1e\r\nBREAK\r\n1\r\n25a24\r\nBREAK\r\n1\r\n25a2a\r\nBREAK\r\n1\r\n25a30\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25a36\r\nBREAK\r\n1\r\n25a3c\r\nBREAK\r\n1\r\n25a42\r\nBREAK\r\n1\r\n25a48\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25a4e\r\nBREAK\r\n1\r\n25a54\r\nBREAK\r\n1\r\n25a5a\r\nBREAK\r\n1\r\n25a60\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25a66\r\nBREAK\r\n1\r\n25a6c\r\nBREAK\r\n1\r\n25a72\r\nBREAK\r\n1\r\n25a78\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25a7e\r\nBREAK\r\n1\r\n25a84\r\nBREAK\r\n1\r\n25a8a\r\nBREAK\r\n1\r\n25a90\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25a96\r\nBREAK\r\n1\r\n25a9c\r\nBREAK\r\n1\r\n25aa2\r\nBREAK\r\n1\r\n25aa8\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25aae\r\nBREAK\r\n1\r\n25ab4\r\nBREAK\r\n1\r\n25aba\r\nBREAK\r\n1\r\n25ac0\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25ac6\r\nBREAK\r\n1\r\n25acc\r\nBREAK\r\n1\r\n25ad2\r\nBREAK\r\n1\r\n25ad8\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25ade\r\nBREAK\r\n1\r\n25ae4\r\nBREAK\r\n1\r\n25aea\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25af0\r\nBREAK\r\n1\r\n25af6\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25afc\r\nBREAK\r\n1\r\n25b02\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25b08\r\nBREAK\r\n1\r\n25b0e\r\nBREAK\r\n1\r\n4d9\r\na48c\r\na48e\r\na496\r\na49a\r\na4a2\r\na4a6\r\na4ae\r\na4b2\r\na4ba\r\na4be\r\na4c6\r\na4ca\r\na4d2\r\na4d6\r\na4de\r\na4e2\r\na4ea\r\na4ee\r\na4f6\r\na4fa\r\na502\r\na506\r\na50e\r\na512\r\na51a\r\na51e\r\na526\r\na52a\r\na532\r\na536\r\na53e\r\na542\r\na54a\r\na54e\r\na556\r\na55a\r\na562\r\na566\r\na56e\r\na572\r\na57a\r\na57e\r\na586\r\na58a\r\na592\r\na596\r\na59e\r\na5a2\r\na5aa\r\na5ae\r\na5b6\r\na5ba\r\na5c2\r\na5c6\r\na5ce\r\na5d2\r\na5da\r\na5de\r\na5e6\r\na5ea\r\na5f2\r\na5f6\r\na5fe\r\nBREAK\r\n1\r\n25b14\r\nBREAK\r\n1\r\n25b1a\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25b20\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25b26\r\nBREAK\r\n1\r\n25b2c\r\nBREAK\r\n1\r\n25b32\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25b38\r\nBREAK\r\n1\r\n25b3e\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25b44\r\nBREAK\r\n1\r\n25b4a\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25b50\r\nBREAK\r\n1\r\n25b56\r\nBREAK\r\n1\r\n25b5c\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25b62\r\nBREAK\r\n1\r\n25b68\r\nBREAK\r\n1\r\n25b6e\r\nBREAK\r\n1\r\n25b74\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25b7a\r\nBREAK\r\n1\r\n25b80\r\nBREAK\r\n1\r\n25b86\r\nBREAK\r\n1\r\n25b8c\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25b92\r\nBREAK\r\n1\r\n25b98\r\nBREAK\r\n1\r\n25b9e\r\nBREAK\r\n1\r\n25ba4\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25baa\r\nBREAK\r\n1\r\n25bb0\r\nBREAK\r\n1\r\n25bb6\r\nBREAK\r\n1\r\n25bbc\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25bc2\r\nBREAK\r\n1\r\n25bc8\r\nBREAK\r\n1\r\n25bce\r\nBREAK\r\n1\r\n25bd4\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25bda\r\nBREAK\r\n1\r\n25be0\r\nBREAK\r\n1\r\n25be6\r\nBREAK\r\n1\r\n25bec\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25bf2\r\nBREAK\r\n1\r\n25bf8\r\nBREAK\r\n1\r\n25bfe\r\nBREAK\r\n1\r\n25c04\r\nBREAK\r\n1\r\n25c0a\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25c10\r\nBREAK\r\n1\r\n25c16\r\nBREAK\r\n1\r\n25c1c\r\nBREAK\r\n1\r\n25c22\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25c28\r\nBREAK\r\n1\r\n25c2e\r\nBREAK\r\n1\r\n25c34\r\nBREAK\r\n1\r\n25c3a\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25c40\r\nBREAK\r\n1\r\n25c46\r\nBREAK\r\n1\r\n25c4c\r\nBREAK\r\n1\r\n25c52\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25c58\r\nBREAK\r\n1\r\n25c5e\r\nBREAK\r\n1\r\n25c64\r\nBREAK\r\n1\r\n25c6a\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25c70\r\nBREAK\r\n1\r\n25c76\r\nBREAK\r\n1\r\n25c7c\r\nBREAK\r\n1\r\n25c82\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25c88\r\nBREAK\r\n1\r\n25c8e\r\nBREAK\r\n1\r\n25c94\r\nBREAK\r\n1\r\n25c9a\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25ca0\r\nBREAK\r\n1\r\n25ca6\r\nBREAK\r\n1\r\n25cac\r\nBREAK\r\n1\r\n25cb2\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25cb8\r\nBREAK\r\n1\r\n25cbe\r\nBREAK\r\n1\r\n25cc4\r\nBREAK\r\n1\r\n25cca\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25cd0\r\nBREAK\r\n1\r\n25cd6\r\nBREAK\r\n1\r\n25cdc\r\nBREAK\r\n1\r\n25ce2\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25ce8\r\nBREAK\r\n1\r\n25cee\r\nBREAK\r\n1\r\n25cf4\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25cfa\r\nBREAK\r\n1\r\n25d00\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25d06\r\nBREAK\r\n1\r\n25d0c\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25d12\r\nBREAK\r\n1\r\n25d18\r\nBREAK\r\n1\r\n4dc\r\na602\r\na604\r\na60c\r\na610\r\na618\r\na61c\r\na624\r\na628\r\na630\r\na634\r\na63c\r\na640\r\na648\r\na64c\r\na654\r\na658\r\na660\r\na664\r\na66c\r\na670\r\na678\r\na67c\r\na684\r\na688\r\na690\r\na694\r\na69c\r\na6a0\r\na6a8\r\na6ac\r\na6b4\r\na6b8\r\na6c0\r\na6c4\r\na6cc\r\na6d0\r\na6d8\r\na6dc\r\na6e4\r\na6e8\r\na6f0\r\na6f4\r\na6fc\r\na700\r\na708\r\na70c\r\na714\r\na718\r\na720\r\na724\r\na72c\r\na730\r\na738\r\na73c\r\na744\r\na748\r\na750\r\na754\r\na75c\r\na760\r\na768\r\na76c\r\na774\r\nBREAK\r\n1\r\n25d1e\r\nBREAK\r\n1\r\n25d24\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25d2a\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25d30\r\nBREAK\r\n1\r\n25d36\r\nBREAK\r\n1\r\n25d3c\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25d42\r\nBREAK\r\n1\r\n25d48\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25d4e\r\nBREAK\r\n1\r\n25d54\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25d5a\r\nBREAK\r\n1\r\n25d60\r\nBREAK\r\n1\r\n25d66\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25d6c\r\nBREAK\r\n1\r\n25d72\r\nBREAK\r\n1\r\n25d78\r\nBREAK\r\n1\r\n25d7e\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25d84\r\nBREAK\r\n1\r\n25d8a\r\nBREAK\r\n1\r\n25d90\r\nBREAK\r\n1\r\n25d96\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25d9c\r\nBREAK\r\n1\r\n25da2\r\nBREAK\r\n1\r\n25da8\r\nBREAK\r\n1\r\n25dae\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25db4\r\nBREAK\r\n1\r\n25dba\r\nBREAK\r\n1\r\n25dc0\r\nBREAK\r\n1\r\n25dc6\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25dcc\r\nBREAK\r\n1\r\n25dd2\r\nBREAK\r\n1\r\n25dd8\r\nBREAK\r\n1\r\n25dde\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25de4\r\nBREAK\r\n1\r\n25dea\r\nBREAK\r\n1\r\n25df0\r\nBREAK\r\n1\r\n25df6\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25dfc\r\nBREAK\r\n1\r\n25e02\r\nBREAK\r\n1\r\n25e08\r\nBREAK\r\n1\r\n25e0e\r\nBREAK\r\n1\r\n25e14\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25e1a\r\nBREAK\r\n1\r\n25e20\r\nBREAK\r\n1\r\n25e26\r\nBREAK\r\n1\r\n25e2c\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25e32\r\nBREAK\r\n1\r\n25e38\r\nBREAK\r\n1\r\n25e3e\r\nBREAK\r\n1\r\n25e44\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25e4a\r\nBREAK\r\n1\r\n25e50\r\nBREAK\r\n1\r\n25e56\r\nBREAK\r\n1\r\n25e5c\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25e62\r\nBREAK\r\n1\r\n25e68\r\nBREAK\r\n1\r\n25e6e\r\nBREAK\r\n1\r\n25e74\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25e7a\r\nBREAK\r\n1\r\n25e80\r\nBREAK\r\n1\r\n25e86\r\nBREAK\r\n1\r\n25e8c\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25e92\r\nBREAK\r\n1\r\n25e98\r\nBREAK\r\n1\r\n25e9e\r\nBREAK\r\n1\r\n25ea4\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25eaa\r\nBREAK\r\n1\r\n25eb0\r\nBREAK\r\n1\r\n25eb6\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25ebc\r\nBREAK\r\n1\r\n25ec2\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25ec8\r\nBREAK\r\n1\r\n25ece\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25ed4\r\nBREAK\r\n1\r\n25eda\r\nBREAK\r\n1\r\n4df\r\na778\r\na77a\r\na782\r\na786\r\na78e\r\na792\r\na79a\r\na79e\r\na7a6\r\na7aa\r\na7b2\r\na7b6\r\na7be\r\na7c2\r\na7ca\r\na7ce\r\na7d6\r\na7da\r\na7e2\r\na7e6\r\na7ee\r\na7f2\r\na7fa\r\na7fe\r\na806\r\na80a\r\na812\r\na816\r\na81e\r\na822\r\na82a\r\na82e\r\na836\r\na83a\r\na842\r\na846\r\na84e\r\na852\r\na85a\r\na85e\r\na866\r\na86a\r\na872\r\na876\r\na87e\r\na882\r\na88a\r\na88e\r\na896\r\na89a\r\na8a2\r\na8a6\r\na8ae\r\na8b2\r\na8ba\r\na8be\r\na8c6\r\na8ca\r\na8d2\r\na8d6\r\na8de\r\na8e2\r\na8ea\r\nBREAK\r\n1\r\n25ee0\r\nBREAK\r\n1\r\n25ee6\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n25eec\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n25ef2\r\nBREAK\r\n1\r\n25ef8\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n25efe\r\nBREAK\r\n1\r\n25f04\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n25f0a\r\nBREAK\r\n1\r\n25f10\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n25f16\r\nBREAK\r\n1\r\n25f1c\r\nBREAK\r\n1\r\n25f22\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n25f28\r\nBREAK\r\n1\r\n25f2e\r\nBREAK\r\n1\r\n25f34\r\nBREAK\r\n1\r\n25f3a\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n25f40\r\nBREAK\r\n1\r\n25f46\r\nBREAK\r\n1\r\n25f4c\r\nBREAK\r\n1\r\n25f52\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n25f58\r\nBREAK\r\n1\r\n25f5e\r\nBREAK\r\n1\r\n25f64\r\nBREAK\r\n1\r\n25f6a\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n25f70\r\nBREAK\r\n1\r\n25f76\r\nBREAK\r\n1\r\n25f7c\r\nBREAK\r\n1\r\n25f82\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n25f88\r\nBREAK\r\n1\r\n25f8e\r\nBREAK\r\n1\r\n25f94\r\nBREAK\r\n1\r\n25f9a\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa67\r\naa6f\r\naa73\r\naa7b\r\naa7f\r\naa87\r\naa8b\r\naa93\r\naa97\r\naa9f\r\naaa3\r\naaab\r\naaaf\r\naab7\r\naabb\r\naac3\r\naac7\r\naacf\r\naad3\r\naadb\r\naadf\r\naae7\r\naaeb\r\naaf3\r\naaf7\r\naaff\r\nab03\r\n0\r\nab0b\r\nab0f\r\nab17\r\nab1b\r\nab23\r\nab27\r\nab2f\r\nab33\r\nab3b\r\nab3f\r\nab47\r\nab4b\r\nab53\r\nab57\r\nab5f\r\nab63\r\nab6b\r\nab6f\r\nab77\r\nab7b\r\nab83\r\nab87\r\nab8f\r\nab93\r\nab9b\r\nab9f\r\naba7\r\nabab\r\nabb3\r\nabb7\r\nabbf\r\nabc3\r\nabcb\r\nabcf\r\nabd7\r\nBREAK\r\n1\r\n25fa0\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n25fa6\r\nBREAK\r\n1\r\n25fac\r\nBREAK\r\n1\r\n25fb2\r\nBREAK\r\n1\r\n25fb8\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa68\r\naa70\r\naa74\r\naa7c\r\naa80\r\naa88\r\naa8c\r\naa94\r\naa98\r\naaa0\r\naaa4\r\naaac\r\naab0\r\naab8\r\naabc\r\naac4\r\naac8\r\naad0\r\naad4\r\naadc\r\naae0\r\naae8\r\naaec\r\naaf4\r\naaf8\r\nab00\r\nab04\r\nab0c\r\nab10\r\nab18\r\nab1c\r\nab24\r\nab28\r\nab30\r\nab34\r\nab3c\r\nab40\r\nab48\r\nab4c\r\nab54\r\nab58\r\nab60\r\nab64\r\nab6c\r\nab70\r\nab78\r\nab7c\r\nab84\r\nab88\r\nab90\r\nab94\r\nab9c\r\naba0\r\naba8\r\nabac\r\nabb4\r\nabb8\r\nabc0\r\nabc4\r\nabcc\r\nabd0\r\nabd8\r\nBREAK\r\n1\r\n25fbe\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n25fc4\r\nBREAK\r\n1\r\n25fca\r\nBREAK\r\n1\r\n25fd0\r\nBREAK\r\n1\r\n25fd6\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa69\r\naa71\r\naa75\r\naa7d\r\naa81\r\naa89\r\naa8d\r\naa95\r\naa99\r\naaa1\r\naaa5\r\naaad\r\naab1\r\naab9\r\naabd\r\naac5\r\naac9\r\naad1\r\naad5\r\naadd\r\naae1\r\naae9\r\naaed\r\naaf5\r\naaf9\r\nab01\r\nab05\r\nab0d\r\nab11\r\nab19\r\nab1d\r\nab25\r\nab29\r\nab31\r\nab35\r\nab3d\r\nab41\r\nab49\r\nab4d\r\nab55\r\nab59\r\nab61\r\nab65\r\nab6d\r\nab71\r\nab79\r\nab7d\r\nab85\r\nab89\r\nab91\r\nab95\r\nab9d\r\naba1\r\naba9\r\nabad\r\nabb5\r\nabb9\r\nabc1\r\nabc5\r\nabcd\r\nabd1\r\nabd9\r\nBREAK\r\n1\r\n25fdc\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n25fe2\r\nBREAK\r\n1\r\n25fe8\r\nBREAK\r\n1\r\n25fee\r\nBREAK\r\n1\r\n25ff4\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa6a\r\naa72\r\naa76\r\naa7e\r\naa82\r\naa8a\r\naa8e\r\naa96\r\naa9a\r\naaa2\r\naaa6\r\naaae\r\naab2\r\naaba\r\naabe\r\naac6\r\naaca\r\naad2\r\naad6\r\naade\r\naae2\r\naaea\r\naaee\r\naaf6\r\naafa\r\nab02\r\nab06\r\nab0e\r\nab12\r\nab1a\r\nab1e\r\nab26\r\nab2a\r\nab32\r\nab36\r\nab3e\r\nab42\r\nab4a\r\nab4e\r\nab56\r\nab5a\r\nab62\r\nab66\r\nab6e\r\nab72\r\nab7a\r\nab7e\r\nab86\r\nab8a\r\nab92\r\nab96\r\nab9e\r\naba2\r\nabaa\r\nabae\r\nabb6\r\nabba\r\nabc2\r\nabc6\r\nabce\r\nabd2\r\nabda\r\nBREAK\r\n1\r\n25ffa\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n26000\r\nBREAK\r\n1\r\n26006\r\nBREAK\r\n1\r\n2600c\r\nBREAK\r\n1\r\n26012\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa6b\r\naa73\r\naa77\r\naa7f\r\naa83\r\naa8b\r\naa8f\r\naa97\r\naa9b\r\naaa3\r\naaa7\r\naaaf\r\naab3\r\naabb\r\naabf\r\naac7\r\naacb\r\naad3\r\naad7\r\naadf\r\naae3\r\naaeb\r\naaef\r\naaf7\r\naafb\r\nab03\r\n0\r\nab07\r\nab0f\r\nab13\r\nab1b\r\nab1f\r\nab27\r\nab2b\r\nab33\r\nab37\r\nab3f\r\nab43\r\nab4b\r\nab4f\r\nab57\r\nab5b\r\nab63\r\nab67\r\nab6f\r\nab73\r\nab7b\r\nab7f\r\nab87\r\nab8b\r\nab93\r\nab97\r\nab9f\r\naba3\r\nabab\r\nabaf\r\nabb7\r\nabbb\r\nabc3\r\nabc7\r\nabcf\r\nabd3\r\nabdb\r\nBREAK\r\n1\r\n26018\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n2601e\r\nBREAK\r\n1\r\n26024\r\nBREAK\r\n1\r\n2602a\r\nBREAK\r\n1\r\n26030\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa6c\r\naa74\r\naa78\r\naa80\r\naa84\r\naa8c\r\naa90\r\naa98\r\naa9c\r\naaa4\r\naaa8\r\naab0\r\naab4\r\naabc\r\naac0\r\naac8\r\naacc\r\naad4\r\naad8\r\naae0\r\naae4\r\naaec\r\naaf0\r\naaf8\r\naafc\r\nab04\r\nab08\r\nab10\r\nab14\r\nab1c\r\nab20\r\nab28\r\nab2c\r\nab34\r\nab38\r\nab40\r\nab44\r\nab4c\r\nab50\r\nab58\r\nab5c\r\nab64\r\nab68\r\nab70\r\nab74\r\nab7c\r\nab80\r\nab88\r\nab8c\r\nab94\r\nab98\r\naba0\r\naba4\r\nabac\r\nabb0\r\nabb8\r\nabbc\r\nabc4\r\nabc8\r\nabd0\r\nabd4\r\nabdc\r\nBREAK\r\n1\r\n26036\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n2603c\r\nBREAK\r\n1\r\n26042\r\nBREAK\r\n1\r\n26048\r\nBREAK\r\n1\r\n2604e\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa6d\r\naa75\r\naa79\r\naa81\r\naa85\r\naa8d\r\naa91\r\naa99\r\naa9d\r\naaa5\r\naaa9\r\naab1\r\naab5\r\naabd\r\naac1\r\naac9\r\naacd\r\naad5\r\naad9\r\naae1\r\naae5\r\naaed\r\naaf1\r\naaf9\r\naafd\r\nab05\r\nab09\r\nab11\r\nab15\r\nab1d\r\nab21\r\nab29\r\nab2d\r\nab35\r\nab39\r\nab41\r\nab45\r\nab4d\r\nab51\r\nab59\r\nab5d\r\nab65\r\nab69\r\nab71\r\nab75\r\nab7d\r\nab81\r\nab89\r\nab8d\r\nab95\r\nab99\r\naba1\r\naba5\r\nabad\r\nabb1\r\nabb9\r\nabbd\r\nabc5\r\nabc9\r\nabd1\r\nabd5\r\nabdd\r\nBREAK\r\n1\r\n26054\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n2605a\r\nBREAK\r\n1\r\n26060\r\nBREAK\r\n1\r\n26066\r\nBREAK\r\n1\r\n2606c\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa6e\r\naa76\r\naa7a\r\naa82\r\naa86\r\naa8e\r\naa92\r\naa9a\r\naa9e\r\naaa6\r\naaaa\r\naab2\r\naab6\r\naabe\r\naac2\r\naaca\r\naace\r\naad6\r\naada\r\naae2\r\naae6\r\naaee\r\naaf2\r\naafa\r\naafe\r\nab06\r\nab0a\r\nab12\r\nab16\r\nab1e\r\nab22\r\nab2a\r\nab2e\r\nab36\r\nab3a\r\nab42\r\nab46\r\nab4e\r\nab52\r\nab5a\r\nab5e\r\nab66\r\nab6a\r\nab72\r\nab76\r\nab7e\r\nab82\r\nab8a\r\nab8e\r\nab96\r\nab9a\r\naba2\r\naba6\r\nabae\r\nabb2\r\nabba\r\nabbe\r\nabc6\r\nabca\r\nabd2\r\nabd6\r\nabde\r\nBREAK\r\n1\r\n26072\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n26078\r\nBREAK\r\n1\r\n2607e\r\nBREAK\r\n1\r\n26084\r\nBREAK\r\n1\r\n2608a\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa6f\r\naa77\r\naa7b\r\naa83\r\naa87\r\naa8f\r\naa93\r\naa9b\r\naa9f\r\naaa7\r\naaab\r\naab3\r\naab7\r\naabf\r\naac3\r\naacb\r\naacf\r\naad7\r\naadb\r\naae3\r\naae7\r\naaef\r\naaf3\r\naafb\r\naaff\r\nab07\r\nab0b\r\nab13\r\nab17\r\nab1f\r\nab23\r\nab2b\r\nab2f\r\nab37\r\nab3b\r\nab43\r\nab47\r\nab4f\r\nab53\r\nab5b\r\nab5f\r\nab67\r\nab6b\r\nab73\r\nab77\r\nab7f\r\nab83\r\nab8b\r\nab8f\r\nab97\r\nab9b\r\naba3\r\naba7\r\nabaf\r\nabb3\r\nabbb\r\nabbf\r\nabc7\r\nabcb\r\nabd3\r\nabd7\r\nabdf\r\nBREAK\r\n1\r\n26090\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n26096\r\nBREAK\r\n1\r\n2609c\r\nBREAK\r\n1\r\n260a2\r\nBREAK\r\n1\r\n260a8\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa70\r\naa78\r\naa7c\r\naa84\r\naa88\r\naa90\r\naa94\r\naa9c\r\naaa0\r\naaa8\r\naaac\r\naab4\r\naab8\r\naac0\r\naac4\r\naacc\r\naad0\r\naad8\r\naadc\r\naae4\r\naae8\r\naaf0\r\naaf4\r\naafc\r\nab00\r\nab08\r\nab0c\r\nab14\r\nab18\r\nab20\r\nab24\r\nab2c\r\nab30\r\nab38\r\nab3c\r\nab44\r\nab48\r\nab50\r\nab54\r\nab5c\r\nab60\r\nab68\r\nab6c\r\nab74\r\nab78\r\nab80\r\nab84\r\nab8c\r\nab90\r\nab98\r\nab9c\r\naba4\r\naba8\r\nabb0\r\nabb4\r\nabbc\r\nabc0\r\nabc8\r\nabcc\r\nabd4\r\nabd8\r\nabe0\r\nBREAK\r\n1\r\n260ae\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n260b4\r\nBREAK\r\n1\r\n260ba\r\nBREAK\r\n1\r\n260c0\r\nBREAK\r\n1\r\n260c6\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa71\r\naa79\r\naa7d\r\naa85\r\naa89\r\naa91\r\naa95\r\naa9d\r\naaa1\r\naaa9\r\naaad\r\naab5\r\naab9\r\naac1\r\naac5\r\naacd\r\naad1\r\naad9\r\naadd\r\naae5\r\naae9\r\naaf1\r\naaf5\r\naafd\r\nab01\r\nab09\r\nab0d\r\nab15\r\nab19\r\nab21\r\nab25\r\nab2d\r\nab31\r\nab39\r\nab3d\r\nab45\r\nab49\r\nab51\r\nab55\r\nab5d\r\nab61\r\nab69\r\nab6d\r\nab75\r\nab79\r\nab81\r\nab85\r\nab8d\r\nab91\r\nab99\r\nab9d\r\naba5\r\naba9\r\nabb1\r\nabb5\r\nabbd\r\nabc1\r\nabc9\r\nabcd\r\nabd5\r\nabd9\r\nabe1\r\nBREAK\r\n1\r\n260cc\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n260d2\r\nBREAK\r\n1\r\n260d8\r\nBREAK\r\n1\r\n260de\r\nBREAK\r\n1\r\n260e4\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n260ea\r\nBREAK\r\n1\r\n260f0\r\nBREAK\r\n1\r\n260f6\r\nBREAK\r\n1\r\n260fc\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n26102\r\nBREAK\r\n1\r\n26108\r\nBREAK\r\n1\r\n2610e\r\nBREAK\r\n1\r\n26114\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n2611a\r\nBREAK\r\n1\r\n26120\r\nBREAK\r\n1\r\n26126\r\nBREAK\r\n1\r\n2612c\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n26132\r\nBREAK\r\n1\r\n26138\r\nBREAK\r\n1\r\n2613e\r\nBREAK\r\n1\r\n26144\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n2614a\r\nBREAK\r\n1\r\n26150\r\nBREAK\r\n1\r\n26156\r\nBREAK\r\n1\r\n2615c\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n26162\r\nBREAK\r\n1\r\n26168\r\nBREAK\r\n1\r\n2616e\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n26174\r\nBREAK\r\n1\r\n2617a\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n26180\r\nBREAK\r\n1\r\n26186\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n2618c\r\nBREAK\r\n1\r\n26192\r\nBREAK\r\n1\r\n4e5\r\naa64\r\naa66\r\naa6e\r\naa72\r\naa7a\r\naa7e\r\naa86\r\naa8a\r\naa92\r\naa96\r\naa9e\r\naaa2\r\naaaa\r\naaae\r\naab6\r\naaba\r\naac2\r\naac6\r\naace\r\naad2\r\naada\r\naade\r\naae6\r\naaea\r\naaf2\r\naaf6\r\naafe\r\nab02\r\nab0a\r\nab0e\r\nab16\r\nab1a\r\nab22\r\nab26\r\nab2e\r\nab32\r\nab3a\r\nab3e\r\nab46\r\nab4a\r\nab52\r\nab56\r\nab5e\r\nab62\r\nab6a\r\nab6e\r\nab76\r\nab7a\r\nab82\r\nab86\r\nab8e\r\nab92\r\nab9a\r\nab9e\r\naba6\r\nabaa\r\nabb2\r\nabb6\r\nabbe\r\nabc2\r\nabca\r\nabce\r\nabd6\r\nBREAK\r\n1\r\n26198\r\nBREAK\r\n1\r\n2619e\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n261a4\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n261aa\r\nBREAK\r\n1\r\n261b0\r\nBREAK\r\n1\r\n261b6\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n261bc\r\nBREAK\r\n1\r\n261c2\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n261c8\r\nBREAK\r\n1\r\n261ce\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n261d4\r\nBREAK\r\n1\r\n261da\r\nBREAK\r\n1\r\n261e0\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n261e6\r\nBREAK\r\n1\r\n261ec\r\nBREAK\r\n1\r\n261f2\r\nBREAK\r\n1\r\n261f8\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n261fe\r\nBREAK\r\n1\r\n26204\r\nBREAK\r\n1\r\n2620a\r\nBREAK\r\n1\r\n26210\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n26216\r\nBREAK\r\n1\r\n2621c\r\nBREAK\r\n1\r\n26222\r\nBREAK\r\n1\r\n26228\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n2622e\r\nBREAK\r\n1\r\n26234\r\nBREAK\r\n1\r\n2623a\r\nBREAK\r\n1\r\n26240\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n26246\r\nBREAK\r\n1\r\n2624c\r\nBREAK\r\n1\r\n26252\r\nBREAK\r\n1\r\n26258\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n2625e\r\nBREAK\r\n1\r\n26264\r\nBREAK\r\n1\r\n2626a\r\nBREAK\r\n1\r\n26270\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n26276\r\nBREAK\r\n1\r\n2627c\r\nBREAK\r\n1\r\n26282\r\nBREAK\r\n1\r\n26288\r\nBREAK\r\n1\r\n2628e\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n26294\r\nBREAK\r\n1\r\n2629a\r\nBREAK\r\n1\r\n262a0\r\nBREAK\r\n1\r\n262a6\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n262ac\r\nBREAK\r\n1\r\n262b2\r\nBREAK\r\n1\r\n262b8\r\nBREAK\r\n1\r\n262be\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n262c4\r\nBREAK\r\n1\r\n262ca\r\nBREAK\r\n1\r\n262d0\r\nBREAK\r\n1\r\n262d6\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n262dc\r\nBREAK\r\n1\r\n262e2\r\nBREAK\r\n1\r\n262e8\r\nBREAK\r\n1\r\n262ee\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n262f4\r\nBREAK\r\n1\r\n262fa\r\nBREAK\r\n1\r\n26300\r\nBREAK\r\n1\r\n26306\r\nBREAK\r\n1\r\n2630c\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n26312\r\nBREAK\r\n1\r\n26318\r\nBREAK\r\n1\r\n2631e\r\nBREAK\r\n1\r\n26324\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n2632a\r\nBREAK\r\n1\r\n26330\r\nBREAK\r\n1\r\n26336\r\nBREAK\r\n1\r\n2633c\r\nBREAK\r\n1\r\n26342\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n26348\r\nBREAK\r\n1\r\n2634e\r\nBREAK\r\n1\r\n26354\r\nBREAK\r\n1\r\n2635a\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n26360\r\nBREAK\r\n1\r\n26366\r\nBREAK\r\n1\r\n2636c\r\nBREAK\r\n1\r\n26372\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n26378\r\nBREAK\r\n1\r\n2637e\r\nBREAK\r\n1\r\n26384\r\nBREAK\r\n1\r\n2638a\r\nBREAK\r\n1\r\n26390\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n26396\r\nBREAK\r\n1\r\n2639c\r\nBREAK\r\n1\r\n263a2\r\nBREAK\r\n1\r\n263a8\r\nBREAK\r\n1\r\n4e2\r\na8ee\r\na8f0\r\na8f8\r\na8fc\r\na904\r\na908\r\na910\r\na914\r\na91c\r\na920\r\na928\r\na92c\r\na934\r\na938\r\na940\r\na944\r\na94c\r\na950\r\na958\r\na95c\r\na964\r\na968\r\na970\r\na974\r\na97c\r\na980\r\na988\r\na98c\r\na994\r\na998\r\na9a0\r\na9a4\r\na9ac\r\na9b0\r\na9b8\r\na9bc\r\na9c4\r\na9c8\r\na9d0\r\na9d4\r\na9dc\r\na9e0\r\na9e8\r\na9ec\r\na9f4\r\na9f8\r\naa00\r\naa04\r\naa0c\r\naa10\r\naa18\r\naa1c\r\naa24\r\naa28\r\naa30\r\naa34\r\naa3c\r\naa40\r\naa48\r\naa4c\r\naa54\r\naa58\r\naa60\r\nBREAK\r\n1\r\n263ae\r\nBREAK\r\n1\r\n263b4\r\nBREAK\r\n1\r\n263ba\r\nBREAK\r\n1\r\n263c0\r\nBREAK\r\n1\r\n263c6\r\nBREAK\r\n1\r\n263cc\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n263d2\r\nBREAK\r\n1\r\n4a9\r\n9b23\r\n9b25\r\n9b29\r\n9b2d\r\n9b31\r\n9b35\r\n9b39\r\n9b3d\r\nBREAK\r\n1\r\n263d8\r\n200300\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n263de\r\nBREAK\r\n1\r\n4a9\r\n9b23\r\n9b25\r\n9b29\r\n9b2d\r\n9b31\r\n9b35\r\n9b39\r\n9b3d\r\nBREAK\r\n1\r\n263e4\r\n100300\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n263ea\r\nBREAK\r\n1\r\n4a9\r\n9b23\r\n9b25\r\n9b29\r\n9b2d\r\n9b31\r\n9b35\r\n9b39\r\n9b3d\r\nBREAK\r\n1\r\n263f0\r\n100300\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n263f6\r\nBREAK\r\n1\r\n4a9\r\n9b23\r\n9b25\r\n9b29\r\n9b2d\r\n9b31\r\n9b35\r\n9b39\r\n9b3d\r\nBREAK\r\n1\r\n263fc\r\n100300\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n26402\r\nBREAK\r\n1\r\n4ac\r\n9b41\r\n9b43\r\n3009b\r\n9b48\r\n9b4d\r\n9b52\r\n9b57\r\n9b5c\r\n9b61\r\nBREAK\r\n1\r\n26408\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n2640e\r\nBREAK\r\n1\r\n4ac\r\n9b41\r\n9b43\r\n3009b\r\n9b48\r\n9b4d\r\n9b52\r\n9b57\r\n9b5c\r\n9b61\r\nBREAK\r\n1\r\n26414\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n2641a\r\nBREAK\r\n1\r\n4ac\r\n9b41\r\n9b43\r\n3009b\r\n9b48\r\n9b4d\r\n9b52\r\n9b57\r\n9b5c\r\n9b61\r\nBREAK\r\n1\r\n26420\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n26426\r\nBREAK\r\n1\r\n4ac\r\n9b41\r\n9b44\r\n3009b\r\n9b49\r\n9b4e\r\n9b53\r\n9b58\r\n9b5d\r\n9b62\r\nBREAK\r\n1\r\n2642c\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n26432\r\nBREAK\r\n1\r\n4ac\r\n9b41\r\n9b45\r\n3009b\r\n9b4a\r\n9b4f\r\n9b54\r\n9b59\r\n9b5e\r\n9b63\r\nBREAK\r\n1\r\n26438\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n2643e\r\nBREAK\r\n1\r\n4ac\r\n9b41\r\n9b47\r\n3009b\r\n9b4c\r\n9b51\r\n9b56\r\n9b5b\r\n9b60\r\n9b65\r\nBREAK\r\n1\r\n26444\r\nBREAK\r\n1\r\n4a0\r\n996a\r\n996c\r\n9974\r\n9978\r\n9980\r\n9984\r\n998c\r\n9990\r\n9998\r\n999c\r\n99a4\r\n99a8\r\n99b0\r\n99b4\r\n99bc\r\n99c0\r\n99c8\r\n99cc\r\n99d4\r\n99d8\r\n99e0\r\n99e4\r\n99ec\r\n99f0\r\n99f8\r\n99fc\r\n9a04\r\n9a08\r\n9a10\r\n9a14\r\n9a1c\r\n9a20\r\n9a28\r\n9a2c\r\n9a34\r\n9a38\r\n9a40\r\n9a44\r\n9a4c\r\n9a50\r\n9a58\r\n9a5c\r\n9a64\r\n9a68\r\n9a70\r\n9a74\r\n9a7c\r\n9a80\r\n9a88\r\n9a8c\r\n9a94\r\n9a98\r\n9aa0\r\n9aa4\r\n9aac\r\n9ab0\r\n9ab8\r\n9abc\r\n9ac4\r\n9ac8\r\n9ad0\r\n9ad4\r\n9adc\r\nBREAK\r\n1\r\n2644a\r\nBREAK\r\n1\r\n26450\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n26456\r\nBREAK\r\n1\r\n2645c\r\nBREAK\r\n1\r\n26462\r\nBREAK\r\n1\r\n26468\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n2646e\r\nBREAK\r\n1\r\n26474\r\nBREAK\r\n1\r\n50f\r\nb0d0\r\nb0d2\r\nb0d6\r\nb0da\r\nb0de\r\nb0e2\r\nb0e6\r\nb0ea\r\nb0ee\r\nb0f2\r\nb0f6\r\nb0fa\r\nb0fe\r\nb102\r\nb106\r\nBREAK\r\n1\r\n2647a\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n26480\r\nBREAK\r\n1\r\n26486\r\nBREAK\r\n1\r\n2648c\r\nBREAK\r\n1\r\n26492\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n26498\r\nBREAK\r\n1\r\n2649e\r\nBREAK\r\n1\r\n512\r\nb10a\r\nb10c\r\nb110\r\nb114\r\nb118\r\nb11c\r\nb120\r\nb124\r\nb128\r\nb12c\r\nb130\r\nb134\r\nb138\r\nb13c\r\nb140\r\nBREAK\r\n1\r\n264a4\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n264aa\r\nBREAK\r\n1\r\n264b0\r\nBREAK\r\n1\r\n264b6\r\nBREAK\r\n1\r\n264bc\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n264c2\r\nBREAK\r\n1\r\n264c8\r\nBREAK\r\n1\r\n50f\r\nb0d0\r\nb0d2\r\nb0d6\r\nb0da\r\nb0de\r\nb0e2\r\nb0e6\r\nb0ea\r\nb0ee\r\nb0f2\r\nb0f6\r\nb0fa\r\nb0fe\r\nb102\r\nb106\r\nBREAK\r\n1\r\n264ce\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n264d4\r\nBREAK\r\n1\r\n264da\r\nBREAK\r\n1\r\n264e0\r\nBREAK\r\n1\r\n264e6\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n264ec\r\nBREAK\r\n1\r\n264f2\r\nBREAK\r\n1\r\n512\r\nb10a\r\nb10c\r\nb110\r\nb114\r\nb118\r\nb11c\r\nb120\r\nb124\r\nb128\r\nb12c\r\nb130\r\nb134\r\nb138\r\nb13c\r\nb140\r\nBREAK\r\n1\r\n264f8\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n264fe\r\nBREAK\r\n1\r\n26504\r\nBREAK\r\n1\r\n2650a\r\nBREAK\r\n1\r\n26510\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n26516\r\nBREAK\r\n1\r\n2651c\r\nBREAK\r\n1\r\n500\r\nafae\r\nafb0\r\nafb4\r\nafb8\r\nafbc\r\nafc0\r\nafc4\r\nafc8\r\nafcc\r\nafd0\r\nafd4\r\nafd8\r\nafdc\r\nafe0\r\nafe4\r\nBREAK\r\n1\r\n26522\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n26528\r\nBREAK\r\n1\r\n2652e\r\nBREAK\r\n1\r\n26534\r\nBREAK\r\n1\r\n2653a\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n26540\r\nBREAK\r\n1\r\n26546\r\nBREAK\r\n1\r\n503\r\n0\r\nafe8\r\nafea\r\nafee\r\naff2\r\naff6\r\naffa\r\naffe\r\nb002\r\nb006\r\nb00a\r\nb00e\r\nb012\r\nb016\r\nb01a\r\nb01e\r\nBREAK\r\n1\r\n2654c\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n26552\r\nBREAK\r\n1\r\n26558\r\nBREAK\r\n1\r\n2655e\r\nBREAK\r\n1\r\n26564\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n2656a\r\nBREAK\r\n1\r\n26570\r\nBREAK\r\n1\r\n506\r\nb022\r\nb024\r\nb028\r\nb02c\r\nb030\r\nb034\r\nb038\r\nb03c\r\nb040\r\nb044\r\nb048\r\nb04c\r\nb050\r\nb054\r\nb058\r\nBREAK\r\n1\r\n26576\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n2657c\r\nBREAK\r\n1\r\n26582\r\nBREAK\r\n1\r\n26588\r\nBREAK\r\n1\r\n2658e\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n26594\r\nBREAK\r\n1\r\n2659a\r\nBREAK\r\n1\r\n509\r\nb05c\r\nb05e\r\nb062\r\nb066\r\nb06a\r\nb06e\r\nb072\r\nb076\r\nb07a\r\nb07e\r\nb082\r\nb086\r\nb08a\r\nb08e\r\nb092\r\nBREAK\r\n1\r\n265a0\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n265a6\r\nBREAK\r\n1\r\n265ac\r\nBREAK\r\n1\r\n265b2\r\nBREAK\r\n1\r\n265b8\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n265be\r\nBREAK\r\n1\r\n265c4\r\nBREAK\r\n1\r\n50c\r\nb096\r\nb098\r\nb09c\r\nb0a0\r\nb0a4\r\nb0a8\r\nb0ac\r\nb0b0\r\nb0b4\r\nb0b8\r\nb0bc\r\nb0c0\r\nb0c4\r\nb0c8\r\nb0cc\r\nBREAK\r\n1\r\n265ca\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n265d0\r\nBREAK\r\n1\r\n265d6\r\nBREAK\r\n1\r\n265dc\r\nBREAK\r\n1\r\n265e2\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n265e8\r\nBREAK\r\n1\r\n265ee\r\nBREAK\r\n1\r\n4fa\r\naf3a\r\naf3c\r\naf40\r\naf44\r\naf48\r\naf4c\r\naf50\r\naf54\r\naf58\r\naf5c\r\naf60\r\naf64\r\naf68\r\naf6c\r\naf70\r\nBREAK\r\n1\r\n265f4\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n265fa\r\nBREAK\r\n1\r\n26600\r\nBREAK\r\n1\r\n26606\r\nBREAK\r\n1\r\n2660c\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n26612\r\nBREAK\r\n1\r\n26618\r\nBREAK\r\n1\r\n4fa\r\naf3a\r\naf3c\r\naf40\r\naf44\r\naf48\r\naf4c\r\naf50\r\naf54\r\naf58\r\naf5c\r\naf60\r\naf64\r\naf68\r\naf6c\r\naf70\r\nBREAK\r\n1\r\n2661e\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n26624\r\nBREAK\r\n1\r\n2662a\r\nBREAK\r\n1\r\n26630\r\nBREAK\r\n1\r\n26636\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n2663c\r\nBREAK\r\n1\r\n26642\r\nBREAK\r\n1\r\n4fd\r\naf74\r\naf76\r\naf7a\r\naf7e\r\naf82\r\naf86\r\naf8a\r\naf8e\r\naf92\r\naf96\r\naf9a\r\naf9e\r\nafa2\r\nafa6\r\nafaa\r\nBREAK\r\n1\r\n26648\r\nBREAK\r\n1\r\n4f4\r\nad62\r\nad64\r\nad6c\r\nad70\r\nad78\r\nad7c\r\nad84\r\nad88\r\nad90\r\nad94\r\nad9c\r\nada0\r\nada8\r\nadac\r\nadb4\r\nadb8\r\nadc0\r\nadc4\r\nadcc\r\nadd0\r\nadd8\r\naddc\r\nade4\r\nade8\r\nadf0\r\nadf4\r\nadfc\r\nae00\r\nae08\r\nae0c\r\nae14\r\nae18\r\nae20\r\nae24\r\nae2c\r\nae30\r\nae38\r\nae3c\r\nae44\r\nae48\r\nae50\r\nae54\r\nae5c\r\nae60\r\nae68\r\nae6c\r\nae74\r\nae78\r\nae80\r\nae84\r\nae8c\r\nae90\r\nae98\r\nae9c\r\naea4\r\naea8\r\naeb0\r\naeb4\r\naebc\r\naec0\r\naec8\r\naecc\r\naed4\r\nBREAK\r\n1\r\n2664e\r\nBREAK\r\n1\r\n26654\r\nBREAK\r\n1\r\n2665a\r\nBREAK\r\n1\r\n26660\r\nBREAK\r\n1\r\n4f7\r\naed8\r\naeda\r\naee2\r\naee6\r\naeee\r\naef2\r\naefa\r\naefe\r\naf06\r\naf0a\r\naf12\r\naf16\r\naf1e\r\naf22\r\naf2a\r\naf2e\r\naf36\r\nBREAK\r\n1\r\n26666\r\nBREAK\r\n1\r\n2666c\r\nBREAK\r\n1\r\n4fd\r\naf74\r\naf76\r\naf7a\r\naf7e\r\naf82\r\naf86\r\naf8a\r\naf8e\r\naf92\r\naf96\r\naf9a\r\naf9e\r\nafa2\r\nafa6\r\nafaa\r\nBREAK\r\n1\r\n26672\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\n26678\r\nBREAK\r\n1\r\n2667e\r\nBREAK\r\n1\r\n26684\r\nBREAK\r\n1\r\n386\r\n860000\r\n6e06\r\n6e08\r\n6e0a\r\n6e0c\r\n6e0e\r\n6e10\r\n6e12\r\n6e14\r\n6e16\r\n6e18\r\n6e1a\r\n6e1c\r\n6e1e\r\n6e20\r\n6e22\r\n6e24\r\n6e26\r\n6e28\r\n6e2a\r\n6e2c\r\n6e2e\r\n6e30\r\n6e32\r\n6e34\r\n6e36\r\n6e38\r\n6e3a\r\n6e3c\r\n6e3e\r\n6e40\r\n6e42\r\n6e44\r\nBREAK\r\n1\r\n2668a\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\n26690\r\nBREAK\r\n1\r\n26696\r\nBREAK\r\n1\r\n4b5\r\n9ce2\r\n9ce4\r\n9ce6\r\n9ce8\r\n9cea\r\n9cec\r\n9cee\r\n9cf0\r\n9cf2\r\n9cf4\r\n9cf6\r\n9cf8\r\n9cfa\r\n9cfc\r\n9cfe\r\n9d00\r\n9d02\r\n9d04\r\n9d06\r\n9d08\r\n9d0a\r\n9d0c\r\n9d0e\r\n9d10\r\n9d12\r\n9d14\r\n9d16\r\n9d18\r\n9d1a\r\n9d1c\r\n9d1e\r\n9d20\r\nBREAK\r\n1\r\n2669c\r\nBREAK\r\n1\r\n266a2\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\nBREAK\r\n1\r\nce\r\n2436\r\n2438\r\n243d\r\n2442\r\n2447\r\n244c\r\n2451\r\n2456\r\n245b\r\n2460\r\n2465\r\n246a\r\n246f\r\n2474\r\n2479\r\n247e\r\n2483\r\n2488\r\n248d\r\n2492\r\n2497\r\n249c\r\n" }, { "path": "figure/SignalPulls/usatourbuy.txt", "content": "here\r\nTime [s],Packet ID,MOSI,MISO\r\n\r\nBREAK\r\n1\r\nbf\r\n2300\r\n2302\r\n2307\r\n230c\r\n2311\r\n2316\r\n231b\r\n2320\r\n2325\r\n232a\r\n232f\r\n2334\r\n2339\r\nBREAK\r\n1\r\nbc\r\n2225\r\n2227\r\n222e\r\n2235\r\n223c\r\n2243\r\n224a\r\n2251\r\n2258\r\n225f\r\n2266\r\n226d\r\n2274\r\n227b\r\n2282\r\n2289\r\n2290\r\n2297\r\n229e\r\n22a5\r\n22ac\r\n22b3\r\n22ba\r\n22c1\r\n22c8\r\n22cf\r\n22d6\r\n22dd\r\n22e4\r\n22eb\r\n22f2\r\n22f9\r\nBREAK\r\n1\r\nc5\r\n237c\r\n237e\r\n2383\r\n2388\r\n238d\r\n2392\r\n2397\r\n239c\r\n23a1\r\n23a6\r\n23ab\r\n23b0\r\n23b5\r\nBREAK\r\n1\r\nbc\r\n2225\r\n2227\r\n222e\r\n2235\r\n223c\r\n2243\r\n224a\r\n2251\r\n2258\r\n225f\r\n2266\r\n226d\r\n2274\r\n227b\r\n2282\r\n2289\r\n2290\r\n2297\r\n229e\r\n22a5\r\n22ac\r\n22b3\r\n22ba\r\n22c1\r\n22c8\r\n22cf\r\n22d6\r\n22dd\r\n22e4\r\n22eb\r\n22f2\r\n22f9\r\nBREAK\r\n1\r\n2a8\r\n2af2\r\n2af4\r\n2af8\r\n2afc\r\n2b00\r\n2b04\r\n2b08\r\n2b0c\r\n2b10\r\n2b14\r\n2b18\r\n2b1c\r\n2b20\r\n2b24\r\n2b28\r\n2b2c\r\n2b30\r\nBREAK\r\n1\r\n2cc\r\n2e06\r\n2e08\r\n2e10\r\n2e18\r\n2e20\r\n2e28\r\n2e30\r\n2e38\r\n2e40\r\n2e48\r\n2e50\r\n2e58\r\n2e60\r\nBREAK\r\n1\r\n163\r\nBREAK\r\n1\r\nc5\r\n237c\r\n237e\r\n2383\r\n2388\r\n238d\r\n2392\r\n2397\r\n239c\r\n23a1\r\n23a6\r\n23ab\r\n23b0\r\n23b5\r\nBREAK\r\n1\r\n2a8\r\n2af2\r\n2af4\r\n2af8\r\n2afc\r\n2b00\r\n2b04\r\n2b08\r\n2b0c\r\n2b10\r\n2b14\r\n2b18\r\n2b1c\r\n2b20\r\n2b24\r\n2b28\r\n2b2c\r\n2b30\r\nBREAK\r\n1\r\nc5\r\n237c\r\n237e\r\n2383\r\n2388\r\n238d\r\n2392\r\n2397\r\n239c\r\n23a1\r\n23a6\r\n23ab\r\n23b0\r\n23b5\r\nBREAK\r\n1\r\nc5\r\n237c\r\n237e\r\n2383\r\n2388\r\n238d\r\n2392\r\n2397\r\n239c\r\n23a1\r\n23a6\r\n23ab\r\n23b0\r\n23b5\r\nBREAK\r\n1\r\nbc\r\n2225\r\n2227\r\n222e\r\n2235\r\n223c\r\n2243\r\n224a\r\n2251\r\n2258\r\n225f\r\n2266\r\n226d\r\n2274\r\n227b\r\n2282\r\n2289\r\n2290\r\n2297\r\n229e\r\n22a5\r\n22ac\r\n22b3\r\n22ba\r\n22c1\r\n22c8\r\n22cf\r\n22d6\r\n22dd\r\n22e4\r\n22eb\r\n22f2\r\n22f9\r\n" }, { "path": "figure/scripts/README", "content": "im.py -- extracts images from ROM dump" }, { "path": "figure/scripts/im.py", "content": "import Image\r\n\r\nf = open(\"C:\\\\Users\\\\Natalie\\\\Downloads\\\\Tamagotchi-Hack-master\\\\figure\\\\ROMDump\\\\makiko\", 'rb')\r\n\r\na = f.read()\r\ns = \"\"\r\n#offset = 0x201292\r\n#offset = 0x257010\r\n#offset = 0x2AB139\r\noffset = 0\r\n\r\na = a[offset:]\r\n\r\nnum = 0\r\no = 0x1539\r\n\r\nwhile True:\r\n\twidth = ord(a[o])\r\n\t#//while (width == 0):\r\n\t#//\to = o + 1\r\n\t#//\twidth = ord(a[o])\r\n\theight = ord(a[o+1])\r\n\tprint width,\r\n\tprint height\r\n\to = o + 2\r\n\tif( height > 0x60):\r\n\t\tprint \"end\"\r\n\t\tprint o + offset\r\n\t\tbreak\r\n\textra = 0\r\n\tif( height > 0x60):\r\n\t\tprint \"end\"\r\n\t\tprint o + offset\r\n\t\tbreak\r\n\tif ((width) % 4 != 0):\r\n\t\twhile ((width) % 4 != 0):\r\n\t\t\twidth = width + 1\r\n\tif ((height) % 4 != 0):\r\n\t\t#for t in range(0, (height) % 4):\r\n\t\t#height = height + 1\r\n\r\n\t\tprint \"Padded to \" + str(width) + \" by \" + str(height)\r\n\ts = \"\"\r\n\tfor i in range(0, height*width/4 + 1):\r\n\t\tfor j in range(0, 4):\r\n\t\t\t#print ord(a[i])\r\n\t\t\t#print (0x03 << ((3- j)*2))\r\n\t\t\tk = ord(a[i+o]) & (0x03 << ((3- j)*2))\r\n\r\n\t\t\tl = ((k) >> ((3-j)*2))\r\n\t\t\r\n\t\t\ts = s + chr(0xFF&(~(l*(255/4))))\r\n\to = o + height*width/4\r\n\t#print s\r\n\r\n\timage = Image.fromstring(\r\n \"L\", (width, height), s, \"raw\", \r\n \"L\"\r\n )\r\n\tprint \"img \" + str(num) + \" at \" + str(o)\r\n\timage.save(\"../ROMDump/m/im-\" + str(num) + \".bmp\")\r\n\tnum = num + 1\r\n\r\n" }, { "path": "figure/scripts/l.txt", "content": "48 31\r\nPadded to 48 by 31\r\nimg 0 at 5807\r\n48 31\r\nPadded to 48 by 31\r\nimg 1 at 6181\r\n48 31\r\nPadded to 48 by 31\r\nimg 2 at 6555\r\n48 31\r\nPadded to 48 by 31\r\nimg 3 at 6929\r\n48 31\r\nPadded to 48 by 31\r\nimg 4 at 7303\r\n48 31\r\nPadded to 48 by 31\r\nimg 5 at 7677\r\n48 31\r\nPadded to 48 by 31\r\nimg 6 at 8051\r\n48 31\r\nPadded to 48 by 31\r\nimg 7 at 8425\r\n48 13\r\nPadded to 48 by 13\r\nimg 8 at 8583\r\n48 13\r\nPadded to 48 by 13\r\nimg 9 at 8741\r\n28 31\r\nPadded to 28 by 31\r\nimg 10 at 8960\r\n18 12\r\nimg 11 at 9022\r\n18 12\r\nimg 12 at 9084\r\n18 12\r\nimg 13 at 9146\r\n18 12\r\nimg 14 at 9208\r\n18 12\r\nimg 15 at 9270\r\n17 21\r\nPadded to 20 by 21\r\nimg 16 at 9377\r\n17 21\r\nPadded to 20 by 21\r\nimg 17 at 9484\r\n32 8\r\nimg 18 at 9550\r\n32 8\r\nimg 19 at 9616\r\n32 8\r\nimg 20 at 9682\r\n32 8\r\nimg 21 at 9748\r\n32 8\r\nimg 22 at 9814\r\n32 8\r\nimg 23 at 9880\r\n8 8\r\nimg 24 at 9898\r\n8 8\r\nimg 25 at 9916\r\n8 8\r\nimg 26 at 9934\r\n8 8\r\nimg 27 at 9952\r\n8 8\r\nimg 28 at 9970\r\n1 1\r\nPadded to 4 by 1\r\nimg 29 at 9973\r\n12 12\r\nimg 30 at 10011\r\n12 12\r\nimg 31 at 10049\r\n12 12\r\nimg 32 at 10087\r\n12 12\r\nimg 33 at 10125\r\n12 12\r\nimg 34 at 10163\r\n12 12\r\nimg 35 at 10201\r\n12 12\r\nimg 36 at 10239\r\n12 12\r\nimg 37 at 10277\r\n12 12\r\nimg 38 at 10315\r\n12 12\r\nimg 39 at 10353\r\n48 31\r\nPadded to 48 by 31\r\nimg 40 at 10727\r\n1 1\r\nPadded to 4 by 1\r\nimg 41 at 10730\r\n16 16\r\nimg 42 at 10796\r\n16 16\r\nimg 43 at 10862\r\n16 16\r\nimg 44 at 10928\r\n16 16\r\nimg 45 at 10994\r\n16 16\r\nimg 46 at 11060\r\n16 16\r\nimg 47 at 11126\r\n16 16\r\nimg 48 at 11192\r\n16 16\r\nimg 49 at 11258\r\n16 16\r\nimg 50 at 11324\r\n16 16\r\nimg 51 at 11390\r\n30 12\r\nimg 52 at 11488\r\n30 12\r\nimg 53 at 11586\r\n30 12\r\nimg 54 at 11684\r\n30 12\r\nimg 55 at 11782\r\n30 12\r\nimg 56 at 11880\r\n30 12\r\nimg 57 at 11978\r\n30 12\r\nimg 58 at 12076\r\n30 12\r\nimg 59 at 12174\r\n30 12\r\nimg 60 at 12272\r\n30 12\r\nimg 61 at 12370\r\n17 25\r\nPadded to 20 by 25\r\nimg 62 at 12497\r\n20 19\r\nPadded to 20 by 19\r\nimg 63 at 12594\r\n20 19\r\nPadded to 20 by 19\r\nimg 64 at 12691\r\n20 19\r\nPadded to 20 by 19\r\nimg 65 at 12788\r\n20 19\r\nPadded to 20 by 19\r\nimg 66 at 12885\r\n20 19\r\nPadded to 20 by 19\r\nimg 67 at 12982\r\n19 18\r\nPadded to 20 by 18\r\nimg 68 at 13074\r\n20 18\r\nPadded to 20 by 18\r\nimg 69 at 13166\r\n20 18\r\nPadded to 20 by 18\r\nimg 70 at 13258\r\n7 31\r\nPadded to 8 by 31\r\nimg 71 at 13322\r\n31 17\r\nPadded to 32 by 17\r\nimg 72 at 13460\r\n48 31\r\nPadded to 48 by 31\r\nimg 73 at 13834\r\n48 31\r\nPadded to 48 by 31\r\nimg 74 at 14208\r\n48 31\r\nPadded to 48 by 31\r\nimg 75 at 14582\r\n48 31\r\nPadded to 48 by 31\r\nimg 76 at 14956\r\n48 22\r\nPadded to 48 by 22\r\nimg 77 at 15222\r\n48 31\r\nPadded to 48 by 31\r\nimg 78 at 15596\r\n48 31\r\nPadded to 48 by 31\r\nimg 79 at 15970\r\n48 31\r\nPadded to 48 by 31\r\nimg 80 at 16344\r\n48 31\r\nPadded to 48 by 31\r\nimg 81 at 16718\r\n48 15\r\nPadded to 48 by 15\r\nimg 82 at 16900\r\n48 15\r\nPadded to 48 by 15\r\nimg 83 at 17082\r\n48 31\r\nPadded to 48 by 31\r\nimg 84 at 17456\r\n48 31\r\nPadded to 48 by 31\r\nimg 85 at 17830\r\n48 3\r\nPadded to 48 by 3\r\nimg 86 at 17868\r\n25 24\r\nimg 87 at 18038\r\n48 6\r\nPadded to 48 by 6\r\nimg 88 at 18112\r\n48 31\r\nPadded to 48 by 31\r\nimg 89 at 18486\r\n48 31\r\nPadded to 48 by 31\r\nimg 90 at 18860\r\n48 31\r\nPadded to 48 by 31\r\nimg 91 at 19234\r\n48 31\r\nPadded to 48 by 31\r\nimg 92 at 19608\r\n48 31\r\nPadded to 48 by 31\r\nimg 93 at 19982\r\n48 31\r\nPadded to 48 by 31\r\nimg 94 at 20356\r\n6 7\r\nPadded to 8 by 7\r\nimg 95 at 20372\r\n7 31\r\nPadded to 8 by 31\r\nimg 96 at 20436\r\n32 31\r\nPadded to 32 by 31\r\nimg 97 at 20686\r\n48 31\r\nPadded to 48 by 31\r\nimg 98 at 21060\r\n48 31\r\nPadded to 48 by 31\r\nimg 99 at 21434\r\n48 31\r\nPadded to 48 by 31\r\nimg 100 at 21808\r\n48 31\r\nPadded to 48 by 31\r\nimg 101 at 22182\r\n48 31\r\nPadded to 48 by 31\r\nimg 102 at 22556\r\n48 31\r\nPadded to 48 by 31\r\nimg 103 at 22930\r\n48 31\r\nPadded to 48 by 31\r\nimg 104 at 23304\r\n48 31\r\nPadded to 48 by 31\r\nimg 105 at 23678\r\n48 31\r\nPadded to 48 by 31\r\nimg 106 at 24052\r\n48 31\r\nPadded to 48 by 31\r\nimg 107 at 24426\r\n48 31\r\nPadded to 48 by 31\r\nimg 108 at 24800\r\n48 31\r\nPadded to 48 by 31\r\nimg 109 at 25174\r\n48 31\r\nPadded to 48 by 31\r\nimg 110 at 25548\r\n48 31\r\nPadded to 48 by 31\r\nimg 111 at 25922\r\n48 31\r\nPadded to 48 by 31\r\nimg 112 at 26296\r\n48 31\r\nPadded to 48 by 31\r\nimg 113 at 26670\r\n48 31\r\nPadded to 48 by 31\r\nimg 114 at 27044\r\n48 31\r\nPadded to 48 by 31\r\nimg 115 at 27418\r\n48 31\r\nPadded to 48 by 31\r\nimg 116 at 27792\r\n48 31\r\nPadded to 48 by 31\r\nimg 117 at 28166\r\n7 31\r\nPadded to 8 by 31\r\nimg 118 at 28230\r\n32 29\r\nPadded to 32 by 29\r\nimg 119 at 28464\r\n32 29\r\nPadded to 32 by 29\r\nimg 120 at 28698\r\n48 31\r\nPadded to 48 by 31\r\nimg 121 at 29072\r\n48 31\r\nPadded to 48 by 31\r\nimg 122 at 29446\r\n48 31\r\nPadded to 48 by 31\r\nimg 123 at 29820\r\n48 31\r\nPadded to 48 by 31\r\nimg 124 at 30194\r\n48 31\r\nPadded to 48 by 31\r\nimg 125 at 30568\r\n48 31\r\nPadded to 48 by 31\r\nimg 126 at 30942\r\n48 31\r\nPadded to 48 by 31\r\nimg 127 at 31316\r\n48 31\r\nPadded to 48 by 31\r\nimg 128 at 31690\r\n48 31\r\nPadded to 48 by 31\r\nimg 129 at 32064\r\n48 8\r\nimg 130 at 32162\r\n48 22\r\nPadded to 48 by 22\r\nimg 131 at 32428\r\n48 22\r\nPadded to 48 by 22\r\nimg 132 at 32694\r\n48 22\r\nPadded to 48 by 22\r\nimg 133 at 32960\r\n48 22\r\nPadded to 48 by 22\r\nimg 134 at 33226\r\n48 7\r\nPadded to 48 by 7\r\nimg 135 at 33312\r\n48 7\r\nPadded to 48 by 7\r\nimg 136 at 33398\r\n48 31\r\nPadded to 48 by 31\r\nimg 137 at 33772\r\n48 31\r\nPadded to 48 by 31\r\nimg 138 at 34146\r\n20 6\r\nPadded to 20 by 6\r\nimg 139 at 34178\r\n48 31\r\nPadded to 48 by 31\r\nimg 140 at 34552\r\n35 26\r\nPadded to 36 by 26\r\nimg 141 at 34788\r\n35 26\r\nPadded to 36 by 26\r\nimg 142 at 35024\r\n16 15\r\nPadded to 16 by 15\r\nimg 143 at 35086\r\n16 15\r\nPadded to 16 by 15\r\nimg 144 at 35148\r\n16 15\r\nPadded to 16 by 15\r\nimg 145 at 35210\r\n16 15\r\nPadded to 16 by 15\r\nimg 146 at 35272\r\n16 15\r\nPadded to 16 by 15\r\nimg 147 at 35334\r\n16 15\r\nPadded to 16 by 15\r\nimg 148 at 35396\r\n16 15\r\nPadded to 16 by 15\r\nimg 149 at 35458\r\n16 15\r\nPadded to 16 by 15\r\nimg 150 at 35520\r\n16 15\r\nPadded to 16 by 15\r\nimg 151 at 35582\r\n16 15\r\nPadded to 16 by 15\r\nimg 152 at 35644\r\n16 15\r\nPadded to 16 by 15\r\nimg 153 at 35706\r\n16 15\r\nPadded to 16 by 15\r\nimg 154 at 35768\r\n16 15\r\nPadded to 16 by 15\r\nimg 155 at 35830\r\n16 15\r\nPadded to 16 by 15\r\nimg 156 at 35892\r\n16 15\r\nPadded to 16 by 15\r\nimg 157 at 35954\r\n16 15\r\nPadded to 16 by 15\r\nimg 158 at 36016\r\n16 15\r\nPadded to 16 by 15\r\nimg 159 at 36078\r\n16 15\r\nPadded to 16 by 15\r\nimg 160 at 36140\r\n16 15\r\nPadded to 16 by 15\r\nimg 161 at 36202\r\n16 15\r\nPadded to 16 by 15\r\nimg 162 at 36264\r\n16 15\r\nPadded to 16 by 15\r\nimg 163 at 36326\r\n16 15\r\nPadded to 16 by 15\r\nimg 164 at 36388\r\n16 15\r\nPadded to 16 by 15\r\nimg 165 at 36450\r\n16 15\r\nPadded to 16 by 15\r\nimg 166 at 36512\r\n16 15\r\nPadded to 16 by 15\r\nimg 167 at 36574\r\n16 15\r\nPadded to 16 by 15\r\nimg 168 at 36636\r\n16 15\r\nPadded to 16 by 15\r\nimg 169 at 36698\r\n16 15\r\nPadded to 16 by 15\r\nimg 170 at 36760\r\n16 15\r\nPadded to 16 by 15\r\nimg 171 at 36822\r\n16 15\r\nPadded to 16 by 15\r\nimg 172 at 36884\r\n16 15\r\nPadded to 16 by 15\r\nimg 173 at 36946\r\n16 15\r\nPadded to 16 by 15\r\nimg 174 at 37008\r\n16 15\r\nPadded to 16 by 15\r\nimg 175 at 37070\r\n16 15\r\nPadded to 16 by 15\r\nimg 176 at 37132\r\n16 15\r\nPadded to 16 by 15\r\nimg 177 at 37194\r\n16 15\r\nPadded to 16 by 15\r\nimg 178 at 37256\r\n24 31\r\nPadded to 24 by 31\r\nimg 179 at 37444\r\n24 15\r\nPadded to 24 by 15\r\nimg 180 at 37536\r\n16 19\r\nPadded to 16 by 19\r\nimg 181 at 37614\r\n30 31\r\nPadded to 32 by 31\r\nimg 182 at 37864\r\n30 31\r\nPadded to 32 by 31\r\nimg 183 at 38114\r\n30 31\r\nPadded to 32 by 31\r\nimg 184 at 38364\r\n30 31\r\nPadded to 32 by 31\r\nimg 185 at 38614\r\n30 31\r\nPadded to 32 by 31\r\nimg 186 at 38864\r\n4 7\r\nPadded to 4 by 7\r\nimg 187 at 38873\r\n4 7\r\nPadded to 4 by 7\r\nimg 188 at 38882\r\n4 7\r\nPadded to 4 by 7\r\nimg 189 at 38891\r\n4 7\r\nPadded to 4 by 7\r\nimg 190 at 38900\r\n48 31\r\nPadded to 48 by 31\r\nimg 191 at 39274\r\n48 31\r\nPadded to 48 by 31\r\nimg 192 at 39648\r\n19 7\r\nPadded to 20 by 7\r\nimg 193 at 39685\r\n13 7\r\nPadded to 16 by 7\r\nimg 194 at 39715\r\n13 7\r\nPadded to 16 by 7\r\nimg 195 at 39745\r\n19 7\r\nPadded to 20 by 7\r\nimg 196 at 39782\r\n48 31\r\nPadded to 48 by 31\r\nimg 197 at 40156\r\n4 4\r\nimg 198 at 40162\r\n7 31\r\nPadded to 8 by 31\r\nimg 199 at 40226\r\n48 31\r\nPadded to 48 by 31\r\nimg 200 at 40600\r\n48 31\r\nPadded to 48 by 31\r\nimg 201 at 40974\r\n48 31\r\nPadded to 48 by 31\r\nimg 202 at 41348\r\n48 31\r\nPadded to 48 by 31\r\nimg 203 at 41722\r\n16 31\r\nPadded to 16 by 31\r\nimg 204 at 41848\r\n16 16\r\nimg 205 at 41914\r\n16 16\r\nimg 206 at 41980\r\n16 16\r\nimg 207 at 42046\r\n16 16\r\nimg 208 at 42112\r\n4 4\r\nimg 209 at 42118\r\n4 4\r\nimg 210 at 42124\r\n48 31\r\nPadded to 48 by 31\r\nimg 211 at 42498\r\n48 31\r\nPadded to 48 by 31\r\nimg 212 at 42872\r\n48 31\r\nPadded to 48 by 31\r\nimg 213 at 43246\r\n48 31\r\nPadded to 48 by 31\r\nimg 214 at 43620\r\n48 31\r\nPadded to 48 by 31\r\nimg 215 at 43994\r\n4 4\r\nimg 216 at 44000\r\n4 4\r\nimg 217 at 44006\r\n4 4\r\nimg 218 at 44012\r\n48 31\r\nPadded to 48 by 31\r\nimg 219 at 44386\r\n48 31\r\nPadded to 48 by 31\r\nimg 220 at 44760\r\n48 8\r\nimg 221 at 44858\r\n16 14\r\nPadded to 16 by 14\r\nimg 222 at 44916\r\n16 14\r\nPadded to 16 by 14\r\nimg 223 at 44974\r\n16 14\r\nPadded to 16 by 14\r\nimg 224 at 45032\r\n16 14\r\nPadded to 16 by 14\r\nimg 225 at 45090\r\n16 14\r\nPadded to 16 by 14\r\nimg 226 at 45148\r\n16 14\r\nPadded to 16 by 14\r\nimg 227 at 45206\r\n16 14\r\nPadded to 16 by 14\r\nimg 228 at 45264\r\n16 14\r\nPadded to 16 by 14\r\nimg 229 at 45322\r\n16 14\r\nPadded to 16 by 14\r\nimg 230 at 45380\r\n48 31\r\nPadded to 48 by 31\r\nimg 231 at 45754\r\n24 31\r\nPadded to 24 by 31\r\nimg 232 at 45942\r\n24 15\r\nPadded to 24 by 15\r\nimg 233 at 46034\r\n16 19\r\nPadded to 16 by 19\r\nimg 234 at 46112\r\n30 31\r\nPadded to 32 by 31\r\nimg 235 at 46362\r\n30 31\r\nPadded to 32 by 31\r\nimg 236 at 46612\r\n30 31\r\nPadded to 32 by 31\r\nimg 237 at 46862\r\n30 31\r\nPadded to 32 by 31\r\nimg 238 at 47112\r\n30 31\r\nPadded to 32 by 31\r\nimg 239 at 47362\r\n4 7\r\nPadded to 4 by 7\r\nimg 240 at 47371\r\n4 7\r\nPadded to 4 by 7\r\nimg 241 at 47380\r\n4 7\r\nPadded to 4 by 7\r\nimg 242 at 47389\r\n4 7\r\nPadded to 4 by 7\r\nimg 243 at 47398\r\n48 31\r\nPadded to 48 by 31\r\nimg 244 at 47772\r\n48 31\r\nPadded to 48 by 31\r\nimg 245 at 48146\r\n19 7\r\nPadded to 20 by 7\r\nimg 246 at 48183\r\n13 7\r\nPadded to 16 by 7\r\nimg 247 at 48213\r\n13 7\r\nPadded to 16 by 7\r\nimg 248 at 48243\r\n19 7\r\nPadded to 20 by 7\r\nimg 249 at 48280\r\n48 31\r\nPadded to 48 by 31\r\nimg 250 at 48654\r\n4 4\r\nimg 251 at 48660\r\n7 31\r\nPadded to 8 by 31\r\nimg 252 at 48724\r\n48 31\r\nPadded to 48 by 31\r\nimg 253 at 49098\r\n48 31\r\nPadded to 48 by 31\r\nimg 254 at 49472\r\n48 31\r\nPadded to 48 by 31\r\nimg 255 at 49846\r\n48 31\r\nPadded to 48 by 31\r\nimg 256 at 50220\r\n48 31\r\nPadded to 48 by 31\r\nimg 257 at 50594\r\n48 31\r\nPadded to 48 by 31\r\nimg 258 at 50968\r\n48 31\r\nPadded to 48 by 31\r\nimg 259 at 51342\r\n16 16\r\nimg 260 at 51408\r\n16 16\r\nimg 261 at 51474\r\n16 16\r\nimg 262 at 51540\r\n16 16\r\nimg 263 at 51606\r\n48 31\r\nPadded to 48 by 31\r\nimg 264 at 51980\r\n48 31\r\nPadded to 48 by 31\r\nimg 265 at 52354\r\n48 31\r\nPadded to 48 by 31\r\nimg 266 at 52728\r\n48 31\r\nPadded to 48 by 31\r\nimg 267 at 53102\r\n48 31\r\nPadded to 48 by 31\r\nimg 268 at 53476\r\n4 4\r\nimg 269 at 53482\r\n4 4\r\nimg 270 at 53488\r\n4 4\r\nimg 271 at 53494\r\n48 31\r\nPadded to 48 by 31\r\nimg 272 at 53868\r\n48 31\r\nPadded to 48 by 31\r\nimg 273 at 54242\r\n48 8\r\nimg 274 at 54340\r\n16 14\r\nPadded to 16 by 14\r\nimg 275 at 54398\r\n16 14\r\nPadded to 16 by 14\r\nimg 276 at 54456\r\n16 14\r\nPadded to 16 by 14\r\nimg 277 at 54514\r\n16 14\r\nPadded to 16 by 14\r\nimg 278 at 54572\r\n16 14\r\nPadded to 16 by 14\r\nimg 279 at 54630\r\n16 14\r\nPadded to 16 by 14\r\nimg 280 at 54688\r\n16 14\r\nPadded to 16 by 14\r\nimg 281 at 54746\r\n16 14\r\nPadded to 16 by 14\r\nimg 282 at 54804\r\n16 14\r\nPadded to 16 by 14\r\nimg 283 at 54862\r\n48 31\r\nPadded to 48 by 31\r\nimg 284 at 55236\r\n24 31\r\nPadded to 24 by 31\r\nimg 285 at 55424\r\n24 15\r\nPadded to 24 by 15\r\nimg 286 at 55516\r\n16 19\r\nPadded to 16 by 19\r\nimg 287 at 55594\r\n30 31\r\nPadded to 32 by 31\r\nimg 288 at 55844\r\n30 31\r\nPadded to 32 by 31\r\nimg 289 at 56094\r\n30 31\r\nPadded to 32 by 31\r\nimg 290 at 56344\r\n30 31\r\nPadded to 32 by 31\r\nimg 291 at 56594\r\n30 31\r\nPadded to 32 by 31\r\nimg 292 at 56844\r\n4 7\r\nPadded to 4 by 7\r\nimg 293 at 56853\r\n4 7\r\nPadded to 4 by 7\r\nimg 294 at 56862\r\n4 7\r\nPadded to 4 by 7\r\nimg 295 at 56871\r\n4 7\r\nPadded to 4 by 7\r\nimg 296 at 56880\r\n48 31\r\nPadded to 48 by 31\r\nimg 297 at 57254\r\n48 31\r\nPadded to 48 by 31\r\nimg 298 at 57628\r\n19 7\r\nPadded to 20 by 7\r\nimg 299 at 57665\r\n13 7\r\nPadded to 16 by 7\r\nimg 300 at 57695\r\n13 7\r\nPadded to 16 by 7\r\nimg 301 at 57725\r\n19 7\r\nPadded to 20 by 7\r\nimg 302 at 57762\r\n48 31\r\nPadded to 48 by 31\r\nimg 303 at 58136\r\n4 4\r\nimg 304 at 58142\r\n7 31\r\nPadded to 8 by 31\r\nimg 305 at 58206\r\n48 31\r\nPadded to 48 by 31\r\nimg 306 at 58580\r\n48 31\r\nPadded to 48 by 31\r\nimg 307 at 58954\r\n48 31\r\nPadded to 48 by 31\r\nimg 308 at 59328\r\n48 31\r\nPadded to 48 by 31\r\nimg 309 at 59702\r\n48 31\r\nPadded to 48 by 31\r\nimg 310 at 60076\r\n48 31\r\nPadded to 48 by 31\r\nimg 311 at 60450\r\n48 31\r\nPadded to 48 by 31\r\nimg 312 at 60824\r\n48 31\r\nPadded to 48 by 31\r\nimg 313 at 61198\r\n48 31\r\nPadded to 48 by 31\r\nimg 314 at 61572\r\n48 31\r\nPadded to 48 by 31\r\nimg 315 at 61946\r\n16 16\r\nimg 316 at 62012\r\n16 16\r\nimg 317 at 62078\r\n16 16\r\nimg 318 at 62144\r\n16 16\r\nimg 319 at 62210\r\n4 4\r\nimg 320 at 62216\r\n4 4\r\nimg 321 at 62222\r\n4 4\r\nimg 322 at 62228\r\n4 4\r\nimg 323 at 62234\r\n4 4\r\nimg 324 at 62240\r\n48 31\r\nPadded to 48 by 31\r\nimg 325 at 62614\r\n48 31\r\nPadded to 48 by 31\r\nimg 326 at 62988\r\n48 8\r\nimg 327 at 63086\r\n16 14\r\nPadded to 16 by 14\r\nimg 328 at 63144\r\n16 14\r\nPadded to 16 by 14\r\nimg 329 at 63202\r\n16 14\r\nPadded to 16 by 14\r\nimg 330 at 63260\r\n16 14\r\nPadded to 16 by 14\r\nimg 331 at 63318\r\n16 14\r\nPadded to 16 by 14\r\nimg 332 at 63376\r\n16 14\r\nPadded to 16 by 14\r\nimg 333 at 63434\r\n16 14\r\nPadded to 16 by 14\r\nimg 334 at 63492\r\n16 14\r\nPadded to 16 by 14\r\nimg 335 at 63550\r\n16 14\r\nPadded to 16 by 14\r\nimg 336 at 63608\r\n48 31\r\nPadded to 48 by 31\r\nimg 337 at 63982\r\n24 31\r\nPadded to 24 by 31\r\nimg 338 at 64170\r\n24 15\r\nPadded to 24 by 15\r\nimg 339 at 64262\r\n16 19\r\nPadded to 16 by 19\r\nimg 340 at 64340\r\n30 31\r\nPadded to 32 by 31\r\nimg 341 at 64590\r\n30 31\r\nPadded to 32 by 31\r\nimg 342 at 64840\r\n30 31\r\nPadded to 32 by 31\r\nimg 343 at 65090\r\n30 31\r\nPadded to 32 by 31\r\nimg 344 at 65340\r\n30 31\r\nPadded to 32 by 31\r\nimg 345 at 65590\r\n4 7\r\nPadded to 4 by 7\r\nimg 346 at 65599\r\n4 7\r\nPadded to 4 by 7\r\nimg 347 at 65608\r\n4 7\r\nPadded to 4 by 7\r\nimg 348 at 65617\r\n4 7\r\nPadded to 4 by 7\r\nimg 349 at 65626\r\n48 31\r\nPadded to 48 by 31\r\nimg 350 at 66000\r\n48 31\r\nPadded to 48 by 31\r\nimg 351 at 66374\r\n19 7\r\nPadded to 20 by 7\r\nimg 352 at 66411\r\n13 7\r\nPadded to 16 by 7\r\nimg 353 at 66441\r\n13 7\r\nPadded to 16 by 7\r\nimg 354 at 66471\r\n19 7\r\nPadded to 20 by 7\r\nimg 355 at 66508\r\n48 31\r\nPadded to 48 by 31\r\nimg 356 at 66882\r\n4 4\r\nimg 357 at 66888\r\n7 31\r\nPadded to 8 by 31\r\nimg 358 at 66952\r\n48 31\r\nPadded to 48 by 31\r\nimg 359 at 67326\r\n48 31\r\nPadded to 48 by 31\r\nimg 360 at 67700\r\n48 31\r\nPadded to 48 by 31\r\nimg 361 at 68074\r\n48 31\r\nPadded to 48 by 31\r\nimg 362 at 68448\r\n48 31\r\nPadded to 48 by 31\r\nimg 363 at 68822\r\n48 31\r\nPadded to 48 by 31\r\nimg 364 at 69196\r\n48 31\r\nPadded to 48 by 31\r\nimg 365 at 69570\r\n48 31\r\nPadded to 48 by 31\r\nimg 366 at 69944\r\n48 31\r\nPadded to 48 by 31\r\nimg 367 at 70318\r\n26 15\r\nPadded to 28 by 15\r\nimg 368 at 70425\r\n24 12\r\nimg 369 at 70499\r\n48 2\r\nPadded to 48 by 2\r\nimg 370 at 70525\r\n48 31\r\nPadded to 48 by 31\r\nimg 371 at 70899\r\n4 4\r\nimg 372 at 70905\r\n4 4\r\nimg 373 at 70911\r\n4 4\r\nimg 374 at 70917\r\n4 4\r\nimg 375 at 70923\r\n4 4\r\nimg 376 at 70929\r\n4 4\r\nimg 377 at 70935\r\n48 31\r\nPadded to 48 by 31\r\nimg 378 at 71309\r\n48 31\r\nPadded to 48 by 31\r\nimg 379 at 71683\r\n48 8\r\nimg 380 at 71781\r\n16 14\r\nPadded to 16 by 14\r\nimg 381 at 71839\r\n16 14\r\nPadded to 16 by 14\r\nimg 382 at 71897\r\n16 14\r\nPadded to 16 by 14\r\nimg 383 at 71955\r\n16 14\r\nPadded to 16 by 14\r\nimg 384 at 72013\r\n16 14\r\nPadded to 16 by 14\r\nimg 385 at 72071\r\n16 14\r\nPadded to 16 by 14\r\nimg 386 at 72129\r\n16 14\r\nPadded to 16 by 14\r\nimg 387 at 72187\r\n16 14\r\nPadded to 16 by 14\r\nimg 388 at 72245\r\n16 14\r\nPadded to 16 by 14\r\nimg 389 at 72303\r\n48 31\r\nPadded to 48 by 31\r\nimg 390 at 72677\r\n14 13\r\nPadded to 16 by 13\r\nimg 391 at 72731\r\n14 13\r\nPadded to 16 by 13\r\nimg 392 at 72785\r\n14 13\r\nPadded to 16 by 13\r\nimg 393 at 72839\r\n14 13\r\nPadded to 16 by 13\r\nimg 394 at 72893\r\n14 13\r\nPadded to 16 by 13\r\nimg 395 at 72947\r\n14 13\r\nPadded to 16 by 13\r\nimg 396 at 73001\r\n14 13\r\nPadded to 16 by 13\r\nimg 397 at 73055\r\n14 13\r\nPadded to 16 by 13\r\nimg 398 at 73109\r\n14 13\r\nPadded to 16 by 13\r\nimg 399 at 73163\r\n14 13\r\nPadded to 16 by 13\r\nimg 400 at 73217\r\n14 13\r\nPadded to 16 by 13\r\nimg 401 at 73271\r\n14 13\r\nPadded to 16 by 13\r\nimg 402 at 73325\r\n14 13\r\nPadded to 16 by 13\r\nimg 403 at 73379\r\n14 13\r\nPadded to 16 by 13\r\nimg 404 at 73433\r\n14 13\r\nPadded to 16 by 13\r\nimg 405 at 73487\r\n14 13\r\nPadded to 16 by 13\r\nimg 406 at 73541\r\n14 13\r\nPadded to 16 by 13\r\nimg 407 at 73595\r\n14 13\r\nPadded to 16 by 13\r\nimg 408 at 73649\r\n14 13\r\nPadded to 16 by 13\r\nimg 409 at 73703\r\n14 13\r\nPadded to 16 by 13\r\nimg 410 at 73757\r\n14 13\r\nPadded to 16 by 13\r\nimg 411 at 73811\r\n14 13\r\nPadded to 16 by 13\r\nimg 412 at 73865\r\n14 13\r\nPadded to 16 by 13\r\nimg 413 at 73919\r\n14 13\r\nPadded to 16 by 13\r\nimg 414 at 73973\r\n14 13\r\nPadded to 16 by 13\r\nimg 415 at 74027\r\n14 13\r\nPadded to 16 by 13\r\nimg 416 at 74081\r\n14 13\r\nPadded to 16 by 13\r\nimg 417 at 74135\r\n14 13\r\nPadded to 16 by 13\r\nimg 418 at 74189\r\n14 13\r\nPadded to 16 by 13\r\nimg 419 at 74243\r\n14 13\r\nPadded to 16 by 13\r\nimg 420 at 74297\r\n14 13\r\nPadded to 16 by 13\r\nimg 421 at 74351\r\n14 13\r\nPadded to 16 by 13\r\nimg 422 at 74405\r\n14 13\r\nPadded to 16 by 13\r\nimg 423 at 74459\r\n14 13\r\nPadded to 16 by 13\r\nimg 424 at 74513\r\n14 13\r\nPadded to 16 by 13\r\nimg 425 at 74567\r\n14 13\r\nPadded to 16 by 13\r\nimg 426 at 74621\r\n14 13\r\nPadded to 16 by 13\r\nimg 427 at 74675\r\n14 13\r\nPadded to 16 by 13\r\nimg 428 at 74729\r\n14 13\r\nPadded to 16 by 13\r\nimg 429 at 74783\r\n14 13\r\nPadded to 16 by 13\r\nimg 430 at 74837\r\n14 13\r\nPadded to 16 by 13\r\nimg 431 at 74891\r\n14 13\r\nPadded to 16 by 13\r\nimg 432 at 74945\r\n14 13\r\nPadded to 16 by 13\r\nimg 433 at 74999\r\n14 13\r\nPadded to 16 by 13\r\nimg 434 at 75053\r\n32 17\r\nPadded to 32 by 17\r\nimg 435 at 75191\r\n32 17\r\nPadded to 32 by 17\r\nimg 436 at 75329\r\n48 31\r\nPadded to 48 by 31\r\nimg 437 at 75703\r\n48 31\r\nPadded to 48 by 31\r\nimg 438 at 76077\r\n45 27\r\nPadded to 48 by 27\r\nimg 439 at 76403\r\n45 27\r\nPadded to 48 by 27\r\nimg 440 at 76729\r\n30 25\r\nPadded to 32 by 25\r\nimg 441 at 76931\r\n30 25\r\nPadded to 32 by 25\r\nimg 442 at 77133\r\n48 31\r\nPadded to 48 by 31\r\nimg 443 at 77507\r\n48 31\r\nPadded to 48 by 31\r\nimg 444 at 77881\r\n48 31\r\nPadded to 48 by 31\r\nimg 445 at 78255\r\n48 31\r\nPadded to 48 by 31\r\nimg 446 at 78629\r\n14 11\r\nPadded to 16 by 11\r\nimg 447 at 78675\r\n48 31\r\nPadded to 48 by 31\r\nimg 448 at 79049\r\n48 31\r\nPadded to 48 by 31\r\nimg 449 at 79423\r\n7 31\r\nPadded to 8 by 31\r\nimg 450 at 79487\r\n22 16\r\nimg 451 at 79585\r\n22 16\r\nimg 452 at 79683\r\n7 31\r\nPadded to 8 by 31\r\nimg 453 at 79747\r\n48 7\r\nPadded to 48 by 7\r\nimg 454 at 79833\r\n48 6\r\nPadded to 48 by 6\r\nimg 455 at 79907\r\n48 6\r\nPadded to 48 by 6\r\nimg 456 at 79981\r\n9 8\r\nimg 457 at 80007\r\n20 23\r\nPadded to 20 by 23\r\nimg 458 at 80124\r\n48 31\r\nPadded to 48 by 31\r\nimg 459 at 80498\r\n48 31\r\nPadded to 48 by 31\r\nimg 460 at 80872\r\n48 31\r\nPadded to 48 by 31\r\nimg 461 at 81246\r\n10 10\r\nPadded to 12 by 10\r\nimg 462 at 81278\r\n10 10\r\nPadded to 12 by 10\r\nimg 463 at 81310\r\n10 12\r\nimg 464 at 81348\r\n10 12\r\nimg 465 at 81386\r\n24 9\r\nPadded to 24 by 9\r\nimg 466 at 81442\r\n28 6\r\nPadded to 28 by 6\r\nimg 467 at 81486\r\n28 6\r\nPadded to 28 by 6\r\nimg 468 at 81530\r\n1 0\r\n" }, { "path": "figure-simulator/README", "content": "Code to simulate a memetchi figure. In progress." }, { "path": "figure-simulator/simulator.pde", "content": "#include \n\nDSPI0 spi;\nconst int len = 200;\nuint8_t rgbSnd[len] = {0};\nuint8_t rgbRcv[len] = {0};\nuint8_t b[] ={0x40, 0x00, 0x00, 0xC4, 0x00, 0x00, 0xDC, 0x00, 0x00, 0x0F, 0x01, 0x00, 0x91, 0x01, 0x00, 0x0D, 0x02, 0x00, 0x89, 0x02, 0x00, 0xD1, 0x02, 0x00, 0x1F, 0x06, 0x00, 0x67, 0x0F, 0x00, 0x67, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x12, 0x00, 0xA7, 0x12, 0x00, 0x0D, 0x13, 0x00, 0x73, 0x13, 0x00, 0xD9, 0x13, 0x00, 0x3F, 0x14, 0x00, 0xA5, 0x14, 0x00, 0x0B, 0x15, 0x00, 0x71, 0x15, 0x00, 0xD7, 0x15, 0x00, 0x3D, 0x16, 0x00, 0xA3, 0x16, 0x00, 0x09, 0x17, 0x00, 0x6F, 0x17, 0x00, 0xD5, 0x17, 0x00, 0x3B, 0x18, 0x00, 0xA1, 0x18, 0x00, 0x07, 0x19, 0x00, 0x6D, 0x19, 0x00, 0xD3, 0x19, 0x00, 0x39, 0x1A, 0x00, 0x9F, 0x1A, 0x00, 0x05, 0x1B, 0x00, 0x6B, 0x1B, 0x00, 0xD1, 0x1B, 0x00, 0x37, 0x1C, 0x00, 0x9D, 0x1C, 0x00, 0x13, 0x1E, 0x00, 0x89, 0x1F, 0x00, 0xFF, 0x20, 0x00, 0x75, 0x22, 0x00, 0xEB, 0x23, 0x00, 0x61, 0x25, 0x00, 0xD7, 0x26, 0x00, 0x4D, 0x28, 0x00, 0xEB, 0x28, 0x00, 0x89, 0x29, 0x00, 0x64, 0x2A, 0x00, 0xA2, 0x2A, 0x00, 0xE0, 0x2A, 0x00, 0x1E, 0x2B, 0x00, 0x5C, 0x2B, 0x00, 0x9A, 0x2B, 0x00, 0x05, 0x2C, 0x00, 0x70, 0x2C, 0x00, 0x82, 0x2C, 0x00, 0x90, 0x2C, 0x00, 0x9E, 0x2C, 0x00, 0xB0, 0x2C, 0x00, 0xC2, 0x2C, 0x00, 0xD4, 0x2C};\nint i;\nint yc = 0;\nint x=0;\nint y=0;\n\nvoid setup()\n{\n Serial.begin(9600);\n Serial.println(\"start\");\n spi.begin();\n spi.setSpeed(600000);\n SPI2CONbits.ON = 0;\n rgbRcv[0] = SPI2BUF;\n SPI2CONbits.MSTEN = 0;\n SPI2CONbits.SSEN = 1;\n SPI2CONbits.CKP = 0; \n SPI2CONbits.CKE = 1;\n rgbSnd[4] = 0xaa;\n rgbSnd[5] = 0x55; \n rgbSnd[6] = 0x08; \n\n rgbSnd[11] = 0xaa;\n rgbSnd[12] = 0x55; \n \n \n \n rgbSnd[17] = 0x03; \n rgbSnd[18] = 0x03;\n rgbSnd[19] = 0x03;\n rgbSnd[20] = 0x00;\n rgbSnd[21] = 0x00;\n rgbSnd[22] = 0x10;\n rgbSnd[23] = 0x03;\n // rgbSnd[28] = 0x40;\n // rgbSnd[31] = 0xc4;\n // rgbSnd[34] = 0xdc;\n \n // rgbSnd[40] = \n while(i<96-28){\n for(y = 0; y < 8; y++){\n rgbSnd[28 + i] = b[yc++];\n i++;\n }\n for(x = 0; x < 4; x++){\n i++;\n }\n } \n \n rgbSnd[100] = 0xaa;\n rgbSnd[101] = 0x55; \n rgbSnd[106] = 0x9a; \n rgbSnd[107] = 0x2b; \n rgbSnd[108] = 0x00; \n rgbSnd[113] = 0x11; \n rgbSnd[114] = 0x15; \n rgbSnd[119] = 0xaa;\n rgbSnd[120] = 0x55; \n /// rgbSnd[140] = 0xff;\n SPI2CONbits.ON = 1;\n Serial.println(\"start 2\");\n}\n\nvoid loop()\n{\n for (i = 0; i < 150; i++)\n {\n rgbRcv[i] = spiComm(rgbSnd[i]);\n }\n \n\n for(i = 0; i < 150; i++)\n {\n Serial.print(i);\n Serial.print(\" \");\n Serial.print(rgbSnd[i], HEX);\n Serial.print(\" \");\n Serial.println(rgbRcv[i], HEX);\n }\n Serial.println(\"END\");\n}\n\nuint8_t spiComm(uint8_t bVal)\n{\n while ((SPI2STAT & (1 << _SPISTAT_SPITBE)) == 0) {\n }\n SPI2BUF = bVal;\n\n while ((SPI2STAT & (1 << _SPISTAT_SPIRBF)) == 0) {\n }\n\n return SPI2BUF;\n}\r\n" }, { "path": "figure-simulator-discovery/.cproject", "content": "\r\n\r\n\t\r\n\t\t\r\n\t\t\t\r\n\t\t\t\t\r\n\t\t\t\t\r\n\t\t\t\t\t\r\n\t\t\t\t\t\r\n\t\t\t\t\t\r\n\t\t\t\t\t\r\n\t\t\t\t\r\n\t\t\t\r\n\t\t\t\r\n\t\t\t\t\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\r\n\t\t\t\t\r\n\t\t\t\r\n\t\t\t\r\n\t\t\r\n\t\t\r\n\t\t\t\r\n\t\t\t\t\r\n\t\t\t\t\r\n\t\t\t\t\t\r\n\t\t\t\t\t\r\n\t\t\t\t\t\r\n\t\t\t\t\t\r\n\t\t\t\t\r\n\t\t\t\r\n\t\t\t\r\n\t\t\t\t\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\r\n\t\t\t\t\r\n\t\t\t\r\n\t\t\t\r\n\t\t\r\n\t\r\n\t\r\n\t\t\r\n\t\r\n\t\r\n\t\t\r\n\t\r\n\t\r\n\t\r\n\r\n" }, { "path": "figure-simulator-discovery/.project", "content": "\r\n\r\n\tspi\r\n\t\r\n\t\r\n\t\r\n\t\r\n\t\t\r\n\t\t\torg.eclipse.cdt.managedbuilder.core.genmakebuilder\r\n\t\t\tclean,full,incremental,\r\n\t\t\t\r\n\t\t\t\t\r\n\t\t\t\t\t?name?\r\n\t\t\t\t\t\r\n\t\t\t\t\r\n\t\t\t\t\r\n\t\t\t\t\torg.eclipse.cdt.make.core.append_environment\r\n\t\t\t\t\ttrue\r\n\t\t\t\t\r\n\t\t\t\t\r\n\t\t\t\t\torg.eclipse.cdt.make.core.buildArguments\r\n\t\t\t\t\t\r\n\t\t\t\t\r\n\t\t\t\t\r\n\t\t\t\t\torg.eclipse.cdt.make.core.buildCommand\r\n\t\t\t\t\tmake\r\n\t\t\t\t\r\n\t\t\t\t\r\n\t\t\t\t\torg.eclipse.cdt.make.core.buildLocation\r\n\t\t\t\t\t${workspace_loc:/spi/Debug}\r\n\t\t\t\t\r\n\t\t\t\t\r\n\t\t\t\t\torg.eclipse.cdt.make.core.contents\r\n\t\t\t\t\torg.eclipse.cdt.make.core.activeConfigSettings\r\n\t\t\t\t\r\n\t\t\t\t\r\n\t\t\t\t\torg.eclipse.cdt.make.core.enableAutoBuild\r\n\t\t\t\t\tfalse\r\n\t\t\t\t\r\n\t\t\t\t\r\n\t\t\t\t\torg.eclipse.cdt.make.core.enableCleanBuild\r\n\t\t\t\t\ttrue\r\n\t\t\t\t\r\n\t\t\t\t\r\n\t\t\t\t\torg.eclipse.cdt.make.core.enableFullBuild\r\n\t\t\t\t\ttrue\r\n\t\t\t\t\r\n\t\t\t\t\r\n\t\t\t\t\torg.eclipse.cdt.make.core.stopOnError\r\n\t\t\t\t\ttrue\r\n\t\t\t\t\r\n\t\t\t\t\r\n\t\t\t\t\torg.eclipse.cdt.make.core.useDefaultBuildCmd\r\n\t\t\t\t\ttrue\r\n\t\t\t\t\r\n\t\t\t\r\n\t\t\r\n\t\t\r\n\t\t\torg.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder\r\n\t\t\tfull,incremental,\r\n\t\t\t\r\n\t\t\t\r\n\t\t\r\n\t\r\n\t\r\n\t\torg.eclipse.cdt.core.cnature\r\n\t\torg.eclipse.cdt.managedbuilder.core.managedBuildNature\r\n\t\torg.eclipse.cdt.managedbuilder.core.ScannerConfigNature\r\n\t\r\n\r\n" }, { "path": "figure-simulator-discovery/.settings/com.atollic.truestudio.debug.hardware_device.prefs", "content": "#Sun Dec 16 21:31:24 EST 2012\r\nBOARD=STM32F4_Discovery\r\nCODE_LOCATION=FLASH\r\nENDIAN=Little-endian\r\nMCU=STM32F407VG\r\nMCU_VENDOR=STMicroelectronics\r\nMODEL=Lite\r\nPROBE=ST-LINK\r\nPROJECT_FORMAT_VERSION=2\r\nTARGET=ARM\\u00AE\r\nVERSION=3.3.0\r\neclipse.preferences.version=1\r\n" }, { "path": "figure-simulator-discovery/.settings/org.eclipse.cdt.managedbuilder.core.prefs", "content": "#Sat Dec 22 00:56:48 EST 2012\r\neclipse.preferences.version=1\r\nenvironment/buildEnvironmentInclude/com.atollic.truestudio.configuration.release.560513466/CPATH/delimiter=;\r\nenvironment/buildEnvironmentInclude/com.atollic.truestudio.configuration.release.560513466/CPATH/operation=remove\r\nenvironment/buildEnvironmentInclude/com.atollic.truestudio.configuration.release.560513466/C_INCLUDE_PATH/delimiter=;\r\nenvironment/buildEnvironmentInclude/com.atollic.truestudio.configuration.release.560513466/C_INCLUDE_PATH/operation=remove\r\nenvironment/buildEnvironmentInclude/com.atollic.truestudio.configuration.release.560513466/append=true\r\nenvironment/buildEnvironmentInclude/com.atollic.truestudio.configuration.release.560513466/appendContributed=true\r\nenvironment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.238007381/CPATH/delimiter=;\r\nenvironment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.238007381/CPATH/operation=remove\r\nenvironment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.238007381/C_INCLUDE_PATH/delimiter=;\r\nenvironment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.238007381/C_INCLUDE_PATH/operation=remove\r\nenvironment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.238007381/append=true\r\nenvironment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.238007381/appendContributed=true\r\nenvironment/buildEnvironmentLibrary/com.atollic.truestudio.configuration.release.560513466/LIBRARY_PATH/delimiter=;\r\nenvironment/buildEnvironmentLibrary/com.atollic.truestudio.configuration.release.560513466/LIBRARY_PATH/operation=remove\r\nenvironment/buildEnvironmentLibrary/com.atollic.truestudio.configuration.release.560513466/append=true\r\nenvironment/buildEnvironmentLibrary/com.atollic.truestudio.configuration.release.560513466/appendContributed=true\r\nenvironment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.238007381/LIBRARY_PATH/delimiter=;\r\nenvironment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.238007381/LIBRARY_PATH/operation=remove\r\nenvironment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.238007381/append=true\r\nenvironment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.238007381/appendContributed=true\r\n" }, { "path": "figure-simulator-discovery/Libraries/CMSIS/Include/arm_common_tables.h", "content": "/* ---------------------------------------------------------------------- \r\n* Copyright (C) 2010 ARM Limited. All rights reserved. \r\n* \r\n* $Date: 11. November 2010 \r\n* $Revision: \tV1.0.2 \r\n* \r\n* Project: \t CMSIS DSP Library \r\n* Title:\t arm_common_tables.h \r\n* \r\n* Description:\tThis file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions \r\n* \r\n* Target Processor: Cortex-M4/Cortex-M3\r\n* \r\n* Version 1.0.2 2010/11/11 \r\n* Documentation updated. \r\n* \r\n* Version 1.0.1 2010/10/05 \r\n* Production release and review comments incorporated. \r\n* \r\n* Version 1.0.0 2010/09/20 \r\n* Production release and review comments incorporated. \r\n* -------------------------------------------------------------------- */ \r\n \r\n#ifndef _ARM_COMMON_TABLES_H \r\n#define _ARM_COMMON_TABLES_H \r\n \r\n#include \"arm_math.h\" \r\n \r\nextern uint16_t armBitRevTable[256]; \r\nextern q15_t armRecipTableQ15[64]; \r\nextern q31_t armRecipTableQ31[64]; \r\nextern const q31_t realCoefAQ31[1024];\r\nextern const q31_t realCoefBQ31[1024];\r\n \r\n#endif /* ARM_COMMON_TABLES_H */ \r\n" }, { "path": "figure-simulator-discovery/Libraries/CMSIS/Include/arm_math.h", "content": "/* ---------------------------------------------------------------------- \r\n * Copyright (C) 2010 ARM Limited. All rights reserved. \r\n * \r\n * $Date: 15. July 2011 \r\n * $Revision: \tV1.0.10 \r\n * \r\n * Project: \t CMSIS DSP Library \r\n * Title:\t arm_math.h\r\n * \r\n * Description:\t Public header file for CMSIS DSP Library\r\n * \r\n * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\r\n * \r\n * Version 1.0.10 2011/7/15 \r\n * Big Endian support added and Merged M0 and M3/M4 Source code. \r\n * \r\n * Version 1.0.3 2010/11/29 \r\n * Re-organized the CMSIS folders and updated documentation. \r\n * \r\n * Version 1.0.2 2010/11/11 \r\n * Documentation updated. \r\n * \r\n * Version 1.0.1 2010/10/05 \r\n * Production release and review comments incorporated. \r\n * \r\n * Version 1.0.0 2010/09/20 \r\n * Production release and review comments incorporated. \r\n * -------------------------------------------------------------------- */\r\n\r\n/**\r\n \\mainpage CMSIS DSP Software Library\r\n *\r\n * Introduction\r\n *\r\n * This user manual describes the CMSIS DSP software library, \r\n * a suite of common signal processing functions for use on Cortex-M processor based devices.\r\n *\r\n * The library is divided into a number of modules each covering a specific category:\r\n * - Basic math functions\r\n * - Fast math functions\r\n * - Complex math functions\r\n * - Filters\r\n * - Matrix functions\r\n * - Transforms\r\n * - Motor control functions\r\n * - Statistical functions\r\n * - Support functions\r\n * - Interpolation functions\r\n *\r\n * The library has separate functions for operating on 8-bit integers, 16-bit integers,\r\n * 32-bit integer and 32-bit floating-point values. \r\n *\r\n * Processor Support\r\n *\r\n * The library is completely written in C and is fully CMSIS compliant. \r\n * High performance is achieved through maximum use of Cortex-M4 intrinsics. \r\n *\r\n * The supplied library source code also builds and runs on the Cortex-M3 and Cortex-M0 processor,\r\n * with the DSP intrinsics being emulated through software. \r\n *\r\n *\r\n * Toolchain Support\r\n *\r\n * The library has been developed and tested with MDK-ARM version 4.21. \r\n * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.\r\n *\r\n * Using the Library\r\n *\r\n * The library installer contains prebuilt versions of the libraries in the Lib folder.\r\n * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)\r\n * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)\r\n * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)\r\n * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)\r\n * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)\r\n * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)\r\n * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)\r\n * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)\r\n *\r\n * The library functions are declared in the public file arm_math.h which is placed in the Include folder.\r\n * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single \r\n * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. \r\n * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or \r\n * ARM_MATH_CM0 depending on the target processor in the application.\r\n *\r\n * Examples\r\n *\r\n * The library ships with a number of examples which demonstrate how to use the library functions.\r\n *\r\n * Building the Library\r\n *\r\n * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder.\r\n * - arm_cortexM0b_math.uvproj\r\n * - arm_cortexM0l_math.uvproj\r\n * - arm_cortexM3b_math.uvproj\r\n * - arm_cortexM3l_math.uvproj \r\n * - arm_cortexM4b_math.uvproj\r\n * - arm_cortexM4l_math.uvproj\r\n * - arm_cortexM4bf_math.uvproj\r\n * - arm_cortexM4lf_math.uvproj\r\n *\r\n * Each library project have differant pre-processor macros.\r\n *\r\n * ARM_MATH_CMx:\r\n * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target\r\n * and ARM_MATH_CM0 for building library on cortex-M0 target.\r\n *\r\n * ARM_MATH_BIG_ENDIAN:\r\n * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.\r\n *\r\n * ARM_MATH_MATRIX_CHECK:\r\n * Define macro for checking on the input and output sizes of matrices\r\n *\r\n * ARM_MATH_ROUNDING:\r\n * Define macro for rounding on support functions\r\n *\r\n * __FPU_PRESENT:\r\n * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries \r\n *\r\n *\r\n * The project can be built by opening the appropriate project in MDK-ARM 4.21 chain and defining the optional pre processor MACROs detailed above.\r\n *\r\n * Copyright Notice\r\n *\r\n * Copyright (C) 2010 ARM Limited. All rights reserved.\r\n */\r\n\r\n\r\n/**\r\n * @defgroup groupMath Basic Math Functions\r\n */\r\n\r\n/**\r\n * @defgroup groupFastMath Fast Math Functions\r\n * This set of functions provides a fast approximation to sine, cosine, and square root.\r\n * As compared to most of the other functions in the CMSIS math library, the fast math functions\r\n * operate on individual values and not arrays.\r\n * There are separate functions for Q15, Q31, and floating-point data.\r\n *\r\n */\r\n\r\n/**\r\n * @defgroup groupCmplxMath Complex Math Functions\r\n * This set of functions operates on complex data vectors.\r\n * The data in the complex arrays is stored in an interleaved fashion\r\n * (real, imag, real, imag, ...).\r\n * In the API functions, the number of samples in a complex array refers\r\n * to the number of complex values; the array contains twice this number of\r\n * real values.\r\n */\r\n\r\n/**\r\n * @defgroup groupFilters Filtering Functions\r\n */\r\n\r\n/**\r\n * @defgroup groupMatrix Matrix Functions\r\n *\r\n * This set of functions provides basic matrix math operations.\r\n * The functions operate on matrix data structures. For example,\r\n * the type\r\n * definition for the floating-point matrix structure is shown\r\n * below:\r\n * 
\r\n *     typedef struct\r\n *     {\r\n *       uint16_t numRows;     // number of rows of the matrix.\r\n *       uint16_t numCols;     // number of columns of the matrix.\r\n *       float32_t *pData;     // points to the data of the matrix.\r\n *     } arm_matrix_instance_f32;\r\n *
\r\n * There are similar definitions for Q15 and Q31 data types.\r\n *\r\n * The structure specifies the size of the matrix and then points to\r\n * an array of data. The array is of size numRows X numCols\r\n * and the values are arranged in row order. That is, the\r\n * matrix element (i, j) is stored at:\r\n * 
\r\n *     pData[i*numCols + j]\r\n *
\r\n *\r\n * \\par Init Functions\r\n * There is an associated initialization function for each type of matrix\r\n * data structure.\r\n * The initialization function sets the values of the internal structure fields.\r\n * Refer to the function arm_mat_init_f32(), arm_mat_init_q31()\r\n * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively.\r\n *\r\n * \\par\r\n * Use of the initialization function is optional. However, if initialization function is used\r\n * then the instance structure cannot be placed into a const data section.\r\n * To place the instance structure in a const data\r\n * section, manually initialize the data structure. For example:\r\n * 
\r\n * arm_matrix_instance_f32 S = {nRows, nColumns, pData};\r\n * arm_matrix_instance_q31 S = {nRows, nColumns, pData};\r\n * arm_matrix_instance_q15 S = {nRows, nColumns, pData};\r\n *
\r\n * where nRows specifies the number of rows, nColumns\r\n * specifies the number of columns, and pData points to the\r\n * data array.\r\n *\r\n * \\par Size Checking\r\n * By default all of the matrix functions perform size checking on the input and\r\n * output matrices. For example, the matrix addition function verifies that the\r\n * two input matrices and the output matrix all have the same number of rows and\r\n * columns. If the size check fails the functions return:\r\n * 
\r\n *     ARM_MATH_SIZE_MISMATCH\r\n *
\r\n * Otherwise the functions return\r\n * 
\r\n *     ARM_MATH_SUCCESS\r\n *
\r\n * There is some overhead associated with this matrix size checking.\r\n * The matrix size checking is enabled via the #define\r\n * 
\r\n *     ARM_MATH_MATRIX_CHECK\r\n *
\r\n * within the library project settings. By default this macro is defined\r\n * and size checking is enabled. By changing the project settings and\r\n * undefining this macro size checking is eliminated and the functions\r\n * run a bit faster. With size checking disabled the functions always\r\n * return ARM_MATH_SUCCESS.\r\n */\r\n\r\n/**\r\n * @defgroup groupTransforms Transform Functions\r\n */\r\n\r\n/**\r\n * @defgroup groupController Controller Functions\r\n */\r\n\r\n/**\r\n * @defgroup groupStats Statistics Functions\r\n */\r\n/**\r\n * @defgroup groupSupport Support Functions\r\n */\r\n\r\n/**\r\n * @defgroup groupInterpolation Interpolation Functions\r\n * These functions perform 1- and 2-dimensional interpolation of data.\r\n * Linear interpolation is used for 1-dimensional data and\r\n * bilinear interpolation is used for 2-dimensional data.\r\n */\r\n\r\n/**\r\n * @defgroup groupExamples Examples\r\n */\r\n#ifndef _ARM_MATH_H\r\n#define _ARM_MATH_H\r\n\r\n#define __CMSIS_GENERIC /* disable NVIC and Systick functions */\r\n\r\n#if defined (ARM_MATH_CM4)\r\n #include \"core_cm4.h\"\r\n#elif defined (ARM_MATH_CM3)\r\n #include \"core_cm3.h\"\r\n#elif defined (ARM_MATH_CM0)\r\n #include \"core_cm0.h\"\r\n#else\r\n#include \"ARMCM4.h\"\r\n#warning \"Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4.....\"\r\n#endif\r\n\r\n#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */\r\n#include \"string.h\"\r\n #include \"math.h\"\r\n#ifdef\t__cplusplus\r\nextern \"C\"\r\n{\r\n#endif\r\n\r\n\r\n /**\r\n * @brief Macros required for reciprocal calculation in Normalized LMS\r\n */\r\n\r\n#define DELTA_Q31 \t\t\t(0x100)\r\n#define DELTA_Q15 \t\t\t0x5\r\n#define INDEX_MASK \t\t\t0x0000003F\r\n#define PI\t\t\t\t\t3.14159265358979f\r\n\r\n /**\r\n * @brief Macros required for SINE and COSINE Fast math approximations\r\n */\r\n\r\n#define TABLE_SIZE\t\t\t256\r\n#define TABLE_SPACING_Q31\t0x800000\r\n#define TABLE_SPACING_Q15\t0x80\r\n\r\n /**\r\n * @brief Macros required for SINE and COSINE Controller functions\r\n */\r\n /* 1.31(q31) Fixed value of 2/360 */\r\n /* -1 to +1 is divided into 360 values so total spacing is (2/360) */\r\n#define INPUT_SPACING\t\t\t0xB60B61\r\n\r\n\r\n /**\r\n * @brief Error status returned by some functions in the library.\r\n */\r\n\r\n typedef enum\r\n {\r\n ARM_MATH_SUCCESS = 0, /**< No error */\r\n ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */\r\n ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */\r\n ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */\r\n ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */\r\n ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */\r\n ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */\r\n } arm_status;\r\n\r\n /**\r\n * @brief 8-bit fractional data type in 1.7 format.\r\n */\r\n typedef int8_t q7_t;\r\n\r\n /**\r\n * @brief 16-bit fractional data type in 1.15 format.\r\n */\r\n typedef int16_t q15_t;\r\n\r\n /**\r\n * @brief 32-bit fractional data type in 1.31 format.\r\n */\r\n typedef int32_t q31_t;\r\n\r\n /**\r\n * @brief 64-bit fractional data type in 1.63 format.\r\n */\r\n typedef int64_t q63_t;\r\n\r\n /**\r\n * @brief 32-bit floating-point type definition.\r\n */\r\n typedef float float32_t;\r\n\r\n /**\r\n * @brief 64-bit floating-point type definition.\r\n */\r\n typedef double float64_t;\r\n\r\n /**\r\n * @brief definition to read/write two 16 bit values.\r\n */\r\n#define __SIMD32(addr) (*(int32_t **) & (addr))\r\n\r\n#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)\r\n /**\r\n * @brief definition to pack two 16 bit values.\r\n */\r\n#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \\\r\n (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )\r\n\r\n#endif\r\n\r\n\r\n /**\r\n * @brief definition to pack four 8 bit values.\r\n */\r\n#ifndef ARM_MATH_BIG_ENDIAN\r\n\r\n#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) |\t\\\r\n (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) |\t\\\r\n\t\t\t\t\t\t\t (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) |\t\\\r\n\t\t\t\t\t\t\t (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )\r\n#else\t\t\t\t\t\t\t\t\r\n\r\n#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) |\t\\\r\n (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) |\t\\\r\n\t\t\t\t\t\t\t (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) |\t\\\r\n\t\t\t\t\t\t\t (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )\r\n\t\t\t\t\t\t\t\t\r\n#endif\r\n\r\n\r\n /**\r\n * @brief Clips Q63 to Q31 values.\r\n */\r\n static __INLINE q31_t clip_q63_to_q31(\r\n\t\t\t\t\tq63_t x)\r\n {\r\n return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\r\n ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;\r\n }\r\n\r\n /**\r\n * @brief Clips Q63 to Q15 values.\r\n */\r\n static __INLINE q15_t clip_q63_to_q15(\r\n\t\t\t\t\tq63_t x)\r\n {\r\n return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\r\n ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);\r\n }\r\n\r\n /**\r\n * @brief Clips Q31 to Q7 values.\r\n */\r\n static __INLINE q7_t clip_q31_to_q7(\r\n\t\t\t\t q31_t x)\r\n {\r\n return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?\r\n ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;\r\n }\r\n\r\n /**\r\n * @brief Clips Q31 to Q15 values.\r\n */\r\n static __INLINE q15_t clip_q31_to_q15(\r\n\t\t\t\t\tq31_t x)\r\n {\r\n return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?\r\n ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;\r\n }\r\n\r\n /**\r\n * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.\r\n */\r\n\r\n static __INLINE q63_t mult32x64(\r\n\t\t\t\t q63_t x,\r\n\t\t\t\t q31_t y)\r\n {\r\n return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +\r\n (((q63_t) (x >> 32) * y)));\r\n }\r\n\r\n\r\n#if defined (ARM_MATH_CM0) && defined ( __CC_ARM )\r\n#define __CLZ __clz\r\n#endif \r\n\r\n#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )\r\n\r\n static __INLINE uint32_t __CLZ(q31_t data);\r\n\r\n\r\n static __INLINE uint32_t __CLZ(q31_t data)\r\n {\r\n\t uint32_t count = 0;\r\n\t uint32_t mask = 0x80000000;\r\n\r\n\t while((data & mask) == 0)\r\n\t {\r\n\t\t count += 1u;\r\n\t\t mask = mask >> 1u;\r\n\t }\r\n\r\n\t return(count);\r\n\r\n }\r\n\r\n#endif \r\n\r\n /**\r\n * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type.\r\n */\r\n\r\n static __INLINE uint32_t arm_recip_q31(\r\n\t\t\t\t\t q31_t in,\r\n\t\t\t\t\t q31_t * dst,\r\n\t\t\t\t\t q31_t * pRecipTable)\r\n {\r\n\r\n uint32_t out, tempVal;\r\n uint32_t index, i;\r\n uint32_t signBits;\r\n\r\n if(in > 0)\r\n {\r\n\tsignBits = __CLZ(in) - 1;\r\n }\r\n else\r\n {\r\n\tsignBits = __CLZ(-in) - 1;\r\n }\r\n\r\n /* Convert input sample to 1.31 format */\r\n in = in << signBits;\r\n\r\n /* calculation of index for initial approximated Val */\r\n index = (uint32_t) (in >> 24u);\r\n index = (index & INDEX_MASK);\r\n\r\n /* 1.31 with exp 1 */\r\n out = pRecipTable[index];\r\n\r\n /* calculation of reciprocal value */\r\n /* running approximation for two iterations */\r\n for (i = 0u; i < 2u; i++)\r\n {\r\n\ttempVal = (q31_t) (((q63_t) in * out) >> 31u);\r\n\ttempVal = 0x7FFFFFFF - tempVal;\r\n\t/* 1.31 with exp 1 */\r\n\t//out = (q31_t) (((q63_t) out * tempVal) >> 30u);\r\n\tout = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);\r\n }\r\n\r\n /* write output */\r\n *dst = out;\r\n\r\n /* return num of signbits of out = 1/in value */\r\n return (signBits + 1u);\r\n\r\n }\r\n\r\n /**\r\n * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type.\r\n */\r\n static __INLINE uint32_t arm_recip_q15(\r\n\t\t\t\t\t q15_t in,\r\n\t\t\t\t\t q15_t * dst,\r\n\t\t\t\t\t q15_t * pRecipTable)\r\n {\r\n\r\n uint32_t out = 0, tempVal = 0;\r\n uint32_t index = 0, i = 0;\r\n uint32_t signBits = 0;\r\n\r\n if(in > 0)\r\n {\r\n\tsignBits = __CLZ(in) - 17;\r\n }\r\n else\r\n {\r\n\tsignBits = __CLZ(-in) - 17;\r\n }\r\n\r\n /* Convert input sample to 1.15 format */\r\n in = in << signBits;\r\n\r\n /* calculation of index for initial approximated Val */\r\n index = in >> 8;\r\n index = (index & INDEX_MASK);\r\n\r\n /* 1.15 with exp 1 */\r\n out = pRecipTable[index];\r\n\r\n /* calculation of reciprocal value */\r\n /* running approximation for two iterations */\r\n for (i = 0; i < 2; i++)\r\n {\r\n\ttempVal = (q15_t) (((q31_t) in * out) >> 15);\r\n\ttempVal = 0x7FFF - tempVal;\r\n\t/* 1.15 with exp 1 */\r\n\tout = (q15_t) (((q31_t) out * tempVal) >> 14);\r\n }\r\n\r\n /* write output */\r\n *dst = out;\r\n\r\n /* return num of signbits of out = 1/in value */\r\n return (signBits + 1);\r\n\r\n }\r\n\r\n\r\n /*\r\n * @brief C custom defined intrinisic function for only M0 processors\r\n */\r\n#if defined(ARM_MATH_CM0)\r\n\r\n static __INLINE q31_t __SSAT(\r\n\t\t\t q31_t x,\r\n\t\t\t uint32_t y)\r\n {\r\n int32_t posMax, negMin;\r\n uint32_t i;\r\n\r\n posMax = 1;\r\n for (i = 0; i < (y - 1); i++)\r\n {\r\n\tposMax = posMax * 2;\r\n }\r\n\r\n if(x > 0)\r\n {\r\n\tposMax = (posMax - 1);\r\n\r\n\tif(x > posMax)\r\n\t {\r\n\t x = posMax;\r\n\t }\r\n }\r\n else\r\n {\r\n\tnegMin = -posMax;\r\n\r\n\tif(x < negMin)\r\n\t {\r\n\t x = negMin;\r\n\t }\r\n }\r\n return (x);\r\n\r\n\r\n }\r\n\r\n#endif /* end of ARM_MATH_CM0 */\r\n\r\n\r\n\r\n /*\r\n * @brief C custom defined intrinsic function for M3 and M0 processors\r\n */\r\n#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)\r\n\r\n /*\r\n * @brief C custom defined QADD8 for M3 and M0 processors\r\n */\r\n static __INLINE q31_t __QADD8(\r\n\t\t\t\tq31_t x,\r\n\t\t\t\tq31_t y)\r\n {\r\n\r\n q31_t sum;\r\n q7_t r, s, t, u;\r\n\r\n r = (char) x;\r\n s = (char) y;\r\n\r\n r = __SSAT((q31_t) (r + s), 8);\r\n s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);\r\n t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);\r\n u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);\r\n\r\n sum = (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |\r\n (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);\r\n\r\n return sum;\r\n\r\n }\r\n\r\n /*\r\n * @brief C custom defined QSUB8 for M3 and M0 processors\r\n */\r\n static __INLINE q31_t __QSUB8(\r\n\t\t\t\tq31_t x,\r\n\t\t\t\tq31_t y)\r\n {\r\n\r\n q31_t sum;\r\n q31_t r, s, t, u;\r\n\r\n r = (char) x;\r\n s = (char) y;\r\n\r\n r = __SSAT((r - s), 8);\r\n s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;\r\n t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;\r\n u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;\r\n\r\n sum =\r\n (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF);\r\n\r\n return sum;\r\n }\r\n\r\n /*\r\n * @brief C custom defined QADD16 for M3 and M0 processors\r\n */\r\n\r\n /*\r\n * @brief C custom defined QADD16 for M3 and M0 processors\r\n */\r\n static __INLINE q31_t __QADD16(\r\n\t\t\t\t q31_t x,\r\n\t\t\t\t q31_t y)\r\n {\r\n\r\n q31_t sum;\r\n q31_t r, s;\r\n\r\n r = (short) x;\r\n s = (short) y;\r\n\r\n r = __SSAT(r + s, 16);\r\n s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;\r\n\r\n sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r\n\r\n return sum;\r\n\r\n }\r\n\r\n /*\r\n * @brief C custom defined SHADD16 for M3 and M0 processors\r\n */\r\n static __INLINE q31_t __SHADD16(\r\n\t\t\t\t q31_t x,\r\n\t\t\t\t q31_t y)\r\n {\r\n\r\n q31_t sum;\r\n q31_t r, s;\r\n\r\n r = (short) x;\r\n s = (short) y;\r\n\r\n r = ((r >> 1) + (s >> 1));\r\n s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;\r\n\r\n sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r\n\r\n return sum;\r\n\r\n }\r\n\r\n /*\r\n * @brief C custom defined QSUB16 for M3 and M0 processors\r\n */\r\n static __INLINE q31_t __QSUB16(\r\n\t\t\t\t q31_t x,\r\n\t\t\t\t q31_t y)\r\n {\r\n\r\n q31_t sum;\r\n q31_t r, s;\r\n\r\n r = (short) x;\r\n s = (short) y;\r\n\r\n r = __SSAT(r - s, 16);\r\n s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;\r\n\r\n sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r\n\r\n return sum;\r\n }\r\n\r\n /*\r\n * @brief C custom defined SHSUB16 for M3 and M0 processors\r\n */\r\n static __INLINE q31_t __SHSUB16(\r\n\t\t\t\t q31_t x,\r\n\t\t\t\t q31_t y)\r\n {\r\n\r\n q31_t diff;\r\n q31_t r, s;\r\n\r\n r = (short) x;\r\n s = (short) y;\r\n\r\n r = ((r >> 1) - (s >> 1));\r\n s = (((x >> 17) - (y >> 17)) << 16);\r\n\r\n diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r\n\r\n return diff;\r\n }\r\n\r\n /*\r\n * @brief C custom defined QASX for M3 and M0 processors\r\n */\r\n static __INLINE q31_t __QASX(\r\n\t\t\t q31_t x,\r\n\t\t\t q31_t y)\r\n {\r\n\r\n q31_t sum = 0;\r\n\r\n sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +\r\n clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));\r\n\r\n return sum;\r\n }\r\n\r\n /*\r\n * @brief C custom defined SHASX for M3 and M0 processors\r\n */\r\n static __INLINE q31_t __SHASX(\r\n\t\t\t\tq31_t x,\r\n\t\t\t\tq31_t y)\r\n {\r\n\r\n q31_t sum;\r\n q31_t r, s;\r\n\r\n r = (short) x;\r\n s = (short) y;\r\n\r\n r = ((r >> 1) - (y >> 17));\r\n s = (((x >> 17) + (s >> 1)) << 16);\r\n\r\n sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r\n\r\n return sum;\r\n }\r\n\r\n\r\n /*\r\n * @brief C custom defined QSAX for M3 and M0 processors\r\n */\r\n static __INLINE q31_t __QSAX(\r\n\t\t\t q31_t x,\r\n\t\t\t q31_t y)\r\n {\r\n\r\n q31_t sum = 0;\r\n\r\n sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +\r\n clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));\r\n\r\n return sum;\r\n }\r\n\r\n /*\r\n * @brief C custom defined SHSAX for M3 and M0 processors\r\n */\r\n static __INLINE q31_t __SHSAX(\r\n\t\t\t\tq31_t x,\r\n\t\t\t\tq31_t y)\r\n {\r\n\r\n q31_t sum;\r\n q31_t r, s;\r\n\r\n r = (short) x;\r\n s = (short) y;\r\n\r\n r = ((r >> 1) + (y >> 17));\r\n s = (((x >> 17) - (s >> 1)) << 16);\r\n\r\n sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r\n\r\n return sum;\r\n }\r\n\r\n /*\r\n * @brief C custom defined SMUSDX for M3 and M0 processors\r\n */\r\n static __INLINE q31_t __SMUSDX(\r\n\t\t\t\t q31_t x,\r\n\t\t\t\t q31_t y)\r\n {\r\n\r\n return ((q31_t)(((short) x * (short) (y >> 16)) -\r\n\t\t ((short) (x >> 16) * (short) y)));\r\n }\r\n\r\n /*\r\n * @brief C custom defined SMUADX for M3 and M0 processors\r\n */\r\n static __INLINE q31_t __SMUADX(\r\n\t\t\t\t q31_t x,\r\n\t\t\t\t q31_t y)\r\n {\r\n\r\n return ((q31_t)(((short) x * (short) (y >> 16)) +\r\n\t\t ((short) (x >> 16) * (short) y)));\r\n }\r\n\r\n /*\r\n * @brief C custom defined QADD for M3 and M0 processors\r\n */\r\n static __INLINE q31_t __QADD(\r\n\t\t\t q31_t x,\r\n\t\t\t q31_t y)\r\n {\r\n return clip_q63_to_q31((q63_t) x + y);\r\n }\r\n\r\n /*\r\n * @brief C custom defined QSUB for M3 and M0 processors\r\n */\r\n static __INLINE q31_t __QSUB(\r\n\t\t\t q31_t x,\r\n\t\t\t q31_t y)\r\n {\r\n return clip_q63_to_q31((q63_t) x - y);\r\n }\r\n\r\n /*\r\n * @brief C custom defined SMLAD for M3 and M0 processors\r\n */\r\n static __INLINE q31_t __SMLAD(\r\n\t\t\t\tq31_t x,\r\n\t\t\t\tq31_t y,\r\n\t\t\t\tq31_t sum)\r\n {\r\n\r\n return (sum + ((short) (x >> 16) * (short) (y >> 16)) +\r\n ((short) x * (short) y));\r\n }\r\n\r\n /*\r\n * @brief C custom defined SMLADX for M3 and M0 processors\r\n */\r\n static __INLINE q31_t __SMLADX(\r\n\t\t\t\t q31_t x,\r\n\t\t\t\t q31_t y,\r\n\t\t\t\t q31_t sum)\r\n {\r\n\r\n return (sum + ((short) (x >> 16) * (short) (y)) +\r\n ((short) x * (short) (y >> 16)));\r\n }\r\n\r\n /*\r\n * @brief C custom defined SMLSDX for M3 and M0 processors\r\n */\r\n static __INLINE q31_t __SMLSDX(\r\n\t\t\t\t q31_t x,\r\n\t\t\t\t q31_t y,\r\n\t\t\t\t q31_t sum)\r\n {\r\n\r\n return (sum - ((short) (x >> 16) * (short) (y)) +\r\n ((short) x * (short) (y >> 16)));\r\n }\r\n\r\n /*\r\n * @brief C custom defined SMLALD for M3 and M0 processors\r\n */\r\n static __INLINE q63_t __SMLALD(\r\n\t\t\t\t q31_t x,\r\n\t\t\t\t q31_t y,\r\n\t\t\t\t q63_t sum)\r\n {\r\n\r\n return (sum + ((short) (x >> 16) * (short) (y >> 16)) +\r\n ((short) x * (short) y));\r\n }\r\n\r\n /*\r\n * @brief C custom defined SMLALDX for M3 and M0 processors\r\n */\r\n static __INLINE q63_t __SMLALDX(\r\n\t\t\t\t q31_t x,\r\n\t\t\t\t q31_t y,\r\n\t\t\t\t q63_t sum)\r\n {\r\n\r\n return (sum + ((short) (x >> 16) * (short) y)) +\r\n ((short) x * (short) (y >> 16));\r\n }\r\n\r\n /*\r\n * @brief C custom defined SMUAD for M3 and M0 processors\r\n */\r\n static __INLINE q31_t __SMUAD(\r\n\t\t\t\tq31_t x,\r\n\t\t\t\tq31_t y)\r\n {\r\n\r\n return (((x >> 16) * (y >> 16)) +\r\n (((x << 16) >> 16) * ((y << 16) >> 16)));\r\n }\r\n\r\n /*\r\n * @brief C custom defined SMUSD for M3 and M0 processors\r\n */\r\n static __INLINE q31_t __SMUSD(\r\n\t\t\t\tq31_t x,\r\n\t\t\t\tq31_t y)\r\n {\r\n\r\n return (-((x >> 16) * (y >> 16)) +\r\n (((x << 16) >> 16) * ((y << 16) >> 16)));\r\n }\r\n\r\n\r\n\r\n\r\n#endif /* (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */\r\n\r\n\r\n /**\r\n * @brief Instance structure for the Q7 FIR filter.\r\n */\r\n typedef struct\r\n {\r\n uint16_t numTaps; /**< number of filter coefficients in the filter. */\r\n q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r\n } arm_fir_instance_q7;\r\n\r\n /**\r\n * @brief Instance structure for the Q15 FIR filter.\r\n */\r\n typedef struct\r\n {\r\n uint16_t numTaps; /**< number of filter coefficients in the filter. */\r\n q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r\n } arm_fir_instance_q15;\r\n\r\n /**\r\n * @brief Instance structure for the Q31 FIR filter.\r\n */\r\n typedef struct\r\n {\r\n uint16_t numTaps; /**< number of filter coefficients in the filter. */\r\n q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r\n } arm_fir_instance_q31;\r\n\r\n /**\r\n * @brief Instance structure for the floating-point FIR filter.\r\n */\r\n typedef struct\r\n {\r\n uint16_t numTaps; /**< number of filter coefficients in the filter. */\r\n float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r\n } arm_fir_instance_f32;\r\n\r\n\r\n /**\r\n * @brief Processing function for the Q7 FIR filter.\r\n * @param[in] *S points to an instance of the Q7 FIR filter structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[out] *pDst points to the block of output data.\r\n * @param[in] blockSize number of samples to process.\r\n * @return none.\r\n */\r\n void arm_fir_q7(\r\n\t\t const arm_fir_instance_q7 * S,\r\n\t\t q7_t * pSrc,\r\n\t\t q7_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n\r\n /**\r\n * @brief Initialization function for the Q7 FIR filter.\r\n * @param[in,out] *S points to an instance of the Q7 FIR structure.\r\n * @param[in] numTaps Number of filter coefficients in the filter.\r\n * @param[in] *pCoeffs points to the filter coefficients.\r\n * @param[in] *pState points to the state buffer.\r\n * @param[in] blockSize number of samples that are processed.\r\n * @return none\r\n */\r\n void arm_fir_init_q7(\r\n\t\t arm_fir_instance_q7 * S,\r\n\t\t uint16_t numTaps,\r\n\t\t q7_t * pCoeffs,\r\n\t\t q7_t * pState,\r\n\t\t uint32_t blockSize);\r\n\r\n\r\n /**\r\n * @brief Processing function for the Q15 FIR filter.\r\n * @param[in] *S points to an instance of the Q15 FIR structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[out] *pDst points to the block of output data.\r\n * @param[in] blockSize number of samples to process.\r\n * @return none.\r\n */\r\n void arm_fir_q15(\r\n\t\t const arm_fir_instance_q15 * S,\r\n\t\t q15_t * pSrc,\r\n\t\t q15_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.\r\n * @param[in] *S points to an instance of the Q15 FIR filter structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[out] *pDst points to the block of output data.\r\n * @param[in] blockSize number of samples to process.\r\n * @return none.\r\n */\r\n void arm_fir_fast_q15(\r\n\t\t\tconst arm_fir_instance_q15 * S,\r\n\t\t\t q15_t * pSrc,\r\n\t\t\tq15_t * pDst,\r\n\t\t\tuint32_t blockSize);\r\n\r\n /**\r\n * @brief Initialization function for the Q15 FIR filter.\r\n * @param[in,out] *S points to an instance of the Q15 FIR filter structure.\r\n * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.\r\n * @param[in] *pCoeffs points to the filter coefficients.\r\n * @param[in] *pState points to the state buffer.\r\n * @param[in] blockSize number of samples that are processed at a time.\r\n * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if\r\n * numTaps is not a supported value.\r\n */\r\n \r\n arm_status arm_fir_init_q15(\r\n\t\t\t arm_fir_instance_q15 * S,\r\n\t\t\t uint16_t numTaps,\r\n\t\t\t q15_t * pCoeffs,\r\n\t\t\t q15_t * pState,\r\n\t\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Processing function for the Q31 FIR filter.\r\n * @param[in] *S points to an instance of the Q31 FIR filter structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[out] *pDst points to the block of output data.\r\n * @param[in] blockSize number of samples to process.\r\n * @return none.\r\n */\r\n void arm_fir_q31(\r\n\t\t const arm_fir_instance_q31 * S,\r\n\t\t q31_t * pSrc,\r\n\t\t q31_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.\r\n * @param[in] *S points to an instance of the Q31 FIR structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[out] *pDst points to the block of output data.\r\n * @param[in] blockSize number of samples to process.\r\n * @return none.\r\n */\r\n void arm_fir_fast_q31(\r\n\t\t\tconst arm_fir_instance_q31 * S,\r\n\t\t\t q31_t * pSrc,\r\n\t\t\tq31_t * pDst,\r\n\t\t\tuint32_t blockSize);\r\n\r\n /**\r\n * @brief Initialization function for the Q31 FIR filter.\r\n * @param[in,out] *S points to an instance of the Q31 FIR structure.\r\n * @param[in] \tnumTaps Number of filter coefficients in the filter.\r\n * @param[in] \t*pCoeffs points to the filter coefficients.\r\n * @param[in] \t*pState points to the state buffer.\r\n * @param[in] \tblockSize number of samples that are processed at a time.\r\n * @return \t\tnone.\r\n */\r\n void arm_fir_init_q31(\r\n\t\t\tarm_fir_instance_q31 * S,\r\n\t\t\tuint16_t numTaps,\r\n\t\t\tq31_t * pCoeffs,\r\n\t\t\tq31_t * pState,\r\n\t\t\tuint32_t blockSize);\r\n\r\n /**\r\n * @brief Processing function for the floating-point FIR filter.\r\n * @param[in] *S points to an instance of the floating-point FIR structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[out] *pDst points to the block of output data.\r\n * @param[in] blockSize number of samples to process.\r\n * @return none.\r\n */\r\n void arm_fir_f32(\r\n\t\t const arm_fir_instance_f32 * S,\r\n\t\t float32_t * pSrc,\r\n\t\t float32_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Initialization function for the floating-point FIR filter.\r\n * @param[in,out] *S points to an instance of the floating-point FIR filter structure.\r\n * @param[in] \tnumTaps Number of filter coefficients in the filter.\r\n * @param[in] \t*pCoeffs points to the filter coefficients.\r\n * @param[in] \t*pState points to the state buffer.\r\n * @param[in] \tblockSize number of samples that are processed at a time.\r\n * @return \tnone.\r\n */\r\n void arm_fir_init_f32(\r\n\t\t\tarm_fir_instance_f32 * S,\r\n\t\t\tuint16_t numTaps,\r\n\t\t\tfloat32_t * pCoeffs,\r\n\t\t\tfloat32_t * pState,\r\n\t\t\tuint32_t blockSize);\r\n\r\n\r\n /**\r\n * @brief Instance structure for the Q15 Biquad cascade filter.\r\n */\r\n typedef struct\r\n {\r\n int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r\n q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r\n q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r\n int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */\r\n\r\n } arm_biquad_casd_df1_inst_q15;\r\n\r\n\r\n /**\r\n * @brief Instance structure for the Q31 Biquad cascade filter.\r\n */\r\n typedef struct\r\n {\r\n uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r\n q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r\n q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r\n uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */\r\n\r\n } arm_biquad_casd_df1_inst_q31;\r\n\r\n /**\r\n * @brief Instance structure for the floating-point Biquad cascade filter.\r\n */\r\n typedef struct\r\n {\r\n uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r\n float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r\n float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r\n\r\n\r\n } arm_biquad_casd_df1_inst_f32;\r\n\r\n\r\n\r\n /**\r\n * @brief Processing function for the Q15 Biquad cascade filter.\r\n * @param[in] *S points to an instance of the Q15 Biquad cascade structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[out] *pDst points to the block of output data.\r\n * @param[in] blockSize number of samples to process.\r\n * @return none.\r\n */\r\n\r\n void arm_biquad_cascade_df1_q15(\r\n\t\t\t\t const arm_biquad_casd_df1_inst_q15 * S,\r\n\t\t\t\t q15_t * pSrc,\r\n\t\t\t\t q15_t * pDst,\r\n\t\t\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Initialization function for the Q15 Biquad cascade filter.\r\n * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure.\r\n * @param[in] numStages number of 2nd order stages in the filter.\r\n * @param[in] *pCoeffs points to the filter coefficients.\r\n * @param[in] *pState points to the state buffer.\r\n * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format\r\n * @return none\r\n */\r\n\r\n void arm_biquad_cascade_df1_init_q15(\r\n\t\t\t\t arm_biquad_casd_df1_inst_q15 * S,\r\n\t\t\t\t uint8_t numStages,\r\n\t\t\t\t q15_t * pCoeffs,\r\n\t\t\t\t q15_t * pState,\r\n\t\t\t\t int8_t postShift);\r\n\r\n\r\n /**\r\n * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.\r\n * @param[in] *S points to an instance of the Q15 Biquad cascade structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[out] *pDst points to the block of output data.\r\n * @param[in] blockSize number of samples to process.\r\n * @return none.\r\n */\r\n\r\n void arm_biquad_cascade_df1_fast_q15(\r\n\t\t\t\t const arm_biquad_casd_df1_inst_q15 * S,\r\n\t\t\t\t q15_t * pSrc,\r\n\t\t\t\t q15_t * pDst,\r\n\t\t\t\t uint32_t blockSize);\r\n\r\n\r\n /**\r\n * @brief Processing function for the Q31 Biquad cascade filter\r\n * @param[in] *S points to an instance of the Q31 Biquad cascade structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[out] *pDst points to the block of output data.\r\n * @param[in] blockSize number of samples to process.\r\n * @return none.\r\n */\r\n\r\n void arm_biquad_cascade_df1_q31(\r\n\t\t\t\t const arm_biquad_casd_df1_inst_q31 * S,\r\n\t\t\t\t q31_t * pSrc,\r\n\t\t\t\t q31_t * pDst,\r\n\t\t\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.\r\n * @param[in] *S points to an instance of the Q31 Biquad cascade structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[out] *pDst points to the block of output data.\r\n * @param[in] blockSize number of samples to process.\r\n * @return none.\r\n */\r\n\r\n void arm_biquad_cascade_df1_fast_q31(\r\n\t\t\t\t const arm_biquad_casd_df1_inst_q31 * S,\r\n\t\t\t\t q31_t * pSrc,\r\n\t\t\t\t q31_t * pDst,\r\n\t\t\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Initialization function for the Q31 Biquad cascade filter.\r\n * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure.\r\n * @param[in] numStages number of 2nd order stages in the filter.\r\n * @param[in] *pCoeffs points to the filter coefficients.\r\n * @param[in] *pState points to the state buffer.\r\n * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format\r\n * @return none\r\n */\r\n\r\n void arm_biquad_cascade_df1_init_q31(\r\n\t\t\t\t arm_biquad_casd_df1_inst_q31 * S,\r\n\t\t\t\t uint8_t numStages,\r\n\t\t\t\t q31_t * pCoeffs,\r\n\t\t\t\t q31_t * pState,\r\n\t\t\t\t int8_t postShift);\r\n\r\n /**\r\n * @brief Processing function for the floating-point Biquad cascade filter.\r\n * @param[in] *S points to an instance of the floating-point Biquad cascade structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[out] *pDst points to the block of output data.\r\n * @param[in] blockSize number of samples to process.\r\n * @return none.\r\n */\r\n\r\n void arm_biquad_cascade_df1_f32(\r\n\t\t\t\t const arm_biquad_casd_df1_inst_f32 * S,\r\n\t\t\t\t float32_t * pSrc,\r\n\t\t\t\t float32_t * pDst,\r\n\t\t\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Initialization function for the floating-point Biquad cascade filter.\r\n * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure.\r\n * @param[in] numStages number of 2nd order stages in the filter.\r\n * @param[in] *pCoeffs points to the filter coefficients.\r\n * @param[in] *pState points to the state buffer.\r\n * @return none\r\n */\r\n\r\n void arm_biquad_cascade_df1_init_f32(\r\n\t\t\t\t arm_biquad_casd_df1_inst_f32 * S,\r\n\t\t\t\t uint8_t numStages,\r\n\t\t\t\t float32_t * pCoeffs,\r\n\t\t\t\t float32_t * pState);\r\n\r\n\r\n /**\r\n * @brief Instance structure for the floating-point matrix structure.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint16_t numRows; /**< number of rows of the matrix. */\r\n uint16_t numCols; /**< number of columns of the matrix. */\r\n float32_t *pData; /**< points to the data of the matrix. */\r\n } arm_matrix_instance_f32;\r\n\r\n /**\r\n * @brief Instance structure for the Q15 matrix structure.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint16_t numRows; /**< number of rows of the matrix. */\r\n uint16_t numCols; /**< number of columns of the matrix. */\r\n q15_t *pData; /**< points to the data of the matrix. */\r\n\r\n } arm_matrix_instance_q15;\r\n\r\n /**\r\n * @brief Instance structure for the Q31 matrix structure.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint16_t numRows; /**< number of rows of the matrix. */\r\n uint16_t numCols; /**< number of columns of the matrix. */\r\n q31_t *pData; /**< points to the data of the matrix. */\r\n\r\n } arm_matrix_instance_q31;\r\n\r\n\r\n\r\n /**\r\n * @brief Floating-point matrix addition.\r\n * @param[in] *pSrcA points to the first input matrix structure\r\n * @param[in] *pSrcB points to the second input matrix structure\r\n * @param[out] *pDst points to output matrix structure\r\n * @return The function returns either\r\n * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.\r\n */\r\n\r\n arm_status arm_mat_add_f32(\r\n\t\t\t const arm_matrix_instance_f32 * pSrcA,\r\n\t\t\t const arm_matrix_instance_f32 * pSrcB,\r\n\t\t\t arm_matrix_instance_f32 * pDst);\r\n\r\n /**\r\n * @brief Q15 matrix addition.\r\n * @param[in] *pSrcA points to the first input matrix structure\r\n * @param[in] *pSrcB points to the second input matrix structure\r\n * @param[out] *pDst points to output matrix structure\r\n * @return The function returns either\r\n * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.\r\n */\r\n\r\n arm_status arm_mat_add_q15(\r\n\t\t\t const arm_matrix_instance_q15 * pSrcA,\r\n\t\t\t const arm_matrix_instance_q15 * pSrcB,\r\n\t\t\t arm_matrix_instance_q15 * pDst);\r\n\r\n /**\r\n * @brief Q31 matrix addition.\r\n * @param[in] *pSrcA points to the first input matrix structure\r\n * @param[in] *pSrcB points to the second input matrix structure\r\n * @param[out] *pDst points to output matrix structure\r\n * @return The function returns either\r\n * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.\r\n */\r\n\r\n arm_status arm_mat_add_q31(\r\n\t\t\t const arm_matrix_instance_q31 * pSrcA,\r\n\t\t\t const arm_matrix_instance_q31 * pSrcB,\r\n\t\t\t arm_matrix_instance_q31 * pDst);\r\n\r\n\r\n /**\r\n * @brief Floating-point matrix transpose.\r\n * @param[in] *pSrc points to the input matrix\r\n * @param[out] *pDst points to the output matrix\r\n * @return \tThe function returns either ARM_MATH_SIZE_MISMATCH\r\n * or ARM_MATH_SUCCESS based on the outcome of size checking.\r\n */\r\n\r\n arm_status arm_mat_trans_f32(\r\n\t\t\t const arm_matrix_instance_f32 * pSrc,\r\n\t\t\t arm_matrix_instance_f32 * pDst);\r\n\r\n\r\n /**\r\n * @brief Q15 matrix transpose.\r\n * @param[in] *pSrc points to the input matrix\r\n * @param[out] *pDst points to the output matrix\r\n * @return \tThe function returns either ARM_MATH_SIZE_MISMATCH\r\n * or ARM_MATH_SUCCESS based on the outcome of size checking.\r\n */\r\n\r\n arm_status arm_mat_trans_q15(\r\n\t\t\t const arm_matrix_instance_q15 * pSrc,\r\n\t\t\t arm_matrix_instance_q15 * pDst);\r\n\r\n /**\r\n * @brief Q31 matrix transpose.\r\n * @param[in] *pSrc points to the input matrix\r\n * @param[out] *pDst points to the output matrix\r\n * @return \tThe function returns either ARM_MATH_SIZE_MISMATCH\r\n * or ARM_MATH_SUCCESS based on the outcome of size checking.\r\n */\r\n\r\n arm_status arm_mat_trans_q31(\r\n\t\t\t const arm_matrix_instance_q31 * pSrc,\r\n\t\t\t arm_matrix_instance_q31 * pDst);\r\n\r\n\r\n /**\r\n * @brief Floating-point matrix multiplication\r\n * @param[in] *pSrcA points to the first input matrix structure\r\n * @param[in] *pSrcB points to the second input matrix structure\r\n * @param[out] *pDst points to output matrix structure\r\n * @return The function returns either\r\n * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.\r\n */\r\n\r\n arm_status arm_mat_mult_f32(\r\n\t\t\t const arm_matrix_instance_f32 * pSrcA,\r\n\t\t\t const arm_matrix_instance_f32 * pSrcB,\r\n\t\t\t arm_matrix_instance_f32 * pDst);\r\n\r\n /**\r\n * @brief Q15 matrix multiplication\r\n * @param[in] *pSrcA points to the first input matrix structure\r\n * @param[in] *pSrcB points to the second input matrix structure\r\n * @param[out] *pDst points to output matrix structure\r\n * @return The function returns either\r\n * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.\r\n */\r\n\r\n arm_status arm_mat_mult_q15(\r\n\t\t\t const arm_matrix_instance_q15 * pSrcA,\r\n\t\t\t const arm_matrix_instance_q15 * pSrcB,\r\n\t\t\t arm_matrix_instance_q15 * pDst,\r\n\t\t\t q15_t * pState);\r\n\r\n /**\r\n * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\r\n * @param[in] *pSrcA points to the first input matrix structure\r\n * @param[in] *pSrcB points to the second input matrix structure\r\n * @param[out] *pDst points to output matrix structure\r\n * @param[in]\t\t *pState points to the array for storing intermediate results \r\n * @return The function returns either\r\n * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.\r\n */\r\n\r\n arm_status arm_mat_mult_fast_q15(\r\n\t\t\t\t const arm_matrix_instance_q15 * pSrcA,\r\n\t\t\t\t const arm_matrix_instance_q15 * pSrcB,\r\n\t\t\t\t arm_matrix_instance_q15 * pDst,\r\n\t\t\t\t q15_t * pState);\r\n\r\n /**\r\n * @brief Q31 matrix multiplication\r\n * @param[in] *pSrcA points to the first input matrix structure\r\n * @param[in] *pSrcB points to the second input matrix structure\r\n * @param[out] *pDst points to output matrix structure\r\n * @return The function returns either\r\n * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.\r\n */\r\n\r\n arm_status arm_mat_mult_q31(\r\n\t\t\t const arm_matrix_instance_q31 * pSrcA,\r\n\t\t\t const arm_matrix_instance_q31 * pSrcB,\r\n\t\t\t arm_matrix_instance_q31 * pDst);\r\n\r\n /**\r\n * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\r\n * @param[in] *pSrcA points to the first input matrix structure\r\n * @param[in] *pSrcB points to the second input matrix structure\r\n * @param[out] *pDst points to output matrix structure\r\n * @return The function returns either\r\n * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.\r\n */\r\n\r\n arm_status arm_mat_mult_fast_q31(\r\n\t\t\t\t const arm_matrix_instance_q31 * pSrcA,\r\n\t\t\t\t const arm_matrix_instance_q31 * pSrcB,\r\n\t\t\t\t arm_matrix_instance_q31 * pDst);\r\n\r\n\r\n /**\r\n * @brief Floating-point matrix subtraction\r\n * @param[in] *pSrcA points to the first input matrix structure\r\n * @param[in] *pSrcB points to the second input matrix structure\r\n * @param[out] *pDst points to output matrix structure\r\n * @return The function returns either\r\n * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.\r\n */\r\n\r\n arm_status arm_mat_sub_f32(\r\n\t\t\t const arm_matrix_instance_f32 * pSrcA,\r\n\t\t\t const arm_matrix_instance_f32 * pSrcB,\r\n\t\t\t arm_matrix_instance_f32 * pDst);\r\n\r\n /**\r\n * @brief Q15 matrix subtraction\r\n * @param[in] *pSrcA points to the first input matrix structure\r\n * @param[in] *pSrcB points to the second input matrix structure\r\n * @param[out] *pDst points to output matrix structure\r\n * @return The function returns either\r\n * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.\r\n */\r\n\r\n arm_status arm_mat_sub_q15(\r\n\t\t\t const arm_matrix_instance_q15 * pSrcA,\r\n\t\t\t const arm_matrix_instance_q15 * pSrcB,\r\n\t\t\t arm_matrix_instance_q15 * pDst);\r\n\r\n /**\r\n * @brief Q31 matrix subtraction\r\n * @param[in] *pSrcA points to the first input matrix structure\r\n * @param[in] *pSrcB points to the second input matrix structure\r\n * @param[out] *pDst points to output matrix structure\r\n * @return The function returns either\r\n * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.\r\n */\r\n\r\n arm_status arm_mat_sub_q31(\r\n\t\t\t const arm_matrix_instance_q31 * pSrcA,\r\n\t\t\t const arm_matrix_instance_q31 * pSrcB,\r\n\t\t\t arm_matrix_instance_q31 * pDst);\r\n\r\n /**\r\n * @brief Floating-point matrix scaling.\r\n * @param[in] *pSrc points to the input matrix\r\n * @param[in] scale scale factor\r\n * @param[out] *pDst points to the output matrix\r\n * @return The function returns either\r\n * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.\r\n */\r\n\r\n arm_status arm_mat_scale_f32(\r\n\t\t\t const arm_matrix_instance_f32 * pSrc,\r\n\t\t\t float32_t scale,\r\n\t\t\t arm_matrix_instance_f32 * pDst);\r\n\r\n /**\r\n * @brief Q15 matrix scaling.\r\n * @param[in] *pSrc points to input matrix\r\n * @param[in] scaleFract fractional portion of the scale factor\r\n * @param[in] shift number of bits to shift the result by\r\n * @param[out] *pDst points to output matrix\r\n * @return The function returns either\r\n * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.\r\n */\r\n\r\n arm_status arm_mat_scale_q15(\r\n\t\t\t const arm_matrix_instance_q15 * pSrc,\r\n\t\t\t q15_t scaleFract,\r\n\t\t\t int32_t shift,\r\n\t\t\t arm_matrix_instance_q15 * pDst);\r\n\r\n /**\r\n * @brief Q31 matrix scaling.\r\n * @param[in] *pSrc points to input matrix\r\n * @param[in] scaleFract fractional portion of the scale factor\r\n * @param[in] shift number of bits to shift the result by\r\n * @param[out] *pDst points to output matrix structure\r\n * @return The function returns either\r\n * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.\r\n */\r\n\r\n arm_status arm_mat_scale_q31(\r\n\t\t\t const arm_matrix_instance_q31 * pSrc,\r\n\t\t\t q31_t scaleFract,\r\n\t\t\t int32_t shift,\r\n\t\t\t arm_matrix_instance_q31 * pDst);\r\n\r\n\r\n /**\r\n * @brief Q31 matrix initialization.\r\n * @param[in,out] *S points to an instance of the floating-point matrix structure.\r\n * @param[in] nRows number of rows in the matrix.\r\n * @param[in] nColumns number of columns in the matrix.\r\n * @param[in] *pData\t points to the matrix data array.\r\n * @return none\r\n */\r\n\r\n void arm_mat_init_q31(\r\n\t\t\tarm_matrix_instance_q31 * S,\r\n\t\t\tuint16_t nRows,\r\n\t\t\tuint16_t nColumns,\r\n\t\t\tq31_t *pData);\r\n\r\n /**\r\n * @brief Q15 matrix initialization.\r\n * @param[in,out] *S points to an instance of the floating-point matrix structure.\r\n * @param[in] nRows number of rows in the matrix.\r\n * @param[in] nColumns number of columns in the matrix.\r\n * @param[in] *pData\t points to the matrix data array.\r\n * @return none\r\n */\r\n\r\n void arm_mat_init_q15(\r\n\t\t\tarm_matrix_instance_q15 * S,\r\n\t\t\tuint16_t nRows,\r\n\t\t\tuint16_t nColumns,\r\n\t\t\tq15_t *pData);\r\n\r\n /**\r\n * @brief Floating-point matrix initialization.\r\n * @param[in,out] *S points to an instance of the floating-point matrix structure.\r\n * @param[in] nRows number of rows in the matrix.\r\n * @param[in] nColumns number of columns in the matrix.\r\n * @param[in] *pData\t points to the matrix data array.\r\n * @return none\r\n */\r\n\r\n void arm_mat_init_f32(\r\n\t\t\tarm_matrix_instance_f32 * S,\r\n\t\t\tuint16_t nRows,\r\n\t\t\tuint16_t nColumns,\r\n\t\t\tfloat32_t *pData);\r\n\r\n\r\n\r\n /**\r\n * @brief Instance structure for the Q15 PID Control.\r\n */\r\n typedef struct\r\n {\r\n q15_t A0; \t /**< The derived gain, A0 = Kp + Ki + Kd . */\r\n\t#ifdef ARM_MATH_CM0 \r\n\tq15_t A1;\r\n\tq15_t A2; \r\n\t#else \t \r\n q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/\r\n\t#endif \r\n q15_t state[3]; /**< The state array of length 3. */\r\n q15_t Kp; /**< The proportional gain. */\r\n q15_t Ki; /**< The integral gain. */\r\n q15_t Kd; /**< The derivative gain. */\r\n } arm_pid_instance_q15;\r\n\r\n /**\r\n * @brief Instance structure for the Q31 PID Control.\r\n */\r\n typedef struct\r\n {\r\n q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r\n q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */\r\n q31_t A2; /**< The derived gain, A2 = Kd . */\r\n q31_t state[3]; /**< The state array of length 3. */\r\n q31_t Kp; /**< The proportional gain. */\r\n q31_t Ki; /**< The integral gain. */\r\n q31_t Kd; /**< The derivative gain. */\r\n\r\n } arm_pid_instance_q31;\r\n\r\n /**\r\n * @brief Instance structure for the floating-point PID Control.\r\n */\r\n typedef struct\r\n {\r\n float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r\n float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */\r\n float32_t A2; /**< The derived gain, A2 = Kd . */\r\n float32_t state[3]; /**< The state array of length 3. */\r\n float32_t Kp; /**< The proportional gain. */\r\n float32_t Ki; /**< The integral gain. */\r\n float32_t Kd; /**< The derivative gain. */\r\n } arm_pid_instance_f32;\r\n\r\n\r\n\r\n /**\r\n * @brief Initialization function for the floating-point PID Control.\r\n * @param[in,out] *S points to an instance of the PID structure.\r\n * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r\n * @return none.\r\n */\r\n void arm_pid_init_f32(\r\n\t\t\tarm_pid_instance_f32 * S,\r\n\t\t\tint32_t resetStateFlag);\r\n\r\n /**\r\n * @brief Reset function for the floating-point PID Control.\r\n * @param[in,out] *S is an instance of the floating-point PID Control structure\r\n * @return none\r\n */\r\n void arm_pid_reset_f32(\r\n\t\t\t arm_pid_instance_f32 * S);\r\n\r\n\r\n /**\r\n * @brief Initialization function for the Q31 PID Control.\r\n * @param[in,out] *S points to an instance of the Q15 PID structure.\r\n * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r\n * @return none.\r\n */\r\n void arm_pid_init_q31(\r\n\t\t\tarm_pid_instance_q31 * S,\r\n\t\t\tint32_t resetStateFlag);\r\n\r\n \r\n /**\r\n * @brief Reset function for the Q31 PID Control.\r\n * @param[in,out] *S points to an instance of the Q31 PID Control structure\r\n * @return none\r\n */\r\n\r\n void arm_pid_reset_q31(\r\n\t\t\t arm_pid_instance_q31 * S);\r\n\r\n /**\r\n * @brief Initialization function for the Q15 PID Control.\r\n * @param[in,out] *S points to an instance of the Q15 PID structure.\r\n * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r\n * @return none.\r\n */\r\n void arm_pid_init_q15(\r\n\t\t\tarm_pid_instance_q15 * S,\r\n\t\t\tint32_t resetStateFlag);\r\n\r\n /**\r\n * @brief Reset function for the Q15 PID Control.\r\n * @param[in,out] *S points to an instance of the q15 PID Control structure\r\n * @return none\r\n */\r\n void arm_pid_reset_q15(\r\n\t\t\t arm_pid_instance_q15 * S);\r\n\r\n\r\n /**\r\n * @brief Instance structure for the floating-point Linear Interpolate function.\r\n */\r\n typedef struct\r\n {\r\n uint32_t nValues;\r\n float32_t x1;\r\n float32_t xSpacing;\r\n float32_t *pYData; /**< pointer to the table of Y values */\r\n } arm_linear_interp_instance_f32;\r\n\r\n /**\r\n * @brief Instance structure for the floating-point bilinear interpolation function.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint16_t numRows;\t/**< number of rows in the data table. */\r\n uint16_t numCols;\t/**< number of columns in the data table. */\r\n float32_t *pData;\t/**< points to the data table. */\r\n } arm_bilinear_interp_instance_f32;\r\n\r\n /**\r\n * @brief Instance structure for the Q31 bilinear interpolation function.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint16_t numRows;\t/**< number of rows in the data table. */\r\n uint16_t numCols;\t/**< number of columns in the data table. */\r\n q31_t *pData;\t/**< points to the data table. */\r\n } arm_bilinear_interp_instance_q31;\r\n\r\n /**\r\n * @brief Instance structure for the Q15 bilinear interpolation function.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint16_t numRows;\t/**< number of rows in the data table. */\r\n uint16_t numCols;\t/**< number of columns in the data table. */\r\n q15_t *pData;\t/**< points to the data table. */\r\n } arm_bilinear_interp_instance_q15;\r\n\r\n /**\r\n * @brief Instance structure for the Q15 bilinear interpolation function.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint16_t numRows; \t/**< number of rows in the data table. */\r\n uint16_t numCols;\t/**< number of columns in the data table. */\r\n q7_t *pData;\t\t/**< points to the data table. */\r\n } arm_bilinear_interp_instance_q7;\r\n\r\n\r\n /**\r\n * @brief Q7 vector multiplication.\r\n * @param[in] *pSrcA points to the first input vector\r\n * @param[in] *pSrcB points to the second input vector\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] blockSize number of samples in each vector\r\n * @return none.\r\n */\r\n\r\n void arm_mult_q7(\r\n\t\t q7_t * pSrcA,\r\n\t\t q7_t * pSrcB,\r\n\t\t q7_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Q15 vector multiplication.\r\n * @param[in] *pSrcA points to the first input vector\r\n * @param[in] *pSrcB points to the second input vector\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] blockSize number of samples in each vector\r\n * @return none.\r\n */\r\n\r\n void arm_mult_q15(\r\n\t\t q15_t * pSrcA,\r\n\t\t q15_t * pSrcB,\r\n\t\t q15_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Q31 vector multiplication.\r\n * @param[in] *pSrcA points to the first input vector\r\n * @param[in] *pSrcB points to the second input vector\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] blockSize number of samples in each vector\r\n * @return none.\r\n */\r\n\r\n void arm_mult_q31(\r\n\t\t q31_t * pSrcA,\r\n\t\t q31_t * pSrcB,\r\n\t\t q31_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Floating-point vector multiplication.\r\n * @param[in] *pSrcA points to the first input vector\r\n * @param[in] *pSrcB points to the second input vector\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] blockSize number of samples in each vector\r\n * @return none.\r\n */\r\n\r\n void arm_mult_f32(\r\n\t\t float32_t * pSrcA,\r\n\t\t float32_t * pSrcB,\r\n\t\t float32_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n\r\n /**\r\n * @brief Instance structure for the Q15 CFFT/CIFFT function.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint16_t fftLen; /**< length of the FFT. */\r\n uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r\n uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r\n q15_t *pTwiddle; /**< points to the twiddle factor table. */\r\n uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r\n uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r\n uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r\n } arm_cfft_radix4_instance_q15;\r\n\r\n /**\r\n * @brief Instance structure for the Q31 CFFT/CIFFT function.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint16_t fftLen; /**< length of the FFT. */\r\n uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r\n uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r\n q31_t *pTwiddle; /**< points to the twiddle factor table. */\r\n uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r\n uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r\n uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r\n } arm_cfft_radix4_instance_q31;\r\n\r\n /**\r\n * @brief Instance structure for the floating-point CFFT/CIFFT function.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint16_t fftLen; /**< length of the FFT. */\r\n uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r\n uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r\n float32_t *pTwiddle; /**< points to the twiddle factor table. */\r\n uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r\n uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r\n uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r\n\tfloat32_t onebyfftLen; /**< value of 1/fftLen. */\r\n } arm_cfft_radix4_instance_f32;\r\n\r\n /**\r\n * @brief Processing function for the Q15 CFFT/CIFFT.\r\n * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure.\r\n * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.\r\n * @return none.\r\n */\r\n\r\n void arm_cfft_radix4_q15(\r\n\t\t\t const arm_cfft_radix4_instance_q15 * S,\r\n\t\t\t q15_t * pSrc);\r\n\r\n /**\r\n * @brief Initialization function for the Q15 CFFT/CIFFT.\r\n * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure.\r\n * @param[in] fftLen length of the FFT.\r\n * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.\r\n * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.\r\n * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.\r\n */\r\n\r\n arm_status arm_cfft_radix4_init_q15(\r\n\t\t\t\t arm_cfft_radix4_instance_q15 * S,\r\n\t\t\t\t uint16_t fftLen,\r\n\t\t\t\t uint8_t ifftFlag,\r\n\t\t\t\t uint8_t bitReverseFlag);\r\n\r\n /**\r\n * @brief Processing function for the Q31 CFFT/CIFFT.\r\n * @param[in] *S points to an instance of the Q31 CFFT/CIFFT structure.\r\n * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.\r\n * @return none.\r\n */\r\n\r\n void arm_cfft_radix4_q31(\r\n\t\t\t const arm_cfft_radix4_instance_q31 * S,\r\n\t\t\t q31_t * pSrc);\r\n\r\n /**\r\n * @brief Initialization function for the Q31 CFFT/CIFFT.\r\n * @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure.\r\n * @param[in] fftLen length of the FFT.\r\n * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.\r\n * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.\r\n * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.\r\n */\r\n \r\n arm_status arm_cfft_radix4_init_q31(\r\n\t\t\t\t arm_cfft_radix4_instance_q31 * S,\r\n\t\t\t\t uint16_t fftLen,\r\n\t\t\t\t uint8_t ifftFlag,\r\n\t\t\t\t uint8_t bitReverseFlag);\r\n\r\n /**\r\n * @brief Processing function for the floating-point CFFT/CIFFT.\r\n * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure.\r\n * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.\r\n * @return none.\r\n */\r\n\r\n void arm_cfft_radix4_f32(\r\n\t\t\t const arm_cfft_radix4_instance_f32 * S,\r\n\t\t\t float32_t * pSrc);\r\n\r\n /**\r\n * @brief Initialization function for the floating-point CFFT/CIFFT.\r\n * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure.\r\n * @param[in] fftLen length of the FFT.\r\n * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.\r\n * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.\r\n * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.\r\n */\r\n \r\n arm_status arm_cfft_radix4_init_f32(\r\n\t\t\t\t arm_cfft_radix4_instance_f32 * S,\r\n\t\t\t\t uint16_t fftLen,\r\n\t\t\t\t uint8_t ifftFlag,\r\n\t\t\t\t uint8_t bitReverseFlag);\r\n\r\n\r\n\r\n /*----------------------------------------------------------------------\r\n *\t\tInternal functions prototypes FFT function\r\n ----------------------------------------------------------------------*/\r\n\r\n /**\r\n * @brief Core function for the floating-point CFFT butterfly process.\r\n * @param[in, out] *pSrc points to the in-place buffer of floating-point data type.\r\n * @param[in] fftLen length of the FFT.\r\n * @param[in] *pCoef points to the twiddle coefficient buffer.\r\n * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.\r\n * @return none.\r\n */\r\n \r\n void arm_radix4_butterfly_f32(\r\n\t\t\t\tfloat32_t * pSrc,\r\n\t\t\t\tuint16_t fftLen,\r\n\t\t\t\tfloat32_t * pCoef,\r\n\t\t\t\tuint16_t twidCoefModifier);\r\n\r\n /**\r\n * @brief Core function for the floating-point CIFFT butterfly process.\r\n * @param[in, out] *pSrc points to the in-place buffer of floating-point data type.\r\n * @param[in] fftLen length of the FFT.\r\n * @param[in] *pCoef points to twiddle coefficient buffer.\r\n * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.\r\n * @param[in] onebyfftLen value of 1/fftLen.\r\n * @return none.\r\n */\r\n \r\n void arm_radix4_butterfly_inverse_f32(\r\n\t\t\t\t\tfloat32_t * pSrc,\r\n\t\t\t\t\tuint16_t fftLen,\r\n\t\t\t\t\tfloat32_t * pCoef,\r\n\t\t\t\t\tuint16_t twidCoefModifier,\r\n\t\t\t\t\tfloat32_t onebyfftLen);\r\n\r\n /**\r\n * @brief In-place bit reversal function.\r\n * @param[in, out] *pSrc points to the in-place buffer of floating-point data type.\r\n * @param[in] fftSize length of the FFT.\r\n * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table.\r\n * @param[in] *pBitRevTab points to the bit reversal table.\r\n * @return none.\r\n */\r\n\r\n void arm_bitreversal_f32(\r\n\t\t\t float32_t *pSrc,\r\n\t\t\t uint16_t fftSize,\r\n\t\t\t uint16_t bitRevFactor,\r\n\t\t\t uint16_t *pBitRevTab);\r\n\r\n /**\r\n * @brief Core function for the Q31 CFFT butterfly process.\r\n * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.\r\n * @param[in] fftLen length of the FFT.\r\n * @param[in] *pCoef points to twiddle coefficient buffer.\r\n * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.\r\n * @return none.\r\n */\r\n \r\n void arm_radix4_butterfly_q31(\r\n\t\t\t\tq31_t *pSrc,\r\n\t\t\t\tuint32_t fftLen,\r\n\t\t\t\tq31_t *pCoef,\r\n\t\t\t\tuint32_t twidCoefModifier);\r\n\r\n /**\r\n * @brief Core function for the Q31 CIFFT butterfly process.\r\n * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.\r\n * @param[in] fftLen length of the FFT.\r\n * @param[in] *pCoef points to twiddle coefficient buffer.\r\n * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.\r\n * @return none.\r\n */\r\n \r\n void arm_radix4_butterfly_inverse_q31(\r\n\t\t\t\t\tq31_t * pSrc,\r\n\t\t\t\t\tuint32_t fftLen,\r\n\t\t\t\t\tq31_t * pCoef,\r\n\t\t\t\t\tuint32_t twidCoefModifier);\r\n \r\n /**\r\n * @brief In-place bit reversal function.\r\n * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.\r\n * @param[in] fftLen length of the FFT.\r\n * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table\r\n * @param[in] *pBitRevTab points to bit reversal table.\r\n * @return none.\r\n */\r\n\r\n void arm_bitreversal_q31(\r\n\t\t\t q31_t * pSrc,\r\n\t\t\t uint32_t fftLen,\r\n\t\t\t uint16_t bitRevFactor,\r\n\t\t\t uint16_t *pBitRevTab);\r\n\r\n /**\r\n * @brief Core function for the Q15 CFFT butterfly process.\r\n * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type.\r\n * @param[in] fftLen length of the FFT.\r\n * @param[in] *pCoef16 points to twiddle coefficient buffer.\r\n * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.\r\n * @return none.\r\n */\r\n\r\n void arm_radix4_butterfly_q15(\r\n\t\t\t\tq15_t *pSrc16,\r\n\t\t\t\tuint32_t fftLen,\r\n\t\t\t\tq15_t *pCoef16,\r\n\t\t\t\tuint32_t twidCoefModifier);\r\n\r\n /**\r\n * @brief Core function for the Q15 CIFFT butterfly process.\r\n * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type.\r\n * @param[in] fftLen length of the FFT.\r\n * @param[in] *pCoef16 points to twiddle coefficient buffer.\r\n * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.\r\n * @return none.\r\n */\r\n\r\n void arm_radix4_butterfly_inverse_q15(\r\n\t\t\t\t\tq15_t *pSrc16,\r\n\t\t\t\t\tuint32_t fftLen,\r\n\t\t\t\t\tq15_t *pCoef16,\r\n\t\t\t\t\tuint32_t twidCoefModifier);\r\n\r\n /**\r\n * @brief In-place bit reversal function.\r\n * @param[in, out] *pSrc points to the in-place buffer of Q15 data type.\r\n * @param[in] fftLen length of the FFT.\r\n * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table\r\n * @param[in] *pBitRevTab points to bit reversal table.\r\n * @return none.\r\n */\r\n\r\n void arm_bitreversal_q15(\r\n\t\t\t q15_t * pSrc,\r\n\t\t\t uint32_t fftLen,\r\n\t\t\t uint16_t bitRevFactor,\r\n\t\t\t uint16_t *pBitRevTab);\r\n\r\n /**\r\n * @brief Instance structure for the Q15 RFFT/RIFFT function.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint32_t fftLenReal; /**< length of the real FFT. */\r\n uint32_t fftLenBy2; /**< length of the complex FFT. */\r\n uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r\n\tuint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r\n uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ \r\n q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r\n q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r\n arm_cfft_radix4_instance_q15 *pCfft;\t /**< points to the complex FFT instance. */\r\n } arm_rfft_instance_q15;\r\n\r\n /**\r\n * @brief Instance structure for the Q31 RFFT/RIFFT function.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint32_t fftLenReal; /**< length of the real FFT. */\r\n uint32_t fftLenBy2; /**< length of the complex FFT. */\r\n uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r\n\tuint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r\n uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r\n q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r\n q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r\n arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */\r\n } arm_rfft_instance_q31;\r\n\r\n /**\r\n * @brief Instance structure for the floating-point RFFT/RIFFT function.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint32_t fftLenReal; /**< length of the real FFT. */\r\n uint16_t fftLenBy2; /**< length of the complex FFT. */\r\n uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r\n uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r\n\tuint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r\n float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r\n float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r\n arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */\r\n } arm_rfft_instance_f32;\r\n\r\n /**\r\n * @brief Processing function for the Q15 RFFT/RIFFT.\r\n * @param[in] *S points to an instance of the Q15 RFFT/RIFFT structure.\r\n * @param[in] *pSrc points to the input buffer.\r\n * @param[out] *pDst points to the output buffer.\r\n * @return none.\r\n */\r\n\r\n void arm_rfft_q15(\r\n\t\t const arm_rfft_instance_q15 * S,\r\n\t\t q15_t * pSrc,\r\n\t\t q15_t * pDst);\r\n\r\n /**\r\n * @brief Initialization function for the Q15 RFFT/RIFFT.\r\n * @param[in, out] *S points to an instance of the Q15 RFFT/RIFFT structure.\r\n * @param[in] *S_CFFT points to an instance of the Q15 CFFT/CIFFT structure.\r\n * @param[in] fftLenReal length of the FFT.\r\n * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.\r\n * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.\r\n * @return\t\tThe function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.\r\n */\r\n\r\n arm_status arm_rfft_init_q15(\r\n\t\t\t arm_rfft_instance_q15 * S,\r\n\t\t\t arm_cfft_radix4_instance_q15 * S_CFFT,\r\n\t\t\t uint32_t fftLenReal,\r\n\t\t\t uint32_t ifftFlagR,\r\n\t\t\t uint32_t bitReverseFlag);\r\n\r\n /**\r\n * @brief Processing function for the Q31 RFFT/RIFFT.\r\n * @param[in] *S points to an instance of the Q31 RFFT/RIFFT structure.\r\n * @param[in] *pSrc points to the input buffer.\r\n * @param[out] *pDst points to the output buffer.\r\n * @return none.\r\n */\r\n\r\n void arm_rfft_q31(\r\n\t\t const arm_rfft_instance_q31 * S,\r\n\t\t q31_t * pSrc,\r\n\t\t q31_t * pDst);\r\n\r\n /**\r\n * @brief Initialization function for the Q31 RFFT/RIFFT.\r\n * @param[in, out] *S points to an instance of the Q31 RFFT/RIFFT structure.\r\n * @param[in, out] *S_CFFT points to an instance of the Q31 CFFT/CIFFT structure.\r\n * @param[in] fftLenReal length of the FFT.\r\n * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.\r\n * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.\r\n * @return\t\tThe function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.\r\n */\r\n\r\n arm_status arm_rfft_init_q31(\r\n\t\t\t arm_rfft_instance_q31 * S,\r\n\t\t\t arm_cfft_radix4_instance_q31 * S_CFFT,\r\n\t\t\t uint32_t fftLenReal,\r\n\t\t\t uint32_t ifftFlagR,\r\n\t\t\t uint32_t bitReverseFlag);\r\n\r\n /**\r\n * @brief Initialization function for the floating-point RFFT/RIFFT.\r\n * @param[in,out] *S points to an instance of the floating-point RFFT/RIFFT structure.\r\n * @param[in,out] *S_CFFT points to an instance of the floating-point CFFT/CIFFT structure.\r\n * @param[in] fftLenReal length of the FFT.\r\n * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.\r\n * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.\r\n * @return\t\tThe function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.\r\n */\r\n\r\n arm_status arm_rfft_init_f32(\r\n\t\t\t arm_rfft_instance_f32 * S,\r\n\t\t\t arm_cfft_radix4_instance_f32 * S_CFFT,\r\n\t\t\t uint32_t fftLenReal,\r\n\t\t\t uint32_t ifftFlagR,\r\n\t\t\t uint32_t bitReverseFlag);\r\n\r\n /**\r\n * @brief Processing function for the floating-point RFFT/RIFFT.\r\n * @param[in] *S points to an instance of the floating-point RFFT/RIFFT structure.\r\n * @param[in] *pSrc points to the input buffer.\r\n * @param[out] *pDst points to the output buffer.\r\n * @return none.\r\n */\r\n\r\n void arm_rfft_f32(\r\n\t\t const arm_rfft_instance_f32 * S,\r\n\t\t float32_t * pSrc,\r\n\t\t float32_t * pDst);\r\n\r\n /**\r\n * @brief Instance structure for the floating-point DCT4/IDCT4 function.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint16_t N; /**< length of the DCT4. */\r\n uint16_t Nby2; /**< half of the length of the DCT4. */\r\n float32_t normalize; /**< normalizing factor. */\r\n float32_t *pTwiddle; /**< points to the twiddle factor table. */\r\n float32_t *pCosFactor; /**< points to the cosFactor table. */\r\n arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */\r\n arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */\r\n } arm_dct4_instance_f32;\r\n\r\n /**\r\n * @brief Initialization function for the floating-point DCT4/IDCT4.\r\n * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure.\r\n * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure.\r\n * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure.\r\n * @param[in] N length of the DCT4.\r\n * @param[in] Nby2 half of the length of the DCT4.\r\n * @param[in] normalize normalizing factor.\r\n * @return\t\tarm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.\r\n */\r\n\r\n arm_status arm_dct4_init_f32(\r\n\t\t\t arm_dct4_instance_f32 * S,\r\n\t\t\t arm_rfft_instance_f32 * S_RFFT,\r\n\t\t\t arm_cfft_radix4_instance_f32 * S_CFFT,\r\n\t\t\t uint16_t N,\r\n\t\t\t uint16_t Nby2,\r\n\t\t\t float32_t normalize);\r\n\r\n /**\r\n * @brief Processing function for the floating-point DCT4/IDCT4.\r\n * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure.\r\n * @param[in] *pState points to state buffer.\r\n * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.\r\n * @return none.\r\n */\r\n\r\n void arm_dct4_f32(\r\n\t\t const arm_dct4_instance_f32 * S,\r\n\t\t float32_t * pState,\r\n\t\t float32_t * pInlineBuffer);\r\n\r\n /**\r\n * @brief Instance structure for the Q31 DCT4/IDCT4 function.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint16_t N; /**< length of the DCT4. */\r\n uint16_t Nby2; /**< half of the length of the DCT4. */\r\n q31_t normalize; /**< normalizing factor. */\r\n q31_t *pTwiddle; /**< points to the twiddle factor table. */\r\n q31_t *pCosFactor; /**< points to the cosFactor table. */\r\n arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */\r\n arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */\r\n } arm_dct4_instance_q31;\r\n\r\n /**\r\n * @brief Initialization function for the Q31 DCT4/IDCT4.\r\n * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure.\r\n * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure\r\n * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure\r\n * @param[in] N length of the DCT4.\r\n * @param[in] Nby2 half of the length of the DCT4.\r\n * @param[in] normalize normalizing factor.\r\n * @return\t\tarm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.\r\n */\r\n\r\n arm_status arm_dct4_init_q31(\r\n\t\t\t arm_dct4_instance_q31 * S,\r\n\t\t\t arm_rfft_instance_q31 * S_RFFT,\r\n\t\t\t arm_cfft_radix4_instance_q31 * S_CFFT,\r\n\t\t\t uint16_t N,\r\n\t\t\t uint16_t Nby2,\r\n\t\t\t q31_t normalize);\r\n\r\n /**\r\n * @brief Processing function for the Q31 DCT4/IDCT4.\r\n * @param[in] *S points to an instance of the Q31 DCT4 structure.\r\n * @param[in] *pState points to state buffer.\r\n * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.\r\n * @return none.\r\n */\r\n\r\n void arm_dct4_q31(\r\n\t\t const arm_dct4_instance_q31 * S,\r\n\t\t q31_t * pState,\r\n\t\t q31_t * pInlineBuffer);\r\n\r\n /**\r\n * @brief Instance structure for the Q15 DCT4/IDCT4 function.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint16_t N; /**< length of the DCT4. */\r\n uint16_t Nby2; /**< half of the length of the DCT4. */\r\n q15_t normalize; /**< normalizing factor. */\r\n q15_t *pTwiddle; /**< points to the twiddle factor table. */\r\n q15_t *pCosFactor; /**< points to the cosFactor table. */\r\n arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */\r\n arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */\r\n } arm_dct4_instance_q15;\r\n\r\n /**\r\n * @brief Initialization function for the Q15 DCT4/IDCT4.\r\n * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure.\r\n * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure.\r\n * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure.\r\n * @param[in] N length of the DCT4.\r\n * @param[in] Nby2 half of the length of the DCT4.\r\n * @param[in] normalize normalizing factor.\r\n * @return\t\tarm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.\r\n */\r\n\r\n arm_status arm_dct4_init_q15(\r\n\t\t\t arm_dct4_instance_q15 * S,\r\n\t\t\t arm_rfft_instance_q15 * S_RFFT,\r\n\t\t\t arm_cfft_radix4_instance_q15 * S_CFFT,\r\n\t\t\t uint16_t N,\r\n\t\t\t uint16_t Nby2,\r\n\t\t\t q15_t normalize);\r\n\r\n /**\r\n * @brief Processing function for the Q15 DCT4/IDCT4.\r\n * @param[in] *S points to an instance of the Q15 DCT4 structure.\r\n * @param[in] *pState points to state buffer.\r\n * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.\r\n * @return none.\r\n */\r\n\r\n void arm_dct4_q15(\r\n\t\t const arm_dct4_instance_q15 * S,\r\n\t\t q15_t * pState,\r\n\t\t q15_t * pInlineBuffer);\r\n\r\n /**\r\n * @brief Floating-point vector addition.\r\n * @param[in] *pSrcA points to the first input vector\r\n * @param[in] *pSrcB points to the second input vector\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] blockSize number of samples in each vector\r\n * @return none.\r\n */\r\n\r\n void arm_add_f32(\r\n\t\t float32_t * pSrcA,\r\n\t\t float32_t * pSrcB,\r\n\t\t float32_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Q7 vector addition.\r\n * @param[in] *pSrcA points to the first input vector\r\n * @param[in] *pSrcB points to the second input vector\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] blockSize number of samples in each vector\r\n * @return none.\r\n */\r\n\r\n void arm_add_q7(\r\n\t\t q7_t * pSrcA,\r\n\t\t q7_t * pSrcB,\r\n\t\t q7_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Q15 vector addition.\r\n * @param[in] *pSrcA points to the first input vector\r\n * @param[in] *pSrcB points to the second input vector\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] blockSize number of samples in each vector\r\n * @return none.\r\n */\r\n\r\n void arm_add_q15(\r\n\t\t q15_t * pSrcA,\r\n\t\t q15_t * pSrcB,\r\n\t\t q15_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Q31 vector addition.\r\n * @param[in] *pSrcA points to the first input vector\r\n * @param[in] *pSrcB points to the second input vector\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] blockSize number of samples in each vector\r\n * @return none.\r\n */\r\n\r\n void arm_add_q31(\r\n\t\t q31_t * pSrcA,\r\n\t\t q31_t * pSrcB,\r\n\t\t q31_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Floating-point vector subtraction.\r\n * @param[in] *pSrcA points to the first input vector\r\n * @param[in] *pSrcB points to the second input vector\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] blockSize number of samples in each vector\r\n * @return none.\r\n */\r\n\r\n void arm_sub_f32(\r\n\t\t float32_t * pSrcA,\r\n\t\t float32_t * pSrcB,\r\n\t\t float32_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Q7 vector subtraction.\r\n * @param[in] *pSrcA points to the first input vector\r\n * @param[in] *pSrcB points to the second input vector\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] blockSize number of samples in each vector\r\n * @return none.\r\n */\r\n\r\n void arm_sub_q7(\r\n\t\t q7_t * pSrcA,\r\n\t\t q7_t * pSrcB,\r\n\t\t q7_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Q15 vector subtraction.\r\n * @param[in] *pSrcA points to the first input vector\r\n * @param[in] *pSrcB points to the second input vector\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] blockSize number of samples in each vector\r\n * @return none.\r\n */\r\n\r\n void arm_sub_q15(\r\n\t\t q15_t * pSrcA,\r\n\t\t q15_t * pSrcB,\r\n\t\t q15_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Q31 vector subtraction.\r\n * @param[in] *pSrcA points to the first input vector\r\n * @param[in] *pSrcB points to the second input vector\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] blockSize number of samples in each vector\r\n * @return none.\r\n */\r\n\r\n void arm_sub_q31(\r\n\t\t q31_t * pSrcA,\r\n\t\t q31_t * pSrcB,\r\n\t\t q31_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Multiplies a floating-point vector by a scalar.\r\n * @param[in] *pSrc points to the input vector\r\n * @param[in] scale scale factor to be applied\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] blockSize number of samples in the vector\r\n * @return none.\r\n */\r\n\r\n void arm_scale_f32(\r\n\t\t float32_t * pSrc,\r\n\t\t float32_t scale,\r\n\t\t float32_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Multiplies a Q7 vector by a scalar.\r\n * @param[in] *pSrc points to the input vector\r\n * @param[in] scaleFract fractional portion of the scale value\r\n * @param[in] shift number of bits to shift the result by\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] blockSize number of samples in the vector\r\n * @return none.\r\n */\r\n\r\n void arm_scale_q7(\r\n\t\t q7_t * pSrc,\r\n\t\t q7_t scaleFract,\r\n\t\t int8_t shift,\r\n\t\t q7_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Multiplies a Q15 vector by a scalar.\r\n * @param[in] *pSrc points to the input vector\r\n * @param[in] scaleFract fractional portion of the scale value\r\n * @param[in] shift number of bits to shift the result by\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] blockSize number of samples in the vector\r\n * @return none.\r\n */\r\n\r\n void arm_scale_q15(\r\n\t\t q15_t * pSrc,\r\n\t\t q15_t scaleFract,\r\n\t\t int8_t shift,\r\n\t\t q15_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Multiplies a Q31 vector by a scalar.\r\n * @param[in] *pSrc points to the input vector\r\n * @param[in] scaleFract fractional portion of the scale value\r\n * @param[in] shift number of bits to shift the result by\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] blockSize number of samples in the vector\r\n * @return none.\r\n */\r\n\r\n void arm_scale_q31(\r\n\t\t q31_t * pSrc,\r\n\t\t q31_t scaleFract,\r\n\t\t int8_t shift,\r\n\t\t q31_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Q7 vector absolute value.\r\n * @param[in] *pSrc points to the input buffer\r\n * @param[out] *pDst points to the output buffer\r\n * @param[in] blockSize number of samples in each vector\r\n * @return none.\r\n */\r\n\r\n void arm_abs_q7(\r\n\t\t q7_t * pSrc,\r\n\t\t q7_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Floating-point vector absolute value.\r\n * @param[in] *pSrc points to the input buffer\r\n * @param[out] *pDst points to the output buffer\r\n * @param[in] blockSize number of samples in each vector\r\n * @return none.\r\n */\r\n\r\n void arm_abs_f32(\r\n\t\t float32_t * pSrc,\r\n\t\t float32_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Q15 vector absolute value.\r\n * @param[in] *pSrc points to the input buffer\r\n * @param[out] *pDst points to the output buffer\r\n * @param[in] blockSize number of samples in each vector\r\n * @return none.\r\n */\r\n\r\n void arm_abs_q15(\r\n\t\t q15_t * pSrc,\r\n\t\t q15_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Q31 vector absolute value.\r\n * @param[in] *pSrc points to the input buffer\r\n * @param[out] *pDst points to the output buffer\r\n * @param[in] blockSize number of samples in each vector\r\n * @return none.\r\n */\r\n\r\n void arm_abs_q31(\r\n\t\t q31_t * pSrc,\r\n\t\t q31_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Dot product of floating-point vectors.\r\n * @param[in] *pSrcA points to the first input vector\r\n * @param[in] *pSrcB points to the second input vector\r\n * @param[in] blockSize number of samples in each vector\r\n * @param[out] *result output result returned here\r\n * @return none.\r\n */\r\n\r\n void arm_dot_prod_f32(\r\n\t\t\t float32_t * pSrcA,\r\n\t\t\t float32_t * pSrcB,\r\n\t\t\tuint32_t blockSize,\r\n\t\t\tfloat32_t * result);\r\n\r\n /**\r\n * @brief Dot product of Q7 vectors.\r\n * @param[in] *pSrcA points to the first input vector\r\n * @param[in] *pSrcB points to the second input vector\r\n * @param[in] blockSize number of samples in each vector\r\n * @param[out] *result output result returned here\r\n * @return none.\r\n */\r\n\r\n void arm_dot_prod_q7(\r\n\t\t q7_t * pSrcA,\r\n\t\t q7_t * pSrcB,\r\n\t\t uint32_t blockSize,\r\n\t\t q31_t * result);\r\n\r\n /**\r\n * @brief Dot product of Q15 vectors.\r\n * @param[in] *pSrcA points to the first input vector\r\n * @param[in] *pSrcB points to the second input vector\r\n * @param[in] blockSize number of samples in each vector\r\n * @param[out] *result output result returned here\r\n * @return none.\r\n */\r\n\r\n void arm_dot_prod_q15(\r\n\t\t\t q15_t * pSrcA,\r\n\t\t\t q15_t * pSrcB,\r\n\t\t\tuint32_t blockSize,\r\n\t\t\tq63_t * result);\r\n\r\n /**\r\n * @brief Dot product of Q31 vectors.\r\n * @param[in] *pSrcA points to the first input vector\r\n * @param[in] *pSrcB points to the second input vector\r\n * @param[in] blockSize number of samples in each vector\r\n * @param[out] *result output result returned here\r\n * @return none.\r\n */\r\n\r\n void arm_dot_prod_q31(\r\n\t\t\t q31_t * pSrcA,\r\n\t\t\t q31_t * pSrcB,\r\n\t\t\tuint32_t blockSize,\r\n\t\t\tq63_t * result);\r\n\r\n /**\r\n * @brief Shifts the elements of a Q7 vector a specified number of bits.\r\n * @param[in] *pSrc points to the input vector\r\n * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] blockSize number of samples in the vector\r\n * @return none.\r\n */\r\n\r\n void arm_shift_q7(\r\n\t\t q7_t * pSrc,\r\n\t\t int8_t shiftBits,\r\n\t\t q7_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Shifts the elements of a Q15 vector a specified number of bits.\r\n * @param[in] *pSrc points to the input vector\r\n * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] blockSize number of samples in the vector\r\n * @return none.\r\n */\r\n\r\n void arm_shift_q15(\r\n\t\t q15_t * pSrc,\r\n\t\t int8_t shiftBits,\r\n\t\t q15_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Shifts the elements of a Q31 vector a specified number of bits.\r\n * @param[in] *pSrc points to the input vector\r\n * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] blockSize number of samples in the vector\r\n * @return none.\r\n */\r\n\r\n void arm_shift_q31(\r\n\t\t q31_t * pSrc,\r\n\t\t int8_t shiftBits,\r\n\t\t q31_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Adds a constant offset to a floating-point vector.\r\n * @param[in] *pSrc points to the input vector\r\n * @param[in] offset is the offset to be added\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] blockSize number of samples in the vector\r\n * @return none.\r\n */\r\n\r\n void arm_offset_f32(\r\n\t\t float32_t * pSrc,\r\n\t\t float32_t offset,\r\n\t\t float32_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Adds a constant offset to a Q7 vector.\r\n * @param[in] *pSrc points to the input vector\r\n * @param[in] offset is the offset to be added\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] blockSize number of samples in the vector\r\n * @return none.\r\n */\r\n\r\n void arm_offset_q7(\r\n\t\t q7_t * pSrc,\r\n\t\t q7_t offset,\r\n\t\t q7_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Adds a constant offset to a Q15 vector.\r\n * @param[in] *pSrc points to the input vector\r\n * @param[in] offset is the offset to be added\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] blockSize number of samples in the vector\r\n * @return none.\r\n */\r\n\r\n void arm_offset_q15(\r\n\t\t q15_t * pSrc,\r\n\t\t q15_t offset,\r\n\t\t q15_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Adds a constant offset to a Q31 vector.\r\n * @param[in] *pSrc points to the input vector\r\n * @param[in] offset is the offset to be added\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] blockSize number of samples in the vector\r\n * @return none.\r\n */\r\n\r\n void arm_offset_q31(\r\n\t\t q31_t * pSrc,\r\n\t\t q31_t offset,\r\n\t\t q31_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Negates the elements of a floating-point vector.\r\n * @param[in] *pSrc points to the input vector\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] blockSize number of samples in the vector\r\n * @return none.\r\n */\r\n\r\n void arm_negate_f32(\r\n\t\t float32_t * pSrc,\r\n\t\t float32_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Negates the elements of a Q7 vector.\r\n * @param[in] *pSrc points to the input vector\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] blockSize number of samples in the vector\r\n * @return none.\r\n */\r\n\r\n void arm_negate_q7(\r\n\t\t q7_t * pSrc,\r\n\t\t q7_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Negates the elements of a Q15 vector.\r\n * @param[in] *pSrc points to the input vector\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] blockSize number of samples in the vector\r\n * @return none.\r\n */\r\n\r\n void arm_negate_q15(\r\n\t\t q15_t * pSrc,\r\n\t\t q15_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Negates the elements of a Q31 vector.\r\n * @param[in] *pSrc points to the input vector\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] blockSize number of samples in the vector\r\n * @return none.\r\n */\r\n\r\n void arm_negate_q31(\r\n\t\t q31_t * pSrc,\r\n\t\t q31_t * pDst,\r\n\t\t uint32_t blockSize);\r\n /**\r\n * @brief Copies the elements of a floating-point vector. \r\n * @param[in] *pSrc input pointer\r\n * @param[out] *pDst output pointer\r\n * @param[in] blockSize number of samples to process\r\n * @return none.\r\n */\r\n void arm_copy_f32(\r\n\t\t float32_t * pSrc,\r\n\t\t float32_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Copies the elements of a Q7 vector. \r\n * @param[in] *pSrc input pointer\r\n * @param[out] *pDst output pointer\r\n * @param[in] blockSize number of samples to process\r\n * @return none.\r\n */\r\n void arm_copy_q7(\r\n\t\t q7_t * pSrc,\r\n\t\t q7_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Copies the elements of a Q15 vector. \r\n * @param[in] *pSrc input pointer\r\n * @param[out] *pDst output pointer\r\n * @param[in] blockSize number of samples to process\r\n * @return none.\r\n */\r\n void arm_copy_q15(\r\n\t\t q15_t * pSrc,\r\n\t\t q15_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Copies the elements of a Q31 vector. \r\n * @param[in] *pSrc input pointer\r\n * @param[out] *pDst output pointer\r\n * @param[in] blockSize number of samples to process\r\n * @return none.\r\n */\r\n void arm_copy_q31(\r\n\t\t q31_t * pSrc,\r\n\t\t q31_t * pDst,\r\n\t\t uint32_t blockSize);\r\n /**\r\n * @brief Fills a constant value into a floating-point vector. \r\n * @param[in] value input value to be filled\r\n * @param[out] *pDst output pointer\r\n * @param[in] blockSize number of samples to process\r\n * @return none.\r\n */\r\n void arm_fill_f32(\r\n\t\t float32_t value,\r\n\t\t float32_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Fills a constant value into a Q7 vector. \r\n * @param[in] value input value to be filled\r\n * @param[out] *pDst output pointer\r\n * @param[in] blockSize number of samples to process\r\n * @return none.\r\n */\r\n void arm_fill_q7(\r\n\t\t q7_t value,\r\n\t\t q7_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Fills a constant value into a Q15 vector. \r\n * @param[in] value input value to be filled\r\n * @param[out] *pDst output pointer\r\n * @param[in] blockSize number of samples to process\r\n * @return none.\r\n */\r\n void arm_fill_q15(\r\n\t\t q15_t value,\r\n\t\t q15_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Fills a constant value into a Q31 vector. \r\n * @param[in] value input value to be filled\r\n * @param[out] *pDst output pointer\r\n * @param[in] blockSize number of samples to process\r\n * @return none.\r\n */\r\n void arm_fill_q31(\r\n\t\t q31_t value,\r\n\t\t q31_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n/** \r\n * @brief Convolution of floating-point sequences. \r\n * @param[in] *pSrcA points to the first input sequence. \r\n * @param[in] srcALen length of the first input sequence. \r\n * @param[in] *pSrcB points to the second input sequence. \r\n * @param[in] srcBLen length of the second input sequence. \r\n * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. \r\n * @return none. \r\n */ \r\n\r\n void arm_conv_f32(\r\n\t\t float32_t * pSrcA,\r\n\t\t uint32_t srcALen,\r\n\t\t float32_t * pSrcB,\r\n\t\t uint32_t srcBLen,\r\n\t\t float32_t * pDst);\r\n\r\n/** \r\n * @brief Convolution of Q15 sequences. \r\n * @param[in] *pSrcA points to the first input sequence. \r\n * @param[in] srcALen length of the first input sequence. \r\n * @param[in] *pSrcB points to the second input sequence. \r\n * @param[in] srcBLen length of the second input sequence. \r\n * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. \r\n * @return none. \r\n */\r\n\r\n void arm_conv_q15(\r\n\t\t q15_t * pSrcA,\r\n\t\t uint32_t srcALen,\r\n\t\t q15_t * pSrcB,\r\n\t\t uint32_t srcBLen,\r\n\t\t q15_t * pDst);\r\n\r\n /**\r\n * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r\n * @param[in] *pSrcA points to the first input sequence.\r\n * @param[in] srcALen length of the first input sequence.\r\n * @param[in] *pSrcB points to the second input sequence.\r\n * @param[in] srcBLen length of the second input sequence.\r\n * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r\n * @return none.\r\n */\r\n\r\n void arm_conv_fast_q15(\r\n\t\t\t q15_t * pSrcA,\r\n\t\t\t uint32_t srcALen,\r\n\t\t\t q15_t * pSrcB,\r\n\t\t\t uint32_t srcBLen,\r\n\t\t\t q15_t * pDst);\r\n\r\n /**\r\n * @brief Convolution of Q31 sequences.\r\n * @param[in] *pSrcA points to the first input sequence.\r\n * @param[in] srcALen length of the first input sequence.\r\n * @param[in] *pSrcB points to the second input sequence.\r\n * @param[in] srcBLen length of the second input sequence.\r\n * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r\n * @return none.\r\n */\r\n\r\n void arm_conv_q31(\r\n\t\t q31_t * pSrcA,\r\n\t\t uint32_t srcALen,\r\n\t\t q31_t * pSrcB,\r\n\t\t uint32_t srcBLen,\r\n\t\t q31_t * pDst);\r\n\r\n /**\r\n * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r\n * @param[in] *pSrcA points to the first input sequence.\r\n * @param[in] srcALen length of the first input sequence.\r\n * @param[in] *pSrcB points to the second input sequence.\r\n * @param[in] srcBLen length of the second input sequence.\r\n * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r\n * @return none.\r\n */\r\n\r\n void arm_conv_fast_q31(\r\n\t\t\t q31_t * pSrcA,\r\n\t\t\t uint32_t srcALen,\r\n\t\t\t q31_t * pSrcB,\r\n\t\t\t uint32_t srcBLen,\r\n\t\t\t q31_t * pDst);\r\n\r\n /**\r\n * @brief Convolution of Q7 sequences.\r\n * @param[in] *pSrcA points to the first input sequence.\r\n * @param[in] srcALen length of the first input sequence.\r\n * @param[in] *pSrcB points to the second input sequence.\r\n * @param[in] srcBLen length of the second input sequence.\r\n * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r\n * @return none.\r\n */\r\n\r\n void arm_conv_q7(\r\n\t\t q7_t * pSrcA,\r\n\t\t uint32_t srcALen,\r\n\t\t q7_t * pSrcB,\r\n\t\t uint32_t srcBLen,\r\n\t\t q7_t * pDst);\r\n\r\n /**\r\n * @brief Partial convolution of floating-point sequences.\r\n * @param[in] *pSrcA points to the first input sequence.\r\n * @param[in] srcALen length of the first input sequence.\r\n * @param[in] *pSrcB points to the second input sequence.\r\n * @param[in] srcBLen length of the second input sequence.\r\n * @param[out] *pDst points to the block of output data\r\n * @param[in] firstIndex is the first output sample to start with.\r\n * @param[in] numPoints is the number of output points to be computed.\r\n * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r\n */\r\n\r\n arm_status arm_conv_partial_f32(\r\n\t\t\t\t float32_t * pSrcA,\r\n\t\t\t\t uint32_t srcALen,\r\n\t\t\t\t float32_t * pSrcB,\r\n\t\t\t\t uint32_t srcBLen,\r\n\t\t\t\t float32_t * pDst,\r\n\t\t\t\t uint32_t firstIndex,\r\n\t\t\t\t uint32_t numPoints);\r\n\r\n /**\r\n * @brief Partial convolution of Q15 sequences.\r\n * @param[in] *pSrcA points to the first input sequence.\r\n * @param[in] srcALen length of the first input sequence.\r\n * @param[in] *pSrcB points to the second input sequence.\r\n * @param[in] srcBLen length of the second input sequence.\r\n * @param[out] *pDst points to the block of output data\r\n * @param[in] firstIndex is the first output sample to start with.\r\n * @param[in] numPoints is the number of output points to be computed.\r\n * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r\n */\r\n\r\n arm_status arm_conv_partial_q15(\r\n\t\t\t\t q15_t * pSrcA,\r\n\t\t\t\t uint32_t srcALen,\r\n\t\t\t\t q15_t * pSrcB,\r\n\t\t\t\t uint32_t srcBLen,\r\n\t\t\t\t q15_t * pDst,\r\n\t\t\t\t uint32_t firstIndex,\r\n\t\t\t\t uint32_t numPoints);\r\n\r\n /**\r\n * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r\n * @param[in] *pSrcA points to the first input sequence.\r\n * @param[in] srcALen length of the first input sequence.\r\n * @param[in] *pSrcB points to the second input sequence.\r\n * @param[in] srcBLen length of the second input sequence.\r\n * @param[out] *pDst points to the block of output data\r\n * @param[in] firstIndex is the first output sample to start with.\r\n * @param[in] numPoints is the number of output points to be computed.\r\n * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r\n */\r\n\r\n arm_status arm_conv_partial_fast_q15(\r\n\t\t\t\t q15_t * pSrcA,\r\n\t\t\t\t uint32_t srcALen,\r\n\t\t\t\t q15_t * pSrcB,\r\n\t\t\t\t uint32_t srcBLen,\r\n\t\t\t\t q15_t * pDst,\r\n\t\t\t\t uint32_t firstIndex,\r\n\t\t\t\t uint32_t numPoints);\r\n\r\n /**\r\n * @brief Partial convolution of Q31 sequences.\r\n * @param[in] *pSrcA points to the first input sequence.\r\n * @param[in] srcALen length of the first input sequence.\r\n * @param[in] *pSrcB points to the second input sequence.\r\n * @param[in] srcBLen length of the second input sequence.\r\n * @param[out] *pDst points to the block of output data\r\n * @param[in] firstIndex is the first output sample to start with.\r\n * @param[in] numPoints is the number of output points to be computed.\r\n * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r\n */\r\n\r\n arm_status arm_conv_partial_q31(\r\n\t\t\t\t q31_t * pSrcA,\r\n\t\t\t\t uint32_t srcALen,\r\n\t\t\t\t q31_t * pSrcB,\r\n\t\t\t\t uint32_t srcBLen,\r\n\t\t\t\t q31_t * pDst,\r\n\t\t\t\t uint32_t firstIndex,\r\n\t\t\t\t uint32_t numPoints);\r\n\r\n\r\n /**\r\n * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r\n * @param[in] *pSrcA points to the first input sequence.\r\n * @param[in] srcALen length of the first input sequence.\r\n * @param[in] *pSrcB points to the second input sequence.\r\n * @param[in] srcBLen length of the second input sequence.\r\n * @param[out] *pDst points to the block of output data\r\n * @param[in] firstIndex is the first output sample to start with.\r\n * @param[in] numPoints is the number of output points to be computed.\r\n * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r\n */\r\n\r\n arm_status arm_conv_partial_fast_q31(\r\n\t\t\t\t q31_t * pSrcA,\r\n\t\t\t\t uint32_t srcALen,\r\n\t\t\t\t q31_t * pSrcB,\r\n\t\t\t\t uint32_t srcBLen,\r\n\t\t\t\t q31_t * pDst,\r\n\t\t\t\t uint32_t firstIndex,\r\n\t\t\t\t uint32_t numPoints);\r\n\r\n /**\r\n * @brief Partial convolution of Q7 sequences.\r\n * @param[in] *pSrcA points to the first input sequence.\r\n * @param[in] srcALen length of the first input sequence.\r\n * @param[in] *pSrcB points to the second input sequence.\r\n * @param[in] srcBLen length of the second input sequence.\r\n * @param[out] *pDst points to the block of output data\r\n * @param[in] firstIndex is the first output sample to start with.\r\n * @param[in] numPoints is the number of output points to be computed.\r\n * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r\n */\r\n\r\n arm_status arm_conv_partial_q7(\r\n\t\t\t\t q7_t * pSrcA,\r\n\t\t\t\t uint32_t srcALen,\r\n\t\t\t\t q7_t * pSrcB,\r\n\t\t\t\t uint32_t srcBLen,\r\n\t\t\t\t q7_t * pDst,\r\n\t\t\t\t uint32_t firstIndex,\r\n\t\t\t\t uint32_t numPoints);\r\n\r\n\r\n /**\r\n * @brief Instance structure for the Q15 FIR decimator.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint8_t M; /**< decimation factor. */\r\n uint16_t numTaps; /**< number of coefficients in the filter. */\r\n q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r\n q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n } arm_fir_decimate_instance_q15;\r\n\r\n /**\r\n * @brief Instance structure for the Q31 FIR decimator.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint8_t M; /**< decimation factor. */\r\n uint16_t numTaps; /**< number of coefficients in the filter. */\r\n q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r\n q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n\r\n } arm_fir_decimate_instance_q31;\r\n\r\n /**\r\n * @brief Instance structure for the floating-point FIR decimator.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint8_t M; /**< decimation factor. */\r\n uint16_t numTaps; /**< number of coefficients in the filter. */\r\n float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r\n float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n\r\n } arm_fir_decimate_instance_f32;\r\n\r\n\r\n\r\n /**\r\n * @brief Processing function for the floating-point FIR decimator.\r\n * @param[in] *S points to an instance of the floating-point FIR decimator structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[out] *pDst points to the block of output data\r\n * @param[in] blockSize number of input samples to process per call.\r\n * @return none\r\n */\r\n\r\n void arm_fir_decimate_f32(\r\n\t\t\t const arm_fir_decimate_instance_f32 * S,\r\n\t\t\t float32_t * pSrc,\r\n\t\t\t float32_t * pDst,\r\n\t\t\t uint32_t blockSize);\r\n\r\n\r\n /**\r\n * @brief Initialization function for the floating-point FIR decimator.\r\n * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.\r\n * @param[in] numTaps number of coefficients in the filter.\r\n * @param[in] M decimation factor.\r\n * @param[in] *pCoeffs points to the filter coefficients.\r\n * @param[in] *pState points to the state buffer.\r\n * @param[in] blockSize number of input samples to process per call.\r\n * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r\n * blockSize is not a multiple of M.\r\n */\r\n\r\n arm_status arm_fir_decimate_init_f32(\r\n\t\t\t\t arm_fir_decimate_instance_f32 * S,\r\n\t\t\t\t uint16_t numTaps,\r\n\t\t\t\t uint8_t M,\r\n\t\t\t\t float32_t * pCoeffs,\r\n\t\t\t\t float32_t * pState,\r\n\t\t\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Processing function for the Q15 FIR decimator.\r\n * @param[in] *S points to an instance of the Q15 FIR decimator structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[out] *pDst points to the block of output data\r\n * @param[in] blockSize number of input samples to process per call.\r\n * @return none\r\n */\r\n\r\n void arm_fir_decimate_q15(\r\n\t\t\t const arm_fir_decimate_instance_q15 * S,\r\n\t\t\t q15_t * pSrc,\r\n\t\t\t q15_t * pDst,\r\n\t\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\r\n * @param[in] *S points to an instance of the Q15 FIR decimator structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[out] *pDst points to the block of output data\r\n * @param[in] blockSize number of input samples to process per call.\r\n * @return none\r\n */\r\n\r\n void arm_fir_decimate_fast_q15(\r\n\t\t\t\t const arm_fir_decimate_instance_q15 * S,\r\n\t\t\t\t q15_t * pSrc,\r\n\t\t\t\t q15_t * pDst,\r\n\t\t\t\t uint32_t blockSize);\r\n\r\n\r\n\r\n /**\r\n * @brief Initialization function for the Q15 FIR decimator.\r\n * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.\r\n * @param[in] numTaps number of coefficients in the filter.\r\n * @param[in] M decimation factor.\r\n * @param[in] *pCoeffs points to the filter coefficients.\r\n * @param[in] *pState points to the state buffer.\r\n * @param[in] blockSize number of input samples to process per call.\r\n * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r\n * blockSize is not a multiple of M.\r\n */\r\n\r\n arm_status arm_fir_decimate_init_q15(\r\n\t\t\t\t arm_fir_decimate_instance_q15 * S,\r\n\t\t\t\t uint16_t numTaps,\r\n\t\t\t\t uint8_t M,\r\n\t\t\t\t q15_t * pCoeffs,\r\n\t\t\t\t q15_t * pState,\r\n\t\t\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Processing function for the Q31 FIR decimator.\r\n * @param[in] *S points to an instance of the Q31 FIR decimator structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[out] *pDst points to the block of output data\r\n * @param[in] blockSize number of input samples to process per call.\r\n * @return none\r\n */\r\n\r\n void arm_fir_decimate_q31(\r\n\t\t\t const arm_fir_decimate_instance_q31 * S,\r\n\t\t\t q31_t * pSrc,\r\n\t\t\t q31_t * pDst,\r\n\t\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\r\n * @param[in] *S points to an instance of the Q31 FIR decimator structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[out] *pDst points to the block of output data\r\n * @param[in] blockSize number of input samples to process per call.\r\n * @return none\r\n */\r\n\r\n void arm_fir_decimate_fast_q31(\r\n\t\t\t\t arm_fir_decimate_instance_q31 * S,\r\n\t\t\t\t q31_t * pSrc,\r\n\t\t\t\t q31_t * pDst,\r\n\t\t\t\t uint32_t blockSize);\r\n\r\n\r\n /**\r\n * @brief Initialization function for the Q31 FIR decimator.\r\n * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.\r\n * @param[in] numTaps number of coefficients in the filter.\r\n * @param[in] M decimation factor.\r\n * @param[in] *pCoeffs points to the filter coefficients.\r\n * @param[in] *pState points to the state buffer.\r\n * @param[in] blockSize number of input samples to process per call.\r\n * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r\n * blockSize is not a multiple of M.\r\n */\r\n\r\n arm_status arm_fir_decimate_init_q31(\r\n\t\t\t\t arm_fir_decimate_instance_q31 * S,\r\n\t\t\t\t uint16_t numTaps,\r\n\t\t\t\t uint8_t M,\r\n\t\t\t\t q31_t * pCoeffs,\r\n\t\t\t\t q31_t * pState,\r\n\t\t\t\t uint32_t blockSize);\r\n\r\n\r\n\r\n /**\r\n * @brief Instance structure for the Q15 FIR interpolator.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint8_t L; /**< upsample factor. */\r\n uint16_t phaseLength; /**< length of each polyphase filter component. */\r\n q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r\n q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\r\n } arm_fir_interpolate_instance_q15;\r\n\r\n /**\r\n * @brief Instance structure for the Q31 FIR interpolator.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint8_t L; /**< upsample factor. */\r\n uint16_t phaseLength; /**< length of each polyphase filter component. */\r\n q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r\n q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\r\n } arm_fir_interpolate_instance_q31;\r\n\r\n /**\r\n * @brief Instance structure for the floating-point FIR interpolator.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint8_t L; /**< upsample factor. */\r\n uint16_t phaseLength; /**< length of each polyphase filter component. */\r\n float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r\n float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */\r\n } arm_fir_interpolate_instance_f32;\r\n\r\n\r\n /**\r\n * @brief Processing function for the Q15 FIR interpolator.\r\n * @param[in] *S points to an instance of the Q15 FIR interpolator structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[out] *pDst points to the block of output data.\r\n * @param[in] blockSize number of input samples to process per call.\r\n * @return none.\r\n */\r\n\r\n void arm_fir_interpolate_q15(\r\n\t\t\t const arm_fir_interpolate_instance_q15 * S,\r\n\t\t\t q15_t * pSrc,\r\n\t\t\t q15_t * pDst,\r\n\t\t\t uint32_t blockSize);\r\n\r\n\r\n /**\r\n * @brief Initialization function for the Q15 FIR interpolator.\r\n * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure.\r\n * @param[in] L upsample factor.\r\n * @param[in] numTaps number of filter coefficients in the filter.\r\n * @param[in] *pCoeffs points to the filter coefficient buffer.\r\n * @param[in] *pState points to the state buffer.\r\n * @param[in] blockSize number of input samples to process per call.\r\n * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r\n * the filter length numTaps is not a multiple of the interpolation factor L.\r\n */\r\n\r\n arm_status arm_fir_interpolate_init_q15(\r\n\t\t\t\t\t arm_fir_interpolate_instance_q15 * S,\r\n\t\t\t\t\t uint8_t L,\r\n\t\t\t\t\t uint16_t numTaps,\r\n\t\t\t\t\t q15_t * pCoeffs,\r\n\t\t\t\t\t q15_t * pState,\r\n\t\t\t\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Processing function for the Q31 FIR interpolator.\r\n * @param[in] *S points to an instance of the Q15 FIR interpolator structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[out] *pDst points to the block of output data.\r\n * @param[in] blockSize number of input samples to process per call.\r\n * @return none.\r\n */\r\n\r\n void arm_fir_interpolate_q31(\r\n\t\t\t const arm_fir_interpolate_instance_q31 * S,\r\n\t\t\t q31_t * pSrc,\r\n\t\t\t q31_t * pDst,\r\n\t\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Initialization function for the Q31 FIR interpolator.\r\n * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure.\r\n * @param[in] L upsample factor.\r\n * @param[in] numTaps number of filter coefficients in the filter.\r\n * @param[in] *pCoeffs points to the filter coefficient buffer.\r\n * @param[in] *pState points to the state buffer.\r\n * @param[in] blockSize number of input samples to process per call.\r\n * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r\n * the filter length numTaps is not a multiple of the interpolation factor L.\r\n */\r\n\r\n arm_status arm_fir_interpolate_init_q31(\r\n\t\t\t\t\t arm_fir_interpolate_instance_q31 * S,\r\n\t\t\t\t\t uint8_t L,\r\n\t\t\t\t\t uint16_t numTaps,\r\n\t\t\t\t\t q31_t * pCoeffs,\r\n\t\t\t\t\t q31_t * pState,\r\n\t\t\t\t\t uint32_t blockSize);\r\n\r\n\r\n /**\r\n * @brief Processing function for the floating-point FIR interpolator.\r\n * @param[in] *S points to an instance of the floating-point FIR interpolator structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[out] *pDst points to the block of output data.\r\n * @param[in] blockSize number of input samples to process per call.\r\n * @return none.\r\n */\r\n\r\n void arm_fir_interpolate_f32(\r\n\t\t\t const arm_fir_interpolate_instance_f32 * S,\r\n\t\t\t float32_t * pSrc,\r\n\t\t\t float32_t * pDst,\r\n\t\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Initialization function for the floating-point FIR interpolator.\r\n * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure.\r\n * @param[in] L upsample factor.\r\n * @param[in] numTaps number of filter coefficients in the filter.\r\n * @param[in] *pCoeffs points to the filter coefficient buffer.\r\n * @param[in] *pState points to the state buffer.\r\n * @param[in] blockSize number of input samples to process per call.\r\n * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r\n * the filter length numTaps is not a multiple of the interpolation factor L.\r\n */\r\n\r\n arm_status arm_fir_interpolate_init_f32(\r\n\t\t\t\t\t arm_fir_interpolate_instance_f32 * S,\r\n\t\t\t\t\t uint8_t L,\r\n\t\t\t\t\t uint16_t numTaps,\r\n\t\t\t\t\t float32_t * pCoeffs,\r\n\t\t\t\t\t float32_t * pState,\r\n\t\t\t\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Instance structure for the high precision Q31 Biquad cascade filter.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r\n q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */\r\n q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r\n uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */\r\n\r\n } arm_biquad_cas_df1_32x64_ins_q31;\r\n\r\n\r\n /**\r\n * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[out] *pDst points to the block of output data\r\n * @param[in] blockSize number of samples to process.\r\n * @return none.\r\n */\r\n\r\n void arm_biquad_cas_df1_32x64_q31(\r\n\t\t\t\t const arm_biquad_cas_df1_32x64_ins_q31 * S,\r\n\t\t\t\t q31_t * pSrc,\r\n\t\t\t\t q31_t * pDst,\r\n\t\t\t\t uint32_t blockSize);\r\n\r\n\r\n /**\r\n * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure.\r\n * @param[in] numStages number of 2nd order stages in the filter.\r\n * @param[in] *pCoeffs points to the filter coefficients.\r\n * @param[in] *pState points to the state buffer.\r\n * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format\r\n * @return none\r\n */\r\n\r\n void arm_biquad_cas_df1_32x64_init_q31(\r\n\t\t\t\t\t arm_biquad_cas_df1_32x64_ins_q31 * S,\r\n\t\t\t\t\t uint8_t numStages,\r\n\t\t\t\t\t q31_t * pCoeffs,\r\n\t\t\t\t\t q63_t * pState,\r\n\t\t\t\t\t uint8_t postShift);\r\n\r\n\r\n\r\n /**\r\n * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r\n float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */\r\n float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r\n } arm_biquad_cascade_df2T_instance_f32;\r\n\r\n\r\n /**\r\n * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.\r\n * @param[in] *S points to an instance of the filter data structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[out] *pDst points to the block of output data\r\n * @param[in] blockSize number of samples to process.\r\n * @return none.\r\n */\r\n\r\n void arm_biquad_cascade_df2T_f32(\r\n\t\t\t\t const arm_biquad_cascade_df2T_instance_f32 * S,\r\n\t\t\t\t float32_t * pSrc,\r\n\t\t\t\t float32_t * pDst,\r\n\t\t\t\t uint32_t blockSize);\r\n\r\n\r\n /**\r\n * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r\n * @param[in,out] *S points to an instance of the filter data structure.\r\n * @param[in] numStages number of 2nd order stages in the filter.\r\n * @param[in] *pCoeffs points to the filter coefficients.\r\n * @param[in] *pState points to the state buffer.\r\n * @return none\r\n */\r\n\r\n void arm_biquad_cascade_df2T_init_f32(\r\n\t\t\t\t\tarm_biquad_cascade_df2T_instance_f32 * S,\r\n\t\t\t\t\tuint8_t numStages,\r\n\t\t\t\t\tfloat32_t * pCoeffs,\r\n\t\t\t\t\tfloat32_t * pState);\r\n\r\n\r\n\r\n /**\r\n * @brief Instance structure for the Q15 FIR lattice filter.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint16_t numStages; /**< number of filter stages. */\r\n q15_t *pState; /**< points to the state variable array. The array is of length numStages. */\r\n q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r\n } arm_fir_lattice_instance_q15;\r\n\r\n /**\r\n * @brief Instance structure for the Q31 FIR lattice filter.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint16_t numStages; /**< number of filter stages. */\r\n q31_t *pState; /**< points to the state variable array. The array is of length numStages. */\r\n q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r\n } arm_fir_lattice_instance_q31;\r\n\r\n /**\r\n * @brief Instance structure for the floating-point FIR lattice filter.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint16_t numStages; /**< number of filter stages. */\r\n float32_t *pState; /**< points to the state variable array. The array is of length numStages. */\r\n float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r\n } arm_fir_lattice_instance_f32;\r\n\r\n /**\r\n * @brief Initialization function for the Q15 FIR lattice filter.\r\n * @param[in] *S points to an instance of the Q15 FIR lattice structure.\r\n * @param[in] numStages number of filter stages.\r\n * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. \r\n * @param[in] *pState points to the state buffer. The array is of length numStages. \r\n * @return none.\r\n */\r\n\r\n void arm_fir_lattice_init_q15(\r\n\t\t\t\tarm_fir_lattice_instance_q15 * S,\r\n\t\t\t\tuint16_t numStages,\r\n\t\t\t\tq15_t * pCoeffs,\r\n\t\t\t\tq15_t * pState);\r\n\r\n\r\n /**\r\n * @brief Processing function for the Q15 FIR lattice filter.\r\n * @param[in] *S points to an instance of the Q15 FIR lattice structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[out] *pDst points to the block of output data.\r\n * @param[in] blockSize number of samples to process.\r\n * @return none.\r\n */\r\n void arm_fir_lattice_q15(\r\n\t\t\t const arm_fir_lattice_instance_q15 * S,\r\n\t\t\t q15_t * pSrc,\r\n\t\t\t q15_t * pDst,\r\n\t\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Initialization function for the Q31 FIR lattice filter.\r\n * @param[in] *S points to an instance of the Q31 FIR lattice structure.\r\n * @param[in] numStages number of filter stages.\r\n * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.\r\n * @param[in] *pState points to the state buffer. The array is of length numStages.\r\n * @return none.\r\n */\r\n\r\n void arm_fir_lattice_init_q31(\r\n\t\t\t\tarm_fir_lattice_instance_q31 * S,\r\n\t\t\t\tuint16_t numStages,\r\n\t\t\t\tq31_t * pCoeffs,\r\n\t\t\t\tq31_t * pState);\r\n\r\n\r\n /**\r\n * @brief Processing function for the Q31 FIR lattice filter.\r\n * @param[in] *S points to an instance of the Q31 FIR lattice structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[out] *pDst points to the block of output data\r\n * @param[in] blockSize number of samples to process.\r\n * @return none.\r\n */\r\n\r\n void arm_fir_lattice_q31(\r\n\t\t\t const arm_fir_lattice_instance_q31 * S,\r\n\t\t\t q31_t * pSrc,\r\n\t\t\t q31_t * pDst,\r\n\t\t\t uint32_t blockSize);\r\n\r\n/**\r\n * @brief Initialization function for the floating-point FIR lattice filter.\r\n * @param[in] *S points to an instance of the floating-point FIR lattice structure.\r\n * @param[in] numStages number of filter stages.\r\n * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.\r\n * @param[in] *pState points to the state buffer. The array is of length numStages.\r\n * @return none.\r\n */\r\n\r\n void arm_fir_lattice_init_f32(\r\n\t\t\t\tarm_fir_lattice_instance_f32 * S,\r\n\t\t\t\tuint16_t numStages,\r\n\t\t\t\tfloat32_t * pCoeffs,\r\n\t\t\t\tfloat32_t * pState);\r\n\r\n /**\r\n * @brief Processing function for the floating-point FIR lattice filter.\r\n * @param[in] *S points to an instance of the floating-point FIR lattice structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[out] *pDst points to the block of output data\r\n * @param[in] blockSize number of samples to process.\r\n * @return none.\r\n */\r\n\r\n void arm_fir_lattice_f32(\r\n\t\t\t const arm_fir_lattice_instance_f32 * S,\r\n\t\t\t float32_t * pSrc,\r\n\t\t\t float32_t * pDst,\r\n\t\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Instance structure for the Q15 IIR lattice filter.\r\n */\r\n typedef struct\r\n {\r\n uint16_t numStages; /**< number of stages in the filter. */\r\n q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r\n q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r\n q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r\n } arm_iir_lattice_instance_q15;\r\n\r\n /**\r\n * @brief Instance structure for the Q31 IIR lattice filter.\r\n */\r\n typedef struct\r\n {\r\n uint16_t numStages; /**< number of stages in the filter. */\r\n q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r\n q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r\n q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r\n } arm_iir_lattice_instance_q31;\r\n\r\n /**\r\n * @brief Instance structure for the floating-point IIR lattice filter.\r\n */\r\n typedef struct\r\n {\r\n uint16_t numStages; /**< number of stages in the filter. */\r\n float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r\n float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r\n float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r\n } arm_iir_lattice_instance_f32;\r\n\r\n /**\r\n * @brief Processing function for the floating-point IIR lattice filter.\r\n * @param[in] *S points to an instance of the floating-point IIR lattice structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[out] *pDst points to the block of output data.\r\n * @param[in] blockSize number of samples to process.\r\n * @return none.\r\n */\r\n\r\n void arm_iir_lattice_f32(\r\n\t\t\t const arm_iir_lattice_instance_f32 * S,\r\n\t\t\t float32_t * pSrc,\r\n\t\t\t float32_t * pDst,\r\n\t\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Initialization function for the floating-point IIR lattice filter.\r\n * @param[in] *S points to an instance of the floating-point IIR lattice structure.\r\n * @param[in] numStages number of stages in the filter.\r\n * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.\r\n * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.\r\n * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1.\r\n * @param[in] blockSize number of samples to process.\r\n * @return none.\r\n */\r\n\r\n void arm_iir_lattice_init_f32(\r\n\t\t\t\tarm_iir_lattice_instance_f32 * S,\r\n\t\t\t\tuint16_t numStages,\r\n\t\t\t\tfloat32_t *pkCoeffs,\r\n\t\t\t\tfloat32_t *pvCoeffs,\r\n\t\t\t\tfloat32_t *pState,\r\n\t\t\t\tuint32_t blockSize);\r\n\r\n\r\n /**\r\n * @brief Processing function for the Q31 IIR lattice filter.\r\n * @param[in] *S points to an instance of the Q31 IIR lattice structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[out] *pDst points to the block of output data.\r\n * @param[in] blockSize number of samples to process.\r\n * @return none.\r\n */\r\n\r\n void arm_iir_lattice_q31(\r\n\t\t\t const arm_iir_lattice_instance_q31 * S,\r\n\t\t\t q31_t * pSrc,\r\n\t\t\t q31_t * pDst,\r\n\t\t\t uint32_t blockSize);\r\n\r\n\r\n /**\r\n * @brief Initialization function for the Q31 IIR lattice filter.\r\n * @param[in] *S points to an instance of the Q31 IIR lattice structure.\r\n * @param[in] numStages number of stages in the filter.\r\n * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.\r\n * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.\r\n * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize.\r\n * @param[in] blockSize number of samples to process.\r\n * @return none.\r\n */\r\n\r\n void arm_iir_lattice_init_q31(\r\n\t\t\t\tarm_iir_lattice_instance_q31 * S,\r\n\t\t\t\tuint16_t numStages,\r\n\t\t\t\tq31_t *pkCoeffs,\r\n\t\t\t\tq31_t *pvCoeffs,\r\n\t\t\t\tq31_t *pState,\r\n\t\t\t\tuint32_t blockSize);\r\n\r\n\r\n /**\r\n * @brief Processing function for the Q15 IIR lattice filter.\r\n * @param[in] *S points to an instance of the Q15 IIR lattice structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[out] *pDst points to the block of output data.\r\n * @param[in] blockSize number of samples to process.\r\n * @return none.\r\n */\r\n\r\n void arm_iir_lattice_q15(\r\n\t\t\t const arm_iir_lattice_instance_q15 * S,\r\n\t\t\t q15_t * pSrc,\r\n\t\t\t q15_t * pDst,\r\n\t\t\t uint32_t blockSize);\r\n\r\n\r\n/**\r\n * @brief Initialization function for the Q15 IIR lattice filter.\r\n * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.\r\n * @param[in] numStages number of stages in the filter.\r\n * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages.\r\n * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.\r\n * @param[in] *pState points to state buffer. The array is of length numStages+blockSize.\r\n * @param[in] blockSize number of samples to process per call.\r\n * @return none.\r\n */\r\n\r\n void arm_iir_lattice_init_q15(\r\n\t\t\t\tarm_iir_lattice_instance_q15 * S,\r\n\t\t\t\tuint16_t numStages,\r\n\t\t\t\tq15_t *pkCoeffs,\r\n\t\t\t\tq15_t *pvCoeffs,\r\n\t\t\t\tq15_t *pState,\r\n\t\t\t\tuint32_t blockSize);\r\n\r\n /**\r\n * @brief Instance structure for the floating-point LMS filter.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint16_t numTaps; /**< number of coefficients in the filter. */\r\n float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r\n float32_t mu; /**< step size that controls filter coefficient updates. */\r\n } arm_lms_instance_f32;\r\n\r\n /**\r\n * @brief Processing function for floating-point LMS filter.\r\n * @param[in] *S points to an instance of the floating-point LMS filter structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[in] *pRef points to the block of reference data.\r\n * @param[out] *pOut points to the block of output data.\r\n * @param[out] *pErr points to the block of error data.\r\n * @param[in] blockSize number of samples to process.\r\n * @return none.\r\n */\r\n\r\n void arm_lms_f32(\r\n\t\t const arm_lms_instance_f32 * S,\r\n\t\t float32_t * pSrc,\r\n\t\t float32_t * pRef,\r\n\t\t float32_t * pOut,\r\n\t\t float32_t * pErr,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Initialization function for floating-point LMS filter.\r\n * @param[in] *S points to an instance of the floating-point LMS filter structure.\r\n * @param[in] numTaps number of filter coefficients.\r\n * @param[in] *pCoeffs points to the coefficient buffer.\r\n * @param[in] *pState points to state buffer.\r\n * @param[in] mu step size that controls filter coefficient updates.\r\n * @param[in] blockSize number of samples to process.\r\n * @return none.\r\n */\r\n\r\n void arm_lms_init_f32(\r\n\t\t\tarm_lms_instance_f32 * S,\r\n\t\t\tuint16_t numTaps,\r\n\t\t\tfloat32_t * pCoeffs,\r\n\t\t\tfloat32_t * pState,\r\n\t\t\tfloat32_t mu,\r\n\t\t\tuint32_t blockSize);\r\n\r\n /**\r\n * @brief Instance structure for the Q15 LMS filter.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint16_t numTaps; /**< number of coefficients in the filter. */\r\n q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r\n q15_t mu; /**< step size that controls filter coefficient updates. */\r\n uint32_t postShift; /**< bit shift applied to coefficients. */\r\n } arm_lms_instance_q15;\r\n\r\n\r\n /**\r\n * @brief Initialization function for the Q15 LMS filter.\r\n * @param[in] *S points to an instance of the Q15 LMS filter structure.\r\n * @param[in] numTaps number of filter coefficients.\r\n * @param[in] *pCoeffs points to the coefficient buffer.\r\n * @param[in] *pState points to the state buffer.\r\n * @param[in] mu step size that controls filter coefficient updates.\r\n * @param[in] blockSize number of samples to process.\r\n * @param[in] postShift bit shift applied to coefficients.\r\n * @return none.\r\n */\r\n\r\n void arm_lms_init_q15(\r\n\t\t\tarm_lms_instance_q15 * S,\r\n\t\t\tuint16_t numTaps,\r\n\t\t\tq15_t * pCoeffs,\r\n\t\t\tq15_t * pState,\r\n\t\t\tq15_t mu,\r\n\t\t\tuint32_t blockSize,\r\n\t\t\tuint32_t postShift);\r\n\r\n /**\r\n * @brief Processing function for Q15 LMS filter.\r\n * @param[in] *S points to an instance of the Q15 LMS filter structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[in] *pRef points to the block of reference data.\r\n * @param[out] *pOut points to the block of output data.\r\n * @param[out] *pErr points to the block of error data.\r\n * @param[in] blockSize number of samples to process.\r\n * @return none.\r\n */\r\n\r\n void arm_lms_q15(\r\n\t\t const arm_lms_instance_q15 * S,\r\n\t\t q15_t * pSrc,\r\n\t\t q15_t * pRef,\r\n\t\t q15_t * pOut,\r\n\t\t q15_t * pErr,\r\n\t\t uint32_t blockSize);\r\n\r\n\r\n /**\r\n * @brief Instance structure for the Q31 LMS filter.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint16_t numTaps; /**< number of coefficients in the filter. */\r\n q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r\n q31_t mu; /**< step size that controls filter coefficient updates. */\r\n uint32_t postShift; /**< bit shift applied to coefficients. */\r\n\r\n } arm_lms_instance_q31;\r\n\r\n /**\r\n * @brief Processing function for Q31 LMS filter.\r\n * @param[in] *S points to an instance of the Q15 LMS filter structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[in] *pRef points to the block of reference data.\r\n * @param[out] *pOut points to the block of output data.\r\n * @param[out] *pErr points to the block of error data.\r\n * @param[in] blockSize number of samples to process.\r\n * @return none.\r\n */\r\n\r\n void arm_lms_q31(\r\n\t\t const arm_lms_instance_q31 * S,\r\n\t\t q31_t * pSrc,\r\n\t\t q31_t * pRef,\r\n\t\t q31_t * pOut,\r\n\t\t q31_t * pErr,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Initialization function for Q31 LMS filter.\r\n * @param[in] *S points to an instance of the Q31 LMS filter structure.\r\n * @param[in] numTaps number of filter coefficients.\r\n * @param[in] *pCoeffs points to coefficient buffer.\r\n * @param[in] *pState points to state buffer.\r\n * @param[in] mu step size that controls filter coefficient updates.\r\n * @param[in] blockSize number of samples to process.\r\n * @param[in] postShift bit shift applied to coefficients.\r\n * @return none.\r\n */\r\n\r\n void arm_lms_init_q31(\r\n\t\t\tarm_lms_instance_q31 * S,\r\n\t\t\tuint16_t numTaps,\r\n\t\t\tq31_t *pCoeffs,\r\n\t\t\tq31_t *pState,\r\n\t\t\tq31_t mu,\r\n\t\t\tuint32_t blockSize,\r\n\t\t\tuint32_t postShift);\r\n\r\n /**\r\n * @brief Instance structure for the floating-point normalized LMS filter.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint16_t numTaps; /**< number of coefficients in the filter. */\r\n float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r\n float32_t mu; /**< step size that control filter coefficient updates. */\r\n float32_t energy; /**< saves previous frame energy. */\r\n float32_t x0; /**< saves previous input sample. */\r\n } arm_lms_norm_instance_f32;\r\n\r\n /**\r\n * @brief Processing function for floating-point normalized LMS filter.\r\n * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[in] *pRef points to the block of reference data.\r\n * @param[out] *pOut points to the block of output data.\r\n * @param[out] *pErr points to the block of error data.\r\n * @param[in] blockSize number of samples to process.\r\n * @return none.\r\n */\r\n\r\n void arm_lms_norm_f32(\r\n\t\t\tarm_lms_norm_instance_f32 * S,\r\n\t\t\t float32_t * pSrc,\r\n\t\t\t float32_t * pRef,\r\n\t\t\tfloat32_t * pOut,\r\n\t\t\tfloat32_t * pErr,\r\n\t\t\tuint32_t blockSize);\r\n\r\n /**\r\n * @brief Initialization function for floating-point normalized LMS filter.\r\n * @param[in] *S points to an instance of the floating-point LMS filter structure.\r\n * @param[in] numTaps number of filter coefficients.\r\n * @param[in] *pCoeffs points to coefficient buffer.\r\n * @param[in] *pState points to state buffer.\r\n * @param[in] mu step size that controls filter coefficient updates.\r\n * @param[in] blockSize number of samples to process.\r\n * @return none.\r\n */\r\n\r\n void arm_lms_norm_init_f32(\r\n\t\t\t arm_lms_norm_instance_f32 * S,\r\n\t\t\t uint16_t numTaps,\r\n\t\t\t float32_t * pCoeffs,\r\n\t\t\t float32_t * pState,\r\n\t\t\t float32_t mu,\r\n\t\t\t uint32_t blockSize);\r\n\r\n\r\n /**\r\n * @brief Instance structure for the Q31 normalized LMS filter.\r\n */\r\n typedef struct\r\n {\r\n uint16_t numTaps; /**< number of coefficients in the filter. */\r\n q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r\n q31_t mu; /**< step size that controls filter coefficient updates. */\r\n uint8_t postShift; /**< bit shift applied to coefficients. */\r\n q31_t *recipTable; /**< points to the reciprocal initial value table. */\r\n q31_t energy; /**< saves previous frame energy. */\r\n q31_t x0; /**< saves previous input sample. */\r\n } arm_lms_norm_instance_q31;\r\n\r\n /**\r\n * @brief Processing function for Q31 normalized LMS filter.\r\n * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[in] *pRef points to the block of reference data.\r\n * @param[out] *pOut points to the block of output data.\r\n * @param[out] *pErr points to the block of error data.\r\n * @param[in] blockSize number of samples to process.\r\n * @return none.\r\n */\r\n\r\n void arm_lms_norm_q31(\r\n\t\t\tarm_lms_norm_instance_q31 * S,\r\n\t\t\t q31_t * pSrc,\r\n\t\t\t q31_t * pRef,\r\n\t\t\tq31_t * pOut,\r\n\t\t\tq31_t * pErr,\r\n\t\t\tuint32_t blockSize);\r\n\r\n /**\r\n * @brief Initialization function for Q31 normalized LMS filter.\r\n * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.\r\n * @param[in] numTaps number of filter coefficients.\r\n * @param[in] *pCoeffs points to coefficient buffer.\r\n * @param[in] *pState points to state buffer.\r\n * @param[in] mu step size that controls filter coefficient updates.\r\n * @param[in] blockSize number of samples to process.\r\n * @param[in] postShift bit shift applied to coefficients.\r\n * @return none.\r\n */\r\n\r\n void arm_lms_norm_init_q31(\r\n\t\t\t arm_lms_norm_instance_q31 * S,\r\n\t\t\t uint16_t numTaps,\r\n\t\t\t q31_t * pCoeffs,\r\n\t\t\t q31_t * pState,\r\n\t\t\t q31_t mu,\r\n\t\t\t uint32_t blockSize,\r\n\t\t\t uint8_t postShift);\r\n\r\n /**\r\n * @brief Instance structure for the Q15 normalized LMS filter.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint16_t numTaps; /**< Number of coefficients in the filter. */\r\n q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r\n q15_t mu; /**< step size that controls filter coefficient updates. */\r\n uint8_t postShift; /**< bit shift applied to coefficients. */\r\n q15_t *recipTable; /**< Points to the reciprocal initial value table. */\r\n q15_t energy; /**< saves previous frame energy. */\r\n q15_t x0; /**< saves previous input sample. */\r\n } arm_lms_norm_instance_q15;\r\n\r\n /**\r\n * @brief Processing function for Q15 normalized LMS filter.\r\n * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[in] *pRef points to the block of reference data.\r\n * @param[out] *pOut points to the block of output data.\r\n * @param[out] *pErr points to the block of error data.\r\n * @param[in] blockSize number of samples to process.\r\n * @return none.\r\n */\r\n\r\n void arm_lms_norm_q15(\r\n\t\t\tarm_lms_norm_instance_q15 * S,\r\n\t\t\t q15_t * pSrc,\r\n\t\t\t q15_t * pRef,\r\n\t\t\tq15_t * pOut,\r\n\t\t\tq15_t * pErr,\r\n\t\t\tuint32_t blockSize);\r\n\r\n\r\n /**\r\n * @brief Initialization function for Q15 normalized LMS filter.\r\n * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.\r\n * @param[in] numTaps number of filter coefficients.\r\n * @param[in] *pCoeffs points to coefficient buffer.\r\n * @param[in] *pState points to state buffer.\r\n * @param[in] mu step size that controls filter coefficient updates.\r\n * @param[in] blockSize number of samples to process.\r\n * @param[in] postShift bit shift applied to coefficients.\r\n * @return none.\r\n */\r\n\r\n void arm_lms_norm_init_q15(\r\n\t\t\t arm_lms_norm_instance_q15 * S,\r\n\t\t\t uint16_t numTaps,\r\n\t\t\t q15_t * pCoeffs,\r\n\t\t\t q15_t * pState,\r\n\t\t\t q15_t mu,\r\n\t\t\t uint32_t blockSize,\r\n\t\t\t uint8_t postShift);\r\n\r\n /**\r\n * @brief Correlation of floating-point sequences.\r\n * @param[in] *pSrcA points to the first input sequence.\r\n * @param[in] srcALen length of the first input sequence.\r\n * @param[in] *pSrcB points to the second input sequence.\r\n * @param[in] srcBLen length of the second input sequence.\r\n * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r\n * @return none.\r\n */\r\n\r\n void arm_correlate_f32(\r\n\t\t\t float32_t * pSrcA,\r\n\t\t\t uint32_t srcALen,\r\n\t\t\t float32_t * pSrcB,\r\n\t\t\t uint32_t srcBLen,\r\n\t\t\t float32_t * pDst);\r\n\r\n /**\r\n * @brief Correlation of Q15 sequences.\r\n * @param[in] *pSrcA points to the first input sequence.\r\n * @param[in] srcALen length of the first input sequence.\r\n * @param[in] *pSrcB points to the second input sequence.\r\n * @param[in] srcBLen length of the second input sequence.\r\n * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r\n * @return none.\r\n */\r\n\r\n void arm_correlate_q15(\r\n\t\t\t q15_t * pSrcA,\r\n\t\t\t uint32_t srcALen,\r\n\t\t\t q15_t * pSrcB,\r\n\t\t\t uint32_t srcBLen,\r\n\t\t\t q15_t * pDst);\r\n\r\n /**\r\n * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.\r\n * @param[in] *pSrcA points to the first input sequence.\r\n * @param[in] srcALen length of the first input sequence.\r\n * @param[in] *pSrcB points to the second input sequence.\r\n * @param[in] srcBLen length of the second input sequence.\r\n * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r\n * @return none.\r\n */\r\n\r\n void arm_correlate_fast_q15(\r\n\t\t\t q15_t * pSrcA,\r\n\t\t\t uint32_t srcALen,\r\n\t\t\t q15_t * pSrcB,\r\n\t\t\t uint32_t srcBLen,\r\n\t\t\t q15_t * pDst);\r\n\r\n /**\r\n * @brief Correlation of Q31 sequences.\r\n * @param[in] *pSrcA points to the first input sequence.\r\n * @param[in] srcALen length of the first input sequence.\r\n * @param[in] *pSrcB points to the second input sequence.\r\n * @param[in] srcBLen length of the second input sequence.\r\n * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r\n * @return none.\r\n */\r\n\r\n void arm_correlate_q31(\r\n\t\t\t q31_t * pSrcA,\r\n\t\t\t uint32_t srcALen,\r\n\t\t\t q31_t * pSrcB,\r\n\t\t\t uint32_t srcBLen,\r\n\t\t\t q31_t * pDst);\r\n\r\n /**\r\n * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r\n * @param[in] *pSrcA points to the first input sequence.\r\n * @param[in] srcALen length of the first input sequence.\r\n * @param[in] *pSrcB points to the second input sequence.\r\n * @param[in] srcBLen length of the second input sequence.\r\n * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r\n * @return none.\r\n */\r\n\r\n void arm_correlate_fast_q31(\r\n\t\t\t q31_t * pSrcA,\r\n\t\t\t uint32_t srcALen,\r\n\t\t\t q31_t * pSrcB,\r\n\t\t\t uint32_t srcBLen,\r\n\t\t\t q31_t * pDst);\r\n\r\n /**\r\n * @brief Correlation of Q7 sequences.\r\n * @param[in] *pSrcA points to the first input sequence.\r\n * @param[in] srcALen length of the first input sequence.\r\n * @param[in] *pSrcB points to the second input sequence.\r\n * @param[in] srcBLen length of the second input sequence.\r\n * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r\n * @return none.\r\n */\r\n\r\n void arm_correlate_q7(\r\n\t\t\t q7_t * pSrcA,\r\n\t\t\tuint32_t srcALen,\r\n\t\t\t q7_t * pSrcB,\r\n\t\t\tuint32_t srcBLen,\r\n\t\t\tq7_t * pDst);\r\n\r\n /**\r\n * @brief Instance structure for the floating-point sparse FIR filter.\r\n */\r\n typedef struct\r\n {\r\n uint16_t numTaps; /**< number of coefficients in the filter. */\r\n uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r\n float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r\n float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r\n uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r\n int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r\n } arm_fir_sparse_instance_f32;\r\n\r\n /**\r\n * @brief Instance structure for the Q31 sparse FIR filter.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint16_t numTaps; /**< number of coefficients in the filter. */\r\n uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r\n q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r\n q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r\n uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r\n int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r\n } arm_fir_sparse_instance_q31;\r\n\r\n /**\r\n * @brief Instance structure for the Q15 sparse FIR filter.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint16_t numTaps; /**< number of coefficients in the filter. */\r\n uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r\n q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r\n q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r\n uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r\n int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r\n } arm_fir_sparse_instance_q15;\r\n\r\n /**\r\n * @brief Instance structure for the Q7 sparse FIR filter.\r\n */\r\n\r\n typedef struct\r\n {\r\n uint16_t numTaps; /**< number of coefficients in the filter. */\r\n uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r\n q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r\n q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r\n uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r\n int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r\n } arm_fir_sparse_instance_q7;\r\n\r\n /**\r\n * @brief Processing function for the floating-point sparse FIR filter.\r\n * @param[in] *S points to an instance of the floating-point sparse FIR structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[out] *pDst points to the block of output data\r\n * @param[in] *pScratchIn points to a temporary buffer of size blockSize.\r\n * @param[in] blockSize number of input samples to process per call.\r\n * @return none.\r\n */\r\n\r\n void arm_fir_sparse_f32(\r\n\t\t\t arm_fir_sparse_instance_f32 * S,\r\n\t\t\t float32_t * pSrc,\r\n\t\t\t float32_t * pDst,\r\n\t\t\t float32_t * pScratchIn,\r\n\t\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Initialization function for the floating-point sparse FIR filter.\r\n * @param[in,out] *S points to an instance of the floating-point sparse FIR structure.\r\n * @param[in] numTaps number of nonzero coefficients in the filter.\r\n * @param[in] *pCoeffs points to the array of filter coefficients.\r\n * @param[in] *pState points to the state buffer.\r\n * @param[in] *pTapDelay points to the array of offset times.\r\n * @param[in] maxDelay maximum offset time supported.\r\n * @param[in] blockSize number of samples that will be processed per block.\r\n * @return none\r\n */\r\n\r\n void arm_fir_sparse_init_f32(\r\n\t\t\t arm_fir_sparse_instance_f32 * S,\r\n\t\t\t uint16_t numTaps,\r\n\t\t\t float32_t * pCoeffs,\r\n\t\t\t float32_t * pState,\r\n\t\t\t int32_t * pTapDelay,\r\n\t\t\t uint16_t maxDelay,\r\n\t\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Processing function for the Q31 sparse FIR filter.\r\n * @param[in] *S points to an instance of the Q31 sparse FIR structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[out] *pDst points to the block of output data\r\n * @param[in] *pScratchIn points to a temporary buffer of size blockSize.\r\n * @param[in] blockSize number of input samples to process per call.\r\n * @return none.\r\n */\r\n\r\n void arm_fir_sparse_q31(\r\n\t\t\t arm_fir_sparse_instance_q31 * S,\r\n\t\t\t q31_t * pSrc,\r\n\t\t\t q31_t * pDst,\r\n\t\t\t q31_t * pScratchIn,\r\n\t\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Initialization function for the Q31 sparse FIR filter.\r\n * @param[in,out] *S points to an instance of the Q31 sparse FIR structure.\r\n * @param[in] numTaps number of nonzero coefficients in the filter.\r\n * @param[in] *pCoeffs points to the array of filter coefficients.\r\n * @param[in] *pState points to the state buffer.\r\n * @param[in] *pTapDelay points to the array of offset times.\r\n * @param[in] maxDelay maximum offset time supported.\r\n * @param[in] blockSize number of samples that will be processed per block.\r\n * @return none\r\n */\r\n\r\n void arm_fir_sparse_init_q31(\r\n\t\t\t arm_fir_sparse_instance_q31 * S,\r\n\t\t\t uint16_t numTaps,\r\n\t\t\t q31_t * pCoeffs,\r\n\t\t\t q31_t * pState,\r\n\t\t\t int32_t * pTapDelay,\r\n\t\t\t uint16_t maxDelay,\r\n\t\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Processing function for the Q15 sparse FIR filter.\r\n * @param[in] *S points to an instance of the Q15 sparse FIR structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[out] *pDst points to the block of output data\r\n * @param[in] *pScratchIn points to a temporary buffer of size blockSize.\r\n * @param[in] *pScratchOut points to a temporary buffer of size blockSize.\r\n * @param[in] blockSize number of input samples to process per call.\r\n * @return none.\r\n */\r\n\r\n void arm_fir_sparse_q15(\r\n\t\t\t arm_fir_sparse_instance_q15 * S,\r\n\t\t\t q15_t * pSrc,\r\n\t\t\t q15_t * pDst,\r\n\t\t\t q15_t * pScratchIn,\r\n\t\t\t q31_t * pScratchOut,\r\n\t\t\t uint32_t blockSize);\r\n\r\n\r\n /**\r\n * @brief Initialization function for the Q15 sparse FIR filter.\r\n * @param[in,out] *S points to an instance of the Q15 sparse FIR structure.\r\n * @param[in] numTaps number of nonzero coefficients in the filter.\r\n * @param[in] *pCoeffs points to the array of filter coefficients.\r\n * @param[in] *pState points to the state buffer.\r\n * @param[in] *pTapDelay points to the array of offset times.\r\n * @param[in] maxDelay maximum offset time supported.\r\n * @param[in] blockSize number of samples that will be processed per block.\r\n * @return none\r\n */\r\n\r\n void arm_fir_sparse_init_q15(\r\n\t\t\t arm_fir_sparse_instance_q15 * S,\r\n\t\t\t uint16_t numTaps,\r\n\t\t\t q15_t * pCoeffs,\r\n\t\t\t q15_t * pState,\r\n\t\t\t int32_t * pTapDelay,\r\n\t\t\t uint16_t maxDelay,\r\n\t\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Processing function for the Q7 sparse FIR filter.\r\n * @param[in] *S points to an instance of the Q7 sparse FIR structure.\r\n * @param[in] *pSrc points to the block of input data.\r\n * @param[out] *pDst points to the block of output data\r\n * @param[in] *pScratchIn points to a temporary buffer of size blockSize.\r\n * @param[in] *pScratchOut points to a temporary buffer of size blockSize.\r\n * @param[in] blockSize number of input samples to process per call.\r\n * @return none.\r\n */\r\n\r\n void arm_fir_sparse_q7(\r\n\t\t\t arm_fir_sparse_instance_q7 * S,\r\n\t\t\t q7_t * pSrc,\r\n\t\t\t q7_t * pDst,\r\n\t\t\t q7_t * pScratchIn,\r\n\t\t\t q31_t * pScratchOut,\r\n\t\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Initialization function for the Q7 sparse FIR filter.\r\n * @param[in,out] *S points to an instance of the Q7 sparse FIR structure.\r\n * @param[in] numTaps number of nonzero coefficients in the filter.\r\n * @param[in] *pCoeffs points to the array of filter coefficients.\r\n * @param[in] *pState points to the state buffer.\r\n * @param[in] *pTapDelay points to the array of offset times.\r\n * @param[in] maxDelay maximum offset time supported.\r\n * @param[in] blockSize number of samples that will be processed per block.\r\n * @return none\r\n */\r\n\r\n void arm_fir_sparse_init_q7(\r\n\t\t\t arm_fir_sparse_instance_q7 * S,\r\n\t\t\t uint16_t numTaps,\r\n\t\t\t q7_t * pCoeffs,\r\n\t\t\t q7_t * pState,\r\n\t\t\t int32_t *pTapDelay,\r\n\t\t\t uint16_t maxDelay,\r\n\t\t\t uint32_t blockSize);\r\n\r\n\r\n /*\r\n * @brief Floating-point sin_cos function.\r\n * @param[in] theta input value in degrees \r\n * @param[out] *pSinVal points to the processed sine output. \r\n * @param[out] *pCosVal points to the processed cos output. \r\n * @return none.\r\n */\r\n\r\n void arm_sin_cos_f32(\r\n\t\t float32_t theta,\r\n\t\t float32_t *pSinVal,\r\n\t\t float32_t *pCcosVal);\r\n\r\n /*\r\n * @brief Q31 sin_cos function.\r\n * @param[in] theta scaled input value in degrees \r\n * @param[out] *pSinVal points to the processed sine output. \r\n * @param[out] *pCosVal points to the processed cosine output. \r\n * @return none.\r\n */\r\n\r\n void arm_sin_cos_q31(\r\n\t\t q31_t theta,\r\n\t\t q31_t *pSinVal,\r\n\t\t q31_t *pCosVal);\r\n\r\n\r\n /**\r\n * @brief Floating-point complex conjugate.\r\n * @param[in] *pSrc points to the input vector\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] numSamples number of complex samples in each vector\r\n * @return none.\r\n */\r\n\r\n void arm_cmplx_conj_f32(\r\n\t\t\t float32_t * pSrc,\r\n\t\t\t float32_t * pDst,\r\n\t\t\t uint32_t numSamples);\r\n\r\n /**\r\n * @brief Q31 complex conjugate.\r\n * @param[in] *pSrc points to the input vector\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] numSamples number of complex samples in each vector\r\n * @return none.\r\n */\r\n\r\n void arm_cmplx_conj_q31(\r\n\t\t\t q31_t * pSrc,\r\n\t\t\t q31_t * pDst,\r\n\t\t\t uint32_t numSamples);\r\n\r\n /**\r\n * @brief Q15 complex conjugate.\r\n * @param[in] *pSrc points to the input vector\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] numSamples number of complex samples in each vector\r\n * @return none.\r\n */\r\n\r\n void arm_cmplx_conj_q15(\r\n\t\t\t q15_t * pSrc,\r\n\t\t\t q15_t * pDst,\r\n\t\t\t uint32_t numSamples);\r\n\r\n\r\n\r\n /**\r\n * @brief Floating-point complex magnitude squared\r\n * @param[in] *pSrc points to the complex input vector\r\n * @param[out] *pDst points to the real output vector\r\n * @param[in] numSamples number of complex samples in the input vector\r\n * @return none.\r\n */\r\n\r\n void arm_cmplx_mag_squared_f32(\r\n\t\t\t\t float32_t * pSrc,\r\n\t\t\t\t float32_t * pDst,\r\n\t\t\t\t uint32_t numSamples);\r\n\r\n /**\r\n * @brief Q31 complex magnitude squared\r\n * @param[in] *pSrc points to the complex input vector\r\n * @param[out] *pDst points to the real output vector\r\n * @param[in] numSamples number of complex samples in the input vector\r\n * @return none.\r\n */\r\n\r\n void arm_cmplx_mag_squared_q31(\r\n\t\t\t\t q31_t * pSrc,\r\n\t\t\t\t q31_t * pDst,\r\n\t\t\t\t uint32_t numSamples);\r\n\r\n /**\r\n * @brief Q15 complex magnitude squared\r\n * @param[in] *pSrc points to the complex input vector\r\n * @param[out] *pDst points to the real output vector\r\n * @param[in] numSamples number of complex samples in the input vector\r\n * @return none.\r\n */\r\n\r\n void arm_cmplx_mag_squared_q15(\r\n\t\t\t\t q15_t * pSrc,\r\n\t\t\t\t q15_t * pDst,\r\n\t\t\t\t uint32_t numSamples);\r\n\r\n\r\n /**\r\n * @ingroup groupController\r\n */\r\n\r\n /**\r\n * @defgroup PID PID Motor Control\r\n *\r\n * A Proportional Integral Derivative (PID) controller is a generic feedback control \r\n * loop mechanism widely used in industrial control systems.\r\n * A PID controller is the most commonly used type of feedback controller.\r\n *\r\n * This set of functions implements (PID) controllers\r\n * for Q15, Q31, and floating-point data types. The functions operate on a single sample\r\n * of data and each call to the function returns a single processed value.\r\n * S points to an instance of the PID control data structure. in\r\n * is the input sample value. The functions return the output value.\r\n *\r\n * \\par Algorithm:\r\n * 
\r\n   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]\r\n   *    A0 = Kp + Ki + Kd\r\n   *    A1 = (-Kp ) - (2 * Kd )\r\n   *    A2 = Kd
\r\n *\r\n * \\par\r\n * where \\c Kp is proportional constant, \\c Ki is Integral constant and \\c Kd is Derivative constant\r\n * \r\n * \\par \r\n * \\image html PID.gif \"Proportional Integral Derivative Controller\" \r\n *\r\n * \\par\r\n * The PID controller calculates an \"error\" value as the difference between\r\n * the measured output and the reference input.\r\n * The controller attempts to minimize the error by adjusting the process control inputs. \r\n * The proportional value determines the reaction to the current error, \r\n * the integral value determines the reaction based on the sum of recent errors, \r\n * and the derivative value determines the reaction based on the rate at which the error has been changing.\r\n *\r\n * \\par Instance Structure \r\n * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. \r\n * A separate instance structure must be defined for each PID Controller. \r\n * There are separate instance structure declarations for each of the 3 supported data types. \r\n * \r\n * \\par Reset Functions \r\n * There is also an associated reset function for each data type which clears the state array. \r\n *\r\n * \\par Initialization Functions \r\n * There is also an associated initialization function for each data type. \r\n * The initialization function performs the following operations: \r\n * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.\r\n * - Zeros out the values in the state buffer. \r\n * \r\n * \\par \r\n * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. \r\n *\r\n * \\par Fixed-Point Behavior \r\n * Care must be taken when using the fixed-point versions of the PID Controller functions. \r\n * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. \r\n * Refer to the function specific documentation below for usage guidelines. \r\n */\r\n\r\n /**\r\n * @addtogroup PID\r\n * @{\r\n */\r\n\r\n /**\r\n * @brief Process function for the floating-point PID Control.\r\n * @param[in,out] *S is an instance of the floating-point PID Control structure\r\n * @param[in] in input sample to process\r\n * @return out processed output sample.\r\n */\r\n\r\n\r\n static __INLINE float32_t arm_pid_f32(\r\n\t\t\t\t\tarm_pid_instance_f32 * S,\r\n\t\t\t\t\tfloat32_t in)\r\n {\r\n float32_t out;\r\n\r\n /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */\r\n out = (S->A0 * in) +\r\n (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);\r\n\r\n /* Update state */\r\n S->state[1] = S->state[0];\r\n S->state[0] = in;\r\n S->state[2] = out;\r\n\r\n /* return to application */\r\n return (out);\r\n\r\n }\r\n\r\n /**\r\n * @brief Process function for the Q31 PID Control.\r\n * @param[in,out] *S points to an instance of the Q31 PID Control structure\r\n * @param[in] in input sample to process\r\n * @return out processed output sample.\r\n *\r\n * Scaling and Overflow Behavior: \r\n * \\par \r\n * The function is implemented using an internal 64-bit accumulator. \r\n * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. \r\n * Thus, if the accumulator result overflows it wraps around rather than clip. \r\n * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. \r\n * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. \r\n */\r\n\r\n static __INLINE q31_t arm_pid_q31(\r\n\t\t\t\t arm_pid_instance_q31 * S,\r\n\t\t\t\t q31_t in)\r\n {\r\n q63_t acc;\r\n\tq31_t out;\r\n\r\n /* acc = A0 * x[n] */\r\n acc = (q63_t) S->A0 * in;\r\n\r\n /* acc += A1 * x[n-1] */\r\n acc += (q63_t) S->A1 * S->state[0];\r\n\r\n /* acc += A2 * x[n-2] */\r\n acc += (q63_t) S->A2 * S->state[1];\r\n\r\n /* convert output to 1.31 format to add y[n-1] */\r\n out = (q31_t) (acc >> 31u);\r\n\r\n /* out += y[n-1] */\r\n out += S->state[2];\r\n\r\n /* Update state */\r\n S->state[1] = S->state[0];\r\n S->state[0] = in;\r\n S->state[2] = out;\r\n\r\n /* return to application */\r\n return (out);\r\n\r\n }\r\n\r\n /**\r\n * @brief Process function for the Q15 PID Control.\r\n * @param[in,out] *S points to an instance of the Q15 PID Control structure\r\n * @param[in] in input sample to process\r\n * @return out processed output sample.\r\n *\r\n * Scaling and Overflow Behavior: \r\n * \\par \r\n * The function is implemented using a 64-bit internal accumulator. \r\n * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. \r\n * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. \r\n * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. \r\n * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. \r\n * Lastly, the accumulator is saturated to yield a result in 1.15 format.\r\n */\r\n\r\n static __INLINE q15_t arm_pid_q15(\r\n\t\t\t\t arm_pid_instance_q15 * S,\r\n\t\t\t\t q15_t in)\r\n {\r\n q63_t acc;\r\n q15_t out;\r\n\r\n /* Implementation of PID controller */\r\n\r\n\t#ifdef ARM_MATH_CM0\r\n\r\n \t/* acc = A0 * x[n] */\r\n\tacc = ((q31_t) S->A0 )* in ;\r\n\r\n #else\r\n\t\t\t\t\r\n /* acc = A0 * x[n] */\r\n acc = (q31_t) __SMUAD(S->A0, in);\r\n\t\r\n\t#endif\r\n\r\n\t#ifdef ARM_MATH_CM0\r\n\t\t\t\t\t\t \r\n\t/* acc += A1 * x[n-1] + A2 * x[n-2] */\r\n\tacc += (q31_t) S->A1 * S->state[0] ;\r\n\tacc += (q31_t) S->A2 * S->state[1] ;\r\n\r\n\t#else\r\n\r\n /* acc += A1 * x[n-1] + A2 * x[n-2] */\r\n acc = __SMLALD(S->A1, (q31_t)__SIMD32(S->state), acc);\r\n\r\n\t#endif\r\n\r\n /* acc += y[n-1] */\r\n acc += (q31_t) S->state[2] << 15;\r\n\r\n /* saturate the output */\r\n out = (q15_t) (__SSAT((acc >> 15), 16));\r\n\r\n /* Update state */\r\n S->state[1] = S->state[0];\r\n S->state[0] = in;\r\n S->state[2] = out;\r\n\r\n /* return to application */\r\n return (out);\r\n\r\n }\r\n \r\n /**\r\n * @} end of PID group\r\n */\r\n\r\n\r\n /**\r\n * @brief Floating-point matrix inverse.\r\n * @param[in] *src points to the instance of the input floating-point matrix structure.\r\n * @param[out] *dst points to the instance of the output floating-point matrix structure.\r\n * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.\r\n * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.\r\n */\r\n\r\n arm_status arm_mat_inverse_f32(\r\n\t\t\t\t const arm_matrix_instance_f32 * src,\r\n\t\t\t\t arm_matrix_instance_f32 * dst);\r\n\r\n \r\n \r\n /**\r\n * @ingroup groupController\r\n */\r\n\r\n\r\n /**\r\n * @defgroup clarke Vector Clarke Transform\r\n * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.\r\n * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents\r\n * in the two-phase orthogonal stator axis Ialpha and Ibeta.\r\n * When Ialpha is superposed with Ia as shown in the figure below\r\n * \\image html clarke.gif Stator current space vector and its components in (a,b).\r\n * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta\r\n * can be calculated using only Ia and Ib.\r\n *\r\n * The function operates on a single sample of data and each call to the function returns the processed output. \r\n * The library provides separate functions for Q31 and floating-point data types.\r\n * \\par Algorithm\r\n * \\image html clarkeFormula.gif\r\n * where Ia and Ib are the instantaneous stator phases and\r\n * pIalpha and pIbeta are the two coordinates of time invariant vector.\r\n * \\par Fixed-Point Behavior\r\n * Care must be taken when using the Q31 version of the Clarke transform.\r\n * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r\n * Refer to the function specific documentation below for usage guidelines.\r\n */\r\n\r\n /**\r\n * @addtogroup clarke\r\n * @{\r\n */\r\n\r\n /**\r\n *\r\n * @brief Floating-point Clarke transform\r\n * @param[in] Ia input three-phase coordinate a\r\n * @param[in] Ib input three-phase coordinate b\r\n * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha\r\n * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta\r\n * @return none.\r\n */\r\n\r\n static __INLINE void arm_clarke_f32(\r\n\t\t\t\t float32_t Ia,\r\n\t\t\t\t float32_t Ib,\r\n\t\t\t\t float32_t * pIalpha,\r\n\t\t\t\t float32_t * pIbeta)\r\n {\r\n /* Calculate pIalpha using the equation, pIalpha = Ia */\r\n *pIalpha = Ia;\r\n\r\n /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */\r\n *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);\r\n\r\n }\r\n\r\n /**\r\n * @brief Clarke transform for Q31 version\r\n * @param[in] Ia input three-phase coordinate a\r\n * @param[in] Ib input three-phase coordinate b\r\n * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha\r\n * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta\r\n * @return none.\r\n *\r\n * Scaling and Overflow Behavior:\r\n * \\par\r\n * The function is implemented using an internal 32-bit accumulator.\r\n * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r\n * There is saturation on the addition, hence there is no risk of overflow.\r\n */\r\n\r\n static __INLINE void arm_clarke_q31(\r\n\t\t\t\t q31_t Ia,\r\n\t\t\t\t q31_t Ib,\r\n\t\t\t\t q31_t * pIalpha,\r\n\t\t\t\t q31_t * pIbeta)\r\n {\r\n q31_t product1, product2; /* Temporary variables used to store intermediate results */\r\n\r\n /* Calculating pIalpha from Ia by equation pIalpha = Ia */\r\n *pIalpha = Ia;\r\n\r\n /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */\r\n product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);\r\n\r\n /* Intermediate product is calculated by (2/sqrt(3) * Ib) */\r\n product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);\r\n\r\n /* pIbeta is calculated by adding the intermediate products */\r\n *pIbeta = __QADD(product1, product2);\r\n }\r\n\r\n /**\r\n * @} end of clarke group\r\n */\r\n\r\n /**\r\n * @brief Converts the elements of the Q7 vector to Q31 vector.\r\n * @param[in] *pSrc input pointer\r\n * @param[out] *pDst output pointer\r\n * @param[in] blockSize number of samples to process\r\n * @return none.\r\n */\r\n void arm_q7_to_q31(\r\n\t\t q7_t * pSrc,\r\n\t\t q31_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n\r\n \r\n\r\n /**\r\n * @ingroup groupController\r\n */\r\n\r\n /**\r\n * @defgroup inv_clarke Vector Inverse Clarke Transform\r\n * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.\r\n * \r\n * The function operates on a single sample of data and each call to the function returns the processed output. \r\n * The library provides separate functions for Q31 and floating-point data types.\r\n * \\par Algorithm\r\n * \\image html clarkeInvFormula.gif\r\n * where pIa and pIb are the instantaneous stator phases and\r\n * Ialpha and Ibeta are the two coordinates of time invariant vector.\r\n * \\par Fixed-Point Behavior\r\n * Care must be taken when using the Q31 version of the Clarke transform.\r\n * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r\n * Refer to the function specific documentation below for usage guidelines.\r\n */\r\n\r\n /**\r\n * @addtogroup inv_clarke\r\n * @{\r\n */\r\n\r\n /**\r\n * @brief Floating-point Inverse Clarke transform\r\n * @param[in] Ialpha input two-phase orthogonal vector axis alpha\r\n * @param[in] Ibeta input two-phase orthogonal vector axis beta\r\n * @param[out] *pIa points to output three-phase coordinate a\r\n * @param[out] *pIb points to output three-phase coordinate b\r\n * @return none.\r\n */\r\n\r\n\r\n static __INLINE void arm_inv_clarke_f32(\r\n\t\t\t\t\t float32_t Ialpha,\r\n\t\t\t\t\t float32_t Ibeta,\r\n\t\t\t\t\t float32_t * pIa,\r\n\t\t\t\t\t float32_t * pIb)\r\n {\r\n /* Calculating pIa from Ialpha by equation pIa = Ialpha */\r\n *pIa = Ialpha;\r\n\r\n /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */\r\n *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;\r\n\r\n }\r\n\r\n /**\r\n * @brief Inverse Clarke transform for Q31 version \r\n * @param[in] Ialpha input two-phase orthogonal vector axis alpha\r\n * @param[in] Ibeta input two-phase orthogonal vector axis beta\r\n * @param[out] *pIa points to output three-phase coordinate a\r\n * @param[out] *pIb points to output three-phase coordinate b\r\n * @return none.\r\n *\r\n * Scaling and Overflow Behavior:\r\n * \\par\r\n * The function is implemented using an internal 32-bit accumulator.\r\n * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r\n * There is saturation on the subtraction, hence there is no risk of overflow.\r\n */\r\n\r\n static __INLINE void arm_inv_clarke_q31(\r\n\t\t\t\t\t q31_t Ialpha,\r\n\t\t\t\t\t q31_t Ibeta,\r\n\t\t\t\t\t q31_t * pIa,\r\n\t\t\t\t\t q31_t * pIb)\r\n {\r\n q31_t product1, product2; /* Temporary variables used to store intermediate results */\r\n\r\n /* Calculating pIa from Ialpha by equation pIa = Ialpha */\r\n *pIa = Ialpha;\r\n\r\n /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */\r\n product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);\r\n\r\n /* Intermediate product is calculated by (1/sqrt(3) * pIb) */\r\n product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);\r\n\r\n /* pIb is calculated by subtracting the products */\r\n *pIb = __QSUB(product2, product1);\r\n\r\n }\r\n\r\n /**\r\n * @} end of inv_clarke group\r\n */\r\n\r\n /**\r\n * @brief Converts the elements of the Q7 vector to Q15 vector.\r\n * @param[in] *pSrc input pointer\r\n * @param[out] *pDst output pointer\r\n * @param[in] blockSize number of samples to process\r\n * @return none.\r\n */\r\n void arm_q7_to_q15(\r\n\t\t q7_t * pSrc,\r\n\t\t q15_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n \r\n\r\n /**\r\n * @ingroup groupController\r\n */\r\n\r\n /**\r\n * @defgroup park Vector Park Transform\r\n *\r\n * Forward Park transform converts the input two-coordinate vector to flux and torque components.\r\n * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents \r\n * from the stationary to the moving reference frame and control the spatial relationship between \r\n * the stator vector current and rotor flux vector.\r\n * If we consider the d axis aligned with the rotor flux, the diagram below shows the \r\n * current vector and the relationship from the two reference frames:\r\n * \\image html park.gif \"Stator current space vector and its component in (a,b) and in the d,q rotating reference frame\"\r\n *\r\n * The function operates on a single sample of data and each call to the function returns the processed output. \r\n * The library provides separate functions for Q31 and floating-point data types.\r\n * \\par Algorithm\r\n * \\image html parkFormula.gif\r\n * where Ialpha and Ibeta are the stator vector components, \r\n * pId and pIq are rotor vector components and cosVal and sinVal are the \r\n * cosine and sine values of theta (rotor flux position).\r\n * \\par Fixed-Point Behavior\r\n * Care must be taken when using the Q31 version of the Park transform.\r\n * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r\n * Refer to the function specific documentation below for usage guidelines.\r\n */\r\n\r\n /**\r\n * @addtogroup park\r\n * @{\r\n */\r\n\r\n /**\r\n * @brief Floating-point Park transform\r\n * @param[in] Ialpha input two-phase vector coordinate alpha\r\n * @param[in] Ibeta input two-phase vector coordinate beta\r\n * @param[out] *pId points to output\trotor reference frame d\r\n * @param[out] *pIq points to output\trotor reference frame q\r\n * @param[in] sinVal sine value of rotation angle theta\r\n * @param[in] cosVal cosine value of rotation angle theta\r\n * @return none.\r\n *\r\n * The function implements the forward Park transform.\r\n *\r\n */\r\n\r\n static __INLINE void arm_park_f32(\r\n\t\t\t\t float32_t Ialpha,\r\n\t\t\t\t float32_t Ibeta,\r\n\t\t\t\t float32_t * pId,\r\n\t\t\t\t float32_t * pIq,\r\n\t\t\t\t float32_t sinVal,\r\n\t\t\t\t float32_t cosVal)\r\n {\r\n /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */\r\n *pId = Ialpha * cosVal + Ibeta * sinVal;\r\n\r\n /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */\r\n *pIq = -Ialpha * sinVal + Ibeta * cosVal;\r\n\r\n }\r\n\r\n /**\r\n * @brief Park transform for Q31 version \r\n * @param[in] Ialpha input two-phase vector coordinate alpha\r\n * @param[in] Ibeta input two-phase vector coordinate beta\r\n * @param[out] *pId points to output rotor reference frame d\r\n * @param[out] *pIq points to output rotor reference frame q\r\n * @param[in] sinVal sine value of rotation angle theta\r\n * @param[in] cosVal cosine value of rotation angle theta\r\n * @return none.\r\n *\r\n * Scaling and Overflow Behavior:\r\n * \\par\r\n * The function is implemented using an internal 32-bit accumulator.\r\n * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r\n * There is saturation on the addition and subtraction, hence there is no risk of overflow.\r\n */\r\n\r\n\r\n static __INLINE void arm_park_q31(\r\n\t\t\t\t q31_t Ialpha,\r\n\t\t\t\t q31_t Ibeta,\r\n\t\t\t\t q31_t * pId,\r\n\t\t\t\t q31_t * pIq,\r\n\t\t\t\t q31_t sinVal,\r\n\t\t\t\t q31_t cosVal)\r\n {\r\n q31_t product1, product2; /* Temporary variables used to store intermediate results */\r\n q31_t product3, product4; /* Temporary variables used to store intermediate results */\r\n\r\n /* Intermediate product is calculated by (Ialpha * cosVal) */\r\n product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);\r\n\r\n /* Intermediate product is calculated by (Ibeta * sinVal) */\r\n product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);\r\n\r\n\r\n /* Intermediate product is calculated by (Ialpha * sinVal) */\r\n product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);\r\n\r\n /* Intermediate product is calculated by (Ibeta * cosVal) */\r\n product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);\r\n\r\n /* Calculate pId by adding the two intermediate products 1 and 2 */\r\n *pId = __QADD(product1, product2);\r\n\r\n /* Calculate pIq by subtracting the two intermediate products 3 from 4 */\r\n *pIq = __QSUB(product4, product3);\r\n }\r\n\r\n /**\r\n * @} end of park group\r\n */\r\n\r\n /**\r\n * @brief Converts the elements of the Q7 vector to floating-point vector.\r\n * @param[in] *pSrc is input pointer\r\n * @param[out] *pDst is output pointer\r\n * @param[in] blockSize is the number of samples to process\r\n * @return none.\r\n */\r\n void arm_q7_to_float(\r\n\t\t q7_t * pSrc,\r\n\t\t float32_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n \r\n /**\r\n * @ingroup groupController\r\n */\r\n\r\n /**\r\n * @defgroup inv_park Vector Inverse Park transform\r\n * Inverse Park transform converts the input flux and torque components to two-coordinate vector.\r\n *\r\n * The function operates on a single sample of data and each call to the function returns the processed output. \r\n * The library provides separate functions for Q31 and floating-point data types.\r\n * \\par Algorithm\r\n * \\image html parkInvFormula.gif\r\n * where pIalpha and pIbeta are the stator vector components, \r\n * Id and Iq are rotor vector components and cosVal and sinVal are the \r\n * cosine and sine values of theta (rotor flux position).\r\n * \\par Fixed-Point Behavior\r\n * Care must be taken when using the Q31 version of the Park transform.\r\n * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r\n * Refer to the function specific documentation below for usage guidelines.\r\n */\r\n\r\n /**\r\n * @addtogroup inv_park\r\n * @{\r\n */\r\n\r\n /**\r\n * @brief Floating-point Inverse Park transform\r\n * @param[in] Id input coordinate of rotor reference frame d\r\n * @param[in] Iq input coordinate of rotor reference frame q\r\n * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha\r\n * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta\r\n * @param[in] sinVal sine value of rotation angle theta\r\n * @param[in] cosVal cosine value of rotation angle theta\r\n * @return none.\r\n */\r\n\r\n static __INLINE void arm_inv_park_f32(\r\n\t\t\t\t\tfloat32_t Id,\r\n\t\t\t\t\tfloat32_t Iq,\r\n\t\t\t\t\tfloat32_t * pIalpha,\r\n\t\t\t\t\tfloat32_t * pIbeta,\r\n\t\t\t\t\tfloat32_t sinVal,\r\n\t\t\t\t\tfloat32_t cosVal)\r\n {\r\n /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */\r\n *pIalpha = Id * cosVal - Iq * sinVal;\r\n\r\n /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */\r\n *pIbeta = Id * sinVal + Iq * cosVal;\r\n\r\n }\r\n\r\n\r\n /**\r\n * @brief Inverse Park transform for\tQ31 version \r\n * @param[in] Id input coordinate of rotor reference frame d\r\n * @param[in] Iq input coordinate of rotor reference frame q\r\n * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha\r\n * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta\r\n * @param[in] sinVal sine value of rotation angle theta\r\n * @param[in] cosVal cosine value of rotation angle theta\r\n * @return none.\r\n *\r\n * Scaling and Overflow Behavior:\r\n * \\par\r\n * The function is implemented using an internal 32-bit accumulator.\r\n * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r\n * There is saturation on the addition, hence there is no risk of overflow.\r\n */\r\n\r\n\r\n static __INLINE void arm_inv_park_q31(\r\n\t\t\t\t\tq31_t Id,\r\n\t\t\t\t\tq31_t Iq,\r\n\t\t\t\t\tq31_t * pIalpha,\r\n\t\t\t\t\tq31_t * pIbeta,\r\n\t\t\t\t\tq31_t sinVal,\r\n\t\t\t\t\tq31_t cosVal)\r\n {\r\n q31_t product1, product2; /* Temporary variables used to store intermediate results */\r\n q31_t product3, product4; /* Temporary variables used to store intermediate results */\r\n\r\n /* Intermediate product is calculated by (Id * cosVal) */\r\n product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);\r\n\r\n /* Intermediate product is calculated by (Iq * sinVal) */\r\n product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);\r\n\r\n\r\n /* Intermediate product is calculated by (Id * sinVal) */\r\n product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);\r\n\r\n /* Intermediate product is calculated by (Iq * cosVal) */\r\n product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);\r\n\r\n /* Calculate pIalpha by using the two intermediate products 1 and 2 */\r\n *pIalpha = __QSUB(product1, product2);\r\n\r\n /* Calculate pIbeta by using the two intermediate products 3 and 4 */\r\n *pIbeta = __QADD(product4, product3);\r\n\r\n }\r\n\r\n /**\r\n * @} end of Inverse park group\r\n */\r\n\r\n \r\n /**\r\n * @brief Converts the elements of the Q31 vector to floating-point vector.\r\n * @param[in] *pSrc is input pointer\r\n * @param[out] *pDst is output pointer\r\n * @param[in] blockSize is the number of samples to process\r\n * @return none.\r\n */\r\n void arm_q31_to_float(\r\n\t\t\t q31_t * pSrc,\r\n\t\t\tfloat32_t * pDst,\r\n\t\t\tuint32_t blockSize);\r\n\r\n /**\r\n * @ingroup groupInterpolation\r\n */\r\n\r\n /**\r\n * @defgroup LinearInterpolate Linear Interpolation\r\n *\r\n * Linear interpolation is a method of curve fitting using linear polynomials.\r\n * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line\r\n *\r\n * \\par \r\n * \\image html LinearInterp.gif \"Linear interpolation\"\r\n *\r\n * \\par\r\n * A Linear Interpolate function calculates an output value(y), for the input(x)\r\n * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)\r\n *\r\n * \\par Algorithm:\r\n * 
\r\n   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))\r\n   *       where x0, x1 are nearest values of input x\r\n   *             y0, y1 are nearest values to output y\r\n   *
\r\n *\r\n * \\par\r\n * This set of functions implements Linear interpolation process\r\n * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single\r\n * sample of data and each call to the function returns a single processed value.\r\n * S points to an instance of the Linear Interpolate function data structure.\r\n * x is the input sample value. The functions returns the output value.\r\n * \r\n * \\par\r\n * if x is outside of the table boundary, Linear interpolation returns first value of the table \r\n * if x is below input range and returns last value of table if x is above range. \r\n */\r\n\r\n /**\r\n * @addtogroup LinearInterpolate\r\n * @{\r\n */\r\n\r\n /**\r\n * @brief Process function for the floating-point Linear Interpolation Function.\r\n * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure\r\n * @param[in] x input sample to process\r\n * @return y processed output sample.\r\n *\r\n */\r\n\r\n static __INLINE float32_t arm_linear_interp_f32(\r\n\t\t\t\t\t\t arm_linear_interp_instance_f32 * S,\r\n\t\t\t\t\t\t float32_t x)\r\n {\r\n\r\n\t float32_t y;\r\n\t float32_t x0, x1;\t\t\t\t\t\t/* Nearest input values */\r\n\t float32_t y0, y1;\t \t\t\t\t\t/* Nearest output values */\r\n\t float32_t xSpacing = S->xSpacing;\t\t/* spacing between input values */\r\n\t int32_t i; \t\t\t\t\t\t\t/* Index variable */\r\n\t float32_t *pYData = S->pYData;\t /* pointer to output table */\r\n\r\n\t /* Calculation of index */\r\n\t i = (x - S->x1) / xSpacing;\r\n\r\n\t if(i < 0)\r\n\t {\r\n\t /* Iniatilize output for below specified range as least output value of table */\r\n\t\t y = pYData[0];\r\n\t }\r\n\t else if(i >= S->nValues)\r\n\t {\r\n\t \t /* Iniatilize output for above specified range as last output value of table */\r\n\t \t y = pYData[S->nValues-1];\t\r\n\t }\r\n\t else\r\n\t {\t \r\n\t \t /* Calculation of nearest input values */\r\n\t\t x0 = S->x1 + i * xSpacing;\r\n\t\t x1 = S->x1 + (i +1) * xSpacing;\r\n\t\t \r\n\t\t /* Read of nearest output values */\r\n\t\t y0 = pYData[i];\r\n\t\t y1 = pYData[i + 1];\r\n\t\t\r\n\t\t /* Calculation of output */\r\n\t\t y = y0 + (x - x0) * ((y1 - y0)/(x1-x0));\t\r\n\t\t\r\n\t }\r\n\r\n /* returns output value */\r\n\t return (y);\r\n }\r\n\r\n /**\r\n *\r\n * @brief Process function for the Q31 Linear Interpolation Function.\r\n * @param[in] *pYData pointer to Q31 Linear Interpolation table\r\n * @param[in] x input sample to process\r\n * @param[in] nValues number of table values\r\n * @return y processed output sample.\r\n *\r\n * \\par\r\n * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r\n * This function can support maximum of table size 2^12.\r\n *\r\n */\r\n\r\n\r\n static __INLINE q31_t arm_linear_interp_q31(q31_t *pYData,\r\n\t\t\t\t\t q31_t x, uint32_t nValues)\r\n {\r\n q31_t y; /* output */\r\n q31_t y0, y1; /* Nearest output values */\r\n q31_t fract; /* fractional part */\r\n int32_t index; /* Index to read nearest output values */\r\n \r\n /* Input is in 12.20 format */\r\n /* 12 bits for the table index */\r\n /* Index value calculation */\r\n index = ((x & 0xFFF00000) >> 20);\r\n\r\n\tif(index >= (nValues - 1))\r\n\t{\r\n\t\treturn(pYData[nValues - 1]);\r\n\t}\r\n\telse if(index < 0)\r\n\t{\r\n\t\treturn(pYData[0]);\r\n\t}\r\n\telse\r\n\t{\r\n\r\n\t /* 20 bits for the fractional part */\r\n\t /* shift left by 11 to keep fract in 1.31 format */\r\n\t fract = (x & 0x000FFFFF) << 11;\r\n\t\r\n\t /* Read two nearest output values from the index in 1.31(q31) format */\r\n\t y0 = pYData[index];\r\n\t y1 = pYData[index + 1u];\r\n\t\r\n\t /* Calculation of y0 * (1-fract) and y is in 2.30 format */\r\n\t y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));\r\n\t\r\n\t /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */\r\n\t y += ((q31_t) (((q63_t) y1 * fract) >> 32));\r\n\t\r\n\t /* Convert y to 1.31 format */\r\n\t return (y << 1u);\r\n\r\n\t}\r\n\r\n }\r\n\r\n /**\r\n *\r\n * @brief Process function for the Q15 Linear Interpolation Function.\r\n * @param[in] *pYData pointer to Q15 Linear Interpolation table\r\n * @param[in] x input sample to process\r\n * @param[in] nValues number of table values\r\n * @return y processed output sample.\r\n *\r\n * \\par\r\n * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r\n * This function can support maximum of table size 2^12. \r\n *\r\n */\r\n\r\n\r\n static __INLINE q15_t arm_linear_interp_q15(q15_t *pYData, q31_t x, uint32_t nValues)\r\n {\r\n q63_t y; /* output */\r\n q15_t y0, y1; /* Nearest output values */\r\n q31_t fract; /* fractional part */\r\n int32_t index; /* Index to read nearest output values */ \r\n\r\n /* Input is in 12.20 format */\r\n /* 12 bits for the table index */\r\n /* Index value calculation */\r\n index = ((x & 0xFFF00000) >> 20u); \r\n\r\n\tif(index >= (nValues - 1))\r\n\t{\r\n\t\treturn(pYData[nValues - 1]);\r\n\t}\r\n\telse if(index < 0)\r\n\t{\r\n\t\treturn(pYData[0]);\r\n\t}\r\n\telse\r\n\t{\t\r\n\t /* 20 bits for the fractional part */\r\n\t /* fract is in 12.20 format */\r\n\t fract = (x & 0x000FFFFF);\r\n\t\r\n\t /* Read two nearest output values from the index */\r\n\t y0 = pYData[index];\r\n\t y1 = pYData[index + 1u];\r\n\t\r\n\t /* Calculation of y0 * (1-fract) and y is in 13.35 format */\r\n\t y = ((q63_t) y0 * (0xFFFFF - fract));\r\n\t\r\n\t /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */\r\n\t y += ((q63_t) y1 * (fract));\r\n\t\r\n\t /* convert y to 1.15 format */\r\n\t return (y >> 20);\r\n\t}\r\n\r\n\r\n }\r\n\r\n /**\r\n *\r\n * @brief Process function for the Q7 Linear Interpolation Function.\r\n * @param[in] *pYData pointer to Q7 Linear Interpolation table\r\n * @param[in] x input sample to process\r\n * @param[in] nValues number of table values\r\n * @return y processed output sample.\r\n *\r\n * \\par\r\n * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r\n * This function can support maximum of table size 2^12.\r\n */\r\n\r\n\r\n static __INLINE q7_t arm_linear_interp_q7(q7_t *pYData, q31_t x, uint32_t nValues)\r\n {\r\n q31_t y; /* output */\r\n q7_t y0, y1; /* Nearest output values */\r\n q31_t fract; /* fractional part */\r\n int32_t index; /* Index to read nearest output values */\r\n \r\n /* Input is in 12.20 format */\r\n /* 12 bits for the table index */\r\n /* Index value calculation */\r\n index = ((x & 0xFFF00000) >> 20u);\r\n\r\n\r\n if(index >= (nValues - 1))\r\n\t{\r\n\t\treturn(pYData[nValues - 1]);\r\n\t}\r\n\telse if(index < 0)\r\n\t{\r\n\t\treturn(pYData[0]);\r\n\t}\r\n\telse\r\n\t{\r\n\r\n\t /* 20 bits for the fractional part */\r\n\t /* fract is in 12.20 format */\r\n\t fract = (x & 0x000FFFFF);\r\n\t\r\n\t /* Read two nearest output values from the index and are in 1.7(q7) format */\r\n\t y0 = pYData[index];\r\n\t y1 = pYData[index + 1u];\r\n\t\r\n\t /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */\r\n\t y = ((y0 * (0xFFFFF - fract)));\r\n\t\r\n\t /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */\r\n\t y += (y1 * fract);\r\n\t\r\n\t /* convert y to 1.7(q7) format */\r\n\t return (y >> 20u);\r\n\r\n\t}\r\n\r\n }\r\n /**\r\n * @} end of LinearInterpolate group\r\n */\r\n\r\n /**\r\n * @brief Fast approximation to the trigonometric sine function for floating-point data.\r\n * @param[in] x input value in radians.\r\n * @return sin(x).\r\n */\r\n\r\n float32_t arm_sin_f32(\r\n\t\t\t float32_t x);\r\n\r\n /**\r\n * @brief Fast approximation to the trigonometric sine function for Q31 data.\r\n * @param[in] x Scaled input value in radians.\r\n * @return sin(x).\r\n */\r\n\r\n q31_t arm_sin_q31(\r\n\t\t q31_t x);\r\n\r\n /**\r\n * @brief Fast approximation to the trigonometric sine function for Q15 data.\r\n * @param[in] x Scaled input value in radians.\r\n * @return sin(x).\r\n */\r\n\r\n q15_t arm_sin_q15(\r\n\t\t q15_t x);\r\n\r\n /**\r\n * @brief Fast approximation to the trigonometric cosine function for floating-point data.\r\n * @param[in] x input value in radians.\r\n * @return cos(x).\r\n */\r\n\r\n float32_t arm_cos_f32(\r\n\t\t\t float32_t x);\r\n\r\n /**\r\n * @brief Fast approximation to the trigonometric cosine function for Q31 data.\r\n * @param[in] x Scaled input value in radians.\r\n * @return cos(x).\r\n */\r\n\r\n q31_t arm_cos_q31(\r\n\t\t q31_t x);\r\n\r\n /**\r\n * @brief Fast approximation to the trigonometric cosine function for Q15 data.\r\n * @param[in] x Scaled input value in radians.\r\n * @return cos(x).\r\n */\r\n\r\n q15_t arm_cos_q15(\r\n\t\t q15_t x);\r\n\r\n\r\n /**\r\n * @ingroup groupFastMath\r\n */\r\n\r\n\r\n /**\r\n * @defgroup SQRT Square Root\r\n *\r\n * Computes the square root of a number.\r\n * There are separate functions for Q15, Q31, and floating-point data types. \r\n * The square root function is computed using the Newton-Raphson algorithm.\r\n * This is an iterative algorithm of the form:\r\n * 
\r\n   *      x1 = x0 - f(x0)/f'(x0)\r\n   *
\r\n * where x1 is the current estimate,\r\n * x0 is the previous estimate and\r\n * f'(x0) is the derivative of f() evaluated at x0.\r\n * For the square root function, the algorithm reduces to:\r\n * 
\r\n   *     x0 = in/2                         [initial guess]\r\n   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]\r\n   *
\r\n */\r\n\r\n\r\n /**\r\n * @addtogroup SQRT\r\n * @{\r\n */\r\n\r\n /**\r\n * @brief Floating-point square root function.\r\n * @param[in] in input value.\r\n * @param[out] *pOut square root of input value.\r\n * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r\n * in is negative value and returns zero output for negative values.\r\n */\r\n\r\n static __INLINE arm_status arm_sqrt_f32(\r\n\t\t\t\t\t float32_t in, float32_t *pOut)\r\n {\r\n \tif(in > 0)\r\n\t{\r\n\r\n//\t#if __FPU_USED\r\n #if (__FPU_USED == 1) && defined ( __CC_ARM )\r\n\t\t*pOut = __sqrtf(in);\r\n\t#else\t \r\n\t\t*pOut = sqrtf(in);\r\n\t#endif\r\n\r\n\t\treturn (ARM_MATH_SUCCESS);\r\n\t}\r\n \telse\r\n\t{\r\n\t\t*pOut = 0.0f;\r\n\t\treturn (ARM_MATH_ARGUMENT_ERROR);\r\n\t}\r\n\r\n }\r\n\r\n\r\n /**\r\n * @brief Q31 square root function.\r\n * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.\r\n * @param[out] *pOut square root of input value.\r\n * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r\n * in is negative value and returns zero output for negative values.\r\n */\r\n arm_status arm_sqrt_q31(\r\n\t\t q31_t in, q31_t *pOut);\r\n\r\n /**\r\n * @brief Q15 square root function.\r\n * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.\r\n * @param[out] *pOut square root of input value.\r\n * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r\n * in is negative value and returns zero output for negative values.\r\n */\r\n arm_status arm_sqrt_q15(\r\n\t\t q15_t in, q15_t *pOut);\r\n\r\n /**\r\n * @} end of SQRT group\r\n */\r\n\r\n\r\n\r\n\r\n\r\n\r\n /**\r\n * @brief floating-point Circular write function.\r\n */\r\n\r\n static __INLINE void arm_circularWrite_f32(\r\n\t\t\t\t\t int32_t * circBuffer,\r\n\t\t\t\t\t int32_t L,\r\n\t\t\t\t\t uint16_t * writeOffset,\r\n\t\t\t\t\t int32_t bufferInc,\r\n\t\t\t\t\t const int32_t * src,\r\n\t\t\t\t\t int32_t srcInc,\r\n\t\t\t\t\t uint32_t blockSize)\r\n {\r\n uint32_t i = 0u;\r\n int32_t wOffset;\r\n\r\n /* Copy the value of Index pointer that points\r\n * to the current location where the input samples to be copied */\r\n wOffset = *writeOffset;\r\n\r\n /* Loop over the blockSize */\r\n i = blockSize;\r\n\r\n while(i > 0u)\r\n {\r\n\t/* copy the input sample to the circular buffer */\r\n\tcircBuffer[wOffset] = *src;\r\n\r\n\t/* Update the input pointer */\r\n\tsrc += srcInc;\r\n\r\n\t/* Circularly update wOffset. Watch out for positive and negative value */\r\n\twOffset += bufferInc;\r\n\tif(wOffset >= L)\r\n\t wOffset -= L;\r\n\r\n\t/* Decrement the loop counter */\r\n\ti--;\r\n }\r\n\r\n /* Update the index pointer */\r\n *writeOffset = wOffset;\r\n }\r\n\r\n\r\n\r\n /**\r\n * @brief floating-point Circular Read function.\r\n */\r\n static __INLINE void arm_circularRead_f32(\r\n\t\t\t\t\t int32_t * circBuffer,\r\n\t\t\t\t\t int32_t L,\r\n\t\t\t\t\t int32_t * readOffset,\r\n\t\t\t\t\t int32_t bufferInc,\r\n\t\t\t\t\t int32_t * dst,\r\n\t\t\t\t\t int32_t * dst_base,\r\n\t\t\t\t\t int32_t dst_length,\r\n\t\t\t\t\t int32_t dstInc,\r\n\t\t\t\t\t uint32_t blockSize)\r\n {\r\n uint32_t i = 0u;\r\n int32_t rOffset, dst_end;\r\n\r\n /* Copy the value of Index pointer that points\r\n * to the current location from where the input samples to be read */\r\n rOffset = *readOffset;\r\n dst_end = (int32_t) (dst_base + dst_length);\r\n\r\n /* Loop over the blockSize */\r\n i = blockSize;\r\n\r\n while(i > 0u)\r\n {\r\n\t/* copy the sample from the circular buffer to the destination buffer */\r\n\t*dst = circBuffer[rOffset];\r\n\r\n\t/* Update the input pointer */\r\n\tdst += dstInc;\r\n\r\n\tif(dst == (int32_t *) dst_end)\r\n\t {\r\n\t dst = dst_base;\r\n\t }\r\n\r\n\t/* Circularly update rOffset. Watch out for positive and negative value */\r\n\trOffset += bufferInc;\r\n\r\n\tif(rOffset >= L)\r\n\t {\r\n\t rOffset -= L;\r\n\t }\r\n\r\n\t/* Decrement the loop counter */\r\n\ti--;\r\n }\r\n\r\n /* Update the index pointer */\r\n *readOffset = rOffset;\r\n }\r\n\r\n /**\r\n * @brief Q15 Circular write function.\r\n */\r\n\r\n static __INLINE void arm_circularWrite_q15(\r\n\t\t\t\t\t q15_t * circBuffer,\r\n\t\t\t\t\t int32_t L,\r\n\t\t\t\t\t uint16_t * writeOffset,\r\n\t\t\t\t\t int32_t bufferInc,\r\n\t\t\t\t\t const q15_t * src,\r\n\t\t\t\t\t int32_t srcInc,\r\n\t\t\t\t\t uint32_t blockSize)\r\n {\r\n uint32_t i = 0u;\r\n int32_t wOffset;\r\n\r\n /* Copy the value of Index pointer that points\r\n * to the current location where the input samples to be copied */\r\n wOffset = *writeOffset;\r\n\r\n /* Loop over the blockSize */\r\n i = blockSize;\r\n\r\n while(i > 0u)\r\n {\r\n\t/* copy the input sample to the circular buffer */\r\n\tcircBuffer[wOffset] = *src;\r\n\r\n\t/* Update the input pointer */\r\n\tsrc += srcInc;\r\n\r\n\t/* Circularly update wOffset. Watch out for positive and negative value */\r\n\twOffset += bufferInc;\r\n\tif(wOffset >= L)\r\n\t wOffset -= L;\r\n\r\n\t/* Decrement the loop counter */\r\n\ti--;\r\n }\r\n\r\n /* Update the index pointer */\r\n *writeOffset = wOffset;\r\n }\r\n\r\n\r\n\r\n /**\r\n * @brief Q15 Circular Read function.\r\n */\r\n static __INLINE void arm_circularRead_q15(\r\n\t\t\t\t\t q15_t * circBuffer,\r\n\t\t\t\t\t int32_t L,\r\n\t\t\t\t\t int32_t * readOffset,\r\n\t\t\t\t\t int32_t bufferInc,\r\n\t\t\t\t\t q15_t * dst,\r\n\t\t\t\t\t q15_t * dst_base,\r\n\t\t\t\t\t int32_t dst_length,\r\n\t\t\t\t\t int32_t dstInc,\r\n\t\t\t\t\t uint32_t blockSize)\r\n {\r\n uint32_t i = 0;\r\n int32_t rOffset, dst_end;\r\n\r\n /* Copy the value of Index pointer that points\r\n * to the current location from where the input samples to be read */\r\n rOffset = *readOffset;\r\n\r\n dst_end = (int32_t) (dst_base + dst_length);\r\n\r\n /* Loop over the blockSize */\r\n i = blockSize;\r\n\r\n while(i > 0u)\r\n {\r\n\t/* copy the sample from the circular buffer to the destination buffer */\r\n\t*dst = circBuffer[rOffset];\r\n\r\n\t/* Update the input pointer */\r\n\tdst += dstInc;\r\n\r\n\tif(dst == (q15_t *) dst_end)\r\n\t {\r\n\t dst = dst_base;\r\n\t }\r\n\r\n\t/* Circularly update wOffset. Watch out for positive and negative value */\r\n\trOffset += bufferInc;\r\n\r\n\tif(rOffset >= L)\r\n\t {\r\n\t rOffset -= L;\r\n\t }\r\n\r\n\t/* Decrement the loop counter */\r\n\ti--;\r\n }\r\n\r\n /* Update the index pointer */\r\n *readOffset = rOffset;\r\n }\r\n\r\n\r\n /**\r\n * @brief Q7 Circular write function.\r\n */\r\n\r\n static __INLINE void arm_circularWrite_q7(\r\n\t\t\t\t\t q7_t * circBuffer,\r\n\t\t\t\t\t int32_t L,\r\n\t\t\t\t\t uint16_t * writeOffset,\r\n\t\t\t\t\t int32_t bufferInc,\r\n\t\t\t\t\t const q7_t * src,\r\n\t\t\t\t\t int32_t srcInc,\r\n\t\t\t\t\t uint32_t blockSize)\r\n {\r\n uint32_t i = 0u;\r\n int32_t wOffset;\r\n\r\n /* Copy the value of Index pointer that points\r\n * to the current location where the input samples to be copied */\r\n wOffset = *writeOffset;\r\n\r\n /* Loop over the blockSize */\r\n i = blockSize;\r\n\r\n while(i > 0u)\r\n {\r\n\t/* copy the input sample to the circular buffer */\r\n\tcircBuffer[wOffset] = *src;\r\n\r\n\t/* Update the input pointer */\r\n\tsrc += srcInc;\r\n\r\n\t/* Circularly update wOffset. Watch out for positive and negative value */\r\n\twOffset += bufferInc;\r\n\tif(wOffset >= L)\r\n\t wOffset -= L;\r\n\r\n\t/* Decrement the loop counter */\r\n\ti--;\r\n }\r\n\r\n /* Update the index pointer */\r\n *writeOffset = wOffset;\r\n }\r\n\r\n\r\n\r\n /**\r\n * @brief Q7 Circular Read function.\r\n */\r\n static __INLINE void arm_circularRead_q7(\r\n\t\t\t\t\t q7_t * circBuffer,\r\n\t\t\t\t\t int32_t L,\r\n\t\t\t\t\t int32_t * readOffset,\r\n\t\t\t\t\t int32_t bufferInc,\r\n\t\t\t\t\t q7_t * dst,\r\n\t\t\t\t\t q7_t * dst_base,\r\n\t\t\t\t\t int32_t dst_length,\r\n\t\t\t\t\t int32_t dstInc,\r\n\t\t\t\t\t uint32_t blockSize)\r\n {\r\n uint32_t i = 0;\r\n int32_t rOffset, dst_end;\r\n\r\n /* Copy the value of Index pointer that points\r\n * to the current location from where the input samples to be read */\r\n rOffset = *readOffset;\r\n\r\n dst_end = (int32_t) (dst_base + dst_length);\r\n\r\n /* Loop over the blockSize */\r\n i = blockSize;\r\n\r\n while(i > 0u)\r\n {\r\n\t/* copy the sample from the circular buffer to the destination buffer */\r\n\t*dst = circBuffer[rOffset];\r\n\r\n\t/* Update the input pointer */\r\n\tdst += dstInc;\r\n\r\n\tif(dst == (q7_t *) dst_end)\r\n\t {\r\n\t dst = dst_base;\r\n\t }\r\n\r\n\t/* Circularly update rOffset. Watch out for positive and negative value */\r\n\trOffset += bufferInc;\r\n\r\n\tif(rOffset >= L)\r\n\t {\r\n\t rOffset -= L;\r\n\t }\r\n\r\n\t/* Decrement the loop counter */\r\n\ti--;\r\n }\r\n\r\n /* Update the index pointer */\r\n *readOffset = rOffset;\r\n }\r\n\r\n\r\n /**\r\n * @brief Sum of the squares of the elements of a Q31 vector.\r\n * @param[in] *pSrc is input pointer\r\n * @param[in] blockSize is the number of samples to process\r\n * @param[out] *pResult is output value.\r\n * @return none.\r\n */\r\n\r\n void arm_power_q31(\r\n\t\t q31_t * pSrc,\r\n\t\t uint32_t blockSize,\r\n\t\t q63_t * pResult);\r\n\r\n /**\r\n * @brief Sum of the squares of the elements of a floating-point vector.\r\n * @param[in] *pSrc is input pointer\r\n * @param[in] blockSize is the number of samples to process\r\n * @param[out] *pResult is output value.\r\n * @return none.\r\n */\r\n\r\n void arm_power_f32(\r\n\t\t float32_t * pSrc,\r\n\t\t uint32_t blockSize,\r\n\t\t float32_t * pResult);\r\n\r\n /**\r\n * @brief Sum of the squares of the elements of a Q15 vector.\r\n * @param[in] *pSrc is input pointer\r\n * @param[in] blockSize is the number of samples to process\r\n * @param[out] *pResult is output value.\r\n * @return none.\r\n */\r\n\r\n void arm_power_q15(\r\n\t\t q15_t * pSrc,\r\n\t\t uint32_t blockSize,\r\n\t\t q63_t * pResult);\r\n\r\n /**\r\n * @brief Sum of the squares of the elements of a Q7 vector.\r\n * @param[in] *pSrc is input pointer\r\n * @param[in] blockSize is the number of samples to process\r\n * @param[out] *pResult is output value.\r\n * @return none.\r\n */\r\n\r\n void arm_power_q7(\r\n\t\t q7_t * pSrc,\r\n\t\t uint32_t blockSize,\r\n\t\t q31_t * pResult);\r\n\r\n /**\r\n * @brief Mean value of a Q7 vector.\r\n * @param[in] *pSrc is input pointer\r\n * @param[in] blockSize is the number of samples to process\r\n * @param[out] *pResult is output value.\r\n * @return none.\r\n */\r\n\r\n void arm_mean_q7(\r\n\t\t q7_t * pSrc,\r\n\t\t uint32_t blockSize,\r\n\t\t q7_t * pResult);\r\n\r\n /**\r\n * @brief Mean value of a Q15 vector.\r\n * @param[in] *pSrc is input pointer\r\n * @param[in] blockSize is the number of samples to process\r\n * @param[out] *pResult is output value.\r\n * @return none.\r\n */\r\n void arm_mean_q15(\r\n\t\t q15_t * pSrc,\r\n\t\t uint32_t blockSize,\r\n\t\t q15_t * pResult);\r\n\r\n /**\r\n * @brief Mean value of a Q31 vector.\r\n * @param[in] *pSrc is input pointer\r\n * @param[in] blockSize is the number of samples to process\r\n * @param[out] *pResult is output value.\r\n * @return none.\r\n */\r\n void arm_mean_q31(\r\n\t\t q31_t * pSrc,\r\n\t\t uint32_t blockSize,\r\n\t\t q31_t * pResult);\r\n\r\n /**\r\n * @brief Mean value of a floating-point vector.\r\n * @param[in] *pSrc is input pointer\r\n * @param[in] blockSize is the number of samples to process\r\n * @param[out] *pResult is output value.\r\n * @return none.\r\n */\r\n void arm_mean_f32(\r\n\t\t float32_t * pSrc,\r\n\t\t uint32_t blockSize,\r\n\t\t float32_t * pResult);\r\n\r\n /**\r\n * @brief Variance of the elements of a floating-point vector.\r\n * @param[in] *pSrc is input pointer\r\n * @param[in] blockSize is the number of samples to process\r\n * @param[out] *pResult is output value.\r\n * @return none.\r\n */\r\n\r\n void arm_var_f32(\r\n\t\t float32_t * pSrc,\r\n\t\t uint32_t blockSize,\r\n\t\t float32_t * pResult);\r\n\r\n /**\r\n * @brief Variance of the elements of a Q31 vector.\r\n * @param[in] *pSrc is input pointer\r\n * @param[in] blockSize is the number of samples to process\r\n * @param[out] *pResult is output value.\r\n * @return none.\r\n */\r\n\r\n void arm_var_q31(\r\n\t\t q31_t * pSrc,\r\n\t\t uint32_t blockSize,\r\n\t\t q63_t * pResult);\r\n\r\n /**\r\n * @brief Variance of the elements of a Q15 vector.\r\n * @param[in] *pSrc is input pointer\r\n * @param[in] blockSize is the number of samples to process\r\n * @param[out] *pResult is output value.\r\n * @return none.\r\n */\r\n\r\n void arm_var_q15(\r\n\t\t q15_t * pSrc,\r\n\t\t uint32_t blockSize,\r\n\t\t q31_t * pResult);\r\n\r\n /**\r\n * @brief Root Mean Square of the elements of a floating-point vector.\r\n * @param[in] *pSrc is input pointer\r\n * @param[in] blockSize is the number of samples to process\r\n * @param[out] *pResult is output value.\r\n * @return none.\r\n */\r\n\r\n void arm_rms_f32(\r\n\t\t float32_t * pSrc,\r\n\t\t uint32_t blockSize,\r\n\t\t float32_t * pResult);\r\n\r\n /**\r\n * @brief Root Mean Square of the elements of a Q31 vector.\r\n * @param[in] *pSrc is input pointer\r\n * @param[in] blockSize is the number of samples to process\r\n * @param[out] *pResult is output value.\r\n * @return none.\r\n */\r\n\r\n void arm_rms_q31(\r\n\t\t q31_t * pSrc,\r\n\t\t uint32_t blockSize,\r\n\t\t q31_t * pResult);\r\n\r\n /**\r\n * @brief Root Mean Square of the elements of a Q15 vector.\r\n * @param[in] *pSrc is input pointer\r\n * @param[in] blockSize is the number of samples to process\r\n * @param[out] *pResult is output value.\r\n * @return none.\r\n */\r\n\r\n void arm_rms_q15(\r\n\t\t q15_t * pSrc,\r\n\t\t uint32_t blockSize,\r\n\t\t q15_t * pResult);\r\n\r\n /**\r\n * @brief Standard deviation of the elements of a floating-point vector.\r\n * @param[in] *pSrc is input pointer\r\n * @param[in] blockSize is the number of samples to process\r\n * @param[out] *pResult is output value.\r\n * @return none.\r\n */\r\n\r\n void arm_std_f32(\r\n\t\t float32_t * pSrc,\r\n\t\t uint32_t blockSize,\r\n\t\t float32_t * pResult);\r\n\r\n /**\r\n * @brief Standard deviation of the elements of a Q31 vector.\r\n * @param[in] *pSrc is input pointer\r\n * @param[in] blockSize is the number of samples to process\r\n * @param[out] *pResult is output value.\r\n * @return none.\r\n */\r\n\r\n void arm_std_q31(\r\n\t\t q31_t * pSrc,\r\n\t\t uint32_t blockSize,\r\n\t\t q31_t * pResult);\r\n\r\n /**\r\n * @brief Standard deviation of the elements of a Q15 vector.\r\n * @param[in] *pSrc is input pointer\r\n * @param[in] blockSize is the number of samples to process\r\n * @param[out] *pResult is output value.\r\n * @return none.\r\n */\r\n\r\n void arm_std_q15(\r\n\t\t q15_t * pSrc,\r\n\t\t uint32_t blockSize,\r\n\t\t q15_t * pResult);\r\n\r\n /**\r\n * @brief Floating-point complex magnitude\r\n * @param[in] *pSrc points to the complex input vector\r\n * @param[out] *pDst points to the real output vector\r\n * @param[in] numSamples number of complex samples in the input vector\r\n * @return none.\r\n */\r\n\r\n void arm_cmplx_mag_f32(\r\n\t\t\t float32_t * pSrc,\r\n\t\t\t float32_t * pDst,\r\n\t\t\t uint32_t numSamples);\r\n\r\n /**\r\n * @brief Q31 complex magnitude\r\n * @param[in] *pSrc points to the complex input vector\r\n * @param[out] *pDst points to the real output vector\r\n * @param[in] numSamples number of complex samples in the input vector\r\n * @return none.\r\n */\r\n\r\n void arm_cmplx_mag_q31(\r\n\t\t\t q31_t * pSrc,\r\n\t\t\t q31_t * pDst,\r\n\t\t\t uint32_t numSamples);\r\n\r\n /**\r\n * @brief Q15 complex magnitude\r\n * @param[in] *pSrc points to the complex input vector\r\n * @param[out] *pDst points to the real output vector\r\n * @param[in] numSamples number of complex samples in the input vector\r\n * @return none.\r\n */\r\n\r\n void arm_cmplx_mag_q15(\r\n\t\t\t q15_t * pSrc,\r\n\t\t\t q15_t * pDst,\r\n\t\t\t uint32_t numSamples);\r\n\r\n /**\r\n * @brief Q15 complex dot product\r\n * @param[in] *pSrcA points to the first input vector\r\n * @param[in] *pSrcB points to the second input vector\r\n * @param[in] numSamples number of complex samples in each vector\r\n * @param[out] *realResult real part of the result returned here\r\n * @param[out] *imagResult imaginary part of the result returned here\r\n * @return none.\r\n */\r\n\r\n void arm_cmplx_dot_prod_q15(\r\n\t\t\t q15_t * pSrcA,\r\n\t\t\t q15_t * pSrcB,\r\n\t\t\t uint32_t numSamples,\r\n\t\t\t q31_t * realResult,\r\n\t\t\t q31_t * imagResult);\r\n\r\n /**\r\n * @brief Q31 complex dot product\r\n * @param[in] *pSrcA points to the first input vector\r\n * @param[in] *pSrcB points to the second input vector\r\n * @param[in] numSamples number of complex samples in each vector\r\n * @param[out] *realResult real part of the result returned here\r\n * @param[out] *imagResult imaginary part of the result returned here\r\n * @return none.\r\n */\r\n\r\n void arm_cmplx_dot_prod_q31(\r\n\t\t\t q31_t * pSrcA,\r\n\t\t\t q31_t * pSrcB,\r\n\t\t\t uint32_t numSamples,\r\n\t\t\t q63_t * realResult,\r\n\t\t\t q63_t * imagResult);\r\n\r\n /**\r\n * @brief Floating-point complex dot product\r\n * @param[in] *pSrcA points to the first input vector\r\n * @param[in] *pSrcB points to the second input vector\r\n * @param[in] numSamples number of complex samples in each vector\r\n * @param[out] *realResult real part of the result returned here\r\n * @param[out] *imagResult imaginary part of the result returned here\r\n * @return none.\r\n */\r\n\r\n void arm_cmplx_dot_prod_f32(\r\n\t\t\t float32_t * pSrcA,\r\n\t\t\t float32_t * pSrcB,\r\n\t\t\t uint32_t numSamples,\r\n\t\t\t float32_t * realResult,\r\n\t\t\t float32_t * imagResult);\r\n\r\n /**\r\n * @brief Q15 complex-by-real multiplication\r\n * @param[in] *pSrcCmplx points to the complex input vector\r\n * @param[in] *pSrcReal points to the real input vector\r\n * @param[out] *pCmplxDst points to the complex output vector\r\n * @param[in] numSamples number of samples in each vector\r\n * @return none.\r\n */\r\n\r\n void arm_cmplx_mult_real_q15(\r\n\t\t\t q15_t * pSrcCmplx,\r\n\t\t\t q15_t * pSrcReal,\r\n\t\t\t q15_t * pCmplxDst,\r\n\t\t\t uint32_t numSamples);\r\n\r\n /**\r\n * @brief Q31 complex-by-real multiplication\r\n * @param[in] *pSrcCmplx points to the complex input vector\r\n * @param[in] *pSrcReal points to the real input vector\r\n * @param[out] *pCmplxDst points to the complex output vector\r\n * @param[in] numSamples number of samples in each vector\r\n * @return none.\r\n */\r\n\r\n void arm_cmplx_mult_real_q31(\r\n\t\t\t q31_t * pSrcCmplx,\r\n\t\t\t q31_t * pSrcReal,\r\n\t\t\t q31_t * pCmplxDst,\r\n\t\t\t uint32_t numSamples);\r\n\r\n /**\r\n * @brief Floating-point complex-by-real multiplication\r\n * @param[in] *pSrcCmplx points to the complex input vector\r\n * @param[in] *pSrcReal points to the real input vector\r\n * @param[out] *pCmplxDst points to the complex output vector\r\n * @param[in] numSamples number of samples in each vector\r\n * @return none.\r\n */\r\n\r\n void arm_cmplx_mult_real_f32(\r\n\t\t\t float32_t * pSrcCmplx,\r\n\t\t\t float32_t * pSrcReal,\r\n\t\t\t float32_t * pCmplxDst,\r\n\t\t\t uint32_t numSamples);\r\n\r\n /**\r\n * @brief Minimum value of a Q7 vector.\r\n * @param[in] *pSrc is input pointer\r\n * @param[in] blockSize is the number of samples to process\r\n * @param[out] *result is output pointer\r\n * @param[in] index is the array index of the minimum value in the input buffer.\r\n * @return none.\r\n */\r\n\r\n void arm_min_q7(\r\n\t\t q7_t * pSrc,\r\n\t\t uint32_t blockSize,\r\n\t\t q7_t * result,\r\n\t\t uint32_t * index);\r\n\r\n /**\r\n * @brief Minimum value of a Q15 vector.\r\n * @param[in] *pSrc is input pointer\r\n * @param[in] blockSize is the number of samples to process\r\n * @param[out] *pResult is output pointer\r\n * @param[in] *pIndex is the array index of the minimum value in the input buffer.\r\n * @return none.\r\n */\r\n\r\n void arm_min_q15(\r\n\t\t q15_t * pSrc,\r\n\t\t uint32_t blockSize,\r\n\t\t q15_t * pResult,\r\n\t\t uint32_t * pIndex);\r\n\r\n /**\r\n * @brief Minimum value of a Q31 vector.\r\n * @param[in] *pSrc is input pointer\r\n * @param[in] blockSize is the number of samples to process\r\n * @param[out] *pResult is output pointer\r\n * @param[out] *pIndex is the array index of the minimum value in the input buffer.\r\n * @return none.\r\n */\r\n void arm_min_q31(\r\n\t\t q31_t * pSrc,\r\n\t\t uint32_t blockSize,\r\n\t\t q31_t * pResult,\r\n\t\t uint32_t * pIndex);\r\n\r\n /**\r\n * @brief Minimum value of a floating-point vector.\r\n * @param[in] *pSrc is input pointer\r\n * @param[in] blockSize is the number of samples to process\r\n * @param[out] *pResult is output pointer\r\n * @param[out] *pIndex is the array index of the minimum value in the input buffer.\r\n * @return none.\r\n */\r\n\r\n void arm_min_f32(\r\n\t\t float32_t * pSrc,\r\n\t\t uint32_t blockSize,\r\n\t\t float32_t * pResult,\r\n\t\t uint32_t * pIndex);\r\n\r\n/**\r\n * @brief Maximum value of a Q7 vector.\r\n * @param[in] *pSrc points to the input buffer\r\n * @param[in] blockSize length of the input vector\r\n * @param[out] *pResult maximum value returned here\r\n * @param[out] *pIndex index of maximum value returned here\r\n * @return none.\r\n */\r\n\r\n void arm_max_q7(\r\n\t\t q7_t * pSrc,\r\n\t\t uint32_t blockSize,\r\n\t\t q7_t * pResult,\r\n\t\t uint32_t * pIndex);\r\n\r\n/**\r\n * @brief Maximum value of a Q15 vector.\r\n * @param[in] *pSrc points to the input buffer\r\n * @param[in] blockSize length of the input vector\r\n * @param[out] *pResult maximum value returned here\r\n * @param[out] *pIndex index of maximum value returned here\r\n * @return none.\r\n */\r\n\r\n void arm_max_q15(\r\n\t\t q15_t * pSrc,\r\n\t\t uint32_t blockSize,\r\n\t\t q15_t * pResult,\r\n\t\t uint32_t * pIndex);\r\n\r\n/**\r\n * @brief Maximum value of a Q31 vector.\r\n * @param[in] *pSrc points to the input buffer\r\n * @param[in] blockSize length of the input vector\r\n * @param[out] *pResult maximum value returned here\r\n * @param[out] *pIndex index of maximum value returned here\r\n * @return none.\r\n */\r\n\r\n void arm_max_q31(\r\n\t\t q31_t * pSrc,\r\n\t\t uint32_t blockSize,\r\n\t\t q31_t * pResult,\r\n\t\t uint32_t * pIndex);\r\n\r\n/**\r\n * @brief Maximum value of a floating-point vector.\r\n * @param[in] *pSrc points to the input buffer\r\n * @param[in] blockSize length of the input vector\r\n * @param[out] *pResult maximum value returned here\r\n * @param[out] *pIndex index of maximum value returned here\r\n * @return none.\r\n */\r\n\r\n void arm_max_f32(\r\n\t\t float32_t * pSrc,\r\n\t\t uint32_t blockSize,\r\n\t\t float32_t * pResult,\r\n\t\t uint32_t * pIndex);\r\n\r\n /**\r\n * @brief Q15 complex-by-complex multiplication\r\n * @param[in] *pSrcA points to the first input vector\r\n * @param[in] *pSrcB points to the second input vector\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] numSamples number of complex samples in each vector\r\n * @return none.\r\n */\r\n\r\n void arm_cmplx_mult_cmplx_q15(\r\n\t\t\t q15_t * pSrcA,\r\n\t\t\t q15_t * pSrcB,\r\n\t\t\t q15_t * pDst,\r\n\t\t\t uint32_t numSamples);\r\n\r\n /**\r\n * @brief Q31 complex-by-complex multiplication\r\n * @param[in] *pSrcA points to the first input vector\r\n * @param[in] *pSrcB points to the second input vector\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] numSamples number of complex samples in each vector\r\n * @return none.\r\n */\r\n\r\n void arm_cmplx_mult_cmplx_q31(\r\n\t\t\t q31_t * pSrcA,\r\n\t\t\t q31_t * pSrcB,\r\n\t\t\t q31_t * pDst,\r\n\t\t\t uint32_t numSamples);\r\n\r\n /**\r\n * @brief Floating-point complex-by-complex multiplication\r\n * @param[in] *pSrcA points to the first input vector\r\n * @param[in] *pSrcB points to the second input vector\r\n * @param[out] *pDst points to the output vector\r\n * @param[in] numSamples number of complex samples in each vector\r\n * @return none.\r\n */\r\n\r\n void arm_cmplx_mult_cmplx_f32(\r\n\t\t\t float32_t * pSrcA,\r\n\t\t\t float32_t * pSrcB,\r\n\t\t\t float32_t * pDst,\r\n\t\t\t uint32_t numSamples);\r\n\r\n /**\r\n * @brief Converts the elements of the floating-point vector to Q31 vector. \r\n * @param[in] *pSrc points to the floating-point input vector \r\n * @param[out] *pDst points to the Q31 output vector\r\n * @param[in] blockSize length of the input vector \r\n * @return none. \r\n */\r\n void arm_float_to_q31(\r\n\t\t\t float32_t * pSrc,\r\n\t\t\t q31_t * pDst,\r\n\t\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Converts the elements of the floating-point vector to Q15 vector. \r\n * @param[in] *pSrc points to the floating-point input vector \r\n * @param[out] *pDst points to the Q15 output vector\r\n * @param[in] blockSize length of the input vector \r\n * @return none\r\n */\r\n void arm_float_to_q15(\r\n\t\t\t float32_t * pSrc,\r\n\t\t\t q15_t * pDst,\r\n\t\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Converts the elements of the floating-point vector to Q7 vector. \r\n * @param[in] *pSrc points to the floating-point input vector \r\n * @param[out] *pDst points to the Q7 output vector\r\n * @param[in] blockSize length of the input vector \r\n * @return none\r\n */\r\n void arm_float_to_q7(\r\n\t\t\t float32_t * pSrc,\r\n\t\t\t q7_t * pDst,\r\n\t\t\t uint32_t blockSize);\r\n\r\n\r\n /**\r\n * @brief Converts the elements of the Q31 vector to Q15 vector.\r\n * @param[in] *pSrc is input pointer\r\n * @param[out] *pDst is output pointer\r\n * @param[in] blockSize is the number of samples to process\r\n * @return none.\r\n */\r\n void arm_q31_to_q15(\r\n\t\t q31_t * pSrc,\r\n\t\t q15_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Converts the elements of the Q31 vector to Q7 vector.\r\n * @param[in] *pSrc is input pointer\r\n * @param[out] *pDst is output pointer\r\n * @param[in] blockSize is the number of samples to process\r\n * @return none.\r\n */\r\n void arm_q31_to_q7(\r\n\t\t q31_t * pSrc,\r\n\t\t q7_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n /**\r\n * @brief Converts the elements of the Q15 vector to floating-point vector.\r\n * @param[in] *pSrc is input pointer\r\n * @param[out] *pDst is output pointer\r\n * @param[in] blockSize is the number of samples to process\r\n * @return none.\r\n */\r\n void arm_q15_to_float(\r\n\t\t\t q15_t * pSrc,\r\n\t\t\tfloat32_t * pDst,\r\n\t\t\tuint32_t blockSize);\r\n\r\n\r\n /**\r\n * @brief Converts the elements of the Q15 vector to Q31 vector.\r\n * @param[in] *pSrc is input pointer\r\n * @param[out] *pDst is output pointer\r\n * @param[in] blockSize is the number of samples to process\r\n * @return none.\r\n */\r\n void arm_q15_to_q31(\r\n\t\t q15_t * pSrc,\r\n\t\t q31_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n\r\n /**\r\n * @brief Converts the elements of the Q15 vector to Q7 vector.\r\n * @param[in] *pSrc is input pointer\r\n * @param[out] *pDst is output pointer\r\n * @param[in] blockSize is the number of samples to process\r\n * @return none.\r\n */\r\n void arm_q15_to_q7(\r\n\t\t q15_t * pSrc,\r\n\t\t q7_t * pDst,\r\n\t\t uint32_t blockSize);\r\n\r\n\r\n /**\r\n * @ingroup groupInterpolation\r\n */\r\n\r\n /**\r\n * @defgroup BilinearInterpolate Bilinear Interpolation\r\n *\r\n * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.\r\n * The underlying function f(x, y) is sampled on a regular grid and the interpolation process\r\n * determines values between the grid points.\r\n * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.\r\n * Bilinear interpolation is often used in image processing to rescale images.\r\n * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.\r\n *\r\n * Algorithm\r\n * \\par\r\n * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.\r\n * For floating-point, the instance structure is defined as:\r\n * 
\r\n   *   typedef struct\r\n   *   {\r\n   *     uint16_t numRows;\r\n   *     uint16_t numCols;\r\n   *     float32_t *pData;\r\n   * } arm_bilinear_interp_instance_f32;\r\n   *
\r\n *\r\n * \\par\r\n * where numRows specifies the number of rows in the table;\r\n * numCols specifies the number of columns in the table;\r\n * and pData points to an array of size numRows*numCols values.\r\n * The data table pTable is organized in row order and the supplied data values fall on integer indexes.\r\n * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers.\r\n *\r\n * \\par\r\n * Let (x, y) specify the desired interpolation point. Then define:\r\n * 
\r\n   *     XF = floor(x)\r\n   *     YF = floor(y)\r\n   *
\r\n * \\par\r\n * The interpolated output point is computed as:\r\n * 
\r\n   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))\r\n   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))\r\n   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)\r\n   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)\r\n   *
\r\n * Note that the coordinates (x, y) contain integer and fractional components. \r\n * The integer components specify which portion of the table to use while the\r\n * fractional components control the interpolation processor.\r\n *\r\n * \\par\r\n * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. \r\n */\r\n\r\n /**\r\n * @addtogroup BilinearInterpolate\r\n * @{\r\n */\r\n\r\n /**\r\n *\r\n * @brief Floating-point bilinear interpolation.\r\n * @param[in,out] *S points to an instance of the interpolation structure.\r\n * @param[in] X interpolation coordinate.\r\n * @param[in] Y interpolation coordinate.\r\n * @return out interpolated value.\r\n */\r\n\r\n \r\n static __INLINE float32_t arm_bilinear_interp_f32(\r\n\t\t\t\t\t\t const arm_bilinear_interp_instance_f32 * S,\r\n\t\t\t\t\t\t float32_t X,\r\n\t\t\t\t\t\t float32_t Y)\r\n {\r\n float32_t out;\r\n float32_t f00, f01, f10, f11;\r\n float32_t *pData = S->pData;\r\n int32_t xIndex, yIndex, index;\r\n float32_t xdiff, ydiff;\r\n float32_t b1, b2, b3, b4;\r\n\r\n xIndex = (int32_t) X;\r\n yIndex = (int32_t) Y;\r\n\r\n\t/* Care taken for table outside boundary */\r\n\t/* Returns zero output when values are outside table boundary */\r\n\tif(xIndex < 0 || xIndex > (S->numRows-1) || yIndex < 0 || yIndex > ( S->numCols-1))\r\n\t{\r\n\t\treturn(0);\r\n\t}\r\n\t\r\n /* Calculation of index for two nearest points in X-direction */\r\n index = (xIndex - 1) + (yIndex-1) * S->numCols ;\r\n\r\n\r\n /* Read two nearest points in X-direction */\r\n f00 = pData[index];\r\n f01 = pData[index + 1];\r\n\r\n /* Calculation of index for two nearest points in Y-direction */\r\n index = (xIndex-1) + (yIndex) * S->numCols;\r\n\r\n\r\n /* Read two nearest points in Y-direction */\r\n f10 = pData[index];\r\n f11 = pData[index + 1];\r\n\r\n /* Calculation of intermediate values */\r\n b1 = f00;\r\n b2 = f01 - f00;\r\n b3 = f10 - f00;\r\n b4 = f00 - f01 - f10 + f11;\r\n\r\n /* Calculation of fractional part in X */\r\n xdiff = X - xIndex;\r\n\r\n /* Calculation of fractional part in Y */\r\n ydiff = Y - yIndex;\r\n\r\n /* Calculation of bi-linear interpolated output */\r\n out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;\r\n\r\n /* return to application */\r\n return (out);\r\n\r\n }\r\n\r\n /**\r\n *\r\n * @brief Q31 bilinear interpolation.\r\n * @param[in,out] *S points to an instance of the interpolation structure.\r\n * @param[in] X interpolation coordinate in 12.20 format.\r\n * @param[in] Y interpolation coordinate in 12.20 format.\r\n * @return out interpolated value.\r\n */\r\n\r\n static __INLINE q31_t arm_bilinear_interp_q31(\r\n\t\t\t\t\t\tarm_bilinear_interp_instance_q31 * S,\r\n\t\t\t\t\t\tq31_t X,\r\n\t\t\t\t\t\tq31_t Y)\r\n {\r\n q31_t out; /* Temporary output */\r\n q31_t acc = 0; /* output */\r\n q31_t xfract, yfract; /* X, Y fractional parts */\r\n q31_t x1, x2, y1, y2; /* Nearest output values */\r\n int32_t rI, cI; /* Row and column indices */\r\n q31_t *pYData = S->pData; /* pointer to output table values */\r\n uint32_t nCols = S->numCols; /* num of rows */\r\n\r\n\r\n /* Input is in 12.20 format */\r\n /* 12 bits for the table index */\r\n /* Index value calculation */\r\n rI = ((X & 0xFFF00000) >> 20u);\r\n\r\n /* Input is in 12.20 format */\r\n /* 12 bits for the table index */\r\n /* Index value calculation */\r\n cI = ((Y & 0xFFF00000) >> 20u);\r\n\r\n\t/* Care taken for table outside boundary */\r\n\t/* Returns zero output when values are outside table boundary */\r\n\tif(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1))\r\n\t{\r\n\t\treturn(0);\r\n\t}\r\n\r\n /* 20 bits for the fractional part */\r\n /* shift left xfract by 11 to keep 1.31 format */\r\n xfract = (X & 0x000FFFFF) << 11u;\r\n\r\n /* Read two nearest output values from the index */\r\n x1 = pYData[(rI) + nCols * (cI)];\r\n x2 = pYData[(rI) + nCols * (cI) + 1u];\r\n\r\n /* 20 bits for the fractional part */\r\n /* shift left yfract by 11 to keep 1.31 format */\r\n yfract = (Y & 0x000FFFFF) << 11u;\r\n\r\n /* Read two nearest output values from the index */\r\n y1 = pYData[(rI) + nCols * (cI + 1)];\r\n y2 = pYData[(rI) + nCols * (cI + 1) + 1u];\r\n\r\n /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */\r\n out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));\r\n acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));\r\n\r\n /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */\r\n out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));\r\n acc += ((q31_t) ((q63_t) out * (xfract) >> 32));\r\n\r\n /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */\r\n out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));\r\n acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\r\n\r\n /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */\r\n out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));\r\n acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\r\n\r\n /* Convert acc to 1.31(q31) format */\r\n return (acc << 2u);\r\n\r\n }\r\n\r\n /**\r\n * @brief Q15 bilinear interpolation.\r\n * @param[in,out] *S points to an instance of the interpolation structure.\r\n * @param[in] X interpolation coordinate in 12.20 format.\r\n * @param[in] Y interpolation coordinate in 12.20 format.\r\n * @return out interpolated value.\r\n */\r\n\r\n static __INLINE q15_t arm_bilinear_interp_q15(\r\n\t\t\t\t\t\tarm_bilinear_interp_instance_q15 * S,\r\n\t\t\t\t\t\tq31_t X,\r\n\t\t\t\t\t\tq31_t Y)\r\n {\r\n q63_t acc = 0; /* output */\r\n q31_t out; /* Temporary output */\r\n q15_t x1, x2, y1, y2; /* Nearest output values */\r\n q31_t xfract, yfract; /* X, Y fractional parts */\r\n int32_t rI, cI; /* Row and column indices */\r\n q15_t *pYData = S->pData; /* pointer to output table values */\r\n uint32_t nCols = S->numCols; /* num of rows */\r\n\r\n /* Input is in 12.20 format */\r\n /* 12 bits for the table index */\r\n /* Index value calculation */\r\n rI = ((X & 0xFFF00000) >> 20);\r\n\r\n /* Input is in 12.20 format */\r\n /* 12 bits for the table index */\r\n /* Index value calculation */\r\n cI = ((Y & 0xFFF00000) >> 20);\r\n\r\n\t/* Care taken for table outside boundary */\r\n\t/* Returns zero output when values are outside table boundary */\r\n\tif(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1))\r\n\t{\r\n\t\treturn(0);\r\n\t}\r\n\r\n /* 20 bits for the fractional part */\r\n /* xfract should be in 12.20 format */\r\n xfract = (X & 0x000FFFFF);\r\n\r\n /* Read two nearest output values from the index */\r\n x1 = pYData[(rI) + nCols * (cI)];\r\n x2 = pYData[(rI) + nCols * (cI) + 1u];\r\n\r\n\r\n /* 20 bits for the fractional part */\r\n /* yfract should be in 12.20 format */\r\n yfract = (Y & 0x000FFFFF);\r\n\r\n /* Read two nearest output values from the index */\r\n y1 = pYData[(rI) + nCols * (cI + 1)];\r\n y2 = pYData[(rI) + nCols * (cI + 1) + 1u];\r\n\r\n /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */\r\n\r\n /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */\r\n /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */\r\n out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);\r\n acc = ((q63_t) out * (0xFFFFF - yfract));\r\n\r\n /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */\r\n out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);\r\n acc += ((q63_t) out * (xfract));\r\n\r\n /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */\r\n out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);\r\n acc += ((q63_t) out * (yfract));\r\n\r\n /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */\r\n out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);\r\n acc += ((q63_t) out * (yfract));\r\n\r\n /* acc is in 13.51 format and down shift acc by 36 times */\r\n /* Convert out to 1.15 format */\r\n return (acc >> 36);\r\n\r\n }\r\n\r\n /**\r\n * @brief Q7 bilinear interpolation.\r\n * @param[in,out] *S points to an instance of the interpolation structure.\r\n * @param[in] X interpolation coordinate in 12.20 format.\r\n * @param[in] Y interpolation coordinate in 12.20 format.\r\n * @return out interpolated value.\r\n */\r\n\r\n static __INLINE q7_t arm_bilinear_interp_q7(\r\n\t\t\t\t\t arm_bilinear_interp_instance_q7 * S,\r\n\t\t\t\t\t q31_t X,\r\n\t\t\t\t\t q31_t Y)\r\n {\r\n q63_t acc = 0; /* output */\r\n q31_t out; /* Temporary output */\r\n q31_t xfract, yfract; /* X, Y fractional parts */\r\n q7_t x1, x2, y1, y2; /* Nearest output values */\r\n int32_t rI, cI; /* Row and column indices */\r\n q7_t *pYData = S->pData; /* pointer to output table values */\r\n uint32_t nCols = S->numCols; /* num of rows */\r\n\r\n /* Input is in 12.20 format */\r\n /* 12 bits for the table index */\r\n /* Index value calculation */\r\n rI = ((X & 0xFFF00000) >> 20);\r\n\r\n /* Input is in 12.20 format */\r\n /* 12 bits for the table index */\r\n /* Index value calculation */\r\n cI = ((Y & 0xFFF00000) >> 20);\r\n\r\n\t/* Care taken for table outside boundary */\r\n\t/* Returns zero output when values are outside table boundary */\r\n\tif(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1))\r\n\t{\r\n\t\treturn(0);\r\n\t}\r\n\r\n /* 20 bits for the fractional part */\r\n /* xfract should be in 12.20 format */\r\n xfract = (X & 0x000FFFFF);\r\n\r\n /* Read two nearest output values from the index */\r\n x1 = pYData[(rI) + nCols * (cI)];\r\n x2 = pYData[(rI) + nCols * (cI) + 1u];\r\n\r\n\r\n /* 20 bits for the fractional part */\r\n /* yfract should be in 12.20 format */\r\n yfract = (Y & 0x000FFFFF);\r\n\r\n /* Read two nearest output values from the index */\r\n y1 = pYData[(rI) + nCols * (cI + 1)];\r\n y2 = pYData[(rI) + nCols * (cI + 1) + 1u];\r\n\r\n /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */\r\n out = ((x1 * (0xFFFFF - xfract)));\r\n acc = (((q63_t) out * (0xFFFFF - yfract)));\r\n\r\n /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */\r\n out = ((x2 * (0xFFFFF - yfract)));\r\n acc += (((q63_t) out * (xfract)));\r\n\r\n /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */\r\n out = ((y1 * (0xFFFFF - xfract)));\r\n acc += (((q63_t) out * (yfract)));\r\n\r\n /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */\r\n out = ((y2 * (yfract)));\r\n acc += (((q63_t) out * (xfract)));\r\n\r\n /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */\r\n return (acc >> 40);\r\n\r\n }\r\n\r\n /**\r\n * @} end of BilinearInterpolate group\r\n */\r\n\r\n\r\n\r\n\r\n\r\n\r\n#ifdef\t__cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif /* _ARM_MATH_H */\r\n\r\n\r\n/**\r\n *\r\n * End of file.\r\n */\r\n" }, { "path": "figure-simulator-discovery/Libraries/CMSIS/Include/core_cm4.h", "content": "/**************************************************************************//**\r\n * @file core_cm4.h\r\n * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File\r\n * @version V2.10\r\n * @date 19. July 2011\r\n *\r\n * @note\r\n * Copyright (C) 2009-2011 ARM Limited. All rights reserved.\r\n *\r\n * @par\r\n * ARM Limited (ARM) is supplying this software for use with Cortex-M\r\n * processor based microcontrollers. This file can be freely distributed\r\n * within development tools that are supporting such ARM based processors.\r\n *\r\n * @par\r\n * THIS SOFTWARE IS PROVIDED \"AS IS\". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r\n * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r\n * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r\n * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r\n * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r\n *\r\n ******************************************************************************/\r\n#if defined ( __ICCARM__ )\r\n #pragma system_include /* treat file as system include file for MISRA check */\r\n#endif\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n#ifndef __CORE_CM4_H_GENERIC\r\n#define __CORE_CM4_H_GENERIC\r\n\r\n\r\n/** \\mainpage CMSIS Cortex-M4\r\n\r\n This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.\r\n It consists of:\r\n\r\n - Cortex-M Core Register Definitions\r\n - Cortex-M functions\r\n - Cortex-M instructions\r\n - Cortex-M SIMD instructions\r\n\r\n The CMSIS Cortex-M4 Core Peripheral Access Layer contains C and assembly functions that ease\r\n access to the Cortex-M Core\r\n */\r\n\r\n/** \\defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions\r\n CMSIS violates following MISRA-C2004 Rules:\r\n \r\n - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
\r\n Function definitions in header files are used to allow 'inlining'. \r\n\r\n - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
\r\n Unions are used for effective representation of core registers.\r\n \r\n - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
\r\n Function-like macros are used to allow more efficient code. \r\n\r\n */\r\n\r\n\r\n/*******************************************************************************\r\n * CMSIS definitions\r\n ******************************************************************************/\r\n/** \\defgroup CMSIS_core_definitions CMSIS Core Definitions\r\n This file defines all structures and symbols for CMSIS core:\r\n - CMSIS version number\r\n - Cortex-M core\r\n - Cortex-M core Revision Number\r\n @{\r\n */\r\n\r\n/* CMSIS CM4 definitions */\r\n#define __CM4_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */\r\n#define __CM4_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */\r\n#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */\r\n\r\n#define __CORTEX_M (0x04) /*!< Cortex core */\r\n\r\n\r\n#if defined ( __CC_ARM )\r\n #define __ASM __asm /*!< asm keyword for ARM Compiler */\r\n #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r\n\r\n#elif defined ( __ICCARM__ )\r\n #define __ASM __asm /*!< asm keyword for IAR Compiler */\r\n #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r\n\r\n#elif defined ( __GNUC__ )\r\n #define __ASM __asm /*!< asm keyword for GNU Compiler */\r\n #define __INLINE inline /*!< inline keyword for GNU Compiler */\r\n\r\n#elif defined ( __TASKING__ )\r\n #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r\n #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r\n\r\n#endif\r\n\r\n/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */\r\n#if defined ( __CC_ARM )\r\n #if defined __TARGET_FPU_VFP\r\n #if (__FPU_PRESENT == 1)\r\n #define __FPU_USED 1\r\n #else\r\n #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n #define __FPU_USED 0\r\n #endif\r\n #else\r\n #define __FPU_USED 0\r\n #endif\r\n\r\n#elif defined ( __ICCARM__ )\r\n #if defined __ARMVFP__\r\n #if (__FPU_PRESENT == 1)\r\n #define __FPU_USED 1\r\n #else\r\n #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n #define __FPU_USED 0\r\n #endif\r\n #else\r\n #define __FPU_USED 0\r\n #endif\r\n\r\n#elif defined ( __GNUC__ )\r\n #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r\n #if (__FPU_PRESENT == 1)\r\n #define __FPU_USED 1\r\n #else\r\n #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n #define __FPU_USED 0\r\n #endif\r\n #else\r\n #define __FPU_USED 0\r\n #endif\r\n\r\n#elif defined ( __TASKING__ )\r\n /* add preprocessor checks to define __FPU_USED */\r\n #define __FPU_USED 0\r\n#endif\r\n\r\n#include /*!< standard types definitions */\r\n#include /*!< Core Instruction Access */\r\n#include /*!< Core Function Access */\r\n#include /*!< Compiler specific SIMD Intrinsics */\r\n\r\n#endif /* __CORE_CM4_H_GENERIC */\r\n\r\n#ifndef __CMSIS_GENERIC\r\n\r\n#ifndef __CORE_CM4_H_DEPENDANT\r\n#define __CORE_CM4_H_DEPENDANT\r\n\r\n/* check device defines and use defaults */\r\n#if defined __CHECK_DEVICE_DEFINES\r\n #ifndef __CM4_REV\r\n #define __CM4_REV 0x0000\r\n #warning \"__CM4_REV not defined in device header file; using default!\"\r\n #endif\r\n\r\n #ifndef __FPU_PRESENT\r\n #define __FPU_PRESENT 0\r\n #warning \"__FPU_PRESENT not defined in device header file; using default!\"\r\n #endif\r\n\r\n #ifndef __MPU_PRESENT\r\n #define __MPU_PRESENT 0\r\n #warning \"__MPU_PRESENT not defined in device header file; using default!\"\r\n #endif\r\n\r\n #ifndef __NVIC_PRIO_BITS\r\n #define __NVIC_PRIO_BITS 4\r\n #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\r\n #endif\r\n\r\n #ifndef __Vendor_SysTickConfig\r\n #define __Vendor_SysTickConfig 0\r\n #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\r\n #endif\r\n#endif\r\n\r\n/* IO definitions (access restrictions to peripheral registers) */\r\n#ifdef __cplusplus\r\n #define __I volatile /*!< defines 'read only' permissions */\r\n#else\r\n #define __I volatile const /*!< defines 'read only' permissions */\r\n#endif\r\n#define __O volatile /*!< defines 'write only' permissions */\r\n#define __IO volatile /*!< defines 'read / write' permissions */\r\n\r\n/*@} end of group CMSIS_core_definitions */\r\n\r\n\r\n\r\n/*******************************************************************************\r\n * Register Abstraction\r\n ******************************************************************************/\r\n/** \\defgroup CMSIS_core_register CMSIS Core Register\r\n Core Register contain:\r\n - Core Register\r\n - Core NVIC Register\r\n - Core SCB Register\r\n - Core SysTick Register\r\n - Core Debug Register\r\n - Core MPU Register\r\n - Core FPU Register\r\n*/\r\n\r\n/** \\ingroup CMSIS_core_register\r\n \\defgroup CMSIS_CORE CMSIS Core\r\n Type definitions for the Cortex-M Core Registers\r\n @{\r\n */\r\n\r\n/** \\brief Union type to access the Application Program Status Register (APSR).\r\n */\r\ntypedef union\r\n{\r\n struct\r\n {\r\n#if (__CORTEX_M != 0x04)\r\n uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r\n#else\r\n uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r\n uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r\n uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r\n#endif\r\n uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r\n uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r\n uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r\n uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r\n uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r\n } b; /*!< Structure used for bit access */\r\n uint32_t w; /*!< Type used for word access */\r\n} APSR_Type;\r\n\r\n\r\n/** \\brief Union type to access the Interrupt Program Status Register (IPSR).\r\n */\r\ntypedef union\r\n{\r\n struct\r\n {\r\n uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r\n uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r\n } b; /*!< Structure used for bit access */\r\n uint32_t w; /*!< Type used for word access */\r\n} IPSR_Type;\r\n\r\n\r\n/** \\brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r\n */\r\ntypedef union\r\n{\r\n struct\r\n {\r\n uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r\n#if (__CORTEX_M != 0x04)\r\n uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r\n#else\r\n uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r\n uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r\n uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r\n#endif\r\n uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r\n uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r\n uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r\n uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r\n uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r\n uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r\n uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r\n } b; /*!< Structure used for bit access */\r\n uint32_t w; /*!< Type used for word access */\r\n} xPSR_Type;\r\n\r\n\r\n/** \\brief Union type to access the Control Registers (CONTROL).\r\n */\r\ntypedef union\r\n{\r\n struct\r\n {\r\n uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r\n uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r\n uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r\n uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r\n } b; /*!< Structure used for bit access */\r\n uint32_t w; /*!< Type used for word access */\r\n} CONTROL_Type;\r\n\r\n/*@} end of group CMSIS_CORE */\r\n\r\n\r\n/** \\ingroup CMSIS_core_register\r\n \\defgroup CMSIS_NVIC CMSIS NVIC\r\n Type definitions for the Cortex-M NVIC Registers\r\n @{\r\n */\r\n\r\n/** \\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r\n */\r\ntypedef struct\r\n{\r\n __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r\n uint32_t RESERVED0[24];\r\n __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r\n uint32_t RSERVED1[24];\r\n __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r\n uint32_t RESERVED2[24];\r\n __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r\n uint32_t RESERVED3[24];\r\n __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r\n uint32_t RESERVED4[56];\r\n __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r\n uint32_t RESERVED5[644];\r\n __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r\n} NVIC_Type;\r\n\r\n/* Software Triggered Interrupt Register Definitions */\r\n#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */\r\n#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */\r\n\r\n/*@} end of group CMSIS_NVIC */\r\n\r\n\r\n/** \\ingroup CMSIS_core_register\r\n \\defgroup CMSIS_SCB CMSIS SCB\r\n Type definitions for the Cortex-M System Control Block Registers\r\n @{\r\n */\r\n\r\n/** \\brief Structure type to access the System Control Block (SCB).\r\n */\r\ntypedef struct\r\n{\r\n __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r\n __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r\n __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r\n __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r\n __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r\n __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r\n __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r\n __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r\n __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r\n __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r\n __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r\n __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r\n __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r\n __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r\n __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r\n __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r\n __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r\n __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r\n __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r\n uint32_t RESERVED0[5];\r\n __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r\n} SCB_Type;\r\n\r\n/* SCB CPUID Register Definitions */\r\n#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r\n#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r\n\r\n#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r\n#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r\n\r\n#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r\n#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r\n\r\n#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r\n#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r\n\r\n#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r\n#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r\n\r\n/* SCB Interrupt Control State Register Definitions */\r\n#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r\n#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r\n\r\n#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r\n#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r\n\r\n#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r\n#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r\n\r\n#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r\n#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r\n\r\n#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r\n#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r\n\r\n#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r\n#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r\n\r\n#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r\n#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r\n\r\n#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r\n#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r\n\r\n#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r\n#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r\n\r\n#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r\n#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r\n\r\n/* SCB Vector Table Offset Register Definitions */\r\n#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r\n#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r\n\r\n/* SCB Application Interrupt and Reset Control Register Definitions */\r\n#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r\n#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r\n\r\n#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r\n#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r\n\r\n#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r\n#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r\n\r\n#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r\n#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r\n\r\n#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r\n#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r\n\r\n#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r\n#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r\n\r\n#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r\n#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r\n\r\n/* SCB System Control Register Definitions */\r\n#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r\n#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r\n\r\n#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r\n#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r\n\r\n#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r\n#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r\n\r\n/* SCB Configuration Control Register Definitions */\r\n#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r\n#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r\n\r\n#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r\n#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r\n\r\n#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r\n#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r\n\r\n#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r\n#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r\n\r\n#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r\n#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r\n\r\n#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r\n#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r\n\r\n/* SCB System Handler Control and State Register Definitions */\r\n#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r\n#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r\n\r\n#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r\n#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r\n\r\n#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r\n#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r\n\r\n#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r\n#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r\n\r\n#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r\n#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r\n\r\n#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r\n#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r\n\r\n#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r\n#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r\n\r\n#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r\n#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r\n\r\n#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r\n#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r\n\r\n#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r\n#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r\n\r\n#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r\n#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r\n\r\n#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r\n#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r\n\r\n#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r\n#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r\n\r\n#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r\n#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r\n\r\n/* SCB Configurable Fault Status Registers Definitions */\r\n#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r\n#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r\n\r\n#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r\n#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r\n\r\n#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r\n#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r\n\r\n/* SCB Hard Fault Status Registers Definitions */\r\n#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r\n#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r\n\r\n#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r\n#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r\n\r\n#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r\n#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r\n\r\n/* SCB Debug Fault Status Register Definitions */\r\n#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r\n#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r\n\r\n#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r\n#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r\n\r\n#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r\n#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r\n\r\n#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r\n#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r\n\r\n#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r\n#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r\n\r\n/*@} end of group CMSIS_SCB */\r\n\r\n\r\n/** \\ingroup CMSIS_core_register\r\n \\defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB\r\n Type definitions for the Cortex-M System Control and ID Register not in the SCB\r\n @{\r\n */\r\n\r\n/** \\brief Structure type to access the System Control and ID Register not in the SCB.\r\n */\r\ntypedef struct\r\n{\r\n uint32_t RESERVED0[1];\r\n __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r\n __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r\n} SCnSCB_Type;\r\n\r\n/* Interrupt Controller Type Register Definitions */\r\n#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */\r\n#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */\r\n\r\n/* Auxiliary Control Register Definitions */\r\n#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */\r\n#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */\r\n\r\n#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */\r\n#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */\r\n\r\n#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */\r\n#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r\n\r\n#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */\r\n#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r\n\r\n#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */\r\n#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */\r\n\r\n/*@} end of group CMSIS_SCnotSCB */\r\n\r\n\r\n/** \\ingroup CMSIS_core_register\r\n \\defgroup CMSIS_SysTick CMSIS SysTick\r\n Type definitions for the Cortex-M System Timer Registers\r\n @{\r\n */\r\n\r\n/** \\brief Structure type to access the System Timer (SysTick).\r\n */\r\ntypedef struct\r\n{\r\n __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r\n __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r\n __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r\n __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r\n} SysTick_Type;\r\n\r\n/* SysTick Control / Status Register Definitions */\r\n#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r\n#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r\n\r\n#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r\n#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r\n\r\n#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r\n#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r\n\r\n#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r\n#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r\n\r\n/* SysTick Reload Register Definitions */\r\n#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r\n#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r\n\r\n/* SysTick Current Register Definitions */\r\n#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r\n#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r\n\r\n/* SysTick Calibration Register Definitions */\r\n#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r\n#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r\n\r\n#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r\n#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r\n\r\n#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r\n#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r\n\r\n/*@} end of group CMSIS_SysTick */\r\n\r\n\r\n/** \\ingroup CMSIS_core_register\r\n \\defgroup CMSIS_ITM CMSIS ITM\r\n Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)\r\n @{\r\n */\r\n\r\n/** \\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r\n */\r\ntypedef struct\r\n{\r\n __O union\r\n {\r\n __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r\n __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r\n __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r\n } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r\n uint32_t RESERVED0[864];\r\n __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r\n uint32_t RESERVED1[15];\r\n __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r\n uint32_t RESERVED2[15];\r\n __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r\n} ITM_Type;\r\n\r\n/* ITM Trace Privilege Register Definitions */\r\n#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r\n#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r\n\r\n/* ITM Trace Control Register Definitions */\r\n#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r\n#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r\n\r\n#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */\r\n#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r\n\r\n#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */\r\n#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r\n\r\n#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r\n#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r\n\r\n#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r\n#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r\n\r\n#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */\r\n#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */\r\n\r\n#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r\n#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r\n\r\n#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r\n#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r\n\r\n#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r\n#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r\n\r\n/*@}*/ /* end of group CMSIS_ITM */\r\n\r\n\r\n#if (__MPU_PRESENT == 1)\r\n/** \\ingroup CMSIS_core_register\r\n \\defgroup CMSIS_MPU CMSIS MPU\r\n Type definitions for the Cortex-M Memory Protection Unit (MPU)\r\n @{\r\n */\r\n\r\n/** \\brief Structure type to access the Memory Protection Unit (MPU).\r\n */\r\ntypedef struct\r\n{\r\n __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r\n __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r\n __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r\n __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r\n __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r\n __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r\n __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r\n __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r\n __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r\n __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r\n __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r\n} MPU_Type;\r\n\r\n/* MPU Type Register */\r\n#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r\n#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r\n\r\n#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r\n#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r\n\r\n#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r\n#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r\n\r\n/* MPU Control Register */\r\n#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r\n#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r\n\r\n#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r\n#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r\n\r\n#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r\n#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r\n\r\n/* MPU Region Number Register */\r\n#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r\n#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r\n\r\n/* MPU Region Base Address Register */\r\n#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r\n#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r\n\r\n#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r\n#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r\n\r\n#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r\n#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r\n\r\n/* MPU Region Attribute and Size Register */\r\n#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r\n#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r\n\r\n#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r\n#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r\n\r\n#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r\n#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r\n\r\n#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r\n#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r\n\r\n/*@} end of group CMSIS_MPU */\r\n#endif\r\n\r\n\r\n#if (__FPU_PRESENT == 1)\r\n/** \\ingroup CMSIS_core_register\r\n \\defgroup CMSIS_FPU CMSIS FPU\r\n Type definitions for the Cortex-M Floating Point Unit (FPU)\r\n @{\r\n */\r\n\r\n/** \\brief Structure type to access the Floating Point Unit (FPU).\r\n */\r\ntypedef struct\r\n{\r\n uint32_t RESERVED0[1];\r\n __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r\n __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r\n __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r\n __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r\n __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r\n} FPU_Type;\r\n\r\n/* Floating-Point Context Control Register */\r\n#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */\r\n#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r\n\r\n#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */\r\n#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r\n\r\n#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */\r\n#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r\n\r\n#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */\r\n#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r\n\r\n#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */\r\n#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r\n\r\n#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */\r\n#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r\n\r\n#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */\r\n#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r\n\r\n#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */\r\n#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r\n\r\n#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */\r\n#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */\r\n\r\n/* Floating-Point Context Address Register */\r\n#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */\r\n#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r\n\r\n/* Floating-Point Default Status Control Register */\r\n#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */\r\n#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r\n\r\n#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */\r\n#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r\n\r\n#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */\r\n#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r\n\r\n#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */\r\n#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r\n\r\n/* Media and FP Feature Register 0 */\r\n#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */\r\n#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r\n\r\n#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */\r\n#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r\n\r\n#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */\r\n#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r\n\r\n#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */\r\n#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r\n\r\n#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */\r\n#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r\n\r\n#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */\r\n#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r\n\r\n#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */\r\n#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r\n\r\n#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */\r\n#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */\r\n\r\n/* Media and FP Feature Register 1 */\r\n#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */\r\n#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r\n\r\n#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */\r\n#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r\n\r\n#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */\r\n#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r\n\r\n#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */\r\n#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */\r\n\r\n/*@} end of group CMSIS_FPU */\r\n#endif\r\n\r\n\r\n/** \\ingroup CMSIS_core_register\r\n \\defgroup CMSIS_CoreDebug CMSIS Core Debug\r\n Type definitions for the Cortex-M Core Debug Registers\r\n @{\r\n */\r\n\r\n/** \\brief Structure type to access the Core Debug Register (CoreDebug).\r\n */\r\ntypedef struct\r\n{\r\n __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r\n __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r\n __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r\n __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r\n} CoreDebug_Type;\r\n\r\n/* Debug Halting Control and Status Register */\r\n#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r\n#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r\n\r\n#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r\n#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r\n\r\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r\n\r\n#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r\n#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r\n\r\n#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r\n#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r\n\r\n#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r\n#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r\n\r\n#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r\n#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r\n\r\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r\n\r\n#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r\n#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r\n\r\n#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r\n#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r\n\r\n#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r\n#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r\n\r\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r\n\r\n/* Debug Core Register Selector Register */\r\n#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r\n#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r\n\r\n#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r\n#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r\n\r\n/* Debug Exception and Monitor Control Register */\r\n#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r\n#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r\n#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r\n#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r\n#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r\n#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r\n#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r\n#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r\n#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r\n#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r\n#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r\n#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r\n#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r\n\r\n/*@} end of group CMSIS_CoreDebug */\r\n\r\n\r\n/** \\ingroup CMSIS_core_register\r\n @{\r\n */\r\n\r\n/* Memory mapping of Cortex-M4 Hardware */\r\n#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r\n#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r\n#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r\n#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r\n#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r\n#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r\n\r\n#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r\n#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r\n#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r\n#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r\n#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r\n#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r\n\r\n#if (__MPU_PRESENT == 1)\r\n #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r\n #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r\n#endif\r\n\r\n#if (__FPU_PRESENT == 1)\r\n #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r\n #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r\n#endif\r\n\r\n/*@} */\r\n\r\n\r\n\r\n/*******************************************************************************\r\n * Hardware Abstraction Layer\r\n ******************************************************************************/\r\n/** \\defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface\r\n Core Function Interface contains:\r\n - Core NVIC Functions\r\n - Core SysTick Functions\r\n - Core Debug Functions\r\n - Core Register Access Functions\r\n*/\r\n\r\n\r\n\r\n/* ########################## NVIC functions #################################### */\r\n/** \\ingroup CMSIS_Core_FunctionInterface\r\n \\defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions\r\n @{\r\n */\r\n\r\n/** \\brief Set Priority Grouping\r\n\r\n This function sets the priority grouping field using the required unlock sequence.\r\n The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r\n Only values from 0..7 are used.\r\n In case of a conflict between priority grouping and available\r\n priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r\n\r\n \\param [in] PriorityGroup Priority grouping field\r\n */\r\nstatic __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r\n{\r\n uint32_t reg_value;\r\n uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */\r\n\r\n reg_value = SCB->AIRCR; /* read old register configuration */\r\n reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r\n reg_value = (reg_value |\r\n ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r\n (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r\n SCB->AIRCR = reg_value;\r\n}\r\n\r\n\r\n/** \\brief Get Priority Grouping\r\n\r\n This function gets the priority grouping from NVIC Interrupt Controller.\r\n Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.\r\n\r\n \\return Priority grouping field\r\n */\r\nstatic __INLINE uint32_t NVIC_GetPriorityGrouping(void)\r\n{\r\n return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r\n}\r\n\r\n\r\n/** \\brief Enable External Interrupt\r\n\r\n This function enables a device specific interrupt in the NVIC interrupt controller.\r\n The interrupt number cannot be a negative value.\r\n\r\n \\param [in] IRQn Number of the external interrupt to enable\r\n */\r\nstatic __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r\n{\r\n/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */\r\n NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */\r\n}\r\n\r\n\r\n/** \\brief Disable External Interrupt\r\n\r\n This function disables a device specific interrupt in the NVIC interrupt controller.\r\n The interrupt number cannot be a negative value.\r\n\r\n \\param [in] IRQn Number of the external interrupt to disable\r\n */\r\nstatic __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r\n{\r\n NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r\n}\r\n\r\n\r\n/** \\brief Get Pending Interrupt\r\n\r\n This function reads the pending register in the NVIC and returns the pending bit\r\n for the specified interrupt.\r\n\r\n \\param [in] IRQn Number of the interrupt for get pending\r\n \\return 0 Interrupt status is not pending\r\n \\return 1 Interrupt status is pending\r\n */\r\nstatic __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r\n}\r\n\r\n\r\n/** \\brief Set Pending Interrupt\r\n\r\n This function sets the pending bit for the specified interrupt.\r\n The interrupt number cannot be a negative value.\r\n\r\n \\param [in] IRQn Number of the interrupt for set pending\r\n */\r\nstatic __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r\n}\r\n\r\n\r\n/** \\brief Clear Pending Interrupt\r\n\r\n This function clears the pending bit for the specified interrupt.\r\n The interrupt number cannot be a negative value.\r\n\r\n \\param [in] IRQn Number of the interrupt for clear pending\r\n */\r\nstatic __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r\n{\r\n NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r\n}\r\n\r\n\r\n/** \\brief Get Active Interrupt\r\n\r\n This function reads the active register in NVIC and returns the active bit.\r\n \\param [in] IRQn Number of the interrupt for get active\r\n \\return 0 Interrupt status is not active\r\n \\return 1 Interrupt status is active\r\n */\r\nstatic __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r\n{\r\n return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r\n}\r\n\r\n\r\n/** \\brief Set Interrupt Priority\r\n\r\n This function sets the priority for the specified interrupt. The interrupt\r\n number can be positive to specify an external (device specific)\r\n interrupt, or negative to specify an internal (core) interrupt.\r\n\r\n Note: The priority cannot be set for every core interrupt.\r\n\r\n \\param [in] IRQn Number of the interrupt for set priority\r\n \\param [in] priority Priority to set\r\n */\r\nstatic __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r\n{\r\n if(IRQn < 0) {\r\n SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */\r\n else {\r\n NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r\n}\r\n\r\n\r\n/** \\brief Get Interrupt Priority\r\n\r\n This function reads the priority for the specified interrupt. The interrupt\r\n number can be positive to specify an external (device specific)\r\n interrupt, or negative to specify an internal (core) interrupt.\r\n\r\n The returned priority value is automatically aligned to the implemented\r\n priority bits of the microcontroller.\r\n\r\n \\param [in] IRQn Number of the interrupt for get priority\r\n \\return Interrupt Priority\r\n */\r\nstatic __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r\n{\r\n\r\n if(IRQn < 0) {\r\n return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */\r\n else {\r\n return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r\n}\r\n\r\n\r\n/** \\brief Encode Priority\r\n\r\n This function encodes the priority for an interrupt with the given priority group,\r\n preemptive priority value and sub priority value.\r\n In case of a conflict between priority grouping and available\r\n priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r\n\r\n The returned priority value can be used for NVIC_SetPriority(...) function\r\n\r\n \\param [in] PriorityGroup Used priority group\r\n \\param [in] PreemptPriority Preemptive priority value (starting from 0)\r\n \\param [in] SubPriority Sub priority value (starting from 0)\r\n \\return Encoded priority for the interrupt\r\n */\r\nstatic __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r\n{\r\n uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r\n uint32_t PreemptPriorityBits;\r\n uint32_t SubPriorityBits;\r\n\r\n PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r\n SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r\n\r\n return (\r\n ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r\n ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r\n );\r\n}\r\n\r\n\r\n/** \\brief Decode Priority\r\n\r\n This function decodes an interrupt priority value with the given priority group to\r\n preemptive priority value and sub priority value.\r\n In case of a conflict between priority grouping and available\r\n priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r\n\r\n The priority value can be retrieved with NVIC_GetPriority(...) function\r\n\r\n \\param [in] Priority Priority value\r\n \\param [in] PriorityGroup Used priority group\r\n \\param [out] pPreemptPriority Preemptive priority value (starting from 0)\r\n \\param [out] pSubPriority Sub priority value (starting from 0)\r\n */\r\nstatic __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r\n{\r\n uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r\n uint32_t PreemptPriorityBits;\r\n uint32_t SubPriorityBits;\r\n\r\n PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r\n SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r\n\r\n *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r\n *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r\n}\r\n\r\n\r\n/** \\brief System Reset\r\n\r\n This function initiate a system reset request to reset the MCU.\r\n */\r\nstatic __INLINE void NVIC_SystemReset(void)\r\n{\r\n __DSB(); /* Ensure all outstanding memory accesses included\r\n buffered write are completed before reset */\r\n SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r\n (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r\n SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r\n __DSB(); /* Ensure completion of memory access */\r\n while(1); /* wait until reset */\r\n}\r\n\r\n/*@} end of CMSIS_Core_NVICFunctions */\r\n\r\n\r\n\r\n/* ################################## SysTick function ############################################ */\r\n/** \\ingroup CMSIS_Core_FunctionInterface\r\n \\defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions\r\n @{\r\n */\r\n\r\n#if (__Vendor_SysTickConfig == 0)\r\n\r\n/** \\brief System Tick Configuration\r\n\r\n This function initialises the system tick timer and its interrupt and start the system tick timer.\r\n Counter is in free running mode to generate periodical interrupts.\r\n\r\n \\param [in] ticks Number of ticks between two interrupts\r\n \\return 0 Function succeeded\r\n \\return 1 Function failed\r\n */\r\nstatic __INLINE uint32_t SysTick_Config(uint32_t ticks)\r\n{\r\n if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r\n\r\n SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */\r\n NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */\r\n SysTick->VAL = 0; /* Load the SysTick Counter Value */\r\n SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r\n SysTick_CTRL_TICKINT_Msk |\r\n SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r\n return (0); /* Function successful */\r\n}\r\n\r\n#endif\r\n\r\n/*@} end of CMSIS_Core_SysTickFunctions */\r\n\r\n\r\n\r\n/* ##################################### Debug In/Output function ########################################### */\r\n/** \\ingroup CMSIS_Core_FunctionInterface\r\n \\defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions\r\n @{\r\n */\r\n\r\nextern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */\r\n#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */\r\n\r\n\r\n/** \\brief ITM Send Character\r\n\r\n This function transmits a character via the ITM channel 0.\r\n It just returns when no debugger is connected that has booked the output.\r\n It is blocking when a debugger is connected, but the previous character send is not transmitted.\r\n\r\n \\param [in] ch Character to transmit\r\n \\return Character to transmit\r\n */\r\nstatic __INLINE uint32_t ITM_SendChar (uint32_t ch)\r\n{\r\n if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */\r\n (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r\n (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */\r\n {\r\n while (ITM->PORT[0].u32 == 0);\r\n ITM->PORT[0].u8 = (uint8_t) ch;\r\n }\r\n return (ch);\r\n}\r\n\r\n\r\n/** \\brief ITM Receive Character\r\n\r\n This function inputs a character via external variable ITM_RxBuffer.\r\n It just returns when no debugger is connected that has booked the output.\r\n It is blocking when a debugger is connected, but the previous character send is not transmitted.\r\n\r\n \\return Received character\r\n \\return -1 No character received\r\n */\r\nstatic __INLINE int32_t ITM_ReceiveChar (void) {\r\n int32_t ch = -1; /* no character available */\r\n\r\n if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r\n ch = ITM_RxBuffer;\r\n ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r\n }\r\n\r\n return (ch);\r\n}\r\n\r\n\r\n/** \\brief ITM Check Character\r\n\r\n This function checks external variable ITM_RxBuffer whether a character is available or not.\r\n It returns '1' if a character is available and '0' if no character is available.\r\n\r\n \\return 0 No character available\r\n \\return 1 Character available\r\n */\r\nstatic __INLINE int32_t ITM_CheckChar (void) {\r\n\r\n if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r\n return (0); /* no character available */\r\n } else {\r\n return (1); /* character available */\r\n }\r\n}\r\n\r\n/*@} end of CMSIS_core_DebugFunctions */\r\n\r\n#endif /* __CORE_CM4_H_DEPENDANT */\r\n\r\n#endif /* __CMSIS_GENERIC */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n" }, { "path": "figure-simulator-discovery/Libraries/CMSIS/Include/core_cm4_simd.h", "content": "/**************************************************************************//**\r\n * @file core_cm4_simd.h\r\n * @brief CMSIS Cortex-M4 SIMD Header File\r\n * @version V2.10\r\n * @date 19. July 2011\r\n *\r\n * @note\r\n * Copyright (C) 2010-2011 ARM Limited. All rights reserved.\r\n *\r\n * @par\r\n * ARM Limited (ARM) is supplying this software for use with Cortex-M \r\n * processor based microcontrollers. This file can be freely distributed \r\n * within development tools that are supporting such ARM based processors. \r\n *\r\n * @par\r\n * THIS SOFTWARE IS PROVIDED \"AS IS\". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r\n * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r\n * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r\n * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r\n * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r\n *\r\n ******************************************************************************/\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif \r\n\r\n#ifndef __CORE_CM4_SIMD_H\r\n#define __CORE_CM4_SIMD_H\r\n\r\n\r\n/*******************************************************************************\r\n * Hardware Abstraction Layer\r\n ******************************************************************************/\r\n\r\n\r\n/* ################### Compiler specific Intrinsics ########################### */\r\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r\n Access to dedicated SIMD instructions\r\n @{\r\n*/\r\n\r\n#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r\n/* ARM armcc specific functions */\r\n\r\n/*------ CM4 SOMD Intrinsics -----------------------------------------------------*/\r\n#define __SADD8 __sadd8\r\n#define __QADD8 __qadd8\r\n#define __SHADD8 __shadd8\r\n#define __UADD8 __uadd8\r\n#define __UQADD8 __uqadd8\r\n#define __UHADD8 __uhadd8\r\n#define __SSUB8 __ssub8\r\n#define __QSUB8 __qsub8\r\n#define __SHSUB8 __shsub8\r\n#define __USUB8 __usub8\r\n#define __UQSUB8 __uqsub8\r\n#define __UHSUB8 __uhsub8\r\n#define __SADD16 __sadd16\r\n#define __QADD16 __qadd16\r\n#define __SHADD16 __shadd16\r\n#define __UADD16 __uadd16\r\n#define __UQADD16 __uqadd16\r\n#define __UHADD16 __uhadd16\r\n#define __SSUB16 __ssub16\r\n#define __QSUB16 __qsub16\r\n#define __SHSUB16 __shsub16\r\n#define __USUB16 __usub16\r\n#define __UQSUB16 __uqsub16\r\n#define __UHSUB16 __uhsub16\r\n#define __SASX __sasx\r\n#define __QASX __qasx\r\n#define __SHASX __shasx\r\n#define __UASX __uasx\r\n#define __UQASX __uqasx\r\n#define __UHASX __uhasx\r\n#define __SSAX __ssax\r\n#define __QSAX __qsax\r\n#define __SHSAX __shsax\r\n#define __USAX __usax\r\n#define __UQSAX __uqsax\r\n#define __UHSAX __uhsax\r\n#define __USAD8 __usad8\r\n#define __USADA8 __usada8\r\n#define __SSAT16 __ssat16\r\n#define __USAT16 __usat16\r\n#define __UXTB16 __uxtb16\r\n#define __UXTAB16 __uxtab16\r\n#define __SXTB16 __sxtb16\r\n#define __SXTAB16 __sxtab16\r\n#define __SMUAD __smuad\r\n#define __SMUADX __smuadx\r\n#define __SMLAD __smlad\r\n#define __SMLADX __smladx\r\n#define __SMLALD __smlald\r\n#define __SMLALDX __smlaldx\r\n#define __SMUSD __smusd\r\n#define __SMUSDX __smusdx\r\n#define __SMLSD __smlsd\r\n#define __SMLSDX __smlsdx\r\n#define __SMLSLD __smlsld\r\n#define __SMLSLDX __smlsldx\r\n#define __SEL __sel\r\n#define __QADD __qadd\r\n#define __QSUB __qsub\r\n\r\n#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \\\r\n ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )\r\n\r\n#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \\\r\n ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )\r\n\r\n\r\n/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/\r\n\r\n\r\n\r\n#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r\n/* IAR iccarm specific functions */\r\n\r\n#include \r\n\r\n/*------ CM4 SIMDDSP Intrinsics -----------------------------------------------------*/\r\n/* intrinsic __SADD8 see intrinsics.h */\r\n/* intrinsic __QADD8 see intrinsics.h */\r\n/* intrinsic __SHADD8 see intrinsics.h */\r\n/* intrinsic __UADD8 see intrinsics.h */\r\n/* intrinsic __UQADD8 see intrinsics.h */\r\n/* intrinsic __UHADD8 see intrinsics.h */\r\n/* intrinsic __SSUB8 see intrinsics.h */\r\n/* intrinsic __QSUB8 see intrinsics.h */\r\n/* intrinsic __SHSUB8 see intrinsics.h */\r\n/* intrinsic __USUB8 see intrinsics.h */\r\n/* intrinsic __UQSUB8 see intrinsics.h */\r\n/* intrinsic __UHSUB8 see intrinsics.h */\r\n/* intrinsic __SADD16 see intrinsics.h */\r\n/* intrinsic __QADD16 see intrinsics.h */\r\n/* intrinsic __SHADD16 see intrinsics.h */\r\n/* intrinsic __UADD16 see intrinsics.h */\r\n/* intrinsic __UQADD16 see intrinsics.h */\r\n/* intrinsic __UHADD16 see intrinsics.h */\r\n/* intrinsic __SSUB16 see intrinsics.h */\r\n/* intrinsic __QSUB16 see intrinsics.h */\r\n/* intrinsic __SHSUB16 see intrinsics.h */\r\n/* intrinsic __USUB16 see intrinsics.h */\r\n/* intrinsic __UQSUB16 see intrinsics.h */\r\n/* intrinsic __UHSUB16 see intrinsics.h */\r\n/* intrinsic __SASX see intrinsics.h */\r\n/* intrinsic __QASX see intrinsics.h */\r\n/* intrinsic __SHASX see intrinsics.h */\r\n/* intrinsic __UASX see intrinsics.h */\r\n/* intrinsic __UQASX see intrinsics.h */\r\n/* intrinsic __UHASX see intrinsics.h */\r\n/* intrinsic __SSAX see intrinsics.h */\r\n/* intrinsic __QSAX see intrinsics.h */\r\n/* intrinsic __SHSAX see intrinsics.h */\r\n/* intrinsic __USAX see intrinsics.h */\r\n/* intrinsic __UQSAX see intrinsics.h */\r\n/* intrinsic __UHSAX see intrinsics.h */\r\n/* intrinsic __USAD8 see intrinsics.h */\r\n/* intrinsic __USADA8 see intrinsics.h */\r\n/* intrinsic __SSAT16 see intrinsics.h */\r\n/* intrinsic __USAT16 see intrinsics.h */\r\n/* intrinsic __UXTB16 see intrinsics.h */\r\n/* intrinsic __SXTB16 see intrinsics.h */\r\n/* intrinsic __UXTAB16 see intrinsics.h */\r\n/* intrinsic __SXTAB16 see intrinsics.h */\r\n/* intrinsic __SMUAD see intrinsics.h */\r\n/* intrinsic __SMUADX see intrinsics.h */\r\n/* intrinsic __SMLAD see intrinsics.h */\r\n/* intrinsic __SMLADX see intrinsics.h */\r\n/* intrinsic __SMLALD see intrinsics.h */\r\n/* intrinsic __SMLALDX see intrinsics.h */\r\n/* intrinsic __SMUSD see intrinsics.h */\r\n/* intrinsic __SMUSDX see intrinsics.h */\r\n/* intrinsic __SMLSD see intrinsics.h */\r\n/* intrinsic __SMLSDX see intrinsics.h */\r\n/* intrinsic __SMLSLD see intrinsics.h */\r\n/* intrinsic __SMLSLDX see intrinsics.h */\r\n/* intrinsic __SEL see intrinsics.h */\r\n/* intrinsic __QADD see intrinsics.h */\r\n/* intrinsic __QSUB see intrinsics.h */\r\n/* intrinsic __PKHBT see intrinsics.h */\r\n/* intrinsic __PKHTB see intrinsics.h */\r\n\r\n/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/\r\n\r\n\r\n\r\n#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r\n/* GNU gcc specific functions */\r\n\r\n/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"sadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"qadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"shadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"uadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"uqadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"uhadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"ssub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"qsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"shsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"usub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"uqsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"uhsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"sadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"qadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"shadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"uadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"uqadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"uhadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"ssub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"qsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"shsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"usub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"uqsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"uhsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"sasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"qasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"shasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"uasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"uqasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"uhasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"ssax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"qsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"shsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"usax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"uqsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"uhsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"usad8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"usada8 %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\r\n return(result);\r\n}\r\n\r\n#define __SSAT16(ARG1,ARG2) \\\r\n({ \\\r\n uint32_t __RES, __ARG1 = (ARG1); \\\r\n __ASM (\"ssat16 %0, %1, %2\" : \"=r\" (__RES) : \"I\" (ARG2), \"r\" (__ARG1) ); \\\r\n __RES; \\\r\n })\r\n \r\n#define __USAT16(ARG1,ARG2) \\\r\n({ \\\r\n uint32_t __RES, __ARG1 = (ARG1); \\\r\n __ASM (\"usat16 %0, %1, %2\" : \"=r\" (__RES) : \"I\" (ARG2), \"r\" (__ARG1) ); \\\r\n __RES; \\\r\n })\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTB16(uint32_t op1)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"uxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"uxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTB16(uint32_t op1)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"sxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"sxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"smuad %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"smuadx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"smlad %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"smladx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\r\n return(result);\r\n}\r\n\r\n#define __SMLALD(ARG1,ARG2,ARG3) \\\r\n({ \\\r\n uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \\\r\n __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (__ARG3_L), \"=r\" (__ARG3_H) : \"r\" (__ARG1), \"r\" (__ARG2), \"0\" (__ARG3_L), \"1\" (__ARG3_H) ); \\\r\n (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \\\r\n })\r\n\r\n#define __SMLALDX(ARG1,ARG2,ARG3) \\\r\n({ \\\r\n uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \\\r\n __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (__ARG3_L), \"=r\" (__ARG3_H) : \"r\" (__ARG1), \"r\" (__ARG2), \"0\" (__ARG3_L), \"1\" (__ARG3_H) ); \\\r\n (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \\\r\n })\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"smusd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"smusdx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"smlsd %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"smlsdx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\r\n return(result);\r\n}\r\n\r\n#define __SMLSLD(ARG1,ARG2,ARG3) \\\r\n({ \\\r\n uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \\\r\n __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (__ARG3_L), \"=r\" (__ARG3_H) : \"r\" (__ARG1), \"r\" (__ARG2), \"0\" (__ARG3_L), \"1\" (__ARG3_H) ); \\\r\n (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \\\r\n })\r\n\r\n#define __SMLSLDX(ARG1,ARG2,ARG3) \\\r\n({ \\\r\n uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \\\r\n __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (__ARG3_L), \"=r\" (__ARG3_H) : \"r\" (__ARG1), \"r\" (__ARG2), \"0\" (__ARG3_L), \"1\" (__ARG3_H) ); \\\r\n (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \\\r\n })\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"sel %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n\r\n __ASM volatile (\"qadd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"qsub %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n return(result);\r\n}\r\n\r\n#define __PKHBT(ARG1,ARG2,ARG3) \\\r\n({ \\\r\n uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\r\n __ASM (\"pkhbt %0, %1, %2, lsl %3\" : \"=r\" (__RES) : \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3) ); \\\r\n __RES; \\\r\n })\r\n\r\n#define __PKHTB(ARG1,ARG2,ARG3) \\\r\n({ \\\r\n uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\r\n if (ARG3 == 0) \\\r\n __ASM (\"pkhtb %0, %1, %2\" : \"=r\" (__RES) : \"r\" (__ARG1), \"r\" (__ARG2) ); \\\r\n else\t\\\r\n __ASM (\"pkhtb %0, %1, %2, asr %3\" : \"=r\" (__RES) : \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3) ); \\\r\n __RES; \\\r\n })\r\n\r\n/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/\r\n\r\n\r\n\r\n#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r\n/* TASKING carm specific functions */\r\n\r\n\r\n/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/\r\n/* not yet supported */\r\n/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/\r\n\r\n\r\n#endif\r\n\r\n/*@} end of group CMSIS_SIMD_intrinsics */\r\n\r\n\r\n#endif /* __CORE_CM4_SIMD_H */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n" }, { "path": "figure-simulator-discovery/Libraries/CMSIS/Include/core_cmFunc.h", "content": "/**************************************************************************//**\r\n * @file core_cmFunc.h\r\n * @brief CMSIS Cortex-M Core Function Access Header File\r\n * @version V2.10\r\n * @date 26. July 2011\r\n *\r\n * @note\r\n * Copyright (C) 2009-2011 ARM Limited. All rights reserved.\r\n *\r\n * @par\r\n * ARM Limited (ARM) is supplying this software for use with Cortex-M \r\n * processor based microcontrollers. This file can be freely distributed \r\n * within development tools that are supporting such ARM based processors. \r\n *\r\n * @par\r\n * THIS SOFTWARE IS PROVIDED \"AS IS\". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r\n * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r\n * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r\n * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r\n * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r\n *\r\n ******************************************************************************/\r\n\r\n#ifndef __CORE_CMFUNC_H\r\n#define __CORE_CMFUNC_H\r\n\r\n\r\n/* ########################### Core Function Access ########################### */\r\n/** \\ingroup CMSIS_Core_FunctionInterface \r\n \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r\n @{\r\n */\r\n\r\n#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r\n/* ARM armcc specific functions */\r\n\r\n#if (__ARMCC_VERSION < 400677)\r\n #error \"Please use ARM Compiler Toolchain V4.0.677 or later!\"\r\n#endif\r\n\r\n/* intrinsic void __enable_irq(); */\r\n/* intrinsic void __disable_irq(); */\r\n\r\n/** \\brief Get Control Register\r\n\r\n This function returns the content of the Control Register.\r\n\r\n \\return Control Register value\r\n */\r\nstatic __INLINE uint32_t __get_CONTROL(void)\r\n{\r\n register uint32_t __regControl __ASM(\"control\");\r\n return(__regControl);\r\n}\r\n\r\n\r\n/** \\brief Set Control Register\r\n\r\n This function writes the given value to the Control Register.\r\n\r\n \\param [in] control Control Register value to set\r\n */\r\nstatic __INLINE void __set_CONTROL(uint32_t control)\r\n{\r\n register uint32_t __regControl __ASM(\"control\");\r\n __regControl = control;\r\n}\r\n\r\n\r\n/** \\brief Get ISPR Register\r\n\r\n This function returns the content of the ISPR Register.\r\n\r\n \\return ISPR Register value\r\n */\r\nstatic __INLINE uint32_t __get_IPSR(void)\r\n{\r\n register uint32_t __regIPSR __ASM(\"ipsr\");\r\n return(__regIPSR);\r\n}\r\n\r\n\r\n/** \\brief Get APSR Register\r\n\r\n This function returns the content of the APSR Register.\r\n\r\n \\return APSR Register value\r\n */\r\nstatic __INLINE uint32_t __get_APSR(void)\r\n{\r\n register uint32_t __regAPSR __ASM(\"apsr\");\r\n return(__regAPSR);\r\n}\r\n\r\n\r\n/** \\brief Get xPSR Register\r\n\r\n This function returns the content of the xPSR Register.\r\n\r\n \\return xPSR Register value\r\n */\r\nstatic __INLINE uint32_t __get_xPSR(void)\r\n{\r\n register uint32_t __regXPSR __ASM(\"xpsr\");\r\n return(__regXPSR);\r\n}\r\n\r\n\r\n/** \\brief Get Process Stack Pointer\r\n\r\n This function returns the current value of the Process Stack Pointer (PSP).\r\n\r\n \\return PSP Register value\r\n */\r\nstatic __INLINE uint32_t __get_PSP(void)\r\n{\r\n register uint32_t __regProcessStackPointer __ASM(\"psp\");\r\n return(__regProcessStackPointer);\r\n}\r\n\r\n\r\n/** \\brief Set Process Stack Pointer\r\n\r\n This function assigns the given value to the Process Stack Pointer (PSP).\r\n\r\n \\param [in] topOfProcStack Process Stack Pointer value to set\r\n */\r\nstatic __INLINE void __set_PSP(uint32_t topOfProcStack)\r\n{\r\n register uint32_t __regProcessStackPointer __ASM(\"psp\");\r\n __regProcessStackPointer = topOfProcStack;\r\n}\r\n\r\n\r\n/** \\brief Get Main Stack Pointer\r\n\r\n This function returns the current value of the Main Stack Pointer (MSP).\r\n\r\n \\return MSP Register value\r\n */\r\nstatic __INLINE uint32_t __get_MSP(void)\r\n{\r\n register uint32_t __regMainStackPointer __ASM(\"msp\");\r\n return(__regMainStackPointer);\r\n}\r\n\r\n\r\n/** \\brief Set Main Stack Pointer\r\n\r\n This function assigns the given value to the Main Stack Pointer (MSP).\r\n\r\n \\param [in] topOfMainStack Main Stack Pointer value to set\r\n */\r\nstatic __INLINE void __set_MSP(uint32_t topOfMainStack)\r\n{\r\n register uint32_t __regMainStackPointer __ASM(\"msp\");\r\n __regMainStackPointer = topOfMainStack;\r\n}\r\n\r\n\r\n/** \\brief Get Priority Mask\r\n\r\n This function returns the current state of the priority mask bit from the Priority Mask Register.\r\n\r\n \\return Priority Mask value\r\n */\r\nstatic __INLINE uint32_t __get_PRIMASK(void)\r\n{\r\n register uint32_t __regPriMask __ASM(\"primask\");\r\n return(__regPriMask);\r\n}\r\n\r\n\r\n/** \\brief Set Priority Mask\r\n\r\n This function assigns the given value to the Priority Mask Register.\r\n\r\n \\param [in] priMask Priority Mask\r\n */\r\nstatic __INLINE void __set_PRIMASK(uint32_t priMask)\r\n{\r\n register uint32_t __regPriMask __ASM(\"primask\");\r\n __regPriMask = (priMask);\r\n}\r\n \r\n\r\n#if (__CORTEX_M >= 0x03)\r\n\r\n/** \\brief Enable FIQ\r\n\r\n This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r\n Can only be executed in Privileged modes.\r\n */\r\n#define __enable_fault_irq __enable_fiq\r\n\r\n\r\n/** \\brief Disable FIQ\r\n\r\n This function disables FIQ interrupts by setting the F-bit in the CPSR.\r\n Can only be executed in Privileged modes.\r\n */\r\n#define __disable_fault_irq __disable_fiq\r\n\r\n\r\n/** \\brief Get Base Priority\r\n\r\n This function returns the current value of the Base Priority register.\r\n\r\n \\return Base Priority register value\r\n */\r\nstatic __INLINE uint32_t __get_BASEPRI(void)\r\n{\r\n register uint32_t __regBasePri __ASM(\"basepri\");\r\n return(__regBasePri);\r\n}\r\n\r\n\r\n/** \\brief Set Base Priority\r\n\r\n This function assigns the given value to the Base Priority register.\r\n\r\n \\param [in] basePri Base Priority value to set\r\n */\r\nstatic __INLINE void __set_BASEPRI(uint32_t basePri)\r\n{\r\n register uint32_t __regBasePri __ASM(\"basepri\");\r\n __regBasePri = (basePri & 0xff);\r\n}\r\n \r\n\r\n/** \\brief Get Fault Mask\r\n\r\n This function returns the current value of the Fault Mask register.\r\n\r\n \\return Fault Mask register value\r\n */\r\nstatic __INLINE uint32_t __get_FAULTMASK(void)\r\n{\r\n register uint32_t __regFaultMask __ASM(\"faultmask\");\r\n return(__regFaultMask);\r\n}\r\n\r\n\r\n/** \\brief Set Fault Mask\r\n\r\n This function assigns the given value to the Fault Mask register.\r\n\r\n \\param [in] faultMask Fault Mask value to set\r\n */\r\nstatic __INLINE void __set_FAULTMASK(uint32_t faultMask)\r\n{\r\n register uint32_t __regFaultMask __ASM(\"faultmask\");\r\n __regFaultMask = (faultMask & (uint32_t)1);\r\n}\r\n\r\n#endif /* (__CORTEX_M >= 0x03) */\r\n\r\n\r\n#if (__CORTEX_M == 0x04)\r\n\r\n/** \\brief Get FPSCR\r\n\r\n This function returns the current value of the Floating Point Status/Control register.\r\n\r\n \\return Floating Point Status/Control register value\r\n */\r\nstatic __INLINE uint32_t __get_FPSCR(void)\r\n{\r\n#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r\n register uint32_t __regfpscr __ASM(\"fpscr\");\r\n return(__regfpscr);\r\n#else\r\n return(0);\r\n#endif\r\n}\r\n\r\n\r\n/** \\brief Set FPSCR\r\n\r\n This function assigns the given value to the Floating Point Status/Control register.\r\n\r\n \\param [in] fpscr Floating Point Status/Control value to set\r\n */\r\nstatic __INLINE void __set_FPSCR(uint32_t fpscr)\r\n{\r\n#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r\n register uint32_t __regfpscr __ASM(\"fpscr\");\r\n __regfpscr = (fpscr);\r\n#endif\r\n}\r\n\r\n#endif /* (__CORTEX_M == 0x04) */\r\n\r\n\r\n#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r\n/* IAR iccarm specific functions */\r\n\r\n#include \r\n\r\n#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r\n/* GNU gcc specific functions */\r\n\r\n/** \\brief Enable IRQ Interrupts\r\n\r\n This function enables IRQ interrupts by clearing the I-bit in the CPSR.\r\n Can only be executed in Privileged modes.\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)\r\n{\r\n __ASM volatile (\"cpsie i\");\r\n}\r\n\r\n\r\n/** \\brief Disable IRQ Interrupts\r\n\r\n This function disables IRQ interrupts by setting the I-bit in the CPSR.\r\n Can only be executed in Privileged modes.\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)\r\n{\r\n __ASM volatile (\"cpsid i\");\r\n}\r\n\r\n\r\n/** \\brief Get Control Register\r\n\r\n This function returns the content of the Control Register.\r\n\r\n \\return Control Register value\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)\r\n{\r\n uint32_t result;\r\n\r\n __ASM volatile (\"MRS %0, control\" : \"=r\" (result) );\r\n return(result);\r\n}\r\n\r\n\r\n/** \\brief Set Control Register\r\n\r\n This function writes the given value to the Control Register.\r\n\r\n \\param [in] control Control Register value to set\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)\r\n{\r\n __ASM volatile (\"MSR control, %0\" : : \"r\" (control) );\r\n}\r\n\r\n\r\n/** \\brief Get ISPR Register\r\n\r\n This function returns the content of the ISPR Register.\r\n\r\n \\return ISPR Register value\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)\r\n{\r\n uint32_t result;\r\n\r\n __ASM volatile (\"MRS %0, ipsr\" : \"=r\" (result) );\r\n return(result);\r\n}\r\n\r\n\r\n/** \\brief Get APSR Register\r\n\r\n This function returns the content of the APSR Register.\r\n\r\n \\return APSR Register value\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)\r\n{\r\n uint32_t result;\r\n\r\n __ASM volatile (\"MRS %0, apsr\" : \"=r\" (result) );\r\n return(result);\r\n}\r\n\r\n\r\n/** \\brief Get xPSR Register\r\n\r\n This function returns the content of the xPSR Register.\r\n\r\n \\return xPSR Register value\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)\r\n{\r\n uint32_t result;\r\n\r\n __ASM volatile (\"MRS %0, xpsr\" : \"=r\" (result) );\r\n return(result);\r\n}\r\n\r\n\r\n/** \\brief Get Process Stack Pointer\r\n\r\n This function returns the current value of the Process Stack Pointer (PSP).\r\n\r\n \\return PSP Register value\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)\r\n{\r\n register uint32_t result;\r\n\r\n __ASM volatile (\"MRS %0, psp\\n\" : \"=r\" (result) );\r\n return(result);\r\n}\r\n \r\n\r\n/** \\brief Set Process Stack Pointer\r\n\r\n This function assigns the given value to the Process Stack Pointer (PSP).\r\n\r\n \\param [in] topOfProcStack Process Stack Pointer value to set\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)\r\n{\r\n __ASM volatile (\"MSR psp, %0\\n\" : : \"r\" (topOfProcStack) );\r\n}\r\n\r\n\r\n/** \\brief Get Main Stack Pointer\r\n\r\n This function returns the current value of the Main Stack Pointer (MSP).\r\n\r\n \\return MSP Register value\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)\r\n{\r\n register uint32_t result;\r\n\r\n __ASM volatile (\"MRS %0, msp\\n\" : \"=r\" (result) );\r\n return(result);\r\n}\r\n \r\n\r\n/** \\brief Set Main Stack Pointer\r\n\r\n This function assigns the given value to the Main Stack Pointer (MSP).\r\n\r\n \\param [in] topOfMainStack Main Stack Pointer value to set\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)\r\n{\r\n __ASM volatile (\"MSR msp, %0\\n\" : : \"r\" (topOfMainStack) );\r\n}\r\n\r\n\r\n/** \\brief Get Priority Mask\r\n\r\n This function returns the current state of the priority mask bit from the Priority Mask Register.\r\n\r\n \\return Priority Mask value\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)\r\n{\r\n uint32_t result;\r\n\r\n __ASM volatile (\"MRS %0, primask\" : \"=r\" (result) );\r\n return(result);\r\n}\r\n\r\n\r\n/** \\brief Set Priority Mask\r\n\r\n This function assigns the given value to the Priority Mask Register.\r\n\r\n \\param [in] priMask Priority Mask\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)\r\n{\r\n __ASM volatile (\"MSR primask, %0\" : : \"r\" (priMask) );\r\n}\r\n \r\n\r\n#if (__CORTEX_M >= 0x03)\r\n\r\n/** \\brief Enable FIQ\r\n\r\n This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r\n Can only be executed in Privileged modes.\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)\r\n{\r\n __ASM volatile (\"cpsie f\");\r\n}\r\n\r\n\r\n/** \\brief Disable FIQ\r\n\r\n This function disables FIQ interrupts by setting the F-bit in the CPSR.\r\n Can only be executed in Privileged modes.\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)\r\n{\r\n __ASM volatile (\"cpsid f\");\r\n}\r\n\r\n\r\n/** \\brief Get Base Priority\r\n\r\n This function returns the current value of the Base Priority register.\r\n\r\n \\return Base Priority register value\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"MRS %0, basepri_max\" : \"=r\" (result) );\r\n return(result);\r\n}\r\n\r\n\r\n/** \\brief Set Base Priority\r\n\r\n This function assigns the given value to the Base Priority register.\r\n\r\n \\param [in] basePri Base Priority value to set\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)\r\n{\r\n __ASM volatile (\"MSR basepri, %0\" : : \"r\" (value) );\r\n}\r\n\r\n\r\n/** \\brief Get Fault Mask\r\n\r\n This function returns the current value of the Fault Mask register.\r\n\r\n \\return Fault Mask register value\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"MRS %0, faultmask\" : \"=r\" (result) );\r\n return(result);\r\n}\r\n\r\n\r\n/** \\brief Set Fault Mask\r\n\r\n This function assigns the given value to the Fault Mask register.\r\n\r\n \\param [in] faultMask Fault Mask value to set\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r\n{\r\n __ASM volatile (\"MSR faultmask, %0\" : : \"r\" (faultMask) );\r\n}\r\n\r\n#endif /* (__CORTEX_M >= 0x03) */\r\n\r\n\r\n#if (__CORTEX_M == 0x04)\r\n\r\n/** \\brief Get FPSCR\r\n\r\n This function returns the current value of the Floating Point Status/Control register.\r\n\r\n \\return Floating Point Status/Control register value\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)\r\n{\r\n#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r\n uint32_t result;\r\n\r\n __ASM volatile (\"VMRS %0, fpscr\" : \"=r\" (result) );\r\n return(result);\r\n#else\r\n return(0);\r\n#endif\r\n}\r\n\r\n\r\n/** \\brief Set FPSCR\r\n\r\n This function assigns the given value to the Floating Point Status/Control register.\r\n\r\n \\param [in] fpscr Floating Point Status/Control value to set\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)\r\n{\r\n#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r\n __ASM volatile (\"VMSR fpscr, %0\" : : \"r\" (fpscr) );\r\n#endif\r\n}\r\n\r\n#endif /* (__CORTEX_M == 0x04) */\r\n\r\n\r\n#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r\n/* TASKING carm specific functions */\r\n\r\n/*\r\n * The CMSIS functions have been implemented as intrinsics in the compiler.\r\n * Please use \"carm -?i\" to get an up to date list of all instrinsics,\r\n * Including the CMSIS ones.\r\n */\r\n\r\n#endif\r\n\r\n/*@} end of CMSIS_Core_RegAccFunctions */\r\n\r\n\r\n#endif /* __CORE_CMFUNC_H */\r\n" }, { "path": "figure-simulator-discovery/Libraries/CMSIS/Include/core_cmInstr.h", "content": "/**************************************************************************//**\r\n * @file core_cmInstr.h\r\n * @brief CMSIS Cortex-M Core Instruction Access Header File\r\n * @version V2.10\r\n * @date 19. July 2011\r\n *\r\n * @note\r\n * Copyright (C) 2009-2011 ARM Limited. All rights reserved.\r\n *\r\n * @par\r\n * ARM Limited (ARM) is supplying this software for use with Cortex-M \r\n * processor based microcontrollers. This file can be freely distributed \r\n * within development tools that are supporting such ARM based processors. \r\n *\r\n * @par\r\n * THIS SOFTWARE IS PROVIDED \"AS IS\". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r\n * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r\n * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r\n * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r\n * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r\n *\r\n ******************************************************************************/\r\n\r\n#ifndef __CORE_CMINSTR_H\r\n#define __CORE_CMINSTR_H\r\n\r\n\r\n/* ########################## Core Instruction Access ######################### */\r\n/** \\defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r\n Access to dedicated instructions\r\n @{\r\n*/\r\n\r\n#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r\n/* ARM armcc specific functions */\r\n\r\n#if (__ARMCC_VERSION < 400677)\r\n #error \"Please use ARM Compiler Toolchain V4.0.677 or later!\"\r\n#endif\r\n\r\n\r\n/** \\brief No Operation\r\n\r\n No Operation does nothing. This instruction can be used for code alignment purposes.\r\n */\r\n#define __NOP __nop\r\n\r\n\r\n/** \\brief Wait For Interrupt\r\n\r\n Wait For Interrupt is a hint instruction that suspends execution\r\n until one of a number of events occurs.\r\n */\r\n#define __WFI __wfi\r\n\r\n\r\n/** \\brief Wait For Event\r\n\r\n Wait For Event is a hint instruction that permits the processor to enter\r\n a low-power state until one of a number of events occurs.\r\n */\r\n#define __WFE __wfe\r\n\r\n\r\n/** \\brief Send Event\r\n\r\n Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r\n */\r\n#define __SEV __sev\r\n\r\n\r\n/** \\brief Instruction Synchronization Barrier\r\n\r\n Instruction Synchronization Barrier flushes the pipeline in the processor, \r\n so that all instructions following the ISB are fetched from cache or \r\n memory, after the instruction has been completed.\r\n */\r\n#define __ISB() __isb(0xF)\r\n\r\n\r\n/** \\brief Data Synchronization Barrier\r\n\r\n This function acts as a special kind of Data Memory Barrier. \r\n It completes when all explicit memory accesses before this instruction complete.\r\n */\r\n#define __DSB() __dsb(0xF)\r\n\r\n\r\n/** \\brief Data Memory Barrier\r\n\r\n This function ensures the apparent order of the explicit memory operations before \r\n and after the instruction, without ensuring their completion.\r\n */\r\n#define __DMB() __dmb(0xF)\r\n\r\n\r\n/** \\brief Reverse byte order (32 bit)\r\n\r\n This function reverses the byte order in integer value.\r\n\r\n \\param [in] value Value to reverse\r\n \\return Reversed value\r\n */\r\n#define __REV __rev\r\n\r\n\r\n/** \\brief Reverse byte order (16 bit)\r\n\r\n This function reverses the byte order in two unsigned short values.\r\n\r\n \\param [in] value Value to reverse\r\n \\return Reversed value\r\n */\r\nstatic __INLINE __ASM uint32_t __REV16(uint32_t value)\r\n{\r\n rev16 r0, r0\r\n bx lr\r\n}\r\n\r\n\r\n/** \\brief Reverse byte order in signed short value\r\n\r\n This function reverses the byte order in a signed short value with sign extension to integer.\r\n\r\n \\param [in] value Value to reverse\r\n \\return Reversed value\r\n */\r\nstatic __INLINE __ASM int32_t __REVSH(int32_t value)\r\n{\r\n revsh r0, r0\r\n bx lr\r\n}\r\n\r\n\r\n#if (__CORTEX_M >= 0x03)\r\n\r\n/** \\brief Reverse bit order of value\r\n\r\n This function reverses the bit order of the given value.\r\n\r\n \\param [in] value Value to reverse\r\n \\return Reversed value\r\n */\r\n#define __RBIT __rbit\r\n\r\n\r\n/** \\brief LDR Exclusive (8 bit)\r\n\r\n This function performs a exclusive LDR command for 8 bit value.\r\n\r\n \\param [in] ptr Pointer to data\r\n \\return value of type uint8_t at (*ptr)\r\n */\r\n#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))\r\n\r\n\r\n/** \\brief LDR Exclusive (16 bit)\r\n\r\n This function performs a exclusive LDR command for 16 bit values.\r\n\r\n \\param [in] ptr Pointer to data\r\n \\return value of type uint16_t at (*ptr)\r\n */\r\n#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))\r\n\r\n\r\n/** \\brief LDR Exclusive (32 bit)\r\n\r\n This function performs a exclusive LDR command for 32 bit values.\r\n\r\n \\param [in] ptr Pointer to data\r\n \\return value of type uint32_t at (*ptr)\r\n */\r\n#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))\r\n\r\n\r\n/** \\brief STR Exclusive (8 bit)\r\n\r\n This function performs a exclusive STR command for 8 bit values.\r\n\r\n \\param [in] value Value to store\r\n \\param [in] ptr Pointer to location\r\n \\return 0 Function succeeded\r\n \\return 1 Function failed\r\n */\r\n#define __STREXB(value, ptr) __strex(value, ptr)\r\n\r\n\r\n/** \\brief STR Exclusive (16 bit)\r\n\r\n This function performs a exclusive STR command for 16 bit values.\r\n\r\n \\param [in] value Value to store\r\n \\param [in] ptr Pointer to location\r\n \\return 0 Function succeeded\r\n \\return 1 Function failed\r\n */\r\n#define __STREXH(value, ptr) __strex(value, ptr)\r\n\r\n\r\n/** \\brief STR Exclusive (32 bit)\r\n\r\n This function performs a exclusive STR command for 32 bit values.\r\n\r\n \\param [in] value Value to store\r\n \\param [in] ptr Pointer to location\r\n \\return 0 Function succeeded\r\n \\return 1 Function failed\r\n */\r\n#define __STREXW(value, ptr) __strex(value, ptr)\r\n\r\n\r\n/** \\brief Remove the exclusive lock\r\n\r\n This function removes the exclusive lock which is created by LDREX.\r\n\r\n */\r\n#define __CLREX __clrex\r\n\r\n\r\n/** \\brief Signed Saturate\r\n\r\n This function saturates a signed value.\r\n\r\n \\param [in] value Value to be saturated\r\n \\param [in] sat Bit position to saturate to (1..32)\r\n \\return Saturated value\r\n */\r\n#define __SSAT __ssat\r\n\r\n\r\n/** \\brief Unsigned Saturate\r\n\r\n This function saturates an unsigned value.\r\n\r\n \\param [in] value Value to be saturated\r\n \\param [in] sat Bit position to saturate to (0..31)\r\n \\return Saturated value\r\n */\r\n#define __USAT __usat\r\n\r\n\r\n/** \\brief Count leading zeros\r\n\r\n This function counts the number of leading zeros of a data value.\r\n\r\n \\param [in] value Value to count the leading zeros\r\n \\return number of leading zeros in value\r\n */\r\n#define __CLZ __clz \r\n\r\n#endif /* (__CORTEX_M >= 0x03) */\r\n\r\n\r\n\r\n#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r\n/* IAR iccarm specific functions */\r\n\r\n#include \r\n\r\n\r\n#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r\n/* GNU gcc specific functions */\r\n\r\n/** \\brief No Operation\r\n\r\n No Operation does nothing. This instruction can be used for code alignment purposes.\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)\r\n{\r\n __ASM volatile (\"nop\");\r\n}\r\n\r\n\r\n/** \\brief Wait For Interrupt\r\n\r\n Wait For Interrupt is a hint instruction that suspends execution\r\n until one of a number of events occurs.\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)\r\n{\r\n __ASM volatile (\"wfi\");\r\n}\r\n\r\n\r\n/** \\brief Wait For Event\r\n\r\n Wait For Event is a hint instruction that permits the processor to enter\r\n a low-power state until one of a number of events occurs.\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)\r\n{\r\n __ASM volatile (\"wfe\");\r\n}\r\n\r\n\r\n/** \\brief Send Event\r\n\r\n Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)\r\n{\r\n __ASM volatile (\"sev\");\r\n}\r\n\r\n\r\n/** \\brief Instruction Synchronization Barrier\r\n\r\n Instruction Synchronization Barrier flushes the pipeline in the processor, \r\n so that all instructions following the ISB are fetched from cache or \r\n memory, after the instruction has been completed.\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)\r\n{\r\n __ASM volatile (\"isb\");\r\n}\r\n\r\n\r\n/** \\brief Data Synchronization Barrier\r\n\r\n This function acts as a special kind of Data Memory Barrier. \r\n It completes when all explicit memory accesses before this instruction complete.\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)\r\n{\r\n __ASM volatile (\"dsb\");\r\n}\r\n\r\n\r\n/** \\brief Data Memory Barrier\r\n\r\n This function ensures the apparent order of the explicit memory operations before \r\n and after the instruction, without ensuring their completion.\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)\r\n{\r\n __ASM volatile (\"dmb\");\r\n}\r\n\r\n\r\n/** \\brief Reverse byte order (32 bit)\r\n\r\n This function reverses the byte order in integer value.\r\n\r\n \\param [in] value Value to reverse\r\n \\return Reversed value\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"rev %0, %1\" : \"=r\" (result) : \"r\" (value) );\r\n return(result);\r\n}\r\n\r\n\r\n/** \\brief Reverse byte order (16 bit)\r\n\r\n This function reverses the byte order in two unsigned short values.\r\n\r\n \\param [in] value Value to reverse\r\n \\return Reversed value\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"rev16 %0, %1\" : \"=r\" (result) : \"r\" (value) );\r\n return(result);\r\n}\r\n\r\n\r\n/** \\brief Reverse byte order in signed short value\r\n\r\n This function reverses the byte order in a signed short value with sign extension to integer.\r\n\r\n \\param [in] value Value to reverse\r\n \\return Reversed value\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"revsh %0, %1\" : \"=r\" (result) : \"r\" (value) );\r\n return(result);\r\n}\r\n\r\n\r\n#if (__CORTEX_M >= 0x03)\r\n\r\n/** \\brief Reverse bit order of value\r\n\r\n This function reverses the bit order of the given value.\r\n\r\n \\param [in] value Value to reverse\r\n \\return Reversed value\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"rbit %0, %1\" : \"=r\" (result) : \"r\" (value) );\r\n return(result);\r\n}\r\n\r\n\r\n/** \\brief LDR Exclusive (8 bit)\r\n\r\n This function performs a exclusive LDR command for 8 bit value.\r\n\r\n \\param [in] ptr Pointer to data\r\n \\return value of type uint8_t at (*ptr)\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r\n{\r\n uint8_t result;\r\n \r\n __ASM volatile (\"ldrexb %0, [%1]\" : \"=r\" (result) : \"r\" (addr) );\r\n return(result);\r\n}\r\n\r\n\r\n/** \\brief LDR Exclusive (16 bit)\r\n\r\n This function performs a exclusive LDR command for 16 bit values.\r\n\r\n \\param [in] ptr Pointer to data\r\n \\return value of type uint16_t at (*ptr)\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r\n{\r\n uint16_t result;\r\n \r\n __ASM volatile (\"ldrexh %0, [%1]\" : \"=r\" (result) : \"r\" (addr) );\r\n return(result);\r\n}\r\n\r\n\r\n/** \\brief LDR Exclusive (32 bit)\r\n\r\n This function performs a exclusive LDR command for 32 bit values.\r\n\r\n \\param [in] ptr Pointer to data\r\n \\return value of type uint32_t at (*ptr)\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"ldrex %0, [%1]\" : \"=r\" (result) : \"r\" (addr) );\r\n return(result);\r\n}\r\n\r\n\r\n/** \\brief STR Exclusive (8 bit)\r\n\r\n This function performs a exclusive STR command for 8 bit values.\r\n\r\n \\param [in] value Value to store\r\n \\param [in] ptr Pointer to location\r\n \\return 0 Function succeeded\r\n \\return 1 Function failed\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"strexb %0, %2, [%1]\" : \"=r\" (result) : \"r\" (addr), \"r\" (value) );\r\n return(result);\r\n}\r\n\r\n\r\n/** \\brief STR Exclusive (16 bit)\r\n\r\n This function performs a exclusive STR command for 16 bit values.\r\n\r\n \\param [in] value Value to store\r\n \\param [in] ptr Pointer to location\r\n \\return 0 Function succeeded\r\n \\return 1 Function failed\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"strexh %0, %2, [%1]\" : \"=r\" (result) : \"r\" (addr), \"r\" (value) );\r\n return(result);\r\n}\r\n\r\n\r\n/** \\brief STR Exclusive (32 bit)\r\n\r\n This function performs a exclusive STR command for 32 bit values.\r\n\r\n \\param [in] value Value to store\r\n \\param [in] ptr Pointer to location\r\n \\return 0 Function succeeded\r\n \\return 1 Function failed\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r\n{\r\n uint32_t result;\r\n \r\n __ASM volatile (\"strex %0, %2, [%1]\" : \"=r\" (result) : \"r\" (addr), \"r\" (value) );\r\n return(result);\r\n}\r\n\r\n\r\n/** \\brief Remove the exclusive lock\r\n\r\n This function removes the exclusive lock which is created by LDREX.\r\n\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)\r\n{\r\n __ASM volatile (\"clrex\");\r\n}\r\n\r\n\r\n/** \\brief Signed Saturate\r\n\r\n This function saturates a signed value.\r\n\r\n \\param [in] value Value to be saturated\r\n \\param [in] sat Bit position to saturate to (1..32)\r\n \\return Saturated value\r\n */\r\n#define __SSAT(ARG1,ARG2) \\\r\n({ \\\r\n uint32_t __RES, __ARG1 = (ARG1); \\\r\n __ASM (\"ssat %0, %1, %2\" : \"=r\" (__RES) : \"I\" (ARG2), \"r\" (__ARG1) ); \\\r\n __RES; \\\r\n })\r\n\r\n\r\n/** \\brief Unsigned Saturate\r\n\r\n This function saturates an unsigned value.\r\n\r\n \\param [in] value Value to be saturated\r\n \\param [in] sat Bit position to saturate to (0..31)\r\n \\return Saturated value\r\n */\r\n#define __USAT(ARG1,ARG2) \\\r\n({ \\\r\n uint32_t __RES, __ARG1 = (ARG1); \\\r\n __ASM (\"usat %0, %1, %2\" : \"=r\" (__RES) : \"I\" (ARG2), \"r\" (__ARG1) ); \\\r\n __RES; \\\r\n })\r\n\r\n\r\n/** \\brief Count leading zeros\r\n\r\n This function counts the number of leading zeros of a data value.\r\n\r\n \\param [in] value Value to count the leading zeros\r\n \\return number of leading zeros in value\r\n */\r\n__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)\r\n{\r\n uint8_t result;\r\n \r\n __ASM volatile (\"clz %0, %1\" : \"=r\" (result) : \"r\" (value) );\r\n return(result);\r\n}\r\n\r\n#endif /* (__CORTEX_M >= 0x03) */\r\n\r\n\r\n\r\n\r\n#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r\n/* TASKING carm specific functions */\r\n\r\n/*\r\n * The CMSIS functions have been implemented as intrinsics in the compiler.\r\n * Please use \"carm -?i\" to get an up to date list of all intrinsics,\r\n * Including the CMSIS ones.\r\n */\r\n\r\n#endif\r\n\r\n/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r\n\r\n#endif /* __CORE_CMINSTR_H */\r\n" }, { "path": "figure-simulator-discovery/Libraries/Device/STM32F4xx/Include/stm32f4xx.h", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx.h\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File. \r\n * This file contains all the peripheral register's definitions, bits \r\n * definitions and memory mapping for STM32F4xx devices.\r\n * \r\n * The file is the unique include file that the application programmer\r\n * is using in the C source code, usually in main.c. This file contains:\r\n * - Configuration section that allows to select:\r\n * - The device used in the target application\r\n * - To use or not the peripherals drivers in application code(i.e. \r\n * code will be based on direct access to peripherals registers \r\n * rather than drivers API), this option is controlled by \r\n * \"#define USE_STDPERIPH_DRIVER\"\r\n * - To change few application-specific parameters such as the HSE \r\n * crystal frequency\r\n * - Data structures and the address mapping for all peripherals\r\n * - Peripheral's registers declarations and bits definition\r\n * - Macros to access peripherals registers hardware\r\n * \r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/** @addtogroup CMSIS\r\n * @{\r\n */\r\n\r\n/** @addtogroup stm32f4xx\r\n * @{\r\n */\r\n \r\n#ifndef __STM32F4xx_H\r\n#define __STM32F4xx_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif /* __cplusplus */\r\n \r\n/** @addtogroup Library_configuration_section\r\n * @{\r\n */\r\n \r\n/* Uncomment the line below according to the target STM32 device used in your\r\n application \r\n */\r\n\r\n#if !defined (STM32F4XX) \r\n #define STM32F4XX\r\n#endif\r\n\r\n/* Tip: To avoid modifying this file each time you need to switch between these\r\n devices, you can define the device in your toolchain compiler preprocessor.\r\n */\r\n\r\n#if !defined (STM32F4XX)\r\n #error \"Please select first the target STM32F4XX device used in your application (in stm32f4xx.h file)\"\r\n#endif\r\n\r\n#if !defined (USE_STDPERIPH_DRIVER)\r\n/**\r\n * @brief Comment the line below if you will not use the peripherals drivers.\r\n In this case, these drivers will not be included and the application code will \r\n be based on direct access to peripherals registers \r\n */\r\n /*#define USE_STDPERIPH_DRIVER*/\r\n#endif /* USE_STDPERIPH_DRIVER */\r\n\r\n/**\r\n * @brief In the following line adjust the value of External High Speed oscillator (HSE)\r\n used in your application \r\n \r\n Tip: To avoid modifying this file each time you need to use different HSE, you\r\n can define the HSE value in your toolchain compiler preprocessor.\r\n */ \r\n\r\n#if !defined (HSE_VALUE) \r\n #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */\r\n#endif /* HSE_VALUE */\r\n\r\n/**\r\n * @brief In the following line adjust the External High Speed oscillator (HSE) Startup \r\n Timeout value \r\n */\r\n#if !defined (HSE_STARTUP_TIMEOUT) \r\n #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */\r\n#endif /* HSE_STARTUP_TIMEOUT */ \r\n\r\n#if !defined (HSI_VALUE) \r\n #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/\r\n#endif /* HSI_VALUE */ \r\n\r\n/**\r\n * @brief STM32F4XX Standard Peripherals Library version number V1.0.2\r\n */\r\n#define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ \r\n#define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */\r\n#define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */\r\n#define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ \r\n#define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\\\r\n |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\\\r\n |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\\\r\n |(__STM32F4XX_STDPERIPH_VERSION_RC))\r\n \r\n/**\r\n * @}\r\n */\r\n\r\n/** @addtogroup Configuration_section_for_CMSIS\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Configuration of the Cortex-M4 Processor and Core Peripherals \r\n */\r\n#define __CM4_REV 0x0001 /*!< Core revision r0p1 */\r\n#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */\r\n#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */\r\n#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r\n#define __FPU_PRESENT 1 /*!< FPU present */\r\n\r\n/**\r\n * @brief STM32F4XX Interrupt Number Definition, according to the selected device \r\n * in @ref Library_configuration_section \r\n */\r\ntypedef enum IRQn\r\n{\r\n/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/\r\n NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */\r\n MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */\r\n BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */\r\n UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */\r\n SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */\r\n DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */\r\n PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */\r\n SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */\r\n/****** STM32 specific Interrupt Numbers **********************************************************************/\r\n WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */\r\n PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */\r\n TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */\r\n RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */\r\n FLASH_IRQn = 4, /*!< FLASH global Interrupt */\r\n RCC_IRQn = 5, /*!< RCC global Interrupt */\r\n EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */\r\n EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */\r\n EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */\r\n EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */\r\n EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */\r\n DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */\r\n DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */\r\n DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */\r\n DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */\r\n DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */\r\n DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */\r\n DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */\r\n ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */\r\n CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */\r\n CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */\r\n CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r\n CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */\r\n EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r\n TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */\r\n TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */\r\n TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */\r\n TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r\n TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r\n TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r\n TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r\n I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r\n I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r\n I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r\n I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ \r\n SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r\n SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r\n USART1_IRQn = 37, /*!< USART1 global Interrupt */\r\n USART2_IRQn = 38, /*!< USART2 global Interrupt */\r\n USART3_IRQn = 39, /*!< USART3 global Interrupt */\r\n EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r\n RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */\r\n OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ \r\n TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */\r\n TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */\r\n TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */\r\n TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */\r\n DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */\r\n FSMC_IRQn = 48, /*!< FSMC global Interrupt */\r\n SDIO_IRQn = 49, /*!< SDIO global Interrupt */\r\n TIM5_IRQn = 50, /*!< TIM5 global Interrupt */\r\n SPI3_IRQn = 51, /*!< SPI3 global Interrupt */\r\n UART4_IRQn = 52, /*!< UART4 global Interrupt */\r\n UART5_IRQn = 53, /*!< UART5 global Interrupt */\r\n TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */\r\n TIM7_IRQn = 55, /*!< TIM7 global interrupt */\r\n DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */\r\n DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */\r\n DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */\r\n DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */\r\n DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */\r\n ETH_IRQn = 61, /*!< Ethernet global Interrupt */\r\n ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */\r\n CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */\r\n CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */\r\n CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */\r\n CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */\r\n OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */\r\n DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */\r\n DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */\r\n DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */\r\n USART6_IRQn = 71, /*!< USART6 global interrupt */ \r\n I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */\r\n I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */\r\n OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */\r\n OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */\r\n OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */\r\n OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */\r\n DCMI_IRQn = 78, /*!< DCMI global interrupt */\r\n CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */\r\n HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */\r\n FPU_IRQn = 81 /*!< FPU global interrupt */\r\n} IRQn_Type;\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n#include \"core_cm4.h\" /* Cortex-M4 processor and core peripherals */\r\n#include \"system_stm32f4xx.h\"\r\n#include \r\n\r\n/** @addtogroup Exported_types\r\n * @{\r\n */ \r\n/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */\r\ntypedef int32_t s32;\r\ntypedef int16_t s16;\r\ntypedef int8_t s8;\r\n\r\ntypedef const int32_t sc32; /*!< Read Only */\r\ntypedef const int16_t sc16; /*!< Read Only */\r\ntypedef const int8_t sc8; /*!< Read Only */\r\n\r\ntypedef __IO int32_t vs32;\r\ntypedef __IO int16_t vs16;\r\ntypedef __IO int8_t vs8;\r\n\r\ntypedef __I int32_t vsc32; /*!< Read Only */\r\ntypedef __I int16_t vsc16; /*!< Read Only */\r\ntypedef __I int8_t vsc8; /*!< Read Only */\r\n\r\ntypedef uint32_t u32;\r\ntypedef uint16_t u16;\r\ntypedef uint8_t u8;\r\n\r\ntypedef const uint32_t uc32; /*!< Read Only */\r\ntypedef const uint16_t uc16; /*!< Read Only */\r\ntypedef const uint8_t uc8; /*!< Read Only */\r\n\r\ntypedef __IO uint32_t vu32;\r\ntypedef __IO uint16_t vu16;\r\ntypedef __IO uint8_t vu8;\r\n\r\ntypedef __I uint32_t vuc32; /*!< Read Only */\r\ntypedef __I uint16_t vuc16; /*!< Read Only */\r\ntypedef __I uint8_t vuc8; /*!< Read Only */\r\n\r\ntypedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;\r\n\r\ntypedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;\r\n#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\r\n\r\ntypedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @addtogroup Peripheral_registers_structures\r\n * @{\r\n */ \r\n\r\n/** \r\n * @brief Analog to Digital Converter \r\n */\r\n\r\ntypedef struct\r\n{\r\n __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */\r\n __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ \r\n __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */\r\n __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */\r\n __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */\r\n __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */\r\n __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */\r\n __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */\r\n __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */\r\n __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */\r\n __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */\r\n __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */\r\n __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */\r\n __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */\r\n __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/\r\n __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */\r\n __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */\r\n __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */\r\n __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */\r\n __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */\r\n} ADC_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */\r\n __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */\r\n __IO uint32_t CDR; /*!< ADC common regular data register for dual\r\n AND triple modes, Address offset: ADC1 base address + 0x308 */\r\n} ADC_Common_TypeDef;\r\n\r\n\r\n/** \r\n * @brief Controller Area Network TxMailBox \r\n */\r\n\r\ntypedef struct\r\n{\r\n __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */\r\n __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */\r\n __IO uint32_t TDLR; /*!< CAN mailbox data low register */\r\n __IO uint32_t TDHR; /*!< CAN mailbox data high register */\r\n} CAN_TxMailBox_TypeDef;\r\n\r\n/** \r\n * @brief Controller Area Network FIFOMailBox \r\n */\r\n \r\ntypedef struct\r\n{\r\n __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */\r\n __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */\r\n __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */\r\n __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */\r\n} CAN_FIFOMailBox_TypeDef;\r\n\r\n/** \r\n * @brief Controller Area Network FilterRegister \r\n */\r\n \r\ntypedef struct\r\n{\r\n __IO uint32_t FR1; /*!< CAN Filter bank register 1 */\r\n __IO uint32_t FR2; /*!< CAN Filter bank register 1 */\r\n} CAN_FilterRegister_TypeDef;\r\n\r\n/** \r\n * @brief Controller Area Network \r\n */\r\n \r\ntypedef struct\r\n{\r\n __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */\r\n __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */\r\n __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */\r\n __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */\r\n __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */\r\n __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */\r\n __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */\r\n __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */\r\n uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */\r\n CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */\r\n CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */\r\n uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */\r\n __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */\r\n __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */\r\n uint32_t RESERVED2; /*!< Reserved, 0x208 */\r\n __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */\r\n uint32_t RESERVED3; /*!< Reserved, 0x210 */\r\n __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */\r\n uint32_t RESERVED4; /*!< Reserved, 0x218 */\r\n __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */\r\n uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ \r\n CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */\r\n} CAN_TypeDef;\r\n\r\n/** \r\n * @brief CRC calculation unit \r\n */\r\n\r\ntypedef struct\r\n{\r\n __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */\r\n __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */\r\n uint8_t RESERVED0; /*!< Reserved, 0x05 */\r\n uint16_t RESERVED1; /*!< Reserved, 0x06 */\r\n __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */\r\n} CRC_TypeDef;\r\n\r\n/** \r\n * @brief Digital to Analog Converter\r\n */\r\n\r\ntypedef struct\r\n{\r\n __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */\r\n __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */\r\n __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\r\n __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */\r\n __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */\r\n __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\r\n __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */\r\n __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */\r\n __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */\r\n __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */\r\n __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */\r\n __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */\r\n __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */\r\n __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */\r\n} DAC_TypeDef;\r\n\r\n/** \r\n * @brief Debug MCU\r\n */\r\n\r\ntypedef struct\r\n{\r\n __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */\r\n __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */\r\n __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */\r\n __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */\r\n}DBGMCU_TypeDef;\r\n\r\n/** \r\n * @brief DCMI\r\n */\r\n\r\ntypedef struct\r\n{\r\n __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */\r\n __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */\r\n __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */\r\n __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */\r\n __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */\r\n __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */\r\n __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */\r\n __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */\r\n __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */\r\n __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */\r\n __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */\r\n} DCMI_TypeDef;\r\n\r\n/** \r\n * @brief DMA Controller\r\n */\r\n\r\ntypedef struct\r\n{\r\n __IO uint32_t CR; /*!< DMA stream x configuration register */\r\n __IO uint32_t NDTR; /*!< DMA stream x number of data register */\r\n __IO uint32_t PAR; /*!< DMA stream x peripheral address register */\r\n __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */\r\n __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */\r\n __IO uint32_t FCR; /*!< DMA stream x FIFO control register */\r\n} DMA_Stream_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */\r\n __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */\r\n __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */\r\n __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */\r\n} DMA_TypeDef;\r\n\r\n/** \r\n * @brief Ethernet MAC\r\n */\r\n\r\ntypedef struct\r\n{\r\n __IO uint32_t MACCR;\r\n __IO uint32_t MACFFR;\r\n __IO uint32_t MACHTHR;\r\n __IO uint32_t MACHTLR;\r\n __IO uint32_t MACMIIAR;\r\n __IO uint32_t MACMIIDR;\r\n __IO uint32_t MACFCR;\r\n __IO uint32_t MACVLANTR; /* 8 */\r\n uint32_t RESERVED0[2];\r\n __IO uint32_t MACRWUFFR; /* 11 */\r\n __IO uint32_t MACPMTCSR;\r\n uint32_t RESERVED1[2];\r\n __IO uint32_t MACSR; /* 15 */\r\n __IO uint32_t MACIMR;\r\n __IO uint32_t MACA0HR;\r\n __IO uint32_t MACA0LR;\r\n __IO uint32_t MACA1HR;\r\n __IO uint32_t MACA1LR;\r\n __IO uint32_t MACA2HR;\r\n __IO uint32_t MACA2LR;\r\n __IO uint32_t MACA3HR;\r\n __IO uint32_t MACA3LR; /* 24 */\r\n uint32_t RESERVED2[40];\r\n __IO uint32_t MMCCR; /* 65 */\r\n __IO uint32_t MMCRIR;\r\n __IO uint32_t MMCTIR;\r\n __IO uint32_t MMCRIMR;\r\n __IO uint32_t MMCTIMR; /* 69 */\r\n uint32_t RESERVED3[14];\r\n __IO uint32_t MMCTGFSCCR; /* 84 */\r\n __IO uint32_t MMCTGFMSCCR;\r\n uint32_t RESERVED4[5];\r\n __IO uint32_t MMCTGFCR;\r\n uint32_t RESERVED5[10];\r\n __IO uint32_t MMCRFCECR;\r\n __IO uint32_t MMCRFAECR;\r\n uint32_t RESERVED6[10];\r\n __IO uint32_t MMCRGUFCR;\r\n uint32_t RESERVED7[334];\r\n __IO uint32_t PTPTSCR;\r\n __IO uint32_t PTPSSIR;\r\n __IO uint32_t PTPTSHR;\r\n __IO uint32_t PTPTSLR;\r\n __IO uint32_t PTPTSHUR;\r\n __IO uint32_t PTPTSLUR;\r\n __IO uint32_t PTPTSAR;\r\n __IO uint32_t PTPTTHR;\r\n __IO uint32_t PTPTTLR;\r\n __IO uint32_t RESERVED8;\r\n __IO uint32_t PTPTSSR;\r\n uint32_t RESERVED9[565];\r\n __IO uint32_t DMABMR;\r\n __IO uint32_t DMATPDR;\r\n __IO uint32_t DMARPDR;\r\n __IO uint32_t DMARDLAR;\r\n __IO uint32_t DMATDLAR;\r\n __IO uint32_t DMASR;\r\n __IO uint32_t DMAOMR;\r\n __IO uint32_t DMAIER;\r\n __IO uint32_t DMAMFBOCR;\r\n __IO uint32_t DMARSWTR;\r\n uint32_t RESERVED10[8];\r\n __IO uint32_t DMACHTDR;\r\n __IO uint32_t DMACHRDR;\r\n __IO uint32_t DMACHTBAR;\r\n __IO uint32_t DMACHRBAR;\r\n} ETH_TypeDef;\r\n\r\n/** \r\n * @brief External Interrupt/Event Controller\r\n */\r\n\r\ntypedef struct\r\n{\r\n __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */\r\n __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */\r\n __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */\r\n __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */\r\n __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */\r\n __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */\r\n} EXTI_TypeDef;\r\n\r\n/** \r\n * @brief FLASH Registers\r\n */\r\n\r\ntypedef struct\r\n{\r\n __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */\r\n __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */\r\n __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */\r\n __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */\r\n __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */\r\n __IO uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x14 */\r\n} FLASH_TypeDef;\r\n\r\n/** \r\n * @brief Flexible Static Memory Controller\r\n */\r\n\r\ntypedef struct\r\n{\r\n __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ \r\n} FSMC_Bank1_TypeDef; \r\n\r\n/** \r\n * @brief Flexible Static Memory Controller Bank1E\r\n */\r\n \r\ntypedef struct\r\n{\r\n __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\r\n} FSMC_Bank1E_TypeDef;\r\n\r\n/** \r\n * @brief Flexible Static Memory Controller Bank2\r\n */\r\n \r\ntypedef struct\r\n{\r\n __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */\r\n __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */\r\n __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */\r\n __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */\r\n uint32_t RESERVED0; /*!< Reserved, 0x70 */\r\n __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */\r\n} FSMC_Bank2_TypeDef;\r\n\r\n/** \r\n * @brief Flexible Static Memory Controller Bank3\r\n */\r\n \r\ntypedef struct\r\n{\r\n __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */\r\n __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */\r\n __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */\r\n __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */\r\n uint32_t RESERVED0; /*!< Reserved, 0x90 */\r\n __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */\r\n} FSMC_Bank3_TypeDef;\r\n\r\n/** \r\n * @brief Flexible Static Memory Controller Bank4\r\n */\r\n \r\ntypedef struct\r\n{\r\n __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */\r\n __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */\r\n __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */\r\n __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */\r\n __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */\r\n} FSMC_Bank4_TypeDef; \r\n\r\n/** \r\n * @brief General Purpose I/O\r\n */\r\n\r\ntypedef struct\r\n{\r\n __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */\r\n __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */\r\n __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */\r\n __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */\r\n __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */\r\n __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */\r\n __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */\r\n __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */\r\n __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */\r\n __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */\r\n} GPIO_TypeDef;\r\n\r\n/** \r\n * @brief System configuration controller\r\n */\r\n \r\ntypedef struct\r\n{\r\n __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */\r\n __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */\r\n __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\r\n uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ \r\n __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */\r\n} SYSCFG_TypeDef;\r\n\r\n/** \r\n * @brief Inter-integrated Circuit Interface\r\n */\r\n\r\ntypedef struct\r\n{\r\n __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */\r\n uint16_t RESERVED0; /*!< Reserved, 0x02 */\r\n __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */\r\n uint16_t RESERVED1; /*!< Reserved, 0x06 */\r\n __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */\r\n uint16_t RESERVED2; /*!< Reserved, 0x0A */\r\n __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */\r\n uint16_t RESERVED3; /*!< Reserved, 0x0E */\r\n __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */\r\n uint16_t RESERVED4; /*!< Reserved, 0x12 */\r\n __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */\r\n uint16_t RESERVED5; /*!< Reserved, 0x16 */\r\n __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */\r\n uint16_t RESERVED6; /*!< Reserved, 0x1A */\r\n __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */\r\n uint16_t RESERVED7; /*!< Reserved, 0x1E */\r\n __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */\r\n uint16_t RESERVED8; /*!< Reserved, 0x22 */\r\n} I2C_TypeDef;\r\n\r\n/** \r\n * @brief Independent WATCHDOG\r\n */\r\n\r\ntypedef struct\r\n{\r\n __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */\r\n __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */\r\n __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */\r\n __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */\r\n} IWDG_TypeDef;\r\n\r\n/** \r\n * @brief Power Control\r\n */\r\n\r\ntypedef struct\r\n{\r\n __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */\r\n __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */\r\n} PWR_TypeDef;\r\n\r\n/** \r\n * @brief Reset and Clock Control\r\n */\r\n\r\ntypedef struct\r\n{\r\n __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */\r\n __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */\r\n __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */\r\n __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */\r\n __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */\r\n __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */\r\n __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */\r\n uint32_t RESERVED0; /*!< Reserved, 0x1C */\r\n __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */\r\n __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */\r\n uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */\r\n __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */\r\n __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */\r\n __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */\r\n uint32_t RESERVED2; /*!< Reserved, 0x3C */\r\n __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */\r\n __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */\r\n uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */\r\n __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */\r\n __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */\r\n __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */\r\n uint32_t RESERVED4; /*!< Reserved, 0x5C */\r\n __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */\r\n __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */\r\n uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */\r\n __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */\r\n __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */\r\n uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */\r\n __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */\r\n __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */\r\n} RCC_TypeDef;\r\n\r\n/** \r\n * @brief Real-Time Clock\r\n */\r\n\r\ntypedef struct\r\n{\r\n __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */\r\n __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */\r\n __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */\r\n __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */\r\n __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */\r\n __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */\r\n __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */\r\n __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */\r\n __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */\r\n __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */\r\n __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */\r\n __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */\r\n __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */\r\n __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */\r\n __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */\r\n __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */\r\n __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */\r\n __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */\r\n __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */\r\n uint32_t RESERVED7; /*!< Reserved, 0x4C */\r\n __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */\r\n __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */\r\n __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */\r\n __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */\r\n __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */\r\n __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */\r\n __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */\r\n __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */\r\n __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */\r\n __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */\r\n __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */\r\n __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */\r\n __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */\r\n __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */\r\n __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */\r\n __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */\r\n __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */\r\n __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */\r\n __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */\r\n __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */\r\n} RTC_TypeDef;\r\n\r\n/** \r\n * @brief SD host Interface\r\n */\r\n\r\ntypedef struct\r\n{\r\n __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */\r\n __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */\r\n __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */\r\n __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */\r\n __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */\r\n __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */\r\n __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */\r\n __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */\r\n __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */\r\n __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */\r\n __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */\r\n __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */\r\n __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */\r\n __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */\r\n __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */\r\n __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */\r\n uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */\r\n __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */\r\n uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */\r\n __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */\r\n} SDIO_TypeDef;\r\n\r\n/** \r\n * @brief Serial Peripheral Interface\r\n */\r\n\r\ntypedef struct\r\n{\r\n __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */\r\n uint16_t RESERVED0; /*!< Reserved, 0x02 */\r\n __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */\r\n uint16_t RESERVED1; /*!< Reserved, 0x06 */\r\n __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */\r\n uint16_t RESERVED2; /*!< Reserved, 0x0A */\r\n __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */\r\n uint16_t RESERVED3; /*!< Reserved, 0x0E */\r\n __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */\r\n uint16_t RESERVED4; /*!< Reserved, 0x12 */\r\n __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */\r\n uint16_t RESERVED5; /*!< Reserved, 0x16 */\r\n __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */\r\n uint16_t RESERVED6; /*!< Reserved, 0x1A */\r\n __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */\r\n uint16_t RESERVED7; /*!< Reserved, 0x1E */\r\n __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */\r\n uint16_t RESERVED8; /*!< Reserved, 0x22 */\r\n} SPI_TypeDef;\r\n\r\n/** \r\n * @brief TIM\r\n */\r\n\r\ntypedef struct\r\n{\r\n __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */\r\n uint16_t RESERVED0; /*!< Reserved, 0x02 */\r\n __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */\r\n uint16_t RESERVED1; /*!< Reserved, 0x06 */\r\n __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */\r\n uint16_t RESERVED2; /*!< Reserved, 0x0A */\r\n __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */\r\n uint16_t RESERVED3; /*!< Reserved, 0x0E */\r\n __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */\r\n uint16_t RESERVED4; /*!< Reserved, 0x12 */\r\n __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */\r\n uint16_t RESERVED5; /*!< Reserved, 0x16 */\r\n __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\r\n uint16_t RESERVED6; /*!< Reserved, 0x1A */\r\n __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\r\n uint16_t RESERVED7; /*!< Reserved, 0x1E */\r\n __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */\r\n uint16_t RESERVED8; /*!< Reserved, 0x22 */\r\n __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */\r\n __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */\r\n uint16_t RESERVED9; /*!< Reserved, 0x2A */\r\n __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */\r\n __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */\r\n uint16_t RESERVED10; /*!< Reserved, 0x32 */\r\n __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */\r\n __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */\r\n __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */\r\n __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */\r\n __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */\r\n uint16_t RESERVED11; /*!< Reserved, 0x46 */\r\n __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */\r\n uint16_t RESERVED12; /*!< Reserved, 0x4A */\r\n __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */\r\n uint16_t RESERVED13; /*!< Reserved, 0x4E */\r\n __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */\r\n uint16_t RESERVED14; /*!< Reserved, 0x52 */\r\n} TIM_TypeDef;\r\n\r\n/** \r\n * @brief Universal Synchronous Asynchronous Receiver Transmitter\r\n */\r\n \r\ntypedef struct\r\n{\r\n __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */\r\n uint16_t RESERVED0; /*!< Reserved, 0x02 */\r\n __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */\r\n uint16_t RESERVED1; /*!< Reserved, 0x06 */\r\n __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */\r\n uint16_t RESERVED2; /*!< Reserved, 0x0A */\r\n __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */\r\n uint16_t RESERVED3; /*!< Reserved, 0x0E */\r\n __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */\r\n uint16_t RESERVED4; /*!< Reserved, 0x12 */\r\n __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */\r\n uint16_t RESERVED5; /*!< Reserved, 0x16 */\r\n __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */\r\n uint16_t RESERVED6; /*!< Reserved, 0x1A */\r\n} USART_TypeDef;\r\n\r\n/** \r\n * @brief Window WATCHDOG\r\n */\r\n\r\ntypedef struct\r\n{\r\n __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */\r\n __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */\r\n __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */\r\n} WWDG_TypeDef;\r\n\r\n/** \r\n * @brief Crypto Processor\r\n */\r\n\r\ntypedef struct\r\n{\r\n __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */\r\n __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */\r\n __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */\r\n __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */\r\n __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */\r\n __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */\r\n __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */\r\n __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */\r\n __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */\r\n __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */\r\n __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */\r\n __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */\r\n __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */\r\n __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */\r\n __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */\r\n __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */\r\n __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */\r\n __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */\r\n __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */\r\n __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */\r\n} CRYP_TypeDef;\r\n\r\n/** \r\n * @brief HASH\r\n */\r\n \r\ntypedef struct \r\n{\r\n __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */\r\n __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */\r\n __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */\r\n __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */\r\n __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */\r\n __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */\r\n uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */\r\n __IO uint32_t CSR[51]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1C0 */ \r\n} HASH_TypeDef;\r\n\r\n/** \r\n * @brief HASH\r\n */\r\n \r\ntypedef struct \r\n{\r\n __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */\r\n __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */\r\n __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */\r\n} RNG_TypeDef;\r\n\r\n/**\r\n * @}\r\n */\r\n \r\n/** @addtogroup Peripheral_memory_map\r\n * @{\r\n */\r\n#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */\r\n#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */\r\n#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */\r\n#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */\r\n#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */\r\n#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */\r\n#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */\r\n\r\n#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */\r\n#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */\r\n#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */\r\n#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */\r\n#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */\r\n\r\n/* Legacy defines */\r\n#define SRAM_BASE SRAM1_BASE\r\n#define SRAM_BB_BASE SRAM1_BB_BASE\r\n\r\n\r\n/*!< Peripheral memory map */\r\n#define APB1PERIPH_BASE PERIPH_BASE\r\n#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)\r\n#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)\r\n#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)\r\n\r\n/*!< APB1 peripherals */\r\n#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)\r\n#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)\r\n#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)\r\n#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)\r\n#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)\r\n#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)\r\n#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)\r\n#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)\r\n#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)\r\n#define RTC_BASE (APB1PERIPH_BASE + 0x2800)\r\n#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)\r\n#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)\r\n#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)\r\n#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)\r\n#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)\r\n#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)\r\n#define USART2_BASE (APB1PERIPH_BASE + 0x4400)\r\n#define USART3_BASE (APB1PERIPH_BASE + 0x4800)\r\n#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)\r\n#define UART5_BASE (APB1PERIPH_BASE + 0x5000)\r\n#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)\r\n#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)\r\n#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)\r\n#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)\r\n#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)\r\n#define PWR_BASE (APB1PERIPH_BASE + 0x7000)\r\n#define DAC_BASE (APB1PERIPH_BASE + 0x7400)\r\n\r\n/*!< APB2 peripherals */\r\n#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)\r\n#define TIM8_BASE (APB2PERIPH_BASE + 0x0400)\r\n#define USART1_BASE (APB2PERIPH_BASE + 0x1000)\r\n#define USART6_BASE (APB2PERIPH_BASE + 0x1400)\r\n#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)\r\n#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)\r\n#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)\r\n#define ADC_BASE (APB2PERIPH_BASE + 0x2300)\r\n#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)\r\n#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)\r\n#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)\r\n#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)\r\n#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)\r\n#define TIM10_BASE (APB2PERIPH_BASE + 0x4400)\r\n#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)\r\n\r\n/*!< AHB1 peripherals */\r\n#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)\r\n#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)\r\n#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)\r\n#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)\r\n#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)\r\n#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)\r\n#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)\r\n#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)\r\n#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)\r\n#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)\r\n#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)\r\n#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)\r\n#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)\r\n#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)\r\n#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)\r\n#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)\r\n#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)\r\n#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)\r\n#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)\r\n#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)\r\n#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)\r\n#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)\r\n#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)\r\n#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)\r\n#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)\r\n#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)\r\n#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)\r\n#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)\r\n#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)\r\n#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)\r\n#define ETH_BASE (AHB1PERIPH_BASE + 0x8000)\r\n#define ETH_MAC_BASE (ETH_BASE)\r\n#define ETH_MMC_BASE (ETH_BASE + 0x0100)\r\n#define ETH_PTP_BASE (ETH_BASE + 0x0700)\r\n#define ETH_DMA_BASE (ETH_BASE + 0x1000)\r\n\r\n/*!< AHB2 peripherals */\r\n#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)\r\n#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000)\r\n#define HASH_BASE (AHB2PERIPH_BASE + 0x60400)\r\n#define RNG_BASE (AHB2PERIPH_BASE + 0x60800)\r\n\r\n/*!< FSMC Bankx registers base address */\r\n#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)\r\n#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)\r\n#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)\r\n#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)\r\n#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)\r\n\r\n/* Debug MCU registers base address */\r\n#define DBGMCU_BASE ((uint32_t )0xE0042000)\r\n\r\n/**\r\n * @}\r\n */\r\n \r\n/** @addtogroup Peripheral_declaration\r\n * @{\r\n */ \r\n#define TIM2 ((TIM_TypeDef *) TIM2_BASE)\r\n#define TIM3 ((TIM_TypeDef *) TIM3_BASE)\r\n#define TIM4 ((TIM_TypeDef *) TIM4_BASE)\r\n#define TIM5 ((TIM_TypeDef *) TIM5_BASE)\r\n#define TIM6 ((TIM_TypeDef *) TIM6_BASE)\r\n#define TIM7 ((TIM_TypeDef *) TIM7_BASE)\r\n#define TIM12 ((TIM_TypeDef *) TIM12_BASE)\r\n#define TIM13 ((TIM_TypeDef *) TIM13_BASE)\r\n#define TIM14 ((TIM_TypeDef *) TIM14_BASE)\r\n#define RTC ((RTC_TypeDef *) RTC_BASE)\r\n#define WWDG ((WWDG_TypeDef *) WWDG_BASE)\r\n#define IWDG ((IWDG_TypeDef *) IWDG_BASE)\r\n#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)\r\n#define SPI2 ((SPI_TypeDef *) SPI2_BASE)\r\n#define SPI3 ((SPI_TypeDef *) SPI3_BASE)\r\n#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)\r\n#define USART2 ((USART_TypeDef *) USART2_BASE)\r\n#define USART3 ((USART_TypeDef *) USART3_BASE)\r\n#define UART4 ((USART_TypeDef *) UART4_BASE)\r\n#define UART5 ((USART_TypeDef *) UART5_BASE)\r\n#define I2C1 ((I2C_TypeDef *) I2C1_BASE)\r\n#define I2C2 ((I2C_TypeDef *) I2C2_BASE)\r\n#define I2C3 ((I2C_TypeDef *) I2C3_BASE)\r\n#define CAN1 ((CAN_TypeDef *) CAN1_BASE)\r\n#define CAN2 ((CAN_TypeDef *) CAN2_BASE)\r\n#define PWR ((PWR_TypeDef *) PWR_BASE)\r\n#define DAC ((DAC_TypeDef *) DAC_BASE)\r\n#define TIM1 ((TIM_TypeDef *) TIM1_BASE)\r\n#define TIM8 ((TIM_TypeDef *) TIM8_BASE)\r\n#define USART1 ((USART_TypeDef *) USART1_BASE)\r\n#define USART6 ((USART_TypeDef *) USART6_BASE)\r\n#define ADC ((ADC_Common_TypeDef *) ADC_BASE)\r\n#define ADC1 ((ADC_TypeDef *) ADC1_BASE)\r\n#define ADC2 ((ADC_TypeDef *) ADC2_BASE)\r\n#define ADC3 ((ADC_TypeDef *) ADC3_BASE)\r\n#define SDIO ((SDIO_TypeDef *) SDIO_BASE)\r\n#define SPI1 ((SPI_TypeDef *) SPI1_BASE)\r\n#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)\r\n#define EXTI ((EXTI_TypeDef *) EXTI_BASE)\r\n#define TIM9 ((TIM_TypeDef *) TIM9_BASE)\r\n#define TIM10 ((TIM_TypeDef *) TIM10_BASE)\r\n#define TIM11 ((TIM_TypeDef *) TIM11_BASE)\r\n#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)\r\n#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)\r\n#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)\r\n#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)\r\n#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)\r\n#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)\r\n#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)\r\n#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)\r\n#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)\r\n#define CRC ((CRC_TypeDef *) CRC_BASE)\r\n#define RCC ((RCC_TypeDef *) RCC_BASE)\r\n#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)\r\n#define DMA1 ((DMA_TypeDef *) DMA1_BASE)\r\n#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)\r\n#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)\r\n#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)\r\n#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)\r\n#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)\r\n#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)\r\n#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)\r\n#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)\r\n#define DMA2 ((DMA_TypeDef *) DMA2_BASE)\r\n#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)\r\n#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)\r\n#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)\r\n#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)\r\n#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)\r\n#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)\r\n#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)\r\n#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)\r\n#define ETH ((ETH_TypeDef *) ETH_BASE) \r\n#define DCMI ((DCMI_TypeDef *) DCMI_BASE)\r\n#define CRYP ((CRYP_TypeDef *) CRYP_BASE)\r\n#define HASH ((HASH_TypeDef *) HASH_BASE)\r\n#define RNG ((RNG_TypeDef *) RNG_BASE)\r\n#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)\r\n#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)\r\n#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)\r\n#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)\r\n#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)\r\n#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @addtogroup Exported_constants\r\n * @{\r\n */\r\n \r\n /** @addtogroup Peripheral_Registers_Bits_Definition\r\n * @{\r\n */\r\n \r\n/******************************************************************************/\r\n/* Peripheral Registers_Bits_Definition */\r\n/******************************************************************************/\r\n\r\n/******************************************************************************/\r\n/* */\r\n/* Analog to Digital Converter */\r\n/* */\r\n/******************************************************************************/\r\n/******************** Bit definition for ADC_SR register ********************/\r\n#define ADC_SR_AWD ((uint8_t)0x01) /*!
© COPYRIGHT 2012 STMicroelectronics
\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/** @addtogroup CMSIS\r\n * @{\r\n */\r\n\r\n/** @addtogroup stm32f4xx_system\r\n * @{\r\n */ \r\n \r\n/**\r\n * @brief Define to prevent recursive inclusion\r\n */\r\n#ifndef __SYSTEM_STM32F4XX_H\r\n#define __SYSTEM_STM32F4XX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif \r\n\r\n/** @addtogroup STM32F4xx_System_Includes\r\n * @{\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n\r\n/** @addtogroup STM32F4xx_System_Exported_types\r\n * @{\r\n */\r\n\r\nextern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */\r\n\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @addtogroup STM32F4xx_System_Exported_Constants\r\n * @{\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @addtogroup STM32F4xx_System_Exported_Macros\r\n * @{\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @addtogroup STM32F4xx_System_Exported_Functions\r\n * @{\r\n */\r\n \r\nextern void SystemInit(void);\r\nextern void SystemCoreClockUpdate(void);\r\n/**\r\n * @}\r\n */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /*__SYSTEM_STM32F4XX_H */\r\n\r\n/**\r\n * @}\r\n */\r\n \r\n/**\r\n * @}\r\n */ \r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/Device/STM32F4xx/Release_Notes.html", "content": "\n\r\n\r\n\r\n\r\n\r\n\r\nRelease Notes for STM32F4xx CMSIS\r\n\r\n\r\n\r\n\r\n\r\n
\r\n


\r\n

\r\n
\r\n\r\n\r\n\r\n\r\n\r\n\r\n
\r\n\r\n\r\n \r\n \r\n \r\n\r\n\r\n\r\n\r\n
Back to Release page
\r\n

Release\r\nNotes for STM32F4xx CMSIS

\r\n

Copyright 2012 STMicroelectronics

\r\n

\"\"

\r\n
\r\n

 

\r\n\r\n\r\n\r\n\r\n\r\n\r\n
\r\n

Contents

\r\n
    \r\n
  1. STM32F4xx CMSIS\r\nupdate History
    2. \r\n
  2. License
    3. \r\n
\r\n\r\n

STM32F4xx CMSIS\r\nupdate History

V1.0.2 / 05-March-2012

\r\n

Main\r\nChanges

\r\n\r\n
  • All source files: license disclaimer text update and add link to the License file on ST Internet.

V1.0.1 / 28-December-2011

Main\r\nChanges

\r\n
  • All source files: update disclaimer to add reference to the new license agreement
  • stm32f4xx.h
    • Correct bit definition: RCC_AHB2RSTR_HSAHRST changed to RCC_AHB2RSTR_HASHRST

V1.0.0 / 30-September-2011

Main\r\nChanges

\r\n
  • First official release for STM32F40x/41x devices
  • Add startup file for TASKING toolchain
  • system_stm32f4xx.c: driver's comments update

V1.0.0RC2 / 26-September-2011

Main\r\nChanges

\r\n
  • Official version (V1.0.0) Release Candidate2 for STM32F40x/41x devices
  • stm32f4xx.h
    • Add define for Cortex-M4 revision __CM4_REV
    • Correct RCC_CFGR_PPRE2_DIV16 bit (in RCC_CFGR register) value to 0x0000E000
    • Correct some bits definition to be in line with naming used in the Reference Manual (RM0090)
      • GPIO_OTYPER_IDR_x changed to GPIO_IDR_IDR_x
      • GPIO_OTYPER_ODR_x changed to GPIO_ODR_ODR_x
      • SYSCFG_PMC_MII_RMII changed to SYSCFG_PMC_MII_RMII_SEL
      • RCC_APB2RSTR_SPI1 changed to RCC_APB2RSTR_SPI1RST
      • DBGMCU_APB1_FZ_DBG_IWDEG_STOP changed to DBGMCU_APB1_FZ_DBG_IWDG_STOP
      • PWR_CR_PMODE changed to PWR_CR_VOS
      • PWR_CSR_REGRDY changed to PWR_CSR_VOSRDY
      • Add new define RCC_AHB1ENR_CCMDATARAMEN
      • Add new defines SRAM2_BASE, CCMDATARAM_BASE and BKPSRAM_BASE
    • GPIO_TypeDef structure: in the comment change AFR[2] address mapping to 0x20-0x24 instead of 0x24-0x28
  • system_stm32f4xx.c
    • SystemInit(): add code to enable the FPU
    • SetSysClock(): change PWR_CR_PMODE by PWR_CR_VOS
    • SystemInit_ExtMemCtl(): remove commented values
  • startup (for all compilers)
    • Delete code used to enable the FPU (moved to system_stm32f4xx.c file)
    • File’s header updated

V1.0.0RC1 / 25-August-2011

Main\r\nChanges

\r\n
  • Official version (V1.0.0) Release Candidate1 for STM32F4xx devices
\r\n\r\n
    \r\n
\r\n

License

\r\n\r\n\r\n

Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:


Unless\r\nrequired by applicable law or agreed to in writing, software\r\ndistributed under the License is distributed on an \"AS IS\" BASIS,
WITHOUT\r\nWARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See\r\nthe License for the specific language governing permissions and\r\nlimitations under the License.\r\n
\r\n
\r\n

For\r\ncomplete documentation on STM32 Microcontrollers\r\nvisit www.st.com/STM32

\r\n
\r\n

\r\n
\r\n
\r\n

 

\r\n
\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/Release_Notes.html", "content": "\n\r\n\r\n\r\n\r\n\r\n\r\n\r\nRelease Notes for STM32F4xx Standard Peripherals Library Drivers\r\n\r\n\r\n\r\n\r\n\r\n
\r\n\r\n

 

\r\n\r\n
\r\n\r\n\r\n \r\n \r\n \r\n
\r\n \r\n \r\n \r\n \r\n \r\n \r\n \r\n
\r\n

Back to Release page

\r\n
\r\n

Release Notes for STM32F4xx Standard\r\n Peripherals Library Drivers

\r\n

Copyright\r\n 2012 STMicroelectronics

\r\n

\r\n
\r\n

 

\r\n \r\n \r\n \r\n \r\n
\r\n

Contents

\r\n
    \r\n
  1. STM32F4xx Standard Peripherals Library Drivers\r\n update History
    2. \r\n
  2. License
    3. \r\n
\r\n

STM32F4xx\r\n Standard Peripherals Library Drivers  update History

V1.0.2 / 05-March-2012

\r\n

Main\r\nChanges

\r\n\r\n
  • All source files: license disclaimer text update and add link to the License file on ST Internet.
  • stm32f4xx_dcmi.c
    • DCMI_GetFlagStatus() function: fix test condition on RISR register, use if (dcmireg == 0x00) instead of if (dcmireg == 0x01)
  • stm32f4xx_pwr.c
    • PWR_PVDLevelConfig()\r\nfunction: remove value of the voltage threshold corresponding to each\r\nPVD detection level, user should refer to the electrical\r\ncharacteristics of the STM32 device datasheet to have the correct\r\nvalue

V1.0.1 / 28-December-2011

Main\r\nChanges

\r\n
  • All source files: update disclaimer to add reference to the new license agreement
  • stm32f4xx_rtc.c: 
    • In RTC_FLAGS_MASK define: add RTC_FLAG_RECALPF and RTC_FLAG_SHPF
    • RTC_DeInit() function: add reset of the following registers: SHIFTR, CALR, ALRMASSR and ALRMBSSR
    • RTC_SetTime() and RTC_SetDate() functions: add test condition on BYPSHAD flag before to test RSF flag (when Bypass mode is enabled, the RSF bit is never set).

V1.0.0 / 30-September-2011

Main\r\nChanges

\r\n
  • First official release for STM32F40x/41x devices
  • stm32f4xx_rtc.c: remove useless code from RTC_GetDate() function
  • stm32f4xx_rcc.c, stm32f4xx_spi.c, stm32f4xx_wwdg.c and stm32f4xx_syscfg.c: driver's comments update

V1.0.0RC2 / 26-September-2011

Main\r\nChanges

\r\n
  • Official version (V1.0.0) Release Candidate1 for STM32F40x/STM32F41x devices
  • stm32f4xx_usart.h/.c
    • Update procedure to check on overrun error interrupt pending bit, defines for the following flag are added:
      • USART_IT_ORE_RX: this flag is set if overrun error interrupt occurs and RXNEIE bit is set
      • USART_IT_ORE_ER: this flag is set if overrun error interrupt occurs and EIE bit is set
  • stm32f4xx_tim.c
    • TIM_UpdateRequestConfig(): correct function header's comment 
    • TIM_ICInit(): add assert macros to test if the passed TIM parameter has channel 2, 3 or 4
  • stm32f4xx_pwr.h/.c
    • Rename PWR_FLAG_REGRDY constant to PWR_CSR_REGRDY
    • Rename PWR_FLAG_VOSRDY constant to PWR_CSR_VOSRDY
    • Rename PWR_HighPerformanceModeCmd(FunctionalState NewState) function to PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage)
  • stm32f4xx_rcc.h/.c
    • RCC_AHB1PeriphClockCmd(): add new constant RCC_AHB1Periph_CCMDATARAMEN as value for RCC_AHB1Periph parameter
  • stm32f4xx_spi.h
    • IS_I2S_EXT_PERIPH(): add check on I2S3ext peripheral

V1.0.0RC1 / 25-August-2011

Main\r\nChanges

\r\n
  • Official version (V1.0.0) Release Candidate1 for STM32F4xx devices
\r\n

License

\r\n \r\n \r\n

Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:


Unless\r\nrequired by applicable law or agreed to in writing, software\r\ndistributed under the License is distributed on an \"AS IS\" BASIS,
WITHOUT\r\nWARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See\r\nthe License for the specific language governing permissions and\r\nlimitations under the License.\r\n
\r\n
\r\n
\r\n

For\r\n complete documentation on STM32\r\n Microcontrollers visit www.st.com/STM32

\r\n
\r\n

\r\n
\r\n\r\n
\r\n\r\n

 

\r\n\r\n
\r\n\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/misc.h", "content": "/**\r\n ******************************************************************************\r\n * @file misc.h\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file contains all the functions prototypes for the miscellaneous\r\n * firmware library functions (add-on to CMSIS functions).\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __MISC_H\r\n#define __MISC_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @addtogroup MISC\r\n * @{\r\n */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n\r\n/** \r\n * @brief NVIC Init Structure definition \r\n */\r\n\r\ntypedef struct\r\n{\r\n uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.\r\n This parameter can be an enumerator of @ref IRQn_Type \r\n enumeration (For the complete STM32 Devices IRQ Channels\r\n list, please refer to stm32f4xx.h file) */\r\n\r\n uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel\r\n specified in NVIC_IRQChannel. This parameter can be a value\r\n between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table\r\n A lower priority value indicates a higher priority */\r\n\r\n uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified\r\n in NVIC_IRQChannel. This parameter can be a value\r\n between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table\r\n A lower priority value indicates a higher priority */\r\n\r\n FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel\r\n will be enabled or disabled. \r\n This parameter can be set either to ENABLE or DISABLE */ \r\n} NVIC_InitTypeDef;\r\n \r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup MISC_Exported_Constants\r\n * @{\r\n */\r\n\r\n/** @defgroup MISC_Vector_Table_Base \r\n * @{\r\n */\r\n\r\n#define NVIC_VectTab_RAM ((uint32_t)0x20000000)\r\n#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)\r\n#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \\\r\n ((VECTTAB) == NVIC_VectTab_FLASH))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup MISC_System_Low_Power \r\n * @{\r\n */\r\n\r\n#define NVIC_LP_SEVONPEND ((uint8_t)0x10)\r\n#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)\r\n#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)\r\n#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \\\r\n ((LP) == NVIC_LP_SLEEPDEEP) || \\\r\n ((LP) == NVIC_LP_SLEEPONEXIT))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup MISC_Preemption_Priority_Group \r\n * @{\r\n */\r\n\r\n#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority\r\n 4 bits for subpriority */\r\n#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority\r\n 3 bits for subpriority */\r\n#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority\r\n 2 bits for subpriority */\r\n#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority\r\n 1 bits for subpriority */\r\n#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority\r\n 0 bits for subpriority */\r\n\r\n#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \\\r\n ((GROUP) == NVIC_PriorityGroup_1) || \\\r\n ((GROUP) == NVIC_PriorityGroup_2) || \\\r\n ((GROUP) == NVIC_PriorityGroup_3) || \\\r\n ((GROUP) == NVIC_PriorityGroup_4))\r\n\r\n#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)\r\n\r\n#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)\r\n\r\n#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup MISC_SysTick_clock_source \r\n * @{\r\n */\r\n\r\n#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)\r\n#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)\r\n#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \\\r\n ((SOURCE) == SysTick_CLKSource_HCLK_Div8))\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\nvoid NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);\r\nvoid NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);\r\nvoid NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);\r\nvoid NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);\r\nvoid SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __MISC_H */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_adc.h\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file contains all the functions prototypes for the ADC firmware \r\n * library.\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F4xx_ADC_H\r\n#define __STM32F4xx_ADC_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @addtogroup ADC\r\n * @{\r\n */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n\r\n/** \r\n * @brief ADC Init structure definition \r\n */ \r\ntypedef struct\r\n{\r\n uint32_t ADC_Resolution; /*!< Configures the ADC resolution dual mode. \r\n This parameter can be a value of @ref ADC_resolution */ \r\n FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion \r\n is performed in Scan (multichannels) \r\n or Single (one channel) mode.\r\n This parameter can be set to ENABLE or DISABLE */ \r\n FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion \r\n is performed in Continuous or Single mode.\r\n This parameter can be set to ENABLE or DISABLE. */\r\n uint32_t ADC_ExternalTrigConvEdge; /*!< Select the external trigger edge and\r\n enable the trigger of a regular group. \r\n This parameter can be a value of \r\n @ref ADC_external_trigger_edge_for_regular_channels_conversion */\r\n uint32_t ADC_ExternalTrigConv; /*!< Select the external event used to trigger \r\n the start of conversion of a regular group.\r\n This parameter can be a value of \r\n @ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */\r\n uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment\r\n is left or right. This parameter can be \r\n a value of @ref ADC_data_align */\r\n uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions\r\n that will be done using the sequencer for\r\n regular channel group.\r\n This parameter must range from 1 to 16. */\r\n}ADC_InitTypeDef;\r\n \r\n/** \r\n * @brief ADC Common Init structure definition \r\n */ \r\ntypedef struct \r\n{\r\n uint32_t ADC_Mode; /*!< Configures the ADC to operate in \r\n independent or multi mode. \r\n This parameter can be a value of @ref ADC_Common_mode */ \r\n uint32_t ADC_Prescaler; /*!< Select the frequency of the clock \r\n to the ADC. The clock is common for all the ADCs.\r\n This parameter can be a value of @ref ADC_Prescaler */\r\n uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access \r\n mode for multi ADC mode.\r\n This parameter can be a value of \r\n @ref ADC_Direct_memory_access_mode_for_multi_mode */\r\n uint32_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.\r\n This parameter can be a value of \r\n @ref ADC_delay_between_2_sampling_phases */\r\n \r\n}ADC_CommonInitTypeDef;\r\n\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup ADC_Exported_Constants\r\n * @{\r\n */ \r\n#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \\\r\n ((PERIPH) == ADC2) || \\\r\n ((PERIPH) == ADC3)) \r\n\r\n/** @defgroup ADC_Common_mode \r\n * @{\r\n */ \r\n#define ADC_Mode_Independent ((uint32_t)0x00000000) \r\n#define ADC_DualMode_RegSimult_InjecSimult ((uint32_t)0x00000001)\r\n#define ADC_DualMode_RegSimult_AlterTrig ((uint32_t)0x00000002)\r\n#define ADC_DualMode_InjecSimult ((uint32_t)0x00000005)\r\n#define ADC_DualMode_RegSimult ((uint32_t)0x00000006)\r\n#define ADC_DualMode_Interl ((uint32_t)0x00000007)\r\n#define ADC_DualMode_AlterTrig ((uint32_t)0x00000009)\r\n#define ADC_TripleMode_RegSimult_InjecSimult ((uint32_t)0x00000011)\r\n#define ADC_TripleMode_RegSimult_AlterTrig ((uint32_t)0x00000012)\r\n#define ADC_TripleMode_InjecSimult ((uint32_t)0x00000015)\r\n#define ADC_TripleMode_RegSimult ((uint32_t)0x00000016)\r\n#define ADC_TripleMode_Interl ((uint32_t)0x00000017)\r\n#define ADC_TripleMode_AlterTrig ((uint32_t)0x00000019)\r\n#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \\\r\n ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \\\r\n ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \\\r\n ((MODE) == ADC_DualMode_InjecSimult) || \\\r\n ((MODE) == ADC_DualMode_RegSimult) || \\\r\n ((MODE) == ADC_DualMode_Interl) || \\\r\n ((MODE) == ADC_DualMode_AlterTrig) || \\\r\n ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \\\r\n ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \\\r\n ((MODE) == ADC_TripleMode_InjecSimult) || \\\r\n ((MODE) == ADC_TripleMode_RegSimult) || \\\r\n ((MODE) == ADC_TripleMode_Interl) || \\\r\n ((MODE) == ADC_TripleMode_AlterTrig))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup ADC_Prescaler \r\n * @{\r\n */ \r\n#define ADC_Prescaler_Div2 ((uint32_t)0x00000000)\r\n#define ADC_Prescaler_Div4 ((uint32_t)0x00010000)\r\n#define ADC_Prescaler_Div6 ((uint32_t)0x00020000)\r\n#define ADC_Prescaler_Div8 ((uint32_t)0x00030000)\r\n#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \\\r\n ((PRESCALER) == ADC_Prescaler_Div4) || \\\r\n ((PRESCALER) == ADC_Prescaler_Div6) || \\\r\n ((PRESCALER) == ADC_Prescaler_Div8))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode \r\n * @{\r\n */ \r\n#define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /* DMA mode disabled */\r\n#define ADC_DMAAccessMode_1 ((uint32_t)0x00004000) /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/\r\n#define ADC_DMAAccessMode_2 ((uint32_t)0x00008000) /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/\r\n#define ADC_DMAAccessMode_3 ((uint32_t)0x0000C000) /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */\r\n#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \\\r\n ((MODE) == ADC_DMAAccessMode_1) || \\\r\n ((MODE) == ADC_DMAAccessMode_2) || \\\r\n ((MODE) == ADC_DMAAccessMode_3))\r\n \r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup ADC_delay_between_2_sampling_phases \r\n * @{\r\n */ \r\n#define ADC_TwoSamplingDelay_5Cycles ((uint32_t)0x00000000)\r\n#define ADC_TwoSamplingDelay_6Cycles ((uint32_t)0x00000100)\r\n#define ADC_TwoSamplingDelay_7Cycles ((uint32_t)0x00000200)\r\n#define ADC_TwoSamplingDelay_8Cycles ((uint32_t)0x00000300)\r\n#define ADC_TwoSamplingDelay_9Cycles ((uint32_t)0x00000400)\r\n#define ADC_TwoSamplingDelay_10Cycles ((uint32_t)0x00000500)\r\n#define ADC_TwoSamplingDelay_11Cycles ((uint32_t)0x00000600)\r\n#define ADC_TwoSamplingDelay_12Cycles ((uint32_t)0x00000700)\r\n#define ADC_TwoSamplingDelay_13Cycles ((uint32_t)0x00000800)\r\n#define ADC_TwoSamplingDelay_14Cycles ((uint32_t)0x00000900)\r\n#define ADC_TwoSamplingDelay_15Cycles ((uint32_t)0x00000A00)\r\n#define ADC_TwoSamplingDelay_16Cycles ((uint32_t)0x00000B00)\r\n#define ADC_TwoSamplingDelay_17Cycles ((uint32_t)0x00000C00)\r\n#define ADC_TwoSamplingDelay_18Cycles ((uint32_t)0x00000D00)\r\n#define ADC_TwoSamplingDelay_19Cycles ((uint32_t)0x00000E00)\r\n#define ADC_TwoSamplingDelay_20Cycles ((uint32_t)0x00000F00)\r\n#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \\\r\n ((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \\\r\n ((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \\\r\n ((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \\\r\n ((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \\\r\n ((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \\\r\n ((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \\\r\n ((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \\\r\n ((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \\\r\n ((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \\\r\n ((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \\\r\n ((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \\\r\n ((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \\\r\n ((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \\\r\n ((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \\\r\n ((DELAY) == ADC_TwoSamplingDelay_20Cycles))\r\n \r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup ADC_resolution \r\n * @{\r\n */ \r\n#define ADC_Resolution_12b ((uint32_t)0x00000000)\r\n#define ADC_Resolution_10b ((uint32_t)0x01000000)\r\n#define ADC_Resolution_8b ((uint32_t)0x02000000)\r\n#define ADC_Resolution_6b ((uint32_t)0x03000000)\r\n#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \\\r\n ((RESOLUTION) == ADC_Resolution_10b) || \\\r\n ((RESOLUTION) == ADC_Resolution_8b) || \\\r\n ((RESOLUTION) == ADC_Resolution_6b))\r\n \r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion \r\n * @{\r\n */ \r\n#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000)\r\n#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000)\r\n#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000)\r\n#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000)\r\n#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \\\r\n ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \\\r\n ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \\\r\n ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion \r\n * @{\r\n */ \r\n#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000)\r\n#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x01000000)\r\n#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x02000000)\r\n#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000)\r\n#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x04000000)\r\n#define ADC_ExternalTrigConv_T2_CC4 ((uint32_t)0x05000000)\r\n#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000)\r\n#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000)\r\n#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x08000000)\r\n#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x09000000)\r\n#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x0A000000)\r\n#define ADC_ExternalTrigConv_T5_CC2 ((uint32_t)0x0B000000)\r\n#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x0C000000)\r\n#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x0D000000)\r\n#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x0E000000)\r\n#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000)\r\n#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \\\r\n ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \\\r\n ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \\\r\n ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \\\r\n ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \\\r\n ((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \\\r\n ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \\\r\n ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \\\r\n ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \\\r\n ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \\\r\n ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \\\r\n ((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \\\r\n ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \\\r\n ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \\\r\n ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \\\r\n ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup ADC_data_align \r\n * @{\r\n */ \r\n#define ADC_DataAlign_Right ((uint32_t)0x00000000)\r\n#define ADC_DataAlign_Left ((uint32_t)0x00000800)\r\n#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \\\r\n ((ALIGN) == ADC_DataAlign_Left))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup ADC_channels \r\n * @{\r\n */ \r\n#define ADC_Channel_0 ((uint8_t)0x00)\r\n#define ADC_Channel_1 ((uint8_t)0x01)\r\n#define ADC_Channel_2 ((uint8_t)0x02)\r\n#define ADC_Channel_3 ((uint8_t)0x03)\r\n#define ADC_Channel_4 ((uint8_t)0x04)\r\n#define ADC_Channel_5 ((uint8_t)0x05)\r\n#define ADC_Channel_6 ((uint8_t)0x06)\r\n#define ADC_Channel_7 ((uint8_t)0x07)\r\n#define ADC_Channel_8 ((uint8_t)0x08)\r\n#define ADC_Channel_9 ((uint8_t)0x09)\r\n#define ADC_Channel_10 ((uint8_t)0x0A)\r\n#define ADC_Channel_11 ((uint8_t)0x0B)\r\n#define ADC_Channel_12 ((uint8_t)0x0C)\r\n#define ADC_Channel_13 ((uint8_t)0x0D)\r\n#define ADC_Channel_14 ((uint8_t)0x0E)\r\n#define ADC_Channel_15 ((uint8_t)0x0F)\r\n#define ADC_Channel_16 ((uint8_t)0x10)\r\n#define ADC_Channel_17 ((uint8_t)0x11)\r\n#define ADC_Channel_18 ((uint8_t)0x12)\r\n\r\n#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)\r\n#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)\r\n#define ADC_Channel_Vbat ((uint8_t)ADC_Channel_18)\r\n\r\n#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \\\r\n ((CHANNEL) == ADC_Channel_1) || \\\r\n ((CHANNEL) == ADC_Channel_2) || \\\r\n ((CHANNEL) == ADC_Channel_3) || \\\r\n ((CHANNEL) == ADC_Channel_4) || \\\r\n ((CHANNEL) == ADC_Channel_5) || \\\r\n ((CHANNEL) == ADC_Channel_6) || \\\r\n ((CHANNEL) == ADC_Channel_7) || \\\r\n ((CHANNEL) == ADC_Channel_8) || \\\r\n ((CHANNEL) == ADC_Channel_9) || \\\r\n ((CHANNEL) == ADC_Channel_10) || \\\r\n ((CHANNEL) == ADC_Channel_11) || \\\r\n ((CHANNEL) == ADC_Channel_12) || \\\r\n ((CHANNEL) == ADC_Channel_13) || \\\r\n ((CHANNEL) == ADC_Channel_14) || \\\r\n ((CHANNEL) == ADC_Channel_15) || \\\r\n ((CHANNEL) == ADC_Channel_16) || \\\r\n ((CHANNEL) == ADC_Channel_17) || \\\r\n ((CHANNEL) == ADC_Channel_18))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup ADC_sampling_times \r\n * @{\r\n */ \r\n#define ADC_SampleTime_3Cycles ((uint8_t)0x00)\r\n#define ADC_SampleTime_15Cycles ((uint8_t)0x01)\r\n#define ADC_SampleTime_28Cycles ((uint8_t)0x02)\r\n#define ADC_SampleTime_56Cycles ((uint8_t)0x03)\r\n#define ADC_SampleTime_84Cycles ((uint8_t)0x04)\r\n#define ADC_SampleTime_112Cycles ((uint8_t)0x05)\r\n#define ADC_SampleTime_144Cycles ((uint8_t)0x06)\r\n#define ADC_SampleTime_480Cycles ((uint8_t)0x07)\r\n#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \\\r\n ((TIME) == ADC_SampleTime_15Cycles) || \\\r\n ((TIME) == ADC_SampleTime_28Cycles) || \\\r\n ((TIME) == ADC_SampleTime_56Cycles) || \\\r\n ((TIME) == ADC_SampleTime_84Cycles) || \\\r\n ((TIME) == ADC_SampleTime_112Cycles) || \\\r\n ((TIME) == ADC_SampleTime_144Cycles) || \\\r\n ((TIME) == ADC_SampleTime_480Cycles))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion \r\n * @{\r\n */ \r\n#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000)\r\n#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000)\r\n#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000)\r\n#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)\r\n#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \\\r\n ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \\\r\n ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \\\r\n ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))\r\n \r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion \r\n * @{\r\n */ \r\n#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00000000)\r\n#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00010000)\r\n#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00020000)\r\n#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00030000)\r\n#define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00040000)\r\n#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00050000)\r\n#define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000)\r\n#define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000)\r\n#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000)\r\n#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00090000)\r\n#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x000A0000)\r\n#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x000B0000)\r\n#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x000C0000)\r\n#define ADC_ExternalTrigInjecConv_T8_CC3 ((uint32_t)0x000D0000)\r\n#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x000E0000)\r\n#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000)\r\n#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \\\r\n ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \\\r\n ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \\\r\n ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \\\r\n ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \\\r\n ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \\\r\n ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \\\r\n ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \\\r\n ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \\\r\n ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \\\r\n ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \\\r\n ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \\\r\n ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \\\r\n ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \\\r\n ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \\\r\n ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup ADC_injected_channel_selection \r\n * @{\r\n */ \r\n#define ADC_InjectedChannel_1 ((uint8_t)0x14)\r\n#define ADC_InjectedChannel_2 ((uint8_t)0x18)\r\n#define ADC_InjectedChannel_3 ((uint8_t)0x1C)\r\n#define ADC_InjectedChannel_4 ((uint8_t)0x20)\r\n#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \\\r\n ((CHANNEL) == ADC_InjectedChannel_2) || \\\r\n ((CHANNEL) == ADC_InjectedChannel_3) || \\\r\n ((CHANNEL) == ADC_InjectedChannel_4))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup ADC_analog_watchdog_selection \r\n * @{\r\n */ \r\n#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)\r\n#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)\r\n#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)\r\n#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)\r\n#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)\r\n#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)\r\n#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)\r\n#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \\\r\n ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \\\r\n ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \\\r\n ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \\\r\n ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \\\r\n ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \\\r\n ((WATCHDOG) == ADC_AnalogWatchdog_None))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup ADC_interrupts_definition \r\n * @{\r\n */ \r\n#define ADC_IT_EOC ((uint16_t)0x0205) \r\n#define ADC_IT_AWD ((uint16_t)0x0106) \r\n#define ADC_IT_JEOC ((uint16_t)0x0407) \r\n#define ADC_IT_OVR ((uint16_t)0x201A) \r\n#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \\\r\n ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) \r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup ADC_flags_definition \r\n * @{\r\n */ \r\n#define ADC_FLAG_AWD ((uint8_t)0x01)\r\n#define ADC_FLAG_EOC ((uint8_t)0x02)\r\n#define ADC_FLAG_JEOC ((uint8_t)0x04)\r\n#define ADC_FLAG_JSTRT ((uint8_t)0x08)\r\n#define ADC_FLAG_STRT ((uint8_t)0x10)\r\n#define ADC_FLAG_OVR ((uint8_t)0x20) \r\n \r\n#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00)) \r\n#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \\\r\n ((FLAG) == ADC_FLAG_EOC) || \\\r\n ((FLAG) == ADC_FLAG_JEOC) || \\\r\n ((FLAG)== ADC_FLAG_JSTRT) || \\\r\n ((FLAG) == ADC_FLAG_STRT) || \\\r\n ((FLAG)== ADC_FLAG_OVR)) \r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup ADC_thresholds \r\n * @{\r\n */ \r\n#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup ADC_injected_offset \r\n * @{\r\n */ \r\n#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup ADC_injected_length \r\n * @{\r\n */ \r\n#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup ADC_injected_rank \r\n * @{\r\n */ \r\n#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup ADC_regular_length \r\n * @{\r\n */ \r\n#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup ADC_regular_rank \r\n * @{\r\n */ \r\n#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup ADC_regular_discontinuous_mode_number \r\n * @{\r\n */ \r\n#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/ \r\n\r\n/* Function used to set the ADC configuration to the default reset state *****/ \r\nvoid ADC_DeInit(void);\r\n\r\n/* Initialization and Configuration functions *********************************/\r\nvoid ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);\r\nvoid ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);\r\nvoid ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);\r\nvoid ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);\r\nvoid ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r\n\r\n/* Analog Watchdog configuration functions ************************************/\r\nvoid ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);\r\nvoid ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);\r\nvoid ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);\r\n\r\n/* Temperature Sensor, Vrefint and VBAT management functions ******************/\r\nvoid ADC_TempSensorVrefintCmd(FunctionalState NewState);\r\nvoid ADC_VBATCmd(FunctionalState NewState);\r\n\r\n/* Regular Channels Configuration functions ***********************************/\r\nvoid ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);\r\nvoid ADC_SoftwareStartConv(ADC_TypeDef* ADCx);\r\nFlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);\r\nvoid ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r\nvoid ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r\nvoid ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);\r\nvoid ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r\nuint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);\r\nuint32_t ADC_GetMultiModeConversionValue(void);\r\n\r\n/* Regular Channels DMA Configuration functions *******************************/\r\nvoid ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r\nvoid ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r\nvoid ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState);\r\n\r\n/* Injected channels Configuration functions **********************************/\r\nvoid ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);\r\nvoid ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);\r\nvoid ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);\r\nvoid ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);\r\nvoid ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);\r\nvoid ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);\r\nFlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);\r\nvoid ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r\nvoid ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r\nuint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);\r\n\r\n/* Interrupts and flags management functions **********************************/\r\nvoid ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);\r\nFlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);\r\nvoid ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);\r\nITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);\r\nvoid ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /*__STM32F4xx_ADC_H */\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_can.h", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_can.h\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file contains all the functions prototypes for the CAN firmware \r\n * library.\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F4xx_CAN_H\r\n#define __STM32F4xx_CAN_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @addtogroup CAN\r\n * @{\r\n */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n\r\n#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \\\r\n ((PERIPH) == CAN2))\r\n\r\n/** \r\n * @brief CAN init structure definition\r\n */\r\ntypedef struct\r\n{\r\n uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. \r\n It ranges from 1 to 1024. */\r\n \r\n uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.\r\n This parameter can be a value of @ref CAN_operating_mode */\r\n\r\n uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta \r\n the CAN hardware is allowed to lengthen or \r\n shorten a bit to perform resynchronization.\r\n This parameter can be a value of @ref CAN_synchronisation_jump_width */\r\n\r\n uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit \r\n Segment 1. This parameter can be a value of \r\n @ref CAN_time_quantum_in_bit_segment_1 */\r\n\r\n uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2.\r\n This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */\r\n \r\n FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode.\r\n This parameter can be set either to ENABLE or DISABLE. */\r\n \r\n FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management.\r\n This parameter can be set either to ENABLE or DISABLE. */\r\n\r\n FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. \r\n This parameter can be set either to ENABLE or DISABLE. */\r\n\r\n FunctionalState CAN_NART; /*!< Enable or disable the non-automatic retransmission mode.\r\n This parameter can be set either to ENABLE or DISABLE. */\r\n\r\n FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode.\r\n This parameter can be set either to ENABLE or DISABLE. */\r\n\r\n FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority.\r\n This parameter can be set either to ENABLE or DISABLE. */\r\n} CAN_InitTypeDef;\r\n\r\n/** \r\n * @brief CAN filter init structure definition\r\n */\r\ntypedef struct\r\n{\r\n uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit\r\n configuration, first one for a 16-bit configuration).\r\n This parameter can be a value between 0x0000 and 0xFFFF */\r\n\r\n uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit\r\n configuration, second one for a 16-bit configuration).\r\n This parameter can be a value between 0x0000 and 0xFFFF */\r\n\r\n uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,\r\n according to the mode (MSBs for a 32-bit configuration,\r\n first one for a 16-bit configuration).\r\n This parameter can be a value between 0x0000 and 0xFFFF */\r\n\r\n uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,\r\n according to the mode (LSBs for a 32-bit configuration,\r\n second one for a 16-bit configuration).\r\n This parameter can be a value between 0x0000 and 0xFFFF */\r\n\r\n uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.\r\n This parameter can be a value of @ref CAN_filter_FIFO */\r\n \r\n uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */\r\n\r\n uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.\r\n This parameter can be a value of @ref CAN_filter_mode */\r\n\r\n uint8_t CAN_FilterScale; /*!< Specifies the filter scale.\r\n This parameter can be a value of @ref CAN_filter_scale */\r\n\r\n FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.\r\n This parameter can be set either to ENABLE or DISABLE. */\r\n} CAN_FilterInitTypeDef;\r\n\r\n/** \r\n * @brief CAN Tx message structure definition \r\n */\r\ntypedef struct\r\n{\r\n uint32_t StdId; /*!< Specifies the standard identifier.\r\n This parameter can be a value between 0 to 0x7FF. */\r\n\r\n uint32_t ExtId; /*!< Specifies the extended identifier.\r\n This parameter can be a value between 0 to 0x1FFFFFFF. */\r\n\r\n uint8_t IDE; /*!< Specifies the type of identifier for the message that \r\n will be transmitted. This parameter can be a value \r\n of @ref CAN_identifier_type */\r\n\r\n uint8_t RTR; /*!< Specifies the type of frame for the message that will \r\n be transmitted. This parameter can be a value of \r\n @ref CAN_remote_transmission_request */\r\n\r\n uint8_t DLC; /*!< Specifies the length of the frame that will be \r\n transmitted. This parameter can be a value between \r\n 0 to 8 */\r\n\r\n uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 \r\n to 0xFF. */\r\n} CanTxMsg;\r\n\r\n/** \r\n * @brief CAN Rx message structure definition \r\n */\r\ntypedef struct\r\n{\r\n uint32_t StdId; /*!< Specifies the standard identifier.\r\n This parameter can be a value between 0 to 0x7FF. */\r\n\r\n uint32_t ExtId; /*!< Specifies the extended identifier.\r\n This parameter can be a value between 0 to 0x1FFFFFFF. */\r\n\r\n uint8_t IDE; /*!< Specifies the type of identifier for the message that \r\n will be received. This parameter can be a value of \r\n @ref CAN_identifier_type */\r\n\r\n uint8_t RTR; /*!< Specifies the type of frame for the received message.\r\n This parameter can be a value of \r\n @ref CAN_remote_transmission_request */\r\n\r\n uint8_t DLC; /*!< Specifies the length of the frame that will be received.\r\n This parameter can be a value between 0 to 8 */\r\n\r\n uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to \r\n 0xFF. */\r\n\r\n uint8_t FMI; /*!< Specifies the index of the filter the message stored in \r\n the mailbox passes through. This parameter can be a \r\n value between 0 to 0xFF */\r\n} CanRxMsg;\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup CAN_Exported_Constants\r\n * @{\r\n */\r\n\r\n/** @defgroup CAN_InitStatus \r\n * @{\r\n */\r\n\r\n#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */\r\n#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */\r\n\r\n\r\n/* Legacy defines */\r\n#define CANINITFAILED CAN_InitStatus_Failed\r\n#define CANINITOK CAN_InitStatus_Success\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup CAN_operating_mode \r\n * @{\r\n */\r\n\r\n#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */\r\n#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */\r\n#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */\r\n#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */\r\n\r\n#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \\\r\n ((MODE) == CAN_Mode_LoopBack)|| \\\r\n ((MODE) == CAN_Mode_Silent) || \\\r\n ((MODE) == CAN_Mode_Silent_LoopBack))\r\n/**\r\n * @}\r\n */\r\n\r\n\r\n /**\r\n * @defgroup CAN_operating_mode \r\n * @{\r\n */ \r\n#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */\r\n#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */\r\n#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */\r\n\r\n\r\n#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\\\r\n ((MODE) == CAN_OperatingMode_Normal)|| \\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((MODE) == CAN_OperatingMode_Sleep))\r\n/**\r\n * @}\r\n */\r\n \r\n/**\r\n * @defgroup CAN_operating_mode_status\r\n * @{\r\n */ \r\n\r\n#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */\r\n#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup CAN_synchronisation_jump_width \r\n * @{\r\n */\r\n#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */\r\n#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */\r\n#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */\r\n#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */\r\n\r\n#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \\\r\n ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup CAN_time_quantum_in_bit_segment_1 \r\n * @{\r\n */\r\n#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */\r\n#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */\r\n#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */\r\n#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */\r\n#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */\r\n#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */\r\n#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */\r\n#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */\r\n#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */\r\n#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */\r\n#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */\r\n#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */\r\n#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */\r\n#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */\r\n#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */\r\n#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */\r\n\r\n#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup CAN_time_quantum_in_bit_segment_2 \r\n * @{\r\n */\r\n#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */\r\n#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */\r\n#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */\r\n#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */\r\n#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */\r\n#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */\r\n#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */\r\n#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */\r\n\r\n#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup CAN_clock_prescaler \r\n * @{\r\n */\r\n#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup CAN_filter_number \r\n * @{\r\n */\r\n#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup CAN_filter_mode \r\n * @{\r\n */\r\n#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */\r\n#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */\r\n\r\n#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \\\r\n ((MODE) == CAN_FilterMode_IdList))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup CAN_filter_scale \r\n * @{\r\n */\r\n#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */\r\n#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */\r\n\r\n#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \\\r\n ((SCALE) == CAN_FilterScale_32bit))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup CAN_filter_FIFO\r\n * @{\r\n */\r\n#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */\r\n#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */\r\n#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \\\r\n ((FIFO) == CAN_FilterFIFO1))\r\n\r\n/* Legacy defines */\r\n#define CAN_FilterFIFO0 CAN_Filter_FIFO0\r\n#define CAN_FilterFIFO1 CAN_Filter_FIFO1\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup CAN_Start_bank_filter_for_slave_CAN \r\n * @{\r\n */\r\n#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup CAN_Tx \r\n * @{\r\n */\r\n#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))\r\n#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))\r\n#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))\r\n#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup CAN_identifier_type \r\n * @{\r\n */\r\n#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */\r\n#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */\r\n#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \\\r\n ((IDTYPE) == CAN_Id_Extended))\r\n\r\n/* Legacy defines */\r\n#define CAN_ID_STD CAN_Id_Standard \r\n#define CAN_ID_EXT CAN_Id_Extended\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup CAN_remote_transmission_request \r\n * @{\r\n */\r\n#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */\r\n#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */\r\n#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))\r\n\r\n/* Legacy defines */\r\n#define CAN_RTR_DATA CAN_RTR_Data \r\n#define CAN_RTR_REMOTE CAN_RTR_Remote\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup CAN_transmit_constants \r\n * @{\r\n */\r\n#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */\r\n#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */\r\n#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */\r\n#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide \r\n an empty mailbox */\r\n/* Legacy defines */\t\r\n#define CANTXFAILED CAN_TxStatus_Failed\r\n#define CANTXOK CAN_TxStatus_Ok\r\n#define CANTXPENDING CAN_TxStatus_Pending\r\n#define CAN_NO_MB CAN_TxStatus_NoMailBox\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup CAN_receive_FIFO_number_constants \r\n * @{\r\n */\r\n#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */\r\n#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */\r\n\r\n#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup CAN_sleep_constants \r\n * @{\r\n */\r\n#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */\r\n#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */\r\n\r\n/* Legacy defines */\t\r\n#define CANSLEEPFAILED CAN_Sleep_Failed\r\n#define CANSLEEPOK CAN_Sleep_Ok\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup CAN_wake_up_constants \r\n * @{\r\n */\r\n#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */\r\n#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */\r\n\r\n/* Legacy defines */\r\n#define CANWAKEUPFAILED CAN_WakeUp_Failed \r\n#define CANWAKEUPOK CAN_WakeUp_Ok \r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @defgroup CAN_Error_Code_constants\r\n * @{\r\n */ \r\n#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */ \r\n#define\tCAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */ \r\n#define\tCAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */ \r\n#define\tCAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */ \r\n#define\tCAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ \r\n#define\tCAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */ \r\n#define\tCAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */ \r\n#define\tCAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */ \r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup CAN_flags \r\n * @{\r\n */\r\n/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()\r\n and CAN_ClearFlag() functions. */\r\n/* If the flag is 0x1XXXXXXX, it means that it can only be used with \r\n CAN_GetFlagStatus() function. */\r\n\r\n/* Transmit Flags */\r\n#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */\r\n#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */\r\n#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */\r\n\r\n/* Receive Flags */\r\n#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */\r\n#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */\r\n#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */\r\n#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */\r\n#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */\r\n#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */\r\n\r\n/* Operating Mode Flags */\r\n#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */\r\n#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */\r\n/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. \r\n In this case the SLAK bit can be polled.*/\r\n\r\n/* Error Flags */\r\n#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */\r\n#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */\r\n#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */\r\n#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */\r\n\r\n#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \\\r\n ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \\\r\n ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \\\r\n ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \\\r\n ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \\\r\n ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \\\r\n ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \\\r\n ((FLAG) == CAN_FLAG_SLAK ))\r\n\r\n#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \\\r\n ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \\\r\n ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\\\r\n ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \\\r\n ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))\r\n/**\r\n * @}\r\n */\r\n\r\n \r\n/** @defgroup CAN_interrupts \r\n * @{\r\n */ \r\n#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/\r\n\r\n/* Receive Interrupts */\r\n#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/\r\n#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/\r\n#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/\r\n#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/\r\n#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/\r\n#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/\r\n\r\n/* Operating Mode Interrupts */\r\n#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/\r\n#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/\r\n\r\n/* Error Interrupts */\r\n#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/\r\n#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/\r\n#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/\r\n#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/\r\n#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/\r\n\r\n/* Flags named as Interrupts : kept only for FW compatibility */\r\n#define CAN_IT_RQCP0 CAN_IT_TME\r\n#define CAN_IT_RQCP1 CAN_IT_TME\r\n#define CAN_IT_RQCP2 CAN_IT_TME\r\n\r\n\r\n#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\\\r\n ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\\\r\n ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\\\r\n ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\\\r\n ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\\\r\n ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\\\r\n ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))\r\n\r\n#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\\\r\n ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\\\r\n ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\\\r\n ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\\\r\n ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\\\r\n ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/ \r\n\r\n/* Function used to set the CAN configuration to the default reset state *****/ \r\nvoid CAN_DeInit(CAN_TypeDef* CANx);\r\n\r\n/* Initialization and Configuration functions *********************************/ \r\nuint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);\r\nvoid CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);\r\nvoid CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);\r\nvoid CAN_SlaveStartBank(uint8_t CAN_BankNumber); \r\nvoid CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);\r\nvoid CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);\r\n\r\n/* CAN Frames Transmission functions ******************************************/\r\nuint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);\r\nuint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);\r\nvoid CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);\r\n\r\n/* CAN Frames Reception functions *********************************************/\r\nvoid CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);\r\nvoid CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);\r\nuint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);\r\n\r\n/* Operation modes functions **************************************************/\r\nuint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);\r\nuint8_t CAN_Sleep(CAN_TypeDef* CANx);\r\nuint8_t CAN_WakeUp(CAN_TypeDef* CANx);\r\n\r\n/* CAN Bus Error management functions *****************************************/\r\nuint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);\r\nuint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);\r\nuint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);\r\n\r\n/* Interrupts and flags management functions **********************************/\r\nvoid CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);\r\nFlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);\r\nvoid CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);\r\nITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);\r\nvoid CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F4xx_CAN_H */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_crc.h", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_crc.h\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file contains all the functions prototypes for the CRC firmware \r\n * library.\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F4xx_CRC_H\r\n#define __STM32F4xx_CRC_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @addtogroup CRC\r\n * @{\r\n */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup CRC_Exported_Constants\r\n * @{\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/ \r\n\r\nvoid CRC_ResetDR(void);\r\nuint32_t CRC_CalcCRC(uint32_t Data);\r\nuint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);\r\nuint32_t CRC_GetCRC(void);\r\nvoid CRC_SetIDRegister(uint8_t IDValue);\r\nuint8_t CRC_GetIDRegister(void);\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F4xx_CRC_H */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_cryp.h", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_cryp.h\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file contains all the functions prototypes for the Cryptographic\r\n * processor(CRYP) firmware library.\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F4xx_CRYP_H\r\n#define __STM32F4xx_CRYP_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @addtogroup CRYP\r\n * @{\r\n */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n\r\n/** \r\n * @brief CRYP Init structure definition \r\n */ \r\ntypedef struct\r\n{\r\n uint16_t CRYP_AlgoDir; /*!< Encrypt or Decrypt. This parameter can be a \r\n value of @ref CRYP_Algorithm_Direction */\r\n uint16_t CRYP_AlgoMode; /*!< TDES-ECB, TDES-CBC, DES-ECB, DES-CBC, AES-ECB, \r\n AES-CBC, AES-CTR, AES-Key. This parameter can be\r\n a value of @ref CRYP_Algorithm_Mode */\r\n uint16_t CRYP_DataType; /*!< 32-bit data, 16-bit data, bit data or bit-string.\r\n This parameter can be a value of @ref CRYP_Data_Type */ \r\n uint16_t CRYP_KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit \r\n key length. This parameter can be a value of \r\n @ref CRYP_Key_Size_for_AES_only */\r\n}CRYP_InitTypeDef;\r\n\r\n/** \r\n * @brief CRYP Key(s) structure definition \r\n */ \r\ntypedef struct\r\n{\r\n uint32_t CRYP_Key0Left; /*!< Key 0 Left */\r\n uint32_t CRYP_Key0Right; /*!< Key 0 Right */\r\n uint32_t CRYP_Key1Left; /*!< Key 1 left */\r\n uint32_t CRYP_Key1Right; /*!< Key 1 Right */\r\n uint32_t CRYP_Key2Left; /*!< Key 2 left */\r\n uint32_t CRYP_Key2Right; /*!< Key 2 Right */\r\n uint32_t CRYP_Key3Left; /*!< Key 3 left */\r\n uint32_t CRYP_Key3Right; /*!< Key 3 Right */\r\n}CRYP_KeyInitTypeDef;\r\n/** \r\n * @brief CRYP Initialization Vectors (IV) structure definition \r\n */ \r\ntypedef struct\r\n{\r\n uint32_t CRYP_IV0Left; /*!< Init Vector 0 Left */\r\n uint32_t CRYP_IV0Right; /*!< Init Vector 0 Right */\r\n uint32_t CRYP_IV1Left; /*!< Init Vector 1 left */\r\n uint32_t CRYP_IV1Right; /*!< Init Vector 1 Right */\r\n}CRYP_IVInitTypeDef;\r\n\r\n/** \r\n * @brief CRYP context swapping structure definition \r\n */ \r\ntypedef struct\r\n{\r\n /*!< Configuration */\r\n uint32_t CR_bits9to2;\r\n /*!< KEY */\r\n uint32_t CRYP_IV0LR;\r\n uint32_t CRYP_IV0RR;\r\n uint32_t CRYP_IV1LR;\r\n uint32_t CRYP_IV1RR;\r\n /*!< IV */\r\n uint32_t CRYP_K0LR;\r\n uint32_t CRYP_K0RR;\r\n uint32_t CRYP_K1LR;\r\n uint32_t CRYP_K1RR;\r\n uint32_t CRYP_K2LR;\r\n uint32_t CRYP_K2RR;\r\n uint32_t CRYP_K3LR;\r\n uint32_t CRYP_K3RR;\r\n}CRYP_Context;\r\n\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup CRYP_Exported_Constants\r\n * @{\r\n */\r\n\r\n/** @defgroup CRYP_Algorithm_Direction \r\n * @{\r\n */\r\n#define CRYP_AlgoDir_Encrypt ((uint16_t)0x0000)\r\n#define CRYP_AlgoDir_Decrypt ((uint16_t)0x0004)\r\n#define IS_CRYP_ALGODIR(ALGODIR) (((ALGODIR) == CRYP_AlgoDir_Encrypt) || \\\r\n ((ALGODIR) == CRYP_AlgoDir_Decrypt))\r\n\r\n/**\r\n * @}\r\n */ \r\n \r\n/** @defgroup CRYP_Algorithm_Mode \r\n * @{\r\n */\r\n\r\n/*!< TDES Modes */\r\n#define CRYP_AlgoMode_TDES_ECB ((uint16_t)0x0000)\r\n#define CRYP_AlgoMode_TDES_CBC ((uint16_t)0x0008)\r\n\r\n/*!< DES Modes */\r\n#define CRYP_AlgoMode_DES_ECB ((uint16_t)0x0010)\r\n#define CRYP_AlgoMode_DES_CBC ((uint16_t)0x0018)\r\n\r\n/*!< AES Modes */\r\n#define CRYP_AlgoMode_AES_ECB ((uint16_t)0x0020)\r\n#define CRYP_AlgoMode_AES_CBC ((uint16_t)0x0028)\r\n#define CRYP_AlgoMode_AES_CTR ((uint16_t)0x0030)\r\n#define CRYP_AlgoMode_AES_Key ((uint16_t)0x0038)\r\n\r\n#define IS_CRYP_ALGOMODE(ALGOMODE) (((ALGOMODE) == CRYP_AlgoMode_TDES_ECB) || \\\r\n ((ALGOMODE) == CRYP_AlgoMode_TDES_CBC)|| \\\r\n ((ALGOMODE) == CRYP_AlgoMode_DES_ECB)|| \\\r\n ((ALGOMODE) == CRYP_AlgoMode_DES_CBC) || \\\r\n ((ALGOMODE) == CRYP_AlgoMode_AES_ECB) || \\\r\n ((ALGOMODE) == CRYP_AlgoMode_AES_CBC) || \\\r\n ((ALGOMODE) == CRYP_AlgoMode_AES_CTR) || \\\r\n ((ALGOMODE) == CRYP_AlgoMode_AES_Key))\r\n/**\r\n * @}\r\n */ \r\n \r\n/** @defgroup CRYP_Data_Type \r\n * @{\r\n */\r\n#define CRYP_DataType_32b ((uint16_t)0x0000)\r\n#define CRYP_DataType_16b ((uint16_t)0x0040)\r\n#define CRYP_DataType_8b ((uint16_t)0x0080)\r\n#define CRYP_DataType_1b ((uint16_t)0x00C0)\r\n#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DataType_32b) || \\\r\n ((DATATYPE) == CRYP_DataType_16b)|| \\\r\n ((DATATYPE) == CRYP_DataType_8b)|| \\\r\n ((DATATYPE) == CRYP_DataType_1b)) \r\n/**\r\n * @}\r\n */\r\n \r\n/** @defgroup CRYP_Key_Size_for_AES_only \r\n * @{\r\n */\r\n#define CRYP_KeySize_128b ((uint16_t)0x0000)\r\n#define CRYP_KeySize_192b ((uint16_t)0x0100)\r\n#define CRYP_KeySize_256b ((uint16_t)0x0200)\r\n#define IS_CRYP_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KeySize_128b)|| \\\r\n ((KEYSIZE) == CRYP_KeySize_192b)|| \\\r\n ((KEYSIZE) == CRYP_KeySize_256b))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup CRYP_flags_definition \r\n * @{\r\n */\r\n#define CRYP_FLAG_BUSY ((uint8_t)0x10) /*!< The CRYP core is currently \r\n processing a block of data \r\n or a key preparation (for \r\n AES decryption). */\r\n#define CRYP_FLAG_IFEM ((uint8_t)0x01) /*!< Input Fifo Empty */\r\n#define CRYP_FLAG_IFNF ((uint8_t)0x02) /*!< Input Fifo is Not Full */\r\n#define CRYP_FLAG_INRIS ((uint8_t)0x22) /*!< Raw interrupt pending */\r\n#define CRYP_FLAG_OFNE ((uint8_t)0x04) /*!< Input Fifo service raw \r\n interrupt status */\r\n#define CRYP_FLAG_OFFU ((uint8_t)0x08) /*!< Output Fifo is Full */\r\n#define CRYP_FLAG_OUTRIS ((uint8_t)0x21) /*!< Output Fifo service raw \r\n interrupt status */\r\n\r\n#define IS_CRYP_GET_FLAG(FLAG) (((FLAG) == CRYP_FLAG_IFEM) || \\\r\n ((FLAG) == CRYP_FLAG_IFNF) || \\\r\n ((FLAG) == CRYP_FLAG_OFNE) || \\\r\n ((FLAG) == CRYP_FLAG_OFFU) || \\\r\n ((FLAG) == CRYP_FLAG_BUSY) || \\\r\n ((FLAG) == CRYP_FLAG_OUTRIS)|| \\\r\n ((FLAG) == CRYP_FLAG_INRIS))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup CRYP_interrupts_definition \r\n * @{\r\n */\r\n#define CRYP_IT_INI ((uint8_t)0x01) /*!< IN Fifo Interrupt */\r\n#define CRYP_IT_OUTI ((uint8_t)0x02) /*!< OUT Fifo Interrupt */\r\n#define IS_CRYP_CONFIG_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00))\r\n#define IS_CRYP_GET_IT(IT) (((IT) == CRYP_IT_INI) || ((IT) == CRYP_IT_OUTI))\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup CRYP_Encryption_Decryption_modes_definition \r\n * @{\r\n */\r\n#define MODE_ENCRYPT ((uint8_t)0x01)\r\n#define MODE_DECRYPT ((uint8_t)0x00)\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup CRYP_DMA_transfer_requests \r\n * @{\r\n */\r\n#define CRYP_DMAReq_DataIN ((uint8_t)0x01)\r\n#define CRYP_DMAReq_DataOUT ((uint8_t)0x02)\r\n#define IS_CRYP_DMAREQ(DMAREQ) ((((DMAREQ) & (uint8_t)0xFC) == 0x00) && ((DMAREQ) != 0x00))\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/* Function used to set the CRYP configuration to the default reset state ****/\r\nvoid CRYP_DeInit(void);\r\n\r\n/* CRYP Initialization and Configuration functions ****************************/\r\nvoid CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct);\r\nvoid CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct);\r\nvoid CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);\r\nvoid CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);\r\nvoid CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct);\r\nvoid CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct);\r\nvoid CRYP_Cmd(FunctionalState NewState);\r\n\r\n/* CRYP Data processing functions *********************************************/\r\nvoid CRYP_DataIn(uint32_t Data);\r\nuint32_t CRYP_DataOut(void);\r\nvoid CRYP_FIFOFlush(void);\r\n\r\n/* CRYP Context swapping functions ********************************************/\r\nErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave,\r\n CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);\r\nvoid CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore);\r\n\r\n/* CRYP's DMA interface function **********************************************/\r\nvoid CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState);\r\n\r\n/* Interrupts and flags management functions **********************************/\r\nvoid CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState);\r\nITStatus CRYP_GetITStatus(uint8_t CRYP_IT);\r\nFlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG);\r\n\r\n/* High Level AES functions **************************************************/\r\nErrorStatus CRYP_AES_ECB(uint8_t Mode,\r\n uint8_t *Key, uint16_t Keysize,\r\n uint8_t *Input, uint32_t Ilength,\r\n uint8_t *Output);\r\n\r\nErrorStatus CRYP_AES_CBC(uint8_t Mode,\r\n uint8_t InitVectors[16],\r\n uint8_t *Key, uint16_t Keysize,\r\n uint8_t *Input, uint32_t Ilength,\r\n uint8_t *Output);\r\n\r\nErrorStatus CRYP_AES_CTR(uint8_t Mode,\r\n uint8_t InitVectors[16],\r\n uint8_t *Key, uint16_t Keysize,\r\n uint8_t *Input, uint32_t Ilength,\r\n uint8_t *Output);\r\n\r\n/* High Level TDES functions **************************************************/\r\nErrorStatus CRYP_TDES_ECB(uint8_t Mode,\r\n uint8_t Key[24], \r\n uint8_t *Input, uint32_t Ilength,\r\n uint8_t *Output);\r\n\r\nErrorStatus CRYP_TDES_CBC(uint8_t Mode,\r\n uint8_t Key[24],\r\n uint8_t InitVectors[8],\r\n uint8_t *Input, uint32_t Ilength,\r\n uint8_t *Output);\r\n\r\n/* High Level DES functions **************************************************/\r\nErrorStatus CRYP_DES_ECB(uint8_t Mode,\r\n uint8_t Key[8],\r\n uint8_t *Input, uint32_t Ilength,\r\n uint8_t *Output);\r\n\r\nErrorStatus CRYP_DES_CBC(uint8_t Mode,\r\n uint8_t Key[8],\r\n uint8_t InitVectors[8],\r\n uint8_t *Input,uint32_t Ilength,\r\n uint8_t *Output);\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /*__STM32F4xx_CRYP_H */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dac.h", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_dac.h\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file contains all the functions prototypes for the DAC firmware \r\n * library.\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F4xx_DAC_H\r\n#define __STM32F4xx_DAC_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @addtogroup DAC\r\n * @{\r\n */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n\r\n/** \r\n * @brief DAC Init structure definition\r\n */\r\n\r\ntypedef struct\r\n{\r\n uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.\r\n This parameter can be a value of @ref DAC_trigger_selection */\r\n\r\n uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves\r\n are generated, or whether no wave is generated.\r\n This parameter can be a value of @ref DAC_wave_generation */\r\n\r\n uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or\r\n the maximum amplitude triangle generation for the DAC channel. \r\n This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */\r\n\r\n uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.\r\n This parameter can be a value of @ref DAC_output_buffer */\r\n}DAC_InitTypeDef;\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup DAC_Exported_Constants\r\n * @{\r\n */\r\n\r\n/** @defgroup DAC_trigger_selection \r\n * @{\r\n */\r\n\r\n#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register \r\n has been loaded, and not by external trigger */\r\n#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */\r\n#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */\r\n#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */\r\n#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */\r\n#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */\r\n#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ \r\n\r\n#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */\r\n#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */\r\n\r\n#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \\\r\n ((TRIGGER) == DAC_Trigger_T6_TRGO) || \\\r\n ((TRIGGER) == DAC_Trigger_T8_TRGO) || \\\r\n ((TRIGGER) == DAC_Trigger_T7_TRGO) || \\\r\n ((TRIGGER) == DAC_Trigger_T5_TRGO) || \\\r\n ((TRIGGER) == DAC_Trigger_T2_TRGO) || \\\r\n ((TRIGGER) == DAC_Trigger_T4_TRGO) || \\\r\n ((TRIGGER) == DAC_Trigger_Ext_IT9) || \\\r\n ((TRIGGER) == DAC_Trigger_Software))\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup DAC_wave_generation \r\n * @{\r\n */\r\n\r\n#define DAC_WaveGeneration_None ((uint32_t)0x00000000)\r\n#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)\r\n#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)\r\n#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \\\r\n ((WAVE) == DAC_WaveGeneration_Noise) || \\\r\n ((WAVE) == DAC_WaveGeneration_Triangle))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup DAC_lfsrunmask_triangleamplitude\r\n * @{\r\n */\r\n\r\n#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */\r\n#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */\r\n#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */\r\n#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */\r\n#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */\r\n#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */\r\n#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */\r\n#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */\r\n#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */\r\n#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */\r\n#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */\r\n#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */\r\n#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */\r\n#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */\r\n#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */\r\n#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */\r\n#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */\r\n#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */\r\n#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */\r\n#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */\r\n#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */\r\n#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */\r\n#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */\r\n#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */\r\n\r\n#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \\\r\n ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \\\r\n ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \\\r\n ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \\\r\n ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \\\r\n ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \\\r\n ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \\\r\n ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \\\r\n ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \\\r\n ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \\\r\n ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \\\r\n ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \\\r\n ((VALUE) == DAC_TriangleAmplitude_1) || \\\r\n ((VALUE) == DAC_TriangleAmplitude_3) || \\\r\n ((VALUE) == DAC_TriangleAmplitude_7) || \\\r\n ((VALUE) == DAC_TriangleAmplitude_15) || \\\r\n ((VALUE) == DAC_TriangleAmplitude_31) || \\\r\n ((VALUE) == DAC_TriangleAmplitude_63) || \\\r\n ((VALUE) == DAC_TriangleAmplitude_127) || \\\r\n ((VALUE) == DAC_TriangleAmplitude_255) || \\\r\n ((VALUE) == DAC_TriangleAmplitude_511) || \\\r\n ((VALUE) == DAC_TriangleAmplitude_1023) || \\\r\n ((VALUE) == DAC_TriangleAmplitude_2047) || \\\r\n ((VALUE) == DAC_TriangleAmplitude_4095))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup DAC_output_buffer \r\n * @{\r\n */\r\n\r\n#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)\r\n#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)\r\n#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \\\r\n ((STATE) == DAC_OutputBuffer_Disable))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup DAC_Channel_selection \r\n * @{\r\n */\r\n\r\n#define DAC_Channel_1 ((uint32_t)0x00000000)\r\n#define DAC_Channel_2 ((uint32_t)0x00000010)\r\n#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \\\r\n ((CHANNEL) == DAC_Channel_2))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup DAC_data_alignement \r\n * @{\r\n */\r\n\r\n#define DAC_Align_12b_R ((uint32_t)0x00000000)\r\n#define DAC_Align_12b_L ((uint32_t)0x00000004)\r\n#define DAC_Align_8b_R ((uint32_t)0x00000008)\r\n#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \\\r\n ((ALIGN) == DAC_Align_12b_L) || \\\r\n ((ALIGN) == DAC_Align_8b_R))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup DAC_wave_generation \r\n * @{\r\n */\r\n\r\n#define DAC_Wave_Noise ((uint32_t)0x00000040)\r\n#define DAC_Wave_Triangle ((uint32_t)0x00000080)\r\n#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \\\r\n ((WAVE) == DAC_Wave_Triangle))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup DAC_data \r\n * @{\r\n */\r\n\r\n#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) \r\n/**\r\n * @}\r\n */\r\n \r\n/** @defgroup DAC_interrupts_definition \r\n * @{\r\n */ \r\n#define DAC_IT_DMAUDR ((uint32_t)0x00002000) \r\n#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup DAC_flags_definition \r\n * @{\r\n */ \r\n \r\n#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) \r\n#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) \r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/ \r\n\r\n/* Function used to set the DAC configuration to the default reset state *****/ \r\nvoid DAC_DeInit(void);\r\n\r\n/* DAC channels configuration: trigger, output buffer, data format functions */\r\nvoid DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);\r\nvoid DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);\r\nvoid DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);\r\nvoid DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);\r\nvoid DAC_DualSoftwareTriggerCmd(FunctionalState NewState);\r\nvoid DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);\r\nvoid DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);\r\nvoid DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);\r\nvoid DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);\r\nuint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);\r\n\r\n/* DMA management functions ***************************************************/\r\nvoid DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);\r\n\r\n/* Interrupts and flags management functions **********************************/\r\nvoid DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);\r\nFlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);\r\nvoid DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);\r\nITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);\r\nvoid DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /*__STM32F4xx_DAC_H */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dbgmcu.h", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_dbgmcu.h\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file contains all the functions prototypes for the DBGMCU firmware library.\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F4xx_DBGMCU_H\r\n#define __STM32F4xx_DBGMCU_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @addtogroup DBGMCU\r\n * @{\r\n */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup DBGMCU_Exported_Constants\r\n * @{\r\n */ \r\n#define DBGMCU_SLEEP ((uint32_t)0x00000001)\r\n#define DBGMCU_STOP ((uint32_t)0x00000002)\r\n#define DBGMCU_STANDBY ((uint32_t)0x00000004)\r\n#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))\r\n\r\n#define DBGMCU_TIM2_STOP ((uint32_t)0x00000001)\r\n#define DBGMCU_TIM3_STOP ((uint32_t)0x00000002)\r\n#define DBGMCU_TIM4_STOP ((uint32_t)0x00000004)\r\n#define DBGMCU_TIM5_STOP ((uint32_t)0x00000008)\r\n#define DBGMCU_TIM6_STOP ((uint32_t)0x00000010)\r\n#define DBGMCU_TIM7_STOP ((uint32_t)0x00000020)\r\n#define DBGMCU_TIM12_STOP ((uint32_t)0x00000040)\r\n#define DBGMCU_TIM13_STOP ((uint32_t)0x00000080)\r\n#define DBGMCU_TIM14_STOP ((uint32_t)0x00000100)\r\n#define DBGMCU_RTC_STOP ((uint32_t)0x00000400)\r\n#define DBGMCU_WWDG_STOP ((uint32_t)0x00000800)\r\n#define DBGMCU_IWDG_STOP ((uint32_t)0x00001000)\r\n#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)\r\n#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)\r\n#define DBGMCU_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)\r\n#define DBGMCU_CAN1_STOP ((uint32_t)0x02000000)\r\n#define DBGMCU_CAN2_STOP ((uint32_t)0x04000000)\r\n#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xF91FE200) == 0x00) && ((PERIPH) != 0x00))\r\n\r\n#define DBGMCU_TIM1_STOP ((uint32_t)0x00000001)\r\n#define DBGMCU_TIM8_STOP ((uint32_t)0x00000002)\r\n#define DBGMCU_TIM9_STOP ((uint32_t)0x00010000)\r\n#define DBGMCU_TIM10_STOP ((uint32_t)0x00020000)\r\n#define DBGMCU_TIM11_STOP ((uint32_t)0x00040000)\r\n#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8FFFC) == 0x00) && ((PERIPH) != 0x00))\r\n/**\r\n * @}\r\n */ \r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/ \r\nuint32_t DBGMCU_GetREVID(void);\r\nuint32_t DBGMCU_GetDEVID(void);\r\nvoid DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);\r\nvoid DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);\r\nvoid DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F4xx_DBGMCU_H */\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dcmi.h", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_dcmi.h\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file contains all the functions prototypes for the DCMI firmware library.\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F4xx_DCMI_H\r\n#define __STM32F4xx_DCMI_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @addtogroup DCMI\r\n * @{\r\n */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** \r\n * @brief DCMI Init structure definition \r\n */ \r\ntypedef struct\r\n{\r\n uint16_t DCMI_CaptureMode; /*!< Specifies the Capture Mode: Continuous or Snapshot.\r\n This parameter can be a value of @ref DCMI_Capture_Mode */\r\n\r\n uint16_t DCMI_SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded.\r\n This parameter can be a value of @ref DCMI_Synchronization_Mode */\r\n\r\n uint16_t DCMI_PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising.\r\n This parameter can be a value of @ref DCMI_PIXCK_Polarity */\r\n\r\n uint16_t DCMI_VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low.\r\n This parameter can be a value of @ref DCMI_VSYNC_Polarity */\r\n\r\n uint16_t DCMI_HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low.\r\n This parameter can be a value of @ref DCMI_HSYNC_Polarity */\r\n\r\n uint16_t DCMI_CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.\r\n This parameter can be a value of @ref DCMI_Capture_Rate */\r\n\r\n uint16_t DCMI_ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.\r\n This parameter can be a value of @ref DCMI_Extended_Data_Mode */\r\n} DCMI_InitTypeDef;\r\n\r\n/** \r\n * @brief DCMI CROP Init structure definition \r\n */ \r\ntypedef struct\r\n{\r\n uint16_t DCMI_VerticalStartLine; /*!< Specifies the Vertical start line count from which the image capture\r\n will start. This parameter can be a value between 0x00 and 0x1FFF */\r\n\r\n uint16_t DCMI_HorizontalOffsetCount; /*!< Specifies the number of pixel clocks to count before starting a capture.\r\n This parameter can be a value between 0x00 and 0x3FFF */\r\n\r\n uint16_t DCMI_VerticalLineCount; /*!< Specifies the number of lines to be captured from the starting point.\r\n This parameter can be a value between 0x00 and 0x3FFF */\r\n\r\n uint16_t DCMI_CaptureCount; /*!< Specifies the number of pixel clocks to be captured from the starting\r\n point on the same line.\r\n This parameter can be a value between 0x00 and 0x3FFF */\r\n} DCMI_CROPInitTypeDef;\r\n\r\n/** \r\n * @brief DCMI Embedded Synchronisation CODE Init structure definition \r\n */ \r\ntypedef struct\r\n{\r\n uint8_t DCMI_FrameStartCode; /*!< Specifies the code of the frame start delimiter. */\r\n uint8_t DCMI_LineStartCode; /*!< Specifies the code of the line start delimiter. */\r\n uint8_t DCMI_LineEndCode; /*!< Specifies the code of the line end delimiter. */\r\n uint8_t DCMI_FrameEndCode; /*!< Specifies the code of the frame end delimiter. */\r\n} DCMI_CodesInitTypeDef;\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup DCMI_Exported_Constants\r\n * @{\r\n */\r\n\r\n/** @defgroup DCMI_Capture_Mode \r\n * @{\r\n */ \r\n#define DCMI_CaptureMode_Continuous ((uint16_t)0x0000) /*!< The received data are transferred continuously \r\n into the destination memory through the DMA */\r\n#define DCMI_CaptureMode_SnapShot ((uint16_t)0x0002) /*!< Once activated, the interface waits for the start of \r\n frame and then transfers a single frame through the DMA */\r\n#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_CaptureMode_Continuous) || \\\r\n ((MODE) == DCMI_CaptureMode_SnapShot))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup DCMI_Synchronization_Mode\r\n * @{\r\n */ \r\n#define DCMI_SynchroMode_Hardware ((uint16_t)0x0000) /*!< Hardware synchronization data capture (frame/line start/stop)\r\n is synchronized with the HSYNC/VSYNC signals */\r\n#define DCMI_SynchroMode_Embedded ((uint16_t)0x0010) /*!< Embedded synchronization data capture is synchronized with \r\n synchronization codes embedded in the data flow */\r\n#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SynchroMode_Hardware) || \\\r\n ((MODE) == DCMI_SynchroMode_Embedded))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup DCMI_PIXCK_Polarity \r\n * @{\r\n */ \r\n#define DCMI_PCKPolarity_Falling ((uint16_t)0x0000) /*!< Pixel clock active on Falling edge */\r\n#define DCMI_PCKPolarity_Rising ((uint16_t)0x0020) /*!< Pixel clock active on Rising edge */\r\n#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPolarity_Falling) || \\\r\n ((POLARITY) == DCMI_PCKPolarity_Rising))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup DCMI_VSYNC_Polarity \r\n * @{\r\n */ \r\n#define DCMI_VSPolarity_Low ((uint16_t)0x0000) /*!< Vertical synchronization active Low */\r\n#define DCMI_VSPolarity_High ((uint16_t)0x0080) /*!< Vertical synchronization active High */\r\n#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPolarity_Low) || \\\r\n ((POLARITY) == DCMI_VSPolarity_High))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup DCMI_HSYNC_Polarity \r\n * @{\r\n */ \r\n#define DCMI_HSPolarity_Low ((uint16_t)0x0000) /*!< Horizontal synchronization active Low */\r\n#define DCMI_HSPolarity_High ((uint16_t)0x0040) /*!< Horizontal synchronization active High */\r\n#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPolarity_Low) || \\\r\n ((POLARITY) == DCMI_HSPolarity_High))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup DCMI_Capture_Rate \r\n * @{\r\n */ \r\n#define DCMI_CaptureRate_All_Frame ((uint16_t)0x0000) /*!< All frames are captured */\r\n#define DCMI_CaptureRate_1of2_Frame ((uint16_t)0x0100) /*!< Every alternate frame captured */\r\n#define DCMI_CaptureRate_1of4_Frame ((uint16_t)0x0200) /*!< One frame in 4 frames captured */\r\n#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CaptureRate_All_Frame) || \\\r\n ((RATE) == DCMI_CaptureRate_1of2_Frame) ||\\\r\n ((RATE) == DCMI_CaptureRate_1of4_Frame))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup DCMI_Extended_Data_Mode \r\n * @{\r\n */ \r\n#define DCMI_ExtendedDataMode_8b ((uint16_t)0x0000) /*!< Interface captures 8-bit data on every pixel clock */\r\n#define DCMI_ExtendedDataMode_10b ((uint16_t)0x0400) /*!< Interface captures 10-bit data on every pixel clock */\r\n#define DCMI_ExtendedDataMode_12b ((uint16_t)0x0800) /*!< Interface captures 12-bit data on every pixel clock */\r\n#define DCMI_ExtendedDataMode_14b ((uint16_t)0x0C00) /*!< Interface captures 14-bit data on every pixel clock */\r\n#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_ExtendedDataMode_8b) || \\\r\n ((DATA) == DCMI_ExtendedDataMode_10b) ||\\\r\n ((DATA) == DCMI_ExtendedDataMode_12b) ||\\\r\n ((DATA) == DCMI_ExtendedDataMode_14b))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup DCMI_interrupt_sources \r\n * @{\r\n */ \r\n#define DCMI_IT_FRAME ((uint16_t)0x0001)\r\n#define DCMI_IT_OVF ((uint16_t)0x0002)\r\n#define DCMI_IT_ERR ((uint16_t)0x0004)\r\n#define DCMI_IT_VSYNC ((uint16_t)0x0008)\r\n#define DCMI_IT_LINE ((uint16_t)0x0010)\r\n#define IS_DCMI_CONFIG_IT(IT) ((((IT) & (uint16_t)0xFFE0) == 0x0000) && ((IT) != 0x0000))\r\n#define IS_DCMI_GET_IT(IT) (((IT) == DCMI_IT_FRAME) || \\\r\n ((IT) == DCMI_IT_OVF) || \\\r\n ((IT) == DCMI_IT_ERR) || \\\r\n ((IT) == DCMI_IT_VSYNC) || \\\r\n ((IT) == DCMI_IT_LINE))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup DCMI_Flags \r\n * @{\r\n */ \r\n/** \r\n * @brief DCMI SR register \r\n */ \r\n#define DCMI_FLAG_HSYNC ((uint16_t)0x2001)\r\n#define DCMI_FLAG_VSYNC ((uint16_t)0x2002)\r\n#define DCMI_FLAG_FNE ((uint16_t)0x2004)\r\n/** \r\n * @brief DCMI RISR register \r\n */ \r\n#define DCMI_FLAG_FRAMERI ((uint16_t)0x0001)\r\n#define DCMI_FLAG_OVFRI ((uint16_t)0x0002)\r\n#define DCMI_FLAG_ERRRI ((uint16_t)0x0004)\r\n#define DCMI_FLAG_VSYNCRI ((uint16_t)0x0008)\r\n#define DCMI_FLAG_LINERI ((uint16_t)0x0010)\r\n/** \r\n * @brief DCMI MISR register \r\n */ \r\n#define DCMI_FLAG_FRAMEMI ((uint16_t)0x1001)\r\n#define DCMI_FLAG_OVFMI ((uint16_t)0x1002)\r\n#define DCMI_FLAG_ERRMI ((uint16_t)0x1004)\r\n#define DCMI_FLAG_VSYNCMI ((uint16_t)0x1008)\r\n#define DCMI_FLAG_LINEMI ((uint16_t)0x1010)\r\n#define IS_DCMI_GET_FLAG(FLAG) (((FLAG) == DCMI_FLAG_HSYNC) || \\\r\n ((FLAG) == DCMI_FLAG_VSYNC) || \\\r\n ((FLAG) == DCMI_FLAG_FNE) || \\\r\n ((FLAG) == DCMI_FLAG_FRAMERI) || \\\r\n ((FLAG) == DCMI_FLAG_OVFRI) || \\\r\n ((FLAG) == DCMI_FLAG_ERRRI) || \\\r\n ((FLAG) == DCMI_FLAG_VSYNCRI) || \\\r\n ((FLAG) == DCMI_FLAG_LINERI) || \\\r\n ((FLAG) == DCMI_FLAG_FRAMEMI) || \\\r\n ((FLAG) == DCMI_FLAG_OVFMI) || \\\r\n ((FLAG) == DCMI_FLAG_ERRMI) || \\\r\n ((FLAG) == DCMI_FLAG_VSYNCMI) || \\\r\n ((FLAG) == DCMI_FLAG_LINEMI))\r\n \r\n#define IS_DCMI_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFE0) == 0x0000) && ((FLAG) != 0x0000))\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/ \r\n\r\n/* Function used to set the DCMI configuration to the default reset state ****/ \r\nvoid DCMI_DeInit(void);\r\n\r\n/* Initialization and Configuration functions *********************************/\r\nvoid DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct);\r\nvoid DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct);\r\nvoid DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct);\r\nvoid DCMI_CROPCmd(FunctionalState NewState);\r\nvoid DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct);\r\nvoid DCMI_JPEGCmd(FunctionalState NewState);\r\n\r\n/* Image capture functions ****************************************************/\r\nvoid DCMI_Cmd(FunctionalState NewState);\r\nvoid DCMI_CaptureCmd(FunctionalState NewState);\r\nuint32_t DCMI_ReadData(void);\r\n\r\n/* Interrupts and flags management functions **********************************/\r\nvoid DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState);\r\nFlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG);\r\nvoid DCMI_ClearFlag(uint16_t DCMI_FLAG);\r\nITStatus DCMI_GetITStatus(uint16_t DCMI_IT);\r\nvoid DCMI_ClearITPendingBit(uint16_t DCMI_IT);\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /*__STM32F4xx_DCMI_H */\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma.h", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_dma.h\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file contains all the functions prototypes for the DMA firmware \r\n * library.\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F4xx_DMA_H\r\n#define __STM32F4xx_DMA_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @addtogroup DMA\r\n * @{\r\n */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n\r\n/** \r\n * @brief DMA Init structure definition\r\n */\r\n\r\ntypedef struct\r\n{\r\n uint32_t DMA_Channel; /*!< Specifies the channel used for the specified stream. \r\n This parameter can be a value of @ref DMA_channel */\r\n \r\n uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Streamx. */\r\n\r\n uint32_t DMA_Memory0BaseAddr; /*!< Specifies the memory 0 base address for DMAy Streamx. \r\n This memory is the default memory used when double buffer mode is\r\n not enabled. */\r\n\r\n uint32_t DMA_DIR; /*!< Specifies if the data will be transferred from memory to peripheral, \r\n from memory to memory or from peripheral to memory.\r\n This parameter can be a value of @ref DMA_data_transfer_direction */\r\n\r\n uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Stream. \r\n The data unit is equal to the configuration set in DMA_PeripheralDataSize\r\n or DMA_MemoryDataSize members depending in the transfer direction. */\r\n\r\n uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register should be incremented or not.\r\n This parameter can be a value of @ref DMA_peripheral_incremented_mode */\r\n\r\n uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register should be incremented or not.\r\n This parameter can be a value of @ref DMA_memory_incremented_mode */\r\n\r\n uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.\r\n This parameter can be a value of @ref DMA_peripheral_data_size */\r\n\r\n uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.\r\n This parameter can be a value of @ref DMA_memory_data_size */\r\n\r\n uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Streamx.\r\n This parameter can be a value of @ref DMA_circular_normal_mode\r\n @note The circular buffer mode cannot be used if the memory-to-memory\r\n data transfer is configured on the selected Stream */\r\n\r\n uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Streamx.\r\n This parameter can be a value of @ref DMA_priority_level */\r\n\r\n uint32_t DMA_FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified Stream.\r\n This parameter can be a value of @ref DMA_fifo_direct_mode\r\n @note The Direct mode (FIFO mode disabled) cannot be used if the \r\n memory-to-memory data transfer is configured on the selected Stream */\r\n\r\n uint32_t DMA_FIFOThreshold; /*!< Specifies the FIFO threshold level.\r\n This parameter can be a value of @ref DMA_fifo_threshold_level */\r\n\r\n uint32_t DMA_MemoryBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. \r\n It specifies the amount of data to be transferred in a single non interruptable \r\n transaction. This parameter can be a value of @ref DMA_memory_burst \r\n @note The burst mode is possible only if the address Increment mode is enabled. */\r\n\r\n uint32_t DMA_PeripheralBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. \r\n It specifies the amount of data to be transferred in a single non interruptable \r\n transaction. This parameter can be a value of @ref DMA_peripheral_burst\r\n @note The burst mode is possible only if the address Increment mode is enabled. */ \r\n}DMA_InitTypeDef;\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup DMA_Exported_Constants\r\n * @{\r\n */\r\n\r\n#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \\\r\n ((PERIPH) == DMA1_Stream1) || \\\r\n ((PERIPH) == DMA1_Stream2) || \\\r\n ((PERIPH) == DMA1_Stream3) || \\\r\n ((PERIPH) == DMA1_Stream4) || \\\r\n ((PERIPH) == DMA1_Stream5) || \\\r\n ((PERIPH) == DMA1_Stream6) || \\\r\n ((PERIPH) == DMA1_Stream7) || \\\r\n ((PERIPH) == DMA2_Stream0) || \\\r\n ((PERIPH) == DMA2_Stream1) || \\\r\n ((PERIPH) == DMA2_Stream2) || \\\r\n ((PERIPH) == DMA2_Stream3) || \\\r\n ((PERIPH) == DMA2_Stream4) || \\\r\n ((PERIPH) == DMA2_Stream5) || \\\r\n ((PERIPH) == DMA2_Stream6) || \\\r\n ((PERIPH) == DMA2_Stream7))\r\n\r\n#define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1) || \\\r\n ((CONTROLLER) == DMA2))\r\n\r\n/** @defgroup DMA_channel \r\n * @{\r\n */ \r\n#define DMA_Channel_0 ((uint32_t)0x00000000)\r\n#define DMA_Channel_1 ((uint32_t)0x02000000)\r\n#define DMA_Channel_2 ((uint32_t)0x04000000)\r\n#define DMA_Channel_3 ((uint32_t)0x06000000)\r\n#define DMA_Channel_4 ((uint32_t)0x08000000)\r\n#define DMA_Channel_5 ((uint32_t)0x0A000000)\r\n#define DMA_Channel_6 ((uint32_t)0x0C000000)\r\n#define DMA_Channel_7 ((uint32_t)0x0E000000)\r\n\r\n#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \\\r\n ((CHANNEL) == DMA_Channel_1) || \\\r\n ((CHANNEL) == DMA_Channel_2) || \\\r\n ((CHANNEL) == DMA_Channel_3) || \\\r\n ((CHANNEL) == DMA_Channel_4) || \\\r\n ((CHANNEL) == DMA_Channel_5) || \\\r\n ((CHANNEL) == DMA_Channel_6) || \\\r\n ((CHANNEL) == DMA_Channel_7))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup DMA_data_transfer_direction \r\n * @{\r\n */ \r\n#define DMA_DIR_PeripheralToMemory ((uint32_t)0x00000000)\r\n#define DMA_DIR_MemoryToPeripheral ((uint32_t)0x00000040) \r\n#define DMA_DIR_MemoryToMemory ((uint32_t)0x00000080)\r\n\r\n#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \\\r\n ((DIRECTION) == DMA_DIR_MemoryToPeripheral) || \\\r\n ((DIRECTION) == DMA_DIR_MemoryToMemory)) \r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup DMA_data_buffer_size \r\n * @{\r\n */ \r\n#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup DMA_peripheral_incremented_mode \r\n * @{\r\n */ \r\n#define DMA_PeripheralInc_Enable ((uint32_t)0x00000200)\r\n#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)\r\n\r\n#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \\\r\n ((STATE) == DMA_PeripheralInc_Disable))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup DMA_memory_incremented_mode \r\n * @{\r\n */ \r\n#define DMA_MemoryInc_Enable ((uint32_t)0x00000400)\r\n#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)\r\n\r\n#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \\\r\n ((STATE) == DMA_MemoryInc_Disable))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup DMA_peripheral_data_size \r\n * @{\r\n */ \r\n#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) \r\n#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000800) \r\n#define DMA_PeripheralDataSize_Word ((uint32_t)0x00001000)\r\n\r\n#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \\\r\n ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \\\r\n ((SIZE) == DMA_PeripheralDataSize_Word))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup DMA_memory_data_size \r\n * @{\r\n */ \r\n#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) \r\n#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00002000) \r\n#define DMA_MemoryDataSize_Word ((uint32_t)0x00004000)\r\n\r\n#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \\\r\n ((SIZE) == DMA_MemoryDataSize_HalfWord) || \\\r\n ((SIZE) == DMA_MemoryDataSize_Word ))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup DMA_circular_normal_mode \r\n * @{\r\n */ \r\n#define DMA_Mode_Normal ((uint32_t)0x00000000) \r\n#define DMA_Mode_Circular ((uint32_t)0x00000100)\r\n\r\n#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal ) || \\\r\n ((MODE) == DMA_Mode_Circular)) \r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup DMA_priority_level \r\n * @{\r\n */ \r\n#define DMA_Priority_Low ((uint32_t)0x00000000)\r\n#define DMA_Priority_Medium ((uint32_t)0x00010000) \r\n#define DMA_Priority_High ((uint32_t)0x00020000)\r\n#define DMA_Priority_VeryHigh ((uint32_t)0x00030000)\r\n\r\n#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_Low ) || \\\r\n ((PRIORITY) == DMA_Priority_Medium) || \\\r\n ((PRIORITY) == DMA_Priority_High) || \\\r\n ((PRIORITY) == DMA_Priority_VeryHigh)) \r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup DMA_fifo_direct_mode \r\n * @{\r\n */ \r\n#define DMA_FIFOMode_Disable ((uint32_t)0x00000000) \r\n#define DMA_FIFOMode_Enable ((uint32_t)0x00000004)\r\n\r\n#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \\\r\n ((STATE) == DMA_FIFOMode_Enable)) \r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup DMA_fifo_threshold_level \r\n * @{\r\n */ \r\n#define DMA_FIFOThreshold_1QuarterFull ((uint32_t)0x00000000)\r\n#define DMA_FIFOThreshold_HalfFull ((uint32_t)0x00000001) \r\n#define DMA_FIFOThreshold_3QuartersFull ((uint32_t)0x00000002)\r\n#define DMA_FIFOThreshold_Full ((uint32_t)0x00000003)\r\n\r\n#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \\\r\n ((THRESHOLD) == DMA_FIFOThreshold_HalfFull) || \\\r\n ((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \\\r\n ((THRESHOLD) == DMA_FIFOThreshold_Full)) \r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup DMA_memory_burst \r\n * @{\r\n */ \r\n#define DMA_MemoryBurst_Single ((uint32_t)0x00000000)\r\n#define DMA_MemoryBurst_INC4 ((uint32_t)0x00800000) \r\n#define DMA_MemoryBurst_INC8 ((uint32_t)0x01000000)\r\n#define DMA_MemoryBurst_INC16 ((uint32_t)0x01800000)\r\n\r\n#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MemoryBurst_Single) || \\\r\n ((BURST) == DMA_MemoryBurst_INC4) || \\\r\n ((BURST) == DMA_MemoryBurst_INC8) || \\\r\n ((BURST) == DMA_MemoryBurst_INC16))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup DMA_peripheral_burst \r\n * @{\r\n */ \r\n#define DMA_PeripheralBurst_Single ((uint32_t)0x00000000)\r\n#define DMA_PeripheralBurst_INC4 ((uint32_t)0x00200000) \r\n#define DMA_PeripheralBurst_INC8 ((uint32_t)0x00400000)\r\n#define DMA_PeripheralBurst_INC16 ((uint32_t)0x00600000)\r\n\r\n#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \\\r\n ((BURST) == DMA_PeripheralBurst_INC4) || \\\r\n ((BURST) == DMA_PeripheralBurst_INC8) || \\\r\n ((BURST) == DMA_PeripheralBurst_INC16))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup DMA_fifo_status_level \r\n * @{\r\n */\r\n#define DMA_FIFOStatus_Less1QuarterFull ((uint32_t)0x00000000 << 3)\r\n#define DMA_FIFOStatus_1QuarterFull ((uint32_t)0x00000001 << 3)\r\n#define DMA_FIFOStatus_HalfFull ((uint32_t)0x00000002 << 3) \r\n#define DMA_FIFOStatus_3QuartersFull ((uint32_t)0x00000003 << 3)\r\n#define DMA_FIFOStatus_Empty ((uint32_t)0x00000004 << 3)\r\n#define DMA_FIFOStatus_Full ((uint32_t)0x00000005 << 3)\r\n\r\n#define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \\\r\n ((STATUS) == DMA_FIFOStatus_HalfFull) || \\\r\n ((STATUS) == DMA_FIFOStatus_1QuarterFull) || \\\r\n ((STATUS) == DMA_FIFOStatus_3QuartersFull) || \\\r\n ((STATUS) == DMA_FIFOStatus_Full) || \\\r\n ((STATUS) == DMA_FIFOStatus_Empty)) \r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup DMA_flags_definition \r\n * @{\r\n */\r\n#define DMA_FLAG_FEIF0 ((uint32_t)0x10800001)\r\n#define DMA_FLAG_DMEIF0 ((uint32_t)0x10800004)\r\n#define DMA_FLAG_TEIF0 ((uint32_t)0x10000008)\r\n#define DMA_FLAG_HTIF0 ((uint32_t)0x10000010)\r\n#define DMA_FLAG_TCIF0 ((uint32_t)0x10000020)\r\n#define DMA_FLAG_FEIF1 ((uint32_t)0x10000040)\r\n#define DMA_FLAG_DMEIF1 ((uint32_t)0x10000100)\r\n#define DMA_FLAG_TEIF1 ((uint32_t)0x10000200)\r\n#define DMA_FLAG_HTIF1 ((uint32_t)0x10000400)\r\n#define DMA_FLAG_TCIF1 ((uint32_t)0x10000800)\r\n#define DMA_FLAG_FEIF2 ((uint32_t)0x10010000)\r\n#define DMA_FLAG_DMEIF2 ((uint32_t)0x10040000)\r\n#define DMA_FLAG_TEIF2 ((uint32_t)0x10080000)\r\n#define DMA_FLAG_HTIF2 ((uint32_t)0x10100000)\r\n#define DMA_FLAG_TCIF2 ((uint32_t)0x10200000)\r\n#define DMA_FLAG_FEIF3 ((uint32_t)0x10400000)\r\n#define DMA_FLAG_DMEIF3 ((uint32_t)0x11000000)\r\n#define DMA_FLAG_TEIF3 ((uint32_t)0x12000000)\r\n#define DMA_FLAG_HTIF3 ((uint32_t)0x14000000)\r\n#define DMA_FLAG_TCIF3 ((uint32_t)0x18000000)\r\n#define DMA_FLAG_FEIF4 ((uint32_t)0x20000001)\r\n#define DMA_FLAG_DMEIF4 ((uint32_t)0x20000004)\r\n#define DMA_FLAG_TEIF4 ((uint32_t)0x20000008)\r\n#define DMA_FLAG_HTIF4 ((uint32_t)0x20000010)\r\n#define DMA_FLAG_TCIF4 ((uint32_t)0x20000020)\r\n#define DMA_FLAG_FEIF5 ((uint32_t)0x20000040)\r\n#define DMA_FLAG_DMEIF5 ((uint32_t)0x20000100)\r\n#define DMA_FLAG_TEIF5 ((uint32_t)0x20000200)\r\n#define DMA_FLAG_HTIF5 ((uint32_t)0x20000400)\r\n#define DMA_FLAG_TCIF5 ((uint32_t)0x20000800)\r\n#define DMA_FLAG_FEIF6 ((uint32_t)0x20010000)\r\n#define DMA_FLAG_DMEIF6 ((uint32_t)0x20040000)\r\n#define DMA_FLAG_TEIF6 ((uint32_t)0x20080000)\r\n#define DMA_FLAG_HTIF6 ((uint32_t)0x20100000)\r\n#define DMA_FLAG_TCIF6 ((uint32_t)0x20200000)\r\n#define DMA_FLAG_FEIF7 ((uint32_t)0x20400000)\r\n#define DMA_FLAG_DMEIF7 ((uint32_t)0x21000000)\r\n#define DMA_FLAG_TEIF7 ((uint32_t)0x22000000)\r\n#define DMA_FLAG_HTIF7 ((uint32_t)0x24000000)\r\n#define DMA_FLAG_TCIF7 ((uint32_t)0x28000000)\r\n\r\n#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \\\r\n (((FLAG) & 0xC082F082) == 0x00) && ((FLAG) != 0x00))\r\n\r\n#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \\\r\n ((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \\\r\n ((FLAG) == DMA_FLAG_FEIF0) || ((FLAG) == DMA_FLAG_TCIF1) || \\\r\n ((FLAG) == DMA_FLAG_HTIF1) || ((FLAG) == DMA_FLAG_TEIF1) || \\\r\n ((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1) || \\\r\n ((FLAG) == DMA_FLAG_TCIF2) || ((FLAG) == DMA_FLAG_HTIF2) || \\\r\n ((FLAG) == DMA_FLAG_TEIF2) || ((FLAG) == DMA_FLAG_DMEIF2) || \\\r\n ((FLAG) == DMA_FLAG_FEIF2) || ((FLAG) == DMA_FLAG_TCIF3) || \\\r\n ((FLAG) == DMA_FLAG_HTIF3) || ((FLAG) == DMA_FLAG_TEIF3) || \\\r\n ((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3) || \\\r\n ((FLAG) == DMA_FLAG_TCIF4) || ((FLAG) == DMA_FLAG_HTIF4) || \\\r\n ((FLAG) == DMA_FLAG_TEIF4) || ((FLAG) == DMA_FLAG_DMEIF4) || \\\r\n ((FLAG) == DMA_FLAG_FEIF4) || ((FLAG) == DMA_FLAG_TCIF5) || \\\r\n ((FLAG) == DMA_FLAG_HTIF5) || ((FLAG) == DMA_FLAG_TEIF5) || \\\r\n ((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5) || \\\r\n ((FLAG) == DMA_FLAG_TCIF6) || ((FLAG) == DMA_FLAG_HTIF6) || \\\r\n ((FLAG) == DMA_FLAG_TEIF6) || ((FLAG) == DMA_FLAG_DMEIF6) || \\\r\n ((FLAG) == DMA_FLAG_FEIF6) || ((FLAG) == DMA_FLAG_TCIF7) || \\\r\n ((FLAG) == DMA_FLAG_HTIF7) || ((FLAG) == DMA_FLAG_TEIF7) || \\\r\n ((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup DMA_interrupt_enable_definitions \r\n * @{\r\n */ \r\n#define DMA_IT_TC ((uint32_t)0x00000010)\r\n#define DMA_IT_HT ((uint32_t)0x00000008)\r\n#define DMA_IT_TE ((uint32_t)0x00000004)\r\n#define DMA_IT_DME ((uint32_t)0x00000002)\r\n#define DMA_IT_FE ((uint32_t)0x00000080)\r\n\r\n#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup DMA_interrupts_definitions \r\n * @{\r\n */ \r\n#define DMA_IT_FEIF0 ((uint32_t)0x90000001)\r\n#define DMA_IT_DMEIF0 ((uint32_t)0x10001004)\r\n#define DMA_IT_TEIF0 ((uint32_t)0x10002008)\r\n#define DMA_IT_HTIF0 ((uint32_t)0x10004010)\r\n#define DMA_IT_TCIF0 ((uint32_t)0x10008020)\r\n#define DMA_IT_FEIF1 ((uint32_t)0x90000040)\r\n#define DMA_IT_DMEIF1 ((uint32_t)0x10001100)\r\n#define DMA_IT_TEIF1 ((uint32_t)0x10002200)\r\n#define DMA_IT_HTIF1 ((uint32_t)0x10004400)\r\n#define DMA_IT_TCIF1 ((uint32_t)0x10008800)\r\n#define DMA_IT_FEIF2 ((uint32_t)0x90010000)\r\n#define DMA_IT_DMEIF2 ((uint32_t)0x10041000)\r\n#define DMA_IT_TEIF2 ((uint32_t)0x10082000)\r\n#define DMA_IT_HTIF2 ((uint32_t)0x10104000)\r\n#define DMA_IT_TCIF2 ((uint32_t)0x10208000)\r\n#define DMA_IT_FEIF3 ((uint32_t)0x90400000)\r\n#define DMA_IT_DMEIF3 ((uint32_t)0x11001000)\r\n#define DMA_IT_TEIF3 ((uint32_t)0x12002000)\r\n#define DMA_IT_HTIF3 ((uint32_t)0x14004000)\r\n#define DMA_IT_TCIF3 ((uint32_t)0x18008000)\r\n#define DMA_IT_FEIF4 ((uint32_t)0xA0000001)\r\n#define DMA_IT_DMEIF4 ((uint32_t)0x20001004)\r\n#define DMA_IT_TEIF4 ((uint32_t)0x20002008)\r\n#define DMA_IT_HTIF4 ((uint32_t)0x20004010)\r\n#define DMA_IT_TCIF4 ((uint32_t)0x20008020)\r\n#define DMA_IT_FEIF5 ((uint32_t)0xA0000040)\r\n#define DMA_IT_DMEIF5 ((uint32_t)0x20001100)\r\n#define DMA_IT_TEIF5 ((uint32_t)0x20002200)\r\n#define DMA_IT_HTIF5 ((uint32_t)0x20004400)\r\n#define DMA_IT_TCIF5 ((uint32_t)0x20008800)\r\n#define DMA_IT_FEIF6 ((uint32_t)0xA0010000)\r\n#define DMA_IT_DMEIF6 ((uint32_t)0x20041000)\r\n#define DMA_IT_TEIF6 ((uint32_t)0x20082000)\r\n#define DMA_IT_HTIF6 ((uint32_t)0x20104000)\r\n#define DMA_IT_TCIF6 ((uint32_t)0x20208000)\r\n#define DMA_IT_FEIF7 ((uint32_t)0xA0400000)\r\n#define DMA_IT_DMEIF7 ((uint32_t)0x21001000)\r\n#define DMA_IT_TEIF7 ((uint32_t)0x22002000)\r\n#define DMA_IT_HTIF7 ((uint32_t)0x24004000)\r\n#define DMA_IT_TCIF7 ((uint32_t)0x28008000)\r\n\r\n#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \\\r\n (((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \\\r\n (((IT) & 0x40820082) == 0x00))\r\n\r\n#define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0) || \\\r\n ((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \\\r\n ((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1) || \\\r\n ((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1) || \\\r\n ((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1) || \\\r\n ((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2) || \\\r\n ((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \\\r\n ((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3) || \\\r\n ((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3) || \\\r\n ((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3) || \\\r\n ((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4) || \\\r\n ((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \\\r\n ((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5) || \\\r\n ((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5) || \\\r\n ((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5) || \\\r\n ((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6) || \\\r\n ((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \\\r\n ((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7) || \\\r\n ((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7) || \\\r\n ((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup DMA_peripheral_increment_offset \r\n * @{\r\n */ \r\n#define DMA_PINCOS_Psize ((uint32_t)0x00000000)\r\n#define DMA_PINCOS_WordAligned ((uint32_t)0x00008000)\r\n\r\n#define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \\\r\n ((SIZE) == DMA_PINCOS_WordAligned))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup DMA_flow_controller_definitions \r\n * @{\r\n */ \r\n#define DMA_FlowCtrl_Memory ((uint32_t)0x00000000)\r\n#define DMA_FlowCtrl_Peripheral ((uint32_t)0x00000020)\r\n\r\n#define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \\\r\n ((CTRL) == DMA_FlowCtrl_Peripheral))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup DMA_memory_targets_definitions \r\n * @{\r\n */ \r\n#define DMA_Memory_0 ((uint32_t)0x00000000)\r\n#define DMA_Memory_1 ((uint32_t)0x00080000)\r\n\r\n#define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1))\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/ \r\n\r\n/* Function used to set the DMA configuration to the default reset state *****/ \r\nvoid DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx);\r\n\r\n/* Initialization and Configuration functions *********************************/\r\nvoid DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct);\r\nvoid DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);\r\nvoid DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);\r\n\r\n/* Optional Configuration functions *******************************************/\r\nvoid DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos);\r\nvoid DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl);\r\n\r\n/* Data Counter functions *****************************************************/\r\nvoid DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter);\r\nuint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx);\r\n\r\n/* Double Buffer mode functions ***********************************************/\r\nvoid DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,\r\n uint32_t DMA_CurrentMemory);\r\nvoid DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);\r\nvoid DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,\r\n uint32_t DMA_MemoryTarget);\r\nuint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx);\r\n\r\n/* Interrupts and flags management functions **********************************/\r\nFunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx);\r\nuint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx);\r\nFlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);\r\nvoid DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);\r\nvoid DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);\r\nITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);\r\nvoid DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /*__STM32F4xx_DMA_H */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_exti.h", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_exti.h\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file contains all the functions prototypes for the EXTI firmware\r\n * library.\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F4xx_EXTI_H\r\n#define __STM32F4xx_EXTI_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @addtogroup EXTI\r\n * @{\r\n */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n\r\n/** \r\n * @brief EXTI mode enumeration \r\n */\r\n\r\ntypedef enum\r\n{\r\n EXTI_Mode_Interrupt = 0x00,\r\n EXTI_Mode_Event = 0x04\r\n}EXTIMode_TypeDef;\r\n\r\n#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))\r\n\r\n/** \r\n * @brief EXTI Trigger enumeration \r\n */\r\n\r\ntypedef enum\r\n{\r\n EXTI_Trigger_Rising = 0x08,\r\n EXTI_Trigger_Falling = 0x0C, \r\n EXTI_Trigger_Rising_Falling = 0x10\r\n}EXTITrigger_TypeDef;\r\n\r\n#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \\\r\n ((TRIGGER) == EXTI_Trigger_Falling) || \\\r\n ((TRIGGER) == EXTI_Trigger_Rising_Falling))\r\n/** \r\n * @brief EXTI Init Structure definition \r\n */\r\n\r\ntypedef struct\r\n{\r\n uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.\r\n This parameter can be any combination value of @ref EXTI_Lines */\r\n \r\n EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.\r\n This parameter can be a value of @ref EXTIMode_TypeDef */\r\n\r\n EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.\r\n This parameter can be a value of @ref EXTITrigger_TypeDef */\r\n\r\n FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.\r\n This parameter can be set either to ENABLE or DISABLE */ \r\n}EXTI_InitTypeDef;\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup EXTI_Exported_Constants\r\n * @{\r\n */\r\n\r\n/** @defgroup EXTI_Lines \r\n * @{\r\n */\r\n\r\n#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */\r\n#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */\r\n#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */\r\n#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */\r\n#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */\r\n#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */\r\n#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */\r\n#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */\r\n#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */\r\n#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */\r\n#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */\r\n#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */\r\n#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */\r\n#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */\r\n#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */\r\n#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */\r\n#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */\r\n#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */\r\n#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */ \r\n#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */\r\n#define EXTI_Line20 ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */\r\n#define EXTI_Line21 ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ \r\n#define EXTI_Line22 ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to the RTC Wakeup event */ \r\n \r\n#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00))\r\n\r\n#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \\\r\n ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \\\r\n ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \\\r\n ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \\\r\n ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \\\r\n ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \\\r\n ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \\\r\n ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \\\r\n ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \\\r\n ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \\\r\n ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) ||\\\r\n ((LINE) == EXTI_Line22))\r\n \r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/* Function used to set the EXTI configuration to the default reset state *****/\r\nvoid EXTI_DeInit(void);\r\n\r\n/* Initialization and Configuration functions *********************************/\r\nvoid EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);\r\nvoid EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);\r\nvoid EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);\r\n\r\n/* Interrupts and flags management functions **********************************/\r\nFlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);\r\nvoid EXTI_ClearFlag(uint32_t EXTI_Line);\r\nITStatus EXTI_GetITStatus(uint32_t EXTI_Line);\r\nvoid EXTI_ClearITPendingBit(uint32_t EXTI_Line);\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F4xx_EXTI_H */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash.h", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_flash.h\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file contains all the functions prototypes for the FLASH \r\n * firmware library.\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F4xx_FLASH_H\r\n#define __STM32F4xx_FLASH_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @addtogroup FLASH\r\n * @{\r\n */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** \r\n * @brief FLASH Status \r\n */ \r\ntypedef enum\r\n{ \r\n FLASH_BUSY = 1,\r\n FLASH_ERROR_PGS,\r\n FLASH_ERROR_PGP,\r\n FLASH_ERROR_PGA,\r\n FLASH_ERROR_WRP,\r\n FLASH_ERROR_PROGRAM,\r\n FLASH_ERROR_OPERATION,\r\n FLASH_COMPLETE\r\n}FLASH_Status;\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup FLASH_Exported_Constants\r\n * @{\r\n */ \r\n\r\n/** @defgroup Flash_Latency \r\n * @{\r\n */ \r\n#define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */\r\n#define FLASH_Latency_1 ((uint8_t)0x0001) /*!< FLASH One Latency cycle */\r\n#define FLASH_Latency_2 ((uint8_t)0x0002) /*!< FLASH Two Latency cycles */\r\n#define FLASH_Latency_3 ((uint8_t)0x0003) /*!< FLASH Three Latency cycles */\r\n#define FLASH_Latency_4 ((uint8_t)0x0004) /*!< FLASH Four Latency cycles */\r\n#define FLASH_Latency_5 ((uint8_t)0x0005) /*!< FLASH Five Latency cycles */\r\n#define FLASH_Latency_6 ((uint8_t)0x0006) /*!< FLASH Six Latency cycles */\r\n#define FLASH_Latency_7 ((uint8_t)0x0007) /*!< FLASH Seven Latency cycles */\r\n\r\n#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \\\r\n ((LATENCY) == FLASH_Latency_1) || \\\r\n ((LATENCY) == FLASH_Latency_2) || \\\r\n ((LATENCY) == FLASH_Latency_3) || \\\r\n ((LATENCY) == FLASH_Latency_4) || \\\r\n ((LATENCY) == FLASH_Latency_5) || \\\r\n ((LATENCY) == FLASH_Latency_6) || \\\r\n ((LATENCY) == FLASH_Latency_7))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup FLASH_Voltage_Range \r\n * @{\r\n */ \r\n#define VoltageRange_1 ((uint8_t)0x00) /*!< Device operating range: 1.8V to 2.1V */\r\n#define VoltageRange_2 ((uint8_t)0x01) /*!= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) ||\\\r\n (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F))) \r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup Option_Bytes_Write_Protection \r\n * @{\r\n */ \r\n#define OB_WRP_Sector_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */\r\n#define OB_WRP_Sector_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */\r\n#define OB_WRP_Sector_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */\r\n#define OB_WRP_Sector_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */\r\n#define OB_WRP_Sector_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */\r\n#define OB_WRP_Sector_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */\r\n#define OB_WRP_Sector_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */\r\n#define OB_WRP_Sector_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */\r\n#define OB_WRP_Sector_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */\r\n#define OB_WRP_Sector_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */\r\n#define OB_WRP_Sector_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */\r\n#define OB_WRP_Sector_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */\r\n#define OB_WRP_Sector_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */\r\n\r\n#define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FLASH_Option_Bytes_Read_Protection \r\n * @{\r\n */\r\n#define OB_RDP_Level_0 ((uint8_t)0xAA)\r\n#define OB_RDP_Level_1 ((uint8_t)0x55)\r\n/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2 \r\n it's no more possible to go back to level 1 or 0 */\r\n#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\\\r\n ((LEVEL) == OB_RDP_Level_1))/*||\\\r\n ((LEVEL) == OB_RDP_Level_2))*/\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup FLASH_Option_Bytes_IWatchdog \r\n * @{\r\n */ \r\n#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */\r\n#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */\r\n#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup FLASH_Option_Bytes_nRST_STOP \r\n * @{\r\n */ \r\n#define OB_STOP_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */\r\n#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */\r\n#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup FLASH_Option_Bytes_nRST_STDBY \r\n * @{\r\n */ \r\n#define OB_STDBY_NoRST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */\r\n#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */\r\n#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))\r\n/**\r\n * @}\r\n */\r\n \r\n/** @defgroup FLASH_BOR_Reset_Level \r\n * @{\r\n */ \r\n#define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */\r\n#define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */\r\n#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */\r\n#define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */\r\n#define IS_OB_BOR(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\\\r\n ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FLASH_Interrupts \r\n * @{\r\n */ \r\n#define FLASH_IT_EOP ((uint32_t)0x01000000) /*!< End of FLASH Operation Interrupt source */\r\n#define FLASH_IT_ERR ((uint32_t)0x02000000) /*!< Error Interrupt source */\r\n#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup FLASH_Flags \r\n * @{\r\n */ \r\n#define FLASH_FLAG_EOP ((uint32_t)0x00000001) /*!< FLASH End of Operation flag */\r\n#define FLASH_FLAG_OPERR ((uint32_t)0x00000002) /*!< FLASH operation Error flag */\r\n#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */\r\n#define FLASH_FLAG_PGAERR ((uint32_t)0x00000020) /*!< FLASH Programming Alignment error flag */\r\n#define FLASH_FLAG_PGPERR ((uint32_t)0x00000040) /*!< FLASH Programming Parallelism error flag */\r\n#define FLASH_FLAG_PGSERR ((uint32_t)0x00000080) /*!< FLASH Programming Sequence error flag */\r\n#define FLASH_FLAG_BSY ((uint32_t)0x00010000) /*!< FLASH Busy flag */ \r\n#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF0C) == 0x00000000) && ((FLAG) != 0x00000000))\r\n#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \\\r\n ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \\\r\n ((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \\\r\n ((FLAG) == FLASH_FLAG_BSY))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FLASH_Program_Parallelism \r\n * @{\r\n */\r\n#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000)\r\n#define FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100)\r\n#define FLASH_PSIZE_WORD ((uint32_t)0x00000200)\r\n#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300)\r\n#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF)\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup FLASH_Keys \r\n * @{\r\n */ \r\n#define RDP_KEY ((uint16_t)0x00A5)\r\n#define FLASH_KEY1 ((uint32_t)0x45670123)\r\n#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)\r\n#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3B)\r\n#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F)\r\n/**\r\n * @}\r\n */ \r\n\r\n/** \r\n * @brief ACR register byte 0 (Bits[8:0]) base address \r\n */ \r\n#define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00) \r\n/** \r\n * @brief OPTCR register byte 3 (Bits[24:16]) base address \r\n */ \r\n#define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14)\r\n#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15)\r\n#define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16)\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/ \r\n \r\n/* FLASH Interface configuration functions ************************************/\r\nvoid FLASH_SetLatency(uint32_t FLASH_Latency);\r\nvoid FLASH_PrefetchBufferCmd(FunctionalState NewState);\r\nvoid FLASH_InstructionCacheCmd(FunctionalState NewState);\r\nvoid FLASH_DataCacheCmd(FunctionalState NewState);\r\nvoid FLASH_InstructionCacheReset(void);\r\nvoid FLASH_DataCacheReset(void);\r\n\r\n/* FLASH Memory Programming functions *****************************************/ \r\nvoid FLASH_Unlock(void);\r\nvoid FLASH_Lock(void);\r\nFLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange);\r\nFLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange);\r\nFLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data);\r\nFLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);\r\nFLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);\r\nFLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data);\r\n\r\n/* Option Bytes Programming functions *****************************************/ \r\nvoid FLASH_OB_Unlock(void);\r\nvoid FLASH_OB_Lock(void);\r\nvoid FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);\r\nvoid FLASH_OB_RDPConfig(uint8_t OB_RDP);\r\nvoid FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);\r\nvoid FLASH_OB_BORConfig(uint8_t OB_BOR);\r\nFLASH_Status FLASH_OB_Launch(void);\r\nuint8_t FLASH_OB_GetUser(void);\r\nuint16_t FLASH_OB_GetWRP(void);\r\nFlagStatus FLASH_OB_GetRDP(void);\r\nuint8_t FLASH_OB_GetBOR(void);\r\n\r\n/* Interrupts and flags management functions **********************************/\r\nvoid FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);\r\nFlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);\r\nvoid FLASH_ClearFlag(uint32_t FLASH_FLAG);\r\nFLASH_Status FLASH_GetStatus(void);\r\nFLASH_Status FLASH_WaitForLastOperation(void);\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F4xx_FLASH_H */\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fsmc.h", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_fsmc.h\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file contains all the functions prototypes for the FSMC firmware \r\n * library.\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F4xx_FSMC_H\r\n#define __STM32F4xx_FSMC_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @addtogroup FSMC\r\n * @{\r\n */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n\r\n/** \r\n * @brief Timing parameters For NOR/SRAM Banks \r\n */\r\ntypedef struct\r\n{\r\n uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure\r\n the duration of the address setup time. \r\n This parameter can be a value between 0 and 0xF.\r\n @note This parameter is not used with synchronous NOR Flash memories. */\r\n\r\n uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure\r\n the duration of the address hold time.\r\n This parameter can be a value between 0 and 0xF. \r\n @note This parameter is not used with synchronous NOR Flash memories.*/\r\n\r\n uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure\r\n the duration of the data setup time.\r\n This parameter can be a value between 0 and 0xFF.\r\n @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */\r\n\r\n uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure\r\n the duration of the bus turnaround.\r\n This parameter can be a value between 0 and 0xF.\r\n @note This parameter is only used for multiplexed NOR Flash memories. */\r\n\r\n uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.\r\n This parameter can be a value between 1 and 0xF.\r\n @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */\r\n\r\n uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue\r\n to the memory before getting the first data.\r\n The parameter value depends on the memory type as shown below:\r\n - It must be set to 0 in case of a CRAM\r\n - It is don't care in asynchronous NOR, SRAM or ROM accesses\r\n - It may assume a value between 0 and 0xF in NOR Flash memories\r\n with synchronous burst mode enable */\r\n\r\n uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. \r\n This parameter can be a value of @ref FSMC_Access_Mode */\r\n}FSMC_NORSRAMTimingInitTypeDef;\r\n\r\n/** \r\n * @brief FSMC NOR/SRAM Init structure definition\r\n */\r\ntypedef struct\r\n{\r\n uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.\r\n This parameter can be a value of @ref FSMC_NORSRAM_Bank */\r\n\r\n uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are\r\n multiplexed on the databus or not. \r\n This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */\r\n\r\n uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to\r\n the corresponding memory bank.\r\n This parameter can be a value of @ref FSMC_Memory_Type */\r\n\r\n uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.\r\n This parameter can be a value of @ref FSMC_Data_Width */\r\n\r\n uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,\r\n valid only with synchronous burst Flash memories.\r\n This parameter can be a value of @ref FSMC_Burst_Access_Mode */\r\n\r\n uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,\r\n valid only with asynchronous Flash memories.\r\n This parameter can be a value of @ref FSMC_AsynchronousWait */ \r\n\r\n uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing\r\n the Flash memory in burst mode.\r\n This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */\r\n\r\n uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash\r\n memory, valid only when accessing Flash memories in burst mode.\r\n This parameter can be a value of @ref FSMC_Wrap_Mode */\r\n\r\n uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one\r\n clock cycle before the wait state or during the wait state,\r\n valid only when accessing memories in burst mode. \r\n This parameter can be a value of @ref FSMC_Wait_Timing */\r\n\r\n uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. \r\n This parameter can be a value of @ref FSMC_Write_Operation */\r\n\r\n uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait\r\n signal, valid for Flash memory access in burst mode. \r\n This parameter can be a value of @ref FSMC_Wait_Signal */\r\n\r\n uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.\r\n This parameter can be a value of @ref FSMC_Extended_Mode */\r\n\r\n uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.\r\n This parameter can be a value of @ref FSMC_Write_Burst */ \r\n\r\n FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ \r\n\r\n FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ \r\n}FSMC_NORSRAMInitTypeDef;\r\n\r\n/** \r\n * @brief Timing parameters For FSMC NAND and PCCARD Banks\r\n */\r\ntypedef struct\r\n{\r\n uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before\r\n the command assertion for NAND-Flash read or write access\r\n to common/Attribute or I/O memory space (depending on\r\n the memory space timing to be configured).\r\n This parameter can be a value between 0 and 0xFF.*/\r\n\r\n uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the\r\n command for NAND-Flash read or write access to\r\n common/Attribute or I/O memory space (depending on the\r\n memory space timing to be configured). \r\n This parameter can be a number between 0x00 and 0xFF */\r\n\r\n uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address\r\n (and data for write access) after the command deassertion\r\n for NAND-Flash read or write access to common/Attribute\r\n or I/O memory space (depending on the memory space timing\r\n to be configured).\r\n This parameter can be a number between 0x00 and 0xFF */\r\n\r\n uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the\r\n databus is kept in HiZ after the start of a NAND-Flash\r\n write access to common/Attribute or I/O memory space (depending\r\n on the memory space timing to be configured).\r\n This parameter can be a number between 0x00 and 0xFF */\r\n}FSMC_NAND_PCCARDTimingInitTypeDef;\r\n\r\n/** \r\n * @brief FSMC NAND Init structure definition\r\n */\r\ntypedef struct\r\n{\r\n uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used.\r\n This parameter can be a value of @ref FSMC_NAND_Bank */\r\n\r\n uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.\r\n This parameter can be any value of @ref FSMC_Wait_feature */\r\n\r\n uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.\r\n This parameter can be any value of @ref FSMC_Data_Width */\r\n\r\n uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation.\r\n This parameter can be any value of @ref FSMC_ECC */\r\n\r\n uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC.\r\n This parameter can be any value of @ref FSMC_ECC_Page_Size */\r\n\r\n uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the\r\n delay between CLE low and RE low.\r\n This parameter can be a value between 0 and 0xFF. */\r\n\r\n uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the\r\n delay between ALE low and RE low.\r\n This parameter can be a number between 0x0 and 0xFF */ \r\n\r\n FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ \r\n\r\n FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */\r\n}FSMC_NANDInitTypeDef;\r\n\r\n/** \r\n * @brief FSMC PCCARD Init structure definition\r\n */\r\n\r\ntypedef struct\r\n{\r\n uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.\r\n This parameter can be any value of @ref FSMC_Wait_feature */\r\n\r\n uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the\r\n delay between CLE low and RE low.\r\n This parameter can be a value between 0 and 0xFF. */\r\n\r\n uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the\r\n delay between ALE low and RE low.\r\n This parameter can be a number between 0x0 and 0xFF */ \r\n\r\n \r\n FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */\r\n\r\n FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ \r\n \r\n FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ \r\n}FSMC_PCCARDInitTypeDef;\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup FSMC_Exported_Constants\r\n * @{\r\n */\r\n\r\n/** @defgroup FSMC_NORSRAM_Bank \r\n * @{\r\n */\r\n#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)\r\n#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)\r\n#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)\r\n#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FSMC_NAND_Bank \r\n * @{\r\n */ \r\n#define FSMC_Bank2_NAND ((uint32_t)0x00000010)\r\n#define FSMC_Bank3_NAND ((uint32_t)0x00000100)\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FSMC_PCCARD_Bank \r\n * @{\r\n */ \r\n#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)\r\n/**\r\n * @}\r\n */\r\n\r\n#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \\\r\n ((BANK) == FSMC_Bank1_NORSRAM2) || \\\r\n ((BANK) == FSMC_Bank1_NORSRAM3) || \\\r\n ((BANK) == FSMC_Bank1_NORSRAM4))\r\n\r\n#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \\\r\n ((BANK) == FSMC_Bank3_NAND))\r\n\r\n#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \\\r\n ((BANK) == FSMC_Bank3_NAND) || \\\r\n ((BANK) == FSMC_Bank4_PCCARD))\r\n\r\n#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \\\r\n ((BANK) == FSMC_Bank3_NAND) || \\\r\n ((BANK) == FSMC_Bank4_PCCARD))\r\n\r\n/** @defgroup FSMC_NOR_SRAM_Controller \r\n * @{\r\n */\r\n\r\n/** @defgroup FSMC_Data_Address_Bus_Multiplexing \r\n * @{\r\n */\r\n\r\n#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)\r\n#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)\r\n#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \\\r\n ((MUX) == FSMC_DataAddressMux_Enable))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FSMC_Memory_Type \r\n * @{\r\n */\r\n\r\n#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)\r\n#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)\r\n#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)\r\n#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \\\r\n ((MEMORY) == FSMC_MemoryType_PSRAM)|| \\\r\n ((MEMORY) == FSMC_MemoryType_NOR))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FSMC_Data_Width \r\n * @{\r\n */\r\n\r\n#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)\r\n#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)\r\n#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \\\r\n ((WIDTH) == FSMC_MemoryDataWidth_16b))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FSMC_Burst_Access_Mode \r\n * @{\r\n */\r\n\r\n#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) \r\n#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)\r\n#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \\\r\n ((STATE) == FSMC_BurstAccessMode_Enable))\r\n/**\r\n * @}\r\n */\r\n \r\n/** @defgroup FSMC_AsynchronousWait \r\n * @{\r\n */\r\n#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)\r\n#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)\r\n#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \\\r\n ((STATE) == FSMC_AsynchronousWait_Enable))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FSMC_Wait_Signal_Polarity \r\n * @{\r\n */\r\n#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)\r\n#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)\r\n#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \\\r\n ((POLARITY) == FSMC_WaitSignalPolarity_High))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FSMC_Wrap_Mode \r\n * @{\r\n */\r\n#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)\r\n#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) \r\n#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \\\r\n ((MODE) == FSMC_WrapMode_Enable))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FSMC_Wait_Timing \r\n * @{\r\n */\r\n#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)\r\n#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) \r\n#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \\\r\n ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FSMC_Write_Operation \r\n * @{\r\n */\r\n#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)\r\n#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)\r\n#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \\\r\n ((OPERATION) == FSMC_WriteOperation_Enable)) \r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FSMC_Wait_Signal \r\n * @{\r\n */\r\n#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)\r\n#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) \r\n#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \\\r\n ((SIGNAL) == FSMC_WaitSignal_Enable))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FSMC_Extended_Mode \r\n * @{\r\n */\r\n#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)\r\n#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)\r\n\r\n#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \\\r\n ((MODE) == FSMC_ExtendedMode_Enable)) \r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FSMC_Write_Burst \r\n * @{\r\n */\r\n\r\n#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)\r\n#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) \r\n#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \\\r\n ((BURST) == FSMC_WriteBurst_Enable))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FSMC_Address_Setup_Time \r\n * @{\r\n */\r\n#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FSMC_Address_Hold_Time \r\n * @{\r\n */\r\n#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FSMC_Data_Setup_Time \r\n * @{\r\n */\r\n#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FSMC_Bus_Turn_around_Duration \r\n * @{\r\n */\r\n#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FSMC_CLK_Division \r\n * @{\r\n */\r\n#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FSMC_Data_Latency \r\n * @{\r\n */\r\n#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FSMC_Access_Mode \r\n * @{\r\n */\r\n#define FSMC_AccessMode_A ((uint32_t)0x00000000)\r\n#define FSMC_AccessMode_B ((uint32_t)0x10000000) \r\n#define FSMC_AccessMode_C ((uint32_t)0x20000000)\r\n#define FSMC_AccessMode_D ((uint32_t)0x30000000)\r\n#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \\\r\n ((MODE) == FSMC_AccessMode_B) || \\\r\n ((MODE) == FSMC_AccessMode_C) || \\\r\n ((MODE) == FSMC_AccessMode_D))\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n \r\n/** @defgroup FSMC_NAND_PCCARD_Controller \r\n * @{\r\n */\r\n\r\n/** @defgroup FSMC_Wait_feature \r\n * @{\r\n */\r\n#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)\r\n#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)\r\n#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \\\r\n ((FEATURE) == FSMC_Waitfeature_Enable))\r\n/**\r\n * @}\r\n */\r\n\r\n\r\n/** @defgroup FSMC_ECC \r\n * @{\r\n */\r\n#define FSMC_ECC_Disable ((uint32_t)0x00000000)\r\n#define FSMC_ECC_Enable ((uint32_t)0x00000040)\r\n#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \\\r\n ((STATE) == FSMC_ECC_Enable))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FSMC_ECC_Page_Size \r\n * @{\r\n */\r\n#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)\r\n#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)\r\n#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)\r\n#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)\r\n#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)\r\n#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)\r\n#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \\\r\n ((SIZE) == FSMC_ECCPageSize_512Bytes) || \\\r\n ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \\\r\n ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \\\r\n ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \\\r\n ((SIZE) == FSMC_ECCPageSize_8192Bytes))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FSMC_TCLR_Setup_Time \r\n * @{\r\n */\r\n#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FSMC_TAR_Setup_Time \r\n * @{\r\n */\r\n#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FSMC_Setup_Time \r\n * @{\r\n */\r\n#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FSMC_Wait_Setup_Time \r\n * @{\r\n */\r\n#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FSMC_Hold_Setup_Time \r\n * @{\r\n */\r\n#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FSMC_HiZ_Setup_Time \r\n * @{\r\n */\r\n#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FSMC_Interrupt_sources \r\n * @{\r\n */\r\n#define FSMC_IT_RisingEdge ((uint32_t)0x00000008)\r\n#define FSMC_IT_Level ((uint32_t)0x00000010)\r\n#define FSMC_IT_FallingEdge ((uint32_t)0x00000020)\r\n#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))\r\n#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \\\r\n ((IT) == FSMC_IT_Level) || \\\r\n ((IT) == FSMC_IT_FallingEdge)) \r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FSMC_Flags \r\n * @{\r\n */\r\n#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)\r\n#define FSMC_FLAG_Level ((uint32_t)0x00000002)\r\n#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)\r\n#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)\r\n#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \\\r\n ((FLAG) == FSMC_FLAG_Level) || \\\r\n ((FLAG) == FSMC_FLAG_FallingEdge) || \\\r\n ((FLAG) == FSMC_FLAG_FEMPT))\r\n\r\n#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/ \r\n\r\n/* NOR/SRAM Controller functions **********************************************/\r\nvoid FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);\r\nvoid FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);\r\nvoid FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);\r\nvoid FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);\r\n\r\n/* NAND Controller functions **************************************************/\r\nvoid FSMC_NANDDeInit(uint32_t FSMC_Bank);\r\nvoid FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);\r\nvoid FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);\r\nvoid FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);\r\nvoid FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);\r\nuint32_t FSMC_GetECC(uint32_t FSMC_Bank);\r\n\r\n/* PCCARD Controller functions ************************************************/\r\nvoid FSMC_PCCARDDeInit(void);\r\nvoid FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);\r\nvoid FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);\r\nvoid FSMC_PCCARDCmd(FunctionalState NewState);\r\n\r\n/* Interrupts and flags management functions **********************************/\r\nvoid FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);\r\nFlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);\r\nvoid FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);\r\nITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);\r\nvoid FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /*__STM32F4xx_FSMC_H */\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_gpio.h\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file contains all the functions prototypes for the GPIO firmware\r\n * library.\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F4xx_GPIO_H\r\n#define __STM32F4xx_GPIO_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @addtogroup GPIO\r\n * @{\r\n */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n\r\n#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \\\r\n ((PERIPH) == GPIOB) || \\\r\n ((PERIPH) == GPIOC) || \\\r\n ((PERIPH) == GPIOD) || \\\r\n ((PERIPH) == GPIOE) || \\\r\n ((PERIPH) == GPIOF) || \\\r\n ((PERIPH) == GPIOG) || \\\r\n ((PERIPH) == GPIOH) || \\\r\n ((PERIPH) == GPIOI))\r\n \r\n/** \r\n * @brief GPIO Configuration Mode enumeration \r\n */ \r\ntypedef enum\r\n{ \r\n GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */\r\n GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */\r\n GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */\r\n GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */\r\n}GPIOMode_TypeDef;\r\n#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \\\r\n ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))\r\n\r\n/** \r\n * @brief GPIO Output type enumeration \r\n */ \r\ntypedef enum\r\n{ \r\n GPIO_OType_PP = 0x00,\r\n GPIO_OType_OD = 0x01\r\n}GPIOOType_TypeDef;\r\n#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))\r\n\r\n\r\n/** \r\n * @brief GPIO Output Maximum frequency enumeration \r\n */ \r\ntypedef enum\r\n{ \r\n GPIO_Speed_2MHz = 0x00, /*!< Low speed */\r\n GPIO_Speed_25MHz = 0x01, /*!< Medium speed */\r\n GPIO_Speed_50MHz = 0x02, /*!< Fast speed */\r\n GPIO_Speed_100MHz = 0x03 /*!< High speed on 30 pF (80 MHz Output max speed on 15 pF) */\r\n}GPIOSpeed_TypeDef;\r\n#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_2MHz) || ((SPEED) == GPIO_Speed_25MHz) || \\\r\n ((SPEED) == GPIO_Speed_50MHz)|| ((SPEED) == GPIO_Speed_100MHz)) \r\n\r\n/** \r\n * @brief GPIO Configuration PullUp PullDown enumeration \r\n */ \r\ntypedef enum\r\n{ \r\n GPIO_PuPd_NOPULL = 0x00,\r\n GPIO_PuPd_UP = 0x01,\r\n GPIO_PuPd_DOWN = 0x02\r\n}GPIOPuPd_TypeDef;\r\n#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \\\r\n ((PUPD) == GPIO_PuPd_DOWN))\r\n\r\n/** \r\n * @brief GPIO Bit SET and Bit RESET enumeration \r\n */ \r\ntypedef enum\r\n{ \r\n Bit_RESET = 0,\r\n Bit_SET\r\n}BitAction;\r\n#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))\r\n\r\n\r\n/** \r\n * @brief GPIO Init structure definition \r\n */ \r\ntypedef struct\r\n{\r\n uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.\r\n This parameter can be any value of @ref GPIO_pins_define */\r\n\r\n GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.\r\n This parameter can be a value of @ref GPIOMode_TypeDef */\r\n\r\n GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.\r\n This parameter can be a value of @ref GPIOSpeed_TypeDef */\r\n\r\n GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.\r\n This parameter can be a value of @ref GPIOOType_TypeDef */\r\n\r\n GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.\r\n This parameter can be a value of @ref GPIOPuPd_TypeDef */\r\n}GPIO_InitTypeDef;\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup GPIO_Exported_Constants\r\n * @{\r\n */ \r\n\r\n/** @defgroup GPIO_pins_define \r\n * @{\r\n */ \r\n#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */\r\n#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */\r\n#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */\r\n#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */\r\n#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */\r\n#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */\r\n#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */\r\n#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */\r\n#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */\r\n#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */\r\n#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */\r\n#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */\r\n#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */\r\n#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */\r\n#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */\r\n#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */\r\n#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */\r\n\r\n#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))\r\n#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \\\r\n ((PIN) == GPIO_Pin_1) || \\\r\n ((PIN) == GPIO_Pin_2) || \\\r\n ((PIN) == GPIO_Pin_3) || \\\r\n ((PIN) == GPIO_Pin_4) || \\\r\n ((PIN) == GPIO_Pin_5) || \\\r\n ((PIN) == GPIO_Pin_6) || \\\r\n ((PIN) == GPIO_Pin_7) || \\\r\n ((PIN) == GPIO_Pin_8) || \\\r\n ((PIN) == GPIO_Pin_9) || \\\r\n ((PIN) == GPIO_Pin_10) || \\\r\n ((PIN) == GPIO_Pin_11) || \\\r\n ((PIN) == GPIO_Pin_12) || \\\r\n ((PIN) == GPIO_Pin_13) || \\\r\n ((PIN) == GPIO_Pin_14) || \\\r\n ((PIN) == GPIO_Pin_15))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup GPIO_Pin_sources \r\n * @{\r\n */ \r\n#define GPIO_PinSource0 ((uint8_t)0x00)\r\n#define GPIO_PinSource1 ((uint8_t)0x01)\r\n#define GPIO_PinSource2 ((uint8_t)0x02)\r\n#define GPIO_PinSource3 ((uint8_t)0x03)\r\n#define GPIO_PinSource4 ((uint8_t)0x04)\r\n#define GPIO_PinSource5 ((uint8_t)0x05)\r\n#define GPIO_PinSource6 ((uint8_t)0x06)\r\n#define GPIO_PinSource7 ((uint8_t)0x07)\r\n#define GPIO_PinSource8 ((uint8_t)0x08)\r\n#define GPIO_PinSource9 ((uint8_t)0x09)\r\n#define GPIO_PinSource10 ((uint8_t)0x0A)\r\n#define GPIO_PinSource11 ((uint8_t)0x0B)\r\n#define GPIO_PinSource12 ((uint8_t)0x0C)\r\n#define GPIO_PinSource13 ((uint8_t)0x0D)\r\n#define GPIO_PinSource14 ((uint8_t)0x0E)\r\n#define GPIO_PinSource15 ((uint8_t)0x0F)\r\n\r\n#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \\\r\n ((PINSOURCE) == GPIO_PinSource1) || \\\r\n ((PINSOURCE) == GPIO_PinSource2) || \\\r\n ((PINSOURCE) == GPIO_PinSource3) || \\\r\n ((PINSOURCE) == GPIO_PinSource4) || \\\r\n ((PINSOURCE) == GPIO_PinSource5) || \\\r\n ((PINSOURCE) == GPIO_PinSource6) || \\\r\n ((PINSOURCE) == GPIO_PinSource7) || \\\r\n ((PINSOURCE) == GPIO_PinSource8) || \\\r\n ((PINSOURCE) == GPIO_PinSource9) || \\\r\n ((PINSOURCE) == GPIO_PinSource10) || \\\r\n ((PINSOURCE) == GPIO_PinSource11) || \\\r\n ((PINSOURCE) == GPIO_PinSource12) || \\\r\n ((PINSOURCE) == GPIO_PinSource13) || \\\r\n ((PINSOURCE) == GPIO_PinSource14) || \\\r\n ((PINSOURCE) == GPIO_PinSource15))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup GPIO_Alternat_function_selection_define \r\n * @{\r\n */ \r\n/** \r\n * @brief AF 0 selection \r\n */ \r\n#define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */\r\n#define GPIO_AF_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */\r\n#define GPIO_AF_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */\r\n#define GPIO_AF_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */\r\n#define GPIO_AF_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */\r\n\r\n/** \r\n * @brief AF 1 selection \r\n */ \r\n#define GPIO_AF_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */\r\n#define GPIO_AF_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */\r\n\r\n/** \r\n * @brief AF 2 selection \r\n */ \r\n#define GPIO_AF_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */\r\n#define GPIO_AF_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */\r\n#define GPIO_AF_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */\r\n\r\n/** \r\n * @brief AF 3 selection \r\n */ \r\n#define GPIO_AF_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */\r\n#define GPIO_AF_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */\r\n#define GPIO_AF_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */\r\n#define GPIO_AF_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */\r\n\r\n/** \r\n * @brief AF 4 selection \r\n */ \r\n#define GPIO_AF_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */\r\n#define GPIO_AF_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */\r\n#define GPIO_AF_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */\r\n\r\n/** \r\n * @brief AF 5 selection \r\n */ \r\n#define GPIO_AF_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */\r\n#define GPIO_AF_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */\r\n\r\n/** \r\n * @brief AF 6 selection \r\n */ \r\n#define GPIO_AF_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */\r\n\r\n/** \r\n * @brief AF 7 selection \r\n */ \r\n#define GPIO_AF_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */\r\n#define GPIO_AF_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */\r\n#define GPIO_AF_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */\r\n#define GPIO_AF_I2S3ext ((uint8_t)0x07) /* I2S3ext Alternate Function mapping */\r\n\r\n/** \r\n * @brief AF 8 selection \r\n */ \r\n#define GPIO_AF_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */\r\n#define GPIO_AF_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */\r\n#define GPIO_AF_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */\r\n\r\n/** \r\n * @brief AF 9 selection \r\n */ \r\n#define GPIO_AF_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */\r\n#define GPIO_AF_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */\r\n#define GPIO_AF_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */\r\n#define GPIO_AF_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */\r\n#define GPIO_AF_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */\r\n\r\n/** \r\n * @brief AF 10 selection \r\n */ \r\n#define GPIO_AF_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */\r\n#define GPIO_AF_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */\r\n\r\n/** \r\n * @brief AF 11 selection \r\n */ \r\n#define GPIO_AF_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */\r\n\r\n/** \r\n * @brief AF 12 selection \r\n */ \r\n#define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */\r\n#define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */\r\n#define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */\r\n\r\n/** \r\n * @brief AF 13 selection \r\n */ \r\n#define GPIO_AF_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */\r\n\r\n/** \r\n * @brief AF 15 selection \r\n */ \r\n#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */\r\n\r\n#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \\\r\n ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \\\r\n ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \\\r\n ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \\\r\n ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \\\r\n ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \\\r\n ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \\\r\n ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \\\r\n ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \\\r\n ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \\\r\n ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \\\r\n ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \\\r\n ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \\\r\n ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \\\r\n ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \\\r\n ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_FSMC) || \\\r\n ((AF) == GPIO_AF_OTG_HS_FS) || ((AF) == GPIO_AF_SDIO) || \\\r\n ((AF) == GPIO_AF_DCMI) || ((AF) == GPIO_AF_EVENTOUT))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup GPIO_Legacy \r\n * @{\r\n */\r\n \r\n#define GPIO_Mode_AIN GPIO_Mode_AN\r\n\r\n#define GPIO_AF_OTG1_FS GPIO_AF_OTG_FS\r\n#define GPIO_AF_OTG2_HS GPIO_AF_OTG_HS\r\n#define GPIO_AF_OTG2_FS GPIO_AF_OTG_HS_FS\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/ \r\n\r\n/* Function used to set the GPIO configuration to the default reset state ****/\r\nvoid GPIO_DeInit(GPIO_TypeDef* GPIOx);\r\n\r\n/* Initialization and Configuration functions *********************************/\r\nvoid GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);\r\nvoid GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);\r\nvoid GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r\n\r\n/* GPIO Read and Write functions **********************************************/\r\nuint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r\nuint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);\r\nuint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r\nuint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);\r\nvoid GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r\nvoid GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r\nvoid GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);\r\nvoid GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);\r\nvoid GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r\n\r\n/* GPIO Alternate functions configuration function ****************************/\r\nvoid GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /*__STM32F4xx_GPIO_H */\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_hash.h", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_hash.h\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file contains all the functions prototypes for the HASH \r\n * firmware library.\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F4xx_HASH_H\r\n#define __STM32F4xx_HASH_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @addtogroup HASH\r\n * @{\r\n */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n\r\n/** \r\n * @brief HASH Init structure definition\r\n */ \r\ntypedef struct\r\n{\r\n uint32_t HASH_AlgoSelection; /*!< SHA-1 or MD5. This parameter can be a value \r\n of @ref HASH_Algo_Selection */\r\n uint32_t HASH_AlgoMode; /*!< HASH or HMAC. This parameter can be a value \r\n of @ref HASH_processor_Algorithm_Mode */\r\n uint32_t HASH_DataType; /*!< 32-bit data, 16-bit data, 8-bit data or \r\n bit-string. This parameter can be a value of\r\n @ref HASH_Data_Type */\r\n uint32_t HASH_HMACKeyType; /*!< HMAC Short key or HMAC Long Key. This parameter\r\n can be a value of @ref HASH_HMAC_Long_key_only_for_HMAC_mode */\r\n}HASH_InitTypeDef;\r\n\r\n/** \r\n * @brief HASH message digest result structure definition \r\n */ \r\ntypedef struct\r\n{\r\n uint32_t Data[5]; /*!< Message digest result : 5x 32bit words for SHA1 or \r\n 4x 32bit words for MD5 */\r\n} HASH_MsgDigest; \r\n\r\n/** \r\n * @brief HASH context swapping structure definition \r\n */ \r\ntypedef struct\r\n{\r\n uint32_t HASH_IMR; \r\n uint32_t HASH_STR; \r\n uint32_t HASH_CR; \r\n uint32_t HASH_CSR[51]; \r\n}HASH_Context;\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup HASH_Exported_Constants\r\n * @{\r\n */ \r\n\r\n/** @defgroup HASH_Algo_Selection \r\n * @{\r\n */ \r\n#define HASH_AlgoSelection_SHA1 ((uint16_t)0x0000) /*!< HASH function is SHA1 */\r\n#define HASH_AlgoSelection_MD5 ((uint16_t)0x0080) /*!< HASH function is MD5 */\r\n\r\n#define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || \\\r\n ((ALGOSELECTION) == HASH_AlgoSelection_MD5))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup HASH_processor_Algorithm_Mode \r\n * @{\r\n */ \r\n#define HASH_AlgoMode_HASH ((uint16_t)0x0000) /*!< Algorithm is HASH */ \r\n#define HASH_AlgoMode_HMAC ((uint16_t)0x0040) /*!< Algorithm is HMAC */\r\n\r\n#define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || \\\r\n ((ALGOMODE) == HASH_AlgoMode_HMAC))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup HASH_Data_Type \r\n * @{\r\n */ \r\n#define HASH_DataType_32b ((uint16_t)0x0000)\r\n#define HASH_DataType_16b ((uint16_t)0x0010)\r\n#define HASH_DataType_8b ((uint16_t)0x0020)\r\n#define HASH_DataType_1b ((uint16_t)0x0030)\r\n\r\n#define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DataType_32b)|| \\\r\n ((DATATYPE) == HASH_DataType_16b)|| \\\r\n ((DATATYPE) == HASH_DataType_8b)|| \\\r\n ((DATATYPE) == HASH_DataType_1b))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode \r\n * @{\r\n */ \r\n#define HASH_HMACKeyType_ShortKey ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */\r\n#define HASH_HMACKeyType_LongKey ((uint32_t)0x00010000) /*!< HMAC Key is > 64 bytes */\r\n\r\n#define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \\\r\n ((KEYTYPE) == HASH_HMACKeyType_LongKey))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup Number_of_valid_bits_in_last_word_of_the_message \r\n * @{\r\n */ \r\n#define IS_HASH_VALIDBITSNUMBER(VALIDBITS) ((VALIDBITS) <= 0x1F)\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup HASH_interrupts_definition \r\n * @{\r\n */ \r\n#define HASH_IT_DINI ((uint8_t)0x01) /*!< A new block can be entered into the input buffer (DIN)*/\r\n#define HASH_IT_DCI ((uint8_t)0x02) /*!< Digest calculation complete */\r\n\r\n#define IS_HASH_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00))\r\n#define IS_HASH_GET_IT(IT) (((IT) == HASH_IT_DINI) || ((IT) == HASH_IT_DCI))\r\n\t\t\t\t \r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup HASH_flags_definition \r\n * @{\r\n */ \r\n#define HASH_FLAG_DINIS ((uint16_t)0x0001) /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer.*/\r\n#define HASH_FLAG_DCIS ((uint16_t)0x0002) /*!< Digest calculation complete */\r\n#define HASH_FLAG_DMAS ((uint16_t)0x0004) /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */\r\n#define HASH_FLAG_BUSY ((uint16_t)0x0008) /*!< The hash core is Busy : processing a block of data */\r\n#define HASH_FLAG_DINNE ((uint16_t)0x1000) /*!< DIN not empty : The input buffer contains at least one word of data */\r\n\r\n#define IS_HASH_GET_FLAG(FLAG) (((FLAG) == HASH_FLAG_DINIS) || \\\r\n ((FLAG) == HASH_FLAG_DCIS) || \\\r\n ((FLAG) == HASH_FLAG_DMAS) || \\\r\n ((FLAG) == HASH_FLAG_BUSY) || \\\r\n ((FLAG) == HASH_FLAG_DINNE)) \r\n\r\n#define IS_HASH_CLEAR_FLAG(FLAG)(((FLAG) == HASH_FLAG_DINIS) || \\\r\n ((FLAG) == HASH_FLAG_DCIS)) \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/ \r\n \r\n/* Function used to set the HASH configuration to the default reset state ****/\r\nvoid HASH_DeInit(void);\r\n\r\n/* HASH Configuration function ************************************************/\r\nvoid HASH_Init(HASH_InitTypeDef* HASH_InitStruct);\r\nvoid HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct);\r\nvoid HASH_Reset(void);\r\n\r\n/* HASH Message Digest generation functions ***********************************/\r\nvoid HASH_DataIn(uint32_t Data);\r\nuint8_t HASH_GetInFIFOWordsNbr(void);\r\nvoid HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber);\r\nvoid HASH_StartDigest(void);\r\nvoid HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest);\r\n\r\n/* HASH Context swapping functions ********************************************/\r\nvoid HASH_SaveContext(HASH_Context* HASH_ContextSave);\r\nvoid HASH_RestoreContext(HASH_Context* HASH_ContextRestore);\r\n\r\n/* HASH's DMA interface function **********************************************/\r\nvoid HASH_DMACmd(FunctionalState NewState);\r\n\r\n/* HASH Interrupts and flags management functions *****************************/\r\nvoid HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState);\r\nFlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG);\r\nvoid HASH_ClearFlag(uint16_t HASH_FLAG);\r\nITStatus HASH_GetITStatus(uint8_t HASH_IT);\r\nvoid HASH_ClearITPendingBit(uint8_t HASH_IT);\r\n\r\n/* High Level SHA1 functions **************************************************/\r\nErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]);\r\nErrorStatus HMAC_SHA1(uint8_t *Key, uint32_t Keylen,\r\n uint8_t *Input, uint32_t Ilen,\r\n uint8_t Output[20]);\r\n\r\n/* High Level MD5 functions ***************************************************/\r\nErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]);\r\nErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen,\r\n uint8_t *Input, uint32_t Ilen,\r\n uint8_t Output[16]);\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /*__STM32F4xx_HASH_H */\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_i2c.h", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_i2c.h\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file contains all the functions prototypes for the I2C firmware \r\n * library.\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F4xx_I2C_H\r\n#define __STM32F4xx_I2C_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @addtogroup I2C\r\n * @{\r\n */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n\r\n/** \r\n * @brief I2C Init structure definition \r\n */\r\n\r\ntypedef struct\r\n{\r\n uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.\r\n This parameter must be set to a value lower than 400kHz */\r\n\r\n uint16_t I2C_Mode; /*!< Specifies the I2C mode.\r\n This parameter can be a value of @ref I2C_mode */\r\n\r\n uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.\r\n This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */\r\n\r\n uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.\r\n This parameter can be a 7-bit or 10-bit address. */\r\n\r\n uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.\r\n This parameter can be a value of @ref I2C_acknowledgement */\r\n\r\n uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.\r\n This parameter can be a value of @ref I2C_acknowledged_address */\r\n}I2C_InitTypeDef;\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n\r\n/** @defgroup I2C_Exported_Constants\r\n * @{\r\n */\r\n\r\n#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \\\r\n ((PERIPH) == I2C2) || \\\r\n ((PERIPH) == I2C3))\r\n/** @defgroup I2C_mode \r\n * @{\r\n */\r\n\r\n#define I2C_Mode_I2C ((uint16_t)0x0000)\r\n#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) \r\n#define I2C_Mode_SMBusHost ((uint16_t)0x000A)\r\n#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \\\r\n ((MODE) == I2C_Mode_SMBusDevice) || \\\r\n ((MODE) == I2C_Mode_SMBusHost))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup I2C_duty_cycle_in_fast_mode \r\n * @{\r\n */\r\n\r\n#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */\r\n#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */\r\n#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \\\r\n ((CYCLE) == I2C_DutyCycle_2))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup I2C_acknowledgement\r\n * @{\r\n */\r\n\r\n#define I2C_Ack_Enable ((uint16_t)0x0400)\r\n#define I2C_Ack_Disable ((uint16_t)0x0000)\r\n#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \\\r\n ((STATE) == I2C_Ack_Disable))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup I2C_transfer_direction \r\n * @{\r\n */\r\n\r\n#define I2C_Direction_Transmitter ((uint8_t)0x00)\r\n#define I2C_Direction_Receiver ((uint8_t)0x01)\r\n#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \\\r\n ((DIRECTION) == I2C_Direction_Receiver))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup I2C_acknowledged_address \r\n * @{\r\n */\r\n\r\n#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)\r\n#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)\r\n#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \\\r\n ((ADDRESS) == I2C_AcknowledgedAddress_10bit))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup I2C_registers \r\n * @{\r\n */\r\n\r\n#define I2C_Register_CR1 ((uint8_t)0x00)\r\n#define I2C_Register_CR2 ((uint8_t)0x04)\r\n#define I2C_Register_OAR1 ((uint8_t)0x08)\r\n#define I2C_Register_OAR2 ((uint8_t)0x0C)\r\n#define I2C_Register_DR ((uint8_t)0x10)\r\n#define I2C_Register_SR1 ((uint8_t)0x14)\r\n#define I2C_Register_SR2 ((uint8_t)0x18)\r\n#define I2C_Register_CCR ((uint8_t)0x1C)\r\n#define I2C_Register_TRISE ((uint8_t)0x20)\r\n#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \\\r\n ((REGISTER) == I2C_Register_CR2) || \\\r\n ((REGISTER) == I2C_Register_OAR1) || \\\r\n ((REGISTER) == I2C_Register_OAR2) || \\\r\n ((REGISTER) == I2C_Register_DR) || \\\r\n ((REGISTER) == I2C_Register_SR1) || \\\r\n ((REGISTER) == I2C_Register_SR2) || \\\r\n ((REGISTER) == I2C_Register_CCR) || \\\r\n ((REGISTER) == I2C_Register_TRISE))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup I2C_NACK_position \r\n * @{\r\n */\r\n\r\n#define I2C_NACKPosition_Next ((uint16_t)0x0800)\r\n#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)\r\n#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \\\r\n ((POSITION) == I2C_NACKPosition_Current))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup I2C_SMBus_alert_pin_level \r\n * @{\r\n */\r\n\r\n#define I2C_SMBusAlert_Low ((uint16_t)0x2000)\r\n#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)\r\n#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \\\r\n ((ALERT) == I2C_SMBusAlert_High))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup I2C_PEC_position \r\n * @{\r\n */\r\n\r\n#define I2C_PECPosition_Next ((uint16_t)0x0800)\r\n#define I2C_PECPosition_Current ((uint16_t)0xF7FF)\r\n#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \\\r\n ((POSITION) == I2C_PECPosition_Current))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup I2C_interrupts_definition \r\n * @{\r\n */\r\n\r\n#define I2C_IT_BUF ((uint16_t)0x0400)\r\n#define I2C_IT_EVT ((uint16_t)0x0200)\r\n#define I2C_IT_ERR ((uint16_t)0x0100)\r\n#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup I2C_interrupts_definition \r\n * @{\r\n */\r\n\r\n#define I2C_IT_SMBALERT ((uint32_t)0x01008000)\r\n#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)\r\n#define I2C_IT_PECERR ((uint32_t)0x01001000)\r\n#define I2C_IT_OVR ((uint32_t)0x01000800)\r\n#define I2C_IT_AF ((uint32_t)0x01000400)\r\n#define I2C_IT_ARLO ((uint32_t)0x01000200)\r\n#define I2C_IT_BERR ((uint32_t)0x01000100)\r\n#define I2C_IT_TXE ((uint32_t)0x06000080)\r\n#define I2C_IT_RXNE ((uint32_t)0x06000040)\r\n#define I2C_IT_STOPF ((uint32_t)0x02000010)\r\n#define I2C_IT_ADD10 ((uint32_t)0x02000008)\r\n#define I2C_IT_BTF ((uint32_t)0x02000004)\r\n#define I2C_IT_ADDR ((uint32_t)0x02000002)\r\n#define I2C_IT_SB ((uint32_t)0x02000001)\r\n\r\n#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))\r\n\r\n#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \\\r\n ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \\\r\n ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \\\r\n ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \\\r\n ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \\\r\n ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \\\r\n ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup I2C_flags_definition \r\n * @{\r\n */\r\n\r\n/** \r\n * @brief SR2 register flags \r\n */\r\n\r\n#define I2C_FLAG_DUALF ((uint32_t)0x00800000)\r\n#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)\r\n#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)\r\n#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)\r\n#define I2C_FLAG_TRA ((uint32_t)0x00040000)\r\n#define I2C_FLAG_BUSY ((uint32_t)0x00020000)\r\n#define I2C_FLAG_MSL ((uint32_t)0x00010000)\r\n\r\n/** \r\n * @brief SR1 register flags \r\n */\r\n\r\n#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)\r\n#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)\r\n#define I2C_FLAG_PECERR ((uint32_t)0x10001000)\r\n#define I2C_FLAG_OVR ((uint32_t)0x10000800)\r\n#define I2C_FLAG_AF ((uint32_t)0x10000400)\r\n#define I2C_FLAG_ARLO ((uint32_t)0x10000200)\r\n#define I2C_FLAG_BERR ((uint32_t)0x10000100)\r\n#define I2C_FLAG_TXE ((uint32_t)0x10000080)\r\n#define I2C_FLAG_RXNE ((uint32_t)0x10000040)\r\n#define I2C_FLAG_STOPF ((uint32_t)0x10000010)\r\n#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)\r\n#define I2C_FLAG_BTF ((uint32_t)0x10000004)\r\n#define I2C_FLAG_ADDR ((uint32_t)0x10000002)\r\n#define I2C_FLAG_SB ((uint32_t)0x10000001)\r\n\r\n#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))\r\n\r\n#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \\\r\n ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \\\r\n ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \\\r\n ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \\\r\n ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \\\r\n ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \\\r\n ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \\\r\n ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \\\r\n ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \\\r\n ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \\\r\n ((FLAG) == I2C_FLAG_SB))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup I2C_Events \r\n * @{\r\n */\r\n\r\n/**\r\n ===============================================================================\r\n I2C Master Events (Events grouped in order of communication)\r\n ===============================================================================\r\n */\r\n\r\n/** \r\n * @brief Communication start\r\n * \r\n * After sending the START condition (I2C_GenerateSTART() function) the master \r\n * has to wait for this event. It means that the Start condition has been correctly \r\n * released on the I2C bus (the bus is free, no other devices is communicating).\r\n * \r\n */\r\n/* --EV5 */\r\n#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */\r\n\r\n/** \r\n * @brief Address Acknowledge\r\n * \r\n * After checking on EV5 (start condition correctly released on the bus), the \r\n * master sends the address of the slave(s) with which it will communicate \r\n * (I2C_Send7bitAddress() function, it also determines the direction of the communication: \r\n * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges \r\n * his address. If an acknowledge is sent on the bus, one of the following events will \r\n * be set:\r\n * \r\n * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED \r\n * event is set.\r\n * \r\n * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED \r\n * is set\r\n * \r\n * 3) In case of 10-Bit addressing mode, the master (just after generating the START \r\n * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() \r\n * function). Then master should wait on EV9. It means that the 10-bit addressing \r\n * header has been correctly sent on the bus. Then master should send the second part of \r\n * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master \r\n * should wait for event EV6. \r\n * \r\n */\r\n\r\n/* --EV6 */\r\n#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */\r\n#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */\r\n/* --EV9 */\r\n#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */\r\n\r\n/** \r\n * @brief Communication events\r\n * \r\n * If a communication is established (START condition generated and slave address \r\n * acknowledged) then the master has to check on one of the following events for \r\n * communication procedures:\r\n * \r\n * 1) Master Receiver mode: The master has to wait on the event EV7 then to read \r\n * the data received from the slave (I2C_ReceiveData() function).\r\n * \r\n * 2) Master Transmitter mode: The master has to send data (I2C_SendData() \r\n * function) then to wait on event EV8 or EV8_2.\r\n * These two events are similar: \r\n * - EV8 means that the data has been written in the data register and is \r\n * being shifted out.\r\n * - EV8_2 means that the data has been physically shifted out and output \r\n * on the bus.\r\n * In most cases, using EV8 is sufficient for the application.\r\n * Using EV8_2 leads to a slower communication but ensure more reliable test.\r\n * EV8_2 is also more suitable than EV8 for testing on the last data transmission \r\n * (before Stop condition generation).\r\n * \r\n * @note In case the user software does not guarantee that this event EV7 is \r\n * managed before the current byte end of transfer, then user may check on EV7 \r\n * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).\r\n * In this case the communication may be slower.\r\n * \r\n */\r\n\r\n/* Master RECEIVER mode -----------------------------*/ \r\n/* --EV7 */\r\n#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */\r\n\r\n/* Master TRANSMITTER mode --------------------------*/\r\n/* --EV8 */\r\n#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */\r\n/* --EV8_2 */\r\n#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */\r\n\r\n\r\n/**\r\n ===============================================================================\r\n I2C Slave Events (Events grouped in order of communication)\r\n ===============================================================================\r\n */\r\n\r\n\r\n/** \r\n * @brief Communication start events\r\n * \r\n * Wait on one of these events at the start of the communication. It means that \r\n * the I2C peripheral detected a Start condition on the bus (generated by master \r\n * device) followed by the peripheral address. The peripheral generates an ACK \r\n * condition on the bus (if the acknowledge feature is enabled through function \r\n * I2C_AcknowledgeConfig()) and the events listed above are set :\r\n * \r\n * 1) In normal case (only one address managed by the slave), when the address \r\n * sent by the master matches the own address of the peripheral (configured by \r\n * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set \r\n * (where XXX could be TRANSMITTER or RECEIVER).\r\n * \r\n * 2) In case the address sent by the master matches the second address of the \r\n * peripheral (configured by the function I2C_OwnAddress2Config() and enabled \r\n * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED \r\n * (where XXX could be TRANSMITTER or RECEIVER) are set.\r\n * \r\n * 3) In case the address sent by the master is General Call (address 0x00) and \r\n * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) \r\n * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. \r\n * \r\n */\r\n\r\n/* --EV1 (all the events below are variants of EV1) */ \r\n/* 1) Case of One Single Address managed by the slave */\r\n#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */\r\n#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */\r\n\r\n/* 2) Case of Dual address managed by the slave */\r\n#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */\r\n#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */\r\n\r\n/* 3) Case of General Call enabled for the slave */\r\n#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */\r\n\r\n/** \r\n * @brief Communication events\r\n * \r\n * Wait on one of these events when EV1 has already been checked and: \r\n * \r\n * - Slave RECEIVER mode:\r\n * - EV2: When the application is expecting a data byte to be received. \r\n * - EV4: When the application is expecting the end of the communication: master \r\n * sends a stop condition and data transmission is stopped.\r\n * \r\n * - Slave Transmitter mode:\r\n * - EV3: When a byte has been transmitted by the slave and the application is expecting \r\n * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and\r\n * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be \r\n * used when the user software doesn't guarantee the EV3 is managed before the\r\n * current byte end of transfer.\r\n * - EV3_2: When the master sends a NACK in order to tell slave that data transmission \r\n * shall end (before sending the STOP condition). In this case slave has to stop sending \r\n * data bytes and expect a Stop condition on the bus.\r\n * \r\n * @note In case the user software does not guarantee that the event EV2 is \r\n * managed before the current byte end of transfer, then user may check on EV2 \r\n * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).\r\n * In this case the communication may be slower.\r\n *\r\n */\r\n\r\n/* Slave RECEIVER mode --------------------------*/ \r\n/* --EV2 */\r\n#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */\r\n/* --EV4 */\r\n#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */\r\n\r\n/* Slave TRANSMITTER mode -----------------------*/\r\n/* --EV3 */\r\n#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */\r\n#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */\r\n/* --EV3_2 */\r\n#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */\r\n\r\n/*\r\n ===============================================================================\r\n End of Events Description\r\n ===============================================================================\r\n */\r\n\r\n#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \\\r\n ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \\\r\n ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \\\r\n ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \\\r\n ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \\\r\n ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \\\r\n ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \\\r\n ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \\\r\n ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \\\r\n ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \\\r\n ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \\\r\n ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \\\r\n ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \\\r\n ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \\\r\n ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \\\r\n ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \\\r\n ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \\\r\n ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \\\r\n ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \\\r\n ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup I2C_own_address1 \r\n * @{\r\n */\r\n\r\n#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup I2C_clock_speed \r\n * @{\r\n */\r\n\r\n#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/ \r\n\r\n/* Function used to set the I2C configuration to the default reset state *****/\r\nvoid I2C_DeInit(I2C_TypeDef* I2Cx);\r\n\r\n/* Initialization and Configuration functions *********************************/\r\nvoid I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);\r\nvoid I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);\r\nvoid I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r\nvoid I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);\r\nvoid I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);\r\nvoid I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);\r\nvoid I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);\r\nvoid I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);\r\nvoid I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r\nvoid I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r\nvoid I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r\nvoid I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r\nvoid I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);\r\nvoid I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);\r\nvoid I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);\r\nvoid I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r\n\r\n/* Data transfers functions ***************************************************/ \r\nvoid I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);\r\nuint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);\r\n\r\n/* PEC management functions ***************************************************/ \r\nvoid I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);\r\nvoid I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);\r\nvoid I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);\r\nuint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);\r\n\r\n/* DMA transfers management functions *****************************************/\r\nvoid I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r\nvoid I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r\n\r\n/* Interrupts, events and flags management functions **************************/\r\nuint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);\r\nvoid I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);\r\n\r\n/* \r\n ===============================================================================\r\n I2C State Monitoring Functions\r\n ===============================================================================\r\n This I2C driver provides three different ways for I2C state monitoring\r\n depending on the application requirements and constraints:\r\n \r\n \r\n 1. Basic state monitoring (Using I2C_CheckEvent() function)\r\n -----------------------------------------------------------\r\n It compares the status registers (SR1 and SR2) content to a given event\r\n (can be the combination of one or more flags).\r\n It returns SUCCESS if the current status includes the given flags \r\n and returns ERROR if one or more flags are missing in the current status.\r\n\r\n - When to use\r\n - This function is suitable for most applications as well as for startup \r\n activity since the events are fully described in the product reference \r\n manual (RM0090).\r\n - It is also suitable for users who need to define their own events.\r\n\r\n - Limitations\r\n - If an error occurs (ie. error flags are set besides to the monitored \r\n flags), the I2C_CheckEvent() function may return SUCCESS despite \r\n the communication hold or corrupted real state. \r\n In this case, it is advised to use error interrupts to monitor \r\n the error events and handle them in the interrupt IRQ handler.\r\n \r\n Note \r\n For error management, it is advised to use the following functions:\r\n - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).\r\n - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.\r\n Where x is the peripheral instance (I2C1, I2C2 ...)\r\n - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the \r\n I2Cx_ER_IRQHandler() function in order to determine which error occurred.\r\n - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() \r\n and/or I2C_GenerateStop() in order to clear the error flag and source \r\n and return to correct communication status.\r\n \r\n \r\n 2. Advanced state monitoring (Using the function I2C_GetLastEvent())\r\n -------------------------------------------------------------------- \r\n Using the function I2C_GetLastEvent() which returns the image of both status \r\n registers in a single word (uint32_t) (Status Register 2 value is shifted left \r\n by 16 bits and concatenated to Status Register 1).\r\n\r\n - When to use\r\n - This function is suitable for the same applications above but it \r\n allows to overcome the mentioned limitation of I2C_GetFlagStatus() \r\n function.\r\n - The returned value could be compared to events already defined in \r\n this file or to custom values defined by user.\r\n This function is suitable when multiple flags are monitored at the \r\n same time.\r\n - At the opposite of I2C_CheckEvent() function, this function allows \r\n user to choose when an event is accepted (when all events flags are \r\n set and no other flags are set or just when the needed flags are set \r\n like I2C_CheckEvent() function.\r\n\r\n - Limitations\r\n - User may need to define his own events.\r\n - Same remark concerning the error management is applicable for this \r\n function if user decides to check only regular communication flags \r\n (and ignores error flags).\r\n \r\n \r\n 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())\r\n -----------------------------------------------------------------------\r\n \r\n Using the function I2C_GetFlagStatus() which simply returns the status of \r\n one single flag (ie. I2C_FLAG_RXNE ...). \r\n\r\n - When to use\r\n - This function could be used for specific applications or in debug \r\n phase.\r\n - It is suitable when only one flag checking is needed (most I2C \r\n events are monitored through multiple flags).\r\n - Limitations: \r\n - When calling this function, the Status register is accessed. \r\n Some flags are cleared when the status register is accessed. \r\n So checking the status of one Flag, may clear other ones.\r\n - Function may need to be called twice or more in order to monitor \r\n one single event. \r\n */\r\n\r\n/*\r\n ===============================================================================\r\n 1. Basic state monitoring\r\n ===============================================================================\r\n */\r\nErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);\r\n/*\r\n ===============================================================================\r\n 2. Advanced state monitoring\r\n ===============================================================================\r\n */\r\nuint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);\r\n/*\r\n ===============================================================================\r\n 3. Flag-based state monitoring\r\n ===============================================================================\r\n */\r\nFlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);\r\n\r\n\r\nvoid I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);\r\nITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);\r\nvoid I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /*__STM32F4xx_I2C_H */\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_iwdg.h\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file contains all the functions prototypes for the IWDG \r\n * firmware library.\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F4xx_IWDG_H\r\n#define __STM32F4xx_IWDG_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @addtogroup IWDG\r\n * @{\r\n */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup IWDG_Exported_Constants\r\n * @{\r\n */\r\n \r\n/** @defgroup IWDG_WriteAccess\r\n * @{\r\n */\r\n#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)\r\n#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)\r\n#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \\\r\n ((ACCESS) == IWDG_WriteAccess_Disable))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup IWDG_prescaler \r\n * @{\r\n */\r\n#define IWDG_Prescaler_4 ((uint8_t)0x00)\r\n#define IWDG_Prescaler_8 ((uint8_t)0x01)\r\n#define IWDG_Prescaler_16 ((uint8_t)0x02)\r\n#define IWDG_Prescaler_32 ((uint8_t)0x03)\r\n#define IWDG_Prescaler_64 ((uint8_t)0x04)\r\n#define IWDG_Prescaler_128 ((uint8_t)0x05)\r\n#define IWDG_Prescaler_256 ((uint8_t)0x06)\r\n#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \\\r\n ((PRESCALER) == IWDG_Prescaler_8) || \\\r\n ((PRESCALER) == IWDG_Prescaler_16) || \\\r\n ((PRESCALER) == IWDG_Prescaler_32) || \\\r\n ((PRESCALER) == IWDG_Prescaler_64) || \\\r\n ((PRESCALER) == IWDG_Prescaler_128)|| \\\r\n ((PRESCALER) == IWDG_Prescaler_256))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup IWDG_Flag \r\n * @{\r\n */\r\n#define IWDG_FLAG_PVU ((uint16_t)0x0001)\r\n#define IWDG_FLAG_RVU ((uint16_t)0x0002)\r\n#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))\r\n#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/* Prescaler and Counter configuration functions ******************************/\r\nvoid IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);\r\nvoid IWDG_SetPrescaler(uint8_t IWDG_Prescaler);\r\nvoid IWDG_SetReload(uint16_t Reload);\r\nvoid IWDG_ReloadCounter(void);\r\n\r\n/* IWDG activation function ***************************************************/\r\nvoid IWDG_Enable(void);\r\n\r\n/* Flag management function ***************************************************/\r\nFlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F4xx_IWDG_H */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_pwr.h", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_pwr.h\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file contains all the functions prototypes for the PWR firmware \r\n * library.\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F4xx_PWR_H\r\n#define __STM32F4xx_PWR_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @addtogroup PWR\r\n * @{\r\n */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup PWR_Exported_Constants\r\n * @{\r\n */ \r\n\r\n/** @defgroup PWR_PVD_detection_level \r\n * @{\r\n */ \r\n\r\n#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0\r\n#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1\r\n#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2\r\n#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3\r\n#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4\r\n#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5\r\n#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6\r\n#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7\r\n\r\n#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \\\r\n ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \\\r\n ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \\\r\n ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))\r\n/**\r\n * @}\r\n */\r\n\r\n \r\n/** @defgroup PWR_Regulator_state_in_STOP_mode \r\n * @{\r\n */\r\n\r\n#define PWR_Regulator_ON ((uint32_t)0x00000000)\r\n#define PWR_Regulator_LowPower PWR_CR_LPDS\r\n#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \\\r\n ((REGULATOR) == PWR_Regulator_LowPower))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup PWR_STOP_mode_entry \r\n * @{\r\n */\r\n\r\n#define PWR_STOPEntry_WFI ((uint8_t)0x01)\r\n#define PWR_STOPEntry_WFE ((uint8_t)0x02)\r\n#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))\r\n\r\n/** @defgroup PWR_Regulator_Voltage_Scale \r\n * @{\r\n */\r\n\r\n#define PWR_Regulator_Voltage_Scale1 ((uint32_t)0x00004000)\r\n#define PWR_Regulator_Voltage_Scale2 ((uint32_t)0x00000000)\r\n#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_Regulator_Voltage_Scale1) || ((VOLTAGE) == PWR_Regulator_Voltage_Scale2))\r\n \r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup PWR_Flag \r\n * @{\r\n */\r\n\r\n#define PWR_FLAG_WU PWR_CSR_WUF\r\n#define PWR_FLAG_SB PWR_CSR_SBF\r\n#define PWR_FLAG_PVDO PWR_CSR_PVDO\r\n#define PWR_FLAG_BRR PWR_CSR_BRR\r\n#define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY\r\n\r\n/** @defgroup PWR_Flag_Legacy \r\n * @{\r\n */\r\n#define PWR_FLAG_REGRDY PWR_FLAG_VOSRDY \r\n/**\r\n * @}\r\n */\r\n\r\n#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \\\r\n ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) || \\\r\n ((FLAG) == PWR_FLAG_VOSRDY))\r\n\r\n#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/ \r\n\r\n/* Function used to set the PWR configuration to the default reset state ******/ \r\nvoid PWR_DeInit(void);\r\n\r\n/* Backup Domain Access function **********************************************/ \r\nvoid PWR_BackupAccessCmd(FunctionalState NewState);\r\n\r\n/* PVD configuration functions ************************************************/ \r\nvoid PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);\r\nvoid PWR_PVDCmd(FunctionalState NewState);\r\n\r\n/* WakeUp pins configuration functions ****************************************/ \r\nvoid PWR_WakeUpPinCmd(FunctionalState NewState);\r\n\r\n/* Main and Backup Regulators configuration functions *************************/ \r\nvoid PWR_BackupRegulatorCmd(FunctionalState NewState);\r\nvoid PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage);\r\n\r\n/* FLASH Power Down configuration functions ***********************************/ \r\nvoid PWR_FlashPowerDownCmd(FunctionalState NewState);\r\n\r\n/* Low Power modes configuration functions ************************************/ \r\nvoid PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);\r\nvoid PWR_EnterSTANDBYMode(void);\r\n\r\n/* Flags management functions *************************************************/ \r\nFlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);\r\nvoid PWR_ClearFlag(uint32_t PWR_FLAG);\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F4xx_PWR_H */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_rcc.h\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file contains all the functions prototypes for the RCC firmware library.\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F4xx_RCC_H\r\n#define __STM32F4xx_RCC_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @addtogroup RCC\r\n * @{\r\n */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\ntypedef struct\r\n{\r\n uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */\r\n uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */\r\n uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */\r\n uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */\r\n}RCC_ClocksTypeDef;\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup RCC_Exported_Constants\r\n * @{\r\n */\r\n \r\n/** @defgroup RCC_HSE_configuration \r\n * @{\r\n */\r\n#define RCC_HSE_OFF ((uint8_t)0x00)\r\n#define RCC_HSE_ON ((uint8_t)0x01)\r\n#define RCC_HSE_Bypass ((uint8_t)0x05)\r\n#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \\\r\n ((HSE) == RCC_HSE_Bypass))\r\n/**\r\n * @}\r\n */ \r\n \r\n/** @defgroup RCC_PLL_Clock_Source \r\n * @{\r\n */\r\n#define RCC_PLLSource_HSI ((uint32_t)0x00000000)\r\n#define RCC_PLLSource_HSE ((uint32_t)0x00400000)\r\n#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \\\r\n ((SOURCE) == RCC_PLLSource_HSE))\r\n#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)\r\n#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))\r\n#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))\r\n#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))\r\n \r\n#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))\r\n#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) \r\n/**\r\n * @}\r\n */ \r\n \r\n/** @defgroup RCC_System_Clock_Source \r\n * @{\r\n */\r\n#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)\r\n#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)\r\n#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)\r\n#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \\\r\n ((SOURCE) == RCC_SYSCLKSource_HSE) || \\\r\n ((SOURCE) == RCC_SYSCLKSource_PLLCLK))\r\n/**\r\n * @}\r\n */ \r\n \r\n/** @defgroup RCC_AHB_Clock_Source\r\n * @{\r\n */\r\n#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)\r\n#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)\r\n#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)\r\n#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)\r\n#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)\r\n#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)\r\n#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)\r\n#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)\r\n#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)\r\n#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \\\r\n ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \\\r\n ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \\\r\n ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \\\r\n ((HCLK) == RCC_SYSCLK_Div512))\r\n/**\r\n * @}\r\n */ \r\n \r\n/** @defgroup RCC_APB1_APB2_Clock_Source\r\n * @{\r\n */\r\n#define RCC_HCLK_Div1 ((uint32_t)0x00000000)\r\n#define RCC_HCLK_Div2 ((uint32_t)0x00001000)\r\n#define RCC_HCLK_Div4 ((uint32_t)0x00001400)\r\n#define RCC_HCLK_Div8 ((uint32_t)0x00001800)\r\n#define RCC_HCLK_Div16 ((uint32_t)0x00001C00)\r\n#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \\\r\n ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \\\r\n ((PCLK) == RCC_HCLK_Div16))\r\n/**\r\n * @}\r\n */ \r\n \r\n/** @defgroup RCC_Interrupt_Source \r\n * @{\r\n */\r\n#define RCC_IT_LSIRDY ((uint8_t)0x01)\r\n#define RCC_IT_LSERDY ((uint8_t)0x02)\r\n#define RCC_IT_HSIRDY ((uint8_t)0x04)\r\n#define RCC_IT_HSERDY ((uint8_t)0x08)\r\n#define RCC_IT_PLLRDY ((uint8_t)0x10)\r\n#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)\r\n#define RCC_IT_CSS ((uint8_t)0x80)\r\n#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))\r\n#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \\\r\n ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \\\r\n ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \\\r\n ((IT) == RCC_IT_PLLI2SRDY))\r\n#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))\r\n/**\r\n * @}\r\n */ \r\n \r\n/** @defgroup RCC_LSE_Configuration \r\n * @{\r\n */\r\n#define RCC_LSE_OFF ((uint8_t)0x00)\r\n#define RCC_LSE_ON ((uint8_t)0x01)\r\n#define RCC_LSE_Bypass ((uint8_t)0x04)\r\n#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \\\r\n ((LSE) == RCC_LSE_Bypass))\r\n/**\r\n * @}\r\n */ \r\n \r\n/** @defgroup RCC_RTC_Clock_Source\r\n * @{\r\n */\r\n#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)\r\n#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)\r\n#define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300)\r\n#define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300)\r\n#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300)\r\n#define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300)\r\n#define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300)\r\n#define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300)\r\n#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300)\r\n#define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300)\r\n#define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300)\r\n#define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300)\r\n#define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300)\r\n#define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300)\r\n#define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300)\r\n#define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300)\r\n#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300)\r\n#define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300)\r\n#define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300)\r\n#define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300)\r\n#define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300)\r\n#define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300)\r\n#define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300)\r\n#define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300)\r\n#define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300)\r\n#define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300)\r\n#define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300)\r\n#define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300)\r\n#define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300)\r\n#define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300)\r\n#define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300)\r\n#define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300)\r\n#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \\\r\n ((SOURCE) == RCC_RTCCLKSource_LSI) || \\\r\n ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \\\r\n ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \\\r\n ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \\\r\n ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \\\r\n ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \\\r\n ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \\\r\n ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \\\r\n ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \\\r\n ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \\\r\n ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \\\r\n ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \\\r\n ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \\\r\n ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \\\r\n ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \\\r\n ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \\\r\n ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \\\r\n ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \\\r\n ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \\\r\n ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \\\r\n ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \\\r\n ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \\\r\n ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \\\r\n ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \\\r\n ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \\\r\n ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \\\r\n ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \\\r\n ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \\\r\n ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \\\r\n ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \\\r\n ((SOURCE) == RCC_RTCCLKSource_HSE_Div31))\r\n/**\r\n * @}\r\n */ \r\n \r\n/** @defgroup RCC_I2S_Clock_Source\r\n * @{\r\n */\r\n#define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00)\r\n#define RCC_I2S2CLKSource_Ext ((uint8_t)0x01)\r\n\r\n#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext)) \r\n/**\r\n * @}\r\n */ \r\n \r\n/** @defgroup RCC_AHB1_Peripherals \r\n * @{\r\n */ \r\n#define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001)\r\n#define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002)\r\n#define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004)\r\n#define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008)\r\n#define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010)\r\n#define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020)\r\n#define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040)\r\n#define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080)\r\n#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100)\r\n#define RCC_AHB1Periph_CRC ((uint32_t)0x00001000)\r\n#define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000)\r\n#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000)\r\n#define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000)\r\n#define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000)\r\n#define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000)\r\n#define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000)\r\n#define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000)\r\n#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000)\r\n#define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000)\r\n#define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000)\r\n#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000)\r\n#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000)\r\n#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000)\r\n#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x818BEE00) == 0x00) && ((PERIPH) != 0x00))\r\n#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD9FEE00) == 0x00) && ((PERIPH) != 0x00))\r\n#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81986E00) == 0x00) && ((PERIPH) != 0x00))\r\n/**\r\n * @}\r\n */ \r\n \r\n/** @defgroup RCC_AHB2_Peripherals \r\n * @{\r\n */ \r\n#define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001)\r\n#define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010)\r\n#define RCC_AHB2Periph_HASH ((uint32_t)0x00000020)\r\n#define RCC_AHB2Periph_RNG ((uint32_t)0x00000040)\r\n#define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080)\r\n#define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))\r\n/**\r\n * @}\r\n */ \r\n \r\n/** @defgroup RCC_AHB3_Peripherals \r\n * @{\r\n */ \r\n#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)\r\n#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))\r\n/**\r\n * @}\r\n */ \r\n \r\n/** @defgroup RCC_APB1_Peripherals \r\n * @{\r\n */ \r\n#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)\r\n#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)\r\n#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)\r\n#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)\r\n#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)\r\n#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)\r\n#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)\r\n#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)\r\n#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)\r\n#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)\r\n#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)\r\n#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)\r\n#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)\r\n#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)\r\n#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)\r\n#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)\r\n#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)\r\n#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)\r\n#define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000)\r\n#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)\r\n#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)\r\n#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)\r\n#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)\r\n#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC9013600) == 0x00) && ((PERIPH) != 0x00))\r\n/**\r\n * @}\r\n */ \r\n \r\n/** @defgroup RCC_APB2_Peripherals \r\n * @{\r\n */ \r\n#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001)\r\n#define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002)\r\n#define RCC_APB2Periph_USART1 ((uint32_t)0x00000010)\r\n#define RCC_APB2Periph_USART6 ((uint32_t)0x00000020)\r\n#define RCC_APB2Periph_ADC ((uint32_t)0x00000100)\r\n#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100)\r\n#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200)\r\n#define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400)\r\n#define RCC_APB2Periph_SDIO ((uint32_t)0x00000800)\r\n#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)\r\n#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000)\r\n#define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000)\r\n#define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000)\r\n#define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000)\r\n#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A0CC) == 0x00) && ((PERIPH) != 0x00))\r\n#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A6CC) == 0x00) && ((PERIPH) != 0x00))\r\n/**\r\n * @}\r\n */ \r\n \r\n/** @defgroup RCC_MCO1_Clock_Source_Prescaler\r\n * @{\r\n */\r\n#define RCC_MCO1Source_HSI ((uint32_t)0x00000000)\r\n#define RCC_MCO1Source_LSE ((uint32_t)0x00200000)\r\n#define RCC_MCO1Source_HSE ((uint32_t)0x00400000)\r\n#define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000)\r\n#define RCC_MCO1Div_1 ((uint32_t)0x00000000)\r\n#define RCC_MCO1Div_2 ((uint32_t)0x04000000)\r\n#define RCC_MCO1Div_3 ((uint32_t)0x05000000)\r\n#define RCC_MCO1Div_4 ((uint32_t)0x06000000)\r\n#define RCC_MCO1Div_5 ((uint32_t)0x07000000)\r\n#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \\\r\n ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))\r\n \r\n#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \\\r\n ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \\\r\n ((DIV) == RCC_MCO1Div_5)) \r\n/**\r\n * @}\r\n */ \r\n \r\n/** @defgroup RCC_MCO2_Clock_Source_Prescaler\r\n * @{\r\n */\r\n#define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000)\r\n#define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000)\r\n#define RCC_MCO2Source_HSE ((uint32_t)0x80000000)\r\n#define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000)\r\n#define RCC_MCO2Div_1 ((uint32_t)0x00000000)\r\n#define RCC_MCO2Div_2 ((uint32_t)0x20000000)\r\n#define RCC_MCO2Div_3 ((uint32_t)0x28000000)\r\n#define RCC_MCO2Div_4 ((uint32_t)0x30000000)\r\n#define RCC_MCO2Div_5 ((uint32_t)0x38000000)\r\n#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \\\r\n ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK))\r\n \r\n#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \\\r\n ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \\\r\n ((DIV) == RCC_MCO2Div_5)) \r\n/**\r\n * @}\r\n */ \r\n \r\n/** @defgroup RCC_Flag \r\n * @{\r\n */\r\n#define RCC_FLAG_HSIRDY ((uint8_t)0x21)\r\n#define RCC_FLAG_HSERDY ((uint8_t)0x31)\r\n#define RCC_FLAG_PLLRDY ((uint8_t)0x39)\r\n#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)\r\n#define RCC_FLAG_LSERDY ((uint8_t)0x41)\r\n#define RCC_FLAG_LSIRDY ((uint8_t)0x61)\r\n#define RCC_FLAG_BORRST ((uint8_t)0x79)\r\n#define RCC_FLAG_PINRST ((uint8_t)0x7A)\r\n#define RCC_FLAG_PORRST ((uint8_t)0x7B)\r\n#define RCC_FLAG_SFTRST ((uint8_t)0x7C)\r\n#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)\r\n#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)\r\n#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)\r\n#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \\\r\n ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \\\r\n ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \\\r\n ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \\\r\n ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \\\r\n ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \\\r\n ((FLAG) == RCC_FLAG_PLLI2SRDY))\r\n#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/ \r\n\r\n/* Function used to set the RCC clock configuration to the default reset state */\r\nvoid RCC_DeInit(void);\r\n\r\n/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/\r\nvoid RCC_HSEConfig(uint8_t RCC_HSE);\r\nErrorStatus RCC_WaitForHSEStartUp(void);\r\nvoid RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);\r\nvoid RCC_HSICmd(FunctionalState NewState);\r\nvoid RCC_LSEConfig(uint8_t RCC_LSE);\r\nvoid RCC_LSICmd(FunctionalState NewState);\r\n\r\nvoid RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);\r\nvoid RCC_PLLCmd(FunctionalState NewState);\r\nvoid RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);\r\nvoid RCC_PLLI2SCmd(FunctionalState NewState);\r\n\r\nvoid RCC_ClockSecuritySystemCmd(FunctionalState NewState);\r\nvoid RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);\r\nvoid RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);\r\n\r\n/* System, AHB and APB busses clocks configuration functions ******************/\r\nvoid RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);\r\nuint8_t RCC_GetSYSCLKSource(void);\r\nvoid RCC_HCLKConfig(uint32_t RCC_SYSCLK);\r\nvoid RCC_PCLK1Config(uint32_t RCC_HCLK);\r\nvoid RCC_PCLK2Config(uint32_t RCC_HCLK);\r\nvoid RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);\r\n\r\n/* Peripheral clocks configuration functions **********************************/\r\nvoid RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);\r\nvoid RCC_RTCCLKCmd(FunctionalState NewState);\r\nvoid RCC_BackupResetCmd(FunctionalState NewState);\r\nvoid RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); \r\n\r\nvoid RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);\r\nvoid RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);\r\nvoid RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);\r\nvoid RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r\nvoid RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r\n\r\nvoid RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);\r\nvoid RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);\r\nvoid RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);\r\nvoid RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r\nvoid RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r\n\r\nvoid RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);\r\nvoid RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);\r\nvoid RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);\r\nvoid RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r\nvoid RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r\n\r\n/* Interrupts and flags management functions **********************************/\r\nvoid RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);\r\nFlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);\r\nvoid RCC_ClearFlag(void);\r\nITStatus RCC_GetITStatus(uint8_t RCC_IT);\r\nvoid RCC_ClearITPendingBit(uint8_t RCC_IT);\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F4xx_RCC_H */\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rng.h", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_rng.h\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file contains all the functions prototypes for the Random \r\n * Number Generator(RNG) firmware library.\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F4xx_RNG_H\r\n#define __STM32F4xx_RNG_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @addtogroup RNG\r\n * @{\r\n */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/ \r\n\r\n/** @defgroup RNG_Exported_Constants\r\n * @{\r\n */\r\n \r\n/** @defgroup RNG_flags_definition \r\n * @{\r\n */ \r\n#define RNG_FLAG_DRDY ((uint8_t)0x0001) /*!< Data ready */\r\n#define RNG_FLAG_CECS ((uint8_t)0x0002) /*!< Clock error current status */\r\n#define RNG_FLAG_SECS ((uint8_t)0x0004) /*!< Seed error current status */\r\n\r\n#define IS_RNG_GET_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_DRDY) || \\\r\n ((RNG_FLAG) == RNG_FLAG_CECS) || \\\r\n ((RNG_FLAG) == RNG_FLAG_SECS))\r\n#define IS_RNG_CLEAR_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_CECS) || \\\r\n ((RNG_FLAG) == RNG_FLAG_SECS))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup RNG_interrupts_definition \r\n * @{\r\n */ \r\n#define RNG_IT_CEI ((uint8_t)0x20) /*!< Clock error interrupt */\r\n#define RNG_IT_SEI ((uint8_t)0x40) /*!< Seed error interrupt */\r\n\r\n#define IS_RNG_IT(IT) ((((IT) & (uint8_t)0x9F) == 0x00) && ((IT) != 0x00))\r\n#define IS_RNG_GET_IT(RNG_IT) (((RNG_IT) == RNG_IT_CEI) || ((RNG_IT) == RNG_IT_SEI))\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/ \r\n\r\n/* Function used to set the RNG configuration to the default reset state *****/ \r\nvoid RNG_DeInit(void);\r\n\r\n/* Configuration function *****************************************************/\r\nvoid RNG_Cmd(FunctionalState NewState);\r\n\r\n/* Get 32 bit Random number function ******************************************/\r\nuint32_t RNG_GetRandomNumber(void);\r\n\r\n/* Interrupts and flags management functions **********************************/\r\nvoid RNG_ITConfig(FunctionalState NewState);\r\nFlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG);\r\nvoid RNG_ClearFlag(uint8_t RNG_FLAG);\r\nITStatus RNG_GetITStatus(uint8_t RNG_IT);\r\nvoid RNG_ClearITPendingBit(uint8_t RNG_IT);\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /*__STM32F4xx_RNG_H */\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rtc.h", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_rtc.h\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file contains all the functions prototypes for the RTC firmware\r\n * library.\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F4xx_RTC_H\r\n#define __STM32F4xx_RTC_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @addtogroup RTC\r\n * @{\r\n */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n\r\n/** \r\n * @brief RTC Init structures definition \r\n */ \r\ntypedef struct\r\n{\r\n uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format.\r\n This parameter can be a value of @ref RTC_Hour_Formats */\r\n \r\n uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.\r\n This parameter must be set to a value lower than 0x7F */\r\n \r\n uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.\r\n This parameter must be set to a value lower than 0x7FFF */\r\n}RTC_InitTypeDef;\r\n\r\n/** \r\n * @brief RTC Time structure definition \r\n */\r\ntypedef struct\r\n{\r\n uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour.\r\n This parameter must be set to a value in the 0-12 range\r\n if the RTC_HourFormat_12 is selected or 0-23 range if\r\n the RTC_HourFormat_24 is selected. */\r\n\r\n uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes.\r\n This parameter must be set to a value in the 0-59 range. */\r\n \r\n uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds.\r\n This parameter must be set to a value in the 0-59 range. */\r\n\r\n uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time.\r\n This parameter can be a value of @ref RTC_AM_PM_Definitions */\r\n}RTC_TimeTypeDef; \r\n\r\n/** \r\n * @brief RTC Date structure definition \r\n */\r\ntypedef struct\r\n{\r\n uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.\r\n This parameter can be a value of @ref RTC_WeekDay_Definitions */\r\n \r\n uint8_t RTC_Month; /*!< Specifies the RTC Date Month (in BCD format).\r\n This parameter can be a value of @ref RTC_Month_Date_Definitions */\r\n\r\n uint8_t RTC_Date; /*!< Specifies the RTC Date.\r\n This parameter must be set to a value in the 1-31 range. */\r\n \r\n uint8_t RTC_Year; /*!< Specifies the RTC Date Year.\r\n This parameter must be set to a value in the 0-99 range. */\r\n}RTC_DateTypeDef;\r\n\r\n/** \r\n * @brief RTC Alarm structure definition \r\n */\r\ntypedef struct\r\n{\r\n RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */\r\n\r\n uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks.\r\n This parameter can be a value of @ref RTC_AlarmMask_Definitions */\r\n\r\n uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.\r\n This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */\r\n \r\n uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.\r\n If the Alarm Date is selected, this parameter\r\n must be set to a value in the 1-31 range.\r\n If the Alarm WeekDay is selected, this \r\n parameter can be a value of @ref RTC_WeekDay_Definitions */\r\n}RTC_AlarmTypeDef;\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup RTC_Exported_Constants\r\n * @{\r\n */ \r\n\r\n\r\n/** @defgroup RTC_Hour_Formats \r\n * @{\r\n */ \r\n#define RTC_HourFormat_24 ((uint32_t)0x00000000)\r\n#define RTC_HourFormat_12 ((uint32_t)0x00000040)\r\n#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \\\r\n ((FORMAT) == RTC_HourFormat_24))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup RTC_Asynchronous_Predivider \r\n * @{\r\n */ \r\n#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F)\r\n \r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup RTC_Synchronous_Predivider \r\n * @{\r\n */ \r\n#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF)\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup RTC_Time_Definitions \r\n * @{\r\n */ \r\n#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))\r\n#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23)\r\n#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)\r\n#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup RTC_AM_PM_Definitions \r\n * @{\r\n */ \r\n#define RTC_H12_AM ((uint8_t)0x00)\r\n#define RTC_H12_PM ((uint8_t)0x40)\r\n#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup RTC_Year_Date_Definitions \r\n * @{\r\n */ \r\n#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup RTC_Month_Date_Definitions \r\n * @{\r\n */ \r\n\r\n/* Coded in BCD format */\r\n#define RTC_Month_January ((uint8_t)0x01)\r\n#define RTC_Month_February ((uint8_t)0x02)\r\n#define RTC_Month_March ((uint8_t)0x03)\r\n#define RTC_Month_April ((uint8_t)0x04)\r\n#define RTC_Month_May ((uint8_t)0x05)\r\n#define RTC_Month_June ((uint8_t)0x06)\r\n#define RTC_Month_July ((uint8_t)0x07)\r\n#define RTC_Month_August ((uint8_t)0x08)\r\n#define RTC_Month_September ((uint8_t)0x09)\r\n#define RTC_Month_October ((uint8_t)0x10)\r\n#define RTC_Month_November ((uint8_t)0x11)\r\n#define RTC_Month_December ((uint8_t)0x12)\r\n#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12))\r\n#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31))\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup RTC_WeekDay_Definitions \r\n * @{\r\n */ \r\n \r\n#define RTC_Weekday_Monday ((uint8_t)0x01)\r\n#define RTC_Weekday_Tuesday ((uint8_t)0x02)\r\n#define RTC_Weekday_Wednesday ((uint8_t)0x03)\r\n#define RTC_Weekday_Thursday ((uint8_t)0x04)\r\n#define RTC_Weekday_Friday ((uint8_t)0x05)\r\n#define RTC_Weekday_Saturday ((uint8_t)0x06)\r\n#define RTC_Weekday_Sunday ((uint8_t)0x07)\r\n#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \\\r\n ((WEEKDAY) == RTC_Weekday_Tuesday) || \\\r\n ((WEEKDAY) == RTC_Weekday_Wednesday) || \\\r\n ((WEEKDAY) == RTC_Weekday_Thursday) || \\\r\n ((WEEKDAY) == RTC_Weekday_Friday) || \\\r\n ((WEEKDAY) == RTC_Weekday_Saturday) || \\\r\n ((WEEKDAY) == RTC_Weekday_Sunday))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup RTC_Alarm_Definitions\r\n * @{\r\n */ \r\n#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))\r\n#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \\\r\n ((WEEKDAY) == RTC_Weekday_Tuesday) || \\\r\n ((WEEKDAY) == RTC_Weekday_Wednesday) || \\\r\n ((WEEKDAY) == RTC_Weekday_Thursday) || \\\r\n ((WEEKDAY) == RTC_Weekday_Friday) || \\\r\n ((WEEKDAY) == RTC_Weekday_Saturday) || \\\r\n ((WEEKDAY) == RTC_Weekday_Sunday))\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup RTC_AlarmDateWeekDay_Definitions \r\n * @{\r\n */ \r\n#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000)\r\n#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000)\r\n\r\n#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \\\r\n ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup RTC_AlarmMask_Definitions \r\n * @{\r\n */ \r\n#define RTC_AlarmMask_None ((uint32_t)0x00000000)\r\n#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000)\r\n#define RTC_AlarmMask_Hours ((uint32_t)0x00800000)\r\n#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000)\r\n#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080)\r\n#define RTC_AlarmMask_All ((uint32_t)0x80808080)\r\n#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup RTC_Alarms_Definitions \r\n * @{\r\n */ \r\n#define RTC_Alarm_A ((uint32_t)0x00000100)\r\n#define RTC_Alarm_B ((uint32_t)0x00000200)\r\n#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B))\r\n#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET)\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions\r\n * @{\r\n */ \r\n#define RTC_AlarmSubSecondMask_All ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. \r\n There is no comparison on sub seconds \r\n for Alarm */\r\n#define RTC_AlarmSubSecondMask_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm \r\n comparison. Only SS[0] is compared. */\r\n#define RTC_AlarmSubSecondMask_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm \r\n comparison. Only SS[1:0] are compared */\r\n#define RTC_AlarmSubSecondMask_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm \r\n comparison. Only SS[2:0] are compared */\r\n#define RTC_AlarmSubSecondMask_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm \r\n comparison. Only SS[3:0] are compared */\r\n#define RTC_AlarmSubSecondMask_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm \r\n comparison. Only SS[4:0] are compared */\r\n#define RTC_AlarmSubSecondMask_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm \r\n comparison. Only SS[5:0] are compared */\r\n#define RTC_AlarmSubSecondMask_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm \r\n comparison. Only SS[6:0] are compared */\r\n#define RTC_AlarmSubSecondMask_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm \r\n comparison. Only SS[7:0] are compared */\r\n#define RTC_AlarmSubSecondMask_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm \r\n comparison. Only SS[8:0] are compared */\r\n#define RTC_AlarmSubSecondMask_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm \r\n comparison. Only SS[9:0] are compared */\r\n#define RTC_AlarmSubSecondMask_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm \r\n comparison. Only SS[10:0] are compared */\r\n#define RTC_AlarmSubSecondMask_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm \r\n comparison.Only SS[11:0] are compared */\r\n#define RTC_AlarmSubSecondMask_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm \r\n comparison. Only SS[12:0] are compared */\r\n#define RTC_AlarmSubSecondMask_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm \r\n comparison.Only SS[13:0] are compared */\r\n#define RTC_AlarmSubSecondMask_None ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match \r\n to activate alarm. */\r\n#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \\\r\n ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \\\r\n ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \\\r\n ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \\\r\n ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \\\r\n ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \\\r\n ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \\\r\n ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \\\r\n ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \\\r\n ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \\\r\n ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \\\r\n ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \\\r\n ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \\\r\n ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \\\r\n ((MASK) == RTC_AlarmSubSecondMask_SS14) || \\\r\n ((MASK) == RTC_AlarmSubSecondMask_None))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup RTC_Alarm_Sub_Seconds_Value\r\n * @{\r\n */ \r\n\r\n#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup RTC_Wakeup_Timer_Definitions \r\n * @{\r\n */ \r\n#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000)\r\n#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001)\r\n#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002)\r\n#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003)\r\n#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004)\r\n#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006)\r\n#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \\\r\n ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \\\r\n ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \\\r\n ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \\\r\n ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \\\r\n ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))\r\n#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup RTC_Time_Stamp_Edges_definitions \r\n * @{\r\n */ \r\n#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000)\r\n#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008)\r\n#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \\\r\n ((EDGE) == RTC_TimeStampEdge_Falling))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup RTC_Output_selection_Definitions \r\n * @{\r\n */ \r\n#define RTC_Output_Disable ((uint32_t)0x00000000)\r\n#define RTC_Output_AlarmA ((uint32_t)0x00200000)\r\n#define RTC_Output_AlarmB ((uint32_t)0x00400000)\r\n#define RTC_Output_WakeUp ((uint32_t)0x00600000)\r\n \r\n#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \\\r\n ((OUTPUT) == RTC_Output_AlarmA) || \\\r\n ((OUTPUT) == RTC_Output_AlarmB) || \\\r\n ((OUTPUT) == RTC_Output_WakeUp))\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup RTC_Output_Polarity_Definitions \r\n * @{\r\n */ \r\n#define RTC_OutputPolarity_High ((uint32_t)0x00000000)\r\n#define RTC_OutputPolarity_Low ((uint32_t)0x00100000)\r\n#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \\\r\n ((POL) == RTC_OutputPolarity_Low))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup RTC_Digital_Calibration_Definitions \r\n * @{\r\n */ \r\n#define RTC_CalibSign_Positive ((uint32_t)0x00000000) \r\n#define RTC_CalibSign_Negative ((uint32_t)0x00000080)\r\n#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \\\r\n ((SIGN) == RTC_CalibSign_Negative))\r\n#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n /** @defgroup RTC_Calib_Output_selection_Definitions \r\n * @{\r\n */ \r\n#define RTC_CalibOutput_512Hz ((uint32_t)0x00000000) \r\n#define RTC_CalibOutput_1Hz ((uint32_t)0x00080000)\r\n#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \\\r\n ((OUTPUT) == RTC_CalibOutput_1Hz))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup RTC_Smooth_calib_period_Definitions \r\n * @{\r\n */ \r\n#define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation\r\n period is 32s, else 2exp20 RTCCLK seconds */\r\n#define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \r\n period is 16s, else 2exp19 RTCCLK seconds */\r\n#define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \r\n period is 8s, else 2exp18 RTCCLK seconds */\r\n#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \\\r\n ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \\\r\n ((PERIOD) == RTC_SmoothCalibPeriod_8sec))\r\n \r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions \r\n * @{\r\n */ \r\n#define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added \r\n during a X -second window = Y - CALM[8:0]. \r\n with Y = 512, 256, 128 when X = 32, 16, 8 */\r\n#define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited\r\n during a 32-second window = CALM[8:0]. */\r\n#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \\\r\n ((PLUS) == RTC_SmoothCalibPlusPulses_Reset))\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions \r\n * @{\r\n */ \r\n#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup RTC_DayLightSaving_Definitions \r\n * @{\r\n */ \r\n#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000)\r\n#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000)\r\n#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \\\r\n ((SAVE) == RTC_DayLightSaving_ADD1H))\r\n\r\n#define RTC_StoreOperation_Reset ((uint32_t)0x00000000)\r\n#define RTC_StoreOperation_Set ((uint32_t)0x00040000)\r\n#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \\\r\n ((OPERATION) == RTC_StoreOperation_Set))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup RTC_Tamper_Trigger_Definitions \r\n * @{\r\n */ \r\n#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000)\r\n#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001)\r\n#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000)\r\n#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001)\r\n#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \\\r\n ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \\\r\n ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \\\r\n ((TRIGGER) == RTC_TamperTrigger_HighLevel)) \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup RTC_Tamper_Filter_Definitions \r\n * @{\r\n */ \r\n#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */\r\n\r\n#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2 \r\n consecutive samples at the active level */\r\n#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4 \r\n consecutive samples at the active level */\r\n#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8 \r\n consecutive samples at the active leve. */\r\n#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \\\r\n ((FILTER) == RTC_TamperFilter_2Sample) || \\\r\n ((FILTER) == RTC_TamperFilter_4Sample) || \\\r\n ((FILTER) == RTC_TamperFilter_8Sample))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions \r\n * @{\r\n */ \r\n#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled\r\n with a frequency = RTCCLK / 32768 */\r\n#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled\r\n with a frequency = RTCCLK / 16384 */\r\n#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled\r\n with a frequency = RTCCLK / 8192 */\r\n#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled\r\n with a frequency = RTCCLK / 4096 */\r\n#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled\r\n with a frequency = RTCCLK / 2048 */\r\n#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled\r\n with a frequency = RTCCLK / 1024 */\r\n#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled\r\n with a frequency = RTCCLK / 512 */\r\n#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled\r\n with a frequency = RTCCLK / 256 */\r\n#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \\\r\n ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \\\r\n ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \\\r\n ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \\\r\n ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \\\r\n ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \\\r\n ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \\\r\n ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions \r\n * @{\r\n */ \r\n#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before \r\n sampling during 1 RTCCLK cycle */\r\n#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before \r\n sampling during 2 RTCCLK cycles */\r\n#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before \r\n sampling during 4 RTCCLK cycles */\r\n#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before \r\n sampling during 8 RTCCLK cycles */\r\n\r\n#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \\\r\n ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \\\r\n ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \\\r\n ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup RTC_Tamper_Pins_Definitions \r\n * @{\r\n */ \r\n#define RTC_Tamper_1 RTC_TAFCR_TAMP1E\r\n#define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1))\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup RTC_Tamper_Pin_Selection \r\n * @{\r\n */ \r\n#define RTC_TamperPin_PC13 ((uint32_t)0x00000000)\r\n#define RTC_TamperPin_PI8 ((uint32_t)0x00010000)\r\n#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TamperPin_PC13) || \\\r\n ((PIN) == RTC_TamperPin_PI8))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup RTC_TimeStamp_Pin_Selection \r\n * @{\r\n */ \r\n#define RTC_TimeStampPin_PC13 ((uint32_t)0x00000000)\r\n#define RTC_TimeStampPin_PI8 ((uint32_t)0x00020000)\r\n#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TimeStampPin_PC13) || \\\r\n ((PIN) == RTC_TimeStampPin_PI8))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup RTC_Output_Type_ALARM_OUT \r\n * @{\r\n */ \r\n#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000)\r\n#define RTC_OutputType_PushPull ((uint32_t)0x00040000)\r\n#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \\\r\n ((TYPE) == RTC_OutputType_PushPull))\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup RTC_Add_1_Second_Parameter_Definitions\r\n * @{\r\n */ \r\n#define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000)\r\n#define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000)\r\n#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \\\r\n ((SEL) == RTC_ShiftAdd1S_Set))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup RTC_Substract_Fraction_Of_Second_Value\r\n * @{\r\n */ \r\n#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup RTC_Backup_Registers_Definitions \r\n * @{\r\n */\r\n\r\n#define RTC_BKP_DR0 ((uint32_t)0x00000000)\r\n#define RTC_BKP_DR1 ((uint32_t)0x00000001)\r\n#define RTC_BKP_DR2 ((uint32_t)0x00000002)\r\n#define RTC_BKP_DR3 ((uint32_t)0x00000003)\r\n#define RTC_BKP_DR4 ((uint32_t)0x00000004)\r\n#define RTC_BKP_DR5 ((uint32_t)0x00000005)\r\n#define RTC_BKP_DR6 ((uint32_t)0x00000006)\r\n#define RTC_BKP_DR7 ((uint32_t)0x00000007)\r\n#define RTC_BKP_DR8 ((uint32_t)0x00000008)\r\n#define RTC_BKP_DR9 ((uint32_t)0x00000009)\r\n#define RTC_BKP_DR10 ((uint32_t)0x0000000A)\r\n#define RTC_BKP_DR11 ((uint32_t)0x0000000B)\r\n#define RTC_BKP_DR12 ((uint32_t)0x0000000C)\r\n#define RTC_BKP_DR13 ((uint32_t)0x0000000D)\r\n#define RTC_BKP_DR14 ((uint32_t)0x0000000E)\r\n#define RTC_BKP_DR15 ((uint32_t)0x0000000F)\r\n#define RTC_BKP_DR16 ((uint32_t)0x00000010)\r\n#define RTC_BKP_DR17 ((uint32_t)0x00000011)\r\n#define RTC_BKP_DR18 ((uint32_t)0x00000012)\r\n#define RTC_BKP_DR19 ((uint32_t)0x00000013)\r\n#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \\\r\n ((BKP) == RTC_BKP_DR1) || \\\r\n ((BKP) == RTC_BKP_DR2) || \\\r\n ((BKP) == RTC_BKP_DR3) || \\\r\n ((BKP) == RTC_BKP_DR4) || \\\r\n ((BKP) == RTC_BKP_DR5) || \\\r\n ((BKP) == RTC_BKP_DR6) || \\\r\n ((BKP) == RTC_BKP_DR7) || \\\r\n ((BKP) == RTC_BKP_DR8) || \\\r\n ((BKP) == RTC_BKP_DR9) || \\\r\n ((BKP) == RTC_BKP_DR10) || \\\r\n ((BKP) == RTC_BKP_DR11) || \\\r\n ((BKP) == RTC_BKP_DR12) || \\\r\n ((BKP) == RTC_BKP_DR13) || \\\r\n ((BKP) == RTC_BKP_DR14) || \\\r\n ((BKP) == RTC_BKP_DR15) || \\\r\n ((BKP) == RTC_BKP_DR16) || \\\r\n ((BKP) == RTC_BKP_DR17) || \\\r\n ((BKP) == RTC_BKP_DR18) || \\\r\n ((BKP) == RTC_BKP_DR19))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup RTC_Input_parameter_format_definitions \r\n * @{\r\n */ \r\n#define RTC_Format_BIN ((uint32_t)0x000000000)\r\n#define RTC_Format_BCD ((uint32_t)0x000000001)\r\n#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup RTC_Flags_Definitions \r\n * @{\r\n */ \r\n#define RTC_FLAG_RECALPF ((uint32_t)0x00010000)\r\n#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)\r\n#define RTC_FLAG_TSOVF ((uint32_t)0x00001000)\r\n#define RTC_FLAG_TSF ((uint32_t)0x00000800)\r\n#define RTC_FLAG_WUTF ((uint32_t)0x00000400)\r\n#define RTC_FLAG_ALRBF ((uint32_t)0x00000200)\r\n#define RTC_FLAG_ALRAF ((uint32_t)0x00000100)\r\n#define RTC_FLAG_INITF ((uint32_t)0x00000040)\r\n#define RTC_FLAG_RSF ((uint32_t)0x00000020)\r\n#define RTC_FLAG_INITS ((uint32_t)0x00000010)\r\n#define RTC_FLAG_SHPF ((uint32_t)0x00000008)\r\n#define RTC_FLAG_WUTWF ((uint32_t)0x00000004)\r\n#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002)\r\n#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001)\r\n#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \\\r\n ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \\\r\n ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \\\r\n ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \\\r\n ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \\\r\n ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_RECALPF) || \\\r\n ((FLAG) == RTC_FLAG_SHPF))\r\n#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup RTC_Interrupts_Definitions \r\n * @{\r\n */ \r\n#define RTC_IT_TS ((uint32_t)0x00008000)\r\n#define RTC_IT_WUT ((uint32_t)0x00004000)\r\n#define RTC_IT_ALRB ((uint32_t)0x00002000)\r\n#define RTC_IT_ALRA ((uint32_t)0x00001000)\r\n#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */\r\n#define RTC_IT_TAMP1 ((uint32_t)0x00020000)\r\n\r\n#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))\r\n#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \\\r\n ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \\\r\n ((IT) == RTC_IT_TAMP1))\r\n#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFD0FFF) == (uint32_t)RESET))\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup RTC_Legacy \r\n * @{\r\n */ \r\n#define RTC_DigitalCalibConfig RTC_CoarseCalibConfig\r\n#define RTC_DigitalCalibCmd RTC_CoarseCalibCmd\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/ \r\n\r\n/* Function used to set the RTC configuration to the default reset state *****/\r\nErrorStatus RTC_DeInit(void);\r\n\r\n/* Initialization and Configuration functions *********************************/\r\nErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);\r\nvoid RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);\r\nvoid RTC_WriteProtectionCmd(FunctionalState NewState);\r\nErrorStatus RTC_EnterInitMode(void);\r\nvoid RTC_ExitInitMode(void);\r\nErrorStatus RTC_WaitForSynchro(void);\r\nErrorStatus RTC_RefClockCmd(FunctionalState NewState);\r\nvoid RTC_BypassShadowCmd(FunctionalState NewState);\r\n\r\n/* Time and Date configuration functions **************************************/\r\nErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);\r\nvoid RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);\r\nvoid RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);\r\nuint32_t RTC_GetSubSecond(void);\r\nErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);\r\nvoid RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);\r\nvoid RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);\r\n\r\n/* Alarms (Alarm A and Alarm B) configuration functions **********************/\r\nvoid RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);\r\nvoid RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);\r\nvoid RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);\r\nErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);\r\nvoid RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask);\r\nuint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);\r\n\r\n/* WakeUp Timer configuration functions ***************************************/\r\nvoid RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock);\r\nvoid RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter);\r\nuint32_t RTC_GetWakeUpCounter(void);\r\nErrorStatus RTC_WakeUpCmd(FunctionalState NewState);\r\n\r\n/* Daylight Saving configuration functions ************************************/\r\nvoid RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);\r\nuint32_t RTC_GetStoreOperation(void);\r\n\r\n/* Output pin Configuration function ******************************************/\r\nvoid RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);\r\n\r\n/* Digital Calibration configuration functions *********************************/\r\nErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value);\r\nErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState);\r\nvoid RTC_CalibOutputCmd(FunctionalState NewState);\r\nvoid RTC_CalibOutputConfig(uint32_t RTC_CalibOutput);\r\nErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, \r\n uint32_t RTC_SmoothCalibPlusPulses,\r\n uint32_t RTC_SmouthCalibMinusPulsesValue);\r\n\r\n/* TimeStamp configuration functions ******************************************/\r\nvoid RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);\r\nvoid RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct,\r\n RTC_DateTypeDef* RTC_StampDateStruct);\r\nuint32_t RTC_GetTimeStampSubSecond(void);\r\n\r\n/* Tampers configuration functions ********************************************/\r\nvoid RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);\r\nvoid RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);\r\nvoid RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);\r\nvoid RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);\r\nvoid RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);\r\nvoid RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);\r\nvoid RTC_TamperPullUpCmd(FunctionalState NewState);\r\n\r\n/* Backup Data Registers configuration functions ******************************/\r\nvoid RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);\r\nuint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);\r\n\r\n/* RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration\r\n functions ******************************************************************/\r\nvoid RTC_TamperPinSelection(uint32_t RTC_TamperPin);\r\nvoid RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin);\r\nvoid RTC_OutputTypeConfig(uint32_t RTC_OutputType);\r\n\r\n/* RTC_Shift_control_synchonisation_functions *********************************/\r\nErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);\r\n\r\n/* Interrupts and flags management functions **********************************/\r\nvoid RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);\r\nFlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);\r\nvoid RTC_ClearFlag(uint32_t RTC_FLAG);\r\nITStatus RTC_GetITStatus(uint32_t RTC_IT);\r\nvoid RTC_ClearITPendingBit(uint32_t RTC_IT);\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /*__STM32F4xx_RTC_H */\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sdio.h", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_sdio.h\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file contains all the functions prototypes for the SDIO firmware\r\n * library.\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F4xx_SDIO_H\r\n#define __STM32F4xx_SDIO_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @addtogroup SDIO\r\n * @{\r\n */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n\r\ntypedef struct\r\n{\r\n uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.\r\n This parameter can be a value of @ref SDIO_Clock_Edge */\r\n\r\n uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is\r\n enabled or disabled.\r\n This parameter can be a value of @ref SDIO_Clock_Bypass */\r\n\r\n uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or\r\n disabled when the bus is idle.\r\n This parameter can be a value of @ref SDIO_Clock_Power_Save */\r\n\r\n uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width.\r\n This parameter can be a value of @ref SDIO_Bus_Wide */\r\n\r\n uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.\r\n This parameter can be a value of @ref SDIO_Hardware_Flow_Control */\r\n\r\n uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.\r\n This parameter can be a value between 0x00 and 0xFF. */\r\n \r\n} SDIO_InitTypeDef;\r\n\r\ntypedef struct\r\n{\r\n uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent\r\n to a card as part of a command message. If a command\r\n contains an argument, it must be loaded into this register\r\n before writing the command to the command register */\r\n\r\n uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */\r\n\r\n uint32_t SDIO_Response; /*!< Specifies the SDIO response type.\r\n This parameter can be a value of @ref SDIO_Response_Type */\r\n\r\n uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.\r\n This parameter can be a value of @ref SDIO_Wait_Interrupt_State */\r\n\r\n uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)\r\n is enabled or disabled.\r\n This parameter can be a value of @ref SDIO_CPSM_State */\r\n} SDIO_CmdInitTypeDef;\r\n\r\ntypedef struct\r\n{\r\n uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */\r\n\r\n uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */\r\n \r\n uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer.\r\n This parameter can be a value of @ref SDIO_Data_Block_Size */\r\n \r\n uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer\r\n is a read or write.\r\n This parameter can be a value of @ref SDIO_Transfer_Direction */\r\n \r\n uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode.\r\n This parameter can be a value of @ref SDIO_Transfer_Type */\r\n \r\n uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)\r\n is enabled or disabled.\r\n This parameter can be a value of @ref SDIO_DPSM_State */\r\n} SDIO_DataInitTypeDef;\r\n\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup SDIO_Exported_Constants\r\n * @{\r\n */\r\n\r\n/** @defgroup SDIO_Clock_Edge \r\n * @{\r\n */\r\n\r\n#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)\r\n#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)\r\n#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \\\r\n ((EDGE) == SDIO_ClockEdge_Falling))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SDIO_Clock_Bypass \r\n * @{\r\n */\r\n\r\n#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)\r\n#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) \r\n#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \\\r\n ((BYPASS) == SDIO_ClockBypass_Enable))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup SDIO_Clock_Power_Save \r\n * @{\r\n */\r\n\r\n#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)\r\n#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) \r\n#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \\\r\n ((SAVE) == SDIO_ClockPowerSave_Enable))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SDIO_Bus_Wide \r\n * @{\r\n */\r\n\r\n#define SDIO_BusWide_1b ((uint32_t)0x00000000)\r\n#define SDIO_BusWide_4b ((uint32_t)0x00000800)\r\n#define SDIO_BusWide_8b ((uint32_t)0x00001000)\r\n#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \\\r\n ((WIDE) == SDIO_BusWide_8b))\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SDIO_Hardware_Flow_Control \r\n * @{\r\n */\r\n\r\n#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)\r\n#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)\r\n#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \\\r\n ((CONTROL) == SDIO_HardwareFlowControl_Enable))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SDIO_Power_State \r\n * @{\r\n */\r\n\r\n#define SDIO_PowerState_OFF ((uint32_t)0x00000000)\r\n#define SDIO_PowerState_ON ((uint32_t)0x00000003)\r\n#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup SDIO_Interrupt_sources\r\n * @{\r\n */\r\n\r\n#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)\r\n#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)\r\n#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)\r\n#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)\r\n#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)\r\n#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)\r\n#define SDIO_IT_CMDREND ((uint32_t)0x00000040)\r\n#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)\r\n#define SDIO_IT_DATAEND ((uint32_t)0x00000100)\r\n#define SDIO_IT_STBITERR ((uint32_t)0x00000200)\r\n#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)\r\n#define SDIO_IT_CMDACT ((uint32_t)0x00000800)\r\n#define SDIO_IT_TXACT ((uint32_t)0x00001000)\r\n#define SDIO_IT_RXACT ((uint32_t)0x00002000)\r\n#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)\r\n#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)\r\n#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)\r\n#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)\r\n#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)\r\n#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)\r\n#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)\r\n#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)\r\n#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)\r\n#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)\r\n#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup SDIO_Command_Index\r\n * @{\r\n */\r\n\r\n#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SDIO_Response_Type\r\n * @{\r\n */\r\n\r\n#define SDIO_Response_No ((uint32_t)0x00000000)\r\n#define SDIO_Response_Short ((uint32_t)0x00000040)\r\n#define SDIO_Response_Long ((uint32_t)0x000000C0)\r\n#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \\\r\n ((RESPONSE) == SDIO_Response_Short) || \\\r\n ((RESPONSE) == SDIO_Response_Long))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SDIO_Wait_Interrupt_State\r\n * @{\r\n */\r\n\r\n#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */\r\n#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */\r\n#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */\r\n#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \\\r\n ((WAIT) == SDIO_Wait_Pend))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SDIO_CPSM_State\r\n * @{\r\n */\r\n\r\n#define SDIO_CPSM_Disable ((uint32_t)0x00000000)\r\n#define SDIO_CPSM_Enable ((uint32_t)0x00000400)\r\n#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup SDIO_Response_Registers\r\n * @{\r\n */\r\n\r\n#define SDIO_RESP1 ((uint32_t)0x00000000)\r\n#define SDIO_RESP2 ((uint32_t)0x00000004)\r\n#define SDIO_RESP3 ((uint32_t)0x00000008)\r\n#define SDIO_RESP4 ((uint32_t)0x0000000C)\r\n#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \\\r\n ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SDIO_Data_Length \r\n * @{\r\n */\r\n\r\n#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SDIO_Data_Block_Size \r\n * @{\r\n */\r\n\r\n#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)\r\n#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)\r\n#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)\r\n#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)\r\n#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)\r\n#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)\r\n#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)\r\n#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)\r\n#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)\r\n#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)\r\n#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)\r\n#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)\r\n#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)\r\n#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)\r\n#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)\r\n#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \\\r\n ((SIZE) == SDIO_DataBlockSize_2b) || \\\r\n ((SIZE) == SDIO_DataBlockSize_4b) || \\\r\n ((SIZE) == SDIO_DataBlockSize_8b) || \\\r\n ((SIZE) == SDIO_DataBlockSize_16b) || \\\r\n ((SIZE) == SDIO_DataBlockSize_32b) || \\\r\n ((SIZE) == SDIO_DataBlockSize_64b) || \\\r\n ((SIZE) == SDIO_DataBlockSize_128b) || \\\r\n ((SIZE) == SDIO_DataBlockSize_256b) || \\\r\n ((SIZE) == SDIO_DataBlockSize_512b) || \\\r\n ((SIZE) == SDIO_DataBlockSize_1024b) || \\\r\n ((SIZE) == SDIO_DataBlockSize_2048b) || \\\r\n ((SIZE) == SDIO_DataBlockSize_4096b) || \\\r\n ((SIZE) == SDIO_DataBlockSize_8192b) || \\\r\n ((SIZE) == SDIO_DataBlockSize_16384b)) \r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SDIO_Transfer_Direction \r\n * @{\r\n */\r\n\r\n#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)\r\n#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)\r\n#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \\\r\n ((DIR) == SDIO_TransferDir_ToSDIO))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SDIO_Transfer_Type \r\n * @{\r\n */\r\n\r\n#define SDIO_TransferMode_Block ((uint32_t)0x00000000)\r\n#define SDIO_TransferMode_Stream ((uint32_t)0x00000004)\r\n#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \\\r\n ((MODE) == SDIO_TransferMode_Block))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SDIO_DPSM_State \r\n * @{\r\n */\r\n\r\n#define SDIO_DPSM_Disable ((uint32_t)0x00000000)\r\n#define SDIO_DPSM_Enable ((uint32_t)0x00000001)\r\n#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SDIO_Flags \r\n * @{\r\n */\r\n\r\n#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)\r\n#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)\r\n#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)\r\n#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)\r\n#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)\r\n#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)\r\n#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)\r\n#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)\r\n#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)\r\n#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)\r\n#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)\r\n#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)\r\n#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)\r\n#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)\r\n#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)\r\n#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)\r\n#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)\r\n#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)\r\n#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)\r\n#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)\r\n#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)\r\n#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)\r\n#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)\r\n#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)\r\n#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \\\r\n ((FLAG) == SDIO_FLAG_DCRCFAIL) || \\\r\n ((FLAG) == SDIO_FLAG_CTIMEOUT) || \\\r\n ((FLAG) == SDIO_FLAG_DTIMEOUT) || \\\r\n ((FLAG) == SDIO_FLAG_TXUNDERR) || \\\r\n ((FLAG) == SDIO_FLAG_RXOVERR) || \\\r\n ((FLAG) == SDIO_FLAG_CMDREND) || \\\r\n ((FLAG) == SDIO_FLAG_CMDSENT) || \\\r\n ((FLAG) == SDIO_FLAG_DATAEND) || \\\r\n ((FLAG) == SDIO_FLAG_STBITERR) || \\\r\n ((FLAG) == SDIO_FLAG_DBCKEND) || \\\r\n ((FLAG) == SDIO_FLAG_CMDACT) || \\\r\n ((FLAG) == SDIO_FLAG_TXACT) || \\\r\n ((FLAG) == SDIO_FLAG_RXACT) || \\\r\n ((FLAG) == SDIO_FLAG_TXFIFOHE) || \\\r\n ((FLAG) == SDIO_FLAG_RXFIFOHF) || \\\r\n ((FLAG) == SDIO_FLAG_TXFIFOF) || \\\r\n ((FLAG) == SDIO_FLAG_RXFIFOF) || \\\r\n ((FLAG) == SDIO_FLAG_TXFIFOE) || \\\r\n ((FLAG) == SDIO_FLAG_RXFIFOE) || \\\r\n ((FLAG) == SDIO_FLAG_TXDAVL) || \\\r\n ((FLAG) == SDIO_FLAG_RXDAVL) || \\\r\n ((FLAG) == SDIO_FLAG_SDIOIT) || \\\r\n ((FLAG) == SDIO_FLAG_CEATAEND))\r\n\r\n#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))\r\n\r\n#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \\\r\n ((IT) == SDIO_IT_DCRCFAIL) || \\\r\n ((IT) == SDIO_IT_CTIMEOUT) || \\\r\n ((IT) == SDIO_IT_DTIMEOUT) || \\\r\n ((IT) == SDIO_IT_TXUNDERR) || \\\r\n ((IT) == SDIO_IT_RXOVERR) || \\\r\n ((IT) == SDIO_IT_CMDREND) || \\\r\n ((IT) == SDIO_IT_CMDSENT) || \\\r\n ((IT) == SDIO_IT_DATAEND) || \\\r\n ((IT) == SDIO_IT_STBITERR) || \\\r\n ((IT) == SDIO_IT_DBCKEND) || \\\r\n ((IT) == SDIO_IT_CMDACT) || \\\r\n ((IT) == SDIO_IT_TXACT) || \\\r\n ((IT) == SDIO_IT_RXACT) || \\\r\n ((IT) == SDIO_IT_TXFIFOHE) || \\\r\n ((IT) == SDIO_IT_RXFIFOHF) || \\\r\n ((IT) == SDIO_IT_TXFIFOF) || \\\r\n ((IT) == SDIO_IT_RXFIFOF) || \\\r\n ((IT) == SDIO_IT_TXFIFOE) || \\\r\n ((IT) == SDIO_IT_RXFIFOE) || \\\r\n ((IT) == SDIO_IT_TXDAVL) || \\\r\n ((IT) == SDIO_IT_RXDAVL) || \\\r\n ((IT) == SDIO_IT_SDIOIT) || \\\r\n ((IT) == SDIO_IT_CEATAEND))\r\n\r\n#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SDIO_Read_Wait_Mode \r\n * @{\r\n */\r\n\r\n#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000000)\r\n#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000001)\r\n#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \\\r\n ((MODE) == SDIO_ReadWaitMode_DATA2))\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n/* Function used to set the SDIO configuration to the default reset state ****/\r\nvoid SDIO_DeInit(void);\r\n\r\n/* Initialization and Configuration functions *********************************/\r\nvoid SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);\r\nvoid SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);\r\nvoid SDIO_ClockCmd(FunctionalState NewState);\r\nvoid SDIO_SetPowerState(uint32_t SDIO_PowerState);\r\nuint32_t SDIO_GetPowerState(void);\r\n\r\n/* Command path state machine (CPSM) management functions *********************/\r\nvoid SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);\r\nvoid SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);\r\nuint8_t SDIO_GetCommandResponse(void);\r\nuint32_t SDIO_GetResponse(uint32_t SDIO_RESP);\r\n\r\n/* Data path state machine (DPSM) management functions ************************/\r\nvoid SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);\r\nvoid SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);\r\nuint32_t SDIO_GetDataCounter(void);\r\nuint32_t SDIO_ReadData(void);\r\nvoid SDIO_WriteData(uint32_t Data);\r\nuint32_t SDIO_GetFIFOCount(void);\r\n\r\n/* SDIO IO Cards mode management functions ************************************/\r\nvoid SDIO_StartSDIOReadWait(FunctionalState NewState);\r\nvoid SDIO_StopSDIOReadWait(FunctionalState NewState);\r\nvoid SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);\r\nvoid SDIO_SetSDIOOperation(FunctionalState NewState);\r\nvoid SDIO_SendSDIOSuspendCmd(FunctionalState NewState);\r\n\r\n/* CE-ATA mode management functions *******************************************/\r\nvoid SDIO_CommandCompletionCmd(FunctionalState NewState);\r\nvoid SDIO_CEATAITCmd(FunctionalState NewState);\r\nvoid SDIO_SendCEATACmd(FunctionalState NewState);\r\n\r\n/* DMA transfers management functions *****************************************/\r\nvoid SDIO_DMACmd(FunctionalState NewState);\r\n\r\n/* Interrupts and flags management functions **********************************/\r\nvoid SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);\r\nFlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);\r\nvoid SDIO_ClearFlag(uint32_t SDIO_FLAG);\r\nITStatus SDIO_GetITStatus(uint32_t SDIO_IT);\r\nvoid SDIO_ClearITPendingBit(uint32_t SDIO_IT);\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F4xx_SDIO_H */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_spi.h", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_spi.h\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file contains all the functions prototypes for the SPI \r\n * firmware library.\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F4xx_SPI_H\r\n#define __STM32F4xx_SPI_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @addtogroup SPI\r\n * @{\r\n */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n\r\n/** \r\n * @brief SPI Init structure definition \r\n */\r\n\r\ntypedef struct\r\n{\r\n uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.\r\n This parameter can be a value of @ref SPI_data_direction */\r\n\r\n uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.\r\n This parameter can be a value of @ref SPI_mode */\r\n\r\n uint16_t SPI_DataSize; /*!< Specifies the SPI data size.\r\n This parameter can be a value of @ref SPI_data_size */\r\n\r\n uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.\r\n This parameter can be a value of @ref SPI_Clock_Polarity */\r\n\r\n uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.\r\n This parameter can be a value of @ref SPI_Clock_Phase */\r\n\r\n uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by\r\n hardware (NSS pin) or by software using the SSI bit.\r\n This parameter can be a value of @ref SPI_Slave_Select_management */\r\n \r\n uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be\r\n used to configure the transmit and receive SCK clock.\r\n This parameter can be a value of @ref SPI_BaudRate_Prescaler\r\n @note The communication clock is derived from the master\r\n clock. The slave clock does not need to be set. */\r\n\r\n uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.\r\n This parameter can be a value of @ref SPI_MSB_LSB_transmission */\r\n\r\n uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */\r\n}SPI_InitTypeDef;\r\n\r\n/** \r\n * @brief I2S Init structure definition \r\n */\r\n\r\ntypedef struct\r\n{\r\n\r\n uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.\r\n This parameter can be a value of @ref I2S_Mode */\r\n\r\n uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.\r\n This parameter can be a value of @ref I2S_Standard */\r\n\r\n uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.\r\n This parameter can be a value of @ref I2S_Data_Format */\r\n\r\n uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.\r\n This parameter can be a value of @ref I2S_MCLK_Output */\r\n\r\n uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.\r\n This parameter can be a value of @ref I2S_Audio_Frequency */\r\n\r\n uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.\r\n This parameter can be a value of @ref I2S_Clock_Polarity */\r\n}I2S_InitTypeDef;\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup SPI_Exported_Constants\r\n * @{\r\n */\r\n\r\n#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \\\r\n ((PERIPH) == SPI2) || \\\r\n ((PERIPH) == SPI3))\r\n\r\n#define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \\\r\n ((PERIPH) == SPI2) || \\\r\n ((PERIPH) == SPI3) || \\\r\n ((PERIPH) == I2S2ext) || \\\r\n ((PERIPH) == I2S3ext))\r\n\r\n#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \\\r\n ((PERIPH) == SPI3))\r\n\r\n#define IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || \\\r\n ((PERIPH) == SPI3) || \\\r\n ((PERIPH) == I2S2ext) || \\\r\n ((PERIPH) == I2S3ext))\r\n\r\n#define IS_I2S_EXT_PERIPH(PERIPH) (((PERIPH) == I2S2ext) || \\\r\n ((PERIPH) == I2S3ext))\r\n\r\n\r\n/** @defgroup SPI_data_direction \r\n * @{\r\n */\r\n \r\n#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)\r\n#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)\r\n#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)\r\n#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)\r\n#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \\\r\n ((MODE) == SPI_Direction_2Lines_RxOnly) || \\\r\n ((MODE) == SPI_Direction_1Line_Rx) || \\\r\n ((MODE) == SPI_Direction_1Line_Tx))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SPI_mode \r\n * @{\r\n */\r\n\r\n#define SPI_Mode_Master ((uint16_t)0x0104)\r\n#define SPI_Mode_Slave ((uint16_t)0x0000)\r\n#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \\\r\n ((MODE) == SPI_Mode_Slave))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SPI_data_size \r\n * @{\r\n */\r\n\r\n#define SPI_DataSize_16b ((uint16_t)0x0800)\r\n#define SPI_DataSize_8b ((uint16_t)0x0000)\r\n#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \\\r\n ((DATASIZE) == SPI_DataSize_8b))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup SPI_Clock_Polarity \r\n * @{\r\n */\r\n\r\n#define SPI_CPOL_Low ((uint16_t)0x0000)\r\n#define SPI_CPOL_High ((uint16_t)0x0002)\r\n#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \\\r\n ((CPOL) == SPI_CPOL_High))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SPI_Clock_Phase \r\n * @{\r\n */\r\n\r\n#define SPI_CPHA_1Edge ((uint16_t)0x0000)\r\n#define SPI_CPHA_2Edge ((uint16_t)0x0001)\r\n#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \\\r\n ((CPHA) == SPI_CPHA_2Edge))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SPI_Slave_Select_management \r\n * @{\r\n */\r\n\r\n#define SPI_NSS_Soft ((uint16_t)0x0200)\r\n#define SPI_NSS_Hard ((uint16_t)0x0000)\r\n#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \\\r\n ((NSS) == SPI_NSS_Hard))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup SPI_BaudRate_Prescaler \r\n * @{\r\n */\r\n\r\n#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)\r\n#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)\r\n#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)\r\n#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)\r\n#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)\r\n#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)\r\n#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)\r\n#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)\r\n#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \\\r\n ((PRESCALER) == SPI_BaudRatePrescaler_4) || \\\r\n ((PRESCALER) == SPI_BaudRatePrescaler_8) || \\\r\n ((PRESCALER) == SPI_BaudRatePrescaler_16) || \\\r\n ((PRESCALER) == SPI_BaudRatePrescaler_32) || \\\r\n ((PRESCALER) == SPI_BaudRatePrescaler_64) || \\\r\n ((PRESCALER) == SPI_BaudRatePrescaler_128) || \\\r\n ((PRESCALER) == SPI_BaudRatePrescaler_256))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup SPI_MSB_LSB_transmission \r\n * @{\r\n */\r\n\r\n#define SPI_FirstBit_MSB ((uint16_t)0x0000)\r\n#define SPI_FirstBit_LSB ((uint16_t)0x0080)\r\n#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \\\r\n ((BIT) == SPI_FirstBit_LSB))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SPI_I2S_Mode \r\n * @{\r\n */\r\n\r\n#define I2S_Mode_SlaveTx ((uint16_t)0x0000)\r\n#define I2S_Mode_SlaveRx ((uint16_t)0x0100)\r\n#define I2S_Mode_MasterTx ((uint16_t)0x0200)\r\n#define I2S_Mode_MasterRx ((uint16_t)0x0300)\r\n#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \\\r\n ((MODE) == I2S_Mode_SlaveRx) || \\\r\n ((MODE) == I2S_Mode_MasterTx)|| \\\r\n ((MODE) == I2S_Mode_MasterRx))\r\n/**\r\n * @}\r\n */\r\n \r\n\r\n/** @defgroup SPI_I2S_Standard \r\n * @{\r\n */\r\n\r\n#define I2S_Standard_Phillips ((uint16_t)0x0000)\r\n#define I2S_Standard_MSB ((uint16_t)0x0010)\r\n#define I2S_Standard_LSB ((uint16_t)0x0020)\r\n#define I2S_Standard_PCMShort ((uint16_t)0x0030)\r\n#define I2S_Standard_PCMLong ((uint16_t)0x00B0)\r\n#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \\\r\n ((STANDARD) == I2S_Standard_MSB) || \\\r\n ((STANDARD) == I2S_Standard_LSB) || \\\r\n ((STANDARD) == I2S_Standard_PCMShort) || \\\r\n ((STANDARD) == I2S_Standard_PCMLong))\r\n/**\r\n * @}\r\n */\r\n \r\n/** @defgroup SPI_I2S_Data_Format \r\n * @{\r\n */\r\n\r\n#define I2S_DataFormat_16b ((uint16_t)0x0000)\r\n#define I2S_DataFormat_16bextended ((uint16_t)0x0001)\r\n#define I2S_DataFormat_24b ((uint16_t)0x0003)\r\n#define I2S_DataFormat_32b ((uint16_t)0x0005)\r\n#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \\\r\n ((FORMAT) == I2S_DataFormat_16bextended) || \\\r\n ((FORMAT) == I2S_DataFormat_24b) || \\\r\n ((FORMAT) == I2S_DataFormat_32b))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SPI_I2S_MCLK_Output \r\n * @{\r\n */\r\n\r\n#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)\r\n#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)\r\n#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \\\r\n ((OUTPUT) == I2S_MCLKOutput_Disable))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SPI_I2S_Audio_Frequency \r\n * @{\r\n */\r\n\r\n#define I2S_AudioFreq_192k ((uint32_t)192000)\r\n#define I2S_AudioFreq_96k ((uint32_t)96000)\r\n#define I2S_AudioFreq_48k ((uint32_t)48000)\r\n#define I2S_AudioFreq_44k ((uint32_t)44100)\r\n#define I2S_AudioFreq_32k ((uint32_t)32000)\r\n#define I2S_AudioFreq_22k ((uint32_t)22050)\r\n#define I2S_AudioFreq_16k ((uint32_t)16000)\r\n#define I2S_AudioFreq_11k ((uint32_t)11025)\r\n#define I2S_AudioFreq_8k ((uint32_t)8000)\r\n#define I2S_AudioFreq_Default ((uint32_t)2)\r\n\r\n#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \\\r\n ((FREQ) <= I2S_AudioFreq_192k)) || \\\r\n ((FREQ) == I2S_AudioFreq_Default))\r\n/**\r\n * @}\r\n */\r\n \r\n/** @defgroup SPI_I2S_Clock_Polarity \r\n * @{\r\n */\r\n\r\n#define I2S_CPOL_Low ((uint16_t)0x0000)\r\n#define I2S_CPOL_High ((uint16_t)0x0008)\r\n#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \\\r\n ((CPOL) == I2S_CPOL_High))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SPI_I2S_DMA_transfer_requests \r\n * @{\r\n */\r\n\r\n#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)\r\n#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)\r\n#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SPI_NSS_internal_software_management \r\n * @{\r\n */\r\n\r\n#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)\r\n#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)\r\n#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \\\r\n ((INTERNAL) == SPI_NSSInternalSoft_Reset))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SPI_CRC_Transmit_Receive \r\n * @{\r\n */\r\n\r\n#define SPI_CRC_Tx ((uint8_t)0x00)\r\n#define SPI_CRC_Rx ((uint8_t)0x01)\r\n#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SPI_direction_transmit_receive \r\n * @{\r\n */\r\n\r\n#define SPI_Direction_Rx ((uint16_t)0xBFFF)\r\n#define SPI_Direction_Tx ((uint16_t)0x4000)\r\n#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \\\r\n ((DIRECTION) == SPI_Direction_Tx))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SPI_I2S_interrupts_definition \r\n * @{\r\n */\r\n\r\n#define SPI_I2S_IT_TXE ((uint8_t)0x71)\r\n#define SPI_I2S_IT_RXNE ((uint8_t)0x60)\r\n#define SPI_I2S_IT_ERR ((uint8_t)0x50)\r\n#define I2S_IT_UDR ((uint8_t)0x53)\r\n#define SPI_I2S_IT_TIFRFE ((uint8_t)0x58)\r\n\r\n#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \\\r\n ((IT) == SPI_I2S_IT_RXNE) || \\\r\n ((IT) == SPI_I2S_IT_ERR))\r\n\r\n#define SPI_I2S_IT_OVR ((uint8_t)0x56)\r\n#define SPI_IT_MODF ((uint8_t)0x55)\r\n#define SPI_IT_CRCERR ((uint8_t)0x54)\r\n\r\n#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))\r\n\r\n#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE)|| ((IT) == SPI_I2S_IT_TXE) || \\\r\n ((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \\\r\n ((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\\\r\n ((IT) == SPI_I2S_IT_TIFRFE))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SPI_I2S_flags_definition \r\n * @{\r\n */\r\n\r\n#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)\r\n#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)\r\n#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)\r\n#define I2S_FLAG_UDR ((uint16_t)0x0008)\r\n#define SPI_FLAG_CRCERR ((uint16_t)0x0010)\r\n#define SPI_FLAG_MODF ((uint16_t)0x0020)\r\n#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)\r\n#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)\r\n#define SPI_I2S_FLAG_TIFRFE ((uint16_t)0x0100)\r\n\r\n#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))\r\n#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \\\r\n ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \\\r\n ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \\\r\n ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \\\r\n ((FLAG) == SPI_I2S_FLAG_TIFRFE))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SPI_CRC_polynomial \r\n * @{\r\n */\r\n\r\n#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SPI_I2S_Legacy \r\n * @{\r\n */\r\n\r\n#define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx\r\n#define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx\r\n#define SPI_IT_TXE SPI_I2S_IT_TXE\r\n#define SPI_IT_RXNE SPI_I2S_IT_RXNE\r\n#define SPI_IT_ERR SPI_I2S_IT_ERR\r\n#define SPI_IT_OVR SPI_I2S_IT_OVR\r\n#define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE\r\n#define SPI_FLAG_TXE SPI_I2S_FLAG_TXE\r\n#define SPI_FLAG_OVR SPI_I2S_FLAG_OVR\r\n#define SPI_FLAG_BSY SPI_I2S_FLAG_BSY\r\n#define SPI_DeInit SPI_I2S_DeInit\r\n#define SPI_ITConfig SPI_I2S_ITConfig\r\n#define SPI_DMACmd SPI_I2S_DMACmd\r\n#define SPI_SendData SPI_I2S_SendData\r\n#define SPI_ReceiveData SPI_I2S_ReceiveData\r\n#define SPI_GetFlagStatus SPI_I2S_GetFlagStatus\r\n#define SPI_ClearFlag SPI_I2S_ClearFlag\r\n#define SPI_GetITStatus SPI_I2S_GetITStatus\r\n#define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit\r\n/**\r\n * @}\r\n */\r\n \r\n/**\r\n * @}\r\n */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/ \r\n\r\n/* Function used to set the SPI configuration to the default reset state *****/ \r\nvoid SPI_I2S_DeInit(SPI_TypeDef* SPIx);\r\n\r\n/* Initialization and Configuration functions *********************************/\r\nvoid SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);\r\nvoid I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);\r\nvoid SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);\r\nvoid I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);\r\nvoid SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r\nvoid I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r\nvoid SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);\r\nvoid SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);\r\nvoid SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);\r\nvoid SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r\nvoid SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r\n\r\nvoid I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct);\r\n\r\n/* Data transfers functions ***************************************************/ \r\nvoid SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);\r\nuint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);\r\n\r\n/* Hardware CRC Calculation functions *****************************************/\r\nvoid SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);\r\nvoid SPI_TransmitCRC(SPI_TypeDef* SPIx);\r\nuint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);\r\nuint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);\r\n\r\n/* DMA transfers management functions *****************************************/\r\nvoid SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);\r\n\r\n/* Interrupts and flags management functions **********************************/\r\nvoid SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);\r\nFlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r\nvoid SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r\nITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);\r\nvoid SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /*__STM32F4xx_SPI_H */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_syscfg.h", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_syscfg.h\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file contains all the functions prototypes for the SYSCFG firmware\r\n * library.\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F4xx_SYSCFG_H\r\n#define __STM32F4xx_SYSCFG_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @addtogroup SYSCFG\r\n * @{\r\n */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n \r\n/** @defgroup SYSCFG_Exported_Constants \r\n * @{\r\n */ \r\n\r\n/** @defgroup SYSCFG_EXTI_Port_Sources \r\n * @{\r\n */ \r\n#define EXTI_PortSourceGPIOA ((uint8_t)0x00)\r\n#define EXTI_PortSourceGPIOB ((uint8_t)0x01)\r\n#define EXTI_PortSourceGPIOC ((uint8_t)0x02)\r\n#define EXTI_PortSourceGPIOD ((uint8_t)0x03)\r\n#define EXTI_PortSourceGPIOE ((uint8_t)0x04)\r\n#define EXTI_PortSourceGPIOF ((uint8_t)0x05)\r\n#define EXTI_PortSourceGPIOG ((uint8_t)0x06)\r\n#define EXTI_PortSourceGPIOH ((uint8_t)0x07)\r\n#define EXTI_PortSourceGPIOI ((uint8_t)0x08)\r\n \r\n#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \\\r\n ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \\\r\n ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \\\r\n ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \\\r\n ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \\\r\n ((PORTSOURCE) == EXTI_PortSourceGPIOF) || \\\r\n ((PORTSOURCE) == EXTI_PortSourceGPIOG) || \\\r\n ((PORTSOURCE) == EXTI_PortSourceGPIOH) || \\\r\n ((PORTSOURCE) == EXTI_PortSourceGPIOI)) \r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup SYSCFG_EXTI_Pin_Sources \r\n * @{\r\n */ \r\n#define EXTI_PinSource0 ((uint8_t)0x00)\r\n#define EXTI_PinSource1 ((uint8_t)0x01)\r\n#define EXTI_PinSource2 ((uint8_t)0x02)\r\n#define EXTI_PinSource3 ((uint8_t)0x03)\r\n#define EXTI_PinSource4 ((uint8_t)0x04)\r\n#define EXTI_PinSource5 ((uint8_t)0x05)\r\n#define EXTI_PinSource6 ((uint8_t)0x06)\r\n#define EXTI_PinSource7 ((uint8_t)0x07)\r\n#define EXTI_PinSource8 ((uint8_t)0x08)\r\n#define EXTI_PinSource9 ((uint8_t)0x09)\r\n#define EXTI_PinSource10 ((uint8_t)0x0A)\r\n#define EXTI_PinSource11 ((uint8_t)0x0B)\r\n#define EXTI_PinSource12 ((uint8_t)0x0C)\r\n#define EXTI_PinSource13 ((uint8_t)0x0D)\r\n#define EXTI_PinSource14 ((uint8_t)0x0E)\r\n#define EXTI_PinSource15 ((uint8_t)0x0F)\r\n#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \\\r\n ((PINSOURCE) == EXTI_PinSource1) || \\\r\n ((PINSOURCE) == EXTI_PinSource2) || \\\r\n ((PINSOURCE) == EXTI_PinSource3) || \\\r\n ((PINSOURCE) == EXTI_PinSource4) || \\\r\n ((PINSOURCE) == EXTI_PinSource5) || \\\r\n ((PINSOURCE) == EXTI_PinSource6) || \\\r\n ((PINSOURCE) == EXTI_PinSource7) || \\\r\n ((PINSOURCE) == EXTI_PinSource8) || \\\r\n ((PINSOURCE) == EXTI_PinSource9) || \\\r\n ((PINSOURCE) == EXTI_PinSource10) || \\\r\n ((PINSOURCE) == EXTI_PinSource11) || \\\r\n ((PINSOURCE) == EXTI_PinSource12) || \\\r\n ((PINSOURCE) == EXTI_PinSource13) || \\\r\n ((PINSOURCE) == EXTI_PinSource14) || \\\r\n ((PINSOURCE) == EXTI_PinSource15))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup SYSCFG_Memory_Remap_Config \r\n * @{\r\n */ \r\n#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)\r\n#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01)\r\n#define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02)\r\n#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)\r\n \r\n#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \\\r\n ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \\\r\n ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \\\r\n ((REMAP) == SYSCFG_MemoryRemap_FSMC))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup SYSCFG_ETHERNET_Media_Interface \r\n * @{\r\n */ \r\n#define SYSCFG_ETH_MediaInterface_MII ((uint32_t)0x00000000) \r\n#define SYSCFG_ETH_MediaInterface_RMII ((uint32_t)0x00000001) \r\n\r\n#define IS_SYSCFG_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == SYSCFG_ETH_MediaInterface_MII) || \\\r\n ((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII))\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/ \r\n \r\nvoid SYSCFG_DeInit(void);\r\nvoid SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap);\r\nvoid SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);\r\nvoid SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface); \r\nvoid SYSCFG_CompensationCellCmd(FunctionalState NewState); \r\nFlagStatus SYSCFG_GetCompensationCellStatus(void);\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /*__STM32F4xx_SYSCFG_H */\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_tim.h", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_tim.h\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file contains all the functions prototypes for the TIM firmware \r\n * library.\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F4xx_TIM_H\r\n#define __STM32F4xx_TIM_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @addtogroup TIM\r\n * @{\r\n */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n\r\n/** \r\n * @brief TIM Time Base Init structure definition \r\n * @note This structure is used with all TIMx except for TIM6 and TIM7. \r\n */\r\n\r\ntypedef struct\r\n{\r\n uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.\r\n This parameter can be a number between 0x0000 and 0xFFFF */\r\n\r\n uint16_t TIM_CounterMode; /*!< Specifies the counter mode.\r\n This parameter can be a value of @ref TIM_Counter_Mode */\r\n\r\n uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active\r\n Auto-Reload Register at the next update event.\r\n This parameter must be a number between 0x0000 and 0xFFFF. */ \r\n\r\n uint16_t TIM_ClockDivision; /*!< Specifies the clock division.\r\n This parameter can be a value of @ref TIM_Clock_Division_CKD */\r\n\r\n uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter\r\n reaches zero, an update event is generated and counting restarts\r\n from the RCR value (N).\r\n This means in PWM mode that (N+1) corresponds to:\r\n - the number of PWM periods in edge-aligned mode\r\n - the number of half PWM period in center-aligned mode\r\n This parameter must be a number between 0x00 and 0xFF. \r\n @note This parameter is valid only for TIM1 and TIM8. */\r\n} TIM_TimeBaseInitTypeDef; \r\n\r\n/** \r\n * @brief TIM Output Compare Init structure definition \r\n */\r\n\r\ntypedef struct\r\n{\r\n uint16_t TIM_OCMode; /*!< Specifies the TIM mode.\r\n This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */\r\n\r\n uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.\r\n This parameter can be a value of @ref TIM_Output_Compare_State */\r\n\r\n uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.\r\n This parameter can be a value of @ref TIM_Output_Compare_N_State\r\n @note This parameter is valid only for TIM1 and TIM8. */\r\n\r\n uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. \r\n This parameter can be a number between 0x0000 and 0xFFFF */\r\n\r\n uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.\r\n This parameter can be a value of @ref TIM_Output_Compare_Polarity */\r\n\r\n uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.\r\n This parameter can be a value of @ref TIM_Output_Compare_N_Polarity\r\n @note This parameter is valid only for TIM1 and TIM8. */\r\n\r\n uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.\r\n This parameter can be a value of @ref TIM_Output_Compare_Idle_State\r\n @note This parameter is valid only for TIM1 and TIM8. */\r\n\r\n uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.\r\n This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State\r\n @note This parameter is valid only for TIM1 and TIM8. */\r\n} TIM_OCInitTypeDef;\r\n\r\n/** \r\n * @brief TIM Input Capture Init structure definition \r\n */\r\n\r\ntypedef struct\r\n{\r\n\r\n uint16_t TIM_Channel; /*!< Specifies the TIM channel.\r\n This parameter can be a value of @ref TIM_Channel */\r\n\r\n uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.\r\n This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r\n\r\n uint16_t TIM_ICSelection; /*!< Specifies the input.\r\n This parameter can be a value of @ref TIM_Input_Capture_Selection */\r\n\r\n uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.\r\n This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r\n\r\n uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.\r\n This parameter can be a number between 0x0 and 0xF */\r\n} TIM_ICInitTypeDef;\r\n\r\n/** \r\n * @brief BDTR structure definition \r\n * @note This structure is used only with TIM1 and TIM8. \r\n */\r\n\r\ntypedef struct\r\n{\r\n\r\n uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.\r\n This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */\r\n\r\n uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.\r\n This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */\r\n\r\n uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.\r\n This parameter can be a value of @ref TIM_Lock_level */ \r\n\r\n uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the\r\n switching-on of the outputs.\r\n This parameter can be a number between 0x00 and 0xFF */\r\n\r\n uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. \r\n This parameter can be a value of @ref TIM_Break_Input_enable_disable */\r\n\r\n uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.\r\n This parameter can be a value of @ref TIM_Break_Polarity */\r\n\r\n uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. \r\n This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */\r\n} TIM_BDTRInitTypeDef;\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup TIM_Exported_constants \r\n * @{\r\n */\r\n\r\n#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\\r\n ((PERIPH) == TIM2) || \\\r\n ((PERIPH) == TIM3) || \\\r\n ((PERIPH) == TIM4) || \\\r\n ((PERIPH) == TIM5) || \\\r\n ((PERIPH) == TIM6) || \\\r\n ((PERIPH) == TIM7) || \\\r\n ((PERIPH) == TIM8) || \\\r\n ((PERIPH) == TIM9) || \\\r\n ((PERIPH) == TIM10) || \\\r\n ((PERIPH) == TIM11) || \\\r\n ((PERIPH) == TIM12) || \\\r\n (((PERIPH) == TIM13) || \\\r\n ((PERIPH) == TIM14)))\r\n/* LIST1: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14 */ \r\n#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\\r\n ((PERIPH) == TIM2) || \\\r\n ((PERIPH) == TIM3) || \\\r\n ((PERIPH) == TIM4) || \\\r\n ((PERIPH) == TIM5) || \\\r\n ((PERIPH) == TIM8) || \\\r\n ((PERIPH) == TIM9) || \\\r\n ((PERIPH) == TIM10) || \\\r\n ((PERIPH) == TIM11) || \\\r\n ((PERIPH) == TIM12) || \\\r\n ((PERIPH) == TIM13) || \\\r\n ((PERIPH) == TIM14))\r\n \r\n/* LIST2: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9 and TIM12 */\r\n#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\\r\n ((PERIPH) == TIM2) || \\\r\n ((PERIPH) == TIM3) || \\\r\n ((PERIPH) == TIM4) || \\\r\n ((PERIPH) == TIM5) || \\\r\n ((PERIPH) == TIM8) || \\\r\n ((PERIPH) == TIM9) || \\\r\n ((PERIPH) == TIM12))\r\n/* LIST3: TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 */\r\n#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\\r\n ((PERIPH) == TIM2) || \\\r\n ((PERIPH) == TIM3) || \\\r\n ((PERIPH) == TIM4) || \\\r\n ((PERIPH) == TIM5) || \\\r\n ((PERIPH) == TIM8))\r\n/* LIST4: TIM1 and TIM8 */\r\n#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\\r\n ((PERIPH) == TIM8))\r\n/* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */\r\n#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\\r\n ((PERIPH) == TIM2) || \\\r\n ((PERIPH) == TIM3) || \\\r\n ((PERIPH) == TIM4) || \\\r\n ((PERIPH) == TIM5) || \\\r\n ((PERIPH) == TIM6) || \\\r\n ((PERIPH) == TIM7) || \\\r\n ((PERIPH) == TIM8))\r\n/* LIST6: TIM2, TIM5 and TIM11 */ \r\n#define IS_TIM_LIST6_PERIPH(TIMx)(((TIMx) == TIM2) || \\\r\n ((TIMx) == TIM5) || \\\r\n ((TIMx) == TIM11))\r\n\r\n/** @defgroup TIM_Output_Compare_and_PWM_modes \r\n * @{\r\n */\r\n\r\n#define TIM_OCMode_Timing ((uint16_t)0x0000)\r\n#define TIM_OCMode_Active ((uint16_t)0x0010)\r\n#define TIM_OCMode_Inactive ((uint16_t)0x0020)\r\n#define TIM_OCMode_Toggle ((uint16_t)0x0030)\r\n#define TIM_OCMode_PWM1 ((uint16_t)0x0060)\r\n#define TIM_OCMode_PWM2 ((uint16_t)0x0070)\r\n#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \\\r\n ((MODE) == TIM_OCMode_Active) || \\\r\n ((MODE) == TIM_OCMode_Inactive) || \\\r\n ((MODE) == TIM_OCMode_Toggle)|| \\\r\n ((MODE) == TIM_OCMode_PWM1) || \\\r\n ((MODE) == TIM_OCMode_PWM2))\r\n#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \\\r\n ((MODE) == TIM_OCMode_Active) || \\\r\n ((MODE) == TIM_OCMode_Inactive) || \\\r\n ((MODE) == TIM_OCMode_Toggle)|| \\\r\n ((MODE) == TIM_OCMode_PWM1) || \\\r\n ((MODE) == TIM_OCMode_PWM2) ||\t\\\r\n ((MODE) == TIM_ForcedAction_Active) || \\\r\n ((MODE) == TIM_ForcedAction_InActive))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup TIM_One_Pulse_Mode \r\n * @{\r\n */\r\n\r\n#define TIM_OPMode_Single ((uint16_t)0x0008)\r\n#define TIM_OPMode_Repetitive ((uint16_t)0x0000)\r\n#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \\\r\n ((MODE) == TIM_OPMode_Repetitive))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_Channel \r\n * @{\r\n */\r\n\r\n#define TIM_Channel_1 ((uint16_t)0x0000)\r\n#define TIM_Channel_2 ((uint16_t)0x0004)\r\n#define TIM_Channel_3 ((uint16_t)0x0008)\r\n#define TIM_Channel_4 ((uint16_t)0x000C)\r\n \r\n#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\\r\n ((CHANNEL) == TIM_Channel_2) || \\\r\n ((CHANNEL) == TIM_Channel_3) || \\\r\n ((CHANNEL) == TIM_Channel_4))\r\n \r\n#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\\r\n ((CHANNEL) == TIM_Channel_2))\r\n#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\\r\n ((CHANNEL) == TIM_Channel_2) || \\\r\n ((CHANNEL) == TIM_Channel_3))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_Clock_Division_CKD \r\n * @{\r\n */\r\n\r\n#define TIM_CKD_DIV1 ((uint16_t)0x0000)\r\n#define TIM_CKD_DIV2 ((uint16_t)0x0100)\r\n#define TIM_CKD_DIV4 ((uint16_t)0x0200)\r\n#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \\\r\n ((DIV) == TIM_CKD_DIV2) || \\\r\n ((DIV) == TIM_CKD_DIV4))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup TIM_Counter_Mode \r\n * @{\r\n */\r\n\r\n#define TIM_CounterMode_Up ((uint16_t)0x0000)\r\n#define TIM_CounterMode_Down ((uint16_t)0x0010)\r\n#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)\r\n#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)\r\n#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)\r\n#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \\\r\n ((MODE) == TIM_CounterMode_Down) || \\\r\n ((MODE) == TIM_CounterMode_CenterAligned1) || \\\r\n ((MODE) == TIM_CounterMode_CenterAligned2) || \\\r\n ((MODE) == TIM_CounterMode_CenterAligned3))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_Output_Compare_Polarity \r\n * @{\r\n */\r\n\r\n#define TIM_OCPolarity_High ((uint16_t)0x0000)\r\n#define TIM_OCPolarity_Low ((uint16_t)0x0002)\r\n#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \\\r\n ((POLARITY) == TIM_OCPolarity_Low))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup TIM_Output_Compare_N_Polarity \r\n * @{\r\n */\r\n \r\n#define TIM_OCNPolarity_High ((uint16_t)0x0000)\r\n#define TIM_OCNPolarity_Low ((uint16_t)0x0008)\r\n#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \\\r\n ((POLARITY) == TIM_OCNPolarity_Low))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup TIM_Output_Compare_State \r\n * @{\r\n */\r\n\r\n#define TIM_OutputState_Disable ((uint16_t)0x0000)\r\n#define TIM_OutputState_Enable ((uint16_t)0x0001)\r\n#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \\\r\n ((STATE) == TIM_OutputState_Enable))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_Output_Compare_N_State\r\n * @{\r\n */\r\n\r\n#define TIM_OutputNState_Disable ((uint16_t)0x0000)\r\n#define TIM_OutputNState_Enable ((uint16_t)0x0004)\r\n#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \\\r\n ((STATE) == TIM_OutputNState_Enable))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_Capture_Compare_State\r\n * @{\r\n */\r\n\r\n#define TIM_CCx_Enable ((uint16_t)0x0001)\r\n#define TIM_CCx_Disable ((uint16_t)0x0000)\r\n#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \\\r\n ((CCX) == TIM_CCx_Disable))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_Capture_Compare_N_State\r\n * @{\r\n */\r\n\r\n#define TIM_CCxN_Enable ((uint16_t)0x0004)\r\n#define TIM_CCxN_Disable ((uint16_t)0x0000)\r\n#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \\\r\n ((CCXN) == TIM_CCxN_Disable))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_Break_Input_enable_disable \r\n * @{\r\n */\r\n\r\n#define TIM_Break_Enable ((uint16_t)0x1000)\r\n#define TIM_Break_Disable ((uint16_t)0x0000)\r\n#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \\\r\n ((STATE) == TIM_Break_Disable))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_Break_Polarity \r\n * @{\r\n */\r\n\r\n#define TIM_BreakPolarity_Low ((uint16_t)0x0000)\r\n#define TIM_BreakPolarity_High ((uint16_t)0x2000)\r\n#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \\\r\n ((POLARITY) == TIM_BreakPolarity_High))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_AOE_Bit_Set_Reset \r\n * @{\r\n */\r\n\r\n#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)\r\n#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)\r\n#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \\\r\n ((STATE) == TIM_AutomaticOutput_Disable))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_Lock_level\r\n * @{\r\n */\r\n\r\n#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)\r\n#define TIM_LOCKLevel_1 ((uint16_t)0x0100)\r\n#define TIM_LOCKLevel_2 ((uint16_t)0x0200)\r\n#define TIM_LOCKLevel_3 ((uint16_t)0x0300)\r\n#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \\\r\n ((LEVEL) == TIM_LOCKLevel_1) || \\\r\n ((LEVEL) == TIM_LOCKLevel_2) || \\\r\n ((LEVEL) == TIM_LOCKLevel_3))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state \r\n * @{\r\n */\r\n\r\n#define TIM_OSSIState_Enable ((uint16_t)0x0400)\r\n#define TIM_OSSIState_Disable ((uint16_t)0x0000)\r\n#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \\\r\n ((STATE) == TIM_OSSIState_Disable))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state\r\n * @{\r\n */\r\n\r\n#define TIM_OSSRState_Enable ((uint16_t)0x0800)\r\n#define TIM_OSSRState_Disable ((uint16_t)0x0000)\r\n#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \\\r\n ((STATE) == TIM_OSSRState_Disable))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_Output_Compare_Idle_State \r\n * @{\r\n */\r\n\r\n#define TIM_OCIdleState_Set ((uint16_t)0x0100)\r\n#define TIM_OCIdleState_Reset ((uint16_t)0x0000)\r\n#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \\\r\n ((STATE) == TIM_OCIdleState_Reset))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_Output_Compare_N_Idle_State \r\n * @{\r\n */\r\n\r\n#define TIM_OCNIdleState_Set ((uint16_t)0x0200)\r\n#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)\r\n#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \\\r\n ((STATE) == TIM_OCNIdleState_Reset))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_Input_Capture_Polarity \r\n * @{\r\n */\r\n\r\n#define TIM_ICPolarity_Rising ((uint16_t)0x0000)\r\n#define TIM_ICPolarity_Falling ((uint16_t)0x0002)\r\n#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)\r\n#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \\\r\n ((POLARITY) == TIM_ICPolarity_Falling)|| \\\r\n ((POLARITY) == TIM_ICPolarity_BothEdge))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_Input_Capture_Selection \r\n * @{\r\n */\r\n\r\n#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be \r\n connected to IC1, IC2, IC3 or IC4, respectively */\r\n#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be\r\n connected to IC2, IC1, IC4 or IC3, respectively. */\r\n#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */\r\n#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \\\r\n ((SELECTION) == TIM_ICSelection_IndirectTI) || \\\r\n ((SELECTION) == TIM_ICSelection_TRC))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_Input_Capture_Prescaler \r\n * @{\r\n */\r\n\r\n#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */\r\n#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */\r\n#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */\r\n#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */\r\n#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \\\r\n ((PRESCALER) == TIM_ICPSC_DIV2) || \\\r\n ((PRESCALER) == TIM_ICPSC_DIV4) || \\\r\n ((PRESCALER) == TIM_ICPSC_DIV8))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_interrupt_sources \r\n * @{\r\n */\r\n\r\n#define TIM_IT_Update ((uint16_t)0x0001)\r\n#define TIM_IT_CC1 ((uint16_t)0x0002)\r\n#define TIM_IT_CC2 ((uint16_t)0x0004)\r\n#define TIM_IT_CC3 ((uint16_t)0x0008)\r\n#define TIM_IT_CC4 ((uint16_t)0x0010)\r\n#define TIM_IT_COM ((uint16_t)0x0020)\r\n#define TIM_IT_Trigger ((uint16_t)0x0040)\r\n#define TIM_IT_Break ((uint16_t)0x0080)\r\n#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))\r\n\r\n#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \\\r\n ((IT) == TIM_IT_CC1) || \\\r\n ((IT) == TIM_IT_CC2) || \\\r\n ((IT) == TIM_IT_CC3) || \\\r\n ((IT) == TIM_IT_CC4) || \\\r\n ((IT) == TIM_IT_COM) || \\\r\n ((IT) == TIM_IT_Trigger) || \\\r\n ((IT) == TIM_IT_Break))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_DMA_Base_address \r\n * @{\r\n */\r\n\r\n#define TIM_DMABase_CR1 ((uint16_t)0x0000)\r\n#define TIM_DMABase_CR2 ((uint16_t)0x0001)\r\n#define TIM_DMABase_SMCR ((uint16_t)0x0002)\r\n#define TIM_DMABase_DIER ((uint16_t)0x0003)\r\n#define TIM_DMABase_SR ((uint16_t)0x0004)\r\n#define TIM_DMABase_EGR ((uint16_t)0x0005)\r\n#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)\r\n#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)\r\n#define TIM_DMABase_CCER ((uint16_t)0x0008)\r\n#define TIM_DMABase_CNT ((uint16_t)0x0009)\r\n#define TIM_DMABase_PSC ((uint16_t)0x000A)\r\n#define TIM_DMABase_ARR ((uint16_t)0x000B)\r\n#define TIM_DMABase_RCR ((uint16_t)0x000C)\r\n#define TIM_DMABase_CCR1 ((uint16_t)0x000D)\r\n#define TIM_DMABase_CCR2 ((uint16_t)0x000E)\r\n#define TIM_DMABase_CCR3 ((uint16_t)0x000F)\r\n#define TIM_DMABase_CCR4 ((uint16_t)0x0010)\r\n#define TIM_DMABase_BDTR ((uint16_t)0x0011)\r\n#define TIM_DMABase_DCR ((uint16_t)0x0012)\r\n#define TIM_DMABase_OR ((uint16_t)0x0013)\r\n#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \\\r\n ((BASE) == TIM_DMABase_CR2) || \\\r\n ((BASE) == TIM_DMABase_SMCR) || \\\r\n ((BASE) == TIM_DMABase_DIER) || \\\r\n ((BASE) == TIM_DMABase_SR) || \\\r\n ((BASE) == TIM_DMABase_EGR) || \\\r\n ((BASE) == TIM_DMABase_CCMR1) || \\\r\n ((BASE) == TIM_DMABase_CCMR2) || \\\r\n ((BASE) == TIM_DMABase_CCER) || \\\r\n ((BASE) == TIM_DMABase_CNT) || \\\r\n ((BASE) == TIM_DMABase_PSC) || \\\r\n ((BASE) == TIM_DMABase_ARR) || \\\r\n ((BASE) == TIM_DMABase_RCR) || \\\r\n ((BASE) == TIM_DMABase_CCR1) || \\\r\n ((BASE) == TIM_DMABase_CCR2) || \\\r\n ((BASE) == TIM_DMABase_CCR3) || \\\r\n ((BASE) == TIM_DMABase_CCR4) || \\\r\n ((BASE) == TIM_DMABase_BDTR) || \\\r\n ((BASE) == TIM_DMABase_DCR) || \\\r\n ((BASE) == TIM_DMABase_OR)) \r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_DMA_Burst_Length \r\n * @{\r\n */\r\n\r\n#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)\r\n#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)\r\n#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)\r\n#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)\r\n#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)\r\n#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)\r\n#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)\r\n#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)\r\n#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)\r\n#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)\r\n#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)\r\n#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)\r\n#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)\r\n#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)\r\n#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)\r\n#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)\r\n#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)\r\n#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)\r\n#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \\\r\n ((LENGTH) == TIM_DMABurstLength_2Transfers) || \\\r\n ((LENGTH) == TIM_DMABurstLength_3Transfers) || \\\r\n ((LENGTH) == TIM_DMABurstLength_4Transfers) || \\\r\n ((LENGTH) == TIM_DMABurstLength_5Transfers) || \\\r\n ((LENGTH) == TIM_DMABurstLength_6Transfers) || \\\r\n ((LENGTH) == TIM_DMABurstLength_7Transfers) || \\\r\n ((LENGTH) == TIM_DMABurstLength_8Transfers) || \\\r\n ((LENGTH) == TIM_DMABurstLength_9Transfers) || \\\r\n ((LENGTH) == TIM_DMABurstLength_10Transfers) || \\\r\n ((LENGTH) == TIM_DMABurstLength_11Transfers) || \\\r\n ((LENGTH) == TIM_DMABurstLength_12Transfers) || \\\r\n ((LENGTH) == TIM_DMABurstLength_13Transfers) || \\\r\n ((LENGTH) == TIM_DMABurstLength_14Transfers) || \\\r\n ((LENGTH) == TIM_DMABurstLength_15Transfers) || \\\r\n ((LENGTH) == TIM_DMABurstLength_16Transfers) || \\\r\n ((LENGTH) == TIM_DMABurstLength_17Transfers) || \\\r\n ((LENGTH) == TIM_DMABurstLength_18Transfers))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_DMA_sources \r\n * @{\r\n */\r\n\r\n#define TIM_DMA_Update ((uint16_t)0x0100)\r\n#define TIM_DMA_CC1 ((uint16_t)0x0200)\r\n#define TIM_DMA_CC2 ((uint16_t)0x0400)\r\n#define TIM_DMA_CC3 ((uint16_t)0x0800)\r\n#define TIM_DMA_CC4 ((uint16_t)0x1000)\r\n#define TIM_DMA_COM ((uint16_t)0x2000)\r\n#define TIM_DMA_Trigger ((uint16_t)0x4000)\r\n#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_External_Trigger_Prescaler \r\n * @{\r\n */\r\n\r\n#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)\r\n#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)\r\n#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)\r\n#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)\r\n#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \\\r\n ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \\\r\n ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \\\r\n ((PRESCALER) == TIM_ExtTRGPSC_DIV8))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_Internal_Trigger_Selection \r\n * @{\r\n */\r\n\r\n#define TIM_TS_ITR0 ((uint16_t)0x0000)\r\n#define TIM_TS_ITR1 ((uint16_t)0x0010)\r\n#define TIM_TS_ITR2 ((uint16_t)0x0020)\r\n#define TIM_TS_ITR3 ((uint16_t)0x0030)\r\n#define TIM_TS_TI1F_ED ((uint16_t)0x0040)\r\n#define TIM_TS_TI1FP1 ((uint16_t)0x0050)\r\n#define TIM_TS_TI2FP2 ((uint16_t)0x0060)\r\n#define TIM_TS_ETRF ((uint16_t)0x0070)\r\n#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\\r\n ((SELECTION) == TIM_TS_ITR1) || \\\r\n ((SELECTION) == TIM_TS_ITR2) || \\\r\n ((SELECTION) == TIM_TS_ITR3) || \\\r\n ((SELECTION) == TIM_TS_TI1F_ED) || \\\r\n ((SELECTION) == TIM_TS_TI1FP1) || \\\r\n ((SELECTION) == TIM_TS_TI2FP2) || \\\r\n ((SELECTION) == TIM_TS_ETRF))\r\n#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\\r\n ((SELECTION) == TIM_TS_ITR1) || \\\r\n ((SELECTION) == TIM_TS_ITR2) || \\\r\n ((SELECTION) == TIM_TS_ITR3))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_TIx_External_Clock_Source \r\n * @{\r\n */\r\n\r\n#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)\r\n#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)\r\n#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_External_Trigger_Polarity \r\n * @{\r\n */ \r\n#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)\r\n#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)\r\n#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \\\r\n ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup TIM_Prescaler_Reload_Mode \r\n * @{\r\n */\r\n\r\n#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)\r\n#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)\r\n#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \\\r\n ((RELOAD) == TIM_PSCReloadMode_Immediate))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_Forced_Action \r\n * @{\r\n */\r\n\r\n#define TIM_ForcedAction_Active ((uint16_t)0x0050)\r\n#define TIM_ForcedAction_InActive ((uint16_t)0x0040)\r\n#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \\\r\n ((ACTION) == TIM_ForcedAction_InActive))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_Encoder_Mode \r\n * @{\r\n */\r\n\r\n#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)\r\n#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)\r\n#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)\r\n#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \\\r\n ((MODE) == TIM_EncoderMode_TI2) || \\\r\n ((MODE) == TIM_EncoderMode_TI12))\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup TIM_Event_Source \r\n * @{\r\n */\r\n\r\n#define TIM_EventSource_Update ((uint16_t)0x0001)\r\n#define TIM_EventSource_CC1 ((uint16_t)0x0002)\r\n#define TIM_EventSource_CC2 ((uint16_t)0x0004)\r\n#define TIM_EventSource_CC3 ((uint16_t)0x0008)\r\n#define TIM_EventSource_CC4 ((uint16_t)0x0010)\r\n#define TIM_EventSource_COM ((uint16_t)0x0020)\r\n#define TIM_EventSource_Trigger ((uint16_t)0x0040)\r\n#define TIM_EventSource_Break ((uint16_t)0x0080)\r\n#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) \r\n \r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_Update_Source \r\n * @{\r\n */\r\n\r\n#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow\r\n or the setting of UG bit, or an update generation\r\n through the slave mode controller. */\r\n#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */\r\n#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \\\r\n ((SOURCE) == TIM_UpdateSource_Regular))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_Output_Compare_Preload_State \r\n * @{\r\n */\r\n\r\n#define TIM_OCPreload_Enable ((uint16_t)0x0008)\r\n#define TIM_OCPreload_Disable ((uint16_t)0x0000)\r\n#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \\\r\n ((STATE) == TIM_OCPreload_Disable))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_Output_Compare_Fast_State \r\n * @{\r\n */\r\n\r\n#define TIM_OCFast_Enable ((uint16_t)0x0004)\r\n#define TIM_OCFast_Disable ((uint16_t)0x0000)\r\n#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \\\r\n ((STATE) == TIM_OCFast_Disable))\r\n \r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_Output_Compare_Clear_State \r\n * @{\r\n */\r\n\r\n#define TIM_OCClear_Enable ((uint16_t)0x0080)\r\n#define TIM_OCClear_Disable ((uint16_t)0x0000)\r\n#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \\\r\n ((STATE) == TIM_OCClear_Disable))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_Trigger_Output_Source \r\n * @{\r\n */\r\n\r\n#define TIM_TRGOSource_Reset ((uint16_t)0x0000)\r\n#define TIM_TRGOSource_Enable ((uint16_t)0x0010)\r\n#define TIM_TRGOSource_Update ((uint16_t)0x0020)\r\n#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)\r\n#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)\r\n#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)\r\n#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)\r\n#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)\r\n#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \\\r\n ((SOURCE) == TIM_TRGOSource_Enable) || \\\r\n ((SOURCE) == TIM_TRGOSource_Update) || \\\r\n ((SOURCE) == TIM_TRGOSource_OC1) || \\\r\n ((SOURCE) == TIM_TRGOSource_OC1Ref) || \\\r\n ((SOURCE) == TIM_TRGOSource_OC2Ref) || \\\r\n ((SOURCE) == TIM_TRGOSource_OC3Ref) || \\\r\n ((SOURCE) == TIM_TRGOSource_OC4Ref))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_Slave_Mode \r\n * @{\r\n */\r\n\r\n#define TIM_SlaveMode_Reset ((uint16_t)0x0004)\r\n#define TIM_SlaveMode_Gated ((uint16_t)0x0005)\r\n#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)\r\n#define TIM_SlaveMode_External1 ((uint16_t)0x0007)\r\n#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \\\r\n ((MODE) == TIM_SlaveMode_Gated) || \\\r\n ((MODE) == TIM_SlaveMode_Trigger) || \\\r\n ((MODE) == TIM_SlaveMode_External1))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_Master_Slave_Mode \r\n * @{\r\n */\r\n\r\n#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)\r\n#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)\r\n#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \\\r\n ((STATE) == TIM_MasterSlaveMode_Disable))\r\n/**\r\n * @}\r\n */ \r\n/** @defgroup TIM_Remap \r\n * @{\r\n */\r\n\r\n#define TIM2_TIM8_TRGO ((uint16_t)0x0000)\r\n#define TIM2_ETH_PTP ((uint16_t)0x0400)\r\n#define TIM2_USBFS_SOF ((uint16_t)0x0800)\r\n#define TIM2_USBHS_SOF ((uint16_t)0x0C00)\r\n\r\n#define TIM5_GPIO ((uint16_t)0x0000)\r\n#define TIM5_LSI ((uint16_t)0x0040)\r\n#define TIM5_LSE ((uint16_t)0x0080)\r\n#define TIM5_RTC ((uint16_t)0x00C0)\r\n\r\n#define TIM11_GPIO ((uint16_t)0x0000)\r\n#define TIM11_HSE ((uint16_t)0x0002)\r\n\r\n#define IS_TIM_REMAP(TIM_REMAP)\t (((TIM_REMAP) == TIM2_TIM8_TRGO)||\\\r\n ((TIM_REMAP) == TIM2_ETH_PTP)||\\\r\n ((TIM_REMAP) == TIM2_USBFS_SOF)||\\\r\n ((TIM_REMAP) == TIM2_USBHS_SOF)||\\\r\n ((TIM_REMAP) == TIM5_GPIO)||\\\r\n ((TIM_REMAP) == TIM5_LSI)||\\\r\n ((TIM_REMAP) == TIM5_LSE)||\\\r\n ((TIM_REMAP) == TIM5_RTC)||\\\r\n ((TIM_REMAP) == TIM11_GPIO)||\\\r\n ((TIM_REMAP) == TIM11_HSE))\r\n\r\n/**\r\n * @}\r\n */ \r\n/** @defgroup TIM_Flags \r\n * @{\r\n */\r\n\r\n#define TIM_FLAG_Update ((uint16_t)0x0001)\r\n#define TIM_FLAG_CC1 ((uint16_t)0x0002)\r\n#define TIM_FLAG_CC2 ((uint16_t)0x0004)\r\n#define TIM_FLAG_CC3 ((uint16_t)0x0008)\r\n#define TIM_FLAG_CC4 ((uint16_t)0x0010)\r\n#define TIM_FLAG_COM ((uint16_t)0x0020)\r\n#define TIM_FLAG_Trigger ((uint16_t)0x0040)\r\n#define TIM_FLAG_Break ((uint16_t)0x0080)\r\n#define TIM_FLAG_CC1OF ((uint16_t)0x0200)\r\n#define TIM_FLAG_CC2OF ((uint16_t)0x0400)\r\n#define TIM_FLAG_CC3OF ((uint16_t)0x0800)\r\n#define TIM_FLAG_CC4OF ((uint16_t)0x1000)\r\n#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \\\r\n ((FLAG) == TIM_FLAG_CC1) || \\\r\n ((FLAG) == TIM_FLAG_CC2) || \\\r\n ((FLAG) == TIM_FLAG_CC3) || \\\r\n ((FLAG) == TIM_FLAG_CC4) || \\\r\n ((FLAG) == TIM_FLAG_COM) || \\\r\n ((FLAG) == TIM_FLAG_Trigger) || \\\r\n ((FLAG) == TIM_FLAG_Break) || \\\r\n ((FLAG) == TIM_FLAG_CC1OF) || \\\r\n ((FLAG) == TIM_FLAG_CC2OF) || \\\r\n ((FLAG) == TIM_FLAG_CC3OF) || \\\r\n ((FLAG) == TIM_FLAG_CC4OF))\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_Input_Capture_Filer_Value \r\n * @{\r\n */\r\n\r\n#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) \r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_External_Trigger_Filter \r\n * @{\r\n */\r\n\r\n#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup TIM_Legacy \r\n * @{\r\n */\r\n\r\n#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer\r\n#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers\r\n#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers\r\n#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers\r\n#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers\r\n#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers\r\n#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers\r\n#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers\r\n#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers\r\n#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers\r\n#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers\r\n#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers\r\n#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers\r\n#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers\r\n#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers\r\n#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers\r\n#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers\r\n#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/ \r\n\r\n/* TimeBase management ********************************************************/\r\nvoid TIM_DeInit(TIM_TypeDef* TIMx);\r\nvoid TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);\r\nvoid TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);\r\nvoid TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);\r\nvoid TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);\r\nvoid TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);\r\nvoid TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);\r\nuint32_t TIM_GetCounter(TIM_TypeDef* TIMx);\r\nuint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);\r\nvoid TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);\r\nvoid TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);\r\nvoid TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);\r\nvoid TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);\r\nvoid TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);\r\nvoid TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);\r\n\r\n/* Output Compare management **************************************************/\r\nvoid TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r\nvoid TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r\nvoid TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r\nvoid TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r\nvoid TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);\r\nvoid TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);\r\nvoid TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);\r\nvoid TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);\r\nvoid TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);\r\nvoid TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);\r\nvoid TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r\nvoid TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r\nvoid TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r\nvoid TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r\nvoid TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r\nvoid TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r\nvoid TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r\nvoid TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r\nvoid TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r\nvoid TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r\nvoid TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r\nvoid TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r\nvoid TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r\nvoid TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r\nvoid TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r\nvoid TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r\nvoid TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r\nvoid TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);\r\nvoid TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r\nvoid TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);\r\nvoid TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r\nvoid TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);\r\nvoid TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r\nvoid TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);\r\nvoid TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);\r\n\r\n/* Input Capture management ***************************************************/\r\nvoid TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);\r\nvoid TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);\r\nvoid TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);\r\nuint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);\r\nuint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);\r\nuint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);\r\nuint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);\r\nvoid TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r\nvoid TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r\nvoid TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r\nvoid TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r\n\r\n/* Advanced-control timers (TIM1 and TIM8) specific features ******************/\r\nvoid TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);\r\nvoid TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);\r\nvoid TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);\r\nvoid TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);\r\nvoid TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);\r\n\r\n/* Interrupts, DMA and flags management ***************************************/\r\nvoid TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);\r\nvoid TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);\r\nFlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);\r\nvoid TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);\r\nITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);\r\nvoid TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);\r\nvoid TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);\r\nvoid TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);\r\nvoid TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);\r\n\r\n/* Clocks management **********************************************************/\r\nvoid TIM_InternalClockConfig(TIM_TypeDef* TIMx);\r\nvoid TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);\r\nvoid TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,\r\n uint16_t TIM_ICPolarity, uint16_t ICFilter);\r\nvoid TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r\n uint16_t ExtTRGFilter);\r\nvoid TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, \r\n uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);\r\n\r\n/* Synchronization management *************************************************/\r\nvoid TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);\r\nvoid TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);\r\nvoid TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);\r\nvoid TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);\r\nvoid TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r\n uint16_t ExtTRGFilter);\r\n\r\n/* Specific interface management **********************************************/ \r\nvoid TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,\r\n uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);\r\nvoid TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);\r\n\r\n/* Specific remapping management **********************************************/\r\nvoid TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /*__STM32F4xx_TIM_H */\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_usart.h", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_usart.h\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file contains all the functions prototypes for the USART \r\n * firmware library.\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F4xx_USART_H\r\n#define __STM32F4xx_USART_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @addtogroup USART\r\n * @{\r\n */ \r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n\r\n/** \r\n * @brief USART Init Structure definition \r\n */ \r\n \r\ntypedef struct\r\n{\r\n uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.\r\n The baud rate is computed using the following formula:\r\n - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate)))\r\n - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 \r\n Where OVR8 is the \"oversampling by 8 mode\" configuration bit in the CR1 register. */\r\n\r\n uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.\r\n This parameter can be a value of @ref USART_Word_Length */\r\n\r\n uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.\r\n This parameter can be a value of @ref USART_Stop_Bits */\r\n\r\n uint16_t USART_Parity; /*!< Specifies the parity mode.\r\n This parameter can be a value of @ref USART_Parity\r\n @note When parity is enabled, the computed parity is inserted\r\n at the MSB position of the transmitted data (9th bit when\r\n the word length is set to 9 data bits; 8th bit when the\r\n word length is set to 8 data bits). */\r\n \r\n uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.\r\n This parameter can be a value of @ref USART_Mode */\r\n\r\n uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled\r\n or disabled.\r\n This parameter can be a value of @ref USART_Hardware_Flow_Control */\r\n} USART_InitTypeDef;\r\n\r\n/** \r\n * @brief USART Clock Init Structure definition \r\n */ \r\n \r\ntypedef struct\r\n{\r\n\r\n uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.\r\n This parameter can be a value of @ref USART_Clock */\r\n\r\n uint16_t USART_CPOL; /*!< Specifies the steady state of the serial clock.\r\n This parameter can be a value of @ref USART_Clock_Polarity */\r\n\r\n uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.\r\n This parameter can be a value of @ref USART_Clock_Phase */\r\n\r\n uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted\r\n data bit (MSB) has to be output on the SCLK pin in synchronous mode.\r\n This parameter can be a value of @ref USART_Last_Bit */\r\n} USART_ClockInitTypeDef;\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup USART_Exported_Constants\r\n * @{\r\n */ \r\n \r\n#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \\\r\n ((PERIPH) == USART2) || \\\r\n ((PERIPH) == USART3) || \\\r\n ((PERIPH) == UART4) || \\\r\n ((PERIPH) == UART5) || \\\r\n ((PERIPH) == USART6))\r\n\r\n#define IS_USART_1236_PERIPH(PERIPH) (((PERIPH) == USART1) || \\\r\n ((PERIPH) == USART2) || \\\r\n ((PERIPH) == USART3) || \\\r\n ((PERIPH) == USART6))\r\n\r\n/** @defgroup USART_Word_Length \r\n * @{\r\n */ \r\n \r\n#define USART_WordLength_8b ((uint16_t)0x0000)\r\n#define USART_WordLength_9b ((uint16_t)0x1000)\r\n \r\n#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \\\r\n ((LENGTH) == USART_WordLength_9b))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup USART_Stop_Bits \r\n * @{\r\n */ \r\n \r\n#define USART_StopBits_1 ((uint16_t)0x0000)\r\n#define USART_StopBits_0_5 ((uint16_t)0x1000)\r\n#define USART_StopBits_2 ((uint16_t)0x2000)\r\n#define USART_StopBits_1_5 ((uint16_t)0x3000)\r\n#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \\\r\n ((STOPBITS) == USART_StopBits_0_5) || \\\r\n ((STOPBITS) == USART_StopBits_2) || \\\r\n ((STOPBITS) == USART_StopBits_1_5))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup USART_Parity \r\n * @{\r\n */ \r\n \r\n#define USART_Parity_No ((uint16_t)0x0000)\r\n#define USART_Parity_Even ((uint16_t)0x0400)\r\n#define USART_Parity_Odd ((uint16_t)0x0600) \r\n#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \\\r\n ((PARITY) == USART_Parity_Even) || \\\r\n ((PARITY) == USART_Parity_Odd))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup USART_Mode \r\n * @{\r\n */ \r\n \r\n#define USART_Mode_Rx ((uint16_t)0x0004)\r\n#define USART_Mode_Tx ((uint16_t)0x0008)\r\n#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup USART_Hardware_Flow_Control \r\n * @{\r\n */ \r\n#define USART_HardwareFlowControl_None ((uint16_t)0x0000)\r\n#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)\r\n#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)\r\n#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)\r\n#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\\\r\n (((CONTROL) == USART_HardwareFlowControl_None) || \\\r\n ((CONTROL) == USART_HardwareFlowControl_RTS) || \\\r\n ((CONTROL) == USART_HardwareFlowControl_CTS) || \\\r\n ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup USART_Clock \r\n * @{\r\n */ \r\n#define USART_Clock_Disable ((uint16_t)0x0000)\r\n#define USART_Clock_Enable ((uint16_t)0x0800)\r\n#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \\\r\n ((CLOCK) == USART_Clock_Enable))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup USART_Clock_Polarity \r\n * @{\r\n */\r\n \r\n#define USART_CPOL_Low ((uint16_t)0x0000)\r\n#define USART_CPOL_High ((uint16_t)0x0400)\r\n#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup USART_Clock_Phase\r\n * @{\r\n */\r\n\r\n#define USART_CPHA_1Edge ((uint16_t)0x0000)\r\n#define USART_CPHA_2Edge ((uint16_t)0x0200)\r\n#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup USART_Last_Bit\r\n * @{\r\n */\r\n\r\n#define USART_LastBit_Disable ((uint16_t)0x0000)\r\n#define USART_LastBit_Enable ((uint16_t)0x0100)\r\n#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \\\r\n ((LASTBIT) == USART_LastBit_Enable))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup USART_Interrupt_definition \r\n * @{\r\n */\r\n \r\n#define USART_IT_PE ((uint16_t)0x0028)\r\n#define USART_IT_TXE ((uint16_t)0x0727)\r\n#define USART_IT_TC ((uint16_t)0x0626)\r\n#define USART_IT_RXNE ((uint16_t)0x0525)\r\n#define USART_IT_ORE_RX ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */\r\n#define USART_IT_IDLE ((uint16_t)0x0424)\r\n#define USART_IT_LBD ((uint16_t)0x0846)\r\n#define USART_IT_CTS ((uint16_t)0x096A)\r\n#define USART_IT_ERR ((uint16_t)0x0060)\r\n#define USART_IT_ORE_ER ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */\r\n#define USART_IT_NE ((uint16_t)0x0260)\r\n#define USART_IT_FE ((uint16_t)0x0160)\r\n\r\n/** @defgroup USART_Legacy \r\n * @{\r\n */\r\n#define USART_IT_ORE USART_IT_ORE_ER \r\n/**\r\n * @}\r\n */\r\n\r\n#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \\\r\n ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\\r\n ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \\\r\n ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))\r\n#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \\\r\n ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\\r\n ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \\\r\n ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \\\r\n ((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) || \\\r\n ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))\r\n#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\\r\n ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup USART_DMA_Requests \r\n * @{\r\n */\r\n\r\n#define USART_DMAReq_Tx ((uint16_t)0x0080)\r\n#define USART_DMAReq_Rx ((uint16_t)0x0040)\r\n#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup USART_WakeUp_methods\r\n * @{\r\n */\r\n\r\n#define USART_WakeUp_IdleLine ((uint16_t)0x0000)\r\n#define USART_WakeUp_AddressMark ((uint16_t)0x0800)\r\n#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \\\r\n ((WAKEUP) == USART_WakeUp_AddressMark))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup USART_LIN_Break_Detection_Length \r\n * @{\r\n */\r\n \r\n#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)\r\n#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)\r\n#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \\\r\n (((LENGTH) == USART_LINBreakDetectLength_10b) || \\\r\n ((LENGTH) == USART_LINBreakDetectLength_11b))\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup USART_IrDA_Low_Power \r\n * @{\r\n */\r\n\r\n#define USART_IrDAMode_LowPower ((uint16_t)0x0004)\r\n#define USART_IrDAMode_Normal ((uint16_t)0x0000)\r\n#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \\\r\n ((MODE) == USART_IrDAMode_Normal))\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup USART_Flags \r\n * @{\r\n */\r\n\r\n#define USART_FLAG_CTS ((uint16_t)0x0200)\r\n#define USART_FLAG_LBD ((uint16_t)0x0100)\r\n#define USART_FLAG_TXE ((uint16_t)0x0080)\r\n#define USART_FLAG_TC ((uint16_t)0x0040)\r\n#define USART_FLAG_RXNE ((uint16_t)0x0020)\r\n#define USART_FLAG_IDLE ((uint16_t)0x0010)\r\n#define USART_FLAG_ORE ((uint16_t)0x0008)\r\n#define USART_FLAG_NE ((uint16_t)0x0004)\r\n#define USART_FLAG_FE ((uint16_t)0x0002)\r\n#define USART_FLAG_PE ((uint16_t)0x0001)\r\n#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \\\r\n ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \\\r\n ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \\\r\n ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \\\r\n ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))\r\n \r\n#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))\r\n\r\n#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 7500001))\r\n#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)\r\n#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/ \r\n\r\n/* Function used to set the USART configuration to the default reset state ***/ \r\nvoid USART_DeInit(USART_TypeDef* USARTx);\r\n\r\n/* Initialization and Configuration functions *********************************/\r\nvoid USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);\r\nvoid USART_StructInit(USART_InitTypeDef* USART_InitStruct);\r\nvoid USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);\r\nvoid USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);\r\nvoid USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);\r\nvoid USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);\r\nvoid USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);\r\nvoid USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r\n\r\n/* Data transfers functions ***************************************************/ \r\nvoid USART_SendData(USART_TypeDef* USARTx, uint16_t Data);\r\nuint16_t USART_ReceiveData(USART_TypeDef* USARTx);\r\n\r\n/* Multi-Processor Communication functions ************************************/\r\nvoid USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);\r\nvoid USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);\r\nvoid USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r\n\r\n/* LIN mode functions *********************************************************/\r\nvoid USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);\r\nvoid USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r\nvoid USART_SendBreak(USART_TypeDef* USARTx);\r\n\r\n/* Half-duplex mode function **************************************************/\r\nvoid USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r\n\r\n/* Smartcard mode functions ***************************************************/\r\nvoid USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r\nvoid USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r\nvoid USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);\r\n\r\n/* IrDA mode functions ********************************************************/\r\nvoid USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);\r\nvoid USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);\r\n\r\n/* DMA transfers management functions *****************************************/\r\nvoid USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);\r\n\r\n/* Interrupts and flags management functions **********************************/\r\nvoid USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);\r\nFlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);\r\nvoid USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);\r\nITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);\r\nvoid USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F4xx_USART_H */\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_wwdg.h", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_wwdg.h\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file contains all the functions prototypes for the WWDG firmware\r\n * library.\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F4xx_WWDG_H\r\n#define __STM32F4xx_WWDG_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @addtogroup WWDG\r\n * @{\r\n */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup WWDG_Exported_Constants\r\n * @{\r\n */ \r\n \r\n/** @defgroup WWDG_Prescaler \r\n * @{\r\n */\r\n \r\n#define WWDG_Prescaler_1 ((uint32_t)0x00000000)\r\n#define WWDG_Prescaler_2 ((uint32_t)0x00000080)\r\n#define WWDG_Prescaler_4 ((uint32_t)0x00000100)\r\n#define WWDG_Prescaler_8 ((uint32_t)0x00000180)\r\n#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \\\r\n ((PRESCALER) == WWDG_Prescaler_2) || \\\r\n ((PRESCALER) == WWDG_Prescaler_4) || \\\r\n ((PRESCALER) == WWDG_Prescaler_8))\r\n#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)\r\n#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n \r\n/* Function used to set the WWDG configuration to the default reset state ****/ \r\nvoid WWDG_DeInit(void);\r\n\r\n/* Prescaler, Refresh window and Counter configuration functions **************/\r\nvoid WWDG_SetPrescaler(uint32_t WWDG_Prescaler);\r\nvoid WWDG_SetWindowValue(uint8_t WindowValue);\r\nvoid WWDG_EnableIT(void);\r\nvoid WWDG_SetCounter(uint8_t Counter);\r\n\r\n/* WWDG activation function ***************************************************/\r\nvoid WWDG_Enable(uint8_t Counter);\r\n\r\n/* Interrupts and flags management functions **********************************/\r\nFlagStatus WWDG_GetFlagStatus(void);\r\nvoid WWDG_ClearFlag(void);\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F4xx_WWDG_H */\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/misc.c", "content": "/**\r\n ******************************************************************************\r\n * @file misc.c\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file provides all the miscellaneous firmware functions (add-on\r\n * to CMSIS functions).\r\n * \r\n * @verbatim \r\n * \r\n * =================================================================== \r\n * How to configure Interrupts using driver \r\n * =================================================================== \r\n * \r\n * This section provide functions allowing to configure the NVIC interrupts (IRQ).\r\n * The Cortex-M4 exceptions are managed by CMSIS functions.\r\n *\r\n * 1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig()\r\n * function according to the following table.\r\n \r\n * The table below gives the allowed values of the pre-emption priority and subpriority according\r\n * to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function\r\n * ==========================================================================================================================\r\n * NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description\r\n * ==========================================================================================================================\r\n * NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority\r\n * | | | 4 bits for subpriority\r\n * --------------------------------------------------------------------------------------------------------------------------\r\n * NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority\r\n * | | | 3 bits for subpriority\r\n * -------------------------------------------------------------------------------------------------------------------------- \r\n * NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority\r\n * | | | 2 bits for subpriority\r\n * -------------------------------------------------------------------------------------------------------------------------- \r\n * NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority\r\n * | | | 1 bits for subpriority\r\n * -------------------------------------------------------------------------------------------------------------------------- \r\n * NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority\r\n * | | | 0 bits for subpriority \r\n * ========================================================================================================================== \r\n *\r\n * 2. Enable and Configure the priority of the selected IRQ Channels using NVIC_Init() \r\n *\r\n * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. \r\n * The pending IRQ priority will be managed only by the subpriority.\r\n *\r\n * @note IRQ priority order (sorted by highest to lowest priority):\r\n * - Lowest pre-emption priority\r\n * - Lowest subpriority\r\n * - Lowest hardware priority (IRQ number)\r\n *\r\n * @endverbatim\r\n *\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"misc.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @defgroup MISC \r\n * @brief MISC driver modules\r\n * @{\r\n */\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup MISC_Private_Functions\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Configures the priority grouping: pre-emption priority and subpriority.\r\n * @param NVIC_PriorityGroup: specifies the priority grouping bits length. \r\n * This parameter can be one of the following values:\r\n * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority\r\n * 4 bits for subpriority\r\n * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority\r\n * 3 bits for subpriority\r\n * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority\r\n * 2 bits for subpriority\r\n * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority\r\n * 1 bits for subpriority\r\n * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority\r\n * 0 bits for subpriority\r\n * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. \r\n * The pending IRQ priority will be managed only by the subpriority. \r\n * @retval None\r\n */\r\nvoid NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));\r\n \r\n /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */\r\n SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;\r\n}\r\n\r\n/**\r\n * @brief Initializes the NVIC peripheral according to the specified\r\n * parameters in the NVIC_InitStruct.\r\n * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()\r\n * function should be called before. \r\n * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains\r\n * the configuration information for the specified NVIC peripheral.\r\n * @retval None\r\n */\r\nvoid NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)\r\n{\r\n uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));\r\n assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); \r\n assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));\r\n \r\n if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)\r\n {\r\n /* Compute the Corresponding IRQ Priority --------------------------------*/ \r\n tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;\r\n tmppre = (0x4 - tmppriority);\r\n tmpsub = tmpsub >> tmppriority;\r\n\r\n tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;\r\n tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub);\r\n \r\n tmppriority = tmppriority << 0x04;\r\n \r\n NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;\r\n \r\n /* Enable the Selected IRQ Channels --------------------------------------*/\r\n NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =\r\n (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);\r\n }\r\n else\r\n {\r\n /* Disable the Selected IRQ Channels -------------------------------------*/\r\n NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =\r\n (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Sets the vector table location and Offset.\r\n * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.\r\n * This parameter can be one of the following values:\r\n * @arg NVIC_VectTab_RAM: Vector Table in internal SRAM.\r\n * @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH.\r\n * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200.\r\n * @retval None\r\n */\r\nvoid NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)\r\n{ \r\n /* Check the parameters */\r\n assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));\r\n assert_param(IS_NVIC_OFFSET(Offset)); \r\n \r\n SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);\r\n}\r\n\r\n/**\r\n * @brief Selects the condition for the system to enter low power mode.\r\n * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.\r\n * This parameter can be one of the following values:\r\n * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend.\r\n * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.\r\n * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.\r\n * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_NVIC_LP(LowPowerMode));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState)); \r\n \r\n if (NewState != DISABLE)\r\n {\r\n SCB->SCR |= LowPowerMode;\r\n }\r\n else\r\n {\r\n SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Configures the SysTick clock source.\r\n * @param SysTick_CLKSource: specifies the SysTick clock source.\r\n * This parameter can be one of the following values:\r\n * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.\r\n * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.\r\n * @retval None\r\n */\r\nvoid SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));\r\n if (SysTick_CLKSource == SysTick_CLKSource_HCLK)\r\n {\r\n SysTick->CTRL |= SysTick_CLKSource_HCLK;\r\n }\r\n else\r\n {\r\n SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;\r\n }\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_adc.c\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file provides firmware functions to manage the following \r\n * functionalities of the Analog to Digital Convertor (ADC) peripheral:\r\n * - Initialization and Configuration (in addition to ADC multi mode \r\n * selection)\r\n * - Analog Watchdog configuration\r\n * - Temperature Sensor & Vrefint (Voltage Reference internal) & VBAT\r\n * management \r\n * - Regular Channels Configuration\r\n * - Regular Channels DMA Configuration\r\n * - Injected channels Configuration\r\n * - Interrupts and flags management\r\n * \r\n * @verbatim\r\n *\r\n * ===================================================================\r\n * How to use this driver\r\n * ===================================================================\r\n\r\n * 1. Enable the ADC interface clock using \r\n * RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADCx, ENABLE); \r\n * \r\n * 2. ADC pins configuration\r\n * - Enable the clock for the ADC GPIOs using the following function:\r\n * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); \r\n * - Configure these ADC pins in analog mode using GPIO_Init(); \r\n *\r\n * 3. Configure the ADC Prescaler, conversion resolution and data \r\n * alignment using the ADC_Init() function.\r\n * 4. Activate the ADC peripheral using ADC_Cmd() function.\r\n *\r\n * Regular channels group configuration\r\n * ==================================== \r\n * - To configure the ADC regular channels group features, use \r\n * ADC_Init() and ADC_RegularChannelConfig() functions.\r\n * - To activate the continuous mode, use the ADC_continuousModeCmd()\r\n * function.\r\n * - To configurate and activate the Discontinuous mode, use the \r\n * ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions.\r\n * - To read the ADC converted values, use the ADC_GetConversionValue()\r\n * function.\r\n *\r\n * Multi mode ADCs Regular channels configuration\r\n * ===============================================\r\n * - Refer to \"Regular channels group configuration\" description to\r\n * configure the ADC1, ADC2 and ADC3 regular channels. \r\n * - Select the Multi mode ADC regular channels features (dual or \r\n * triple mode) using ADC_CommonInit() function and configure \r\n * the DMA mode using ADC_MultiModeDMARequestAfterLastTransferCmd() \r\n * functions. \r\n * - Read the ADCs converted values using the \r\n * ADC_GetMultiModeConversionValue() function.\r\n *\r\n * DMA for Regular channels group features configuration\r\n * ====================================================== \r\n * - To enable the DMA mode for regular channels group, use the \r\n * ADC_DMACmd() function.\r\n * - To enable the generation of DMA requests continuously at the end\r\n * of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd() \r\n * function.\r\n *\r\n * Injected channels group configuration\r\n * ===================================== \r\n * - To configure the ADC Injected channels group features, use \r\n * ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig()\r\n * functions.\r\n * - To activate the continuous mode, use the ADC_continuousModeCmd()\r\n * function.\r\n * - To activate the Injected Discontinuous mode, use the \r\n * ADC_InjectedDiscModeCmd() function. \r\n * - To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd() \r\n * function. \r\n * - To read the ADC converted values, use the ADC_GetInjectedConversionValue() \r\n * function.\r\n *\r\n * @endverbatim\r\n *\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx_adc.h\"\r\n#include \"stm32f4xx_rcc.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @defgroup ADC \r\n * @brief ADC driver modules\r\n * @{\r\n */ \r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/ \r\n\r\n/* ADC DISCNUM mask */\r\n#define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF)\r\n\r\n/* ADC AWDCH mask */\r\n#define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0) \r\n\r\n/* ADC Analog watchdog enable mode mask */\r\n#define CR1_AWDMode_RESET ((uint32_t)0xFF3FFDFF) \r\n\r\n/* CR1 register Mask */\r\n#define CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF)\r\n\r\n/* ADC EXTEN mask */\r\n#define CR2_EXTEN_RESET ((uint32_t)0xCFFFFFFF) \r\n\r\n/* ADC JEXTEN mask */\r\n#define CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF) \r\n\r\n/* ADC JEXTSEL mask */\r\n#define CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF) \r\n\r\n/* CR2 register Mask */\r\n#define CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD)\r\n\r\n/* ADC SQx mask */\r\n#define SQR3_SQ_SET ((uint32_t)0x0000001F) \r\n#define SQR2_SQ_SET ((uint32_t)0x0000001F) \r\n#define SQR1_SQ_SET ((uint32_t)0x0000001F) \r\n\r\n/* ADC L Mask */\r\n#define SQR1_L_RESET ((uint32_t)0xFF0FFFFF) \r\n\r\n/* ADC JSQx mask */\r\n#define JSQR_JSQ_SET ((uint32_t)0x0000001F) \r\n\r\n/* ADC JL mask */\r\n#define JSQR_JL_SET ((uint32_t)0x00300000) \r\n#define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF) \r\n\r\n/* ADC SMPx mask */\r\n#define SMPR1_SMP_SET ((uint32_t)0x00000007) \r\n#define SMPR2_SMP_SET ((uint32_t)0x00000007) \r\n\r\n/* ADC JDRx registers offset */\r\n#define JDR_OFFSET ((uint8_t)0x28) \r\n\r\n/* ADC CDR register base address */\r\n#define CDR_ADDRESS ((uint32_t)0x40012308) \r\n\r\n/* ADC CCR register Mask */\r\n#define CR_CLEAR_MASK ((uint32_t)0xFFFC30E0) \r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup ADC_Private_Functions\r\n * @{\r\n */ \r\n\r\n/** @defgroup ADC_Group1 Initialization and Configuration functions\r\n * @brief Initialization and Configuration functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Initialization and Configuration functions\r\n =============================================================================== \r\n This section provides functions allowing to:\r\n - Initialize and configure the ADC Prescaler\r\n - ADC Conversion Resolution (12bit..6bit)\r\n - Scan Conversion Mode (multichannels or one channel) for regular group\r\n - ADC Continuous Conversion Mode (Continuous or Single conversion) for \r\n regular group\r\n - External trigger Edge and source of regular group, \r\n - Converted data alignment (left or right)\r\n - The number of ADC conversions that will be done using the sequencer for \r\n regular channel group\r\n - Multi ADC mode selection\r\n - Direct memory access mode selection for multi ADC mode \r\n - Delay between 2 sampling phases (used in dual or triple interleaved modes)\r\n - Enable or disable the ADC peripheral\r\n \r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Deinitializes all ADCs peripherals registers to their default reset \r\n * values.\r\n * @param None\r\n * @retval None\r\n */\r\nvoid ADC_DeInit(void)\r\n{\r\n /* Enable all ADCs reset state */\r\n RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, ENABLE);\r\n \r\n /* Release all ADCs from reset state */\r\n RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, DISABLE);\r\n}\r\n\r\n/**\r\n * @brief Initializes the ADCx peripheral according to the specified parameters \r\n * in the ADC_InitStruct.\r\n * @note This function is used to configure the global features of the ADC ( \r\n * Resolution and Data Alignment), however, the rest of the configuration\r\n * parameters are specific to the regular channels group (scan mode \r\n * activation, continuous mode activation, External trigger source and \r\n * edge, number of conversion in the regular channels group sequencer). \r\n * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r\n * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains\r\n * the configuration information for the specified ADC peripheral.\r\n * @retval None\r\n */\r\nvoid ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)\r\n{\r\n uint32_t tmpreg1 = 0;\r\n uint8_t tmpreg2 = 0;\r\n /* Check the parameters */\r\n assert_param(IS_ADC_ALL_PERIPH(ADCx));\r\n assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution)); \r\n assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));\r\n assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); \r\n assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge)); \r\n assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); \r\n assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); \r\n assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion));\r\n \r\n /*---------------------------- ADCx CR1 Configuration -----------------*/\r\n /* Get the ADCx CR1 value */\r\n tmpreg1 = ADCx->CR1;\r\n \r\n /* Clear RES and SCAN bits */\r\n tmpreg1 &= CR1_CLEAR_MASK;\r\n \r\n /* Configure ADCx: scan conversion mode and resolution */\r\n /* Set SCAN bit according to ADC_ScanConvMode value */\r\n /* Set RES bit according to ADC_Resolution value */ \r\n tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | \\\r\n ADC_InitStruct->ADC_Resolution);\r\n /* Write to ADCx CR1 */\r\n ADCx->CR1 = tmpreg1;\r\n /*---------------------------- ADCx CR2 Configuration -----------------*/\r\n /* Get the ADCx CR2 value */\r\n tmpreg1 = ADCx->CR2;\r\n \r\n /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */\r\n tmpreg1 &= CR2_CLEAR_MASK;\r\n \r\n /* Configure ADCx: external trigger event and edge, data alignment and \r\n continuous conversion mode */\r\n /* Set ALIGN bit according to ADC_DataAlign value */\r\n /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */ \r\n /* Set EXTSEL bits according to ADC_ExternalTrigConv value */\r\n /* Set CONT bit according to ADC_ContinuousConvMode value */\r\n tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | \\\r\n ADC_InitStruct->ADC_ExternalTrigConv | \r\n ADC_InitStruct->ADC_ExternalTrigConvEdge | \\\r\n ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));\r\n \r\n /* Write to ADCx CR2 */\r\n ADCx->CR2 = tmpreg1;\r\n /*---------------------------- ADCx SQR1 Configuration -----------------*/\r\n /* Get the ADCx SQR1 value */\r\n tmpreg1 = ADCx->SQR1;\r\n \r\n /* Clear L bits */\r\n tmpreg1 &= SQR1_L_RESET;\r\n \r\n /* Configure ADCx: regular channel sequence length */\r\n /* Set L bits according to ADC_NbrOfConversion value */\r\n tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1);\r\n tmpreg1 |= ((uint32_t)tmpreg2 << 20);\r\n \r\n /* Write to ADCx SQR1 */\r\n ADCx->SQR1 = tmpreg1;\r\n}\r\n\r\n/**\r\n * @brief Fills each ADC_InitStruct member with its default value.\r\n * @note This function is used to initialize the global features of the ADC ( \r\n * Resolution and Data Alignment), however, the rest of the configuration\r\n * parameters are specific to the regular channels group (scan mode \r\n * activation, continuous mode activation, External trigger source and \r\n * edge, number of conversion in the regular channels group sequencer). \r\n * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will \r\n * be initialized.\r\n * @retval None\r\n */\r\nvoid ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)\r\n{\r\n /* Initialize the ADC_Mode member */\r\n ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;\r\n\r\n /* initialize the ADC_ScanConvMode member */\r\n ADC_InitStruct->ADC_ScanConvMode = DISABLE;\r\n\r\n /* Initialize the ADC_ContinuousConvMode member */\r\n ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;\r\n\r\n /* Initialize the ADC_ExternalTrigConvEdge member */\r\n ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;\r\n\r\n /* Initialize the ADC_ExternalTrigConv member */\r\n ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;\r\n\r\n /* Initialize the ADC_DataAlign member */\r\n ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;\r\n\r\n /* Initialize the ADC_NbrOfConversion member */\r\n ADC_InitStruct->ADC_NbrOfConversion = 1;\r\n}\r\n\r\n/**\r\n * @brief Initializes the ADCs peripherals according to the specified parameters \r\n * in the ADC_CommonInitStruct.\r\n * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure \r\n * that contains the configuration information for All ADCs peripherals.\r\n * @retval None\r\n */\r\nvoid ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct)\r\n{\r\n uint32_t tmpreg1 = 0;\r\n /* Check the parameters */\r\n assert_param(IS_ADC_MODE(ADC_CommonInitStruct->ADC_Mode));\r\n assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler));\r\n assert_param(IS_ADC_DMA_ACCESS_MODE(ADC_CommonInitStruct->ADC_DMAAccessMode));\r\n assert_param(IS_ADC_SAMPLING_DELAY(ADC_CommonInitStruct->ADC_TwoSamplingDelay));\r\n /*---------------------------- ADC CCR Configuration -----------------*/\r\n /* Get the ADC CCR value */\r\n tmpreg1 = ADC->CCR;\r\n \r\n /* Clear MULTI, DELAY, DMA and ADCPRE bits */\r\n tmpreg1 &= CR_CLEAR_MASK;\r\n \r\n /* Configure ADCx: Multi mode, Delay between two sampling time, ADC prescaler,\r\n and DMA access mode for multimode */\r\n /* Set MULTI bits according to ADC_Mode value */\r\n /* Set ADCPRE bits according to ADC_Prescaler value */\r\n /* Set DMA bits according to ADC_DMAAccessMode value */\r\n /* Set DELAY bits according to ADC_TwoSamplingDelay value */ \r\n tmpreg1 |= (uint32_t)(ADC_CommonInitStruct->ADC_Mode | \r\n ADC_CommonInitStruct->ADC_Prescaler | \r\n ADC_CommonInitStruct->ADC_DMAAccessMode | \r\n ADC_CommonInitStruct->ADC_TwoSamplingDelay);\r\n \r\n /* Write to ADC CCR */\r\n ADC->CCR = tmpreg1;\r\n}\r\n\r\n/**\r\n * @brief Fills each ADC_CommonInitStruct member with its default value.\r\n * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure\r\n * which will be initialized.\r\n * @retval None\r\n */\r\nvoid ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct)\r\n{\r\n /* Initialize the ADC_Mode member */\r\n ADC_CommonInitStruct->ADC_Mode = ADC_Mode_Independent;\r\n\r\n /* initialize the ADC_Prescaler member */\r\n ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div2;\r\n\r\n /* Initialize the ADC_DMAAccessMode member */\r\n ADC_CommonInitStruct->ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;\r\n\r\n /* Initialize the ADC_TwoSamplingDelay member */\r\n ADC_CommonInitStruct->ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the specified ADC peripheral.\r\n * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r\n * @param NewState: new state of the ADCx peripheral. \r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_ADC_ALL_PERIPH(ADCx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n /* Set the ADON bit to wake up the ADC from power down mode */\r\n ADCx->CR2 |= (uint32_t)ADC_CR2_ADON;\r\n }\r\n else\r\n {\r\n /* Disable the selected ADC peripheral */\r\n ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON);\r\n }\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup ADC_Group2 Analog Watchdog configuration functions\r\n * @brief Analog Watchdog configuration functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Analog Watchdog configuration functions\r\n =============================================================================== \r\n\r\n This section provides functions allowing to configure the Analog Watchdog\r\n (AWD) feature in the ADC.\r\n \r\n A typical configuration Analog Watchdog is done following these steps :\r\n 1. the ADC guarded channel(s) is (are) selected using the \r\n ADC_AnalogWatchdogSingleChannelConfig() function.\r\n 2. The Analog watchdog lower and higher threshold are configured using the \r\n ADC_AnalogWatchdogThresholdsConfig() function.\r\n 3. The Analog watchdog is enabled and configured to enable the check, on one\r\n or more channels, using the ADC_AnalogWatchdogCmd() function.\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n \r\n/**\r\n * @brief Enables or disables the analog watchdog on single/all regular or \r\n * injected channels\r\n * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r\n * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration.\r\n * This parameter can be one of the following values:\r\n * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel\r\n * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel\r\n * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel\r\n * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel\r\n * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel\r\n * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels\r\n * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog\r\n * @retval None\t \r\n */\r\nvoid ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)\r\n{\r\n uint32_t tmpreg = 0;\r\n /* Check the parameters */\r\n assert_param(IS_ADC_ALL_PERIPH(ADCx));\r\n assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));\r\n \r\n /* Get the old register value */\r\n tmpreg = ADCx->CR1;\r\n \r\n /* Clear AWDEN, JAWDEN and AWDSGL bits */\r\n tmpreg &= CR1_AWDMode_RESET;\r\n \r\n /* Set the analog watchdog enable mode */\r\n tmpreg |= ADC_AnalogWatchdog;\r\n \r\n /* Store the new register value */\r\n ADCx->CR1 = tmpreg;\r\n}\r\n\r\n/**\r\n * @brief Configures the high and low thresholds of the analog watchdog.\r\n * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r\n * @param HighThreshold: the ADC analog watchdog High threshold value.\r\n * This parameter must be a 12-bit value.\r\n * @param LowThreshold: the ADC analog watchdog Low threshold value.\r\n * This parameter must be a 12-bit value.\r\n * @retval None\r\n */\r\nvoid ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,\r\n uint16_t LowThreshold)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_ADC_ALL_PERIPH(ADCx));\r\n assert_param(IS_ADC_THRESHOLD(HighThreshold));\r\n assert_param(IS_ADC_THRESHOLD(LowThreshold));\r\n \r\n /* Set the ADCx high threshold */\r\n ADCx->HTR = HighThreshold;\r\n \r\n /* Set the ADCx low threshold */\r\n ADCx->LTR = LowThreshold;\r\n}\r\n\r\n/**\r\n * @brief Configures the analog watchdog guarded single channel\r\n * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r\n * @param ADC_Channel: the ADC channel to configure for the analog watchdog. \r\n * This parameter can be one of the following values:\r\n * @arg ADC_Channel_0: ADC Channel0 selected\r\n * @arg ADC_Channel_1: ADC Channel1 selected\r\n * @arg ADC_Channel_2: ADC Channel2 selected\r\n * @arg ADC_Channel_3: ADC Channel3 selected\r\n * @arg ADC_Channel_4: ADC Channel4 selected\r\n * @arg ADC_Channel_5: ADC Channel5 selected\r\n * @arg ADC_Channel_6: ADC Channel6 selected\r\n * @arg ADC_Channel_7: ADC Channel7 selected\r\n * @arg ADC_Channel_8: ADC Channel8 selected\r\n * @arg ADC_Channel_9: ADC Channel9 selected\r\n * @arg ADC_Channel_10: ADC Channel10 selected\r\n * @arg ADC_Channel_11: ADC Channel11 selected\r\n * @arg ADC_Channel_12: ADC Channel12 selected\r\n * @arg ADC_Channel_13: ADC Channel13 selected\r\n * @arg ADC_Channel_14: ADC Channel14 selected\r\n * @arg ADC_Channel_15: ADC Channel15 selected\r\n * @arg ADC_Channel_16: ADC Channel16 selected\r\n * @arg ADC_Channel_17: ADC Channel17 selected\r\n * @arg ADC_Channel_18: ADC Channel18 selected\r\n * @retval None\r\n */\r\nvoid ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)\r\n{\r\n uint32_t tmpreg = 0;\r\n /* Check the parameters */\r\n assert_param(IS_ADC_ALL_PERIPH(ADCx));\r\n assert_param(IS_ADC_CHANNEL(ADC_Channel));\r\n \r\n /* Get the old register value */\r\n tmpreg = ADCx->CR1;\r\n \r\n /* Clear the Analog watchdog channel select bits */\r\n tmpreg &= CR1_AWDCH_RESET;\r\n \r\n /* Set the Analog watchdog channel */\r\n tmpreg |= ADC_Channel;\r\n \r\n /* Store the new register value */\r\n ADCx->CR1 = tmpreg;\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup ADC_Group3 Temperature Sensor, Vrefint (Voltage Reference internal) \r\n * and VBAT (Voltage BATtery) management functions\r\n * @brief Temperature Sensor, Vrefint and VBAT management functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Temperature Sensor, Vrefint and VBAT management functions\r\n =============================================================================== \r\n\r\n This section provides functions allowing to enable/ disable the internal \r\n connections between the ADC and the Temperature Sensor, the Vrefint and the\r\n Vbat sources.\r\n \r\n A typical configuration to get the Temperature sensor and Vrefint channels \r\n voltages is done following these steps :\r\n 1. Enable the internal connection of Temperature sensor and Vrefint sources \r\n with the ADC channels using ADC_TempSensorVrefintCmd() function. \r\n 2. Select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using \r\n ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions \r\n 3. Get the voltage values, using ADC_GetConversionValue() or \r\n ADC_GetInjectedConversionValue().\r\n\r\n A typical configuration to get the VBAT channel voltage is done following \r\n these steps :\r\n 1. Enable the internal connection of VBAT source with the ADC channel using \r\n ADC_VBATCmd() function. \r\n 2. Select the ADC_Channel_Vbat using ADC_RegularChannelConfig() or \r\n ADC_InjectedChannelConfig() functions \r\n 3. Get the voltage value, using ADC_GetConversionValue() or \r\n ADC_GetInjectedConversionValue().\r\n \r\n@endverbatim\r\n * @{\r\n */\r\n \r\n \r\n/**\r\n * @brief Enables or disables the temperature sensor and Vrefint channels.\r\n * @param NewState: new state of the temperature sensor and Vrefint channels.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid ADC_TempSensorVrefintCmd(FunctionalState NewState) \r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the temperature sensor and Vrefint channel*/\r\n ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE;\r\n }\r\n else\r\n {\r\n /* Disable the temperature sensor and Vrefint channel*/\r\n ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the VBAT (Voltage Battery) channel.\r\n * @param NewState: new state of the VBAT channel.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid ADC_VBATCmd(FunctionalState NewState) \r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the VBAT channel*/\r\n ADC->CCR |= (uint32_t)ADC_CCR_VBATE;\r\n }\r\n else\r\n {\r\n /* Disable the VBAT channel*/\r\n ADC->CCR &= (uint32_t)(~ADC_CCR_VBATE);\r\n }\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup ADC_Group4 Regular Channels Configuration functions\r\n * @brief Regular Channels Configuration functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Regular Channels Configuration functions\r\n =============================================================================== \r\n\r\n This section provides functions allowing to manage the ADC's regular channels,\r\n it is composed of 2 sub sections : \r\n \r\n 1. Configuration and management functions for regular channels: This subsection \r\n provides functions allowing to configure the ADC regular channels : \r\n - Configure the rank in the regular group sequencer for each channel\r\n - Configure the sampling time for each channel\r\n - select the conversion Trigger for regular channels\r\n - select the desired EOC event behavior configuration\r\n - Activate the continuous Mode (*)\r\n - Activate the Discontinuous Mode \r\n Please Note that the following features for regular channels are configurated\r\n using the ADC_Init() function : \r\n - scan mode activation \r\n - continuous mode activation (**) \r\n - External trigger source \r\n - External trigger edge \r\n - number of conversion in the regular channels group sequencer.\r\n \r\n @note (*) and (**) are performing the same configuration\r\n \r\n 2. Get the conversion data: This subsection provides an important function in \r\n the ADC peripheral since it returns the converted data of the current \r\n regular channel. When the Conversion value is read, the EOC Flag is \r\n automatically cleared.\r\n \r\n @note For multi ADC mode, the last ADC1, ADC2 and ADC3 regular conversions \r\n results data (in the selected multi mode) can be returned in the same \r\n time using ADC_GetMultiModeConversionValue() function. \r\n \r\n \r\n@endverbatim\r\n * @{\r\n */\r\n/**\r\n * @brief Configures for the selected ADC regular channel its corresponding\r\n * rank in the sequencer and its sample time.\r\n * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r\n * @param ADC_Channel: the ADC channel to configure. \r\n * This parameter can be one of the following values:\r\n * @arg ADC_Channel_0: ADC Channel0 selected\r\n * @arg ADC_Channel_1: ADC Channel1 selected\r\n * @arg ADC_Channel_2: ADC Channel2 selected\r\n * @arg ADC_Channel_3: ADC Channel3 selected\r\n * @arg ADC_Channel_4: ADC Channel4 selected\r\n * @arg ADC_Channel_5: ADC Channel5 selected\r\n * @arg ADC_Channel_6: ADC Channel6 selected\r\n * @arg ADC_Channel_7: ADC Channel7 selected\r\n * @arg ADC_Channel_8: ADC Channel8 selected\r\n * @arg ADC_Channel_9: ADC Channel9 selected\r\n * @arg ADC_Channel_10: ADC Channel10 selected\r\n * @arg ADC_Channel_11: ADC Channel11 selected\r\n * @arg ADC_Channel_12: ADC Channel12 selected\r\n * @arg ADC_Channel_13: ADC Channel13 selected\r\n * @arg ADC_Channel_14: ADC Channel14 selected\r\n * @arg ADC_Channel_15: ADC Channel15 selected\r\n * @arg ADC_Channel_16: ADC Channel16 selected\r\n * @arg ADC_Channel_17: ADC Channel17 selected\r\n * @arg ADC_Channel_18: ADC Channel18 selected \r\n * @param Rank: The rank in the regular group sequencer.\r\n * This parameter must be between 1 to 16.\r\n * @param ADC_SampleTime: The sample time value to be set for the selected channel. \r\n * This parameter can be one of the following values:\r\n * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles\r\n * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles\r\n * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles\r\n * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles\t\r\n * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles\t\r\n * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles\t\r\n * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles\t\r\n * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles\t\r\n * @retval None\r\n */\r\nvoid ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)\r\n{\r\n uint32_t tmpreg1 = 0, tmpreg2 = 0;\r\n /* Check the parameters */\r\n assert_param(IS_ADC_ALL_PERIPH(ADCx));\r\n assert_param(IS_ADC_CHANNEL(ADC_Channel));\r\n assert_param(IS_ADC_REGULAR_RANK(Rank));\r\n assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));\r\n \r\n /* if ADC_Channel_10 ... ADC_Channel_18 is selected */\r\n if (ADC_Channel > ADC_Channel_9)\r\n {\r\n /* Get the old register value */\r\n tmpreg1 = ADCx->SMPR1;\r\n \r\n /* Calculate the mask to clear */\r\n tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 10));\r\n \r\n /* Clear the old sample time */\r\n tmpreg1 &= ~tmpreg2;\r\n \r\n /* Calculate the mask to set */\r\n tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));\r\n \r\n /* Set the new sample time */\r\n tmpreg1 |= tmpreg2;\r\n \r\n /* Store the new register value */\r\n ADCx->SMPR1 = tmpreg1;\r\n }\r\n else /* ADC_Channel include in ADC_Channel_[0..9] */\r\n {\r\n /* Get the old register value */\r\n tmpreg1 = ADCx->SMPR2;\r\n \r\n /* Calculate the mask to clear */\r\n tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel);\r\n \r\n /* Clear the old sample time */\r\n tmpreg1 &= ~tmpreg2;\r\n \r\n /* Calculate the mask to set */\r\n tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);\r\n \r\n /* Set the new sample time */\r\n tmpreg1 |= tmpreg2;\r\n \r\n /* Store the new register value */\r\n ADCx->SMPR2 = tmpreg1;\r\n }\r\n /* For Rank 1 to 6 */\r\n if (Rank < 7)\r\n {\r\n /* Get the old register value */\r\n tmpreg1 = ADCx->SQR3;\r\n \r\n /* Calculate the mask to clear */\r\n tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 1));\r\n \r\n /* Clear the old SQx bits for the selected rank */\r\n tmpreg1 &= ~tmpreg2;\r\n \r\n /* Calculate the mask to set */\r\n tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));\r\n \r\n /* Set the SQx bits for the selected rank */\r\n tmpreg1 |= tmpreg2;\r\n \r\n /* Store the new register value */\r\n ADCx->SQR3 = tmpreg1;\r\n }\r\n /* For Rank 7 to 12 */\r\n else if (Rank < 13)\r\n {\r\n /* Get the old register value */\r\n tmpreg1 = ADCx->SQR2;\r\n \r\n /* Calculate the mask to clear */\r\n tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 7));\r\n \r\n /* Clear the old SQx bits for the selected rank */\r\n tmpreg1 &= ~tmpreg2;\r\n \r\n /* Calculate the mask to set */\r\n tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));\r\n \r\n /* Set the SQx bits for the selected rank */\r\n tmpreg1 |= tmpreg2;\r\n \r\n /* Store the new register value */\r\n ADCx->SQR2 = tmpreg1;\r\n }\r\n /* For Rank 13 to 16 */\r\n else\r\n {\r\n /* Get the old register value */\r\n tmpreg1 = ADCx->SQR1;\r\n \r\n /* Calculate the mask to clear */\r\n tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 13));\r\n \r\n /* Clear the old SQx bits for the selected rank */\r\n tmpreg1 &= ~tmpreg2;\r\n \r\n /* Calculate the mask to set */\r\n tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));\r\n \r\n /* Set the SQx bits for the selected rank */\r\n tmpreg1 |= tmpreg2;\r\n \r\n /* Store the new register value */\r\n ADCx->SQR1 = tmpreg1;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables the selected ADC software start conversion of the regular channels.\r\n * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r\n * @retval None\r\n */\r\nvoid ADC_SoftwareStartConv(ADC_TypeDef* ADCx)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_ADC_ALL_PERIPH(ADCx));\r\n \r\n /* Enable the selected ADC conversion for regular group */\r\n ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r\n}\r\n\r\n/**\r\n * @brief Gets the selected ADC Software start regular conversion Status.\r\n * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r\n * @retval The new state of ADC software start conversion (SET or RESET).\r\n */\r\nFlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)\r\n{\r\n FlagStatus bitstatus = RESET;\r\n /* Check the parameters */\r\n assert_param(IS_ADC_ALL_PERIPH(ADCx));\r\n \r\n /* Check the status of SWSTART bit */\r\n if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET)\r\n {\r\n /* SWSTART bit is set */\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n /* SWSTART bit is reset */\r\n bitstatus = RESET;\r\n }\r\n \r\n /* Return the SWSTART bit status */\r\n return bitstatus;\r\n}\r\n\r\n\r\n/**\r\n * @brief Enables or disables the EOC on each regular channel conversion\r\n * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r\n * @param NewState: new state of the selected ADC EOC flag rising\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_ADC_ALL_PERIPH(ADCx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected ADC EOC rising on each regular channel conversion */\r\n ADCx->CR2 |= (uint32_t)ADC_CR2_EOCS;\r\n }\r\n else\r\n {\r\n /* Disable the selected ADC EOC rising on each regular channel conversion */\r\n ADCx->CR2 &= (uint32_t)(~ADC_CR2_EOCS);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the ADC continuous conversion mode \r\n * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r\n * @param NewState: new state of the selected ADC continuous conversion mode\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_ADC_ALL_PERIPH(ADCx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected ADC continuous conversion mode */\r\n ADCx->CR2 |= (uint32_t)ADC_CR2_CONT;\r\n }\r\n else\r\n {\r\n /* Disable the selected ADC continuous conversion mode */\r\n ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Configures the discontinuous mode for the selected ADC regular group \r\n * channel.\r\n * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r\n * @param Number: specifies the discontinuous mode regular channel count value.\r\n * This number must be between 1 and 8.\r\n * @retval None\r\n */\r\nvoid ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)\r\n{\r\n uint32_t tmpreg1 = 0;\r\n uint32_t tmpreg2 = 0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_ADC_ALL_PERIPH(ADCx));\r\n assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));\r\n \r\n /* Get the old register value */\r\n tmpreg1 = ADCx->CR1;\r\n \r\n /* Clear the old discontinuous mode channel count */\r\n tmpreg1 &= CR1_DISCNUM_RESET;\r\n \r\n /* Set the discontinuous mode channel count */\r\n tmpreg2 = Number - 1;\r\n tmpreg1 |= tmpreg2 << 13;\r\n \r\n /* Store the new register value */\r\n ADCx->CR1 = tmpreg1;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the discontinuous mode on regular group channel \r\n * for the specified ADC\r\n * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r\n * @param NewState: new state of the selected ADC discontinuous mode on \r\n * regular group channel.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_ADC_ALL_PERIPH(ADCx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected ADC regular discontinuous mode */\r\n ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN;\r\n }\r\n else\r\n {\r\n /* Disable the selected ADC regular discontinuous mode */\r\n ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Returns the last ADCx conversion result data for regular channel.\r\n * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r\n * @retval The Data conversion value.\r\n */\r\nuint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_ADC_ALL_PERIPH(ADCx));\r\n \r\n /* Return the selected ADC conversion value */\r\n return (uint16_t) ADCx->DR;\r\n}\r\n\r\n/**\r\n * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results \r\n * data in the selected multi mode.\r\n * @param None \r\n * @retval The Data conversion value.\r\n * @note In dual mode, the value returned by this function is as following\r\n * Data[15:0] : these bits contain the regular data of ADC1.\r\n * Data[31:16]: these bits contain the regular data of ADC2.\r\n * @note In triple mode, the value returned by this function is as following\r\n * Data[15:0] : these bits contain alternatively the regular data of ADC1, ADC3 and ADC2.\r\n * Data[31:16]: these bits contain alternatively the regular data of ADC2, ADC1 and ADC3. \r\n */\r\nuint32_t ADC_GetMultiModeConversionValue(void)\r\n{\r\n /* Return the multi mode conversion value */\r\n return (*(__IO uint32_t *) CDR_ADDRESS);\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup ADC_Group5 Regular Channels DMA Configuration functions\r\n * @brief Regular Channels DMA Configuration functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Regular Channels DMA Configuration functions\r\n =============================================================================== \r\n\r\n This section provides functions allowing to configure the DMA for ADC regular \r\n channels.\r\n Since converted regular channel values are stored into a unique data register, \r\n it is useful to use DMA for conversion of more than one regular channel. This \r\n avoids the loss of the data already stored in the ADC Data register. \r\n \r\n When the DMA mode is enabled (using the ADC_DMACmd() function), after each\r\n conversion of a regular channel, a DMA request is generated.\r\n \r\n Depending on the \"DMA disable selection for Independent ADC mode\" \r\n configuration (using the ADC_DMARequestAfterLastTransferCmd() function), \r\n at the end of the last DMA transfer, two possibilities are allowed:\r\n - No new DMA request is issued to the DMA controller (feature DISABLED) \r\n - Requests can continue to be generated (feature ENABLED).\r\n \r\n Depending on the \"DMA disable selection for multi ADC mode\" configuration \r\n (using the void ADC_MultiModeDMARequestAfterLastTransferCmd() function), \r\n at the end of the last DMA transfer, two possibilities are allowed:\r\n - No new DMA request is issued to the DMA controller (feature DISABLED) \r\n - Requests can continue to be generated (feature ENABLED).\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n \r\n /**\r\n * @brief Enables or disables the specified ADC DMA request.\r\n * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r\n * @param NewState: new state of the selected ADC DMA transfer.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_ADC_ALL_PERIPH(ADCx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected ADC DMA request */\r\n ADCx->CR2 |= (uint32_t)ADC_CR2_DMA;\r\n }\r\n else\r\n {\r\n /* Disable the selected ADC DMA request */\r\n ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode) \r\n * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r\n * @param NewState: new state of the selected ADC DMA request after last transfer.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_ADC_ALL_PERIPH(ADCx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected ADC DMA request after last transfer */\r\n ADCx->CR2 |= (uint32_t)ADC_CR2_DDS;\r\n }\r\n else\r\n {\r\n /* Disable the selected ADC DMA request after last transfer */\r\n ADCx->CR2 &= (uint32_t)(~ADC_CR2_DDS);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the ADC DMA request after last transfer in multi ADC mode \r\n * @param NewState: new state of the selected ADC DMA request after last transfer.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @note if Enabled, DMA requests are issued as long as data are converted and \r\n * DMA mode for multi ADC mode (selected using ADC_CommonInit() function \r\n * by ADC_CommonInitStruct.ADC_DMAAccessMode structure member) is \r\n * ADC_DMAAccessMode_1, ADC_DMAAccessMode_2 or ADC_DMAAccessMode_3. \r\n * @retval None\r\n */\r\nvoid ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected ADC DMA request after last transfer */\r\n ADC->CCR |= (uint32_t)ADC_CCR_DDS;\r\n }\r\n else\r\n {\r\n /* Disable the selected ADC DMA request after last transfer */\r\n ADC->CCR &= (uint32_t)(~ADC_CCR_DDS);\r\n }\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup ADC_Group6 Injected channels Configuration functions\r\n * @brief Injected channels Configuration functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Injected channels Configuration functions\r\n =============================================================================== \r\n\r\n This section provide functions allowing to configure the ADC Injected channels,\r\n it is composed of 2 sub sections : \r\n \r\n 1. Configuration functions for Injected channels: This subsection provides \r\n functions allowing to configure the ADC injected channels : \r\n - Configure the rank in the injected group sequencer for each channel\r\n - Configure the sampling time for each channel \r\n - Activate the Auto injected Mode \r\n - Activate the Discontinuous Mode \r\n - scan mode activation \r\n - External/software trigger source \r\n - External trigger edge \r\n - injected channels sequencer.\r\n \r\n 2. Get the Specified Injected channel conversion data: This subsection \r\n provides an important function in the ADC peripheral since it returns the \r\n converted data of the specific injected channel.\r\n\r\n@endverbatim\r\n * @{\r\n */ \r\n/**\r\n * @brief Configures for the selected ADC injected channel its corresponding\r\n * rank in the sequencer and its sample time.\r\n * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r\n * @param ADC_Channel: the ADC channel to configure. \r\n * This parameter can be one of the following values:\r\n * @arg ADC_Channel_0: ADC Channel0 selected\r\n * @arg ADC_Channel_1: ADC Channel1 selected\r\n * @arg ADC_Channel_2: ADC Channel2 selected\r\n * @arg ADC_Channel_3: ADC Channel3 selected\r\n * @arg ADC_Channel_4: ADC Channel4 selected\r\n * @arg ADC_Channel_5: ADC Channel5 selected\r\n * @arg ADC_Channel_6: ADC Channel6 selected\r\n * @arg ADC_Channel_7: ADC Channel7 selected\r\n * @arg ADC_Channel_8: ADC Channel8 selected\r\n * @arg ADC_Channel_9: ADC Channel9 selected\r\n * @arg ADC_Channel_10: ADC Channel10 selected\r\n * @arg ADC_Channel_11: ADC Channel11 selected\r\n * @arg ADC_Channel_12: ADC Channel12 selected\r\n * @arg ADC_Channel_13: ADC Channel13 selected\r\n * @arg ADC_Channel_14: ADC Channel14 selected\r\n * @arg ADC_Channel_15: ADC Channel15 selected\r\n * @arg ADC_Channel_16: ADC Channel16 selected\r\n * @arg ADC_Channel_17: ADC Channel17 selected\r\n * @arg ADC_Channel_18: ADC Channel18 selected \r\n * @param Rank: The rank in the injected group sequencer. \r\n * This parameter must be between 1 to 4.\r\n * @param ADC_SampleTime: The sample time value to be set for the selected channel. \r\n * This parameter can be one of the following values:\r\n * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles\r\n * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles\r\n * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles\r\n * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles\t\r\n * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles\t\r\n * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles\t\r\n * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles\t\r\n * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles\t\r\n * @retval None\r\n */\r\nvoid ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)\r\n{\r\n uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;\r\n /* Check the parameters */\r\n assert_param(IS_ADC_ALL_PERIPH(ADCx));\r\n assert_param(IS_ADC_CHANNEL(ADC_Channel));\r\n assert_param(IS_ADC_INJECTED_RANK(Rank));\r\n assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));\r\n /* if ADC_Channel_10 ... ADC_Channel_18 is selected */\r\n if (ADC_Channel > ADC_Channel_9)\r\n {\r\n /* Get the old register value */\r\n tmpreg1 = ADCx->SMPR1;\r\n /* Calculate the mask to clear */\r\n tmpreg2 = SMPR1_SMP_SET << (3*(ADC_Channel - 10));\r\n /* Clear the old sample time */\r\n tmpreg1 &= ~tmpreg2;\r\n /* Calculate the mask to set */\r\n tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10));\r\n /* Set the new sample time */\r\n tmpreg1 |= tmpreg2;\r\n /* Store the new register value */\r\n ADCx->SMPR1 = tmpreg1;\r\n }\r\n else /* ADC_Channel include in ADC_Channel_[0..9] */\r\n {\r\n /* Get the old register value */\r\n tmpreg1 = ADCx->SMPR2;\r\n /* Calculate the mask to clear */\r\n tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel);\r\n /* Clear the old sample time */\r\n tmpreg1 &= ~tmpreg2;\r\n /* Calculate the mask to set */\r\n tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);\r\n /* Set the new sample time */\r\n tmpreg1 |= tmpreg2;\r\n /* Store the new register value */\r\n ADCx->SMPR2 = tmpreg1;\r\n }\r\n /* Rank configuration */\r\n /* Get the old register value */\r\n tmpreg1 = ADCx->JSQR;\r\n /* Get JL value: Number = JL+1 */\r\n tmpreg3 = (tmpreg1 & JSQR_JL_SET)>> 20;\r\n /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */\r\n tmpreg2 = JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));\r\n /* Clear the old JSQx bits for the selected rank */\r\n tmpreg1 &= ~tmpreg2;\r\n /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */\r\n tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));\r\n /* Set the JSQx bits for the selected rank */\r\n tmpreg1 |= tmpreg2;\r\n /* Store the new register value */\r\n ADCx->JSQR = tmpreg1;\r\n}\r\n\r\n/**\r\n * @brief Configures the sequencer length for injected channels\r\n * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r\n * @param Length: The sequencer length. \r\n * This parameter must be a number between 1 to 4.\r\n * @retval None\r\n */\r\nvoid ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)\r\n{\r\n uint32_t tmpreg1 = 0;\r\n uint32_t tmpreg2 = 0;\r\n /* Check the parameters */\r\n assert_param(IS_ADC_ALL_PERIPH(ADCx));\r\n assert_param(IS_ADC_INJECTED_LENGTH(Length));\r\n \r\n /* Get the old register value */\r\n tmpreg1 = ADCx->JSQR;\r\n \r\n /* Clear the old injected sequence length JL bits */\r\n tmpreg1 &= JSQR_JL_RESET;\r\n \r\n /* Set the injected sequence length JL bits */\r\n tmpreg2 = Length - 1; \r\n tmpreg1 |= tmpreg2 << 20;\r\n \r\n /* Store the new register value */\r\n ADCx->JSQR = tmpreg1;\r\n}\r\n\r\n/**\r\n * @brief Set the injected channels conversion value offset\r\n * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r\n * @param ADC_InjectedChannel: the ADC injected channel to set its offset. \r\n * This parameter can be one of the following values:\r\n * @arg ADC_InjectedChannel_1: Injected Channel1 selected\r\n * @arg ADC_InjectedChannel_2: Injected Channel2 selected\r\n * @arg ADC_InjectedChannel_3: Injected Channel3 selected\r\n * @arg ADC_InjectedChannel_4: Injected Channel4 selected\r\n * @param Offset: the offset value for the selected ADC injected channel\r\n * This parameter must be a 12bit value.\r\n * @retval None\r\n */\r\nvoid ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)\r\n{\r\n __IO uint32_t tmp = 0;\r\n /* Check the parameters */\r\n assert_param(IS_ADC_ALL_PERIPH(ADCx));\r\n assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));\r\n assert_param(IS_ADC_OFFSET(Offset));\r\n \r\n tmp = (uint32_t)ADCx;\r\n tmp += ADC_InjectedChannel;\r\n \r\n /* Set the selected injected channel data offset */\r\n *(__IO uint32_t *) tmp = (uint32_t)Offset;\r\n}\r\n\r\n /**\r\n * @brief Configures the ADCx external trigger for injected channels conversion.\r\n * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r\n * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion.\r\n * This parameter can be one of the following values: \r\n * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected \r\n * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected \r\n * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected \r\n * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected \r\n * @arg ADC_ExternalTrigInjecConv_T3_CC2: Timer3 capture compare2 selected \r\n * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected \r\n * @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected \r\n * @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected \r\n * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected \r\n * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected \r\n * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected \r\n * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected \r\n * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected\r\n * @arg ADC_ExternalTrigInjecConv_T8_CC3: Timer8 capture compare3 selected \r\n * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected \r\n * @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected \r\n * @retval None\r\n */\r\nvoid ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)\r\n{\r\n uint32_t tmpreg = 0;\r\n /* Check the parameters */\r\n assert_param(IS_ADC_ALL_PERIPH(ADCx));\r\n assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));\r\n \r\n /* Get the old register value */\r\n tmpreg = ADCx->CR2;\r\n \r\n /* Clear the old external event selection for injected group */\r\n tmpreg &= CR2_JEXTSEL_RESET;\r\n \r\n /* Set the external event selection for injected group */\r\n tmpreg |= ADC_ExternalTrigInjecConv;\r\n \r\n /* Store the new register value */\r\n ADCx->CR2 = tmpreg;\r\n}\r\n\r\n/**\r\n * @brief Configures the ADCx external trigger edge for injected channels conversion.\r\n * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r\n * @param ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger edge\r\n * to start injected conversion. \r\n * This parameter can be one of the following values:\r\n * @arg ADC_ExternalTrigInjecConvEdge_None: external trigger disabled for \r\n * injected conversion\r\n * @arg ADC_ExternalTrigInjecConvEdge_Rising: detection on rising edge\r\n * @arg ADC_ExternalTrigInjecConvEdge_Falling: detection on falling edge\r\n * @arg ADC_ExternalTrigInjecConvEdge_RisingFalling: detection on both rising \r\n * and falling edge\r\n * @retval None\r\n */\r\nvoid ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge)\r\n{\r\n uint32_t tmpreg = 0;\r\n /* Check the parameters */\r\n assert_param(IS_ADC_ALL_PERIPH(ADCx));\r\n assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge));\r\n /* Get the old register value */\r\n tmpreg = ADCx->CR2;\r\n /* Clear the old external trigger edge for injected group */\r\n tmpreg &= CR2_JEXTEN_RESET;\r\n /* Set the new external trigger edge for injected group */\r\n tmpreg |= ADC_ExternalTrigInjecConvEdge;\r\n /* Store the new register value */\r\n ADCx->CR2 = tmpreg;\r\n}\r\n\r\n/**\r\n * @brief Enables the selected ADC software start conversion of the injected channels.\r\n * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r\n * @retval None\r\n */\r\nvoid ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_ADC_ALL_PERIPH(ADCx));\r\n /* Enable the selected ADC conversion for injected group */\r\n ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART;\r\n}\r\n\r\n/**\r\n * @brief Gets the selected ADC Software start injected conversion Status.\r\n * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r\n * @retval The new state of ADC software start injected conversion (SET or RESET).\r\n */\r\nFlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)\r\n{\r\n FlagStatus bitstatus = RESET;\r\n /* Check the parameters */\r\n assert_param(IS_ADC_ALL_PERIPH(ADCx));\r\n \r\n /* Check the status of JSWSTART bit */\r\n if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET)\r\n {\r\n /* JSWSTART bit is set */\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n /* JSWSTART bit is reset */\r\n bitstatus = RESET;\r\n }\r\n /* Return the JSWSTART bit status */\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the selected ADC automatic injected group \r\n * conversion after regular one.\r\n * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r\n * @param NewState: new state of the selected ADC auto injected conversion\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_ADC_ALL_PERIPH(ADCx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected ADC automatic injected group conversion */\r\n ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO;\r\n }\r\n else\r\n {\r\n /* Disable the selected ADC automatic injected group conversion */\r\n ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the discontinuous mode for injected group \r\n * channel for the specified ADC\r\n * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r\n * @param NewState: new state of the selected ADC discontinuous mode on injected\r\n * group channel.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_ADC_ALL_PERIPH(ADCx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected ADC injected discontinuous mode */\r\n ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN;\r\n }\r\n else\r\n {\r\n /* Disable the selected ADC injected discontinuous mode */\r\n ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Returns the ADC injected channel conversion result\r\n * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r\n * @param ADC_InjectedChannel: the converted ADC injected channel.\r\n * This parameter can be one of the following values:\r\n * @arg ADC_InjectedChannel_1: Injected Channel1 selected\r\n * @arg ADC_InjectedChannel_2: Injected Channel2 selected\r\n * @arg ADC_InjectedChannel_3: Injected Channel3 selected\r\n * @arg ADC_InjectedChannel_4: Injected Channel4 selected\r\n * @retval The Data conversion value.\r\n */\r\nuint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)\r\n{\r\n __IO uint32_t tmp = 0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_ADC_ALL_PERIPH(ADCx));\r\n assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));\r\n\r\n tmp = (uint32_t)ADCx;\r\n tmp += ADC_InjectedChannel + JDR_OFFSET;\r\n \r\n /* Returns the selected injected channel conversion data value */\r\n return (uint16_t) (*(__IO uint32_t*) tmp); \r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup ADC_Group7 Interrupts and flags management functions\r\n * @brief Interrupts and flags management functions\r\n *\r\n@verbatim \r\n ===============================================================================\r\n Interrupts and flags management functions\r\n =============================================================================== \r\n\r\n This section provides functions allowing to configure the ADC Interrupts and \r\n to get the status and clear flags and Interrupts pending bits.\r\n \r\n Each ADC provides 4 Interrupts sources and 6 Flags which can be divided into \r\n 3 groups:\r\n \r\n I. Flags and Interrupts for ADC regular channels\r\n =================================================\r\n Flags :\r\n ---------- \r\n 1. ADC_FLAG_OVR : Overrun detection when regular converted data are lost\r\n\r\n 2. ADC_FLAG_EOC : Regular channel end of conversion ==> to indicate (depending \r\n on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() ) the end of:\r\n ==> a regular CHANNEL conversion \r\n ==> sequence of regular GROUP conversions .\r\n\r\n 3. ADC_FLAG_STRT: Regular channel start ==> to indicate when regular CHANNEL \r\n conversion starts.\r\n\r\n Interrupts :\r\n ------------\r\n 1. ADC_IT_OVR : specifies the interrupt source for Overrun detection event. \r\n 2. ADC_IT_EOC : specifies the interrupt source for Regular channel end of \r\n conversion event.\r\n \r\n \r\n II. Flags and Interrupts for ADC Injected channels\r\n =================================================\r\n Flags :\r\n ---------- \r\n 1. ADC_FLAG_JEOC : Injected channel end of conversion ==> to indicate at \r\n the end of injected GROUP conversion \r\n \r\n 2. ADC_FLAG_JSTRT: Injected channel start ==> to indicate hardware when \r\n injected GROUP conversion starts.\r\n\r\n Interrupts :\r\n ------------\r\n 1. ADC_IT_JEOC : specifies the interrupt source for Injected channel end of \r\n conversion event. \r\n\r\n III. General Flags and Interrupts for the ADC\r\n ================================================= \r\n Flags :\r\n ---------- \r\n 1. ADC_FLAG_AWD: Analog watchdog ==> to indicate if the converted voltage \r\n crosses the programmed thresholds values.\r\n \r\n Interrupts :\r\n ------------\r\n 1. ADC_IT_AWD : specifies the interrupt source for Analog watchdog event. \r\n\r\n \r\n The user should identify which mode will be used in his application to manage \r\n the ADC controller events: Polling mode or Interrupt mode.\r\n \r\n In the Polling Mode it is advised to use the following functions:\r\n - ADC_GetFlagStatus() : to check if flags events occur. \r\n - ADC_ClearFlag() : to clear the flags events.\r\n \r\n In the Interrupt Mode it is advised to use the following functions:\r\n - ADC_ITConfig() : to enable or disable the interrupt source.\r\n - ADC_GetITStatus() : to check if Interrupt occurs.\r\n - ADC_ClearITPendingBit() : to clear the Interrupt pending Bit \r\n (corresponding Flag). \r\n@endverbatim\r\n * @{\r\n */ \r\n/**\r\n * @brief Enables or disables the specified ADC interrupts.\r\n * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r\n * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. \r\n * This parameter can be one of the following values:\r\n * @arg ADC_IT_EOC: End of conversion interrupt mask\r\n * @arg ADC_IT_AWD: Analog watchdog interrupt mask\r\n * @arg ADC_IT_JEOC: End of injected conversion interrupt mask\r\n * @arg ADC_IT_OVR: Overrun interrupt enable \r\n * @param NewState: new state of the specified ADC interrupts.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) \r\n{\r\n uint32_t itmask = 0;\r\n /* Check the parameters */\r\n assert_param(IS_ADC_ALL_PERIPH(ADCx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n assert_param(IS_ADC_IT(ADC_IT)); \r\n\r\n /* Get the ADC IT index */\r\n itmask = (uint8_t)ADC_IT;\r\n itmask = (uint32_t)0x01 << itmask; \r\n\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected ADC interrupts */\r\n ADCx->CR1 |= itmask;\r\n }\r\n else\r\n {\r\n /* Disable the selected ADC interrupts */\r\n ADCx->CR1 &= (~(uint32_t)itmask);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Checks whether the specified ADC flag is set or not.\r\n * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r\n * @param ADC_FLAG: specifies the flag to check. \r\n * This parameter can be one of the following values:\r\n * @arg ADC_FLAG_AWD: Analog watchdog flag\r\n * @arg ADC_FLAG_EOC: End of conversion flag\r\n * @arg ADC_FLAG_JEOC: End of injected group conversion flag\r\n * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag\r\n * @arg ADC_FLAG_STRT: Start of regular group conversion flag\r\n * @arg ADC_FLAG_OVR: Overrun flag \r\n * @retval The new state of ADC_FLAG (SET or RESET).\r\n */\r\nFlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)\r\n{\r\n FlagStatus bitstatus = RESET;\r\n /* Check the parameters */\r\n assert_param(IS_ADC_ALL_PERIPH(ADCx));\r\n assert_param(IS_ADC_GET_FLAG(ADC_FLAG));\r\n\r\n /* Check the status of the specified ADC flag */\r\n if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)\r\n {\r\n /* ADC_FLAG is set */\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n /* ADC_FLAG is reset */\r\n bitstatus = RESET;\r\n }\r\n /* Return the ADC_FLAG status */\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @brief Clears the ADCx's pending flags.\r\n * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r\n * @param ADC_FLAG: specifies the flag to clear. \r\n * This parameter can be any combination of the following values:\r\n * @arg ADC_FLAG_AWD: Analog watchdog flag\r\n * @arg ADC_FLAG_EOC: End of conversion flag\r\n * @arg ADC_FLAG_JEOC: End of injected group conversion flag\r\n * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag\r\n * @arg ADC_FLAG_STRT: Start of regular group conversion flag\r\n * @arg ADC_FLAG_OVR: Overrun flag \r\n * @retval None\r\n */\r\nvoid ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_ADC_ALL_PERIPH(ADCx));\r\n assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));\r\n\r\n /* Clear the selected ADC flags */\r\n ADCx->SR = ~(uint32_t)ADC_FLAG;\r\n}\r\n\r\n/**\r\n * @brief Checks whether the specified ADC interrupt has occurred or not.\r\n * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r\n * @param ADC_IT: specifies the ADC interrupt source to check. \r\n * This parameter can be one of the following values:\r\n * @arg ADC_IT_EOC: End of conversion interrupt mask\r\n * @arg ADC_IT_AWD: Analog watchdog interrupt mask\r\n * @arg ADC_IT_JEOC: End of injected conversion interrupt mask\r\n * @arg ADC_IT_OVR: Overrun interrupt mask \r\n * @retval The new state of ADC_IT (SET or RESET).\r\n */\r\nITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)\r\n{\r\n ITStatus bitstatus = RESET;\r\n uint32_t itmask = 0, enablestatus = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_ADC_ALL_PERIPH(ADCx));\r\n assert_param(IS_ADC_IT(ADC_IT));\r\n\r\n /* Get the ADC IT index */\r\n itmask = ADC_IT >> 8;\r\n\r\n /* Get the ADC_IT enable bit status */\r\n enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)) ;\r\n\r\n /* Check the status of the specified ADC interrupt */\r\n if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus)\r\n {\r\n /* ADC_IT is set */\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n /* ADC_IT is reset */\r\n bitstatus = RESET;\r\n }\r\n /* Return the ADC_IT status */\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @brief Clears the ADCx's interrupt pending bits.\r\n * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r\n * @param ADC_IT: specifies the ADC interrupt pending bit to clear.\r\n * This parameter can be one of the following values:\r\n * @arg ADC_IT_EOC: End of conversion interrupt mask\r\n * @arg ADC_IT_AWD: Analog watchdog interrupt mask\r\n * @arg ADC_IT_JEOC: End of injected conversion interrupt mask\r\n * @arg ADC_IT_OVR: Overrun interrupt mask \r\n * @retval None\r\n */\r\nvoid ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)\r\n{\r\n uint8_t itmask = 0;\r\n /* Check the parameters */\r\n assert_param(IS_ADC_ALL_PERIPH(ADCx));\r\n assert_param(IS_ADC_IT(ADC_IT)); \r\n /* Get the ADC IT index */\r\n itmask = (uint8_t)(ADC_IT >> 8);\r\n /* Clear the selected ADC interrupt pending bits */\r\n ADCx->SR = ~(uint32_t)itmask;\r\n} \r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_can.c\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file provides firmware functions to manage the following \r\n * functionalities of the Controller area network (CAN) peripheral: \r\n * - Initialization and Configuration \r\n * - CAN Frames Transmission \r\n * - CAN Frames Reception \r\n * - Operation modes switch \r\n * - Error management \r\n * - Interrupts and flags \r\n * \r\n * @verbatim\r\n * \r\n * =================================================================== \r\n * How to use this driver\r\n * ===================================================================\r\n \r\n * 1. Enable the CAN controller interface clock using \r\n * RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE); for CAN1 \r\n * and RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE); for CAN2\r\n * @note In case you are using CAN2 only, you have to enable the CAN1 clock.\r\n * \r\n * 2. CAN pins configuration\r\n * - Enable the clock for the CAN GPIOs using the following function:\r\n * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); \r\n * - Connect the involved CAN pins to AF9 using the following function \r\n * GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_CANx); \r\n * - Configure these CAN pins in alternate function mode by calling\r\n * the function GPIO_Init();\r\n * \r\n * 3. Initialise and configure the CAN using CAN_Init() and \r\n * CAN_FilterInit() functions. \r\n * \r\n * 4. Transmit the desired CAN frame using CAN_Transmit() function.\r\n * \r\n * 5. Check the transmission of a CAN frame using CAN_TransmitStatus()\r\n * function.\r\n * \r\n * 6. Cancel the transmission of a CAN frame using CAN_CancelTransmit()\r\n * function. \r\n * \r\n * 7. Receive a CAN frame using CAN_Recieve() function.\r\n * \r\n * 8. Release the receive FIFOs using CAN_FIFORelease() function.\r\n * \r\n * 9. Return the number of pending received frames using \r\n * CAN_MessagePending() function. \r\n * \r\n * 10. To control CAN events you can use one of the following two methods:\r\n * - Check on CAN flags using the CAN_GetFlagStatus() function. \r\n * - Use CAN interrupts through the function CAN_ITConfig() at \r\n * initialization phase and CAN_GetITStatus() function into \r\n * interrupt routines to check if the event has occurred or not.\r\n * After checking on a flag you should clear it using CAN_ClearFlag()\r\n * function. And after checking on an interrupt event you should \r\n * clear it using CAN_ClearITPendingBit() function. \r\n * \r\n * \r\n * @endverbatim\r\n * \r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx_can.h\"\r\n#include \"stm32f4xx_rcc.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @defgroup CAN \r\n * @brief CAN driver modules\r\n * @{\r\n */ \r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n\r\n/* CAN Master Control Register bits */\r\n#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */\r\n\r\n/* CAN Mailbox Transmit Request */\r\n#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */\r\n\r\n/* CAN Filter Master Register bits */\r\n#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */\r\n\r\n/* Time out for INAK bit */\r\n#define INAK_TIMEOUT ((uint32_t)0x0000FFFF)\r\n/* Time out for SLAK bit */\r\n#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF)\r\n\r\n/* Flags in TSR register */\r\n#define CAN_FLAGS_TSR ((uint32_t)0x08000000) \r\n/* Flags in RF1R register */\r\n#define CAN_FLAGS_RF1R ((uint32_t)0x04000000) \r\n/* Flags in RF0R register */\r\n#define CAN_FLAGS_RF0R ((uint32_t)0x02000000) \r\n/* Flags in MSR register */\r\n#define CAN_FLAGS_MSR ((uint32_t)0x01000000) \r\n/* Flags in ESR register */\r\n#define CAN_FLAGS_ESR ((uint32_t)0x00F00000) \r\n\r\n/* Mailboxes definition */\r\n#define CAN_TXMAILBOX_0 ((uint8_t)0x00)\r\n#define CAN_TXMAILBOX_1 ((uint8_t)0x01)\r\n#define CAN_TXMAILBOX_2 ((uint8_t)0x02) \r\n\r\n#define CAN_MODE_MASK ((uint32_t) 0x00000003)\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\nstatic ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);\r\n\r\n/** @defgroup CAN_Private_Functions\r\n * @{\r\n */\r\n\r\n/** @defgroup CAN_Group1 Initialization and Configuration functions\r\n * @brief Initialization and Configuration functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Initialization and Configuration functions\r\n =============================================================================== \r\n This section provides functions allowing to \r\n - Initialize the CAN peripherals : Prescaler, operating mode, the maximum number \r\n of time quanta to perform resynchronization, the number of time quanta in\r\n Bit Segment 1 and 2 and many other modes. \r\n Refer to @ref CAN_InitTypeDef for more details.\r\n - Configures the CAN reception filter. \r\n - Select the start bank filter for slave CAN.\r\n - Enables or disables the Debug Freeze mode for CAN\r\n - Enables or disables the CAN Time Trigger Operation communication mode\r\n \r\n@endverbatim\r\n * @{\r\n */\r\n \r\n/**\r\n * @brief Deinitializes the CAN peripheral registers to their default reset values.\r\n * @param CANx: where x can be 1 or 2 to select the CAN peripheral.\r\n * @retval None.\r\n */\r\nvoid CAN_DeInit(CAN_TypeDef* CANx)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_CAN_ALL_PERIPH(CANx));\r\n \r\n if (CANx == CAN1)\r\n {\r\n /* Enable CAN1 reset state */\r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE);\r\n /* Release CAN1 from reset state */\r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE);\r\n }\r\n else\r\n { \r\n /* Enable CAN2 reset state */\r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE);\r\n /* Release CAN2 from reset state */\r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Initializes the CAN peripheral according to the specified\r\n * parameters in the CAN_InitStruct.\r\n * @param CANx: where x can be 1 or 2 to select the CAN peripheral.\r\n * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that contains\r\n * the configuration information for the CAN peripheral.\r\n * @retval Constant indicates initialization succeed which will be \r\n * CAN_InitStatus_Failed or CAN_InitStatus_Success.\r\n */\r\nuint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)\r\n{\r\n uint8_t InitStatus = CAN_InitStatus_Failed;\r\n uint32_t wait_ack = 0x00000000;\r\n /* Check the parameters */\r\n assert_param(IS_CAN_ALL_PERIPH(CANx));\r\n assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));\r\n assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));\r\n assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));\r\n assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));\r\n assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));\r\n assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));\r\n assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));\r\n assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));\r\n assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));\r\n assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));\r\n assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));\r\n\r\n /* Exit from sleep mode */\r\n CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP);\r\n\r\n /* Request initialisation */\r\n CANx->MCR |= CAN_MCR_INRQ ;\r\n\r\n /* Wait the acknowledge */\r\n while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))\r\n {\r\n wait_ack++;\r\n }\r\n\r\n /* Check acknowledge */\r\n if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)\r\n {\r\n InitStatus = CAN_InitStatus_Failed;\r\n }\r\n else \r\n {\r\n /* Set the time triggered communication mode */\r\n if (CAN_InitStruct->CAN_TTCM == ENABLE)\r\n {\r\n CANx->MCR |= CAN_MCR_TTCM;\r\n }\r\n else\r\n {\r\n CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM;\r\n }\r\n\r\n /* Set the automatic bus-off management */\r\n if (CAN_InitStruct->CAN_ABOM == ENABLE)\r\n {\r\n CANx->MCR |= CAN_MCR_ABOM;\r\n }\r\n else\r\n {\r\n CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM;\r\n }\r\n\r\n /* Set the automatic wake-up mode */\r\n if (CAN_InitStruct->CAN_AWUM == ENABLE)\r\n {\r\n CANx->MCR |= CAN_MCR_AWUM;\r\n }\r\n else\r\n {\r\n CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM;\r\n }\r\n\r\n /* Set the no automatic retransmission */\r\n if (CAN_InitStruct->CAN_NART == ENABLE)\r\n {\r\n CANx->MCR |= CAN_MCR_NART;\r\n }\r\n else\r\n {\r\n CANx->MCR &= ~(uint32_t)CAN_MCR_NART;\r\n }\r\n\r\n /* Set the receive FIFO locked mode */\r\n if (CAN_InitStruct->CAN_RFLM == ENABLE)\r\n {\r\n CANx->MCR |= CAN_MCR_RFLM;\r\n }\r\n else\r\n {\r\n CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM;\r\n }\r\n\r\n /* Set the transmit FIFO priority */\r\n if (CAN_InitStruct->CAN_TXFP == ENABLE)\r\n {\r\n CANx->MCR |= CAN_MCR_TXFP;\r\n }\r\n else\r\n {\r\n CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP;\r\n }\r\n\r\n /* Set the bit timing register */\r\n CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \\\r\n ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \\\r\n ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \\\r\n ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \\\r\n ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);\r\n\r\n /* Request leave initialisation */\r\n CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ;\r\n\r\n /* Wait the acknowledge */\r\n wait_ack = 0;\r\n\r\n while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))\r\n {\r\n wait_ack++;\r\n }\r\n\r\n /* ...and check acknowledged */\r\n if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)\r\n {\r\n InitStatus = CAN_InitStatus_Failed;\r\n }\r\n else\r\n {\r\n InitStatus = CAN_InitStatus_Success ;\r\n }\r\n }\r\n\r\n /* At this step, return the status of initialization */\r\n return InitStatus;\r\n}\r\n\r\n/**\r\n * @brief Configures the CAN reception filter according to the specified\r\n * parameters in the CAN_FilterInitStruct.\r\n * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef structure that\r\n * contains the configuration information.\r\n * @retval None\r\n */\r\nvoid CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)\r\n{\r\n uint32_t filter_number_bit_pos = 0;\r\n /* Check the parameters */\r\n assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));\r\n assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));\r\n assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));\r\n assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));\r\n assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));\r\n\r\n filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber;\r\n\r\n /* Initialisation mode for the filter */\r\n CAN1->FMR |= FMR_FINIT;\r\n\r\n /* Filter Deactivation */\r\n CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos;\r\n\r\n /* Filter Scale */\r\n if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)\r\n {\r\n /* 16-bit scale for the filter */\r\n CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos;\r\n\r\n /* First 16-bit identifier and First 16-bit mask */\r\n /* Or First 16-bit identifier and Second 16-bit identifier */\r\n CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = \r\n ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |\r\n (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);\r\n\r\n /* Second 16-bit identifier and Second 16-bit mask */\r\n /* Or Third 16-bit identifier and Fourth 16-bit identifier */\r\n CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = \r\n ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |\r\n (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);\r\n }\r\n\r\n if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)\r\n {\r\n /* 32-bit scale for the filter */\r\n CAN1->FS1R |= filter_number_bit_pos;\r\n /* 32-bit identifier or First 32-bit identifier */\r\n CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = \r\n ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |\r\n (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);\r\n /* 32-bit mask or Second 32-bit identifier */\r\n CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = \r\n ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |\r\n (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);\r\n }\r\n\r\n /* Filter Mode */\r\n if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)\r\n {\r\n /*Id/Mask mode for the filter*/\r\n CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos;\r\n }\r\n else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */\r\n {\r\n /*Identifier list mode for the filter*/\r\n CAN1->FM1R |= (uint32_t)filter_number_bit_pos;\r\n }\r\n\r\n /* Filter FIFO assignment */\r\n if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0)\r\n {\r\n /* FIFO 0 assignation for the filter */\r\n CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos;\r\n }\r\n\r\n if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1)\r\n {\r\n /* FIFO 1 assignation for the filter */\r\n CAN1->FFA1R |= (uint32_t)filter_number_bit_pos;\r\n }\r\n \r\n /* Filter activation */\r\n if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)\r\n {\r\n CAN1->FA1R |= filter_number_bit_pos;\r\n }\r\n\r\n /* Leave the initialisation mode for the filter */\r\n CAN1->FMR &= ~FMR_FINIT;\r\n}\r\n\r\n/**\r\n * @brief Fills each CAN_InitStruct member with its default value.\r\n * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which ill be initialized.\r\n * @retval None\r\n */\r\nvoid CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)\r\n{\r\n /* Reset CAN init structure parameters values */\r\n \r\n /* Initialize the time triggered communication mode */\r\n CAN_InitStruct->CAN_TTCM = DISABLE;\r\n \r\n /* Initialize the automatic bus-off management */\r\n CAN_InitStruct->CAN_ABOM = DISABLE;\r\n \r\n /* Initialize the automatic wake-up mode */\r\n CAN_InitStruct->CAN_AWUM = DISABLE;\r\n \r\n /* Initialize the no automatic retransmission */\r\n CAN_InitStruct->CAN_NART = DISABLE;\r\n \r\n /* Initialize the receive FIFO locked mode */\r\n CAN_InitStruct->CAN_RFLM = DISABLE;\r\n \r\n /* Initialize the transmit FIFO priority */\r\n CAN_InitStruct->CAN_TXFP = DISABLE;\r\n \r\n /* Initialize the CAN_Mode member */\r\n CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;\r\n \r\n /* Initialize the CAN_SJW member */\r\n CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;\r\n \r\n /* Initialize the CAN_BS1 member */\r\n CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;\r\n \r\n /* Initialize the CAN_BS2 member */\r\n CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;\r\n \r\n /* Initialize the CAN_Prescaler member */\r\n CAN_InitStruct->CAN_Prescaler = 1;\r\n}\r\n\r\n/**\r\n * @brief Select the start bank filter for slave CAN.\r\n * @param CAN_BankNumber: Select the start slave bank filter from 1..27.\r\n * @retval None\r\n */\r\nvoid CAN_SlaveStartBank(uint8_t CAN_BankNumber) \r\n{\r\n /* Check the parameters */\r\n assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));\r\n \r\n /* Enter Initialisation mode for the filter */\r\n CAN1->FMR |= FMR_FINIT;\r\n \r\n /* Select the start slave bank */\r\n CAN1->FMR &= (uint32_t)0xFFFFC0F1 ;\r\n CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8;\r\n \r\n /* Leave Initialisation mode for the filter */\r\n CAN1->FMR &= ~FMR_FINIT;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the DBG Freeze for CAN.\r\n * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r\n * @param NewState: new state of the CAN peripheral. \r\n * This parameter can be: ENABLE (CAN reception/transmission is frozen\r\n * during debug. Reception FIFOs can still be accessed/controlled normally) \r\n * or DISABLE (CAN is working during debug).\r\n * @retval None\r\n */\r\nvoid CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_CAN_ALL_PERIPH(CANx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Enable Debug Freeze */\r\n CANx->MCR |= MCR_DBF;\r\n }\r\n else\r\n {\r\n /* Disable Debug Freeze */\r\n CANx->MCR &= ~MCR_DBF;\r\n }\r\n}\r\n\r\n\r\n/**\r\n * @brief Enables or disables the CAN Time TriggerOperation communication mode.\r\n * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be \r\n * sent over the CAN bus. \r\n * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r\n * @param NewState: Mode new state. This parameter can be: ENABLE or DISABLE.\r\n * When enabled, Time stamp (TIME[15:0]) value is sent in the last two\r\n * data bytes of the 8-byte message: TIME[7:0] in data byte 6 and TIME[15:8] \r\n * in data byte 7. \r\n * @retval None\r\n */\r\nvoid CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_CAN_ALL_PERIPH(CANx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the TTCM mode */\r\n CANx->MCR |= CAN_MCR_TTCM;\r\n\r\n /* Set TGT bits */\r\n CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT);\r\n CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT);\r\n CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT);\r\n }\r\n else\r\n {\r\n /* Disable the TTCM mode */\r\n CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM);\r\n\r\n /* Reset TGT bits */\r\n CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT);\r\n CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT);\r\n CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT);\r\n }\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n\r\n/** @defgroup CAN_Group2 CAN Frames Transmission functions\r\n * @brief CAN Frames Transmission functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n CAN Frames Transmission functions\r\n =============================================================================== \r\n This section provides functions allowing to \r\n - Initiate and transmit a CAN frame message (if there is an empty mailbox).\r\n - Check the transmission status of a CAN Frame\r\n - Cancel a transmit request\r\n \r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Initiates and transmits a CAN frame message.\r\n * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r\n * @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data.\r\n * @retval The number of the mailbox that is used for transmission or\r\n * CAN_TxStatus_NoMailBox if there is no empty mailbox.\r\n */\r\nuint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)\r\n{\r\n uint8_t transmit_mailbox = 0;\r\n /* Check the parameters */\r\n assert_param(IS_CAN_ALL_PERIPH(CANx));\r\n assert_param(IS_CAN_IDTYPE(TxMessage->IDE));\r\n assert_param(IS_CAN_RTR(TxMessage->RTR));\r\n assert_param(IS_CAN_DLC(TxMessage->DLC));\r\n\r\n /* Select one empty transmit mailbox */\r\n if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)\r\n {\r\n transmit_mailbox = 0;\r\n }\r\n else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)\r\n {\r\n transmit_mailbox = 1;\r\n }\r\n else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)\r\n {\r\n transmit_mailbox = 2;\r\n }\r\n else\r\n {\r\n transmit_mailbox = CAN_TxStatus_NoMailBox;\r\n }\r\n\r\n if (transmit_mailbox != CAN_TxStatus_NoMailBox)\r\n {\r\n /* Set up the Id */\r\n CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ;\r\n if (TxMessage->IDE == CAN_Id_Standard)\r\n {\r\n assert_param(IS_CAN_STDID(TxMessage->StdId)); \r\n CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \\\r\n TxMessage->RTR);\r\n }\r\n else\r\n {\r\n assert_param(IS_CAN_EXTID(TxMessage->ExtId));\r\n CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \\\r\n TxMessage->IDE | \\\r\n TxMessage->RTR);\r\n }\r\n \r\n /* Set up the DLC */\r\n TxMessage->DLC &= (uint8_t)0x0000000F;\r\n CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0;\r\n CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC;\r\n\r\n /* Set up the data field */\r\n CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | \r\n ((uint32_t)TxMessage->Data[2] << 16) |\r\n ((uint32_t)TxMessage->Data[1] << 8) | \r\n ((uint32_t)TxMessage->Data[0]));\r\n CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | \r\n ((uint32_t)TxMessage->Data[6] << 16) |\r\n ((uint32_t)TxMessage->Data[5] << 8) |\r\n ((uint32_t)TxMessage->Data[4]));\r\n /* Request transmission */\r\n CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ;\r\n }\r\n return transmit_mailbox;\r\n}\r\n\r\n/**\r\n * @brief Checks the transmission status of a CAN Frame.\r\n * @param CANx: where x can be 1 or 2 to select the CAN peripheral.\r\n * @param TransmitMailbox: the number of the mailbox that is used for transmission.\r\n * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, \r\n * CAN_TxStatus_Failed in an other case.\r\n */\r\nuint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)\r\n{\r\n uint32_t state = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_CAN_ALL_PERIPH(CANx));\r\n assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));\r\n \r\n switch (TransmitMailbox)\r\n {\r\n case (CAN_TXMAILBOX_0): \r\n state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0);\r\n break;\r\n case (CAN_TXMAILBOX_1): \r\n state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1);\r\n break;\r\n case (CAN_TXMAILBOX_2): \r\n state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2);\r\n break;\r\n default:\r\n state = CAN_TxStatus_Failed;\r\n break;\r\n }\r\n switch (state)\r\n {\r\n /* transmit pending */\r\n case (0x0): state = CAN_TxStatus_Pending;\r\n break;\r\n /* transmit failed */\r\n case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed;\r\n break;\r\n case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed;\r\n break;\r\n case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed;\r\n break;\r\n /* transmit succeeded */\r\n case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok;\r\n break;\r\n case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok;\r\n break;\r\n case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok;\r\n break;\r\n default: state = CAN_TxStatus_Failed;\r\n break;\r\n }\r\n return (uint8_t) state;\r\n}\r\n\r\n/**\r\n * @brief Cancels a transmit request.\r\n * @param CANx: where x can be 1 or 2 to select the CAN peripheral.\r\n * @param Mailbox: Mailbox number.\r\n * @retval None\r\n */\r\nvoid CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_CAN_ALL_PERIPH(CANx));\r\n assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));\r\n /* abort transmission */\r\n switch (Mailbox)\r\n {\r\n case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0;\r\n break;\r\n case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1;\r\n break;\r\n case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2;\r\n break;\r\n default:\r\n break;\r\n }\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n\r\n/** @defgroup CAN_Group3 CAN Frames Reception functions\r\n * @brief CAN Frames Reception functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n CAN Frames Reception functions\r\n =============================================================================== \r\n This section provides functions allowing to \r\n - Receive a correct CAN frame\r\n - Release a specified receive FIFO (2 FIFOs are available)\r\n - Return the number of the pending received CAN frames\r\n \r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Receives a correct CAN frame.\r\n * @param CANx: where x can be 1 or 2 to select the CAN peripheral.\r\n * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.\r\n * @param RxMessage: pointer to a structure receive frame which contains CAN Id,\r\n * CAN DLC, CAN data and FMI number.\r\n * @retval None\r\n */\r\nvoid CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_CAN_ALL_PERIPH(CANx));\r\n assert_param(IS_CAN_FIFO(FIFONumber));\r\n /* Get the Id */\r\n RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR;\r\n if (RxMessage->IDE == CAN_Id_Standard)\r\n {\r\n RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21);\r\n }\r\n else\r\n {\r\n RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3);\r\n }\r\n \r\n RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR;\r\n /* Get the DLC */\r\n RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR;\r\n /* Get the FMI */\r\n RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8);\r\n /* Get the data field */\r\n RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR;\r\n RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8);\r\n RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16);\r\n RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24);\r\n RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR;\r\n RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8);\r\n RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16);\r\n RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24);\r\n /* Release the FIFO */\r\n /* Release FIFO0 */\r\n if (FIFONumber == CAN_FIFO0)\r\n {\r\n CANx->RF0R |= CAN_RF0R_RFOM0;\r\n }\r\n /* Release FIFO1 */\r\n else /* FIFONumber == CAN_FIFO1 */\r\n {\r\n CANx->RF1R |= CAN_RF1R_RFOM1;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Releases the specified receive FIFO.\r\n * @param CANx: where x can be 1 or 2 to select the CAN peripheral.\r\n * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.\r\n * @retval None\r\n */\r\nvoid CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_CAN_ALL_PERIPH(CANx));\r\n assert_param(IS_CAN_FIFO(FIFONumber));\r\n /* Release FIFO0 */\r\n if (FIFONumber == CAN_FIFO0)\r\n {\r\n CANx->RF0R |= CAN_RF0R_RFOM0;\r\n }\r\n /* Release FIFO1 */\r\n else /* FIFONumber == CAN_FIFO1 */\r\n {\r\n CANx->RF1R |= CAN_RF1R_RFOM1;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Returns the number of pending received messages.\r\n * @param CANx: where x can be 1 or 2 to select the CAN peripheral.\r\n * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.\r\n * @retval NbMessage : which is the number of pending message.\r\n */\r\nuint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)\r\n{\r\n uint8_t message_pending=0;\r\n /* Check the parameters */\r\n assert_param(IS_CAN_ALL_PERIPH(CANx));\r\n assert_param(IS_CAN_FIFO(FIFONumber));\r\n if (FIFONumber == CAN_FIFO0)\r\n {\r\n message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03);\r\n }\r\n else if (FIFONumber == CAN_FIFO1)\r\n {\r\n message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03);\r\n }\r\n else\r\n {\r\n message_pending = 0;\r\n }\r\n return message_pending;\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n\r\n/** @defgroup CAN_Group4 CAN Operation modes functions\r\n * @brief CAN Operation modes functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n CAN Operation modes functions\r\n =============================================================================== \r\n This section provides functions allowing to select the CAN Operation modes\r\n - sleep mode\r\n - normal mode \r\n - initialization mode\r\n \r\n@endverbatim\r\n * @{\r\n */\r\n \r\n \r\n/**\r\n * @brief Selects the CAN Operation mode.\r\n * @param CAN_OperatingMode: CAN Operating Mode.\r\n * This parameter can be one of @ref CAN_OperatingMode_TypeDef enumeration.\r\n * @retval status of the requested mode which can be \r\n * - CAN_ModeStatus_Failed: CAN failed entering the specific mode \r\n * - CAN_ModeStatus_Success: CAN Succeed entering the specific mode \r\n */\r\nuint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode)\r\n{\r\n uint8_t status = CAN_ModeStatus_Failed;\r\n \r\n /* Timeout for INAK or also for SLAK bits*/\r\n uint32_t timeout = INAK_TIMEOUT; \r\n\r\n /* Check the parameters */\r\n assert_param(IS_CAN_ALL_PERIPH(CANx));\r\n assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode));\r\n\r\n if (CAN_OperatingMode == CAN_OperatingMode_Initialization)\r\n {\r\n /* Request initialisation */\r\n CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ);\r\n\r\n /* Wait the acknowledge */\r\n while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0))\r\n {\r\n timeout--;\r\n }\r\n if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK)\r\n {\r\n status = CAN_ModeStatus_Failed;\r\n }\r\n else\r\n {\r\n status = CAN_ModeStatus_Success;\r\n }\r\n }\r\n else if (CAN_OperatingMode == CAN_OperatingMode_Normal)\r\n {\r\n /* Request leave initialisation and sleep mode and enter Normal mode */\r\n CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ));\r\n\r\n /* Wait the acknowledge */\r\n while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0))\r\n {\r\n timeout--;\r\n }\r\n if ((CANx->MSR & CAN_MODE_MASK) != 0)\r\n {\r\n status = CAN_ModeStatus_Failed;\r\n }\r\n else\r\n {\r\n status = CAN_ModeStatus_Success;\r\n }\r\n }\r\n else if (CAN_OperatingMode == CAN_OperatingMode_Sleep)\r\n {\r\n /* Request Sleep mode */\r\n CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);\r\n\r\n /* Wait the acknowledge */\r\n while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0))\r\n {\r\n timeout--;\r\n }\r\n if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK)\r\n {\r\n status = CAN_ModeStatus_Failed;\r\n }\r\n else\r\n {\r\n status = CAN_ModeStatus_Success;\r\n }\r\n }\r\n else\r\n {\r\n status = CAN_ModeStatus_Failed;\r\n }\r\n\r\n return (uint8_t) status;\r\n}\r\n\r\n/**\r\n * @brief Enters the Sleep (low power) mode.\r\n * @param CANx: where x can be 1 or 2 to select the CAN peripheral.\r\n * @retval CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed otherwise.\r\n */\r\nuint8_t CAN_Sleep(CAN_TypeDef* CANx)\r\n{\r\n uint8_t sleepstatus = CAN_Sleep_Failed;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_CAN_ALL_PERIPH(CANx));\r\n \r\n /* Request Sleep mode */\r\n CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);\r\n \r\n /* Sleep mode status */\r\n if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)\r\n {\r\n /* Sleep mode not entered */\r\n sleepstatus = CAN_Sleep_Ok;\r\n }\r\n /* return sleep mode status */\r\n return (uint8_t)sleepstatus;\r\n}\r\n\r\n/**\r\n * @brief Wakes up the CAN peripheral from sleep mode .\r\n * @param CANx: where x can be 1 or 2 to select the CAN peripheral.\r\n * @retval CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed otherwise.\r\n */\r\nuint8_t CAN_WakeUp(CAN_TypeDef* CANx)\r\n{\r\n uint32_t wait_slak = SLAK_TIMEOUT;\r\n uint8_t wakeupstatus = CAN_WakeUp_Failed;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_CAN_ALL_PERIPH(CANx));\r\n \r\n /* Wake up request */\r\n CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP;\r\n \r\n /* Sleep mode status */\r\n while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00))\r\n {\r\n wait_slak--;\r\n }\r\n if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)\r\n {\r\n /* wake up done : Sleep mode exited */\r\n wakeupstatus = CAN_WakeUp_Ok;\r\n }\r\n /* return wakeup status */\r\n return (uint8_t)wakeupstatus;\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n\r\n/** @defgroup CAN_Group5 CAN Bus Error management functions\r\n * @brief CAN Bus Error management functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n CAN Bus Error management functions\r\n =============================================================================== \r\n This section provides functions allowing to \r\n - Return the CANx's last error code (LEC)\r\n - Return the CANx Receive Error Counter (REC)\r\n - Return the LSB of the 9-bit CANx Transmit Error Counter(TEC).\r\n \r\n @note If TEC is greater than 255, The CAN is in bus-off state.\r\n @note if REC or TEC are greater than 96, an Error warning flag occurs.\r\n @note if REC or TEC are greater than 127, an Error Passive Flag occurs.\r\n \r\n@endverbatim\r\n * @{\r\n */\r\n \r\n/**\r\n * @brief Returns the CANx's last error code (LEC).\r\n * @param CANx: where x can be 1 or 2 to select the CAN peripheral.\r\n * @retval Error code: \r\n * - CAN_ERRORCODE_NoErr: No Error \r\n * - CAN_ERRORCODE_StuffErr: Stuff Error\r\n * - CAN_ERRORCODE_FormErr: Form Error\r\n * - CAN_ERRORCODE_ACKErr : Acknowledgment Error\r\n * - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error\r\n * - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error\r\n * - CAN_ERRORCODE_CRCErr: CRC Error\r\n * - CAN_ERRORCODE_SoftwareSetErr: Software Set Error \r\n */\r\nuint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx)\r\n{\r\n uint8_t errorcode=0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_CAN_ALL_PERIPH(CANx));\r\n \r\n /* Get the error code*/\r\n errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC);\r\n \r\n /* Return the error code*/\r\n return errorcode;\r\n}\r\n\r\n/**\r\n * @brief Returns the CANx Receive Error Counter (REC).\r\n * @note In case of an error during reception, this counter is incremented \r\n * by 1 or by 8 depending on the error condition as defined by the CAN \r\n * standard. After every successful reception, the counter is \r\n * decremented by 1 or reset to 120 if its value was higher than 128. \r\n * When the counter value exceeds 127, the CAN controller enters the \r\n * error passive state. \r\n * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. \r\n * @retval CAN Receive Error Counter. \r\n */\r\nuint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx)\r\n{\r\n uint8_t counter=0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_CAN_ALL_PERIPH(CANx));\r\n \r\n /* Get the Receive Error Counter*/\r\n counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24);\r\n \r\n /* Return the Receive Error Counter*/\r\n return counter;\r\n}\r\n\r\n\r\n/**\r\n * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).\r\n * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r\n * @retval LSB of the 9-bit CAN Transmit Error Counter. \r\n */\r\nuint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx)\r\n{\r\n uint8_t counter=0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_CAN_ALL_PERIPH(CANx));\r\n \r\n /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */\r\n counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16);\r\n \r\n /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */\r\n return counter;\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup CAN_Group6 Interrupts and flags management functions\r\n * @brief Interrupts and flags management functions\r\n *\r\n@verbatim \r\n ===============================================================================\r\n Interrupts and flags management functions\r\n =============================================================================== \r\n\r\n This section provides functions allowing to configure the CAN Interrupts and \r\n to get the status and clear flags and Interrupts pending bits.\r\n \r\n The CAN provides 14 Interrupts sources and 15 Flags:\r\n\r\n =============== \r\n Flags :\r\n ===============\r\n The 15 flags can be divided on 4 groups: \r\n\r\n A. Transmit Flags\r\n -----------------------\r\n CAN_FLAG_RQCP0, \r\n CAN_FLAG_RQCP1, \r\n CAN_FLAG_RQCP2 : Request completed MailBoxes 0, 1 and 2 Flags\r\n Set when when the last request (transmit or abort) has \r\n been performed. \r\n\r\n B. Receive Flags\r\n -----------------------\r\n\r\n CAN_FLAG_FMP0,\r\n CAN_FLAG_FMP1 : FIFO 0 and 1 Message Pending Flags \r\n set to signal that messages are pending in the receive \r\n FIFO.\r\n These Flags are cleared only by hardware. \r\n\r\n CAN_FLAG_FF0,\r\n CAN_FLAG_FF1 : FIFO 0 and 1 Full Flags\r\n set when three messages are stored in the selected \r\n FIFO. \r\n\r\n CAN_FLAG_FOV0 \r\n CAN_FLAG_FOV1 : FIFO 0 and 1 Overrun Flags\r\n set when a new message has been received and passed \r\n the filter while the FIFO was full. \r\n\r\n C. Operating Mode Flags\r\n ----------------------- \r\n CAN_FLAG_WKU : Wake up Flag\r\n set to signal that a SOF bit has been detected while \r\n the CAN hardware was in Sleep mode. \r\n \r\n CAN_FLAG_SLAK : Sleep acknowledge Flag\r\n Set to signal that the CAN has entered Sleep Mode. \r\n \r\n D. Error Flags\r\n ----------------------- \r\n CAN_FLAG_EWG : Error Warning Flag\r\n Set when the warning limit has been reached (Receive \r\n Error Counter or Transmit Error Counter greater than 96). \r\n This Flag is cleared only by hardware.\r\n \r\n CAN_FLAG_EPV : Error Passive Flag\r\n Set when the Error Passive limit has been reached \r\n (Receive Error Counter or Transmit Error Counter \r\n greater than 127).\r\n This Flag is cleared only by hardware.\r\n \r\n CAN_FLAG_BOF : Bus-Off Flag\r\n set when CAN enters the bus-off state. The bus-off \r\n state is entered on TEC overflow, greater than 255.\r\n This Flag is cleared only by hardware.\r\n \r\n CAN_FLAG_LEC : Last error code Flag\r\n set If a message has been transferred (reception or\r\n transmission) with error, and the error code is hold. \r\n \r\n =============== \r\n Interrupts :\r\n ===============\r\n The 14 interrupts can be divided on 4 groups: \r\n \r\n A. Transmit interrupt\r\n ----------------------- \r\n CAN_IT_TME : Transmit mailbox empty Interrupt\r\n if enabled, this interrupt source is pending when \r\n no transmit request are pending for Tx mailboxes. \r\n\r\n B. Receive Interrupts\r\n ----------------------- \r\n CAN_IT_FMP0,\r\n CAN_IT_FMP1 : FIFO 0 and FIFO1 message pending Interrupts\r\n if enabled, these interrupt sources are pending when \r\n messages are pending in the receive FIFO.\r\n The corresponding interrupt pending bits are cleared \r\n only by hardware.\r\n \r\n CAN_IT_FF0, \r\n CAN_IT_FF1 : FIFO 0 and FIFO1 full Interrupts\r\n if enabled, these interrupt sources are pending when\r\n three messages are stored in the selected FIFO.\r\n \r\n CAN_IT_FOV0, \r\n CAN_IT_FOV1 : FIFO 0 and FIFO1 overrun Interrupts \r\n if enabled, these interrupt sources are pending when\r\n a new message has been received and passed the filter\r\n while the FIFO was full.\r\n\r\n C. Operating Mode Interrupts\r\n ------------------------------- \r\n CAN_IT_WKU : Wake-up Interrupt\r\n if enabled, this interrupt source is pending when \r\n a SOF bit has been detected while the CAN hardware was \r\n in Sleep mode.\r\n \r\n CAN_IT_SLK : Sleep acknowledge Interrupt\r\n if enabled, this interrupt source is pending when \r\n the CAN has entered Sleep Mode. \r\n\r\n D. Error Interrupts \r\n ----------------------- \r\n CAN_IT_EWG : Error warning Interrupt \r\n if enabled, this interrupt source is pending when\r\n the warning limit has been reached (Receive Error \r\n Counter or Transmit Error Counter=96). \r\n \r\n CAN_IT_EPV : Error passive Interrupt \r\n if enabled, this interrupt source is pending when\r\n the Error Passive limit has been reached (Receive \r\n Error Counter or Transmit Error Counter>127).\r\n \r\n CAN_IT_BOF : Bus-off Interrupt\r\n if enabled, this interrupt source is pending when\r\n CAN enters the bus-off state. The bus-off state is \r\n entered on TEC overflow, greater than 255.\r\n This Flag is cleared only by hardware.\r\n \r\n CAN_IT_LEC : Last error code Interrupt \r\n if enabled, this interrupt source is pending when\r\n a message has been transferred (reception or\r\n transmission) with error, and the error code is hold.\r\n \r\n CAN_IT_ERR : Error Interrupt\r\n if enabled, this interrupt source is pending when \r\n an error condition is pending. \r\n \r\n\r\n Managing the CAN controller events :\r\n ------------------------------------ \r\n The user should identify which mode will be used in his application to manage \r\n the CAN controller events: Polling mode or Interrupt mode.\r\n \r\n 1. In the Polling Mode it is advised to use the following functions:\r\n - CAN_GetFlagStatus() : to check if flags events occur. \r\n - CAN_ClearFlag() : to clear the flags events.\r\n \r\n\r\n \r\n 2. In the Interrupt Mode it is advised to use the following functions:\r\n - CAN_ITConfig() : to enable or disable the interrupt source.\r\n - CAN_GetITStatus() : to check if Interrupt occurs.\r\n - CAN_ClearITPendingBit() : to clear the Interrupt pending Bit (corresponding Flag).\r\n @note This function has no impact on CAN_IT_FMP0 and CAN_IT_FMP1 Interrupts \r\n pending bits since there are cleared only by hardware. \r\n \r\n@endverbatim\r\n * @{\r\n */ \r\n/**\r\n * @brief Enables or disables the specified CANx interrupts.\r\n * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r\n * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.\r\n * This parameter can be: \r\n * @arg CAN_IT_TME: Transmit mailbox empty Interrupt \r\n * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt \r\n * @arg CAN_IT_FF0: FIFO 0 full Interrupt\r\n * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt\r\n * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt \r\n * @arg CAN_IT_FF1: FIFO 1 full Interrupt\r\n * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt\r\n * @arg CAN_IT_WKU: Wake-up Interrupt\r\n * @arg CAN_IT_SLK: Sleep acknowledge Interrupt \r\n * @arg CAN_IT_EWG: Error warning Interrupt\r\n * @arg CAN_IT_EPV: Error passive Interrupt\r\n * @arg CAN_IT_BOF: Bus-off Interrupt \r\n * @arg CAN_IT_LEC: Last error code Interrupt\r\n * @arg CAN_IT_ERR: Error Interrupt\r\n * @param NewState: new state of the CAN interrupts.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_CAN_ALL_PERIPH(CANx));\r\n assert_param(IS_CAN_IT(CAN_IT));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected CANx interrupt */\r\n CANx->IER |= CAN_IT;\r\n }\r\n else\r\n {\r\n /* Disable the selected CANx interrupt */\r\n CANx->IER &= ~CAN_IT;\r\n }\r\n}\r\n/**\r\n * @brief Checks whether the specified CAN flag is set or not.\r\n * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r\n * @param CAN_FLAG: specifies the flag to check.\r\n * This parameter can be one of the following values:\r\n * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag\r\n * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag\r\n * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag\r\n * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag \r\n * @arg CAN_FLAG_FF0: FIFO 0 Full Flag \r\n * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag \r\n * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag \r\n * @arg CAN_FLAG_FF1: FIFO 1 Full Flag \r\n * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag \r\n * @arg CAN_FLAG_WKU: Wake up Flag\r\n * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag \r\n * @arg CAN_FLAG_EWG: Error Warning Flag\r\n * @arg CAN_FLAG_EPV: Error Passive Flag \r\n * @arg CAN_FLAG_BOF: Bus-Off Flag \r\n * @arg CAN_FLAG_LEC: Last error code Flag \r\n * @retval The new state of CAN_FLAG (SET or RESET).\r\n */\r\nFlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)\r\n{\r\n FlagStatus bitstatus = RESET;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_CAN_ALL_PERIPH(CANx));\r\n assert_param(IS_CAN_GET_FLAG(CAN_FLAG));\r\n \r\n\r\n if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET)\r\n { \r\n /* Check the status of the specified CAN flag */\r\n if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)\r\n { \r\n /* CAN_FLAG is set */\r\n bitstatus = SET;\r\n }\r\n else\r\n { \r\n /* CAN_FLAG is reset */\r\n bitstatus = RESET;\r\n }\r\n }\r\n else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET)\r\n { \r\n /* Check the status of the specified CAN flag */\r\n if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)\r\n { \r\n /* CAN_FLAG is set */\r\n bitstatus = SET;\r\n }\r\n else\r\n { \r\n /* CAN_FLAG is reset */\r\n bitstatus = RESET;\r\n }\r\n }\r\n else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET)\r\n { \r\n /* Check the status of the specified CAN flag */\r\n if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)\r\n { \r\n /* CAN_FLAG is set */\r\n bitstatus = SET;\r\n }\r\n else\r\n { \r\n /* CAN_FLAG is reset */\r\n bitstatus = RESET;\r\n }\r\n }\r\n else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET)\r\n { \r\n /* Check the status of the specified CAN flag */\r\n if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)\r\n { \r\n /* CAN_FLAG is set */\r\n bitstatus = SET;\r\n }\r\n else\r\n { \r\n /* CAN_FLAG is reset */\r\n bitstatus = RESET;\r\n }\r\n }\r\n else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */\r\n { \r\n /* Check the status of the specified CAN flag */\r\n if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)\r\n { \r\n /* CAN_FLAG is set */\r\n bitstatus = SET;\r\n }\r\n else\r\n { \r\n /* CAN_FLAG is reset */\r\n bitstatus = RESET;\r\n }\r\n }\r\n /* Return the CAN_FLAG status */\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @brief Clears the CAN's pending flags.\r\n * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r\n * @param CAN_FLAG: specifies the flag to clear.\r\n * This parameter can be one of the following values:\r\n * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag\r\n * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag\r\n * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag \r\n * @arg CAN_FLAG_FF0: FIFO 0 Full Flag \r\n * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag \r\n * @arg CAN_FLAG_FF1: FIFO 1 Full Flag \r\n * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag \r\n * @arg CAN_FLAG_WKU: Wake up Flag\r\n * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag \r\n * @arg CAN_FLAG_LEC: Last error code Flag \r\n * @retval None\r\n */\r\nvoid CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)\r\n{\r\n uint32_t flagtmp=0;\r\n /* Check the parameters */\r\n assert_param(IS_CAN_ALL_PERIPH(CANx));\r\n assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG));\r\n \r\n if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */\r\n {\r\n /* Clear the selected CAN flags */\r\n CANx->ESR = (uint32_t)RESET;\r\n }\r\n else /* MSR or TSR or RF0R or RF1R */\r\n {\r\n flagtmp = CAN_FLAG & 0x000FFFFF;\r\n\r\n if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET)\r\n {\r\n /* Receive Flags */\r\n CANx->RF0R = (uint32_t)(flagtmp);\r\n }\r\n else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET)\r\n {\r\n /* Receive Flags */\r\n CANx->RF1R = (uint32_t)(flagtmp);\r\n }\r\n else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET)\r\n {\r\n /* Transmit Flags */\r\n CANx->TSR = (uint32_t)(flagtmp);\r\n }\r\n else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */\r\n {\r\n /* Operating mode Flags */\r\n CANx->MSR = (uint32_t)(flagtmp);\r\n }\r\n }\r\n}\r\n\r\n/**\r\n * @brief Checks whether the specified CANx interrupt has occurred or not.\r\n * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r\n * @param CAN_IT: specifies the CAN interrupt source to check.\r\n * This parameter can be one of the following values:\r\n * @arg CAN_IT_TME: Transmit mailbox empty Interrupt \r\n * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt \r\n * @arg CAN_IT_FF0: FIFO 0 full Interrupt\r\n * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt\r\n * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt \r\n * @arg CAN_IT_FF1: FIFO 1 full Interrupt\r\n * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt\r\n * @arg CAN_IT_WKU: Wake-up Interrupt\r\n * @arg CAN_IT_SLK: Sleep acknowledge Interrupt \r\n * @arg CAN_IT_EWG: Error warning Interrupt\r\n * @arg CAN_IT_EPV: Error passive Interrupt\r\n * @arg CAN_IT_BOF: Bus-off Interrupt \r\n * @arg CAN_IT_LEC: Last error code Interrupt\r\n * @arg CAN_IT_ERR: Error Interrupt\r\n * @retval The current state of CAN_IT (SET or RESET).\r\n */\r\nITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)\r\n{\r\n ITStatus itstatus = RESET;\r\n /* Check the parameters */\r\n assert_param(IS_CAN_ALL_PERIPH(CANx));\r\n assert_param(IS_CAN_IT(CAN_IT));\r\n \r\n /* check the interrupt enable bit */\r\n if((CANx->IER & CAN_IT) != RESET)\r\n {\r\n /* in case the Interrupt is enabled, .... */\r\n switch (CAN_IT)\r\n {\r\n case CAN_IT_TME:\r\n /* Check CAN_TSR_RQCPx bits */\r\n itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2); \r\n break;\r\n case CAN_IT_FMP0:\r\n /* Check CAN_RF0R_FMP0 bit */\r\n itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0); \r\n break;\r\n case CAN_IT_FF0:\r\n /* Check CAN_RF0R_FULL0 bit */\r\n itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0); \r\n break;\r\n case CAN_IT_FOV0:\r\n /* Check CAN_RF0R_FOVR0 bit */\r\n itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0); \r\n break;\r\n case CAN_IT_FMP1:\r\n /* Check CAN_RF1R_FMP1 bit */\r\n itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1); \r\n break;\r\n case CAN_IT_FF1:\r\n /* Check CAN_RF1R_FULL1 bit */\r\n itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1); \r\n break;\r\n case CAN_IT_FOV1:\r\n /* Check CAN_RF1R_FOVR1 bit */\r\n itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1); \r\n break;\r\n case CAN_IT_WKU:\r\n /* Check CAN_MSR_WKUI bit */\r\n itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI); \r\n break;\r\n case CAN_IT_SLK:\r\n /* Check CAN_MSR_SLAKI bit */\r\n itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI); \r\n break;\r\n case CAN_IT_EWG:\r\n /* Check CAN_ESR_EWGF bit */\r\n itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF); \r\n break;\r\n case CAN_IT_EPV:\r\n /* Check CAN_ESR_EPVF bit */\r\n itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF); \r\n break;\r\n case CAN_IT_BOF:\r\n /* Check CAN_ESR_BOFF bit */\r\n itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF); \r\n break;\r\n case CAN_IT_LEC:\r\n /* Check CAN_ESR_LEC bit */\r\n itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC); \r\n break;\r\n case CAN_IT_ERR:\r\n /* Check CAN_MSR_ERRI bit */ \r\n itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI); \r\n break;\r\n default:\r\n /* in case of error, return RESET */\r\n itstatus = RESET;\r\n break;\r\n }\r\n }\r\n else\r\n {\r\n /* in case the Interrupt is not enabled, return RESET */\r\n itstatus = RESET;\r\n }\r\n \r\n /* Return the CAN_IT status */\r\n return itstatus;\r\n}\r\n\r\n/**\r\n * @brief Clears the CANx's interrupt pending bits.\r\n * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r\n * @param CAN_IT: specifies the interrupt pending bit to clear.\r\n * This parameter can be one of the following values:\r\n * @arg CAN_IT_TME: Transmit mailbox empty Interrupt\r\n * @arg CAN_IT_FF0: FIFO 0 full Interrupt\r\n * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt\r\n * @arg CAN_IT_FF1: FIFO 1 full Interrupt\r\n * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt\r\n * @arg CAN_IT_WKU: Wake-up Interrupt\r\n * @arg CAN_IT_SLK: Sleep acknowledge Interrupt \r\n * @arg CAN_IT_EWG: Error warning Interrupt\r\n * @arg CAN_IT_EPV: Error passive Interrupt\r\n * @arg CAN_IT_BOF: Bus-off Interrupt \r\n * @arg CAN_IT_LEC: Last error code Interrupt\r\n * @arg CAN_IT_ERR: Error Interrupt \r\n * @retval None\r\n */\r\nvoid CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_CAN_ALL_PERIPH(CANx));\r\n assert_param(IS_CAN_CLEAR_IT(CAN_IT));\r\n\r\n switch (CAN_IT)\r\n {\r\n case CAN_IT_TME:\r\n /* Clear CAN_TSR_RQCPx (rc_w1)*/\r\n CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2; \r\n break;\r\n case CAN_IT_FF0:\r\n /* Clear CAN_RF0R_FULL0 (rc_w1)*/\r\n CANx->RF0R = CAN_RF0R_FULL0; \r\n break;\r\n case CAN_IT_FOV0:\r\n /* Clear CAN_RF0R_FOVR0 (rc_w1)*/\r\n CANx->RF0R = CAN_RF0R_FOVR0; \r\n break;\r\n case CAN_IT_FF1:\r\n /* Clear CAN_RF1R_FULL1 (rc_w1)*/\r\n CANx->RF1R = CAN_RF1R_FULL1; \r\n break;\r\n case CAN_IT_FOV1:\r\n /* Clear CAN_RF1R_FOVR1 (rc_w1)*/\r\n CANx->RF1R = CAN_RF1R_FOVR1; \r\n break;\r\n case CAN_IT_WKU:\r\n /* Clear CAN_MSR_WKUI (rc_w1)*/\r\n CANx->MSR = CAN_MSR_WKUI; \r\n break;\r\n case CAN_IT_SLK:\r\n /* Clear CAN_MSR_SLAKI (rc_w1)*/ \r\n CANx->MSR = CAN_MSR_SLAKI; \r\n break;\r\n case CAN_IT_EWG:\r\n /* Clear CAN_MSR_ERRI (rc_w1) */\r\n CANx->MSR = CAN_MSR_ERRI;\r\n /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ \r\n break;\r\n case CAN_IT_EPV:\r\n /* Clear CAN_MSR_ERRI (rc_w1) */\r\n CANx->MSR = CAN_MSR_ERRI; \r\n /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/\r\n break;\r\n case CAN_IT_BOF:\r\n /* Clear CAN_MSR_ERRI (rc_w1) */ \r\n CANx->MSR = CAN_MSR_ERRI; \r\n /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/\r\n break;\r\n case CAN_IT_LEC:\r\n /* Clear LEC bits */\r\n CANx->ESR = RESET; \r\n /* Clear CAN_MSR_ERRI (rc_w1) */\r\n CANx->MSR = CAN_MSR_ERRI; \r\n break;\r\n case CAN_IT_ERR:\r\n /*Clear LEC bits */\r\n CANx->ESR = RESET; \r\n /* Clear CAN_MSR_ERRI (rc_w1) */\r\n CANx->MSR = CAN_MSR_ERRI; \r\n /* @note BOFF, EPVF and EWGF Flags are cleared by hardware depending on the CAN Bus status*/\r\n break;\r\n default:\r\n break;\r\n }\r\n}\r\n /**\r\n * @}\r\n */\r\n\r\n/**\r\n * @brief Checks whether the CAN interrupt has occurred or not.\r\n * @param CAN_Reg: specifies the CAN interrupt register to check.\r\n * @param It_Bit: specifies the interrupt source bit to check.\r\n * @retval The new state of the CAN Interrupt (SET or RESET).\r\n */\r\nstatic ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)\r\n{\r\n ITStatus pendingbitstatus = RESET;\r\n \r\n if ((CAN_Reg & It_Bit) != (uint32_t)RESET)\r\n {\r\n /* CAN_IT is set */\r\n pendingbitstatus = SET;\r\n }\r\n else\r\n {\r\n /* CAN_IT is reset */\r\n pendingbitstatus = RESET;\r\n }\r\n return pendingbitstatus;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_crc.c", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_crc.c\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file provides all the CRC firmware functions.\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx_crc.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @defgroup CRC \r\n * @brief CRC driver modules\r\n * @{\r\n */\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup CRC_Private_Functions\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Resets the CRC Data register (DR).\r\n * @param None\r\n * @retval None\r\n */\r\nvoid CRC_ResetDR(void)\r\n{\r\n /* Reset CRC generator */\r\n CRC->CR = CRC_CR_RESET;\r\n}\r\n\r\n/**\r\n * @brief Computes the 32-bit CRC of a given data word(32-bit).\r\n * @param Data: data word(32-bit) to compute its CRC\r\n * @retval 32-bit CRC\r\n */\r\nuint32_t CRC_CalcCRC(uint32_t Data)\r\n{\r\n CRC->DR = Data;\r\n \r\n return (CRC->DR);\r\n}\r\n\r\n/**\r\n * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).\r\n * @param pBuffer: pointer to the buffer containing the data to be computed\r\n * @param BufferLength: length of the buffer to be computed\t\t\t\t\t\r\n * @retval 32-bit CRC\r\n */\r\nuint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)\r\n{\r\n uint32_t index = 0;\r\n \r\n for(index = 0; index < BufferLength; index++)\r\n {\r\n CRC->DR = pBuffer[index];\r\n }\r\n return (CRC->DR);\r\n}\r\n\r\n/**\r\n * @brief Returns the current CRC value.\r\n * @param None\r\n * @retval 32-bit CRC\r\n */\r\nuint32_t CRC_GetCRC(void)\r\n{\r\n return (CRC->DR);\r\n}\r\n\r\n/**\r\n * @brief Stores a 8-bit data in the Independent Data(ID) register.\r\n * @param IDValue: 8-bit value to be stored in the ID register \t\t\t\t\t\r\n * @retval None\r\n */\r\nvoid CRC_SetIDRegister(uint8_t IDValue)\r\n{\r\n CRC->IDR = IDValue;\r\n}\r\n\r\n/**\r\n * @brief Returns the 8-bit data stored in the Independent Data(ID) register\r\n * @param None\r\n * @retval 8-bit value of the ID register \r\n */\r\nuint8_t CRC_GetIDRegister(void)\r\n{\r\n return (CRC->IDR);\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_cryp.c\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file provides firmware functions to manage the following \r\n * functionalities of the Cryptographic processor (CRYP) peripheral: \r\n * - Initialization and Configuration functions\r\n * - Data treatment functions \r\n * - Context swapping functions \r\n * - DMA interface function \r\n * - Interrupts and flags management \r\n *\r\n * @verbatim\r\n * \r\n * =================================================================== \r\n * How to use this driver\r\n * =================================================================== \r\n * 1. Enable the CRYP controller clock using \r\n * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.\r\n *\r\n * 2. Initialise the CRYP using CRYP_Init(), CRYP_KeyInit() and if \r\n * needed CRYP_IVInit(). \r\n *\r\n * 3. Flush the IN and OUT FIFOs by using CRYP_FIFOFlush() function.\r\n *\r\n * 4. Enable the CRYP controller using the CRYP_Cmd() function. \r\n *\r\n * 5. If using DMA for Data input and output transfer, \r\n * Activate the needed DMA Requests using CRYP_DMACmd() function \r\n \r\n * 6. If DMA is not used for data transfer, use CRYP_DataIn() and \r\n * CRYP_DataOut() functions to enter data to IN FIFO and get result\r\n * from OUT FIFO.\r\n *\r\n * 7. To control CRYP events you can use one of the following \r\n * two methods:\r\n * - Check on CRYP flags using the CRYP_GetFlagStatus() function. \r\n * - Use CRYP interrupts through the function CRYP_ITConfig() at \r\n * initialization phase and CRYP_GetITStatus() function into \r\n * interrupt routines in processing phase.\r\n * \r\n * 8. Save and restore Cryptographic processor context using \r\n * CRYP_SaveContext() and CRYP_RestoreContext() functions. \r\n *\r\n *\r\n * =================================================================== \r\n * Procedure to perform an encryption or a decryption\r\n * =================================================================== \r\n *\r\n * Initialization\r\n * =============== \r\n * 1. Initialize the peripheral using CRYP_Init(), CRYP_KeyInit() and \r\n * CRYP_IVInit functions:\r\n * - Configure the key size (128-, 192- or 256-bit, in the AES only) \r\n * - Enter the symmetric key \r\n * - Configure the data type\r\n * - In case of decryption in AES-ECB or AES-CBC, you must prepare \r\n * the key: configure the key preparation mode. Then Enable the CRYP \r\n * peripheral using CRYP_Cmd() function: the BUSY flag is set. \r\n * Wait until BUSY flag is reset : the key is prepared for decryption\r\n * - Configure the algorithm and chaining (the DES/TDES in ECB/CBC, the \r\n * AES in ECB/CBC/CTR) \r\n * - Configure the direction (encryption/decryption).\r\n * - Write the initialization vectors (in CBC or CTR modes only)\r\n *\r\n * 2. Flush the IN and OUT FIFOs using the CRYP_FIFOFlush() function\r\n *\r\n *\r\n * Basic Processing mode (polling mode) \r\n * ==================================== \r\n * 1. Enable the cryptographic processor using CRYP_Cmd() function.\r\n *\r\n * 2. Write the first blocks in the input FIFO (2 to 8 words) using \r\n * CRYP_DataIn() function.\r\n *\r\n * 3. Repeat the following sequence until the complete message has been \r\n * processed:\r\n *\r\n * a) Wait for flag CRYP_FLAG_OFNE occurs (using CRYP_GetFlagStatus() \r\n * function), then read the OUT-FIFO using CRYP_DataOut() function\r\n * (1 block or until the FIFO is empty)\r\n *\r\n * b) Wait for flag CRYP_FLAG_IFNF occurs, (using CRYP_GetFlagStatus() \r\n * function then write the IN FIFO using CRYP_DataIn() function \r\n * (1 block or until the FIFO is full)\r\n *\r\n * 4. At the end of the processing, CRYP_FLAG_BUSY flag will be reset and \r\n * both FIFOs are empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is \r\n * reset). You can disable the peripheral using CRYP_Cmd() function.\r\n *\r\n * Interrupts Processing mode \r\n * ===========================\r\n * In this mode, Processing is done when the data are transferred by the \r\n * CPU during interrupts.\r\n *\r\n * 1. Enable the interrupts CRYP_IT_INI and CRYP_IT_OUTI using \r\n * CRYP_ITConfig() function.\r\n *\r\n * 2. Enable the cryptographic processor using CRYP_Cmd() function.\r\n *\r\n * 3. In the CRYP_IT_INI interrupt handler : load the input message into the \r\n * IN FIFO using CRYP_DataIn() function . You can load 2 or 4 words at a \r\n * time, or load data until the IN FIFO is full. When the last word of\r\n * the message has been entered into the IN FIFO, disable the CRYP_IT_INI \r\n * interrupt (using CRYP_ITConfig() function).\r\n *\r\n * 4. In the CRYP_IT_OUTI interrupt handler : read the output message from \r\n * the OUT FIFO using CRYP_DataOut() function. You can read 1 block (2 or \r\n * 4 words) at a time or read data until the FIFO is empty.\r\n * When the last word has been read, INIM=0, BUSY=0 and both FIFOs are \r\n * empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is reset). \r\n * You can disable the CRYP_IT_OUTI interrupt (using CRYP_ITConfig() \r\n * function) and you can disable the peripheral using CRYP_Cmd() function.\r\n *\r\n * DMA Processing mode \r\n * ====================\r\n * In this mode, Processing is done when the DMA is used to transfer the \r\n * data from/to the memory.\r\n *\r\n * 1. Configure the DMA controller to transfer the input data from the \r\n * memory using DMA_Init() function. \r\n * The transfer length is the length of the message. \r\n * As message padding is not managed by the peripheral, the message \r\n * length must be an entire number of blocks. The data are transferred \r\n * in burst mode. The burst length is 4 words in the AES and 2 or 4 \r\n * words in the DES/TDES. The DMA should be configured to set an \r\n * interrupt on transfer completion of the output data to indicate that \r\n * the processing is finished. \r\n * Refer to DMA peripheral driver for more details. \r\n *\r\n * 2. Enable the cryptographic processor using CRYP_Cmd() function. \r\n * Enable the DMA requests CRYP_DMAReq_DataIN and CRYP_DMAReq_DataOUT \r\n * using CRYP_DMACmd() function.\r\n *\r\n * 3. All the transfers and processing are managed by the DMA and the \r\n * cryptographic processor. The DMA transfer complete interrupt indicates \r\n * that the processing is complete. Both FIFOs are normally empty and \r\n * CRYP_FLAG_BUSY flag is reset.\r\n *\r\n * @endverbatim\r\n *\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx_cryp.h\"\r\n#include \"stm32f4xx_rcc.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @defgroup CRYP \r\n * @brief CRYP driver modules\r\n * @{\r\n */ \r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n#define FLAG_MASK ((uint8_t)0x20)\r\n#define MAX_TIMEOUT ((uint16_t)0xFFFF)\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup CRYP_Private_Functions\r\n * @{\r\n */ \r\n\r\n/** @defgroup CRYP_Group1 Initialization and Configuration functions\r\n * @brief Initialization and Configuration functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Initialization and Configuration functions\r\n =============================================================================== \r\n This section provides functions allowing to \r\n - Initialize the cryptographic Processor using CRYP_Init() function \r\n - Encrypt or Decrypt \r\n - mode : TDES-ECB, TDES-CBC, \r\n DES-ECB, DES-CBC, \r\n AES-ECB, AES-CBC, AES-CTR, AES-Key \r\n - DataType : 32-bit data, 16-bit data, bit data or bit-string\r\n - Key Size (only in AES modes)\r\n - Configure the Encrypt or Decrypt Key using CRYP_KeyInit() function \r\n - Configure the Initialization Vectors(IV) for CBC and CTR modes using \r\n CRYP_IVInit() function. \r\n - Flushes the IN and OUT FIFOs : using CRYP_FIFOFlush() function. \r\n - Enable or disable the CRYP Processor using CRYP_Cmd() function \r\n \r\n \r\n@endverbatim\r\n * @{\r\n */\r\n/**\r\n * @brief Deinitializes the CRYP peripheral registers to their default reset values\r\n * @param None\r\n * @retval None\r\n */\r\nvoid CRYP_DeInit(void)\r\n{\r\n /* Enable CRYP reset state */\r\n RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, ENABLE);\r\n\r\n /* Release CRYP from reset state */\r\n RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, DISABLE);\r\n}\r\n\r\n/**\r\n * @brief Initializes the CRYP peripheral according to the specified parameters\r\n * in the CRYP_InitStruct.\r\n * @param CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure that contains\r\n * the configuration information for the CRYP peripheral.\r\n * @retval None\r\n */\r\nvoid CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_CRYP_ALGOMODE(CRYP_InitStruct->CRYP_AlgoMode));\r\n assert_param(IS_CRYP_DATATYPE(CRYP_InitStruct->CRYP_DataType));\r\n assert_param(IS_CRYP_ALGODIR(CRYP_InitStruct->CRYP_AlgoDir));\r\n\r\n /* Select Algorithm mode*/ \r\n CRYP->CR &= ~CRYP_CR_ALGOMODE;\r\n CRYP->CR |= CRYP_InitStruct->CRYP_AlgoMode;\r\n\r\n /* Select dataType */ \r\n CRYP->CR &= ~CRYP_CR_DATATYPE;\r\n CRYP->CR |= CRYP_InitStruct->CRYP_DataType;\r\n\r\n /* select Key size (used only with AES algorithm) */\r\n if ((CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_ECB) ||\r\n (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_CBC) ||\r\n (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_CTR) ||\r\n (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_Key))\r\n {\r\n assert_param(IS_CRYP_KEYSIZE(CRYP_InitStruct->CRYP_KeySize));\r\n CRYP->CR &= ~CRYP_CR_KEYSIZE;\r\n CRYP->CR |= CRYP_InitStruct->CRYP_KeySize; /* Key size and value must be \r\n configured once the key has \r\n been prepared */\r\n }\r\n\r\n /* Select data Direction */ \r\n CRYP->CR &= ~CRYP_CR_ALGODIR;\r\n CRYP->CR |= CRYP_InitStruct->CRYP_AlgoDir;\r\n}\r\n\r\n/**\r\n * @brief Fills each CRYP_InitStruct member with its default value.\r\n * @param CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure which will\r\n * be initialized.\r\n * @retval None\r\n */\r\nvoid CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct)\r\n{\r\n /* Initialize the CRYP_AlgoDir member */\r\n CRYP_InitStruct->CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;\r\n\r\n /* initialize the CRYP_AlgoMode member */\r\n CRYP_InitStruct->CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB;\r\n\r\n /* initialize the CRYP_DataType member */\r\n CRYP_InitStruct->CRYP_DataType = CRYP_DataType_32b;\r\n \r\n /* Initialize the CRYP_KeySize member */\r\n CRYP_InitStruct->CRYP_KeySize = CRYP_KeySize_128b;\r\n}\r\n\r\n/**\r\n * @brief Initializes the CRYP Keys according to the specified parameters in\r\n * the CRYP_KeyInitStruct.\r\n * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that\r\n * contains the configuration information for the CRYP Keys.\r\n * @retval None\r\n */\r\nvoid CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct)\r\n{\r\n /* Key Initialisation */\r\n CRYP->K0LR = CRYP_KeyInitStruct->CRYP_Key0Left;\r\n CRYP->K0RR = CRYP_KeyInitStruct->CRYP_Key0Right;\r\n CRYP->K1LR = CRYP_KeyInitStruct->CRYP_Key1Left;\r\n CRYP->K1RR = CRYP_KeyInitStruct->CRYP_Key1Right;\r\n CRYP->K2LR = CRYP_KeyInitStruct->CRYP_Key2Left;\r\n CRYP->K2RR = CRYP_KeyInitStruct->CRYP_Key2Right;\r\n CRYP->K3LR = CRYP_KeyInitStruct->CRYP_Key3Left;\r\n CRYP->K3RR = CRYP_KeyInitStruct->CRYP_Key3Right;\r\n}\r\n\r\n/**\r\n * @brief Fills each CRYP_KeyInitStruct member with its default value.\r\n * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure \r\n * which will be initialized.\r\n * @retval None\r\n */\r\nvoid CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct)\r\n{\r\n CRYP_KeyInitStruct->CRYP_Key0Left = 0;\r\n CRYP_KeyInitStruct->CRYP_Key0Right = 0;\r\n CRYP_KeyInitStruct->CRYP_Key1Left = 0;\r\n CRYP_KeyInitStruct->CRYP_Key1Right = 0;\r\n CRYP_KeyInitStruct->CRYP_Key2Left = 0;\r\n CRYP_KeyInitStruct->CRYP_Key2Right = 0;\r\n CRYP_KeyInitStruct->CRYP_Key3Left = 0;\r\n CRYP_KeyInitStruct->CRYP_Key3Right = 0;\r\n}\r\n/**\r\n * @brief Initializes the CRYP Initialization Vectors(IV) according to the\r\n * specified parameters in the CRYP_IVInitStruct.\r\n * @param CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef structure that contains\r\n * the configuration information for the CRYP Initialization Vectors(IV).\r\n * @retval None\r\n */\r\nvoid CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct)\r\n{\r\n CRYP->IV0LR = CRYP_IVInitStruct->CRYP_IV0Left;\r\n CRYP->IV0RR = CRYP_IVInitStruct->CRYP_IV0Right;\r\n CRYP->IV1LR = CRYP_IVInitStruct->CRYP_IV1Left;\r\n CRYP->IV1RR = CRYP_IVInitStruct->CRYP_IV1Right;\r\n}\r\n\r\n/**\r\n * @brief Fills each CRYP_IVInitStruct member with its default value.\r\n * @param CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef Initialization \r\n * Vectors(IV) structure which will be initialized.\r\n * @retval None\r\n */\r\nvoid CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct)\r\n{\r\n CRYP_IVInitStruct->CRYP_IV0Left = 0;\r\n CRYP_IVInitStruct->CRYP_IV0Right = 0;\r\n CRYP_IVInitStruct->CRYP_IV1Left = 0;\r\n CRYP_IVInitStruct->CRYP_IV1Right = 0;\r\n}\r\n\r\n/**\r\n * @brief Flushes the IN and OUT FIFOs (that is read and write pointers of the \r\n * FIFOs are reset)\r\n * @note The FIFOs must be flushed only when BUSY flag is reset. \r\n * @param None\r\n * @retval None\r\n */\r\nvoid CRYP_FIFOFlush(void)\r\n{\r\n /* Reset the read and write pointers of the FIFOs */\r\n CRYP->CR |= CRYP_CR_FFLUSH;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the CRYP peripheral.\r\n * @param NewState: new state of the CRYP peripheral.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid CRYP_Cmd(FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the Cryptographic processor */\r\n CRYP->CR |= CRYP_CR_CRYPEN;\r\n }\r\n else\r\n {\r\n /* Disable the Cryptographic processor */\r\n CRYP->CR &= ~CRYP_CR_CRYPEN;\r\n }\r\n}\r\n/**\r\n * @}\r\n */\r\n \r\n/** @defgroup CRYP_Group2 CRYP Data processing functions\r\n * @brief CRYP Data processing functions\r\n *\r\n@verbatim \r\n ===============================================================================\r\n CRYP Data processing functions\r\n =============================================================================== \r\n This section provides functions allowing the encryption and decryption \r\n operations: \r\n - Enter data to be treated in the IN FIFO : using CRYP_DataIn() function.\r\n - Get the data result from the OUT FIFO : using CRYP_DataOut() function.\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Writes data in the Data Input register (DIN).\r\n * @note After the DIN register has been read once or several times, \r\n * the FIFO must be flushed (using CRYP_FIFOFlush() function). \r\n * @param Data: data to write in Data Input register\r\n * @retval None\r\n */\r\nvoid CRYP_DataIn(uint32_t Data)\r\n{\r\n CRYP->DR = Data;\r\n}\r\n\r\n/**\r\n * @brief Returns the last data entered into the output FIFO.\r\n * @param None\r\n * @retval Last data entered into the output FIFO.\r\n */\r\nuint32_t CRYP_DataOut(void)\r\n{\r\n return CRYP->DOUT;\r\n}\r\n/**\r\n * @}\r\n */\r\n \r\n/** @defgroup CRYP_Group3 Context swapping functions\r\n * @brief Context swapping functions\r\n *\r\n@verbatim \r\n ===============================================================================\r\n Context swapping functions\r\n =============================================================================== \r\n\r\n This section provides functions allowing to save and store CRYP Context\r\n\r\n It is possible to interrupt an encryption/ decryption/ key generation process \r\n to perform another processing with a higher priority, and to complete the \r\n interrupted process later on, when the higher-priority task is complete. To do \r\n so, the context of the interrupted task must be saved from the CRYP registers \r\n to memory, and then be restored from memory to the CRYP registers.\r\n \r\n 1. To save the current context, use CRYP_SaveContext() function\r\n 2. To restore the saved context, use CRYP_RestoreContext() function \r\n\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n \r\n/**\r\n * @brief Saves the CRYP peripheral Context. \r\n * @note This function stops DMA transfer before to save the context. After \r\n * restoring the context, you have to enable the DMA again (if the DMA\r\n * was previously used).\r\n * @param CRYP_ContextSave: pointer to a CRYP_Context structure that contains\r\n * the repository for current context.\r\n * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that \r\n * contains the configuration information for the CRYP Keys. \r\n * @retval None\r\n */\r\nErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave,\r\n CRYP_KeyInitTypeDef* CRYP_KeyInitStruct)\r\n{\r\n __IO uint32_t timeout = 0;\r\n uint32_t ckeckmask = 0, bitstatus; \r\n ErrorStatus status = ERROR;\r\n\r\n /* Stop DMA transfers on the IN FIFO by clearing the DIEN bit in the CRYP_DMACR */\r\n CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DIEN;\r\n \r\n /* Wait until both the IN and OUT FIFOs are empty \r\n (IFEM=1 and OFNE=0 in the CRYP_SR register) and the \r\n BUSY bit is cleared. */\r\n\r\n if ((CRYP->CR & (uint32_t)(CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGOMODE_TDES_CBC)) != (uint32_t)0 )/* TDES */\r\n { \r\n ckeckmask = CRYP_SR_IFEM | CRYP_SR_BUSY ;\r\n }\r\n else /* AES or DES */\r\n {\r\n ckeckmask = CRYP_SR_IFEM | CRYP_SR_BUSY | CRYP_SR_OFNE;\r\n } \r\n \r\n do \r\n {\r\n bitstatus = CRYP->SR & ckeckmask;\r\n timeout++;\r\n }\r\n while ((timeout != MAX_TIMEOUT) && (bitstatus != CRYP_SR_IFEM));\r\n \r\n if ((CRYP->SR & ckeckmask) != CRYP_SR_IFEM)\r\n {\r\n status = ERROR;\r\n }\r\n else\r\n { \r\n /* Stop DMA transfers on the OUT FIFO by \r\n - writing the DOEN bit to 0 in the CRYP_DMACR register \r\n - and clear the CRYPEN bit. */\r\n\r\n CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DOEN;\r\n CRYP->CR &= ~(uint32_t)CRYP_CR_CRYPEN;\r\n\r\n /* Save the current configuration (bits [9:2] in the CRYP_CR register) */\r\n CRYP_ContextSave->CR_bits9to2 = CRYP->CR & (CRYP_CR_KEYSIZE | \r\n CRYP_CR_DATATYPE | \r\n CRYP_CR_ALGOMODE |\r\n CRYP_CR_ALGODIR); \r\n\r\n /* and, if not in ECB mode, the initialization vectors. */\r\n CRYP_ContextSave->CRYP_IV0LR = CRYP->IV0LR;\r\n CRYP_ContextSave->CRYP_IV0RR = CRYP->IV0RR;\r\n CRYP_ContextSave->CRYP_IV1LR = CRYP->IV1LR;\r\n CRYP_ContextSave->CRYP_IV1RR = CRYP->IV1RR;\r\n\r\n /* save The key value */\r\n CRYP_ContextSave->CRYP_K0LR = CRYP_KeyInitStruct->CRYP_Key0Left; \r\n CRYP_ContextSave->CRYP_K0RR = CRYP_KeyInitStruct->CRYP_Key0Right; \r\n CRYP_ContextSave->CRYP_K1LR = CRYP_KeyInitStruct->CRYP_Key1Left; \r\n CRYP_ContextSave->CRYP_K1RR = CRYP_KeyInitStruct->CRYP_Key1Right; \r\n CRYP_ContextSave->CRYP_K2LR = CRYP_KeyInitStruct->CRYP_Key2Left; \r\n CRYP_ContextSave->CRYP_K2RR = CRYP_KeyInitStruct->CRYP_Key2Right; \r\n CRYP_ContextSave->CRYP_K3LR = CRYP_KeyInitStruct->CRYP_Key3Left; \r\n CRYP_ContextSave->CRYP_K3RR = CRYP_KeyInitStruct->CRYP_Key3Right; \r\n\r\n /* When needed, save the DMA status (pointers for IN and OUT messages, \r\n number of remaining bytes, etc.) */\r\n \r\n status = SUCCESS;\r\n }\r\n\r\n return status;\r\n}\r\n\r\n/**\r\n * @brief Restores the CRYP peripheral Context.\r\n * @note Since teh DMA transfer is stopped in CRYP_SaveContext() function,\r\n * after restoring the context, you have to enable the DMA again (if the\r\n * DMA was previously used). \r\n * @param CRYP_ContextRestore: pointer to a CRYP_Context structure that contains\r\n * the repository for saved context.\r\n * @note The data that were saved during context saving must be rewrited into\r\n * the IN FIFO.\r\n * @retval None\r\n */\r\nvoid CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore) \r\n{\r\n\r\n /* Configure the processor with the saved configuration */\r\n CRYP->CR = CRYP_ContextRestore->CR_bits9to2;\r\n\r\n /* restore The key value */\r\n CRYP->K0LR = CRYP_ContextRestore->CRYP_K0LR; \r\n CRYP->K0RR = CRYP_ContextRestore->CRYP_K0RR;\r\n CRYP->K1LR = CRYP_ContextRestore->CRYP_K1LR;\r\n CRYP->K1RR = CRYP_ContextRestore->CRYP_K1RR;\r\n CRYP->K2LR = CRYP_ContextRestore->CRYP_K2LR;\r\n CRYP->K2RR = CRYP_ContextRestore->CRYP_K2RR;\r\n CRYP->K3LR = CRYP_ContextRestore->CRYP_K3LR;\r\n CRYP->K3RR = CRYP_ContextRestore->CRYP_K3RR;\r\n\r\n /* and the initialization vectors. */\r\n CRYP->IV0LR = CRYP_ContextRestore->CRYP_IV0LR;\r\n CRYP->IV0RR = CRYP_ContextRestore->CRYP_IV0RR;\r\n CRYP->IV1LR = CRYP_ContextRestore->CRYP_IV1LR;\r\n CRYP->IV1RR = CRYP_ContextRestore->CRYP_IV1RR;\r\n\r\n /* Enable the cryptographic processor */\r\n CRYP->CR |= CRYP_CR_CRYPEN;\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup CRYP_Group4 CRYP's DMA interface Configuration function\r\n * @brief CRYP's DMA interface Configuration function \r\n *\r\n@verbatim \r\n ===============================================================================\r\n CRYP's DMA interface Configuration function\r\n =============================================================================== \r\n\r\n This section provides functions allowing to configure the DMA interface for \r\n CRYP data input and output transfer.\r\n \r\n When the DMA mode is enabled (using the CRYP_DMACmd() function), data can be \r\n transferred:\r\n - From memory to the CRYP IN FIFO using the DMA peripheral by enabling \r\n the CRYP_DMAReq_DataIN request.\r\n - From the CRYP OUT FIFO to the memory using the DMA peripheral by enabling \r\n the CRYP_DMAReq_DataOUT request.\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Enables or disables the CRYP DMA interface.\r\n * @param CRYP_DMAReq: specifies the CRYP DMA transfer request to be enabled or disabled.\r\n * This parameter can be any combination of the following values:\r\n * @arg CRYP_DMAReq_DataOUT: DMA for outgoing(Tx) data transfer\r\n * @arg CRYP_DMAReq_DataIN: DMA for incoming(Rx) data transfer\r\n * @param NewState: new state of the selected CRYP DMA transfer request.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_CRYP_DMAREQ(CRYP_DMAReq));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected CRYP DMA request */\r\n CRYP->DMACR |= CRYP_DMAReq;\r\n }\r\n else\r\n {\r\n /* Disable the selected CRYP DMA request */\r\n CRYP->DMACR &= (uint8_t)~CRYP_DMAReq;\r\n }\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup CRYP_Group5 Interrupts and flags management functions\r\n * @brief Interrupts and flags management functions\r\n *\r\n@verbatim \r\n ===============================================================================\r\n Interrupts and flags management functions\r\n =============================================================================== \r\n\r\n This section provides functions allowing to configure the CRYP Interrupts and \r\n to get the status and Interrupts pending bits.\r\n\r\n The CRYP provides 2 Interrupts sources and 7 Flags:\r\n\r\n Flags :\r\n ------- \r\n \r\n 1. CRYP_FLAG_IFEM : Set when Input FIFO is empty.\r\n This Flag is cleared only by hardware.\r\n \r\n 2. CRYP_FLAG_IFNF : Set when Input FIFO is not full.\r\n This Flag is cleared only by hardware.\r\n\r\n\r\n 3. CRYP_FLAG_INRIS : Set when Input FIFO Raw interrupt is pending \r\n it gives the raw interrupt state prior to masking \r\n of the input FIFO service interrupt.\r\n This Flag is cleared only by hardware.\r\n \r\n 4. CRYP_FLAG_OFNE : Set when Output FIFO not empty.\r\n This Flag is cleared only by hardware.\r\n \r\n 5. CRYP_FLAG_OFFU : Set when Output FIFO is full.\r\n This Flag is cleared only by hardware.\r\n \r\n 6. CRYP_FLAG_OUTRIS : Set when Output FIFO Raw interrupt is pending \r\n it gives the raw interrupt state prior to masking \r\n of the output FIFO service interrupt.\r\n This Flag is cleared only by hardware.\r\n \r\n 7. CRYP_FLAG_BUSY : Set when the CRYP core is currently processing a \r\n block of data or a key preparation (for AES \r\n decryption).\r\n This Flag is cleared only by hardware.\r\n To clear it, the CRYP core must be disabled and the \r\n last processing has completed. \r\n\r\n Interrupts :\r\n ------------\r\n\r\n 1. CRYP_IT_INI : The input FIFO service interrupt is asserted when there \r\n are less than 4 words in the input FIFO.\r\n This interrupt is associated to CRYP_FLAG_INRIS flag.\r\n\r\n @note This interrupt is cleared by performing write operations \r\n to the input FIFO until it holds 4 or more words. The \r\n input FIFO service interrupt INMIS is enabled with the \r\n CRYP enable bit. Consequently, when CRYP is disabled, the \r\n INMIS signal is low even if the input FIFO is empty.\r\n\r\n\r\n\r\n 2. CRYP_IT_OUTI : The output FIFO service interrupt is asserted when there \r\n is one or more (32-bit word) data items in the output FIFO.\r\n This interrupt is associated to CRYP_FLAG_OUTRIS flag.\r\n\r\n @note This interrupt is cleared by reading data from the output \r\n FIFO until there is no valid (32-bit) word left (that is, \r\n the interrupt follows the state of the OFNE (output FIFO \r\n not empty) flag).\r\n\r\n\r\n Managing the CRYP controller events :\r\n ------------------------------------ \r\n The user should identify which mode will be used in his application to manage \r\n the CRYP controller events: Polling mode or Interrupt mode.\r\n\r\n 1. In the Polling Mode it is advised to use the following functions:\r\n - CRYP_GetFlagStatus() : to check if flags events occur. \r\n\r\n @note The CRYPT flags do not need to be cleared since they are cleared as \r\n soon as the associated event are reset. \r\n\r\n\r\n 2. In the Interrupt Mode it is advised to use the following functions:\r\n - CRYP_ITConfig() : to enable or disable the interrupt source.\r\n - CRYP_GetITStatus() : to check if Interrupt occurs.\r\n\r\n @note The CRYPT interrupts have no pending bits, the interrupt is cleared as \r\n soon as the associated event is reset. \r\n\r\n@endverbatim\r\n * @{\r\n */ \r\n\r\n/**\r\n * @brief Enables or disables the specified CRYP interrupts.\r\n * @param CRYP_IT: specifies the CRYP interrupt source to be enabled or disabled.\r\n * This parameter can be any combination of the following values:\r\n * @arg CRYP_IT_INI: Input FIFO interrupt\r\n * @arg CRYP_IT_OUTI: Output FIFO interrupt\r\n * @param NewState: new state of the specified CRYP interrupt.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_CRYP_CONFIG_IT(CRYP_IT));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected CRYP interrupt */\r\n CRYP->IMSCR |= CRYP_IT;\r\n }\r\n else\r\n {\r\n /* Disable the selected CRYP interrupt */\r\n CRYP->IMSCR &= (uint8_t)~CRYP_IT;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Checks whether the specified CRYP interrupt has occurred or not.\r\n * @note This function checks the status of the masked interrupt (i.e the \r\n * interrupt should be previously enabled). \r\n * @param CRYP_IT: specifies the CRYP (masked) interrupt source to check.\r\n * This parameter can be one of the following values:\r\n * @arg CRYP_IT_INI: Input FIFO interrupt\r\n * @arg CRYP_IT_OUTI: Output FIFO interrupt\r\n * @retval The new state of CRYP_IT (SET or RESET).\r\n */\r\nITStatus CRYP_GetITStatus(uint8_t CRYP_IT)\r\n{\r\n ITStatus bitstatus = RESET;\r\n /* Check the parameters */\r\n assert_param(IS_CRYP_GET_IT(CRYP_IT));\r\n\r\n /* Check the status of the specified CRYP interrupt */\r\n if ((CRYP->MISR & CRYP_IT) != (uint8_t)RESET)\r\n {\r\n /* CRYP_IT is set */\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n /* CRYP_IT is reset */\r\n bitstatus = RESET;\r\n }\r\n /* Return the CRYP_IT status */\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @brief Checks whether the specified CRYP flag is set or not.\r\n * @param CRYP_FLAG: specifies the CRYP flag to check.\r\n * This parameter can be one of the following values:\r\n * @arg CRYP_FLAG_IFEM: Input FIFO Empty flag.\r\n * @arg CRYP_FLAG_IFNF: Input FIFO Not Full flag.\r\n * @arg CRYP_FLAG_OFNE: Output FIFO Not Empty flag.\r\n * @arg CRYP_FLAG_OFFU: Output FIFO Full flag.\r\n * @arg CRYP_FLAG_BUSY: Busy flag.\r\n * @arg CRYP_FLAG_OUTRIS: Output FIFO raw interrupt flag.\r\n * @arg CRYP_FLAG_INRIS: Input FIFO raw interrupt flag.\r\n * @retval The new state of CRYP_FLAG (SET or RESET).\r\n */\r\nFlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG)\r\n{\r\n FlagStatus bitstatus = RESET;\r\n uint32_t tempreg = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_CRYP_GET_FLAG(CRYP_FLAG));\r\n\r\n /* check if the FLAG is in RISR register */\r\n if ((CRYP_FLAG & FLAG_MASK) != 0x00) \r\n {\r\n tempreg = CRYP->RISR;\r\n }\r\n else /* The FLAG is in SR register */\r\n {\r\n tempreg = CRYP->SR;\r\n }\r\n\r\n\r\n /* Check the status of the specified CRYP flag */\r\n if ((tempreg & CRYP_FLAG ) != (uint8_t)RESET)\r\n {\r\n /* CRYP_FLAG is set */\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n /* CRYP_FLAG is reset */\r\n bitstatus = RESET;\r\n }\r\n\r\n /* Return the CRYP_FLAG status */\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_cryp_aes.c\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file provides high level functions to encrypt and decrypt an \r\n * input message using AES in ECB/CBC/CTR modes.\r\n * It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP\r\n * peripheral.\r\n *\r\n * @verbatim\r\n *\r\n * ===================================================================\r\n * How to use this driver\r\n * ===================================================================\r\n * 1. Enable The CRYP controller clock using \r\n * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.\r\n *\r\n * 2. Encrypt and decrypt using AES in ECB Mode using CRYP_AES_ECB()\r\n * function.\r\n *\r\n * 3. Encrypt and decrypt using AES in CBC Mode using CRYP_AES_CBC()\r\n * function.\r\n *\r\n * 4. Encrypt and decrypt using AES in CTR Mode using CRYP_AES_CTR()\r\n * function.\r\n *\r\n * @endverbatim\r\n *\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx_cryp.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @defgroup CRYP \r\n * @brief CRYP driver modules\r\n * @{\r\n */\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n#define AESBUSY_TIMEOUT ((uint32_t) 0x00010000)\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup CRYP_Private_Functions\r\n * @{\r\n */ \r\n\r\n/** @defgroup CRYP_Group6 High Level AES functions\r\n * @brief High Level AES functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n High Level AES functions\r\n ===============================================================================\r\n\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Encrypt and decrypt using AES in ECB Mode\r\n * @param Mode: encryption or decryption Mode.\r\n * This parameter can be one of the following values:\r\n * @arg MODE_ENCRYPT: Encryption\r\n * @arg MODE_DECRYPT: Decryption\r\n * @param Key: Key used for AES algorithm.\r\n * @param Keysize: length of the Key, must be a 128, 192 or 256.\r\n * @param Input: pointer to the Input buffer.\r\n * @param Ilength: length of the Input buffer, must be a multiple of 16.\r\n * @param Output: pointer to the returned buffer.\r\n * @retval An ErrorStatus enumeration value:\r\n * - SUCCESS: Operation done\r\n * - ERROR: Operation failed\r\n */\r\nErrorStatus CRYP_AES_ECB(uint8_t Mode, uint8_t* Key, uint16_t Keysize,\r\n uint8_t* Input, uint32_t Ilength, uint8_t* Output)\r\n{\r\n CRYP_InitTypeDef AES_CRYP_InitStructure;\r\n CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure;\r\n __IO uint32_t counter = 0;\r\n uint32_t busystatus = 0;\r\n ErrorStatus status = SUCCESS;\r\n uint32_t keyaddr = (uint32_t)Key;\r\n uint32_t inputaddr = (uint32_t)Input;\r\n uint32_t outputaddr = (uint32_t)Output;\r\n uint32_t i = 0;\r\n\r\n /* Crypto structures initialisation*/\r\n CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure);\r\n\r\n switch(Keysize)\r\n {\r\n case 128:\r\n AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b;\r\n AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));\r\n keyaddr+=4;\r\n AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));\r\n keyaddr+=4;\r\n AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));\r\n keyaddr+=4;\r\n AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));\r\n break;\r\n case 192:\r\n AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b;\r\n AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));\r\n keyaddr+=4;\r\n AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));\r\n keyaddr+=4;\r\n AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));\r\n keyaddr+=4;\r\n AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));\r\n keyaddr+=4;\r\n AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));\r\n keyaddr+=4;\r\n AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));\r\n break;\r\n case 256:\r\n AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b;\r\n AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr));\r\n keyaddr+=4;\r\n AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr));\r\n keyaddr+=4;\r\n AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));\r\n keyaddr+=4;\r\n AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));\r\n keyaddr+=4;\r\n AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));\r\n keyaddr+=4;\r\n AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));\r\n keyaddr+=4;\r\n AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));\r\n keyaddr+=4;\r\n AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));\r\n break;\r\n default:\r\n break;\r\n }\r\n\r\n /*------------------ AES Decryption ------------------*/\r\n if(Mode == MODE_DECRYPT) /* AES decryption */\r\n {\r\n /* Flush IN/OUT FIFOs */\r\n CRYP_FIFOFlush();\r\n\r\n /* Crypto Init for Key preparation for decryption process */\r\n AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;\r\n AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_Key;\r\n AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_32b;\r\n CRYP_Init(&AES_CRYP_InitStructure);\r\n\r\n /* Key Initialisation */\r\n CRYP_KeyInit(&AES_CRYP_KeyInitStructure);\r\n\r\n /* Enable Crypto processor */\r\n CRYP_Cmd(ENABLE);\r\n\r\n /* wait until the Busy flag is RESET */\r\n do\r\n {\r\n busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);\r\n counter++;\r\n }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));\r\n\r\n if (busystatus != RESET)\r\n {\r\n status = ERROR;\r\n }\r\n else\r\n {\r\n /* Crypto Init for decryption process */ \r\n AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;\r\n }\r\n }\r\n /*------------------ AES Encryption ------------------*/\r\n else /* AES encryption */\r\n {\r\n\r\n CRYP_KeyInit(&AES_CRYP_KeyInitStructure);\r\n\r\n /* Crypto Init for Encryption process */\r\n AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;\r\n }\r\n\r\n AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_ECB;\r\n AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;\r\n CRYP_Init(&AES_CRYP_InitStructure);\r\n\r\n /* Flush IN/OUT FIFOs */\r\n CRYP_FIFOFlush();\r\n\r\n /* Enable Crypto processor */\r\n CRYP_Cmd(ENABLE);\r\n\r\n for(i=0; ((i
© COPYRIGHT 2012 STMicroelectronics
\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx_cryp.h\"\r\n\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @defgroup CRYP \r\n * @brief CRYP driver modules\r\n * @{\r\n */\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n#define DESBUSY_TIMEOUT ((uint32_t) 0x00010000)\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n\r\n/** @defgroup CRYP_Private_Functions\r\n * @{\r\n */ \r\n\r\n/** @defgroup CRYP_Group8 High Level DES functions\r\n * @brief High Level DES functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n High Level DES functions\r\n ===============================================================================\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Encrypt and decrypt using DES in ECB Mode\r\n * @param Mode: encryption or decryption Mode.\r\n * This parameter can be one of the following values:\r\n * @arg MODE_ENCRYPT: Encryption\r\n * @arg MODE_DECRYPT: Decryption\r\n * @param Key: Key used for DES algorithm.\r\n * @param Ilength: length of the Input buffer, must be a multiple of 8.\r\n * @param Input: pointer to the Input buffer.\r\n * @param Output: pointer to the returned buffer.\r\n * @retval An ErrorStatus enumeration value:\r\n * - SUCCESS: Operation done\r\n * - ERROR: Operation failed\r\n */\r\nErrorStatus CRYP_DES_ECB(uint8_t Mode, uint8_t Key[8], uint8_t *Input, \r\n uint32_t Ilength, uint8_t *Output)\r\n{\r\n CRYP_InitTypeDef DES_CRYP_InitStructure;\r\n CRYP_KeyInitTypeDef DES_CRYP_KeyInitStructure;\r\n __IO uint32_t counter = 0;\r\n uint32_t busystatus = 0;\r\n ErrorStatus status = SUCCESS;\r\n uint32_t keyaddr = (uint32_t)Key;\r\n uint32_t inputaddr = (uint32_t)Input;\r\n uint32_t outputaddr = (uint32_t)Output;\r\n uint32_t i = 0;\r\n\r\n /* Crypto structures initialisation*/\r\n CRYP_KeyStructInit(&DES_CRYP_KeyInitStructure);\r\n\r\n /* Crypto Init for Encryption process */\r\n if( Mode == MODE_ENCRYPT ) /* DES encryption */\r\n {\r\n DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;\r\n }\r\n else/* if( Mode == MODE_DECRYPT )*/ /* DES decryption */\r\n { \r\n DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;\r\n }\r\n\r\n DES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_DES_ECB;\r\n DES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;\r\n CRYP_Init(&DES_CRYP_InitStructure);\r\n\r\n /* Key Initialisation */\r\n DES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));\r\n keyaddr+=4;\r\n DES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));\r\n CRYP_KeyInit(& DES_CRYP_KeyInitStructure);\r\n\r\n /* Flush IN/OUT FIFO */\r\n CRYP_FIFOFlush();\r\n\r\n /* Enable Crypto processor */\r\n CRYP_Cmd(ENABLE);\r\n\r\n for(i=0; ((i
© COPYRIGHT 2012 STMicroelectronics
\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx_cryp.h\"\r\n\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @defgroup CRYP \r\n * @brief CRYP driver modules\r\n * @{\r\n */\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n#define TDESBUSY_TIMEOUT ((uint32_t) 0x00010000)\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n\r\n/** @defgroup CRYP_Private_Functions\r\n * @{\r\n */ \r\n\r\n/** @defgroup CRYP_Group7 High Level TDES functions\r\n * @brief High Level TDES functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n High Level TDES functions\r\n ===============================================================================\r\n\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Encrypt and decrypt using TDES in ECB Mode\r\n * @param Mode: encryption or decryption Mode.\r\n * This parameter can be one of the following values:\r\n * @arg MODE_ENCRYPT: Encryption\r\n * @arg MODE_DECRYPT: Decryption\r\n * @param Key: Key used for TDES algorithm.\r\n * @param Ilength: length of the Input buffer, must be a multiple of 8.\r\n * @param Input: pointer to the Input buffer.\r\n * @param Output: pointer to the returned buffer.\r\n * @retval An ErrorStatus enumeration value:\r\n * - SUCCESS: Operation done\r\n * - ERROR: Operation failed\r\n */\r\nErrorStatus CRYP_TDES_ECB(uint8_t Mode, uint8_t Key[24], uint8_t *Input, \r\n uint32_t Ilength, uint8_t *Output)\r\n{\r\n CRYP_InitTypeDef TDES_CRYP_InitStructure;\r\n CRYP_KeyInitTypeDef TDES_CRYP_KeyInitStructure;\r\n __IO uint32_t counter = 0;\r\n uint32_t busystatus = 0;\r\n ErrorStatus status = SUCCESS;\r\n uint32_t keyaddr = (uint32_t)Key;\r\n uint32_t inputaddr = (uint32_t)Input;\r\n uint32_t outputaddr = (uint32_t)Output;\r\n uint32_t i = 0;\r\n\r\n /* Crypto structures initialisation*/\r\n CRYP_KeyStructInit(&TDES_CRYP_KeyInitStructure);\r\n\r\n /* Crypto Init for Encryption process */\r\n if(Mode == MODE_ENCRYPT) /* TDES encryption */\r\n {\r\n TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;\r\n }\r\n else /*if(Mode == MODE_DECRYPT)*/ /* TDES decryption */\r\n {\r\n TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;\r\n }\r\n\r\n TDES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB;\r\n TDES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;\r\n CRYP_Init(&TDES_CRYP_InitStructure);\r\n\r\n /* Key Initialisation */\r\n TDES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));\r\n keyaddr+=4;\r\n TDES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));\r\n keyaddr+=4;\r\n TDES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));\r\n keyaddr+=4;\r\n TDES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));\r\n keyaddr+=4;\r\n TDES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));\r\n keyaddr+=4;\r\n TDES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));\r\n CRYP_KeyInit(& TDES_CRYP_KeyInitStructure);\r\n\r\n /* Flush IN/OUT FIFO */\r\n CRYP_FIFOFlush();\r\n\r\n /* Enable Crypto processor */\r\n CRYP_Cmd(ENABLE);\r\n\r\n for(i=0; ((i
© COPYRIGHT 2012 STMicroelectronics
\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */ \r\n\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx_dac.h\"\r\n#include \"stm32f4xx_rcc.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @defgroup DAC \r\n * @brief DAC driver modules\r\n * @{\r\n */ \r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n\r\n/* CR register Mask */\r\n#define CR_CLEAR_MASK ((uint32_t)0x00000FFE)\r\n\r\n/* DAC Dual Channels SWTRIG masks */\r\n#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)\r\n#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)\r\n\r\n/* DHR registers offsets */\r\n#define DHR12R1_OFFSET ((uint32_t)0x00000008)\r\n#define DHR12R2_OFFSET ((uint32_t)0x00000014)\r\n#define DHR12RD_OFFSET ((uint32_t)0x00000020)\r\n\r\n/* DOR register offset */\r\n#define DOR_OFFSET ((uint32_t)0x0000002C)\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup DAC_Private_Functions\r\n * @{\r\n */\r\n\r\n/** @defgroup DAC_Group1 DAC channels configuration\r\n * @brief DAC channels configuration: trigger, output buffer, data format \r\n *\r\n@verbatim \r\n ===============================================================================\r\n DAC channels configuration: trigger, output buffer, data format\r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Deinitializes the DAC peripheral registers to their default reset values.\r\n * @param None\r\n * @retval None\r\n */\r\nvoid DAC_DeInit(void)\r\n{\r\n /* Enable DAC reset state */\r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);\r\n /* Release DAC from reset state */\r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);\r\n}\r\n\r\n/**\r\n * @brief Initializes the DAC peripheral according to the specified parameters\r\n * in the DAC_InitStruct.\r\n * @param DAC_Channel: the selected DAC channel. \r\n * This parameter can be one of the following values:\r\n * @arg DAC_Channel_1: DAC Channel1 selected\r\n * @arg DAC_Channel_2: DAC Channel2 selected\r\n * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains\r\n * the configuration information for the specified DAC channel.\r\n * @retval None\r\n */\r\nvoid DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)\r\n{\r\n uint32_t tmpreg1 = 0, tmpreg2 = 0;\r\n\r\n /* Check the DAC parameters */\r\n assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));\r\n assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));\r\n assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));\r\n assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));\r\n\r\n/*---------------------------- DAC CR Configuration --------------------------*/\r\n /* Get the DAC CR value */\r\n tmpreg1 = DAC->CR;\r\n /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */\r\n tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);\r\n /* Configure for the selected DAC channel: buffer output, trigger, \r\n wave generation, mask/amplitude for wave generation */\r\n /* Set TSELx and TENx bits according to DAC_Trigger value */\r\n /* Set WAVEx bits according to DAC_WaveGeneration value */\r\n /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ \r\n /* Set BOFFx bit according to DAC_OutputBuffer value */ \r\n tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |\r\n DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | \\\r\n DAC_InitStruct->DAC_OutputBuffer);\r\n /* Calculate CR register value depending on DAC_Channel */\r\n tmpreg1 |= tmpreg2 << DAC_Channel;\r\n /* Write to DAC CR */\r\n DAC->CR = tmpreg1;\r\n}\r\n\r\n/**\r\n * @brief Fills each DAC_InitStruct member with its default value.\r\n * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will \r\n * be initialized.\r\n * @retval None\r\n */\r\nvoid DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)\r\n{\r\n/*--------------- Reset DAC init structure parameters values -----------------*/\r\n /* Initialize the DAC_Trigger member */\r\n DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;\r\n /* Initialize the DAC_WaveGeneration member */\r\n DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;\r\n /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */\r\n DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;\r\n /* Initialize the DAC_OutputBuffer member */\r\n DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the specified DAC channel.\r\n * @param DAC_Channel: The selected DAC channel. \r\n * This parameter can be one of the following values:\r\n * @arg DAC_Channel_1: DAC Channel1 selected\r\n * @arg DAC_Channel_2: DAC Channel2 selected\r\n * @param NewState: new state of the DAC channel. \r\n * This parameter can be: ENABLE or DISABLE.\r\n * @note When the DAC channel is enabled the trigger source can no more be modified.\r\n * @retval None\r\n */\r\nvoid DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_DAC_CHANNEL(DAC_Channel));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected DAC channel */\r\n DAC->CR |= (DAC_CR_EN1 << DAC_Channel);\r\n }\r\n else\r\n {\r\n /* Disable the selected DAC channel */\r\n DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel));\r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the selected DAC channel software trigger.\r\n * @param DAC_Channel: The selected DAC channel. \r\n * This parameter can be one of the following values:\r\n * @arg DAC_Channel_1: DAC Channel1 selected\r\n * @arg DAC_Channel_2: DAC Channel2 selected\r\n * @param NewState: new state of the selected DAC channel software trigger.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_DAC_CHANNEL(DAC_Channel));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable software trigger for the selected DAC channel */\r\n DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);\r\n }\r\n else\r\n {\r\n /* Disable software trigger for the selected DAC channel */\r\n DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));\r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables or disables simultaneously the two DAC channels software triggers.\r\n * @param NewState: new state of the DAC channels software triggers.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid DAC_DualSoftwareTriggerCmd(FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable software trigger for both DAC channels */\r\n DAC->SWTRIGR |= DUAL_SWTRIG_SET;\r\n }\r\n else\r\n {\r\n /* Disable software trigger for both DAC channels */\r\n DAC->SWTRIGR &= DUAL_SWTRIG_RESET;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the selected DAC channel wave generation.\r\n * @param DAC_Channel: The selected DAC channel. \r\n * This parameter can be one of the following values:\r\n * @arg DAC_Channel_1: DAC Channel1 selected\r\n * @arg DAC_Channel_2: DAC Channel2 selected\r\n * @param DAC_Wave: specifies the wave type to enable or disable.\r\n * This parameter can be one of the following values:\r\n * @arg DAC_Wave_Noise: noise wave generation\r\n * @arg DAC_Wave_Triangle: triangle wave generation\r\n * @param NewState: new state of the selected DAC channel wave generation.\r\n * This parameter can be: ENABLE or DISABLE. \r\n * @retval None\r\n */\r\nvoid DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_DAC_CHANNEL(DAC_Channel));\r\n assert_param(IS_DAC_WAVE(DAC_Wave)); \r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected wave generation for the selected DAC channel */\r\n DAC->CR |= DAC_Wave << DAC_Channel;\r\n }\r\n else\r\n {\r\n /* Disable the selected wave generation for the selected DAC channel */\r\n DAC->CR &= ~(DAC_Wave << DAC_Channel);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Set the specified data holding register value for DAC channel1.\r\n * @param DAC_Align: Specifies the data alignment for DAC channel1.\r\n * This parameter can be one of the following values:\r\n * @arg DAC_Align_8b_R: 8bit right data alignment selected\r\n * @arg DAC_Align_12b_L: 12bit left data alignment selected\r\n * @arg DAC_Align_12b_R: 12bit right data alignment selected\r\n * @param Data: Data to be loaded in the selected data holding register.\r\n * @retval None\r\n */\r\nvoid DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)\r\n{ \r\n __IO uint32_t tmp = 0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_DAC_ALIGN(DAC_Align));\r\n assert_param(IS_DAC_DATA(Data));\r\n \r\n tmp = (uint32_t)DAC_BASE; \r\n tmp += DHR12R1_OFFSET + DAC_Align;\r\n\r\n /* Set the DAC channel1 selected data holding register */\r\n *(__IO uint32_t *) tmp = Data;\r\n}\r\n\r\n/**\r\n * @brief Set the specified data holding register value for DAC channel2.\r\n * @param DAC_Align: Specifies the data alignment for DAC channel2.\r\n * This parameter can be one of the following values:\r\n * @arg DAC_Align_8b_R: 8bit right data alignment selected\r\n * @arg DAC_Align_12b_L: 12bit left data alignment selected\r\n * @arg DAC_Align_12b_R: 12bit right data alignment selected\r\n * @param Data: Data to be loaded in the selected data holding register.\r\n * @retval None\r\n */\r\nvoid DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)\r\n{\r\n __IO uint32_t tmp = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_DAC_ALIGN(DAC_Align));\r\n assert_param(IS_DAC_DATA(Data));\r\n \r\n tmp = (uint32_t)DAC_BASE;\r\n tmp += DHR12R2_OFFSET + DAC_Align;\r\n\r\n /* Set the DAC channel2 selected data holding register */\r\n *(__IO uint32_t *)tmp = Data;\r\n}\r\n\r\n/**\r\n * @brief Set the specified data holding register value for dual channel DAC.\r\n * @param DAC_Align: Specifies the data alignment for dual channel DAC.\r\n * This parameter can be one of the following values:\r\n * @arg DAC_Align_8b_R: 8bit right data alignment selected\r\n * @arg DAC_Align_12b_L: 12bit left data alignment selected\r\n * @arg DAC_Align_12b_R: 12bit right data alignment selected\r\n * @param Data2: Data for DAC Channel2 to be loaded in the selected data holding register.\r\n * @param Data1: Data for DAC Channel1 to be loaded in the selected data holding register.\r\n * @note In dual mode, a unique register access is required to write in both\r\n * DAC channels at the same time.\r\n * @retval None\r\n */\r\nvoid DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)\r\n{\r\n uint32_t data = 0, tmp = 0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_DAC_ALIGN(DAC_Align));\r\n assert_param(IS_DAC_DATA(Data1));\r\n assert_param(IS_DAC_DATA(Data2));\r\n \r\n /* Calculate and set dual DAC data holding register value */\r\n if (DAC_Align == DAC_Align_8b_R)\r\n {\r\n data = ((uint32_t)Data2 << 8) | Data1; \r\n }\r\n else\r\n {\r\n data = ((uint32_t)Data2 << 16) | Data1;\r\n }\r\n \r\n tmp = (uint32_t)DAC_BASE;\r\n tmp += DHR12RD_OFFSET + DAC_Align;\r\n\r\n /* Set the dual DAC selected data holding register */\r\n *(__IO uint32_t *)tmp = data;\r\n}\r\n\r\n/**\r\n * @brief Returns the last data output value of the selected DAC channel.\r\n * @param DAC_Channel: The selected DAC channel. \r\n * This parameter can be one of the following values:\r\n * @arg DAC_Channel_1: DAC Channel1 selected\r\n * @arg DAC_Channel_2: DAC Channel2 selected\r\n * @retval The selected DAC channel data output value.\r\n */\r\nuint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)\r\n{\r\n __IO uint32_t tmp = 0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_DAC_CHANNEL(DAC_Channel));\r\n \r\n tmp = (uint32_t) DAC_BASE ;\r\n tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);\r\n \r\n /* Returns the DAC channel data output register value */\r\n return (uint16_t) (*(__IO uint32_t*) tmp);\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup DAC_Group2 DMA management functions\r\n * @brief DMA management functions\r\n *\r\n@verbatim \r\n ===============================================================================\r\n DMA management functions\r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Enables or disables the specified DAC channel DMA request.\r\n * @note When enabled DMA1 is generated when an external trigger (EXTI Line9,\r\n * TIM2, TIM4, TIM5, TIM6, TIM7 or TIM8 but not a software trigger) occurs.\r\n * @param DAC_Channel: The selected DAC channel. \r\n * This parameter can be one of the following values:\r\n * @arg DAC_Channel_1: DAC Channel1 selected\r\n * @arg DAC_Channel_2: DAC Channel2 selected\r\n * @param NewState: new state of the selected DAC channel DMA request.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @note The DAC channel1 is mapped on DMA1 Stream 5 channel7 which must be\r\n * already configured.\r\n * @note The DAC channel2 is mapped on DMA1 Stream 6 channel7 which must be\r\n * already configured. \r\n * @retval None\r\n */\r\nvoid DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_DAC_CHANNEL(DAC_Channel));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected DAC channel DMA request */\r\n DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);\r\n }\r\n else\r\n {\r\n /* Disable the selected DAC channel DMA request */\r\n DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));\r\n }\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup DAC_Group3 Interrupts and flags management functions\r\n * @brief Interrupts and flags management functions\r\n *\r\n@verbatim \r\n ===============================================================================\r\n Interrupts and flags management functions\r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Enables or disables the specified DAC interrupts.\r\n * @param DAC_Channel: The selected DAC channel. \r\n * This parameter can be one of the following values:\r\n * @arg DAC_Channel_1: DAC Channel1 selected\r\n * @arg DAC_Channel_2: DAC Channel2 selected\r\n * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. \r\n * This parameter can be the following values:\r\n * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask\r\n * @note The DMA underrun occurs when a second external trigger arrives before the \r\n * acknowledgement for the first external trigger is received (first request).\r\n * @param NewState: new state of the specified DAC interrupts.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */ \r\nvoid DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) \r\n{\r\n /* Check the parameters */\r\n assert_param(IS_DAC_CHANNEL(DAC_Channel));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n assert_param(IS_DAC_IT(DAC_IT)); \r\n\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected DAC interrupts */\r\n DAC->CR |= (DAC_IT << DAC_Channel);\r\n }\r\n else\r\n {\r\n /* Disable the selected DAC interrupts */\r\n DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));\r\n }\r\n}\r\n\r\n/**\r\n * @brief Checks whether the specified DAC flag is set or not.\r\n * @param DAC_Channel: The selected DAC channel. \r\n * This parameter can be one of the following values:\r\n * @arg DAC_Channel_1: DAC Channel1 selected\r\n * @arg DAC_Channel_2: DAC Channel2 selected\r\n * @param DAC_FLAG: specifies the flag to check. \r\n * This parameter can be only of the following value:\r\n * @arg DAC_FLAG_DMAUDR: DMA underrun flag\r\n * @note The DMA underrun occurs when a second external trigger arrives before the \r\n * acknowledgement for the first external trigger is received (first request).\r\n * @retval The new state of DAC_FLAG (SET or RESET).\r\n */\r\nFlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)\r\n{\r\n FlagStatus bitstatus = RESET;\r\n /* Check the parameters */\r\n assert_param(IS_DAC_CHANNEL(DAC_Channel));\r\n assert_param(IS_DAC_FLAG(DAC_FLAG));\r\n\r\n /* Check the status of the specified DAC flag */\r\n if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)\r\n {\r\n /* DAC_FLAG is set */\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n /* DAC_FLAG is reset */\r\n bitstatus = RESET;\r\n }\r\n /* Return the DAC_FLAG status */\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @brief Clears the DAC channel's pending flags.\r\n * @param DAC_Channel: The selected DAC channel. \r\n * This parameter can be one of the following values:\r\n * @arg DAC_Channel_1: DAC Channel1 selected\r\n * @arg DAC_Channel_2: DAC Channel2 selected\r\n * @param DAC_FLAG: specifies the flag to clear. \r\n * This parameter can be of the following value:\r\n * @arg DAC_FLAG_DMAUDR: DMA underrun flag \r\n * @note The DMA underrun occurs when a second external trigger arrives before the \r\n * acknowledgement for the first external trigger is received (first request). \r\n * @retval None\r\n */\r\nvoid DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_DAC_CHANNEL(DAC_Channel));\r\n assert_param(IS_DAC_FLAG(DAC_FLAG));\r\n\r\n /* Clear the selected DAC flags */\r\n DAC->SR = (DAC_FLAG << DAC_Channel);\r\n}\r\n\r\n/**\r\n * @brief Checks whether the specified DAC interrupt has occurred or not.\r\n * @param DAC_Channel: The selected DAC channel. \r\n * This parameter can be one of the following values:\r\n * @arg DAC_Channel_1: DAC Channel1 selected\r\n * @arg DAC_Channel_2: DAC Channel2 selected\r\n * @param DAC_IT: specifies the DAC interrupt source to check. \r\n * This parameter can be the following values:\r\n * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask\r\n * @note The DMA underrun occurs when a second external trigger arrives before the \r\n * acknowledgement for the first external trigger is received (first request).\r\n * @retval The new state of DAC_IT (SET or RESET).\r\n */\r\nITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)\r\n{\r\n ITStatus bitstatus = RESET;\r\n uint32_t enablestatus = 0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_DAC_CHANNEL(DAC_Channel));\r\n assert_param(IS_DAC_IT(DAC_IT));\r\n\r\n /* Get the DAC_IT enable bit status */\r\n enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;\r\n \r\n /* Check the status of the specified DAC interrupt */\r\n if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)\r\n {\r\n /* DAC_IT is set */\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n /* DAC_IT is reset */\r\n bitstatus = RESET;\r\n }\r\n /* Return the DAC_IT status */\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @brief Clears the DAC channel's interrupt pending bits.\r\n * @param DAC_Channel: The selected DAC channel. \r\n * This parameter can be one of the following values:\r\n * @arg DAC_Channel_1: DAC Channel1 selected\r\n * @arg DAC_Channel_2: DAC Channel2 selected\r\n * @param DAC_IT: specifies the DAC interrupt pending bit to clear.\r\n * This parameter can be the following values:\r\n * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask \r\n * @note The DMA underrun occurs when a second external trigger arrives before the \r\n * acknowledgement for the first external trigger is received (first request). \r\n * @retval None\r\n */\r\nvoid DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_DAC_CHANNEL(DAC_Channel));\r\n assert_param(IS_DAC_IT(DAC_IT)); \r\n\r\n /* Clear the selected DAC interrupt pending bits */\r\n DAC->SR = (DAC_IT << DAC_Channel);\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dbgmcu.c", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_dbgmcu.c\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file provides all the DBGMCU firmware functions.\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx_dbgmcu.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @defgroup DBGMCU \r\n * @brief DBGMCU driver modules\r\n * @{\r\n */ \r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup DBGMCU_Private_Functions\r\n * @{\r\n */ \r\n\r\n/**\r\n * @brief Returns the device revision identifier.\r\n * @param None\r\n * @retval Device revision identifier\r\n */\r\nuint32_t DBGMCU_GetREVID(void)\r\n{\r\n return(DBGMCU->IDCODE >> 16);\r\n}\r\n\r\n/**\r\n * @brief Returns the device identifier.\r\n * @param None\r\n * @retval Device identifier\r\n */\r\nuint32_t DBGMCU_GetDEVID(void)\r\n{\r\n return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);\r\n}\r\n\r\n/**\r\n * @brief Configures low power mode behavior when the MCU is in Debug mode.\r\n * @param DBGMCU_Periph: specifies the low power mode.\r\n * This parameter can be any combination of the following values:\r\n * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode \r\n * @arg DBGMCU_STOP: Keep debugger connection during STOP mode \r\n * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode \r\n * @param NewState: new state of the specified low power mode in Debug mode.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n DBGMCU->CR |= DBGMCU_Periph;\r\n }\r\n else\r\n {\r\n DBGMCU->CR &= ~DBGMCU_Periph;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode.\r\n * @param DBGMCU_Periph: specifies the APB1 peripheral.\r\n * This parameter can be any combination of the following values: \r\n * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted \r\n * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted \r\n * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted\r\n * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted \r\n * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted \r\n * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted\r\n * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted \r\n * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted \r\n * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted \r\n * @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped when Core is halted. \r\n * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted\r\n * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted \r\n * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted\r\n * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted\r\n * @arg DBGMCU_I2C3_SMBUS_TIMEOUT: I2C3 SMBUS timeout mode stopped when Core is halted\r\n * @arg DBGMCU_CAN2_STOP: Debug CAN1 stopped when Core is halted \r\n * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted \r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n if (NewState != DISABLE)\r\n {\r\n DBGMCU->APB1FZ |= DBGMCU_Periph;\r\n }\r\n else\r\n {\r\n DBGMCU->APB1FZ &= ~DBGMCU_Periph;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode.\r\n * @param DBGMCU_Periph: specifies the APB2 peripheral.\r\n * This parameter can be any combination of the following values: \r\n * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted \r\n * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted\r\n * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted \r\n * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted \r\n * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted \r\n * @param NewState: new state of the specified peripheral in Debug mode.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n if (NewState != DISABLE)\r\n {\r\n DBGMCU->APB2FZ |= DBGMCU_Periph;\r\n }\r\n else\r\n {\r\n DBGMCU->APB2FZ &= ~DBGMCU_Periph;\r\n }\r\n}\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_dcmi.c\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file provides firmware functions to manage the following \r\n * functionalities of the DCMI peripheral: \r\n * - Initialization and Configuration\r\n * - Image capture functions \r\n * - Interrupts and flags management\r\n *\r\n * @verbatim \r\n * \r\n * \r\n * ===================================================================\r\n * How to use this driver\r\n * =================================================================== \r\n * \r\n * The sequence below describes how to use this driver to capture image\r\n * from a camera module connected to the DCMI Interface.\r\n * This sequence does not take into account the configuration of the \r\n * camera module, which should be made before to configure and enable\r\n * the DCMI to capture images.\r\n * \r\n * 1. Enable the clock for the DCMI and associated GPIOs using the following functions:\r\n * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_DCMI, ENABLE);\r\n * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);\r\n *\r\n * 2. DCMI pins configuration \r\n * - Connect the involved DCMI pins to AF13 using the following function \r\n * GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_DCMI); \r\n * - Configure these DCMI pins in alternate function mode by calling the function\r\n * GPIO_Init();\r\n * \r\n * 3. Declare a DCMI_InitTypeDef structure, for example:\r\n * DCMI_InitTypeDef DCMI_InitStructure;\r\n * and fill the DCMI_InitStructure variable with the allowed values\r\n * of the structure member.\r\n * \r\n * 4. Initialize the DCMI interface by calling the function\r\n * DCMI_Init(&DCMI_InitStructure); \r\n * \r\n * 5. Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR\r\n * register to the destination memory buffer.\r\n * \r\n * 6. Enable DCMI interface using the function\r\n * DCMI_Cmd(ENABLE);\r\n * \r\n * 7. Start the image capture using the function\r\n * DCMI_CaptureCmd(ENABLE);\r\n * \r\n * 8. At this stage the DCMI interface waits for the first start of frame,\r\n * then a DMA request is generated continuously/once (depending on the\r\n * mode used, Continuous/Snapshot) to transfer the received data into\r\n * the destination memory. \r\n * \r\n * @note If you need to capture only a rectangular window from the received\r\n * image, you have to use the DCMI_CROPConfig() function to configure \r\n * the coordinates and size of the window to be captured, then enable \r\n * the Crop feature using DCMI_CROPCmd(ENABLE); \r\n * In this case, the Crop configuration should be made before to enable\r\n * and start the DCMI interface. \r\n * \r\n * @endverbatim \r\n * \r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx_dcmi.h\"\r\n#include \"stm32f4xx_rcc.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @defgroup DCMI \r\n * @brief DCMI driver modules\r\n * @{\r\n */ \r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup DCMI_Private_Functions\r\n * @{\r\n */ \r\n\r\n/** @defgroup DCMI_Group1 Initialization and Configuration functions\r\n * @brief Initialization and Configuration functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Initialization and Configuration functions\r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Deinitializes the DCMI registers to their default reset values.\r\n * @param None\r\n * @retval None\r\n */\r\nvoid DCMI_DeInit(void)\r\n{\r\n DCMI->CR = 0x0;\r\n DCMI->IER = 0x0;\r\n DCMI->ICR = 0x1F;\r\n DCMI->ESCR = 0x0;\r\n DCMI->ESUR = 0x0;\r\n DCMI->CWSTRTR = 0x0;\r\n DCMI->CWSIZER = 0x0;\r\n}\r\n\r\n/**\r\n * @brief Initializes the DCMI according to the specified parameters in the DCMI_InitStruct.\r\n * @param DCMI_InitStruct: pointer to a DCMI_InitTypeDef structure that contains \r\n * the configuration information for the DCMI.\r\n * @retval None\r\n */\r\nvoid DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct)\r\n{\r\n uint32_t temp = 0x0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_DCMI_CAPTURE_MODE(DCMI_InitStruct->DCMI_CaptureMode));\r\n assert_param(IS_DCMI_SYNCHRO(DCMI_InitStruct->DCMI_SynchroMode));\r\n assert_param(IS_DCMI_PCKPOLARITY(DCMI_InitStruct->DCMI_PCKPolarity));\r\n assert_param(IS_DCMI_VSPOLARITY(DCMI_InitStruct->DCMI_VSPolarity));\r\n assert_param(IS_DCMI_HSPOLARITY(DCMI_InitStruct->DCMI_HSPolarity));\r\n assert_param(IS_DCMI_CAPTURE_RATE(DCMI_InitStruct->DCMI_CaptureRate));\r\n assert_param(IS_DCMI_EXTENDED_DATA(DCMI_InitStruct->DCMI_ExtendedDataMode));\r\n\r\n /* The DCMI configuration registers should be programmed correctly before \r\n enabling the CR_ENABLE Bit and the CR_CAPTURE Bit */\r\n DCMI->CR &= ~(DCMI_CR_ENABLE | DCMI_CR_CAPTURE);\r\n \r\n /* Reset the old DCMI configuration */\r\n temp = DCMI->CR;\r\n \r\n temp &= ~((uint32_t)DCMI_CR_CM | DCMI_CR_ESS | DCMI_CR_PCKPOL |\r\n DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_FCRC_0 | \r\n DCMI_CR_FCRC_1 | DCMI_CR_EDM_0 | DCMI_CR_EDM_1); \r\n \r\n /* Sets the new configuration of the DCMI peripheral */\r\n temp |= ((uint32_t)DCMI_InitStruct->DCMI_CaptureMode |\r\n DCMI_InitStruct->DCMI_SynchroMode |\r\n DCMI_InitStruct->DCMI_PCKPolarity |\r\n DCMI_InitStruct->DCMI_VSPolarity |\r\n DCMI_InitStruct->DCMI_HSPolarity |\r\n DCMI_InitStruct->DCMI_CaptureRate |\r\n DCMI_InitStruct->DCMI_ExtendedDataMode);\r\n\r\n DCMI->CR = temp; \r\n}\r\n\r\n/**\r\n * @brief Fills each DCMI_InitStruct member with its default value.\r\n * @param DCMI_InitStruct : pointer to a DCMI_InitTypeDef structure which will\r\n * be initialized.\r\n * @retval None\r\n */\r\nvoid DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct)\r\n{\r\n /* Set the default configuration */\r\n DCMI_InitStruct->DCMI_CaptureMode = DCMI_CaptureMode_Continuous;\r\n DCMI_InitStruct->DCMI_SynchroMode = DCMI_SynchroMode_Hardware;\r\n DCMI_InitStruct->DCMI_PCKPolarity = DCMI_PCKPolarity_Falling;\r\n DCMI_InitStruct->DCMI_VSPolarity = DCMI_VSPolarity_Low;\r\n DCMI_InitStruct->DCMI_HSPolarity = DCMI_HSPolarity_Low;\r\n DCMI_InitStruct->DCMI_CaptureRate = DCMI_CaptureRate_All_Frame;\r\n DCMI_InitStruct->DCMI_ExtendedDataMode = DCMI_ExtendedDataMode_8b;\r\n}\r\n\r\n/**\r\n * @brief Initializes the DCMI peripheral CROP mode according to the specified\r\n * parameters in the DCMI_CROPInitStruct.\r\n * @note This function should be called before to enable and start the DCMI interface. \r\n * @param DCMI_CROPInitStruct: pointer to a DCMI_CROPInitTypeDef structure that \r\n * contains the configuration information for the DCMI peripheral CROP mode.\r\n * @retval None\r\n */\r\nvoid DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct)\r\n{ \r\n /* Sets the CROP window coordinates */\r\n DCMI->CWSTRTR = (uint32_t)((uint32_t)DCMI_CROPInitStruct->DCMI_HorizontalOffsetCount |\r\n ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalStartLine << 16));\r\n\r\n /* Sets the CROP window size */\r\n DCMI->CWSIZER = (uint32_t)(DCMI_CROPInitStruct->DCMI_CaptureCount |\r\n ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalLineCount << 16));\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the DCMI Crop feature.\r\n * @note This function should be called before to enable and start the DCMI interface.\r\n * @param NewState: new state of the DCMI Crop feature. \r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid DCMI_CROPCmd(FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the DCMI Crop feature */\r\n DCMI->CR |= (uint32_t)DCMI_CR_CROP;\r\n }\r\n else\r\n {\r\n /* Disable the DCMI Crop feature */\r\n DCMI->CR &= ~(uint32_t)DCMI_CR_CROP;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Sets the embedded synchronization codes\r\n * @param DCMI_CodesInitTypeDef: pointer to a DCMI_CodesInitTypeDef structure that\r\n * contains the embedded synchronization codes for the DCMI peripheral.\r\n * @retval None\r\n */\r\nvoid DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct)\r\n{\r\n DCMI->ESCR = (uint32_t)(DCMI_CodesInitStruct->DCMI_FrameStartCode |\r\n ((uint32_t)DCMI_CodesInitStruct->DCMI_LineStartCode << 8)|\r\n ((uint32_t)DCMI_CodesInitStruct->DCMI_LineEndCode << 16)|\r\n ((uint32_t)DCMI_CodesInitStruct->DCMI_FrameEndCode << 24));\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the DCMI JPEG format.\r\n * @note The Crop and Embedded Synchronization features cannot be used in this mode. \r\n * @param NewState: new state of the DCMI JPEG format. \r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid DCMI_JPEGCmd(FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the DCMI JPEG format */\r\n DCMI->CR |= (uint32_t)DCMI_CR_JPEG;\r\n }\r\n else\r\n {\r\n /* Disable the DCMI JPEG format */\r\n DCMI->CR &= ~(uint32_t)DCMI_CR_JPEG;\r\n }\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup DCMI_Group2 Image capture functions\r\n * @brief Image capture functions\r\n *\r\n@verbatim \r\n ===============================================================================\r\n Image capture functions\r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n \r\n/**\r\n * @brief Enables or disables the DCMI interface.\r\n * @param NewState: new state of the DCMI interface. \r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid DCMI_Cmd(FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the DCMI by setting ENABLE bit */\r\n DCMI->CR |= (uint32_t)DCMI_CR_ENABLE;\r\n }\r\n else\r\n {\r\n /* Disable the DCMI by clearing ENABLE bit */\r\n DCMI->CR &= ~(uint32_t)DCMI_CR_ENABLE;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the DCMI Capture.\r\n * @param NewState: new state of the DCMI capture. \r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid DCMI_CaptureCmd(FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the DCMI Capture */\r\n DCMI->CR |= (uint32_t)DCMI_CR_CAPTURE;\r\n }\r\n else\r\n {\r\n /* Disable the DCMI Capture */\r\n DCMI->CR &= ~(uint32_t)DCMI_CR_CAPTURE;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Reads the data stored in the DR register.\r\n * @param None \r\n * @retval Data register value\r\n */\r\nuint32_t DCMI_ReadData(void)\r\n{\r\n return DCMI->DR;\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup DCMI_Group3 Interrupts and flags management functions\r\n * @brief Interrupts and flags management functions\r\n *\r\n@verbatim \r\n ===============================================================================\r\n Interrupts and flags management functions\r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Enables or disables the DCMI interface interrupts.\r\n * @param DCMI_IT: specifies the DCMI interrupt sources to be enabled or disabled. \r\n * This parameter can be any combination of the following values:\r\n * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask\r\n * @arg DCMI_IT_OVF: Overflow interrupt mask\r\n * @arg DCMI_IT_ERR: Synchronization error interrupt mask\r\n * @arg DCMI_IT_VSYNC: VSYNC interrupt mask\r\n * @arg DCMI_IT_LINE: Line interrupt mask\r\n * @param NewState: new state of the specified DCMI interrupts.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_DCMI_CONFIG_IT(DCMI_IT));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the Interrupt sources */\r\n DCMI->IER |= DCMI_IT;\r\n }\r\n else\r\n {\r\n /* Disable the Interrupt sources */\r\n DCMI->IER &= (uint16_t)(~DCMI_IT);\r\n } \r\n}\r\n\r\n/**\r\n * @brief Checks whether the DCMI interface flag is set or not.\r\n * @param DCMI_FLAG: specifies the flag to check.\r\n * This parameter can be one of the following values:\r\n * @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask\r\n * @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask\r\n * @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask\r\n * @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask\r\n * @arg DCMI_FLAG_LINERI: Line Raw flag mask\r\n * @arg DCMI_FLAG_FRAMEMI: Frame capture complete Masked flag mask\r\n * @arg DCMI_FLAG_OVFMI: Overflow Masked flag mask\r\n * @arg DCMI_FLAG_ERRMI: Synchronization error Masked flag mask\r\n * @arg DCMI_FLAG_VSYNCMI: VSYNC Masked flag mask\r\n * @arg DCMI_FLAG_LINEMI: Line Masked flag mask\r\n * @arg DCMI_FLAG_HSYNC: HSYNC flag mask\r\n * @arg DCMI_FLAG_VSYNC: VSYNC flag mask\r\n * @arg DCMI_FLAG_FNE: Fifo not empty flag mask\r\n * @retval The new state of DCMI_FLAG (SET or RESET).\r\n */\r\nFlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG)\r\n{\r\n FlagStatus bitstatus = RESET;\r\n uint32_t dcmireg, tempreg = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_DCMI_GET_FLAG(DCMI_FLAG));\r\n \r\n /* Get the DCMI register index */\r\n dcmireg = (((uint16_t)DCMI_FLAG) >> 12);\r\n \r\n if (dcmireg == 0x00) /* The FLAG is in RISR register */\r\n {\r\n tempreg= DCMI->RISR;\r\n }\r\n else if (dcmireg == 0x02) /* The FLAG is in SR register */\r\n {\r\n tempreg = DCMI->SR;\r\n }\r\n else /* The FLAG is in MISR register */\r\n {\r\n tempreg = DCMI->MISR;\r\n }\r\n \r\n if ((tempreg & DCMI_FLAG) != (uint16_t)RESET )\r\n {\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n bitstatus = RESET;\r\n }\r\n /* Return the DCMI_FLAG status */\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @brief Clears the DCMI's pending flags.\r\n * @param DCMI_FLAG: specifies the flag to clear.\r\n * This parameter can be any combination of the following values:\r\n * @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask\r\n * @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask\r\n * @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask\r\n * @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask\r\n * @arg DCMI_FLAG_LINERI: Line Raw flag mask\r\n * @retval None\r\n */\r\nvoid DCMI_ClearFlag(uint16_t DCMI_FLAG)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_DCMI_CLEAR_FLAG(DCMI_FLAG));\r\n \r\n /* Clear the flag by writing in the ICR register 1 in the corresponding \r\n Flag position*/\r\n \r\n DCMI->ICR = DCMI_FLAG;\r\n}\r\n\r\n/**\r\n * @brief Checks whether the DCMI interrupt has occurred or not.\r\n * @param DCMI_IT: specifies the DCMI interrupt source to check.\r\n * This parameter can be one of the following values:\r\n * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask\r\n * @arg DCMI_IT_OVF: Overflow interrupt mask\r\n * @arg DCMI_IT_ERR: Synchronization error interrupt mask\r\n * @arg DCMI_IT_VSYNC: VSYNC interrupt mask\r\n * @arg DCMI_IT_LINE: Line interrupt mask\r\n * @retval The new state of DCMI_IT (SET or RESET).\r\n */\r\nITStatus DCMI_GetITStatus(uint16_t DCMI_IT)\r\n{\r\n ITStatus bitstatus = RESET;\r\n uint32_t itstatus = 0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_DCMI_GET_IT(DCMI_IT));\r\n \r\n itstatus = DCMI->MISR & DCMI_IT; /* Only masked interrupts are checked */\r\n \r\n if ((itstatus != (uint16_t)RESET))\r\n {\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n bitstatus = RESET;\r\n }\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @brief Clears the DCMI's interrupt pending bits.\r\n * @param DCMI_IT: specifies the DCMI interrupt pending bit to clear.\r\n * This parameter can be any combination of the following values:\r\n * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask\r\n * @arg DCMI_IT_OVF: Overflow interrupt mask\r\n * @arg DCMI_IT_ERR: Synchronization error interrupt mask\r\n * @arg DCMI_IT_VSYNC: VSYNC interrupt mask\r\n * @arg DCMI_IT_LINE: Line interrupt mask\r\n * @retval None\r\n */\r\nvoid DCMI_ClearITPendingBit(uint16_t DCMI_IT)\r\n{\r\n /* Clear the interrupt pending Bit by writing in the ICR register 1 in the \r\n corresponding pending Bit position*/\r\n \r\n DCMI->ICR = DCMI_IT;\r\n}\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_dma.c\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file provides firmware functions to manage the following \r\n * functionalities of the Direct Memory Access controller (DMA): \r\n * - Initialization and Configuration\r\n * - Data Counter\r\n * - Double Buffer mode configuration and command \r\n * - Interrupts and flags management\r\n * \r\n * @verbatim\r\n * \r\n * =================================================================== \r\n * How to use this driver\r\n * =================================================================== \r\n * 1. Enable The DMA controller clock using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA1, ENABLE)\r\n * function for DMA1 or using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2, ENABLE)\r\n * function for DMA2.\r\n *\r\n * 2. Enable and configure the peripheral to be connected to the DMA Stream\r\n * (except for internal SRAM / FLASH memories: no initialization is \r\n * necessary). \r\n * \r\n * 3. For a given Stream, program the required configuration through following parameters: \r\n * Source and Destination addresses, Transfer Direction, Transfer size, Source and Destination \r\n * data formats, Circular or Normal mode, Stream Priority level, Source and Destination \r\n * Incrementation mode, FIFO mode and its Threshold (if needed), Burst mode for Source and/or \r\n * Destination (if needed) using the DMA_Init() function.\r\n * To avoid filling un-nesecessary fields, you can call DMA_StructInit() function\r\n * to initialize a given structure with default values (reset values), the modify\r\n * only necessary fields (ie. Source and Destination addresses, Transfer size and Data Formats).\r\n *\r\n * 4. Enable the NVIC and the corresponding interrupt(s) using the function \r\n * DMA_ITConfig() if you need to use DMA interrupts. \r\n *\r\n * 5. Optionally, if the Circular mode is enabled, you can use the Double buffer mode by configuring \r\n * the second Memory address and the first Memory to be used through the function \r\n * DMA_DoubleBufferModeConfig(). Then enable the Double buffer mode through the function\r\n * DMA_DoubleBufferModeCmd(). These operations must be done before step 6.\r\n * \r\n * 6. Enable the DMA stream using the DMA_Cmd() function. \r\n * \r\n * 7. Activate the needed Stream Request using PPP_DMACmd() function for\r\n * any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...)\r\n * The function allowing this operation is provided in each PPP peripheral\r\n * driver (ie. SPI_DMACmd for SPI peripheral).\r\n * Once the Stream is enabled, it is not possible to modify its configuration\r\n * unless the stream is stopped and disabled.\r\n * After enabling the Stream, it is advised to monitor the EN bit status using\r\n * the function DMA_GetCmdStatus(). In case of configuration errors or bus errors\r\n * this bit will remain reset and all transfers on this Stream will remain on hold. \r\n *\r\n * 8. Optionally, you can configure the number of data to be transferred\r\n * when the Stream is disabled (ie. after each Transfer Complete event\r\n * or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().\r\n * And you can get the number of remaining data to be transferred using \r\n * the function DMA_GetCurrDataCounter() at run time (when the DMA Stream is\r\n * enabled and running). \r\n * \r\n * 9. To control DMA events you can use one of the following \r\n * two methods:\r\n * a- Check on DMA Stream flags using the function DMA_GetFlagStatus(). \r\n * b- Use DMA interrupts through the function DMA_ITConfig() at initialization\r\n * phase and DMA_GetITStatus() function into interrupt routines in\r\n * communication phase. \r\n * After checking on a flag you should clear it using DMA_ClearFlag()\r\n * function. And after checking on an interrupt event you should \r\n * clear it using DMA_ClearITPendingBit() function. \r\n * \r\n * 10. Optionally, if Circular mode and Double Buffer mode are enabled, you can modify\r\n * the Memory Addresses using the function DMA_MemoryTargetConfig(). Make sure that\r\n * the Memory Address to be modified is not the one currently in use by DMA Stream.\r\n * This condition can be monitored using the function DMA_GetCurrentMemoryTarget().\r\n * \r\n * 11. Optionally, Pause-Resume operations may be performed:\r\n * The DMA_Cmd() function may be used to perform Pause-Resume operation. When a \r\n * transfer is ongoing, calling this function to disable the Stream will cause the \r\n * transfer to be paused. All configuration registers and the number of remaining \r\n * data will be preserved. When calling again this function to re-enable the Stream, \r\n * the transfer will be resumed from the point where it was paused. \r\n * \r\n * @note Memory-to-Memory transfer is possible by setting the address of the memory into\r\n * the Peripheral registers. In this mode, Circular mode and Double Buffer mode\r\n * are not allowed.\r\n * \r\n * @note The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is\r\n * possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set\r\n * Half-Word data size for the peripheral to access its data register and set Word data size\r\n * for the Memory to gain in access time. Each two Half-words will be packed and written in\r\n * a single access to a Word in the Memory).\r\n * \r\n * @note When FIFO is disabled, it is not allowed to configure different Data Sizes for Source\r\n * and Destination. In this case the Peripheral Data Size will be applied to both Source\r\n * and Destination. \r\n *\r\n * @endverbatim\r\n * \r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx_dma.h\"\r\n#include \"stm32f4xx_rcc.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @defgroup DMA \r\n * @brief DMA driver modules\r\n * @{\r\n */ \r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n\r\n/* Masks Definition */\r\n#define TRANSFER_IT_ENABLE_MASK (uint32_t)(DMA_SxCR_TCIE | DMA_SxCR_HTIE | \\\r\n DMA_SxCR_TEIE | DMA_SxCR_DMEIE)\r\n\r\n#define DMA_Stream0_IT_MASK (uint32_t)(DMA_LISR_FEIF0 | DMA_LISR_DMEIF0 | \\\r\n DMA_LISR_TEIF0 | DMA_LISR_HTIF0 | \\\r\n DMA_LISR_TCIF0)\r\n\r\n#define DMA_Stream1_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 6)\r\n#define DMA_Stream2_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 16)\r\n#define DMA_Stream3_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 22)\r\n#define DMA_Stream4_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK | (uint32_t)0x20000000)\r\n#define DMA_Stream5_IT_MASK (uint32_t)(DMA_Stream1_IT_MASK | (uint32_t)0x20000000)\r\n#define DMA_Stream6_IT_MASK (uint32_t)(DMA_Stream2_IT_MASK | (uint32_t)0x20000000)\r\n#define DMA_Stream7_IT_MASK (uint32_t)(DMA_Stream3_IT_MASK | (uint32_t)0x20000000)\r\n#define TRANSFER_IT_MASK (uint32_t)0x0F3C0F3C\r\n#define HIGH_ISR_MASK (uint32_t)0x20000000\r\n#define RESERVED_MASK (uint32_t)0x0F7D0F7D \r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n\r\n/** @defgroup DMA_Private_Functions\r\n * @{\r\n */\r\n\r\n/** @defgroup DMA_Group1 Initialization and Configuration functions\r\n * @brief Initialization and Configuration functions\r\n *\r\n@verbatim \r\n ===============================================================================\r\n Initialization and Configuration functions\r\n =============================================================================== \r\n\r\n This subsection provides functions allowing to initialize the DMA Stream source\r\n and destination addresses, incrementation and data sizes, transfer direction, \r\n buffer size, circular/normal mode selection, memory-to-memory mode selection \r\n and Stream priority value.\r\n \r\n The DMA_Init() function follows the DMA configuration procedures as described in\r\n reference manual (RM0090) except the first point: waiting on EN bit to be reset.\r\n This condition should be checked by user application using the function DMA_GetCmdStatus()\r\n before calling the DMA_Init() function.\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Deinitialize the DMAy Streamx registers to their default reset values.\r\n * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0\r\n * to 7 to select the DMA Stream.\r\n * @retval None\r\n */\r\nvoid DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));\r\n\r\n /* Disable the selected DMAy Streamx */\r\n DMAy_Streamx->CR &= ~((uint32_t)DMA_SxCR_EN);\r\n\r\n /* Reset DMAy Streamx control register */\r\n DMAy_Streamx->CR = 0;\r\n \r\n /* Reset DMAy Streamx Number of Data to Transfer register */\r\n DMAy_Streamx->NDTR = 0;\r\n \r\n /* Reset DMAy Streamx peripheral address register */\r\n DMAy_Streamx->PAR = 0;\r\n \r\n /* Reset DMAy Streamx memory 0 address register */\r\n DMAy_Streamx->M0AR = 0;\r\n\r\n /* Reset DMAy Streamx memory 1 address register */\r\n DMAy_Streamx->M1AR = 0;\r\n\r\n /* Reset DMAy Streamx FIFO control register */\r\n DMAy_Streamx->FCR = (uint32_t)0x00000021; \r\n\r\n /* Reset interrupt pending bits for the selected stream */\r\n if (DMAy_Streamx == DMA1_Stream0)\r\n {\r\n /* Reset interrupt pending bits for DMA1 Stream0 */\r\n DMA1->LIFCR = DMA_Stream0_IT_MASK;\r\n }\r\n else if (DMAy_Streamx == DMA1_Stream1)\r\n {\r\n /* Reset interrupt pending bits for DMA1 Stream1 */\r\n DMA1->LIFCR = DMA_Stream1_IT_MASK;\r\n }\r\n else if (DMAy_Streamx == DMA1_Stream2)\r\n {\r\n /* Reset interrupt pending bits for DMA1 Stream2 */\r\n DMA1->LIFCR = DMA_Stream2_IT_MASK;\r\n }\r\n else if (DMAy_Streamx == DMA1_Stream3)\r\n {\r\n /* Reset interrupt pending bits for DMA1 Stream3 */\r\n DMA1->LIFCR = DMA_Stream3_IT_MASK;\r\n }\r\n else if (DMAy_Streamx == DMA1_Stream4)\r\n {\r\n /* Reset interrupt pending bits for DMA1 Stream4 */\r\n DMA1->HIFCR = DMA_Stream4_IT_MASK;\r\n }\r\n else if (DMAy_Streamx == DMA1_Stream5)\r\n {\r\n /* Reset interrupt pending bits for DMA1 Stream5 */\r\n DMA1->HIFCR = DMA_Stream5_IT_MASK;\r\n }\r\n else if (DMAy_Streamx == DMA1_Stream6)\r\n {\r\n /* Reset interrupt pending bits for DMA1 Stream6 */\r\n DMA1->HIFCR = (uint32_t)DMA_Stream6_IT_MASK;\r\n }\r\n else if (DMAy_Streamx == DMA1_Stream7)\r\n {\r\n /* Reset interrupt pending bits for DMA1 Stream7 */\r\n DMA1->HIFCR = DMA_Stream7_IT_MASK;\r\n }\r\n else if (DMAy_Streamx == DMA2_Stream0)\r\n {\r\n /* Reset interrupt pending bits for DMA2 Stream0 */\r\n DMA2->LIFCR = DMA_Stream0_IT_MASK;\r\n }\r\n else if (DMAy_Streamx == DMA2_Stream1)\r\n {\r\n /* Reset interrupt pending bits for DMA2 Stream1 */\r\n DMA2->LIFCR = DMA_Stream1_IT_MASK;\r\n }\r\n else if (DMAy_Streamx == DMA2_Stream2)\r\n {\r\n /* Reset interrupt pending bits for DMA2 Stream2 */\r\n DMA2->LIFCR = DMA_Stream2_IT_MASK;\r\n }\r\n else if (DMAy_Streamx == DMA2_Stream3)\r\n {\r\n /* Reset interrupt pending bits for DMA2 Stream3 */\r\n DMA2->LIFCR = DMA_Stream3_IT_MASK;\r\n }\r\n else if (DMAy_Streamx == DMA2_Stream4)\r\n {\r\n /* Reset interrupt pending bits for DMA2 Stream4 */\r\n DMA2->HIFCR = DMA_Stream4_IT_MASK;\r\n }\r\n else if (DMAy_Streamx == DMA2_Stream5)\r\n {\r\n /* Reset interrupt pending bits for DMA2 Stream5 */\r\n DMA2->HIFCR = DMA_Stream5_IT_MASK;\r\n }\r\n else if (DMAy_Streamx == DMA2_Stream6)\r\n {\r\n /* Reset interrupt pending bits for DMA2 Stream6 */\r\n DMA2->HIFCR = DMA_Stream6_IT_MASK;\r\n }\r\n else \r\n {\r\n if (DMAy_Streamx == DMA2_Stream7)\r\n {\r\n /* Reset interrupt pending bits for DMA2 Stream7 */\r\n DMA2->HIFCR = DMA_Stream7_IT_MASK;\r\n }\r\n }\r\n}\r\n\r\n/**\r\n * @brief Initializes the DMAy Streamx according to the specified parameters in \r\n * the DMA_InitStruct structure.\r\n * @note Before calling this function, it is recommended to check that the Stream \r\n * is actually disabled using the function DMA_GetCmdStatus(). \r\n * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0\r\n * to 7 to select the DMA Stream.\r\n * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains\r\n * the configuration information for the specified DMA Stream. \r\n * @retval None\r\n */\r\nvoid DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct)\r\n{\r\n uint32_t tmpreg = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));\r\n assert_param(IS_DMA_CHANNEL(DMA_InitStruct->DMA_Channel));\r\n assert_param(IS_DMA_DIRECTION(DMA_InitStruct->DMA_DIR));\r\n assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));\r\n assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));\r\n assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));\r\n assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));\r\n assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));\r\n assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));\r\n assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));\r\n assert_param(IS_DMA_FIFO_MODE_STATE(DMA_InitStruct->DMA_FIFOMode));\r\n assert_param(IS_DMA_FIFO_THRESHOLD(DMA_InitStruct->DMA_FIFOThreshold));\r\n assert_param(IS_DMA_MEMORY_BURST(DMA_InitStruct->DMA_MemoryBurst));\r\n assert_param(IS_DMA_PERIPHERAL_BURST(DMA_InitStruct->DMA_PeripheralBurst));\r\n\r\n /*------------------------- DMAy Streamx CR Configuration ------------------*/\r\n /* Get the DMAy_Streamx CR value */\r\n tmpreg = DMAy_Streamx->CR;\r\n\r\n /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */\r\n tmpreg &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \\\r\n DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \\\r\n DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \\\r\n DMA_SxCR_DIR));\r\n\r\n /* Configure DMAy Streamx: */\r\n /* Set CHSEL bits according to DMA_CHSEL value */\r\n /* Set DIR bits according to DMA_DIR value */\r\n /* Set PINC bit according to DMA_PeripheralInc value */\r\n /* Set MINC bit according to DMA_MemoryInc value */\r\n /* Set PSIZE bits according to DMA_PeripheralDataSize value */\r\n /* Set MSIZE bits according to DMA_MemoryDataSize value */\r\n /* Set CIRC bit according to DMA_Mode value */\r\n /* Set PL bits according to DMA_Priority value */\r\n /* Set MBURST bits according to DMA_MemoryBurst value */\r\n /* Set PBURST bits according to DMA_PeripheralBurst value */\r\n tmpreg |= DMA_InitStruct->DMA_Channel | DMA_InitStruct->DMA_DIR |\r\n DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |\r\n DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |\r\n DMA_InitStruct->DMA_Mode | DMA_InitStruct->DMA_Priority |\r\n DMA_InitStruct->DMA_MemoryBurst | DMA_InitStruct->DMA_PeripheralBurst;\r\n\r\n /* Write to DMAy Streamx CR register */\r\n DMAy_Streamx->CR = tmpreg;\r\n\r\n /*------------------------- DMAy Streamx FCR Configuration -----------------*/\r\n /* Get the DMAy_Streamx FCR value */\r\n tmpreg = DMAy_Streamx->FCR;\r\n\r\n /* Clear DMDIS and FTH bits */\r\n tmpreg &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);\r\n\r\n /* Configure DMAy Streamx FIFO: \r\n Set DMDIS bits according to DMA_FIFOMode value \r\n Set FTH bits according to DMA_FIFOThreshold value */\r\n tmpreg |= DMA_InitStruct->DMA_FIFOMode | DMA_InitStruct->DMA_FIFOThreshold;\r\n\r\n /* Write to DMAy Streamx CR */\r\n DMAy_Streamx->FCR = tmpreg;\r\n\r\n /*------------------------- DMAy Streamx NDTR Configuration ----------------*/\r\n /* Write to DMAy Streamx NDTR register */\r\n DMAy_Streamx->NDTR = DMA_InitStruct->DMA_BufferSize;\r\n\r\n /*------------------------- DMAy Streamx PAR Configuration -----------------*/\r\n /* Write to DMAy Streamx PAR */\r\n DMAy_Streamx->PAR = DMA_InitStruct->DMA_PeripheralBaseAddr;\r\n\r\n /*------------------------- DMAy Streamx M0AR Configuration ----------------*/\r\n /* Write to DMAy Streamx M0AR */\r\n DMAy_Streamx->M0AR = DMA_InitStruct->DMA_Memory0BaseAddr;\r\n}\r\n\r\n/**\r\n * @brief Fills each DMA_InitStruct member with its default value.\r\n * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will \r\n * be initialized.\r\n * @retval None\r\n */\r\nvoid DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)\r\n{\r\n /*-------------- Reset DMA init structure parameters values ----------------*/\r\n /* Initialize the DMA_Channel member */\r\n DMA_InitStruct->DMA_Channel = 0;\r\n\r\n /* Initialize the DMA_PeripheralBaseAddr member */\r\n DMA_InitStruct->DMA_PeripheralBaseAddr = 0;\r\n\r\n /* Initialize the DMA_Memory0BaseAddr member */\r\n DMA_InitStruct->DMA_Memory0BaseAddr = 0;\r\n\r\n /* Initialize the DMA_DIR member */\r\n DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralToMemory;\r\n\r\n /* Initialize the DMA_BufferSize member */\r\n DMA_InitStruct->DMA_BufferSize = 0;\r\n\r\n /* Initialize the DMA_PeripheralInc member */\r\n DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;\r\n\r\n /* Initialize the DMA_MemoryInc member */\r\n DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;\r\n\r\n /* Initialize the DMA_PeripheralDataSize member */\r\n DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;\r\n\r\n /* Initialize the DMA_MemoryDataSize member */\r\n DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;\r\n\r\n /* Initialize the DMA_Mode member */\r\n DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;\r\n\r\n /* Initialize the DMA_Priority member */\r\n DMA_InitStruct->DMA_Priority = DMA_Priority_Low;\r\n\r\n /* Initialize the DMA_FIFOMode member */\r\n DMA_InitStruct->DMA_FIFOMode = DMA_FIFOMode_Disable;\r\n\r\n /* Initialize the DMA_FIFOThreshold member */\r\n DMA_InitStruct->DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull;\r\n\r\n /* Initialize the DMA_MemoryBurst member */\r\n DMA_InitStruct->DMA_MemoryBurst = DMA_MemoryBurst_Single;\r\n\r\n /* Initialize the DMA_PeripheralBurst member */\r\n DMA_InitStruct->DMA_PeripheralBurst = DMA_PeripheralBurst_Single;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the specified DMAy Streamx.\r\n * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0\r\n * to 7 to select the DMA Stream.\r\n * @param NewState: new state of the DMAy Streamx. \r\n * This parameter can be: ENABLE or DISABLE.\r\n *\r\n * @note This function may be used to perform Pause-Resume operation. When a\r\n * transfer is ongoing, calling this function to disable the Stream will\r\n * cause the transfer to be paused. All configuration registers and the\r\n * number of remaining data will be preserved. When calling again this\r\n * function to re-enable the Stream, the transfer will be resumed from\r\n * the point where it was paused. \r\n * \r\n * @note After configuring the DMA Stream (DMA_Init() function) and enabling the\r\n * stream, it is recommended to check (or wait until) the DMA Stream is\r\n * effectively enabled. A Stream may remain disabled if a configuration \r\n * parameter is wrong.\r\n * After disabling a DMA Stream, it is also recommended to check (or wait\r\n * until) the DMA Stream is effectively disabled. If a Stream is disabled \r\n * while a data transfer is ongoing, the current data will be transferred\r\n * and the Stream will be effectively disabled only after the transfer of\r\n * this single data is finished. \r\n * \r\n * @retval None\r\n */\r\nvoid DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected DMAy Streamx by setting EN bit */\r\n DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_EN;\r\n }\r\n else\r\n {\r\n /* Disable the selected DMAy Streamx by clearing EN bit */\r\n DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_EN;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Configures, when the PINC (Peripheral Increment address mode) bit is\r\n * set, if the peripheral address should be incremented with the data \r\n * size (configured with PSIZE bits) or by a fixed offset equal to 4\r\n * (32-bit aligned addresses).\r\n * \r\n * @note This function has no effect if the Peripheral Increment mode is disabled.\r\n * \r\n * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0\r\n * to 7 to select the DMA Stream.\r\n * @param DMA_Pincos: specifies the Peripheral increment offset size.\r\n * This parameter can be one of the following values:\r\n * @arg DMA_PINCOS_Psize: Peripheral address increment is done \r\n * accordingly to PSIZE parameter.\r\n * @arg DMA_PINCOS_WordAligned: Peripheral address increment offset is \r\n * fixed to 4 (32-bit aligned addresses). \r\n * @retval None\r\n */\r\nvoid DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));\r\n assert_param(IS_DMA_PINCOS_SIZE(DMA_Pincos));\r\n\r\n /* Check the needed Peripheral increment offset */\r\n if(DMA_Pincos != DMA_PINCOS_Psize)\r\n {\r\n /* Configure DMA_SxCR_PINCOS bit with the input parameter */\r\n DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PINCOS; \r\n }\r\n else\r\n {\r\n /* Clear the PINCOS bit: Peripheral address incremented according to PSIZE */\r\n DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PINCOS; \r\n }\r\n}\r\n\r\n/**\r\n * @brief Configures, when the DMAy Streamx is disabled, the flow controller for\r\n * the next transactions (Peripheral or Memory).\r\n * \r\n * @note Before enabling this feature, check if the used peripheral supports \r\n * the Flow Controller mode or not. \r\n * \r\n * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0\r\n * to 7 to select the DMA Stream.\r\n * @param DMA_FlowCtrl: specifies the DMA flow controller.\r\n * This parameter can be one of the following values:\r\n * @arg DMA_FlowCtrl_Memory: DMAy_Streamx transactions flow controller is \r\n * the DMA controller.\r\n * @arg DMA_FlowCtrl_Peripheral: DMAy_Streamx transactions flow controller \r\n * is the peripheral. \r\n * @retval None\r\n */\r\nvoid DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));\r\n assert_param(IS_DMA_FLOW_CTRL(DMA_FlowCtrl));\r\n\r\n /* Check the needed flow controller */\r\n if(DMA_FlowCtrl != DMA_FlowCtrl_Memory)\r\n {\r\n /* Configure DMA_SxCR_PFCTRL bit with the input parameter */\r\n DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PFCTRL; \r\n }\r\n else\r\n {\r\n /* Clear the PFCTRL bit: Memory is the flow controller */\r\n DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PFCTRL; \r\n }\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup DMA_Group2 Data Counter functions\r\n * @brief Data Counter functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Data Counter functions\r\n =============================================================================== \r\n\r\n This subsection provides function allowing to configure and read the buffer size\r\n (number of data to be transferred). \r\n\r\n The DMA data counter can be written only when the DMA Stream is disabled \r\n (ie. after transfer complete event).\r\n\r\n The following function can be used to write the Stream data counter value:\r\n - void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter);\r\n\r\n@note It is advised to use this function rather than DMA_Init() in situations where\r\n only the Data buffer needs to be reloaded.\r\n\r\n@note If the Source and Destination Data Sizes are different, then the value written in\r\n data counter, expressing the number of transfers, is relative to the number of \r\n transfers from the Peripheral point of view.\r\n ie. If Memory data size is Word, Peripheral data size is Half-Words, then the value\r\n to be configured in the data counter is the number of Half-Words to be transferred\r\n from/to the peripheral.\r\n\r\n The DMA data counter can be read to indicate the number of remaining transfers for\r\n the relative DMA Stream. This counter is decremented at the end of each data \r\n transfer and when the transfer is complete: \r\n - If Normal mode is selected: the counter is set to 0.\r\n - If Circular mode is selected: the counter is reloaded with the initial value\r\n (configured before enabling the DMA Stream)\r\n \r\n The following function can be used to read the Stream data counter value:\r\n - uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx);\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Writes the number of data units to be transferred on the DMAy Streamx.\r\n * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0\r\n * to 7 to select the DMA Stream.\r\n * @param Counter: Number of data units to be transferred (from 0 to 65535) \r\n * Number of data items depends only on the Peripheral data format.\r\n * \r\n * @note If Peripheral data format is Bytes: number of data units is equal \r\n * to total number of bytes to be transferred.\r\n * \r\n * @note If Peripheral data format is Half-Word: number of data units is \r\n * equal to total number of bytes to be transferred / 2.\r\n * \r\n * @note If Peripheral data format is Word: number of data units is equal \r\n * to total number of bytes to be transferred / 4.\r\n * \r\n * @note In Memory-to-Memory transfer mode, the memory buffer pointed by \r\n * DMAy_SxPAR register is considered as Peripheral.\r\n * \r\n * @retval The number of remaining data units in the current DMAy Streamx transfer.\r\n */\r\nvoid DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));\r\n\r\n /* Write the number of data units to be transferred */\r\n DMAy_Streamx->NDTR = (uint16_t)Counter;\r\n}\r\n\r\n/**\r\n * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.\r\n * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0\r\n * to 7 to select the DMA Stream.\r\n * @retval The number of remaining data units in the current DMAy Streamx transfer.\r\n */\r\nuint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));\r\n\r\n /* Return the number of remaining data units for DMAy Streamx */\r\n return ((uint16_t)(DMAy_Streamx->NDTR));\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup DMA_Group3 Double Buffer mode functions\r\n * @brief Double Buffer mode functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Double Buffer mode functions\r\n =============================================================================== \r\n\r\n This subsection provides function allowing to configure and control the double \r\n buffer mode parameters.\r\n \r\n The Double Buffer mode can be used only when Circular mode is enabled.\r\n The Double Buffer mode cannot be used when transferring data from Memory to Memory.\r\n \r\n The Double Buffer mode allows to set two different Memory addresses from/to which\r\n the DMA controller will access alternatively (after completing transfer to/from target\r\n memory 0, it will start transfer to/from target memory 1).\r\n This allows to reduce software overhead for double buffering and reduce the CPU\r\n access time.\r\n\r\n Two functions must be called before calling the DMA_Init() function:\r\n - void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,\r\n uint32_t DMA_CurrentMemory);\r\n - void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);\r\n \r\n DMA_DoubleBufferModeConfig() is called to configure the Memory 1 base address and the first\r\n Memory target from/to which the transfer will start after enabling the DMA Stream.\r\n Then DMA_DoubleBufferModeCmd() must be called to enable the Double Buffer mode (or disable \r\n it when it should not be used).\r\n \r\n \r\n Two functions can be called dynamically when the transfer is ongoing (or when the DMA Stream is \r\n stopped) to modify on of the target Memories addresses or to check wich Memory target is currently\r\n used:\r\n - void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,\r\n uint32_t DMA_MemoryTarget);\r\n - uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx);\r\n\r\n DMA_MemoryTargetConfig() can be called to modify the base address of one of the two target Memories.\r\n The Memory of which the base address will be modified must not be currently be used by the DMA Stream\r\n (ie. if the DMA Stream is currently transferring from Memory 1 then you can only modify base address\r\n of target Memory 0 and vice versa).\r\n To check this condition, it is recommended to use the function DMA_GetCurrentMemoryTarget() which\r\n returns the index of the Memory target currently in use by the DMA Stream.\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n \r\n/**\r\n * @brief Configures, when the DMAy Streamx is disabled, the double buffer mode \r\n * and the current memory target.\r\n * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0\r\n * to 7 to select the DMA Stream.\r\n * @param Memory1BaseAddr: the base address of the second buffer (Memory 1) \r\n * @param DMA_CurrentMemory: specifies which memory will be first buffer for\r\n * the transactions when the Stream will be enabled. \r\n * This parameter can be one of the following values:\r\n * @arg DMA_Memory_0: Memory 0 is the current buffer.\r\n * @arg DMA_Memory_1: Memory 1 is the current buffer. \r\n * \r\n * @note Memory0BaseAddr is set by the DMA structure configuration in DMA_Init().\r\n * \r\n * @retval None\r\n */\r\nvoid DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,\r\n uint32_t DMA_CurrentMemory)\r\n{ \r\n /* Check the parameters */\r\n assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));\r\n assert_param(IS_DMA_CURRENT_MEM(DMA_CurrentMemory));\r\n\r\n if (DMA_CurrentMemory != DMA_Memory_0)\r\n {\r\n /* Set Memory 1 as current memory address */\r\n DMAy_Streamx->CR |= (uint32_t)(DMA_SxCR_CT); \r\n }\r\n else\r\n {\r\n /* Set Memory 0 as current memory address */\r\n DMAy_Streamx->CR &= ~(uint32_t)(DMA_SxCR_CT); \r\n }\r\n\r\n /* Write to DMAy Streamx M1AR */\r\n DMAy_Streamx->M1AR = Memory1BaseAddr;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the double buffer mode for the selected DMA stream.\r\n * @note This function can be called only when the DMA Stream is disabled. \r\n * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0\r\n * to 7 to select the DMA Stream.\r\n * @param NewState: new state of the DMAy Streamx double buffer mode. \r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState)\r\n{ \r\n /* Check the parameters */\r\n assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n /* Configure the Double Buffer mode */\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the Double buffer mode */\r\n DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_DBM;\r\n }\r\n else\r\n {\r\n /* Disable the Double buffer mode */\r\n DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_DBM;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Configures the Memory address for the next buffer transfer in double\r\n * buffer mode (for dynamic use). This function can be called when the\r\n * DMA Stream is enabled and when the transfer is ongoing. \r\n * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0\r\n * to 7 to select the DMA Stream.\r\n * @param MemoryBaseAddr: The base address of the target memory buffer\r\n * @param DMA_MemoryTarget: Next memory target to be used. \r\n * This parameter can be one of the following values:\r\n * @arg DMA_Memory_0: To use the memory address 0\r\n * @arg DMA_Memory_1: To use the memory address 1\r\n * \r\n * @note It is not allowed to modify the Base Address of a target Memory when\r\n * this target is involved in the current transfer. ie. If the DMA Stream\r\n * is currently transferring to/from Memory 1, then it not possible to\r\n * modify Base address of Memory 1, but it is possible to modify Base\r\n * address of Memory 0.\r\n * To know which Memory is currently used, you can use the function\r\n * DMA_GetCurrentMemoryTarget(). \r\n * \r\n * @retval None\r\n */\r\nvoid DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,\r\n uint32_t DMA_MemoryTarget)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));\r\n assert_param(IS_DMA_CURRENT_MEM(DMA_MemoryTarget));\r\n \r\n /* Check the Memory target to be configured */\r\n if (DMA_MemoryTarget != DMA_Memory_0)\r\n {\r\n /* Write to DMAy Streamx M1AR */\r\n DMAy_Streamx->M1AR = MemoryBaseAddr; \r\n } \r\n else\r\n {\r\n /* Write to DMAy Streamx M0AR */\r\n DMAy_Streamx->M0AR = MemoryBaseAddr; \r\n }\r\n}\r\n\r\n/**\r\n * @brief Returns the current memory target used by double buffer transfer.\r\n * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0\r\n * to 7 to select the DMA Stream.\r\n * @retval The memory target number: 0 for Memory0 or 1 for Memory1. \r\n */\r\nuint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx)\r\n{\r\n uint32_t tmp = 0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));\r\n\r\n /* Get the current memory target */\r\n if ((DMAy_Streamx->CR & DMA_SxCR_CT) != 0)\r\n {\r\n /* Current memory buffer used is Memory 1 */\r\n tmp = 1;\r\n } \r\n else\r\n {\r\n /* Current memory buffer used is Memory 0 */\r\n tmp = 0; \r\n }\r\n return tmp;\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup DMA_Group4 Interrupts and flags management functions\r\n * @brief Interrupts and flags management functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Interrupts and flags management functions\r\n =============================================================================== \r\n\r\n This subsection provides functions allowing to\r\n - Check the DMA enable status\r\n - Check the FIFO status \r\n - Configure the DMA Interrupts sources and check or clear the flags or pending bits status. \r\n \r\n 1. DMA Enable status:\r\n After configuring the DMA Stream (DMA_Init() function) and enabling the stream,\r\n it is recommended to check (or wait until) the DMA Stream is effectively enabled.\r\n A Stream may remain disabled if a configuration parameter is wrong.\r\n After disabling a DMA Stream, it is also recommended to check (or wait until) the DMA\r\n Stream is effectively disabled. If a Stream is disabled while a data transfer is ongoing, \r\n the current data will be transferred and the Stream will be effectively disabled only after\r\n this data transfer completion.\r\n To monitor this state it is possible to use the following function:\r\n - FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx); \r\n \r\n 2. FIFO Status:\r\n It is possible to monitor the FIFO status when a transfer is ongoing using the following \r\n function:\r\n - uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx); \r\n \r\n 3. DMA Interrupts and Flags:\r\n The user should identify which mode will be used in his application to manage the\r\n DMA controller events: Polling mode or Interrupt mode. \r\n \r\n Polling Mode\r\n =============\r\n Each DMA stream can be managed through 4 event Flags:\r\n (x : DMA Stream number )\r\n 1. DMA_FLAG_FEIFx : to indicate that a FIFO Mode Transfer Error event occurred.\r\n 2. DMA_FLAG_DMEIFx : to indicate that a Direct Mode Transfer Error event occurred.\r\n 3. DMA_FLAG_TEIFx : to indicate that a Transfer Error event occurred.\r\n 4. DMA_FLAG_HTIFx : to indicate that a Half-Transfer Complete event occurred.\r\n 5. DMA_FLAG_TCIFx : to indicate that a Transfer Complete event occurred . \r\n\r\n In this Mode it is advised to use the following functions:\r\n - FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);\r\n - void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);\r\n\r\n Interrupt Mode\r\n ===============\r\n Each DMA Stream can be managed through 4 Interrupts:\r\n\r\n Interrupt Source\r\n ----------------\r\n 1. DMA_IT_FEIFx : specifies the interrupt source for the FIFO Mode Transfer Error event.\r\n 2. DMA_IT_DMEIFx : specifies the interrupt source for the Direct Mode Transfer Error event.\r\n 3. DMA_IT_TEIFx : specifies the interrupt source for the Transfer Error event.\r\n 4. DMA_IT_HTIFx : specifies the interrupt source for the Half-Transfer Complete event.\r\n 5. DMA_IT_TCIFx : specifies the interrupt source for the a Transfer Complete event. \r\n \r\n In this Mode it is advised to use the following functions:\r\n - void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);\r\n - ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);\r\n - void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Returns the status of EN bit for the specified DMAy Streamx.\r\n * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0\r\n * to 7 to select the DMA Stream.\r\n * \r\n * @note After configuring the DMA Stream (DMA_Init() function) and enabling\r\n * the stream, it is recommended to check (or wait until) the DMA Stream\r\n * is effectively enabled. A Stream may remain disabled if a configuration\r\n * parameter is wrong.\r\n * After disabling a DMA Stream, it is also recommended to check (or wait \r\n * until) the DMA Stream is effectively disabled. If a Stream is disabled\r\n * while a data transfer is ongoing, the current data will be transferred\r\n * and the Stream will be effectively disabled only after the transfer\r\n * of this single data is finished. \r\n * \r\n * @retval Current state of the DMAy Streamx (ENABLE or DISABLE).\r\n */\r\nFunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx)\r\n{\r\n FunctionalState state = DISABLE;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));\r\n\r\n if ((DMAy_Streamx->CR & (uint32_t)DMA_SxCR_EN) != 0)\r\n {\r\n /* The selected DMAy Streamx EN bit is set (DMA is still transferring) */\r\n state = ENABLE;\r\n }\r\n else\r\n {\r\n /* The selected DMAy Streamx EN bit is cleared (DMA is disabled and \r\n all transfers are complete) */\r\n state = DISABLE;\r\n }\r\n return state;\r\n}\r\n\r\n/**\r\n * @brief Returns the current DMAy Streamx FIFO filled level.\r\n * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 \r\n * to 7 to select the DMA Stream.\r\n * @retval The FIFO filling state.\r\n * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full \r\n * and not empty.\r\n * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.\r\n * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.\r\n * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.\r\n * - DMA_FIFOStatus_Empty: when FIFO is empty\r\n * - DMA_FIFOStatus_Full: when FIFO is full\r\n */\r\nuint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx)\r\n{\r\n uint32_t tmpreg = 0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));\r\n \r\n /* Get the FIFO level bits */\r\n tmpreg = (uint32_t)((DMAy_Streamx->FCR & DMA_SxFCR_FS));\r\n \r\n return tmpreg;\r\n}\r\n\r\n/**\r\n * @brief Checks whether the specified DMAy Streamx flag is set or not.\r\n * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0\r\n * to 7 to select the DMA Stream.\r\n * @param DMA_FLAG: specifies the flag to check.\r\n * This parameter can be one of the following values:\r\n * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag\r\n * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag\r\n * @arg DMA_FLAG_TEIFx: Streamx transfer error flag\r\n * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag\r\n * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag\r\n * Where x can be 0 to 7 to select the DMA Stream.\r\n * @retval The new state of DMA_FLAG (SET or RESET).\r\n */\r\nFlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG)\r\n{\r\n FlagStatus bitstatus = RESET;\r\n DMA_TypeDef* DMAy;\r\n uint32_t tmpreg = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));\r\n assert_param(IS_DMA_GET_FLAG(DMA_FLAG));\r\n\r\n /* Determine the DMA to which belongs the stream */\r\n if (DMAy_Streamx < DMA2_Stream0)\r\n {\r\n /* DMAy_Streamx belongs to DMA1 */\r\n DMAy = DMA1; \r\n } \r\n else \r\n {\r\n /* DMAy_Streamx belongs to DMA2 */\r\n DMAy = DMA2; \r\n }\r\n\r\n /* Check if the flag is in HISR or LISR */\r\n if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET)\r\n {\r\n /* Get DMAy HISR register value */\r\n tmpreg = DMAy->HISR;\r\n }\r\n else\r\n {\r\n /* Get DMAy LISR register value */\r\n tmpreg = DMAy->LISR;\r\n } \r\n \r\n /* Mask the reserved bits */\r\n tmpreg &= (uint32_t)RESERVED_MASK;\r\n\r\n /* Check the status of the specified DMA flag */\r\n if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)\r\n {\r\n /* DMA_FLAG is set */\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n /* DMA_FLAG is reset */\r\n bitstatus = RESET;\r\n }\r\n\r\n /* Return the DMA_FLAG status */\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @brief Clears the DMAy Streamx's pending flags.\r\n * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0\r\n * to 7 to select the DMA Stream.\r\n * @param DMA_FLAG: specifies the flag to clear.\r\n * This parameter can be any combination of the following values:\r\n * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag\r\n * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag\r\n * @arg DMA_FLAG_TEIFx: Streamx transfer error flag\r\n * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag\r\n * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag\r\n * Where x can be 0 to 7 to select the DMA Stream. \r\n * @retval None\r\n */\r\nvoid DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG)\r\n{\r\n DMA_TypeDef* DMAy;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));\r\n assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));\r\n\r\n /* Determine the DMA to which belongs the stream */\r\n if (DMAy_Streamx < DMA2_Stream0)\r\n {\r\n /* DMAy_Streamx belongs to DMA1 */\r\n DMAy = DMA1; \r\n } \r\n else \r\n {\r\n /* DMAy_Streamx belongs to DMA2 */\r\n DMAy = DMA2; \r\n }\r\n\r\n /* Check if LIFCR or HIFCR register is targeted */\r\n if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET)\r\n {\r\n /* Set DMAy HIFCR register clear flag bits */\r\n DMAy->HIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK);\r\n }\r\n else \r\n {\r\n /* Set DMAy LIFCR register clear flag bits */\r\n DMAy->LIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK);\r\n } \r\n}\r\n\r\n/**\r\n * @brief Enables or disables the specified DMAy Streamx interrupts.\r\n * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0\r\n * to 7 to select the DMA Stream.\r\n * @param DMA_IT: specifies the DMA interrupt sources to be enabled or disabled. \r\n * This parameter can be any combination of the following values:\r\n * @arg DMA_IT_TC: Transfer complete interrupt mask\r\n * @arg DMA_IT_HT: Half transfer complete interrupt mask\r\n * @arg DMA_IT_TE: Transfer error interrupt mask\r\n * @arg DMA_IT_FE: FIFO error interrupt mask\r\n * @param NewState: new state of the specified DMA interrupts.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));\r\n assert_param(IS_DMA_CONFIG_IT(DMA_IT));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n /* Check if the DMA_IT parameter contains a FIFO interrupt */\r\n if ((DMA_IT & DMA_IT_FE) != 0)\r\n {\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected DMA FIFO interrupts */\r\n DMAy_Streamx->FCR |= (uint32_t)DMA_IT_FE;\r\n } \r\n else \r\n {\r\n /* Disable the selected DMA FIFO interrupts */\r\n DMAy_Streamx->FCR &= ~(uint32_t)DMA_IT_FE; \r\n }\r\n }\r\n\r\n /* Check if the DMA_IT parameter contains a Transfer interrupt */\r\n if (DMA_IT != DMA_IT_FE)\r\n {\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected DMA transfer interrupts */\r\n DMAy_Streamx->CR |= (uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK);\r\n }\r\n else\r\n {\r\n /* Disable the selected DMA transfer interrupts */\r\n DMAy_Streamx->CR &= ~(uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK);\r\n } \r\n }\r\n}\r\n\r\n/**\r\n * @brief Checks whether the specified DMAy Streamx interrupt has occurred or not.\r\n * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0\r\n * to 7 to select the DMA Stream.\r\n * @param DMA_IT: specifies the DMA interrupt source to check.\r\n * This parameter can be one of the following values:\r\n * @arg DMA_IT_TCIFx: Streamx transfer complete interrupt\r\n * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt\r\n * @arg DMA_IT_TEIFx: Streamx transfer error interrupt\r\n * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt\r\n * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt\r\n * Where x can be 0 to 7 to select the DMA Stream.\r\n * @retval The new state of DMA_IT (SET or RESET).\r\n */\r\nITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT)\r\n{\r\n ITStatus bitstatus = RESET;\r\n DMA_TypeDef* DMAy;\r\n uint32_t tmpreg = 0, enablestatus = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));\r\n assert_param(IS_DMA_GET_IT(DMA_IT));\r\n \r\n /* Determine the DMA to which belongs the stream */\r\n if (DMAy_Streamx < DMA2_Stream0)\r\n {\r\n /* DMAy_Streamx belongs to DMA1 */\r\n DMAy = DMA1; \r\n } \r\n else \r\n {\r\n /* DMAy_Streamx belongs to DMA2 */\r\n DMAy = DMA2; \r\n }\r\n\r\n /* Check if the interrupt enable bit is in the CR or FCR register */\r\n if ((DMA_IT & TRANSFER_IT_MASK) != (uint32_t)RESET)\r\n {\r\n /* Get the interrupt enable position mask in CR register */\r\n tmpreg = (uint32_t)((DMA_IT >> 11) & TRANSFER_IT_ENABLE_MASK); \r\n \r\n /* Check the enable bit in CR register */\r\n enablestatus = (uint32_t)(DMAy_Streamx->CR & tmpreg);\r\n }\r\n else \r\n {\r\n /* Check the enable bit in FCR register */\r\n enablestatus = (uint32_t)(DMAy_Streamx->FCR & DMA_IT_FE); \r\n }\r\n \r\n /* Check if the interrupt pending flag is in LISR or HISR */\r\n if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET)\r\n {\r\n /* Get DMAy HISR register value */\r\n tmpreg = DMAy->HISR ;\r\n }\r\n else\r\n {\r\n /* Get DMAy LISR register value */\r\n tmpreg = DMAy->LISR ;\r\n } \r\n\r\n /* mask all reserved bits */\r\n tmpreg &= (uint32_t)RESERVED_MASK;\r\n\r\n /* Check the status of the specified DMA interrupt */\r\n if (((tmpreg & DMA_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))\r\n {\r\n /* DMA_IT is set */\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n /* DMA_IT is reset */\r\n bitstatus = RESET;\r\n }\r\n\r\n /* Return the DMA_IT status */\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @brief Clears the DMAy Streamx's interrupt pending bits.\r\n * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0\r\n * to 7 to select the DMA Stream.\r\n * @param DMA_IT: specifies the DMA interrupt pending bit to clear.\r\n * This parameter can be any combination of the following values:\r\n * @arg DMA_IT_TCIFx: Streamx transfer complete interrupt\r\n * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt\r\n * @arg DMA_IT_TEIFx: Streamx transfer error interrupt\r\n * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt\r\n * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt\r\n * Where x can be 0 to 7 to select the DMA Stream.\r\n * @retval None\r\n */\r\nvoid DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT)\r\n{\r\n DMA_TypeDef* DMAy;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));\r\n assert_param(IS_DMA_CLEAR_IT(DMA_IT));\r\n\r\n /* Determine the DMA to which belongs the stream */\r\n if (DMAy_Streamx < DMA2_Stream0)\r\n {\r\n /* DMAy_Streamx belongs to DMA1 */\r\n DMAy = DMA1; \r\n } \r\n else \r\n {\r\n /* DMAy_Streamx belongs to DMA2 */\r\n DMAy = DMA2; \r\n }\r\n\r\n /* Check if LIFCR or HIFCR register is targeted */\r\n if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET)\r\n {\r\n /* Set DMAy HIFCR register clear interrupt bits */\r\n DMAy->HIFCR = (uint32_t)(DMA_IT & RESERVED_MASK);\r\n }\r\n else \r\n {\r\n /* Set DMAy LIFCR register clear interrupt bits */\r\n DMAy->LIFCR = (uint32_t)(DMA_IT & RESERVED_MASK);\r\n } \r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_exti.c\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file provides firmware functions to manage the following \r\n * functionalities of the EXTI peripheral: \r\n * - Initialization and Configuration\r\n * - Interrupts and flags management\r\n *\r\n * @verbatim \r\n * \r\n * ===================================================================\r\n * EXTI features\r\n * ===================================================================\r\n * \r\n * External interrupt/event lines are mapped as following:\r\n * 1- All available GPIO pins are connected to the 16 external \r\n * interrupt/event lines from EXTI0 to EXTI15.\r\n * 2- EXTI line 16 is connected to the PVD Output\r\n * 3- EXTI line 17 is connected to the RTC Alarm event\r\n * 4- EXTI line 18 is connected to the USB OTG FS Wakeup from suspend event \r\n * 5- EXTI line 19 is connected to the Ethernet Wakeup event\r\n * 6- EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event \r\n * 7- EXTI line 21 is connected to the RTC Tamper and Time Stamp events \r\n * 8- EXTI line 22 is connected to the RTC Wakeup event\r\n * \r\n * ===================================================================\r\n * How to use this driver\r\n * =================================================================== \r\n * \r\n * In order to use an I/O pin as an external interrupt source, follow\r\n * steps below:\r\n * 1- Configure the I/O in input mode using GPIO_Init()\r\n * 2- Select the input source pin for the EXTI line using SYSCFG_EXTILineConfig()\r\n * 3- Select the mode(interrupt, event) and configure the trigger \r\n * selection (Rising, falling or both) using EXTI_Init()\r\n * 4- Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init()\r\n * \r\n * @note SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx\r\n * registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);\r\n * \r\n * @endverbatim \r\n *\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx_exti.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @defgroup EXTI \r\n * @brief EXTI driver modules\r\n * @{\r\n */\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n\r\n#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup EXTI_Private_Functions\r\n * @{\r\n */\r\n\r\n/** @defgroup EXTI_Group1 Initialization and Configuration functions\r\n * @brief Initialization and Configuration functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Initialization and Configuration functions\r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Deinitializes the EXTI peripheral registers to their default reset values.\r\n * @param None\r\n * @retval None\r\n */\r\nvoid EXTI_DeInit(void)\r\n{\r\n EXTI->IMR = 0x00000000;\r\n EXTI->EMR = 0x00000000;\r\n EXTI->RTSR = 0x00000000;\r\n EXTI->FTSR = 0x00000000;\r\n EXTI->PR = 0x007FFFFF;\r\n}\r\n\r\n/**\r\n * @brief Initializes the EXTI peripheral according to the specified\r\n * parameters in the EXTI_InitStruct.\r\n * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure\r\n * that contains the configuration information for the EXTI peripheral.\r\n * @retval None\r\n */\r\nvoid EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)\r\n{\r\n uint32_t tmp = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));\r\n assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));\r\n assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); \r\n assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));\r\n\r\n tmp = (uint32_t)EXTI_BASE;\r\n \r\n if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)\r\n {\r\n /* Clear EXTI line configuration */\r\n EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;\r\n EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;\r\n \r\n tmp += EXTI_InitStruct->EXTI_Mode;\r\n\r\n *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;\r\n\r\n /* Clear Rising Falling edge configuration */\r\n EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;\r\n EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;\r\n \r\n /* Select the trigger for the selected external interrupts */\r\n if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)\r\n {\r\n /* Rising Falling edge */\r\n EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;\r\n EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;\r\n }\r\n else\r\n {\r\n tmp = (uint32_t)EXTI_BASE;\r\n tmp += EXTI_InitStruct->EXTI_Trigger;\r\n\r\n *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;\r\n }\r\n }\r\n else\r\n {\r\n tmp += EXTI_InitStruct->EXTI_Mode;\r\n\r\n /* Disable the selected external lines */\r\n *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Fills each EXTI_InitStruct member with its reset value.\r\n * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will\r\n * be initialized.\r\n * @retval None\r\n */\r\nvoid EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)\r\n{\r\n EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;\r\n EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;\r\n EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;\r\n EXTI_InitStruct->EXTI_LineCmd = DISABLE;\r\n}\r\n\r\n/**\r\n * @brief Generates a Software interrupt on selected EXTI line.\r\n * @param EXTI_Line: specifies the EXTI line on which the software interrupt\r\n * will be generated.\r\n * This parameter can be any combination of EXTI_Linex where x can be (0..22)\r\n * @retval None\r\n */\r\nvoid EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_EXTI_LINE(EXTI_Line));\r\n \r\n EXTI->SWIER |= EXTI_Line;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup EXTI_Group2 Interrupts and flags management functions\r\n * @brief Interrupts and flags management functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Interrupts and flags management functions\r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Checks whether the specified EXTI line flag is set or not.\r\n * @param EXTI_Line: specifies the EXTI line flag to check.\r\n * This parameter can be EXTI_Linex where x can be(0..22)\r\n * @retval The new state of EXTI_Line (SET or RESET).\r\n */\r\nFlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)\r\n{\r\n FlagStatus bitstatus = RESET;\r\n /* Check the parameters */\r\n assert_param(IS_GET_EXTI_LINE(EXTI_Line));\r\n \r\n if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)\r\n {\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n bitstatus = RESET;\r\n }\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @brief Clears the EXTI's line pending flags.\r\n * @param EXTI_Line: specifies the EXTI lines flags to clear.\r\n * This parameter can be any combination of EXTI_Linex where x can be (0..22)\r\n * @retval None\r\n */\r\nvoid EXTI_ClearFlag(uint32_t EXTI_Line)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_EXTI_LINE(EXTI_Line));\r\n \r\n EXTI->PR = EXTI_Line;\r\n}\r\n\r\n/**\r\n * @brief Checks whether the specified EXTI line is asserted or not.\r\n * @param EXTI_Line: specifies the EXTI line to check.\r\n * This parameter can be EXTI_Linex where x can be(0..22)\r\n * @retval The new state of EXTI_Line (SET or RESET).\r\n */\r\nITStatus EXTI_GetITStatus(uint32_t EXTI_Line)\r\n{\r\n ITStatus bitstatus = RESET;\r\n uint32_t enablestatus = 0;\r\n /* Check the parameters */\r\n assert_param(IS_GET_EXTI_LINE(EXTI_Line));\r\n \r\n enablestatus = EXTI->IMR & EXTI_Line;\r\n if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))\r\n {\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n bitstatus = RESET;\r\n }\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @brief Clears the EXTI's line pending bits.\r\n * @param EXTI_Line: specifies the EXTI lines to clear.\r\n * This parameter can be any combination of EXTI_Linex where x can be (0..22)\r\n * @retval None\r\n */\r\nvoid EXTI_ClearITPendingBit(uint32_t EXTI_Line)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_EXTI_LINE(EXTI_Line));\r\n \r\n EXTI->PR = EXTI_Line;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash.c", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_flash.c\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file provides firmware functions to manage the following \r\n * functionalities of the FLASH peripheral:\r\n * - FLASH Interface configuration\r\n * - FLASH Memory Programming\r\n * - Option Bytes Programming\r\n * - Interrupts and flags management\r\n * \r\n * @verbatim\r\n * \r\n * ===================================================================\r\n * How to use this driver\r\n * ===================================================================\r\n * \r\n * This driver provides functions to configure and program the FLASH \r\n * memory of all STM32F4xx devices.\r\n * These functions are split in 4 groups:\r\n * \r\n * 1. FLASH Interface configuration functions: this group includes the\r\n * management of the following features:\r\n * - Set the latency\r\n * - Enable/Disable the prefetch buffer\r\n * - Enable/Disable the Instruction cache and the Data cache\r\n * - Reset the Instruction cache and the Data cache\r\n * \r\n * 2. FLASH Memory Programming functions: this group includes all needed\r\n * functions to erase and program the main memory:\r\n * - Lock and Unlock the FLASH interface\r\n * - Erase function: Erase sector, erase all sectors\r\n * - Program functions: byte, half word, word and double word\r\n * \r\n * 3. Option Bytes Programming functions: this group includes all needed\r\n * functions to manage the Option Bytes:\r\n * - Set/Reset the write protection\r\n * - Set the Read protection Level\r\n * - Set the BOR level\r\n * - Program the user Option Bytes\r\n * - Launch the Option Bytes loader\r\n * \r\n * 4. Interrupts and flags management functions: this group \r\n * includes all needed functions to:\r\n * - Enable/Disable the FLASH interrupt sources\r\n * - Get flags status\r\n * - Clear flags\r\n * - Get FLASH operation status\r\n * - Wait for last FLASH operation\r\n * \r\n * @endverbatim\r\n * \r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx_flash.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @defgroup FLASH \r\n * @brief FLASH driver modules\r\n * @{\r\n */ \r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/ \r\n#define SECTOR_MASK ((uint32_t)0xFFFFFF07)\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup FLASH_Private_Functions\r\n * @{\r\n */ \r\n\r\n/** @defgroup FLASH_Group1 FLASH Interface configuration functions\r\n * @brief FLASH Interface configuration functions \r\n *\r\n\r\n@verbatim \r\n ===============================================================================\r\n FLASH Interface configuration functions\r\n ===============================================================================\r\n\r\n This group includes the following functions:\r\n - void FLASH_SetLatency(uint32_t FLASH_Latency)\r\n To correctly read data from FLASH memory, the number of wait states (LATENCY) \r\n must be correctly programmed according to the frequency of the CPU clock \r\n (HCLK) and the supply voltage of the device.\r\n +-------------------------------------------------------------------------------------+ \r\n | Latency | HCLK clock frequency (MHz) |\r\n | |---------------------------------------------------------------------| \r\n | | voltage range | voltage range | voltage range | voltage range |\r\n | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |\r\n |---------------|----------------|----------------|-----------------|-----------------| \r\n |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 |\r\n |---------------|----------------|----------------|-----------------|-----------------| \r\n |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 | \r\n |---------------|----------------|----------------|-----------------|-----------------| \r\n |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 |\r\n |---------------|----------------|----------------|-----------------|-----------------| \r\n |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 |\r\n |---------------|----------------|----------------|-----------------|-----------------| \r\n |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 |\r\n |---------------|----------------|----------------|-----------------|-----------------| \r\n |5WS(6CPU cycle)|120< HCLK <= 168|120< HCLK <= 144|90 < HCLK <= 108 |80 < HCLK <= 96 | \r\n |---------------|----------------|----------------|-----------------|-----------------| \r\n |6WS(7CPU cycle)| NA |144< HCLK <= 168|108 < HCLK <= 120|96 < HCLK <= 112 | \r\n |---------------|----------------|----------------|-----------------|-----------------| \r\n |7WS(8CPU cycle)| NA | NA |120 < HCLK <= 138|112 < HCLK <= 120| \r\n |***************|****************|****************|*****************|*****************|*****************************+\r\n | | voltage range | voltage range | voltage range | voltage range | voltage range 2.7 V - 3.6 V |\r\n | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | with External Vpp = 9V |\r\n |---------------|----------------|----------------|-----------------|-----------------|-----------------------------| \r\n |Max Parallelism| x32 | x16 | x8 | x64 | \r\n |---------------|----------------|----------------|-----------------|-----------------|-----------------------------| \r\n |PSIZE[1:0] | 10 | 01 | 00 | 11 |\r\n +-------------------------------------------------------------------------------------------------------------------+ \r\n @note When VOS bit (in PWR_CR register) is reset to '0, the maximum value of HCLK is 144 MHz.\r\n You can use PWR_MainRegulatorModeConfig() function to set or reset this bit.\r\n \r\n - void FLASH_PrefetchBufferCmd(FunctionalState NewState)\r\n - void FLASH_InstructionCacheCmd(FunctionalState NewState)\r\n - void FLASH_DataCacheCmd(FunctionalState NewState)\r\n - void FLASH_InstructionCacheReset(void)\r\n - void FLASH_DataCacheReset(void)\r\n \r\n The unlock sequence is not needed for these functions.\r\n \r\n@endverbatim\r\n * @{\r\n */\r\n \r\n/**\r\n * @brief Sets the code latency value.\r\n * @param FLASH_Latency: specifies the FLASH Latency value.\r\n * This parameter can be one of the following values:\r\n * @arg FLASH_Latency_0: FLASH Zero Latency cycle\r\n * @arg FLASH_Latency_1: FLASH One Latency cycle\r\n * @arg FLASH_Latency_2: FLASH Two Latency cycles\r\n * @arg FLASH_Latency_3: FLASH Three Latency cycles\r\n * @arg FLASH_Latency_4: FLASH Four Latency cycles \r\n * @arg FLASH_Latency_5: FLASH Five Latency cycles \r\n * @arg FLASH_Latency_6: FLASH Six Latency cycles\r\n * @arg FLASH_Latency_7: FLASH Seven Latency cycles \r\n * @retval None\r\n */\r\nvoid FLASH_SetLatency(uint32_t FLASH_Latency)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FLASH_LATENCY(FLASH_Latency));\r\n \r\n /* Perform Byte access to FLASH_ACR[8:0] to set the Latency value */\r\n *(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)FLASH_Latency;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the Prefetch Buffer.\r\n * @param NewState: new state of the Prefetch Buffer.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid FLASH_PrefetchBufferCmd(FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n /* Enable or disable the Prefetch Buffer */\r\n if(NewState != DISABLE)\r\n {\r\n FLASH->ACR |= FLASH_ACR_PRFTEN;\r\n }\r\n else\r\n {\r\n FLASH->ACR &= (~FLASH_ACR_PRFTEN);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the Instruction Cache feature.\r\n * @param NewState: new state of the Instruction Cache.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid FLASH_InstructionCacheCmd(FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n if(NewState != DISABLE)\r\n {\r\n FLASH->ACR |= FLASH_ACR_ICEN;\r\n }\r\n else\r\n {\r\n FLASH->ACR &= (~FLASH_ACR_ICEN);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the Data Cache feature.\r\n * @param NewState: new state of the Data Cache.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid FLASH_DataCacheCmd(FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n if(NewState != DISABLE)\r\n {\r\n FLASH->ACR |= FLASH_ACR_DCEN;\r\n }\r\n else\r\n {\r\n FLASH->ACR &= (~FLASH_ACR_DCEN);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Resets the Instruction Cache.\r\n * @note This function must be used only when the Instruction Cache is disabled. \r\n * @param None\r\n * @retval None\r\n */\r\nvoid FLASH_InstructionCacheReset(void)\r\n{\r\n FLASH->ACR |= FLASH_ACR_ICRST;\r\n}\r\n\r\n/**\r\n * @brief Resets the Data Cache.\r\n * @note This function must be used only when the Data Cache is disabled. \r\n * @param None\r\n * @retval None\r\n */\r\nvoid FLASH_DataCacheReset(void)\r\n{\r\n FLASH->ACR |= FLASH_ACR_DCRST;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FLASH_Group2 FLASH Memory Programming functions\r\n * @brief FLASH Memory Programming functions\r\n *\r\n@verbatim \r\n ===============================================================================\r\n FLASH Memory Programming functions\r\n =============================================================================== \r\n\r\n This group includes the following functions:\r\n - void FLASH_Unlock(void)\r\n - void FLASH_Lock(void)\r\n - FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange)\r\n - FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)\r\n - FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data)\r\n - FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)\r\n - FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)\r\n - FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)\r\n \r\n Any operation of erase or program should follow these steps:\r\n 1. Call the FLASH_Unlock() function to enable the FLASH control register access\r\n\r\n 2. Call the desired function to erase sector(s) or program data\r\n\r\n 3. Call the FLASH_Lock() function to disable the FLASH control register access\r\n (recommended to protect the FLASH memory against possible unwanted operation)\r\n \r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Unlocks the FLASH control register access\r\n * @param None\r\n * @retval None\r\n */\r\nvoid FLASH_Unlock(void)\r\n{\r\n if((FLASH->CR & FLASH_CR_LOCK) != RESET)\r\n {\r\n /* Authorize the FLASH Registers access */\r\n FLASH->KEYR = FLASH_KEY1;\r\n FLASH->KEYR = FLASH_KEY2;\r\n } \r\n}\r\n\r\n/**\r\n * @brief Locks the FLASH control register access\r\n * @param None\r\n * @retval None\r\n */\r\nvoid FLASH_Lock(void)\r\n{\r\n /* Set the LOCK Bit to lock the FLASH Registers access */\r\n FLASH->CR |= FLASH_CR_LOCK;\r\n}\r\n\r\n/**\r\n * @brief Erases a specified FLASH Sector.\r\n * \r\n * @param FLASH_Sector: The Sector number to be erased.\r\n * This parameter can be a value between FLASH_Sector_0 and FLASH_Sector_11\r\n * \r\n * @param VoltageRange: The device voltage range which defines the erase parallelism. \r\n * This parameter can be one of the following values:\r\n * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, \r\n * the operation will be done by byte (8-bit) \r\n * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,\r\n * the operation will be done by half word (16-bit)\r\n * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,\r\n * the operation will be done by word (32-bit)\r\n * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, \r\n * the operation will be done by double word (64-bit)\r\n * \r\n * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,\r\n * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.\r\n */\r\nFLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange)\r\n{\r\n uint32_t tmp_psize = 0x0;\r\n FLASH_Status status = FLASH_COMPLETE;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_FLASH_SECTOR(FLASH_Sector));\r\n assert_param(IS_VOLTAGERANGE(VoltageRange));\r\n \r\n if(VoltageRange == VoltageRange_1)\r\n {\r\n tmp_psize = FLASH_PSIZE_BYTE;\r\n }\r\n else if(VoltageRange == VoltageRange_2)\r\n {\r\n tmp_psize = FLASH_PSIZE_HALF_WORD;\r\n }\r\n else if(VoltageRange == VoltageRange_3)\r\n {\r\n tmp_psize = FLASH_PSIZE_WORD;\r\n }\r\n else\r\n {\r\n tmp_psize = FLASH_PSIZE_DOUBLE_WORD;\r\n }\r\n /* Wait for last operation to be completed */\r\n status = FLASH_WaitForLastOperation();\r\n \r\n if(status == FLASH_COMPLETE)\r\n { \r\n /* if the previous operation is completed, proceed to erase the sector */\r\n FLASH->CR &= CR_PSIZE_MASK;\r\n FLASH->CR |= tmp_psize;\r\n FLASH->CR &= SECTOR_MASK;\r\n FLASH->CR |= FLASH_CR_SER | FLASH_Sector;\r\n FLASH->CR |= FLASH_CR_STRT;\r\n \r\n /* Wait for last operation to be completed */\r\n status = FLASH_WaitForLastOperation();\r\n \r\n /* if the erase operation is completed, disable the SER Bit */\r\n FLASH->CR &= (~FLASH_CR_SER);\r\n FLASH->CR &= SECTOR_MASK; \r\n }\r\n /* Return the Erase Status */\r\n return status;\r\n}\r\n\r\n/**\r\n * @brief Erases all FLASH Sectors.\r\n * \r\n * @param VoltageRange: The device voltage range which defines the erase parallelism. \r\n * This parameter can be one of the following values:\r\n * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, \r\n * the operation will be done by byte (8-bit) \r\n * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,\r\n * the operation will be done by half word (16-bit)\r\n * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,\r\n * the operation will be done by word (32-bit)\r\n * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, \r\n * the operation will be done by double word (64-bit)\r\n * \r\n * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,\r\n * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.\r\n */\r\nFLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)\r\n{\r\n uint32_t tmp_psize = 0x0;\r\n FLASH_Status status = FLASH_COMPLETE;\r\n \r\n /* Wait for last operation to be completed */\r\n status = FLASH_WaitForLastOperation();\r\n assert_param(IS_VOLTAGERANGE(VoltageRange));\r\n \r\n if(VoltageRange == VoltageRange_1)\r\n {\r\n tmp_psize = FLASH_PSIZE_BYTE;\r\n }\r\n else if(VoltageRange == VoltageRange_2)\r\n {\r\n tmp_psize = FLASH_PSIZE_HALF_WORD;\r\n }\r\n else if(VoltageRange == VoltageRange_3)\r\n {\r\n tmp_psize = FLASH_PSIZE_WORD;\r\n }\r\n else\r\n {\r\n tmp_psize = FLASH_PSIZE_DOUBLE_WORD;\r\n } \r\n if(status == FLASH_COMPLETE)\r\n {\r\n /* if the previous operation is completed, proceed to erase all sectors */\r\n FLASH->CR &= CR_PSIZE_MASK;\r\n FLASH->CR |= tmp_psize;\r\n FLASH->CR |= FLASH_CR_MER;\r\n FLASH->CR |= FLASH_CR_STRT;\r\n \r\n /* Wait for last operation to be completed */\r\n status = FLASH_WaitForLastOperation();\r\n\r\n /* if the erase operation is completed, disable the MER Bit */\r\n FLASH->CR &= (~FLASH_CR_MER);\r\n\r\n } \r\n /* Return the Erase Status */\r\n return status;\r\n}\r\n\r\n/**\r\n * @brief Programs a double word (64-bit) at a specified address.\r\n * @note This function must be used when the device voltage range is from\r\n * 2.7V to 3.6V and an External Vpp is present. \r\n * @param Address: specifies the address to be programmed.\r\n * @param Data: specifies the data to be programmed.\r\n * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,\r\n * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.\r\n */\r\nFLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data)\r\n{\r\n FLASH_Status status = FLASH_COMPLETE;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_FLASH_ADDRESS(Address));\r\n\r\n /* Wait for last operation to be completed */\r\n status = FLASH_WaitForLastOperation();\r\n \r\n if(status == FLASH_COMPLETE)\r\n {\r\n /* if the previous operation is completed, proceed to program the new data */\r\n FLASH->CR &= CR_PSIZE_MASK;\r\n FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;\r\n FLASH->CR |= FLASH_CR_PG;\r\n \r\n *(__IO uint64_t*)Address = Data;\r\n \r\n /* Wait for last operation to be completed */\r\n status = FLASH_WaitForLastOperation();\r\n\r\n /* if the program operation is completed, disable the PG Bit */\r\n FLASH->CR &= (~FLASH_CR_PG);\r\n } \r\n /* Return the Program Status */\r\n return status;\r\n}\r\n\r\n/**\r\n * @brief Programs a word (32-bit) at a specified address.\r\n * @param Address: specifies the address to be programmed.\r\n * This parameter can be any address in Program memory zone or in OTP zone. \r\n * @note This function must be used when the device voltage range is from 2.7V to 3.6V. \r\n * @param Data: specifies the data to be programmed.\r\n * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,\r\n * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.\r\n */\r\nFLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)\r\n{\r\n FLASH_Status status = FLASH_COMPLETE;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_FLASH_ADDRESS(Address));\r\n\r\n /* Wait for last operation to be completed */\r\n status = FLASH_WaitForLastOperation();\r\n \r\n if(status == FLASH_COMPLETE)\r\n {\r\n /* if the previous operation is completed, proceed to program the new data */\r\n FLASH->CR &= CR_PSIZE_MASK;\r\n FLASH->CR |= FLASH_PSIZE_WORD;\r\n FLASH->CR |= FLASH_CR_PG;\r\n \r\n *(__IO uint32_t*)Address = Data;\r\n \r\n /* Wait for last operation to be completed */\r\n status = FLASH_WaitForLastOperation();\r\n\r\n /* if the program operation is completed, disable the PG Bit */\r\n FLASH->CR &= (~FLASH_CR_PG);\r\n } \r\n /* Return the Program Status */\r\n return status;\r\n}\r\n\r\n/**\r\n * @brief Programs a half word (16-bit) at a specified address. \r\n * @note This function must be used when the device voltage range is from 2.1V to 3.6V. \r\n * @param Address: specifies the address to be programmed.\r\n * This parameter can be any address in Program memory zone or in OTP zone. \r\n * @param Data: specifies the data to be programmed.\r\n * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,\r\n * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.\r\n */\r\nFLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)\r\n{\r\n FLASH_Status status = FLASH_COMPLETE;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_FLASH_ADDRESS(Address));\r\n\r\n /* Wait for last operation to be completed */\r\n status = FLASH_WaitForLastOperation();\r\n \r\n if(status == FLASH_COMPLETE)\r\n {\r\n /* if the previous operation is completed, proceed to program the new data */\r\n FLASH->CR &= CR_PSIZE_MASK;\r\n FLASH->CR |= FLASH_PSIZE_HALF_WORD;\r\n FLASH->CR |= FLASH_CR_PG;\r\n \r\n *(__IO uint16_t*)Address = Data;\r\n \r\n /* Wait for last operation to be completed */\r\n status = FLASH_WaitForLastOperation();\r\n\r\n /* if the program operation is completed, disable the PG Bit */\r\n FLASH->CR &= (~FLASH_CR_PG);\r\n } \r\n /* Return the Program Status */\r\n return status;\r\n}\r\n\r\n/**\r\n * @brief Programs a byte (8-bit) at a specified address.\r\n * @note This function can be used within all the device supply voltage ranges. \r\n * @param Address: specifies the address to be programmed.\r\n * This parameter can be any address in Program memory zone or in OTP zone. \r\n * @param Data: specifies the data to be programmed.\r\n * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,\r\n * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.\r\n */\r\nFLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)\r\n{\r\n FLASH_Status status = FLASH_COMPLETE;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_FLASH_ADDRESS(Address));\r\n\r\n /* Wait for last operation to be completed */\r\n status = FLASH_WaitForLastOperation();\r\n \r\n if(status == FLASH_COMPLETE)\r\n {\r\n /* if the previous operation is completed, proceed to program the new data */\r\n FLASH->CR &= CR_PSIZE_MASK;\r\n FLASH->CR |= FLASH_PSIZE_BYTE;\r\n FLASH->CR |= FLASH_CR_PG;\r\n \r\n *(__IO uint8_t*)Address = Data;\r\n \r\n /* Wait for last operation to be completed */\r\n status = FLASH_WaitForLastOperation();\r\n\r\n /* if the program operation is completed, disable the PG Bit */\r\n FLASH->CR &= (~FLASH_CR_PG);\r\n } \r\n\r\n /* Return the Program Status */\r\n return status;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FLASH_Group3 Option Bytes Programming functions\r\n * @brief Option Bytes Programming functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Option Bytes Programming functions\r\n =============================================================================== \r\n \r\n This group includes the following functions:\r\n - void FLASH_OB_Unlock(void)\r\n - void FLASH_OB_Lock(void)\r\n - void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)\r\n - void FLASH_OB_RDPConfig(uint8_t OB_RDP)\r\n - void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)\r\n - void FLASH_OB_BORConfig(uint8_t OB_BOR)\r\n - FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data)\t\t\t\t\t\t\t\r\n - FLASH_Status FLASH_OB_Launch(void)\r\n - uint32_t FLASH_OB_GetUser(void)\t\t\t\t\t\t\r\n - uint8_t FLASH_OB_GetWRP(void)\t\t\t\t\t\t\r\n - uint8_t FLASH_OB_GetRDP(void)\t\t\t\t\t\t\t\r\n - uint8_t FLASH_OB_GetBOR(void)\r\n \r\n Any operation of erase or program should follow these steps:\r\n 1. Call the FLASH_OB_Unlock() function to enable the FLASH option control register access\r\n\r\n 2. Call one or several functions to program the desired Option Bytes:\r\n - void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) => to Enable/Disable \r\n the desired sector write protection\r\n - void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read Protection Level\r\n - void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) => to configure \r\n the user Option Bytes.\r\n - void FLASH_OB_BORConfig(uint8_t OB_BOR) => to set the BOR Level \t\t\t \r\n\r\n 3. Once all needed Option Bytes to be programmed are correctly written, call the\r\n FLASH_OB_Launch() function to launch the Option Bytes programming process.\r\n \r\n @note When changing the IWDG mode from HW to SW or from SW to HW, a system \r\n reset is needed to make the change effective. \r\n\r\n 4. Call the FLASH_OB_Lock() function to disable the FLASH option control register\r\n access (recommended to protect the Option Bytes against possible unwanted operations)\r\n \r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Unlocks the FLASH Option Control Registers access.\r\n * @param None\r\n * @retval None\r\n */\r\nvoid FLASH_OB_Unlock(void)\r\n{\r\n if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)\r\n {\r\n /* Authorizes the Option Byte register programming */\r\n FLASH->OPTKEYR = FLASH_OPT_KEY1;\r\n FLASH->OPTKEYR = FLASH_OPT_KEY2;\r\n } \r\n}\r\n\r\n/**\r\n * @brief Locks the FLASH Option Control Registers access.\r\n * @param None\r\n * @retval None\r\n */\r\nvoid FLASH_OB_Lock(void)\r\n{\r\n /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */\r\n FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the write protection of the desired sectors\r\n * @param OB_WRP: specifies the sector(s) to be write protected or unprotected.\r\n * This parameter can be one of the following values:\r\n * @arg OB_WRP: A value between OB_WRP_Sector0 and OB_WRP_Sector11 \r\n * @arg OB_WRP_Sector_All\r\n * @param Newstate: new state of the Write Protection.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None \r\n */\r\nvoid FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)\r\n{ \r\n FLASH_Status status = FLASH_COMPLETE;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_OB_WRP(OB_WRP));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n status = FLASH_WaitForLastOperation();\r\n\r\n if(status == FLASH_COMPLETE)\r\n { \r\n if(NewState != DISABLE)\r\n {\r\n *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_WRP);\r\n }\r\n else\r\n {\r\n *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_WRP;\r\n }\r\n }\r\n}\r\n\r\n/**\r\n * @brief Sets the read protection level.\r\n * @param OB_RDP: specifies the read protection level.\r\n * This parameter can be one of the following values:\r\n * @arg OB_RDP_Level_0: No protection\r\n * @arg OB_RDP_Level_1: Read protection of the memory\r\n * @arg OB_RDP_Level_2: Full chip protection\r\n * \r\n * !!!Warning!!! When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0\r\n * \r\n * @retval None\r\n */\r\nvoid FLASH_OB_RDPConfig(uint8_t OB_RDP)\r\n{\r\n FLASH_Status status = FLASH_COMPLETE;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_OB_RDP(OB_RDP));\r\n\r\n status = FLASH_WaitForLastOperation();\r\n\r\n if(status == FLASH_COMPLETE)\r\n {\r\n *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = OB_RDP;\r\n\r\n }\r\n}\r\n\r\n/**\r\n * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. \r\n * @param OB_IWDG: Selects the IWDG mode\r\n * This parameter can be one of the following values:\r\n * @arg OB_IWDG_SW: Software IWDG selected\r\n * @arg OB_IWDG_HW: Hardware IWDG selected\r\n * @param OB_STOP: Reset event when entering STOP mode.\r\n * This parameter can be one of the following values:\r\n * @arg OB_STOP_NoRST: No reset generated when entering in STOP\r\n * @arg OB_STOP_RST: Reset generated when entering in STOP\r\n * @param OB_STDBY: Reset event when entering Standby mode.\r\n * This parameter can be one of the following values:\r\n * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY\r\n * @arg OB_STDBY_RST: Reset generated when entering in STANDBY\r\n * @retval None\r\n */\r\nvoid FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)\r\n{\r\n uint8_t optiontmp = 0xFF;\r\n FLASH_Status status = FLASH_COMPLETE; \r\n\r\n /* Check the parameters */\r\n assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));\r\n assert_param(IS_OB_STOP_SOURCE(OB_STOP));\r\n assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));\r\n\r\n /* Wait for last operation to be completed */\r\n status = FLASH_WaitForLastOperation();\r\n \r\n if(status == FLASH_COMPLETE)\r\n { \r\n /* Mask OPTLOCK, OPTSTRT and BOR_LEV bits */\r\n optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0F); \r\n\r\n /* Update User Option Byte */\r\n *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = OB_IWDG | (uint8_t)(OB_STDBY | (uint8_t)(OB_STOP | ((uint8_t)optiontmp))); \r\n } \r\n}\r\n\r\n/**\r\n * @brief Sets the BOR Level. \r\n * @param OB_BOR: specifies the Option Bytes BOR Reset Level.\r\n * This parameter can be one of the following values:\r\n * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V\r\n * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V\r\n * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V\r\n * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V\r\n * @retval None\r\n */\r\nvoid FLASH_OB_BORConfig(uint8_t OB_BOR)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_OB_BOR(OB_BOR));\r\n\r\n /* Set the BOR Level */\r\n *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV);\r\n *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOR;\r\n\r\n}\r\n\r\n/**\r\n * @brief Launch the option byte loading.\r\n * @param None\r\n * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,\r\n * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.\r\n */\r\nFLASH_Status FLASH_OB_Launch(void)\r\n{\r\n FLASH_Status status = FLASH_COMPLETE;\r\n\r\n /* Set the OPTSTRT bit in OPTCR register */\r\n *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT;\r\n\r\n /* Wait for last operation to be completed */\r\n status = FLASH_WaitForLastOperation();\r\n\r\n return status;\r\n}\r\n\r\n/**\r\n * @brief Returns the FLASH User Option Bytes values.\r\n * @param None\r\n * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1)\r\n * and RST_STDBY(Bit2).\r\n */\r\nuint8_t FLASH_OB_GetUser(void)\r\n{\r\n /* Return the User Option Byte */\r\n return (uint8_t)(FLASH->OPTCR >> 5);\r\n}\r\n\r\n/**\r\n * @brief Returns the FLASH Write Protection Option Bytes value.\r\n * @param None\r\n * @retval The FLASH Write Protection Option Bytes value\r\n */\r\nuint16_t FLASH_OB_GetWRP(void)\r\n{\r\n /* Return the FLASH write protection Register value */\r\n return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));\r\n}\r\n\r\n/**\r\n * @brief Returns the FLASH Read Protection level.\r\n * @param None\r\n * @retval FLASH ReadOut Protection Status:\r\n * - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set\r\n * - RESET, when OB_RDP_Level_0 is set\r\n */\r\nFlagStatus FLASH_OB_GetRDP(void)\r\n{\r\n FlagStatus readstatus = RESET;\r\n\r\n if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) != (uint8_t)OB_RDP_Level_0))\r\n {\r\n readstatus = SET;\r\n }\r\n else\r\n {\r\n readstatus = RESET;\r\n }\r\n return readstatus;\r\n}\r\n\r\n/**\r\n * @brief Returns the FLASH BOR level.\r\n * @param None\r\n * @retval The FLASH BOR level:\r\n * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V\r\n * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V\r\n * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V\r\n * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V \r\n */\r\nuint8_t FLASH_OB_GetBOR(void)\r\n{\r\n /* Return the FLASH BOR level */\r\n return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C);\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FLASH_Group4 Interrupts and flags management functions\r\n * @brief Interrupts and flags management functions\r\n *\r\n@verbatim \r\n ===============================================================================\r\n Interrupts and flags management functions\r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Enables or disables the specified FLASH interrupts.\r\n * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled.\r\n * This parameter can be any combination of the following values:\r\n * @arg FLASH_IT_ERR: FLASH Error Interrupt\r\n * @arg FLASH_IT_EOP: FLASH end of operation Interrupt\r\n * @retval None \r\n */\r\nvoid FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FLASH_IT(FLASH_IT)); \r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n if(NewState != DISABLE)\r\n {\r\n /* Enable the interrupt sources */\r\n FLASH->CR |= FLASH_IT;\r\n }\r\n else\r\n {\r\n /* Disable the interrupt sources */\r\n FLASH->CR &= ~(uint32_t)FLASH_IT;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Checks whether the specified FLASH flag is set or not.\r\n * @param FLASH_FLAG: specifies the FLASH flag to check.\r\n * This parameter can be one of the following values:\r\n * @arg FLASH_FLAG_EOP: FLASH End of Operation flag \r\n * @arg FLASH_FLAG_OPERR: FLASH operation Error flag \r\n * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag \r\n * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag\r\n * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag\r\n * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag\r\n * @arg FLASH_FLAG_BSY: FLASH Busy flag\r\n * @retval The new state of FLASH_FLAG (SET or RESET).\r\n */\r\nFlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)\r\n{\r\n FlagStatus bitstatus = RESET;\r\n /* Check the parameters */\r\n assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));\r\n\r\n if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)\r\n {\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n bitstatus = RESET;\r\n }\r\n /* Return the new state of FLASH_FLAG (SET or RESET) */\r\n return bitstatus; \r\n}\r\n\r\n/**\r\n * @brief Clears the FLASH's pending flags.\r\n * @param FLASH_FLAG: specifies the FLASH flags to clear.\r\n * This parameter can be any combination of the following values:\r\n * @arg FLASH_FLAG_EOP: FLASH End of Operation flag \r\n * @arg FLASH_FLAG_OPERR: FLASH operation Error flag \r\n * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag \r\n * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag \r\n * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag\r\n * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag\r\n * @retval None\r\n */\r\nvoid FLASH_ClearFlag(uint32_t FLASH_FLAG)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));\r\n \r\n /* Clear the flags */\r\n FLASH->SR = FLASH_FLAG;\r\n}\r\n\r\n/**\r\n * @brief Returns the FLASH Status.\r\n * @param None\r\n * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,\r\n * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.\r\n */\r\nFLASH_Status FLASH_GetStatus(void)\r\n{\r\n FLASH_Status flashstatus = FLASH_COMPLETE;\r\n \r\n if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) \r\n {\r\n flashstatus = FLASH_BUSY;\r\n }\r\n else \r\n { \r\n if((FLASH->SR & FLASH_FLAG_WRPERR) != (uint32_t)0x00)\r\n { \r\n flashstatus = FLASH_ERROR_WRP;\r\n }\r\n else \r\n {\r\n if((FLASH->SR & (uint32_t)0xEF) != (uint32_t)0x00)\r\n {\r\n flashstatus = FLASH_ERROR_PROGRAM; \r\n }\r\n else\r\n {\r\n if((FLASH->SR & FLASH_FLAG_OPERR) != (uint32_t)0x00)\r\n {\r\n flashstatus = FLASH_ERROR_OPERATION;\r\n }\r\n else\r\n {\r\n flashstatus = FLASH_COMPLETE;\r\n }\r\n }\r\n }\r\n }\r\n /* Return the FLASH Status */\r\n return flashstatus;\r\n}\r\n\r\n/**\r\n * @brief Waits for a FLASH operation to complete.\r\n * @param None\r\n * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,\r\n * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.\r\n */\r\nFLASH_Status FLASH_WaitForLastOperation(void)\r\n{ \r\n __IO FLASH_Status status = FLASH_COMPLETE;\r\n \r\n /* Check for the FLASH Status */\r\n status = FLASH_GetStatus();\r\n\r\n /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.\r\n Even if the FLASH operation fails, the BUSY flag will be reset and an error\r\n flag will be set */\r\n while(status == FLASH_BUSY)\r\n {\r\n status = FLASH_GetStatus();\r\n }\r\n /* Return the operation status */\r\n return status;\r\n}\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_fsmc.c\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file provides firmware functions to manage the following \r\n * functionalities of the FSMC peripheral: \r\n * - Interface with SRAM, PSRAM, NOR and OneNAND memories\r\n * - Interface with NAND memories\r\n * - Interface with 16-bit PC Card compatible memories \r\n * - Interrupts and flags management \r\n * \r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx_fsmc.h\"\r\n#include \"stm32f4xx_rcc.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @defgroup FSMC \r\n * @brief FSMC driver modules\r\n * @{\r\n */ \r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n\r\n/* --------------------- FSMC registers bit mask ---------------------------- */\r\n/* FSMC BCRx Mask */\r\n#define BCR_MBKEN_SET ((uint32_t)0x00000001)\r\n#define BCR_MBKEN_RESET ((uint32_t)0x000FFFFE)\r\n#define BCR_FACCEN_SET ((uint32_t)0x00000040)\r\n\r\n/* FSMC PCRx Mask */\r\n#define PCR_PBKEN_SET ((uint32_t)0x00000004)\r\n#define PCR_PBKEN_RESET ((uint32_t)0x000FFFFB)\r\n#define PCR_ECCEN_SET ((uint32_t)0x00000040)\r\n#define PCR_ECCEN_RESET ((uint32_t)0x000FFFBF)\r\n#define PCR_MEMORYTYPE_NAND ((uint32_t)0x00000008)\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup FSMC_Private_Functions\r\n * @{\r\n */\r\n\r\n/** @defgroup FSMC_Group1 NOR/SRAM Controller functions\r\n * @brief NOR/SRAM Controller functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n NOR/SRAM Controller functions\r\n =============================================================================== \r\n\r\n The following sequence should be followed to configure the FSMC to interface with\r\n SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank:\r\n \r\n 1. Enable the clock for the FSMC and associated GPIOs using the following functions:\r\n RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);\r\n RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);\r\n\r\n 2. FSMC pins configuration \r\n - Connect the involved FSMC pins to AF12 using the following function \r\n GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); \r\n - Configure these FSMC pins in alternate function mode by calling the function\r\n GPIO_Init(); \r\n \r\n 3. Declare a FSMC_NORSRAMInitTypeDef structure, for example:\r\n FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;\r\n and fill the FSMC_NORSRAMInitStructure variable with the allowed values of\r\n the structure member.\r\n \r\n 4. Initialize the NOR/SRAM Controller by calling the function\r\n FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); \r\n\r\n 5. Then enable the NOR/SRAM Bank, for example:\r\n FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE); \r\n\r\n 6. At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank. \r\n \r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default \r\n * reset values.\r\n * @param FSMC_Bank: specifies the FSMC Bank to be used\r\n * This parameter can be one of the following values:\r\n * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 \r\n * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 \r\n * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 \r\n * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 \r\n * @retval None\r\n */\r\nvoid FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)\r\n{\r\n /* Check the parameter */\r\n assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));\r\n \r\n /* FSMC_Bank1_NORSRAM1 */\r\n if(FSMC_Bank == FSMC_Bank1_NORSRAM1)\r\n {\r\n FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; \r\n }\r\n /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */\r\n else\r\n { \r\n FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; \r\n }\r\n FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;\r\n FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; \r\n}\r\n\r\n/**\r\n * @brief Initializes the FSMC NOR/SRAM Banks according to the specified\r\n * parameters in the FSMC_NORSRAMInitStruct.\r\n * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef structure\r\n * that contains the configuration information for the FSMC NOR/SRAM \r\n * specified Banks. \r\n * @retval None\r\n */\r\nvoid FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)\r\n{ \r\n /* Check the parameters */\r\n assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));\r\n assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));\r\n assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));\r\n assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));\r\n assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));\r\n assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));\r\n assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));\r\n assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));\r\n assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));\r\n assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));\r\n assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));\r\n assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));\r\n assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); \r\n assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));\r\n assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));\r\n assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));\r\n assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));\r\n assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));\r\n assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));\r\n assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); \r\n \r\n /* Bank1 NOR/SRAM control register configuration */ \r\n FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = \r\n (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |\r\n FSMC_NORSRAMInitStruct->FSMC_MemoryType |\r\n FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |\r\n FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |\r\n FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |\r\n FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |\r\n FSMC_NORSRAMInitStruct->FSMC_WrapMode |\r\n FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |\r\n FSMC_NORSRAMInitStruct->FSMC_WriteOperation |\r\n FSMC_NORSRAMInitStruct->FSMC_WaitSignal |\r\n FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |\r\n FSMC_NORSRAMInitStruct->FSMC_WriteBurst;\r\n if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)\r\n {\r\n FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_SET;\r\n }\r\n /* Bank1 NOR/SRAM timing register configuration */\r\n FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = \r\n (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |\r\n (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |\r\n (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |\r\n (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |\r\n (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |\r\n (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |\r\n FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;\r\n \r\n \r\n /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */\r\n if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)\r\n {\r\n assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));\r\n assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));\r\n assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));\r\n assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));\r\n assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));\r\n assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));\r\n FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = \r\n (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |\r\n (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|\r\n (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |\r\n (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |\r\n (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |\r\n FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;\r\n }\r\n else\r\n {\r\n FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Fills each FSMC_NORSRAMInitStruct member with its default value.\r\n * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef structure \r\n * which will be initialized.\r\n * @retval None\r\n */\r\nvoid FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)\r\n{ \r\n /* Reset NOR/SRAM Init structure parameters values */\r\n FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;\r\n FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;\r\n FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;\r\n FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;\r\n FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;\r\n FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;\r\n FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;\r\n FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;\r\n FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;\r\n FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;\r\n FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;\r\n FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;\r\n FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;\r\n FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;\r\n FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;\r\n FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;\r\n FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;\r\n FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;\r\n FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;\r\n FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; \r\n FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;\r\n FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;\r\n FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;\r\n FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;\r\n FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;\r\n FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;\r\n FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the specified NOR/SRAM Memory Bank.\r\n * @param FSMC_Bank: specifies the FSMC Bank to be used\r\n * This parameter can be one of the following values:\r\n * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 \r\n * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 \r\n * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 \r\n * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 \r\n * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)\r\n{\r\n assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */\r\n FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_SET;\r\n }\r\n else\r\n {\r\n /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */\r\n FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_RESET;\r\n }\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FSMC_Group2 NAND Controller functions\r\n * @brief NAND Controller functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n NAND Controller functions\r\n =============================================================================== \r\n\r\n The following sequence should be followed to configure the FSMC to interface with\r\n 8-bit or 16-bit NAND memory connected to the NAND Bank:\r\n \r\n 1. Enable the clock for the FSMC and associated GPIOs using the following functions:\r\n RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);\r\n RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);\r\n\r\n 2. FSMC pins configuration \r\n - Connect the involved FSMC pins to AF12 using the following function \r\n GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); \r\n - Configure these FSMC pins in alternate function mode by calling the function\r\n GPIO_Init(); \r\n \r\n 3. Declare a FSMC_NANDInitTypeDef structure, for example:\r\n FSMC_NANDInitTypeDef FSMC_NANDInitStructure;\r\n and fill the FSMC_NANDInitStructure variable with the allowed values of\r\n the structure member.\r\n \r\n 4. Initialize the NAND Controller by calling the function\r\n FSMC_NANDInit(&FSMC_NANDInitStructure); \r\n\r\n 5. Then enable the NAND Bank, for example:\r\n FSMC_NANDCmd(FSMC_Bank3_NAND, ENABLE); \r\n\r\n 6. At this stage you can read/write from/to the memory connected to the NAND Bank. \r\n \r\n@note To enable the Error Correction Code (ECC), you have to use the function\r\n FSMC_NANDECCCmd(FSMC_Bank3_NAND, ENABLE); \r\n and to get the current ECC value you have to use the function\r\n ECCval = FSMC_GetECC(FSMC_Bank3_NAND); \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n \r\n/**\r\n * @brief Deinitializes the FSMC NAND Banks registers to their default reset values.\r\n * @param FSMC_Bank: specifies the FSMC Bank to be used\r\n * This parameter can be one of the following values:\r\n * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r\n * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND \r\n * @retval None\r\n */\r\nvoid FSMC_NANDDeInit(uint32_t FSMC_Bank)\r\n{\r\n /* Check the parameter */\r\n assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));\r\n \r\n if(FSMC_Bank == FSMC_Bank2_NAND)\r\n {\r\n /* Set the FSMC_Bank2 registers to their reset values */\r\n FSMC_Bank2->PCR2 = 0x00000018;\r\n FSMC_Bank2->SR2 = 0x00000040;\r\n FSMC_Bank2->PMEM2 = 0xFCFCFCFC;\r\n FSMC_Bank2->PATT2 = 0xFCFCFCFC; \r\n }\r\n /* FSMC_Bank3_NAND */ \r\n else\r\n {\r\n /* Set the FSMC_Bank3 registers to their reset values */\r\n FSMC_Bank3->PCR3 = 0x00000018;\r\n FSMC_Bank3->SR3 = 0x00000040;\r\n FSMC_Bank3->PMEM3 = 0xFCFCFCFC;\r\n FSMC_Bank3->PATT3 = 0xFCFCFCFC; \r\n } \r\n}\r\n\r\n/**\r\n * @brief Initializes the FSMC NAND Banks according to the specified parameters\r\n * in the FSMC_NANDInitStruct.\r\n * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef structure that\r\n * contains the configuration information for the FSMC NAND specified Banks. \r\n * @retval None\r\n */\r\nvoid FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)\r\n{\r\n uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; \r\n \r\n /* Check the parameters */\r\n assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));\r\n assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));\r\n assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));\r\n assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));\r\n assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));\r\n assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));\r\n assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));\r\n assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));\r\n assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));\r\n assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));\r\n assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));\r\n assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));\r\n assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));\r\n assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));\r\n assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));\r\n \r\n /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */\r\n tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |\r\n PCR_MEMORYTYPE_NAND |\r\n FSMC_NANDInitStruct->FSMC_MemoryDataWidth |\r\n FSMC_NANDInitStruct->FSMC_ECC |\r\n FSMC_NANDInitStruct->FSMC_ECCPageSize |\r\n (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|\r\n (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);\r\n \r\n /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */\r\n tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |\r\n (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r\n (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r\n (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); \r\n \r\n /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */\r\n tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |\r\n (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r\n (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r\n (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);\r\n \r\n if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)\r\n {\r\n /* FSMC_Bank2_NAND registers configuration */\r\n FSMC_Bank2->PCR2 = tmppcr;\r\n FSMC_Bank2->PMEM2 = tmppmem;\r\n FSMC_Bank2->PATT2 = tmppatt;\r\n }\r\n else\r\n {\r\n /* FSMC_Bank3_NAND registers configuration */\r\n FSMC_Bank3->PCR3 = tmppcr;\r\n FSMC_Bank3->PMEM3 = tmppmem;\r\n FSMC_Bank3->PATT3 = tmppatt;\r\n }\r\n}\r\n\r\n\r\n/**\r\n * @brief Fills each FSMC_NANDInitStruct member with its default value.\r\n * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef structure which\r\n * will be initialized.\r\n * @retval None\r\n */\r\nvoid FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)\r\n{ \r\n /* Reset NAND Init structure parameters values */\r\n FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;\r\n FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;\r\n FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;\r\n FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;\r\n FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;\r\n FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;\r\n FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;\r\n FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r\n FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r\n FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r\n FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;\r\n FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r\n FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r\n FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r\n FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;\t \r\n}\r\n\r\n/**\r\n * @brief Enables or disables the specified NAND Memory Bank.\r\n * @param FSMC_Bank: specifies the FSMC Bank to be used\r\n * This parameter can be one of the following values:\r\n * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r\n * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r\n * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)\r\n{\r\n assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */\r\n if(FSMC_Bank == FSMC_Bank2_NAND)\r\n {\r\n FSMC_Bank2->PCR2 |= PCR_PBKEN_SET;\r\n }\r\n else\r\n {\r\n FSMC_Bank3->PCR3 |= PCR_PBKEN_SET;\r\n }\r\n }\r\n else\r\n {\r\n /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */\r\n if(FSMC_Bank == FSMC_Bank2_NAND)\r\n {\r\n FSMC_Bank2->PCR2 &= PCR_PBKEN_RESET;\r\n }\r\n else\r\n {\r\n FSMC_Bank3->PCR3 &= PCR_PBKEN_RESET;\r\n }\r\n }\r\n}\r\n/**\r\n * @brief Enables or disables the FSMC NAND ECC feature.\r\n * @param FSMC_Bank: specifies the FSMC Bank to be used\r\n * This parameter can be one of the following values:\r\n * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r\n * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r\n * @param NewState: new state of the FSMC NAND ECC feature. \r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)\r\n{\r\n assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */\r\n if(FSMC_Bank == FSMC_Bank2_NAND)\r\n {\r\n FSMC_Bank2->PCR2 |= PCR_ECCEN_SET;\r\n }\r\n else\r\n {\r\n FSMC_Bank3->PCR3 |= PCR_ECCEN_SET;\r\n }\r\n }\r\n else\r\n {\r\n /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */\r\n if(FSMC_Bank == FSMC_Bank2_NAND)\r\n {\r\n FSMC_Bank2->PCR2 &= PCR_ECCEN_RESET;\r\n }\r\n else\r\n {\r\n FSMC_Bank3->PCR3 &= PCR_ECCEN_RESET;\r\n }\r\n }\r\n}\r\n\r\n/**\r\n * @brief Returns the error correction code register value.\r\n * @param FSMC_Bank: specifies the FSMC Bank to be used\r\n * This parameter can be one of the following values:\r\n * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r\n * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r\n * @retval The Error Correction Code (ECC) value.\r\n */\r\nuint32_t FSMC_GetECC(uint32_t FSMC_Bank)\r\n{\r\n uint32_t eccval = 0x00000000;\r\n \r\n if(FSMC_Bank == FSMC_Bank2_NAND)\r\n {\r\n /* Get the ECCR2 register value */\r\n eccval = FSMC_Bank2->ECCR2;\r\n }\r\n else\r\n {\r\n /* Get the ECCR3 register value */\r\n eccval = FSMC_Bank3->ECCR3;\r\n }\r\n /* Return the error correction code value */\r\n return(eccval);\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FSMC_Group3 PCCARD Controller functions\r\n * @brief PCCARD Controller functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n PCCARD Controller functions\r\n =============================================================================== \r\n\r\n The following sequence should be followed to configure the FSMC to interface with\r\n 16-bit PC Card compatible memory connected to the PCCARD Bank:\r\n \r\n 1. Enable the clock for the FSMC and associated GPIOs using the following functions:\r\n RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);\r\n RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);\r\n\r\n 2. FSMC pins configuration \r\n - Connect the involved FSMC pins to AF12 using the following function \r\n GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); \r\n - Configure these FSMC pins in alternate function mode by calling the function\r\n GPIO_Init(); \r\n \r\n 3. Declare a FSMC_PCCARDInitTypeDef structure, for example:\r\n FSMC_PCCARDInitTypeDef FSMC_PCCARDInitStructure;\r\n and fill the FSMC_PCCARDInitStructure variable with the allowed values of\r\n the structure member.\r\n \r\n 4. Initialize the PCCARD Controller by calling the function\r\n FSMC_PCCARDInit(&FSMC_PCCARDInitStructure); \r\n\r\n 5. Then enable the PCCARD Bank:\r\n FSMC_PCCARDCmd(ENABLE); \r\n\r\n 6. At this stage you can read/write from/to the memory connected to the PCCARD Bank. \r\n \r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values.\r\n * @param None \r\n * @retval None\r\n */\r\nvoid FSMC_PCCARDDeInit(void)\r\n{\r\n /* Set the FSMC_Bank4 registers to their reset values */\r\n FSMC_Bank4->PCR4 = 0x00000018; \r\n FSMC_Bank4->SR4 = 0x00000000;\t\r\n FSMC_Bank4->PMEM4 = 0xFCFCFCFC;\r\n FSMC_Bank4->PATT4 = 0xFCFCFCFC;\r\n FSMC_Bank4->PIO4 = 0xFCFCFCFC;\r\n}\r\n\r\n/**\r\n * @brief Initializes the FSMC PCCARD Bank according to the specified parameters\r\n * in the FSMC_PCCARDInitStruct.\r\n * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef structure\r\n * that contains the configuration information for the FSMC PCCARD Bank. \r\n * @retval None\r\n */\r\nvoid FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));\r\n assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));\r\n assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));\r\n \r\n assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));\r\n assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));\r\n assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));\r\n assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));\r\n \r\n assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));\r\n assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));\r\n assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));\r\n assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));\r\n assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));\r\n assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));\r\n assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));\r\n assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));\r\n \r\n /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */\r\n FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |\r\n FSMC_MemoryDataWidth_16b | \r\n (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |\r\n (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);\r\n \r\n /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */\r\n FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |\r\n (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r\n (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r\n (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); \r\n \r\n /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */\r\n FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |\r\n (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r\n (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r\n (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);\t\r\n \r\n /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */\r\n FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |\r\n (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r\n (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r\n (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); \r\n}\r\n\r\n/**\r\n * @brief Fills each FSMC_PCCARDInitStruct member with its default value.\r\n * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef structure\r\n * which will be initialized.\r\n * @retval None\r\n */\r\nvoid FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)\r\n{\r\n /* Reset PCCARD Init structure parameters values */\r\n FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;\r\n FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;\r\n FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;\r\n FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r\n FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r\n FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r\n FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;\r\n FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r\n FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r\n FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r\n FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;\t\r\n FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r\n FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r\n FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r\n FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the PCCARD Memory Bank.\r\n * @param NewState: new state of the PCCARD Memory Bank. \r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid FSMC_PCCARDCmd(FunctionalState NewState)\r\n{\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */\r\n FSMC_Bank4->PCR4 |= PCR_PBKEN_SET;\r\n }\r\n else\r\n {\r\n /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */\r\n FSMC_Bank4->PCR4 &= PCR_PBKEN_RESET;\r\n }\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup FSMC_Group4 Interrupts and flags management functions\r\n * @brief Interrupts and flags management functions\r\n *\r\n@verbatim \r\n ===============================================================================\r\n Interrupts and flags management functions\r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Enables or disables the specified FSMC interrupts.\r\n * @param FSMC_Bank: specifies the FSMC Bank to be used\r\n * This parameter can be one of the following values:\r\n * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r\n * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r\n * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r\n * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.\r\n * This parameter can be any combination of the following values:\r\n * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. \r\n * @arg FSMC_IT_Level: Level edge detection interrupt.\r\n * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.\r\n * @param NewState: new state of the specified FSMC interrupts.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)\r\n{\r\n assert_param(IS_FSMC_IT_BANK(FSMC_Bank));\r\n assert_param(IS_FSMC_IT(FSMC_IT));\t\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected FSMC_Bank2 interrupts */\r\n if(FSMC_Bank == FSMC_Bank2_NAND)\r\n {\r\n FSMC_Bank2->SR2 |= FSMC_IT;\r\n }\r\n /* Enable the selected FSMC_Bank3 interrupts */\r\n else if (FSMC_Bank == FSMC_Bank3_NAND)\r\n {\r\n FSMC_Bank3->SR3 |= FSMC_IT;\r\n }\r\n /* Enable the selected FSMC_Bank4 interrupts */\r\n else\r\n {\r\n FSMC_Bank4->SR4 |= FSMC_IT; \r\n }\r\n }\r\n else\r\n {\r\n /* Disable the selected FSMC_Bank2 interrupts */\r\n if(FSMC_Bank == FSMC_Bank2_NAND)\r\n {\r\n \r\n FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;\r\n }\r\n /* Disable the selected FSMC_Bank3 interrupts */\r\n else if (FSMC_Bank == FSMC_Bank3_NAND)\r\n {\r\n FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;\r\n }\r\n /* Disable the selected FSMC_Bank4 interrupts */\r\n else\r\n {\r\n FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; \r\n }\r\n }\r\n}\r\n\r\n/**\r\n * @brief Checks whether the specified FSMC flag is set or not.\r\n * @param FSMC_Bank: specifies the FSMC Bank to be used\r\n * This parameter can be one of the following values:\r\n * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r\n * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r\n * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r\n * @param FSMC_FLAG: specifies the flag to check.\r\n * This parameter can be one of the following values:\r\n * @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag.\r\n * @arg FSMC_FLAG_Level: Level detection Flag.\r\n * @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag.\r\n * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. \r\n * @retval The new state of FSMC_FLAG (SET or RESET).\r\n */\r\nFlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)\r\n{\r\n FlagStatus bitstatus = RESET;\r\n uint32_t tmpsr = 0x00000000;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));\r\n assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));\r\n \r\n if(FSMC_Bank == FSMC_Bank2_NAND)\r\n {\r\n tmpsr = FSMC_Bank2->SR2;\r\n } \r\n else if(FSMC_Bank == FSMC_Bank3_NAND)\r\n {\r\n tmpsr = FSMC_Bank3->SR3;\r\n }\r\n /* FSMC_Bank4_PCCARD*/\r\n else\r\n {\r\n tmpsr = FSMC_Bank4->SR4;\r\n } \r\n \r\n /* Get the flag status */\r\n if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )\r\n {\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n bitstatus = RESET;\r\n }\r\n /* Return the flag status */\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @brief Clears the FSMC's pending flags.\r\n * @param FSMC_Bank: specifies the FSMC Bank to be used\r\n * This parameter can be one of the following values:\r\n * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r\n * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r\n * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r\n * @param FSMC_FLAG: specifies the flag to clear.\r\n * This parameter can be any combination of the following values:\r\n * @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag.\r\n * @arg FSMC_FLAG_Level: Level detection Flag.\r\n * @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag.\r\n * @retval None\r\n */\r\nvoid FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));\r\n assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;\r\n \r\n if(FSMC_Bank == FSMC_Bank2_NAND)\r\n {\r\n FSMC_Bank2->SR2 &= ~FSMC_FLAG; \r\n } \r\n else if(FSMC_Bank == FSMC_Bank3_NAND)\r\n {\r\n FSMC_Bank3->SR3 &= ~FSMC_FLAG;\r\n }\r\n /* FSMC_Bank4_PCCARD*/\r\n else\r\n {\r\n FSMC_Bank4->SR4 &= ~FSMC_FLAG;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Checks whether the specified FSMC interrupt has occurred or not.\r\n * @param FSMC_Bank: specifies the FSMC Bank to be used\r\n * This parameter can be one of the following values:\r\n * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r\n * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r\n * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r\n * @param FSMC_IT: specifies the FSMC interrupt source to check.\r\n * This parameter can be one of the following values:\r\n * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. \r\n * @arg FSMC_IT_Level: Level edge detection interrupt.\r\n * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. \r\n * @retval The new state of FSMC_IT (SET or RESET).\r\n */\r\nITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)\r\n{\r\n ITStatus bitstatus = RESET;\r\n uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; \r\n \r\n /* Check the parameters */\r\n assert_param(IS_FSMC_IT_BANK(FSMC_Bank));\r\n assert_param(IS_FSMC_GET_IT(FSMC_IT));\r\n \r\n if(FSMC_Bank == FSMC_Bank2_NAND)\r\n {\r\n tmpsr = FSMC_Bank2->SR2;\r\n } \r\n else if(FSMC_Bank == FSMC_Bank3_NAND)\r\n {\r\n tmpsr = FSMC_Bank3->SR3;\r\n }\r\n /* FSMC_Bank4_PCCARD*/\r\n else\r\n {\r\n tmpsr = FSMC_Bank4->SR4;\r\n } \r\n \r\n itstatus = tmpsr & FSMC_IT;\r\n \r\n itenable = tmpsr & (FSMC_IT >> 3);\r\n if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))\r\n {\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n bitstatus = RESET;\r\n }\r\n return bitstatus; \r\n}\r\n\r\n/**\r\n * @brief Clears the FSMC's interrupt pending bits.\r\n * @param FSMC_Bank: specifies the FSMC Bank to be used\r\n * This parameter can be one of the following values:\r\n * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r\n * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r\n * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r\n * @param FSMC_IT: specifies the interrupt pending bit to clear.\r\n * This parameter can be any combination of the following values:\r\n * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. \r\n * @arg FSMC_IT_Level: Level edge detection interrupt.\r\n * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.\r\n * @retval None\r\n */\r\nvoid FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FSMC_IT_BANK(FSMC_Bank));\r\n assert_param(IS_FSMC_IT(FSMC_IT));\r\n \r\n if(FSMC_Bank == FSMC_Bank2_NAND)\r\n {\r\n FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); \r\n } \r\n else if(FSMC_Bank == FSMC_Bank3_NAND)\r\n {\r\n FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);\r\n }\r\n /* FSMC_Bank4_PCCARD*/\r\n else\r\n {\r\n FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);\r\n }\r\n}\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_gpio.c", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_gpio.c\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file provides firmware functions to manage the following \r\n * functionalities of the GPIO peripheral: \r\n * - Initialization and Configuration\r\n * - GPIO Read and Write\r\n * - GPIO Alternate functions configuration\r\n * \r\n * @verbatim\r\n *\r\n * ===================================================================\r\n * How to use this driver\r\n * =================================================================== \r\n * 1. Enable the GPIO AHB clock using the following function\r\n * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);\r\n * \r\n * 2. Configure the GPIO pin(s) using GPIO_Init()\r\n * Four possible configuration are available for each pin:\r\n * - Input: Floating, Pull-up, Pull-down.\r\n * - Output: Push-Pull (Pull-up, Pull-down or no Pull)\r\n * Open Drain (Pull-up, Pull-down or no Pull).\r\n * In output mode, the speed is configurable: 2 MHz, 25 MHz,\r\n * 50 MHz or 100 MHz.\r\n * - Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull)\r\n * Open Drain (Pull-up, Pull-down or no Pull).\r\n * - Analog: required mode when a pin is to be used as ADC channel\r\n * or DAC output.\r\n * \r\n * 3- Peripherals alternate function:\r\n * - For ADC and DAC, configure the desired pin in analog mode using \r\n * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN;\r\n * - For other peripherals (TIM, USART...):\r\n * - Connect the pin to the desired peripherals' Alternate \r\n * Function (AF) using GPIO_PinAFConfig() function\r\n * - Configure the desired pin in alternate function mode using\r\n * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF\r\n * - Select the type, pull-up/pull-down and output speed via \r\n * GPIO_PuPd, GPIO_OType and GPIO_Speed members\r\n * - Call GPIO_Init() function\r\n * \r\n * 4. To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()\r\n * \r\n * 5. To set/reset the level of a pin configured in output mode use\r\n * GPIO_SetBits()/GPIO_ResetBits()\r\n * \r\n * 6. During and just after reset, the alternate functions are not \r\n * active and the GPIO pins are configured in input floating mode\r\n * (except JTAG pins).\r\n *\r\n * 7. The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as \r\n * general-purpose (PC14 and PC15, respectively) when the LSE\r\n * oscillator is off. The LSE has priority over the GPIO function.\r\n *\r\n * 8. The HSE oscillator pins OSC_IN/OSC_OUT can be used as \r\n * general-purpose PH0 and PH1, respectively, when the HSE \r\n * oscillator is off. The HSE has priority over the GPIO function.\r\n * \r\n * @endverbatim \r\n *\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx_gpio.h\"\r\n#include \"stm32f4xx_rcc.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @defgroup GPIO \r\n * @brief GPIO driver modules\r\n * @{\r\n */ \r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup GPIO_Private_Functions\r\n * @{\r\n */ \r\n\r\n/** @defgroup GPIO_Group1 Initialization and Configuration\r\n * @brief Initialization and Configuration\r\n *\r\n@verbatim \r\n ===============================================================================\r\n Initialization and Configuration\r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Deinitializes the GPIOx peripheral registers to their default reset values.\r\n * @note By default, The GPIO pins are configured in input floating mode (except JTAG pins).\r\n * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.\r\n * @retval None\r\n */\r\nvoid GPIO_DeInit(GPIO_TypeDef* GPIOx)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r\n\r\n if (GPIOx == GPIOA)\r\n {\r\n RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE);\r\n RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE);\r\n }\r\n else if (GPIOx == GPIOB)\r\n {\r\n RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE);\r\n RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE);\r\n }\r\n else if (GPIOx == GPIOC)\r\n {\r\n RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE);\r\n RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE);\r\n }\r\n else if (GPIOx == GPIOD)\r\n {\r\n RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE);\r\n RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE);\r\n }\r\n else if (GPIOx == GPIOE)\r\n {\r\n RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE);\r\n RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE);\r\n }\r\n else if (GPIOx == GPIOF)\r\n {\r\n RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE);\r\n RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE);\r\n }\r\n else if (GPIOx == GPIOG)\r\n {\r\n RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE);\r\n RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE);\r\n }\r\n else if (GPIOx == GPIOH)\r\n {\r\n RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE);\r\n RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE);\r\n }\r\n else\r\n {\r\n if (GPIOx == GPIOI)\r\n {\r\n RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE);\r\n RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE);\r\n }\r\n }\r\n}\r\n\r\n/**\r\n * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.\r\n * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.\r\n * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains\r\n * the configuration information for the specified GPIO peripheral.\r\n * @retval None\r\n */\r\nvoid GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)\r\n{\r\n uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r\n assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));\r\n assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));\r\n assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));\r\n\r\n /* -------------------------Configure the port pins---------------- */\r\n /*-- GPIO Mode Configuration --*/\r\n for (pinpos = 0x00; pinpos < 0x10; pinpos++)\r\n {\r\n pos = ((uint32_t)0x01) << pinpos;\r\n /* Get the port pins position */\r\n currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;\r\n\r\n if (currentpin == pos)\r\n {\r\n GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2));\r\n GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));\r\n\r\n if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))\r\n {\r\n /* Check Speed mode parameters */\r\n assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));\r\n\r\n /* Speed mode configuration */\r\n GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));\r\n GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));\r\n\r\n /* Check Output mode parameters */\r\n assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));\r\n\r\n /* Output mode configuration*/\r\n GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ;\r\n GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));\r\n }\r\n\r\n /* Pull-up Pull down resistor configuration*/\r\n GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));\r\n GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));\r\n }\r\n }\r\n}\r\n\r\n/**\r\n * @brief Fills each GPIO_InitStruct member with its default value.\r\n * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized.\r\n * @retval None\r\n */\r\nvoid GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)\r\n{\r\n /* Reset GPIO init structure parameters values */\r\n GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;\r\n GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;\r\n GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;\r\n GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;\r\n GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;\r\n}\r\n\r\n/**\r\n * @brief Locks GPIO Pins configuration registers.\r\n * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,\r\n * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.\r\n * @note The configuration of the locked GPIO pins can no longer be modified\r\n * until the next reset.\r\n * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.\r\n * @param GPIO_Pin: specifies the port bit to be locked.\r\n * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r\n * @retval None\r\n */\r\nvoid GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r\n{\r\n __IO uint32_t tmp = 0x00010000;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r\n assert_param(IS_GPIO_PIN(GPIO_Pin));\r\n\r\n tmp |= GPIO_Pin;\r\n /* Set LCKK bit */\r\n GPIOx->LCKR = tmp;\r\n /* Reset LCKK bit */\r\n GPIOx->LCKR = GPIO_Pin;\r\n /* Set LCKK bit */\r\n GPIOx->LCKR = tmp;\r\n /* Read LCKK bit*/\r\n tmp = GPIOx->LCKR;\r\n /* Read LCKK bit*/\r\n tmp = GPIOx->LCKR;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup GPIO_Group2 GPIO Read and Write\r\n * @brief GPIO Read and Write\r\n *\r\n@verbatim \r\n ===============================================================================\r\n GPIO Read and Write\r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Reads the specified input port pin.\r\n * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.\r\n * @param GPIO_Pin: specifies the port bit to read.\r\n * This parameter can be GPIO_Pin_x where x can be (0..15).\r\n * @retval The input port pin value.\r\n */\r\nuint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r\n{\r\n //uint8_t bitstatus = 0x00;\r\n\r\n /* Check the parameters */\r\n //assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r\n //assert_param(IS_GET_GPIO_PIN(GPIO_Pin));\r\n\r\n //if (\r\n\r\n\r\n\t\t return (GPIOx->IDR & GPIO_Pin) ? 0x01 : 0x00;\r\n // {\r\n // return (uint8_t)Bit_SET;\r\n // }\r\n //else\r\n //{\r\n // return (uint8_t)Bit_RESET;\r\n //}\r\n //return bitstatus;\r\n}\r\n\r\n/**\r\n * @brief Reads the specified GPIO input data port.\r\n * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.\r\n * @retval GPIO input data port value.\r\n */\r\nuint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r\n\r\n return ((uint16_t)GPIOx->IDR);\r\n}\r\n\r\n/**\r\n * @brief Reads the specified output data port bit.\r\n * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.\r\n * @param GPIO_Pin: specifies the port bit to read.\r\n * This parameter can be GPIO_Pin_x where x can be (0..15).\r\n * @retval The output port pin value.\r\n */\r\nuint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r\n{\r\n uint8_t bitstatus = 0x00;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r\n assert_param(IS_GET_GPIO_PIN(GPIO_Pin));\r\n\r\n if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)\r\n {\r\n bitstatus = (uint8_t)Bit_SET;\r\n }\r\n else\r\n {\r\n bitstatus = (uint8_t)Bit_RESET;\r\n }\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @brief Reads the specified GPIO output data port.\r\n * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.\r\n * @retval GPIO output data port value.\r\n */\r\nuint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r\n\r\n return ((uint16_t)GPIOx->ODR);\r\n}\r\n\r\n/**\r\n * @brief Sets the selected data port bits.\r\n * @note This functions uses GPIOx_BSRR register to allow atomic read/modify \r\n * accesses. In this way, there is no risk of an IRQ occurring between\r\n * the read and the modify access.\r\n * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.\r\n * @param GPIO_Pin: specifies the port bits to be written.\r\n * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r\n * @retval None\r\n */\r\nvoid GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r\n{\r\n /* Check the parameters */\r\n //assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r\n //assert_param(IS_GPIO_PIN(GPIO_Pin));\r\n\r\n GPIOx->BSRRL = GPIO_Pin;\r\n}\r\n\r\n/**\r\n * @brief Clears the selected data port bits.\r\n * @note This functions uses GPIOx_BSRR register to allow atomic read/modify \r\n * accesses. In this way, there is no risk of an IRQ occurring between\r\n * the read and the modify access.\r\n * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.\r\n * @param GPIO_Pin: specifies the port bits to be written.\r\n * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r\n * @retval None\r\n */\r\nvoid GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r\n{\r\n /* Check the parameters */\r\n //assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r\n //assert_param(IS_GPIO_PIN(GPIO_Pin));\r\n\r\n GPIOx->BSRRH = GPIO_Pin;\r\n}\r\n\r\n/**\r\n * @brief Sets or clears the selected data port bit.\r\n * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.\r\n * @param GPIO_Pin: specifies the port bit to be written.\r\n * This parameter can be one of GPIO_Pin_x where x can be (0..15).\r\n * @param BitVal: specifies the value to be written to the selected bit.\r\n * This parameter can be one of the BitAction enum values:\r\n * @arg Bit_RESET: to clear the port pin\r\n * @arg Bit_SET: to set the port pin\r\n * @retval None\r\n */\r\nvoid GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r\n assert_param(IS_GET_GPIO_PIN(GPIO_Pin));\r\n assert_param(IS_GPIO_BIT_ACTION(BitVal));\r\n\r\n if (BitVal != Bit_RESET)\r\n {\r\n GPIOx->BSRRL = GPIO_Pin;\r\n }\r\n else\r\n {\r\n GPIOx->BSRRH = GPIO_Pin ;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Writes data to the specified GPIO data port.\r\n * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.\r\n * @param PortVal: specifies the value to be written to the port output data register.\r\n * @retval None\r\n */\r\nvoid GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r\n\r\n GPIOx->ODR = PortVal;\r\n}\r\n\r\n/**\r\n * @brief Toggles the specified GPIO pins..\r\n * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.\r\n * @param GPIO_Pin: Specifies the pins to be toggled.\r\n * @retval None\r\n */\r\nvoid GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r\n\r\n GPIOx->ODR ^= GPIO_Pin;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup GPIO_Group3 GPIO Alternate functions configuration function\r\n * @brief GPIO Alternate functions configuration function\r\n *\r\n@verbatim \r\n ===============================================================================\r\n GPIO Alternate functions configuration function\r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Changes the mapping of the specified pin.\r\n * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.\r\n * @param GPIO_PinSource: specifies the pin for the Alternate function.\r\n * This parameter can be GPIO_PinSourcex where x can be (0..15).\r\n * @param GPIO_AFSelection: selects the pin to used as Alternate function.\r\n * This parameter can be one of the following values:\r\n * @arg GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset) \r\n * @arg GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset) \r\n * @arg GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset) \r\n * @arg GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset) \r\n * @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset)\r\n * @arg GPIO_AF_TIM1: Connect TIM1 pins to AF1\r\n * @arg GPIO_AF_TIM2: Connect TIM2 pins to AF1\r\n * @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2\r\n * @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2\r\n * @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2\r\n * @arg GPIO_AF_TIM8: Connect TIM8 pins to AF3\r\n * @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3\r\n * @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3\r\n * @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3\r\n * @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4\r\n * @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4\r\n * @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4\r\n * @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5\r\n * @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5\r\n * @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6\r\n * @arg GPIO_AF_I2S3ext: Connect I2S3ext pins to AF7\r\n * @arg GPIO_AF_USART1: Connect USART1 pins to AF7\r\n * @arg GPIO_AF_USART2: Connect USART2 pins to AF7\r\n * @arg GPIO_AF_USART3: Connect USART3 pins to AF7\r\n * @arg GPIO_AF_UART4: Connect UART4 pins to AF8\r\n * @arg GPIO_AF_UART5: Connect UART5 pins to AF8\r\n * @arg GPIO_AF_USART6: Connect USART6 pins to AF8\r\n * @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9\r\n * @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9\r\n * @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9\r\n * @arg GPIO_AF_TIM13: Connect TIM13 pins to AF9\r\n * @arg GPIO_AF_TIM14: Connect TIM14 pins to AF9\r\n * @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10\r\n * @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10\r\n * @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11\r\n * @arg GPIO_AF_FSMC: Connect FSMC pins to AF12\r\n * @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12\r\n * @arg GPIO_AF_SDIO: Connect SDIO pins to AF12\r\n * @arg GPIO_AF_DCMI: Connect DCMI pins to AF13\r\n * @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15\r\n * @retval None\r\n */\r\nvoid GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)\r\n{\r\n uint32_t temp = 0x00;\r\n uint32_t temp_2 = 0x00;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r\n assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));\r\n assert_param(IS_GPIO_AF(GPIO_AF));\r\n \r\n temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;\r\n GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;\r\n temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;\r\n GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;\r\n}\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_hash.c\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file provides firmware functions to manage the following \r\n * functionalities of the HASH / HMAC Processor (HASH) peripheral: \r\n * - Initialization and Configuration functions\r\n * - Message Digest generation functions\r\n * - context swapping functions \r\n * - DMA interface function \r\n * - Interrupts and flags management \r\n * \r\n * @verbatim\r\n * \r\n * =================================================================== \r\n * How to use this driver\r\n * ===================================================================\r\n * HASH operation : \r\n * ---------------- \r\n * 1. Enable the HASH controller clock using \r\n * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE) function.\r\n * \r\n * 2. Initialise the HASH using HASH_Init() function. \r\n * \r\n * 3 . Reset the HASH processor core, so that the HASH will be ready \r\n * to compute he message digest of a new message by using \r\n * HASH_Reset() function.\r\n *\r\n * 4. Enable the HASH controller using the HASH_Cmd() function. \r\n * \r\n * 5. if using DMA for Data input transfer, Activate the DMA Request \r\n * using HASH_DMACmd() function \r\n * \r\n * 6. if DMA is not used for data transfer, use HASH_DataIn() function \r\n * to enter data to IN FIFO.\r\n * \r\n * \r\n * 7. Configure the Number of valid bits in last word of the message \r\n * using HASH_SetLastWordValidBitsNbr() function.\r\n * \r\n * 8. if the message length is not an exact multiple of 512 bits, \r\n * then the function HASH_StartDigest() must be called to \r\n * launch the computation of the final digest. \r\n * \r\n * 9. Once computed, the digest can be read using HASH_GetDigest() \r\n * function. \r\n * \r\n * 10. To control HASH events you can use one of the following \r\n * two methods:\r\n * a- Check on HASH flags using the HASH_GetFlagStatus() function. \r\n * b- Use HASH interrupts through the function HASH_ITConfig() at \r\n * initialization phase and HASH_GetITStatus() function into \r\n * interrupt routines in hashing phase.\r\n * After checking on a flag you should clear it using HASH_ClearFlag()\r\n * function. And after checking on an interrupt event you should \r\n * clear it using HASH_ClearITPendingBit() function. \r\n * \r\n * 11. Save and restore hash processor context using \r\n * HASH_SaveContext() and HASH_RestoreContext() functions. \r\n * \r\n *\r\n * \r\n * HMAC operation : \r\n * ---------------- \r\n * The HMAC algorithm is used for message authentication, by \r\n * irreversibly binding the message being processed to a key chosen \r\n * by the user. \r\n * For HMAC specifications, refer to \"HMAC: keyed-hashing for message \r\n * authentication, H. Krawczyk, M. Bellare, R. Canetti, February 1997\"\r\n * \r\n * Basically, the HMAC algorithm consists of two nested hash operations:\r\n * HMAC(message) = Hash[((key | pad) XOR 0x5C) | Hash(((key | pad) XOR 0x36) | message)]\r\n * where:\r\n * - \"pad\" is a sequence of zeroes needed to extend the key to the \r\n * length of the underlying hash function data block (that is \r\n * 512 bits for both the SHA-1 and MD5 hash algorithms)\r\n * - \"|\" represents the concatenation operator \r\n * \r\n * \r\n * To compute the HMAC, four different phases are required:\r\n * \r\n * 1. Initialise the HASH using HASH_Init() function to do HMAC \r\n * operation. \r\n * \r\n * 2. The key (to be used for the inner hash function) is then given \r\n * to the core. This operation follows the same mechanism as the \r\n * one used to send the message in the hash operation (that is, \r\n * by HASH_DataIn() function and, finally, \r\n * HASH_StartDigest() function.\r\n * \r\n * 3. Once the last word has been entered and computation has started, \r\n * the hash processor elaborates the key. It is then ready to \r\n * accept the message text using the same mechanism as the one \r\n * used to send the message in the hash operation.\r\n * \r\n * 4. After the first hash round, the hash processor returns \"ready\" \r\n * to indicate that it is ready to receive the key to be used for \r\n * the outer hash function (normally, this key is the same as the \r\n * one used for the inner hash function). When the last word of \r\n * the key is entered and computation starts, the HMAC result is \r\n * made available using HASH_GetDigest() function.\r\n * \r\n * \r\n * @endverbatim\r\n * \r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx_hash.h\"\r\n#include \"stm32f4xx_rcc.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @defgroup HASH \r\n * @brief HASH driver modules\r\n * @{\r\n */ \r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/ \r\n\r\n/** @defgroup HASH_Private_Functions\r\n * @{\r\n */ \r\n\r\n/** @defgroup HASH_Group1 Initialization and Configuration functions\r\n * @brief Initialization and Configuration functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Initialization and Configuration functions\r\n =============================================================================== \r\n This section provides functions allowing to \r\n - Initialize the HASH peripheral\r\n - Configure the HASH Processor \r\n - MD5/SHA1, \r\n - HASH/HMAC, \r\n - datatype \r\n - HMAC Key (if mode = HMAC)\r\n - Reset the HASH Processor \r\n \r\n@endverbatim\r\n * @{\r\n */\r\n \r\n/**\r\n * @brief Deinitializes the HASH peripheral registers to their default reset values\r\n * @param None\r\n * @retval None\r\n */\r\nvoid HASH_DeInit(void)\r\n{\r\n /* Enable HASH reset state */\r\n RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, ENABLE);\r\n /* Release HASH from reset state */\r\n RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, DISABLE);\r\n}\r\n\r\n/**\r\n * @brief Initializes the HASH peripheral according to the specified parameters\r\n * in the HASH_InitStruct structure.\r\n * @note the hash processor is reset when calling this function so that the\r\n * HASH will be ready to compute the message digest of a new message.\r\n * There is no need to call HASH_Reset() function. \r\n * @param HASH_InitStruct: pointer to a HASH_InitTypeDef structure that contains\r\n * the configuration information for the HASH peripheral.\r\n * @note The field HASH_HMACKeyType in HASH_InitTypeDef must be filled only \r\n * if the algorithm mode is HMAC. \r\n * @retval None\r\n */\r\nvoid HASH_Init(HASH_InitTypeDef* HASH_InitStruct)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_HASH_ALGOSELECTION(HASH_InitStruct->HASH_AlgoSelection));\r\n assert_param(IS_HASH_DATATYPE(HASH_InitStruct->HASH_DataType));\r\n assert_param(IS_HASH_ALGOMODE(HASH_InitStruct->HASH_AlgoMode));\r\n \r\n /* Configure the Algorithm used, algorithm mode and the datatype */\r\n HASH->CR &= ~ (HASH_CR_ALGO | HASH_CR_DATATYPE | HASH_CR_MODE);\r\n HASH->CR |= (HASH_InitStruct->HASH_AlgoSelection | \\\r\n HASH_InitStruct->HASH_DataType | \\\r\n HASH_InitStruct->HASH_AlgoMode);\r\n \r\n /* if algorithm mode is HMAC, set the Key */ \r\n if(HASH_InitStruct->HASH_AlgoMode == HASH_AlgoMode_HMAC) \r\n {\r\n assert_param(IS_HASH_HMAC_KEYTYPE(HASH_InitStruct->HASH_HMACKeyType));\r\n HASH->CR &= ~HASH_CR_LKEY;\r\n HASH->CR |= HASH_InitStruct->HASH_HMACKeyType;\r\n }\r\n\r\n /* Reset the HASH processor core, so that the HASH will be ready to compute \r\n the message digest of a new message */\r\n HASH->CR |= HASH_CR_INIT; \r\n}\r\n\r\n/**\r\n * @brief Fills each HASH_InitStruct member with its default value.\r\n * @param HASH_InitStruct : pointer to a HASH_InitTypeDef structure which will\r\n * be initialized. \r\n * @note The default values set are : Processor mode is HASH, Algorithm selected is SHA1,\r\n * Data type selected is 32b and HMAC Key Type is short key. \r\n * @retval None\r\n */\r\nvoid HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct)\r\n{\r\n /* Initialize the HASH_AlgoSelection member */\r\n HASH_InitStruct->HASH_AlgoSelection = HASH_AlgoSelection_SHA1;\r\n\r\n /* Initialize the HASH_AlgoMode member */\r\n HASH_InitStruct->HASH_AlgoMode = HASH_AlgoMode_HASH;\r\n\r\n /* Initialize the HASH_DataType member */\r\n HASH_InitStruct->HASH_DataType = HASH_DataType_32b;\r\n\r\n /* Initialize the HASH_HMACKeyType member */\r\n HASH_InitStruct->HASH_HMACKeyType = HASH_HMACKeyType_ShortKey;\r\n}\r\n\r\n/**\r\n * @brief Resets the HASH processor core, so that the HASH will be ready\r\n * to compute the message digest of a new message.\r\n * @note Calling this function will clear the HASH_SR_DCIS (Digest calculation \r\n * completion interrupt status) bit corresponding to HASH_IT_DCI \r\n * interrupt and HASH_FLAG_DCIS flag. \r\n * @param None\r\n * @retval None\r\n */\r\nvoid HASH_Reset(void)\r\n{\r\n /* Reset the HASH processor core */\r\n HASH->CR |= HASH_CR_INIT;\r\n}\r\n/**\r\n * @}\r\n */\r\n \r\n/** @defgroup HASH_Group2 Message Digest generation functions\r\n * @brief Message Digest generation functions\r\n *\r\n@verbatim \r\n ===============================================================================\r\n Message Digest generation functions\r\n =============================================================================== \r\n This section provides functions allowing the generation of message digest: \r\n - Push data in the IN FIFO : using HASH_DataIn()\r\n - Get the number of words set in IN FIFO, use HASH_GetInFIFOWordsNbr() \r\n - set the last word valid bits number using HASH_SetLastWordValidBitsNbr() \r\n - start digest calculation : using HASH_StartDigest()\r\n - Get the Digest message : using HASH_GetDigest()\r\n \r\n@endverbatim\r\n * @{\r\n */\r\n\r\n\r\n/**\r\n * @brief Configure the Number of valid bits in last word of the message\r\n * @param ValidNumber: Number of valid bits in last word of the message.\r\n * This parameter must be a number between 0 and 0x1F.\r\n * - 0x00: All 32 bits of the last data written are valid\r\n * - 0x01: Only bit [0] of the last data written is valid\r\n * - 0x02: Only bits[1:0] of the last data written are valid\r\n * - 0x03: Only bits[2:0] of the last data written are valid\r\n * - ...\r\n * - 0x1F: Only bits[30:0] of the last data written are valid \r\n * @note The Number of valid bits must be set before to start the message \r\n * digest competition (in Hash and HMAC) and key treatment(in HMAC). \r\n * @retval None\r\n */\r\nvoid HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_HASH_VALIDBITSNUMBER(ValidNumber));\r\n \r\n /* Configure the Number of valid bits in last word of the message */\r\n HASH->STR &= ~(HASH_STR_NBW);\r\n HASH->STR |= ValidNumber;\r\n}\r\n\r\n/**\r\n * @brief Writes data in the Data Input FIFO\r\n * @param Data: new data of the message to be processed.\r\n * @retval None\r\n */\r\nvoid HASH_DataIn(uint32_t Data)\r\n{\r\n /* Write in the DIN register a new data */\r\n HASH->DIN = Data;\r\n}\r\n\r\n/**\r\n * @brief Returns the number of words already pushed into the IN FIFO.\r\n * @param None\r\n * @retval The value of words already pushed into the IN FIFO.\r\n */\r\nuint8_t HASH_GetInFIFOWordsNbr(void)\r\n{\r\n /* Return the value of NBW bits */\r\n return ((HASH->CR & HASH_CR_NBW) >> 8);\r\n}\r\n\r\n/**\r\n * @brief Provides the message digest result.\r\n * @note In MD5 mode, Data[4] filed of HASH_MsgDigest structure is not used\r\n * and is read as zero. \r\n * @param HASH_MessageDigest: pointer to a HASH_MsgDigest structure which will \r\n * hold the message digest result \r\n * @retval None\r\n */\r\nvoid HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest)\r\n{\r\n /* Get the data field */\r\n HASH_MessageDigest->Data[0] = HASH->HR[0];\r\n HASH_MessageDigest->Data[1] = HASH->HR[1];\r\n HASH_MessageDigest->Data[2] = HASH->HR[2];\r\n HASH_MessageDigest->Data[3] = HASH->HR[3];\r\n HASH_MessageDigest->Data[4] = HASH->HR[4];\r\n}\r\n\r\n/**\r\n * @brief Starts the message padding and calculation of the final message \r\n * @param None\r\n * @retval None\r\n */\r\nvoid HASH_StartDigest(void)\r\n{\r\n /* Start the Digest calculation */\r\n HASH->STR |= HASH_STR_DCAL;\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup HASH_Group3 Context swapping functions\r\n * @brief Context swapping functions\r\n *\r\n@verbatim \r\n ===============================================================================\r\n Context swapping functions\r\n =============================================================================== \r\n\r\n This section provides functions allowing to save and store HASH Context\r\n \r\n It is possible to interrupt a HASH/HMAC process to perform another processing \r\n with a higher priority, and to complete the interrupted process later on, when \r\n the higher priority task is complete. To do so, the context of the interrupted \r\n task must be saved from the HASH registers to memory, and then be restored \r\n from memory to the HASH registers.\r\n \r\n 1. To save the current context, use HASH_SaveContext() function\r\n 2. To restore the saved context, use HASH_RestoreContext() function \r\n \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n \r\n/**\r\n * @brief Save the Hash peripheral Context. \r\n * @note The context can be saved only when no block is currently being \r\n * processed. So user must wait for DINIS = 1 (the last block has been \r\n * processed and the input FIFO is empty) or NBW != 0 (the FIFO is not \r\n * full and no processing is ongoing). \r\n * @param HASH_ContextSave: pointer to a HASH_Context structure that contains\r\n * the repository for current context.\r\n * @retval None\r\n */\r\nvoid HASH_SaveContext(HASH_Context* HASH_ContextSave)\r\n{\r\n uint8_t i = 0;\r\n \r\n /* save context registers */\r\n HASH_ContextSave->HASH_IMR = HASH->IMR; \r\n HASH_ContextSave->HASH_STR = HASH->STR; \r\n HASH_ContextSave->HASH_CR = HASH->CR; \r\n for(i=0; i<=50;i++)\r\n {\r\n HASH_ContextSave->HASH_CSR[i] = HASH->CSR[i];\r\n } \r\n}\r\n\r\n/**\r\n * @brief Restore the Hash peripheral Context. \r\n * @note After calling this function, user can restart the processing from the\r\n * point where it has been interrupted. \r\n * @param HASH_ContextRestore: pointer to a HASH_Context structure that contains\r\n * the repository for saved context.\r\n * @retval None\r\n */\r\nvoid HASH_RestoreContext(HASH_Context* HASH_ContextRestore) \r\n{\r\n uint8_t i = 0;\r\n \r\n /* restore context registers */\r\n HASH->IMR = HASH_ContextRestore->HASH_IMR; \r\n HASH->STR = HASH_ContextRestore->HASH_STR; \r\n HASH->CR = HASH_ContextRestore->HASH_CR;\r\n \r\n /* Initialize the hash processor */\r\n HASH->CR |= HASH_CR_INIT; \r\n \r\n /* continue restoring context registers */ \r\n for(i=0; i<=50;i++)\r\n {\r\n HASH->CSR[i] = HASH_ContextRestore->HASH_CSR[i];\r\n } \r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup HASH_Group4 HASH's DMA interface Configuration function\r\n * @brief HASH's DMA interface Configuration function \r\n *\r\n@verbatim \r\n ===============================================================================\r\n HASH's DMA interface Configuration function\r\n =============================================================================== \r\n\r\n This section provides functions allowing to configure the DMA interface for \r\n HASH/ HMAC data input transfer.\r\n \r\n When the DMA mode is enabled (using the HASH_DMACmd() function), data can be \r\n sent to the IN FIFO using the DMA peripheral.\r\n\r\n\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n \r\n/**\r\n * @brief Enables or disables the HASH DMA interface.\r\n * @note The DMA is disabled by hardware after the end of transfer.\r\n * @param NewState: new state of the selected HASH DMA transfer request.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid HASH_DMACmd(FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the HASH DMA request */\r\n HASH->CR |= HASH_CR_DMAE;\r\n }\r\n else\r\n {\r\n /* Disable the HASH DMA request */\r\n HASH->CR &= ~HASH_CR_DMAE;\r\n }\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup HASH_Group5 Interrupts and flags management functions\r\n * @brief Interrupts and flags management functions\r\n *\r\n@verbatim \r\n ===============================================================================\r\n Interrupts and flags management functions\r\n =============================================================================== \r\n\r\n This section provides functions allowing to configure the HASH Interrupts and \r\n to get the status and clear flags and Interrupts pending bits.\r\n \r\n The HASH provides 2 Interrupts sources and 5 Flags:\r\n \r\n Flags :\r\n ---------- \r\n 1. HASH_FLAG_DINIS : set when 16 locations are free in the Data IN FIFO \r\n which means that a new block (512 bit) can be entered \r\n into the input buffer.\r\n \r\n 2. HASH_FLAG_DCIS : set when Digest calculation is complete\r\n \r\n 3. HASH_FLAG_DMAS : set when HASH's DMA interface is enabled (DMAE=1) or \r\n a transfer is ongoing.\r\n This Flag is cleared only by hardware.\r\n \r\n 4. HASH_FLAG_BUSY : set when The hash core is processing a block of data\r\n This Flag is cleared only by hardware. \r\n \r\n 5. HASH_FLAG_DINNE : set when Data IN FIFO is not empty which means that \r\n the Data IN FIFO contains at least one word of data.\r\n This Flag is cleared only by hardware.\r\n \r\n Interrupts :\r\n ------------\r\n \r\n 1. HASH_IT_DINI : if enabled, this interrupt source is pending when 16 \r\n locations are free in the Data IN FIFO which means that \r\n a new block (512 bit) can be entered into the input buffer.\r\n This interrupt source is cleared using \r\n HASH_ClearITPendingBit(HASH_IT_DINI) function.\r\n \r\n 2. HASH_IT_DCI : if enabled, this interrupt source is pending when Digest \r\n calculation is complete.\r\n This interrupt source is cleared using \r\n HASH_ClearITPendingBit(HASH_IT_DCI) function.\r\n\r\n Managing the HASH controller events :\r\n ------------------------------------ \r\n The user should identify which mode will be used in his application to manage \r\n the HASH controller events: Polling mode or Interrupt mode.\r\n \r\n 1. In the Polling Mode it is advised to use the following functions:\r\n - HASH_GetFlagStatus() : to check if flags events occur. \r\n - HASH_ClearFlag() : to clear the flags events.\r\n \r\n 2. In the Interrupt Mode it is advised to use the following functions:\r\n - HASH_ITConfig() : to enable or disable the interrupt source.\r\n - HASH_GetITStatus() : to check if Interrupt occurs.\r\n - HASH_ClearITPendingBit() : to clear the Interrupt pending Bit \r\n (corresponding Flag). \r\n\r\n@endverbatim\r\n * @{\r\n */ \r\n \r\n/**\r\n * @brief Enables or disables the specified HASH interrupts.\r\n * @param HASH_IT: specifies the HASH interrupt source to be enabled or disabled.\r\n * This parameter can be any combination of the following values:\r\n * @arg HASH_IT_DINI: Data Input interrupt\r\n * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt\r\n * @param NewState: new state of the specified HASH interrupt.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_HASH_IT(HASH_IT));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected HASH interrupt */\r\n HASH->IMR |= HASH_IT;\r\n }\r\n else\r\n {\r\n /* Disable the selected HASH interrupt */\r\n HASH->IMR &= (uint8_t) ~HASH_IT;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Checks whether the specified HASH flag is set or not.\r\n * @param HASH_FLAG: specifies the HASH flag to check.\r\n * This parameter can be one of the following values:\r\n * @arg HASH_FLAG_DINIS: Data input interrupt status flag\r\n * @arg HASH_FLAG_DCIS: Digest calculation completion interrupt status flag\r\n * @arg HASH_FLAG_BUSY: Busy flag\r\n * @arg HASH_FLAG_DMAS: DMAS Status flag\r\n * @arg HASH_FLAG_DINNE: Data Input register (DIN) not empty status flag\r\n * @retval The new state of HASH_FLAG (SET or RESET)\r\n */\r\nFlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG)\r\n{\r\n FlagStatus bitstatus = RESET;\r\n uint32_t tempreg = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_HASH_GET_FLAG(HASH_FLAG));\r\n\r\n /* check if the FLAG is in CR register */\r\n if ((HASH_FLAG & HASH_FLAG_DINNE) != (uint16_t)RESET ) \r\n {\r\n tempreg = HASH->CR;\r\n }\r\n else /* The FLAG is in SR register */\r\n {\r\n tempreg = HASH->SR;\r\n }\r\n\r\n /* Check the status of the specified HASH flag */\r\n if ((tempreg & HASH_FLAG) != (uint16_t)RESET)\r\n {\r\n /* HASH is set */\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n /* HASH_FLAG is reset */\r\n bitstatus = RESET;\r\n }\r\n\r\n /* Return the HASH_FLAG status */\r\n return bitstatus;\r\n}\r\n/**\r\n * @brief Clears the HASH flags.\r\n * @param HASH_FLAG: specifies the flag to clear. \r\n * This parameter can be any combination of the following values:\r\n * @arg HASH_FLAG_DINIS: Data Input Flag\r\n * @arg HASH_FLAG_DCIS: Digest Calculation Completion Flag \r\n * @retval None\r\n */\r\nvoid HASH_ClearFlag(uint16_t HASH_FLAG)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_HASH_CLEAR_FLAG(HASH_FLAG));\r\n \r\n /* Clear the selected HASH flags */\r\n HASH->SR = ~(uint32_t)HASH_FLAG;\r\n}\r\n/**\r\n * @brief Checks whether the specified HASH interrupt has occurred or not.\r\n * @param HASH_IT: specifies the HASH interrupt source to check.\r\n * This parameter can be one of the following values:\r\n * @arg HASH_IT_DINI: Data Input interrupt\r\n * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt\r\n * @retval The new state of HASH_IT (SET or RESET).\r\n */\r\nITStatus HASH_GetITStatus(uint8_t HASH_IT)\r\n{\r\n ITStatus bitstatus = RESET;\r\n uint32_t tmpreg = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_HASH_GET_IT(HASH_IT)); \r\n\r\n\r\n /* Check the status of the specified HASH interrupt */\r\n tmpreg = HASH->SR;\r\n\r\n if (((HASH->IMR & tmpreg) & HASH_IT) != RESET)\r\n {\r\n /* HASH_IT is set */\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n /* HASH_IT is reset */\r\n bitstatus = RESET;\r\n }\r\n /* Return the HASH_IT status */\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @brief Clears the HASH interrupt pending bit(s).\r\n * @param HASH_IT: specifies the HASH interrupt pending bit(s) to clear.\r\n * This parameter can be any combination of the following values:\r\n * @arg HASH_IT_DINI: Data Input interrupt\r\n * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt\r\n * @retval None\r\n */\r\nvoid HASH_ClearITPendingBit(uint8_t HASH_IT)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_HASH_IT(HASH_IT));\r\n\r\n /* Clear the selected HASH interrupt pending bit */\r\n HASH->SR = (uint8_t)~HASH_IT;\r\n}\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_hash_md5.c\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file provides high level functions to compute the HASH MD5 and\r\n * HMAC MD5 Digest of an input message.\r\n * It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH\r\n * peripheral.\r\n *\r\n * @verbatim\r\n * \r\n * ===================================================================\r\n * How to use this driver\r\n * ===================================================================\r\n * 1. Enable The HASH controller clock using \r\n * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function.\r\n *\r\n * 2. Calculate the HASH MD5 Digest using HASH_MD5() function.\r\n *\r\n * 3. Calculate the HMAC MD5 Digest using HMAC_MD5() function.\r\n *\r\n * @endverbatim\r\n *\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx_hash.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @defgroup HASH \r\n * @brief HASH driver modules\r\n * @{\r\n */\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n#define MD5BUSY_TIMEOUT ((uint32_t) 0x00010000)\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup HASH_Private_Functions\r\n * @{\r\n */ \r\n\r\n/** @defgroup HASH_Group7 High Level MD5 functions\r\n * @brief High Level MD5 Hash and HMAC functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n High Level MD5 Hash and HMAC functions\r\n ===============================================================================\r\n\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Compute the HASH MD5 digest.\r\n * @param Input: pointer to the Input buffer to be treated.\r\n * @param Ilen: length of the Input buffer.\r\n * @param Output: the returned digest\r\n * @retval An ErrorStatus enumeration value:\r\n * - SUCCESS: digest computation done\r\n * - ERROR: digest computation failed\r\n */\r\nErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16])\r\n{\r\n HASH_InitTypeDef MD5_HASH_InitStructure;\r\n HASH_MsgDigest MD5_MessageDigest;\r\n __IO uint16_t nbvalidbitsdata = 0;\r\n uint32_t i = 0;\r\n __IO uint32_t counter = 0;\r\n uint32_t busystatus = 0;\r\n ErrorStatus status = SUCCESS;\r\n uint32_t inputaddr = (uint32_t)Input;\r\n uint32_t outputaddr = (uint32_t)Output;\r\n\r\n\r\n /* Number of valid bits in last word of the Input data */\r\n nbvalidbitsdata = 8 * (Ilen % 4);\r\n\r\n /* HASH peripheral initialization */\r\n HASH_DeInit();\r\n\r\n /* HASH Configuration */\r\n MD5_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_MD5;\r\n MD5_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH;\r\n MD5_HASH_InitStructure.HASH_DataType = HASH_DataType_8b;\r\n HASH_Init(&MD5_HASH_InitStructure);\r\n\r\n /* Configure the number of valid bits in last word of the data */\r\n HASH_SetLastWordValidBitsNbr(nbvalidbitsdata);\r\n\r\n /* Write the Input block in the IN FIFO */\r\n for(i=0; i 64)\r\n {\r\n /* HMAC long Key */\r\n MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey;\r\n }\r\n else\r\n {\r\n /* HMAC short Key */\r\n MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey;\r\n }\r\n HASH_Init(&MD5_HASH_InitStructure);\r\n\r\n /* Configure the number of valid bits in last word of the Key */\r\n HASH_SetLastWordValidBitsNbr(nbvalidbitskey);\r\n\r\n /* Write the Key */\r\n for(i=0; i
© COPYRIGHT 2012 STMicroelectronics
\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx_hash.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @defgroup HASH \r\n * @brief HASH driver modules\r\n * @{\r\n */\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n#define SHA1BUSY_TIMEOUT ((uint32_t) 0x00010000)\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup HASH_Private_Functions\r\n * @{\r\n */ \r\n\r\n/** @defgroup HASH_Group6 High Level SHA1 functions\r\n * @brief High Level SHA1 Hash and HMAC functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n High Level SHA1 Hash and HMAC functions\r\n ===============================================================================\r\n\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Compute the HASH SHA1 digest.\r\n * @param Input: pointer to the Input buffer to be treated.\r\n * @param Ilen: length of the Input buffer.\r\n * @param Output: the returned digest\r\n * @retval An ErrorStatus enumeration value:\r\n * - SUCCESS: digest computation done\r\n * - ERROR: digest computation failed\r\n */\r\nErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20])\r\n{\r\n HASH_InitTypeDef SHA1_HASH_InitStructure;\r\n HASH_MsgDigest SHA1_MessageDigest;\r\n __IO uint16_t nbvalidbitsdata = 0;\r\n uint32_t i = 0;\r\n __IO uint32_t counter = 0;\r\n uint32_t busystatus = 0;\r\n ErrorStatus status = SUCCESS;\r\n uint32_t inputaddr = (uint32_t)Input;\r\n uint32_t outputaddr = (uint32_t)Output;\r\n\r\n /* Number of valid bits in last word of the Input data */\r\n nbvalidbitsdata = 8 * (Ilen % 4);\r\n\r\n /* HASH peripheral initialization */\r\n HASH_DeInit();\r\n\r\n /* HASH Configuration */\r\n SHA1_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_SHA1;\r\n SHA1_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH;\r\n SHA1_HASH_InitStructure.HASH_DataType = HASH_DataType_8b;\r\n HASH_Init(&SHA1_HASH_InitStructure);\r\n\r\n /* Configure the number of valid bits in last word of the data */\r\n HASH_SetLastWordValidBitsNbr(nbvalidbitsdata);\r\n\r\n /* Write the Input block in the IN FIFO */\r\n for(i=0; i 64)\r\n {\r\n /* HMAC long Key */\r\n SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey;\r\n }\r\n else\r\n {\r\n /* HMAC short Key */\r\n SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey;\r\n }\r\n HASH_Init(&SHA1_HASH_InitStructure);\r\n\r\n /* Configure the number of valid bits in last word of the Key */\r\n HASH_SetLastWordValidBitsNbr(nbvalidbitskey);\r\n\r\n /* Write the Key */\r\n for(i=0; iGPIO_Mode = GPIO_Mode_AF\r\n * - Select the type, pull-up/pull-down and output speed via \r\n * GPIO_PuPd, GPIO_OType and GPIO_Speed members\r\n * - Call GPIO_Init() function\r\n * Recommended configuration is Push-Pull, Pull-up, Open-Drain.\r\n * Add an external pull up if necessary (typically 4.7 KOhm). \r\n * \r\n * 4. Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged\r\n * Address using the I2C_Init() function.\r\n *\r\n * 5. Optionally you can enable/configure the following parameters without\r\n * re-initialization (i.e there is no need to call again I2C_Init() function):\r\n * - Enable the acknowledge feature using I2C_AcknowledgeConfig() function\r\n * - Enable the dual addressing mode using I2C_DualAddressCmd() function\r\n * - Enable the general call using the I2C_GeneralCallCmd() function\r\n * - Enable the clock stretching using I2C_StretchClockCmd() function\r\n * - Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig()\r\n * function.\r\n * - Configure the NACK position for Master Receiver mode in case of \r\n * 2 bytes reception using the function I2C_NACKPositionConfig(). \r\n * - Enable the PEC Calculation using I2C_CalculatePEC() function\r\n * - For SMBus Mode: \r\n * - Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function\r\n * - Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function\r\n *\r\n * 6. Enable the NVIC and the corresponding interrupt using the function \r\n * I2C_ITConfig() if you need to use interrupt mode. \r\n *\r\n * 7. When using the DMA mode \r\n * - Configure the DMA using DMA_Init() function\r\n * - Active the needed channel Request using I2C_DMACmd() or\r\n * I2C_DMALastTransferCmd() function.\r\n * @note When using DMA mode, I2C interrupts may be used at the same time to\r\n * control the communication flow (Start/Stop/Ack... events and errors).\r\n * \r\n * 8. Enable the I2C using the I2C_Cmd() function.\r\n * \r\n * 9. Enable the DMA using the DMA_Cmd() function when using DMA mode in the \r\n * transfers. \r\n *\r\n * @endverbatim\r\n * \r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx_i2c.h\"\r\n#include \"stm32f4xx_rcc.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @defgroup I2C \r\n * @brief I2C driver modules\r\n * @{\r\n */ \r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n\r\n#define CR1_CLEAR_MASK ((uint16_t)0xFBF5) /*I2C_ClockSpeed));\r\n assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));\r\n assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));\r\n assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));\r\n assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));\r\n assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));\r\n\r\n/*---------------------------- I2Cx CR2 Configuration ------------------------*/\r\n /* Get the I2Cx CR2 value */\r\n tmpreg = I2Cx->CR2;\r\n /* Clear frequency FREQ[5:0] bits */\r\n tmpreg &= (uint16_t)~((uint16_t)I2C_CR2_FREQ);\r\n /* Get pclk1 frequency value */\r\n RCC_GetClocksFreq(&rcc_clocks);\r\n pclk1 = rcc_clocks.PCLK1_Frequency;\r\n /* Set frequency bits depending on pclk1 value */\r\n freqrange = (uint16_t)(pclk1 / 1000000);\r\n tmpreg |= freqrange;\r\n /* Write to I2Cx CR2 */\r\n I2Cx->CR2 = tmpreg;\r\n\r\n/*---------------------------- I2Cx CCR Configuration ------------------------*/\r\n /* Disable the selected I2C peripheral to configure TRISE */\r\n I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE);\r\n /* Reset tmpreg value */\r\n /* Clear F/S, DUTY and CCR[11:0] bits */\r\n tmpreg = 0;\r\n\r\n /* Configure speed in standard mode */\r\n if (I2C_InitStruct->I2C_ClockSpeed <= 100000)\r\n {\r\n /* Standard mode speed calculate */\r\n result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));\r\n /* Test if CCR value is under 0x4*/\r\n if (result < 0x04)\r\n {\r\n /* Set minimum allowed value */\r\n result = 0x04; \r\n }\r\n /* Set speed value for standard mode */\r\n tmpreg |= result;\t \r\n /* Set Maximum Rise Time for standard mode */\r\n I2Cx->TRISE = freqrange + 1; \r\n }\r\n /* Configure speed in fast mode */\r\n /* To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral\r\n input clock) must be a multiple of 10 MHz */\r\n else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/\r\n {\r\n if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)\r\n {\r\n /* Fast mode speed calculate: Tlow/Thigh = 2 */\r\n result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));\r\n }\r\n else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/\r\n {\r\n /* Fast mode speed calculate: Tlow/Thigh = 16/9 */\r\n result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));\r\n /* Set DUTY bit */\r\n result |= I2C_DutyCycle_16_9;\r\n }\r\n\r\n /* Test if CCR value is under 0x1*/\r\n if ((result & I2C_CCR_CCR) == 0)\r\n {\r\n /* Set minimum allowed value */\r\n result |= (uint16_t)0x0001; \r\n }\r\n /* Set speed value and set F/S bit for fast mode */\r\n tmpreg |= (uint16_t)(result | I2C_CCR_FS);\r\n /* Set Maximum Rise Time for fast mode */\r\n I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); \r\n }\r\n\r\n /* Write to I2Cx CCR */\r\n I2Cx->CCR = tmpreg;\r\n /* Enable the selected I2C peripheral */\r\n I2Cx->CR1 |= I2C_CR1_PE;\r\n\r\n/*---------------------------- I2Cx CR1 Configuration ------------------------*/\r\n /* Get the I2Cx CR1 value */\r\n tmpreg = I2Cx->CR1;\r\n /* Clear ACK, SMBTYPE and SMBUS bits */\r\n tmpreg &= CR1_CLEAR_MASK;\r\n /* Configure I2Cx: mode and acknowledgement */\r\n /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */\r\n /* Set ACK bit according to I2C_Ack value */\r\n tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);\r\n /* Write to I2Cx CR1 */\r\n I2Cx->CR1 = tmpreg;\r\n\r\n/*---------------------------- I2Cx OAR1 Configuration -----------------------*/\r\n /* Set I2Cx Own Address1 and acknowledged address */\r\n I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);\r\n}\r\n\r\n/**\r\n * @brief Fills each I2C_InitStruct member with its default value.\r\n * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.\r\n * @retval None\r\n */\r\nvoid I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)\r\n{\r\n/*---------------- Reset I2C init structure parameters values ----------------*/\r\n /* initialize the I2C_ClockSpeed member */\r\n I2C_InitStruct->I2C_ClockSpeed = 5000;\r\n /* Initialize the I2C_Mode member */\r\n I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;\r\n /* Initialize the I2C_DutyCycle member */\r\n I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;\r\n /* Initialize the I2C_OwnAddress1 member */\r\n I2C_InitStruct->I2C_OwnAddress1 = 0;\r\n /* Initialize the I2C_Ack member */\r\n I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;\r\n /* Initialize the I2C_AcknowledgedAddress member */\r\n I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the specified I2C peripheral.\r\n * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.\r\n * @param NewState: new state of the I2Cx peripheral. \r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected I2C peripheral */\r\n I2Cx->CR1 |= I2C_CR1_PE;\r\n }\r\n else\r\n {\r\n /* Disable the selected I2C peripheral */\r\n I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Generates I2Cx communication START condition.\r\n * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.\r\n * @param NewState: new state of the I2C START condition generation.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None.\r\n */\r\nvoid I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n /* Generate a START condition */\r\n I2Cx->CR1 |= I2C_CR1_START;\r\n }\r\n else\r\n {\r\n /* Disable the START condition generation */\r\n I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_START);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Generates I2Cx communication STOP condition.\r\n * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.\r\n * @param NewState: new state of the I2C STOP condition generation.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None.\r\n */\r\nvoid I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n /* Generate a STOP condition */\r\n I2Cx->CR1 |= I2C_CR1_STOP;\r\n }\r\n else\r\n {\r\n /* Disable the STOP condition generation */\r\n I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_STOP);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Transmits the address byte to select the slave device.\r\n * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.\r\n * @param Address: specifies the slave address which will be transmitted\r\n * @param I2C_Direction: specifies whether the I2C device will be a Transmitter\r\n * or a Receiver. \r\n * This parameter can be one of the following values\r\n * @arg I2C_Direction_Transmitter: Transmitter mode\r\n * @arg I2C_Direction_Receiver: Receiver mode\r\n * @retval None.\r\n */\r\nvoid I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r\n assert_param(IS_I2C_DIRECTION(I2C_Direction));\r\n /* Test on the direction to set/reset the read/write bit */\r\n if (I2C_Direction != I2C_Direction_Transmitter)\r\n {\r\n /* Set the address bit0 for read */\r\n Address |= I2C_OAR1_ADD0;\r\n }\r\n else\r\n {\r\n /* Reset the address bit0 for write */\r\n Address &= (uint8_t)~((uint8_t)I2C_OAR1_ADD0);\r\n }\r\n /* Send the address */\r\n I2Cx->DR = Address;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the specified I2C acknowledge feature.\r\n * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.\r\n * @param NewState: new state of the I2C Acknowledgement.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None.\r\n */\r\nvoid I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the acknowledgement */\r\n I2Cx->CR1 |= I2C_CR1_ACK;\r\n }\r\n else\r\n {\r\n /* Disable the acknowledgement */\r\n I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ACK);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Configures the specified I2C own address2.\r\n * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.\r\n * @param Address: specifies the 7bit I2C own address2.\r\n * @retval None.\r\n */\r\nvoid I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)\r\n{\r\n uint16_t tmpreg = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r\n\r\n /* Get the old register value */\r\n tmpreg = I2Cx->OAR2;\r\n\r\n /* Reset I2Cx Own address2 bit [7:1] */\r\n tmpreg &= (uint16_t)~((uint16_t)I2C_OAR2_ADD2);\r\n\r\n /* Set I2Cx Own address2 */\r\n tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);\r\n\r\n /* Store the new register value */\r\n I2Cx->OAR2 = tmpreg;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the specified I2C dual addressing mode.\r\n * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.\r\n * @param NewState: new state of the I2C dual addressing mode.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable dual addressing mode */\r\n I2Cx->OAR2 |= I2C_OAR2_ENDUAL;\r\n }\r\n else\r\n {\r\n /* Disable dual addressing mode */\r\n I2Cx->OAR2 &= (uint16_t)~((uint16_t)I2C_OAR2_ENDUAL);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the specified I2C general call feature.\r\n * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.\r\n * @param NewState: new state of the I2C General call.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable generall call */\r\n I2Cx->CR1 |= I2C_CR1_ENGC;\r\n }\r\n else\r\n {\r\n /* Disable generall call */\r\n I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENGC);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the specified I2C software reset.\r\n * @note When software reset is enabled, the I2C IOs are released (this can\r\n * be useful to recover from bus errors). \r\n * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.\r\n * @param NewState: new state of the I2C software reset.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n /* Peripheral under reset */\r\n I2Cx->CR1 |= I2C_CR1_SWRST;\r\n }\r\n else\r\n {\r\n /* Peripheral not under reset */\r\n I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_SWRST);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the specified I2C Clock stretching.\r\n * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.\r\n * @param NewState: new state of the I2Cx Clock stretching.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState == DISABLE)\r\n {\r\n /* Enable the selected I2C Clock stretching */\r\n I2Cx->CR1 |= I2C_CR1_NOSTRETCH;\r\n }\r\n else\r\n {\r\n /* Disable the selected I2C Clock stretching */\r\n I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_NOSTRETCH);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Selects the specified I2C fast mode duty cycle.\r\n * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.\r\n * @param I2C_DutyCycle: specifies the fast mode duty cycle.\r\n * This parameter can be one of the following values:\r\n * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2\r\n * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9\r\n * @retval None\r\n */\r\nvoid I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r\n assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));\r\n if (I2C_DutyCycle != I2C_DutyCycle_16_9)\r\n {\r\n /* I2C fast mode Tlow/Thigh=2 */\r\n I2Cx->CCR &= I2C_DutyCycle_2;\r\n }\r\n else\r\n {\r\n /* I2C fast mode Tlow/Thigh=16/9 */\r\n I2Cx->CCR |= I2C_DutyCycle_16_9;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Selects the specified I2C NACK position in master receiver mode.\r\n * @note This function is useful in I2C Master Receiver mode when the number\r\n * of data to be received is equal to 2. In this case, this function \r\n * should be called (with parameter I2C_NACKPosition_Next) before data \r\n * reception starts,as described in the 2-byte reception procedure \r\n * recommended in Reference Manual in Section: Master receiver. \r\n * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.\r\n * @param I2C_NACKPosition: specifies the NACK position. \r\n * This parameter can be one of the following values:\r\n * @arg I2C_NACKPosition_Next: indicates that the next byte will be the last\r\n * received byte. \r\n * @arg I2C_NACKPosition_Current: indicates that current byte is the last \r\n * received byte.\r\n * \r\n * @note This function configures the same bit (POS) as I2C_PECPositionConfig() \r\n * but is intended to be used in I2C mode while I2C_PECPositionConfig() \r\n * is intended to used in SMBUS mode. \r\n * \r\n * @retval None\r\n */\r\nvoid I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r\n assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition));\r\n \r\n /* Check the input parameter */\r\n if (I2C_NACKPosition == I2C_NACKPosition_Next)\r\n {\r\n /* Next byte in shift register is the last received byte */\r\n I2Cx->CR1 |= I2C_NACKPosition_Next;\r\n }\r\n else\r\n {\r\n /* Current byte in shift register is the last received byte */\r\n I2Cx->CR1 &= I2C_NACKPosition_Current;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Drives the SMBusAlert pin high or low for the specified I2C.\r\n * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.\r\n * @param I2C_SMBusAlert: specifies SMBAlert pin level. \r\n * This parameter can be one of the following values:\r\n * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low\r\n * @arg I2C_SMBusAlert_High: SMBAlert pin driven high\r\n * @retval None\r\n */\r\nvoid I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r\n assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));\r\n if (I2C_SMBusAlert == I2C_SMBusAlert_Low)\r\n {\r\n /* Drive the SMBusAlert pin Low */\r\n I2Cx->CR1 |= I2C_SMBusAlert_Low;\r\n }\r\n else\r\n {\r\n /* Drive the SMBusAlert pin High */\r\n I2Cx->CR1 &= I2C_SMBusAlert_High;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the specified I2C ARP.\r\n * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.\r\n * @param NewState: new state of the I2Cx ARP. \r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected I2C ARP */\r\n I2Cx->CR1 |= I2C_CR1_ENARP;\r\n }\r\n else\r\n {\r\n /* Disable the selected I2C ARP */\r\n I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENARP);\r\n }\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup I2C_Group2 Data transfers functions\r\n * @brief Data transfers functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Data transfers functions\r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Sends a data byte through the I2Cx peripheral.\r\n * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.\r\n * @param Data: Byte to be transmitted..\r\n * @retval None\r\n */\r\nvoid I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r\n /* Write in the DR register the data to be sent */\r\n I2Cx->DR = Data;\r\n}\r\n\r\n/**\r\n * @brief Returns the most recent received data by the I2Cx peripheral.\r\n * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.\r\n * @retval The value of the received data.\r\n */\r\nuint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r\n /* Return the data in the DR register */\r\n return (uint8_t)I2Cx->DR;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup I2C_Group3 PEC management functions\r\n * @brief PEC management functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n PEC management functions\r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Enables or disables the specified I2C PEC transfer.\r\n * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.\r\n * @param NewState: new state of the I2C PEC transmission.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected I2C PEC transmission */\r\n I2Cx->CR1 |= I2C_CR1_PEC;\r\n }\r\n else\r\n {\r\n /* Disable the selected I2C PEC transmission */\r\n I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PEC);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Selects the specified I2C PEC position.\r\n * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.\r\n * @param I2C_PECPosition: specifies the PEC position. \r\n * This parameter can be one of the following values:\r\n * @arg I2C_PECPosition_Next: indicates that the next byte is PEC\r\n * @arg I2C_PECPosition_Current: indicates that current byte is PEC\r\n * \r\n * @note This function configures the same bit (POS) as I2C_NACKPositionConfig()\r\n * but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() \r\n * is intended to used in I2C mode.\r\n * \r\n * @retval None\r\n */\r\nvoid I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r\n assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));\r\n if (I2C_PECPosition == I2C_PECPosition_Next)\r\n {\r\n /* Next byte in shift register is PEC */\r\n I2Cx->CR1 |= I2C_PECPosition_Next;\r\n }\r\n else\r\n {\r\n /* Current byte in shift register is PEC */\r\n I2Cx->CR1 &= I2C_PECPosition_Current;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the PEC value calculation of the transferred bytes.\r\n * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.\r\n * @param NewState: new state of the I2Cx PEC value calculation.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected I2C PEC calculation */\r\n I2Cx->CR1 |= I2C_CR1_ENPEC;\r\n }\r\n else\r\n {\r\n /* Disable the selected I2C PEC calculation */\r\n I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENPEC);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Returns the PEC value for the specified I2C.\r\n * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.\r\n * @retval The PEC value.\r\n */\r\nuint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r\n /* Return the selected I2C PEC value */\r\n return ((I2Cx->SR2) >> 8);\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup I2C_Group4 DMA transfers management functions\r\n * @brief DMA transfers management functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n DMA transfers management functions\r\n =============================================================================== \r\n This section provides functions allowing to configure the I2C DMA channels \r\n requests.\r\n \r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Enables or disables the specified I2C DMA requests.\r\n * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.\r\n * @param NewState: new state of the I2C DMA transfer.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected I2C DMA requests */\r\n I2Cx->CR2 |= I2C_CR2_DMAEN;\r\n }\r\n else\r\n {\r\n /* Disable the selected I2C DMA requests */\r\n I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_DMAEN);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Specifies that the next DMA transfer is the last one.\r\n * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.\r\n * @param NewState: new state of the I2C DMA last transfer.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n /* Next DMA transfer is the last transfer */\r\n I2Cx->CR2 |= I2C_CR2_LAST;\r\n }\r\n else\r\n {\r\n /* Next DMA transfer is not the last transfer */\r\n I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_LAST);\r\n }\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup I2C_Group5 Interrupts events and flags management functions\r\n * @brief Interrupts, events and flags management functions\r\n *\r\n@verbatim \r\n ===============================================================================\r\n Interrupts, events and flags management functions\r\n =============================================================================== \r\n This section provides functions allowing to configure the I2C Interrupts \r\n sources and check or clear the flags or pending bits status.\r\n The user should identify which mode will be used in his application to manage \r\n the communication: Polling mode, Interrupt mode or DMA mode. \r\n\r\n ===============================================================================\r\n I2C State Monitoring Functions \r\n =============================================================================== \r\n This I2C driver provides three different ways for I2C state monitoring\r\n depending on the application requirements and constraints:\r\n \r\n \r\n 1. Basic state monitoring (Using I2C_CheckEvent() function)\r\n -----------------------------------------------------------\r\n It compares the status registers (SR1 and SR2) content to a given event\r\n (can be the combination of one or more flags).\r\n It returns SUCCESS if the current status includes the given flags \r\n and returns ERROR if one or more flags are missing in the current status.\r\n\r\n - When to use\r\n - This function is suitable for most applications as well as for startup \r\n activity since the events are fully described in the product reference \r\n manual (RM0090).\r\n - It is also suitable for users who need to define their own events.\r\n\r\n - Limitations\r\n - If an error occurs (ie. error flags are set besides to the monitored \r\n flags), the I2C_CheckEvent() function may return SUCCESS despite \r\n the communication hold or corrupted real state. \r\n In this case, it is advised to use error interrupts to monitor \r\n the error events and handle them in the interrupt IRQ handler.\r\n \r\n @note \r\n For error management, it is advised to use the following functions:\r\n - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).\r\n - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.\r\n Where x is the peripheral instance (I2C1, I2C2 ...)\r\n - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the \r\n I2Cx_ER_IRQHandler() function in order to determine which error occurred.\r\n - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() \r\n and/or I2C_GenerateStop() in order to clear the error flag and source \r\n and return to correct communication status.\r\n \r\n \r\n 2. Advanced state monitoring (Using the function I2C_GetLastEvent())\r\n -------------------------------------------------------------------- \r\n Using the function I2C_GetLastEvent() which returns the image of both status \r\n registers in a single word (uint32_t) (Status Register 2 value is shifted left \r\n by 16 bits and concatenated to Status Register 1).\r\n\r\n - When to use\r\n - This function is suitable for the same applications above but it \r\n allows to overcome the mentioned limitation of I2C_GetFlagStatus() \r\n function.\r\n - The returned value could be compared to events already defined in \r\n the library (stm32f4xx_i2c.h) or to custom values defined by user.\r\n This function is suitable when multiple flags are monitored at the \r\n same time.\r\n - At the opposite of I2C_CheckEvent() function, this function allows \r\n user to choose when an event is accepted (when all events flags are \r\n set and no other flags are set or just when the needed flags are set \r\n like I2C_CheckEvent() function.\r\n\r\n - Limitations\r\n - User may need to define his own events.\r\n - Same remark concerning the error management is applicable for this \r\n function if user decides to check only regular communication flags \r\n (and ignores error flags).\r\n \r\n \r\n 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())\r\n -----------------------------------------------------------------------\r\n \r\n Using the function I2C_GetFlagStatus() which simply returns the status of \r\n one single flag (ie. I2C_FLAG_RXNE ...). \r\n\r\n - When to use\r\n - This function could be used for specific applications or in debug \r\n phase.\r\n - It is suitable when only one flag checking is needed (most I2C \r\n events are monitored through multiple flags).\r\n - Limitations: \r\n - When calling this function, the Status register is accessed. \r\n Some flags are cleared when the status register is accessed. \r\n So checking the status of one Flag, may clear other ones.\r\n - Function may need to be called twice or more in order to monitor \r\n one single event.\r\n \r\n For detailed description of Events, please refer to section I2C_Events in \r\n stm32f4xx_i2c.h file.\r\n \r\n@endverbatim\r\n * @{\r\n */\r\n \r\n/**\r\n * @brief Reads the specified I2C register and returns its value.\r\n * @param I2C_Register: specifies the register to read.\r\n * This parameter can be one of the following values:\r\n * @arg I2C_Register_CR1: CR1 register.\r\n * @arg I2C_Register_CR2: CR2 register.\r\n * @arg I2C_Register_OAR1: OAR1 register.\r\n * @arg I2C_Register_OAR2: OAR2 register.\r\n * @arg I2C_Register_DR: DR register.\r\n * @arg I2C_Register_SR1: SR1 register.\r\n * @arg I2C_Register_SR2: SR2 register.\r\n * @arg I2C_Register_CCR: CCR register.\r\n * @arg I2C_Register_TRISE: TRISE register.\r\n * @retval The value of the read register.\r\n */\r\nuint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)\r\n{\r\n __IO uint32_t tmp = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r\n assert_param(IS_I2C_REGISTER(I2C_Register));\r\n\r\n tmp = (uint32_t) I2Cx;\r\n tmp += I2C_Register;\r\n\r\n /* Return the selected register value */\r\n return (*(__IO uint16_t *) tmp);\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the specified I2C interrupts.\r\n * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.\r\n * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. \r\n * This parameter can be any combination of the following values:\r\n * @arg I2C_IT_BUF: Buffer interrupt mask\r\n * @arg I2C_IT_EVT: Event interrupt mask\r\n * @arg I2C_IT_ERR: Error interrupt mask\r\n * @param NewState: new state of the specified I2C interrupts.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n assert_param(IS_I2C_CONFIG_IT(I2C_IT));\r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected I2C interrupts */\r\n I2Cx->CR2 |= I2C_IT;\r\n }\r\n else\r\n {\r\n /* Disable the selected I2C interrupts */\r\n I2Cx->CR2 &= (uint16_t)~I2C_IT;\r\n }\r\n}\r\n\r\n/*\r\n ===============================================================================\r\n 1. Basic state monitoring \r\n =============================================================================== \r\n */\r\n\r\n/**\r\n * @brief Checks whether the last I2Cx Event is equal to the one passed\r\n * as parameter.\r\n * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.\r\n * @param I2C_EVENT: specifies the event to be checked. \r\n * This parameter can be one of the following values:\r\n * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED: EV1\r\n * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED: EV1\r\n * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED: EV1\r\n * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED: EV1\r\n * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED: EV1\r\n * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED: EV2\r\n * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF): EV2\r\n * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL): EV2\r\n * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED: EV3\r\n * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF): EV3\r\n * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL): EV3\r\n * @arg I2C_EVENT_SLAVE_ACK_FAILURE: EV3_2\r\n * @arg I2C_EVENT_SLAVE_STOP_DETECTED: EV4\r\n * @arg I2C_EVENT_MASTER_MODE_SELECT: EV5\r\n * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED: EV6 \r\n * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED: EV6\r\n * @arg I2C_EVENT_MASTER_BYTE_RECEIVED: EV7\r\n * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING: EV8\r\n * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED: EV8_2\r\n * @arg I2C_EVENT_MASTER_MODE_ADDRESS10: EV9\r\n * \r\n * @note For detailed description of Events, please refer to section I2C_Events\r\n * in stm32f4xx_i2c.h file.\r\n * \r\n * @retval An ErrorStatus enumeration value:\r\n * - SUCCESS: Last event is equal to the I2C_EVENT\r\n * - ERROR: Last event is different from the I2C_EVENT\r\n */\r\nErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)\r\n{\r\n uint32_t lastevent = 0;\r\n uint32_t flag1 = 0, flag2 = 0;\r\n ErrorStatus status = ERROR;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r\n assert_param(IS_I2C_EVENT(I2C_EVENT));\r\n\r\n /* Read the I2Cx status register */\r\n flag1 = I2Cx->SR1;\r\n flag2 = I2Cx->SR2;\r\n flag2 = flag2 << 16;\r\n\r\n /* Get the last event value from I2C status register */\r\n lastevent = (flag1 | flag2) & FLAG_MASK;\r\n\r\n /* Check whether the last event contains the I2C_EVENT */\r\n if ((lastevent & I2C_EVENT) == I2C_EVENT)\r\n {\r\n /* SUCCESS: last event is equal to I2C_EVENT */\r\n status = SUCCESS;\r\n }\r\n else\r\n {\r\n /* ERROR: last event is different from I2C_EVENT */\r\n status = ERROR;\r\n }\r\n /* Return status */\r\n return status;\r\n}\r\n\r\n/*\r\n ===============================================================================\r\n 2. Advanced state monitoring \r\n =============================================================================== \r\n */\r\n\r\n/**\r\n * @brief Returns the last I2Cx Event.\r\n * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.\r\n * \r\n * @note For detailed description of Events, please refer to section I2C_Events\r\n * in stm32f4xx_i2c.h file.\r\n * \r\n * @retval The last event\r\n */\r\nuint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)\r\n{\r\n uint32_t lastevent = 0;\r\n uint32_t flag1 = 0, flag2 = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r\n\r\n /* Read the I2Cx status register */\r\n flag1 = I2Cx->SR1;\r\n flag2 = I2Cx->SR2;\r\n flag2 = flag2 << 16;\r\n\r\n /* Get the last event value from I2C status register */\r\n lastevent = (flag1 | flag2) & FLAG_MASK;\r\n\r\n /* Return status */\r\n return lastevent;\r\n}\r\n\r\n/*\r\n ===============================================================================\r\n 3. Flag-based state monitoring \r\n =============================================================================== \r\n */\r\n\r\n/**\r\n * @brief Checks whether the specified I2C flag is set or not.\r\n * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.\r\n * @param I2C_FLAG: specifies the flag to check. \r\n * This parameter can be one of the following values:\r\n * @arg I2C_FLAG_DUALF: Dual flag (Slave mode)\r\n * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)\r\n * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)\r\n * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)\r\n * @arg I2C_FLAG_TRA: Transmitter/Receiver flag\r\n * @arg I2C_FLAG_BUSY: Bus busy flag\r\n * @arg I2C_FLAG_MSL: Master/Slave flag\r\n * @arg I2C_FLAG_SMBALERT: SMBus Alert flag\r\n * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag\r\n * @arg I2C_FLAG_PECERR: PEC error in reception flag\r\n * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)\r\n * @arg I2C_FLAG_AF: Acknowledge failure flag\r\n * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)\r\n * @arg I2C_FLAG_BERR: Bus error flag\r\n * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)\r\n * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag\r\n * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)\r\n * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)\r\n * @arg I2C_FLAG_BTF: Byte transfer finished flag\r\n * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) \"ADSL\"\r\n * Address matched flag (Slave mode)\"ENDAD\"\r\n * @arg I2C_FLAG_SB: Start bit flag (Master mode)\r\n * @retval The new state of I2C_FLAG (SET or RESET).\r\n */\r\nFlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)\r\n{\r\n FlagStatus bitstatus = RESET;\r\n __IO uint32_t i2creg = 0, i2cxbase = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r\n assert_param(IS_I2C_GET_FLAG(I2C_FLAG));\r\n\r\n /* Get the I2Cx peripheral base address */\r\n i2cxbase = (uint32_t)I2Cx;\r\n \r\n /* Read flag register index */\r\n i2creg = I2C_FLAG >> 28;\r\n \r\n /* Get bit[23:0] of the flag */\r\n I2C_FLAG &= FLAG_MASK;\r\n \r\n if(i2creg != 0)\r\n {\r\n /* Get the I2Cx SR1 register address */\r\n i2cxbase += 0x14;\r\n }\r\n else\r\n {\r\n /* Flag in I2Cx SR2 Register */\r\n I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);\r\n /* Get the I2Cx SR2 register address */\r\n i2cxbase += 0x18;\r\n }\r\n \r\n if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)\r\n {\r\n /* I2C_FLAG is set */\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n /* I2C_FLAG is reset */\r\n bitstatus = RESET;\r\n }\r\n \r\n /* Return the I2C_FLAG status */\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @brief Clears the I2Cx's pending flags.\r\n * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.\r\n * @param I2C_FLAG: specifies the flag to clear. \r\n * This parameter can be any combination of the following values:\r\n * @arg I2C_FLAG_SMBALERT: SMBus Alert flag\r\n * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag\r\n * @arg I2C_FLAG_PECERR: PEC error in reception flag\r\n * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)\r\n * @arg I2C_FLAG_AF: Acknowledge failure flag\r\n * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)\r\n * @arg I2C_FLAG_BERR: Bus error flag\r\n * \r\n * @note STOPF (STOP detection) is cleared by software sequence: a read operation \r\n * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation \r\n * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).\r\n * @note ADD10 (10-bit header sent) is cleared by software sequence: a read \r\n * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the \r\n * second byte of the address in DR register.\r\n * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read \r\n * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a \r\n * read/write to I2C_DR register (I2C_SendData()).\r\n * @note ADDR (Address sent) is cleared by software sequence: a read operation to \r\n * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to \r\n * I2C_SR2 register ((void)(I2Cx->SR2)).\r\n * @note SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1\r\n * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR\r\n * register (I2C_SendData()).\r\n * \r\n * @retval None\r\n */\r\nvoid I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)\r\n{\r\n uint32_t flagpos = 0;\r\n /* Check the parameters */\r\n assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r\n assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));\r\n /* Get the I2C flag position */\r\n flagpos = I2C_FLAG & FLAG_MASK;\r\n /* Clear the selected I2C flag */\r\n I2Cx->SR1 = (uint16_t)~flagpos;\r\n}\r\n\r\n/**\r\n * @brief Checks whether the specified I2C interrupt has occurred or not.\r\n * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.\r\n * @param I2C_IT: specifies the interrupt source to check. \r\n * This parameter can be one of the following values:\r\n * @arg I2C_IT_SMBALERT: SMBus Alert flag\r\n * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag\r\n * @arg I2C_IT_PECERR: PEC error in reception flag\r\n * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)\r\n * @arg I2C_IT_AF: Acknowledge failure flag\r\n * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)\r\n * @arg I2C_IT_BERR: Bus error flag\r\n * @arg I2C_IT_TXE: Data register empty flag (Transmitter)\r\n * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag\r\n * @arg I2C_IT_STOPF: Stop detection flag (Slave mode)\r\n * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)\r\n * @arg I2C_IT_BTF: Byte transfer finished flag\r\n * @arg I2C_IT_ADDR: Address sent flag (Master mode) \"ADSL\"\r\n * Address matched flag (Slave mode)\"ENDAD\"\r\n * @arg I2C_IT_SB: Start bit flag (Master mode)\r\n * @retval The new state of I2C_IT (SET or RESET).\r\n */\r\nITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)\r\n{\r\n ITStatus bitstatus = RESET;\r\n uint32_t enablestatus = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r\n assert_param(IS_I2C_GET_IT(I2C_IT));\r\n\r\n /* Check if the interrupt source is enabled or not */\r\n enablestatus = (uint32_t)(((I2C_IT & ITEN_MASK) >> 16) & (I2Cx->CR2)) ;\r\n \r\n /* Get bit[23:0] of the flag */\r\n I2C_IT &= FLAG_MASK;\r\n\r\n /* Check the status of the specified I2C flag */\r\n if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)\r\n {\r\n /* I2C_IT is set */\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n /* I2C_IT is reset */\r\n bitstatus = RESET;\r\n }\r\n /* Return the I2C_IT status */\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @brief Clears the I2Cx's interrupt pending bits.\r\n * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.\r\n * @param I2C_IT: specifies the interrupt pending bit to clear. \r\n * This parameter can be any combination of the following values:\r\n * @arg I2C_IT_SMBALERT: SMBus Alert interrupt\r\n * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt\r\n * @arg I2C_IT_PECERR: PEC error in reception interrupt\r\n * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)\r\n * @arg I2C_IT_AF: Acknowledge failure interrupt\r\n * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)\r\n * @arg I2C_IT_BERR: Bus error interrupt\r\n * \r\n * @note STOPF (STOP detection) is cleared by software sequence: a read operation \r\n * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to \r\n * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).\r\n * @note ADD10 (10-bit header sent) is cleared by software sequence: a read \r\n * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second \r\n * byte of the address in I2C_DR register.\r\n * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read \r\n * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a \r\n * read/write to I2C_DR register (I2C_SendData()).\r\n * @note ADDR (Address sent) is cleared by software sequence: a read operation to \r\n * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to \r\n * I2C_SR2 register ((void)(I2Cx->SR2)).\r\n * @note SB (Start Bit) is cleared by software sequence: a read operation to \r\n * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to \r\n * I2C_DR register (I2C_SendData()).\r\n * @retval None\r\n */\r\nvoid I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)\r\n{\r\n uint32_t flagpos = 0;\r\n /* Check the parameters */\r\n assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r\n assert_param(IS_I2C_CLEAR_IT(I2C_IT));\r\n\r\n /* Get the I2C flag position */\r\n flagpos = I2C_IT & FLAG_MASK;\r\n\r\n /* Clear the selected I2C flag */\r\n I2Cx->SR1 = (uint16_t)~flagpos;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_iwdg.c\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file provides firmware functions to manage the following \r\n * functionalities of the Independent watchdog (IWDG) peripheral: \r\n * - Prescaler and Counter configuration\r\n * - IWDG activation\r\n * - Flag management\r\n *\r\n * @verbatim \r\n * \r\n * ===================================================================\r\n * IWDG features\r\n * ===================================================================\r\n * \r\n * The IWDG can be started by either software or hardware (configurable\r\n * through option byte).\r\n * \r\n * The IWDG is clocked by its own dedicated low-speed clock (LSI) and\r\n * thus stays active even if the main clock fails.\r\n * Once the IWDG is started, the LSI is forced ON and cannot be disabled\r\n * (LSI cannot be disabled too), and the counter starts counting down from \r\n * the reset value of 0xFFF. When it reaches the end of count value (0x000)\r\n * a system reset is generated.\r\n * The IWDG counter should be reloaded at regular intervals to prevent\r\n * an MCU reset.\r\n * \r\n * The IWDG is implemented in the VDD voltage domain that is still functional\r\n * in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). \r\n * \r\n * IWDGRST flag in RCC_CSR register can be used to inform when a IWDG\r\n * reset occurs.\r\n * \r\n * Min-max timeout value @32KHz (LSI): ~125us / ~32.7s\r\n * The IWDG timeout may vary due to LSI frequency dispersion. STM32F4xx\r\n * devices provide the capability to measure the LSI frequency (LSI clock\r\n * connected internally to TIM5 CH4 input capture). The measured value\r\n * can be used to have an IWDG timeout with an acceptable accuracy. \r\n * For more information, please refer to the STM32F4xx Reference manual\r\n * \r\n * \r\n * ===================================================================\r\n * How to use this driver\r\n * ===================================================================\r\n * 1. Enable write access to IWDG_PR and IWDG_RLR registers using\r\n * IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function\r\n * \r\n * 2. Configure the IWDG prescaler using IWDG_SetPrescaler() function\r\n * \r\n * 3. Configure the IWDG counter value using IWDG_SetReload() function.\r\n * This value will be loaded in the IWDG counter each time the counter\r\n * is reloaded, then the IWDG will start counting down from this value.\r\n * \r\n * 4. Start the IWDG using IWDG_Enable() function, when the IWDG is used\r\n * in software mode (no need to enable the LSI, it will be enabled\r\n * by hardware)\r\n * \r\n * 5. Then the application program must reload the IWDG counter at regular\r\n * intervals during normal operation to prevent an MCU reset, using\r\n * IWDG_ReloadCounter() function. \r\n * \r\n * @endverbatim\r\n * \r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx_iwdg.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @defgroup IWDG \r\n * @brief IWDG driver modules\r\n * @{\r\n */ \r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n\r\n/* KR register bit mask */\r\n#define KR_KEY_RELOAD ((uint16_t)0xAAAA)\r\n#define KR_KEY_ENABLE ((uint16_t)0xCCCC)\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup IWDG_Private_Functions\r\n * @{\r\n */\r\n\r\n/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions\r\n * @brief Prescaler and Counter configuration functions\r\n *\r\n@verbatim \r\n ===============================================================================\r\n Prescaler and Counter configuration functions\r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.\r\n * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.\r\n * This parameter can be one of the following values:\r\n * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers\r\n * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers\r\n * @retval None\r\n */\r\nvoid IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));\r\n IWDG->KR = IWDG_WriteAccess;\r\n}\r\n\r\n/**\r\n * @brief Sets IWDG Prescaler value.\r\n * @param IWDG_Prescaler: specifies the IWDG Prescaler value.\r\n * This parameter can be one of the following values:\r\n * @arg IWDG_Prescaler_4: IWDG prescaler set to 4\r\n * @arg IWDG_Prescaler_8: IWDG prescaler set to 8\r\n * @arg IWDG_Prescaler_16: IWDG prescaler set to 16\r\n * @arg IWDG_Prescaler_32: IWDG prescaler set to 32\r\n * @arg IWDG_Prescaler_64: IWDG prescaler set to 64\r\n * @arg IWDG_Prescaler_128: IWDG prescaler set to 128\r\n * @arg IWDG_Prescaler_256: IWDG prescaler set to 256\r\n * @retval None\r\n */\r\nvoid IWDG_SetPrescaler(uint8_t IWDG_Prescaler)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));\r\n IWDG->PR = IWDG_Prescaler;\r\n}\r\n\r\n/**\r\n * @brief Sets IWDG Reload value.\r\n * @param Reload: specifies the IWDG Reload value.\r\n * This parameter must be a number between 0 and 0x0FFF.\r\n * @retval None\r\n */\r\nvoid IWDG_SetReload(uint16_t Reload)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_IWDG_RELOAD(Reload));\r\n IWDG->RLR = Reload;\r\n}\r\n\r\n/**\r\n * @brief Reloads IWDG counter with value defined in the reload register\r\n * (write access to IWDG_PR and IWDG_RLR registers disabled).\r\n * @param None\r\n * @retval None\r\n */\r\nvoid IWDG_ReloadCounter(void)\r\n{\r\n IWDG->KR = KR_KEY_RELOAD;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup IWDG_Group2 IWDG activation function\r\n * @brief IWDG activation function \r\n *\r\n@verbatim \r\n ===============================================================================\r\n IWDG activation function\r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).\r\n * @param None\r\n * @retval None\r\n */\r\nvoid IWDG_Enable(void)\r\n{\r\n IWDG->KR = KR_KEY_ENABLE;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup IWDG_Group3 Flag management function \r\n * @brief Flag management function \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Flag management function \r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Checks whether the specified IWDG flag is set or not.\r\n * @param IWDG_FLAG: specifies the flag to check.\r\n * This parameter can be one of the following values:\r\n * @arg IWDG_FLAG_PVU: Prescaler Value Update on going\r\n * @arg IWDG_FLAG_RVU: Reload Value Update on going\r\n * @retval The new state of IWDG_FLAG (SET or RESET).\r\n */\r\nFlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)\r\n{\r\n FlagStatus bitstatus = RESET;\r\n /* Check the parameters */\r\n assert_param(IS_IWDG_FLAG(IWDG_FLAG));\r\n if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)\r\n {\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n bitstatus = RESET;\r\n }\r\n /* Return the flag status */\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_pwr.c", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_pwr.c\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file provides firmware functions to manage the following \r\n * functionalities of the Power Controller (PWR) peripheral: \r\n * - Backup Domain Access\r\n * - PVD configuration\r\n * - WakeUp pin configuration\r\n * - Main and Backup Regulators configuration\r\n * - FLASH Power Down configuration\r\n * - Low Power modes configuration\r\n * - Flags management\r\n * \r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx_pwr.h\"\r\n#include \"stm32f4xx_rcc.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @defgroup PWR \r\n * @brief PWR driver modules\r\n * @{\r\n */ \r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* --------- PWR registers bit address in the alias region ---------- */\r\n#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)\r\n\r\n/* --- CR Register ---*/\r\n\r\n/* Alias word address of DBP bit */\r\n#define CR_OFFSET (PWR_OFFSET + 0x00)\r\n#define DBP_BitNumber 0x08\r\n#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))\r\n\r\n/* Alias word address of PVDE bit */\r\n#define PVDE_BitNumber 0x04\r\n#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))\r\n\r\n/* Alias word address of FPDS bit */\r\n#define FPDS_BitNumber 0x09\r\n#define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4))\r\n\r\n/* Alias word address of PMODE bit */\r\n#define PMODE_BitNumber 0x0E\r\n#define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4))\r\n\r\n\r\n/* --- CSR Register ---*/\r\n\r\n/* Alias word address of EWUP bit */\r\n#define CSR_OFFSET (PWR_OFFSET + 0x04)\r\n#define EWUP_BitNumber 0x08\r\n#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))\r\n\r\n/* Alias word address of BRE bit */\r\n#define BRE_BitNumber 0x09\r\n#define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4))\r\n\r\n/* ------------------ PWR registers bit mask ------------------------ */\r\n\r\n/* CR register bit mask */\r\n#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)\r\n#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup PWR_Private_Functions\r\n * @{\r\n */\r\n\r\n/** @defgroup PWR_Group1 Backup Domain Access function \r\n * @brief Backup Domain Access function \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Backup Domain Access function \r\n =============================================================================== \r\n\r\n After reset, the backup domain (RTC registers, RTC backup data \r\n registers and backup SRAM) is protected against possible unwanted \r\n write accesses. \r\n To enable access to the RTC Domain and RTC registers, proceed as follows:\r\n - Enable the Power Controller (PWR) APB1 interface clock using the\r\n RCC_APB1PeriphClockCmd() function.\r\n - Enable access to RTC domain using the PWR_BackupAccessCmd() function.\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Deinitializes the PWR peripheral registers to their default reset values. \r\n * @param None\r\n * @retval None\r\n */\r\nvoid PWR_DeInit(void)\r\n{\r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);\r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);\r\n}\r\n\r\n/**\r\n * @brief Enables or disables access to the backup domain (RTC registers, RTC \r\n * backup data registers and backup SRAM).\r\n * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the \r\n * Backup Domain Access should be kept enabled.\r\n * @param NewState: new state of the access to the backup domain.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid PWR_BackupAccessCmd(FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup PWR_Group2 PVD configuration functions\r\n * @brief PVD configuration functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n PVD configuration functions\r\n =============================================================================== \r\n\r\n - The PVD is used to monitor the VDD power supply by comparing it to a threshold\r\n selected by the PVD Level (PLS[2:0] bits in the PWR_CR).\r\n - A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the \r\n PVD threshold. This event is internally connected to the EXTI line16\r\n and can generate an interrupt if enabled through the EXTI registers.\r\n - The PVD is stopped in Standby mode.\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).\r\n * @param PWR_PVDLevel: specifies the PVD detection level\r\n * This parameter can be one of the following values:\r\n * @arg PWR_PVDLevel_0\r\n * @arg PWR_PVDLevel_1\r\n * @arg PWR_PVDLevel_2\r\n * @arg PWR_PVDLevel_3\r\n * @arg PWR_PVDLevel_4\r\n * @arg PWR_PVDLevel_5\r\n * @arg PWR_PVDLevel_6\r\n * @arg PWR_PVDLevel_7\r\n * @note Refer to the electrical characteristics of your device datasheet for\r\n * more details about the voltage threshold corresponding to each \r\n * detection level.\r\n * @retval None\r\n */\r\nvoid PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)\r\n{\r\n uint32_t tmpreg = 0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));\r\n \r\n tmpreg = PWR->CR;\r\n \r\n /* Clear PLS[7:5] bits */\r\n tmpreg &= CR_PLS_MASK;\r\n \r\n /* Set PLS[7:5] bits according to PWR_PVDLevel value */\r\n tmpreg |= PWR_PVDLevel;\r\n \r\n /* Store the new value */\r\n PWR->CR = tmpreg;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the Power Voltage Detector(PVD).\r\n * @param NewState: new state of the PVD.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid PWR_PVDCmd(FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup PWR_Group3 WakeUp pin configuration functions\r\n * @brief WakeUp pin configuration functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n WakeUp pin configuration functions\r\n =============================================================================== \r\n\r\n - WakeUp pin is used to wakeup the system from Standby mode. This pin is \r\n forced in input pull down configuration and is active on rising edges.\r\n - There is only one WakeUp pin: WakeUp Pin 1 on PA.00.\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Enables or disables the WakeUp Pin functionality.\r\n * @param NewState: new state of the WakeUp Pin functionality.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid PWR_WakeUpPinCmd(FunctionalState NewState)\r\n{\r\n /* Check the parameters */ \r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup PWR_Group4 Main and Backup Regulators configuration functions\r\n * @brief Main and Backup Regulators configuration functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Main and Backup Regulators configuration functions\r\n =============================================================================== \r\n\r\n - The backup domain includes 4 Kbytes of backup SRAM accessible only from the \r\n CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is retained \r\n even in Standby or VBAT mode when the low power backup regulator is enabled. \r\n It can be considered as an internal EEPROM when VBAT is always present.\r\n You can use the PWR_BackupRegulatorCmd() function to enable the low power\r\n backup regulator and use the PWR_GetFlagStatus(PWR_FLAG_BRR) to check if it is\r\n ready or not. \r\n\r\n - When the backup domain is supplied by VDD (analog switch connected to VDD) \r\n the backup SRAM is powered from VDD which replaces the VBAT power supply to \r\n save battery life.\r\n\r\n - The backup SRAM is not mass erased by an tamper event. It is read protected \r\n to prevent confidential data, such as cryptographic private key, from being \r\n accessed. The backup SRAM can be erased only through the Flash interface when\r\n a protection level change from level 1 to level 0 is requested. \r\n Refer to the description of Read protection (RDP) in the Flash programming manual.\r\n\r\n - The main internal regulator can be configured to have a tradeoff between performance\r\n and power consumption when the device does not operate at the maximum frequency. \r\n This is done through PWR_MainRegulatorModeConfig() function which configure VOS bit\r\n in PWR_CR register: \r\n - When this bit is set (Regulator voltage output Scale 1 mode selected) the System\r\n frequency can go up to 168 MHz. \r\n - When this bit is reset (Regulator voltage output Scale 2 mode selected) the System\r\n frequency can go up to 144 MHz. \r\n Refer to the datasheets for more details.\r\n \r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Enables or disables the Backup Regulator.\r\n * @param NewState: new state of the Backup Regulator.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid PWR_BackupRegulatorCmd(FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)NewState;\r\n}\r\n\r\n/**\r\n * @brief Configures the main internal regulator output voltage.\r\n * @param PWR_Regulator_Voltage: specifies the regulator output voltage to achieve\r\n * a tradeoff between performance and power consumption when the device does\r\n * not operate at the maximum frequency (refer to the datasheets for more details).\r\n * This parameter can be one of the following values:\r\n * @arg PWR_Regulator_Voltage_Scale1: Regulator voltage output Scale 1 mode, \r\n * System frequency up to 168 MHz. \r\n * @arg PWR_Regulator_Voltage_Scale2: Regulator voltage output Scale 2 mode, \r\n * System frequency up to 144 MHz. \r\n * @retval None\r\n */\r\nvoid PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_PWR_REGULATOR_VOLTAGE(PWR_Regulator_Voltage));\r\n\r\n if (PWR_Regulator_Voltage == PWR_Regulator_Voltage_Scale2)\r\n {\r\n PWR->CR &= ~PWR_Regulator_Voltage_Scale1;\r\n }\r\n else\r\n { \r\n PWR->CR |= PWR_Regulator_Voltage_Scale1;\r\n }\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup PWR_Group5 FLASH Power Down configuration functions\r\n * @brief FLASH Power Down configuration functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n FLASH Power Down configuration functions\r\n =============================================================================== \r\n\r\n - By setting the FPDS bit in the PWR_CR register by using the PWR_FlashPowerDownCmd()\r\n function, the Flash memory also enters power down mode when the device enters \r\n Stop mode. When the Flash memory is in power down mode, an additional startup \r\n delay is incurred when waking up from Stop mode.\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Enables or disables the Flash Power Down in STOP mode.\r\n * @param NewState: new state of the Flash power mode.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid PWR_FlashPowerDownCmd(FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)NewState;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup PWR_Group6 Low Power modes configuration functions\r\n * @brief Low Power modes configuration functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Low Power modes configuration functions\r\n =============================================================================== \r\n\r\n The devices feature 3 low-power modes:\r\n - Sleep mode: Cortex-M4 core stopped, peripherals kept running.\r\n - Stop mode: all clocks are stopped, regulator running, regulator in low power mode\r\n - Standby mode: 1.2V domain powered off.\r\n \r\n Sleep mode\r\n ===========\r\n - Entry:\r\n - The Sleep mode is entered by using the __WFI() or __WFE() functions.\r\n - Exit:\r\n - Any peripheral interrupt acknowledged by the nested vectored interrupt \r\n controller (NVIC) can wake up the device from Sleep mode.\r\n\r\n Stop mode\r\n ==========\r\n In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,\r\n and the HSE RC oscillators are disabled. Internal SRAM and register contents \r\n are preserved.\r\n The voltage regulator can be configured either in normal or low-power mode.\r\n To minimize the consumption In Stop mode, FLASH can be powered off before \r\n entering the Stop mode. It can be switched on again by software after exiting \r\n the Stop mode using the PWR_FlashPowerDownCmd() function. \r\n \r\n - Entry:\r\n - The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,) \r\n function with regulator in LowPower or with Regulator ON.\r\n - Exit:\r\n - Any EXTI Line (Internal or External) configured in Interrupt/Event mode.\r\n \r\n Standby mode\r\n ============\r\n The Standby mode allows to achieve the lowest power consumption. It is based \r\n on the Cortex-M4 deepsleep mode, with the voltage regulator disabled. \r\n The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and \r\n the HSE oscillator are also switched off. SRAM and register contents are lost \r\n except for the RTC registers, RTC backup registers, backup SRAM and Standby \r\n circuitry.\r\n \r\n The voltage regulator is OFF.\r\n \r\n - Entry:\r\n - The Standby mode is entered using the PWR_EnterSTANDBYMode() function.\r\n - Exit:\r\n - WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,\r\n tamper event, time-stamp event, external reset in NRST pin, IWDG reset. \r\n\r\n Auto-wakeup (AWU) from low-power mode\r\n =====================================\r\n The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC \r\n Wakeup event, a tamper event, a time-stamp event, or a comparator event, \r\n without depending on an external interrupt (Auto-wakeup mode).\r\n\r\n - RTC auto-wakeup (AWU) from the Stop mode\r\n ----------------------------------------\r\n \r\n - To wake up from the Stop mode with an RTC alarm event, it is necessary to:\r\n - Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt \r\n or Event modes) using the EXTI_Init() function.\r\n - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function\r\n - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() \r\n and RTC_AlarmCmd() functions.\r\n - To wake up from the Stop mode with an RTC Tamper or time stamp event, it \r\n is necessary to:\r\n - Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt \r\n or Event modes) using the EXTI_Init() function.\r\n - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() \r\n function\r\n - Configure the RTC to detect the tamper or time stamp event using the\r\n RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()\r\n functions.\r\n - To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:\r\n - Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt \r\n or Event modes) using the EXTI_Init() function.\r\n - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function\r\n - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), \r\n RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.\r\n\r\n - RTC auto-wakeup (AWU) from the Standby mode\r\n -------------------------------------------\r\n - To wake up from the Standby mode with an RTC alarm event, it is necessary to:\r\n - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function\r\n - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() \r\n and RTC_AlarmCmd() functions.\r\n - To wake up from the Standby mode with an RTC Tamper or time stamp event, it \r\n is necessary to:\r\n - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() \r\n function\r\n - Configure the RTC to detect the tamper or time stamp event using the\r\n RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()\r\n functions.\r\n - To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:\r\n - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function\r\n - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), \r\n RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Enters STOP mode.\r\n * \r\n * @note In Stop mode, all I/O pins keep the same state as in Run mode.\r\n * @note When exiting Stop mode by issuing an interrupt or a wakeup event, \r\n * the HSI RC oscillator is selected as system clock.\r\n * @note When the voltage regulator operates in low power mode, an additional \r\n * startup delay is incurred when waking up from Stop mode. \r\n * By keeping the internal regulator ON during Stop mode, the consumption \r\n * is higher although the startup time is reduced. \r\n * \r\n * @param PWR_Regulator: specifies the regulator state in STOP mode.\r\n * This parameter can be one of the following values:\r\n * @arg PWR_Regulator_ON: STOP mode with regulator ON\r\n * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode\r\n * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.\r\n * This parameter can be one of the following values:\r\n * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction\r\n * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction\r\n * @retval None\r\n */\r\nvoid PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)\r\n{\r\n uint32_t tmpreg = 0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_PWR_REGULATOR(PWR_Regulator));\r\n assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));\r\n \r\n /* Select the regulator state in STOP mode ---------------------------------*/\r\n tmpreg = PWR->CR;\r\n /* Clear PDDS and LPDSR bits */\r\n tmpreg &= CR_DS_MASK;\r\n \r\n /* Set LPDSR bit according to PWR_Regulator value */\r\n tmpreg |= PWR_Regulator;\r\n \r\n /* Store the new value */\r\n PWR->CR = tmpreg;\r\n \r\n /* Set SLEEPDEEP bit of Cortex System Control Register */\r\n SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r\n \r\n /* Select STOP mode entry --------------------------------------------------*/\r\n if(PWR_STOPEntry == PWR_STOPEntry_WFI)\r\n { \r\n /* Request Wait For Interrupt */\r\n __WFI();\r\n }\r\n else\r\n {\r\n /* Request Wait For Event */\r\n __WFE();\r\n }\r\n /* Reset SLEEPDEEP bit of Cortex System Control Register */\r\n SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); \r\n}\r\n\r\n/**\r\n * @brief Enters STANDBY mode.\r\n * @note In Standby mode, all I/O pins are high impedance except for:\r\n * - Reset pad (still available) \r\n * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC \r\n * Alarm out, or RTC clock calibration out.\r\n * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. \r\n * - WKUP pin 1 (PA0) if enabled. \r\n * @param None\r\n * @retval None\r\n */\r\nvoid PWR_EnterSTANDBYMode(void)\r\n{\r\n /* Clear Wakeup flag */\r\n PWR->CR |= PWR_CR_CWUF;\r\n \r\n /* Select STANDBY mode */\r\n PWR->CR |= PWR_CR_PDDS;\r\n \r\n /* Set SLEEPDEEP bit of Cortex System Control Register */\r\n SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r\n \r\n/* This option is used to ensure that store operations are completed */\r\n#if defined ( __CC_ARM )\r\n __force_stores();\r\n#endif\r\n /* Request Wait For Interrupt */\r\n __WFI();\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup PWR_Group7 Flags management functions\r\n * @brief Flags management functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Flags management functions\r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Checks whether the specified PWR flag is set or not.\r\n * @param PWR_FLAG: specifies the flag to check.\r\n * This parameter can be one of the following values:\r\n * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event \r\n * was received from the WKUP pin or from the RTC alarm (Alarm A \r\n * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.\r\n * An additional wakeup event is detected if the WKUP pin is enabled \r\n * (by setting the EWUP bit) when the WKUP pin level is already high. \r\n * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was\r\n * resumed from StandBy mode. \r\n * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled \r\n * by the PWR_PVDCmd() function. The PVD is stopped by Standby mode \r\n * For this reason, this bit is equal to 0 after Standby or reset\r\n * until the PVDE bit is set.\r\n * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset \r\n * when the device wakes up from Standby mode or by a system reset \r\n * or power reset. \r\n * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage \r\n * scaling output selection is ready. \r\n * @retval The new state of PWR_FLAG (SET or RESET).\r\n */\r\nFlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)\r\n{\r\n FlagStatus bitstatus = RESET;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_PWR_GET_FLAG(PWR_FLAG));\r\n \r\n if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)\r\n {\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n bitstatus = RESET;\r\n }\r\n /* Return the flag status */\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @brief Clears the PWR's pending flags.\r\n * @param PWR_FLAG: specifies the flag to clear.\r\n * This parameter can be one of the following values:\r\n * @arg PWR_FLAG_WU: Wake Up flag\r\n * @arg PWR_FLAG_SB: StandBy flag\r\n * @retval None\r\n */\r\nvoid PWR_ClearFlag(uint32_t PWR_FLAG)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));\r\n \r\n PWR->CR |= PWR_FLAG << 2;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_rcc.c\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file provides firmware functions to manage the following \r\n * functionalities of the Reset and clock control (RCC) peripheral:\r\n * - Internal/external clocks, PLL, CSS and MCO configuration\r\n * - System, AHB and APB busses clocks configuration\r\n * - Peripheral clocks configuration\r\n * - Interrupts and flags management\r\n *\r\n * @verbatim\r\n * \r\n * ===================================================================\r\n * RCC specific features\r\n * ===================================================================\r\n * \r\n * After reset the device is running from Internal High Speed oscillator \r\n * (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache \r\n * and I-Cache are disabled, and all peripherals are off except internal\r\n * SRAM, Flash and JTAG.\r\n * - There is no prescaler on High speed (AHB) and Low speed (APB) busses;\r\n * all peripherals mapped on these busses are running at HSI speed.\r\n * \t - The clock for all peripherals is switched off, except the SRAM and FLASH.\r\n * - All GPIOs are in input floating state, except the JTAG pins which\r\n * are assigned to be used for debug purpose.\r\n * \r\n * Once the device started from reset, the user application has to: \r\n * - Configure the clock source to be used to drive the System clock\r\n * (if the application needs higher frequency/performance)\r\n * - Configure the System clock frequency and Flash settings \r\n * - Configure the AHB and APB busses prescalers\r\n * - Enable the clock for the peripheral(s) to be used\r\n * - Configure the clock source(s) for peripherals which clocks are not\r\n * derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) \r\n * \r\n * @endverbatim\r\n * \r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx_rcc.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @defgroup RCC \r\n * @brief RCC driver modules\r\n * @{\r\n */ \r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* ------------ RCC registers bit address in the alias region ----------- */\r\n#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)\r\n/* --- CR Register ---*/\r\n/* Alias word address of HSION bit */\r\n#define CR_OFFSET (RCC_OFFSET + 0x00)\r\n#define HSION_BitNumber 0x00\r\n#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))\r\n/* Alias word address of CSSON bit */\r\n#define CSSON_BitNumber 0x13\r\n#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))\r\n/* Alias word address of PLLON bit */\r\n#define PLLON_BitNumber 0x18\r\n#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))\r\n/* Alias word address of PLLI2SON bit */\r\n#define PLLI2SON_BitNumber 0x1A\r\n#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))\r\n\r\n/* --- CFGR Register ---*/\r\n/* Alias word address of I2SSRC bit */\r\n#define CFGR_OFFSET (RCC_OFFSET + 0x08)\r\n#define I2SSRC_BitNumber 0x17\r\n#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))\r\n\r\n/* --- BDCR Register ---*/\r\n/* Alias word address of RTCEN bit */\r\n#define BDCR_OFFSET (RCC_OFFSET + 0x70)\r\n#define RTCEN_BitNumber 0x0F\r\n#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))\r\n/* Alias word address of BDRST bit */\r\n#define BDRST_BitNumber 0x10\r\n#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))\r\n/* --- CSR Register ---*/\r\n/* Alias word address of LSION bit */\r\n#define CSR_OFFSET (RCC_OFFSET + 0x74)\r\n#define LSION_BitNumber 0x00\r\n#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))\r\n/* ---------------------- RCC registers bit mask ------------------------ */\r\n/* CFGR register bit mask */\r\n#define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF)\r\n#define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF)\r\n\r\n/* RCC Flag Mask */\r\n#define FLAG_MASK ((uint8_t)0x1F)\r\n\r\n/* CR register byte 3 (Bits[23:16]) base address */\r\n#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802)\r\n\r\n/* CIR register byte 2 (Bits[15:8]) base address */\r\n#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))\r\n\r\n/* CIR register byte 3 (Bits[23:16]) base address */\r\n#define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))\r\n\r\n/* BDCR register base address */\r\n#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\nstatic __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};\r\n\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup RCC_Private_Functions\r\n * @{\r\n */ \r\n\r\n/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions\r\n * @brief Internal and external clocks, PLL, CSS and MCO configuration functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Internal/external clocks, PLL, CSS and MCO configuration functions\r\n =============================================================================== \r\n\r\n This section provide functions allowing to configure the internal/external clocks,\r\n PLLs, CSS and MCO pins.\r\n \r\n 1. HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through\r\n the PLL as System clock source.\r\n\r\n 2. LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC\r\n clock source.\r\n\r\n 3. HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or\r\n through the PLL as System clock source. Can be used also as RTC clock source.\r\n\r\n 4. LSE (low-speed external), 32 KHz oscillator used as RTC clock source. \r\n\r\n 5. PLL (clocked by HSI or HSE), featuring two different output clocks:\r\n - The first output is used to generate the high speed system clock (up to 168 MHz)\r\n - The second output is used to generate the clock for the USB OTG FS (48 MHz),\r\n the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).\r\n\r\n 6. PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve \r\n high-quality audio performance on the I2S interface.\r\n \r\n 7. CSS (Clock security system), once enable and if a HSE clock failure occurs \r\n (HSE used directly or through PLL as System clock source), the System clock\r\n is automatically switched to HSI and an interrupt is generated if enabled. \r\n The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) \r\n exception vector. \r\n\r\n 8. MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL\r\n clock (through a configurable prescaler) on PA8 pin.\r\n\r\n 9. MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S\r\n clock (through a configurable prescaler) on PC9 pin.\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Resets the RCC clock configuration to the default reset state.\r\n * @note The default reset state of the clock configuration is given below:\r\n * - HSI ON and used as system clock source\r\n * - HSE, PLL and PLLI2S OFF\r\n * - AHB, APB1 and APB2 prescaler set to 1.\r\n * - CSS, MCO1 and MCO2 OFF\r\n * - All interrupts disabled\r\n * @note This function doesn't modify the configuration of the\r\n * - Peripheral clocks\r\n * - LSI, LSE and RTC clocks \r\n * @param None\r\n * @retval None\r\n */\r\nvoid RCC_DeInit(void)\r\n{\r\n /* Set HSION bit */\r\n RCC->CR |= (uint32_t)0x00000001;\r\n\r\n /* Reset CFGR register */\r\n RCC->CFGR = 0x00000000;\r\n\r\n /* Reset HSEON, CSSON and PLLON bits */\r\n RCC->CR &= (uint32_t)0xFEF6FFFF;\r\n\r\n /* Reset PLLCFGR register */\r\n RCC->PLLCFGR = 0x24003010;\r\n\r\n /* Reset HSEBYP bit */\r\n RCC->CR &= (uint32_t)0xFFFBFFFF;\r\n\r\n /* Disable all interrupts */\r\n RCC->CIR = 0x00000000;\r\n}\r\n\r\n/**\r\n * @brief Configures the External High Speed oscillator (HSE).\r\n * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application\r\n * software should wait on HSERDY flag to be set indicating that HSE clock\r\n * is stable and can be used to clock the PLL and/or system clock.\r\n * @note HSE state can not be changed if it is used directly or through the\r\n * PLL as system clock. In this case, you have to select another source\r\n * of the system clock then change the HSE state (ex. disable it).\r\n * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. \r\n * @note This function reset the CSSON bit, so if the Clock security system(CSS)\r\n * was previously enabled you have to enable it again after calling this\r\n * function. \r\n * @param RCC_HSE: specifies the new state of the HSE.\r\n * This parameter can be one of the following values:\r\n * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after\r\n * 6 HSE oscillator clock cycles.\r\n * @arg RCC_HSE_ON: turn ON the HSE oscillator\r\n * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock\r\n * @retval None\r\n */\r\nvoid RCC_HSEConfig(uint8_t RCC_HSE)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RCC_HSE(RCC_HSE));\r\n\r\n /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/\r\n *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF;\r\n\r\n /* Set the new HSE configuration -------------------------------------------*/\r\n *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE;\r\n}\r\n\r\n/**\r\n * @brief Waits for HSE start-up.\r\n * @note This functions waits on HSERDY flag to be set and return SUCCESS if \r\n * this flag is set, otherwise returns ERROR if the timeout is reached \r\n * and this flag is not set. The timeout value is defined by the constant\r\n * HSE_STARTUP_TIMEOUT in stm32f4xx.h file. You can tailor it depending\r\n * on the HSE crystal used in your application. \r\n * @param None\r\n * @retval An ErrorStatus enumeration value:\r\n * - SUCCESS: HSE oscillator is stable and ready to use\r\n * - ERROR: HSE oscillator not yet ready\r\n */\r\nErrorStatus RCC_WaitForHSEStartUp(void)\r\n{\r\n __IO uint32_t startupcounter = 0;\r\n ErrorStatus status = ERROR;\r\n FlagStatus hsestatus = RESET;\r\n /* Wait till HSE is ready and if Time out is reached exit */\r\n do\r\n {\r\n hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);\r\n startupcounter++;\r\n } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET));\r\n\r\n if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)\r\n {\r\n status = SUCCESS;\r\n }\r\n else\r\n {\r\n status = ERROR;\r\n }\r\n return (status);\r\n}\r\n\r\n/**\r\n * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.\r\n * @note The calibration is used to compensate for the variations in voltage\r\n * and temperature that influence the frequency of the internal HSI RC.\r\n * @param HSICalibrationValue: specifies the calibration trimming value.\r\n * This parameter must be a number between 0 and 0x1F.\r\n * @retval None\r\n */\r\nvoid RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)\r\n{\r\n uint32_t tmpreg = 0;\r\n /* Check the parameters */\r\n assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));\r\n\r\n tmpreg = RCC->CR;\r\n\r\n /* Clear HSITRIM[4:0] bits */\r\n tmpreg &= ~RCC_CR_HSITRIM;\r\n\r\n /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */\r\n tmpreg |= (uint32_t)HSICalibrationValue << 3;\r\n\r\n /* Store the new value */\r\n RCC->CR = tmpreg;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the Internal High Speed oscillator (HSI).\r\n * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.\r\n * It is used (enabled by hardware) as system clock source after startup\r\n * from Reset, wakeup from STOP and STANDBY mode, or in case of failure\r\n * of the HSE used directly or indirectly as system clock (if the Clock\r\n * Security System CSS is enabled). \r\n * @note HSI can not be stopped if it is used as system clock source. In this case,\r\n * you have to select another source of the system clock then stop the HSI. \r\n * @note After enabling the HSI, the application software should wait on HSIRDY\r\n * flag to be set indicating that HSI clock is stable and can be used as\r\n * system clock source. \r\n * @param NewState: new state of the HSI.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator\r\n * clock cycles. \r\n * @retval None\r\n */\r\nvoid RCC_HSICmd(FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;\r\n}\r\n\r\n/**\r\n * @brief Configures the External Low Speed oscillator (LSE).\r\n * @note As the LSE is in the Backup domain and write access is denied to\r\n * this domain after reset, you have to enable write access using \r\n * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE\r\n * (to be done once after reset). \r\n * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application\r\n * software should wait on LSERDY flag to be set indicating that LSE clock\r\n * is stable and can be used to clock the RTC.\r\n * @param RCC_LSE: specifies the new state of the LSE.\r\n * This parameter can be one of the following values:\r\n * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after\r\n * 6 LSE oscillator clock cycles.\r\n * @arg RCC_LSE_ON: turn ON the LSE oscillator\r\n * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock\r\n * @retval None\r\n */\r\nvoid RCC_LSEConfig(uint8_t RCC_LSE)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RCC_LSE(RCC_LSE));\r\n\r\n /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/\r\n /* Reset LSEON bit */\r\n *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;\r\n\r\n /* Reset LSEBYP bit */\r\n *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;\r\n\r\n /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */\r\n switch (RCC_LSE)\r\n {\r\n case RCC_LSE_ON:\r\n /* Set LSEON bit */\r\n *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;\r\n break;\r\n case RCC_LSE_Bypass:\r\n /* Set LSEBYP and LSEON bits */\r\n *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;\r\n break;\r\n default:\r\n break;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the Internal Low Speed oscillator (LSI).\r\n * @note After enabling the LSI, the application software should wait on \r\n * LSIRDY flag to be set indicating that LSI clock is stable and can\r\n * be used to clock the IWDG and/or the RTC.\r\n * @note LSI can not be disabled if the IWDG is running. \r\n * @param NewState: new state of the LSI.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator\r\n * clock cycles. \r\n * @retval None\r\n */\r\nvoid RCC_LSICmd(FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;\r\n}\r\n\r\n/**\r\n * @brief Configures the main PLL clock source, multiplication and division factors.\r\n * @note This function must be used only when the main PLL is disabled.\r\n * \r\n * @param RCC_PLLSource: specifies the PLL entry clock source.\r\n * This parameter can be one of the following values:\r\n * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry\r\n * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry\r\n * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. \r\n * \r\n * @param PLLM: specifies the division factor for PLL VCO input clock\r\n * This parameter must be a number between 0 and 63.\r\n * @note You have to set the PLLM parameter correctly to ensure that the VCO input\r\n * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency\r\n * of 2 MHz to limit PLL jitter.\r\n * \r\n * @param PLLN: specifies the multiplication factor for PLL VCO output clock\r\n * This parameter must be a number between 192 and 432.\r\n * @note You have to set the PLLN parameter correctly to ensure that the VCO\r\n * output frequency is between 192 and 432 MHz.\r\n * \r\n * @param PLLP: specifies the division factor for main system clock (SYSCLK)\r\n * This parameter must be a number in the range {2, 4, 6, or 8}.\r\n * @note You have to set the PLLP parameter correctly to not exceed 168 MHz on\r\n * the System clock frequency.\r\n * \r\n * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks\r\n * This parameter must be a number between 4 and 15.\r\n * @note If the USB OTG FS is used in your application, you have to set the\r\n * PLLQ parameter correctly to have 48 MHz clock for the USB. However,\r\n * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work\r\n * correctly.\r\n * \r\n * @retval None\r\n */\r\nvoid RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));\r\n assert_param(IS_RCC_PLLM_VALUE(PLLM));\r\n assert_param(IS_RCC_PLLN_VALUE(PLLN));\r\n assert_param(IS_RCC_PLLP_VALUE(PLLP));\r\n assert_param(IS_RCC_PLLQ_VALUE(PLLQ));\r\n\r\n RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |\r\n (PLLQ << 24);\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the main PLL.\r\n * @note After enabling the main PLL, the application software should wait on \r\n * PLLRDY flag to be set indicating that PLL clock is stable and can\r\n * be used as system clock source.\r\n * @note The main PLL can not be disabled if it is used as system clock source\r\n * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.\r\n * @param NewState: new state of the main PLL. This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid RCC_PLLCmd(FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;\r\n}\r\n\r\n/**\r\n * @brief Configures the PLLI2S clock multiplication and division factors.\r\n * \r\n * @note This function must be used only when the PLLI2S is disabled.\r\n * @note PLLI2S clock source is common with the main PLL (configured in \r\n * RCC_PLLConfig function ) \r\n * \r\n * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock\r\n * This parameter must be a number between 192 and 432.\r\n * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO \r\n * output frequency is between 192 and 432 MHz.\r\n * \r\n * @param PLLI2SR: specifies the division factor for I2S clock\r\n * This parameter must be a number between 2 and 7.\r\n * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz\r\n * on the I2S clock frequency.\r\n * \r\n * @retval None\r\n */\r\nvoid RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));\r\n assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR));\r\n\r\n RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28);\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the PLLI2S. \r\n * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. \r\n * @param NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid RCC_PLLI2SCmd(FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the Clock Security System.\r\n * @note If a failure is detected on the HSE oscillator clock, this oscillator\r\n * is automatically disabled and an interrupt is generated to inform the\r\n * software about the failure (Clock Security System Interrupt, CSSI),\r\n * allowing the MCU to perform rescue operations. The CSSI is linked to \r\n * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. \r\n * @param NewState: new state of the Clock Security System.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid RCC_ClockSecuritySystemCmd(FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;\r\n}\r\n\r\n/**\r\n * @brief Selects the clock source to output on MCO1 pin(PA8).\r\n * @note PA8 should be configured in alternate function mode.\r\n * @param RCC_MCO1Source: specifies the clock source to output.\r\n * This parameter can be one of the following values:\r\n * @arg RCC_MCO1Source_HSI: HSI clock selected as MCO1 source\r\n * @arg RCC_MCO1Source_LSE: LSE clock selected as MCO1 source\r\n * @arg RCC_MCO1Source_HSE: HSE clock selected as MCO1 source\r\n * @arg RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source\r\n * @param RCC_MCO1Div: specifies the MCO1 prescaler.\r\n * This parameter can be one of the following values:\r\n * @arg RCC_MCO1Div_1: no division applied to MCO1 clock\r\n * @arg RCC_MCO1Div_2: division by 2 applied to MCO1 clock\r\n * @arg RCC_MCO1Div_3: division by 3 applied to MCO1 clock\r\n * @arg RCC_MCO1Div_4: division by 4 applied to MCO1 clock\r\n * @arg RCC_MCO1Div_5: division by 5 applied to MCO1 clock\r\n * @retval None\r\n */\r\nvoid RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)\r\n{\r\n uint32_t tmpreg = 0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source));\r\n assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div)); \r\n\r\n tmpreg = RCC->CFGR;\r\n\r\n /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */\r\n tmpreg &= CFGR_MCO1_RESET_MASK;\r\n\r\n /* Select MCO1 clock source and prescaler */\r\n tmpreg |= RCC_MCO1Source | RCC_MCO1Div;\r\n\r\n /* Store the new value */\r\n RCC->CFGR = tmpreg; \r\n}\r\n\r\n/**\r\n * @brief Selects the clock source to output on MCO2 pin(PC9).\r\n * @note PC9 should be configured in alternate function mode.\r\n * @param RCC_MCO2Source: specifies the clock source to output.\r\n * This parameter can be one of the following values:\r\n * @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source\r\n * @arg RCC_MCO2Source_PLLI2SCLK: PLLI2S clock selected as MCO2 source\r\n * @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source\r\n * @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source\r\n * @param RCC_MCO2Div: specifies the MCO2 prescaler.\r\n * This parameter can be one of the following values:\r\n * @arg RCC_MCO2Div_1: no division applied to MCO2 clock\r\n * @arg RCC_MCO2Div_2: division by 2 applied to MCO2 clock\r\n * @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock\r\n * @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock\r\n * @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock\r\n * @retval None\r\n */\r\nvoid RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)\r\n{\r\n uint32_t tmpreg = 0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source));\r\n assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div));\r\n \r\n tmpreg = RCC->CFGR;\r\n \r\n /* Clear MCO2 and MCO2PRE[2:0] bits */\r\n tmpreg &= CFGR_MCO2_RESET_MASK;\r\n\r\n /* Select MCO2 clock source and prescaler */\r\n tmpreg |= RCC_MCO2Source | RCC_MCO2Div;\r\n\r\n /* Store the new value */\r\n RCC->CFGR = tmpreg; \r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions\r\n * @brief System, AHB and APB busses clocks configuration functions\r\n *\r\n@verbatim \r\n ===============================================================================\r\n System, AHB and APB busses clocks configuration functions\r\n =============================================================================== \r\n\r\n This section provide functions allowing to configure the System, AHB, APB1 and \r\n APB2 busses clocks.\r\n \r\n 1. Several clock sources can be used to drive the System clock (SYSCLK): HSI,\r\n HSE and PLL.\r\n The AHB clock (HCLK) is derived from System clock through configurable prescaler\r\n and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA, GPIO...).\r\n APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through \r\n configurable prescalers and used to clock the peripherals mapped on these busses.\r\n You can use \"RCC_GetClocksFreq()\" function to retrieve the frequencies of these clocks. \r\n\r\n@note All the peripheral clocks are derived from the System clock (SYSCLK) except:\r\n - I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or\r\n from an external clock mapped on the I2S_CKIN pin. \r\n You have to use RCC_I2SCLKConfig() function to configure this clock. \r\n - RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock\r\n divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd()\r\n functions to configure this clock. \r\n - USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz\r\n to work correctly, while the SDIO require a frequency equal or lower than\r\n to 48. This clock is derived of the main PLL through PLLQ divider.\r\n - IWDG clock which is always the LSI clock.\r\n \r\n 2. The maximum frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 82 MHz and PCLK1 42 MHz.\r\n Depending on the device voltage range, the maximum frequency should be \r\n adapted accordingly:\r\n +-------------------------------------------------------------------------------------+ \r\n | Latency | HCLK clock frequency (MHz) |\r\n | |---------------------------------------------------------------------| \r\n | | voltage range | voltage range | voltage range | voltage range |\r\n | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |\r\n |---------------|----------------|----------------|-----------------|-----------------| \r\n |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 |\r\n |---------------|----------------|----------------|-----------------|-----------------| \r\n |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 | \r\n |---------------|----------------|----------------|-----------------|-----------------| \r\n |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 |\r\n |---------------|----------------|----------------|-----------------|-----------------| \r\n |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 |\r\n |---------------|----------------|----------------|-----------------|-----------------| \r\n |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 |\r\n |---------------|----------------|----------------|-----------------|-----------------| \r\n |5WS(6CPU cycle)|120< HCLK <= 168|120< HCLK <= 144|90 < HCLK <= 108 |80 < HCLK <= 96 | \r\n |---------------|----------------|----------------|-----------------|-----------------| \r\n |6WS(7CPU cycle)| NA |144< HCLK <= 168|108 < HCLK <= 120|96 < HCLK <= 112 | \r\n |---------------|----------------|----------------|-----------------|-----------------| \r\n |7WS(8CPU cycle)| NA | NA |120 < HCLK <= 138|112 < HCLK <= 120| \r\n +-------------------------------------------------------------------------------------+ \r\n @note When VOS bit (in PWR_CR register) is reset to '0, the maximum value of HCLK is 144 MHz.\r\n You can use PWR_MainRegulatorModeConfig() function to set or reset this bit.\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Configures the system clock (SYSCLK).\r\n * @note The HSI is used (enabled by hardware) as system clock source after\r\n * startup from Reset, wake-up from STOP and STANDBY mode, or in case\r\n * of failure of the HSE used directly or indirectly as system clock\r\n * (if the Clock Security System CSS is enabled).\r\n * @note A switch from one clock source to another occurs only if the target\r\n * clock source is ready (clock stable after startup delay or PLL locked). \r\n * If a clock source which is not yet ready is selected, the switch will\r\n * occur when the clock source will be ready. \r\n * You can use RCC_GetSYSCLKSource() function to know which clock is\r\n * currently used as system clock source. \r\n * @param RCC_SYSCLKSource: specifies the clock source used as system clock.\r\n * This parameter can be one of the following values:\r\n * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source\r\n * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source\r\n * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source\r\n * @retval None\r\n */\r\nvoid RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)\r\n{\r\n uint32_t tmpreg = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));\r\n\r\n tmpreg = RCC->CFGR;\r\n\r\n /* Clear SW[1:0] bits */\r\n tmpreg &= ~RCC_CFGR_SW;\r\n\r\n /* Set SW[1:0] bits according to RCC_SYSCLKSource value */\r\n tmpreg |= RCC_SYSCLKSource;\r\n\r\n /* Store the new value */\r\n RCC->CFGR = tmpreg;\r\n}\r\n\r\n/**\r\n * @brief Returns the clock source used as system clock.\r\n * @param None\r\n * @retval The clock source used as system clock. The returned value can be one\r\n * of the following:\r\n * - 0x00: HSI used as system clock\r\n * - 0x04: HSE used as system clock\r\n * - 0x08: PLL used as system clock\r\n */\r\nuint8_t RCC_GetSYSCLKSource(void)\r\n{\r\n return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));\r\n}\r\n\r\n/**\r\n * @brief Configures the AHB clock (HCLK).\r\n * @note Depending on the device voltage range, the software has to set correctly\r\n * these bits to ensure that HCLK not exceed the maximum allowed frequency\r\n * (for more details refer to section above\r\n * \"CPU, AHB and APB busses clocks configuration functions\")\r\n * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from \r\n * the system clock (SYSCLK).\r\n * This parameter can be one of the following values:\r\n * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK\r\n * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2\r\n * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4\r\n * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8\r\n * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16\r\n * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64\r\n * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128\r\n * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256\r\n * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512\r\n * @retval None\r\n */\r\nvoid RCC_HCLKConfig(uint32_t RCC_SYSCLK)\r\n{\r\n uint32_t tmpreg = 0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_RCC_HCLK(RCC_SYSCLK));\r\n\r\n tmpreg = RCC->CFGR;\r\n\r\n /* Clear HPRE[3:0] bits */\r\n tmpreg &= ~RCC_CFGR_HPRE;\r\n\r\n /* Set HPRE[3:0] bits according to RCC_SYSCLK value */\r\n tmpreg |= RCC_SYSCLK;\r\n\r\n /* Store the new value */\r\n RCC->CFGR = tmpreg;\r\n}\r\n\r\n\r\n/**\r\n * @brief Configures the Low Speed APB clock (PCLK1).\r\n * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from \r\n * the AHB clock (HCLK).\r\n * This parameter can be one of the following values:\r\n * @arg RCC_HCLK_Div1: APB1 clock = HCLK\r\n * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2\r\n * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4\r\n * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8\r\n * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16\r\n * @retval None\r\n */\r\nvoid RCC_PCLK1Config(uint32_t RCC_HCLK)\r\n{\r\n uint32_t tmpreg = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_RCC_PCLK(RCC_HCLK));\r\n\r\n tmpreg = RCC->CFGR;\r\n\r\n /* Clear PPRE1[2:0] bits */\r\n tmpreg &= ~RCC_CFGR_PPRE1;\r\n\r\n /* Set PPRE1[2:0] bits according to RCC_HCLK value */\r\n tmpreg |= RCC_HCLK;\r\n\r\n /* Store the new value */\r\n RCC->CFGR = tmpreg;\r\n}\r\n\r\n/**\r\n * @brief Configures the High Speed APB clock (PCLK2).\r\n * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from \r\n * the AHB clock (HCLK).\r\n * This parameter can be one of the following values:\r\n * @arg RCC_HCLK_Div1: APB2 clock = HCLK\r\n * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2\r\n * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4\r\n * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8\r\n * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16\r\n * @retval None\r\n */\r\nvoid RCC_PCLK2Config(uint32_t RCC_HCLK)\r\n{\r\n uint32_t tmpreg = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_RCC_PCLK(RCC_HCLK));\r\n\r\n tmpreg = RCC->CFGR;\r\n\r\n /* Clear PPRE2[2:0] bits */\r\n tmpreg &= ~RCC_CFGR_PPRE2;\r\n\r\n /* Set PPRE2[2:0] bits according to RCC_HCLK value */\r\n tmpreg |= RCC_HCLK << 3;\r\n\r\n /* Store the new value */\r\n RCC->CFGR = tmpreg;\r\n}\r\n\r\n/**\r\n * @brief Returns the frequencies of different on chip clocks; SYSCLK, HCLK, \r\n * PCLK1 and PCLK2. \r\n * \r\n * @note The system frequency computed by this function is not the real \r\n * frequency in the chip. It is calculated based on the predefined \r\n * constant and the selected clock source:\r\n * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)\r\n * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)\r\n * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) \r\n * or HSI_VALUE(*) multiplied/divided by the PLL factors. \r\n * @note (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value\r\n * 16 MHz) but the real value may vary depending on the variations\r\n * in voltage and temperature.\r\n * @note (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value\r\n * 25 MHz), user has to ensure that HSE_VALUE is same as the real\r\n * frequency of the crystal used. Otherwise, this function may\r\n * have wrong result.\r\n * \r\n * @note The result of this function could be not correct when using fractional\r\n * value for HSE crystal.\r\n * \r\n * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold\r\n * the clocks frequencies.\r\n * \r\n * @note This function can be used by the user application to compute the \r\n * baudrate for the communication peripherals or configure other parameters.\r\n * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function\r\n * must be called to update the structure's field. Otherwise, any\r\n * configuration based on this function will be incorrect.\r\n * \r\n * @retval None\r\n */\r\nvoid RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)\r\n{\r\n uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;\r\n\r\n /* Get SYSCLK source -------------------------------------------------------*/\r\n tmp = RCC->CFGR & RCC_CFGR_SWS;\r\n\r\n switch (tmp)\r\n {\r\n case 0x00: /* HSI used as system clock source */\r\n RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;\r\n break;\r\n case 0x04: /* HSE used as system clock source */\r\n RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;\r\n break;\r\n case 0x08: /* PLL used as system clock source */\r\n\r\n /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN\r\n SYSCLK = PLL_VCO / PLLP\r\n */ \r\n pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;\r\n pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;\r\n \r\n if (pllsource != 0)\r\n {\r\n /* HSE used as PLL clock source */\r\n pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);\r\n }\r\n else\r\n {\r\n /* HSI used as PLL clock source */\r\n pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); \r\n }\r\n\r\n pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;\r\n RCC_Clocks->SYSCLK_Frequency = pllvco/pllp;\r\n break;\r\n default:\r\n RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;\r\n break;\r\n }\r\n /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/\r\n\r\n /* Get HCLK prescaler */\r\n tmp = RCC->CFGR & RCC_CFGR_HPRE;\r\n tmp = tmp >> 4;\r\n presc = APBAHBPrescTable[tmp];\r\n /* HCLK clock frequency */\r\n RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;\r\n\r\n /* Get PCLK1 prescaler */\r\n tmp = RCC->CFGR & RCC_CFGR_PPRE1;\r\n tmp = tmp >> 10;\r\n presc = APBAHBPrescTable[tmp];\r\n /* PCLK1 clock frequency */\r\n RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;\r\n\r\n /* Get PCLK2 prescaler */\r\n tmp = RCC->CFGR & RCC_CFGR_PPRE2;\r\n tmp = tmp >> 13;\r\n presc = APBAHBPrescTable[tmp];\r\n /* PCLK2 clock frequency */\r\n RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup RCC_Group3 Peripheral clocks configuration functions\r\n * @brief Peripheral clocks configuration functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Peripheral clocks configuration functions\r\n =============================================================================== \r\n\r\n This section provide functions allowing to configure the Peripheral clocks. \r\n \r\n 1. The RTC clock which is derived from the LSI, LSE or HSE clock divided by 2 to 31.\r\n \r\n 2. After restart from Reset or wakeup from STANDBY, all peripherals are off\r\n except internal SRAM, Flash and JTAG. Before to start using a peripheral you\r\n have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd()\r\n , RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.\r\n\r\n 3. To reset the peripherals configuration (to the default state after device reset)\r\n you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and \r\n RCC_APB1PeriphResetCmd() functions.\r\n \r\n 4. To further reduce power consumption in SLEEP mode the peripheral clocks can\r\n be disabled prior to executing the WFI or WFE instructions. You can do this\r\n using RCC_AHBPeriphClockLPModeCmd(), RCC_APB2PeriphClockLPModeCmd() and\r\n RCC_APB1PeriphClockLPModeCmd() functions. \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Configures the RTC clock (RTCCLK).\r\n * @note As the RTC clock configuration bits are in the Backup domain and write\r\n * access is denied to this domain after reset, you have to enable write\r\n * access using PWR_BackupAccessCmd(ENABLE) function before to configure\r\n * the RTC clock source (to be done once after reset). \r\n * @note Once the RTC clock is configured it can't be changed unless the \r\n * Backup domain is reset using RCC_BackupResetCmd() function, or by\r\n * a Power On Reset (POR).\r\n * \r\n * @param RCC_RTCCLKSource: specifies the RTC clock source.\r\n * This parameter can be one of the following values:\r\n * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock\r\n * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock\r\n * @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected\r\n * as RTC clock, where x:[2,31]\r\n * \r\n * @note If the LSE or LSI is used as RTC clock source, the RTC continues to\r\n * work in STOP and STANDBY modes, and can be used as wakeup source.\r\n * However, when the HSE clock is used as RTC clock source, the RTC\r\n * cannot be used in STOP and STANDBY modes. \r\n * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as\r\n * RTC clock source).\r\n * \r\n * @retval None\r\n */\r\nvoid RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)\r\n{\r\n uint32_t tmpreg = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));\r\n\r\n if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300)\r\n { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */\r\n tmpreg = RCC->CFGR;\r\n\r\n /* Clear RTCPRE[4:0] bits */\r\n tmpreg &= ~RCC_CFGR_RTCPRE;\r\n\r\n /* Configure HSE division factor for RTC clock */\r\n tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF);\r\n\r\n /* Store the new value */\r\n RCC->CFGR = tmpreg;\r\n }\r\n \r\n /* Select the RTC clock source */\r\n RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF);\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the RTC clock.\r\n * @note This function must be used only after the RTC clock source was selected\r\n * using the RCC_RTCCLKConfig function.\r\n * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid RCC_RTCCLKCmd(FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;\r\n}\r\n\r\n/**\r\n * @brief Forces or releases the Backup domain reset.\r\n * @note This function resets the RTC peripheral (including the backup registers)\r\n * and the RTC clock source selection in RCC_CSR register.\r\n * @note The BKPSRAM is not affected by this reset. \r\n * @param NewState: new state of the Backup domain reset.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid RCC_BackupResetCmd(FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;\r\n}\r\n\r\n/**\r\n * @brief Configures the I2S clock source (I2SCLK).\r\n * @note This function must be called before enabling the I2S APB clock.\r\n * @param RCC_I2SCLKSource: specifies the I2S clock source.\r\n * This parameter can be one of the following values:\r\n * @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source\r\n * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin\r\n * used as I2S clock source\r\n * @retval None\r\n */\r\nvoid RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));\r\n\r\n *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the AHB1 peripheral clock.\r\n * @note After reset, the peripheral clock (used for registers read/write access)\r\n * is disabled and the application software has to enable this clock before \r\n * using it. \r\n * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.\r\n * This parameter can be any combination of the following values:\r\n * @arg RCC_AHB1Periph_GPIOA: GPIOA clock\r\n * @arg RCC_AHB1Periph_GPIOB: GPIOB clock \r\n * @arg RCC_AHB1Periph_GPIOC: GPIOC clock\r\n * @arg RCC_AHB1Periph_GPIOD: GPIOD clock\r\n * @arg RCC_AHB1Periph_GPIOE: GPIOE clock\r\n * @arg RCC_AHB1Periph_GPIOF: GPIOF clock\r\n * @arg RCC_AHB1Periph_GPIOG: GPIOG clock\r\n * @arg RCC_AHB1Periph_GPIOG: GPIOG clock\r\n * @arg RCC_AHB1Periph_GPIOI: GPIOI clock\r\n * @arg RCC_AHB1Periph_CRC: CRC clock\r\n * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock\r\n * @arg RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock\r\n * @arg RCC_AHB1Periph_DMA1: DMA1 clock\r\n * @arg RCC_AHB1Periph_DMA2: DMA2 clock\r\n * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock\r\n * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock\r\n * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock\r\n * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock\r\n * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock\r\n * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock\r\n * @param NewState: new state of the specified peripheral clock.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph));\r\n\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n RCC->AHB1ENR |= RCC_AHB1Periph;\r\n }\r\n else\r\n {\r\n RCC->AHB1ENR &= ~RCC_AHB1Periph;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the AHB2 peripheral clock.\r\n * @note After reset, the peripheral clock (used for registers read/write access)\r\n * is disabled and the application software has to enable this clock before \r\n * using it. \r\n * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.\r\n * This parameter can be any combination of the following values:\r\n * @arg RCC_AHB2Periph_DCMI: DCMI clock\r\n * @arg RCC_AHB2Periph_CRYP: CRYP clock\r\n * @arg RCC_AHB2Periph_HASH: HASH clock\r\n * @arg RCC_AHB2Periph_RNG: RNG clock\r\n * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock\r\n * @param NewState: new state of the specified peripheral clock.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n if (NewState != DISABLE)\r\n {\r\n RCC->AHB2ENR |= RCC_AHB2Periph;\r\n }\r\n else\r\n {\r\n RCC->AHB2ENR &= ~RCC_AHB2Periph;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the AHB3 peripheral clock.\r\n * @note After reset, the peripheral clock (used for registers read/write access)\r\n * is disabled and the application software has to enable this clock before \r\n * using it. \r\n * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.\r\n * This parameter must be: RCC_AHB3Periph_FSMC\r\n * @param NewState: new state of the specified peripheral clock.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); \r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n if (NewState != DISABLE)\r\n {\r\n RCC->AHB3ENR |= RCC_AHB3Periph;\r\n }\r\n else\r\n {\r\n RCC->AHB3ENR &= ~RCC_AHB3Periph;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.\r\n * @note After reset, the peripheral clock (used for registers read/write access)\r\n * is disabled and the application software has to enable this clock before \r\n * using it. \r\n * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.\r\n * This parameter can be any combination of the following values:\r\n * @arg RCC_APB1Periph_TIM2: TIM2 clock\r\n * @arg RCC_APB1Periph_TIM3: TIM3 clock\r\n * @arg RCC_APB1Periph_TIM4: TIM4 clock\r\n * @arg RCC_APB1Periph_TIM5: TIM5 clock\r\n * @arg RCC_APB1Periph_TIM6: TIM6 clock\r\n * @arg RCC_APB1Periph_TIM7: TIM7 clock\r\n * @arg RCC_APB1Periph_TIM12: TIM12 clock\r\n * @arg RCC_APB1Periph_TIM13: TIM13 clock\r\n * @arg RCC_APB1Periph_TIM14: TIM14 clock\r\n * @arg RCC_APB1Periph_WWDG: WWDG clock\r\n * @arg RCC_APB1Periph_SPI2: SPI2 clock\r\n * @arg RCC_APB1Periph_SPI3: SPI3 clock\r\n * @arg RCC_APB1Periph_USART2: USART2 clock\r\n * @arg RCC_APB1Periph_USART3: USART3 clock\r\n * @arg RCC_APB1Periph_UART4: UART4 clock\r\n * @arg RCC_APB1Periph_UART5: UART5 clock\r\n * @arg RCC_APB1Periph_I2C1: I2C1 clock\r\n * @arg RCC_APB1Periph_I2C2: I2C2 clock\r\n * @arg RCC_APB1Periph_I2C3: I2C3 clock\r\n * @arg RCC_APB1Periph_CAN1: CAN1 clock\r\n * @arg RCC_APB1Periph_CAN2: CAN2 clock\r\n * @arg RCC_APB1Periph_PWR: PWR clock\r\n * @arg RCC_APB1Periph_DAC: DAC clock\r\n * @param NewState: new state of the specified peripheral clock.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); \r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n if (NewState != DISABLE)\r\n {\r\n RCC->APB1ENR |= RCC_APB1Periph;\r\n }\r\n else\r\n {\r\n RCC->APB1ENR &= ~RCC_APB1Periph;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the High Speed APB (APB2) peripheral clock.\r\n * @note After reset, the peripheral clock (used for registers read/write access)\r\n * is disabled and the application software has to enable this clock before \r\n * using it.\r\n * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.\r\n * This parameter can be any combination of the following values:\r\n * @arg RCC_APB2Periph_TIM1: TIM1 clock\r\n * @arg RCC_APB2Periph_TIM8: TIM8 clock\r\n * @arg RCC_APB2Periph_USART1: USART1 clock\r\n * @arg RCC_APB2Periph_USART6: USART6 clock\r\n * @arg RCC_APB2Periph_ADC1: ADC1 clock\r\n * @arg RCC_APB2Periph_ADC2: ADC2 clock\r\n * @arg RCC_APB2Periph_ADC3: ADC3 clock\r\n * @arg RCC_APB2Periph_SDIO: SDIO clock\r\n * @arg RCC_APB2Periph_SPI1: SPI1 clock\r\n * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock\r\n * @arg RCC_APB2Periph_TIM9: TIM9 clock\r\n * @arg RCC_APB2Periph_TIM10: TIM10 clock\r\n * @arg RCC_APB2Periph_TIM11: TIM11 clock\r\n * @param NewState: new state of the specified peripheral clock.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n if (NewState != DISABLE)\r\n {\r\n RCC->APB2ENR |= RCC_APB2Periph;\r\n }\r\n else\r\n {\r\n RCC->APB2ENR &= ~RCC_APB2Periph;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Forces or releases AHB1 peripheral reset.\r\n * @param RCC_AHB1Periph: specifies the AHB1 peripheral to reset.\r\n * This parameter can be any combination of the following values:\r\n * @arg RCC_AHB1Periph_GPIOA: GPIOA clock\r\n * @arg RCC_AHB1Periph_GPIOB: GPIOB clock \r\n * @arg RCC_AHB1Periph_GPIOC: GPIOC clock\r\n * @arg RCC_AHB1Periph_GPIOD: GPIOD clock\r\n * @arg RCC_AHB1Periph_GPIOE: GPIOE clock\r\n * @arg RCC_AHB1Periph_GPIOF: GPIOF clock\r\n * @arg RCC_AHB1Periph_GPIOG: GPIOG clock\r\n * @arg RCC_AHB1Periph_GPIOG: GPIOG clock\r\n * @arg RCC_AHB1Periph_GPIOI: GPIOI clock\r\n * @arg RCC_AHB1Periph_CRC: CRC clock\r\n * @arg RCC_AHB1Periph_DMA1: DMA1 clock\r\n * @arg RCC_AHB1Periph_DMA2: DMA2 clock\r\n * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock\r\n * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock\r\n * \r\n * @param NewState: new state of the specified peripheral reset.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n if (NewState != DISABLE)\r\n {\r\n RCC->AHB1RSTR |= RCC_AHB1Periph;\r\n }\r\n else\r\n {\r\n RCC->AHB1RSTR &= ~RCC_AHB1Periph;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Forces or releases AHB2 peripheral reset.\r\n * @param RCC_AHB2Periph: specifies the AHB2 peripheral to reset.\r\n * This parameter can be any combination of the following values:\r\n * @arg RCC_AHB2Periph_DCMI: DCMI clock\r\n * @arg RCC_AHB2Periph_CRYP: CRYP clock\r\n * @arg RCC_AHB2Periph_HASH: HASH clock\r\n * @arg RCC_AHB2Periph_RNG: RNG clock\r\n * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock\r\n * @param NewState: new state of the specified peripheral reset.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n if (NewState != DISABLE)\r\n {\r\n RCC->AHB2RSTR |= RCC_AHB2Periph;\r\n }\r\n else\r\n {\r\n RCC->AHB2RSTR &= ~RCC_AHB2Periph;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Forces or releases AHB3 peripheral reset.\r\n * @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset.\r\n * This parameter must be: RCC_AHB3Periph_FSMC\r\n * @param NewState: new state of the specified peripheral reset.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n if (NewState != DISABLE)\r\n {\r\n RCC->AHB3RSTR |= RCC_AHB3Periph;\r\n }\r\n else\r\n {\r\n RCC->AHB3RSTR &= ~RCC_AHB3Periph;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Forces or releases Low Speed APB (APB1) peripheral reset.\r\n * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.\r\n * This parameter can be any combination of the following values:\r\n * @arg RCC_APB1Periph_TIM2: TIM2 clock\r\n * @arg RCC_APB1Periph_TIM3: TIM3 clock\r\n * @arg RCC_APB1Periph_TIM4: TIM4 clock\r\n * @arg RCC_APB1Periph_TIM5: TIM5 clock\r\n * @arg RCC_APB1Periph_TIM6: TIM6 clock\r\n * @arg RCC_APB1Periph_TIM7: TIM7 clock\r\n * @arg RCC_APB1Periph_TIM12: TIM12 clock\r\n * @arg RCC_APB1Periph_TIM13: TIM13 clock\r\n * @arg RCC_APB1Periph_TIM14: TIM14 clock\r\n * @arg RCC_APB1Periph_WWDG: WWDG clock\r\n * @arg RCC_APB1Periph_SPI2: SPI2 clock\r\n * @arg RCC_APB1Periph_SPI3: SPI3 clock\r\n * @arg RCC_APB1Periph_USART2: USART2 clock\r\n * @arg RCC_APB1Periph_USART3: USART3 clock\r\n * @arg RCC_APB1Periph_UART4: UART4 clock\r\n * @arg RCC_APB1Periph_UART5: UART5 clock\r\n * @arg RCC_APB1Periph_I2C1: I2C1 clock\r\n * @arg RCC_APB1Periph_I2C2: I2C2 clock\r\n * @arg RCC_APB1Periph_I2C3: I2C3 clock\r\n * @arg RCC_APB1Periph_CAN1: CAN1 clock\r\n * @arg RCC_APB1Periph_CAN2: CAN2 clock\r\n * @arg RCC_APB1Periph_PWR: PWR clock\r\n * @arg RCC_APB1Periph_DAC: DAC clock\r\n * @param NewState: new state of the specified peripheral reset.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n RCC->APB1RSTR |= RCC_APB1Periph;\r\n }\r\n else\r\n {\r\n RCC->APB1RSTR &= ~RCC_APB1Periph;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Forces or releases High Speed APB (APB2) peripheral reset.\r\n * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.\r\n * This parameter can be any combination of the following values:\r\n * @arg RCC_APB2Periph_TIM1: TIM1 clock\r\n * @arg RCC_APB2Periph_TIM8: TIM8 clock\r\n * @arg RCC_APB2Periph_USART1: USART1 clock\r\n * @arg RCC_APB2Periph_USART6: USART6 clock\r\n * @arg RCC_APB2Periph_ADC1: ADC1 clock\r\n * @arg RCC_APB2Periph_ADC2: ADC2 clock\r\n * @arg RCC_APB2Periph_ADC3: ADC3 clock\r\n * @arg RCC_APB2Periph_SDIO: SDIO clock\r\n * @arg RCC_APB2Periph_SPI1: SPI1 clock\r\n * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock\r\n * @arg RCC_APB2Periph_TIM9: TIM9 clock\r\n * @arg RCC_APB2Periph_TIM10: TIM10 clock\r\n * @arg RCC_APB2Periph_TIM11: TIM11 clock\r\n * @param NewState: new state of the specified peripheral reset.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n RCC->APB2RSTR |= RCC_APB2Periph;\r\n }\r\n else\r\n {\r\n RCC->APB2RSTR &= ~RCC_APB2Periph;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.\r\n * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r\n * power consumption.\r\n * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n * @note By default, all peripheral clocks are enabled during SLEEP mode.\r\n * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.\r\n * This parameter can be any combination of the following values:\r\n * @arg RCC_AHB1Periph_GPIOA: GPIOA clock\r\n * @arg RCC_AHB1Periph_GPIOB: GPIOB clock \r\n * @arg RCC_AHB1Periph_GPIOC: GPIOC clock\r\n * @arg RCC_AHB1Periph_GPIOD: GPIOD clock\r\n * @arg RCC_AHB1Periph_GPIOE: GPIOE clock\r\n * @arg RCC_AHB1Periph_GPIOF: GPIOF clock\r\n * @arg RCC_AHB1Periph_GPIOG: GPIOG clock\r\n * @arg RCC_AHB1Periph_GPIOG: GPIOG clock\r\n * @arg RCC_AHB1Periph_GPIOI: GPIOI clock\r\n * @arg RCC_AHB1Periph_CRC: CRC clock\r\n * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock\r\n * @arg RCC_AHB1Periph_DMA1: DMA1 clock\r\n * @arg RCC_AHB1Periph_DMA2: DMA2 clock\r\n * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock\r\n * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock\r\n * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock\r\n * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock\r\n * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock\r\n * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock\r\n * @param NewState: new state of the specified peripheral clock.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n RCC->AHB1LPENR |= RCC_AHB1Periph;\r\n }\r\n else\r\n {\r\n RCC->AHB1LPENR &= ~RCC_AHB1Periph;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode.\r\n * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r\n * power consumption.\r\n * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n * @note By default, all peripheral clocks are enabled during SLEEP mode.\r\n * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.\r\n * This parameter can be any combination of the following values:\r\n * @arg RCC_AHB2Periph_DCMI: DCMI clock\r\n * @arg RCC_AHB2Periph_CRYP: CRYP clock\r\n * @arg RCC_AHB2Periph_HASH: HASH clock\r\n * @arg RCC_AHB2Periph_RNG: RNG clock\r\n * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock \r\n * @param NewState: new state of the specified peripheral clock.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n RCC->AHB2LPENR |= RCC_AHB2Periph;\r\n }\r\n else\r\n {\r\n RCC->AHB2LPENR &= ~RCC_AHB2Periph;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.\r\n * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r\n * power consumption.\r\n * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n * @note By default, all peripheral clocks are enabled during SLEEP mode.\r\n * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.\r\n * This parameter must be: RCC_AHB3Periph_FSMC\r\n * @param NewState: new state of the specified peripheral clock.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n RCC->AHB3LPENR |= RCC_AHB3Periph;\r\n }\r\n else\r\n {\r\n RCC->AHB3LPENR &= ~RCC_AHB3Periph;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.\r\n * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r\n * power consumption.\r\n * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n * @note By default, all peripheral clocks are enabled during SLEEP mode.\r\n * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.\r\n * This parameter can be any combination of the following values:\r\n * @arg RCC_APB1Periph_TIM2: TIM2 clock\r\n * @arg RCC_APB1Periph_TIM3: TIM3 clock\r\n * @arg RCC_APB1Periph_TIM4: TIM4 clock\r\n * @arg RCC_APB1Periph_TIM5: TIM5 clock\r\n * @arg RCC_APB1Periph_TIM6: TIM6 clock\r\n * @arg RCC_APB1Periph_TIM7: TIM7 clock\r\n * @arg RCC_APB1Periph_TIM12: TIM12 clock\r\n * @arg RCC_APB1Periph_TIM13: TIM13 clock\r\n * @arg RCC_APB1Periph_TIM14: TIM14 clock\r\n * @arg RCC_APB1Periph_WWDG: WWDG clock\r\n * @arg RCC_APB1Periph_SPI2: SPI2 clock\r\n * @arg RCC_APB1Periph_SPI3: SPI3 clock\r\n * @arg RCC_APB1Periph_USART2: USART2 clock\r\n * @arg RCC_APB1Periph_USART3: USART3 clock\r\n * @arg RCC_APB1Periph_UART4: UART4 clock\r\n * @arg RCC_APB1Periph_UART5: UART5 clock\r\n * @arg RCC_APB1Periph_I2C1: I2C1 clock\r\n * @arg RCC_APB1Periph_I2C2: I2C2 clock\r\n * @arg RCC_APB1Periph_I2C3: I2C3 clock\r\n * @arg RCC_APB1Periph_CAN1: CAN1 clock\r\n * @arg RCC_APB1Periph_CAN2: CAN2 clock\r\n * @arg RCC_APB1Periph_PWR: PWR clock\r\n * @arg RCC_APB1Periph_DAC: DAC clock\r\n * @param NewState: new state of the specified peripheral clock.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n RCC->APB1LPENR |= RCC_APB1Periph;\r\n }\r\n else\r\n {\r\n RCC->APB1LPENR &= ~RCC_APB1Periph;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.\r\n * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r\n * power consumption.\r\n * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n * @note By default, all peripheral clocks are enabled during SLEEP mode.\r\n * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.\r\n * This parameter can be any combination of the following values:\r\n * @arg RCC_APB2Periph_TIM1: TIM1 clock\r\n * @arg RCC_APB2Periph_TIM8: TIM8 clock\r\n * @arg RCC_APB2Periph_USART1: USART1 clock\r\n * @arg RCC_APB2Periph_USART6: USART6 clock\r\n * @arg RCC_APB2Periph_ADC1: ADC1 clock\r\n * @arg RCC_APB2Periph_ADC2: ADC2 clock\r\n * @arg RCC_APB2Periph_ADC3: ADC3 clock\r\n * @arg RCC_APB2Periph_SDIO: SDIO clock\r\n * @arg RCC_APB2Periph_SPI1: SPI1 clock\r\n * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock\r\n * @arg RCC_APB2Periph_TIM9: TIM9 clock\r\n * @arg RCC_APB2Periph_TIM10: TIM10 clock\r\n * @arg RCC_APB2Periph_TIM11: TIM11 clock\r\n * @param NewState: new state of the specified peripheral clock.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n RCC->APB2LPENR |= RCC_APB2Periph;\r\n }\r\n else\r\n {\r\n RCC->APB2LPENR &= ~RCC_APB2Periph;\r\n }\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup RCC_Group4 Interrupts and flags management functions\r\n * @brief Interrupts and flags management functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Interrupts and flags management functions\r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Enables or disables the specified RCC interrupts.\r\n * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.\r\n * This parameter can be any combination of the following values:\r\n * @arg RCC_IT_LSIRDY: LSI ready interrupt\r\n * @arg RCC_IT_LSERDY: LSE ready interrupt\r\n * @arg RCC_IT_HSIRDY: HSI ready interrupt\r\n * @arg RCC_IT_HSERDY: HSE ready interrupt\r\n * @arg RCC_IT_PLLRDY: main PLL ready interrupt\r\n * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt \r\n * @param NewState: new state of the specified RCC interrupts.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RCC_IT(RCC_IT));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */\r\n *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;\r\n }\r\n else\r\n {\r\n /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */\r\n *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Checks whether the specified RCC flag is set or not.\r\n * @param RCC_FLAG: specifies the flag to check.\r\n * This parameter can be one of the following values:\r\n * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready\r\n * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready\r\n * @arg RCC_FLAG_PLLRDY: main PLL clock ready\r\n * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready\r\n * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready\r\n * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready\r\n * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset\r\n * @arg RCC_FLAG_PINRST: Pin reset\r\n * @arg RCC_FLAG_PORRST: POR/PDR reset\r\n * @arg RCC_FLAG_SFTRST: Software reset\r\n * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset\r\n * @arg RCC_FLAG_WWDGRST: Window Watchdog reset\r\n * @arg RCC_FLAG_LPWRRST: Low Power reset\r\n * @retval The new state of RCC_FLAG (SET or RESET).\r\n */\r\nFlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)\r\n{\r\n uint32_t tmp = 0;\r\n uint32_t statusreg = 0;\r\n FlagStatus bitstatus = RESET;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_RCC_FLAG(RCC_FLAG));\r\n\r\n /* Get the RCC register index */\r\n tmp = RCC_FLAG >> 5;\r\n if (tmp == 1) /* The flag to check is in CR register */\r\n {\r\n statusreg = RCC->CR;\r\n }\r\n else if (tmp == 2) /* The flag to check is in BDCR register */\r\n {\r\n statusreg = RCC->BDCR;\r\n }\r\n else /* The flag to check is in CSR register */\r\n {\r\n statusreg = RCC->CSR;\r\n }\r\n\r\n /* Get the flag position */\r\n tmp = RCC_FLAG & FLAG_MASK;\r\n if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)\r\n {\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n bitstatus = RESET;\r\n }\r\n /* Return the flag status */\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @brief Clears the RCC reset flags.\r\n * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,\r\n * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST\r\n * @param None\r\n * @retval None\r\n */\r\nvoid RCC_ClearFlag(void)\r\n{\r\n /* Set RMVF bit to clear the reset flags */\r\n RCC->CSR |= RCC_CSR_RMVF;\r\n}\r\n\r\n/**\r\n * @brief Checks whether the specified RCC interrupt has occurred or not.\r\n * @param RCC_IT: specifies the RCC interrupt source to check.\r\n * This parameter can be one of the following values:\r\n * @arg RCC_IT_LSIRDY: LSI ready interrupt\r\n * @arg RCC_IT_LSERDY: LSE ready interrupt\r\n * @arg RCC_IT_HSIRDY: HSI ready interrupt\r\n * @arg RCC_IT_HSERDY: HSE ready interrupt\r\n * @arg RCC_IT_PLLRDY: main PLL ready interrupt\r\n * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt \r\n * @arg RCC_IT_CSS: Clock Security System interrupt\r\n * @retval The new state of RCC_IT (SET or RESET).\r\n */\r\nITStatus RCC_GetITStatus(uint8_t RCC_IT)\r\n{\r\n ITStatus bitstatus = RESET;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_RCC_GET_IT(RCC_IT));\r\n\r\n /* Check the status of the specified RCC interrupt */\r\n if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)\r\n {\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n bitstatus = RESET;\r\n }\r\n /* Return the RCC_IT status */\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @brief Clears the RCC's interrupt pending bits.\r\n * @param RCC_IT: specifies the interrupt pending bit to clear.\r\n * This parameter can be any combination of the following values:\r\n * @arg RCC_IT_LSIRDY: LSI ready interrupt\r\n * @arg RCC_IT_LSERDY: LSE ready interrupt\r\n * @arg RCC_IT_HSIRDY: HSI ready interrupt\r\n * @arg RCC_IT_HSERDY: HSE ready interrupt\r\n * @arg RCC_IT_PLLRDY: main PLL ready interrupt\r\n * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt \r\n * @arg RCC_IT_CSS: Clock Security System interrupt\r\n * @retval None\r\n */\r\nvoid RCC_ClearITPendingBit(uint8_t RCC_IT)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RCC_CLEAR_IT(RCC_IT));\r\n\r\n /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt\r\n pending bits */\r\n *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;\r\n}\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_rng.c\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file provides firmware functions to manage the following \r\n * functionalities of the Random Number Generator (RNG) peripheral: \r\n * - Initialization and Configuration \r\n * - Get 32 bit Random number \r\n * - Interrupts and flags management \r\n * \r\n * @verbatim\r\n * \r\n * =================================================================== \r\n * How to use this driver\r\n * =================================================================== \r\n * 1. Enable The RNG controller clock using \r\n * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_RNG, ENABLE) function.\r\n * \r\n * 2. Activate the RNG peripheral using RNG_Cmd() function.\r\n * \r\n * 3. Wait until the 32 bit Random number Generator contains a valid \r\n * random data (using polling/interrupt mode). For more details, \r\n * refer to \"Interrupts and flags management functions\" module \r\n * description.\r\n * \r\n * 4. Get the 32 bit Random number using RNG_GetRandomNumber() function\r\n * \r\n * 5. To get another 32 bit Random number, go to step 3. \r\n *\r\n * \r\n * \r\n * @endverbatim\r\n * \r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx_rng.h\"\r\n#include \"stm32f4xx_rcc.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @defgroup RNG \r\n * @brief RNG driver modules\r\n * @{\r\n */ \r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup RNG_Private_Functions\r\n * @{\r\n */ \r\n\r\n/** @defgroup RNG_Group1 Initialization and Configuration functions\r\n * @brief Initialization and Configuration functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Initialization and Configuration functions\r\n =============================================================================== \r\n This section provides functions allowing to \r\n - Initialize the RNG peripheral\r\n - Enable or disable the RNG peripheral\r\n \r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Deinitializes the RNG peripheral registers to their default reset values.\r\n * @param None\r\n * @retval None\r\n */\r\nvoid RNG_DeInit(void)\r\n{\r\n /* Enable RNG reset state */\r\n RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, ENABLE);\r\n\r\n /* Release RNG from reset state */\r\n RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, DISABLE);\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the RNG peripheral.\r\n * @param NewState: new state of the RNG peripheral.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid RNG_Cmd(FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the RNG */\r\n RNG->CR |= RNG_CR_RNGEN;\r\n }\r\n else\r\n {\r\n /* Disable the RNG */\r\n RNG->CR &= ~RNG_CR_RNGEN;\r\n }\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup RNG_Group2 Get 32 bit Random number function\r\n * @brief Get 32 bit Random number function \r\n *\r\n\r\n@verbatim \r\n ===============================================================================\r\n Get 32 bit Random number function\r\n =============================================================================== \r\n This section provides a function allowing to get the 32 bit Random number \r\n \r\n @note Before to call this function you have to wait till DRDY flag is set,\r\n using RNG_GetFlagStatus(RNG_FLAG_DRDY) function. \r\n \r\n@endverbatim\r\n * @{\r\n */\r\n\r\n\r\n/**\r\n * @brief Returns a 32-bit random number.\r\n * \r\n * @note Before to call this function you have to wait till DRDY (data ready)\r\n * flag is set, using RNG_GetFlagStatus(RNG_FLAG_DRDY) function.\r\n * @note Each time the the Random number data is read (using RNG_GetRandomNumber()\r\n * function), the RNG_FLAG_DRDY flag is automatically cleared.\r\n * @note In the case of a seed error, the generation of random numbers is \r\n * interrupted for as long as the SECS bit is '1'. If a number is \r\n * available in the RNG_DR register, it must not be used because it may \r\n * not have enough entropy. In this case, it is recommended to clear the \r\n * SEIS bit(using RNG_ClearFlag(RNG_FLAG_SECS) function), then disable \r\n * and enable the RNG peripheral (using RNG_Cmd() function) to \r\n * reinitialize and restart the RNG.\r\n * @note In the case of a clock error, the RNG is no more able to generate \r\n * random numbers because the PLL48CLK clock is not correct. User have \r\n * to check that the clock controller is correctly configured to provide\r\n * the RNG clock and clear the CEIS bit (using RNG_ClearFlag(RNG_FLAG_CECS) \r\n * function) . The clock error has no impact on the previously generated \r\n * random numbers, and the RNG_DR register contents can be used.\r\n * \r\n * @param None\r\n * @retval 32-bit random number.\r\n */\r\nuint32_t RNG_GetRandomNumber(void)\r\n{\r\n /* Return the 32 bit random number from the DR register */\r\n return RNG->DR;\r\n}\r\n\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup RNG_Group3 Interrupts and flags management functions\r\n * @brief Interrupts and flags management functions\r\n *\r\n@verbatim \r\n ===============================================================================\r\n Interrupts and flags management functions\r\n =============================================================================== \r\n\r\n This section provides functions allowing to configure the RNG Interrupts and \r\n to get the status and clear flags and Interrupts pending bits.\r\n \r\n The RNG provides 3 Interrupts sources and 3 Flags:\r\n \r\n Flags :\r\n ---------- \r\n 1. RNG_FLAG_DRDY : In the case of the RNG_DR register contains valid \r\n random data. it is cleared by reading the valid data \r\n (using RNG_GetRandomNumber() function).\r\n\r\n 2. RNG_FLAG_CECS : In the case of a seed error detection. \r\n \r\n 3. RNG_FLAG_SECS : In the case of a clock error detection.\r\n \r\n\r\n Interrupts :\r\n ------------\r\n if enabled, an RNG interrupt is pending :\r\n \r\n 1. In the case of the RNG_DR register contains valid random data. \r\n This interrupt source is cleared once the RNG_DR register has been read \r\n (using RNG_GetRandomNumber() function) until a new valid value is \r\n computed. \r\n \r\n or \r\n 2. In the case of a seed error : One of the following faulty sequences has \r\n been detected:\r\n - More than 64 consecutive bits at the same value (0 or 1)\r\n - More than 32 consecutive alternance of 0 and 1 (0101010101...01)\r\n This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_SEI)\r\n function.\r\n \r\n or\r\n 3. In the case of a clock error : the PLL48CLK (RNG peripheral clock source) \r\n was not correctly detected (fPLL48CLK< fHCLK/16).\r\n This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_CEI)\r\n function.\r\n @note In this case, User have to check that the clock controller is \r\n correctly configured to provide the RNG clock. \r\n\r\n Managing the RNG controller events :\r\n ------------------------------------ \r\n The user should identify which mode will be used in his application to manage \r\n the RNG controller events: Polling mode or Interrupt mode.\r\n \r\n 1. In the Polling Mode it is advised to use the following functions:\r\n - RNG_GetFlagStatus() : to check if flags events occur. \r\n - RNG_ClearFlag() : to clear the flags events.\r\n \r\n @note RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag(). it is cleared only \r\n by reading the Random number data. \r\n \r\n 2. In the Interrupt Mode it is advised to use the following functions:\r\n - RNG_ITConfig() : to enable or disable the interrupt source.\r\n - RNG_GetITStatus() : to check if Interrupt occurs.\r\n - RNG_ClearITPendingBit() : to clear the Interrupt pending Bit \r\n (corresponding Flag). \r\n \r\n\r\n@endverbatim\r\n * @{\r\n */ \r\n\r\n/**\r\n * @brief Enables or disables the RNG interrupt.\r\n * @note The RNG provides 3 interrupt sources,\r\n * - Computed data is ready event (DRDY), and \r\n * - Seed error Interrupt (SEI) and \r\n * - Clock error Interrupt (CEI), \r\n * all these interrupts sources are enabled by setting the IE bit in \r\n * CR register. However, each interrupt have its specific status bit\r\n * (see RNG_GetITStatus() function) and clear bit except the DRDY event\r\n * (see RNG_ClearITPendingBit() function).\r\n * @param NewState: new state of the RNG interrupt.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid RNG_ITConfig(FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the RNG interrupt */\r\n RNG->CR |= RNG_CR_IE;\r\n }\r\n else\r\n {\r\n /* Disable the RNG interrupt */\r\n RNG->CR &= ~RNG_CR_IE;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Checks whether the specified RNG flag is set or not.\r\n * @param RNG_FLAG: specifies the RNG flag to check.\r\n * This parameter can be one of the following values:\r\n * @arg RNG_FLAG_DRDY: Data Ready flag.\r\n * @arg RNG_FLAG_CECS: Clock Error Current flag.\r\n * @arg RNG_FLAG_SECS: Seed Error Current flag.\r\n * @retval The new state of RNG_FLAG (SET or RESET).\r\n */\r\nFlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG)\r\n{\r\n FlagStatus bitstatus = RESET;\r\n /* Check the parameters */\r\n assert_param(IS_RNG_GET_FLAG(RNG_FLAG));\r\n\r\n /* Check the status of the specified RNG flag */\r\n if ((RNG->SR & RNG_FLAG) != (uint8_t)RESET)\r\n {\r\n /* RNG_FLAG is set */\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n /* RNG_FLAG is reset */\r\n bitstatus = RESET;\r\n }\r\n /* Return the RNG_FLAG status */\r\n return bitstatus;\r\n}\r\n\r\n\r\n/**\r\n * @brief Clears the RNG flags.\r\n * @param RNG_FLAG: specifies the flag to clear. \r\n * This parameter can be any combination of the following values:\r\n * @arg RNG_FLAG_CECS: Clock Error Current flag.\r\n * @arg RNG_FLAG_SECS: Seed Error Current flag.\r\n * @note RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag() function. \r\n * This flag is cleared only by reading the Random number data (using \r\n * RNG_GetRandomNumber() function). \r\n * @retval None\r\n */\r\nvoid RNG_ClearFlag(uint8_t RNG_FLAG)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RNG_CLEAR_FLAG(RNG_FLAG));\r\n /* Clear the selected RNG flags */\r\n RNG->SR = ~(uint32_t)(((uint32_t)RNG_FLAG) << 4);\r\n}\r\n\r\n/**\r\n * @brief Checks whether the specified RNG interrupt has occurred or not.\r\n * @param RNG_IT: specifies the RNG interrupt source to check.\r\n * This parameter can be one of the following values:\r\n * @arg RNG_IT_CEI: Clock Error Interrupt.\r\n * @arg RNG_IT_SEI: Seed Error Interrupt. \r\n * @retval The new state of RNG_IT (SET or RESET).\r\n */\r\nITStatus RNG_GetITStatus(uint8_t RNG_IT)\r\n{\r\n ITStatus bitstatus = RESET;\r\n /* Check the parameters */\r\n assert_param(IS_RNG_GET_IT(RNG_IT));\r\n\r\n /* Check the status of the specified RNG interrupt */\r\n if ((RNG->SR & RNG_IT) != (uint8_t)RESET)\r\n {\r\n /* RNG_IT is set */\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n /* RNG_IT is reset */\r\n bitstatus = RESET;\r\n }\r\n /* Return the RNG_IT status */\r\n return bitstatus;\r\n}\r\n\r\n\r\n/**\r\n * @brief Clears the RNG interrupt pending bit(s).\r\n * @param RNG_IT: specifies the RNG interrupt pending bit(s) to clear.\r\n * This parameter can be any combination of the following values:\r\n * @arg RNG_IT_CEI: Clock Error Interrupt.\r\n * @arg RNG_IT_SEI: Seed Error Interrupt.\r\n * @retval None\r\n */\r\nvoid RNG_ClearITPendingBit(uint8_t RNG_IT)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RNG_IT(RNG_IT));\r\n\r\n /* Clear the selected RNG interrupt pending bit */\r\n RNG->SR = (uint8_t)~RNG_IT;\r\n}\r\n/**\r\n * @}\r\n */ \r\n \r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_rtc.c\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file provides firmware functions to manage the following \r\n * functionalities of the Real-Time Clock (RTC) peripheral:\r\n * - Initialization\r\n * - Calendar (Time and Date) configuration\r\n * - Alarms (Alarm A and Alarm B) configuration\r\n * - WakeUp Timer configuration\r\n * - Daylight Saving configuration\r\n * - Output pin Configuration\r\n * - Coarse digital Calibration configuration\r\n * - Smooth digital Calibration configuration\r\n * - TimeStamp configuration\r\n * - Tampers configuration\r\n * - Backup Data Registers configuration\r\n * - Shift control synchronisation \r\n * - RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration\r\n * - Interrupts and flags management\r\n *\r\n * @verbatim\r\n *\r\n * ===================================================================\r\n * Backup Domain Operating Condition\r\n * ===================================================================\r\n * The real-time clock (RTC), the RTC backup registers, and the backup \r\n * SRAM (BKP SRAM) can be powered from the VBAT voltage when the main \r\n * VDD supply is powered off.\r\n * To retain the content of the RTC backup registers, backup SRAM, \r\n * and supply the RTC when VDD is turned off, VBAT pin can be connected \r\n * to an optional standby voltage supplied by a battery or by another \r\n * source.\r\n *\r\n * To allow the RTC to operate even when the main digital supply (VDD) \r\n * is turned off, the VBAT pin powers the following blocks:\r\n * 1 - The RTC\r\n * 2 - The LSE oscillator\r\n * 3 - The backup SRAM when the low power backup regulator is enabled\r\n * 4 - PC13 to PC15 I/Os, plus PI8 I/O (when available)\r\n *\r\n * When the backup domain is supplied by VDD (analog switch connected \r\n * to VDD), the following functions are available:\r\n * 1 - PC14 and PC15 can be used as either GPIO or LSE pins\r\n * 2 - PC13 can be used as a GPIO or as the RTC_AF1 pin\r\n * 3 - PI8 can be used as a GPIO or as the RTC_AF2 pin\r\n *\r\n * When the backup domain is supplied by VBAT (analog switch connected \r\n * to VBAT because VDD is not present), the following functions are available:\r\n * 1 - PC14 and PC15 can be used as LSE pins only\r\n * 2 - PC13 can be used as the RTC_AF1 pin \r\n * 3 - PI8 can be used as the RTC_AF2 pin\r\n *\r\n * ===================================================================\r\n * Backup Domain Reset\r\n * ===================================================================\r\n * The backup domain reset sets all RTC registers and the RCC_BDCR \r\n * register to their reset values. The BKPSRAM is not affected by this\r\n * reset. The only way of resetting the BKPSRAM is through the Flash \r\n * interface by requesting a protection level change from 1 to 0.\r\n * A backup domain reset is generated when one of the following events\r\n * occurs:\r\n * 1 - Software reset, triggered by setting the BDRST bit in the \r\n * RCC Backup domain control register (RCC_BDCR). You can use the\r\n * RCC_BackupResetCmd().\r\n * 2 - VDD or VBAT power on, if both supplies have previously been\r\n * powered off.\r\n *\r\n * ===================================================================\r\n * Backup Domain Access\r\n * ===================================================================\r\n * After reset, the backup domain (RTC registers, RTC backup data \r\n * registers and backup SRAM) is protected against possible unwanted \r\n * write accesses. \r\n * To enable access to the RTC Domain and RTC registers, proceed as follows:\r\n * - Enable the Power Controller (PWR) APB1 interface clock using the\r\n * RCC_APB1PeriphClockCmd() function.\r\n * - Enable access to RTC domain using the PWR_BackupAccessCmd() function.\r\n * - Select the RTC clock source using the RCC_RTCCLKConfig() function.\r\n * - Enable RTC Clock using the RCC_RTCCLKCmd() function.\r\n *\r\n * ===================================================================\r\n * RTC Driver: how to use it\r\n * ===================================================================\r\n * - Enable the RTC domain access (see description in the section above)\r\n * - Configure the RTC Prescaler (Asynchronous and Synchronous) and\r\n * RTC hour format using the RTC_Init() function.\r\n *\r\n * Time and Date configuration\r\n * ===========================\r\n * - To configure the RTC Calendar (Time and Date) use the RTC_SetTime()\r\n * and RTC_SetDate() functions.\r\n * - To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate()\r\n * functions.\r\n * - Use the RTC_DayLightSavingConfig() function to add or sub one\r\n * hour to the RTC Calendar. \r\n *\r\n * Alarm configuration\r\n * ===================\r\n * - To configure the RTC Alarm use the RTC_SetAlarm() function.\r\n * - Enable the selected RTC Alarm using the RTC_AlarmCmd() function\r\n * - To read the RTC Alarm, use the RTC_GetAlarm() function.\r\n * - To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function.\r\n *\r\n * RTC Wakeup configuration\r\n * ========================\r\n * - Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig()\r\n * function.\r\n * - Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() \r\n * function \r\n * - Enable the RTC WakeUp using the RTC_WakeUpCmd() function \r\n * - To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter() \r\n * function.\r\n *\r\n * Outputs configuration\r\n * =====================\r\n * The RTC has 2 different outputs:\r\n * - AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B\r\n * and WaKeUp signals. \r\n * To output the selected RTC signal on RTC_AF1 pin, use the \r\n * RTC_OutputConfig() function. \r\n * - AFO_CALIB: this output is 512Hz signal or 1Hz . \r\n * To output the RTC Clock on RTC_AF1 pin, use the RTC_CalibOutputCmd()\r\n * function.\r\n *\r\n * Smooth digital Calibration configuration\r\n * ================================= \r\n * - Configure the RTC Original Digital Calibration Value and the corresponding\r\n * calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig() \r\n * function.\r\n *\r\n * Coarse digital Calibration configuration\r\n * =================================\r\n * - Configure the RTC Coarse Calibration Value and the corresponding\r\n * sign using the RTC_CoarseCalibConfig() function.\r\n * - Enable the RTC Coarse Calibration using the RTC_CoarseCalibCmd() \r\n * function \r\n *\r\n * TimeStamp configuration\r\n * =======================\r\n * - Configure the RTC_AF1 trigger and enables the RTC TimeStamp \r\n * using the RTC_TimeStampCmd() function.\r\n * - To read the RTC TimeStamp Time and Date register, use the \r\n * RTC_GetTimeStamp() function.\r\n * - To read the RTC TimeStamp SubSecond register, use the \r\n * RTC_GetTimeStampSubSecond() function.\r\n * - The TAMPER1 alternate function can be mapped either to RTC_AF1(PC13)\r\n * or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in \r\n * RTC_TAFCR register. You can use the RTC_TamperPinSelection()\r\n * function to select the corresponding pin. \r\n *\r\n * Tamper configuration\r\n * ====================\r\n * - Enable the RTC Tamper using the RTC_TamperCmd() function.\r\n * - Configure the Tamper filter count using RTC_TamperFilterConfig()\r\n * function. \r\n * - Configure the RTC Tamper trigger Edge or Level according to the Tamper \r\n * filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig() function.\r\n * - Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig()\r\n * function.\r\n * - Configure the Tamper precharge or discharge duration using \r\n * RTC_TamperPinsPrechargeDuration() function.\r\n * - Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function.\r\n * - Enable the Time stamp on Tamper detection event using \r\n * RTC_TSOnTamperDetecCmd() function.\r\n * - The TIMESTAMP alternate function can be mapped to either RTC_AF1 \r\n * or RTC_AF2 depending on the value of the TSINSEL bit in the \r\n * RTC_TAFCR register. You can use the RTC_TimeStampPinSelection()\r\n * function to select the corresponding pin. \r\n *\r\n * Backup Data Registers configuration\r\n * ===================================\r\n * - To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister()\r\n * function. \r\n * - To read the RTC Backup Data registers, use the RTC_ReadBackupRegister()\r\n * function.\r\n * \r\n * ===================================================================\r\n * RTC and low power modes\r\n * ===================================================================\r\n * The MCU can be woken up from a low power mode by an RTC alternate \r\n * function.\r\n * The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), \r\n * RTC wakeup, RTC tamper event detection and RTC time stamp event detection.\r\n * These RTC alternate functions can wake up the system from the Stop \r\n * and Standby lowpower modes.\r\n * The system can also wake up from low power modes without depending \r\n * on an external interrupt (Auto-wakeup mode), by using the RTC alarm \r\n * or the RTC wakeup events.\r\n * The RTC provides a programmable time base for waking up from the \r\n * Stop or Standby mode at regular intervals.\r\n * Wakeup from STOP and Standby modes is possible only when the RTC \r\n * clock source is LSE or LSI.\r\n *\r\n * ===================================================================\r\n * Selection of RTC_AF1 alternate functions\r\n * ===================================================================\r\n * The RTC_AF1 pin (PC13) can be used for the following purposes:\r\n * - AFO_ALARM output\r\n * - AFO_CALIB output\r\n * - AFI_TAMPER\r\n * - AFI_TIMESTAMP\r\n *\r\n * +-------------------------------------------------------------------------------------------------------------+\r\n * | Pin |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE |\r\n * | configuration | ENABLED | ENABLED | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM |\r\n * | and function | | | | | selection | selection |Configuration |\r\n * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|\r\n * | Alarm out | | | | | Don't | Don't | |\r\n * | output OD | 1 |Don't care|Don't care | Don't care | care | care | 0 |\r\n * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|\r\n * | Alarm out | | | | | Don't | Don't | |\r\n * | output PP | 1 |Don't care|Don't care | Don't care | care | care | 1 |\r\n * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|\r\n * | Calibration out | | | | | Don't | Don't | |\r\n * | output PP | 0 | 1 |Don't care | Don't care | care | care | Don't care |\r\n * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|\r\n * | TAMPER input | | | | | | Don't | |\r\n * | floating | 0 | 0 | 1 | 0 | 0 | care | Don't care |\r\n * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|\r\n * | TIMESTAMP and | | | | | | | |\r\n * | TAMPER input | 0 | 0 | 1 | 1 | 0 | 0 | Don't care |\r\n * | floating | | | | | | | |\r\n * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|\r\n * | TIMESTAMP input | | | | | Don't | | |\r\n * | floating | 0 | 0 | 0 | 1 | care | 0 | Don't care |\r\n * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|\r\n * | Standard GPIO | 0 | 0 | 0 | 0 | Don't care | Don't care | Don't care |\r\n * +-------------------------------------------------------------------------------------------------------------+\r\n *\r\n *\r\n * ===================================================================\r\n * Selection of RTC_AF2 alternate functions\r\n * ===================================================================\r\n * The RTC_AF2 pin (PI8) can be used for the following purposes:\r\n * - AFI_TAMPER\r\n * - AFI_TIMESTAMP\r\n *\r\n * +---------------------------------------------------------------------------------------+\r\n * | Pin |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE |\r\n * | configuration | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM |\r\n * | and function | | | selection | selection |Configuration |\r\n * |-----------------|-----------|--------------|------------|--------------|--------------|\r\n * | TAMPER input | | | | Don't | |\r\n * | floating | 1 | 0 | 1 | care | Don't care |\r\n * |-----------------|-----------|--------------|------------|--------------|--------------|\r\n * | TIMESTAMP and | | | | | |\r\n * | TAMPER input | 1 | 1 | 1 | 1 | Don't care |\r\n * | floating | | | | | |\r\n * |-----------------|-----------|--------------|------------|--------------|--------------|\r\n * | TIMESTAMP input | | | Don't | | |\r\n * | floating | 0 | 1 | care | 1 | Don't care |\r\n * |-----------------|-----------|--------------|------------|--------------|--------------|\r\n * | Standard GPIO | 0 | 0 | Don't care | Don't care | Don't care |\r\n * +---------------------------------------------------------------------------------------+\r\n * \r\n *\r\n * @endverbatim\r\n *\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx_rtc.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @defgroup RTC \r\n * @brief RTC driver modules\r\n * @{\r\n */\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n\r\n/* Masks Definition */\r\n#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)\r\n#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) \r\n#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) \r\n#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)\r\n#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \\\r\n RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \\\r\n RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \\\r\n RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \\\r\n RTC_FLAG_RECALPF | RTC_FLAG_SHPF))\r\n\r\n#define INITMODE_TIMEOUT ((uint32_t) 0x00010000)\r\n#define SYNCHRO_TIMEOUT ((uint32_t) 0x00020000)\r\n#define RECALPF_TIMEOUT ((uint32_t) 0x00020000)\r\n#define SHPF_TIMEOUT ((uint32_t) 0x00001000)\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\nstatic uint8_t RTC_ByteToBcd2(uint8_t Value);\r\nstatic uint8_t RTC_Bcd2ToByte(uint8_t Value);\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup RTC_Private_Functions\r\n * @{\r\n */ \r\n\r\n/** @defgroup RTC_Group1 Initialization and Configuration functions\r\n * @brief Initialization and Configuration functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Initialization and Configuration functions\r\n ===============================================================================\r\n\r\n This section provide functions allowing to initialize and configure the RTC\r\n Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers\r\n Write protection, enter and exit the RTC initialization mode, RTC registers\r\n synchronization check and reference clock detection enable.\r\n \r\n 1. The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is\r\n split into 2 programmable prescalers to minimize power consumption.\r\n - A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler.\r\n - When both prescalers are used, it is recommended to configure the asynchronous\r\n prescaler to a high value to minimize consumption.\r\n\r\n 2. All RTC registers are Write protected. Writing to the RTC registers\r\n is enabled by writing a key into the Write Protection register, RTC_WPR.\r\n\r\n 3. To Configure the RTC Calendar, user application should enter initialization\r\n mode. In this mode, the calendar counter is stopped and its value can be \r\n updated. When the initialization sequence is complete, the calendar restarts \r\n counting after 4 RTCCLK cycles.\r\n\r\n 4. To read the calendar through the shadow registers after Calendar initialization,\r\n calendar update or after wakeup from low power modes the software must first \r\n clear the RSF flag. The software must then wait until it is set again before \r\n reading the calendar, which means that the calendar registers have been \r\n correctly copied into the RTC_TR and RTC_DR shadow registers.\r\n The RTC_WaitForSynchro() function implements the above software sequence \r\n (RSF clear and RSF check).\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Deinitializes the RTC registers to their default reset values.\r\n * @note This function doesn't reset the RTC Clock source and RTC Backup Data\r\n * registers. \r\n * @param None\r\n * @retval An ErrorStatus enumeration value:\r\n * - SUCCESS: RTC registers are deinitialized\r\n * - ERROR: RTC registers are not deinitialized\r\n */\r\nErrorStatus RTC_DeInit(void)\r\n{\r\n __IO uint32_t wutcounter = 0x00;\r\n uint32_t wutwfstatus = 0x00;\r\n ErrorStatus status = ERROR;\r\n \r\n /* Disable the write protection for RTC registers */\r\n RTC->WPR = 0xCA;\r\n RTC->WPR = 0x53;\r\n\r\n /* Set Initialization mode */\r\n if (RTC_EnterInitMode() == ERROR)\r\n {\r\n status = ERROR;\r\n } \r\n else\r\n {\r\n /* Reset TR, DR and CR registers */\r\n RTC->TR = (uint32_t)0x00000000;\r\n RTC->DR = (uint32_t)0x00002101;\r\n /* Reset All CR bits except CR[2:0] */\r\n RTC->CR &= (uint32_t)0x00000007;\r\n \r\n /* Wait till RTC WUTWF flag is set and if Time out is reached exit */\r\n do\r\n {\r\n wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;\r\n wutcounter++; \r\n } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));\r\n \r\n if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)\r\n {\r\n status = ERROR;\r\n }\r\n else\r\n {\r\n /* Reset all RTC CR register bits */\r\n RTC->CR &= (uint32_t)0x00000000;\r\n RTC->WUTR = (uint32_t)0x0000FFFF;\r\n RTC->PRER = (uint32_t)0x007F00FF;\r\n RTC->CALIBR = (uint32_t)0x00000000;\r\n RTC->ALRMAR = (uint32_t)0x00000000; \r\n RTC->ALRMBR = (uint32_t)0x00000000;\r\n RTC->SHIFTR = (uint32_t)0x00000000;\r\n RTC->CALR = (uint32_t)0x00000000;\r\n RTC->ALRMASSR = (uint32_t)0x00000000;\r\n RTC->ALRMBSSR = (uint32_t)0x00000000;\r\n \r\n /* Reset ISR register and exit initialization mode */\r\n RTC->ISR = (uint32_t)0x00000000;\r\n \r\n /* Reset Tamper and alternate functions configuration register */\r\n RTC->TAFCR = 0x00000000;\r\n \r\n if(RTC_WaitForSynchro() == ERROR)\r\n {\r\n status = ERROR;\r\n }\r\n else\r\n {\r\n status = SUCCESS; \r\n }\r\n }\r\n }\r\n \r\n /* Enable the write protection for RTC registers */\r\n RTC->WPR = 0xFF; \r\n \r\n return status;\r\n}\r\n\r\n/**\r\n * @brief Initializes the RTC registers according to the specified parameters \r\n * in RTC_InitStruct.\r\n * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains \r\n * the configuration information for the RTC peripheral.\r\n * @note The RTC Prescaler register is write protected and can be written in \r\n * initialization mode only. \r\n * @retval An ErrorStatus enumeration value:\r\n * - SUCCESS: RTC registers are initialized\r\n * - ERROR: RTC registers are not initialized \r\n */\r\nErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct)\r\n{\r\n ErrorStatus status = ERROR;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat));\r\n assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv));\r\n assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv));\r\n\r\n /* Disable the write protection for RTC registers */\r\n RTC->WPR = 0xCA;\r\n RTC->WPR = 0x53;\r\n\r\n /* Set Initialization mode */\r\n if (RTC_EnterInitMode() == ERROR)\r\n {\r\n status = ERROR;\r\n } \r\n else\r\n {\r\n /* Clear RTC CR FMT Bit */\r\n RTC->CR &= ((uint32_t)~(RTC_CR_FMT));\r\n /* Set RTC_CR register */\r\n RTC->CR |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat));\r\n \r\n /* Configure the RTC PRER */\r\n RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv);\r\n RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16);\r\n\r\n /* Exit Initialization mode */\r\n RTC_ExitInitMode();\r\n\r\n status = SUCCESS; \r\n }\r\n /* Enable the write protection for RTC registers */\r\n RTC->WPR = 0xFF; \r\n \r\n return status;\r\n}\r\n\r\n/**\r\n * @brief Fills each RTC_InitStruct member with its default value.\r\n * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be \r\n * initialized.\r\n * @retval None\r\n */\r\nvoid RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct)\r\n{\r\n /* Initialize the RTC_HourFormat member */\r\n RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24;\r\n \r\n /* Initialize the RTC_AsynchPrediv member */\r\n RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F;\r\n\r\n /* Initialize the RTC_SynchPrediv member */\r\n RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; \r\n}\r\n\r\n/**\r\n * @brief Enables or disables the RTC registers write protection.\r\n * @note All the RTC registers are write protected except for RTC_ISR[13:8], \r\n * RTC_TAFCR and RTC_BKPxR.\r\n * @note Writing a wrong key reactivates the write protection.\r\n * @note The protection mechanism is not affected by system reset. \r\n * @param NewState: new state of the write protection.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid RTC_WriteProtectionCmd(FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the write protection for RTC registers */\r\n RTC->WPR = 0xFF; \r\n }\r\n else\r\n {\r\n /* Disable the write protection for RTC registers */\r\n RTC->WPR = 0xCA;\r\n RTC->WPR = 0x53; \r\n }\r\n}\r\n\r\n/**\r\n * @brief Enters the RTC Initialization mode.\r\n * @note The RTC Initialization mode is write protected, use the \r\n * RTC_WriteProtectionCmd(DISABLE) before calling this function. \r\n * @param None\r\n * @retval An ErrorStatus enumeration value:\r\n * - SUCCESS: RTC is in Init mode\r\n * - ERROR: RTC is not in Init mode \r\n */\r\nErrorStatus RTC_EnterInitMode(void)\r\n{\r\n __IO uint32_t initcounter = 0x00;\r\n ErrorStatus status = ERROR;\r\n uint32_t initstatus = 0x00;\r\n \r\n /* Check if the Initialization mode is set */\r\n if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET)\r\n {\r\n /* Set the Initialization mode */\r\n RTC->ISR = (uint32_t)RTC_INIT_MASK;\r\n \r\n /* Wait till RTC is in INIT state and if Time out is reached exit */\r\n do\r\n {\r\n initstatus = RTC->ISR & RTC_ISR_INITF;\r\n initcounter++; \r\n } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));\r\n \r\n if ((RTC->ISR & RTC_ISR_INITF) != RESET)\r\n {\r\n status = SUCCESS;\r\n }\r\n else\r\n {\r\n status = ERROR;\r\n } \r\n }\r\n else\r\n {\r\n status = SUCCESS; \r\n } \r\n \r\n return (status); \r\n}\r\n\r\n/**\r\n * @brief Exits the RTC Initialization mode.\r\n * @note When the initialization sequence is complete, the calendar restarts \r\n * counting after 4 RTCCLK cycles. \r\n * @note The RTC Initialization mode is write protected, use the \r\n * RTC_WriteProtectionCmd(DISABLE) before calling this function. \r\n * @param None\r\n * @retval None\r\n */\r\nvoid RTC_ExitInitMode(void)\r\n{ \r\n /* Exit Initialization mode */\r\n RTC->ISR &= (uint32_t)~RTC_ISR_INIT; \r\n}\r\n\r\n/**\r\n * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are \r\n * synchronized with RTC APB clock.\r\n * @note The RTC Resynchronization mode is write protected, use the \r\n * RTC_WriteProtectionCmd(DISABLE) before calling this function. \r\n * @note To read the calendar through the shadow registers after Calendar \r\n * initialization, calendar update or after wakeup from low power modes \r\n * the software must first clear the RSF flag. \r\n * The software must then wait until it is set again before reading \r\n * the calendar, which means that the calendar registers have been \r\n * correctly copied into the RTC_TR and RTC_DR shadow registers. \r\n * @param None\r\n * @retval An ErrorStatus enumeration value:\r\n * - SUCCESS: RTC registers are synchronised\r\n * - ERROR: RTC registers are not synchronised\r\n */\r\nErrorStatus RTC_WaitForSynchro(void)\r\n{\r\n __IO uint32_t synchrocounter = 0;\r\n ErrorStatus status = ERROR;\r\n uint32_t synchrostatus = 0x00;\r\n\r\n /* Disable the write protection for RTC registers */\r\n RTC->WPR = 0xCA;\r\n RTC->WPR = 0x53;\r\n \r\n /* Clear RSF flag */\r\n RTC->ISR &= (uint32_t)RTC_RSF_MASK;\r\n \r\n /* Wait the registers to be synchronised */\r\n do\r\n {\r\n synchrostatus = RTC->ISR & RTC_ISR_RSF;\r\n synchrocounter++; \r\n } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));\r\n \r\n if ((RTC->ISR & RTC_ISR_RSF) != RESET)\r\n {\r\n status = SUCCESS;\r\n }\r\n else\r\n {\r\n status = ERROR;\r\n } \r\n\r\n /* Enable the write protection for RTC registers */\r\n RTC->WPR = 0xFF; \r\n \r\n return (status); \r\n}\r\n\r\n/**\r\n * @brief Enables or disables the RTC reference clock detection.\r\n * @param NewState: new state of the RTC reference clock.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval An ErrorStatus enumeration value:\r\n * - SUCCESS: RTC reference clock detection is enabled\r\n * - ERROR: RTC reference clock detection is disabled \r\n */\r\nErrorStatus RTC_RefClockCmd(FunctionalState NewState)\r\n{ \r\n ErrorStatus status = ERROR;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n /* Disable the write protection for RTC registers */\r\n RTC->WPR = 0xCA;\r\n RTC->WPR = 0x53;\r\n \r\n /* Set Initialization mode */\r\n if (RTC_EnterInitMode() == ERROR)\r\n {\r\n status = ERROR;\r\n } \r\n else\r\n { \r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the RTC reference clock detection */\r\n RTC->CR |= RTC_CR_REFCKON; \r\n }\r\n else\r\n {\r\n /* Disable the RTC reference clock detection */\r\n RTC->CR &= ~RTC_CR_REFCKON; \r\n }\r\n /* Exit Initialization mode */\r\n RTC_ExitInitMode();\r\n \r\n status = SUCCESS;\r\n }\r\n \r\n /* Enable the write protection for RTC registers */\r\n RTC->WPR = 0xFF; \r\n \r\n return status; \r\n}\r\n\r\n/**\r\n * @brief Enables or Disables the Bypass Shadow feature.\r\n * @note When the Bypass Shadow is enabled the calendar value are taken \r\n * directly from the Calendar counter.\r\n * @param NewState: new state of the Bypass Shadow feature.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n*/\r\nvoid RTC_BypassShadowCmd(FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n /* Disable the write protection for RTC registers */\r\n RTC->WPR = 0xCA;\r\n RTC->WPR = 0x53;\r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Set the BYPSHAD bit */\r\n RTC->CR |= (uint8_t)RTC_CR_BYPSHAD;\r\n }\r\n else\r\n {\r\n /* Reset the BYPSHAD bit */\r\n RTC->CR &= (uint8_t)~RTC_CR_BYPSHAD;\r\n }\r\n\r\n /* Enable the write protection for RTC registers */\r\n RTC->WPR = 0xFF;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup RTC_Group2 Time and Date configuration functions\r\n * @brief Time and Date configuration functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Time and Date configuration functions\r\n =============================================================================== \r\n\r\n This section provide functions allowing to program and read the RTC Calendar\r\n (Time and Date).\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Set the RTC current time.\r\n * @param RTC_Format: specifies the format of the entered parameters.\r\n * This parameter can be one of the following values:\r\n * @arg RTC_Format_BIN: Binary data format \r\n * @arg RTC_Format_BCD: BCD data format\r\n * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains \r\n * the time configuration information for the RTC. \r\n * @retval An ErrorStatus enumeration value:\r\n * - SUCCESS: RTC Time register is configured\r\n * - ERROR: RTC Time register is not configured\r\n */\r\nErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)\r\n{\r\n uint32_t tmpreg = 0;\r\n ErrorStatus status = ERROR;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_RTC_FORMAT(RTC_Format));\r\n \r\n if (RTC_Format == RTC_Format_BIN)\r\n {\r\n if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)\r\n {\r\n assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours));\r\n assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12));\r\n } \r\n else\r\n {\r\n RTC_TimeStruct->RTC_H12 = 0x00;\r\n assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours));\r\n }\r\n assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes));\r\n assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds));\r\n }\r\n else\r\n {\r\n if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)\r\n {\r\n tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);\r\n assert_param(IS_RTC_HOUR12(tmpreg));\r\n assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); \r\n } \r\n else\r\n {\r\n RTC_TimeStruct->RTC_H12 = 0x00;\r\n assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours)));\r\n }\r\n assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes)));\r\n assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds)));\r\n }\r\n \r\n /* Check the input parameters format */\r\n if (RTC_Format != RTC_Format_BIN)\r\n {\r\n tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \\\r\n ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \\\r\n ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \\\r\n ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16)); \r\n } \r\n else\r\n {\r\n tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \\\r\n ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \\\r\n ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \\\r\n (((uint32_t)RTC_TimeStruct->RTC_H12) << 16));\r\n } \r\n\r\n /* Disable the write protection for RTC registers */\r\n RTC->WPR = 0xCA;\r\n RTC->WPR = 0x53;\r\n\r\n /* Set Initialization mode */\r\n if (RTC_EnterInitMode() == ERROR)\r\n {\r\n status = ERROR;\r\n } \r\n else\r\n {\r\n /* Set the RTC_TR register */\r\n RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);\r\n\r\n /* Exit Initialization mode */\r\n RTC_ExitInitMode(); \r\n\r\n /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */\r\n if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)\r\n {\r\n if (RTC_WaitForSynchro() == ERROR)\r\n {\r\n status = ERROR;\r\n }\r\n else\r\n {\r\n status = SUCCESS;\r\n }\r\n }\r\n else\r\n {\r\n status = SUCCESS;\r\n }\r\n }\r\n /* Enable the write protection for RTC registers */\r\n RTC->WPR = 0xFF; \r\n \r\n return status;\r\n}\r\n\r\n/**\r\n * @brief Fills each RTC_TimeStruct member with its default value\r\n * (Time = 00h:00min:00sec).\r\n * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be \r\n * initialized.\r\n * @retval None\r\n */\r\nvoid RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct)\r\n{\r\n /* Time = 00h:00min:00sec */\r\n RTC_TimeStruct->RTC_H12 = RTC_H12_AM;\r\n RTC_TimeStruct->RTC_Hours = 0;\r\n RTC_TimeStruct->RTC_Minutes = 0;\r\n RTC_TimeStruct->RTC_Seconds = 0; \r\n}\r\n\r\n/**\r\n * @brief Get the RTC current Time.\r\n * @param RTC_Format: specifies the format of the returned parameters.\r\n * This parameter can be one of the following values:\r\n * @arg RTC_Format_BIN: Binary data format \r\n * @arg RTC_Format_BCD: BCD data format\r\n * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will \r\n * contain the returned current time configuration. \r\n * @retval None\r\n */\r\nvoid RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)\r\n{\r\n uint32_t tmpreg = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_RTC_FORMAT(RTC_Format));\r\n\r\n /* Get the RTC_TR register */\r\n tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); \r\n \r\n /* Fill the structure fields with the read parameters */\r\n RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);\r\n RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);\r\n RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));\r\n RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); \r\n\r\n /* Check the input parameters format */\r\n if (RTC_Format == RTC_Format_BIN)\r\n {\r\n /* Convert the structure parameters to Binary format */\r\n RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);\r\n RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes);\r\n RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds); \r\n }\r\n}\r\n\r\n/**\r\n * @brief Gets the RTC current Calendar Subseconds value.\r\n * @note This function freeze the Time and Date registers after reading the \r\n * SSR register.\r\n * @param None\r\n * @retval RTC current Calendar Subseconds value.\r\n */\r\nuint32_t RTC_GetSubSecond(void)\r\n{\r\n uint32_t tmpreg = 0;\r\n \r\n /* Get subseconds values from the correspondent registers*/\r\n tmpreg = (uint32_t)(RTC->SSR);\r\n \r\n /* Read DR register to unfroze calendar registers */\r\n (void) (RTC->DR);\r\n \r\n return (tmpreg);\r\n}\r\n\r\n/**\r\n * @brief Set the RTC current date.\r\n * @param RTC_Format: specifies the format of the entered parameters.\r\n * This parameter can be one of the following values:\r\n * @arg RTC_Format_BIN: Binary data format \r\n * @arg RTC_Format_BCD: BCD data format\r\n * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains \r\n * the date configuration information for the RTC.\r\n * @retval An ErrorStatus enumeration value:\r\n * - SUCCESS: RTC Date register is configured\r\n * - ERROR: RTC Date register is not configured\r\n */\r\nErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)\r\n{\r\n uint32_t tmpreg = 0;\r\n ErrorStatus status = ERROR;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_RTC_FORMAT(RTC_Format));\r\n\r\n if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10))\r\n {\r\n RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A;\r\n } \r\n if (RTC_Format == RTC_Format_BIN)\r\n {\r\n assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year));\r\n assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month));\r\n assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date));\r\n }\r\n else\r\n {\r\n assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year)));\r\n tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);\r\n assert_param(IS_RTC_MONTH(tmpreg));\r\n tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);\r\n assert_param(IS_RTC_DATE(tmpreg));\r\n }\r\n assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay));\r\n\r\n /* Check the input parameters format */\r\n if (RTC_Format != RTC_Format_BIN)\r\n {\r\n tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \\\r\n (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \\\r\n ((uint32_t)RTC_DateStruct->RTC_Date) | \\\r\n (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13)); \r\n } \r\n else\r\n {\r\n tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \\\r\n ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \\\r\n ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \\\r\n ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13));\r\n }\r\n\r\n /* Disable the write protection for RTC registers */\r\n RTC->WPR = 0xCA;\r\n RTC->WPR = 0x53;\r\n\r\n /* Set Initialization mode */\r\n if (RTC_EnterInitMode() == ERROR)\r\n {\r\n status = ERROR;\r\n } \r\n else\r\n {\r\n /* Set the RTC_DR register */\r\n RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK);\r\n\r\n /* Exit Initialization mode */\r\n RTC_ExitInitMode(); \r\n\r\n /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */\r\n if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)\r\n {\r\n if (RTC_WaitForSynchro() == ERROR)\r\n {\r\n status = ERROR;\r\n }\r\n else\r\n {\r\n status = SUCCESS;\r\n }\r\n }\r\n else\r\n {\r\n status = SUCCESS;\r\n }\r\n }\r\n /* Enable the write protection for RTC registers */\r\n RTC->WPR = 0xFF; \r\n \r\n return status;\r\n}\r\n\r\n/**\r\n * @brief Fills each RTC_DateStruct member with its default value\r\n * (Monday, January 01 xx00).\r\n * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be \r\n * initialized.\r\n * @retval None\r\n */\r\nvoid RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct)\r\n{\r\n /* Monday, January 01 xx00 */\r\n RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday;\r\n RTC_DateStruct->RTC_Date = 1;\r\n RTC_DateStruct->RTC_Month = RTC_Month_January;\r\n RTC_DateStruct->RTC_Year = 0;\r\n}\r\n\r\n/**\r\n * @brief Get the RTC current date. \r\n * @param RTC_Format: specifies the format of the returned parameters.\r\n * This parameter can be one of the following values:\r\n * @arg RTC_Format_BIN: Binary data format \r\n * @arg RTC_Format_BCD: BCD data format\r\n * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will \r\n * contain the returned current date configuration. \r\n * @retval None\r\n */\r\nvoid RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)\r\n{\r\n uint32_t tmpreg = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_RTC_FORMAT(RTC_Format));\r\n \r\n /* Get the RTC_TR register */\r\n tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); \r\n\r\n /* Fill the structure fields with the read parameters */\r\n RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);\r\n RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);\r\n RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU));\r\n RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13);\r\n\r\n /* Check the input parameters format */\r\n if (RTC_Format == RTC_Format_BIN)\r\n {\r\n /* Convert the structure parameters to Binary format */\r\n RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year);\r\n RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);\r\n RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);\r\n }\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup RTC_Group3 Alarms configuration functions\r\n * @brief Alarms (Alarm A and Alarm B) configuration functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Alarms (Alarm A and Alarm B) configuration functions\r\n =============================================================================== \r\n\r\n This section provide functions allowing to program and read the RTC Alarms.\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Set the specified RTC Alarm.\r\n * @note The Alarm register can only be written when the corresponding Alarm\r\n * is disabled (Use the RTC_AlarmCmd(DISABLE)). \r\n * @param RTC_Format: specifies the format of the returned parameters.\r\n * This parameter can be one of the following values:\r\n * @arg RTC_Format_BIN: Binary data format \r\n * @arg RTC_Format_BCD: BCD data format\r\n * @param RTC_Alarm: specifies the alarm to be configured.\r\n * This parameter can be one of the following values:\r\n * @arg RTC_Alarm_A: to select Alarm A\r\n * @arg RTC_Alarm_B: to select Alarm B \r\n * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that \r\n * contains the alarm configuration parameters. \r\n * @retval None\r\n */\r\nvoid RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)\r\n{\r\n uint32_t tmpreg = 0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_RTC_FORMAT(RTC_Format));\r\n assert_param(IS_RTC_ALARM(RTC_Alarm));\r\n assert_param(IS_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask));\r\n assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel));\r\n\r\n if (RTC_Format == RTC_Format_BIN)\r\n {\r\n if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)\r\n {\r\n assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));\r\n assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));\r\n } \r\n else\r\n {\r\n RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;\r\n assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));\r\n }\r\n assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes));\r\n assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds));\r\n \r\n if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)\r\n {\r\n assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay));\r\n }\r\n else\r\n {\r\n assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay));\r\n }\r\n }\r\n else\r\n {\r\n if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)\r\n {\r\n tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours);\r\n assert_param(IS_RTC_HOUR12(tmpreg));\r\n assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));\r\n } \r\n else\r\n {\r\n RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;\r\n assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)));\r\n }\r\n \r\n assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)));\r\n assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)));\r\n \r\n if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)\r\n {\r\n tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);\r\n assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); \r\n }\r\n else\r\n {\r\n tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);\r\n assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); \r\n } \r\n }\r\n\r\n /* Check the input parameters format */\r\n if (RTC_Format != RTC_Format_BIN)\r\n {\r\n tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \\\r\n ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \\\r\n ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \\\r\n ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \\\r\n ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \\\r\n ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \\\r\n ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); \r\n } \r\n else\r\n {\r\n tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \\\r\n ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \\\r\n ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \\\r\n ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \\\r\n ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \\\r\n ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \\\r\n ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); \r\n } \r\n\r\n /* Disable the write protection for RTC registers */\r\n RTC->WPR = 0xCA;\r\n RTC->WPR = 0x53;\r\n\r\n /* Configure the Alarm register */\r\n if (RTC_Alarm == RTC_Alarm_A)\r\n {\r\n RTC->ALRMAR = (uint32_t)tmpreg;\r\n }\r\n else\r\n {\r\n RTC->ALRMBR = (uint32_t)tmpreg;\r\n }\r\n\r\n /* Enable the write protection for RTC registers */\r\n RTC->WPR = 0xFF; \r\n}\r\n\r\n/**\r\n * @brief Fills each RTC_AlarmStruct member with its default value\r\n * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask =\r\n * all fields are masked).\r\n * @param RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which\r\n * will be initialized.\r\n * @retval None\r\n */\r\nvoid RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct)\r\n{\r\n /* Alarm Time Settings : Time = 00h:00mn:00sec */\r\n RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM;\r\n RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0;\r\n RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0;\r\n RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0;\r\n\r\n /* Alarm Date Settings : Date = 1st day of the month */\r\n RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date;\r\n RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1;\r\n\r\n /* Alarm Masks Settings : Mask = all fields are not masked */\r\n RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None;\r\n}\r\n\r\n/**\r\n * @brief Get the RTC Alarm value and masks.\r\n * @param RTC_Format: specifies the format of the output parameters.\r\n * This parameter can be one of the following values:\r\n * @arg RTC_Format_BIN: Binary data format \r\n * @arg RTC_Format_BCD: BCD data format\r\n * @param RTC_Alarm: specifies the alarm to be read.\r\n * This parameter can be one of the following values:\r\n * @arg RTC_Alarm_A: to select Alarm A\r\n * @arg RTC_Alarm_B: to select Alarm B \r\n * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will \r\n * contains the output alarm configuration values. \r\n * @retval None\r\n */\r\nvoid RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)\r\n{\r\n uint32_t tmpreg = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_RTC_FORMAT(RTC_Format));\r\n assert_param(IS_RTC_ALARM(RTC_Alarm)); \r\n\r\n /* Get the RTC_ALRMxR register */\r\n if (RTC_Alarm == RTC_Alarm_A)\r\n {\r\n tmpreg = (uint32_t)(RTC->ALRMAR);\r\n }\r\n else\r\n {\r\n tmpreg = (uint32_t)(RTC->ALRMBR);\r\n }\r\n\r\n /* Fill the structure with the read parameters */\r\n RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \\\r\n RTC_ALRMAR_HU)) >> 16);\r\n RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \\\r\n RTC_ALRMAR_MNU)) >> 8);\r\n RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \\\r\n RTC_ALRMAR_SU));\r\n RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);\r\n RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);\r\n RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);\r\n RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All);\r\n\r\n if (RTC_Format == RTC_Format_BIN)\r\n {\r\n RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \\\r\n RTC_AlarmTime.RTC_Hours);\r\n RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \\\r\n RTC_AlarmTime.RTC_Minutes);\r\n RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \\\r\n RTC_AlarmTime.RTC_Seconds);\r\n RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);\r\n } \r\n}\r\n\r\n/**\r\n * @brief Enables or disables the specified RTC Alarm.\r\n * @param RTC_Alarm: specifies the alarm to be configured.\r\n * This parameter can be any combination of the following values:\r\n * @arg RTC_Alarm_A: to select Alarm A\r\n * @arg RTC_Alarm_B: to select Alarm B \r\n * @param NewState: new state of the specified alarm.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval An ErrorStatus enumeration value:\r\n * - SUCCESS: RTC Alarm is enabled/disabled\r\n * - ERROR: RTC Alarm is not enabled/disabled \r\n */\r\nErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState)\r\n{\r\n __IO uint32_t alarmcounter = 0x00;\r\n uint32_t alarmstatus = 0x00;\r\n ErrorStatus status = ERROR;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_RTC_CMD_ALARM(RTC_Alarm));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n /* Disable the write protection for RTC registers */\r\n RTC->WPR = 0xCA;\r\n RTC->WPR = 0x53;\r\n\r\n /* Configure the Alarm state */\r\n if (NewState != DISABLE)\r\n {\r\n RTC->CR |= (uint32_t)RTC_Alarm;\r\n\r\n status = SUCCESS; \r\n }\r\n else\r\n { \r\n /* Disable the Alarm in RTC_CR register */\r\n RTC->CR &= (uint32_t)~RTC_Alarm;\r\n \r\n /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */\r\n do\r\n {\r\n alarmstatus = RTC->ISR & (RTC_Alarm >> 8);\r\n alarmcounter++; \r\n } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00));\r\n \r\n if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET)\r\n {\r\n status = ERROR;\r\n } \r\n else\r\n {\r\n status = SUCCESS;\r\n } \r\n } \r\n\r\n /* Enable the write protection for RTC registers */\r\n RTC->WPR = 0xFF; \r\n \r\n return status;\r\n}\r\n\r\n/**\r\n * @brief Configure the RTC AlarmA/B Subseconds value and mask.*\r\n * @note This function is performed only when the Alarm is disabled. \r\n * @param RTC_Alarm: specifies the alarm to be configured.\r\n * This parameter can be one of the following values:\r\n * @arg RTC_Alarm_A: to select Alarm A\r\n * @arg RTC_Alarm_B: to select Alarm B\r\n * @param RTC_AlarmSubSecondValue: specifies the Subseconds value.\r\n * This parameter can be a value from 0 to 0x00007FFF.\r\n * @param RTC_AlarmSubSecondMask: specifies the Subseconds Mask.\r\n * This parameter can be any combination of the following values:\r\n * @arg RTC_AlarmSubSecondMask_All : All Alarm SS fields are masked.\r\n * There is no comparison on sub seconds for Alarm.\r\n * @arg RTC_AlarmSubSecondMask_SS14_1 : SS[14:1] are don't care in Alarm comparison.\r\n * Only SS[0] is compared\r\n * @arg RTC_AlarmSubSecondMask_SS14_2 : SS[14:2] are don't care in Alarm comparison.\r\n * Only SS[1:0] are compared\r\n * @arg RTC_AlarmSubSecondMask_SS14_3 : SS[14:3] are don't care in Alarm comparison.\r\n * Only SS[2:0] are compared\r\n * @arg RTC_AlarmSubSecondMask_SS14_4 : SS[14:4] are don't care in Alarm comparison.\r\n * Only SS[3:0] are compared\r\n * @arg RTC_AlarmSubSecondMask_SS14_5 : SS[14:5] are don't care in Alarm comparison.\r\n * Only SS[4:0] are compared\r\n * @arg RTC_AlarmSubSecondMask_SS14_6 : SS[14:6] are don't care in Alarm comparison.\r\n * Only SS[5:0] are compared\r\n * @arg RTC_AlarmSubSecondMask_SS14_7 : SS[14:7] are don't care in Alarm comparison.\r\n * Only SS[6:0] are compared\r\n * @arg RTC_AlarmSubSecondMask_SS14_8 : SS[14:8] are don't care in Alarm comparison.\r\n * Only SS[7:0] are compared\r\n * @arg RTC_AlarmSubSecondMask_SS14_9 : SS[14:9] are don't care in Alarm comparison.\r\n * Only SS[8:0] are compared\r\n * @arg RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison.\r\n * Only SS[9:0] are compared\r\n * @arg RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison.\r\n * Only SS[10:0] are compared\r\n * @arg RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison.\r\n * Only SS[11:0] are compared\r\n * @arg RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison.\r\n * Only SS[12:0] are compared\r\n * @arg RTC_AlarmSubSecondMask_SS14 : SS[14] is don't care in Alarm comparison.\r\n * Only SS[13:0] are compared\r\n * @arg RTC_AlarmSubSecondMask_None : SS[14:0] are compared and must match\r\n * to activate alarm\r\n * @retval None\r\n */\r\nvoid RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask)\r\n{\r\n uint32_t tmpreg = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_RTC_ALARM(RTC_Alarm));\r\n assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue));\r\n assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(RTC_AlarmSubSecondMask));\r\n \r\n /* Disable the write protection for RTC registers */\r\n RTC->WPR = 0xCA;\r\n RTC->WPR = 0x53;\r\n \r\n /* Configure the Alarm A or Alarm B SubSecond registers */\r\n tmpreg = (uint32_t) (uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask);\r\n \r\n if (RTC_Alarm == RTC_Alarm_A)\r\n {\r\n /* Configure the AlarmA SubSecond register */\r\n RTC->ALRMASSR = tmpreg;\r\n }\r\n else\r\n {\r\n /* Configure the Alarm B SubSecond register */\r\n RTC->ALRMBSSR = tmpreg;\r\n }\r\n\r\n /* Enable the write protection for RTC registers */\r\n RTC->WPR = 0xFF;\r\n\r\n}\r\n\r\n/**\r\n * @brief Gets the RTC Alarm Subseconds value.\r\n * @param RTC_Alarm: specifies the alarm to be read.\r\n * This parameter can be one of the following values:\r\n * @arg RTC_Alarm_A: to select Alarm A\r\n * @arg RTC_Alarm_B: to select Alarm B\r\n * @param None\r\n * @retval RTC Alarm Subseconds value.\r\n */\r\nuint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm)\r\n{\r\n uint32_t tmpreg = 0;\r\n \r\n /* Get the RTC_ALRMxR register */\r\n if (RTC_Alarm == RTC_Alarm_A)\r\n {\r\n tmpreg = (uint32_t)((RTC->ALRMASSR) & RTC_ALRMASSR_SS);\r\n }\r\n else\r\n {\r\n tmpreg = (uint32_t)((RTC->ALRMBSSR) & RTC_ALRMBSSR_SS);\r\n } \r\n \r\n return (tmpreg);\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup RTC_Group4 WakeUp Timer configuration functions\r\n * @brief WakeUp Timer configuration functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n WakeUp Timer configuration functions\r\n =============================================================================== \r\n\r\n This section provide functions allowing to program and read the RTC WakeUp.\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Configures the RTC Wakeup clock source.\r\n * @note The WakeUp Clock source can only be changed when the RTC WakeUp\r\n * is disabled (Use the RTC_WakeUpCmd(DISABLE)). \r\n * @param RTC_WakeUpClock: Wakeup Clock source.\r\n * This parameter can be one of the following values:\r\n * @arg RTC_WakeUpClock_RTCCLK_Div16: RTC Wakeup Counter Clock = RTCCLK/16\r\n * @arg RTC_WakeUpClock_RTCCLK_Div8: RTC Wakeup Counter Clock = RTCCLK/8\r\n * @arg RTC_WakeUpClock_RTCCLK_Div4: RTC Wakeup Counter Clock = RTCCLK/4\r\n * @arg RTC_WakeUpClock_RTCCLK_Div2: RTC Wakeup Counter Clock = RTCCLK/2\r\n * @arg RTC_WakeUpClock_CK_SPRE_16bits: RTC Wakeup Counter Clock = CK_SPRE\r\n * @arg RTC_WakeUpClock_CK_SPRE_17bits: RTC Wakeup Counter Clock = CK_SPRE\r\n * @retval None\r\n */\r\nvoid RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock));\r\n\r\n /* Disable the write protection for RTC registers */\r\n RTC->WPR = 0xCA;\r\n RTC->WPR = 0x53;\r\n\r\n /* Clear the Wakeup Timer clock source bits in CR register */\r\n RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL;\r\n\r\n /* Configure the clock source */\r\n RTC->CR |= (uint32_t)RTC_WakeUpClock;\r\n \r\n /* Enable the write protection for RTC registers */\r\n RTC->WPR = 0xFF; \r\n}\r\n\r\n/**\r\n * @brief Configures the RTC Wakeup counter.\r\n * @note The RTC WakeUp counter can only be written when the RTC WakeUp\r\n * is disabled (Use the RTC_WakeUpCmd(DISABLE)). \r\n * @param RTC_WakeUpCounter: specifies the WakeUp counter.\r\n * This parameter can be a value from 0x0000 to 0xFFFF. \r\n * @retval None\r\n */\r\nvoid RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter));\r\n \r\n /* Disable the write protection for RTC registers */\r\n RTC->WPR = 0xCA;\r\n RTC->WPR = 0x53;\r\n \r\n /* Configure the Wakeup Timer counter */\r\n RTC->WUTR = (uint32_t)RTC_WakeUpCounter;\r\n \r\n /* Enable the write protection for RTC registers */\r\n RTC->WPR = 0xFF; \r\n}\r\n\r\n/**\r\n * @brief Returns the RTC WakeUp timer counter value.\r\n * @param None\r\n * @retval The RTC WakeUp Counter value.\r\n */\r\nuint32_t RTC_GetWakeUpCounter(void)\r\n{\r\n /* Get the counter value */\r\n return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT));\r\n}\r\n\r\n/**\r\n * @brief Enables or Disables the RTC WakeUp timer.\r\n * @param NewState: new state of the WakeUp timer.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nErrorStatus RTC_WakeUpCmd(FunctionalState NewState)\r\n{\r\n __IO uint32_t wutcounter = 0x00;\r\n uint32_t wutwfstatus = 0x00;\r\n ErrorStatus status = ERROR;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n /* Disable the write protection for RTC registers */\r\n RTC->WPR = 0xCA;\r\n RTC->WPR = 0x53;\r\n\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the Wakeup Timer */\r\n RTC->CR |= (uint32_t)RTC_CR_WUTE;\r\n status = SUCCESS; \r\n }\r\n else\r\n {\r\n /* Disable the Wakeup Timer */\r\n RTC->CR &= (uint32_t)~RTC_CR_WUTE;\r\n /* Wait till RTC WUTWF flag is set and if Time out is reached exit */\r\n do\r\n {\r\n wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;\r\n wutcounter++; \r\n } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));\r\n \r\n if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)\r\n {\r\n status = ERROR;\r\n }\r\n else\r\n {\r\n status = SUCCESS;\r\n } \r\n }\r\n\r\n /* Enable the write protection for RTC registers */\r\n RTC->WPR = 0xFF; \r\n \r\n return status;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup RTC_Group5 Daylight Saving configuration functions\r\n * @brief Daylight Saving configuration functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Daylight Saving configuration functions\r\n =============================================================================== \r\n\r\n This section provide functions allowing to configure the RTC DayLight Saving.\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Adds or substract one hour from the current time.\r\n * @param RTC_DayLightSaveOperation: the value of hour adjustment. \r\n * This parameter can be one of the following values:\r\n * @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time)\r\n * @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time)\r\n * @param RTC_StoreOperation: Specifies the value to be written in the BCK bit \r\n * in CR register to store the operation.\r\n * This parameter can be one of the following values:\r\n * @arg RTC_StoreOperation_Reset: BCK Bit Reset\r\n * @arg RTC_StoreOperation_Set: BCK Bit Set\r\n * @retval None\r\n */\r\nvoid RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving));\r\n assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation));\r\n\r\n /* Disable the write protection for RTC registers */\r\n RTC->WPR = 0xCA;\r\n RTC->WPR = 0x53;\r\n\r\n /* Clear the bits to be configured */\r\n RTC->CR &= (uint32_t)~(RTC_CR_BCK);\r\n\r\n /* Configure the RTC_CR register */\r\n RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation);\r\n\r\n /* Enable the write protection for RTC registers */\r\n RTC->WPR = 0xFF; \r\n}\r\n\r\n/**\r\n * @brief Returns the RTC Day Light Saving stored operation.\r\n * @param None\r\n * @retval RTC Day Light Saving stored operation.\r\n * - RTC_StoreOperation_Reset\r\n * - RTC_StoreOperation_Set \r\n */\r\nuint32_t RTC_GetStoreOperation(void)\r\n{\r\n return (RTC->CR & RTC_CR_BCK);\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup RTC_Group6 Output pin Configuration function\r\n * @brief Output pin Configuration function \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Output pin Configuration function\r\n =============================================================================== \r\n\r\n This section provide functions allowing to configure the RTC Output source.\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Configures the RTC output source (AFO_ALARM).\r\n * @param RTC_Output: Specifies which signal will be routed to the RTC output. \r\n * This parameter can be one of the following values:\r\n * @arg RTC_Output_Disable: No output selected\r\n * @arg RTC_Output_AlarmA: signal of AlarmA mapped to output\r\n * @arg RTC_Output_AlarmB: signal of AlarmB mapped to output\r\n * @arg RTC_Output_WakeUp: signal of WakeUp mapped to output\r\n * @param RTC_OutputPolarity: Specifies the polarity of the output signal. \r\n * This parameter can be one of the following:\r\n * @arg RTC_OutputPolarity_High: The output pin is high when the \r\n * ALRAF/ALRBF/WUTF is high (depending on OSEL)\r\n * @arg RTC_OutputPolarity_Low: The output pin is low when the \r\n * ALRAF/ALRBF/WUTF is high (depending on OSEL)\r\n * @retval None\r\n */\r\nvoid RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RTC_OUTPUT(RTC_Output));\r\n assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity));\r\n\r\n /* Disable the write protection for RTC registers */\r\n RTC->WPR = 0xCA;\r\n RTC->WPR = 0x53;\r\n\r\n /* Clear the bits to be configured */\r\n RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL);\r\n\r\n /* Configure the output selection and polarity */\r\n RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity);\r\n\r\n /* Enable the write protection for RTC registers */\r\n RTC->WPR = 0xFF; \r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup RTC_Group7 Digital Calibration configuration functions\r\n * @brief Coarse Calibration configuration functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Digital Calibration configuration functions\r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Configures the Coarse calibration parameters.\r\n * @param RTC_CalibSign: specifies the sign of the coarse calibration value.\r\n * This parameter can be one of the following values:\r\n * @arg RTC_CalibSign_Positive: The value sign is positive \r\n * @arg RTC_CalibSign_Negative: The value sign is negative\r\n * @param Value: value of coarse calibration expressed in ppm (coded on 5 bits).\r\n * \r\n * @note This Calibration value should be between 0 and 63 when using negative\r\n * sign with a 2-ppm step.\r\n * \r\n * @note This Calibration value should be between 0 and 126 when using positive\r\n * sign with a 4-ppm step.\r\n * \r\n * @retval An ErrorStatus enumeration value:\r\n * - SUCCESS: RTC Coarse calibration are initialized\r\n * - ERROR: RTC Coarse calibration are not initialized \r\n */\r\nErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value)\r\n{\r\n ErrorStatus status = ERROR;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_RTC_CALIB_SIGN(RTC_CalibSign));\r\n assert_param(IS_RTC_CALIB_VALUE(Value)); \r\n\r\n /* Disable the write protection for RTC registers */\r\n RTC->WPR = 0xCA;\r\n RTC->WPR = 0x53;\r\n\r\n /* Set Initialization mode */\r\n if (RTC_EnterInitMode() == ERROR)\r\n {\r\n status = ERROR;\r\n } \r\n else\r\n {\r\n /* Set the coarse calibration value */\r\n RTC->CALIBR = (uint32_t)(RTC_CalibSign | Value);\r\n /* Exit Initialization mode */\r\n RTC_ExitInitMode();\r\n \r\n status = SUCCESS;\r\n } \r\n\r\n /* Enable the write protection for RTC registers */\r\n RTC->WPR = 0xFF; \r\n \r\n return status;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the Coarse calibration process.\r\n * @param NewState: new state of the Coarse calibration.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval An ErrorStatus enumeration value:\r\n * - SUCCESS: RTC Coarse calibration are enabled/disabled\r\n * - ERROR: RTC Coarse calibration are not enabled/disabled \r\n */\r\nErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState)\r\n{\r\n ErrorStatus status = ERROR;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n /* Disable the write protection for RTC registers */\r\n RTC->WPR = 0xCA;\r\n RTC->WPR = 0x53;\r\n \r\n /* Set Initialization mode */\r\n if (RTC_EnterInitMode() == ERROR)\r\n {\r\n status = ERROR;\r\n }\r\n else\r\n {\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the Coarse Calibration */\r\n RTC->CR |= (uint32_t)RTC_CR_DCE;\r\n }\r\n else\r\n { \r\n /* Disable the Coarse Calibration */\r\n RTC->CR &= (uint32_t)~RTC_CR_DCE;\r\n }\r\n /* Exit Initialization mode */\r\n RTC_ExitInitMode();\r\n \r\n status = SUCCESS;\r\n } \r\n \r\n /* Enable the write protection for RTC registers */\r\n RTC->WPR = 0xFF; \r\n \r\n return status;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the RTC clock to be output through the relative pin.\r\n * @param NewState: new state of the digital calibration Output.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid RTC_CalibOutputCmd(FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n /* Disable the write protection for RTC registers */\r\n RTC->WPR = 0xCA;\r\n RTC->WPR = 0x53;\r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the RTC clock output */\r\n RTC->CR |= (uint32_t)RTC_CR_COE;\r\n }\r\n else\r\n { \r\n /* Disable the RTC clock output */\r\n RTC->CR &= (uint32_t)~RTC_CR_COE;\r\n }\r\n \r\n /* Enable the write protection for RTC registers */\r\n RTC->WPR = 0xFF; \r\n}\r\n\r\n/**\r\n * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).\r\n * @param RTC_CalibOutput : Select the Calibration output Selection .\r\n * This parameter can be one of the following values:\r\n * @arg RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz. \r\n * @arg RTC_CalibOutput_1Hz : A signal has a regular waveform at 1Hz.\r\n * @retval None\r\n*/\r\nvoid RTC_CalibOutputConfig(uint32_t RTC_CalibOutput)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput));\r\n\r\n /* Disable the write protection for RTC registers */\r\n RTC->WPR = 0xCA;\r\n RTC->WPR = 0x53;\r\n \r\n /*clear flags before config*/\r\n RTC->CR &= (uint32_t)~(RTC_CR_COSEL);\r\n\r\n /* Configure the RTC_CR register */\r\n RTC->CR |= (uint32_t)RTC_CalibOutput;\r\n\r\n /* Enable the write protection for RTC registers */\r\n RTC->WPR = 0xFF;\r\n}\r\n\r\n/**\r\n * @brief Configures the Smooth Calibration Settings.\r\n * @param RTC_SmoothCalibPeriod : Select the Smooth Calibration Period.\r\n * This parameter can be can be one of the following values:\r\n * @arg RTC_SmoothCalibPeriod_32sec : The smooth calibration periode is 32s.\r\n * @arg RTC_SmoothCalibPeriod_16sec : The smooth calibration periode is 16s.\r\n * @arg RTC_SmoothCalibPeriod_8sec : The smooth calibartion periode is 8s.\r\n * @param RTC_SmoothCalibPlusPulses : Select to Set or reset the CALP bit.\r\n * This parameter can be one of the following values:\r\n * @arg RTC_SmoothCalibPlusPulses_Set : Add one RTCCLK puls every 2**11 pulses.\r\n * @arg RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added.\r\n * @param RTC_SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.\r\n * This parameter can be one any value from 0 to 0x000001FF.\r\n * @retval An ErrorStatus enumeration value:\r\n * - SUCCESS: RTC Calib registers are configured\r\n * - ERROR: RTC Calib registers are not configured\r\n*/\r\nErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,\r\n uint32_t RTC_SmoothCalibPlusPulses,\r\n uint32_t RTC_SmouthCalibMinusPulsesValue)\r\n{\r\n ErrorStatus status = ERROR;\r\n uint32_t recalpfcount = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(RTC_SmoothCalibPeriod));\r\n assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses));\r\n assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue));\r\n\r\n /* Disable the write protection for RTC registers */\r\n RTC->WPR = 0xCA;\r\n RTC->WPR = 0x53;\r\n \r\n /* check if a calibration is pending*/\r\n if ((RTC->ISR & RTC_ISR_RECALPF) != RESET)\r\n {\r\n /* wait until the Calibration is completed*/\r\n while (((RTC->ISR & RTC_ISR_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT))\r\n {\r\n recalpfcount++;\r\n }\r\n }\r\n\r\n /* check if the calibration pending is completed or if there is no calibration operation at all*/\r\n if ((RTC->ISR & RTC_ISR_RECALPF) == RESET)\r\n {\r\n /* Configure the Smooth calibration settings */\r\n RTC->CALR = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses | (uint32_t)RTC_SmouthCalibMinusPulsesValue);\r\n\r\n status = SUCCESS;\r\n }\r\n else\r\n {\r\n status = ERROR;\r\n }\r\n\r\n /* Enable the write protection for RTC registers */\r\n RTC->WPR = 0xFF;\r\n \r\n return (ErrorStatus)(status);\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n\r\n/** @defgroup RTC_Group8 TimeStamp configuration functions\r\n * @brief TimeStamp configuration functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n TimeStamp configuration functions\r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Enables or Disables the RTC TimeStamp functionality with the \r\n * specified time stamp pin stimulating edge.\r\n * @param RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is \r\n * activated.\r\n * This parameter can be one of the following:\r\n * @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising \r\n * edge of the related pin.\r\n * @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the \r\n * falling edge of the related pin.\r\n * @param NewState: new state of the TimeStamp.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState)\r\n{\r\n uint32_t tmpreg = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n /* Get the RTC_CR register and clear the bits to be configured */\r\n tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));\r\n\r\n /* Get the new configuration */\r\n if (NewState != DISABLE)\r\n {\r\n tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE);\r\n }\r\n else\r\n {\r\n tmpreg |= (uint32_t)(RTC_TimeStampEdge);\r\n }\r\n\r\n /* Disable the write protection for RTC registers */\r\n RTC->WPR = 0xCA;\r\n RTC->WPR = 0x53;\r\n\r\n /* Configure the Time Stamp TSEDGE and Enable bits */\r\n RTC->CR = (uint32_t)tmpreg;\r\n\r\n /* Enable the write protection for RTC registers */\r\n RTC->WPR = 0xFF; \r\n}\r\n\r\n/**\r\n * @brief Get the RTC TimeStamp value and masks.\r\n * @param RTC_Format: specifies the format of the output parameters.\r\n * This parameter can be one of the following values:\r\n * @arg RTC_Format_BIN: Binary data format \r\n * @arg RTC_Format_BCD: BCD data format\r\n * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will \r\n * contains the TimeStamp time values. \r\n * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will \r\n * contains the TimeStamp date values. \r\n * @retval None\r\n */\r\nvoid RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, \r\n RTC_DateTypeDef* RTC_StampDateStruct)\r\n{\r\n uint32_t tmptime = 0, tmpdate = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_RTC_FORMAT(RTC_Format));\r\n\r\n /* Get the TimeStamp time and date registers values */\r\n tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK);\r\n tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK);\r\n\r\n /* Fill the Time structure fields with the read parameters */\r\n RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);\r\n RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);\r\n RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));\r\n RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); \r\n\r\n /* Fill the Date structure fields with the read parameters */\r\n RTC_StampDateStruct->RTC_Year = 0;\r\n RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);\r\n RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));\r\n RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);\r\n\r\n /* Check the input parameters format */\r\n if (RTC_Format == RTC_Format_BIN)\r\n {\r\n /* Convert the Time structure parameters to Binary format */\r\n RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours);\r\n RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes);\r\n RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds);\r\n\r\n /* Convert the Date structure parameters to Binary format */\r\n RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month);\r\n RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date);\r\n RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Get the RTC timestamp Subseconds value.\r\n * @param None\r\n * @retval RTC current timestamp Subseconds value.\r\n */\r\nuint32_t RTC_GetTimeStampSubSecond(void)\r\n{\r\n /* Get timestamp subseconds values from the correspondent registers */\r\n return (uint32_t)(RTC->TSSSR);\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup RTC_Group9 Tampers configuration functions\r\n * @brief Tampers configuration functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Tampers configuration functions\r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Configures the select Tamper pin edge.\r\n * @param RTC_Tamper: Selected tamper pin.\r\n * This parameter can be RTC_Tamper_1.\r\n * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that \r\n * stimulates tamper event. \r\n * This parameter can be one of the following values:\r\n * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event.\r\n * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event.\r\n * @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event.\r\n * @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event.\r\n * @retval None\r\n */\r\nvoid RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RTC_TAMPER(RTC_Tamper)); \r\n assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger));\r\n \r\n if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge)\r\n { \r\n /* Configure the RTC_TAFCR register */\r\n RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1));\t\r\n }\r\n else\r\n { \r\n /* Configure the RTC_TAFCR register */\r\n RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1); \r\n } \r\n}\r\n\r\n/**\r\n * @brief Enables or Disables the Tamper detection.\r\n * @param RTC_Tamper: Selected tamper pin.\r\n * This parameter can be RTC_Tamper_1.\r\n * @param NewState: new state of the tamper pin.\r\n * This parameter can be: ENABLE or DISABLE. \r\n * @retval None\r\n */\r\nvoid RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RTC_TAMPER(RTC_Tamper)); \r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected Tamper pin */\r\n RTC->TAFCR |= (uint32_t)RTC_Tamper;\r\n }\r\n else\r\n {\r\n /* Disable the selected Tamper pin */\r\n RTC->TAFCR &= (uint32_t)~RTC_Tamper; \r\n } \r\n}\r\n\r\n/**\r\n * @brief Configures the Tampers Filter.\r\n * @param RTC_TamperFilter: Specifies the tampers filter.\r\n * This parameter can be one of the following values:\r\n * @arg RTC_TamperFilter_Disable: Tamper filter is disabled.\r\n * @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive \r\n * samples at the active level \r\n * @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive \r\n * samples at the active level\r\n * @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive \r\n * samples at the active level \r\n * @retval None\r\n */\r\nvoid RTC_TamperFilterConfig(uint32_t RTC_TamperFilter)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter));\r\n \r\n /* Clear TAMPFLT[1:0] bits in the RTC_TAFCR register */\r\n RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFLT);\r\n\r\n /* Configure the RTC_TAFCR register */\r\n RTC->TAFCR |= (uint32_t)RTC_TamperFilter;\r\n}\r\n\r\n/**\r\n * @brief Configures the Tampers Sampling Frequency.\r\n * @param RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency.\r\n * This parameter can be one of the following values:\r\n * @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled\r\n * with a frequency = RTCCLK / 32768\r\n * @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled\r\n * with a frequency = RTCCLK / 16384\r\n * @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled\r\n * with a frequency = RTCCLK / 8192\r\n * @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled\r\n * with a frequency = RTCCLK / 4096\r\n * @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled\r\n * with a frequency = RTCCLK / 2048\r\n * @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled\r\n * with a frequency = RTCCLK / 1024\r\n * @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled\r\n * with a frequency = RTCCLK / 512 \r\n * @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled\r\n * with a frequency = RTCCLK / 256 \r\n * @retval None\r\n */\r\nvoid RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq));\r\n \r\n /* Clear TAMPFREQ[2:0] bits in the RTC_TAFCR register */\r\n RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFREQ);\r\n\r\n /* Configure the RTC_TAFCR register */\r\n RTC->TAFCR |= (uint32_t)RTC_TamperSamplingFreq;\r\n}\r\n\r\n/**\r\n * @brief Configures the Tampers Pins input Precharge Duration.\r\n * @param RTC_TamperPrechargeDuration: Specifies the Tampers Pins input\r\n * Precharge Duration.\r\n * This parameter can be one of the following values:\r\n * @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle\r\n * @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle\r\n * @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle \r\n * @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle\r\n * @retval None\r\n */\r\nvoid RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration));\r\n \r\n /* Clear TAMPPRCH[1:0] bits in the RTC_TAFCR register */\r\n RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPPRCH);\r\n\r\n /* Configure the RTC_TAFCR register */\r\n RTC->TAFCR |= (uint32_t)RTC_TamperPrechargeDuration;\r\n}\r\n\r\n/**\r\n * @brief Enables or Disables the TimeStamp on Tamper Detection Event.\r\n * @note The timestamp is valid even the TSE bit in tamper control register \r\n * is reset. \r\n * @param NewState: new state of the timestamp on tamper event.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Save timestamp on tamper detection event */\r\n RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPTS;\r\n }\r\n else\r\n {\r\n /* Tamper detection does not cause a timestamp to be saved */\r\n RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPTS; \r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables or Disables the Precharge of Tamper pin.\r\n * @param NewState: new state of tamper pull up.\r\n * This parameter can be: ENABLE or DISABLE. \r\n * @retval None\r\n */\r\nvoid RTC_TamperPullUpCmd(FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Enable precharge of the selected Tamper pin */\r\n RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPPUDIS; \r\n }\r\n else\r\n {\r\n /* Disable precharge of the selected Tamper pin */\r\n RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPPUDIS; \r\n } \r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup RTC_Group10 Backup Data Registers configuration functions\r\n * @brief Backup Data Registers configuration functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Backup Data Registers configuration functions \r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Writes a data in a specified RTC Backup data register.\r\n * @param RTC_BKP_DR: RTC Backup data Register number.\r\n * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to \r\n * specify the register.\r\n * @param Data: Data to be written in the specified RTC Backup data register. \r\n * @retval None\r\n */\r\nvoid RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data)\r\n{\r\n __IO uint32_t tmp = 0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_RTC_BKP(RTC_BKP_DR));\r\n\r\n tmp = RTC_BASE + 0x50;\r\n tmp += (RTC_BKP_DR * 4);\r\n\r\n /* Write the specified register */\r\n *(__IO uint32_t *)tmp = (uint32_t)Data;\r\n}\r\n\r\n/**\r\n * @brief Reads data from the specified RTC Backup data Register.\r\n * @param RTC_BKP_DR: RTC Backup data Register number.\r\n * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to \r\n * specify the register. \r\n * @retval None\r\n */\r\nuint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR)\r\n{\r\n __IO uint32_t tmp = 0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_RTC_BKP(RTC_BKP_DR));\r\n\r\n tmp = RTC_BASE + 0x50;\r\n tmp += (RTC_BKP_DR * 4);\r\n \r\n /* Read the specified register */\r\n return (*(__IO uint32_t *)tmp);\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup RTC_Group11 RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions\r\n * @brief RTC Tamper and TimeStamp Pins Selection and Output Type Config \r\n * configuration functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration \r\n functions \r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Selects the RTC Tamper Pin.\r\n * @param RTC_TamperPin: specifies the RTC Tamper Pin.\r\n * This parameter can be one of the following values:\r\n * @arg RTC_TamperPin_PC13: PC13 is selected as RTC Tamper Pin.\r\n * @arg RTC_TamperPin_PI8: PI8 is selected as RTC Tamper Pin. \r\n * @retval None\r\n */\r\nvoid RTC_TamperPinSelection(uint32_t RTC_TamperPin)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RTC_TAMPER_PIN(RTC_TamperPin));\r\n \r\n RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPINSEL);\r\n RTC->TAFCR |= (uint32_t)(RTC_TamperPin); \r\n}\r\n\r\n/**\r\n * @brief Selects the RTC TimeStamp Pin.\r\n * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin.\r\n * This parameter can be one of the following values:\r\n * @arg RTC_TimeStampPin_PC13: PC13 is selected as RTC TimeStamp Pin.\r\n * @arg RTC_TimeStampPin_PI8: PI8 is selected as RTC TimeStamp Pin. \r\n * @retval None\r\n */\r\nvoid RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));\r\n \r\n RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TSINSEL);\r\n RTC->TAFCR |= (uint32_t)(RTC_TimeStampPin); \r\n}\r\n\r\n/**\r\n * @brief Configures the RTC Output Pin mode. \r\n * @param RTC_OutputType: specifies the RTC Output (PC13) pin mode.\r\n * This parameter can be one of the following values:\r\n * @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in \r\n * Open Drain mode.\r\n * @arg RTC_OutputType_PushPull: RTC Output (PC13) is configured in \r\n * Push Pull mode. \r\n * @retval None\r\n */\r\nvoid RTC_OutputTypeConfig(uint32_t RTC_OutputType)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType));\r\n \r\n RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE);\r\n RTC->TAFCR |= (uint32_t)(RTC_OutputType); \r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup RTC_Group12 Shift control synchronisation functions\r\n * @brief Shift control synchronisation functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Shift control synchronisation functions\r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Configures the Synchronization Shift Control Settings.\r\n * @note When REFCKON is set, firmware must not write to Shift control register \r\n * @param RTC_ShiftAdd1S : Select to add or not 1 second to the time Calendar.\r\n * This parameter can be one of the following values :\r\n * @arg RTC_ShiftAdd1S_Set : Add one second to the clock calendar. \r\n * @arg RTC_ShiftAdd1S_Reset: No effect.\r\n * @param RTC_ShiftSubFS: Select the number of Second Fractions to Substitute.\r\n * This parameter can be one any value from 0 to 0x7FFF.\r\n * @retval An ErrorStatus enumeration value:\r\n * - SUCCESS: RTC Shift registers are configured\r\n * - ERROR: RTC Shift registers are not configured\r\n*/\r\nErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS)\r\n{\r\n ErrorStatus status = ERROR;\r\n uint32_t shpfcount = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S));\r\n assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS));\r\n\r\n /* Disable the write protection for RTC registers */\r\n RTC->WPR = 0xCA;\r\n RTC->WPR = 0x53;\r\n \r\n /* Check if a Shift is pending*/\r\n if ((RTC->ISR & RTC_ISR_SHPF) != RESET)\r\n {\r\n /* Wait until the shift is completed*/\r\n while (((RTC->ISR & RTC_ISR_SHPF) != RESET) && (shpfcount != SHPF_TIMEOUT))\r\n {\r\n shpfcount++;\r\n }\r\n }\r\n\r\n /* Check if the Shift pending is completed or if there is no Shift operation at all*/\r\n if ((RTC->ISR & RTC_ISR_SHPF) == RESET)\r\n {\r\n /* check if the reference clock detection is disabled */\r\n if((RTC->CR & RTC_CR_REFCKON) == RESET)\r\n {\r\n /* Configure the Shift settings */\r\n RTC->SHIFTR = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S);\r\n \r\n if(RTC_WaitForSynchro() == ERROR)\r\n {\r\n status = ERROR;\r\n }\r\n else\r\n {\r\n status = SUCCESS;\r\n }\r\n }\r\n else\r\n {\r\n status = ERROR;\r\n }\r\n }\r\n else\r\n {\r\n status = ERROR;\r\n }\r\n\r\n /* Enable the write protection for RTC registers */\r\n RTC->WPR = 0xFF;\r\n \r\n return (ErrorStatus)(status);\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup RTC_Group13 Interrupts and flags management functions\r\n * @brief Interrupts and flags management functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Interrupts and flags management functions\r\n =============================================================================== \r\n All RTC interrupts are connected to the EXTI controller.\r\n \r\n - To enable the RTC Alarm interrupt, the following sequence is required:\r\n - Configure and enable the EXTI Line 17 in interrupt mode and select the rising \r\n edge sensitivity using the EXTI_Init() function.\r\n - Configure and enable the RTC_Alarm IRQ channel in the NVIC using the NVIC_Init()\r\n function.\r\n - Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) using\r\n the RTC_SetAlarm() and RTC_AlarmCmd() functions.\r\n\r\n - To enable the RTC Wakeup interrupt, the following sequence is required:\r\n - Configure and enable the EXTI Line 22 in interrupt mode and select the rising \r\n edge sensitivity using the EXTI_Init() function.\r\n - Configure and enable the RTC_WKUP IRQ channel in the NVIC using the NVIC_Init()\r\n function.\r\n - Configure the RTC to generate the RTC wakeup timer event using the \r\n RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.\r\n\r\n - To enable the RTC Tamper interrupt, the following sequence is required:\r\n - Configure and enable the EXTI Line 21 in interrupt mode and select the rising \r\n edge sensitivity using the EXTI_Init() function.\r\n - Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init()\r\n function.\r\n - Configure the RTC to detect the RTC tamper event using the \r\n RTC_TamperTriggerConfig() and RTC_TamperCmd() functions.\r\n\r\n - To enable the RTC TimeStamp interrupt, the following sequence is required:\r\n - Configure and enable the EXTI Line 21 in interrupt mode and select the rising \r\n edge sensitivity using the EXTI_Init() function.\r\n - Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init()\r\n function.\r\n - Configure the RTC to detect the RTC time-stamp event using the \r\n RTC_TimeStampCmd() functions.\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Enables or disables the specified RTC interrupts.\r\n * @param RTC_IT: specifies the RTC interrupt sources to be enabled or disabled. \r\n * This parameter can be any combination of the following values:\r\n * @arg RTC_IT_TS: Time Stamp interrupt mask\r\n * @arg RTC_IT_WUT: WakeUp Timer interrupt mask\r\n * @arg RTC_IT_ALRB: Alarm B interrupt mask\r\n * @arg RTC_IT_ALRA: Alarm A interrupt mask\r\n * @arg RTC_IT_TAMP: Tamper event interrupt mask\r\n * @param NewState: new state of the specified RTC interrupts.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RTC_CONFIG_IT(RTC_IT));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n /* Disable the write protection for RTC registers */\r\n RTC->WPR = 0xCA;\r\n RTC->WPR = 0x53;\r\n\r\n if (NewState != DISABLE)\r\n {\r\n /* Configure the Interrupts in the RTC_CR register */\r\n RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE);\r\n /* Configure the Tamper Interrupt in the RTC_TAFCR */\r\n RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE);\r\n }\r\n else\r\n {\r\n /* Configure the Interrupts in the RTC_CR register */\r\n RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE);\r\n /* Configure the Tamper Interrupt in the RTC_TAFCR */\r\n RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE);\r\n }\r\n /* Enable the write protection for RTC registers */\r\n RTC->WPR = 0xFF; \r\n}\r\n\r\n/**\r\n * @brief Checks whether the specified RTC flag is set or not.\r\n * @param RTC_FLAG: specifies the flag to check.\r\n * This parameter can be one of the following values:\r\n * @arg RTC_FLAG_RECALPF: RECALPF event flag.\r\n * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag\r\n * @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag\r\n * @arg RTC_FLAG_TSF: Time Stamp event flag\r\n * @arg RTC_FLAG_WUTF: WakeUp Timer flag\r\n * @arg RTC_FLAG_ALRBF: Alarm B flag\r\n * @arg RTC_FLAG_ALRAF: Alarm A flag\r\n * @arg RTC_FLAG_INITF: Initialization mode flag\r\n * @arg RTC_FLAG_RSF: Registers Synchronized flag\r\n * @arg RTC_FLAG_INITS: Registers Configured flag\r\n * @arg RTC_FLAG_SHPF: Shift operation pending flag.\r\n * @arg RTC_FLAG_WUTWF: WakeUp Timer Write flag\r\n * @arg RTC_FLAG_ALRBWF: Alarm B Write flag\r\n * @arg RTC_FLAG_ALRAWF: Alarm A write flag\r\n * @retval The new state of RTC_FLAG (SET or RESET).\r\n */\r\nFlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG)\r\n{\r\n FlagStatus bitstatus = RESET;\r\n uint32_t tmpreg = 0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_RTC_GET_FLAG(RTC_FLAG));\r\n \r\n /* Get all the flags */\r\n tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK);\r\n \r\n /* Return the status of the flag */\r\n if ((tmpreg & RTC_FLAG) != (uint32_t)RESET)\r\n {\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n bitstatus = RESET;\r\n }\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @brief Clears the RTC's pending flags.\r\n * @param RTC_FLAG: specifies the RTC flag to clear.\r\n * This parameter can be any combination of the following values:\r\n * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag\r\n * @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag \r\n * @arg RTC_FLAG_TSF: Time Stamp event flag\r\n * @arg RTC_FLAG_WUTF: WakeUp Timer flag\r\n * @arg RTC_FLAG_ALRBF: Alarm B flag\r\n * @arg RTC_FLAG_ALRAF: Alarm A flag\r\n * @arg RTC_FLAG_RSF: Registers Synchronized flag\r\n * @retval None\r\n */\r\nvoid RTC_ClearFlag(uint32_t RTC_FLAG)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));\r\n\r\n /* Clear the Flags in the RTC_ISR register */\r\n RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); \r\n}\r\n\r\n/**\r\n * @brief Checks whether the specified RTC interrupt has occurred or not.\r\n * @param RTC_IT: specifies the RTC interrupt source to check.\r\n * This parameter can be one of the following values:\r\n * @arg RTC_IT_TS: Time Stamp interrupt \r\n * @arg RTC_IT_WUT: WakeUp Timer interrupt \r\n * @arg RTC_IT_ALRB: Alarm B interrupt \r\n * @arg RTC_IT_ALRA: Alarm A interrupt \r\n * @arg RTC_IT_TAMP1: Tamper 1 event interrupt \r\n * @retval The new state of RTC_IT (SET or RESET).\r\n */\r\nITStatus RTC_GetITStatus(uint32_t RTC_IT)\r\n{\r\n ITStatus bitstatus = RESET;\r\n uint32_t tmpreg = 0, enablestatus = 0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_RTC_GET_IT(RTC_IT));\r\n \r\n /* Get the TAMPER Interrupt enable bit and pending bit */\r\n tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE));\r\n \r\n /* Get the Interrupt enable Status */\r\n enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & (RTC_IT >> 15)));\r\n \r\n /* Get the Interrupt pending bit */\r\n tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4)));\r\n \r\n /* Get the status of the Interrupt */\r\n if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET))\r\n {\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n bitstatus = RESET;\r\n }\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @brief Clears the RTC's interrupt pending bits.\r\n * @param RTC_IT: specifies the RTC interrupt pending bit to clear.\r\n * This parameter can be any combination of the following values:\r\n * @arg RTC_IT_TS: Time Stamp interrupt \r\n * @arg RTC_IT_WUT: WakeUp Timer interrupt \r\n * @arg RTC_IT_ALRB: Alarm B interrupt \r\n * @arg RTC_IT_ALRA: Alarm A interrupt \r\n * @arg RTC_IT_TAMP1: Tamper 1 event interrupt \r\n * @retval None\r\n */\r\nvoid RTC_ClearITPendingBit(uint32_t RTC_IT)\r\n{\r\n uint32_t tmpreg = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_RTC_CLEAR_IT(RTC_IT));\r\n\r\n /* Get the RTC_ISR Interrupt pending bits mask */\r\n tmpreg = (uint32_t)(RTC_IT >> 4);\r\n\r\n /* Clear the interrupt pending bits in the RTC_ISR register */\r\n RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); \r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @brief Converts a 2 digit decimal to BCD format.\r\n * @param Value: Byte to be converted.\r\n * @retval Converted byte\r\n */\r\nstatic uint8_t RTC_ByteToBcd2(uint8_t Value)\r\n{\r\n uint8_t bcdhigh = 0;\r\n \r\n while (Value >= 10)\r\n {\r\n bcdhigh++;\r\n Value -= 10;\r\n }\r\n \r\n return ((uint8_t)(bcdhigh << 4) | Value);\r\n}\r\n\r\n/**\r\n * @brief Convert from 2 digit BCD to Binary.\r\n * @param Value: BCD value to be converted.\r\n * @retval Converted word\r\n */\r\nstatic uint8_t RTC_Bcd2ToByte(uint8_t Value)\r\n{\r\n uint8_t tmp = 0;\r\n tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;\r\n return (tmp + (Value & (uint8_t)0x0F));\r\n}\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sdio.c", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_sdio.c\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file provides firmware functions to manage the following \r\n * functionalities of the Secure digital input/output interface (SDIO) \r\n * peripheral:\r\n * - Initialization and Configuration\r\n * - Command path state machine (CPSM) management\r\n * - Data path state machine (DPSM) management\r\n * - SDIO IO Cards mode management\r\n * - CE-ATA mode management\r\n * - DMA transfers management\r\n * - Interrupts and flags management\r\n *\r\n * @verbatim\r\n *\r\n *\r\n * ===================================================================\r\n * How to use this driver\r\n * ===================================================================\r\n * 1. The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output\r\n * of PLL (PLL48CLK). Before to start working with SDIO peripheral\r\n * make sure that the PLL is well configured.\r\n * The SDIO peripheral uses two clock signals:\r\n * - SDIO adapter clock (SDIOCLK = 48 MHz)\r\n * - APB2 bus clock (PCLK2)\r\n * PCLK2 and SDIO_CK clock frequencies must respect the following condition:\r\n * Frequenc(PCLK2) >= (3 / 8 x Frequency(SDIO_CK))\r\n *\r\n * 2. Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE).\r\n *\r\n * 3. According to the SDIO mode, enable the GPIO clocks using \r\n * RCC_AHB1PeriphClockCmd() function. \r\n * The I/O can be one of the following configurations:\r\n * - 1-bit data length: SDIO_CMD, SDIO_CK and D0.\r\n * - 4-bit data length: SDIO_CMD, SDIO_CK and D[3:0].\r\n * - 8-bit data length: SDIO_CMD, SDIO_CK and D[7:0]. \r\n *\r\n * 4. Peripheral's alternate function: \r\n * - Connect the pin to the desired peripherals' Alternate \r\n * Function (AF) using GPIO_PinAFConfig() function\r\n * - Configure the desired pin in alternate function by:\r\n * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF\r\n * - Select the type, pull-up/pull-down and output speed via \r\n * GPIO_PuPd, GPIO_OType and GPIO_Speed members\r\n * - Call GPIO_Init() function\r\n *\r\n * 5. Program the Clock Edge, Clock Bypass, Clock Power Save, Bus Wide, \r\n * hardware, flow control and the Clock Divider using the SDIO_Init()\r\n * function.\r\n *\r\n * 6. Enable the Power ON State using the SDIO_SetPowerState(SDIO_PowerState_ON) \r\n * function.\r\n * \r\n * 7. Enable the clock using the SDIO_ClockCmd() function.\r\n *\r\n * 8. Enable the NVIC and the corresponding interrupt using the function \r\n * SDIO_ITConfig() if you need to use interrupt mode. \r\n *\r\n * 9. When using the DMA mode \r\n * - Configure the DMA using DMA_Init() function\r\n * - Active the needed channel Request using SDIO_DMACmd() function\r\n *\r\n * 10. Enable the DMA using the DMA_Cmd() function, when using DMA mode. \r\n *\r\n * 11. To control the CPSM (Command Path State Machine) and send \r\n * commands to the card use the SDIO_SendCommand(), \r\n * SDIO_GetCommandResponse() and SDIO_GetResponse() functions. \r\n * First, user has to fill the command structure (pointer to\r\n * SDIO_CmdInitTypeDef) according to the selected command to be sent.\r\n * The parameters that should be filled are:\r\n * - Command Argument\r\n * - Command Index\r\n * - Command Response type\r\n * - Command Wait\r\n * - CPSM Status (Enable or Disable)\r\n *\r\n * To check if the command is well received, read the SDIO_CMDRESP\r\n * register using the SDIO_GetCommandResponse().\r\n * The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the\r\n * SDIO_GetResponse() function.\r\n *\r\n * 12. To control the DPSM (Data Path State Machine) and send/receive \r\n * data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(), \r\n * SDIO_ReadData(), SDIO_WriteData() and SDIO_GetFIFOCount() functions.\r\n *\r\n * Read Operations\r\n * ---------------\r\n * a) First, user has to fill the data structure (pointer to\r\n * SDIO_DataInitTypeDef) according to the selected data type to\r\n * be received.\r\n * The parameters that should be filled are:\r\n * - Data TimeOut\r\n * - Data Length\r\n * - Data Block size\r\n * - Data Transfer direction: should be from card (To SDIO)\r\n * - Data Transfer mode\r\n * - DPSM Status (Enable or Disable)\r\n * \r\n * b) Configure the SDIO resources to receive the data from the card\r\n * according to selected transfer mode (Refer to Step 8, 9 and 10).\r\n *\r\n * c) Send the selected Read command (refer to step 11).\r\n * \r\n * d) Use the SDIO flags/interrupts to check the transfer status.\r\n *\r\n * Write Operations\r\n * ---------------\r\n * a) First, user has to fill the data structure (pointer to\r\n * SDIO_DataInitTypeDef) according to the selected data type to\r\n * be received.\r\n * The parameters that should be filled are:\r\n * - Data TimeOut\r\n * - Data Length\r\n * - Data Block size\r\n * - Data Transfer direction: should be to card (To CARD)\r\n * - Data Transfer mode\r\n * - DPSM Status (Enable or Disable)\r\n *\r\n * b) Configure the SDIO resources to send the data to the card\r\n * according to selected transfer mode (Refer to Step 8, 9 and 10).\r\n * \r\n * c) Send the selected Write command (refer to step 11).\r\n * \r\n * d) Use the SDIO flags/interrupts to check the transfer status.\r\n *\r\n *\r\n * @endverbatim\r\n *\r\n *\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx_sdio.h\"\r\n#include \"stm32f4xx_rcc.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @defgroup SDIO \r\n * @brief SDIO driver modules\r\n * @{\r\n */ \r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n\r\n/* ------------ SDIO registers bit address in the alias region ----------- */\r\n#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)\r\n\r\n/* --- CLKCR Register ---*/\r\n/* Alias word address of CLKEN bit */\r\n#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)\r\n#define CLKEN_BitNumber 0x08\r\n#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))\r\n\r\n/* --- CMD Register ---*/\r\n/* Alias word address of SDIOSUSPEND bit */\r\n#define CMD_OFFSET (SDIO_OFFSET + 0x0C)\r\n#define SDIOSUSPEND_BitNumber 0x0B\r\n#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))\r\n\r\n/* Alias word address of ENCMDCOMPL bit */\r\n#define ENCMDCOMPL_BitNumber 0x0C\r\n#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))\r\n\r\n/* Alias word address of NIEN bit */\r\n#define NIEN_BitNumber 0x0D\r\n#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))\r\n\r\n/* Alias word address of ATACMD bit */\r\n#define ATACMD_BitNumber 0x0E\r\n#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))\r\n\r\n/* --- DCTRL Register ---*/\r\n/* Alias word address of DMAEN bit */\r\n#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)\r\n#define DMAEN_BitNumber 0x03\r\n#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))\r\n\r\n/* Alias word address of RWSTART bit */\r\n#define RWSTART_BitNumber 0x08\r\n#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))\r\n\r\n/* Alias word address of RWSTOP bit */\r\n#define RWSTOP_BitNumber 0x09\r\n#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))\r\n\r\n/* Alias word address of RWMOD bit */\r\n#define RWMOD_BitNumber 0x0A\r\n#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))\r\n\r\n/* Alias word address of SDIOEN bit */\r\n#define SDIOEN_BitNumber 0x0B\r\n#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))\r\n\r\n/* ---------------------- SDIO registers bit mask ------------------------ */\r\n/* --- CLKCR Register ---*/\r\n/* CLKCR register clear mask */\r\n#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) \r\n\r\n/* --- PWRCTRL Register ---*/\r\n/* SDIO PWRCTRL Mask */\r\n#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)\r\n\r\n/* --- DCTRL Register ---*/\r\n/* SDIO DCTRL Clear Mask */\r\n#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)\r\n\r\n/* --- CMD Register ---*/\r\n/* CMD Register clear mask */\r\n#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)\r\n\r\n/* SDIO RESP Registers Address */\r\n#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup SDIO_Private_Functions\r\n * @{\r\n */\r\n\r\n/** @defgroup SDIO_Group1 Initialization and Configuration functions\r\n * @brief Initialization and Configuration functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Initialization and Configuration functions\r\n ===============================================================================\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Deinitializes the SDIO peripheral registers to their default reset values.\r\n * @param None\r\n * @retval None\r\n */\r\nvoid SDIO_DeInit(void)\r\n{\r\n RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, ENABLE);\r\n RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, DISABLE);\r\n}\r\n\r\n/**\r\n * @brief Initializes the SDIO peripheral according to the specified \r\n * parameters in the SDIO_InitStruct.\r\n * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure \r\n * that contains the configuration information for the SDIO peripheral.\r\n * @retval None\r\n */\r\nvoid SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)\r\n{\r\n uint32_t tmpreg = 0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));\r\n assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));\r\n assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));\r\n assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));\r\n assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); \r\n \r\n/*---------------------------- SDIO CLKCR Configuration ------------------------*/ \r\n /* Get the SDIO CLKCR value */\r\n tmpreg = SDIO->CLKCR;\r\n \r\n /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */\r\n tmpreg &= CLKCR_CLEAR_MASK;\r\n \r\n /* Set CLKDIV bits according to SDIO_ClockDiv value */\r\n /* Set PWRSAV bit according to SDIO_ClockPowerSave value */\r\n /* Set BYPASS bit according to SDIO_ClockBypass value */\r\n /* Set WIDBUS bits according to SDIO_BusWide value */\r\n /* Set NEGEDGE bits according to SDIO_ClockEdge value */\r\n /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */\r\n tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |\r\n SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |\r\n SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); \r\n \r\n /* Write to SDIO CLKCR */\r\n SDIO->CLKCR = tmpreg;\r\n}\r\n\r\n/**\r\n * @brief Fills each SDIO_InitStruct member with its default value.\r\n * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which \r\n * will be initialized.\r\n * @retval None\r\n */\r\nvoid SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)\r\n{\r\n /* SDIO_InitStruct members default value */\r\n SDIO_InitStruct->SDIO_ClockDiv = 0x00;\r\n SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;\r\n SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;\r\n SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;\r\n SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;\r\n SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the SDIO Clock.\r\n * @param NewState: new state of the SDIO Clock. \r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid SDIO_ClockCmd(FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;\r\n}\r\n\r\n/**\r\n * @brief Sets the power status of the controller.\r\n * @param SDIO_PowerState: new state of the Power state. \r\n * This parameter can be one of the following values:\r\n * @arg SDIO_PowerState_OFF: SDIO Power OFF\r\n * @arg SDIO_PowerState_ON: SDIO Power ON\r\n * @retval None\r\n */\r\nvoid SDIO_SetPowerState(uint32_t SDIO_PowerState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));\r\n \r\n SDIO->POWER = SDIO_PowerState;\r\n}\r\n\r\n/**\r\n * @brief Gets the power status of the controller.\r\n * @param None\r\n * @retval Power status of the controller. The returned value can be one of the \r\n * following values:\r\n * - 0x00: Power OFF\r\n * - 0x02: Power UP\r\n * - 0x03: Power ON \r\n */\r\nuint32_t SDIO_GetPowerState(void)\r\n{\r\n return (SDIO->POWER & (~PWR_PWRCTRL_MASK));\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SDIO_Group2 Command path state machine (CPSM) management functions\r\n * @brief Command path state machine (CPSM) management functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Command path state machine (CPSM) management functions\r\n =============================================================================== \r\n\r\n This section provide functions allowing to program and read the Command path \r\n state machine (CPSM).\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Initializes the SDIO Command according to the specified \r\n * parameters in the SDIO_CmdInitStruct and send the command.\r\n * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef \r\n * structure that contains the configuration information for the SDIO \r\n * command.\r\n * @retval None\r\n */\r\nvoid SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)\r\n{\r\n uint32_t tmpreg = 0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));\r\n assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));\r\n assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));\r\n assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));\r\n \r\n/*---------------------------- SDIO ARG Configuration ------------------------*/\r\n /* Set the SDIO Argument value */\r\n SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;\r\n \r\n/*---------------------------- SDIO CMD Configuration ------------------------*/ \r\n /* Get the SDIO CMD value */\r\n tmpreg = SDIO->CMD;\r\n /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */\r\n tmpreg &= CMD_CLEAR_MASK;\r\n /* Set CMDINDEX bits according to SDIO_CmdIndex value */\r\n /* Set WAITRESP bits according to SDIO_Response value */\r\n /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */\r\n /* Set CPSMEN bits according to SDIO_CPSM value */\r\n tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response\r\n | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;\r\n \r\n /* Write to SDIO CMD */\r\n SDIO->CMD = tmpreg;\r\n}\r\n\r\n/**\r\n * @brief Fills each SDIO_CmdInitStruct member with its default value.\r\n * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef \r\n * structure which will be initialized.\r\n * @retval None\r\n */\r\nvoid SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)\r\n{\r\n /* SDIO_CmdInitStruct members default value */\r\n SDIO_CmdInitStruct->SDIO_Argument = 0x00;\r\n SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;\r\n SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;\r\n SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;\r\n SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;\r\n}\r\n\r\n/**\r\n * @brief Returns command index of last command for which response received.\r\n * @param None\r\n * @retval Returns the command index of the last command response received.\r\n */\r\nuint8_t SDIO_GetCommandResponse(void)\r\n{\r\n return (uint8_t)(SDIO->RESPCMD);\r\n}\r\n\r\n/**\r\n * @brief Returns response received from the card for the last command.\r\n * @param SDIO_RESP: Specifies the SDIO response register. \r\n * This parameter can be one of the following values:\r\n * @arg SDIO_RESP1: Response Register 1\r\n * @arg SDIO_RESP2: Response Register 2\r\n * @arg SDIO_RESP3: Response Register 3\r\n * @arg SDIO_RESP4: Response Register 4\r\n * @retval The Corresponding response register value.\r\n */\r\nuint32_t SDIO_GetResponse(uint32_t SDIO_RESP)\r\n{\r\n __IO uint32_t tmp = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_SDIO_RESP(SDIO_RESP));\r\n\r\n tmp = SDIO_RESP_ADDR + SDIO_RESP;\r\n \r\n return (*(__IO uint32_t *) tmp); \r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SDIO_Group3 Data path state machine (DPSM) management functions\r\n * @brief Data path state machine (DPSM) management functions\r\n *\r\n@verbatim \r\n ===============================================================================\r\n Data path state machine (DPSM) management functions\r\n =============================================================================== \r\n\r\n This section provide functions allowing to program and read the Data path \r\n state machine (DPSM).\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Initializes the SDIO data path according to the specified \r\n * parameters in the SDIO_DataInitStruct.\r\n * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure \r\n * that contains the configuration information for the SDIO command.\r\n * @retval None\r\n */\r\nvoid SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)\r\n{\r\n uint32_t tmpreg = 0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));\r\n assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));\r\n assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));\r\n assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));\r\n assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));\r\n\r\n/*---------------------------- SDIO DTIMER Configuration ---------------------*/\r\n /* Set the SDIO Data TimeOut value */\r\n SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;\r\n\r\n/*---------------------------- SDIO DLEN Configuration -----------------------*/\r\n /* Set the SDIO DataLength value */\r\n SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;\r\n\r\n/*---------------------------- SDIO DCTRL Configuration ----------------------*/ \r\n /* Get the SDIO DCTRL value */\r\n tmpreg = SDIO->DCTRL;\r\n /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */\r\n tmpreg &= DCTRL_CLEAR_MASK;\r\n /* Set DEN bit according to SDIO_DPSM value */\r\n /* Set DTMODE bit according to SDIO_TransferMode value */\r\n /* Set DTDIR bit according to SDIO_TransferDir value */\r\n /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */\r\n tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir\r\n | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;\r\n\r\n /* Write to SDIO DCTRL */\r\n SDIO->DCTRL = tmpreg;\r\n}\r\n\r\n/**\r\n * @brief Fills each SDIO_DataInitStruct member with its default value.\r\n * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure \r\n * which will be initialized.\r\n * @retval None\r\n */\r\nvoid SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)\r\n{\r\n /* SDIO_DataInitStruct members default value */\r\n SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;\r\n SDIO_DataInitStruct->SDIO_DataLength = 0x00;\r\n SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;\r\n SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;\r\n SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; \r\n SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;\r\n}\r\n\r\n/**\r\n * @brief Returns number of remaining data bytes to be transferred.\r\n * @param None\r\n * @retval Number of remaining data bytes to be transferred\r\n */\r\nuint32_t SDIO_GetDataCounter(void)\r\n{ \r\n return SDIO->DCOUNT;\r\n}\r\n\r\n/**\r\n * @brief Read one data word from Rx FIFO.\r\n * @param None\r\n * @retval Data received\r\n */\r\nuint32_t SDIO_ReadData(void)\r\n{ \r\n return SDIO->FIFO;\r\n}\r\n\r\n/**\r\n * @brief Write one data word to Tx FIFO.\r\n * @param Data: 32-bit data word to write.\r\n * @retval None\r\n */\r\nvoid SDIO_WriteData(uint32_t Data)\r\n{ \r\n SDIO->FIFO = Data;\r\n}\r\n\r\n/**\r\n * @brief Returns the number of words left to be written to or read from FIFO.\t\r\n * @param None\r\n * @retval Remaining number of words.\r\n */\r\nuint32_t SDIO_GetFIFOCount(void)\r\n{ \r\n return SDIO->FIFOCNT;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SDIO_Group4 SDIO IO Cards mode management functions\r\n * @brief SDIO IO Cards mode management functions\r\n *\r\n@verbatim \r\n ===============================================================================\r\n SDIO IO Cards mode management functions\r\n =============================================================================== \r\n\r\n This section provide functions allowing to program and read the SDIO IO Cards.\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Starts the SD I/O Read Wait operation.\t\r\n * @param NewState: new state of the Start SDIO Read Wait operation. \r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid SDIO_StartSDIOReadWait(FunctionalState NewState)\r\n{ \r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;\r\n}\r\n\r\n/**\r\n * @brief Stops the SD I/O Read Wait operation.\t\r\n * @param NewState: new state of the Stop SDIO Read Wait operation. \r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid SDIO_StopSDIOReadWait(FunctionalState NewState)\r\n{ \r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;\r\n}\r\n\r\n/**\r\n * @brief Sets one of the two options of inserting read wait interval.\r\n * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.\r\n * This parameter can be:\r\n * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK\r\n * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2\r\n * @retval None\r\n */\r\nvoid SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));\r\n \r\n *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the SD I/O Mode Operation.\r\n * @param NewState: new state of SDIO specific operation. \r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid SDIO_SetSDIOOperation(FunctionalState NewState)\r\n{ \r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the SD I/O Mode suspend command sending.\r\n * @param NewState: new state of the SD I/O Mode suspend command.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid SDIO_SendSDIOSuspendCmd(FunctionalState NewState)\r\n{ \r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SDIO_Group5 CE-ATA mode management functions\r\n * @brief CE-ATA mode management functions\r\n *\r\n@verbatim \r\n ===============================================================================\r\n CE-ATA mode management functions\r\n =============================================================================== \r\n\r\n This section provide functions allowing to program and read the CE-ATA card.\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Enables or disables the command completion signal.\r\n * @param NewState: new state of command completion signal. \r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid SDIO_CommandCompletionCmd(FunctionalState NewState)\r\n{ \r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the CE-ATA interrupt.\r\n * @param NewState: new state of CE-ATA interrupt. \r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid SDIO_CEATAITCmd(FunctionalState NewState)\r\n{ \r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));\r\n}\r\n\r\n/**\r\n * @brief Sends CE-ATA command (CMD61).\r\n * @param NewState: new state of CE-ATA command. \r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid SDIO_SendCEATACmd(FunctionalState NewState)\r\n{ \r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SDIO_Group6 DMA transfers management functions\r\n * @brief DMA transfers management functions\r\n *\r\n@verbatim \r\n ===============================================================================\r\n DMA transfers management functions\r\n =============================================================================== \r\n\r\n This section provide functions allowing to program SDIO DMA transfer.\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Enables or disables the SDIO DMA request.\r\n * @param NewState: new state of the selected SDIO DMA request.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid SDIO_DMACmd(FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SDIO_Group7 Interrupts and flags management functions\r\n * @brief Interrupts and flags management functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Interrupts and flags management functions\r\n =============================================================================== \r\n\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Enables or disables the SDIO interrupts.\r\n * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.\r\n * This parameter can be one or a combination of the following values:\r\n * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r\n * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r\n * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt\r\n * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt\r\n * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r\n * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt\r\n * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt\r\n * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt\r\n * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt\r\n * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide \r\n * bus mode interrupt\r\n * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt\r\n * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt\r\n * @arg SDIO_IT_TXACT: Data transmit in progress interrupt\r\n * @arg SDIO_IT_RXACT: Data receive in progress interrupt\r\n * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r\n * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r\n * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt\r\n * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt\r\n * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt\r\n * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt\r\n * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt\r\n * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt\r\n * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt\r\n * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt\r\n * @param NewState: new state of the specified SDIO interrupts.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None \r\n */\r\nvoid SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_SDIO_IT(SDIO_IT));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the SDIO interrupts */\r\n SDIO->MASK |= SDIO_IT;\r\n }\r\n else\r\n {\r\n /* Disable the SDIO interrupts */\r\n SDIO->MASK &= ~SDIO_IT;\r\n } \r\n}\r\n\r\n/**\r\n * @brief Checks whether the specified SDIO flag is set or not.\r\n * @param SDIO_FLAG: specifies the flag to check. \r\n * This parameter can be one of the following values:\r\n * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)\r\n * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)\r\n * @arg SDIO_FLAG_CTIMEOUT: Command response timeout\r\n * @arg SDIO_FLAG_DTIMEOUT: Data timeout\r\n * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error\r\n * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error\r\n * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)\r\n * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)\r\n * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)\r\n * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.\r\n * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)\r\n * @arg SDIO_FLAG_CMDACT: Command transfer in progress\r\n * @arg SDIO_FLAG_TXACT: Data transmit in progress\r\n * @arg SDIO_FLAG_RXACT: Data receive in progress\r\n * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty\r\n * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full\r\n * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full\r\n * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full\r\n * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty\r\n * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty\r\n * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO\r\n * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO\r\n * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received\r\n * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61\r\n * @retval The new state of SDIO_FLAG (SET or RESET).\r\n */\r\nFlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)\r\n{ \r\n FlagStatus bitstatus = RESET;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_SDIO_FLAG(SDIO_FLAG));\r\n \r\n if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)\r\n {\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n bitstatus = RESET;\r\n }\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @brief Clears the SDIO's pending flags.\r\n * @param SDIO_FLAG: specifies the flag to clear. \r\n * This parameter can be one or a combination of the following values:\r\n * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)\r\n * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)\r\n * @arg SDIO_FLAG_CTIMEOUT: Command response timeout\r\n * @arg SDIO_FLAG_DTIMEOUT: Data timeout\r\n * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error\r\n * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error\r\n * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)\r\n * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)\r\n * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)\r\n * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode\r\n * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)\r\n * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received\r\n * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61\r\n * @retval None\r\n */\r\nvoid SDIO_ClearFlag(uint32_t SDIO_FLAG)\r\n{ \r\n /* Check the parameters */\r\n assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));\r\n \r\n SDIO->ICR = SDIO_FLAG;\r\n}\r\n\r\n/**\r\n * @brief Checks whether the specified SDIO interrupt has occurred or not.\r\n * @param SDIO_IT: specifies the SDIO interrupt source to check. \r\n * This parameter can be one of the following values:\r\n * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r\n * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r\n * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt\r\n * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt\r\n * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r\n * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt\r\n * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt\r\n * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt\r\n * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt\r\n * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide \r\n * bus mode interrupt\r\n * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt\r\n * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt\r\n * @arg SDIO_IT_TXACT: Data transmit in progress interrupt\r\n * @arg SDIO_IT_RXACT: Data receive in progress interrupt\r\n * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r\n * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r\n * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt\r\n * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt\r\n * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt\r\n * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt\r\n * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt\r\n * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt\r\n * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt\r\n * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt\r\n * @retval The new state of SDIO_IT (SET or RESET).\r\n */\r\nITStatus SDIO_GetITStatus(uint32_t SDIO_IT)\r\n{ \r\n ITStatus bitstatus = RESET;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_SDIO_GET_IT(SDIO_IT));\r\n if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) \r\n {\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n bitstatus = RESET;\r\n }\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @brief Clears the SDIO's interrupt pending bits.\r\n * @param SDIO_IT: specifies the interrupt pending bit to clear. \r\n * This parameter can be one or a combination of the following values:\r\n * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r\n * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r\n * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt\r\n * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt\r\n * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r\n * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt\r\n * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt\r\n * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt\r\n * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt\r\n * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide \r\n * bus mode interrupt\r\n * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt\r\n * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61\r\n * @retval None\r\n */\r\nvoid SDIO_ClearITPendingBit(uint32_t SDIO_IT)\r\n{ \r\n /* Check the parameters */\r\n assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));\r\n \r\n SDIO->ICR = SDIO_IT;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_spi.c\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file provides firmware functions to manage the following \r\n * functionalities of the Serial peripheral interface (SPI):\r\n * - Initialization and Configuration\r\n * - Data transfers functions\r\n * - Hardware CRC Calculation\r\n * - DMA transfers management\r\n * - Interrupts and flags management \r\n * \r\n * @verbatim\r\n * \r\n * \r\n * ===================================================================\r\n * How to use this driver\r\n * ===================================================================\r\n * \r\n * 1. Enable peripheral clock using the following functions \r\n * RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) for SPI1\r\n * RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) for SPI2\r\n * RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI3.\r\n *\r\n * 2. Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHB1PeriphClockCmd()\r\n * function.\r\n * In I2S mode, if an external clock source is used then the I2S CKIN pin GPIO\r\n * clock should also be enabled.\r\n *\r\n * 3. Peripherals alternate function: \r\n * - Connect the pin to the desired peripherals' Alternate \r\n * Function (AF) using GPIO_PinAFConfig() function\r\n * - Configure the desired pin in alternate function by:\r\n * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF\r\n * - Select the type, pull-up/pull-down and output speed via \r\n * GPIO_PuPd, GPIO_OType and GPIO_Speed members\r\n * - Call GPIO_Init() function\r\n * In I2S mode, if an external clock source is used then the I2S CKIN pin\r\n * should be also configured in Alternate function Push-pull pull-up mode. \r\n * \r\n * 4. Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave \r\n * Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()\r\n * function.\r\n * In I2S mode, program the Mode, Standard, Data Format, MCLK Output, Audio \r\n * frequency and Polarity using I2S_Init() function.\r\n * For I2S mode, make sure that either:\r\n * - I2S PLL is configured using the functions RCC_I2SCLKConfig(RCC_I2S2CLKSource_PLLI2S), \r\n * RCC_PLLI2SCmd(ENABLE) and RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY).\r\n * or \r\n * - External clock source is configured using the function \r\n * RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly the define constant\r\n * I2S_EXTERNAL_CLOCK_VAL in the stm32f4xx_conf.h file. \r\n *\r\n * 5. Enable the NVIC and the corresponding interrupt using the function \r\n * SPI_ITConfig() if you need to use interrupt mode. \r\n *\r\n * 6. When using the DMA mode \r\n * - Configure the DMA using DMA_Init() function\r\n * - Active the needed channel Request using SPI_I2S_DMACmd() function\r\n * \r\n * 7. Enable the SPI using the SPI_Cmd() function or enable the I2S using\r\n * I2S_Cmd().\r\n * \r\n * 8. Enable the DMA using the DMA_Cmd() function when using DMA mode. \r\n *\r\n * 9. Optionally, you can enable/configure the following parameters without\r\n * re-initialization (i.e there is no need to call again SPI_Init() function):\r\n * - When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)\r\n * is programmed as Data direction parameter using the SPI_Init() function\r\n * it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx\r\n * using the SPI_BiDirectionalLineConfig() function.\r\n * - When SPI_NSS_Soft is selected as Slave Select Management parameter \r\n * using the SPI_Init() function it can be possible to manage the \r\n * NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.\r\n * - Reconfigure the data size using the SPI_DataSizeConfig() function \r\n * - Enable or disable the SS output using the SPI_SSOutputCmd() function \r\n * \r\n * 10. To use the CRC Hardware calculation feature refer to the Peripheral \r\n * CRC hardware Calculation subsection.\r\n * \r\n *\r\n * It is possible to use SPI in I2S full duplex mode, in this case, each SPI \r\n * peripheral is able to manage sending and receiving data simultaneously\r\n * using two data lines. Each SPI peripheral has an extended block called I2Sxext\r\n * (ie. I2S2ext for SPI2 and I2S3ext for SPI3).\r\n * The extension block is not a full SPI IP, it is used only as I2S slave to\r\n * implement full duplex mode. The extension block uses the same clock sources\r\n * as its master. \r\n * To configure I2S full duplex you have to:\r\n * \r\n * 1. Configure SPIx in I2S mode (I2S_Init() function) as described above. \r\n * \r\n * 2. Call the I2S_FullDuplexConfig() function using the same strucutre passed to \r\n * I2S_Init() function.\r\n * \r\n * 3. Call I2S_Cmd() for SPIx then for its extended block.\r\n * \r\n * 4. To configure interrupts or DMA requests and to get/clear flag status, \r\n * use I2Sxext instance for the extension block.\r\n * \r\n * Functions that can be called with I2Sxext instances are:\r\n * I2S_Cmd(), I2S_FullDuplexConfig(), SPI_I2S_ReceiveData(), SPI_I2S_SendData(), \r\n * SPI_I2S_DMACmd(), SPI_I2S_ITConfig(), SPI_I2S_GetFlagStatus(), SPI_I2S_ClearFlag(),\r\n * SPI_I2S_GetITStatus() and SPI_I2S_ClearITPendingBit().\r\n * \r\n * Example: To use SPI3 in Full duplex mode (SPI3 is Master Tx, I2S3ext is Slave Rx):\r\n * \r\n * RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE); \r\n * I2S_StructInit(&I2SInitStruct);\r\n * I2SInitStruct.Mode = I2S_Mode_MasterTx; \r\n * I2S_Init(SPI3, &I2SInitStruct);\r\n * I2S_FullDuplexConfig(SPI3ext, &I2SInitStruct)\r\n * I2S_Cmd(SPI3, ENABLE);\r\n * I2S_Cmd(SPI3ext, ENABLE);\r\n * ...\r\n * while (SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)\r\n * {}\r\n * SPI_I2S_SendData(SPI3, txdata[i]);\r\n * ... \r\n * while (SPI_I2S_GetFlagStatus(I2S3ext, SPI_FLAG_RXNE) == RESET)\r\n * {}\r\n * rxdata[i] = SPI_I2S_ReceiveData(I2S3ext);\r\n * ... \r\n * \r\n * \r\n * @note In I2S mode: if an external clock is used as source clock for the I2S, \r\n * then the define I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should \r\n * be enabled and set to the value of the source clock frequency (in Hz).\r\n * \r\n * @note In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd() \r\n * just after calling the function SPI_Init().\r\n *\r\n * @endverbatim \r\n * \r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx_spi.h\"\r\n#include \"stm32f4xx_rcc.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @defgroup SPI \r\n * @brief SPI driver modules\r\n * @{\r\n */ \r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n\r\n/* SPI registers Masks */\r\n#define CR1_CLEAR_MASK ((uint16_t)0x3040)\r\n#define I2SCFGR_CLEAR_MASK ((uint16_t)0xF040)\r\n\r\n/* RCC PLLs masks */\r\n#define PLLCFGR_PPLR_MASK ((uint32_t)0x70000000)\r\n#define PLLCFGR_PPLN_MASK ((uint32_t)0x00007FC0)\r\n\r\n#define SPI_CR2_FRF ((uint16_t)0x0010)\r\n#define SPI_SR_TIFRFE ((uint16_t)0x0100)\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup SPI_Private_Functions\r\n * @{\r\n */\r\n\r\n/** @defgroup SPI_Group1 Initialization and Configuration functions\r\n * @brief Initialization and Configuration functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Initialization and Configuration functions\r\n =============================================================================== \r\n\r\n This section provides a set of functions allowing to initialize the SPI Direction,\r\n SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud\r\n Rate Prescaler, SPI First Bit and SPI CRC Polynomial.\r\n \r\n The SPI_Init() function follows the SPI configuration procedures for Master mode\r\n and Slave mode (details for these procedures are available in reference manual\r\n (RM0090)).\r\n \r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Deinitialize the SPIx peripheral registers to their default reset values.\r\n * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 \r\n * in SPI mode or 2 or 3 in I2S mode. \r\n * \r\n * @note The extended I2S blocks (ie. I2S2ext and I2S3ext blocks) are deinitialized\r\n * when the relative I2S peripheral is deinitialized (the extended block's clock\r\n * is managed by the I2S peripheral clock).\r\n * \r\n * @retval None\r\n */\r\nvoid SPI_I2S_DeInit(SPI_TypeDef* SPIx)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_SPI_ALL_PERIPH(SPIx));\r\n\r\n if (SPIx == SPI1)\r\n {\r\n /* Enable SPI1 reset state */\r\n RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);\r\n /* Release SPI1 from reset state */\r\n RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);\r\n }\r\n else if (SPIx == SPI2)\r\n {\r\n /* Enable SPI2 reset state */\r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);\r\n /* Release SPI2 from reset state */\r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);\r\n }\r\n else\r\n {\r\n if (SPIx == SPI3)\r\n {\r\n /* Enable SPI3 reset state */\r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);\r\n /* Release SPI3 from reset state */\r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);\r\n }\r\n }\r\n}\r\n\r\n/**\r\n * @brief Initializes the SPIx peripheral according to the specified \r\n * parameters in the SPI_InitStruct.\r\n * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r\n * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that\r\n * contains the configuration information for the specified SPI peripheral.\r\n * @retval None\r\n */\r\nvoid SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)\r\n{\r\n uint16_t tmpreg = 0;\r\n \r\n /* check the parameters */\r\n assert_param(IS_SPI_ALL_PERIPH(SPIx));\r\n \r\n /* Check the SPI parameters */\r\n assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));\r\n assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));\r\n assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));\r\n assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));\r\n assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));\r\n assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));\r\n assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));\r\n assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));\r\n assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));\r\n\r\n/*---------------------------- SPIx CR1 Configuration ------------------------*/\r\n /* Get the SPIx CR1 value */\r\n tmpreg = SPIx->CR1;\r\n /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */\r\n tmpreg &= CR1_CLEAR_MASK;\r\n /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler\r\n master/salve mode, CPOL and CPHA */\r\n /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */\r\n /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */\r\n /* Set LSBFirst bit according to SPI_FirstBit value */\r\n /* Set BR bits according to SPI_BaudRatePrescaler value */\r\n /* Set CPOL bit according to SPI_CPOL value */\r\n /* Set CPHA bit according to SPI_CPHA value */\r\n tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |\r\n SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | \r\n SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | \r\n SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);\r\n /* Write to SPIx CR1 */\r\n SPIx->CR1 = tmpreg;\r\n\r\n /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */\r\n SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD);\r\n/*---------------------------- SPIx CRCPOLY Configuration --------------------*/\r\n /* Write to SPIx CRCPOLY */\r\n SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;\r\n}\r\n\r\n/**\r\n * @brief Initializes the SPIx peripheral according to the specified \r\n * parameters in the I2S_InitStruct.\r\n * @param SPIx: where x can be 2 or 3 to select the SPI peripheral (configured in I2S mode).\r\n * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that\r\n * contains the configuration information for the specified SPI peripheral\r\n * configured in I2S mode.\r\n * \r\n * @note The function calculates the optimal prescaler needed to obtain the most \r\n * accurate audio frequency (depending on the I2S clock source, the PLL values \r\n * and the product configuration). But in case the prescaler value is greater \r\n * than 511, the default value (0x02) will be configured instead. \r\n * \r\n * @note if an external clock is used as source clock for the I2S, then the define\r\n * I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should be enabled and set\r\n * to the value of the the source clock frequency (in Hz).\r\n * \r\n * @retval None\r\n */\r\nvoid I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)\r\n{\r\n uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;\r\n uint32_t tmp = 0, i2sclk = 0;\r\n#ifndef I2S_EXTERNAL_CLOCK_VAL\r\n uint32_t pllm = 0, plln = 0, pllr = 0;\r\n#endif /* I2S_EXTERNAL_CLOCK_VAL */\r\n \r\n /* Check the I2S parameters */\r\n assert_param(IS_SPI_23_PERIPH(SPIx));\r\n assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));\r\n assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));\r\n assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));\r\n assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));\r\n assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));\r\n assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); \r\n\r\n/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/\r\n /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */\r\n SPIx->I2SCFGR &= I2SCFGR_CLEAR_MASK; \r\n SPIx->I2SPR = 0x0002;\r\n \r\n /* Get the I2SCFGR register value */\r\n tmpreg = SPIx->I2SCFGR;\r\n \r\n /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/\r\n if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)\r\n {\r\n i2sodd = (uint16_t)0;\r\n i2sdiv = (uint16_t)2; \r\n }\r\n /* If the requested audio frequency is not the default, compute the prescaler */\r\n else\r\n {\r\n /* Check the frame length (For the Prescaler computing) *******************/\r\n if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)\r\n {\r\n /* Packet length is 16 bits */\r\n packetlength = 1;\r\n }\r\n else\r\n {\r\n /* Packet length is 32 bits */\r\n packetlength = 2;\r\n }\r\n\r\n /* Get I2S source Clock frequency ****************************************/\r\n \r\n /* If an external I2S clock has to be used, this define should be set \r\n in the project configuration or in the stm32f4xx_conf.h file */\r\n #ifdef I2S_EXTERNAL_CLOCK_VAL \r\n /* Set external clock as I2S clock source */\r\n if ((RCC->CFGR & RCC_CFGR_I2SSRC) == 0)\r\n {\r\n RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC;\r\n }\r\n \r\n /* Set the I2S clock to the external clock value */\r\n i2sclk = I2S_EXTERNAL_CLOCK_VAL;\r\n\r\n #else /* There is no define for External I2S clock source */\r\n /* Set PLLI2S as I2S clock source */\r\n if ((RCC->CFGR & RCC_CFGR_I2SSRC) != 0)\r\n {\r\n RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC;\r\n } \r\n \r\n /* Get the PLLI2SN value */\r\n plln = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & \\\r\n (RCC_PLLI2SCFGR_PLLI2SN >> 6));\r\n \r\n /* Get the PLLI2SR value */\r\n pllr = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & \\\r\n (RCC_PLLI2SCFGR_PLLI2SR >> 28));\r\n \r\n /* Get the PLLM value */\r\n pllm = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); \r\n \r\n /* Get the I2S source clock value */\r\n i2sclk = (uint32_t)(((HSE_VALUE / pllm) * plln) / pllr);\r\n #endif /* I2S_EXTERNAL_CLOCK_VAL */\r\n \r\n /* Compute the Real divider depending on the MCLK output state, with a floating point */\r\n if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)\r\n {\r\n /* MCLK output is enabled */\r\n tmp = (uint16_t)(((((i2sclk / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);\r\n }\r\n else\r\n {\r\n /* MCLK output is disabled */\r\n tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);\r\n }\r\n \r\n /* Remove the flatting point */\r\n tmp = tmp / 10; \r\n \r\n /* Check the parity of the divider */\r\n i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);\r\n \r\n /* Compute the i2sdiv prescaler */\r\n i2sdiv = (uint16_t)((tmp - i2sodd) / 2);\r\n \r\n /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */\r\n i2sodd = (uint16_t) (i2sodd << 8);\r\n }\r\n\r\n /* Test if the divider is 1 or 0 or greater than 0xFF */\r\n if ((i2sdiv < 2) || (i2sdiv > 0xFF))\r\n {\r\n /* Set the default values */\r\n i2sdiv = 2;\r\n i2sodd = 0;\r\n }\r\n\r\n /* Write to SPIx I2SPR register the computed value */\r\n SPIx->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));\r\n \r\n /* Configure the I2S with the SPI_InitStruct values */\r\n tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \\\r\n (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \\\r\n (uint16_t)I2S_InitStruct->I2S_CPOL))));\r\n \r\n /* Write to SPIx I2SCFGR */ \r\n SPIx->I2SCFGR = tmpreg;\r\n}\r\n\r\n/**\r\n * @brief Fills each SPI_InitStruct member with its default value.\r\n * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized.\r\n * @retval None\r\n */\r\nvoid SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)\r\n{\r\n/*--------------- Reset SPI init structure parameters values -----------------*/\r\n /* Initialize the SPI_Direction member */\r\n SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;\r\n /* initialize the SPI_Mode member */\r\n SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;\r\n /* initialize the SPI_DataSize member */\r\n SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;\r\n /* Initialize the SPI_CPOL member */\r\n SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;\r\n /* Initialize the SPI_CPHA member */\r\n SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;\r\n /* Initialize the SPI_NSS member */\r\n SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;\r\n /* Initialize the SPI_BaudRatePrescaler member */\r\n SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;\r\n /* Initialize the SPI_FirstBit member */\r\n SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;\r\n /* Initialize the SPI_CRCPolynomial member */\r\n SPI_InitStruct->SPI_CRCPolynomial = 7;\r\n}\r\n\r\n/**\r\n * @brief Fills each I2S_InitStruct member with its default value.\r\n * @param I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized.\r\n * @retval None\r\n */\r\nvoid I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)\r\n{\r\n/*--------------- Reset I2S init structure parameters values -----------------*/\r\n /* Initialize the I2S_Mode member */\r\n I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;\r\n \r\n /* Initialize the I2S_Standard member */\r\n I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;\r\n \r\n /* Initialize the I2S_DataFormat member */\r\n I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;\r\n \r\n /* Initialize the I2S_MCLKOutput member */\r\n I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;\r\n \r\n /* Initialize the I2S_AudioFreq member */\r\n I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;\r\n \r\n /* Initialize the I2S_CPOL member */\r\n I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the specified SPI peripheral.\r\n * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r\n * @param NewState: new state of the SPIx peripheral. \r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_SPI_ALL_PERIPH(SPIx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected SPI peripheral */\r\n SPIx->CR1 |= SPI_CR1_SPE;\r\n }\r\n else\r\n {\r\n /* Disable the selected SPI peripheral */\r\n SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the specified SPI peripheral (in I2S mode).\r\n * @param SPIx: where x can be 2 or 3 to select the SPI peripheral (or I2Sxext \r\n * for full duplex mode).\r\n * @param NewState: new state of the SPIx peripheral. \r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_SPI_23_PERIPH_EXT(SPIx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected SPI peripheral (in I2S mode) */\r\n SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE;\r\n }\r\n else\r\n {\r\n /* Disable the selected SPI peripheral in I2S mode */\r\n SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Configures the data size for the selected SPI.\r\n * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r\n * @param SPI_DataSize: specifies the SPI data size.\r\n * This parameter can be one of the following values:\r\n * @arg SPI_DataSize_16b: Set data frame format to 16bit\r\n * @arg SPI_DataSize_8b: Set data frame format to 8bit\r\n * @retval None\r\n */\r\nvoid SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_SPI_ALL_PERIPH(SPIx));\r\n assert_param(IS_SPI_DATASIZE(SPI_DataSize));\r\n /* Clear DFF bit */\r\n SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;\r\n /* Set new DFF bit value */\r\n SPIx->CR1 |= SPI_DataSize;\r\n}\r\n\r\n/**\r\n * @brief Selects the data transfer direction in bidirectional mode for the specified SPI.\r\n * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r\n * @param SPI_Direction: specifies the data transfer direction in bidirectional mode. \r\n * This parameter can be one of the following values:\r\n * @arg SPI_Direction_Tx: Selects Tx transmission direction\r\n * @arg SPI_Direction_Rx: Selects Rx receive direction\r\n * @retval None\r\n */\r\nvoid SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_SPI_ALL_PERIPH(SPIx));\r\n assert_param(IS_SPI_DIRECTION(SPI_Direction));\r\n if (SPI_Direction == SPI_Direction_Tx)\r\n {\r\n /* Set the Tx only mode */\r\n SPIx->CR1 |= SPI_Direction_Tx;\r\n }\r\n else\r\n {\r\n /* Set the Rx only mode */\r\n SPIx->CR1 &= SPI_Direction_Rx;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Configures internally by software the NSS pin for the selected SPI.\r\n * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r\n * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.\r\n * This parameter can be one of the following values:\r\n * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally\r\n * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally\r\n * @retval None\r\n */\r\nvoid SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_SPI_ALL_PERIPH(SPIx));\r\n assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));\r\n if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)\r\n {\r\n /* Set NSS pin internally by software */\r\n SPIx->CR1 |= SPI_NSSInternalSoft_Set;\r\n }\r\n else\r\n {\r\n /* Reset NSS pin internally by software */\r\n SPIx->CR1 &= SPI_NSSInternalSoft_Reset;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the SS output for the selected SPI.\r\n * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r\n * @param NewState: new state of the SPIx SS output. \r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_SPI_ALL_PERIPH(SPIx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected SPI SS output */\r\n SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE;\r\n }\r\n else\r\n {\r\n /* Disable the selected SPI SS output */\r\n SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the SPIx/I2Sx DMA interface.\r\n * \r\n * @note This function can be called only after the SPI_Init() function has \r\n * been called. \r\n * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA \r\n * are not taken into consideration and are configured by hardware\r\n * respectively to the TI mode requirements. \r\n * \r\n * @param SPIx: where x can be 1, 2 or 3 \r\n * @param NewState: new state of the selected SPI TI communication mode.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_SPI_ALL_PERIPH(SPIx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the TI mode for the selected SPI peripheral */\r\n SPIx->CR2 |= SPI_CR2_FRF;\r\n }\r\n else\r\n {\r\n /* Disable the TI mode for the selected SPI peripheral */\r\n SPIx->CR2 &= (uint16_t)~SPI_CR2_FRF;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Configures the full duplex mode for the I2Sx peripheral using its\r\n * extension I2Sxext according to the specified parameters in the \r\n * I2S_InitStruct.\r\n * @param I2Sxext: where x can be 2 or 3 to select the I2S peripheral extension block.\r\n * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that\r\n * contains the configuration information for the specified I2S peripheral\r\n * extension.\r\n * \r\n * @note The structure pointed by I2S_InitStruct parameter should be the same\r\n * used for the master I2S peripheral. In this case, if the master is \r\n * configured as transmitter, the slave will be receiver and vice versa.\r\n * Or you can force a different mode by modifying the field I2S_Mode to the\r\n * value I2S_SlaveRx or I2S_SlaveTx indepedently of the master configuration. \r\n * \r\n * @note The I2S full duplex extension can be configured in slave mode only. \r\n * \r\n * @retval None\r\n */\r\nvoid I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct)\r\n{\r\n uint16_t tmpreg = 0, tmp = 0;\r\n \r\n /* Check the I2S parameters */\r\n assert_param(IS_I2S_EXT_PERIPH(I2Sxext));\r\n assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));\r\n assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));\r\n assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));\r\n assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); \r\n\r\n/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/\r\n /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */\r\n I2Sxext->I2SCFGR &= I2SCFGR_CLEAR_MASK; \r\n I2Sxext->I2SPR = 0x0002;\r\n \r\n /* Get the I2SCFGR register value */\r\n tmpreg = I2Sxext->I2SCFGR;\r\n \r\n /* Get the mode to be configured for the extended I2S */\r\n if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveTx))\r\n {\r\n tmp = I2S_Mode_SlaveRx;\r\n }\r\n else\r\n {\r\n if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterRx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveRx))\r\n {\r\n tmp = I2S_Mode_SlaveTx;\r\n }\r\n }\r\n\r\n \r\n /* Configure the I2S with the SPI_InitStruct values */\r\n tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \\\r\n (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \\\r\n (uint16_t)I2S_InitStruct->I2S_CPOL))));\r\n \r\n /* Write to SPIx I2SCFGR */ \r\n I2Sxext->I2SCFGR = tmpreg;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SPI_Group2 Data transfers functions\r\n * @brief Data transfers functions\r\n *\r\n@verbatim \r\n ===============================================================================\r\n Data transfers functions\r\n =============================================================================== \r\n\r\n This section provides a set of functions allowing to manage the SPI data transfers\r\n \r\n In reception, data are received and then stored into an internal Rx buffer while \r\n In transmission, data are first stored into an internal Tx buffer before being \r\n transmitted.\r\n\r\n The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData()\r\n function and returns the Rx buffered value. Whereas a write access to the SPI_DR \r\n can be done using SPI_I2S_SendData() function and stores the written data into \r\n Tx buffer.\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. \r\n * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 \r\n * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. \r\n * @retval The value of the received data.\r\n */\r\nuint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));\r\n \r\n /* Return the data in the DR register */\r\n return SPIx->DR;\r\n}\r\n\r\n/**\r\n * @brief Transmits a Data through the SPIx/I2Sx peripheral.\r\n * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 \r\n * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. \r\n * @param Data: Data to be transmitted.\r\n * @retval None\r\n */\r\nvoid SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));\r\n \r\n /* Write in the DR register the data to be sent */\r\n SPIx->DR = Data;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SPI_Group3 Hardware CRC Calculation functions\r\n * @brief Hardware CRC Calculation functions\r\n *\r\n@verbatim \r\n ===============================================================================\r\n Hardware CRC Calculation functions\r\n =============================================================================== \r\n\r\n This section provides a set of functions allowing to manage the SPI CRC hardware \r\n calculation\r\n\r\n SPI communication using CRC is possible through the following procedure:\r\n 1. Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, \r\n Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()\r\n function.\r\n 2. Enable the CRC calculation using the SPI_CalculateCRC() function.\r\n 3. Enable the SPI using the SPI_Cmd() function\r\n 4. Before writing the last data to the TX buffer, set the CRCNext bit using the \r\n SPI_TransmitCRC() function to indicate that after transmission of the last \r\n data, the CRC should be transmitted.\r\n 5. After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT\r\n bit is reset. The CRC is also received and compared against the SPI_RXCRCR \r\n value. \r\n If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt\r\n can be generated when the SPI_I2S_IT_ERR interrupt is enabled.\r\n\r\n@note It is advised not to read the calculated CRC values during the communication.\r\n\r\n@note When the SPI is in slave mode, be careful to enable CRC calculation only \r\n when the clock is stable, that is, when the clock is in the steady state. \r\n If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive \r\n to the SCK slave input clock as soon as CRCEN is set, and this, whatever \r\n the value of the SPE bit.\r\n\r\n@note With high bitrate frequencies, be careful when transmitting the CRC.\r\n As the number of used CPU cycles has to be as low as possible in the CRC \r\n transfer phase, it is forbidden to call software functions in the CRC \r\n transmission sequence to avoid errors in the last data and CRC reception. \r\n In fact, CRCNEXT bit has to be written before the end of the transmission/reception \r\n of the last data.\r\n\r\n@note For high bit rate frequencies, it is advised to use the DMA mode to avoid the\r\n degradation of the SPI speed performance due to CPU accesses impacting the \r\n SPI bandwidth.\r\n\r\n@note When the STM32F4xx is configured as slave and the NSS hardware mode is \r\n used, the NSS pin needs to be kept low between the data phase and the CRC \r\n phase.\r\n\r\n@note When the SPI is configured in slave mode with the CRC feature enabled, CRC\r\n calculation takes place even if a high level is applied on the NSS pin. \r\n This may happen for example in case of a multi-slave environment where the \r\n communication master addresses slaves alternately.\r\n\r\n@note Between a slave de-selection (high level on NSS) and a new slave selection \r\n (low level on NSS), the CRC value should be cleared on both master and slave\r\n sides in order to resynchronize the master and slave for their respective \r\n CRC calculation.\r\n\r\n@note To clear the CRC, follow the procedure below:\r\n 1. Disable SPI using the SPI_Cmd() function\r\n 2. Disable the CRC calculation using the SPI_CalculateCRC() function.\r\n 3. Enable the CRC calculation using the SPI_CalculateCRC() function.\r\n 4. Enable SPI using the SPI_Cmd() function.\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Enables or disables the CRC value calculation of the transferred bytes.\r\n * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r\n * @param NewState: new state of the SPIx CRC value calculation.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_SPI_ALL_PERIPH(SPIx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected SPI CRC calculation */\r\n SPIx->CR1 |= SPI_CR1_CRCEN;\r\n }\r\n else\r\n {\r\n /* Disable the selected SPI CRC calculation */\r\n SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Transmit the SPIx CRC value.\r\n * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r\n * @retval None\r\n */\r\nvoid SPI_TransmitCRC(SPI_TypeDef* SPIx)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_SPI_ALL_PERIPH(SPIx));\r\n \r\n /* Enable the selected SPI CRC transmission */\r\n SPIx->CR1 |= SPI_CR1_CRCNEXT;\r\n}\r\n\r\n/**\r\n * @brief Returns the transmit or the receive CRC register value for the specified SPI.\r\n * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r\n * @param SPI_CRC: specifies the CRC register to be read.\r\n * This parameter can be one of the following values:\r\n * @arg SPI_CRC_Tx: Selects Tx CRC register\r\n * @arg SPI_CRC_Rx: Selects Rx CRC register\r\n * @retval The selected CRC register value..\r\n */\r\nuint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)\r\n{\r\n uint16_t crcreg = 0;\r\n /* Check the parameters */\r\n assert_param(IS_SPI_ALL_PERIPH(SPIx));\r\n assert_param(IS_SPI_CRC(SPI_CRC));\r\n if (SPI_CRC != SPI_CRC_Rx)\r\n {\r\n /* Get the Tx CRC register */\r\n crcreg = SPIx->TXCRCR;\r\n }\r\n else\r\n {\r\n /* Get the Rx CRC register */\r\n crcreg = SPIx->RXCRCR;\r\n }\r\n /* Return the selected CRC register */\r\n return crcreg;\r\n}\r\n\r\n/**\r\n * @brief Returns the CRC Polynomial register value for the specified SPI.\r\n * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r\n * @retval The CRC Polynomial register value.\r\n */\r\nuint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_SPI_ALL_PERIPH(SPIx));\r\n \r\n /* Return the CRC polynomial register */\r\n return SPIx->CRCPR;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SPI_Group4 DMA transfers management functions\r\n * @brief DMA transfers management functions\r\n *\r\n@verbatim \r\n ===============================================================================\r\n DMA transfers management functions\r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Enables or disables the SPIx/I2Sx DMA interface.\r\n * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 \r\n * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. \r\n * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. \r\n * This parameter can be any combination of the following values:\r\n * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request\r\n * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request\r\n * @param NewState: new state of the selected SPI DMA transfer request.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));\r\n\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected SPI DMA requests */\r\n SPIx->CR2 |= SPI_I2S_DMAReq;\r\n }\r\n else\r\n {\r\n /* Disable the selected SPI DMA requests */\r\n SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;\r\n }\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup SPI_Group5 Interrupts and flags management functions\r\n * @brief Interrupts and flags management functions\r\n *\r\n@verbatim \r\n ===============================================================================\r\n Interrupts and flags management functions\r\n =============================================================================== \r\n\r\n This section provides a set of functions allowing to configure the SPI Interrupts \r\n sources and check or clear the flags or pending bits status.\r\n The user should identify which mode will be used in his application to manage \r\n the communication: Polling mode, Interrupt mode or DMA mode. \r\n \r\n Polling Mode\r\n =============\r\n In Polling Mode, the SPI/I2S communication can be managed by 9 flags:\r\n 1. SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register\r\n 2. SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register\r\n 3. SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI.\r\n 4. SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur \r\n 5. SPI_FLAG_MODF : to indicate if a Mode Fault error occur\r\n 6. SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur\r\n 7. I2S_FLAG_TIFRFE: to indicate a Frame Format error occurs.\r\n 8. I2S_FLAG_UDR: to indicate an Underrun error occurs.\r\n 9. I2S_FLAG_CHSIDE: to indicate Channel Side.\r\n\r\n@note Do not use the BSY flag to handle each data transmission or reception. It is\r\n better to use the TXE and RXNE flags instead.\r\n\r\n In this Mode it is advised to use the following functions:\r\n - FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r\n - void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r\n\r\n Interrupt Mode\r\n ===============\r\n In Interrupt Mode, the SPI communication can be managed by 3 interrupt sources\r\n and 7 pending bits: \r\n Pending Bits:\r\n ------------- \r\n 1. SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register\r\n 2. SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register\r\n 3. SPI_IT_CRCERR : to indicate if a CRC Calculation error occur (available in SPI mode only) \r\n 4. SPI_IT_MODF : to indicate if a Mode Fault error occur (available in SPI mode only)\r\n 5. SPI_I2S_IT_OVR : to indicate if an Overrun error occur\r\n 6. I2S_IT_UDR : to indicate an Underrun Error occurs (available in I2S mode only).\r\n 7. I2S_FLAG_TIFRFE : to indicate a Frame Format error occurs (available in TI mode only).\r\n\r\n Interrupt Source:\r\n -----------------\r\n 1. SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty \r\n interrupt. \r\n 2. SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not \r\n empty interrupt.\r\n 3. SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt.\r\n\r\n In this Mode it is advised to use the following functions:\r\n - void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);\r\n - ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);\r\n - void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);\r\n\r\n DMA Mode\r\n ========\r\n In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests:\r\n 1. SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request\r\n 2. SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request\r\n\r\n In this Mode it is advised to use the following function:\r\n - void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Enables or disables the specified SPI/I2S interrupts.\r\n * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 \r\n * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. \r\n * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. \r\n * This parameter can be one of the following values:\r\n * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask\r\n * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask\r\n * @arg SPI_I2S_IT_ERR: Error interrupt mask\r\n * @param NewState: new state of the specified SPI interrupt.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)\r\n{\r\n uint16_t itpos = 0, itmask = 0 ;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));\r\n\r\n /* Get the SPI IT index */\r\n itpos = SPI_I2S_IT >> 4;\r\n\r\n /* Set the IT mask */\r\n itmask = (uint16_t)1 << (uint16_t)itpos;\r\n\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected SPI interrupt */\r\n SPIx->CR2 |= itmask;\r\n }\r\n else\r\n {\r\n /* Disable the selected SPI interrupt */\r\n SPIx->CR2 &= (uint16_t)~itmask;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Checks whether the specified SPIx/I2Sx flag is set or not.\r\n * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 \r\n * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. \r\n * @param SPI_I2S_FLAG: specifies the SPI flag to check. \r\n * This parameter can be one of the following values:\r\n * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.\r\n * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.\r\n * @arg SPI_I2S_FLAG_BSY: Busy flag.\r\n * @arg SPI_I2S_FLAG_OVR: Overrun flag.\r\n * @arg SPI_FLAG_MODF: Mode Fault flag.\r\n * @arg SPI_FLAG_CRCERR: CRC Error flag.\r\n * @arg SPI_I2S_FLAG_TIFRFE: Format Error.\r\n * @arg I2S_FLAG_UDR: Underrun Error flag.\r\n * @arg I2S_FLAG_CHSIDE: Channel Side flag. \r\n * @retval The new state of SPI_I2S_FLAG (SET or RESET).\r\n */\r\nFlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)\r\n{\r\n FlagStatus bitstatus = RESET;\r\n /* Check the parameters */\r\n assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));\r\n assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));\r\n \r\n /* Check the status of the specified SPI flag */\r\n if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)\r\n {\r\n /* SPI_I2S_FLAG is set */\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n /* SPI_I2S_FLAG is reset */\r\n bitstatus = RESET;\r\n }\r\n /* Return the SPI_I2S_FLAG status */\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @brief Clears the SPIx CRC Error (CRCERR) flag.\r\n * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 \r\n * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. \r\n * @param SPI_I2S_FLAG: specifies the SPI flag to clear. \r\n * This function clears only CRCERR flag.\r\n * @arg SPI_FLAG_CRCERR: CRC Error flag. \r\n * \r\n * @note OVR (OverRun error) flag is cleared by software sequence: a read \r\n * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read \r\n * operation to SPI_SR register (SPI_I2S_GetFlagStatus()).\r\n * @note UDR (UnderRun error) flag is cleared by a read operation to \r\n * SPI_SR register (SPI_I2S_GetFlagStatus()). \r\n * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write \r\n * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a \r\n * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).\r\n * \r\n * @retval None\r\n */\r\nvoid SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));\r\n assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));\r\n \r\n /* Clear the selected SPI CRC Error (CRCERR) flag */\r\n SPIx->SR = (uint16_t)~SPI_I2S_FLAG;\r\n}\r\n\r\n/**\r\n * @brief Checks whether the specified SPIx/I2Sx interrupt has occurred or not.\r\n * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 \r\n * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. \r\n * @param SPI_I2S_IT: specifies the SPI interrupt source to check. \r\n * This parameter can be one of the following values:\r\n * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.\r\n * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.\r\n * @arg SPI_I2S_IT_OVR: Overrun interrupt.\r\n * @arg SPI_IT_MODF: Mode Fault interrupt.\r\n * @arg SPI_IT_CRCERR: CRC Error interrupt.\r\n * @arg I2S_IT_UDR: Underrun interrupt. \r\n * @arg SPI_I2S_IT_TIFRFE: Format Error interrupt. \r\n * @retval The new state of SPI_I2S_IT (SET or RESET).\r\n */\r\nITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)\r\n{\r\n ITStatus bitstatus = RESET;\r\n uint16_t itpos = 0, itmask = 0, enablestatus = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));\r\n assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));\r\n\r\n /* Get the SPI_I2S_IT index */\r\n itpos = 0x01 << (SPI_I2S_IT & 0x0F);\r\n\r\n /* Get the SPI_I2S_IT IT mask */\r\n itmask = SPI_I2S_IT >> 4;\r\n\r\n /* Set the IT mask */\r\n itmask = 0x01 << itmask;\r\n\r\n /* Get the SPI_I2S_IT enable bit status */\r\n enablestatus = (SPIx->CR2 & itmask) ;\r\n\r\n /* Check the status of the specified SPI interrupt */\r\n if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)\r\n {\r\n /* SPI_I2S_IT is set */\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n /* SPI_I2S_IT is reset */\r\n bitstatus = RESET;\r\n }\r\n /* Return the SPI_I2S_IT status */\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.\r\n * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 \r\n * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. \r\n * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.\r\n * This function clears only CRCERR interrupt pending bit. \r\n * @arg SPI_IT_CRCERR: CRC Error interrupt.\r\n * \r\n * @note OVR (OverRun Error) interrupt pending bit is cleared by software \r\n * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) \r\n * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).\r\n * @note UDR (UnderRun Error) interrupt pending bit is cleared by a read \r\n * operation to SPI_SR register (SPI_I2S_GetITStatus()). \r\n * @note MODF (Mode Fault) interrupt pending bit is cleared by software sequence:\r\n * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) \r\n * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable \r\n * the SPI).\r\n * @retval None\r\n */\r\nvoid SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)\r\n{\r\n uint16_t itpos = 0;\r\n /* Check the parameters */\r\n assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));\r\n assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));\r\n\r\n /* Get the SPI_I2S IT index */\r\n itpos = 0x01 << (SPI_I2S_IT & 0x0F);\r\n\r\n /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */\r\n SPIx->SR = (uint16_t)~itpos;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_syscfg.c\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file provides firmware functions to manage the SYSCFG peripheral.\r\n *\r\n * @verbatim\r\n * \r\n * ===================================================================\r\n * How to use this driver\r\n * ===================================================================\r\n * \r\n * This driver provides functions for:\r\n * \r\n * 1. Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig()\r\n * \r\n * 2. Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig()\r\n * \r\n * 3. Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig()\r\n *\r\n * @note SYSCFG APB clock must be enabled to get write access to SYSCFG registers,\r\n * using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);\r\n * \r\n * @endverbatim\r\n * \r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx_syscfg.h\"\r\n#include \"stm32f4xx_rcc.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @defgroup SYSCFG \r\n * @brief SYSCFG driver modules\r\n * @{\r\n */ \r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* ------------ RCC registers bit address in the alias region ----------- */\r\n#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)\r\n/* --- PMC Register ---*/ \r\n/* Alias word address of MII_RMII_SEL bit */ \r\n#define PMC_OFFSET (SYSCFG_OFFSET + 0x04) \r\n#define MII_RMII_SEL_BitNumber ((uint8_t)0x17) \r\n#define PMC_MII_RMII_SEL_BB (PERIPH_BB_BASE + (PMC_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) \r\n\r\n/* --- CMPCR Register ---*/ \r\n/* Alias word address of CMP_PD bit */ \r\n#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20) \r\n#define CMP_PD_BitNumber ((uint8_t)0x00) \r\n#define CMPCR_CMP_PD_BB (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4)) \r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup SYSCFG_Private_Functions\r\n * @{\r\n */ \r\n\r\n/**\r\n * @brief Deinitializes the Alternate Functions (remap and EXTI configuration)\r\n * registers to their default reset values.\r\n * @param None\r\n * @retval None\r\n */\r\nvoid SYSCFG_DeInit(void)\r\n{\r\n RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE);\r\n RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE);\r\n}\r\n\r\n/**\r\n * @brief Changes the mapping of the specified pin.\r\n * @param SYSCFG_Memory: selects the memory remapping.\r\n * This parameter can be one of the following values:\r\n * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000 \r\n * @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000\r\n * @arg SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000\r\n * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM (112kB) mapped at 0x00000000\r\n * @retval None\r\n */\r\nvoid SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap));\r\n\r\n SYSCFG->MEMRMP = SYSCFG_MemoryRemap;\r\n}\r\n\r\n/**\r\n * @brief Selects the GPIO pin used as EXTI Line.\r\n * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for\r\n * EXTI lines where x can be (A..I).\r\n * @param EXTI_PinSourcex: specifies the EXTI line to be configured.\r\n * This parameter can be EXTI_PinSourcex where x can be (0..15, except\r\n * for EXTI_PortSourceGPIOI x can be (0..11).\r\n * @retval None\r\n */\r\nvoid SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)\r\n{\r\n uint32_t tmp = 0x00;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));\r\n assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));\r\n\r\n tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));\r\n SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;\r\n SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));\r\n}\r\n\r\n/**\r\n * @brief Selects the ETHERNET media interface \r\n * @param SYSCFG_ETH_MediaInterface: specifies the Media Interface mode. \r\n * This parameter can be one of the following values: \r\n * @arg SYSCFG_ETH_MediaInterface_MII: MII mode selected\r\n * @arg SYSCFG_ETH_MediaInterface_RMII: RMII mode selected \r\n * @retval None \r\n */\r\nvoid SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface) \r\n{ \r\n assert_param(IS_SYSCFG_ETH_MEDIA_INTERFACE(SYSCFG_ETH_MediaInterface)); \r\n /* Configure MII_RMII selection bit */ \r\n *(__IO uint32_t *) PMC_MII_RMII_SEL_BB = SYSCFG_ETH_MediaInterface; \r\n}\r\n\r\n/**\r\n * @brief Enables or disables the I/O Compensation Cell.\r\n * @note The I/O compensation cell can be used only when the device supply\r\n * voltage ranges from 2.4 to 3.6 V. \r\n * @param NewState: new state of the I/O Compensation Cell.\r\n * This parameter can be one of the following values:\r\n * @arg ENABLE: I/O compensation cell enabled \r\n * @arg DISABLE: I/O compensation cell power-down mode \r\n * @retval None\r\n */\r\nvoid SYSCFG_CompensationCellCmd(FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n *(__IO uint32_t *) CMPCR_CMP_PD_BB = (uint32_t)NewState;\r\n}\r\n\r\n/**\r\n * @brief Checks whether the I/O Compensation Cell ready flag is set or not.\r\n * @param None\r\n * @retval The new state of the I/O Compensation Cell ready flag (SET or RESET)\r\n */\r\nFlagStatus SYSCFG_GetCompensationCellStatus(void)\r\n{\r\n FlagStatus bitstatus = RESET;\r\n \r\n if ((SYSCFG->CMPCR & SYSCFG_CMPCR_READY ) != (uint32_t)RESET)\r\n {\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n bitstatus = RESET;\r\n }\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ \r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_tim.c\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file provides firmware functions to manage the following \r\n * functionalities of the TIM peripheral:\r\n * - TimeBase management\r\n * - Output Compare management\r\n * - Input Capture management\r\n * - Advanced-control timers (TIM1 and TIM8) specific features \r\n * - Interrupts, DMA and flags management\r\n * - Clocks management\r\n * - Synchronization management\r\n * - Specific interface management\r\n * - Specific remapping management \r\n * \r\n * @verbatim\r\n * \r\n * ===================================================================\r\n * How to use this driver\r\n * ===================================================================\r\n * This driver provides functions to configure and program the TIM \r\n * of all STM32F4xx devices.\r\n * These functions are split in 9 groups: \r\n * \r\n * 1. TIM TimeBase management: this group includes all needed functions \r\n * to configure the TM Timebase unit:\r\n * - Set/Get Prescaler\r\n * - Set/Get Autoreload \r\n * - Counter modes configuration\r\n * - Set Clock division \r\n * - Select the One Pulse mode\r\n * - Update Request Configuration\r\n * - Update Disable Configuration\r\n * - Auto-Preload Configuration \r\n * - Enable/Disable the counter \r\n * \r\n * 2. TIM Output Compare management: this group includes all needed \r\n * functions to configure the Capture/Compare unit used in Output \r\n * compare mode: \r\n * - Configure each channel, independently, in Output Compare mode\r\n * - Select the output compare modes\r\n * - Select the Polarities of each channel\r\n * - Set/Get the Capture/Compare register values\r\n * - Select the Output Compare Fast mode \r\n * - Select the Output Compare Forced mode \r\n * - Output Compare-Preload Configuration \r\n * - Clear Output Compare Reference\r\n * - Select the OCREF Clear signal\r\n * - Enable/Disable the Capture/Compare Channels \r\n * \r\n * 3. TIM Input Capture management: this group includes all needed \r\n * functions to configure the Capture/Compare unit used in \r\n * Input Capture mode:\r\n * - Configure each channel in input capture mode\r\n * - Configure Channel1/2 in PWM Input mode\r\n * - Set the Input Capture Prescaler\r\n * - Get the Capture/Compare values \r\n * \r\n * 4. Advanced-control timers (TIM1 and TIM8) specific features\r\n * - Configures the Break input, dead time, Lock level, the OSSI,\r\n * the OSSR State and the AOE(automatic output enable)\r\n * - Enable/Disable the TIM peripheral Main Outputs\r\n * - Select the Commutation event\r\n * - Set/Reset the Capture Compare Preload Control bit\r\n * \r\n * 5. TIM interrupts, DMA and flags management\r\n * - Enable/Disable interrupt sources\r\n * - Get flags status\r\n * - Clear flags/ Pending bits\r\n * - Enable/Disable DMA requests \r\n * - Configure DMA burst mode\r\n * - Select CaptureCompare DMA request \r\n * \r\n * 6. TIM clocks management: this group includes all needed functions \r\n * to configure the clock controller unit:\r\n * - Select internal/External clock\r\n * - Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx\r\n * \r\n * 7. TIM synchronization management: this group includes all needed \r\n * functions to configure the Synchronization unit:\r\n * - Select Input Trigger \r\n * - Select Output Trigger \r\n * - Select Master Slave Mode \r\n * - ETR Configuration when used as external trigger \r\n * \r\n * 8. TIM specific interface management, this group includes all \r\n * needed functions to use the specific TIM interface:\r\n * - Encoder Interface Configuration\r\n * - Select Hall Sensor \r\n * \r\n * 9. TIM specific remapping management includes the Remapping \r\n * configuration of specific timers \r\n * \r\n * @endverbatim\r\n * \r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx_tim.h\"\r\n#include \"stm32f4xx_rcc.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @defgroup TIM \r\n * @brief TIM driver modules\r\n * @{\r\n */\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n\r\n/* ---------------------- TIM registers bit mask ------------------------ */\r\n#define SMCR_ETR_MASK ((uint16_t)0x00FF) \r\n#define CCMR_OFFSET ((uint16_t)0x0018)\r\n#define CCER_CCE_SET ((uint16_t)0x0001) \r\n#define\tCCER_CCNE_SET ((uint16_t)0x0004) \r\n#define CCMR_OC13M_MASK ((uint16_t)0xFF8F)\r\n#define CCMR_OC24M_MASK ((uint16_t)0x8FFF) \r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\nstatic void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r\n uint16_t TIM_ICFilter);\r\nstatic void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r\n uint16_t TIM_ICFilter);\r\nstatic void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r\n uint16_t TIM_ICFilter);\r\nstatic void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r\n uint16_t TIM_ICFilter);\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup TIM_Private_Functions\r\n * @{\r\n */\r\n\r\n/** @defgroup TIM_Group1 TimeBase management functions\r\n * @brief TimeBase management functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n TimeBase management functions\r\n =============================================================================== \r\n \r\n =================================================================== \r\n TIM Driver: how to use it in Timing(Time base) Mode\r\n =================================================================== \r\n To use the Timer in Timing(Time base) mode, the following steps are mandatory:\r\n \r\n 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function\r\n \r\n 2. Fill the TIM_TimeBaseInitStruct with the desired parameters.\r\n \r\n 3. Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit\r\n with the corresponding configuration\r\n \r\n 4. Enable the NVIC if you need to generate the update interrupt. \r\n \r\n 5. Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update) \r\n \r\n 6. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.\r\n \r\n Note1: All other functions can be used separately to modify, if needed,\r\n a specific feature of the Timer. \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n \r\n/**\r\n * @brief Deinitializes the TIMx peripheral registers to their default reset values.\r\n * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.\r\n * @retval None\r\n\r\n */\r\nvoid TIM_DeInit(TIM_TypeDef* TIMx)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_ALL_PERIPH(TIMx)); \r\n \r\n if (TIMx == TIM1)\r\n {\r\n RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);\r\n RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); \r\n } \r\n else if (TIMx == TIM2) \r\n { \r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);\r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);\r\n } \r\n else if (TIMx == TIM3)\r\n { \r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);\r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);\r\n } \r\n else if (TIMx == TIM4)\r\n { \r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);\r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);\r\n } \r\n else if (TIMx == TIM5)\r\n { \r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);\r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);\r\n } \r\n else if (TIMx == TIM6) \r\n { \r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);\r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);\r\n } \r\n else if (TIMx == TIM7)\r\n { \r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);\r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);\r\n } \r\n else if (TIMx == TIM8)\r\n { \r\n RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);\r\n RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); \r\n } \r\n else if (TIMx == TIM9)\r\n { \r\n RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);\r\n RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); \r\n } \r\n else if (TIMx == TIM10)\r\n { \r\n RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);\r\n RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); \r\n } \r\n else if (TIMx == TIM11) \r\n { \r\n RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);\r\n RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); \r\n } \r\n else if (TIMx == TIM12)\r\n { \r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);\r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE); \r\n } \r\n else if (TIMx == TIM13) \r\n { \r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);\r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE); \r\n } \r\n else\r\n { \r\n if (TIMx == TIM14) \r\n { \r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);\r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); \r\n } \r\n }\r\n}\r\n\r\n/**\r\n * @brief Initializes the TIMx Time Base Unit peripheral according to \r\n * the specified parameters in the TIM_TimeBaseInitStruct.\r\n * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.\r\n * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure\r\n * that contains the configuration information for the specified TIM peripheral.\r\n * @retval None\r\n */\r\nvoid TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)\r\n{\r\n uint16_t tmpcr1 = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_TIM_ALL_PERIPH(TIMx)); \r\n assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));\r\n assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));\r\n\r\n tmpcr1 = TIMx->CR1; \r\n\r\n if((TIMx == TIM1) || (TIMx == TIM8)||\r\n (TIMx == TIM2) || (TIMx == TIM3)||\r\n (TIMx == TIM4) || (TIMx == TIM5)) \r\n {\r\n /* Select the Counter Mode */\r\n tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS));\r\n tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;\r\n }\r\n \r\n if((TIMx != TIM6) && (TIMx != TIM7))\r\n {\r\n /* Set the clock division */\r\n tmpcr1 &= (uint16_t)(~TIM_CR1_CKD);\r\n tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;\r\n }\r\n\r\n TIMx->CR1 = tmpcr1;\r\n\r\n /* Set the Autoreload value */\r\n TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;\r\n \r\n /* Set the Prescaler value */\r\n TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;\r\n \r\n if ((TIMx == TIM1) || (TIMx == TIM8)) \r\n {\r\n /* Set the Repetition Counter value */\r\n TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;\r\n }\r\n\r\n /* Generate an update event to reload the Prescaler \r\n and the repetition counter(only for TIM1 and TIM8) value immediatly */\r\n TIMx->EGR = TIM_PSCReloadMode_Immediate; \r\n}\r\n\r\n/**\r\n * @brief Fills each TIM_TimeBaseInitStruct member with its default value.\r\n * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef\r\n * structure which will be initialized.\r\n * @retval None\r\n */\r\nvoid TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)\r\n{\r\n /* Set the default configuration */\r\n TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF;\r\n TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;\r\n TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;\r\n TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;\r\n TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;\r\n}\r\n\r\n/**\r\n * @brief Configures the TIMx Prescaler.\r\n * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.\r\n * @param Prescaler: specifies the Prescaler Register value\r\n * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode\r\n * This parameter can be one of the following values:\r\n * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.\r\n * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.\r\n * @retval None\r\n */\r\nvoid TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_ALL_PERIPH(TIMx));\r\n assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));\r\n /* Set the Prescaler value */\r\n TIMx->PSC = Prescaler;\r\n /* Set or reset the UG Bit */\r\n TIMx->EGR = TIM_PSCReloadMode;\r\n}\r\n\r\n/**\r\n * @brief Specifies the TIMx Counter Mode to be used.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r\n * @param TIM_CounterMode: specifies the Counter Mode to be used\r\n * This parameter can be one of the following values:\r\n * @arg TIM_CounterMode_Up: TIM Up Counting Mode\r\n * @arg TIM_CounterMode_Down: TIM Down Counting Mode\r\n * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1\r\n * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2\r\n * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3\r\n * @retval None\r\n */\r\nvoid TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)\r\n{\r\n uint16_t tmpcr1 = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r\n assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));\r\n\r\n tmpcr1 = TIMx->CR1;\r\n\r\n /* Reset the CMS and DIR Bits */\r\n tmpcr1 &= (uint16_t)~(TIM_CR1_DIR | TIM_CR1_CMS);\r\n\r\n /* Set the Counter Mode */\r\n tmpcr1 |= TIM_CounterMode;\r\n\r\n /* Write to TIMx CR1 register */\r\n TIMx->CR1 = tmpcr1;\r\n}\r\n\r\n/**\r\n * @brief Sets the TIMx Counter Register value\r\n * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.\r\n * @param Counter: specifies the Counter register new value.\r\n * @retval None\r\n */\r\nvoid TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_ALL_PERIPH(TIMx));\r\n\r\n /* Set the Counter Register value */\r\n TIMx->CNT = Counter;\r\n}\r\n\r\n/**\r\n * @brief Sets the TIMx Autoreload Register value\r\n * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.\r\n * @param Autoreload: specifies the Autoreload register new value.\r\n * @retval None\r\n */\r\nvoid TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_ALL_PERIPH(TIMx));\r\n \r\n /* Set the Autoreload Register value */\r\n TIMx->ARR = Autoreload;\r\n}\r\n\r\n/**\r\n * @brief Gets the TIMx Counter value.\r\n * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.\r\n * @retval Counter Register value\r\n */\r\nuint32_t TIM_GetCounter(TIM_TypeDef* TIMx)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_ALL_PERIPH(TIMx));\r\n\r\n /* Get the Counter Register value */\r\n return TIMx->CNT;\r\n}\r\n\r\n/**\r\n * @brief Gets the TIMx Prescaler value.\r\n * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.\r\n * @retval Prescaler Register value.\r\n */\r\nuint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_ALL_PERIPH(TIMx));\r\n\r\n /* Get the Prescaler Register value */\r\n return TIMx->PSC;\r\n}\r\n\r\n/**\r\n * @brief Enables or Disables the TIMx Update event.\r\n * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.\r\n * @param NewState: new state of the TIMx UDIS bit\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_ALL_PERIPH(TIMx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n if (NewState != DISABLE)\r\n {\r\n /* Set the Update Disable Bit */\r\n TIMx->CR1 |= TIM_CR1_UDIS;\r\n }\r\n else\r\n {\r\n /* Reset the Update Disable Bit */\r\n TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Configures the TIMx Update Request Interrupt source.\r\n * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.\r\n * @param TIM_UpdateSource: specifies the Update source.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_UpdateSource_Global: Source of update is the counter\r\n * overflow/underflow or the setting of UG bit, or an update\r\n * generation through the slave mode controller.\r\n * @arg TIM_UpdateSource_Regular: Source of update is counter overflow/underflow.\r\n * @retval None\r\n */\r\nvoid TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_ALL_PERIPH(TIMx));\r\n assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));\r\n\r\n if (TIM_UpdateSource != TIM_UpdateSource_Global)\r\n {\r\n /* Set the URS Bit */\r\n TIMx->CR1 |= TIM_CR1_URS;\r\n }\r\n else\r\n {\r\n /* Reset the URS Bit */\r\n TIMx->CR1 &= (uint16_t)~TIM_CR1_URS;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables or disables TIMx peripheral Preload register on ARR.\r\n * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.\r\n * @param NewState: new state of the TIMx peripheral Preload register\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_ALL_PERIPH(TIMx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n if (NewState != DISABLE)\r\n {\r\n /* Set the ARR Preload Bit */\r\n TIMx->CR1 |= TIM_CR1_ARPE;\r\n }\r\n else\r\n {\r\n /* Reset the ARR Preload Bit */\r\n TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Selects the TIMx's One Pulse Mode.\r\n * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.\r\n * @param TIM_OPMode: specifies the OPM Mode to be used.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_OPMode_Single\r\n * @arg TIM_OPMode_Repetitive\r\n * @retval None\r\n */\r\nvoid TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_ALL_PERIPH(TIMx));\r\n assert_param(IS_TIM_OPM_MODE(TIM_OPMode));\r\n\r\n /* Reset the OPM Bit */\r\n TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM;\r\n\r\n /* Configure the OPM Mode */\r\n TIMx->CR1 |= TIM_OPMode;\r\n}\r\n\r\n/**\r\n * @brief Sets the TIMx Clock Division value.\r\n * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.\r\n * @param TIM_CKD: specifies the clock division value.\r\n * This parameter can be one of the following value:\r\n * @arg TIM_CKD_DIV1: TDTS = Tck_tim\r\n * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim\r\n * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim\r\n * @retval None\r\n */\r\nvoid TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r\n assert_param(IS_TIM_CKD_DIV(TIM_CKD));\r\n\r\n /* Reset the CKD Bits */\r\n TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD);\r\n\r\n /* Set the CKD value */\r\n TIMx->CR1 |= TIM_CKD;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the specified TIM peripheral.\r\n * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral.\r\n * @param NewState: new state of the TIMx peripheral.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_ALL_PERIPH(TIMx)); \r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the TIM Counter */\r\n TIMx->CR1 |= TIM_CR1_CEN;\r\n }\r\n else\r\n {\r\n /* Disable the TIM Counter */\r\n TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN;\r\n }\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup TIM_Group2 Output Compare management functions\r\n * @brief Output Compare management functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Output Compare management functions\r\n =============================================================================== \r\n \r\n =================================================================== \r\n TIM Driver: how to use it in Output Compare Mode\r\n =================================================================== \r\n To use the Timer in Output Compare mode, the following steps are mandatory:\r\n \r\n 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function\r\n \r\n 2. Configure the TIM pins by configuring the corresponding GPIO pins\r\n \r\n 2. Configure the Time base unit as described in the first part of this driver, \r\n if needed, else the Timer will run with the default configuration:\r\n - Autoreload value = 0xFFFF\r\n - Prescaler value = 0x0000\r\n - Counter mode = Up counting\r\n - Clock Division = TIM_CKD_DIV1\r\n \r\n 3. Fill the TIM_OCInitStruct with the desired parameters including:\r\n - The TIM Output Compare mode: TIM_OCMode\r\n - TIM Output State: TIM_OutputState\r\n - TIM Pulse value: TIM_Pulse\r\n - TIM Output Compare Polarity : TIM_OCPolarity\r\n \r\n 4. Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired channel with the \r\n corresponding configuration\r\n \r\n 5. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.\r\n \r\n Note1: All other functions can be used separately to modify, if needed,\r\n a specific feature of the Timer. \r\n \r\n Note2: In case of PWM mode, this function is mandatory:\r\n TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE); \r\n \r\n Note3: If the corresponding interrupt or DMA request are needed, the user should:\r\n 1. Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). \r\n 2. Enable the corresponding interrupt (or DMA request) using the function \r\n TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Initializes the TIMx Channel1 according to the specified parameters in\r\n * the TIM_OCInitStruct.\r\n * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.\r\n * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains\r\n * the configuration information for the specified TIM peripheral.\r\n * @retval None\r\n */\r\nvoid TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r\n{\r\n uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST1_PERIPH(TIMx)); \r\n assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r\n assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r\n assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r\n\r\n /* Disable the Channel 1: Reset the CC1E Bit */\r\n TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E;\r\n \r\n /* Get the TIMx CCER register value */\r\n tmpccer = TIMx->CCER;\r\n /* Get the TIMx CR2 register value */\r\n tmpcr2 = TIMx->CR2;\r\n \r\n /* Get the TIMx CCMR1 register value */\r\n tmpccmrx = TIMx->CCMR1;\r\n \r\n /* Reset the Output Compare Mode Bits */\r\n tmpccmrx &= (uint16_t)~TIM_CCMR1_OC1M;\r\n tmpccmrx &= (uint16_t)~TIM_CCMR1_CC1S;\r\n /* Select the Output Compare Mode */\r\n tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;\r\n \r\n /* Reset the Output Polarity level */\r\n tmpccer &= (uint16_t)~TIM_CCER_CC1P;\r\n /* Set the Output Compare Polarity */\r\n tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;\r\n \r\n /* Set the Output State */\r\n tmpccer |= TIM_OCInitStruct->TIM_OutputState;\r\n \r\n if((TIMx == TIM1) || (TIMx == TIM8))\r\n {\r\n assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));\r\n assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));\r\n assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));\r\n assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));\r\n \r\n /* Reset the Output N Polarity level */\r\n tmpccer &= (uint16_t)~TIM_CCER_CC1NP;\r\n /* Set the Output N Polarity */\r\n tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;\r\n /* Reset the Output N State */\r\n tmpccer &= (uint16_t)~TIM_CCER_CC1NE;\r\n \r\n /* Set the Output N State */\r\n tmpccer |= TIM_OCInitStruct->TIM_OutputNState;\r\n /* Reset the Output Compare and Output Compare N IDLE State */\r\n tmpcr2 &= (uint16_t)~TIM_CR2_OIS1;\r\n tmpcr2 &= (uint16_t)~TIM_CR2_OIS1N;\r\n /* Set the Output Idle state */\r\n tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;\r\n /* Set the Output N Idle state */\r\n tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;\r\n }\r\n /* Write to TIMx CR2 */\r\n TIMx->CR2 = tmpcr2;\r\n \r\n /* Write to TIMx CCMR1 */\r\n TIMx->CCMR1 = tmpccmrx;\r\n \r\n /* Set the Capture Compare Register value */\r\n TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;\r\n \r\n /* Write to TIMx CCER */\r\n TIMx->CCER = tmpccer;\r\n}\r\n\r\n/**\r\n * @brief Initializes the TIMx Channel2 according to the specified parameters \r\n * in the TIM_OCInitStruct.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM \r\n * peripheral.\r\n * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains\r\n * the configuration information for the specified TIM peripheral.\r\n * @retval None\r\n */\r\nvoid TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r\n{\r\n uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST2_PERIPH(TIMx)); \r\n assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r\n assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r\n assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r\n\r\n /* Disable the Channel 2: Reset the CC2E Bit */\r\n TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E;\r\n \r\n /* Get the TIMx CCER register value */ \r\n tmpccer = TIMx->CCER;\r\n /* Get the TIMx CR2 register value */\r\n tmpcr2 = TIMx->CR2;\r\n \r\n /* Get the TIMx CCMR1 register value */\r\n tmpccmrx = TIMx->CCMR1;\r\n \r\n /* Reset the Output Compare mode and Capture/Compare selection Bits */\r\n tmpccmrx &= (uint16_t)~TIM_CCMR1_OC2M;\r\n tmpccmrx &= (uint16_t)~TIM_CCMR1_CC2S;\r\n \r\n /* Select the Output Compare Mode */\r\n tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);\r\n \r\n /* Reset the Output Polarity level */\r\n tmpccer &= (uint16_t)~TIM_CCER_CC2P;\r\n /* Set the Output Compare Polarity */\r\n tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);\r\n \r\n /* Set the Output State */\r\n tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);\r\n \r\n if((TIMx == TIM1) || (TIMx == TIM8))\r\n {\r\n assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));\r\n assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));\r\n assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));\r\n assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));\r\n \r\n /* Reset the Output N Polarity level */\r\n tmpccer &= (uint16_t)~TIM_CCER_CC2NP;\r\n /* Set the Output N Polarity */\r\n tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);\r\n /* Reset the Output N State */\r\n tmpccer &= (uint16_t)~TIM_CCER_CC2NE;\r\n \r\n /* Set the Output N State */\r\n tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);\r\n /* Reset the Output Compare and Output Compare N IDLE State */\r\n tmpcr2 &= (uint16_t)~TIM_CR2_OIS2;\r\n tmpcr2 &= (uint16_t)~TIM_CR2_OIS2N;\r\n /* Set the Output Idle state */\r\n tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);\r\n /* Set the Output N Idle state */\r\n tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);\r\n }\r\n /* Write to TIMx CR2 */\r\n TIMx->CR2 = tmpcr2;\r\n \r\n /* Write to TIMx CCMR1 */\r\n TIMx->CCMR1 = tmpccmrx;\r\n \r\n /* Set the Capture Compare Register value */\r\n TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;\r\n \r\n /* Write to TIMx CCER */\r\n TIMx->CCER = tmpccer;\r\n}\r\n\r\n/**\r\n * @brief Initializes the TIMx Channel3 according to the specified parameters\r\n * in the TIM_OCInitStruct.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r\n * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains\r\n * the configuration information for the specified TIM peripheral.\r\n * @retval None\r\n */\r\nvoid TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r\n{\r\n uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST3_PERIPH(TIMx)); \r\n assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r\n assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r\n assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r\n\r\n /* Disable the Channel 3: Reset the CC2E Bit */\r\n TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E;\r\n \r\n /* Get the TIMx CCER register value */\r\n tmpccer = TIMx->CCER;\r\n /* Get the TIMx CR2 register value */\r\n tmpcr2 = TIMx->CR2;\r\n \r\n /* Get the TIMx CCMR2 register value */\r\n tmpccmrx = TIMx->CCMR2;\r\n \r\n /* Reset the Output Compare mode and Capture/Compare selection Bits */\r\n tmpccmrx &= (uint16_t)~TIM_CCMR2_OC3M;\r\n tmpccmrx &= (uint16_t)~TIM_CCMR2_CC3S; \r\n /* Select the Output Compare Mode */\r\n tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;\r\n \r\n /* Reset the Output Polarity level */\r\n tmpccer &= (uint16_t)~TIM_CCER_CC3P;\r\n /* Set the Output Compare Polarity */\r\n tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);\r\n \r\n /* Set the Output State */\r\n tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);\r\n \r\n if((TIMx == TIM1) || (TIMx == TIM8))\r\n {\r\n assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));\r\n assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));\r\n assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));\r\n assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));\r\n \r\n /* Reset the Output N Polarity level */\r\n tmpccer &= (uint16_t)~TIM_CCER_CC3NP;\r\n /* Set the Output N Polarity */\r\n tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);\r\n /* Reset the Output N State */\r\n tmpccer &= (uint16_t)~TIM_CCER_CC3NE;\r\n \r\n /* Set the Output N State */\r\n tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);\r\n /* Reset the Output Compare and Output Compare N IDLE State */\r\n tmpcr2 &= (uint16_t)~TIM_CR2_OIS3;\r\n tmpcr2 &= (uint16_t)~TIM_CR2_OIS3N;\r\n /* Set the Output Idle state */\r\n tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);\r\n /* Set the Output N Idle state */\r\n tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);\r\n }\r\n /* Write to TIMx CR2 */\r\n TIMx->CR2 = tmpcr2;\r\n \r\n /* Write to TIMx CCMR2 */\r\n TIMx->CCMR2 = tmpccmrx;\r\n \r\n /* Set the Capture Compare Register value */\r\n TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;\r\n \r\n /* Write to TIMx CCER */\r\n TIMx->CCER = tmpccer;\r\n}\r\n\r\n/**\r\n * @brief Initializes the TIMx Channel4 according to the specified parameters\r\n * in the TIM_OCInitStruct.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r\n * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains\r\n * the configuration information for the specified TIM peripheral.\r\n * @retval None\r\n */\r\nvoid TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r\n{\r\n uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST3_PERIPH(TIMx)); \r\n assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r\n assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r\n assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r\n\r\n /* Disable the Channel 4: Reset the CC4E Bit */\r\n TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E;\r\n \r\n /* Get the TIMx CCER register value */\r\n tmpccer = TIMx->CCER;\r\n /* Get the TIMx CR2 register value */\r\n tmpcr2 = TIMx->CR2;\r\n \r\n /* Get the TIMx CCMR2 register value */\r\n tmpccmrx = TIMx->CCMR2;\r\n \r\n /* Reset the Output Compare mode and Capture/Compare selection Bits */\r\n tmpccmrx &= (uint16_t)~TIM_CCMR2_OC4M;\r\n tmpccmrx &= (uint16_t)~TIM_CCMR2_CC4S;\r\n \r\n /* Select the Output Compare Mode */\r\n tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);\r\n \r\n /* Reset the Output Polarity level */\r\n tmpccer &= (uint16_t)~TIM_CCER_CC4P;\r\n /* Set the Output Compare Polarity */\r\n tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);\r\n \r\n /* Set the Output State */\r\n tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);\r\n \r\n if((TIMx == TIM1) || (TIMx == TIM8))\r\n {\r\n assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));\r\n /* Reset the Output Compare IDLE State */\r\n tmpcr2 &=(uint16_t) ~TIM_CR2_OIS4;\r\n /* Set the Output Idle state */\r\n tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);\r\n }\r\n /* Write to TIMx CR2 */\r\n TIMx->CR2 = tmpcr2;\r\n \r\n /* Write to TIMx CCMR2 */ \r\n TIMx->CCMR2 = tmpccmrx;\r\n \r\n /* Set the Capture Compare Register value */\r\n TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;\r\n \r\n /* Write to TIMx CCER */\r\n TIMx->CCER = tmpccer;\r\n}\r\n\r\n/**\r\n * @brief Fills each TIM_OCInitStruct member with its default value.\r\n * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will\r\n * be initialized.\r\n * @retval None\r\n */\r\nvoid TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)\r\n{\r\n /* Set the default configuration */\r\n TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;\r\n TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;\r\n TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;\r\n TIM_OCInitStruct->TIM_Pulse = 0x00000000;\r\n TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;\r\n TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;\r\n TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;\r\n TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;\r\n}\r\n\r\n/**\r\n * @brief Selects the TIM Output Compare Mode.\r\n * @note This function disables the selected channel before changing the Output\r\n * Compare Mode. If needed, user has to enable this channel using\r\n * TIM_CCxCmd() and TIM_CCxNCmd() functions.\r\n * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.\r\n * @param TIM_Channel: specifies the TIM Channel\r\n * This parameter can be one of the following values:\r\n * @arg TIM_Channel_1: TIM Channel 1\r\n * @arg TIM_Channel_2: TIM Channel 2\r\n * @arg TIM_Channel_3: TIM Channel 3\r\n * @arg TIM_Channel_4: TIM Channel 4\r\n * @param TIM_OCMode: specifies the TIM Output Compare Mode.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_OCMode_Timing\r\n * @arg TIM_OCMode_Active\r\n * @arg TIM_OCMode_Toggle\r\n * @arg TIM_OCMode_PWM1\r\n * @arg TIM_OCMode_PWM2\r\n * @arg TIM_ForcedAction_Active\r\n * @arg TIM_ForcedAction_InActive\r\n * @retval None\r\n */\r\nvoid TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)\r\n{\r\n uint32_t tmp = 0;\r\n uint16_t tmp1 = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r\n assert_param(IS_TIM_CHANNEL(TIM_Channel));\r\n assert_param(IS_TIM_OCM(TIM_OCMode));\r\n\r\n tmp = (uint32_t) TIMx;\r\n tmp += CCMR_OFFSET;\r\n\r\n tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;\r\n\r\n /* Disable the Channel: Reset the CCxE Bit */\r\n TIMx->CCER &= (uint16_t) ~tmp1;\r\n\r\n if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))\r\n {\r\n tmp += (TIM_Channel>>1);\r\n\r\n /* Reset the OCxM bits in the CCMRx register */\r\n *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK;\r\n \r\n /* Configure the OCxM bits in the CCMRx register */\r\n *(__IO uint32_t *) tmp |= TIM_OCMode;\r\n }\r\n else\r\n {\r\n tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;\r\n\r\n /* Reset the OCxM bits in the CCMRx register */\r\n *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK;\r\n \r\n /* Configure the OCxM bits in the CCMRx register */\r\n *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Sets the TIMx Capture Compare1 Register value\r\n * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.\r\n * @param Compare1: specifies the Capture Compare1 register new value.\r\n * @retval None\r\n */\r\nvoid TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r\n\r\n /* Set the Capture Compare1 Register value */\r\n TIMx->CCR1 = Compare1;\r\n}\r\n\r\n/**\r\n * @brief Sets the TIMx Capture Compare2 Register value\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM \r\n * peripheral.\r\n * @param Compare2: specifies the Capture Compare2 register new value.\r\n * @retval None\r\n */\r\nvoid TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r\n\r\n /* Set the Capture Compare2 Register value */\r\n TIMx->CCR2 = Compare2;\r\n}\r\n\r\n/**\r\n * @brief Sets the TIMx Capture Compare3 Register value\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r\n * @param Compare3: specifies the Capture Compare3 register new value.\r\n * @retval None\r\n */\r\nvoid TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r\n\r\n /* Set the Capture Compare3 Register value */\r\n TIMx->CCR3 = Compare3;\r\n}\r\n\r\n/**\r\n * @brief Sets the TIMx Capture Compare4 Register value\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r\n * @param Compare4: specifies the Capture Compare4 register new value.\r\n * @retval None\r\n */\r\nvoid TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r\n\r\n /* Set the Capture Compare4 Register value */\r\n TIMx->CCR4 = Compare4;\r\n}\r\n\r\n/**\r\n * @brief Forces the TIMx output 1 waveform to active or inactive level.\r\n * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.\r\n * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_ForcedAction_Active: Force active level on OC1REF\r\n * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.\r\n * @retval None\r\n */\r\nvoid TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r\n{\r\n uint16_t tmpccmr1 = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r\n assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r\n tmpccmr1 = TIMx->CCMR1;\r\n\r\n /* Reset the OC1M Bits */\r\n tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1M;\r\n\r\n /* Configure The Forced output Mode */\r\n tmpccmr1 |= TIM_ForcedAction;\r\n\r\n /* Write to TIMx CCMR1 register */\r\n TIMx->CCMR1 = tmpccmr1;\r\n}\r\n\r\n/**\r\n * @brief Forces the TIMx output 2 waveform to active or inactive level.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM \r\n * peripheral.\r\n * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_ForcedAction_Active: Force active level on OC2REF\r\n * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.\r\n * @retval None\r\n */\r\nvoid TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r\n{\r\n uint16_t tmpccmr1 = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r\n assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r\n tmpccmr1 = TIMx->CCMR1;\r\n\r\n /* Reset the OC2M Bits */\r\n tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2M;\r\n\r\n /* Configure The Forced output Mode */\r\n tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);\r\n\r\n /* Write to TIMx CCMR1 register */\r\n TIMx->CCMR1 = tmpccmr1;\r\n}\r\n\r\n/**\r\n * @brief Forces the TIMx output 3 waveform to active or inactive level.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r\n * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_ForcedAction_Active: Force active level on OC3REF\r\n * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.\r\n * @retval None\r\n */\r\nvoid TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r\n{\r\n uint16_t tmpccmr2 = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r\n assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r\n\r\n tmpccmr2 = TIMx->CCMR2;\r\n\r\n /* Reset the OC1M Bits */\r\n tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3M;\r\n\r\n /* Configure The Forced output Mode */\r\n tmpccmr2 |= TIM_ForcedAction;\r\n\r\n /* Write to TIMx CCMR2 register */\r\n TIMx->CCMR2 = tmpccmr2;\r\n}\r\n\r\n/**\r\n * @brief Forces the TIMx output 4 waveform to active or inactive level.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r\n * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_ForcedAction_Active: Force active level on OC4REF\r\n * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.\r\n * @retval None\r\n */\r\nvoid TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r\n{\r\n uint16_t tmpccmr2 = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r\n assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r\n tmpccmr2 = TIMx->CCMR2;\r\n\r\n /* Reset the OC2M Bits */\r\n tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4M;\r\n\r\n /* Configure The Forced output Mode */\r\n tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);\r\n\r\n /* Write to TIMx CCMR2 register */\r\n TIMx->CCMR2 = tmpccmr2;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the TIMx peripheral Preload register on CCR1.\r\n * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.\r\n * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r\n * This parameter can be one of the following values:\r\n * @arg TIM_OCPreload_Enable\r\n * @arg TIM_OCPreload_Disable\r\n * @retval None\r\n */\r\nvoid TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r\n{\r\n uint16_t tmpccmr1 = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r\n assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r\n\r\n tmpccmr1 = TIMx->CCMR1;\r\n\r\n /* Reset the OC1PE Bit */\r\n tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC1PE);\r\n\r\n /* Enable or Disable the Output Compare Preload feature */\r\n tmpccmr1 |= TIM_OCPreload;\r\n\r\n /* Write to TIMx CCMR1 register */\r\n TIMx->CCMR1 = tmpccmr1;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the TIMx peripheral Preload register on CCR2.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM \r\n * peripheral.\r\n * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r\n * This parameter can be one of the following values:\r\n * @arg TIM_OCPreload_Enable\r\n * @arg TIM_OCPreload_Disable\r\n * @retval None\r\n */\r\nvoid TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r\n{\r\n uint16_t tmpccmr1 = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r\n assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r\n\r\n tmpccmr1 = TIMx->CCMR1;\r\n\r\n /* Reset the OC2PE Bit */\r\n tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2PE);\r\n\r\n /* Enable or Disable the Output Compare Preload feature */\r\n tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);\r\n\r\n /* Write to TIMx CCMR1 register */\r\n TIMx->CCMR1 = tmpccmr1;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the TIMx peripheral Preload register on CCR3.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r\n * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r\n * This parameter can be one of the following values:\r\n * @arg TIM_OCPreload_Enable\r\n * @arg TIM_OCPreload_Disable\r\n * @retval None\r\n */\r\nvoid TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r\n{\r\n uint16_t tmpccmr2 = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r\n assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r\n\r\n tmpccmr2 = TIMx->CCMR2;\r\n\r\n /* Reset the OC3PE Bit */\r\n tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC3PE);\r\n\r\n /* Enable or Disable the Output Compare Preload feature */\r\n tmpccmr2 |= TIM_OCPreload;\r\n\r\n /* Write to TIMx CCMR2 register */\r\n TIMx->CCMR2 = tmpccmr2;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the TIMx peripheral Preload register on CCR4.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r\n * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r\n * This parameter can be one of the following values:\r\n * @arg TIM_OCPreload_Enable\r\n * @arg TIM_OCPreload_Disable\r\n * @retval None\r\n */\r\nvoid TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r\n{\r\n uint16_t tmpccmr2 = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r\n assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r\n\r\n tmpccmr2 = TIMx->CCMR2;\r\n\r\n /* Reset the OC4PE Bit */\r\n tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4PE);\r\n\r\n /* Enable or Disable the Output Compare Preload feature */\r\n tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);\r\n\r\n /* Write to TIMx CCMR2 register */\r\n TIMx->CCMR2 = tmpccmr2;\r\n}\r\n\r\n/**\r\n * @brief Configures the TIMx Output Compare 1 Fast feature.\r\n * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.\r\n * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_OCFast_Enable: TIM output compare fast enable\r\n * @arg TIM_OCFast_Disable: TIM output compare fast disable\r\n * @retval None\r\n */\r\nvoid TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r\n{\r\n uint16_t tmpccmr1 = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r\n assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r\n\r\n /* Get the TIMx CCMR1 register value */\r\n tmpccmr1 = TIMx->CCMR1;\r\n\r\n /* Reset the OC1FE Bit */\r\n tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1FE;\r\n\r\n /* Enable or Disable the Output Compare Fast Bit */\r\n tmpccmr1 |= TIM_OCFast;\r\n\r\n /* Write to TIMx CCMR1 */\r\n TIMx->CCMR1 = tmpccmr1;\r\n}\r\n\r\n/**\r\n * @brief Configures the TIMx Output Compare 2 Fast feature.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM \r\n * peripheral.\r\n * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_OCFast_Enable: TIM output compare fast enable\r\n * @arg TIM_OCFast_Disable: TIM output compare fast disable\r\n * @retval None\r\n */\r\nvoid TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r\n{\r\n uint16_t tmpccmr1 = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r\n assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r\n\r\n /* Get the TIMx CCMR1 register value */\r\n tmpccmr1 = TIMx->CCMR1;\r\n\r\n /* Reset the OC2FE Bit */\r\n tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2FE);\r\n\r\n /* Enable or Disable the Output Compare Fast Bit */\r\n tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);\r\n\r\n /* Write to TIMx CCMR1 */\r\n TIMx->CCMR1 = tmpccmr1;\r\n}\r\n\r\n/**\r\n * @brief Configures the TIMx Output Compare 3 Fast feature.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r\n * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_OCFast_Enable: TIM output compare fast enable\r\n * @arg TIM_OCFast_Disable: TIM output compare fast disable\r\n * @retval None\r\n */\r\nvoid TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r\n{\r\n uint16_t tmpccmr2 = 0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r\n assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r\n\r\n /* Get the TIMx CCMR2 register value */\r\n tmpccmr2 = TIMx->CCMR2;\r\n\r\n /* Reset the OC3FE Bit */\r\n tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3FE;\r\n\r\n /* Enable or Disable the Output Compare Fast Bit */\r\n tmpccmr2 |= TIM_OCFast;\r\n\r\n /* Write to TIMx CCMR2 */\r\n TIMx->CCMR2 = tmpccmr2;\r\n}\r\n\r\n/**\r\n * @brief Configures the TIMx Output Compare 4 Fast feature.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r\n * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_OCFast_Enable: TIM output compare fast enable\r\n * @arg TIM_OCFast_Disable: TIM output compare fast disable\r\n * @retval None\r\n */\r\nvoid TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r\n{\r\n uint16_t tmpccmr2 = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r\n assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r\n\r\n /* Get the TIMx CCMR2 register value */\r\n tmpccmr2 = TIMx->CCMR2;\r\n\r\n /* Reset the OC4FE Bit */\r\n tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4FE);\r\n\r\n /* Enable or Disable the Output Compare Fast Bit */\r\n tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);\r\n\r\n /* Write to TIMx CCMR2 */\r\n TIMx->CCMR2 = tmpccmr2;\r\n}\r\n\r\n/**\r\n * @brief Clears or safeguards the OCREF1 signal on an external event\r\n * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.\r\n * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_OCClear_Enable: TIM Output clear enable\r\n * @arg TIM_OCClear_Disable: TIM Output clear disable\r\n * @retval None\r\n */\r\nvoid TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r\n{\r\n uint16_t tmpccmr1 = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r\n assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r\n\r\n tmpccmr1 = TIMx->CCMR1;\r\n\r\n /* Reset the OC1CE Bit */\r\n tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1CE;\r\n\r\n /* Enable or Disable the Output Compare Clear Bit */\r\n tmpccmr1 |= TIM_OCClear;\r\n\r\n /* Write to TIMx CCMR1 register */\r\n TIMx->CCMR1 = tmpccmr1;\r\n}\r\n\r\n/**\r\n * @brief Clears or safeguards the OCREF2 signal on an external event\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM \r\n * peripheral.\r\n * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_OCClear_Enable: TIM Output clear enable\r\n * @arg TIM_OCClear_Disable: TIM Output clear disable\r\n * @retval None\r\n */\r\nvoid TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r\n{\r\n uint16_t tmpccmr1 = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r\n assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r\n\r\n tmpccmr1 = TIMx->CCMR1;\r\n\r\n /* Reset the OC2CE Bit */\r\n tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2CE;\r\n\r\n /* Enable or Disable the Output Compare Clear Bit */\r\n tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);\r\n\r\n /* Write to TIMx CCMR1 register */\r\n TIMx->CCMR1 = tmpccmr1;\r\n}\r\n\r\n/**\r\n * @brief Clears or safeguards the OCREF3 signal on an external event\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r\n * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_OCClear_Enable: TIM Output clear enable\r\n * @arg TIM_OCClear_Disable: TIM Output clear disable\r\n * @retval None\r\n */\r\nvoid TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r\n{\r\n uint16_t tmpccmr2 = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r\n assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r\n\r\n tmpccmr2 = TIMx->CCMR2;\r\n\r\n /* Reset the OC3CE Bit */\r\n tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3CE;\r\n\r\n /* Enable or Disable the Output Compare Clear Bit */\r\n tmpccmr2 |= TIM_OCClear;\r\n\r\n /* Write to TIMx CCMR2 register */\r\n TIMx->CCMR2 = tmpccmr2;\r\n}\r\n\r\n/**\r\n * @brief Clears or safeguards the OCREF4 signal on an external event\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r\n * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_OCClear_Enable: TIM Output clear enable\r\n * @arg TIM_OCClear_Disable: TIM Output clear disable\r\n * @retval None\r\n */\r\nvoid TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r\n{\r\n uint16_t tmpccmr2 = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r\n assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r\n\r\n tmpccmr2 = TIMx->CCMR2;\r\n\r\n /* Reset the OC4CE Bit */\r\n tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4CE;\r\n\r\n /* Enable or Disable the Output Compare Clear Bit */\r\n tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);\r\n\r\n /* Write to TIMx CCMR2 register */\r\n TIMx->CCMR2 = tmpccmr2;\r\n}\r\n\r\n/**\r\n * @brief Configures the TIMx channel 1 polarity.\r\n * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.\r\n * @param TIM_OCPolarity: specifies the OC1 Polarity\r\n * This parameter can be one of the following values:\r\n * @arg TIM_OCPolarity_High: Output Compare active high\r\n * @arg TIM_OCPolarity_Low: Output Compare active low\r\n * @retval None\r\n */\r\nvoid TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r\n{\r\n uint16_t tmpccer = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r\n assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r\n\r\n tmpccer = TIMx->CCER;\r\n\r\n /* Set or Reset the CC1P Bit */\r\n tmpccer &= (uint16_t)(~TIM_CCER_CC1P);\r\n tmpccer |= TIM_OCPolarity;\r\n\r\n /* Write to TIMx CCER register */\r\n TIMx->CCER = tmpccer;\r\n}\r\n\r\n/**\r\n * @brief Configures the TIMx Channel 1N polarity.\r\n * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.\r\n * @param TIM_OCNPolarity: specifies the OC1N Polarity\r\n * This parameter can be one of the following values:\r\n * @arg TIM_OCNPolarity_High: Output Compare active high\r\n * @arg TIM_OCNPolarity_Low: Output Compare active low\r\n * @retval None\r\n */\r\nvoid TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)\r\n{\r\n uint16_t tmpccer = 0;\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r\n assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));\r\n \r\n tmpccer = TIMx->CCER;\r\n\r\n /* Set or Reset the CC1NP Bit */\r\n tmpccer &= (uint16_t)~TIM_CCER_CC1NP;\r\n tmpccer |= TIM_OCNPolarity;\r\n\r\n /* Write to TIMx CCER register */\r\n TIMx->CCER = tmpccer;\r\n}\r\n\r\n/**\r\n * @brief Configures the TIMx channel 2 polarity.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM \r\n * peripheral.\r\n * @param TIM_OCPolarity: specifies the OC2 Polarity\r\n * This parameter can be one of the following values:\r\n * @arg TIM_OCPolarity_High: Output Compare active high\r\n * @arg TIM_OCPolarity_Low: Output Compare active low\r\n * @retval None\r\n */\r\nvoid TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r\n{\r\n uint16_t tmpccer = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r\n assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r\n\r\n tmpccer = TIMx->CCER;\r\n\r\n /* Set or Reset the CC2P Bit */\r\n tmpccer &= (uint16_t)(~TIM_CCER_CC2P);\r\n tmpccer |= (uint16_t)(TIM_OCPolarity << 4);\r\n\r\n /* Write to TIMx CCER register */\r\n TIMx->CCER = tmpccer;\r\n}\r\n\r\n/**\r\n * @brief Configures the TIMx Channel 2N polarity.\r\n * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.\r\n * @param TIM_OCNPolarity: specifies the OC2N Polarity\r\n * This parameter can be one of the following values:\r\n * @arg TIM_OCNPolarity_High: Output Compare active high\r\n * @arg TIM_OCNPolarity_Low: Output Compare active low\r\n * @retval None\r\n */\r\nvoid TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)\r\n{\r\n uint16_t tmpccer = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r\n assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));\r\n \r\n tmpccer = TIMx->CCER;\r\n\r\n /* Set or Reset the CC2NP Bit */\r\n tmpccer &= (uint16_t)~TIM_CCER_CC2NP;\r\n tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);\r\n\r\n /* Write to TIMx CCER register */\r\n TIMx->CCER = tmpccer;\r\n}\r\n\r\n/**\r\n * @brief Configures the TIMx channel 3 polarity.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r\n * @param TIM_OCPolarity: specifies the OC3 Polarity\r\n * This parameter can be one of the following values:\r\n * @arg TIM_OCPolarity_High: Output Compare active high\r\n * @arg TIM_OCPolarity_Low: Output Compare active low\r\n * @retval None\r\n */\r\nvoid TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r\n{\r\n uint16_t tmpccer = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r\n assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r\n\r\n tmpccer = TIMx->CCER;\r\n\r\n /* Set or Reset the CC3P Bit */\r\n tmpccer &= (uint16_t)~TIM_CCER_CC3P;\r\n tmpccer |= (uint16_t)(TIM_OCPolarity << 8);\r\n\r\n /* Write to TIMx CCER register */\r\n TIMx->CCER = tmpccer;\r\n}\r\n\r\n/**\r\n * @brief Configures the TIMx Channel 3N polarity.\r\n * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.\r\n * @param TIM_OCNPolarity: specifies the OC3N Polarity\r\n * This parameter can be one of the following values:\r\n * @arg TIM_OCNPolarity_High: Output Compare active high\r\n * @arg TIM_OCNPolarity_Low: Output Compare active low\r\n * @retval None\r\n */\r\nvoid TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)\r\n{\r\n uint16_t tmpccer = 0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r\n assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));\r\n \r\n tmpccer = TIMx->CCER;\r\n\r\n /* Set or Reset the CC3NP Bit */\r\n tmpccer &= (uint16_t)~TIM_CCER_CC3NP;\r\n tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);\r\n\r\n /* Write to TIMx CCER register */\r\n TIMx->CCER = tmpccer;\r\n}\r\n\r\n/**\r\n * @brief Configures the TIMx channel 4 polarity.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r\n * @param TIM_OCPolarity: specifies the OC4 Polarity\r\n * This parameter can be one of the following values:\r\n * @arg TIM_OCPolarity_High: Output Compare active high\r\n * @arg TIM_OCPolarity_Low: Output Compare active low\r\n * @retval None\r\n */\r\nvoid TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r\n{\r\n uint16_t tmpccer = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r\n assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r\n\r\n tmpccer = TIMx->CCER;\r\n\r\n /* Set or Reset the CC4P Bit */\r\n tmpccer &= (uint16_t)~TIM_CCER_CC4P;\r\n tmpccer |= (uint16_t)(TIM_OCPolarity << 12);\r\n\r\n /* Write to TIMx CCER register */\r\n TIMx->CCER = tmpccer;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the TIM Capture Compare Channel x.\r\n * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.\r\n * @param TIM_Channel: specifies the TIM Channel\r\n * This parameter can be one of the following values:\r\n * @arg TIM_Channel_1: TIM Channel 1\r\n * @arg TIM_Channel_2: TIM Channel 2\r\n * @arg TIM_Channel_3: TIM Channel 3\r\n * @arg TIM_Channel_4: TIM Channel 4\r\n * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.\r\n * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. \r\n * @retval None\r\n */\r\nvoid TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)\r\n{\r\n uint16_t tmp = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST1_PERIPH(TIMx)); \r\n assert_param(IS_TIM_CHANNEL(TIM_Channel));\r\n assert_param(IS_TIM_CCX(TIM_CCx));\r\n\r\n tmp = CCER_CCE_SET << TIM_Channel;\r\n\r\n /* Reset the CCxE Bit */\r\n TIMx->CCER &= (uint16_t)~ tmp;\r\n\r\n /* Set or reset the CCxE Bit */ \r\n TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the TIM Capture Compare Channel xN.\r\n * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.\r\n * @param TIM_Channel: specifies the TIM Channel\r\n * This parameter can be one of the following values:\r\n * @arg TIM_Channel_1: TIM Channel 1\r\n * @arg TIM_Channel_2: TIM Channel 2\r\n * @arg TIM_Channel_3: TIM Channel 3\r\n * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.\r\n * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. \r\n * @retval None\r\n */\r\nvoid TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)\r\n{\r\n uint16_t tmp = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r\n assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));\r\n assert_param(IS_TIM_CCXN(TIM_CCxN));\r\n\r\n tmp = CCER_CCNE_SET << TIM_Channel;\r\n\r\n /* Reset the CCxNE Bit */\r\n TIMx->CCER &= (uint16_t) ~tmp;\r\n\r\n /* Set or reset the CCxNE Bit */ \r\n TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup TIM_Group3 Input Capture management functions\r\n * @brief Input Capture management functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Input Capture management functions\r\n =============================================================================== \r\n \r\n =================================================================== \r\n TIM Driver: how to use it in Input Capture Mode\r\n =================================================================== \r\n To use the Timer in Input Capture mode, the following steps are mandatory:\r\n \r\n 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function\r\n \r\n 2. Configure the TIM pins by configuring the corresponding GPIO pins\r\n \r\n 2. Configure the Time base unit as described in the first part of this driver,\r\n if needed, else the Timer will run with the default configuration:\r\n - Autoreload value = 0xFFFF\r\n - Prescaler value = 0x0000\r\n - Counter mode = Up counting\r\n - Clock Division = TIM_CKD_DIV1\r\n \r\n 3. Fill the TIM_ICInitStruct with the desired parameters including:\r\n - TIM Channel: TIM_Channel\r\n - TIM Input Capture polarity: TIM_ICPolarity\r\n - TIM Input Capture selection: TIM_ICSelection\r\n - TIM Input Capture Prescaler: TIM_ICPrescaler\r\n - TIM Input CApture filter value: TIM_ICFilter\r\n \r\n 4. Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel with the \r\n corresponding configuration and to measure only frequency or duty cycle of the input signal,\r\n or,\r\n Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired channels with the \r\n corresponding configuration and to measure the frequency and the duty cycle of the input signal\r\n \r\n 5. Enable the NVIC or the DMA to read the measured frequency. \r\n \r\n 6. Enable the corresponding interrupt (or DMA request) to read the Captured value,\r\n using the function TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) \r\n \r\n 7. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.\r\n \r\n 8. Use TIM_GetCapturex(TIMx); to read the captured value.\r\n \r\n Note1: All other functions can be used separately to modify, if needed,\r\n a specific feature of the Timer. \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Initializes the TIM peripheral according to the specified parameters\r\n * in the TIM_ICInitStruct.\r\n * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.\r\n * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains\r\n * the configuration information for the specified TIM peripheral.\r\n * @retval None\r\n */\r\nvoid TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r\n assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));\r\n assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));\r\n assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));\r\n assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));\r\n \r\n if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)\r\n {\r\n /* TI1 Configuration */\r\n TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r\n TIM_ICInitStruct->TIM_ICSelection,\r\n TIM_ICInitStruct->TIM_ICFilter);\r\n /* Set the Input Capture Prescaler value */\r\n TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r\n }\r\n else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)\r\n {\r\n /* TI2 Configuration */\r\n assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r\n TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r\n TIM_ICInitStruct->TIM_ICSelection,\r\n TIM_ICInitStruct->TIM_ICFilter);\r\n /* Set the Input Capture Prescaler value */\r\n TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r\n }\r\n else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)\r\n {\r\n /* TI3 Configuration */\r\n assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r\n TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r\n TIM_ICInitStruct->TIM_ICSelection,\r\n TIM_ICInitStruct->TIM_ICFilter);\r\n /* Set the Input Capture Prescaler value */\r\n TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r\n }\r\n else\r\n {\r\n /* TI4 Configuration */\r\n assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r\n TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r\n TIM_ICInitStruct->TIM_ICSelection,\r\n TIM_ICInitStruct->TIM_ICFilter);\r\n /* Set the Input Capture Prescaler value */\r\n TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Fills each TIM_ICInitStruct member with its default value.\r\n * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will\r\n * be initialized.\r\n * @retval None\r\n */\r\nvoid TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)\r\n{\r\n /* Set the default configuration */\r\n TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;\r\n TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;\r\n TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;\r\n TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;\r\n TIM_ICInitStruct->TIM_ICFilter = 0x00;\r\n}\r\n\r\n/**\r\n * @brief Configures the TIM peripheral according to the specified parameters\r\n * in the TIM_ICInitStruct to measure an external PWM signal.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5,8, 9 or 12 to select the TIM \r\n * peripheral.\r\n * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains\r\n * the configuration information for the specified TIM peripheral.\r\n * @retval None\r\n */\r\nvoid TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)\r\n{\r\n uint16_t icoppositepolarity = TIM_ICPolarity_Rising;\r\n uint16_t icoppositeselection = TIM_ICSelection_DirectTI;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r\n\r\n /* Select the Opposite Input Polarity */\r\n if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)\r\n {\r\n icoppositepolarity = TIM_ICPolarity_Falling;\r\n }\r\n else\r\n {\r\n icoppositepolarity = TIM_ICPolarity_Rising;\r\n }\r\n /* Select the Opposite Input */\r\n if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)\r\n {\r\n icoppositeselection = TIM_ICSelection_IndirectTI;\r\n }\r\n else\r\n {\r\n icoppositeselection = TIM_ICSelection_DirectTI;\r\n }\r\n if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)\r\n {\r\n /* TI1 Configuration */\r\n TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,\r\n TIM_ICInitStruct->TIM_ICFilter);\r\n /* Set the Input Capture Prescaler value */\r\n TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r\n /* TI2 Configuration */\r\n TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);\r\n /* Set the Input Capture Prescaler value */\r\n TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r\n }\r\n else\r\n { \r\n /* TI2 Configuration */\r\n TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,\r\n TIM_ICInitStruct->TIM_ICFilter);\r\n /* Set the Input Capture Prescaler value */\r\n TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r\n /* TI1 Configuration */\r\n TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);\r\n /* Set the Input Capture Prescaler value */\r\n TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Gets the TIMx Input Capture 1 value.\r\n * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.\r\n * @retval Capture Compare 1 Register value.\r\n */\r\nuint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r\n\r\n /* Get the Capture 1 Register value */\r\n return TIMx->CCR1;\r\n}\r\n\r\n/**\r\n * @brief Gets the TIMx Input Capture 2 value.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM \r\n * peripheral.\r\n * @retval Capture Compare 2 Register value.\r\n */\r\nuint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r\n\r\n /* Get the Capture 2 Register value */\r\n return TIMx->CCR2;\r\n}\r\n\r\n/**\r\n * @brief Gets the TIMx Input Capture 3 value.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r\n * @retval Capture Compare 3 Register value.\r\n */\r\nuint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST3_PERIPH(TIMx)); \r\n\r\n /* Get the Capture 3 Register value */\r\n return TIMx->CCR3;\r\n}\r\n\r\n/**\r\n * @brief Gets the TIMx Input Capture 4 value.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r\n * @retval Capture Compare 4 Register value.\r\n */\r\nuint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r\n\r\n /* Get the Capture 4 Register value */\r\n return TIMx->CCR4;\r\n}\r\n\r\n/**\r\n * @brief Sets the TIMx Input Capture 1 prescaler.\r\n * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.\r\n * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_ICPSC_DIV1: no prescaler\r\n * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r\n * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r\n * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r\n * @retval None\r\n */\r\nvoid TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r\n assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r\n\r\n /* Reset the IC1PSC Bits */\r\n TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC;\r\n\r\n /* Set the IC1PSC value */\r\n TIMx->CCMR1 |= TIM_ICPSC;\r\n}\r\n\r\n/**\r\n * @brief Sets the TIMx Input Capture 2 prescaler.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM \r\n * peripheral.\r\n * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_ICPSC_DIV1: no prescaler\r\n * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r\n * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r\n * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r\n * @retval None\r\n */\r\nvoid TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r\n assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r\n\r\n /* Reset the IC2PSC Bits */\r\n TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC;\r\n\r\n /* Set the IC2PSC value */\r\n TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);\r\n}\r\n\r\n/**\r\n * @brief Sets the TIMx Input Capture 3 prescaler.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r\n * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_ICPSC_DIV1: no prescaler\r\n * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r\n * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r\n * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r\n * @retval None\r\n */\r\nvoid TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r\n assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r\n\r\n /* Reset the IC3PSC Bits */\r\n TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC;\r\n\r\n /* Set the IC3PSC value */\r\n TIMx->CCMR2 |= TIM_ICPSC;\r\n}\r\n\r\n/**\r\n * @brief Sets the TIMx Input Capture 4 prescaler.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r\n * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_ICPSC_DIV1: no prescaler\r\n * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r\n * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r\n * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r\n * @retval None\r\n */\r\nvoid TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r\n{ \r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r\n assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r\n\r\n /* Reset the IC4PSC Bits */\r\n TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC;\r\n\r\n /* Set the IC4PSC value */\r\n TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup TIM_Group4 Advanced-control timers (TIM1 and TIM8) specific features\r\n * @brief Advanced-control timers (TIM1 and TIM8) specific features\r\n *\r\n@verbatim \r\n ===============================================================================\r\n Advanced-control timers (TIM1 and TIM8) specific features\r\n =============================================================================== \r\n \r\n =================================================================== \r\n TIM Driver: how to use the Break feature\r\n =================================================================== \r\n After configuring the Timer channel(s) in the appropriate Output Compare mode: \r\n \r\n 1. Fill the TIM_BDTRInitStruct with the desired parameters for the Timer\r\n Break Polarity, dead time, Lock level, the OSSI/OSSR State and the \r\n AOE(automatic output enable).\r\n \r\n 2. Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer\r\n \r\n 3. Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE) \r\n \r\n 4. Once the break even occurs, the Timer's output signals are put in reset\r\n state or in a known state (according to the configuration made in\r\n TIM_BDTRConfig() function).\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State\r\n * and the AOE(automatic output enable).\r\n * @param TIMx: where x can be 1 or 8 to select the TIM \r\n * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that\r\n * contains the BDTR Register configuration information for the TIM peripheral.\r\n * @retval None\r\n */\r\nvoid TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r\n assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));\r\n assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));\r\n assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));\r\n assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));\r\n assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));\r\n assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));\r\n\r\n /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,\r\n the OSSI State, the dead time value and the Automatic Output Enable Bit */\r\n TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |\r\n TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |\r\n TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |\r\n TIM_BDTRInitStruct->TIM_AutomaticOutput;\r\n}\r\n\r\n/**\r\n * @brief Fills each TIM_BDTRInitStruct member with its default value.\r\n * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which\r\n * will be initialized.\r\n * @retval None\r\n */\r\nvoid TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)\r\n{\r\n /* Set the default configuration */\r\n TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;\r\n TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;\r\n TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;\r\n TIM_BDTRInitStruct->TIM_DeadTime = 0x00;\r\n TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;\r\n TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;\r\n TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the TIM peripheral Main Outputs.\r\n * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral.\r\n * @param NewState: new state of the TIM peripheral Main Outputs.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the TIM Main Output */\r\n TIMx->BDTR |= TIM_BDTR_MOE;\r\n }\r\n else\r\n {\r\n /* Disable the TIM Main Output */\r\n TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE;\r\n } \r\n}\r\n\r\n/**\r\n * @brief Selects the TIM peripheral Commutation event.\r\n * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral\r\n * @param NewState: new state of the Commutation event.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n if (NewState != DISABLE)\r\n {\r\n /* Set the COM Bit */\r\n TIMx->CR2 |= TIM_CR2_CCUS;\r\n }\r\n else\r\n {\r\n /* Reset the COM Bit */\r\n TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.\r\n * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral\r\n * @param NewState: new state of the Capture Compare Preload Control bit\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)\r\n{ \r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n /* Set the CCPC Bit */\r\n TIMx->CR2 |= TIM_CR2_CCPC;\r\n }\r\n else\r\n {\r\n /* Reset the CCPC Bit */\r\n TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC;\r\n }\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup TIM_Group5 Interrupts DMA and flags management functions\r\n * @brief Interrupts, DMA and flags management functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Interrupts, DMA and flags management functions\r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Enables or disables the specified TIM interrupts.\r\n * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral.\r\n * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.\r\n * This parameter can be any combination of the following values:\r\n * @arg TIM_IT_Update: TIM update Interrupt source\r\n * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r\n * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r\n * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r\n * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r\n * @arg TIM_IT_COM: TIM Commutation Interrupt source\r\n * @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r\n * @arg TIM_IT_Break: TIM Break Interrupt source\r\n * \r\n * @note For TIM6 and TIM7 only the parameter TIM_IT_Update can be used\r\n * @note For TIM9 and TIM12 only one of the following parameters can be used: TIM_IT_Update,\r\n * TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. \r\n * @note For TIM10, TIM11, TIM13 and TIM14 only one of the following parameters can\r\n * be used: TIM_IT_Update or TIM_IT_CC1 \r\n * @note TIM_IT_COM and TIM_IT_Break can be used only with TIM1 and TIM8 \r\n * \r\n * @param NewState: new state of the TIM interrupts.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)\r\n{ \r\n /* Check the parameters */\r\n assert_param(IS_TIM_ALL_PERIPH(TIMx));\r\n assert_param(IS_TIM_IT(TIM_IT));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the Interrupt sources */\r\n TIMx->DIER |= TIM_IT;\r\n }\r\n else\r\n {\r\n /* Disable the Interrupt sources */\r\n TIMx->DIER &= (uint16_t)~TIM_IT;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Configures the TIMx event to be generate by software.\r\n * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.\r\n * @param TIM_EventSource: specifies the event source.\r\n * This parameter can be one or more of the following values:\t \r\n * @arg TIM_EventSource_Update: Timer update Event source\r\n * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source\r\n * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source\r\n * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source\r\n * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source\r\n * @arg TIM_EventSource_COM: Timer COM event source \r\n * @arg TIM_EventSource_Trigger: Timer Trigger Event source\r\n * @arg TIM_EventSource_Break: Timer Break event source\r\n * \r\n * @note TIM6 and TIM7 can only generate an update event. \r\n * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.\r\n * \r\n * @retval None\r\n */\r\nvoid TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)\r\n{ \r\n /* Check the parameters */\r\n assert_param(IS_TIM_ALL_PERIPH(TIMx));\r\n assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));\r\n \r\n /* Set the event sources */\r\n TIMx->EGR = TIM_EventSource;\r\n}\r\n\r\n/**\r\n * @brief Checks whether the specified TIM flag is set or not.\r\n * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.\r\n * @param TIM_FLAG: specifies the flag to check.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_FLAG_Update: TIM update Flag\r\n * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag\r\n * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag\r\n * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag\r\n * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag\r\n * @arg TIM_FLAG_COM: TIM Commutation Flag\r\n * @arg TIM_FLAG_Trigger: TIM Trigger Flag\r\n * @arg TIM_FLAG_Break: TIM Break Flag\r\n * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag\r\n * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag\r\n * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag\r\n * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag\r\n *\r\n * @note TIM6 and TIM7 can have only one update flag. \r\n * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. \r\n *\r\n * @retval The new state of TIM_FLAG (SET or RESET).\r\n */\r\nFlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)\r\n{ \r\n ITStatus bitstatus = RESET; \r\n /* Check the parameters */\r\n assert_param(IS_TIM_ALL_PERIPH(TIMx));\r\n assert_param(IS_TIM_GET_FLAG(TIM_FLAG));\r\n\r\n \r\n if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)\r\n {\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n bitstatus = RESET;\r\n }\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @brief Clears the TIMx's pending flags.\r\n * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.\r\n * @param TIM_FLAG: specifies the flag bit to clear.\r\n * This parameter can be any combination of the following values:\r\n * @arg TIM_FLAG_Update: TIM update Flag\r\n * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag\r\n * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag\r\n * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag\r\n * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag\r\n * @arg TIM_FLAG_COM: TIM Commutation Flag\r\n * @arg TIM_FLAG_Trigger: TIM Trigger Flag\r\n * @arg TIM_FLAG_Break: TIM Break Flag\r\n * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag\r\n * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag\r\n * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag\r\n * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag\r\n *\r\n * @note TIM6 and TIM7 can have only one update flag. \r\n * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.\r\n * \r\n * @retval None\r\n */\r\nvoid TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)\r\n{ \r\n /* Check the parameters */\r\n assert_param(IS_TIM_ALL_PERIPH(TIMx));\r\n \r\n /* Clear the flags */\r\n TIMx->SR = (uint16_t)~TIM_FLAG;\r\n}\r\n\r\n/**\r\n * @brief Checks whether the TIM interrupt has occurred or not.\r\n * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.\r\n * @param TIM_IT: specifies the TIM interrupt source to check.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_IT_Update: TIM update Interrupt source\r\n * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r\n * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r\n * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r\n * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r\n * @arg TIM_IT_COM: TIM Commutation Interrupt source\r\n * @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r\n * @arg TIM_IT_Break: TIM Break Interrupt source\r\n *\r\n * @note TIM6 and TIM7 can generate only an update interrupt.\r\n * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.\r\n * \r\n * @retval The new state of the TIM_IT(SET or RESET).\r\n */\r\nITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)\r\n{\r\n ITStatus bitstatus = RESET; \r\n uint16_t itstatus = 0x0, itenable = 0x0;\r\n /* Check the parameters */\r\n assert_param(IS_TIM_ALL_PERIPH(TIMx));\r\n assert_param(IS_TIM_GET_IT(TIM_IT));\r\n \r\n itstatus = TIMx->SR & TIM_IT;\r\n \r\n itenable = TIMx->DIER & TIM_IT;\r\n if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))\r\n {\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n bitstatus = RESET;\r\n }\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @brief Clears the TIMx's interrupt pending bits.\r\n * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.\r\n * @param TIM_IT: specifies the pending bit to clear.\r\n * This parameter can be any combination of the following values:\r\n * @arg TIM_IT_Update: TIM1 update Interrupt source\r\n * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r\n * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r\n * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r\n * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r\n * @arg TIM_IT_COM: TIM Commutation Interrupt source\r\n * @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r\n * @arg TIM_IT_Break: TIM Break Interrupt source\r\n *\r\n * @note TIM6 and TIM7 can generate only an update interrupt.\r\n * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.\r\n * \r\n * @retval None\r\n */\r\nvoid TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_ALL_PERIPH(TIMx));\r\n\r\n /* Clear the IT pending Bit */\r\n TIMx->SR = (uint16_t)~TIM_IT;\r\n}\r\n\r\n/**\r\n * @brief Configures the TIMx's DMA interface.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r\n * @param TIM_DMABase: DMA Base address.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_DMABase_CR1 \r\n * @arg TIM_DMABase_CR2\r\n * @arg TIM_DMABase_SMCR\r\n * @arg TIM_DMABase_DIER\r\n * @arg TIM1_DMABase_SR\r\n * @arg TIM_DMABase_EGR\r\n * @arg TIM_DMABase_CCMR1\r\n * @arg TIM_DMABase_CCMR2\r\n * @arg TIM_DMABase_CCER\r\n * @arg TIM_DMABase_CNT \r\n * @arg TIM_DMABase_PSC \r\n * @arg TIM_DMABase_ARR\r\n * @arg TIM_DMABase_RCR\r\n * @arg TIM_DMABase_CCR1\r\n * @arg TIM_DMABase_CCR2\r\n * @arg TIM_DMABase_CCR3 \r\n * @arg TIM_DMABase_CCR4\r\n * @arg TIM_DMABase_BDTR\r\n * @arg TIM_DMABase_DCR\r\n * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value\r\n * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.\r\n * @retval None\r\n */\r\nvoid TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r\n assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); \r\n assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));\r\n\r\n /* Set the DMA Base and the DMA Burst Length */\r\n TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the TIMx's DMA Requests.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral.\r\n * @param TIM_DMASource: specifies the DMA Request sources.\r\n * This parameter can be any combination of the following values:\r\n * @arg TIM_DMA_Update: TIM update Interrupt source\r\n * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r\n * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r\n * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r\n * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r\n * @arg TIM_DMA_COM: TIM Commutation DMA source\r\n * @arg TIM_DMA_Trigger: TIM Trigger DMA source\r\n * @param NewState: new state of the DMA Request sources.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)\r\n{ \r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST5_PERIPH(TIMx)); \r\n assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the DMA sources */\r\n TIMx->DIER |= TIM_DMASource; \r\n }\r\n else\r\n {\r\n /* Disable the DMA sources */\r\n TIMx->DIER &= (uint16_t)~TIM_DMASource;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Selects the TIMx peripheral Capture Compare DMA source.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r\n * @param NewState: new state of the Capture Compare DMA source\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n if (NewState != DISABLE)\r\n {\r\n /* Set the CCDS Bit */\r\n TIMx->CR2 |= TIM_CR2_CCDS;\r\n }\r\n else\r\n {\r\n /* Reset the CCDS Bit */\r\n TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS;\r\n }\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup TIM_Group6 Clocks management functions\r\n * @brief Clocks management functions\r\n *\r\n@verbatim \r\n ===============================================================================\r\n Clocks management functions\r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Configures the TIMx internal Clock\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM \r\n * peripheral.\r\n * @retval None\r\n */\r\nvoid TIM_InternalClockConfig(TIM_TypeDef* TIMx)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r\n\r\n /* Disable slave mode to clock the prescaler directly with the internal clock */\r\n TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS;\r\n}\r\n\r\n/**\r\n * @brief Configures the TIMx Internal Trigger as External Clock\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM \r\n * peripheral.\r\n * @param TIM_InputTriggerSource: Trigger source.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_TS_ITR0: Internal Trigger 0\r\n * @arg TIM_TS_ITR1: Internal Trigger 1\r\n * @arg TIM_TS_ITR2: Internal Trigger 2\r\n * @arg TIM_TS_ITR3: Internal Trigger 3\r\n * @retval None\r\n */\r\nvoid TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r\n assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));\r\n\r\n /* Select the Internal Trigger */\r\n TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);\r\n\r\n /* Select the External clock mode1 */\r\n TIMx->SMCR |= TIM_SlaveMode_External1;\r\n}\r\n\r\n/**\r\n * @brief Configures the TIMx Trigger as External Clock\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 \r\n * to select the TIM peripheral.\r\n * @param TIM_TIxExternalCLKSource: Trigger source.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector\r\n * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1\r\n * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2\r\n * @param TIM_ICPolarity: specifies the TIx Polarity.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_ICPolarity_Rising\r\n * @arg TIM_ICPolarity_Falling\r\n * @param ICFilter: specifies the filter value.\r\n * This parameter must be a value between 0x0 and 0xF.\r\n * @retval None\r\n */\r\nvoid TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,\r\n uint16_t TIM_ICPolarity, uint16_t ICFilter)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r\n assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));\r\n assert_param(IS_TIM_IC_FILTER(ICFilter));\r\n\r\n /* Configure the Timer Input Clock Source */\r\n if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)\r\n {\r\n TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);\r\n }\r\n else\r\n {\r\n TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);\r\n }\r\n /* Select the Trigger source */\r\n TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);\r\n /* Select the External clock mode1 */\r\n TIMx->SMCR |= TIM_SlaveMode_External1;\r\n}\r\n\r\n/**\r\n * @brief Configures the External clock Mode1\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r\n * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r\n * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r\n * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r\n * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r\n * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r\n * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r\n * @param ExtTRGFilter: External Trigger Filter.\r\n * This parameter must be a value between 0x00 and 0x0F\r\n * @retval None\r\n */\r\nvoid TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,\r\n uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)\r\n{\r\n uint16_t tmpsmcr = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r\n assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r\n assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r\n assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r\n /* Configure the ETR Clock source */\r\n TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);\r\n \r\n /* Get the TIMx SMCR register value */\r\n tmpsmcr = TIMx->SMCR;\r\n\r\n /* Reset the SMS Bits */\r\n tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;\r\n\r\n /* Select the External clock mode1 */\r\n tmpsmcr |= TIM_SlaveMode_External1;\r\n\r\n /* Select the Trigger selection : ETRF */\r\n tmpsmcr &= (uint16_t)~TIM_SMCR_TS;\r\n tmpsmcr |= TIM_TS_ETRF;\r\n\r\n /* Write to TIMx SMCR */\r\n TIMx->SMCR = tmpsmcr;\r\n}\r\n\r\n/**\r\n * @brief Configures the External clock Mode2\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r\n * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r\n * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r\n * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r\n * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r\n * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r\n * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r\n * @param ExtTRGFilter: External Trigger Filter.\r\n * This parameter must be a value between 0x00 and 0x0F\r\n * @retval None\r\n */\r\nvoid TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, \r\n uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r\n assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r\n assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r\n assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r\n\r\n /* Configure the ETR Clock source */\r\n TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);\r\n\r\n /* Enable the External clock mode2 */\r\n TIMx->SMCR |= TIM_SMCR_ECE;\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup TIM_Group7 Synchronization management functions\r\n * @brief Synchronization management functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Synchronization management functions\r\n =============================================================================== \r\n \r\n =================================================================== \r\n TIM Driver: how to use it in synchronization Mode\r\n =================================================================== \r\n Case of two/several Timers\r\n **************************\r\n 1. Configure the Master Timers using the following functions:\r\n - void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); \r\n - void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); \r\n 2. Configure the Slave Timers using the following functions: \r\n - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); \r\n - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); \r\n \r\n Case of Timers and external trigger(ETR pin)\r\n ******************************************** \r\n 1. Configure the External trigger using this function:\r\n - void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r\n uint16_t ExtTRGFilter);\r\n 2. Configure the Slave Timers using the following functions: \r\n - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); \r\n - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Selects the Input Trigger source\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 \r\n * to select the TIM peripheral.\r\n * @param TIM_InputTriggerSource: The Input Trigger source.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_TS_ITR0: Internal Trigger 0\r\n * @arg TIM_TS_ITR1: Internal Trigger 1\r\n * @arg TIM_TS_ITR2: Internal Trigger 2\r\n * @arg TIM_TS_ITR3: Internal Trigger 3\r\n * @arg TIM_TS_TI1F_ED: TI1 Edge Detector\r\n * @arg TIM_TS_TI1FP1: Filtered Timer Input 1\r\n * @arg TIM_TS_TI2FP2: Filtered Timer Input 2\r\n * @arg TIM_TS_ETRF: External Trigger input\r\n * @retval None\r\n */\r\nvoid TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)\r\n{\r\n uint16_t tmpsmcr = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST1_PERIPH(TIMx)); \r\n assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));\r\n\r\n /* Get the TIMx SMCR register value */\r\n tmpsmcr = TIMx->SMCR;\r\n\r\n /* Reset the TS Bits */\r\n tmpsmcr &= (uint16_t)~TIM_SMCR_TS;\r\n\r\n /* Set the Input Trigger source */\r\n tmpsmcr |= TIM_InputTriggerSource;\r\n\r\n /* Write to TIMx SMCR */\r\n TIMx->SMCR = tmpsmcr;\r\n}\r\n\r\n/**\r\n * @brief Selects the TIMx Trigger Output Mode.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral.\r\n * \r\n * @param TIM_TRGOSource: specifies the Trigger Output source.\r\n * This parameter can be one of the following values:\r\n *\r\n * - For all TIMx\r\n * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO)\r\n * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO)\r\n * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO)\r\n *\r\n * - For all TIMx except TIM6 and TIM7\r\n * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag\r\n * is to be set, as soon as a capture or compare match occurs(TRGO)\r\n * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO)\r\n * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO)\r\n * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO)\r\n * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO)\r\n *\r\n * @retval None\r\n */\r\nvoid TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST5_PERIPH(TIMx));\r\n assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));\r\n\r\n /* Reset the MMS Bits */\r\n TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS;\r\n /* Select the TRGO source */\r\n TIMx->CR2 |= TIM_TRGOSource;\r\n}\r\n\r\n/**\r\n * @brief Selects the TIMx Slave Mode.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.\r\n * @param TIM_SlaveMode: specifies the Timer Slave Mode.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal(TRGI) reinitialize \r\n * the counter and triggers an update of the registers\r\n * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high\r\n * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI\r\n * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter\r\n * @retval None\r\n */\r\nvoid TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r\n assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));\r\n\r\n /* Reset the SMS Bits */\r\n TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS;\r\n\r\n /* Select the Slave Mode */\r\n TIMx->SMCR |= TIM_SlaveMode;\r\n}\r\n\r\n/**\r\n * @brief Sets or Resets the TIMx Master/Slave Mode.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.\r\n * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer\r\n * and its slaves (through TRGO)\r\n * @arg TIM_MasterSlaveMode_Disable: No action\r\n * @retval None\r\n */\r\nvoid TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r\n assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));\r\n\r\n /* Reset the MSM Bit */\r\n TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM;\r\n \r\n /* Set or Reset the MSM Bit */\r\n TIMx->SMCR |= TIM_MasterSlaveMode;\r\n}\r\n\r\n/**\r\n * @brief Configures the TIMx External Trigger (ETR).\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r\n * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r\n * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r\n * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r\n * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r\n * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r\n * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r\n * @param ExtTRGFilter: External Trigger Filter.\r\n * This parameter must be a value between 0x00 and 0x0F\r\n * @retval None\r\n */\r\nvoid TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,\r\n uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)\r\n{\r\n uint16_t tmpsmcr = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r\n assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r\n assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r\n assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r\n\r\n tmpsmcr = TIMx->SMCR;\r\n\r\n /* Reset the ETR Bits */\r\n tmpsmcr &= SMCR_ETR_MASK;\r\n\r\n /* Set the Prescaler, the Filter value and the Polarity */\r\n tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));\r\n\r\n /* Write to TIMx SMCR */\r\n TIMx->SMCR = tmpsmcr;\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup TIM_Group8 Specific interface management functions\r\n * @brief Specific interface management functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Specific interface management functions\r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Configures the TIMx Encoder Interface.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM \r\n * peripheral.\r\n * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.\r\n * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.\r\n * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending\r\n * on the level of the other input.\r\n * @param TIM_IC1Polarity: specifies the IC1 Polarity\r\n * This parameter can be one of the following values:\r\n * @arg TIM_ICPolarity_Falling: IC Falling edge.\r\n * @arg TIM_ICPolarity_Rising: IC Rising edge.\r\n * @param TIM_IC2Polarity: specifies the IC2 Polarity\r\n * This parameter can be one of the following values:\r\n * @arg TIM_ICPolarity_Falling: IC Falling edge.\r\n * @arg TIM_ICPolarity_Rising: IC Rising edge.\r\n * @retval None\r\n */\r\nvoid TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,\r\n uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)\r\n{\r\n uint16_t tmpsmcr = 0;\r\n uint16_t tmpccmr1 = 0;\r\n uint16_t tmpccer = 0;\r\n \r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r\n assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));\r\n assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));\r\n assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));\r\n\r\n /* Get the TIMx SMCR register value */\r\n tmpsmcr = TIMx->SMCR;\r\n\r\n /* Get the TIMx CCMR1 register value */\r\n tmpccmr1 = TIMx->CCMR1;\r\n\r\n /* Get the TIMx CCER register value */\r\n tmpccer = TIMx->CCER;\r\n\r\n /* Set the encoder Mode */\r\n tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;\r\n tmpsmcr |= TIM_EncoderMode;\r\n\r\n /* Select the Capture Compare 1 and the Capture Compare 2 as input */\r\n tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S);\r\n tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;\r\n\r\n /* Set the TI1 and the TI2 Polarities */\r\n tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P);\r\n tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));\r\n\r\n /* Write to TIMx SMCR */\r\n TIMx->SMCR = tmpsmcr;\r\n\r\n /* Write to TIMx CCMR1 */\r\n TIMx->CCMR1 = tmpccmr1;\r\n\r\n /* Write to TIMx CCER */\r\n TIMx->CCER = tmpccer;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the TIMx's Hall sensor interface.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM \r\n * peripheral.\r\n * @param NewState: new state of the TIMx Hall sensor interface.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n if (NewState != DISABLE)\r\n {\r\n /* Set the TI1S Bit */\r\n TIMx->CR2 |= TIM_CR2_TI1S;\r\n }\r\n else\r\n {\r\n /* Reset the TI1S Bit */\r\n TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S;\r\n }\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup TIM_Group9 Specific remapping management function\r\n * @brief Specific remapping management function\r\n *\r\n@verbatim \r\n ===============================================================================\r\n Specific remapping management function\r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.\r\n * @param TIMx: where x can be 2, 5 or 11 to select the TIM peripheral.\r\n * @param TIM_Remap: specifies the TIM input remapping source.\r\n * This parameter can be one of the following values:\r\n * @arg TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)\r\n * @arg TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trogger output.\r\n * @arg TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF. \r\n * @arg TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF. \r\n * @arg TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default)\r\n * @arg TIM5_LSI: TIM5 CH4 input is connected to LSI clock.\r\n * @arg TIM5_LSE: TIM5 CH4 input is connected to LSE clock.\r\n * @arg TIM5_RTC: TIM5 CH4 input is connected to RTC Output event.\r\n * @arg TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default) \r\n * @arg TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock\r\n * (HSE divided by a programmable prescaler) \r\n * @retval None\r\n */\r\nvoid TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r\n assert_param(IS_TIM_REMAP(TIM_Remap));\r\n\r\n /* Set the Timer remapping configuration */\r\n TIMx->OR = TIM_Remap;\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @brief Configure the TI1 as Input.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 \r\n * to select the TIM peripheral.\r\n * @param TIM_ICPolarity : The Input Polarity.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_ICPolarity_Rising\r\n * @arg TIM_ICPolarity_Falling\r\n * @arg TIM_ICPolarity_BothEdge \r\n * @param TIM_ICSelection: specifies the input to be used.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.\r\n * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.\r\n * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.\r\n * @param TIM_ICFilter: Specifies the Input Capture Filter.\r\n * This parameter must be a value between 0x00 and 0x0F.\r\n * @retval None\r\n */\r\nstatic void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r\n uint16_t TIM_ICFilter)\r\n{\r\n uint16_t tmpccmr1 = 0, tmpccer = 0;\r\n\r\n /* Disable the Channel 1: Reset the CC1E Bit */\r\n TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E;\r\n tmpccmr1 = TIMx->CCMR1;\r\n tmpccer = TIMx->CCER;\r\n\r\n /* Select the Input and set the filter */\r\n tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_IC1F);\r\n tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));\r\n\r\n /* Select the Polarity and set the CC1E Bit */\r\n tmpccer &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP);\r\n tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);\r\n\r\n /* Write to TIMx CCMR1 and CCER registers */\r\n TIMx->CCMR1 = tmpccmr1;\r\n TIMx->CCER = tmpccer;\r\n}\r\n\r\n/**\r\n * @brief Configure the TI2 as Input.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM \r\n * peripheral.\r\n * @param TIM_ICPolarity : The Input Polarity.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_ICPolarity_Rising\r\n * @arg TIM_ICPolarity_Falling\r\n * @arg TIM_ICPolarity_BothEdge \r\n * @param TIM_ICSelection: specifies the input to be used.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.\r\n * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.\r\n * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.\r\n * @param TIM_ICFilter: Specifies the Input Capture Filter.\r\n * This parameter must be a value between 0x00 and 0x0F.\r\n * @retval None\r\n */\r\nstatic void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r\n uint16_t TIM_ICFilter)\r\n{\r\n uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;\r\n\r\n /* Disable the Channel 2: Reset the CC2E Bit */\r\n TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E;\r\n tmpccmr1 = TIMx->CCMR1;\r\n tmpccer = TIMx->CCER;\r\n tmp = (uint16_t)(TIM_ICPolarity << 4);\r\n\r\n /* Select the Input and set the filter */\r\n tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F);\r\n tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);\r\n tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);\r\n\r\n /* Select the Polarity and set the CC2E Bit */\r\n tmpccer &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP);\r\n tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);\r\n\r\n /* Write to TIMx CCMR1 and CCER registers */\r\n TIMx->CCMR1 = tmpccmr1 ;\r\n TIMx->CCER = tmpccer;\r\n}\r\n\r\n/**\r\n * @brief Configure the TI3 as Input.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r\n * @param TIM_ICPolarity : The Input Polarity.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_ICPolarity_Rising\r\n * @arg TIM_ICPolarity_Falling\r\n * @arg TIM_ICPolarity_BothEdge \r\n * @param TIM_ICSelection: specifies the input to be used.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.\r\n * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.\r\n * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.\r\n * @param TIM_ICFilter: Specifies the Input Capture Filter.\r\n * This parameter must be a value between 0x00 and 0x0F.\r\n * @retval None\r\n */\r\nstatic void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r\n uint16_t TIM_ICFilter)\r\n{\r\n uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;\r\n\r\n /* Disable the Channel 3: Reset the CC3E Bit */\r\n TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E;\r\n tmpccmr2 = TIMx->CCMR2;\r\n tmpccer = TIMx->CCER;\r\n tmp = (uint16_t)(TIM_ICPolarity << 8);\r\n\r\n /* Select the Input and set the filter */\r\n tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F);\r\n tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));\r\n\r\n /* Select the Polarity and set the CC3E Bit */\r\n tmpccer &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP);\r\n tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);\r\n\r\n /* Write to TIMx CCMR2 and CCER registers */\r\n TIMx->CCMR2 = tmpccmr2;\r\n TIMx->CCER = tmpccer;\r\n}\r\n\r\n/**\r\n * @brief Configure the TI4 as Input.\r\n * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r\n * @param TIM_ICPolarity : The Input Polarity.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_ICPolarity_Rising\r\n * @arg TIM_ICPolarity_Falling\r\n * @arg TIM_ICPolarity_BothEdge \r\n * @param TIM_ICSelection: specifies the input to be used.\r\n * This parameter can be one of the following values:\r\n * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.\r\n * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.\r\n * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.\r\n * @param TIM_ICFilter: Specifies the Input Capture Filter.\r\n * This parameter must be a value between 0x00 and 0x0F.\r\n * @retval None\r\n */\r\nstatic void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r\n uint16_t TIM_ICFilter)\r\n{\r\n uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;\r\n\r\n /* Disable the Channel 4: Reset the CC4E Bit */\r\n TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E;\r\n tmpccmr2 = TIMx->CCMR2;\r\n tmpccer = TIMx->CCER;\r\n tmp = (uint16_t)(TIM_ICPolarity << 12);\r\n\r\n /* Select the Input and set the filter */\r\n tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F);\r\n tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);\r\n tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);\r\n\r\n /* Select the Polarity and set the CC4E Bit */\r\n tmpccer &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP);\r\n tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);\r\n\r\n /* Write to TIMx CCMR2 and CCER registers */\r\n TIMx->CCMR2 = tmpccmr2;\r\n TIMx->CCER = tmpccer ;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_usart.c\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file provides firmware functions to manage the following \r\n * functionalities of the Universal synchronous asynchronous receiver\r\n * transmitter (USART): \r\n * - Initialization and Configuration\r\n * - Data transfers\r\n * - Multi-Processor Communication\r\n * - LIN mode\r\n * - Half-duplex mode\r\n * - Smartcard mode\r\n * - IrDA mode\r\n * - DMA transfers management\r\n * - Interrupts and flags management \r\n * \r\n * @verbatim\r\n * \r\n * ===================================================================\r\n * How to use this driver\r\n * ===================================================================\r\n * 1. Enable peripheral clock using the follwoing functions\r\n * RCC_APB2PeriphClockCmd(RCC_APB2Periph_USARTx, ENABLE) for USART1 and USART6 \r\n * RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE) for USART2, USART3, UART4 or UART5.\r\n *\r\n * 2. According to the USART mode, enable the GPIO clocks using \r\n * RCC_AHB1PeriphClockCmd() function. (The I/O can be TX, RX, CTS, \r\n * or/and SCLK). \r\n *\r\n * 3. Peripheral's alternate function: \r\n * - Connect the pin to the desired peripherals' Alternate \r\n * Function (AF) using GPIO_PinAFConfig() function\r\n * - Configure the desired pin in alternate function by:\r\n * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF\r\n * - Select the type, pull-up/pull-down and output speed via \r\n * GPIO_PuPd, GPIO_OType and GPIO_Speed members\r\n * - Call GPIO_Init() function\r\n * \r\n * 4. Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware \r\n * flow control and Mode(Receiver/Transmitter) using the USART_Init()\r\n * function.\r\n *\r\n * 5. For synchronous mode, enable the clock and program the polarity,\r\n * phase and last bit using the USART_ClockInit() function.\r\n *\r\n * 5. Enable the NVIC and the corresponding interrupt using the function \r\n * USART_ITConfig() if you need to use interrupt mode. \r\n *\r\n * 6. When using the DMA mode \r\n * - Configure the DMA using DMA_Init() function\r\n * - Active the needed channel Request using USART_DMACmd() function\r\n * \r\n * 7. Enable the USART using the USART_Cmd() function.\r\n * \r\n * 8. Enable the DMA using the DMA_Cmd() function, when using DMA mode. \r\n *\r\n * Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections\r\n * for more details\r\n * \r\n * In order to reach higher communication baudrates, it is possible to\r\n * enable the oversampling by 8 mode using the function USART_OverSampling8Cmd().\r\n * This function should be called after enabling the USART clock (RCC_APBxPeriphClockCmd())\r\n * and before calling the function USART_Init().\r\n * \r\n * @endverbatim\r\n * \r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx_usart.h\"\r\n#include \"stm32f4xx_rcc.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @defgroup USART \r\n * @brief USART driver modules\r\n * @{\r\n */\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n\r\n/*!< USART CR1 register clear Mask ((~(uint16_t)0xE9F3)) */\r\n#define CR1_CLEAR_MASK ((uint16_t)(USART_CR1_M | USART_CR1_PCE | \\\r\n USART_CR1_PS | USART_CR1_TE | \\\r\n USART_CR1_RE))\r\n\r\n/*!< USART CR2 register clock bits clear Mask ((~(uint16_t)0xF0FF)) */\r\n#define CR2_CLOCK_CLEAR_MASK ((uint16_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \\\r\n USART_CR2_CPHA | USART_CR2_LBCL))\r\n\r\n/*!< USART CR3 register clear Mask ((~(uint16_t)0xFCFF)) */\r\n#define CR3_CLEAR_MASK ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE))\r\n\r\n/*!< USART Interrupts mask */\r\n#define IT_MASK ((uint16_t)0x001F)\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup USART_Private_Functions\r\n * @{\r\n */\r\n\r\n/** @defgroup USART_Group1 Initialization and Configuration functions\r\n * @brief Initialization and Configuration functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Initialization and Configuration functions\r\n =============================================================================== \r\n\r\n This subsection provides a set of functions allowing to initialize the USART \r\n in asynchronous and in synchronous modes.\r\n - For the asynchronous mode only these parameters can be configured: \r\n - Baud Rate\r\n - Word Length \r\n - Stop Bit\r\n - Parity: If the parity is enabled, then the MSB bit of the data written\r\n in the data register is transmitted but is changed by the parity bit.\r\n Depending on the frame length defined by the M bit (8-bits or 9-bits),\r\n the possible USART frame formats are as listed in the following table:\r\n +-------------------------------------------------------------+ \r\n | M bit | PCE bit | USART frame |\r\n |---------------------|---------------------------------------| \r\n | 0 | 0 | | SB | 8 bit data | STB | |\r\n |---------|-----------|---------------------------------------| \r\n | 0 | 1 | | SB | 7 bit data | PB | STB | |\r\n |---------|-----------|---------------------------------------| \r\n | 1 | 0 | | SB | 9 bit data | STB | |\r\n |---------|-----------|---------------------------------------| \r\n | 1 | 1 | | SB | 8 bit data | PB | STB | |\r\n +-------------------------------------------------------------+ \r\n - Hardware flow control\r\n - Receiver/transmitter modes\r\n\r\n The USART_Init() function follows the USART asynchronous configuration procedure\r\n (details for the procedure are available in reference manual (RM0090)).\r\n\r\n - For the synchronous mode in addition to the asynchronous mode parameters these \r\n parameters should be also configured:\r\n - USART Clock Enabled\r\n - USART polarity\r\n - USART phase\r\n - USART LastBit\r\n \r\n These parameters can be configured using the USART_ClockInit() function.\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n \r\n/**\r\n * @brief Deinitializes the USARTx peripheral registers to their default reset values.\r\n * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or \r\n * UART peripheral.\r\n * @retval None\r\n */\r\nvoid USART_DeInit(USART_TypeDef* USARTx)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_USART_ALL_PERIPH(USARTx));\r\n\r\n if (USARTx == USART1)\r\n {\r\n RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);\r\n RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);\r\n }\r\n else if (USARTx == USART2)\r\n {\r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);\r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);\r\n }\r\n else if (USARTx == USART3)\r\n {\r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);\r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);\r\n } \r\n else if (USARTx == UART4)\r\n {\r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);\r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);\r\n }\r\n else if (USARTx == UART5)\r\n {\r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);\r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);\r\n } \r\n else\r\n {\r\n if (USARTx == USART6)\r\n { \r\n RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE);\r\n RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE);\r\n }\r\n }\r\n}\r\n\r\n/**\r\n * @brief Initializes the USARTx peripheral according to the specified\r\n * parameters in the USART_InitStruct .\r\n * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or \r\n * UART peripheral.\r\n * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that contains\r\n * the configuration information for the specified USART peripheral.\r\n * @retval None\r\n */\r\nvoid USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)\r\n{\r\n uint32_t tmpreg = 0x00, apbclock = 0x00;\r\n uint32_t integerdivider = 0x00;\r\n uint32_t fractionaldivider = 0x00;\r\n RCC_ClocksTypeDef RCC_ClocksStatus;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_USART_ALL_PERIPH(USARTx));\r\n assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); \r\n assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));\r\n assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));\r\n assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));\r\n assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));\r\n assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));\r\n\r\n /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */\r\n if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)\r\n {\r\n assert_param(IS_USART_1236_PERIPH(USARTx));\r\n }\r\n\r\n/*---------------------------- USART CR2 Configuration -----------------------*/\r\n tmpreg = USARTx->CR2;\r\n\r\n /* Clear STOP[13:12] bits */\r\n tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);\r\n\r\n /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit :\r\n Set STOP[13:12] bits according to USART_StopBits value */\r\n tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;\r\n \r\n /* Write to USART CR2 */\r\n USARTx->CR2 = (uint16_t)tmpreg;\r\n\r\n/*---------------------------- USART CR1 Configuration -----------------------*/\r\n tmpreg = USARTx->CR1;\r\n\r\n /* Clear M, PCE, PS, TE and RE bits */\r\n tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK);\r\n\r\n /* Configure the USART Word Length, Parity and mode: \r\n Set the M bits according to USART_WordLength value \r\n Set PCE and PS bits according to USART_Parity value\r\n Set TE and RE bits according to USART_Mode value */\r\n tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |\r\n USART_InitStruct->USART_Mode;\r\n\r\n /* Write to USART CR1 */\r\n USARTx->CR1 = (uint16_t)tmpreg;\r\n\r\n/*---------------------------- USART CR3 Configuration -----------------------*/ \r\n tmpreg = USARTx->CR3;\r\n\r\n /* Clear CTSE and RTSE bits */\r\n tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK);\r\n\r\n /* Configure the USART HFC : \r\n Set CTSE and RTSE bits according to USART_HardwareFlowControl value */\r\n tmpreg |= USART_InitStruct->USART_HardwareFlowControl;\r\n\r\n /* Write to USART CR3 */\r\n USARTx->CR3 = (uint16_t)tmpreg;\r\n\r\n/*---------------------------- USART BRR Configuration -----------------------*/\r\n /* Configure the USART Baud Rate */\r\n RCC_GetClocksFreq(&RCC_ClocksStatus);\r\n\r\n if ((USARTx == USART1) || (USARTx == USART6))\r\n {\r\n apbclock = RCC_ClocksStatus.PCLK2_Frequency;\r\n }\r\n else\r\n {\r\n apbclock = RCC_ClocksStatus.PCLK1_Frequency;\r\n }\r\n \r\n /* Determine the integer part */\r\n if ((USARTx->CR1 & USART_CR1_OVER8) != 0)\r\n {\r\n /* Integer part computing in case Oversampling mode is 8 Samples */\r\n integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); \r\n }\r\n else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */\r\n {\r\n /* Integer part computing in case Oversampling mode is 16 Samples */\r\n integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); \r\n }\r\n tmpreg = (integerdivider / 100) << 4;\r\n\r\n /* Determine the fractional part */\r\n fractionaldivider = integerdivider - (100 * (tmpreg >> 4));\r\n\r\n /* Implement the fractional part in the register */\r\n if ((USARTx->CR1 & USART_CR1_OVER8) != 0)\r\n {\r\n tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);\r\n }\r\n else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */\r\n {\r\n tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);\r\n }\r\n \r\n /* Write to USART BRR register */\r\n USARTx->BRR = (uint16_t)tmpreg;\r\n}\r\n\r\n/**\r\n * @brief Fills each USART_InitStruct member with its default value.\r\n * @param USART_InitStruct: pointer to a USART_InitTypeDef structure which will\r\n * be initialized.\r\n * @retval None\r\n */\r\nvoid USART_StructInit(USART_InitTypeDef* USART_InitStruct)\r\n{\r\n /* USART_InitStruct members default value */\r\n USART_InitStruct->USART_BaudRate = 9600;\r\n USART_InitStruct->USART_WordLength = USART_WordLength_8b;\r\n USART_InitStruct->USART_StopBits = USART_StopBits_1;\r\n USART_InitStruct->USART_Parity = USART_Parity_No ;\r\n USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;\r\n USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; \r\n}\r\n\r\n/**\r\n * @brief Initializes the USARTx peripheral Clock according to the \r\n * specified parameters in the USART_ClockInitStruct .\r\n * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART peripheral.\r\n * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure that\r\n * contains the configuration information for the specified USART peripheral.\r\n * @note The Smart Card and Synchronous modes are not available for UART4 and UART5. \r\n * @retval None\r\n */\r\nvoid USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)\r\n{\r\n uint32_t tmpreg = 0x00;\r\n /* Check the parameters */\r\n assert_param(IS_USART_1236_PERIPH(USARTx));\r\n assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));\r\n assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));\r\n assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));\r\n assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));\r\n \r\n/*---------------------------- USART CR2 Configuration -----------------------*/\r\n tmpreg = USARTx->CR2;\r\n /* Clear CLKEN, CPOL, CPHA and LBCL bits */\r\n tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK);\r\n /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/\r\n /* Set CLKEN bit according to USART_Clock value */\r\n /* Set CPOL bit according to USART_CPOL value */\r\n /* Set CPHA bit according to USART_CPHA value */\r\n /* Set LBCL bit according to USART_LastBit value */\r\n tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | \r\n USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;\r\n /* Write to USART CR2 */\r\n USARTx->CR2 = (uint16_t)tmpreg;\r\n}\r\n\r\n/**\r\n * @brief Fills each USART_ClockInitStruct member with its default value.\r\n * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure\r\n * which will be initialized.\r\n * @retval None\r\n */\r\nvoid USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)\r\n{\r\n /* USART_ClockInitStruct members default value */\r\n USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;\r\n USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;\r\n USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;\r\n USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the specified USART peripheral.\r\n * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or \r\n * UART peripheral.\r\n * @param NewState: new state of the USARTx peripheral.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_USART_ALL_PERIPH(USARTx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the selected USART by setting the UE bit in the CR1 register */\r\n USARTx->CR1 |= USART_CR1_UE;\r\n }\r\n else\r\n {\r\n /* Disable the selected USART by clearing the UE bit in the CR1 register */\r\n USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_UE);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Sets the system clock prescaler.\r\n * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or \r\n * UART peripheral.\r\n * @param USART_Prescaler: specifies the prescaler clock. \r\n * @note The function is used for IrDA mode with UART4 and UART5. \r\n * @retval None\r\n */\r\nvoid USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)\r\n{ \r\n /* Check the parameters */\r\n assert_param(IS_USART_ALL_PERIPH(USARTx));\r\n \r\n /* Clear the USART prescaler */\r\n USARTx->GTPR &= USART_GTPR_GT;\r\n /* Set the USART prescaler */\r\n USARTx->GTPR |= USART_Prescaler;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the USART's 8x oversampling mode.\r\n * @note This function has to be called before calling USART_Init() function\r\n * in order to have correct baudrate Divider value.\r\n * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or \r\n * UART peripheral.\r\n * @param NewState: new state of the USART 8x oversampling mode.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_USART_ALL_PERIPH(USARTx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */\r\n USARTx->CR1 |= USART_CR1_OVER8;\r\n }\r\n else\r\n {\r\n /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */\r\n USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_OVER8);\r\n }\r\n} \r\n\r\n/**\r\n * @brief Enables or disables the USART's one bit sampling method.\r\n * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or \r\n * UART peripheral.\r\n * @param NewState: new state of the USART one bit sampling method.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_USART_ALL_PERIPH(USARTx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */\r\n USARTx->CR3 |= USART_CR3_ONEBIT;\r\n }\r\n else\r\n {\r\n /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */\r\n USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT);\r\n }\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup USART_Group2 Data transfers functions\r\n * @brief Data transfers functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Data transfers functions\r\n =============================================================================== \r\n\r\n This subsection provides a set of functions allowing to manage the USART data \r\n transfers.\r\n \r\n During an USART reception, data shifts in least significant bit first through \r\n the RX pin. In this mode, the USART_DR register consists of a buffer (RDR) \r\n between the internal bus and the received shift register.\r\n\r\n When a transmission is taking place, a write instruction to the USART_DR register \r\n stores the data in the TDR register and which is copied in the shift register \r\n at the end of the current transmission.\r\n\r\n The read access of the USART_DR register can be done using the USART_ReceiveData()\r\n function and returns the RDR buffered value. Whereas a write access to the USART_DR \r\n can be done using USART_SendData() function and stores the written data into \r\n TDR buffer.\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Transmits single data through the USARTx peripheral.\r\n * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or \r\n * UART peripheral.\r\n * @param Data: the data to transmit.\r\n * @retval None\r\n */\r\nvoid USART_SendData(USART_TypeDef* USARTx, uint16_t Data)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_USART_ALL_PERIPH(USARTx));\r\n assert_param(IS_USART_DATA(Data)); \r\n \r\n /* Transmit Data */\r\n USARTx->DR = (Data & (uint16_t)0x01FF);\r\n}\r\n\r\n/**\r\n * @brief Returns the most recent received data by the USARTx peripheral.\r\n * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or \r\n * UART peripheral.\r\n * @retval The received data.\r\n */\r\nuint16_t USART_ReceiveData(USART_TypeDef* USARTx)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_USART_ALL_PERIPH(USARTx));\r\n \r\n /* Receive Data */\r\n return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup USART_Group3 MultiProcessor Communication functions\r\n * @brief Multi-Processor Communication functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Multi-Processor Communication functions\r\n =============================================================================== \r\n\r\n This subsection provides a set of functions allowing to manage the USART \r\n multiprocessor communication.\r\n \r\n For instance one of the USARTs can be the master, its TX output is connected to \r\n the RX input of the other USART. The others are slaves, their respective TX outputs \r\n are logically ANDed together and connected to the RX input of the master.\r\n\r\n USART multiprocessor communication is possible through the following procedure:\r\n 1. Program the Baud rate, Word length = 9 bits, Stop bits, Parity, Mode transmitter \r\n or Mode receiver and hardware flow control values using the USART_Init()\r\n function.\r\n 2. Configures the USART address using the USART_SetAddress() function.\r\n 3. Configures the wake up method (USART_WakeUp_IdleLine or USART_WakeUp_AddressMark)\r\n using USART_WakeUpConfig() function only for the slaves.\r\n 4. Enable the USART using the USART_Cmd() function.\r\n 5. Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() function.\r\n\r\n The USART Slave exit from mute mode when receive the wake up condition.\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Sets the address of the USART node.\r\n * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or \r\n * UART peripheral.\r\n * @param USART_Address: Indicates the address of the USART node.\r\n * @retval None\r\n */\r\nvoid USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_USART_ALL_PERIPH(USARTx));\r\n assert_param(IS_USART_ADDRESS(USART_Address)); \r\n \r\n /* Clear the USART address */\r\n USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_ADD);\r\n /* Set the USART address node */\r\n USARTx->CR2 |= USART_Address;\r\n}\r\n\r\n/**\r\n * @brief Determines if the USART is in mute mode or not.\r\n * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or \r\n * UART peripheral.\r\n * @param NewState: new state of the USART mute mode.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_USART_ALL_PERIPH(USARTx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState)); \r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the USART mute mode by setting the RWU bit in the CR1 register */\r\n USARTx->CR1 |= USART_CR1_RWU;\r\n }\r\n else\r\n {\r\n /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */\r\n USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_RWU);\r\n }\r\n}\r\n/**\r\n * @brief Selects the USART WakeUp method.\r\n * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or \r\n * UART peripheral.\r\n * @param USART_WakeUp: specifies the USART wakeup method.\r\n * This parameter can be one of the following values:\r\n * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection\r\n * @arg USART_WakeUp_AddressMark: WakeUp by an address mark\r\n * @retval None\r\n */\r\nvoid USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_USART_ALL_PERIPH(USARTx));\r\n assert_param(IS_USART_WAKEUP(USART_WakeUp));\r\n \r\n USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_WAKE);\r\n USARTx->CR1 |= USART_WakeUp;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup USART_Group4 LIN mode functions\r\n * @brief LIN mode functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n LIN mode functions\r\n =============================================================================== \r\n\r\n This subsection provides a set of functions allowing to manage the USART LIN \r\n Mode communication.\r\n \r\n In LIN mode, 8-bit data format with 1 stop bit is required in accordance with \r\n the LIN standard.\r\n\r\n Only this LIN Feature is supported by the USART IP:\r\n - LIN Master Synchronous Break send capability and LIN slave break detection\r\n capability : 13-bit break generation and 10/11 bit break detection\r\n\r\n\r\n USART LIN Master transmitter communication is possible through the following procedure:\r\n 1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, \r\n Mode transmitter or Mode receiver and hardware flow control values using \r\n the USART_Init() function.\r\n 2. Enable the USART using the USART_Cmd() function.\r\n 3. Enable the LIN mode using the USART_LINCmd() function.\r\n 4. Send the break character using USART_SendBreak() function.\r\n\r\n USART LIN Master receiver communication is possible through the following procedure:\r\n 1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, \r\n Mode transmitter or Mode receiver and hardware flow control values using \r\n the USART_Init() function.\r\n 2. Enable the USART using the USART_Cmd() function.\r\n 3. Configures the break detection length using the USART_LINBreakDetectLengthConfig()\r\n function.\r\n 4. Enable the LIN mode using the USART_LINCmd() function.\r\n\r\n\r\n@note In LIN mode, the following bits must be kept cleared:\r\n - CLKEN in the USART_CR2 register,\r\n - STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register.\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Sets the USART LIN Break detection length.\r\n * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or \r\n * UART peripheral.\r\n * @param USART_LINBreakDetectLength: specifies the LIN break detection length.\r\n * This parameter can be one of the following values:\r\n * @arg USART_LINBreakDetectLength_10b: 10-bit break detection\r\n * @arg USART_LINBreakDetectLength_11b: 11-bit break detection\r\n * @retval None\r\n */\r\nvoid USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_USART_ALL_PERIPH(USARTx));\r\n assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));\r\n \r\n USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LBDL);\r\n USARTx->CR2 |= USART_LINBreakDetectLength; \r\n}\r\n\r\n/**\r\n * @brief Enables or disables the USART's LIN mode.\r\n * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or \r\n * UART peripheral.\r\n * @param NewState: new state of the USART LIN mode.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_USART_ALL_PERIPH(USARTx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the LIN mode by setting the LINEN bit in the CR2 register */\r\n USARTx->CR2 |= USART_CR2_LINEN;\r\n }\r\n else\r\n {\r\n /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */\r\n USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LINEN);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Transmits break characters.\r\n * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or \r\n * UART peripheral.\r\n * @retval None\r\n */\r\nvoid USART_SendBreak(USART_TypeDef* USARTx)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_USART_ALL_PERIPH(USARTx));\r\n \r\n /* Send break characters */\r\n USARTx->CR1 |= USART_CR1_SBK;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup USART_Group5 Halfduplex mode function\r\n * @brief Half-duplex mode function \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Half-duplex mode function\r\n =============================================================================== \r\n\r\n This subsection provides a set of functions allowing to manage the USART \r\n Half-duplex communication.\r\n \r\n The USART can be configured to follow a single-wire half-duplex protocol where \r\n the TX and RX lines are internally connected.\r\n\r\n USART Half duplex communication is possible through the following procedure:\r\n 1. Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter \r\n or Mode receiver and hardware flow control values using the USART_Init()\r\n function.\r\n 2. Configures the USART address using the USART_SetAddress() function.\r\n 3. Enable the USART using the USART_Cmd() function.\r\n 4. Enable the half duplex mode using USART_HalfDuplexCmd() function.\r\n\r\n\r\n@note The RX pin is no longer used\r\n@note In Half-duplex mode the following bits must be kept cleared:\r\n - LINEN and CLKEN bits in the USART_CR2 register.\r\n - SCEN and IREN bits in the USART_CR3 register.\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Enables or disables the USART's Half Duplex communication.\r\n * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or \r\n * UART peripheral.\r\n * @param NewState: new state of the USART Communication.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_USART_ALL_PERIPH(USARTx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */\r\n USARTx->CR3 |= USART_CR3_HDSEL;\r\n }\r\n else\r\n {\r\n /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */\r\n USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_HDSEL);\r\n }\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n\r\n/** @defgroup USART_Group6 Smartcard mode functions\r\n * @brief Smartcard mode functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Smartcard mode functions\r\n =============================================================================== \r\n\r\n This subsection provides a set of functions allowing to manage the USART \r\n Smartcard communication.\r\n \r\n The Smartcard interface is designed to support asynchronous protocol Smartcards as\r\n defined in the ISO 7816-3 standard.\r\n\r\n The USART can provide a clock to the smartcard through the SCLK output.\r\n In smartcard mode, SCLK is not associated to the communication but is simply derived \r\n from the internal peripheral input clock through a 5-bit prescaler.\r\n\r\n Smartcard communication is possible through the following procedure:\r\n 1. Configures the Smartcard Prescaler using the USART_SetPrescaler() function.\r\n 2. Configures the Smartcard Guard Time using the USART_SetGuardTime() function.\r\n 3. Program the USART clock using the USART_ClockInit() function as following:\r\n - USART Clock enabled\r\n - USART CPOL Low\r\n - USART CPHA on first edge\r\n - USART Last Bit Clock Enabled\r\n 4. Program the Smartcard interface using the USART_Init() function as following:\r\n - Word Length = 9 Bits\r\n - 1.5 Stop Bit\r\n - Even parity\r\n - BaudRate = 12096 baud\r\n - Hardware flow control disabled (RTS and CTS signals)\r\n - Tx and Rx enabled\r\n 5. Optionally you can enable the parity error interrupt using the USART_ITConfig()\r\n function\r\n 6. Enable the USART using the USART_Cmd() function.\r\n 7. Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function.\r\n 8. Enable the Smartcard interface using the USART_SmartCardCmd() function.\r\n\r\n Please refer to the ISO 7816-3 specification for more details.\r\n\r\n\r\n@note It is also possible to choose 0.5 stop bit for receiving but it is recommended \r\n to use 1.5 stop bits for both transmitting and receiving to avoid switching \r\n between the two configurations.\r\n@note In smartcard mode, the following bits must be kept cleared:\r\n - LINEN bit in the USART_CR2 register.\r\n - HDSEL and IREN bits in the USART_CR3 register.\r\n@note Smartcard mode is available on USART peripherals only (not available on UART4 \r\n and UART5 peripherals).\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Sets the specified USART guard time.\r\n * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or \r\n * UART peripheral.\r\n * @param USART_GuardTime: specifies the guard time. \r\n * @retval None\r\n */\r\nvoid USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)\r\n{ \r\n /* Check the parameters */\r\n assert_param(IS_USART_1236_PERIPH(USARTx));\r\n \r\n /* Clear the USART Guard time */\r\n USARTx->GTPR &= USART_GTPR_PSC;\r\n /* Set the USART guard time */\r\n USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the USART's Smart Card mode.\r\n * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or \r\n * UART peripheral.\r\n * @param NewState: new state of the Smart Card mode.\r\n * This parameter can be: ENABLE or DISABLE. \r\n * @retval None\r\n */\r\nvoid USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_USART_1236_PERIPH(USARTx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the SC mode by setting the SCEN bit in the CR3 register */\r\n USARTx->CR3 |= USART_CR3_SCEN;\r\n }\r\n else\r\n {\r\n /* Disable the SC mode by clearing the SCEN bit in the CR3 register */\r\n USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_SCEN);\r\n }\r\n}\r\n\r\n/**\r\n * @brief Enables or disables NACK transmission.\r\n * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or \r\n * UART peripheral.\r\n * @param NewState: new state of the NACK transmission.\r\n * This parameter can be: ENABLE or DISABLE. \r\n * @retval None\r\n */\r\nvoid USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_USART_1236_PERIPH(USARTx)); \r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the NACK transmission by setting the NACK bit in the CR3 register */\r\n USARTx->CR3 |= USART_CR3_NACK;\r\n }\r\n else\r\n {\r\n /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */\r\n USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_NACK);\r\n }\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup USART_Group7 IrDA mode functions\r\n * @brief IrDA mode functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n IrDA mode functions\r\n =============================================================================== \r\n\r\n This subsection provides a set of functions allowing to manage the USART \r\n IrDA communication.\r\n \r\n IrDA is a half duplex communication protocol. If the Transmitter is busy, any data\r\n on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver \r\n is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.\r\n While receiving data, transmission should be avoided as the data to be transmitted\r\n could be corrupted.\r\n\r\n IrDA communication is possible through the following procedure:\r\n 1. Program the Baud rate, Word length = 8 bits, Stop bits, Parity, Transmitter/Receiver \r\n modes and hardware flow control values using the USART_Init() function.\r\n 2. Enable the USART using the USART_Cmd() function.\r\n 3. Configures the IrDA pulse width by configuring the prescaler using \r\n the USART_SetPrescaler() function.\r\n 4. Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal mode\r\n using the USART_IrDAConfig() function.\r\n 5. Enable the IrDA using the USART_IrDACmd() function.\r\n\r\n@note A pulse of width less than two and greater than one PSC period(s) may or may\r\n not be rejected.\r\n@note The receiver set up time should be managed by software. The IrDA physical layer\r\n specification specifies a minimum of 10 ms delay between transmission and \r\n reception (IrDA is a half duplex protocol).\r\n@note In IrDA mode, the following bits must be kept cleared:\r\n - LINEN, STOP and CLKEN bits in the USART_CR2 register.\r\n - SCEN and HDSEL bits in the USART_CR3 register.\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Configures the USART's IrDA interface.\r\n * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or \r\n * UART peripheral.\r\n * @param USART_IrDAMode: specifies the IrDA mode.\r\n * This parameter can be one of the following values:\r\n * @arg USART_IrDAMode_LowPower\r\n * @arg USART_IrDAMode_Normal\r\n * @retval None\r\n */\r\nvoid USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_USART_ALL_PERIPH(USARTx));\r\n assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));\r\n \r\n USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IRLP);\r\n USARTx->CR3 |= USART_IrDAMode;\r\n}\r\n\r\n/**\r\n * @brief Enables or disables the USART's IrDA interface.\r\n * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or \r\n * UART peripheral.\r\n * @param NewState: new state of the IrDA mode.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_USART_ALL_PERIPH(USARTx));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n \r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the IrDA mode by setting the IREN bit in the CR3 register */\r\n USARTx->CR3 |= USART_CR3_IREN;\r\n }\r\n else\r\n {\r\n /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */\r\n USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IREN);\r\n }\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup USART_Group8 DMA transfers management functions\r\n * @brief DMA transfers management functions\r\n *\r\n@verbatim \r\n ===============================================================================\r\n DMA transfers management functions\r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n \r\n/**\r\n * @brief Enables or disables the USART's DMA interface.\r\n * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or \r\n * UART peripheral.\r\n * @param USART_DMAReq: specifies the DMA request.\r\n * This parameter can be any combination of the following values:\r\n * @arg USART_DMAReq_Tx: USART DMA transmit request\r\n * @arg USART_DMAReq_Rx: USART DMA receive request\r\n * @param NewState: new state of the DMA Request sources.\r\n * This parameter can be: ENABLE or DISABLE. \r\n * @retval None\r\n */\r\nvoid USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_USART_ALL_PERIPH(USARTx));\r\n assert_param(IS_USART_DMAREQ(USART_DMAReq)); \r\n assert_param(IS_FUNCTIONAL_STATE(NewState)); \r\n\r\n if (NewState != DISABLE)\r\n {\r\n /* Enable the DMA transfer for selected requests by setting the DMAT and/or\r\n DMAR bits in the USART CR3 register */\r\n USARTx->CR3 |= USART_DMAReq;\r\n }\r\n else\r\n {\r\n /* Disable the DMA transfer for selected requests by clearing the DMAT and/or\r\n DMAR bits in the USART CR3 register */\r\n USARTx->CR3 &= (uint16_t)~USART_DMAReq;\r\n }\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n \r\n/** @defgroup USART_Group9 Interrupts and flags management functions\r\n * @brief Interrupts and flags management functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Interrupts and flags management functions\r\n =============================================================================== \r\n\r\n This subsection provides a set of functions allowing to configure the USART \r\n Interrupts sources, DMA channels requests and check or clear the flags or \r\n pending bits status.\r\n The user should identify which mode will be used in his application to manage \r\n the communication: Polling mode, Interrupt mode or DMA mode. \r\n \r\n Polling Mode\r\n =============\r\n In Polling Mode, the SPI communication can be managed by 10 flags:\r\n 1. USART_FLAG_TXE : to indicate the status of the transmit buffer register\r\n 2. USART_FLAG_RXNE : to indicate the status of the receive buffer register\r\n 3. USART_FLAG_TC : to indicate the status of the transmit operation\r\n 4. USART_FLAG_IDLE : to indicate the status of the Idle Line \r\n 5. USART_FLAG_CTS : to indicate the status of the nCTS input\r\n 6. USART_FLAG_LBD : to indicate the status of the LIN break detection\r\n 7. USART_FLAG_NE : to indicate if a noise error occur\r\n 8. USART_FLAG_FE : to indicate if a frame error occur\r\n 9. USART_FLAG_PE : to indicate if a parity error occur\r\n 10. USART_FLAG_ORE : to indicate if an Overrun error occur\r\n\r\n In this Mode it is advised to use the following functions:\r\n - FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);\r\n - void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);\r\n\r\n Interrupt Mode\r\n ===============\r\n In Interrupt Mode, the USART communication can be managed by 8 interrupt sources\r\n and 10 pending bits: \r\n\r\n Pending Bits:\r\n ------------- \r\n 1. USART_IT_TXE : to indicate the status of the transmit buffer register\r\n 2. USART_IT_RXNE : to indicate the status of the receive buffer register\r\n 3. USART_IT_TC : to indicate the status of the transmit operation\r\n 4. USART_IT_IDLE : to indicate the status of the Idle Line \r\n 5. USART_IT_CTS : to indicate the status of the nCTS input\r\n 6. USART_IT_LBD : to indicate the status of the LIN break detection\r\n 7. USART_IT_NE : to indicate if a noise error occur\r\n 8. USART_IT_FE : to indicate if a frame error occur\r\n 9. USART_IT_PE : to indicate if a parity error occur\r\n 10. USART_IT_ORE : to indicate if an Overrun error occur\r\n\r\n Interrupt Source:\r\n -----------------\r\n 1. USART_IT_TXE : specifies the interrupt source for the Tx buffer empty \r\n interrupt. \r\n 2. USART_IT_RXNE : specifies the interrupt source for the Rx buffer not \r\n empty interrupt.\r\n 3. USART_IT_TC : specifies the interrupt source for the Transmit complete \r\n interrupt. \r\n 4. USART_IT_IDLE : specifies the interrupt source for the Idle Line interrupt. \r\n 5. USART_IT_CTS : specifies the interrupt source for the CTS interrupt. \r\n 6. USART_IT_LBD : specifies the interrupt source for the LIN break detection\r\n interrupt. \r\n 7. USART_IT_PE : specifies the interrupt source for the parity error interrupt. \r\n 8. USART_IT_ERR : specifies the interrupt source for the errors interrupt.\r\n\r\n@note Some parameters are coded in order to use them as interrupt source or as pending bits.\r\n\r\n In this Mode it is advised to use the following functions:\r\n - void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);\r\n - ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);\r\n - void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);\r\n\r\n DMA Mode\r\n ========\r\n In DMA Mode, the USART communication can be managed by 2 DMA Channel requests:\r\n 1. USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request\r\n 2. USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request\r\n\r\n In this Mode it is advised to use the following function:\r\n - void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);\r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Enables or disables the specified USART interrupts.\r\n * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or \r\n * UART peripheral.\r\n * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled.\r\n * This parameter can be one of the following values:\r\n * @arg USART_IT_CTS: CTS change interrupt\r\n * @arg USART_IT_LBD: LIN Break detection interrupt\r\n * @arg USART_IT_TXE: Transmit Data Register empty interrupt\r\n * @arg USART_IT_TC: Transmission complete interrupt\r\n * @arg USART_IT_RXNE: Receive Data register not empty interrupt\r\n * @arg USART_IT_IDLE: Idle line detection interrupt\r\n * @arg USART_IT_PE: Parity Error interrupt\r\n * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)\r\n * @param NewState: new state of the specified USARTx interrupts.\r\n * This parameter can be: ENABLE or DISABLE.\r\n * @retval None\r\n */\r\nvoid USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)\r\n{\r\n uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;\r\n uint32_t usartxbase = 0x00;\r\n /* Check the parameters */\r\n assert_param(IS_USART_ALL_PERIPH(USARTx));\r\n assert_param(IS_USART_CONFIG_IT(USART_IT));\r\n assert_param(IS_FUNCTIONAL_STATE(NewState));\r\n\r\n /* The CTS interrupt is not available for UART4 and UART5 */\r\n if (USART_IT == USART_IT_CTS)\r\n {\r\n assert_param(IS_USART_1236_PERIPH(USARTx));\r\n } \r\n \r\n usartxbase = (uint32_t)USARTx;\r\n\r\n /* Get the USART register index */\r\n usartreg = (((uint8_t)USART_IT) >> 0x05);\r\n\r\n /* Get the interrupt position */\r\n itpos = USART_IT & IT_MASK;\r\n itmask = (((uint32_t)0x01) << itpos);\r\n \r\n if (usartreg == 0x01) /* The IT is in CR1 register */\r\n {\r\n usartxbase += 0x0C;\r\n }\r\n else if (usartreg == 0x02) /* The IT is in CR2 register */\r\n {\r\n usartxbase += 0x10;\r\n }\r\n else /* The IT is in CR3 register */\r\n {\r\n usartxbase += 0x14; \r\n }\r\n if (NewState != DISABLE)\r\n {\r\n *(__IO uint32_t*)usartxbase |= itmask;\r\n }\r\n else\r\n {\r\n *(__IO uint32_t*)usartxbase &= ~itmask;\r\n }\r\n}\r\n\r\n/**\r\n * @brief Checks whether the specified USART flag is set or not.\r\n * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or \r\n * UART peripheral.\r\n * @param USART_FLAG: specifies the flag to check.\r\n * This parameter can be one of the following values:\r\n * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)\r\n * @arg USART_FLAG_LBD: LIN Break detection flag\r\n * @arg USART_FLAG_TXE: Transmit data register empty flag\r\n * @arg USART_FLAG_TC: Transmission Complete flag\r\n * @arg USART_FLAG_RXNE: Receive data register not empty flag\r\n * @arg USART_FLAG_IDLE: Idle Line detection flag\r\n * @arg USART_FLAG_ORE: OverRun Error flag\r\n * @arg USART_FLAG_NE: Noise Error flag\r\n * @arg USART_FLAG_FE: Framing Error flag\r\n * @arg USART_FLAG_PE: Parity Error flag\r\n * @retval The new state of USART_FLAG (SET or RESET).\r\n */\r\nFlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)\r\n{\r\n FlagStatus bitstatus = RESET;\r\n /* Check the parameters */\r\n assert_param(IS_USART_ALL_PERIPH(USARTx));\r\n assert_param(IS_USART_FLAG(USART_FLAG));\r\n\r\n /* The CTS flag is not available for UART4 and UART5 */\r\n if (USART_FLAG == USART_FLAG_CTS)\r\n {\r\n assert_param(IS_USART_1236_PERIPH(USARTx));\r\n } \r\n \r\n if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)\r\n {\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n bitstatus = RESET;\r\n }\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @brief Clears the USARTx's pending flags.\r\n * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or \r\n * UART peripheral.\r\n * @param USART_FLAG: specifies the flag to clear.\r\n * This parameter can be any combination of the following values:\r\n * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).\r\n * @arg USART_FLAG_LBD: LIN Break detection flag.\r\n * @arg USART_FLAG_TC: Transmission Complete flag.\r\n * @arg USART_FLAG_RXNE: Receive data register not empty flag.\r\n * \r\n * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun \r\n * error) and IDLE (Idle line detected) flags are cleared by software \r\n * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) \r\n * followed by a read operation to USART_DR register (USART_ReceiveData()).\r\n * @note RXNE flag can be also cleared by a read to the USART_DR register \r\n * (USART_ReceiveData()).\r\n * @note TC flag can be also cleared by software sequence: a read operation to \r\n * USART_SR register (USART_GetFlagStatus()) followed by a write operation\r\n * to USART_DR register (USART_SendData()).\r\n * @note TXE flag is cleared only by a write to the USART_DR register \r\n * (USART_SendData()).\r\n * \r\n * @retval None\r\n */\r\nvoid USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_USART_ALL_PERIPH(USARTx));\r\n assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));\r\n\r\n /* The CTS flag is not available for UART4 and UART5 */\r\n if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)\r\n {\r\n assert_param(IS_USART_1236_PERIPH(USARTx));\r\n } \r\n \r\n USARTx->SR = (uint16_t)~USART_FLAG;\r\n}\r\n\r\n/**\r\n * @brief Checks whether the specified USART interrupt has occurred or not.\r\n * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or \r\n * UART peripheral.\r\n * @param USART_IT: specifies the USART interrupt source to check.\r\n * This parameter can be one of the following values:\r\n * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)\r\n * @arg USART_IT_LBD: LIN Break detection interrupt\r\n * @arg USART_IT_TXE: Transmit Data Register empty interrupt\r\n * @arg USART_IT_TC: Transmission complete interrupt\r\n * @arg USART_IT_RXNE: Receive Data register not empty interrupt\r\n * @arg USART_IT_IDLE: Idle line detection interrupt\r\n * @arg USART_IT_ORE_RX : OverRun Error interrupt if the RXNEIE bit is set\r\n * @arg USART_IT_ORE_ER : OverRun Error interrupt if the EIE bit is set \r\n * @arg USART_IT_NE: Noise Error interrupt\r\n * @arg USART_IT_FE: Framing Error interrupt\r\n * @arg USART_IT_PE: Parity Error interrupt\r\n * @retval The new state of USART_IT (SET or RESET).\r\n */\r\nITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)\r\n{\r\n uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;\r\n ITStatus bitstatus = RESET;\r\n /* Check the parameters */\r\n assert_param(IS_USART_ALL_PERIPH(USARTx));\r\n assert_param(IS_USART_GET_IT(USART_IT)); \r\n\r\n /* The CTS interrupt is not available for UART4 and UART5 */ \r\n if (USART_IT == USART_IT_CTS)\r\n {\r\n assert_param(IS_USART_1236_PERIPH(USARTx));\r\n } \r\n \r\n /* Get the USART register index */\r\n usartreg = (((uint8_t)USART_IT) >> 0x05);\r\n /* Get the interrupt position */\r\n itmask = USART_IT & IT_MASK;\r\n itmask = (uint32_t)0x01 << itmask;\r\n \r\n if (usartreg == 0x01) /* The IT is in CR1 register */\r\n {\r\n itmask &= USARTx->CR1;\r\n }\r\n else if (usartreg == 0x02) /* The IT is in CR2 register */\r\n {\r\n itmask &= USARTx->CR2;\r\n }\r\n else /* The IT is in CR3 register */\r\n {\r\n itmask &= USARTx->CR3;\r\n }\r\n \r\n bitpos = USART_IT >> 0x08;\r\n bitpos = (uint32_t)0x01 << bitpos;\r\n bitpos &= USARTx->SR;\r\n if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))\r\n {\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n bitstatus = RESET;\r\n }\r\n \r\n return bitstatus; \r\n}\r\n\r\n/**\r\n * @brief Clears the USARTx's interrupt pending bits.\r\n * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or \r\n * UART peripheral.\r\n * @param USART_IT: specifies the interrupt pending bit to clear.\r\n * This parameter can be one of the following values:\r\n * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)\r\n * @arg USART_IT_LBD: LIN Break detection interrupt\r\n * @arg USART_IT_TC: Transmission complete interrupt. \r\n * @arg USART_IT_RXNE: Receive Data register not empty interrupt.\r\n *\r\n * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun \r\n * error) and IDLE (Idle line detected) pending bits are cleared by \r\n * software sequence: a read operation to USART_SR register \r\n * (USART_GetITStatus()) followed by a read operation to USART_DR register \r\n * (USART_ReceiveData()).\r\n * @note RXNE pending bit can be also cleared by a read to the USART_DR register \r\n * (USART_ReceiveData()).\r\n * @note TC pending bit can be also cleared by software sequence: a read \r\n * operation to USART_SR register (USART_GetITStatus()) followed by a write \r\n * operation to USART_DR register (USART_SendData()).\r\n * @note TXE pending bit is cleared only by a write to the USART_DR register \r\n * (USART_SendData()).\r\n * \r\n * @retval None\r\n */\r\nvoid USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)\r\n{\r\n uint16_t bitpos = 0x00, itmask = 0x00;\r\n /* Check the parameters */\r\n assert_param(IS_USART_ALL_PERIPH(USARTx));\r\n assert_param(IS_USART_CLEAR_IT(USART_IT)); \r\n\r\n /* The CTS interrupt is not available for UART4 and UART5 */\r\n if (USART_IT == USART_IT_CTS)\r\n {\r\n assert_param(IS_USART_1236_PERIPH(USARTx));\r\n } \r\n \r\n bitpos = USART_IT >> 0x08;\r\n itmask = ((uint16_t)0x01 << (uint16_t)bitpos);\r\n USARTx->SR = (uint16_t)~itmask;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4xx_wwdg.c\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief This file provides firmware functions to manage the following \r\n * functionalities of the Window watchdog (WWDG) peripheral: \r\n * - Prescaler, Refresh window and Counter configuration\r\n * - WWDG activation\r\n * - Interrupts and flags management\r\n * \r\n * @verbatim\r\n * \r\n * ===================================================================\r\n * WWDG features\r\n * ===================================================================\r\n * \r\n * Once enabled the WWDG generates a system reset on expiry of a programmed\r\n * time period, unless the program refreshes the counter (downcounter) \r\n * before to reach 0x3F value (i.e. a reset is generated when the counter\r\n * value rolls over from 0x40 to 0x3F). \r\n * An MCU reset is also generated if the counter value is refreshed\r\n * before the counter has reached the refresh window value. This \r\n * implies that the counter must be refreshed in a limited window.\r\n * \r\n * Once enabled the WWDG cannot be disabled except by a system reset. \r\n * \r\n * WWDGRST flag in RCC_CSR register can be used to inform when a WWDG\r\n * reset occurs.\r\n * \r\n * The WWDG counter input clock is derived from the APB clock divided \r\n * by a programmable prescaler.\r\n * \r\n * WWDG counter clock = PCLK1 / Prescaler\r\n * WWDG timeout = (WWDG counter clock) * (counter value)\r\n * \r\n * Min-max timeout value @42 MHz(PCLK1): ~97.5 us / ~49.9 ms\r\n * \r\n * ===================================================================\r\n * How to use this driver\r\n * =================================================================== \r\n * 1. Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) function\r\n * \r\n * 2. Configure the WWDG prescaler using WWDG_SetPrescaler() function\r\n * \r\n * 3. Configure the WWDG refresh window using WWDG_SetWindowValue() function\r\n * \r\n * 4. Set the WWDG counter value and start it using WWDG_Enable() function.\r\n * When the WWDG is enabled the counter value should be configured to \r\n * a value greater than 0x40 to prevent generating an immediate reset. \r\n * \r\n * 5. Optionally you can enable the Early wakeup interrupt which is \r\n * generated when the counter reach 0x40.\r\n * Once enabled this interrupt cannot be disabled except by a system reset.\r\n * \r\n * 6. Then the application program must refresh the WWDG counter at regular\r\n * intervals during normal operation to prevent an MCU reset, using\r\n * WWDG_SetCounter() function. This operation must occur only when\r\n * the counter value is lower than the refresh window value, \r\n * programmed using WWDG_SetWindowValue(). \r\n *\r\n * @endverbatim \r\n * \r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx_wwdg.h\"\r\n#include \"stm32f4xx_rcc.h\"\r\n\r\n/** @addtogroup STM32F4xx_StdPeriph_Driver\r\n * @{\r\n */\r\n\r\n/** @defgroup WWDG \r\n * @brief WWDG driver modules\r\n * @{\r\n */\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n\r\n/* ----------- WWDG registers bit address in the alias region ----------- */\r\n#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)\r\n/* Alias word address of EWI bit */\r\n#define CFR_OFFSET (WWDG_OFFSET + 0x04)\r\n#define EWI_BitNumber 0x09\r\n#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))\r\n\r\n/* --------------------- WWDG registers bit mask ------------------------ */\r\n/* CFR register bit mask */\r\n#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F)\r\n#define CFR_W_MASK ((uint32_t)0xFFFFFF80)\r\n#define BIT_MASK ((uint8_t)0x7F)\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup WWDG_Private_Functions\r\n * @{\r\n */\r\n\r\n/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions\r\n * @brief Prescaler, Refresh window and Counter configuration functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Prescaler, Refresh window and Counter configuration functions\r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Deinitializes the WWDG peripheral registers to their default reset values.\r\n * @param None\r\n * @retval None\r\n */\r\nvoid WWDG_DeInit(void)\r\n{\r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);\r\n RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);\r\n}\r\n\r\n/**\r\n * @brief Sets the WWDG Prescaler.\r\n * @param WWDG_Prescaler: specifies the WWDG Prescaler.\r\n * This parameter can be one of the following values:\r\n * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1\r\n * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2\r\n * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4\r\n * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8\r\n * @retval None\r\n */\r\nvoid WWDG_SetPrescaler(uint32_t WWDG_Prescaler)\r\n{\r\n uint32_t tmpreg = 0;\r\n /* Check the parameters */\r\n assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));\r\n /* Clear WDGTB[1:0] bits */\r\n tmpreg = WWDG->CFR & CFR_WDGTB_MASK;\r\n /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */\r\n tmpreg |= WWDG_Prescaler;\r\n /* Store the new value */\r\n WWDG->CFR = tmpreg;\r\n}\r\n\r\n/**\r\n * @brief Sets the WWDG window value.\r\n * @param WindowValue: specifies the window value to be compared to the downcounter.\r\n * This parameter value must be lower than 0x80.\r\n * @retval None\r\n */\r\nvoid WWDG_SetWindowValue(uint8_t WindowValue)\r\n{\r\n __IO uint32_t tmpreg = 0;\r\n\r\n /* Check the parameters */\r\n assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));\r\n /* Clear W[6:0] bits */\r\n\r\n tmpreg = WWDG->CFR & CFR_W_MASK;\r\n\r\n /* Set W[6:0] bits according to WindowValue value */\r\n tmpreg |= WindowValue & (uint32_t) BIT_MASK;\r\n\r\n /* Store the new value */\r\n WWDG->CFR = tmpreg;\r\n}\r\n\r\n/**\r\n * @brief Enables the WWDG Early Wakeup interrupt(EWI).\r\n * @note Once enabled this interrupt cannot be disabled except by a system reset.\r\n * @param None\r\n * @retval None\r\n */\r\nvoid WWDG_EnableIT(void)\r\n{\r\n *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;\r\n}\r\n\r\n/**\r\n * @brief Sets the WWDG counter value.\r\n * @param Counter: specifies the watchdog counter value.\r\n * This parameter must be a number between 0x40 and 0x7F (to prevent generating\r\n * an immediate reset) \r\n * @retval None\r\n */\r\nvoid WWDG_SetCounter(uint8_t Counter)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_WWDG_COUNTER(Counter));\r\n /* Write to T[6:0] bits to configure the counter value, no need to do\r\n a read-modify-write; writing a 0 to WDGA bit does nothing */\r\n WWDG->CR = Counter & BIT_MASK;\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup WWDG_Group2 WWDG activation functions\r\n * @brief WWDG activation functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n WWDG activation function\r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Enables WWDG and load the counter value. \r\n * @param Counter: specifies the watchdog counter value.\r\n * This parameter must be a number between 0x40 and 0x7F (to prevent generating\r\n * an immediate reset)\r\n * @retval None\r\n */\r\nvoid WWDG_Enable(uint8_t Counter)\r\n{\r\n /* Check the parameters */\r\n assert_param(IS_WWDG_COUNTER(Counter));\r\n WWDG->CR = WWDG_CR_WDGA | Counter;\r\n}\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup WWDG_Group3 Interrupts and flags management functions\r\n * @brief Interrupts and flags management functions \r\n *\r\n@verbatim \r\n ===============================================================================\r\n Interrupts and flags management functions\r\n =============================================================================== \r\n\r\n@endverbatim\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Checks whether the Early Wakeup interrupt flag is set or not.\r\n * @param None\r\n * @retval The new state of the Early Wakeup interrupt flag (SET or RESET)\r\n */\r\nFlagStatus WWDG_GetFlagStatus(void)\r\n{\r\n FlagStatus bitstatus = RESET;\r\n \r\n if ((WWDG->SR) != (uint32_t)RESET)\r\n {\r\n bitstatus = SET;\r\n }\r\n else\r\n {\r\n bitstatus = RESET;\r\n }\r\n return bitstatus;\r\n}\r\n\r\n/**\r\n * @brief Clears Early Wakeup interrupt flag.\r\n * @param None\r\n * @retval None\r\n */\r\nvoid WWDG_ClearFlag(void)\r\n{\r\n WWDG->SR = (uint32_t)RESET;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/README", "content": "Figure simulator for STM32F4 Discovery board. Builds with Atollic\r\n\r\nQuestions? Comments? Contributions? \r\n\r\nContact: namely_audacious@hotmail.com / @natashenka" }, { "path": "figure-simulator-discovery/Utilities/STM32F4-Discovery/Release_Notes.html", "content": "\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n \r\n \r\n\r\n \r\n \r\n\r\n \r\n Release Notes for STM32F4-Discovery Board Drivers\r\n\r\n\r\n \r\n\r\n \r\n\r\n \r\n \r\n \r\n\r\n
\r\n


\r\n

\r\n
\r\n\r\n \r\n \r\n \r\n \r\n \r\n
\r\n \r\n \r\n \r\n \r\n \r\n \r\n \r\n \r\n \r\n
\r\n

Back to Release page

\r\n
\r\n

Release\r\nNotes for STM32F4-Discovery Board Drivers

\r\n

Copyright\r\n2012 STMicroelectronics

\r\n

\"\"

\r\n
\r\n

 

\r\n \r\n \r\n \r\n \r\n \r\n \r\n
\r\n

Contents

\r\n
    \r\n
  1. STM32F4-Discovery Board Drivers update History
    2. \r\n
  2. License
    3. \r\n
\r\n \r\n \r\n

STM32F4-Discovery Board Drivers update History

For more information on the STM32F4-Discovery board visit www.st.com/stm32f4-discovery.

V1.1.1 / 14-May-2012

Main\r\nChanges

\r\n
  • All source files: license disclaimer text update and add link to the License file on ST Internet.

V1.1.0 / 28-October-2011

\r\n

Main\r\nChanges

\r\n\r\n
  • Add PDM audio software decoding Library drivers, used to decode and reconstruct the audio signal produced by MP45DT02 MEMS microphone from STMicroelectronics. For more details about this Library, please refer to document \"PDM audio software decoding on STM32 microcontrollers (AN3998)\".
  • stm32f4_discovery_audio_codec.c/.h: update to use DMA instead of Interrupt in I2S communication with the external codec.

V1.0.0 / 19-September-2011

\r\n

Main\r\nChanges

\r\n\r\n
  • First official version of the STM32F4-Discovery Board Drivers

License

The PDM audio software decoding Library is licensed under MCD-ST Image SW License Agreement V2, (the \"License\"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:


Unless\r\nrequired by applicable law or agreed to in writing, software\r\ndistributed under the License is distributed on an \"AS IS\" BASIS,
WITHOUT\r\nWARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See\r\nthe License for the specific language governing permissions and\r\nlimitations under the License.

Other STM32F4-Discovery board drivers are licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:


Unless\r\nrequired by applicable law or agreed to in writing, software\r\ndistributed under the License is distributed on an \"AS IS\" BASIS,
WITHOUT\r\nWARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See\r\nthe License for the specific language governing permissions and\r\nlimitations under the License.\r\n \r\n
\r\n
\r\n

For\r\ncomplete documentation on STMicroelectronics Microcontrollers visit www.st.com

\r\n
\r\n

\r\n
\r\n
\r\n

 

\r\n
\r\n\r\n" }, { "path": "figure-simulator-discovery/Utilities/STM32F4-Discovery/pdm_filter.h", "content": "/**\r\n ******************************************************************************\r\n * @file pdm_filter.h\r\n * @author MCD Application Team\r\n * @version V1.1.1\r\n * @date 14-May-2012\r\n * @brief Header file for PDM audio software decoding Library.\r\n * This Library is used to decode and reconstruct the audio signal\r\n * produced by MP45DT02 MEMS microphone from STMicroelectronics.\r\n * For more details about this Library, please refer to document\r\n * \"PDM audio software decoding on STM32 microcontrollers (AN3998)\". \r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Image SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_image_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n \r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __PDM_FILTER_H\r\n#define __PDM_FILTER_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\ntypedef struct {\r\n\tuint16_t Fs;\r\n\tfloat LP_HZ;\r\n\tfloat HP_HZ;\r\n\tuint16_t In_MicChannels;\r\n\tuint16_t Out_MicChannels;\r\n\tchar InternalFilter[34];\r\n} PDMFilter_InitStruct;\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/* Exported macros -----------------------------------------------------------*/\r\n#define HTONS(A) ((((u16)(A) & 0xff00) >> 8) | \\\r\n (((u16)(A) & 0x00ff) << 8))\r\n\r\n/* Exported functions ------------------------------------------------------- */ \r\nvoid PDM_Filter_Init(PDMFilter_InitStruct * Filter);\r\n\r\nint32_t PDM_Filter_64_MSB(uint8_t* data, uint16_t* dataOut, uint16_t MicGain, PDMFilter_InitStruct * Filter);\r\nint32_t PDM_Filter_80_MSB(uint8_t* data, uint16_t* dataOut, uint16_t MicGain, PDMFilter_InitStruct * Filter);\r\nint32_t PDM_Filter_64_LSB(uint8_t* data, uint16_t* dataOut, uint16_t MicGain, PDMFilter_InitStruct * Filter);\r\nint32_t PDM_Filter_80_LSB(uint8_t* data, uint16_t* dataOut, uint16_t MicGain, PDMFilter_InitStruct * Filter);\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __PDM_FILTER_H */\r\n\r\n/*******************(C)COPYRIGHT 2011 STMicroelectronics *****END OF FILE******/\r\n" }, { "path": "figure-simulator-discovery/Utilities/STM32F4-Discovery/stm32f4_discovery.c", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4_discovery.c\r\n * @author MCD Application Team\r\n * @version V1.1.1\r\n * @date 14-May-2012\r\n * @brief This file provides set of firmware functions to manage Leds and\r\n * push-button available on STM32F4-Discovery Kit from STMicroelectronics.\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */ \r\n \r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4_discovery.h\"\r\n\r\n/** @addtogroup Utilities\r\n * @{\r\n */ \r\n\r\n/** @addtogroup STM32F4_DISCOVERY\r\n * @{\r\n */ \r\n \r\n/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL \r\n * @brief This file provides set of firmware functions to manage Leds and push-button\r\n * available on STM32F4-Discovery Kit from STMicroelectronics.\r\n * @{\r\n */ \r\n\r\n/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Private_TypesDefinitions\r\n * @{\r\n */ \r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Private_Defines\r\n * @{\r\n */ \r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Private_Macros\r\n * @{\r\n */ \r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Private_Variables\r\n * @{\r\n */ \r\nGPIO_TypeDef* GPIO_PORT[LEDn] = {LED4_GPIO_PORT, LED3_GPIO_PORT, LED5_GPIO_PORT,\r\n LED6_GPIO_PORT};\r\nconst uint16_t GPIO_PIN[LEDn] = {LED4_PIN, LED3_PIN, LED5_PIN,\r\n LED6_PIN};\r\nconst uint32_t GPIO_CLK[LEDn] = {LED4_GPIO_CLK, LED3_GPIO_CLK, LED5_GPIO_CLK,\r\n LED6_GPIO_CLK};\r\n\r\nGPIO_TypeDef* BUTTON_PORT[BUTTONn] = {USER_BUTTON_GPIO_PORT }; \r\n\r\nconst uint16_t BUTTON_PIN[BUTTONn] = {USER_BUTTON_PIN }; \r\n\r\nconst uint32_t BUTTON_CLK[BUTTONn] = {USER_BUTTON_GPIO_CLK };\r\n\r\nconst uint16_t BUTTON_EXTI_LINE[BUTTONn] = {USER_BUTTON_EXTI_LINE };\r\n\r\nconst uint8_t BUTTON_PORT_SOURCE[BUTTONn] = {USER_BUTTON_EXTI_PORT_SOURCE};\r\n\t\t\t\t\t\t\t\t \r\nconst uint8_t BUTTON_PIN_SOURCE[BUTTONn] = {USER_BUTTON_EXTI_PIN_SOURCE }; \r\nconst uint8_t BUTTON_IRQn[BUTTONn] = {USER_BUTTON_EXTI_IRQn };\r\n\r\nNVIC_InitTypeDef NVIC_InitStructure;\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Private_FunctionPrototypes\r\n * @{\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Private_Functions\r\n * @{\r\n */ \r\n\r\n/**\r\n * @brief Configures LED GPIO.\r\n * @param Led: Specifies the Led to be configured. \r\n * This parameter can be one of following parameters:\r\n * @arg LED4\r\n * @arg LED3\r\n * @arg LED5\r\n * @arg LED6\r\n * @retval None\r\n */\r\nvoid STM_EVAL_LEDInit(Led_TypeDef Led)\r\n{\r\n GPIO_InitTypeDef GPIO_InitStructure;\r\n \r\n /* Enable the GPIO_LED Clock */\r\n RCC_AHB1PeriphClockCmd(GPIO_CLK[Led], ENABLE);\r\n\r\n /* Configure the GPIO_LED pin */\r\n GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led];\r\n GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;\r\n GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r\n GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;\r\n GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;\r\n GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure);\r\n}\r\n\r\n/**\r\n * @brief Turns selected LED On.\r\n * @param Led: Specifies the Led to be set on. \r\n * This parameter can be one of following parameters:\r\n * @arg LED4\r\n * @arg LED3\r\n * @arg LED5\r\n * @arg LED6 \r\n * @retval None\r\n */\r\nvoid STM_EVAL_LEDOn(Led_TypeDef Led)\r\n{\r\n GPIO_PORT[Led]->BSRRL = GPIO_PIN[Led];\r\n}\r\n\r\n/**\r\n * @brief Turns selected LED Off.\r\n * @param Led: Specifies the Led to be set off. \r\n * This parameter can be one of following parameters:\r\n * @arg LED4\r\n * @arg LED3\r\n * @arg LED5\r\n * @arg LED6 \r\n * @retval None\r\n */\r\nvoid STM_EVAL_LEDOff(Led_TypeDef Led)\r\n{\r\n GPIO_PORT[Led]->BSRRH = GPIO_PIN[Led]; \r\n}\r\n\r\n/**\r\n * @brief Toggles the selected LED.\r\n * @param Led: Specifies the Led to be toggled. \r\n * This parameter can be one of following parameters:\r\n * @arg LED4\r\n * @arg LED3\r\n * @arg LED5\r\n * @arg LED6 \r\n * @retval None\r\n */\r\nvoid STM_EVAL_LEDToggle(Led_TypeDef Led)\r\n{\r\n GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led];\r\n}\r\n\r\n/**\r\n * @brief Configures Button GPIO and EXTI Line.\r\n * @param Button: Specifies the Button to be configured.\r\n * This parameter should be: BUTTON_USER\r\n * @param Button_Mode: Specifies Button mode.\r\n * This parameter can be one of following parameters: \r\n * @arg BUTTON_MODE_GPIO: Button will be used as simple IO \r\n * @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt\r\n * generation capability \r\n * @retval None\r\n */\r\nvoid STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)\r\n{\r\n GPIO_InitTypeDef GPIO_InitStructure;\r\n EXTI_InitTypeDef EXTI_InitStructure;\r\n NVIC_InitTypeDef NVIC_InitStructure;\r\n\r\n /* Enable the BUTTON Clock */\r\n RCC_AHB1PeriphClockCmd(BUTTON_CLK[Button], ENABLE);\r\n RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);\r\n\r\n /* Configure Button pin as input */\r\n GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r\n GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r\n GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button];\r\n GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure);\r\n\r\n if (Button_Mode == BUTTON_MODE_EXTI)\r\n {\r\n /* Connect Button EXTI Line to Button GPIO Pin */\r\n SYSCFG_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]);\r\n\r\n /* Configure Button EXTI line */\r\n EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button];\r\n EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;\r\n EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; \r\n EXTI_InitStructure.EXTI_LineCmd = ENABLE;\r\n EXTI_Init(&EXTI_InitStructure);\r\n\r\n /* Enable and set Button EXTI Interrupt to the lowest priority */\r\n NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button];\r\n NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;\r\n NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;\r\n NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r\n\r\n NVIC_Init(&NVIC_InitStructure); \r\n }\r\n}\r\n\r\n/**\r\n * @brief Returns the selected Button state.\r\n * @param Button: Specifies the Button to be checked.\r\n * This parameter should be: BUTTON_USER \r\n * @retval The Button GPIO pin value.\r\n */\r\nuint32_t STM_EVAL_PBGetState(Button_TypeDef Button)\r\n{\r\n return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]);\r\n}\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n \r\n/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Utilities/STM32F4-Discovery/stm32f4_discovery.h", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4_discovery.h\r\n * @author MCD Application Team\r\n * @version V1.1.1\r\n * @date 14-May-2012\r\n * @brief This file contains definitions for STM32F4-Discovery Kit's Leds and \r\n * push-button hardware resources.\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ****************************************************************************** \r\n */ \r\n \r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F4_DISCOVERY_H\r\n#define __STM32F4_DISCOVERY_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n \r\n/* Includes ------------------------------------------------------------------*/\r\n #include \"stm32f4xx.h\"\r\n \r\n/** @addtogroup Utilities\r\n * @{\r\n */\r\n \r\n/** @addtogroup STM32F4_DISCOVERY\r\n * @{\r\n */\r\n \r\n/** @addtogroup STM32F4_DISCOVERY_LOW_LEVEL\r\n * @{\r\n */ \r\n\r\n/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Types\r\n * @{\r\n */\r\ntypedef enum \r\n{\r\n LED4 = 0,\r\n LED3 = 1,\r\n LED5 = 2,\r\n LED6 = 3\r\n} Led_TypeDef;\r\n\r\ntypedef enum \r\n{ \r\n BUTTON_USER = 0,\r\n} Button_TypeDef;\r\n\r\ntypedef enum \r\n{ \r\n BUTTON_MODE_GPIO = 0,\r\n BUTTON_MODE_EXTI = 1\r\n} ButtonMode_TypeDef; \r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Constants\r\n * @{\r\n */ \r\n\r\n/** @addtogroup STM32F4_DISCOVERY_LOW_LEVEL_LED\r\n * @{\r\n */\r\n#define LEDn 4\r\n\r\n#define LED4_PIN GPIO_Pin_12\r\n#define LED4_GPIO_PORT GPIOD\r\n#define LED4_GPIO_CLK RCC_AHB1Periph_GPIOD \r\n \r\n#define LED3_PIN GPIO_Pin_13\r\n#define LED3_GPIO_PORT GPIOD\r\n#define LED3_GPIO_CLK RCC_AHB1Periph_GPIOD \r\n \r\n#define LED5_PIN GPIO_Pin_14\r\n#define LED5_GPIO_PORT GPIOD\r\n#define LED5_GPIO_CLK RCC_AHB1Periph_GPIOD \r\n \r\n#define LED6_PIN GPIO_Pin_15\r\n#define LED6_GPIO_PORT GPIOD\r\n#define LED6_GPIO_CLK RCC_AHB1Periph_GPIOD\r\n/**\r\n * @}\r\n */ \r\n \r\n/** @addtogroup STM32F4_DISCOVERY_LOW_LEVEL_BUTTON\r\n * @{\r\n */ \r\n#define BUTTONn 1 \r\n\r\n/**\r\n * @brief Wakeup push-button\r\n */\r\n#define USER_BUTTON_PIN GPIO_Pin_0\r\n#define USER_BUTTON_GPIO_PORT GPIOA\r\n#define USER_BUTTON_GPIO_CLK RCC_AHB1Periph_GPIOA\r\n#define USER_BUTTON_EXTI_LINE EXTI_Line0\r\n#define USER_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOA\r\n#define USER_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource0\r\n#define USER_BUTTON_EXTI_IRQn EXTI0_IRQn \r\n/**\r\n * @}\r\n */ \r\n \r\n/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Macros\r\n * @{\r\n */ \r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Functions\r\n * @{\r\n */\r\nvoid STM_EVAL_LEDInit(Led_TypeDef Led);\r\nvoid STM_EVAL_LEDOn(Led_TypeDef Led);\r\nvoid STM_EVAL_LEDOff(Led_TypeDef Led);\r\nvoid STM_EVAL_LEDToggle(Led_TypeDef Led);\r\nvoid STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);\r\nuint32_t STM_EVAL_PBGetState(Button_TypeDef Button);\r\n/**\r\n * @}\r\n */\r\n \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F4_DISCOVERY_H */\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */\r\n\r\n \r\n\r\n/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Utilities/STM32F4-Discovery/stm32f4_discovery_lis302dl.c", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4_discovery_lis302dl.c\r\n * @author MCD Application Team\r\n * @version V1.1.1\r\n * @date 14-May-2012\r\n * @brief This file provides a set of functions needed to manage the LIS302DL\r\n * MEMS accelerometer available on STM32F4-Discovery Kit.\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ****************************************************************************** \r\n */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4_discovery_lis302dl.h\"\r\n\r\n/** @addtogroup Utilities\r\n * @{\r\n */ \r\n\r\n/** @addtogroup STM32F4_DISCOVERY\r\n * @{\r\n */ \r\n\r\n/** @addtogroup STM32F4_DISCOVERY_LIS302DL\r\n * @{\r\n */\r\n\r\n\r\n/** @defgroup STM32F4_DISCOVERY_LIS302DL_Private_TypesDefinitions\r\n * @{\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup STM32F4_DISCOVERY_LIS302DL_Private_Defines\r\n * @{\r\n */\r\n__IO uint32_t LIS302DLTimeout = LIS302DL_FLAG_TIMEOUT; \r\n\r\n/* Read/Write command */\r\n#define READWRITE_CMD ((uint8_t)0x80) \r\n/* Multiple byte read/write command */ \r\n#define MULTIPLEBYTE_CMD ((uint8_t)0x40)\r\n/* Dummy Byte Send by the SPI Master device in order to generate the Clock to the Slave device */\r\n#define DUMMY_BYTE ((uint8_t)0x00)\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup STM32F4_DISCOVERY_LIS302DL_Private_Macros\r\n * @{\r\n */\r\n\r\n/**\r\n * @}\r\n */ \r\n \r\n/** @defgroup STM32F4_DISCOVERY_LIS302DL_Private_Variables\r\n * @{\r\n */ \r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup STM32F4_DISCOVERY_LIS302DL_Private_FunctionPrototypes\r\n * @{\r\n */\r\nstatic uint8_t LIS302DL_SendByte(uint8_t byte);\r\nstatic void LIS302DL_LowLevel_Init(void);\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup STM32F4_DISCOVERY_LIS302DL_Private_Functions\r\n * @{\r\n */\r\n\r\n\r\n/**\r\n * @brief Set LIS302DL Initialization.\r\n * @param LIS302DL_Config_Struct: pointer to a LIS302DL_Config_TypeDef structure \r\n * that contains the configuration setting for the LIS302DL.\r\n * @retval None\r\n */\r\nvoid LIS302DL_Init(LIS302DL_InitTypeDef *LIS302DL_InitStruct)\r\n{\r\n uint8_t ctrl = 0x00;\r\n \r\n /* Configure the low level interface ---------------------------------------*/\r\n LIS302DL_LowLevel_Init();\r\n \r\n /* Configure MEMS: data rate, power mode, full scale, self test and axes */\r\n ctrl = (uint8_t) (LIS302DL_InitStruct->Output_DataRate | LIS302DL_InitStruct->Power_Mode | \\\r\n LIS302DL_InitStruct->Full_Scale | LIS302DL_InitStruct->Self_Test | \\\r\n LIS302DL_InitStruct->Axes_Enable);\r\n \r\n /* Write value to MEMS CTRL_REG1 regsister */\r\n LIS302DL_Write(&ctrl, LIS302DL_CTRL_REG1_ADDR, 1);\r\n}\r\n\r\n/**\r\n * @brief Set LIS302DL Internal High Pass Filter configuration.\r\n * @param LIS302DL_Filter_ConfigTypeDef: pointer to a LIS302DL_FilterConfig_TypeDef \r\n * structure that contains the configuration setting for the LIS302DL Filter.\r\n * @retval None\r\n */\r\nvoid LIS302DL_FilterConfig(LIS302DL_FilterConfigTypeDef *LIS302DL_FilterConfigStruct)\r\n{\r\n uint8_t ctrl = 0x00;\r\n \r\n /* Read CTRL_REG2 register */\r\n LIS302DL_Read(&ctrl, LIS302DL_CTRL_REG2_ADDR, 1);\r\n \r\n /* Clear high pass filter cut-off level, interrupt and data selection bits*/\r\n ctrl &= (uint8_t)~(LIS302DL_FILTEREDDATASELECTION_OUTPUTREGISTER | \\\r\n LIS302DL_HIGHPASSFILTER_LEVEL_3 | \\\r\n LIS302DL_HIGHPASSFILTERINTERRUPT_1_2);\r\n /* Configure MEMS high pass filter cut-off level, interrupt and data selection bits */ \r\n ctrl |= (uint8_t)(LIS302DL_FilterConfigStruct->HighPassFilter_Data_Selection | \\\r\n LIS302DL_FilterConfigStruct->HighPassFilter_CutOff_Frequency | \\\r\n LIS302DL_FilterConfigStruct->HighPassFilter_Interrupt);\r\n \r\n /* Write value to MEMS CTRL_REG2 register */\r\n LIS302DL_Write(&ctrl, LIS302DL_CTRL_REG2_ADDR, 1);\r\n}\r\n\r\n/**\r\n * @brief Set LIS302DL Interrupt configuration\r\n * @param LIS302DL_InterruptConfig_TypeDef: pointer to a LIS302DL_InterruptConfig_TypeDef \r\n * structure that contains the configuration setting for the LIS302DL Interrupt.\r\n * @retval None\r\n */\r\nvoid LIS302DL_InterruptConfig(LIS302DL_InterruptConfigTypeDef *LIS302DL_IntConfigStruct)\r\n{\r\n uint8_t ctrl = 0x00;\r\n \r\n /* Read CLICK_CFG register */\r\n LIS302DL_Read(&ctrl, LIS302DL_CLICK_CFG_REG_ADDR, 1);\r\n \r\n /* Configure latch Interrupt request, click interrupts and double click interrupts */ \r\n ctrl = (uint8_t)(LIS302DL_IntConfigStruct->Latch_Request| \\\r\n LIS302DL_IntConfigStruct->SingleClick_Axes | \\\r\n LIS302DL_IntConfigStruct->DoubleClick_Axes);\r\n \r\n /* Write value to MEMS CLICK_CFG register */\r\n LIS302DL_Write(&ctrl, LIS302DL_CLICK_CFG_REG_ADDR, 1);\r\n}\r\n\r\n/**\r\n * @brief Change the lowpower mode for LIS302DL\r\n * @param LowPowerMode: new state for the lowpower mode.\r\n * This parameter can be one of the following values:\r\n * @arg LIS302DL_LOWPOWERMODE_POWERDOWN: Power down mode\r\n * @arg LIS302DL_LOWPOWERMODE_ACTIVE: Active mode \r\n * @retval None\r\n */\r\nvoid LIS302DL_LowpowerCmd(uint8_t LowPowerMode)\r\n{\r\n uint8_t tmpreg;\r\n \r\n /* Read CTRL_REG1 register */\r\n LIS302DL_Read(&tmpreg, LIS302DL_CTRL_REG1_ADDR, 1);\r\n \r\n /* Set new low power mode configuration */\r\n tmpreg &= (uint8_t)~LIS302DL_LOWPOWERMODE_ACTIVE;\r\n tmpreg |= LowPowerMode;\r\n \r\n /* Write value to MEMS CTRL_REG1 regsister */\r\n LIS302DL_Write(&tmpreg, LIS302DL_CTRL_REG1_ADDR, 1);\r\n}\r\n\r\n/**\r\n * @brief Data Rate command \r\n * @param DataRateValue: Data rate value\r\n * This parameter can be one of the following values:\r\n * @arg LIS302DL_DATARATE_100: 100 Hz output data rate \r\n * @arg LIS302DL_DATARATE_400: 400 Hz output data rate \r\n * @retval None\r\n */\r\nvoid LIS302DL_DataRateCmd(uint8_t DataRateValue)\r\n{\r\n uint8_t tmpreg;\r\n \r\n /* Read CTRL_REG1 register */\r\n LIS302DL_Read(&tmpreg, LIS302DL_CTRL_REG1_ADDR, 1);\r\n \r\n /* Set new Data rate configuration */\r\n tmpreg &= (uint8_t)~LIS302DL_DATARATE_400;\r\n tmpreg |= DataRateValue;\r\n \r\n /* Write value to MEMS CTRL_REG1 regsister */\r\n LIS302DL_Write(&tmpreg, LIS302DL_CTRL_REG1_ADDR, 1);\r\n}\r\n\r\n/**\r\n * @brief Change the Full Scale of LIS302DL\r\n * @param FS_value: new full scale value. \r\n * This parameter can be one of the following values:\r\n * @arg LIS302DL_FULLSCALE_2_3: +-2.3g\r\n * @arg LIS302DL_FULLSCALE_9_2: +-9.2g \r\n * @retval None\r\n */\r\nvoid LIS302DL_FullScaleCmd(uint8_t FS_value)\r\n{\r\n uint8_t tmpreg;\r\n \r\n /* Read CTRL_REG1 register */\r\n LIS302DL_Read(&tmpreg, LIS302DL_CTRL_REG1_ADDR, 1);\r\n \r\n /* Set new full scale configuration */\r\n tmpreg &= (uint8_t)~LIS302DL_FULLSCALE_9_2;\r\n tmpreg |= FS_value;\r\n \r\n /* Write value to MEMS CTRL_REG1 regsister */\r\n LIS302DL_Write(&tmpreg, LIS302DL_CTRL_REG1_ADDR, 1);\r\n}\r\n\r\n/**\r\n * @brief Reboot memory content of LIS302DL\r\n * @param None\r\n * @retval None\r\n */\r\nvoid LIS302DL_RebootCmd(void)\r\n{\r\n uint8_t tmpreg;\r\n /* Read CTRL_REG2 register */\r\n LIS302DL_Read(&tmpreg, LIS302DL_CTRL_REG2_ADDR, 1);\r\n \r\n /* Enable or Disable the reboot memory */\r\n tmpreg |= LIS302DL_BOOT_REBOOTMEMORY;\r\n \r\n /* Write value to MEMS CTRL_REG2 regsister */\r\n LIS302DL_Write(&tmpreg, LIS302DL_CTRL_REG2_ADDR, 1);\r\n}\r\n\r\n/**\r\n * @brief Writes one byte to the LIS302DL.\r\n * @param pBuffer : pointer to the buffer containing the data to be written to the LIS302DL.\r\n * @param WriteAddr : LIS302DL's internal address to write to.\r\n * @param NumByteToWrite: Number of bytes to write.\r\n * @retval None\r\n */\r\nvoid LIS302DL_Write(uint8_t* pBuffer, uint8_t WriteAddr, uint16_t NumByteToWrite)\r\n{\r\n /* Configure the MS bit: \r\n - When 0, the address will remain unchanged in multiple read/write commands.\r\n - When 1, the address will be auto incremented in multiple read/write commands.\r\n */\r\n if(NumByteToWrite > 0x01)\r\n {\r\n WriteAddr |= (uint8_t)MULTIPLEBYTE_CMD;\r\n }\r\n /* Set chip select Low at the start of the transmission */\r\n LIS302DL_CS_LOW();\r\n \r\n /* Send the Address of the indexed register */\r\n LIS302DL_SendByte(WriteAddr);\r\n /* Send the data that will be written into the device (MSB First) */\r\n while(NumByteToWrite >= 0x01)\r\n {\r\n LIS302DL_SendByte(*pBuffer);\r\n NumByteToWrite--;\r\n pBuffer++;\r\n }\r\n \r\n /* Set chip select High at the end of the transmission */ \r\n LIS302DL_CS_HIGH();\r\n}\r\n\r\n/**\r\n * @brief Reads a block of data from the LIS302DL.\r\n * @param pBuffer : pointer to the buffer that receives the data read from the LIS302DL.\r\n * @param ReadAddr : LIS302DL's internal address to read from.\r\n * @param NumByteToRead : number of bytes to read from the LIS302DL.\r\n * @retval None\r\n */\r\nvoid LIS302DL_Read(uint8_t* pBuffer, uint8_t ReadAddr, uint16_t NumByteToRead)\r\n{ \r\n if(NumByteToRead > 0x01)\r\n {\r\n ReadAddr |= (uint8_t)(READWRITE_CMD | MULTIPLEBYTE_CMD);\r\n }\r\n else\r\n {\r\n ReadAddr |= (uint8_t)READWRITE_CMD;\r\n }\r\n /* Set chip select Low at the start of the transmission */\r\n LIS302DL_CS_LOW();\r\n \r\n /* Send the Address of the indexed register */\r\n LIS302DL_SendByte(ReadAddr);\r\n \r\n /* Receive the data that will be read from the device (MSB First) */\r\n while(NumByteToRead > 0x00)\r\n {\r\n /* Send dummy byte (0x00) to generate the SPI clock to LIS302DL (Slave device) */\r\n *pBuffer = LIS302DL_SendByte(DUMMY_BYTE);\r\n NumByteToRead--;\r\n pBuffer++;\r\n }\r\n \r\n /* Set chip select High at the end of the transmission */ \r\n LIS302DL_CS_HIGH();\r\n}\r\n\r\n/**\r\n * @brief Read LIS302DL output register, and calculate the acceleration \r\n * ACC[mg]=SENSITIVITY* (out_h*256+out_l)/16 (12 bit rappresentation)\r\n * @param s16 buffer to store data\r\n * @retval None\r\n */\r\nvoid LIS302DL_ReadACC(int32_t* out)\r\n{\r\n uint8_t buffer[6];\r\n uint8_t crtl, i = 0x00;\r\n \r\n LIS302DL_Read(&crtl, LIS302DL_CTRL_REG1_ADDR, 1); \r\n LIS302DL_Read(buffer, LIS302DL_OUT_X_ADDR, 6);\r\n \r\n switch(crtl & 0x20) \r\n {\r\n /* FS bit = 0 ==> Sensitivity typical value = 18milligals/digit*/ \r\n case 0x00:\r\n for(i=0; i<0x03; i++)\r\n {\r\n *out =(int32_t)(LIS302DL_SENSITIVITY_2_3G * (int8_t)buffer[2*i]);\r\n out++;\r\n }\r\n break;\r\n /* FS bit = 1 ==> Sensitivity typical value = 72milligals/digit*/ \r\n case 0x20:\r\n for(i=0; i<0x03; i++)\r\n {\r\n *out =(int32_t)(LIS302DL_SENSITIVITY_9_2G * (int8_t)buffer[2*i]);\r\n out++;\r\n } \r\n break;\r\n default:\r\n break;\r\n }\r\n }\r\n\r\n/**\r\n * @brief Initializes the low level interface used to drive the LIS302DL\r\n * @param None\r\n * @retval None\r\n */\r\nstatic void LIS302DL_LowLevel_Init(void)\r\n{\r\n GPIO_InitTypeDef GPIO_InitStructure;\r\n SPI_InitTypeDef SPI_InitStructure;\r\n\r\n /* Enable the SPI periph */\r\n RCC_APB2PeriphClockCmd(LIS302DL_SPI_CLK, ENABLE);\r\n\r\n /* Enable SCK, MOSI and MISO GPIO clocks */\r\n RCC_AHB1PeriphClockCmd(LIS302DL_SPI_SCK_GPIO_CLK | LIS302DL_SPI_MISO_GPIO_CLK | LIS302DL_SPI_MOSI_GPIO_CLK, ENABLE);\r\n\r\n /* Enable CS GPIO clock */\r\n RCC_AHB1PeriphClockCmd(LIS302DL_SPI_CS_GPIO_CLK, ENABLE);\r\n \r\n /* Enable INT1 GPIO clock */\r\n RCC_AHB1PeriphClockCmd(LIS302DL_SPI_INT1_GPIO_CLK, ENABLE);\r\n \r\n /* Enable INT2 GPIO clock */\r\n RCC_AHB1PeriphClockCmd(LIS302DL_SPI_INT2_GPIO_CLK, ENABLE);\r\n\r\n GPIO_PinAFConfig(LIS302DL_SPI_SCK_GPIO_PORT, LIS302DL_SPI_SCK_SOURCE, LIS302DL_SPI_SCK_AF);\r\n GPIO_PinAFConfig(LIS302DL_SPI_MISO_GPIO_PORT, LIS302DL_SPI_MISO_SOURCE, LIS302DL_SPI_MISO_AF);\r\n GPIO_PinAFConfig(LIS302DL_SPI_MOSI_GPIO_PORT, LIS302DL_SPI_MOSI_SOURCE, LIS302DL_SPI_MOSI_AF);\r\n\r\n GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r\n GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r\n GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN;\r\n GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;\r\n\r\n /* SPI SCK pin configuration */\r\n GPIO_InitStructure.GPIO_Pin = LIS302DL_SPI_SCK_PIN;\r\n GPIO_Init(LIS302DL_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);\r\n\r\n /* SPI MOSI pin configuration */\r\n GPIO_InitStructure.GPIO_Pin = LIS302DL_SPI_MOSI_PIN;\r\n GPIO_Init(LIS302DL_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);\r\n\r\n /* SPI MISO pin configuration */\r\n GPIO_InitStructure.GPIO_Pin = LIS302DL_SPI_MISO_PIN;\r\n GPIO_Init(LIS302DL_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);\r\n\r\n /* SPI configuration -------------------------------------------------------*/\r\n SPI_I2S_DeInit(LIS302DL_SPI);\r\n SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;\r\n SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;\r\n SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;\r\n SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;\r\n SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;\r\n SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;\r\n SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;\r\n SPI_InitStructure.SPI_CRCPolynomial = 7;\r\n SPI_InitStructure.SPI_Mode = SPI_Mode_Master;\r\n SPI_Init(LIS302DL_SPI, &SPI_InitStructure);\r\n\r\n /* Enable SPI1 */\r\n SPI_Cmd(LIS302DL_SPI, ENABLE);\r\n\r\n /* Configure GPIO PIN for Lis Chip select */\r\n GPIO_InitStructure.GPIO_Pin = LIS302DL_SPI_CS_PIN;\r\n GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;\r\n GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r\n GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;\r\n GPIO_Init(LIS302DL_SPI_CS_GPIO_PORT, &GPIO_InitStructure);\r\n\r\n /* Deselect : Chip Select high */\r\n GPIO_SetBits(LIS302DL_SPI_CS_GPIO_PORT, LIS302DL_SPI_CS_PIN);\r\n \r\n /* Configure GPIO PINs to detect Interrupts */\r\n GPIO_InitStructure.GPIO_Pin = LIS302DL_SPI_INT1_PIN;\r\n GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r\n GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r\n GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;\r\n GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r\n GPIO_Init(LIS302DL_SPI_INT1_GPIO_PORT, &GPIO_InitStructure);\r\n \r\n GPIO_InitStructure.GPIO_Pin = LIS302DL_SPI_INT2_PIN;\r\n GPIO_Init(LIS302DL_SPI_INT2_GPIO_PORT, &GPIO_InitStructure);\r\n}\r\n\r\n/**\r\n * @brief Sends a Byte through the SPI interface and return the Byte received \r\n * from the SPI bus.\r\n * @param Byte : Byte send.\r\n * @retval The received byte value\r\n */\r\nstatic uint8_t LIS302DL_SendByte(uint8_t byte)\r\n{\r\n /* Loop while DR register in not emplty */\r\n LIS302DLTimeout = LIS302DL_FLAG_TIMEOUT;\r\n while (SPI_I2S_GetFlagStatus(LIS302DL_SPI, SPI_I2S_FLAG_TXE) == RESET)\r\n {\r\n if((LIS302DLTimeout--) == 0) return LIS302DL_TIMEOUT_UserCallback();\r\n }\r\n \r\n /* Send a Byte through the SPI peripheral */\r\n SPI_I2S_SendData(LIS302DL_SPI, byte);\r\n \r\n /* Wait to receive a Byte */\r\n LIS302DLTimeout = LIS302DL_FLAG_TIMEOUT;\r\n while (SPI_I2S_GetFlagStatus(LIS302DL_SPI, SPI_I2S_FLAG_RXNE) == RESET)\r\n {\r\n if((LIS302DLTimeout--) == 0) return LIS302DL_TIMEOUT_UserCallback();\r\n }\r\n \r\n /* Return the Byte read from the SPI bus */\r\n return (uint8_t)SPI_I2S_ReceiveData(LIS302DL_SPI);\r\n}\r\n\r\n#ifdef USE_DEFAULT_TIMEOUT_CALLBACK\r\n/**\r\n * @brief Basic management of the timeout situation.\r\n * @param None.\r\n * @retval None.\r\n */\r\nuint32_t LIS302DL_TIMEOUT_UserCallback(void)\r\n{\r\n /* Block communication and all processes */\r\n while (1)\r\n { \r\n }\r\n}\r\n#endif /* USE_DEFAULT_TIMEOUT_CALLBACK */\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n \r\n/**\r\n * @}\r\n */ \r\n\r\n/**\r\n * @}\r\n */ \r\n \r\n\r\n/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/Utilities/STM32F4-Discovery/stm32f4_discovery_lis302dl.h", "content": "/**\r\n ******************************************************************************\r\n * @file stm32f4_discovery_lis302dl.h\r\n * @author MCD Application Team\r\n * @version V1.1.1\r\n * @date 14-May-2012\r\n * @brief This file contains all the functions prototypes for the stm32f4_discovery_lis302dl.c\r\n * firmware driver.\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ****************************************************************************** \r\n */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F4_DISCOVERY_LIS302DL_H\r\n#define __STM32F4_DISCOVERY_LIS302DL_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n #include \"stm32f4xx.h\"\r\n\r\n/** @addtogroup Utilities\r\n * @{\r\n */\r\n \r\n/** @addtogroup STM32F4_DISCOVERY\r\n * @{\r\n */ \r\n\r\n/** @addtogroup STM32F4_DISCOVERY_LIS302DL\r\n * @{\r\n */\r\n \r\n\r\n/** @defgroup STM32F4_DISCOVERY_LIS302DL_Exported_Types\r\n * @{\r\n */\r\n \r\n/* LIS302DL struct */\r\ntypedef struct\r\n{\r\n uint8_t Power_Mode; /* Power-down/Active Mode */\r\n uint8_t Output_DataRate; /* OUT data rate 100 Hz / 400 Hz */\r\n uint8_t Axes_Enable; /* Axes enable */\r\n uint8_t Full_Scale; /* Full scale */\r\n uint8_t Self_Test; /* Self test */\r\n}LIS302DL_InitTypeDef;\r\n\r\n/* LIS302DL High Pass Filter struct */\r\ntypedef struct\r\n{\r\n uint8_t HighPassFilter_Data_Selection; /* Internal filter bypassed or data from internal filter send to output register*/\r\n uint8_t HighPassFilter_CutOff_Frequency; /* High pass filter cut-off frequency */\r\n uint8_t HighPassFilter_Interrupt; /* High pass filter enabled for Freefall/WakeUp #1 or #2 */ \r\n}LIS302DL_FilterConfigTypeDef; \r\n\r\n/* LIS302DL Interrupt struct */\r\ntypedef struct\r\n{\r\n uint8_t Latch_Request; /* Latch interrupt request into CLICK_SRC register*/\r\n uint8_t SingleClick_Axes; /* Single Click Axes Interrupts */\r\n uint8_t DoubleClick_Axes; /* Double Click Axes Interrupts */ \r\n}LIS302DL_InterruptConfigTypeDef; \r\n\r\n/**\r\n * @}\r\n */\r\n \r\n/** @defgroup STM32F4_DISCOVERY_LIS302DL_Exported_Constants\r\n * @{\r\n */\r\n\r\n/* Uncomment the following line to use the default LIS302DL_TIMEOUT_UserCallback() \r\n function implemented in stm32f4_discovery_lis302dl.c file.\r\n LIS302DL_TIMEOUT_UserCallback() function is called whenever a timeout condition \r\n occure during communication (waiting transmit data register empty flag(TXE)\r\n or waiting receive data register is not empty flag (RXNE)). */ \r\n/* #define USE_DEFAULT_TIMEOUT_CALLBACK */\r\n\r\n/* Maximum Timeout values for flags waiting loops. These timeouts are not based\r\n on accurate values, they just guarantee that the application will not remain\r\n stuck if the SPI communication is corrupted.\r\n You may modify these timeout values depending on CPU frequency and application\r\n conditions (interrupts routines ...). */ \r\n#define LIS302DL_FLAG_TIMEOUT ((uint32_t)0x1000)\r\n\r\n/**\r\n * @brief LIS302DL SPI Interface pins\r\n */\r\n#define LIS302DL_SPI SPI1\r\n#define LIS302DL_SPI_CLK RCC_APB2Periph_SPI1\r\n\r\n#define LIS302DL_SPI_SCK_PIN GPIO_Pin_5 /* PA.05 */\r\n#define LIS302DL_SPI_SCK_GPIO_PORT GPIOA /* GPIOA */\r\n#define LIS302DL_SPI_SCK_GPIO_CLK RCC_AHB1Periph_GPIOA\r\n#define LIS302DL_SPI_SCK_SOURCE GPIO_PinSource5\r\n#define LIS302DL_SPI_SCK_AF GPIO_AF_SPI1\r\n\r\n#define LIS302DL_SPI_MISO_PIN GPIO_Pin_6 /* PA.6 */\r\n#define LIS302DL_SPI_MISO_GPIO_PORT GPIOA /* GPIOA */\r\n#define LIS302DL_SPI_MISO_GPIO_CLK RCC_AHB1Periph_GPIOA\r\n#define LIS302DL_SPI_MISO_SOURCE GPIO_PinSource6\r\n#define LIS302DL_SPI_MISO_AF GPIO_AF_SPI1\r\n\r\n#define LIS302DL_SPI_MOSI_PIN GPIO_Pin_7 /* PA.7 */\r\n#define LIS302DL_SPI_MOSI_GPIO_PORT GPIOA /* GPIOA */\r\n#define LIS302DL_SPI_MOSI_GPIO_CLK RCC_AHB1Periph_GPIOA\r\n#define LIS302DL_SPI_MOSI_SOURCE GPIO_PinSource7\r\n#define LIS302DL_SPI_MOSI_AF GPIO_AF_SPI1\r\n\r\n#define LIS302DL_SPI_CS_PIN GPIO_Pin_3 /* PE.03 */\r\n#define LIS302DL_SPI_CS_GPIO_PORT GPIOE /* GPIOE */\r\n#define LIS302DL_SPI_CS_GPIO_CLK RCC_AHB1Periph_GPIOE\r\n\r\n#define LIS302DL_SPI_INT1_PIN GPIO_Pin_0 /* PE.00 */\r\n#define LIS302DL_SPI_INT1_GPIO_PORT GPIOE /* GPIOE */\r\n#define LIS302DL_SPI_INT1_GPIO_CLK RCC_AHB1Periph_GPIOE\r\n#define LIS302DL_SPI_INT1_EXTI_LINE EXTI_Line0\r\n#define LIS302DL_SPI_INT1_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE\r\n#define LIS302DL_SPI_INT1_EXTI_PIN_SOURCE EXTI_PinSource0\r\n#define LIS302DL_SPI_INT1_EXTI_IRQn EXTI0_IRQn \r\n\r\n#define LIS302DL_SPI_INT2_PIN GPIO_Pin_1 /* PE.01 */\r\n#define LIS302DL_SPI_INT2_GPIO_PORT GPIOE /* GPIOE */\r\n#define LIS302DL_SPI_INT2_GPIO_CLK RCC_AHB1Periph_GPIOE\r\n#define LIS302DL_SPI_INT2_EXTI_LINE EXTI_Line1\r\n#define LIS302DL_SPI_INT2_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE\r\n#define LIS302DL_SPI_INT2_EXTI_PIN_SOURCE EXTI_PinSource1\r\n#define LIS302DL_SPI_INT2_EXTI_IRQn EXTI1_IRQn \r\n\r\n\r\n/******************************************************************************/\r\n/*************************** START REGISTER MAPPING **************************/\r\n/******************************************************************************/\r\n\r\n/*******************************************************************************\r\n* WHO_AM_I Register: Device Identification Register\r\n* Read only register\r\n* Default value: 0x3B\r\n*******************************************************************************/\r\n#define LIS302DL_WHO_AM_I_ADDR 0x0F\r\n\r\n/*******************************************************************************\r\n* CTRL_REG1 Register: Control Register 1\r\n* Read Write register\r\n* Default value: 0x07\r\n* 7 DR: Data Rate selection.\r\n* 0 - 100 Hz output data rate\r\n* 1 - 400 Hz output data rate\r\n* 6 PD: Power Down control.\r\n* 0 - power down mode\r\n* 1 - active mode\r\n* 5 FS: Full Scale selection.\r\n* 0 - Typical measurement range 2.3\r\n* 1 - Typical measurement range 9.2\r\n* 4:3 STP-STM Self Test Enable:\r\n* STP | STM | mode\r\n* ----------------------------\r\n* 0 | 0 | Normal mode\r\n* 0 | 1 | Self Test M\r\n* 1 | 0 | Self Test P\r\n* 2 Zen: Z axis enable.\r\n* 0 - Z axis disabled\r\n* 1- Z axis enabled\r\n* 1 Yen: Y axis enable.\r\n* 0 - Y axis disabled\r\n* 1- Y axis enabled\r\n* 0 Xen: X axis enable.\r\n* 0 - X axis disabled\r\n* 1- X axis enabled\r\n********************************************************************************/\r\n#define LIS302DL_CTRL_REG1_ADDR 0x20\r\n\r\n/*******************************************************************************\r\n* CTRL_REG2 Regsiter: Control Register 2\r\n* Read Write register\r\n* Default value: 0x00\r\n* 7 SIM: SPI Serial Interface Mode Selection. \r\n* 0 - 4 wire interface\r\n* 1 - 3 wire interface\r\n* 6 BOOT: Reboot memory content\r\n* 0 - normal mode \r\n* 1 - reboot memory content\r\n* 5 Reserved\r\n* 4 FDS: Filtered data selection.\r\n* 0 - internal filter bypassed\r\n* 1 - data from internal filter sent to output register\r\n* 3 HP FF_WU2: High pass filter enabled for FreeFall/WakeUp#2.\r\n* 0 - filter bypassed\r\n* 1 - filter enabled\r\n* 2 HP FF_WU1: High pass filter enabled for FreeFall/WakeUp#1.\r\n* 0 - filter bypassed\r\n* 1 - filter enabled\r\n* 1:0 HP coeff2-HP coeff1 High pass filter cut-off frequency (ft) configuration.\r\n* ft= ODR[hz]/6*HP coeff\r\n* HP coeff2 | HP coeff1 | HP coeff\r\n* -------------------------------------------\r\n* 0 | 0 | 8\r\n* 0 | 1 | 16\r\n* 1 | 0 | 32\r\n* 1 | 1 | 64\r\n* HP coeff | ft[hz] | ft[hz] |\r\n* |ODR 100Hz | ODR 400Hz |\r\n* --------------------------------------------\r\n* 00 | 2 | 8 |\r\n* 01 | 1 | 4 |\r\n* 10 | 0.5 | 2 |\r\n* 11 | 0.25 | 1 |\r\n*******************************************************************************/\r\n#define LIS302DL_CTRL_REG2_ADDR 0x21\r\n\r\n/*******************************************************************************\r\n* CTRL_REG3 Register: Interrupt Control Register\r\n* Read Write register\r\n* Default value: 0x00\r\n* 7 IHL active: Interrupt active high/low.\r\n* 0 - active high\r\n* 1 - active low\r\n* 6 PP_OD: push-pull/open-drain.\r\n* 0 - push-pull\r\n* 1 - open-drain\r\n* 5:3 I2_CFG2 - I2_CFG0 Data signal on INT2 pad control bits\r\n* 2:0 I1_CFG2 - I1_CFG0 Data signal on INT1 pad control bits\r\n* I1(2)_CFG2 | I1(2)_CFG1 | I1(2)_CFG0 | INT1(2) Pad\r\n* ----------------------------------------------------------\r\n* 0 | 0 | 0 | GND\r\n* 0 | 0 | 1 | FreeFall/WakeUp#1\r\n* 0 | 1 | 0 | FreeFall/WakeUp#2\r\n* 0 | 1 | 1 | FreeFall/WakeUp#1 or FreeFall/WakeUp#2\r\n* 1 | 0 | 0 | Data ready\r\n* 1 | 1 | 1 | Click interrupt\r\n*******************************************************************************/\r\n#define LIS302DL_CTRL_REG3_ADDR 0x22\r\n\r\n/*******************************************************************************\r\n* HP_FILTER_RESET Register: Dummy register. Reading at this address zeroes \r\n* instantaneously the content of the internal high pass filter. If the high pass\r\n* filter is enabled all three axes are instantaneously set to 0g.\r\n* This allows to overcome the settling time of the high pass filter.\r\n* Read only register\r\n* Default value: Dummy\r\n*******************************************************************************/\r\n#define LIS302DL_HP_FILTER_RESET_REG_ADDR 0x23\r\n\r\n/*******************************************************************************\r\n* STATUS_REG Register: Status Register\r\n* Default value: 0x00\r\n* 7 ZYXOR: X, Y and Z axis data overrun.\r\n* 0: no overrun has occurred\r\n* 1: new data has overwritten the previous one before it was read\r\n* 6 ZOR: Z axis data overrun.\r\n* 0: no overrun has occurred \r\n* 1: new data for Z-axis has overwritten the previous one before it was read\r\n* 5 yOR: y axis data overrun.\r\n* 0: no overrun has occurred\r\n* 1: new data for y-axis has overwritten the previous one before it was read\r\n* 4 XOR: X axis data overrun.\r\n* 0: no overrun has occurred\r\n* 1: new data for X-axis has overwritten the previous one before it was read\r\n* 3 ZYXDA: X, Y and Z axis new data available\r\n* 0: a new set of data is not yet available\r\n* 1: a new set of data is available\r\n* 2 ZDA: Z axis new data available.\r\n* 0: a new set of data is not yet available\r\n* 1: a new data for Z axis is available\r\n* 1 YDA: Y axis new data available\r\n* 0: a new set of data is not yet available\r\n* 1: a new data for Y axis is available\r\n* 0 XDA: X axis new data available\r\n* 0: a new set of data is not yet available\r\n* 1: a new data for X axis is available\r\n*******************************************************************************/\r\n#define LIS302DL_STATUS_REG_ADDR 0x27\r\n\r\n/*******************************************************************************\r\n* OUT_X Register: X-axis output Data\r\n* Read only register\r\n* Default value: output\r\n* 7:0 XD7-XD0: X-axis output Data\r\n*******************************************************************************/\r\n#define LIS302DL_OUT_X_ADDR 0x29\r\n\r\n/*******************************************************************************\r\n* OUT_Y Register: Y-axis output Data\r\n* Read only register\r\n* Default value: output\r\n* 7:0 YD7-YD0: Y-axis output Data\r\n*******************************************************************************/\r\n#define LIS302DL_OUT_Y_ADDR 0x2B\r\n\r\n/*******************************************************************************\r\n* OUT_Z Register: Z-axis output Data\r\n* Read only register\r\n* Default value: output\r\n* 7:0 ZD7-ZD0: Z-axis output Data\r\n*******************************************************************************/\r\n#define LIS302DL_OUT_Z_ADDR 0x2D\r\n\r\n/*******************************************************************************\r\n* FF_WW_CFG_1 Register: Configuration register for Interrupt 1 source.\r\n* Read write register\r\n* Default value: 0x00\r\n* 7 AOI: AND/OR combination of Interrupt events. \r\n* 0: OR combination of interrupt events\r\n* 1: AND combination of interrupt events \r\n* 6 LIR: Latch/not latch interrupt request\r\n* 0: interrupt request not latched\r\n* 1: interrupt request latched\r\n* 5 ZHIE: Enable interrupt generation on Z high event.\r\n* 0: disable interrupt request\r\n* 1: enable interrupt request on measured accel. value higher than preset threshold\r\n* 4 ZLIE: Enable interrupt generation on Z low event.\r\n* 0: disable interrupt request\r\n* 1: enable interrupt request on measured accel. value lower than preset threshold\r\n* 3 YHIE: Enable interrupt generation on Y high event.\r\n* 0: disable interrupt request\r\n* 1: enable interrupt request on measured accel. value higher than preset threshold\r\n* 2 YLIE: Enable interrupt generation on Y low event. \r\n* 0: disable interrupt request\r\n* 1: enable interrupt request on measured accel. value lower than preset threshold\r\n* 1 XHIE: Enable interrupt generation on X high event.\r\n* 0: disable interrupt request\r\n* 1: enable interrupt request on measured accel. value higher than preset threshold\r\n* 0 XLIE: Enable interrupt generation on X low event.\r\n* 0: disable interrupt request\r\n* 1: enable interrupt request on measured accel. value lower than preset threshold\r\n*******************************************************************************/\r\n#define LIS302DL_FF_WU_CFG1_REG_ADDR 0x30\r\n\r\n/*******************************************************************************\r\n* FF_WU_SRC_1 Register: Interrupt 1 source register.\r\n* Reading at this address clears FF_WU_SRC_1 register and the FF, WU 1 interrupt\r\n* and allow the refreshment of data in the FF_WU_SRC_1 register if the latched option\r\n* was chosen.\r\n* Read only register\r\n* Default value: 0x00\r\n* 7 Reserved\r\n* 6 IA: Interrupt active.\r\n* 0: no interrupt has been generated\r\n* 1: one or more interrupts have been generated\r\n* 5 ZH: Z high. \r\n* 0: no interrupt\r\n* 1: ZH event has occurred \r\n* 4 ZL: Z low.\r\n* 0: no interrupt\r\n* 1: ZL event has occurred\r\n* 3 YH: Y high.\r\n* 0: no interrupt\r\n* 1: YH event has occurred \r\n* 2 YL: Y low.\r\n* 0: no interrupt\r\n* 1: YL event has occurred\r\n* 1 YH: X high.\r\n* 0: no interrupt\r\n* 1: XH event has occurred \r\n* 0 YL: X low.\r\n* 0: no interrupt\r\n* 1: XL event has occurred\r\n*******************************************************************************/\r\n#define LIS302DL_FF_WU_SRC1_REG_ADDR 0x31\r\n\r\n/*******************************************************************************\r\n* FF_WU_THS_1 Register: Threshold register\r\n* Read Write register\r\n* Default value: 0x00\r\n* 7 DCRM: Reset mode selection.\r\n* 0 - counter resetted\r\n* 1 - counter decremented\r\n* 6 THS6-THS0: Free-fall/wake-up threshold value.\r\n*******************************************************************************/\r\n#define LIS302DL_FF_WU_THS1_REG_ADDR 0x32\r\n\r\n/*******************************************************************************\r\n* FF_WU_DURATION_1 Register: duration Register\r\n* Read Write register\r\n* Default value: 0x00\r\n* 7:0 D7-D0 Duration value. (Duration steps and maximum values depend on the ODR chosen)\r\n ******************************************************************************/\r\n#define LIS302DL_FF_WU_DURATION1_REG_ADDR 0x33\r\n\r\n/*******************************************************************************\r\n* FF_WW_CFG_2 Register: Configuration register for Interrupt 2 source.\r\n* Read write register\r\n* Default value: 0x00\r\n* 7 AOI: AND/OR combination of Interrupt events. \r\n* 0: OR combination of interrupt events\r\n* 1: AND combination of interrupt events \r\n* 6 LIR: Latch/not latch interrupt request\r\n* 0: interrupt request not latched\r\n* 1: interrupt request latched\r\n* 5 ZHIE: Enable interrupt generation on Z high event.\r\n* 0: disable interrupt request\r\n* 1: enable interrupt request on measured accel. value higher than preset threshold\r\n* 4 ZLIE: Enable interrupt generation on Z low event.\r\n* 0: disable interrupt request\r\n* 1: enable interrupt request on measured accel. value lower than preset threshold\r\n* 3 YHIE: Enable interrupt generation on Y high event.\r\n* 0: disable interrupt request\r\n* 1: enable interrupt request on measured accel. value higher than preset threshold\r\n* 2 YLIE: Enable interrupt generation on Y low event. \r\n* 0: disable interrupt request\r\n* 1: enable interrupt request on measured accel. value lower than preset threshold\r\n* 1 XHIE: Enable interrupt generation on X high event.\r\n* 0: disable interrupt request\r\n* 1: enable interrupt request on measured accel. value higher than preset threshold\r\n* 0 XLIE: Enable interrupt generation on X low event.\r\n* 0: disable interrupt request\r\n* 1: enable interrupt request on measured accel. value lower than preset threshold\r\n*******************************************************************************/\r\n#define LIS302DL_FF_WU_CFG2_REG_ADDR 0x34\r\n\r\n/*******************************************************************************\r\n* FF_WU_SRC_2 Register: Interrupt 2 source register.\r\n* Reading at this address clears FF_WU_SRC_2 register and the FF, WU 2 interrupt\r\n* and allow the refreshment of data in the FF_WU_SRC_2 register if the latched option\r\n* was chosen.\r\n* Read only register\r\n* Default value: 0x00\r\n* 7 Reserved\r\n* 6 IA: Interrupt active.\r\n* 0: no interrupt has been generated\r\n* 1: one or more interrupts have been generated\r\n* 5 ZH: Z high. \r\n* 0: no interrupt\r\n* 1: ZH event has occurred \r\n* 4 ZL: Z low.\r\n* 0: no interrupt\r\n* 1: ZL event has occurred\r\n* 3 YH: Y high.\r\n* 0: no interrupt\r\n* 1: YH event has occurred \r\n* 2 YL: Y low.\r\n* 0: no interrupt\r\n* 1: YL event has occurred\r\n* 1 YH: X high.\r\n* 0: no interrupt\r\n* 1: XH event has occurred \r\n* 0 YL: X low.\r\n* 0: no interrupt\r\n* 1: XL event has occurred\r\n*******************************************************************************/\r\n#define LIS302DL_FF_WU_SRC2_REG_ADDR 0x35\r\n\r\n/*******************************************************************************\r\n* FF_WU_THS_2 Register: Threshold register\r\n* Read Write register\r\n* Default value: 0x00\r\n* 7 DCRM: Reset mode selection.\r\n* 0 - counter resetted\r\n* 1 - counter decremented\r\n* 6 THS6-THS0: Free-fall/wake-up threshold value.\r\n*******************************************************************************/\r\n#define LIS302DL_FF_WU_THS2_REG_ADDR 0x36\r\n\r\n/*******************************************************************************\r\n* FF_WU_DURATION_2 Register: duration Register\r\n* Read Write register\r\n* Default value: 0x00\r\n* 7:0 D7-D0 Duration value. (Duration steps and maximum values depend on the ODR chosen)\r\n ******************************************************************************/\r\n#define LIS302DL_FF_WU_DURATION2_REG_ADDR 0x37\r\n\r\n/******************************************************************************\r\n* CLICK_CFG Register: click Register\r\n* Read Write register\r\n* Default value: 0x00\r\n* 7 Reserved\r\n* 6 LIR: Latch Interrupt request.\r\n* 0: interrupt request not latched\r\n* 1: interrupt request latched\r\n* 5 Double_Z: Enable interrupt generation on double click event on Z axis.\r\n* 0: disable interrupt request\r\n* 1: enable interrupt request\r\n* 4 Single_Z: Enable interrupt generation on single click event on Z axis.\r\n* 0: disable interrupt request\r\n* 1: enable interrupt request\r\n* 3 Double_Y: Enable interrupt generation on double click event on Y axis.\r\n* 0: disable interrupt request\r\n* 1: enable interrupt request\r\n* 2 Single_Y: Enable interrupt generation on single click event on Y axis.\r\n* 0: disable interrupt request\r\n* 1: enable interrupt request\r\n* 1 Double_X: Enable interrupt generation on double click event on X axis.\r\n* 0: disable interrupt request\r\n* 1: enable interrupt request\r\n* 0 Single_y: Enable interrupt generation on single click event on X axis.\r\n* 0: disable interrupt request\r\n* 1: enable interrupt request\r\n ******************************************************************************/\r\n#define LIS302DL_CLICK_CFG_REG_ADDR 0x38\r\n\r\n/******************************************************************************\r\n* CLICK_SRC Register: click status Register\r\n* Read only register\r\n* Default value: 0x00\r\n* 7 Reserved\r\n* 6 IA: Interrupt active.\r\n* 0: no interrupt has been generated\r\n* 1: one or more interrupts have been generated\r\n* 5 Double_Z: Double click on Z axis event.\r\n* 0: no interrupt\r\n* 1: Double Z event has occurred \r\n* 4 Single_Z: Z low.\r\n* 0: no interrupt\r\n* 1: Single Z event has occurred \r\n* 3 Double_Y: Y high.\r\n* 0: no interrupt\r\n* 1: Double Y event has occurred \r\n* 2 Single_Y: Y low.\r\n* 0: no interrupt\r\n* 1: Single Y event has occurred \r\n* 1 Double_X: X high.\r\n* 0: no interrupt\r\n* 1: Double X event has occurred \r\n* 0 Single_X: X low.\r\n* 0: no interrupt\r\n* 1: Single X event has occurred \r\n*******************************************************************************/\r\n#define LIS302DL_CLICK_SRC_REG_ADDR 0x39\r\n\r\n/*******************************************************************************\r\n* CLICK_THSY_X Register: Click threshold Y and X register\r\n* Read Write register\r\n* Default value: 0x00\r\n* 7:4 THSy3-THSy0: Click threshold on Y axis, step 0.5g\r\n* 3:0 THSx3-THSx0: Click threshold on X axis, step 0.5g\r\n*******************************************************************************/\r\n#define LIS302DL_CLICK_THSY_X_REG_ADDR 0x3B\r\n\r\n/*******************************************************************************\r\n* CLICK_THSZ Register: Click threshold Z register\r\n* Read Write register\r\n* Default value: 0x00\r\n* 7:4 Reserved\r\n* 3:0 THSz3-THSz0: Click threshold on Z axis, step 0.5g\r\n*******************************************************************************/\r\n#define LIS302DL_CLICK_THSZ_REG_ADDR 0x3C\r\n\r\n/*******************************************************************************\r\n* CLICK_TimeLimit Register: Time Limit register\r\n* Read Write register\r\n* Default value: 0x00\r\n* 7:0 Dur7-Dur0: Time Limit value, step 0.5g\r\n*******************************************************************************/\r\n#define LIS302DL_CLICK_TIMELIMIT_REG_ADDR 0x3D\r\n\r\n/*******************************************************************************\r\n* CLICK_Latency Register: Latency register\r\n* Read Write register\r\n* Default value: 0x00\r\n* 7:0 Lat7-Lat0: Latency value, step 1msec\r\n*******************************************************************************/\r\n#define LIS302DL_CLICK_LATENCY_REG_ADDR 0x3E\r\n\r\n/*******************************************************************************\r\n* CLICK_Window Register: Window register\r\n* Read Write register\r\n* Default value: 0x00\r\n* 7:0 Win7-Win0: Window value, step 1msec\r\n*******************************************************************************/\r\n#define LIS302DL_CLICK_WINDOW_REG_ADDR 0x3F\r\n\r\n/******************************************************************************/\r\n/**************************** END REGISTER MAPPING ***************************/\r\n/******************************************************************************/\r\n\r\n#define LIS302DL_SENSITIVITY_2_3G 18 /* 18 mg/digit*/\r\n#define LIS302DL_SENSITIVITY_9_2G 72 /* 72 mg/digit*/\r\n\r\n/** @defgroup Data_Rate_selection \r\n * @{\r\n */\r\n#define LIS302DL_DATARATE_100 ((uint8_t)0x00)\r\n#define LIS302DL_DATARATE_400 ((uint8_t)0x80)\r\n/**\r\n * @}\r\n */\r\n \r\n/** @defgroup Power_Mode_selection \r\n * @{\r\n */\r\n#define LIS302DL_LOWPOWERMODE_POWERDOWN ((uint8_t)0x00)\r\n#define LIS302DL_LOWPOWERMODE_ACTIVE ((uint8_t)0x40)\r\n/**\r\n * @}\r\n */\r\n \r\n/** @defgroup Full_Scale_selection \r\n * @{\r\n */\r\n#define LIS302DL_FULLSCALE_2_3 ((uint8_t)0x00)\r\n#define LIS302DL_FULLSCALE_9_2 ((uint8_t)0x20)\r\n/**\r\n * @}\r\n */\r\n \r\n/** @defgroup Self_Test_selection \r\n * @{\r\n */\r\n#define LIS302DL_SELFTEST_NORMAL ((uint8_t)0x00)\r\n#define LIS302DL_SELFTEST_P ((uint8_t)0x10)\r\n#define LIS302DL_SELFTEST_M ((uint8_t)0x08)\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup Direction_XYZ_selection \r\n * @{\r\n */\r\n#define LIS302DL_X_ENABLE ((uint8_t)0x01)\r\n#define LIS302DL_Y_ENABLE ((uint8_t)0x02)\r\n#define LIS302DL_Z_ENABLE ((uint8_t)0x04)\r\n#define LIS302DL_XYZ_ENABLE ((uint8_t)0x07)\r\n/**\r\n * @}\r\n */\r\n \r\n /** @defgroup SPI_Serial_Interface_Mode_selection \r\n * @{\r\n */\r\n#define LIS302DL_SERIALINTERFACE_4WIRE ((uint8_t)0x00)\r\n#define LIS302DL_SERIALINTERFACE_3WIRE ((uint8_t)0x80)\r\n/**\r\n * @}\r\n */ \r\n\r\n /** @defgroup Boot_Mode_selection \r\n * @{\r\n */\r\n#define LIS302DL_BOOT_NORMALMODE ((uint8_t)0x00)\r\n#define LIS302DL_BOOT_REBOOTMEMORY ((uint8_t)0x40)\r\n/**\r\n * @}\r\n */ \r\n\r\n /** @defgroup Filtered_Data_Selection_Mode_selection \r\n * @{\r\n */\r\n#define LIS302DL_FILTEREDDATASELECTION_BYPASSED ((uint8_t)0x00)\r\n#define LIS302DL_FILTEREDDATASELECTION_OUTPUTREGISTER ((uint8_t)0x20)\r\n/**\r\n * @}\r\n */ \r\n \r\n /** @defgroup High_Pass_Filter_Interrupt_selection \r\n * @{\r\n */ \r\n#define LIS302DL_HIGHPASSFILTERINTERRUPT_OFF ((uint8_t)0x00)\r\n#define LIS302DL_HIGHPASSFILTERINTERRUPT_1 ((uint8_t)0x04)\r\n#define LIS302DL_HIGHPASSFILTERINTERRUPT_2 ((uint8_t)0x08)\r\n#define LIS302DL_HIGHPASSFILTERINTERRUPT_1_2 ((uint8_t)0x0C)\r\n/**\r\n * @}\r\n */ \r\n \r\n /** @defgroup High_Pass_Filter_selection \r\n * @{\r\n */\r\n#define LIS302DL_HIGHPASSFILTER_LEVEL_0 ((uint8_t)0x00)\r\n#define LIS302DL_HIGHPASSFILTER_LEVEL_1 ((uint8_t)0x01)\r\n#define LIS302DL_HIGHPASSFILTER_LEVEL_2 ((uint8_t)0x02)\r\n#define LIS302DL_HIGHPASSFILTER_LEVEL_3 ((uint8_t)0x03)\r\n/**\r\n * @}\r\n */\r\n\r\n\r\n/** @defgroup latch_Interrupt_Request_selection \r\n * @{\r\n */\r\n#define LIS302DL_INTERRUPTREQUEST_NOTLATCHED ((uint8_t)0x00)\r\n#define LIS302DL_INTERRUPTREQUEST_LATCHED ((uint8_t)0x40)\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup Click_Interrupt_XYZ_selection \r\n * @{\r\n */\r\n#define LIS302DL_CLICKINTERRUPT_XYZ_DISABLE ((uint8_t)0x00)\r\n#define LIS302DL_CLICKINTERRUPT_X_ENABLE ((uint8_t)0x01)\r\n#define LIS302DL_CLICKINTERRUPT_Y_ENABLE ((uint8_t)0x04)\r\n#define LIS302DL_CLICKINTERRUPT_Z_ENABLE ((uint8_t)0x10)\r\n#define LIS302DL_CLICKINTERRUPT_XYZ_ENABLE ((uint8_t)0x15)\r\n/**\r\n * @}\r\n */\r\n\r\n/** @defgroup Double_Click_Interrupt_XYZ_selection \r\n * @{\r\n */\r\n#define LIS302DL_DOUBLECLICKINTERRUPT_XYZ_DISABLE ((uint8_t)0x00)\r\n#define LIS302DL_DOUBLECLICKINTERRUPT_X_ENABLE ((uint8_t)0x02)\r\n#define LIS302DL_DOUBLECLICKINTERRUPT_Y_ENABLE ((uint8_t)0x08)\r\n#define LIS302DL_DOUBLECLICKINTERRUPT_Z_ENABLE ((uint8_t)0x20)\r\n#define LIS302DL_DOUBLECLICKINTERRUPT_XYZ_ENABLE ((uint8_t)0x2A)\r\n/**\r\n * @}\r\n */\r\n/**\r\n * @}\r\n */ \r\n \r\n/** @defgroup STM32F4_DISCOVERY_LIS302DL_Exported_Macros\r\n * @{\r\n */\r\n#define LIS302DL_CS_LOW() GPIO_ResetBits(LIS302DL_SPI_CS_GPIO_PORT, LIS302DL_SPI_CS_PIN)\r\n#define LIS302DL_CS_HIGH() GPIO_SetBits(LIS302DL_SPI_CS_GPIO_PORT, LIS302DL_SPI_CS_PIN)\r\n/**\r\n * @}\r\n */ \r\n\r\n/** @defgroup STM32F4_DISCOVERY_LIS302DL_Exported_Functions\r\n * @{\r\n */ \r\nvoid LIS302DL_Init(LIS302DL_InitTypeDef *LIS302DL_InitStruct);\r\nvoid LIS302DL_InterruptConfig(LIS302DL_InterruptConfigTypeDef *LIS302DL_InterruptConfigStruct);\r\nvoid LIS302DL_FilterConfig(LIS302DL_FilterConfigTypeDef *LIS302DL_FilterConfigStruct);\r\nvoid LIS302DL_LowpowerCmd(uint8_t LowPowerMode);\r\nvoid LIS302DL_FullScaleCmd(uint8_t FS_value);\r\nvoid LIS302DL_DataRateCmd(uint8_t DataRateValue);\r\nvoid LIS302DL_RebootCmd(void);\r\nvoid LIS302DL_ReadACC(int32_t* out);\r\nvoid LIS302DL_Write(uint8_t* pBuffer, uint8_t WriteAddr, uint16_t NumByteToWrite);\r\nvoid LIS302DL_Read(uint8_t* pBuffer, uint8_t ReadAddr, uint16_t NumByteToRead);\r\n\r\n/* USER Callbacks: This is function for which prototype only is declared in\r\n MEMS accelerometre driver and that should be implemented into user applicaiton. */ \r\n/* LIS302DL_TIMEOUT_UserCallback() function is called whenever a timeout condition \r\n occure during communication (waiting transmit data register empty flag(TXE)\r\n or waiting receive data register is not empty flag (RXNE)).\r\n You can use the default timeout callback implementation by uncommenting the \r\n define USE_DEFAULT_TIMEOUT_CALLBACK in stm32f4_discovery_lis302dl.h file.\r\n Typically the user implementation of this callback should reset MEMS peripheral\r\n and re-initialize communication or in worst case reset all the application. */\r\nuint32_t LIS302DL_TIMEOUT_UserCallback(void);\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F4_DISCOVERY_LIS302DL_H */\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */ \r\n\r\n\r\n/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/spi.elf.launch", "content": "\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n" }, { "path": "figure-simulator-discovery/src/main.c", "content": "/**\r\n ******************************************************************************\r\n * @file main.c\r\n * @author MCD Application Team\r\n * @version V1.0.0\r\n * @date 19-September-2011\r\n * @brief Main program body\r\n ******************************************************************************\r\n * @attention\r\n *\r\n * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r\n * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r\n * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r\n * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r\n * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r\n * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r\n *\r\n *

© COPYRIGHT 2011 STMicroelectronics

\r\n ******************************************************************************\r\n */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n//#include \"main.h\"\r\n#include \"stm32f4_discovery.h\"\r\n//#include \"stm32f4xx_it.c\"\r\nuint8_t flag;\r\n//#include \r\n/** @addtogroup STM32F4-Discovery_Demo\r\n * @{\r\n */\r\nint i;\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n\r\n\r\n//#define CLK GPIO_Pin_11\r\n//#define ADDRESS GPIO_Pin_10\r\n//#define E GPIO_Pin_9\r\nEXTI_InitTypeDef EXTI_InitStructure;\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n\r\n\r\n//uint32_t a = 0;\r\n//int i;\r\nint index;\r\nint started = 0;\r\n/* Private function prototypes -----------------------------------------------*/\r\n\r\nGPIO_InitTypeDef GPIO_InitStructure;\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\nvoid EXTILine0_Config(void)\r\n{\r\n\r\n GPIO_InitTypeDef GPIO_InitStructure;\r\n NVIC_InitTypeDef NVIC_InitStructure;\r\n\r\n /* Enable GPIOA clock */\r\n RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);\r\n /* Enable SYSCFG clock */\r\n RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);\r\n\r\n /* Configure PA0 pin as input floating */\r\n GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r\n GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;\r\n GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;\r\n GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;\r\n GPIO_Init(GPIOA, &GPIO_InitStructure);\r\n\r\n GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r\n GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r\n GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;\r\n GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1;\r\n GPIO_Init(GPIOA, &GPIO_InitStructure);\r\n\r\n /* Connect EXTI Line0 to PA0 pin */\r\n SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOA, EXTI_PinSource0);\r\n\r\n /* Configure EXTI Line0 */\r\n EXTI_InitStructure.EXTI_Line = EXTI_Line0;\r\n EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;\r\n EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;\r\n EXTI_InitStructure.EXTI_LineCmd = ENABLE;\r\n EXTI_Init(&EXTI_InitStructure);\r\n\r\n /* Enable and set EXTI Line0 Interrupt to the lowest priority */\r\n NVIC_InitStructure.NVIC_IRQChannel = EXTI0_IRQn;\r\n NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x01;\r\n NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x01;\r\n NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r\n NVIC_Init(&NVIC_InitStructure);\r\n\r\n SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOA, EXTI_PinSource1);\r\n\r\n /* Configure EXTI Line0 */\r\n EXTI_InitStructure.EXTI_Line = EXTI_Line1;\r\n EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;\r\n EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;\r\n EXTI_InitStructure.EXTI_LineCmd = ENABLE;\r\n EXTI_Init(&EXTI_InitStructure);\r\n\r\n /* Enable and set EXTI Line0 Interrupt to the lowest priority */\r\n NVIC_InitStructure.NVIC_IRQChannel = EXTI1_IRQn;\r\n NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x02;\r\n NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x01;\r\n NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r\n NVIC_Init(&NVIC_InitStructure);\r\n\r\n\r\n\r\n}\r\n\r\nint loops = 0;\r\nint hit = 0;\r\nint q;\r\nint as[2000];\r\nint read = 1;\r\nuint32_t a = 0;\r\nint acount = 0;\r\nuint8_t val;\r\nuint8_t c;\r\n\r\nuint8_t *vs[8];\r\nuint8_t v1[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0x29, 0xc0, 0xff, 0xca, 0x9f, 0x28, 0xc0, 0xff, 0xca, 0xa7, 0x67, 0xc0, 0xff, 0xda, 0xa8, 0xa7, 0xc0, 0xff, 0xda, 0xaa, 0xa3, 0xc0, 0xff, 0x2a, 0xaa, 0x9f, 0xc0, 0xff, 0x69, 0xaa, 0x8f, 0xc0, 0xff, 0x65, 0xaa, 0x8f, 0xc0, 0xfc, 0xa4, 0xaa, 0x7f, 0xc0, 0xfd, 0xa0, 0xaa, 0x7f, 0xc0, 0xf2, 0xa3, 0x6a, 0x7f, 0xc0, 0xf2, 0x9f, 0x6a, 0x3f, 0xc0, 0xfa, 0x8f, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0};\r\nuint8_t v2[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0x6a, 0x7f, 0xc0, 0xff, 0xfd, 0xaa, 0x3f, 0xc0, 0xff, 0xf2, 0xaa, 0x3f, 0xc0, 0xff, 0xf6, 0xa9, 0xff, 0xc0, 0xff, 0xda, 0xa9, 0xff, 0xc0, 0xff, 0x2a, 0xa9, 0xff, 0xc0, 0xff, 0x6a, 0xa8, 0xff, 0xc0, 0xfc, 0xa4, 0xa8, 0xff, 0xc0, 0xfd, 0xa0, 0xa7, 0xff, 0xc0, 0xf2, 0x91, 0xa7, 0xff, 0xc0, 0xfa, 0x82, 0xa7, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0};\r\nuint8_t v3[] = { 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfa, 0xaa, 0xab, 0xc0, 0xff, 0xfa, 0xaa, 0xaf, 0xc0, 0xff, 0xfa, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xea, 0xbf, 0xff, 0xc0, 0xff, 0xea, 0xff, 0xff, 0xc0, 0xff, 0xea, 0xff, 0xff, 0xc0, 0xff, 0xaa, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0};\r\n\r\nuint8_t v4[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xaa, 0xff, 0xc0, 0xff, 0xff, 0xab, 0xff, 0xc0, 0xff, 0xfe, 0xab, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xff, 0xff, 0xc0, 0xff, 0xea, 0xff, 0xff, 0xc0, 0xff, 0xeb, 0xff, 0xff, 0xc0, 0xff, 0xeb, 0xff, 0xff, 0xc0, 0xff, 0xab, 0xea, 0xff, 0xc0, 0xff, 0xaa, 0xaa, 0xff, 0xc0, 0xff, 0xaa, 0xaa, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0 };\r\nuint8_t v5[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xea, 0xff, 0xc0, 0xff, 0xff, 0xea, 0xff, 0xc0, 0xff, 0xff, 0xeb, 0xff, 0xc0, 0xff, 0xff, 0xeb, 0xff, 0xc0, 0xff, 0xff, 0xab, 0xff, 0xc0, 0xff, 0xff, 0xaf, 0xff, 0xc0, 0xff, 0xff, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xbf, 0xff, 0xc0, 0xff, 0xfe, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0};\r\n\r\nuint8_t v6[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xaa, 0xaa, 0xc0, 0xff, 0xff, 0xaa, 0xaa, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfa, 0xaa, 0xff, 0xc0, 0xff, 0xfa, 0xab, 0xff, 0xc0, 0xff, 0xfa, 0xff, 0xff, 0xc0, 0xff, 0xea, 0xff, 0xff, 0xc0, 0xff, 0xea, 0xff, 0xff, 0xc0, 0xff, 0xea, 0xab, 0xff, 0xc0, 0xff, 0xaa, 0xab, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0};\r\nuint8_t v7[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xeb, 0xff, 0xc0, 0xff, 0xff, 0xab, 0xff, 0xc0, 0xff, 0xfe, 0xab, 0xff, 0xc0, 0xfe, 0xaa, 0xaa, 0xab, 0xc0, 0xff, 0xaa, 0xaa, 0xbf, 0xc0, 0xff, 0xea, 0xab, 0xff, 0xc0, 0xff, 0xea, 0xab, 0xff, 0xc0, 0xff, 0xaa, 0xab, 0xff, 0xc0, 0xff, 0xaf, 0xab, 0xff, 0xc0, 0xfe, 0xff, 0xeb, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0};\r\n\r\n\r\n\r\n\r\nuint8_t v[] =\r\n{ 0x0a, 0xaa, 0x55, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0-f\r\n 0x00, 0xaa, 0x55, 0x04, 0x0d, 0x04, 0x00, 0x00, 0x11, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //10-f\r\n\r\n // 0x00, 0xaa, 0x55, 0x04, 0x0d, 0x04, 0x04, 0x01, 0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n// 0x40, 0x00, 0x00, 0x55, 0x55, 0x55, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,\r\n 0x40, 0x00, 0x00, 0xc4, 0x00, 0x00, 0xdc, 0x00, 0x00, 0x0f, 0x01, 0x00, 0x91, 0x01, 0x00, 0x0d, //20\r\n\r\n\r\n 0x02, 0x00, 0x89, 0x02, 0x00, 0xd1, 0x02, 0x00, 0x1f, 0x06, 0x00, 0x67, 0x0f, 0x00, 0x67, 0x0f,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //40\r\n 0xf0, 0x03, 0x00, 0xf0, 0x03, 0x00, 0xf0, 0x03, 0x00, 0xf0, 0x03, 0x00, 0xd9, 0x13, 0x00, 0x3f,\r\n 0x14, 0x00, 0xa5, 0x14, 0x00, 0x0b, 0x15, 0x00, 0x71, 0x15, 0x00, 0xd7, 0x15, 0x00, 0x3d, 0x16,\r\n 0x00, 0xa3, 0x16, 0x00, 0x09, 0x17, 0x00, 0x6f, 0x17, 0x00, 0xd5, 0x17, 0x00, 0x3b, 0x18, 0x00,\r\n 0xa1, 0x18, 0x00, 0x07, 0x19, 0x00, 0x6d, 0x19, 0x00, 0xd3, 0x19, 0x00, 0x39, 0x1a, 0x00, 0x9f, //80\r\n 0x1a, 0x00, 0x05, 0x1b, 0x00, 0x6b, 0x1b, 0x00, 0xd1, 0x1b, 0x00, 0x37, 0x1c, 0x00, 0x9d, 0x1c, //90\r\n 0x00, 0x13, 0x1e, 0x00, 0x72, 0x05, 0x00, 0x72, 0x05, 0x00, 0x75, 0x22, 0x00, 0xeb, 0x23, 0x00,\r\n 0x61, 0x25, 0x00, 0xd7, 0x26, 0x00, 0xf4, 0x06, 0x00, 0xf4, 0x06, 0x00, 0x89, 0x29, 0x00, 0x64, //b0\r\n 0x2a, 0x00, 0xa2, 0x2a, 0x00, 0xe0, 0x2a, 0x00, 0x1e, 0x2b, 0x00, 0x5c, 0x2b, 0x00, 0xce, 0x00, //c0\r\n 0x00, 0xce, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x44, 0x12, 0x34, 0x30, 0x1f,// max:0x50, 0x20, //d0\r\n\r\n\r\n 0x2a, 0xaa, 0xaa, 0xaa, 0xa8, 0x01, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x2a, 0xaa, 0xaa, 0xaa, //e0 NATALIE PIC for bg\r\n 0xa8, 0x00, 0x6a, 0xaa, 0xaa, 0xaa, 0xa9, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0xa9, 0x00, 0x2a, 0xaa,\r\n 0xaa, 0xa0, 0x00, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0xa9, 0x00, 0x0a, 0x6a, 0xa8, 0x00, 0x00, 0x00, //100\r\n 0x2a, 0xaa, 0xaa, 0xaa, 0xa9, 0x00, 0x00, 0x2a, 0xaa, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xaa, 0xaa,\r\n 0xa8, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n 0x2a, 0xaa, 0xa4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0x80, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6a, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x6a, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0x80, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x10,\r\n 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0x90, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00,\r\n 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0xaa, 0xaa, 0xa0, 0x00, //1a0\r\n 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x01, 0xaa, 0xaa, 0xa4, 0x00, 0x00, 0x00, 0x1a, 0xa0,\r\n 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0xa8, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x00, 0x02,\r\n 0xaa, 0xaa, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xaa, 0xaa, 0xaa, 0x00,\r\n 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x01, 0x00, 0x00,\r\n 0x00, 0x00, 0x00, 0x0a, 0x6a, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1a,\r\n 0x2a, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0xa4, 0x00, 0x00, 0x2a, 0x2a, 0xaa, 0xaa, 0xa0, //200\r\n 0x04, 0x2a, 0xaa, 0xaa, 0xa9, 0x00, 0x00, 0x6a, 0x2a, 0xaa, 0xaa, 0xa4, 0x0a, 0xaa, 0xaa, 0xa9,\r\n 0x00, 0x00, 0x00, 0xaa, 0x2a, 0xaa, 0xaa, 0xa8, 0x00, 0x1a, 0xaa, 0x80, 0x00, 0x00, 0x01, 0xaa,\r\n 0x1a, 0xaa, 0xaa, 0xaa, 0x00, 0x0a, 0xaa, 0x80, 0x00, 0x00, 0x02, 0xaa, 0x0a, 0xaa, 0xaa, 0xaa,\r\n 0x80, 0x0a, 0xaa, 0x90, 0x00, 0x00, 0x06, 0xaa, 0x0a, 0xaa, 0xaa, 0xaa, 0x90, 0x01, 0xaa, 0xa4,\r\n 0x00, 0x00, 0x1a, 0xaa, 0x8a, 0xaa, 0x86, 0xa8, 0x24, 0x00, 0xaa, 0x50, 0x00, 0x00, 0x6a, 0xaa, //250\r\n\r\n\r\n\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //260\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf4, 0x06, 0x00, 0xf4, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, //300\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //350\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //3f0\r\n\r\n\r\n\r\n\r\n\r\n 0x30, 0x1f, 0x2a, 0xaa, 0xaa, 0xaa, 0xa8, 0x01, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x2a, 0xaa, 0xaa, 0xaa, //400 NATALIE PIC for SPRITE\r\n 0xa8, 0x00, 0x6a, 0xaa, 0xaa, 0xaa, 0xa9, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0xa9, 0x00, 0x2a, 0xaa,\r\n 0xaa, 0xa0, 0x00, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0xa9, 0x00, 0x0a, 0x6a, 0xa8, 0x00, 0x00, 0x00, //422\r\n 0x2a, 0xaa, 0xaa, 0xaa, 0xa9, 0x00, 0x00, 0x2a, 0xaa, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xaa, 0xaa,\r\n 0xa8, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n 0x2a, 0xaa, 0xa4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0x80, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6a, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x6a, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0x80, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x10, //4a2\r\n 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0x90, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00,\r\n 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0xaa, 0xaa, 0xa0, 0x00, //3c2\r\n 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x01, 0xaa, 0xaa, 0xa4, 0x00, 0x00, 0x00, 0x1a, 0xa0,\r\n 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0xa8, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x00, 0x02,\r\n 0xaa, 0xaa, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xaa, 0xaa, 0xaa, 0x00,\r\n 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x01, 0x00, 0x00, //502\r\n 0x00, 0x00, 0x00, 0x0a, 0x6a, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1a,\r\n 0x2a, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0xa4, 0x00, 0x00, 0x2a, 0x2a, 0xaa, 0xaa, 0xa0, //522\r\n 0x04, 0x2a, 0xaa, 0xaa, 0xa9, 0x00, 0x00, 0x6a, 0x2a, 0xaa, 0xaa, 0xa4, 0x0a, 0xaa, 0xaa, 0xa9,\r\n 0x00, 0x00, 0x00, 0xaa, 0x2a, 0xaa, 0xaa, 0xa8, 0x00, 0x1a, 0xaa, 0x80, 0x00, 0x00, 0x01, 0xaa,\r\n 0x1a, 0xaa, 0xaa, 0xaa, 0x00, 0x0a, 0xaa, 0x80, 0x00, 0x00, 0x02, 0xaa, 0x0a, 0xaa, 0xaa, 0xaa,\r\n 0x80, 0x0a, 0xaa, 0x90, 0x00, 0x00, 0x06, 0xaa, 0x0a, 0xaa, 0xaa, 0xaa, 0x90, 0x01, 0xaa, 0xa4,\r\n 0x00, 0x00, 0x1a, 0xaa, 0x8a, 0xaa, 0x86, 0xa8, 0x24, 0x00, 0xaa, 0x50, 0x00, 0x00, 0x6a, 0xaa, //572\r\n\r\n 0x30, 0x1f, 0x2a, 0xaa, 0xaa, 0xaa, 0xa8, 0x01, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x2a, 0xaa, 0xaa, 0xaa, //582 NATALIE PIC GAME\r\n 0xa8, 0x00, 0x6a, 0xaa, 0xaa, 0xaa, 0xa9, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0xa9, 0x00, 0x2a, 0xaa,//594\r\n 0xaa, 0xa0, 0x00, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0xa9, 0x00, 0x0a, 0x6a, 0xa8, 0x00, 0x00, 0x00, //5a4\r\n 0x2a, 0xaa, 0xaa, 0xaa, 0xa9, 0x00, 0x00, 0x2a, 0xaa, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xaa, 0xaa,\r\n 0xa8, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00,//5c4\r\n 0x00, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n 0x2a, 0xaa, 0xa4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0x80, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6a, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x6a, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //604\r\n 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0x80, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x10, //\r\n 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0x90, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00,\r\n 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0xaa, 0xaa, 0xa0, 0x00, //\r\n 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x01, 0xaa, 0xaa, 0xa4, 0x00, 0x00, 0x00, 0x1a, 0xa0,\r\n 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0xa8, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x00, 0x02,\r\n 0xaa, 0xaa, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xaa, 0xaa, 0xaa, 0x00,\r\n 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x01, 0x00, 0x00,\r\n 0x00, 0x00, 0x00, 0x0a, 0x6a, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1a,\r\n 0x2a, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0xa4, 0x00, 0x00, 0x2a, 0x2a, 0xaa, 0xaa, 0xa0, //6a4\r\n 0x04, 0x2a, 0xaa, 0xaa, 0xa9, 0x00, 0x00, 0x6a, 0x2a, 0xaa, 0xaa, 0xa4, 0x0a, 0xaa, 0xaa, 0xa9,\r\n 0x00, 0x00, 0x00, 0xaa, 0x2a, 0xaa, 0xaa, 0xa8, 0x00, 0x1a, 0xaa, 0x80, 0x00, 0x00, 0x01, 0xaa,//\r\n 0x1a, 0xaa, 0xaa, 0xaa, 0x00, 0x0a, 0xaa, 0x80, 0x00, 0x00, 0x02, 0xaa, 0x0a, 0xaa, 0xaa, 0xaa,\r\n 0x80, 0x0a, 0xaa, 0x90, 0x00, 0x00, 0x06, 0xaa, 0x0a, 0xaa, 0xaa, 0xaa, 0x90, 0x01, 0xaa, 0xa4,\r\n 0x00, 0x00, 0x1a, 0xaa, 0x8a, 0xaa, 0x86, 0xa8, 0x24, 0x00, 0xaa, 0x50, 0x00, 0x00, 0x6a, 0xaa, // 6f4\r\n\r\n\r\n 0x30, 0x1f, 0x2a, 0xaa, 0xaa, 0xaa, 0xa8, 0x01, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x2a, 0xaa, 0xaa, 0xaa, //704 GAME TITLES\r\n 0xa8, 0x00, 0x6a, 0xaa, 0xaa, 0xaa, 0xa9, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0xa9, 0x00, 0x2a, 0xaa,//716\r\n 0xaa, 0xa0, 0x00, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0xa9, 0x00, 0x0a, 0x6a, 0xa8, 0x00, 0x00, 0x00, //\r\n 0x2a, 0xaa, 0xaa, 0xaa, 0xa9, 0x00, 0x00, 0x2a, 0xaa, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xaa, 0xaa,\r\n 0xa8, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00,//746\r\n 0x00, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n 0x2a, 0xaa, 0xa4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0x80, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6a, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x6a, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //604\r\n 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0x80, 0x00,\r\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x10, //\r\n 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0x90, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00,\r\n 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0xaa, 0xaa, 0xa0, 0x00, //\r\n 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x01, 0xaa, 0xaa, 0xa4, 0x00, 0x00, 0x00, 0x1a, 0xa0,\r\n 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0xa8, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x00, 0x02,\r\n 0xaa, 0xaa, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xaa, 0xaa, 0xaa, 0x00,\r\n 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x01, 0x00, 0x00,\r\n 0x00, 0x00, 0x00, 0x0a, 0x6a, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1a,\r\n 0x2a, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0xa4, 0x00, 0x00, 0x2a, 0x2a, 0xaa, 0xaa, 0xa0, //6a4\r\n 0x04, 0x2a, 0xaa, 0xaa, 0xa9, 0x00, 0x00, 0x6a, 0x2a, 0xaa, 0xaa, 0xa4, 0x0a, 0xaa, 0xaa, 0xa9,\r\n 0x00, 0x00, 0x00, 0xaa, 0x2a, 0xaa, 0xaa, 0xa8, 0x00, 0x1a, 0xaa, 0x80, 0x00, 0x00, 0x01, 0xaa,//\r\n 0x1a, 0xaa, 0xaa, 0xaa, 0x00, 0x0a, 0xaa, 0x80, 0x00, 0x00, 0x02, 0xaa, 0x0a, 0xaa, 0xaa, 0xaa,\r\n 0x80, 0x0a, 0xaa, 0x90, 0x00, 0x00, 0x06, 0xaa, 0x0a, 0xaa, 0xaa, 0xaa, 0x90, 0x01, 0xaa, 0xa4,\r\n 0x00, 0x00, 0x1a, 0xaa, 0x8a, 0xaa, 0x86, 0xa8, 0x24, 0x00, 0xaa, 0x50, 0x00, 0x00, 0x6a, 0xaa, // 6f4\r\n\r\n\r\n\r\n\r\n // 0x00, 0xcf, 0xff, 0x00, 0x00, 0x00, 0x00, 0xcf, 0xff, 0x00, 0x00, 0x00, 0x00,\r\n // 0xcf, 0xff, 0x00, 0x00, 0xc, 0xff, 0xff, 0xff, 0x00, 0x00, 0xff, 0xff,\r\n // 0xff, 0xff, 0x00, 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n //0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n // 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n // 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF,\r\n 0x00, 0x00, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF,\r\n 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFA, 0xAA,\r\n 0xAB, 0xC0, 0xFF, 0xE5, 0x55, 0x5A, 0xC0, 0x00, 0xE5, 0x55, 0x5A, 0xC0, 0xFF, 0x95, 0x55, 0x66,\r\n 0xC0, 0xFF, 0xAA, 0xAA, 0xA6, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x8A, 0x28, 0x26, 0xC0,\r\n 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x8A, 0x28, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF,\r\n 0x80, 0x00, 0x26, 0xC0, 0xFF, 0xAA, 0xAA, 0xAB, 0xC0, 0x11, 0x15, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0,\r\n\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0x00, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF,\r\n 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFA, 0xAA, 0xAB, 0xC0, 0xFF, 0xE5, 0x55,\r\n 0x5A, 0xC0, 0xFF, 0xE5, 0x55, 0x5A, 0xC0, 0xFF, 0x95, 0x55, 0x66, 0xC0, 0xFF, 0xAA, 0xAA, 0xA6,\r\n 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x8A, 0x28, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0,\r\n 0xFF, 0x8A, 0x28, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF,\r\n 0xAA, 0xAA, 0xAB, 0xC0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r\n 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};// 0x70, 0x2c, 0x00, 0x82, 0x2c, 0x00, 0x90, 0x2c, 0x00, 0x9e, 0x2c, 0x00, 0xb0, 0x2c, 0x00, 0xc2, 0x2c, 0x00, 0xd4, 0x2c, 0x00, 0xe6, 0x2c, 0x00, 0xe9, 0x2c, 0x00, 0x1b, 0x2d, 0x00, 0x4d, 0x2d, 0x00, 0x7f, 0x2d, 0x00, 0xb1, 0x2d, 0x00, 0xe3, 0x2d, 0x00, 0x15, 0x2e, 0x00, 0x27, 0x2e, 0x00, 0x39, 0x2e, 0x00, 0x4b, 0x2e, 0x00, 0x6c, 0x2e, 0x00, 0x73, 0x2e, 0x00, 0xb5, 0x2e, 0x00, 0xf7, 0x2e, 0x00, 0x21, 0x2f, 0x00, 0x5f, 0x2f, 0x00, 0xc1, 0x2f, 0x00, 0x02, 0x00, 0x06, 0x03, 0x04, 0x09, 0x0a, 0x05, 0x08, 0x07, 0x00, 0x00, 0x58, 0x00, 0x00, 0x32, 0x00, 0x00, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x10, 0x00, 0x00, 0x08, 0x00, 0x00, 0x50, 0x04, 0x00, 0x30, 0x02, 0x00, 0x20, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00, 0x50, 0x08, 0x00, 0x50, 0x11, 0x00, 0x00, 0x00, 0x28, 0x00, 0x40, 0x15, 0x00, 0x60, 0x12, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x45, 0x00, 0x00, 0x35, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x22, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00, 0x22, 0x00, 0x00, 0x13, 0x00, 0x01, 0x00, 0x02, 0x00, 0x50, 0x01, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x04, 0xff, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x02, 0xff, 0x01, 0x01, 0x00, 0x1e, 0x01, 0x00, 0x03, 0xff, 0x01, 0x01, 0x00, 0x2d, 0x01, 0x00, 0x04, 0xfe, 0x01, 0x01, 0x00, 0x3c, 0x01, 0x00, 0x05, 0xfe, 0x01, 0x01, 0x00, 0x4b, 0x02, 0x00, 0x06, 0xfe, 0x02, 0x02, 0x00, 0x5a, 0x02, 0x00, 0x07, 0xfd, 0x02, 0x02, 0x00, 0x63, 0x02, 0x00, 0x08, 0xfd, 0x02, 0x02, 0x00, 0x64, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0x00, 0x02, 0x04, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x02, 0xff, 0x01, 0x01, 0x00, 0x0f, 0x01, 0x00, 0x03, 0xff, 0x01, 0x01, 0x00, 0x19, 0x01, 0x00, 0x04, 0xfe, 0x01, 0x01, 0x00, 0x23, 0x01, 0x00, 0x05, 0xfe, 0x01, 0x02, 0x00, 0x2d, 0x02, 0x00, 0x06, 0xfe, 0x02, 0x02, 0x00, 0x37, 0x02, 0x00, 0x07, 0xfd, 0x02, 0x02, 0x00, 0x40, 0x02, 0x00, 0x08, 0xfd, 0x02, 0x02, 0x00, 0x41, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xc4, 0x2f, 0x00, 0xff, 0xff, 0xff, 0x06, 0x30, 0x00, 0x48, 0x30, 0x00, 0x8a, 0x30, 0x00, 0xcc, 0x30, 0x00, 0x0e, 0x31, 0x00, 0x50, 0x31, 0x00, 0x92, 0x31, 0x00, 0xd4, 0x31, 0x00, 0x16, 0x32, 0x00, 0xff, 0xff, 0xff, 0x58, 0x32, 0x00, 0xff, 0xff, 0xff, 0xba, 0x32, 0x00, 0x1c, 0x33, 0x00, 0x7e, 0x33, 0x00, 0xe0, 0x33, 0x00, 0x42, 0x34, 0x00, 0xa4, 0x34, 0x00, 0x06, 0x35, 0x00, 0x68, 0x35, 0x00, 0xca, 0x35, 0x00, 0xff, 0xff, 0xff, 0x2c, 0x36, 0x00, 0x3e, 0x36, 0x00, 0x80, 0x36, 0x00, 0xc2, 0x36, 0x00, 0x04, 0x37, 0x00, 0x46, 0x37, 0x00, 0x88, 0x37, 0x00, 0xca, 0x37, 0x00, 0x24, 0x38, 0x00, 0x9d, 0x38, 0x00, 0xf9, 0x38, 0x00, 0x7d, 0x39, 0x00, 0xd7, 0x39, 0x00, 0x50, 0x3a, 0x00, 0xac, 0x3a, 0x00, 0x30, 0x3b, 0x00, 0x72, 0x3b, 0x00, 0xb4, 0x3b, 0x00, 0xf6, 0x3b, 0x00, 0x38, 0x3c, 0x00, 0x7a, 0x3c, 0x00, 0xbc, 0x3c, 0x00, 0xfe, 0x3c, 0x00, 0x40, 0x3d, 0x00, 0x3a, 0x3e, 0x00, 0x34, 0x3f, 0x00, 0x2e, 0x40, 0x00, 0x28, 0x41, 0x00, 0x22, 0x42, 0x00, 0x98, 0x43, 0x00, 0xea, 0x43, 0x00, 0x3c, 0x44, 0x00, 0x8e, 0x44, 0x00, 0xe0, 0x44, 0x00, 0x32, 0x45, 0x00, 0x84, 0x45, 0x00, 0x7e, 0x46, 0x00, 0x78, 0x47, 0x00, 0xba, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0x76, 0x48, 0x00, 0xf0, 0x48, 0x00, 0x6a, 0x49, 0x00, 0xe4, 0x49, 0x00, 0x5e, 0x4a, 0x00, 0xd8, 0x4a, 0x00, 0x52, 0x4b, 0x00, 0xcc, 0x4b, 0x00, 0x46, 0x4c, 0x00, 0xc0, 0x4c, 0x00, 0x3a, 0x4d, 0x00, 0xb4, 0x4d, 0x00, 0x2e, 0x4e, 0x00, 0xa8, 0x4e, 0x00, 0x22, 0x4f, 0x00, 0x9c, 0x4f, 0x00, 0x16, 0x50, 0x00, 0x90, 0x50, 0x00, 0x0a, 0x51, 0x00, 0x84, 0x51, 0x00, 0xfe, 0x51, 0x00, 0x78, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0x6c, 0x53, 0x00, 0xe6, 0x53, 0x00, 0x60, 0x54, 0x00, 0xda, 0x54, 0x00, 0x54, 0x55, 0x00, 0xce, 0x55, 0x00, 0x48, 0x56, 0x00, 0xc2, 0x56, 0x00, 0x3c, 0x57, 0x00, 0xb6, 0x57, 0x00, 0x30, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0x24, 0x59, 0x00, 0x9e, 0x59, 0x00, 0x18, 0x5a, 0x00, 0x92, 0x5a, 0x00, 0x0c, 0x5b, 0x00, 0x86, 0x5b, 0x00, 0x00, 0x5c, 0x00, 0x7a, 0x5c, 0x00, 0xf4, 0x5c, 0x00, 0x6e, 0x5d, 0x00, 0xe8, 0x5d, 0x00, 0x62, 0x5e, 0x00, 0xdc, 0x5e, 0x00, 0x56, 0x5f, 0x00, 0xd0, 0x5f, 0x00, 0x4a, 0x60, 0x00, 0xc4, 0x60, 0x00, 0x3e, 0x61, 0x00, 0xb8, 0x61, 0x00, 0x32, 0x62, 0x00, 0xac, 0x62, 0x00, 0x26, 0x63, 0x00, 0xa0, 0x63, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x94, 0x64, 0x00, 0x0e, 0x65, 0x00, 0x88, 0x65, 0x00, 0x02, 0x66, 0x00, 0x7c, 0x66, 0x00, 0xf6, 0x66, 0x00, 0x70, 0x67, 0x00, 0xea, 0x67, 0x00, 0x64, 0x68, 0x00, 0xde, 0x68, 0x00, 0x58, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0x4c, 0x6a, 0x00, 0xc6, 0x6a, 0x00, 0x40, 0x6b, 0x00, 0xba, 0x6b, 0x00, 0x34, 0x6c, 0x00, 0xae, 0x6c, 0x00, 0x28, 0x6d, 0x00, 0xa2, 0x6d, 0x00, 0x1c, 0x6e, 0x00, 0x96, 0x6e, 0x00, 0x10, 0x6f, 0x00, 0x8a, 0x6f, 0x00, 0x04, 0x70, 0x00, 0x7e, 0x70, 0x00, 0xf8, 0x70, 0x00, 0x72, 0x71, 0x00, 0xec, 0x71, 0x00, 0x66, 0x72, 0x00, 0xe0, 0x72, 0x00, 0x5a, 0x73, 0x00, 0xd4, 0x73, 0x00, 0x4e, 0x74, 0x00, 0xc8, 0x74, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0xbc, 0x75, 0x00, 0x36, 0x76, 0x00, 0xb0, 0x76, 0x00, 0x2a, 0x77, 0x00, 0xa4, 0x77, 0x00, 0x1e, 0x78, 0x00, 0x98, 0x78, 0x00, 0x12, 0x79, 0x00, 0x8c, 0x79, 0x00, 0x06, 0x7a, 0x00, 0x80, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0x74, 0x7b, 0x00, 0xe2, 0x7b, 0x00, 0x50, 0x7c, 0x00, 0xbe, 0x7c, 0x00, 0x2c, 0x7d, 0x00, 0x9a, 0x7d, 0x00, 0x08, 0x7e, 0x00, 0x76, 0x7e, 0x00, 0xe4, 0x7e, 0x00, 0x52, 0x7f, 0x00, 0xc0, 0x7f, 0x00, 0x2e, 0x80, 0x00, 0x9c, 0x80, 0x00, 0x0a, 0x81, 0x00, 0x78, 0x81, 0x00, 0xe6, 0x81, 0x00, 0x54, 0x82, 0x00, 0xc2, 0x82, 0x00, 0x30, 0x83, 0x00, 0x9e, 0x83, 0x00, 0x0c, 0x84, 0x00, 0x7a, 0x84, 0x00, 0xe8, 0x84, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0xc4, 0x85, 0x00, 0x32, 0x86, 0x00, 0xa0, 0x86, 0x00, 0x0e, 0x87, 0x00, 0x7c, 0x87, 0x00, 0xea, 0x87, 0x00, 0x58, 0x88, 0x00, 0xc6, 0x88, 0x00, 0x34, 0x89, 0x00, 0xa2, 0x89, 0x00, 0x10, 0x8a, 0x00, 0x7e, 0x8a, 0x00, 0xec, 0x8a, 0x00, 0x2e, 0x8b, 0x00, 0xac, 0x8b, 0x00, 0x2a, 0x8c, 0x00, 0xa8, 0x8c, 0x00, 0x26, 0x8d, 0x00, 0xa4, 0x8d, 0x00, 0x22, 0x8e, 0x00, 0xa0, 0x8e, 0x00, 0x1e, 0x8f, 0x00, 0x60, 0x8f, 0x00, 0xa2, 0x8f, 0x00, 0xe4, 0x8f, 0x00, 0x13, 0x90, 0x00, 0x42, 0x90, 0x00, 0x65, 0x90, 0x00, 0x88, 0x90, 0x00, 0xab, 0x90, 0x00, 0xce, 0x90, 0x00, 0xf1, 0x90, 0x00, 0x57, 0x91, 0x00, 0xbd, 0x91, 0x00, 0x23, 0x92, 0x00, 0x89, 0x92, 0x00, 0xef, 0x92, 0x00, 0x55, 0x93, 0x00, 0xbb, 0x93, 0x00, 0x21, 0x94, 0x00, 0x87, 0x94, 0x00, 0xed, 0x94, 0x00, 0x53, 0x95, 0x00, 0xb9, 0x95, 0x00, 0x1f, 0x96, 0x00, 0x85, 0x96, 0x00, 0xeb, 0x96, 0x00, 0x51, 0x97, 0x00, 0xb7, 0x97, 0x00, 0x1d, 0x98, 0x00, 0x83, 0x98, 0x00, 0xe9, 0x98, 0x00, 0x4f, 0x99, 0x00, 0xb5, 0x99, 0x00, 0x1b, 0x9a, 0x00, 0x81, 0x9a, 0x00, 0xe7, 0x9a, 0x00, 0x4d, 0x9b, 0x00, 0xb3, 0x9b, 0x00, 0x19, 0x9c, 0x00, 0x7f, 0x9c, 0x00, 0xe5, 0x9c, 0x00, 0x4b, 0x9d, 0x00, 0xb1, 0x9d, 0x00, 0x17, 0x9e, 0x00, 0x7d, 0x9e, 0x00, 0xe3, 0x9e, 0x00, 0x49, 0x9f, 0x00, 0xaf, 0x9f, 0x00, 0x15, 0xa0, 0x00, 0x7b, 0xa0, 0x00, 0xe1, 0xa0, 0x00, 0x47, 0xa1, 0x00, 0xad, 0xa1, 0x00, 0x13, 0xa2, 0x00, 0x79, 0xa2, 0x00, 0xdf, 0xa2, 0x00, 0x45, 0xa3, 0x00, 0xab, 0xa3, 0x00, 0x11, 0xa4, 0x00, 0x77, 0xa4, 0x00, 0xdd, 0xa4, 0x00, 0x43, 0xa5, 0x00, 0xa9, 0xa5, 0x00, 0x0f, 0xa6, 0x00, 0x75, 0xa6, 0x00, 0xdb, 0xa6, 0x00, 0x41, 0xa7, 0x00, 0xa7, 0xa7, 0x00, 0x0d, 0xa8, 0x00, 0x73, 0xa8, 0x00, 0xd9, 0xa8, 0x00, 0x3f, 0xa9, 0x00, 0xa5, 0xa9, 0x00, 0x0b, 0xaa, 0x00, 0x71, 0xaa, 0x00, 0xd7, 0xaa, 0x00, 0x3d, 0xab, 0x00, 0xa3, 0xab, 0x00, 0x09, 0xac, 0x00, 0x6f, 0xac, 0x00, 0xd5, 0xac, 0x00, 0x3b, 0xad, 0x00, 0xa1, 0xad, 0x00, 0x07, 0xae, 0x00, 0x6d, 0xae, 0x00, 0xd3, 0xae, 0x00, 0x39, 0xaf, 0x00, 0x9f, 0xaf, 0x00, 0x05, 0xb0, 0x00, 0x6b, 0xb0, 0x00, 0xd1, 0xb0, 0x00, 0x37, 0xb1, 0x00, 0x9d, 0xb1, 0x00, 0x03, 0xb2, 0x00, 0x69, 0xb2, 0x00, 0xcf, 0xb2, 0x00, 0x35, 0xb3, 0x00, 0x9b, 0xb3, 0x00, 0x01, 0xb4, 0x00, 0x67, 0xb4, 0x00, 0xcd, 0xb4, 0x00, 0x33, 0xb5, 0x00, 0x99, 0xb5, 0x00, 0xff, 0xb5, 0x00, 0x65, 0xb6, 0x00, 0xcb, 0xb6, 0x00, 0x31, 0xb7, 0x00, 0x97, 0xb7, 0x00, 0xfd, 0xb7, 0x00, 0x63, 0xb8, 0x00, 0xc9, 0xb8, 0x00, 0x2f, 0xb9, 0x00, 0x95, 0xb9, 0x00, 0xfb, 0xb9, 0x00, 0x61, 0xba, 0x00, 0xc7, 0xba, 0x00, 0x2d, 0xbb, 0x00, 0x93, 0xbb, 0x00, 0xf9, 0xbb, 0x00, 0x5f, 0xbc, 0x00, 0xc5, 0xbc, 0x00, 0x2b, 0xbd, 0x00, 0x91, 0xbd, 0x00, 0xf7, 0xbd, 0x00, 0x5d, 0xbe, 0x00, 0xc3, 0xbe, 0x00, 0x29, 0xbf, 0x00, 0x8f, 0xbf, 0x00, 0xf5, 0xbf, 0x00, 0x5b, 0xc0, 0x00, 0xc1, 0xc0, 0x00, 0x27, 0xc1, 0x00, 0x8d, 0xc1, 0x00, 0xf3, 0xc1, 0x00, 0x59, 0xc2, 0x00, 0xbf, 0xc2, 0x00, 0x25, 0xc3, 0x00, 0x8b, 0xc3, 0x00, 0xf1, 0xc3, 0x00, 0x57, 0xc4, 0x00, 0xbd, 0xc4, 0x00, 0x23, 0xc5, 0x00, 0x89, 0xc5, 0x00, 0xef, 0xc5, 0x00, 0x55, 0xc6, 0x00, 0xbb, 0xc6, 0x00, 0x21, 0xc7, 0x00, 0x87, 0xc7, 0x00, 0xed, 0xc7, 0x00, 0x53, 0xc8, 0x00, 0xb9, 0xc8, 0x00, 0x1f, 0xc9, 0x00, 0x85, 0xc9, 0x00, 0xeb, 0xc9, 0x00, 0x51, 0xca, 0x00, 0xb7, 0xca, 0x00, 0x1d, 0xcb, 0x00, 0x83, 0xcb, 0x00, 0xe9, 0xcb, 0x00, 0x4f, 0xcc, 0x00, 0xb5, 0xcc, 0x00, 0x1b, 0xcd, 0x00, 0x81, 0xcd, 0x00, 0xe7, 0xcd, 0x00, 0x4d, 0xce, 0x00, 0xb3, 0xce, 0x00, 0x19, 0xcf, 0x00, 0x7f, 0xcf, 0x00, 0xe5, 0xcf, 0x00, 0x4b, 0xd0, 0x00, 0xb1, 0xd0, 0x00, 0x17, 0xd1, 0x00, 0x7d, 0xd1, 0x00, 0xe3, 0xd1, 0x00, 0x49, 0xd2, 0x00, 0xaf, 0xd2, 0x00, 0x15, 0xd3, 0x00, 0x7b, 0xd3, 0x00, 0xe1, 0xd3, 0x00, 0x47, 0xd4, 0x00, 0xad, 0xd4, 0x00, 0x13, 0xd5, 0x00, 0x79, 0xd5, 0x00, 0xdf, 0xd5, 0x00, 0x45, 0xd6, 0x00, 0xab, 0xd6, 0x00, 0x11, 0xd7, 0x00, 0x77, 0xd7, 0x00, 0xdd, 0xd7, 0x00, 0x43, 0xd8, 0x00, 0xa9, 0xd8, 0x00, 0x0f, 0xd9, 0x00, 0x75, 0xd9, 0x00, 0xdb, 0xd9, 0x00, 0x41, 0xda, 0x00, 0xa7, 0xda, 0x00, 0x0d, 0xdb, 0x00, 0x73, 0xdb, 0x00, 0xd9, 0xdb, 0x00, 0x3f, 0xdc, 0x00, 0xa5, 0xdc, 0x00, 0x0b, 0xdd, 0x00, 0x71, 0xdd, 0x00, 0xd7, 0xdd, 0x00, 0x3d, 0xde, 0x00, 0xa3, 0xde, 0x00, 0x09, 0xdf, 0x00, 0x6f, 0xdf, 0x00, 0xd5, 0xdf, 0x00, 0x3b, 0xe0, 0x00, 0xa1, 0xe0, 0x00, 0x07, 0xe1, 0x00, 0x6d, 0xe1, 0x00, 0xd3, 0xe1, 0x00, 0x39, 0xe2, 0x00, 0x9f, 0xe2, 0x00, 0x05, 0xe3, 0x00, 0x6b, 0xe3, 0x00, 0xd1, 0xe3, 0x00, 0x37, 0xe4, 0x00, 0x9d, 0xe4, 0x00, 0x03, 0xe5, 0x00, 0x69, 0xe5, 0x00, 0xcf, 0xe5, 0x00, 0x35, 0xe6, 0x00, 0x9b, 0xe6, 0x00, 0x01, 0xe7, 0x00, 0x67, 0xe7, 0x00, 0xcd, 0xe7, 0x00, 0x33, 0xe8, 0x00, 0x99, 0xe8, 0x00, 0xff, 0xe8, 0x00, 0x65, 0xe9, 0x00, 0xcb, 0xe9, 0x00, 0x31, 0xea, 0x00, 0x97, 0xea, 0x00, 0xfd, 0xea, 0x00, 0x63, 0xeb, 0x00, 0xc9, 0xeb, 0x00, 0x2f, 0xec, 0x00, 0x95, 0xec, 0x00, 0xfb, 0xec, 0x00, 0x61, 0xed, 0x00, 0xc7, 0xed, 0x00, 0x2d, 0xee, 0x00, 0x93, 0xee, 0x00, 0xf9, 0xee, 0x00, 0x5f, 0xef, 0x00, 0xc5, 0xef, 0x00, 0x2b, 0xf0, 0x00, 0x91, 0xf0, 0x00, 0xf7, 0xf0, 0x00, 0x5d, 0xf1, 0x00, 0xc3, 0xf1, 0x00, 0x29, 0xf2, 0x00, 0x8f, 0xf2, 0x00, 0xf5, 0xf2, 0x00, 0x5b, 0xf3, 0x00, 0xc1, 0xf3, 0x00, 0x27, 0xf4, 0x00, 0x8d, 0xf4, 0x00, 0xf3, 0xf4, 0x00, 0x59, 0xf5, 0x00, 0xbf, 0xf5, 0x00, 0x25, 0xf6, 0x00, 0x8b, 0xf6, 0x00, 0xf1, 0xf6, 0x00, 0x57, 0xf7, 0x00, 0xbd, 0xf7, 0x00, 0x23, 0xf8, 0x00, 0x89, 0xf8, 0x00, 0xef, 0xf8, 0x00, 0x55, 0xf9, 0x00, 0xbb, 0xf9, 0x00, 0x21, 0xfa, 0x00, 0x87, 0xfa, 0x00, 0xed, 0xfa, 0x00, 0x53, 0xfb, 0x00, 0xb9, 0xfb, 0x00, 0x1f, 0xfc, 0x00, 0x85, 0xfc, 0x00, 0xeb, 0xfc, 0x00, 0x51, 0xfd, 0x00, 0xb7, 0xfd, 0x00, 0x1d, 0xfe, 0x00, 0x83, 0xfe, 0x00, 0xe9, 0xfe, 0x00, 0x4f, 0xff, 0x00, 0xb5, 0xff, 0x00, 0x1b, 0x00, 0x01, 0x81, 0x00, 0x01, 0xe7, 0x00, 0x01, 0x4d, 0x01, 0x01, 0xb3, 0x01, 0x01, 0x19, 0x02, 0x01, 0x7f, 0x02, 0x01, 0xe5, 0x02, 0x01, 0x4b, 0x03, 0x01, 0xb1, 0x03, 0x01, 0x17, 0x04, 0x01, 0x7d, 0x04, 0x01, 0xe3, 0x04, 0x01, 0x49, 0x05, 0x01, 0xaf, 0x05, 0x01, 0x15, 0x06, 0x01, 0x7b, 0x06, 0x01, 0xe1, 0x06, 0x01, 0x47, 0x07, 0x01, 0xad, 0x07, 0x01, 0x13, 0x08, 0x01, 0x79, 0x08, 0x01, 0xdf, 0x08, 0x01, 0x45, 0x09, 0x01, 0xab, 0x09, 0x01, 0x11, 0x0a, 0x01, 0x77, 0x0a, 0x01, 0xdd, 0x0a, 0x01, 0x43, 0x0b, 0x01, 0xa9, 0x0b, 0x01, 0x0f, 0x0c, 0x01, 0x75, 0x0c, 0x01, 0xdb, 0x0c, 0x01, 0x41, 0x0d, 0x01, 0xa7, 0x0d, 0x01, 0x0d, 0x0e, 0x01, 0x73, 0x0e, 0x01, 0xd9, 0x0e, 0x01, 0x3f, 0x0f, 0x01, 0xa5, 0x0f, 0x01, 0x0b, 0x10, 0x01, 0x71, 0x10, 0x01, 0xd7, 0x10, 0x01, 0x3d, 0x11, 0x01, 0xa3, 0x11, 0x01, 0x09, 0x12, 0x01, 0x6f, 0x12, 0x01, 0xd5, 0x12, 0x01, 0x3b, 0x13, 0x01, 0xa1, 0x13, 0x01, 0x07, 0x14, 0x01, 0x6d, 0x14, 0x01, 0xd3, 0x14, 0x01, 0x39, 0x15, 0x01, 0x9f, 0x15, 0x01, 0x05, 0x16, 0x01, 0x6b, 0x16, 0x01, 0xd1, 0x16, 0x01, 0x37, 0x17, 0x01, 0x9d, 0x17, 0x01, 0x03, 0x18, 0x01, 0x69, 0x18, 0x01, 0xcf, 0x18, 0x01, 0x35, 0x19, 0x01, 0x9b, 0x19, 0x01, 0x01, 0x1a, 0x01, 0x67, 0x1a, 0x01, 0xcd, 0x1a, 0x01, 0x33, 0x1b, 0x01, 0x99, 0x1b, 0x01, 0xff, 0x1b, 0x01, 0x65, 0x1c, 0x01, 0xcb, 0x1c, 0x01, 0x31, 0x1d, 0x01, 0x97, 0x1d, 0x01, 0xfd, 0x1d, 0x01, 0x63, 0x1e, 0x01, 0xc9, 0x1e, 0x01, 0x2f, 0x1f, 0x01, 0x95, 0x1f, 0x01, 0xfb, 0x1f, 0x01, 0x61, 0x20, 0x01, 0xc7, 0x20, 0x01, 0x2d, 0x21, 0x01, 0x93, 0x21, 0x01, 0xf9, 0x21, 0x01, 0x5f, 0x22, 0x01, 0xc5, 0x22, 0x01, 0x2b, 0x23, 0x01, 0x91, 0x23, 0x01, 0xf7, 0x23, 0x01, 0x5d, 0x24, 0x01, 0xc3, 0x24, 0x01, 0x29, 0x25, 0x01, 0x8f, 0x25, 0x01, 0xf5, 0x25, 0x01, 0x5b, 0x26, 0x01, 0xc1, 0x26, 0x01, 0x27, 0x27, 0x01, 0x8d, 0x27, 0x01, 0xf3, 0x27, 0x01, 0x59, 0x28, 0x01, 0xbf, 0x28, 0x01, 0x25, 0x29, 0x01, 0x8b, 0x29, 0x01, 0xf1, 0x29, 0x01, 0x57, 0x2a, 0x01, 0xbd, 0x2a, 0x01, 0x23, 0x2b, 0x01, 0x89, 0x2b, 0x01, 0xef, 0x2b, 0x01, 0x55, 0x2c, 0x01, 0xbb, 0x2c, 0x01, 0x21, 0x2d, 0x01, 0x87, 0x2d, 0x01, 0xed, 0x2d, 0x01, 0x53, 0x2e, 0x01, 0xb9, 0x2e, 0x01, 0x1f, 0x2f, 0x01, 0x85, 0x2f, 0x01, 0xeb, 0x2f, 0x01, 0x51, 0x30, 0x01, 0xb7, 0x30, 0x01, 0x1d, 0x31, 0x01, 0x83, 0x31, 0x01, 0xe9, 0x31, 0x01, 0x4f, 0x32, 0x01, 0xb5, 0x32, 0x01, 0x1b, 0x33, 0x01, 0x81, 0x33, 0x01, 0xe7, 0x33, 0x01, 0x4d, 0x34, 0x01, 0xb3, 0x34, 0x01, 0x19, 0x35, 0x01, 0x7f, 0x35, 0x01, 0xe5, 0x35, 0x01, 0x4b, 0x36, 0x01, 0xb1, 0x36, 0x01, 0x17, 0x37, 0x01, 0x7d, 0x37, 0x01, 0xe3, 0x37, 0x01, 0x49, 0x38, 0x01, 0xaf, 0x38, 0x01, 0x15, 0x39, 0x01, 0x7b, 0x39, 0x01, 0xe1, 0x39, 0x01, 0x47, 0x3a, 0x01, 0xad, 0x3a, 0x01, 0x13, 0x3b, 0x01, 0x79, 0x3b, 0x01, 0xdf, 0x3b, 0x01, 0x45, 0x3c, 0x01, 0xab, 0x3c, 0x01, 0x11, 0x3d, 0x01, 0x77, 0x3d, 0x01, 0xdd, 0x3d, 0x01, 0x43, 0x3e, 0x01, 0xa9, 0x3e, 0x01, 0x0f, 0x3f, 0x01, 0x75, 0x3f, 0x01, 0xdb, 0x3f, 0x01, 0x41, 0x40, 0x01, 0xa7, 0x40, 0x01, 0x0d, 0x41, 0x01, 0x73, 0x41, 0x01, 0xd9, 0x41, 0x01, 0x3f, 0x42, 0x01, 0xa5, 0x42, 0x01, 0x0b, 0x43, 0x01, 0x71, 0x43, 0x01, 0xd7, 0x43, 0x01, 0x3d, 0x44, 0x01, 0xa3, 0x44, 0x01, 0x09, 0x45, 0x01, 0x6f, 0x45, 0x01, 0xd5, 0x45, 0x01, 0x3b, 0x46, 0x01, 0xa1, 0x46, 0x01, 0x07, 0x47, 0x01, 0x6d, 0x47, 0x01, 0xd3, 0x47, 0x01, 0x39, 0x48, 0x01, 0x9f, 0x48, 0x01, 0x05, 0x49, 0x01, 0x6b, 0x49, 0x01, 0xd1, 0x49, 0x01, 0x37, 0x4a, 0x01, 0x9d, 0x4a, 0x01, 0x03, 0x4b, 0x01, 0x69, 0x4b, 0x01, 0xcf, 0x4b, 0x01, 0x35, 0x4c, 0x01, 0x9b, 0x4c, 0x01, 0x01, 0x4d, 0x01, 0x67, 0x4d, 0x01, 0xcd, 0x4d, 0x01, 0x33, 0x4e, 0x01, 0x99, 0x4e, 0x01, 0xff, 0x4e, 0x01, 0x65, 0x4f, 0x01, 0xcb, 0x4f, 0x01, 0x31, 0x50, 0x01, 0x97, 0x50, 0x01, 0xfd, 0x50, 0x01, 0x63, 0x51, 0x01, 0xc9, 0x51, 0x01, 0x2f, 0x52, 0x01, 0x95, 0x52, 0x01, 0xfb, 0x52, 0x01, 0x61, 0x53, 0x01, 0xc7, 0x53, 0x01, 0x2d, 0x54, 0x01, 0x93, 0x54, 0x01, 0xf9, 0x54, 0x01, 0x5f, 0x55, 0x01, 0xc5, 0x55, 0x01, 0x2b, 0x56, 0x01, 0x91, 0x56, 0x01, 0xf7, 0x56, 0x01, 0x5d, 0x57, 0x01, 0xc3, 0x57, 0x01, 0x29, 0x58, 0x01, 0x8f, 0x58, 0x01, 0xf5, 0x58, 0x01, 0x5b, 0x59, 0x01, 0xc1, 0x59, 0x01, 0x27, 0x5a, 0x01, 0x8d, 0x5a, 0x01, 0xf3, 0x5a, 0x01, 0x59, 0x5b, 0x01, 0xbf, 0x5b, 0x01, 0x25, 0x5c, 0x01, 0x8b, 0x5c, 0x01, 0xf1, 0x5c, 0x01, 0x57, 0x5d, 0x01, 0xbd, 0x5d, 0x01, 0x23, 0x5e, 0x01, 0x89, 0x5e, 0x01, 0xef, 0x5e, 0x01, 0x55, 0x5f, 0x01, 0xbb, 0x5f, 0x01, 0x21, 0x60, 0x01, 0x87, 0x60, 0x01, 0xed, 0x60, 0x01, 0x53, 0x61, 0x01, 0xb9, 0x61, 0x01, 0x1f, 0x62, 0x01, 0x85, 0x62, 0x01, 0xeb, 0x62, 0x01, 0x51, 0x63, 0x01, 0xb7, 0x63, 0x01, 0x1d, 0x64, 0x01, 0x83, 0x64, 0x01, 0xe9, 0x64, 0x01, 0x4f, 0x65, 0x01, 0xb5, 0x65, 0x01, 0x1b, 0x66, 0x01, 0x81, 0x66, 0x01, 0xe7, 0x66, 0x01, 0x4d, 0x67, 0x01, 0xb3, 0x67, 0x01, 0x19, 0x68, 0x01, 0x7f, 0x68, 0x01, 0xe5, 0x68, 0x01, 0x4b, 0x69, 0x01, 0xb1, 0x69, 0x01, 0x17, 0x6a, 0x01, 0x7d, 0x6a, 0x01, 0xe3, 0x6a, 0x01, 0x49, 0x6b, 0x01, 0xaf, 0x6b, 0x01, 0x15, 0x6c, 0x01, 0x7b, 0x6c, 0x01, 0xe1, 0x6c, 0x01, 0x47, 0x6d, 0x01, 0xad, 0x6d, 0x01, 0x13, 0x6e, 0x01, 0x79, 0x6e, 0x01, 0xdf, 0x6e, 0x01, 0x45, 0x6f, 0x01, 0xab, 0x6f, 0x01, 0x11, 0x70, 0x01, 0x77, 0x70, 0x01, 0xdd, 0x70, 0x01, 0x43, 0x71, 0x01, 0xa9, 0x71, 0x01, 0x0f, 0x72, 0x01, 0x75, 0x72, 0x01, 0xdb, 0x72, 0x01, 0x41, 0x73, 0x01, 0xa7, 0x73, 0x01, 0x0d, 0x74, 0x01, 0x73, 0x74, 0x01, 0xd9, 0x74, 0x01, 0x3f, 0x75, 0x01, 0xa5, 0x75, 0x01, 0x0b, 0x76, 0x01, 0x71, 0x76, 0x01, 0xd7, 0x76, 0x01, 0x3d, 0x77, 0x01, 0xa3, 0x77, 0x01, 0x09, 0x78, 0x01, 0x6f, 0x78, 0x01, 0xd5, 0x78, 0x01, 0x3b, 0x79, 0x01, 0xa1, 0x79, 0x01, 0x07, 0x7a, 0x01, 0x6d, 0x7a, 0x01, 0xd3, 0x7a, 0x01, 0x39, 0x7b, 0x01, 0x9f, 0x7b, 0x01, 0x05, 0x7c, 0x01, 0x6b, 0x7c, 0x01, 0xd1, 0x7c, 0x01, 0x37, 0x7d, 0x01, 0x9d, 0x7d, 0x01, 0x03, 0x7e, 0x01, 0x69, 0x7e, 0x01, 0xcf, 0x7e, 0x01, 0x35, 0x7f, 0x01, 0x9b, 0x7f, 0x01, 0x01, 0x80, 0x01, 0x67, 0x80, 0x01, 0xcd, 0x80, 0x01, 0x33, 0x81, 0x01, 0x99, 0x81, 0x01, 0xff, 0x81, 0x01, 0x65, 0x82, 0x01, 0xcb, 0x82, 0x01, 0x31, 0x83, 0x01, 0x97, 0x83, 0x01, 0xfd, 0x83, 0x01, 0x63, 0x84, 0x01, 0xc9, 0x84, 0x01, 0x2f, 0x85, 0x01, 0x95, 0x85, 0x01, 0xfb, 0x85, 0x01, 0x61, 0x86, 0x01, 0xc7, 0x86, 0x01, 0x2d, 0x87, 0x01, 0x93, 0x87, 0x01, 0xf9, 0x87, 0x01, 0x5f, 0x88, 0x01, 0xc5, 0x88, 0x01, 0x2b, 0x89, 0x01, 0x91, 0x89, 0x01, 0xf7, 0x89, 0x01, 0x5d, 0x8a, 0x01, 0xc3, 0x8a, 0x01, 0x29, 0x8b, 0x01, 0x8f, 0x8b, 0x01, 0xf5, 0x8b, 0x01, 0x5b, 0x8c, 0x01, 0xc1, 0x8c, 0x01, 0x27, 0x8d, 0x01, 0x8d, 0x8d, 0x01, 0xf3, 0x8d, 0x01, 0x59, 0x8e, 0x01, 0xbf, 0x8e, 0x01, 0x25, 0x8f, 0x01, 0x8b, 0x8f, 0x01, 0xf1, 0x8f, 0x01, 0x57, 0x90, 0x01, 0xbd, 0x90, 0x01, 0x23, 0x91, 0x01, 0x89, 0x91, 0x01, 0xef, 0x91, 0x01, 0x55, 0x92, 0x01, 0xbb, 0x92, 0x01, 0x21, 0x93, 0x01, 0x87, 0x93, 0x01, 0xed, 0x93, 0x01, 0x53, 0x94, 0x01, 0xb9, 0x94, 0x01, 0x1f, 0x95, 0x01, 0x85, 0x95, 0x01, 0xeb, 0x95, 0x01, 0x51, 0x96, 0x01, 0xb7, 0x96, 0x01, 0x1d, 0x97, 0x01, 0x83, 0x97, 0x01, 0xe9, 0x97, 0x01, 0x4f, 0x98, 0x01, 0xb5, 0x98, 0x01, 0x1b, 0x99, 0x01, 0x81, 0x99, 0x01, 0xe7, 0x99, 0x01, 0x4d, 0x9a, 0x01, 0xb3, 0x9a, 0x01, 0x19, 0x9b, 0x01, 0x7f, 0x9b, 0x01, 0xe5, 0x9b, 0x01, 0x4b, 0x9c, 0x01, 0xb1, 0x9c, 0x01, 0x17, 0x9d, 0x01, 0x7d, 0x9d, 0x01, 0xe3, 0x9d, 0x01, 0x49, 0x9e, 0x01, 0xaf, 0x9e, 0x01, 0x15, 0x9f, 0x01, 0x7b, 0x9f, 0x01, 0xe1, 0x9f, 0x01, 0x47, 0xa0, 0x01, 0xad, 0xa0, 0x01, 0x13, 0xa1, 0x01, 0x79, 0xa1, 0x01, 0xdf, 0xa1, 0x01, 0x45, 0xa2, 0x01, 0xab, 0xa2, 0x01, 0x11, 0xa3, 0x01, 0x77, 0xa3, 0x01, 0xdd, 0xa3, 0x01, 0x43, 0xa4, 0x01, 0xa9, 0xa4, 0x01, 0x0f, 0xa5, 0x01, 0x75, 0xa5, 0x01, 0xdb, 0xa5, 0x01, 0x41, 0xa6, 0x01, 0xa7, 0xa6, 0x01, 0x0d, 0xa7, 0x01, 0x73, 0xa7, 0x01, 0xd9, 0xa7, 0x01, 0x3f, 0xa8, 0x01, 0xa5, 0xa8, 0x01, 0x0b, 0xa9, 0x01, 0x71, 0xa9, 0x01, 0xd7, 0xa9, 0x01, 0x3d, 0xaa, 0x01, 0xa3, 0xaa, 0x01, 0x09, 0xab, 0x01, 0x6f, 0xab, 0x01, 0xd5, 0xab, 0x01, 0x3b, 0xac, 0x01, 0xa1, 0xac, 0x01, 0x07, 0xad, 0x01, 0x6d, 0xad, 0x01, 0xd3, 0xad, 0x01, 0x39, 0xae, 0x01, 0x9f, 0xae, 0x01, 0x05, 0xaf, 0x01, 0x6b, 0xaf, 0x01, 0xd1, 0xaf, 0x01, 0x37, 0xb0, 0x01, 0x9d, 0xb0, 0x01, 0x03, 0xb1, 0x01, 0x69, 0xb1, 0x01, 0xcf, 0xb1, 0x01, 0x35, 0xb2, 0x01, 0x9b, 0xb2, 0x01, 0x01, 0xb3, 0x01, 0x67, 0xb3, 0x01, 0xcd, 0xb3, 0x01, 0x33, 0xb4, 0x01, 0x99, 0xb4, 0x01, 0xff, 0xb4, 0x01, 0x65, 0xb5, 0x01, 0xcb, 0xb5, 0x01, 0x31, 0xb6, 0x01, 0x97, 0xb6, 0x01, 0xfd, 0xb6, 0x01, 0x63, 0xb7, 0x01, 0xc9, 0xb7, 0x01, 0x2f, 0xb8, 0x01, 0x95, 0xb8, 0x01, 0xfb, 0xb8, 0x01, 0x61, 0xb9, 0x01, 0xc7, 0xb9, 0x01, 0x2d, 0xba, 0x01, 0x93, 0xba, 0x01, 0xf9, 0xba, 0x01, 0x5f, 0xbb, 0x01, 0xc5, 0xbb, 0x01, 0x2b, 0xbc, 0x01, 0x91, 0xbc, 0x01, 0xf7, 0xbc, 0x01, 0x5d, 0xbd, 0x01, 0xc3, 0xbd, 0x01, 0x29, 0xbe, 0x01, 0x8f, 0xbe, 0x01, 0xf5, 0xbe, 0x01, 0x5b, 0xbf, 0x01, 0xc1, 0xbf, 0x01, 0x27, 0xc0, 0x01, 0x8d, 0xc0, 0x01, 0xf3, 0xc0, 0x01, 0x59, 0xc1, 0x01, 0xbf, 0xc1, 0x01, 0x25, 0xc2, 0x01, 0x8b, 0xc2, 0x01, 0xf1, 0xc2, 0x01, 0x57, 0xc3, 0x01, 0xbd, 0xc3, 0x01, 0x23, 0xc4, 0x01, 0x89, 0xc4, 0x01, 0xef, 0xc4, 0x01, 0x55, 0xc5, 0x01, 0xbb, 0xc5, 0x01, 0x21, 0xc6, 0x01, 0x87, 0xc6, 0x01, 0xed, 0xc6, 0x01, 0x53, 0xc7, 0x01, 0xb9, 0xc7, 0x01, 0x1f, 0xc8, 0x01, 0x85, 0xc8, 0x01, 0xeb, 0xc8, 0x01, 0x51, 0xc9, 0x01, 0xb7, 0xc9, 0x01, 0x1d, 0xca, 0x01, 0x83, 0xca, 0x01, 0xe9, 0xca, 0x01, 0x4f, 0xcb, 0x01, 0xb5, 0xcb, 0x01, 0x1b, 0xcc, 0x01, 0x1f, 0x04, 0x07, 0x04, 0x04, 0x02, 0x03, 0x10, 0x00, 0x00, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x0a, 0x06, 0x00, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x10, 0x00, 0x00, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x1f, 0x00, 0x08, 0x00, 0x06, 0x00, 0x03, 0x0a, 0x06, 0x00, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x1e, 0x0b, 0x06, 0x04, 0x04, 0x03, 0x04, 0x0c, 0x04, 0x00, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x13, 0xf8, 0x01, 0x87, 0xf9, 0x01, 0x87, 0xf9, 0x01, 0x35, 0xee, 0x01, 0xa9, 0xf2, 0x01, 0xa9, 0xf2, 0x01, 0x35, 0xee, 0x01, 0xa9, 0xf2, 0x01, 0xa9, 0xf2, 0x01, 0x1e, 0x04, 0x0b, 0x04, 0x08, 0x02, 0x06, 0x04, 0x06, 0x06, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x18, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x0a, 0x06, 0x00, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x08, 0x04, 0x04, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0xb7, 0x11, 0x02, 0x21, 0x17, 0x02, 0x09, 0x1d, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x03, 0x05, 0x08, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0x7c, 0x00, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x73, 0x30, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xf0, 0x3c, 0x03, 0x55, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0xff, 0x00, 0x03, 0x55, 0x55, 0xff, 0x00, 0x3d, 0x55, 0x55, 0xff, 0x00, 0xcd, 0x55, 0x55, 0xcf, 0xff, 0x0d, 0x55, 0x55, 0x73, 0x30, 0x3d, 0x55, 0x55, 0x73, 0xf0, 0xf5, 0x55, 0x55, 0x73, 0xf0, 0x35, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x7f, 0x55, 0x57, 0xff, 0x55, 0xff, 0xd5, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x0f, 0x00, 0xf0, 0xd5, 0x57, 0x30, 0xc3, 0x0c, 0xd5, 0x57, 0x00, 0x3c, 0x00, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x57, 0x3f, 0xff, 0xfc, 0xd5, 0x57, 0xf0, 0xc3, 0x0f, 0xd5, 0x55, 0x73, 0xff, 0xcd, 0x55, 0x55, 0xc3, 0xff, 0xc3, 0x55, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x03, 0x00, 0xc0, 0xd5, 0x57, 0x0c, 0x00, 0x30, 0xd5, 0x57, 0x00, 0x3c, 0x00, 0xd5, 0x55, 0xc0, 0xff, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x3f, 0x0f, 0xc3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x00, 0xf0, 0x0d, 0x55, 0x55, 0xff, 0x0f, 0xf5, 0x55, 0x57, 0x33, 0xfc, 0xcd, 0x55, 0x57, 0xf3, 0xfc, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x30, 0x00, 0x0c, 0xd5, 0x57, 0x0c, 0x00, 0x30, 0xd5, 0x57, 0x00, 0xff, 0x00, 0xd5, 0x5f, 0x03, 0xff, 0xc0, 0xf5, 0x5c, 0xc3, 0xff, 0xc3, 0x35, 0x5f, 0x3f, 0xff, 0xfc, 0xf5, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0xc3, 0xff, 0xc3, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x7f, 0x55, 0x57, 0xff, 0x55, 0xff, 0xd5, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x03, 0x00, 0xc0, 0xd5, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x30, 0x3c, 0x0c, 0xd5, 0x55, 0xcc, 0x3c, 0x33, 0xd5, 0x55, 0xcc, 0x3c, 0x33, 0x55, 0x55, 0xc3, 0xc3, 0xc3, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xd7, 0xf5, 0x55, 0x55, 0x5f, 0x55, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x5c, 0x3f, 0xff, 0xc3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x55, 0xff, 0xff, 0xf5, 0x55, 0x55, 0xc0, 0x00, 0x35, 0x55, 0x57, 0x30, 0x00, 0xcd, 0x55, 0x57, 0xf0, 0x00, 0xfd, 0x55, 0x55, 0x70, 0x00, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0x55, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0x70, 0x00, 0x3d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x70, 0x0c, 0xd5, 0x55, 0x57, 0xc0, 0xfc, 0xd5, 0x55, 0x55, 0xf0, 0x3f, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0x57, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0x70, 0x00, 0x3d, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x30, 0xcd, 0x55, 0x55, 0xfc, 0x3f, 0xf5, 0x55, 0x55, 0x70, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x70, 0x3f, 0xf5, 0x55, 0x55, 0xc0, 0x0f, 0xf5, 0x55, 0x7f, 0xc0, 0x0f, 0xf5, 0x5f, 0xc0, 0xc0, 0x0f, 0x55, 0x5f, 0xc0, 0xc0, 0xcf, 0xd5, 0x55, 0xc0, 0xc0, 0xcf, 0xd5, 0x57, 0xc0, 0x3c, 0xcf, 0xf5, 0x5f, 0xfc, 0x03, 0x0f, 0xf5, 0x5f, 0xff, 0xff, 0xf7, 0xd5, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x3c, 0x03, 0xc3, 0x55, 0x5c, 0xc3, 0x0c, 0x33, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0xc3, 0x0c, 0x33, 0x55, 0x57, 0x30, 0xf0, 0xcc, 0xd5, 0x55, 0xff, 0xff, 0xf0, 0xd5, 0x55, 0x73, 0x0c, 0x03, 0x55, 0x55, 0xcc, 0xfc, 0x0d, 0x55, 0x55, 0xfc, 0xff, 0x0d, 0x55, 0x55, 0x5c, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x55, 0xf5, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x00, 0xc3, 0x00, 0xd5, 0x57, 0x3f, 0xc3, 0xfc, 0xd5, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x5c, 0xcc, 0x35, 0x55, 0x55, 0x73, 0xff, 0xcd, 0x55, 0x55, 0x70, 0xfc, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xc0, 0x30, 0x03, 0x55, 0x55, 0xc0, 0xc0, 0x03, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xfc, 0x00, 0x03, 0x55, 0x55, 0xff, 0x03, 0xc3, 0x55, 0x55, 0x7f, 0x03, 0x3d, 0x55, 0x55, 0x5f, 0xff, 0x35, 0x55, 0x55, 0x5c, 0xcc, 0x0d, 0x55, 0x55, 0x57, 0x3c, 0x03, 0x55, 0x55, 0x57, 0x3c, 0x3f, 0x55, 0x55, 0x57, 0xff, 0xf5, 0x55, 0x55, 0x55, 0x7d, 0xfd, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0x7f, 0x55, 0x55, 0x55, 0xff, 0xff, 0xd5, 0x55, 0x55, 0xff, 0xff, 0xd5, 0x55, 0x55, 0xff, 0x00, 0x35, 0x55, 0x57, 0xf0, 0x00, 0x3d, 0x55, 0x57, 0xc0, 0x03, 0x03, 0x55, 0x57, 0x00, 0x3c, 0x03, 0x55, 0x57, 0x00, 0x00, 0x0f, 0x55, 0x57, 0x00, 0x00, 0x35, 0x55, 0x57, 0xc0, 0x03, 0xd5, 0x55, 0x55, 0x7f, 0xff, 0x55, 0x55, 0x55, 0xc0, 0xcf, 0x55, 0x55, 0x57, 0x30, 0xfd, 0x55, 0x55, 0x57, 0xf0, 0xfd, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x7d, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xf5, 0x55, 0x55, 0x5f, 0xfd, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0x00, 0x0d, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x0f, 0xc3, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0x70, 0x00, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x5c, 0x3c, 0xd5, 0x55, 0x55, 0x5f, 0x0f, 0xd5, 0x55, 0x55, 0x5c, 0xff, 0xd5, 0x55, 0x55, 0x70, 0x0f, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3c, 0x0f, 0x55, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0xc0, 0x00, 0xff, 0x55, 0x55, 0xc0, 0xf0, 0xff, 0x55, 0x55, 0x70, 0xcc, 0xfd, 0x55, 0x55, 0x5f, 0xcf, 0xd5, 0x55, 0x55, 0x5c, 0xcc, 0xd5, 0x55, 0x55, 0x5c, 0x3f, 0xd5, 0x55, 0x55, 0x5c, 0x0f, 0xd5, 0x55, 0x55, 0x70, 0x0f, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x55, 0xfd, 0x55, 0x55, 0x7f, 0xdf, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0xc3, 0x55, 0x55, 0xcc, 0x00, 0x03, 0x55, 0x55, 0x73, 0x00, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x73, 0x30, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0x7f, 0x55, 0x55, 0xff, 0xd5, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0xd5, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0x70, 0x00, 0x03, 0x55, 0x55, 0xc3, 0x00, 0x30, 0xd5, 0x55, 0xcc, 0xc0, 0xcc, 0xd5, 0x55, 0xc3, 0x00, 0x30, 0xd5, 0x57, 0xc0, 0x3f, 0x00, 0xd5, 0x57, 0x30, 0xff, 0xc3, 0x55, 0x55, 0xcf, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xc3, 0xfc, 0x03, 0x55, 0x55, 0xc3, 0xfc, 0x3c, 0xd5, 0x55, 0x7f, 0xfc, 0x37, 0xd5, 0x55, 0x5f, 0x7f, 0xd5, 0x55, 0x55, 0x55, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x3c, 0x03, 0xc3, 0x55, 0x5c, 0xf3, 0x0f, 0x33, 0x55, 0x5c, 0xff, 0x0f, 0xf3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x0f, 0xf0, 0x0d, 0x55, 0x55, 0xfc, 0x3f, 0xf5, 0x55, 0x55, 0xc3, 0xcc, 0x3d, 0x55, 0x55, 0x70, 0xfc, 0xf3, 0x55, 0x55, 0x70, 0xfc, 0xdf, 0x55, 0x55, 0x7f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xcd, 0x55, 0x5f, 0xff, 0xff, 0xfd, 0x55, 0x7f, 0xff, 0xff, 0xd5, 0x55, 0x70, 0x00, 0x03, 0xd5, 0x55, 0xff, 0xff, 0xfc, 0xd5, 0x55, 0xc0, 0x00, 0x0f, 0xd5, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0x7c, 0x00, 0x0c, 0xd5, 0x55, 0x5f, 0xff, 0xf0, 0x35, 0x55, 0x7f, 0x3f, 0xfc, 0x0d, 0x55, 0x7f, 0x3f, 0xfc, 0x0d, 0x55, 0x70, 0x00, 0x3c, 0x0d, 0x55, 0x7f, 0xff, 0xf0, 0x0d, 0x55, 0x5f, 0xff, 0xdf, 0xf5, 0x55, 0x7f, 0xdf, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0x55, 0x55, 0x55, 0x57, 0x35, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0xff, 0xff, 0x55, 0x55, 0x5f, 0xff, 0xff, 0x55, 0x55, 0x70, 0x00, 0x0f, 0x55, 0x55, 0x7f, 0xff, 0xf3, 0xfd, 0x55, 0xc0, 0x00, 0x0c, 0xc3, 0x55, 0xc0, 0x00, 0x03, 0xc3, 0x55, 0xc0, 0x00, 0x03, 0x03, 0x55, 0xf0, 0x03, 0x03, 0xc3, 0x55, 0xc3, 0xc0, 0x0f, 0xc3, 0x55, 0xc3, 0xc0, 0x3f, 0x0d, 0x55, 0x7f, 0xff, 0xfc, 0x35, 0x5d, 0xff, 0x3f, 0xf3, 0xd5, 0x5f, 0x00, 0x00, 0xfd, 0x55, 0x5f, 0xff, 0xff, 0x3d, 0x55, 0x55, 0xff, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xff, 0x55, 0x55, 0x7f, 0xff, 0xff, 0xd5, 0x55, 0xf0, 0x00, 0x03, 0xf5, 0x55, 0xcf, 0xff, 0xfc, 0xf5, 0x55, 0xf0, 0x00, 0x03, 0xff, 0x57, 0x0f, 0xc0, 0xfc, 0xf3, 0x57, 0x33, 0xc3, 0x3c, 0xdf, 0x57, 0x33, 0xc3, 0x3c, 0xd5, 0x57, 0x0f, 0xc0, 0xfc, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x35, 0x55, 0xff, 0xff, 0xfc, 0x0d, 0x57, 0xff, 0xcf, 0xf3, 0x0d, 0x5c, 0xff, 0xcf, 0xff, 0x0d, 0x57, 0x70, 0x00, 0x0c, 0x0d, 0x55, 0x7f, 0xff, 0xf7, 0xf5, 0x55, 0x57, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xf7, 0xfd, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xff, 0xf5, 0x55, 0x70, 0x00, 0xff, 0xff, 0x55, 0x7f, 0xfc, 0x03, 0xf3, 0x55, 0xf0, 0xff, 0xf0, 0xdf, 0x55, 0xf0, 0xf3, 0x0f, 0xd5, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xff, 0xf0, 0x33, 0x55, 0x57, 0x3f, 0xc0, 0xff, 0xd5, 0x57, 0xcf, 0xff, 0xfc, 0x35, 0x55, 0xff, 0x3f, 0xfc, 0x0d, 0x55, 0x7f, 0x3f, 0xf0, 0x0d, 0x55, 0x7f, 0x3f, 0xf0, 0x0d, 0x55, 0x70, 0x00, 0xf0, 0x0d, 0x55, 0x5f, 0xff, 0xdf, 0xf5, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x55, 0xf7, 0xd5, 0x55, 0x30, 0x1f, 0x01, 0x55, 0x40, 0x00, 0x00, 0x00, 0x15, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x11, 0x41, 0x50, 0x00, 0x00, 0x15, 0x55, 0x55, 0x54, 0x04, 0x10, 0x01, 0x55, 0x41, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa1, 0x14, 0x15, 0x54, 0x01, 0x11, 0x45, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa5, 0x54, 0x15, 0x54, 0x01, 0x55, 0x45, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa1, 0x14, 0x44, 0x11, 0x55, 0x55, 0x55, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x15, 0x40, 0x01, 0x55, 0x11, 0x56, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x95, 0x40, 0x01, 0x55, 0x55, 0x56, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x95, 0x55, 0x55, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x55, 0x50, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x01, 0x50, 0x55, 0x50, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x15, 0x55, 0x55, 0x54, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x02, 0x55, 0x55, 0x55, 0x00, 0x04, 0x00, 0x80, 0x28, 0x00, 0x00, 0xa0, 0x02, 0x01, 0x15, 0x55, 0x10, 0x04, 0x55, 0x80, 0x28, 0x00, 0x00, 0xa0, 0x02, 0x01, 0x15, 0x55, 0x01, 0x55, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x02, 0x55, 0x55, 0x55, 0x01, 0x01, 0x00, 0x80, 0xaa, 0xaa, 0xaa, 0xa8, 0x02, 0x00, 0x04, 0x01, 0x01, 0x55, 0x00, 0x82, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x04, 0x01, 0x00, 0x41, 0x00, 0x82, 0xaa, 0xaa, 0xaa, 0xaa, 0x02, 0x00, 0x04, 0x01, 0x55, 0x5a, 0xa5, 0x80, 0x95, 0x95, 0x80, 0x00, 0x02, 0x55, 0x54, 0x01, 0x00, 0x25, 0x58, 0x80, 0x95, 0x95, 0x85, 0x54, 0x0a, 0xaa, 0xa8, 0x01, 0x00, 0x26, 0x98, 0x80, 0x95, 0x95, 0x85, 0x54, 0x08, 0x00, 0x09, 0x55, 0x00, 0x25, 0x58, 0x80, 0x95, 0x95, 0xaa, 0xaa, 0x08, 0x88, 0x88, 0x00, 0x00, 0x20, 0x08, 0x95, 0x95, 0x95, 0x80, 0x02, 0x58, 0x88, 0x88, 0x00, 0xaa, 0xa0, 0x0a, 0x95, 0x95, 0x95, 0x80, 0x02, 0x58, 0x00, 0x0a, 0xaa, 0x04, 0x20, 0x08, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa9, 0x55, 0x58, 0x00, 0x00, 0x0a, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xaa, 0xa9, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0x42, 0x82, 0x20, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa6, 0x86, 0x26, 0x62, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x45, 0x86, 0x24, 0xa4, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xa4, 0xa1, 0x61, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x61, 0x40, 0xa2, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0xaa, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa9, 0x55, 0x69, 0x55, 0x6a, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x9a, 0xa9, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x59, 0x59, 0x6a, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x98, 0x49, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x95, 0x55, 0xaa, 0x95, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa5, 0x56, 0xaa, 0x40, 0x68, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa8, 0x0a, 0xa5, 0x55, 0x58, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa9, 0x5a, 0xa5, 0x55, 0x58, 0x00, 0x95, 0x5a, 0x69, 0xa5, 0x56, 0x02, 0xa5, 0x96, 0xa9, 0x69, 0x68, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x96, 0x5a, 0x69, 0xa5, 0x96, 0x54, 0x54, 0x54, 0x54, 0x54, 0x55, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x54, 0x54, 0x54, 0x54, 0x54, 0x55, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x30, 0x1f, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x15, 0x00, 0x00, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x55, 0x00, 0x01, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x40, 0x51, 0x55, 0x55, 0x15, 0x54, 0x00, 0x00, 0x15, 0x54, 0x55, 0x55, 0x45, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x40, 0x00, 0x44, 0x11, 0x10, 0x11, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x44, 0x04, 0x44, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x40, 0x00, 0x44, 0x15, 0x05, 0x41, 0x50, 0x05, 0x55, 0x55, 0x50, 0x05, 0x41, 0x50, 0x54, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x50, 0x40, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x50, 0x40, 0x01, 0x00, 0x01, 0x00, 0x17, 0xfc, 0x3f, 0xfc, 0x00, 0x43, 0xff, 0xc0, 0x01, 0x00, 0x01, 0x00, 0x1f, 0xf4, 0xff, 0xd4, 0x00, 0x4f, 0xfc, 0x40, 0x01, 0x55, 0x55, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x40, 0x01, 0x11, 0x11, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x40, 0x01, 0x00, 0x01, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xc0, 0x01, 0x05, 0x41, 0x00, 0xf0, 0xfc, 0x03, 0xff, 0xff, 0x00, 0x00, 0xc0, 0x01, 0x05, 0x41, 0x00, 0xf0, 0xf3, 0x0c, 0x71, 0xc7, 0x33, 0x30, 0xc0, 0xaa, 0xaa, 0xaa, 0xaa, 0xf0, 0xf3, 0x0d, 0x75, 0xd7, 0x33, 0x30, 0xea, 0x55, 0x55, 0x55, 0x55, 0xf0, 0xfc, 0x0d, 0x34, 0xd3, 0x33, 0x30, 0xd5, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x0d, 0x34, 0xc3, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x03, 0xff, 0xff, 0xaa, 0xaa, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 0xc0, 0x00, 0xfc, 0x0f, 0xc0, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x3a, 0xbf, 0xfa, 0xab, 0xff, 0xbf, 0xfb, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0xff, 0xff, 0xcf, 0xfc, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf0, 0x03, 0xff, 0x3f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xc0, 0x00, 0xfc, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x55, 0x51, 0x55, 0x55, 0x15, 0x54, 0x00, 0x00, 0x15, 0x10, 0x00, 0x00, 0x40, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x40, 0x11, 0x10, 0x11, 0x10, 0x04, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x40, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x15, 0x55, 0x55, 0x40, 0x15, 0x05, 0x41, 0x50, 0x05, 0x55, 0x55, 0x50, 0x00, 0x00, 0x00, 0x00, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf5, 0xff, 0xf0, 0x00, 0x0f, 0xff, 0x00, 0x50, 0x50, 0x50, 0x50, 0x3f, 0xc3, 0xff, 0x00, 0x14, 0x3f, 0xf4, 0x14, 0x55, 0x50, 0x55, 0x50, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x54, 0x55, 0x50, 0x55, 0x50, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x54, 0x55, 0x55, 0x55, 0x53, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x54, 0x40, 0x10, 0x40, 0x13, 0xc3, 0xf0, 0x0f, 0xff, 0xfc, 0x00, 0x03, 0x04, 0x50, 0x50, 0x50, 0x53, 0xc3, 0xcc, 0x31, 0xc7, 0x1c, 0xcc, 0xc3, 0x14, 0x40, 0x10, 0x40, 0x13, 0xc3, 0xcc, 0x35, 0xd7, 0x5c, 0xcc, 0xc3, 0x04, 0xaa, 0xaa, 0xaa, 0xab, 0xc3, 0xf0, 0x34, 0xd3, 0x4c, 0xcc, 0xc3, 0xaa, 0x55, 0x55, 0x55, 0x57, 0x00, 0x00, 0x34, 0xd3, 0x0c, 0x00, 0x03, 0x55, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x0f, 0xff, 0xfe, 0xaa, 0xab, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x3f, 0x00, 0x03, 0xf0, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xea, 0xff, 0xea, 0xaf, 0xfe, 0xff, 0xec, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf3, 0xff, 0xff, 0x3f, 0xf3, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x0f, 0xfc, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x03, 0xf0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xfd, 0x7d, 0x7f, 0x5d, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x5d, 0xd5, 0xd7, 0x75, 0xdd, 0xd5, 0x55, 0x55, 0x55, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x30, 0xcc, 0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0xc0, 0xff, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xc0, 0xc3, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0x3f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xfc, 0x3f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x03, 0xc0, 0x30, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0xf3, 0xff, 0xff, 0xcf, 0x00, 0x00, 0x0f, 0xf0, 0x70, 0x0f, 0x55, 0x55, 0xc3, 0x0c, 0x30, 0xc3, 0x55, 0x55, 0xf0, 0x0d, 0xc3, 0x30, 0xd5, 0xff, 0x7c, 0xcf, 0xf3, 0x3d, 0xff, 0x57, 0x0c, 0xc3, 0xc0, 0x3f, 0x5f, 0x03, 0x57, 0xcf, 0xf3, 0xd5, 0xc0, 0xf5, 0xfc, 0x03, 0xc0, 0x30, 0xdc, 0x0d, 0x5f, 0xff, 0xff, 0xf5, 0x70, 0x37, 0x0c, 0x03, 0x7f, 0xff, 0x5f, 0xf5, 0x5f, 0x55, 0x55, 0xf5, 0x5f, 0xf5, 0xff, 0xfd, 0x30, 0x1f, 0xa4, 0x00, 0xa4, 0x01, 0x90, 0x00, 0x64, 0x06, 0x40, 0x1a, 0x00, 0x16, 0xa9, 0x40, 0x09, 0x00, 0x40, 0x00, 0x10, 0x01, 0x00, 0x60, 0x01, 0x6a, 0x2a, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xaa, 0x00, 0xa5, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x01, 0x6a, 0x80, 0x00, 0x01, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x30, 0xc0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x00, 0x05, 0x94, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x15, 0x56, 0xa5, 0x55, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x15, 0x40, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x29, 0x50, 0x15, 0x68, 0x00, 0x40, 0x07, 0xf0, 0x0f, 0xc0, 0x10, 0x00, 0x0a, 0xa5, 0x6a, 0x80, 0x01, 0x00, 0x1f, 0xfc, 0x3f, 0xf0, 0x04, 0x00, 0x00, 0xaa, 0xa8, 0x00, 0x15, 0x00, 0x1f, 0xff, 0xff, 0xf0, 0x05, 0x40, 0x00, 0x0a, 0xa0, 0x00, 0x04, 0x00, 0x5c, 0x00, 0x00, 0x30, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xf0, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xc0, 0x33, 0x00, 0x00, 0xcc, 0x03, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x30, 0x03, 0xc0, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x0c, 0x30, 0x03, 0xc0, 0x0c, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x3c, 0x03, 0xc0, 0x3c, 0xff, 0xc0, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0xc3, 0xff, 0xff, 0xc3, 0x00, 0x00, 0x0f, 0xf0, 0x30, 0x0c, 0x00, 0x00, 0xcc, 0x30, 0x0c, 0x33, 0x00, 0x00, 0x30, 0x0c, 0xc3, 0x0f, 0x00, 0x00, 0x3f, 0x3f, 0xfc, 0xfc, 0x00, 0x00, 0xf0, 0xc3, 0xc0, 0x30, 0xc0, 0x00, 0x03, 0x3f, 0xfc, 0xc0, 0x00, 0x03, 0x0c, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0xfc, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x3f, 0xfc, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x30, 0x30, 0xc0, 0x00, 0x00, 0x3c, 0x3c, 0x00, 0x00, 0x03, 0x0c, 0x0c, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x0c, 0x30, 0x00, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xfd, 0x7d, 0x7f, 0x5d, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x5d, 0xd5, 0xd7, 0x75, 0xdd, 0xd5, 0x55, 0x55, 0x55, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x30, 0xcc, 0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0xc0, 0xff, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xc0, 0xc3, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x70, 0x0f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xf0, 0x0d, 0xc3, 0x30, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x0c, 0xc3, 0xc0, 0x3f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfc, 0x03, 0xc0, 0x30, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x0c, 0x03, 0x7f, 0xff, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xfd, 0x30, 0x1f, 0xa4, 0x00, 0xa4, 0x01, 0x90, 0x00, 0x64, 0x06, 0x40, 0x1a, 0x00, 0x16, 0xa9, 0x40, 0x09, 0x00, 0x40, 0x00, 0x10, 0x01, 0x00, 0x60, 0x01, 0x6a, 0x2a, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xaa, 0x00, 0xa5, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x01, 0x6a, 0x80, 0x00, 0x01, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x30, 0xc0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x00, 0x05, 0x94, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x15, 0x56, 0xa5, 0x55, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x15, 0x40, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x29, 0x50, 0x15, 0x68, 0x00, 0x40, 0x04, 0x00, 0x04, 0x00, 0x10, 0x00, 0x0a, 0xa5, 0x6a, 0x80, 0x01, 0x00, 0x14, 0x00, 0x05, 0x00, 0x04, 0x00, 0x00, 0xaa, 0xa8, 0x00, 0x15, 0x00, 0x15, 0x00, 0x15, 0x00, 0x05, 0x40, 0x00, 0x0a, 0xa0, 0x00, 0x04, 0x00, 0x54, 0x00, 0x05, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x30, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0c, 0xc3, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xc3, 0xc0, 0x30, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x30, 0x30, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x0c, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xfc, 0x00, 0xc3, 0x0f, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xc3, 0x00, 0xc3, 0x30, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xcc, 0xc3, 0x00, 0xff, 0x30, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xfc, 0x00, 0xc3, 0x30, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xc0, 0x00, 0xc3, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x3f, 0x0f, 0xcf, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0xcc, 0x0c, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0xcf, 0xcf, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0x0f, 0xcf, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x30, 0xcc, 0x33, 0x0c, 0xfc, 0xfc, 0x00, 0x00, 0xc0, 0x00, 0x00, 0xc3, 0x30, 0xcf, 0x33, 0xcc, 0xc0, 0xc3, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc3, 0x30, 0xcc, 0xf3, 0x3c, 0xfc, 0xc3, 0x00, 0x00, 0xfc, 0x00, 0x00, 0xfc, 0x30, 0xcc, 0x33, 0x0c, 0xc0, 0xfc, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc3, 0x0f, 0x0c, 0x33, 0x0c, 0xfc, 0xc3, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x1f, 0x05, 0x55, 0x55, 0x55, 0x55, 0x55, 0x54, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x05, 0x54, 0x55, 0x45, 0x51, 0x10, 0x00, 0x04, 0x04, 0x55, 0x44, 0x51, 0x11, 0x55, 0x44, 0x04, 0x44, 0x44, 0x51, 0x11, 0x00, 0x44, 0x04, 0x44, 0x44, 0x51, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x00, 0x00, 0x00, 0x05, 0x41, 0x10, 0x00, 0x00, 0x00, 0x00, 0x04, 0x41, 0x10, 0x00, 0x00, 0x10, 0x55, 0x05, 0x41, 0x10, 0x54, 0x00, 0x55, 0x45, 0x10, 0x11, 0x11, 0x01, 0x40, 0x55, 0x54, 0x10, 0x11, 0x11, 0x00, 0x10, 0x55, 0x54, 0x15, 0x51, 0x11, 0x41, 0x11, 0x51, 0x10, 0x04, 0x41, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x50, 0x50, 0x00, 0x00, 0x10, 0x01, 0x10, 0x55, 0x50, 0x55, 0x00, 0x55, 0x01, 0x10, 0x44, 0x51, 0x00, 0x51, 0x00, 0x41, 0x10, 0x40, 0x11, 0x04, 0x41, 0x11, 0x41, 0x10, 0x15, 0x41, 0x00, 0x41, 0x00, 0x41, 0x10, 0x10, 0x41, 0x00, 0x40, 0x41, 0x01, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x55, 0x55, 0x55, 0x55, 0x55, 0x41, 0x10, 0x40, 0x00, 0x00, 0x00, 0x00, 0x41, 0x10, 0x55, 0x55, 0x55, 0x55, 0x55, 0x41, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x15, 0x50, 0x00, 0x00, 0x00, 0x01, 0x55, 0x12, 0x0c, 0x57, 0xf5, 0x7d, 0x55, 0x50, 0x5f, 0xfd, 0xff, 0x55, 0x50, 0x5f, 0xff, 0xff, 0x55, 0x50, 0x5f, 0xff, 0xff, 0xd5, 0x50, 0x7c, 0x00, 0x00, 0xd5, 0x50, 0x70, 0x0f, 0xc3, 0xd5, 0x50, 0x70, 0x33, 0xc3, 0xd5, 0x50, 0x70, 0x33, 0xc3, 0xd5, 0x50, 0x70, 0x0f, 0xc3, 0xd5, 0x50, 0x5c, 0x00, 0x0f, 0x55, 0x50, 0x57, 0xff, 0xfd, 0x55, 0x50, 0x5c, 0x3c, 0x33, 0x55, 0x50, 0x12, 0x0c, 0x55, 0xfd, 0x5f, 0x55, 0x50, 0x57, 0xff, 0x7f, 0xd5, 0x50, 0x57, 0xff, 0xff, 0xd5, 0x50, 0x57, 0xff, 0xff, 0xf5, 0x50, 0x5f, 0x00, 0x00, 0x35, 0x50, 0x5c, 0x03, 0xc0, 0x35, 0x50, 0x5c, 0x0c, 0x30, 0xf5, 0x50, 0x5c, 0x00, 0x00, 0x35, 0x50, 0x5c, 0x0c, 0x0f, 0xf5, 0x50, 0x57, 0x33, 0x0f, 0xd5, 0x50, 0x55, 0xf3, 0xff, 0x35, 0x50, 0x55, 0xc3, 0xc3, 0xf5, 0x50, 0x12, 0x0c, 0x5f, 0xd5, 0x7f, 0xff, 0xf0, 0x7f, 0xf5, 0xff, 0x00, 0x30, 0x7f, 0xff, 0xff, 0x00, 0x30, 0x7f, 0xff, 0xff, 0x00, 0x30, 0x70, 0x00, 0x03, 0x00, 0x30, 0xc3, 0xf0, 0x3f, 0x00, 0x30, 0xcc, 0xf0, 0xcf, 0x00, 0x30, 0xcc, 0xf0, 0xcf, 0x00, 0x30, 0xc3, 0xf0, 0x3f, 0xff, 0xf0, 0x70, 0x0f, 0x00, 0xcd, 0x50, 0x5f, 0xff, 0xff, 0x35, 0x50, 0x70, 0x30, 0x3c, 0xd5, 0x50, 0x12, 0x0c, 0x55, 0xfd, 0x57, 0xd5, 0x50, 0x57, 0xff, 0xdf, 0xf5, 0x50, 0x57, 0xff, 0xff, 0xfd, 0x50, 0x55, 0xff, 0xff, 0xfd, 0x50, 0x57, 0xc0, 0x00, 0x0d, 0x50, 0x57, 0x00, 0x00, 0x0d, 0x50, 0x57, 0x00, 0x00, 0x0d, 0x50, 0x57, 0x0f, 0xf0, 0x0d, 0x50, 0x57, 0x00, 0x00, 0xcd, 0x50, 0x55, 0xc0, 0x03, 0x35, 0x50, 0x55, 0x7f, 0xff, 0xd5, 0x50, 0x55, 0xc3, 0xc3, 0xd5, 0x50, 0x12, 0x0c, 0x57, 0xf5, 0x5f, 0xd5, 0x50, 0x5f, 0xfd, 0x7f, 0xf5, 0x50, 0x5f, 0xff, 0xff, 0xf5, 0x50, 0x5f, 0xff, 0xff, 0xf5, 0x50, 0x5c, 0x00, 0x00, 0x35, 0x50, 0x70, 0x00, 0x00, 0x0d, 0x50, 0x70, 0x30, 0x0c, 0x0d, 0x50, 0x70, 0xc0, 0x03, 0x0d, 0x50, 0x70, 0x03, 0xc0, 0x0d, 0x50, 0x5c, 0x0f, 0xf0, 0x35, 0x50, 0x57, 0xff, 0xff, 0xd5, 0x50, 0x55, 0xcc, 0x33, 0x55, 0x50, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfa, 0xaa, 0xab, 0xc0, 0xff, 0xe5, 0x55, 0x5a, 0xc0, 0xff, 0xe5, 0x55, 0x5a, 0xc0, 0xff, 0x95, 0x55, 0x66, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0xaa, 0xaa, 0xab, 0xc0, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfe, 0xaa, 0xaa, 0xc0, 0xff, 0xfe, 0x55, 0x56, 0xc0, 0xff, 0xfe, 0x55, 0x56, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xea, 0xaa, 0xaa, 0xc0, 0xff, 0xea, 0xaa, 0xaa, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0xaa, 0xaa, 0xab, 0xc0, 0x08, 0x08, 0x7f, 0xf5, 0xff, 0xfd, 0xc3, 0x0d, 0xff, 0xfd, 0xff, 0xfd, 0xfc, 0xfd, 0x7f, 0xf5, 0x77, 0x75, 0x10, 0x03, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xc0, 0x03, 0x03, 0xff, 0xff, 0xff, 0xff, 0x10, 0x03, 0x55, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x03, 0x55, 0x55, 0xff, 0xff, 0x55, 0x08, 0x08, 0x55, 0x75, 0x55, 0x75, 0x55, 0x75, 0x5f, 0x75, 0x70, 0xf5, 0x70, 0xd5, 0x5f, 0x55, 0x55, 0x55, 0x08, 0x08, 0x55, 0x75, 0x55, 0x75, 0x55, 0x75, 0x5f, 0x75, 0x7f, 0xf5, 0x7f, 0xd5, 0x5f, 0x55, 0x55, 0x55, 0x08, 0x08, 0x55, 0xd5, 0x55, 0xf5, 0x55, 0xfd, 0x7d, 0xdd, 0xff, 0xd5, 0xff, 0x55, 0x7d, 0x55, 0x55, 0x55, 0x08, 0x08, 0x5f, 0xfd, 0x5d, 0x5d, 0x5d, 0x5d, 0x5d, 0x5d, 0xfd, 0xfd, 0xfd, 0xfd, 0xf5, 0xf5, 0x55, 0x55, 0x01, 0x01, 0x00, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x7f, 0xfd, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x5f, 0xfd, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x7f, 0xfd, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x5f, 0xfd, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x7f, 0xfd, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0x03, 0x5f, 0xfd, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x08, 0x08, 0x50, 0x05, 0x43, 0xc1, 0x00, 0x00, 0x30, 0xcc, 0x33, 0x0c, 0x00, 0x00, 0x43, 0xc1, 0x50, 0x05, 0x08, 0x08, 0xc0, 0x03, 0x33, 0xcc, 0x00, 0x30, 0x33, 0x0c, 0x30, 0xcc, 0x0c, 0x00, 0x33, 0xcc, 0xc0, 0x03, 0x08, 0x08, 0x57, 0xd5, 0x5c, 0x35, 0x5c, 0x35, 0xdc, 0x37, 0xd7, 0xd7, 0xdf, 0xf7, 0xfd, 0x7f, 0xf7, 0xdf, 0x04, 0x1f, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x02, 0x05, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0x06, 0x20, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0x20, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf7, 0xff, 0x5f, 0x5f, 0xd7, 0xff, 0x75, 0x5d, 0x55, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x57, 0xd5, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x55, 0x75, 0x75, 0x7f, 0xdf, 0xd5, 0x75, 0x75, 0x55, 0x75, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x55, 0x5f, 0xd5, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x08, 0x7f, 0x5f, 0x57, 0xd7, 0x57, 0xd5, 0x75, 0xdd, 0x77, 0x57, 0xdf, 0x75, 0xdd, 0x77, 0x57, 0xd7, 0x75, 0xdf, 0xf7, 0x55, 0x7d, 0x5f, 0x5d, 0x77, 0xf7, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x0c, 0x7f, 0x5f, 0x5d, 0x5d, 0xfd, 0xd5, 0x75, 0xdf, 0x7d, 0xd5, 0xdf, 0x75, 0xdf, 0xfd, 0xfd, 0xd7, 0x7f, 0xdd, 0xdd, 0xd5, 0x7f, 0x75, 0xdd, 0x5d, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7d, 0x75, 0x77, 0xf7, 0xf5, 0xd7, 0x75, 0x77, 0x57, 0x5d, 0xd7, 0x5d, 0xd7, 0xf7, 0x5d, 0xd7, 0x5d, 0xd7, 0x57, 0xf5, 0x7d, 0x57, 0x57, 0xf7, 0x5d, 0x55, 0x55, 0x55, 0x55, 0x55, 0x20, 0x0c, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xff, 0x55, 0xc3, 0x7d, 0x55, 0x55, 0x55, 0x70, 0x00, 0xd5, 0x70, 0xff, 0x55, 0x55, 0x55, 0xc0, 0x00, 0x35, 0x7c, 0x3f, 0xd5, 0x55, 0x57, 0x00, 0x03, 0x0d, 0x5f, 0xff, 0xff, 0xff, 0xfc, 0x03, 0x00, 0x0d, 0x70, 0x00, 0x03, 0xc0, 0x00, 0x00, 0x3f, 0xfd, 0x7f, 0xff, 0xfc, 0x30, 0x00, 0x00, 0xc0, 0x03, 0xc0, 0x00, 0x03, 0x30, 0x00, 0x03, 0x0f, 0xfc, 0xc0, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc0, 0x03, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x01, 0x01, 0x00, 0x10, 0x10, 0x55, 0x7d, 0x55, 0xf5, 0x55, 0xc3, 0x57, 0x0d, 0x55, 0xc0, 0xdc, 0x0d, 0x55, 0x70, 0xdc, 0x3d, 0x55, 0x5c, 0x30, 0x35, 0x55, 0x70, 0x00, 0xd5, 0x55, 0xc3, 0xfc, 0xd5, 0x55, 0xcf, 0xff, 0x35, 0x57, 0x0f, 0xff, 0x35, 0x57, 0x00, 0xfc, 0x35, 0x57, 0xc0 };\r\n//uint8_t v[] = { 0x0a, 0xaa, 0x55, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x55, 0x03, 0x03, 0x03, 0x00, 0x00, 0x10, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0xc4, 0x00, 0x00, 0xdc, 0x00, 0x00, 0x0f, 0x01, 0x00, 0x91, 0x01, 0x00, 0x0d, 0x02, 0x00, 0x89, 0x02, 0x00, 0xd1, 0x02, 0x00, 0x1f, 0x06, 0x00, 0x67, 0x0f, 0x00, 0x67, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x12, 0x00, 0xa7, 0x12, 0x00, 0x0d, 0x13, 0x00, 0x73, 0x13, 0x00, 0xd9, 0x13, 0x00, 0x3f, 0x14, 0x00, 0xa5, 0x14, 0x00, 0x0b, 0x15, 0x00, 0x71, 0x15, 0x00, 0xd7, 0x15, 0x00, 0x3d, 0x16, 0x00, 0xa3, 0x16, 0x00, 0x09, 0x17, 0x00, 0x6f, 0x17, 0x00, 0xd5, 0x17, 0x00, 0x3b, 0x18, 0x00, 0xa1, 0x18, 0x00, 0x07, 0x19, 0x00, 0x6d, 0x19, 0x00, 0xd3, 0x19, 0x00, 0x39, 0x1a, 0x00, 0x9f, 0x1a, 0x00, 0x05, 0x1b, 0x00, 0x6b, 0x1b, 0x00, 0xd1, 0x1b, 0x00, 0x37, 0x1c, 0x00, 0x9d, 0x1c, 0x00, 0x13, 0x1e, 0x00, 0x89, 0x1f, 0x00, 0xff, 0x20, 0x00, 0x75, 0x22, 0x00, 0xeb, 0x23, 0x00, 0x61, 0x25, 0x00, 0xd7, 0x26, 0x00, 0x4d, 0x28, 0x00, 0xeb, 0x28, 0x00, 0x89, 0x29, 0x00, 0x64, 0x2a, 0x00, 0xa2, 0x2a, 0x00, 0xe0, 0x2a, 0x00, 0x1e, 0x2b, 0x00, 0x5c, 0x2b, 0x00, 0xce, 0x00, 0x00, 0xf1, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x44, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};// 0x70, 0x2c, 0x00, 0x82, 0x2c, 0x00, 0x90, 0x2c, 0x00, 0x9e, 0x2c, 0x00, 0xb0, 0x2c, 0x00, 0xc2, 0x2c, 0x00, 0xd4, 0x2c, 0x00, 0xe6, 0x2c, 0x00, 0xe9, 0x2c, 0x00, 0x1b, 0x2d, 0x00, 0x4d, 0x2d, 0x00, 0x7f, 0x2d, 0x00, 0xb1, 0x2d, 0x00, 0xe3, 0x2d, 0x00, 0x15, 0x2e, 0x00, 0x27, 0x2e, 0x00, 0x39, 0x2e, 0x00, 0x4b, 0x2e, 0x00, 0x6c, 0x2e, 0x00, 0x73, 0x2e, 0x00, 0xb5, 0x2e, 0x00, 0xf7, 0x2e, 0x00, 0x21, 0x2f, 0x00, 0x5f, 0x2f, 0x00, 0xc1, 0x2f, 0x00, 0x02, 0x00, 0x06, 0x03, 0x04, 0x09, 0x0a, 0x05, 0x08, 0x07, 0x00, 0x00, 0x58, 0x00, 0x00, 0x32, 0x00, 0x00, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x10, 0x00, 0x00, 0x08, 0x00, 0x00, 0x50, 0x04, 0x00, 0x30, 0x02, 0x00, 0x20, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00, 0x50, 0x08, 0x00, 0x50, 0x11, 0x00, 0x00, 0x00, 0x28, 0x00, 0x40, 0x15, 0x00, 0x60, 0x12, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x45, 0x00, 0x00, 0x35, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x22, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00, 0x22, 0x00, 0x00, 0x13, 0x00, 0x01, 0x00, 0x02, 0x00, 0x50, 0x01, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x04, 0xff, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x02, 0xff, 0x01, 0x01, 0x00, 0x1e, 0x01, 0x00, 0x03, 0xff, 0x01, 0x01, 0x00, 0x2d, 0x01, 0x00, 0x04, 0xfe, 0x01, 0x01, 0x00, 0x3c, 0x01, 0x00, 0x05, 0xfe, 0x01, 0x01, 0x00, 0x4b, 0x02, 0x00, 0x06, 0xfe, 0x02, 0x02, 0x00, 0x5a, 0x02, 0x00, 0x07, 0xfd, 0x02, 0x02, 0x00, 0x63, 0x02, 0x00, 0x08, 0xfd, 0x02, 0x02, 0x00, 0x64, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0x00, 0x02, 0x04, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x02, 0xff, 0x01, 0x01, 0x00, 0x0f, 0x01, 0x00, 0x03, 0xff, 0x01, 0x01, 0x00, 0x19, 0x01, 0x00, 0x04, 0xfe, 0x01, 0x01, 0x00, 0x23, 0x01, 0x00, 0x05, 0xfe, 0x01, 0x02, 0x00, 0x2d, 0x02, 0x00, 0x06, 0xfe, 0x02, 0x02, 0x00, 0x37, 0x02, 0x00, 0x07, 0xfd, 0x02, 0x02, 0x00, 0x40, 0x02, 0x00, 0x08, 0xfd, 0x02, 0x02, 0x00, 0x41, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xc4, 0x2f, 0x00, 0xff, 0xff, 0xff, 0x06, 0x30, 0x00, 0x48, 0x30, 0x00, 0x8a, 0x30, 0x00, 0xcc, 0x30, 0x00, 0x0e, 0x31, 0x00, 0x50, 0x31, 0x00, 0x92, 0x31, 0x00, 0xd4, 0x31, 0x00, 0x16, 0x32, 0x00, 0xff, 0xff, 0xff, 0x58, 0x32, 0x00, 0xff, 0xff, 0xff, 0xba, 0x32, 0x00, 0x1c, 0x33, 0x00, 0x7e, 0x33, 0x00, 0xe0, 0x33, 0x00, 0x42, 0x34, 0x00, 0xa4, 0x34, 0x00, 0x06, 0x35, 0x00, 0x68, 0x35, 0x00, 0xca, 0x35, 0x00, 0xff, 0xff, 0xff, 0x2c, 0x36, 0x00, 0x3e, 0x36, 0x00, 0x80, 0x36, 0x00, 0xc2, 0x36, 0x00, 0x04, 0x37, 0x00, 0x46, 0x37, 0x00, 0x88, 0x37, 0x00, 0xca, 0x37, 0x00, 0x24, 0x38, 0x00, 0x9d, 0x38, 0x00, 0xf9, 0x38, 0x00, 0x7d, 0x39, 0x00, 0xd7, 0x39, 0x00, 0x50, 0x3a, 0x00, 0xac, 0x3a, 0x00, 0x30, 0x3b, 0x00, 0x72, 0x3b, 0x00, 0xb4, 0x3b, 0x00, 0xf6, 0x3b, 0x00, 0x38, 0x3c, 0x00, 0x7a, 0x3c, 0x00, 0xbc, 0x3c, 0x00, 0xfe, 0x3c, 0x00, 0x40, 0x3d, 0x00, 0x3a, 0x3e, 0x00, 0x34, 0x3f, 0x00, 0x2e, 0x40, 0x00, 0x28, 0x41, 0x00, 0x22, 0x42, 0x00, 0x98, 0x43, 0x00, 0xea, 0x43, 0x00, 0x3c, 0x44, 0x00, 0x8e, 0x44, 0x00, 0xe0, 0x44, 0x00, 0x32, 0x45, 0x00, 0x84, 0x45, 0x00, 0x7e, 0x46, 0x00, 0x78, 0x47, 0x00, 0xba, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0x76, 0x48, 0x00, 0xf0, 0x48, 0x00, 0x6a, 0x49, 0x00, 0xe4, 0x49, 0x00, 0x5e, 0x4a, 0x00, 0xd8, 0x4a, 0x00, 0x52, 0x4b, 0x00, 0xcc, 0x4b, 0x00, 0x46, 0x4c, 0x00, 0xc0, 0x4c, 0x00, 0x3a, 0x4d, 0x00, 0xb4, 0x4d, 0x00, 0x2e, 0x4e, 0x00, 0xa8, 0x4e, 0x00, 0x22, 0x4f, 0x00, 0x9c, 0x4f, 0x00, 0x16, 0x50, 0x00, 0x90, 0x50, 0x00, 0x0a, 0x51, 0x00, 0x84, 0x51, 0x00, 0xfe, 0x51, 0x00, 0x78, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0x6c, 0x53, 0x00, 0xe6, 0x53, 0x00, 0x60, 0x54, 0x00, 0xda, 0x54, 0x00, 0x54, 0x55, 0x00, 0xce, 0x55, 0x00, 0x48, 0x56, 0x00, 0xc2, 0x56, 0x00, 0x3c, 0x57, 0x00, 0xb6, 0x57, 0x00, 0x30, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0x24, 0x59, 0x00, 0x9e, 0x59, 0x00, 0x18, 0x5a, 0x00, 0x92, 0x5a, 0x00, 0x0c, 0x5b, 0x00, 0x86, 0x5b, 0x00, 0x00, 0x5c, 0x00, 0x7a, 0x5c, 0x00, 0xf4, 0x5c, 0x00, 0x6e, 0x5d, 0x00, 0xe8, 0x5d, 0x00, 0x62, 0x5e, 0x00, 0xdc, 0x5e, 0x00, 0x56, 0x5f, 0x00, 0xd0, 0x5f, 0x00, 0x4a, 0x60, 0x00, 0xc4, 0x60, 0x00, 0x3e, 0x61, 0x00, 0xb8, 0x61, 0x00, 0x32, 0x62, 0x00, 0xac, 0x62, 0x00, 0x26, 0x63, 0x00, 0xa0, 0x63, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x94, 0x64, 0x00, 0x0e, 0x65, 0x00, 0x88, 0x65, 0x00, 0x02, 0x66, 0x00, 0x7c, 0x66, 0x00, 0xf6, 0x66, 0x00, 0x70, 0x67, 0x00, 0xea, 0x67, 0x00, 0x64, 0x68, 0x00, 0xde, 0x68, 0x00, 0x58, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0x4c, 0x6a, 0x00, 0xc6, 0x6a, 0x00, 0x40, 0x6b, 0x00, 0xba, 0x6b, 0x00, 0x34, 0x6c, 0x00, 0xae, 0x6c, 0x00, 0x28, 0x6d, 0x00, 0xa2, 0x6d, 0x00, 0x1c, 0x6e, 0x00, 0x96, 0x6e, 0x00, 0x10, 0x6f, 0x00, 0x8a, 0x6f, 0x00, 0x04, 0x70, 0x00, 0x7e, 0x70, 0x00, 0xf8, 0x70, 0x00, 0x72, 0x71, 0x00, 0xec, 0x71, 0x00, 0x66, 0x72, 0x00, 0xe0, 0x72, 0x00, 0x5a, 0x73, 0x00, 0xd4, 0x73, 0x00, 0x4e, 0x74, 0x00, 0xc8, 0x74, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0xbc, 0x75, 0x00, 0x36, 0x76, 0x00, 0xb0, 0x76, 0x00, 0x2a, 0x77, 0x00, 0xa4, 0x77, 0x00, 0x1e, 0x78, 0x00, 0x98, 0x78, 0x00, 0x12, 0x79, 0x00, 0x8c, 0x79, 0x00, 0x06, 0x7a, 0x00, 0x80, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0x74, 0x7b, 0x00, 0xe2, 0x7b, 0x00, 0x50, 0x7c, 0x00, 0xbe, 0x7c, 0x00, 0x2c, 0x7d, 0x00, 0x9a, 0x7d, 0x00, 0x08, 0x7e, 0x00, 0x76, 0x7e, 0x00, 0xe4, 0x7e, 0x00, 0x52, 0x7f, 0x00, 0xc0, 0x7f, 0x00, 0x2e, 0x80, 0x00, 0x9c, 0x80, 0x00, 0x0a, 0x81, 0x00, 0x78, 0x81, 0x00, 0xe6, 0x81, 0x00, 0x54, 0x82, 0x00, 0xc2, 0x82, 0x00, 0x30, 0x83, 0x00, 0x9e, 0x83, 0x00, 0x0c, 0x84, 0x00, 0x7a, 0x84, 0x00, 0xe8, 0x84, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0xc4, 0x85, 0x00, 0x32, 0x86, 0x00, 0xa0, 0x86, 0x00, 0x0e, 0x87, 0x00, 0x7c, 0x87, 0x00, 0xea, 0x87, 0x00, 0x58, 0x88, 0x00, 0xc6, 0x88, 0x00, 0x34, 0x89, 0x00, 0xa2, 0x89, 0x00, 0x10, 0x8a, 0x00, 0x7e, 0x8a, 0x00, 0xec, 0x8a, 0x00, 0x2e, 0x8b, 0x00, 0xac, 0x8b, 0x00, 0x2a, 0x8c, 0x00, 0xa8, 0x8c, 0x00, 0x26, 0x8d, 0x00, 0xa4, 0x8d, 0x00, 0x22, 0x8e, 0x00, 0xa0, 0x8e, 0x00, 0x1e, 0x8f, 0x00, 0x60, 0x8f, 0x00, 0xa2, 0x8f, 0x00, 0xe4, 0x8f, 0x00, 0x13, 0x90, 0x00, 0x42, 0x90, 0x00, 0x65, 0x90, 0x00, 0x88, 0x90, 0x00, 0xab, 0x90, 0x00, 0xce, 0x90, 0x00, 0xf1, 0x90, 0x00, 0x57, 0x91, 0x00, 0xbd, 0x91, 0x00, 0x23, 0x92, 0x00, 0x89, 0x92, 0x00, 0xef, 0x92, 0x00, 0x55, 0x93, 0x00, 0xbb, 0x93, 0x00, 0x21, 0x94, 0x00, 0x87, 0x94, 0x00, 0xed, 0x94, 0x00, 0x53, 0x95, 0x00, 0xb9, 0x95, 0x00, 0x1f, 0x96, 0x00, 0x85, 0x96, 0x00, 0xeb, 0x96, 0x00, 0x51, 0x97, 0x00, 0xb7, 0x97, 0x00, 0x1d, 0x98, 0x00, 0x83, 0x98, 0x00, 0xe9, 0x98, 0x00, 0x4f, 0x99, 0x00, 0xb5, 0x99, 0x00, 0x1b, 0x9a, 0x00, 0x81, 0x9a, 0x00, 0xe7, 0x9a, 0x00, 0x4d, 0x9b, 0x00, 0xb3, 0x9b, 0x00, 0x19, 0x9c, 0x00, 0x7f, 0x9c, 0x00, 0xe5, 0x9c, 0x00, 0x4b, 0x9d, 0x00, 0xb1, 0x9d, 0x00, 0x17, 0x9e, 0x00, 0x7d, 0x9e, 0x00, 0xe3, 0x9e, 0x00, 0x49, 0x9f, 0x00, 0xaf, 0x9f, 0x00, 0x15, 0xa0, 0x00, 0x7b, 0xa0, 0x00, 0xe1, 0xa0, 0x00, 0x47, 0xa1, 0x00, 0xad, 0xa1, 0x00, 0x13, 0xa2, 0x00, 0x79, 0xa2, 0x00, 0xdf, 0xa2, 0x00, 0x45, 0xa3, 0x00, 0xab, 0xa3, 0x00, 0x11, 0xa4, 0x00, 0x77, 0xa4, 0x00, 0xdd, 0xa4, 0x00, 0x43, 0xa5, 0x00, 0xa9, 0xa5, 0x00, 0x0f, 0xa6, 0x00, 0x75, 0xa6, 0x00, 0xdb, 0xa6, 0x00, 0x41, 0xa7, 0x00, 0xa7, 0xa7, 0x00, 0x0d, 0xa8, 0x00, 0x73, 0xa8, 0x00, 0xd9, 0xa8, 0x00, 0x3f, 0xa9, 0x00, 0xa5, 0xa9, 0x00, 0x0b, 0xaa, 0x00, 0x71, 0xaa, 0x00, 0xd7, 0xaa, 0x00, 0x3d, 0xab, 0x00, 0xa3, 0xab, 0x00, 0x09, 0xac, 0x00, 0x6f, 0xac, 0x00, 0xd5, 0xac, 0x00, 0x3b, 0xad, 0x00, 0xa1, 0xad, 0x00, 0x07, 0xae, 0x00, 0x6d, 0xae, 0x00, 0xd3, 0xae, 0x00, 0x39, 0xaf, 0x00, 0x9f, 0xaf, 0x00, 0x05, 0xb0, 0x00, 0x6b, 0xb0, 0x00, 0xd1, 0xb0, 0x00, 0x37, 0xb1, 0x00, 0x9d, 0xb1, 0x00, 0x03, 0xb2, 0x00, 0x69, 0xb2, 0x00, 0xcf, 0xb2, 0x00, 0x35, 0xb3, 0x00, 0x9b, 0xb3, 0x00, 0x01, 0xb4, 0x00, 0x67, 0xb4, 0x00, 0xcd, 0xb4, 0x00, 0x33, 0xb5, 0x00, 0x99, 0xb5, 0x00, 0xff, 0xb5, 0x00, 0x65, 0xb6, 0x00, 0xcb, 0xb6, 0x00, 0x31, 0xb7, 0x00, 0x97, 0xb7, 0x00, 0xfd, 0xb7, 0x00, 0x63, 0xb8, 0x00, 0xc9, 0xb8, 0x00, 0x2f, 0xb9, 0x00, 0x95, 0xb9, 0x00, 0xfb, 0xb9, 0x00, 0x61, 0xba, 0x00, 0xc7, 0xba, 0x00, 0x2d, 0xbb, 0x00, 0x93, 0xbb, 0x00, 0xf9, 0xbb, 0x00, 0x5f, 0xbc, 0x00, 0xc5, 0xbc, 0x00, 0x2b, 0xbd, 0x00, 0x91, 0xbd, 0x00, 0xf7, 0xbd, 0x00, 0x5d, 0xbe, 0x00, 0xc3, 0xbe, 0x00, 0x29, 0xbf, 0x00, 0x8f, 0xbf, 0x00, 0xf5, 0xbf, 0x00, 0x5b, 0xc0, 0x00, 0xc1, 0xc0, 0x00, 0x27, 0xc1, 0x00, 0x8d, 0xc1, 0x00, 0xf3, 0xc1, 0x00, 0x59, 0xc2, 0x00, 0xbf, 0xc2, 0x00, 0x25, 0xc3, 0x00, 0x8b, 0xc3, 0x00, 0xf1, 0xc3, 0x00, 0x57, 0xc4, 0x00, 0xbd, 0xc4, 0x00, 0x23, 0xc5, 0x00, 0x89, 0xc5, 0x00, 0xef, 0xc5, 0x00, 0x55, 0xc6, 0x00, 0xbb, 0xc6, 0x00, 0x21, 0xc7, 0x00, 0x87, 0xc7, 0x00, 0xed, 0xc7, 0x00, 0x53, 0xc8, 0x00, 0xb9, 0xc8, 0x00, 0x1f, 0xc9, 0x00, 0x85, 0xc9, 0x00, 0xeb, 0xc9, 0x00, 0x51, 0xca, 0x00, 0xb7, 0xca, 0x00, 0x1d, 0xcb, 0x00, 0x83, 0xcb, 0x00, 0xe9, 0xcb, 0x00, 0x4f, 0xcc, 0x00, 0xb5, 0xcc, 0x00, 0x1b, 0xcd, 0x00, 0x81, 0xcd, 0x00, 0xe7, 0xcd, 0x00, 0x4d, 0xce, 0x00, 0xb3, 0xce, 0x00, 0x19, 0xcf, 0x00, 0x7f, 0xcf, 0x00, 0xe5, 0xcf, 0x00, 0x4b, 0xd0, 0x00, 0xb1, 0xd0, 0x00, 0x17, 0xd1, 0x00, 0x7d, 0xd1, 0x00, 0xe3, 0xd1, 0x00, 0x49, 0xd2, 0x00, 0xaf, 0xd2, 0x00, 0x15, 0xd3, 0x00, 0x7b, 0xd3, 0x00, 0xe1, 0xd3, 0x00, 0x47, 0xd4, 0x00, 0xad, 0xd4, 0x00, 0x13, 0xd5, 0x00, 0x79, 0xd5, 0x00, 0xdf, 0xd5, 0x00, 0x45, 0xd6, 0x00, 0xab, 0xd6, 0x00, 0x11, 0xd7, 0x00, 0x77, 0xd7, 0x00, 0xdd, 0xd7, 0x00, 0x43, 0xd8, 0x00, 0xa9, 0xd8, 0x00, 0x0f, 0xd9, 0x00, 0x75, 0xd9, 0x00, 0xdb, 0xd9, 0x00, 0x41, 0xda, 0x00, 0xa7, 0xda, 0x00, 0x0d, 0xdb, 0x00, 0x73, 0xdb, 0x00, 0xd9, 0xdb, 0x00, 0x3f, 0xdc, 0x00, 0xa5, 0xdc, 0x00, 0x0b, 0xdd, 0x00, 0x71, 0xdd, 0x00, 0xd7, 0xdd, 0x00, 0x3d, 0xde, 0x00, 0xa3, 0xde, 0x00, 0x09, 0xdf, 0x00, 0x6f, 0xdf, 0x00, 0xd5, 0xdf, 0x00, 0x3b, 0xe0, 0x00, 0xa1, 0xe0, 0x00, 0x07, 0xe1, 0x00, 0x6d, 0xe1, 0x00, 0xd3, 0xe1, 0x00, 0x39, 0xe2, 0x00, 0x9f, 0xe2, 0x00, 0x05, 0xe3, 0x00, 0x6b, 0xe3, 0x00, 0xd1, 0xe3, 0x00, 0x37, 0xe4, 0x00, 0x9d, 0xe4, 0x00, 0x03, 0xe5, 0x00, 0x69, 0xe5, 0x00, 0xcf, 0xe5, 0x00, 0x35, 0xe6, 0x00, 0x9b, 0xe6, 0x00, 0x01, 0xe7, 0x00, 0x67, 0xe7, 0x00, 0xcd, 0xe7, 0x00, 0x33, 0xe8, 0x00, 0x99, 0xe8, 0x00, 0xff, 0xe8, 0x00, 0x65, 0xe9, 0x00, 0xcb, 0xe9, 0x00, 0x31, 0xea, 0x00, 0x97, 0xea, 0x00, 0xfd, 0xea, 0x00, 0x63, 0xeb, 0x00, 0xc9, 0xeb, 0x00, 0x2f, 0xec, 0x00, 0x95, 0xec, 0x00, 0xfb, 0xec, 0x00, 0x61, 0xed, 0x00, 0xc7, 0xed, 0x00, 0x2d, 0xee, 0x00, 0x93, 0xee, 0x00, 0xf9, 0xee, 0x00, 0x5f, 0xef, 0x00, 0xc5, 0xef, 0x00, 0x2b, 0xf0, 0x00, 0x91, 0xf0, 0x00, 0xf7, 0xf0, 0x00, 0x5d, 0xf1, 0x00, 0xc3, 0xf1, 0x00, 0x29, 0xf2, 0x00, 0x8f, 0xf2, 0x00, 0xf5, 0xf2, 0x00, 0x5b, 0xf3, 0x00, 0xc1, 0xf3, 0x00, 0x27, 0xf4, 0x00, 0x8d, 0xf4, 0x00, 0xf3, 0xf4, 0x00, 0x59, 0xf5, 0x00, 0xbf, 0xf5, 0x00, 0x25, 0xf6, 0x00, 0x8b, 0xf6, 0x00, 0xf1, 0xf6, 0x00, 0x57, 0xf7, 0x00, 0xbd, 0xf7, 0x00, 0x23, 0xf8, 0x00, 0x89, 0xf8, 0x00, 0xef, 0xf8, 0x00, 0x55, 0xf9, 0x00, 0xbb, 0xf9, 0x00, 0x21, 0xfa, 0x00, 0x87, 0xfa, 0x00, 0xed, 0xfa, 0x00, 0x53, 0xfb, 0x00, 0xb9, 0xfb, 0x00, 0x1f, 0xfc, 0x00, 0x85, 0xfc, 0x00, 0xeb, 0xfc, 0x00, 0x51, 0xfd, 0x00, 0xb7, 0xfd, 0x00, 0x1d, 0xfe, 0x00, 0x83, 0xfe, 0x00, 0xe9, 0xfe, 0x00, 0x4f, 0xff, 0x00, 0xb5, 0xff, 0x00, 0x1b, 0x00, 0x01, 0x81, 0x00, 0x01, 0xe7, 0x00, 0x01, 0x4d, 0x01, 0x01, 0xb3, 0x01, 0x01, 0x19, 0x02, 0x01, 0x7f, 0x02, 0x01, 0xe5, 0x02, 0x01, 0x4b, 0x03, 0x01, 0xb1, 0x03, 0x01, 0x17, 0x04, 0x01, 0x7d, 0x04, 0x01, 0xe3, 0x04, 0x01, 0x49, 0x05, 0x01, 0xaf, 0x05, 0x01, 0x15, 0x06, 0x01, 0x7b, 0x06, 0x01, 0xe1, 0x06, 0x01, 0x47, 0x07, 0x01, 0xad, 0x07, 0x01, 0x13, 0x08, 0x01, 0x79, 0x08, 0x01, 0xdf, 0x08, 0x01, 0x45, 0x09, 0x01, 0xab, 0x09, 0x01, 0x11, 0x0a, 0x01, 0x77, 0x0a, 0x01, 0xdd, 0x0a, 0x01, 0x43, 0x0b, 0x01, 0xa9, 0x0b, 0x01, 0x0f, 0x0c, 0x01, 0x75, 0x0c, 0x01, 0xdb, 0x0c, 0x01, 0x41, 0x0d, 0x01, 0xa7, 0x0d, 0x01, 0x0d, 0x0e, 0x01, 0x73, 0x0e, 0x01, 0xd9, 0x0e, 0x01, 0x3f, 0x0f, 0x01, 0xa5, 0x0f, 0x01, 0x0b, 0x10, 0x01, 0x71, 0x10, 0x01, 0xd7, 0x10, 0x01, 0x3d, 0x11, 0x01, 0xa3, 0x11, 0x01, 0x09, 0x12, 0x01, 0x6f, 0x12, 0x01, 0xd5, 0x12, 0x01, 0x3b, 0x13, 0x01, 0xa1, 0x13, 0x01, 0x07, 0x14, 0x01, 0x6d, 0x14, 0x01, 0xd3, 0x14, 0x01, 0x39, 0x15, 0x01, 0x9f, 0x15, 0x01, 0x05, 0x16, 0x01, 0x6b, 0x16, 0x01, 0xd1, 0x16, 0x01, 0x37, 0x17, 0x01, 0x9d, 0x17, 0x01, 0x03, 0x18, 0x01, 0x69, 0x18, 0x01, 0xcf, 0x18, 0x01, 0x35, 0x19, 0x01, 0x9b, 0x19, 0x01, 0x01, 0x1a, 0x01, 0x67, 0x1a, 0x01, 0xcd, 0x1a, 0x01, 0x33, 0x1b, 0x01, 0x99, 0x1b, 0x01, 0xff, 0x1b, 0x01, 0x65, 0x1c, 0x01, 0xcb, 0x1c, 0x01, 0x31, 0x1d, 0x01, 0x97, 0x1d, 0x01, 0xfd, 0x1d, 0x01, 0x63, 0x1e, 0x01, 0xc9, 0x1e, 0x01, 0x2f, 0x1f, 0x01, 0x95, 0x1f, 0x01, 0xfb, 0x1f, 0x01, 0x61, 0x20, 0x01, 0xc7, 0x20, 0x01, 0x2d, 0x21, 0x01, 0x93, 0x21, 0x01, 0xf9, 0x21, 0x01, 0x5f, 0x22, 0x01, 0xc5, 0x22, 0x01, 0x2b, 0x23, 0x01, 0x91, 0x23, 0x01, 0xf7, 0x23, 0x01, 0x5d, 0x24, 0x01, 0xc3, 0x24, 0x01, 0x29, 0x25, 0x01, 0x8f, 0x25, 0x01, 0xf5, 0x25, 0x01, 0x5b, 0x26, 0x01, 0xc1, 0x26, 0x01, 0x27, 0x27, 0x01, 0x8d, 0x27, 0x01, 0xf3, 0x27, 0x01, 0x59, 0x28, 0x01, 0xbf, 0x28, 0x01, 0x25, 0x29, 0x01, 0x8b, 0x29, 0x01, 0xf1, 0x29, 0x01, 0x57, 0x2a, 0x01, 0xbd, 0x2a, 0x01, 0x23, 0x2b, 0x01, 0x89, 0x2b, 0x01, 0xef, 0x2b, 0x01, 0x55, 0x2c, 0x01, 0xbb, 0x2c, 0x01, 0x21, 0x2d, 0x01, 0x87, 0x2d, 0x01, 0xed, 0x2d, 0x01, 0x53, 0x2e, 0x01, 0xb9, 0x2e, 0x01, 0x1f, 0x2f, 0x01, 0x85, 0x2f, 0x01, 0xeb, 0x2f, 0x01, 0x51, 0x30, 0x01, 0xb7, 0x30, 0x01, 0x1d, 0x31, 0x01, 0x83, 0x31, 0x01, 0xe9, 0x31, 0x01, 0x4f, 0x32, 0x01, 0xb5, 0x32, 0x01, 0x1b, 0x33, 0x01, 0x81, 0x33, 0x01, 0xe7, 0x33, 0x01, 0x4d, 0x34, 0x01, 0xb3, 0x34, 0x01, 0x19, 0x35, 0x01, 0x7f, 0x35, 0x01, 0xe5, 0x35, 0x01, 0x4b, 0x36, 0x01, 0xb1, 0x36, 0x01, 0x17, 0x37, 0x01, 0x7d, 0x37, 0x01, 0xe3, 0x37, 0x01, 0x49, 0x38, 0x01, 0xaf, 0x38, 0x01, 0x15, 0x39, 0x01, 0x7b, 0x39, 0x01, 0xe1, 0x39, 0x01, 0x47, 0x3a, 0x01, 0xad, 0x3a, 0x01, 0x13, 0x3b, 0x01, 0x79, 0x3b, 0x01, 0xdf, 0x3b, 0x01, 0x45, 0x3c, 0x01, 0xab, 0x3c, 0x01, 0x11, 0x3d, 0x01, 0x77, 0x3d, 0x01, 0xdd, 0x3d, 0x01, 0x43, 0x3e, 0x01, 0xa9, 0x3e, 0x01, 0x0f, 0x3f, 0x01, 0x75, 0x3f, 0x01, 0xdb, 0x3f, 0x01, 0x41, 0x40, 0x01, 0xa7, 0x40, 0x01, 0x0d, 0x41, 0x01, 0x73, 0x41, 0x01, 0xd9, 0x41, 0x01, 0x3f, 0x42, 0x01, 0xa5, 0x42, 0x01, 0x0b, 0x43, 0x01, 0x71, 0x43, 0x01, 0xd7, 0x43, 0x01, 0x3d, 0x44, 0x01, 0xa3, 0x44, 0x01, 0x09, 0x45, 0x01, 0x6f, 0x45, 0x01, 0xd5, 0x45, 0x01, 0x3b, 0x46, 0x01, 0xa1, 0x46, 0x01, 0x07, 0x47, 0x01, 0x6d, 0x47, 0x01, 0xd3, 0x47, 0x01, 0x39, 0x48, 0x01, 0x9f, 0x48, 0x01, 0x05, 0x49, 0x01, 0x6b, 0x49, 0x01, 0xd1, 0x49, 0x01, 0x37, 0x4a, 0x01, 0x9d, 0x4a, 0x01, 0x03, 0x4b, 0x01, 0x69, 0x4b, 0x01, 0xcf, 0x4b, 0x01, 0x35, 0x4c, 0x01, 0x9b, 0x4c, 0x01, 0x01, 0x4d, 0x01, 0x67, 0x4d, 0x01, 0xcd, 0x4d, 0x01, 0x33, 0x4e, 0x01, 0x99, 0x4e, 0x01, 0xff, 0x4e, 0x01, 0x65, 0x4f, 0x01, 0xcb, 0x4f, 0x01, 0x31, 0x50, 0x01, 0x97, 0x50, 0x01, 0xfd, 0x50, 0x01, 0x63, 0x51, 0x01, 0xc9, 0x51, 0x01, 0x2f, 0x52, 0x01, 0x95, 0x52, 0x01, 0xfb, 0x52, 0x01, 0x61, 0x53, 0x01, 0xc7, 0x53, 0x01, 0x2d, 0x54, 0x01, 0x93, 0x54, 0x01, 0xf9, 0x54, 0x01, 0x5f, 0x55, 0x01, 0xc5, 0x55, 0x01, 0x2b, 0x56, 0x01, 0x91, 0x56, 0x01, 0xf7, 0x56, 0x01, 0x5d, 0x57, 0x01, 0xc3, 0x57, 0x01, 0x29, 0x58, 0x01, 0x8f, 0x58, 0x01, 0xf5, 0x58, 0x01, 0x5b, 0x59, 0x01, 0xc1, 0x59, 0x01, 0x27, 0x5a, 0x01, 0x8d, 0x5a, 0x01, 0xf3, 0x5a, 0x01, 0x59, 0x5b, 0x01, 0xbf, 0x5b, 0x01, 0x25, 0x5c, 0x01, 0x8b, 0x5c, 0x01, 0xf1, 0x5c, 0x01, 0x57, 0x5d, 0x01, 0xbd, 0x5d, 0x01, 0x23, 0x5e, 0x01, 0x89, 0x5e, 0x01, 0xef, 0x5e, 0x01, 0x55, 0x5f, 0x01, 0xbb, 0x5f, 0x01, 0x21, 0x60, 0x01, 0x87, 0x60, 0x01, 0xed, 0x60, 0x01, 0x53, 0x61, 0x01, 0xb9, 0x61, 0x01, 0x1f, 0x62, 0x01, 0x85, 0x62, 0x01, 0xeb, 0x62, 0x01, 0x51, 0x63, 0x01, 0xb7, 0x63, 0x01, 0x1d, 0x64, 0x01, 0x83, 0x64, 0x01, 0xe9, 0x64, 0x01, 0x4f, 0x65, 0x01, 0xb5, 0x65, 0x01, 0x1b, 0x66, 0x01, 0x81, 0x66, 0x01, 0xe7, 0x66, 0x01, 0x4d, 0x67, 0x01, 0xb3, 0x67, 0x01, 0x19, 0x68, 0x01, 0x7f, 0x68, 0x01, 0xe5, 0x68, 0x01, 0x4b, 0x69, 0x01, 0xb1, 0x69, 0x01, 0x17, 0x6a, 0x01, 0x7d, 0x6a, 0x01, 0xe3, 0x6a, 0x01, 0x49, 0x6b, 0x01, 0xaf, 0x6b, 0x01, 0x15, 0x6c, 0x01, 0x7b, 0x6c, 0x01, 0xe1, 0x6c, 0x01, 0x47, 0x6d, 0x01, 0xad, 0x6d, 0x01, 0x13, 0x6e, 0x01, 0x79, 0x6e, 0x01, 0xdf, 0x6e, 0x01, 0x45, 0x6f, 0x01, 0xab, 0x6f, 0x01, 0x11, 0x70, 0x01, 0x77, 0x70, 0x01, 0xdd, 0x70, 0x01, 0x43, 0x71, 0x01, 0xa9, 0x71, 0x01, 0x0f, 0x72, 0x01, 0x75, 0x72, 0x01, 0xdb, 0x72, 0x01, 0x41, 0x73, 0x01, 0xa7, 0x73, 0x01, 0x0d, 0x74, 0x01, 0x73, 0x74, 0x01, 0xd9, 0x74, 0x01, 0x3f, 0x75, 0x01, 0xa5, 0x75, 0x01, 0x0b, 0x76, 0x01, 0x71, 0x76, 0x01, 0xd7, 0x76, 0x01, 0x3d, 0x77, 0x01, 0xa3, 0x77, 0x01, 0x09, 0x78, 0x01, 0x6f, 0x78, 0x01, 0xd5, 0x78, 0x01, 0x3b, 0x79, 0x01, 0xa1, 0x79, 0x01, 0x07, 0x7a, 0x01, 0x6d, 0x7a, 0x01, 0xd3, 0x7a, 0x01, 0x39, 0x7b, 0x01, 0x9f, 0x7b, 0x01, 0x05, 0x7c, 0x01, 0x6b, 0x7c, 0x01, 0xd1, 0x7c, 0x01, 0x37, 0x7d, 0x01, 0x9d, 0x7d, 0x01, 0x03, 0x7e, 0x01, 0x69, 0x7e, 0x01, 0xcf, 0x7e, 0x01, 0x35, 0x7f, 0x01, 0x9b, 0x7f, 0x01, 0x01, 0x80, 0x01, 0x67, 0x80, 0x01, 0xcd, 0x80, 0x01, 0x33, 0x81, 0x01, 0x99, 0x81, 0x01, 0xff, 0x81, 0x01, 0x65, 0x82, 0x01, 0xcb, 0x82, 0x01, 0x31, 0x83, 0x01, 0x97, 0x83, 0x01, 0xfd, 0x83, 0x01, 0x63, 0x84, 0x01, 0xc9, 0x84, 0x01, 0x2f, 0x85, 0x01, 0x95, 0x85, 0x01, 0xfb, 0x85, 0x01, 0x61, 0x86, 0x01, 0xc7, 0x86, 0x01, 0x2d, 0x87, 0x01, 0x93, 0x87, 0x01, 0xf9, 0x87, 0x01, 0x5f, 0x88, 0x01, 0xc5, 0x88, 0x01, 0x2b, 0x89, 0x01, 0x91, 0x89, 0x01, 0xf7, 0x89, 0x01, 0x5d, 0x8a, 0x01, 0xc3, 0x8a, 0x01, 0x29, 0x8b, 0x01, 0x8f, 0x8b, 0x01, 0xf5, 0x8b, 0x01, 0x5b, 0x8c, 0x01, 0xc1, 0x8c, 0x01, 0x27, 0x8d, 0x01, 0x8d, 0x8d, 0x01, 0xf3, 0x8d, 0x01, 0x59, 0x8e, 0x01, 0xbf, 0x8e, 0x01, 0x25, 0x8f, 0x01, 0x8b, 0x8f, 0x01, 0xf1, 0x8f, 0x01, 0x57, 0x90, 0x01, 0xbd, 0x90, 0x01, 0x23, 0x91, 0x01, 0x89, 0x91, 0x01, 0xef, 0x91, 0x01, 0x55, 0x92, 0x01, 0xbb, 0x92, 0x01, 0x21, 0x93, 0x01, 0x87, 0x93, 0x01, 0xed, 0x93, 0x01, 0x53, 0x94, 0x01, 0xb9, 0x94, 0x01, 0x1f, 0x95, 0x01, 0x85, 0x95, 0x01, 0xeb, 0x95, 0x01, 0x51, 0x96, 0x01, 0xb7, 0x96, 0x01, 0x1d, 0x97, 0x01, 0x83, 0x97, 0x01, 0xe9, 0x97, 0x01, 0x4f, 0x98, 0x01, 0xb5, 0x98, 0x01, 0x1b, 0x99, 0x01, 0x81, 0x99, 0x01, 0xe7, 0x99, 0x01, 0x4d, 0x9a, 0x01, 0xb3, 0x9a, 0x01, 0x19, 0x9b, 0x01, 0x7f, 0x9b, 0x01, 0xe5, 0x9b, 0x01, 0x4b, 0x9c, 0x01, 0xb1, 0x9c, 0x01, 0x17, 0x9d, 0x01, 0x7d, 0x9d, 0x01, 0xe3, 0x9d, 0x01, 0x49, 0x9e, 0x01, 0xaf, 0x9e, 0x01, 0x15, 0x9f, 0x01, 0x7b, 0x9f, 0x01, 0xe1, 0x9f, 0x01, 0x47, 0xa0, 0x01, 0xad, 0xa0, 0x01, 0x13, 0xa1, 0x01, 0x79, 0xa1, 0x01, 0xdf, 0xa1, 0x01, 0x45, 0xa2, 0x01, 0xab, 0xa2, 0x01, 0x11, 0xa3, 0x01, 0x77, 0xa3, 0x01, 0xdd, 0xa3, 0x01, 0x43, 0xa4, 0x01, 0xa9, 0xa4, 0x01, 0x0f, 0xa5, 0x01, 0x75, 0xa5, 0x01, 0xdb, 0xa5, 0x01, 0x41, 0xa6, 0x01, 0xa7, 0xa6, 0x01, 0x0d, 0xa7, 0x01, 0x73, 0xa7, 0x01, 0xd9, 0xa7, 0x01, 0x3f, 0xa8, 0x01, 0xa5, 0xa8, 0x01, 0x0b, 0xa9, 0x01, 0x71, 0xa9, 0x01, 0xd7, 0xa9, 0x01, 0x3d, 0xaa, 0x01, 0xa3, 0xaa, 0x01, 0x09, 0xab, 0x01, 0x6f, 0xab, 0x01, 0xd5, 0xab, 0x01, 0x3b, 0xac, 0x01, 0xa1, 0xac, 0x01, 0x07, 0xad, 0x01, 0x6d, 0xad, 0x01, 0xd3, 0xad, 0x01, 0x39, 0xae, 0x01, 0x9f, 0xae, 0x01, 0x05, 0xaf, 0x01, 0x6b, 0xaf, 0x01, 0xd1, 0xaf, 0x01, 0x37, 0xb0, 0x01, 0x9d, 0xb0, 0x01, 0x03, 0xb1, 0x01, 0x69, 0xb1, 0x01, 0xcf, 0xb1, 0x01, 0x35, 0xb2, 0x01, 0x9b, 0xb2, 0x01, 0x01, 0xb3, 0x01, 0x67, 0xb3, 0x01, 0xcd, 0xb3, 0x01, 0x33, 0xb4, 0x01, 0x99, 0xb4, 0x01, 0xff, 0xb4, 0x01, 0x65, 0xb5, 0x01, 0xcb, 0xb5, 0x01, 0x31, 0xb6, 0x01, 0x97, 0xb6, 0x01, 0xfd, 0xb6, 0x01, 0x63, 0xb7, 0x01, 0xc9, 0xb7, 0x01, 0x2f, 0xb8, 0x01, 0x95, 0xb8, 0x01, 0xfb, 0xb8, 0x01, 0x61, 0xb9, 0x01, 0xc7, 0xb9, 0x01, 0x2d, 0xba, 0x01, 0x93, 0xba, 0x01, 0xf9, 0xba, 0x01, 0x5f, 0xbb, 0x01, 0xc5, 0xbb, 0x01, 0x2b, 0xbc, 0x01, 0x91, 0xbc, 0x01, 0xf7, 0xbc, 0x01, 0x5d, 0xbd, 0x01, 0xc3, 0xbd, 0x01, 0x29, 0xbe, 0x01, 0x8f, 0xbe, 0x01, 0xf5, 0xbe, 0x01, 0x5b, 0xbf, 0x01, 0xc1, 0xbf, 0x01, 0x27, 0xc0, 0x01, 0x8d, 0xc0, 0x01, 0xf3, 0xc0, 0x01, 0x59, 0xc1, 0x01, 0xbf, 0xc1, 0x01, 0x25, 0xc2, 0x01, 0x8b, 0xc2, 0x01, 0xf1, 0xc2, 0x01, 0x57, 0xc3, 0x01, 0xbd, 0xc3, 0x01, 0x23, 0xc4, 0x01, 0x89, 0xc4, 0x01, 0xef, 0xc4, 0x01, 0x55, 0xc5, 0x01, 0xbb, 0xc5, 0x01, 0x21, 0xc6, 0x01, 0x87, 0xc6, 0x01, 0xed, 0xc6, 0x01, 0x53, 0xc7, 0x01, 0xb9, 0xc7, 0x01, 0x1f, 0xc8, 0x01, 0x85, 0xc8, 0x01, 0xeb, 0xc8, 0x01, 0x51, 0xc9, 0x01, 0xb7, 0xc9, 0x01, 0x1d, 0xca, 0x01, 0x83, 0xca, 0x01, 0xe9, 0xca, 0x01, 0x4f, 0xcb, 0x01, 0xb5, 0xcb, 0x01, 0x1b, 0xcc, 0x01, 0x1f, 0x04, 0x07, 0x04, 0x04, 0x02, 0x03, 0x10, 0x00, 0x00, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x0a, 0x06, 0x00, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x10, 0x00, 0x00, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x1f, 0x00, 0x08, 0x00, 0x06, 0x00, 0x03, 0x0a, 0x06, 0x00, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x1e, 0x0b, 0x06, 0x04, 0x04, 0x03, 0x04, 0x0c, 0x04, 0x00, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x13, 0xf8, 0x01, 0x87, 0xf9, 0x01, 0x87, 0xf9, 0x01, 0x35, 0xee, 0x01, 0xa9, 0xf2, 0x01, 0xa9, 0xf2, 0x01, 0x35, 0xee, 0x01, 0xa9, 0xf2, 0x01, 0xa9, 0xf2, 0x01, 0x1e, 0x04, 0x0b, 0x04, 0x08, 0x02, 0x06, 0x04, 0x06, 0x06, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x18, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x0a, 0x06, 0x00, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x08, 0x04, 0x04, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0xb7, 0x11, 0x02, 0x21, 0x17, 0x02, 0x09, 0x1d, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x03, 0x05, 0x08, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0x7c, 0x00, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x73, 0x30, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xf0, 0x3c, 0x03, 0x55, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0xff, 0x00, 0x03, 0x55, 0x55, 0xff, 0x00, 0x3d, 0x55, 0x55, 0xff, 0x00, 0xcd, 0x55, 0x55, 0xcf, 0xff, 0x0d, 0x55, 0x55, 0x73, 0x30, 0x3d, 0x55, 0x55, 0x73, 0xf0, 0xf5, 0x55, 0x55, 0x73, 0xf0, 0x35, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x7f, 0x55, 0x57, 0xff, 0x55, 0xff, 0xd5, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x0f, 0x00, 0xf0, 0xd5, 0x57, 0x30, 0xc3, 0x0c, 0xd5, 0x57, 0x00, 0x3c, 0x00, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x57, 0x3f, 0xff, 0xfc, 0xd5, 0x57, 0xf0, 0xc3, 0x0f, 0xd5, 0x55, 0x73, 0xff, 0xcd, 0x55, 0x55, 0xc3, 0xff, 0xc3, 0x55, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x03, 0x00, 0xc0, 0xd5, 0x57, 0x0c, 0x00, 0x30, 0xd5, 0x57, 0x00, 0x3c, 0x00, 0xd5, 0x55, 0xc0, 0xff, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x3f, 0x0f, 0xc3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x00, 0xf0, 0x0d, 0x55, 0x55, 0xff, 0x0f, 0xf5, 0x55, 0x57, 0x33, 0xfc, 0xcd, 0x55, 0x57, 0xf3, 0xfc, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x30, 0x00, 0x0c, 0xd5, 0x57, 0x0c, 0x00, 0x30, 0xd5, 0x57, 0x00, 0xff, 0x00, 0xd5, 0x5f, 0x03, 0xff, 0xc0, 0xf5, 0x5c, 0xc3, 0xff, 0xc3, 0x35, 0x5f, 0x3f, 0xff, 0xfc, 0xf5, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0xc3, 0xff, 0xc3, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x7f, 0x55, 0x57, 0xff, 0x55, 0xff, 0xd5, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x03, 0x00, 0xc0, 0xd5, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x30, 0x3c, 0x0c, 0xd5, 0x55, 0xcc, 0x3c, 0x33, 0xd5, 0x55, 0xcc, 0x3c, 0x33, 0x55, 0x55, 0xc3, 0xc3, 0xc3, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xd7, 0xf5, 0x55, 0x55, 0x5f, 0x55, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x5c, 0x3f, 0xff, 0xc3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x55, 0xff, 0xff, 0xf5, 0x55, 0x55, 0xc0, 0x00, 0x35, 0x55, 0x57, 0x30, 0x00, 0xcd, 0x55, 0x57, 0xf0, 0x00, 0xfd, 0x55, 0x55, 0x70, 0x00, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0x55, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0x70, 0x00, 0x3d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x70, 0x0c, 0xd5, 0x55, 0x57, 0xc0, 0xfc, 0xd5, 0x55, 0x55, 0xf0, 0x3f, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0x57, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0x70, 0x00, 0x3d, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x30, 0xcd, 0x55, 0x55, 0xfc, 0x3f, 0xf5, 0x55, 0x55, 0x70, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x70, 0x3f, 0xf5, 0x55, 0x55, 0xc0, 0x0f, 0xf5, 0x55, 0x7f, 0xc0, 0x0f, 0xf5, 0x5f, 0xc0, 0xc0, 0x0f, 0x55, 0x5f, 0xc0, 0xc0, 0xcf, 0xd5, 0x55, 0xc0, 0xc0, 0xcf, 0xd5, 0x57, 0xc0, 0x3c, 0xcf, 0xf5, 0x5f, 0xfc, 0x03, 0x0f, 0xf5, 0x5f, 0xff, 0xff, 0xf7, 0xd5, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x3c, 0x03, 0xc3, 0x55, 0x5c, 0xc3, 0x0c, 0x33, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0xc3, 0x0c, 0x33, 0x55, 0x57, 0x30, 0xf0, 0xcc, 0xd5, 0x55, 0xff, 0xff, 0xf0, 0xd5, 0x55, 0x73, 0x0c, 0x03, 0x55, 0x55, 0xcc, 0xfc, 0x0d, 0x55, 0x55, 0xfc, 0xff, 0x0d, 0x55, 0x55, 0x5c, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x55, 0xf5, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x00, 0xc3, 0x00, 0xd5, 0x57, 0x3f, 0xc3, 0xfc, 0xd5, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x5c, 0xcc, 0x35, 0x55, 0x55, 0x73, 0xff, 0xcd, 0x55, 0x55, 0x70, 0xfc, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xc0, 0x30, 0x03, 0x55, 0x55, 0xc0, 0xc0, 0x03, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xfc, 0x00, 0x03, 0x55, 0x55, 0xff, 0x03, 0xc3, 0x55, 0x55, 0x7f, 0x03, 0x3d, 0x55, 0x55, 0x5f, 0xff, 0x35, 0x55, 0x55, 0x5c, 0xcc, 0x0d, 0x55, 0x55, 0x57, 0x3c, 0x03, 0x55, 0x55, 0x57, 0x3c, 0x3f, 0x55, 0x55, 0x57, 0xff, 0xf5, 0x55, 0x55, 0x55, 0x7d, 0xfd, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0x7f, 0x55, 0x55, 0x55, 0xff, 0xff, 0xd5, 0x55, 0x55, 0xff, 0xff, 0xd5, 0x55, 0x55, 0xff, 0x00, 0x35, 0x55, 0x57, 0xf0, 0x00, 0x3d, 0x55, 0x57, 0xc0, 0x03, 0x03, 0x55, 0x57, 0x00, 0x3c, 0x03, 0x55, 0x57, 0x00, 0x00, 0x0f, 0x55, 0x57, 0x00, 0x00, 0x35, 0x55, 0x57, 0xc0, 0x03, 0xd5, 0x55, 0x55, 0x7f, 0xff, 0x55, 0x55, 0x55, 0xc0, 0xcf, 0x55, 0x55, 0x57, 0x30, 0xfd, 0x55, 0x55, 0x57, 0xf0, 0xfd, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x7d, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xf5, 0x55, 0x55, 0x5f, 0xfd, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0x00, 0x0d, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x0f, 0xc3, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0x70, 0x00, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x5c, 0x3c, 0xd5, 0x55, 0x55, 0x5f, 0x0f, 0xd5, 0x55, 0x55, 0x5c, 0xff, 0xd5, 0x55, 0x55, 0x70, 0x0f, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3c, 0x0f, 0x55, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0xc0, 0x00, 0xff, 0x55, 0x55, 0xc0, 0xf0, 0xff, 0x55, 0x55, 0x70, 0xcc, 0xfd, 0x55, 0x55, 0x5f, 0xcf, 0xd5, 0x55, 0x55, 0x5c, 0xcc, 0xd5, 0x55, 0x55, 0x5c, 0x3f, 0xd5, 0x55, 0x55, 0x5c, 0x0f, 0xd5, 0x55, 0x55, 0x70, 0x0f, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x55, 0xfd, 0x55, 0x55, 0x7f, 0xdf, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0xc3, 0x55, 0x55, 0xcc, 0x00, 0x03, 0x55, 0x55, 0x73, 0x00, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x73, 0x30, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0x7f, 0x55, 0x55, 0xff, 0xd5, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0xd5, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0x70, 0x00, 0x03, 0x55, 0x55, 0xc3, 0x00, 0x30, 0xd5, 0x55, 0xcc, 0xc0, 0xcc, 0xd5, 0x55, 0xc3, 0x00, 0x30, 0xd5, 0x57, 0xc0, 0x3f, 0x00, 0xd5, 0x57, 0x30, 0xff, 0xc3, 0x55, 0x55, 0xcf, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xc3, 0xfc, 0x03, 0x55, 0x55, 0xc3, 0xfc, 0x3c, 0xd5, 0x55, 0x7f, 0xfc, 0x37, 0xd5, 0x55, 0x5f, 0x7f, 0xd5, 0x55, 0x55, 0x55, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x3c, 0x03, 0xc3, 0x55, 0x5c, 0xf3, 0x0f, 0x33, 0x55, 0x5c, 0xff, 0x0f, 0xf3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x0f, 0xf0, 0x0d, 0x55, 0x55, 0xfc, 0x3f, 0xf5, 0x55, 0x55, 0xc3, 0xcc, 0x3d, 0x55, 0x55, 0x70, 0xfc, 0xf3, 0x55, 0x55, 0x70, 0xfc, 0xdf, 0x55, 0x55, 0x7f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xcd, 0x55, 0x5f, 0xff, 0xff, 0xfd, 0x55, 0x7f, 0xff, 0xff, 0xd5, 0x55, 0x70, 0x00, 0x03, 0xd5, 0x55, 0xff, 0xff, 0xfc, 0xd5, 0x55, 0xc0, 0x00, 0x0f, 0xd5, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0x7c, 0x00, 0x0c, 0xd5, 0x55, 0x5f, 0xff, 0xf0, 0x35, 0x55, 0x7f, 0x3f, 0xfc, 0x0d, 0x55, 0x7f, 0x3f, 0xfc, 0x0d, 0x55, 0x70, 0x00, 0x3c, 0x0d, 0x55, 0x7f, 0xff, 0xf0, 0x0d, 0x55, 0x5f, 0xff, 0xdf, 0xf5, 0x55, 0x7f, 0xdf, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0x55, 0x55, 0x55, 0x57, 0x35, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0xff, 0xff, 0x55, 0x55, 0x5f, 0xff, 0xff, 0x55, 0x55, 0x70, 0x00, 0x0f, 0x55, 0x55, 0x7f, 0xff, 0xf3, 0xfd, 0x55, 0xc0, 0x00, 0x0c, 0xc3, 0x55, 0xc0, 0x00, 0x03, 0xc3, 0x55, 0xc0, 0x00, 0x03, 0x03, 0x55, 0xf0, 0x03, 0x03, 0xc3, 0x55, 0xc3, 0xc0, 0x0f, 0xc3, 0x55, 0xc3, 0xc0, 0x3f, 0x0d, 0x55, 0x7f, 0xff, 0xfc, 0x35, 0x5d, 0xff, 0x3f, 0xf3, 0xd5, 0x5f, 0x00, 0x00, 0xfd, 0x55, 0x5f, 0xff, 0xff, 0x3d, 0x55, 0x55, 0xff, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xff, 0x55, 0x55, 0x7f, 0xff, 0xff, 0xd5, 0x55, 0xf0, 0x00, 0x03, 0xf5, 0x55, 0xcf, 0xff, 0xfc, 0xf5, 0x55, 0xf0, 0x00, 0x03, 0xff, 0x57, 0x0f, 0xc0, 0xfc, 0xf3, 0x57, 0x33, 0xc3, 0x3c, 0xdf, 0x57, 0x33, 0xc3, 0x3c, 0xd5, 0x57, 0x0f, 0xc0, 0xfc, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x35, 0x55, 0xff, 0xff, 0xfc, 0x0d, 0x57, 0xff, 0xcf, 0xf3, 0x0d, 0x5c, 0xff, 0xcf, 0xff, 0x0d, 0x57, 0x70, 0x00, 0x0c, 0x0d, 0x55, 0x7f, 0xff, 0xf7, 0xf5, 0x55, 0x57, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xf7, 0xfd, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xff, 0xf5, 0x55, 0x70, 0x00, 0xff, 0xff, 0x55, 0x7f, 0xfc, 0x03, 0xf3, 0x55, 0xf0, 0xff, 0xf0, 0xdf, 0x55, 0xf0, 0xf3, 0x0f, 0xd5, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xff, 0xf0, 0x33, 0x55, 0x57, 0x3f, 0xc0, 0xff, 0xd5, 0x57, 0xcf, 0xff, 0xfc, 0x35, 0x55, 0xff, 0x3f, 0xfc, 0x0d, 0x55, 0x7f, 0x3f, 0xf0, 0x0d, 0x55, 0x7f, 0x3f, 0xf0, 0x0d, 0x55, 0x70, 0x00, 0xf0, 0x0d, 0x55, 0x5f, 0xff, 0xdf, 0xf5, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x55, 0xf7, 0xd5, 0x55, 0x30, 0x1f, 0x01, 0x55, 0x40, 0x00, 0x00, 0x00, 0x15, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x11, 0x41, 0x50, 0x00, 0x00, 0x15, 0x55, 0x55, 0x54, 0x04, 0x10, 0x01, 0x55, 0x41, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa1, 0x14, 0x15, 0x54, 0x01, 0x11, 0x45, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa5, 0x54, 0x15, 0x54, 0x01, 0x55, 0x45, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa1, 0x14, 0x44, 0x11, 0x55, 0x55, 0x55, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x15, 0x40, 0x01, 0x55, 0x11, 0x56, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x95, 0x40, 0x01, 0x55, 0x55, 0x56, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x95, 0x55, 0x55, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x55, 0x50, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x01, 0x50, 0x55, 0x50, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x15, 0x55, 0x55, 0x54, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x02, 0x55, 0x55, 0x55, 0x00, 0x04, 0x00, 0x80, 0x28, 0x00, 0x00, 0xa0, 0x02, 0x01, 0x15, 0x55, 0x10, 0x04, 0x55, 0x80, 0x28, 0x00, 0x00, 0xa0, 0x02, 0x01, 0x15, 0x55, 0x01, 0x55, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x02, 0x55, 0x55, 0x55, 0x01, 0x01, 0x00, 0x80, 0xaa, 0xaa, 0xaa, 0xa8, 0x02, 0x00, 0x04, 0x01, 0x01, 0x55, 0x00, 0x82, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x04, 0x01, 0x00, 0x41, 0x00, 0x82, 0xaa, 0xaa, 0xaa, 0xaa, 0x02, 0x00, 0x04, 0x01, 0x55, 0x5a, 0xa5, 0x80, 0x95, 0x95, 0x80, 0x00, 0x02, 0x55, 0x54, 0x01, 0x00, 0x25, 0x58, 0x80, 0x95, 0x95, 0x85, 0x54, 0x0a, 0xaa, 0xa8, 0x01, 0x00, 0x26, 0x98, 0x80, 0x95, 0x95, 0x85, 0x54, 0x08, 0x00, 0x09, 0x55, 0x00, 0x25, 0x58, 0x80, 0x95, 0x95, 0xaa, 0xaa, 0x08, 0x88, 0x88, 0x00, 0x00, 0x20, 0x08, 0x95, 0x95, 0x95, 0x80, 0x02, 0x58, 0x88, 0x88, 0x00, 0xaa, 0xa0, 0x0a, 0x95, 0x95, 0x95, 0x80, 0x02, 0x58, 0x00, 0x0a, 0xaa, 0x04, 0x20, 0x08, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa9, 0x55, 0x58, 0x00, 0x00, 0x0a, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xaa, 0xa9, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0x42, 0x82, 0x20, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa6, 0x86, 0x26, 0x62, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x45, 0x86, 0x24, 0xa4, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xa4, 0xa1, 0x61, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x61, 0x40, 0xa2, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0xaa, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa9, 0x55, 0x69, 0x55, 0x6a, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x9a, 0xa9, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x59, 0x59, 0x6a, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x98, 0x49, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x95, 0x55, 0xaa, 0x95, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa5, 0x56, 0xaa, 0x40, 0x68, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa8, 0x0a, 0xa5, 0x55, 0x58, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa9, 0x5a, 0xa5, 0x55, 0x58, 0x00, 0x95, 0x5a, 0x69, 0xa5, 0x56, 0x02, 0xa5, 0x96, 0xa9, 0x69, 0x68, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x96, 0x5a, 0x69, 0xa5, 0x96, 0x54, 0x54, 0x54, 0x54, 0x54, 0x55, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x54, 0x54, 0x54, 0x54, 0x54, 0x55, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x30, 0x1f, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x15, 0x00, 0x00, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x55, 0x00, 0x01, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x40, 0x51, 0x55, 0x55, 0x15, 0x54, 0x00, 0x00, 0x15, 0x54, 0x55, 0x55, 0x45, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x40, 0x00, 0x44, 0x11, 0x10, 0x11, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x44, 0x04, 0x44, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x40, 0x00, 0x44, 0x15, 0x05, 0x41, 0x50, 0x05, 0x55, 0x55, 0x50, 0x05, 0x41, 0x50, 0x54, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x50, 0x40, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x50, 0x40, 0x01, 0x00, 0x01, 0x00, 0x17, 0xfc, 0x3f, 0xfc, 0x00, 0x43, 0xff, 0xc0, 0x01, 0x00, 0x01, 0x00, 0x1f, 0xf4, 0xff, 0xd4, 0x00, 0x4f, 0xfc, 0x40, 0x01, 0x55, 0x55, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x40, 0x01, 0x11, 0x11, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x40, 0x01, 0x00, 0x01, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xc0, 0x01, 0x05, 0x41, 0x00, 0xf0, 0xfc, 0x03, 0xff, 0xff, 0x00, 0x00, 0xc0, 0x01, 0x05, 0x41, 0x00, 0xf0, 0xf3, 0x0c, 0x71, 0xc7, 0x33, 0x30, 0xc0, 0xaa, 0xaa, 0xaa, 0xaa, 0xf0, 0xf3, 0x0d, 0x75, 0xd7, 0x33, 0x30, 0xea, 0x55, 0x55, 0x55, 0x55, 0xf0, 0xfc, 0x0d, 0x34, 0xd3, 0x33, 0x30, 0xd5, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x0d, 0x34, 0xc3, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x03, 0xff, 0xff, 0xaa, 0xaa, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 0xc0, 0x00, 0xfc, 0x0f, 0xc0, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x3a, 0xbf, 0xfa, 0xab, 0xff, 0xbf, 0xfb, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0xff, 0xff, 0xcf, 0xfc, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf0, 0x03, 0xff, 0x3f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xc0, 0x00, 0xfc, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x55, 0x51, 0x55, 0x55, 0x15, 0x54, 0x00, 0x00, 0x15, 0x10, 0x00, 0x00, 0x40, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x40, 0x11, 0x10, 0x11, 0x10, 0x04, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x40, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x15, 0x55, 0x55, 0x40, 0x15, 0x05, 0x41, 0x50, 0x05, 0x55, 0x55, 0x50, 0x00, 0x00, 0x00, 0x00, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf5, 0xff, 0xf0, 0x00, 0x0f, 0xff, 0x00, 0x50, 0x50, 0x50, 0x50, 0x3f, 0xc3, 0xff, 0x00, 0x14, 0x3f, 0xf4, 0x14, 0x55, 0x50, 0x55, 0x50, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x54, 0x55, 0x50, 0x55, 0x50, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x54, 0x55, 0x55, 0x55, 0x53, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x54, 0x40, 0x10, 0x40, 0x13, 0xc3, 0xf0, 0x0f, 0xff, 0xfc, 0x00, 0x03, 0x04, 0x50, 0x50, 0x50, 0x53, 0xc3, 0xcc, 0x31, 0xc7, 0x1c, 0xcc, 0xc3, 0x14, 0x40, 0x10, 0x40, 0x13, 0xc3, 0xcc, 0x35, 0xd7, 0x5c, 0xcc, 0xc3, 0x04, 0xaa, 0xaa, 0xaa, 0xab, 0xc3, 0xf0, 0x34, 0xd3, 0x4c, 0xcc, 0xc3, 0xaa, 0x55, 0x55, 0x55, 0x57, 0x00, 0x00, 0x34, 0xd3, 0x0c, 0x00, 0x03, 0x55, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x0f, 0xff, 0xfe, 0xaa, 0xab, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x3f, 0x00, 0x03, 0xf0, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xea, 0xff, 0xea, 0xaf, 0xfe, 0xff, 0xec, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf3, 0xff, 0xff, 0x3f, 0xf3, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x0f, 0xfc, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x03, 0xf0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xfd, 0x7d, 0x7f, 0x5d, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x5d, 0xd5, 0xd7, 0x75, 0xdd, 0xd5, 0x55, 0x55, 0x55, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x30, 0xcc, 0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0xc0, 0xff, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xc0, 0xc3, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0x3f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xfc, 0x3f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x03, 0xc0, 0x30, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0xf3, 0xff, 0xff, 0xcf, 0x00, 0x00, 0x0f, 0xf0, 0x70, 0x0f, 0x55, 0x55, 0xc3, 0x0c, 0x30, 0xc3, 0x55, 0x55, 0xf0, 0x0d, 0xc3, 0x30, 0xd5, 0xff, 0x7c, 0xcf, 0xf3, 0x3d, 0xff, 0x57, 0x0c, 0xc3, 0xc0, 0x3f, 0x5f, 0x03, 0x57, 0xcf, 0xf3, 0xd5, 0xc0, 0xf5, 0xfc, 0x03, 0xc0, 0x30, 0xdc, 0x0d, 0x5f, 0xff, 0xff, 0xf5, 0x70, 0x37, 0x0c, 0x03, 0x7f, 0xff, 0x5f, 0xf5, 0x5f, 0x55, 0x55, 0xf5, 0x5f, 0xf5, 0xff, 0xfd, 0x30, 0x1f, 0xa4, 0x00, 0xa4, 0x01, 0x90, 0x00, 0x64, 0x06, 0x40, 0x1a, 0x00, 0x16, 0xa9, 0x40, 0x09, 0x00, 0x40, 0x00, 0x10, 0x01, 0x00, 0x60, 0x01, 0x6a, 0x2a, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xaa, 0x00, 0xa5, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x01, 0x6a, 0x80, 0x00, 0x01, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x30, 0xc0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x00, 0x05, 0x94, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x15, 0x56, 0xa5, 0x55, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x15, 0x40, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x29, 0x50, 0x15, 0x68, 0x00, 0x40, 0x07, 0xf0, 0x0f, 0xc0, 0x10, 0x00, 0x0a, 0xa5, 0x6a, 0x80, 0x01, 0x00, 0x1f, 0xfc, 0x3f, 0xf0, 0x04, 0x00, 0x00, 0xaa, 0xa8, 0x00, 0x15, 0x00, 0x1f, 0xff, 0xff, 0xf0, 0x05, 0x40, 0x00, 0x0a, 0xa0, 0x00, 0x04, 0x00, 0x5c, 0x00, 0x00, 0x30, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xf0, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xc0, 0x33, 0x00, 0x00, 0xcc, 0x03, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x30, 0x03, 0xc0, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x0c, 0x30, 0x03, 0xc0, 0x0c, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x3c, 0x03, 0xc0, 0x3c, 0xff, 0xc0, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0xc3, 0xff, 0xff, 0xc3, 0x00, 0x00, 0x0f, 0xf0, 0x30, 0x0c, 0x00, 0x00, 0xcc, 0x30, 0x0c, 0x33, 0x00, 0x00, 0x30, 0x0c, 0xc3, 0x0f, 0x00, 0x00, 0x3f, 0x3f, 0xfc, 0xfc, 0x00, 0x00, 0xf0, 0xc3, 0xc0, 0x30, 0xc0, 0x00, 0x03, 0x3f, 0xfc, 0xc0, 0x00, 0x03, 0x0c, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0xfc, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x3f, 0xfc, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x30, 0x30, 0xc0, 0x00, 0x00, 0x3c, 0x3c, 0x00, 0x00, 0x03, 0x0c, 0x0c, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x0c, 0x30, 0x00, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xfd, 0x7d, 0x7f, 0x5d, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x5d, 0xd5, 0xd7, 0x75, 0xdd, 0xd5, 0x55, 0x55, 0x55, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x30, 0xcc, 0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0xc0, 0xff, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xc0, 0xc3, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x70, 0x0f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xf0, 0x0d, 0xc3, 0x30, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x0c, 0xc3, 0xc0, 0x3f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfc, 0x03, 0xc0, 0x30, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x0c, 0x03, 0x7f, 0xff, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xfd, 0x30, 0x1f, 0xa4, 0x00, 0xa4, 0x01, 0x90, 0x00, 0x64, 0x06, 0x40, 0x1a, 0x00, 0x16, 0xa9, 0x40, 0x09, 0x00, 0x40, 0x00, 0x10, 0x01, 0x00, 0x60, 0x01, 0x6a, 0x2a, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xaa, 0x00, 0xa5, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x01, 0x6a, 0x80, 0x00, 0x01, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x30, 0xc0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x00, 0x05, 0x94, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x15, 0x56, 0xa5, 0x55, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x15, 0x40, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x29, 0x50, 0x15, 0x68, 0x00, 0x40, 0x04, 0x00, 0x04, 0x00, 0x10, 0x00, 0x0a, 0xa5, 0x6a, 0x80, 0x01, 0x00, 0x14, 0x00, 0x05, 0x00, 0x04, 0x00, 0x00, 0xaa, 0xa8, 0x00, 0x15, 0x00, 0x15, 0x00, 0x15, 0x00, 0x05, 0x40, 0x00, 0x0a, 0xa0, 0x00, 0x04, 0x00, 0x54, 0x00, 0x05, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x30, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0c, 0xc3, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xc3, 0xc0, 0x30, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x30, 0x30, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x0c, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xfc, 0x00, 0xc3, 0x0f, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xc3, 0x00, 0xc3, 0x30, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xcc, 0xc3, 0x00, 0xff, 0x30, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xfc, 0x00, 0xc3, 0x30, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xc0, 0x00, 0xc3, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x3f, 0x0f, 0xcf, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0xcc, 0x0c, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0xcf, 0xcf, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0x0f, 0xcf, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x30, 0xcc, 0x33, 0x0c, 0xfc, 0xfc, 0x00, 0x00, 0xc0, 0x00, 0x00, 0xc3, 0x30, 0xcf, 0x33, 0xcc, 0xc0, 0xc3, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc3, 0x30, 0xcc, 0xf3, 0x3c, 0xfc, 0xc3, 0x00, 0x00, 0xfc, 0x00, 0x00, 0xfc, 0x30, 0xcc, 0x33, 0x0c, 0xc0, 0xfc, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc3, 0x0f, 0x0c, 0x33, 0x0c, 0xfc, 0xc3, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x1f, 0x05, 0x55, 0x55, 0x55, 0x55, 0x55, 0x54, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x05, 0x54, 0x55, 0x45, 0x51, 0x10, 0x00, 0x04, 0x04, 0x55, 0x44, 0x51, 0x11, 0x55, 0x44, 0x04, 0x44, 0x44, 0x51, 0x11, 0x00, 0x44, 0x04, 0x44, 0x44, 0x51, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x00, 0x00, 0x00, 0x05, 0x41, 0x10, 0x00, 0x00, 0x00, 0x00, 0x04, 0x41, 0x10, 0x00, 0x00, 0x10, 0x55, 0x05, 0x41, 0x10, 0x54, 0x00, 0x55, 0x45, 0x10, 0x11, 0x11, 0x01, 0x40, 0x55, 0x54, 0x10, 0x11, 0x11, 0x00, 0x10, 0x55, 0x54, 0x15, 0x51, 0x11, 0x41, 0x11, 0x51, 0x10, 0x04, 0x41, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x50, 0x50, 0x00, 0x00, 0x10, 0x01, 0x10, 0x55, 0x50, 0x55, 0x00, 0x55, 0x01, 0x10, 0x44, 0x51, 0x00, 0x51, 0x00, 0x41, 0x10, 0x40, 0x11, 0x04, 0x41, 0x11, 0x41, 0x10, 0x15, 0x41, 0x00, 0x41, 0x00, 0x41, 0x10, 0x10, 0x41, 0x00, 0x40, 0x41, 0x01, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x55, 0x55, 0x55, 0x55, 0x55, 0x41, 0x10, 0x40, 0x00, 0x00, 0x00, 0x00, 0x41, 0x10, 0x55, 0x55, 0x55, 0x55, 0x55, 0x41, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x15, 0x50, 0x00, 0x00, 0x00, 0x01, 0x55, 0x12, 0x0c, 0x57, 0xf5, 0x7d, 0x55, 0x50, 0x5f, 0xfd, 0xff, 0x55, 0x50, 0x5f, 0xff, 0xff, 0x55, 0x50, 0x5f, 0xff, 0xff, 0xd5, 0x50, 0x7c, 0x00, 0x00, 0xd5, 0x50, 0x70, 0x0f, 0xc3, 0xd5, 0x50, 0x70, 0x33, 0xc3, 0xd5, 0x50, 0x70, 0x33, 0xc3, 0xd5, 0x50, 0x70, 0x0f, 0xc3, 0xd5, 0x50, 0x5c, 0x00, 0x0f, 0x55, 0x50, 0x57, 0xff, 0xfd, 0x55, 0x50, 0x5c, 0x3c, 0x33, 0x55, 0x50, 0x12, 0x0c, 0x55, 0xfd, 0x5f, 0x55, 0x50, 0x57, 0xff, 0x7f, 0xd5, 0x50, 0x57, 0xff, 0xff, 0xd5, 0x50, 0x57, 0xff, 0xff, 0xf5, 0x50, 0x5f, 0x00, 0x00, 0x35, 0x50, 0x5c, 0x03, 0xc0, 0x35, 0x50, 0x5c, 0x0c, 0x30, 0xf5, 0x50, 0x5c, 0x00, 0x00, 0x35, 0x50, 0x5c, 0x0c, 0x0f, 0xf5, 0x50, 0x57, 0x33, 0x0f, 0xd5, 0x50, 0x55, 0xf3, 0xff, 0x35, 0x50, 0x55, 0xc3, 0xc3, 0xf5, 0x50, 0x12, 0x0c, 0x5f, 0xd5, 0x7f, 0xff, 0xf0, 0x7f, 0xf5, 0xff, 0x00, 0x30, 0x7f, 0xff, 0xff, 0x00, 0x30, 0x7f, 0xff, 0xff, 0x00, 0x30, 0x70, 0x00, 0x03, 0x00, 0x30, 0xc3, 0xf0, 0x3f, 0x00, 0x30, 0xcc, 0xf0, 0xcf, 0x00, 0x30, 0xcc, 0xf0, 0xcf, 0x00, 0x30, 0xc3, 0xf0, 0x3f, 0xff, 0xf0, 0x70, 0x0f, 0x00, 0xcd, 0x50, 0x5f, 0xff, 0xff, 0x35, 0x50, 0x70, 0x30, 0x3c, 0xd5, 0x50, 0x12, 0x0c, 0x55, 0xfd, 0x57, 0xd5, 0x50, 0x57, 0xff, 0xdf, 0xf5, 0x50, 0x57, 0xff, 0xff, 0xfd, 0x50, 0x55, 0xff, 0xff, 0xfd, 0x50, 0x57, 0xc0, 0x00, 0x0d, 0x50, 0x57, 0x00, 0x00, 0x0d, 0x50, 0x57, 0x00, 0x00, 0x0d, 0x50, 0x57, 0x0f, 0xf0, 0x0d, 0x50, 0x57, 0x00, 0x00, 0xcd, 0x50, 0x55, 0xc0, 0x03, 0x35, 0x50, 0x55, 0x7f, 0xff, 0xd5, 0x50, 0x55, 0xc3, 0xc3, 0xd5, 0x50, 0x12, 0x0c, 0x57, 0xf5, 0x5f, 0xd5, 0x50, 0x5f, 0xfd, 0x7f, 0xf5, 0x50, 0x5f, 0xff, 0xff, 0xf5, 0x50, 0x5f, 0xff, 0xff, 0xf5, 0x50, 0x5c, 0x00, 0x00, 0x35, 0x50, 0x70, 0x00, 0x00, 0x0d, 0x50, 0x70, 0x30, 0x0c, 0x0d, 0x50, 0x70, 0xc0, 0x03, 0x0d, 0x50, 0x70, 0x03, 0xc0, 0x0d, 0x50, 0x5c, 0x0f, 0xf0, 0x35, 0x50, 0x57, 0xff, 0xff, 0xd5, 0x50, 0x55, 0xcc, 0x33, 0x55, 0x50, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfa, 0xaa, 0xab, 0xc0, 0xff, 0xe5, 0x55, 0x5a, 0xc0, 0xff, 0xe5, 0x55, 0x5a, 0xc0, 0xff, 0x95, 0x55, 0x66, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0xaa, 0xaa, 0xab, 0xc0, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfe, 0xaa, 0xaa, 0xc0, 0xff, 0xfe, 0x55, 0x56, 0xc0, 0xff, 0xfe, 0x55, 0x56, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xea, 0xaa, 0xaa, 0xc0, 0xff, 0xea, 0xaa, 0xaa, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0xaa, 0xaa, 0xab, 0xc0, 0x08, 0x08, 0x7f, 0xf5, 0xff, 0xfd, 0xc3, 0x0d, 0xff, 0xfd, 0xff, 0xfd, 0xfc, 0xfd, 0x7f, 0xf5, 0x77, 0x75, 0x10, 0x03, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xc0, 0x03, 0x03, 0xff, 0xff, 0xff, 0xff, 0x10, 0x03, 0x55, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x03, 0x55, 0x55, 0xff, 0xff, 0x55, 0x08, 0x08, 0x55, 0x75, 0x55, 0x75, 0x55, 0x75, 0x5f, 0x75, 0x70, 0xf5, 0x70, 0xd5, 0x5f, 0x55, 0x55, 0x55, 0x08, 0x08, 0x55, 0x75, 0x55, 0x75, 0x55, 0x75, 0x5f, 0x75, 0x7f, 0xf5, 0x7f, 0xd5, 0x5f, 0x55, 0x55, 0x55, 0x08, 0x08, 0x55, 0xd5, 0x55, 0xf5, 0x55, 0xfd, 0x7d, 0xdd, 0xff, 0xd5, 0xff, 0x55, 0x7d, 0x55, 0x55, 0x55, 0x08, 0x08, 0x5f, 0xfd, 0x5d, 0x5d, 0x5d, 0x5d, 0x5d, 0x5d, 0xfd, 0xfd, 0xfd, 0xfd, 0xf5, 0xf5, 0x55, 0x55, 0x01, 0x01, 0x00, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x7f, 0xfd, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x5f, 0xfd, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x7f, 0xfd, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x5f, 0xfd, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x7f, 0xfd, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0x03, 0x5f, 0xfd, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x08, 0x08, 0x50, 0x05, 0x43, 0xc1, 0x00, 0x00, 0x30, 0xcc, 0x33, 0x0c, 0x00, 0x00, 0x43, 0xc1, 0x50, 0x05, 0x08, 0x08, 0xc0, 0x03, 0x33, 0xcc, 0x00, 0x30, 0x33, 0x0c, 0x30, 0xcc, 0x0c, 0x00, 0x33, 0xcc, 0xc0, 0x03, 0x08, 0x08, 0x57, 0xd5, 0x5c, 0x35, 0x5c, 0x35, 0xdc, 0x37, 0xd7, 0xd7, 0xdf, 0xf7, 0xfd, 0x7f, 0xf7, 0xdf, 0x04, 0x1f, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x02, 0x05, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0x06, 0x20, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0x20, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf7, 0xff, 0x5f, 0x5f, 0xd7, 0xff, 0x75, 0x5d, 0x55, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x57, 0xd5, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x55, 0x75, 0x75, 0x7f, 0xdf, 0xd5, 0x75, 0x75, 0x55, 0x75, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x55, 0x5f, 0xd5, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x08, 0x7f, 0x5f, 0x57, 0xd7, 0x57, 0xd5, 0x75, 0xdd, 0x77, 0x57, 0xdf, 0x75, 0xdd, 0x77, 0x57, 0xd7, 0x75, 0xdf, 0xf7, 0x55, 0x7d, 0x5f, 0x5d, 0x77, 0xf7, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x0c, 0x7f, 0x5f, 0x5d, 0x5d, 0xfd, 0xd5, 0x75, 0xdf, 0x7d, 0xd5, 0xdf, 0x75, 0xdf, 0xfd, 0xfd, 0xd7, 0x7f, 0xdd, 0xdd, 0xd5, 0x7f, 0x75, 0xdd, 0x5d, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7d, 0x75, 0x77, 0xf7, 0xf5, 0xd7, 0x75, 0x77, 0x57, 0x5d, 0xd7, 0x5d, 0xd7, 0xf7, 0x5d, 0xd7, 0x5d, 0xd7, 0x57, 0xf5, 0x7d, 0x57, 0x57, 0xf7, 0x5d, 0x55, 0x55, 0x55, 0x55, 0x55, 0x20, 0x0c, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xff, 0x55, 0xc3, 0x7d, 0x55, 0x55, 0x55, 0x70, 0x00, 0xd5, 0x70, 0xff, 0x55, 0x55, 0x55, 0xc0, 0x00, 0x35, 0x7c, 0x3f, 0xd5, 0x55, 0x57, 0x00, 0x03, 0x0d, 0x5f, 0xff, 0xff, 0xff, 0xfc, 0x03, 0x00, 0x0d, 0x70, 0x00, 0x03, 0xc0, 0x00, 0x00, 0x3f, 0xfd, 0x7f, 0xff, 0xfc, 0x30, 0x00, 0x00, 0xc0, 0x03, 0xc0, 0x00, 0x03, 0x30, 0x00, 0x03, 0x0f, 0xfc, 0xc0, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc0, 0x03, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x01, 0x01, 0x00, 0x10, 0x10, 0x55, 0x7d, 0x55, 0xf5, 0x55, 0xc3, 0x57, 0x0d, 0x55, 0xc0, 0xdc, 0x0d, 0x55, 0x70, 0xdc, 0x3d, 0x55, 0x5c, 0x30, 0x35, 0x55, 0x70, 0x00, 0xd5, 0x55, 0xc3, 0xfc, 0xd5, 0x55, 0xcf, 0xff, 0x35, 0x57, 0x0f, 0xff, 0x35, 0x57, 0x00, 0xfc, 0x35, 0x57, 0xc0 };\r\n\r\n\r\nvoid EXTI0_IRQHandler() {\r\n\r\n\t//GPIO_SetBits(GPIOB, GPIO_Pin_14);\r\n //if (EXTI_GetITStatus(EXTI_Line0) != RESET) {\r\n if(started){\r\n \tif(loops > 2000){\r\n\r\n \t\tloops = 0;\r\n \t}\r\n \tread = 1;\r\n \t//GPIO_SetBits(GPIOB, GPIO_Pin_14);\r\n \ta = 0;\r\n \tacount = 0;\r\n //\tas[loops++] = a;\r\n \t//as[loops++] = acount;\r\n \tas[loops++] = hit;\r\n \thit = 0;\r\n\r\n\r\n }\r\n EXTI_ClearITPendingBit(EXTI_Line0);\r\n //}\r\n\t//GPIO_ResetBits(GPIOB, GPIO_Pin_14);\r\n}\r\n\r\nvoid EXTI1_IRQHandler() {\r\n\t//hit++;\r\n\t//if (EXTI_GetITStatus(EXTI_Line1) != RESET) {\r\n\r\n \tif(read){\r\n\r\n \t//\ta = a << 1;\r\n \t//\tGPIO_SetBits(GPIOB, GPIO_Pin_15);\r\n \t\t// a = a | (GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_8));\r\n\r\n \t\t(GPIOD->IDR & GPIO_Pin_8) ? (a = ((a << 1)|1) ) : (a <<= 1);\r\n\r\n \t\t//GPIO_ResetBits(GPIOB, GPIO_Pin_15);\r\n \t\tacount++;\r\n\t\t//\t if(acount > 32){\r\n\r\n\t\t\t//\t\t GPIO_SetBits(GPIOD, GPIO_Pin_15);\r\n\t\t\t\t// }\r\n\r\n \t\tif (acount ==32){\r\n \t\t\tread = 0;\r\n\r\n \t\t\t //if((a & 0xff000000) != 0x03000000){\r\n\r\n \t\t\t\t//\t GPIO_SetBits(GPIOD, GPIO_Pin_14);\r\n \t\t\t\t// }\r\n\r\n \t\t\tas[loops++] = a;\r\n\r\n \t\t\t a = 0xffffff & a;\r\n\r\n \t\t\t// index = (loops % 800) / 100;\r\n \t\t\t/* if(loops > 100){\r\n \t\t\t\t loops = 0;\r\n \t\t\t\t index++;\r\n \t\t\t\t if (index > 7)\r\n \t\t\t\t\t index = 0;\r\n \t\t\t }\r\n \t\t\tfor(i = 0; i < 105; i++){\r\n\r\n \t\t\t\tv[0xe0 + i] = vs[index][i];\r\n \t\t\t}*/\r\n\r\n\r\n \t\t\tval = v[a++];\r\n\r\n \t\t//\tas[loops++] = val;\r\n \t\t//\tas[loops++] = val;\r\n \t\t\tc = 0x80;\r\n \t\t\tif(val&c){\r\n \t\t\t\t\t\t GPIO_SetBits(GPIOD, GPIO_Pin_4);\r\n \t\t\t \t\t }else{\r\n \t\t\t \t\t\t GPIO_ResetBits(GPIOD, GPIO_Pin_4);\r\n\r\n \t\t\t \t\t }\r\n\r\n \t\t\t \t\t c = c >> 1;\r\n \t\t\t \t\t started = 1;\r\n \t\t}\r\n\r\n \t}else{\r\n \t\t if(val&c){\r\n \t\t\t GPIOD->BSRRL = GPIO_Pin_4;\r\n \t\t }else{\r\n \t\t\t GPIOD->BSRRH = GPIO_Pin_4;\r\n\r\n \t\t }\r\n\r\n \t\t c = c >> 1;\r\n \t\t if(c==0){\r\n \t\t\t c = 0x80;\r\n \t\t\t val = v[a++];\r\n \t\t\t // as[loops++] = val;\r\n\r\n \t\t }\r\n \t\t //as[loops++] = 2;\r\n \t}\r\n\r\n \tEXTI_ClearITPendingBit(EXTI_Line1);\r\n\r\n //}\r\n\r\n\r\n}\r\n\r\n\r\n\r\n\r\n/**\r\n * @brief Main program.\r\n * @param None\r\n * @retval None\r\n */\r\nuint32_t getAddress();\r\n\r\n\r\nint main(void)\r\n{\r\n RCC_ClocksTypeDef RCC_Clocks;\r\n\r\n int l = 0;\r\n\r\n /* Initialize LEDs and User_Button on STM32F4-Discovery --------------------*/\r\n\r\n RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE);\r\n RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE);\r\n /* SysTick end of count event each 10ms */\r\n // RCC_GetClocksFreq(&RCC_Clocks);\r\n // SysTick_Config(RCC_Clocks.HCLK_Frequency / 100);\r\n\r\n GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_8 ;\r\n GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r\n GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r\n GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;\r\n GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r\n GPIO_Init(GPIOD, &GPIO_InitStructure);\r\n\r\n GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;\r\n GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r\n GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r\n GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;\r\n GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;\r\n GPIO_Init(GPIOD, &GPIO_InitStructure);\r\n\r\n GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_13| GPIO_Pin_14| GPIO_Pin_15;\r\n GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;\r\n GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r\n GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;\r\n GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r\n GPIO_Init(GPIOD, &GPIO_InitStructure);\r\n\r\n\r\n GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14 | GPIO_Pin_15;\r\n GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;\r\n GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r\n GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;\r\n GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r\n GPIO_Init(GPIOB, &GPIO_InitStructure);\r\n\r\n\r\n EXTILine0_Config();\r\n GPIO_SetBits(GPIOD, GPIO_Pin_12);\r\n // GPIO_SetBits(GPIOD, GPIO_Pin_14);\r\n// GPIO_SetBits(GPIOD, GPIO_Pin_12);\r\n // GPIO_ResetBits(GPIOB, GPIO_Pin_14);\r\n //GPIO_SetBits(GPIOB, GPIO_Pin_14);\r\n vs[0] = v1;\r\n vs[1] = v2;\r\n vs[2] = v3;\r\n vs[3] = v2;\r\n vs[4] = v4;\r\n vs[5] = v5;\r\n vs[6] = v6;\r\n vs[7] = v7;\r\n while(1){\r\n\r\n}\r\n\r\n}\r\n\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n\r\n/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/src/startup_stm32f4xx.s", "content": "/**\r\n ******************************************************************************\r\n * @file startup_stm32f4xx.s\r\n * @author MCD Application Team\r\n * @version V1.0.2\r\n * @date 05-March-2012\r\n * @brief STM32F4xx Devices vector table for Atollic TrueSTUDIO toolchain. \r\n * This module performs:\r\n * - Set the initial SP\r\n * - Set the initial PC == Reset_Handler,\r\n * - Set the vector table entries with the exceptions ISR address\r\n * - Configure the clock system and the external SRAM mounted on \r\n * STM324xG-EVAL board to be used as data memory (optional, \r\n * to be enabled by user)\r\n * - Branches to main in the C library (which eventually\r\n * calls main()).\r\n * After Reset the Cortex-M4 processor is in Thread mode,\r\n * priority is Privileged, and the Stack is set to Main.\r\n ******************************************************************************\r\n * @attention\r\n *\r\n *

© COPYRIGHT 2012 STMicroelectronics

\r\n *\r\n * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n * You may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at:\r\n *\r\n * http://www.st.com/software_license_agreement_liberty_v2\r\n *\r\n * Unless required by applicable law or agreed to in writing, software \r\n * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\r\n ******************************************************************************\r\n */\r\n \r\n .syntax unified\r\n .cpu cortex-m3\r\n .fpu softvfp\r\n .thumb\r\n\r\n.global g_pfnVectors\r\n.global Default_Handler\r\n\r\n/* start address for the initialization values of the .data section. \r\ndefined in linker script */\r\n.word _sidata\r\n/* start address for the .data section. defined in linker script */ \r\n.word _sdata\r\n/* end address for the .data section. defined in linker script */\r\n.word _edata\r\n/* start address for the .bss section. defined in linker script */\r\n.word _sbss\r\n/* end address for the .bss section. defined in linker script */\r\n.word _ebss\r\n/* stack used for SystemInit_ExtMemCtl; always internal RAM used */\r\n\r\n/**\r\n * @brief This is the code that gets called when the processor first\r\n * starts execution following a reset event. Only the absolutely\r\n * necessary set is performed, after which the application\r\n * supplied main() routine is called. \r\n * @param None\r\n * @retval : None\r\n*/\r\n\r\n .section .text.Reset_Handler\r\n .weak Reset_Handler\r\n .type Reset_Handler, %function\r\nReset_Handler: \r\n\r\n/* Copy the data segment initializers from flash to SRAM */ \r\n movs r1, #0\r\n b LoopCopyDataInit\r\n\r\nCopyDataInit:\r\n ldr r3, =_sidata\r\n ldr r3, [r3, r1]\r\n str r3, [r0, r1]\r\n adds r1, r1, #4\r\n \r\nLoopCopyDataInit:\r\n ldr r0, =_sdata\r\n ldr r3, =_edata\r\n adds r2, r0, r1\r\n cmp r2, r3\r\n bcc CopyDataInit\r\n ldr r2, =_sbss\r\n b LoopFillZerobss\r\n/* Zero fill the bss segment. */ \r\nFillZerobss:\r\n movs r3, #0\r\n str r3, [r2], #4\r\n \r\nLoopFillZerobss:\r\n ldr r3, = _ebss\r\n cmp r2, r3\r\n bcc FillZerobss\r\n\r\n/* Call the clock system intitialization function.*/\r\n bl SystemInit \r\n/* Call static constructors */\r\n bl __libc_init_array\r\n/* Call the application's entry point.*/\r\n bl main\r\n bx lr \r\n.size Reset_Handler, .-Reset_Handler\r\n\r\n/**\r\n * @brief This is the code that gets called when the processor receives an \r\n * unexpected interrupt. This simply enters an infinite loop, preserving\r\n * the system state for examination by a debugger.\r\n * @param None \r\n * @retval None \r\n*/\r\n .section .text.Default_Handler,\"ax\",%progbits\r\nDefault_Handler:\r\nInfinite_Loop:\r\n b Infinite_Loop\r\n .size Default_Handler, .-Default_Handler\r\n/******************************************************************************\r\n*\r\n* The minimal vector table for a Cortex M3. Note that the proper constructs\r\n* must be placed on this to ensure that it ends up at physical address\r\n* 0x0000.0000.\r\n* \r\n*******************************************************************************/\r\n .section .isr_vector,\"a\",%progbits\r\n .type g_pfnVectors, %object\r\n .size g_pfnVectors, .-g_pfnVectors\r\n \r\n \r\ng_pfnVectors:\r\n .word _estack\r\n .word Reset_Handler\r\n .word NMI_Handler\r\n .word HardFault_Handler\r\n .word MemManage_Handler\r\n .word BusFault_Handler\r\n .word UsageFault_Handler\r\n .word 0\r\n .word 0\r\n .word 0\r\n .word 0\r\n .word SVC_Handler\r\n .word DebugMon_Handler\r\n .word 0\r\n .word PendSV_Handler\r\n .word SysTick_Handler\r\n \r\n /* External Interrupts */\r\n .word WWDG_IRQHandler /* Window WatchDog */ \r\n .word PVD_IRQHandler /* PVD through EXTI Line detection */ \r\n .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ \r\n .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ \r\n .word FLASH_IRQHandler /* FLASH */ \r\n .word RCC_IRQHandler /* RCC */ \r\n .word EXTI0_IRQHandler /* EXTI Line0 */ \r\n .word EXTI1_IRQHandler /* EXTI Line1 */ \r\n .word EXTI2_IRQHandler /* EXTI Line2 */ \r\n .word EXTI3_IRQHandler /* EXTI Line3 */ \r\n .word EXTI4_IRQHandler /* EXTI Line4 */ \r\n .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ \r\n .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ \r\n .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ \r\n .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ \r\n .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ \r\n .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ \r\n .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ \r\n .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ \r\n .word CAN1_TX_IRQHandler /* CAN1 TX */ \r\n .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ \r\n .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ \r\n .word CAN1_SCE_IRQHandler /* CAN1 SCE */ \r\n .word EXTI9_5_IRQHandler /* External Line[9:5]s */ \r\n .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ \r\n .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ \r\n .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */\r\n .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ \r\n .word TIM2_IRQHandler /* TIM2 */ \r\n .word TIM3_IRQHandler /* TIM3 */ \r\n .word TIM4_IRQHandler /* TIM4 */ \r\n .word I2C1_EV_IRQHandler /* I2C1 Event */ \r\n .word I2C1_ER_IRQHandler /* I2C1 Error */ \r\n .word I2C2_EV_IRQHandler /* I2C2 Event */ \r\n .word I2C2_ER_IRQHandler /* I2C2 Error */ \r\n .word SPI1_IRQHandler /* SPI1 */ \r\n .word SPI2_IRQHandler /* SPI2 */ \r\n .word USART1_IRQHandler /* USART1 */ \r\n .word USART2_IRQHandler /* USART2 */ \r\n .word USART3_IRQHandler /* USART3 */ \r\n .word EXTI15_10_IRQHandler /* External Line[15:10]s */ \r\n .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ \r\n .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ \r\n .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ \r\n .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ \r\n .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */\r\n .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ \r\n .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ \r\n .word FSMC_IRQHandler /* FSMC */ \r\n .word SDIO_IRQHandler /* SDIO */ \r\n .word TIM5_IRQHandler /* TIM5 */ \r\n .word SPI3_IRQHandler /* SPI3 */ \r\n .word UART4_IRQHandler /* UART4 */ \r\n .word UART5_IRQHandler /* UART5 */ \r\n .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ \r\n .word TIM7_IRQHandler /* TIM7 */\r\n .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ \r\n .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ \r\n .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ \r\n .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ \r\n .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ \r\n .word ETH_IRQHandler /* Ethernet */ \r\n .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ \r\n .word CAN2_TX_IRQHandler /* CAN2 TX */ \r\n .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ \r\n .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ \r\n .word CAN2_SCE_IRQHandler /* CAN2 SCE */ \r\n .word OTG_FS_IRQHandler /* USB OTG FS */ \r\n .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ \r\n .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ \r\n .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ \r\n .word USART6_IRQHandler /* USART6 */ \r\n .word I2C3_EV_IRQHandler /* I2C3 event */ \r\n .word I2C3_ER_IRQHandler /* I2C3 error */ \r\n .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ \r\n .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ \r\n .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ \r\n .word OTG_HS_IRQHandler /* USB OTG HS */ \r\n .word DCMI_IRQHandler /* DCMI */ \r\n .word CRYP_IRQHandler /* CRYP crypto */ \r\n .word HASH_RNG_IRQHandler /* Hash and Rng */\r\n .word FPU_IRQHandler /* FPU */\r\n \r\n \r\n/*******************************************************************************\r\n*\r\n* Provide weak aliases for each Exception handler to the Default_Handler. \r\n* As they are weak aliases, any function with the same name will override \r\n* this definition.\r\n* \r\n*******************************************************************************/\r\n .weak NMI_Handler\r\n .thumb_set NMI_Handler,Default_Handler\r\n \r\n .weak HardFault_Handler\r\n .thumb_set HardFault_Handler,Default_Handler\r\n \r\n .weak MemManage_Handler\r\n .thumb_set MemManage_Handler,Default_Handler\r\n \r\n .weak BusFault_Handler\r\n .thumb_set BusFault_Handler,Default_Handler\r\n\r\n .weak UsageFault_Handler\r\n .thumb_set UsageFault_Handler,Default_Handler\r\n\r\n .weak SVC_Handler\r\n .thumb_set SVC_Handler,Default_Handler\r\n\r\n .weak DebugMon_Handler\r\n .thumb_set DebugMon_Handler,Default_Handler\r\n\r\n .weak PendSV_Handler\r\n .thumb_set PendSV_Handler,Default_Handler\r\n\r\n .weak SysTick_Handler\r\n .thumb_set SysTick_Handler,Default_Handler \r\n \r\n .weak WWDG_IRQHandler \r\n .thumb_set WWDG_IRQHandler,Default_Handler \r\n \r\n .weak PVD_IRQHandler \r\n .thumb_set PVD_IRQHandler,Default_Handler\r\n \r\n .weak TAMP_STAMP_IRQHandler \r\n .thumb_set TAMP_STAMP_IRQHandler,Default_Handler\r\n \r\n .weak RTC_WKUP_IRQHandler \r\n .thumb_set RTC_WKUP_IRQHandler,Default_Handler\r\n \r\n .weak FLASH_IRQHandler \r\n .thumb_set FLASH_IRQHandler,Default_Handler\r\n \r\n .weak RCC_IRQHandler \r\n .thumb_set RCC_IRQHandler,Default_Handler\r\n \r\n .weak EXTI0_IRQHandler \r\n .thumb_set EXTI0_IRQHandler,Default_Handler\r\n \r\n .weak EXTI1_IRQHandler \r\n .thumb_set EXTI1_IRQHandler,Default_Handler\r\n \r\n .weak EXTI2_IRQHandler \r\n .thumb_set EXTI2_IRQHandler,Default_Handler \r\n \r\n .weak EXTI3_IRQHandler \r\n .thumb_set EXTI3_IRQHandler,Default_Handler\r\n \r\n .weak EXTI4_IRQHandler \r\n .thumb_set EXTI4_IRQHandler,Default_Handler\r\n \r\n .weak DMA1_Stream0_IRQHandler \r\n .thumb_set DMA1_Stream0_IRQHandler,Default_Handler\r\n \r\n .weak DMA1_Stream1_IRQHandler \r\n .thumb_set DMA1_Stream1_IRQHandler,Default_Handler\r\n \r\n .weak DMA1_Stream2_IRQHandler \r\n .thumb_set DMA1_Stream2_IRQHandler,Default_Handler\r\n \r\n .weak DMA1_Stream3_IRQHandler \r\n .thumb_set DMA1_Stream3_IRQHandler,Default_Handler \r\n \r\n .weak DMA1_Stream4_IRQHandler \r\n .thumb_set DMA1_Stream4_IRQHandler,Default_Handler\r\n \r\n .weak DMA1_Stream5_IRQHandler \r\n .thumb_set DMA1_Stream5_IRQHandler,Default_Handler\r\n \r\n .weak DMA1_Stream6_IRQHandler \r\n .thumb_set DMA1_Stream6_IRQHandler,Default_Handler\r\n \r\n .weak ADC_IRQHandler \r\n .thumb_set ADC_IRQHandler,Default_Handler\r\n \r\n .weak CAN1_TX_IRQHandler \r\n .thumb_set CAN1_TX_IRQHandler,Default_Handler\r\n \r\n .weak CAN1_RX0_IRQHandler \r\n .thumb_set CAN1_RX0_IRQHandler,Default_Handler\r\n \r\n .weak CAN1_RX1_IRQHandler \r\n .thumb_set CAN1_RX1_IRQHandler,Default_Handler\r\n \r\n .weak CAN1_SCE_IRQHandler \r\n .thumb_set CAN1_SCE_IRQHandler,Default_Handler\r\n \r\n .weak EXTI9_5_IRQHandler \r\n .thumb_set EXTI9_5_IRQHandler,Default_Handler\r\n \r\n .weak TIM1_BRK_TIM9_IRQHandler \r\n .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler\r\n \r\n .weak TIM1_UP_TIM10_IRQHandler \r\n .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler\r\n \r\n .weak TIM1_TRG_COM_TIM11_IRQHandler \r\n .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler\r\n \r\n .weak TIM1_CC_IRQHandler \r\n .thumb_set TIM1_CC_IRQHandler,Default_Handler\r\n \r\n .weak TIM2_IRQHandler \r\n .thumb_set TIM2_IRQHandler,Default_Handler\r\n \r\n .weak TIM3_IRQHandler \r\n .thumb_set TIM3_IRQHandler,Default_Handler\r\n \r\n .weak TIM4_IRQHandler \r\n .thumb_set TIM4_IRQHandler,Default_Handler\r\n \r\n .weak I2C1_EV_IRQHandler \r\n .thumb_set I2C1_EV_IRQHandler,Default_Handler\r\n \r\n .weak I2C1_ER_IRQHandler \r\n .thumb_set I2C1_ER_IRQHandler,Default_Handler\r\n \r\n .weak I2C2_EV_IRQHandler \r\n .thumb_set I2C2_EV_IRQHandler,Default_Handler\r\n \r\n .weak I2C2_ER_IRQHandler \r\n .thumb_set I2C2_ER_IRQHandler,Default_Handler\r\n \r\n .weak SPI1_IRQHandler \r\n .thumb_set SPI1_IRQHandler,Default_Handler\r\n \r\n .weak SPI2_IRQHandler \r\n .thumb_set SPI2_IRQHandler,Default_Handler\r\n \r\n .weak USART1_IRQHandler \r\n .thumb_set USART1_IRQHandler,Default_Handler\r\n \r\n .weak USART2_IRQHandler \r\n .thumb_set USART2_IRQHandler,Default_Handler\r\n \r\n .weak USART3_IRQHandler \r\n .thumb_set USART3_IRQHandler,Default_Handler\r\n \r\n .weak EXTI15_10_IRQHandler \r\n .thumb_set EXTI15_10_IRQHandler,Default_Handler\r\n \r\n .weak RTC_Alarm_IRQHandler \r\n .thumb_set RTC_Alarm_IRQHandler,Default_Handler\r\n \r\n .weak OTG_FS_WKUP_IRQHandler \r\n .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler\r\n \r\n .weak TIM8_BRK_TIM12_IRQHandler \r\n .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler\r\n \r\n .weak TIM8_UP_TIM13_IRQHandler \r\n .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler\r\n \r\n .weak TIM8_TRG_COM_TIM14_IRQHandler \r\n .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler\r\n \r\n .weak TIM8_CC_IRQHandler \r\n .thumb_set TIM8_CC_IRQHandler,Default_Handler\r\n \r\n .weak DMA1_Stream7_IRQHandler \r\n .thumb_set DMA1_Stream7_IRQHandler,Default_Handler\r\n \r\n .weak FSMC_IRQHandler \r\n .thumb_set FSMC_IRQHandler,Default_Handler\r\n \r\n .weak SDIO_IRQHandler \r\n .thumb_set SDIO_IRQHandler,Default_Handler\r\n \r\n .weak TIM5_IRQHandler \r\n .thumb_set TIM5_IRQHandler,Default_Handler\r\n \r\n .weak SPI3_IRQHandler \r\n .thumb_set SPI3_IRQHandler,Default_Handler\r\n \r\n .weak UART4_IRQHandler \r\n .thumb_set UART4_IRQHandler,Default_Handler\r\n \r\n .weak UART5_IRQHandler \r\n .thumb_set UART5_IRQHandler,Default_Handler\r\n \r\n .weak TIM6_DAC_IRQHandler \r\n .thumb_set TIM6_DAC_IRQHandler,Default_Handler\r\n \r\n .weak TIM7_IRQHandler \r\n .thumb_set TIM7_IRQHandler,Default_Handler\r\n \r\n .weak DMA2_Stream0_IRQHandler \r\n .thumb_set DMA2_Stream0_IRQHandler,Default_Handler\r\n \r\n .weak DMA2_Stream1_IRQHandler \r\n .thumb_set DMA2_Stream1_IRQHandler,Default_Handler\r\n \r\n .weak DMA2_Stream2_IRQHandler \r\n .thumb_set DMA2_Stream2_IRQHandler,Default_Handler\r\n \r\n .weak DMA2_Stream3_IRQHandler \r\n .thumb_set DMA2_Stream3_IRQHandler,Default_Handler\r\n \r\n .weak DMA2_Stream4_IRQHandler \r\n .thumb_set DMA2_Stream4_IRQHandler,Default_Handler\r\n \r\n .weak ETH_IRQHandler \r\n .thumb_set ETH_IRQHandler,Default_Handler\r\n \r\n .weak ETH_WKUP_IRQHandler \r\n .thumb_set ETH_WKUP_IRQHandler,Default_Handler\r\n \r\n .weak CAN2_TX_IRQHandler \r\n .thumb_set CAN2_TX_IRQHandler,Default_Handler\r\n \r\n .weak CAN2_RX0_IRQHandler \r\n .thumb_set CAN2_RX0_IRQHandler,Default_Handler\r\n \r\n .weak CAN2_RX1_IRQHandler \r\n .thumb_set CAN2_RX1_IRQHandler,Default_Handler\r\n \r\n .weak CAN2_SCE_IRQHandler \r\n .thumb_set CAN2_SCE_IRQHandler,Default_Handler\r\n \r\n .weak OTG_FS_IRQHandler \r\n .thumb_set OTG_FS_IRQHandler,Default_Handler\r\n \r\n .weak DMA2_Stream5_IRQHandler \r\n .thumb_set DMA2_Stream5_IRQHandler,Default_Handler\r\n \r\n .weak DMA2_Stream6_IRQHandler \r\n .thumb_set DMA2_Stream6_IRQHandler,Default_Handler\r\n \r\n .weak DMA2_Stream7_IRQHandler \r\n .thumb_set DMA2_Stream7_IRQHandler,Default_Handler\r\n \r\n .weak USART6_IRQHandler \r\n .thumb_set USART6_IRQHandler,Default_Handler\r\n \r\n .weak I2C3_EV_IRQHandler \r\n .thumb_set I2C3_EV_IRQHandler,Default_Handler\r\n \r\n .weak I2C3_ER_IRQHandler \r\n .thumb_set I2C3_ER_IRQHandler,Default_Handler\r\n \r\n .weak OTG_HS_EP1_OUT_IRQHandler \r\n .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler\r\n \r\n .weak OTG_HS_EP1_IN_IRQHandler \r\n .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler\r\n \r\n .weak OTG_HS_WKUP_IRQHandler \r\n .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler\r\n \r\n .weak OTG_HS_IRQHandler \r\n .thumb_set OTG_HS_IRQHandler,Default_Handler\r\n \r\n .weak DCMI_IRQHandler \r\n .thumb_set DCMI_IRQHandler,Default_Handler\r\n \r\n .weak CRYP_IRQHandler \r\n .thumb_set CRYP_IRQHandler,Default_Handler\r\n \r\n .weak HASH_RNG_IRQHandler \r\n .thumb_set HASH_RNG_IRQHandler,Default_Handler \r\n\r\n .weak FPU_IRQHandler \r\n .thumb_set FPU_IRQHandler,Default_Handler \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n" }, { "path": "figure-simulator-discovery/src/stm32f4xx_conf.h", "content": "/**\r\n*****************************************************************************\r\n**\r\n** File : stm32f4xx_conf.h\r\n**\r\n** Abstract : STM32F4xx library configuration file \r\n**\r\n** Environment : Atollic TrueSTUDIO(R)\r\n** STMicroelectronics STM32F4xx Standard Peripherals Library\r\n**\r\n** Distribution: The file is distributed as is, without any warranty\r\n** of any kind.\r\n**\r\n** (c)Copyright Atollic AB.\r\n** You may use this file as-is or modify it according to the needs of your\r\n** project. Distribution of this file (unmodified or modified) is not\r\n** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the\r\n** rights to distribute the assembled, compiled & linked contents of this\r\n** file as part of an application binary file, provided that it is built\r\n** using the Atollic TrueSTUDIO(R) toolchain.\r\n**\r\n**\r\n*****************************************************************************\r\n*/\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F4xx_CONF_H\r\n#define __STM32F4xx_CONF_H\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n/* Uncomment the line below to enable peripheral header file inclusion */\r\n#include \"stm32f4xx_adc.h\"\r\n#include \"stm32f4xx_can.h\"\r\n#include \"stm32f4xx_crc.h\"\r\n#include \"stm32f4xx_cryp.h\"\r\n#include \"stm32f4xx_dac.h\"\r\n#include \"stm32f4xx_dbgmcu.h\"\r\n#include \"stm32f4xx_dcmi.h\"\r\n#include \"stm32f4xx_dma.h\"\r\n#include \"stm32f4xx_exti.h\"\r\n#include \"stm32f4xx_flash.h\"\r\n#include \"stm32f4xx_fsmc.h\"\r\n#include \"stm32f4xx_hash.h\"\r\n#include \"stm32f4xx_gpio.h\"\r\n#include \"stm32f4xx_i2c.h\"\r\n#include \"stm32f4xx_iwdg.h\"\r\n#include \"stm32f4xx_pwr.h\"\r\n#include \"stm32f4xx_rcc.h\"\r\n#include \"stm32f4xx_rng.h\"\r\n#include \"stm32f4xx_rtc.h\"\r\n#include \"stm32f4xx_sdio.h\"\r\n#include \"stm32f4xx_spi.h\"\r\n#include \"stm32f4xx_syscfg.h\"\r\n#include \"stm32f4xx_tim.h\"\r\n#include \"stm32f4xx_usart.h\"\r\n#include \"stm32f4xx_wwdg.h\"\r\n#include \"misc.h\" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/* If an external clock source is used, then the value of the following define \r\n should be set to the value of the external clock source, else, if no external \r\n clock is used, keep this define commented */\r\n/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */\r\n\r\n\r\n/* Uncomment the line below to expanse the \"assert_param\" macro in the \r\n Standard Peripheral Library drivers code */\r\n/* #define USE_FULL_ASSERT 1 */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n#ifdef USE_FULL_ASSERT\r\n\r\n/**\r\n * @brief The assert_param macro is used for function's parameters check.\r\n * @param expr: If expr is false, it calls assert_failed function\r\n * which reports the name of the source file and the source\r\n * line number of the call that failed. \r\n * If expr is true, it returns no value.\r\n * @retval None\r\n */\r\n #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))\r\n/* Exported functions ------------------------------------------------------- */\r\n void assert_failed(uint8_t* file, uint32_t line);\r\n#else\r\n #define assert_param(expr) ((void)0)\r\n#endif /* USE_FULL_ASSERT */\r\n\r\n#endif /* __STM32F45x_CONF_H */\r\n" }, { "path": "figure-simulator-discovery/src/stm32f4xx_it.c", "content": "/**\r\n*****************************************************************************\r\n**\r\n** File : stm32f4xx_it.c\r\n**\r\n** Abstract : Main Interrupt Service Routines.\r\n** This file provides template for all exceptions handler and\r\n** peripherals interrupt service routine.\r\n**\r\n** Environment : Atollic TrueSTUDIO(R)\r\n** STMicroelectronics STM32F4xx Standard Peripherals Library\r\n**\r\n** Distribution: The file is distributed as is, without any warranty\r\n** of any kind.\r\n**\r\n** (c)Copyright Atollic AB.\r\n** You may use this file as-is or modify it according to the needs of your\r\n** project. Distribution of this file (unmodified or modified) is not\r\n** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the\r\n** rights to distribute the assembled, compiled & linked contents of this\r\n** file as part of an application binary file, provided that it is built\r\n** using the Atollic TrueSTUDIO(R) toolchain.\r\n**\r\n**\r\n*****************************************************************************\r\n*/\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx_it.h\"\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/******************************************************************************/\r\n/* Cortex-M4 Processor Exceptions Handlers */\r\n/******************************************************************************/\r\n\r\n/**\r\n * @brief This function handles NMI exception.\r\n * @param None\r\n * @retval None\r\n */\r\nvoid NMI_Handler(void)\r\n{\r\n}\r\n\r\n/**\r\n * @brief This function handles Hard Fault exception.\r\n * @param None\r\n * @retval None\r\n */\r\nvoid HardFault_Handler(void)\r\n{\r\n /* Go to infinite loop when Hard Fault exception occurs */\r\n while (1)\r\n {\r\n }\r\n}\r\n\r\n/**\r\n * @brief This function handles Memory Manage exception.\r\n * @param None\r\n * @retval None\r\n */\r\nvoid MemManage_Handler(void)\r\n{\r\n /* Go to infinite loop when Memory Manage exception occurs */\r\n while (1)\r\n {\r\n }\r\n}\r\n\r\n/**\r\n * @brief This function handles Bus Fault exception.\r\n * @param None\r\n * @retval None\r\n */\r\nvoid BusFault_Handler(void)\r\n{\r\n /* Go to infinite loop when Bus Fault exception occurs */\r\n while (1)\r\n {\r\n }\r\n}\r\n\r\n/**\r\n * @brief This function handles Usage Fault exception.\r\n * @param None\r\n * @retval None\r\n */\r\nvoid UsageFault_Handler(void)\r\n{\r\n /* Go to infinite loop when Usage Fault exception occurs */\r\n while (1)\r\n {\r\n }\r\n}\r\n\r\n/**\r\n * @brief This function handles SVCall exception.\r\n * @param None\r\n * @retval None\r\n */\r\nvoid SVC_Handler(void)\r\n{\r\n}\r\n\r\n/**\r\n * @brief This function handles Debug Monitor exception.\r\n * @param None\r\n * @retval None\r\n */\r\nvoid DebugMon_Handler(void)\r\n{\r\n}\r\n\r\n/**\r\n * @brief This function handles PendSVC exception.\r\n * @param None\r\n * @retval None\r\n */\r\nvoid PendSV_Handler(void)\r\n{\r\n}\r\n\r\n/**\r\n * @brief This function handles SysTick Handler.\r\n * @param None\r\n * @retval None\r\n */\r\nvoid SysTick_Handler(void)\r\n{\r\n}\r\n\r\n/******************************************************************************/\r\n/* STM32F4xx Peripherals Interrupt Handlers */\r\n/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */\r\n/* available peripheral interrupt handler's name please refer to the startup */\r\n/* file (startup_stm32f4xx.s). */\r\n/******************************************************************************/\r\n\r\n/**\r\n * @brief This function handles PPP interrupt request.\r\n * @param None\r\n * @retval None\r\n */\r\n/*void PPP_IRQHandler(void)\r\n{\r\n}*/\r\n\r\n" }, { "path": "figure-simulator-discovery/src/stm32f4xx_it.h", "content": "/**\r\n*****************************************************************************\r\n**\r\n** File : stm32f4xx_it.h\r\n**\r\n** Abstract : Main Interrupt Service Routines.\r\n** This file provides template for all exceptions handler and\r\n** peripherals interrupt service routine.\r\n**\r\n** Environment : Atollic TrueSTUDIO(R)\r\n** STMicroelectronics STM32F4xx Standard Peripherals Library\r\n**\r\n** Distribution: The file is distributed as is, without any warranty\r\n** of any kind.\r\n**\r\n** (c)Copyright Atollic AB.\r\n** You may use this file as-is or modify it according to the needs of your\r\n** project. Distribution of this file (unmodified or modified) is not\r\n** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the\r\n** rights to distribute the assembled, compiled & linked contents of this\r\n** file as part of an application binary file, provided that it is built\r\n** using the Atollic TrueSTUDIO(R) toolchain.\r\n**\r\n**\r\n*****************************************************************************\r\n*/\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F4xx_IT_H\r\n#define __STM32F4xx_IT_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f4xx.h\"\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions ------------------------------------------------------- */\r\n\r\nvoid NMI_Handler(void);\r\nvoid HardFault_Handler(void);\r\nvoid MemManage_Handler(void);\r\nvoid BusFault_Handler(void);\r\nvoid UsageFault_Handler(void);\r\nvoid SVC_Handler(void);\r\nvoid DebugMon_Handler(void);\r\nvoid PendSV_Handler(void);\r\nvoid SysTick_Handler(void);\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F4xx_IT_H */\r\n" }, { "path": "figure-simulator-discovery/src/system_stm32f4xx.c", "content": "/**\r\n ******************************************************************************\r\n * @file system_stm32f4xx.c\r\n * @author MCD Application Team\r\n * @version V1.0.0\r\n * @date 19-September-2011\r\n * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.\r\n * This file contains the system clock configuration for STM32F4xx devices,\r\n * and is generated by the clock configuration tool\r\n * stm32f4xx_Clock_Configuration_V1.0.0.xls\r\n * \r\n * 1. This file provides two functions and one global variable to be called from \r\n * user application:\r\n * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier\r\n * and Divider factors, AHB/APBx prescalers and Flash settings),\r\n * depending on the configuration made in the clock xls tool. \r\n * This function is called at startup just after reset and \r\n * before branch to main program. This call is made inside\r\n * the \"startup_stm32f4xx.s\" file.\r\n *\r\n * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\r\n * by the user application to setup the SysTick \r\n * timer or configure other parameters.\r\n * \r\n * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\r\n * be called whenever the core clock is changed\r\n * during program execution.\r\n *\r\n * 2. After each device reset the HSI (16 MHz) is used as system clock source.\r\n * Then SystemInit() function is called, in \"startup_stm32f4xx.s\" file, to\r\n * configure the system clock before to branch to main program.\r\n *\r\n * 3. If the system clock source selected by user fails to startup, the SystemInit()\r\n * function will do nothing and HSI still used as system clock source. User can \r\n * add some code to deal with this issue inside the SetSysClock() function.\r\n *\r\n * 4. The default value of HSE crystal is set to 8 MHz, refer to \"HSE_VALUE\" define\r\n * in \"stm32f4xx.h\" file. When HSE is used as system clock source, directly or\r\n * through PLL, and you are using different crystal you have to adapt the HSE\r\n * value to your own configuration.\r\n *\r\n * 5. This file configures the system clock as follows:\r\n *=============================================================================\r\n *=============================================================================\r\n * Supported STM32F4xx device revision | Rev A\r\n *-----------------------------------------------------------------------------\r\n * System Clock source | PLL (HSE)\r\n *-----------------------------------------------------------------------------\r\n * SYSCLK(Hz) | 168000000\r\n *-----------------------------------------------------------------------------\r\n * HCLK(Hz) | 168000000\r\n *-----------------------------------------------------------------------------\r\n * AHB Prescaler | 1\r\n *-----------------------------------------------------------------------------\r\n * APB1 Prescaler | 4\r\n *-----------------------------------------------------------------------------\r\n * APB2 Prescaler | 2\r\n *-----------------------------------------------------------------------------\r\n * HSE Frequency(Hz) | 8000000\r\n *-----------------------------------------------------------------------------\r\n * PLL_M | 8\r\n *-----------------------------------------------------------------------------\r\n * PLL_N | 336\r\n *-----------------------------------------------------------------------------\r\n * PLL_P | 2\r\n *-----------------------------------------------------------------------------\r\n * PLL_Q | 7\r\n *-----------------------------------------------------------------------------\r\n * PLLI2S_N | NA\r\n *-----------------------------------------------------------------------------\r\n * PLLI2S_R | NA\r\n *-----------------------------------------------------------------------------\r\n * I2S input clock | NA\r\n *-----------------------------------------------------------------------------\r\n * VDD(V) | 3.3\r\n *-----------------------------------------------------------------------------\r\n * High Performance mode | Enabled\r\n *-----------------------------------------------------------------------------\r\n * Flash Latency(WS) | 5\r\n *-----------------------------------------------------------------------------\r\n * Prefetch Buffer | OFF\r\n *-----------------------------------------------------------------------------\r\n * Instruction cache | ON\r\n *-----------------------------------------------------------------------------\r\n * Data cache | ON\r\n *-----------------------------------------------------------------------------\r\n * Require 48MHz for USB OTG FS, | Enabled\r\n * SDIO and RNG clock |\r\n *-----------------------------------------------------------------------------\r\n *=============================================================================\r\n ****************************************************************************** \r\n * @attention\r\n *\r\n * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r\n * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r\n * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r\n * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r\n * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r\n * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r\n *\r\n *

© COPYRIGHT 2011 STMicroelectronics

\r\n ******************************************************************************\r\n */\r\n\r\n/** @addtogroup CMSIS\r\n * @{\r\n */\r\n\r\n/** @addtogroup stm32f4xx_system\r\n * @{\r\n */ \r\n \r\n/** @addtogroup STM32F4xx_System_Private_Includes\r\n * @{\r\n */\r\n\r\n#include \"stm32f4xx.h\"\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @addtogroup STM32F4xx_System_Private_TypesDefinitions\r\n * @{\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @addtogroup STM32F4xx_System_Private_Defines\r\n * @{\r\n */\r\n\r\n/*!< Uncomment the following line if you need to use external SRAM mounted\r\n on STM324xG_EVAL board as data memory */\r\n/* #define DATA_IN_ExtSRAM */\r\n\r\n/*!< Uncomment the following line if you need to relocate your vector Table in\r\n Internal SRAM. */\r\n/* #define VECT_TAB_SRAM */\r\n#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. \r\n This value must be a multiple of 0x200. */\r\n\r\n\r\n/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */\r\n#define PLL_M 8\r\n#define PLL_N 500\r\n\r\n/* SYSCLK = PLL_VCO / PLL_P */\r\n#define PLL_P 2\r\n\r\n/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */\r\n#define PLL_Q 7\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @addtogroup STM32F4xx_System_Private_Macros\r\n * @{\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @addtogroup STM32F4xx_System_Private_Variables\r\n * @{\r\n */\r\n\r\n uint32_t SystemCoreClock = 168000000;\r\n\r\n __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes\r\n * @{\r\n */\r\n\r\nstatic void SetSysClock(void);\r\n#ifdef DATA_IN_ExtSRAM\r\n static void SystemInit_ExtMemCtl(void); \r\n#endif /* DATA_IN_ExtSRAM */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @addtogroup STM32F4xx_System_Private_Functions\r\n * @{\r\n */\r\n\r\n/**\r\n * @brief Setup the microcontroller system\r\n * Initialize the Embedded Flash Interface, the PLL and update the \r\n * SystemFrequency variable.\r\n * @param None\r\n * @retval None\r\n */\r\nvoid SystemInit(void)\r\n{\r\n /* FPU settings ------------------------------------------------------------*/\r\n #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r\n\tSCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */\r\n #endif\r\n\r\n /* Reset the RCC clock configuration to the default reset state ------------*/\r\n /* Set HSION bit */\r\n RCC->CR |= (uint32_t)0x00000001;\r\n\r\n /* Reset CFGR register */\r\n RCC->CFGR = 0x00000000;\r\n\r\n /* Reset HSEON, CSSON and PLLON bits */\r\n RCC->CR &= (uint32_t)0xFEF6FFFF;\r\n\r\n /* Reset PLLCFGR register */\r\n RCC->PLLCFGR = 0x24003010;\r\n\r\n /* Reset HSEBYP bit */\r\n RCC->CR &= (uint32_t)0xFFFBFFFF;\r\n\r\n /* Disable all interrupts */\r\n RCC->CIR = 0x00000000;\r\n\r\n#ifdef DATA_IN_ExtSRAM\r\n SystemInit_ExtMemCtl(); \r\n#endif /* DATA_IN_ExtSRAM */\r\n \r\n /* Configure the System clock source, PLL Multiplier and Divider factors, \r\n AHB/APBx prescalers and Flash settings ----------------------------------*/\r\n SetSysClock();\r\n\r\n /* Configure the Vector Table location add offset address ------------------*/\r\n#ifdef VECT_TAB_SRAM\r\n SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */\r\n#else\r\n SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Update SystemCoreClock variable according to Clock Register Values.\r\n * The SystemCoreClock variable contains the core clock (HCLK), it can\r\n * be used by the user application to setup the SysTick timer or configure\r\n * other parameters.\r\n * \r\n * @note Each time the core clock (HCLK) changes, this function must be called\r\n * to update SystemCoreClock variable value. Otherwise, any configuration\r\n * based on this variable will be incorrect. \r\n * \r\n * @note - The system frequency computed by this function is not the real \r\n * frequency in the chip. It is calculated based on the predefined \r\n * constant and the selected clock source:\r\n * \r\n * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)\r\n * \r\n * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)\r\n * \r\n * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) \r\n * or HSI_VALUE(*) multiplied/divided by the PLL factors.\r\n * \r\n * (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value\r\n * 16 MHz) but the real value may vary depending on the variations\r\n * in voltage and temperature. \r\n * \r\n * (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value\r\n * 25 MHz), user has to ensure that HSE_VALUE is same as the real\r\n * frequency of the crystal used. Otherwise, this function may\r\n * have wrong result.\r\n * \r\n * - The result of this function could be not correct when using fractional\r\n * value for HSE crystal.\r\n * \r\n * @param None\r\n * @retval None\r\n */\r\nvoid SystemCoreClockUpdate(void)\r\n{\r\n uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;\r\n \r\n /* Get SYSCLK source -------------------------------------------------------*/\r\n tmp = RCC->CFGR & RCC_CFGR_SWS;\r\n\r\n switch (tmp)\r\n {\r\n case 0x00: /* HSI used as system clock source */\r\n SystemCoreClock = HSI_VALUE;\r\n break;\r\n case 0x04: /* HSE used as system clock source */\r\n SystemCoreClock = HSE_VALUE;\r\n break;\r\n case 0x08: /* PLL used as system clock source */\r\n\r\n /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N\r\n SYSCLK = PLL_VCO / PLL_P\r\n */ \r\n pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;\r\n pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;\r\n \r\n if (pllsource != 0)\r\n {\r\n /* HSE used as PLL clock source */\r\n pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);\r\n }\r\n else\r\n {\r\n /* HSI used as PLL clock source */\r\n pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); \r\n }\r\n\r\n pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;\r\n SystemCoreClock = pllvco/pllp;\r\n break;\r\n default:\r\n SystemCoreClock = HSI_VALUE;\r\n break;\r\n }\r\n /* Compute HCLK frequency --------------------------------------------------*/\r\n /* Get HCLK prescaler */\r\n tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];\r\n /* HCLK frequency */\r\n SystemCoreClock >>= tmp;\r\n}\r\n\r\n/**\r\n * @brief Configures the System clock source, PLL Multiplier and Divider factors, \r\n * AHB/APBx prescalers and Flash settings\r\n * @Note This function should be called only once the RCC clock configuration \r\n * is reset to the default reset state (done in SystemInit() function). \r\n * @param None\r\n * @retval None\r\n */\r\nstatic void SetSysClock(void)\r\n{\r\n/******************************************************************************/\r\n/* PLL (clocked by HSE) used as System clock source */\r\n/******************************************************************************/\r\n __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r\n \r\n /* Enable HSE */\r\n RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r\n \r\n /* Wait till HSE is ready and if Time out is reached exit */\r\n do\r\n {\r\n HSEStatus = RCC->CR & RCC_CR_HSERDY;\r\n StartUpCounter++;\r\n } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));\r\n\r\n if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r\n {\r\n HSEStatus = (uint32_t)0x01;\r\n }\r\n else\r\n {\r\n HSEStatus = (uint32_t)0x00;\r\n }\r\n\r\n if (HSEStatus == (uint32_t)0x01)\r\n {\r\n /* Enable high performance mode, System frequency up to 168 MHz */\r\n RCC->APB1ENR |= RCC_APB1ENR_PWREN;\r\n PWR->CR |= PWR_CR_PMODE; \r\n\r\n /* HCLK = SYSCLK / 1*/\r\n RCC->CFGR |= RCC_CFGR_HPRE_DIV1;\r\n \r\n /* PCLK2 = HCLK / 2*/\r\n RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;\r\n \r\n /* PCLK1 = HCLK / 4*/\r\n RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;\r\n\r\n /* Configure the main PLL */\r\n RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |\r\n (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);\r\n\r\n /* Enable the main PLL */\r\n RCC->CR |= RCC_CR_PLLON;\r\n\r\n /* Wait till the main PLL is ready */\r\n while((RCC->CR & RCC_CR_PLLRDY) == 0)\r\n {\r\n }\r\n \r\n /* Configure Flash prefetch, Instruction cache, Data cache and wait state */\r\n FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;\r\n\r\n /* Select the main PLL as system clock source */\r\n RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r\n RCC->CFGR |= RCC_CFGR_SW_PLL;\r\n\r\n /* Wait till the main PLL is used as system clock source */\r\n while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);\r\n {\r\n }\r\n }\r\n else\r\n { /* If HSE fails to start-up, the application will have wrong clock\r\n configuration. User can add here some code to deal with this error */\r\n }\r\n\r\n}\r\n\r\n/**\r\n * @brief Setup the external memory controller. Called in startup_stm32f4xx.s \r\n * before jump to __main\r\n * @param None\r\n * @retval None\r\n */ \r\n#ifdef DATA_IN_ExtSRAM\r\n/**\r\n * @brief Setup the external memory controller.\r\n * Called in startup_stm32f4xx.s before jump to main.\r\n * This function configures the external SRAM mounted on STM324xG_EVAL board\r\n * This SRAM will be used as program data memory (including heap and stack).\r\n * @param None\r\n * @retval None\r\n */\r\nvoid SystemInit_ExtMemCtl(void)\r\n{\r\n/*-- GPIOs Configuration -----------------------------------------------------*/\r\n/*\r\n +-------------------+--------------------+------------------+------------------+\r\n + SRAM pins assignment +\r\n +-------------------+--------------------+------------------+------------------+\r\n | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | \r\n | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | \r\n | PD4 <-> FSMC_NOE | PE3 <-> FSMC_A19 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | \r\n | PD5 <-> FSMC_NWE | PE4 <-> FSMC_A20 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | \r\n | PD8 <-> FSMC_D13 | PE7 <-> FSMC_D4 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | \r\n | PD9 <-> FSMC_D14 | PE8 <-> FSMC_D5 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | \r\n | PD10 <-> FSMC_D15 | PE9 <-> FSMC_D6 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | \r\n | PD11 <-> FSMC_A16 | PE10 <-> FSMC_D7 | PF13 <-> FSMC_A7 |------------------+\r\n | PD12 <-> FSMC_A17 | PE11 <-> FSMC_D8 | PF14 <-> FSMC_A8 | \r\n | PD13 <-> FSMC_A18 | PE12 <-> FSMC_D9 | PF15 <-> FSMC_A9 | \r\n | PD14 <-> FSMC_D0 | PE13 <-> FSMC_D10 |------------------+\r\n | PD15 <-> FSMC_D1 | PE14 <-> FSMC_D11 |\r\n | | PE15 <-> FSMC_D12 |\r\n +-------------------+--------------------+\r\n*/\r\n /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */\r\n RCC->AHB1ENR = 0x00000078;\r\n \r\n /* Connect PDx pins to FSMC Alternate function */\r\n GPIOD->AFR[0] = 0x00cc00cc;\r\n GPIOD->AFR[1] = 0xcc0ccccc;\r\n /* Configure PDx pins in Alternate function mode */ \r\n GPIOD->MODER = 0xaaaa0a0a;\r\n /* Configure PDx pins speed to 100 MHz */ \r\n GPIOD->OSPEEDR = 0xffff0f0f;\r\n /* Configure PDx pins Output type to push-pull */ \r\n GPIOD->OTYPER = 0x00000000;\r\n /* No pull-up, pull-down for PDx pins */ \r\n GPIOD->PUPDR = 0x00000000;\r\n\r\n /* Connect PEx pins to FSMC Alternate function */\r\n GPIOE->AFR[0] = 0xc00cc0cc;\r\n GPIOE->AFR[1] = 0xcccccccc;\r\n /* Configure PEx pins in Alternate function mode */ \r\n GPIOE->MODER = 0xaaaa828a;\r\n /* Configure PEx pins speed to 100 MHz */ \r\n GPIOE->OSPEEDR = 0xffffc3cf;\r\n /* Configure PEx pins Output type to push-pull */ \r\n GPIOE->OTYPER = 0x00000000;\r\n /* No pull-up, pull-down for PEx pins */ \r\n GPIOE->PUPDR = 0x00000000;\r\n\r\n /* Connect PFx pins to FSMC Alternate function */\r\n GPIOF->AFR[0] = 0x00cccccc;\r\n GPIOF->AFR[1] = 0xcccc0000;\r\n /* Configure PFx pins in Alternate function mode */ \r\n GPIOF->MODER = 0xaa000aaa;\r\n /* Configure PFx pins speed to 100 MHz */ \r\n GPIOF->OSPEEDR = 0xff000fff;\r\n /* Configure PFx pins Output type to push-pull */ \r\n GPIOF->OTYPER = 0x00000000;\r\n /* No pull-up, pull-down for PFx pins */ \r\n GPIOF->PUPDR = 0x00000000;\r\n\r\n /* Connect PGx pins to FSMC Alternate function */\r\n GPIOG->AFR[0] = 0x00cccccc;\r\n GPIOG->AFR[1] = 0x000000c0;\r\n /* Configure PGx pins in Alternate function mode */ \r\n GPIOG->MODER = 0x00080aaa;\r\n /* Configure PGx pins speed to 100 MHz */ \r\n GPIOG->OSPEEDR = 0x000c0fff;\r\n /* Configure PGx pins Output type to push-pull */ \r\n GPIOG->OTYPER = 0x00000000;\r\n /* No pull-up, pull-down for PGx pins */ \r\n GPIOG->PUPDR = 0x00000000;\r\n \r\n/*-- FSMC Configuration ------------------------------------------------------*/\r\n /* Enable the FSMC interface clock */\r\n RCC->AHB3ENR = 0x00000001;\r\n\r\n /* Configure and enable Bank1_SRAM2 */\r\n FSMC_Bank1->BTCR[2] = 0x00001015;\r\n FSMC_Bank1->BTCR[3] = 0x00010603;//0x00010400;\r\n FSMC_Bank1E->BWTR[2] = 0x0fffffff;\r\n/*\r\n Bank1_SRAM2 is configured as follow:\r\n\r\n p.FSMC_AddressSetupTime = 3;//0;\r\n p.FSMC_AddressHoldTime = 0;\r\n p.FSMC_DataSetupTime = 6;//4;\r\n p.FSMC_BusTurnAroundDuration = 1;\r\n p.FSMC_CLKDivision = 0;\r\n p.FSMC_DataLatency = 0;\r\n p.FSMC_AccessMode = FSMC_AccessMode_A;\r\n\r\n FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;\r\n FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;\r\n FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;\r\n FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;\r\n FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;\r\n FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; \r\n FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;\r\n FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;\r\n FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;\r\n FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;\r\n FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;\r\n FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;\r\n FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;\r\n FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;\r\n FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;\r\n*/\r\n \r\n}\r\n#endif /* DATA_IN_ExtSRAM */\r\n\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n \r\n/**\r\n * @}\r\n */ \r\n/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r\n\r\n" }, { "path": "figure-simulator-discovery/src/tiny_printf.c", "content": "/**\r\n*****************************************************************************\r\n**\r\n** File : tiny_printf.c\r\n**\r\n** Abstract : Atollic TrueSTUDIO Minimal printf/sprintf/fprintf\r\n** and puts/fputs\r\n**\r\n** The argument contains a format string that may include\r\n** conversion specifications. Each conversion specification\r\n** is introduced by the character %, and ends with a\r\n** conversion specifier.\r\n**\r\n** The following conversion specifiers are supported\r\n** cdisuxX%\r\n**\r\n** Usage:\r\n** c character\r\n** d,i signed integer (-sign added, + sign not supported)\r\n** s character string\r\n** u unsigned integer as decimal\r\n** x,X unsigned integer as hexadecimal (uppercase letter)\r\n** % % is written (conversion specification is '%%')\r\n**\r\n** Note:\r\n** Character padding is not supported\r\n**\r\n** Environment : Atollic TrueSTUDIO\r\n**\r\n** Distribution: The file is distributed as is, without any warranty\r\n** of any kind.\r\n**\r\n** (c)Copyright Atollic AB.\r\n** You may use this file as-is or modify it according to the needs of your\r\n** project. Distribution of this file (unmodified or modified) is not\r\n** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the\r\n** rights to distribute the assembled, compiled & linked contents of this\r\n** file as part of an application binary file, provided that it is built\r\n** using the Atollic TrueSTUDIO(R) Pro toolchain.\r\n**\r\n*****************************************************************************\r\n*/\r\n\r\n/* Includes */\r\n#include \r\n#include \r\n#include \r\n\r\n/* External function prototypes (defined in syscalls.c) */\r\nextern int _write(int fd, char *str, int len);\r\n\r\n/* Private function prototypes */\r\nvoid ts_itoa(char **buf, unsigned int d, int base);\r\nint ts_formatstring(char *buf, const char *fmt, va_list va);\r\nint ts_formatlength(const char *fmt, va_list va);\r\n\r\n/* Private functions */\r\n\r\n/**\r\n**---------------------------------------------------------------------------\r\n** Abstract: Convert integer to ascii\r\n** Returns: void\r\n**---------------------------------------------------------------------------\r\n*/\r\nvoid ts_itoa(char **buf, unsigned int d, int base)\r\n{\r\n\tint div = 1;\r\n\twhile (d/div >= base)\r\n\t\tdiv *= base;\r\n\r\n\twhile (div != 0)\r\n\t{\r\n\t\tint num = d/div;\r\n\t\td = d%div;\r\n\t\tdiv /= base;\r\n\t\tif (num > 9)\r\n\t\t\t*((*buf)++) = (num-10) + 'A';\r\n\t\telse\r\n\t\t\t*((*buf)++) = num + '0';\r\n\t}\r\n}\r\n\r\n/**\r\n**---------------------------------------------------------------------------\r\n** Abstract: Writes arguments va to buffer buf according to format fmt\r\n** Returns: Length of string\r\n**---------------------------------------------------------------------------\r\n*/\r\nint ts_formatstring(char *buf, const char *fmt, va_list va)\r\n{\r\n\tchar *start_buf = buf;\r\n\twhile(*fmt)\r\n\t{\r\n\t\t/* Character needs formating? */\r\n\t\tif (*fmt == '%')\r\n\t\t{\r\n\t\t\tswitch (*(++fmt))\r\n\t\t\t{\r\n\t\t\t case 'c':\r\n\t\t\t\t*buf++ = va_arg(va, int);\r\n\t\t\t\tbreak;\r\n\t\t\t case 'd':\r\n\t\t\t case 'i':\r\n\t\t\t\t{\r\n\t\t\t\t\tsigned int val = va_arg(va, signed int);\r\n\t\t\t\t\tif (val < 0)\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tval *= -1;\r\n\t\t\t\t\t\t*buf++ = '-';\r\n\t\t\t\t\t}\r\n\t\t\t\t\tts_itoa(&buf, val, 10);\r\n\t\t\t\t}\r\n\t\t\t\tbreak;\r\n\t\t\t case 's':\r\n\t\t\t\t{\r\n\t\t\t\t\tchar * arg = va_arg(va, char *);\r\n\t\t\t\t\twhile (*arg)\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t*buf++ = *arg++;\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\tbreak;\r\n\t\t\t case 'u':\r\n\t\t\t\t\tts_itoa(&buf, va_arg(va, unsigned int), 10);\r\n\t\t\t\tbreak;\r\n\t\t\t case 'x':\r\n\t\t\t case 'X':\r\n\t\t\t\t\tts_itoa(&buf, va_arg(va, int), 16);\r\n\t\t\t\tbreak;\r\n\t\t\t case '%':\r\n\t\t\t\t *buf++ = '%';\r\n\t\t\t\t break;\r\n\t\t\t}\r\n\t\t\tfmt++;\r\n\t\t}\r\n\t\t/* Else just copy */\r\n\t\telse\r\n\t\t{\r\n\t\t\t*buf++ = *fmt++;\r\n\t\t}\r\n\t}\r\n\t*buf = 0;\r\n\r\n\treturn (int)(buf - start_buf);\r\n}\r\n\r\n\r\n/**\r\n**---------------------------------------------------------------------------\r\n** Abstract: Calculate maximum length of the resulting string from the\r\n** format string and va_list va\r\n** Returns: Maximum length\r\n**---------------------------------------------------------------------------\r\n*/\r\nint ts_formatlength(const char *fmt, va_list va)\r\n{\r\n\tint length = 0;\r\n\twhile (*fmt)\r\n\t{\r\n\t\tif (*fmt == '%')\r\n\t\t{\r\n\t\t\t++fmt;\r\n\t\t\tswitch (*fmt)\r\n\t\t\t{\r\n\t\t\t case 'c':\r\n\t\t \t\t va_arg(va, int);\r\n\t\t\t\t ++length;\r\n\t\t\t\t break;\r\n\t\t\t case 'd':\r\n\t\t\t case 'i':\r\n\t\t\t case 'u':\r\n\t\t\t\t /* 32 bits integer is max 11 characters with minus sign */\r\n\t\t\t\t length += 11;\r\n\t\t\t\t va_arg(va, int);\r\n\t\t\t\t break;\r\n\t\t\t case 's':\r\n\t\t\t \t {\r\n\t\t\t \t\t char * str = va_arg(va, char *);\r\n\t\t\t \t\t while (*str++)\r\n\t\t\t \t\t\t ++length;\r\n\t\t\t \t }\r\n\t\t\t\t break;\r\n\t\t\t case 'x':\r\n\t\t\t case 'X':\r\n\t\t\t\t /* 32 bits integer as hex is max 8 characters */\r\n\t\t\t\t length += 8;\r\n\t\t\t\t va_arg(va, unsigned int);\r\n\t\t\t\t break;\r\n\t\t\t default:\r\n\t\t\t\t ++length;\r\n\t\t\t\t break;\r\n\t\t\t}\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\t++length;\r\n\t\t}\r\n\t\t++fmt;\r\n\t}\r\n\treturn length;\r\n}\r\n\r\n/**\r\n**===========================================================================\r\n** Abstract: Loads data from the given locations and writes them to the\r\n** given character string according to the format parameter.\r\n** Returns: Number of bytes written\r\n**===========================================================================\r\n*/\r\nint sprintf(char *buf, const char *fmt, ...)\r\n{\r\n\tint length;\r\n\tva_list va;\r\n\tva_start(va, fmt);\r\n\tlength = ts_formatstring(buf, fmt, va);\r\n\tva_end(va);\r\n\treturn length;\r\n}\r\n\r\n/**\r\n**===========================================================================\r\n** Abstract: Loads data from the given locations and writes them to the\r\n** given file stream according to the format parameter.\r\n** Returns: Number of bytes written\r\n**===========================================================================\r\n*/\r\nint fprintf(FILE * stream, const char *fmt, ...)\r\n{\r\n\tint length = 0;\r\n\tva_list va;\r\n\tva_start(va, fmt);\r\n\tlength = ts_formatlength(fmt, va);\r\n\tva_end(va);\r\n\t{\r\n\t\tchar buf[length];\r\n\t\tva_start(va, fmt);\r\n\t\tlength = ts_formatstring(buf, fmt, va);\r\n\t\tlength = _write(stream->_file, buf, length);\r\n\t\tva_end(va);\r\n\t}\r\n\treturn length;\r\n}\r\n\r\n/**\r\n**===========================================================================\r\n** Abstract: Loads data from the given locations and writes them to the\r\n** standard output according to the format parameter.\r\n** Returns: Number of bytes written\r\n**\r\n**===========================================================================\r\n*/\r\nint printf(const char *fmt, ...)\r\n{\r\n\tint length = 0;\r\n\tva_list va;\r\n\tva_start(va, fmt);\r\n\tlength = ts_formatlength(fmt, va);\r\n\tva_end(va);\r\n\t{\r\n\t\tchar buf[length];\r\n\t\tva_start(va, fmt);\r\n\t\tlength = ts_formatstring(buf, fmt, va);\r\n\t\tlength = _write(1, buf, length);\r\n\t\tva_end(va);\r\n\t}\r\n\treturn length;\r\n}\r\n\r\n/**\r\n**===========================================================================\r\n** Abstract: fputs writes the string at s (but without the trailing null) to\r\n** the file or stream identified by fp.\r\n** Returns: If successful, the result is 0; otherwise, the result is EOF.\r\n**\r\n**===========================================================================\r\n*/\r\nint fputs(const char *s, FILE *fp)\r\n{\r\n\tint length = strlen(s);\r\n\tint wlen = 0;\r\n\tint res;\r\n\r\n\twlen = _write((fp->_file), (char*)s, length);\r\n\twlen += _write((fp->_file), \"\\n\", 1);\r\n\r\n\tif (wlen == (length+1))\r\n\t{\r\n\t\tres = 0;\r\n\t}\r\n\telse\r\n\t{\r\n\t\tres = EOF;\r\n\t}\r\n\r\n\treturn res;\r\n}\r\n\r\n/**\r\n**===========================================================================\r\n** Abstract: puts writes the string at s (followed by a newline, instead of\r\n** the trailing null) to the standard output stream.\r\n** Returns: If successful, the result is a nonnegative integer; otherwise,\r\n** the result is EOF.\r\n**\r\n**===========================================================================\r\n*/\r\nint puts(const char *s)\r\n{\r\n\tint length = strlen(s);\r\n\tint numbytes = 0;\r\n\tint res;\r\n\r\n\tnumbytes = _write(1, (char*)s, length);\r\n\tnumbytes += _write(1, \"\\n\", 1);\r\n\r\n\tif (numbytes == (length+1))\r\n\t{\r\n\t\tres = 0;\r\n\t}\r\n\telse\r\n\t{\r\n\t\tres = EOF;\r\n\t}\r\n\r\n\treturn res;\r\n}\r\n" }, { "path": "figure-simulator-discovery/stm32f4_flash.ld", "content": "/*\n*****************************************************************************\n**\n** File : stm32_flash.ld\n**\n** Abstract : Linker script for STM32F407VG Device with\n** 1024KByte FLASH, 128KByte RAM\n**\n** Set heap size, stack size and stack location according\n** to application requirements.\n**\n** Set memory bank area and size if external memory is used.\n**\n** Target : STMicroelectronics STM32\n**\n** Environment : Atollic TrueSTUDIO(R)\n**\n** Distribution: The file is distributed as is, without any warranty\n** of any kind.\n**\n** (c)Copyright Atollic AB.\n** You may use this file as-is or modify it according to the needs of your\n** project. Distribution of this file (unmodified or modified) is not\n** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the\n** rights to distribute the assembled, compiled & linked contents of this\n** file as part of an application binary file, provided that it is built\n** using the Atollic TrueSTUDIO(R) toolchain.\n**\n*****************************************************************************\n*/\n\n/* Entry Point */\nENTRY(Reset_Handler)\n\n/* Highest address of the user mode stack */\n_estack = 0x20020000; /* end of 128K RAM */\n\n/* Generate a link error if heap and stack don't fit into RAM */\n_Min_Heap_Size = 0; /* required amount of heap */\n_Min_Stack_Size = 0x400; /* required amount of stack */\n\n/* Specify the memory areas */\nMEMORY\n{\n FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K\n RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K\n MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K\n CCMRAM (rw) : ORIGIN = 0x10000000, LENGTH = 64K\n}\n\n/* Define output sections */\nSECTIONS\n{\n /* The startup code goes first into FLASH */\n .isr_vector :\n {\n . = ALIGN(4);\n KEEP(*(.isr_vector)) /* Startup code */\n . = ALIGN(4);\n } >FLASH\n\n /* The program code and other data goes into FLASH */\n .text :\n {\n . = ALIGN(4);\n *(.text) /* .text sections (code) */\n *(.text*) /* .text* sections (code) */\n *(.rodata) /* .rodata sections (constants, strings, etc.) */\n *(.rodata*) /* .rodata* sections (constants, strings, etc.) */\n *(.glue_7) /* glue arm to thumb code */\n *(.glue_7t) /* glue thumb to arm code */\n *(.eh_frame)\n\n KEEP (*(.init))\n KEEP (*(.fini))\n\n . = ALIGN(4);\n _etext = .; /* define a global symbols at end of code */\n } >FLASH\n\n\n .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n .ARM : {\n __exidx_start = .;\n *(.ARM.exidx*)\n __exidx_end = .;\n } >FLASH\n\n .preinit_array :\n {\n PROVIDE_HIDDEN (__preinit_array_start = .);\n KEEP (*(.preinit_array*))\n PROVIDE_HIDDEN (__preinit_array_end = .);\n } >FLASH\n .init_array :\n {\n PROVIDE_HIDDEN (__init_array_start = .);\n KEEP (*(SORT(.init_array.*)))\n KEEP (*(.init_array*))\n PROVIDE_HIDDEN (__init_array_end = .);\n } >FLASH\n .fini_array :\n {\n PROVIDE_HIDDEN (__fini_array_start = .);\n KEEP (*(SORT(.fini_array.*)))\n KEEP (*(.fini_array*))\n PROVIDE_HIDDEN (__fini_array_end = .);\n } >FLASH\n\n /* used by the startup to initialize data */\n _sidata = LOADADDR(.data);\n\n /* Initialized data sections goes into RAM, load LMA copy after code */\n .data : \n {\n . = ALIGN(4);\n _sdata = .; /* create a global symbol at data start */\n *(.data) /* .data sections */\n *(.data*) /* .data* sections */\n\n . = ALIGN(4);\n _edata = .; /* define a global symbol at data end */\n } >RAM AT> FLASH\n \n _siccmram = LOADADDR(.ccmram);\n\n /* CCM-RAM section \n * \n * IMPORTANT NOTE! \n * If initialized variables will be placed in this section, \n * the startup code needs to be modified to copy the init-values. \n */\n .ccmram :\n {\n . = ALIGN(4);\n _sccmram = .; /* create a global symbol at ccmram start */\n *(.ccmram)\n *(.ccmram*)\n \n . = ALIGN(4);\n _eccmram = .; /* create a global symbol at ccmram end */\n } >CCMRAM AT> FLASH\n\n /* Uninitialized data section */\n . = ALIGN(4);\n .bss :\n {\n /* This is used by the startup in order to initialize the .bss secion */\n _sbss = .; /* define a global symbol at bss start */\n __bss_start__ = _sbss;\n *(.bss)\n *(.bss*)\n *(COMMON)\n\n . = ALIGN(4);\n _ebss = .; /* define a global symbol at bss end */\n __bss_end__ = _ebss;\n } >RAM\n\n /* User_heap_stack section, used to check that there is enough RAM left */\n ._user_heap_stack :\n {\n . = ALIGN(4);\n PROVIDE ( end = . );\n PROVIDE ( _end = . );\n . = . + _Min_Heap_Size;\n . = . + _Min_Stack_Size;\n . = ALIGN(4);\n } >RAM\n\n /* MEMORY_bank1 section, code must be located here explicitly */\n /* Example: extern int foo(void) __attribute__ ((section (\".mb1text\"))); */\n .memory_b1_text :\n {\n *(.mb1text) /* .mb1text sections (code) */\n *(.mb1text*) /* .mb1text* sections (code) */\n *(.mb1rodata) /* read-only data (constants) */\n *(.mb1rodata*)\n } >MEMORY_B1\n\n /* Remove information from the standard libraries */\n /DISCARD/ :\n {\n libc.a ( * )\n libm.a ( * )\n libgcc.a ( * )\n }\n\n .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n" }, { "path": "imageformats/README", "content": "Repository for Tamagotchi image coverters!\r\n\r\nconv.py -- converts a 16 bit bitmap to a Tamagotchi image\r\n\r\nQuestions? Comments? Contributions? \r\n\r\nContact: namely_audacious@hotmail.com / @natashenka" }, { "path": "imageformats/conv.py", "content": "\r\ns = \"\"\r\ntmp = 0\r\nrol = 0\r\n\r\nimport Image\r\n\r\nim = Image.open(\"../../../pictures/harlem/title.bmp\")\r\n\r\ndef tofourbit(a):\r\n\t#print a\r\n\tif ((a > -1) and (a < 1)):\r\n\t\treturn 3;\r\n\tif ((a > 0) and (a < 8)):\r\n\t\treturn 2;\r\n\tif ((a > 7) and (a < 10 )):\r\n\t\treturn 1;\r\n\tif (a > 9):\r\n\t\treturn 0;\r\n\r\ndef conv(a):\r\n\r\n\tt = 0;\r\n\tt = t | (tofourbit(ord(a) & 0x0f) << 2)\r\n\tt = t | (tofourbit((ord(a) & 0xf0) >> 4))\r\n\treturn t\r\ni = 0\r\nwidth = im.size[0]\r\nheight = im.size[1]\r\nwhile ( i < (width * height) ):\r\n\ttmp = 0;\r\n\t#print \"start\"\r\n\t#if( (i + 1)% 17) == 0:\r\n\t#\ttmp = tmp | tofourbit(im.getpixel(((i)%17, (i)/17)))\r\n\t#\ti = i + 1\t\r\n\t#\ttmp = tmp << 6\r\n\r\n\t#else:\r\n\tif(1):\r\n\t\tfor j in range(0, 4):\r\n\t\t\t\r\n\t\t\ttmp = tmp | tofourbit(im.getpixel(((i)%width, (i)/width)))\r\n\t\t\t\r\n\t\t\ti = i + 1\r\n\t\t\tif j != 3:\r\n\t\t\t\ttmp = tmp * 4\r\n\t\t\t#print tmp\r\n\t\t\t\r\n\r\n\t#print tmp\r\n\ts = s + chr(tmp)\r\n\t\r\nf = open(\"pic.txt\", 'ab')\r\nf.write(chr(width))\r\nf.write(chr(height))\r\nf.write(s)\r\nprint len(s)\r\n\r\n" } ]