Repository: natashenka/Tamagotchi-Hack Branch: master Commit: b88aa36c5bf0 Files: 248 Total size: 39.1 MB Directory structure: gitextract_qaqs9osu/ ├── IR/ │ ├── README.txt │ ├── ir.pde │ └── ir2.pde ├── README ├── RFIDler/ │ └── tama.py ├── TamagotchiFriends/ │ └── proxmark/ │ └── armsrc/ │ ├── LCD.c │ ├── LCD.h │ ├── Makefile │ ├── appmain.c │ ├── apps.h │ ├── crapto1.c │ ├── crapto1.h │ ├── crypto1.c │ ├── epa.c │ ├── epa.h │ ├── fonts.c │ ├── fonts.h │ ├── fpgaloader.c │ ├── hitag2.c │ ├── iclass.c │ ├── iso14443.c │ ├── iso14443a.c │ ├── iso14443a.h │ ├── iso15693.c │ ├── ldscript │ ├── legicrf.c │ ├── legicrf.h │ ├── lfops.c │ ├── lfops_rcv_works.txt │ ├── mifarecmd.c │ ├── mifarecmd.h │ ├── mifaresniff.c │ ├── mifaresniff.h │ ├── mifareutil.c │ ├── mifareutil.h │ ├── obj/ │ │ ├── appmain.d │ │ ├── appmain.o │ │ ├── cmd.d │ │ ├── cmd.o │ │ ├── crapto1.d │ │ ├── crapto1.o │ │ ├── crc.d │ │ ├── crc.o │ │ ├── crc16.d │ │ ├── crc16.o │ │ ├── crypto1.d │ │ ├── crypto1.o │ │ ├── epa.d │ │ ├── epa.o │ │ ├── fpga.o │ │ ├── fpgaimage.elf │ │ ├── fpgaimage.s19 │ │ ├── fpgaloader.d │ │ ├── fpgaloader.o │ │ ├── fullimage.elf │ │ ├── hitag2.d │ │ ├── hitag2.o │ │ ├── iclass.d │ │ ├── iclass.o │ │ ├── iso14443.d │ │ ├── iso14443.o │ │ ├── iso14443a.d │ │ ├── iso14443a.o │ │ ├── iso14443crc.d │ │ ├── iso14443crc.o │ │ ├── iso15693.d │ │ ├── iso15693.o │ │ ├── iso15693tools.d │ │ ├── iso15693tools.o │ │ ├── legic_prng.d │ │ ├── legic_prng.o │ │ ├── legicrf.d │ │ ├── legicrf.o │ │ ├── lfops.d │ │ ├── lfops.o │ │ ├── mifarecmd.d │ │ ├── mifarecmd.o │ │ ├── mifaresniff.d │ │ ├── mifaresniff.o │ │ ├── mifareutil.d │ │ ├── mifareutil.o │ │ ├── osimage.elf │ │ ├── osimage.s19 │ │ ├── printf.d │ │ ├── printf.o │ │ ├── start.d │ │ ├── start.o │ │ ├── string.d │ │ ├── string.o │ │ ├── usb_cdc.d │ │ ├── usb_cdc.o │ │ ├── util.d │ │ ├── util.o │ │ └── version.o │ ├── printf.c │ ├── printf.h │ ├── start.c │ ├── stdint.h │ ├── string.c │ ├── string.h │ ├── util.c │ ├── util.h │ └── version.c ├── TamagotchiOn/ │ └── tasmgotchi/ │ ├── demos/ │ │ └── waitforbutton/ │ │ ├── myassembly.txt │ │ └── myimages.txt │ └── makegame.py ├── codedump/ │ ├── GPTestProgram │ ├── README.txt │ ├── binbits │ ├── binbits2 │ ├── decode.py │ ├── first100.txt │ ├── in.txt │ ├── ports.txt │ └── tf/ │ ├── eeprom5cd/ │ │ └── eeprom5cd.ino │ └── glitch2/ │ └── glitch2.ino ├── demos/ │ ├── README │ ├── facemain.c │ ├── harlemshake │ ├── mad │ ├── nataliemain.c │ └── nsdemomain.c ├── devtools/ │ └── itemmake/ │ ├── README │ ├── itemmake.py │ ├── samplescript.txt │ └── template.txt ├── die/ │ └── README ├── disassembler/ │ ├── README │ ├── a.txt │ ├── bytecode.txt │ ├── bytecoden.txt │ ├── bytecoder.txt │ ├── bytecodes.txt │ └── dissa.py ├── figure/ │ ├── Arduino/ │ │ ├── ClientSide/ │ │ │ ├── README.txt │ │ │ ├── ser.py │ │ │ └── serw.py │ │ ├── GeneralPlusRomDump/ │ │ │ └── GeneralPlusRomDump.ino │ │ ├── GeneralPlusRomWrite/ │ │ │ └── GeneralPlusRomWrite.ino │ │ └── README.txt │ ├── README │ ├── ROMDump/ │ │ ├── README │ │ ├── ROMDump │ │ ├── imgs/ │ │ │ └── adds.txt │ │ ├── makiko │ │ └── shimashimatchi │ ├── SignalPulls/ │ │ ├── README │ │ ├── empire.txt │ │ ├── signaldecode.py │ │ ├── usatour.txt │ │ └── usatourbuy.txt │ └── scripts/ │ ├── README │ ├── im.py │ └── l.txt ├── figure-simulator/ │ ├── README │ └── simulator.pde ├── figure-simulator-discovery/ │ ├── .cproject │ ├── .project │ ├── .settings/ │ │ ├── com.atollic.truestudio.debug.hardware_device.prefs │ │ └── org.eclipse.cdt.managedbuilder.core.prefs │ ├── Libraries/ │ │ ├── CMSIS/ │ │ │ └── Include/ │ │ │ ├── arm_common_tables.h │ │ │ ├── arm_math.h │ │ │ ├── core_cm4.h │ │ │ ├── core_cm4_simd.h │ │ │ ├── core_cmFunc.h │ │ │ └── core_cmInstr.h │ │ ├── Device/ │ │ │ └── STM32F4xx/ │ │ │ ├── Include/ │ │ │ │ ├── stm32f4xx.h │ │ │ │ └── system_stm32f4xx.h │ │ │ └── Release_Notes.html │ │ └── STM32F4xx_StdPeriph_Driver/ │ │ ├── Release_Notes.html │ │ ├── inc/ │ │ │ ├── misc.h │ │ │ ├── stm32f4xx_adc.h │ │ │ ├── stm32f4xx_can.h │ │ │ ├── stm32f4xx_crc.h │ │ │ ├── stm32f4xx_cryp.h │ │ │ ├── stm32f4xx_dac.h │ │ │ ├── stm32f4xx_dbgmcu.h │ │ │ ├── stm32f4xx_dcmi.h │ │ │ ├── stm32f4xx_dma.h │ │ │ ├── stm32f4xx_exti.h │ │ │ ├── stm32f4xx_flash.h │ │ │ ├── stm32f4xx_fsmc.h │ │ │ ├── stm32f4xx_gpio.h │ │ │ ├── stm32f4xx_hash.h │ │ │ ├── stm32f4xx_i2c.h │ │ │ ├── stm32f4xx_iwdg.h │ │ │ ├── stm32f4xx_pwr.h │ │ │ ├── stm32f4xx_rcc.h │ │ │ ├── stm32f4xx_rng.h │ │ │ ├── stm32f4xx_rtc.h │ │ │ ├── stm32f4xx_sdio.h │ │ │ ├── stm32f4xx_spi.h │ │ │ ├── stm32f4xx_syscfg.h │ │ │ ├── stm32f4xx_tim.h │ │ │ ├── stm32f4xx_usart.h │ │ │ └── stm32f4xx_wwdg.h │ │ └── src/ │ │ ├── misc.c │ │ ├── stm32f4xx_adc.c │ │ ├── stm32f4xx_can.c │ │ ├── stm32f4xx_crc.c │ │ ├── stm32f4xx_cryp.c │ │ ├── stm32f4xx_cryp_aes.c │ │ ├── stm32f4xx_cryp_des.c │ │ ├── stm32f4xx_cryp_tdes.c │ │ ├── stm32f4xx_dac.c │ │ ├── stm32f4xx_dbgmcu.c │ │ ├── stm32f4xx_dcmi.c │ │ ├── stm32f4xx_dma.c │ │ ├── stm32f4xx_exti.c │ │ ├── stm32f4xx_flash.c │ │ ├── stm32f4xx_fsmc.c │ │ ├── stm32f4xx_gpio.c │ │ ├── stm32f4xx_hash.c │ │ ├── stm32f4xx_hash_md5.c │ │ ├── stm32f4xx_hash_sha1.c │ │ ├── stm32f4xx_i2c.c │ │ ├── stm32f4xx_iwdg.c │ │ ├── stm32f4xx_pwr.c │ │ ├── stm32f4xx_rcc.c │ │ ├── stm32f4xx_rng.c │ │ ├── stm32f4xx_rtc.c │ │ ├── stm32f4xx_sdio.c │ │ ├── stm32f4xx_spi.c │ │ ├── stm32f4xx_syscfg.c │ │ ├── stm32f4xx_tim.c │ │ ├── stm32f4xx_usart.c │ │ └── stm32f4xx_wwdg.c │ ├── README │ ├── Utilities/ │ │ └── STM32F4-Discovery/ │ │ ├── Release_Notes.html │ │ ├── libPDMFilter_GCC.a │ │ ├── pdm_filter.h │ │ ├── stm32f4_discovery.c │ │ ├── stm32f4_discovery.h │ │ ├── stm32f4_discovery_lis302dl.c │ │ └── stm32f4_discovery_lis302dl.h │ ├── spi.elf.launch │ ├── src/ │ │ ├── main.c │ │ ├── startup_stm32f4xx.s │ │ ├── stm32f4xx_conf.h │ │ ├── stm32f4xx_it.c │ │ ├── stm32f4xx_it.h │ │ ├── system_stm32f4xx.c │ │ └── tiny_printf.c │ └── stm32f4_flash.ld ├── imageformats/ │ ├── README │ ├── conv.py │ └── pic.txt └── slides/ └── recon.ppt ================================================ FILE CONTENTS ================================================ ================================================ FILE: IR/README.txt ================================================ IR.pde -- Arduino code for IR that sends the first request repeatedly, and waits for a listening Tamagotchi IR2.pde -- Arduino code for IR that waits for the first request, and responds (Tamagotchi intiates interaction) ================================================ FILE: IR/ir.pde ================================================ #define BIT_IS_SET(i, bits) (1 << i & bits) // LED connected to digital pin 13 const int LED_PIN = 13; // Width of a pulse, in microseconds const int PULSE_WIDTH = 2300; // # of bytes per command const int COMMAND_LENGTH = 4; //const int REQUEST[] = {0xac, 0, 0xde, 0xde, 2, 0xd, 5, 0x18, 0, 0, 0x14, 0x00, 0, 0, 0x10, 0, 2, 0, 0, 0xff, 1, 0xff, 0xff, 0x55}; //const int RC[] = {0xac, 0x1a, 0xdd, 0xdd, 1, 2, 0, 0x3d, 0}; int conf[9]; int r[24]; #include // choose the pin for the LED int inputPin = 2; // choose the input pin (for a pushbutton) int val = 0; // variable for reading the pin status int count; boolean done = false; void suck( int sig ){ while(digitalRead(inputPin) == sig){ } } int decodebuf( int* b){ int a = 0; for( int i = 0; i < 8; i++){ if( b[i] != 1 &&b[i] != 2 &&b[i] != 3){ Serial.println("I've fallen and i can't get up"); Serial.println(b[i]); } if( b[i] == 3) b[i] = 2; a = a + ((b[i] - 1) << i); } return a; } void getser(void){ //while(Serial.available()){ boolean gr = false; boolean gc = false; while(true){ if(!Serial.available()) continue; byte c = Serial.read(); //Serial.println(c); if( c == 'R' ){ for( int i = 0; i < 24; i++) { while(!Serial.available()); r[i] = Serial.read(); //Serial.println(Serial.read()); } gr = true; Serial.println("read request"); } if( c == 'C' ) { for( int i = 0; i < 9; i++) { //conf[i] = Serial.read(); while(!Serial.available()); conf[i] = Serial.read(); //Serial.println(Serial.read()); } Serial.println("read conf"); gc = true; } if (gr && gc) break; } //} } boolean dec(void){ // int i = 0; // getser(); int time; int diff, hi, lo; //char buf[9]; int buf[400]; int cycles = 0; int c; char obuf[12]; int i; //char out = 0xf0; // for(i = 0; i < 7; i ++ ) { time = millis(); while(digitalRead(inputPin) == HIGH ){ if( millis() - time > 5000){ return false; } } time = millis(); while(digitalRead(inputPin) == LOW){ } diff = millis() - time; time = millis(); if( diff > 8 && diff < 12){ //while(digitalRead(inputPin) == LOW ){ //} time = millis(); while(digitalRead(inputPin) == HIGH ){ } diff = millis() - time; if( diff < 0){ Serial.println("NEG"); } if( diff > 1 && diff < 6){ // Serial.println("HIT "); // Serial.println(diff); // Serial.println( diff); cycles = 0; i = 0; while(true){ // suck(HIGH); cycles++; time = micros(); suck(LOW); lo = micros() - time; time = micros(); if( lo > 1000){ // Serial.println("SMALL LO"); // Serial.println(lo); // Serial.println(cycles); //cycles = 0; break; } suck(HIGH); hi = micros() - time; time = micros(); buf[i] = hi/lo; i++; } Serial.println("DETECTED"); cycles = cycles/8; for( i = 0; i < cycles; i++){ c = decodebuf( buf + 8*i ); sprintf( obuf, "%x ", c); //for( i = 0; i < 16; i++){ Serial.print(obuf); } cycles = 0; return true; //} } } else{ } } void setup() { pinMode(LED_PIN, OUTPUT); Serial.begin(9600); // declare LED as output pinMode(inputPin, INPUT); // getser(); //size(400, 300); // set inital background: // background(0); } /* Modulate pin at 39 kHz for give number of microseconds */ void off(int pin, int time) { static const int period = 25; // found wait_time by measuring with oscilloscope // static const int wait_time = 12; for (time = time/period; time > 0; time--) { digitalWrite(pin, HIGH); delayMicroseconds(9); digitalWrite(pin, LOW); delayMicroseconds(9); } } /* Leave pin off for time (given in microseconds) */ void on(int pin, int time) { digitalWrite(pin, LOW); delayMicroseconds(time); } /* Send a byte over the IR LED */ void send_byte(int bits) { for (int i = 0; i < 8; i++) { if (BIT_IS_SET(i, bits)) { off(LED_PIN, 500); on(LED_PIN, 1270); } else { off(LED_PIN, 500); on(LED_PIN, 675); } } } /* Send a full command */ void command(const int bytes[], int len) { int sum = 0; for (int i = 0; i < len -1; i++) { send_byte(bytes[i]); sum = sum + bytes[i]; } send_byte(sum%256); off(LED_PIN, 1200); //check if not working on(LED_PIN, 0); } void loop() { if(!done){ getser(); done = true; } while (Serial.available() > 0) { Serial.write(Serial.read()); } while(!dec()){ off(LED_PIN, 9500); on(LED_PIN, 2500); command(r, 24); } do{ off(LED_PIN, 9500); on(LED_PIN, 2500); command(conf, 9); }while(!dec()); // delay(10000); // dec(); } ================================================ FILE: IR/ir2.pde ================================================ /* Control a Lutron Maestro light dimmer */ #define BIT_IS_SET(i, bits) (1 << i & bits) // LED connected to digital pin 13 const int LED_PIN = 13; // Width of a pulse, in microseconds const int PULSE_WIDTH = 2300; // # of bytes per command const int COMMAND_LENGTH = 4; volatile int REQUEST[] = {0xac, 1, 0x24, 0xd7, 0x0a, 1, 0x0e, 0x09, 0x05, 0x01, 0x03, 0x88, 0x00, 0x01, 0x33, 0xc0, 0x0b, 0, 0, 0xff, 1, 0xff, 0xff, 0x55}; volatile int RC[] = {0xac, 0x0b, 0x24, 0xd7, 0x00, 0x47, 0x0, 0x17, 0x5a }; int conf[9]; int r[24]; volatile int bounce = 0; #include // choose the pin for the LED int inputPin = 2; // choose the input pin (for a pushbutton) int val = 0; // variable for reading the pin status int count; volatile int b = 0x47; boolean done = false; void suck( int sig ){ while(digitalRead(inputPin) == sig){ } } int decodebuf( int* b){ int a = 0; for( int i = 0; i < 8; i++){ if( b[i] != 1 &&b[i] != 2 &&b[i] != 3){ Serial.println("I've fallen and i can't get up"); Serial.println(b[i]); } if( b[i] == 3) b[i] = 2; a = a + ((b[i] - 1) << i); } return a; } void getser(void){ //while(Serial.available()){ boolean gr = false; boolean gc = false; while(true){ if(!Serial.available()) continue; byte c = Serial.read(); //Serial.println(c); if( c == 'R' ){ for( int i = 0; i < 24; i++) { while(!Serial.available()); r[i] = Serial.read(); //Serial.println(Serial.read()); } gr = true; Serial.println("read request"); } if( c == 'C' ) { for( int i = 0; i < 9; i++) { //conf[i] = Serial.read(); while(!Serial.available()); conf[i] = Serial.read(); //Serial.println(Serial.read()); } Serial.println("read conf"); gc = true; } if (gr && gc) break; } //} } boolean dec(void){ // int i = 0; // getser(); int time; int diff, hi, lo; //char buf[9]; int buf[400]; int cycles = 0; int c; char obuf[12]; int i; //char out = 0xf0; // for(i = 0; i < 7; i ++ ) { time = millis(); while(digitalRead(inputPin) == HIGH ){ if( millis() - time > 5000){ return false; } } time = millis(); while(digitalRead(inputPin) == LOW){ } diff = millis() - time; time = millis(); if( diff > 8 && diff < 12){ //while(digitalRead(inputPin) == LOW ){ //} time = millis(); while(digitalRead(inputPin) == HIGH ){ } diff = millis() - time; if( diff < 0){ Serial.println("NEG"); } if( diff > 1 && diff < 6){ // Serial.println("HIT "); // Serial.println(diff); // Serial.println( diff); cycles = 0; i = 0; while(true){ // suck(HIGH); cycles++; time = micros(); suck(LOW); lo = micros() - time; time = micros(); if( lo > 1000){ // Serial.println("SMALL LO"); // Serial.println(lo); // Serial.println(cycles); //cycles = 0; break; } suck(HIGH); hi = micros() - time; time = micros(); buf[i] = hi/lo; i++; } Serial.println("DETECTED"); cycles = cycles/8; for( i = 0; i < cycles; i++){ c = decodebuf( buf + 8*i ); sprintf( obuf, "%x ", c); //for( i = 0; i < 16; i++){ Serial.print(obuf); } cycles = 0; return true; } } else{ return false; } } void setup() { pinMode(LED_PIN, OUTPUT); Serial.begin(9600); // declare LED as output pinMode(inputPin, INPUT); // pinMode(5, INPUT); // attachInterrupt(1, blink, FALLING); // getser(); //size(400, 300); // set inital background: // background(0); } /* Modulate pin at 39 kHz for give number of microseconds */ void off(int pin, int time) { static const int period = 25; // found wait_time by measuring with oscilloscope // static const int wait_time = 12; for (time = time/period; time > 0; time--) { digitalWrite(pin, HIGH); delayMicroseconds(9); digitalWrite(pin, LOW); delayMicroseconds(9); } } /* Leave pin off for time (given in microseconds) */ void on(int pin, int time) { digitalWrite(pin, LOW); delayMicroseconds(time); } /* Send a byte over the IR LED */ void send_byte(int bits) { for (int i = 0; i < 8; i++) { if (BIT_IS_SET(i, bits)) { off(LED_PIN, 500); on(LED_PIN, 1270); } else { off(LED_PIN, 500); on(LED_PIN, 675); } } } /* Send a full command */ void command(volatile int bytes[], int len) { int sum = 0; for (int i = 0; i < len -1; i++) { send_byte(bytes[i]); sum = sum + bytes[i]; } send_byte(sum%256); off(LED_PIN, 1200); //check if not working on(LED_PIN, 0); } void loop() { /*if(!done){ getser(); done = true; } */ while(!dec()){} //if( digitalRead( 5 ) == HIGH) do{ off(LED_PIN, 9500); on(LED_PIN, 2500); command(REQUEST, 24); }while(!dec()); do{ off(LED_PIN, 9500); on(LED_PIN, 2500); command(RC, 9); }while(!dec()); // delay(10000); // dec(); } // Serial.println("yes, i do enjoy being interrupted" ); ================================================ FILE: README ================================================ Repository for Tamagotchi hacking code! Directories: /demos/ - Discovery board demos /devtools/ - Tamagotchi development tools /die/ - Photos of the Tamagotchi chip/die /dissasembler/ - GeneralPlus binary dissasembler /figure/ - Dumps and code from Tamagotchi figures /figure-simulator/ - Chipkit Uno figure simulator /figure-simulator-discovery/ - STM32F4 Discovery board figure simulator /imageformats/ - Tamagotchi image format converters /IR/ - IR code Questions? Comments? Contributions? Contact: natashenka@kwartzlab.ca / @natashenka ================================================ FILE: RFIDler/tama.py ================================================ import RFIDler import sys import time packet1 = [0xf0, 0, 0x0f, 1, 0, 0x2e, 0x25, 0, 2 , 0x80, 2, 0x7, 8, 0x01, 0x8, 0x1a, 0x1a, 0x1a] packet2 = [0xf0, int(sys.argv[2]), 5, 1, int(sys.argv[2]), 0x2e, 0x25, 0x1] def send_byte(b): i = 0; result, data= rfidler.command("CLOCKH 125000") time.sleep(0.540/1000); result, data= rfidler.command("STOP") i = 7 #print "send" while(i>=0): if (1): result, data= rfidler.command("STOP") time.sleep(1.650/1000); result, data= rfidler.command("CLOCKH 125000") time.sleep(0.150/1000); else: result, data= rfidler.command("STOP") time.sleep(0.270/1000); result, data= rfidler.command("CLOCKH 125000") time.sleep(0.150/1000); i = i - 1 result, data= rfidler.command("STOP"); time.sleep(0.210/1000); def toBinary(n): # print n # print ''.join(str(1 & int(n) >> i) for i in range(8)[::-1]) return ''.join(str(1 & int(n) >> i) for i in range(8)[::-1]) port= sys.argv[1] rfidler= RFIDler.RFIDler() result, reason= rfidler.connect(port) if not result: print 'Warning - could not open serial port:', reason for i in range(6, 7): s = "" n = 0 first = False for item in packet1: if (first==False): first = True else: n = n + item s = s + toBinary(item) s = s + toBinary(n&0xff) result, data= rfidler.command("PWM2 800 0 0 19 19 10 0 0 1 100 20 1 75 20"); time.sleep(.1) result, data= rfidler.command("RWD2 " + s); print len(s) s = "" n = 0 first = False packet2[1] = i packet2[4] = i for item in packet2: if (first==False): first = True else: n = n + item s = s + toBinary(item) s = s + toBinary(n&0xff) print len(s) print result print data time.sleep(0.1) result, data= rfidler.command("RWD2 " + s); print result print data time.sleep(2) print i ================================================ FILE: TamagotchiFriends/proxmark/armsrc/LCD.c ================================================ //----------------------------------------------------------------------------- // This code is licensed to you under the terms of the GNU GPL, version 2 or, // at your option, any later version. See the LICENSE.txt file for the text of // the license. //----------------------------------------------------------------------------- // LCD code //----------------------------------------------------------------------------- #include "proxmark3.h" #include "apps.h" #include "LCD.h" #include "fonts.h" void LCDSend(unsigned int data) { // 9th bit set for data, clear for command while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TXEMPTY) == 0); // wait for the transfer to complete // For clarity's sake we pass data with 9th bit clear and commands with 9th // bit set since they're implemented as defines, se we need to invert bit AT91C_BASE_SPI->SPI_TDR = data^0x100; // Send the data/command } void LCDSetXY(unsigned char x, unsigned char y) { LCDSend(PPASET); // page start/end ram LCDSend(y); // Start Page to display to LCDSend(131); // End Page to display to LCDSend(PCASET); // column start/end ram LCDSend(x); // Start Column to display to LCDSend(131); // End Column to display to } void LCDSetPixel(unsigned char x, unsigned char y, unsigned char color) { LCDSetXY(x,y); // Set position LCDSend(PRAMWR); // Now write the pixel to the display LCDSend(color); // Write the data in the specified Color } void LCDFill (unsigned char xs,unsigned char ys,unsigned char width,unsigned char height, unsigned char color) { unsigned char i,j; for (i=0;i < height;i++) // Number of horizontal lines { LCDSetXY(xs,ys+i); // Goto start of fill area (Top Left) LCDSend(PRAMWR); // Write to display for (j=0;j < width;j++) // pixels per line LCDSend(color); } } void LCDString (char *lcd_string, const char *font_style,unsigned char x, unsigned char y, unsigned char fcolor, unsigned char bcolor) { unsigned int i; unsigned char mask=0, px, py, xme, yme, offset; const char *data; data = font_style; // point to the start of the font table xme = *data; // get font x width data++; yme = *data; // get font y length data++; offset = *data; // get data bytes per font do { // point to data in table to be loaded data = (font_style + offset) + (offset * (int)(*lcd_string - 32)); for (i=0;i < yme;i++) { mask |=0x80; for (px=x; px < (x + xme); px++) { py= y + i; if (*data & mask) LCDSetPixel (px,py,fcolor); else LCDSetPixel (px,py,bcolor); mask>>=1; } data++; } x+=xme; lcd_string++; // next character in string } while(*lcd_string !='\0'); // keep spitting chars out until end of string } void LCDReset(void) { LED_A_ON(); SetupSpi(SPI_LCD_MODE); LOW(GPIO_LRST); SpinDelay(100); HIGH(GPIO_LRST); SpinDelay(100); LED_A_OFF(); } void LCDInit(void) { int i; LCDReset(); LCDSend(PSWRESET); // software reset SpinDelay(100); LCDSend(PSLEEPOUT); // exit sleep mode LCDSend(PBSTRON); // booster on LCDSend(PDISPON); // display on LCDSend(PNORON); // normal on LCDSend(PMADCTL); // rotate display 180 deg LCDSend(0xC0); LCDSend(PCOLMOD); // color mode LCDSend(0x02); // 8bpp color mode LCDSend(PSETCON); // set contrast LCDSend(0xDC); // clear display LCDSetXY(0,0); LCDSend(PRAMWR); // Write to display i=LCD_XRES*LCD_YRES; while(i--) LCDSend(WHITE); // test text on different colored backgrounds LCDString(" The quick brown fox ", (char *)&FONT6x8,1,1+8*0,WHITE ,BLACK ); LCDString(" jumped over the ", (char *)&FONT6x8,1,1+8*1,BLACK ,WHITE ); LCDString(" lazy dog. ", (char *)&FONT6x8,1,1+8*2,YELLOW ,RED ); LCDString(" AaBbCcDdEeFfGgHhIiJj ", (char *)&FONT6x8,1,1+8*3,RED ,GREEN ); LCDString(" KkLlMmNnOoPpQqRrSsTt ", (char *)&FONT6x8,1,1+8*4,MAGENTA,BLUE ); LCDString("UuVvWwXxYyZz0123456789", (char *)&FONT6x8,1,1+8*5,BLUE ,YELLOW); LCDString("`-=[]_;',./~!@#$%^&*()", (char *)&FONT6x8,1,1+8*6,BLACK ,CYAN ); LCDString(" _+{}|:\\\"<>? ",(char *)&FONT6x8,1,1+8*7,BLUE ,MAGENTA); // color bands LCDFill(0, 1+8* 8, 132, 8, BLACK); LCDFill(0, 1+8* 9, 132, 8, WHITE); LCDFill(0, 1+8*10, 132, 8, RED); LCDFill(0, 1+8*11, 132, 8, GREEN); LCDFill(0, 1+8*12, 132, 8, BLUE); LCDFill(0, 1+8*13, 132, 8, YELLOW); LCDFill(0, 1+8*14, 132, 8, CYAN); LCDFill(0, 1+8*15, 132, 8, MAGENTA); } ================================================ FILE: TamagotchiFriends/proxmark/armsrc/LCD.h ================================================ //----------------------------------------------------------------------------- // This code is licensed to you under the terms of the GNU GPL, version 2 or, // at your option, any later version. See the LICENSE.txt file for the text of // the license. //----------------------------------------------------------------------------- // LCD code //----------------------------------------------------------------------------- #ifndef __LCD_H #define __LCD_H // The resolution of the LCD #define LCD_XRES 132 #define LCD_YRES 132 // 8bpp Color Mode - Some basic colors defined for ease of use // remember 8bpp color = 3xRed, 3xGreen & 2xBlue bits // organised as RRRGGGBB #define BLACK 0x00 #define BLUE 0x03 #define GREEN 0x1C #define CYAN 0x1F #define RED 0xE0 #define MAGENTA 0xE3 #define YELLOW 0xFC #define WHITE 0xFF // EPSON LCD command set #define ECASET 0x115 #define EPWRCTR 0x120 #define ENOP 0x125 #define ERAMWR 0x15C #define ERAMRD 0x15D #define EPASET 0x175 #define EEPSRRD1 0x17C #define EEPSRRD2 0x17D #define EVOLCTR 0x181 #define ETMPGRD 0x182 #define ESLPOUT 0x194 #define ESLPIN 0x195 #define EDISNOR 0x1A6 #define EDISINV 0x1A7 #define EPTLIN 0x1A8 #define EPTLOUT 0x1A9 #define EASCSET 0x1AA #define ESCSTART 0x1AB #define EDISOFF 0x1AE #define EDISON 0x1AF #define ECOMSCN 0x1BB #define EDATCTL 0x1BC #define EDISCTL 0x1CA #define EEPCOUT 0x1CC #define EEPCTIN 0x1CD #define ERGBSET8 0x1CE #define EOSCON 0x1D1 #define EOSCOFF 0x1D2 #define EVOLUP 0x1D6 #define EVOLDOWN 0x1D7 #define ERMWIN 0x1E0 #define ERMWOUT 0x1EE #define EEPMWR 0x1FC #define EEPMRD 0x1FD // PHILIPS LCD command set #define PNOP 0x100 #define PSWRESET 0x101 #define PBSTROFF 0x102 #define PBSTRON 0x103 #define PRDDIDIF 0x104 #define PRDDST 0x109 #define PSLEEPIN 0x110 #define PSLEEPOUT 0x111 #define PPTLON 0x112 #define PNORON 0x113 #define PINVOFF 0x120 #define PINVON 0x121 #define PDALO 0x122 #define PDAL 0x123 #define PSETCON 0x125 #define PDISPOFF 0x128 #define PDISPON 0x129 #define PCASET 0x12A #define PPASET 0x12B #define PRAMWR 0x12C #define PRGBSET 0x12D #define PPTLAR 0x130 #define PVSCRDEF 0x133 #define PTEOFF 0x134 #define PTEON 0x135 #define PMADCTL 0x136 #define PSEP 0x137 #define PIDMOFF 0x138 #define PIDMON 0x139 #define PCOLMOD 0x13A #define PSETVOP 0x1B0 #define PBRS 0x1B4 #define PTRS 0x1B6 #define PFINV 0x1B9 #define PDOR 0x1BA #define PTCDFE 0x1BD #define PTCVOPE 0x1BF #define PEC 0x1C0 #define PSETMUL 0x1C2 #define PTCVOPAB 0x1C3 #define PTCVOPCD 0x1C4 #define PTCDF 0x1C5 #define PDF8C 0x1C6 #define PSETBS 0x1C7 #define PRDTEMP 0x1C8 #define PNLI 0x1C9 #define PRDID1 0x1DA #define PRDID2 0x1DB #define PRDID3 0x1DC #define PSFD 0x1EF #define PECM 0x1F0 void LCDSend(unsigned int data); void LCDInit(void); void LCDReset(void); void LCDSetXY(unsigned char x, unsigned char y); void LCDSetPixel(unsigned char x, unsigned char y, unsigned char color); void LCDString (char *lcd_string, const char *font_style,unsigned char x, unsigned char y, unsigned char fcolor, unsigned char bcolor); void LCDFill (unsigned char xs,unsigned char ys,unsigned char width,unsigned char height, unsigned char color); #endif ================================================ FILE: TamagotchiFriends/proxmark/armsrc/Makefile ================================================ #----------------------------------------------------------------------------- # This code is licensed to you under the terms of the GNU GPL, version 2 or, # at your option, any later version. See the LICENSE.txt file for the text of # the license. #----------------------------------------------------------------------------- # Makefile for armsrc, see ../common/Makefile.common for common settings #----------------------------------------------------------------------------- APP_INCLUDES = apps.h #remove one of the following defines and comment out the relevant line #in the next section to remove that particular feature from compilation APP_CFLAGS = -DWITH_LF -DWITH_ISO15693 -DWITH_ISO14443a -DWITH_ISO14443b -DWITH_ICLASS -DWITH_LEGICRF -DWITH_HITAG #-DWITH_LCD #SRC_LCD = fonts.c LCD.c SRC_LF = lfops.c hitag2.c SRC_ISO15693 = iso15693.c iso15693tools.c SRC_ISO14443a = epa.c iso14443a.c mifareutil.c mifarecmd.c mifaresniff.c SRC_ISO14443b = iso14443.c SRC_CRAPTO1 = crapto1.c crypto1.c THUMBSRC = start.c \ $(SRC_LCD) \ $(SRC_ISO15693) \ $(SRC_LF) \ appmain.c printf.c \ util.c \ string.c \ usb_cdc.c \ cmd.c # These are to be compiled in ARM mode ARMSRC = fpgaloader.c \ legicrf.c \ iso14443crc.c \ crc16.c \ $(SRC_ISO14443a) \ $(SRC_ISO14443b) \ $(SRC_CRAPTO1) \ legic_prng.c \ iclass.c \ crc.c # stdint.h provided locally until GCC 4.5 becomes C99 compliant APP_CFLAGS += -I. # Do not move this inclusion before the definition of {THUMB,ASM,ARM}SRC include ../common/Makefile.common OBJS = $(OBJDIR)/osimage.s19 $(OBJDIR)/fpgaimage.s19 all: $(OBJS) $(OBJDIR)/fpga.o: fpga.bit $(OBJCOPY) -O elf32-littlearm -I binary -B arm --redefine-sym _binary____fpga_fpga_bit_start=_binary_fpga_bit_start --redefine-sym _binary____fpga_fpga_bit_end=_binary_fpga_bit_end --prefix-sections=fpga_bit $^ $@ $(OBJDIR)/fullimage.elf: $(VERSIONOBJ) $(OBJDIR)/fpga.o $(THUMBOBJ) $(ARMOBJ) $(CC) $(LDFLAGS) -Wl,-T,ldscript,-Map,$(patsubst %.elf,%.map,$@) -o $@ $^ $(LIBS) $(OBJDIR)/fpgaimage.elf: $(OBJDIR)/fullimage.elf $(OBJCOPY) -F elf32-littlearm --only-section .fpgaimage $^ $@ $(OBJDIR)/osimage.elf: $(OBJDIR)/fullimage.elf $(OBJCOPY) -F elf32-littlearm --remove-section .fpgaimage $^ $@ tarbin: $(OBJS) $(TAR) $(TARFLAGS) ../proxmark3-$(platform)-bin.tar $(OBJS:%=armsrc/%) $(OBJS:%.s19=armsrc/%.elf) clean: $(DELETE) $(OBJDIR)$(PATHSEP)*.o $(DELETE) $(OBJDIR)$(PATHSEP)*.elf $(DELETE) $(OBJDIR)$(PATHSEP)*.s19 $(DELETE) $(OBJDIR)$(PATHSEP)*.map $(DELETE) $(OBJDIR)$(PATHSEP)*.d $(DELETE) version.c .PHONY: all clean help help: @echo Multi-OS Makefile, you are running on $(DETECTED_OS) @echo Possible targets: @echo + all - Make both: @echo + $(OBJDIR)/osimage.s19 - The OS image @echo + $(OBJDIR)/fpgaimage.s19 - The FPGA image @echo + clean - Clean $(OBJDIR) ================================================ FILE: TamagotchiFriends/proxmark/armsrc/appmain.c ================================================ //----------------------------------------------------------------------------- // Jonathan Westhues, Mar 2006 // Edits by Gerhard de Koning Gans, Sep 2007 (##) // // This code is licensed to you under the terms of the GNU GPL, version 2 or, // at your option, any later version. See the LICENSE.txt file for the text of // the license. //----------------------------------------------------------------------------- // The main application code. This is the first thing called after start.c // executes. //----------------------------------------------------------------------------- #include "usb_cdc.h" #include "cmd.h" #include "proxmark3.h" #include "apps.h" #include "util.h" #include "printf.h" #include "string.h" #include #include "legicrf.h" #include #ifdef WITH_LCD #include "LCD.h" #endif #define abs(x) ( ((x)<0) ? -(x) : (x) ) //============================================================================= // A buffer where we can queue things up to be sent through the FPGA, for // any purpose (fake tag, as reader, whatever). We go MSB first, since that // is the order in which they go out on the wire. //============================================================================= uint8_t ToSend[512]; int ToSendMax; static int ToSendBit; struct common_area common_area __attribute__((section(".commonarea"))); void BufferClear(void) { memset(BigBuf,0,sizeof(BigBuf)); Dbprintf("Buffer cleared (%i bytes)",sizeof(BigBuf)); } void ToSendReset(void) { ToSendMax = -1; ToSendBit = 8; } void ToSendStuffBit(int b) { if(ToSendBit >= 8) { ToSendMax++; ToSend[ToSendMax] = 0; ToSendBit = 0; } if(b) { ToSend[ToSendMax] |= (1 << (7 - ToSendBit)); } ToSendBit++; if(ToSendBit >= sizeof(ToSend)) { ToSendBit = 0; DbpString("ToSendStuffBit overflowed!"); } } //============================================================================= // Debug print functions, to go out over USB, to the usual PC-side client. //============================================================================= void DbpString(char *str) { byte_t len = strlen(str); cmd_send(CMD_DEBUG_PRINT_STRING,len,0,0,(byte_t*)str,len); // /* this holds up stuff unless we're connected to usb */ // if (!UsbConnected()) // return; // // UsbCommand c; // c.cmd = CMD_DEBUG_PRINT_STRING; // c.arg[0] = strlen(str); // if(c.arg[0] > sizeof(c.d.asBytes)) { // c.arg[0] = sizeof(c.d.asBytes); // } // memcpy(c.d.asBytes, str, c.arg[0]); // // UsbSendPacket((uint8_t *)&c, sizeof(c)); // // TODO fix USB so stupid things like this aren't req'd // SpinDelay(50); } #if 0 void DbpIntegers(int x1, int x2, int x3) { cmd_send(CMD_DEBUG_PRINT_INTEGERS,x1,x2,x3,0,0); // /* this holds up stuff unless we're connected to usb */ // if (!UsbConnected()) // return; // // UsbCommand c; // c.cmd = CMD_DEBUG_PRINT_INTEGERS; // c.arg[0] = x1; // c.arg[1] = x2; // c.arg[2] = x3; // // UsbSendPacket((uint8_t *)&c, sizeof(c)); // // XXX // SpinDelay(50); } #endif void Dbprintf(const char *fmt, ...) { // should probably limit size here; oh well, let's just use a big buffer char output_string[128]; va_list ap; va_start(ap, fmt); kvsprintf(fmt, output_string, 10, ap); va_end(ap); DbpString(output_string); } // prints HEX & ASCII void Dbhexdump(int len, uint8_t *d, bool bAsci) { int l=0,i; char ascii[9]; while (len>0) { if (len>8) l=8; else l=len; memcpy(ascii,d,l); ascii[l]=0; // filter safe ascii for (i=0;i126) ascii[i]='.'; if (bAsci) { Dbprintf("%-8s %*D",ascii,l,d," "); } else { Dbprintf("%*D",l,d," "); } len-=8; d+=8; } } //----------------------------------------------------------------------------- // Read an ADC channel and block till it completes, then return the result // in ADC units (0 to 1023). Also a routine to average 32 samples and // return that. //----------------------------------------------------------------------------- static int ReadAdc(int ch) { uint32_t d; AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST; AT91C_BASE_ADC->ADC_MR = ADC_MODE_PRESCALE(32) | ADC_MODE_STARTUP_TIME(16) | ADC_MODE_SAMPLE_HOLD_TIME(8); AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ch); AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START; while(!(AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ch))) ; d = AT91C_BASE_ADC->ADC_CDR[ch]; return d; } int AvgAdc(int ch) // was static - merlok { int i; int a = 0; for(i = 0; i < 32; i++) { a += ReadAdc(ch); } return (a + 15) >> 5; } void MeasureAntennaTuning(void) { uint8_t *dest = (uint8_t *)BigBuf+FREE_BUFFER_OFFSET; int i, adcval = 0, peak = 0, peakv = 0, peakf = 0; //ptr = 0 int vLf125 = 0, vLf134 = 0, vHf = 0; // in mV // UsbCommand c; LED_B_ON(); DbpString("Measuring antenna characteristics, please wait..."); memset(dest,0,sizeof(FREE_BUFFER_SIZE)); /* * Sweeps the useful LF range of the proxmark from * 46.8kHz (divisor=255) to 600kHz (divisor=19) and * read the voltage in the antenna, the result left * in the buffer is a graph which should clearly show * the resonating frequency of your LF antenna * ( hopefully around 95 if it is tuned to 125kHz!) */ FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); for (i=255; i>19; i--) { WDT_HIT(); FpgaSendCommand(FPGA_CMD_SET_DIVISOR, i); SpinDelay(20); // Vref = 3.3V, and a 10000:240 voltage divider on the input // can measure voltages up to 137500 mV adcval = ((137500 * AvgAdc(ADC_CHAN_LF)) >> 10); if (i==95) vLf125 = adcval; // voltage at 125Khz if (i==89) vLf134 = adcval; // voltage at 134Khz dest[i] = adcval>>8; // scale int to fit in byte for graphing purposes if(dest[i] > peak) { peakv = adcval; peak = dest[i]; peakf = i; //ptr = i; } } LED_A_ON(); // Let the FPGA drive the high-frequency antenna around 13.56 MHz. FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR); SpinDelay(20); // Vref = 3300mV, and an 10:1 voltage divider on the input // can measure voltages up to 33000 mV vHf = (33000 * AvgAdc(ADC_CHAN_HF)) >> 10; // c.cmd = CMD_MEASURED_ANTENNA_TUNING; // c.arg[0] = (vLf125 << 0) | (vLf134 << 16); // c.arg[1] = vHf; // c.arg[2] = peakf | (peakv << 16); DbpString("Measuring complete, sending report back to host"); cmd_send(CMD_MEASURED_ANTENNA_TUNING,vLf125|(vLf134<<16),vHf,peakf|(peakv<<16),0,0); // UsbSendPacket((uint8_t *)&c, sizeof(c)); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); LED_A_OFF(); LED_B_OFF(); return; } void MeasureAntennaTuningHf(void) { int vHf = 0; // in mV DbpString("Measuring HF antenna, press button to exit"); for (;;) { // Let the FPGA drive the high-frequency antenna around 13.56 MHz. FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR); SpinDelay(20); // Vref = 3300mV, and an 10:1 voltage divider on the input // can measure voltages up to 33000 mV vHf = (33000 * AvgAdc(ADC_CHAN_HF)) >> 10; Dbprintf("%d mV",vHf); if (BUTTON_PRESS()) break; } DbpString("cancelled"); } void SimulateTagHfListen(void) { uint8_t *dest = (uint8_t *)BigBuf+FREE_BUFFER_OFFSET; uint8_t v = 0; int i; int p = 0; // We're using this mode just so that I can test it out; the simulated // tag mode would work just as well and be simpler. FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ | FPGA_HF_READER_RX_XCORR_SNOOP); // We need to listen to the high-frequency, peak-detected path. SetAdcMuxFor(GPIO_MUXSEL_HIPKD); FpgaSetupSsc(); i = 0; for(;;) { if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { AT91C_BASE_SSC->SSC_THR = 0xff; } if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { uint8_t r = (uint8_t)AT91C_BASE_SSC->SSC_RHR; v <<= 1; if(r & 1) { v |= 1; } p++; if(p >= 8) { dest[i] = v; v = 0; p = 0; i++; if(i >= FREE_BUFFER_SIZE) { break; } } } } DbpString("simulate tag (now type bitsamples)"); } void ReadMem(int addr) { const uint8_t *data = ((uint8_t *)addr); Dbprintf("%x: %02x %02x %02x %02x %02x %02x %02x %02x", addr, data[0], data[1], data[2], data[3], data[4], data[5], data[6], data[7]); } /* osimage version information is linked in */ extern struct version_information version_information; /* bootrom version information is pointed to from _bootphase1_version_pointer */ extern char *_bootphase1_version_pointer, _flash_start, _flash_end; void SendVersion(void) { char temp[48]; /* Limited data payload in USB packets */ DbpString("Prox/RFID mark3 RFID instrument"); /* Try to find the bootrom version information. Expect to find a pointer at * symbol _bootphase1_version_pointer, perform slight sanity checks on the * pointer, then use it. */ char *bootrom_version = *(char**)&_bootphase1_version_pointer; if( bootrom_version < &_flash_start || bootrom_version >= &_flash_end ) { DbpString("bootrom version information appears invalid"); } else { FormatVersionInformation(temp, sizeof(temp), "bootrom: ", bootrom_version); DbpString(temp); } FormatVersionInformation(temp, sizeof(temp), "os: ", &version_information); DbpString(temp); FpgaGatherVersion(temp, sizeof(temp)); DbpString(temp); } #ifdef WITH_LF // samy's sniff and repeat routine void SamyRun() { DbpString("Stand-alone mode! No PC necessary."); // 3 possible options? no just 2 for now #define OPTS 2 int high[OPTS], low[OPTS]; // Oooh pretty -- notify user we're in elite samy mode now LED(LED_RED, 200); LED(LED_ORANGE, 200); LED(LED_GREEN, 200); LED(LED_ORANGE, 200); LED(LED_RED, 200); LED(LED_ORANGE, 200); LED(LED_GREEN, 200); LED(LED_ORANGE, 200); LED(LED_RED, 200); int selected = 0; int playing = 0; // Turn on selected LED LED(selected + 1, 0); for (;;) { // UsbPoll(FALSE); usb_poll(); WDT_HIT(); // Was our button held down or pressed? int button_pressed = BUTTON_HELD(1000); SpinDelay(300); // Button was held for a second, begin recording if (button_pressed > 0) { LEDsoff(); LED(selected + 1, 0); LED(LED_RED2, 0); // record DbpString("Starting recording"); // wait for button to be released while(BUTTON_PRESS()) WDT_HIT(); /* need this delay to prevent catching some weird data */ SpinDelay(500); CmdHIDdemodFSK(1, &high[selected], &low[selected], 0); Dbprintf("Recorded %x %x %x", selected, high[selected], low[selected]); LEDsoff(); LED(selected + 1, 0); // Finished recording // If we were previously playing, set playing off // so next button push begins playing what we recorded playing = 0; } // Change where to record (or begin playing) else if (button_pressed) { // Next option if we were previously playing if (playing) selected = (selected + 1) % OPTS; playing = !playing; LEDsoff(); LED(selected + 1, 0); // Begin transmitting if (playing) { LED(LED_GREEN, 0); DbpString("Playing"); // wait for button to be released while(BUTTON_PRESS()) WDT_HIT(); Dbprintf("%x %x %x", selected, high[selected], low[selected]); CmdHIDsimTAG(high[selected], low[selected], 0); DbpString("Done playing"); if (BUTTON_HELD(1000) > 0) { DbpString("Exiting"); LEDsoff(); return; } /* We pressed a button so ignore it here with a delay */ SpinDelay(300); // when done, we're done playing, move to next option selected = (selected + 1) % OPTS; playing = !playing; LEDsoff(); LED(selected + 1, 0); } else while(BUTTON_PRESS()) WDT_HIT(); } } } #endif /* OBJECTIVE Listen and detect an external reader. Determine the best location for the antenna. INSTRUCTIONS: Inside the ListenReaderField() function, there is two mode. By default, when you call the function, you will enter mode 1. If you press the PM3 button one time, you will enter mode 2. If you press the PM3 button a second time, you will exit the function. DESCRIPTION OF MODE 1: This mode just listens for an external reader field and lights up green for HF and/or red for LF. This is the original mode of the detectreader function. DESCRIPTION OF MODE 2: This mode will visually represent, using the LEDs, the actual strength of the current compared to the maximum current detected. Basically, once you know what kind of external reader is present, it will help you spot the best location to place your antenna. You will probably not get some good results if there is a LF and a HF reader at the same place! :-) LIGHT SCHEME USED: */ static const char LIGHT_SCHEME[] = { 0x0, /* ---- | No field detected */ 0x1, /* X--- | 14% of maximum current detected */ 0x2, /* -X-- | 29% of maximum current detected */ 0x4, /* --X- | 43% of maximum current detected */ 0x8, /* ---X | 57% of maximum current detected */ 0xC, /* --XX | 71% of maximum current detected */ 0xE, /* -XXX | 86% of maximum current detected */ 0xF, /* XXXX | 100% of maximum current detected */ }; static const int LIGHT_LEN = sizeof(LIGHT_SCHEME)/sizeof(LIGHT_SCHEME[0]); void ListenReaderField(int limit) { int lf_av, lf_av_new, lf_baseline= 0, lf_count= 0, lf_max; int hf_av, hf_av_new, hf_baseline= 0, hf_count= 0, hf_max; int mode=1, display_val, display_max, i; #define LF_ONLY 1 #define HF_ONLY 2 LEDsoff(); lf_av=lf_max=ReadAdc(ADC_CHAN_LF); if(limit != HF_ONLY) { Dbprintf("LF 125/134 Baseline: %d", lf_av); lf_baseline = lf_av; } hf_av=hf_max=ReadAdc(ADC_CHAN_HF); if (limit != LF_ONLY) { Dbprintf("HF 13.56 Baseline: %d", hf_av); hf_baseline = hf_av; } for(;;) { if (BUTTON_PRESS()) { SpinDelay(500); switch (mode) { case 1: mode=2; DbpString("Signal Strength Mode"); break; case 2: default: DbpString("Stopped"); LEDsoff(); return; break; } } WDT_HIT(); if (limit != HF_ONLY) { if(mode==1) { if (abs(lf_av - lf_baseline) > 10) LED_D_ON(); else LED_D_OFF(); } ++lf_count; lf_av_new= ReadAdc(ADC_CHAN_LF); // see if there's a significant change if(abs(lf_av - lf_av_new) > 10) { Dbprintf("LF 125/134 Field Change: %x %x %x", lf_av, lf_av_new, lf_count); lf_av = lf_av_new; if (lf_av > lf_max) lf_max = lf_av; lf_count= 0; } } if (limit != LF_ONLY) { if (mode == 1){ if (abs(hf_av - hf_baseline) > 10) LED_B_ON(); else LED_B_OFF(); } ++hf_count; hf_av_new= ReadAdc(ADC_CHAN_HF); // see if there's a significant change if(abs(hf_av - hf_av_new) > 10) { Dbprintf("HF 13.56 Field Change: %x %x %x", hf_av, hf_av_new, hf_count); hf_av = hf_av_new; if (hf_av > hf_max) hf_max = hf_av; hf_count= 0; } } if(mode == 2) { if (limit == LF_ONLY) { display_val = lf_av; display_max = lf_max; } else if (limit == HF_ONLY) { display_val = hf_av; display_max = hf_max; } else { /* Pick one at random */ if( (hf_max - hf_baseline) > (lf_max - lf_baseline) ) { display_val = hf_av; display_max = hf_max; } else { display_val = lf_av; display_max = lf_max; } } for (i=0; i= ((display_max/LIGHT_LEN)*i) && display_val <= ((display_max/LIGHT_LEN)*(i+1))) { if (LIGHT_SCHEME[i] & 0x1) LED_C_ON(); else LED_C_OFF(); if (LIGHT_SCHEME[i] & 0x2) LED_A_ON(); else LED_A_OFF(); if (LIGHT_SCHEME[i] & 0x4) LED_B_ON(); else LED_B_OFF(); if (LIGHT_SCHEME[i] & 0x8) LED_D_ON(); else LED_D_OFF(); break; } } } } } void UsbPacketReceived(uint8_t *packet, int len) { UsbCommand *c = (UsbCommand *)packet; // Dbprintf("received %d bytes, with command: 0x%04x and args: %d %d %d",len,c->cmd,c->arg[0],c->arg[1],c->arg[2]); switch(c->cmd) { #ifdef WITH_LF case CMD_ACQUIRE_RAW_ADC_SAMPLES_125K: AcquireRawAdcSamples125k(c->arg[0]); cmd_send(CMD_ACK,0,0,0,0,0); break; case CMD_MOD_THEN_ACQUIRE_RAW_ADC_SAMPLES_125K: ModThenAcquireRawAdcSamples125k(c->arg[0],c->arg[1],c->arg[2],c->d.asBytes); break; case CMD_HID_DEMOD_FSK: CmdHIDdemodFSK(0, 0, 0, 1); // Demodulate HID tag break; case CMD_HID_SIM_TAG: CmdHIDsimTAG(c->arg[0], c->arg[1], 1); // Simulate HID tag by ID break; case CMD_HID_CLONE_TAG: // Clone HID tag by ID to T55x7 CopyHIDtoT55x7(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes[0]); break; case CMD_EM410X_WRITE_TAG: WriteEM410x(c->arg[0], c->arg[1], c->arg[2]); break; case CMD_READ_TI_TYPE: ReadTItag(); break; case CMD_WRITE_TI_TYPE: WriteTItag(c->arg[0],c->arg[1],c->arg[2]); break; case CMD_SIMULATE_TAG_125K: LED_A_ON(); SimulateTagLowFrequency(c->arg[0], c->arg[1], 1); LED_A_OFF(); break; case CMD_LF_SIMULATE_BIDIR: SimulateTagLowFrequencyBidir(c->arg[0], c->arg[1]); break; case CMD_INDALA_CLONE_TAG: // Clone Indala 64-bit tag by UID to T55x7 CopyIndala64toT55x7(c->arg[0], c->arg[1]); break; case CMD_INDALA_CLONE_TAG_L: // Clone Indala 224-bit tag by UID to T55x7 CopyIndala224toT55x7(c->d.asDwords[0], c->d.asDwords[1], c->d.asDwords[2], c->d.asDwords[3], c->d.asDwords[4], c->d.asDwords[5], c->d.asDwords[6]); break; case CMD_T55XX_READ_BLOCK: T55xxReadBlock(c->arg[1], c->arg[2],c->d.asBytes[0]); break; case CMD_T55XX_WRITE_BLOCK: T55xxWriteBlock(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes[0]); break; case CMD_T55XX_READ_TRACE: // Clone HID tag by ID to T55x7 T55xxReadTrace(); break; case CMD_PCF7931_READ: // Read PCF7931 tag ReadPCF7931(); cmd_send(CMD_ACK,0,0,0,0,0); // UsbSendPacket((uint8_t*)&ack, sizeof(ack)); break; case CMD_EM4X_READ_WORD: EM4xReadWord(c->arg[1], c->arg[2],c->d.asBytes[0]); break; case CMD_EM4X_WRITE_WORD: EM4xWriteWord(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes[0]); break; #endif #ifdef WITH_HITAG case CMD_SNOOP_HITAG: // Eavesdrop Hitag tag, args = type SnoopHitag(c->arg[0]); break; case CMD_SIMULATE_HITAG: // Simulate Hitag tag, args = memory content SimulateHitagTag((bool)c->arg[0],(byte_t*)c->d.asBytes); break; case CMD_READER_HITAG: // Reader for Hitag tags, args = type and function ReaderHitag((hitag_function)c->arg[0],(hitag_data*)c->d.asBytes); break; #endif #ifdef WITH_ISO15693 case CMD_ACQUIRE_RAW_ADC_SAMPLES_ISO_15693: AcquireRawAdcSamplesIso15693(); break; case CMD_RECORD_RAW_ADC_SAMPLES_ISO_15693: RecordRawAdcSamplesIso15693(); break; case CMD_ISO_15693_COMMAND: DirectTag15693Command(c->arg[0],c->arg[1],c->arg[2],c->d.asBytes); break; case CMD_ISO_15693_FIND_AFI: BruteforceIso15693Afi(c->arg[0]); break; case CMD_ISO_15693_DEBUG: SetDebugIso15693(c->arg[0]); break; case CMD_READER_ISO_15693: ReaderIso15693(c->arg[0]); break; case CMD_SIMTAG_ISO_15693: SimTagIso15693(c->arg[0]); break; #endif #ifdef WITH_LEGICRF case CMD_SIMULATE_TAG_LEGIC_RF: LegicRfSimulate(c->arg[0], c->arg[1], c->arg[2]); break; case CMD_WRITER_LEGIC_RF: LegicRfWriter(c->arg[1], c->arg[0]); break; case CMD_READER_LEGIC_RF: LegicRfReader(c->arg[0], c->arg[1]); break; #endif #ifdef WITH_ISO14443b case CMD_ACQUIRE_RAW_ADC_SAMPLES_ISO_14443: AcquireRawAdcSamplesIso14443(c->arg[0]); break; case CMD_READ_SRI512_TAG: ReadSRI512Iso14443(c->arg[0]); break; case CMD_READ_SRIX4K_TAG: ReadSRIX4KIso14443(c->arg[0]); break; case CMD_SNOOP_ISO_14443: SnoopIso14443(); break; case CMD_SIMULATE_TAG_ISO_14443: SimulateIso14443Tag(); break; #endif #ifdef WITH_ISO14443a case CMD_SNOOP_ISO_14443a: SnoopIso14443a(c->arg[0]); break; case CMD_READER_ISO_14443a: ReaderIso14443a(c); break; case CMD_SIMULATE_TAG_ISO_14443a: SimulateIso14443aTag(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes); // ## Simulate iso14443a tag - pass tag type & UID break; case CMD_EPA_PACE_COLLECT_NONCE: EPA_PACE_Collect_Nonce(c); break; case CMD_READER_MIFARE: ReaderMifare(c->arg[0]); break; case CMD_MIFARE_READBL: MifareReadBlock(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes); break; case CMD_MIFARE_READSC: MifareReadSector(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes); break; case CMD_MIFARE_WRITEBL: MifareWriteBlock(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes); break; case CMD_MIFARE_NESTED: MifareNested(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes); break; case CMD_MIFARE_CHKKEYS: MifareChkKeys(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes); break; case CMD_SIMULATE_MIFARE_CARD: Mifare1ksim(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes); break; // emulator case CMD_MIFARE_SET_DBGMODE: MifareSetDbgLvl(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes); break; case CMD_MIFARE_EML_MEMCLR: MifareEMemClr(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes); break; case CMD_MIFARE_EML_MEMSET: MifareEMemSet(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes); break; case CMD_MIFARE_EML_MEMGET: MifareEMemGet(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes); break; case CMD_MIFARE_EML_CARDLOAD: MifareECardLoad(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes); break; // Work with "magic Chinese" card case CMD_MIFARE_EML_CSETBLOCK: MifareCSetBlock(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes); break; case CMD_MIFARE_EML_CGETBLOCK: MifareCGetBlock(c->arg[0], c->arg[1], c->arg[2], c->d.asBytes); break; // mifare sniffer case CMD_MIFARE_SNIFFER: SniffMifare(c->arg[0]); break; #endif #ifdef WITH_ICLASS // Makes use of ISO14443a FPGA Firmware case CMD_SNOOP_ICLASS: SnoopIClass(); break; case CMD_SIMULATE_TAG_ICLASS: SimulateIClass(c->arg[0], c->d.asBytes); break; case CMD_READER_ICLASS: ReaderIClass(c->arg[0]); break; #endif case CMD_SIMULATE_TAG_HF_LISTEN: SimulateTagHfListen(); break; case CMD_BUFF_CLEAR: BufferClear(); break; case CMD_MEASURE_ANTENNA_TUNING: MeasureAntennaTuning(); break; case CMD_MEASURE_ANTENNA_TUNING_HF: MeasureAntennaTuningHf(); break; case CMD_LISTEN_READER_FIELD: ListenReaderField(c->arg[0]); break; case CMD_FPGA_MAJOR_MODE_OFF: // ## FPGA Control FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); SpinDelay(200); LED_D_OFF(); // LED D indicates field ON or OFF break; case CMD_DOWNLOAD_RAW_ADC_SAMPLES_125K: // UsbCommand n; // if(c->cmd == CMD_DOWNLOAD_RAW_ADC_SAMPLES_125K) { // n.cmd = CMD_DOWNLOADED_RAW_ADC_SAMPLES_125K; // } else { // n.cmd = CMD_DOWNLOADED_RAW_BITS_TI_TYPE; // } // n.arg[0] = c->arg[0]; // memcpy(n.d.asBytes, BigBuf+c->arg[0], 48); // 12*sizeof(uint32_t) // LED_B_ON(); // usb_write((uint8_t *)&n, sizeof(n)); // UsbSendPacket((uint8_t *)&n, sizeof(n)); // LED_B_OFF(); LED_B_ON(); for(size_t i=0; iarg[1]; i += USB_CMD_DATA_SIZE) { size_t len = MIN((c->arg[1] - i),USB_CMD_DATA_SIZE); cmd_send(CMD_DOWNLOADED_RAW_ADC_SAMPLES_125K,i,len,0,((byte_t*)BigBuf)+c->arg[0]+i,len); } // Trigger a finish downloading signal with an ACK frame cmd_send(CMD_ACK,0,0,0,0,0); LED_B_OFF(); break; case CMD_DOWNLOADED_SIM_SAMPLES_125K: { uint8_t *b = (uint8_t *)BigBuf; memcpy(b+c->arg[0], c->d.asBytes, 48); //Dbprintf("copied 48 bytes to %i",b+c->arg[0]); // UsbSendPacket((uint8_t*)&ack, sizeof(ack)); cmd_send(CMD_ACK,0,0,0,0,0); break; } case CMD_READ_MEM: ReadMem(c->arg[0]); break; case CMD_SET_LF_DIVISOR: FpgaSendCommand(FPGA_CMD_SET_DIVISOR, c->arg[0]); break; case CMD_SET_ADC_MUX: switch(c->arg[0]) { case 0: SetAdcMuxFor(GPIO_MUXSEL_LOPKD); break; case 1: SetAdcMuxFor(GPIO_MUXSEL_LORAW); break; case 2: SetAdcMuxFor(GPIO_MUXSEL_HIPKD); break; case 3: SetAdcMuxFor(GPIO_MUXSEL_HIRAW); break; } break; case CMD_VERSION: SendVersion(); break; #ifdef WITH_LCD case CMD_LCD_RESET: LCDReset(); break; case CMD_LCD: LCDSend(c->arg[0]); break; #endif case CMD_SETUP_WRITE: case CMD_FINISH_WRITE: case CMD_HARDWARE_RESET: usb_disable(); SpinDelay(1000); SpinDelay(1000); AT91C_BASE_RSTC->RSTC_RCR = RST_CONTROL_KEY | AT91C_RSTC_PROCRST; for(;;) { // We're going to reset, and the bootrom will take control. } break; case CMD_START_FLASH: if(common_area.flags.bootrom_present) { common_area.command = COMMON_AREA_COMMAND_ENTER_FLASH_MODE; } usb_disable(); AT91C_BASE_RSTC->RSTC_RCR = RST_CONTROL_KEY | AT91C_RSTC_PROCRST; for(;;); break; case CMD_DEVICE_INFO: { uint32_t dev_info = DEVICE_INFO_FLAG_OSIMAGE_PRESENT | DEVICE_INFO_FLAG_CURRENT_MODE_OS; if(common_area.flags.bootrom_present) dev_info |= DEVICE_INFO_FLAG_BOOTROM_PRESENT; // UsbSendPacket((uint8_t*)&c, sizeof(c)); cmd_send(CMD_DEVICE_INFO,dev_info,0,0,0,0); break; } default: Dbprintf("%s: 0x%04x","unknown command:",c->cmd); break; } } void __attribute__((noreturn)) AppMain(void) { SpinDelay(100); if(common_area.magic != COMMON_AREA_MAGIC || common_area.version != 1) { /* Initialize common area */ memset(&common_area, 0, sizeof(common_area)); common_area.magic = COMMON_AREA_MAGIC; common_area.version = 1; } common_area.flags.osimage_present = 1; LED_D_OFF(); LED_C_OFF(); LED_B_OFF(); LED_A_OFF(); // Init USB device` usb_enable(); // UsbStart(); // The FPGA gets its clock from us from PCK0 output, so set that up. AT91C_BASE_PIOA->PIO_BSR = GPIO_PCK0; AT91C_BASE_PIOA->PIO_PDR = GPIO_PCK0; AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_PCK0; // PCK0 is PLL clock / 4 = 96Mhz / 4 = 24Mhz AT91C_BASE_PMC->PMC_PCKR[0] = AT91C_PMC_CSS_PLL_CLK | AT91C_PMC_PRES_CLK_4; AT91C_BASE_PIOA->PIO_OER = GPIO_PCK0; // Reset SPI AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST; // Reset SSC AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST; // Load the FPGA image, which we have stored in our flash. FpgaDownloadAndGo(); StartTickCount(); #ifdef WITH_LCD LCDInit(); #endif byte_t rx[sizeof(UsbCommand)]; size_t rx_len; for(;;) { if (usb_poll()) { rx_len = usb_read(rx,sizeof(UsbCommand)); if (rx_len) { UsbPacketReceived(rx,rx_len); } } // UsbPoll(FALSE); WDT_HIT(); #ifdef WITH_LF if (BUTTON_HELD(1000) > 0) SamyRun(); #endif } } ================================================ FILE: TamagotchiFriends/proxmark/armsrc/apps.h ================================================ //----------------------------------------------------------------------------- // Jonathan Westhues, Aug 2005 // Gerhard de Koning Gans, April 2008, May 2011 // // This code is licensed to you under the terms of the GNU GPL, version 2 or, // at your option, any later version. See the LICENSE.txt file for the text of // the license. //----------------------------------------------------------------------------- // Definitions internal to the app source. //----------------------------------------------------------------------------- #ifndef __APPS_H #define __APPS_H #include #include #include "common.h" #include "hitag2.h" #include "mifare.h" // The large multi-purpose buffer, typically used to hold A/D samples, // maybe processed in some way. uint8_t BigBuf[40000]; // BIG CHANGE - UNDERSTAND THIS BEFORE WE COMMIT #define TRACE_OFFSET 0 #define TRACE_SIZE 3000 #define RECV_CMD_OFFSET 3032 #define RECV_CMD_SIZE 64 #define RECV_RES_OFFSET 3096 #define RECV_RES_SIZE 64 #define DMA_BUFFER_OFFSET 3160 #define DMA_BUFFER_SIZE 4096 #define FREE_BUFFER_OFFSET 7256 #define FREE_BUFFER_SIZE 2744 extern const uint8_t OddByteParity[256]; extern uint8_t *trace; // = (uint8_t *) BigBuf; extern int traceLen; // = 0; extern int rsamples; // = 0; extern int tracing; // = TRUE; extern uint8_t trigger; // This may be used (sparingly) to declare a function to be copied to // and executed from RAM #define RAMFUNC __attribute((long_call, section(".ramfunc"))) /// appmain.h void ReadMem(int addr); void __attribute__((noreturn)) AppMain(void); void SamyRun(void); //void DbpIntegers(int a, int b, int c); void DbpString(char *str); void Dbprintf(const char *fmt, ...); void Dbhexdump(int len, uint8_t *d, bool bAsci); int AvgAdc(int ch); void ToSendStuffBit(int b); void ToSendReset(void); void ListenReaderField(int limit); void AcquireRawAdcSamples125k(int at134khz); void DoAcquisition125k(void); extern int ToSendMax; extern uint8_t ToSend[]; extern uint8_t BigBuf[]; /// fpga.h void FpgaSendCommand(uint16_t cmd, uint16_t v); void FpgaWriteConfWord(uint8_t v); void FpgaDownloadAndGo(void); void FpgaGatherVersion(char *dst, int len); void FpgaSetupSsc(void); void SetupSpi(int mode); bool FpgaSetupSscDma(uint8_t *buf, int len); #define FpgaDisableSscDma(void) AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS; #define FpgaEnableSscDma(void) AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN; void SetAdcMuxFor(uint32_t whichGpio); // Definitions for the FPGA commands. #define FPGA_CMD_SET_CONFREG (1<<12) #define FPGA_CMD_SET_DIVISOR (2<<12) // Definitions for the FPGA configuration word. #define FPGA_MAJOR_MODE_LF_READER (0<<5) #define FPGA_MAJOR_MODE_LF_EDGE_DETECT (1<<5) #define FPGA_MAJOR_MODE_HF_READER_TX (2<<5) #define FPGA_MAJOR_MODE_HF_READER_RX_XCORR (3<<5) #define FPGA_MAJOR_MODE_HF_SIMULATOR (4<<5) #define FPGA_MAJOR_MODE_HF_ISO14443A (5<<5) #define FPGA_MAJOR_MODE_LF_PASSTHRU (6<<5) #define FPGA_MAJOR_MODE_OFF (7<<5) // Options for LF_EDGE_DETECT #define FPGA_LF_EDGE_DETECT_READER_FIELD (1<<0) // Options for the HF reader, tx to tag #define FPGA_HF_READER_TX_SHALLOW_MOD (1<<0) // Options for the HF reader, correlating against rx from tag #define FPGA_HF_READER_RX_XCORR_848_KHZ (1<<0) #define FPGA_HF_READER_RX_XCORR_SNOOP (1<<1) #define FPGA_HF_READER_RX_XCORR_QUARTER_FREQ (1<<2) // Options for the HF simulated tag, how to modulate #define FPGA_HF_SIMULATOR_NO_MODULATION (0<<0) #define FPGA_HF_SIMULATOR_MODULATE_BPSK (1<<0) #define FPGA_HF_SIMULATOR_MODULATE_212K (2<<0) // Options for ISO14443A #define FPGA_HF_ISO14443A_SNIFFER (0<<0) #define FPGA_HF_ISO14443A_TAGSIM_LISTEN (1<<0) #define FPGA_HF_ISO14443A_TAGSIM_MOD (2<<0) #define FPGA_HF_ISO14443A_READER_LISTEN (3<<0) #define FPGA_HF_ISO14443A_READER_MOD (4<<0) /// lfops.h void AcquireRawAdcSamples125k(int at134khz); void ModThenAcquireRawAdcSamples125k(int delay_off,int period_0,int period_1,uint8_t *command); void ReadTItag(void); void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc); void AcquireTiType(void); void AcquireRawBitsTI(void); void SimulateTagLowFrequency(int period, int gap, int ledcontrol); void CmdHIDsimTAG(int hi, int lo, int ledcontrol); void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol); void SimulateTagLowFrequencyBidir(int divisor, int max_bitlen); void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT); // Clone an HID card to T5557/T5567 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo); void CopyIndala64toT55x7(int hi, int lo); // Clone Indala 64-bit tag by UID to T55x7 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7); // Clone Indala 224-bit tag by UID to T55x7 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode); void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode ); void T55xxReadTrace(void); int DemodPCF7931(uint8_t **outBlocks); int IsBlock0PCF7931(uint8_t *Block); int IsBlock1PCF7931(uint8_t *Block); void ReadPCF7931(); void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode); void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode); /// iso14443.h void SimulateIso14443Tag(void); void AcquireRawAdcSamplesIso14443(uint32_t parameter); void ReadSRI512Iso14443(uint32_t parameter); void ReadSRIX4KIso14443(uint32_t parameter); void ReadSTMemoryIso14443(uint32_t parameter,uint32_t dwLast); void RAMFUNC SnoopIso14443(void); /// iso14443a.h void RAMFUNC SnoopIso14443a(uint8_t param); void SimulateIso14443aTag(int tagType, int uid_1st, int uid_2nd, byte_t* data); void ReaderIso14443a(UsbCommand * c); // Also used in iclass.c int RAMFUNC LogTrace(const uint8_t * btBytes, int iLen, int iSamples, uint32_t dwParity, int bReader); uint32_t GetParity(const uint8_t * pbtCmd, int iLen); void iso14a_set_trigger(bool enable); void iso14a_clear_trace(); void iso14a_set_tracing(bool enable); void RAMFUNC SniffMifare(uint8_t param); /// epa.h void EPA_PACE_Collect_Nonce(UsbCommand * c); // mifarecmd.h void ReaderMifare(bool first_try); void MifareReadBlock(uint8_t arg0, uint8_t arg1, uint8_t arg2, uint8_t *data); void MifareReadSector(uint8_t arg0, uint8_t arg1, uint8_t arg2, uint8_t *datain); void MifareWriteBlock(uint8_t arg0, uint8_t arg1, uint8_t arg2, uint8_t *datain); void MifareNested(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain); void MifareChkKeys(uint8_t arg0, uint8_t arg1, uint8_t arg2, uint8_t *datain); void Mifare1ksim(uint8_t arg0, uint8_t arg1, uint8_t arg2, uint8_t *datain); void MifareSetDbgLvl(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain); void MifareEMemClr(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain); void MifareEMemSet(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain); void MifareEMemGet(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain); void MifareECardLoad(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain); void MifareCSetBlock(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain); // Work with "magic Chinese" card void MifareCGetBlock(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain); /// iso15693.h void RecordRawAdcSamplesIso15693(void); void AcquireRawAdcSamplesIso15693(void); void ReaderIso15693(uint32_t parameter); // Simulate an ISO15693 reader - greg void SimTagIso15693(uint32_t parameter); // simulate an ISO15693 tag - greg void BruteforceIso15693Afi(uint32_t speed); // find an AFI of a tag - atrox void DirectTag15693Command(uint32_t datalen,uint32_t speed, uint32_t recv, uint8_t data[]); // send arbitrary commands from CLI - atrox void SetDebugIso15693(uint32_t flag); /// iclass.h void RAMFUNC SnoopIClass(void); void SimulateIClass(uint8_t arg0, uint8_t *datain); void ReaderIClass(uint8_t arg0); // hitag2.h void SnoopHitag(uint32_t type); void SimulateHitagTag(bool tag_mem_supplied, byte_t* data); void ReaderHitag(hitag_function htf, hitag_data* htd); // cmd.h bool cmd_receive(UsbCommand* cmd); bool cmd_send(uint32_t cmd, uint32_t arg0, uint32_t arg1, uint32_t arg2, void* data, size_t len); /// util.h #endif ================================================ FILE: TamagotchiFriends/proxmark/armsrc/crapto1.c ================================================ /* crapto1.c This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, US$ Copyright (C) 2008-2008 bla */ #include "crapto1.h" #include #if !defined LOWMEM && defined __GNUC__ static uint8_t filterlut[1 << 20]; static void __attribute__((constructor)) fill_lut() { uint32_t i; for(i = 0; i < 1 << 20; ++i) filterlut[i] = filter(i); } #define filter(x) (filterlut[(x) & 0xfffff]) #endif static void quicksort(uint32_t* const start, uint32_t* const stop) { uint32_t *it = start + 1, *rit = stop; if(it > rit) return; while(it < rit) if(*it <= *start) ++it; else if(*rit > *start) --rit; else *it ^= (*it ^= *rit, *rit ^= *it); if(*rit >= *start) --rit; if(rit != start) *rit ^= (*rit ^= *start, *start ^= *rit); quicksort(start, rit - 1); quicksort(rit + 1, stop); } /** binsearch * Binary search for the first occurence of *stop's MSB in sorted [start,stop] */ static inline uint32_t* binsearch(uint32_t *start, uint32_t *stop) { uint32_t mid, val = *stop & 0xff000000; while(start != stop) if(start[mid = (stop - start) >> 1] > val) stop = &start[mid]; else start += mid + 1; return start; } /** update_contribution * helper, calculates the partial linear feedback contributions and puts in MSB */ static inline void update_contribution(uint32_t *item, const uint32_t mask1, const uint32_t mask2) { uint32_t p = *item >> 25; p = p << 1 | parity(*item & mask1); p = p << 1 | parity(*item & mask2); *item = p << 24 | (*item & 0xffffff); } /** extend_table * using a bit of the keystream extend the table of possible lfsr states */ static inline void extend_table(uint32_t *tbl, uint32_t **end, int bit, int m1, int m2, uint32_t in) { in <<= 24; for(*tbl <<= 1; tbl <= *end; *++tbl <<= 1) if(filter(*tbl) ^ filter(*tbl | 1)) { *tbl |= filter(*tbl) ^ bit; update_contribution(tbl, m1, m2); *tbl ^= in; } else if(filter(*tbl) == bit) { *++*end = tbl[1]; tbl[1] = tbl[0] | 1; update_contribution(tbl, m1, m2); *tbl++ ^= in; update_contribution(tbl, m1, m2); *tbl ^= in; } else *tbl-- = *(*end)--; } /** extend_table_simple * using a bit of the keystream extend the table of possible lfsr states */ static inline void extend_table_simple(uint32_t *tbl, uint32_t **end, int bit) { for(*tbl <<= 1; tbl <= *end; *++tbl <<= 1) if(filter(*tbl) ^ filter(*tbl | 1)) *tbl |= filter(*tbl) ^ bit; else if(filter(*tbl) == bit) { *++*end = *++tbl; *tbl = tbl[-1] | 1; } else *tbl-- = *(*end)--; } /** recover * recursively narrow down the search space, 4 bits of keystream at a time */ static struct Crypto1State* recover(uint32_t *o_head, uint32_t *o_tail, uint32_t oks, uint32_t *e_head, uint32_t *e_tail, uint32_t eks, int rem, struct Crypto1State *sl, uint32_t in) { uint32_t *o, *e, i; if(rem == -1) { for(e = e_head; e <= e_tail; ++e) { *e = *e << 1 ^ parity(*e & LF_POLY_EVEN) ^ !!(in & 4); for(o = o_head; o <= o_tail; ++o, ++sl) { sl->even = *o; sl->odd = *e ^ parity(*o & LF_POLY_ODD); sl[1].odd = sl[1].even = 0; } } return sl; } for(i = 0; i < 4 && rem--; i++) { oks >>= 1; eks >>= 1; in >>= 2; extend_table(o_head, &o_tail, oks & 1, LF_POLY_EVEN << 1 | 1, LF_POLY_ODD << 1, 0); if(o_head > o_tail) return sl; extend_table(e_head, &e_tail, eks & 1, LF_POLY_ODD, LF_POLY_EVEN << 1 | 1, in & 3); if(e_head > e_tail) return sl; } quicksort(o_head, o_tail); quicksort(e_head, e_tail); while(o_tail >= o_head && e_tail >= e_head) if(((*o_tail ^ *e_tail) >> 24) == 0) { o_tail = binsearch(o_head, o = o_tail); e_tail = binsearch(e_head, e = e_tail); sl = recover(o_tail--, o, oks, e_tail--, e, eks, rem, sl, in); } else if(*o_tail > *e_tail) o_tail = binsearch(o_head, o_tail) - 1; else e_tail = binsearch(e_head, e_tail) - 1; return sl; } /** lfsr_recovery * recover the state of the lfsr given 32 bits of the keystream * additionally you can use the in parameter to specify the value * that was fed into the lfsr at the time the keystream was generated */ struct Crypto1State* lfsr_recovery32(uint32_t ks2, uint32_t in) { struct Crypto1State *statelist; uint32_t *odd_head = 0, *odd_tail = 0, oks = 0; uint32_t *even_head = 0, *even_tail = 0, eks = 0; int i; for(i = 31; i >= 0; i -= 2) oks = oks << 1 | BEBIT(ks2, i); for(i = 30; i >= 0; i -= 2) eks = eks << 1 | BEBIT(ks2, i); odd_head = odd_tail = malloc(sizeof(uint32_t) << 21); even_head = even_tail = malloc(sizeof(uint32_t) << 21); statelist = malloc(sizeof(struct Crypto1State) << 18); if(!odd_tail-- || !even_tail-- || !statelist) { free(statelist); statelist = 0; goto out; } statelist->odd = statelist->even = 0; for(i = 1 << 20; i >= 0; --i) { if(filter(i) == (oks & 1)) *++odd_tail = i; if(filter(i) == (eks & 1)) *++even_tail = i; } for(i = 0; i < 4; i++) { extend_table_simple(odd_head, &odd_tail, (oks >>= 1) & 1); extend_table_simple(even_head, &even_tail, (eks >>= 1) & 1); } in = (in >> 16 & 0xff) | (in << 16) | (in & 0xff00); recover(odd_head, odd_tail, oks, even_head, even_tail, eks, 11, statelist, in << 1); out: free(odd_head); free(even_head); return statelist; } static const uint32_t S1[] = { 0x62141, 0x310A0, 0x18850, 0x0C428, 0x06214, 0x0310A, 0x85E30, 0xC69AD, 0x634D6, 0xB5CDE, 0xDE8DA, 0x6F46D, 0xB3C83, 0x59E41, 0xA8995, 0xD027F, 0x6813F, 0x3409F, 0x9E6FA}; static const uint32_t S2[] = { 0x3A557B00, 0x5D2ABD80, 0x2E955EC0, 0x174AAF60, 0x0BA557B0, 0x05D2ABD8, 0x0449DE68, 0x048464B0, 0x42423258, 0x278192A8, 0x156042D0, 0x0AB02168, 0x43F89B30, 0x61FC4D98, 0x765EAD48, 0x7D8FDD20, 0x7EC7EE90, 0x7F63F748, 0x79117020}; static const uint32_t T1[] = { 0x4F37D, 0x279BE, 0x97A6A, 0x4BD35, 0x25E9A, 0x12F4D, 0x097A6, 0x80D66, 0xC4006, 0x62003, 0xB56B4, 0x5AB5A, 0xA9318, 0xD0F39, 0x6879C, 0xB057B, 0x582BD, 0x2C15E, 0x160AF, 0x8F6E2, 0xC3DC4, 0xE5857, 0x72C2B, 0x39615, 0x98DBF, 0xC806A, 0xE0680, 0x70340, 0x381A0, 0x98665, 0x4C332, 0xA272C}; static const uint32_t T2[] = { 0x3C88B810, 0x5E445C08, 0x2982A580, 0x14C152C0, 0x4A60A960, 0x253054B0, 0x52982A58, 0x2FEC9EA8, 0x1156C4D0, 0x08AB6268, 0x42F53AB0, 0x217A9D58, 0x161DC528, 0x0DAE6910, 0x46D73488, 0x25CB11C0, 0x52E588E0, 0x6972C470, 0x34B96238, 0x5CFC3A98, 0x28DE96C8, 0x12CFC0E0, 0x4967E070, 0x64B3F038, 0x74F97398, 0x7CDC3248, 0x38CE92A0, 0x1C674950, 0x0E33A4A8, 0x01B959D0, 0x40DCACE8, 0x26CEDDF0}; static const uint32_t C1[] = { 0x846B5, 0x4235A, 0x211AD}; static const uint32_t C2[] = { 0x1A822E0, 0x21A822E0, 0x21A822E0}; /** Reverse 64 bits of keystream into possible cipher states * Variation mentioned in the paper. Somewhat optimized version */ struct Crypto1State* lfsr_recovery64(uint32_t ks2, uint32_t ks3) { struct Crypto1State *statelist, *sl; uint8_t oks[32], eks[32], hi[32]; uint32_t low = 0, win = 0; uint32_t *tail, table[1 << 16]; int i, j; sl = statelist = malloc(sizeof(struct Crypto1State) << 4); if(!sl) return 0; sl->odd = sl->even = 0; for(i = 30; i >= 0; i -= 2) { oks[i >> 1] = BEBIT(ks2, i); oks[16 + (i >> 1)] = BEBIT(ks3, i); } for(i = 31; i >= 0; i -= 2) { eks[i >> 1] = BEBIT(ks2, i); eks[16 + (i >> 1)] = BEBIT(ks3, i); } for(i = 0xfffff; i >= 0; --i) { if (filter(i) != oks[0]) continue; *(tail = table) = i; for(j = 1; tail >= table && j < 29; ++j) extend_table_simple(table, &tail, oks[j]); if(tail < table) continue; for(j = 0; j < 19; ++j) low = low << 1 | parity(i & S1[j]); for(j = 0; j < 32; ++j) hi[j] = parity(i & T1[j]); for(; tail >= table; --tail) { for(j = 0; j < 3; ++j) { *tail = *tail << 1; *tail |= parity((i & C1[j]) ^ (*tail & C2[j])); if(filter(*tail) != oks[29 + j]) goto continue2; } for(j = 0; j < 19; ++j) win = win << 1 | parity(*tail & S2[j]); win ^= low; for(j = 0; j < 32; ++j) { win = win << 1 ^ hi[j] ^ parity(*tail & T2[j]); if(filter(win) != eks[j]) goto continue2; } *tail = *tail << 1 | parity(LF_POLY_EVEN & *tail); sl->odd = *tail ^ parity(LF_POLY_ODD & win); sl->even = win; ++sl; sl->odd = sl->even = 0; continue2:; } } return statelist; } /** lfsr_rollback_bit * Rollback the shift register in order to get previous states */ uint8_t lfsr_rollback_bit(struct Crypto1State *s, uint32_t in, int fb) { int out; uint8_t ret; s->odd &= 0xffffff; s->odd ^= (s->odd ^= s->even, s->even ^= s->odd); out = s->even & 1; out ^= LF_POLY_EVEN & (s->even >>= 1); out ^= LF_POLY_ODD & s->odd; out ^= !!in; out ^= (ret = filter(s->odd)) & !!fb; s->even |= parity(out) << 23; return ret; } /** lfsr_rollback_byte * Rollback the shift register in order to get previous states */ uint8_t lfsr_rollback_byte(struct Crypto1State *s, uint32_t in, int fb) { int i, ret = 0; for (i = 7; i >= 0; --i) ret |= lfsr_rollback_bit(s, BIT(in, i), fb) << i; return ret; } /** lfsr_rollback_word * Rollback the shift register in order to get previous states */ uint32_t lfsr_rollback_word(struct Crypto1State *s, uint32_t in, int fb) { int i; uint32_t ret = 0; for (i = 31; i >= 0; --i) ret |= lfsr_rollback_bit(s, BEBIT(in, i), fb) << (i ^ 24); return ret; } /** nonce_distance * x,y valid tag nonces, then prng_successor(x, nonce_distance(x, y)) = y */ static uint16_t *dist = 0; int nonce_distance(uint32_t from, uint32_t to) { uint16_t x, i; if(!dist) { dist = malloc(2 << 16); if(!dist) return -1; for (x = i = 1; i; ++i) { dist[(x & 0xff) << 8 | x >> 8] = i; x = x >> 1 | (x ^ x >> 2 ^ x >> 3 ^ x >> 5) << 15; } } return (65535 + dist[to >> 16] - dist[from >> 16]) % 65535; } static uint32_t fastfwd[2][8] = { { 0, 0x4BC53, 0xECB1, 0x450E2, 0x25E29, 0x6E27A, 0x2B298, 0x60ECB}, { 0, 0x1D962, 0x4BC53, 0x56531, 0xECB1, 0x135D3, 0x450E2, 0x58980}}; /** lfsr_prefix_ks * * Is an exported helper function from the common prefix attack * Described in the "dark side" paper. It returns an -1 terminated array * of possible partial(21 bit) secret state. * The required keystream(ks) needs to contain the keystream that was used to * encrypt the NACK which is observed when varying only the 3 last bits of Nr * only correct iff [NR_3] ^ NR_3 does not depend on Nr_3 */ uint32_t *lfsr_prefix_ks(uint8_t ks[8], int isodd) { uint32_t c, entry, *candidates = malloc(4 << 10); int i, size = 0, good; if(!candidates) return 0; for(i = 0; i < 1 << 21; ++i) { for(c = 0, good = 1; good && c < 8; ++c) { entry = i ^ fastfwd[isodd][c]; good &= (BIT(ks[c], isodd) == filter(entry >> 1)); good &= (BIT(ks[c], isodd + 2) == filter(entry)); } if(good) candidates[size++] = i; } candidates[size] = -1; return candidates; } /** check_pfx_parity * helper function which eliminates possible secret states using parity bits */ static struct Crypto1State* check_pfx_parity(uint32_t prefix, uint32_t rresp, uint8_t parities[8][8], uint32_t odd, uint32_t even, struct Crypto1State* sl) { uint32_t ks1, nr, ks2, rr, ks3, c, good = 1; for(c = 0; good && c < 8; ++c) { sl->odd = odd ^ fastfwd[1][c]; sl->even = even ^ fastfwd[0][c]; lfsr_rollback_bit(sl, 0, 0); lfsr_rollback_bit(sl, 0, 0); ks3 = lfsr_rollback_bit(sl, 0, 0); ks2 = lfsr_rollback_word(sl, 0, 0); ks1 = lfsr_rollback_word(sl, prefix | c << 5, 1); nr = ks1 ^ (prefix | c << 5); rr = ks2 ^ rresp; good &= parity(nr & 0x000000ff) ^ parities[c][3] ^ BIT(ks2, 24); good &= parity(rr & 0xff000000) ^ parities[c][4] ^ BIT(ks2, 16); good &= parity(rr & 0x00ff0000) ^ parities[c][5] ^ BIT(ks2, 8); good &= parity(rr & 0x0000ff00) ^ parities[c][6] ^ BIT(ks2, 0); good &= parity(rr & 0x000000ff) ^ parities[c][7] ^ ks3; } return sl + good; } /** lfsr_common_prefix * Implentation of the common prefix attack. */ struct Crypto1State* lfsr_common_prefix(uint32_t pfx, uint32_t rr, uint8_t ks[8], uint8_t par[8][8]) { struct Crypto1State *statelist, *s; uint32_t *odd, *even, *o, *e, top; odd = lfsr_prefix_ks(ks, 1); even = lfsr_prefix_ks(ks, 0); s = statelist = malloc((sizeof *statelist) << 20); if(!s || !odd || !even) { free(statelist); statelist = 0; goto out; } for(o = odd; *o + 1; ++o) for(e = even; *e + 1; ++e) for(top = 0; top < 64; ++top) { *o += 1 << 21; *e += (!(top & 7) + 1) << 21; s = check_pfx_parity(pfx, rr, par, *o, *e, s); } s->odd = s->even = 0; out: free(odd); free(even); return statelist; } ================================================ FILE: TamagotchiFriends/proxmark/armsrc/crapto1.h ================================================ /* crapto1.h This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, US$ Copyright (C) 2008-2008 bla */ #ifndef CRAPTO1_INCLUDED #define CRAPTO1_INCLUDED #include #ifdef __cplusplus extern "C" { #endif struct Crypto1State {uint32_t odd, even;}; void crypto1_create(struct Crypto1State *s, uint64_t key); void crypto1_destroy(struct Crypto1State*); void crypto1_get_lfsr(struct Crypto1State*, uint64_t*); uint8_t crypto1_bit(struct Crypto1State*, uint8_t, int); uint8_t crypto1_byte(struct Crypto1State*, uint8_t, int); uint32_t crypto1_word(struct Crypto1State*, uint32_t, int); uint32_t prng_successor(uint32_t x, uint32_t n); struct Crypto1State* lfsr_recovery32(uint32_t ks2, uint32_t in); struct Crypto1State* lfsr_recovery64(uint32_t ks2, uint32_t ks3); uint32_t *lfsr_prefix_ks(uint8_t ks[8], int isodd); struct Crypto1State* lfsr_common_prefix(uint32_t pfx, uint32_t rr, uint8_t ks[8], uint8_t par[8][8]); uint8_t lfsr_rollback_bit(struct Crypto1State* s, uint32_t in, int fb); uint8_t lfsr_rollback_byte(struct Crypto1State* s, uint32_t in, int fb); uint32_t lfsr_rollback_word(struct Crypto1State* s, uint32_t in, int fb); int nonce_distance(uint32_t from, uint32_t to); #define FOREACH_VALID_NONCE(N, FILTER, FSIZE)\ uint32_t __n = 0,__M = 0, N = 0;\ int __i;\ for(; __n < 1 << 16; N = prng_successor(__M = ++__n, 16))\ for(__i = FSIZE - 1; __i >= 0; __i--)\ if(BIT(FILTER, __i) ^ parity(__M & 0xFF01))\ break;\ else if(__i)\ __M = prng_successor(__M, (__i == 7) ? 48 : 8);\ else #define LF_POLY_ODD (0x29CE5C) #define LF_POLY_EVEN (0x870804) #define BIT(x, n) ((x) >> (n) & 1) #define BEBIT(x, n) BIT(x, (n) ^ 24) static inline int parity(uint32_t x) { #if !defined __i386__ || !defined __GNUC__ x ^= x >> 16; x ^= x >> 8; x ^= x >> 4; return BIT(0x6996, x & 0xf); #else asm( "movl %1, %%eax\n" "mov %%ax, %%cx\n" "shrl $0x10, %%eax\n" "xor %%ax, %%cx\n" "xor %%ch, %%cl\n" "setpo %%al\n" "movzx %%al, %0\n": "=r"(x) : "r"(x): "eax","ecx"); return x; #endif } static inline int filter(uint32_t const x) { uint32_t f; f = 0xf22c0 >> (x & 0xf) & 16; f |= 0x6c9c0 >> (x >> 4 & 0xf) & 8; f |= 0x3c8b0 >> (x >> 8 & 0xf) & 4; f |= 0x1e458 >> (x >> 12 & 0xf) & 2; f |= 0x0d938 >> (x >> 16 & 0xf) & 1; return BIT(0xEC57E80A, f); } #ifdef __cplusplus } #endif #endif ================================================ FILE: TamagotchiFriends/proxmark/armsrc/crypto1.c ================================================ /* crypto1.c This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, US Copyright (C) 2008-2008 bla */ #include "crapto1.h" #include #define SWAPENDIAN(x)\ (x = (x >> 8 & 0xff00ff) | (x & 0xff00ff) << 8, x = x >> 16 | x << 16) void crypto1_create(struct Crypto1State *s, uint64_t key) { // struct Crypto1State *s = malloc(sizeof(*s)); int i; for(i = 47;s && i > 0; i -= 2) { s->odd = s->odd << 1 | BIT(key, (i - 1) ^ 7); s->even = s->even << 1 | BIT(key, i ^ 7); } return; } void crypto1_destroy(struct Crypto1State *state) { // free(state); state->odd = 0; state->even = 0; } void crypto1_get_lfsr(struct Crypto1State *state, uint64_t *lfsr) { int i; for(*lfsr = 0, i = 23; i >= 0; --i) { *lfsr = *lfsr << 1 | BIT(state->odd, i ^ 3); *lfsr = *lfsr << 1 | BIT(state->even, i ^ 3); } } uint8_t crypto1_bit(struct Crypto1State *s, uint8_t in, int is_encrypted) { uint32_t feedin; uint8_t ret = filter(s->odd); feedin = ret & !!is_encrypted; feedin ^= !!in; feedin ^= LF_POLY_ODD & s->odd; feedin ^= LF_POLY_EVEN & s->even; s->even = s->even << 1 | parity(feedin); s->odd ^= (s->odd ^= s->even, s->even ^= s->odd); return ret; } uint8_t crypto1_byte(struct Crypto1State *s, uint8_t in, int is_encrypted) { uint8_t i, ret = 0; for (i = 0; i < 8; ++i) ret |= crypto1_bit(s, BIT(in, i), is_encrypted) << i; return ret; } uint32_t crypto1_word(struct Crypto1State *s, uint32_t in, int is_encrypted) { uint32_t i, ret = 0; for (i = 0; i < 32; ++i) ret |= crypto1_bit(s, BEBIT(in, i), is_encrypted) << (i ^ 24); return ret; } /* prng_successor * helper used to obscure the keystream during authentication */ uint32_t prng_successor(uint32_t x, uint32_t n) { SWAPENDIAN(x); while(n--) x = x >> 1 | (x >> 16 ^ x >> 18 ^ x >> 19 ^ x >> 21) << 31; return SWAPENDIAN(x); } ================================================ FILE: TamagotchiFriends/proxmark/armsrc/epa.c ================================================ //----------------------------------------------------------------------------- // Frederik Möllers - August 2012 // // This code is licensed to you under the terms of the GNU GPL, version 2 or, // at your option, any later version. See the LICENSE.txt file for the text of // the license. //----------------------------------------------------------------------------- // Routines to support the German eletronic "Personalausweis" (ID card) // Note that the functions which do not implement USB commands do NOT initialize // the card (with iso14443a_select_card etc.). If You want to use these // functions, You need to do the setup before calling them! //----------------------------------------------------------------------------- #include "iso14443a.h" #include "epa.h" #include "cmd.h" // Protocol and Parameter Selection Request // use regular (1x) speed in both directions // CRC is already included static const uint8_t pps[] = {0xD0, 0x11, 0x00, 0x52, 0xA6}; // APDUs for communication with German Identification Card // General Authenticate (request encrypted nonce) WITHOUT the Le at the end static const uint8_t apdu_general_authenticate_pace_get_nonce[] = { 0x10, // CLA 0x86, // INS 0x00, // P1 0x00, // P2 0x02, // Lc 0x7C, // Type: Dynamic Authentication Data 0x00, // Length: 0 bytes }; // MSE: Set AT (only CLA, INS, P1 and P2) static const uint8_t apdu_mse_set_at_start[] = { 0x00, // CLA 0x22, // INS 0xC1, // P1 0xA4, // P2 }; // SELECT BINARY with the ID for EF.CardAccess static const uint8_t apdu_select_binary_cardaccess[] = { 0x00, // CLA 0xA4, // INS 0x02, // P1 0x0C, // P2 0x02, // Lc 0x01, // ID 0x1C // ID }; // READ BINARY static const uint8_t apdu_read_binary[] = { 0x00, // CLA 0xB0, // INS 0x00, // P1 0x00, // P2 0x38 // Le }; // the leading bytes of a PACE OID static const uint8_t oid_pace_start[] = { 0x04, // itu-t, identified-organization 0x00, // etsi 0x7F, // reserved 0x00, // etsi-identified-organization 0x07, // bsi-de 0x02, // protocols 0x02, // smartcard 0x04 // id-PACE }; //----------------------------------------------------------------------------- // Closes the communication channel and turns off the field //----------------------------------------------------------------------------- void EPA_Finish() { FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); LEDsoff(); } //----------------------------------------------------------------------------- // Parses DER encoded data, e.g. from EF.CardAccess and fills out the given // structs. If a pointer is 0, it is ignored. // The function returns 0 on success and if an error occured, it returns the // offset where it occured. // // TODO: This function can access memory outside of the given data if the DER // encoding is broken // TODO: Support skipping elements with a length > 0x7F // TODO: Support OIDs with a length > 7F // TODO: Support elements with long tags (tag is longer than 1 byte) // TODO: Support proprietary PACE domain parameters //----------------------------------------------------------------------------- size_t EPA_Parse_CardAccess(uint8_t *data, size_t length, pace_version_info_t *pace_info) { size_t index = 0; while (index <= length - 2) { // determine type of element // SET or SEQUENCE if (data[index] == 0x31 || data[index] == 0x30) { // enter the set (skip tag + length) index += 2; // extended length if ((data[index - 1] & 0x80) != 0) { index += (data[index] & 0x7F); } } // OID else if (data[index] == 0x06) { // is this a PACE OID? if (data[index + 1] == 0x0A // length matches && memcmp(data + index + 2, oid_pace_start, sizeof(oid_pace_start)) == 0 // content matches && pace_info != NULL) { // first, clear the pace_info struct memset(pace_info, 0, sizeof(pace_version_info_t)); memcpy(pace_info->oid, data + index + 2, sizeof(pace_info->oid)); // a PACE OID is followed by the version index += data[index + 1] + 2; if (data[index] == 02 && data[index + 1] == 01) { pace_info->version = data[index + 2]; index += 3; } else { return index; } // after that there might(!) be the parameter ID if (data[index] == 02 && data[index + 1] == 01) { pace_info->parameter_id = data[index + 2]; index += 3; } } else { // skip this OID index += 2 + data[index + 1]; } } // if the length is 0, something is wrong // TODO: This needs to be extended to support long tags else if (data[index + 1] == 0) { return index; } else { // skip this part // TODO: This needs to be extended to support long tags // TODO: This needs to be extended to support unknown elements with // a size > 0x7F index += 2 + data[index + 1]; } } // TODO: We should check whether we reached the end in error, but for that // we need a better parser (e.g. with states like IN_SET or IN_PACE_INFO) return 0; } //----------------------------------------------------------------------------- // Read the file EF.CardAccess and save it into a buffer (at most max_length bytes) // Returns -1 on failure or the length of the data on success // TODO: for the moment this sends only 1 APDU regardless of the requested length //----------------------------------------------------------------------------- int EPA_Read_CardAccess(uint8_t *buffer, size_t max_length) { // the response APDU of the card // since the card doesn't always care for the expected length we send it, // we reserve 262 bytes here just to be safe (256-byte APDU + SW + ISO frame) uint8_t response_apdu[262]; int rapdu_length = 0; // select the file EF.CardAccess rapdu_length = iso14_apdu((uint8_t *)apdu_select_binary_cardaccess, sizeof(apdu_select_binary_cardaccess), response_apdu); if (rapdu_length != 6 || response_apdu[rapdu_length - 4] != 0x90 || response_apdu[rapdu_length - 3] != 0x00) { return -1; } // read the file rapdu_length = iso14_apdu((uint8_t *)apdu_read_binary, sizeof(apdu_read_binary), response_apdu); if (rapdu_length <= 6 || response_apdu[rapdu_length - 4] != 0x90 || response_apdu[rapdu_length - 3] != 0x00) { return -1; } // copy the content into the buffer // length of data available: apdu_length - 4 (ISO frame) - 2 (SW) size_t to_copy = rapdu_length - 6; to_copy = to_copy < max_length ? to_copy : max_length; memcpy(buffer, response_apdu+2, to_copy); return to_copy; } //----------------------------------------------------------------------------- // Abort helper function for EPA_PACE_Collect_Nonce // sets relevant data in ack, sends the response //----------------------------------------------------------------------------- static void EPA_PACE_Collect_Nonce_Abort(uint8_t step, int func_return) { // // step in which the failure occured // ack->arg[0] = step; // // last return code // ack->arg[1] = func_return; // power down the field EPA_Finish(); // send the USB packet cmd_send(CMD_ACK,step,func_return,0,0,0); //UsbSendPacket((void *)ack, sizeof(UsbCommand)); } //----------------------------------------------------------------------------- // Acquire one encrypted PACE nonce //----------------------------------------------------------------------------- void EPA_PACE_Collect_Nonce(UsbCommand *c) { /* * ack layout: * arg: * 1. element * step where the error occured or 0 if no error occured * 2. element * return code of the last executed function * d: * Encrypted nonce */ // return value of a function int func_return; // // initialize ack with 0s // memset(ack->arg, 0, 12); // memset(ack->d.asBytes, 0, 48); // set up communication func_return = EPA_Setup(); if (func_return != 0) { EPA_PACE_Collect_Nonce_Abort(1, func_return); return; } // increase the timeout (at least some cards really do need this!) iso14a_set_timeout(0x0002FFFF); // read the CardAccess file // this array will hold the CardAccess file uint8_t card_access[256] = {0}; int card_access_length = EPA_Read_CardAccess(card_access, 256); // the response has to be at least this big to hold the OID if (card_access_length < 18) { EPA_PACE_Collect_Nonce_Abort(2, card_access_length); return; } // this will hold the PACE info of the card pace_version_info_t pace_version_info; // search for the PACE OID func_return = EPA_Parse_CardAccess(card_access, card_access_length, &pace_version_info); if (func_return != 0 || pace_version_info.version == 0) { EPA_PACE_Collect_Nonce_Abort(3, func_return); return; } // initiate the PACE protocol // use the CAN for the password since that doesn't change func_return = EPA_PACE_MSE_Set_AT(pace_version_info, 2); // now get the nonce uint8_t nonce[256] = {0}; uint8_t requested_size = (uint8_t)c->arg[0]; func_return = EPA_PACE_Get_Nonce(requested_size, nonce); // check if the command succeeded if (func_return < 0) { EPA_PACE_Collect_Nonce_Abort(4, func_return); return; } // all done, return EPA_Finish(); // save received information // ack->arg[1] = func_return; // memcpy(ack->d.asBytes, nonce, func_return); // UsbSendPacket((void *)ack, sizeof(UsbCommand)); cmd_send(CMD_ACK,0,func_return,0,nonce,func_return); } //----------------------------------------------------------------------------- // Performs the "Get Nonce" step of the PACE protocol and saves the returned // nonce. The caller is responsible for allocating enough memory to store the // nonce. Note that the returned size might be less or than or greater than the // requested size! // Returns the actual size of the nonce on success or a less-than-zero error // code on failure. //----------------------------------------------------------------------------- int EPA_PACE_Get_Nonce(uint8_t requested_length, uint8_t *nonce) { // build the APDU uint8_t apdu[sizeof(apdu_general_authenticate_pace_get_nonce) + 1]; // copy the constant part memcpy(apdu, apdu_general_authenticate_pace_get_nonce, sizeof(apdu_general_authenticate_pace_get_nonce)); // append Le (requested length + 2 due to tag/length taking 2 bytes) in RAPDU apdu[sizeof(apdu_general_authenticate_pace_get_nonce)] = requested_length + 4; // send it uint8_t response_apdu[262]; int send_return = iso14_apdu(apdu, sizeof(apdu), response_apdu); // check if the command succeeded if (send_return < 6 || response_apdu[send_return - 4] != 0x90 || response_apdu[send_return - 3] != 0x00) { return -1; } // if there is no nonce in the RAPDU, return here if (send_return < 10) { // no error return 0; } // get the actual length of the nonce uint8_t nonce_length = response_apdu[5]; if (nonce_length > send_return - 10) { nonce_length = send_return - 10; } // copy the nonce memcpy(nonce, response_apdu + 6, nonce_length); return nonce_length; } //----------------------------------------------------------------------------- // Initializes the PACE protocol by performing the "MSE: Set AT" step // Returns 0 on success or a non-zero error code on failure //----------------------------------------------------------------------------- int EPA_PACE_MSE_Set_AT(pace_version_info_t pace_version_info, uint8_t password) { // create the MSE: Set AT APDU uint8_t apdu[23]; // the minimum length (will be increased as more data is added) size_t apdu_length = 20; // copy the constant part memcpy(apdu, apdu_mse_set_at_start, sizeof(apdu_mse_set_at_start)); // type: OID apdu[5] = 0x80; // length of the OID apdu[6] = sizeof(pace_version_info.oid); // copy the OID memcpy(apdu + 7, pace_version_info.oid, sizeof(pace_version_info.oid)); // type: password apdu[17] = 0x83; // length: 1 apdu[18] = 1; // password apdu[19] = password; // if standardized domain parameters are used, copy the ID if (pace_version_info.parameter_id != 0) { apdu_length += 3; // type: domain parameter apdu[20] = 0x84; // length: 1 apdu[21] = 1; // copy the parameter ID apdu[22] = pace_version_info.parameter_id; } // now set Lc to the actual length apdu[4] = apdu_length - 5; // send it uint8_t response_apdu[6]; int send_return = iso14_apdu(apdu, apdu_length, response_apdu); // check if the command succeeded if (send_return != 6 || response_apdu[send_return - 4] != 0x90 || response_apdu[send_return - 3] != 0x00) { return 1; } return 0; } //----------------------------------------------------------------------------- // Set up a communication channel (Card Select, PPS) // Returns 0 on success or a non-zero error code on failure //----------------------------------------------------------------------------- int EPA_Setup() { // return code int return_code = 0; // card UID uint8_t uid[8]; // card select information iso14a_card_select_t card_select_info; // power up the field iso14443a_setup(); // select the card return_code = iso14443a_select_card(uid, &card_select_info, NULL); if (return_code != 1) { return 1; } // send the PPS request ReaderTransmit((uint8_t *)pps, sizeof(pps)); uint8_t pps_response[3]; return_code = ReaderReceive(pps_response); if (return_code != 3 || pps_response[0] != 0xD0) { return return_code == 0 ? 2 : return_code; } return 0; } ================================================ FILE: TamagotchiFriends/proxmark/armsrc/epa.h ================================================ //----------------------------------------------------------------------------- // Frederik Möllers - August 2012 // // This code is licensed to you under the terms of the GNU GPL, version 2 or, // at your option, any later version. See the LICENSE.txt file for the text of // the license. //----------------------------------------------------------------------------- // Routines to support the German eletronic "Personalausweis" (ID card) //----------------------------------------------------------------------------- #ifndef __EPA_H #define __EPA_H // this struct is used by EPA_Parse_CardAccess and contains info about the // PACE protocol supported by the chip typedef struct { uint8_t oid[10]; uint8_t version; uint8_t parameter_id; } pace_version_info_t; // note: EPA_PACE_GetNonce is declared in apps.h // general functions void EPA_Finish(); size_t EPA_Parse_CardAccess(uint8_t *data, size_t length, pace_version_info_t *pace_info); int EPA_Read_CardAccess(uint8_t *buffer, size_t max_length); int EPA_Setup(); // PACE related functions int EPA_PACE_MSE_Set_AT(pace_version_info_t pace_version_info, uint8_t password); int EPA_PACE_Get_Nonce(uint8_t requested_length, uint8_t *nonce); #endif /* __EPA_H */ ================================================ FILE: TamagotchiFriends/proxmark/armsrc/fonts.c ================================================ //----------------------------------------------------------------------------- // This code is licensed to you under the terms of the GNU GPL, version 2 or, // at your option, any later version. See the LICENSE.txt file for the text of // the license. //----------------------------------------------------------------------------- // Fonts for the LCD //----------------------------------------------------------------------------- const char FONT6x8[97][8] = { {0x06,0x08,0x08,0x00,0x00,0x00,0x00,0x00}, // columns, rows, bytes per char {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // space {0x20,0x20,0x20,0x20,0x20,0x00,0x20,0x00}, // ! {0x50,0x50,0x50,0x00,0x00,0x00,0x00,0x00}, // " {0x50,0x50,0xF8,0x50,0xF8,0x50,0x50,0x00}, // # {0x20,0x78,0xA0,0x70,0x28,0xF0,0x20,0x00}, // $ {0xC0,0xC8,0x10,0x20,0x40,0x98,0x18,0x00}, // % {0x40,0xA0,0xA0,0x40,0xA8,0x90,0x68,0x00}, // & {0x30,0x30,0x20,0x40,0x00,0x00,0x00,0x00}, // ' {0x10,0x20,0x40,0x40,0x40,0x20,0x10,0x00}, // ( {0x40,0x20,0x10,0x10,0x10,0x20,0x40,0x00}, // ) {0x00,0x20,0xA8,0x70,0x70,0xA8,0x20,0x00}, // * {0x00,0x20,0x20,0xF8,0x20,0x20,0x00,0x00}, // + {0x00,0x00,0x00,0x00,0x30,0x30,0x20,0x40}, // , {0x00,0x00,0x00,0xF8,0x00,0x00,0x00,0x00}, // - {0x00,0x00,0x00,0x00,0x00,0x30,0x30,0x00}, // . {0x00,0x08,0x10,0x20,0x40,0x80,0x00,0x00}, // / {0x70,0x88,0x88,0xA8,0x88,0x88,0x70,0x00}, // 0 {0x20,0x60,0x20,0x20,0x20,0x20,0x70,0x00}, // 1 {0x70,0x88,0x08,0x70,0x80,0x80,0xF8,0x00}, // 2 {0xF8,0x08,0x10,0x30,0x08,0x88,0x70,0x00}, // 3 {0x10,0x30,0x50,0x90,0xF8,0x10,0x10,0x00}, // 4 {0xF8,0x80,0xF0,0x08,0x08,0x88,0x70,0x00}, // 5 {0x38,0x40,0x80,0xF0,0x88,0x88,0x70,0x00}, // 6 {0xF8,0x08,0x08,0x10,0x20,0x40,0x80,0x00}, // 7 {0x70,0x88,0x88,0x70,0x88,0x88,0x70,0x00}, // 8 {0x70,0x88,0x88,0x78,0x08,0x10,0xE0,0x00}, // 9 {0x00,0x00,0x20,0x00,0x20,0x00,0x00,0x00}, // : {0x00,0x00,0x20,0x00,0x20,0x20,0x40,0x00}, // ; {0x08,0x10,0x20,0x40,0x20,0x10,0x08,0x00}, // < {0x00,0x00,0xF8,0x00,0xF8,0x00,0x00,0x00}, // = {0x40,0x20,0x10,0x08,0x10,0x20,0x40,0x00}, // > {0x70,0x88,0x08,0x30,0x20,0x00,0x20,0x00}, // ? {0x70,0x88,0xA8,0xB8,0xB0,0x80,0x78,0x00}, // @ {0x20,0x50,0x88,0x88,0xF8,0x88,0x88,0x00}, // A {0xF0,0x88,0x88,0xF0,0x88,0x88,0xF0,0x00}, // B {0x70,0x88,0x80,0x80,0x80,0x88,0x70,0x00}, // C {0xF0,0x88,0x88,0x88,0x88,0x88,0xF0,0x00}, // D {0xF8,0x80,0x80,0xF0,0x80,0x80,0xF8,0x00}, // E {0xF8,0x80,0x80,0xF0,0x80,0x80,0x80,0x00}, // F {0x78,0x88,0x80,0x80,0x98,0x88,0x78,0x00}, // G {0x88,0x88,0x88,0xF8,0x88,0x88,0x88,0x00}, // H {0x70,0x20,0x20,0x20,0x20,0x20,0x70,0x00}, // I {0x38,0x10,0x10,0x10,0x10,0x90,0x60,0x00}, // J {0x88,0x90,0xA0,0xC0,0xA0,0x90,0x88,0x00}, // K {0x80,0x80,0x80,0x80,0x80,0x80,0xF8,0x00}, // L {0x88,0xD8,0xA8,0xA8,0xA8,0x88,0x88,0x00}, // M {0x88,0x88,0xC8,0xA8,0x98,0x88,0x88,0x00}, // N {0x70,0x88,0x88,0x88,0x88,0x88,0x70,0x00}, // O {0xF0,0x88,0x88,0xF0,0x80,0x80,0x80,0x00}, // P {0x70,0x88,0x88,0x88,0xA8,0x90,0x68,0x00}, // Q {0xF0,0x88,0x88,0xF0,0xA0,0x90,0x88,0x00}, // R {0x70,0x88,0x80,0x70,0x08,0x88,0x70,0x00}, // S {0xF8,0xA8,0x20,0x20,0x20,0x20,0x20,0x00}, // T {0x88,0x88,0x88,0x88,0x88,0x88,0x70,0x00}, // U {0x88,0x88,0x88,0x88,0x88,0x50,0x20,0x00}, // V {0x88,0x88,0x88,0xA8,0xA8,0xA8,0x50,0x00}, // W {0x88,0x88,0x50,0x20,0x50,0x88,0x88,0x00}, // X {0x88,0x88,0x50,0x20,0x20,0x20,0x20,0x00}, // Y {0xF8,0x08,0x10,0x70,0x40,0x80,0xF8,0x00}, // Z {0x78,0x40,0x40,0x40,0x40,0x40,0x78,0x00}, // [ {0x00,0x80,0x40,0x20,0x10,0x08,0x00,0x00}, // backslash {0x78,0x08,0x08,0x08,0x08,0x08,0x78,0x00}, // ] {0x20,0x50,0x88,0x00,0x00,0x00,0x00,0x00}, // ^ {0x00,0x00,0x00,0x00,0x00,0x00,0xF8,0x00}, // _ {0x60,0x60,0x20,0x10,0x00,0x00,0x00,0x00}, // ` {0x00,0x00,0x60,0x10,0x70,0x90,0x78,0x00}, // a {0x80,0x80,0xB0,0xC8,0x88,0xC8,0xB0,0x00}, // b {0x00,0x00,0x70,0x88,0x80,0x88,0x70,0x00}, // c {0x08,0x08,0x68,0x98,0x88,0x98,0x68,0x00}, // d {0x00,0x00,0x70,0x88,0xF8,0x80,0x70,0x00}, // e {0x10,0x28,0x20,0x70,0x20,0x20,0x20,0x00}, // f {0x00,0x00,0x70,0x98,0x98,0x68,0x08,0x70}, // g {0x80,0x80,0xB0,0xC8,0x88,0x88,0x88,0x00}, // h {0x20,0x00,0x60,0x20,0x20,0x20,0x70,0x00}, // i {0x10,0x00,0x10,0x10,0x10,0x90,0x60,0x00}, // j {0x80,0x80,0x90,0xA0,0xC0,0xA0,0x90,0x00}, // k {0x60,0x20,0x20,0x20,0x20,0x20,0x70,0x00}, // l {0x00,0x00,0xD0,0xA8,0xA8,0xA8,0xA8,0x00}, // m {0x00,0x00,0xB0,0xC8,0x88,0x88,0x88,0x00}, // n {0x00,0x00,0x70,0x88,0x88,0x88,0x70,0x00}, // o {0x00,0x00,0xB0,0xC8,0xC8,0xB0,0x80,0x80}, // p {0x00,0x00,0x68,0x98,0x98,0x68,0x08,0x08}, // q {0x00,0x00,0xB0,0xC8,0x80,0x80,0x80,0x00}, // r {0x00,0x00,0x78,0x80,0x70,0x08,0xF0,0x00}, // s {0x20,0x20,0xF8,0x20,0x20,0x28,0x10,0x00}, // t {0x00,0x00,0x88,0x88,0x88,0x98,0x68,0x00}, // u {0x00,0x00,0x88,0x88,0x88,0x50,0x20,0x00}, // v {0x00,0x00,0x88,0x88,0xA8,0xA8,0x50,0x00}, // w {0x00,0x00,0x88,0x50,0x20,0x50,0x88,0x00}, // x {0x00,0x00,0x88,0x88,0x78,0x08,0x88,0x70}, // y {0x00,0x00,0xF8,0x10,0x20,0x40,0xF8,0x00}, // z {0x10,0x20,0x20,0x40,0x20,0x20,0x10,0x00}, // { {0x20,0x20,0x20,0x00,0x20,0x20,0x20,0x00}, // | {0x40,0x20,0x20,0x10,0x20,0x20,0x40,0x00}, // } {0x40,0xA8,0x10,0x00,0x00,0x00,0x00,0x00}, // ~ {0x70,0xD8,0xD8,0x70,0x00,0x00,0x00,0x00} // DEL }; /* const char FONT8x8F[97][8] = { {0x08,0x08,0x08,0x00,0x00,0x00,0x00,0x00}, // columns, rows, bytes per char {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // space {0x30,0x78,0x78,0x30,0x30,0x00,0x30,0x00}, // ! {0x6C,0x6C,0x6C,0x00,0x00,0x00,0x00,0x00}, // " {0x6C,0x6C,0xFE,0x6C,0xFE,0x6C,0x6C,0x00}, // # {0x18,0x3E,0x60,0x3C,0x06,0x7C,0x18,0x00}, // $ {0x00,0x63,0x66,0x0C,0x18,0x33,0x63,0x00}, // % {0x1C,0x36,0x1C,0x3B,0x6E,0x66,0x3B,0x00}, // & {0x30,0x30,0x60,0x00,0x00,0x00,0x00,0x00}, // ' {0x0C,0x18,0x30,0x30,0x30,0x18,0x0C,0x00}, // ( {0x30,0x18,0x0C,0x0C,0x0C,0x18,0x30,0x00}, // ) {0x00,0x66,0x3C,0xFF,0x3C,0x66,0x00,0x00}, // * {0x00,0x30,0x30,0xFC,0x30,0x30,0x00,0x00}, // + {0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x30}, // , {0x00,0x00,0x00,0x7E,0x00,0x00,0x00,0x00}, // - {0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00}, // . {0x03,0x06,0x0C,0x18,0x30,0x60,0x40,0x00}, // / {0x3E,0x63,0x63,0x6B,0x63,0x63,0x3E,0x00}, // 0 {0x18,0x38,0x58,0x18,0x18,0x18,0x7E,0x00}, // 1 {0x3C,0x66,0x06,0x1C,0x30,0x66,0x7E,0x00}, // 2 {0x3C,0x66,0x06,0x1C,0x06,0x66,0x3C,0x00}, // 3 {0x0E,0x1E,0x36,0x66,0x7F,0x06,0x0F,0x00}, // 4 {0x7E,0x60,0x7C,0x06,0x06,0x66,0x3C,0x00}, // 5 {0x1C,0x30,0x60,0x7C,0x66,0x66,0x3C,0x00}, // 6 {0x7E,0x66,0x06,0x0C,0x18,0x18,0x18,0x00}, // 7 {0x3C,0x66,0x66,0x3C,0x66,0x66,0x3C,0x00}, // 8 {0x3C,0x66,0x66,0x3E,0x06,0x0C,0x38,0x00}, // 9 {0x00,0x18,0x18,0x00,0x00,0x18,0x18,0x00}, // : {0x00,0x18,0x18,0x00,0x00,0x18,0x18,0x30}, // ; {0x0C,0x18,0x30,0x60,0x30,0x18,0x0C,0x00}, // < {0x00,0x00,0x7E,0x00,0x00,0x7E,0x00,0x00}, // = {0x30,0x18,0x0C,0x06,0x0C,0x18,0x30,0x00}, // > {0x3C,0x66,0x06,0x0C,0x18,0x00,0x18,0x00}, // ? {0x3E,0x63,0x6F,0x69,0x6F,0x60,0x3E,0x00}, // @ {0x18,0x3C,0x66,0x66,0x7E,0x66,0x66,0x00}, // A {0x7E,0x33,0x33,0x3E,0x33,0x33,0x7E,0x00}, // B {0x1E,0x33,0x60,0x60,0x60,0x33,0x1E,0x00}, // C {0x7C,0x36,0x33,0x33,0x33,0x36,0x7C,0x00}, // D {0x7F,0x31,0x34,0x3C,0x34,0x31,0x7F,0x00}, // E {0x7F,0x31,0x34,0x3C,0x34,0x30,0x78,0x00}, // F {0x1E,0x33,0x60,0x60,0x67,0x33,0x1F,0x00}, // G {0x66,0x66,0x66,0x7E,0x66,0x66,0x66,0x00}, // H {0x3C,0x18,0x18,0x18,0x18,0x18,0x3C,0x00}, // I {0x0F,0x06,0x06,0x06,0x66,0x66,0x3C,0x00}, // J {0x73,0x33,0x36,0x3C,0x36,0x33,0x73,0x00}, // K {0x78,0x30,0x30,0x30,0x31,0x33,0x7F,0x00}, // L {0x63,0x77,0x7F,0x7F,0x6B,0x63,0x63,0x00}, // M {0x63,0x73,0x7B,0x6F,0x67,0x63,0x63,0x00}, // N {0x3E,0x63,0x63,0x63,0x63,0x63,0x3E,0x00}, // O {0x7E,0x33,0x33,0x3E,0x30,0x30,0x78,0x00}, // P {0x3C,0x66,0x66,0x66,0x6E,0x3C,0x0E,0x00}, // Q {0x7E,0x33,0x33,0x3E,0x36,0x33,0x73,0x00}, // R {0x3C,0x66,0x30,0x18,0x0C,0x66,0x3C,0x00}, // S {0x7E,0x5A,0x18,0x18,0x18,0x18,0x3C,0x00}, // T {0x66,0x66,0x66,0x66,0x66,0x66,0x7E,0x00}, // U {0x66,0x66,0x66,0x66,0x66,0x3C,0x18,0x00}, // V {0x63,0x63,0x63,0x6B,0x7F,0x77,0x63,0x00}, // W {0x63,0x63,0x36,0x1C,0x1C,0x36,0x63,0x00}, // X {0x66,0x66,0x66,0x3C,0x18,0x18,0x3C,0x00}, // Y {0x7F,0x63,0x46,0x0C,0x19,0x33,0x7F,0x00}, // Z {0x3C,0x30,0x30,0x30,0x30,0x30,0x3C,0x00}, // [ {0x60,0x30,0x18,0x0C,0x06,0x03,0x01,0x00}, // backslash {0x3C,0x0C,0x0C,0x0C,0x0C,0x0C,0x3C,0x00}, // ] {0x08,0x1C,0x36,0x63,0x00,0x00,0x00,0x00}, // ^ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF}, // _ {0x18,0x18,0x0C,0x00,0x00,0x00,0x00,0x00}, // ` {0x00,0x00,0x3C,0x06,0x3E,0x66,0x3B,0x00}, // a {0x70,0x30,0x3E,0x33,0x33,0x33,0x6E,0x00}, // b {0x00,0x00,0x3C,0x66,0x60,0x66,0x3C,0x00}, // c {0x0E,0x06,0x3E,0x66,0x66,0x66,0x3B,0x00}, // d {0x00,0x00,0x3C,0x66,0x7E,0x60,0x3C,0x00}, // e {0x1C,0x36,0x30,0x78,0x30,0x30,0x78,0x00}, // f {0x00,0x00,0x3B,0x66,0x66,0x3E,0x06,0x7C}, // g {0x70,0x30,0x36,0x3B,0x33,0x33,0x73,0x00}, // h {0x18,0x00,0x38,0x18,0x18,0x18,0x3C,0x00}, // i {0x06,0x00,0x06,0x06,0x06,0x66,0x66,0x3C}, // j {0x70,0x30,0x33,0x36,0x3C,0x36,0x73,0x00}, // k {0x38,0x18,0x18,0x18,0x18,0x18,0x3C,0x00}, // l {0x00,0x00,0x66,0x7F,0x7F,0x6B,0x63,0x00}, // m {0x00,0x00,0x7C,0x66,0x66,0x66,0x66,0x00}, // n {0x00,0x00,0x3C,0x66,0x66,0x66,0x3C,0x00}, // o {0x00,0x00,0x6E,0x33,0x33,0x3E,0x30,0x78}, // p {0x00,0x00,0x3B,0x66,0x66,0x3E,0x06,0x0F}, // q {0x00,0x00,0x6E,0x3B,0x33,0x30,0x78,0x00}, // r {0x00,0x00,0x3E,0x60,0x3C,0x06,0x7C,0x00}, // s {0x08,0x18,0x3E,0x18,0x18,0x1A,0x0C,0x00}, // t {0x00,0x00,0x66,0x66,0x66,0x66,0x3B,0x00}, // u {0x00,0x00,0x66,0x66,0x66,0x3C,0x18,0x00}, // v {0x00,0x00,0x63,0x6B,0x7F,0x7F,0x36,0x00}, // w {0x00,0x00,0x63,0x36,0x1C,0x36,0x63,0x00}, // x {0x00,0x00,0x66,0x66,0x66,0x3E,0x06,0x7C}, // y {0x00,0x00,0x7E,0x4C,0x18,0x32,0x7E,0x00}, // z {0x0E,0x18,0x18,0x70,0x18,0x18,0x0E,0x00}, // { {0x0C,0x0C,0x0C,0x00,0x0C,0x0C,0x0C,0x00}, // | {0x70,0x18,0x18,0x0E,0x18,0x18,0x70,0x00}, // } {0x3B,0x6E,0x00,0x00,0x00,0x00,0x00,0x00}, // ~ {0x1C,0x36,0x36,0x1C,0x00,0x00,0x00,0x00} // DEL }; const char FONT8x16[97][16] = { {0x08,0x10,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // columns, rows, bytes per char {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // space {0x00,0x00,0x18,0x3C,0x3C,0x3C,0x18,0x18,0x18,0x00,0x18,0x18,0x00,0x00,0x00,0x00}, // ! {0x00,0x63,0x63,0x63,0x22,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // " {0x00,0x00,0x00,0x36,0x36,0x7F,0x36,0x36,0x36,0x7F,0x36,0x36,0x00,0x00,0x00,0x00}, // # {0x0C,0x0C,0x3E,0x63,0x61,0x60,0x3E,0x03,0x03,0x43,0x63,0x3E,0x0C,0x0C,0x00,0x00}, // $ {0x00,0x00,0x00,0x00,0x00,0x61,0x63,0x06,0x0C,0x18,0x33,0x63,0x00,0x00,0x00,0x00}, // % {0x00,0x00,0x00,0x1C,0x36,0x36,0x1C,0x3B,0x6E,0x66,0x66,0x3B,0x00,0x00,0x00,0x00}, // & {0x00,0x30,0x30,0x30,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // ' {0x00,0x00,0x0C,0x18,0x18,0x30,0x30,0x30,0x30,0x18,0x18,0x0C,0x00,0x00,0x00,0x00}, // ( {0x00,0x00,0x18,0x0C,0x0C,0x06,0x06,0x06,0x06,0x0C,0x0C,0x18,0x00,0x00,0x00,0x00}, // ) {0x00,0x00,0x00,0x00,0x42,0x66,0x3C,0xFF,0x3C,0x66,0x42,0x00,0x00,0x00,0x00,0x00}, // * {0x00,0x00,0x00,0x00,0x18,0x18,0x18,0xFF,0x18,0x18,0x18,0x00,0x00,0x00,0x00,0x00}, // + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x18,0x30,0x00,0x00}, // , {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // - {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x00}, // . {0x00,0x00,0x01,0x03,0x07,0x0E,0x1C,0x38,0x70,0xE0,0xC0,0x80,0x00,0x00,0x00,0x00}, // / {0x00,0x00,0x3E,0x63,0x63,0x63,0x6B,0x6B,0x63,0x63,0x63,0x3E,0x00,0x00,0x00,0x00}, // 0 {0x00,0x00,0x0C,0x1C,0x3C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x3F,0x00,0x00,0x00,0x00}, // 1 {0x00,0x00,0x3E,0x63,0x03,0x06,0x0C,0x18,0x30,0x61,0x63,0x7F,0x00,0x00,0x00,0x00}, // 2 {0x00,0x00,0x3E,0x63,0x03,0x03,0x1E,0x03,0x03,0x03,0x63,0x3E,0x00,0x00,0x00,0x00}, // 3 {0x00,0x00,0x06,0x0E,0x1E,0x36,0x66,0x66,0x7F,0x06,0x06,0x0F,0x00,0x00,0x00,0x00}, // 4 {0x00,0x00,0x7F,0x60,0x60,0x60,0x7E,0x03,0x03,0x63,0x73,0x3E,0x00,0x00,0x00,0x00}, // 5 {0x00,0x00,0x1C,0x30,0x60,0x60,0x7E,0x63,0x63,0x63,0x63,0x3E,0x00,0x00,0x00,0x00}, // 6 {0x00,0x00,0x7F,0x63,0x03,0x06,0x06,0x0C,0x0C,0x18,0x18,0x18,0x00,0x00,0x00,0x00}, // 7 {0x00,0x00,0x3E,0x63,0x63,0x63,0x3E,0x63,0x63,0x63,0x63,0x3E,0x00,0x00,0x00,0x00}, // 8 {0x00,0x00,0x3E,0x63,0x63,0x63,0x63,0x3F,0x03,0x03,0x06,0x3C,0x00,0x00,0x00,0x00}, // 9 {0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x00}, // : {0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x18,0x18,0x18,0x30,0x00,0x00}, // ; {0x00,0x00,0x00,0x06,0x0C,0x18,0x30,0x60,0x30,0x18,0x0C,0x06,0x00,0x00,0x00,0x00}, // < {0x00,0x00,0x00,0x00,0x00,0x00,0x7E,0x00,0x00,0x7E,0x00,0x00,0x00,0x00,0x00,0x00}, // = {0x00,0x00,0x00,0x60,0x30,0x18,0x0C,0x06,0x0C,0x18,0x30,0x60,0x00,0x00,0x00,0x00}, // > {0x00,0x00,0x3E,0x63,0x63,0x06,0x0C,0x0C,0x0C,0x00,0x0C,0x0C,0x00,0x00,0x00,0x00}, // ? {0x00,0x00,0x3E,0x63,0x63,0x6F,0x6B,0x6B,0x6E,0x60,0x60,0x3E,0x00,0x00,0x00,0x00}, // @ {0x00,0x00,0x08,0x1C,0x36,0x63,0x63,0x63,0x7F,0x63,0x63,0x63,0x00,0x00,0x00,0x00}, // A {0x00,0x00,0x7E,0x33,0x33,0x33,0x3E,0x33,0x33,0x33,0x33,0x7E,0x00,0x00,0x00,0x00}, // B {0x00,0x00,0x1E,0x33,0x61,0x60,0x60,0x60,0x60,0x61,0x33,0x1E,0x00,0x00,0x00,0x00}, // C {0x00,0x00,0x7C,0x36,0x33,0x33,0x33,0x33,0x33,0x33,0x36,0x7C,0x00,0x00,0x00,0x00}, // D {0x00,0x00,0x7F,0x33,0x31,0x34,0x3C,0x34,0x30,0x31,0x33,0x7F,0x00,0x00,0x00,0x00}, // E {0x00,0x00,0x7F,0x33,0x31,0x34,0x3C,0x34,0x30,0x30,0x30,0x78,0x00,0x00,0x00,0x00}, // F {0x00,0x00,0x1E,0x33,0x61,0x60,0x60,0x6F,0x63,0x63,0x37,0x1D,0x00,0x00,0x00,0x00}, // G {0x00,0x00,0x63,0x63,0x63,0x63,0x7F,0x63,0x63,0x63,0x63,0x63,0x00,0x00,0x00,0x00}, // H {0x00,0x00,0x3C,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x3C,0x00,0x00,0x00,0x00}, // I {0x00,0x00,0x0F,0x06,0x06,0x06,0x06,0x06,0x06,0x66,0x66,0x3C,0x00,0x00,0x00,0x00}, // J {0x00,0x00,0x73,0x33,0x36,0x36,0x3C,0x36,0x36,0x33,0x33,0x73,0x00,0x00,0x00,0x00}, // K {0x00,0x00,0x78,0x30,0x30,0x30,0x30,0x30,0x30,0x31,0x33,0x7F,0x00,0x00,0x00,0x00}, // L {0x00,0x00,0x63,0x77,0x7F,0x6B,0x63,0x63,0x63,0x63,0x63,0x63,0x00,0x00,0x00,0x00}, // M {0x00,0x00,0x63,0x63,0x73,0x7B,0x7F,0x6F,0x67,0x63,0x63,0x63,0x00,0x00,0x00,0x00}, // N {0x00,0x00,0x1C,0x36,0x63,0x63,0x63,0x63,0x63,0x63,0x36,0x1C,0x00,0x00,0x00,0x00}, // O {0x00,0x00,0x7E,0x33,0x33,0x33,0x3E,0x30,0x30,0x30,0x30,0x78,0x00,0x00,0x00,0x00}, // P {0x00,0x00,0x3E,0x63,0x63,0x63,0x63,0x63,0x63,0x6B,0x6F,0x3E,0x06,0x07,0x00,0x00}, // Q {0x00,0x00,0x7E,0x33,0x33,0x33,0x3E,0x36,0x36,0x33,0x33,0x73,0x00,0x00,0x00,0x00}, // R {0x00,0x00,0x3E,0x63,0x63,0x30,0x1C,0x06,0x03,0x63,0x63,0x3E,0x00,0x00,0x00,0x00}, // S {0x00,0x00,0xFF,0xDB,0x99,0x18,0x18,0x18,0x18,0x18,0x18,0x3C,0x00,0x00,0x00,0x00}, // T {0x00,0x00,0x63,0x63,0x63,0x63,0x63,0x63,0x63,0x63,0x63,0x3E,0x00,0x00,0x00,0x00}, // U {0x00,0x00,0x63,0x63,0x63,0x63,0x63,0x63,0x63,0x36,0x1C,0x08,0x00,0x00,0x00,0x00}, // V {0x00,0x00,0x63,0x63,0x63,0x63,0x63,0x6B,0x6B,0x7F,0x36,0x36,0x00,0x00,0x00,0x00}, // W {0x00,0x00,0xC3,0xC3,0x66,0x3C,0x18,0x18,0x3C,0x66,0xC3,0xC3,0x00,0x00,0x00,0x00}, // X {0x00,0x00,0xC3,0xC3,0xC3,0x66,0x3C,0x18,0x18,0x18,0x18,0x3C,0x00,0x00,0x00,0x00}, // Y {0x00,0x00,0x7F,0x63,0x43,0x06,0x0C,0x18,0x30,0x61,0x63,0x7F,0x00,0x00,0x00,0x00}, // Z {0x00,0x00,0x3C,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x3C,0x00,0x00,0x00,0x00}, // [ {0x00,0x00,0x80,0xC0,0xE0,0x70,0x38,0x1C,0x0E,0x07,0x03,0x01,0x00,0x00,0x00,0x00}, // backslash {0x00,0x00,0x3C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x3C,0x00,0x00,0x00,0x00}, // ] {0x08,0x1C,0x36,0x63,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // ^ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00}, // _ {0x18,0x18,0x0C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // ` {0x00,0x00,0x00,0x00,0x00,0x3C,0x46,0x06,0x3E,0x66,0x66,0x3B,0x00,0x00,0x00,0x00}, // a {0x00,0x00,0x70,0x30,0x30,0x3C,0x36,0x33,0x33,0x33,0x33,0x6E,0x00,0x00,0x00,0x00}, // b {0x00,0x00,0x00,0x00,0x00,0x3E,0x63,0x60,0x60,0x60,0x63,0x3E,0x00,0x00,0x00,0x00}, // c {0x00,0x00,0x0E,0x06,0x06,0x1E,0x36,0x66,0x66,0x66,0x66,0x3B,0x00,0x00,0x00,0x00}, // d {0x00,0x00,0x00,0x00,0x00,0x3E,0x63,0x63,0x7E,0x60,0x63,0x3E,0x00,0x00,0x00,0x00}, // e {0x00,0x00,0x1C,0x36,0x32,0x30,0x7C,0x30,0x30,0x30,0x30,0x78,0x00,0x00,0x00,0x00}, // f {0x00,0x00,0x00,0x00,0x00,0x3B,0x66,0x66,0x66,0x66,0x3E,0x06,0x66,0x3C,0x00,0x00}, // g {0x00,0x00,0x70,0x30,0x30,0x36,0x3B,0x33,0x33,0x33,0x33,0x73,0x00,0x00,0x00,0x00}, // h {0x00,0x00,0x0C,0x0C,0x00,0x1C,0x0C,0x0C,0x0C,0x0C,0x0C,0x1E,0x00,0x00,0x00,0x00}, // i {0x00,0x00,0x06,0x06,0x00,0x0E,0x06,0x06,0x06,0x06,0x06,0x66,0x66,0x3C,0x00,0x00}, // j {0x00,0x00,0x70,0x30,0x30,0x33,0x33,0x36,0x3C,0x36,0x33,0x73,0x00,0x00,0x00,0x00}, // k {0x00,0x00,0x1C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x1E,0x00,0x00,0x00,0x00}, // l {0x00,0x00,0x00,0x00,0x00,0x6E,0x7F,0x6B,0x6B,0x6B,0x6B,0x6B,0x00,0x00,0x00,0x00}, // m {0x00,0x00,0x00,0x00,0x00,0x6E,0x33,0x33,0x33,0x33,0x33,0x33,0x00,0x00,0x00,0x00}, // n {0x00,0x00,0x00,0x00,0x00,0x3E,0x63,0x63,0x63,0x63,0x63,0x3E,0x00,0x00,0x00,0x00}, // o {0x00,0x00,0x00,0x00,0x00,0x6E,0x33,0x33,0x33,0x33,0x3E,0x30,0x30,0x78,0x00,0x00}, // p {0x00,0x00,0x00,0x00,0x00,0x3B,0x66,0x66,0x66,0x66,0x3E,0x06,0x06,0x0F,0x00,0x00}, // q {0x00,0x00,0x00,0x00,0x00,0x6E,0x3B,0x33,0x30,0x30,0x30,0x78,0x00,0x00,0x00,0x00}, // r {0x00,0x00,0x00,0x00,0x00,0x3E,0x63,0x38,0x0E,0x03,0x63,0x3E,0x00,0x00,0x00,0x00}, // s {0x00,0x00,0x08,0x18,0x18,0x7E,0x18,0x18,0x18,0x18,0x1B,0x0E,0x00,0x00,0x00,0x00}, // t {0x00,0x00,0x00,0x00,0x00,0x66,0x66,0x66,0x66,0x66,0x66,0x3B,0x00,0x00,0x00,0x00}, // u {0x00,0x00,0x00,0x00,0x00,0x63,0x63,0x36,0x36,0x1C,0x1C,0x08,0x00,0x00,0x00,0x00}, // v {0x00,0x00,0x00,0x00,0x00,0x63,0x63,0x63,0x6B,0x6B,0x7F,0x36,0x00,0x00,0x00,0x00}, // w {0x00,0x00,0x00,0x00,0x00,0x63,0x36,0x1C,0x1C,0x1C,0x36,0x63,0x00,0x00,0x00,0x00}, // x {0x00,0x00,0x00,0x00,0x00,0x63,0x63,0x63,0x63,0x63,0x3F,0x03,0x06,0x3C,0x00,0x00}, // y {0x00,0x00,0x00,0x00,0x00,0x7F,0x66,0x0C,0x18,0x30,0x63,0x7F,0x00,0x00,0x00,0x00}, // z {0x00,0x00,0x0E,0x18,0x18,0x18,0x70,0x18,0x18,0x18,0x18,0x0E,0x00,0x00,0x00,0x00}, // { {0x00,0x00,0x18,0x18,0x18,0x18,0x18,0x00,0x18,0x18,0x18,0x18,0x18,0x00,0x00,0x00}, // | {0x00,0x00,0x70,0x18,0x18,0x18,0x0E,0x18,0x18,0x18,0x18,0x70,0x00,0x00,0x00,0x00}, // } {0x00,0x00,0x3B,0x6E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // ~ {0x00,0x70,0xD8,0xD8,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00} // DEL }; */ ================================================ FILE: TamagotchiFriends/proxmark/armsrc/fonts.h ================================================ //----------------------------------------------------------------------------- // This code is licensed to you under the terms of the GNU GPL, version 2 or, // at your option, any later version. See the LICENSE.txt file for the text of // the license. //----------------------------------------------------------------------------- // Fonts for the LCD //----------------------------------------------------------------------------- #ifndef __FONTS_H #define __FONTS_H extern const char FONT6x8[97][8]; extern const char FONT8x8F[97][8]; extern const char FONT8x16[97][16]; #endif ================================================ FILE: TamagotchiFriends/proxmark/armsrc/fpgaloader.c ================================================ //----------------------------------------------------------------------------- // Jonathan Westhues, April 2006 // // This code is licensed to you under the terms of the GNU GPL, version 2 or, // at your option, any later version. See the LICENSE.txt file for the text of // the license. //----------------------------------------------------------------------------- // Routines to load the FPGA image, and then to configure the FPGA's major // mode once it is configured. //----------------------------------------------------------------------------- #include "proxmark3.h" #include "apps.h" #include "util.h" #include "string.h" //----------------------------------------------------------------------------- // Set up the Serial Peripheral Interface as master // Used to write the FPGA config word // May also be used to write to other SPI attached devices like an LCD //----------------------------------------------------------------------------- void SetupSpi(int mode) { // PA10 -> SPI_NCS2 chip select (LCD) // PA11 -> SPI_NCS0 chip select (FPGA) // PA12 -> SPI_MISO Master-In Slave-Out // PA13 -> SPI_MOSI Master-Out Slave-In // PA14 -> SPI_SPCK Serial Clock // Disable PIO control of the following pins, allows use by the SPI peripheral AT91C_BASE_PIOA->PIO_PDR = GPIO_NCS0 | GPIO_NCS2 | GPIO_MISO | GPIO_MOSI | GPIO_SPCK; AT91C_BASE_PIOA->PIO_ASR = GPIO_NCS0 | GPIO_MISO | GPIO_MOSI | GPIO_SPCK; AT91C_BASE_PIOA->PIO_BSR = GPIO_NCS2; //enable the SPI Peripheral clock AT91C_BASE_PMC->PMC_PCER = (1<SPI_CR = AT91C_SPI_SPIEN; switch (mode) { case SPI_FPGA_MODE: AT91C_BASE_SPI->SPI_MR = ( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods) (14 << 16) | // Peripheral Chip Select (selects FPGA SPI_NCS0 or PA11) ( 0 << 7) | // Local Loopback Disabled ( 1 << 4) | // Mode Fault Detection disabled ( 0 << 2) | // Chip selects connected directly to peripheral ( 0 << 1) | // Fixed Peripheral Select ( 1 << 0); // Master Mode AT91C_BASE_SPI->SPI_CSR[0] = ( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods) ( 1 << 16) | // Delay Before SPCK (1 MCK period) ( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud ( 8 << 4) | // Bits per Transfer (16 bits) ( 0 << 3) | // Chip Select inactive after transfer ( 1 << 1) | // Clock Phase data captured on leading edge, changes on following edge ( 0 << 0); // Clock Polarity inactive state is logic 0 break; case SPI_LCD_MODE: AT91C_BASE_SPI->SPI_MR = ( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods) (11 << 16) | // Peripheral Chip Select (selects LCD SPI_NCS2 or PA10) ( 0 << 7) | // Local Loopback Disabled ( 1 << 4) | // Mode Fault Detection disabled ( 0 << 2) | // Chip selects connected directly to peripheral ( 0 << 1) | // Fixed Peripheral Select ( 1 << 0); // Master Mode AT91C_BASE_SPI->SPI_CSR[2] = ( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods) ( 1 << 16) | // Delay Before SPCK (1 MCK period) ( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud ( 1 << 4) | // Bits per Transfer (9 bits) ( 0 << 3) | // Chip Select inactive after transfer ( 1 << 1) | // Clock Phase data captured on leading edge, changes on following edge ( 0 << 0); // Clock Polarity inactive state is logic 0 break; default: // Disable SPI AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIDIS; break; } } //----------------------------------------------------------------------------- // Set up the synchronous serial port, with the one set of options that we // always use when we are talking to the FPGA. Both RX and TX are enabled. //----------------------------------------------------------------------------- void FpgaSetupSsc(void) { // First configure the GPIOs, and get ourselves a clock. AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_FRAME | GPIO_SSC_DIN | GPIO_SSC_DOUT | GPIO_SSC_CLK; AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT; AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_SSC); // Now set up the SSC proper, starting from a known state. AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST; // RX clock comes from TX clock, RX starts when TX starts, data changes // on RX clock rising edge, sampled on falling edge AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1); // 8 bits per transfer, no loopback, MSB first, 1 transfer per sync // pulse, no output sync, start on positive-going edge of sync AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) | AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0); // clock comes from TK pin, no clock output, outputs change on falling // edge of TK, start on rising edge of TF AT91C_BASE_SSC->SSC_TCMR = SSC_CLOCK_MODE_SELECT(2) | SSC_CLOCK_MODE_START(5); // tx framing is the same as the rx framing AT91C_BASE_SSC->SSC_TFMR = AT91C_BASE_SSC->SSC_RFMR; AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN; } //----------------------------------------------------------------------------- // Set up DMA to receive samples from the FPGA. We will use the PDC, with // a single buffer as a circular buffer (so that we just chain back to // ourselves, not to another buffer). The stuff to manipulate those buffers // is in apps.h, because it should be inlined, for speed. //----------------------------------------------------------------------------- bool FpgaSetupSscDma(uint8_t *buf, int len) { if (buf == NULL) { return false; } AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS; AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) buf; AT91C_BASE_PDC_SSC->PDC_RCR = len; AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) buf; AT91C_BASE_PDC_SSC->PDC_RNCR = len; AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN; return true; } static void DownloadFPGA_byte(unsigned char w) { #define SEND_BIT(x) { if(w & (1<PIO_OER = GPIO_FPGA_ON; AT91C_BASE_PIOA->PIO_PER = GPIO_FPGA_ON; HIGH(GPIO_FPGA_ON); // ensure everything is powered on SpinDelay(50); LED_D_ON(); // These pins are inputs AT91C_BASE_PIOA->PIO_ODR = GPIO_FPGA_NINIT | GPIO_FPGA_DONE; // PIO controls the following pins AT91C_BASE_PIOA->PIO_PER = GPIO_FPGA_NINIT | GPIO_FPGA_DONE; // Enable pull-ups AT91C_BASE_PIOA->PIO_PPUER = GPIO_FPGA_NINIT | GPIO_FPGA_DONE; // setup initial logic state HIGH(GPIO_FPGA_NPROGRAM); LOW(GPIO_FPGA_CCLK); LOW(GPIO_FPGA_DIN); // These pins are outputs AT91C_BASE_PIOA->PIO_OER = GPIO_FPGA_NPROGRAM | GPIO_FPGA_CCLK | GPIO_FPGA_DIN; // enter FPGA configuration mode LOW(GPIO_FPGA_NPROGRAM); SpinDelay(50); HIGH(GPIO_FPGA_NPROGRAM); i=100000; // wait for FPGA ready to accept data signal while ((i) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_NINIT ) ) ) { i--; } // crude error indicator, leave both red LEDs on and return if (i==0){ LED_C_ON(); LED_D_ON(); return; } if(bytereversal) { /* This is only supported for uint32_t aligned images */ if( ((int)FpgaImage % sizeof(uint32_t)) == 0 ) { i=0; while(FpgaImageLen-->0) DownloadFPGA_byte(FpgaImage[(i++)^0x3]); /* Explanation of the magic in the above line: * i^0x3 inverts the lower two bits of the integer i, counting backwards * for each 4 byte increment. The generated sequence of (i++)^3 is * 3 2 1 0 7 6 5 4 11 10 9 8 15 14 13 12 etc. pp. */ } } else { while(FpgaImageLen-->0) DownloadFPGA_byte(*FpgaImage++); } // continue to clock FPGA until ready signal goes high i=100000; while ( (i--) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_DONE ) ) ) { HIGH(GPIO_FPGA_CCLK); LOW(GPIO_FPGA_CCLK); } // crude error indicator, leave both red LEDs on and return if (i==0){ LED_C_ON(); LED_D_ON(); return; } LED_D_OFF(); } static char *bitparse_headers_start; static char *bitparse_bitstream_end; static int bitparse_initialized; /* Simple Xilinx .bit parser. The file starts with the fixed opaque byte sequence * 00 09 0f f0 0f f0 0f f0 0f f0 00 00 01 * After that the format is 1 byte section type (ASCII character), 2 byte length * (big endian), bytes content. Except for section 'e' which has 4 bytes * length. */ static const char _bitparse_fixed_header[] = {0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x00, 0x00, 0x01}; static int bitparse_init(void * start_address, void *end_address) { bitparse_initialized = 0; if(memcmp(_bitparse_fixed_header, start_address, sizeof(_bitparse_fixed_header)) != 0) { return 0; /* Not matched */ } else { bitparse_headers_start= ((char*)start_address) + sizeof(_bitparse_fixed_header); bitparse_bitstream_end= (char*)end_address; bitparse_initialized = 1; return 1; } } int bitparse_find_section(char section_name, char **section_start, unsigned int *section_length) { char *pos = bitparse_headers_start; int result = 0; if(!bitparse_initialized) return 0; while(pos < bitparse_bitstream_end) { char current_name = *pos++; unsigned int current_length = 0; if(current_name < 'a' || current_name > 'e') { /* Strange section name, abort */ break; } current_length = 0; switch(current_name) { case 'e': /* Four byte length field */ current_length += (*pos++) << 24; current_length += (*pos++) << 16; default: /* Fall through, two byte length field */ current_length += (*pos++) << 8; current_length += (*pos++) << 0; } if(current_name != 'e' && current_length > 255) { /* Maybe a parse error */ break; } if(current_name == section_name) { /* Found it */ *section_start = pos; *section_length = current_length; result = 1; break; } pos += current_length; /* Skip section */ } return result; } //----------------------------------------------------------------------------- // Find out which FPGA image format is stored in flash, then call DownloadFPGA // with the right parameters to download the image //----------------------------------------------------------------------------- extern char _binary_fpga_bit_start, _binary_fpga_bit_end; void FpgaDownloadAndGo(void) { /* Check for the new flash image format: Should have the .bit file at &_binary_fpga_bit_start */ if(bitparse_init(&_binary_fpga_bit_start, &_binary_fpga_bit_end)) { /* Successfully initialized the .bit parser. Find the 'e' section and * send its contents to the FPGA. */ char *bitstream_start; unsigned int bitstream_length; if(bitparse_find_section('e', &bitstream_start, &bitstream_length)) { DownloadFPGA(bitstream_start, bitstream_length, 0); return; /* All done */ } } /* Fallback for the old flash image format: Check for the magic marker 0xFFFFFFFF * 0xAA995566 at address 0x102000. This is raw bitstream with a size of 336,768 bits * = 10,524 uint32_t, stored as uint32_t e.g. little-endian in memory, but each DWORD * is still to be transmitted in MSBit first order. Set the invert flag to indicate * that the DownloadFPGA function should invert every 4 byte sequence when doing * the bytewise download. */ if( *(uint32_t*)0x102000 == 0xFFFFFFFF && *(uint32_t*)0x102004 == 0xAA995566 ) DownloadFPGA((char*)0x102000, 10524*4, 1); } void FpgaGatherVersion(char *dst, int len) { char *fpga_info; unsigned int fpga_info_len; dst[0] = 0; if(!bitparse_find_section('e', &fpga_info, &fpga_info_len)) { strncat(dst, "FPGA image: legacy image without version information", len-1); } else { strncat(dst, "FPGA image built", len-1); /* USB packets only have 48 bytes data payload, so be terse */ #if 0 if(bitparse_find_section('a', &fpga_info, &fpga_info_len) && fpga_info[fpga_info_len-1] == 0 ) { strncat(dst, " from ", len-1); strncat(dst, fpga_info, len-1); } if(bitparse_find_section('b', &fpga_info, &fpga_info_len) && fpga_info[fpga_info_len-1] == 0 ) { strncat(dst, " for ", len-1); strncat(dst, fpga_info, len-1); } #endif if(bitparse_find_section('c', &fpga_info, &fpga_info_len) && fpga_info[fpga_info_len-1] == 0 ) { strncat(dst, " on ", len-1); strncat(dst, fpga_info, len-1); } if(bitparse_find_section('d', &fpga_info, &fpga_info_len) && fpga_info[fpga_info_len-1] == 0 ) { strncat(dst, " at ", len-1); strncat(dst, fpga_info, len-1); } } } //----------------------------------------------------------------------------- // Send a 16 bit command/data pair to the FPGA. // The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 // where C is the 4 bit command and D is the 12 bit data //----------------------------------------------------------------------------- void FpgaSendCommand(uint16_t cmd, uint16_t v) { SetupSpi(SPI_FPGA_MODE); while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TXEMPTY) == 0); // wait for the transfer to complete AT91C_BASE_SPI->SPI_TDR = AT91C_SPI_LASTXFER | cmd | v; // send the data } //----------------------------------------------------------------------------- // Write the FPGA setup word (that determines what mode the logic is in, read // vs. clone vs. etc.). This is now a special case of FpgaSendCommand() to // avoid changing this function's occurence everywhere in the source code. //----------------------------------------------------------------------------- void FpgaWriteConfWord(uint8_t v) { FpgaSendCommand(FPGA_CMD_SET_CONFREG, v); } //----------------------------------------------------------------------------- // Set up the CMOS switches that mux the ADC: four switches, independently // closable, but should only close one at a time. Not an FPGA thing, but // the samples from the ADC always flow through the FPGA. //----------------------------------------------------------------------------- void SetAdcMuxFor(uint32_t whichGpio) { AT91C_BASE_PIOA->PIO_OER = GPIO_MUXSEL_HIPKD | GPIO_MUXSEL_LOPKD | GPIO_MUXSEL_LORAW | GPIO_MUXSEL_HIRAW; AT91C_BASE_PIOA->PIO_PER = GPIO_MUXSEL_HIPKD | GPIO_MUXSEL_LOPKD | GPIO_MUXSEL_LORAW | GPIO_MUXSEL_HIRAW; LOW(GPIO_MUXSEL_HIPKD); LOW(GPIO_MUXSEL_HIRAW); LOW(GPIO_MUXSEL_LORAW); LOW(GPIO_MUXSEL_LOPKD); HIGH(whichGpio); } ================================================ FILE: TamagotchiFriends/proxmark/armsrc/hitag2.c ================================================ //----------------------------------------------------------------------------- // This code is licensed to you under the terms of the GNU GPL, version 2 or, // at your option, any later version. See the LICENSE.txt file for the text of // the license. //----------------------------------------------------------------------------- // Hitag2 emulation (preliminary test version) // // (c) 2009 Henryk Plötz //----------------------------------------------------------------------------- // Hitag2 complete rewrite of the code // - Fixed modulation/encoding issues // - Rewrote code for transponder emulation // - Added snooping of transponder communication // - Added reader functionality // // (c) 2012 Roel Verdult //----------------------------------------------------------------------------- #include "proxmark3.h" #include "apps.h" #include "util.h" #include "hitag2.h" #include "string.h" static bool bQuiet; bool bCrypto; bool bAuthenticating; bool bPwd; bool bSuccessful; int LogTraceHitag(const uint8_t * btBytes, int iBits, int iSamples, uint32_t dwParity, int bReader) { // Return when trace is full if (traceLen >= TRACE_SIZE) return FALSE; // Trace the random, i'm curious rsamples += iSamples; trace[traceLen++] = ((rsamples >> 0) & 0xff); trace[traceLen++] = ((rsamples >> 8) & 0xff); trace[traceLen++] = ((rsamples >> 16) & 0xff); trace[traceLen++] = ((rsamples >> 24) & 0xff); if (!bReader) { trace[traceLen - 1] |= 0x80; } trace[traceLen++] = ((dwParity >> 0) & 0xff); trace[traceLen++] = ((dwParity >> 8) & 0xff); trace[traceLen++] = ((dwParity >> 16) & 0xff); trace[traceLen++] = ((dwParity >> 24) & 0xff); trace[traceLen++] = iBits; memcpy(trace + traceLen, btBytes, nbytes(iBits)); traceLen += nbytes(iBits); return TRUE; } struct hitag2_tag { uint32_t uid; enum { TAG_STATE_RESET = 0x01, // Just powered up, awaiting GetSnr TAG_STATE_ACTIVATING = 0x02 , // In activation phase (password mode), sent UID, awaiting reader password TAG_STATE_ACTIVATED = 0x03, // Activation complete, awaiting read/write commands TAG_STATE_WRITING = 0x04, // In write command, awaiting sector contents to be written } state; unsigned int active_sector; byte_t crypto_active; uint64_t cs; byte_t sectors[12][4]; }; static struct hitag2_tag tag = { .state = TAG_STATE_RESET, .sectors = { // Password mode: | Crypto mode: [0] = { 0x02, 0x4e, 0x02, 0x20}, // UID | UID [1] = { 0x4d, 0x49, 0x4b, 0x52}, // Password RWD | 32 bit LSB key [2] = { 0x20, 0xf0, 0x4f, 0x4e}, // Reserved | 16 bit MSB key, 16 bit reserved [3] = { 0x0e, 0xaa, 0x48, 0x54}, // Configuration, password TAG | Configuration, password TAG [4] = { 0x46, 0x5f, 0x4f, 0x4b}, // Data: F_OK [5] = { 0x55, 0x55, 0x55, 0x55}, // Data: UUUU [6] = { 0xaa, 0xaa, 0xaa, 0xaa}, // Data: .... [7] = { 0x55, 0x55, 0x55, 0x55}, // Data: UUUU [8] = { 0x00, 0x00, 0x00, 0x00}, // RSK Low [9] = { 0x00, 0x00, 0x00, 0x00}, // RSK High [10] = { 0x00, 0x00, 0x00, 0x00}, // RCF [11] = { 0x00, 0x00, 0x00, 0x00}, // SYNC }, }; //#define TRACE_LENGTH 3000 //uint8_t *trace = (uint8_t *) BigBuf; //int traceLen = 0; //int rsamples = 0; #define AUTH_TABLE_OFFSET FREE_BUFFER_OFFSET #define AUTH_TABLE_LENGTH FREE_BUFFER_SIZE byte_t* auth_table = (byte_t *)BigBuf+AUTH_TABLE_OFFSET; size_t auth_table_pos = 0; size_t auth_table_len = AUTH_TABLE_LENGTH; byte_t password[4]; byte_t NrAr[8]; byte_t key[8]; uint64_t cipher_state; /* Following is a modified version of cryptolib.com/ciphers/hitag2/ */ // Software optimized 48-bit Philips/NXP Mifare Hitag2 PCF7936/46/47/52 stream cipher algorithm by I.C. Wiener 2006-2007. // For educational purposes only. // No warranties or guarantees of any kind. // This code is released into the public domain by its author. // Basic macros: #define u8 uint8_t #define u32 uint32_t #define u64 uint64_t #define rev8(x) ((((x)>>7)&1)+((((x)>>6)&1)<<1)+((((x)>>5)&1)<<2)+((((x)>>4)&1)<<3)+((((x)>>3)&1)<<4)+((((x)>>2)&1)<<5)+((((x)>>1)&1)<<6)+(((x)&1)<<7)) #define rev16(x) (rev8 (x)+(rev8 (x>> 8)<< 8)) #define rev32(x) (rev16(x)+(rev16(x>>16)<<16)) #define rev64(x) (rev32(x)+(rev32(x>>32)<<32)) #define bit(x,n) (((x)>>(n))&1) #define bit32(x,n) ((((x)[(n)>>5])>>((n)))&1) #define inv32(x,i,n) ((x)[(i)>>5]^=((u32)(n))<<((i)&31)) #define rotl64(x, n) ((((u64)(x))<<((n)&63))+(((u64)(x))>>((0-(n))&63))) // Single bit Hitag2 functions: #define i4(x,a,b,c,d) ((u32)((((x)>>(a))&1)+(((x)>>(b))&1)*2+(((x)>>(c))&1)*4+(((x)>>(d))&1)*8)) static const u32 ht2_f4a = 0x2C79; // 0010 1100 0111 1001 static const u32 ht2_f4b = 0x6671; // 0110 0110 0111 0001 static const u32 ht2_f5c = 0x7907287B; // 0111 1001 0000 0111 0010 1000 0111 1011 static u32 _f20 (const u64 x) { u32 i5; i5 = ((ht2_f4a >> i4 (x, 1, 2, 4, 5)) & 1)* 1 + ((ht2_f4b >> i4 (x, 7,11,13,14)) & 1)* 2 + ((ht2_f4b >> i4 (x,16,20,22,25)) & 1)* 4 + ((ht2_f4b >> i4 (x,27,28,30,32)) & 1)* 8 + ((ht2_f4a >> i4 (x,33,42,43,45)) & 1)*16; return (ht2_f5c >> i5) & 1; } static u64 _hitag2_init (const u64 key, const u32 serial, const u32 IV) { u32 i; u64 x = ((key & 0xFFFF) << 32) + serial; for (i = 0; i < 32; i++) { x >>= 1; x += (u64) (_f20 (x) ^ (((IV >> i) ^ (key >> (i+16))) & 1)) << 47; } return x; } static u64 _hitag2_round (u64 *state) { u64 x = *state; x = (x >> 1) + ((((x >> 0) ^ (x >> 2) ^ (x >> 3) ^ (x >> 6) ^ (x >> 7) ^ (x >> 8) ^ (x >> 16) ^ (x >> 22) ^ (x >> 23) ^ (x >> 26) ^ (x >> 30) ^ (x >> 41) ^ (x >> 42) ^ (x >> 43) ^ (x >> 46) ^ (x >> 47)) & 1) << 47); *state = x; return _f20 (x); } static u32 _hitag2_byte (u64 * x) { u32 i, c; for (i = 0, c = 0; i < 8; i++) c += (u32) _hitag2_round (x) << (i^7); return c; } int hitag2_reset(void) { tag.state = TAG_STATE_RESET; tag.crypto_active = 0; return 0; } int hitag2_init(void) { // memcpy(&tag, &resetdata, sizeof(tag)); hitag2_reset(); return 0; } static void hitag2_cipher_reset(struct hitag2_tag *tag, const byte_t *iv) { uint64_t key = ((uint64_t)tag->sectors[2][2]) | ((uint64_t)tag->sectors[2][3] << 8) | ((uint64_t)tag->sectors[1][0] << 16) | ((uint64_t)tag->sectors[1][1] << 24) | ((uint64_t)tag->sectors[1][2] << 32) | ((uint64_t)tag->sectors[1][3] << 40); uint32_t uid = ((uint32_t)tag->sectors[0][0]) | ((uint32_t)tag->sectors[0][1] << 8) | ((uint32_t)tag->sectors[0][2] << 16) | ((uint32_t)tag->sectors[0][3] << 24); uint32_t iv_ = (((uint32_t)(iv[0]))) | (((uint32_t)(iv[1])) << 8) | (((uint32_t)(iv[2])) << 16) | (((uint32_t)(iv[3])) << 24); tag->cs = _hitag2_init(rev64(key), rev32(uid), rev32(iv_)); } static int hitag2_cipher_authenticate(uint64_t* cs, const byte_t *authenticator_is) { byte_t authenticator_should[4]; authenticator_should[0] = ~_hitag2_byte(cs); authenticator_should[1] = ~_hitag2_byte(cs); authenticator_should[2] = ~_hitag2_byte(cs); authenticator_should[3] = ~_hitag2_byte(cs); return (memcmp(authenticator_should, authenticator_is, 4) == 0); } static int hitag2_cipher_transcrypt(uint64_t* cs, byte_t *data, unsigned int bytes, unsigned int bits) { int i; for(i=0; i 36 */ #define HITAG_T_LOW 8 /* T_LOW should be 4..10 */ #define HITAG_T_0_MIN 15 /* T[0] should be 18..22 */ #define HITAG_T_1_MIN 25 /* T[1] should be 26..30 */ //#define HITAG_T_EOF 40 /* T_EOF should be > 36 */ #define HITAG_T_EOF 80 /* T_EOF should be > 36 */ #define HITAG_T_WAIT_1 200 /* T_wresp should be 199..206 */ #define HITAG_T_WAIT_2 90 /* T_wresp should be 199..206 */ #define HITAG_T_WAIT_MAX 300 /* bit more than HITAG_T_WAIT_1 + HITAG_T_WAIT_2 */ #define HITAG_T_TAG_ONE_HALF_PERIOD 10 #define HITAG_T_TAG_TWO_HALF_PERIOD 25 #define HITAG_T_TAG_THREE_HALF_PERIOD 41 #define HITAG_T_TAG_FOUR_HALF_PERIOD 57 #define HITAG_T_TAG_HALF_PERIOD 16 #define HITAG_T_TAG_FULL_PERIOD 32 #define HITAG_T_TAG_CAPTURE_ONE_HALF 13 #define HITAG_T_TAG_CAPTURE_TWO_HALF 25 #define HITAG_T_TAG_CAPTURE_THREE_HALF 41 #define HITAG_T_TAG_CAPTURE_FOUR_HALF 57 static void hitag_send_bit(int bit) { LED_A_ON(); // Reset clock for the next bit AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG; // Fixed modulation, earlier proxmark version used inverted signal if(bit == 0) { // Manchester: Unloaded, then loaded |__--| LOW(GPIO_SSC_DOUT); while(AT91C_BASE_TC0->TC_CV < T0*HITAG_T_TAG_HALF_PERIOD); HIGH(GPIO_SSC_DOUT); while(AT91C_BASE_TC0->TC_CV < T0*HITAG_T_TAG_FULL_PERIOD); } else { // Manchester: Loaded, then unloaded |--__| HIGH(GPIO_SSC_DOUT); while(AT91C_BASE_TC0->TC_CV < T0*HITAG_T_TAG_HALF_PERIOD); LOW(GPIO_SSC_DOUT); while(AT91C_BASE_TC0->TC_CV < T0*HITAG_T_TAG_FULL_PERIOD); } LED_A_OFF(); } static void hitag_send_frame(const byte_t* frame, size_t frame_len) { // Send start of frame for(size_t i=0; i<5; i++) { hitag_send_bit(1); } // Send the content of the frame for(size_t i=0; i> (7-(i%8)))&1); } // Drop the modulation LOW(GPIO_SSC_DOUT); } void hitag2_handle_reader_command(byte_t* rx, const size_t rxlen, byte_t* tx, size_t* txlen) { byte_t rx_air[HITAG_FRAME_LEN]; // Copy the (original) received frame how it is send over the air memcpy(rx_air,rx,nbytes(rxlen)); if(tag.crypto_active) { hitag2_cipher_transcrypt(&(tag.cs),rx,rxlen/8,rxlen%8); } // Reset the transmission frame length *txlen = 0; // Try to find out which command was send by selecting on length (in bits) switch (rxlen) { // Received 11000 from the reader, request for UID, send UID case 05: { // Always send over the air in the clear plaintext mode if(rx_air[0] != 0xC0) { // Unknown frame ? return; } *txlen = 32; memcpy(tx,tag.sectors[0],4); tag.crypto_active = 0; } break; // Read/Write command: ..xx x..y yy with yyy == ~xxx, xxx is sector number case 10: { unsigned int sector = (~( ((rx[0]<<2)&0x04) | ((rx[1]>>6)&0x03) ) & 0x07); // Verify complement of sector index if(sector != ((rx[0]>>3)&0x07)) { //DbpString("Transmission error (read/write)"); return; } switch (rx[0] & 0xC6) { // Read command: 11xx x00y case 0xC0: memcpy(tx,tag.sectors[sector],4); *txlen = 32; break; // Inverted Read command: 01xx x10y case 0x44: for (size_t i=0; i<4; i++) { tx[i] = tag.sectors[sector][i] ^ 0xff; } *txlen = 32; break; // Write command: 10xx x01y case 0x82: // Prepare write, acknowledge by repeating command memcpy(tx,rx,nbytes(rxlen)); *txlen = rxlen; tag.active_sector = sector; tag.state=TAG_STATE_WRITING; break; // Unknown command default: Dbprintf("Uknown command: %02x %02x",rx[0],rx[1]); return; break; } } break; // Writing data or Reader password case 32: { if(tag.state == TAG_STATE_WRITING) { // These are the sector contents to be written. We don't have to do anything else. memcpy(tag.sectors[tag.active_sector],rx,nbytes(rxlen)); tag.state=TAG_STATE_RESET; return; } else { // Received RWD password, respond with configuration and our password if(memcmp(rx,tag.sectors[1],4) != 0) { DbpString("Reader password is wrong"); return; } *txlen = 32; memcpy(tx,tag.sectors[3],4); } } break; // Received RWD authentication challenge and respnse case 64: { // Store the authentication attempt if (auth_table_len < (AUTH_TABLE_LENGTH-8)) { memcpy(auth_table+auth_table_len,rx,8); auth_table_len += 8; } // Reset the cipher state hitag2_cipher_reset(&tag,rx); // Check if the authentication was correct if(!hitag2_cipher_authenticate(&(tag.cs),rx+4)) { // The reader failed to authenticate, do nothing Dbprintf("auth: %02x%02x%02x%02x%02x%02x%02x%02x Failed!",rx[0],rx[1],rx[2],rx[3],rx[4],rx[5],rx[6],rx[7]); return; } // Succesful, but commented out reporting back to the Host, this may delay to much. // Dbprintf("auth: %02x%02x%02x%02x%02x%02x%02x%02x OK!",rx[0],rx[1],rx[2],rx[3],rx[4],rx[5],rx[6],rx[7]); // Activate encryption algorithm for all further communication tag.crypto_active = 1; // Use the tag password as response memcpy(tx,tag.sectors[3],4); *txlen = 32; } break; } // LogTraceHitag(rx,rxlen,0,0,false); // LogTraceHitag(tx,*txlen,0,0,true); if(tag.crypto_active) { hitag2_cipher_transcrypt(&(tag.cs), tx, *txlen/8, *txlen%8); } } static void hitag_reader_send_bit(int bit) { LED_A_ON(); // Reset clock for the next bit AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG; // Binary puls length modulation (BPLM) is used to encode the data stream // This means that a transmission of a one takes longer than that of a zero // Enable modulation, which means, drop the the field HIGH(GPIO_SSC_DOUT); // Wait for 4-10 times the carrier period while(AT91C_BASE_TC0->TC_CV < T0*6); // SpinDelayUs(8*8); // Disable modulation, just activates the field again LOW(GPIO_SSC_DOUT); if(bit == 0) { // Zero bit: |_-| while(AT91C_BASE_TC0->TC_CV < T0*22); // SpinDelayUs(16*8); } else { // One bit: |_--| while(AT91C_BASE_TC0->TC_CV < T0*28); // SpinDelayUs(22*8); } LED_A_OFF(); } static void hitag_reader_send_frame(const byte_t* frame, size_t frame_len) { // Send the content of the frame for(size_t i=0; i> (7-(i%8)))&1); } // Send EOF AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG; // Enable modulation, which means, drop the the field HIGH(GPIO_SSC_DOUT); // Wait for 4-10 times the carrier period while(AT91C_BASE_TC0->TC_CV < T0*6); // Disable modulation, just activates the field again LOW(GPIO_SSC_DOUT); } size_t blocknr; bool hitag2_password(byte_t* rx, const size_t rxlen, byte_t* tx, size_t* txlen) { // Reset the transmission frame length *txlen = 0; // Try to find out which command was send by selecting on length (in bits) switch (rxlen) { // No answer, try to resurrect case 0: { // Stop if there is no answer (after sending password) if (bPwd) { DbpString("Password failed!"); return false; } *txlen = 5; memcpy(tx,"\xc0",nbytes(*txlen)); } break; // Received UID, tag password case 32: { if (!bPwd) { *txlen = 32; memcpy(tx,password,4); bPwd = true; memcpy(tag.sectors[blocknr],rx,4); blocknr++; } else { if(blocknr == 1){ //store password in block1, the TAG answers with Block3, but we need the password in memory memcpy(tag.sectors[blocknr],tx,4); }else{ memcpy(tag.sectors[blocknr],rx,4); } blocknr++; if (blocknr > 7) { DbpString("Read succesful!"); bSuccessful = true; return false; } *txlen = 10; tx[0] = 0xc0 | (blocknr << 3) | ((blocknr^7) >> 2); tx[1] = ((blocknr^7) << 6); } } break; // Unexpected response default: { Dbprintf("Uknown frame length: %d",rxlen); return false; } break; } return true; } bool hitag2_crypto(byte_t* rx, const size_t rxlen, byte_t* tx, size_t* txlen) { // Reset the transmission frame length *txlen = 0; if(bCrypto) { hitag2_cipher_transcrypt(&cipher_state,rx,rxlen/8,rxlen%8); } // Try to find out which command was send by selecting on length (in bits) switch (rxlen) { // No answer, try to resurrect case 0: { // Stop if there is no answer while we are in crypto mode (after sending NrAr) if (bCrypto) { // Failed during authentication if (bAuthenticating) { DbpString("Authentication failed!"); return false; } else { // Failed reading a block, could be (read/write) locked, skip block and re-authenticate if (blocknr == 1) { // Write the low part of the key in memory memcpy(tag.sectors[1],key+2,4); } else if (blocknr == 2) { // Write the high part of the key in memory tag.sectors[2][0] = 0x00; tag.sectors[2][1] = 0x00; tag.sectors[2][2] = key[0]; tag.sectors[2][3] = key[1]; } else { // Just put zero's in the memory (of the unreadable block) memset(tag.sectors[blocknr],0x00,4); } blocknr++; bCrypto = false; } } else { *txlen = 5; memcpy(tx,"\xc0",nbytes(*txlen)); } } break; // Received UID, crypto tag answer case 32: { if (!bCrypto) { uint64_t ui64key = key[0] | ((uint64_t)key[1]) << 8 | ((uint64_t)key[2]) << 16 | ((uint64_t)key[3]) << 24 | ((uint64_t)key[4]) << 32 | ((uint64_t)key[5]) << 40; uint32_t ui32uid = rx[0] | ((uint32_t)rx[1]) << 8 | ((uint32_t)rx[2]) << 16 | ((uint32_t)rx[3]) << 24; cipher_state = _hitag2_init(rev64(ui64key), rev32(ui32uid), 0); memset(tx,0x00,4); memset(tx+4,0xff,4); hitag2_cipher_transcrypt(&cipher_state,tx+4,4,0); *txlen = 64; bCrypto = true; bAuthenticating = true; } else { // Check if we received answer tag (at) if (bAuthenticating) { bAuthenticating = false; } else { // Store the received block memcpy(tag.sectors[blocknr],rx,4); blocknr++; } if (blocknr > 7) { DbpString("Read succesful!"); bSuccessful = true; return false; } *txlen = 10; tx[0] = 0xc0 | (blocknr << 3) | ((blocknr^7) >> 2); tx[1] = ((blocknr^7) << 6); } } break; // Unexpected response default: { Dbprintf("Uknown frame length: %d",rxlen); return false; } break; } if(bCrypto) { // We have to return now to avoid double encryption if (!bAuthenticating) { hitag2_cipher_transcrypt(&cipher_state,tx,*txlen/8,*txlen%8); } } return true; } bool hitag2_authenticate(byte_t* rx, const size_t rxlen, byte_t* tx, size_t* txlen) { // Reset the transmission frame length *txlen = 0; // Try to find out which command was send by selecting on length (in bits) switch (rxlen) { // No answer, try to resurrect case 0: { // Stop if there is no answer while we are in crypto mode (after sending NrAr) if (bCrypto) { DbpString("Authentication failed!"); return false; } *txlen = 5; memcpy(tx,"\xc0",nbytes(*txlen)); } break; // Received UID, crypto tag answer case 32: { if (!bCrypto) { *txlen = 64; memcpy(tx,NrAr,8); bCrypto = true; } else { DbpString("Authentication succesful!"); // We are done... for now return false; } } break; // Unexpected response default: { Dbprintf("Uknown frame length: %d",rxlen); return false; } break; } return true; } bool hitag2_test_auth_attempts(byte_t* rx, const size_t rxlen, byte_t* tx, size_t* txlen) { // Reset the transmission frame length *txlen = 0; // Try to find out which command was send by selecting on length (in bits) switch (rxlen) { // No answer, try to resurrect case 0: { // Stop if there is no answer while we are in crypto mode (after sending NrAr) if (bCrypto) { Dbprintf("auth: %02x%02x%02x%02x%02x%02x%02x%02x Failed, removed entry!",NrAr[0],NrAr[1],NrAr[2],NrAr[3],NrAr[4],NrAr[5],NrAr[6],NrAr[7]); // Removing failed entry from authentiations table memcpy(auth_table+auth_table_pos,auth_table+auth_table_pos+8,8); auth_table_len -= 8; // Return if we reached the end of the authentiactions table bCrypto = false; if (auth_table_pos == auth_table_len) { return false; } // Copy the next authentication attempt in row (at the same position, b/c we removed last failed entry) memcpy(NrAr,auth_table+auth_table_pos,8); } *txlen = 5; memcpy(tx,"\xc0",nbytes(*txlen)); } break; // Received UID, crypto tag answer, or read block response case 32: { if (!bCrypto) { *txlen = 64; memcpy(tx,NrAr,8); bCrypto = true; } else { Dbprintf("auth: %02x%02x%02x%02x%02x%02x%02x%02x OK",NrAr[0],NrAr[1],NrAr[2],NrAr[3],NrAr[4],NrAr[5],NrAr[6],NrAr[7]); bCrypto = false; if ((auth_table_pos+8) == auth_table_len) { return false; } auth_table_pos += 8; memcpy(NrAr,auth_table+auth_table_pos,8); } } break; default: { Dbprintf("Uknown frame length: %d",rxlen); return false; } break; } return true; } void SnoopHitag(uint32_t type) { int frame_count; int response; int overflow; bool rising_edge; bool reader_frame; int lastbit; bool bSkip; int tag_sof; byte_t rx[HITAG_FRAME_LEN]; size_t rxlen=0; // Clean up trace and prepare it for storing frames iso14a_set_tracing(TRUE); iso14a_clear_trace(); auth_table_len = 0; auth_table_pos = 0; memset(auth_table, 0x00, AUTH_TABLE_LENGTH); DbpString("Starting Hitag2 snoop"); LED_D_ON(); // Set up eavesdropping mode, frequency divisor which will drive the FPGA // and analog mux selection. FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT); FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz SetAdcMuxFor(GPIO_MUXSEL_LOPKD); RELAY_OFF(); // Configure output pin that is connected to the FPGA (for modulating) AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT; // Disable modulation, we are going to eavesdrop, not modulate ;) LOW(GPIO_SSC_DOUT); // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the reader frames AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1); AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME; // Disable timer during configuration AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger, // external trigger rising edge, load RA on rising edge of TIOA. uint32_t t1_channel_mode = AT91C_TC_CLKS_TIMER_DIV1_CLOCK | AT91C_TC_ETRGEDG_BOTH | AT91C_TC_ABETRG | AT91C_TC_LDRA_BOTH; AT91C_BASE_TC1->TC_CMR = t1_channel_mode; // Enable and reset counter AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // Reset the received frame, frame count and timing info memset(rx,0x00,sizeof(rx)); frame_count = 0; response = 0; overflow = 0; reader_frame = false; lastbit = 1; bSkip = true; tag_sof = 4; while(!BUTTON_PRESS()) { // Watchdog hit WDT_HIT(); // Receive frame, watch for at most T0*EOF periods while (AT91C_BASE_TC1->TC_CV < T0*HITAG_T_EOF) { // Check if rising edge in modulation is detected if(AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) { // Retrieve the new timing values int ra = (AT91C_BASE_TC1->TC_RA/T0); // Find out if we are dealing with a rising or falling edge rising_edge = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME) > 0; // Shorter periods will only happen with reader frames if (!reader_frame && rising_edge && ra < HITAG_T_TAG_CAPTURE_ONE_HALF) { // Switch from tag to reader capture LED_C_OFF(); reader_frame = true; memset(rx,0x00,sizeof(rx)); rxlen = 0; } // Only handle if reader frame and rising edge, or tag frame and falling edge if (reader_frame != rising_edge) { overflow += ra; continue; } // Add the buffered timing values of earlier captured edges which were skipped ra += overflow; overflow = 0; if (reader_frame) { LED_B_ON(); // Capture reader frame if(ra >= HITAG_T_STOP) { if (rxlen != 0) { //DbpString("wierd0?"); } // Capture the T0 periods that have passed since last communication or field drop (reset) response = (ra - HITAG_T_LOW); } else if(ra >= HITAG_T_1_MIN ) { // '1' bit rx[rxlen / 8] |= 1 << (7-(rxlen%8)); rxlen++; } else if(ra >= HITAG_T_0_MIN) { // '0' bit rx[rxlen / 8] |= 0 << (7-(rxlen%8)); rxlen++; } else { // Ignore wierd value, is to small to mean anything } } else { LED_C_ON(); // Capture tag frame (manchester decoding using only falling edges) if(ra >= HITAG_T_EOF) { if (rxlen != 0) { //DbpString("wierd1?"); } // Capture the T0 periods that have passed since last communication or field drop (reset) // We always recieve a 'one' first, which has the falling edge after a half period |-_| response = ra-HITAG_T_TAG_HALF_PERIOD; } else if(ra >= HITAG_T_TAG_CAPTURE_FOUR_HALF) { // Manchester coding example |-_|_-|-_| (101) rx[rxlen / 8] |= 0 << (7-(rxlen%8)); rxlen++; rx[rxlen / 8] |= 1 << (7-(rxlen%8)); rxlen++; } else if(ra >= HITAG_T_TAG_CAPTURE_THREE_HALF) { // Manchester coding example |_-|...|_-|-_| (0...01) rx[rxlen / 8] |= 0 << (7-(rxlen%8)); rxlen++; // We have to skip this half period at start and add the 'one' the second time if (!bSkip) { rx[rxlen / 8] |= 1 << (7-(rxlen%8)); rxlen++; } lastbit = !lastbit; bSkip = !bSkip; } else if(ra >= HITAG_T_TAG_CAPTURE_TWO_HALF) { // Manchester coding example |_-|_-| (00) or |-_|-_| (11) if (tag_sof) { // Ignore bits that are transmitted during SOF tag_sof--; } else { // bit is same as last bit rx[rxlen / 8] |= lastbit << (7-(rxlen%8)); rxlen++; } } else { // Ignore wierd value, is to small to mean anything } } } } // Check if frame was captured if(rxlen > 0) { frame_count++; if (!LogTraceHitag(rx,rxlen,response,0,reader_frame)) { DbpString("Trace full"); break; } // Check if we recognize a valid authentication attempt if (nbytes(rxlen) == 8) { // Store the authentication attempt if (auth_table_len < (AUTH_TABLE_LENGTH-8)) { memcpy(auth_table+auth_table_len,rx,8); auth_table_len += 8; } } // Reset the received frame and response timing info memset(rx,0x00,sizeof(rx)); response = 0; reader_frame = false; lastbit = 1; bSkip = true; tag_sof = 4; overflow = 0; LED_B_OFF(); LED_C_OFF(); } else { // Save the timer overflow, will be 0 when frame was received overflow += (AT91C_BASE_TC1->TC_CV/T0); } // Reset the frame length rxlen = 0; // Reset the timer to restart while-loop that receives frames AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG; } LED_A_ON(); LED_B_OFF(); LED_C_OFF(); LED_D_OFF(); AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); LED_A_OFF(); // Dbprintf("frame received: %d",frame_count); // Dbprintf("Authentication Attempts: %d",(auth_table_len/8)); // DbpString("All done"); } void SimulateHitagTag(bool tag_mem_supplied, byte_t* data) { int frame_count; int response; int overflow; byte_t rx[HITAG_FRAME_LEN]; size_t rxlen=0; byte_t tx[HITAG_FRAME_LEN]; size_t txlen=0; bool bQuitTraceFull = false; bQuiet = false; // Clean up trace and prepare it for storing frames iso14a_set_tracing(TRUE); iso14a_clear_trace(); auth_table_len = 0; auth_table_pos = 0; memset(auth_table, 0x00, AUTH_TABLE_LENGTH); DbpString("Starting Hitag2 simulation"); LED_D_ON(); hitag2_init(); if (tag_mem_supplied) { DbpString("Loading hitag2 memory..."); memcpy((byte_t*)tag.sectors,data,48); } uint32_t block = 0; for (size_t i=0; i<12; i++) { for (size_t j=0; j<4; j++) { block <<= 8; block |= tag.sectors[i][j]; } Dbprintf("| %d | %08x |",i,block); } // Set up simulator mode, frequency divisor which will drive the FPGA // and analog mux selection. FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT); FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz SetAdcMuxFor(GPIO_MUXSEL_LOPKD); RELAY_OFF(); // Configure output pin that is connected to the FPGA (for modulating) AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT; // Disable modulation at default, which means release resistance LOW(GPIO_SSC_DOUT); // Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0); // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the reader frames AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1); AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME; // Disable timer during configuration AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger, // external trigger rising edge, load RA on rising edge of TIOA. AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK | AT91C_TC_ETRGEDG_RISING | AT91C_TC_ABETRG | AT91C_TC_LDRA_RISING; // Enable and reset counter AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // Reset the received frame, frame count and timing info memset(rx,0x00,sizeof(rx)); frame_count = 0; response = 0; overflow = 0; while(!BUTTON_PRESS()) { // Watchdog hit WDT_HIT(); // Receive frame, watch for at most T0*EOF periods while (AT91C_BASE_TC1->TC_CV < T0*HITAG_T_EOF) { // Check if rising edge in modulation is detected if(AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) { // Retrieve the new timing values int ra = (AT91C_BASE_TC1->TC_RA/T0) + overflow; overflow = 0; // Reset timer every frame, we have to capture the last edge for timing AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; LED_B_ON(); // Capture reader frame if(ra >= HITAG_T_STOP) { if (rxlen != 0) { //DbpString("wierd0?"); } // Capture the T0 periods that have passed since last communication or field drop (reset) response = (ra - HITAG_T_LOW); } else if(ra >= HITAG_T_1_MIN ) { // '1' bit rx[rxlen / 8] |= 1 << (7-(rxlen%8)); rxlen++; } else if(ra >= HITAG_T_0_MIN) { // '0' bit rx[rxlen / 8] |= 0 << (7-(rxlen%8)); rxlen++; } else { // Ignore wierd value, is to small to mean anything } } } // Check if frame was captured if(rxlen > 4) { frame_count++; if (!bQuiet) { if (!LogTraceHitag(rx,rxlen,response,0,true)) { DbpString("Trace full"); if (bQuitTraceFull) { break; } else { bQuiet = true; } } } // Disable timer 1 with external trigger to avoid triggers during our own modulation AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // Process the incoming frame (rx) and prepare the outgoing frame (tx) hitag2_handle_reader_command(rx,rxlen,tx,&txlen); // Wait for HITAG_T_WAIT_1 carrier periods after the last reader bit, // not that since the clock counts since the rising edge, but T_Wait1 is // with respect to the falling edge, we need to wait actually (T_Wait1 - T_Low) // periods. The gap time T_Low varies (4..10). All timer values are in // terms of T0 units while(AT91C_BASE_TC0->TC_CV < T0*(HITAG_T_WAIT_1-HITAG_T_LOW)); // Send and store the tag answer (if there is any) if (txlen) { // Transmit the tag frame hitag_send_frame(tx,txlen); // Store the frame in the trace if (!bQuiet) { if (!LogTraceHitag(tx,txlen,0,0,false)) { DbpString("Trace full"); if (bQuitTraceFull) { break; } else { bQuiet = true; } } } } // Reset the received frame and response timing info memset(rx,0x00,sizeof(rx)); response = 0; // Enable and reset external trigger in timer for capturing future frames AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; LED_B_OFF(); } // Reset the frame length rxlen = 0; // Save the timer overflow, will be 0 when frame was received overflow += (AT91C_BASE_TC1->TC_CV/T0); // Reset the timer to restart while-loop that receives frames AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG; } LED_B_OFF(); LED_D_OFF(); AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // Dbprintf("frame received: %d",frame_count); // Dbprintf("Authentication Attempts: %d",(auth_table_len/8)); // DbpString("All done"); } void ReaderHitag(hitag_function htf, hitag_data* htd) { int frame_count; int response; byte_t rx[HITAG_FRAME_LEN]; size_t rxlen=0; byte_t txbuf[HITAG_FRAME_LEN]; byte_t* tx = txbuf; size_t txlen=0; int lastbit; bool bSkip; int reset_sof; int tag_sof; int t_wait = HITAG_T_WAIT_MAX; bool bStop; bool bQuitTraceFull = false; // Reset the return status bSuccessful = false; // Clean up trace and prepare it for storing frames iso14a_set_tracing(TRUE); iso14a_clear_trace(); DbpString("Starting Hitag reader family"); // Check configuration switch(htf) { case RHT2F_PASSWORD: { Dbprintf("List identifier in password mode"); memcpy(password,htd->pwd.password,4); blocknr = 0; bQuitTraceFull = false; bQuiet = false; bPwd = false; } break; case RHT2F_AUTHENTICATE: { DbpString("Authenticating using nr,ar pair:"); memcpy(NrAr,htd->auth.NrAr,8); Dbhexdump(8,NrAr,false); bQuiet = false; bCrypto = false; bAuthenticating = false; bQuitTraceFull = true; } break; case RHT2F_CRYPTO: { DbpString("Authenticating using key:"); memcpy(key,htd->crypto.key,6); Dbhexdump(6,key,false); blocknr = 0; bQuiet = false; bCrypto = false; bAuthenticating = false; bQuitTraceFull = true; } break; case RHT2F_TEST_AUTH_ATTEMPTS: { Dbprintf("Testing %d authentication attempts",(auth_table_len/8)); auth_table_pos = 0; memcpy(NrAr,auth_table,8); bQuitTraceFull = false; bQuiet = false; bCrypto = false; } break; default: { Dbprintf("Error, unknown function: %d",htf); return; } break; } LED_D_ON(); hitag2_init(); // Configure output and enable pin that is connected to the FPGA (for modulating) AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT; // Set fpga in edge detect with reader field, we can modulate as reader now FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD); // Set Frequency divisor which will drive the FPGA and analog mux selection FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz SetAdcMuxFor(GPIO_MUXSEL_LOPKD); RELAY_OFF(); // Disable modulation at default, which means enable the field LOW(GPIO_SSC_DOUT); // Give it a bit of time for the resonant antenna to settle. SpinDelay(30); // Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0); // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the tag frames AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1); AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME; // Disable timer during configuration AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger, // external trigger rising edge, load RA on falling edge of TIOA. AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK | AT91C_TC_ETRGEDG_FALLING | AT91C_TC_ABETRG | AT91C_TC_LDRA_FALLING; // Enable and reset counters AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // Reset the received frame, frame count and timing info frame_count = 0; response = 0; lastbit = 1; bStop = false; // Tag specific configuration settings (sof, timings, etc.) if (htf < 10){ // hitagS settings reset_sof = 1; t_wait = 200; DbpString("Configured for hitagS reader"); } else if (htf < 20) { // hitag1 settings reset_sof = 1; t_wait = 200; DbpString("Configured for hitag1 reader"); } else if (htf < 30) { // hitag2 settings reset_sof = 4; t_wait = HITAG_T_WAIT_2; DbpString("Configured for hitag2 reader"); } else { Dbprintf("Error, unknown hitag reader type: %d",htf); return; } while(!bStop && !BUTTON_PRESS()) { // Watchdog hit WDT_HIT(); // Check if frame was captured and store it if(rxlen > 0) { frame_count++; if (!bQuiet) { if (!LogTraceHitag(rx,rxlen,response,0,false)) { DbpString("Trace full"); if (bQuitTraceFull) { break; } else { bQuiet = true; } } } } // By default reset the transmission buffer tx = txbuf; switch(htf) { case RHT2F_PASSWORD: { bStop = !hitag2_password(rx,rxlen,tx,&txlen); } break; case RHT2F_AUTHENTICATE: { bStop = !hitag2_authenticate(rx,rxlen,tx,&txlen); } break; case RHT2F_CRYPTO: { bStop = !hitag2_crypto(rx,rxlen,tx,&txlen); } break; case RHT2F_TEST_AUTH_ATTEMPTS: { bStop = !hitag2_test_auth_attempts(rx,rxlen,tx,&txlen); } break; default: { Dbprintf("Error, unknown function: %d",htf); return; } break; } // Send and store the reader command // Disable timer 1 with external trigger to avoid triggers during our own modulation AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // Wait for HITAG_T_WAIT_2 carrier periods after the last tag bit before transmitting, // Since the clock counts since the last falling edge, a 'one' means that the // falling edge occured halfway the period. with respect to this falling edge, // we need to wait (T_Wait2 + half_tag_period) when the last was a 'one'. // All timer values are in terms of T0 units while(AT91C_BASE_TC0->TC_CV < T0*(t_wait+(HITAG_T_TAG_HALF_PERIOD*lastbit))); // Transmit the reader frame hitag_reader_send_frame(tx,txlen); // Enable and reset external trigger in timer for capturing future frames AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // Add transmitted frame to total count if(txlen > 0) { frame_count++; if (!bQuiet) { // Store the frame in the trace if (!LogTraceHitag(tx,txlen,HITAG_T_WAIT_2,0,true)) { if (bQuitTraceFull) { break; } else { bQuiet = true; } } } } // Reset values for receiving frames memset(rx,0x00,sizeof(rx)); rxlen = 0; lastbit = 1; bSkip = true; tag_sof = reset_sof; response = 0; // Receive frame, watch for at most T0*EOF periods while (AT91C_BASE_TC1->TC_CV < T0*HITAG_T_WAIT_MAX) { // Check if falling edge in tag modulation is detected if(AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) { // Retrieve the new timing values int ra = (AT91C_BASE_TC1->TC_RA/T0); // Reset timer every frame, we have to capture the last edge for timing AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG; LED_B_ON(); // Capture tag frame (manchester decoding using only falling edges) if(ra >= HITAG_T_EOF) { if (rxlen != 0) { //DbpString("wierd1?"); } // Capture the T0 periods that have passed since last communication or field drop (reset) // We always recieve a 'one' first, which has the falling edge after a half period |-_| response = ra-HITAG_T_TAG_HALF_PERIOD; } else if(ra >= HITAG_T_TAG_CAPTURE_FOUR_HALF) { // Manchester coding example |-_|_-|-_| (101) rx[rxlen / 8] |= 0 << (7-(rxlen%8)); rxlen++; rx[rxlen / 8] |= 1 << (7-(rxlen%8)); rxlen++; } else if(ra >= HITAG_T_TAG_CAPTURE_THREE_HALF) { // Manchester coding example |_-|...|_-|-_| (0...01) rx[rxlen / 8] |= 0 << (7-(rxlen%8)); rxlen++; // We have to skip this half period at start and add the 'one' the second time if (!bSkip) { rx[rxlen / 8] |= 1 << (7-(rxlen%8)); rxlen++; } lastbit = !lastbit; bSkip = !bSkip; } else if(ra >= HITAG_T_TAG_CAPTURE_TWO_HALF) { // Manchester coding example |_-|_-| (00) or |-_|-_| (11) if (tag_sof) { // Ignore bits that are transmitted during SOF tag_sof--; } else { // bit is same as last bit rx[rxlen / 8] |= lastbit << (7-(rxlen%8)); rxlen++; } } else { // Ignore wierd value, is to small to mean anything } } // We can break this loop if we received the last bit from a frame if (AT91C_BASE_TC1->TC_CV > T0*HITAG_T_EOF) { if (rxlen>0) break; } } } LED_B_OFF(); LED_D_OFF(); AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); Dbprintf("frame received: %d",frame_count); DbpString("All done"); cmd_send(CMD_ACK,bSuccessful,0,0,(byte_t*)tag.sectors,48); } ================================================ FILE: TamagotchiFriends/proxmark/armsrc/iclass.c ================================================ //----------------------------------------------------------------------------- // Gerhard de Koning Gans - May 2008 // Hagen Fritsch - June 2010 // Gerhard de Koning Gans - May 2011 // Gerhard de Koning Gans - June 2012 - Added iClass card and reader emulation // // This code is licensed to you under the terms of the GNU GPL, version 2 or, // at your option, any later version. See the LICENSE.txt file for the text of // the license. //----------------------------------------------------------------------------- // Routines to support iClass. //----------------------------------------------------------------------------- // Based on ISO14443a implementation. Still in experimental phase. // Contribution made during a security research at Radboud University Nijmegen // // Please feel free to contribute and extend iClass support!! //----------------------------------------------------------------------------- // // FIX: // ==== // We still have sometimes a demodulation error when snooping iClass communication. // The resulting trace of a read-block-03 command may look something like this: // // + 22279: : 0c 03 e8 01 // // ...with an incorrect answer... // // + 85: 0: TAG ff! ff! ff! ff! ff! ff! ff! ff! bb 33 bb 00 01! 0e! 04! bb !crc // // We still left the error signalling bytes in the traces like 0xbb // // A correct trace should look like this: // // + 21112: : 0c 03 e8 01 // + 85: 0: TAG ff ff ff ff ff ff ff ff ea f5 // //----------------------------------------------------------------------------- #include "proxmark3.h" #include "apps.h" #include "util.h" #include "string.h" #include "common.h" // Needed for CRC in emulation mode; // same construction as in ISO 14443; // different initial value (CRC_ICLASS) #include "iso14443crc.h" static int timeout = 4096; // CARD TO READER // Sequence D: 11110000 modulation with subcarrier during first half // Sequence E: 00001111 modulation with subcarrier during second half // Sequence F: 00000000 no modulation with subcarrier // READER TO CARD // Sequence X: 00001100 drop after half a period // Sequence Y: 00000000 no drop // Sequence Z: 11000000 drop at start #define SEC_X 0x0c #define SEC_Y 0x00 #define SEC_Z 0xc0 static int SendIClassAnswer(uint8_t *resp, int respLen, int delay); //----------------------------------------------------------------------------- // The software UART that receives commands from the reader, and its state // variables. //----------------------------------------------------------------------------- static struct { enum { STATE_UNSYNCD, STATE_START_OF_COMMUNICATION, STATE_RECEIVING } state; uint16_t shiftReg; int bitCnt; int byteCnt; int byteCntMax; int posCnt; int nOutOfCnt; int OutOfCnt; int syncBit; int parityBits; int samples; int highCnt; int swapper; int counter; int bitBuffer; int dropPosition; uint8_t *output; } Uart; static RAMFUNC int OutOfNDecoding(int bit) { //int error = 0; int bitright; if(!Uart.bitBuffer) { Uart.bitBuffer = bit ^ 0xFF0; return FALSE; } else { Uart.bitBuffer <<= 4; Uart.bitBuffer ^= bit; } /*if(Uart.swapper) { Uart.output[Uart.byteCnt] = Uart.bitBuffer & 0xFF; Uart.byteCnt++; Uart.swapper = 0; if(Uart.byteCnt > 15) { return TRUE; } } else { Uart.swapper = 1; }*/ if(Uart.state != STATE_UNSYNCD) { Uart.posCnt++; if((Uart.bitBuffer & Uart.syncBit) ^ Uart.syncBit) { bit = 0x00; } else { bit = 0x01; } if(((Uart.bitBuffer << 1) & Uart.syncBit) ^ Uart.syncBit) { bitright = 0x00; } else { bitright = 0x01; } if(bit != bitright) { bit = bitright; } // So, now we only have to deal with *bit*, lets see... if(Uart.posCnt == 1) { // measurement first half bitperiod if(!bit) { // Drop in first half means that we are either seeing // an SOF or an EOF. if(Uart.nOutOfCnt == 1) { // End of Communication Uart.state = STATE_UNSYNCD; Uart.highCnt = 0; if(Uart.byteCnt == 0) { // Its not straightforward to show single EOFs // So just leave it and do not return TRUE Uart.output[Uart.byteCnt] = 0xf0; Uart.byteCnt++; // Calculate the parity bit for the client... Uart.parityBits = 1; } else { return TRUE; } } else if(Uart.state != STATE_START_OF_COMMUNICATION) { // When not part of SOF or EOF, it is an error Uart.state = STATE_UNSYNCD; Uart.highCnt = 0; //error = 4; } } } else { // measurement second half bitperiod // Count the bitslot we are in... (ISO 15693) Uart.nOutOfCnt++; if(!bit) { if(Uart.dropPosition) { if(Uart.state == STATE_START_OF_COMMUNICATION) { //error = 1; } else { //error = 7; } // It is an error if we already have seen a drop in current frame Uart.state = STATE_UNSYNCD; Uart.highCnt = 0; } else { Uart.dropPosition = Uart.nOutOfCnt; } } Uart.posCnt = 0; if(Uart.nOutOfCnt == Uart.OutOfCnt && Uart.OutOfCnt == 4) { Uart.nOutOfCnt = 0; if(Uart.state == STATE_START_OF_COMMUNICATION) { if(Uart.dropPosition == 4) { Uart.state = STATE_RECEIVING; Uart.OutOfCnt = 256; } else if(Uart.dropPosition == 3) { Uart.state = STATE_RECEIVING; Uart.OutOfCnt = 4; //Uart.output[Uart.byteCnt] = 0xdd; //Uart.byteCnt++; } else { Uart.state = STATE_UNSYNCD; Uart.highCnt = 0; } Uart.dropPosition = 0; } else { // RECEIVING DATA // 1 out of 4 if(!Uart.dropPosition) { Uart.state = STATE_UNSYNCD; Uart.highCnt = 0; //error = 9; } else { Uart.shiftReg >>= 2; // Swap bit order Uart.dropPosition--; //if(Uart.dropPosition == 1) { Uart.dropPosition = 2; } //else if(Uart.dropPosition == 2) { Uart.dropPosition = 1; } Uart.shiftReg ^= ((Uart.dropPosition & 0x03) << 6); Uart.bitCnt += 2; Uart.dropPosition = 0; if(Uart.bitCnt == 8) { Uart.output[Uart.byteCnt] = (Uart.shiftReg & 0xff); Uart.byteCnt++; // Calculate the parity bit for the client... Uart.parityBits <<= 1; Uart.parityBits ^= OddByteParity[(Uart.shiftReg & 0xff)]; Uart.bitCnt = 0; Uart.shiftReg = 0; } } } } else if(Uart.nOutOfCnt == Uart.OutOfCnt) { // RECEIVING DATA // 1 out of 256 if(!Uart.dropPosition) { Uart.state = STATE_UNSYNCD; Uart.highCnt = 0; //error = 3; } else { Uart.dropPosition--; Uart.output[Uart.byteCnt] = (Uart.dropPosition & 0xff); Uart.byteCnt++; // Calculate the parity bit for the client... Uart.parityBits <<= 1; Uart.parityBits ^= OddByteParity[(Uart.dropPosition & 0xff)]; Uart.bitCnt = 0; Uart.shiftReg = 0; Uart.nOutOfCnt = 0; Uart.dropPosition = 0; } } /*if(error) { Uart.output[Uart.byteCnt] = 0xAA; Uart.byteCnt++; Uart.output[Uart.byteCnt] = error & 0xFF; Uart.byteCnt++; Uart.output[Uart.byteCnt] = 0xAA; Uart.byteCnt++; Uart.output[Uart.byteCnt] = (Uart.bitBuffer >> 8) & 0xFF; Uart.byteCnt++; Uart.output[Uart.byteCnt] = Uart.bitBuffer & 0xFF; Uart.byteCnt++; Uart.output[Uart.byteCnt] = (Uart.syncBit >> 3) & 0xFF; Uart.byteCnt++; Uart.output[Uart.byteCnt] = 0xAA; Uart.byteCnt++; return TRUE; }*/ } } else { bit = Uart.bitBuffer & 0xf0; bit >>= 4; bit ^= 0x0F; // drops become 1s ;-) if(bit) { // should have been high or at least (4 * 128) / fc // according to ISO this should be at least (9 * 128 + 20) / fc if(Uart.highCnt == 8) { // we went low, so this could be start of communication // it turns out to be safer to choose a less significant // syncbit... so we check whether the neighbour also represents the drop Uart.posCnt = 1; // apparently we are busy with our first half bit period Uart.syncBit = bit & 8; Uart.samples = 3; if(!Uart.syncBit) { Uart.syncBit = bit & 4; Uart.samples = 2; } else if(bit & 4) { Uart.syncBit = bit & 4; Uart.samples = 2; bit <<= 2; } if(!Uart.syncBit) { Uart.syncBit = bit & 2; Uart.samples = 1; } else if(bit & 2) { Uart.syncBit = bit & 2; Uart.samples = 1; bit <<= 1; } if(!Uart.syncBit) { Uart.syncBit = bit & 1; Uart.samples = 0; if(Uart.syncBit && (Uart.bitBuffer & 8)) { Uart.syncBit = 8; // the first half bit period is expected in next sample Uart.posCnt = 0; Uart.samples = 3; } } else if(bit & 1) { Uart.syncBit = bit & 1; Uart.samples = 0; } Uart.syncBit <<= 4; Uart.state = STATE_START_OF_COMMUNICATION; Uart.bitCnt = 0; Uart.byteCnt = 0; Uart.parityBits = 0; Uart.nOutOfCnt = 0; Uart.OutOfCnt = 4; // Start at 1/4, could switch to 1/256 Uart.dropPosition = 0; Uart.shiftReg = 0; //error = 0; } else { Uart.highCnt = 0; } } else { if(Uart.highCnt < 8) { Uart.highCnt++; } } } return FALSE; } //============================================================================= // Manchester //============================================================================= static struct { enum { DEMOD_UNSYNCD, DEMOD_START_OF_COMMUNICATION, DEMOD_START_OF_COMMUNICATION2, DEMOD_START_OF_COMMUNICATION3, DEMOD_SOF_COMPLETE, DEMOD_MANCHESTER_D, DEMOD_MANCHESTER_E, DEMOD_END_OF_COMMUNICATION, DEMOD_END_OF_COMMUNICATION2, DEMOD_MANCHESTER_F, DEMOD_ERROR_WAIT } state; int bitCount; int posCount; int syncBit; int parityBits; uint16_t shiftReg; int buffer; int buffer2; int buffer3; int buff; int samples; int len; enum { SUB_NONE, SUB_FIRST_HALF, SUB_SECOND_HALF, SUB_BOTH } sub; uint8_t *output; } Demod; static RAMFUNC int ManchesterDecoding(int v) { int bit; int modulation; int error = 0; bit = Demod.buffer; Demod.buffer = Demod.buffer2; Demod.buffer2 = Demod.buffer3; Demod.buffer3 = v; if(Demod.buff < 3) { Demod.buff++; return FALSE; } if(Demod.state==DEMOD_UNSYNCD) { Demod.output[Demod.len] = 0xfa; Demod.syncBit = 0; //Demod.samples = 0; Demod.posCount = 1; // This is the first half bit period, so after syncing handle the second part if(bit & 0x08) { Demod.syncBit = 0x08; } if(bit & 0x04) { if(Demod.syncBit) { bit <<= 4; } Demod.syncBit = 0x04; } if(bit & 0x02) { if(Demod.syncBit) { bit <<= 2; } Demod.syncBit = 0x02; } if(bit & 0x01 && Demod.syncBit) { Demod.syncBit = 0x01; } if(Demod.syncBit) { Demod.len = 0; Demod.state = DEMOD_START_OF_COMMUNICATION; Demod.sub = SUB_FIRST_HALF; Demod.bitCount = 0; Demod.shiftReg = 0; Demod.parityBits = 0; Demod.samples = 0; if(Demod.posCount) { //if(trigger) LED_A_OFF(); // Not useful in this case... switch(Demod.syncBit) { case 0x08: Demod.samples = 3; break; case 0x04: Demod.samples = 2; break; case 0x02: Demod.samples = 1; break; case 0x01: Demod.samples = 0; break; } // SOF must be long burst... otherwise stay unsynced!!! if(!(Demod.buffer & Demod.syncBit) || !(Demod.buffer2 & Demod.syncBit)) { Demod.state = DEMOD_UNSYNCD; } } else { // SOF must be long burst... otherwise stay unsynced!!! if(!(Demod.buffer2 & Demod.syncBit) || !(Demod.buffer3 & Demod.syncBit)) { Demod.state = DEMOD_UNSYNCD; error = 0x88; } } error = 0; } } else { modulation = bit & Demod.syncBit; modulation |= ((bit << 1) ^ ((Demod.buffer & 0x08) >> 3)) & Demod.syncBit; //modulation = ((bit << 1) ^ ((Demod.buffer & 0x08) >> 3)) & Demod.syncBit; Demod.samples += 4; if(Demod.posCount==0) { Demod.posCount = 1; if(modulation) { Demod.sub = SUB_FIRST_HALF; } else { Demod.sub = SUB_NONE; } } else { Demod.posCount = 0; /*(modulation && (Demod.sub == SUB_FIRST_HALF)) { if(Demod.state!=DEMOD_ERROR_WAIT) { Demod.state = DEMOD_ERROR_WAIT; Demod.output[Demod.len] = 0xaa; error = 0x01; } }*/ //else if(modulation) { if(modulation) { if(Demod.sub == SUB_FIRST_HALF) { Demod.sub = SUB_BOTH; } else { Demod.sub = SUB_SECOND_HALF; } } else if(Demod.sub == SUB_NONE) { if(Demod.state == DEMOD_SOF_COMPLETE) { Demod.output[Demod.len] = 0x0f; Demod.len++; Demod.parityBits <<= 1; Demod.parityBits ^= OddByteParity[0x0f]; Demod.state = DEMOD_UNSYNCD; // error = 0x0f; return TRUE; } else { Demod.state = DEMOD_ERROR_WAIT; error = 0x33; } /*if(Demod.state!=DEMOD_ERROR_WAIT) { Demod.state = DEMOD_ERROR_WAIT; Demod.output[Demod.len] = 0xaa; error = 0x01; }*/ } switch(Demod.state) { case DEMOD_START_OF_COMMUNICATION: if(Demod.sub == SUB_BOTH) { //Demod.state = DEMOD_MANCHESTER_D; Demod.state = DEMOD_START_OF_COMMUNICATION2; Demod.posCount = 1; Demod.sub = SUB_NONE; } else { Demod.output[Demod.len] = 0xab; Demod.state = DEMOD_ERROR_WAIT; error = 0xd2; } break; case DEMOD_START_OF_COMMUNICATION2: if(Demod.sub == SUB_SECOND_HALF) { Demod.state = DEMOD_START_OF_COMMUNICATION3; } else { Demod.output[Demod.len] = 0xab; Demod.state = DEMOD_ERROR_WAIT; error = 0xd3; } break; case DEMOD_START_OF_COMMUNICATION3: if(Demod.sub == SUB_SECOND_HALF) { // Demod.state = DEMOD_MANCHESTER_D; Demod.state = DEMOD_SOF_COMPLETE; //Demod.output[Demod.len] = Demod.syncBit & 0xFF; //Demod.len++; } else { Demod.output[Demod.len] = 0xab; Demod.state = DEMOD_ERROR_WAIT; error = 0xd4; } break; case DEMOD_SOF_COMPLETE: case DEMOD_MANCHESTER_D: case DEMOD_MANCHESTER_E: // OPPOSITE FROM ISO14443 - 11110000 = 0 (1 in 14443) // 00001111 = 1 (0 in 14443) if(Demod.sub == SUB_SECOND_HALF) { // SUB_FIRST_HALF Demod.bitCount++; Demod.shiftReg = (Demod.shiftReg >> 1) ^ 0x100; Demod.state = DEMOD_MANCHESTER_D; } else if(Demod.sub == SUB_FIRST_HALF) { // SUB_SECOND_HALF Demod.bitCount++; Demod.shiftReg >>= 1; Demod.state = DEMOD_MANCHESTER_E; } else if(Demod.sub == SUB_BOTH) { Demod.state = DEMOD_MANCHESTER_F; } else { Demod.state = DEMOD_ERROR_WAIT; error = 0x55; } break; case DEMOD_MANCHESTER_F: // Tag response does not need to be a complete byte! if(Demod.len > 0 || Demod.bitCount > 0) { if(Demod.bitCount > 1) { // was > 0, do not interpret last closing bit, is part of EOF Demod.shiftReg >>= (9 - Demod.bitCount); Demod.output[Demod.len] = Demod.shiftReg & 0xff; Demod.len++; // No parity bit, so just shift a 0 Demod.parityBits <<= 1; } Demod.state = DEMOD_UNSYNCD; return TRUE; } else { Demod.output[Demod.len] = 0xad; Demod.state = DEMOD_ERROR_WAIT; error = 0x03; } break; case DEMOD_ERROR_WAIT: Demod.state = DEMOD_UNSYNCD; break; default: Demod.output[Demod.len] = 0xdd; Demod.state = DEMOD_UNSYNCD; break; } /*if(Demod.bitCount>=9) { Demod.output[Demod.len] = Demod.shiftReg & 0xff; Demod.len++; Demod.parityBits <<= 1; Demod.parityBits ^= ((Demod.shiftReg >> 8) & 0x01); Demod.bitCount = 0; Demod.shiftReg = 0; }*/ if(Demod.bitCount>=8) { Demod.shiftReg >>= 1; Demod.output[Demod.len] = (Demod.shiftReg & 0xff); Demod.len++; // FOR ISO15639 PARITY NOT SEND OTA, JUST CALCULATE IT FOR THE CLIENT Demod.parityBits <<= 1; Demod.parityBits ^= OddByteParity[(Demod.shiftReg & 0xff)]; Demod.bitCount = 0; Demod.shiftReg = 0; } if(error) { Demod.output[Demod.len] = 0xBB; Demod.len++; Demod.output[Demod.len] = error & 0xFF; Demod.len++; Demod.output[Demod.len] = 0xBB; Demod.len++; Demod.output[Demod.len] = bit & 0xFF; Demod.len++; Demod.output[Demod.len] = Demod.buffer & 0xFF; Demod.len++; // Look harder ;-) Demod.output[Demod.len] = Demod.buffer2 & 0xFF; Demod.len++; Demod.output[Demod.len] = Demod.syncBit & 0xFF; Demod.len++; Demod.output[Demod.len] = 0xBB; Demod.len++; return TRUE; } } } // end (state != UNSYNCED) return FALSE; } //============================================================================= // Finally, a `sniffer' for iClass communication // Both sides of communication! //============================================================================= //----------------------------------------------------------------------------- // Record the sequence of commands sent by the reader to the tag, with // triggering so that we start recording at the point that the tag is moved // near the reader. //----------------------------------------------------------------------------- void RAMFUNC SnoopIClass(void) { // DEFINED ABOVE // #define RECV_CMD_OFFSET 3032 // #define RECV_RES_OFFSET 3096 // #define DMA_BUFFER_OFFSET 3160 // #define DMA_BUFFER_SIZE 4096 // #define TRACE_SIZE 3000 // We won't start recording the frames that we acquire until we trigger; // a good trigger condition to get started is probably when we see a // response from the tag. //int triggered = FALSE; // FALSE to wait first for card // The command (reader -> tag) that we're receiving. // The length of a received command will in most cases be no more than 18 bytes. // So 32 should be enough! uint8_t *receivedCmd = (((uint8_t *)BigBuf) + RECV_CMD_OFFSET); // The response (tag -> reader) that we're receiving. uint8_t *receivedResponse = (((uint8_t *)BigBuf) + RECV_RES_OFFSET); // As we receive stuff, we copy it from receivedCmd or receivedResponse // into trace, along with its length and other annotations. //uint8_t *trace = (uint8_t *)BigBuf; // reset traceLen to 0 iso14a_set_tracing(TRUE); iso14a_clear_trace(); iso14a_set_trigger(FALSE); // The DMA buffer, used to stream samples from the FPGA int8_t *dmaBuf = ((int8_t *)BigBuf) + DMA_BUFFER_OFFSET; int lastRxCounter; int8_t *upTo; int smpl; int maxBehindBy = 0; // Count of samples received so far, so that we can include timing // information in the trace buffer. int samples = 0; rsamples = 0; memset(trace, 0x44, RECV_CMD_OFFSET); // Set up the demodulator for tag -> reader responses. Demod.output = receivedResponse; Demod.len = 0; Demod.state = DEMOD_UNSYNCD; // Setup for the DMA. FpgaSetupSsc(); upTo = dmaBuf; lastRxCounter = DMA_BUFFER_SIZE; FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // And the reader -> tag commands memset(&Uart, 0, sizeof(Uart)); Uart.output = receivedCmd; Uart.byteCntMax = 32; // was 100 (greg)//////////////////////////////////////////////////////////////////////// Uart.state = STATE_UNSYNCD; // And put the FPGA in the appropriate mode // Signal field is off with the appropriate LED LED_D_OFF(); FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_SNIFFER); SetAdcMuxFor(GPIO_MUXSEL_HIPKD); int div = 0; //int div2 = 0; int decbyte = 0; int decbyter = 0; // And now we loop, receiving samples. for(;;) { LED_A_ON(); WDT_HIT(); int behindBy = (lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) & (DMA_BUFFER_SIZE-1); if(behindBy > maxBehindBy) { maxBehindBy = behindBy; if(behindBy > 400) { Dbprintf("blew circular buffer! behindBy=0x%x", behindBy); goto done; } } if(behindBy < 1) continue; LED_A_OFF(); smpl = upTo[0]; upTo++; lastRxCounter -= 1; if(upTo - dmaBuf > DMA_BUFFER_SIZE) { upTo -= DMA_BUFFER_SIZE; lastRxCounter += DMA_BUFFER_SIZE; AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo; AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE; } //samples += 4; samples += 1; //div2++; //if(div2 > 3) { //div2 = 0; //decbyte ^= ((smpl & 0x01) << (3 - div)); //decbyte ^= (((smpl & 0x01) | ((smpl & 0x02) >> 1)) << (3 - div)); // better already... //decbyte ^= (((smpl & 0x01) | ((smpl & 0x02) >> 1) | ((smpl & 0x04) >> 2)) << (3 - div)); // even better... if(smpl & 0xF) { decbyte ^= (1 << (3 - div)); } //decbyte ^= (MajorityNibble[(smpl & 0x0F)] << (3 - div)); // FOR READER SIDE COMMUMICATION... //decbyte ^= ((smpl & 0x10) << (3 - div)); decbyter <<= 2; decbyter ^= (smpl & 0x30); div++; if((div + 1) % 2 == 0) { smpl = decbyter; if(OutOfNDecoding((smpl & 0xF0) >> 4)) { rsamples = samples - Uart.samples; LED_C_ON(); //if(triggered) { trace[traceLen++] = ((rsamples >> 0) & 0xff); trace[traceLen++] = ((rsamples >> 8) & 0xff); trace[traceLen++] = ((rsamples >> 16) & 0xff); trace[traceLen++] = ((rsamples >> 24) & 0xff); trace[traceLen++] = ((Uart.parityBits >> 0) & 0xff); trace[traceLen++] = ((Uart.parityBits >> 8) & 0xff); trace[traceLen++] = ((Uart.parityBits >> 16) & 0xff); trace[traceLen++] = ((Uart.parityBits >> 24) & 0xff); trace[traceLen++] = Uart.byteCnt; memcpy(trace+traceLen, receivedCmd, Uart.byteCnt); traceLen += Uart.byteCnt; if(traceLen > TRACE_SIZE) break; //} /* And ready to receive another command. */ Uart.state = STATE_UNSYNCD; /* And also reset the demod code, which might have been */ /* false-triggered by the commands from the reader. */ Demod.state = DEMOD_UNSYNCD; LED_B_OFF(); Uart.byteCnt = 0; } decbyter = 0; } if(div > 3) { smpl = decbyte; if(ManchesterDecoding(smpl & 0x0F)) { rsamples = samples - Demod.samples; LED_B_ON(); // timestamp, as a count of samples trace[traceLen++] = ((rsamples >> 0) & 0xff); trace[traceLen++] = ((rsamples >> 8) & 0xff); trace[traceLen++] = ((rsamples >> 16) & 0xff); trace[traceLen++] = 0x80 | ((rsamples >> 24) & 0xff); trace[traceLen++] = ((Demod.parityBits >> 0) & 0xff); trace[traceLen++] = ((Demod.parityBits >> 8) & 0xff); trace[traceLen++] = ((Demod.parityBits >> 16) & 0xff); trace[traceLen++] = ((Demod.parityBits >> 24) & 0xff); // length trace[traceLen++] = Demod.len; memcpy(trace+traceLen, receivedResponse, Demod.len); traceLen += Demod.len; if(traceLen > TRACE_SIZE) break; //triggered = TRUE; // And ready to receive another response. memset(&Demod, 0, sizeof(Demod)); Demod.output = receivedResponse; Demod.state = DEMOD_UNSYNCD; LED_C_OFF(); } div = 0; decbyte = 0x00; } //} if(BUTTON_PRESS()) { DbpString("cancelled_a"); goto done; } } DbpString("COMMAND FINISHED"); Dbprintf("%x %x %x", maxBehindBy, Uart.state, Uart.byteCnt); Dbprintf("%x %x %x", Uart.byteCntMax, traceLen, (int)Uart.output[0]); done: AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS; Dbprintf("%x %x %x", maxBehindBy, Uart.state, Uart.byteCnt); Dbprintf("%x %x %x", Uart.byteCntMax, traceLen, (int)Uart.output[0]); LED_A_OFF(); LED_B_OFF(); LED_C_OFF(); LED_D_OFF(); } void rotateCSN(uint8_t* originalCSN, uint8_t* rotatedCSN) { int i; for(i = 0; i < 8; i++) { rotatedCSN[i] = (originalCSN[i] >> 3) | (originalCSN[(i+1)%8] << 5); } } //----------------------------------------------------------------------------- // Wait for commands from reader // Stop when button is pressed // Or return TRUE when command is captured //----------------------------------------------------------------------------- static int GetIClassCommandFromReader(uint8_t *received, int *len, int maxLen) { // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen // only, since we are receiving, not transmitting). // Signal field is off with the appropriate LED LED_D_OFF(); FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN); // Now run a `software UART' on the stream of incoming samples. Uart.output = received; Uart.byteCntMax = maxLen; Uart.state = STATE_UNSYNCD; for(;;) { WDT_HIT(); if(BUTTON_PRESS()) return FALSE; if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { AT91C_BASE_SSC->SSC_THR = 0x00; } if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR; /*if(OutOfNDecoding((b & 0xf0) >> 4)) { *len = Uart.byteCnt; return TRUE; }*/ if(OutOfNDecoding(b & 0x0f)) { *len = Uart.byteCnt; return TRUE; } } } } //----------------------------------------------------------------------------- // Prepare tag messages //----------------------------------------------------------------------------- static void CodeIClassTagAnswer(const uint8_t *cmd, int len) { int i; ToSendReset(); // Send SOF ToSend[++ToSendMax] = 0x00; ToSend[++ToSendMax] = 0x00; ToSend[++ToSendMax] = 0x00; ToSend[++ToSendMax] = 0xff; ToSend[++ToSendMax] = 0xff; ToSend[++ToSendMax] = 0xff; ToSend[++ToSendMax] = 0x00; ToSend[++ToSendMax] = 0xff; for(i = 0; i < len; i++) { int j; uint8_t b = cmd[i]; // Data bits for(j = 0; j < 8; j++) { if(b & 1) { ToSend[++ToSendMax] = 0x00; ToSend[++ToSendMax] = 0xff; } else { ToSend[++ToSendMax] = 0xff; ToSend[++ToSendMax] = 0x00; } b >>= 1; } } // Send EOF ToSend[++ToSendMax] = 0xff; ToSend[++ToSendMax] = 0x00; ToSend[++ToSendMax] = 0xff; ToSend[++ToSendMax] = 0xff; ToSend[++ToSendMax] = 0xff; ToSend[++ToSendMax] = 0x00; ToSend[++ToSendMax] = 0x00; ToSend[++ToSendMax] = 0x00; // Convert from last byte pos to length ToSendMax++; } // Only SOF static void CodeIClassTagSOF() { ToSendReset(); // Send SOF ToSend[++ToSendMax] = 0x00; ToSend[++ToSendMax] = 0x00; ToSend[++ToSendMax] = 0x00; ToSend[++ToSendMax] = 0xff; ToSend[++ToSendMax] = 0xff; ToSend[++ToSendMax] = 0xff; ToSend[++ToSendMax] = 0x00; ToSend[++ToSendMax] = 0xff; // Convert from last byte pos to length ToSendMax++; } //----------------------------------------------------------------------------- // Simulate iClass Card // Only CSN (Card Serial Number) // //----------------------------------------------------------------------------- void SimulateIClass(uint8_t arg0, uint8_t *datain) { uint8_t simType = arg0; // Enable and clear the trace tracing = TRUE; traceLen = 0; memset(trace, 0x44, TRACE_SIZE); // CSN followed by two CRC bytes uint8_t response2[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; uint8_t response3[] = { 0x03, 0x1f, 0xec, 0x8a, 0xf7, 0xff, 0x12, 0xe0, 0x00, 0x00 }; // e-Purse uint8_t response4[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; if(simType == 0) { // Use the CSN from commandline memcpy(response3, datain, 8); } // Construct anticollision-CSN rotateCSN(response3,response2); // Compute CRC on both CSNs ComputeCrc14443(CRC_ICLASS, response2, 8, &response2[8], &response2[9]); ComputeCrc14443(CRC_ICLASS, response3, 8, &response3[8], &response3[9]); // Reader 0a // Tag 0f // Reader 0c // Tag anticoll. CSN // Reader 81 anticoll. CSN // Tag CSN uint8_t *resp; int respLen; uint8_t* respdata = NULL; int respsize = 0; uint8_t sof = 0x0f; // Respond SOF -- takes 8 bytes uint8_t *resp1 = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET); int resp1Len; // Anticollision CSN (rotated CSN) // 176: Takes 16 bytes for SOF/EOF and 10 * 16 = 160 bytes (2 bytes/bit) uint8_t *resp2 = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET + 10); int resp2Len; // CSN // 176: Takes 16 bytes for SOF/EOF and 10 * 16 = 160 bytes (2 bytes/bit) uint8_t *resp3 = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET + 190); int resp3Len; // e-Purse // 144: Takes 16 bytes for SOF/EOF and 8 * 16 = 128 bytes (2 bytes/bit) uint8_t *resp4 = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET + 370); int resp4Len; // + 1720.. uint8_t *receivedCmd = (((uint8_t *)BigBuf) + RECV_CMD_OFFSET); memset(receivedCmd, 0x44, RECV_CMD_SIZE); int len; // Prepare card messages ToSendMax = 0; // First card answer: SOF CodeIClassTagSOF(); memcpy(resp1, ToSend, ToSendMax); resp1Len = ToSendMax; // Anticollision CSN CodeIClassTagAnswer(response2, sizeof(response2)); memcpy(resp2, ToSend, ToSendMax); resp2Len = ToSendMax; // CSN CodeIClassTagAnswer(response3, sizeof(response3)); memcpy(resp3, ToSend, ToSendMax); resp3Len = ToSendMax; // e-Purse CodeIClassTagAnswer(response4, sizeof(response4)); memcpy(resp4, ToSend, ToSendMax); resp4Len = ToSendMax; // We need to listen to the high-frequency, peak-detected path. SetAdcMuxFor(GPIO_MUXSEL_HIPKD); FpgaSetupSsc(); // To control where we are in the protocol int cmdsRecvd = 0; LED_A_ON(); for(;;) { LED_B_OFF(); if(!GetIClassCommandFromReader(receivedCmd, &len, 100)) { DbpString("button press"); break; } // Okay, look at the command now. if(receivedCmd[0] == 0x0a) { // Reader in anticollission phase resp = resp1; respLen = resp1Len; //order = 1; respdata = &sof; respsize = sizeof(sof); //resp = resp2; respLen = resp2Len; order = 2; //DbpString("Hello request from reader:"); } else if(receivedCmd[0] == 0x0c) { // Reader asks for anticollission CSN resp = resp2; respLen = resp2Len; //order = 2; respdata = response2; respsize = sizeof(response2); //DbpString("Reader requests anticollission CSN:"); } else if(receivedCmd[0] == 0x81) { // Reader selects anticollission CSN. // Tag sends the corresponding real CSN resp = resp3; respLen = resp3Len; //order = 3; respdata = response3; respsize = sizeof(response3); //DbpString("Reader selects anticollission CSN:"); } else if(receivedCmd[0] == 0x88) { // Read e-purse (88 02) resp = resp4; respLen = resp4Len; //order = 4; respdata = response4; respsize = sizeof(response4); LED_B_ON(); } else if(receivedCmd[0] == 0x05) { // Reader random and reader MAC!!! // Lets store this ;-) /* Dbprintf(" CSN: %02x %02x %02x %02x %02x %02x %02x %02x", response3[0], response3[1], response3[2], response3[3], response3[4], response3[5], response3[6], response3[7]); */ Dbprintf("READER AUTH (len=%02d): %02x %02x %02x %02x %02x %02x %02x %02x %02x", len, receivedCmd[0], receivedCmd[1], receivedCmd[2], receivedCmd[3], receivedCmd[4], receivedCmd[5], receivedCmd[6], receivedCmd[7], receivedCmd[8]); // Do not respond // We do not know what to answer, so lets keep quit resp = resp1; respLen = 0; //order = 5; respdata = NULL; respsize = 0; } else if(receivedCmd[0] == 0x00 && len == 1) { // Reader ends the session resp = resp1; respLen = 0; //order = 0; respdata = NULL; respsize = 0; } else { // Never seen this command before Dbprintf("Unknown command received from reader (len=%d): %x %x %x %x %x %x %x %x %x", len, receivedCmd[0], receivedCmd[1], receivedCmd[2], receivedCmd[3], receivedCmd[4], receivedCmd[5], receivedCmd[6], receivedCmd[7], receivedCmd[8]); // Do not respond resp = resp1; respLen = 0; //order = 0; respdata = NULL; respsize = 0; } if(cmdsRecvd > 999) { DbpString("1000 commands later..."); break; } else { cmdsRecvd++; } if(respLen > 0) { SendIClassAnswer(resp, respLen, 21); } if (tracing) { LogTrace(receivedCmd,len, 0, Uart.parityBits, TRUE); if (respdata != NULL) { LogTrace(respdata,respsize, 0, SwapBits(GetParity(respdata,respsize),respsize), FALSE); } if(traceLen > TRACE_SIZE) { DbpString("Trace full"); break; } } memset(receivedCmd, 0x44, RECV_CMD_SIZE); } Dbprintf("%x", cmdsRecvd); LED_A_OFF(); LED_B_OFF(); } static int SendIClassAnswer(uint8_t *resp, int respLen, int delay) { int i = 0, u = 0, d = 0; uint8_t b = 0; // return 0; // Modulate Manchester // FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD424); FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD); AT91C_BASE_SSC->SSC_THR = 0x00; FpgaSetupSsc(); // send cycle for(;;) { if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { volatile uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR; (void)b; } if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { if(d < delay) { b = 0x00; d++; } else if(i >= respLen) { b = 0x00; u++; } else { b = resp[i]; u++; if(u > 1) { i++; u = 0; } } AT91C_BASE_SSC->SSC_THR = b; if(u > 4) break; } if(BUTTON_PRESS()) { break; } } return 0; } /// THE READER CODE //----------------------------------------------------------------------------- // Transmit the command (to the tag) that was placed in ToSend[]. //----------------------------------------------------------------------------- static void TransmitIClassCommand(const uint8_t *cmd, int len, int *samples, int *wait) { int c; FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD); AT91C_BASE_SSC->SSC_THR = 0x00; FpgaSetupSsc(); if (wait) if(*wait < 10) *wait = 10; for(c = 0; c < *wait;) { if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { AT91C_BASE_SSC->SSC_THR = 0x00; // For exact timing! c++; } if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR; (void)r; } WDT_HIT(); } uint8_t sendbyte; bool firstpart = TRUE; c = 0; for(;;) { if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { // DOUBLE THE SAMPLES! if(firstpart) { sendbyte = (cmd[c] & 0xf0) | (cmd[c] >> 4); } else { sendbyte = (cmd[c] & 0x0f) | (cmd[c] << 4); c++; } if(sendbyte == 0xff) { sendbyte = 0xfe; } AT91C_BASE_SSC->SSC_THR = sendbyte; firstpart = !firstpart; if(c >= len) { break; } } if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR; (void)r; } WDT_HIT(); } if (samples) *samples = (c + *wait) << 3; } //----------------------------------------------------------------------------- // Prepare iClass reader command to send to FPGA //----------------------------------------------------------------------------- void CodeIClassCommand(const uint8_t * cmd, int len) { int i, j, k; uint8_t b; ToSendReset(); // Start of Communication: 1 out of 4 ToSend[++ToSendMax] = 0xf0; ToSend[++ToSendMax] = 0x00; ToSend[++ToSendMax] = 0x0f; ToSend[++ToSendMax] = 0x00; // Modulate the bytes for (i = 0; i < len; i++) { b = cmd[i]; for(j = 0; j < 4; j++) { for(k = 0; k < 4; k++) { if(k == (b & 3)) { ToSend[++ToSendMax] = 0x0f; } else { ToSend[++ToSendMax] = 0x00; } } b >>= 2; } } // End of Communication ToSend[++ToSendMax] = 0x00; ToSend[++ToSendMax] = 0x00; ToSend[++ToSendMax] = 0xf0; ToSend[++ToSendMax] = 0x00; // Convert from last character reference to length ToSendMax++; } void ReaderTransmitIClass(uint8_t* frame, int len) { int wait = 0; int samples = 0; int par = 0; // This is tied to other size changes // uint8_t* frame_addr = ((uint8_t*)BigBuf) + 2024; CodeIClassCommand(frame,len); // Select the card TransmitIClassCommand(ToSend, ToSendMax, &samples, &wait); if(trigger) LED_A_ON(); // Store reader command in buffer if (tracing) LogTrace(frame,len,0,par,TRUE); } //----------------------------------------------------------------------------- // Wait a certain time for tag response // If a response is captured return TRUE // If it takes too long return FALSE //----------------------------------------------------------------------------- static int GetIClassAnswer(uint8_t *receivedResponse, int maxLen, int *samples, int *elapsed) //uint8_t *buffer { // buffer needs to be 512 bytes int c; // Set FPGA mode to "reader listen mode", no modulation (listen // only, since we are receiving, not transmitting). FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN); // Now get the answer from the card Demod.output = receivedResponse; Demod.len = 0; Demod.state = DEMOD_UNSYNCD; uint8_t b; if (elapsed) *elapsed = 0; bool skip = FALSE; c = 0; for(;;) { WDT_HIT(); if(BUTTON_PRESS()) return FALSE; if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { AT91C_BASE_SSC->SSC_THR = 0x00; // To make use of exact timing of next command from reader!! if (elapsed) (*elapsed)++; } if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { if(c < timeout) { c++; } else { return FALSE; } b = (uint8_t)AT91C_BASE_SSC->SSC_RHR; skip = !skip; if(skip) continue; /*if(ManchesterDecoding((b>>4) & 0xf)) { *samples = ((c - 1) << 3) + 4; return TRUE; }*/ if(ManchesterDecoding(b & 0x0f)) { *samples = c << 3; return TRUE; } } } } int ReaderReceiveIClass(uint8_t* receivedAnswer) { int samples = 0; if (!GetIClassAnswer(receivedAnswer,160,&samples,0)) return FALSE; if (tracing) LogTrace(receivedAnswer,Demod.len,samples,Demod.parityBits,FALSE); if(samples == 0) return FALSE; return Demod.len; } // Reader iClass Anticollission void ReaderIClass(uint8_t arg0) { uint8_t act_all[] = { 0x0a }; uint8_t identify[] = { 0x0c }; uint8_t select[] = { 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; uint8_t* resp = (((uint8_t *)BigBuf) + 3560); // was 3560 - tied to other size changes // Reset trace buffer memset(trace, 0x44, RECV_CMD_OFFSET); traceLen = 0; // Setup SSC FpgaSetupSsc(); // Start from off (no field generated) // Signal field is off with the appropriate LED LED_D_OFF(); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); SpinDelay(200); SetAdcMuxFor(GPIO_MUXSEL_HIPKD); // Now give it time to spin up. // Signal field is on with the appropriate LED FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD); SpinDelay(200); LED_A_ON(); for(;;) { if(traceLen > TRACE_SIZE) { DbpString("Trace full"); break; } if (BUTTON_PRESS()) break; // Send act_all ReaderTransmitIClass(act_all, 1); // Card present? if(ReaderReceiveIClass(resp)) { ReaderTransmitIClass(identify, 1); if(ReaderReceiveIClass(resp) == 10) { // Select card memcpy(&select[1],resp,8); ReaderTransmitIClass(select, sizeof(select)); if(ReaderReceiveIClass(resp) == 10) { Dbprintf(" Selected CSN: %02x %02x %02x %02x %02x %02x %02x %02x", resp[0], resp[1], resp[2], resp[3], resp[4], resp[5], resp[6], resp[7]); } // Card selected, whats next... ;-) } } WDT_HIT(); } LED_A_OFF(); } ================================================ FILE: TamagotchiFriends/proxmark/armsrc/iso14443.c ================================================ //----------------------------------------------------------------------------- // Jonathan Westhues, split Nov 2006 // // This code is licensed to you under the terms of the GNU GPL, version 2 or, // at your option, any later version. See the LICENSE.txt file for the text of // the license. //----------------------------------------------------------------------------- // Routines to support ISO 14443. This includes both the reader software and // the `fake tag' modes. At the moment only the Type B modulation is // supported. //----------------------------------------------------------------------------- #include "proxmark3.h" #include "apps.h" #include "util.h" #include "string.h" #include "iso14443crc.h" //static void GetSamplesFor14443(int weTx, int n); #define DEMOD_TRACE_SIZE 4096 #define READER_TAG_BUFFER_SIZE 2048 #define TAG_READER_BUFFER_SIZE 2048 #define DEMOD_DMA_BUFFER_SIZE 1024 //============================================================================= // An ISO 14443 Type B tag. We listen for commands from the reader, using // a UART kind of thing that's implemented in software. When we get a // frame (i.e., a group of bytes between SOF and EOF), we check the CRC. // If it's good, then we can do something appropriate with it, and send // a response. //============================================================================= //----------------------------------------------------------------------------- // Code up a string of octets at layer 2 (including CRC, we don't generate // that here) so that they can be transmitted to the reader. Doesn't transmit // them yet, just leaves them ready to send in ToSend[]. //----------------------------------------------------------------------------- static void CodeIso14443bAsTag(const uint8_t *cmd, int len) { int i; ToSendReset(); // Transmit a burst of ones, as the initial thing that lets the // reader get phase sync. This (TR1) must be > 80/fs, per spec, // but tag that I've tried (a Paypass) exceeds that by a fair bit, // so I will too. for(i = 0; i < 20; i++) { ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(1); } // Send SOF. for(i = 0; i < 10; i++) { ToSendStuffBit(0); ToSendStuffBit(0); ToSendStuffBit(0); ToSendStuffBit(0); } for(i = 0; i < 2; i++) { ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(1); } for(i = 0; i < len; i++) { int j; uint8_t b = cmd[i]; // Start bit ToSendStuffBit(0); ToSendStuffBit(0); ToSendStuffBit(0); ToSendStuffBit(0); // Data bits for(j = 0; j < 8; j++) { if(b & 1) { ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(1); } else { ToSendStuffBit(0); ToSendStuffBit(0); ToSendStuffBit(0); ToSendStuffBit(0); } b >>= 1; } // Stop bit ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(1); } // Send SOF. for(i = 0; i < 10; i++) { ToSendStuffBit(0); ToSendStuffBit(0); ToSendStuffBit(0); ToSendStuffBit(0); } for(i = 0; i < 10; i++) { ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(1); } // Convert from last byte pos to length ToSendMax++; // Add a few more for slop ToSendMax += 2; } //----------------------------------------------------------------------------- // The software UART that receives commands from the reader, and its state // variables. //----------------------------------------------------------------------------- static struct { enum { STATE_UNSYNCD, STATE_GOT_FALLING_EDGE_OF_SOF, STATE_AWAITING_START_BIT, STATE_RECEIVING_DATA, STATE_ERROR_WAIT } state; uint16_t shiftReg; int bitCnt; int byteCnt; int byteCntMax; int posCnt; uint8_t *output; } Uart; /* Receive & handle a bit coming from the reader. * * LED handling: * LED A -> ON once we have received the SOF and are expecting the rest. * LED A -> OFF once we have received EOF or are in error state or unsynced * * Returns: true if we received a EOF * false if we are still waiting for some more */ static int Handle14443UartBit(int bit) { switch(Uart.state) { case STATE_UNSYNCD: LED_A_OFF(); if(!bit) { // we went low, so this could be the beginning // of an SOF Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF; Uart.posCnt = 0; Uart.bitCnt = 0; } break; case STATE_GOT_FALLING_EDGE_OF_SOF: Uart.posCnt++; if(Uart.posCnt == 2) { if(bit) { if(Uart.bitCnt >= 10) { // we've seen enough consecutive // zeros that it's a valid SOF Uart.posCnt = 0; Uart.byteCnt = 0; Uart.state = STATE_AWAITING_START_BIT; LED_A_ON(); // Indicate we got a valid SOF } else { // didn't stay down long enough // before going high, error Uart.state = STATE_ERROR_WAIT; } } else { // do nothing, keep waiting } Uart.bitCnt++; } if(Uart.posCnt >= 4) Uart.posCnt = 0; if(Uart.bitCnt > 14) { // Give up if we see too many zeros without // a one, too. Uart.state = STATE_ERROR_WAIT; } break; case STATE_AWAITING_START_BIT: Uart.posCnt++; if(bit) { if(Uart.posCnt > 25) { // stayed high for too long between // characters, error Uart.state = STATE_ERROR_WAIT; } } else { // falling edge, this starts the data byte Uart.posCnt = 0; Uart.bitCnt = 0; Uart.shiftReg = 0; Uart.state = STATE_RECEIVING_DATA; LED_A_ON(); // Indicate we're receiving } break; case STATE_RECEIVING_DATA: Uart.posCnt++; if(Uart.posCnt == 2) { // time to sample a bit Uart.shiftReg >>= 1; if(bit) { Uart.shiftReg |= 0x200; } Uart.bitCnt++; } if(Uart.posCnt >= 4) { Uart.posCnt = 0; } if(Uart.bitCnt == 10) { if((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001)) { // this is a data byte, with correct // start and stop bits Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff; Uart.byteCnt++; if(Uart.byteCnt >= Uart.byteCntMax) { // Buffer overflowed, give up Uart.posCnt = 0; Uart.state = STATE_ERROR_WAIT; } else { // so get the next byte now Uart.posCnt = 0; Uart.state = STATE_AWAITING_START_BIT; } } else if(Uart.shiftReg == 0x000) { // this is an EOF byte LED_A_OFF(); // Finished receiving return TRUE; } else { // this is an error Uart.posCnt = 0; Uart.state = STATE_ERROR_WAIT; } } break; case STATE_ERROR_WAIT: // We're all screwed up, so wait a little while // for whatever went wrong to finish, and then // start over. Uart.posCnt++; if(Uart.posCnt > 10) { Uart.state = STATE_UNSYNCD; } break; default: Uart.state = STATE_UNSYNCD; break; } if (Uart.state == STATE_ERROR_WAIT) LED_A_OFF(); // Error return FALSE; } //----------------------------------------------------------------------------- // Receive a command (from the reader to us, where we are the simulated tag), // and store it in the given buffer, up to the given maximum length. Keeps // spinning, waiting for a well-framed command, until either we get one // (returns TRUE) or someone presses the pushbutton on the board (FALSE). // // Assume that we're called with the SSC (to the FPGA) and ADC path set // correctly. //----------------------------------------------------------------------------- static int GetIso14443CommandFromReader(uint8_t *received, int *len, int maxLen) { uint8_t mask; int i, bit; // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen // only, since we are receiving, not transmitting). // Signal field is off with the appropriate LED LED_D_OFF(); FpgaWriteConfWord( FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_NO_MODULATION); // Now run a `software UART' on the stream of incoming samples. Uart.output = received; Uart.byteCntMax = maxLen; Uart.state = STATE_UNSYNCD; for(;;) { WDT_HIT(); if(BUTTON_PRESS()) return FALSE; if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { AT91C_BASE_SSC->SSC_THR = 0x00; } if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR; mask = 0x80; for(i = 0; i < 8; i++, mask >>= 1) { bit = (b & mask); if(Handle14443UartBit(bit)) { *len = Uart.byteCnt; return TRUE; } } } } } //----------------------------------------------------------------------------- // Main loop of simulated tag: receive commands from reader, decide what // response to send, and send it. //----------------------------------------------------------------------------- void SimulateIso14443Tag(void) { static const uint8_t cmd1[] = { 0x05, 0x00, 0x08, 0x39, 0x73 }; static const uint8_t response1[] = { 0x50, 0x82, 0x0d, 0xe1, 0x74, 0x20, 0x38, 0x19, 0x22, 0x00, 0x21, 0x85, 0x5e, 0xd7 }; uint8_t *resp; int respLen; uint8_t *resp1 = (((uint8_t *)BigBuf) + 800); int resp1Len; uint8_t *receivedCmd = (uint8_t *)BigBuf; int len; int i; int cmdsRecvd = 0; memset(receivedCmd, 0x44, 400); CodeIso14443bAsTag(response1, sizeof(response1)); memcpy(resp1, ToSend, ToSendMax); resp1Len = ToSendMax; // We need to listen to the high-frequency, peak-detected path. SetAdcMuxFor(GPIO_MUXSEL_HIPKD); FpgaSetupSsc(); cmdsRecvd = 0; for(;;) { uint8_t b1, b2; if(!GetIso14443CommandFromReader(receivedCmd, &len, 100)) { Dbprintf("button pressed, received %d commands", cmdsRecvd); break; } // Good, look at the command now. if(len == sizeof(cmd1) && memcmp(receivedCmd, cmd1, len)==0) { resp = resp1; respLen = resp1Len; } else { Dbprintf("new cmd from reader: len=%d, cmdsRecvd=%d", len, cmdsRecvd); // And print whether the CRC fails, just for good measure ComputeCrc14443(CRC_14443_B, receivedCmd, len-2, &b1, &b2); if(b1 != receivedCmd[len-2] || b2 != receivedCmd[len-1]) { // Not so good, try again. DbpString("+++CRC fail"); } else { DbpString("CRC passes"); } break; } memset(receivedCmd, 0x44, 32); cmdsRecvd++; if(cmdsRecvd > 0x30) { DbpString("many commands later..."); break; } if(respLen <= 0) continue; // Modulate BPSK // Signal field is off with the appropriate LED LED_D_OFF(); FpgaWriteConfWord( FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_BPSK); AT91C_BASE_SSC->SSC_THR = 0xff; FpgaSetupSsc(); // Transmit the response. i = 0; for(;;) { if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { uint8_t b = resp[i]; AT91C_BASE_SSC->SSC_THR = b; i++; if(i > respLen) { break; } } if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { volatile uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR; (void)b; } } } } //============================================================================= // An ISO 14443 Type B reader. We take layer two commands, code them // appropriately, and then send them to the tag. We then listen for the // tag's response, which we leave in the buffer to be demodulated on the // PC side. //============================================================================= static struct { enum { DEMOD_UNSYNCD, DEMOD_PHASE_REF_TRAINING, DEMOD_AWAITING_FALLING_EDGE_OF_SOF, DEMOD_GOT_FALLING_EDGE_OF_SOF, DEMOD_AWAITING_START_BIT, DEMOD_RECEIVING_DATA, DEMOD_ERROR_WAIT } state; int bitCount; int posCount; int thisBit; int metric; int metricN; uint16_t shiftReg; uint8_t *output; int len; int sumI; int sumQ; } Demod; /* * Handles reception of a bit from the tag * * LED handling: * LED C -> ON once we have received the SOF and are expecting the rest. * LED C -> OFF once we have received EOF or are unsynced * * Returns: true if we received a EOF * false if we are still waiting for some more * */ static RAMFUNC int Handle14443SamplesDemod(int ci, int cq) { int v; // The soft decision on the bit uses an estimate of just the // quadrant of the reference angle, not the exact angle. #define MAKE_SOFT_DECISION() { \ if(Demod.sumI > 0) { \ v = ci; \ } else { \ v = -ci; \ } \ if(Demod.sumQ > 0) { \ v += cq; \ } else { \ v -= cq; \ } \ } switch(Demod.state) { case DEMOD_UNSYNCD: v = ci; if(v < 0) v = -v; if(cq > 0) { v += cq; } else { v -= cq; } if(v > 40) { Demod.posCount = 0; Demod.state = DEMOD_PHASE_REF_TRAINING; Demod.sumI = 0; Demod.sumQ = 0; } break; case DEMOD_PHASE_REF_TRAINING: if(Demod.posCount < 8) { Demod.sumI += ci; Demod.sumQ += cq; } else if(Demod.posCount > 100) { // error, waited too long Demod.state = DEMOD_UNSYNCD; } else { MAKE_SOFT_DECISION(); if(v < 0) { Demod.state = DEMOD_AWAITING_FALLING_EDGE_OF_SOF; Demod.posCount = 0; } } Demod.posCount++; break; case DEMOD_AWAITING_FALLING_EDGE_OF_SOF: MAKE_SOFT_DECISION(); if(v < 0) { Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF; Demod.posCount = 0; } else { if(Demod.posCount > 100) { Demod.state = DEMOD_UNSYNCD; } } Demod.posCount++; break; case DEMOD_GOT_FALLING_EDGE_OF_SOF: MAKE_SOFT_DECISION(); if(v > 0) { if(Demod.posCount < 12) { Demod.state = DEMOD_UNSYNCD; } else { LED_C_ON(); // Got SOF Demod.state = DEMOD_AWAITING_START_BIT; Demod.posCount = 0; Demod.len = 0; Demod.metricN = 0; Demod.metric = 0; } } else { if(Demod.posCount > 100) { Demod.state = DEMOD_UNSYNCD; } } Demod.posCount++; break; case DEMOD_AWAITING_START_BIT: MAKE_SOFT_DECISION(); if(v > 0) { if(Demod.posCount > 10) { Demod.state = DEMOD_UNSYNCD; } } else { Demod.bitCount = 0; Demod.posCount = 1; Demod.thisBit = v; Demod.shiftReg = 0; Demod.state = DEMOD_RECEIVING_DATA; } break; case DEMOD_RECEIVING_DATA: MAKE_SOFT_DECISION(); if(Demod.posCount == 0) { Demod.thisBit = v; Demod.posCount = 1; } else { Demod.thisBit += v; if(Demod.thisBit > 0) { Demod.metric += Demod.thisBit; } else { Demod.metric -= Demod.thisBit; } (Demod.metricN)++; Demod.shiftReg >>= 1; if(Demod.thisBit > 0) { Demod.shiftReg |= 0x200; } Demod.bitCount++; if(Demod.bitCount == 10) { uint16_t s = Demod.shiftReg; if((s & 0x200) && !(s & 0x001)) { uint8_t b = (s >> 1); Demod.output[Demod.len] = b; Demod.len++; Demod.state = DEMOD_AWAITING_START_BIT; } else if(s == 0x000) { // This is EOF LED_C_OFF(); return TRUE; Demod.state = DEMOD_UNSYNCD; } else { Demod.state = DEMOD_UNSYNCD; } } Demod.posCount = 0; } break; default: Demod.state = DEMOD_UNSYNCD; break; } if (Demod.state == DEMOD_UNSYNCD) LED_C_OFF(); // Not synchronized... return FALSE; } /* * Demodulate the samples we received from the tag * weTx: set to 'TRUE' if we behave like a reader * set to 'FALSE' if we behave like a snooper * quiet: set to 'TRUE' to disable debug output */ static void GetSamplesFor14443Demod(int weTx, int n, int quiet) { int max = 0; int gotFrame = FALSE; //# define DMA_BUFFER_SIZE 8 int8_t *dmaBuf; int lastRxCounter; int8_t *upTo; int ci, cq; int samples = 0; // Clear out the state of the "UART" that receives from the tag. memset(BigBuf, 0x44, 400); Demod.output = (uint8_t *)BigBuf; Demod.len = 0; Demod.state = DEMOD_UNSYNCD; // And the UART that receives from the reader Uart.output = (((uint8_t *)BigBuf) + 1024); Uart.byteCntMax = 100; Uart.state = STATE_UNSYNCD; // Setup for the DMA. dmaBuf = (int8_t *)(BigBuf + 32); upTo = dmaBuf; lastRxCounter = DEMOD_DMA_BUFFER_SIZE; FpgaSetupSscDma((uint8_t *)dmaBuf, DEMOD_DMA_BUFFER_SIZE); // Signal field is ON with the appropriate LED: if (weTx) LED_D_ON(); else LED_D_OFF(); // And put the FPGA in the appropriate mode FpgaWriteConfWord( FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ | (weTx ? 0 : FPGA_HF_READER_RX_XCORR_SNOOP)); for(;;) { int behindBy = lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR; if(behindBy > max) max = behindBy; while(((lastRxCounter-AT91C_BASE_PDC_SSC->PDC_RCR) & (DEMOD_DMA_BUFFER_SIZE-1)) > 2) { ci = upTo[0]; cq = upTo[1]; upTo += 2; if(upTo - dmaBuf > DEMOD_DMA_BUFFER_SIZE) { upTo -= DEMOD_DMA_BUFFER_SIZE; AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo; AT91C_BASE_PDC_SSC->PDC_RNCR = DEMOD_DMA_BUFFER_SIZE; } lastRxCounter -= 2; if(lastRxCounter <= 0) { lastRxCounter += DEMOD_DMA_BUFFER_SIZE; } samples += 2; Handle14443UartBit(1); Handle14443UartBit(1); if(Handle14443SamplesDemod(ci, cq)) { gotFrame = 1; } } if(samples > 2000) { break; } } AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS; if (!quiet) Dbprintf("%x %x %x", max, gotFrame, Demod.len); } //----------------------------------------------------------------------------- // Read the tag's response. We just receive a stream of slightly-processed // samples from the FPGA, which we will later do some signal processing on, // to get the bits. //----------------------------------------------------------------------------- /*static void GetSamplesFor14443(int weTx, int n) { uint8_t *dest = (uint8_t *)BigBuf; int c; FpgaWriteConfWord( FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ | (weTx ? 0 : FPGA_HF_READER_RX_XCORR_SNOOP)); c = 0; for(;;) { if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { AT91C_BASE_SSC->SSC_THR = 0x43; } if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { int8_t b; b = (int8_t)AT91C_BASE_SSC->SSC_RHR; dest[c++] = (uint8_t)b; if(c >= n) { break; } } } }*/ //----------------------------------------------------------------------------- // Transmit the command (to the tag) that was placed in ToSend[]. //----------------------------------------------------------------------------- static void TransmitFor14443(void) { int c; FpgaSetupSsc(); while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { AT91C_BASE_SSC->SSC_THR = 0xff; } // Signal field is ON with the appropriate Red LED LED_D_ON(); // Signal we are transmitting with the Green LED LED_B_ON(); FpgaWriteConfWord( FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD); for(c = 0; c < 10;) { if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { AT91C_BASE_SSC->SSC_THR = 0xff; c++; } if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR; (void)r; } WDT_HIT(); } c = 0; for(;;) { if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { AT91C_BASE_SSC->SSC_THR = ToSend[c]; c++; if(c >= ToSendMax) { break; } } if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR; (void)r; } WDT_HIT(); } LED_B_OFF(); // Finished sending } //----------------------------------------------------------------------------- // Code a layer 2 command (string of octets, including CRC) into ToSend[], // so that it is ready to transmit to the tag using TransmitFor14443(). //----------------------------------------------------------------------------- void CodeIso14443bAsReader(const uint8_t *cmd, int len) { int i, j; uint8_t b; ToSendReset(); // Establish initial reference level for(i = 0; i < 40; i++) { ToSendStuffBit(1); } // Send SOF for(i = 0; i < 10; i++) { ToSendStuffBit(0); } for(i = 0; i < len; i++) { // Stop bits/EGT ToSendStuffBit(1); ToSendStuffBit(1); // Start bit ToSendStuffBit(0); // Data bits b = cmd[i]; for(j = 0; j < 8; j++) { if(b & 1) { ToSendStuffBit(1); } else { ToSendStuffBit(0); } b >>= 1; } } // Send EOF ToSendStuffBit(1); for(i = 0; i < 10; i++) { ToSendStuffBit(0); } for(i = 0; i < 8; i++) { ToSendStuffBit(1); } // And then a little more, to make sure that the last character makes // it out before we switch to rx mode. for(i = 0; i < 24; i++) { ToSendStuffBit(1); } // Convert from last character reference to length ToSendMax++; } //----------------------------------------------------------------------------- // Read an ISO 14443 tag. We send it some set of commands, and record the // responses. // The command name is misleading, it actually decodes the reponse in HEX // into the output buffer (read the result using hexsamples, not hisamples) //----------------------------------------------------------------------------- void AcquireRawAdcSamplesIso14443(uint32_t parameter) { uint8_t cmd1[] = { 0x05, 0x00, 0x08, 0x39, 0x73 }; // Make sure that we start from off, since the tags are stateful; // confusing things will happen if we don't reset them between reads. FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); LED_D_OFF(); SpinDelay(200); SetAdcMuxFor(GPIO_MUXSEL_HIPKD); FpgaSetupSsc(); // Now give it time to spin up. // Signal field is on with the appropriate LED LED_D_ON(); FpgaWriteConfWord( FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ); SpinDelay(200); CodeIso14443bAsReader(cmd1, sizeof(cmd1)); TransmitFor14443(); // LED_A_ON(); GetSamplesFor14443Demod(TRUE, 2000, FALSE); // LED_A_OFF(); } //----------------------------------------------------------------------------- // Read a SRI512 ISO 14443 tag. // // SRI512 tags are just simple memory tags, here we're looking at making a dump // of the contents of the memory. No anticollision algorithm is done, we assume // we have a single tag in the field. // // I tried to be systematic and check every answer of the tag, every CRC, etc... //----------------------------------------------------------------------------- void ReadSRI512Iso14443(uint32_t parameter) { ReadSTMemoryIso14443(parameter,0x0F); } void ReadSRIX4KIso14443(uint32_t parameter) { ReadSTMemoryIso14443(parameter,0x7F); } void ReadSTMemoryIso14443(uint32_t parameter,uint32_t dwLast) { uint8_t i = 0x00; // Make sure that we start from off, since the tags are stateful; // confusing things will happen if we don't reset them between reads. LED_D_OFF(); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); SpinDelay(200); SetAdcMuxFor(GPIO_MUXSEL_HIPKD); FpgaSetupSsc(); // Now give it time to spin up. // Signal field is on with the appropriate LED LED_D_ON(); FpgaWriteConfWord( FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ); SpinDelay(200); // First command: wake up the tag using the INITIATE command uint8_t cmd1[] = { 0x06, 0x00, 0x97, 0x5b}; CodeIso14443bAsReader(cmd1, sizeof(cmd1)); TransmitFor14443(); // LED_A_ON(); GetSamplesFor14443Demod(TRUE, 2000,TRUE); // LED_A_OFF(); if (Demod.len == 0) { DbpString("No response from tag"); return; } else { Dbprintf("Randomly generated UID from tag (+ 2 byte CRC): %x %x %x", Demod.output[0], Demod.output[1],Demod.output[2]); } // There is a response, SELECT the uid DbpString("Now SELECT tag:"); cmd1[0] = 0x0E; // 0x0E is SELECT cmd1[1] = Demod.output[0]; ComputeCrc14443(CRC_14443_B, cmd1, 2, &cmd1[2], &cmd1[3]); CodeIso14443bAsReader(cmd1, sizeof(cmd1)); TransmitFor14443(); // LED_A_ON(); GetSamplesFor14443Demod(TRUE, 2000,TRUE); // LED_A_OFF(); if (Demod.len != 3) { Dbprintf("Expected 3 bytes from tag, got %d", Demod.len); return; } // Check the CRC of the answer: ComputeCrc14443(CRC_14443_B, Demod.output, 1 , &cmd1[2], &cmd1[3]); if(cmd1[2] != Demod.output[1] || cmd1[3] != Demod.output[2]) { DbpString("CRC Error reading select response."); return; } // Check response from the tag: should be the same UID as the command we just sent: if (cmd1[1] != Demod.output[0]) { Dbprintf("Bad response to SELECT from Tag, aborting: %x %x", cmd1[1], Demod.output[0]); return; } // Tag is now selected, // First get the tag's UID: cmd1[0] = 0x0B; ComputeCrc14443(CRC_14443_B, cmd1, 1 , &cmd1[1], &cmd1[2]); CodeIso14443bAsReader(cmd1, 3); // Only first three bytes for this one TransmitFor14443(); // LED_A_ON(); GetSamplesFor14443Demod(TRUE, 2000,TRUE); // LED_A_OFF(); if (Demod.len != 10) { Dbprintf("Expected 10 bytes from tag, got %d", Demod.len); return; } // The check the CRC of the answer (use cmd1 as temporary variable): ComputeCrc14443(CRC_14443_B, Demod.output, 8, &cmd1[2], &cmd1[3]); if(cmd1[2] != Demod.output[8] || cmd1[3] != Demod.output[9]) { Dbprintf("CRC Error reading block! - Below: expected, got %x %x", (cmd1[2]<<8)+cmd1[3], (Demod.output[8]<<8)+Demod.output[9]); // Do not return;, let's go on... (we should retry, maybe ?) } Dbprintf("Tag UID (64 bits): %08x %08x", (Demod.output[7]<<24) + (Demod.output[6]<<16) + (Demod.output[5]<<8) + Demod.output[4], (Demod.output[3]<<24) + (Demod.output[2]<<16) + (Demod.output[1]<<8) + Demod.output[0]); // Now loop to read all 16 blocks, address from 0 to 15 DbpString("Tag memory dump, block 0 to 15"); cmd1[0] = 0x08; i = 0x00; dwLast++; for (;;) { if (i == dwLast) { DbpString("System area block (0xff):"); i = 0xff; } cmd1[1] = i; ComputeCrc14443(CRC_14443_B, cmd1, 2, &cmd1[2], &cmd1[3]); CodeIso14443bAsReader(cmd1, sizeof(cmd1)); TransmitFor14443(); // LED_A_ON(); GetSamplesFor14443Demod(TRUE, 2000,TRUE); // LED_A_OFF(); if (Demod.len != 6) { // Check if we got an answer from the tag DbpString("Expected 6 bytes from tag, got less..."); return; } // The check the CRC of the answer (use cmd1 as temporary variable): ComputeCrc14443(CRC_14443_B, Demod.output, 4, &cmd1[2], &cmd1[3]); if(cmd1[2] != Demod.output[4] || cmd1[3] != Demod.output[5]) { Dbprintf("CRC Error reading block! - Below: expected, got %x %x", (cmd1[2]<<8)+cmd1[3], (Demod.output[4]<<8)+Demod.output[5]); // Do not return;, let's go on... (we should retry, maybe ?) } // Now print out the memory location: Dbprintf("Address=%x, Contents=%x, CRC=%x", i, (Demod.output[3]<<24) + (Demod.output[2]<<16) + (Demod.output[1]<<8) + Demod.output[0], (Demod.output[4]<<8)+Demod.output[5]); if (i == 0xff) { break; } i++; } } //============================================================================= // Finally, the `sniffer' combines elements from both the reader and // simulated tag, to show both sides of the conversation. //============================================================================= //----------------------------------------------------------------------------- // Record the sequence of commands sent by the reader to the tag, with // triggering so that we start recording at the point that the tag is moved // near the reader. //----------------------------------------------------------------------------- /* * Memory usage for this function, (within BigBuf) * 0-4095 : Demodulated samples receive (4096 bytes) - DEMOD_TRACE_SIZE * 4096-6143 : Last Received command, 2048 bytes (reader->tag) - READER_TAG_BUFFER_SIZE * 6144-8191 : Last Received command, 2048 bytes(tag->reader) - TAG_READER_BUFFER_SIZE * 8192-9215 : DMA Buffer, 1024 bytes (samples) - DEMOD_DMA_BUFFER_SIZE */ void RAMFUNC SnoopIso14443(void) { // We won't start recording the frames that we acquire until we trigger; // a good trigger condition to get started is probably when we see a // response from the tag. int triggered = TRUE; // The command (reader -> tag) that we're working on receiving. uint8_t *receivedCmd = (uint8_t *)(BigBuf) + DEMOD_TRACE_SIZE; // The response (tag -> reader) that we're working on receiving. uint8_t *receivedResponse = (uint8_t *)(BigBuf) + DEMOD_TRACE_SIZE + READER_TAG_BUFFER_SIZE; // As we receive stuff, we copy it from receivedCmd or receivedResponse // into trace, along with its length and other annotations. uint8_t *trace = (uint8_t *)BigBuf; int traceLen = 0; // The DMA buffer, used to stream samples from the FPGA. int8_t *dmaBuf = (int8_t *)(BigBuf) + DEMOD_TRACE_SIZE + READER_TAG_BUFFER_SIZE + TAG_READER_BUFFER_SIZE; int lastRxCounter; int8_t *upTo; int ci, cq; int maxBehindBy = 0; // Count of samples received so far, so that we can include timing // information in the trace buffer. int samples = 0; // Initialize the trace buffer memset(trace, 0x44, DEMOD_TRACE_SIZE); // Set up the demodulator for tag -> reader responses. Demod.output = receivedResponse; Demod.len = 0; Demod.state = DEMOD_UNSYNCD; // And the reader -> tag commands memset(&Uart, 0, sizeof(Uart)); Uart.output = receivedCmd; Uart.byteCntMax = 100; Uart.state = STATE_UNSYNCD; // Print some debug information about the buffer sizes Dbprintf("Snooping buffers initialized:"); Dbprintf(" Trace: %i bytes", DEMOD_TRACE_SIZE); Dbprintf(" Reader -> tag: %i bytes", READER_TAG_BUFFER_SIZE); Dbprintf(" tag -> Reader: %i bytes", TAG_READER_BUFFER_SIZE); Dbprintf(" DMA: %i bytes", DEMOD_DMA_BUFFER_SIZE); // And put the FPGA in the appropriate mode // Signal field is off with the appropriate LED LED_D_OFF(); FpgaWriteConfWord( FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ | FPGA_HF_READER_RX_XCORR_SNOOP); SetAdcMuxFor(GPIO_MUXSEL_HIPKD); // Setup for the DMA. FpgaSetupSsc(); upTo = dmaBuf; lastRxCounter = DEMOD_DMA_BUFFER_SIZE; FpgaSetupSscDma((uint8_t *)dmaBuf, DEMOD_DMA_BUFFER_SIZE); LED_A_ON(); // And now we loop, receiving samples. for(;;) { int behindBy = (lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) & (DEMOD_DMA_BUFFER_SIZE-1); if(behindBy > maxBehindBy) { maxBehindBy = behindBy; if(behindBy > (DEMOD_DMA_BUFFER_SIZE-2)) { // TODO: understand whether we can increase/decrease as we want or not? Dbprintf("blew circular buffer! behindBy=0x%x", behindBy); goto done; } } if(behindBy < 2) continue; ci = upTo[0]; cq = upTo[1]; upTo += 2; lastRxCounter -= 2; if(upTo - dmaBuf > DEMOD_DMA_BUFFER_SIZE) { upTo -= DEMOD_DMA_BUFFER_SIZE; lastRxCounter += DEMOD_DMA_BUFFER_SIZE; AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo; AT91C_BASE_PDC_SSC->PDC_RNCR = DEMOD_DMA_BUFFER_SIZE; } samples += 2; #define HANDLE_BIT_IF_BODY \ if(triggered) { \ trace[traceLen++] = ((samples >> 0) & 0xff); \ trace[traceLen++] = ((samples >> 8) & 0xff); \ trace[traceLen++] = ((samples >> 16) & 0xff); \ trace[traceLen++] = ((samples >> 24) & 0xff); \ trace[traceLen++] = 0; \ trace[traceLen++] = 0; \ trace[traceLen++] = 0; \ trace[traceLen++] = 0; \ trace[traceLen++] = Uart.byteCnt; \ memcpy(trace+traceLen, receivedCmd, Uart.byteCnt); \ traceLen += Uart.byteCnt; \ if(traceLen > 1000) break; \ } \ /* And ready to receive another command. */ \ memset(&Uart, 0, sizeof(Uart)); \ Uart.output = receivedCmd; \ Uart.byteCntMax = 100; \ Uart.state = STATE_UNSYNCD; \ /* And also reset the demod code, which might have been */ \ /* false-triggered by the commands from the reader. */ \ memset(&Demod, 0, sizeof(Demod)); \ Demod.output = receivedResponse; \ Demod.state = DEMOD_UNSYNCD; \ if(Handle14443UartBit(ci & 1)) { HANDLE_BIT_IF_BODY } if(Handle14443UartBit(cq & 1)) { HANDLE_BIT_IF_BODY } if(Handle14443SamplesDemod(ci, cq)) { // timestamp, as a count of samples trace[traceLen++] = ((samples >> 0) & 0xff); trace[traceLen++] = ((samples >> 8) & 0xff); trace[traceLen++] = ((samples >> 16) & 0xff); trace[traceLen++] = 0x80 | ((samples >> 24) & 0xff); // correlation metric (~signal strength estimate) if(Demod.metricN != 0) { Demod.metric /= Demod.metricN; } trace[traceLen++] = ((Demod.metric >> 0) & 0xff); trace[traceLen++] = ((Demod.metric >> 8) & 0xff); trace[traceLen++] = ((Demod.metric >> 16) & 0xff); trace[traceLen++] = ((Demod.metric >> 24) & 0xff); // length trace[traceLen++] = Demod.len; memcpy(trace+traceLen, receivedResponse, Demod.len); traceLen += Demod.len; if(traceLen > DEMOD_TRACE_SIZE) { DbpString("Reached trace limit"); goto done; } triggered = TRUE; LED_A_OFF(); LED_B_ON(); // And ready to receive another response. memset(&Demod, 0, sizeof(Demod)); Demod.output = receivedResponse; Demod.state = DEMOD_UNSYNCD; } WDT_HIT(); if(BUTTON_PRESS()) { DbpString("cancelled"); goto done; } } done: LED_A_OFF(); LED_B_OFF(); LED_C_OFF(); AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS; DbpString("Snoop statistics:"); Dbprintf(" Max behind by: %i", maxBehindBy); Dbprintf(" Uart State: %x", Uart.state); Dbprintf(" Uart ByteCnt: %i", Uart.byteCnt); Dbprintf(" Uart ByteCntMax: %i", Uart.byteCntMax); Dbprintf(" Trace length: %i", traceLen); } ================================================ FILE: TamagotchiFriends/proxmark/armsrc/iso14443a.c ================================================ //----------------------------------------------------------------------------- // Merlok - June 2011, 2012 // Gerhard de Koning Gans - May 2008 // Hagen Fritsch - June 2010 // // This code is licensed to you under the terms of the GNU GPL, version 2 or, // at your option, any later version. See the LICENSE.txt file for the text of // the license. //----------------------------------------------------------------------------- // Routines to support ISO 14443 type A. //----------------------------------------------------------------------------- #include "proxmark3.h" #include "apps.h" #include "util.h" #include "string.h" #include "cmd.h" #include "iso14443crc.h" #include "iso14443a.h" #include "crapto1.h" #include "mifareutil.h" static uint32_t iso14a_timeout; uint8_t *trace = (uint8_t *) BigBuf+TRACE_OFFSET; int traceLen = 0; int rsamples = 0; int tracing = TRUE; uint8_t trigger = 0; // the block number for the ISO14443-4 PCB static uint8_t iso14_pcb_blocknum = 0; // CARD TO READER - manchester // Sequence D: 11110000 modulation with subcarrier during first half // Sequence E: 00001111 modulation with subcarrier during second half // Sequence F: 00000000 no modulation with subcarrier // READER TO CARD - miller // Sequence X: 00001100 drop after half a period // Sequence Y: 00000000 no drop // Sequence Z: 11000000 drop at start #define SEC_D 0xf0 #define SEC_E 0x0f #define SEC_F 0x00 #define SEC_X 0x0c #define SEC_Y 0x00 #define SEC_Z 0xc0 const uint8_t OddByteParity[256] = { 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1 }; void iso14a_set_trigger(bool enable) { trigger = enable; } void iso14a_clear_trace() { memset(trace, 0x44, TRACE_SIZE); traceLen = 0; } void iso14a_set_tracing(bool enable) { tracing = enable; } void iso14a_set_timeout(uint32_t timeout) { iso14a_timeout = timeout; } //----------------------------------------------------------------------------- // Generate the parity value for a byte sequence // //----------------------------------------------------------------------------- byte_t oddparity (const byte_t bt) { return OddByteParity[bt]; } uint32_t GetParity(const uint8_t * pbtCmd, int iLen) { int i; uint32_t dwPar = 0; // Generate the encrypted data for (i = 0; i < iLen; i++) { // Save the encrypted parity bit dwPar |= ((OddByteParity[pbtCmd[i]]) << i); } return dwPar; } void AppendCrc14443a(uint8_t* data, int len) { ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1); } // The function LogTrace() is also used by the iClass implementation in iClass.c int RAMFUNC LogTrace(const uint8_t * btBytes, int iLen, int iSamples, uint32_t dwParity, int bReader) { // Return when trace is full if (traceLen >= TRACE_SIZE) return FALSE; // Trace the random, i'm curious rsamples += iSamples; trace[traceLen++] = ((rsamples >> 0) & 0xff); trace[traceLen++] = ((rsamples >> 8) & 0xff); trace[traceLen++] = ((rsamples >> 16) & 0xff); trace[traceLen++] = ((rsamples >> 24) & 0xff); if (!bReader) { trace[traceLen - 1] |= 0x80; } trace[traceLen++] = ((dwParity >> 0) & 0xff); trace[traceLen++] = ((dwParity >> 8) & 0xff); trace[traceLen++] = ((dwParity >> 16) & 0xff); trace[traceLen++] = ((dwParity >> 24) & 0xff); trace[traceLen++] = iLen; memcpy(trace + traceLen, btBytes, iLen); traceLen += iLen; return TRUE; } //----------------------------------------------------------------------------- // The software UART that receives commands from the reader, and its state // variables. //----------------------------------------------------------------------------- static tUart Uart; static RAMFUNC int MillerDecoding(int bit) { //int error = 0; int bitright; if(!Uart.bitBuffer) { Uart.bitBuffer = bit ^ 0xFF0; return FALSE; } else { Uart.bitBuffer <<= 4; Uart.bitBuffer ^= bit; } int EOC = FALSE; if(Uart.state != STATE_UNSYNCD) { Uart.posCnt++; if((Uart.bitBuffer & Uart.syncBit) ^ Uart.syncBit) { bit = 0x00; } else { bit = 0x01; } if(((Uart.bitBuffer << 1) & Uart.syncBit) ^ Uart.syncBit) { bitright = 0x00; } else { bitright = 0x01; } if(bit != bitright) { bit = bitright; } if(Uart.posCnt == 1) { // measurement first half bitperiod if(!bit) { Uart.drop = DROP_FIRST_HALF; } } else { // measurement second half bitperiod if(!bit & (Uart.drop == DROP_NONE)) { Uart.drop = DROP_SECOND_HALF; } else if(!bit) { // measured a drop in first and second half // which should not be possible Uart.state = STATE_ERROR_WAIT; //error = 0x01; } Uart.posCnt = 0; switch(Uart.state) { case STATE_START_OF_COMMUNICATION: Uart.shiftReg = 0; if(Uart.drop == DROP_SECOND_HALF) { // error, should not happen in SOC Uart.state = STATE_ERROR_WAIT; //error = 0x02; } else { // correct SOC Uart.state = STATE_MILLER_Z; } break; case STATE_MILLER_Z: Uart.bitCnt++; Uart.shiftReg >>= 1; if(Uart.drop == DROP_NONE) { // logic '0' followed by sequence Y // end of communication Uart.state = STATE_UNSYNCD; EOC = TRUE; } // if(Uart.drop == DROP_FIRST_HALF) { // Uart.state = STATE_MILLER_Z; stay the same // we see a logic '0' } if(Uart.drop == DROP_SECOND_HALF) { // we see a logic '1' Uart.shiftReg |= 0x100; Uart.state = STATE_MILLER_X; } break; case STATE_MILLER_X: Uart.shiftReg >>= 1; if(Uart.drop == DROP_NONE) { // sequence Y, we see a '0' Uart.state = STATE_MILLER_Y; Uart.bitCnt++; } if(Uart.drop == DROP_FIRST_HALF) { // Would be STATE_MILLER_Z // but Z does not follow X, so error Uart.state = STATE_ERROR_WAIT; //error = 0x03; } if(Uart.drop == DROP_SECOND_HALF) { // We see a '1' and stay in state X Uart.shiftReg |= 0x100; Uart.bitCnt++; } break; case STATE_MILLER_Y: Uart.bitCnt++; Uart.shiftReg >>= 1; if(Uart.drop == DROP_NONE) { // logic '0' followed by sequence Y // end of communication Uart.state = STATE_UNSYNCD; EOC = TRUE; } if(Uart.drop == DROP_FIRST_HALF) { // we see a '0' Uart.state = STATE_MILLER_Z; } if(Uart.drop == DROP_SECOND_HALF) { // We see a '1' and go to state X Uart.shiftReg |= 0x100; Uart.state = STATE_MILLER_X; } break; case STATE_ERROR_WAIT: // That went wrong. Now wait for at least two bit periods // and try to sync again if(Uart.drop == DROP_NONE) { Uart.highCnt = 6; Uart.state = STATE_UNSYNCD; } break; default: Uart.state = STATE_UNSYNCD; Uart.highCnt = 0; break; } Uart.drop = DROP_NONE; // should have received at least one whole byte... if((Uart.bitCnt == 2) && EOC && (Uart.byteCnt > 0)) { return TRUE; } if(Uart.bitCnt == 9) { Uart.output[Uart.byteCnt] = (Uart.shiftReg & 0xff); Uart.byteCnt++; Uart.parityBits <<= 1; Uart.parityBits ^= ((Uart.shiftReg >> 8) & 0x01); if(EOC) { // when End of Communication received and // all data bits processed.. return TRUE; } Uart.bitCnt = 0; } /*if(error) { Uart.output[Uart.byteCnt] = 0xAA; Uart.byteCnt++; Uart.output[Uart.byteCnt] = error & 0xFF; Uart.byteCnt++; Uart.output[Uart.byteCnt] = 0xAA; Uart.byteCnt++; Uart.output[Uart.byteCnt] = (Uart.bitBuffer >> 8) & 0xFF; Uart.byteCnt++; Uart.output[Uart.byteCnt] = Uart.bitBuffer & 0xFF; Uart.byteCnt++; Uart.output[Uart.byteCnt] = (Uart.syncBit >> 3) & 0xFF; Uart.byteCnt++; Uart.output[Uart.byteCnt] = 0xAA; Uart.byteCnt++; return TRUE; }*/ } } else { bit = Uart.bitBuffer & 0xf0; bit >>= 4; bit ^= 0x0F; if(bit) { // should have been high or at least (4 * 128) / fc // according to ISO this should be at least (9 * 128 + 20) / fc if(Uart.highCnt == 8) { // we went low, so this could be start of communication // it turns out to be safer to choose a less significant // syncbit... so we check whether the neighbour also represents the drop Uart.posCnt = 1; // apparently we are busy with our first half bit period Uart.syncBit = bit & 8; Uart.samples = 3; if(!Uart.syncBit) { Uart.syncBit = bit & 4; Uart.samples = 2; } else if(bit & 4) { Uart.syncBit = bit & 4; Uart.samples = 2; bit <<= 2; } if(!Uart.syncBit) { Uart.syncBit = bit & 2; Uart.samples = 1; } else if(bit & 2) { Uart.syncBit = bit & 2; Uart.samples = 1; bit <<= 1; } if(!Uart.syncBit) { Uart.syncBit = bit & 1; Uart.samples = 0; if(Uart.syncBit && (Uart.bitBuffer & 8)) { Uart.syncBit = 8; // the first half bit period is expected in next sample Uart.posCnt = 0; Uart.samples = 3; } } else if(bit & 1) { Uart.syncBit = bit & 1; Uart.samples = 0; } Uart.syncBit <<= 4; Uart.state = STATE_START_OF_COMMUNICATION; Uart.drop = DROP_FIRST_HALF; Uart.bitCnt = 0; Uart.byteCnt = 0; Uart.parityBits = 0; //error = 0; } else { Uart.highCnt = 0; } } else { if(Uart.highCnt < 8) { Uart.highCnt++; } } } return FALSE; } //============================================================================= // ISO 14443 Type A - Manchester //============================================================================= static tDemod Demod; static RAMFUNC int ManchesterDecoding(int v) { int bit; int modulation; //int error = 0; if(!Demod.buff) { Demod.buff = 1; Demod.buffer = v; return FALSE; } else { bit = Demod.buffer; Demod.buffer = v; } if(Demod.state==DEMOD_UNSYNCD) { Demod.output[Demod.len] = 0xfa; Demod.syncBit = 0; //Demod.samples = 0; Demod.posCount = 1; // This is the first half bit period, so after syncing handle the second part if(bit & 0x08) { Demod.syncBit = 0x08; } if(bit & 0x04) { if(Demod.syncBit) { bit <<= 4; } Demod.syncBit = 0x04; } if(bit & 0x02) { if(Demod.syncBit) { bit <<= 2; } Demod.syncBit = 0x02; } if(bit & 0x01 && Demod.syncBit) { Demod.syncBit = 0x01; } if(Demod.syncBit) { Demod.len = 0; Demod.state = DEMOD_START_OF_COMMUNICATION; Demod.sub = SUB_FIRST_HALF; Demod.bitCount = 0; Demod.shiftReg = 0; Demod.parityBits = 0; Demod.samples = 0; if(Demod.posCount) { if(trigger) LED_A_OFF(); switch(Demod.syncBit) { case 0x08: Demod.samples = 3; break; case 0x04: Demod.samples = 2; break; case 0x02: Demod.samples = 1; break; case 0x01: Demod.samples = 0; break; } } //error = 0; } } else { //modulation = bit & Demod.syncBit; modulation = ((bit << 1) ^ ((Demod.buffer & 0x08) >> 3)) & Demod.syncBit; Demod.samples += 4; if(Demod.posCount==0) { Demod.posCount = 1; if(modulation) { Demod.sub = SUB_FIRST_HALF; } else { Demod.sub = SUB_NONE; } } else { Demod.posCount = 0; if(modulation && (Demod.sub == SUB_FIRST_HALF)) { if(Demod.state!=DEMOD_ERROR_WAIT) { Demod.state = DEMOD_ERROR_WAIT; Demod.output[Demod.len] = 0xaa; //error = 0x01; } } else if(modulation) { Demod.sub = SUB_SECOND_HALF; } switch(Demod.state) { case DEMOD_START_OF_COMMUNICATION: if(Demod.sub == SUB_FIRST_HALF) { Demod.state = DEMOD_MANCHESTER_D; } else { Demod.output[Demod.len] = 0xab; Demod.state = DEMOD_ERROR_WAIT; //error = 0x02; } break; case DEMOD_MANCHESTER_D: case DEMOD_MANCHESTER_E: if(Demod.sub == SUB_FIRST_HALF) { Demod.bitCount++; Demod.shiftReg = (Demod.shiftReg >> 1) ^ 0x100; Demod.state = DEMOD_MANCHESTER_D; } else if(Demod.sub == SUB_SECOND_HALF) { Demod.bitCount++; Demod.shiftReg >>= 1; Demod.state = DEMOD_MANCHESTER_E; } else { Demod.state = DEMOD_MANCHESTER_F; } break; case DEMOD_MANCHESTER_F: // Tag response does not need to be a complete byte! if(Demod.len > 0 || Demod.bitCount > 0) { if(Demod.bitCount > 0) { Demod.shiftReg >>= (9 - Demod.bitCount); Demod.output[Demod.len] = Demod.shiftReg & 0xff; Demod.len++; // No parity bit, so just shift a 0 Demod.parityBits <<= 1; } Demod.state = DEMOD_UNSYNCD; return TRUE; } else { Demod.output[Demod.len] = 0xad; Demod.state = DEMOD_ERROR_WAIT; //error = 0x03; } break; case DEMOD_ERROR_WAIT: Demod.state = DEMOD_UNSYNCD; break; default: Demod.output[Demod.len] = 0xdd; Demod.state = DEMOD_UNSYNCD; break; } if(Demod.bitCount>=9) { Demod.output[Demod.len] = Demod.shiftReg & 0xff; Demod.len++; Demod.parityBits <<= 1; Demod.parityBits ^= ((Demod.shiftReg >> 8) & 0x01); Demod.bitCount = 0; Demod.shiftReg = 0; } /*if(error) { Demod.output[Demod.len] = 0xBB; Demod.len++; Demod.output[Demod.len] = error & 0xFF; Demod.len++; Demod.output[Demod.len] = 0xBB; Demod.len++; Demod.output[Demod.len] = bit & 0xFF; Demod.len++; Demod.output[Demod.len] = Demod.buffer & 0xFF; Demod.len++; Demod.output[Demod.len] = Demod.syncBit & 0xFF; Demod.len++; Demod.output[Demod.len] = 0xBB; Demod.len++; return TRUE; }*/ } } // end (state != UNSYNCED) return FALSE; } //============================================================================= // Finally, a `sniffer' for ISO 14443 Type A // Both sides of communication! //============================================================================= //----------------------------------------------------------------------------- // Record the sequence of commands sent by the reader to the tag, with // triggering so that we start recording at the point that the tag is moved // near the reader. //----------------------------------------------------------------------------- void RAMFUNC SnoopIso14443a(uint8_t param) { // param: // bit 0 - trigger from first card answer // bit 1 - trigger from first reader 7-bit request LEDsoff(); // init trace buffer iso14a_clear_trace(); // We won't start recording the frames that we acquire until we trigger; // a good trigger condition to get started is probably when we see a // response from the tag. // triggered == FALSE -- to wait first for card int triggered = !(param & 0x03); // The command (reader -> tag) that we're receiving. // The length of a received command will in most cases be no more than 18 bytes. // So 32 should be enough! uint8_t *receivedCmd = (((uint8_t *)BigBuf) + RECV_CMD_OFFSET); // The response (tag -> reader) that we're receiving. uint8_t *receivedResponse = (((uint8_t *)BigBuf) + RECV_RES_OFFSET); // As we receive stuff, we copy it from receivedCmd or receivedResponse // into trace, along with its length and other annotations. //uint8_t *trace = (uint8_t *)BigBuf; // The DMA buffer, used to stream samples from the FPGA int8_t *dmaBuf = ((int8_t *)BigBuf) + DMA_BUFFER_OFFSET; int8_t *data = dmaBuf; int maxDataLen = 0; int dataLen = 0; // Set up the demodulator for tag -> reader responses. Demod.output = receivedResponse; Demod.len = 0; Demod.state = DEMOD_UNSYNCD; // Set up the demodulator for the reader -> tag commands memset(&Uart, 0, sizeof(Uart)); Uart.output = receivedCmd; Uart.byteCntMax = 32; // was 100 (greg)////////////////// Uart.state = STATE_UNSYNCD; // Setup for the DMA. FpgaSetupSsc(); FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // And put the FPGA in the appropriate mode // Signal field is off with the appropriate LED LED_D_OFF(); FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_SNIFFER); SetAdcMuxFor(GPIO_MUXSEL_HIPKD); // Count of samples received so far, so that we can include timing // information in the trace buffer. rsamples = 0; // And now we loop, receiving samples. while(true) { if(BUTTON_PRESS()) { DbpString("cancelled by button"); goto done; } LED_A_ON(); WDT_HIT(); int register readBufDataP = data - dmaBuf; int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; if (readBufDataP <= dmaBufDataP){ dataLen = dmaBufDataP - readBufDataP; } else { dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP + 1; } // test for length of buffer if(dataLen > maxDataLen) { maxDataLen = dataLen; if(dataLen > 400) { Dbprintf("blew circular buffer! dataLen=0x%x", dataLen); goto done; } } if(dataLen < 1) continue; // primary buffer was stopped( <-- we lost data! if (!AT91C_BASE_PDC_SSC->PDC_RCR) { AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf; AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE; } // secondary buffer sets as primary, secondary buffer was stopped if (!AT91C_BASE_PDC_SSC->PDC_RNCR) { AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf; AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE; } LED_A_OFF(); rsamples += 4; if(MillerDecoding((data[0] & 0xF0) >> 4)) { LED_C_ON(); // check - if there is a short 7bit request from reader if ((!triggered) && (param & 0x02) && (Uart.byteCnt == 1) && (Uart.bitCnt = 9)) triggered = TRUE; if(triggered) { if (!LogTrace(receivedCmd, Uart.byteCnt, 0 - Uart.samples, Uart.parityBits, TRUE)) break; } /* And ready to receive another command. */ Uart.state = STATE_UNSYNCD; /* And also reset the demod code, which might have been */ /* false-triggered by the commands from the reader. */ Demod.state = DEMOD_UNSYNCD; LED_B_OFF(); } if(ManchesterDecoding(data[0] & 0x0F)) { LED_B_ON(); if (!LogTrace(receivedResponse, Demod.len, 0 - Demod.samples, Demod.parityBits, FALSE)) break; if ((!triggered) && (param & 0x01)) triggered = TRUE; // And ready to receive another response. memset(&Demod, 0, sizeof(Demod)); Demod.output = receivedResponse; Demod.state = DEMOD_UNSYNCD; LED_C_OFF(); } data++; if(data > dmaBuf + DMA_BUFFER_SIZE) { data = dmaBuf; } } // main cycle DbpString("COMMAND FINISHED"); done: AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS; Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.byteCnt=%x", maxDataLen, Uart.state, Uart.byteCnt); Dbprintf("Uart.byteCntMax=%x, traceLen=%x, Uart.output[0]=%08x", Uart.byteCntMax, traceLen, (int)Uart.output[0]); LEDsoff(); } //----------------------------------------------------------------------------- // Prepare tag messages //----------------------------------------------------------------------------- static void CodeIso14443aAsTagPar(const uint8_t *cmd, int len, uint32_t dwParity) { int i; ToSendReset(); // Correction bit, might be removed when not needed ToSendStuffBit(0); ToSendStuffBit(0); ToSendStuffBit(0); ToSendStuffBit(0); ToSendStuffBit(1); // 1 ToSendStuffBit(0); ToSendStuffBit(0); ToSendStuffBit(0); // Send startbit ToSend[++ToSendMax] = SEC_D; for(i = 0; i < len; i++) { int j; uint8_t b = cmd[i]; // Data bits for(j = 0; j < 8; j++) { if(b & 1) { ToSend[++ToSendMax] = SEC_D; } else { ToSend[++ToSendMax] = SEC_E; } b >>= 1; } // Get the parity bit if ((dwParity >> i) & 0x01) { ToSend[++ToSendMax] = SEC_D; } else { ToSend[++ToSendMax] = SEC_E; } } // Send stopbit ToSend[++ToSendMax] = SEC_F; // Convert from last byte pos to length ToSendMax++; } static void CodeIso14443aAsTag(const uint8_t *cmd, int len){ CodeIso14443aAsTagPar(cmd, len, GetParity(cmd, len)); } //----------------------------------------------------------------------------- // This is to send a NACK kind of answer, its only 3 bits, I know it should be 4 //----------------------------------------------------------------------------- static void CodeStrangeAnswerAsTag() { int i; ToSendReset(); // Correction bit, might be removed when not needed ToSendStuffBit(0); ToSendStuffBit(0); ToSendStuffBit(0); ToSendStuffBit(0); ToSendStuffBit(1); // 1 ToSendStuffBit(0); ToSendStuffBit(0); ToSendStuffBit(0); // Send startbit ToSend[++ToSendMax] = SEC_D; // 0 ToSend[++ToSendMax] = SEC_E; // 0 ToSend[++ToSendMax] = SEC_E; // 1 ToSend[++ToSendMax] = SEC_D; // Send stopbit ToSend[++ToSendMax] = SEC_F; // Flush the buffer in FPGA!! for(i = 0; i < 5; i++) { ToSend[++ToSendMax] = SEC_F; } // Convert from last byte pos to length ToSendMax++; } static void Code4bitAnswerAsTag(uint8_t cmd) { int i; ToSendReset(); // Correction bit, might be removed when not needed ToSendStuffBit(0); ToSendStuffBit(0); ToSendStuffBit(0); ToSendStuffBit(0); ToSendStuffBit(1); // 1 ToSendStuffBit(0); ToSendStuffBit(0); ToSendStuffBit(0); // Send startbit ToSend[++ToSendMax] = SEC_D; uint8_t b = cmd; for(i = 0; i < 4; i++) { if(b & 1) { ToSend[++ToSendMax] = SEC_D; } else { ToSend[++ToSendMax] = SEC_E; } b >>= 1; } // Send stopbit ToSend[++ToSendMax] = SEC_F; // Flush the buffer in FPGA!! for(i = 0; i < 5; i++) { ToSend[++ToSendMax] = SEC_F; } // Convert from last byte pos to length ToSendMax++; } //----------------------------------------------------------------------------- // Wait for commands from reader // Stop when button is pressed // Or return TRUE when command is captured //----------------------------------------------------------------------------- static int GetIso14443aCommandFromReader(uint8_t *received, int *len, int maxLen) { // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen // only, since we are receiving, not transmitting). // Signal field is off with the appropriate LED LED_D_OFF(); FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN); // Now run a `software UART' on the stream of incoming samples. Uart.output = received; Uart.byteCntMax = maxLen; Uart.state = STATE_UNSYNCD; for(;;) { WDT_HIT(); if(BUTTON_PRESS()) return FALSE; if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { AT91C_BASE_SSC->SSC_THR = 0x00; } if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR; if(MillerDecoding((b & 0xf0) >> 4)) { *len = Uart.byteCnt; return TRUE; } if(MillerDecoding(b & 0x0f)) { *len = Uart.byteCnt; return TRUE; } } } } static int EmSendCmd14443aRaw(uint8_t *resp, int respLen, int correctionNeeded); int EmSend4bitEx(uint8_t resp, int correctionNeeded); int EmSend4bit(uint8_t resp); int EmSendCmdExPar(uint8_t *resp, int respLen, int correctionNeeded, uint32_t par); int EmSendCmdExPar(uint8_t *resp, int respLen, int correctionNeeded, uint32_t par); int EmSendCmdEx(uint8_t *resp, int respLen, int correctionNeeded); int EmSendCmd(uint8_t *resp, int respLen); int EmSendCmdPar(uint8_t *resp, int respLen, uint32_t par); //----------------------------------------------------------------------------- // Main loop of simulated tag: receive commands from reader, decide what // response to send, and send it. //----------------------------------------------------------------------------- void SimulateIso14443aTag(int tagType, int uid_1st, int uid_2nd, byte_t* data) { // Enable and clear the trace tracing = TRUE; iso14a_clear_trace(); // This function contains the tag emulation uint8_t sak; // The first response contains the ATQA (note: bytes are transmitted in reverse order). uint8_t response1[2]; switch (tagType) { case 1: { // MIFARE Classic // Says: I am Mifare 1k - original line response1[0] = 0x04; response1[1] = 0x00; sak = 0x08; } break; case 2: { // MIFARE Ultralight // Says: I am a stupid memory tag, no crypto response1[0] = 0x04; response1[1] = 0x00; sak = 0x00; } break; case 3: { // MIFARE DESFire // Says: I am a DESFire tag, ph33r me response1[0] = 0x04; response1[1] = 0x03; sak = 0x20; } break; case 4: { // ISO/IEC 14443-4 // Says: I am a javacard (JCOP) response1[0] = 0x04; response1[1] = 0x00; sak = 0x28; } break; default: { Dbprintf("Error: unkown tagtype (%d)",tagType); return; } break; } // The second response contains the (mandatory) first 24 bits of the UID uint8_t response2[5]; // Check if the uid uses the (optional) part uint8_t response2a[5]; if (uid_2nd) { response2[0] = 0x88; num_to_bytes(uid_1st,3,response2+1); num_to_bytes(uid_2nd,4,response2a); response2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3]; // Configure the ATQA and SAK accordingly response1[0] |= 0x40; sak |= 0x04; } else { num_to_bytes(uid_1st,4,response2); // Configure the ATQA and SAK accordingly response1[0] &= 0xBF; sak &= 0xFB; } // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID. response2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3]; // Prepare the mandatory SAK (for 4 and 7 byte UID) uint8_t response3[3]; response3[0] = sak; ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]); // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit uint8_t response3a[3]; response3a[0] = sak & 0xFB; ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]); uint8_t response5[] = { 0x00, 0x00, 0x00, 0x00 }; // Very random tag nonce uint8_t response6[] = { 0x03, 0x3B, 0x00, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS ComputeCrc14443(CRC_14443_A, response6, 3, &response6[3], &response6[4]); uint8_t *resp = NULL; int respLen; // Longest possible response will be 16 bytes + 2 CRC = 18 bytes // This will need // 144 data bits (18 * 8) // 18 parity bits // 2 Start and stop // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA) // 1 just for the case // ----------- + // 166 // // 166 bytes, since every bit that needs to be send costs us a byte // // Respond with card type uint8_t *resp1 = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET); int resp1Len; // Anticollision cascade1 - respond with uid uint8_t *resp2 = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET + 166); int resp2Len; // Anticollision cascade2 - respond with 2nd half of uid if asked // we're only going to be asked if we set the 1st byte of the UID (during cascade1) to 0x88 uint8_t *resp2a = (((uint8_t *)BigBuf) + 1140); int resp2aLen; // Acknowledge select - cascade 1 uint8_t *resp3 = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET + (166*2)); int resp3Len; // Acknowledge select - cascade 2 uint8_t *resp3a = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET + (166*3)); int resp3aLen; // Response to a read request - not implemented atm uint8_t *resp4 = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET + (166*4)); // int resp4Len; // Authenticate response - nonce uint8_t *resp5 = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET + (166*5)); int resp5Len; // Authenticate response - nonce uint8_t *resp6 = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET + (166*6)); int resp6Len; uint8_t *receivedCmd = (((uint8_t *)BigBuf) + RECV_CMD_OFFSET); int len; // To control where we are in the protocol int order = 0; int lastorder; // Just to allow some checks int happened = 0; int happened2 = 0; int cmdsRecvd = 0; uint8_t* respdata = NULL; int respsize = 0; // uint8_t nack = 0x04; memset(receivedCmd, 0x44, RECV_CMD_SIZE); // Prepare the responses of the anticollision phase // there will be not enough time to do this at the moment the reader sends it REQA // Answer to request CodeIso14443aAsTag(response1, sizeof(response1)); memcpy(resp1, ToSend, ToSendMax); resp1Len = ToSendMax; // Send our UID (cascade 1) CodeIso14443aAsTag(response2, sizeof(response2)); memcpy(resp2, ToSend, ToSendMax); resp2Len = ToSendMax; // Answer to select (cascade1) CodeIso14443aAsTag(response3, sizeof(response3)); memcpy(resp3, ToSend, ToSendMax); resp3Len = ToSendMax; // Send the cascade 2 2nd part of the uid CodeIso14443aAsTag(response2a, sizeof(response2a)); memcpy(resp2a, ToSend, ToSendMax); resp2aLen = ToSendMax; // Answer to select (cascade 2) CodeIso14443aAsTag(response3a, sizeof(response3a)); memcpy(resp3a, ToSend, ToSendMax); resp3aLen = ToSendMax; // Strange answer is an example of rare message size (3 bits) CodeStrangeAnswerAsTag(); memcpy(resp4, ToSend, ToSendMax);// resp4Len = ToSendMax; // Authentication answer (random nonce) CodeIso14443aAsTag(response5, sizeof(response5)); memcpy(resp5, ToSend, ToSendMax); resp5Len = ToSendMax; // dummy ATS (pseudo-ATR), answer to RATS CodeIso14443aAsTag(response6, sizeof(response6)); memcpy(resp6, ToSend, ToSendMax); resp6Len = ToSendMax; // We need to listen to the high-frequency, peak-detected path. SetAdcMuxFor(GPIO_MUXSEL_HIPKD); FpgaSetupSsc(); cmdsRecvd = 0; LED_A_ON(); for(;;) { if(!GetIso14443aCommandFromReader(receivedCmd, &len, RECV_CMD_SIZE)) { DbpString("button press"); break; } if (tracing) { LogTrace(receivedCmd,len, 0, Uart.parityBits, TRUE); } // doob - added loads of debug strings so we can see what the reader is saying to us during the sim as hi14alist is not populated // Okay, look at the command now. lastorder = order; if(receivedCmd[0] == 0x26) { // Received a REQUEST resp = resp1; respLen = resp1Len; order = 1; respdata = response1; respsize = sizeof(response1); } else if(receivedCmd[0] == 0x52) { // Received a WAKEUP resp = resp1; respLen = resp1Len; order = 6; respdata = response1; respsize = sizeof(response1); } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x93) { // Received request for UID (cascade 1) resp = resp2; respLen = resp2Len; order = 2; respdata = response2; respsize = sizeof(response2); } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x95) { // Received request for UID (cascade 2) resp = resp2a; respLen = resp2aLen; order = 20; respdata = response2a; respsize = sizeof(response2a); } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x93) { // Received a SELECT (cascade 1) resp = resp3; respLen = resp3Len; order = 3; respdata = response3; respsize = sizeof(response3); } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x95) { // Received a SELECT (cascade 2) resp = resp3a; respLen = resp3aLen; order = 30; respdata = response3a; respsize = sizeof(response3a); } else if(receivedCmd[0] == 0x30) { // Received a (plain) READ // resp = resp4; respLen = resp4Len; order = 4; // Do nothing // respdata = &nack; // respsize = sizeof(nack); // 4-bit answer EmSendCmdEx(data+(4*receivedCmd[0]),16,false); Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]); // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below respLen = 0; } else if(receivedCmd[0] == 0x50) { // Received a HALT // DbpString("Reader requested we HALT!:"); // Do not respond resp = resp1; respLen = 0; order = 0; respdata = NULL; respsize = 0; } else if(receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61) { // Received an authentication request resp = resp5; respLen = resp5Len; order = 7; respdata = response5; respsize = sizeof(response5); } else if(receivedCmd[0] == 0xE0) { // Received a RATS request resp = resp6; respLen = resp6Len; order = 70; respdata = response6; respsize = sizeof(response6); } else { if (order == 7 && len ==8) { uint32_t nr = bytes_to_num(receivedCmd,4); uint32_t ar = bytes_to_num(receivedCmd+4,4); Dbprintf("Auth attempt {nr}{ar}: %08x %08x",nr,ar); } else { // Never seen this command before Dbprintf("Received unknown command (len=%d):",len); Dbhexdump(len,receivedCmd,false); } // Do not respond resp = resp1; respLen = 0; order = 0; respdata = NULL; respsize = 0; } // Count number of wakeups received after a halt if(order == 6 && lastorder == 5) { happened++; } // Count number of other messages after a halt if(order != 6 && lastorder == 5) { happened2++; } // Look at last parity bit to determine timing of answer if((Uart.parityBits & 0x01) || receivedCmd[0] == 0x52) { // 1236, so correction bit needed //i = 0; } if(cmdsRecvd > 999) { DbpString("1000 commands later..."); break; } else { cmdsRecvd++; } if(respLen > 0) { EmSendCmd14443aRaw(resp, respLen, receivedCmd[0] == 0x52); } if (tracing) { if (respdata != NULL) { LogTrace(respdata,respsize, 0, SwapBits(GetParity(respdata,respsize),respsize), FALSE); } if(traceLen > TRACE_SIZE) { DbpString("Trace full"); break; } } memset(receivedCmd, 0x44, RECV_CMD_SIZE); } Dbprintf("%x %x %x", happened, happened2, cmdsRecvd); LED_A_OFF(); } //----------------------------------------------------------------------------- // Transmit the command (to the tag) that was placed in ToSend[]. //----------------------------------------------------------------------------- static void TransmitFor14443a(const uint8_t *cmd, int len, int *samples, int *wait) { int c; FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD); if (wait) if(*wait < 10) *wait = 10; for(c = 0; c < *wait;) { if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { AT91C_BASE_SSC->SSC_THR = 0x00; // For exact timing! c++; } if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR; (void)r; } WDT_HIT(); } c = 0; for(;;) { if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { AT91C_BASE_SSC->SSC_THR = cmd[c]; c++; if(c >= len) { break; } } if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR; (void)r; } WDT_HIT(); } if (samples) *samples = (c + *wait) << 3; } //----------------------------------------------------------------------------- // Prepare reader command (in bits, support short frames) to send to FPGA //----------------------------------------------------------------------------- void CodeIso14443aBitsAsReaderPar(const uint8_t * cmd, int bits, uint32_t dwParity) { int i, j; int last; uint8_t b; ToSendReset(); // Start of Communication (Seq. Z) ToSend[++ToSendMax] = SEC_Z; last = 0; size_t bytecount = nbytes(bits); // Generate send structure for the data bits for (i = 0; i < bytecount; i++) { // Get the current byte to send b = cmd[i]; size_t bitsleft = MIN((bits-(i*8)),8); for (j = 0; j < bitsleft; j++) { if (b & 1) { // Sequence X ToSend[++ToSendMax] = SEC_X; last = 1; } else { if (last == 0) { // Sequence Z ToSend[++ToSendMax] = SEC_Z; } else { // Sequence Y ToSend[++ToSendMax] = SEC_Y; last = 0; } } b >>= 1; } // Only transmit (last) parity bit if we transmitted a complete byte if (j == 8) { // Get the parity bit if ((dwParity >> i) & 0x01) { // Sequence X ToSend[++ToSendMax] = SEC_X; last = 1; } else { if (last == 0) { // Sequence Z ToSend[++ToSendMax] = SEC_Z; } else { // Sequence Y ToSend[++ToSendMax] = SEC_Y; last = 0; } } } } // End of Communication if (last == 0) { // Sequence Z ToSend[++ToSendMax] = SEC_Z; } else { // Sequence Y ToSend[++ToSendMax] = SEC_Y; last = 0; } // Sequence Y ToSend[++ToSendMax] = SEC_Y; // Just to be sure! ToSend[++ToSendMax] = SEC_Y; ToSend[++ToSendMax] = SEC_Y; ToSend[++ToSendMax] = SEC_Y; // Convert from last character reference to length ToSendMax++; } //----------------------------------------------------------------------------- // Prepare reader command to send to FPGA //----------------------------------------------------------------------------- void CodeIso14443aAsReaderPar(const uint8_t * cmd, int len, uint32_t dwParity) { CodeIso14443aBitsAsReaderPar(cmd,len*8,dwParity); } //----------------------------------------------------------------------------- // Wait for commands from reader // Stop when button is pressed (return 1) or field was gone (return 2) // Or return 0 when command is captured //----------------------------------------------------------------------------- static int EmGetCmd(uint8_t *received, int *len, int maxLen) { *len = 0; uint32_t timer = 0, vtime = 0; int analogCnt = 0; int analogAVG = 0; // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen // only, since we are receiving, not transmitting). // Signal field is off with the appropriate LED LED_D_OFF(); FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN); // Set ADC to read field strength AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST; AT91C_BASE_ADC->ADC_MR = ADC_MODE_PRESCALE(32) | ADC_MODE_STARTUP_TIME(16) | ADC_MODE_SAMPLE_HOLD_TIME(8); AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF); // start ADC AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START; // Now run a 'software UART' on the stream of incoming samples. Uart.output = received; Uart.byteCntMax = maxLen; Uart.state = STATE_UNSYNCD; for(;;) { WDT_HIT(); if (BUTTON_PRESS()) return 1; // test if the field exists if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) { analogCnt++; analogAVG += AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF]; AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START; if (analogCnt >= 32) { if ((33000 * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) { vtime = GetTickCount(); if (!timer) timer = vtime; // 50ms no field --> card to idle state if (vtime - timer > 50) return 2; } else if (timer) timer = 0; analogCnt = 0; analogAVG = 0; } } // transmit none if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { AT91C_BASE_SSC->SSC_THR = 0x00; } // receive and test the miller decoding if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { volatile uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR; if(MillerDecoding((b & 0xf0) >> 4)) { *len = Uart.byteCnt; if (tracing) LogTrace(received, *len, GetDeltaCountUS(), Uart.parityBits, TRUE); return 0; } if(MillerDecoding(b & 0x0f)) { *len = Uart.byteCnt; if (tracing) LogTrace(received, *len, GetDeltaCountUS(), Uart.parityBits, TRUE); return 0; } } } } static int EmSendCmd14443aRaw(uint8_t *resp, int respLen, int correctionNeeded) { int i, u = 0; uint8_t b = 0; // Modulate Manchester FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD); AT91C_BASE_SSC->SSC_THR = 0x00; FpgaSetupSsc(); // include correction bit i = 1; if((Uart.parityBits & 0x01) || correctionNeeded) { // 1236, so correction bit needed i = 0; } // send cycle for(;;) { if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { volatile uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR; (void)b; } if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { if(i > respLen) { b = 0xff; // was 0x00 u++; } else { b = resp[i]; i++; } AT91C_BASE_SSC->SSC_THR = b; if(u > 4) break; } if(BUTTON_PRESS()) { break; } } return 0; } int EmSend4bitEx(uint8_t resp, int correctionNeeded){ Code4bitAnswerAsTag(resp); int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded); if (tracing) LogTrace(&resp, 1, GetDeltaCountUS(), GetParity(&resp, 1), FALSE); return res; } int EmSend4bit(uint8_t resp){ return EmSend4bitEx(resp, 0); } int EmSendCmdExPar(uint8_t *resp, int respLen, int correctionNeeded, uint32_t par){ CodeIso14443aAsTagPar(resp, respLen, par); int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded); if (tracing) LogTrace(resp, respLen, GetDeltaCountUS(), par, FALSE); return res; } int EmSendCmdEx(uint8_t *resp, int respLen, int correctionNeeded){ return EmSendCmdExPar(resp, respLen, correctionNeeded, GetParity(resp, respLen)); } int EmSendCmd(uint8_t *resp, int respLen){ return EmSendCmdExPar(resp, respLen, 0, GetParity(resp, respLen)); } int EmSendCmdPar(uint8_t *resp, int respLen, uint32_t par){ return EmSendCmdExPar(resp, respLen, 0, par); } //----------------------------------------------------------------------------- // Wait a certain time for tag response // If a response is captured return TRUE // If it takes to long return FALSE //----------------------------------------------------------------------------- static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, int maxLen, int *samples, int *elapsed) //uint8_t *buffer { // buffer needs to be 512 bytes int c; // Set FPGA mode to "reader listen mode", no modulation (listen // only, since we are receiving, not transmitting). // Signal field is on with the appropriate LED LED_D_ON(); FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN); // Now get the answer from the card Demod.output = receivedResponse; Demod.len = 0; Demod.state = DEMOD_UNSYNCD; uint8_t b; if (elapsed) *elapsed = 0; c = 0; for(;;) { WDT_HIT(); if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { AT91C_BASE_SSC->SSC_THR = 0x00; // To make use of exact timing of next command from reader!! if (elapsed) (*elapsed)++; } if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { if(c < iso14a_timeout) { c++; } else { return FALSE; } b = (uint8_t)AT91C_BASE_SSC->SSC_RHR; if(ManchesterDecoding((b>>4) & 0xf)) { *samples = ((c - 1) << 3) + 4; return TRUE; } if(ManchesterDecoding(b & 0x0f)) { *samples = c << 3; return TRUE; } } } } void ReaderTransmitBitsPar(uint8_t* frame, int bits, uint32_t par) { int wait = 0; int samples = 0; // This is tied to other size changes // uint8_t* frame_addr = ((uint8_t*)BigBuf) + 2024; CodeIso14443aBitsAsReaderPar(frame,bits,par); // Select the card TransmitFor14443a(ToSend, ToSendMax, &samples, &wait); if(trigger) LED_A_ON(); // Store reader command in buffer if (tracing) LogTrace(frame,nbytes(bits),0,par,TRUE); } void ReaderTransmitPar(uint8_t* frame, int len, uint32_t par) { ReaderTransmitBitsPar(frame,len*8,par); } void ReaderTransmit(uint8_t* frame, int len) { // Generate parity and redirect ReaderTransmitBitsPar(frame,len*8,GetParity(frame,len)); } int ReaderReceive(uint8_t* receivedAnswer) { int samples = 0; if (!GetIso14443aAnswerFromTag(receivedAnswer,160,&samples,0)) return FALSE; if (tracing) LogTrace(receivedAnswer,Demod.len,samples,Demod.parityBits,FALSE); if(samples == 0) return FALSE; return Demod.len; } int ReaderReceivePar(uint8_t* receivedAnswer, uint32_t * parptr) { int samples = 0; if (!GetIso14443aAnswerFromTag(receivedAnswer,160,&samples,0)) return FALSE; if (tracing) LogTrace(receivedAnswer,Demod.len,samples,Demod.parityBits,FALSE); *parptr = Demod.parityBits; if(samples == 0) return FALSE; return Demod.len; } /* performs iso14443a anticolision procedure * fills the uid pointer unless NULL * fills resp_data unless NULL */ int iso14443a_select_card(byte_t* uid_ptr, iso14a_card_select_t* p_hi14a_card, uint32_t* cuid_ptr) { uint8_t wupa[] = { 0x52 }; // 0x26 - REQA 0x52 - WAKE-UP uint8_t sel_all[] = { 0x93,0x20 }; uint8_t sel_uid[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00 }; uint8_t rats[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0 uint8_t* resp = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET); // was 3560 - tied to other size changes byte_t uid_resp[4]; size_t uid_resp_len; uint8_t sak = 0x04; // cascade uid int cascade_level = 0; int len; // Broadcast for a card, WUPA (0x52) will force response from all cards in the field ReaderTransmitBitsPar(wupa,7,0); // Receive the ATQA if(!ReaderReceive(resp)) return 0; // Dbprintf("atqa: %02x %02x",resp[0],resp[1]); if(p_hi14a_card) { memcpy(p_hi14a_card->atqa, resp, 2); p_hi14a_card->uidlen = 0; memset(p_hi14a_card->uid,0,10); } // clear uid if (uid_ptr) { memset(uid_ptr,0,10); } // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in // which case we need to make a cascade 2 request and select - this is a long UID // While the UID is not complete, the 3nd bit (from the right) is set in the SAK. for(; sak & 0x04; cascade_level++) { // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97) sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2; // SELECT_ALL ReaderTransmit(sel_all,sizeof(sel_all)); if (!ReaderReceive(resp)) return 0; // First backup the current uid memcpy(uid_resp,resp,4); uid_resp_len = 4; // Dbprintf("uid: %02x %02x %02x %02x",uid_resp[0],uid_resp[1],uid_resp[2],uid_resp[3]); // calculate crypto UID if(cuid_ptr) { *cuid_ptr = bytes_to_num(uid_resp, 4); } // Construct SELECT UID command memcpy(sel_uid+2,resp,5); AppendCrc14443a(sel_uid,7); ReaderTransmit(sel_uid,sizeof(sel_uid)); // Receive the SAK if (!ReaderReceive(resp)) return 0; sak = resp[0]; // Test if more parts of the uid are comming if ((sak & 0x04) && uid_resp[0] == 0x88) { // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of: // http://www.nxp.com/documents/application_note/AN10927.pdf memcpy(uid_resp, uid_resp + 1, 3); uid_resp_len = 3; } if(uid_ptr) { memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len); } if(p_hi14a_card) { memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len); p_hi14a_card->uidlen += uid_resp_len; } } if(p_hi14a_card) { p_hi14a_card->sak = sak; p_hi14a_card->ats_len = 0; } if( (sak & 0x20) == 0) { return 2; // non iso14443a compliant tag } // Request for answer to select AppendCrc14443a(rats, 2); ReaderTransmit(rats, sizeof(rats)); if (!(len = ReaderReceive(resp))) return 0; if(p_hi14a_card) { memcpy(p_hi14a_card->ats, resp, sizeof(p_hi14a_card->ats)); p_hi14a_card->ats_len = len; } // reset the PCB block number iso14_pcb_blocknum = 0; return 1; } void iso14443a_setup() { // Set up the synchronous serial port FpgaSetupSsc(); // Start from off (no field generated) // Signal field is off with the appropriate LED LED_D_OFF(); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); SpinDelay(50); SetAdcMuxFor(GPIO_MUXSEL_HIPKD); // Now give it time to spin up. // Signal field is on with the appropriate LED LED_D_ON(); FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD); SpinDelay(50); iso14a_timeout = 2048; //default } int iso14_apdu(uint8_t * cmd, size_t cmd_len, void * data) { uint8_t real_cmd[cmd_len+4]; real_cmd[0] = 0x0a; //I-Block // put block number into the PCB real_cmd[0] |= iso14_pcb_blocknum; real_cmd[1] = 0x00; //CID: 0 //FIXME: allow multiple selected cards memcpy(real_cmd+2, cmd, cmd_len); AppendCrc14443a(real_cmd,cmd_len+2); ReaderTransmit(real_cmd, cmd_len+4); size_t len = ReaderReceive(data); uint8_t * data_bytes = (uint8_t *) data; if (!len) return 0; //DATA LINK ERROR // if we received an I- or R(ACK)-Block with a block number equal to the // current block number, toggle the current block number else if (len >= 4 // PCB+CID+CRC = 4 bytes && ((data_bytes[0] & 0xC0) == 0 // I-Block || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0 && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers { iso14_pcb_blocknum ^= 1; } return len; } //----------------------------------------------------------------------------- // Read an ISO 14443a tag. Send out commands and store answers. // //----------------------------------------------------------------------------- void ReaderIso14443a(UsbCommand * c) { iso14a_command_t param = c->arg[0]; uint8_t * cmd = c->d.asBytes; size_t len = c->arg[1]; uint32_t arg0 = 0; byte_t buf[USB_CMD_DATA_SIZE]; iso14a_clear_trace(); iso14a_set_tracing(true); if(param & ISO14A_REQUEST_TRIGGER) { iso14a_set_trigger(1); } if(param & ISO14A_CONNECT) { iso14443a_setup(); arg0 = iso14443a_select_card(NULL,(iso14a_card_select_t*)buf,NULL); cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(iso14a_card_select_t)); // UsbSendPacket((void *)ack, sizeof(UsbCommand)); } if(param & ISO14A_SET_TIMEOUT) { iso14a_timeout = c->arg[2]; } if(param & ISO14A_SET_TIMEOUT) { iso14a_timeout = c->arg[2]; } if(param & ISO14A_APDU) { arg0 = iso14_apdu(cmd, len, buf); cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf)); // UsbSendPacket((void *)ack, sizeof(UsbCommand)); } if(param & ISO14A_RAW) { if(param & ISO14A_APPEND_CRC) { AppendCrc14443a(cmd,len); len += 2; } ReaderTransmit(cmd,len); arg0 = ReaderReceive(buf); // UsbSendPacket((void *)ack, sizeof(UsbCommand)); cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf)); } if(param & ISO14A_REQUEST_TRIGGER) { iso14a_set_trigger(0); } if(param & ISO14A_NO_DISCONNECT) { return; } FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); LEDsoff(); } // prepare the Mifare AUTH transfer with an added necessary delay. void PrepareDelayedAuthTransfer(uint8_t* frame, int len, uint16_t delay) { CodeIso14443aBitsAsReaderPar(frame, len*8, GetParity(frame,len)); uint8_t bitmask = 0; uint8_t bits_to_shift = 0; uint8_t bits_shifted = 0; if (delay) { for (uint16_t i = 0; i < delay; i++) { bitmask |= (0x01 << i); } ToSend[++ToSendMax] = 0x00; for (uint16_t i = 0; i < ToSendMax; i++) { bits_to_shift = ToSend[i] & bitmask; ToSend[i] = ToSend[i] >> delay; ToSend[i] = ToSend[i] | (bits_shifted << (8 - delay)); bits_shifted = bits_to_shift; } } } // Determine the distance between two nonces. // Assume that the difference is small, but we don't know which is first. // Therefore try in alternating directions. int32_t dist_nt(uint32_t nt1, uint32_t nt2) { uint16_t i; uint32_t nttmp1, nttmp2; if (nt1 == nt2) return 0; nttmp1 = nt1; nttmp2 = nt2; for (i = 1; i < 32768; i++) { nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i; nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -i; } return(-99999); // either nt1 or nt2 are invalid nonces } //----------------------------------------------------------------------------- // Recover several bits of the cypher stream. This implements (first stages of) // the algorithm described in "The Dark Side of Security by Obscurity and // Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime" // (article by Nicolas T. Courtois, 2009) //----------------------------------------------------------------------------- void ReaderMifare(bool first_try) { // Mifare AUTH uint8_t mf_auth[] = { 0x60,0x00,0xf5,0x7b }; uint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 }; static uint8_t mf_nr_ar3; uint8_t* receivedAnswer = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET); traceLen = 0; tracing = false; byte_t nt_diff = 0; byte_t par = 0; //byte_t par_mask = 0xff; static byte_t par_low = 0; bool led_on = TRUE; uint8_t uid[10]; uint32_t cuid; uint32_t nt, previous_nt; static uint32_t nt_attacked = 0; byte_t par_list[8] = {0,0,0,0,0,0,0,0}; byte_t ks_list[8] = {0,0,0,0,0,0,0,0}; static uint32_t sync_time; static uint32_t sync_cycles; int catch_up_cycles = 0; int last_catch_up = 0; uint16_t consecutive_resyncs = 0; int isOK = 0; if (first_try) { StartCountMifare(); mf_nr_ar3 = 0; iso14443a_setup(); FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN); // resets some FPGA internal registers while((GetCountMifare() & 0xffff0000) != 0x10000); // wait for counter to reset and "warm up" while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME); // wait for ssp_frame to be low while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME)); // sync on rising edge of ssp_frame sync_time = GetCountMifare(); sync_cycles = 65536; // theory: Mifare Classic's random generator repeats every 2^16 cycles (and so do the nonces). nt_attacked = 0; nt = 0; par = 0; } else { // we were unsuccessful on a previous call. Try another READER nonce (first 3 parity bits remain the same) // nt_attacked = prng_successor(nt_attacked, 1); mf_nr_ar3++; mf_nr_ar[3] = mf_nr_ar3; par = par_low; } LED_A_ON(); LED_B_OFF(); LED_C_OFF(); for(uint16_t i = 0; TRUE; i++) { WDT_HIT(); // Test if the action was cancelled if(BUTTON_PRESS()) { break; } LED_C_ON(); if(!iso14443a_select_card(uid, NULL, &cuid)) { continue; } //keep the card active FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD); PrepareDelayedAuthTransfer(mf_auth, sizeof(mf_auth), (sync_cycles + catch_up_cycles) & 0x00000007); sync_time = sync_time + ((sync_cycles + catch_up_cycles) & 0xfffffff8); catch_up_cycles = 0; // if we missed the sync time already, advance to the next nonce repeat while(GetCountMifare() > sync_time) { sync_time = sync_time + (sync_cycles & 0xfffffff8); } // now sync. After syncing, the following Classic Auth will return the same tag nonce (mostly) while(GetCountMifare() < sync_time); // Transmit MIFARE_CLASSIC_AUTH int samples = 0; int wait = 0; TransmitFor14443a(ToSend, ToSendMax, &samples, &wait); // Receive the (4 Byte) "random" nonce if (!ReaderReceive(receivedAnswer)) { continue; } previous_nt = nt; nt = bytes_to_num(receivedAnswer, 4); // Transmit reader nonce with fake par ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par); if (first_try && previous_nt && !nt_attacked) { // we didn't calibrate our clock yet int nt_distance = dist_nt(previous_nt, nt); if (nt_distance == 0) { nt_attacked = nt; } else { if (nt_distance == -99999) { // invalid nonce received, try again continue; } sync_cycles = (sync_cycles - nt_distance); // Dbprintf("calibrating in cycle %d. nt_distance=%d, Sync_cycles: %d\n", i, nt_distance, sync_cycles); continue; } } if ((nt != nt_attacked) && nt_attacked) { // we somehow lost sync. Try to catch up again... catch_up_cycles = -dist_nt(nt_attacked, nt); if (catch_up_cycles == 99999) { // invalid nonce received. Don't resync on that one. catch_up_cycles = 0; continue; } if (catch_up_cycles == last_catch_up) { consecutive_resyncs++; } else { last_catch_up = catch_up_cycles; consecutive_resyncs = 0; } if (consecutive_resyncs < 3) { Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i, -catch_up_cycles, consecutive_resyncs); } else { sync_cycles = sync_cycles + catch_up_cycles; Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i, -catch_up_cycles, sync_cycles); } continue; } consecutive_resyncs = 0; // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding if (ReaderReceive(receivedAnswer)) { catch_up_cycles = 8; // the PRNG doesn't run during data transfers. 4 Bit = 8 cycles if (nt_diff == 0) { par_low = par & 0x07; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change } led_on = !led_on; if(led_on) LED_B_ON(); else LED_B_OFF(); par_list[nt_diff] = par; ks_list[nt_diff] = receivedAnswer[0] ^ 0x05; // Test if the information is complete if (nt_diff == 0x07) { isOK = 1; break; } nt_diff = (nt_diff + 1) & 0x07; mf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5); par = par_low; } else { if (nt_diff == 0 && first_try) { par++; } else { par = (((par >> 3) + 1) << 3) | par_low; } } } LogTrace((const uint8_t *)&nt, 4, 0, GetParity((const uint8_t *)&nt, 4), TRUE); LogTrace(par_list, 8, 0, GetParity(par_list, 8), TRUE); LogTrace(ks_list, 8, 0, GetParity(ks_list, 8), TRUE); mf_nr_ar[3] &= 0x1F; byte_t buf[28]; memcpy(buf + 0, uid, 4); num_to_bytes(nt, 4, buf + 4); memcpy(buf + 8, par_list, 8); memcpy(buf + 16, ks_list, 8); memcpy(buf + 24, mf_nr_ar, 4); cmd_send(CMD_ACK,isOK,0,0,buf,28); // Thats it... FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); LEDsoff(); tracing = TRUE; } //----------------------------------------------------------------------------- // MIFARE 1K simulate. // //----------------------------------------------------------------------------- void Mifare1ksim(uint8_t arg0, uint8_t arg1, uint8_t arg2, uint8_t *datain) { int cardSTATE = MFEMUL_NOFIELD; int _7BUID = 0; int vHf = 0; // in mV //int nextCycleTimeout = 0; int res; // uint32_t timer = 0; uint32_t selTimer = 0; uint32_t authTimer = 0; uint32_t par = 0; int len = 0; uint8_t cardWRBL = 0; uint8_t cardAUTHSC = 0; uint8_t cardAUTHKEY = 0xff; // no authentication //uint32_t cardRn = 0; uint32_t cardRr = 0; uint32_t cuid = 0; //uint32_t rn_enc = 0; uint32_t ans = 0; uint32_t cardINTREG = 0; uint8_t cardINTBLOCK = 0; struct Crypto1State mpcs = {0, 0}; struct Crypto1State *pcs; pcs = &mpcs; uint8_t* receivedCmd = eml_get_bigbufptr_recbuf(); uint8_t *response = eml_get_bigbufptr_sendbuf(); static uint8_t rATQA[] = {0x04, 0x00}; // Mifare classic 1k 4BUID static uint8_t rUIDBCC1[] = {0xde, 0xad, 0xbe, 0xaf, 0x62}; static uint8_t rUIDBCC2[] = {0xde, 0xad, 0xbe, 0xaf, 0x62}; // !!! static uint8_t rSAK[] = {0x08, 0xb6, 0xdd}; static uint8_t rSAK1[] = {0x04, 0xda, 0x17}; static uint8_t rAUTH_NT[] = {0x01, 0x02, 0x03, 0x04}; // static uint8_t rAUTH_NT[] = {0x1a, 0xac, 0xff, 0x4f}; static uint8_t rAUTH_AT[] = {0x00, 0x00, 0x00, 0x00}; // clear trace traceLen = 0; tracing = true; // Authenticate response - nonce uint32_t nonce = bytes_to_num(rAUTH_NT, 4); // get UID from emul memory emlGetMemBt(receivedCmd, 7, 1); _7BUID = !(receivedCmd[0] == 0x00); if (!_7BUID) { // ---------- 4BUID rATQA[0] = 0x04; emlGetMemBt(rUIDBCC1, 0, 4); rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3]; } else { // ---------- 7BUID rATQA[0] = 0x44; rUIDBCC1[0] = 0x88; emlGetMemBt(&rUIDBCC1[1], 0, 3); rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3]; emlGetMemBt(rUIDBCC2, 3, 4); rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3]; } // -------------------------------------- test area // -------------------------------------- END test area // start mkseconds counter StartCountUS(); // We need to listen to the high-frequency, peak-detected path. SetAdcMuxFor(GPIO_MUXSEL_HIPKD); FpgaSetupSsc(); FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN); SpinDelay(200); if (MF_DBGLEVEL >= 1) Dbprintf("Started. 7buid=%d", _7BUID); // calibrate mkseconds counter GetDeltaCountUS(); while (true) { WDT_HIT(); if(BUTTON_PRESS()) { break; } // find reader field // Vref = 3300mV, and an 10:1 voltage divider on the input // can measure voltages up to 33000 mV if (cardSTATE == MFEMUL_NOFIELD) { vHf = (33000 * AvgAdc(ADC_CHAN_HF)) >> 10; if (vHf > MF_MINFIELDV) { cardSTATE_TO_IDLE(); LED_A_ON(); } } if (cardSTATE != MFEMUL_NOFIELD) { res = EmGetCmd(receivedCmd, &len, RECV_CMD_SIZE); // (+ nextCycleTimeout) if (res == 2) { cardSTATE = MFEMUL_NOFIELD; LEDsoff(); continue; } if(res) break; } //nextCycleTimeout = 0; // if (len) Dbprintf("len:%d cmd: %02x %02x %02x %02x", len, receivedCmd[0], receivedCmd[1], receivedCmd[2], receivedCmd[3]); if (len != 4 && cardSTATE != MFEMUL_NOFIELD) { // len != 4 <---- speed up the code 4 authentication // REQ or WUP request in ANY state and WUP in HALTED state if (len == 1 && ((receivedCmd[0] == 0x26 && cardSTATE != MFEMUL_HALTED) || receivedCmd[0] == 0x52)) { selTimer = GetTickCount(); EmSendCmdEx(rATQA, sizeof(rATQA), (receivedCmd[0] == 0x52)); cardSTATE = MFEMUL_SELECT1; // init crypto block LED_B_OFF(); LED_C_OFF(); crypto1_destroy(pcs); cardAUTHKEY = 0xff; } } switch (cardSTATE) { case MFEMUL_NOFIELD:{ break; } case MFEMUL_HALTED:{ break; } case MFEMUL_IDLE:{ break; } case MFEMUL_SELECT1:{ // select all if (len == 2 && (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x20)) { EmSendCmd(rUIDBCC1, sizeof(rUIDBCC1)); break; } // select card if (len == 9 && (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC1, 4) == 0)) { if (!_7BUID) EmSendCmd(rSAK, sizeof(rSAK)); else EmSendCmd(rSAK1, sizeof(rSAK1)); cuid = bytes_to_num(rUIDBCC1, 4); if (!_7BUID) { cardSTATE = MFEMUL_WORK; LED_B_ON(); if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol1 time: %d", GetTickCount() - selTimer); break; } else { cardSTATE = MFEMUL_SELECT2; break; } } break; } case MFEMUL_SELECT2:{ if (!len) break; if (len == 2 && (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x20)) { EmSendCmd(rUIDBCC2, sizeof(rUIDBCC2)); break; } // select 2 card if (len == 9 && (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC2, 4) == 0)) { EmSendCmd(rSAK, sizeof(rSAK)); cuid = bytes_to_num(rUIDBCC2, 4); cardSTATE = MFEMUL_WORK; LED_B_ON(); if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol2 time: %d", GetTickCount() - selTimer); break; } // i guess there is a command). go into the work state. if (len != 4) break; cardSTATE = MFEMUL_WORK; goto lbWORK; } case MFEMUL_AUTH1:{ if (len == 8) { // --- crypto //rn_enc = bytes_to_num(receivedCmd, 4); //cardRn = rn_enc ^ crypto1_word(pcs, rn_enc , 1); cardRr = bytes_to_num(&receivedCmd[4], 4) ^ crypto1_word(pcs, 0, 0); // test if auth OK if (cardRr != prng_successor(nonce, 64)){ if (MF_DBGLEVEL >= 4) Dbprintf("AUTH FAILED. cardRr=%08x, succ=%08x", cardRr, prng_successor(nonce, 64)); cardSTATE_TO_IDLE(); break; } ans = prng_successor(nonce, 96) ^ crypto1_word(pcs, 0, 0); num_to_bytes(ans, 4, rAUTH_AT); // --- crypto EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT)); cardSTATE = MFEMUL_AUTH2; } else { cardSTATE_TO_IDLE(); } if (cardSTATE != MFEMUL_AUTH2) break; } case MFEMUL_AUTH2:{ LED_C_ON(); cardSTATE = MFEMUL_WORK; if (MF_DBGLEVEL >= 4) Dbprintf("AUTH COMPLETED. sec=%d, key=%d time=%d", cardAUTHSC, cardAUTHKEY, GetTickCount() - authTimer); break; } case MFEMUL_WORK:{ lbWORK: if (len == 0) break; if (cardAUTHKEY == 0xff) { // first authentication if (len == 4 && (receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61)) { authTimer = GetTickCount(); cardAUTHSC = receivedCmd[1] / 4; // received block num cardAUTHKEY = receivedCmd[0] - 0x60; // --- crypto crypto1_create(pcs, emlGetKey(cardAUTHSC, cardAUTHKEY)); ans = nonce ^ crypto1_word(pcs, cuid ^ nonce, 0); num_to_bytes(nonce, 4, rAUTH_AT); EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT)); // --- crypto // last working revision // EmSendCmd14443aRaw(resp1, resp1Len, 0); // LogTrace(NULL, 0, GetDeltaCountUS(), 0, true); cardSTATE = MFEMUL_AUTH1; //nextCycleTimeout = 10; break; } } else { // decrypt seqence mf_crypto1_decrypt(pcs, receivedCmd, len); // nested authentication if (len == 4 && (receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61)) { authTimer = GetTickCount(); cardAUTHSC = receivedCmd[1] / 4; // received block num cardAUTHKEY = receivedCmd[0] - 0x60; // --- crypto crypto1_create(pcs, emlGetKey(cardAUTHSC, cardAUTHKEY)); ans = nonce ^ crypto1_word(pcs, cuid ^ nonce, 0); num_to_bytes(ans, 4, rAUTH_AT); EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT)); // --- crypto cardSTATE = MFEMUL_AUTH1; //nextCycleTimeout = 10; break; } } // rule 13 of 7.5.3. in ISO 14443-4. chaining shall be continued // BUT... ACK --> NACK if (len == 1 && receivedCmd[0] == CARD_ACK) { EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA)); break; } // rule 12 of 7.5.3. in ISO 14443-4. R(NAK) --> R(ACK) if (len == 1 && receivedCmd[0] == CARD_NACK_NA) { EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK)); break; } // read block if (len == 4 && receivedCmd[0] == 0x30) { if (receivedCmd[1] >= 16 * 4 || receivedCmd[1] / 4 != cardAUTHSC) { EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA)); break; } emlGetMem(response, receivedCmd[1], 1); AppendCrc14443a(response, 16); mf_crypto1_encrypt(pcs, response, 18, &par); EmSendCmdPar(response, 18, par); break; } // write block if (len == 4 && receivedCmd[0] == 0xA0) { if (receivedCmd[1] >= 16 * 4 || receivedCmd[1] / 4 != cardAUTHSC) { EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA)); break; } EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK)); //nextCycleTimeout = 50; cardSTATE = MFEMUL_WRITEBL2; cardWRBL = receivedCmd[1]; break; } // works with cardINTREG // increment, decrement, restore if (len == 4 && (receivedCmd[0] == 0xC0 || receivedCmd[0] == 0xC1 || receivedCmd[0] == 0xC2)) { if (receivedCmd[1] >= 16 * 4 || receivedCmd[1] / 4 != cardAUTHSC || emlCheckValBl(receivedCmd[1])) { EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA)); break; } EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK)); if (receivedCmd[0] == 0xC1) cardSTATE = MFEMUL_INTREG_INC; if (receivedCmd[0] == 0xC0) cardSTATE = MFEMUL_INTREG_DEC; if (receivedCmd[0] == 0xC2) cardSTATE = MFEMUL_INTREG_REST; cardWRBL = receivedCmd[1]; break; } // transfer if (len == 4 && receivedCmd[0] == 0xB0) { if (receivedCmd[1] >= 16 * 4 || receivedCmd[1] / 4 != cardAUTHSC) { EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA)); break; } if (emlSetValBl(cardINTREG, cardINTBLOCK, receivedCmd[1])) EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA)); else EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK)); break; } // halt if (len == 4 && (receivedCmd[0] == 0x50 && receivedCmd[1] == 0x00)) { LED_B_OFF(); LED_C_OFF(); cardSTATE = MFEMUL_HALTED; if (MF_DBGLEVEL >= 4) Dbprintf("--> HALTED. Selected time: %d ms", GetTickCount() - selTimer); break; } // command not allowed if (len == 4) { EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA)); break; } // case break break; } case MFEMUL_WRITEBL2:{ if (len == 18){ mf_crypto1_decrypt(pcs, receivedCmd, len); emlSetMem(receivedCmd, cardWRBL, 1); EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK)); cardSTATE = MFEMUL_WORK; break; } else { cardSTATE_TO_IDLE(); break; } break; } case MFEMUL_INTREG_INC:{ mf_crypto1_decrypt(pcs, receivedCmd, len); memcpy(&ans, receivedCmd, 4); if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) { EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA)); cardSTATE_TO_IDLE(); break; } cardINTREG = cardINTREG + ans; cardSTATE = MFEMUL_WORK; break; } case MFEMUL_INTREG_DEC:{ mf_crypto1_decrypt(pcs, receivedCmd, len); memcpy(&ans, receivedCmd, 4); if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) { EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA)); cardSTATE_TO_IDLE(); break; } cardINTREG = cardINTREG - ans; cardSTATE = MFEMUL_WORK; break; } case MFEMUL_INTREG_REST:{ mf_crypto1_decrypt(pcs, receivedCmd, len); memcpy(&ans, receivedCmd, 4); if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) { EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA)); cardSTATE_TO_IDLE(); break; } cardSTATE = MFEMUL_WORK; break; } } } FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); LEDsoff(); // add trace trailer memset(rAUTH_NT, 0x44, 4); LogTrace(rAUTH_NT, 4, 0, 0, TRUE); if (MF_DBGLEVEL >= 1) Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, traceLen); } //----------------------------------------------------------------------------- // MIFARE sniffer. // //----------------------------------------------------------------------------- void RAMFUNC SniffMifare(uint8_t param) { // param: // bit 0 - trigger from first card answer // bit 1 - trigger from first reader 7-bit request // C(red) A(yellow) B(green) LEDsoff(); // init trace buffer iso14a_clear_trace(); // The command (reader -> tag) that we're receiving. // The length of a received command will in most cases be no more than 18 bytes. // So 32 should be enough! uint8_t *receivedCmd = (((uint8_t *)BigBuf) + RECV_CMD_OFFSET); // The response (tag -> reader) that we're receiving. uint8_t *receivedResponse = (((uint8_t *)BigBuf) + RECV_RES_OFFSET); // As we receive stuff, we copy it from receivedCmd or receivedResponse // into trace, along with its length and other annotations. //uint8_t *trace = (uint8_t *)BigBuf; // The DMA buffer, used to stream samples from the FPGA int8_t *dmaBuf = ((int8_t *)BigBuf) + DMA_BUFFER_OFFSET; int8_t *data = dmaBuf; int maxDataLen = 0; int dataLen = 0; // Set up the demodulator for tag -> reader responses. Demod.output = receivedResponse; Demod.len = 0; Demod.state = DEMOD_UNSYNCD; // Set up the demodulator for the reader -> tag commands memset(&Uart, 0, sizeof(Uart)); Uart.output = receivedCmd; Uart.byteCntMax = 32; // was 100 (greg)////////////////// Uart.state = STATE_UNSYNCD; // Setup for the DMA. FpgaSetupSsc(); FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // And put the FPGA in the appropriate mode // Signal field is off with the appropriate LED LED_D_OFF(); FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_SNIFFER); SetAdcMuxFor(GPIO_MUXSEL_HIPKD); // init sniffer MfSniffInit(); int sniffCounter = 0; // And now we loop, receiving samples. while(true) { if(BUTTON_PRESS()) { DbpString("cancelled by button"); goto done; } LED_A_ON(); WDT_HIT(); if (++sniffCounter > 65) { if (MfSniffSend(2000)) { FpgaEnableSscDma(); } sniffCounter = 0; } int register readBufDataP = data - dmaBuf; int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; if (readBufDataP <= dmaBufDataP){ dataLen = dmaBufDataP - readBufDataP; } else { dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP + 1; } // test for length of buffer if(dataLen > maxDataLen) { maxDataLen = dataLen; if(dataLen > 400) { Dbprintf("blew circular buffer! dataLen=0x%x", dataLen); goto done; } } if(dataLen < 1) continue; // primary buffer was stopped( <-- we lost data! if (!AT91C_BASE_PDC_SSC->PDC_RCR) { AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf; AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE; Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary } // secondary buffer sets as primary, secondary buffer was stopped if (!AT91C_BASE_PDC_SSC->PDC_RNCR) { AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf; AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE; } LED_A_OFF(); if(MillerDecoding((data[0] & 0xF0) >> 4)) { LED_C_INV(); // check - if there is a short 7bit request from reader if (MfSniffLogic(receivedCmd, Uart.byteCnt, Uart.parityBits, Uart.bitCnt, TRUE)) break; /* And ready to receive another command. */ Uart.state = STATE_UNSYNCD; /* And also reset the demod code */ Demod.state = DEMOD_UNSYNCD; } if(ManchesterDecoding(data[0] & 0x0F)) { LED_C_INV(); if (MfSniffLogic(receivedResponse, Demod.len, Demod.parityBits, Demod.bitCount, FALSE)) break; // And ready to receive another response. memset(&Demod, 0, sizeof(Demod)); Demod.output = receivedResponse; Demod.state = DEMOD_UNSYNCD; /* And also reset the uart code */ Uart.state = STATE_UNSYNCD; } data++; if(data > dmaBuf + DMA_BUFFER_SIZE) { data = dmaBuf; } } // main cycle DbpString("COMMAND FINISHED"); done: FpgaDisableSscDma(); MfSniffEnd(); Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.byteCnt=%x Uart.byteCntMax=%x", maxDataLen, Uart.state, Uart.byteCnt, Uart.byteCntMax); LEDsoff(); } ================================================ FILE: TamagotchiFriends/proxmark/armsrc/iso14443a.h ================================================ //----------------------------------------------------------------------------- // Merlok - June 2011 // Gerhard de Koning Gans - May 2008 // Hagen Fritsch - June 2010 // // This code is licensed to you under the terms of the GNU GPL, version 2 or, // at your option, any later version. See the LICENSE.txt file for the text of // the license. //----------------------------------------------------------------------------- // Routines to support ISO 14443 type A. //----------------------------------------------------------------------------- #ifndef __ISO14443A_H #define __ISO14443A_H #include "common.h" #include "mifaresniff.h" // mifare reader over DMA buffer (SnoopIso14443a())!!! #define MIFARE_BUFF_OFFSET 3560 // \/ \/ \/ // card emulator memory #define EML_RESPONSES 4000 #define CARD_MEMORY 6000 #define CARD_MEMORY_LEN 4096 typedef struct nestedVector { uint32_t nt, ks1; } nestedVector; typedef struct { enum { DEMOD_UNSYNCD, DEMOD_START_OF_COMMUNICATION, DEMOD_MANCHESTER_D, DEMOD_MANCHESTER_E, DEMOD_MANCHESTER_F, DEMOD_ERROR_WAIT } state; int bitCount; int posCount; int syncBit; int parityBits; uint16_t shiftReg; int buffer; int buff; int samples; int len; enum { SUB_NONE, SUB_FIRST_HALF, SUB_SECOND_HALF } sub; uint8_t *output; } tDemod; typedef struct { enum { STATE_UNSYNCD, STATE_START_OF_COMMUNICATION, STATE_MILLER_X, STATE_MILLER_Y, STATE_MILLER_Z, STATE_ERROR_WAIT } state; uint16_t shiftReg; int bitCnt; int byteCnt; int byteCntMax; int posCnt; int syncBit; int parityBits; int samples; int highCnt; int bitBuffer; enum { DROP_NONE, DROP_FIRST_HALF, DROP_SECOND_HALF } drop; uint8_t *output; } tUart; extern byte_t oddparity (const byte_t bt); extern uint32_t GetParity(const uint8_t * pbtCmd, int iLen); extern void AppendCrc14443a(uint8_t* data, int len); extern void ReaderTransmit(uint8_t* frame, int len); extern void ReaderTransmitBitsPar(uint8_t* frame, int bits, uint32_t par); extern void ReaderTransmitPar(uint8_t* frame, int len, uint32_t par); extern int ReaderReceive(uint8_t* receivedAnswer); extern int ReaderReceivePar(uint8_t* receivedAnswer, uint32_t * parptr); extern void iso14443a_setup(); extern int iso14_apdu(uint8_t * cmd, size_t cmd_len, void * data); extern int iso14443a_select_card(uint8_t * uid_ptr, iso14a_card_select_t * resp_data, uint32_t * cuid_ptr); extern void iso14a_set_trigger(bool enable); extern void iso14a_set_timeout(uint32_t timeout); extern void iso14a_clear_tracelen(); extern void iso14a_set_tracing(bool enable); #endif /* __ISO14443A_H */ ================================================ FILE: TamagotchiFriends/proxmark/armsrc/iso15693.c ================================================ //----------------------------------------------------------------------------- // Jonathan Westhues, split Nov 2006 // Modified by Greg Jones, Jan 2009 // Modified by Adrian Dabrowski "atrox", Mar-Sept 2010,Oct 2011 // // This code is licensed to you under the terms of the GNU GPL, version 2 or, // at your option, any later version. See the LICENSE.txt file for the text of // the license. //----------------------------------------------------------------------------- // Routines to support ISO 15693. This includes both the reader software and // the `fake tag' modes, but at the moment I've implemented only the reader // stuff, and that barely. // Modified to perform modulation onboard in arm rather than on PC // Also added additional reader commands (SELECT, READ etc.) //----------------------------------------------------------------------------- // The ISO 15693 describes two transmission modes from reader to tag, and 4 // transmission modes from tag to reader. As of Mar 2010 this code only // supports one of each: "1of4" mode from reader to tag, and the highspeed // variant with one subcarrier from card to reader. // As long, as the card fully support ISO 15693 this is no problem, since the // reader chooses both data rates, but some non-standard tags do not. Further for // the simulation to work, we will need to support all data rates. // // VCD (reader) -> VICC (tag) // 1 out of 256: // data rate: 1,66 kbit/s (fc/8192) // used for long range // 1 out of 4: // data rate: 26,48 kbit/s (fc/512) // used for short range, high speed // // VICC (tag) -> VCD (reader) // Modulation: // ASK / one subcarrier (423,75 khz) // FSK / two subcarriers (423,75 khz && 484,28 khz) // Data Rates / Modes: // low ASK: 6,62 kbit/s // low FSK: 6.67 kbit/s // high ASK: 26,48 kbit/s // high FSK: 26,69 kbit/s //----------------------------------------------------------------------------- // added "1 out of 256" mode (for VCD->PICC) - atrox 20100911 // Random Remarks: // *) UID is always used "transmission order" (LSB), which is reverse to display order // TODO / BUGS / ISSUES: // *) writing to tags takes longer: we miss the answer from the tag in most cases // -> tweak the read-timeout times // *) signal decoding from the card is still a bit shaky. // *) signal decoding is unable to detect collissions. // *) add anti-collission support for inventory-commands // *) read security status of a block // *) sniffing and simulation do only support one transmission mode. need to support // all 8 transmission combinations // *) remove or refactor code under "depricated" // *) document all the functions #include "proxmark3.h" #include "util.h" #include "apps.h" #include "string.h" #include "iso15693tools.h" #include "cmd.h" #define arraylen(x) (sizeof(x)/sizeof((x)[0])) /////////////////////////////////////////////////////////////////////// // ISO 15693 Part 2 - Air Interface // This section basicly contains transmission and receiving of bits /////////////////////////////////////////////////////////////////////// #define FrameSOF Iso15693FrameSOF #define Logic0 Iso15693Logic0 #define Logic1 Iso15693Logic1 #define FrameEOF Iso15693FrameEOF #define Crc(data,datalen) Iso15693Crc(data,datalen) #define AddCrc(data,datalen) Iso15693AddCrc(data,datalen) #define sprintUID(target,uid) Iso15693sprintUID(target,uid) int DEBUG=0; // --------------------------- // Signal Processing // --------------------------- // prepare data using "1 out of 4" code for later transmission // resulting data rate is 26,48 kbit/s (fc/512) // cmd ... data // n ... length of data static void CodeIso15693AsReader(uint8_t *cmd, int n) { int i, j; ToSendReset(); // Give it a bit of slack at the beginning for(i = 0; i < 24; i++) { ToSendStuffBit(1); } // SOF for 1of4 ToSendStuffBit(0); ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(0); ToSendStuffBit(1); ToSendStuffBit(1); for(i = 0; i < n; i++) { for(j = 0; j < 8; j += 2) { int these = (cmd[i] >> j) & 3; switch(these) { case 0: ToSendStuffBit(1); ToSendStuffBit(0); ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(1); break; case 1: ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(0); ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(1); break; case 2: ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(0); ToSendStuffBit(1); ToSendStuffBit(1); break; case 3: ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(0); break; } } } // EOF ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(0); ToSendStuffBit(1); // And slack at the end, too. for(i = 0; i < 24; i++) { ToSendStuffBit(1); } } // encode data using "1 out of 256" sheme // data rate is 1,66 kbit/s (fc/8192) // is designed for more robust communication over longer distances static void CodeIso15693AsReader256(uint8_t *cmd, int n) { int i, j; ToSendReset(); // Give it a bit of slack at the beginning for(i = 0; i < 24; i++) { ToSendStuffBit(1); } // SOF for 1of256 ToSendStuffBit(0); ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(0); for(i = 0; i < n; i++) { for (j = 0; j<=255; j++) { if (cmd[i]==j) { ToSendStuffBit(1); ToSendStuffBit(0); } else { ToSendStuffBit(1); ToSendStuffBit(1); } } } // EOF ToSendStuffBit(1); ToSendStuffBit(1); ToSendStuffBit(0); ToSendStuffBit(1); // And slack at the end, too. for(i = 0; i < 24; i++) { ToSendStuffBit(1); } } // Transmit the command (to the tag) that was placed in ToSend[]. static void TransmitTo15693Tag(const uint8_t *cmd, int len, int *samples, int *wait) { int c; // FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD); FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX); if(*wait < 10) { *wait = 10; } // for(c = 0; c < *wait;) { // if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { // AT91C_BASE_SSC->SSC_THR = 0x00; // For exact timing! // c++; // } // if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { // volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR; // (void)r; // } // WDT_HIT(); // } c = 0; for(;;) { if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { AT91C_BASE_SSC->SSC_THR = cmd[c]; c++; if(c >= len) { break; } } if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR; (void)r; } WDT_HIT(); } *samples = (c + *wait) << 3; } //----------------------------------------------------------------------------- // Transmit the command (to the reader) that was placed in ToSend[]. //----------------------------------------------------------------------------- static void TransmitTo15693Reader(const uint8_t *cmd, int len, int *samples, int *wait) { int c; // FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX); FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR); // No requirement to energise my coils if(*wait < 10) { *wait = 10; } c = 0; for(;;) { if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { AT91C_BASE_SSC->SSC_THR = cmd[c]; c++; if(c >= len) { break; } } if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR; (void)r; } WDT_HIT(); } *samples = (c + *wait) << 3; } // Read from Tag // Parameters: // receivedResponse // maxLen // samples // elapsed // returns: // number of decoded bytes static int GetIso15693AnswerFromTag(uint8_t *receivedResponse, int maxLen, int *samples, int *elapsed) { int c = 0; uint8_t *dest = (uint8_t *)BigBuf; int getNext = 0; int8_t prev = 0; // NOW READ RESPONSE FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR); //spindelay(60); // greg - experiment to get rid of some of the 0 byte/failed reads c = 0; getNext = FALSE; for(;;) { if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { AT91C_BASE_SSC->SSC_THR = 0x43; } if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { int8_t b; b = (int8_t)AT91C_BASE_SSC->SSC_RHR; // The samples are correlations against I and Q versions of the // tone that the tag AM-modulates, so every other sample is I, // every other is Q. We just want power, so abs(I) + abs(Q) is // close to what we want. if(getNext) { int8_t r; if(b < 0) { r = -b; } else { r = b; } if(prev < 0) { r -= prev; } else { r += prev; } dest[c++] = (uint8_t)r; if(c >= 2000) { break; } } else { prev = b; } getNext = !getNext; } } ////////////////////////////////////////// /////////// DEMODULATE /////////////////// ////////////////////////////////////////// int i, j; int max = 0, maxPos=0; int skip = 4; // if(GraphTraceLen < 1000) return; // THIS CHECKS FOR A BUFFER TO SMALL // First, correlate for SOF for(i = 0; i < 100; i++) { int corr = 0; for(j = 0; j < arraylen(FrameSOF); j += skip) { corr += FrameSOF[j]*dest[i+(j/skip)]; } if(corr > max) { max = corr; maxPos = i; } } // DbpString("SOF at %d, correlation %d", maxPos,max/(arraylen(FrameSOF)/skip)); int k = 0; // this will be our return value // greg - If correlation is less than 1 then there's little point in continuing if ((max/(arraylen(FrameSOF)/skip)) >= 1) { i = maxPos + arraylen(FrameSOF)/skip; uint8_t outBuf[20]; memset(outBuf, 0, sizeof(outBuf)); uint8_t mask = 0x01; for(;;) { int corr0 = 0, corr1 = 0, corrEOF = 0; for(j = 0; j < arraylen(Logic0); j += skip) { corr0 += Logic0[j]*dest[i+(j/skip)]; } for(j = 0; j < arraylen(Logic1); j += skip) { corr1 += Logic1[j]*dest[i+(j/skip)]; } for(j = 0; j < arraylen(FrameEOF); j += skip) { corrEOF += FrameEOF[j]*dest[i+(j/skip)]; } // Even things out by the length of the target waveform. corr0 *= 4; corr1 *= 4; if(corrEOF > corr1 && corrEOF > corr0) { // DbpString("EOF at %d", i); break; } else if(corr1 > corr0) { i += arraylen(Logic1)/skip; outBuf[k] |= mask; } else { i += arraylen(Logic0)/skip; } mask <<= 1; if(mask == 0) { k++; mask = 0x01; } if((i+(int)arraylen(FrameEOF)) >= 2000) { DbpString("ran off end!"); break; } } if(mask != 0x01) { // this happens, when we miss the EOF // TODO: for some reason this happens quite often if (DEBUG) Dbprintf("error, uneven octet! (extra bits!) mask=%02x", mask); if (mask<0x08) k--; // discard the last uneven octet; // 0x08 is an assumption - but works quite often } // uint8_t str1 [8]; // itoa(k,str1); // strncat(str1," octets read",8); // DbpString( str1); // DbpString("%d octets", k); // for(i = 0; i < k; i+=3) { // //DbpString("# %2d: %02x ", i, outBuf[i]); // DbpIntegers(outBuf[i],outBuf[i+1],outBuf[i+2]); // } for(i = 0; i < k; i++) { receivedResponse[i] = outBuf[i]; } } // "end if correlation > 0" (max/(arraylen(FrameSOF)/skip)) return k; // return the number of bytes demodulated /// DbpString("CRC=%04x", Iso15693Crc(outBuf, k-2)); } // Now the GetISO15693 message from sniffing command static int GetIso15693AnswerFromSniff(uint8_t *receivedResponse, int maxLen, int *samples, int *elapsed) { int c = 0; uint8_t *dest = (uint8_t *)BigBuf; int getNext = 0; int8_t prev = 0; // NOW READ RESPONSE FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR); //spindelay(60); // greg - experiment to get rid of some of the 0 byte/failed reads c = 0; getNext = FALSE; for(;;) { if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { AT91C_BASE_SSC->SSC_THR = 0x43; } if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { int8_t b; b = (int8_t)AT91C_BASE_SSC->SSC_RHR; // The samples are correlations against I and Q versions of the // tone that the tag AM-modulates, so every other sample is I, // every other is Q. We just want power, so abs(I) + abs(Q) is // close to what we want. if(getNext) { int8_t r; if(b < 0) { r = -b; } else { r = b; } if(prev < 0) { r -= prev; } else { r += prev; } dest[c++] = (uint8_t)r; if(c >= 20000) { break; } } else { prev = b; } getNext = !getNext; } } ////////////////////////////////////////// /////////// DEMODULATE /////////////////// ////////////////////////////////////////// int i, j; int max = 0, maxPos=0; int skip = 4; // if(GraphTraceLen < 1000) return; // THIS CHECKS FOR A BUFFER TO SMALL // First, correlate for SOF for(i = 0; i < 19000; i++) { int corr = 0; for(j = 0; j < arraylen(FrameSOF); j += skip) { corr += FrameSOF[j]*dest[i+(j/skip)]; } if(corr > max) { max = corr; maxPos = i; } } // DbpString("SOF at %d, correlation %d", maxPos,max/(arraylen(FrameSOF)/skip)); int k = 0; // this will be our return value // greg - If correlation is less than 1 then there's little point in continuing if ((max/(arraylen(FrameSOF)/skip)) >= 1) // THIS SHOULD BE 1 { i = maxPos + arraylen(FrameSOF)/skip; uint8_t outBuf[20]; memset(outBuf, 0, sizeof(outBuf)); uint8_t mask = 0x01; for(;;) { int corr0 = 0, corr1 = 0, corrEOF = 0; for(j = 0; j < arraylen(Logic0); j += skip) { corr0 += Logic0[j]*dest[i+(j/skip)]; } for(j = 0; j < arraylen(Logic1); j += skip) { corr1 += Logic1[j]*dest[i+(j/skip)]; } for(j = 0; j < arraylen(FrameEOF); j += skip) { corrEOF += FrameEOF[j]*dest[i+(j/skip)]; } // Even things out by the length of the target waveform. corr0 *= 4; corr1 *= 4; if(corrEOF > corr1 && corrEOF > corr0) { // DbpString("EOF at %d", i); break; } else if(corr1 > corr0) { i += arraylen(Logic1)/skip; outBuf[k] |= mask; } else { i += arraylen(Logic0)/skip; } mask <<= 1; if(mask == 0) { k++; mask = 0x01; } if((i+(int)arraylen(FrameEOF)) >= 2000) { DbpString("ran off end!"); break; } } if(mask != 0x01) { DbpString("sniff: error, uneven octet! (discard extra bits!)"); /// DbpString(" mask=%02x", mask); } // uint8_t str1 [8]; // itoa(k,str1); // strncat(str1," octets read",8); // DbpString( str1); // DbpString("%d octets", k); // for(i = 0; i < k; i+=3) { // //DbpString("# %2d: %02x ", i, outBuf[i]); // DbpIntegers(outBuf[i],outBuf[i+1],outBuf[i+2]); // } for(i = 0; i < k; i++) { receivedResponse[i] = outBuf[i]; } } // "end if correlation > 0" (max/(arraylen(FrameSOF)/skip)) return k; // return the number of bytes demodulated /// DbpString("CRC=%04x", Iso15693Crc(outBuf, k-2)); } static void BuildIdentifyRequest(void); //----------------------------------------------------------------------------- // Start to read an ISO 15693 tag. We send an identify request, then wait // for the response. The response is not demodulated, just left in the buffer // so that it can be downloaded to a PC and processed there. //----------------------------------------------------------------------------- void AcquireRawAdcSamplesIso15693(void) { int c = 0; uint8_t *dest = (uint8_t *)BigBuf; int getNext = 0; int8_t prev = 0; BuildIdentifyRequest(); SetAdcMuxFor(GPIO_MUXSEL_HIPKD); // Give the tags time to energize FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR); SpinDelay(100); // Now send the command FpgaSetupSsc(); FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX); c = 0; for(;;) { if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { AT91C_BASE_SSC->SSC_THR = ToSend[c]; c++; if(c == ToSendMax+3) { break; } } if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR; (void)r; } WDT_HIT(); } FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR); c = 0; getNext = FALSE; for(;;) { if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { AT91C_BASE_SSC->SSC_THR = 0x43; } if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { int8_t b; b = (int8_t)AT91C_BASE_SSC->SSC_RHR; // The samples are correlations against I and Q versions of the // tone that the tag AM-modulates, so every other sample is I, // every other is Q. We just want power, so abs(I) + abs(Q) is // close to what we want. if(getNext) { int8_t r; if(b < 0) { r = -b; } else { r = b; } if(prev < 0) { r -= prev; } else { r += prev; } dest[c++] = (uint8_t)r; if(c >= 2000) { break; } } else { prev = b; } getNext = !getNext; } } } void RecordRawAdcSamplesIso15693(void) { int c = 0; uint8_t *dest = (uint8_t *)BigBuf; int getNext = 0; int8_t prev = 0; // Setup SSC FpgaSetupSsc(); // Start from off (no field generated) FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); SpinDelay(200); SetAdcMuxFor(GPIO_MUXSEL_HIPKD); SpinDelay(100); FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR); c = 0; getNext = FALSE; for(;;) { if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { AT91C_BASE_SSC->SSC_THR = 0x43; } if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { int8_t b; b = (int8_t)AT91C_BASE_SSC->SSC_RHR; // The samples are correlations against I and Q versions of the // tone that the tag AM-modulates, so every other sample is I, // every other is Q. We just want power, so abs(I) + abs(Q) is // close to what we want. if(getNext) { int8_t r; if(b < 0) { r = -b; } else { r = b; } if(prev < 0) { r -= prev; } else { r += prev; } dest[c++] = (uint8_t)r; if(c >= 7000) { break; } } else { prev = b; } getNext = !getNext; WDT_HIT(); } } Dbprintf("fin record"); } // Initialize the proxmark as iso15k reader // (this might produces glitches that confuse some tags void Iso15693InitReader() { LED_A_ON(); LED_B_ON(); LED_C_OFF(); LED_D_OFF(); // Setup SSC // FpgaSetupSsc(); // Start from off (no field generated) FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); SpinDelay(10); SetAdcMuxFor(GPIO_MUXSEL_HIPKD); FpgaSetupSsc(); // Give the tags time to energize FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR); SpinDelay(250); LED_A_ON(); LED_B_OFF(); LED_C_OFF(); LED_D_OFF(); } /////////////////////////////////////////////////////////////////////// // ISO 15693 Part 3 - Air Interface // This section basicly contains transmission and receiving of bits /////////////////////////////////////////////////////////////////////// // Encode (into the ToSend buffers) an identify request, which is the first // thing that you must send to a tag to get a response. static void BuildIdentifyRequest(void) { uint8_t cmd[5]; uint16_t crc; // one sub-carrier, inventory, 1 slot, fast rate // AFI is at bit 5 (1<<4) when doing an INVENTORY cmd[0] = (1 << 2) | (1 << 5) | (1 << 1); // inventory command code cmd[1] = 0x01; // no mask cmd[2] = 0x00; //Now the CRC crc = Crc(cmd, 3); cmd[3] = crc & 0xff; cmd[4] = crc >> 8; CodeIso15693AsReader(cmd, sizeof(cmd)); } // uid is in transmission order (which is reverse of display order) static void BuildReadBlockRequest(uint8_t *uid, uint8_t blockNumber ) { uint8_t cmd[13]; uint16_t crc; // If we set the Option_Flag in this request, the VICC will respond with the secuirty status of the block // followed by teh block data // one sub-carrier, inventory, 1 slot, fast rate cmd[0] = (1 << 6)| (1 << 5) | (1 << 1); // no SELECT bit, ADDR bit, OPTION bit // READ BLOCK command code cmd[1] = 0x20; // UID may be optionally specified here // 64-bit UID cmd[2] = uid[0]; cmd[3] = uid[1]; cmd[4] = uid[2]; cmd[5] = uid[3]; cmd[6] = uid[4]; cmd[7] = uid[5]; cmd[8] = uid[6]; cmd[9] = uid[7]; // 0xe0; // always e0 (not exactly unique) // Block number to read cmd[10] = blockNumber;//0x00; //Now the CRC crc = Crc(cmd, 11); // the crc needs to be calculated over 12 bytes cmd[11] = crc & 0xff; cmd[12] = crc >> 8; CodeIso15693AsReader(cmd, sizeof(cmd)); } // Now the VICC>VCD responses when we are simulating a tag static void BuildInventoryResponse(void) { uint8_t cmd[12]; uint16_t crc; // one sub-carrier, inventory, 1 slot, fast rate // AFI is at bit 5 (1<<4) when doing an INVENTORY cmd[0] = 0; //(1 << 2) | (1 << 5) | (1 << 1); cmd[1] = 0; // 64-bit UID cmd[2] = 0x32; cmd[3]= 0x4b; cmd[4] = 0x03; cmd[5] = 0x01; cmd[6] = 0x00; cmd[7] = 0x10; cmd[8] = 0x05; cmd[9]= 0xe0; //Now the CRC crc = Crc(cmd, 10); cmd[10] = crc & 0xff; cmd[11] = crc >> 8; CodeIso15693AsReader(cmd, sizeof(cmd)); } // Universal Method for sending to and recv bytes from a tag // init ... should we initialize the reader? // speed ... 0 low speed, 1 hi speed // **recv will return you a pointer to the received data // If you do not need the answer use NULL for *recv[] // return: lenght of received data int SendDataTag(uint8_t *send, int sendlen, int init, int speed, uint8_t **recv) { int samples = 0; int tsamples = 0; int wait = 0; int elapsed = 0; LED_A_ON(); LED_B_ON(); LED_C_OFF(); LED_D_OFF(); int answerLen=0; uint8_t *answer = (((uint8_t *)BigBuf) + 3660); if (recv!=NULL) memset(BigBuf + 3660, 0, 100); if (init) Iso15693InitReader(); if (!speed) { // low speed (1 out of 256) CodeIso15693AsReader256(send, sendlen); } else { // high speed (1 out of 4) CodeIso15693AsReader(send, sendlen); } LED_A_ON(); LED_B_OFF(); TransmitTo15693Tag(ToSend,ToSendMax,&tsamples, &wait); // Now wait for a response if (recv!=NULL) { LED_A_OFF(); LED_B_ON(); answerLen = GetIso15693AnswerFromTag(answer, 100, &samples, &elapsed) ; *recv=answer; } LED_A_OFF(); LED_B_OFF(); LED_C_OFF(); LED_D_OFF(); return answerLen; } // -------------------------------------------------------------------- // Debug Functions // -------------------------------------------------------------------- // Decodes a message from a tag and displays its metadata and content #define DBD15STATLEN 48 void DbdecodeIso15693Answer(int len, uint8_t *d) { char status[DBD15STATLEN+1]={0}; uint16_t crc; if (len>3) { if (d[0]&(1<<3)) strncat(status,"ProtExt ",DBD15STATLEN); if (d[0]&1) { // error strncat(status,"Error ",DBD15STATLEN); switch (d[1]) { case 0x01: strncat(status,"01:notSupp",DBD15STATLEN); break; case 0x02: strncat(status,"02:notRecog",DBD15STATLEN); break; case 0x03: strncat(status,"03:optNotSupp",DBD15STATLEN); break; case 0x0f: strncat(status,"0f:noInfo",DBD15STATLEN); break; case 0x10: strncat(status,"10:dontExist",DBD15STATLEN); break; case 0x11: strncat(status,"11:lockAgain",DBD15STATLEN); break; case 0x12: strncat(status,"12:locked",DBD15STATLEN); break; case 0x13: strncat(status,"13:progErr",DBD15STATLEN); break; case 0x14: strncat(status,"14:lockErr",DBD15STATLEN); break; default: strncat(status,"unknownErr",DBD15STATLEN); } strncat(status," ",DBD15STATLEN); } else { strncat(status,"NoErr ",DBD15STATLEN); } crc=Crc(d,len-2); if ( (( crc & 0xff ) == d[len-2]) && (( crc >> 8 ) == d[len-1]) ) strncat(status,"CrcOK",DBD15STATLEN); else strncat(status,"CrcFail!",DBD15STATLEN); Dbprintf("%s",status); } } /////////////////////////////////////////////////////////////////////// // Functions called via USB/Client /////////////////////////////////////////////////////////////////////// void SetDebugIso15693(uint32_t debug) { DEBUG=debug; Dbprintf("Iso15693 Debug is now %s",DEBUG?"on":"off"); return; } //----------------------------------------------------------------------------- // Simulate an ISO15693 reader, perform anti-collision and then attempt to read a sector // all demodulation performed in arm rather than host. - greg //----------------------------------------------------------------------------- void ReaderIso15693(uint32_t parameter) { LED_A_ON(); LED_B_ON(); LED_C_OFF(); LED_D_OFF(); //DbpString(parameter); //uint8_t *answer0 = (((uint8_t *)BigBuf) + 3560); // allow 100 bytes per reponse (way too much) uint8_t *answer1 = (((uint8_t *)BigBuf) + 3660); // uint8_t *answer2 = (((uint8_t *)BigBuf) + 3760); uint8_t *answer3 = (((uint8_t *)BigBuf) + 3860); //uint8_t *TagUID= (((uint8_t *)BigBuf) + 3960); // where we hold the uid for hi15reader // int answerLen0 = 0; int answerLen1 = 0; int answerLen2 = 0; int answerLen3 = 0; int i=0; // counter // Blank arrays memset(BigBuf + 3660, 0, 300); // Setup SSC FpgaSetupSsc(); // Start from off (no field generated) FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); SpinDelay(200); SetAdcMuxFor(GPIO_MUXSEL_HIPKD); FpgaSetupSsc(); // Give the tags time to energize FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR); SpinDelay(200); LED_A_ON(); LED_B_OFF(); LED_C_OFF(); LED_D_OFF(); int samples = 0; int tsamples = 0; int wait = 0; int elapsed = 0; // FIRST WE RUN AN INVENTORY TO GET THE TAG UID // THIS MEANS WE CAN PRE-BUILD REQUESTS TO SAVE CPU TIME uint8_t TagUID[8] = {0, 0, 0, 0, 0, 0, 0, 0}; // where we hold the uid for hi15reader // BuildIdentifyRequest(); // //TransmitTo15693Tag(ToSend,ToSendMax+3,&tsamples, &wait); // TransmitTo15693Tag(ToSend,ToSendMax,&tsamples, &wait); // No longer ToSendMax+3 // // Now wait for a response // responseLen0 = GetIso15693AnswerFromTag(receivedAnswer0, 100, &samples, &elapsed) ; // if (responseLen0 >=12) // we should do a better check than this // { // // really we should check it is a valid mesg // // but for now just grab what we think is the uid // TagUID[0] = receivedAnswer0[2]; // TagUID[1] = receivedAnswer0[3]; // TagUID[2] = receivedAnswer0[4]; // TagUID[3] = receivedAnswer0[5]; // TagUID[4] = receivedAnswer0[6]; // TagUID[5] = receivedAnswer0[7]; // TagUID[6] = receivedAnswer0[8]; // IC Manufacturer code // DbpIntegers(TagUID[6],TagUID[5],TagUID[4]); //} // Now send the IDENTIFY command BuildIdentifyRequest(); //TransmitTo15693Tag(ToSend,ToSendMax+3,&tsamples, &wait); TransmitTo15693Tag(ToSend,ToSendMax,&tsamples, &wait); // No longer ToSendMax+3 // Now wait for a response answerLen1 = GetIso15693AnswerFromTag(answer1, 100, &samples, &elapsed) ; if (answerLen1 >=12) // we should do a better check than this { TagUID[0] = answer1[2]; TagUID[1] = answer1[3]; TagUID[2] = answer1[4]; TagUID[3] = answer1[5]; TagUID[4] = answer1[6]; TagUID[5] = answer1[7]; TagUID[6] = answer1[8]; // IC Manufacturer code TagUID[7] = answer1[9]; // always E0 // Now send the SELECT command // since the SELECT command is optional, we should not rely on it. //// BuildSelectRequest(TagUID); // TransmitTo15693Tag(ToSend,ToSendMax,&tsamples, &wait); // No longer ToSendMax+3 // Now wait for a response /// answerLen2 = GetIso15693AnswerFromTag(answer2, 100, &samples, &elapsed); // Now send the MULTI READ command // BuildArbitraryRequest(*TagUID,parameter); /// BuildArbitraryCustomRequest(TagUID,parameter); // BuildReadBlockRequest(*TagUID,parameter); // BuildSysInfoRequest(*TagUID); //TransmitTo15693Tag(ToSend,ToSendMax+3,&tsamples, &wait); /// TransmitTo15693Tag(ToSend,ToSendMax,&tsamples, &wait); // No longer ToSendMax+3 // Now wait for a response /// answerLen3 = GetIso15693AnswerFromTag(answer3, 100, &samples, &elapsed) ; } Dbprintf("%d octets read from IDENTIFY request:", answerLen1); DbdecodeIso15693Answer(answerLen1,answer1); Dbhexdump(answerLen1,answer1,true); // UID is reverse if (answerLen1>=12) //Dbprintf("UID = %*D",8,TagUID," "); Dbprintf("UID = %02hX%02hX%02hX%02hX%02hX%02hX%02hX%02hX",TagUID[7],TagUID[6],TagUID[5], TagUID[4],TagUID[3],TagUID[2],TagUID[1],TagUID[0]); Dbprintf("%d octets read from SELECT request:", answerLen2); DbdecodeIso15693Answer(answerLen2,answer2); Dbhexdump(answerLen2,answer2,true); Dbprintf("%d octets read from XXX request:", answerLen3); DbdecodeIso15693Answer(answerLen3,answer3); Dbhexdump(answerLen3,answer3,true); // read all pages if (answerLen1>=12 && DEBUG) { i=0; while (i<32) { // sanity check, assume max 32 pages BuildReadBlockRequest(TagUID,i); TransmitTo15693Tag(ToSend,ToSendMax,&tsamples, &wait); answerLen2 = GetIso15693AnswerFromTag(answer2, 100, &samples, &elapsed); if (answerLen2>0) { Dbprintf("READ SINGLE BLOCK %d returned %d octets:",i,answerLen2); DbdecodeIso15693Answer(answerLen2,answer2); Dbhexdump(answerLen2,answer2,true); if ( *((uint32_t*) answer2) == 0x07160101 ) break; // exit on NoPageErr } i++; } } // str2[0]=0; // for(i = 0; i < responseLen3; i++) { // itoa(str1,receivedAnswer3[i]); // strncat(str2,str1,8); // } // DbpString(str2); LED_A_OFF(); LED_B_OFF(); LED_C_OFF(); LED_D_OFF(); } // Simulate an ISO15693 TAG, perform anti-collision and then print any reader commands // all demodulation performed in arm rather than host. - greg void SimTagIso15693(uint32_t parameter) { LED_A_ON(); LED_B_ON(); LED_C_OFF(); LED_D_OFF(); uint8_t *answer1 = (((uint8_t *)BigBuf) + 3660); // int answerLen1 = 0; // Blank arrays memset(answer1, 0, 100); // Setup SSC FpgaSetupSsc(); // Start from off (no field generated) FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); SpinDelay(200); SetAdcMuxFor(GPIO_MUXSEL_HIPKD); FpgaSetupSsc(); // Give the tags time to energize // FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR); // NO GOOD FOR SIM TAG!!!! SpinDelay(200); LED_A_OFF(); LED_B_OFF(); LED_C_ON(); LED_D_OFF(); int samples = 0; int tsamples = 0; int wait = 0; int elapsed = 0; answerLen1 = GetIso15693AnswerFromSniff(answer1, 100, &samples, &elapsed) ; if (answerLen1 >=1) // we should do a better check than this { // Build a suitable reponse to the reader INVENTORY cocmmand BuildInventoryResponse(); TransmitTo15693Reader(ToSend,ToSendMax, &tsamples, &wait); } Dbprintf("%d octets read from reader command: %x %x %x %x %x %x %x %x %x", answerLen1, answer1[0], answer1[1], answer1[2], answer1[3], answer1[4], answer1[5], answer1[6], answer1[7], answer1[8]); LED_A_OFF(); LED_B_OFF(); LED_C_OFF(); LED_D_OFF(); } // Since there is no standardized way of reading the AFI out of a tag, we will brute force it // (some manufactures offer a way to read the AFI, though) void BruteforceIso15693Afi(uint32_t speed) { uint8_t data[20]; uint8_t *recv=data; int datalen=0, recvlen=0; Iso15693InitReader(); // first without AFI // Tags should respond wihtout AFI and with AFI=0 even when AFI is active data[0]=ISO15_REQ_SUBCARRIER_SINGLE | ISO15_REQ_DATARATE_HIGH | ISO15_REQ_INVENTORY | ISO15_REQINV_SLOT1; data[1]=ISO15_CMD_INVENTORY; data[2]=0; // mask length datalen=AddCrc(data,3); recvlen=SendDataTag(data,datalen,0,speed,&recv); WDT_HIT(); if (recvlen>=12) { Dbprintf("NoAFI UID=%s",sprintUID(NULL,&recv[2])); } // now with AFI data[0]=ISO15_REQ_SUBCARRIER_SINGLE | ISO15_REQ_DATARATE_HIGH | ISO15_REQ_INVENTORY | ISO15_REQINV_AFI | ISO15_REQINV_SLOT1; data[1]=ISO15_CMD_INVENTORY; data[2]=0; // AFI data[3]=0; // mask length for (int i=0;i<256;i++) { data[2]=i & 0xFF; datalen=AddCrc(data,4); recvlen=SendDataTag(data,datalen,0,speed,&recv); WDT_HIT(); if (recvlen>=12) { Dbprintf("AFI=%i UID=%s",i,sprintUID(NULL,&recv[2])); } } Dbprintf("AFI Bruteforcing done."); } // Allows to directly send commands to the tag via the client void DirectTag15693Command(uint32_t datalen,uint32_t speed, uint32_t recv, uint8_t data[]) { int recvlen=0; uint8_t *recvbuf=(uint8_t *)BigBuf; // UsbCommand n; if (DEBUG) { Dbprintf("SEND"); Dbhexdump(datalen,data,true); } recvlen=SendDataTag(data,datalen,1,speed,(recv?&recvbuf:NULL)); if (recv) { // n.cmd=/* CMD_ISO_15693_COMMAND_DONE */ CMD_ACK; // n.arg[0]=recvlen>48?48:recvlen; // memcpy(n.d.asBytes, recvbuf, 48); LED_B_ON(); cmd_send(CMD_ACK,recvlen>48?48:recvlen,0,0,recvbuf,48); // UsbSendPacket((uint8_t *)&n, sizeof(n)); LED_B_OFF(); if (DEBUG) { Dbprintf("RECV"); DbdecodeIso15693Answer(recvlen,recvbuf); Dbhexdump(recvlen,recvbuf,true); } } } // -------------------------------------------------------------------- // -- Misc & deprecated functions // -------------------------------------------------------------------- /* // do not use; has a fix UID static void __attribute__((unused)) BuildSysInfoRequest(uint8_t *uid) { uint8_t cmd[12]; uint16_t crc; // If we set the Option_Flag in this request, the VICC will respond with the secuirty status of the block // followed by teh block data // one sub-carrier, inventory, 1 slot, fast rate cmd[0] = (1 << 5) | (1 << 1); // no SELECT bit // System Information command code cmd[1] = 0x2B; // UID may be optionally specified here // 64-bit UID cmd[2] = 0x32; cmd[3]= 0x4b; cmd[4] = 0x03; cmd[5] = 0x01; cmd[6] = 0x00; cmd[7] = 0x10; cmd[8] = 0x05; cmd[9]= 0xe0; // always e0 (not exactly unique) //Now the CRC crc = Crc(cmd, 10); // the crc needs to be calculated over 2 bytes cmd[10] = crc & 0xff; cmd[11] = crc >> 8; CodeIso15693AsReader(cmd, sizeof(cmd)); } // do not use; has a fix UID static void __attribute__((unused)) BuildReadMultiBlockRequest(uint8_t *uid) { uint8_t cmd[14]; uint16_t crc; // If we set the Option_Flag in this request, the VICC will respond with the secuirty status of the block // followed by teh block data // one sub-carrier, inventory, 1 slot, fast rate cmd[0] = (1 << 5) | (1 << 1); // no SELECT bit // READ Multi BLOCK command code cmd[1] = 0x23; // UID may be optionally specified here // 64-bit UID cmd[2] = 0x32; cmd[3]= 0x4b; cmd[4] = 0x03; cmd[5] = 0x01; cmd[6] = 0x00; cmd[7] = 0x10; cmd[8] = 0x05; cmd[9]= 0xe0; // always e0 (not exactly unique) // First Block number to read cmd[10] = 0x00; // Number of Blocks to read cmd[11] = 0x2f; // read quite a few //Now the CRC crc = Crc(cmd, 12); // the crc needs to be calculated over 2 bytes cmd[12] = crc & 0xff; cmd[13] = crc >> 8; CodeIso15693AsReader(cmd, sizeof(cmd)); } // do not use; has a fix UID static void __attribute__((unused)) BuildArbitraryRequest(uint8_t *uid,uint8_t CmdCode) { uint8_t cmd[14]; uint16_t crc; // If we set the Option_Flag in this request, the VICC will respond with the secuirty status of the block // followed by teh block data // one sub-carrier, inventory, 1 slot, fast rate cmd[0] = (1 << 5) | (1 << 1); // no SELECT bit // READ BLOCK command code cmd[1] = CmdCode; // UID may be optionally specified here // 64-bit UID cmd[2] = 0x32; cmd[3]= 0x4b; cmd[4] = 0x03; cmd[5] = 0x01; cmd[6] = 0x00; cmd[7] = 0x10; cmd[8] = 0x05; cmd[9]= 0xe0; // always e0 (not exactly unique) // Parameter cmd[10] = 0x00; cmd[11] = 0x0a; // cmd[12] = 0x00; // cmd[13] = 0x00; //Now the CRC crc = Crc(cmd, 12); // the crc needs to be calculated over 2 bytes cmd[12] = crc & 0xff; cmd[13] = crc >> 8; CodeIso15693AsReader(cmd, sizeof(cmd)); } // do not use; has a fix UID static void __attribute__((unused)) BuildArbitraryCustomRequest(uint8_t uid[], uint8_t CmdCode) { uint8_t cmd[14]; uint16_t crc; // If we set the Option_Flag in this request, the VICC will respond with the secuirty status of the block // followed by teh block data // one sub-carrier, inventory, 1 slot, fast rate cmd[0] = (1 << 5) | (1 << 1); // no SELECT bit // READ BLOCK command code cmd[1] = CmdCode; // UID may be optionally specified here // 64-bit UID cmd[2] = 0x32; cmd[3]= 0x4b; cmd[4] = 0x03; cmd[5] = 0x01; cmd[6] = 0x00; cmd[7] = 0x10; cmd[8] = 0x05; cmd[9]= 0xe0; // always e0 (not exactly unique) // Parameter cmd[10] = 0x05; // for custom codes this must be manufcturer code cmd[11] = 0x00; // cmd[12] = 0x00; // cmd[13] = 0x00; //Now the CRC crc = Crc(cmd, 12); // the crc needs to be calculated over 2 bytes cmd[12] = crc & 0xff; cmd[13] = crc >> 8; CodeIso15693AsReader(cmd, sizeof(cmd)); } */ ================================================ FILE: TamagotchiFriends/proxmark/armsrc/ldscript ================================================ /* ----------------------------------------------------------------------------- This code is licensed to you under the terms of the GNU GPL, version 2 or, at your option, any later version. See the LICENSE.txt file for the text of the license. ----------------------------------------------------------------------------- Linker script for the ARM binary ----------------------------------------------------------------------------- */ INCLUDE ../common/ldscript.common PHDRS { fpgaimage PT_LOAD FLAGS(4); text PT_LOAD; data PT_LOAD; bss PT_LOAD; } ENTRY(Vector) SECTIONS { .fpgaimage : { *(fpga_bit.data) } >fpgaimage :fpgaimage .start : { *(.startos) } >osimage :text .text : { *(.text) *(.text.*) *(.eh_frame) *(.glue_7) *(.glue_7t) } >osimage :text .rodata : { *(.rodata) *(.rodata.*) KEEP(*(.version_information)) } >osimage :text . = ALIGN(4); .data : { *(.data) *(.data.*) *(.ramfunc) . = ALIGN(4); } >ram AT>osimage :data __data_src_start__ = LOADADDR(.data); __data_start__ = ADDR(.data); __data_end__ = __data_start__ + SIZEOF(.data); .bss : { __bss_start__ = .; *(.bss) *(.bss.*) . = ALIGN(4); __bss_end__ = .; } >ram AT>ram :bss .commonarea (NOLOAD) : { *(.commonarea) } >commonarea :NONE } ================================================ FILE: TamagotchiFriends/proxmark/armsrc/legicrf.c ================================================ //----------------------------------------------------------------------------- // (c) 2009 Henryk Plötz // // This code is licensed to you under the terms of the GNU GPL, version 2 or, // at your option, any later version. See the LICENSE.txt file for the text of // the license. //----------------------------------------------------------------------------- // LEGIC RF simulation code //----------------------------------------------------------------------------- #include "proxmark3.h" #include "apps.h" #include "util.h" #include "string.h" #include "legicrf.h" #include "legic_prng.h" #include "crc.h" static struct legic_frame { int bits; uint32_t data; } current_frame; static enum { STATE_DISCON, STATE_IV, STATE_CON, } legic_state; static crc_t legic_crc; static int legic_read_count; static uint32_t legic_prng_bc; static uint32_t legic_prng_iv; static int legic_phase_drift; static int legic_frame_drift; static int legic_reqresp_drift; AT91PS_TC timer; AT91PS_TC prng_timer; static void setup_timer(void) { /* Set up Timer 1 to use for measuring time between pulses. Since we're bit-banging * this it won't be terribly accurate but should be good enough. */ AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1); timer = AT91C_BASE_TC1; timer->TC_CCR = AT91C_TC_CLKDIS; timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK; timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; /* * Set up Timer 2 to use for measuring time between frames in * tag simulation mode. Runs 4x faster as Timer 1 */ AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC2); prng_timer = AT91C_BASE_TC2; prng_timer->TC_CCR = AT91C_TC_CLKDIS; prng_timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV2_CLOCK; prng_timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; } /* At TIMER_CLOCK3 (MCK/32) */ #define RWD_TIME_1 150 /* RWD_TIME_PAUSE off, 80us on = 100us */ #define RWD_TIME_0 90 /* RWD_TIME_PAUSE off, 40us on = 60us */ #define RWD_TIME_PAUSE 30 /* 20us */ #define RWD_TIME_FUZZ 20 /* rather generous 13us, since the peak detector + hysteresis fuzz quite a bit */ #define TAG_TIME_BIT 150 /* 100us for every bit */ #define TAG_TIME_WAIT 490 /* time from RWD frame end to tag frame start, experimentally determined */ #define SIM_DIVISOR 586 /* prng_time/SIM_DIVISOR count prng needs to be forwared */ #define SIM_SHIFT 900 /* prng_time+SIM_SHIFT shift of delayed start */ #define SESSION_IV 0x55 #define OFFSET_LOG 1024 #define FUZZ_EQUAL(value, target, fuzz) ((value) > ((target)-(fuzz)) && (value) < ((target)+(fuzz))) /* Generate Keystream */ static uint32_t get_key_stream(int skip, int count) { uint32_t key=0; int i; /* Use int to enlarge timer tc to 32bit */ legic_prng_bc += prng_timer->TC_CV; prng_timer->TC_CCR = AT91C_TC_SWTRG; /* If skip == -1, forward prng time based */ if(skip == -1) { i = (legic_prng_bc+SIM_SHIFT)/SIM_DIVISOR; /* Calculate Cycles based on timer */ i -= legic_prng_count(); /* substract cycles of finished frames */ i -= count; /* substract current frame length, rewidn to bedinning */ legic_prng_forward(i); } else { legic_prng_forward(skip); } /* Write Time Data into LOG */ if(count == 6) { i = -1; } else { i = legic_read_count; } ((uint8_t*)BigBuf)[OFFSET_LOG+128+i] = legic_prng_count(); ((uint8_t*)BigBuf)[OFFSET_LOG+256+i*4] = (legic_prng_bc >> 0) & 0xff; ((uint8_t*)BigBuf)[OFFSET_LOG+256+i*4+1] = (legic_prng_bc >> 8) & 0xff; ((uint8_t*)BigBuf)[OFFSET_LOG+256+i*4+2] = (legic_prng_bc >>16) & 0xff; ((uint8_t*)BigBuf)[OFFSET_LOG+256+i*4+3] = (legic_prng_bc >>24) & 0xff; ((uint8_t*)BigBuf)[OFFSET_LOG+384+i] = count; /* Generate KeyStream */ for(i=0; iPIO_CODR = GPIO_SSC_DOUT; AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT; /* Use time to crypt frame */ if(crypt) { legic_prng_forward(2); /* TAG_TIME_WAIT -> shift by 2 */ int i; int key = 0; for(i=0; iTC_CV < (TAG_TIME_WAIT - 30)) ; int i; for(i=0; iTC_CV + TAG_TIME_BIT; int bit = response & 1; response = response >> 1; if(bit) { AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT; } else { AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT; } while(timer->TC_CV < nextbit) ; } AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT; } /* Send a frame in reader mode, the FPGA must have been set up by * LegicRfReader */ static void frame_send_rwd(uint32_t data, int bits) { /* Start clock */ timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; while(timer->TC_CV > 1) ; /* Wait till the clock has reset */ int i; for(i=0; iTC_CV; int pause_end = starttime + RWD_TIME_PAUSE, bit_end; int bit = data & 1; data = data >> 1; if(bit ^ legic_prng_get_bit()) { bit_end = starttime + RWD_TIME_1; } else { bit_end = starttime + RWD_TIME_0; } /* RWD_TIME_PAUSE time off, then some time on, so that the complete bit time is * RWD_TIME_x, where x is the bit to be transmitted */ AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT; while(timer->TC_CV < pause_end) ; AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT; legic_prng_forward(1); /* bit duration is longest. use this time to forward the lfsr */ while(timer->TC_CV < bit_end) ; } { /* One final pause to mark the end of the frame */ int pause_end = timer->TC_CV + RWD_TIME_PAUSE; AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT; while(timer->TC_CV < pause_end) ; AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT; } /* Reset the timer, to measure time until the start of the tag frame */ timer->TC_CCR = AT91C_TC_SWTRG; while(timer->TC_CV > 1) ; /* Wait till the clock has reset */ } /* Receive a frame from the card in reader emulation mode, the FPGA and * timer must have been set up by LegicRfReader and frame_send_rwd. * * The LEGIC RF protocol from card to reader does not include explicit * frame start/stop information or length information. The reader must * know beforehand how many bits it wants to receive. (Notably: a card * sending a stream of 0-bits is indistinguishable from no card present.) * * Receive methodology: There is a fancy correlator in hi_read_rx_xcorr, but * I'm not smart enough to use it. Instead I have patched hi_read_tx to output * the ADC signal with hysteresis on SSP_DIN. Bit-bang that signal and look * for edges. Count the edges in each bit interval. If they are approximately * 0 this was a 0-bit, if they are approximately equal to the number of edges * expected for a 212kHz subcarrier, this was a 1-bit. For timing we use the * timer that's still running from frame_send_rwd in order to get a synchronization * with the frame that we just sent. * * FIXME: Because we're relying on the hysteresis to just do the right thing * the range is severely reduced (and you'll probably also need a good antenna). * So this should be fixed some time in the future for a proper receiver. */ static void frame_receive_rwd(struct legic_frame * const f, int bits, int crypt) { uint32_t the_bit = 1; /* Use a bitmask to save on shifts */ uint32_t data=0; int i, old_level=0, edges=0; int next_bit_at = TAG_TIME_WAIT; if(bits > 32) { bits = 32; } AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN; AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN; /* we have some time now, precompute the cipher * since we cannot compute it on the fly while reading */ legic_prng_forward(2); if(crypt) { for(i=0; iTC_CV < next_bit_at) ; next_bit_at += TAG_TIME_BIT; for(i=0; iTC_CV < next_bit_at) { int level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN); if(level != old_level) edges++; old_level = level; } next_bit_at += TAG_TIME_BIT; if(edges > 20 && edges < 60) { /* expected are 42 edges */ data ^= the_bit; } the_bit <<= 1; } f->data = data; f->bits = bits; /* Reset the timer, to synchronize the next frame */ timer->TC_CCR = AT91C_TC_SWTRG; while(timer->TC_CV > 1) ; /* Wait till the clock has reset */ } static void frame_append_bit(struct legic_frame * const f, int bit) { if(f->bits >= 31) { return; /* Overflow, won't happen */ } f->data |= (bit<bits); f->bits++; } static void frame_clean(struct legic_frame * const f) { f->data = 0; f->bits = 0; } static uint32_t perform_setup_phase_rwd(int iv) { /* Switch on carrier and let the tag charge for 1ms */ AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT; SpinDelay(1); legic_prng_init(0); /* no keystream yet */ frame_send_rwd(iv, 7); legic_prng_init(iv); frame_clean(¤t_frame); frame_receive_rwd(¤t_frame, 6, 1); legic_prng_forward(1); /* we wait anyways */ while(timer->TC_CV < 387) ; /* ~ 258us */ frame_send_rwd(0x19, 6); return current_frame.data; } static void LegicCommonInit(void) { SetAdcMuxFor(GPIO_MUXSEL_HIPKD); FpgaSetupSsc(); FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX); /* Bitbang the transmitter */ AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT; AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT; setup_timer(); crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0); } static void switch_off_tag_rwd(void) { /* Switch off carrier, make sure tag is reset */ AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT; SpinDelay(10); WDT_HIT(); } /* calculate crc for a legic command */ static int LegicCRC(int byte_index, int value, int cmd_sz) { crc_clear(&legic_crc); crc_update(&legic_crc, 1, 1); /* CMD_READ */ crc_update(&legic_crc, byte_index, cmd_sz-1); crc_update(&legic_crc, value, 8); return crc_finish(&legic_crc); } int legic_read_byte(int byte_index, int cmd_sz) { int byte; legic_prng_forward(4); /* we wait anyways */ while(timer->TC_CV < 387) ; /* ~ 258us + 100us*delay */ frame_send_rwd(1 | (byte_index << 1), cmd_sz); frame_clean(¤t_frame); frame_receive_rwd(¤t_frame, 12, 1); byte = current_frame.data & 0xff; if( LegicCRC(byte_index, byte, cmd_sz) != (current_frame.data >> 8) ) { Dbprintf("!!! crc mismatch: expected %x but got %x !!!", LegicCRC(byte_index, current_frame.data & 0xff, cmd_sz), current_frame.data >> 8); return -1; } return byte; } /* legic_write_byte() is not included, however it's trivial to implement * and here are some hints on what remains to be done: * * * assemble a write_cmd_frame with crc and send it * * wait until the tag sends back an ACK ('1' bit unencrypted) * * forward the prng based on the timing */ int legic_write_byte(int byte, int addr, int addr_sz) { //do not write UID, CRC, DCF if(addr <= 0x06) { return 0; } //== send write command ============================== crc_clear(&legic_crc); crc_update(&legic_crc, 0, 1); /* CMD_WRITE */ crc_update(&legic_crc, addr, addr_sz); crc_update(&legic_crc, byte, 8); uint32_t crc = crc_finish(&legic_crc); uint32_t cmd = ((crc <<(addr_sz+1+8)) //CRC |(byte <<(addr_sz+1)) //Data |(addr <<1) //Address |(0x00 <<0)); //CMD = W uint32_t cmd_sz = addr_sz+1+8+4; //crc+data+cmd legic_prng_forward(2); /* we wait anyways */ while(timer->TC_CV < 387) ; /* ~ 258us */ frame_send_rwd(cmd, cmd_sz); //== wait for ack ==================================== int t, old_level=0, edges=0; int next_bit_at =0; while(timer->TC_CV < 387) ; /* ~ 258us */ for(t=0; t<80; t++) { edges = 0; next_bit_at += TAG_TIME_BIT; while(timer->TC_CV < next_bit_at) { int level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN); if(level != old_level) { edges++; } old_level = level; } if(edges > 20 && edges < 60) { /* expected are 42 edges */ int t = timer->TC_CV; int c = t/TAG_TIME_BIT; timer->TC_CCR = AT91C_TC_SWTRG; while(timer->TC_CV > 1) ; /* Wait till the clock has reset */ legic_prng_forward(c); return 0; } } timer->TC_CCR = AT91C_TC_SWTRG; while(timer->TC_CV > 1) ; /* Wait till the clock has reset */ return -1; } int LegicRfReader(int offset, int bytes) { int byte_index=0, cmd_sz=0, card_sz=0; LegicCommonInit(); memset(BigBuf, 0, 1024); DbpString("setting up legic card"); uint32_t tag_type = perform_setup_phase_rwd(SESSION_IV); switch_off_tag_rwd(); //we lose to mutch time with dprintf switch(tag_type) { case 0x1d: DbpString("MIM 256 card found, reading card ..."); cmd_sz = 9; card_sz = 256; break; case 0x3d: DbpString("MIM 1024 card found, reading card ..."); cmd_sz = 11; card_sz = 1024; break; default: Dbprintf("Unknown card format: %x",tag_type); return -1; } if(bytes == -1) { bytes = card_sz; } if(bytes+offset >= card_sz) { bytes = card_sz-offset; } perform_setup_phase_rwd(SESSION_IV); LED_B_ON(); while(byte_index < bytes) { int r = legic_read_byte(byte_index+offset, cmd_sz); if(r == -1 ||BUTTON_PRESS()) { DbpString("operation aborted"); switch_off_tag_rwd(); LED_B_OFF(); LED_C_OFF(); return -1; } ((uint8_t*)BigBuf)[byte_index] = r; WDT_HIT(); byte_index++; if(byte_index & 0x10) LED_C_ON(); else LED_C_OFF(); } LED_B_OFF(); LED_C_OFF(); switch_off_tag_rwd(); Dbprintf("Card read, use 'hf legic decode' or"); Dbprintf("'data hexsamples %d' to view results", (bytes+7) & ~7); return 0; } void LegicRfWriter(int bytes, int offset) { int byte_index=0, addr_sz=0; LegicCommonInit(); DbpString("setting up legic card"); uint32_t tag_type = perform_setup_phase_rwd(SESSION_IV); switch_off_tag_rwd(); switch(tag_type) { case 0x1d: if(offset+bytes > 0x100) { Dbprintf("Error: can not write to 0x%03.3x on MIM 256", offset+bytes); return; } addr_sz = 8; Dbprintf("MIM 256 card found, writing 0x%02.2x - 0x%02.2x ...", offset, offset+bytes); break; case 0x3d: if(offset+bytes > 0x400) { Dbprintf("Error: can not write to 0x%03.3x on MIM 1024", offset+bytes); return; } addr_sz = 10; Dbprintf("MIM 1024 card found, writing 0x%03.3x - 0x%03.3x ...", offset, offset+bytes); break; default: Dbprintf("No or unknown card found, aborting"); return; } LED_B_ON(); perform_setup_phase_rwd(SESSION_IV); legic_prng_forward(2); while(byte_index < bytes) { int r = legic_write_byte(((uint8_t*)BigBuf)[byte_index+offset], byte_index+offset, addr_sz); if((r != 0) || BUTTON_PRESS()) { Dbprintf("operation aborted @ 0x%03.3x", byte_index); switch_off_tag_rwd(); LED_B_OFF(); LED_C_OFF(); return; } WDT_HIT(); byte_index++; if(byte_index & 0x10) LED_C_ON(); else LED_C_OFF(); } LED_B_OFF(); LED_C_OFF(); DbpString("write successful"); } int timestamp; /* Handle (whether to respond) a frame in tag mode */ static void frame_handle_tag(struct legic_frame const * const f) { /* First Part of Handshake (IV) */ if(f->bits == 7) { if(f->data == SESSION_IV) { LED_C_ON(); prng_timer->TC_CCR = AT91C_TC_SWTRG; legic_prng_init(f->data); frame_send_tag(0x3d, 6, 1); /* 0x3d^0x26 = 0x1b */ legic_state = STATE_IV; legic_read_count = 0; legic_prng_bc = 0; legic_prng_iv = f->data; /* TIMEOUT */ timer->TC_CCR = AT91C_TC_SWTRG; while(timer->TC_CV > 1); while(timer->TC_CV < 280); return; } else if((prng_timer->TC_CV % 50) > 40) { legic_prng_init(f->data); frame_send_tag(0x3d, 6, 1); SpinDelay(20); return; } } /* 0x19==??? */ if(legic_state == STATE_IV) { if((f->bits == 6) && (f->data == (0x19 ^ get_key_stream(1, 6)))) { legic_state = STATE_CON; /* TIMEOUT */ timer->TC_CCR = AT91C_TC_SWTRG; while(timer->TC_CV > 1); while(timer->TC_CV < 200); return; } else { legic_state = STATE_DISCON; LED_C_OFF(); Dbprintf("0x19 - Frame: %03.3x", f->data); return; } } /* Read */ if(f->bits == 11) { if(legic_state == STATE_CON) { int key = get_key_stream(-1, 11); //legic_phase_drift, 11); int addr = f->data ^ key; addr = addr >> 1; int data = ((uint8_t*)BigBuf)[addr]; int hash = LegicCRC(addr, data, 11) << 8; ((uint8_t*)BigBuf)[OFFSET_LOG+legic_read_count] = (uint8_t)addr; legic_read_count++; //Dbprintf("Data:%03.3x, key:%03.3x, addr: %03.3x, read_c:%u", f->data, key, addr, read_c); legic_prng_forward(legic_reqresp_drift); frame_send_tag(hash | data, 12, 1); /* SHORT TIMEOUT */ timer->TC_CCR = AT91C_TC_SWTRG; while(timer->TC_CV > 1); legic_prng_forward(legic_frame_drift); while(timer->TC_CV < 180); return; } } /* Write */ if(f->bits == 23) { int key = get_key_stream(-1, 23); //legic_frame_drift, 23); int addr = f->data ^ key; addr = addr >> 1; addr = addr & 0x3ff; int data = f->data ^ key; data = data >> 11; data = data & 0xff; /* write command */ legic_state = STATE_DISCON; LED_C_OFF(); Dbprintf("write - addr: %x, data: %x", addr, data); return; } if(legic_state != STATE_DISCON) { Dbprintf("Unexpected: sz:%u, Data:%03.3x, State:%u, Count:%u", f->bits, f->data, legic_state, legic_read_count); int i; Dbprintf("IV: %03.3x", legic_prng_iv); for(i = 0; iPIO_ODR = GPIO_SSC_DIN; AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN; setup_timer(); crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0); int old_level = 0; int active = 0; legic_state = STATE_DISCON; LED_B_ON(); DbpString("Starting Legic emulator, press button to end"); while(!BUTTON_PRESS()) { int level = !!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN); int time = timer->TC_CV; if(level != old_level) { if(level == 1) { timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; if(FUZZ_EQUAL(time, RWD_TIME_1, RWD_TIME_FUZZ)) { /* 1 bit */ emit(1); active = 1; LED_A_ON(); } else if(FUZZ_EQUAL(time, RWD_TIME_0, RWD_TIME_FUZZ)) { /* 0 bit */ emit(0); active = 1; LED_A_ON(); } else if(active) { /* invalid */ emit(-1); active = 0; LED_A_OFF(); } } } if(time >= (RWD_TIME_1+RWD_TIME_FUZZ) && active) { /* Frame end */ emit(-1); active = 0; LED_A_OFF(); } if(time >= (20*RWD_TIME_1) && (timer->TC_SR & AT91C_TC_CLKSTA)) { timer->TC_CCR = AT91C_TC_CLKDIS; } old_level = level; WDT_HIT(); } DbpString("Stopped"); LED_B_OFF(); LED_A_OFF(); LED_C_OFF(); } ================================================ FILE: TamagotchiFriends/proxmark/armsrc/legicrf.h ================================================ //----------------------------------------------------------------------------- // (c) 2009 Henryk Plötz // // This code is licensed to you under the terms of the GNU GPL, version 2 or, // at your option, any later version. See the LICENSE.txt file for the text of // the license. //----------------------------------------------------------------------------- // LEGIC RF emulation public interface //----------------------------------------------------------------------------- #ifndef __LEGICRF_H #define __LEGICRF_H extern void LegicRfSimulate(int phase, int frame, int reqresp); extern int LegicRfReader(int bytes, int offset); extern void LegicRfWriter(int bytes, int offset); #endif /* __LEGICRF_H */ ================================================ FILE: TamagotchiFriends/proxmark/armsrc/lfops.c ================================================ //----------------------------------------------------------------------------- // This code is licensed to you under the terms of the GNU GPL, version 2 or, // at your option, any later version. See the LICENSE.txt file for the text of // the license. //----------------------------------------------------------------------------- // Miscellaneous routines for low frequency tag operations. // Tags supported here so far are Texas Instruments (TI), HID // Also routines for raw mode reading/simulating of LF waveform //----------------------------------------------------------------------------- #include "proxmark3.h" #include "apps.h" #include "util.h" #include "hitag2.h" #include "crc16.h" #include "string.h" volatile unsigned long timer0_millis = 0; void AcquireRawAdcSamples125k(int at134khz) { if (at134khz) FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz else FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 94); //125Khz AcquireTiType(); } // split into two routines so we can avoid timing issues after sending commands // void DoAcquisition125k(void) { uint8_t *dest = (uint8_t *)BigBuf; int n = sizeof(BigBuf); int i; memset(dest, 0, n); i = 0; for(;;) { if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) { AT91C_BASE_SSC->SSC_THR = 0x43; LED_D_ON(); } if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) { dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR; i++; LED_D_OFF(); if (i >= n) break; } } Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...", dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]); } void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command) { int at134khz; /* Make sure the tag is reset */ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); SpinDelay(2500); // see if 'h' was specified if (command[strlen((char *) command) - 1] == 'h') at134khz = TRUE; else at134khz = FALSE; if (at134khz) FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz else FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz ////FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); // Give it a bit of time for the resonant antenna to settle. SpinDelay(50); // And a little more time for the tag to fully power up SpinDelay(2000); // Now set up the SSC to get the ADC samples that are now streaming at us. FpgaSetupSsc(); // now modulate the reader field while(*command != '\0' && *command != ' ') { FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); LED_D_OFF(); SpinDelayUs(delay_off); if (at134khz) FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz else FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz ////FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); LED_D_ON(); if(*(command++) == '0') SpinDelayUs(period_0); else SpinDelayUs(period_1); } FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); LED_D_OFF(); SpinDelayUs(delay_off); if (at134khz) FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz else FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz ////FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); // now do the read DoAcquisition125k(); } /* blank r/w tag data stream ...0000000000000000 01111111 1010101010101010101010101010101010101010101010101010101010101010 0011010010100001 01111111 101010101010101[0]000... [5555fe852c5555555555555555fe0000] */ void ReadTItag(void) { // some hardcoded initial params // when we read a TI tag we sample the zerocross line at 2Mhz // TI tags modulate a 1 as 16 cycles of 123.2Khz // TI tags modulate a 0 as 16 cycles of 134.2Khz #define FSAMPLE 2000000 #define FREQLO 123200 #define FREQHI 134200 signed char *dest = (signed char *)BigBuf; int n = sizeof(BigBuf); // int *dest = GraphBuffer; // int n = GraphTraceLen; // 128 bit shift register [shift3:shift2:shift1:shift0] uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0; int i, cycles=0, samples=0; // how many sample points fit in 16 cycles of each frequency uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI; // when to tell if we're close enough to one freq or another uint32_t threshold = (sampleslo - sampleshi + 1)>>1; // TI tags charge at 134.2Khz FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 94); //134.8Khz // Place FPGA in passthrough mode, in this mode the CROSS_LO line // connects to SSP_DIN and the SSP_DOUT logic level controls // whether we're modulating the antenna (high) // or listening to the antenna (low) FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU); // get TI tag data into the buffer AcquireTiType(); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); for (i=0; i0) ) { cycles++; // after 16 cycles, measure the frequency if (cycles>15) { cycles=0; samples=i-samples; // number of samples in these 16 cycles // TI bits are coming to us lsb first so shift them // right through our 128 bit right shift register shift0 = (shift0>>1) | (shift1 << 31); shift1 = (shift1>>1) | (shift2 << 31); shift2 = (shift2>>1) | (shift3 << 31); shift3 >>= 1; // check if the cycles fall close to the number // expected for either the low or high frequency if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) { // low frequency represents a 1 shift3 |= (1<<31); } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) { // high frequency represents a 0 } else { // probably detected a gay waveform or noise // use this as gaydar or discard shift register and start again shift3 = shift2 = shift1 = shift0 = 0; } samples = i; // for each bit we receive, test if we've detected a valid tag // if we see 17 zeroes followed by 6 ones, we might have a tag // remember the bits are backwards if ( ((shift0 & 0x7fffff) == 0x7e0000) ) { // if start and end bytes match, we have a tag so break out of the loop if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) { cycles = 0xF0B; //use this as a flag (ugly but whatever) break; } } } } } // if flag is set we have a tag if (cycles!=0xF0B) { DbpString("Info: No valid tag detected."); } else { // put 64 bit data into shift1 and shift0 shift0 = (shift0>>24) | (shift1 << 8); shift1 = (shift1>>24) | (shift2 << 8); // align 16 bit crc into lower half of shift2 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff; // if r/w tag, check ident match if ( shift3&(1<<15) ) { DbpString("Info: TI tag is rewriteable"); // only 15 bits compare, last bit of ident is not valid if ( ((shift3>>16)^shift0)&0x7fff ) { DbpString("Error: Ident mismatch!"); } else { DbpString("Info: TI tag ident is valid"); } } else { DbpString("Info: TI tag is readonly"); } // WARNING the order of the bytes in which we calc crc below needs checking // i'm 99% sure the crc algorithm is correct, but it may need to eat the // bytes in reverse or something // calculate CRC uint32_t crc=0; crc = update_crc16(crc, (shift0)&0xff); crc = update_crc16(crc, (shift0>>8)&0xff); crc = update_crc16(crc, (shift0>>16)&0xff); crc = update_crc16(crc, (shift0>>24)&0xff); crc = update_crc16(crc, (shift1)&0xff); crc = update_crc16(crc, (shift1>>8)&0xff); crc = update_crc16(crc, (shift1>>16)&0xff); crc = update_crc16(crc, (shift1>>24)&0xff); Dbprintf("Info: Tag data: %x%08x, crc=%x", (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF); if (crc != (shift2&0xffff)) { Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc); } else { DbpString("Info: CRC is good"); } } } void WriteTIbyte(uint8_t b) { int i = 0; //prolog //SpinDelayUs(1000); // modulate antenna HIGH(GPIO_SSC_DOUT); SpinDelayUs(540); LOW(GPIO_SSC_DOUT); // modulate 8 bits out to the antenna for (i=7; i>=0; i--) { if (b&(1<PIO_PDR = GPIO_SSC_DIN; AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN; // steal this pin from the SSP and use it to control the modulation AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT; AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST; AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN; // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long // 48/2 = 24 MHz clock must be divided by 12 AT91C_BASE_SSC->SSC_CMR = 12; AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0); AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF; AT91C_BASE_SSC->SSC_TCMR = 0; AT91C_BASE_SSC->SSC_TFMR = 0; // modulate antenna //HIGH(GPIO_SSC_DOUT); // Charge TI tag for 50ms. SpinDelay(50); // stop modulating antenna and listen //LED_A_ON(); LOW(GPIO_SSC_DOUT); //ti = GetTickCount(); //SpinDelay(1000); //ti = GetTickCount() - ti; //Dbprintf("timer(1s): %d t=%d", ti, GetTickCount()); //LED_A_OFF(); LED_D_ON(); i = 0; ti = GetTickCount(); for(;;) { if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) { BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer i++; if(i >= 40000) break; } WDT_HIT(); } ti = GetTickCount() - ti; Dbprintf("timer(1s): %d t=%d", ti, GetTickCount()); LED_D_OFF(); // return stolen pin to SSP AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT; AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT; } // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc // if crc provided, it will be written with the data verbatim (even if bogus) // if not provided a valid crc will be computed from the data and written. void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc) { int i, sum; sum = 0x23 + idhi + idlo; //if(crc == 0) { // crc = update_crc16(crc, (idlo)&0xff); // crc = update_crc16(crc, (idlo>>8)&0xff); // crc = update_crc16(crc, (idlo>>16)&0xff); // crc = update_crc16(crc, (idlo>>24)&0xff); // crc = update_crc16(crc, (idhi)&0xff); // crc = update_crc16(crc, (idhi>>8)&0xff); // crc = update_crc16(crc, (idhi>>16)&0xff); // crc = update_crc16(crc, (idhi>>24)&0xff); //} //Dbprintf("Writing to tag: %x%08x, crc=%x", // (unsigned int) idhi, (unsigned int) idlo, crc); // TI tags charge at 134.2Khz //88 is 125 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 94); //134.8Khz // Place FPGA in passthrough mode, in this mode the CROSS_LO line // connects to SSP_DIN and the SSP_DOUT logic level controls // whether we're modulating the antenna (high) // or listening to the antenna (low) FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU); LED_A_ON(); // steal this pin from the SSP and use it to control the modulation AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT; AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; // writing algorithm: // a high bit consists of a field off for 1ms and field on for 1ms // a low bit consists of a field off for 0.3ms and field on for 1.7ms // initiate a charge time of 50ms (field on) then immediately start writing bits // start by writing 0xBB (keyword) and 0xEB (password) // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer) // finally end with 0x0300 (write frame) // all data is sent lsb firts // finish with 15ms programming time // modulate antenna //HIGH(GPIO_SSC_DOUT); //SpinDelay(10000); // charge time for(i = 0; i < 10; i++){ WriteTIbyte(0xf0); WriteTIbyte(0x01); WriteTIbyte( 0x0f ); WriteTIbyte(0x01); WriteTIbyte(0x01); WriteTIbyte(0x0F); WriteTIbyte(0x0B); WriteTIbyte( 0x00 ); WriteTIbyte(0x06); WriteTIbyte(0x80); WriteTIbyte(0x02); WriteTIbyte(0x08); WriteTIbyte( 0x01 ); WriteTIbyte(0x08); WriteTIbyte(0x1a); WriteTIbyte(0x1a); WriteTIbyte(0x1a); WriteTIbyte( 0x1a ); WriteTIbyte( 0x2d ); //LOW(GPIO_SSC_DOUT); SpinDelay(100); WriteTIbyte(0xf0); WriteTIbyte(0x07); WriteTIbyte( 0x05 ); WriteTIbyte(0x01); WriteTIbyte(0x07); WriteTIbyte(0x0f); WriteTIbyte(idhi); WriteTIbyte( idlo ); WriteTIbyte( sum & 0xFF ); SpinDelay(1000); } LED_A_OFF(); // get TI tag data into the buffer //AcquireTiType(); //FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); DbpString("Done"); } void SimulateTagLowFrequency(int period, int gap, int ledcontrol) { int i; uint8_t *tab = (uint8_t *)BigBuf; FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT); AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK; AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK; #define SHORT_COIL() LOW(GPIO_SSC_DOUT) #define OPEN_COIL() HIGH(GPIO_SSC_DOUT) i = 0; for(;;) { while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) { if(BUTTON_PRESS()) { DbpString("Stopped"); return; } WDT_HIT(); } if (ledcontrol) LED_D_ON(); if(tab[i]) OPEN_COIL(); else SHORT_COIL(); if (ledcontrol) LED_D_OFF(); while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) { if(BUTTON_PRESS()) { DbpString("Stopped"); return; } WDT_HIT(); } i++; if(i == period) { i = 0; if (gap) { SHORT_COIL(); SpinDelayUs(gap); } } } } #define DEBUG_FRAME_CONTENTS 1 void SimulateTagLowFrequencyBidir(int divisor, int t0) { } // compose fc/8 fc/10 waveform static void fc(int c, int *n) { uint8_t *dest = (uint8_t *)BigBuf; int idx; // for when we want an fc8 pattern every 4 logical bits if(c==0) { dest[((*n)++)]=1; dest[((*n)++)]=1; dest[((*n)++)]=0; dest[((*n)++)]=0; dest[((*n)++)]=0; dest[((*n)++)]=0; dest[((*n)++)]=0; dest[((*n)++)]=0; } // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples if(c==8) { for (idx=0; idx<6; idx++) { dest[((*n)++)]=1; dest[((*n)++)]=1; dest[((*n)++)]=0; dest[((*n)++)]=0; dest[((*n)++)]=0; dest[((*n)++)]=0; dest[((*n)++)]=0; dest[((*n)++)]=0; } } // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples if(c==10) { for (idx=0; idx<5; idx++) { dest[((*n)++)]=1; dest[((*n)++)]=1; dest[((*n)++)]=1; dest[((*n)++)]=0; dest[((*n)++)]=0; dest[((*n)++)]=0; dest[((*n)++)]=0; dest[((*n)++)]=0; dest[((*n)++)]=0; dest[((*n)++)]=0; } } } // prepare a waveform pattern in the buffer based on the ID given then // simulate a HID tag until the button is pressed void CmdHIDsimTAG(int hi, int lo, int ledcontrol) { int n=0, i=0; /* HID tag bitstream format The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits A 1 bit is represented as 6 fc8 and 5 fc10 patterns A 0 bit is represented as 5 fc10 and 6 fc8 patterns A fc8 is inserted before every 4 bits A special start of frame pattern is used consisting a0b0 where a and b are neither 0 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10) */ if (hi>0xFFF) { DbpString("Tags can only have 44 bits."); return; } fc(0,&n); // special start of frame marker containing invalid bit sequences fc(8, &n); fc(8, &n); // invalid fc(8, &n); fc(10, &n); // logical 0 fc(10, &n); fc(10, &n); // invalid fc(8, &n); fc(10, &n); // logical 0 WDT_HIT(); // manchester encode bits 43 to 32 for (i=11; i>=0; i--) { if ((i%4)==3) fc(0,&n); if ((hi>>i)&1) { fc(10, &n); fc(8, &n); // low-high transition } else { fc(8, &n); fc(10, &n); // high-low transition } } WDT_HIT(); // manchester encode bits 31 to 0 for (i=31; i>=0; i--) { if ((i%4)==3) fc(0,&n); if ((lo>>i)&1) { fc(10, &n); fc(8, &n); // low-high transition } else { fc(8, &n); fc(10, &n); // high-low transition } } if (ledcontrol) LED_A_ON(); SimulateTagLowFrequency(n, 0, ledcontrol); if (ledcontrol) LED_A_OFF(); } // loop to capture raw HID waveform then FSK demodulate the TAG ID from it void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol) { uint8_t *dest = (uint8_t *)BigBuf; int m=0, n=0, i=0, idx=0, found=0, lastval=0; uint32_t hi2=0, hi=0, lo=0; FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); // Connect the A/D to the peak-detected low-frequency path. SetAdcMuxFor(GPIO_MUXSEL_LOPKD); // Give it a bit of time for the resonant antenna to settle. SpinDelay(50); // Now set up the SSC to get the ADC samples that are now streaming at us. FpgaSetupSsc(); for(;;) { WDT_HIT(); if (ledcontrol) LED_A_ON(); if(BUTTON_PRESS()) { DbpString("Stopped"); if (ledcontrol) LED_A_OFF(); return; } i = 0; m = sizeof(BigBuf); memset(dest,128,m); for(;;) { if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { AT91C_BASE_SSC->SSC_THR = 0x43; if (ledcontrol) LED_D_ON(); } if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR; // we don't care about actual value, only if it's more or less than a // threshold essentially we capture zero crossings for later analysis if(dest[i] < 127) dest[i] = 0; else dest[i] = 1; i++; if (ledcontrol) LED_D_OFF(); if(i >= m) { break; } } } // FSK demodulator // sync to first lo-hi transition for( idx=1; idx>1) & 0xFFFF); } else { Dbprintf("TAG ID: %x%08x (%d)", (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); } /* if we're only looking for one tag */ if (findone) { *high = hi; *low = lo; return; } hi2=0; hi=0; lo=0; found=0; } } if (found) { if (dest[idx] && (!dest[idx+1]) ) { hi2=(hi2<<1)|(hi>>31); hi=(hi<<1)|(lo>>31); lo=(lo<<1)|0; } else if ( (!dest[idx]) && dest[idx+1]) { hi2=(hi2<<1)|(hi>>31); hi=(hi<<1)|(lo>>31); lo=(lo<<1)|1; } else { found=0; hi2=0; hi=0; lo=0; } idx++; } if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) ) { found=1; idx+=6; if (found && (hi|lo)) { if (hi2 != 0){ Dbprintf("TAG ID: %x%08x%08x (%d)", (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); } else { Dbprintf("TAG ID: %x%08x (%d)", (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); } /* if we're only looking for one tag */ if (findone) { *high = hi; *low = lo; return; } hi2=0; hi=0; lo=0; found=0; } } } WDT_HIT(); } } /*------------------------------ * T5555/T5557/T5567 routines *------------------------------ */ /* T55x7 configuration register definitions */ #define T55x7_POR_DELAY 0x00000001 #define T55x7_ST_TERMINATOR 0x00000008 #define T55x7_PWD 0x00000010 #define T55x7_MAXBLOCK_SHIFT 5 #define T55x7_AOR 0x00000200 #define T55x7_PSKCF_RF_2 0 #define T55x7_PSKCF_RF_4 0x00000400 #define T55x7_PSKCF_RF_8 0x00000800 #define T55x7_MODULATION_DIRECT 0 #define T55x7_MODULATION_PSK1 0x00001000 #define T55x7_MODULATION_PSK2 0x00002000 #define T55x7_MODULATION_PSK3 0x00003000 #define T55x7_MODULATION_FSK1 0x00004000 #define T55x7_MODULATION_FSK2 0x00005000 #define T55x7_MODULATION_FSK1a 0x00006000 #define T55x7_MODULATION_FSK2a 0x00007000 #define T55x7_MODULATION_MANCHESTER 0x00008000 #define T55x7_MODULATION_BIPHASE 0x00010000 #define T55x7_BITRATE_RF_8 0 #define T55x7_BITRATE_RF_16 0x00040000 #define T55x7_BITRATE_RF_32 0x00080000 #define T55x7_BITRATE_RF_40 0x000C0000 #define T55x7_BITRATE_RF_50 0x00100000 #define T55x7_BITRATE_RF_64 0x00140000 #define T55x7_BITRATE_RF_100 0x00180000 #define T55x7_BITRATE_RF_128 0x001C0000 /* T5555 (Q5) configuration register definitions */ #define T5555_ST_TERMINATOR 0x00000001 #define T5555_MAXBLOCK_SHIFT 0x00000001 #define T5555_MODULATION_MANCHESTER 0 #define T5555_MODULATION_PSK1 0x00000010 #define T5555_MODULATION_PSK2 0x00000020 #define T5555_MODULATION_PSK3 0x00000030 #define T5555_MODULATION_FSK1 0x00000040 #define T5555_MODULATION_FSK2 0x00000050 #define T5555_MODULATION_BIPHASE 0x00000060 #define T5555_MODULATION_DIRECT 0x00000070 #define T5555_INVERT_OUTPUT 0x00000080 #define T5555_PSK_RF_2 0 #define T5555_PSK_RF_4 0x00000100 #define T5555_PSK_RF_8 0x00000200 #define T5555_USE_PWD 0x00000400 #define T5555_USE_AOR 0x00000800 #define T5555_BITRATE_SHIFT 12 #define T5555_FAST_WRITE 0x00004000 #define T5555_PAGE_SELECT 0x00008000 /* * Relevant times in microsecond * To compensate antenna falling times shorten the write times * and enlarge the gap ones. */ #define START_GAP 250 #define WRITE_GAP 160 #define WRITE_0 144 // 192 #define WRITE_1 400 // 432 for T55x7; 448 for E5550 // Write one bit to card void T55xxWriteBit(int bit) { FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); if (bit == 0) SpinDelayUs(WRITE_0); else SpinDelayUs(WRITE_1); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); SpinDelayUs(WRITE_GAP); } // Write one card block in page 0, no lock void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode) { unsigned int i; FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); // Give it a bit of time for the resonant antenna to settle. // And for the tag to fully power up SpinDelay(150); // Now start writting FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); SpinDelayUs(START_GAP); // Opcode T55xxWriteBit(1); T55xxWriteBit(0); //Page 0 if (PwdMode == 1){ // Pwd for (i = 0x80000000; i != 0; i >>= 1) T55xxWriteBit(Pwd & i); } // Lock bit T55xxWriteBit(0); // Data for (i = 0x80000000; i != 0; i >>= 1) T55xxWriteBit(Data & i); // Block for (i = 0x04; i != 0; i >>= 1) T55xxWriteBit(Block & i); // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550, // so wait a little more) FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); SpinDelay(20); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); } // Read one card block in page 0 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode) { uint8_t *dest = (uint8_t *)BigBuf; int m=0, i=0; m = sizeof(BigBuf); // Clear destination buffer before sending the command memset(dest, 128, m); // Connect the A/D to the peak-detected low-frequency path. SetAdcMuxFor(GPIO_MUXSEL_LOPKD); // Now set up the SSC to get the ADC samples that are now streaming at us. FpgaSetupSsc(); LED_D_ON(); FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); // Give it a bit of time for the resonant antenna to settle. // And for the tag to fully power up SpinDelay(150); // Now start writting FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); SpinDelayUs(START_GAP); // Opcode T55xxWriteBit(1); T55xxWriteBit(0); //Page 0 if (PwdMode == 1){ // Pwd for (i = 0x80000000; i != 0; i >>= 1) T55xxWriteBit(Pwd & i); } // Lock bit T55xxWriteBit(0); // Block for (i = 0x04; i != 0; i >>= 1) T55xxWriteBit(Block & i); // Turn field on to read the response FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); // Now do the acquisition i = 0; for(;;) { if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) { AT91C_BASE_SSC->SSC_THR = 0x43; } if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) { dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR; // we don't care about actual value, only if it's more or less than a // threshold essentially we capture zero crossings for later analysis // if(dest[i] < 127) dest[i] = 0; else dest[i] = 1; i++; if (i >= m) break; } } FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off LED_D_OFF(); DbpString("DONE!"); } // Read card traceability data (page 1) void T55xxReadTrace(void){ uint8_t *dest = (uint8_t *)BigBuf; int m=0, i=0; m = sizeof(BigBuf); // Clear destination buffer before sending the command memset(dest, 128, m); // Connect the A/D to the peak-detected low-frequency path. SetAdcMuxFor(GPIO_MUXSEL_LOPKD); // Now set up the SSC to get the ADC samples that are now streaming at us. FpgaSetupSsc(); LED_D_ON(); FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); // Give it a bit of time for the resonant antenna to settle. // And for the tag to fully power up SpinDelay(150); // Now start writting FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); SpinDelayUs(START_GAP); // Opcode T55xxWriteBit(1); T55xxWriteBit(1); //Page 1 // Turn field on to read the response FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); // Now do the acquisition i = 0; for(;;) { if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) { AT91C_BASE_SSC->SSC_THR = 0x43; } if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) { dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR; i++; if (i >= m) break; } } FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off LED_D_OFF(); DbpString("DONE!"); } /*-------------- Cloning routines -----------*/ // Copy HID id to card and setup block 0 config void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) { int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format int last_block = 0; if (longFMT){ // Ensure no more than 84 bits supplied if (hi2>0xFFFFF) { DbpString("Tags can only have 84 bits."); return; } // Build the 6 data blocks for supplied 84bit ID last_block = 6; data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded) for (int i=0;i<4;i++) { if (hi2 & (1<<(19-i))) data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10 else data1 |= (1<<((3-i)*2)); // 0 -> 01 } data2 = 0; for (int i=0;i<16;i++) { if (hi2 & (1<<(15-i))) data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10 else data2 |= (1<<((15-i)*2)); // 0 -> 01 } data3 = 0; for (int i=0;i<16;i++) { if (hi & (1<<(31-i))) data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10 else data3 |= (1<<((15-i)*2)); // 0 -> 01 } data4 = 0; for (int i=0;i<16;i++) { if (hi & (1<<(15-i))) data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10 else data4 |= (1<<((15-i)*2)); // 0 -> 01 } data5 = 0; for (int i=0;i<16;i++) { if (lo & (1<<(31-i))) data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10 else data5 |= (1<<((15-i)*2)); // 0 -> 01 } data6 = 0; for (int i=0;i<16;i++) { if (lo & (1<<(15-i))) data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10 else data6 |= (1<<((15-i)*2)); // 0 -> 01 } } else { // Ensure no more than 44 bits supplied if (hi>0xFFF) { DbpString("Tags can only have 44 bits."); return; } // Build the 3 data blocks for supplied 44bit ID last_block = 3; data1 = 0x1D000000; // load preamble for (int i=0;i<12;i++) { if (hi & (1<<(11-i))) data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10 else data1 |= (1<<((11-i)*2)); // 0 -> 01 } data2 = 0; for (int i=0;i<16;i++) { if (lo & (1<<(31-i))) data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10 else data2 |= (1<<((15-i)*2)); // 0 -> 01 } data3 = 0; for (int i=0;i<16;i++) { if (lo & (1<<(15-i))) data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10 else data3 |= (1<<((15-i)*2)); // 0 -> 01 } } LED_D_ON(); // Program the data blocks for supplied ID // and the block 0 for HID format T55xxWriteBlock(data1,1,0,0); T55xxWriteBlock(data2,2,0,0); T55xxWriteBlock(data3,3,0,0); if (longFMT) { // if long format there are 6 blocks T55xxWriteBlock(data4,4,0,0); T55xxWriteBlock(data5,5,0,0); T55xxWriteBlock(data6,6,0,0); } // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long) T55xxWriteBlock(T55x7_BITRATE_RF_50 | T55x7_MODULATION_FSK2a | last_block << T55x7_MAXBLOCK_SHIFT, 0,0,0); LED_D_OFF(); DbpString("DONE!"); } // Define 9bit header for EM410x tags #define EM410X_HEADER 0x1FF #define EM410X_ID_LENGTH 40 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo) { int i, id_bit; uint64_t id = EM410X_HEADER; uint64_t rev_id = 0; // reversed ID int c_parity[4]; // column parity int r_parity = 0; // row parity uint32_t clock = 0; // Reverse ID bits given as parameter (for simpler operations) for (i = 0; i < EM410X_ID_LENGTH; ++i) { if (i < 32) { rev_id = (rev_id << 1) | (id_lo & 1); id_lo >>= 1; } else { rev_id = (rev_id << 1) | (id_hi & 1); id_hi >>= 1; } } for (i = 0; i < EM410X_ID_LENGTH; ++i) { id_bit = rev_id & 1; if (i % 4 == 0) { // Don't write row parity bit at start of parsing if (i) id = (id << 1) | r_parity; // Start counting parity for new row r_parity = id_bit; } else { // Count row parity r_parity ^= id_bit; } // First elements in column? if (i < 4) // Fill out first elements c_parity[i] = id_bit; else // Count column parity c_parity[i % 4] ^= id_bit; // Insert ID bit id = (id << 1) | id_bit; rev_id >>= 1; } // Insert parity bit of last row id = (id << 1) | r_parity; // Fill out column parity at the end of tag for (i = 0; i < 4; ++i) id = (id << 1) | c_parity[i]; // Add stop bit id <<= 1; Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555"); LED_D_ON(); // Write EM410x ID T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0); T55xxWriteBlock((uint32_t)id, 2, 0, 0); // Config for EM410x (RF/64, Manchester, Maxblock=2) if (card) { // Clock rate is stored in bits 8-15 of the card value clock = (card & 0xFF00) >> 8; Dbprintf("Clock rate: %d", clock); switch (clock) { case 32: clock = T55x7_BITRATE_RF_32; break; case 16: clock = T55x7_BITRATE_RF_16; break; case 0: // A value of 0 is assumed to be 64 for backwards-compatibility // Fall through... case 64: clock = T55x7_BITRATE_RF_64; break; default: Dbprintf("Invalid clock rate: %d", clock); return; } // Writing configuration for T55x7 tag T55xxWriteBlock(clock | T55x7_MODULATION_MANCHESTER | 2 << T55x7_MAXBLOCK_SHIFT, 0, 0, 0); } else // Writing configuration for T5555(Q5) tag T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT | T5555_MODULATION_MANCHESTER | 2 << T5555_MAXBLOCK_SHIFT, 0, 0, 0); LED_D_OFF(); Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555", (uint32_t)(id >> 32), (uint32_t)id); } // Clone Indala 64-bit tag by UID to T55x7 void CopyIndala64toT55x7(int hi, int lo) { //Program the 2 data blocks for supplied 64bit UID // and the block 0 for Indala64 format T55xxWriteBlock(hi,1,0,0); T55xxWriteBlock(lo,2,0,0); //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2) T55xxWriteBlock(T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | 2 << T55x7_MAXBLOCK_SHIFT, 0, 0, 0); //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data) // T5567WriteBlock(0x603E1042,0); DbpString("DONE!"); } void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7) { //Program the 7 data blocks for supplied 224bit UID // and the block 0 for Indala224 format T55xxWriteBlock(uid1,1,0,0); T55xxWriteBlock(uid2,2,0,0); T55xxWriteBlock(uid3,3,0,0); T55xxWriteBlock(uid4,4,0,0); T55xxWriteBlock(uid5,5,0,0); T55xxWriteBlock(uid6,6,0,0); T55xxWriteBlock(uid7,7,0,0); //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7) T55xxWriteBlock(T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | 7 << T55x7_MAXBLOCK_SHIFT, 0,0,0); //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data) // T5567WriteBlock(0x603E10E2,0); DbpString("DONE!"); } #define abs(x) ( ((x)<0) ? -(x) : (x) ) #define max(x,y) ( x GraphBuffer[0]) { while(i < GraphTraceLen) { if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax) break; i++; } dir = 0; } else { while(i < GraphTraceLen) { if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin) break; i++; } dir = 1; } lastval = i++; half_switch = 0; pmc = 0; block_done = 0; for (bitidx = 0; i < GraphTraceLen; i++) { if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin)) { lc = i - lastval; lastval = i; // Switch depending on lc length: // Tolerance is 1/8 of clock rate (arbitrary) if (abs(lc-clock/4) < tolerance) { // 16T0 if((i - pmc) == lc) { /* 16T0 was previous one */ /* It's a PMC ! */ i += (128+127+16+32+33+16)-1; lastval = i; pmc = 0; block_done = 1; } else { pmc = i; } } else if (abs(lc-clock/2) < tolerance) { // 32TO if((i - pmc) == lc) { /* 16T0 was previous one */ /* It's a PMC ! */ i += (128+127+16+32+33)-1; lastval = i; pmc = 0; block_done = 1; } else if(half_switch == 1) { BitStream[bitidx++] = 0; half_switch = 0; } else half_switch++; } else if (abs(lc-clock) < tolerance) { // 64TO BitStream[bitidx++] = 1; } else { // Error warnings++; if (warnings > 10) { Dbprintf("Error: too many detection errors, aborting."); return 0; } } if(block_done == 1) { if(bitidx == 128) { for(j=0; j<16; j++) { Blocks[num_blocks][j] = 128*BitStream[j*8+7]+ 64*BitStream[j*8+6]+ 32*BitStream[j*8+5]+ 16*BitStream[j*8+4]+ 8*BitStream[j*8+3]+ 4*BitStream[j*8+2]+ 2*BitStream[j*8+1]+ BitStream[j*8]; } num_blocks++; } bitidx = 0; block_done = 0; half_switch = 0; } if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0; else dir = 1; } if(bitidx==255) bitidx=0; warnings = 0; if(num_blocks == 4) break; } memcpy(outBlocks, Blocks, 16*num_blocks); return num_blocks; } int IsBlock0PCF7931(uint8_t *Block) { // Assume RFU means 0 :) if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled return 1; if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ? return 1; return 0; } int IsBlock1PCF7931(uint8_t *Block) { // Assume RFU means 0 :) if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0) if((Block[14] & 0x7f) <= 9 && Block[15] <= 9) return 1; return 0; } #define ALLOC 16 void ReadPCF7931() { uint8_t Blocks[8][17]; uint8_t tmpBlocks[4][16]; int i, j, ind, ind2, n; int num_blocks = 0; int max_blocks = 8; int ident = 0; int error = 0; int tries = 0; memset(Blocks, 0, 8*17*sizeof(uint8_t)); do { memset(tmpBlocks, 0, 4*16*sizeof(uint8_t)); n = DemodPCF7931((uint8_t**)tmpBlocks); if(!n) error++; if(error==10 && num_blocks == 0) { Dbprintf("Error, no tag or bad tag"); return; } else if (tries==20 || error==10) { Dbprintf("Error reading the tag"); Dbprintf("Here is the partial content"); goto end; } for(i=0; i= 0; ind--,ind2--) { if(ind2 < 0) ind2 = max_blocks; if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found // Dbprintf("Tmp %d -> Block %d", ind, ind2); memcpy(Blocks[ind2], tmpBlocks[ind], 16); Blocks[ind2][ALLOC] = 1; num_blocks++; if(num_blocks == max_blocks) goto end; } } for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) { if(ind2 > max_blocks) ind2 = 0; if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found // Dbprintf("Tmp %d -> Block %d", ind, ind2); memcpy(Blocks[ind2], tmpBlocks[ind], 16); Blocks[ind2][ALLOC] = 1; num_blocks++; if(num_blocks == max_blocks) goto end; } } } } } } } tries++; if (BUTTON_PRESS()) return; } while (num_blocks != max_blocks); end: Dbprintf("-----------------------------------------"); Dbprintf("Memory content:"); Dbprintf("-----------------------------------------"); for(i=0; i", i); } Dbprintf("-----------------------------------------"); return ; } //----------------------------------- // EM4469 / EM4305 routines //----------------------------------- #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored #define FWD_CMD_WRITE 0xA #define FWD_CMD_READ 0x9 #define FWD_CMD_DISABLE 0x5 uint8_t forwardLink_data[64]; //array of forwarded bits uint8_t * forward_ptr; //ptr for forward message preparation uint8_t fwd_bit_sz; //forwardlink bit counter uint8_t * fwd_write_ptr; //forwardlink bit pointer //==================================================================== // prepares command bits // see EM4469 spec //==================================================================== //-------------------------------------------------------------------- uint8_t Prepare_Cmd( uint8_t cmd ) { //-------------------------------------------------------------------- *forward_ptr++ = 0; //start bit *forward_ptr++ = 0; //second pause for 4050 code *forward_ptr++ = cmd; cmd >>= 1; *forward_ptr++ = cmd; cmd >>= 1; *forward_ptr++ = cmd; cmd >>= 1; *forward_ptr++ = cmd; return 6; //return number of emited bits } //==================================================================== // prepares address bits // see EM4469 spec //==================================================================== //-------------------------------------------------------------------- uint8_t Prepare_Addr( uint8_t addr ) { //-------------------------------------------------------------------- register uint8_t line_parity; uint8_t i; line_parity = 0; for(i=0;i<6;i++) { *forward_ptr++ = addr; line_parity ^= addr; addr >>= 1; } *forward_ptr++ = (line_parity & 1); return 7; //return number of emited bits } //==================================================================== // prepares data bits intreleaved with parity bits // see EM4469 spec //==================================================================== //-------------------------------------------------------------------- uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) { //-------------------------------------------------------------------- register uint8_t line_parity; register uint8_t column_parity; register uint8_t i, j; register uint16_t data; data = data_low; column_parity = 0; for(i=0; i<4; i++) { line_parity = 0; for(j=0; j<8; j++) { line_parity ^= data; column_parity ^= (data & 1) << j; *forward_ptr++ = data; data >>= 1; } *forward_ptr++ = line_parity; if(i == 1) data = data_hi; } for(j=0; j<8; j++) { *forward_ptr++ = column_parity; column_parity >>= 1; } *forward_ptr = 0; return 45; //return number of emited bits } //==================================================================== // Forward Link send function // Requires: forwarLink_data filled with valid bits (1 bit per byte) // fwd_bit_count set with number of bits to be sent //==================================================================== void SendForward(uint8_t fwd_bit_count) { fwd_write_ptr = forwardLink_data; fwd_bit_sz = fwd_bit_count; LED_D_ON(); //Field on FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); // Give it a bit of time for the resonant antenna to settle. // And for the tag to fully power up SpinDelay(150); // force 1st mod pulse (start gap must be longer for 4305) fwd_bit_sz--; //prepare next bit modulation fwd_write_ptr++; FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off SpinDelayUs(55*8); //55 cycles off (8us each)for 4305 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);//field on SpinDelayUs(16*8); //16 cycles on (8us each) // now start writting while(fwd_bit_sz-- > 0) { //prepare next bit modulation if(((*fwd_write_ptr++) & 1) == 1) SpinDelayUs(32*8); //32 cycles at 125Khz (8us each) else { //These timings work for 4469/4269/4305 (with the 55*8 above) FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off SpinDelayUs(23*8); //16-4 cycles off (8us each) FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);//field on SpinDelayUs(9*8); //16 cycles on (8us each) } } } void EM4xLogin(uint32_t Password) { uint8_t fwd_bit_count; forward_ptr = forwardLink_data; fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN ); fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 ); SendForward(fwd_bit_count); //Wait for command to complete SpinDelay(20); } void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) { uint8_t fwd_bit_count; uint8_t *dest = (uint8_t *)BigBuf; int m=0, i=0; //If password mode do login if (PwdMode == 1) EM4xLogin(Pwd); forward_ptr = forwardLink_data; fwd_bit_count = Prepare_Cmd( FWD_CMD_READ ); fwd_bit_count += Prepare_Addr( Address ); m = sizeof(BigBuf); // Clear destination buffer before sending the command memset(dest, 128, m); // Connect the A/D to the peak-detected low-frequency path. SetAdcMuxFor(GPIO_MUXSEL_LOPKD); // Now set up the SSC to get the ADC samples that are now streaming at us. FpgaSetupSsc(); SendForward(fwd_bit_count); // Now do the acquisition i = 0; for(;;) { if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) { AT91C_BASE_SSC->SSC_THR = 0x43; } if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) { dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR; i++; if (i >= m) break; } } FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off LED_D_OFF(); } void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) { uint8_t fwd_bit_count; //If password mode do login if (PwdMode == 1) EM4xLogin(Pwd); forward_ptr = forwardLink_data; fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE ); fwd_bit_count += Prepare_Addr( Address ); fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 ); SendForward(fwd_bit_count); //Wait for write to complete SpinDelay(20); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off LED_D_OFF(); } ================================================ FILE: TamagotchiFriends/proxmark/armsrc/lfops_rcv_works.txt ================================================ //----------------------------------------------------------------------------- // This code is licensed to you under the terms of the GNU GPL, version 2 or, // at your option, any later version. See the LICENSE.txt file for the text of // the license. //----------------------------------------------------------------------------- // Miscellaneous routines for low frequency tag operations. // Tags supported here so far are Texas Instruments (TI), HID // Also routines for raw mode reading/simulating of LF waveform //----------------------------------------------------------------------------- #include "proxmark3.h" #include "apps.h" #include "util.h" #include "hitag2.h" #include "crc16.h" #include "string.h" volatile unsigned long timer0_millis = 0; void AcquireRawAdcSamples125k(int at134khz) { if (at134khz) FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz else FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 94); //125Khz AcquireTiType(); } // split into two routines so we can avoid timing issues after sending commands // void DoAcquisition125k(void) { uint8_t *dest = (uint8_t *)BigBuf; int n = sizeof(BigBuf); int i; memset(dest, 0, n); i = 0; for(;;) { if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) { AT91C_BASE_SSC->SSC_THR = 0x43; LED_D_ON(); } if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) { dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR; i++; LED_D_OFF(); if (i >= n) break; } } Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...", dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]); } void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command) { int at134khz; /* Make sure the tag is reset */ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); SpinDelay(2500); // see if 'h' was specified if (command[strlen((char *) command) - 1] == 'h') at134khz = TRUE; else at134khz = FALSE; if (at134khz) FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz else FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz ////FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); // Give it a bit of time for the resonant antenna to settle. SpinDelay(50); // And a little more time for the tag to fully power up SpinDelay(2000); // Now set up the SSC to get the ADC samples that are now streaming at us. FpgaSetupSsc(); // now modulate the reader field while(*command != '\0' && *command != ' ') { FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); LED_D_OFF(); SpinDelayUs(delay_off); if (at134khz) FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz else FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz ////FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); LED_D_ON(); if(*(command++) == '0') SpinDelayUs(period_0); else SpinDelayUs(period_1); } FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); LED_D_OFF(); SpinDelayUs(delay_off); if (at134khz) FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz else FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz ////FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); // now do the read DoAcquisition125k(); } /* blank r/w tag data stream ...0000000000000000 01111111 1010101010101010101010101010101010101010101010101010101010101010 0011010010100001 01111111 101010101010101[0]000... [5555fe852c5555555555555555fe0000] */ void ReadTItag(void) { // some hardcoded initial params // when we read a TI tag we sample the zerocross line at 2Mhz // TI tags modulate a 1 as 16 cycles of 123.2Khz // TI tags modulate a 0 as 16 cycles of 134.2Khz #define FSAMPLE 2000000 #define FREQLO 123200 #define FREQHI 134200 signed char *dest = (signed char *)BigBuf; int n = sizeof(BigBuf); // int *dest = GraphBuffer; // int n = GraphTraceLen; // 128 bit shift register [shift3:shift2:shift1:shift0] uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0; int i, cycles=0, samples=0; // how many sample points fit in 16 cycles of each frequency uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI; // when to tell if we're close enough to one freq or another uint32_t threshold = (sampleslo - sampleshi + 1)>>1; // TI tags charge at 134.2Khz FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 94); //134.8Khz // Place FPGA in passthrough mode, in this mode the CROSS_LO line // connects to SSP_DIN and the SSP_DOUT logic level controls // whether we're modulating the antenna (high) // or listening to the antenna (low) FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU); // get TI tag data into the buffer AcquireTiType(); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); for (i=0; i0) ) { cycles++; // after 16 cycles, measure the frequency if (cycles>15) { cycles=0; samples=i-samples; // number of samples in these 16 cycles // TI bits are coming to us lsb first so shift them // right through our 128 bit right shift register shift0 = (shift0>>1) | (shift1 << 31); shift1 = (shift1>>1) | (shift2 << 31); shift2 = (shift2>>1) | (shift3 << 31); shift3 >>= 1; // check if the cycles fall close to the number // expected for either the low or high frequency if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) { // low frequency represents a 1 shift3 |= (1<<31); } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) { // high frequency represents a 0 } else { // probably detected a gay waveform or noise // use this as gaydar or discard shift register and start again shift3 = shift2 = shift1 = shift0 = 0; } samples = i; // for each bit we receive, test if we've detected a valid tag // if we see 17 zeroes followed by 6 ones, we might have a tag // remember the bits are backwards if ( ((shift0 & 0x7fffff) == 0x7e0000) ) { // if start and end bytes match, we have a tag so break out of the loop if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) { cycles = 0xF0B; //use this as a flag (ugly but whatever) break; } } } } } // if flag is set we have a tag if (cycles!=0xF0B) { DbpString("Info: No valid tag detected."); } else { // put 64 bit data into shift1 and shift0 shift0 = (shift0>>24) | (shift1 << 8); shift1 = (shift1>>24) | (shift2 << 8); // align 16 bit crc into lower half of shift2 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff; // if r/w tag, check ident match if ( shift3&(1<<15) ) { DbpString("Info: TI tag is rewriteable"); // only 15 bits compare, last bit of ident is not valid if ( ((shift3>>16)^shift0)&0x7fff ) { DbpString("Error: Ident mismatch!"); } else { DbpString("Info: TI tag ident is valid"); } } else { DbpString("Info: TI tag is readonly"); } // WARNING the order of the bytes in which we calc crc below needs checking // i'm 99% sure the crc algorithm is correct, but it may need to eat the // bytes in reverse or something // calculate CRC uint32_t crc=0; crc = update_crc16(crc, (shift0)&0xff); crc = update_crc16(crc, (shift0>>8)&0xff); crc = update_crc16(crc, (shift0>>16)&0xff); crc = update_crc16(crc, (shift0>>24)&0xff); crc = update_crc16(crc, (shift1)&0xff); crc = update_crc16(crc, (shift1>>8)&0xff); crc = update_crc16(crc, (shift1>>16)&0xff); crc = update_crc16(crc, (shift1>>24)&0xff); Dbprintf("Info: Tag data: %x%08x, crc=%x", (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF); if (crc != (shift2&0xffff)) { Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc); } else { DbpString("Info: CRC is good"); } } } void WriteTIbyte(uint8_t b) { int i = 0; //prolog //SpinDelayUs(1000); // modulate antenna HIGH(GPIO_SSC_DOUT); SpinDelayUs(540); LOW(GPIO_SSC_DOUT); // modulate 8 bits out to the antenna for (i=7; i>=0; i--) { if (b&(1<PIO_PDR = GPIO_SSC_DIN; AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN; // steal this pin from the SSP and use it to control the modulation AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT; AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST; AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN; // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long // 48/2 = 24 MHz clock must be divided by 12 AT91C_BASE_SSC->SSC_CMR = 12; AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0); AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF; AT91C_BASE_SSC->SSC_TCMR = 0; AT91C_BASE_SSC->SSC_TFMR = 0; // modulate antenna //HIGH(GPIO_SSC_DOUT); // Charge TI tag for 50ms. SpinDelay(50); // stop modulating antenna and listen //LED_A_ON(); LOW(GPIO_SSC_DOUT); //ti = GetTickCount(); //SpinDelay(1000); //ti = GetTickCount() - ti; //Dbprintf("timer(1s): %d t=%d", ti, GetTickCount()); //LED_A_OFF(); LED_D_ON(); i = 0; ti = GetTickCount(); for(;;) { if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) { BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer i++; if(i >= 40000) break; } WDT_HIT(); } ti = GetTickCount() - ti; Dbprintf("timer(1s): %d t=%d", ti, GetTickCount()); LED_D_OFF(); // return stolen pin to SSP AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT; AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT; } // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc // if crc provided, it will be written with the data verbatim (even if bogus) // if not provided a valid crc will be computed from the data and written. void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc) { int i; //if(crc == 0) { // crc = update_crc16(crc, (idlo)&0xff); // crc = update_crc16(crc, (idlo>>8)&0xff); // crc = update_crc16(crc, (idlo>>16)&0xff); // crc = update_crc16(crc, (idlo>>24)&0xff); // crc = update_crc16(crc, (idhi)&0xff); // crc = update_crc16(crc, (idhi>>8)&0xff); // crc = update_crc16(crc, (idhi>>16)&0xff); // crc = update_crc16(crc, (idhi>>24)&0xff); //} //Dbprintf("Writing to tag: %x%08x, crc=%x", // (unsigned int) idhi, (unsigned int) idlo, crc); // TI tags charge at 134.2Khz //88 is 125 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 94); //134.8Khz // Place FPGA in passthrough mode, in this mode the CROSS_LO line // connects to SSP_DIN and the SSP_DOUT logic level controls // whether we're modulating the antenna (high) // or listening to the antenna (low) FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU); LED_A_ON(); // steal this pin from the SSP and use it to control the modulation AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT; AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; // writing algorithm: // a high bit consists of a field off for 1ms and field on for 1ms // a low bit consists of a field off for 0.3ms and field on for 1.7ms // initiate a charge time of 50ms (field on) then immediately start writing bits // start by writing 0xBB (keyword) and 0xEB (password) // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer) // finally end with 0x0300 (write frame) // all data is sent lsb firts // finish with 15ms programming time // modulate antenna //HIGH(GPIO_SSC_DOUT); //SpinDelay(10000); // charge time for(i = 0; i < 10; i++){ WriteTIbyte(0xf0); WriteTIbyte(0x00); WriteTIbyte( 0x0f ); WriteTIbyte(0x01); WriteTIbyte(0x00); WriteTIbyte(0x07); WriteTIbyte(0x2d); WriteTIbyte( 0x00 ); WriteTIbyte(0x09); WriteTIbyte(0x00); WriteTIbyte(0x01); WriteTIbyte(0x0B); WriteTIbyte( 0x08 ); WriteTIbyte(0x0D); WriteTIbyte(0x0A); WriteTIbyte(0x18); WriteTIbyte(0x1a); WriteTIbyte( 0x1a ); WriteTIbyte( 0xc4 ); //LOW(GPIO_SSC_DOUT); SpinDelay(100); WriteTIbyte(0xf0); WriteTIbyte(0x06); WriteTIbyte( 0x04 ); WriteTIbyte(0x01); WriteTIbyte(0x06); WriteTIbyte(0x07); WriteTIbyte(0x2d); WriteTIbyte( 0x45 ); SpinDelay(1000); } LED_A_OFF(); // get TI tag data into the buffer //AcquireTiType(); //FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); DbpString("Done"); } void SimulateTagLowFrequency(int period, int gap, int ledcontrol) { int i; uint8_t *tab = (uint8_t *)BigBuf; FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT); AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK; AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK; #define SHORT_COIL() LOW(GPIO_SSC_DOUT) #define OPEN_COIL() HIGH(GPIO_SSC_DOUT) i = 0; for(;;) { while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) { if(BUTTON_PRESS()) { DbpString("Stopped"); return; } WDT_HIT(); } if (ledcontrol) LED_D_ON(); if(tab[i]) OPEN_COIL(); else SHORT_COIL(); if (ledcontrol) LED_D_OFF(); while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) { if(BUTTON_PRESS()) { DbpString("Stopped"); return; } WDT_HIT(); } i++; if(i == period) { i = 0; if (gap) { SHORT_COIL(); SpinDelayUs(gap); } } } } #define DEBUG_FRAME_CONTENTS 1 void SimulateTagLowFrequencyBidir(int divisor, int t0) { } // compose fc/8 fc/10 waveform static void fc(int c, int *n) { uint8_t *dest = (uint8_t *)BigBuf; int idx; // for when we want an fc8 pattern every 4 logical bits if(c==0) { dest[((*n)++)]=1; dest[((*n)++)]=1; dest[((*n)++)]=0; dest[((*n)++)]=0; dest[((*n)++)]=0; dest[((*n)++)]=0; dest[((*n)++)]=0; dest[((*n)++)]=0; } // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples if(c==8) { for (idx=0; idx<6; idx++) { dest[((*n)++)]=1; dest[((*n)++)]=1; dest[((*n)++)]=0; dest[((*n)++)]=0; dest[((*n)++)]=0; dest[((*n)++)]=0; dest[((*n)++)]=0; dest[((*n)++)]=0; } } // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples if(c==10) { for (idx=0; idx<5; idx++) { dest[((*n)++)]=1; dest[((*n)++)]=1; dest[((*n)++)]=1; dest[((*n)++)]=0; dest[((*n)++)]=0; dest[((*n)++)]=0; dest[((*n)++)]=0; dest[((*n)++)]=0; dest[((*n)++)]=0; dest[((*n)++)]=0; } } } // prepare a waveform pattern in the buffer based on the ID given then // simulate a HID tag until the button is pressed void CmdHIDsimTAG(int hi, int lo, int ledcontrol) { int n=0, i=0; /* HID tag bitstream format The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits A 1 bit is represented as 6 fc8 and 5 fc10 patterns A 0 bit is represented as 5 fc10 and 6 fc8 patterns A fc8 is inserted before every 4 bits A special start of frame pattern is used consisting a0b0 where a and b are neither 0 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10) */ if (hi>0xFFF) { DbpString("Tags can only have 44 bits."); return; } fc(0,&n); // special start of frame marker containing invalid bit sequences fc(8, &n); fc(8, &n); // invalid fc(8, &n); fc(10, &n); // logical 0 fc(10, &n); fc(10, &n); // invalid fc(8, &n); fc(10, &n); // logical 0 WDT_HIT(); // manchester encode bits 43 to 32 for (i=11; i>=0; i--) { if ((i%4)==3) fc(0,&n); if ((hi>>i)&1) { fc(10, &n); fc(8, &n); // low-high transition } else { fc(8, &n); fc(10, &n); // high-low transition } } WDT_HIT(); // manchester encode bits 31 to 0 for (i=31; i>=0; i--) { if ((i%4)==3) fc(0,&n); if ((lo>>i)&1) { fc(10, &n); fc(8, &n); // low-high transition } else { fc(8, &n); fc(10, &n); // high-low transition } } if (ledcontrol) LED_A_ON(); SimulateTagLowFrequency(n, 0, ledcontrol); if (ledcontrol) LED_A_OFF(); } // loop to capture raw HID waveform then FSK demodulate the TAG ID from it void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol) { uint8_t *dest = (uint8_t *)BigBuf; int m=0, n=0, i=0, idx=0, found=0, lastval=0; uint32_t hi2=0, hi=0, lo=0; FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); // Connect the A/D to the peak-detected low-frequency path. SetAdcMuxFor(GPIO_MUXSEL_LOPKD); // Give it a bit of time for the resonant antenna to settle. SpinDelay(50); // Now set up the SSC to get the ADC samples that are now streaming at us. FpgaSetupSsc(); for(;;) { WDT_HIT(); if (ledcontrol) LED_A_ON(); if(BUTTON_PRESS()) { DbpString("Stopped"); if (ledcontrol) LED_A_OFF(); return; } i = 0; m = sizeof(BigBuf); memset(dest,128,m); for(;;) { if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { AT91C_BASE_SSC->SSC_THR = 0x43; if (ledcontrol) LED_D_ON(); } if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR; // we don't care about actual value, only if it's more or less than a // threshold essentially we capture zero crossings for later analysis if(dest[i] < 127) dest[i] = 0; else dest[i] = 1; i++; if (ledcontrol) LED_D_OFF(); if(i >= m) { break; } } } // FSK demodulator // sync to first lo-hi transition for( idx=1; idx>1) & 0xFFFF); } else { Dbprintf("TAG ID: %x%08x (%d)", (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); } /* if we're only looking for one tag */ if (findone) { *high = hi; *low = lo; return; } hi2=0; hi=0; lo=0; found=0; } } if (found) { if (dest[idx] && (!dest[idx+1]) ) { hi2=(hi2<<1)|(hi>>31); hi=(hi<<1)|(lo>>31); lo=(lo<<1)|0; } else if ( (!dest[idx]) && dest[idx+1]) { hi2=(hi2<<1)|(hi>>31); hi=(hi<<1)|(lo>>31); lo=(lo<<1)|1; } else { found=0; hi2=0; hi=0; lo=0; } idx++; } if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) ) { found=1; idx+=6; if (found && (hi|lo)) { if (hi2 != 0){ Dbprintf("TAG ID: %x%08x%08x (%d)", (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); } else { Dbprintf("TAG ID: %x%08x (%d)", (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); } /* if we're only looking for one tag */ if (findone) { *high = hi; *low = lo; return; } hi2=0; hi=0; lo=0; found=0; } } } WDT_HIT(); } } /*------------------------------ * T5555/T5557/T5567 routines *------------------------------ */ /* T55x7 configuration register definitions */ #define T55x7_POR_DELAY 0x00000001 #define T55x7_ST_TERMINATOR 0x00000008 #define T55x7_PWD 0x00000010 #define T55x7_MAXBLOCK_SHIFT 5 #define T55x7_AOR 0x00000200 #define T55x7_PSKCF_RF_2 0 #define T55x7_PSKCF_RF_4 0x00000400 #define T55x7_PSKCF_RF_8 0x00000800 #define T55x7_MODULATION_DIRECT 0 #define T55x7_MODULATION_PSK1 0x00001000 #define T55x7_MODULATION_PSK2 0x00002000 #define T55x7_MODULATION_PSK3 0x00003000 #define T55x7_MODULATION_FSK1 0x00004000 #define T55x7_MODULATION_FSK2 0x00005000 #define T55x7_MODULATION_FSK1a 0x00006000 #define T55x7_MODULATION_FSK2a 0x00007000 #define T55x7_MODULATION_MANCHESTER 0x00008000 #define T55x7_MODULATION_BIPHASE 0x00010000 #define T55x7_BITRATE_RF_8 0 #define T55x7_BITRATE_RF_16 0x00040000 #define T55x7_BITRATE_RF_32 0x00080000 #define T55x7_BITRATE_RF_40 0x000C0000 #define T55x7_BITRATE_RF_50 0x00100000 #define T55x7_BITRATE_RF_64 0x00140000 #define T55x7_BITRATE_RF_100 0x00180000 #define T55x7_BITRATE_RF_128 0x001C0000 /* T5555 (Q5) configuration register definitions */ #define T5555_ST_TERMINATOR 0x00000001 #define T5555_MAXBLOCK_SHIFT 0x00000001 #define T5555_MODULATION_MANCHESTER 0 #define T5555_MODULATION_PSK1 0x00000010 #define T5555_MODULATION_PSK2 0x00000020 #define T5555_MODULATION_PSK3 0x00000030 #define T5555_MODULATION_FSK1 0x00000040 #define T5555_MODULATION_FSK2 0x00000050 #define T5555_MODULATION_BIPHASE 0x00000060 #define T5555_MODULATION_DIRECT 0x00000070 #define T5555_INVERT_OUTPUT 0x00000080 #define T5555_PSK_RF_2 0 #define T5555_PSK_RF_4 0x00000100 #define T5555_PSK_RF_8 0x00000200 #define T5555_USE_PWD 0x00000400 #define T5555_USE_AOR 0x00000800 #define T5555_BITRATE_SHIFT 12 #define T5555_FAST_WRITE 0x00004000 #define T5555_PAGE_SELECT 0x00008000 /* * Relevant times in microsecond * To compensate antenna falling times shorten the write times * and enlarge the gap ones. */ #define START_GAP 250 #define WRITE_GAP 160 #define WRITE_0 144 // 192 #define WRITE_1 400 // 432 for T55x7; 448 for E5550 // Write one bit to card void T55xxWriteBit(int bit) { FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); if (bit == 0) SpinDelayUs(WRITE_0); else SpinDelayUs(WRITE_1); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); SpinDelayUs(WRITE_GAP); } // Write one card block in page 0, no lock void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode) { unsigned int i; FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); // Give it a bit of time for the resonant antenna to settle. // And for the tag to fully power up SpinDelay(150); // Now start writting FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); SpinDelayUs(START_GAP); // Opcode T55xxWriteBit(1); T55xxWriteBit(0); //Page 0 if (PwdMode == 1){ // Pwd for (i = 0x80000000; i != 0; i >>= 1) T55xxWriteBit(Pwd & i); } // Lock bit T55xxWriteBit(0); // Data for (i = 0x80000000; i != 0; i >>= 1) T55xxWriteBit(Data & i); // Block for (i = 0x04; i != 0; i >>= 1) T55xxWriteBit(Block & i); // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550, // so wait a little more) FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); SpinDelay(20); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); } // Read one card block in page 0 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode) { uint8_t *dest = (uint8_t *)BigBuf; int m=0, i=0; m = sizeof(BigBuf); // Clear destination buffer before sending the command memset(dest, 128, m); // Connect the A/D to the peak-detected low-frequency path. SetAdcMuxFor(GPIO_MUXSEL_LOPKD); // Now set up the SSC to get the ADC samples that are now streaming at us. FpgaSetupSsc(); LED_D_ON(); FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); // Give it a bit of time for the resonant antenna to settle. // And for the tag to fully power up SpinDelay(150); // Now start writting FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); SpinDelayUs(START_GAP); // Opcode T55xxWriteBit(1); T55xxWriteBit(0); //Page 0 if (PwdMode == 1){ // Pwd for (i = 0x80000000; i != 0; i >>= 1) T55xxWriteBit(Pwd & i); } // Lock bit T55xxWriteBit(0); // Block for (i = 0x04; i != 0; i >>= 1) T55xxWriteBit(Block & i); // Turn field on to read the response FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); // Now do the acquisition i = 0; for(;;) { if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) { AT91C_BASE_SSC->SSC_THR = 0x43; } if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) { dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR; // we don't care about actual value, only if it's more or less than a // threshold essentially we capture zero crossings for later analysis // if(dest[i] < 127) dest[i] = 0; else dest[i] = 1; i++; if (i >= m) break; } } FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off LED_D_OFF(); DbpString("DONE!"); } // Read card traceability data (page 1) void T55xxReadTrace(void){ uint8_t *dest = (uint8_t *)BigBuf; int m=0, i=0; m = sizeof(BigBuf); // Clear destination buffer before sending the command memset(dest, 128, m); // Connect the A/D to the peak-detected low-frequency path. SetAdcMuxFor(GPIO_MUXSEL_LOPKD); // Now set up the SSC to get the ADC samples that are now streaming at us. FpgaSetupSsc(); LED_D_ON(); FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); // Give it a bit of time for the resonant antenna to settle. // And for the tag to fully power up SpinDelay(150); // Now start writting FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); SpinDelayUs(START_GAP); // Opcode T55xxWriteBit(1); T55xxWriteBit(1); //Page 1 // Turn field on to read the response FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); // Now do the acquisition i = 0; for(;;) { if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) { AT91C_BASE_SSC->SSC_THR = 0x43; } if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) { dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR; i++; if (i >= m) break; } } FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off LED_D_OFF(); DbpString("DONE!"); } /*-------------- Cloning routines -----------*/ // Copy HID id to card and setup block 0 config void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) { int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format int last_block = 0; if (longFMT){ // Ensure no more than 84 bits supplied if (hi2>0xFFFFF) { DbpString("Tags can only have 84 bits."); return; } // Build the 6 data blocks for supplied 84bit ID last_block = 6; data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded) for (int i=0;i<4;i++) { if (hi2 & (1<<(19-i))) data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10 else data1 |= (1<<((3-i)*2)); // 0 -> 01 } data2 = 0; for (int i=0;i<16;i++) { if (hi2 & (1<<(15-i))) data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10 else data2 |= (1<<((15-i)*2)); // 0 -> 01 } data3 = 0; for (int i=0;i<16;i++) { if (hi & (1<<(31-i))) data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10 else data3 |= (1<<((15-i)*2)); // 0 -> 01 } data4 = 0; for (int i=0;i<16;i++) { if (hi & (1<<(15-i))) data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10 else data4 |= (1<<((15-i)*2)); // 0 -> 01 } data5 = 0; for (int i=0;i<16;i++) { if (lo & (1<<(31-i))) data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10 else data5 |= (1<<((15-i)*2)); // 0 -> 01 } data6 = 0; for (int i=0;i<16;i++) { if (lo & (1<<(15-i))) data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10 else data6 |= (1<<((15-i)*2)); // 0 -> 01 } } else { // Ensure no more than 44 bits supplied if (hi>0xFFF) { DbpString("Tags can only have 44 bits."); return; } // Build the 3 data blocks for supplied 44bit ID last_block = 3; data1 = 0x1D000000; // load preamble for (int i=0;i<12;i++) { if (hi & (1<<(11-i))) data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10 else data1 |= (1<<((11-i)*2)); // 0 -> 01 } data2 = 0; for (int i=0;i<16;i++) { if (lo & (1<<(31-i))) data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10 else data2 |= (1<<((15-i)*2)); // 0 -> 01 } data3 = 0; for (int i=0;i<16;i++) { if (lo & (1<<(15-i))) data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10 else data3 |= (1<<((15-i)*2)); // 0 -> 01 } } LED_D_ON(); // Program the data blocks for supplied ID // and the block 0 for HID format T55xxWriteBlock(data1,1,0,0); T55xxWriteBlock(data2,2,0,0); T55xxWriteBlock(data3,3,0,0); if (longFMT) { // if long format there are 6 blocks T55xxWriteBlock(data4,4,0,0); T55xxWriteBlock(data5,5,0,0); T55xxWriteBlock(data6,6,0,0); } // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long) T55xxWriteBlock(T55x7_BITRATE_RF_50 | T55x7_MODULATION_FSK2a | last_block << T55x7_MAXBLOCK_SHIFT, 0,0,0); LED_D_OFF(); DbpString("DONE!"); } // Define 9bit header for EM410x tags #define EM410X_HEADER 0x1FF #define EM410X_ID_LENGTH 40 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo) { int i, id_bit; uint64_t id = EM410X_HEADER; uint64_t rev_id = 0; // reversed ID int c_parity[4]; // column parity int r_parity = 0; // row parity uint32_t clock = 0; // Reverse ID bits given as parameter (for simpler operations) for (i = 0; i < EM410X_ID_LENGTH; ++i) { if (i < 32) { rev_id = (rev_id << 1) | (id_lo & 1); id_lo >>= 1; } else { rev_id = (rev_id << 1) | (id_hi & 1); id_hi >>= 1; } } for (i = 0; i < EM410X_ID_LENGTH; ++i) { id_bit = rev_id & 1; if (i % 4 == 0) { // Don't write row parity bit at start of parsing if (i) id = (id << 1) | r_parity; // Start counting parity for new row r_parity = id_bit; } else { // Count row parity r_parity ^= id_bit; } // First elements in column? if (i < 4) // Fill out first elements c_parity[i] = id_bit; else // Count column parity c_parity[i % 4] ^= id_bit; // Insert ID bit id = (id << 1) | id_bit; rev_id >>= 1; } // Insert parity bit of last row id = (id << 1) | r_parity; // Fill out column parity at the end of tag for (i = 0; i < 4; ++i) id = (id << 1) | c_parity[i]; // Add stop bit id <<= 1; Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555"); LED_D_ON(); // Write EM410x ID T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0); T55xxWriteBlock((uint32_t)id, 2, 0, 0); // Config for EM410x (RF/64, Manchester, Maxblock=2) if (card) { // Clock rate is stored in bits 8-15 of the card value clock = (card & 0xFF00) >> 8; Dbprintf("Clock rate: %d", clock); switch (clock) { case 32: clock = T55x7_BITRATE_RF_32; break; case 16: clock = T55x7_BITRATE_RF_16; break; case 0: // A value of 0 is assumed to be 64 for backwards-compatibility // Fall through... case 64: clock = T55x7_BITRATE_RF_64; break; default: Dbprintf("Invalid clock rate: %d", clock); return; } // Writing configuration for T55x7 tag T55xxWriteBlock(clock | T55x7_MODULATION_MANCHESTER | 2 << T55x7_MAXBLOCK_SHIFT, 0, 0, 0); } else // Writing configuration for T5555(Q5) tag T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT | T5555_MODULATION_MANCHESTER | 2 << T5555_MAXBLOCK_SHIFT, 0, 0, 0); LED_D_OFF(); Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555", (uint32_t)(id >> 32), (uint32_t)id); } // Clone Indala 64-bit tag by UID to T55x7 void CopyIndala64toT55x7(int hi, int lo) { //Program the 2 data blocks for supplied 64bit UID // and the block 0 for Indala64 format T55xxWriteBlock(hi,1,0,0); T55xxWriteBlock(lo,2,0,0); //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2) T55xxWriteBlock(T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | 2 << T55x7_MAXBLOCK_SHIFT, 0, 0, 0); //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data) // T5567WriteBlock(0x603E1042,0); DbpString("DONE!"); } void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7) { //Program the 7 data blocks for supplied 224bit UID // and the block 0 for Indala224 format T55xxWriteBlock(uid1,1,0,0); T55xxWriteBlock(uid2,2,0,0); T55xxWriteBlock(uid3,3,0,0); T55xxWriteBlock(uid4,4,0,0); T55xxWriteBlock(uid5,5,0,0); T55xxWriteBlock(uid6,6,0,0); T55xxWriteBlock(uid7,7,0,0); //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7) T55xxWriteBlock(T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | 7 << T55x7_MAXBLOCK_SHIFT, 0,0,0); //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data) // T5567WriteBlock(0x603E10E2,0); DbpString("DONE!"); } #define abs(x) ( ((x)<0) ? -(x) : (x) ) #define max(x,y) ( x GraphBuffer[0]) { while(i < GraphTraceLen) { if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax) break; i++; } dir = 0; } else { while(i < GraphTraceLen) { if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin) break; i++; } dir = 1; } lastval = i++; half_switch = 0; pmc = 0; block_done = 0; for (bitidx = 0; i < GraphTraceLen; i++) { if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin)) { lc = i - lastval; lastval = i; // Switch depending on lc length: // Tolerance is 1/8 of clock rate (arbitrary) if (abs(lc-clock/4) < tolerance) { // 16T0 if((i - pmc) == lc) { /* 16T0 was previous one */ /* It's a PMC ! */ i += (128+127+16+32+33+16)-1; lastval = i; pmc = 0; block_done = 1; } else { pmc = i; } } else if (abs(lc-clock/2) < tolerance) { // 32TO if((i - pmc) == lc) { /* 16T0 was previous one */ /* It's a PMC ! */ i += (128+127+16+32+33)-1; lastval = i; pmc = 0; block_done = 1; } else if(half_switch == 1) { BitStream[bitidx++] = 0; half_switch = 0; } else half_switch++; } else if (abs(lc-clock) < tolerance) { // 64TO BitStream[bitidx++] = 1; } else { // Error warnings++; if (warnings > 10) { Dbprintf("Error: too many detection errors, aborting."); return 0; } } if(block_done == 1) { if(bitidx == 128) { for(j=0; j<16; j++) { Blocks[num_blocks][j] = 128*BitStream[j*8+7]+ 64*BitStream[j*8+6]+ 32*BitStream[j*8+5]+ 16*BitStream[j*8+4]+ 8*BitStream[j*8+3]+ 4*BitStream[j*8+2]+ 2*BitStream[j*8+1]+ BitStream[j*8]; } num_blocks++; } bitidx = 0; block_done = 0; half_switch = 0; } if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0; else dir = 1; } if(bitidx==255) bitidx=0; warnings = 0; if(num_blocks == 4) break; } memcpy(outBlocks, Blocks, 16*num_blocks); return num_blocks; } int IsBlock0PCF7931(uint8_t *Block) { // Assume RFU means 0 :) if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled return 1; if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ? return 1; return 0; } int IsBlock1PCF7931(uint8_t *Block) { // Assume RFU means 0 :) if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0) if((Block[14] & 0x7f) <= 9 && Block[15] <= 9) return 1; return 0; } #define ALLOC 16 void ReadPCF7931() { uint8_t Blocks[8][17]; uint8_t tmpBlocks[4][16]; int i, j, ind, ind2, n; int num_blocks = 0; int max_blocks = 8; int ident = 0; int error = 0; int tries = 0; memset(Blocks, 0, 8*17*sizeof(uint8_t)); do { memset(tmpBlocks, 0, 4*16*sizeof(uint8_t)); n = DemodPCF7931((uint8_t**)tmpBlocks); if(!n) error++; if(error==10 && num_blocks == 0) { Dbprintf("Error, no tag or bad tag"); return; } else if (tries==20 || error==10) { Dbprintf("Error reading the tag"); Dbprintf("Here is the partial content"); goto end; } for(i=0; i= 0; ind--,ind2--) { if(ind2 < 0) ind2 = max_blocks; if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found // Dbprintf("Tmp %d -> Block %d", ind, ind2); memcpy(Blocks[ind2], tmpBlocks[ind], 16); Blocks[ind2][ALLOC] = 1; num_blocks++; if(num_blocks == max_blocks) goto end; } } for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) { if(ind2 > max_blocks) ind2 = 0; if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found // Dbprintf("Tmp %d -> Block %d", ind, ind2); memcpy(Blocks[ind2], tmpBlocks[ind], 16); Blocks[ind2][ALLOC] = 1; num_blocks++; if(num_blocks == max_blocks) goto end; } } } } } } } tries++; if (BUTTON_PRESS()) return; } while (num_blocks != max_blocks); end: Dbprintf("-----------------------------------------"); Dbprintf("Memory content:"); Dbprintf("-----------------------------------------"); for(i=0; i", i); } Dbprintf("-----------------------------------------"); return ; } //----------------------------------- // EM4469 / EM4305 routines //----------------------------------- #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored #define FWD_CMD_WRITE 0xA #define FWD_CMD_READ 0x9 #define FWD_CMD_DISABLE 0x5 uint8_t forwardLink_data[64]; //array of forwarded bits uint8_t * forward_ptr; //ptr for forward message preparation uint8_t fwd_bit_sz; //forwardlink bit counter uint8_t * fwd_write_ptr; //forwardlink bit pointer //==================================================================== // prepares command bits // see EM4469 spec //==================================================================== //-------------------------------------------------------------------- uint8_t Prepare_Cmd( uint8_t cmd ) { //-------------------------------------------------------------------- *forward_ptr++ = 0; //start bit *forward_ptr++ = 0; //second pause for 4050 code *forward_ptr++ = cmd; cmd >>= 1; *forward_ptr++ = cmd; cmd >>= 1; *forward_ptr++ = cmd; cmd >>= 1; *forward_ptr++ = cmd; return 6; //return number of emited bits } //==================================================================== // prepares address bits // see EM4469 spec //==================================================================== //-------------------------------------------------------------------- uint8_t Prepare_Addr( uint8_t addr ) { //-------------------------------------------------------------------- register uint8_t line_parity; uint8_t i; line_parity = 0; for(i=0;i<6;i++) { *forward_ptr++ = addr; line_parity ^= addr; addr >>= 1; } *forward_ptr++ = (line_parity & 1); return 7; //return number of emited bits } //==================================================================== // prepares data bits intreleaved with parity bits // see EM4469 spec //==================================================================== //-------------------------------------------------------------------- uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) { //-------------------------------------------------------------------- register uint8_t line_parity; register uint8_t column_parity; register uint8_t i, j; register uint16_t data; data = data_low; column_parity = 0; for(i=0; i<4; i++) { line_parity = 0; for(j=0; j<8; j++) { line_parity ^= data; column_parity ^= (data & 1) << j; *forward_ptr++ = data; data >>= 1; } *forward_ptr++ = line_parity; if(i == 1) data = data_hi; } for(j=0; j<8; j++) { *forward_ptr++ = column_parity; column_parity >>= 1; } *forward_ptr = 0; return 45; //return number of emited bits } //==================================================================== // Forward Link send function // Requires: forwarLink_data filled with valid bits (1 bit per byte) // fwd_bit_count set with number of bits to be sent //==================================================================== void SendForward(uint8_t fwd_bit_count) { fwd_write_ptr = forwardLink_data; fwd_bit_sz = fwd_bit_count; LED_D_ON(); //Field on FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); // Give it a bit of time for the resonant antenna to settle. // And for the tag to fully power up SpinDelay(150); // force 1st mod pulse (start gap must be longer for 4305) fwd_bit_sz--; //prepare next bit modulation fwd_write_ptr++; FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off SpinDelayUs(55*8); //55 cycles off (8us each)for 4305 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);//field on SpinDelayUs(16*8); //16 cycles on (8us each) // now start writting while(fwd_bit_sz-- > 0) { //prepare next bit modulation if(((*fwd_write_ptr++) & 1) == 1) SpinDelayUs(32*8); //32 cycles at 125Khz (8us each) else { //These timings work for 4469/4269/4305 (with the 55*8 above) FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off SpinDelayUs(23*8); //16-4 cycles off (8us each) FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);//field on SpinDelayUs(9*8); //16 cycles on (8us each) } } } void EM4xLogin(uint32_t Password) { uint8_t fwd_bit_count; forward_ptr = forwardLink_data; fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN ); fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 ); SendForward(fwd_bit_count); //Wait for command to complete SpinDelay(20); } void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) { uint8_t fwd_bit_count; uint8_t *dest = (uint8_t *)BigBuf; int m=0, i=0; //If password mode do login if (PwdMode == 1) EM4xLogin(Pwd); forward_ptr = forwardLink_data; fwd_bit_count = Prepare_Cmd( FWD_CMD_READ ); fwd_bit_count += Prepare_Addr( Address ); m = sizeof(BigBuf); // Clear destination buffer before sending the command memset(dest, 128, m); // Connect the A/D to the peak-detected low-frequency path. SetAdcMuxFor(GPIO_MUXSEL_LOPKD); // Now set up the SSC to get the ADC samples that are now streaming at us. FpgaSetupSsc(); SendForward(fwd_bit_count); // Now do the acquisition i = 0; for(;;) { if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) { AT91C_BASE_SSC->SSC_THR = 0x43; } if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) { dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR; i++; if (i >= m) break; } } FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off LED_D_OFF(); } void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) { uint8_t fwd_bit_count; //If password mode do login if (PwdMode == 1) EM4xLogin(Pwd); forward_ptr = forwardLink_data; fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE ); fwd_bit_count += Prepare_Addr( Address ); fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 ); SendForward(fwd_bit_count); //Wait for write to complete SpinDelay(20); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off LED_D_OFF(); } ================================================ FILE: TamagotchiFriends/proxmark/armsrc/mifarecmd.c ================================================ //----------------------------------------------------------------------------- // Merlok - June 2011, 2012 // Gerhard de Koning Gans - May 2008 // Hagen Fritsch - June 2010 // // This code is licensed to you under the terms of the GNU GPL, version 2 or, // at your option, any later version. See the LICENSE.txt file for the text of // the license. //----------------------------------------------------------------------------- // Routines to support ISO 14443 type A. //----------------------------------------------------------------------------- #include "mifarecmd.h" #include "apps.h" //----------------------------------------------------------------------------- // Select, Authenticaate, Read an MIFARE tag. // read block //----------------------------------------------------------------------------- void MifareReadBlock(uint8_t arg0, uint8_t arg1, uint8_t arg2, uint8_t *datain) { // params uint8_t blockNo = arg0; uint8_t keyType = arg1; uint64_t ui64Key = 0; ui64Key = bytes_to_num(datain, 6); // variables byte_t isOK = 0; byte_t dataoutbuf[16]; uint8_t uid[10]; uint32_t cuid; struct Crypto1State mpcs = {0, 0}; struct Crypto1State *pcs; pcs = &mpcs; // clear trace iso14a_clear_trace(); // iso14a_set_tracing(false); iso14443a_setup(); LED_A_ON(); LED_B_OFF(); LED_C_OFF(); while (true) { if(!iso14443a_select_card(uid, NULL, &cuid)) { if (MF_DBGLEVEL >= 1) Dbprintf("Can't select card"); break; }; if(mifare_classic_auth(pcs, cuid, blockNo, keyType, ui64Key, AUTH_FIRST)) { if (MF_DBGLEVEL >= 1) Dbprintf("Auth error"); break; }; if(mifare_classic_readblock(pcs, cuid, blockNo, dataoutbuf)) { if (MF_DBGLEVEL >= 1) Dbprintf("Read block error"); break; }; if(mifare_classic_halt(pcs, cuid)) { if (MF_DBGLEVEL >= 1) Dbprintf("Halt error"); break; }; isOK = 1; break; } // ----------------------------- crypto1 destroy crypto1_destroy(pcs); if (MF_DBGLEVEL >= 2) DbpString("READ BLOCK FINISHED"); // add trace trailer memset(uid, 0x44, 4); LogTrace(uid, 4, 0, 0, TRUE); // UsbCommand ack = {CMD_ACK, {isOK, 0, 0}}; // memcpy(ack.d.asBytes, dataoutbuf, 16); LED_B_ON(); cmd_send(CMD_ACK,isOK,0,0,dataoutbuf,16); // UsbSendPacket((uint8_t *)&ack, sizeof(UsbCommand)); LED_B_OFF(); // Thats it... FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); LEDsoff(); // iso14a_set_tracing(TRUE); } //----------------------------------------------------------------------------- // Select, Authenticaate, Read an MIFARE tag. // read sector (data = 4 x 16 bytes = 64 bytes) //----------------------------------------------------------------------------- void MifareReadSector(uint8_t arg0, uint8_t arg1, uint8_t arg2, uint8_t *datain) { // params uint8_t sectorNo = arg0; uint8_t keyType = arg1; uint64_t ui64Key = 0; ui64Key = bytes_to_num(datain, 6); // variables byte_t isOK = 0; byte_t dataoutbuf[16 * 4]; uint8_t uid[10]; uint32_t cuid; struct Crypto1State mpcs = {0, 0}; struct Crypto1State *pcs; pcs = &mpcs; // clear trace iso14a_clear_trace(); // iso14a_set_tracing(false); iso14443a_setup(); LED_A_ON(); LED_B_OFF(); LED_C_OFF(); while (true) { if(!iso14443a_select_card(uid, NULL, &cuid)) { if (MF_DBGLEVEL >= 1) Dbprintf("Can't select card"); break; }; if(mifare_classic_auth(pcs, cuid, sectorNo * 4, keyType, ui64Key, AUTH_FIRST)) { if (MF_DBGLEVEL >= 1) Dbprintf("Auth error"); break; }; if(mifare_classic_readblock(pcs, cuid, sectorNo * 4 + 0, dataoutbuf + 16 * 0)) { if (MF_DBGLEVEL >= 1) Dbprintf("Read block 0 error"); break; }; if(mifare_classic_readblock(pcs, cuid, sectorNo * 4 + 1, dataoutbuf + 16 * 1)) { if (MF_DBGLEVEL >= 1) Dbprintf("Read block 1 error"); break; }; if(mifare_classic_readblock(pcs, cuid, sectorNo * 4 + 2, dataoutbuf + 16 * 2)) { if (MF_DBGLEVEL >= 1) Dbprintf("Read block 2 error"); break; }; if(mifare_classic_readblock(pcs, cuid, sectorNo * 4 + 3, dataoutbuf + 16 * 3)) { if (MF_DBGLEVEL >= 1) Dbprintf("Read block 3 error"); break; }; if(mifare_classic_halt(pcs, cuid)) { if (MF_DBGLEVEL >= 1) Dbprintf("Halt error"); break; }; isOK = 1; break; } // ----------------------------- crypto1 destroy crypto1_destroy(pcs); if (MF_DBGLEVEL >= 2) DbpString("READ SECTOR FINISHED"); // add trace trailer memset(uid, 0x44, 4); LogTrace(uid, 4, 0, 0, TRUE); // UsbCommand ack = {CMD_ACK, {isOK, 0, 0}}; // memcpy(ack.d.asBytes, dataoutbuf, 16 * 2); LED_B_ON(); cmd_send(CMD_ACK,isOK,0,0,dataoutbuf,32); // UsbSendPacket((uint8_t *)&ack, sizeof(UsbCommand)); // SpinDelay(100); // memcpy(ack.d.asBytes, dataoutbuf + 16 * 2, 16 * 2); // UsbSendPacket((uint8_t *)&ack, sizeof(UsbCommand)); cmd_send(CMD_ACK,isOK,0,0,dataoutbuf+32, 32); LED_B_OFF(); // Thats it... FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); LEDsoff(); // iso14a_set_tracing(TRUE); } //----------------------------------------------------------------------------- // Select, Authenticaate, Read an MIFARE tag. // read block //----------------------------------------------------------------------------- void MifareWriteBlock(uint8_t arg0, uint8_t arg1, uint8_t arg2, uint8_t *datain) { // params uint8_t blockNo = arg0; uint8_t keyType = arg1; uint64_t ui64Key = 0; byte_t blockdata[16]; ui64Key = bytes_to_num(datain, 6); memcpy(blockdata, datain + 10, 16); // variables byte_t isOK = 0; uint8_t uid[10]; uint32_t cuid; struct Crypto1State mpcs = {0, 0}; struct Crypto1State *pcs; pcs = &mpcs; // clear trace iso14a_clear_trace(); // iso14a_set_tracing(false); iso14443a_setup(); LED_A_ON(); LED_B_OFF(); LED_C_OFF(); while (true) { if(!iso14443a_select_card(uid, NULL, &cuid)) { if (MF_DBGLEVEL >= 1) Dbprintf("Can't select card"); break; }; if(mifare_classic_auth(pcs, cuid, blockNo, keyType, ui64Key, AUTH_FIRST)) { if (MF_DBGLEVEL >= 1) Dbprintf("Auth error"); break; }; if(mifare_classic_writeblock(pcs, cuid, blockNo, blockdata)) { if (MF_DBGLEVEL >= 1) Dbprintf("Write block error"); break; }; if(mifare_classic_halt(pcs, cuid)) { if (MF_DBGLEVEL >= 1) Dbprintf("Halt error"); break; }; isOK = 1; break; } // ----------------------------- crypto1 destroy crypto1_destroy(pcs); if (MF_DBGLEVEL >= 2) DbpString("WRITE BLOCK FINISHED"); // add trace trailer memset(uid, 0x44, 4); LogTrace(uid, 4, 0, 0, TRUE); // UsbCommand ack = {CMD_ACK, {isOK, 0, 0}}; LED_B_ON(); cmd_send(CMD_ACK,isOK,0,0,0,0); // UsbSendPacket((uint8_t *)&ack, sizeof(UsbCommand)); LED_B_OFF(); // Thats it... FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); LEDsoff(); // iso14a_set_tracing(TRUE); } // Return 1 if the nonce is invalid else return 0 int valid_nonce(uint32_t Nt, uint32_t NtEnc, uint32_t Ks1, byte_t * parity) { return ((oddparity((Nt >> 24) & 0xFF) == ((parity[0]) ^ oddparity((NtEnc >> 24) & 0xFF) ^ BIT(Ks1,16))) & \ (oddparity((Nt >> 16) & 0xFF) == ((parity[1]) ^ oddparity((NtEnc >> 16) & 0xFF) ^ BIT(Ks1,8))) & \ (oddparity((Nt >> 8) & 0xFF) == ((parity[2]) ^ oddparity((NtEnc >> 8) & 0xFF) ^ BIT(Ks1,0)))) ? 1 : 0; } //----------------------------------------------------------------------------- // MIFARE nested authentication. // //----------------------------------------------------------------------------- void MifareNested(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain) { // params uint8_t blockNo = arg0; uint8_t keyType = arg1; uint8_t targetBlockNo = arg2 & 0xff; uint8_t targetKeyType = (arg2 >> 8) & 0xff; uint64_t ui64Key = 0; ui64Key = bytes_to_num(datain, 6); // variables int rtr, i, j, m, len; int davg, dmin, dmax; uint8_t uid[10]; uint32_t cuid, nt1, nt2, nttmp, nttest, par, ks1; uint8_t par_array[4]; nestedVector nvector[NES_MAX_INFO + 1][11]; int nvectorcount[NES_MAX_INFO + 1]; int ncount = 0; struct Crypto1State mpcs = {0, 0}; struct Crypto1State *pcs; pcs = &mpcs; uint8_t* receivedAnswer = mifare_get_bigbufptr(); //init for (i = 0; i < NES_MAX_INFO + 1; i++) nvectorcount[i] = 11; // 11 - empty block; // clear trace iso14a_clear_trace(); iso14a_set_tracing(false); iso14443a_setup(); LED_A_ON(); LED_B_ON(); LED_C_OFF(); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); SpinDelay(200); davg = dmax = 0; dmin = 2000; // test nonce distance for (rtr = 0; rtr < 10; rtr++) { FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); SpinDelay(100); FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD); // Test if the action was cancelled if(BUTTON_PRESS()) { break; } if(!iso14443a_select_card(uid, NULL, &cuid)) { if (MF_DBGLEVEL >= 1) Dbprintf("Can't select card"); break; }; if(mifare_classic_authex(pcs, cuid, blockNo, keyType, ui64Key, AUTH_FIRST, &nt1)) { if (MF_DBGLEVEL >= 1) Dbprintf("Auth1 error"); break; }; if(mifare_classic_authex(pcs, cuid, blockNo, keyType, ui64Key, AUTH_NESTED, &nt2)) { if (MF_DBGLEVEL >= 1) Dbprintf("Auth2 error"); break; }; nttmp = prng_successor(nt1, 500); for (i = 501; i < 2000; i++) { nttmp = prng_successor(nttmp, 1); if (nttmp == nt2) break; } if (i != 2000) { davg += i; if (dmin > i) dmin = i; if (dmax < i) dmax = i; if (MF_DBGLEVEL >= 4) Dbprintf("r=%d nt1=%08x nt2=%08x distance=%d", rtr, nt1, nt2, i); } } if (rtr == 0) return; davg = davg / rtr; if (MF_DBGLEVEL >= 3) Dbprintf("distance: min=%d max=%d avg=%d", dmin, dmax, davg); LED_B_OFF(); // ------------------------------------------------------------------------------------------------- LED_C_ON(); // get crypted nonces for target sector for (rtr = 0; rtr < NS_RETRIES_GETNONCE; rtr++) { if (MF_DBGLEVEL >= 4) Dbprintf("------------------------------"); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); SpinDelay(100); FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD); // Test if the action was cancelled if(BUTTON_PRESS()) { break; } if(!iso14443a_select_card(uid, NULL, &cuid)) { if (MF_DBGLEVEL >= 1) Dbprintf("Can't select card"); break; }; if(mifare_classic_authex(pcs, cuid, blockNo, keyType, ui64Key, AUTH_FIRST, &nt1)) { if (MF_DBGLEVEL >= 1) Dbprintf("Auth1 error"); break; }; // nested authentication len = mifare_sendcmd_shortex(pcs, AUTH_NESTED, 0x60 + (targetKeyType & 0x01), targetBlockNo, receivedAnswer, &par); if (len != 4) { if (MF_DBGLEVEL >= 1) Dbprintf("Auth2 error len=%d", len); break; }; nt2 = bytes_to_num(receivedAnswer, 4); if (MF_DBGLEVEL >= 4) Dbprintf("r=%d nt1=%08x nt2enc=%08x nt2par=%08x", rtr, nt1, nt2, par); // Parity validity check for (i = 0; i < 4; i++) { par_array[i] = (oddparity(receivedAnswer[i]) != ((par & 0x08) >> 3)); par = par << 1; } ncount = 0; nttest = prng_successor(nt1, dmin - NS_TOLERANCE); for (m = dmin - NS_TOLERANCE + 1; m < dmax + NS_TOLERANCE; m++) { nttest = prng_successor(nttest, 1); ks1 = nt2 ^ nttest; if (valid_nonce(nttest, nt2, ks1, par_array) && (ncount < 11)){ nvector[NES_MAX_INFO][ncount].nt = nttest; nvector[NES_MAX_INFO][ncount].ks1 = ks1; ncount++; nvectorcount[NES_MAX_INFO] = ncount; if (MF_DBGLEVEL >= 4) Dbprintf("valid m=%d ks1=%08x nttest=%08x", m, ks1, nttest); } } // select vector with length less than got if (nvectorcount[NES_MAX_INFO] != 0) { m = NES_MAX_INFO; for (i = 0; i < NES_MAX_INFO; i++) if (nvectorcount[i] > 10) { m = i; break; } if (m == NES_MAX_INFO) for (i = 0; i < NES_MAX_INFO; i++) if (nvectorcount[NES_MAX_INFO] < nvectorcount[i]) { m = i; break; } if (m != NES_MAX_INFO) { for (i = 0; i < nvectorcount[m]; i++) { nvector[m][i] = nvector[NES_MAX_INFO][i]; } nvectorcount[m] = nvectorcount[NES_MAX_INFO]; } } } LED_C_OFF(); // ----------------------------- crypto1 destroy crypto1_destroy(pcs); // add trace trailer memset(uid, 0x44, 4); LogTrace(uid, 4, 0, 0, TRUE); // UsbCommand ack = {CMD_ACK, {0, 0, 0}}; for (i = 0; i < NES_MAX_INFO; i++) { if (nvectorcount[i] > 10) continue; for (j = 0; j < nvectorcount[i]; j += 5) { ncount = nvectorcount[i] - j; if (ncount > 5) ncount = 5; // ack.arg[0] = 0; // isEOF = 0 // ack.arg[1] = ncount; // ack.arg[2] = targetBlockNo + (targetKeyType * 0x100); // memset(ack.d.asBytes, 0x00, sizeof(ack.d.asBytes)); byte_t buf[48]; memset(buf, 0x00, sizeof(buf)); memcpy(buf, &cuid, 4); for (m = 0; m < ncount; m++) { memcpy(buf + 8 + m * 8 + 0, &nvector[i][m + j].nt, 4); memcpy(buf + 8 + m * 8 + 4, &nvector[i][m + j].ks1, 4); } LED_B_ON(); cmd_send(CMD_ACK,0,ncount,targetBlockNo + (targetKeyType * 0x100),buf,48); // UsbSendPacket((uint8_t *)&ack, sizeof(UsbCommand)); LED_B_OFF(); } } // finalize list // ack.arg[0] = 1; // isEOF = 1 // ack.arg[1] = 0; // ack.arg[2] = 0; // memset(ack.d.asBytes, 0x00, sizeof(ack.d.asBytes)); LED_B_ON(); // UsbSendPacket((uint8_t *)&ack, sizeof(UsbCommand)); cmd_send(CMD_ACK,1,0,0,0,0); LED_B_OFF(); if (MF_DBGLEVEL >= 4) DbpString("NESTED FINISHED"); // Thats it... FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); LEDsoff(); iso14a_set_tracing(TRUE); } //----------------------------------------------------------------------------- // MIFARE check keys. key count up to 8. // //----------------------------------------------------------------------------- void MifareChkKeys(uint8_t arg0, uint8_t arg1, uint8_t arg2, uint8_t *datain) { // params uint8_t blockNo = arg0; uint8_t keyType = arg1; uint8_t keyCount = arg2; uint64_t ui64Key = 0; // variables int i; byte_t isOK = 0; uint8_t uid[10]; uint32_t cuid; struct Crypto1State mpcs = {0, 0}; struct Crypto1State *pcs; pcs = &mpcs; // clear debug level int OLD_MF_DBGLEVEL = MF_DBGLEVEL; MF_DBGLEVEL = MF_DBG_NONE; // clear trace iso14a_clear_trace(); iso14a_set_tracing(TRUE); iso14443a_setup(); LED_A_ON(); LED_B_OFF(); LED_C_OFF(); SpinDelay(300); for (i = 0; i < keyCount; i++) { FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); SpinDelay(100); FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD); if(!iso14443a_select_card(uid, NULL, &cuid)) { if (OLD_MF_DBGLEVEL >= 1) Dbprintf("Can't select card"); break; }; ui64Key = bytes_to_num(datain + i * 6, 6); if(mifare_classic_auth(pcs, cuid, blockNo, keyType, ui64Key, AUTH_FIRST)) { continue; }; isOK = 1; break; } // ----------------------------- crypto1 destroy crypto1_destroy(pcs); // add trace trailer memset(uid, 0x44, 4); LogTrace(uid, 4, 0, 0, TRUE); // UsbCommand ack = {CMD_ACK, {isOK, 0, 0}}; // if (isOK) memcpy(ack.d.asBytes, datain + i * 6, 6); LED_B_ON(); cmd_send(CMD_ACK,isOK,0,0,datain + i * 6,6); // UsbSendPacket((uint8_t *)&ack, sizeof(UsbCommand)); LED_B_OFF(); // Thats it... FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); LEDsoff(); // restore debug level MF_DBGLEVEL = OLD_MF_DBGLEVEL; } //----------------------------------------------------------------------------- // MIFARE commands set debug level // //----------------------------------------------------------------------------- void MifareSetDbgLvl(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain){ MF_DBGLEVEL = arg0; Dbprintf("Debug level: %d", MF_DBGLEVEL); } //----------------------------------------------------------------------------- // Work with emulator memory // //----------------------------------------------------------------------------- void MifareEMemClr(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain){ emlClearMem(); } void MifareEMemSet(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain){ emlSetMem(datain, arg0, arg1); // data, block num, blocks count } void MifareEMemGet(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain){ // UsbCommand ack = {CMD_ACK, {arg0, arg1, 0}}; byte_t buf[48]; emlGetMem(buf, arg0, arg1); // data, block num, blocks count LED_B_ON(); cmd_send(CMD_ACK,arg0,arg1,0,buf,48); // UsbSendPacket((uint8_t *)&ack, sizeof(UsbCommand)); LED_B_OFF(); } //----------------------------------------------------------------------------- // Load a card into the emulator memory // //----------------------------------------------------------------------------- void MifareECardLoad(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain){ int i; uint8_t sectorNo = 0; uint8_t keyType = arg1; uint64_t ui64Key = 0; uint32_t cuid; struct Crypto1State mpcs = {0, 0}; struct Crypto1State *pcs; pcs = &mpcs; // variables byte_t dataoutbuf[16]; byte_t dataoutbuf2[16]; uint8_t uid[10]; // clear trace iso14a_clear_trace(); iso14a_set_tracing(false); iso14443a_setup(); LED_A_ON(); LED_B_OFF(); LED_C_OFF(); while (true) { if(!iso14443a_select_card(uid, NULL, &cuid)) { if (MF_DBGLEVEL >= 1) Dbprintf("Can't select card"); break; }; for (i = 0; i < 16; i++) { sectorNo = i; ui64Key = emlGetKey(sectorNo, keyType); if (!i){ if(mifare_classic_auth(pcs, cuid, sectorNo * 4, keyType, ui64Key, AUTH_FIRST)) { if (MF_DBGLEVEL >= 1) Dbprintf("Sector[%d]. Auth error", i); break; } } else { if(mifare_classic_auth(pcs, cuid, sectorNo * 4, keyType, ui64Key, AUTH_NESTED)) { if (MF_DBGLEVEL >= 1) Dbprintf("Sector[%d]. Auth nested error", i); break; } } if(mifare_classic_readblock(pcs, cuid, sectorNo * 4 + 0, dataoutbuf)) { if (MF_DBGLEVEL >= 1) Dbprintf("Read block 0 error"); break; }; emlSetMem(dataoutbuf, sectorNo * 4 + 0, 1); if(mifare_classic_readblock(pcs, cuid, sectorNo * 4 + 1, dataoutbuf)) { if (MF_DBGLEVEL >= 1) Dbprintf("Read block 1 error"); break; }; emlSetMem(dataoutbuf, sectorNo * 4 + 1, 1); if(mifare_classic_readblock(pcs, cuid, sectorNo * 4 + 2, dataoutbuf)) { if (MF_DBGLEVEL >= 1) Dbprintf("Read block 2 error"); break; }; emlSetMem(dataoutbuf, sectorNo * 4 + 2, 1); // get block 3 bytes 6-9 if(mifare_classic_readblock(pcs, cuid, sectorNo * 4 + 3, dataoutbuf)) { if (MF_DBGLEVEL >= 1) Dbprintf("Read block 3 error"); break; }; emlGetMem(dataoutbuf2, sectorNo * 4 + 3, 1); memcpy(&dataoutbuf2[6], &dataoutbuf[6], 4); emlSetMem(dataoutbuf2, sectorNo * 4 + 3, 1); } if(mifare_classic_halt(pcs, cuid)) { if (MF_DBGLEVEL >= 1) Dbprintf("Halt error"); break; }; break; } // ----------------------------- crypto1 destroy crypto1_destroy(pcs); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); LEDsoff(); if (MF_DBGLEVEL >= 2) DbpString("EMUL FILL SECTORS FINISHED"); // add trace trailer memset(uid, 0x44, 4); LogTrace(uid, 4, 0, 0, TRUE); } //----------------------------------------------------------------------------- // MIFARE 1k emulator // //----------------------------------------------------------------------------- //----------------------------------------------------------------------------- // Work with "magic Chinese" card (email him: ouyangweidaxian@live.cn) // //----------------------------------------------------------------------------- void MifareCSetBlock(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain){ // params uint8_t needWipe = arg0; // bit 0 - need get UID // bit 1 - need wupC // bit 2 - need HALT after sequence // bit 3 - need init FPGA and field before sequence // bit 4 - need reset FPGA and LED uint8_t workFlags = arg1; uint8_t blockNo = arg2; // card commands uint8_t wupC1[] = { 0x40 }; uint8_t wupC2[] = { 0x43 }; uint8_t wipeC[] = { 0x41 }; // variables byte_t isOK = 0; uint8_t uid[10]; uint8_t d_block[18]; uint32_t cuid; memset(uid, 0x00, 10); uint8_t* receivedAnswer = mifare_get_bigbufptr(); if (workFlags & 0x08) { // clear trace iso14a_clear_trace(); iso14a_set_tracing(TRUE); iso14443a_setup(); LED_A_ON(); LED_B_OFF(); LED_C_OFF(); SpinDelay(300); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); SpinDelay(100); FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD); } while (true) { // get UID from chip if (workFlags & 0x01) { if(!iso14443a_select_card(uid, NULL, &cuid)) { if (MF_DBGLEVEL >= 1) Dbprintf("Can't select card"); break; }; if(mifare_classic_halt(NULL, cuid)) { if (MF_DBGLEVEL >= 1) Dbprintf("Halt error"); break; }; }; // reset chip if (needWipe){ ReaderTransmitBitsPar(wupC1,7,0); if(!ReaderReceive(receivedAnswer) || (receivedAnswer[0] != 0x0a)) { if (MF_DBGLEVEL >= 1) Dbprintf("wupC1 error"); break; }; ReaderTransmit(wipeC, sizeof(wipeC)); if(!ReaderReceive(receivedAnswer) || (receivedAnswer[0] != 0x0a)) { if (MF_DBGLEVEL >= 1) Dbprintf("wipeC error"); break; }; if(mifare_classic_halt(NULL, cuid)) { if (MF_DBGLEVEL >= 1) Dbprintf("Halt error"); break; }; }; // write block if (workFlags & 0x02) { ReaderTransmitBitsPar(wupC1,7,0); if(!ReaderReceive(receivedAnswer) || (receivedAnswer[0] != 0x0a)) { if (MF_DBGLEVEL >= 1) Dbprintf("wupC1 error"); break; }; ReaderTransmit(wupC2, sizeof(wupC2)); if(!ReaderReceive(receivedAnswer) || (receivedAnswer[0] != 0x0a)) { if (MF_DBGLEVEL >= 1) Dbprintf("wupC2 error"); break; }; } if ((mifare_sendcmd_short(NULL, 0, 0xA0, blockNo, receivedAnswer) != 1) || (receivedAnswer[0] != 0x0a)) { if (MF_DBGLEVEL >= 1) Dbprintf("write block send command error"); break; }; memcpy(d_block, datain, 16); AppendCrc14443a(d_block, 16); ReaderTransmit(d_block, sizeof(d_block)); if ((ReaderReceive(receivedAnswer) != 1) || (receivedAnswer[0] != 0x0a)) { if (MF_DBGLEVEL >= 1) Dbprintf("write block send data error"); break; }; if (workFlags & 0x04) { if (mifare_classic_halt(NULL, cuid)) { if (MF_DBGLEVEL >= 1) Dbprintf("Halt error"); break; }; } isOK = 1; break; } // UsbCommand ack = {CMD_ACK, {isOK, 0, 0}}; // if (isOK) memcpy(ack.d.asBytes, uid, 4); // add trace trailer /** * Removed by Martin, the uid is overwritten with 0x44, * which can 't be intended. * * memset(uid, 0x44, 4); * LogTrace(uid, 4, 0, 0, TRUE); **/ LED_B_ON(); cmd_send(CMD_ACK,isOK,0,0,uid,4); // UsbSendPacket((uint8_t *)&ack, sizeof(UsbCommand)); LED_B_OFF(); if ((workFlags & 0x10) || (!isOK)) { // Thats it... FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); LEDsoff(); } } void MifareCGetBlock(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain){ // params // bit 1 - need wupC // bit 2 - need HALT after sequence // bit 3 - need init FPGA and field before sequence // bit 4 - need reset FPGA and LED uint8_t workFlags = arg0; uint8_t blockNo = arg2; // card commands uint8_t wupC1[] = { 0x40 }; uint8_t wupC2[] = { 0x43 }; // variables byte_t isOK = 0; uint8_t data[18]; uint32_t cuid = 0; memset(data, 0x00, 18); uint8_t* receivedAnswer = mifare_get_bigbufptr(); if (workFlags & 0x08) { // clear trace iso14a_clear_trace(); iso14a_set_tracing(TRUE); iso14443a_setup(); LED_A_ON(); LED_B_OFF(); LED_C_OFF(); SpinDelay(300); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); SpinDelay(100); FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD); } while (true) { if (workFlags & 0x02) { ReaderTransmitBitsPar(wupC1,7,0); if(!ReaderReceive(receivedAnswer) || (receivedAnswer[0] != 0x0a)) { if (MF_DBGLEVEL >= 1) Dbprintf("wupC1 error"); break; }; ReaderTransmit(wupC2, sizeof(wupC2)); if(!ReaderReceive(receivedAnswer) || (receivedAnswer[0] != 0x0a)) { if (MF_DBGLEVEL >= 1) Dbprintf("wupC2 error"); break; }; } // read block if ((mifare_sendcmd_short(NULL, 0, 0x30, blockNo, receivedAnswer) != 18)) { if (MF_DBGLEVEL >= 1) Dbprintf("read block send command error"); break; }; memcpy(data, receivedAnswer, 18); if (workFlags & 0x04) { if (mifare_classic_halt(NULL, cuid)) { if (MF_DBGLEVEL >= 1) Dbprintf("Halt error"); break; }; } isOK = 1; break; } // UsbCommand ack = {CMD_ACK, {isOK, 0, 0}}; // if (isOK) memcpy(ack.d.asBytes, data, 18); // add trace trailer /* * Removed by Martin, this piece of overwrites the 'data' variable * which is sent two lines down, and is obviously not correct. * * memset(data, 0x44, 4); * LogTrace(data, 4, 0, 0, TRUE); */ LED_B_ON(); cmd_send(CMD_ACK,isOK,0,0,data,18); // UsbSendPacket((uint8_t *)&ack, sizeof(UsbCommand)); LED_B_OFF(); if ((workFlags & 0x10) || (!isOK)) { // Thats it... FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); LEDsoff(); } } ================================================ FILE: TamagotchiFriends/proxmark/armsrc/mifarecmd.h ================================================ //----------------------------------------------------------------------------- // Merlok - June 2011 // Gerhard de Koning Gans - May 2008 // Hagen Fritsch - June 2010 // // This code is licensed to you under the terms of the GNU GPL, version 2 or, // at your option, any later version. See the LICENSE.txt file for the text of // the license. //----------------------------------------------------------------------------- // Routines to support ISO 14443 type A. //----------------------------------------------------------------------------- #ifndef __MIFARECMD_H #define __MIFARECMD_H #include "proxmark3.h" #include "apps.h" #include "util.h" #include "string.h" #include "iso14443crc.h" #include "iso14443a.h" #include "crapto1.h" #include "mifareutil.h" #include "common.h" #endif ================================================ FILE: TamagotchiFriends/proxmark/armsrc/mifaresniff.c ================================================ //----------------------------------------------------------------------------- // Merlok - 2012 // // This code is licensed to you under the terms of the GNU GPL, version 2 or, // at your option, any later version. See the LICENSE.txt file for the text of // the license. //----------------------------------------------------------------------------- // Routines to support mifare classic sniffer. //----------------------------------------------------------------------------- #include "mifaresniff.h" #include "apps.h" static int sniffState = SNF_INIT; static uint8_t sniffUIDType; static uint8_t sniffUID[8]; static uint8_t sniffATQA[2]; static uint8_t sniffSAK; static uint8_t sniffBuf[16]; static int timerData = 0; int MfSniffInit(void){ rsamples = 0; memset(sniffUID, 0x00, 8); memset(sniffATQA, 0x00, 2); sniffSAK = 0; sniffUIDType = SNF_UID_4; return 0; } int MfSniffEnd(void){ // UsbCommand ack = {CMD_ACK, {0, 0, 0}}; LED_B_ON(); cmd_send(CMD_ACK,0,0,0,0,0); // UsbSendPacket((uint8_t *)&ack, sizeof(UsbCommand)); LED_B_OFF(); return 0; } int RAMFUNC MfSniffLogic(const uint8_t * data, int len, uint32_t parity, int bitCnt, int reader) { if ((len == 1) && (bitCnt = 9) && (data[0] > 0x0F)) { sniffState = SNF_INIT; } switch (sniffState) { case SNF_INIT:{ if ((reader) && (len == 1) && (bitCnt == 9) && ((data[0] == 0x26) || (data[0] == 0x52))) { sniffUIDType = SNF_UID_4; memset(sniffUID, 0x00, 8); memset(sniffATQA, 0x00, 2); sniffSAK = 0; sniffState = SNF_WUPREQ; } break; } case SNF_WUPREQ:{ if ((!reader) && (len == 2)) { memcpy(sniffATQA, data, 2); sniffState = SNF_ATQA; } break; } case SNF_ATQA:{ if ((reader) && (len == 2) && (data[0] == 0x93) && (data[1] == 0x20)) { sniffState = SNF_ANTICOL1; } break; } case SNF_ANTICOL1:{ if ((!reader) && (len == 5) && ((data[0] ^ data[1] ^ data[2] ^ data[3]) == data[4])) { memcpy(sniffUID + 3, data, 4); sniffState = SNF_UID1; } break; } case SNF_UID1:{ if ((reader) && (len == 9) && (data[0] == 0x93) && (data[1] == 0x70) && (CheckCrc14443(CRC_14443_A, data, 9))) { sniffState = SNF_SAK; } break; } case SNF_SAK:{ if ((!reader) && (len == 3) && (CheckCrc14443(CRC_14443_A, data, 3))) { sniffSAK = data[0]; if (sniffUID[3] == 0x88) { sniffState = SNF_ANTICOL2; } else { sniffState = SNF_CARD_IDLE; } } break; } case SNF_ANTICOL2:{ if ((!reader) && (len == 5) && ((data[0] ^ data[1] ^ data[2] ^ data[3]) == data[4])) { memcpy(sniffUID, data, 4); sniffUIDType = SNF_UID_7; sniffState = SNF_UID2; } break; } case SNF_UID2:{ if ((reader) && (len == 9) && (data[0] == 0x95) && (data[1] == 0x70) && (CheckCrc14443(CRC_14443_A, data, 9))) { sniffState = SNF_SAK; Dbprintf("SNF_SAK"); } break; } case SNF_CARD_IDLE:{ sniffBuf[0] = 0xFF; sniffBuf[1] = 0xFF; memcpy(sniffBuf + 2, sniffUID, 7); memcpy(sniffBuf + 9, sniffATQA, 2); sniffBuf[11] = sniffSAK; sniffBuf[12] = 0xFF; sniffBuf[13] = 0xFF; LogTrace(sniffBuf, 14, 0, parity, true); timerData = GetTickCount(); } case SNF_CARD_CMD:{ LogTrace(data, len, 0, parity, true); sniffState = SNF_CARD_RESP; timerData = GetTickCount(); break; } case SNF_CARD_RESP:{ LogTrace(data, len, 0, parity, false); sniffState = SNF_CARD_CMD; timerData = GetTickCount(); break; } default: sniffState = SNF_INIT; break; } return 0; } int RAMFUNC MfSniffSend(int maxTimeoutMs) { if (traceLen && (timerData + maxTimeoutMs < GetTickCount())) { return intMfSniffSend(); } return 0; } // internal seding function. not a RAMFUNC. int intMfSniffSend() { int pckSize = 0; int pckLen = traceLen; int pckNum = 0; if (!traceLen) return 0; FpgaDisableSscDma(); while (pckLen > 0) { pckSize = MIN(32, pckLen); // UsbCommand ack = {CMD_ACK, {1, pckSize, pckNum}}; // memcpy(ack.d.asBytes, trace + traceLen - pckLen, pckSize); LED_B_ON(); cmd_send(CMD_ACK,1,pckSize,pckNum,trace + traceLen - pckLen,pckSize); // UsbSendPacket((uint8_t *)&ack, sizeof(UsbCommand)); // SpinDelay(20); LED_B_OFF(); pckLen -= pckSize; pckNum++; } // UsbCommand ack = {CMD_ACK, {2, 0, 0}}; LED_B_ON(); cmd_send(CMD_ACK,2,0,0,0,0); // UsbSendPacket((uint8_t *)&ack, sizeof(UsbCommand)); LED_B_OFF(); traceLen = 0; memset(trace, 0x44, TRACE_SIZE); return 1; } ================================================ FILE: TamagotchiFriends/proxmark/armsrc/mifaresniff.h ================================================ //----------------------------------------------------------------------------- // Merlok - June 2012 // // This code is licensed to you under the terms of the GNU GPL, version 2 or, // at your option, any later version. See the LICENSE.txt file for the text of // the license. //----------------------------------------------------------------------------- // Routines to support mifare classic sniffer. //----------------------------------------------------------------------------- #ifndef __MIFARESNIFF_H #define __MIFARESNIFF_H #include "proxmark3.h" #include "apps.h" #include "util.h" #include "string.h" #include "iso14443crc.h" #include "iso14443a.h" #include "crapto1.h" #include "mifareutil.h" #include "common.h" #define SNF_INIT 0 #define SNF_NO_FIELD 1 #define SNF_WUPREQ 2 #define SNF_ATQA 3 #define SNF_ANTICOL1 4 #define SNF_UID1 5 #define SNF_ANTICOL2 6 #define SNF_UID2 7 #define SNF_SAK 8 #define SNF_CARD_IDLE 9 #define SNF_CARD_CMD 10 #define SNF_CARD_RESP 11 #define SNF_UID_4 0 #define SNF_UID_7 0 int MfSniffInit(void); int RAMFUNC MfSniffLogic(const uint8_t * data, int len, uint32_t parity, int bitCnt, int reader); int RAMFUNC MfSniffSend(int maxTimeoutMs); int intMfSniffSend(); int MfSniffEnd(void); #endif ================================================ FILE: TamagotchiFriends/proxmark/armsrc/mifareutil.c ================================================ //----------------------------------------------------------------------------- // Merlok, May 2011, 2012 // Many authors, whom made it possible // // This code is licensed to you under the terms of the GNU GPL, version 2 or, // at your option, any later version. See the LICENSE.txt file for the text of // the license. //----------------------------------------------------------------------------- // Work with mifare cards. //----------------------------------------------------------------------------- #include "proxmark3.h" #include "apps.h" #include "util.h" #include "string.h" #include "iso14443crc.h" #include "iso14443a.h" #include "crapto1.h" #include "mifareutil.h" int MF_DBGLEVEL = MF_DBG_ALL; // memory management uint8_t* mifare_get_bigbufptr(void) { return (((uint8_t *)BigBuf) + MIFARE_BUFF_OFFSET); // was 3560 - tied to other size changes } uint8_t* eml_get_bigbufptr_sendbuf(void) { return (((uint8_t *)BigBuf) + RECV_CMD_OFFSET); } uint8_t* eml_get_bigbufptr_recbuf(void) { return (((uint8_t *)BigBuf) + MIFARE_BUFF_OFFSET); } uint8_t* eml_get_bigbufptr_cardmem(void) { return (((uint8_t *)BigBuf) + CARD_MEMORY); } // crypto1 helpers void mf_crypto1_decrypt(struct Crypto1State *pcs, uint8_t *data, int len){ uint8_t bt = 0; int i; if (len != 1) { for (i = 0; i < len; i++) data[i] = crypto1_byte(pcs, 0x00, 0) ^ data[i]; } else { bt = 0; for (i = 0; i < 4; i++) bt |= (crypto1_bit(pcs, 0, 0) ^ BIT(data[0], i)) << i; data[0] = bt; } return; } void mf_crypto1_encrypt(struct Crypto1State *pcs, uint8_t *data, int len, uint32_t *par) { uint8_t bt = 0; int i; uint32_t mltpl = 1 << (len - 1); // for len=18 it=0x20000 *par = 0; for (i = 0; i < len; i++) { bt = data[i]; data[i] = crypto1_byte(pcs, 0x00, 0) ^ data[i]; *par = (*par >> 1) | ( ((filter(pcs->odd) ^ oddparity(bt)) & 0x01) * mltpl ); } return; } uint8_t mf_crypto1_encrypt4bit(struct Crypto1State *pcs, uint8_t data) { uint8_t bt = 0; int i; for (i = 0; i < 4; i++) bt |= (crypto1_bit(pcs, 0, 0) ^ BIT(data, i)) << i; return bt; } // send commands int mifare_sendcmd_short(struct Crypto1State *pcs, uint8_t crypted, uint8_t cmd, uint8_t data, uint8_t* answer) { return mifare_sendcmd_shortex(pcs, crypted, cmd, data, answer, NULL); } int mifare_sendcmd_shortex(struct Crypto1State *pcs, uint8_t crypted, uint8_t cmd, uint8_t data, uint8_t* answer, uint32_t * parptr) { uint8_t dcmd[4], ecmd[4]; uint32_t pos, par, res; dcmd[0] = cmd; dcmd[1] = data; AppendCrc14443a(dcmd, 2); memcpy(ecmd, dcmd, sizeof(dcmd)); if (crypted) { par = 0; for (pos = 0; pos < 4; pos++) { ecmd[pos] = crypto1_byte(pcs, 0x00, 0) ^ dcmd[pos]; par = (par >> 1) | ( ((filter(pcs->odd) ^ oddparity(dcmd[pos])) & 0x01) * 0x08 ); } ReaderTransmitPar(ecmd, sizeof(ecmd), par); } else { ReaderTransmit(dcmd, sizeof(dcmd)); } int len = ReaderReceivePar(answer, &par); if (parptr) *parptr = par; if (crypted == CRYPT_ALL) { if (len == 1) { res = 0; for (pos = 0; pos < 4; pos++) res |= (crypto1_bit(pcs, 0, 0) ^ BIT(answer[0], pos)) << pos; answer[0] = res; } else { for (pos = 0; pos < len; pos++) { answer[pos] = crypto1_byte(pcs, 0x00, 0) ^ answer[pos]; } } } return len; } // mifare commands int mifare_classic_auth(struct Crypto1State *pcs, uint32_t uid, uint8_t blockNo, uint8_t keyType, uint64_t ui64Key, uint64_t isNested) { return mifare_classic_authex(pcs, uid, blockNo, keyType, ui64Key, isNested, NULL); } int mifare_classic_authex(struct Crypto1State *pcs, uint32_t uid, uint8_t blockNo, uint8_t keyType, uint64_t ui64Key, uint64_t isNested, uint32_t * ntptr) { // variables int len; uint32_t pos; uint8_t tmp4[4]; byte_t par = 0; byte_t ar[4]; uint32_t nt, ntpp; // Supplied tag nonce uint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 }; uint8_t* receivedAnswer = mifare_get_bigbufptr(); // Transmit MIFARE_CLASSIC_AUTH len = mifare_sendcmd_short(pcs, isNested, 0x60 + (keyType & 0x01), blockNo, receivedAnswer); if (MF_DBGLEVEL >= 4) Dbprintf("rand nonce len: %x", len); if (len != 4) return 1; ar[0] = 0x55; ar[1] = 0x41; ar[2] = 0x49; ar[3] = 0x92; // Save the tag nonce (nt) nt = bytes_to_num(receivedAnswer, 4); // ----------------------------- crypto1 create if (isNested) crypto1_destroy(pcs); // Init cipher with key crypto1_create(pcs, ui64Key); if (isNested == AUTH_NESTED) { // decrypt nt with help of new key nt = crypto1_word(pcs, nt ^ uid, 1) ^ nt; } else { // Load (plain) uid^nt into the cipher crypto1_word(pcs, nt ^ uid, 0); } // some statistic if (!ntptr && (MF_DBGLEVEL >= 3)) Dbprintf("auth uid: %08x nt: %08x", uid, nt); // save Nt if (ntptr) *ntptr = nt; par = 0; // Generate (encrypted) nr+parity by loading it into the cipher (Nr) for (pos = 0; pos < 4; pos++) { mf_nr_ar[pos] = crypto1_byte(pcs, ar[pos], 0) ^ ar[pos]; par = (par >> 1) | ( ((filter(pcs->odd) ^ oddparity(ar[pos])) & 0x01) * 0x80 ); } // Skip 32 bits in pseudo random generator nt = prng_successor(nt,32); // ar+parity for (pos = 4; pos < 8; pos++) { nt = prng_successor(nt,8); mf_nr_ar[pos] = crypto1_byte(pcs,0x00,0) ^ (nt & 0xff); par = (par >> 1)| ( ((filter(pcs->odd) ^ oddparity(nt & 0xff)) & 0x01) * 0x80 ); } // Transmit reader nonce and reader answer ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par); // Receive 4 bit answer len = ReaderReceive(receivedAnswer); if (!len) { if (MF_DBGLEVEL >= 1) Dbprintf("Authentication failed. Card timeout."); return 2; } memcpy(tmp4, receivedAnswer, 4); ntpp = prng_successor(nt, 32) ^ crypto1_word(pcs, 0,0); if (ntpp != bytes_to_num(tmp4, 4)) { if (MF_DBGLEVEL >= 1) Dbprintf("Authentication failed. Error card response."); return 3; } return 0; } int mifare_classic_readblock(struct Crypto1State *pcs, uint32_t uid, uint8_t blockNo, uint8_t *blockData) { // variables int len; uint8_t bt[2]; uint8_t* receivedAnswer = mifare_get_bigbufptr(); // command MIFARE_CLASSIC_READBLOCK len = mifare_sendcmd_short(pcs, 1, 0x30, blockNo, receivedAnswer); if (len == 1) { if (MF_DBGLEVEL >= 1) Dbprintf("Cmd Error: %02x", receivedAnswer[0]); return 1; } if (len != 18) { if (MF_DBGLEVEL >= 1) Dbprintf("Cmd Error: card timeout. len: %x", len); return 2; } memcpy(bt, receivedAnswer + 16, 2); AppendCrc14443a(receivedAnswer, 16); if (bt[0] != receivedAnswer[16] || bt[1] != receivedAnswer[17]) { if (MF_DBGLEVEL >= 1) Dbprintf("Cmd CRC response error."); return 3; } memcpy(blockData, receivedAnswer, 16); return 0; } int mifare_classic_writeblock(struct Crypto1State *pcs, uint32_t uid, uint8_t blockNo, uint8_t *blockData) { // variables int len, i; uint32_t pos; uint32_t par = 0; byte_t res; uint8_t d_block[18], d_block_enc[18]; uint8_t* receivedAnswer = mifare_get_bigbufptr(); // command MIFARE_CLASSIC_WRITEBLOCK len = mifare_sendcmd_short(pcs, 1, 0xA0, blockNo, receivedAnswer); if ((len != 1) || (receivedAnswer[0] != 0x0A)) { // 0x0a - ACK if (MF_DBGLEVEL >= 1) Dbprintf("Cmd Error: %02x", receivedAnswer[0]); return 1; } memcpy(d_block, blockData, 16); AppendCrc14443a(d_block, 16); // crypto par = 0; for (pos = 0; pos < 18; pos++) { d_block_enc[pos] = crypto1_byte(pcs, 0x00, 0) ^ d_block[pos]; par = (par >> 1) | ( ((filter(pcs->odd) ^ oddparity(d_block[pos])) & 0x01) * 0x20000 ); } ReaderTransmitPar(d_block_enc, sizeof(d_block_enc), par); // Receive the response len = ReaderReceive(receivedAnswer); res = 0; for (i = 0; i < 4; i++) res |= (crypto1_bit(pcs, 0, 0) ^ BIT(receivedAnswer[0], i)) << i; if ((len != 1) || (res != 0x0A)) { if (MF_DBGLEVEL >= 1) Dbprintf("Cmd send data2 Error: %02x", res); return 2; } return 0; } int mifare_classic_halt(struct Crypto1State *pcs, uint32_t uid) { // variables int len; // Mifare HALT uint8_t* receivedAnswer = mifare_get_bigbufptr(); len = mifare_sendcmd_short(pcs, pcs == NULL ? 0:1, 0x50, 0x00, receivedAnswer); if (len != 0) { if (MF_DBGLEVEL >= 1) Dbprintf("halt error. response len: %x", len); return 1; } return 0; } // work with emulator memory void emlSetMem(uint8_t *data, int blockNum, int blocksCount) { uint8_t* emCARD = eml_get_bigbufptr_cardmem(); memcpy(emCARD + blockNum * 16, data, blocksCount * 16); } void emlGetMem(uint8_t *data, int blockNum, int blocksCount) { uint8_t* emCARD = eml_get_bigbufptr_cardmem(); memcpy(data, emCARD + blockNum * 16, blocksCount * 16); } void emlGetMemBt(uint8_t *data, int bytePtr, int byteCount) { uint8_t* emCARD = eml_get_bigbufptr_cardmem(); memcpy(data, emCARD + bytePtr, byteCount); } int emlCheckValBl(int blockNum) { uint8_t* emCARD = eml_get_bigbufptr_cardmem(); uint8_t* data = emCARD + blockNum * 16; if ((data[0] != (data[4] ^ 0xff)) || (data[0] != data[8]) || (data[1] != (data[5] ^ 0xff)) || (data[1] != data[9]) || (data[2] != (data[6] ^ 0xff)) || (data[2] != data[10]) || (data[3] != (data[7] ^ 0xff)) || (data[3] != data[11]) || (data[12] != (data[13] ^ 0xff)) || (data[12] != data[14]) || (data[12] != (data[15] ^ 0xff)) ) return 1; return 0; } int emlGetValBl(uint32_t *blReg, uint8_t *blBlock, int blockNum) { uint8_t* emCARD = eml_get_bigbufptr_cardmem(); uint8_t* data = emCARD + blockNum * 16; if (emlCheckValBl(blockNum)) { return 1; } memcpy(blReg, data, 4); *blBlock = data[12]; return 0; } int emlSetValBl(uint32_t blReg, uint8_t blBlock, int blockNum) { uint8_t* emCARD = eml_get_bigbufptr_cardmem(); uint8_t* data = emCARD + blockNum * 16; memcpy(data + 0, &blReg, 4); memcpy(data + 8, &blReg, 4); blReg = blReg ^ 0xffffffff; memcpy(data + 4, &blReg, 4); data[12] = blBlock; data[13] = blBlock ^ 0xff; data[14] = blBlock; data[15] = blBlock ^ 0xff; return 0; } uint64_t emlGetKey(int sectorNum, int keyType) { uint8_t key[6]; uint8_t* emCARD = eml_get_bigbufptr_cardmem(); memcpy(key, emCARD + 3 * 16 + sectorNum * 4 * 16 + keyType * 10, 6); return bytes_to_num(key, 6); } void emlClearMem(void) { int b; const uint8_t trailer[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07, 0x80, 0x69, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; const uint8_t uid[] = {0xe6, 0x84, 0x87, 0xf3, 0x16, 0x88, 0x04, 0x00, 0x46, 0x8e, 0x45, 0x55, 0x4d, 0x70, 0x41, 0x04}; uint8_t* emCARD = eml_get_bigbufptr_cardmem(); memset(emCARD, 0, CARD_MEMORY_LEN); // fill sectors trailer data for(b = 3; b < 256; b<127?(b+=4):(b+=16)) { emlSetMem((uint8_t *)trailer, b , 1); } // uid emlSetMem((uint8_t *)uid, 0, 1); return; } ================================================ FILE: TamagotchiFriends/proxmark/armsrc/mifareutil.h ================================================ //----------------------------------------------------------------------------- // Merlok, May 2011 // Many authors, that makes it possible // // This code is licensed to you under the terms of the GNU GPL, version 2 or, // at your option, any later version. See the LICENSE.txt file for the text of // the license. //----------------------------------------------------------------------------- // code for work with mifare cards. //----------------------------------------------------------------------------- #ifndef __MIFAREUTIL_H #define __MIFAREUTIL_H // mifare authentication #define CRYPT_NONE 0 #define CRYPT_ALL 1 #define CRYPT_REQUEST 2 #define AUTH_FIRST 0 #define AUTH_NESTED 2 // mifare 4bit card answers #define CARD_ACK 0x0A // 1010 - ACK #define CARD_NACK_NA 0x04 // 0100 - NACK, not allowed (command not allowed) #define CARD_NACK_TR 0x05 // 0101 - NACK, transmission error // reader voltage field detector #define MF_MINFIELDV 4000 // debug // 0 - no debug messages 1 - error messages 2 - all messages 4 - extended debug mode #define MF_DBG_NONE 0 #define MF_DBG_ERROR 1 #define MF_DBG_ALL 2 #define MF_DBG_EXTENDED 4 extern int MF_DBGLEVEL; //mifare nested #define MEM_CHUNK 10000 #define TRY_KEYS 50 #define NS_TOLERANCE 10 // [distance avg-value, distance avg+value] #define NS_RETRIES_GETNONCE 15 #define NES_MAX_INFO 5 //mifare emulator states #define MFEMUL_NOFIELD 0 #define MFEMUL_IDLE 1 #define MFEMUL_SELECT1 2 #define MFEMUL_SELECT2 3 #define MFEMUL_AUTH1 4 #define MFEMUL_AUTH2 5 #define MFEMUL_WORK 6 #define MFEMUL_WRITEBL2 7 #define MFEMUL_INTREG_INC 8 #define MFEMUL_INTREG_DEC 9 #define MFEMUL_INTREG_REST 10 #define MFEMUL_HALTED 11 #define cardSTATE_TO_IDLE() cardSTATE = MFEMUL_IDLE; LED_B_OFF(); LED_C_OFF(); //functions uint8_t* mifare_get_bigbufptr(void); int mifare_sendcmd_short(struct Crypto1State *pcs, uint8_t crypted, uint8_t cmd, uint8_t data, uint8_t* answer); int mifare_sendcmd_shortex(struct Crypto1State *pcs, uint8_t crypted, uint8_t cmd, uint8_t data, uint8_t* answer, uint32_t * parptr); int mifare_classic_auth(struct Crypto1State *pcs, uint32_t uid, \ uint8_t blockNo, uint8_t keyType, uint64_t ui64Key, uint64_t isNested); int mifare_classic_authex(struct Crypto1State *pcs, uint32_t uid, \ uint8_t blockNo, uint8_t keyType, uint64_t ui64Key, uint64_t isNested, uint32_t * ntptr); int mifare_classic_readblock(struct Crypto1State *pcs, uint32_t uid, uint8_t blockNo, uint8_t *blockData); int mifare_classic_writeblock(struct Crypto1State *pcs, uint32_t uid, uint8_t blockNo, uint8_t *blockData); int mifare_classic_halt(struct Crypto1State *pcs, uint32_t uid); // crypto functions void mf_crypto1_decrypt(struct Crypto1State *pcs, uint8_t *receivedCmd, int len); void mf_crypto1_encrypt(struct Crypto1State *pcs, uint8_t *data, int len, uint32_t *par); uint8_t mf_crypto1_encrypt4bit(struct Crypto1State *pcs, uint8_t data); // memory management uint8_t* mifare_get_bigbufptr(void); uint8_t* eml_get_bigbufptr_sendbuf(void); uint8_t* eml_get_bigbufptr_recbuf(void); // emulator functions void emlClearMem(void); void emlSetMem(uint8_t *data, int blockNum, int blocksCount); void emlGetMem(uint8_t *data, int blockNum, int blocksCount); void emlGetMemBt(uint8_t *data, int bytePtr, int byteCount); uint64_t emlGetKey(int sectorNum, int keyType); int emlGetValBl(uint32_t *blReg, uint8_t *blBlock, int blockNum); int emlSetValBl(uint32_t blReg, uint8_t blBlock, int blockNum); int emlCheckValBl(int blockNum); #endif ================================================ FILE: TamagotchiFriends/proxmark/armsrc/obj/appmain.d ================================================ obj/appmain.d obj/appmain.o: appmain.c ../common/usb_cdc.h \ ../include/common.h stdint.h ../include/at91sam7s512.h ../common/cmd.h \ ../include/usb_cmd.h ../common/usb_cdc.h ../include/proxmark3.h \ ../include/at91sam7s512.h ../include/config_gpio.h apps.h \ ../include/hitag2.h ../include/mifare.h ../include/common.h util.h \ printf.h string.h legicrf.h ================================================ FILE: TamagotchiFriends/proxmark/armsrc/obj/cmd.d ================================================ obj/cmd.d obj/cmd.o: ../common/cmd.c ../common/cmd.h ../include/common.h \ stdint.h ../include/at91sam7s512.h ../include/usb_cmd.h \ ../common/usb_cdc.h string.h ../include/proxmark3.h \ ../include/at91sam7s512.h ../include/config_gpio.h ================================================ FILE: TamagotchiFriends/proxmark/armsrc/obj/crapto1.d ================================================ obj/crapto1.d obj/crapto1.o: crapto1.c crapto1.h stdint.h ================================================ FILE: TamagotchiFriends/proxmark/armsrc/obj/crc.d ================================================ obj/crc.d obj/crc.o: ../common/crc.c ../include/crc.h stdint.h ================================================ FILE: TamagotchiFriends/proxmark/armsrc/obj/crc16.d ================================================ obj/crc16.d obj/crc16.o: ../common/crc16.c ../common/crc16.h ================================================ FILE: TamagotchiFriends/proxmark/armsrc/obj/crypto1.d ================================================ obj/crypto1.d obj/crypto1.o: crypto1.c crapto1.h stdint.h ================================================ FILE: TamagotchiFriends/proxmark/armsrc/obj/epa.d ================================================ obj/epa.d obj/epa.o: epa.c iso14443a.h ../include/common.h stdint.h \ ../include/at91sam7s512.h mifaresniff.h ../include/proxmark3.h \ ../include/at91sam7s512.h ../include/config_gpio.h ../include/usb_cmd.h \ apps.h ../include/hitag2.h ../include/mifare.h ../include/common.h \ util.h string.h ../common/iso14443crc.h crapto1.h mifareutil.h epa.h \ ../common/cmd.h ../common/usb_cdc.h ================================================ FILE: TamagotchiFriends/proxmark/armsrc/obj/fpgaimage.s19 ================================================ S01400006F626A2F66706761696D6167652E733139D5 S3150000200000090FF00FF00FF00FF000000161001053 S31500002010667067612D706C616365642E6E63640023 S3150000202062000A3273333076713130300063000B50 S31500002030323031322F20312F2036006400093135FD S315000020403A32373A353600650000A470FFFFFFFFCD S31500002050AA99556630008001000000073001600132 S31500002060000000083001200100803F2D3000C00133 S31500002070000000003000800100000009300020014F S315000020800000000030008001000000013000400028 S315000020905000246300121000000000000000000041 S315000020A0000000000000000000000000000000002A S315000020B00000048000000000001210000000000074 S315000020C0000000000000000000000000000000000A S315000020D0000000000000048000000000090300006A S315000020E000000000000000000000000000000000EA S315000020F0000000000000000000004080000000001A S3150000210000020000000000000000000000000000C7 S315000021100000000000000000000000000000008039 S315000021200000000000120000000000000000000097 S315000021300000000000000000000000000000000099 S31500002140000004A0000000000012000000000000D3 S315000021500000000000000000000000000000000079 S315000021600000000000000480000000000012400093 S315000021700000000000000000000000000000000059 S315000021800000000000000000000004E00000000065 S31500002190F6100060001800060001800060001900BB S315000021A0068003800068003B800E8007203F842065 S315000021B000000000C001FA40E7803FC20CD0833621 S315000021C0007F0033C00CF1033C01CE8033E00CE20B S315000021D002300070000000008010E8808B802EF036 S315000021E00894022600B7C02BF008F7021D428202AF S315000021F022C008610A200430000000008805C800DB S31500002200A1002C600A92820400BB4222C40830025C S315000022100C00828022C0082002220170000000000B S31500002220C015AA008B802EC00AA0822C84B3002A77 S31500002230C108B0020C008A8022C80820023004605F S31500002240000000000015EA20EBE03E800E98012415 S3150000225000FB0230C02CD8032C008A8032C02CA090 S315000022600310047000000000E001B804FF003FC046 S315000022700D990BFE28FF003FC00F9903FC00FE00DE S31500002280BFE00FE003F80060000000004010A80067 S31500002290DB02328C0FB4832400FB0032C00F100324 S315000022A02C00CA0C32C00CA1031004200000000050 S315000022B0C8052A008B0020900326022700BFC037DE S315000022C0DC4B90223C00CA0020C028E402320040C9 S315000022D000000000E00568809300A0C11314468743 S315000022E000B3D820C00B10020C008A0024C00828B6 S315000022F0027900500000000020011A048F8021E0BE S315000023000B59029620BF9065E40B58021E4096902A S31500002310A5E4086C024800400000000048082C6054 S31500002320D02030480B310B8C04F300B0C00F1003E3 S315000023300C00C21036C02C200B5202000000000018 S31500002340400DBC50FE003FC007E1437C00FF453F07 S31500002350C00FD903FC12EE143BC00FE103900260DC S3150000236000000000A855EC08F8003E990F8003AC69 S3150000237000FBA0B2F82CB2032C02CB0132522CA2E5 S31500002380832A00700000000048119400B6002DC298 S315000023908B50431C08B74021DA0870823DC0860185 S315000023A061C008640212046000000000C0009E20A4 S315000023B0B4886DE00B2802D600B3A024E0083802EA S315000023C01E11878021E0086802300020000000000E S315000023D04814EC00B2082CD80BAF020600B3002458 S315000023E0C00838022C0580E022E088200212043062 S315000023F000000000E805B840FE403E800FE403EA16 S3150000240020FA0036800CAA0B2800CEC1A2A00CE050 S315000024100B3A0460000000004800E000F8002E04BB S315000024200F8003E000F8043A000F0003E000F81004 S315000024303E044F0003D20030000000000800E4080C S31500002440D9223EF04F98032440C9003E500B90031A S315000024502400C90032E80C9003020430000000009A S315000024608044678089832E420B9802870089402E1C S31500002470480990022500C900226088908AA00010B1 S31500002480000000001805260099002E400B95022436 S315000024902089086E404B90222502810022408890B8 S315000024A002060040000000000814050081002C40D0 S315000024B00B1402A40081002C4009140204008100C0 S315000024C0204008100282010000000000B80D6000E4 S315000024D0D8003E200B88132002C8803E200F880BB0 S315000024E02200C000B0002C02832E03500000000022 S315000024F09815F614FD003E500FDC03F400F9403F3A S31500002500500FDC03E5A0ED28BE4A0FD283E6067025 S31500002510000000001801F400CD00B3406CD0032485 S3150000252000B90032400F9803A410C90032400C9441 S3150000253003060070000000003810E000880022004A S315000025408C800A2018B00237000B8502228288A1EF S31500002550222888C8020E0430000000000805C400C6 S31500002560890028400818420400BD0021400B1002D3 S3150000257014209508A14228500202017000000000B4 S315000025801815A4808B802A428890022400B5002763 S31500002590400B900284009D00214000D0020604609A S315000025A000000000A014A782C1E03A700C98032630 S315000025B040F900B2400F900B2400D98032600C9095 S315000025C00B280470000000002800A400F90036441F S315000025D00E9273EC00F9003E400F90036400E92070 S315000025E03E500F9003CA0060000000002810A200B1 S315000025F0F8003C120C82432000FC0032000F00035E S31500002600E000C80032000CC0030A042000000000ED S3150000261028043820BEC00FB208E64A2A20BA003E77 S31500002620B80BA000E8008A0022800AE80A8A004067 S315000026300000000028056C00B1222CC0B8A00206DC S3150000264000B00020284B3000CE008B8020C00AA8A6 S31500002650220A00500000000020011C04B5402D8015 S315000026600850021400BE002DC00B7002DD0086402B S3150000267023C02A2082A800400000000028081E006F S31500002680F5803CE00CE8031A00F58031E00F788312 S31500002690FA02CF80B1600E78032A02000000000023 S315000026A0081DA400F9003E800F9003E8B0FB003E31 S315000026B0C00FB303E802FA003C402FB003C2066025 S315000026C0000000004005FE00FC903FE40FF81B3EB2 S315000026D010CC8033E00CF8033600CD8033E00FC811 S315000026E02300007000000000A8119400B4102D0E05 S315000026F00BD2021C00861421D0087102140084102B S3150000270021C04BC0022A04600000000000009800AF S31500002710B4112DD01B50421000810020C008700259 S3150000272010008D0021420B5802000020000000001E S315000027306014E200B0802C800B90020240830020DF S31500002740C008B0020000881020400B1002080430B8 S3150000275000000000A815A480F9083EF00F8A0324A3 S3150000276002C90232C00CF0022C00CB8030A00FA0B0 S315000027700B2A0460000000008000E100F9442E806E S315000027800F9043E000FB403EC00FB003CC00FA00C0 S315000027903E900FA003E00030000000000110F4009E S315000027A0CFC033010FD0833840FD00B3C00FF00314 S315000027B02800CF0833000CF003004430000000006E S315000027C08104622083C02A200B988A2000BB402205 S315000027D0D04BB00A38028E01A31108700A204010AF S315000027E000000000800566008B0222A20B98022CD6 S315000027F020B10822E00BB002240089002282088062 S3150000280002200040000000000800000083002800AD S315000028100B10020000BB0020C00B30020400800039 S31500002820228008800202010000000000000860000B S31500002830CB0032000F90032000F90232C00F700760 S315000028402000C90032008C900300035000000000F5 S31500002850A00DF002FF003F000FD023D000FF003F85 S31500002860C00FF003F000F4003F000FD003E806703D S3150000287000000000C005FC00CF0033000D580336F1 S3150000288004FC8033200CF0031A02CF0833E80CE96D S3150000289003300070000000008010EC648A5A222089 S315000028A00B98036200B8002248089D02AC208BC03A S315000028B035D508E902200430000000008805CC80E8 S315000028C0A02420200B300A0400B100204208100288 S315000028D02C80830020CA08200A2201700000000014 S315000028E0C015AC00A90822200B90006220B9000296 S315000028F040089002AC008B0026C0282002300460FD S31500002900000000004015EC08CC4032000D100122FA S3150000291000F9A032602C71030880CB0032C00CA0F5 S315000029200B10047000000000E001AC005020BFC096 S3150000293003D043F000FDC03F040F9803FE80FB0068 S315000029403DC00FA003F90060000000004010AC007D S31500002950CB5032000FB2032820F9443E400C9003BE S315000029602D00CB0032C14CA00B100420000000004B S31500002970C8053C008B80222C0B9E0A2900B9102E1C S31500002980414D91022C00878023C04AE00A32004064 S3150000299000000000E0056C10000020E00B14028F20 S315000029A040B8502E4008140A0C00838020C008202E S315000029B0027800500000000020011E008480216182 S315000029C00B59029E00B4902F600978023E02879848 S315000029D021E00A69024800400000000048080C4057 S315000029E08320B0C40F31038C00F1103C000C30037F S315000029F00C44C300B0C00C200352020000000000CB S31500002A00401DBC10FF003FC00FD1037C407D113D2F S31500002A10400FF103FC00FF003FC40FE00390066087 S31500002A2000000000A805EC00E80032800F90132E8D S31500002A3000C98032400F10032C00FB1032C80C2353 S31500002A40032A00700000000048119D00B400A1C4D4 S31500002A500B50035C008D0021400B70021400B78000 S31500002A602BC20D610A12046000000000C0009E80A7 S31500002A70B780A1E00B78021F00858021600B7802E9 S31500002A801F00B38061E408EA027000200000000025 S31500002A904814CC00B34020D90B10024D0082882088 S31500002AA0800B301A0600B30028C0292002520410F9 S31500002AB000000000E815A800FE00B2804F20023991 S31500002AC002CE60B3980F20031A00FA0032800CE0A1 S31500002AD0037A0460000000004800E000F818BE1009 S31500002AE00F8413E000F8003E020F8003E000F800B8 S31500002AF03C000F8003920030000000000810E40044 S31500002B00F19032C00F90132420F9803E400C9C4374 S31500002B102400C120B240AC900B020430000000003B S31500002B2080046400B90022600B9602A500B9D02C7F S31500002B30400A9C02240089003240089002200010BE S31500002B400000000018052400B900A2440B912224BD S31500002B5060B9402EC0189402240089002240281033 S31500002B60020600400000000008040500B1402040B5 S31500002B704B10028400B1442E500A100225009328FF S31500002B80204608120202010000000000B80D620093 S31500002B90F08032A04F80022000F8003E000C880B27 S31500002BA02002C82032100C83032E035000000000C0 S31500002BB0981DE700FDC03E504F5003D400FD843FF2 S31500002BC0600BD403F600E9013A49039303E6067065 S31500002BD0000000001805E400FD80B3C083500334F4 S31500002BE000FD0432404CD8132504ED0232400C900F S31500002BF053061270000000003810E000BAE222000E S31500002C000B80022000B800A0800D800A2A008801EF S31500002C1036000880020E0030000000000805C400DF S31500002C20B14820610B104A0400B100224108140289 S31500002C300400A100204008100202017000000000FC S31500002C401811A400B90022618B98022C00BB002247 S31500002C504009980224008900264008901206046064 S31500002C6000000000A011E400F9C0B2600F180324B0 S31500002C7040F96030700C90032400E90032402C903B S31500002C800B280470000000002801A400F9203E4033 S31500002C904B9003E600F9203E640F1003E400F100B8 S31500002CA03C402F9003CA0060000000002810A000DE S31500002CB0E840B2020F81832080C8483E102C88036A S31500002CC0E000F8003E012C80030A0420000000000A S31500002CD028052800BA0023988BE813F800DE882E12 S31500002CE08008E002E800BE202E8008A0020A1040FC S31500002CF00000000028054C01BB0060D00338060F19 S31500002D00008A022CC0083102EC00B3082CC008B0BF S31500002D10028A005000000000A0011C41B50021807D S31500002D208B7016DF1097042DC8087002DC00B50002 S31500002D302DC008700228004000000000A8081E8070 S31500002D40E19431A00F78031E00C6803DF00C780395 S31500002D50DE00F6803CF00CF80BAA00000000000034 S31500002D60081DAC08FB60BE804FB003C404F9013EE9 S31500002D70C84FB003FE00FA003ECA0FB783C2146004 S31500002D80000000000005FE01FF9033E10CF8033E51 S31500002D9000F79013F00CF903FE00FE8033E08CF888 S31500002DA04300007000000000A8119C00B53021848B S31500002DB00872035C40B51035C80D7002DC00B61011 S31500002DC021C00D70022A04600000000000009C0073 S31500002DD0B580A10208F0021C00BE1023C0087002D4 S31500002DE0DC00B60021C4083002000020000000000C S31500002DF02014CC00BB4020A00811064500B02024BA S31500002E00D4093002ED00B20020C009300A080430AF S31500002E1000000000A815BC00FB0032F00C98032D42 S31500002E2000F88033F408B003FC40FA0033C00CF01D S31500002E30032A0460000000008000EC00F9083C084A S31500002E400F9003EC00F8103EC00FB803EC40FA00F8 S31500002E503EC00F3003E00030000000000110FC000F S31500002E60FD0033C00CF003FAA0CE0033C00FF00310 S31500002E70FC02C20033C00CF0130044300000000016 S31500002E8081046C00BF0022200AB802C10480802A97 S31500002E90C00BB802FC048AC8A2C028B00A20501091 S31500002EA00000000080052C00BB0022B0499882EC8F S31500002EB0008B8022C00B9802EC008A8020C008B0EC S31500002EC0022000400000000008040C00B100A00031 S31500002ED00B1032EC00890028C00B1802CC008200CF S31500002EE020C008300202010000000000000D6C0046 S31500002EF0F50032000DB013E802CB0133C00FA0037A S31500002F00EC00CA0031C00CF02300035000000000A2 S31500002F10A01DFC00FF00BD000E4003FC00FD013DAE S31500002F20C00FF003FC00FE003FC08FF003E8067000 S31500002F3000000000C001D480C7803DE00CD083367D S31500002F4000C78033E00CF8039E00CC803DE00CD82F S31500002F5003300070000000008010E6008B842EE035 S31500002F60409C02220088802A200888022600AA01A6 S31500002F702EE00CB002200430000000008805E4407A S31500002F8081002CC00210420C00A10020400810460F S31500002F90000082006EC0B8B002220170000000007E S31500002FA0C015A6048A802ED06A98022800AA002A94 S31500002FB08048A0022800AA002EF009B00230046062 S31500002FC0000000004011E600C9803EF08E1C03059B S31500002FD080EB0032C02CB00A2C02CA003E700C30C6 S31500002FE00B10047000000000E001BC01FF083FC4A4 S31500002FF00D8083F002DC003F000FC0437400FC40EC S315000030003F400ED403F80060000000004010A540C9 S31500003010C900B2C80C90036D00C98032600C9801DB S31500003020E040CA803E548CB003D00420000000006B S31500003030C8050F01DAC820F8188C03280082403032 S31500003040900D20080818DA002C600ABB02F2004036 S3150000305000000000E005449283C120D00811024020 S315000030600A820824821924820E0082002C62093406 S3150000307002F800500000000020013A40878023E05B S3150000308018781216008580616009590217509690CB S315000030902F640B7802C800400000000048080900B1 S315000030A0832030C428200B4800C04074100D050B47 S315000030B08000C0003C408D1023D2020000000000BA S315000030C04019B810FE003FC40BE103DC40FF009539 S315000030D0C00F7103BA04FE043F404EF003D00660F1 S315000030E000000000A805E400CB0032C00FB803C002 S315000030F002CA003C810C20032C00CA0030402CB0D0 S3150000310003EA00700000000048119C00870021C0FF S315000031100B7052140085002D400A50029400860060 S315000031202100087002D2046000000000C000960072 S315000031308F8001300B28029A0094846D2018480273 S3150000314012008E806360187802F0002000000000F4 S315000031504814CF02820120510B2D020C0093002C43 S31500003160C04A3032880280806050181002D3043082 S3150000317000000000E815B980CE88B3B00FE103A8BF S315000031800292003E800CA0012800CE8031840CA261 S3150000319003FA0460000000004800E120F8003E0841 S315000031A08F8003B000EC003F000FC003F000F85022 S315000031B0BE102F8403D20030000000000810E44344 S315000031C0C90032410C9223E400C900324008902322 S315000031D02400C90036680C9803C2043000000000C1 S315000031E080044701812020700A9C02C402892020A5 S315000031F0484D10034402814022620A9E02E00010FC S3150000320000000000180524348900A24408B086F4A2 S31500003210018D0023400AD00234008900264008911F S3150000322002C600400000000008042400810020C0FF S315000032300A1002F4008500A1400B501254108100C0 S3150000324022410A1002C2010000000000B80D62000F S31500003250880022000C8803E011C80032000E80139B S315000032603002CA5436000C8003EE03500000000002 S31500003270981DD508F5023F400FD421E400D9003E41 S31500003280404D9043C400F5803F410FD283E606705F S31500003290000000001801F400DD0013400CD003E428 S315000032A000C10030400F1003C400C94033C02CD009 S315000032B003C60070000000003810E8008A045600BB S315000032C00C8012E000880022000B800278008881C2 S315000032D02280488002CE0430000000000805C400A9 S315000032E099000260081842C400850429400B500664 S315000032F0D402A90060C0081002C2017000000000DC S315000033001815A6008B022660089202E4028D802B17 S31500003310604BD802F604A9012240889002C60460D8 S3150000332000000000A015E500D90222408C9403C6D7 S3150000333000C9803A600F9803C700E980B2400C913B S3150000334003E804700000000028018408F9203E40CC S31500003350AE9003E480F904B6410F90036410DB904D S315000033603E420F9003CA0060000000002810A00033 S31500003370C8007E040F8003E000CC0033000CC00BB5 S315000033803102C80932102C82030A04200000000012 S3150000339028053A0A865025800BE202E800820016CC S315000033A08000A00368000209A18008E8020A004024 S315000033B0000000002805424083C02C380B0482C060 S315000033C0098014200428000040008040248009342D S315000033D0220A005000000000A001100086082DC03F S315000033E01B5022D002870025E00878025C00860088 S315000033F025C009788228004000000000A8081E00A9 S31500003400C6802D600F6803D210C58031600C48035A S315000034105204CC8035E00DF80B2A020000000000B3 S31500003420081D8000FA0036400F8003C0007A003E77 S31500003430804FB00BEC00FA6838C00EB003C20660CD S31500003440000000000005F200FC8033600FC803D2C4 S3150000345010C69031A00C4803F208CD902DE408C8A0 S315000034600B00007000000000A8119920B60021C4CE S315000034700B4102D040853021480872021C0087307B S315000034802D8D2846022A00600000000000009C00E6 S31500003490B40821400B4002F1208F4067D058C40287 S315000034A03040A5092DC00940220000200000000080 S315000034B02014C880B240A0420B0602C0008000243F S315000034C0000830064C00A3802CD1091802080430ED S315000034D000000000A815A000F0C022000F8003E144 S315000034E00088C0363008BC032E00EC803CD01DB0EE S315000034F0832A0460000000008000E800FA003E40D5 S315000035000F9823E000FB803AE00F8C03A28018405E S315000035103EC04EB003E00030000000000110FA404B S31500003520FC08B3410FE003D000CD0033400CF0039C S315000035307E80CD803F8209FA03C04430000000003F S3150000354081046900BA8222E00B8042E000820020FA S31500003550800800420110DD192EF22C8402E0401092 S315000035600000000080052000B88022600B8002E089 S31500003570008A00628008B6022D008A002EE03A809A S3150000358002E000400000000008040800B20120C06C S315000035900B0002E00289002240088002000092002F S315000035A02EC00A2002C2050000000000000D6800BF S315000035B0F80232404B8043E0008B0032C00CB0036F S315000035C02C00CB003EC00E0003C0015000000000DE S315000035D0A01DF800F6003F400FC003F000FC003FBE S315000035E0000FC003D008FF003F000CC003E80470C2 S315000035F000000000C005F820FC0033E00CF00336A4 S3150000360000FF8031A00CF2033C04CFA431C20CEBC6 S3150000361003300070000000008010C910B8D022E00E S3150000362008B0436A00BB8022A008BC02AC008F50E1 S3150000363037D20DEF02200430000000008805C2A03A S31500003640BA0422C008B2820408BA00200028340254 S315000036508000832820C84820422301700000000013 S31500003660C015A010BA8022C008B8026F14BB002291 S315000036700008B002A020830026C009A00230046022 S31500003680000000004015E200F8C0B2D88CF0832597 S3150000369000FB40B2800C3003AB10CB0032C00CA84C S315000036A00310047000000000E001BB00FC003FC0F6 S315000036B00BB003FC101F903FA80FB003E840FB00BF S315000036C07FC00FE103F80060000000004010A46016 S315000036D0CA08F2D90FB0036500FA403E810CB01358 S315000036E00404CB00B0C00C2003100420000000002E S315000036F0C8052700830060D80B30022D00B31C2CB0 S315000037009008F10164008F0023C008A00232004037 S3150000371000000000E0054E00805420D10B30024529 S315000037202191C02C882834020010830020C0482034 S31500003730223800500000000020011E408C8021A08D S315000037400B58021A01B7802DA208781A50408780BC S3150000375023E05868020800400000000048080800FE S31500003760C02020C00F30034440F3503C001C3003FF S315000037700C42C30030C00CA003120200000000007F S31500003780401DB810F4001FD00FD003FC007F053F8A S31500003790040FF103FC08FF003FD06FE003D0066082 S315000037A000000000A805E600CA0032C00FE003E0F2 S315000037B000F9003E180FB0036000FB2072C80CA38E S315000037C0032A00700000000048118C00860421C006 S315000037D00B7002D000B6012D044B72021000B3101C S315000037E0A1C00D608A12046000000000C0009F00A6 S315000037F0868021E00B6892D201B7802D220B390218 S315000038001E00B7B121E4496A023000200000000022 S315000038104814CE00828820C30B3002C080B3022C2D S31500003820200B30020D00B30022C00928021204301A S3150000383000000000E815BA008EA032800FE043FBBE S3150000384080FE003E800FA00B3800FA0032804D4803 S31500003850033A0460000000004800E202F840BE118E S315000038608F8823E100F8003E000F8003A020F004BB S315000038703E000F8103D20030000000000810E50072 S31500003880F10032F00F9003E400F90832F04F18030C S315000038900400C90032400E8003020430000000001C S315000038A080046400B90022400B9042E521B1D82281 S315000038B0680B90022400C90022400D9002200010DF S315000038C00000000018052500BB08A2400B9012E47A S315000038D004B90022400B910624009900A2400A90E8 S315000038E0020600400000000008040500B10020C0E8 S315000038F08B1402C400B90020400B10024402811848 S31500003900204429930A02010000000000B80D62005D S31500003910F88032004B8843E000B80032000F828BFB S3150000392021C0D840301A0E82832E035000000000BA S31500003930981DF708F5403E400FDC03F400FD00BE7D S31500003940400F9003B4C0F9203F480F4203E60670CB S31500003950000000001805F400C50033400C9A03E48B S3150000396000F9003D404F9002A400F90032400C924D S315000039708B060070000000003810E000880122006D S31500003980288502E800B8012E000B80022800B80244 S3150000399034004D84020E0430000000000805CC01FE S315000039A081006040081002C400B1002C400B1002D8 S315000039B08400B100204008100202017000000000DF S315000039C01811A4208900E242089002EC00B9402EAA S315000039D0480B90022480B901264009920206046031 S315000039E000000000A015E440C90830500C9003E523 S315000039F000F9103E404F900BA500F90032410090AF S31500003A000B2804700000000028018602F1903E4059 S31500003A100F9003EC00FB823E400F3003E400F900F8 S31500003A203E400F100BCA0060000000002810A18065 S31500003A30C84036100F80032111F8803E000C800329 S31500003A40E102C80030002C80030A042000000000B8 S31500003A50280538008E002BB80BA0022900FA202F6B S31500003A608028A802E8008A0022800DE0020A0040B1 S31500003A700000000028054D00930024D80B30020CEE S31500003A8020B0802CC0082586CC008B0020C02A30B0 S31500003A90020A005000000000A0011C0097006DC043 S31500003AA00BF8021C11A7042DE0087006DEC0872063 S31500003AB021C009720228004000000000A8083E024A S31500003AC0D78035E00F78031E00B7803DE00C680311 S31500003AD0CE08C3C0B1E80EFC0B2A020000000000AD S31500003AE0081DAC00EB003A800F310BECB4FB6C3ECA S31500003AF0C00FB403EC00FB683EC20FB6C3C206603B S31500003B00000000000005FA00B7A431240CF803DE1B S31500003B1040CC9233E00FEC213E00FF8033E30CF8FB S31500003B204300007000000000A8119000B72021801B S31500003B30087202DC40D61829C80B61035C00B70086 S31500003B4021C00D71022A04600000000000009C40A4 S31500003B50B73121C00A7012FC01870221C01B400246 S31500003B605C00B70021C408300200002000000000FD S31500003B702014CC00B300E09008B802CC2892C028EC S31500003B80C00B00066C00B30020C0093002080430E8 S31500003B9000000000A815A400F140B2800EF182EFEB S31500003BA000C80030410F800B7C00FF00B3C008FA4C S31500003BB00B2A0460000000008000EF00FB403E92EC S31500003BC00FB013EE00F9203ED00F9403EC00FB0477 S31500003BD03EC00FB003E00030000000000110F3000B S31500003BE0FD2AB3610CF0033C01CF001FC00C00039B S31500003BF03C00CB0032C00CF00B004430000000004B S31500003C0081046E04BA80200208B0020C10A9702E3E S31500003C10B00A9C82AC00AB002AC00FB00220401054 S31500003C200000000080052100B940260909B0022CD9 S31500003C300088002E7008B1222C00830020C00830B6 S31500003C40422000400000000008040000BB00A480E1 S31500003C500930022810A3002EC00A30068C00A300EB S31500003C6028C02B300A02010000000000000D600091 S31500003C70F900B6404DB00B2C008B043EC00C9003EF S31500003C802C00CF0033C00CF00300035000000000EE S31500003C90A01DFC00FE003B000CF003FC00F7003FFB S31500003CA0800FD003FC00FF003FC00FF003E8067052 S31500003CB000000000C005FE00CC8233A00EC803B68B S31500003CC000F7803FE00FF803FA00CC403FA008D889 S31500003CD00370007000000000C010C800880120A01A S31500003CE08898022E00BB802EE00BB802EA00A900DD S31500003CF02EE108900220043000000000C805ECA068 S31500003D00802822802010068600B3802CE00B380223 S31500003D10C80082202CC008800262017000000000EA S31500003D20C015AB00A88A208008800A2C00BB002E94 S31500003D30C00BB002EA00AA226E4408B20230046048 S31500003D40000000004015E600C980B2800C8043A642 S31500003D5000F9003E40079003EC00C8403EF08C1886 S31500003D600350047000000000E001B010DD003F8049 S31500003D702DD003FC40FD003F400FD003FC00FA02AB S31500003D803F600FD003F80060000000004410A5005B S31500003D90EB003EA02C91032400F92032480F920339 S31500003DA0EC00F870B2D00F80031004200000000071 S31500003DB0D80507000B412EA08805022F50B94022D6 S31500003DC0400B9602CE00BA4020600BB7023200408C S31500003DD000000000E00540402A812C88200802CB24 S31500003DE000B24020B00B2402C040B04004C50B30E6 S31500003DF00238005000000000A001130086C22FA068 S31500003E0088580AD220BE8021A04B6802D200B78013 S31500003E1025600B5802080040000000004808080012 S31500003E20E0193C802C1203C800F200B0820722037E S31500003E30C000F15034D00FA00B12020000000000A9 S31500003E40401DB845FC103F804F40033040FE103FF8 S31500003E50840FE013F200FF063B440FF403D0066024 S31500003E6000000000A805E000FB003E804F0009AA04 S31500003E7000C08032000C80132410F9003EE00CB420 S31500003E8003EA007000000000C8119000B7042D80FE S31500003E900B500A1000840021000840021404B700E9 S31500003EA02D40485002D204600000000080009600B9 S31500003EB0B7C02DA00B5806BA009C80232009C80263 S31500003EC01608B5C02FE2186902F0002000000000B5 S31500003ED04814C544B2002C800B000A00009400214F S31500003EE0000940021410B3802C70483042D20430CE S31500003EF000000000E815B800F6C03E800F2003A8B9 S31500003F0002DA00B0802D200B2800FE002F802CA0A6 S31500003F1003FB0460000000004800E000F8083E00D3 S31500003F200FC403F100E8003E100E8403E204F80813 S31500003F303E000F8003D20030000000000810E42885 S31500003F40F90636400F9C136600F9003E44089903B3 S31500003F502400F90036620F9003C20430000000000E S31500003F6080046780B9C022520B988A2740B9002E78 S31500003F70600896022410B94022400BB042E00010BF S31500003F800000000018052600B98826400B90027430 S31500003F9000BD002F401AD0023600B14026440B90D7 S31500003FA002C600400000000008040500B940204099 S31500003FB00B50021C09B5002F40BAD00A1608B128CA S31500003FC020400B1002C2010000000000B80D600086 S31500003FD0F80036000F80036000F8003E800E802354 S31500003FE03000F82036010F8003EE03500000000079 S31500003FF0981DF604FD803E400F9003C400F9003C76 S31500004000400D1003E400FD283D400F9083E6067046 S31500004010000000001805E400FD003E400C5003249B S3150000402000CF0032C00FB003F404F9023F408F9472 S3150000403002C60070000000003810E800B8002C002E S3150000404028A0022000880022010B8002F000B8019F S315000040502E000B8802CE0430000000004805C40183 S31500004060B1802F410A504A3400850021401B50027E S31500004070D400B1016C408B1202C201700000000036 S315000040801815A400B9006D402A9002340089002357 S31500004090400BD002E400B9006E440B9002C60460E7 S315000040A000000000A015E600F9003E400E90032433 S315000040B002C900B2400F9003E400F9603E584F94E5 S315000040C083E80470000000006801AC40F9903E40AF S315000040D00D9003E400F9003E400F9043E400FB24FA S315000040E03E600F9203CA0060000000002810A04046 S315000040F0F8103F000EC40B3000FC003F000FC00359 S31500004100E000F80832148F8C030A04200000000037 S3150000411028052900BE422E800828020800B2022E79 S31500004120800BA002E810BA0022A10BA0020A0040F0 S315000041300000000028054620B3A12C1822680211B1 S3150000414080B0602D380B4802C200B04024400B18E6 S31500004150020A005000000000A0011C00B5062F80D6 S3150000416008C0921000B5002D020B4082D100B78026 S3150000417025C00B7C0228004000000000A8081200A1 S31500004180F5803D604E48031200F4803D200F481331 S31500004190DE00F08035E00FD80B2A02000000000098 S315000041A0081DA830F8023EC00F9003EC08F9003E47 S315000041B0C00FB003EC00FB22BAC00FFC43C206607E S315000041C0000000000005FE40FE8431600E49033603 S315000041D000C59033E00CE8033200ECC03DE50CCCA2 S315000041E003C0007000000000A8119C00BC4421C858 S315000041F00843021400840021C008640210048710DA S315000042002DC40A7012EA0460000000000000941138 S31500004210B710234048C00634009D0063C008E00282 S315000042203C0084002F44184002C00020000000001B S315000042302014C910B00200C000148A4A0090000081 S3150000424000481002040083202CE00A3E02C8043015 S3150000425000000000A815A500F252B24004942308FD S3150000426020D80030001C10032002EA402CC24CF07B S3150000427082EA0460000000008000ED00F8003ED0F5 S315000042800F9003A880E9003E000F9403E000FB10A6 S315000042903E420FA403E00030000000000110FC20A5 S315000042A0FD0137404CDC033B00CC0033000CD0034F S315000042B03C00CFA03FF00CF802C0443000000000E4 S315000042C080046E30B88222D82A0E02240081002291 S315000042D0C008A4020C008BA02EE188AB02E04010BF S315000042E00000000080052C40A98124400890022C83 S315000042F00089002AC008B00220008B000EC008808A S3150000430022E000400000000008040C08B90022C0AA S315000043102A90022C0188002AC008B00220008300DF S315000043202EC0080002C2010000000000000D6C0053 S31500004330E90036402C90032C00C9003AC00CB003AB S315000043402C00CB047EC00C8027C003500000000068 S31500004350A01DFC10FC003FC00FC003D000FC0035C0 S31500004360000F40035400FF003F414FC003E80670B2 S3150000437000000000C005F080F78033A00FD803725C S3150000438000CC8033810CE0033000CC0033500C6845 S3150000439003300070000000008010A100BB8022A046 S315000043A00BA00220082800228008A0022201888093 S315000043B022480AB803600430000000008804CB20BD S315000043C0B10220000BB01244000002A08048204237 S315000043D00400820020400830022201700000000024 S315000043E0C011A840B90322028B80120012A810A2A5 S315000043F08008201224008A0820428AB08270046055 S31500004400000000000015E000F3E0B2B10F00036108 S3150000441020C80133810CB0032200884032540CB40A S315000044200B00047000000000E001A200FFA83FA4FA S315000044300FF003F000FC803D806FF00BE040F400CD S31500004440BE600FF003B80060000000004010AC0032 S31500004450CB4032100FA013A002F84036800CB003F8 S315000044602402CA403E500CB5031004200000000090 S31500004470C8052C048B0036008B90222080D80023A0 S315000044808008B00204008A002E40083402B20040C0 S3150000449000000000E0014400828020C48B100284EA S315000044A000BBE12080882006098181022C80683AC1 S315000044B0463800500000000020011E088F98652035 S315000044C00BE8021242BE9821A008280218488580EF S315000044D02DA4087802880040000000004808004229 S315000044E0C21030C40F3003A402F150B6800C200B6A S315000044F00C44C3007C840C3203120200000000004E S31500004500401DB800FF142F040F4013F002D4513F92 S31500004510802FE021FC80EF103FA40FF003D006604F S3150000452000000000A805E400F38432C00F8023A435 S3150000453000E80336818FB0132A08C98032800C3216 S31500004540032A00700000000048111C00B704211463 S315000045500B700210408E0021800B30101812810261 S31500004560208008710352046000000000C00096001D S31500004570BF8021E80BE8029204A488A1A04B7840F2 S315000045804E04878061A008F8023000200000000079 S315000045904814CD00B3C820000B141201068AA020CF S315000045A0800BB4224C00830020800836025204306F S315000045B000000000E815B800FE00B2800FE402A873 S315000045C040AA8033800FA02368008A00B3802C2481 S315000045D0433A0460000000004800E020F8103E0066 S315000045E00F8483E000F8403A000F80ABA000F84447 S315000045F03F000F8403D20030000000000810E400E2 S31500004600F9803E500F900B2C00DBC2B2400C9A0191 S315000046102600F90036400CB00B0204300000000002 S3150000462080046400B9F22EE00B960A250089C020AA S3150000463040089C022440E9602E408A98022000101F S315000046400000000018052400B9002E404B1002049B S3150000465020990022400A9406B500BD10294108920F S31500004660820600400000000008040500B1002C404E S315000046700B140A05000140224D0A14021400A5017C S315000046800D44CA100202010000000000B80D6200CD S31500004690F8003E004B800B0008DA00322A2E800B11 S315000046A0A004F80013100C80032E03700000000015 S315000046B0981DFF04FD023E400F5803E608F9803FAF S315000046C0480D9E036501F9403E584F9003E606707B S315000046D0000000001801E400F10030400F9403E5EB S315000046E000E9003A780CD0033400C90032408D50FE S315000046F003C60070000000003810E000B800B600E5 S315000047000B8A02020284A0AA3808800A28108800B0 S3150000471028000A8002CE0430000000000805C4000C S31500004720B90020400BD212D40025082044081002FC S315000047304C0091002040093002C2017000000000C8 S315000047401815A400B90026600B900234008D002ACB S3150000475040281002640099002A408A9442C60460E8 S3150000476000000000A014A740F90032400F9803E5AE S3150000477082E9903A400C90016500D18132402D903B S3150000478003E80430000000002800A400FB907A40F3 S315000047900F9203E400F9803C400F9003A420EB2025 S315000047A03E404F9003CA0020000000002810210060 S315000047B0F80032004C800B2100CC0032010C820341 S315000047C00102C8003E000C8C0B0A04200000000009 S315000047D028042800B200A2800A280228068E00B605 S315000047E08008E40238008AC02F8008E00A0A000028 S315000047F00000000028040C00B34820009A300A2C60 S31500004800008A0020C0CA3042890080302E800830DD S31500004810020A00500000000020011C40B5002320C1 S315000048200A70821400A600A7C00A70021E00A40027 S315000048300D800878120800400000000028081E803D S31500004840F59031200EE8031A00C58011E02E000312 S315000048508C00C5813DA42C58030202000000000014 S31500004860081DAC00F9413E1087A003E000D9003CCA S31500004870C0098001EC00D9403E880FB003C2066033 S31500004880000000004005FE00CF8033310FD9031E23 S3150000489000CE8033E04CF8233E00FCC03FA20C68FB S315000048A00350047000000000A801BC008540210AE6 S315000048B00BD3821480460129C028F0071C00B400DF S315000048C02F800F7102AA06600000000000009C0005 S315000048D0850025004B40123810158025C00940027E S315000048E01C00B6002D900870020000200000000099 S315000048F06014CC008160A4300B8402001089C02EA5 S31500004900C009800A0C00B2002E800B308290003065 S3150000491000000000A815BC00C94036100FB9032DD1 S31500004920019AE027C00D90022400FA003F900C3453 S3150000493003220060000000008000CE00F9003A80EB S315000049400FB003E401FA003AC02E90038400FA4047 S315000049503EA00FB013E00030000000000110FC0084 S31500004960CDA033220FE0033820CD0832C00CE80B6F S315000049703C00C70033800CF003004030000000000C S3150000498081046C0881C222000BE00230028D0037E0 S31500004990C008A4932E00DB00368088B002284010A1 S315000049A00000000080052C00890022080B90020CF4 S315000049B0018A0022C00882126E108919628008B826 S315000049C0022000500000000008040C0409042080A6 S315000049D01B10020401820064C01800020E00910040 S315000049E024802838020B00000000000000042C0080 S315000049F0C900A2004B800A2800C10032C008B003DB S31500004A002C04CB00B3800CB00B0002100000000099 S31500004A10A019FC00F4023F000BC003F000FD003FAC S31500004A20C02FF002FC087F003B808FF003E907707F S31500004A3000000000C005F200FD2433E00C78033EC0 S31500004A4000FF803FE00FF803FA00DC8037A00FDCA0 S31500004A5007300070000000008010E210B16020E016 S31500004A6088B8022E00BB802EE00BB802EA08BB080D S31500004A70A0C00B9002200430000000008805CC0482 S31500004A80B01CA2E108B8020C00B3802CC00B3002A7 S31500004A90CC00B32024C00B32166201700000000067 S31500004AA0C015A800B28820C008B0022E00BB002E98 S31500004AB0E00BB802EC00BB0422C04BB010700460DF S31500004AC0000000004015E240F98132C02C900B280E S31500004AD000F9003E800FA003E000DB5036F08F8027 S31500004AE00050047000000000E001B000FD003FC06F S31500004AF02FD003F810FD003F800FE083F000FD8209 S31500004B003FD00BE003B80060000000004010AC008E S31500004B10FB2036E00E900B2800F9083E840FA00318 S31500004B20E400FA4032C00C9203D0042000000000DA S31500004B30C8052800BAC222F10814022A00B9402E7C S31500004B40800BAC02E420BB0022F008B482F20040E5 S31500004B5000000000E0054000B11024984A208206BB S31500004B6080B2402C420B1C02CA00BB0020E608980B S31500004B7002F800500000000020011200B58023A0BA S31500004B8028E8021601B6802D600B5882DA00B6803E S31500004B9021E0085802C80040000000004808040050 S31500004BA0F20034800E20030420F2003C400F100374 S31500004BB0CC00F100B0C02C3003D20200000000008F S31500004BC0401DB000FF003F840FE003F440FE103F9D S31500004BD0440FD103FE00F7007F400FF403D00660B8 S31500004BE000000000A805E000F10036800F8001C239 S31500004BF000C08032000880030200C30032D20F8258 S31500004C00032A007000000000481191C0B500218001 S31500004C10034012D000840021010840021004A701BD S31500004C2021C10B620352046000000000C040969050 S31500004C30BFC025A00B4802F2008C80232009C802C1 S31500004C4016008F8021E00BD14630002000000000C6 S31500004C504814C010B30020800B0006C0008000205E S31500004C60000900020410B01120C00B3202120430F9 S31500004C7000000000E815A800F60236810FA003E840 S31500004C8002CA00B0802D200B2800C69030A00FAEBF S31500004C90063A0460000000004800E000F8483E00C4 S31500004CA00F8003E200F8003E304E8803F000E80073 S31500004CB0BE340F8003D20030000000000810E4006C S31500004CC0F9803A410F9003E600F9007E440C920306 S31500004CD02600F90032E00C9003C204300000000008 S31500004CE080046C00B95022420B9006E640B9002EB3 S31500004CF0700894022400B90036542ABC03E0001060 S31500004D000000000018052580B9002A400BD002F4E7 S31500004D1020BD002F4008D0023440BB0022C00896B8 S31500004D2002C600400000000008040408BB40204002 S31500004D300B5042D400B5002FC028F00A1405B10468 S31500004D402640081402C2010000000000B80D6000F1 S31500004D50F8803A000FA002E000F8002E000C800355 S31500004D603000F80032808C8003EE03500000000013 S31500004D70981DEC00FFC43E400F9003E400F9003C90 S31500004D80400F1003E400FD283E4A0F1803A70670E3 S31500004D90000000001801F400F9023A400CB003C408 S31500004DA004FB0022400F9003FC00FD0033400391FA S31500004DB003C60070000000003810E000B804600070 S31500004DC0488042E000B80022000B8002F800B800DC S31500004DD022800B8A02CE0430000000000805C400C1 S31500004DE0B1012B40185002D4083D0021400B50025F S31500004DF0D400B10020400B1002C201700000000078 S31500004E001815A404B9002140089002F400B9002343 S31500004E10400BD002E400B90222400BB002C6046087 S31500004E2000000000A015E400F9C02A402C9003E41D S31500004E3000F100B2400F9003E400F160B2500F9908 S31500004E4083E00470000000002801A500F390BE4036 S31500004E500F9023E400F9003E400F9003E428F92464 S31500004E601E44059803CA0060000000002810A080B8 S31500004E70C8813B0004C013F002EC003F000FC08362 S31500004E80A140F84032100C84230A042000000000E0 S31500004E9028052B00AA83228428A002E8008A003A6B S31500004EA0800BA412E800BE0023A028A0020A00403E S31500004EB0000000002805430082802800596642D180 S31500004EC08082602D380B4C024000B20020C8183199 S31500004ED00A0A005000000000A0011300AC40238025 S31500004EE0096012F200870029020B4080D808B62418 S31500004EF021F118580228004000000000A8081600FA S31500004F00C68A39600D6803D200C6803D200F48036B S31500004F101A00FEA0B3A00CF8072A02000000000049 S31500004F20081D8424F2603EC02EB003EC00DB003E78 S31500004F30C00FB002E000FA907E804FEC03C206601C S31500004F40000000000005F202C7B023640DF823F646 S31500004F5000FF803FE00FF803FE00FE8473688FFCBD S31500004F6043C0007000000000A8119000851821CCF5 S31500004F70087002D400B6002DC00B7002DC00B61318 S31500004F8021420B7202EA0460000000000000B0003B S31500004F908F20A740897002D400B7002DC00B700285 S31500004FA0D420BE0021090B7002C0002000000000C2 S31500004FB02014C084834024C0082002C800B2042CF8 S31500004FC0000B0002C400B2C020404B2902C80430C6 S31500004FD000000000A815A000C9C036402DA003E8B7 S31500004FE000BA003E000F8002E800FE1832F00BE027 S31500004FF003EA0460000000008000E000F8003AD0F8 S315000050000FA003E800FB013E000F8003E880FA00D2 S315000050103EC80F8003E00030000000000110F08061 S31500005020FD993B400CE003F880FE003F000FC003F3 S31500005030F200CE003FA80FF003C04430000000008D S3150000504081046084BBE022D848B002E610FB002E43 S31500005050C00BB002C2408A002E200EE002E04010D3 S315000050600000000080012800B302284048B042EC4E S3150000507000BB002EC00BB002EC008A002E500BA025 S3150000508022E000400000000008040804B00062C0EE S31500005090083002CC00A2002CC00B3002EC008200CB S315000050A02C000B2002C2010000000000000D600071 S315000050B0FB0138402CB023EC05BB023EC00FB00309 S315000050C0E402CA003E800FB003C003500000000097 S315000050D0A01DD004FF00BFC00FE003F000FE003F9C S315000050E0000FC003F400F6003F004EE003E8027034 S315000050F000000000C005FC80CF8033A00FC8031657 S3150000510000CC0033A00CF8037600EF0033C80DF096 S3150000511003F00070000000008010EF408B2402A016 S315000051200B98122C008A80226008B822A2008B00FD S3150000513023CA08BC02E00430000000008805CC0049 S31500005140820820004B000224008200208048304262 S315000051506C00A00024CC093402A2017000000000FB S31500005160C015AC008B80A2200B900220008A002282 S31500005170E008B022AA00884026C008B000F004600B S31500005180000000004015EC00CB8032300F1B0326D8 S3150000519080CC8032B80CB0034700EAC036C00DB0F0 S315000051A003D0047000000000E001BC02FE003FC016 S315000051B00FD003F040FAA03FC00FF243F000F21008 S315000051C0BAC02FF003F80060000000004010AE00E7 S315000051D0FA0036000CB003E500EB00B2800FBC030A S315000051E0ED20F80430C02EB003D0042000000000EB S315000051F0C8051D00B3482290089002C10083822092 S31500005200C80B20022300B82023C008FC02F200408D S3150000521000000000E0054C80B3802488281902C2F3 S3150000522080A28020A00B1002C740B00020C02A3AFE S3150000523022F800500000000020011E00BFD021E02F S31500005240085A12DA0186C021B40B79021200B48121 S3150000525021E0087802C800400000000048080C0061 S31500005260F20034C20C3003C0B0E218B0840F34032D S31500005270CD80F300B0C82E3083D2020000000000BB S31500005280401DBC00F7003DC40FD253F802FE103F8C S31500005290840F7043F800FF003FC08FF003D0066014 S315000052A000000000A805EC00FB003A000F184320A0 S315000052B0A0CE003EE00CB6432600D90072C80CB062 S315000052C0032A00700000000048119C00B40021C0B1 S315000052D00B5002100086002D8008708290008D0011 S315000052E0B0D408700212046000000000C0009E41A5 S315000052F0B6C029600BF886120497802DF0096C025F S315000053001E00978021E089794A30002000000000C5 S315000053104814CC00B18020E00B18460A4093402C7C S31500005320B8093C028C608B4122C00930021204305D S3150000533000000000E815A800FEC03BB80FE40B29EA S3150000534006DE403FA02D2C073B00DE0032802DA05C S31500005350033A0460000000004800E000F8403E12F6 S315000053600F8203E182E8243E010E8087E100F808FF S315000053703A000E8003D20030000000000810E480DE S31500005380F90836404F9003EC0009A13E400FBA03DE S31500005390A700F9A032402C1A0302043000000000D6 S315000053A080046400B10122600B9052C50089A02ED2 S315000053B0600B94422400B9812240089C0220001010 S315000053C00000000018052400B92026C40B9802A48A S315000053D000A9042E605B9082A400B90022400894C4 S315000053E0020601000000000008040400B940244041 S315000053F00B1842C500A1002C401B101A0C00B10965 S31500005400A05088100202010000000000B80D6200E2 S31500005410FA0036800F8003A808E8803E000F80025D S31500005420A000F880B2202C828B2E025000000000D3 S31500005430981DE500F586BB400FD003CE029D403D8A S31500005440400F1013D400FD893E700F1003E606705E S31500005450000000001805F4007D0035400C1013F420 S3150000546010CDA03D400CD0030400FD4032402D90ED S3150000547003060070000000003810E000BA002200A9 S31500005480088012E00088042E00088002A800B88078 S31500005490200008800A0E0430000000000805C40041 S315000054A0B1002640081012C40081402C400810228A S315000054B00400B10020400910020201700000000043 S315000054C01815A400BB00224828B042E40889002E23 S315000054D044089102A604B9412040089002060460DF S315000054E000000000A015E400F90036520C9023C518 S315000054F000C9203C402C90C32400F980B2400D9096 S3150000550003280470000000002801A420F9003E4092 S315000055100FB203E70AF9A03E420F9003EC00F12018 S315000055203E408F3003CA0060000000002810A00033 S31500005530F82132108C81032000E8013E002C8603FE S31500005540A000E80132012C8203CA042000000000FA S3150000555028053A00B60921800AA80238408E502F45 S31500005560A208644368608A04228008AC02CA00402C S315000055700000000028054E40B2C020400826020C5C S315000055800083802CC008301A8800A18020C008083B S3150000559002CA005000000000A0011C00B60023C093 S315000055A00AC8021C0185402D800870225A008740D7 S315000055B021C8085082E8004000000000A8081E002C S315000055C0F78021E00C58133E02C7803D600C48036B S315000055D09A20E380B1E90C7883EA0200000000001B S315000055E0081DAC04F200BEC00FB61BEC00F8003E6E S315000055F0800F2003E980FB003ED40FB003C2066093 S31500005600000000000005FE00C6803F604FFC033E20 S3150000561090F79033200F62033A00D78033F00DE8FD S315000056200300007000000000A8119800862001C841 S315000056300B50021C00B60409008B600298008720FC S3150000564037C0087403EA04600000000000009C00F4 S3150000565086012DC28BD1025C84BF0221000BC102E0 S315000056601800970421C40960020000200000000011 S315000056702014C808829020F20B38824C08B2902081 S31500005680281B2A028940830026C0082002C804304D S3150000569000000000A815A400CA403E600FB2036CCB S315000056A004FA00B2980F26032A00DD0033C02D80CD S315000056B0032A0460000000008000E400FA003ED0E7 S315000056C00F940BA548F8403E800FA403E800F300B2 S315000056D03EC00F9003E00030000000000110E4011E S315000056E0FC08B3C04CEA13FE280F003F000FE0038E S315000056F0B820EF00B3C00C9043C044300000000057 S3150000570081046601B8C4208208A402C12088A026AC S31500005710A04EAC0208648F0022C008B502E040101B S315000057200000000080052E04B280224028B002E866 S3150000573080A9842EB00BA882E800AB0022C008A086 S3150000574002E000400000000008040804B00028C081 S31500005750081042C002A0002C800A200248008300E4 S3150000576020C0083002C2010000000000000D6C00DD S31500005770B800B2C00C9003E810EB003E000FA00B7F S31500005780E800EB0133C02C9003C00350000000007A S31500005790A01DF000FC00B780057003F008DE00379E S315000057A0810EE0439400FF003FC00FF003E806704F S315000057B000000000C005F200FE8031200FC8033053 S315000057C002CD003FC80DD803D200DC80F92088C87E S315000057D003300070000000008010E608EA8022E036 S315000057E00B82822F0081542AC028B0222C04BB01D0 S315000057F022C10D8002200430000000008805C0147C S31500005800B20000200B20020C40890024D008300290 S315000058104C00BB0022C018000622017000000000E8 S31500005820C015A440BA0822E00B88822E008B4028BF S31500005830C0083002AC003A8022E0098000300460E3 S31500005840000000004015E300F88032A00F9C0A23F8 S3150000585000C80036B20CB9036C00F30120F308A8A7 S315000058600B10047000000000E001B408EDC03FC05A S315000058700FF003E400FCA03ED00FF0237A40FF00B7 S3150000588027800FEC03F80060000000004010A0081D S31500005890FA4432C00EB003E700E84036C02CB0032D S315000058A0A400DB613EC20D8003D00420000000008E S315000058B0C805240CB20022E808B902C608820123F2 S315000058C0C048B0022E808B083EC20D8902F200400D S315000058D000000000E0054980B000200208BC02C4B8 S315000058E000A30020401837028D80A3C40CD008887E S315000058F002F800500000000020011200BD90232491 S315000059002978A2DE02879021601878023600A780E7 S315000059102FE0094886C8004000000000480808003B S31500005920F208B0840C3002CC00A100B0400CB003E9 S315000059308800F3003C800C0103D202000000000046 S31500005940401DB000F6003FC40EF003FC00FF003B14 S31500005950540FF103FC02DF003BC00FC003D006600A S3150000596000000000A805E8C0F880320004B003E497 S31500005970007B0036500DB003EC01CA0036C00BA008 S3150000598003EA00700000000048119040B5002100B5 S31500005990087002DC00B7002168087002DC0287008C S315000059A061C10B6002D2046000000000C0009A8052 S315000059B0B68027F0087802DE00B5802564097802F3 S315000059C0DE00AF8621E00B6802F000200000000038 S315000059D04814C004B270A4F008B802CE00BB40223E S315000059E05809B802C060A281A0B40B2802D20430C4 S315000059F000000000E815A804FEC435A42CE483FAD0 S31500005A0080FE4036800DA883DA00EE8437948BEA58 S31500005A1003FA0460000000004800E008F8003A00BD S31500005A200F84A3E000F8203E000E8003E00058300B S31500005A303E000F8003D20030000000000810E40092 S31500005A40C9403E400C90034600C9A032E84C9A0378 S31500005A502400C98032400C9203C2043000000000CA S31500005A6080044C0A89802E40089E022440D9802258 S31500005A70620890022760818020504E9002E000105C S31500005A800000000018012C0089016E600898026C65 S31500005A9000890822401890062C028B10A25008900C S31500005AA002C60040000000000804040883016C40A0 S31500005AB028140204008160205A08140A250089402F S31500005AC022500B3002C2010000000000B80D600039 S31500005AD0C8003E014C800362028080B0082C80031F S31500005AE00000C80032000C8003EE035000000000E6 S31500005AF0981DE400F5013D400FD803F500FD913EE9 S31500005B00600FD803F600F5803F600ED283E606707C S31500005B10000000001805E400FD0003400FD003F468 S31500005B2000F90432400C90036404C90230400CD0E2 S31500005B3003060070000000003810E000B800A20064 S31500005B400B8002E000B800A0000880020000880078 S31500005B5063012880020E0430000000000805C4001E S31500005B60B90060401B1002C400B500214008504235 S31500005B705402A50021400810020201700000000036 S31500005B801815A400B90822D80B9002E500B9102315 S31500005B90420850021400A72021448890020604609F S31500005BA000000000A015E400F14032600F9803E405 S31500005BB040F90032400C980364C0E94822520818A4 S31500005BC00B280470000000002801A400F9203E40C4 S31500005BD00F9903E400F1003C402F9103E604D980BD S31500005BE0BE600F9C03CA0060000000002810A000E1 S31500005BF0F80C3E318F8803E000C8103A100EC083BF S31500005C00B010EC2033041881C3CA04200000000041 S31500005C1028053840BE812F820BE022E8008A8022C8 S31500005C209008A0022A008AC0A3A01AE802CA00406F S31500005C300000000028054000B2402CE00B2002CEF8 S31500005C4000830028C80A3C028E00230020C00920D9 S31500005C5002CA005000000000A0011000B4402D80D0 S31500005C600B4002C700870021C008408210208440F4 S31500005C7023000A7002E8004000000000A808120095 S31500005C80F4843DE00F4803D602CF8039E00EF803D6 S31500005C909E00EF8071E00D7843EA020000000000EC S31500005CA0081DA020FA003E814F8003E400FB003E61 S31500005CB0C00F8003E000F8007E000FB003C206604C S31500005CC0000000000005F600FE803FE00FF903FE2D S31500005CD000CF8037E00DF8033E00C7A073E08CF9D3 S31500005CE00300007000000000A8119004B4422D8447 S31500005CF00B5082DC00DF0023C40840023000842001 S31500005D006308087102AA0460000000000000940005 S31500005D10B4102DD20B5002D4008500258009D00284 S31500005D2094008D3469E068F00280002000000000D5 S31500005D302014C180B2402C200B1802C5008180209F S31500005D40800828122904828820100810028804304E S31500005D5000000000A815A320FB403C400F8803ED7F S31500005D60828B2034D005BA02AC92CB22BAF0001056 S31500005D7003AA0460000000008000E104F9403E919F S31500005D800F9003E408FB403EC80F800BE100F84289 S31500005D902E0D0F9001E00030000000000110F00011 S31500005DA0CD9833410CD003E420F60033400CF003C9 S31500005DB03820EF003384CFD02300443000000000A9 S31500005DC08104418A83C022B02A9802E400BA0022E4 S31500005DD0600D800225008040A2400B9002A040107A S31500005DE0000000008005200089002260088882ECFF S31500005DF000BB0822C40820822C20AA0022420B984D S31500005E00822000400000000008042000890020C015 S31500005E10081002CC009300A2C009100A00008900F5 S31500005E2020800B900282010000000000000D60003F S31500005E308800B2400C9003E400F80032000C8007A2 S31500005E402008E80032000FB00300035000000000F5 S31500005E50A01DF000FC003F400FD023F4007C003F63 S31500005E6000057003FC007F023FC00F5003E8067078 S31500005E7000000000C005FC88FF0035200CE80BF68A S31500005E8000DC0033200D78031200C4813F208CC84B S31500005E9003300070000000008010EC60BFC02221BB S31500005EA00032CA242889942A2008B843A610A8805C S31500005EB02E600A8802A00430000000008805CC800D S31500005EC0B31026400802128C10B10022800930025D S31500005ED0620080002E8008A80222017000000000E7 S31500005EE0C015AC00BB04224028B8022C80A980AAA9 S31500005EF0A0009802AC00A9002E000AA102B004601E S31500005F00000000004015EC00FB0034240C8813A5AB S31500005F1002F8C032320DB8034000C8203C000C180D S31500005F202310047000000000E001BC00FF003FA049 S31500005F304FF00BF600D100BF000FF003F050FE103B S31500005F403FC00FC003F80060000000004010AC0422 S31500005F50F30432400C80172D02C90032000CB8033E S31500005F602040C84232C00F9003D004200000000039 S31500005F70C8053C80BF0022C008BC0A2E00092020AC S31500005F80000D0D22A8008B8836C80B8A02F200404D S31500005F9000000000E0054C00B300A0800891C22478 S31500005FA0C2004C28928A30020A00830020000B00AF S31500005FB002F800500000000020011E00B3842320D8 S31500005FC02849021E06858021A01B7902B6008E8014 S31500005FD025700B5802C800400000000048080C005D S31500005FE0B30230900C040A2C04C140B8800E310371 S31500005FF00802C30030840F2003D202000000000014 S31500006000401DBC00FF083F0203E01BFC027D123D61 S31500006010800DD101FC40FF403F030FF803D006601E S3150000602000000000A805EC00CB6032D80F901B24BE S3150000603008C00530000CB0032F80C9203E0A0BB003 S3150000604003EA00700000000048119C80832821C4E8 S315000060500B60021000C70021000A700295408640BE S315000060602DC8097502D2046000000000C0008E40F1 S31500006070878021E00BD8023F089680212009D8228C S315000060803E0085A22DE80B7A02F0002000000000F9 S315000060904814EC01830020F28BA8022F0483882089 S315000060A0560B04128C0083802CC0093B42D204306C S315000060B000000000E815A800CA0032B80FEB03394B S315000060C000DEE0B3B00DE6032902CA883E940FA8AD S315000060D003FA0460000000004800E006F000BE007D S315000060E00F8043E10AF8403E008E8603E120F84027 S315000060F03E00078403D20030000000000810E600CE S31500006100C900F2400F9003E420E19032400E901354 S315000061102400F9003E400F9903C20430000000003D S3150000612080046600890022F80B962A260089C02082 S3150000613048081203ED24BBD82EC00BB002E00010B5 S315000061400000000018052440898022440B9202EECC S3150000615025A94022401A90022400B9002E400B9037 S3150000616082C60040000000000804050281002040AD S315000061700B140205018100A240081002C400B104FC S315000061802C404B1002C2010000000000B80D620056 S31500006190C88222000F800BE002E88032000E8003E6 S315000061A02000F8023E000F8003EE035000000000BE S315000061B0981DF700F9403E400F5802DE047D403F2F S315000061C0404F5001C400F9003E400F9003E60670B0 S315000061D0000000001801D400CD00164007D003F4DB S315000061E000CD0413400ED0016410F9003EC00F909C S315000061F043C60070000000003810E00088003281BD S315000062000B206220088A0022800A80022000BA0041 S315000062102E008B8000CE0430000000000805C4006C S3150000622081002440093002C400810222C00A100203 S315000062300400B1002C408B1000C201700000000069 S3150000624018158400890026400B1012245A89808272 S31500006250448A96022400B9002E461B9002C60460AA S3150000626000000000A015E402C90436500D9413E6A0 S3150000627002C140306046940B2440F9007E505F987E S3150000628003E80470000000002801A400F1003A4071 S315000062900F9A0BE400F9003E600F9023E600F90028 S315000062A07E400F9203CA0060000000002810A00084 S315000062B0E80032100F84A3E302D84032120C824366 S315000062C02000F84036000F8003CA042000000000BA S315000062D0280528008A08A2860BE00A38008E0037B7 S315000062E080086C93EB10BA402EB80BA502CA00408A S315000062F00000000028054600A38020C01B304A6E1F S3150000630050931028C00A18060C80B32024E80B38D6 S3150000631002CA005000000000A0013C288301A1C071 S315000063200B70021C0582002DC01AD026D420350021 S315000063302D400B5422E8004000000000A8081E80F3 S31500006340E58021A00F780B7200D48039E02E580327 S315000063501A40F69035E20F7803EA020000000000CA S31500006360081DAD24F9003E8A0FB00BE408F800B40E S31500006370C00D1003E000FA203E480FB403C20660C9 S31500006380000000000005DE20CD8203E40FFB03DEE3 S3150000639010DF8035610C58033E00FF803FA00EFCE5 S315000063A003C0107000000000A8119C008520B1C237 S315000063B00BE3121402E66021080F50021420B540C8 S315000063C02D900B5002EA04600000000000009400CB S315000063D0850221408B7386B0028601274008D002D1 S315000063E01800B6102D820B4802C0002000000000E5 S315000063F02014CC00810024400BB0022480A0002091 S31500006400500B14024200B2002C881B0402C8043050 S3150000641000000000A815BC00C30032400FB803A45A S3150000642080CA84B6510C1C032C40FB403EE11EA4DE S3150000643003EA0460000000008000E400FB013A402B S315000064400FB403A502FA303E120EBC83AD00F9501C S315000064503E101F8003E00030000000000110DC0049 S31500006460D90033100FF08BB004F200374002D0038E S315000064703E00FD283FC44FF093C0443000000000AA S3150000648081046C40A900A2000BB8A227008A8020D4 S315000064902008BC03ED00B9C02E300BB082E04010DE S315000064A00000000080052C00990022900B9102222A S315000064B02ABA80A6700AB8862180BA002E418BA01F S315000064C002E000400000000008040C00A10020804B S315000064D00B30020401820022000AB026C001B0007F S315000064E00C000B0002C2010000000000000D7C0041 S315000064F0D90022000FB00B2002FA0436400EB0037A S315000065002000F8001E400F8003C00350000000006A S31500006510A01DF400FD002F000FF003F404FC003F63 S31500006520400DE003F000FC003F000FC023E80670BA S3150000653000000000C005FC08CF00B3640C482330FF S3150000654060FC1833000CC0033000CF8033E00FE04E S315000065500330007000000000C010F4608F6022C09D S315000065600898020180B960224828200221008B0089 S3150000657020C00BA00220003000000000C805CC801F S31500006580811D20C00810120401B20020022810024A S315000065900C40810020C08BA0022201700000000088 S315000065A0C0158402890022C00898022400B301287D S315000065B0C248B10207008301A2C14BA002300460A9 S315000065C0000000000015F400C50032C40C9C022B2C S315000065D028F818B2800C8C032E00CB8022E00FE046 S315000065E00B00007000000000E001BC02F9003FC093 S315000065F00FF003F900FD0136040FD80BF402FFA0DB S315000066003FE40FA083F80460000000004010A422BD S31500006610EB1832C00EB4232C60CA013EC02CA40372 S315000066202D00DB003AC08CA02310042000000000DF S31500006630D8012E008B80A2DC8C300A26108B502EBF S31500006640E008B00224008B042250086402320040A5 S3150000665000000000E0054C02B30422D00A10020339 S315000066600090116C2208800A0400930028F2082981 S315000066700230000000000000F80116229790A1E009 S3150000668008D902120295822D2208580236008F84FC S3150000669021E74868060800000000000048082C8032 S315000066A0F110B2C40E14030400D2023CC88C2403B9 S315000066B00C00D30038C42C20031206000000000092 S315000066C0401DB602ED903FC00CD003FD00EF513FD8 S315000066D0C00FF103DC00F7003FC40FE013D0062023 S315000066E000000000A805E422C90D32C10FB003293D S315000066F000F880B2208C8003EC02CB48B2CA0CA111 S315000067000302007000000000C8119C008100A1C0B7 S315000067100B70029C00B2002000085022DC00A7008B S3150000672021C008E0035200600000000080008600DF S31500006730878021E20BF8021A21B5C021E0486822C1 S31500006740CE00878821E008680208102000000000BB S315000067504814CC12839022E00B38828E91B30060ED S31500006760F2683C02CE00AB8120E00820025A0430D9 S3150000677000000000E815AA02CE00B2A00FE48228AD S3150000678004FAC2339804ED83F960CA0030A028E009 S31500006790033A0020000000004800C140F0003E001F S315000067A00F8003E008B8643E110F0003E000F80014 S315000067B03E040F8043D20420000000000810E68249 S315000067C0C990B2680C9C032C80FB143E404F90236A S315000067D02400CBA032C00C98030204200000000065 S315000067E0800467108980A2600818022490B9402EA0 S315000067F0640B900A2500898022500815022000109B S3150000680000000000180524008900224009900A248F S3150000681000B9002E400B9002050289002250089410 S31500006820020600400000000008040D048340A0504A S315000068300990020480B3202CC84B12020480810008 S31500006840224028928202110000000000B80D620268 S31500006850C88032802D80032340F8D03E340F880351 S315000068602200C000B0000C870B2E0750000000006D S31500006870981DF7007DC03F600E5003E640F9900F6B S31500006880640FD383F4E0F9283E4A0FD803EE06706E S31500006890000000009805F702DDC037404CD0032405 S315000068A000C90032401C94032500C91032440CDA9A S315000068B003CE0070000000003800E3C088C4220048 S315000068C0088002200088002200288A0A2282888006 S315000068D02320280002C60430000000004805C4003A S315000068E09960264008904A040081012060085022E1 S315000068F016008520A148081402D2002000000000DE S3150000690018158C0089202260689402040281602296 S3150000691048489402140085002144189002C60420B9 S3150000692000000000A015E400D90034400C14032632 S3150000693020C900B2600898032608C90022600C909E S3150000694023E80020000000006801A420F90A3E4068 S315000069500F9203ED00FB003EC20F1A03E640F9A0BA S315000069603E400F9003DA0420000000002810A0002B S31500006970C800B2000E8001E100F84830000F8043E5 S315000069802000C80033000C80030A04200000000029 S315000069902805390086C0A3B208A002E880BAA02262 S315000069A0800BA0022A008A00238008E402820000ED S315000069B00000000028054D02828420080A1102CF3B S315000069C084B3C0A0F00B38020E02830020A0093E5B S315000069D00202005000000000A01114028608218067 S315000069E0085002D400B70021420B74021C20870015 S315000069F02190097C0288044000000000A8003E00A7 S31500006A00CE8433200E7803DE40F38431E00FF80B9A S31500006A103A00CD80B3E02D78030A020000000000A2 S31500006A200815A400F8003E000FB003E800FB203E66 S31500006A30080FB003E802F9003EC00EB003C20460BE S31500006A40000000004005FA00DC8033E00059033EF8 S31500006A5002CFC13FF08CD802B600C78133200CC8E4 S31500006A600B18002000000000A81190008C1021C017 S31500006A70085022182084002D8008D2823480871086 S31500006A8023042840036A0420000000000800980040 S31500006A909400234008D00A0C00A4102D4008540688 S31500006AA090008D002D6009C002400020000000000B S31500006AB06014C24083002020481C820B20A0C02CFA S31500006AC0102810028000A9002E4419200A50042024 S31500006AD000000000B815AC02DA00B2480C98822912 S31500006AE004E8212EB808A003AE82CAA03EA009B0D1 S31500006AF0036B0060000000008000C402FA003ED074 S31500006B00AF9003E0005B003C920FA0016C001A40BE S31500006B10B2800EB403E80430000000008010F400D8 S31500006B20CE0033C00FF0033640FF4A3E688CE003C8 S31500006B305800DC0233C004F000C1443000000000FD S31500006B4080047A108400A2B00B30022380BB402E52 S31500006B500088E02238008C40A3C0088102E0401083 S31500006B600000000080052880880122F10B90022495 S31500006B7000B8412ED009008264049A0C62000A8093 S31500006B8086E000500000000008040002800020C0DB S31500006B900B900A0000B0002C8028000A0400920026 S31500006BA020003A1012C2000000000000800D4010C4 S31500006BB0C80432C00F90032400F8003E400D804305 S31500006BC06002D80032408E8003C002100000000030 S31500006BD0A01DFC00FF003D800FD003F000FC013F2C S31500006BE0001FC003F000EC003F400D4003E80670B4 S31500006BF000000000C005FE00FC803F200EF80310D8 S31500006C0080FE801F600FD8033CC0DF003FC90CF038 S31500006C1003300070000000008010EE00B8810E20E6 S31500006C2008B8222B40BA812E200BA802BDC0CB800B S31500006C302FC408F412B00430000000008805CC0010 S31500006C40B0842E000A30128010B2002C400B1002C5 S31500006C500C0883002CC008340232017000000000CA S31500006C60C015AC00B8812E02889002AA00BA082E80 S31500006C70200B880AAC008B002EC008B002B004605E S31500006C80000000004015EC00F8803C400E2403A3F1 S31500006C9084FA041E680F18032C00CF003EC02CB0E7 S31500006CA00300047000000000E001BC40FC023FE469 S31500006CB08FF9237808FE0A3F400FF003EC02FF002D S31500006CC03FC00F3003F80060000000004010AE0027 S31500006CD0F80036000FAC03E900CAC03ED64FB0C379 S31500006CE08C02CB103EC00CB0031004200000000044 S31500006CF0C8052C00B84822808BB002EE0088802E92 S31500006D00900BB0023C008F802FC028F02236004046 S31500006D1000000000E0054400B0A024800B3000CA4B S31500006D204102402C700B31028C1293802EC0083029 S31500006D300A3A00500000000020011E10B48521A16F S31500006D400B7E02DE0086802D200B68021E40178017 S31500006D502CE40878023C00400000000048080C00C3 S31500006D60F10034C40F3403C040C2103C410F31035C S31500006D708C00D3003CC00C3003120200000000005F S31500006D80401DBC00F5003FC10FF203FC02FF003FAF S31500006D90C00F6103FC006F003FC00FF103D0066017 S31500006DA000000000A805CF80C2803A500F3C8368DF S31500006DB000FA013E400FB003ECC0EB0232C80CB241 S31500006DC0032A00700000000048119C40840021CC7A S31500006DD00B70221C00B6002D400B7002FCC0870011 S31500006DE035DB283682B2046000000000C000BE0019 S31500006DF0848829640BF8825A00B6C02DE00B78020D S31500006E00DE00A78028E0087802600020000000006D S31500006E104814CC0280C820D20B34060E41B182241D S31500006E20E00B3502CC0083002EC008B002D204303D S31500006E3000000000E815A800CE403AB00FA1037884 S31500006E4000FE803FA04F6403E800EA003A800CA0F1 S31500006E500B7A0460000000004800E010F8003E04D1 S31500006E600F8003E000F8043E148F8201C002F80090 S31500006E7036000F8003920030000000000810EF007B S31500006E80F9003E500FB023E420F98032620F9003E0 S31500006E902400D10036400C900202043000000000AD S31500006EA080046600B9002EF20B9402E400B1802241 S31500006EB0680B9002240089402240089002200010AE S31500006EC00000000018052400B9C02E40099182E494 S31500006ED000B91822440B90022400995126400890CC S31500006EE0068600400000000008040400B1002C41A2 S31500006EF00B1002C400B902A0400B900005008108E7 S31500006F00205028100682010000000000B80D600025 S31500006F10F8043E000D8003E200F80032004F800BBB S31500006F202200D82236202C880BAE03500000000029 S31500006F30981DE400FD003EC00F9043F500FD003FA4 S31500006F40408FD003E700F1003E504F9483660670F1 S31500006F50000000001805CC00FD003E410FD023F4D0 S31500006F6004CD003F404C50036400C98832500C9455 S31500006F7003260070000000003810E000B8002E0064 S31500006F800B8002E0008A002E000880420000884044 S31500006F90A2200888020E0430000000000805C40084 S31500006FA0B1002C400B3002C60081002A40081002B6 S31500006FB04400A100204018100212017000000000D9 S31500006FC01815A404B9642E404B9016E44A89022E83 S31500006FD0500890020400A9002240089002060460AE S31500006FE000000000A015E600F9403E501F9813C5AA S31500006FF000C94138402C10036402E90032402C904D S315000070000B280470000000002801AC40F9883E41BE S315000070101F9CB3E600F9243E680F9283E400D30078 S315000070203C400F1003DA0060000000002810A000AA S31500007030C84136104F8013E088F8483E004F800B59 S315000070402000C800B2004C800B0A0420000000009B S3150000705028012A228E8022880FE042FB00BE422FA2 S31500007060A08BE80228005A01228008A0020A0040EC S315000070700000000028054E00825024F20B1022CE9C S3150000708001B3402C620B14020C00832020C029306F S31500007090020A005000000000A0011E00848421C0E6 S315000070A00A5022DC20B7006D820BE4021C0091001E S315000070B021C009701228004000000000A8081E2008 S315000070C0C68035E00B5803DE00F5803DE00F58031F S315000070D01EC0C78830E00DF8032A02000000000039 S315000070E0081DAD80F2003EC00F8003EC00F9003EA3 S315000070F0000FA003ED80FB603EC00EB043C20660E9 S31500007100000000000005FE00FE8037F08F580B3EA1 S3150000711044F79033E00F78037E20CE803FE00CF8F2 S315000071200310007000000000A8119C80B61221C553 S315000071300B64021D04B61121800B42037C008400FF S315000071402DC00870022A04600000000000409C2840 S31500007150BE0021000B70021C01B510E1400BF006C9 S315000071605C0286002DC0087002440020000000006A S315000071702014CC00B203A0040B2C020C00B081201A S31500007180100B04024C0082002CC008300658043054 S3150000719000000000A815AE00F22032200FB7232E03 S315000071A020FBC830E00F34037C08CB003FC02CF036 S315000071B0036E0460000000008000EC00FA403A0014 S315000071C00FA003EC80F94D3EB20F8503AC00F90029 S315000071D03CC00F3003A00030000000000110FE008C S315000071E0FE0437400FF103DE40CC003F642CFA83E7 S315000071F01C00DCA13EC00CB003A40430000000005B S3150000720081046608BAA022408BB862ED00D8802EB1 S31500007210200884022C0888C22FC008F00220001023 S315000072200000000080012C48BA8026950B9002E8E9 S31500007230008BC02ED008A08A2C009B402EC008B020 S3150000724006A000400000000008440C10B300608057 S315000072500B0002C00090002C808810020C008100F8 S315000072602CC008300602010000000000000D6C0072 S31500007270FA00B6000F9003E804C8003E408CA00355 S315000072803C00D8013EC02CB003A003500000000013 S31500007290A01DFC00F6003F000FC023F000FC023FDB S315000072A0400FD003FC08FC023FC00FF003E8067055 S315000072B000000000C005FE00C58033080CF0033C4A S315000072C000CF003F210C48033200CC803F204FC046 S315000072D003700070000000008010CC008B002200BC S315000072E00880022000A00026E048B80A2E048B0081 S315000072F02CC00BB502200430000000008805EC000D S3150000730083002011083002000083002EC0081002FE S31500007310080093002CC00B90026201700000000070 S31500007320C015AC40830020084881022C00A809261D S315000073300008A0022500B8406E484BB080300460BB S31500007340000000000015CE00CB8032600CF0033C3C S3150000735008CF003C000CAC032C00DA003EE04F9056 S315000073600350047000000000E001BC06FF11BF409E S315000073700FC00BD008FC983FE40FDC03F000CD00F3 S315000073803FE00FF083F80060000000004010AC0101 S31500007390CB0036500CB013E002CB4032D48CB6038F S315000073A02500C9C83E828CB403D00420000000002A S315000073B0C8052C008B0022C0088002EC00888802D9 S315000073C0210D000208008A840EC0483C02F20040EB S315000073D000000000E0054C8083002480088002CC79 S315000073E000800020D2083D22060001420CF4401421 S315000073F002F8005000000000600116008F9021A0E6 S31500007400087802D2018780212089C9021A00868065 S315000074102DA0087882C800400000000048080C0033 S31500007420830036902C0403E004C020B0080C20032F S315000074300C22C2113CC02C1003D202000000000036 S31500007440401DB402FF042FD0CBF003FC48FF003DE3 S31500007450C00FD003D000FD003FC00FF003D0066080 S3150000746000000000A805EC00FB0032C00F80432C92 S3150000747002C800B0C00C90030A00CB007A408C9082 S31500007480036A00700000000048119C00BF00A14084 S315000074900B70021000A300290008600A140084087B S315000074A02DC008700212046000000000C0009600A3 S315000074B0B78021A00B4812421C04862120084C0AE2 S315000074C0322084802BE2293806700020000000005C S315000074D04814E400BB8020D00B301A6C10830028BF S315000074E0C00838020C0083102C1009320012043038 S315000074F000000000E815A800FA8032800FA002689C S3150000750000CA0032802C28032A00CA0039B04DE296 S31500007510237A0460000000004800E048F8103C0CA4 S315000075200FC003B000FC003F000FC003F002FC4098 S315000075303E020C8003D20030000000000810E40078 S31500007540D9A032C00C90032408C10132640D900307 S315000075506420F9803E682C98030204300000000085 S315000075608004640089C4225048942225108900347E S315000075707008980A2600B9D82E68089C0A200010C0 S315000075800000000018052400994122500810863595 S31500007590008D0023C209F1027480BD002EC00812BE S315000075A00206004000000000080405008140205843 S315000075B03856021582856025400850021400B50031 S315000075C02E4018128202010000000000B80D600073 S315000075D0D800B2200C080B2200C88032000DA00390 S315000075E06000FC513E140CA7032E0350000000005F S315000075F09809F600FD801E64079923E644F9913E3A S31500007600400F1000E400F9803D600FD803E60670D5 S31500007610000000009805E400811032401C9E83267D S3150000762000C99833402CD0233400CD0033400FD00E S3150000763003060070000000003810E28088A0A2A0B7 S31500007640288E020A828CC022000880022000880050 S31500007650220009800A0E0430000000000805D4202C S315000076608500214208520215308520A24108100AE1 S315000076702400810128600B10060201700000000042 S31500007680181584108500214048D01A144885032215 S31500007690420890C2248281402A40C99006060460AE S315000076A000000000A015E402C9803240089023249F S315000076B000C90022400C90030400C9503A400F92C2 S315000076C003280470000000002801A480F9203E442D S315000076D00F100BE400F9003E650F9003E600F980F9 S315000076E0B6520F9203CA0060000000002810A001E5 S315000076F0C80032000C80032002CC0032140C800338 S315000077002000F86132002C8001CA0420000000002D S31500007710280528018A00228008A04228108E02210E S31500007720802D6C022A80BE8023B000E182CA004010 S315000077300000000028054E088301A0E08838420EAC S3150000774000828020C088360A0E04B3C084F008BCCC S3150000775002CA005000000000A00119008F0021D0CD S315000077600874021C208642218009D4021C00B50838 S3150000777025E2087002E8004000000000A8083E026A S31500007780848033A02CE80B1A04CE80B1A00C7803B9 S315000077901E04FF8037604C7843EA020000000000B8 S315000077A0081DA800F8043E800FA003E800FA003C7C S315000077B0000F1001EC00F9003A400FB003C206605A S315000077C0000000004005F600FF803F600FD803363A S315000077D000CC8031E00CF843FE00FFA03FE00FF83C S315000077E003C0007000000000A8119010B7002D42E1 S315000077F00B518A1404A4052106285422DC10B5086E S315000078002DC40B7592EA046000000000000094008D S31500007810B4082D100B000210009080218008710220 S31500007820DC60B7222D400B7002C000200000000073 S315000078306814C200B0002C000B04120100B0B02086 S3150000784012281806CD80B2406CA20B0402C8043080 S3150000785000000000B815AC20FB003EC00FBD032E93 S3150000786080DB40B0B02C3483ED00FAC03EB20F840A S3150000787003EA0460000000008000E808FB003CC149 S315000078800F3003CC20EB403E900F9603EC00B8205F S315000078903E900F8013E00030000000008010FC00D6 S315000078A0FC007F800CE0032800C70033008CFC033B S315000078B07C00FE1133240FC183C044300000000059 S315000078C081007800BC002F8008E0037808DF4022A2 S315000078D0320890032E00B18122000B8C02E040108A S315000078E00000000080012410BB012E4008901224E5 S315000078F000890822A108B0026C80BA0822900B8089 S3150000790002E000400000000008040001B3006C40E3 S3150000791028100244029100A0002810020C00B800B2 S31500007920A0401B2002C2010000000000800D640080 S31500007930F8002E000C800B2000C90132002C902389 S315000079406C00F80032000F9003C0035000000000E6 S31500007950A01DF000FC001F000FC003F008FD003F53 S31500007960000FC023B400FC003F000FC003E8067000 S3150000797000000000C001FE00CF103BE40CD203184B S31500007980C0CC8033E00CF9033E40CFC033E02CF886 S3150000799003300070000000008010EC028744A0C095 S315000079A04817823880A02028C028B0022C848B205B S315000079B028CB08B08A200430000000008805CCA03F S315000079C083602A8808100208C0A00822C20832066E S315000079D00C8083A020C81A3002220170000000002B S315000079E0C0158C008B0122A1A89082080028002ACD S315000079F0C008B4020C608B0028C00A340230046050 S31500007A00000000004011EC80CB0038B04CAD0B28D4 S31500007A1000E80032E80CB5032F18CB0032EC06B8AC S31500007A200310047000000000E001BC00FF003F806E S31500007A300FF043F800FC103DC80FF803FC10FF9050 S31500007A403FC00DF113F80060000000004010AC01CB S31500007A50C30032900CB0032800C82032C00CB0031B S31500007A602C00FB0032C00CB40B10042000000000F8 S31500007A70C8052C048F01E2A808B003780088C03638 S31500007A80C00DB0012C00BB0022C008B0023200407D S31500007A9000000000E0054C018300208008901208D9 S31500007AA08028C020C008B0020C00BB0020C02330D4 S31500007AB0027800500000000020011E0087A5212446 S31500007AC01858067A02A48925E00978021E40B78074 S31500007AD021E00B78024800400000000048080C0036 S31500007AE08300A0940C300B0800E00030C04CB009B5 S31500007AF00C44FB00B0C00FB00352020000000000AF S31500007B00401D9C00FF201F8427F103F8405C003FC6 S31500007B10C007F013FC50FF003FC00CF8039006604E S31500007B2000000000A805EF80CB30B2804CB20328DD S31500007B3000E08832C00FB01B2E00CB0032C00CB064 S31500007B40032A007000000000481198408F08218128 S31500007B504820CB48C0A40029C00B700A3C0087000F S31500007B6021C0A8700A92046000000000C0009E00B8 S31500007B70878021A0087C021AC0AC8025E00B780221 S31500007B809E01978021E088680230002000000000F6 S31500007B904814CC068B00209088B0024802A2012D22 S31500007BA0200BC89213009410212008C702920430BB S31500007BB000000000E815A800CA00B1802CA0031838 S31500007BC002EA8836A20FA403AB83DA0032A80CAC13 S31500007BD0033A0460000000004800E080F8003E0818 S31500007BE00F809BE004F8003A090F8143E080E880AB S31500007BF0BE200F8013D20030000000000810EC00F9 S31500007C00F90032400DBA132400CB003E400C90011F S31500007C102400F90032402C900302043000000000DA S31500007C2080046504B9012250089802240089402E78 S31500007C30400890122400B9002240489003600010CA S31500007C400000000018052420B900225009900224E3 S31500007C500289402D4008D002B405B500214008D065 S31500007C60020600400000000008040500B340225050 S31500007C70081402250081406D5028540A9500B5402D S31500007C80A15008540242010000000000B80D400057 S31500007C90F880B0004D880B2208C8022E000C0003A5 S31500007CA0A000F00030000C40032E0350000000003E S31500007CB0981DE60CF9C11F608B9C23F700B9803E26 S31500007CC0600FB8036600B9803E600F9803E6067041 S31500007CD0000000001805F400C9003AC00C90032407 S31500007CE004C90032400F9003A404C90532410C9028 S31500007CF003060070000000003810E2808880A22889 S31500007D00280A02A2008C84A2800B800208008A0046 S31500007D1028000880020E0430000000000805C42078 S31500007D20852829420850821420A50820400B1002FD S31500007D308400A1002040181002020170000000001B S31500007D40181184208D0161400878829400A50022D4 S31500007D50480B1002A600A1002A4008900206046003 S31500007D6000000000A015E402C900BA5C4C90032490 S31500007D7002690032500F9403A400E9403242249273 S31500007D8003280470000000002801A400F1003E60F2 S31500007D900F902BE400D9203E400F9C036402D9C00B S31500007DA03E688F920BCA0060000000002810A101F7 S31500007DB0C8023E104D800B2002CC0032102C8003EE S31500007DC0E000D840B2100C84030A04200000000032 S31500007DD028052800AA002E8008A0022A00DE01221B S31500007DE0800DA000E8088A00228048A00A0A004008 S31500007DF0000000002805440083046CC00930120C02 S31500007E0000228060C0083042EC10130022C00BB084 S31500007E10060A005000000000A0013410A7006F40C1 S31500007E200870061820B64021EC497000DC00871463 S31500007E3021C80B730628004000000000A8081200A5 S31500007E4086803DA10D58033E00EF80B3E82C7A03EF S31500007E50DE80DF8031F82FFA032A020000000000DE S31500007E60081D80003A003C000F9003E800DB023E4C S31500007E70DA07B413EC60FB403ED00CB403C20660D4 S31500007E80000000000005F602CF8031E00DF8033651 S31500007E9000E48033E00CFC833EC0CFC033F00CFC22 S31500007EA00300007000000000A81194408F012141DA S31500007EB00870221008840221C80DF0423C428F004F S31500007EC023C008F1022A04600000000000009000B0 S31500007ED0860023860811021402BD8023C1087002A1 S31500007EE01C91A71021C0287082000020000000000D S31500007EF02014C0208A00620008100200029980A0A7 S31500007F00F009B0028F47A34022D418380208043083 S31500007F1000000000A815A500C90032E00CA42B2C17 S31500007F2004FA24B3F20CFE4B3D40EF48B3F02CF8B4 S31500007F304B2A0460000000008000E400F9063E4081 S31500007F40AE2403E800EA003EC00FB0036C005B00FD S31500007F503EC10FB013E00030000000000110F00039 S31500007F60CC0037802CC0830C04CF0032C20FF089BE S31500007F703C10CF08B3C200F00300443000000000FC S31500007F80810470088C81230028C40A38048F0036C7 S31500007F90C00BB0122C028B0122C008B00220401088 S31500007FA00000000080050400892022C018A01A24C1 S31500007FB000880022C00BB0028C00830022C00A3069 S31500007FC00220004000000000080404008100204157 S31500007FD02820020003800024C00B30428C0283005C S31500007FE020C10A300A02010000000000000D400016 S31500007FF0C80132802C8023240AC90133C00FF00344 S31500008000BC00CF0433C02EF0030003500000000074 S31500008010A019F000FC003F000FC003F000FD003F78 S31500008020C00FF0037C00FF003FC00DF003E80670B0 S3150000803000000000C005F080F48033000D6813B026 S3150000804028FE2137040FD003F208CC013F010CD0E3 S3150000805023700070000000008010E1A0B880A01A14 S3150000806008B8020128B200A2900B90526800820064 S315000080702E00089002200430000000008805C44944 S31500008080B000001009B0028080BA6A244D0B30029D S31500008090E800A0012C4018100262017000000000E8 S315000080A0C015A440B880220008B0022000BA002201 S315000080B0CA03B0026800AB222C400810823004606C S315000080C0000000004015E180F0CC32280DB603A573 S315000080D000F20136000FD803CA02E8C83F2008D5CF S315000080E00350047000000000E001B000FC003F30C7 S315000080F00FF003F688FE003FA00F9103FB02DD8020 S315000081003E050F9803F80060000000004010A5002F S31500008110F80C30140CB8136403CA0832580FA203C3 S31500008120A800FA403B400D96031004200000000012 S31500008130C8052D00B8C022C008380228688EC022A3 S31500008140E00BA80228003B0022400D90823200403E S3150000815000000000E00549C0B001A0D20830124B73 S315000081600882C120340B3C008800B1002880082C0E S315000081700A3800500000000020011A80BC8021E06F S315000081800878021A08869821A04B78861A40B5907E S3150000819021A00969120800400000000048080C40B0 S315000081A0F20830C10C320348848200B0400F32031B S315000081B08800F20038C00C21031202000000000003 S315000081C0401DBCC0FE003F400FF003F400FE083F18 S315000081D0840FF013F800FF043FC40FE903D00660D4 S315000081E000000000A805E880C00032C80F300B6F01 S315000081F008D2033A100CF0030800E800328004A805 S31500008200032A007000000000481184308400218396 S315000082100B71020C288620214208700A180485007A S31500008220218028200212046000000000C0009A0489 S315000082308E8221E20B78221E008EA029E0092802F8 S315000082403B04A68060E028680230002000000000A1 S315000082504814CE808322A0E00B30820E408200209C S31500008260F00920820A0083C0A2C00820421204300E S3150000827000000000E815A882CE4432810F240328AE S3150000828016CE023AA43D64033A00EE1832800CE0A2 S315000082900B3A0460000000004800E100F8003E02CE S315000082A00F8003A080E8003C144E8403E000F00039 S315000082B07E000FC003D20030000000000810EE80E0 S315000082C0D90036E00FB0136E00F92032E80C902B7F S315000082D02400E9003240AC9002C2043000000000E5 S315000082E08004648081C022520B900A2760B184A268 S315000082F07008904225008940A250889042E0001004 S315000083000000000018050404998226480B900A6CA8 S3150000831000B90022500896020500A908225008D08C S3150000832002C6004000000000080404808180204846 S315000083300B10020481BB2020481892020400A120E1 S315000083402148685200C2010000000000B80D6340D9 S31500008350D80036340F80036340F8D030342C8D0BB0 S315000083602000E08032200CC803EE0350000000001D S31500008370981DE640FF003EE40F9003E640FD903E68 S31500008380E44FF903F4B0DD383E4E0F9383E60670F2 S31500008390000000001805E400FD003E400FD00B244D S315000083A010C9043E400FD8432440C910327A0498BD S315000083B003060070000000003810E000B8002E0030 S315000083C00B8002200080002E000B0002228288A073 S315000083D0A2B828C8120E0430000000000805C40028 S315000083E0B3022C400B18020E0081002C400B140225 S315000083F014008500214808568A020170000000001A S315000084001815A408B9102E410B9002060089002EFB S31500008410400B104204808D80214008500206046003 S3150000842000000000A015E424F9852E700B9013249B S3150000843002C9003E700F9C432600C90832500C90BA S3150000844003280470000000002801AF00F9003EC8B0 S315000084500F9003EC00FB003EC88F9C1BE604F10066 S315000084603E400F9003CA0060000000002810A18063 S31500008470F800B2000F80032200F80832180C84833B S315000084802000E84032102CC0030A0420000000003F S3150000849028052900BE5022920B61022800BA6222EA S315000084A08008E0436A008A00228008E0020A004051 S315000084B00000000028054F00B30020C80B34020C52 S315000084C008B3C120D48831020E00A38024E0082816 S315000084D0020A005000000000A0011420BF8021C045 S315000084E08B70021001B78021E00870025C30874073 S315000084F025C208640228004000000000A8081E00EB S31500008500F78021E40F78031E20F788B0602C7803EB S315000085103A00EE80B4A00CE80B2A0200000000002E S31500008520081DAC00F3003E400F300BE000F9063E9C S31500008530800FB003E804FA003A800FA003C2066079 S31500008540000000000005FF00FF80336084E803FEA2 S3150000855010FC8133B10BFB0B3600CD8237600CC8A3 S3150000856001C0007000000000A8119800B7002104A7 S31500008570286442DD409700A19809750234408D2099 S315000085806140084002EA0460000000000000980014 S31500008590B7102180086402D000B50021C00B72021A S315000085A0500084406500084902C000200000000019 S315000085B02014C920B100A000082002C0809100202C S315000085C090098042400080002000088802C80430DC S315000085D000000000A815A920F14032A40C3023EDBC S315000085E000F30432D00F80036C02CBA036C02CBC43 S315000085F003EA0460000000008000C400F9403E4425 S315000086000F9403CC40DA403E150D8003AC40FB04CA S315000086103EC01FB583E00030000000000110F400EA S31500008620CD0833E00FF8033000D800B3420CC10385 S31500008630B800FE0034800CF01380443000000000C7 S315000086408104644889C8225D0B980A230888802221 S3150000865001088C0A3800BE002F8008F40220401062 S315000086600000000080052020898022800BB2122C99 S31500008670408A282060088002A408B9002E4008908D S3150000868082A00040000000000804000280002000D4 S315000086900B10020C028A00200008000A0400B10038 S315000086A02C4028100202010000000000000D6000AE S315000086B0C900B0800FB0032000C800B2402C3003C0 S315000086C0A000F80036000C90038003500000000064 S315000086D0A01DF000F5011F000FD002F000FC003FC6 S315000086E0000FC003F000FC013F000FD023E8067026 S315000086F000000000C005FA00C7813F610EF803FCC8 S3150000870040C4803F210CC8033200FF3033CE0C48F2 S3150000871003F00070000000008010EA008B802E40FD S31500008720289802EDD0A8802E2008B8022200BF703B S3150000873023D8089802E00430000000008805C00233 S3150000874083002C420A0002CC0880002E408880025A S315000087500000B30420C0082002E2017000000000FF S31500008760C011A0008B122E4408B002EC01A9200E05 S315000087704808B0122000B30022C1089002F004603D S31500008780000000004011EC80CB083E700EB003ECF8 S3150000879000CB813CA00C00072000FB0132C02C80DE S315000087A003D0047000000000E001BC0CFF803F60B5 S315000087B00FFC03FC00FD803FA10FC003FA81FB0004 S315000087C03EC05FE003F80060000000004010A50016 S315000087D0FB20B2580D80072C10CA0072400FB00360 S315000087E0E408FB00B2C02CB0031004200000000017 S315000087F0C8050540BB80224208B0073C00C90002FC S31500008800400EBA02EC00BF0037C048B00372004009 S3150000881000000000E0054E00B14022F04930026C35 S3150000882000800868090B0A12CC00A30022C0880049 S31500008830063800500000000020011E20B59865E4AF S315000088400858061EC18E80A9600A7846D680B7846D S3150000885025E008D80648004000000000480804004B S31500008860B11032C00D00126C82C00028840F0303C1 S31500008870C940F30030C02C200312020000000000A3 S31500008880401DB400FD100BC00F7003FC80FF503775 S31500008890F00FF903F2C0FF103FC40FD003D00660FB S315000088A000000000A805EE00C18032802C9A032C3F S315000088B000EB403E900D8283EE88CB3032CC8C8329 S315000088C083EA00700000000048119C00D504238054 S315000088D00870821C8087602DD90B4012DCA083149F S315000088E028CC086002D2046000000000C000A60088 S315000088F0858021A00858021E40A6802DAA097F0265 S31500008900FEC087A021E8087A02F0002000000000DF S315000089104814C43090042290482C0A2C00A3C02C82 S31500008920C00B3802CD008301AAC0283402D204301D S3150000893000000000E815A800CA50B2900CAD8328CC S3150000894010EA223EA00DAC03EB22CA0032806CA9CD S3150000895003FA0460000000004800F010F8003F0829 S315000089600F8400E01618003E01038013E080F0003B S315000089703E008F8103D20030000000000810E600A0 S31500008980F9003E400CB003E410C9A83E680F908081 S31500008990E600F90112400C9803C204300000000002 S315000089A080046780B9902E72489902E4128B802E5B S315000089B0E00BB002ED00B900A2402ABD02E00010B3 S315000089C00000000018053440BD012FC808B002E4BD S315000089D00289022EC00B9002E464B9002A40089472 S315000089E002C600400000000008041400B7002D5025 S315000089F0283042C50481802CC00B1002C414B14338 S31500008A0088504A1002C2010000000000B80D600044 S31500008A10F8023F000C8023C200C8013E000F80030D S31500008A20E000F8843A200C8003EE035000000000BA S31500008A30981DE400B9003E612F1003E704F9003EDB S31500008A4040039013C404F9C036700F9003E6067015 S31500008A50000000001805F400CD003F400ED003E4EE S31500008A6000C9003E410F9003E400F90032410C902A S31500008A7003C60070000000003810E01288002E00C7 S31500008A8088A002C000A8042E800B8002E004B80073 S31500008A90A2000FA002CE0430000000000805C400AA S31500008AA0A1002C400A1006C40081002C408B18023D S31500008AB0CC00B1002840281002C20170000000005E S31500008AC01815A600A9402E40089006E400A9000E3D S31500008AD0400B9206EC00B10028400B9802C60460D9 S31500008AE000000000A015E400E9413E402E9803E492 S31500008AF000C9601E705F9003E590F9003A400C9043 S31500008B0003E80470000000002801A404D9003E40D8 S31500008B100F9403C402F9003E500F9007E400F900D9 S31500008B20B6400F9003CA0060000000002810A200A3 S31500008B30D8203A000C8003A000C8403E000F8003F6 S31500008B40E104F800B2000C8203CA04200000000011 S31500008B50280518800EC027B80AE002E8008AF42625 S31500008B60A80BA4226940BA00028008A402CA0040E9 S31500008B70000000002805420090922AF2080E048C9C S31500008B800283C02CC00B3F02CC00B30420C048387F S31500008B9042CA005000000000A00110008600258097 S31500008BA00A4082DC81870025805B60025C04B73066 S31500008BB021CC087082E8004000000000A8081200DE S31500008BC0D6813BE02C48039F40C4803D614F7843EB S31500008BD0DE00FF8A33E02C7803EA02000000000082 S31500008BE0081D8000FA0036800F8003EC00F9403E35 S31500008BF0100FA0036DA0FB213EDA2FB683C20660DC S31500008C00000000000005D600C680B3A02C48037EF5 S31500008C1090DFD03FF00FFC03F600FF8033E02CE836 S31500008C2003C0007000000000A81190008600230712 S31500008C300840835C0096002D800B5502D448B7127D S31500008C4021C80D6002EA04600000000000009100E7 S31500008C508600210008E0029C8496046D640B78026D S31500008C60D200B70020C0184002C00020000000005B S31500008C702014C80483002212082402CC10920C6C23 S31500008C80030B1606C204BB0020C1390002C804301B S31500008C9000000000A8158080C20032F0AC8403BC3E S31500008CA000DB803ED00F9C03E800FF0033C00C9C25 S31500008CB003EA0460000000008000E002FA083E803B S31500008CC00F80016C003B103ED0038103E840FB049B S31500008CD03EC10F9183E00030000000000110F0005B S31500008CE0DE0133C00CC083DC00CC233FA00FD801CB S31500008CF0F240FB0031C00CE903C044300000000024 S31500008D00810462008A002AE0888E02EC0289002E25 S31500008D10A80B8D02E304BB0436C008AC02E0401089 S31500008D2000000000800526009A8022A2088802EC36 S31500008D300089002E448BA002EC00BB0222C04890A2 S31500008D40C2E0004000000000080400008200280085 S31500008D50280006CC0480002C401B0002CC04B30083 S31500008D60A4C0081002C2010000000000000D60004F S31500008D70DA0232808C9012FC02C8003E000FA0037B S31500008D80E000FF0133C0248003C003500000000050 S31500008D90A01DF004FF000F800FD023FC04FC003F51 S31500008DA0000FC003F000FF003FC00FC003E80670CD S31500008DB000000000C001D884DC0133080BC203B4F4 S31500008DC000DF003FC00FF0031200F48033200FC80D S31500008DD00330007000000000C010E92088C0208029 S31500008DE0082042240088802E010B80022C00BB0044 S31500008DF020C00BB002B0043000000000C805C8C097 S31500008E00914420110B0102884493002C000B300280 S31500008E100800BB0124000B100232017000000000A4 S31500008E20C015A8208904228208A08A280088002E5E S31500008E30C00380822400B80226C40B2002B004605E S31500008E40000000000015F900DC1033100FC403B455 S31500008E5002DF483FC007F00B2C00F8E036F20FB0F7 S31500008E600300047000000000F001B800F8843F80A1 S31500008E700FE003F402F8403F010F8903F000FF20E2 S31500008E803B200FC403F80060000000004010A9203A S31500008E90D90032100C84032820CB103A000C34037E S31500008EA02400CB0032C20CA00310042000000000F6 S31500008EB0D8052900812122A808AB022A808800361D S31500008EC0C00880022808800022000892137600401D S31500008ED000000000E0056D009280A2400894422741 S31500008EE002800020C00A00020480832420C00828D3 S31500008EF0823A005000000000F0011E02868421E044 S31500008F003878021600878024200A78023A118C905D S31500008F1001200858027C00400000000048080C00B0 S31500008F20D30030480C10032800C00420000E020BAA S31500008F300C02401110C82CB0031202000000000001 S31500008F40401DAC40FB003EC00FB103EA40FB1036AB S31500008F50C00DB003E0407B103E000F8403D00660D6 S31500008F6000000000A805EE10CA003A404C90032409 S31500008F7000D88032C02C800B2800CB8432204C9045 S31500008F80432A027000000000C8118C00860020C031 S31500008F900830021402A3002900087002340284017A S31500008FA021C00860023200600000000080009E00C0 S31500008FB087802D600858021A029480202009080232 S31500008FC052008480212008C80E20002000000000E6 S31500008FD04814CC00830024C008B0022800A3002A4D S31500008FE0C049B0124C44830020F2083C821204307F S31500008FF000000000E815A802CA003E802CA00B382D S3150000900006DA00B2800DA00B4800CA00B2B02C2CC4 S31500009010033A0460000000004800E000F0003A1146 S315000090200F8003F000FC003B000EC043B020FC00A4 S315000090303F040FC503D20030000000000810E60010 S31500009040F9A032400D9003640279203E682C9A0301 S315000090502408C9003E400F900B02043000000000B7 S3150000906080046500B98022580890122400D9802E09 S3150000907060089812240089002E400B9002201010E0 S315000090800000000018012480BD00214009D01A7498 S3150000909000B9042F4018D0063C008D002F400BD09D S315000090A0820600400000000008040D00B501614082 S315000090B00850021402B5202D4808522234028500B9 S315000090C02D408BD00202010000000000B80D6200A6 S315000090D0F880B2342D8D435340F8803E342C8D0BEE S315000090E02144C0503C140FC5032E0150000000005F S315000090F0981DE700F1402E700B9C13E704D9103E33 S31500009100644F9913E604F9803E600F3803E6047055 S31500009110000000009855F680FDA432780E9E0327C5 S3150000912020C98032620C98832500C94032400D90D8 S315000091300A260070000000003810E140BA402228DC S315000091400888423300A85020B0080E8202008A80A8 S31500009150222008CA820E0430000000004805C40020 S31500009160B11421500A540214008100214208500211 S3150000917014008500234A0950021201700000000005 S315000091801815A400B900224008D0023400A9002016 S31500009190C4087002148085802340085002060460CB S315000091A000000000A005E400F940B2404E900B26F6 S315000091B082C90012409C90032602C940B0400D941B S315000091C003280470000000006801A410F9003C4068 S315000091D02F100BE440F300BE402F900BE400F90083 S315000091E03E400F9003DA0060000000002800A00057 S315000091F0D850B2000D80033110C81032014C8003E4 S315000092002000C80032010CC0030A04200000000040 S3150000921028053A208680228008A00238008A00228B S315000092208008A0022A008A00228008E0020A004084 S315000092300000000028054480920020C00930022A60 S31500009240008381A8C028304A0E02838020E00828C7 S31500009250020A005000000000A00112008600214012 S315000092600840021822870069C0087002182086404C S31500009270219008640228004000000000A8080A00A7 S31500009280D28430A04D380B0A02C38039600C5803D3 S315000092901E00CF80B3E02CF80B2A0200000000006D S315000092A0081DA800FA001E000F8003E800FB003628 S315000092B0400F9003E800FA003E800FB003C206603C S315000092C0000000004005FE00FE8033E00FF803B208 S315000092D000CFC03FE00CF8033600CD8031600DC8EA S315000092E003D0007000000000A8119800B6102346B5 S315000092F048418A100087082DC428F00230608C107F S31500009300A104084102EA0460000000001000980071 S31500009310B600A1800A7002922287102C4008510ADA S31500009320140085002340095802C0002000000000F8 S315000093306814C808B2002200088002010083402C8D S3150000934050081402430080802200081806D8043012 S3150000935000000000A815A400FA0032E00EB843ACE5 S3150000936040CBC53EBD2CAF032D42CB4832CC0DA41D S3150000937083EA0460000000009000E000FA003E402E S315000093800E8003EC02FB203E900F2403A810FA2067 S315000093903E800FA203E00030000000008010F806B7 S315000093A0CA223F802CF00B2C02FF00310024C003A0 S315000093B0BC00DF0037C00CF003E004300000000002 S315000093C0800449808A802F0048C0023D2083903760 S315000093D01008C4123800BE002F8008F002E000100A S315000093E00000000080052C008A002EC038B0420420 S315000093F002BB042A800AA006A400B9012E400880F8 S3150000940002E000400000000008040C0082002C402E S31500009410080002040083002C800A20420004300069 S315000094202C00280002C2010000000000800D6C0024 S31500009430CA003E800C30132402FB003A010E800B5A S31500009440A400D90036400C9003E003500000000051 S31500009450A019FC00FC003F000FC003F402FD013719 S31500009460000DC003F000DC003F000FD003E80670DB S3150000947000000000C005F200FC803F208FE8177254 S3150000948000FD9033200CF0033210FC803F200FF2D9 S3150000949003300070000000008010E200B8802E202B S315000094A08BA802E200B12022200AF90A2200E980F4 S315000094B02EE00BF902200430000000008805C000F1 S315000094C0B3022C000B20028400B120200088300259 S315000094D0C000B0002C000B300262017000000000DA S315000094E0C015A400BB002EC00BA002E000B300A272 S315000094F0420AB0026040A8202EC203B00270046087 S31500009500000000004015E200F8023EC00FA0036212 S3150000951000FA00302004B003E000FA223E100FB03B S315000095200B50047000000000E001B288FD903FC0BF S315000095300FE022FF10FF423FB00F7003B000FF00A4 S315000095403FA90F3003B80060000000004010A800DB S31500009550F8003E004FA013E400FB0032100FB203E8 S315000095602D00F8003E100FB003100420000000008C S31500009570C8052C00B9042ED40BA802EC00BB00AA27 S31500009580C00BF2022E00B8802E880BF0023200408B S3150000959000000000E0054C00B0042C200B2102CA9C S315000095A000B30020C08B34000E04B0C82C000B3072 S315000095B0023800500000000020011A00B4902D204F S315000095C00B6802D200B790A9240B38021E20B5887A S315000095D02D600B78020800400000000048080D00CE S315000095E0F3003C020F2003CC20F10030C00F300303 S315000095F00900F3001C004F300B12020000000000AF S31500009600401DBC20FF803FE00FE001F0407F003F9F S31500009610400FF10BFA60FF023F660FF503D00660BC S3150000962000000000A805E700EA803AC00F282328BA S3150000963080CA0030E80CB6032788CAE132E00CB5D0 S31500009640032A00700000000048119040877021CA6C S315000096500B60035D40DF0021820A76A29440C76951 S3150000966029CC0A700212046000000000C000BE800F S31500009670AEA829240B68063F00978823F0087A02D3 S315000096803E209F8023EA083A0230002000000000B6 S315000096904814CC00830220F48B20024E809340A015 S315000096A0E00A30028C80830028E80A300212043077 S315000096B000000000E815AA00EA013A908FE00329AD S315000096C000DE0032804CA0232B02DA8832800CA008 S315000096D00B3A0460000000004800E040F8403E00FD S315000096E0078003E000F8203E100F0003E100E800C9 S315000096F03E000F0003D20030000000000810E40016 S31500009700F9C87E460F9103E508C90032E40F9A2393 S315000097102400F9003E480F900302043000000000C8 S3150000972080046D00BB006EE00B9202CF00A9002200 S31500009730700B94016D08BB002EC80B9003600010DF S315000097400000000018052400B9002E400B9002E42A S3150000975022A100A2420B94022401B9000E408B9074 S31500009760020600400000000008040C00B3002C4074 S315000097700B1002E400A14020400310004401B10494 S315000097802C408B100242010000000000B80D600062 S31500009790F8002E000F8003E000C80022000F8803A7 S315000097A02800F8003E004F880B2E035000000000F2 S315000097B0981DC410F1003E400FD001C4005D803EEC S315000097C040071401C400F3023C400F9403E6067000 S315000097D0000000001805E400F9003C400FD0032407 S315000097E000F90032400F90032400F9023E400F902A S315000097F003060070000000003810E000BA002E00DA S315000098008B80022800B80022008B8002A808B802CC S315000098102E000B80020E0430000000000805C40074 S31500009820B1010C400B90020400B100E0C00B1042E5 S315000098300400B3002C408B100A02017000000000E7 S315000098401815A440B9202E400B90022408B9102206 S31500009850500BB006A400BB002E400B90020604601D S3150000986000000000A015E520F9003E780F900B25BA S3150000987000F9E032504F90032500F9C03E400F90AA S3150000988003280470000000002801A408F9003E68BF S315000098900F9003E408F9003EC00F3003E700F9C05B S315000098A03E400F9003CA0060000000002810A00090 S315000098B0F8003E100D8003E080F840B2000F8803E8 S315000098C0212038603E000F00030A0420000000003B S315000098D028052B00BA802EB0086A02E900BA0022D9 S315000098E0808BA20A2B00BA422E800BA0034A0040AE S315000098F00000000028054F80B3A02CFC092602CCEE S3150000990000BB0064D80B38024C01B3002CF80B30B6 S31500009910020A005000000000A0011D00B7402FA061 S31500009920086002DC00BF0225C00B20025420B500EF S315000099302DC20B300268004000000000A8081E007F S31500009940F7803D600D7803DE00F78025E40F78038D S315000099505E00F7903DE40F78032A02000000000045 S31500009960081DACA0FB483E9A0FB003E5A0F3403AB1 S31500009970D00F9003A500F9403E500FB003C2066019 S31500009980000000000005FA00FE803FE00FC803FE5D S3150000999000CFC833A40CDC033B00FF803F200FF848 S315000099A003C0007000000000A8119800B6002DC981 S315000099B08B4002DC00D70035800862035900B400F2 S315000099C02D100B70026A0460000000000000980071 S315000099D0B5802D610B5002F8008F082140494006E2 S315000099E01E00B7002DF00B7002C000200000000022 S315000099F02014C820B10A2CE60B1022C1009B482473 S31500009A00440900024C00B00C2C600B3002480430B4 S31500009A1000000000A815AD00FB003EE00FA003E12A S31500009A2000CF8032402DB0012C00FA027EC80FB064 S31500009A3003EA0460000000008000ED00FB403E9059 S31500009A408FA003E960FB003E520E3003E500FA40AA S31500009A503ED00F3003E00030000000000110FA0095 S31500009A60FE003F400FF0073200FF04B3A00FD403FF S31500009A703880FEA03F800FF0030044300000000055 S31500009A8081046800BA002E800B38022100BB002238 S31500009A90A00BAC022000BA002E000BB00220401032 S31500009AA00000000080052460BA402EB00BB80264A6 S31500009AB060BB00220A0BA0022008B9002E000BB0E2 S31500009AC0022000400000000008040400B2002C80C0 S31500009AD00BB80A0C00B30020001B00020000B00007 S31500009AE02C000B300A02010000000000000D60008F S31500009AF0F8023E000FB0232000FF0032000F900353 S31500009B002000F9003E800FB0030003500000000063 S31500009B10A01DF000FC043F000FD003D000F7003D6D S31500009B20000F402BF000BC003F000FF003E806706A S31500009B300000000000C541037040DC1037040DC171 S31500009B40037040DC1037040DC1017040DC1037048F S31500009B500DC031000000000000C5440571015C40E5 S31500009B60571015C40571015440571015C4057100EE S31500009B704840571015C03150000000000080020117 S31500009B802080482012080482012080482012080400 S31500009B908201208048201208048020000000000076 S31500009BA00080000060005800160005800160005823 S31500009BB00016000500056000500006000580200024 S31500009BC00000000000C5480572015C80572015C8DA S31500009BD00572015C80572015C80572005480552017 S31500009BE015C031500000000000C54000600018009C S31500009BF00600018000600018000600018000604138 S31500009C0018000600018031000000000000C548046D S31500009C102201088042201088042201088042201078 S31500009C2080042001088042201080310000000000DE S31500009C3000C54A05428150A05428150A05428150A4 S31500009C40A0542815020140C150B0542C15003150C3 S31500009C500000000000800C01530055C01530054C73 S31500009C6001530055C01574054C01570040C0113012 S31500009C7004402000000000000080000040001000AA S31500009C80040001000040001000040001080060000C S31500009C9000000100004121000000000000C5600234 S31500009CA00800820020800820020800820020840824 S31500009CB02002280582002180084131500000000062 S31500009CC000C5400560015900560015800560015920 S31500009CD00056401580076401480056001580310083 S31500009CE00000000000C540036000D80036000D806B S31500009CF0036000D80016000588016002D8007600CF S31500009D000D8031000000000000C5420430810C20A7 S31500009D10430810C20430810C20430810C30430806D S31500009D200C20430810C031500000000000800000E5 S31500009D3030000C00030000C00030000C00030000DF S31500009D40C01032000C00030000C02000000000001C S31500009D500080020130804C20130804C20130804C80 S31500009D6020130804C20532C04C20530804C020103A S31500009D700000000000C54205608158205608158283 S31500009D800560815820560815830560C0582056087E S31500009D90158011500000000000C5420020800820F8 S31500009DA0020800820020800820020800820030811C S31500009DB018200208008031000000000000C542049F S31500009DC06081182046081182046081182046081117 S31500009DD082043481092046481180310000000000C9 S31500009DE000C5600558015600558015600558015696 S31500009DF00055801560011801420015801140315050 S31500009E00000000000080060141805060141805061D S31500009E1001418050601418050601518054601418E1 S31500009E2005002000000000000080020100804020A4 S31500009E3010080402010080402050085402010480EA S31500009E4041211048040020000000000000C5460320 S31500009E505180D46035180D46035180D46035180DF5 S31500009E6046025181946035180D40315000000000C3 S31500009E7000C5460571815C60571815C60171815C85 S31500009E8060571815C60771815C60571811C011001C S31500009E9000000000004546037180DC6037180DC6DF S31500009EA0037180DC6037180DC6017180DC603718DD S31500009EB01DC01100000000000045460571815C6070 S31500009EC0571815C60571815C60571815C614318080 S31500009ED01C60571814C01150000000000000020159 S31500009EE0208048201208048201208048201208049D S31500009EF0820170804C2012080580000000000000DE S31500009F0000000601618058601618058601618058B8 S31500009F1060161805860561805860161815800000C1 S31500009F20000000000045400570015C00570015C0A8 S31500009F300570015C00530014C00570004C0057000A S31500009F4015C0115000000000004542006080182036 S31500009F5006080182006080182002080082006081E5 S31500009F60082006080180110000000000004142049C S31500009F70208108204208108204208108204608110A S31500009F808204208118204208108011000000000081 S31500009F900045420540815020540815020540815075 S31500009FA030550C15420140C154205408050011508B S31500009FB0000000000000430150C05430150C05435A S31500009FC00150C05430150C05430152805420150829 S31500009FD0054000000000000000000800420010805C S31500009FE0042001080042001000040001080040009F S31500009FF01880062001000000000000000045420213 S3150000A000008080202008080202008080A020280806 S3150000A0100202008180202008080011500000000084 S3150000A020004540056001580056001580056000583F S3150000A0300056001580076001580056001580110073 S3150000A0400000000000C540036000D80036000D8007 S3150000A050036000D80076000D80015000D80036005D S3150000A0600D800000000000000000000430010C001C S3150000A070430010C00430010C00630010C0046000EF S3150000A0800C00430010C000000000000000000000AB S3150000A09030000C40030000C00030000C000300003C S3150000A0A0D00024000800030000C0000000000000EB S3150000A0B00000050131404C50131404C50131404CD9 S3150000A0C050131404C50531004C40131004C00000A1 S3150000A0D0000000000000230568C15A30568C15A305 S3150000A0E00568C15A30568C15A30568C05A30568C7F S3150000A0F0158000000000000000000000200008405D S3150000A1000200008000200008800220009000240148 S3150000A1100800020000800000000000000000084463 S3150000A12062111880462111884462111804460111F3 S3150000A1308844601118844621118000000000000048 S3150000A1400000004550115414550115404550115456 S3150000A15004150115404150115404550111400000E9 S3150000A16000000000000008214208508214208508E3 S3150000A17020420850821520854821420C5082142026 S3150000A180850000000000000000000A01028040A0D7 S3150000A1901028040A01028040A00028040A01028057 S3150000A1A040A01028040000000000000000000C037E S3150000A1B05300D4C035300D4C035300D4C0213009B0 S3150000A1C04C035301D4C035300D40000000000000A0 S3150000A1D00000080972015C80572015C80572015CF1 S3150000A1E080572015C80772015C80572015C00000F3 S3150000A1F0000000000000231848C61031848C61233B S3150000A2001848C61031840C61231040C01230848C6B S3150000A210210000000000000000003FFF4FFFD3FFB9 S3150000A220F4FFFD3FFF4FFFD3FFF4FFFD3FFF4FFF5E S3150000A230D3FFF4FFFD000000000000000000000056 S3150000A2400000000000000000000000000000000008 S3150000A25000000000000000000000000000000000F8 S3150000A26000002CDB0B36C3EDB0B36C2CDB0B36C217 S3150000A270CDB0B36C2CDB0B36C2CDB0B36C00000096 S3150000A280000000000000333C4CCF13F3C4CCF13384 S3150000A2903C4CCF1333C4CCF1333C4CCF1333C4CC3A S3150000A2A0F10000000000000000003B7E4EDF93B787 S3150000A2B0E4EDF93B7E4EDF9237E48DF93B7848C6F4 S3150000A2C013B1E4EC79000000000000000000010278 S3150000A2D070409C10270409C10270409C1027040995 S3150000A2E0C10270409C10271409C000000000000045 S3150000A2F00000040571015C40571015C40571015C2E S3150000A30040571015C40571015C40571015C0000078 S3150000A310000000000000020120804820120804828C S3150000A3200120804820120804820120804820120063 S3150000A330048000000000000000000000600018001B S3150000A3400600018000600018000600018000600021 S3150000A350180006000180000000000000000008044C S3150000A36072011C80472011C80472011C804720110D S3150000A370C80472011C80472811C0000000000000BC S3150000A3800000000060001800060001800060001850 S3150000A3900006000180006000180006000180000031 S3150000A3A000000000000008042201088042201088F6 S3150000A3B0042201088042201088042201088042609D S3150000A3C0108000000000000000002A044A8112A04C S3150000A3D044A8112A044A8112A044A8112A044A81D9 S3150000A3E012A044A8110000000000000008C00C00E4 S3150000A3F0530014C00530014C00530014C005300151 S3150000A4004C00530014C0053001401000000000004D S3150000A41000C00000400010000400010000400010D1 S3150000A420000400010000400010000440010030005C S3150000A4300000000008C04002000080002000080064 S3150000A44002000080002000080002000080002000BA S3150000A450080030000000000008C040046001180039 S3150000A4604600118004600118004600118004600156 S3150000A4701800460011803000000000001001400264 S3150000A48060009800260009800260009800260009F6 S3150000A490800260009800260009820000000000008B S3150000A4A04045420430810C20430810C20430810C20 S3150000A4B020430810C20430810C20430810C01150FC S3150000A4C0000000004000000030000C00030000C047 S3150000A4D00030000C00030000C00030000C00030038 S3150000A4E000C00000000000004000020030800C2088 S3150000A4F0030800C20030800C20030800C200308030 S3150000A5000C20030800C00000000000004045420483 S3150000A51060811820460811820460811820460811BF S3150000A5208204608118204608118011500000000046 S3150000A5304001420020800820020800820020800896 S3150000A5402002080082002080082002080080000007 S3150000A5500000000050014204608118204608118264 S3150000A560046081182046081182046081182046087C S3150000A5701180000000000000404540045001140016 S3150000A58045001140045001140045001140045001DB S3150000A590140045001142115000000000480006005A S3150000A5A04180106004180106004180106004180103 S3150000A5B00600418010600418010000000000000041 S3150000A5C0480002010080402010080402010080407B S3150000A5D0201008040201008040201008040000003A S3150000A5E000000000404546035180D46035180D46F2 S3150000A5F0035180D46035180D46035180D460351858 S3150000A6000D401150000000000001460471811C60DD S3150000A610471811C60471811C60471811C604718160 S3150000A6201C60471811C000000000000040014602EF S3150000A63071809C60271809C60271809C60271809E2 S3150000A640C60671809C60271809C000000000000043 S3150000A6505045460571815C60571815C60571815CC9 S3150000A66060571815C60571815C60571815C21150E0 S3150000A67000000000400002012080482012080482E9 S3150000A68001208048201208048201208048201208F8 S3150000A6900480000000000000400006006180186190 S3150000A6A0061801860061801860061801860461801C S3150000A6B018600618018000000000000000456004D4 S3150000A6C078011E00478011E00478011E00478011C2 S3150000A6D0E00078011E00478011C011500000000004 S3150000A6E04001420060801820060801820060801840 S3150000A6F020060801820060801820060801800000FC S3150000A7000000000040014204208108204208108217 S3150000A7100420810820420810820020810820420877 S3150000A72010800000000000004045420440811020D7 S3150000A730440811020440811020440811020040819F S3150000A74010204408110011500000000040000300D2 S3150000A75050C01430050C01430050C01430050C01E4 S3150000A760430050C01430050C0140000000000000FA S3150000A770400008004200108004200108004200103A S3150000A780800420010800420010800420010000001F S3150000A7900000000040454202008080202008080298 S3150000A7A00200808020200808020200808020200805 S3150000A7B0080011500000000040014004600118002C S3150000A7C00600118004600118004600118004600133 S3150000A7D01800460011800000000000004001400201 S3150000A7E06000980026000980026000980026001983 S3150000A7F0800260009800260009800000000000002A S3150000A8004045600438010E00438010E00438010E14 S3150000A81000438010E00438010E00438010C0115040 S3150000A820000000005000010030400C10030400C17D S3150000A8300030400C10030400C10030400C1003042B S3150000A84000C00000000000004000050031400C5030 S3150000A850031400C50031400C50031410C5003140EC S3150000A8600C50031400C200000000000040454304E1 S3150000A87060C11830460C11830460C11830460C01C3 S3150000A880830460C11830460C11801150000000008E S3150000A890400140002000080002000080002000085F S3150000A8A00002000080002000080002000080000076 S3150000A8B000000000400148446211188446211188B6 S3150000A8C04462111884462101884462111884462185 S3150000A8D0118000000000000040454044501114045F S3150000A8E045011140445011140445010140445011E2 S3150000A8F014044501114011500000000040000820DA S3150000A9004208108204208108204208108204208117 S3150000A9100820420810820420010000000000000008 S3150000A92000000A01028040A01028040A110280409B S3150000A930A01028040A01028040A01028040000008C S3150000A9400000000040454D035340D4D035340D4D32 S3150000A950035340D4D035340D4D035340D4D0353451 S3150000A9600D401150000000004001480472001C8098 S3150000A970472011C80472011C80472011C8047201C7 S3150000A9801C80472011C000000000000000002318B2 S3150000A99048C61231848C61231848C61231848C61F2 S3150000A9A0231848C61231848C4100000000000000C4 S3150000A9B000003FFF4FFFD3FFF4FFFD3FFF4FFFD3E4 S3150000A9C0FFF4FFFD3FFF4FFFD3FFF4FFFD00000044 S3150000A9D00000000000000000000000000000000071 S3150000A9E00000000000000000000000000000000061 S3150000A9F0000000000000000000002CDB0B36C2CD7A S3150000AA00B0B36C2CDB0B36C2CDB0B36C2CDB0B3683 S3150000AA10C2CDB0B37D000000000000000000333C52 S3150000AA204CCF1333C4CCF1333C4CCF1333C4CCF1ED S3150000AA30333C4CCF1333C4CCFD00000000000000B3 S3150000AA4000003B7E4EDF93B7E4EDF93B7E4EDF938D S3150000AA50B7E4EDF93B7E4EDF93B7E4EDF900000075 S3150000AA60000000000000028400A10028400A100235 S3150000AA708400A10028400A10028400A10028400A90 S3150000AA801CC0000000000000000008040001008057 S3150000AA904020100804020100804020100804020132 S3150000AAA0008040201000000000000000000000842C S3150000AAB000210008400210008400210008402210F6 S3150000AAC008840221008840221000000000000000D7 S3150000AAD00000000400010000400010000400010016 S3150000AAE00040001000040001000040001CC00000EF S3150000AAF000000000000008800220008800220008F4 S3150000AB00800220000800020000800020CC0800021D S3150000AB100000000000000000080002000080002085 S3150000AB2000080002000080002000080002000080EB S3150000AB300020000800020000000000000800088055 S3150000AB4002200088002200088002200088002200DF S3150000AB500880022000880022000200000000000099 S3150000AB600800080002000080002000080002000023 S3150000AB708000200008000200CC80002000020000B7 S3150000AB800000000008000A8402A100A8402A100A5A S3150000AB908402A100A8402A100A8402A100A8402A23 S3150000ABA010020000000000000800080402010080F6 S3150000ABB04020100804020100804020100804020111 S3150000ABC00080402010020000000000000800008401 S3150000ABD000210008400210008400210008400210F5 S3150000ABE0008400210008400210020000000000005E S3150000ABF0081000040001CC0073001CC0073001CC13 S3150000AC000073001CC0073001CC0073001CC2040096 S3150000AC100000000008000084002100084002100027 S3150000AC20840021000840021000840021CC08400264 S3150000AC301CC200000000000000000200008000208E S3150000AC4000080002000080002000080002000081C9 S3150000AC500020000810000000000000000000008036 S3150000AC60002000080002000080002000080002000A S3150000AC700080002100080002100000000000000013 S3150000AC80001080000000000000000000000000002E S3150000AC900000000000000000000000000CC00420BE S3150000ACA0000000000000000000000000000000009E S3150000ACB0000000000000000000000000000000008E S3150000ACC000000000000000003C3C00000000000006 S3150000ACD0000000000000000000000000000000006E S3150000ACE000000000000F0F00000000000000000040 S3150000ACF0000000000000000000000000000000004E S3150000AD00000000000000000000000000000000003D S3150000AD10000000000000000000000000000000002D S3150000AD20000000000000000000000000000000001D S3150000AD30000000000000000000000000000000000D S3150000AD4000000000000000000000000000000000FD S3150000AD50000000000000000000003FFFFFFFC000F1 S3150000AD600000003FFFFFFFC0000000003FFFFFFFA5 S3150000AD70C0000000000000000000000000003FFFCF S3150000AD80FFFFC0000000003FFFFFFFC00000000003 S3150000AD903FFFFFFFC00000000000000000000000B1 S3150000ADA000003FFFFFFFC0000000003FFFFFFFC0A5 S3150000ADB0000000003FFFFFFFC00000000000000091 S3150000ADC00000000000003FFFFFFFC0000000003F42 S3150000ADD0FFFFFFC0000000003FFFFFFFC0000000B4 S3150000ADE0000000000000000000003FFFFFFFC00061 S3150000ADF00000003FFFFFFFC0000000003FFFFFFF15 S3150000AE00C0000000000000000000000000003FFF3E S3150000AE10FFFFC0000000003FFFFFFFC00000000072 S3150000AE203FFFFFFFC0000000000000000000000020 S3150000AE300000028400A10028400A10028400A1003C S3150000AE4028400A10028400A10028400A10000000D1 S3150000AE500000000000000004000100004000100097 S3150000AE600400010000400010000400010000400042 S3150000AE70100000000000000000000084002100080F S3150000AE8040021000840021000840021000840021C6 S3150000AE90000840021000000000000000000000044E S3150000AEA000010000400010000400010000400010F6 S3150000AEB00004000100004000100000000000000037 S3150000AEC0000008800220008800220CC880022000B2 S3150000AED0880022000880022000880022000000006E S3150000AEE000000000080002000080002000080002A8 S3150000AEF000008000200008000200008000200008FA S3150000AF0000020000000000000800088002200088FF S3150000AF10002200088002200088002200088002200B S3150000AF20008800220002000000000000080008005F S3150000AF300200008000200CC80002000080002000F3 S3150000AF40080002000080002000020000000000004F S3150000AF5008000A8402A1CCA8402A100A8402A10093 S3150000AF60A8402A100A8732A100A8732A10020000FE S3150000AF7000000000080008040201008040201008BC S3150000AF8004020100804020100804020100804020D5 S3150000AF9010020000000000000800008400200008E5 S3150000AFA040021000840021000840021000800021A9 S3150000AFB00008400210020000000000000810000710 S3150000AFC03001000073001CC0073001CC0073001C68 S3150000AFD0C0040001CC0073001CC204000000000085 S3150000AFE008000084002100084002100084002100AF S3150000AFF008400210008400210008400210020000F0 S3150000B000000000000000020000800020000800028E S3150000B01000008000200008000200008000200008D8 S3150000B0200000000000000000000000800020000872 S3150000B03000020000800020000800020000800020BE S3150000B0400008000200000000000000000010800060 S3150000B05000000000000000000000000000000000EA S3150000B06000000000000000000000042000000000B6 S3150000B07000000000000000000000000000000000CA S3150000B08000000000000000000000000000000000BA S3150000B090000000003C3C0000000000000000000032 S3150000B0A0000000000000000000000000000000009A S3150000B0B0000F0F000000000000000000000000006C S3150000B0C0000000000000000000000000000000007A S3150000B0D0000000000000000000000000000000006A S3150000B0E0000000000000000000000000000000005A S3150000B0F0000000000000000000000000000000004A S3150000B1000000000000000000000000000000000039 S3150000B1100000000000000000000000000000000029 S3150000B1200000000000003FFFFFFFC0000000003FDE S3150000B130FFFFFFC0000000003FFFFFFFC000000050 S3150000B140000000000000000000003FFFFFFFC000FD S3150000B1500000003FFFFFFFC0000000003FFFFFFFB1 S3150000B160C0000000000000000000000000003FFFDB S3150000B170FFFFC0000000003FFFFFFFC0000000000F S3150000B1803FFFFFFFC00000000000000000000000BD S3150000B19000003FFFFFFFC0000000003FFFFFFFC0B1 S3150000B1A0000000003FFFFFFFC0000000000000009D S3150000B1B00000000000003FFFFFFFC0000000003F4E S3150000B1C0FFFFFFC0000000003FFFFFFFC0000000C0 S3150000B1D0000000000000000000003FFFFFFFC0006D S3150000B1E00000003FFFFFFFC0000000003FFFFFFF21 S3150000B1F0C000000000000000000000000000000089 S3150000B2000000000000000000000000000000000038 S3150000B2100000000000000000000000000000000028 S3150000B220300020010200000030004249000000000A S3150000B2300000000000000000000000000000000008 S3150000B24000000000000000000000000000000000F8 S3150000B25000000000000000000000000000000000E8 S3150000B26000000000000000000000000000000000D8 S3150000B27000000000000000000000000000000000C8 S3150000B28000000000000000000000000000000000B8 S3150000B29000000000000000000000000000000000A8 S3150000B2A00000000000000000000000000000000098 S3150000B2B00000000000000000000000000000000088 S3150000B2C00000000000000000000000000000000078 S3150000B2D00000000000000000000000000000000068 S3150000B2E00000000000000000000000000000000058 S3150000B2F00000000000000000000000000000000048 S3150000B3000000000000000000000000000000000037 S3150000B3100000000000000000000000000000000027 S3150000B3200000000000000000000000000000000017 S3150000B3300000000000000000000000000000000007 S3150000B34000000000000000000000000000000000F7 S3150000B35000000000000000000000000000000000E7 S3150000B36000000000000000000000000000000000D7 S3150000B37000000000000000000000000000000000C7 S3150000B38000000000000000000000000000000000B7 S3150000B39000000000000000000000000000000000A7 S3150000B3A00000000000000000000000000000000097 S3150000B3B00000000000000000000000000000000087 S3150000B3C00000000000000000000000000000000077 S3150000B3D00000000000000000000000000000000067 S3150000B3E00000000000000000000000000000000057 S3150000B3F00000000000000000000000000000000047 S3150000B4000000000000000000000000000000000036 S3150000B4100000000000000000000000000000000026 S3150000B4200000000000000000000000000000000016 S3150000B4300000000000000000000000000000000006 S3150000B44000000000000000000000000000000000F6 S3150000B45000000000000000000000000000000000E6 S3150000B46000000000000000000000000000000000D6 S3150000B47000000000000000000000000000000000C6 S3150000B48000000000000000000000000000000000B6 S3150000B49000000000000000000000000000000000A6 S3150000B4A00000000000000000000000000000000096 S3150000B4B00000000000000000000000000000000086 S3150000B4C00000000000000000000000000000000076 S3150000B4D00000000000000000000000000000000066 S3150000B4E00000000000000000000000000000000056 S3150000B4F00000000000000000000000000000000046 S3150000B5000000000000000000000000000000000035 S3150000B5100000000000000000000000000000000025 S3150000B5200000000000000000000000000000000015 S3150000B5300000000000000000000000000000000005 S3150000B54000000000000000000000000000000000F5 S3150000B55000000000000000000000000000000000E5 S3150000B56000000000000000000000000000000000D5 S3150000B57000000000000000000000000000000000C5 S3150000B58000000000000000000000000000000000B5 S3150000B59000000000000000000000000000000000A5 S3150000B5A00000000000000000000000000000000095 S3150000B5B00000000000000000000000000000000085 S3150000B5C00000000000000000000000000000000075 S3150000B5D00000000000000000000000000000000065 S3150000B5E00000000000000000000000000000000055 S3150000B5F00000000000000000000000000000000045 S3150000B6000000000000000000000000000000000034 S3150000B6100000000000000000000000000000000024 S3150000B6200000000000000000000000000000000014 S3150000B6300000000000000000000000000000000004 S3150000B64000000000000000000000000000000000F4 S3150000B65000000000000000000000000000000000E4 S3150000B66000000000000000000000000000000000D4 S3150000B67000000000000000000000000000000000C4 S3150000B68000000000000000000000000000000000B4 S3150000B69000000000000000000000000000000000A4 S3150000B6A00000000000000000000000000000000094 S3150000B6B00000000000000000000000000000000084 S3150000B6C00000000000000000000000000000000074 S3150000B6D00000000000000000000000000000000064 S3150000B6E00000000000000000000000000000000054 S3150000B6F00000000000000000000000000000000044 S3150000B7000000000000000000000000000000000033 S3150000B7100000000000000000000000000000000023 S3150000B7200000000000000000000000000000000013 S3150000B7300000000000000000000000000000000003 S3150000B74000000000000000000000000000000000F3 S3150000B75000000000000000000000000000000000E3 S3150000B76000000000000000000000000000000000D3 S3150000B77000000000000000000000000000000000C3 S3150000B78000000000000000000000000000000000B3 S3150000B79000000000000000000000000000000000A3 S3150000B7A00000000000000000000000000000000093 S3150000B7B00000000000000000000000000000000083 S3150000B7C00000000000000000000000000000000073 S3150000B7D00000000000000000000000000000000063 S3150000B7E00000000000000000000000000000000053 S3150000B7F00000000000000000000000000000000043 S3150000B8000000000000000000000000000000000032 S3150000B8100000000000000000000000000000000022 S3150000B8200000000000000000000000000000000012 S3150000B8300000000000000000000000000000000002 S3150000B84000000000000000000000000000000000F2 S3150000B85000000000000000000000000000000000E2 S3150000B86000000000000000000000000000000000D2 S3150000B87000000000000000000000000000000000C2 S3150000B88000000000000000000000000000000000B2 S3150000B89000000000000000000000000000000000A2 S3150000B8A00000000000000000000000000000000092 S3150000B8B00000000000000000000000000000000082 S3150000B8C00000000000000000000000000000000072 S3150000B8D00000000000000000000000000000000062 S3150000B8E00000000000000000000000000000000052 S3150000B8F00000000000000000000000000000000042 S3150000B9000000000000000000000000000000000031 S3150000B9100000000000000000000000000000000021 S3150000B9200000000000000000000000000000000011 S3150000B9300000000000000000000000000000000001 S3150000B94000000000000000000000000000000000F1 S3150000B95000000000000000000000000000000000E1 S3150000B96000000000000000000000000000000000D1 S3150000B97000000000000000000000000000000000C1 S3150000B98000000000000000000000000000000000B1 S3150000B99000000000000000000000000000000000A1 S3150000B9A00000000000000000000000000000000091 S3150000B9B00000000000000000000000000000000081 S3150000B9C00000000000000000000000000000000071 S3150000B9D00000000000000000000000000000000061 S3150000B9E00000000000000000000000000000000051 S3150000B9F00000000000000000000000000000000041 S3150000BA000000000000000000000000000000000030 S3150000BA100000000000000000000000000000000020 S3150000BA200000000000000000000000000000000010 S3150000BA300000000000000000000000000000000000 S3150000BA4000000000000000000000000000000000F0 S3150000BA5000000000000000000000000000000000E0 S3150000BA6000000000000000000000000000000000D0 S3150000BA7000000000000000000000000000000000C0 S3150000BA8000000000000000000000000000000000B0 S3150000BA9000000000000000000000000000000000A0 S3150000BAA00000000000000000000000000000000090 S3150000BAB00000000000000000000000000000000080 S3150000BAC00000000000000000000000000000000070 S3150000BAD00000000000000000000000000000000060 S3150000BAE00000000000000000000000000000000050 S3150000BAF00000000000000000000000000000000040 S3150000BB00000000000000000000000000000000002F S3150000BB10000000000000000000000000000000001F S3150000BB20000000000000000000000000000000000F S3150000BB3000000000000000000000000000000000FF S3150000BB4000000000000000000000000000000000EF S3150000BB5030002001020200003000424000000000D8 S3150000BB6000000000000000000000000000000000CF S3150000BB7000000000000000000000000000000000BF S3150000BB8000000000000000000000000000000000AF S3150000BB90000000000000000000000000000000009F S3150000BBA0000000000000000000000000000000008F S3150000BBB0000000000000000000000000000000007F S3150000BBC0000000000000000000000000000000006F S3150000BBD0000000000000000000000000000000005F S3150000BBE0000000000000000000000000000000004F S3150000BBF0000000000000000000000000000000003F S3150000BC00000000000000000000000000000000002E S3150000BC10000000000000000000000000000000001E S3150000BC20000000000000000000000000000000000E S3150000BC3000000000000000000000000000000000FE S3150000BC4000000000000000000000000000000000EE S3150000BC5000000000000000000000000000000000DE S3150000BC6000000000000000000000000000000000CE S3150000BC7000000000000000000000000000000000BE S3150000BC8000000000000000000000000000000000AE S3150000BC90000000000000000000000000000000009E S3150000BCA0000000000000000000000000000000008E S3150000BCB0000000000000000000000000000000007E S3150000BCC0000000000000000000000000000000006E S3150000BCD0000000000000000000000000000000005E S3150000BCE0000000000000000000000000000000004E S3150000BCF0000000000000000000000000000000003E S3150000BD00000000000000000000000000000000002D S3150000BD10000000000000000000000000000000001D S3150000BD20000000000000000000000000000000000D S3150000BD3000000000000000000000000000000000FD S3150000BD4000000000000000000000000000000000ED S3150000BD5000000000000000000000000000000000DD S3150000BD6000000000000000000000000000000000CD S3150000BD7000000000000000000000000000000000BD S3150000BD8000000000000000000000000000000000AD S3150000BD90000000000000000000000000000000009D S3150000BDA0000000000000000000000000000000008D S3150000BDB0000000000000000000000000000000007D S3150000BDC0000000000000000000000000000000006D S3150000BDD0000000000000000000000000000000005D S3150000BDE0000000000000000000000000000000004D S3150000BDF0000000000000000000000000000000003D S3150000BE00000000000000000000000000000000002C S3150000BE10000000000000000000000000000000001C S3150000BE20000000000000000000000000000000000C S3150000BE3000000000000000000000000000000000FC S3150000BE4000000000000000000000000000000000EC S3150000BE5000000000000000000000000000000000DC S3150000BE6000000000000000000000000000000000CC S3150000BE7000000000000000000000000000000000BC S3150000BE8000000000000000000000000000000000AC S3150000BE90000000000000000000000000000000009C S3150000BEA0000000000000000000000000000000008C S3150000BEB0000000000000000000000000000000007C S3150000BEC0000000000000000000000000000000006C S3150000BED0000000000000000000000000000000005C S3150000BEE0000000000000000000000000000000004C S3150000BEF0000000000000000000000000000000003C S3150000BF00000000000000000000000000000000002B S3150000BF10000000000000000000000000000000001B S3150000BF20000000000000000000000000000000000B S3150000BF3000000000000000000000000000000000FB S3150000BF4000000000000000000000000000000000EB S3150000BF5000000000000000000000000000000000DB S3150000BF6000000000000000000000000000000000CB S3150000BF7000000000000000000000000000000000BB S3150000BF8000000000000000000000000000000000AB S3150000BF90000000000000000000000000000000009B S3150000BFA0000000000000000000000000000000008B S3150000BFB0000000000000000000000000000000007B S3150000BFC0000000000000000000000000000000006B S3150000BFD0000000000000000000000000000000005B S3150000BFE0000000000000000000000000000000004B S3150000BFF0000000000000000000000000000000003B S3150000C000000000000000000000000000000000002A S3150000C010000000000000000000000000000000001A S3150000C020000000000000000000000000000000000A S3150000C03000000000000000000000000000000000FA S3150000C04000000000000000000000000000000000EA S3150000C05000000000000000000000000000000000DA S3150000C06000000000000000000000000000000000CA S3150000C07000000000000000000000000000000000BA S3150000C08000000000000000000000000000000000AA S3150000C090000000000000000000000000000000009A S3150000C0A0000000000000000000000000000000008A S3150000C0B0000000000000000000000000000000007A S3150000C0C0000000000000000000000000000000006A S3150000C0D0000000000000000000000000000000005A S3150000C0E0000000000000000000000000000000004A S3150000C0F0000000000000000000000000000000003A S3150000C1000000000000000000000000000000000029 S3150000C1100000000000000000000000000000000019 S3150000C1200000000000000000000000000000000009 S3150000C13000000000000000000000000000000000F9 S3150000C14000000000000000000000000000000000E9 S3150000C15000000000000000000000000000000000D9 S3150000C16000000000000000000000000000000000C9 S3150000C17000000000000000000000000000000000B9 S3150000C18000000000000000000000000000000000A9 S3150000C1900000000000000000000000000000000099 S3150000C1A00000000000000000000000000000000089 S3150000C1B00000000000000000000000000000000079 S3150000C1C00000000000000000000000000000000069 S3150000C1D00000000000000000000000000000000059 S3150000C1E00000000000000000000000000000000049 S3150000C1F00000000000000000000000000000000039 S3150000C2000000000000000000000000000000000028 S3150000C2100000000000000000000000000000000018 S3150000C2200000000000000000000000000000000008 S3150000C23000000000000000000000000000000000F8 S3150000C24000000000000000000000000000000000E8 S3150000C25000000000000000000000000000000000D8 S3150000C26000000000000000000000000000000000C8 S3150000C27000000000000000000000000000000000B8 S3150000C28000000000000000000000000000000000A8 S3150000C2900000000000000000000000000000000098 S3150000C2A00000000000000000000000000000000088 S3150000C2B00000000000000000000000000000000078 S3150000C2C00000000000000000000000000000000068 S3150000C2D00000000000000000000000000000000058 S3150000C2E00000000000000000000000000000000048 S3150000C2F00000000000000000000000000000000038 S3150000C3000000000000000000000000000000000027 S3150000C3100000000000000000000000000000000017 S3150000C3200000000000000000000000000000000007 S3150000C33000000000000000000000000000000000F7 S3150000C34000000000000000000000000000000000E7 S3150000C35000000000000000000000000000000000D7 S3150000C36000000000000000000000000000000000C7 S3150000C37000000000000000000000000000000000B7 S3150000C38000000000000000000000000000000000A7 S3150000C3900000000000000000000000000000000097 S3150000C3A00000000000000000000000000000000087 S3150000C3B00000000000000000000000000000000077 S3150000C3C00000000000000000000000000000000067 S3150000C3D00000000000000000000000000000000057 S3150000C3E00000000000000000000000000000000047 S3150000C3F00000000000000000000000000000000037 S3150000C4000000000000000000000000000000000026 S3150000C4100000000000000000000000000000000016 S3150000C4200000000000000000000000000000000006 S3150000C43000000000000000000000000000000000F6 S3150000C44000000000000000000000000000000000E6 S3150000C45000000000000000000000000030000001A5 S3150000C46000005BBE30008001000000033000400980 S3150000C47000000000000000000000000000000000B6 S3150000C48000000000000000000000000000000000A6 S3150000C4900000000030008001000000053000A0010F S3150000C4A000000000300000010000C17D0000000017 S3110000C4B00000000000000000000000007A S70500110001E8 ================================================ FILE: TamagotchiFriends/proxmark/armsrc/obj/fpgaloader.d ================================================ obj/fpgaloader.d obj/fpgaloader.o: fpgaloader.c ../include/proxmark3.h \ ../include/at91sam7s512.h ../include/config_gpio.h ../include/usb_cmd.h \ stdint.h apps.h ../include/common.h ../include/at91sam7s512.h \ ../include/hitag2.h ../include/mifare.h ../include/common.h util.h \ string.h ================================================ FILE: TamagotchiFriends/proxmark/armsrc/obj/hitag2.d ================================================ obj/hitag2.d obj/hitag2.o: hitag2.c ../include/proxmark3.h \ ../include/at91sam7s512.h ../include/config_gpio.h ../include/usb_cmd.h \ stdint.h apps.h ../include/common.h ../include/at91sam7s512.h \ ../include/hitag2.h ../include/mifare.h ../include/common.h util.h \ string.h ================================================ FILE: TamagotchiFriends/proxmark/armsrc/obj/iclass.d ================================================ obj/iclass.d obj/iclass.o: iclass.c ../include/proxmark3.h \ ../include/at91sam7s512.h ../include/config_gpio.h ../include/usb_cmd.h \ stdint.h apps.h ../include/common.h ../include/at91sam7s512.h \ ../include/hitag2.h ../include/mifare.h ../include/common.h util.h \ string.h ../common/iso14443crc.h ================================================ FILE: TamagotchiFriends/proxmark/armsrc/obj/iso14443.d ================================================ obj/iso14443.d obj/iso14443.o: iso14443.c ../include/proxmark3.h \ ../include/at91sam7s512.h ../include/config_gpio.h ../include/usb_cmd.h \ stdint.h apps.h ../include/common.h ../include/at91sam7s512.h \ ../include/hitag2.h ../include/mifare.h ../include/common.h util.h \ string.h ../common/iso14443crc.h ================================================ FILE: TamagotchiFriends/proxmark/armsrc/obj/iso14443a.d ================================================ obj/iso14443a.d obj/iso14443a.o: iso14443a.c ../include/proxmark3.h \ ../include/at91sam7s512.h ../include/config_gpio.h ../include/usb_cmd.h \ stdint.h apps.h ../include/common.h ../include/at91sam7s512.h \ ../include/hitag2.h ../include/mifare.h ../include/common.h util.h \ string.h ../common/cmd.h ../common/usb_cdc.h ../common/iso14443crc.h \ iso14443a.h mifaresniff.h crapto1.h mifareutil.h ================================================ FILE: TamagotchiFriends/proxmark/armsrc/obj/iso14443crc.d ================================================ obj/iso14443crc.d obj/iso14443crc.o: ../common/iso14443crc.c \ ../common/iso14443crc.h ../include/common.h stdint.h \ ../include/at91sam7s512.h ================================================ FILE: TamagotchiFriends/proxmark/armsrc/obj/iso15693.d ================================================ obj/iso15693.d obj/iso15693.o: iso15693.c ../include/proxmark3.h \ ../include/at91sam7s512.h ../include/config_gpio.h ../include/usb_cmd.h \ stdint.h util.h ../include/common.h ../include/at91sam7s512.h apps.h \ ../include/hitag2.h ../include/mifare.h ../include/common.h string.h \ ../common/iso15693tools.h ../common/cmd.h ../common/usb_cdc.h ================================================ FILE: TamagotchiFriends/proxmark/armsrc/obj/iso15693tools.d ================================================ obj/iso15693tools.d obj/iso15693tools.o: ../common/iso15693tools.c \ ../include/proxmark3.h ../include/at91sam7s512.h \ ../include/config_gpio.h ../include/usb_cmd.h stdint.h ================================================ FILE: TamagotchiFriends/proxmark/armsrc/obj/legic_prng.d ================================================ obj/legic_prng.d obj/legic_prng.o: ../common/legic_prng.c \ ../include/legic_prng.h stdint.h ================================================ FILE: TamagotchiFriends/proxmark/armsrc/obj/legicrf.d ================================================ obj/legicrf.d obj/legicrf.o: legicrf.c ../include/proxmark3.h \ ../include/at91sam7s512.h ../include/config_gpio.h ../include/usb_cmd.h \ stdint.h apps.h ../include/common.h ../include/at91sam7s512.h \ ../include/hitag2.h ../include/mifare.h ../include/common.h util.h \ string.h legicrf.h ../include/legic_prng.h ../include/crc.h ================================================ FILE: TamagotchiFriends/proxmark/armsrc/obj/lfops.d ================================================ obj/lfops.d obj/lfops.o: lfops.c ../include/proxmark3.h \ ../include/at91sam7s512.h ../include/config_gpio.h ../include/usb_cmd.h \ stdint.h apps.h ../include/common.h ../include/at91sam7s512.h \ ../include/hitag2.h ../include/mifare.h ../include/common.h util.h \ ../common/crc16.h string.h ================================================ FILE: TamagotchiFriends/proxmark/armsrc/obj/mifarecmd.d ================================================ obj/mifarecmd.d obj/mifarecmd.o: mifarecmd.c mifarecmd.h \ ../include/proxmark3.h ../include/at91sam7s512.h \ ../include/config_gpio.h ../include/usb_cmd.h stdint.h apps.h \ ../include/common.h ../include/at91sam7s512.h ../include/hitag2.h \ ../include/mifare.h ../include/common.h util.h string.h \ ../common/iso14443crc.h iso14443a.h mifaresniff.h crapto1.h mifareutil.h ================================================ FILE: TamagotchiFriends/proxmark/armsrc/obj/mifaresniff.d ================================================ obj/mifaresniff.d obj/mifaresniff.o: mifaresniff.c mifaresniff.h \ ../include/proxmark3.h ../include/at91sam7s512.h \ ../include/config_gpio.h ../include/usb_cmd.h stdint.h apps.h \ ../include/common.h ../include/at91sam7s512.h ../include/hitag2.h \ ../include/mifare.h ../include/common.h util.h string.h \ ../common/iso14443crc.h iso14443a.h crapto1.h mifareutil.h ================================================ FILE: TamagotchiFriends/proxmark/armsrc/obj/mifareutil.d ================================================ obj/mifareutil.d obj/mifareutil.o: mifareutil.c ../include/proxmark3.h \ ../include/at91sam7s512.h ../include/config_gpio.h ../include/usb_cmd.h \ stdint.h apps.h ../include/common.h ../include/at91sam7s512.h \ ../include/hitag2.h ../include/mifare.h ../include/common.h util.h \ string.h ../common/iso14443crc.h iso14443a.h mifaresniff.h crapto1.h \ mifareutil.h ================================================ FILE: TamagotchiFriends/proxmark/armsrc/obj/osimage.s19 ================================================ S01200006F626A2F6F73696D6167652E73313993 S3150001000008B50B4B0B495A1E581C00238A4202D2D3 S315000100101370031CF6E7084A08499A188A4204D263 S315000100200749C95C01331170F5E706F0D1F9C046FD S31500010030392A2000142C200000002000382A200034 S30900010040A5271200D7 S31500010048F7B5071C019104F04DFC18240120013C69 S3150001005804F065FC002CF9D1201C04F060FC012099 S3150001006804F05DFC012004F05AFC012004F057FC61 S31500010078012004F054FC201C04F051FC012004F07A S315000100884EFC012004F04BFC3E1C019AF31B9342E3 S3150001009866DA0025347803232C411C40022C2BD028 S315000100A89C4240D0012C10D0012004F038FC0020DD S315000100B804F035FC012004F032FC012004F02FFC89 S315000100C8012004F02CFC012026E0201C04F027FC6A S315000100D8201C04F024FC201C04F021FC002004F060 S315000100E81EFC201C04F01BFC201C04F018FC201C20 S315000100F804F015FC201C2CE0012004F010FC012062 S3150001010804F00DFC012004F00AFC012004F007FCB0 S31500010118012004F004FC002004F001FC012004F095 S31500010128FEFB012015E0012004F0F9FB012004F093 S31500010138F6FB012004F0F3FB012004F0F0FB01209B S3150001014804F0EDFB012004F0EAFB012004F0E7FBD3 S315000101580020023504F0E3FB082D9BD1013694E714 S31500010168012004F0DCFB012004F0D9FB002004F097 S31500010178D6FB012004F0D3FB18240120013C04F02E S31500010188CEFB002CF9D1F7BC01BC004707B52623E5 S315000101986A4613700123537068460023032193703E S315000101A800F09AFE6B46D870000A18710521684658 S315000101B8FFF746FF03B001BC0047F0B58DB00490C8 S315000101C8602010F095FA0022151C101C624B196C60 S315000101D8CC0701D5432159621B6CDF06F6D55E4B68 S315000101E8196A0B061B0E002D16D01C0602D54B42AA S315000101F81B061B0E99180906090E140602D59B1A29 S315000102081906090E554B1954554B441C9C4205DDDC S315000102180026301C311C1BE0041C00E0131C0122C3 S3150001022855401540201C1A1CD0E794104B4D0C194B S315000102382C5D4C4D97007D596C4304321B19402A9D S31500010248F3D1834207DC031C0131642905D0181C4C S3150001025800231A1CE9E70E1CF6E700240F2B75D9B3 S3150001026807A8211C142206F0CDFE10360125002709 S3150001027803973B1C9A103949B2188A5C3A499F0080 S3150001028879584A430398043380180390102BF1D107 S31500010298002102910B1C9A009446304F9A10B2180D S315000102A8B95C314F60464037C7590A1C7A430299EF S315000102B8043389180291102BEDD100231A1C9700DB S315000102C8059726489710F119415C28480191059927 S315000102D808580199844667464F430432DB19402A78 S315000102E8EDD1039A029F9000B9008B4202DD834249 S315000102F808DD13E0814205DD07AB1A5D2A430436A2 S315000103081A5500E004366D062D0E01D1013401257A S31500010318174B9E42ABDD174804F0F0FA012D0CD0BD S31500010328154B1B68002B03D01448291C04F02CFB21 S3150001033800230722AA425B41E41A0023A34205DAF5 S3150001034807AA9A5C049FFA540133F7E7201C0DB0FB S31500010358F0BC02BC0847C0460040FDFF142C200033 S31500010368CF070000D8081200D8091200580A12004F S315000103788F070000A50D1200382A2000B20D1200C1 S3150001038873B5141C061C40200D1C10F0B1F9206829 S31500010398092801DC0A23236000230E4A116CC807C9 S315000103A805D50D49C95C01335162B3420ADA126CAB S315000103B8D10603D5074A126A0192019A0749084AE2 S315000103C81160EAE722689B18DB002B6073BC01BC4D S315000103D80047C0460040FDFFCCC82000010000A52B S315000103E840FDFFFF73B5FFF7D1FE8020000310F033 S315000103F837F9602010F07CF9642006F0FDFC10F056 S3150001040869F9402010F074F9254B18680023033068 S31500010418244A116C141CCD0705D52349C95C01333F S31500010428516283420AD0126CD60603D51D4A126A56 S315000104380192019A1D491E4A1160E9E7602010F0F0 S3150001044857F90022101C151C236CD90702D5154B28 S3150001045843215962236CDE06F6D5124B196A0B063F S315000104681B0E002814D01E0602D54B421B061B0E76 S3150001047899180906090E160602D59B1A1906090EB8 S315000104880C4E71550C496B1C8B4206DC1D1C00E099 S315000104981A1C012358401840D6E773BC01BC004713 S315000104A8CCCA20000040FDFFCCC82000010000A5F1 S315000104B840FDFFFF142C2000CF07000038B510F0CF S315000104C809F9E02010F014F9C82006F095FC8020FF S315000104D8000310F0C5F8642006F08EFC602010F0C9 S315000104E807F90022101C141C184B196CCD0701D5ED S315000104F8432159621B6CD906F6D5144B196A0B06AA S315000105081B0E002814D01D0602D54B421B061B0ED6 S3150001051899180906090E150602D59B1A1906090E18 S315000105280B4D29550B49631C8B4209DC1C1C00E049 S315000105381A1C0123584018400749084B1960D3E78C S31500010548074804F021FA38BC01BC00470040FDFF0A S31500010558142C2000571B0000010000A540FDFFFFD9 S31500010568DF0D1200F8B5124C0127802680250423D9 S31500010578BE40AD002763E02026636563636310F020 S31500010588B7F80A2006F038FC8020000310F068F856 S3150001059810F0A0F8602010F0ABF8FA2006F02CFC59 S315000105A804232763666365636363F8BC01BC00477C S315000105B800F4FFFFF0B54D4C85B001911E1C0021DA S315000105C8012302910391236380235B002363802324 S315000105D89B00151C0A9A63630423071C63638A42FA S315000105E803D04348642206F00DFD002D01D0FFF724 S315000105F8B9FF002E4ED104F075F918250120013DE9 S3150001060804F08DF9002DF9D1281C04F088F9012090 S3150001061804F085F9012004F082F9012004F07FF93C S31500010628012004F07CF9012004F079F9012004F095 S3150001063876F9281C04F073F93E1C019AF31B9342C0 S3150001064814DA002533780120AB4203D104F067F9A7 S31500010658002002E004F063F9012004F060F9013595 S3150001066880235B009D42EDD10136E6E7012004F0C7 S3150001067856F9012004F053F9002004F050F901203D S3150001068804F04DF918250120013D04F048F9002D23 S31500010698F9D103E0381C0199FFF7D2FC012780261E S315000106A8BE402763134B666302A9186803AAFFF7BE S315000106B867FE0A9B0D4D002B08D06F632E630C4D08 S315000106C8281CFFF77AFD0A9A156000E00A980123AB S315000106D8636380235B00636380239B006363042356 S315000106E8636305B0F0BC02BC0847C04600F4FFFFCF S315000106F8603A2000CCCA200070B58EB0051C0C1CCF S3150001070801A80021312206F07DFC032D5EDD267845 S31500010718330703D501A82F4906F0B2FC01A8F30750 S3150001072834D52D4906F0ACFC60780138132826D853 S315000107380FF01AFE0A0D102525252525252525251F S3150001074825251316191C1F2201A8244919E001A8F9 S31500010758234916E001A8234913E001A8224910E01C S3150001076801A822490DE001A821490AE001A8214969 S3150001077807E001A8204904E001A8204901E0204931 S3150001078801A806F07DFC01A81E4900E01E4906F0F5 S3150001079877FC201CA91E00F09FFB6419A21E127883 S315000107A803061B0E934209D1013C000A2378000473 S315000107B8000C834202D101A8144901E0144901A899 S315000107C806F05EFC134801A904F0DEF80EB070BC11 S315000107D801BC0047EA0D1200F30D1200FA0D1200D2 S315000107E8050E1200110E12001F0E1200290E12001C S315000107F8360E1200430E12004D0E1200580E12004C S31500010808630E1200851712006E0E1200750E120085 S315000108187B0E12009E0E120008B5064B18600028C2 S3150001082801D0054900E00549054804F0ADF808BCC2 S3150001083801BC0047382A20008D141200840E1200CC S31500010848880E1200F0B58022794D01278026BE4018 S31500010858784C920004232F632E636A63962295B01F S315000108680021BA406B63201C06F0CCFB0FF032FF67 S31500010878E0200FF03DFFC82006F0BEFA80200003F5 S315000108880FF0EEFE0FF026FF60200FF031FFC820B3 S3150001089806F0B2FA8022920004232F636E630027C2 S315000108A86A636B630E970F97FFF770FC624B0EA98D S315000108B818680FAAFFF764FD201CFFF77EFC061EC9 S315000108C80B2E0FDDA278E3780D9222790C930B9209 S315000108D86379A2790A930992E379227A08930792AE S315000108E8647A07E00797089709970A970B970C9771 S315000108F80D973C1C5148311C04F046F84D4D301CEF S31500010908291CFFF7F9FE301C291C012204F062F8A4 S315000109180B2E0FDD099B0A9A00930B9B01920293FA S315000109280C9A0D9B039204934548211C079A089B30 S3150001093804F02AF84348002104F026F8424D002025 S31500010948291CFFF7D9FE0122291C002004F042F8D0 S3150001095864353E48002104F017F80020291CFFF7EA S31500010968CBFE0020291C012204F034F80B2E0EDCE4 S315000109782F4A0123536380235B00536380239B0023 S3150001098853630423536315B0F0BC01BC0047304BD5 S315000109981B68002BECD0002610AD62232B70202398 S315000109A86B700D9B0C9AAB700B9BEA702B710A9AB4 S315000109B8099B6A71AB71089A079B281C0B21EA717E S315000109C82B726C72AE7200F087FAE872000A28730D S315000109D80D21281CFFF734FB174B0EA918680FAA1F S315000109E8FFF7CEFC184D281CFFF7E7FB071E03DCB3 S315000109F80136202ED0D1BBE73A1C1648311C03F02C S31500010A08C3FF381C291CFFF777FE0122381C291C55 S31500010A1803F0E0FF6A782B7812021A43AB781B04BD S31500010A281A43EB781B061A430B4B9A42E0D19FE710 S31500010A3800F4FFFF603A2000CCCA2000A10E120084 S31500010A48C70E1200F60E1200C43A20001A0F120041 S31500010A58382A20003B0F120001011607F0B5AC4CED S31500010A68012780268025BE40AD000420642295B06A S31500010A7800212763266365636063A64806F0C2FA08 S31500010A880FF028FEE0200FF033FEC82006F0B4F977 S31500010A98802000030FF0E4FD0FF01CFEC82006F0CD S31500010AA8ABF90421676360206663256361630FF010 S31500010AB81FFE0022161C101C974B196CCC0701D57A S31500010AC8432159621B6CDF06F6D5934B196A0B064F S31500010AD81B0E002E16D01C0602D54B421B061B0EFA S31500010AE899180906090E140602D59B1A1906090E44 S31500010AF88A4D8B4B441C29549C4205DD00200C90E1 S31500010B08011C23E0041C00E0131C01225640164078 S31500010B18201C1A1CD0E79600B446804F96108E19F1 S31500010B28BF5D804C0B9767463E590B9FB446664698 S31500010B387E4304329B19402AEDD10C9A934208DC74 S31500010B48131C794A0131914205D00C9300231A1CD2 S31500010B58E1E7081CF5E700260F2B00D8ABE01030BB S31500010B680FAC0B90311C201C142206F04BFA0127FE S31500010B7800230C930B999A108A1868498A5C6B4969 S31500010B88980041584A430C98043380180C90102B4E S31500010B98F0D100218C460B1C9A000B980D929910E6 S31500010BA85E4A4118515C61480A910D9940300858CE S31500010BB80A990A1C424304339444102BECD10022AF S31500010BC809920B98911041185448405C0A9058486C S31500010BD893001B580A98011C5943099B04325B1858 S31500010BE80993402AEDD10C98820009986346990029 S31500010BF8884201DD904214DC0B9B04330B93181CCD S31500010C08914203DD0FAB9A5D3A439A557B061F0E57 S31500010C1801D101360127474B9842A9DD464803F021 S31500010C286DFE012F02D0454803F068FE0023B3424A S31500010C3808DA3A4F42480FA9FA18595C1218117086 S31500010C480133F4E7002E36D03223A3704B23E37029 S31500010C5803232371012363711023E37105230027FD S31500010C682372201CE0230A21637227706770A7711B S31500010C7800F032F9A072000AE0720C21201CFFF77D S31500010C88DFF9304B80201C680FF032FD22490B6CCE S31500010C98DA0705D52C4BDA5D01374A62A7420ADA2B S31500010CA81D48036CD90602D5036A0F930F9B274A81 S31500010CB8274B1A60EAE7224B2649EA5C695C264B10 S31500010CC8EB5C00912549695C0191E5210901695CA3 S31500010CD802912349695C03912249695C049122497D S31500010CE8695C05912149695C21480691311C03F02B S31500010CF84BFE074A0123536380235B00536380231A S31500010D089B0053630423536315B0F0BC01BC004731 S31500010D1800F4FFFF603A20000040FDFF142C20007C S31500010D281F4E0000D8081200384A0000D8091200E0 S31500010D38580A12008F070000A50D1200640F120051 S31500010D484C0E0000CCCA2000CCC82000010000A52A S31500010D5840FDFFFF4E0E00004D0E00004F0E000035 S31500010D68510E0000520E0000530E0000540E0000F2 S31500010D78960F1200F0B589B003AC061C0294FFF772 S31500010D88F1FB26232370002501230321201C637010 S31500010D98A57000F0C1F802AF011C2A1C331C00978C S31500010DA8201CFFF707FC1D4A1D4B13600B2808DDA5 S31500010DB80299281C023100F0BCF8011C194803F0FD S31500010DC8E3FD36232370002501236370E5700421B2 S31500010DD8201CA57000F0A0F80022011C331C009706 S31500010DE8201CFFF7E7FB0E4A0C4B1A600B2809DD9E S31500010DF802990020023100F09CF8291C021C0A48BD S31500010E0803F0C2FD802301355B009D42DFD107480F S31500010E1803F0BAFD09B0F0BC01BC004740FDFFFF75 S31500010E28010000A5D50F1200E20F1200F00F120003 S31500010E38F0B51E1C234B87B00593234B141C1A6867 S31500010E48051C03911F1C002A07D0204803F09CFDAE S31500010E58281C311C012203F0BDFD00239C4200D051 S31500010E6805AB0093291C301C0122039BFFF7A2FB4B S31500010E78051C002C22D0164C80235B0023633023EB S31500010E88011E994200DD191C059A00920022019360 S31500010E98FF20131C06F0F6FB80235B0063633B68A7 S31500010EA8002B0BD00B4803F06FFD281C0599FFF7A3 S31500010EB823FC281C0599012203F08CFD07B0F0BC20 S31500010EC801BC0047142C2000382A20000710120004 S31500010ED800F4FFFF0C10120030B50D4B021C141A5A S31500010EE88C420EDA14786340082401251D405B08FC S31500010EF8002D01D0074D6B40013C002CF5D1013284 S31500010F08EDE7DB431804000C30BC02BC0847C046B9 S31500010F18FFFF00000884000038B50C1C051CFFF70C S31500010F28DBFF28552D19000A6870A01C38BC02BCC5 S31500010F38084710B5041C86B0002800D10B4C487927 S31500010F48CA798B79009008790190C87802908878D7 S31500010F580390487804900978201C0591044905F006 S31500010F682CFE201C06B010BC02BC08473C2A2000F7 S31500010F78CD0E12000000000030B5002822D10A6803 S31500010F88531C0B60454B01249C540A6815190D60C6 S31500010F989C540A6814190C6098540A68541C0C600D S31500010FA898540A68541C0C6098540A68541C0C60BE S31500010FB898540A68541C0C6098540A68541C0C60AE S31500010FC8985467E008282DD106200A68531C0B603F S31500010FD8324B01249C540A6815190D609C540A6801 S31500010FE814190C60D418002222700C68651CE418C8 S31500010FF80D6022700C68651CE4180D6022700C687F S31500011008651CE4180D6022700C68651CE4180D60F7 S3150001101822700C680138651CE3180D601A7090423D S31500011028D3D137E00A2835D105200C68631C0B603B S315000110381A4B01221A550C68A5180D601A550C6829 S31500011048A5180D601A550A68541C0C60D41800229C S3150001105822700C68651CE4180D6022700C68651C0A S31500011068E4180D6022700C68651CE4180D60227086 S315000110780C68651CE4180D6022700C68651CE41880 S315000110880D6022700C680138651CE3180D601A7032 S315000110989042CAD130BC01BC0047C046142C20007E S315000110A810B5194C86B0201C0021184A05F0AAFF74 S315000110B80023201C164A116CCC0704D54321516222 S315000110C8144904240C63126CD106F3D5104A126A2A S315000110D8C254104A042151630C4A01339342E9D19F S315000110E8C478017842788378009404790194447924 S315000110F8029484790394C0790490074803F044FC68 S3150001110806B010BC01BC0047142C2000409C00000E S315000111180040FDFF00F4FFFF11101200F7B5071C90 S31500011128E0201C1C009101920FF0E2FA2B4805F011 S3150001113863FE201C05F084FF201801380378682B0C S3150001114844D18020800158210FF0F2FA012532207E S3150001115805F052FEFA20C00005F04EFE0FF0BAFA6D S315000111682378202293431E4EE020002B1AD00FF03D S31500011178BFFA0423381C736305F014FE802080012E S315000111885821002D00D15F210FF0D2FA04233363D1 S315000111982378302B01D1009800E0019805F002FE72 S315000111A80134DDE70FF0A4FA0423381C736305F054 S315000111B8F9FD802080015821002D00D15F210FF013 S315000111C8B7FAFFF76DFFF7BC01BC00478020800125 S315000111D85F210FF0ADFA0025B9E7C046C409000042 S315000111E800F4FFFFF8B5134C8025AD02071C8720D4 S315000111F82563800005F0D6FD6563072580263B1C1F S31500011208B6022B416663DA0701D50B4801E0872050 S31500011218400005F0C7FD2663962005F0C3FD013D94 S31500011228ECD280239B026363D22005F0BBFDF8BC98 S3150001123801BC004700F4FFFF8A020000F7B5C02091 S315000112480FF056FA0021254A254805F0DBFE254D03 S315000112588023DB026B60244C2B6780278023BF0227 S315000112681B022F602F6123600223FF3323600C23A7 S31500011278636000269F23266132206361A661E661C9 S3150001128805F0BAFD04236F632B63184F01F072FB57 S3150001129813490190236CDA0606D5134B1B6A8B5545 S315000112A8134B01369E4203DC124A134B1A60F1E7CF S315000112B801F060FB019BC41A01F05CFB211C021CB6 S315000112C80E4803F061FB04236B6380239B026B606A S315000112D8C023DB022B67F7BC01BC0047409C00001A S315000112E8142C200000F4FFFF0040FDFF85002000BC S315000112F83F9C0000010000A540FDFFFF4D101200B4 S3150001130808B5002803D080208001582102E08020FA S3150001131880015E210FF00CFAFFF790FF08BC01BCB3 S315000113280047F7B580205E2180010FF001FAC02041 S315000113380FF0DEF9FFF782FFE0200FF0D9F9002060 S31500011348011C051C021C061C031C041C4A4FEF1930 S3150001135801973F787F2F32D9019F7F783F063F1645 S31500011368002F2CDD01310F2929DDF10752080A4327 S315000113787608D9070E435B08E1070B436408281A68 S31500011388F8280CD90E21FF31884204D90022161CEF S31500011398131C141C05E0802109060C4301E0E3280F S315000113A8F4D95002FC21400AC903884205D1200A12 S315000113B8170C78400106090E0AD0281C00212F4F68 S315000113C80135BD42C2D12E48814201D02D484DE09A S315000113D8120E35021543360E1A02164322021B0E49 S315000113E8171C1F4323040AD5240C27486C4003F015 S315000113F885FA640401D0254802E0254800E025481D S3150001140803F07CFA2906090E00200FF0D5F9290AFE S315000114180906090E0FF0D0F9290C0906090E0FF075 S31500011428CBF9290E0FF0C8F93106090E0FF0C4F9E8 S31500011438310A0906090E0FF0BFF9310C0906090E22 S315000114480FF0BAF9310E0FF0B7F93F043F0C041C3F S31500011458311C11482A1C3B1C03F096FABC4204D0E5 S315000114680E48211C03F090FA02E00D4803F046FAF3 S31500011478F7BC01BC0047C046142C20003F9C000065 S315000114880B0F0000601012007D1012009910120057 S31500011498B0101200CC101200E5101200041112004F S315000114A825111200F7B50B1C23331B18061C8020C7 S315000114B880010D1C5E2101933B4F0FF039F9C020C5 S315000114C80FF016F901233B6380239B023B603B61C6 S315000114D80A24F020FFF786FE0120FFF783FE0F207E S315000114E8FFF780FE0120FFF77DFE0120FFF77AFE58 S315000114F80F20FFF777FE0B20FFF774FE0020FFF79A S3150001150871FE0620FFF76EFE8020FFF76BFE0220B4 S31500011518FFF768FE0820FFF765FE0120FFF762FE68 S315000115280820FFF75FFE1A20FFF75CFE1A20FFF777 S3150001153859FE1A20FFF756FE1A20FFF753FE2D20F3 S31500011548FFF750FE642005F057FCF020FFF74AFE2E S315000115580720FFF747FE0520FFF744FE0120FFF7A6 S3150001156841FE0720FFF73EFE0F20FFF73BFE300640 S31500011578000EFFF737FE2806000EFFF733FE019B24 S315000115881806000EFFF72EFEFA208000013C05F032 S3150001159833FC002C9DD101237B63044803F0AEF98B S315000115A8F7BC01BC0047C04600F4FFFF3711120023 S315000115B8F7B501902020264D0F1C161C0FF098F840 S315000115C8C0239B022B6080239B022B6180235B0235 S315000115D86B610024EA6B1E4BD1030CD4DB6B190239 S315000115E805D41C4803F08AF9F7BC01BC00471A4A1E S315000115F81A4B1A60EEE7002E01D004221A63184B23 S315000116081A5D80239B02002A01D02B6300E06B63DD S31500011618002E08D004236B6305E0DB6B1A02E0D5C4 S315000116280D4A0E4B1A60E96B80225202084B0A409A S31500011638F3D1019901348C42CCD1141C002FC9D0A5 S31500011648802292025A63381C05F0ACFBC2E7C046F9 S3150001165800F4FFFF3C111200010000A540FDFFFF49 S31500011668142C20007047F0B5404B85B0061C0020AD S315000116780191151C03909E4203DD3D4803F03EF996 S3150001168870E003A9FFF778FC082003A9FFF774FCAB S31500011698082003A9FFF770FC082003A9FFF76CFCD3 S315000116A80A2003A9FFF768FC0A2003A9FFF764FCCF S315000116B80A2003A9FFF760FC082003A9FFF75CFCD1 S315000116C80A2003A9FFF758FC2A4F2B4B3B600B2432 S315000116D803232340032B03D1002003A9FFF74CFC66 S315000116E8331C2341DA0705D50A2003A9FFF744FC71 S315000116F8082004E0082003A9FFF73EFC0A2003A9F5 S31500011708FFF73AFC013CE3D21B4B3B601F24032342 S315000117182340032B03D1002003A9FFF72DFC019BCE S315000117282341DA0705D50A2003A9FFF725FC082076 S3150001173804E0082003A9FFF71FFC0A2003A9FFF705 S315000117481BFC013CE3D2002D02D00C4B01221A638B S31500011758039800212A1CFFF72BFF002D02D0074B07 S3150001176801225A6305B0F0BC01BC0047FF0F000017 S315000117784411120040FDFFFF010000A500F4FFFF20 S31500011788F0B58BB004908020089180015F21099201 S3150001179807930EF0CDFF8020400300240EF060FF72 S315000117A8322005F029FB0EF095FF02940394059467 S315000117B8271CB54BB54807990360B54D002901D0DB S315000117C801232B63EB6B1A020AD4B24803F096F88D S315000117D8079B002B00D152E1AD4B01225A634EE122 S315000117E8AD488021AD4A05F00DFC0023AC4A116CC9 S315000117F8C80706D5432151620799002901D004215A S315000118082963126CD006F1D5A54A126AA2481206B6 S31500011818120E19180A707E2A01D8002200E0012248 S315000118280A7007990133002901D004226A639B498A S315000118388B42DBD1027843789A4200D20127934B37 S31500011848914A00201A6006900123934A9818451E6A S315000118582D78007885420ED20698DF1B3F0682183E S315000118683F0E17700120082F00D900201070069A24 S31500011878013206921F1C01338B42E6D18348824B03 S31500011888854E036000253778281C013E824B069950 S31500011898F31A01338B4234DA73780130BB422DD007 S315000118A837780621002F00D105210EF049FF0428BB S315000118B822D8794B0EF058FD0303060C15005F5527 S315000118C8013519E05F5531786A1C9954023513E0E0 S315000118D85F553078591C48553178AA1C99540335F7 S315000118E80AE05F5531785A1C51553078991C48558C S315000118F83178EA1C995404357378002001361F1C87 S31500011908C4E7614A614B1A600026AB1F9E4200DBA1 S31500011918B1E0614B9A5D002A34D05A1C925D002AC7 S3150001192830D09A1C925D002A2CD0DA1C925D002ACE S3150001193828D11A1D925D002A24D105339B5D002BFF S3150001194820D1029B03980343063623431ED063081E S315000119581B041B0C002807D0009352480399029ACE S31500011968231C03F011F804E04F480299221C03F0E6 S315000119780BF80499002938D0029A089B09981A602D S3150001198804607CE00599002933D002E00122059222 S315000119981C1C414B9A5D01339B5D002A0DD0002B1F S315000119A81BD102990398CA0F43001A4303924B00AD S315000119B8E20F1A430292640015E0002B0FD0039A36 S315000119C802985300C20F1A4303924300E20F1A43C7 S315000119D86400012302921C4305E0002400E01C1C5C S315000119E8029403940594013603E0049C029403943B S315000119F80594294B9A5D002A3BD05A1C925D002A10 S31500011A0837D09A1C925D002A33D0DA1C925D002ADF S31500011A182FD11A1D925D002A2BD105339B5D002B10 S31500011A2827D1029B063623431AD0630803991B0460 S31500011A381B0C002906D000931A48029A231C02F0AF S31500011A48A3FF04E018480299221C02F09DFF049A9C S31500011A58002A0AD0029B0898099903600C600EE0D7 S31500011A6801221C1C0293059203E0049C0294039430 S31500011A780594013649E7044B0448036099E60BB01F S31500011A88F0BC01BC0047C046010000A540FDFFFFB0 S31500011A9800F4FFFF3C111200142C2000409C0000AA S31500011AA80040FDFF601112007811120010B5041CE8 S31500011AB8802080015F210EF03BFE9020002C01D092 S31500011AC8C820400005F06EF9E0200EF011FEA020B6 S31500011AD805F068F910BC01BC0047F7B5071C802062 S31500011AE880010E1C5F211C1C01920EF021FE96201E S31500011AF805F082F9E0200EF0FBFDFA2005F052F917 S31500011B080120FFF7D3FF0020FFF7D0FF012C06D0F5 S31500011B1800208025FFF7CAFF20242D060BE080252B S31500011B2820242D060198013C2840FFF7BFFF6D08C8 S31500011B38002CF7D1ECE7381C2840013CFFF7B6FF2B S31500011B486D08002CF7D103240425301C2840013CDC S31500011B58FFF7ACFF6D08002CF7D180205F218001CB S31500011B680EF0E6FD142005F047F9E0200EF0C0FD61 S31500011B78F7BC01BC0047F7B52E4D00900191171C23 S31500011B8880212D4A281C05F03DFA802040032B4C64 S31500011B980EF066FD04260EF09DFD80205F21800172 S31500011BA826630EF0C5FD962005F026F9E0200EF015 S31500011BB89FFDFA2005F0F6F80120FFF777FF0020D0 S31500011BC8FFF774FF012F07D18024240601982040CE S31500011BD8FFF76CFF6410F9E70020FFF767FF03259D S31500011BE80098013D3040FFF761FF7610002DF7D1CF S31500011BF8802080015F210EF09BFD114B1A6CD107E5 S31500011C0801D543225A621B6CDA06F6D50C4B0949F3 S31500011C181B6A4B55084B01359D42EED1E0200EF06B S31500011C2867FD04236363074802F068FEF7BC01BC3D S31500011C380047C046142C2000409C000000F4FFFF1A S31500011C480040FDFF8C11120038B5224D224A802131 S31500011C58281C05F0D7F980204003204C0EF000FD22 S31500011C680EF038FD0423802023635F2180010EF0E6 S31500011C785FFD962005F0C0F8E0200EF039FDFA2048 S31500011C8805F090F80120FFF711FF0120FFF70EFF7D S31500011C98802080015F210EF04BFD0023104A116C54 S31500011CA8C80701D543215162126CD106F6D50C4AF3 S31500011CB8126AEA54084A01339342EFD1E0200EF042 S31500011CC817FD04236363074802F018FE38BC01BCFC S31500011CD80047C046142C2000409C000000F4FFFF7A S31500011CE80040FDFF8C111200F0B587B0041C944624 S31500011CF80593002B79D0754B984216D8020301D467 S31500011D08734B00E0734B1020660300D5202018435F S31500011D180423A70300D5082318430123E20300D5AA S31500011D280223184300250F2301E06B48C8E001226E S31500011D38171C9F405E003C4200D0B618B2401543BE S31500011D48013BF4D20F2300241F1C01221037161C55 S31500011D58BE40371C5E00394200D0B618B240144363 S31500011D68013BF1D2002702970F230122171C9F403E S31500011D785E00394205D0029FB618B2401743029752 S31500011D8803E0B240029E16430296013BEDD20027BC S31500011D9803970F231E1C01221036111CB1400E1C7D S31500011DA867465900374205D0039E89188A4016436B S31500011DB8039603E0039F8A4017430397013BE9D241 S31500011DC80F23002601225F00111C019799406746DF S31500011DD80F4202D00199891800E001998A401643F9 S31500011DE8013BEFD20627049735E03C4B994201D9CE S31500011DF83B4865E0E8200B2340050122151C9D4060 S31500011E085C00294200D0A418A2401043013BF4D239 S31500011E180F2300251C1C01221034161CA6406746F8 S31500011E285900374200D089188A401543013BF1D23F S31500011E380F2300240122161C9E406746590037428B S31500011E4800D089188A401443013BF3D2032604962D S31500011E58002603960296234F00220421131C396398 S31500011E680121FFF73AFE0022131C281C0221FFF765 S31500011E7834FE0022131C201C0321FFF72EFE059AAF S31500011E88002A11D00022131C02980421FFF725FE0F S31500011E980022131C03980521FFF71FFE0022301CA0 S31500011EA80621131CFFF719FE049E0F480021730132 S31500011EB818430A1C0B1CFFF710FE04237B630B480F S31500011EC802F01CFD07B0F0BC01BC0047FFFF0F0084 S31500011ED840A9961D80A9961D92111200FF0F0000B8 S31500011EE84411120000F4FFFF007010008C1112005B S31500011EF8F0B589B002900C1C002600270023301C7F S31500011F08391C0125801979411F2B05DC15402E1C2A S31500011F1806430F1C520804E025402E1C06430F1CDD S31500011F2864080133282BEAD100215A4D584C0091F7 S31500011F380123009833409C4680070DD1009A002A58 S31500011F480FD0221C2B1CC81712196B410C1C051C1F S31500011F5814431D43614600E059400098032805DCF7 S31500011F6800E0191C009A930062460AE000980323D0 S31500011F7803409B0010226846D21812586046019207 S31500011F884240103368461A50221C2B1C12196B4109 S31500011F981D1C64467B081443FA071F1C009B9446C4 S31500011FA801337208664616430093282BC0D1221CBA S31500011FB82B1CC81712196B410C1C051C14431D4315 S31500011FC80021221C2B1C12196B41102464186D4622 S31500011FD86059C617041C351C043114431D431029C6 S31500011FE8EFD1029824196D41002801D02A4900E051 S31500011FF82A492B482B4F02F0C7FC002204233B63D6 S31500012008281C131C0121FFF768FD0022131C201C44 S315000120180221FFF762FD029A002A20D01604360E25 S315000120282148311C02F0B0FC102E12D002D8002E25 S3150001203804D006E0202E09D0402E02D1A0235B034E S3150001204809E01A48311C02F09FFC1BE080231B03A0 S3150001205801E08023DB0216480021184301E01548F8 S3150001206802990B1C0A1CFFF738FD04237B63029BAC S31500012078002B01D0084900E008490F482A1C231CF7 S3150001208802F082FC09B0F0BC01BC0047C046C0465C S31500012098FF01000000000000AE111200B411120089 S315000120A8BA11120000F4FFFFD5111200E411120053 S315000120B84080000004F00100FB111200002210B557 S315000120C8131C0C1C0121FFF708FD0022201C131C00 S315000120D80221FFF702FD00210A1C0B1C0448FFF729 S315000120E8FCFC044802F00AFC10BC01BC0047C046CF S315000120F8401008008C11120070B5151C00220E1C28 S315000121081C1C0121131CFFF7E8FC0022301C131CC0 S315000121180221FFF7E2FC0022281C131C0321FFF70A S31500012128DCFC0022201C131C0421FFF7D6FC00222C S315000121380498131C0521FFF7D0FC00220598131CEF S315000121480621FFF7CAFC00220698131C0721FFF790 S31500012158C4FC00210A1C0B1C0448FFF7BEFC0448FA S3150001216802F0CCFB70BC01BC0047C046E010080079 S315000121788C111200F0B5E5B003900020FFF7C0F806 S315000121885F4B59781A7891420DD90221581802786D S3150001219801380078904201D3C02A12DC594A01312C S315000121A89142F3D10DE002215818027801380078DE S315000121B8904201D83F2A06DD524A01319142F3D1B4 S315000121C801E0002500E00125002400944B1C201C99 S315000121D8221C4D4FBB4200DD87E04C4EF75C02974F S315000121E8371C0137B446FF5C029E0197BE4203D9EC S315000121F8012D01D1C02F07DC029F019EB74265D28E S31500012208002D62D13F2E61DC591A0D1C103D0F2994 S3150001221801DC10256D1A072D05DC1D1A181C8D42C7 S3150001222849D160330BE00D1C203D1F2901DC202517 S315000122386D1A072D10DC1D1A8D4204D15033FF3358 S31500012248802A35D113E0009F012F4BD1002624A9FE S315000122588E54013200962EE04039CD17491969404E S31500012268072928DC012524A98D54521923E02101C7 S3150001227804AD681824AA0021D57996796D00AD199F S3150001228856796D00AD1916796D00AD19D6786D00C0 S31500012298AD1996786D00AD1956786D00AD19167899 S315000122A86D00AD194554013108321029E4D10134C4 S315000122B800200090021C654601356646F15CEF5C1C S315000122C800258F426D41191C00E00125FF277F4239 S315000122D8BF187E1EB74102977F423A40042C04D0AC S315000122E8013376E701270097E5E72201039804A958 S315000122F804F07CFE201C65B0F0BC02BC0847C04651 S31500012308142C2000409C00003F9C0000132C200048 S3150001231870B5124E0822311C041C04F07FFE251CE0 S315000123280935002808D1311C0931281C072204F077 S3150001233875FE012300280DD0311C0931281C0722FE S3150001234804F06CFE002801D0002303E0E379002B9A S31500012358FAD10123181C70BC02BC0847580B12009D S31500012368827A031C0020824211D1DA7A82420ED186 S315000123781A7B82420BD15A7B824208D1997B7F22F2 S315000123880A40092A03DCDB7B09229A42404170474D S31500012398F0B5C9B00021882226A804F033FE002230 S315000123A815210823149113920F93151C171C00214C S315000123B8402216A804F026FE16A8FFF7DBFE13999D S315000123C843424341C918119013910A2900D092E05A S315000123D8002F01D1AB488BE0AB4802F0D5FAAB48E8 S315000123E802F0D2FA49E0002D00D1B3E000231093A0 S315000123F8109B11998B4200DB36E1109916AA0B0145 S31500012408A349D2181592101C1131102204F006FEA8 S31500012418002800D124E100231293129A1121514375 S3150001242826AB59180B7C012B00D012E11598102206 S3150001243804F0F4FD002800D00BE1109D129C013D2B S31500012448013C002D00DADFE0611C00D10F9C11264A S31500012458664326AA9619337C002B00D0D2E016AB28 S315000124682901C918301C102204F0C0FD0123337458 S315000124780F99FF188F4200D0C4E0864E301C02F037 S3150001248883FA854802F080FA301C02F07DFA26AC00 S3150001249800250F998D422ADA237C012B20D1E07879 S315000124A821786278A378009020790190607902906A S315000124B8A0790390E0790490207A0590607A0690D5 S315000124C8A07A0790E07A0890207B0990607B0A90B1 S315000124D8A07B0B90E07B0C90704802F055FA03E064 S315000124E86F48291C02F050FA01351134D1E7301C26 S315000124F802F04AFAC2E0149A013A1492002A00D16B S315000125086AE716AC0026119A964200DB6BE7E0787B S3150001251821786278A37800902079019060790290F9 S31500012528A0790390E0790490207A0590607A069064 S31500012538A07A0790E07A0890207B0990607B0A9040 S31500012548A07B0B90E07B0C90564802F01DFA0136F1 S315000125581034D8E71AAE2C1C119B9C4200DB84E090 S31500012568301C1038FFF7D4FE611C1091002846D0A4 S31500012578119B013B9C4242DA301CFFF7F1FE002811 S315000125883DD026AD16AA21015118281C102204F0A7 S315000125982DFD109B16AA1F016846D1190126102286 S315000125A8A9302E7404F022FD6B469A33E97F9A7F8F S315000125B8DE777F230B40934200DA131C01333A4836 S315000125C8191C0F9302F0E0F96E46A51CBA360227CC S315000125D8A54249D011996B1A5A1E93415B421D4077 S315000125E8A54241D0290116AA5118301C102204F01F S315000125F8FDFC01233374ED18FF181136E8E7109C2A S315000126081036A9E7013D1BE7109D129C0135119A69 S31500012618013495421DD00F99E20FCB17A1425341C0 S315000126285B421C401126664326AA9619337C002B69 S315000126380DD116AB2901C918301C102204F0D6FC9D S31500012648012333740F99FF188F4200D115E701351D S31500012658DDE7129B0F99013312938B4200DADCE610 S31500012668109A01321092C3E60125104BDB6B1A0250 S3150001267804D50F9B9F4200D099E6FEE649B0F0BC0F S3150001268801BC00471B121200341212004A12120032 S31500012698580B1200D1121200FB1212006C12120012 S315000126A80B13120066121200BC12120000F4FFFF8F S315000126B8104B1A68511C10B51960002111701A685F S315000126C8541C1C6011701A68511C196010701A6824 S315000126D84008511C196010701A684008511C19608D S315000126E810701A684008511C19601070062010BC39 S315000126F802BC084798C8200030B5062300210B4ABA S315000127081468013B651C1B061560414020701B0EB1 S315000127184008002BF3D11368581C106001221140A0 S315000127280720197030BC02BC0847C04698C820006B S31500012738F7B500220191131C00210D1C0126064044 S315000127488E407340174E37680097BC460127BC4434 S31500012758674604063760009F240E1B060131654053 S315000127681B0E3C7040080829E8D131684C1C3460BE S315000127780D70012A00D1019801321206120E042A9F S31500012788DAD108223168013A481C12063060120E65 S315000127980B705B08002AF5D133682D201A70FEBC30 S315000127A802BC084798C8200038B5214D214B224C58 S315000127B82B60224B0422207080201A635F2180013E S315000127C80DF0B6FF962004F017FB2378013B237022 S315000127D82B68E02001332B600DF08AFFDC204000D6 S315000127E804F0E0FA802080015F210DF0A1FF80202E S315000127F804F0D8FA23785A1E2270002B15D02B68BC S315000128085A1C2A601B78DA0702D580204000EFE7B8 S31500012818E0200DF06DFFB82004F0C4FA8020800195 S315000128285F210DF085FF4820E2E738BC01BC00476F S3150001283894C8200054C820009CC8200000F4FFFF5B S3150001284838B50C4A0C4B041C0C201A60FFF730FFF4 S31500012858051C2004210C000CFFF76AFF401900062D S31500012868000EFFF7A1FF142004F0C6FA38BC01BC1C S315000128780047C04654C8200098C8200038B5051C32 S31500012888012A02D1081CFFF7DBFF1B4B1B4A092053 S315000128981A60FFF70DFF041C281CFFF72DFF184DC2 S315000128A88021184A0419281C04F0ACFB2406802050 S315000128B84003240E0DF0D4FE0DF00CFF201CFFF78B S315000128C873FF0023104A116CC80701D543215162D1 S315000128D8126CD106F6D50C4A126AEA54094A013332 S315000128E89342EFD1E0200DF003FF084B04225A630F S315000128F838BC01BC0047C04698C8200054C820000F S31500012908142C2000409C00000040FDFF00F4FFFF4E S3150001291870B5051C0E1C012B02D1101CFFF790FF88 S31500012928114A124B0A201A60FFF7C2FE041C301C1A S31500012938FFF7E2FE04192804290C000CFFF7F8FE3C S315000129482406240E20180006000EFFF72DFF14207A S3150001295804F052FAE0200DF0CBFE054B04225A632F S3150001296870BC01BC0047C04654C8200098C8200066 S3150001297800F4FFFF3847C0460123F7B54E0B1E404A S31500012988CC0A9E401C4034198A0A9C401A40A21857 S315000129984D08464C9A401D405519221CEA408E00A6 S315000129A8151C0F1C820F1F4032431A409F400E010F S315000129B8BF18020F32431A409F404E01BF18C20E7C S315000129C832431A409F40BF18394A161CFE401D4023 S315000129D8371C9D401F40CE01EF19450E35431D405A S315000129E89D4001958D02AC466646850D35432E1CE4 S315000129F8019D1E40AE199E400196050D0E033543F5 S31500012A082E1C019D1E40AE199E400196050C0E0412 S31500012A1835432E1C019D1E40AE19151CF5402E1C72 S31500012A289F401E40BE19850B8F043D439E401D40A5 S31500012A3801966F00CE04450B35431D407F194D05A0 S31500012A48AC466646C50A35431D409F407F194D066B S31500012A58AC466646C50935439F401D407D19EA4087 S31500012A68019D1A40AE18CD0642092A431A400F079E S31500012A78550002093A431A408F07AD1882083A43AE S31500012A889D401A40C907D840AA1808439A401840D9 S31500012A981018C440201C9E401840064C3018C440EB S31500012AA8201C1840FEBC02BC0847C046792C000011 S31500012AB8716600007B280779F0B5050487B0002404 S31500012AC8039005912D0C101C211C049300196941D2 S31500012AD8CB0746081E434F08391C301CFFF74CFF2D S31500012AE8221C051C1032039805990DF0B5FE049BAE S31500012AF8E3405840012318404540ED030023019562 S31500012B08009300980199013480197941202CDFD16D S31500012B1807B0F0BC04BC10474168F8B50468CD0796 S31500012B2862082A43A7088D074E072F43E508354350 S31500012B386F408E06A509674035437D404E06E70975 S31500012B4837436F40260A0D062E437E40250C0F0497 S31500012B583D437540A70D8E0237436F40E60D4D0282 S31500012B682E437E40A50E8F013D437540A40F8E006E S31500012B7834434F0A6C407C408F0A7C40CF0A7C4024 S31500012B888F0B7C40CE0B4B08211C01257140294037 S31500012B980024CF03261C92197B4102604360191C4D S31500012BA8101CFFF7E9FE211CF8BC04BC104770B5E0 S31500012BB80024061C251C301CFFF7AEFF07236B40BB S31500012BC8984001352418082DF5D1201C70BC02BC8B S31500012BD80847F0B585B00290019103921D1C0C1CA3 S31500012BE88E18B44207D002982778FFF7E0FF4740CE S31500012BF827700134F5E70724671BBC420DD0019AFB S31500012C08039B0298D5182E78FFF786FF221C0DF034 S31500012C187BFD46402E70013CEFE7002005B0F0BC75 S31500012C2802BC0847114B012210B51A63104A042148 S31500012C381160802189020F4C00280DD15963106952 S31500012C48A042FCD9196310690B498842FBD90122B4 S31500012C585A6310BC01BC004719631069A042FCD92C S31500012C685963106904498842FBD9F0E700F4FFFF6C S31500012C780000FAFFFF0B0000FF170000F7B5334C01 S31500012C880D1C276832490090944600208F425ADC71 S31500012C9830490868021C62440A60101C01922E4AD7 S31500012CA87E1C2660061C1068C6552068471C2760CE S31500012CB80F6816683F1237542068471C27600F684B S31500012CC816683F1437542068471C2760C978176867 S31500012CD839540898002808D12168166801397118ED S31500012CE80F78802040423843087021681768481CCD S31500012CF820607B5421681668481C2060180A7054A5 S31500012D0821681768481C2060180C78542168481CEB S31500012D18206010681B0E43542368591C21601168F2 S31500012D28CD5417682268281CBF1803F055FF00996F S31500012D38021C381C04F05AF9281C266803F04CFFBB S31500012D48861926600120FEBC02BC0847142B200008 S31500012D58B70B0000182B200060002000024B002052 S31500012D6801221A71187370470000200008B5FFF791 S31500012D78F5FF002008BC02BC0847F0B5ADB00E90BF S31500012D88081C0F930C1C149203F026FF27AD021C96 S31500012D980E99281C04F02AF94E4B1A7B002A07D0F3 S31500012DA8181C07231030E20823400E99FFF711FF7C S31500012DB80F98002606600A2C19D002D8052C06D0D1 S31500012DC8E8E3202C5CD0402C00D189E0E2E32B78A3 S31500012DD8C02B00D0EBE30F9C3E492023236018311A S31500012DE81498042204F002F93A4D2E73D2E30E9D8B S31500012DF829786A78880004279309384018430723F5 S31500012E081D1C8543C80803409D4200D0CFE33923E2 S31500012E18081C98430006030E822B1FD0C02B05D031 S31500012E28442B29D12B4BAD005D190BE029490635F9 S31500012E38AD00491914983A1C04F0D8F80F9C2023C0 S31500012E482360A7E3AB191B7E149CDB43A35501360C S31500012E58042EF7D10F9D20232B609BE3201C03F042 S31500012E68BBFE0E99021C149804F0C0F8194B0F9E6C S31500012E7834609D601F718DE3174801F085FD96E367 S31500012E88144D2B79042B10D1AE68201C351C114E1C S31500012E9803F0A2FE0635AD007519021C0E99281C11 S31500012EA804F0A4F80123337181E30A490E981C3111 S31500012EB8042204F0B3F8002803D0084801F01EFDE7 S31500012EC875E30F9D03492C6024311498042204F0FC S31500012ED88DF85FE3000020001E131200381312005C S31500012EE8FA4EFB4BB06C984209D8F16C08220818C7 S31500012EF80E9904F07BF8B26C131C0833B364F34DD6 S31500012F08F44C2B7FE27F1B0412021A432B1C03335A S31500012F18DB7F1A436B7F1B061A43AB7FED7FEB4EB4 S31500012F282D021D439446B37E727E1B0412021A4378 S31500012F38337E1A43F37E0E9C1B061A430C92A37822 S31500012F4862781B0412021A4323781A43E3781B0694 S31500012F5860461A430D92C301FF221A4000230B93C0 S31500012F68C1096B0666460A921943EC09760E18944E S31500012F780A1C01240A980B991596224066460023D5 S31500012F8812184B41A806B10901430E1C2640002719 S31500012F98B6197F4192197B41A809664619907109AC S31500012FA8E806014321408E00002792197B416809F2 S31500012FB866461A903109280701432140CE000027A9 S31500012FC8B6185F416246D108EB0821401C930A01F5 S31500012FD8002392197B416646B10821404E0100271C S31500012FE86146B6185F4128094B086A081B902340B9 S31500012FF8A8081D901E9298010021321C3B1C6646AA S3150001300812184B4110921193B10BAB0419430A1CC8 S31500013018760BE9040E43A80B690B264022400023D0 S3150001302892185B411F902091B000002180185941E8 S3150001303862466B04D60B1E43321C224000238018BD S31500013048594162462B05160B1E4326402B0B21932D S31500013058F20000238018594162466B05D60A1E43C1 S315000130682640EB0A22933201002380185941624611 S31500013078AB05960A1E432640AB0A23937201002329 S31500013088801859416246EB05560A1E4326406B0ACB S315000130982493B201002312184B4160462906060AF9 S315000130A80E43F601290AFF20259130400021801898 S315000130B85941060E02020B021098119933438018E2 S315000130C85941624610901191AB02910D6046194320 S315000130D80A1C460DE9020E43264022400023921897 S315000130E85B41B00000218018594162466B02D60D3A S315000130F81E43321C2240002312184B416046290305 S31500013108060D0E432640F000002112184B41604679 S315000131186903C60C0E4326403001002112184B41A3 S315000131286046A903860C0E43264070010021121839 S315000131384B416046E903460C0E432640B001002187 S315000131486646801859412A04330C1343DB01FF26CE S3150001315800271E40021C0B1C92197B4166461692DB S315000131681793B10FAB0019430A1C760FE9000E43FA S315000131783B1C2640224092185B41391CB00080183E S31500013188594162466B00D60F1E43321C3B1C224036 S3150001319812184B4160462901060F0E432640391C79 S315000131A8F00012184B4160466901C60E0E432640CF S315000131B8391C300112184B416046A901860E0E438F S315000131C82640391C700180185941EA01159B161CC5 S315000131D81E43264012923B1CB201664612184B4109 S315000131E82802310E0143C901FF260E400027101C93 S315000131F8191C80197941060E02020B0216981799B5 S31500013208334380185941060C02040B04109811998E S31500013218334380185941199E1A9B2640234000279B S3150001322810901191B6197F419800002180197941B2 S31500013238189E0027264036184F411B992140CA007F S315000132481C990023214092197B410E010027B618CB S315000132585F411D9B234058010021801979411E9E1B S315000132682640B2010023129E12184B41FF21002766 S315000132780E40101C191C8019794112901391209E39 S315000132881F98391C26402040001849413B1CB200B2 S3150001329812184B41E80B391C80185941219B2340D0 S315000132A8DE00229B00272340801979411E01239BBA S315000132B800272340801979415E01249B002723407A S315000132C8801979419E01002706E0C04600002000CA S315000132D8AF0A00000400200036184F412599FF2047 S315000132E8CB011840002136184F41129D31026B1847 S315000132F8109811990022801859410C9A1090119131 S31500013308FF23D1010C9D1940D3092340CA18AB09E3 S315000133182340A340D2186B0923409B00D2182B09DE S315000133282340DB00D218EB08A90823401B012140E2 S31500013338D2184901521869082140890152186B0BA4 S31500013348A90B21402340A1409B00CB18E90B214042 S3150001335859182B0B2340DB00C918EB0A23401B0124 S31500013368C918AB0A23405B01680AC91820402B0A11 S31500013378FF268001DB0109183340CB181B02D3183D S31500013388A90D6A0D21402240A14092008A18E90D33 S31500013398214051182A0D2240D2008918EA0CA80C9E S315000133A8224012012040891840010918680C2A0C8C S315000133B820408001D201091832408A18A80F690FE6 S315000133C8204021408900A0404018E90F4018290FE4 S315000133D82140C9004018E90E214009014018291C5D S315000133E8AD0E25406D01490E401921400C9D8901FC S315000133F84118280EC001304009180E020D98961979 S3150001340836049E19C101FF22C30911402340CA1877 S3150001341883092340A340D218430923409B00D218AD S3150001342803092340DB00D218C308810823401B0186 S315000134382140D218490152184108214089015218E0 S31500013448430B810B21402340A1409B00CB18C10BA4 S3150001345821405918030B2340DB00C918C30A23402E S315000134681B01C918830A0D9D2340400A5B012040B0 S31500013478C91880012B0A0918DB01FF200340CB1864 S315000134881B02D318A90D6A0D21402240A1409200C2 S315000134988A18E90D214051182A0D2240D2008918AF S315000134A8EA0CA80C2240120120408918400109188B S315000134B8680C2A0C20408001FF25D20109182A40F0 S315000134C88A180D99880F490F0D9D204021408900C2 S315000134D8A0404018E90F4018290F2140C90040189B S315000134E8E90E2140AD0E0901254040186D0140192C S315000134F80D9D690E214089014118280EC001FF253D S3150001350828400918090251180904321C5B18109839 S315000135181199FFF7D1FA284E30617161274E0C36A1 S31500013528301CFFF744FB26ADC0432870301CFFF75B S315000135383EFBC0436870301CFFF739FBC043A870D7 S31500013548301CFFF734FB0E99C043E8700431281C80 S31500013558042203F063FD002811D00E9CE07821783F S315000135686278A37800902079019060790290A07919 S315000135780390E0790490124801F006FA17E00E4D1F S31500013588291C2431149804222C7303F02FFD0F9E55 S31500013598202333600848037B002B08D00F9C23683F S315000135A80721DA0810300B401499FFF712FB2DB0EA S315000135B8F0BC01BC0047C046000020000400200002 S315000135C851131200F7B500240190161C1F1C1C602C S315000135D8A14202D0202913D059E0304B1B78002B89 S315000135E803D02F4801F08AF93DE00520386003F041 S315000135F8F3FA2C49021C301C03F0F8FC01204AE0BE S31500013608264A1378284C002B14D13960301C2749D7 S31500013618042203F0EBFC2568254AA81D01261F4B49 S315000136288000101801990422AD191E7003F0DEFC02 S315000136382560E3E72568012D03D11D48311C1C309F S3150001364804E0A81D1A4B80000199181804220135B7 S3150001365803F0CCFC2560072D07D9164801F04EF971 S31500013668154B01221A70002015E00A233B602368D6 S315000136784020DA0040421043072253409908031CB0 S315000136880B43337023685A4092017270B6E70B48B0 S3150001369801F07AF9201CFEBC02BC0847B9C8200013 S315000136A88013120091131200BCC82000A0C8200084 S315000136B80000200093131200B8C82000A3131200BB S315000136C8F0B59BB00893089E00233360264B0392FE S315000136D81A78041C0D1C002A06D00723CA080B40B9 S315000136E82248211CFFF775FA002D02D0202D4BD058 S315000136F811E31D4E3378002B2AD01D4B1B78002B66 S3150001370803D01C4801F0FAF81DE31B4E34681B4828 S31500013718012C06D11A49042202311C3003F066FC39 S3150001372810E0022C0BD1431CDD77831CDD77144B8B S3150001373819785B78C21C0430D177C37702E0A31DE0 S315000137489B00C550084D0134002334602B70E8E214 S31500013758089E0520306003F03FFA0A49021C0398C7 S3150001376803F044FCDDE2C046C0C82000B0C8200012 S31500013778C9C82000BB131200BCC8200000002000E5 S31500013788C1C8200091131200FB4D2D780195002D1B S3150001379800D08FE2F94B59789A780902120411433D S315000137A81A781143DA785D79120611431A792D02CE S315000137B81543A37862781B0412021A4323781A4325 S315000137C8E3788C4666461B0660461A43490EF301A2 S315000137D8FF261E4009916B06C109019F19430292F2 S315000137E8EA0901240C920A1C3B1C224092197B41CE S315000137F86646A806B10901430E1C019F2640B61963 S315000138087F4192197B41A80966460D907109E80620 S31500013818014321408E00002792197B4168096646BB S315000138280E903109280701432140CE000027B6181A S315000138385F416246D108EB08214010930A01002333 S3150001384892197B416646B10821404E01002761461F S31500013858B6185F4128094B086A080F902340A80843 S315000138681190129298010021321C3B1C12184B41EF S31500013878664604920593AA04B30B1343A80B019950 S315000138881390181C2040021C0B1C12184B41760B76 S31500013898E9040E432640690B1491B00000218018F3 S315000138A8594162466B04D60B1E43321C019B2240CA S315000138B88018594162462B05160B1E4326402B0BD1 S315000138C8F200159300238018594162466B05D60A02 S315000138D81E432640EB0A32011693002380185941EC S315000138E86246AB05960A1E432640AB0A7201179338 S315000138F80023801859416246EB05560A1E432640A5 S315000139086B0A1893B201002312184B416046290627 S31500013918060A0E43290A1991F6010199FF2030403A S3150001392880185941060E02020B0204980599334381 S3150001393880185941624604900591AB02910D604683 S3150001394819430A1C460DE902019B0E4326402240F3 S3150001395892185B41B00000218018594162466B02FA S31500013968D60D1E43321C019B224012184B4160465C S315000139782903060D0E432640F000002112184B417B S3150001398860466903C60C0E43264030010021121811 S315000139984B416046A903860C0E432640700100215F S315000139A812184B416046E903460C0E432640B00106 S315000139B800216646801859412A04330C1343019F96 S315000139C8DB01FF261E40021C0B1C92197B41664631 S315000139D80A920B93B10FAB0019430A1C760FE90043 S315000139E80E433B1C2640224092185B41B000002141 S315000139F88018594162466B00D60F1E43321C3B1C88 S31500013A08224012184B4160462901060F0E432640F3 S31500013A18F000002112184B4160466901C60E0E439B S31500013A2826403001002112184B416046A901860E35 S31500013A380E4326407001002180185941EA01099B6D S31500013A48161C1E43264006920023B201664612182A S31500013A584B412802310E0143019FC901FF260E4041 S31500013A68101C191C80197941060E02020B020A98CC S31500013A780B99334380185941060C02040B04049828 S31500013A8805993343801859410D9E0E9B019F23408A S31500013A98264004900591B6197F41980000218019A6 S31500013AA879410C9E019F264036184F410F992140B6 S31500013AB8CA0010990023214092197B410E01002763 S31500013AC8B6185F41119B234058010021801979419D S31500013AD8129E2640B2010023069E12184B41019FF1 S31500013AE8FF210E40101C191C801979410690079177 S31500013AF8149E1398391C2640204000184941B200EB S31500013B08002312184B41E80B391C80185941159BA3 S31500013B182340DE00169B00272340801979411E01A8 S31500013B28179B00272340801979415E01189B0027BE S31500013B382340801979419E01002736184F4119996A S31500013B48FF20CB010199184036184F41069D02986E S31500013B583102019A049E059F6B18B6185F41C1018F S31500013B68FF22C30911402340CA1883092340A340F1 S31500013B78D2184309234003E0C0C82000C1C8200069 S31500013B889B00D21803092340DB00D218C308810819 S31500013B9823401B012140D2184901521841082140EE S31500013BA889015218430B810B21402340A1409B00F8 S31500013BB8CB18C10B21405918030B2340DB00C91848 S31500013BC8C30A23401B01C918830A029D2340400AE0 S31500013BD85B012040C91880012B0A0918DB01FF2067 S31500013BE80340CB181B02D318A90D6A0D21402240A8 S31500013BF8A14092008A18E90D214051182A0D224048 S31500013C08D2008918EA0CA80C224012012040891812 S31500013C1840010918680C2A0C20408001FF25D201B1 S31500013C2809182A408A180299880F490F029D2040CF S31500013C3821408900A0404018E90F4018290F21406A S31500013C48C9004018E90E214009014018A90E214072 S31500013C586D0E490125404018AD014019029D290EF6 S31500013C68C901FF25294041180902521812049A1858 S31500013C78301C019B391CFEF71FFF354E04223060AC S31500013C8871600199039803F0BDF9039D0435281C59 S31500013C98FF21042203F0B6F9301C291C019B0422DA S31500013CA8FEF797FF089E402333602A4D2A4B2C7056 S31500013CB81C7036E0284B1A78284D002A02D00022BB S31500013CC81A700AE02E68264BB01D80001818211CB0 S31500013CD80422013603F08AF92E602E68072E06D9CA S31500013CE8204800F00BFE204B01221A7017E0089EAF S31500013CF80A2333602B684020DA004042104307222A S31500013D0853409908039E031C0B4333702B685A4092 S31500013D189201727005E01548291C00F035FE002550 S31500013D2811E00C4B1B780125002B0CD00A4B1B7894 S31500013D38002B08D1089E33680721DA0804480B408E S31500013D480399FEF746FF281C1BB0F0BC02BC0847C6 S31500013D58B0C82000C0C82000C9C82000BCC82000BF S31500013D680000200093131200B8C82000A313120004 S31500013D7870B500250C1C161C1D60A94202D020290D S31500013D8814D025E0164A1278002A04D0154800F006 S31500013D98B5FD201C20E00520186002F01DFF124920 S31500013DA8021C301C03F022F9012015E00C4C227884 S31500013DB8002A09D140221A60301C0C49082203F056 S31500013DC815F90120207007E0094800F097FD02E087 S31500013DD8084800F0D9FD281C70BC02BC0847C0463B S31500013DE8C0C82000BB13120091131200A4C82000FA S31500013DF8D2131200A3131200F0B5002589B006915B S31500013E0807921E1C1D60A94202D0202938D067E0FE S31500013E1838480378002B2BD0374CE0782178627824 S31500013E28A37800902079019060790290A079039097 S31500013E38E0790490314800F0A7FD314D314FEB6C24 S31500013E483968581808315918082203F0CFF8069B23 S31500013E582849AA6C0B703B68083AAA64934201D1B7 S31500013E68002042E0E96C201CC918082203F0BEF8BC S31500013E780520306002F0B0FE2349021C07982BE0AA S31500013E881C4F3B781C4C002B09D140233360079803 S31500013E98211C082203F0AAF80120387025E0E078F1 S31500013EA821786278A3780090207901906079029050 S31500013EB8A0790390E0790490144800F065FD114952 S31500013EC80F4A0B68906C08333D708342C8D00B606B S31500013ED8D16C201CC918082203F088F8012004E0D7 S31500013EE80B48069900F050FD281C09B0F0BC02BC2D S31500013EF80847C046C0C82000A4C82000EC13120019 S31500013F0800002000502A2000911312002A141200E2 S31500013F18A3131200F0B501208FB00CF0E5FB0CF0ED S31500013F2887FC994B994A0025D86C994E291C15602E S31500013F38984A9D64042703F065F88024964800F0A2 S31500013F48DDFCA401376320200CF0D2FB201C5F2185 S31500013F580CF0EEFB802040030CF082FB80239B04CF S31500013F68736380239B023361336073638B4B1C61DC S31500013F7880238B4C1B02736702232360894B636082 S31500013F880523236009A8291C142203F03BF8012004 S31500013F9804900790069505972F1CF36B190200D418 S31500013FA8DAE0814A814B1A6000247D4B804A1969FF S31500013FB8914200D991E01A6A9106F6D55869C0214D S31500013FC80CF004FCF36B0122DB0B2D18134003954F S31500013FD8002F0FD1002B2FD00C280DDC6C4B802223 S31500013FE892005A63391C09A814223C1C03F00AF8EA S31500013FF8012703E0012B01D0039DD6E780235B004F S315000140083363039B232B02DD083B06934BE003989E S3150001401818280BDD0721A1430120E20809AB8840D6 S31500014028011C985C0143995401343CE0039900252D S315000140380E29BADD0134B8E78023039A9B0033635E S315000140484F2A02DD103A06920FE0039B382B0EDD4C S31500014058611C07208843CA08011C012009AB884056 S31500014068011C985C0143995402343D1C9DE7039950 S3150001407828291ADD049A631C002A0BD107209843C4 S31500014088D908031C012009AA9840031C505C034364 S315000140985354A31C079841424141079104990122AF S315000140A8514004911C1C00257FE7039A3D1C182AE0 S315000140B800DC7AE7059B002B02D0013B059374E7E8 S315000140C807980721A143E20809AB8840011C985CBF S315000140D8014399540134059D67E7002C33D00097B5 S315000140E809A8211C069A0023FEF7C8FD002803D15A S315000140F8304800F003FC2FE0201C02F06DFD021E83 S31500014108082A0CD1204C2C4BA06C984207D8E16C9C S31500014118081809A902F06AFFA36C0833A3641422DC S3150001412809A8002102F06EFF80235B0073638023D8 S315000141389B007363002701230422059204930793C6 S315000141483D1C069704E01869C0210CF03FFB2D18A9 S3150001415813480423036020E701248023A340346322 S31500014168736380239B0073630D4A042373630223DD S315000141781360124AE02013600CF0BAFA74630FB0A8 S31500014188F0BC01BC0047C04600002000502A2000B0 S3150001419800F4FFFFB80A00005414120000FCFFFFE8 S315000141A84000FAFF00070300010000A540FDFFFFDC S315000141B8FF3B00006A141200AF0A00000000FAFF74 S315000141C8F0B58A4E91B00024029001200F1C059487 S315000141D834710CF089FA0CF02BFB854D211C854AAC S315000141E8E86CAC64346002F00DFF834C834800F040 S315000141F885FB04232363FEF7B1FD0298002808D046 S315000142087F4800F07BFB281C1830391C302202F04D S31500014218EDFE0026371CB200AA180023D118097E24 S315000142283F0201330F43042BF8D1311C75483A1C60 S31500014238013600F0A9FB0C2EEDD18025AD01202019 S315000142480CF056FA281C5F210CF072FA8020400304 S315000142580CF006FA80239B04636380239B02236187 S31500014268802223606363684B52011A611D618023B2 S31500014278664D1B02636702232B60654B6B60052342 S3150001428800212B6006A8142202F0BCFE002102912F S315000142980F1C2E1CE26B584B100200D495E05D4AA8 S315000142A85D4B1A60002531695C4A584B914226D804 S315000142B81A6A9006F7D55869C0210CF087FA584B47 S315000142C8029905221A6080235B00081823632328B4 S315000142D802DD071C083F0FE018280ADD0722AA435A S315000142E80121EB08914006A80A1CC15C0A43C25485 S315000142F801E00E2800DD013500210291D3E7042DE6 S3150001430859D93A4A1379002B0ED101200090291C5C S3150001431806A83A1CFEF7B2FC002805D1414800F070 S31500014328EDFA324901220A710223336006A8291CD3 S315000143380BAA05ABFEF721FD394B1A693A4B9A428E S31500014348FAD9059B0393002B2AD005250120013DA7 S31500014358FEF768FC002DF9D1EB080BAFFB5C0720D3 S31500014368A8430341181C01210840FEF75BFC039A88 S3150001437801359542F0D180231C489B02636303797A S31500014388002B0DD10093381C05991A1CFEF776FCF3 S31500014398002805D1234800F0B1FA144901220A710F S315000143A806A80021142202F02DFE0523336080237E S315000143B85B00636300273069C0210CF007FA029B92 S315000143C81B1802930423336064E7802252005A6360 S315000143D804225A63124A02233360E02013600CF068 S315000143E887F911B0F0BC01BC0047C046502A20002D S315000143F800002000B80A000000F4FFFF751412003F S3150001440890141200A914120000FCFFFF4000FAFFE5 S3150001441800050100010000A540FDFFFFFF3B00006C S315000144280000FAFF6A141200FF8F0000F0B5D34AA4 S3150001443899B00023039001200C1C0D9313700CF006 S3150001444853F90CF0F5F9CE4800F058FA03981538E7 S31500014458042800D9E4E00BF087FF03142CE3460097 S31500014468C84800F091FA0422C748211C02F0BEFD93 S31500014478C64A00231360C64A1371C64A06931370C7 S3150001448843E0C54800F03AFAC44D211C0822281C0D S3150001449802F0ACFD08200022291C00F09BFABC4A58 S315000144A800231371BE4A1370BE4A01201370069089 S315000144B82BE0BD4800F022FABC4D211C0622281C1F S315000144C802F094FD291C0022062000F083FAAF4A67 S315000144D800231360AE4A1371B14A1370B14A012120 S315000144E81370069111E0B24EB26CB248D10800F0D1 S315000144F84BFAA74D0024F16CA84808222C6002F05B S3150001450875FDA74B2C711C700694AB4C04268025AF S31500014518AD0226638027FEF721FCBF012561212014 S3150001452825600CF0E5F85F21381C0CF001F98020B4 S3150001453840030CF095F880239B0463631E20656392 S3150001454802F05AFC9D4B802252011A611F61802399 S315000145581B0263679A4B02221A609A4A9A4D5A605D S3150001456805222A601A60039B092B0CD8974800F08C S31500014578C5F9C82001210B900A910026012205924E S31500014588089604963FE0039B132B01D89048EEE763 S31500014598039A1D2A06D88F4800F0B0F95A230B93BF S315000145A80A96EAE78C483CE004232B6080239B02A9 S315000145B8236328699042FCD9814863630523036014 S315000145C8002900D0A4E00EA80021142202F01AFD49 S315000145D80A9B012000260993079005900896784BB7 S315000145E87E4A196991420BD81A6A910600D5A7E045 S315000145F873490A69F0239B019A42F0D9002EEED03D S31500014608002F00D02BE1E36B1A0200D427E1744A8C S31500014618744B1A60002E08D10398153804281DD941 S315000146287148039900F0B0F938E1594F04983B797C S3150001463801300490002BEFD100930EA8311C089A83 S31500014648FEF71CFB0028E7D1684800F057F90699E0 S31500014658002900D003E101233B71DDE70BF07AFE67 S31500014668030A11E018000EA8311C13AA0DABFEF7B8 S31500014678A9FF13E00EA8311C13AA0DABFFF778FBAF S315000146880CE00EA8311C13AA0DABFFF719F805E0CB S315000146980EA8311C13AA0DABFFF7AEFB0123584038 S315000146A80706474A059802230B9913600301CB189D S315000146B8C02253433F0E2A699A42FCD30D9900231F S315000146C84B4A8B4200D16FE7D80813AE365C0720F8 S315000146D898430641301C012630400590266304267E S315000146E82E608026B602266328699042FCD9059A6F S315000146F86663002A04D128693E4A9042FBD903E041 S3150001470828693D4A9042FBD9012262639B18D7E783 S315000147181F4E049A337901320492002B00D052E7D6 S31500014728012000905A2213A8FEF7A8FA002800D003 S3150001473849E70699002900D091E00122327142E742 S315000147485869C0210CF042F804232B6080235B00D2 S3150001475823634F2802DD1038089049E738284DDDD4 S31500014768711C07208843CA08011C01200EAB88402A S31500014778011C985C01439954023639E7B8C82000F0 S31500014788B7141200D4141200A0C82000BCC8200017 S31500014798502A2000B9C82000F5141200A4C8200028 S315000147A8C0C82000C9C8200016151200C1C82000BB S315000147B8000020003015120000F4FFFF00FCFFFF87 S315000147C84000FAFF000602000000FAFF6F1512000A S315000147D88C151200A9151200C6151200FFE000007B S315000147E8010000A540FDFFFF531512006A141200CF S315000147F87F0400007F100000FF140000282819DD3F S31500014808079A731C002A0BD107209843D908031C61 S3150001481801200EAA9840031C505C03435354B31C51 S31500014828059901220798514011405040059107907A S315000148381E1CDDE6182800DCDAE60999002902D0F3 S3150001484801390991D4E605980721B143F2080EAB5F S315000148588840011C985C014399540136C8E68023B7 S315000148685B0063630F4804236363022303602B60C1 S31500014878E0200BF03DFF04990B4800F085F80B4842 S3150001488800F03CF80A4B19780A4B183300930022BA S3150001489830230193FF20131C02F0F4FE19B0F0BC7B S315000148A801BC00474000FAFFEB151200FE15120085 S315000148B8B8C8200000002000084B094901221A60E7 S315000148C85960824002211A611960D9691142FCD0E6 S315000148D8024B0C308000C0587047C0460080FDFF6F S315000148E800201008034B012252421A60024B08228B S315000148F81A607047CCCA2000582A200013B5041C38 S3150001490802F09EFB0106090E002280200094019107 S31500014918131C400002F0B6FE13BC01BC0047154B40 S315000149281A6810B5072A07DD134A1168134C0131B5 S315000149381160002262541A6000280BD01C680E4AC6 S315000149480720001B12680D4901248440201C8C5C39 S31500014958204388541A680A4901328A4201D81A60E2 S3150001496804E0002207481A60FFF7C8FF10BC01BC23 S315000149780047C046582A2000CCCA2000CCC82000CF S31500014988FF010000071612000FB400B5A3B024AB4F S3150001499804CB02A9101C0A22019301F08DFD02A87D S315000149A8FFF7ACFF23B008BC04B0184710B5064C96 S315000149B80021221C054802F025FB0548211CFFF7AA S315000149C8E3FF10BC01BC0047409C0000142C2000EA S315000149D822161200F0B58BB0039004910592041CBF S315000149E8049B039A9E18361B002C29DD251E082DCB S315000149F800DD082507AF381C311C2A1C02F0F6FA1F S31500014A0800237B5507A95A5C203A1206120E5E2A24 S31500014A1801D92E225A540133AB42F3DB059A0A4BCC S31500014A28002A06D0009309482A1C331CFFF7ACFF5D S31500014A3804E00748291C321CFFF7A6FF083CCFE70C S31500014A480BB0F0BC01BC0047851712003C161200DA S31500014A584116120070B5061C20250024301CFFF7EC S31500014A682BFF013D2418002DF8D10F34601170BCBD S31500014A7802BC0847F0B58023364C5B0087B0236338 S31500014A883548FFF73BFF002104223448002502F090 S31500014A98B9FA00200BF02CFE0595039504952F1CF9 S31500014AA8FF262F4A2F4B310480201A60090C8001FA S31500014AB80BF03EFE142002F09FF90420FFF7CAFF0F S31500014AC8294C4443A4125F2E03D0592E02D1251C2A S31500014AD800E00594254A2648B218231212181370C5 S31500014AE81B061B0EBB4202DC049C3B1C00E0039622 S31500014AF8013E132E02D004941F1CD2E71549012644 S31500014B080E6360200BF0F4FD142002F075F9052000 S31500014B18FFF7A0FF071C1748FFF7F0FE059A2904BF S31500014B281143154A57430398230403430020009071 S31500014B3801908220BA12C00002F0A4FDE0200BF019 S31500014B48D7FD04498023B3404E634B6307B0F0BCDD S31500014B5801BC004700F4FFFF451612006C4820000F S31500014B68010000A540FDFFFF1C190200142C2000BE S31500014B78581C000077161200E880000008B50E4898 S31500014B88FFF7BCFE60200BF0B3FD142002F034F9E8 S31500014B980520FFF75FFF0949414309488912FFF7D5 S31500014BA8F3FE084BDB6B1A02ECD40748FFF7A6FEA7 S31500014BB808BC01BC0047C046A7161200E8800000E1 S31500014BC8D216120000F4FFFFD816120038B563207A S31500014BD80BF08EFD802000030BF042FD0BF07AFDF1 S31500014BE80023191C1A1C1148046CE50701D5FF247A S31500014BF84462006CC406F6D50C48046A52060120C4 S31500014C08120E044200D002430133072BEBDD084B99 S31500014C185A54084B0131994201DC0023E2E7064860 S31500014C28FFF76CFE38BC01BC0047C0460040FDFFDB S31500014C386C482000B70A0000E21612007FB5011C75 S31500014C480278437880780090C878019008790290B4 S31500014C584879039088790490C87905900248FFF746 S31500014C6893FE07B001BC00470517120000B51448AA S31500014C788DB0FFF743FE134B134A1B68934202D3C9 S31500014C88124A934201D3124805E068463021114A77 S31500014C9802F0F8F86846FFF731FE0F4A0F4B6846EF S31500014CA8302102F0EFF86846FFF728FE6846302102 S31500014CB80BF004FD6846FFF721FE0DB001BC004765 S31500014CC831171200FC01100000001000000014004A S31500014CD8511712007D171200871712007727120045 S31500014CE8F0B55A4887B0FFF709FE0120C82102F03E S31500014CF88CF80220C82102F088F80420C82102F0A5 S31500014D0884F80220C82102F080F80120C82102F0A7 S31500014D187CF80220C82102F078F80420C82102F0A4 S31500014D2874F80220C82102F070F80120C82102F0A7 S31500014D386CF80120002102F068F80024444D454F23 S31500014D4802F0E8FBFA202F60800001F0E7FF061C5D S31500014D589620400002F050F8002E2DDD661C01F069 S31500014D6873FF301C002102F050F80820002102F0E0 S31500014D784CF83948FFF7C2FD384BDB6B190201D4F1 S31500014D882F60F9E7FA20400002F036F8A50002AADA S31500014D9804AF511901207A190023FCF7F1FC082305 S31500014DA85B1969465A582E48EB59211CFFF7ECFD49 S31500014DB801F04AFF301C45E0002EBFD0661C01F009 S31500014DC843FF301C002102F020F80420002102F0E4 S31500014DD81CF82448FFF792FD204BDB6B1A0201D41D S31500014DE82F60F9E7A500082369465B195B5804AFEC S31500014DF81A1C01931C48EB59211CFFF7C5FD082114 S31500014E0849196A468858E9590022FCF72CFC1748C3 S31500014E18FFF774FDFA20800001F080FF002808DD05 S31500014E281348FFF76BFD01F00FFF07B0F0BC01BC9B S31500014E380047962001244000344001F0DDFF01F0CF S31500014E4803FF601C002101F0E0FF77E78C171200D1 S31500014E5840FDFFFF010000A5AF17120000F4FFFF98 S31500014E68C2171200D4171200FD231200DC17120014 S31500014E78E9171200F0B589B0019001F0E5FE0420AA S31500014E88FFF71AFD0199061C00200690022904D095 S31500014E986948311CFFF778FD06960520FFF70CFDDA S31500014EA8019B002200900792012B05D063480099C7 S31500014EB8FFF76AFD0098079000990022049102966F S31500014EC80392059201255E4CE36B180213D4FA206E S31500014ED8400001F091FF012D04D15A48FFF70EFD5C S31500014EE8022508E05848FFF709FD01F0ADFE09B0B3 S31500014EF8F0BC01BC0047554A554B01991A60022975 S31500014F0829D0012D0AD1069BF21AD0171218424050 S31500014F1804230A2A01DD236300E06363059904205B S31500014F2801310591FFF7C8FC331ADA179B18071CDC S31500014F3853400A2B0CDD059B4648311C3A1CFFF7EA S31500014F4823FD029BBB4200DA0297002005903E1C16 S31500014F58019901293DD0012D0CD1009B07981A1AF8 S31500014F68D117521880234A405B000A2A01DD2363C0 S31500014F7800E06363039A052001320392FFF79CFC64 S31500014F88071C0098C31BD9175B184B400A2B0CDD6D S31500014F983A1C31480099039BFFF7F6FC049ABA427A S31500014FA800DA0497002300970393022D01D0012507 S31500014FB889E7019801280ED0022807D00499079A93 S31500014FC802988B1A0699421A934204DD049A009BA9 S31500014FD803E0022DEBD1029A331CD117490F8A1827 S31500014FE8D210101C0021851AAB421FDB83421DDC3F S31500014FF81A4B5B5C80229200D80701D5226300E038 S3150001500862630122990701D5226300E06263802267 S315000150185200580701D5226300E06263042219078A S3150001502802D5226302254EE76263FBE70131801848 S315000150380829D8D1F6E7C046F11712000918120057 S3150001504800F4FFFF1F1812003C111200010000A511 S3150001505840FDFFFF34181200561812007A0B120091 S31500015068F0B54678037836021E4383781B041E433F S31500015078C37845791B061E4303792D021D4383799F S315000150881B041D43C3791B061D43DF4B89B0041C52 S315000150989E4203D1002D01D100F0D6FE301C291CF9 S315000150A8C44BC34A0BF054FB0130012800D946E230 S315000150B8D64B9E4203D1002D01D100F083FD301C51 S315000150C8291CBD4ABD4B0BF043FB0130012800D911 S315000150D8E9E0CF4B9E4203D1002D01D100F024FD1A S315000150E8301C291CB64AB74B0BF032FB013001289C S315000150F852D8301C291C042200230BF029FB01304D S31500015108012818D8301C291C032200230BF020FB88 S31500015118013001D001F01FF9331C2B4301D101F0F5 S3150001512834F9012E01D001F03AF9002D01D101F02F S3150001513812F901F034F90623FF339E4203D1002DFB S3150001514801D101F040F8301C291C9F4A9F4B0BF0F6 S31500015158FFFA0130012809D8052E01D001F01FF9FF S31500015168002D01D101F005F901F019F983235B003E S315000151789E4203D1002D01D101F0A3F80823FF3384 S315000151889E4201D001F00BF9002D01D001F007F97B S31500015198FFF76CFD01F009F99E4B9E4203D1002DE4 S315000151A801D101F07CF8301C291C894A894B0BF086 S315000151B8CFFA013001284AD8974B9E4203D1002DD8 S315000151C801D100F03CFC301C291C834A834B0BF0AF S315000151D8BFFA0130012824D8904B9E4201D001F034 S315000151E8DEF8002D01D001F0DAF8607A237A0002A0 S315000151F81843A37A1B041843E37A617C1B061843F8 S31500015208237C09021943A37C1B041943E37C627EB0 S315000152181B061943237E12021A43FCF743F901F0D0 S31500015228C4F87F4B9E4203D1002D01D100F014FC36 S315000152387C4B9E4201D001F0B2F8002D01D001F05D S31500015248AEF8794E80235B00336300F0FDFF774BA0 S315000152589E4203D1002D01D100F022FC301C291CED S315000152685F4A604B0BF074FA013001D100F08EFCF5 S3150001527883239B009E4203D1002D01D100F018FC27 S315000152886B4B9E4201D001F08AF8002D01D001F046 S3150001529886F8617A237A09028020194380010BF086 S315000152A847FA01F082F8634B9E4203D1002D01D1E2 S315000152B800F069FD301C291C4B4A4C4B0BF048FA8F S315000152C80130012800D9BDE05B4B9E4203D1002D78 S315000152D801D100F08EFC301C291C454A454B0BF0C8 S315000152E837FA013001283AD8277AA17AE27A842353 S315000152F804970691677A07929B009E4203D1002D77 S3150001530801D100F0EEFB301C291C3B4A3B4B0BF04C S315000153181FFA0130012801D800F0EEFF617C237CD9 S3150001532809021943A37C1B041943E37C627E1B060D S31500015338049E1943237E3F02120237431A43069EEF S31500015348A37E30041B0438431A43079FE37E3D06B8 S315000153581B0628431A43FCF7CBFD01F026F88523E3 S315000153689B009E4203D1002D01D100F0D0FC301CD8 S31500015378291C234A234B0BF0EBF9013001D100F02C S315000153884FFC2E4B9E4203D1002D01D100F0D8FCD3 S315000153982B4B9E4201D001F002F8002D01D000F0FE S315000153A8FEFFFCF751FC01F000F8C046C046C046B6 S315000153B813030000000000000E02000000000000B8 S315000153C802020000000000000501000000000000C4 S315000153D809020000000000000502000000000000AC S315000153E80B02000000000000170200000000000088 S315000153F81202000000000000100200000000000078 S315000154081402000000000000130300000E02000051 S315000154180202000009020000050200000302000062 S31500015428060200000702000000F4FFFF0B0200005D S315000154380D0200001702000012020000150200000A S3150001544816020000D84B9E4203D1002D01D100F06F S315000154587FFD301C291CC14BBF4A0BF079F901307D S3150001546801282FD8D14B9E4203D1002D01D100F03E S31500015478A5FC301C291CBA4ABA4B0BF069F9013054 S3150001548801D100F08BFCC0239B009E4203D1002D65 S3150001549801D100F0D6FCC64B9E4201D000F07FFF39 S315000154A8002D01D000F07BFF607A237A00021843B1 S315000154B8A37A1B041843E37A1B0618430BF0DAF8A0 S315000154C800F073FFC4239B009E4203D1002D01D136 S315000154D800F0EAFC301C291CA34AA44B0BF038F94E S315000154E80130012817D8C1239B009E4201D000F044 S315000154F856FF002D01D000F052FF607A237A000290 S315000155081843A37A1B041843E37A1B0618430BF0C6 S31500015518BFF800F04AFFA74B9E4203D1002D01D1E7 S3150001552800F0CFFCA44B9E4201D000F038FF002DBD S3150001553801D000F034FFFAF7C1FF00F036FF8023EF S31500015548DB009E4203D1002D01D100F03FFE301C45 S31500015558291C874A874B0BF0FBF80130012800D933 S3150001556848E1964B9E4203D1002D01D100F000FD82 S31500015578301C291C804A814B0BF0EAF801300128BE S3150001558869D88F4B9E4203D1002D01D100F03DFC15 S31500015598301C291C7A4A7B4B0BF0DAF801300128BA S315000155A825D8884B9E4203D1002D01D100F06FFC0E S315000155B8DC239B009E4203D1002D01D100F018FC8B S315000155C8814B9E4201D000F0EAFE002D01D000F089 S315000155D8E6FE607A237A00021843A37A1B0418436D S315000155E8E37A1B061843FBF7C5FB00F0DEFEE02352 S315000155F89B009E4203D1002D01D100F0E1FD301C34 S31500015608291C614A614B0BF0A3F8013001280FD818 S315000156186E4B9E4201D000F0C2FE002D01D000F073 S31500015628BEFE211C207A2031FEF700FF00F0BDFEE8 S31500015638674B9E4203D1002D01D100F096FC654BC4 S315000156489E4201D000F0ABFE002D01D000F0A7FE6E S31500015658614B00F0ACFD614B9E4203D1002D01D197 S3150001566800F05DFC301C291C494A4A4B0BF070F8C6 S315000156780130012839D85A4B9E4203D1002D01D158 S3150001568800F079FC301C291C434A444B0BF060F8A6 S31500015698013001D100F073FC524B9E4203D1002D1B S315000156A801D100F01BFCE2239B009E4201D000F0D1 S315000156B876FE002D01D000F072FE607A237A000290 S315000156C81843A37A1B041843E37A617C1B06184323 S315000156D8237C09021943A37C1B041943E37C1B069B S315000156E819430BF047F800F060FE3F4B9E4203D189 S315000156F8002D01D100F05AFD301C291C284A294BDE S315000157080BF026F8013001280DD8384B9E4201D0FE S3150001571800F045FE002D01D000F041FE201C0BF0E3 S315000157281BF800F042FE324B9E4203D1002D01D1F7 S3150001573800F040FDE5239B009E4201D000F02FFEBC S31500015748002D01D000F02BFE207A0BF089F800F02D S315000157582CFEC046C046C0460303000000000000F8 S3150001576819020000000000001003000000000000FC S315000157780004000000000000830300000000000090 S315000157887103000000000000800300000000000013 S3150001579889030000000000008503000000000000E6 S315000157A89203000000000000030300001902000034 S315000157B80103000011030000120300008303000027 S315000157C871030000160300001503000072030000B0 S315000157D881030000820300008C1620008903000063 S315000157E88503000087030000920300008A03000076 S315000157F893030000DA4B9E4203D1002D01D100F03C S31500015808AFFC301C291CCB4BC94A0AF0A1FF013059 S31500015818012872D8C023DB009E4203D1002D01D195 S3150001582800F012FC301C291CC34AC44B0AF090FF35 S31500015838013001281CD88423DB009E4203D1002DA8 S3150001584801D100F0C6FCA023DB009E4203D1002D46 S3150001585801D100F0CBFCC34B9E4201D000F09FFD65 S31500015868002D01D000F09BFDFFF788F900F09DFDA2 S31500015878BD4B9E4203D1002D01D100F02BFC301CFB S31500015888291CAF4AAF4B0AF063FF013001D100F082 S31500015898FEFBB64B9E4203D1002D01D100F03DFC23 S315000158A8B34B9E4201D000F07AFD002D01D000F0E5 S315000158B876FD607A237A00021843A37A1B041843FB S315000158C8E37A617C1B061843237C09021943A37CEE S315000158D81B041943E37C627E1B061943237E1202CD S315000158E81A43A37E1B041A43E37E1B061A43231C91 S315000158F820330AF043FF00F058FDC423DB009E4223 S3150001590802D1002D00D177E3301C291C8E4A8F4B1A S315000159180AF01EFF013001286FD8C223DB009E4220 S3150001592802D1002D00D187E3301C291C884A894BF6 S315000159380AF00EFF013001282CD88E4B9E4201D069 S3150001594800F02DFD002D01D000F029FD607A237AA3 S3150001595800021843A37A1B041843E37A617C1B06E9 S315000159681843237C09021943A37C1B041943E37CCE S31500015978627E1B061943237E12021A43A37E1B0469 S315000159881A43E37E1B061A43231C20330AF02CFF15 S3150001599800F00BFD784B9E4202D1002D00D111E398 S315000159A8764B9E4201D000F0FAFC002D01D000F0A2 S315000159B8F6FC607A237A00021843A37A1B0418437B S315000159C8E37A617C1B061843237C09021943A37CED S315000159D81B041943E37C627E1B061943237E1202CC S315000159E81A43A37E1B041A43E37E1B061A43231C90 S315000159F820330AF0DDFE00F0D8FC614B9E4202D14D S31500015A08002D00D108E3301C291C534A534B0AF0D8 S31500015A189FFE013000D1F7E25A4B9E4202D1002D7A S31500015A2800D101E3C623DB009E4201D000F0B7FC9A S31500015A38002D01D000F0B3FC207A534BB3E3607A12 S31500015A48237A00021843A37A1B041843E37A1B0638 S31500015A581843FBF755FC98E1607A237A000218434C S31500015A68A37A1B041843E37A617C1B061843237C3B S31500015A7809021943A37C1B041943E37C627E1B06B6 S31500015A881943237E12021A43A37E1B041A43E37E9B S31500015A981B061A43231C2033FBF740FB00F085FC49 S31500015AA8281C291C2A1C0123FBF76AFE00F07DFC31 S31500015AB8607A237A00021843A37A1B041843E37A0F S31500015AC8617C1B061843237C09021943A37C1B042A S31500015AD81943E37C1B0619430122FBF7C4FD00F0B9 S31500015AE864FC617C237C09021943A37C1B041943CA S31500015AF8E37C627E1B06049E1943237E3F02120243 S31500015B0837431A43069EA37E30041B0438431A43BF S31500015B18079FE37E3D061B0601341A432843E37FAC S31500015B28FCF7E2F800F041FCFBF7FBFB00F03DFC5B S31500015B380506000000000000000600000000000045 S31500015B480206000000000000200600000000000018 S31500015B5810060000000000002206000000000000F8 S31500015B680506000001040000020600000306000005 S31500015B7804060000060600001106000012060000D1 S31500015B8822060000230600005C0C2000EF4E0125CA S31500015B983563607A237A00021843A37A1B041843F3 S31500015BA8E37A617C1B061843237C09021943A37C0B S31500015BB81B041943E37C1B0619432A1CFBF7F8FC53 S31500015BC87563F2E3607A237A00021843A37A1B0409 S31500015BD81843E37A617C1B061843237C090219439F S31500015BE8A37C1B041943E37C1B061943FBF73AFD07 S31500015BF8DBE3607A237A00021843A37A1B0418436D S31500015C08E37A617C1B061843237C09021943A37CAA S31500015C181B041943E37C1B061943FCF74FFAC4E33B S31500015C28A21CD07F631CDB7F00021843E31CDB7FC9 S31500015C381B041843231DDB7FA21D1B06D17F1843B6 S31500015C48631DDB7F09021943E31DDB7F1B0419432F S31500015C58231C0833DB7F1B0619432332231C1278C6 S31500015C6828331B7812021A43231C2A331B781B0478 S31500015C781A43231C2B331B781B061A43231C2C336C S31500015C881D7801331B781B022B43251C2E352D78D5 S31500015C982D042B43251C2F352D782D062B43251C2A S31500015CA830352E7801352D782D023543261C3236AE S31500015CB8367836043543261C333636783606354368 S31500015CC80095251C34352E7801352D782D0235435E S31500015CD8261C3636367836043543261C373636784A S31500015CE8360635430195251C38352E7801352D782C S31500015CF82D023543261C3A3636783B342478360449 S31500015D08354324062C430294FCF7F6F94DE3607CEF S31500015D18237C00021843A37C1B041843E37C617EA1 S31500015D281B061843237E09021943A37E1B04194344 S31500015D38E37E01341B061943E27FFBF71CFF34E3BC S31500015D48607A237A00021843A37A1B041843E37A7C S31500015D58617C1B061843237C09021943A37C1B0497 S31500015D681943E37C627E1B061943237E12021A43FA S31500015D78A37E1B041A43E37E01341B061A43E37F01 S31500015D88FBF7ABFE11E3FCF703FB00950195FF203A S31500015D98291C2A1C2B1C01F075FC06E3617E237E57 S31500015DA809021943A37E1B041943E37E207C1B06C3 S31500015DB801341943E27FFCF761FDF6E2607A237A42 S31500015DC800021843A37A1B041843E37A627E1B0672 S31500015DD81843237E12021A43A37E1B041A43E37E49 S31500015DE8217C1B0601341A43E37FFCF791FDDCE2B3 S31500015DF8607A237A00021843A37A1B041843E37ACC S31500015E081B061843FEF786F8CFE2607A237A00026A S31500015E181843A37A1B041843E37A1B061843637BCA S31500015E28227B1B021343A27B12041343E27B120655 S31500015E3813431843211C431E98412031FEF7C0F92C S31500015E48B3E2FAF7CFFAB0E2037A407A00021843CE S31500015E58A37A1B041843E37A617C1B061843237C47 S31500015E6809021943A37C1B041943E37C627E1B06C2 S31500015E781943237E12021A43A37E1B041A43E37EA7 S31500015E881B061A43231C2033FAF7D2FF8DE2607AE8 S31500015E98237A00021843A37A1B041843E37A1B06E4 S31500015EA81843FAF7B9FC80E2607A237A00021843AC S31500015EB8A37A1B041843E37A1B061843FAF7C2FCB4 S31500015EC873E2607A237A00021843A37A1B04184303 S31500015ED8E37A1B061843FAF7C1FD66E2607A237A6C S31500015EE800021843A37A1B041843E37A617C1B0654 S31500015EF81843237C09021943A37C1B041943E37C39 S31500015F08627E1B061943237E12021A43A37E1B04D3 S31500015F181A43E37E1B061A430AF086FC45E2607CB7 S31500015F28237C00021843A37C1B041843E37C617A93 S31500015F381B061843237A09021943A37A1B0419433A S31500015F48E37A1B0619430AF05DFC2EE200F4FFFF13 S31500015F58607A237A00021843A37A1B041843E37A6A S31500015F681B0618430AF08AFC1FE20AF0AFFB1CE283 S31500015F78207ADD4B17E1201C0AF048FC15E2607A0D S31500015F88237A00021843A37A1B041843E37A617C37 S31500015F981B061843237C09021943A37C1B041943D6 S31500015FA8E37C627E1B061943237E12021A43A37EF3 S31500015FB81B041A43E37E1B061A43231C20330AF0EB S31500015FC809FCF2E1607A237A00021843A37A1B04DA S31500015FD81843E37A1B061843637B227B1B02134390 S31500015FE8A27B12041343E27B120613431843431E92 S31500015FF898410AF099FBD8E1231C207A217C227E5C S3150001600820330AF07DFBD0E1231C207A217C227EF5 S3150001601820330AF057FBC8E1231C207A217C227E13 S3150001602820330AF0AFFBC0E1231C207A217C227EB3 S3150001603820330AF081FBB8E1231C207A217C227ED9 S3150001604820330AF017FCB0E1607A237A000218437C S31500016058A37A1B041843E37A617C1B061843237C45 S3150001606809021943A37C1B041943E37C627E1B06C0 S315000160781943237E12021A43A37E1B041A43E37EA5 S315000160881B061A43231C20330AF036FB8DE1607A7E S31500016098237A00021843A37A1B041843E37A617C26 S315000160A81B061843237C09021943A37C1B041943C5 S315000160B8E37C627E1B061943237E12021A43A37EE2 S315000160C81B041A43E37E1B061A43231C20330AF0DA S315000160D8D5FA6AE1607A237A00021843A37A1B0487 S315000160E81843E37A617C1B061843237C090219438A S315000160F8A37C1B041943E37C627E1B061943237E9A S3150001610812021A43A37E1B041A43E37E1B061A4393 S31500016118231C20330AF06CFB47E1607A237A0002DC S315000161281843A37A1B041843E37A617C1B061843B8 S31500016138237C09021943A37C1B041943E37C627E71 S315000161481B061943237E12021A43A37E1B041A4314 S31500016158E37E1B061A43231C20330AF061FB24E164 S31500016168607A237A00021843A37A1B041843E37A58 S31500016178617C1B061843237C09021943A37C1B0473 S315000161881943E37C627E1B061943237E12021A43D6 S31500016198A37E1B041A43E37E1B061A43231C2033E2 S315000161A80AF056FB01E100F085F9FEE04F4B00F0DD S315000161B881F9FAE0211C207A20310AF049FAF4E043 S315000161C8FEF704FDF1E0FEF7F1FBEEE0FEF752FC07 S315000161D8EBE0607A237A00021843A37A1B0418437A S315000161E8E37A1B061843FEF745FEDEE0E0200AF0D7 S315000161F87FFAC82000F000FE3D4B04225A63D4E022 S31500016208049E059F021C0B1C921BBB41002B36D119 S31500016218802189008A4232D8637A217A1B020B438C S31500016228A17A09040B43E17A09060B433149EB18B4 S315000162385B1882200093291C01928000002301F03B S3150001624821FA8027BF00ED19637C227C1B021343C8 S31500016258A27C12041343E27C1206101C1843637DC8 S31500016268227D1B021343A27D12041343E27D12060B S315000162780021134305910495191EC1D102E0194B5A S31500016288174AC9E7A842BBD8009301931A1CFF20F5 S3150001629801F0F8F9164E80235B00736385E0607A96 S315000162A8237A00021843A37A1B041843E37A1B06D0 S315000162B81843104B211CC0182031302200F096FEDD S315000162C863E5607A237A00021843A37A1B0418430C S315000162D8E37A1B061843FEF7B1FC66E0C046C046E2 S315000162E80002000000000000780920006424200054 S315000162F800F4FFFF142C2000637B049E227B3F02DF S315000163081B0237431343069EA27B35041204079EDC S315000163181343E27B3D43370612063D4313430320ED S3150001632800212A1C0AF014FA01303ED0032D3CD86C S31500016338281C0AF019F80205080B8020400307E01B S315000163488020C00304E08020000301E08020800350 S315000163580AF086F929E000F017FFFA20800000F01C S315000163684BFDFA20800000F047FD124A124B1A60D5 S31500016378FEE7124B9A79D70701D501225A7100F027 S3150001638803FF0C4A0C4B1A60FEE70C4A917901226D S3150001639811400A3100930193181C1A1CFBE40848A2 S315000163A80849321C2B1CFEF7EFFA09B0F0BC01BCF8 S315000163B80047C046010000A500FDFFFFE0FF2000E1 S315000163C8761812008118120030B5314C6420A544A4 S315000163D800F012FD2F4C6278237812021A43A37833 S315000163E81B041A43E3781B061A432B4B9A4202D124 S315000163F82379012B0ED0201C00210F2200F002FE6A S31500016408502323704D2363703323A3704323E37012 S3150001641801232371A37902221343A3711F4C042379 S31500016428636380239340802563636D00012365635D S31500016438636300F0BBFE1A4A40230B21636763605E S31500016448156011642361174B80221A60164B1202DC S315000164581A600AF001F900F069FD01F05BF80028FD S3150001646809D088218900684601F066F8011E02D024 S315000164786846FEF7F5FD0D4A0D4BFA201A608000B5 S3150001648800F04CFC0028E8DDFEF72AFCE5E7C046EB S31500016498DCFDFFFFE0FF2000504D334300F4FFFF12 S315000164A800FCFFFF0000FEFF0040FDFF010000A504 S315000164B840FDFFFF1847C046F0B59DB007900F9203 S315000164C81C1C002801D1A94D07950F9B023B222BC5 S315000164D801D90A260F9600230493079D08951F1CC8 S315000164E8CA1AD619079A58428446151C654408984B S315000164F8EA5D0130252A08D066468D19EA55013725 S31500016508002A00D149E30890EAE7049D002DF3D15A S3150001651820250B95049D0E97029611950D951095BC S315000165280A950695099503950C95059501952B1CD4 S315000165382A1C411C07910178081C2338572800D9C1 S3150001654845E209F01BFF580044026A00440244026E S31500016558440244026F006400440267009C0044023E S315000165685B0061006100610061006100610061001A S3150001657861006100440244024402440244024402A6 S315000165884402440244024402080144024402440209 S3150001659844024402440244024402440244024402BC S315000165A844024402440244024402440244024402AC S315000165B8E5014402440244024402440244024402FC S315000165C8440244029E0001011402440244024402A8 S315000165D84501140250014402530144025A01EA01D9 S315000165E87A01850187018D01DE01E1014402440238 S315000165F8EF011702E70101200C9003E0002B03D1FC S3150001660830210B91079894E7009100211DE00121A3 S315000166180391F7E701200590F4E7029D252301364A S315000166282B708FE0211D2068002B0BD101900C1CCB S315000166380028E7DA05980121814305910199494224 S315000166480191DFE711900C1C19E00A208446081C09 S315000166586146414300980918079800780090302050 S31500016668404284460098844460463039092803D854 S31500016678079801300790E8E7002BE1D01191012333 S31500016688C0E76368256801951D780393002213AB5B S315000166980595019F1A7008340133381C05991D1C8C S315000166A80AF052F8324B5B5C381C2B7005990AF0DC S315000166B88DF86B1C071EF0D1331C0E9E0298321AF8 S315000166C82878D7181E1C002803D01870013D0133FD S315000166D8F3E7019D002D02D13B1C311CFDE6039A0F S315000166E801321378002B27D0013B01259D402B1C35 S315000166F8019D511C1D4216D03C23002800D02C2395 S3150001670833707B1CF01BC0187D4284465019C05C4F S31500016718D11BC918202803DD7519E8540133F1E79F S315000167286646012005E00B78202B01D90131FAE7ED S315000167383B1C1F1C0A1CD4E7331C0028CCD03E2264 S315000167481A7001360137C7E72068029D013628709D S3150001675801370434C0E76368019D2268029308344F S31500016768002D0CD11025019509E0C046921812009A S31500016778820B120001996546059F01950E1C019829 S31500016788019D8446012040428444002DA4D01178FD S31500016798BA4B0909595C317015780F2028401B5CE2 S315000167A8B11C73706046BE1C059601320028E2D002 S315000167B83B1C9D1C029805957E42CD1BED18801940 S315000167C80195C55C002DD5D08E19F5540133F0E736 S315000167D80699002902D10121069113E700210691A4 S315000167E8012109910EE701210A910BE7002A01D13E S315000167F8012207E70125002204E70A99231D00293A S3150001680818D1002D04D02268F917176051600FE0DE S31500016818002A0FD10D9A002A0CD1069D002D02D00F S315000168282268178004E00999002903D022681770A5 S315000168381C1C51E722681760FAE7019800214542B6 S31500016848454110220C95231D256803910292A0E16A S315000168580125D7E6039B002B00D08EE00F985FE059 S31500016868226804340292002A01D1854D029500203E S31500016878002B08D1029800F0E3FB07E0029D2B5C90 S31500016888002B03D0013011998842F7DB019D2B1AA1 S31500016898059D002D08D1002B06DD321CF11807E0F5 S315000168A8FF180123161C5B42391803913A1C05E0AF S315000168B88A42F5D00B9D15700132F9E7039DAA426C S315000168C80AD079428C4602990D1C6544AD5CB444E4 S315000168D861468D540132F1E72F1C059D3618002DAE S315000168E800D1F9E6002B00DCF6E6321CF0188242EC S315000168F803D00B9E16700132F9E70398161CC718C8 S31500016908EAE6012110917DE6002303930A2007E0B8 S31500016918012108E001210D9174E600230393082063 S31500016928029003E000211023039102930A99231D83 S3150001693800291AD1002D05D0072307349C43231CAF S31500016948083312E0109D231D002D0ED1002A0CD10B S315000169580D99002909D1069A002A01D0258818E13E S31500016968099D002D01D0257813E1256811E10A203A S31500016978029004E01021029101E00F9B02930A990B S31500016988002902D02568043438E0002D06D0E31D1D S31500016998072293431C1C08341D682FE0109D231DF4 S315000169A8002D01D1002A01D025680EE00D99256830 S315000169B800290AD1069A002A02D02D042D1404E0D2 S315000169C80999002901D02D062D0E1C1C16E00E9ED4 S315000169D8029D0899AA1B0E9D7342D6194A1B079D4B S315000169E8D219954207D90899029DCA18D25DEB18A2 S315000169F8DA550137EBE7012504956DE6002D00DB35 S31500016A08C3E000220123039208936D4268460022DF S31500016A1813AB4D301A7009900A950A98029909F034 S31500016A2893FE099A154B039806925B5C00280BD0D6 S31500016A381A1C613A1206120E002119209042494188 S31500016A4849015B1A1B061B0E09990A980B700299D4 S31500016A5809F0BCFE099A01320A9009920028DCD194 S31500016A68069B0C9813AA9A1A00280FD0002D0DD050 S31500016A780299082906D1013208E0C046820B1200A4 S31500016A889E181200029B102B00D102320898059914 S31500016A981218002917D10B9B302B14D00198002806 S31500016AA811D0801A019000280DDD331C31188B4254 S31500016AB803D00B9E1E700133F9E71E1C01230198B2 S31500016AC85B4201933F18089B391C002B03D02D23E9 S31500016AD83370013101360C98002812D0002D10D0E0 S31500016AE8029D082D04D1302333700131013608E0A7 S31500016AF8029D102D05D1302333707823737002312E S31500016B080236059D002D02D1019D002D02D1B44604 S31500016B18301C13E0019DAD1A0195002DF7DD331CDC S31500016B287019834203D00B9E1E700133F9E7019D4C S31500016B381E1C01235B4249190193E8E76346CD1AF6 S31500016B482D1802952F1C069D2B78061C002B05D0A7 S31500016B58069E013E037006960130EFE7059D002D5E S31500016B6800D1B9E5019D002D00D1B5E5AA1A002A83 S31500016B7800DCB1E58318984203D00B9E06700130FC S31500016B88F9E7061C02988718A6E5002003900890E5 S31500016B983CE700211C1C089138E7381C1DB0F0BCE5 S31500016BA802BC084710B5041C131C081C0A22211C28 S31500016BB8FFF782FC10BC02BC08470EB403B503AB51 S31500016BC804CB011C101C0A220193FFF775FC02B0C5 S31500016BD808BC03B01847C046072303405A1E934111 S31500016BE8C0081818704730B50022131C8B4209DA01 S31500016BF8051CDD4001242C404D1EED1AAC406240B7 S31500016C080133F3E7101C30BC02BC084710B5013A42 S31500016C1805D30C069854000A2043090AF7E710BC65 S31500016C2801BC004730B54218031C0020011C9342E1 S31500016C3807D01D78040E09020002284321430133B7 S31500016C48F5E730BC04BC1047054B01225A63802284 S31500016C5852005A63802292005A6304225A6370478B S31500016C6800F4FFFFF0B5002803D0234941438912F8 S31500016C7800E02249224E8024F36B240400201C40A4 S31500016C88844235D11F4B01225A601F4A0A231360D9 S31500016C981E4B54609360D3681B041B0CD068802577 S31500016CA80004000C2D04002C0FD1F76B2F4206D0DF S31500016CB8154BDB681B041B0C012415490EE05D18F6 S31500016CC82D042D0CA84209D10CE0F46B2C420BD0F3 S31500016CD85C182404240CA04208D001240D4D0E484A S31500016CE80560DBE7012003E0022000E001204042C5 S31500016CF8F0BC02BC0847C04680BB00001BB70000B9 S31500016D0800F4FFFF00C0FCFF00C2FCFFFFFF00000C S31500016D188D5B0000010000A540FDFFFF70B500284E S31500016D2803D0184D4543AD1200E0174D174B80228D S31500016D38D96B120400200A401E1C82421ED1144B34 S31500016D4801215960134B0A2119605A60124A9A6047 S31500016D58DA681204120CDC68F16B2404240C0802AC S31500016D6808D451190904090C8C4206D00B480C4960 S31500016D780860F0E70120404200E0012070BC02BC37 S31500016D880847C04680BB00001BB7000000F4FFFFA0 S31500016D9800C0FCFF00C2FCFFFFFF0000010000A5C8 S31500016DA840FDFFFF302358430E4B012210B55A60B0 S31500016DB80D4B0A221A6000225A600C4A9A60DA6858 S31500016DC812048012120CDC68111824040904240C1C S31500016DD8090C8C4203D0064C06490C60F3E710BC3B S31500016DE801BC004700C0FCFF00C2FCFFFFFF00001A S31500016DF8010000A540FDFFFF08B5FA239B00584393 S31500016E08FFF7D0FF08BC01BC0047F8B50126031CF3 S31500016E18064003D080201A4A8000106302251D40CF S31500016E2802D0174A0120106304241C4003D0802095 S31500016E38134A4000106308271F4002D0104B042252 S31500016E481A63002918D0081CFFF7D6FF002E03D0B5 S31500016E5880220B4B92005A63002D02D0084B012267 S31500016E685A63002C03D08022054B52005A63002F27 S31500016E7802D0034B04225A63F8BC01BC0047C04642 S31500016E8800F4FFFF70B51E1C0D1C00230370111CB6 S31500016E982A1C041C00F0DDF87278337812021A43B2 S31500016EA8B3781B041A43F3781B061A43184B9A4204 S31500016EB802D0201C174925E03379012B02D0201C6A S31500016EC815491FE07379002B02D1201C134919E0DB S31500016ED8F11D201C2A1C00F0BCF8B379002B02D145 S31500016EE8201C0F4903E0022B04D10E49201C2A1C41 S31500016EF800F0AFF80C49201C2A1C00F0AAF8311C36 S31500016F081031201C2A1C00F0A4F870BC01BC0047F3 S31500016F18504D3356A5181200C9181200EC18120064 S31500016F280E1912001719120085171200014A024B91 S31500016F381A6070471D00040020FDFFFF0E4BE0227A S31500016F481969D2010A431A610C4B1A1CC432192158 S31500016F5811600B4A0220C021186009025A600122F9 S31500016F685A61D96107490860062048601A600A60B3 S31500016F7880310A607047C04600FCFFFF0000FAFF37 S31500016F8802C046004000FAFF114BE022D20110B5BB S31500016F981A61104B1A1CC432262111600E490F4A78 S31500016FA802240C604A600422CA610D4A1C60002052 S31500016FB85A6001225A61D8610A4804600A4C446041 S31500016FC81A600A60803102600A6010BC01BC004781 S31500016FD800FCFFFF0000FAFF4000FAFF409118008D S31500016FE8058006008000FAFF0780000010B500231F S31500016FF8D41A002C03DDCC5CC4540133F8E710BC69 S3150001700802BC084710B5031C8418E41A002C02DDDB S3150001701819700133F8E710BC02BC084730B50023E4 S31500017028D41A002C08DDC55C0133CC18013C247840 S31500017038A542F5D0281B00E0002030BC02BC084759 S31500017048021C031C1978981A002901D00133F9E7A3 S31500017058704770B5041C0D1C161CFFF7F1FF0023C1 S31500017068B34206D0EA5C002A03D02118CA54013378 S31500017078F6E7E31800221A54201C70BC02BC084724 S3150001708838B5041C0D1CFFF7DBFF0023EA5C002A58 S3150001709803D02118CA540133F8E7E3181A54201CFF S315000170A838BC02BC084710B5041CFFF7C9FF231CEE S315000170B801381A1B824206DA1A78215C19702254A1 S315000170C801330138F5E710BC01BC0047F7B5C21713 S315000170D8861801900C1C56400025301C0A2109F01F S315000170E845FB631930311970301C0A2109F028FB58 S315000170F86F1C061E01D03D1CEFE7019A3B1C002AB6 S3150001710802DA2D22E254AF1C0023E355201CFFF7B7 S31500017118CAFFF7BC01BC004737B5141E082C00D9B5 S3150001712808240B19994203D00D7801310565F9E751 S31500017138056B01231D4204D1036B10252B43036301 S315000171480AE0056B9D430563036BDD07FCD4F3E792 S31500017158019D01231D4209D1036B0193019D022360 S315000171681D42F5D0026B9A4302630AE0121BD4D181 S31500017178026B1A4205D0026B9A430263036BDA0764 S31500017188FCD437BC01BC0047064B802252045A6125 S31500017198054B1B688022D9695201114200D01A6237 S315000171A87047C04600F4FFFF50002000104B37B56A S315000171B8D968802252050A43DA600E4B0E4D8022A9 S315000171C880241A60640412011A612C602C616C63B4 S315000171D8FFF7DAFF00230193019A084B9A4202D876 S315000171E8019B0133F7E72C632C6137BC01BC0047CF S315000171F820FCFFFF00FCFFFF00F4FFFFFFFF0F006D S31500017208036B102213430363026B01231A42FBD05B S31500017218026B9A430263036BDA07FCD47047036B6C S31500017228202213430363036B1A07FCD5036B282239 S3150001723893430363026B28231A42FBD17047F0B5C7 S31500017248974E3068036B85B05A0700D424E1036D65 S31500017258056D046D026DFF210C4012021443019560 S31500017268026D056D0A402D022A43056D2940056DFB S315000172782D0229432404120409040093240C120C38 S31500017288090C1B0604D4056B0427BD43056307E0F7 S31500017298056B80273D430563056B2F06FCD5F2E791 S315000172A8036B04251D40FBD1019FFF231F403F02AD S315000172B80197009F1F40019B3B437A4FBB4200D178 S315000172C8E5E017DC802149008B4200D1E2E009DCC8 S315000172D8812B00D181E0822B00D182E0802B00D066 S315000172E8D8E07AE0812149008B4200D1A6E000DB93 S315000172F8D0E0CCE088273F01BB426BD00CDCA0254F S31500017308ED00AB423FD0D025ED00AB4219D066491E S315000173188B4200D0BEE083E0644A934200D1A6E0E6 S3150001732804DC90221201934238D0B3E0604A9342BA S3150001733800D1A4E05F4A934200D0ABE05E4B5C709B S31500017348A5E080235B009C4205D11222914200D818 S315000173580A1C5A4998E080239B009C4206D1432285 S31500017368914200D80A1C554912318DE0C0239B0071 S315000173781C409C4200D08DE01A22914200D80A1C7A S315000173884E49553180E0FFF73BFF802233685200B2 S3150001739822439A60621E94415C607DE0464B1C70F4 S315000173A8FFF72EFF62426241336802218A1A5A6048 S315000173B8002C01D082252D0200225D63944201D062 S315000173C8862212029A630022944201D0872212026F S315000173D8DA6361E03849012256E069460E310D80CB S315000173E81CE069460F2344680E31134002220D80C2 S315000173F8144209D0032B07D80C3393401C58012398 S31500017408E40BA3430B803FE044680122144241D0B8 S31500017418002B3FD1036BDB0B9A430A80022233E030 S31500017428002C37D10F231A40531E1B041B0C022BA9 S3150001743830D80C3292000023135028E0002C29D1B1 S315000174480F231A40531E1B041B0C022B22D8012A98 S3150001745803D182231B02436319E0022A03D186233F S315000174681B02836313E085231B02C3630FE0026BD0 S3150001747802231A42FBD0026B9A43026307E00822F1 S31500017488914200D80A1C311DFFF746FE04E0FFF7BA S31500017498B7FE01E0FFF7C3FE05B0F0BC01BC00472B S315000174A85000200001030000020300002120000013 S315000174B8A121000021220000602A2000A70B12004A S315000174C8124B07B51B68DA690192019980225201AC S315000174D811420CD01A62012252429A6200229A6221 S315000174E8802252009A60802212021A6306E00199EC S315000174F80122114202D01A62FFF7A1FE044B187845 S31500017508431E984103B002BC0847C04650002000FC S31500017518602A200008B5FFF7D3FF002806D0054BDF S315000175281A681B7B506B1840431E984108BC02BC65 S315000175380847C04650002000F7B580231A4F9B0123 S3150001754801903C7B00930E1C0025002E26D0FFF7E8 S31500017558B7FF002822D03A68536B234219D0516BE2 S31500017568331C090CB14201D2536B1B0CF61A5B1979 S315000175789D4205D03A680199526D4A550135F7E79A S315000175883B685A6BA2435A63022C01D1402400E09E S315000175980224009B013B0093002BD6D1281C3C7387 S315000175A8FEBC02BC0847C0465000200070B5061C48 S315000175B80C1E01D100204BE0FFF782FF0028F9D00D S315000175C8231E3F2B00D93F23234D2A68E41A301C7A S315000175D8F318984203D0017801309165F9E7061C42 S315000175E82B689A6B10210A439A63002C24D0231E18 S315000175F83F2B00D93F232A68E41A301CF318984216 S3150001760803D0017801309165F9E7061C2B68996B5F S315000176180122114205D1FFF753FF0028F6D1201C9C S3150001762816E0996B914399639A6BD107FCD4D7E716 S31500017638FFF746FF0028BDD02B68996B012211423E S31500017648F6D0996B914399639A6BD107FCD4B1E74C S3150001765870BC02BC0847C0465000200010B5041C87 S31500017668FFF758FF002808D08821201C8900FFF75A S3150001767863FF034A83185842584110BC02BC0847A5 S31500017688E0FDFFFFF0B51B4CA5448F9F00256E4614 S315000176980024AC5588260135B600B542F7D10090CD S315000176A88E98019402910394049205940693079483 S315000176B8A0420CD1882168468900FFF777FF43422B S315000176C8584189239B009D44F0BC02BC0847002F02 S315000176D8F0D080233A1C9B009F4200D91A1C002334 S315000176E88E9E00ACE118F05C20310133087093429C S315000176F8F6D3DFE7DCFDFFFF0030E0E3800010E3AF S315000177080121A0E3CF2B0315CB2B03050222A0E30E S31500017718CF2B03E50010E0E3CB2B03E5400010E394 S315000177280131A0E3CF3B0115CB3B01050030E0E376 S31500017738CF2B03E5200010E3CB2B03E50121A0E3C2 S31500017748CF2B0315CB2B03050222A0E3CF2B03E591 S315000177580010E0E3CB2B03E5100010E30131A0E3B1 S31500017768CF3B0115CB3B01050030E0E3CF2B03E509 S31500017778080010E3CB2B03E50121A0E3CF2B03156A S31500017788CB2B03050222A0E3CF2B03E50010E0E390 S31500017798CB2B03E5040010E30131A0E3CF3B011530 S315000177A8CB3B01050030E0E3CF2B03E5020010E3F4 S315000177B8CB2B03E50121A0E3CF2B0315CB2B030527 S315000177C80222A0E3CF2B03E50010E0E3CB2B03E570 S315000177D8010010E30131A0E3CF3B0115CB3B0105C5 S315000177E80030E0E3CF2B03E5CB2B03E51EFF2FE1AA S315000177F8F0412DE90133A0E30040E0E3EF3B04E566 S315000178080050A0E1FF3B04E53200A0E3CF3B04E5CD S315000178180170A0E10280A0E1FD2300EB0430A0E3A2 S31500017828CF3B04E508319FE50162A0E3EB3B04E5A4 S31500017838FF3B04E59B3B04E50232A0E3CF6B04E57D S31500017848CB3B04E50131A0E3CB3B04E50732A0E3DA S31500017858EF3B04E53200A0E3CB6B04E5EC2300EB38 S31500017868CF6B04E5CC009FE50030E0E3C32B13E5BD S31500017878100012E30900001A010050E2F9FFFF1A8D S31500017888010000EA000052E32400001A022CA0E3DA S31500017898CF2B03E50420A0E3CF2B03E5220000EA62 S315000178A8000058E30540A0010C00000A033015E268 S315000178B80100000A7C209FE5160000EA072063E024 S315000178C8000052E3FAFFFFDA014083E2033023E2C4 S315000178D80300D5E787FFFFEB0430A0E1F6FFFFEAD7 S315000178E8073085E0033064E0000053E3F0FFFFDA78 S315000178F80100D4E47FFFFFEBF8FFFFEA0030E0E385 S31500017908C31B13E5020311E3DDFFFF1A0212A0E30D S31500017918CF1B03E5CB1B03E5012052E2F6FFFF2A45 S315000179280420A0E30030E0E3CB2B03E5F041BDE8FA S315000179381EFF2FE110000008A08601000030E0E3D9 S315000179481F2BA0E3FB2B03E51E2BA0E38F2B03E5DF S31500017958012BA0E38B2B03E52020A0E3EF2303E50E S31500017968000050E31F3AE0E30120A0E3FF2F03E5FF S315000179780600000A020050E10900001A2C209FE5C2 S31500017988FB2F03E528209FE5C72F03E51EFF2FE1FF S3150001799820209FE5FB2F03E51C209FE5CF2F03E55C S315000179A81EFF2FE10220A0E3FF2F03E51EFF2FE1B3 S315000179B811000B001206010111000E0082060101D9 S315000179C80030E0E31E29A0E38F2B03E50228A0E39C S315000179D8FB2B03E5012CA0E3EF2303E52B3AE0E3B8 S315000179E80229A0E3FF2F03E520209FE58710A0E3E6 S315000179F8EF2F03E5EB1F03E514109FE5E71F03E5EA S31500017A08EB1F13E5E31F03E5FF2F03E51EFF2FE138 S31500017A180101000002050000000050E31EFF2F01CE S31500017A282B3AE0E30220A0E3DF2E03E5FF0E03E590 S31500017A38FB1E03E5EF0E03E50100A0E3EB1E03E5DC S31500017A48DF0E03E51EFF2FE194C09FE5F0002DE947 S31500017A5818009CE8000054E308609C151D00000A04 S31500017A68060053E11B00002A00C0D3E561404CE241 S31500017A78FF4004E2040054E31600008A65005CE353 S31500017A88034083020250D3050130D3050140831216 S31500017A98033CA0010170D4E5053883000030A0132A S31500017AA8025084E20040D4E5033087E0043483E0E1 S31500017AB865005CE3FF0053130600008A00005CE1E1 S31500017AC8005081050100A003003082050200000A6A S31500017AD8033085E0E1FFFFEA0000A0E3F000BDE81E S31500017AE81EFF2FE1642A200037402DE98C409FE5CF S31500017AF80030A0E388009FE588109FE50D20A0E3EC S31500017B08043084E5202300EB005050E20D00001AF2 S31500017B1874309FE5003084E570309FE56500A0E389 S31500017B28083084E50D10A0E10130A0E304208DE2C0 S31500017B38043084E5C3FFFFEB000050E303009D1802 S31500017B480520A0110900001A44009FE5003090E5C0 S31500017B58010073E30600001A042090E534309FE51E S31500017B68030052E10200001A2C109FE50120A0E350 S31500017B781EFFFFEB0CD08DE23040BDE81EFF2FE162 S31500017B88642A2000160C1200002010000D20100097 S31500017B98BCC4100000201000665599AA70A4000004 S31500017BA873402DE90030A0E30040A0E10150A0E1B7 S31500017BB80030C0E50D10A0E16500A0E304208DE2C8 S31500017BC8A0FFFFEB000050E3015045E20400A0E1ED S31500017BD8B8109F052800000AB4109FE50520A0E10A S31500017BE8EC2200EB6300A0E30D10A0E104208DE276 S31500017BF894FFFFEB000050E30D00000A00609DE5CD S31500017C0804309DE5033086E0013053E5000053E377 S31500017C180700001A7C109FE50520A0E10400A0E1F9 S31500017C28DC2200EB0400A0E10610A0E10520A0E19A S31500017C38D82200EB6400A0E30D10A0E104208DE238 S31500017C4880FFFFEB000050E30D00000A00609DE590 S31500017C5804309DE5033086E0013053E5000053E327 S31500017C680700001A30109FE50400A0E10520A0E1F5 S31500017C78C82200EB0400A0E10610A0E10520A0E15E S31500017C88C42200EB08D08DE27040BDE81EFF2FE14B S31500017C982019120055191200661912006B191200E3 S31500017CA838402DE90040A0E10000A0E30150A0E121 S31500017CB821FFFFEB1F3AE0E3EF2F13E5020C12E376 S31500017CC8FBFFFF0A015485E3044085E1F34F03E511 S31500017CD83840BDE81EFF2FE10010A0E1010AA0E32C S31500017CE8EEFFFFEA0030E0E31E27A0E3EF2B03E5F2 S31500017CF8FF2B03E50227A0E3CB2B03E50226A0E32E S31500017D08CB2B03E50125A0E3CB2B03E50126A0E355 S31500017D18CB2B03E5CF0B03E51EFF2FE10000E0E3C4 S31500017D28023AA0E3EF3300E544209FE544309FE59E S31500017D380510A0E3002083E501C9A0E35F3AE0E36B S31500017D480220A0E3BF2F03E5BB2F03E5BF1F03E511 S31500017D58EFC300E520C09FE520009FE500C080E550 S31500017D687F2F03E50120A0E37B2F03E57F1F03E5B2 S31500017D781EFF2FE14000FAFFD0CA20008000FAFF5B S31500017D88D8CA2000F0472DE9D4409FE5003094E594 S31500017D980520A0E3002083E50050A0E10180A0E1D1 S31500017DA8102093E5010052E3FCFFFF8A0060A0E37F S31500017DB8080056E1003094E5180000AA107093E512 S31500017DC84A1E00EB01A005E20030E0E30228A0E329 S31500017DD800005AE1CB2B03E5001094E51E9087E2DB S31500017DE8A550A0E1967087125A708702102091E576 S31500017DF8090052E1FCFFFF3A0228A0E3CF2B03E575 S31500017E080100A0E31D1E00EB002094E5103092E569 S31500017E18070053E1FCFFFF3A016086E2E3FFFFEA50 S31500017E28101093E50020E0E30208A0E3CB0B02E57E S31500017E381E1081E2100093E5010050E1FCFFFF3AB4 S31500017E480218A0E3CF1B02E50420A0E3002083E586 S31500017E58102093E5010052E3FCFFFF8AF047BDE8D5 S31500017E681EFF2FE1D0CA2000F8402DE950409FE5BA S31500017E780070A0E10400A0E10150A0E10260A0E1C8 S31500017E88212100EB0110A0E30400A0E10120A0E1FB S31500017E980C2100EB0400A0E10710A0E1012046E255 S31500017EA8082100EB0400A0E10510A0E10820A0E3E9 S31500017EB8042100EB0400A0E11F2100EBF840BDE816 S31500017EC81EFF2FE1702A200007402DE90207A0E3D3 S31500017ED883FFFFEBB9FEFFEB4000A0E37DFFFFEB5D S31500017EE80030E0E30228A0E3CB2B03E5EF2B03E503 S31500017EF8FF2B03E588FFFFEB0030A0E300308DE59B S31500017F0818009FE50410A0E30C20A0E30530A0E3C8 S31500017F18022100EB0CD08DE204E09DE41EFF2FE167 S31500017F28702A200010402DE90238A0E30040E0E362 S31500017F38CB3B04E50A00A0E3352200EB08309FE5B8 S31500017F48BF3204E51040BDE81EFF2FE1010000A580 S31500017F58E0309FE570402DE90150A0E1001093E55E S31500017F68D4309FE510C091E5182093E5010070E330 S31500017F7802208CE004C0A0E3182083E500C081E557 S31500017F880360A0E10600001AE10F82E2AC109FE54A S31500017F98FE2000EB0040A0E1D01D00EB040060E0EC S31500017FA8000065E0B51D00EB060055E31C4096157B S31500017FB80040E003C91D00EB84109FE5183096E5E3 S31500017FC80400C1E7050D84E2121D41E20031C1E753 S31500017FD80021A0E16C009FE5052C42E223C4A0E143 S31500017FE800C0C2E723C8A0E1010080E200C0C2E7E1 S31500017FF8233CA0E1010080E2161D81E20030C2E7C0 S315000180080150C4E70040A0E30460A0E1050054E183 S31500018018050000AAB51D00EB106486E10100A0E386 S31500018028961D00EB014084E2F7FFFFEA0600A0E196 S315000180387040BDE81EFF2FE1D8CA2000702A200033 S315000180484A0200009430200015312000F8402DE93D S315000180580127A0E30030E0E3EB2B03E5200050E322 S315000180680060A0B12060A0A3FF2B03E50200A0E3F6 S31500018078821D00EB0050A0E30540A0E1060055E192 S31500018088050000AA991D00EB104584E10100A0E353 S315000180987A1D00EB015085E2F7FFFFEA9C309FE568 S315000180A8003093E5101093E594209FE5020051E115 S315000180B8FBFFFF9A0000A0E30020A0E101C0A0E3B6 S315000180C8060052E1130000AA9670A0E3920707E0A2 S315000180D80010A0E30A7D87E2105093E5070055E1F9 S315000180E80600002A0050E0E3C35B15E5015705E2E7 S315000180F8000055E1011081120500A0E1F5FFFFEA34 S31500018108151041E2260051E30C402490012082E239 S315000181188CC0A0E1E9FFFFEA28209FE5244082E51B S31500018128206082E50420A0E3002083E5102093E582 S31500018138010052E3FCFFFF8AF840BDE81EFF2FE16C S31500018148D0CA2000E9010000702A20000228A0E315 S315000181580030E0E310402DE90100A0E3CF2B03E551 S31500018168AB2100EB0000A0E33A1D00EB0710A0E3EA S315000181785500A0E302FFFFEB50409FE55500A0E341 S31500018188341D00EB0030A0E30600A0E3243084E5AB S31500018198203084E5ACFFFFEB0100A0E3371D00EBBF S315000181A82C309FE5001093E5102091E524309FE5DA S315000181B8030052E1FBFFFF9A1900A0E30610A0E3B2 S315000181C8EFFEFFEB240094E51040BDE81EFF2FE10A S315000181D8702A2000D0CA200082010000F8402DE94B S315000181E80228A0E30030E0E3CB2B03E50070A0E111 S315000181F8EF2B03E50200A0E3FF2B03E50160A0E1F5 S315000182081E1D00EB0040A0E30450A0E1060055E165 S31500018218050000AA351D00EB104584E10100A0E325 S31500018228161D00EB015085E2F7FFFFEA70309FE566 S31500018238074024E00448A0E1002093E52448A0E192 S31500018248103092E5730F53E3FCFFFF3A0030A0E3C9 S31500018258060053E10D0000AA011004E210C092E5E0 S31500018268000051E30208A0E30010E0E3CF0B01157B S31500018278CB0B010596C08CE2A440A0E1101092E553 S315000182880C0051E1FCFFFF3A013083E2EFFFFFEA00 S315000182980030E0E30228A0E3CB2B03E5F840BDE874 S315000182A81EFF2FE1D0CA2000F7432DE92C639FE575 S315000182B8205096E5070055E30640A0E12D00001A77 S315000182C8247096E5550057E314339FE51B00001A01 S315000182D8003093E5021CA0E30020E0E30440A0E39C S315000182E8CF1B02E50700A0E1004083E5D91C00EB9E S315000182F83D00A0E30610A0E3B7FFFFEB0130A0E3C2 S315000183082830C6E50030A0E31C3086E5183086E53E S31500018318243096E52C3086E5C8329FE5003093E592 S31500018328004083E5102093E5010052E3FCFFFF8A34 S31500018338102093E5460F52E3FCFFFF3AA40000EA3A S31500018348003093E53210A0E3100093E54C2000EBD2 S31500018358280051E30700009AFF0007E2BD1C00EB65 S315000183683D00A0E30610A0E39BFFFFEB1400A0E38A S31500018378272100EB960000EA2830D4E5010053E3F3 S3150001838858629FE51E00001A060055E31300001AFD S315000183980300A0E10510A0E1247096E5EBFEFFEBD2 S315000183A8190020E2000057E10C00001A0230A0E390 S315000183B82830C6E52C329FE5003093E50420A0E37A S315000183C8002083E5102093E5010052E3FCFFFF8AB4 S315000183D8102093E5C70052E3FCFFFF9A7C0000EAF0 S315000183E80030A0E32830C4E5022CA0E30030E0E326 S315000183F8CB2B03E5F0019FE5241094E5FD2000EB66 S31500018408730000EA0B0055E32900001A020053E342 S315000184183A00001A0510A0E10000E0E3CBFEFFEBED S31500018428243096E5C4919FE5030020E0C070D9E7A2 S31500018438C080A0E10520A0E10710A0E10800A0E1A5 S3150001844888FEFFEB1C3096E50050A0E1019B89E20E S315000184580980C3E7300096E5013083E2057487E1B8 S315000184681C3086E5851C00EB0708A0E10C10A0E38B S315000184782008A0E158FFFFEB68219FE5003092E54F S315000184880410A0E3001083E50250A0E1102093E553 S31500018498010052E3FCFFFF8A340094E5771C00EBE8 S315000184A8002095E5103092E5B30053E3FCFFFF9AEF S315000184B8470000EA170055E31000001A0510A0E16D S315000184C80000E0E3A1FEFFEB243096E5030020E07F S315000184D80030A0E32830C6E5022CA0E30030E0E333 S315000184E8CB2B03E5801AA0E1A025A0E1211BA0E181 S315000184F8FC009FE5FF2002E2BE2000EB340000EA03 S31500018508000053E30800001A0030A0E30A00A0E3C4 S315000185182830C4E51C3084E5BD2000EB022CA0E31D S315000185280030E0E3CB2B03E5290000EA1C2094E5A3 S3150001853800208DE50510A0E1B8009FE5242094E50B S31500018548AC2000EBB0009FE52C1094E5A92000EBC8 S31500018558A8609FE50050A0E31C3094E5030055E1AF S31500018568050000AA0510A0E194009FE50120F6E5A3 S31500018578A02000EB015085E2F6FFFFEA6C509FE56B S315000185880070E0E30560A0E11C3094E5030057E1C3 S31500018598045085E2016086E2DAFFFFAAFA34D5E5DE S315000185A8F914D5E5F824D5E50338A0E1013483E1CA S315000185B8FBC4D5E5023083E148009FE57E14D6E584 S315000185C87E25D6E50C3C83E18A2000EB017087E223 S315000185D8ECFFFFEA0CD08DE2F043BDE81EFF2FE168 S315000185E8702A2000D8CA2000D0CA200070191200AB S315000185F8142C200085191200A0191200D319120093 S3150001860813302000DE191200F419120024309FE5F8 S31500018618202093E51E0052E31EFF2FC1241093E587 S315000186280100A0E3101281E1002082E0241083E515 S31500018638202083E51EFF2FE1702A2000F8402DE94E S315000186480060A0E10400A0E30150A0E10B1C00EBCF S315000186588C309FE5001093E5102091E584309FE565 S31500018668030052E1FBFFFF9A8600A0E178409FE5EF S315000186780510A0E1010080E3C1FDFFEB0030A0E396 S315000186880C00A0E3243084E5203084E56EFEFFEB80 S315000186982470D4E50600A0E10710A0E10520A0E1B9 S315000186A8F0FDFFEB241094E5210450E10700A00139 S315000186B80900000AFF1001E20520A0E10600A0E179 S315000186C8E8FDFFEB242094E50010A0E12224A0E1B7 S315000186D818009FE5472000EB0000E0E3F840BDE8FD S315000186E81EFF2FE1D0CA200082010000702A200057 S315000186F81B1A1200060051E3F0412DE90060A0E1C2 S315000187080150A0E10240A0E14A0000DA38019FE5E4 S31500018718FD1E00EB30019FE50010A0E30120A0E358 S31500018728E81E00EB0510A0E10420A0E118019FE571 S31500018738E41E00EB0610A0E10820A0E308019FE56E S31500018748E01E00EB00019FE5FB1E00EB013084E211 S315000187581663A0E1855086E1096084E2105685E139 S315000187680200A0E3C51B00EBE0309FE5001093E58E S315000187780D4084E20380A0E1D4309FE5102091E505 S31500018788030052E10370A0E1FAFFFF9A0410A0E189 S315000187980500A0E17AFDFFEB004098E5103094E56D S315000187A8070053E1FCFFFF9A0030A0E30310A0E1A4 S315000187B8963083E20020A0E3100094E5030050E11F S315000187C80600002A0000E0E3C30B10E5010700E2FA S315000187D8010050E1012082120010A0E1F5FFFFEA35 S315000187E8152042E2260052E30900008A100094E5AA S315000187F89610A0E32A1F00EB0430A0E3003084E5BD S31500018808103094E5010053E3FCFFFF8A9B1B00EB44 S31500018818080000EA3C209FE5020053E1E3FFFF1A46 S315000188280430A0E3003084E5103094E5010053E3F9 S31500018838FCFFFF8A010000EA0000A0E3000000EA4D S315000188480000E0E3F041BDE81EFF2FE1702A200099 S31500018858D0CA200082010000E02E0000F8402DE970 S315000188680060A0E10140A0E196FDFFEB0010A0E346 S31500018878012BA0E33C019FE5EE1F00EB38019FE5C4 S31500018888841F00EB30FEFFEB0050A0E1A4FDFFEBD7 S315000188981D0055E30600000A3D0055E30900001ACC S315000188A818019FE57B1F00EB0B70A0E3013BA0E3DA S315000188B8090000EA08019FE5761F00EB0970A0E3AD S315000188C8013CA0E3040000EAF8009FE50510A0E1D9 S315000188D8C81F00EB0000E0E3340000EA010074E37E S315000188E80340A001062084E0030052E1034066A08C S315000188F815FEFFEB012CA0E30030E0E3CF2B03E5E7 S315000189080050A0E3040055E11B0000AA060085E01B S315000189180710A0E148FFFFEB010070E30300000A1E S315000189280030E0E3C32B13E5020512E30800001A41 S3150001893894009FE5571F00EB79FDFFEB0000E0E38C S31500018948013CA0E3CB3B00E5023CA0E3CB3B00E5C1 S31500018958160000EA5C209FE50200C5E76C209FE54A S31500018968015085E2BF2203E5100015E3022CA0E3BE S31500018978CF2B0315CB2B0305E1FFFFEA0030E0E31C S31500018988012CA0E3CB2B03E5022CA0E3CB2B03E5BB S3150001899863FDFFEB38009FE5961F00EB071084E2A5 S315000189A830009FE50710C1E3921F00EB0000A0E32A S315000189B8F840BDE81EFF2FE1142C2000481A1200CA S315000189C8831A12005E1A1200A91A1200C11A12009D S315000189D8010000A5D31A1200F71A1200F8402DE972 S315000189E80150A0E10060A0E136FDFFEB40019FE5E3 S315000189F8281F00EBD4FDFFEB0040A0E148FDFFEB8B S31500018A081D0054E30200000A3D0054E30900000A70 S31500018A18140000EA062085E0010C52E314019FC503 S31500018A28080000CA10019FE50510A0E1711F00EBBF S31500018A380870A0E30E0000EA062085E0010B52E368 S31500018A48030000DAF4009FE50210A0E1691F00EBBC S31500018A58350000EAE8009FE50510A0E1651F00EB77 S31500018A680A70A0E3020000EAD8009FE5611F00EB47 S31500018A782D0000EA012CA0E30030E0E3CF2B03E54B S31500018A88B1FDFFEB0200A0E3FC1A00EB0040A0E3F6 S31500018A98060054E11D0000AAAC309FE5033085E0CD S31500018AA80400D3E7051084E00720A0E110FFFFEBDF S31500018AB8000050E30900000A90009FE50410A0E1B8 S31500018AC84C1F00EB16FDFFEB0030E0E3012CA0E3A1 S31500018AD8CB2B03E5022CA0E3CB2B03E5120000EA1E S31500018AE80030E0E3C32B13E5020512E3F1FFFF0AA9 S31500018AF85C209FE5014084E2BF2203E5100014E3F0 S31500018B08022CA0E3CF2B0315CB2B0305DFFFFFEACE S31500018B180030E0E3012CA0E3CB2B03E5022CA0E314 S31500018B28CB2B03E52C009FE5DA1E00EBF840BDE8E8 S31500018B381EFF2FE1481A12001C1B1200481B1200C7 S31500018B487C1B1200A91B1200DE1B1200142C20002C S31500018B58011C1200010000A51E1C1200F7432DE995 S31500018B68000050E30150A0E10260A0E10040A0B37B S31500018B780C0000AA060054E17F0000CA5500A0E3D4 S31500018B88B41A00EB0400A0E10510A0E1EFFCFFEB2D S31500018B980410A0E10020A0E1E8019FE5151F00EB04 S31500018BA8014084E2F2FFFFEADC419FE5380084E5F3 S31500018BB80207A0E3341084E5302084E548FCFFEB86 S31500018BC87EFBFFEB8200A0E342FCFFEB0060E0E3E3 S31500018BD80137A0E30050A0E3EB3B06E5FF3B06E5C2 S31500018BE84DFCFFEB0C20A0E30400A0E10410A0E378 S31500018BF80530A0E300508DE5C81D00EB013CA0E35C S31500018C082850C4E584019FE5CF3B06E5A11E00EB8C S31500018C180530A0E10520A0E10050E0E3C31B15E5FE S31500018C28020511E34C00000AC36B15E560919FE547 S31500018C382669A0E1016006E2001099E5020056E105 S31500018C48107091E52500000A010056E32300001A79 S31500018C580520A0E3002081E5832047E2260052E3B0 S31500018C680300008A68FEFFEBCF6B05E50630A0E13D S31500018C781A0000EA472047E2260052E30800008A64 S31500018C88203094E51E0053E3FC209FD5013083D2A2 S31500018C98203082D50130A0E30020E0E3CF3B02E596 S31500018CA80E0000EA000053E30C00000A203094E5A8 S31500018CB8040053E3D0509FE50080A0E379FDFFCB84 S31500018CC8D0209FE50030E0E3248085E5208085E516 S31500018CD8BF2203E50120A0E3CB2B03E50030A0E387 S31500018CE8A90057E30020A0D3012003C2000052E3E4 S31500018CF80C00000A203094E5040053E388509FE5F0 S31500018D080080A0E367FDFFCB88209FE50030E0E304 S31500018D18248085E5208085E5BF2203E50120A0E3BF S31500018D28CB2B03E50030A0E36C209FE5020057E159 S31500018D38040000DA002099E5201092E5010811E304 S31500018D480210A0130010821548109FE50020E0E3E9 S31500018D58BF1202E50620A0E1AEFFFFEA3C009FE54F S31500018D684C1E00EB013CA0E3CB3B05E50130A0E33B S31500018D78CB3B05E5023CA0E3CB3B05E50CD08DE2F8 S31500018D88F043BDE81EFF2FE12F1C1200702A2000B8 S31500018D98411C1200D0CA2000010000A5B70B000033 S31500018DA83C11120004402DE500C8A0E12CC8A0E141 S31500018DB8022081E00140D1E404402CE0FF4004E2B6 S31500018DC8044224E0FF4004E22CC4A0E124C22CE0C2 S31500018DD804C48CE1020051E184C12CE0F4FFFF1ABE S31500018DE824209FE5020050E10CC0E0010CC8A00157 S31500018DF82CC8A00100C0C3E504309DE52CC4A0E140 S31500018E0800C0C3E504409DE41EFF2FE1FFFF0000FB S31500018E1830402DE9020052E314D04DE20150A0E1A1 S31500018E280240A0E10F0000DA0F308DE200308DE537 S31500018E38022042E20E308DE2044085E0D8FFFFEBC6 S31500018E480E20DDE5023054E5030052E10500001A63 S31500018E580F00DDE5013054E5033050E0000073E210 S31500018E680300B0E0000000EA0000A0E314D08DE2A0 S31500018E783040BDE81EFF2FE1001021E0FF2001E28E S31500018E880030A0E30810A0E302C023E001001CE3C0 S31500018E98A330A0E1011041E2213B23120118A0E110 S31500018EA8083023122118B0E1A220A0E1F5FFFF1A2C S31500018EB8200423E01EFF2FE108402DE9E000A0E38E S31500018EC884FBFFEB3D1E00EB0840BDE81EFF2FE1CA S31500018ED837402DE90050A0E10140A0E1F5FFFFEB85 S31500018EE80030A0E300308DE504308DE50510A0E1E2 S31500018EF80420A0E1FF00A0E3F71D00EB0CD08DE2F2 S31500018F083040BDE81EFF2FE1F84F2DE90050A0E1E2 S31500018F180180A0E10260A0E10040A0E3023048E23E S31500018F28030054E14300008A0430D5E7302043E2C8 S31500018F38FF2002E2010052E30700008A023084E2C0 S31500018F48044085E0D120D4E1000052E30320D5B7DF S31500018F587F2002B2023083B0340000EA060053E3F0 S31500018F682C00001A019084E20970D5E70A0057E33C S31500018F7802B084E22500001A0BA085E0C8109FE51F S31500018F880A00A0E10820A0E3FF1D00EB001050E253 S31500018F981E00001A000056E31C00000A0C20A0E37C S31500018FA80600A0E1231E00EB0720A0E10600A0E1D0 S31500018FB80A10A0E1AB1D00EB0920D5E7042082E0E9 S31500018FC8020082E20030D5E7020053E31C00001AD2 S31500018FD802C085E00330DCE5010053E31800001AFE S31500018FE80430DCE50A30C6E5053082E20310D5E730 S31500018FF8020051E30D00001A0610DCE5010051E3F9 S315000190080730DC050B30C60508308202070000EA86 S3150001901807308BE0050000EA043085E00130D3E52E S31500019028000053E30500000A024084E2033084E0AD S315000190380340A0E1B8FFFFEA0000A0E3000000EA50 S315000190480400A0E1F84FBDE81EFF2FE1230C120032 S3150001905830402DE943DF4DE20050A0E10140A0E197 S3150001906894009FE50710A0E30D20A0E1160600EB8A S31500019078060050E30100000A0000E0E31B0000EAD5 S315000190880230DDE5900053E3FAFFFF1A0330DDE510 S31500019098000053E3F7FFFF1A60009FE50510A0E300 S315000190A80D20A0E1080600EB060050E3F1FFFFDA08 S315000190B8423F8DE2002083E00C1152E5900051E316 S315000190C8ECFFFF1A0B2152E5000052E3E9FFFF1AF4 S315000190D8063040E2040053E10340A0310500A0E157 S315000190E802108DE20420A0E15E1D00EB0400A0E160 S315000190F843DF8DE23040BDE81EFF2FE12B0C120045 S31500019108320C120030402DE945DF4DE20040A0E166 S315000191180720A0E30150A0E10D00A0E184109FE51E S31500019128501D00EB0810A0E3044084E20D00A0E105 S3150001913801208DE00740CDE5E30500EB050050E38E S31500019148130000DA113E8DE2002083E00C1152E58E S31500019158900051E30E00001A0B4152E5000054E35A S315000191680B00001A090050E30A0000DA0D40DDE59C S31500019178092040E2040052E10A4040D2FF4004D2ED S315000191880500A0E10E108DE20420A0E1351D00EBDB S31500019198000000EA0040E0E30400A0E145DF8DE2BB S315000191A83040BDE81EFF2FE1370C120070402DE953 S315000191B830D04DE204408DE2070084E8A4109FE513 S315000191C80420A0E318008DE20360A0E10F50DDE55D S315000191D8241D00EB0410A0E17F30E0E30A20A0E3A0 S315000191E81F008DE21D30CDE51E20CDE51D1D00EBCE S315000191F8000055E37C30E0E32930CDE50120A0E30A S315000192087B30E0131710A0131410A0032C30CD15D2 S315000192182D20CD152A20CDE5053041E218008DE235 S3150001922810208DE22E50CD152B60CDE51C30CDE5F5 S31500019238A50500EB060050E30600001A1230DDE52D S31500019248900053E30300001A1300DDE5000090E2E5 S315000192580100A013000000EA0100A0E330D08DE26E S315000192687040BDE81EFF2FE13E0C120004E02DE51B S3150001927849DF4DE27E0500EB08008DE210108DE214 S315000192880020A0E3E10400EB010050E30100A01374 S315000192980D00001A3C009FE50510A0E3890400EBC8 S315000192A804008DE2900400EB030050E30400001A69 S315000192B80400DDE5D00050E30300A0130000A0037D S315000192C8010000EA000050E30200A00349DF8DE235 S315000192D804E09DE41EFF2FE1420C120070402DE9C7 S315000192E886DF4DE20060A0E1DFFFFFEB004050E2C0 S315000192F80100A0130410A0112700001AC8009FE559 S315000193082D0100EB0410A0E1012CA0E318008DE269 S31500019318481D00EB011CA0E318008DE24BFFFFEB93 S31500019328110050E30010A0E10200A0D31A0000DAF0 S315000193380C408DE218008DE20420A0E1F1FEFFEB5E S31500019348005050E20200001A1630DDE5000053E332 S315000193580200001A0300A0E30510A0E10E0000EACE S31500019368070094E80230A0E3464F8DE28EFFFFEB3B S315000193780510A0E1012CA0E30400A0E12D1D00EBDE S315000193880800D6E50410A0E15DFFFFEB006050E29E S31500019398030000AA0400A0E30610A0E1CBFEFFEB40 S315000193A8060000EAC3FEFFEB50008DE8FF00A0E3CC S315000193B80510A0E10620A0E10530A0E1C61C00EBDE S315000193C886DF8DE27040BDE81EFF2FE1FFFF020038 S315000193D8F7402DE90050A0E1A200A0E30270A0E148 S315000193E80160A0E10040A0E33AFAFFEB2B3AE0E383 S315000193F8DB4F03E571F9FFEB84309FE5183093E500 S31500019408013003E2033097E10030A0130130A003D5 S315000194180420A0E12BCAE0E3BF1F1CE5100011E3FD S31500019428DF1F1C15FF1001120710CD150710DD15DA S315000194382B1AE0E3BF1F11E5010011E30800000A3A S31500019448060053E103C0D5D7012082C2FFC0A0C3DD S31500019458013083D22B1AE0E3040052E3DBCF01E5A6 S31500019468030000CA0010E0E3C31B11E5020511E37E S31500019478E7FFFF1A0000A0E30CD08DE2F040BDE83B S315000194881EFF2FE1AC2A2000F84F2DE901A0A0E12B S3150001949802B0A0E10090A0E19C1C00EB0000A0E353 S315000194A8771C00EB0000A0E3751C00EB0000A0E3AD S315000194B8731C00EB0000A0E3711C00EB0100A0E3A4 S315000194C86F1C00EB0000A0E36D1C00EBA8609FE594 S315000194D80000A0E36A1C00EB0000A0E3681C00EB97 S315000194E8002096E594309FE5012082E20F10E0E323 S315000194F8002086E50210C3E700C0A0E30A005CE18C S31500019508150000AA004096E50C80D9E7015084E2CF S315000195180870A0E3010018E30F20E0130F20A00351 S31500019528017057E20520C3E7A880A0E1015085E252 S31500019538F7FFFF1A3B2CA0E13C509FE5010012E31F S31500019548094084E20F20E0130F20A003004085E5BF S315000195580420C3E701C08CE2E7FFFFEA002096E595 S315000195680010A0E3023083E00110C3E5022082E285 S31500019578002086E5F84FBDE81EFF2FE1CCCA200082 S31500019588CCC8200073402DE90240A0E10060A0E1AB S31500019598A400A0E30150A0E1CEF9FFEB000054E3DB S315000195A80300000A003094E5090053E30A30A0D30A S315000195B8003084D50030A0E3002094E5020053E191 S315000195C80F0000AA2B2AE0E3BF1F12E5010011E3F1 S315000195D80010A013DB1F0215BF2F12E501308312FD S315000195E8100012E32B2AE013DF2F121500208D1528 S315000195F880109FE500209D150020E0E3BF1202E5DB S31500019608ECFFFFEA0030A0E32B2AE0E3BF1F12E5D7 S31500019618010011E30500000A5C109FE50110D3E77C S31500019628013083E2060053E1DB1F02E5090000AAC7 S315000196382B2AE0E3BF1F12E5100011E3DF2F1215F5 S3150001964804208D152C109FE504209D150020E0E3CC S31500019658BF1202E5EBFFFFEA000055E3002094156F S31500019668023083108331A0110030851508D08DE2B0 S315000196787040BDE81EFF2FE1010000A5CCC82000FF S31500019688F8432DE90420A0E30030E0E30040A0E11F S31500019698CF2B03E5A300A0E30150A0E18DF9FFEB71 S315000196A8B0309FE55C4083E50040A0E3544083E584 S315000196B83040C3E50390A0E19C209FE50030E0E33C S315000196C8BF2203E52B2AE0E3BF3F12E5010013E3BE S315000196D80030A013DB3F0215BF3F12E5100013E36C S315000196E8F4FFFF0A643099E5030054E11600002AE5 S315000196F82B3AE0E3DF8F13E5FF0008E22002A0E141 S3150001970858709FE50FE0A0E117FF2FE1000050E335 S31500019718016084E28441A011044084120040851549 S315000197280700001A0F0008E20FE0A0E117FF2FE17A S31500019738000050E30640A001DEFFFF0A8661A0E1B2 S31500019748006085E50100A0E3000000EA0000A0E34F S31500019758F843BDE81EFF2FE1AC2A2000010000A551 S31500019768B804200004309FE56000C3E51EFF2FE121 S31500019778AC2A200008402DE920309FE520209FE5EE S31500019788000093E54410A0E32A1C00EB14309FE582 S315000197980020A0E3682083E50840BDE81EFF2FE10D S315000197A860002000B80B0000AC2A200004309FE5B9 S315000197B8040083E51EFF2FE16000200004309FE5C9 S315000197C8640083E51EFF2FE1AC2A200004309FE5E3 S315000197D80000D3E71EFF2FE1470C120004402DE5D8 S315000197E80020A0E30230A0E1010053E1050000AA30 S315000197F803C0D0E718409FE50CC0D4E71C2382E1DB S31500019808013083E2F7FFFFEA0200A0E104409DE48C S315000198181EFF2FE1470C120038402DE90050A0E148 S315000198280140A0E1ECFFFFEB0410A0E10020A0E15C S315000198380500A0E13840BDE812FFFFEA07402DE91F S315000198480120A0E1011081E20030A0E1011080E0D1 S3150001985800108DE514009FE50310A0E1023083E0B6 S315000198684FFDFFEB0CD08DE204E09DE41EFF2FE1D6 S3150001987863630000F74F2DE944519FE50180A0E19C S315000198880090A0E104208DE5A01B00EB003095E5D2 S3150001989830619FE5013083E23F20E0E30800A0E163 S315000198A80320C6E7003085E5AC1B00EB00C0A0E34A S315000198B80C40A0E10520A0E10630A0E1000054E13A S315000198C82C00000A84A1A0E1001092E508A06AE034 S315000198D80470D9E708005AE308A0A0A3016081E251 S315000198E80050A0E30A0055E10D00000A01B017E295 S315000198F80CC0A01306C0C31701C0A0130400001AA8 S3150001990800005CE33FB0E00306B0C30706B0C31727 S315000199180BC0A011A770A0E1015085E2016086E2A3 S31500019928EFFFFFEA057081E0080055E390609FE5C7 S31500019938007082E50D00001A04709DE53754A0E118 S31500019948091081E2015015E2001086E50CC0A0134A S3150001995801C0C31701C0A0130400001A00005CE38C S315000199683F50E0030150C3070150C31705C0A011BA S31500019978014084E2D0FFFFEA001092E5011081E27E S31500019988001082E500005CE33F00E0030000A0133D S315000199980100C3E7000092E50010A0E3003083E070 S315000199A8050080E20110C3E50210C3E50310C3E513 S315000199B80410C3E5000082E50CD08DE2F04FBDE846 S315000199C81EFF2FE1CCCA2000CCC820008111A0E1DE S315000199D8A7FFFFEA7F402DE90150A0E10F00CDE581 S315000199E80040A0E1491B00EB0000A0E3241B00EBAB S315000199F80000A0E3221B00EB0000A0E3201B00EB04 S31500019A080000A0E31E1B00EB0100A0E31C1B00EBFA S31500019A180000A0E31A1B00EB0000A0E3181B00EBF3 S31500019A280000A0E3161B00EBD0209FE5000092E59D S31500019A38CCC09FE5010080E20F30E0E30030CCE7BF S31500019A4801E080E20430A0E3010014E30F10E01303 S31500019A580F10A003013053E20E10CCE7A440A0E199 S31500019A6801E08EE2F7FFFF1A050080E20030CCE73D S31500019A780130A0E300108CE00040A0E30340C1E7F9 S31500019A88013083E2060053E3F9FFFF1A061080E26C S31500019A98001082E568009FE50520A0E14BFEFFEB7B S31500019AA860309FE5043093E5040053E10050A0E1DE S31500019AB80E00000A50309FE50FE0A0E113FF2FE1E9 S31500019AC80110A0E30060A0E10F008DE242FFFFEB69 S31500019AD800408DE50030A0E10110A0E30F008DE202 S31500019AE80620A0E124C09FE50FE0A0E11CFF2FE1BD S31500019AF80500A0E110D08DE27040BDE81EFF2FE100 S31500019B08CCCA2000CCC8200060002000B900200083 S31500019B18140820000010A0E3ADFFFFEAF7402DE985 S31500019B280270A0E10320A0E10060A0E10150A0E1DC S31500019B380340A0E153FEFFEB60309FE50720A0E15B S31500019B48001093E558009FE520FEFFEB54309FE592 S31500019B58043093E5000053E30070A0E10B00000A0E S31500019B6844309FE50FE0A0E113FF2FE10030A0E3A9 S31500019B780020A0E100308DE50600A0E10510A0E176 S31500019B880430A0E124C09FE50FE0A0E11CFF2FE10E S31500019B980700A0E10CD08DE2F040BDE81EFF2FE1E1 S31500019BA8CCCA2000CCC8200060002000B9002000E3 S31500019BB81408200070402DE90050A0E10140A0E101 S31500019BC80260A0E104FFFFEB0410A0E10030A0E170 S31500019BD80620A0E10500A0E17040BDE8CEFFFFEA3E S31500019BE8F04F2DE95CD04DE22C308DE578379FE5B5 S31500019BF80040A0E10250A0E10120A0E3042083E592 S31500019C080160A0E1DAFEFFEB013044E2030053E311 S31500019C1803F19F971A0000EA309C1100489C110035 S31500019C285C9C1100749C11000430A0E33030CDE532 S31500019C380030A0E33130CDE50840A0E3140000EA86 S31500019C480430A0E30040A0E33030CDE53140CDE556 S31500019C580F0000EA0430A0E33030CDE50330A0E37D S31500019C683130CDE52040A0E3090000EA0430A0E345 S31500019C783030CDE50030A0E33130CDE52840A0E312 S31500019C88030000EAE4069FE50410A0E1D91A00EBF7 S31500019C98B20100EA000055E30600A0E1C61FA0E1F3 S31500019CA81600000A7730E0E34030CDE50320A0E353 S31500019CB841308DE2C81A00EB0420A0E348308DE25A S31500019CC80500A0E1C51FA0E1C31A00EB4920DDE5A7 S31500019CD84830DDE5033022E04A20DDE5023023E0A5 S31500019CE84B20DDE5023023E04C30CDE53030DDE5B3 S31500019CF8403083E33030CDE5044084E3060000EAD2 S31500019D0840308DE20420A0E3B31A00EB3030DDE5E4 S31500019D184030C3E33030CDE5FB4004E24120DDE5C8 S31500019D284030DDE5033022E04220DDE558808DE252 S31500019D38023023E04320DDE5244068E5023023E0D4 S31500019D484430CDE50120A0E3023088E258708DE267 S31500019D5800308DE518069FE5023088E00810A0E17D S31500019D680440C4E30EFCFFEB204067E50120A0E3B5 S31500019D78023087E200308DE5F4059FE5023087E081 S31500019D880710A0E10040A0E305FCFFEBE4159FE501 S31500019D980520A0E350008DE23C408DE5311A00EB29 S31500019DA850208DE20210A0E154308DE20320A0E399 S31500019DB800308DE5B8059FE5023081E0F8FBFFEB41 S31500019DC8B4659FE54020A0E34410A0E3AC059FE5F8 S31500019DD8981A00EB30008DE20210A0E38DFEFFEB2E S31500019DE89C559FE500C096E50510A0E10C20A0E171 S31500019DF890059FE510C08DE51A1A00EB40008DE22B S31500019E080510A0E383FEFFEB00C096E50510A0E16F S31500019E180C20A0E170059FE514C08DE5111A00EB31 S31500019E280800A0E10310A0E37AFEFFEB00C096E567 S31500019E380510A0E10C20A0E150059FE518C08DE5AD S31500019E48081A00EB48008DE20510A0E371FEFFEB4E S31500019E5800C096E50510A0E10C20A0E130059FE5BC S31500019E681CC08DE5FF1900EB0700A0E10310A0E374 S31500019E7868FEFFEB00C096E50510A0E10C20A0E105 S31500019E8810059FE520C08DE5F61900EB1F1A00EBBA S31500019E980400A0E1FA1900EB0400A0E1F81900EBAF S31500019EA80400A0E1F61900EB0400A0E1F41900EBA7 S31500019EB80100A0E3F21900EB0400A0E1F01900EBA0 S31500019EC80400A0E1EE1900EB0400A0E1EC1900EB97 S31500019ED8002096E50F10E0E3023085E00F00A0E3CD S31500019EE8052082E20110C3E50200C3E50300C3E5CC S31500019EF80410C3E50240C5E70130A0E3021085E07E S31500019F080040A0E30340C1E7013083E2060053E3C2 S31500019F18F9FFFF1A062082E264149FE578049FE59B S31500019F28002086E5CF1900EB3C008DE20410A0E382 S31500019F3838FEFFEB00C096E544149FE50C20A0E12E S31500019F4858049FE524C08DE5C61900EB50008DE243 S31500019F580510A0E32FFEFFEB006096E520149FE5B0 S31500019F680620A0E138049FE528608DE5BD1900EBC0 S31500019F780207A0E35AF7FFEB90F6FFEB0120A0E3F7 S31500019F880030E0E3CF2B03E50450A0E10490A0E103 S31500019F9804B0A0E104A0A0E10470A0E10460A0E17E S31500019FA80420A0E30030E0E3CB2B03E5A100A0E306 S31500019FB848F7FFEBEC339FE5C0239FE52C2083E5AB S31500019FC84020A0E30C2083E50020A0E30020C3E5A0 S31500019FD8D4239FE50030E0E3BF2203E5C33B13E545 S31500019FE8020513E3D300000A2B3AE0E3BF2F13E57A S31500019FF8010012E30020A013DB2F0315BF3F13E571 S3150001A008100013E3F1FFFF0A2B3AE0E3DF3F13E504 S3150001A018FF0003E20C308DE52002A0E18C839FE569 S3150001A0280FE0A0E118FF2FE1000050E30C309DE599 S3150001A0380400001A0F0003E20FE0A0E118FF2FE168 S3150001A048000050E3E1FFFF0A58339FE5088093E5D6 S3150001A05814339FE5043093E5000053E30900000A31 S3150001A0680130A0E300308DE538339FE50C039FE509 S3150001A0780810A0E10020A0E3183093E530C39FE55E S3150001A0880FE0A0E11CFF2FE128239FE5D83BD2E58D S3150001A098260053E34300000A520053E34600000A30 S3150001A0A8D92BD2E5200052E30400001A930053E3AA S3150001A0B84600000A950053E30600001A490000EA23 S3150001A0C8700052E30300001A930053E34B00000AA1 S3150001A0D8950053E34F00000A300053E30C00001AC1 S3150001A0E82CC09DE51010A0E3C0008CE20020A0E37F S3150001A0F8AFFEFFEBBC329FE5BC029FE5D81BD3E55B S3150001A108D92BD3E5BB1900EB0780A0E10010A0E32A S3150001A118510000EA500053E31C00000A602043E2A4 S3150001A128FF2002E2010052E34000009AE00053E3F7 S3150001A1384400000A070057E30D00001A080058E317 S3150001A1480B00001A34029FE50410A0E3C51900EBC1 S3150001A1580410A0E30040A0E160029FE5C11900EBED S3150001A1680410A0E10020A0E154029FE5A11900EB2B S3150001A178060000EA4C029FE50810A0E19D1900EBD4 S3150001A1880800A0E1F4119FE50020A0E3841900EB83 S3150001A1980040A0E30450A0E10480A0E10410A0E17E S3150001A1A8E0619FE52C0000EA10109DE50240A0E35E S3150001A1B830508DE20180A0E3F8FFFFEA10109DE51B S3150001A1C80240A0E330508DE20680A0E3F3FFFFEAE8 S3150001A1D814109DE50540A0E340508DE20280A0E3FE S3150001A1E8A4619FE51C0000EA1C109DE50540A0E35B S3150001A1F848508DE21480A0E394619FE5160000EAB9 S3150001A2080340A0E318109DE534508DE20480A0E1D7 S3150001A21878619FE5100000EA20109DE50340A0E360 S3150001A22838508DE21E80A0E368619FE50A0000EAC6 S3150001A23824109DE50440A0E33C508DE20780A0E38D S3150001A24858619FE5040000EA28109DE550619FE5E5 S3150001A2580540A0E350508DE24680A0E3052057E271 S3150001A268003072E20230B3E0060058E305005703F6 S3150001A27801A08A02060058E30030A0030130031248 S3150001A288000053E301B08B12FA0F59E338019F0519 S3150001A2982900000A000051E3019089E2060000DA6C S3150001A2A810319FE5D82BD3E5523052E2002073E2F4 S3150001A2B80600A0E10320B2E044FCFFEBA8309FE5CD S3150001A2C8043093E5000053E31400000A000055E347 S3150001A2D80C00000A0410A0E10500A0E13EFDFFEB19 S3150001A2E80410A0E1561900EB0020A0E30030A0E11C S3150001A2F800208DE50500A0E10410A0E1B0C09FE5AE S3150001A3080FE0A0E11CFF2FE198309FE5682093E557 S3150001A318B8309FE5030052E1B4009FC5060000CAA4 S3150001A32858009FE54410A0E34020A0E3411900EB43 S3150001A3380870A0E119FFFFEA98009FE5D51800EB20 S3150001A3480B20A0E10930A0E18C009FE50A10A0E1ED S3150001A358281900EB0120A0E30030E0E3CB2B03E54D S3150001A3685CD08DE2F04FBDE81EFF2FE160002000B2 S3150001A378191D120063630000470D1200CCCA2000A4 S3150001A388EC372000CCC820006C4820001249200078 S3150001A398B8492000883020005E4A2000044B20007E S3150001A3A8AA4B2000504C2000AC2A2000010000A531 S3150001A3B8F400200014082000142C2000341D12007B S3150001A3C8F0372000541D1200751D1200981D120049 S3150001A3D8B80B00006A141200AF1D1200FD2312000B S3150001A3E870402DE90050A0E10140A0E1FAFCFFEB25 S3150001A3F80410A0E10030A0E10020A0E30500A0E1DF S3150001A4087040BDE8C4FDFFEA0230A0E10020A0E3E8 S3150001A418C1FDFFEAF0402DE914D04DE200C0A0E3EA S3150001A42810408DE204C024E50060A0E10170A0E1BE S3150001A4380250A0E108C08DE50DFDFFEB6C309FE5EC S3150001A44808208DE2000093E50410A0E14CFCFFEB27 S3150001A4585C309FE56030D3E5000053E30030E0133C S3150001A4680120A013CF2B031548309FE5043093E54F S3150001A478000053E30A00000A0700A0E1B71800EB41 S3150001A4880130A0E30010A0E100308DE50600A0E14F S3150001A4980020A0E30530A0E11CC09FE50FE0A0E184 S3150001A4A81CFF2FE114D08DE2F040BDE81EFF2FE11D S3150001A4B8CCCA2000AC2A2000600020001408200025 S3150001A4C88111A0E1D2FFFFEA38402DE90050A0E151 S3150001A4D80140A0E1C0FCFFEB8411A0E10020A0E14E S3150001A4E80500A0E13840BDE8C9FFFFEA30402DE983 S3150001A4F814D04DE20040A0E310108DE2044021E59E S3150001A5080050A0E15DFCFFEB040050E10100001AD8 S3150001A5180000A0E3110000EA4C309FE5043093E502 S3150001A528000053E30800000A40309FE500408DE52E S3150001A5380500A0E1541093E50C209DE5403093E514 S3150001A5482CC09FE50FE0A0E11CFF2FE10C309DE533 S3150001A558000053E3EDFFFF0A10309FE5540093E531 S3150001A56814D08DE23040BDE81EFF2FE160002000C7 S3150001A578AC2A200014082000F0402DE914D04DE241 S3150001A5880050A0E30160A0E110108DE2045021E51E S3150001A5980070A0E139FCFFEB050050E10100001A4B S3150001A5A80000A0E3130000EA54309FE5043093E568 S3150001A5B8000053E34C409FE50700000A00508DE573 S3150001A5C80700A0E1541094E50C209DE5403094E580 S3150001A5D834C09FE50FE0A0E11CFF2FE1403094E570 S3150001A5E8003086E50C309DE5000053E3EBFFFF0ADA S3150001A5F810309FE5540093E514D08DE2F040BDE894 S3150001A6081EFF2FE160002000AC2A2000140820005C S3150001A618F0472DE920D04DE25230A0E30090A0E1A9 S3150001A6280140A0E102A0A0E128129FE50220A0E3D3 S3150001A63808008DE20430CDE50A1800EB18129FE5F3 S3150001A6480920A0E314008DE2061800EB0C129FE521 S3150001A6580420A0E30C008DE2021800EB04008DE251 S3150001A6680710A0E30020A0E369FFFFEBF0019FE5D7 S3150001A6789DFFFFEB000050E30100001A0000A0E374 S3150001A688710000EA000054E30800000AD0119FE5B2 S3150001A6980220A0E30B0084E2F21700EB0010A0E30E S3150001A6A80A10C4E50400A0E10A20A0E3611800EB42 S3150001A6B8000059E30900A0110010A0130A20A013F5 S3150001A6C85C18001B9380A0E30070A0E30450A0E38C S3150001A6D8043015E24100000A08008DE20210A0E3E9 S3150001A6E80880CDE51480CDE576FFFFEB70019FE587 S3150001A6F87DFFFFEB000050E3DFFFFF0A10008DE24C S3150001A7085C119FE50420A0E3D61700EB00005AE38D S3150001A7180300000A10008DE20410A0E3511800EBB3 S3150001A72800008AE50520A0E334119FE516008DE2B5 S3150001A738CC1700EB14008DE20710A0E33EFCFFEBFB S3150001A74814008DE20910A0E35EFFFFEB10019FE5FF S3150001A75865FFFFEB000050E3C7FFFF0A04319FE5E1 S3150001A76804219FE50350D2E7040015E30800000A17 S3150001A7781030DDE5880053E30500001A10008DE26C S3150001A788011080E20320A0E3B61700EB0360A0E303 S3150001A798000000EA0460A0E3000059E307008910FD S3150001A7A810108D120620A011AE17001B000054E3ED S3150001A7B80600000A0620A0E1070084E010108DE2D9 S3150001A7C8A81700EB0A30D4E5036086E00A60C4E501 S3150001A7D8028088E2037087E2FF8008E2BBFFFFEA96 S3150001A7E8000054E30D50C4150E30C415200015E3BE S3150001A7F80200A0031400000A0C008DE20210A0E377 S3150001A8080DFCFFEB0C008DE20410A0E32DFFFFEB1E S3150001A8184C009FE534FFFFEB005050E296FFFF0A1C S3150001A828000054E30400000A0F0084E230109FE59B S3150001A838012CA0E38B1700EB0E50C4E52C309FE5E5 S3150001A8480020A0E37020C3E50100A0E320D08DE23B S3150001A858F047BDE81EFF2FE14C0D12004E0D120008 S3150001A868570D12006C482000581C0000142C2000BB S3150001A878AC2A200038402DE90040E0E30450A0E36B S3150001A8884EF4FFEBCB5B04E5E000A0E311F5FFEB2B S3150001A8983200A0E3DE1700EB0207A0E310F5FFEB99 S3150001A8A8CF5B04E5A400A0E30AF5FFEB3200A0E3C1 S3150001A8B8D71700EB0C309FE5022BA0E3642083E554 S3150001A8C83840BDE81EFF2FE1AC2A2000F0482DE9EB S3150001A8D80250A0E1A8609FE50B2081E20720C2E3B0 S3150001A8E814B08DE202D04DE07020D6E50A2082E34D S3150001A8F80030A0E10140A0E10020CDE50020A0E361 S3150001A908047081E20120CDE50310A0E10420A0E155 S3150001A91802008DE2531700EB0D00A0E1021084E25C S3150001A928C5FBFFEB0D00A0E10710A0E1E5FEFFEB7B S3150001A9380500A0E1ECFEFFEB000050E30D00000A64 S3150001A948030050E30B00009A0030D5E5C00013E37D S3150001A9580200000AD02003E2800052E30500001A33 S3150001A9687020D6E5013003E2030052E110309F055D S3150001A978012022027020C30514D04BE2F048BDE83D S3150001A9881EFF2FE1AC2A2000F0472DE90830D0E55B S3150001A9980980D0E5088483E10A30D0E5038888E197 S3150001A9A80B30D0E51160D0E5038C88E11030D0E595 S3150001A9B8066483E11230D0E5036886E11330D0E5F9 S3150001A9C882DF4DE2036C86E10040A0E1207080E25F S3150001A9D867FBFFEB48219FE5FF5008E20130A0E342 S3150001A9E8108018E2043082E538219F156030C215BF S3150001A9F8010015E30690A0E10D00000A9CFFFFEB9C S3150001AA0808A08DE20000A0E30A10A0E10020A0E161 S3150001AA18FEFEFFEB10319FE50020A0E30010A0E148 S3150001AA2804308DE500A08DE5FF00A0E30230A0E12A S3150001AA38291700EB400015E30800000A1830D4E591 S3150001AA481920D4E5022483E11A30D4E5032882E1EA S3150001AA581B30D4E5032C82E1C8309FE5642083E5E9 S3150001AA68040015E30C00000A08408DE20610A0E177 S3150001AA780420A0E10700A0E193FFFFEB023CA0E35D S3150001AA880020A0E30010A0E104308DE500408DE52B S3150001AA98FF00A0E30230A0E10F1700EB080015E361 S3150001AAA81300000A200015E30300000A0700A0E1CD S3150001AAB80610A0E160FBFFEB029086E20910A0E117 S3150001AAC80700A0E108408DE27EFEFFEB0400A0E14D S3150001AAD885FEFFEB023CA0E30020A0E30010A0E105 S3150001AAE804308DE500408DE5FF00A0E30230A0E1CA S3150001AAF8F91600EB000058E328309F150020A01333 S3150001AB086020C315020015E30200001AE000A0E365 S3150001AB1870F4FFEB291700EB82DF8DE2F047BDE801 S3150001AB281EFF2FE160002000AC2A20000F01000063 S3150001AB3870402DE90240A0E10060A0E10150A0E1CA S3150001AB4825FBFFEB8511A0E10020A0E10600A0E1AD S3150001AB5847FBFFEB000054E30030A0130310A011DC S3150001AB681A00000A0328A0E1220854E10120A08363 S3150001AB781213818102308380FF100182F8FFFF8A58 S3150001AB8850309FE5002093E54CC09FE5012082E205 S3150001AB98002083E50030A0E30230CCE70300A0E102 S3150001ABA8020053E1090000AA086064E21006A0E168 S3150001ABB80350DCE7550480E10300CCE7013083E26A S3150001ABC80338A0E12338A0E1010005E0F3FFFFEA1D S3150001ABD87040BDE81EFF2FE1CCCA2000CCC820007A S3150001ABE8010050E1F0412DE90070A0E10180A0E1EA S3150001ABF80000A0031700000A0160A0E10750A0E1C8 S3150001AC080140A0E3020914E31100001A0500A0E1BE S3150001AC180110A0E3791200EB080050E10050A0E111 S3150001AC280400A0010B00000A0600A0E10110A0E340 S3150001AC38721200EB070050E10060A0E10000640217 S3150001AC480400000A014084E20448A0E12448A0E186 S3150001AC58EBFFFFEA04009FE5F041BDE81EFF2FE187 S3150001AC686179FEFFF04F2DE96CD04DE200B0A0E10D S3150001AC7800159FE518008DE20420A0E3791600EB84 S3150001AC880050A0E3F0449FE5F0349FE505005BE141 S3150001AC9828508DE52C508DE5685084E5045083E5F0 S3150001ACA830508DE534508DE538508DE53C508DE5B5 S3150001ACB81C00000A981600EB7150C4E5ECFEFFEB88 S3150001ACC8A100A0E303F4FFEBB4549FE50FE0A0E174 S3150001ACD815FF2FE12008A0E10008A0E1010850E3D3 S3150001ACE8F8FFFF1A0030E0E3C33B13E5020913E35B S3150001ACF8FBFFFF1A0030E0E3C33B13E5020913E348 S3150001AD08FBFFFF0A0FE0A0E115FF2FE10060A0E3BA S3150001AD180138A0E3740084E5783084E57C6084E535 S3150001AD2820608DE5050000EA7130D4E5013083E243 S3150001AD38FF3003E27130C4E52B30CDE58060D4E500 S3150001AD480030E0E30190A0E3012CA0E3CF9B03E5EB S3150001AD580070A0E3CB2B03E5022CA0E3CB2B03E584 S3150001AD6814708DE510908DE50780A0E107A0A0E19C S3150001AD780750A0E10C249FE50030E0E3BF2203E57C S3150001AD88C32B13E5022512E2AE00000A022CA0E34A S3150001AD98CF2B03E540008DE20010A0E31C208DE2D5 S3150001ADA81AFEFFEB000050E3EE00000AA400A0E340 S3150001ADB8C8F3FFEB782094E502208AE018008DE2BB S3150001ADC80410A0E3072002E258FFFFEB783094E570 S3150001ADD803C08AE0743094E507C0CCE303C08CE075 S3150001ADE874C084E598939FE50FE0A0E119FF2FE170 S3150001ADF8742094E5020050E17C139FE509A0A0E1C7 S3150001AE08783091850730C383022083807420818539 S3150001AE18F3FFFF8A0FE0A0E11AFF2FE1742094E502 S3150001AE28020050E150939FE5F9FFFF3A0020A0E3A5 S3150001AE3824208DE54C208DE54C239FE524108DE2D9 S3150001AE48000092E54C208DE2CDF9FFEB3C039FE52E S3150001AE58A5FDFFEB000050E300A0A001C100000A18 S3150001AE6820C09DE524039FE50410A0E30CC08DE5F1 S3150001AE787C1600EB0620A0E120008DE54010A0E33A S3150001AE8828008DE262FDFFEB0CC09DE500005CE346 S3150001AE980020A00301200B12000052E30F00000A54 S3150001AEA87CA099E500005AE30C00001A0C00A0E109 S3150001AEB820109DE549FFFFEB000050E320209D058A S3150001AEC87C2089050500000AC4129FE5010050E1AE S3150001AED8781099150100601078008915A10000EA1B S3150001AEE820109DE57C0094E5000051E188229FE54C S3150001AEF82300000A000050E32100000A0C208DE51A S3150001AF0836FFFFEB8C329FE500A060E203005AE1B1 S3150001AF1800E0A0E10C209DE500A0A0039100000A35 S3150001AF2814109DE501005AE10080A0130400001ADF S3150001AF38018088E20888A0E12888A0E1020058E398 S3150001AF480600008A50029FE50710A0E10E20A0E145 S3150001AF580830A0E1271600EB14A08DE5810000EA70 S3150001AF68783092E514109DE5033081E0783082E56A S3150001AF7828029FE50710A0E10E20A0E11D1600EBAF S3150001AF88780000EA04029FE557FDFFEB000050E355 S3150001AF981C00000A10209DE5000055E30730060253 S3150001AFA88030C405012032E210208DE50030E0E34F S3150001AFB8012CA0E368108DE2CF2B0315CB2B0305DB S3150001AFC8053081E0D8219FE5D8119FE50220D1E718 S3150001AFD8070055E3052022E2386043E5302043E5C2 S3150001AFE81A00000A2B30DDE5015085E2075005E21B S3150001AFF81F3003E2853283E12B30CDE58060D4E54D S3150001B00808A0A0E30D0000EA000055E300C0A01364 S3150001B01801C00B0200005CE3F86006028030D4052B S3150001B02808608602016086120050A011036086013D S3150001B038FF60061205A0A011FF6006020CA0A00180 S3150001B0480080A0E3470000EA0280A0E1000000EAD0 S3150001B0580180A0E320008DE20410A0E3DEF9FFEBF6 S3150001B0680140A0E30030A0E13C719FE530608DE22C S3150001B0780020A0E300408DE520008DE20410A0E346 S3150001B0880FE0A0E117FF2FE10600A0E10810A0E3F9 S3150001B098D1F9FFEB38508DE20030A0E10020A0E3A2 S3150001B0A800408DE50600A0E10810A0E30FE0A0E14D S3150001B0B817FF2FE10500A0E10810A0E3C6F9FFEB91 S3150001B0C800408DE50030A0E10810A0E30500A0E1ED S3150001B0D80020A0E30FE0A0E117FF2FE12B30DDE50B S3150001B0E81F3003E22B30CDE540309DE54C708DE2F3 S3150001B0F80420A0E34C308DE520009DE5023087E071 S3150001B1080010A0E3B41500EB030096E854308DE275 S3150001B118030083E8030095E85C308DE2030083E8C9 S3150001B12828309DE50020A0E364308DE51C30A0E3BE S3150001B1380810A0E104308DE500708DE50230A0E12C S3150001B148FF00A0E3641500EBE000A0E3E1F2FFEBEA S3150001B1589A1500EB24309FE5044083E56CD08DE217 S3150001B168F04FBDE81EFF2FE1017087E20778A0E1E5 S3150001B1782778A0E1FEFEFFEA5B0D1200AC2A20004B S3150001B18860002000D5002000010000A5CCCA2000DF S3150001B1986C4820006179FEFF9F860100BC1D1200E4 S3150001B1A81A1E1200581C0000142C20001408200036 S3150001B1B8F04F2DE90060A0E344D04DE22C608DE507 S3150001B1C830608DE534608DE52A60CDE538608DE522 S3150001B1D83C608DE5350300EB0040A0E1300300EB50 S3150001B1E8BC5B9FE5BC3B9FE51C008DE50170A0E3B8 S3150001B1F8080085E20410A0E3686083E5047085E52C S3150001B208981500EB0710A0E324008DE500A0A0E146 S3150001B2180720A0E10400A0E1810500EB0030D4E598 S3150001B228063053E00130A013060053E114308DE5D2 S3150001B2380D00001A0420A0E30310A0E10E0085E228 S3150001B2480C20C5E5760500EB0F20D5E50E30D5E5D2 S3150001B258033022E01020D5E5023023E01120D5E5A0 S3150001B268023023E01230C5E51B0000EA4430A0E3B2 S3150001B2780C30C5E50F0085E27730E0E30610A0E162 S3150001B2880320A0E30E30C5E5650500EB0F20D5E5E3 S3150001B2980E30D5E5033022E01020D5E5023023E053 S3150001B2A81120D5E5130085E2023023E00310A0E35F S3150001B2B80420A0E31230C5E5590500EB1420D5E5B5 S3150001B2C81330D5E5033022E01520D5E5023023E019 S3150001B2D81620D5E5023023E01730C5E5F31400EB57 S3150001B2E80207A0E37EF2FFEBB4F1FFEBA100A0E3B6 S3150001B2F878F2FFEBC800A0E3451500EBA83A9FE5F5 S3150001B308003093E5000053E3A00A9FC514109DC5BC S3150001B318381500CB0080A0E3943A9FE50FE0A0E141 S3150001B32813FF2FE120808DE518808DE5FF90A0E3BE S3150001B3380870A0E108B0A0E10850A0E1743A9FE5C1 S3150001B3480060E0E3BF3206E5C33B16E5020513E3F9 S3150001B3582100000A000055E33A00001A0500A0E39F S3150001B368CF1400EB503A9FE5930000E04035A0E189 S3150001B378FA0E53E3F0FFFFDA013CA0E3CB3B06E507 S3150001B3880150A0E3023CA0E3CB3B06E5CF5B06E513 S3150001B3982C0000EA272AE0E3E30F12E5200010E378 S3150001B3A83F00001A2B2AE0E3BF0F12E5010010E364 S3150001B3B80000A013DB0F0215BF2F12E5100012E3E0 S3150001B3C85200001AEC099FE50020E0E3BF0202E5FE S3150001B3D8C32B12E5020512E3EDFFFF1AC0499FE5EB S3150001B3E8E000A0E33BF2FFEBF41400EB4410A0E30A S3150001B3F80420A0E3080084E20E1500EB0130A0E367 S3150001B4080020A0E300308DE5080084E20230A0E1C7 S3150001B4180410A0E3A4C99FE50FE0A0E11CFF2FE1FA S3150001B42884399FE5003093E5000053E3590200DAB9 S3150001B43870399FE588099FE5041094E5682093E52E S3150001B448EC1400EB530200EA0420A0E30030E0E329 S3150001B458CB2B03E5A100A0E31EF2FFEB273AE0E3BD S3150001B4680120A0E3FF2F03E558299FE5FB2F03E5FC S3150001B4782020A0E3EF2F03E50220A0E3FF2F03E539 S3150001B48820299FE54030A0E30C3082E50030A0E397 S3150001B4982C4082E50030C2E50310A0E10360A0E17B S3150001B4A8C7FFFFEABB0F12E5011081E2003083E016 S3150001B4B81F0051E30200A0E3FF0F02E5B8FFFFDA20 S3150001B4C80300A0E1F61300EBEC389FE5930000E0DA S3150001B4D8FA0950E30030A0A30310A0A10360A0A1BC S3150001B4E8AFFFFFAAE0389FE50FE0A0E113FF2FE1C8 S3150001B4F8000056E30060A001000066E0320050E358 S3150001B5083200008A0030A0E30310A0E1A4FFFFEA9D S3150001B5182B2AE0E3DF2F12E5FF2002E22B20CDE5FF S3150001B528A8289FE52B00DDE50C108DE510208DE59B S3150001B53808308DE52002A0E10FE0A0E112FF2FE11E S3150001B5480C108DE2000050E3060091E808309DE5F5 S3150001B5580900001A2B00DDE50C108DE508308DE594 S3150001B5680F0000E20FE0A0E112FF2FE1000050E317 S3150001B5780C109DE508309DE591FFFF0A20289FE5FF S3150001B588042092E51C389FE5000052E3086093E524 S3150001B5981100000A08308DE514289FE50FE0A0E1A7 S3150001B5A812FF2FE10110A0E300108DE508309DE59B S3150001B5B80020A0E10610A0E10400A0E1183093E5FF S3150001B5C8F8C79FE50FE0A0E11CFF2FE1020000EAA2 S3150001B5D87A1400EB0050A0E357FFFFEA040056E394 S3150001B5E81E00000A010056E31C00001A0030D4E5CB S3150001B5F8260053E30200001A0B0055E30200001A65 S3150001B6084DFFFFEA520053E31400001AB8379FE5CD S3150001B6180FE0A0E113FF2FE10020D4E5523052E2FA S3150001B628002073E20320B2E018008DE50210A0E3C2 S3150001B6389C079FE55EF9FFEB0030E0E3012CA0E3F0 S3150001B648CB2B03E5022CA0E3CB2B03E538008DE2D7 S3150001B658630F00EBFF90A0E30250A0E336FFFFEA79 S3150001B668022045E20030E0E3080052E302F19F9729 S3150001B67831FFFFEAA0B6110078B711004CB81100E6 S3150001B68800B9110044B91100A0BA1100DCBA1100C1 S3150001B69824BB110070BB1100020056E30700001A13 S3150001B6A80030D4E5930053E323FFFF1A0130D4E5B4 S3150001B6B8200053E31C079F051FFFFF1A360000EA07 S3150001B6C8090056E31CFFFF1A0030D4E5930053E343 S3150001B6D819FFFF1A0130D4E5700053E316FFFF1A6C S3150001B6E8020084E2EC169FE50420A0E3261400EB91 S3150001B6F8000050E310FFFF1A14209DE5000052E3F5 S3150001B708D4069F05D4069F150310A0E333FBFFEB70 S3150001B718C0069FE50410A0E3521400EB14309DE522 S3150001B728000053E30080A0E10350A01302FFFF1AB3 S3150001B7380030E0E3012CA0E3CF2B03E568369FE553 S3150001B748003093E5030053E3010000CA0650A0E365 S3150001B758F9FEFFEA70369FE50FE0A0E113FF2FE13E S3150001B76818209DE5001062E074069FE52F0000EAA7 S3150001B778000056E3F0FEFF0A020056E30900001A2C S3150001B7880030D4E5950053E3EBFEFF1A0130D4E50A S3150001B798200053E3E8FEFF1A48069FE50510A0E3DB S3150001B7A80EFBFFEBE4FEFFEA090056E32100001A4F S3150001B7B80030D4E5950053E3DFFEFF1A0130D4E5E6 S3150001B7C8700053E3DCFEFF1A020084E214169FE5BB S3150001B7D80420A0E3EC1300EB000050E3D6FEFF1AA9 S3150001B7E80310A0E3F0059FE5FCFAFFEBF4059FE5DE S3150001B7F80410A0E31B1400EB0030E0E3012CA0E3E6 S3150001B808CF2B03E5A0359FE5003093E5030053E30D S3150001B8180080A0E1CCFFFFDAAC359FE50FE0A0E19F S3150001B82813FF2FE118309DE5001063E0B8059FE589 S3150001B838F01300EBC4FFFFEA040056E36B00000AAD S3150001B848BDFEFFEA080056E3D900001A040084E2A7 S3150001B8580410A0E3031400EB0010A0E30120A0E10B S3150001B8680050A0E138008DE2510F00EB4010A0E333 S3150001B878055020E00A00A0E1600F00EB000055E149 S3150001B8880B00000A20359FE5003093E5030053E3DA S3150001B898C60000DA0A00A0E14010A0E3570F00EB4A S3150001B8A80510A0E10020A0E140059FE5D11300EBBA S3150001B8B8BE0000EA6010A0E30A00A0E14F0F00EB0A S3150001B8C80010A0E30120A0E10050A0E138008DE2BC S3150001B8D8370F00EB0010A0E3050020E00420A0E3E9 S3150001B8E80C359FE530008DE5BB1300EB00059FE5A0 S3150001B8F80410A0E3B9FAFFEB0030E0E3022CA0E361 S3150001B908CF2B03E5A0349FE5003093E5030053E30D S3150001B9188DFFFFDAB0349FE50FE0A0E113FF2FE1B9 S3150001B92820209DE50710A0E1003062E0C4049FE5F0 S3150001B9380920A0E1AF1300EB83FFFFEA000056E3FD S3150001B9487DFEFF0AFF0059E32A00001A040056E3A8 S3150001B9589D00001A0030D4E5603043E2FF3003E26F S3150001B968010053E3A000008A5C349FE50FE0A0E1E3 S3150001B97813FF2FE10090D4E50170D4E5609049E208 S3150001B9882771A0E1FF9009E220008DE50910A0E1E9 S3150001B9980700A0E1170400EB0130A0E10020A0E1B7 S3150001B9A838008DE2710E00EB0A1028E00020A0E3B2 S3150001B9B838008DE2FE0E00EB24209DE50A0020E00A S3150001B9C80030A0E30310A0E130008DE520349FE5A7 S3150001B9D80200A0E10420A0E37F1300EB10049FE519 S3150001B9E80410A0E37DFAFFEB0450A0E352FEFFEA40 S3150001B9F8FF0059E3D6FFFF0A38008DE20410A0E1E3 S3150001BA080620A0E12F0100EB040056E36E00001AA0 S3150001BA180030D4E5603043E2FF3003E2010053E32E S3150001BA287100008AA0339FE50FE0A0E113FF2FE123 S3150001BA380090D4E50170D4E5609049E22771A0E150 S3150001BA48FF9009E220008DE50910A0E10700A0E1B9 S3150001BA58E80300EB0130A0E10020A0E138008DE207 S3150001BA68420E00EB0A1028E00020A0E338008DE220 S3150001BA78CF0E00EB0010A0E30A0020E00620A0E1AB S3150001BA886C339FE530008DE5531300EB60039FE5AA S3150001BA980610A0E1D2FFFFEA120056E34400001A9D S3150001BAA838008DE20410A0E10620A0E1050100EBB3 S3150001BAB80400A0E10B10A0E10120A0E3460300EB7E S3150001BAC838008DE20A10A0E3490100EB10F8FFEBFC S3150001BAD81DFFFFEA38008DE20410A0E10620A0E16F S3150001BAE8F80000EB0410A0E10420A0E330008DE289 S3150001BAF8DC1200EB34008DE22A108DE20B20A0E166 S3150001BB08860300EB000050E32400001A30208DE282 S3150001BB180C0092E8033082E0100000EA38008DE25A S3150001BB280410A0E10620A0E1E60000EB0410A0E164 S3150001BB380420A0E330008DE2CA1200EB0B20A0E13D S3150001BB4834008DE22A108DE2740300EB000050E305 S3150001BB5830309D0534209D05023063000F00001A20 S3150001BB6834308DE5F8FEFFEA38008DE20410A0E1D5 S3150001BB780620A0E1D30000EB0410A0E10420A0E315 S3150001BB8830008DE2B71200EB34008DE22A108DE207 S3150001BB980B20A0E1610300EB000050E3EAFEFF0A77 S3150001BBA80410A0E338008DE2110100EBD8F7FFEB92 S3150001BBB80030E0E3012CA0E3CB2B03E5022CA0E344 S3150001BBC8CB2B03E50150A0E3DBFDFFEA010056E3B9 S3150001BBD8DDFEFF1A0030D4E50A0053E30800000A27 S3150001BBE8040053E3D8FEFF1AB4FFFFEA0030D4E598 S3150001BBF8300053E31700001A0110D4E53F0051E362 S3150001BC080200009A38008DE20410A0E3ADFFFFEAB6 S3150001BC18210157E1FAFFFF1A1C009DE50120A0E367 S3150001BC28F70200EB1C009DE51010A0E302F7FFEBFD S3150001BC3838008DE21C109DE51220A0E32C308DE220 S3150001BC48C30000EB1C009DE51210A0E32C209DE526 S3150001BC58ECF9FFEBBCFEFFEAA00053E30B00001A68 S3150001BC680130D4E53F0053E3E5FFFF8A230157E19D S3150001BC78E3FFFF1A0A10A0E338008DE2DC0000EBAF S3150001BC88A3F7FFEB0750A0E301B0D4E5AAFDFFEA4D S3150001BC98402083E2FF2002E2020052E31900008AF3 S3150001BCA80100D4E53F0050E3D5FFFF8A2061A0E1FA S3150001BCB8070056E1D2FFFF1AE00200EB000050E34D S3150001BCC8CFFFFF1A0A10A0E338008DE2C80000EB87 S3150001BCD88FF7FFEB0050D4E5C10055E30850A003E8 S3150001BCE80500000AC00055E30950A0030200000A36 S3150001BCF8C20055E30A50A0030650A01301B0D4E5CB S3150001BD080670A0E18CFDFFEAB00053E30A00001AB1 S3150001BD180120D4E53F0052E3B9FFFF8A220157E12A S3150001BD28B7FFFF1A34009DE52A10DDE5100300EB85 S3150001BD38000050E361FFFF0AB1FFFFEA500053E339 S3150001BD48AFFFFF1A0130D4E5000053E3ACFFFF1A39 S3150001BD580030E0E3012CA0E3CB2B03E5022CA0E3A2 S3150001BD68CB2B03E540309FE5003093E5030053E311 S3150001BD78060000DA50309FE50FE0A0E113FF2FE13E S3150001BD8818309DE5001063E06C009FE5991200EB01 S3150001BD980B50A0E368FDFFEA44D08DE2F04FBDE801 S3150001BDA81EFF2FE160002000AC2A20008000200041 S3150001BDB8841E1200B9002000010000A5E8800000D9 S3150001BDC8140820003A1F12000020100885002000E0 S3150001BDD8F40020006C0020006E002000780020008E S3150001BDE87B002000961E120073002000B21E12006E S3150001BDF8CE1E12002D2B2000F21E1200191F120052 S3150001BE0878209FE50F3000E25233A0E12012A0E12D S3150001BE186C209FE50F1001E25211A0E164C09FE575 S3150001BE282024A0E10F2002E25C22A0E1081001E231 S3150001BE38042002E2103003E2022081E1032082E1BC S3150001BE4844109FE52036A0E10F3003E25133A0E10B S3150001BE58023003E2032082E12008A0E12C309FE5AD S3150001BE680F0000E25330A0E1013003E2030082E152 S3150001BE781C309FE53300A0E1010000E21EFF2FE11F S3150001BE88C0220F00C0C90600B0C8030058E401006B S3150001BE9838D900000AE857EC00009FE51EFF2FE19C S3150001BEA8FC39200000009FE51EFF2FE1EC3720003A S3150001BEB800009FE51EFF2FE1FC39200000009FE5E9 S3150001BEC81EFF2FE184432000010052E3F8402DE9CB S3150001BED80070A0E10150A0E10260A0E10040A0E3EA S3150001BEE80A00000A060054E1170000AA0010A0E3A0 S3150001BEF80700A0E10120A0E19A0D00EB0430D5E787 S3150001BF08030020E00400C5E7014084E2F4FFFFEAEC S3150001BF180460A0E10010A0E30700A0E10120A0E170 S3150001BF28490D00EB0030D5E55334A0E1013003E2B9 S3150001BF38000023E0106486E1014084E2040054E332 S3150001BF48FF6006E2F2FFFF1A0060C5E5F840BDE8AA S3150001BF581EFF2FE1F74F2DE90350A0E10190A0E361 S3150001BF68013042E21993A0E10030A0E3003085E5F3 S3150001BF780060A0E10180A0E10270A0E10140A0E11A S3150001BF88043068E0070053E1160000AA0010A0E398 S3150001BF980120A0E10600A0E100A0D4E5710D00EBA7 S3150001BFA80130D4E4030020E0010044E5000096E5F1 S3150001BFB892FFFFEB0030A0E10A00A0E100B095E591 S3150001BFC804308DE500F6FFEB04309DE5030020E023 S3150001BFD8013000E2990303E0ABB0A0E10BB083E1C5 S3150001BFE800B085E5E5FFFFEA0CD08DE2F04FBDE82C S3150001BFF81EFF2FE1F8402DE90040A0E30070A0E103 S3150001C0080160A0E10450A0E10010A0E30700A0E14F S3150001C0180120A0E10C0D00EB5634A0E1013003E24A S3150001C028000023E0105485E1014084E2040054E352 S3150001C038FF5005E2F3FFFF1A0500A0E1F840BDE84D S3150001C0481EFF2FE1F04F2DE91CD04DE20C708DE259 S3150001C0580190A0E10060A0E10210A0E30700A0E1C1 S3150001C0680D30CDE540509DE50C20CDE5F2F5FFEB11 S3150001C0780C309DE5000059E310308DE51D00000ADE S3150001C0880040A0E314408DE50010A0E30120A0E1E3 S3150001C0980600A0E1330D00EB04B0D7E714309DE5A7 S3150001C0A800002BE010808DE20800C4E7000096E549 S3150001C0B8A3A0A0E151FFFFEB0020A0E10B00A0E146 S3150001C0C804208DE5C0F5FFEB04209DE5020020E084 S3150001C0D8012000E2014084E282218AE1040054E35E S3150001C0E814208DE5E7FFFF1A0800A0E10410A0E17E S3150001C0F8F2F8FFEB020000EA0700A0E10410A0E352 S3150001C108F0F8FFEB14108DE20500A0E119F9FFEB39 S3150001C11844109DE5000051E314309D15003081154A S3150001C128010059E30080A0E11D00001A010050E357 S3150001C1380040A0130F00001A0070A0E30740A0E119 S3150001C1480010A0E30600A0E10120A0E1BE0C00EB6F S3150001C1580030D5E55334A0E1013003E2000023E0C5 S3150001C168107487E1014084E2040054E3F3FFFF1AE7 S3150001C1780070C5E50A0000EA080054E10800000A53 S3150001C1880010A0E30600A0E10120A0E1F50C00EBF8 S3150001C1980430D5E7030020E00400C5E7014084E246 S3150001C1A8F4FFFFEA0800A0E11CD08DE2F04FBDE8DC S3150001C1B81EFF2FE107402DE910C09DE500C08DE562 S3150001C1C800C0A0E304C08DE59DFFFFEB0CD08DE216 S3150001C1D804E09DE41EFF2FE1F04F2DE91CD04DE24E S3150001C1E802C0A0E148508DE2300095E888229FE51B S3150001C1F8013003E201A0A0E10010A0E310108DE5D3 S3150001C20814108DE500208DE5FF1004E2602083E21D S3150001C2180C30A0E10060A0E150909DE5E4FFFFEB42 S3150001C22858829FE5003098E5030053E30070A0E1CA S3150001C2384C029FC50710A0C16E1100CB040057E33D S3150001C2480100A0138900001A5530A0E30C30CDE592 S3150001C2584130A0E30D30CDE54930A0E30E30CDE500 S3150001C2680710A0E16D30E0E30C029FE50F30CDE544 S3150001C2787C1100EB053094E10070A0E10600A011E5 S3150001C288570C001B0600A0E140308DE20C0093E834 S3150001C298360C00EB000055E3020054030600A0E14A S3150001C2A80A1027E00300001A0120A0E3C00C00EBE6 S3150001C2B8007027E0010000EA0020A0E3BC0C00EBB7 S3150001C2C8000059E3007089150500001A003098E549 S3150001C2D8020053E3AC019FC50A10A0C10720A0C103 S3150001C2E8441100CB0050A0E30540A0E10C308DE2DB S3150001C2F803A0D4E70020A0E30A10A0E10600A0E10C S3150001C308980C00EB10908DE200002AE00900C4E7C2 S3150001C318000096E5B9FEFFEB00B0A0E10A00A0E136 S3150001C32829F5FFEB0B0020E001B000E27F30E0E3E6 S3150001C338930B0BE0014084E2A5508BE1040054E322 S3150001C348FF5005E2E8FFFF1A0700A0E12010A0E36D S3150001C358AA0C00EB0070A0E10700A0E10810A0E319 S3150001C368A60C00EB0010A0E30120A0E10070A0E1FB S3150001C3780600A0E17B0C00EBFFA007E200002AE023 S3150001C3880400C9E7000096E59CFEFFEB00B0A0E1BA S3150001C3980A00A0E10CF5FFEB0B0020E001B000E27A S3150001C3A87F30E0E3930B0BE0014084E2A5508BE17B S3150001C3B8080054E3FF5005E2E6FFFF1A0900A0E171 S3150001C3C80410A0E10520A0E13CF8FFEBA8009FE5D9 S3150001C3D845F8FFEB000050E30500001A003098E528 S3150001C3E8000053E31E0000DA9C009FE5011100EBF3 S3150001C3F81B0000EA0420A0E37C109FE508008DE2FB S3150001C408981000EB2010A0E30700A0E17B0C00EBDD S3150001C4180010A0E30120A0E10040A0E10600A0E190 S3150001C428630C00EB0410A0E30050A0E108008DE2C4 S3150001C4380C1100EB042025E00030A0E3010053E1D4 S3150001C448000052010000A0030800000A003098E528 S3150001C458000053E3040000DA30009FE5E51000EB25 S3150001C468010000EA0200A0E3000000EA0300A0E3DD S3150001C4781CD08DE2F04FBDE81EFF2FE1FC392000EC S3150001C48880002000CC1F1200DF1F1200F71F1200C8 S3150001C4981C20120030402DE91CD04DE228508DE2B7 S3150001C4A8300095E830008DE830508DE2300095E88F S3150001C4B800C0A0E308408DE50C508DE510C08DE560 S3150001C4C844FFFFEB1CD08DE23040BDE81EFF2FE193 S3150001C4D8F3412DE9F4509FE502C0A0E10360A0E114 S3150001C4E800508DE50110A0E33020A0E30C30A0E157 S3150001C4F82FFFFFEB010050E30040A0E10800001AFE S3150001C508CC309FE5003093E5000053E3270000DABD S3150001C518C0309FE5C0009FE5E81DD3E5B51000EBE7 S3150001C528220000EA120050E30700000AA0309FE546 S3150001C538003093E5000053E31E0000DA9C009FE5F6 S3150001C5480410A0E1AB1000EB1A0000EA84409FE555 S3150001C5580500A0E11010A0E3F88DD4E5F97DD4E536 S3150001C568B5F4FFEBF83DD4E5080053E10200001AE3 S3150001C578F93DD4E5070053E10600000A50309FE56E S3150001C588003093E5000053E30C0000DA50009FE504 S3150001C598981000EB090000EA0600A0E10510A0E1E9 S3150001C5A81020A0E32F1000EB0000A0E3040000EA2E S3150001C5B80400A0E1020000EA0200A0E3000000EA8C S3150001C5C80300A0E308D08DE2F041BDE81EFF2FE18C S3150001C5D8FC39200080002000142C2000482012007D S3150001C5E85820120079201200F04F2DE90340A0E1EE S3150001C5F874319FE502C0A0E134D04DE200308DE5EB S3150001C6080110A0E3A020A0E30C30A0E10060A0E1A6 S3150001C618E7FEFFEB010050E30300001A4C819FE59A S3150001C628E83DD8E50A0053E30800000A40319FE5D2 S3150001C638003093E5000053E3450000DA2C319FE50D S3150001C64830019FE5E81DD3E56A1000EB400000EADA S3150001C65808708DE20410A0E11020A0E30700A0E114 S3150001C668001000EB0700A0E11010A0E372F4FFEB45 S3150001C6780050A0E30540A0E10010A0E30120A0E1DD S3150001C6880600A0E1B70B00EB04A0D7E71C908DE2EA S3150001C69800002AE00900C4E7000096E5D7FDFFEB94 S3150001C6A800B0A0E10A00A0E147F4FFEB014084E2F3 S3150001C6B80B0020E0A550A0E101B000E2120054E30E S3150001C6C88B5885E1EBFFFF1A0410A0E10520A0E1D4 S3150001C6D80900A0E179F7FFEB8C009FE582F7FFEBF4 S3150001C6E80040A0E30070A0E10450A0E10010A0E31F S3150001C6F80600A0E10120A0E1530B00EBE83DD8E5D7 S3150001C7085335A0E1013003E2000023E0104584E13E S3150001C718015085E2040055E3FF4004E2F2FFFF1AE7 S3150001C728010057E30A0054030000A0030100A01307 S3150001C7380A00000A38309FE5003093E5000053E30C S3150001C748050000DA30009FE50410A0E1291000EB8E S3150001C758010000EA0100A0E3000000EA0200A0E3EC S3150001C76834D08DE2F04FBDE81EFF2FE1FC392000E1 S3150001C778142C20008000200048201200912012006D S3150001C78807402DE944309FE5001090E200308DE521 S3150001C7980110A0135020A0E30030A0E384FEFFEBB4 S3150001C7A8001050E20100A0010500000A20309FE5B3 S3150001C7B8003093E5000053E318009FC50D1000CB28 S3150001C7C80100A0E30CD08DE204E09DE41EFF2FE1F9 S3150001C7D8FC39200080002000AC20120008402DE919 S3150001C7E80030A0E114009FE50222A0E1010280E0E9 S3150001C7F80310A0E19B0F00EB0840BDE81EFF2FE1E7 S3150001C8088443200008402DE910309FE50222A0E16B S3150001C818011283E0930F00EB0840BDE81EFF2FE1EC S3150001C8288443200008402DE90C309FE5011083E080 S3150001C8388C0F00EB0840BDE81EFF2FE18443200062 S3150001C848D4209FE5003282E00410D3E50022D2E726 S3150001C8580110E0E1FF1001E2010052E12C00001A8B S3150001C8680810D3E5020051E12900001A0510D3E5A5 S3150001C8780120D3E50110E0E1FF1001E2010052E1D8 S3150001C8882300001A0910D3E5020051E12000001A1D S3150001C8980610D3E50220D3E50110E0E1FF1001E21D S3150001C8A8010052E11A00001A0A10D3E5020051E10B S3150001C8B81700001A0710D3E50320D3E50110E0E1BC S3150001C8C8FF1001E2010052E11100001A0B10D3E535 S3150001C8D8020051E10E00001A0D10D3E50C20D3E534 S3150001C8E80110E0E1FF1001E2010052E10800001A1F S3150001C8F80E10D3E5020051E10500001A0F00D3E539 S3150001C9080000E0E1FF0000E2000052E00100A01390 S3150001C9181EFF2FE10100A0E31EFF2FE18443200043 S3150001C928F8402DE90070A0E10200A0E10160A0E154 S3150001C9380250A0E1C1FFFFEB004050E20140A01305 S3150001C9480700001A24309FE5055283E00700A0E19D S3150001C9580510A0E10420A0E3420F00EB0C30D5E559 S3150001C9680030C6E50400A0E1F840BDE81EFF2FE14E S3150001C97884432000F7402DE974409FE508508DE275 S3150001C988040025E5024284E00470A0E30160A0E109 S3150001C9980720A0E10510A0E10400A0E1310F00EB9A S3150001C9A80510A0E10720A0E1080084E22D0F00EBA5 S3150001C9B804309DE5070084E00330E0E10510A0E1BD S3150001C9C80720A0E104308DE5260F00EB0630E0E1F3 S3150001C9D8FF3003E20000A0E30C60C4E50D30C4E5B6 S3150001C9E80E60C4E50F30C4E50CD08DE2F040BDE819 S3150001C9F81EFF2FE18443200013402DE90A30A0E3EE S3150001CA080003A0E1930121E028309FE50640A0E359 S3150001CA18011083E00420A0E10D00A0E1110F00EB55 S3150001CA280D00A0E10410A0E18E0F00EB08D08DE205 S3150001CA381040BDE81EFF2FE1B443200010402DE948 S3150001CA4820D04DE270109FE51020A0E30D00A0E173 S3150001CA58040F00EB64109FE51020A0E310008DE29F S3150001CA68000F00EB58009FE50010A0E3012AA0E3A0 S3150001CA78700F00EB0340A0E30410A0E10D00A0E154 S3150001CA880120A0E354FFFFEB7E0054E3044084D267 S3150001CA98F8FFFFDA104084E2FF0054E3F5FFFFDAFE S3150001CAA810108DE21020A0E314009FE5ED0E00EBB7 S3150001CAB820D08DE21040BDE81EFF2FE15F0D120068 S3150001CAC86F0D120084432000F04F2DE900A0A0E16C S3150001CAD844D04DE20300A0E101B0A0E10610A0E3B5 S3150001CAE8600F00EB0070A0E30040A0E10150A0E157 S3150001CAF81C708DE520708DE50190A0E31CF3FFEB1A S3150001CB085BF7FFEB0030E0E3012CA0E3CF9B03E5E5 S3150001CB18CB2B03E5022CA0E3CB2B03E524008DE206 S3150001CB280710A0E118208DE2B8F6FFEB003050E2BD S3150001CB3858619FE530808DE20700001A002096E5CE S3150001CB48070052E1010000CA0070A0E32C0000EAC8 S3150001CB583C019FE514308DE5270000EA0020A0E39B S3150001CB680030A0E308208DE50C308DE530008DE816 S3150001CB781C008DE218109DE50A20A0E10B30A0E10A S3150001CB8843FEFFEB005050E20500000A003096E52F S3150001CB98000053E3EBFFFFDAF8009FE5150F00EB02 S3150001CBA8170000EA1C008DE218109DE50A20A0E195 S3150001CBB80830A0E145FEFFEB004050E20400000A00 S3150001CBC8003096E5000053E3CC009FC50A0000CA71 S3150001CBD8DCFFFFEA1C008DE218109DE5E7FEFFEB7E S3150001CBE8000050E30970A0010500000A003096E52F S3150001CBF8000053E3D3FFFFDAA0009FE5FD0E00EB2B S3150001CC08D0FFFFEA1C008DE2F50900EB003096E53E S3150001CC18010053E388009FC59E0E00CB84309FE533 S3150001CC280020A0E324308DE50130A0E378C09FE51C S3150001CC3800308DE524008DE20230A0E10410A0E366 S3150001CC480FE0A0E11CFF2FE10040E0E30020A0E394 S3150001CC58015CA0E31030A0E3CF5B04E50710A0E177 S3150001CC6804308DE500808DE50230A0E1FF00A0E3E8 S3150001CC78990E00EBE000A0E3CB5B04E515ECFFEBB6 S3150001CC88CE0E00EB44D08DE2F04FBDE81EFF2FE13A S3150001CC9880002000C920120072221200DB20120037 S3150001CCA8EC201200F72012004444444414082000E2 S3150001CCB8F04F2DE90080A0E174D04DE20300A0E118 S3150001CCC801B0A0E10610A0E3E60E00EB0090A0E398 S3150001CCD80040A0E10150A0E11C908DE520908DE572 S3150001CCE801A0A0E3A2F2FFEBE1F6FFEB0030E0E3DF S3150001CCF8012CA0E3CFAB03E5CB2B03E5022CA0E384 S3150001CD08CB2B03E524008DE20910A0E118208DE262 S3150001CD183EF6FFEB003050E21C629FE530708DE273 S3150001CD280700001A002096E5090052E1010000CA31 S3150001CD380090A0E3550000EA00029FE514308DE556 S3150001CD48500000EA0881A0E10020A0E30030A0E33A S3150001CD58FF8008E208208DE50C308DE530008DE86E S3150001CD681C008DE218109DE50820A0E10B30A0E11A S3150001CD78C7FDFFEB004050E20500000A003096E5CA S3150001CD88000053E3E9FFFFDAB4019FE5990E00EBD2 S3150001CD983E0000EA1C008DE218109DE50820A0E17E S3150001CDA80730A0E1C9FDFFEB005050E20400000A7C S3150001CDB8003096E5000053E388019FC5310000CA9B S3150001CDC8DAFFFFEA012088E2FF2002E21C008DE279 S3150001CDD818109DE5103087E2BCFDFFEB004050E2DC S3150001CDE80400000A003096E5000053E358019FC588 S3150001CDF8240000CACDFFFFEA022088E21C008DE26A S3150001CE0818109DE5FE2002E2203087E2AFFDFFEB18 S3150001CE18005050E20400000A003096E5000053E392 S3150001CE2828019FC5170000CAC0FFFFEA038088E2F0 S3150001CE38FF2008E21C008DE218109DE5303087E2DC S3150001CE48A2FDFFEB004050E20400000A003096E51F S3150001CE58000053E3F8009FC50A0000CAB3FFFFEAC2 S3150001CE681C008DE218109DE544FEFFEB000050E31F S3150001CE780A90A0010500000A003096E5000053E378 S3150001CE88AAFFFFDACC009FE55A0E00EBA7FFFFEADF S3150001CE981C008DE2520900EB003096E5010053E3D0 S3150001CEA8B4009FC5FB0D00CBB0309FE50020A0E381 S3150001CEB824308DE50130A0E3A4C09FE500308DE55F S3150001CEC824008DE20230A0E10410A0E30FE0A0E106 S3150001CED81CFF2FE12060A0E30040E0E3015CA0E332 S3150001CEE80020A0E3CF5B04E50910A0E100708DE501 S3150001CEF80230A0E104608DE5FF00A0E3F60D00EB2A S3150001CF08067087E00020A0E30910A0E10230A0E145 S3150001CF1800708DE504608DE5FF00A0E3EE0D00EBE2 S3150001CF28E000A0E3CB5B04E56AEBFFEB230E00EB25 S3150001CF3874D08DE2F04FBDE81EFF2FE1800020007E S3150001CF48C9201200722212000B2112001E211200A2 S3150001CF583121120044211200EC201200572112003F S3150001CF684444444414082000F04F2DE90090A0E100 S3150001CF783CD04DE20300A0E101A0A0E10610A0E328 S3150001CF880360A0E1370E00EB0070A0E31020A0E3D8 S3150001CF980040A0E10150A0E128008DE20A1086E2D6 S3150001CFA8B00D00EB0180A0E314708DE518708DE5D6 S3150001CFB8EFF1FFEB2EF6FFEB0030E0E3012CA0E3E7 S3150001CFC8CF8B03E5CB2B03E5022CA0E3CB2B03E5A3 S3150001CFD81C008DE20710A0E110208DE28BF5FFEB16 S3150001CFE800B050E244619FE50500001A003096E55D S3150001CFF8070053E138019FC5110000CA0040A0E3AC S3150001D008280000EA30008DE80050A0E30040A0E3C4 S3150001D01808408DE50C508DE514008DE210109DE554 S3150001D0280920A0E10A30A0E119FDFFEB005050E20A S3150001D0380500000A003096E5000053E3EEFFFFDA2B S3150001D048F0009FE5EB0D00EBEBFFFFEA14008DE224 S3150001D05810109DE50920A0E128308DE261FDFFEB66 S3150001D068004050E20400000A003096E5000053E350 S3150001D078C4009FC5F2FFFFCADFFFFFEA14008DE275 S3150001D08810109DE5BDFDFFEB000050E30840A0012F S3150001D0980400000A003096E5000053E3D6FFFFDAE4 S3150001D0A898009FE5D30D00EB14008DE2CC0800EB48 S3150001D0B8003096E5010053E384009FC5750D00CB4A S3150001D0C880309FE50020A0E31C308DE50130A0E308 S3150001D0D874C09FE500308DE51C008DE20230A0E1A9 S3150001D0E80410A0E30FE0A0E11CFF2FE10050E0E3EC S3150001D0F80020A0E3016CA0E3CF6B05E50410A0E1D5 S3150001D10800208DE504208DE50230A0E1FF00A0E3B3 S3150001D118710D00EBE000A0E3CB6B05E5EDEAFFEB53 S3150001D128A60D00EB3CD08DE2F04FBDE81EFF2FE1C6 S3150001D13880002000C9201200722212006C21120000 S3150001D148EC2012007E2112004444444414082000B5 S3150001D158F0472DE90070A0E1200CA0E10150A0E103 S3150001D1680240A0E10360A0E197F1FFEB00A0A0E176 S3150001D178250CA0E10090D6E593F1FFEB090020E02C S3150001D1888487A0E1FF9000E2A89F29E009305AE0D0 S3150001D1982708A0E1009073E2FF0000E20390B9E0DE S3150001D1A889F1FFEB00A0A0E12508A0E1FF0000E25C S3150001D1B80180D6E584F1FFEB080020E0FF8000E25C S3150001D1C82704A0E1843BA0E1FF0000E2A38F28E049 S3150001D1D87DF1FFEB0070A0E12504A0E1FF0000E26C S3150001D1E80260D6E578F1FFEB060020E0014004E293 S3150001D1F8FF0000E208005AE10080A013018009023D S3150001D208040020E0000057E10000A0130100080215 S3150001D218F047BDE81EFF2FE1F04F2DE9FF0000E2C0 S3150001D228ADDF4DE2FF1001E21C008DE528108DE50A S3150001D2380300A0E10610A0E302B0A0E1890D00EB0E S3150001D2480040A0E320008DE524108DE544408DE5DE S3150001D25848408DE50FFBFFEB0B30A0E358308DE519 S3150001D2685C308DE560308DE564308DE568308DE59F S3150001D2786C308DE500A0A0E13DF1FFEB0400A0E1D3 S3150001D28849F1FFEB7AF5FFEB0030E0E30120A0E37B S3150001D298CF2B03E5012CA0E3CF2B03E5022CA0E35A S3150001D2A8CB2B03E5E000A0E38AEAFFEBC800A0E385 S3150001D2B8570D00EB7D5EA0E30470A0E10460A0E1D8 S3150001D2C8E000A0E383EAFFEB6400A0E3500D00EB66 S3150001D2D8A400A0E37FEAFFEB0030E0E3C33B13E5DC S3150001D2E8020513E35900000A4C008DE20010A0E381 S3150001D2F830208DE2C5F4FFEB000050E30500001A6B S3150001D30818369FE5003093E5000053E310069FC5E4 S3150001D318150000CA4D0000EA20308DE20C0093E8A2 S3150001D3280C008DE80020A0E30030A0E308208DE57D S3150001D3380C308DE534308DE210308DE544008DE2F8 S3150001D34830109DE51C209DE528309DE5A1FBFFEBEE S3150001D358000050E30600000AC0359FE5003093E55A S3150001D368000053E3390000DAB8059FE5210D00EB0B S3150001D378360000EA20308DE20C0093E80C008DE8B7 S3150001D3880220A0E30030A0E308208DE50C308DE5EE S3150001D39838308DE210308DE544008DE230109DE580 S3150001D3A81C209DE528309DE58AFBFFEB000050E334 S3150001D3B80500000A64359FE5003093E5000053E354 S3150001D3C864059FC5E8FFFFCA200000EA34009DE511 S3150001D3D87D1FA0E3890800EB50859FE50030A0E199 S3150001D3E80300A0E10110A0E3840800EB38209DE5C5 S3150001D3F8020050E10030A0E10300000A018088E242 S3150001D4087D0E58E3F5FFFF1A0C0000EA0C259FE58F S3150001D418002092E5080055E10850A0A1080054E152 S3150001D4280840A0B1030052E3087087E000808DC56B S3150001D438FC049FC50610A0C134209DC5ED0C00CB88 S3150001D448016086E20A0056E39CFFFF1A010000EA22 S3150001D458000056E32E01000AC0349FE5003093E52B S3150001D468020053E3070000DA0610A0E10700A0E175 S3150001D4780B0C00EB0510A0E10030A0E10420A0E1AF S3150001D488B0049FE5DB0C00EB2B34A0E12C308DE5D5 S3150001D498012CA0E30030E0E3CB2B03E5022CA0E34B S3150001D4A8CF2B03E50080A0E370649FE5003096E585 S3150001D4B8030053E380049FC5CE0C00CBE000A0E334 S3150001D4C804EAFFEB6400A0E3D10C00EBA400A0E39F S3150001D4D800EAFFEB0030E0E3C33B13E5020513E383 S3150001D4E89200000A4C008DE20010A0E330208DE284 S3150001D4F846F4FFEB000050E30400001A003096E5FD S3150001D508000053E318049FC5150000CA870000EA06 S3150001D51820308DE20C0093E80C008DE80020A0E392 S3150001D5280030A0E308208DE50C308DE534308DE21E S3150001D53810308DE544008DE230109DE51C209DE5F7 S3150001D54828309DE523FBFFEB000050E30600000AA7 S3150001D558C8339FE5003093E5000053E3730000DA12 S3150001D568C0039FE5A30C00EB700000EA2C309DE593 S3150001D5783C108DE2012003E204108DE5FF300BE239 S3150001D5880210A0E300A08DE544008DE2602082E24E S3150001D598ABFAFFEB040050E30010A0E17C639FE5C2 S3150001D5A80500000A003096E5000053E35F0000DA43 S3150001D5B888039FE58F0C00EB5C0000EA0A00A0E1F6 S3150001D5C8A80C00EB002096E5030052E30030A0E129 S3150001D5D838008DE5050000DA3C209DE560039FE5EE S3150001D5E800208DE50810A0E134209DE5810C00EBB3 S3150001D5F80060A0E30600DAE773F0FFEB3C309DE537 S3150001D608082003E2A20150E10010A0030110A013B3 S3150001D61840208DE20210C6E7016086E28330A0E170 S3150001D628040056E33C308DE5F1FFFF1A34009DE511 S3150001D6380A1045E2F10700EB099045E20060A0E116 S3150001D6480070A0E3093084E2090053E11F0000BA23 S3150001D6580600A0E10110A0E3E80700EB38109DE5FC S3150001D66801C020E00C20A0E140308DE218C08DE514 S3150001D6780060A0E1B5FEFFEB000050E318C09DE590 S3150001D6881000000A0A0057E30E0000CA373087E285 S3150001D6982B0E8DE2833180E0106203E50CC203E5AF S3150001D6A878329FE5003093E5017087E2030053E382 S3150001D6B86C708DE58C029FC50910A0C10C20A0C114 S3150001D6C80630A0C14B0C00CB019089E2DCFFFFEAD2 S3150001D6D86CE09DE500005EE31100000A0030A0E35E S3150001D6E858208DE2032192E70A0052E3770000CA27 S3150001D6F8013083E2050053E3F8FFFF1A0030A0E387 S3150001D70858208DE2032192E702005EE16F0000BA1C S3150001D718013083E2050053E3F8FFFF1A000000EA2F S3150001D72800E080E5018088E20F0058E35DFFFF1AFB S3150001D738022CA0E30030E0E3CB2B03E544008DE2A5 S3150001D748270700EB00329FE50020A0E34C308DE56A S3150001D7580130A0E300308DE54C008DE20230A0E1F6 S3150001D7680410A0E3E4C19FE50FE0A0E11CFF2FE14F S3150001D7782C209DE5FFB00BE2FF3002E203B48BE0FB S3150001D7880040A0E358308DE2048193E70A0058E38C S3150001D7980BA0A0D39A0403D00050A0D31C308DD57A S3150001D7A8120000DA014084E2050054E3F4FFFF1A8F S3150001D7B8300000EA01CCA0E30070E0E33030A0E3DA S3150001D7C8CFCB07E5FF00A0E304308DE500908DE59A S3150001D7D80010A0E30620A0E10B30A0E118C08DE5FA S3150001D7E8BD0B00EB18C09DE5CBCB07E5055085E2DF S3150001D7F8080055E1EAFFFFAA70908DE23020A0E308 S3150001D8080900A0E10010A0E30A0C00EB30309DE509 S3150001D8181C009DE5086065E070308DE5A0208DE26D S3150001D828003085E0050056E30560A0A378708DE217 S3150001D83883A182E000C0A0E306005CE1DCFFFFAA49 S3150001D8480A10A0E10700A0E10420A0E318C08DE5B5 S3150001D858840B00EB040087E204108AE20420A0E3AB S3150001D868800B00EB18C09DE5087087E201C08CE2C9 S3150001D87808A08AE2EFFFFFEA0020A0E30040E0E308 S3150001D888015CA0E3CF5B04E50230A0E100208DE551 S3150001D89804208DE5FF00A0E30110A0E38E0B00EB49 S3150001D8A8CB5B04E574309FE5003093E5030053E351 S3150001D8B89C009FC5770B00CBE000A0E305E9FFEBD1 S3150001D8C8BE0B00EB0100A0E3B7EFFFEB100000EA87 S3150001D8D85870A0E3930707E0A0208DE200C0A0E3FB S3150001D8E82B0E8DE2031180E0960F41E2581211E5E5 S3150001D8F801005CE189FFFFAA6E1F82E2030091E83D S3150001D908076082E0030086E801C08CE2082082E213 S3150001D918F2FFFFEAADDF8DE2F04FBDE81EFF2FE112 S3150001D92880002000C9201200932112009F211200B5 S3150001D938F5010000AB211200CE211200DC12120003 S3150001D948ED2112000022120026221200444444440A S3150001D9581408200046221200F04F2DE974719FE544 S3150001D9682CD04DE20040A0E30280A0E10360A0E1D3 S3150001D97801A0A0E10090A0E1005097E514408DE5D3 S3150001D98818408DE5004087E579EFFFEB0100A0E33C S3150001D99885EFFFEBB6F3FFEB0030E0E30120A0E3F0 S3150001D9A8CF2B03E5012CA0E3CB2B03E5022CA0E347 S3150001D9B8CB2B03E54B0FA0E3950B00EB080054E1D5 S3150001D9C80D0000AAE000A0E3C2E8FFEB6400A0E3B3 S3150001D9D88F0B00EBA400A0E3BEE8FFEB1C008DE271 S3150001D9E80010A0E310208DE208F3FFEB00B050E22F S3150001D9F80600001A000055E3010000CA0080A0E3F2 S3150001DA08130000EAD0009FE57A0B00EBFAFFFFEA64 S3150001DA180610A0E3916420E0920B00EB0020A0E33E S3150001DA280030A0E303008DE808208DE50C308DE574 S3150001DA3814008DE210109DE50920A0E10A30A0E14D S3150001DA4893FAFFEB000050E301408412DAFFFF1A54 S3150001DA580180A0E314008DE2610600EB7C309FE5AE S3150001DA680020A0E31C308DE50130A0E370C09FE5DE S3150001DA7800308DE51C008DE20230A0E10410A0E320 S3150001DA880FE0A0E11CFF2FE10630A0E3936424E038 S3150001DA980020A0E30090E0E301ACA0E3CFAB09E5E9 S3150001DAA80810A0E104308DE500408DE50230A0E1C3 S3150001DAB8FF00A0E3080B00EBE000A0E3CBAB09E510 S3150001DAC884E8FFEB3D0B00EB005087E52CD08DE297 S3150001DAD8F04FBDE81EFF2FE180002000C92012008B S3150001DAE8444444441408200008402DE914309FE5B5 S3150001DAF80010A0E1000083E50C009FE53D0B00EB5B S3150001DB080840BDE81EFF2FE18000200056221200C2 S3150001DB1808402DE9C8FBFFEB0840BDE81EFF2FE1D1 S3150001DB2808402DE900C0A0E10120A0E10300A0E121 S3150001DB380C10A0E128FBFFEB0840BDE81EFF2FE112 S3150001DB48F0412DE938D04DE20070A0E10160A0E175 S3150001DB5808808DE20800A0E10710A0E10620A0E1F7 S3150001DB6827FBFFEB0040E0E3015CA0E33030A0E3D4 S3150001DB78CF5B04E50710A0E104308DE500808DE553 S3150001DB880620A0E10030A0E3FF00A0E3D20A00EBE3 S3150001DB98CB5B04E538D08DE2F041BDE81EFF2FE1ED S3150001DBA8F0432DE90060A0E34CD04DE20190A0E1DD S3150001DBB814608DE518608DE5EDEEFFEB0600A0E13A S3150001DBC8F9EEFFEB2AF3FFEB0030E0E30120A0E3D7 S3150001DBD8CF2B03E5012CA0E3CB2B03E5022CA0E315 S3150001DBE8CB2B03E51C008DE20610A0E110208DE287 S3150001DBF886F2FFEB060050E10500001AA4329FE504 S3150001DC08003093E5060053E19C029FC58C0000CACB S3150001DC188C0000EAFF9009E20670A0E10700A0E186 S3150001DC280910A0E173FBFFEB000057E303008DE841 S3150001DC38FF8006E21000001A0020A0E30030A0E3EE S3150001DC4808208DE50C308DE514008DE210109DE558 S3150001DC580820A0E10930A0E10DFAFFEB000050E32E S3150001DC681800000A3C329FE5003093E5000053E3B3 S3150001DC7838029FC5100000CA670000EA0240A0E307 S3150001DC880050A0E308408DE50C508DE514008DE2A7 S3150001DC9810109DE50820A0E10930A0E1FCF9FFEB91 S3150001DCA8000050E30700000AF8319FE5003093E5CC S3150001DCB8000053E3580000DAF4019FE50710A0E1DC S3150001DCC8CC0A00EB540000EA14008DE210109DE521 S3150001DCD80820A0E128308DE2FCF9FFEB000050E3B3 S3150001DCE80500000ABC319FE5003093E5000053E3C7 S3150001DCF8C0019FC5350000CA470000EA28008DE229 S3150001DD080610A0E10120A0E3B3FAFFEB012088E2A7 S3150001DD18FF2002E214008DE210109DE528308DE205 S3150001DD28EAF9FFEB000050E30500000A74319FE5AC S3150001DD38003093E5000053E37C019FC5230000CA28 S3150001DD48350000EA28008DE2011086E20120A0E3F1 S3150001DD58A1FAFFEB022088E2FF2002E214008DE21D S3150001DD6810109DE528308DE2D8F9FFEB000050E34D S3150001DD780500000A2C319FE5003093E5000053E3C6 S3150001DD8838019FC5110000CA230000EA28008DE268 S3150001DD98021086E20120A0E3038088E28EFAFFEBF7 S3150001DDA8FF2008E214008DE210109DE528308DE26F S3150001DDB8C6F9FFEB000050E30600000AE4309FE5D0 S3150001DDC8003093E5000053E3130000DAF0009FE505 S3150001DDD8880A00EB100000EA034086E238008DE26B S3150001DDE80410A0E10120A0E385FAFFEB2E108DE2D5 S3150001DDF80420A0E33E008DE21A0A00EB017087E2D7 S3150001DE0838008DE20410A0E10120A0E372FAFFEBCD S3150001DE18100057E3046086E27FFFFF1A14008DE2C3 S3150001DE2810109DE555FAFFEB000050E30500000AC6 S3150001DE3870309FE5003093E5000053E3010000DAF6 S3150001DE4880009FE56B0A00EB14008DE2640500EB88 S3150001DE58E000A0E39FE7FFEB580A00EB44309FE59B S3150001DE68003093E5010053E35C009FC5090A00CB26 S3150001DE7858309FE50020A0E31C308DE50130A0E372 S3150001DE8800308DE51C008DE20410A0E30230A0E10C S3150001DE983CC09FE50FE0A0E11CFF2FE14CD08DE2CD S3150001DEA8F043BDE81EFF2FE180002000C9201200C3 S3150001DEB8662212007D2212000B2112001E21120079 S3150001DEC83121120044211200EC2012009B2212007B S3150001DED84444444414082000F0472DE90380A0E196 S3150001DEE838D04DE24030A0E30830CDE518608DE228 S3150001DEF84330A0E30170A0E10C30CDE50010A0E3AA S3150001DF084130A0E30290A0E1FFA000E20A20A0E3CD S3150001DF180600A0E11030CDE5460A00EBDDF7FFEB80 S3150001DF28080017E30040A0E1FF5007E21200000ACB S3150001DF380FEEFFEB0100A0E31BEEFFEB4CF2FFEB4C S3150001DF4800C0E0E30130A0E3CF3B0CE5013CA0E3D0 S3150001DF58CB3B0CE5023CA0E3CB3B0CE54B0FA0E326 S3150001DF682B0A00EBE000A0E35AE7FFEB6400A0E30D S3150001DF78270A00EBA400A0E356E7FFEB010015E32F S3150001DF881800000A0600A0E10010A0E314208DE2A3 S3150001DF989EF1FFEB007050E20500001A78329FE50A S3150001DFA8003093E5000053E370029FC50A0000CADA S3150001DFB80A0000EA0000A0E314109DE5EFF9FFEB63 S3150001DFC8000050E30700000A4C329FE5003093E554 S3150001DFD8000053E3010000DA44029FE5050A00EB5D S3150001DFE80040A0E3760000EA00005AE32500000A93 S3150001DFF808008DE20710A0E30020A0E304F1FFEB7F S3150001E0080400A0E138F1FFEB000050E30200000A2A S3150001E0180030D4E50A0053E30500000AF8319FE50C S3150001E028003093E5000053E3F8019FC5EAFFFFCAF4 S3150001E038EAFFFFEA10008DE20110A0E321F1FFEBF0 S3150001E0480400A0E128F1FFEB000050E30200000AFA S3150001E0580030D4E50A0053E30500000AB8319FE50C S3150001E068003093E5000053E3BC019FC5DAFFFFCA00 S3150001E078DAFFFFEA0000A0E314109DE5BFF9FFEB04 S3150001E088000050E3CFFFFF1A020015E31A00000A49 S3150001E09808008DE20710A0E30020A0E3DCF0FFEB07 S3150001E0A80400A0E110F1FFEB000050E3DAFFFF0ADC S3150001E0B80030D4E50A0053E3D7FFFF1A0C008DE2BE S3150001E0C80110A0E3FFF0FFEB0400A0E106F1FFEB6E S3150001E0D8000050E30200000A0030D4E50A0053E3C9 S3150001E0E80500000A30319FE5003093E5000053E34F S3150001E0F838019FC5B8FFFFCAB8FFFFEA0000A0E3D1 S3150001E108FF3009E200408DE50010A0E1A020A0E360 S3150001E11827F8FFEB010050E30200001A0030D4E5AE S3150001E1280A0053E30500000AEC309FE5003093E549 S3150001E138000053E3F8009FC5A7FFFFCAA7FFFFEA40 S3150001E1481020A0E30810A0E124008DE2450900EBA8 S3150001E15824008DE21010A0E3B7EDFFEB24008DE259 S3150001E1681210A0E3D7F0FFEB0400A0E1DEF0FFEB0D S3150001E178010050E30200001A0030D4E50A0053E317 S3150001E1880500000A90309FE5003093E5000053E34F S3150001E198A0009FC590FFFFCA90FFFFEA040015E3A0 S3150001E1A80100001A0140A0E3050000EA0000A0E30F S3150001E1B814109DE571F9FFEB000050E3F8FFFF0A23 S3150001E1C880FFFFEA0070E0E3018CA0E30430A0E3DE S3150001E1D80020A0E3CF8B07E5FF00A0E304308DE51F S3150001E1E800608DE50410A0E10230A0E13A0900EBD8 S3150001E1F8100015E3CB8B07E50100001A000054E374 S3150001E2080200001AE000A0E3B2E6FFEB6B0900EB9F S3150001E21838D08DE2F047BDE81EFF2FE180002000CF S3150001E228C9201200EC201200B6221200C2221200E6 S3150001E238CE221200DA221200F9221200F0412DE94B S3150001E24828D04DE24030A0E314608DE20070A0E1D1 S3150001E2580C30CDE50010A0E34330A0E30280A0E135 S3150001E2680600A0E11220A0E31030CDE5710900EB0C S3150001E27808F7FFEB080017E30040A0E1FF5007E2AB S3150001E2881200000A3AEDFFEB0100A0E346EDFFEBB1 S3150001E29877F1FFEB0010E0E30130A0E3CF3B01E5A6 S3150001E2A8013CA0E3CB3B01E5023CA0E3CB3B01E506 S3150001E2B84B0FA0E3560900EBE000A0E385E6FFEB70 S3150001E2C86400A0E3520900EBA400A0E381E6FFEB9A S3150001E2D8020015E32000000A0C008DE20710A0E3F6 S3150001E2E80020A0E34AF0FFEB0400A0E17EF0FFEB7B S3150001E2F8000050E30200000A0030D4E50A0053E3A7 S3150001E3080500000A30319FE5003093E5000053E32C S3150001E31828019FC5300000CA300000EA10008DE2CE S3150001E3280110A0E367F0FFEB0400A0E16EF0FFEB3C S3150001E338000050E30200000A0030D4E50A0053E366 S3150001E3480500000AF0309FE5003093E5000053E32D S3150001E358EC009FC5200000CA200000EA0000A0E3E7 S3150001E3683020A0E3FF3008E200408DE50010A0E16F S3150001E3788FF7FFEB120050E30020A0E10500000A29 S3150001E388B4309FE5003093E5000053E3B4009FC520 S3150001E398110000CA110000EA0600A0E10410A0E17C S3150001E3A8B00800EB040015E30100001A0140A0E3E0 S3150001E3B80B0000EA0000A0E30010A0E1EFF8FFEB74 S3150001E3C8000050E3F8FFFF0A6C309FE5003093E543 S3150001E3D8000053E3010000DA6C009FE5050900EB34 S3150001E3E80040A0E30070E0E3018CA0E31230A0E353 S3150001E3F80020A0E3CF8B07E5FF00A0E304308DE5FD S3150001E40800608DE50410A0E10230A0E1B20800EB3E S3150001E418100015E3CB8B07E50100001A000054E351 S3150001E4280200001AE000A0E32AE6FFEBE30800EB8E S3150001E43828D08DE2F041BDE81EFF2FE180002000C3 S3150001E448B6221200CE22120015231200EC20120069 S3150001E45838402DE934509FE50040A0E330309FE570 S3150001E4680500A0E10410A0E10820A0E3004083E52F S3150001E478F00800EB0400A0E10840C5E50940C5E540 S3150001E4880A40C5E50B40C5E53840BDE81EFF2FE14A S3150001E498342B2000182B200073402DE90040A0E3FF S3150001E4A80050E0E3016CA0E3CF6B05E50410A0E1A1 S3150001E4B800408DE504408DE50420A0E10430A0E18B S3150001E4C8FF00A0E3840800EB0400A0E1CB6B05E59F S3150001E4D808D08DE27040BDE81EFF2FE1F3472DE914 S3150001E4E8C4A09FE500409AE5000054E30400A0019A S3150001E4F82A00000A0220A0E32B3AE0E3DF2E03E517 S3150001E5080070A0E3000054E30050E0E3016CA0E3CF S3150001E51898909FE5110000DACF6B05E500309AE582 S3150001E528002099E5033064E0200054E30480A0B19B S3150001E5382080A0A3033082E008018DE8FF00A0E354 S3150001E5480730A0E10110A0E30820A0E1620800EB72 S3150001E558044068E0CB6B05E5017087E2E8FFFFEA56 S3150001E5680040A0E3CF6B05E50210A0E30420A0E17B S3150001E5780430A0E100408DE504408DE5FF00A0E3ED S3150001E588550800EBCB6B05E5000099E54410A0E3BF S3150001E5981C209FE500408AE5A60800EB0100A0E3E0 S3150001E5A808D08DE2F047BDE81EFF2FE1142B2000AD S3150001E5B860002000B80B00001C329FE50020D3E55F S3150001E5C8040052E302F19F977A0000EAE8E5110098 S3150001E5D808E6110088E61100D0E611009CE7110053 S3150001E5E80120A0E30010E0E3000050E3CB2B01E596 S3150001E5F80020C30510008305040083056F0000EAA7 S3150001E608101093E5011081E2020051E3C8219FE54C S3150001E618101083E50F00001A000050E30A00000AF3 S3150001E628040092E5090050E30000A0C30010C2C52A S3150001E638100082C5080082C50110A0C30020E0C3EE S3150001E6480410A0D3CF1B02C50010C2D5042093E540 S3150001E658012082E2042083E5102093E5030052E3BA S3150001E66874219FC50010A0C3101082C5042093E52C S3150001E6780E0052E30410A0C34B0000CA4F0000EA83 S3150001E688101093E5000050E3011081E248219FE54F S3150001E698101083E50200000A190051E3470000DA69 S3150001E6A8390000EA0310A0E30010C2E5100082E574 S3150001E6B8040082E5B200C2E10110A0E30020E0E314 S3150001E6C8CF1B02E53D0000EA101093E5011081E237 S3150001E6D8020051E300219FE5101083E50800001AA6 S3150001E6E8B210D2E1000050E3A110A0E1021C81138F S3150001E6F8B210C2E1042093E5012082E2042083E5F9 S3150001E708020000EA030051E30010A0C3101082C5FD S3150001E718041093E50A0051E3BC209FE52700001A7F S3150001E728B210D2E1B4009FE5000001E0020C50E30B S3150001E7380D00001A080092E514C092E5A110A0E1A7 S3150001E7480010CCE7081092E50C0092E5011081E271 S3150001E758000051E1081082E50010A0E3101082E5DF S3150001E7680210A0B3110000BA070000EA000051E345 S3150001E7780010A013101082150300001A0100A0E36F S3150001E7880030E0E3CB0B03E51EFF2FE10410A0E305 S3150001E798060000EA102093E5012082E20A0052E30E S3150001E7A8102083E5050000DA0010A0E328209FE584 S3150001E7B80010C2E5010000EA0020A0E30020C3E53D S3150001E7C80030D3E5040053E30120A0030030E00341 S3150001E7D8CB2B03050000A0E31EFF2FE1582B2000D9 S3150001E7E80102000013402DE974E4FFEB2B2AE0E354 S3150001E7F8BF3F12E5014013E2FF30A013DB3F0215CC S3150001E808F9FFFF1A0020E0E30430A0E3CF3B02E55D S3150001E818013CA0E3CF3B02E54100A0E32DE5FFEB78 S3150001E8280430A0E12B2AE0E3BF1F12E5010011E342 S3150001E838FF10A013DB1F0215BF2F12E5013083124B S3150001E848100012E32B2AE013DF2F121500208D1575 S3150001E85884109FE500209D150020E0E3090053E39D S3150001E868BF1202E5EEFFFFDA70309FE5000093E57F S3150001E8780030A0E32B2AE0E3BF1F12E5010011E3F4 S3150001E8880500000A58109FE50310D1E7013083E21D S3150001E898000053E1DB1F02E5090000AA2B2AE0E389 S3150001E8A8BF1F12E5100011E3DF2F121504208D1585 S3150001E8B824109FE504209D150020E0E3BF1202E520 S3150001E8C8EBFFFFEA012CA0E30030E0E3CB2B03E5E5 S3150001E8D808D08DE21040BDE81EFF2FE1010000A51A S3150001E8E8CCCA2000CCC82000F74F2DE948519FE536 S3150001E8F848419FE5192EA0E34410A0E30070A0E16A S3150001E9080500A0E1CB0700EB013B85E20060A0E32F S3150001E918143084E5011BA0E36430A0E3200085E2FE S3150001E9280C3084E5345084E5386084E51860C4E524 S3150001E9380060C4E537E4FFEB0030E0E30420A0E320 S3150001E948CF2B03E56100A0E3E2E4FFEB203085E28B S3150001E95801CBA0E30680A0E10690A0E103B0A0E107 S3150001E9682B2AE0E3FB2E12E50C2062E0020059E1B6 S3150001E9780290A0B12B0AE0E3FB2E10E50C2062E021 S3150001E988022BA0E1020552E31E00009A025083E21F S3150001E99805E06BE0010B5EE3FF5F43C2D020D3E1E4 S3150001E9A8D110D3E102A04CE2013BA0C3025045C2FB S3150001E9B8EF5E00C5EB3E00C500005AE3FFCF8CD2DF S3150001E9C80100A0E302A08CD206008DE8F9FEFFEB58 S3150001E9D80100A0E3F7FEFFEB04209DE560309FE50B S3150001E9E80200A0E100109DE50FE0A0E113FF2FE171 S3150001E9F8000050E3026086E20180A0130530A0E121 S3150001EA080AC0A0E1DAFFFFEA7D0E56E3D3FFFFDA7B S3150001EA180230A0E3000057E3DF3E00E524009F052E S3150001EA280910A0010820A001383094057107000BD0 S3150001EA380CD08DE2F04FBDE81EFF2FE1142C20000B S3150001EA48582B200068132000FD231200F0432DE9FE S3150001EA584410A0E314D04DE2192EA0E3AC039FE5C0 S3150001EA68740700EB290700EB1440A0E30100A0E3BB S3150001EA78030700EB0100A0E3010700EB0100A0E397 S3150001EA88FF0600EB0100A0E3FD0600EB014054E29E S3150001EA98F5FFFF1A0A40A0E30000A0E3F80600EB21 S3150001EAA80000A0E3F60600EB0000A0E3F40600EB85 S3150001EAB80000A0E3F20600EB014054E2F5FFFF1A5D S3150001EAC80100A0E3EE0600EB0100A0E3EC0600EB73 S3150001EAD80100A0E3EA0600EB0100A0E3E80600EB6B S3150001EAE80100A0E3E60600EB0100A0E3E40600EB63 S3150001EAF80100A0E3E20600EB0100A0E3E00600EB5B S3150001EB080C339FE50000A0E30350D4E7DC0600EBD5 S3150001EB180000A0E3DA0600EB0000A0E3D80600EB4C S3150001EB280000A0E3D60600EB0870A0E3016015E239 S3150001EB380700000A0100A0E3D10600EB0100A0E3EB S3150001EB48CF0600EB0100A0E3CD0600EB0100A0E330 S3150001EB58060000EA0600A0E1C90600EB0600A0E1EE S3150001EB68C70600EB0600A0E1C50600EB0600A0E11A S3150001EB78C30600EB017057E2A550A0E1EAFFFF1AB0 S3150001EB880100A0E3BE0600EB0100A0E3BC0600EB12 S3150001EB980100A0E3BA0600EB014084E20100A0E30C S3150001EBA8B70600EB0E0054E3D4FFFF1A0A40A0E3B0 S3150001EBB80000A0E3B20600EB0000A0E3B00600EBFC S3150001EBC80000A0E3AE0600EB0000A0E3AC0600EBF4 S3150001EBD8014054E2F5FFFF1A0A50A0E30100A0E341 S3150001EBE8A70600EB0100A0E3A50600EB0100A0E3E0 S3150001EBF8A30600EB0100A0E3A10600EB015055E2D4 S3150001EC08F5FFFF1A0C329FE5006093E5036086E283 S3150001EC1804129FE50620A0E100029FE5006083E556 S3150001EC28900600EB0207A0E32DE4FFEB63E3FFEB9D S3150001EC380030E0E30420A0E3CB2B03E58000A0E34A S3150001EC4824E4FFEBD8419FE5C0319FE5143084E504 S3150001EC586430A0E30C3084E50030A0E30030C4E55D S3150001EC68C0219FE50030E0E3BF2203E5C33B13E57E S3150001EC78020513E35F00000A2B3AE0E3BF2F13E511 S3150001EC88010012E30020A013DB2F0315BF3F13E594 S3150001EC98100013E3F1FFFF0A2B3AE0E3DF9F13E5C8 S3150001ECA80870A0E3FF9009E28080A0E3090008E06C S3150001ECB840FEFFEB000050E30300000A084094E51C S3150001ECC8050054E30400000A120000EA017057E245 S3150001ECD8A880A0E1F4FFFF1AE0FFFFEA2C019FE5F7 S3150001ECE844119FE50420A0E1A70600EB007050E25D S3150001ECF80800001A14019FE54410A0E32020A0E3B0 S3150001ED08015085E2CB0600EB310055E31B00001AE2 S3150001ED1818019FE5170000EA14019FE50410A0E118 S3150001ED280520A0E1B30600EB0E308DE200308DE53B S3150001ED38D8109FE5022044E20D308DE2F4009FE5EC S3150001ED4817E8FFEBF0309FE50D10DDE50320D4E76A S3150001ED58020051E10400001A013083E20E20DDE5CC S3150001ED680330D4E7030052E10100000ACC009FE515 S3150001ED78000000EAC8009FE5460600EB200000EA0D S3150001ED88000056E3A9FFFFDA0420A0E30030E0E320 S3150001ED98CB2B03E58100A0E3CEE3FFEBFF20A0E345 S3150001EDA82B3AE0E3DB2F03E504E3FFEB0700A0E1E1 S3150001EDB82B3AE0E3BF2F13E5010012E30500000A31 S3150001EDC858209FE50220D0E7010080E2060050E1C5 S3150001EDD8DB2F03E595FFFFCA2B3AE0E3BF2F13E5C7 S3150001EDE8100012E3DF3F1315FF3003120F30CD1564 S3150001EDF80F30DD15EDFFFFEA48009FE50510A0E19C S3150001EE087C0600EB14D08DE2F043BDE81EFF2FE12E S3150001EE18142C20007F0D1200CCCA2000CCC820007B S3150001EE28342F2000582B2000010000A58D0D12005B S3150001EE387C2312003B231200FFFF0000122C200046 S3150001EE48652312007123120093231200F0412DE964 S3150001EE580080A0E10170A0E12C0600EB2840A0E3A8 S3150001EE680100A0E3060600EB014054E2FBFFFF1A8E S3150001EE780A40A0E30000A0E3010600EB014054E2CA S3150001EE88FBFFFF1A070054E10100A0E30E0000AAE8 S3150001EE98FB0500EB0100A0E3F90500EB0000A0E388 S3150001EEA8F70500EB0450D8E70860A0E3010015E276 S3150001EEB80100A013F20500EB016056E2A550A0E19E S3150001EEC8F9FFFF1A014084E2EDFFFFEAEC0500EBCA S3150001EED80A40A0E30000A0E3E90500EB014054E283 S3150001EEE8FBFFFF1A0840A0E30100A0E3E40500EBDD S3150001EEF8014054E2FBFFFF1A1840A0E30100A0E31A S3150001EF08DF0500EB014054E2FBFFFF1A10309FE5D5 S3150001EF18002093E5012082E2002083E5F041BDE867 S3150001EF281EFF2FE1CCCA200073402DE90540A0E35E S3150001EF380420A0E164109FE50D00A0E1C90500EBDE S3150001EF480050E0E30460A0E3E000A0E361E3FFEB27 S3150001EF58CB6B05E5C800A0E32D0600EB0207A0E38D S3150001EF685FE3FFEB95E2FFEBCF6B05E56100A0E3FD S3150001EF7858E3FFEBC800A0E3250600EB0D00A0E16E S3150001EF880410A0E1B0FFFFEB15FEFFEB0000A0E3C4 S3150001EF9854FEFFEB08D08DE27040BDE81EFF2FE15D S3150001EFA8920D1200F0432DE90460A0E30040E0E36E S3150001EFB814D04DE2CB6B04E5E000A0E30190A0E19B S3150001EFC844E3FFEBC800A0E3110600EB0207A0E348 S3150001EFD843E3FFEB79E2FFEBCF6B04E56100A0E3C6 S3150001EFE83CE3FFEBC800A0E3090600EB0620A0E11D S3150001EFF828139FE50C008DE29A0500EB20439FE557 S3150001F0080C008DE20610A0E18FFFFFEBF4FDFFEB8C S3150001F0180100A0E333FEFFEB383094E5000053E32B S3150001F0280450A0E1FC029F053000000A343094E543 S3150001F038F4029FE50010D3E50120D3E50230D3E5BC S3150001F048EC0500EBE4029FE5920500EB0E30A0E328 S3150001F0580C30CDE5343094E50030D3E50E708DE201 S3150001F0680D30CDE50F808DE20C308DE20220A0E354 S3150001F0780310A0E1B8029FE50730A0E100808DE505 S3150001F08847E7FFEB0610A0E10C008DE26EFFFFEBF0 S3150001F098D3FDFFEB0100A0E312FEFFEB386094E518 S3150001F0A8030056E38C029F150610A0112A00001AC8 S3150001F0B800808DE50120A0E3341094E50730A0E136 S3150001F0C86C029FE536E7FFEB343094E50E10DDE57B S3150001F0D80120D3E5020051E10300001A0F10DDE516 S3150001F0E80220D3E5020051E10200000A48029FE529 S3150001F0F8680500EB860000EA0D10DDE50020D3E582 S3150001F108020051E10200000A30029FE5B90500EB51 S3150001F1187F0000EA0120A0E30C108DE20B30A0E38A S3150001F1280C30CDE508029FE5023081E000708DE5DF S3150001F1381BE7FFEB0610A0E10C008DE242FFFFEB97 S3150001F148A7FDFFEB0100A0E3E6FDFFEB381094E510 S3150001F1580A0051E30200000AE4019FE5A50500EB58 S3150001F1686B0000EA00808DE50820A0E3341094E5E1 S3150001F1780730A0E1B8019FE509E7FFEB343094E5D4 S3150001F1880EC0DDE50820D3E502005CE10F10DDE5E0 S3150001F1980930D3E50100001A030051E10300000A12 S3150001F1A8A0019FE50C1481E0022483E0910500EBA0 S3150001F1B8343095E506C0D3E50720D3E50CC8A0E1B0 S3150001F1C802CC8CE00520D3E502C48CE00220D3E50D S3150001F1D80300D3E50228A0E1002C82E00100D3E573 S3150001F1E80410D3E50030D3E5002482E0032082E051 S3150001F1F854019FE501108CE07E0500EB4C019FE56B S3150001F208240500EB0830A0E30C30CDE5019089E236 S3150001F2180040A0E3090054E10200001A30019FE50D S3150001F2281C0500EBFF40A0E30CC08DE20E708DE2D9 S3150001F2380F808DE20C10A0E10730A0E10220A0E3C7 S3150001F248EC009FE500808DE50D40CDE5D4E6FFEBAA S3150001F2580C008DE20410A0E3FBFEFFEB60FDFFEB63 S3150001F2680100A0E39FFDFFEB383095E5060053E367 S3150001F278AC609FE5DC009F159CFFFF1A00808DE5B9 S3150001F2880420A0E3341096E50730A0E1A0009FE52D S3150001F298C3E6FFEB343096E50EC0DDE50420D3E581 S3150001F2A802005CE10F10DDE50530D3E50100001A27 S3150001F2B8030051E10300000A88009FE50C1481E070 S3150001F2C8022483E04B0500EB340095E502E0D0E526 S3150001F2D80330D0E50EE8A0E103EC8EE00130D0E57D S3150001F2E80020D0E503E48EE004C0D0E50530D0E582 S3150001F2F80410A0E160009FE502208EE00C3483E053 S3150001F3083C0500EBFF0054E301408412FF40041260 S3150001F318BFFFFF1A14D08DE2F043BDE81EFF2FE1AF S3150001F328970D1200582B2000B8231200CD23120086 S3150001F33806241200FFFF00001624120038241200CA S3150001F3485B2412008C241200AF241200E52412005B S3150001F35802251200212512003B2512006225120002 S3150001F3680F10A0E30EFFFFEA7F10A0E30CFFFFEAF0 S3150001F378F8402DE90060A0E10240A0E10350A0E1B8 S3150001F3882F70A0E3000056E300005713120000DABD S3150001F398012047E2072022E20400A0E10510A0E1CE S3150001F3A8920400EB003096E5010000E2830080E15B S3150001F3B8000086E5072027E20400A0E10510A0E188 S3150001F3C88A0400EB043096E5010000E2830080E13F S3150001F3D8040086E5027047E2E9FFFFEAF840BDE866 S3150001F3E81EFF2FE10030A0E3003080E5043080E500 S3150001F3F81EFF2FE170002DE900C090E5044090E55D S3150001F4080020A0E30030A0E31700A0E3035020E2A8 S3150001F4183C65A0E13455A0E1022092E0016006E2D4 S3150001F428062082E10330A3E0022092E00330A3E044 S3150001F438015005E2010050E2052082E1F2FFFF2AB0 S3150001F4480C0081E87000BDE81EFF2FE1003090E551 S3150001F45870002DE9E8409FE500C0A0E10F0003E236 S3150001F4685440A0E12352A0E1D8009FE50F5005E2E0 S3150001F4785055A0E1D0609FE52304A0E10F0000E20A S3150001F4885600A0E1085005E2040000E2104004E23B S3150001F498000085E1040080E1B0509FE52346A0E124 S3150001F4A80F4004E25544A0E1024004E2040080E171 S3150001F4B89C509FE52348A0E10F4004E25544A0E192 S3150001F4C8014004E2040080E188409FE53400A0E1A0 S3150001F4D804609CE580509FE580409FE5055006E065 S3150001F4E8044003E0044025E0010000E2000052E385 S3150001F4F80020A00301200012000051E30410A0011E S3150001F50801108413024021E0244824E0244424E025 S3150001F518244224E048209FE50F4004E25244A0E13A S3150001F528014004E2866084E1033026E0066023E0B8 S3150001F538033026E004608CE500308CE57000BDE8F8 S3150001F5481EFF2FE1C0220F00C0C90600B0C8030084 S3150001F55858E4010038D900000AE857EC0408870086 S3150001F5685CCE290096690000F0412DE90040A0E330 S3150001F5780070A0E10180A0E10260A0E10450A0E1D1 S3150001F5885814A0E10700A0E1011001E20620A0E15C S3150001F598ADFFFFEB100485E1014084E2080054E366 S3150001F5A8FF5000E2F5FFFF1A0500A0E1F041BDE8B2 S3150001F5B81EFF2FE1F8432DE90040A0E30080A0E1FA S3150001F5C80190A0E10270A0E10450A0E1186025E2D3 S3150001F5D83916A0E10800A0E1011001E20720A0E127 S3150001F5E899FFFFEB015085E2200055E3104684E1BF S3150001F5F8F5FFFF1A0400A0E1F843BDE81EFF2FE15D S3150001F6082024A0E1FF34C0E3FF2CC2E3FF3CC3E39F S3150001F618033482E16338A0E1011051E20600003AA1 S3150001F6282328A0E1232922E0A32922E0A32A22E014 S3150001F638822FA0E1A33082E1F6FFFFEA2324A0E1AD S3150001F648FF04C3E3FF2CC2E3FF0CC0E3000482E11D S3150001F6586008A0E11EFF2FE11C309FE50020A0E312 S3150001F668020050E10000C3E58000A01101008013EB S3150001F678042083E50100C3E51EFF2FE1DCCA200053 S3150001F68854109FE5043091E5033080E0043081E5AC S3150001F6980020D1E50130D1E5010050E20B00003A26 S3150001F6A822C322E0A220A0E10C2382E1A3C1A0E1AA S3150001F6B823C12CE00CC023E0A3C32CE0A330A0E1B6 S3150001F6C88C3383E1FF2002E2FF3003E2F1FFFFEA18 S3150001F6D80020C1E50130C1E51EFF2FE1DCCA20008B S3150001F6E804309FE5040093E51EFF2FE1DCCA2000E4 S3150001F6F830209FE50030D2E52301A0E1831DA0E17A S3150001F708020000E2A10F80E1043003E2030080E178 S3150001F7180120D2E5070060E2FF0000E25200A0E105 S3150001F728010000E21EFF2FE1DCCA2000F8432DE9A3 S3150001F738DC409FE50180A0E10070A0E1F30300EB46 S3150001F748001094E5CC309FE500C0A0E3012083E0DA S3150001F7580050E0E301C0C2E502C0C2E503C0C2E54C S3150001F7680450C2E50550C2E50650C2E507C0C2E528 S3150001F778082081E2002084E50250C3E708005CE125 S3150001F788130000AA001094E50C50D7E7022081E285 S3150001F798022083E00860A0E3019015E20000E0E39F S3150001F7A80090A013019042150000C2150100420500 S3150001F7B80090C205016056E2A550A0E1022082E24E S3150001F7C8F4FFFF1A101081E2001084E501C08CE2F3 S3150001F7D8E9FFFFEA000094E50010E0E3003083E06A S3150001F7E80020A0E30110C3E50220C3E50310C3E529 S3150001F7F80410C3E50510C3E50620C3E50720C3E5E4 S3150001F8080820C3E5090080E2000084E5F843BDE865 S3150001F8181EFF2FE1CCCA2000CCC8200004402DE5EC S3150001F8280030A0E3012083E207C002E20C40D0E7E2 S3150001F83803C0D0E7ACC1A0E184C28CE1080052E361 S3150001F84803C0C1E70230A011F5FFFF1A04409DE489 S3150001F8581EFF2FE114359FE5F04F2DE90120A0E3A6 S3150001F868002083E508359FE50040A0E3004083E5D5 S3150001F87800359FE55CD04DE20060A0E1F8249FE5E4 S3150001F888000093E50150A0E14410A0E3E90300EB71 S3150001F8980410A0E10A20A0E340008DE2E50300EB95 S3150001F8A84C008DE2D4149FE50A20A0E36D0300EB1A S3150001F8B8040056E138408DE53C408DE54C008D024B S3150001F8C80510A0010820A0036603000B4C008DE279 S3150001F8D840108DE2D0FFFFEB40208DE20210A0E13F S3150001F8E849308DE20820A0E300308DE590049FE5BC S3150001F8F8023081E02AE5FFEB4CC08DE20820A0E347 S3150001F90855308DE20C10A0E178449FE500308DE575 S3150001F9186C049FE502308CE021E5FFEB0070A0E363 S3150001F9280F30A0E34410A0E34020A0E358049FE56C S3150001F93858649FE53630CDE5BE0300EB007084E5DB S3150001F948720300EB009094E5093086E0099089E29C S3150001F9580050E0E30920A0E10610A0E130049FE58C S3150001F9680170C3E50270C3E50370C3E50450C3E53E S3150001F9780550C3E50650C3E50770C3E50850C3E55E S3150001F988009084E5370300EB40008DE20A10A0E3FE S3150001F99865FFFFEB00C094E50610A0E10C20A0E18D S3150001F9A8F0039FE52CC08DE52E0300EB4C008DE29C S3150001F9B80A10A0E35CFFFFEB00A094E50610A0E1A6 S3150001F9C80A20A0E1D0039FE5260300EB38008DE26B S3150001F9D80810A0E354FFFFEB00B094E50610A0E180 S3150001F9E80B20A0E1B4039FE51E0300EB0207A0E389 S3150001F9F8BBE0FFEBF1DFFFEB0130A0E3CF3B05E511 S3150001FA080030E0E3012CA0E3CB2B03E50420A0E3BF S3150001FA18CB2B03E5A100A0E3AEE0FFEB80439FE516 S3150001FA2864339FE53C3084E56430A0E30C3084E51B S3150001FA380030A0E30030C4E568239FE50030E0E329 S3150001FA48BF2203E5C33B13E5020513E3BA00000A27 S3150001FA582B3AE0E3BF2F13E5010012E30020A013C0 S3150001FA68DB2F0315BF3F13E5100013E3F1FFFF0A70 S3150001FA782B3AE0E3DF0F13E52C339FE50F0000E295 S3150001FA880FE0A0E113FF2FE1000050E3E9FFFF0AB1 S3150001FA9818139FE5D82BD1E50A0052E3088094E5AF S3150001FAA83900000A0C0052E33B00000A810052E3C8 S3150001FAB83E00000A880052E30700001A0030E0E31E S3150001FAC8012CA0E3CF2B03E50B60A0E10840A0E3DE S3150001FAD838508DE2C4329FE53C0000EA050052E346 S3150001FAE81000001ADA0BD1E5D93BD1E500008DE506 S3150001FAF8DB0BD1E504008DE5DC0BD1E508008DE5CE S3150001FB08DD0BD1E50C008DE5DE0BD1E510008DE5A9 S3150001FB18DF0BD1E514008DE5E01BD1E590029FE5E9 S3150001FB2818108DE5140000EA000052E30200001ADD S3150001FB38010058E30240A0012100000ADA0BD1E5D1 S3150001FB48D93BD1E500008DE5DB0BD1E504008DE558 S3150001FB58DC0BD1E508008DE5DD0BD1E50C008DE563 S3150001FB68DE0BD1E510008DE5DF0BD1E514008DE53F S3150001FB78E01BD1E53C029FE518108DE50810A0E1D0 S3150001FB881C0300EB0040A0E30D0000EA0960A0E1B8 S3150001FB980140A0E336508DE20B0000EA2C609DE59A S3150001FBA80A40A0E340508DE2E8319FE5070000EAEC S3150001FBB80A60A0E10A40A0E34C508DE2D8319FE5E6 S3150001FBC8020000EA0450A0E10460A0E1C0319FE50B S3150001FBD8FA0F57E3E0019F055800000A000056E3B3 S3150001FBE8017087E2040000CA80319FE5003093E581 S3150001FBF8000053E32D00001A4A0000EAA200A0E320 S3150001FC0824308DE533E0FFEB0010A0E32B2AE0E377 S3150001FC18DB1F02E528108DE568DFFFEB28109DE55F S3150001FC2824309DE50120A0E10100A0E12BCAE0E313 S3150001FC38BFEF1CE510001EE3DFCF1C15FFC00C1239 S3150001FC4837C0CD1537C0DD152BCAE0E3BFCF1CE59C S3150001FC5801001CE31000000A140051E3011081D2CF S3150001FC68020000DA060050E1020000BA012082E231 S3150001FC7800C0A0E3040000EA000052E300C0D3E795 S3150001FC880020A013010080120120A0032BEAE0E363 S3150001FC98040052E3DBCF0EE5D2FFFFCA00C0E0E362 S3150001FCA8C3CB1CE502051CE3DFFFFF1ACDFFFFEA04 S3150001FCB80130A0E300308DE5E4309FE5C8009FE5FB S3150001FCC80810A0E10020A0E3203093E5EC609FE551 S3150001FCD80FE0A0E116FF2FE1000055E30B00000A33 S3150001FCE80410A0E10500A0E1BBE6FFEB0410A0E1CA S3150001FCF8D30200EB0020A0E30030A0E100208DE54F S3150001FD080500A0E10410A0E10FE0A0E116FF2FE134 S3150001FD185C309FE5002093E55C309FE5030052E1E6 S3150001FD289C009FC5050000CA4410A0E34020A0E33B S3150001FD3854009FE5BF0200EB30FFFFEA84009FE510 S3150001FD48540200EB80009FE50710A0E1A90200EB31 S3150001FD580030E0E30120A0E3CB2B03E5012CA0E36F S3150001FD68CB2B03E55CD08DE2F04FBDE81EFF2FE1FA S3150001FD7864002000142B200060002000B80B00004E S3150001FD889B0D120012E00000CCCA2000EC372000BF S3150001FD98CCC820006C482000764820002A4920005B S3150001FDA8DE4920009C2B2000010000A5901B2000A5 S3150001FDB8142C2000AD261200F2261200981D1200FE S3150001FDC8140820006A141200AF1D12009D191200B2 S3150001FDD8F0472DE90090A0E101A0A0E14B0200EB5C S3150001FDE8C0309FE5C0209FE5000093E50FC0E0E322 S3150001FDF8001082E001C0C1E50F40A0E300C0A0E306 S3150001FE0802C0C1E50340C1E5041080E2001083E5A4 S3150001FE1801C0C2E70A005CE1160000AA007093E57A S3150001FE280C80D9E7016087E2111087E20650A0E14C S3150001FE380040A0E3030008E2000054E1014084E227 S3150001FE480F00A0030000A013040054E30500C2E755 S3150001FE58015085E2F6FFFF1A046086E2010056E1C9 S3150001FE682881A0E1F0FFFF1A107087E2007083E590 S3150001FE7801C08CE2E6FFFFEA000093E50010A0E36B S3150001FE88002082E00FC0E0E30110C2E50210C2E5DE S3150001FE9803C0C2E50410C2E5050080E2000083E55F S3150001FEA8F047BDE81EFF2FE1CCCA2000CCC82000D0 S3150001FEB8F0402DE914D04DE20140A0E10050A0E147 S3150001FEC8C2FFFFEB38319FE5A400A0E3006093E58C S3150001FED80070A0E37FDFFFEB2B3AE0E3DB7F03E56E S3150001FEE8B6DEFFEB0730A0E12B2AE0E3BF1F12E5E0 S3150001FEF8010011E30010A013DB1F0215BF2F12E545 S3150001FF0801308312100012E32B2AE013DF2F12159A S3150001FF1808208D15EC109FE508209D150020E0E3CB S3150001FF28090053E3BF1202E5EEFFFFDA01C0A0E3C1 S3150001FF380030A0E32B2AE0E3BF2F12E5010012E30C S3150001FF480F00000AC0209FE50320D2E700005CE30A S3150001FF580F100202022281010F10C21322228111FF S3150001FF68FF20020201308302FF0052E3FE20A003B4 S3150001FF782B1AE0E3060053E1DB2F01E501C02CE271 S3150001FF88090000AA2B2AE0E3BF1F12E5100011E3BE S3150001FF98DF2F12150C208D1568109FE50C209D1575 S3150001FFA80020E0E3BF1202E5E1FFFFEA5C309FE5CE S3150001FFB80030D3E5000053E30030E0130120A0131D S3150001FFC8CF2B031548309FE5003093E5000053E336 S3150001FFD80800000A0130A0E30020A0E300308DE507 S3150001FFE80500A0E10410A0E10230A0E124C09FE5CC S3150001FFF80FE0A0E11CFF2FE114D08DE2F040BDE82F S315000200081EFF2FE1CCCA2000010000A5CCC82000A3 S315000200180C2B2000640020001408200073402DE9F0 S315000200280060A0E1A300A0E32ADFFFEBD4209FE54E S315000200380030A0E3746082E56C3082E54030C2E5A8 S315000200480340A0E10250A0E1BC109FE50020E0E3D6 S31500020058BF1202E5C32B12E5020512E32500000AC8 S315000200682B2AE0E3BF1F12E5010011E30010A013DB S31500020078DB1F0215BF2F12E5100012E3F1FFFF0A7C S31500020088010A54E31B0000AA2B2AE0E3000053E30B S31500020098014084E2DF0F12E50130A003E9FFFF0AFF S315000200A80F0000E264309FE50FE0A0E113FF2FE1A5 S315000200B8000050E30030A001E2FFFF0A50309FE53E S315000200C8003093E5000053E38421A0E10700000A0B S315000200D80030A0E300308DE50600A0E16C1095E53E S315000200E8503095E52CC09FE50FE0A0E11CFF2FE1FB S315000200F86C0095E5000000EA0000A0E308D08DE256 S315000201087040BDE81EFF2FE19C2B2000010000A5D0 S31500020118201F2000640020001408200030402DE92A S315000201280A30A0E334D04DE21C30CDE50010A0E33E S315000201380C30A0E30920A0E324008DE22030CDE5AF S31500020148BC0100EB7E30E0E32430CDE550319FE57B S315000201584410A0E34C219FE5000093E548419FE542 S31500020168B40100EB0030A0E3003084E50050E0E380 S3150002017812DEFFEB0430A0E3CB3B05E5E000A0E38B S31500020188D4DEFFEBC800A0E3A10100EB0207A0E35F S31500020198D3DEFFEBA400A0E3CEDEFFEBC800A0E3AC S315000201A89B0100EB0130A0E3CF3B05E5002094E577 S315000201B8F8309FE5030052E1020000DAF0009FE5FD S315000201C8340100EB300000EA0030E0E3C33B13E5FC S315000201D8020513E32C00000A1C008DE20110A0E3BD S315000201E832FFFFEBCC009FE58BFFFFEB000050E3ED S315000201F82100000A20008DE20110A0E32BFFFFEB8D S31500020208B0009FE584FFFFEB0A0050E31A00001ACC S315000202180820A0E39C109FE525008DE2110100EB62 S3150002022824008DE20910A0E320FFFFEB84009FE57E S3150002023879FFFFEB0A0050E30F00001A78009FE5EA S31500020248EBCDD0E5E81DD0E5E92DD0E5EA3DD0E5D0 S3150002025800C08DE5ECCDD0E504C08DE5EDCDD0E549 S3150002026808C08DE5EECDD0E50CC08DE5EF0DD0E5E5 S3150002027810008DE544009FE55E0100EB40209FE5F6 S315000202880030E0E3BF2203E5C7FFFFEA0120A0E34F S315000202980030E0E3CB2B03E534D08DE23040BDE8F5 S315000202A81EFF2FE160002000D80B0000142B20004F S315000202B8B80B00006A141200FC392000142C200026 S315000202C83C271200010000A504402DE50030A0E3FA S315000202D8020053E10A0000AA004090E5A4C0A0E18A S315000202E8044021E0010014E30840901500C080E5AF S315000202F804C02C1000C08015A110A0E1013083E2D1 S31500020308F2FFFFEA04409DE41EFF2FE1142090E568 S315000203180C3090E5033002E0003080E51EFF2FE145 S315000203280E0080E900309DE5103080E50030E0E3FC S315000203381311E0E1141080E5F3FFFFEA102090E5BF S31500020348003090E5140090E5032022E0000002E068 S315000203581EFF2FE102B471464908490009564900B1 S315000203688E4402BC7047C04602B471464908490029 S31500020378095C49008E4402BC7047C04603B4714604 S31500020388490840004900095A49008E4403BC70478F S31500020398012051E21EFF2F013600003A010050E10A S315000203A82200009A020011E12300000A0E0211E35C S315000203B88111A0010830A0030130A013010251E304 S315000203C8000051310112A0310332A031FAFFFF3A7F S315000203D8020151E3000051318110A0318330A0316E S315000203E8FAFFFF3A0020A0E3010050E10100402095 S315000203F803208221A10050E1A1004020A3208221EE S31500020408210150E12101402023218221A10150E14D S31500020418A1014020A3218221000050E32332B0111A S315000204282112A011EFFFFF1A0200A0E11EFF2FE121 S315000204380100A0030000A0131EFF2FE1010851E3EB S315000204482118A0211020A0230020A033010C51E37B S315000204582114A02108208222100051E32112A02192 S3150002046804208222040051E303208282A120829082 S315000204783002A0E11EFF2FE1000050E30000E01366 S31500020488590000EA000051E3FAFFFF0A03402DE98A S31500020498BEFFFFEB0640BDE8920003E0031041E011 S315000204A81EFF2FE1000051E34300000A01C020E0CD S315000204B800106142012051E22700000A0030B0E133 S315000204C800306042010053E12600009A020011E161 S315000204D82800000A0E0211E38111A0010820A003D8 S315000204E80120A013010251E3030051310112A03188 S315000204F80222A031FAFFFF3A020151E30300513109 S315000205088110A0318220A031FAFFFF3A0000A0E351 S31500020518010053E10130432002008021A10053E18A S31500020528A1304320A2008021210153E12131432039 S3150002053822018021A10153E1A1314320A201802198 S31500020548000053E32222B0112112A011EFFFFF1A75 S3150002055800005CE3000060421EFF2FE100003CE160 S31500020568000060421EFF2FE10000A033CC0FA0015D S31500020578010080031EFF2FE1010851E32118A02183 S315000205881020A0230020A033010C51E32114A0213E S3150002059808208222100051E32112A021042082227F S315000205A8040051E303208282A120829000005CE3CA S315000205B83302A0E1000060421EFF2FE1000050E373 S315000205C80201E0C30201A0B3070000EA000051E3FA S315000205D8F9FFFF0A03402DE9B3FFFFEB0640BDE82A S315000205E8920003E0031041E01EFF2FE11EFF2FE1F8 S315000205F8203052E220C062E23002A0413103A0510B S31500020608110C80413112A0E11EFF2FE1203052E287 S3150002061820C062E21112A0411013A051301C814180 S315000206281002A0E11EFF2FE1030051E10000E033B2 S315000206380100A0831EFF2F11020050E10000E033E3 S315000206480100A0830000A0031EFF2FE100000000A6 S315000206587847C0467EFCFFEA7847C04621DDFFEAB6 S315000206687847C0469EDDFFEA00C09FE51CFF2FE1E2 S31500020678F56F11007847C0462AFAFFEA7847C0465E S3150002068822F5FFEA00C09FE51CFF2FE1274911006A S315000206987847C04633FBFFEA00C09FE51CFF2FE1FF S315000206A80549110000C09FE51CFF2FE15D4A1100B4 S315000206B800C09FE51CFF2FE1456F11007847C04631 S315000206C836DDFFEA7847C04678F1FFEA7847C04642 S315000206D8DDF8FFEA7847C046B8DCFFEA00C09FE5C6 S315000206E81CFF2FE18D7611007847C0462EE4FFEAFB S315000206F87847C04677DDFFEA7847C046F9F4FFEA4D S315000207087847C046EFF0FFEA7847C046BEFFFFEAE1 S3150002071800C09FE51CFF2FE1ED48110000C09FE5D0 S315000207281CFF2FE1916F11007847C0464CE9FFEA9A S315000207387847C04659DDFFEA7847C04685F4FFEA9E S315000207487847C04656FFFFEA7847C0464CFFFFEA9D S315000207587847C046B3FFFFEA7847C046DEE2FFEABB S3150002076800C09FE51CFF2FE1E16B11007847C046E8 S3150002077895FFFFEA7847C04637E0FFEA7847C04662 S3150002078806F5FFEA7847C046F6F1FFEA00C09FE59C S315000207981CFF2FE12570110000C09FE51CFF2FE109 S315000207A85B70110000C09FE51CFF2FE1DD491100B7 S315000207B87847C04697F2FFEA7847C046ADE1FFEAB6 S315000207C800C09FE51CFF2FE1516C11007847C04617 S315000207D8EEFEFFEA7847C04600E5FFEA00C09FE55D S315000207E81CFF2FE1156C11007847C04692F6FFEA06 S315000207F87847C046C9F4FFEA00C09FE51CFF2FE10F S31500020808914911007847C04673E0FFEA7847C04627 S315000208185CE8FFEA00C09FE51CFF2FE1016E1100AC S315000208287847C046C5F4FFEA7847C046CAE0FFEAF9 S315000208387847C046CEE3FFEA00C09FE51CFF2FE1DA S315000208480D70110000C09FE51CFF2FE1EF6B110030 S315000208587847C0469FF5FFEA7847C04663FFFFEA36 S315000208687847C0462CFEFFEA00C09FE51CFF2FE131 S315000208782D6C11007847C0464CEAFFEA7847C04615 S31500020888B6FAFFEA000000000000000000000000BF S315000208980000000000000000000000000000000048 S315000208A80000000000000000000000000000000038 S315000208B80000000000000000000000000000000028 S315000208C80000000000000000000000000000000018 S315000208D8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF18 S315000208E8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF08 S315000208F8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8 S31500020908FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE7 S31500020918FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD7 S31500020928FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC7 S3150002093801000000010000000100000001000000A3 S315000209480100000001000000010000000100000093 S315000209580100000001000000010000000100000083 S315000209680100000001000000010000000100000073 S315000209780100000001000000010000000100000063 S315000209880100000001000000010000000100000053 S31500020998FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF57 S315000209A8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF47 S315000209B80100000001000000010000000100000023 S315000209C80100000001000000010000000100000013 S315000209D80100000001000000010000000100000003 S315000209E801000000010000000100000001000000F3 S315000209F8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7 S31500020A08FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE6 S31500020A18FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD6 S31500020A28FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC6 S31500020A3801000000010000000100000001000000A2 S31500020A480100000001000000010000000100000092 S31500020A580100000001000000010000000100000082 S31500020A680100000001000000010000000100000072 S31500020A78FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF76 S31500020A88FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF66 S31500020A980100000001000000010000000100000042 S31500020AA80100000001000000010000000100000032 S31500020AB80100000001000000010000000100000022 S31500020AC80100000001000000010000000100000012 S31500020AD80100000001000000010000000100000002 S31500020AE801000000010000000100000001000000F2 S31500020AF8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6 S31500020B08FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE5 S31500020B18FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD5 S31500020B28FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC5 S31500020B38FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB5 S31500020B48FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA5 S31500020B580000000000000001000000000000000084 S31500020B680000000000000000000000000000000075 S31500020B78000000010204080C0E0F303132333435FE S31500020B88363738396162636465666768696A6B6CA9 S31500020B986D6E6F707172737475767778797A0012E2 S31500020BA8011001020000082D2D4D50010001000020 S31500020BB80109024300020100C00009040000010203 S31500020BC80200000524001001042402000524060080 S31500020BD8010524010001070583030800FF09040132 S31500020BE800020A000000070501024000000705820C S31500020BF8024000001A03700072006F0078006D0050 S31500020C08610072006B002E006F0072006700000917 S31500020C180FF00FF00FF00FF000000104007F00073D S31500020C2802020400A4020C02011C00B000003810E3 S31500020C38860000027C000022C1A4D0110052A6013F S31500020C48000001000101000001010001000001008D S31500020C58010100010000010100000100010100007C S31500020C68010100010000010100000100010100016B S31500020C78000001000101000001010001000001005D S31500020C88010100010000010100000100010100014B S31500020C98000001000101000001010001000001013C S31500020CA8000001000101000001010001000001002D S31500020CB8010100010000010100000100010100001C S31500020CC8010100010000010100000100010100010B S31500020CD800000100010100000101000100000101FC S31500020CE800000100010100000101000100000100ED S31500020CF801010001000001010000010001010001DB S31500020D0800000100010100000101000100000100CC S31500020D1801010001000001010000010001010000BB S31500020D2801010001000001010000010001010001AA S31500020D380000010001010000010100010000010399 S31500020D483B0000009320937000000000000000E0C2 S31500020D588000006000F57BFFFFFFFFFFFFFF0780B3 S31500020D6869FFFFFFFFFFFFE68487F3168804004644 S31500020D788E45554D70410450820DE1742038192272 S31500020D880021855ED7050008397305000839730600 S31500020D9800975B031FEC8AF7FF12E0000072616E90 S31500020DA8206F666620656E6421006572726F722C0A S31500020DB820756E6576656E206F63746574212028CA S31500020DC8657874726120626974732129206D617372 S31500020DD86B3D253032780066696E207265636F72E4 S31500020DE8640050726F7445787420004572726F728F S31500020DF8200030313A6E6F74537570700030323A93 S31500020E086E6F745265636F670030333A6F70744E53 S31500020E186F74537570700030663A6E6F496E666FFE S31500020E280031303A646F6E744578697374003131F3 S31500020E383A6C6F636B416761696E0031323A6C6F67 S31500020E48636B65640031333A70726F67457272007C S31500020E5831343A6C6F636B45727200756E6B6E6FE6 S31500020E68776E457272004E6F457272200043726346 S31500020E784F4B004372634661696C21006F666600D8 S31500020E8849736F313536393320446562756720698F S31500020E9873206E6F77202573002564206F6374654F S31500020EA8747320726561642066726F6D20494445C9 S31500020EB84E5449465920726571756573743A0055E0 S31500020EC84944203D20253032685825303268582555 S31500020ED830326858253032685825303268582530FD S31500020EE832685825303268582530326858002564E9 S31500020EF8206F637465747320726561642066726F0D S31500020F086D2053454C45435420726571756573745B S31500020F183A002564206F6374657473207265616490 S31500020F282066726F6D205858582072657175657300 S31500020F38743A00524541442053494E474C45204293 S31500020F484C4F434B2025642072657475726E656436 S31500020F58202564206F63746574733A00736E69663C S31500020F68663A206572726F722C20756E6576656EAA S31500020F78206F6374657421202864697363617264DF S31500020F882065787472612062697473212900256468 S31500020F98206F637465747320726561642066726F6C S31500020FA86D2072656164657220636F6D6D616E6432 S31500020FB83A20257820257820257820257820257836 S31500020FC8202578202578202578202578004E6F411F S31500020FD84649205549443D2573004146493D256900 S31500020FE8205549443D25730041464920427275748D S31500020FF865666F7263696E6720646F6E652E00534D S31500021008454E44005245435600627566666572202F S3150002101873616D706C65733A2025303278202530FD S315000210283278202530327820253032782025303221 S3150002103878202530327820253032782025303278CB S31500021048202E2E2E0074696D6572283173293A2076 S31500021058256420743D256400496E666F3A204E6FFA S315000210682076616C696420746167206465746563BF S315000210787465642E00496E666F3A2054492074617D S3150002108867206973207265777269746561626C6537 S31500021098004572726F723A204964656E74206D69F2 S315000210A8736D617463682100496E666F3A2054490C S315000210B820746167206964656E742069732076619D S315000210C86C696400496E666F3A20544920746167F8 S315000210D820697320726561646F6E6C7900496E6669 S315000210E86F3A2054616720646174613A2025782535 S315000210F83038782C206372633D2578004572726F0A S31500021108723A20435243206D69736D617463682C89 S3150002111820657870656374656420257800496E6673 S315000211286F3A2043524320697320676F6F64004405 S315000211386F6E650053746F707065640054616773EF S315000211482063616E206F6E6C792068617665203443 S315000211583420626974732E005441472049443A2068 S3150002116825782530387825303878202825642900CE S315000211785441472049443A20257825303878202892 S3150002118825642900444F4E45210054616773206344 S31500021198616E206F6E6C792068617665203834201E S315000211A8626974732E0054353578370054353535EF S315000211B83500537461727465642077726974696E56 S315000211C86720257320746167202E2E2E00436C6FCC S315000211D8636B20726174653A20256400496E7661F4 S315000211E86C696420636C6F636B20726174653A2064 S315000211F825640054616720257320777269747465C3 S315000212086E2077697468203078253038782530382A S31500021218780A004572726F722C206E6F20746167AD S31500021228206F722062616420746167004572726F72 S31500021238722072656164696E6720746865207461DC S315000212486700486572652069732074686520706155 S31500021258727469616C20636F6E74656E74002864BB S3150002126862672920253032782025303278202530C9 S3150002127832782025303278202530327820253032CF S315000212887820253032782025303278202530327879 S3150002129820253032782025303278202530327820C1 S315000212A825303278202530327820253032782025AC S315000212B8303278002864626729204D617820626C92 S315000212C86F636B733A202564002D2D2D2D2D2D2D40 S315000212D82D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2E S315000212E82D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D1E S315000212F82D2D004D656D6F727920636F6E74656E64 S31500021308743A003C6D697373696E6720626C6F6329 S315000213186B2025643E00556B6E6F776E20636F6D8A S315000213286D616E643A202530327820253032780095 S315000213385265616465722070617373776F72642097 S3150002134869732077726F6E6700617574683A202533 S315000213583032782530327825303278253032782581 S315000213683032782530327825303278253032782076 S315000213784661696C6564210050617373776F7264A4 S31500021388206661696C65642100C00052656164204B S3150002139873756363657366756C2100556B6E6F773B S315000213A86E206672616D65206C656E6774683A2098 S315000213B825640041757468656E7469636174696F42 S315000213C86E206661696C6564210041757468656E94 S315000213D87469636174696F6E207375636365736696 S315000213E8756C2100617574683A202530327825308B S315000213F832782530327825303278253032782530E1 S3150002140832782530327825303278204661696C6523 S31500021418642C2072656D6F76656420656E747279C8 S315000214282100617574683A20253032782530327881 S3150002143825303278253032782530327825303278A0 S315000214482530327825303278204F4B00537461723A S3150002145874696E672048697461673220736E6F6FAC S31500021468700054726163652066756C6C0053746112 S315000214787274696E67204869746167322073696D90 S31500021488756C6174696F6E004C6F6164696E672072 S31500021498686974616732206D656D6F72792E2E2EBA S315000214A8007C202564207C2025303878207C005357 S315000214B874617274696E672048697461672072651F S315000214C8616465722066616D696C79004C69737432 S315000214D8206964656E74696669657220696E207032 S315000214E8617373776F7264206D6F646500417574FA S315000214F868656E7469636174696E67207573696E6F S3150002150867206E722C617220706169723A004175A9 S315000215187468656E7469636174696E672075736948 S315000215286E67206B65793A0054657374696E672035 S3150002153825642061757468656E7469636174696F80 S315000215486E20617474656D707473004572726F7281 S315000215582C20756E6B6E6F776E2066756E63746976 S315000215686F6E3A20256400436F6E66696775726509 S315000215786420666F722068697461675320726561B8 S3150002158864657200436F6E66696775726564206684 S315000215986F72206869746167312072656164657269 S315000215A800436F6E6669677572656420666F72209E S315000215B86869746167322072656164657200457292 S315000215C8726F722C20756E6B6E6F776E20686974F7 S315000215D861672072656164657220747970653A2064 S315000215E82564006672616D65207265636569766554 S315000215F8643A20256400416C6C20646F6E65005461 S315000216086F53656E645374756666426974206F76A5 S315000216186572666C6F7765642100427566666572E7 S3150002162820636C6561726564202825692062797475 S3150002163865732900252D387320252A44004D6561D6 S31500021648737572696E6720616E74656E6E6120636A S3150002165868617261637465726973746963732C2055 S31500021668706C6561736520776169742E2E2E004D44 S315000216786561737572696E6720636F6D706C6574E8 S31500021688652C2073656E64696E67207265706F7269 S3150002169874206261636B20746F20686F7374004DE7 S315000216A86561737572696E6720484620616E746556 S315000216B86E6E612C20707265737320627574746F16 S315000216C86E20746F2065786974002564206D560053 S315000216D863616E63656C6C65640073696D756C61D4 S315000216E874652074616720286E6F77207479706537 S315000216F82062697473616D706C6573290025783A86 S31500021708202530327820253032782025303278204C S315000217182530327820253032782025303278202537 S3150002172830327820253032780050726F782F524640 S315000217384944206D61726B33205246494420696ED2 S31500021748737472756D656E7400626F6F74726F6D05 S315000217582076657273696F6E20696E666F726D6147 S3150002176874696F6E206170706561727320696E7636 S31500021778616C696400626F6F74726F6D3A20006FF4 S31500021788733A20005374616E642D616C6F6E652026 S315000217986D6F646521204E6F205043206E65636528 S315000217A873736172792E005374617274696E67205D S315000217B87265636F7264696E67005265636F7264FD S315000217C8656420257820257820257800506C617973 S315000217D8696E6700446F6E6520706C6179696E6721 S315000217E80045786974696E67004C46203132352F98 S315000217F831333420426173656C696E653A2025641B S315000218080048462031332E353620426173656C69AD S315000218186E653A202564005369676E616C205374BD S3150002182872656E677468204D6F6465004C46203198 S3150002183832352F313334204669656C64204368613A S315000218486E67653A2025782025782025780048464F S315000218582031332E3536204669656C64204368612B S315000218686E67653A20257820257820257800257325 S315000218783A2030782530347800756E6B6E6F776E45 S3150002188820636F6D6D616E643A0028666D74206E12 S31500021898756C6C290A00286E756C6C29004D697383 S315000218A873696E672F496E76616C69642076657214 S315000218B873696F6E20696E666F726D6174696F6E99 S315000218C80056657273696F6E20696E666F726D6116 S315000218D874696F6E206E6F7420756E6465727374A8 S315000218E86F6F640056657273696F6E20696E666FF4 S315000218F8726D6174696F6E206E6F742061766169AC S315000219086C61626C65002D756E636C65616E002D87 S3150002191873757370656374004650474120696D613B S3150002192867653A206C656761637920696D616765E9 S3150002193820776974686F75742076657273696F6E3D S3150002194820696E666F726D6174696F6E00465047E4 S315000219584120696D616765206275696C7400206F44 S315000219686E2000206174200030783139202D2046FF S3150002197872616D653A202530332E337800777269A5 S315000219887465202D20616464723A2025782C2064BF S315000219986174613A20257800556E657870656374BE S315000219A865643A20737A3A25752C20446174613A43 S315000219B82530332E33782C2053746174653A257595 S315000219C82C20436F756E743A25750049563A2025C0 S315000219D830332E33780052656164204E623A2025F0 S315000219E8752C20416464723A202575004379636C2C S315000219F865733A2025752C204672616D65204C6503 S31500021A086E6774683A2025752C2054696D653A20EC S31500021A1825750021212120637263206D69736D612A S31500021A287463683A206578706563746564202578FE S31500021A382062757420676F74202578202121210081 S31500021A4873657474696E67207570206C656769635F S31500021A582063617264004D494D2032353620636138 S31500021A68726420666F756E642C2072656164696E95 S31500021A78672063617264202E2E2E004D494D203157 S31500021A88303234206361726420666F756E642C206E S31500021A9872656164696E672063617264202E2E2EF8 S31500021AA800556E6B6E6F776E206361726420666F87 S31500021AB8726D61743A202578006F70657261746977 S31500021AC86F6E2061626F727465640043617264208E S31500021AD8726561642C2075736520276866206C65BB S31500021AE8676963206465636F646527206F720027E0 S31500021AF8646174612068657873616D706C657320C2 S31500021B0825642720746F2076696577207265737558 S31500021B186C7473004572726F723A2063616E206E3E S31500021B286F7420777269746520746F203078253057 S31500021B38332E3378206F6E204D494D2032353600CC S31500021B484D494D20323536206361726420666F75C1 S31500021B586E642C2077726974696E67203078253036 S31500021B68322E3278202D2030782530322E327820C7 S31500021B782E2E2E004572726F723A2063616E206EA7 S31500021B886F7420777269746520746F2030782530F7 S31500021B98332E3378206F6E204D494D203130323442 S31500021BA8004D494D2031303234206361726420661B S31500021BB86F756E642C2077726974696E6720307847 S31500021BC82530332E3378202D2030782530332E33A6 S31500021BD878202E2E2E004E6F206F7220756E6B6E39 S31500021BE86F776E206361726420666F756E642C204F S31500021BF861626F7274696E67006F7065726174698B S31500021C086F6E2061626F7274656420402030782599 S31500021C1830332E337800777269746520737563637F S31500021C2865737366756C00693D25752C206B65793D S31500021C3820307825332E3378005374617274696EB6 S31500021C4867204C6567696320656D756C61746F7290 S31500021C582C20707265737320627574746F6E2074AB S31500021C686F20656E640063616E63656C6C656420E3 S31500021C78627920627574746F6E00626C6577206390 S31500021C88697263756C617220627566666572212077 S31500021C98646174614C656E3D3078257800434F4D1A S31500021CA84D414E442046494E4953484544006D61CC S31500021CB878446174614C656E3D25782C20556172B5 S31500021CC8742E73746174653D25782C20556172747F S31500021CD82E62797465436E743D2578005561727477 S31500021CE82E62797465436E744D61783D25782C2091 S31500021CF874726163654C656E3D25782C2055617258 S31500021D08742E6F75747075745B305D3D2530387846 S31500021D18004572726F723A20756E6B6F776E207419 S31500021D2861677479706520282564290052656164A3 S31500021D3820726571756573742066726F6D2072659F S31500021D48616465723A2025782025780041757468A1 S31500021D5820617474656D7074207B6E727D7B61720E S31500021D687D3A202530387820253038780052656348 S31500021D78656976656420756E6B6E6F776E20636F24 S31500021D886D6D616E6420286C656E3D2564293A0086 S31500021D983130303020636F6D6D616E6473206C6113 S31500021DA87465722E2E2E00627574746F6E207072B0 S31500021DB8657373004C6F73742073796E6320696E52 S31500021DC8206379636C652025642E206E745F6469CE S31500021DD87374616E63653D25642E20436F6E736569 S31500021DE863757469766520526573796E6373203DEF S31500021DF82025642E20547279696E67206F6E6520DD S31500021E0874696D652063617463682075702E2E2E61 S31500021E180A004C6F73742073796E6320696E2063AF S31500021E2879636C6520256420666F72207468652064 S31500021E38666F757274682074696D6520636F6E7358 S31500021E48656375746976656C7920286E745F646952 S31500021E587374616E6365203D202564292E204164D2 S31500021E686A757374696E672073796E635F637963E3 S31500021E786C657320746F2025642E0A005374617290 S31500021E887465642E2037627569643D2564002D2DBC S31500021E983E20574F524B2E20616E7469636F6C3128 S31500021EA82074696D653A202564002D2D3E20574F12 S31500021EB8524B2E20616E7469636F6C322074696DA1 S31500021EC8653A2025640041555448204641494C4507 S31500021ED8442E206361726452723D253038782C2074 S31500021EE8737563633D25303878004155544820435D S31500021EF84F4D504C455445442E207365633D256429 S31500021F082C206B65793D25642074696D653D2564D1 S31500021F18002D2D3E2048414C5445442E2053656CD5 S31500021F2865637465642074696D653A202564206D5D S31500021F387300456D756C61746F722073746F70707F S31500021F4865642E2054726163696E673A202564209F S31500021F58207472616365206C656E6774683A202521 S31500021F686420005278456D707479204552524F525A S31500021F782121212064617461206C656E6774683A58 S31500021F882564006D6178446174614C656E3D2578FF S31500021F982C20556172742E73746174653D25782CF4 S31500021FA820556172742E62797465436E743D257884 S31500021FB820556172742E62797465436E744D617828 S31500021FC83D25780072616E64206E6F6E6365206CC3 S31500021FD8656E3A2025780061757468207569643AD9 S31500021FE82025303878206E743A202530387800411A S31500021FF8757468656E7469636174696F6E2066616B S31500022008696C65642E20436172642074696D656F1C S3150002201875742E0041757468656E746963617469B6 S315000220286F6E206661696C65642E204572726F72E6 S31500022038206361726420726573706F6E73652E0019 S31500022048436D64204572726F723A202530327800E9 S31500022058436D64204572726F723A2063617264201E S3150002206874696D656F75742E206C656E3A202578D5 S3150002207800436D642043524320726573706F6E731A S3150002208865206572726F722E00436D642073656EE9 S3150002209864206461746132204572726F723A202537 S315000220A83032780068616C74206572726F722E2005 S315000220B8726573706F6E7365206C656E3A2025784B S315000220C80043616E27742073656C656374206361CF S315000220D87264005265616420626C6F636B2065727C S315000220E8726F720048616C74206572726F72005268 S315000220F845414420424C4F434B2046494E4953489A S315000221084544005265616420626C6F636B2030201F S315000221186572726F72005265616420626C6F636BDE S315000221282031206572726F72005265616420626C9A S315000221386F636B2032206572726F7200526561643A S3150002214820626C6F636B2033206572726F72005265 S3150002215845414420534543544F522046494E49531C S3150002216848454400577269746520626C6F636B2038 S315000221786572726F7200575249544520424C4F435A S315000221884B2046494E4953484544004175746831C7 S31500022198206572726F7200417574683220657272B8 S315000221A86F7200723D2564206E74313D2530387891 S315000221B8206E74323D253038782064697374616EF6 S315000221C863653D25640064697374616E63653A20CC S315000221D86D696E3D2564206D61783D2564206176C2 S315000221E8673D2564004175746832206572726F72A4 S315000221F8206C656E3D256400723D2564206E74313F S315000222083D25303878206E7432656E633D25303848 S3150002221878206E74327061723D25303878007661A6 S315000222286C6964206D3D2564206B73313D25303819 S3150002223878206E74746573743D25303878004E457F S31500022248535445442046494E49534845440044653B S31500022258627567206C6576656C3A2025640053655D S3150002226863746F725B25645D2E2041757468206500 S3150002227872726F7200536563746F725B25645D2EAA S315000222882041757468206E65737465642065727280 S315000222986F7200454D554C2046494C4C20534543D8 S315000222A8544F52532046494E495348454400777580 S315000222B8704331206572726F7200776970654320C8 S315000222C86572726F72007775704332206572726F2B S315000222D87200777269746520626C6F636B2073652E S315000222E86E6420636F6D6D616E64206572726F72C3 S315000222F800777269746520626C6F636B2073656E12 S31500022308642064617461206572726F72007265611D S315000223186420626C6F636B2073656E6420636F6DF5 S315000223286D616E64206572726F7200534E465F531A S31500022338414B006E657720636D642066726F6D206F S315000223487265616465723A206C656E3D25642C205F S31500022358636D647352656376643D2564002B2B2B8B S31500022368435243206661696C00435243207061738D S31500022378736573006D616E7920636F6D6D616E644E S3150002238873206C617465722E2E2E00627574746FDA S315000223986E20707265737365642C20726563656955 S315000223A876656420256420636F6D6D616E647300C3 S315000223B84E6F20726573706F6E73652066726F6DED S315000223C8207461670052616E646F6D6C792067656F S315000223D86E657261746564205549442066726F6D34 S315000223E82074616720282B20322062797465204385 S315000223F85243293A202578202578202578004E6FE1 S31500022408772053454C454354207461673A00457812 S315000224187065637465642033206279746573206617 S31500022428726F6D207461672C20676F7420256400B3 S31500022438435243204572726F722072656164696EF7 S31500022448672073656C65637420726573706F6E734B S31500022458652E0042616420726573706F6E73652023 S31500022468746F2053454C4543542066726F6D205451 S3150002247861672C2061626F7274696E673A202578EB S3150002248820257800457870656374656420313020AC S3150002249862797465732066726F6D207461672C2089 S315000224A8676F7420256400435243204572726F7227 S315000224B82072656164696E6720626C6F636B2120A6 S315000224C82D2042656C6F773A20657870656374656E S315000224D8642C20676F74202578202578005461675C S315000224E820554944202836342062697473293A20D3 S315000224F825303878202530387800546167206D6594 S315000225086D6F72792064756D702C20626C6F636BC7 S31500022518203020746F2031350053797374656D202D S315000225286172656120626C6F636B2028307866661B S31500022538293A0045787065637465642036206279A5 S315000225487465732066726F6D207461672C20676FDD S3150002255874206C6573732E2E2E0041646472657343 S31500022568733D25782C20436F6E74656E74733D2512 S31500022578782C204352433D257800536E6F6F70695D S315000225886E67206275666665727320696E6974691C S31500022598616C697A65643A00202054726163653A0F S315000225A8202569206279746573002020526561646A S315000225B86572202D3E207461673A2025692062796A S315000225C8746573002020746167202D3E2052656170 S315000225D86465723A20256920627974657300202041 S315000225E8444D413A20256920627974657300626C0C S315000225F865772063697263756C61722062756666B7 S3150002260865722120626568696E6442793D30782573 S315000226187800526561636865642074726163652037 S315000226286C696D697400536E6F6F70207374617490 S315000226386973746963733A0020204D617820626574 S3150002264868696E642062793A2025690020205561FE S3150002265872742053746174653A20257800202055D7 S315000226686172742042797465436E743A2025690052 S315000226782020556172742042797465436E744D61E7 S31500022688783A2025690020205472616365206C65BA S315000226986E6774683A2025690063616E63656C6CBF S315000226A865645F610052454144455220415554488C S315000226B820286C656E3D25303264293A2025303251 S315000226C87820253032782025303278202530327825 S315000226D8202530327820253032782025303278206D S315000226E825303278202530327800556E6B6E6F773A S315000226F86E20636F6D6D616E6420726563656976BF S3150002270865642066726F6D20726561646572202841 S315000227186C656E3D2564293A202578202578202582 S315000227287820257820257820257820257820257870 S3150002273820257800202020202053656C6563746567 S31500022748642043534E3A2025303278202530327899 S3150002275820253032782025303278202530327820EC S3150002276825303278202530327820253032780050CC S315000227784D335601010073766E2037353600003226 S315000227883031342D30332D30312032303A33343A29 S3120002279834330000000000000000000000C5 S315001227A5000000000100000000000000000000000B S315001227B50000000000000000024E02204D494B5257 S315001227C520F04F4E0EAA4854465F4F4B5555555558 S315001227D5AAAAAAAA555555550000000000000000E0 S315001227E50000000000000000B80A00006C48200036 S315001227F50000FBFF00C201000000080002000000F5 S31500122805142C200001000000010203040400DEADB1 S31500122815BEAF62DEADBEAF6208B6DD04DA170000E2 S3150012282502000000014B98687047C04620FDFFFF65 S31500122835074B10B51C69074B0F21186902F0A6FC48 S315001228450A235843E403001910BC02BC0847C046C4 S315001228554000FAFF0000FAFF08B5FFF7E9FF044B3F S315001228651968021C1A60401A08BC02BC0847C04601 S315001228755C2A2000054A064B10691B690004184399 S3150012288503041B0C01D11069000470478000FAFF7E S315001228950000FAFFB8239FE500C0A0E1240092E5E7 S315001228A5000050E3FFCE2C0204402DE50230A0E1D4 S315001228B524C08205E400000A00C22CE00000D2E51D S315001228C5000050E324C082E59200000A140092E546 S315001228D5101092E58C00C0E1011081E2010070E250 S315001228E50000A033010051E3101082E50400001A1E S315001228F5000050E32810C205D300000A0000A0E329 S31500122905D10000EA2820D2E5010020E2FF0000E20C S31500122915000052E30020A01301200002000052E33A S315001229250220A0132820C3150200001A000050E346 S315001229350520A0130020C3150010D3E50020A0E33F S31500122945011041E2102083E5040051E301F19F973E S315001229554D0000EAC8012000640220001C02200076 S31500122965E4012000CC022000B220C3E12820D3E5E1 S31500122975020052E3D8129FE50520A0033800001A7B S315001229851D0000EA042093E5012082E2B200D3E19C S31500122995042083E52820D3E5A000A0E1000052E338 S315001229A5AC129FE5B200C3E10F00001A0020A0E3A6 S315001229B50020C3E50100A0E3360000EA042093E5F2 S315001229C5012082E2B200D3E1042083E52820D3E573 S315001229D5A000A0E1000052E374129FE5B200C3E124 S315001229E5F1FFFF0A010052E31D00000A020052E33D S315001229F52700001A010C80E3B200C1E10020C1E5EF S31500122A05230000EAB210D3E12800D3E5A110A0E114 S31500122A15000050E338229FE5B210C3E10500001A03 S31500122A250310A0E30010C2E5041092E5011081E23D S31500122A35041082E5170000EA010050E30510A00311 S31500122A450010C2051200000A020050E3011C8103A0 S31500122A55B210C201041092050110810204108205FA S31500122A650B0000EA0420A0E3E3FFFFEA2800D3E502 S31500122A75000050E3D8219FE50500001A0610A0E3D1 S31500122A85201082E50000C2E5020000EA0020C3E537 S31500122A95202083E50000A0E30010A0E32810C3E57B S31500122AA5043093E5020053E3A4219FE50600001ABC S31500122AB5010050E16400000A083092E5010053E175 S31500122AC5600000DA0100A0E35F0000EA090053E3A3 S31500122AD589FFFF1A083092E52C1092E5B2C0D2E1B1 S31500122AE503C0C1E7083092E5013083E2083082E57A S31500122AF5B230D2E1181092E52334A0E1013003E297 S31500122B05813083E1000050E3183082E50400820526 S31500122B154D00000AEAFFFFEAF0100CE24112A0E1AD S31500122B250F1031E24200000A204092E5080054E3F4 S31500122B35200082154400001A0120A0E3102083E527 S31500122B45082001E20300A0E3000052E3142083E506 S31500122B551C0083E5042001E2142083050220A0034C S31500122B651C2083050400000A000052E31420831575 S31500122B750220A0131112A0111C208315140093E52F S31500122B85000050E3C8209FE5020001E21400820509 S31500122B950100A0031C0082050400000A000050E390 S31500122BA5140082150100A0131110A0111C00821524 S31500122BB5140093E5000050E394209FE5011001E20D S31500122BC50A00001A000051E3141082E51C0082E582 S31500122BD50C00000A08001CE30A00000A0810A0E30C S31500122BE5141082E5100082E50310A0E3040000EA42 S31500122BF5000051E30300000A0110A0E3141082E558 S31500122C050010A0E31C1082E5142093E50222A0E130 S31500122C150000A0E3142083E50120A0E30020C3E50C S31500122C252820C3E5040083E5080083E5180083E53B S31500122C35050000EA203092E5070053E32EFFFFCA8E S31500122C45013083E2203082E50100A0E104409DE4D3 S31500122C551EFF2FE1AC2A200050239FE504402DE5E7 S31500122C650040A0E14C0092E5000050E30230A0E1DD S31500122C750130A0034C30820548408205C900000A7E S31500122C8530C0D2E500005CE3481092E5484082E583 S31500122C953C00001A5C0092E5542092E50540E0E3FB S31500122CA50240C0E7080011E30120A0E3382083E5BE S31500122CB50820A0133CC083E53C208315040011E3CC S31500122CC50400000A3C2093E5000052E30420A0E329 S31500122CD53C2083E50112A011020011E30400000A4B S31500122CE53C2093E5000052E30220A0E33C2083E555 S31500122CF50111A011010011E30400000A3C2093E51D S31500122D05000052E3A4229F150110A0133C10821550 S31500122D153C0093E5000050E390229FE5A000000ACF S31500122D250010A0E301C0A0E3541082E530C0C2E54D S31500122D3558C0C2E5341082E5B414C2E1401082E5EA S31500122D45501082E56020D2E5010052E10020E01321 S31500122D55CBCB0215040050E30700000A080050E326 S31500122D650300000A020050E38D00001A0120A0E3B9 S31500122D75020000EA0320A0E3000000EA0220A0E315 S31500122D85502083E5860000EA3C0092E5084004E2FD S31500122D958110A0E1A41181E1001001E0500092E535 S31500122DA5040080E2500082E5380092E5000050E307 S31500122DB50500001A001091E20130A0E30110A013DC S31500122DC5383082E55810C2E5760000EA0020A0E305 S31500122DD5020051E1382083E50C00000A5820D3E59C S31500122DE5010052E30220A0135820C3150700001A4A S31500122DF505005CE30500000A0520A0E33020C3E5C3 S31500122E055C1093E5542093E55500E0E30200C1E713 S31500122E153020D3E5012042E2040052E302F19F97E6 S31500122E25440000EA98062000EC062000EC06200075 S31500122E35B8062000A80720005810D3E56C219FE597 S31500122E45010051E35C0092155410921554C0E0131B S31500122E550900001A170000EA541093E5000051E321 S31500122E6548219FE51F0000CA340092E5000050E391 S31500122E751C0000CA5C0092E552C0E0E301C0C0E73F S31500122E850510A0E33010C2E5300000EA5810D3E56C S31500122E95010051E314219FE50800001A341092E54A S31500122EA5011081E2341082E5B414D2E1A110A0E139 S31500122EB5011C21E2B414C2E10210A0E3F0FFFFEAFD S31500122EC5020051E334109205011081023410820575 S31500122ED5B414D201A110A001B414C2010410A01396 S31500122EE50310A003E6FFFFEA34C093E500005CE396 S31500122EF5B8209FE50B0000DAB404D2E109C06CE2F2 S31500122F05500CA0E15CC092E5B404C2E10100CCE725 S31500122F15541092E5011081E2541082E5401092E5B3 S31500122F258110A0E1401082E50020A0E33020C3E520 S31500122F350100A0E31B0000EA5C1093E5542093E51B S31500122F452200E0E30200C1E70020A0E33020C3E53A S31500122F55343093E5080053E350209FE5100000DA5C S31500122F65543092E5B404D2E15C1092E50300C1E750 S31500122F75543092E5013083E2543082E5B434D2E11D S31500122F85401092E52334A0E1013003E20000A0E3EC S31500122F95813083E1403082E5340082E5B404C2E132 S31500122FA5000000EA0000A0E304409DE41EFF2FE1A5 S31500122FB5AC2A2000F8402DE94C419FE50150A0E1CD S31500122FC5686094E544119FE5010056E10070A0E1A1 S31500122FD50000A0C34A0000CA6C1094E530C19FE5F3 S31500122FE5012082E000109CE5010086E2680084E576 S31500122FF56C2084E50620C1E7682094E5010082E28B S31500123005680084E56C0094E500109CE54004A0E197 S315001230150200C1E7682094E5010082E2680084E5B2 S3150012302500109CE5FE06D4E10200C1E7682094E58E S31500123035010082E2680084E500109CE56F00D4E584 S315001230450200C1E718209DE5000052E30600001AAA S31500123055681094E500009CE5011041E20120D0E7D5 S31500123065822CE0E1A22CE0E10120C0E7682094E57C S3150012307500109CE5010082E2680084E50230C1E792 S31500123085682094E500109CE5010082E2680084E55B S315001230952304A0E10200C1E7682094E500109CE52F S315001230A5010082E2680084E52308A0E10200C1E777 S315001230B5682094E500109CE5010082E2233CA0E11C S315001230C5680084E50230C1E7683094E500209CE586 S315001230D5011083E2681084E50350C2E7683094E56F S315001230E500009CE50520A0E1030080E00710A0E1A1 S315001230F5300800EB683094E5055083E0685084E5A6 S315001231050100A0E3F840BDE81EFF2FE1AC2A20001E S31500123115B70B000060002000F04F2DE9B0429FE585 S3150012312514D04DE20050A0E3A8629FE50090A0E1FD S315001231351D0800EB7863FCEB030019E30510A0E10B S315001231453020A0E30400A0E10070A0130170A003D3 S31500123155545084E53050C4E55C6084E50F0800EBF5 S31500123165403046E22C3084E52030A0E30C3084E56D S31500123175FC5BFCEB011AA0E3400086E20F5CFCEB5C S315001231850420A0E30030E0E3CB2B03E5A000A0E387 S31500123195BA5CFCEB0207A0E3BB5CFCEB0580A0E185 S315001231A56C5084E5405086E206B0A0E105A0A0E188 S315001231B50030E0E3C32B13E5020512E318029F055F S315001231C57000000A0120A0E3CF2B03E5A52482E2B5 S315001231D5BF2203E52B3AE0E3FB3E13E505606AE001 S315001231E5013A63E2030056E1016A66C2036086C0CC S315001231F5036066D0016086C2080056E1070000DA50 S31500123205190E56E3040000DAD0019FE50610A0E177 S31500123215DA0700EB0680A0E15B0000EA0680A0E172 S31500123225000056E3E1FFFFDA2B3AE0E3FB2E13E546 S31500123235000052E3012AA003FFAE0305FB2E030588 S315001232452B3AE0E3EB2E13E5000052E3012AA00325 S31500123255EFAE0305EB2E03050030E0E30120A0E3F4 S31500123265CB2B03E56C2094E50000D5E5042082E21C S315001232752002A0E10C308DE56C2084E584FDFFEB80 S31500123285000050E348619FE50C309DE51000000AE9 S31500123295022CA0E3000057E3CF2B03E52E00001AFC S315001232A5020019E30400000A083096E5010053E30B S315001232B50930A003043086052700000A0030A0E372 S315001232C50030C4E53030C4E5012CA0E30030E0E35C S315001232D5CB2B03E50000D5E50F0000E25DFEFFEB03 S315001232E5000050E31700000A012CA0E30030E0E3CA S315001232F5CF2B03E5502094E50030A0E300308DE591 S31500123305D0009FE5541094E5002062E2403094E522 S3150012331527FFFFEB000050E31900000A000057E3F0 S315001233253020A0E3B8009FE50010A0E30170090262 S315001233350170A013990700EB022CA0E30030E0E31D S315001233455CB084E5CB2B03E598309FE5015085E209 S31500123355030055E1015A438294FFFFEA1C2094E5C6 S315001233650170A0E300708DE57C009FE5081094E5D9 S31500123375002062E2183094E50DFFFFEB000050E3E2 S31500123385CDFFFF1A64009FE5810700EB0220A0E33B S315001233952B3AE0E3DF2E03E50810A0E10020D4E581 S315001233A5083094E548009FE5740700EB2C3094E548 S315001233B540009FE50C1094E5682094E50030D3E5AE S315001233C56E0700EB780700EB14D08DE2F04FBDE8DF S315001233D51EFF2FE1AC2A20002C3820006E1C12008D S315001233E5821C1200DC2A20006C482000EC372000D3 S315001233F5A51C1200B61C1200E41C1200F74F2DE98B S3150012340598429FE598529FE50070A0E3660700EB88 S31500123415C162FCEB3020A0E30710A0E10400A0E195 S315001234255C5084E5547084E53070C4E55B0700EBA7 S31500123435403045E22C3084E52030A0E30C3084E59B S31500123445485BFCEB011AA0E3400085E25B5BFCEBF3 S315001234550420A0E30030E0E3CB2B03E5A000A0E3B4 S31500123465065CFCEB0207A0E3075CFCEBE175FCEBE3 S31500123475405085E20780A0E10590A0E10030E0E327 S31500123485C32B13E5020512E318029F057300000A02 S315001234950160A0E310229FE5067087E0410057E31D S315001234A5CF6B03E5BF2203E5080000DAFC319FE581 S315001234B57D0EA0E30FE0A0E113FF2FE1000050E31C S315001234C52B3AE013DF6E03150070A0130070A001EE S315001234D52B3AE0E3FB3E13E5056069E0013A63E248 S315001234E5030056E1016A66C2036086C0036066D0B0 S315001234F5016086C2080056E1070000DA190E56E386 S31500123505040000DAA8019FE50610A0E11B0700EBEF S315001235150680A0E1520000EA0680A0E1000056E30B S31500123525D5FFFFDA2B3AE0E3FB2E13E5000052E353 S315001235350500001A012AA0E3FF9E03E574019FE523 S31500123545FB2E03E50610A0E10C0700EB2B3AE0E390 S31500123555EB2E13E5000052E3012AA003EF9E0305A5 S315001235650060E0E3EB2E03050130A0E3CB3B06E555 S315001235750000D5E52002A0E1C5FCFFEB000050E3F3 S315001235851200000AC73B16E5020C13E3023CA0E340 S31500123595CF3B0605CB3B06150130A0E300308DE582 S315001235A514019FE5081094E5182094E5043094E576 S315001235B508C19FE50FE0A0E11CFF2FE1000050E3D3 S315001235C5D8609FE52400001A0000C6E53000C6E55E S315001235D50000D5E50F0000E29EFDFFEB000050E36B S315001235E51800000A0030E0E3C72B13E5020C12E3BC S315001235F5022CA0E3CF2B0305CB2B0315A0A09FE529 S315001236050030A0E300308DE50A00A0E1541094E5E0 S31500123615402094E5343094E5A0C09FE50FE0A0E183 S315001236251CFF2FE100B050E270609FE50A00001AF8 S31500123635300086E20B10A0E13020A0E3D70600EB9E S315001236455CA086E500B0C6E574309FE5015085E2BB S31500123655030055E1015A438287FFFFEA64009FE59D S31500123665CB0600EB0220A0E32B3AE0E3DF2E03E5BF S315001236757275FCEB0C3094E50020D4E500308DE52F S3150012368544009FE50810A0E1083094E5BB0600EB5F S31500123695C50600EB0CD08DE2F04FBDE81EFF2FE1FB S315001236A5AC2A20002C3820006E1C1200010000A541 S315001236B518132000821C12006B1F1200EC37200013 S315001236C5300F20006C482000A51C12008B1F12001B S315001236D5F3412DE90160A0E1010056E30050A0E196 S315001236E50280A0E120109DE5A0439FE50400001A83 S315001236F50030D0E50F0053E30030A0830C308485EB S315001237050930A0E30C2094E50B0052E302F19F97D2 S31500123715D80000EAA40F2000D812200004102000B9 S315001237252810200064102000B01020004C11200033 S31500123735A011200004112000001220007012200092 S315001237459C122000001091E20110A013010056E30D S315001237550010A013000051E3C800000A090053E344 S31500123765C600001A0030D5E5260053E3520053135E S31500123775C200001A0050A0E310039FE50510A0E150 S315001237850820A0E30B50C4E5840600EB00339FE541 S315001237950850C4E50A50C4E50150C3E50230A0E35A S315001237A5B50000EA020056E300005103B300001A01 S315001237B5DC029FE50510A0E10220A0E37D0600EBE1 S315001237C50330A0E3AC0000EA020056E2006070E2A4 S315001237D50060B6E0000051E30060A003000056E366 S315001237E5A600000A0030D5E5930053E3A300001A9C S315001237F50130D5E5200053E30430A0039F00001ADB S315001238059D0000EA050056E3000051039B00001ACD S315001238150120D5E50030D5E5033022E00220D5E5B5 S315001238250310D5E5023023E00420D5E5013023E067 S31500123835030052E19100001A58029FE50510A0E116 S315001238450420A0E35B0600EB0530A0E38A0000EA3C S31500123855092056E2006072E20260B6E0000051E30A S315001238650060A003000056E38400000A0030D5E587 S31500123875930053E38100001A0130D5E5700053E336 S315001238857E00001A10029FE50510A0E10920A0E3AB S31500123895485FFCEB000050E30830A0137600001ACF S315001238A5760000EA030056E3000051037300001A7E S315001238B5E4019FE50510A0E10320A0E33D5FFCEBC3 S315001238C5000050E36D00000A0020D5E50A20C4E584 S315001238D50320D4E5B4319FE5880052E30620A00300 S315001238E50920A0130C2083E5640000EA050056E3BF S315001238F5000051036100001A0120D5E50030D5E517 S31500123905033022E00220D5E50310D5E5023023E087 S315001239150420D5E5013023E0030052E15700001AD1 S3150012392568019FE50510A0E10420A0E3210600EB3E S315001239350030A0E30B30C4E50730A0E34E0000EAE1 S31500123945093056E2006073E20360B6E0000051E307 S315001239550060A003000056E34800000A0030D5E5D2 S31500123965950053E34500001A0130D5E5700053E37F S315001239754200001A20019FE50510A0E10920A0E3E7 S315001239850C5FFCEB000050E33C00000A0830A0E394 S3150012399508019FE50C3084E5F80500EB370000EACF S315001239A5FC009FE50070E0E3121040E20720A0E359 S315001239B51070C4E51170C4E5FE0500EBE4009FE541 S315001239C50220A0E3111040E2FA0500EB0A30D4E515 S315001239D51B30C4E50130A0E300308DE50E10A0E3DF S315001239E50020A0E30830A0E1BCC09FE5BC009FE51E S315001239F51C70C4E51D70C4E50FE0A0E11CFF2FE1A4 S31500123A05AC309FE50FE0A0E113FF2FE1200084E51E S31500123A150130A0E300308DE50500A0E10830A0E1F4 S31500123A250610A0E10020A0E37CC09FE50FE0A0E10F S31500123A351CFF2FE10B30A0E3080000EA0020A0E3EB S31500123A450830A0E100208DE50500A0E10610A0E1F1 S31500123A5554C09FE50FE0A0E11CFF2FE10A30A0E359 S31500123A650C3084E548309FE50FE0A0E113FF2FE106 S31500123A75200084E5010000EA0030A0E30C3084E55D S31500123A850000A0E308D08DE2F041BDE81EFF2FE14C S31500123A95342B20003C2B2000372B200063630000BB S31500123AA533231200462B20004D2B2000140820002C S31500123AB5442B2000850020003C309FE5003093E51D S31500123AC5000053E310402DE90800000A2C309FE54B S31500123AD5204093E528309FE5044080E00FE0A0E101 S31500123AE513FF2FE1000054E11040BD386474FC3A0F S31500123AF50000A0E31040BDE81EFF2FE1142B2000A5 S31500123B05342B20008500200014339FE51820D3E5B9 S31500123B15050052E302F19F97B80000EA94132000BC S31500123B25CC13200030142000841420000815200020 S31500123B3564152000000050E3000060B2000051E356 S31500123B45011080C0001061D0280051E3AD0000DAE3 S31500123B550020A0E30110A0E3202083E51810C3E599 S31500123B653C2083E5402083E5A60000EA20C093E5C4 S31500123B7507005CE3A8229FE5060000CA3CC092E551 S31500123B8500008CE03C0082E5400092E5011080E0E1 S31500123B95401082E5400000EA64005CE30010A0C311 S31500123BA51D0000CA3C2092E5000052E3402093E531 S31500123BB5000060D2000052E3010080C0000061D00F S31500123BC5000050E30220A0B3330000AA090000EA60 S31500123BD53C2093E5000052E3402093E5000060D2B5 S31500123BE5000052E3010080C0000061D0000050E3DE S31500123BF5040000AA0320A0E31820C3E50020A0E3D1 S31500123C05202083E5240000EA202093E5640052E390 S31500123C15210000DA08229FE50010A0E31810C2E57C S31500123C251D0000EA3C2093E5000052E3402093E58F S31500123C35000060D2000052E3010080C0000061D08E S31500123C45000050E3110000DA201093E50B0051E352 S31500123C55CC219FE5020000CA0020A0E31820C3E587 S31500123C650D0000EA0010E0E3020CA0E3CF0B01E51C S31500123C750410A0E31810C2E50010A0E3201082E597 S31500123C85381082E52C1082E5281082E5020000EA3A S31500123C95202093E5640052E3EEFFFFCA202093E548 S31500123CA5012082E2530000EA3C2093E5000052E32C S31500123CB5402093E5000060D2000052E3010080C067 S31500123CC5000061D0000050E3050000DA202093E5DC S31500123CD50A0052E348219FC50010A0C31810C2C599 S31500123CE5480000EA0020A0E30110A0E31C2083E5AA S31500123CF5B023C3E1201083E5240083E50520A0E364 S31500123D053F0000EA3C2093E5000052E3402093E58C S31500123D15000060D2000052E3010080C0000061D0AD S31500123D25201093E5000051E3F4209FE50110A0034E S31500123D3524008205201082053200000A241092E51D S31500123D45011080E0280092E5000051E3010080C0D1 S31500123D55000061D0280082E52C0093E5010080E27F S31500123D65000051E3241082E52C0083E51C1093E52F S31500123D75B003D3E1A8209FE5A000A0E1011081E2DE S31500123D85020C80C30A0051E3B003C2E11C1083E59D S31500123D958C209FE51600001AB013D2E184009FE528 S31500123DA5000001E0020C50E30800001A380092E503 S31500123DB534C092E5A110A0E10010CCE7381092E5C7 S31500123DC5011081E2381082E50410A0E3070000EA2B S31500123DD5000051E30010A0130400001A022CA0E300 S31500123DE50030E0E3CB2B03E50100A0E31EFF2FE134 S31500123DF51810C2E50020A0E3202083E5010000EAA1 S31500123E050020A0E31820C3E51800D3E5000050E30F S31500123E15022CA0030030E003CB2B03050000A013F0 S31500123E251EFF2FE1582B200001020000F04F2DE94D S31500123E35A4449FE51CD04DE20050A0E39C749FE577 S31500123E454410A0E3012AA0E394049FE5D30400EBF2 S31500123E551820A0E30510A0E10400A0E1347084E562 S31500123E65385084E51850C4E5CC0400EB023B47E212 S31500123E75143084E56C049FE56430A0E30C3084E5C8 S31500123E85BE0400EB60049FE5011AA0E3BB0400EB38 S31500123E9558049FE5021BA0E3B80400EB50049FE506 S31500123EA5021BA0E3B50400EB011BA0E344049FE546 S31500123EB5B20400EB0040E0E30430A0E3CB3B04E59B S31500123EC56300A0E36D59FCEB0207A0E36E59FCEB08 S31500123ED5A458FCEB020B87E2011BA0E3B758FCEBD7 S31500123EE50130A0E3CF3B04E508508DE5027B87E25E S31500123EF501ABA0E30540A0E12B3AE0E3FB6E13E527 S31500123F050A6066E0066BA0E108309DE5266BA0E126 S31500123F15030056E1080000DADC339FE5030056E19B S31500123F250400001AD4039FE50610A0E1930400EBE2 S31500123F3508608DE5C90000EA08608DE5010056E3C3 S31500123F45ECFFFFDAD030D7E10C308DE50130D7E53D S31500123F5510308DE5D130D7E1A4239FE514308DE5D8 S31500123F65023087E2032062E0010B52E30000D7E537 S31500123F75FF7F47C22B3AE0C3027047C2012BA0C38B S31500123F85FFAF8AC2EF7E03C5010000E2EB2E03C521 S31500123F9502A04AD20370A0D102A08AC26F73FCEBAB S31500123FA5000050E3025085E22F00000A30639FE5B8 S31500123FB54524A0E1013086E20650C4E70320C4E792 S31500123FC5023086E24528A0E10320C4E7033086E2E3 S31500123FD5252CA0E10320C4E70090A0E3043086E275 S31500123FE50390C4E7F0829FE5053086E20390C4E7A5 S31500123FF5063086E20390C4E708B098E5073086E2F4 S315001240050390C4E7082086E2093084E202B0C4E7C9 S31500124015030086E0011A86E20B20A0E100308DE549 S31500124025640400EB00309DE50B4083E0FA0F54E380 S315001240358A0000CA0910A0E11820A0E30800A0E131 S31500124045560400EB013A86E2143088E5180088E238 S315001240556430A0E30910A0E12C20A0E3066B86E2EA S315001240650C3088E54D0400EB346088E510309DE58B S31500124075010003E23973FCEB000050E32F00000A3E S315001240855C629FE54524A0E1013086E20650C4E74D S315001240950320C4E7023086E24528A0E10320C4E7DF S315001240A5033086E2252CA0E10320C4E70090A0E3A5 S315001240B5043086E20390C4E7053086E20390C4E72E S315001240C514829FE5063086E20390C4E7073086E23E S315001240D50390C4E7083098E509C084E2082086E211 S315001240E501BA86E20230C4E70C0086E00320A0E19D S315001240F50B10A0E108108DE82E0400EB08109DE8C0 S3150012410503408CE0FA0F54E3540000CA0910A0E1EB S315001241151820A0E30800A0E1200400EB066B86E256 S315001241256430A0E3180088E20910A0E12C20A0E370 S3150012413514B088E50C3088E5180400EB346088E580 S315001241450C009DE514109DE56EFEFFEB000050E395 S315001241553A00000A88619FE54524A0E1013086E20E S3150012416574819FE50650C4E70320C4E7023086E250 S315001241754528A0E10320C4E72C1098E5253CA0E1CB S31500124185833CE0E1A33CE0E1032086E2000051E333 S315001241950230C4E704B084E20630A0E10400000A46 S315001241A5280098E500608DE5A77AFCEB00309DE5C1 S315001241B5280088E5281098E548219FE54104A0E1E5 S315001241C50B10C6E7388098E50200C4E741C8A0E19E S315001241D5010082E204619FE500C0C4E7211CA0E14B S315001241E5020082E209B084E2032082E20010C4E7EB S315001241F50280C4E70B0083E00610A0E10820A0E1C7 S3150012420508408BE0EB0300EB010A54E3C8909FE5E7 S31500124215F4009FC5100000CA0030E0E30120A0E3B8 S31500124225CB2B03E5012CA0E3CF2B03E5180089E27E S315001242350010A0E32C20A0E3D80300EB346089E537 S31500124245C8209FE50030E0E3BF2203E5C33B13E533 S31500124255020513E327FFFF1AB4009FE5CC0300EB13 S315001242650030E0E30120A0E3CB2B03E5012CA0E30C S31500124275CB2B03E5022CA0E3CB2B03E50220A0E30F S315001242852B3AE0E3DF2E03E54C509FE584009FE5CC S31500124295BF0300EB08109DE57C009FE5B70300EB15 S315001242A50010D5E574009FE5B40300EB081095E5FB S315001242B56C009FE5B10300EB0C1095E564009FE5D4 S315001242C5AE0300EB60009FE50410A0E1AB0300EB23 S315001242D51CD08DE2F04FBDE81EFF2FE1582B2000B2 S315001242E514442000142C200082251200A025120049 S315001242F5B2251200CC251200E6251200FF03000096 S31500124305F6251200144C2000192C20001A2612002C S31500124315010000A5D81612002E26120040261200FC S315001243255426120065261200782612008E261200D1 S3150012433580339FE5341093E5000051E3FF0E20020A S3150012434504402DE50320A0E134008305D600000ABA S3150012435500C0D3E5010220E000005CE3340083E5EA S315001243658000000A1C1093E5104093E58000C1E118 S31500124375014084E2010070E20000A033010054E31B S31500124385104083E51900001A000050E30100000AE7 S315001243950010A0E3C40000EA141093E5010051E3EE S315001243A50D00001A082093E5000052E30000C3E54C S315001243B5280083E5BC00001A3C0093E50FC0E0E334 S315001243C500C0C0E5080093E5010080E2201083E5F0 S315001243D5080083E50210A0E1B30000EA01005CE3E0 S315001243E5EAFFFF0A0000C3E5280083E55B0000EA41 S315001243F5141093E5000050E3011081E2141083E5D1 S315001244050400001A383093E5000053E30000C21584 S31500124415280082153810820518C092E50000A0E31F S315001244250C0051E18C329FE5100082E5D7FFFF1A89 S31500124435040051E33100001A00C0D3E501005CE324 S31500124445140083E50F00001A38C093E504005CE3F7 S315001244550210A0030010C305011CA0030500000AE3 S3150012446503005CE30000C315280083150200001A39 S315001244750200A0E30000C3E5181083E50010A0E3CF S31500124485381082E5880000EA381093E5000051E3FA S315001244951D00000A011041E2B220D3E10113A0E189 S315001244A5FF1001E2221121E0042093E5022082E2A7 S315001244B5080052E3B210C3E1042083E5380083E510 S315001244C5B2FFFF1A082093E53CC093E50210CCE72C S315001244D5082093E5012082E2DC119FE5082083E599 S315001244E50220D3E50220D1E7201093E5812022E0B0 S315001244F5202083E5040083E5B200C3E1170000EA34 S31500124505381093E5000051E30200001A0010C3E5C6 S31500124515281083E5640000EA082093E53CC093E57C S31500124525011041E2381083E50210CCE7082093E525 S31500124535012082E280119FE5082083E53820D3E524 S315001245450220D1E7201093E5812022E0202083E581 S31500124555040083E5B200C3E1140083E5380083E560 S315001245650010A0E1500000EAF01000E24112A0E1AD S315001245750F1031E24700000A284093E5080054E37C S3150012458528C083150C10A0114700001A0130A0E3AC S31500124595103082E5083001E203C0A0E3000053E3C0 S315001245A51C3082E524C082E5043001E21C30820506 S315001245B50230A003243082050400000A000053E3EA S315001245C51C3082150230A0131113A0112430821546 S315001245D51CC092E500005CE3D8309FE502C001E2FB S315001245E51CC0830501C0A00324C083050400000A6C S315001245F500005CE31CC0831501C0A013111CA01199 S3150012460524C083151CC092E500005CE3A4309FE527 S31500124615011001E20A00001A000051E31C1083E59D S3150012462524C083E50C00000A080010E30A00000AFC S315001246350810A0E31C1083E510C083E50310A0E360 S31500124645040000EA000051E30300000A0110A0E38A S315001246551C1083E50010A0E3241083E51C3092E5B7 S315001246650332A0E11C3082E50130A0E30010A0E37D S315001246750030C2E50430A0E3041082E5081082E595 S31500124685201082E5141082E5183082E5381082E58D S31500124695B210C2E1040000EA282093E5070052E3AE S315001246A53AFFFFCA012082E2282083E50100A0E134 S315001246B504409DE41EFF2FE19C2B2000470C12009F S315001246C534259FE530002DE9603092E5600082E5DC S315001246D5640092E5581082E2021091E8020050E356 S315001246E5010080D25C3082E558C082E50230A0E135 S315001246F5640082D5250000DA4050D2E5000055E364 S315001247054000001A740092E56C2092E505C0E0E3BC S3150012471502C0C0E7080011E30120A0E3482083E5A3 S315001247250820A0134C5083E54C208315040011E391 S315001247350400000A4C2093E5000052E30420A0E38E S315001247454C2083E50112A011020011E30400000AB0 S315001247554C2093E5000052E30220A0E34C2083E5AA S315001247650111A011010011E30400000A4C2093E582 S31500124775000052E380249F150110A0134C108215D8 S315001247854C1093E5000051E36C249FE50100001AD5 S315001247950000A0E3160100EA0000A0E301C0A0E3B1 S315001247A5040051E36C0082E5440082E5B405C2E1DA S315001247B5500082E540C0C2E570C0C2E50200A00302 S315001247C50500000A080051E30300A0030200000ACF S315001247D502C051E200007CE20C00B0E0680082E5FE S315001247E5582093E5020011E10300000A08249FE50B S315001247F55C2092E5020011E1E4FFFF1A0000A0E336 S315001248054000C3E5FA0000EA8100A0E108C00CE207 S31500124815ACC180E1680092E5040080E2680082E599 S31500124825480092E54C4092E501C08CE1000050E348 S3150012483504C00CE00500001A00C09CE20130A0E39A S3150012484501C0A013483082E570C0C2E5E80000EA4F S315001248550000A0E300005CE1480082E57040D2E565 S315001248650400000A010054E30320A0030220A0134A S315001248757020C3E5150000EA000054E31200001A81 S31500124885040055E30A20A0134020C3153300A013D4 S315001248950E00001A6C3092E5741092E50F00A0E333 S315001248A50300C1E76C3092E5013083E26C3082E594 S315001248B548339FE5501092E50F30D3E5813023E05A S315001248C5503082E54040C2E5C80000EA0C00A0E17E S315001248D54020D3E5012042E2090052E302F19F97F7 S315001248E5770000EA6C212000B8212000EC21200077 S315001248F528222000282220002822200024232000F6 S3150012490524232000A02220003423200070C0D3E5E2 S3150012491503005CE3E0229FE50600001A02C0A0E34D S3150012492540C0C2E501C0A0E348C082E500C0A0E3CD S3150012493570C0C2E5680000EA6C0092E574C092E5A3 S315001249455440E0E30040CCE70A00A0E34000C2E58C S31500124955D200A0E3600000EA70C0D3E502005CE372 S3150012496594229FE503C0A0030C00000A6C0092E591 S3150012497574C092E55440E0E30040CCE70A00A0E398 S315001249854000C2E5D300A0E3530000EA70C0D3E5A8 S3150012499502005CE360229FE50200001A04C0A0E350 S315001249A540C0C2E54C0000EA6C0092E574C092E57F S315001249B55440E0E30040CCE70A00A0E34000C2E51C S315001249C5D400A0E3440000EA70C0D3E502005CE31C S315001249D524229FE50800001A44C092E501C08CE224 S315001249E544C082E5B4C5D2E1ACC0A0E101CC2CE24B S315001249F5B4C5C2E105C0A0E3E8FFFFEA01005CE326 S31500124A050700001A44C092E501C08CE244C082E553 S31500124A15B4C5D2E1ACC0A0E1B4C5C2E106C0A0E3FB S31500124A25DEFFFFEA03005CE309C0A003DBFFFF0A12 S31500124A350A00A0E34000C2E55500A0E3260000EAFD S31500124A456C0093E5000050E3AC219FE5020000CA15 S31500124A5544C092E500005CE3120000DA44C093E517 S31500124A6501005CE390219FE50B0000DAB415D2E153 S31500124A7509C06CE2511CA0E174C092E5B415C2E1FD S31500124A850010CCE76C1092E5011081E26C1082E5FC S31500124A95501092E58110A0E1501082E50020A0E3A6 S31500124AA54020C3E5510000EA74C092E55240E0E3A6 S31500124AB50040CCE70A00A0E34000C2E50300A0E3EC S31500124AC5050000EA74C093E56C2093E52240E0E305 S31500124AD50240CCE70020A0E34020C3E544C093E59D S31500124AE507005CE310219FE5110000DAB4C5D2E197 S31500124AF56C4092E5745092E5ACC0A0E1B4C5C2E132 S31500124B0504C0C5E76CC092E501C08CE2EC409FE596 S31500124B156CC082E554C0D2E50CC0D4E7504092E58C S31500124B2584C02CE050C082E500C0A0E344C082E5F3 S31500124B35B4C5C2E1000050E314FFFF0A6CC093E549 S31500124B45744093E54420E0E30C20C4E76CC093E57A S31500124B55744093E501C08CE26CC083E50C00C4E792 S31500124B656C0093E574C093E5010080E26C0083E561 S31500124B750020CCE76C0093E574C093E5010080E252 S31500124B856C0083E50010CCE76C1093E5740093E591 S31500124B9558C093E5011081E26C1083E501C0C0E7A8 S31500124BA56C1093E5740093E55CC093E5011081E200 S31500124BB56C1083E501C0C0E76C1093E5740093E5AC S31500124BC54CC093E5011081E26C1083E501C0C0E784 S31500124BD56C1093E5740093E5011081E26C1083E580 S31500124BE50120C0E76C2093E5012082E26C2083E563 S31500124BF50100A0E33000BDE81EFF2FE19C2B20002B S31500124C05470C1200F74F2DE90100A0E3D05CFCEB2F S31500124C15C15CFCEB0000A0E3BB5CFCEB28359FE511 S31500124C250050A0E3005083E520359FE520459FE51A S31500124C3520659FE5000093E51C259FE54410A0E33A S31500124C45560100EB746084E56C5084E54050C4E56A S31500124C554455FCEB400086E2011AA0E35755FCEBDE S31500124C650510A0E14020A0E30400A0E14B0100EBF2 S31500124C752030A0E30C3084E50420A0E30030E0E305 S31500124C85406046E23C6084E5A000A0E3CB2B03E539 S31500124C95FA55FCEB0207A0E3FB55FCEB04508DE538 S31500124CA50570A0E105B0A0E10580A0E1806086E26D S31500124CB5019AA0E30030E0E30120A0E3CF2B03E540 S31500124CC5A52482E2BF2203E52B2AE0E3FB4E12E579 S31500124CD5094064E0044AA0E1244AA0E1080054E12F S31500124CE5060000DA190E54E3070000DA6C049FE594 S31500124CF50410A0E1210100EB0480A0E1F60000EA10 S31500124D05000054E3EAFFFF0A000000EA0480A0E16E S31500124D150120A0E3CB2B03E50630A0E10120D3E465 S31500124D253C149FE5031061E0010A51E3FF6E46C28A S31500124D352B3AE0C3011AA0C30F6046C2EF6E03C534 S31500124D450360A0D1EB1E03C504309DE5FF9E89C203 S31500124D55013083E2019049D20F9089C20F0012E306 S31500124D650110A01304308DE503306B121173271051 S31500124D75302002E201A08BE201B01BE2055122E0CE S31500124D855C00001AF00005E22002A0E167FDFFEBC8 S31500124D95000050E30050A0015600000AB0539FE5EB S31500124DA504309DE5240095E59C239FE5030060E00C S31500124DB500C0E0E3023CA0E3A8439FE5000082E5BC S31500124DC5CF3B0CE5001094E580339FE501E081E2C7 S31500124DD500E084E500E093E50100CEE7001094E5D6 S31500124DE5010081E2000084E5000092E500E093E50A S31500124DF54004A0E10100CEE7001094E5010081E22E S31500124E05000084E500E093E5F200D2E10100CEE769 S31500124E15001094E500E093E50320D2E5010081E256 S31500124E25000084E50120CEE7002094E5010082E228 S31500124E35000084E5001093E5200095E50200C1E720 S31500124E45002094E5010082E2000084E5200095E544 S31500124E55001093E54004A0E10200C1E7002094E5A5 S31500124E65010082E2001093E5000084E5F202D5E125 S31500124E750200C1E7002094E5010082E2000084E504 S31500124E85001093E52300D5E50200C1E7002094E55D S31500124E95010082E2001093E5000084E5080095E51D S31500124EA50200C1E7000093E5003094E5082095E578 S31500124EB5030080E0B0129FE500C08DE5BD0000EB52 S31500124EC5002094E5083095E5033082E09C229FE5A3 S31500124ED5020053E1003084E500C09DE56F0000CA6B S31500124EE5013CA0E300B0C5E540B0C5E5CB3B0CE5FA S31500124EF508B085E50B50A0E103005AE35F0000DA1E S31500124F050F0007E2EDFDFFEB000050E30070A00174 S31500124F155900000A38B29FE504309DE568009BE505 S31500124F2524229FE5030060E00070E0E3013CA0E364 S31500124F3530429FE5000082E5CF3B07E50C329FE53F S31500124F45001094E500C093E501E081E200E084E5F6 S31500124F550100CCE7001094E501C081E200C084E5AA S31500124F6500C092E5000093E54CC4A0E101C0C0E77C S31500124F75001094E501C081E200C084E5000093E5C6 S31500124F85F2C0D2E101C0C0E70320D2E5001094E5D4 S31500124F95000093E5822CE0E101C081E2A22CE0E15A S31500124FA500C084E50120C0E7002094E5010082E2F5 S31500124FB5000084E5001093E550009BE50200C1E769 S31500124FC5002094E5010082E2000084E550009BE58D S31500124FD5001093E54004A0E10200C1E7002094E524 S31500124FE5010082E2001093E5000084E5F205DBE19B S31500124FF50200C1E7002094E5010082E2000084E583 S31500125005001093E55300DBE50200C1E7002094E5A5 S31500125015010082E2001093E5000084E56C009BE531 S315001250250200C1E72CA19FE5000093E5003094E547 S315001250356C209BE5030080E00A10A0E15D0000EB01 S31500125045002094E56C309BE5033082E01C219FE538 S31500125055020053E1003084E5100000CA40008BE2DD S315001250650010A0E33820A0E34C0000EB023CA0E3BD S3150012507574A08BE5CB3B07E50070A0E307A0A0E182 S315001250850030E0E3C33B13E5020513E30AB0A011B2 S3150012509507FFFF1AD8009FE53D0000EB0E0000EA58 S315001250A5AC409FE5CC009FE5390000EBC8009FE5B3 S315001250B50810A0E10020D4E5083094E52F0000EB96 S315001250C53C3094E59C209FE5AC009FE50C1094E5D9 S315001250D5002092E50030D3E5280000EB0220A0E37C S315001250E52B3AE0E368409FE5DF2E03E50810A0E1C1 S315001250F50020D4E5083094E57C009FE51F0000EBFF S315001251053C3094E55C209FE56C009FE50C1094E518 S31500125115002092E50030D3E5180000EB0030E0E3FD S315001251250120A0E3CB2B03E5012CA0E3CB2B03E552 S31500125135022CA0E3CB2B03E50420A0E3CB2B03E53E S315001251450CD08DE2F04FBDE81EFF2FE1182B200083 S31500125155600020009C2B20002C382000D80B000064 S31500125165F62512006C382000142B2000EC3720008F S31500125175B80B0000A1261200A51C1200FD23120071 S3150012518500C09FE51CFF2FE1914911007847C046E3 S315001251956876FCEA00C09FE51CFF2FE10549110060 S315001251A500C09FE51CFF2FE10D70110000C09FE5A1 S315001251B51CFF2FE1516C110000C09FE51CFF2FE16A S315001251C5F56F11000000000000000000000000004D S30D001251D50000000000000000BA S70500110001E8 ================================================ FILE: TamagotchiFriends/proxmark/armsrc/obj/printf.d ================================================ obj/printf.d obj/printf.o: printf.c printf.h util.h stdint.h \ ../include/common.h ../include/at91sam7s512.h string.h ================================================ FILE: TamagotchiFriends/proxmark/armsrc/obj/start.d ================================================ obj/start.d obj/start.o: start.c ../include/proxmark3.h \ ../include/at91sam7s512.h ../include/config_gpio.h ../include/usb_cmd.h \ stdint.h apps.h ../include/common.h ../include/at91sam7s512.h \ ../include/hitag2.h ../include/mifare.h ../include/common.h ================================================ FILE: TamagotchiFriends/proxmark/armsrc/obj/string.d ================================================ obj/string.d obj/string.o: string.c string.h stdint.h ================================================ FILE: TamagotchiFriends/proxmark/armsrc/obj/usb_cdc.d ================================================ obj/usb_cdc.d obj/usb_cdc.o: ../common/usb_cdc.c ../common/usb_cdc.h \ ../include/common.h stdint.h ../include/at91sam7s512.h \ ../include/config_gpio.h ================================================ FILE: TamagotchiFriends/proxmark/armsrc/obj/util.d ================================================ obj/util.d obj/util.o: util.c ../include/proxmark3.h \ ../include/at91sam7s512.h ../include/config_gpio.h ../include/usb_cmd.h \ stdint.h util.h ../include/common.h ../include/at91sam7s512.h string.h ================================================ FILE: TamagotchiFriends/proxmark/armsrc/printf.c ================================================ /*- * Copyright (c) 1986, 1988, 1991, 1993 * The Regents of the University of California. All rights reserved. * (c) UNIX System Laboratories, Inc. * All or some portions of this file are derived from material licensed * to the University of California by American Telephone and Telegraph * Co. or Unix System Laboratories, Inc. and are reproduced herein with * the permission of UNIX System Laboratories, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * @(#)subr_prf.c 8.3 (Berkeley) 1/21/94 */ #include #include #include "printf.h" #include "util.h" #include "string.h" typedef uint32_t uintmax_t; typedef int32_t intmax_t; typedef unsigned char u_char; typedef unsigned int u_int; typedef unsigned long u_long; typedef unsigned short u_short; typedef unsigned long long u_quad_t; typedef long long quad_t; typedef int ssize_t; #define NBBY 8 /* number of bits in a byte */ char const hex2ascii_data[] = "0123456789abcdefghijklmnopqrstuvwxyz"; #define hex2ascii(hex) (hex2ascii_data[hex]) #define toupper(c) ((c) - 0x20 * (((c) >= 'a') && ((c) <= 'z'))) /* Max number conversion buffer length: a u_quad_t in base 2, plus NUL byte. */ #define MAXNBUF (sizeof(intmax_t) * NBBY + 1) /* * Put a NUL-terminated ASCII number (base <= 36) in a buffer in reverse * order; return an optional length and a pointer to the last character * written in the buffer (i.e., the first character of the string). * The buffer pointed to by `nbuf' must have length >= MAXNBUF. */ static char * ksprintn(char *nbuf, uintmax_t num, int base, int *lenp, int upper) { char *p, c; p = nbuf; *p = '\0'; do { c = hex2ascii(num % base); *++p = upper ? toupper(c) : c; } while (num /= base); if (lenp) *lenp = p - nbuf; return (p); } /* * Scaled down version of printf(3). * * Two additional formats: * * The format %b is supported to decode error registers. * Its usage is: * * printf("reg=%b\n", regval, "*"); * * where is the output base expressed as a control character, e.g. * \10 gives octal; \20 gives hex. Each arg is a sequence of characters, * the first of which gives the bit number to be inspected (origin 1), and * the next characters (up to a control character, i.e. a character <= 32), * give the name of the register. Thus: * * kvprintf("reg=%b\n", 3, "\10\2BITTWO\1BITONE\n"); * * would produce output: * * reg=3 * * XXX: %D -- Hexdump, takes pointer and separator string: * ("%6D", ptr, ":") -> XX:XX:XX:XX:XX:XX * ("%*D", len, ptr, " " -> XX XX XX XX ... */ int kvsprintf(char const *fmt, void *arg, int radix, va_list ap) { #define PCHAR(c) {int cc=(c); *d++ = cc; retval++; } char nbuf[MAXNBUF]; char *d; const char *p, *percent, *q; u_char *up; int ch, n; uintmax_t num; int base, lflag, qflag, tmp, width, ladjust, sharpflag, neg, sign, dot; int cflag, hflag, jflag, tflag, zflag; int dwidth, upper; char padc; int stop = 0, retval = 0; num = 0; d = (char *) arg; if (fmt == NULL) fmt = "(fmt null)\n"; if (radix < 2 || radix > 36) radix = 10; for (;;) { padc = ' '; width = 0; while ((ch = (u_char)*fmt++) != '%' || stop) { PCHAR(ch); if (ch == '\0') return (retval); } percent = fmt - 1; qflag = 0; lflag = 0; ladjust = 0; sharpflag = 0; neg = 0; sign = 0; dot = 0; dwidth = 0; upper = 0; cflag = 0; hflag = 0; jflag = 0; tflag = 0; zflag = 0; reswitch: switch (ch = (u_char)*fmt++) { case '.': dot = 1; goto reswitch; case '#': sharpflag = 1; goto reswitch; case '+': sign = 1; goto reswitch; case '-': ladjust = 1; goto reswitch; case '%': PCHAR(ch); break; case '*': if (!dot) { width = va_arg(ap, int); if (width < 0) { ladjust = !ladjust; width = -width; } } else { dwidth = va_arg(ap, int); } goto reswitch; case '0': if (!dot) { padc = '0'; goto reswitch; } case '1': case '2': case '3': case '4': case '5': case '6': case '7': case '8': case '9': for (n = 0;; ++fmt) { n = n * 10 + ch - '0'; ch = *fmt; if (ch < '0' || ch > '9') break; } if (dot) dwidth = n; else width = n; goto reswitch; case 'b': num = (u_int)va_arg(ap, int); p = va_arg(ap, char *); for (q = ksprintn(nbuf, num, *p++, NULL, 0); *q;) PCHAR(*q--); if (num == 0) break; for (tmp = 0; *p;) { n = *p++; if (num & (1 << (n - 1))) { PCHAR(tmp ? ',' : '<'); for (; (n = *p) > ' '; ++p) PCHAR(n); tmp = 1; } else for (; *p > ' '; ++p) continue; } if (tmp) PCHAR('>'); break; case 'c': PCHAR(va_arg(ap, int)); break; case 'D': up = va_arg(ap, u_char *); p = va_arg(ap, char *); if (!width) width = 16; while(width--) { PCHAR(hex2ascii(*up >> 4)); PCHAR(hex2ascii(*up & 0x0f)); up++; if (width) for (q=p;*q;q++) PCHAR(*q); } break; case 'd': case 'i': base = 10; sign = 1; goto handle_sign; case 'h': if (hflag) { hflag = 0; cflag = 1; } else hflag = 1; goto reswitch; case 'j': jflag = 1; goto reswitch; case 'l': if (lflag) { lflag = 0; qflag = 1; } else lflag = 1; goto reswitch; case 'n': if (jflag) *(va_arg(ap, intmax_t *)) = retval; else if (qflag) *(va_arg(ap, quad_t *)) = retval; else if (lflag) *(va_arg(ap, long *)) = retval; else if (zflag) *(va_arg(ap, size_t *)) = retval; else if (hflag) *(va_arg(ap, short *)) = retval; else if (cflag) *(va_arg(ap, char *)) = retval; else *(va_arg(ap, int *)) = retval; break; case 'o': base = 8; goto handle_nosign; case 'p': base = 16; sharpflag = (width == 0); sign = 0; num = (uintptr_t)va_arg(ap, void *); goto number; case 'q': qflag = 1; goto reswitch; case 'r': base = radix; if (sign) goto handle_sign; goto handle_nosign; case 's': p = va_arg(ap, char *); if (p == NULL) p = "(null)"; if (!dot) n = strlen (p); else for (n = 0; n < dwidth && p[n]; n++) continue; width -= n; if (!ladjust && width > 0) while (width--) PCHAR(padc); while (n--) PCHAR(*p++); if (ladjust && width > 0) while (width--) PCHAR(padc); break; case 't': tflag = 1; goto reswitch; case 'u': base = 10; goto handle_nosign; case 'X': upper = 1; case 'x': base = 16; goto handle_nosign; case 'y': base = 16; sign = 1; goto handle_sign; case 'z': zflag = 1; goto reswitch; handle_nosign: sign = 0; if (jflag) num = va_arg(ap, uintmax_t); else if (qflag) num = va_arg(ap, u_quad_t); else if (tflag) num = va_arg(ap, ptrdiff_t); else if (lflag) num = va_arg(ap, u_long); else if (zflag) num = va_arg(ap, size_t); else if (hflag) num = (u_short)va_arg(ap, int); else if (cflag) num = (u_char)va_arg(ap, int); else num = va_arg(ap, u_int); goto number; handle_sign: if (jflag) num = va_arg(ap, intmax_t); else if (qflag) num = va_arg(ap, quad_t); else if (tflag) num = va_arg(ap, ptrdiff_t); else if (lflag) num = va_arg(ap, long); else if (zflag) num = va_arg(ap, ssize_t); else if (hflag) num = (short)va_arg(ap, int); else if (cflag) num = (char)va_arg(ap, int); else num = va_arg(ap, int); number: if (sign && (intmax_t)num < 0) { neg = 1; num = -(intmax_t)num; } p = ksprintn(nbuf, num, base, &tmp, upper); if (sharpflag && num != 0) { if (base == 8) tmp++; else if (base == 16) tmp += 2; } if (neg) tmp++; if (!ladjust && padc != '0' && width && (width -= tmp) > 0) while (width--) PCHAR(padc); if (neg) PCHAR('-'); if (sharpflag && num != 0) { if (base == 8) { PCHAR('0'); } else if (base == 16) { PCHAR('0'); PCHAR('x'); } } if (!ladjust && width && (width -= tmp) > 0) while (width--) PCHAR(padc); while (*p) PCHAR(*p--); if (ladjust && width && (width -= tmp) > 0) while (width--) PCHAR(padc); break; default: while (percent < fmt) PCHAR(*percent++); /* * Since we ignore an formatting argument it is no * longer safe to obey the remaining formatting * arguments as the arguments will no longer match * the format specs. */ stop = 1; break; } } PCHAR(0); return retval; #undef PCHAR } int vsprintf(char *dest, const char *fmt, va_list ap) { return kvsprintf(fmt, dest, 10, ap); } int sprintf(char *dest, const char *fmt, ...) { /* http://www.pagetable.com/?p=298 */ int retval; va_list ap; va_start(ap, fmt); retval = kvsprintf(fmt, dest, 10, ap); va_end(ap); return retval; } ================================================ FILE: TamagotchiFriends/proxmark/armsrc/printf.h ================================================ //----------------------------------------------------------------------------- // Copyright (C) 2010 Hector Martin "marcan" // // This code is licensed to you under the terms of the GNU GPL, version 2 or, // at your option, any later version. See the LICENSE.txt file for the text of // the license. //----------------------------------------------------------------------------- // Common *printf() functions //----------------------------------------------------------------------------- #ifndef __PRINTF_H #define __PRINTF_H #include int kvsprintf(const char *format, void *arg, int radix, va_list ap) __attribute__ ((format (printf, 1, 0))); int vsprintf(char *str, const char *format, va_list ap) __attribute__ ((format (printf, 2, 0))); int sprintf(char *str, const char *format, ...) __attribute__ ((format (printf, 2, 3))); #endif ================================================ FILE: TamagotchiFriends/proxmark/armsrc/start.c ================================================ //----------------------------------------------------------------------------- // Jonathan Westhues, Mar 2006 // // This code is licensed to you under the terms of the GNU GPL, version 2 or, // at your option, any later version. See the LICENSE.txt file for the text of // the license. //----------------------------------------------------------------------------- // Just vector to AppMain(). This is in its own file so that I can place it // with the linker script. //----------------------------------------------------------------------------- #include "proxmark3.h" #include "apps.h" extern char __data_start__, __data_src_start__, __data_end__, __bss_start__, __bss_end__; void __attribute__((section(".startos"))) Vector(void) { /* Stack should have been set up by the bootloader */ char *src, *dst, *end; /* Set up (that is: clear) BSS. */ dst = &__bss_start__; end = &__bss_end__; while(dst < end) *dst++ = 0; /* Set up data segment: Copy from flash to ram */ src = &__data_src_start__; dst = &__data_start__; end = &__data_end__; while(dst < end) *dst++ = *src++; AppMain(); } ================================================ FILE: TamagotchiFriends/proxmark/armsrc/stdint.h ================================================ //----------------------------------------------------------------------------- // Copyright (C) 2010 Hector Martin "marcan" // // This code is licensed to you under the terms of the GNU GPL, version 2 or, // at your option, any later version. See the LICENSE.txt file for the text of // the license. //----------------------------------------------------------------------------- // Replacement stdint.h because GCC doesn't come with it yet (C99) //----------------------------------------------------------------------------- #ifndef __STDINT_H #define __STDINT_H typedef signed char int8_t; typedef short int int16_t; typedef int int32_t; typedef long long int int64_t; typedef unsigned char uint8_t; typedef unsigned short int uint16_t; typedef unsigned int uint32_t; typedef unsigned long long int uint64_t; typedef int intptr_t; typedef unsigned int uintptr_t; #endif /* __STDINT_H */ ================================================ FILE: TamagotchiFriends/proxmark/armsrc/string.c ================================================ //----------------------------------------------------------------------------- // Jonathan Westhues, Sept 2005 // // This code is licensed to you under the terms of the GNU GPL, version 2 or, // at your option, any later version. See the LICENSE.txt file for the text of // the license. //----------------------------------------------------------------------------- // Common string.h functions //----------------------------------------------------------------------------- #include "string.h" #include void *memcpy(void *dest, const void *src, int len) { uint8_t *d = dest; const uint8_t *s = src; while((len--) > 0) { *d = *s; d++; s++; } return dest; } void *memset(void *dest, int c, int len) { uint8_t *d = dest; while((len--) > 0) { *d = c; d++; } return dest; } int memcmp(const void *av, const void *bv, int len) { const uint8_t *a = av; const uint8_t *b = bv; while((len--) > 0) { if(*a != *b) { return *a - *b; } a++; b++; } return 0; } int strlen(const char *str) { int l = 0; while(*str) { l++; str++; } return l; } char* strncat(char *dest, const char *src, unsigned int n) { unsigned int dest_len = strlen(dest); unsigned int i; for (i = 0 ; i < n && src[i] != '\0' ; i++) dest[dest_len + i] = src[i]; dest[dest_len + i] = '\0'; return dest; } char* strcat(char *dest, const char *src) { unsigned int dest_len = strlen(dest); unsigned int i; for (i = 0 ; src[i] != '\0' ; i++) dest[dest_len + i] = src[i]; dest[dest_len + i] = '\0'; return dest; } ////////////////////////////////////////// code to do 'itoa' /* reverse: reverse string s in place */ void strreverse(char s[]) { int c, i, j; for (i = 0, j = strlen(s)-1; i 0); /* delete it */ if (sign < 0) s[i++] = '-'; s[i] = '\0'; strreverse(s); } //////////////////////////////////////// END 'itoa' CODE ================================================ FILE: TamagotchiFriends/proxmark/armsrc/string.h ================================================ //----------------------------------------------------------------------------- // Jonathan Westhues, Aug 2005 // Copyright (C) 2010 Hector Martin "marcan" // // This code is licensed to you under the terms of the GNU GPL, version 2 or, // at your option, any later version. See the LICENSE.txt file for the text of // the license. //----------------------------------------------------------------------------- // Common string.h functions //----------------------------------------------------------------------------- #ifndef __STRING_H #define __STRING_H int strlen(const char *str); void *memcpy(void *dest, const void *src, int len); void *memset(void *dest, int c, int len); int memcmp(const void *av, const void *bv, int len); char *strncat(char *dest, const char *src, unsigned int n); char *strcat(char *dest, const char *src); void strreverse(char s[]); void itoa(int n, char s[]); #endif /* __STRING_H */ ================================================ FILE: TamagotchiFriends/proxmark/armsrc/util.c ================================================ //----------------------------------------------------------------------------- // Jonathan Westhues, Sept 2005 // // This code is licensed to you under the terms of the GNU GPL, version 2 or, // at your option, any later version. See the LICENSE.txt file for the text of // the license. //----------------------------------------------------------------------------- // Utility functions used in many places, not specific to any piece of code. //----------------------------------------------------------------------------- #include "proxmark3.h" #include "util.h" #include "string.h" size_t nbytes(size_t nbits) { return (nbits/8)+((nbits%8)>0); } uint32_t SwapBits(uint32_t value, int nrbits) { int i; uint32_t newvalue = 0; for(i = 0; i < nrbits; i++) { newvalue ^= ((value >> i) & 1) << (nrbits - 1 - i); } return newvalue; } void num_to_bytes(uint64_t n, size_t len, uint8_t* dest) { while (len--) { dest[len] = (uint8_t) n; n >>= 8; } } uint64_t bytes_to_num(uint8_t* src, size_t len) { uint64_t num = 0; while (len--) { num = (num << 8) | (*src); src++; } return num; } void LEDsoff() { LED_A_OFF(); LED_B_OFF(); LED_C_OFF(); LED_D_OFF(); } // LEDs: R(C) O(A) G(B) -- R(D) [1, 2, 4 and 8] void LED(int led, int ms) { if (led & LED_RED) LED_C_ON(); if (led & LED_ORANGE) LED_A_ON(); if (led & LED_GREEN) LED_B_ON(); if (led & LED_RED2) LED_D_ON(); if (!ms) return; SpinDelay(ms); if (led & LED_RED) LED_C_OFF(); if (led & LED_ORANGE) LED_A_OFF(); if (led & LED_GREEN) LED_B_OFF(); if (led & LED_RED2) LED_D_OFF(); } // Determine if a button is double clicked, single clicked, // not clicked, or held down (for ms || 1sec) // In general, don't use this function unless you expect a // double click, otherwise it will waste 500ms -- use BUTTON_HELD instead int BUTTON_CLICKED(int ms) { // Up to 500ms in between clicks to mean a double click int ticks = (48000 * (ms ? ms : 1000)) >> 10; // If we're not even pressed, forget about it! if (!BUTTON_PRESS()) return BUTTON_NO_CLICK; // Borrow a PWM unit for my real-time clock AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0); // 48 MHz / 1024 gives 46.875 kHz AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10); AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0; AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff; uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR; int letoff = 0; for(;;) { uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR; // We haven't let off the button yet if (!letoff) { // We just let it off! if (!BUTTON_PRESS()) { letoff = 1; // reset our timer for 500ms start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR; ticks = (48000 * (500)) >> 10; } // Still haven't let it off else // Have we held down a full second? if (now == (uint16_t)(start + ticks)) return BUTTON_HOLD; } // We already let off, did we click again? else // Sweet, double click! if (BUTTON_PRESS()) return BUTTON_DOUBLE_CLICK; // Have we ran out of time to double click? else if (now == (uint16_t)(start + ticks)) // At least we did a single click return BUTTON_SINGLE_CLICK; WDT_HIT(); } // We should never get here return BUTTON_ERROR; } // Determine if a button is held down int BUTTON_HELD(int ms) { // If button is held for one second int ticks = (48000 * (ms ? ms : 1000)) >> 10; // If we're not even pressed, forget about it! if (!BUTTON_PRESS()) return BUTTON_NO_CLICK; // Borrow a PWM unit for my real-time clock AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0); // 48 MHz / 1024 gives 46.875 kHz AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10); AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0; AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff; uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR; for(;;) { uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR; // As soon as our button let go, we didn't hold long enough if (!BUTTON_PRESS()) return BUTTON_SINGLE_CLICK; // Have we waited the full second? else if (now == (uint16_t)(start + ticks)) return BUTTON_HOLD; WDT_HIT(); } // We should never get here return BUTTON_ERROR; } // attempt at high resolution microsecond timer // beware: timer counts in 21.3uS increments (1024/48Mhz) void SpinDelayUs(int us) { int ticks = (48*us) >> 10; // Borrow a PWM unit for my real-time clock AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0); // 48 MHz / 1024 gives 46.875 kHz AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10); AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0; AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff; uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR; for(;;) { uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR; if (now == (uint16_t)(start + ticks)) return; WDT_HIT(); } } void SpinDelay(int ms) { // convert to uS and call microsecond delay function SpinDelayUs(ms*1000); } /* Similar to FpgaGatherVersion this formats stored version information * into a string representation. It takes a pointer to the struct version_information, * verifies the magic properties, then stores a formatted string, prefixed by * prefix in dst. */ void FormatVersionInformation(char *dst, int len, const char *prefix, void *version_information) { struct version_information *v = (struct version_information*)version_information; dst[0] = 0; strncat(dst, prefix, len); if(v->magic != VERSION_INFORMATION_MAGIC) { strncat(dst, "Missing/Invalid version information", len); return; } if(v->versionversion != 1) { strncat(dst, "Version information not understood", len); return; } if(!v->present) { strncat(dst, "Version information not available", len); return; } strncat(dst, v->svnversion, len); if(v->clean == 0) { strncat(dst, "-unclean", len); } else if(v->clean == 2) { strncat(dst, "-suspect", len); } strncat(dst, " ", len); strncat(dst, v->buildtime, len); } // ------------------------------------------------------------------------- // timer lib // ------------------------------------------------------------------------- // test procedure: // // ti = GetTickCount(); // SpinDelay(1000); // ti = GetTickCount() - ti; // Dbprintf("timer(1s): %d t=%d", ti, GetTickCount()); void StartTickCount() { // must be 0x40, but on my cpu - included divider is optimal // 0x20 - 1 ms / bit // 0x40 - 2 ms / bit AT91C_BASE_RTTC->RTTC_RTMR = AT91C_RTTC_RTTRST + 0x001D; // was 0x003B } /* * Get the current count. */ uint32_t RAMFUNC GetTickCount(){ return AT91C_BASE_RTTC->RTTC_RTVR;// was * 2; } // ------------------------------------------------------------------------- // microseconds timer // ------------------------------------------------------------------------- void StartCountUS() { AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14); // AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC1XC1S_TIOA0; AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE; // fast clock AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR | AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET; AT91C_BASE_TC0->TC_RA = 1; AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN; AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN; AT91C_BASE_TCB->TCB_BCR = 1; } uint32_t RAMFUNC GetCountUS(){ return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV / 15) * 10); } static uint32_t GlobalUsCounter = 0; uint32_t RAMFUNC GetDeltaCountUS(){ uint32_t g_cnt = GetCountUS(); uint32_t g_res = g_cnt - GlobalUsCounter; GlobalUsCounter = g_cnt; return g_res; } // ------------------------------------------------------------------------- // Mifare timer. Uses ssp_clk from FPGA // ------------------------------------------------------------------------- void StartCountMifare() { AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1) | (1 << AT91C_ID_TC2); // Enable Clock to all timers AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1 // XC0 Clock = TIOA1 | AT91C_TCB_TC1XC1S_NONE // XC1 Clock = none | AT91C_TCB_TC2XC2S_TIOA0; // XC2 Clock = TIOA0 // configure TC1 to create a short pulse on TIOA1 when a rising edge on TIOB1 (= ssp_clk from FPGA) occurs: AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // disable TC1 AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK // TC1 Clock = MCK(48MHz)/2 = 24MHz | AT91C_TC_CPCSTOP // Stop clock on RC compare | AT91C_TC_EEVTEDG_RISING // Trigger on rising edge of Event | AT91C_TC_EEVT_TIOB // Event-Source: TIOB1 (= ssc_clk from FPGA = 13,56MHz / 16) | AT91C_TC_ENETRG // Enable external trigger event | AT91C_TC_WAVESEL_UP // Upmode without automatic trigger on RC compare | AT91C_TC_WAVE // Waveform Mode | AT91C_TC_AEEVT_SET // Set TIOA1 on external event | AT91C_TC_ACPC_CLEAR; // Clear TIOA1 on RC Compare AT91C_BASE_TC1->TC_RC = 0x04; // RC Compare value = 0x04 // use TC0 to count TIOA1 pulses AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // disable TC0 AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_XC0 // TC0 clock = XC0 clock = TIOA1 | AT91C_TC_WAVE // Waveform Mode | AT91C_TC_WAVESEL_UP // just count | AT91C_TC_ACPA_CLEAR // Clear TIOA0 on RA Compare | AT91C_TC_ACPC_SET; // Set TIOA0 on RC Compare AT91C_BASE_TC0->TC_RA = 1; // RA Compare value = 1; pulse width to TC2 AT91C_BASE_TC0->TC_RC = 0; // RC Compare value = 0; increment TC2 on overflow // use TC2 to count TIOA0 pulses (giving us a 32bit counter (TC0/TC2) clocked by ssp_clk) AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKDIS; // disable TC2 AT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_XC2 // TC2 clock = XC2 clock = TIOA0 | AT91C_TC_WAVE // Waveform Mode | AT91C_TC_WAVESEL_UP; // just count AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN; // enable TC0 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN; // enable TC1 AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN; // enable TC2 AT91C_BASE_TCB->TCB_BCR = 1; // assert Sync (set all timers to 0 on next active clock edge) } uint32_t RAMFUNC GetCountMifare(){ uint32_t tmp_count; tmp_count = (AT91C_BASE_TC2->TC_CV << 16) | AT91C_BASE_TC0->TC_CV; if ((tmp_count & 0xffff) == 0) { //small chance that we may have missed an increment in TC2 return (AT91C_BASE_TC2->TC_CV << 16); } else { return tmp_count; } } ================================================ FILE: TamagotchiFriends/proxmark/armsrc/util.h ================================================ //----------------------------------------------------------------------------- // Jonathan Westhues, Aug 2005 // // This code is licensed to you under the terms of the GNU GPL, version 2 or, // at your option, any later version. See the LICENSE.txt file for the text of // the license. //----------------------------------------------------------------------------- // Utility functions used in many places, not specific to any piece of code. //----------------------------------------------------------------------------- #ifndef __UTIL_H #define __UTIL_H #include #include #include #define BYTEx(x, n) (((x) >> (n * 8)) & 0xff ) #define LED_RED 1 #define LED_ORANGE 2 #define LED_GREEN 4 #define LED_RED2 8 #define BUTTON_HOLD 1 #define BUTTON_NO_CLICK 0 #define BUTTON_SINGLE_CLICK -1 #define BUTTON_DOUBLE_CLICK -2 #define BUTTON_ERROR -99 size_t nbytes(size_t nbits); uint32_t SwapBits(uint32_t value, int nrbits); void num_to_bytes(uint64_t n, size_t len, uint8_t* dest); uint64_t bytes_to_num(uint8_t* src, size_t len); void SpinDelay(int ms); void SpinDelayUs(int us); void LED(int led, int ms); void LEDsoff(); int BUTTON_CLICKED(int ms); int BUTTON_HELD(int ms); void FormatVersionInformation(char *dst, int len, const char *prefix, void *version_information); void StartTickCount(); uint32_t RAMFUNC GetTickCount(); void StartCountUS(); uint32_t RAMFUNC GetCountUS(); uint32_t RAMFUNC GetDeltaCountUS(); void StartCountMifare(); uint32_t RAMFUNC GetCountMifare(); #endif ================================================ FILE: TamagotchiFriends/proxmark/armsrc/version.c ================================================ #include "proxmark3.h" /* Generated file, do not edit */ const struct version_information __attribute__((section(".version_information"))) version_information = { VERSION_INFORMATION_MAGIC, 1, 1, 0, "svn 756", "2014-03-01 20:34:43", }; ================================================ FILE: TamagotchiOn/tasmgotchi/demos/waitforbutton/myassembly.txt ================================================ PUSH {R4-R8,LR} SUB SP, SP, #0x20 MOV R0, #9 LDR R3, =(set_image_mode+1) MOV LR, PC BX R3 ; MOV R5, #0x40 ; '@' STR R5, [SP] MOV R3, R5 MOV R2, #0 LDR R1, =violetchi MOV R0, R2 LDR R4, =(show_game_image+1) MOV LR, PC BX R4 ; show_game_image LDR R1, =pressa MOV R0, #1 MOV R5, #0x40 ; '@' STR R5, [SP] MOV R3, R5 MOV R2, #0 LDR R4, =(show_game_image+1) MOV LR, PC BX R4 ; show_game_image MOV R1, #1 MOV R0, #0x1000 LDR R3, =(wait_for_button+1) MOV LR, PC BX R3 ; sub_20000932 MOV R7, R0 CMP R0, #1 MOV LR, PC BEQ pass CMP R7, #1 MOV LR, PC BNE lose MOV R5, #0x40 ; '@' STR R5, [SP] MOV R3, R5 MOV R2, #0 MOV R0, #1 LDR R1, =pressb LDR R4, =(show_game_image+1) MOV LR, PC BX R4 ; show_game_image MOV R1, #2 MOV R0, #0x1000 LDR R3, =(wait_for_button+1) MOV LR, PC BX R3 ; sub_20000932 MOV R7, R0 CMP R0, #1 MOV LR, PC BEQ pass CMP R7, #1 MOV LR, PC BNE lose MOV R5, #0x40 ; '@' STR R5, [SP] MOV R3, R5 MOV R2, #0 MOV R0, #1 LDR R1, =pressc LDR R4, =(show_game_image+1) MOV LR, PC BX R4 ; show_game_image MOV R1, #4 MOV R0, #0x1000 LDR R3, =(wait_for_button+1) MOV LR, PC BX R3 ; sub_20000932 MOV R7, R0 CMP R0, #1 MOV LR, PC BEQ pass CMP R7, #1 MOV LR, PC BNE lose B end lose: PUSH {R4-R8,LR} MOV R5, #0x40 STR R5, [SP] MOV R3, R5 MOV R2, #0 LDR R1, =ximg MOV R0, #1 LDR R4, =(show_game_image+1) MOV LR, PC BX R4 ; show_game_image MOV R1, #7 MOV R0, #0x300 LDR R3, =(wait_for_button+1) MOV LR, PC BX R3 ; sub_20000932 POP {R4-R8,LR} BX LR pass: PUSH {R4-R8,LR} MOV R5, #0x40 STR R5, [SP] MOV R3, R5 MOV R2, #0 LDR R1, =check MOV R0, #1 LDR R4, =(show_game_image+1) MOV LR, PC BX R4 ; show_game_image MOV R1, #7 MOV R0, #0x500 LDR R3, =(wait_for_button+1) MOV LR, PC BX R3 ; sub_20000932 POP {R4-R8,LR} BX LR end: ADD SP, SP, #0x20 ; POP {R4-R8,LR} MOV R0, #3 BX LR ================================================ FILE: TamagotchiOn/tasmgotchi/demos/waitforbutton/myimages.txt ================================================ violetchi /home/natashenka/Documents/violetchi_tama.bmp check /home/natashenka/Documents/check.bmp ximg /home/natashenka/Documents/x.bmp pressa /home/natashenka/Documents/pressa.bmp pressb /home/natashenka/Documents/pressb.bmp pressc /home/natashenka/Documents/pressc.bmp ================================================ FILE: TamagotchiOn/tasmgotchi/makegame.py ================================================ import sys try: import armasm except: print "armasm is required https://github.com/stephanh42/armasm" try: import Image except: print "PIL is required" from sets import Set if len(sys.argv) < 4: print "makegame.py assembly image_listing outfile" f = open("gametemp", 'rb') gtemp = f.read() f.close() index = 0x3690 gtemp = gtemp[:index] import random def addimage(path): global gtemp, index im = Image.open(path) px = im.load() s = Set() for y in range(0, im.height): for x in range(0, im.width): s.add(px[x,y]) if len(s) > 16: print "image" + path + " has too many colors" exit() while len(s) != 15: s.add((random.randrange(0, 255), 0, 0)) img = "" img = img + chr(im.width) + chr(im.height) # add width and height img = img + chr(len(s)&0xff) + chr(len(s)>>8) img = img + "\x01\xff" clist = [] j = 0 for item in s: clist.append(item) b = item[0]/8 r = item[2]/8 g = item[1]/4 b1 = (r <<3) + (g >> 3) b2 = ((g& 7) << 5) + b print "index", j, hex(b1), hex(b2), item j = j + 1 img = img + chr(b1) + chr(b2) p = "" for y in range(0, im.height): for x in range(0, im.width): #print px[x,y] v = clist.index(px[x,y]) if v > 16: print v exit() p = p + chr(v) t = "" i = 0 print "p", len(p) pad = False lasfull = 0 if im.width %2 != 0: pad = True lastfull = im.width/2*2 if(lastfull %2!=0): print "error" exit() while i < len(p)-1: #print hex(ord(p[i])) #print hex(ord(p[i+1])) #print(hex(ord(p[i]) + (ord(p[i+1])<<4))) if pad: if i % im.width == lastfull: t = t + chr(ord(p[i]) + 0) i = i + 1 else: t = t + chr(ord(p[i]) + (ord(p[i+1])<<4)) i = i + 2 else: t = t + chr(ord(p[i]) + (ord(p[i+1])<<4)) i = i + 2 img = img + t old_index = len(gtemp) gtemp = gtemp + img if len(gtemp)%4 !=0: index = index + (4-index%4) while len(gtemp) %4 != 0: gtemp = gtemp + '\x00' return 0x207F0000+ old_index ftable = {"show_game_image": 0x200008FE, "set_image_mode" : 0x20003B0E, "set_mem_0": 0x2000074E, "sub_20000A36" : 0x20000A36, "wait_for_button" : 0x20000932, "set_option_1" : 0x20000454, "set_option_2": 0x20000460, "set_option_3": 0x20000448, "check_option_1": 0x20000430, "check_option_2": 0x2000043C, "check_option_3": 0x20000424} itable = {} f = open(sys.argv[2], 'r') images = f.readlines() f.close() for item in images: i = item.split() if len(i) == 0: continue if(len(i) !=2): print "error splitting image" exit() name = i[0] loc = i[1] addr = addimage(loc) # print "image at", hex(addr) itable[name] = addr f = open(sys.argv[1]) assembly = f.read() f.close() for item in ftable: #print item assembly = assembly.replace("(" + item + "+1)", hex(ftable[item]+1)) for item in ftable: #print item assembly = assembly.replace(item, hex(ftable[item])) for item in itable: #print item assembly = assembly.replace(item, hex(itable[item])) #print assembly compiled = armasm.asm("str -> i", assembly) code = compiled.__armasm_code__ code_index = 0x336c cstr = "" for i in range(0, len(code)): num = code[i] cstr = cstr + chr(num&0xff) + chr((num&0xff00)>>8) + chr((num&0xff0000)>>16) + chr((num&0xff000000)>>24) print hex(code_index+len(cstr)) gtemp = gtemp[:code_index] + cstr + gtemp[code_index+len(cstr):] gamelen = len(gtemp) gls = chr((gamelen &0xff000000)>>24)+chr((gamelen &0xff0000)>>16)+chr((gamelen &0xff00)>>8)+chr(gamelen &0xff) gtemp = gtemp[:72]+gls+gtemp[76:] f = open(sys.argv[3], 'wb') f.write(gtemp) f.close() ================================================ FILE: codedump/README.txt ================================================ Code Dump Files binbits -- First 0x100 bytes of Tama code in binary decode.py -- SPI decoding code (not used) first100.txt -- First 0x100 bytes of Tama code dissasembled GPTestProgram -- GeneralPlus test program images -- Tamagotchi images from ROM in.txt -- Code execution POC ports.txt -- Known GPLB52640A ports so far. Please contribute /rompages -- The pages of the ROM Questions? Comments? Contributions? Contact: natashenka@kwartzlab.ca / @natashenka ================================================ FILE: codedump/decode.py ================================================ f = open("c.csv", 'r') o = open("c.bin", 'w') l = f.readlines() begin = True state = 1 val = 0 count = 8 c = 0 for item in l: c = c + 1 item = item[item.find(",")+1:] item = item[:item.find(",")] if state == 1: if item!= "0": print "error1 " + item + " " + str(c) state = 2 elif state == 2: if item!= "1": print "error2 " + item + " " + str(c) state = 2 else: state = 3 elif state == 3: if item == "0": val = val << 1 state = 2 else: val = (val << 1) | 1 state = 1 count = count - 1 if count == 0: count = 8 o.write(chr(val)) val = 0 ================================================ FILE: codedump/first100.txt ================================================ * = 0000 0000 78 SEI 0001 A2 FF LDX #$FF 0003 9A TXS 0004 A9 FF LDA #$FF 0006 8D 04 30 STA $3004 //I have no idea what port this is, but I'm sure setting it to ff is a great idea 0009 A9 82 LDA #$82 000B 8D 01 30 STA $3001 //This is clock control. Gotta keep those clocks under control 000E A9 80 LDA #$80 0010 8D 02 30 STA $3002 // This port controls the 32 k oscillator 0013 A9 00 LDA #$00 0015 8D 40 30 STA $3040 //LCD Setup 0018 A9 03 LDA #$03 001A 8D 4A 30 STA $304A //Not sure what this does (possible LCD related) 001D A9 10 LDA #$10 001F 8D 11 30 STA $3011 //make p0 out and rest in (weird, p0 is in by startup) 0022 A9 88 LDA #$88 0024 8D 10 30 STA $3010 //Port A config 0027 A9 1F LDA #$1F 0029 85 20 STA $20 //wonder what is here? 002B 8D 12 30 STA $3012 // data 002E A9 00 LDA #$00 0030 8D 13 30 STA $3013 // strobe 0033 A9 7E LDA #$7E 0035 8D 15 30 STA $3015 // possibly io for port b 0038 A9 01 LDA #$01 003A 8D 14 30 STA $3014 // possible config for port b 003D A9 07 LDA #$07 003F 85 21 STA $21 // not sure what this is either 0041 8D 16 30 STA $3016 //port b data? 0044 A2 00 LDX #$00 0046 A9 00 LDA #$00 0048 95 00 STA $00,X 004A E8 INX 004B D0 FB BNE $0048 // zero RAM i guess 004D A2 00 LDX #$00 004F A9 00 LDA #$00 0051 85 48 STA $48 // more mystery addresses 0053 A9 01 LDA #$01 0055 85 49 STA $49 //here too 0057 A9 00 LDA #$00 0059 85 4A STA $4A // and here 005B A9 06 LDA #$06 005D 85 4B STA $4B // and here 005F A5 48 LDA $48 0061 C5 4A CMP $4A 0063 D0 06 BNE $006B 0065 A5 49 LDA $49 0067 C5 4B CMP $4B 0069 F0 0D BEQ $0078 006B A9 00 LDA #$00 006D 81 48 STA ($48,X) 006F E6 48 INC $48 0071 D0 02 BNE $0075 0073 E6 49 INC $49 0075 4C 5F CC JMP $CC5F 0078 A2 00 LDX #$00 007A A9 00 LDA #$00 007C 85 48 STA $48 007E A9 10 LDA #$10 0080 85 49 STA $49 0082 A9 00 LDA #$00 0084 85 4A STA $4A 0086 A9 12 LDA #$12 0088 85 4B STA $4B 008A A5 48 LDA $48 008C C5 4A CMP $4A 008E D0 06 BNE $0096 0090 A5 49 LDA $49 0092 C5 4B CMP $4B 0094 F0 0D BEQ $00A3 0096 A9 00 LDA #$00 0098 81 48 STA ($48,X) 009A E6 48 INC $48 009C D0 02 BNE $00A0 009E E6 49 INC $49 00A0 4C 8A CC JMP $CC8A 00A3 A9 10 LDA #$10 00A5 8D 11 30 STA $3011 00A8 A9 88 LDA #$88 00AA 8D 10 30 STA $3010 00AD A9 1F LDA #$1F 00AF 85 20 STA $20 00B1 8D 12 30 STA $3012 00B4 A9 00 LDA #$00 00B6 8D 13 30 STA $3013 00B9 A9 7E LDA #$7E 00BB 8D 15 30 STA $3015 00BE A9 01 LDA #$01 00C0 8D 14 30 STA $3014 00C3 A9 07 LDA #$07 00C5 85 21 STA $21 00C7 8D 16 30 STA $3016 00CA A0 00 LDY #$00 00CC 20 60 D4 JSR $D460 00CF 20 60 D4 JSR $D460 00D2 20 60 D4 JSR $D460 00D5 20 60 D4 JSR $D460 00D8 20 60 D4 JSR $D460 00DB 20 60 D4 JSR $D460 00DE 20 60 D4 JSR $D460 00E1 20 60 D4 JSR $D460 00E4 88 DEY 00E5 D0 E5 BNE $00CC 00E7 20 09 E2 JSR $E209 00EA C9 07 CMP #$07 00EC D0 07 BNE $00F5 00EE A9 41 LDA #$41 00F0 85 22 STA $22 00F2 4C 94 CD JMP $CD94 00F5 A9 0E LDA #$0E 00F7 85 3A STA $3A 00F9 A9 83 LDA #$83 00FB 85 26 STA $26 00FD A9 B3 LDA #$B3 00FF 85 00 STA $00 0101 .END 0013 A9 00 LDA #$00 0015 8D 40 30 STA $3040 0018 A9 03 LDA #$03 001A 8D 4A 30 STA $304A 001D A9 10 LDA #$10 001F 8D 11 30 STA $3011 0022 A9 88 LDA #$88 0024 8D 10 30 STA $3010 0027 A9 1F LDA #$1F 0029 85 20 STA $20 002B 8D 12 30 STA $3012 002E A9 00 LDA #$00 0030 8D 13 30 STA $3013 0033 A9 7E LDA #$7E 0035 8D 15 30 STA $3015 0038 A9 01 LDA #$01 003A 8D 14 30 STA $3014 003D A9 07 LDA #$07 003F 85 21 STA $21 0041 8D 16 30 STA $3016 0044 A2 00 LDX #$00 0046 A9 00 LDA #$00 0048 95 00 STA $00,X 004A E8 INX 004B D0 FB BNE $0048 004D A2 00 LDX #$00 004F A9 00 LDA #$00 0051 85 48 STA $48 0053 A9 01 LDA #$01 0055 85 49 STA $49 0057 A9 00 LDA #$00 0059 85 4A STA $4A 005B A9 06 LDA #$06 005D 85 4B STA $4B 005F A5 48 LDA $48 0061 C5 4A CMP $4A 0063 D0 06 BNE $006B 0065 A5 49 LDA $49 0067 C5 4B CMP $4B 0069 F0 0D BEQ $0078 006B A9 00 LDA #$00 006D 81 48 STA ($48,X) 006F E6 48 INC $48 0071 D0 02 BNE $0075 0073 E6 49 INC $49 0075 4C 5F CC JMP $CC5F 0078 A2 00 LDX #$00 007A A9 00 LDA #$00 007C 85 48 STA $48 007E A9 10 LDA #$10 0080 85 49 STA $49 0082 A9 00 LDA #$00 0084 85 4A STA $4A 0086 A9 12 LDA #$12 0088 85 4B STA $4B 008A A5 48 LDA $48 008C C5 4A CMP $4A 008E D0 06 BNE $0096 0090 A5 49 LDA $49 0092 C5 4B CMP $4B 0094 F0 0D BEQ $00A3 0096 A9 00 LDA #$00 0098 81 48 STA ($48,X) 009A E6 48 INC $48 009C D0 02 BNE $00A0 009E E6 49 INC $49 00A0 4C 8A CC JMP $CC8A 00A3 A9 10 LDA #$10 00A5 8D 11 30 STA $3011 00A8 A9 88 LDA #$88 00AA 8D 10 30 STA $3010 00AD A9 1F LDA #$1F 00AF 85 20 STA $20 00B1 8D 12 30 STA $3012 00B4 A9 00 LDA #$00 00B6 8D 13 30 STA $3013 00B9 A9 7E LDA #$7E 00BB 8D 15 30 STA $3015 00BE A9 01 LDA #$01 00C0 8D 14 30 STA $3014 00C3 A9 07 LDA #$07 00C5 85 21 STA $21 00C7 8D 16 30 STA $3016 00CA A0 00 LDY #$00 00CC 20 60 D4 JSR $D460 00CF 20 60 D4 JSR $D460 00D2 20 60 D4 JSR $D460 00D5 20 60 D4 JSR $D460 00D8 20 60 D4 JSR $D460 00DB 20 60 D4 JSR $D460 00DE 20 60 D4 JSR $D460 00E1 20 60 D4 JSR $D460 00E4 88 DEY 00E5 D0 E5 BNE $00CC 00E7 20 09 E2 JSR $E209 00EA C9 07 CMP #$07 00EC D0 07 BNE $00F5 00EE A9 41 LDA #$41 00F0 85 22 STA $22 00F2 4C 94 CD JMP $CD94 00F5 A9 0E LDA #$0E 00F7 85 3A STA $3A 00F9 A9 83 LDA #$83 00FB 85 26 STA $26 00FD A9 B3 LDA #$B3 00FF 85 00 STA $00 0101 .END 000E A9 80 LDA #$80 0010 8D 02 30 STA $3002 0013 A9 00 LDA #$00 0015 8D 40 30 STA $3040 0018 A9 03 LDA #$03 001A 8D 4A 30 STA $304A 001D A9 10 LDA #$10 001F 8D 11 30 STA $3011 0022 A9 88 LDA #$88 0024 8D 10 30 STA $3010 0027 A9 1F LDA #$1F 0029 85 20 STA $20 002B 8D 12 30 STA $3012 002E A9 00 LDA #$00 0030 8D 13 30 STA $3013 0033 A9 7E LDA #$7E 0035 8D 15 30 STA $3015 0038 A9 01 LDA #$01 003A 8D 14 30 STA $3014 003D A9 07 LDA #$07 003F 85 21 STA $21 0041 8D 16 30 STA $3016 0044 A2 00 LDX #$00 0046 A9 00 LDA #$00 0048 95 00 STA $00,X 004A E8 INX 004B D0 FB BNE $0048 004D A2 00 LDX #$00 004F A9 00 LDA #$00 0051 85 48 STA $48 0053 A9 01 LDA #$01 0055 85 49 STA $49 0057 A9 00 LDA #$00 0059 85 4A STA $4A 005B A9 06 LDA #$06 005D 85 4B STA $4B 005F A5 48 LDA $48 0061 C5 4A CMP $4A 0063 D0 06 BNE $006B 0065 A5 49 LDA $49 0067 C5 4B CMP $4B 0069 F0 0D BEQ $0078 006B A9 00 LDA #$00 006D 81 48 STA ($48,X) 006F E6 48 INC $48 0071 D0 02 BNE $0075 0073 E6 49 INC $49 0075 4C 5F CC JMP $CC5F 0078 A2 00 LDX #$00 007A A9 00 LDA #$00 007C 85 48 STA $48 007E A9 10 LDA #$10 0080 85 49 STA $49 0082 A9 00 LDA #$00 0084 85 4A STA $4A 0086 A9 12 LDA #$12 0088 85 4B STA $4B 008A A5 48 LDA $48 008C C5 4A CMP $4A 008E D0 06 BNE $0096 0090 A5 49 LDA $49 0092 C5 4B CMP $4B 0094 F0 0D BEQ $00A3 0096 A9 00 LDA #$00 0098 81 48 STA ($48,X) 009A E6 48 INC $48 009C D0 02 BNE $00A0 009E E6 49 INC $49 00A0 4C 8A CC JMP $CC8A 00A3 A9 10 LDA #$10 00A5 8D 11 30 STA $3011 00A8 A9 88 LDA #$88 00AA 8D 10 30 STA $3010 00AD A9 1F LDA #$1F 00AF 85 20 STA $20 00B1 8D 12 30 STA $3012 00B4 A9 00 LDA #$00 00B6 8D 13 30 STA $3013 00B9 A9 7E LDA #$7E 00BB 8D 15 30 STA $3015 00BE A9 01 LDA #$01 00C0 8D 14 30 STA $3014 00C3 A9 07 LDA #$07 00C5 85 21 STA $21 00C7 8D 16 30 STA $3016 00CA A0 00 LDY #$00 00CC 20 60 D4 JSR $D460 00CF 20 60 D4 JSR $D460 00D2 20 60 D4 JSR $D460 00D5 20 60 D4 JSR $D460 00D8 20 60 D4 JSR $D460 00DB 20 60 D4 JSR $D460 00DE 20 60 D4 JSR $D460 00E1 20 60 D4 JSR $D460 00E4 88 DEY 00E5 D0 E5 BNE $00CC 00E7 20 09 E2 JSR $E209 00EA C9 07 CMP #$07 00EC D0 07 BNE $00F5 00EE A9 41 LDA #$41 00F0 85 22 STA $22 00F2 4C 94 CD JMP $CD94 00F5 A9 0E LDA #$0E 00F7 85 3A STA $3A 00F9 A9 83 LDA #$83 00FB 85 26 STA $26 00FD A9 B3 LDA #$B3 00FF 85 00 STA $00 0101 .END ================================================ FILE: codedump/ports.txt ================================================ Port Function Source 3000 ROM page Tamagotchi ROM dump (tested) 3001 Clock Control Data sheet 3002 Osc Control Application note 16 3007 Wakeup Control Application note 16 3010 Port A Config Application note 16 3011 Port A Dir Application note 16 3012 Port A Data Application note 16 3013 Port A Pull Application note 16 3014 Port B Config Tamagotchi ROM dump 3015 Port B Dir Tamagotchi ROM dump 3016 Port B Data Tamagotchi ROM dump 303e Seg 0-Seg7 Confirmation sheet 303f Seg8-seg15 Confirmation sheet 3040 LCD Setup Application note 16 3041 LCD Setup 2 Application note 16 3042 LCD Clock 1 Application note 16 3043 LCD Clock 2 Application note 16 3044 LCD Seg Num Application note 16 3045 LCD Com Num Application note 16 3047 LCD Buffer Control Application note 16 3049 LCD Pump Application note 16 ================================================ FILE: codedump/tf/eeprom5cd/eeprom5cd.ino ================================================ #include //I2C library byte somedata[]= { 0x0, 0xaa, 0x55, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x32, 0x17, 0x2, 0x1, 0x2, 0x1, 0xa, 0x0, 0x1a, 0x0, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, //300 0x20, 0x5, 0x6, 0x10, 0x1, 0xff, 0x01, 0x02, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, //310 0x77, 0x77, 0x77, 0x77, 0x77, 0x5, 0x4, 0x6, 0x77, 0x077, 0x55, 0xff, 0x77, 0x77, 0x77, 0x77, //320 0xff, 0xff, 0x40, 0xea, 0xea, 0xea, 0xea, 0xea, 0xea, 0xea, 0xea, 0xea, 0xea, 0xea, 0xea, 0xea, //330 0xea, 0x78, 0xa9, 0xff, 0x8d, 0x11, 0x30, 0x8d, 0x09, 0x11, 0x8d, 0xc5, 0x00, 0x8d, 0xc6, 0x00, //340 0xa2, 0x08, 0xb1, 0xc5, 0x0a, 0xa0, 0x01, 0x90, 0x02, 0xa0, 0x03, 0xd0, 0x04, 0xea, 0xea, 0xea, //350 330 is jump 0xea, 0xea, 0x8c, 0x12, 0x30, 0xa0, 0x00, 0x8c, 0x12, 0x30, 0xca, 0xd0, 0xe7, 0xee, 0xc5, 0x00, 0xd0, 0xde, 0xee, 0xc6, 0x00, //360 34b load 0xd0, 0xd9, 0xa9, 0x17, 0x8d, 0x00, 0x30, 0xd0, 0xd2, 0xc, 0x38, 0x03, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, //370 0xe, 0xd, 0x13, 0x7, 0xa, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2f, 0x2e, 0x31, 0x1f, 0x21, 0xff, 0xff, 0xff, 0xff, 0x3b, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1f, 0x29, 0x5, 0x0, 0x2, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x3, 0xdd, 0xdd, 0xdd, 0xdd, 0xf, 0xb, 0xff, 0x2, 0x8, 0x1, 0x8, 0xf0, 0xaa, 0x1a, 0x1a, 0x1, 0x1, 0x2, 0x3, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1f, 0x29, 0x0, 0x2, 0x1a, 0xff, 0x1a, 0x1a, 0x1a, 0x1a, 0x13, 0xdd, 0x8, 0x12, 0x1a, 0x8, 0x12, 0x1a, 0x0, 0x1a, 0x13, 0x4, 0x12, 0x13, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x1a, 0x2, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x1a, 0x2, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x1a, 0x2, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x1a, 0x2, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; void i2c_eeprom_write_byte( int deviceaddress, unsigned int eeaddress, byte data ) { int rdata = data; Wire.beginTransmission(deviceaddress); Wire.write((int)(eeaddress >> 8)); // MSB Wire.write((int)(eeaddress & 0xFF)); // LSB Wire.write(rdata); Wire.endTransmission(); } // WARNING: address is a page address, 6-bit end will wrap around // also, data can be maximum of about 30 bytes, because the Wire library has a buffer of 32 bytes void i2c_eeprom_write_page( int deviceaddress, unsigned int eeaddresspage, byte* data, byte length ) { Wire.beginTransmission(deviceaddress); Wire.write((int)(eeaddresspage >> 8)); // MSB Wire.write((int)(eeaddresspage & 0xFF)); // LSB byte c; for ( c = 0; c < length; c++) Wire.write(data[c]); Wire.endTransmission(); } byte i2c_eeprom_read_byte( int deviceaddress, unsigned int eeaddress ) { byte rdata = 0xFF; Wire.beginTransmission(deviceaddress); Wire.write((int)(eeaddress >> 8)); // MSB Wire.write((int)(eeaddress & 0xFF)); // LSB Wire.endTransmission(); Wire.requestFrom(deviceaddress,1); if (Wire.available()) rdata = Wire.read(); return rdata; } // maybe let's not read more than 30 or 32 bytes at a time! void i2c_eeprom_read_buffer( int deviceaddress, unsigned int eeaddress, byte *buffer, int length ) { Wire.beginTransmission(deviceaddress); Wire.write((int)(eeaddress >> 8)); // MSB Wire.write((int)(eeaddress & 0xFF)); // LSB Wire.endTransmission(); Wire.requestFrom(deviceaddress,length); int c = 0; for ( c = 0; c < length; c++ ) if (Wire.available()) buffer[c] = Wire.read(); } void setup() { int i; Wire.begin(); // initialise the connection delay(5000); for(i = 0; i < 200; i++){ Serial.print(i); i2c_eeprom_write_byte(0x50, i, somedata[i]); delay(10); } Serial.begin(9600); Serial.print(sizeof(somedata)); delay(5000); // i2c_eeprom_write_byte(0x50, 0x20, 0xaa ); //i2c_eeprom_write_page(0x50, 0, (byte *)somedata, sizeof(somedata)); // write to EEPROM //add a small delay Serial.println("Hello, Natalie"); Serial.println("Memory written"); } void loop() { Serial.begin(9600); Wire.begin(); int addr=0; //first address int i; byte b = i2c_eeprom_read_byte(0x50, 0); // access the first address from the memory for (i = 0; i < 4000; i++) { Serial.print(b, HEX); //print content to serial port Serial.print(" "); addr++; //increase address b = i2c_eeprom_read_byte(0x50, addr); //access an address from the memory } Serial.println(" "); delay(2000); while(true){} } ================================================ FILE: codedump/tf/glitch2/glitch2.ino ================================================ /* Blink Turns on an LED on for one second, then off for one second, repeatedly. This example code is in the public domain. */ // Pin 13 has an LED connected on most Arduino boards. // give it a name: int led = 13; // the setup routine runs once when you press reset: void setup() { // initialize the digital pin as an output. pinMode(led, OUTPUT); digitalWrite(led, HIGH); delay(10000); } // the loop routine runs over and over again forever: void loop() { // turn the LED on (HIGH is the voltage level) digitalWrite(led, HIGH); delay(1000); // wait for a second // digitalWrite(led, LOW); // turn the LED off by making the voltage LOW for(int i = 0; i < 35; i++){ digitalWrite(led, HIGH); delay(5); digitalWrite(led, LOW); delay(5); } digitalWrite(led, HIGH); while(true){} } ================================================ FILE: demos/README ================================================ Figure simulator demos facemain.c -- displays a picture nataliemain.c -- displays an animation nsdemomain.c -- displays static image harlemshake -- makes Tamagotchi do the Harlem Shake (figure image) mafd -- makes Tamagotchi play "Mad World" (figure image) Questions? Comments? Contributions? Contact: natashenka@kwartzlab.ca / @natashenka ================================================ FILE: demos/facemain.c ================================================ /** ****************************************************************************** * @file main.c * @author MCD Application Team * @version V1.0.0 * @date 19-September-2011 * @brief Main program body ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * *

© COPYRIGHT 2011 STMicroelectronics

****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ //#include "main.h" #include "stm32f4_discovery.h" //#include "stm32f4xx_it.c" uint8_t flag; //#include /** @addtogroup STM32F4-Discovery_Demo * @{ */ int i; /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ //#define CLK GPIO_Pin_11 //#define ADDRESS GPIO_Pin_10 //#define E GPIO_Pin_9 EXTI_InitTypeDef EXTI_InitStructure; /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ //uint32_t a = 0; //int i; int index; int started = 0; /* Private function prototypes -----------------------------------------------*/ GPIO_InitTypeDef GPIO_InitStructure; /* Private functions ---------------------------------------------------------*/ void EXTILine0_Config(void) { GPIO_InitTypeDef GPIO_InitStructure; NVIC_InitTypeDef NVIC_InitStructure; /* Enable GPIOA clock */ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); /* Enable SYSCFG clock */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); /* Configure PA0 pin as input floating */ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; GPIO_Init(GPIOA, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1; GPIO_Init(GPIOA, &GPIO_InitStructure); /* Connect EXTI Line0 to PA0 pin */ SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOA, EXTI_PinSource0); /* Configure EXTI Line0 */ EXTI_InitStructure.EXTI_Line = EXTI_Line0; EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; EXTI_InitStructure.EXTI_LineCmd = ENABLE; EXTI_Init(&EXTI_InitStructure); /* Enable and set EXTI Line0 Interrupt to the lowest priority */ NVIC_InitStructure.NVIC_IRQChannel = EXTI0_IRQn; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x01; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x01; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOA, EXTI_PinSource1); /* Configure EXTI Line0 */ EXTI_InitStructure.EXTI_Line = EXTI_Line1; EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; EXTI_InitStructure.EXTI_LineCmd = ENABLE; EXTI_Init(&EXTI_InitStructure); /* Enable and set EXTI Line0 Interrupt to the lowest priority */ NVIC_InitStructure.NVIC_IRQChannel = EXTI1_IRQn; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x02; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x01; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); } int loops = 0; int hit = 0; int q; int as[2000]; int read = 1; uint32_t a = 0; int acount = 0; uint8_t val; uint8_t c; uint8_t *vs[8]; uint8_t v1[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0x29, 0xc0, 0xff, 0xca, 0x9f, 0x28, 0xc0, 0xff, 0xca, 0xa7, 0x67, 0xc0, 0xff, 0xda, 0xa8, 0xa7, 0xc0, 0xff, 0xda, 0xaa, 0xa3, 0xc0, 0xff, 0x2a, 0xaa, 0x9f, 0xc0, 0xff, 0x69, 0xaa, 0x8f, 0xc0, 0xff, 0x65, 0xaa, 0x8f, 0xc0, 0xfc, 0xa4, 0xaa, 0x7f, 0xc0, 0xfd, 0xa0, 0xaa, 0x7f, 0xc0, 0xf2, 0xa3, 0x6a, 0x7f, 0xc0, 0xf2, 0x9f, 0x6a, 0x3f, 0xc0, 0xfa, 0x8f, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0}; uint8_t v2[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0x6a, 0x7f, 0xc0, 0xff, 0xfd, 0xaa, 0x3f, 0xc0, 0xff, 0xf2, 0xaa, 0x3f, 0xc0, 0xff, 0xf6, 0xa9, 0xff, 0xc0, 0xff, 0xda, 0xa9, 0xff, 0xc0, 0xff, 0x2a, 0xa9, 0xff, 0xc0, 0xff, 0x6a, 0xa8, 0xff, 0xc0, 0xfc, 0xa4, 0xa8, 0xff, 0xc0, 0xfd, 0xa0, 0xa7, 0xff, 0xc0, 0xf2, 0x91, 0xa7, 0xff, 0xc0, 0xfa, 0x82, 0xa7, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0}; uint8_t v3[] = { 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfa, 0xaa, 0xab, 0xc0, 0xff, 0xfa, 0xaa, 0xaf, 0xc0, 0xff, 0xfa, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xea, 0xbf, 0xff, 0xc0, 0xff, 0xea, 0xff, 0xff, 0xc0, 0xff, 0xea, 0xff, 0xff, 0xc0, 0xff, 0xaa, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0}; uint8_t v4[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xaa, 0xff, 0xc0, 0xff, 0xff, 0xab, 0xff, 0xc0, 0xff, 0xfe, 0xab, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xff, 0xff, 0xc0, 0xff, 0xea, 0xff, 0xff, 0xc0, 0xff, 0xeb, 0xff, 0xff, 0xc0, 0xff, 0xeb, 0xff, 0xff, 0xc0, 0xff, 0xab, 0xea, 0xff, 0xc0, 0xff, 0xaa, 0xaa, 0xff, 0xc0, 0xff, 0xaa, 0xaa, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0 }; uint8_t v5[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xea, 0xff, 0xc0, 0xff, 0xff, 0xea, 0xff, 0xc0, 0xff, 0xff, 0xeb, 0xff, 0xc0, 0xff, 0xff, 0xeb, 0xff, 0xc0, 0xff, 0xff, 0xab, 0xff, 0xc0, 0xff, 0xff, 0xaf, 0xff, 0xc0, 0xff, 0xff, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xbf, 0xff, 0xc0, 0xff, 0xfe, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0}; uint8_t v6[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xaa, 0xaa, 0xc0, 0xff, 0xff, 0xaa, 0xaa, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfa, 0xaa, 0xff, 0xc0, 0xff, 0xfa, 0xab, 0xff, 0xc0, 0xff, 0xfa, 0xff, 0xff, 0xc0, 0xff, 0xea, 0xff, 0xff, 0xc0, 0xff, 0xea, 0xff, 0xff, 0xc0, 0xff, 0xea, 0xab, 0xff, 0xc0, 0xff, 0xaa, 0xab, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0}; uint8_t v7[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xeb, 0xff, 0xc0, 0xff, 0xff, 0xab, 0xff, 0xc0, 0xff, 0xfe, 0xab, 0xff, 0xc0, 0xfe, 0xaa, 0xaa, 0xab, 0xc0, 0xff, 0xaa, 0xaa, 0xbf, 0xc0, 0xff, 0xea, 0xab, 0xff, 0xc0, 0xff, 0xea, 0xab, 0xff, 0xc0, 0xff, 0xaa, 0xab, 0xff, 0xc0, 0xff, 0xaf, 0xab, 0xff, 0xc0, 0xfe, 0xff, 0xeb, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0}; uint8_t v[] = { 0x0a, 0xaa, 0x55, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0-f 0x00, 0xaa, 0x55, 0x03, 0x03, 0x03, 0x00, 0x00, 0x10, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //10-f 0x40, 0x00, 0x00, 0xc4, 0x00, 0x00, 0xdc, 0x00, 0x00, 0x0f, 0x01, 0x00, 0x91, 0x01, 0x00, 0x0d, //20 0x02, 0x00, 0x89, 0x02, 0x00, 0xd1, 0x02, 0x00, 0x1f, 0x06, 0x00, 0x67, 0x0f, 0x00, 0x67, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //40 0x41, 0x12, 0x00, 0xa7, 0x12, 0x00, 0x0d, 0x13, 0x00, 0x73, 0x13, 0x00, 0xd9, 0x13, 0x00, 0x3f, 0x14, 0x00, 0xa5, 0x14, 0x00, 0x0b, 0x15, 0x00, 0x71, 0x15, 0x00, 0xd7, 0x15, 0x00, 0x3d, 0x16, 0x00, 0xa3, 0x16, 0x00, 0x09, 0x17, 0x00, 0x6f, 0x17, 0x00, 0xd5, 0x17, 0x00, 0x3b, 0x18, 0x00, 0xa1, 0x18, 0x00, 0x07, 0x19, 0x00, 0x6d, 0x19, 0x00, 0xd3, 0x19, 0x00, 0x39, 0x1a, 0x00, 0x9f, //80 0x1a, 0x00, 0x05, 0x1b, 0x00, 0x6b, 0x1b, 0x00, 0xd1, 0x1b, 0x00, 0x37, 0x1c, 0x00, 0x9d, 0x1c, //90 0x00, 0x13, 0x1e, 0x00, 0x89, 0x1f, 0x00, 0xff, 0x20, 0x00, 0x75, 0x22, 0x00, 0xeb, 0x23, 0x00, 0x61, 0x25, 0x00, 0xd7, 0x26, 0x00, 0x4d, 0x28, 0x00, 0xeb, 0x28, 0x00, 0x89, 0x29, 0x00, 0x64, //b0 0x2a, 0x00, 0xa2, 0x2a, 0x00, 0xe0, 0x2a, 0x00, 0x1e, 0x2b, 0x00, 0x5c, 0x2b, 0x00, 0xce, 0x00, //c0 0x00, 0xce, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x44, 0x12, 0x34, 0x30, 0x1f,// max:0x50, 0x20, //d0 0x2a, 0xaa, 0xaa, 0xaa, 0xa8, 0x1, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x2a, 0xaa, 0xaa, 0xaa, 0xa8, 0x0, 0x6a, 0xaa, 0xaa, 0xaa, 0xa9, 0x0, 0x2a, 0xaa, 0xaa, 0xaa, 0xa9, 0x0, 0x2a, 0xaa, 0xaa, 0xa0, 0x0, 0x0, 0x2a, 0xaa, 0xaa, 0xaa, 0xa9, 0x0, 0xa, 0x6a, 0xa8, 0x0, 0x0, 0x0, 0x2a, 0xaa, 0xaa, 0xaa, 0xa9, 0x0, 0x0, 0x2a, 0xaa, 0x0, 0x0, 0x0, 0x2a, 0xaa, 0xaa, 0xaa, 0xa8, 0x0, 0x0, 0x4, 0x0, 0x0, 0x0, 0x0, 0x2a, 0xaa, 0xaa, 0xaa, 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2a, 0xaa, 0xaa, 0xaa, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2a, 0xaa, 0xa4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2a, 0xaa, 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6a, 0xaa, 0x40, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6a, 0xaa, 0x40, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xaa, 0xaa, 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xaa, 0xaa, 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xaa, 0xaa, 0x80, 0x0, 0x0, 0x0, 0x0, 0x10, 0x0, 0x0, 0x0, 0x0, 0xaa, 0xaa, 0x90, 0x0, 0x0, 0x0, 0x0, 0x10, 0x0, 0x0, 0x0, 0x0, 0xaa, 0xaa, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x10, 0x0, 0x0, 0x0, 0x1, 0xaa, 0xaa, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x20, 0x0, 0x0, 0x0, 0x1, 0xaa, 0xaa, 0xa4, 0x0, 0x0, 0x0, 0x1a, 0xa0, 0x0, 0x0, 0x0, 0x2, 0xaa, 0xaa, 0xa8, 0x0, 0x0, 0x0, 0x11, 0x0, 0x0, 0x0, 0x0, 0x2, 0xaa, 0xaa, 0xa8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, 0xaa, 0xaa, 0xaa, 0x0, 0x0, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, 0xaa, 0xaa, 0xaa, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0x6a, 0xaa, 0xaa, 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1a, 0x2a, 0xaa, 0xaa, 0x80, 0x0, 0x0, 0x0, 0x0, 0xa4, 0x0, 0x0, 0x2a, 0x2a, 0xaa, 0xaa, 0xa0, 0x4, 0x2a, 0xaa, 0xaa, 0xa9, 0x0, 0x0, 0x6a, 0x2a, 0xaa, 0xaa, 0xa4, 0xa, 0xaa, 0xaa, 0xa9, 0x0, 0x0, 0x0, 0xaa, 0x2a, 0xaa, 0xaa, 0xa8, 0x0, 0x1a, 0xaa, 0x80, 0x0, 0x0, 0x1, 0xaa, 0x1a, 0xaa, 0xaa, 0xaa, 0x0, 0xa, 0xaa, 0x80, 0x0, 0x0, 0x2, 0xaa, 0xa, 0xaa, 0xaa, 0xaa, 0x80, 0xa, 0xaa, 0x90, 0x0, 0x0, 0x6, 0xaa, 0xa, 0xaa, 0xaa, 0xaa, 0x90, 0x1, 0xaa, 0xa4, 0x0, 0x0, 0x1a, 0xaa, 0x8a, 0xaa, 0x86, 0xa8, 0x24, 0x0, 0xaa, 0x50, 0x0, 0x0, 0x6a, 0xaa, // 0x0, 0xcf, 0xff, 0x0, 0x0, 0x0, 0x0, 0xcf, 0xff, 0x0, 0x0, 0x0, 0x0, // 0xcf, 0xff, 0x0, 0x0, 0xc, 0xff, 0xff, 0xff, 0x0, 0x0, 0xff, 0xff, // 0xff, 0xff, 0x0, 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, //0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, // 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, // 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, 0x0, 0x0, 0x0, 0xC0, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0x00, 0x00, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFA, 0xAA, 0xAB, 0xC0, 0xFF, 0xE5, 0x55, 0x5A, 0xC0, 0x00, 0xE5, 0x55, 0x5A, 0xC0, 0xFF, 0x95, 0x55, 0x66, 0xC0, 0xFF, 0xAA, 0xAA, 0xA6, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x8A, 0x28, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x8A, 0x28, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0xAA, 0xAA, 0xAB, 0xC0, 0x11, 0x15, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0x00, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFA, 0xAA, 0xAB, 0xC0, 0xFF, 0xE5, 0x55, 0x5A, 0xC0, 0xFF, 0xE5, 0x55, 0x5A, 0xC0, 0xFF, 0x95, 0x55, 0x66, 0xC0, 0xFF, 0xAA, 0xAA, 0xA6, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x8A, 0x28, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x8A, 0x28, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0xAA, 0xAA, 0xAB, 0xC0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};// 0x70, 0x2c, 0x00, 0x82, 0x2c, 0x00, 0x90, 0x2c, 0x00, 0x9e, 0x2c, 0x00, 0xb0, 0x2c, 0x00, 0xc2, 0x2c, 0x00, 0xd4, 0x2c, 0x00, 0xe6, 0x2c, 0x00, 0xe9, 0x2c, 0x00, 0x1b, 0x2d, 0x00, 0x4d, 0x2d, 0x00, 0x7f, 0x2d, 0x00, 0xb1, 0x2d, 0x00, 0xe3, 0x2d, 0x00, 0x15, 0x2e, 0x00, 0x27, 0x2e, 0x00, 0x39, 0x2e, 0x00, 0x4b, 0x2e, 0x00, 0x6c, 0x2e, 0x00, 0x73, 0x2e, 0x00, 0xb5, 0x2e, 0x00, 0xf7, 0x2e, 0x00, 0x21, 0x2f, 0x00, 0x5f, 0x2f, 0x00, 0xc1, 0x2f, 0x00, 0x02, 0x00, 0x06, 0x03, 0x04, 0x09, 0x0a, 0x05, 0x08, 0x07, 0x00, 0x00, 0x58, 0x00, 0x00, 0x32, 0x00, 0x00, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x10, 0x00, 0x00, 0x08, 0x00, 0x00, 0x50, 0x04, 0x00, 0x30, 0x02, 0x00, 0x20, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00, 0x50, 0x08, 0x00, 0x50, 0x11, 0x00, 0x00, 0x00, 0x28, 0x00, 0x40, 0x15, 0x00, 0x60, 0x12, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x45, 0x00, 0x00, 0x35, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x22, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00, 0x22, 0x00, 0x00, 0x13, 0x00, 0x01, 0x00, 0x02, 0x00, 0x50, 0x01, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x04, 0xff, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x02, 0xff, 0x01, 0x01, 0x00, 0x1e, 0x01, 0x00, 0x03, 0xff, 0x01, 0x01, 0x00, 0x2d, 0x01, 0x00, 0x04, 0xfe, 0x01, 0x01, 0x00, 0x3c, 0x01, 0x00, 0x05, 0xfe, 0x01, 0x01, 0x00, 0x4b, 0x02, 0x00, 0x06, 0xfe, 0x02, 0x02, 0x00, 0x5a, 0x02, 0x00, 0x07, 0xfd, 0x02, 0x02, 0x00, 0x63, 0x02, 0x00, 0x08, 0xfd, 0x02, 0x02, 0x00, 0x64, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0x00, 0x02, 0x04, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x02, 0xff, 0x01, 0x01, 0x00, 0x0f, 0x01, 0x00, 0x03, 0xff, 0x01, 0x01, 0x00, 0x19, 0x01, 0x00, 0x04, 0xfe, 0x01, 0x01, 0x00, 0x23, 0x01, 0x00, 0x05, 0xfe, 0x01, 0x02, 0x00, 0x2d, 0x02, 0x00, 0x06, 0xfe, 0x02, 0x02, 0x00, 0x37, 0x02, 0x00, 0x07, 0xfd, 0x02, 0x02, 0x00, 0x40, 0x02, 0x00, 0x08, 0xfd, 0x02, 0x02, 0x00, 0x41, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xc4, 0x2f, 0x00, 0xff, 0xff, 0xff, 0x06, 0x30, 0x00, 0x48, 0x30, 0x00, 0x8a, 0x30, 0x00, 0xcc, 0x30, 0x00, 0x0e, 0x31, 0x00, 0x50, 0x31, 0x00, 0x92, 0x31, 0x00, 0xd4, 0x31, 0x00, 0x16, 0x32, 0x00, 0xff, 0xff, 0xff, 0x58, 0x32, 0x00, 0xff, 0xff, 0xff, 0xba, 0x32, 0x00, 0x1c, 0x33, 0x00, 0x7e, 0x33, 0x00, 0xe0, 0x33, 0x00, 0x42, 0x34, 0x00, 0xa4, 0x34, 0x00, 0x06, 0x35, 0x00, 0x68, 0x35, 0x00, 0xca, 0x35, 0x00, 0xff, 0xff, 0xff, 0x2c, 0x36, 0x00, 0x3e, 0x36, 0x00, 0x80, 0x36, 0x00, 0xc2, 0x36, 0x00, 0x04, 0x37, 0x00, 0x46, 0x37, 0x00, 0x88, 0x37, 0x00, 0xca, 0x37, 0x00, 0x24, 0x38, 0x00, 0x9d, 0x38, 0x00, 0xf9, 0x38, 0x00, 0x7d, 0x39, 0x00, 0xd7, 0x39, 0x00, 0x50, 0x3a, 0x00, 0xac, 0x3a, 0x00, 0x30, 0x3b, 0x00, 0x72, 0x3b, 0x00, 0xb4, 0x3b, 0x00, 0xf6, 0x3b, 0x00, 0x38, 0x3c, 0x00, 0x7a, 0x3c, 0x00, 0xbc, 0x3c, 0x00, 0xfe, 0x3c, 0x00, 0x40, 0x3d, 0x00, 0x3a, 0x3e, 0x00, 0x34, 0x3f, 0x00, 0x2e, 0x40, 0x00, 0x28, 0x41, 0x00, 0x22, 0x42, 0x00, 0x98, 0x43, 0x00, 0xea, 0x43, 0x00, 0x3c, 0x44, 0x00, 0x8e, 0x44, 0x00, 0xe0, 0x44, 0x00, 0x32, 0x45, 0x00, 0x84, 0x45, 0x00, 0x7e, 0x46, 0x00, 0x78, 0x47, 0x00, 0xba, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0x76, 0x48, 0x00, 0xf0, 0x48, 0x00, 0x6a, 0x49, 0x00, 0xe4, 0x49, 0x00, 0x5e, 0x4a, 0x00, 0xd8, 0x4a, 0x00, 0x52, 0x4b, 0x00, 0xcc, 0x4b, 0x00, 0x46, 0x4c, 0x00, 0xc0, 0x4c, 0x00, 0x3a, 0x4d, 0x00, 0xb4, 0x4d, 0x00, 0x2e, 0x4e, 0x00, 0xa8, 0x4e, 0x00, 0x22, 0x4f, 0x00, 0x9c, 0x4f, 0x00, 0x16, 0x50, 0x00, 0x90, 0x50, 0x00, 0x0a, 0x51, 0x00, 0x84, 0x51, 0x00, 0xfe, 0x51, 0x00, 0x78, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0x6c, 0x53, 0x00, 0xe6, 0x53, 0x00, 0x60, 0x54, 0x00, 0xda, 0x54, 0x00, 0x54, 0x55, 0x00, 0xce, 0x55, 0x00, 0x48, 0x56, 0x00, 0xc2, 0x56, 0x00, 0x3c, 0x57, 0x00, 0xb6, 0x57, 0x00, 0x30, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0x24, 0x59, 0x00, 0x9e, 0x59, 0x00, 0x18, 0x5a, 0x00, 0x92, 0x5a, 0x00, 0x0c, 0x5b, 0x00, 0x86, 0x5b, 0x00, 0x00, 0x5c, 0x00, 0x7a, 0x5c, 0x00, 0xf4, 0x5c, 0x00, 0x6e, 0x5d, 0x00, 0xe8, 0x5d, 0x00, 0x62, 0x5e, 0x00, 0xdc, 0x5e, 0x00, 0x56, 0x5f, 0x00, 0xd0, 0x5f, 0x00, 0x4a, 0x60, 0x00, 0xc4, 0x60, 0x00, 0x3e, 0x61, 0x00, 0xb8, 0x61, 0x00, 0x32, 0x62, 0x00, 0xac, 0x62, 0x00, 0x26, 0x63, 0x00, 0xa0, 0x63, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x94, 0x64, 0x00, 0x0e, 0x65, 0x00, 0x88, 0x65, 0x00, 0x02, 0x66, 0x00, 0x7c, 0x66, 0x00, 0xf6, 0x66, 0x00, 0x70, 0x67, 0x00, 0xea, 0x67, 0x00, 0x64, 0x68, 0x00, 0xde, 0x68, 0x00, 0x58, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0x4c, 0x6a, 0x00, 0xc6, 0x6a, 0x00, 0x40, 0x6b, 0x00, 0xba, 0x6b, 0x00, 0x34, 0x6c, 0x00, 0xae, 0x6c, 0x00, 0x28, 0x6d, 0x00, 0xa2, 0x6d, 0x00, 0x1c, 0x6e, 0x00, 0x96, 0x6e, 0x00, 0x10, 0x6f, 0x00, 0x8a, 0x6f, 0x00, 0x04, 0x70, 0x00, 0x7e, 0x70, 0x00, 0xf8, 0x70, 0x00, 0x72, 0x71, 0x00, 0xec, 0x71, 0x00, 0x66, 0x72, 0x00, 0xe0, 0x72, 0x00, 0x5a, 0x73, 0x00, 0xd4, 0x73, 0x00, 0x4e, 0x74, 0x00, 0xc8, 0x74, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0xbc, 0x75, 0x00, 0x36, 0x76, 0x00, 0xb0, 0x76, 0x00, 0x2a, 0x77, 0x00, 0xa4, 0x77, 0x00, 0x1e, 0x78, 0x00, 0x98, 0x78, 0x00, 0x12, 0x79, 0x00, 0x8c, 0x79, 0x00, 0x06, 0x7a, 0x00, 0x80, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0x74, 0x7b, 0x00, 0xe2, 0x7b, 0x00, 0x50, 0x7c, 0x00, 0xbe, 0x7c, 0x00, 0x2c, 0x7d, 0x00, 0x9a, 0x7d, 0x00, 0x08, 0x7e, 0x00, 0x76, 0x7e, 0x00, 0xe4, 0x7e, 0x00, 0x52, 0x7f, 0x00, 0xc0, 0x7f, 0x00, 0x2e, 0x80, 0x00, 0x9c, 0x80, 0x00, 0x0a, 0x81, 0x00, 0x78, 0x81, 0x00, 0xe6, 0x81, 0x00, 0x54, 0x82, 0x00, 0xc2, 0x82, 0x00, 0x30, 0x83, 0x00, 0x9e, 0x83, 0x00, 0x0c, 0x84, 0x00, 0x7a, 0x84, 0x00, 0xe8, 0x84, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0xc4, 0x85, 0x00, 0x32, 0x86, 0x00, 0xa0, 0x86, 0x00, 0x0e, 0x87, 0x00, 0x7c, 0x87, 0x00, 0xea, 0x87, 0x00, 0x58, 0x88, 0x00, 0xc6, 0x88, 0x00, 0x34, 0x89, 0x00, 0xa2, 0x89, 0x00, 0x10, 0x8a, 0x00, 0x7e, 0x8a, 0x00, 0xec, 0x8a, 0x00, 0x2e, 0x8b, 0x00, 0xac, 0x8b, 0x00, 0x2a, 0x8c, 0x00, 0xa8, 0x8c, 0x00, 0x26, 0x8d, 0x00, 0xa4, 0x8d, 0x00, 0x22, 0x8e, 0x00, 0xa0, 0x8e, 0x00, 0x1e, 0x8f, 0x00, 0x60, 0x8f, 0x00, 0xa2, 0x8f, 0x00, 0xe4, 0x8f, 0x00, 0x13, 0x90, 0x00, 0x42, 0x90, 0x00, 0x65, 0x90, 0x00, 0x88, 0x90, 0x00, 0xab, 0x90, 0x00, 0xce, 0x90, 0x00, 0xf1, 0x90, 0x00, 0x57, 0x91, 0x00, 0xbd, 0x91, 0x00, 0x23, 0x92, 0x00, 0x89, 0x92, 0x00, 0xef, 0x92, 0x00, 0x55, 0x93, 0x00, 0xbb, 0x93, 0x00, 0x21, 0x94, 0x00, 0x87, 0x94, 0x00, 0xed, 0x94, 0x00, 0x53, 0x95, 0x00, 0xb9, 0x95, 0x00, 0x1f, 0x96, 0x00, 0x85, 0x96, 0x00, 0xeb, 0x96, 0x00, 0x51, 0x97, 0x00, 0xb7, 0x97, 0x00, 0x1d, 0x98, 0x00, 0x83, 0x98, 0x00, 0xe9, 0x98, 0x00, 0x4f, 0x99, 0x00, 0xb5, 0x99, 0x00, 0x1b, 0x9a, 0x00, 0x81, 0x9a, 0x00, 0xe7, 0x9a, 0x00, 0x4d, 0x9b, 0x00, 0xb3, 0x9b, 0x00, 0x19, 0x9c, 0x00, 0x7f, 0x9c, 0x00, 0xe5, 0x9c, 0x00, 0x4b, 0x9d, 0x00, 0xb1, 0x9d, 0x00, 0x17, 0x9e, 0x00, 0x7d, 0x9e, 0x00, 0xe3, 0x9e, 0x00, 0x49, 0x9f, 0x00, 0xaf, 0x9f, 0x00, 0x15, 0xa0, 0x00, 0x7b, 0xa0, 0x00, 0xe1, 0xa0, 0x00, 0x47, 0xa1, 0x00, 0xad, 0xa1, 0x00, 0x13, 0xa2, 0x00, 0x79, 0xa2, 0x00, 0xdf, 0xa2, 0x00, 0x45, 0xa3, 0x00, 0xab, 0xa3, 0x00, 0x11, 0xa4, 0x00, 0x77, 0xa4, 0x00, 0xdd, 0xa4, 0x00, 0x43, 0xa5, 0x00, 0xa9, 0xa5, 0x00, 0x0f, 0xa6, 0x00, 0x75, 0xa6, 0x00, 0xdb, 0xa6, 0x00, 0x41, 0xa7, 0x00, 0xa7, 0xa7, 0x00, 0x0d, 0xa8, 0x00, 0x73, 0xa8, 0x00, 0xd9, 0xa8, 0x00, 0x3f, 0xa9, 0x00, 0xa5, 0xa9, 0x00, 0x0b, 0xaa, 0x00, 0x71, 0xaa, 0x00, 0xd7, 0xaa, 0x00, 0x3d, 0xab, 0x00, 0xa3, 0xab, 0x00, 0x09, 0xac, 0x00, 0x6f, 0xac, 0x00, 0xd5, 0xac, 0x00, 0x3b, 0xad, 0x00, 0xa1, 0xad, 0x00, 0x07, 0xae, 0x00, 0x6d, 0xae, 0x00, 0xd3, 0xae, 0x00, 0x39, 0xaf, 0x00, 0x9f, 0xaf, 0x00, 0x05, 0xb0, 0x00, 0x6b, 0xb0, 0x00, 0xd1, 0xb0, 0x00, 0x37, 0xb1, 0x00, 0x9d, 0xb1, 0x00, 0x03, 0xb2, 0x00, 0x69, 0xb2, 0x00, 0xcf, 0xb2, 0x00, 0x35, 0xb3, 0x00, 0x9b, 0xb3, 0x00, 0x01, 0xb4, 0x00, 0x67, 0xb4, 0x00, 0xcd, 0xb4, 0x00, 0x33, 0xb5, 0x00, 0x99, 0xb5, 0x00, 0xff, 0xb5, 0x00, 0x65, 0xb6, 0x00, 0xcb, 0xb6, 0x00, 0x31, 0xb7, 0x00, 0x97, 0xb7, 0x00, 0xfd, 0xb7, 0x00, 0x63, 0xb8, 0x00, 0xc9, 0xb8, 0x00, 0x2f, 0xb9, 0x00, 0x95, 0xb9, 0x00, 0xfb, 0xb9, 0x00, 0x61, 0xba, 0x00, 0xc7, 0xba, 0x00, 0x2d, 0xbb, 0x00, 0x93, 0xbb, 0x00, 0xf9, 0xbb, 0x00, 0x5f, 0xbc, 0x00, 0xc5, 0xbc, 0x00, 0x2b, 0xbd, 0x00, 0x91, 0xbd, 0x00, 0xf7, 0xbd, 0x00, 0x5d, 0xbe, 0x00, 0xc3, 0xbe, 0x00, 0x29, 0xbf, 0x00, 0x8f, 0xbf, 0x00, 0xf5, 0xbf, 0x00, 0x5b, 0xc0, 0x00, 0xc1, 0xc0, 0x00, 0x27, 0xc1, 0x00, 0x8d, 0xc1, 0x00, 0xf3, 0xc1, 0x00, 0x59, 0xc2, 0x00, 0xbf, 0xc2, 0x00, 0x25, 0xc3, 0x00, 0x8b, 0xc3, 0x00, 0xf1, 0xc3, 0x00, 0x57, 0xc4, 0x00, 0xbd, 0xc4, 0x00, 0x23, 0xc5, 0x00, 0x89, 0xc5, 0x00, 0xef, 0xc5, 0x00, 0x55, 0xc6, 0x00, 0xbb, 0xc6, 0x00, 0x21, 0xc7, 0x00, 0x87, 0xc7, 0x00, 0xed, 0xc7, 0x00, 0x53, 0xc8, 0x00, 0xb9, 0xc8, 0x00, 0x1f, 0xc9, 0x00, 0x85, 0xc9, 0x00, 0xeb, 0xc9, 0x00, 0x51, 0xca, 0x00, 0xb7, 0xca, 0x00, 0x1d, 0xcb, 0x00, 0x83, 0xcb, 0x00, 0xe9, 0xcb, 0x00, 0x4f, 0xcc, 0x00, 0xb5, 0xcc, 0x00, 0x1b, 0xcd, 0x00, 0x81, 0xcd, 0x00, 0xe7, 0xcd, 0x00, 0x4d, 0xce, 0x00, 0xb3, 0xce, 0x00, 0x19, 0xcf, 0x00, 0x7f, 0xcf, 0x00, 0xe5, 0xcf, 0x00, 0x4b, 0xd0, 0x00, 0xb1, 0xd0, 0x00, 0x17, 0xd1, 0x00, 0x7d, 0xd1, 0x00, 0xe3, 0xd1, 0x00, 0x49, 0xd2, 0x00, 0xaf, 0xd2, 0x00, 0x15, 0xd3, 0x00, 0x7b, 0xd3, 0x00, 0xe1, 0xd3, 0x00, 0x47, 0xd4, 0x00, 0xad, 0xd4, 0x00, 0x13, 0xd5, 0x00, 0x79, 0xd5, 0x00, 0xdf, 0xd5, 0x00, 0x45, 0xd6, 0x00, 0xab, 0xd6, 0x00, 0x11, 0xd7, 0x00, 0x77, 0xd7, 0x00, 0xdd, 0xd7, 0x00, 0x43, 0xd8, 0x00, 0xa9, 0xd8, 0x00, 0x0f, 0xd9, 0x00, 0x75, 0xd9, 0x00, 0xdb, 0xd9, 0x00, 0x41, 0xda, 0x00, 0xa7, 0xda, 0x00, 0x0d, 0xdb, 0x00, 0x73, 0xdb, 0x00, 0xd9, 0xdb, 0x00, 0x3f, 0xdc, 0x00, 0xa5, 0xdc, 0x00, 0x0b, 0xdd, 0x00, 0x71, 0xdd, 0x00, 0xd7, 0xdd, 0x00, 0x3d, 0xde, 0x00, 0xa3, 0xde, 0x00, 0x09, 0xdf, 0x00, 0x6f, 0xdf, 0x00, 0xd5, 0xdf, 0x00, 0x3b, 0xe0, 0x00, 0xa1, 0xe0, 0x00, 0x07, 0xe1, 0x00, 0x6d, 0xe1, 0x00, 0xd3, 0xe1, 0x00, 0x39, 0xe2, 0x00, 0x9f, 0xe2, 0x00, 0x05, 0xe3, 0x00, 0x6b, 0xe3, 0x00, 0xd1, 0xe3, 0x00, 0x37, 0xe4, 0x00, 0x9d, 0xe4, 0x00, 0x03, 0xe5, 0x00, 0x69, 0xe5, 0x00, 0xcf, 0xe5, 0x00, 0x35, 0xe6, 0x00, 0x9b, 0xe6, 0x00, 0x01, 0xe7, 0x00, 0x67, 0xe7, 0x00, 0xcd, 0xe7, 0x00, 0x33, 0xe8, 0x00, 0x99, 0xe8, 0x00, 0xff, 0xe8, 0x00, 0x65, 0xe9, 0x00, 0xcb, 0xe9, 0x00, 0x31, 0xea, 0x00, 0x97, 0xea, 0x00, 0xfd, 0xea, 0x00, 0x63, 0xeb, 0x00, 0xc9, 0xeb, 0x00, 0x2f, 0xec, 0x00, 0x95, 0xec, 0x00, 0xfb, 0xec, 0x00, 0x61, 0xed, 0x00, 0xc7, 0xed, 0x00, 0x2d, 0xee, 0x00, 0x93, 0xee, 0x00, 0xf9, 0xee, 0x00, 0x5f, 0xef, 0x00, 0xc5, 0xef, 0x00, 0x2b, 0xf0, 0x00, 0x91, 0xf0, 0x00, 0xf7, 0xf0, 0x00, 0x5d, 0xf1, 0x00, 0xc3, 0xf1, 0x00, 0x29, 0xf2, 0x00, 0x8f, 0xf2, 0x00, 0xf5, 0xf2, 0x00, 0x5b, 0xf3, 0x00, 0xc1, 0xf3, 0x00, 0x27, 0xf4, 0x00, 0x8d, 0xf4, 0x00, 0xf3, 0xf4, 0x00, 0x59, 0xf5, 0x00, 0xbf, 0xf5, 0x00, 0x25, 0xf6, 0x00, 0x8b, 0xf6, 0x00, 0xf1, 0xf6, 0x00, 0x57, 0xf7, 0x00, 0xbd, 0xf7, 0x00, 0x23, 0xf8, 0x00, 0x89, 0xf8, 0x00, 0xef, 0xf8, 0x00, 0x55, 0xf9, 0x00, 0xbb, 0xf9, 0x00, 0x21, 0xfa, 0x00, 0x87, 0xfa, 0x00, 0xed, 0xfa, 0x00, 0x53, 0xfb, 0x00, 0xb9, 0xfb, 0x00, 0x1f, 0xfc, 0x00, 0x85, 0xfc, 0x00, 0xeb, 0xfc, 0x00, 0x51, 0xfd, 0x00, 0xb7, 0xfd, 0x00, 0x1d, 0xfe, 0x00, 0x83, 0xfe, 0x00, 0xe9, 0xfe, 0x00, 0x4f, 0xff, 0x00, 0xb5, 0xff, 0x00, 0x1b, 0x00, 0x01, 0x81, 0x00, 0x01, 0xe7, 0x00, 0x01, 0x4d, 0x01, 0x01, 0xb3, 0x01, 0x01, 0x19, 0x02, 0x01, 0x7f, 0x02, 0x01, 0xe5, 0x02, 0x01, 0x4b, 0x03, 0x01, 0xb1, 0x03, 0x01, 0x17, 0x04, 0x01, 0x7d, 0x04, 0x01, 0xe3, 0x04, 0x01, 0x49, 0x05, 0x01, 0xaf, 0x05, 0x01, 0x15, 0x06, 0x01, 0x7b, 0x06, 0x01, 0xe1, 0x06, 0x01, 0x47, 0x07, 0x01, 0xad, 0x07, 0x01, 0x13, 0x08, 0x01, 0x79, 0x08, 0x01, 0xdf, 0x08, 0x01, 0x45, 0x09, 0x01, 0xab, 0x09, 0x01, 0x11, 0x0a, 0x01, 0x77, 0x0a, 0x01, 0xdd, 0x0a, 0x01, 0x43, 0x0b, 0x01, 0xa9, 0x0b, 0x01, 0x0f, 0x0c, 0x01, 0x75, 0x0c, 0x01, 0xdb, 0x0c, 0x01, 0x41, 0x0d, 0x01, 0xa7, 0x0d, 0x01, 0x0d, 0x0e, 0x01, 0x73, 0x0e, 0x01, 0xd9, 0x0e, 0x01, 0x3f, 0x0f, 0x01, 0xa5, 0x0f, 0x01, 0x0b, 0x10, 0x01, 0x71, 0x10, 0x01, 0xd7, 0x10, 0x01, 0x3d, 0x11, 0x01, 0xa3, 0x11, 0x01, 0x09, 0x12, 0x01, 0x6f, 0x12, 0x01, 0xd5, 0x12, 0x01, 0x3b, 0x13, 0x01, 0xa1, 0x13, 0x01, 0x07, 0x14, 0x01, 0x6d, 0x14, 0x01, 0xd3, 0x14, 0x01, 0x39, 0x15, 0x01, 0x9f, 0x15, 0x01, 0x05, 0x16, 0x01, 0x6b, 0x16, 0x01, 0xd1, 0x16, 0x01, 0x37, 0x17, 0x01, 0x9d, 0x17, 0x01, 0x03, 0x18, 0x01, 0x69, 0x18, 0x01, 0xcf, 0x18, 0x01, 0x35, 0x19, 0x01, 0x9b, 0x19, 0x01, 0x01, 0x1a, 0x01, 0x67, 0x1a, 0x01, 0xcd, 0x1a, 0x01, 0x33, 0x1b, 0x01, 0x99, 0x1b, 0x01, 0xff, 0x1b, 0x01, 0x65, 0x1c, 0x01, 0xcb, 0x1c, 0x01, 0x31, 0x1d, 0x01, 0x97, 0x1d, 0x01, 0xfd, 0x1d, 0x01, 0x63, 0x1e, 0x01, 0xc9, 0x1e, 0x01, 0x2f, 0x1f, 0x01, 0x95, 0x1f, 0x01, 0xfb, 0x1f, 0x01, 0x61, 0x20, 0x01, 0xc7, 0x20, 0x01, 0x2d, 0x21, 0x01, 0x93, 0x21, 0x01, 0xf9, 0x21, 0x01, 0x5f, 0x22, 0x01, 0xc5, 0x22, 0x01, 0x2b, 0x23, 0x01, 0x91, 0x23, 0x01, 0xf7, 0x23, 0x01, 0x5d, 0x24, 0x01, 0xc3, 0x24, 0x01, 0x29, 0x25, 0x01, 0x8f, 0x25, 0x01, 0xf5, 0x25, 0x01, 0x5b, 0x26, 0x01, 0xc1, 0x26, 0x01, 0x27, 0x27, 0x01, 0x8d, 0x27, 0x01, 0xf3, 0x27, 0x01, 0x59, 0x28, 0x01, 0xbf, 0x28, 0x01, 0x25, 0x29, 0x01, 0x8b, 0x29, 0x01, 0xf1, 0x29, 0x01, 0x57, 0x2a, 0x01, 0xbd, 0x2a, 0x01, 0x23, 0x2b, 0x01, 0x89, 0x2b, 0x01, 0xef, 0x2b, 0x01, 0x55, 0x2c, 0x01, 0xbb, 0x2c, 0x01, 0x21, 0x2d, 0x01, 0x87, 0x2d, 0x01, 0xed, 0x2d, 0x01, 0x53, 0x2e, 0x01, 0xb9, 0x2e, 0x01, 0x1f, 0x2f, 0x01, 0x85, 0x2f, 0x01, 0xeb, 0x2f, 0x01, 0x51, 0x30, 0x01, 0xb7, 0x30, 0x01, 0x1d, 0x31, 0x01, 0x83, 0x31, 0x01, 0xe9, 0x31, 0x01, 0x4f, 0x32, 0x01, 0xb5, 0x32, 0x01, 0x1b, 0x33, 0x01, 0x81, 0x33, 0x01, 0xe7, 0x33, 0x01, 0x4d, 0x34, 0x01, 0xb3, 0x34, 0x01, 0x19, 0x35, 0x01, 0x7f, 0x35, 0x01, 0xe5, 0x35, 0x01, 0x4b, 0x36, 0x01, 0xb1, 0x36, 0x01, 0x17, 0x37, 0x01, 0x7d, 0x37, 0x01, 0xe3, 0x37, 0x01, 0x49, 0x38, 0x01, 0xaf, 0x38, 0x01, 0x15, 0x39, 0x01, 0x7b, 0x39, 0x01, 0xe1, 0x39, 0x01, 0x47, 0x3a, 0x01, 0xad, 0x3a, 0x01, 0x13, 0x3b, 0x01, 0x79, 0x3b, 0x01, 0xdf, 0x3b, 0x01, 0x45, 0x3c, 0x01, 0xab, 0x3c, 0x01, 0x11, 0x3d, 0x01, 0x77, 0x3d, 0x01, 0xdd, 0x3d, 0x01, 0x43, 0x3e, 0x01, 0xa9, 0x3e, 0x01, 0x0f, 0x3f, 0x01, 0x75, 0x3f, 0x01, 0xdb, 0x3f, 0x01, 0x41, 0x40, 0x01, 0xa7, 0x40, 0x01, 0x0d, 0x41, 0x01, 0x73, 0x41, 0x01, 0xd9, 0x41, 0x01, 0x3f, 0x42, 0x01, 0xa5, 0x42, 0x01, 0x0b, 0x43, 0x01, 0x71, 0x43, 0x01, 0xd7, 0x43, 0x01, 0x3d, 0x44, 0x01, 0xa3, 0x44, 0x01, 0x09, 0x45, 0x01, 0x6f, 0x45, 0x01, 0xd5, 0x45, 0x01, 0x3b, 0x46, 0x01, 0xa1, 0x46, 0x01, 0x07, 0x47, 0x01, 0x6d, 0x47, 0x01, 0xd3, 0x47, 0x01, 0x39, 0x48, 0x01, 0x9f, 0x48, 0x01, 0x05, 0x49, 0x01, 0x6b, 0x49, 0x01, 0xd1, 0x49, 0x01, 0x37, 0x4a, 0x01, 0x9d, 0x4a, 0x01, 0x03, 0x4b, 0x01, 0x69, 0x4b, 0x01, 0xcf, 0x4b, 0x01, 0x35, 0x4c, 0x01, 0x9b, 0x4c, 0x01, 0x01, 0x4d, 0x01, 0x67, 0x4d, 0x01, 0xcd, 0x4d, 0x01, 0x33, 0x4e, 0x01, 0x99, 0x4e, 0x01, 0xff, 0x4e, 0x01, 0x65, 0x4f, 0x01, 0xcb, 0x4f, 0x01, 0x31, 0x50, 0x01, 0x97, 0x50, 0x01, 0xfd, 0x50, 0x01, 0x63, 0x51, 0x01, 0xc9, 0x51, 0x01, 0x2f, 0x52, 0x01, 0x95, 0x52, 0x01, 0xfb, 0x52, 0x01, 0x61, 0x53, 0x01, 0xc7, 0x53, 0x01, 0x2d, 0x54, 0x01, 0x93, 0x54, 0x01, 0xf9, 0x54, 0x01, 0x5f, 0x55, 0x01, 0xc5, 0x55, 0x01, 0x2b, 0x56, 0x01, 0x91, 0x56, 0x01, 0xf7, 0x56, 0x01, 0x5d, 0x57, 0x01, 0xc3, 0x57, 0x01, 0x29, 0x58, 0x01, 0x8f, 0x58, 0x01, 0xf5, 0x58, 0x01, 0x5b, 0x59, 0x01, 0xc1, 0x59, 0x01, 0x27, 0x5a, 0x01, 0x8d, 0x5a, 0x01, 0xf3, 0x5a, 0x01, 0x59, 0x5b, 0x01, 0xbf, 0x5b, 0x01, 0x25, 0x5c, 0x01, 0x8b, 0x5c, 0x01, 0xf1, 0x5c, 0x01, 0x57, 0x5d, 0x01, 0xbd, 0x5d, 0x01, 0x23, 0x5e, 0x01, 0x89, 0x5e, 0x01, 0xef, 0x5e, 0x01, 0x55, 0x5f, 0x01, 0xbb, 0x5f, 0x01, 0x21, 0x60, 0x01, 0x87, 0x60, 0x01, 0xed, 0x60, 0x01, 0x53, 0x61, 0x01, 0xb9, 0x61, 0x01, 0x1f, 0x62, 0x01, 0x85, 0x62, 0x01, 0xeb, 0x62, 0x01, 0x51, 0x63, 0x01, 0xb7, 0x63, 0x01, 0x1d, 0x64, 0x01, 0x83, 0x64, 0x01, 0xe9, 0x64, 0x01, 0x4f, 0x65, 0x01, 0xb5, 0x65, 0x01, 0x1b, 0x66, 0x01, 0x81, 0x66, 0x01, 0xe7, 0x66, 0x01, 0x4d, 0x67, 0x01, 0xb3, 0x67, 0x01, 0x19, 0x68, 0x01, 0x7f, 0x68, 0x01, 0xe5, 0x68, 0x01, 0x4b, 0x69, 0x01, 0xb1, 0x69, 0x01, 0x17, 0x6a, 0x01, 0x7d, 0x6a, 0x01, 0xe3, 0x6a, 0x01, 0x49, 0x6b, 0x01, 0xaf, 0x6b, 0x01, 0x15, 0x6c, 0x01, 0x7b, 0x6c, 0x01, 0xe1, 0x6c, 0x01, 0x47, 0x6d, 0x01, 0xad, 0x6d, 0x01, 0x13, 0x6e, 0x01, 0x79, 0x6e, 0x01, 0xdf, 0x6e, 0x01, 0x45, 0x6f, 0x01, 0xab, 0x6f, 0x01, 0x11, 0x70, 0x01, 0x77, 0x70, 0x01, 0xdd, 0x70, 0x01, 0x43, 0x71, 0x01, 0xa9, 0x71, 0x01, 0x0f, 0x72, 0x01, 0x75, 0x72, 0x01, 0xdb, 0x72, 0x01, 0x41, 0x73, 0x01, 0xa7, 0x73, 0x01, 0x0d, 0x74, 0x01, 0x73, 0x74, 0x01, 0xd9, 0x74, 0x01, 0x3f, 0x75, 0x01, 0xa5, 0x75, 0x01, 0x0b, 0x76, 0x01, 0x71, 0x76, 0x01, 0xd7, 0x76, 0x01, 0x3d, 0x77, 0x01, 0xa3, 0x77, 0x01, 0x09, 0x78, 0x01, 0x6f, 0x78, 0x01, 0xd5, 0x78, 0x01, 0x3b, 0x79, 0x01, 0xa1, 0x79, 0x01, 0x07, 0x7a, 0x01, 0x6d, 0x7a, 0x01, 0xd3, 0x7a, 0x01, 0x39, 0x7b, 0x01, 0x9f, 0x7b, 0x01, 0x05, 0x7c, 0x01, 0x6b, 0x7c, 0x01, 0xd1, 0x7c, 0x01, 0x37, 0x7d, 0x01, 0x9d, 0x7d, 0x01, 0x03, 0x7e, 0x01, 0x69, 0x7e, 0x01, 0xcf, 0x7e, 0x01, 0x35, 0x7f, 0x01, 0x9b, 0x7f, 0x01, 0x01, 0x80, 0x01, 0x67, 0x80, 0x01, 0xcd, 0x80, 0x01, 0x33, 0x81, 0x01, 0x99, 0x81, 0x01, 0xff, 0x81, 0x01, 0x65, 0x82, 0x01, 0xcb, 0x82, 0x01, 0x31, 0x83, 0x01, 0x97, 0x83, 0x01, 0xfd, 0x83, 0x01, 0x63, 0x84, 0x01, 0xc9, 0x84, 0x01, 0x2f, 0x85, 0x01, 0x95, 0x85, 0x01, 0xfb, 0x85, 0x01, 0x61, 0x86, 0x01, 0xc7, 0x86, 0x01, 0x2d, 0x87, 0x01, 0x93, 0x87, 0x01, 0xf9, 0x87, 0x01, 0x5f, 0x88, 0x01, 0xc5, 0x88, 0x01, 0x2b, 0x89, 0x01, 0x91, 0x89, 0x01, 0xf7, 0x89, 0x01, 0x5d, 0x8a, 0x01, 0xc3, 0x8a, 0x01, 0x29, 0x8b, 0x01, 0x8f, 0x8b, 0x01, 0xf5, 0x8b, 0x01, 0x5b, 0x8c, 0x01, 0xc1, 0x8c, 0x01, 0x27, 0x8d, 0x01, 0x8d, 0x8d, 0x01, 0xf3, 0x8d, 0x01, 0x59, 0x8e, 0x01, 0xbf, 0x8e, 0x01, 0x25, 0x8f, 0x01, 0x8b, 0x8f, 0x01, 0xf1, 0x8f, 0x01, 0x57, 0x90, 0x01, 0xbd, 0x90, 0x01, 0x23, 0x91, 0x01, 0x89, 0x91, 0x01, 0xef, 0x91, 0x01, 0x55, 0x92, 0x01, 0xbb, 0x92, 0x01, 0x21, 0x93, 0x01, 0x87, 0x93, 0x01, 0xed, 0x93, 0x01, 0x53, 0x94, 0x01, 0xb9, 0x94, 0x01, 0x1f, 0x95, 0x01, 0x85, 0x95, 0x01, 0xeb, 0x95, 0x01, 0x51, 0x96, 0x01, 0xb7, 0x96, 0x01, 0x1d, 0x97, 0x01, 0x83, 0x97, 0x01, 0xe9, 0x97, 0x01, 0x4f, 0x98, 0x01, 0xb5, 0x98, 0x01, 0x1b, 0x99, 0x01, 0x81, 0x99, 0x01, 0xe7, 0x99, 0x01, 0x4d, 0x9a, 0x01, 0xb3, 0x9a, 0x01, 0x19, 0x9b, 0x01, 0x7f, 0x9b, 0x01, 0xe5, 0x9b, 0x01, 0x4b, 0x9c, 0x01, 0xb1, 0x9c, 0x01, 0x17, 0x9d, 0x01, 0x7d, 0x9d, 0x01, 0xe3, 0x9d, 0x01, 0x49, 0x9e, 0x01, 0xaf, 0x9e, 0x01, 0x15, 0x9f, 0x01, 0x7b, 0x9f, 0x01, 0xe1, 0x9f, 0x01, 0x47, 0xa0, 0x01, 0xad, 0xa0, 0x01, 0x13, 0xa1, 0x01, 0x79, 0xa1, 0x01, 0xdf, 0xa1, 0x01, 0x45, 0xa2, 0x01, 0xab, 0xa2, 0x01, 0x11, 0xa3, 0x01, 0x77, 0xa3, 0x01, 0xdd, 0xa3, 0x01, 0x43, 0xa4, 0x01, 0xa9, 0xa4, 0x01, 0x0f, 0xa5, 0x01, 0x75, 0xa5, 0x01, 0xdb, 0xa5, 0x01, 0x41, 0xa6, 0x01, 0xa7, 0xa6, 0x01, 0x0d, 0xa7, 0x01, 0x73, 0xa7, 0x01, 0xd9, 0xa7, 0x01, 0x3f, 0xa8, 0x01, 0xa5, 0xa8, 0x01, 0x0b, 0xa9, 0x01, 0x71, 0xa9, 0x01, 0xd7, 0xa9, 0x01, 0x3d, 0xaa, 0x01, 0xa3, 0xaa, 0x01, 0x09, 0xab, 0x01, 0x6f, 0xab, 0x01, 0xd5, 0xab, 0x01, 0x3b, 0xac, 0x01, 0xa1, 0xac, 0x01, 0x07, 0xad, 0x01, 0x6d, 0xad, 0x01, 0xd3, 0xad, 0x01, 0x39, 0xae, 0x01, 0x9f, 0xae, 0x01, 0x05, 0xaf, 0x01, 0x6b, 0xaf, 0x01, 0xd1, 0xaf, 0x01, 0x37, 0xb0, 0x01, 0x9d, 0xb0, 0x01, 0x03, 0xb1, 0x01, 0x69, 0xb1, 0x01, 0xcf, 0xb1, 0x01, 0x35, 0xb2, 0x01, 0x9b, 0xb2, 0x01, 0x01, 0xb3, 0x01, 0x67, 0xb3, 0x01, 0xcd, 0xb3, 0x01, 0x33, 0xb4, 0x01, 0x99, 0xb4, 0x01, 0xff, 0xb4, 0x01, 0x65, 0xb5, 0x01, 0xcb, 0xb5, 0x01, 0x31, 0xb6, 0x01, 0x97, 0xb6, 0x01, 0xfd, 0xb6, 0x01, 0x63, 0xb7, 0x01, 0xc9, 0xb7, 0x01, 0x2f, 0xb8, 0x01, 0x95, 0xb8, 0x01, 0xfb, 0xb8, 0x01, 0x61, 0xb9, 0x01, 0xc7, 0xb9, 0x01, 0x2d, 0xba, 0x01, 0x93, 0xba, 0x01, 0xf9, 0xba, 0x01, 0x5f, 0xbb, 0x01, 0xc5, 0xbb, 0x01, 0x2b, 0xbc, 0x01, 0x91, 0xbc, 0x01, 0xf7, 0xbc, 0x01, 0x5d, 0xbd, 0x01, 0xc3, 0xbd, 0x01, 0x29, 0xbe, 0x01, 0x8f, 0xbe, 0x01, 0xf5, 0xbe, 0x01, 0x5b, 0xbf, 0x01, 0xc1, 0xbf, 0x01, 0x27, 0xc0, 0x01, 0x8d, 0xc0, 0x01, 0xf3, 0xc0, 0x01, 0x59, 0xc1, 0x01, 0xbf, 0xc1, 0x01, 0x25, 0xc2, 0x01, 0x8b, 0xc2, 0x01, 0xf1, 0xc2, 0x01, 0x57, 0xc3, 0x01, 0xbd, 0xc3, 0x01, 0x23, 0xc4, 0x01, 0x89, 0xc4, 0x01, 0xef, 0xc4, 0x01, 0x55, 0xc5, 0x01, 0xbb, 0xc5, 0x01, 0x21, 0xc6, 0x01, 0x87, 0xc6, 0x01, 0xed, 0xc6, 0x01, 0x53, 0xc7, 0x01, 0xb9, 0xc7, 0x01, 0x1f, 0xc8, 0x01, 0x85, 0xc8, 0x01, 0xeb, 0xc8, 0x01, 0x51, 0xc9, 0x01, 0xb7, 0xc9, 0x01, 0x1d, 0xca, 0x01, 0x83, 0xca, 0x01, 0xe9, 0xca, 0x01, 0x4f, 0xcb, 0x01, 0xb5, 0xcb, 0x01, 0x1b, 0xcc, 0x01, 0x1f, 0x04, 0x07, 0x04, 0x04, 0x02, 0x03, 0x10, 0x00, 0x00, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x0a, 0x06, 0x00, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x10, 0x00, 0x00, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x1f, 0x00, 0x08, 0x00, 0x06, 0x00, 0x03, 0x0a, 0x06, 0x00, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x1e, 0x0b, 0x06, 0x04, 0x04, 0x03, 0x04, 0x0c, 0x04, 0x00, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x13, 0xf8, 0x01, 0x87, 0xf9, 0x01, 0x87, 0xf9, 0x01, 0x35, 0xee, 0x01, 0xa9, 0xf2, 0x01, 0xa9, 0xf2, 0x01, 0x35, 0xee, 0x01, 0xa9, 0xf2, 0x01, 0xa9, 0xf2, 0x01, 0x1e, 0x04, 0x0b, 0x04, 0x08, 0x02, 0x06, 0x04, 0x06, 0x06, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x18, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x0a, 0x06, 0x00, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x08, 0x04, 0x04, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0xb7, 0x11, 0x02, 0x21, 0x17, 0x02, 0x09, 0x1d, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x03, 0x05, 0x08, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0x7c, 0x00, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x73, 0x30, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xf0, 0x3c, 0x03, 0x55, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0xff, 0x00, 0x03, 0x55, 0x55, 0xff, 0x00, 0x3d, 0x55, 0x55, 0xff, 0x00, 0xcd, 0x55, 0x55, 0xcf, 0xff, 0x0d, 0x55, 0x55, 0x73, 0x30, 0x3d, 0x55, 0x55, 0x73, 0xf0, 0xf5, 0x55, 0x55, 0x73, 0xf0, 0x35, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x7f, 0x55, 0x57, 0xff, 0x55, 0xff, 0xd5, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x0f, 0x00, 0xf0, 0xd5, 0x57, 0x30, 0xc3, 0x0c, 0xd5, 0x57, 0x00, 0x3c, 0x00, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x57, 0x3f, 0xff, 0xfc, 0xd5, 0x57, 0xf0, 0xc3, 0x0f, 0xd5, 0x55, 0x73, 0xff, 0xcd, 0x55, 0x55, 0xc3, 0xff, 0xc3, 0x55, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x03, 0x00, 0xc0, 0xd5, 0x57, 0x0c, 0x00, 0x30, 0xd5, 0x57, 0x00, 0x3c, 0x00, 0xd5, 0x55, 0xc0, 0xff, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x3f, 0x0f, 0xc3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x00, 0xf0, 0x0d, 0x55, 0x55, 0xff, 0x0f, 0xf5, 0x55, 0x57, 0x33, 0xfc, 0xcd, 0x55, 0x57, 0xf3, 0xfc, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x30, 0x00, 0x0c, 0xd5, 0x57, 0x0c, 0x00, 0x30, 0xd5, 0x57, 0x00, 0xff, 0x00, 0xd5, 0x5f, 0x03, 0xff, 0xc0, 0xf5, 0x5c, 0xc3, 0xff, 0xc3, 0x35, 0x5f, 0x3f, 0xff, 0xfc, 0xf5, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0xc3, 0xff, 0xc3, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x7f, 0x55, 0x57, 0xff, 0x55, 0xff, 0xd5, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x03, 0x00, 0xc0, 0xd5, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x30, 0x3c, 0x0c, 0xd5, 0x55, 0xcc, 0x3c, 0x33, 0xd5, 0x55, 0xcc, 0x3c, 0x33, 0x55, 0x55, 0xc3, 0xc3, 0xc3, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xd7, 0xf5, 0x55, 0x55, 0x5f, 0x55, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x5c, 0x3f, 0xff, 0xc3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x55, 0xff, 0xff, 0xf5, 0x55, 0x55, 0xc0, 0x00, 0x35, 0x55, 0x57, 0x30, 0x00, 0xcd, 0x55, 0x57, 0xf0, 0x00, 0xfd, 0x55, 0x55, 0x70, 0x00, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0x55, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0x70, 0x00, 0x3d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x70, 0x0c, 0xd5, 0x55, 0x57, 0xc0, 0xfc, 0xd5, 0x55, 0x55, 0xf0, 0x3f, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0x57, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0x70, 0x00, 0x3d, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x30, 0xcd, 0x55, 0x55, 0xfc, 0x3f, 0xf5, 0x55, 0x55, 0x70, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x70, 0x3f, 0xf5, 0x55, 0x55, 0xc0, 0x0f, 0xf5, 0x55, 0x7f, 0xc0, 0x0f, 0xf5, 0x5f, 0xc0, 0xc0, 0x0f, 0x55, 0x5f, 0xc0, 0xc0, 0xcf, 0xd5, 0x55, 0xc0, 0xc0, 0xcf, 0xd5, 0x57, 0xc0, 0x3c, 0xcf, 0xf5, 0x5f, 0xfc, 0x03, 0x0f, 0xf5, 0x5f, 0xff, 0xff, 0xf7, 0xd5, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x3c, 0x03, 0xc3, 0x55, 0x5c, 0xc3, 0x0c, 0x33, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0xc3, 0x0c, 0x33, 0x55, 0x57, 0x30, 0xf0, 0xcc, 0xd5, 0x55, 0xff, 0xff, 0xf0, 0xd5, 0x55, 0x73, 0x0c, 0x03, 0x55, 0x55, 0xcc, 0xfc, 0x0d, 0x55, 0x55, 0xfc, 0xff, 0x0d, 0x55, 0x55, 0x5c, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x55, 0xf5, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x00, 0xc3, 0x00, 0xd5, 0x57, 0x3f, 0xc3, 0xfc, 0xd5, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x5c, 0xcc, 0x35, 0x55, 0x55, 0x73, 0xff, 0xcd, 0x55, 0x55, 0x70, 0xfc, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xc0, 0x30, 0x03, 0x55, 0x55, 0xc0, 0xc0, 0x03, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xfc, 0x00, 0x03, 0x55, 0x55, 0xff, 0x03, 0xc3, 0x55, 0x55, 0x7f, 0x03, 0x3d, 0x55, 0x55, 0x5f, 0xff, 0x35, 0x55, 0x55, 0x5c, 0xcc, 0x0d, 0x55, 0x55, 0x57, 0x3c, 0x03, 0x55, 0x55, 0x57, 0x3c, 0x3f, 0x55, 0x55, 0x57, 0xff, 0xf5, 0x55, 0x55, 0x55, 0x7d, 0xfd, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0x7f, 0x55, 0x55, 0x55, 0xff, 0xff, 0xd5, 0x55, 0x55, 0xff, 0xff, 0xd5, 0x55, 0x55, 0xff, 0x00, 0x35, 0x55, 0x57, 0xf0, 0x00, 0x3d, 0x55, 0x57, 0xc0, 0x03, 0x03, 0x55, 0x57, 0x00, 0x3c, 0x03, 0x55, 0x57, 0x00, 0x00, 0x0f, 0x55, 0x57, 0x00, 0x00, 0x35, 0x55, 0x57, 0xc0, 0x03, 0xd5, 0x55, 0x55, 0x7f, 0xff, 0x55, 0x55, 0x55, 0xc0, 0xcf, 0x55, 0x55, 0x57, 0x30, 0xfd, 0x55, 0x55, 0x57, 0xf0, 0xfd, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x7d, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xf5, 0x55, 0x55, 0x5f, 0xfd, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0x00, 0x0d, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x0f, 0xc3, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0x70, 0x00, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x5c, 0x3c, 0xd5, 0x55, 0x55, 0x5f, 0x0f, 0xd5, 0x55, 0x55, 0x5c, 0xff, 0xd5, 0x55, 0x55, 0x70, 0x0f, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3c, 0x0f, 0x55, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0xc0, 0x00, 0xff, 0x55, 0x55, 0xc0, 0xf0, 0xff, 0x55, 0x55, 0x70, 0xcc, 0xfd, 0x55, 0x55, 0x5f, 0xcf, 0xd5, 0x55, 0x55, 0x5c, 0xcc, 0xd5, 0x55, 0x55, 0x5c, 0x3f, 0xd5, 0x55, 0x55, 0x5c, 0x0f, 0xd5, 0x55, 0x55, 0x70, 0x0f, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x55, 0xfd, 0x55, 0x55, 0x7f, 0xdf, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0xc3, 0x55, 0x55, 0xcc, 0x00, 0x03, 0x55, 0x55, 0x73, 0x00, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x73, 0x30, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0x7f, 0x55, 0x55, 0xff, 0xd5, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0xd5, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0x70, 0x00, 0x03, 0x55, 0x55, 0xc3, 0x00, 0x30, 0xd5, 0x55, 0xcc, 0xc0, 0xcc, 0xd5, 0x55, 0xc3, 0x00, 0x30, 0xd5, 0x57, 0xc0, 0x3f, 0x00, 0xd5, 0x57, 0x30, 0xff, 0xc3, 0x55, 0x55, 0xcf, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xc3, 0xfc, 0x03, 0x55, 0x55, 0xc3, 0xfc, 0x3c, 0xd5, 0x55, 0x7f, 0xfc, 0x37, 0xd5, 0x55, 0x5f, 0x7f, 0xd5, 0x55, 0x55, 0x55, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x3c, 0x03, 0xc3, 0x55, 0x5c, 0xf3, 0x0f, 0x33, 0x55, 0x5c, 0xff, 0x0f, 0xf3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x0f, 0xf0, 0x0d, 0x55, 0x55, 0xfc, 0x3f, 0xf5, 0x55, 0x55, 0xc3, 0xcc, 0x3d, 0x55, 0x55, 0x70, 0xfc, 0xf3, 0x55, 0x55, 0x70, 0xfc, 0xdf, 0x55, 0x55, 0x7f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xcd, 0x55, 0x5f, 0xff, 0xff, 0xfd, 0x55, 0x7f, 0xff, 0xff, 0xd5, 0x55, 0x70, 0x00, 0x03, 0xd5, 0x55, 0xff, 0xff, 0xfc, 0xd5, 0x55, 0xc0, 0x00, 0x0f, 0xd5, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0x7c, 0x00, 0x0c, 0xd5, 0x55, 0x5f, 0xff, 0xf0, 0x35, 0x55, 0x7f, 0x3f, 0xfc, 0x0d, 0x55, 0x7f, 0x3f, 0xfc, 0x0d, 0x55, 0x70, 0x00, 0x3c, 0x0d, 0x55, 0x7f, 0xff, 0xf0, 0x0d, 0x55, 0x5f, 0xff, 0xdf, 0xf5, 0x55, 0x7f, 0xdf, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0x55, 0x55, 0x55, 0x57, 0x35, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0xff, 0xff, 0x55, 0x55, 0x5f, 0xff, 0xff, 0x55, 0x55, 0x70, 0x00, 0x0f, 0x55, 0x55, 0x7f, 0xff, 0xf3, 0xfd, 0x55, 0xc0, 0x00, 0x0c, 0xc3, 0x55, 0xc0, 0x00, 0x03, 0xc3, 0x55, 0xc0, 0x00, 0x03, 0x03, 0x55, 0xf0, 0x03, 0x03, 0xc3, 0x55, 0xc3, 0xc0, 0x0f, 0xc3, 0x55, 0xc3, 0xc0, 0x3f, 0x0d, 0x55, 0x7f, 0xff, 0xfc, 0x35, 0x5d, 0xff, 0x3f, 0xf3, 0xd5, 0x5f, 0x00, 0x00, 0xfd, 0x55, 0x5f, 0xff, 0xff, 0x3d, 0x55, 0x55, 0xff, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xff, 0x55, 0x55, 0x7f, 0xff, 0xff, 0xd5, 0x55, 0xf0, 0x00, 0x03, 0xf5, 0x55, 0xcf, 0xff, 0xfc, 0xf5, 0x55, 0xf0, 0x00, 0x03, 0xff, 0x57, 0x0f, 0xc0, 0xfc, 0xf3, 0x57, 0x33, 0xc3, 0x3c, 0xdf, 0x57, 0x33, 0xc3, 0x3c, 0xd5, 0x57, 0x0f, 0xc0, 0xfc, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x35, 0x55, 0xff, 0xff, 0xfc, 0x0d, 0x57, 0xff, 0xcf, 0xf3, 0x0d, 0x5c, 0xff, 0xcf, 0xff, 0x0d, 0x57, 0x70, 0x00, 0x0c, 0x0d, 0x55, 0x7f, 0xff, 0xf7, 0xf5, 0x55, 0x57, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xf7, 0xfd, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xff, 0xf5, 0x55, 0x70, 0x00, 0xff, 0xff, 0x55, 0x7f, 0xfc, 0x03, 0xf3, 0x55, 0xf0, 0xff, 0xf0, 0xdf, 0x55, 0xf0, 0xf3, 0x0f, 0xd5, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xff, 0xf0, 0x33, 0x55, 0x57, 0x3f, 0xc0, 0xff, 0xd5, 0x57, 0xcf, 0xff, 0xfc, 0x35, 0x55, 0xff, 0x3f, 0xfc, 0x0d, 0x55, 0x7f, 0x3f, 0xf0, 0x0d, 0x55, 0x7f, 0x3f, 0xf0, 0x0d, 0x55, 0x70, 0x00, 0xf0, 0x0d, 0x55, 0x5f, 0xff, 0xdf, 0xf5, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x55, 0xf7, 0xd5, 0x55, 0x30, 0x1f, 0x01, 0x55, 0x40, 0x00, 0x00, 0x00, 0x15, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x11, 0x41, 0x50, 0x00, 0x00, 0x15, 0x55, 0x55, 0x54, 0x04, 0x10, 0x01, 0x55, 0x41, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa1, 0x14, 0x15, 0x54, 0x01, 0x11, 0x45, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa5, 0x54, 0x15, 0x54, 0x01, 0x55, 0x45, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa1, 0x14, 0x44, 0x11, 0x55, 0x55, 0x55, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x15, 0x40, 0x01, 0x55, 0x11, 0x56, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x95, 0x40, 0x01, 0x55, 0x55, 0x56, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x95, 0x55, 0x55, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x55, 0x50, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x01, 0x50, 0x55, 0x50, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x15, 0x55, 0x55, 0x54, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x02, 0x55, 0x55, 0x55, 0x00, 0x04, 0x00, 0x80, 0x28, 0x00, 0x00, 0xa0, 0x02, 0x01, 0x15, 0x55, 0x10, 0x04, 0x55, 0x80, 0x28, 0x00, 0x00, 0xa0, 0x02, 0x01, 0x15, 0x55, 0x01, 0x55, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x02, 0x55, 0x55, 0x55, 0x01, 0x01, 0x00, 0x80, 0xaa, 0xaa, 0xaa, 0xa8, 0x02, 0x00, 0x04, 0x01, 0x01, 0x55, 0x00, 0x82, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x04, 0x01, 0x00, 0x41, 0x00, 0x82, 0xaa, 0xaa, 0xaa, 0xaa, 0x02, 0x00, 0x04, 0x01, 0x55, 0x5a, 0xa5, 0x80, 0x95, 0x95, 0x80, 0x00, 0x02, 0x55, 0x54, 0x01, 0x00, 0x25, 0x58, 0x80, 0x95, 0x95, 0x85, 0x54, 0x0a, 0xaa, 0xa8, 0x01, 0x00, 0x26, 0x98, 0x80, 0x95, 0x95, 0x85, 0x54, 0x08, 0x00, 0x09, 0x55, 0x00, 0x25, 0x58, 0x80, 0x95, 0x95, 0xaa, 0xaa, 0x08, 0x88, 0x88, 0x00, 0x00, 0x20, 0x08, 0x95, 0x95, 0x95, 0x80, 0x02, 0x58, 0x88, 0x88, 0x00, 0xaa, 0xa0, 0x0a, 0x95, 0x95, 0x95, 0x80, 0x02, 0x58, 0x00, 0x0a, 0xaa, 0x04, 0x20, 0x08, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa9, 0x55, 0x58, 0x00, 0x00, 0x0a, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xaa, 0xa9, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0x42, 0x82, 0x20, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa6, 0x86, 0x26, 0x62, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x45, 0x86, 0x24, 0xa4, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xa4, 0xa1, 0x61, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x61, 0x40, 0xa2, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0xaa, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa9, 0x55, 0x69, 0x55, 0x6a, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x9a, 0xa9, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x59, 0x59, 0x6a, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x98, 0x49, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x95, 0x55, 0xaa, 0x95, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa5, 0x56, 0xaa, 0x40, 0x68, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa8, 0x0a, 0xa5, 0x55, 0x58, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa9, 0x5a, 0xa5, 0x55, 0x58, 0x00, 0x95, 0x5a, 0x69, 0xa5, 0x56, 0x02, 0xa5, 0x96, 0xa9, 0x69, 0x68, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x96, 0x5a, 0x69, 0xa5, 0x96, 0x54, 0x54, 0x54, 0x54, 0x54, 0x55, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x54, 0x54, 0x54, 0x54, 0x54, 0x55, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x30, 0x1f, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x15, 0x00, 0x00, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x55, 0x00, 0x01, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x40, 0x51, 0x55, 0x55, 0x15, 0x54, 0x00, 0x00, 0x15, 0x54, 0x55, 0x55, 0x45, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x40, 0x00, 0x44, 0x11, 0x10, 0x11, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x44, 0x04, 0x44, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x40, 0x00, 0x44, 0x15, 0x05, 0x41, 0x50, 0x05, 0x55, 0x55, 0x50, 0x05, 0x41, 0x50, 0x54, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x50, 0x40, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x50, 0x40, 0x01, 0x00, 0x01, 0x00, 0x17, 0xfc, 0x3f, 0xfc, 0x00, 0x43, 0xff, 0xc0, 0x01, 0x00, 0x01, 0x00, 0x1f, 0xf4, 0xff, 0xd4, 0x00, 0x4f, 0xfc, 0x40, 0x01, 0x55, 0x55, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x40, 0x01, 0x11, 0x11, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x40, 0x01, 0x00, 0x01, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xc0, 0x01, 0x05, 0x41, 0x00, 0xf0, 0xfc, 0x03, 0xff, 0xff, 0x00, 0x00, 0xc0, 0x01, 0x05, 0x41, 0x00, 0xf0, 0xf3, 0x0c, 0x71, 0xc7, 0x33, 0x30, 0xc0, 0xaa, 0xaa, 0xaa, 0xaa, 0xf0, 0xf3, 0x0d, 0x75, 0xd7, 0x33, 0x30, 0xea, 0x55, 0x55, 0x55, 0x55, 0xf0, 0xfc, 0x0d, 0x34, 0xd3, 0x33, 0x30, 0xd5, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x0d, 0x34, 0xc3, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x03, 0xff, 0xff, 0xaa, 0xaa, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 0xc0, 0x00, 0xfc, 0x0f, 0xc0, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x3a, 0xbf, 0xfa, 0xab, 0xff, 0xbf, 0xfb, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0xff, 0xff, 0xcf, 0xfc, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf0, 0x03, 0xff, 0x3f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xc0, 0x00, 0xfc, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x55, 0x51, 0x55, 0x55, 0x15, 0x54, 0x00, 0x00, 0x15, 0x10, 0x00, 0x00, 0x40, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x40, 0x11, 0x10, 0x11, 0x10, 0x04, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x40, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x15, 0x55, 0x55, 0x40, 0x15, 0x05, 0x41, 0x50, 0x05, 0x55, 0x55, 0x50, 0x00, 0x00, 0x00, 0x00, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf5, 0xff, 0xf0, 0x00, 0x0f, 0xff, 0x00, 0x50, 0x50, 0x50, 0x50, 0x3f, 0xc3, 0xff, 0x00, 0x14, 0x3f, 0xf4, 0x14, 0x55, 0x50, 0x55, 0x50, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x54, 0x55, 0x50, 0x55, 0x50, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x54, 0x55, 0x55, 0x55, 0x53, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x54, 0x40, 0x10, 0x40, 0x13, 0xc3, 0xf0, 0x0f, 0xff, 0xfc, 0x00, 0x03, 0x04, 0x50, 0x50, 0x50, 0x53, 0xc3, 0xcc, 0x31, 0xc7, 0x1c, 0xcc, 0xc3, 0x14, 0x40, 0x10, 0x40, 0x13, 0xc3, 0xcc, 0x35, 0xd7, 0x5c, 0xcc, 0xc3, 0x04, 0xaa, 0xaa, 0xaa, 0xab, 0xc3, 0xf0, 0x34, 0xd3, 0x4c, 0xcc, 0xc3, 0xaa, 0x55, 0x55, 0x55, 0x57, 0x00, 0x00, 0x34, 0xd3, 0x0c, 0x00, 0x03, 0x55, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x0f, 0xff, 0xfe, 0xaa, 0xab, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x3f, 0x00, 0x03, 0xf0, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xea, 0xff, 0xea, 0xaf, 0xfe, 0xff, 0xec, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf3, 0xff, 0xff, 0x3f, 0xf3, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x0f, 0xfc, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x03, 0xf0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xfd, 0x7d, 0x7f, 0x5d, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x5d, 0xd5, 0xd7, 0x75, 0xdd, 0xd5, 0x55, 0x55, 0x55, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x30, 0xcc, 0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0xc0, 0xff, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xc0, 0xc3, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0x3f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xfc, 0x3f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x03, 0xc0, 0x30, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0xf3, 0xff, 0xff, 0xcf, 0x00, 0x00, 0x0f, 0xf0, 0x70, 0x0f, 0x55, 0x55, 0xc3, 0x0c, 0x30, 0xc3, 0x55, 0x55, 0xf0, 0x0d, 0xc3, 0x30, 0xd5, 0xff, 0x7c, 0xcf, 0xf3, 0x3d, 0xff, 0x57, 0x0c, 0xc3, 0xc0, 0x3f, 0x5f, 0x03, 0x57, 0xcf, 0xf3, 0xd5, 0xc0, 0xf5, 0xfc, 0x03, 0xc0, 0x30, 0xdc, 0x0d, 0x5f, 0xff, 0xff, 0xf5, 0x70, 0x37, 0x0c, 0x03, 0x7f, 0xff, 0x5f, 0xf5, 0x5f, 0x55, 0x55, 0xf5, 0x5f, 0xf5, 0xff, 0xfd, 0x30, 0x1f, 0xa4, 0x00, 0xa4, 0x01, 0x90, 0x00, 0x64, 0x06, 0x40, 0x1a, 0x00, 0x16, 0xa9, 0x40, 0x09, 0x00, 0x40, 0x00, 0x10, 0x01, 0x00, 0x60, 0x01, 0x6a, 0x2a, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xaa, 0x00, 0xa5, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x01, 0x6a, 0x80, 0x00, 0x01, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x30, 0xc0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x00, 0x05, 0x94, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x15, 0x56, 0xa5, 0x55, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x15, 0x40, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x29, 0x50, 0x15, 0x68, 0x00, 0x40, 0x07, 0xf0, 0x0f, 0xc0, 0x10, 0x00, 0x0a, 0xa5, 0x6a, 0x80, 0x01, 0x00, 0x1f, 0xfc, 0x3f, 0xf0, 0x04, 0x00, 0x00, 0xaa, 0xa8, 0x00, 0x15, 0x00, 0x1f, 0xff, 0xff, 0xf0, 0x05, 0x40, 0x00, 0x0a, 0xa0, 0x00, 0x04, 0x00, 0x5c, 0x00, 0x00, 0x30, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xf0, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xc0, 0x33, 0x00, 0x00, 0xcc, 0x03, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x30, 0x03, 0xc0, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x0c, 0x30, 0x03, 0xc0, 0x0c, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x3c, 0x03, 0xc0, 0x3c, 0xff, 0xc0, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0xc3, 0xff, 0xff, 0xc3, 0x00, 0x00, 0x0f, 0xf0, 0x30, 0x0c, 0x00, 0x00, 0xcc, 0x30, 0x0c, 0x33, 0x00, 0x00, 0x30, 0x0c, 0xc3, 0x0f, 0x00, 0x00, 0x3f, 0x3f, 0xfc, 0xfc, 0x00, 0x00, 0xf0, 0xc3, 0xc0, 0x30, 0xc0, 0x00, 0x03, 0x3f, 0xfc, 0xc0, 0x00, 0x03, 0x0c, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0xfc, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x3f, 0xfc, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x30, 0x30, 0xc0, 0x00, 0x00, 0x3c, 0x3c, 0x00, 0x00, 0x03, 0x0c, 0x0c, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x0c, 0x30, 0x00, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xfd, 0x7d, 0x7f, 0x5d, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x5d, 0xd5, 0xd7, 0x75, 0xdd, 0xd5, 0x55, 0x55, 0x55, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x30, 0xcc, 0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0xc0, 0xff, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xc0, 0xc3, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x70, 0x0f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xf0, 0x0d, 0xc3, 0x30, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x0c, 0xc3, 0xc0, 0x3f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfc, 0x03, 0xc0, 0x30, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x0c, 0x03, 0x7f, 0xff, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xfd, 0x30, 0x1f, 0xa4, 0x00, 0xa4, 0x01, 0x90, 0x00, 0x64, 0x06, 0x40, 0x1a, 0x00, 0x16, 0xa9, 0x40, 0x09, 0x00, 0x40, 0x00, 0x10, 0x01, 0x00, 0x60, 0x01, 0x6a, 0x2a, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xaa, 0x00, 0xa5, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x01, 0x6a, 0x80, 0x00, 0x01, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x30, 0xc0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x00, 0x05, 0x94, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x15, 0x56, 0xa5, 0x55, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x15, 0x40, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x29, 0x50, 0x15, 0x68, 0x00, 0x40, 0x04, 0x00, 0x04, 0x00, 0x10, 0x00, 0x0a, 0xa5, 0x6a, 0x80, 0x01, 0x00, 0x14, 0x00, 0x05, 0x00, 0x04, 0x00, 0x00, 0xaa, 0xa8, 0x00, 0x15, 0x00, 0x15, 0x00, 0x15, 0x00, 0x05, 0x40, 0x00, 0x0a, 0xa0, 0x00, 0x04, 0x00, 0x54, 0x00, 0x05, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x30, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0c, 0xc3, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xc3, 0xc0, 0x30, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x30, 0x30, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x0c, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xfc, 0x00, 0xc3, 0x0f, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xc3, 0x00, 0xc3, 0x30, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xcc, 0xc3, 0x00, 0xff, 0x30, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xfc, 0x00, 0xc3, 0x30, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xc0, 0x00, 0xc3, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x3f, 0x0f, 0xcf, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0xcc, 0x0c, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0xcf, 0xcf, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0x0f, 0xcf, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x30, 0xcc, 0x33, 0x0c, 0xfc, 0xfc, 0x00, 0x00, 0xc0, 0x00, 0x00, 0xc3, 0x30, 0xcf, 0x33, 0xcc, 0xc0, 0xc3, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc3, 0x30, 0xcc, 0xf3, 0x3c, 0xfc, 0xc3, 0x00, 0x00, 0xfc, 0x00, 0x00, 0xfc, 0x30, 0xcc, 0x33, 0x0c, 0xc0, 0xfc, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc3, 0x0f, 0x0c, 0x33, 0x0c, 0xfc, 0xc3, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x1f, 0x05, 0x55, 0x55, 0x55, 0x55, 0x55, 0x54, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x05, 0x54, 0x55, 0x45, 0x51, 0x10, 0x00, 0x04, 0x04, 0x55, 0x44, 0x51, 0x11, 0x55, 0x44, 0x04, 0x44, 0x44, 0x51, 0x11, 0x00, 0x44, 0x04, 0x44, 0x44, 0x51, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x00, 0x00, 0x00, 0x05, 0x41, 0x10, 0x00, 0x00, 0x00, 0x00, 0x04, 0x41, 0x10, 0x00, 0x00, 0x10, 0x55, 0x05, 0x41, 0x10, 0x54, 0x00, 0x55, 0x45, 0x10, 0x11, 0x11, 0x01, 0x40, 0x55, 0x54, 0x10, 0x11, 0x11, 0x00, 0x10, 0x55, 0x54, 0x15, 0x51, 0x11, 0x41, 0x11, 0x51, 0x10, 0x04, 0x41, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x50, 0x50, 0x00, 0x00, 0x10, 0x01, 0x10, 0x55, 0x50, 0x55, 0x00, 0x55, 0x01, 0x10, 0x44, 0x51, 0x00, 0x51, 0x00, 0x41, 0x10, 0x40, 0x11, 0x04, 0x41, 0x11, 0x41, 0x10, 0x15, 0x41, 0x00, 0x41, 0x00, 0x41, 0x10, 0x10, 0x41, 0x00, 0x40, 0x41, 0x01, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x55, 0x55, 0x55, 0x55, 0x55, 0x41, 0x10, 0x40, 0x00, 0x00, 0x00, 0x00, 0x41, 0x10, 0x55, 0x55, 0x55, 0x55, 0x55, 0x41, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x15, 0x50, 0x00, 0x00, 0x00, 0x01, 0x55, 0x12, 0x0c, 0x57, 0xf5, 0x7d, 0x55, 0x50, 0x5f, 0xfd, 0xff, 0x55, 0x50, 0x5f, 0xff, 0xff, 0x55, 0x50, 0x5f, 0xff, 0xff, 0xd5, 0x50, 0x7c, 0x00, 0x00, 0xd5, 0x50, 0x70, 0x0f, 0xc3, 0xd5, 0x50, 0x70, 0x33, 0xc3, 0xd5, 0x50, 0x70, 0x33, 0xc3, 0xd5, 0x50, 0x70, 0x0f, 0xc3, 0xd5, 0x50, 0x5c, 0x00, 0x0f, 0x55, 0x50, 0x57, 0xff, 0xfd, 0x55, 0x50, 0x5c, 0x3c, 0x33, 0x55, 0x50, 0x12, 0x0c, 0x55, 0xfd, 0x5f, 0x55, 0x50, 0x57, 0xff, 0x7f, 0xd5, 0x50, 0x57, 0xff, 0xff, 0xd5, 0x50, 0x57, 0xff, 0xff, 0xf5, 0x50, 0x5f, 0x00, 0x00, 0x35, 0x50, 0x5c, 0x03, 0xc0, 0x35, 0x50, 0x5c, 0x0c, 0x30, 0xf5, 0x50, 0x5c, 0x00, 0x00, 0x35, 0x50, 0x5c, 0x0c, 0x0f, 0xf5, 0x50, 0x57, 0x33, 0x0f, 0xd5, 0x50, 0x55, 0xf3, 0xff, 0x35, 0x50, 0x55, 0xc3, 0xc3, 0xf5, 0x50, 0x12, 0x0c, 0x5f, 0xd5, 0x7f, 0xff, 0xf0, 0x7f, 0xf5, 0xff, 0x00, 0x30, 0x7f, 0xff, 0xff, 0x00, 0x30, 0x7f, 0xff, 0xff, 0x00, 0x30, 0x70, 0x00, 0x03, 0x00, 0x30, 0xc3, 0xf0, 0x3f, 0x00, 0x30, 0xcc, 0xf0, 0xcf, 0x00, 0x30, 0xcc, 0xf0, 0xcf, 0x00, 0x30, 0xc3, 0xf0, 0x3f, 0xff, 0xf0, 0x70, 0x0f, 0x00, 0xcd, 0x50, 0x5f, 0xff, 0xff, 0x35, 0x50, 0x70, 0x30, 0x3c, 0xd5, 0x50, 0x12, 0x0c, 0x55, 0xfd, 0x57, 0xd5, 0x50, 0x57, 0xff, 0xdf, 0xf5, 0x50, 0x57, 0xff, 0xff, 0xfd, 0x50, 0x55, 0xff, 0xff, 0xfd, 0x50, 0x57, 0xc0, 0x00, 0x0d, 0x50, 0x57, 0x00, 0x00, 0x0d, 0x50, 0x57, 0x00, 0x00, 0x0d, 0x50, 0x57, 0x0f, 0xf0, 0x0d, 0x50, 0x57, 0x00, 0x00, 0xcd, 0x50, 0x55, 0xc0, 0x03, 0x35, 0x50, 0x55, 0x7f, 0xff, 0xd5, 0x50, 0x55, 0xc3, 0xc3, 0xd5, 0x50, 0x12, 0x0c, 0x57, 0xf5, 0x5f, 0xd5, 0x50, 0x5f, 0xfd, 0x7f, 0xf5, 0x50, 0x5f, 0xff, 0xff, 0xf5, 0x50, 0x5f, 0xff, 0xff, 0xf5, 0x50, 0x5c, 0x00, 0x00, 0x35, 0x50, 0x70, 0x00, 0x00, 0x0d, 0x50, 0x70, 0x30, 0x0c, 0x0d, 0x50, 0x70, 0xc0, 0x03, 0x0d, 0x50, 0x70, 0x03, 0xc0, 0x0d, 0x50, 0x5c, 0x0f, 0xf0, 0x35, 0x50, 0x57, 0xff, 0xff, 0xd5, 0x50, 0x55, 0xcc, 0x33, 0x55, 0x50, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfa, 0xaa, 0xab, 0xc0, 0xff, 0xe5, 0x55, 0x5a, 0xc0, 0xff, 0xe5, 0x55, 0x5a, 0xc0, 0xff, 0x95, 0x55, 0x66, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0xaa, 0xaa, 0xab, 0xc0, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfe, 0xaa, 0xaa, 0xc0, 0xff, 0xfe, 0x55, 0x56, 0xc0, 0xff, 0xfe, 0x55, 0x56, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xea, 0xaa, 0xaa, 0xc0, 0xff, 0xea, 0xaa, 0xaa, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0xaa, 0xaa, 0xab, 0xc0, 0x08, 0x08, 0x7f, 0xf5, 0xff, 0xfd, 0xc3, 0x0d, 0xff, 0xfd, 0xff, 0xfd, 0xfc, 0xfd, 0x7f, 0xf5, 0x77, 0x75, 0x10, 0x03, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xc0, 0x03, 0x03, 0xff, 0xff, 0xff, 0xff, 0x10, 0x03, 0x55, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x03, 0x55, 0x55, 0xff, 0xff, 0x55, 0x08, 0x08, 0x55, 0x75, 0x55, 0x75, 0x55, 0x75, 0x5f, 0x75, 0x70, 0xf5, 0x70, 0xd5, 0x5f, 0x55, 0x55, 0x55, 0x08, 0x08, 0x55, 0x75, 0x55, 0x75, 0x55, 0x75, 0x5f, 0x75, 0x7f, 0xf5, 0x7f, 0xd5, 0x5f, 0x55, 0x55, 0x55, 0x08, 0x08, 0x55, 0xd5, 0x55, 0xf5, 0x55, 0xfd, 0x7d, 0xdd, 0xff, 0xd5, 0xff, 0x55, 0x7d, 0x55, 0x55, 0x55, 0x08, 0x08, 0x5f, 0xfd, 0x5d, 0x5d, 0x5d, 0x5d, 0x5d, 0x5d, 0xfd, 0xfd, 0xfd, 0xfd, 0xf5, 0xf5, 0x55, 0x55, 0x01, 0x01, 0x00, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x7f, 0xfd, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x5f, 0xfd, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x7f, 0xfd, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x5f, 0xfd, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x7f, 0xfd, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0x03, 0x5f, 0xfd, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x08, 0x08, 0x50, 0x05, 0x43, 0xc1, 0x00, 0x00, 0x30, 0xcc, 0x33, 0x0c, 0x00, 0x00, 0x43, 0xc1, 0x50, 0x05, 0x08, 0x08, 0xc0, 0x03, 0x33, 0xcc, 0x00, 0x30, 0x33, 0x0c, 0x30, 0xcc, 0x0c, 0x00, 0x33, 0xcc, 0xc0, 0x03, 0x08, 0x08, 0x57, 0xd5, 0x5c, 0x35, 0x5c, 0x35, 0xdc, 0x37, 0xd7, 0xd7, 0xdf, 0xf7, 0xfd, 0x7f, 0xf7, 0xdf, 0x04, 0x1f, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x02, 0x05, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0x06, 0x20, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0x20, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf7, 0xff, 0x5f, 0x5f, 0xd7, 0xff, 0x75, 0x5d, 0x55, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x57, 0xd5, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x55, 0x75, 0x75, 0x7f, 0xdf, 0xd5, 0x75, 0x75, 0x55, 0x75, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x55, 0x5f, 0xd5, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x08, 0x7f, 0x5f, 0x57, 0xd7, 0x57, 0xd5, 0x75, 0xdd, 0x77, 0x57, 0xdf, 0x75, 0xdd, 0x77, 0x57, 0xd7, 0x75, 0xdf, 0xf7, 0x55, 0x7d, 0x5f, 0x5d, 0x77, 0xf7, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x0c, 0x7f, 0x5f, 0x5d, 0x5d, 0xfd, 0xd5, 0x75, 0xdf, 0x7d, 0xd5, 0xdf, 0x75, 0xdf, 0xfd, 0xfd, 0xd7, 0x7f, 0xdd, 0xdd, 0xd5, 0x7f, 0x75, 0xdd, 0x5d, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7d, 0x75, 0x77, 0xf7, 0xf5, 0xd7, 0x75, 0x77, 0x57, 0x5d, 0xd7, 0x5d, 0xd7, 0xf7, 0x5d, 0xd7, 0x5d, 0xd7, 0x57, 0xf5, 0x7d, 0x57, 0x57, 0xf7, 0x5d, 0x55, 0x55, 0x55, 0x55, 0x55, 0x20, 0x0c, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xff, 0x55, 0xc3, 0x7d, 0x55, 0x55, 0x55, 0x70, 0x00, 0xd5, 0x70, 0xff, 0x55, 0x55, 0x55, 0xc0, 0x00, 0x35, 0x7c, 0x3f, 0xd5, 0x55, 0x57, 0x00, 0x03, 0x0d, 0x5f, 0xff, 0xff, 0xff, 0xfc, 0x03, 0x00, 0x0d, 0x70, 0x00, 0x03, 0xc0, 0x00, 0x00, 0x3f, 0xfd, 0x7f, 0xff, 0xfc, 0x30, 0x00, 0x00, 0xc0, 0x03, 0xc0, 0x00, 0x03, 0x30, 0x00, 0x03, 0x0f, 0xfc, 0xc0, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc0, 0x03, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x01, 0x01, 0x00, 0x10, 0x10, 0x55, 0x7d, 0x55, 0xf5, 0x55, 0xc3, 0x57, 0x0d, 0x55, 0xc0, 0xdc, 0x0d, 0x55, 0x70, 0xdc, 0x3d, 0x55, 0x5c, 0x30, 0x35, 0x55, 0x70, 0x00, 0xd5, 0x55, 0xc3, 0xfc, 0xd5, 0x55, 0xcf, 0xff, 0x35, 0x57, 0x0f, 0xff, 0x35, 0x57, 0x00, 0xfc, 0x35, 0x57, 0xc0 }; //uint8_t v[] = { 0x0a, 0xaa, 0x55, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x55, 0x03, 0x03, 0x03, 0x00, 0x00, 0x10, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0xc4, 0x00, 0x00, 0xdc, 0x00, 0x00, 0x0f, 0x01, 0x00, 0x91, 0x01, 0x00, 0x0d, 0x02, 0x00, 0x89, 0x02, 0x00, 0xd1, 0x02, 0x00, 0x1f, 0x06, 0x00, 0x67, 0x0f, 0x00, 0x67, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x12, 0x00, 0xa7, 0x12, 0x00, 0x0d, 0x13, 0x00, 0x73, 0x13, 0x00, 0xd9, 0x13, 0x00, 0x3f, 0x14, 0x00, 0xa5, 0x14, 0x00, 0x0b, 0x15, 0x00, 0x71, 0x15, 0x00, 0xd7, 0x15, 0x00, 0x3d, 0x16, 0x00, 0xa3, 0x16, 0x00, 0x09, 0x17, 0x00, 0x6f, 0x17, 0x00, 0xd5, 0x17, 0x00, 0x3b, 0x18, 0x00, 0xa1, 0x18, 0x00, 0x07, 0x19, 0x00, 0x6d, 0x19, 0x00, 0xd3, 0x19, 0x00, 0x39, 0x1a, 0x00, 0x9f, 0x1a, 0x00, 0x05, 0x1b, 0x00, 0x6b, 0x1b, 0x00, 0xd1, 0x1b, 0x00, 0x37, 0x1c, 0x00, 0x9d, 0x1c, 0x00, 0x13, 0x1e, 0x00, 0x89, 0x1f, 0x00, 0xff, 0x20, 0x00, 0x75, 0x22, 0x00, 0xeb, 0x23, 0x00, 0x61, 0x25, 0x00, 0xd7, 0x26, 0x00, 0x4d, 0x28, 0x00, 0xeb, 0x28, 0x00, 0x89, 0x29, 0x00, 0x64, 0x2a, 0x00, 0xa2, 0x2a, 0x00, 0xe0, 0x2a, 0x00, 0x1e, 0x2b, 0x00, 0x5c, 0x2b, 0x00, 0xce, 0x00, 0x00, 0xf1, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x44, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};// 0x70, 0x2c, 0x00, 0x82, 0x2c, 0x00, 0x90, 0x2c, 0x00, 0x9e, 0x2c, 0x00, 0xb0, 0x2c, 0x00, 0xc2, 0x2c, 0x00, 0xd4, 0x2c, 0x00, 0xe6, 0x2c, 0x00, 0xe9, 0x2c, 0x00, 0x1b, 0x2d, 0x00, 0x4d, 0x2d, 0x00, 0x7f, 0x2d, 0x00, 0xb1, 0x2d, 0x00, 0xe3, 0x2d, 0x00, 0x15, 0x2e, 0x00, 0x27, 0x2e, 0x00, 0x39, 0x2e, 0x00, 0x4b, 0x2e, 0x00, 0x6c, 0x2e, 0x00, 0x73, 0x2e, 0x00, 0xb5, 0x2e, 0x00, 0xf7, 0x2e, 0x00, 0x21, 0x2f, 0x00, 0x5f, 0x2f, 0x00, 0xc1, 0x2f, 0x00, 0x02, 0x00, 0x06, 0x03, 0x04, 0x09, 0x0a, 0x05, 0x08, 0x07, 0x00, 0x00, 0x58, 0x00, 0x00, 0x32, 0x00, 0x00, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x10, 0x00, 0x00, 0x08, 0x00, 0x00, 0x50, 0x04, 0x00, 0x30, 0x02, 0x00, 0x20, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00, 0x50, 0x08, 0x00, 0x50, 0x11, 0x00, 0x00, 0x00, 0x28, 0x00, 0x40, 0x15, 0x00, 0x60, 0x12, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x45, 0x00, 0x00, 0x35, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x22, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00, 0x22, 0x00, 0x00, 0x13, 0x00, 0x01, 0x00, 0x02, 0x00, 0x50, 0x01, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x04, 0xff, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x02, 0xff, 0x01, 0x01, 0x00, 0x1e, 0x01, 0x00, 0x03, 0xff, 0x01, 0x01, 0x00, 0x2d, 0x01, 0x00, 0x04, 0xfe, 0x01, 0x01, 0x00, 0x3c, 0x01, 0x00, 0x05, 0xfe, 0x01, 0x01, 0x00, 0x4b, 0x02, 0x00, 0x06, 0xfe, 0x02, 0x02, 0x00, 0x5a, 0x02, 0x00, 0x07, 0xfd, 0x02, 0x02, 0x00, 0x63, 0x02, 0x00, 0x08, 0xfd, 0x02, 0x02, 0x00, 0x64, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0x00, 0x02, 0x04, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x02, 0xff, 0x01, 0x01, 0x00, 0x0f, 0x01, 0x00, 0x03, 0xff, 0x01, 0x01, 0x00, 0x19, 0x01, 0x00, 0x04, 0xfe, 0x01, 0x01, 0x00, 0x23, 0x01, 0x00, 0x05, 0xfe, 0x01, 0x02, 0x00, 0x2d, 0x02, 0x00, 0x06, 0xfe, 0x02, 0x02, 0x00, 0x37, 0x02, 0x00, 0x07, 0xfd, 0x02, 0x02, 0x00, 0x40, 0x02, 0x00, 0x08, 0xfd, 0x02, 0x02, 0x00, 0x41, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xc4, 0x2f, 0x00, 0xff, 0xff, 0xff, 0x06, 0x30, 0x00, 0x48, 0x30, 0x00, 0x8a, 0x30, 0x00, 0xcc, 0x30, 0x00, 0x0e, 0x31, 0x00, 0x50, 0x31, 0x00, 0x92, 0x31, 0x00, 0xd4, 0x31, 0x00, 0x16, 0x32, 0x00, 0xff, 0xff, 0xff, 0x58, 0x32, 0x00, 0xff, 0xff, 0xff, 0xba, 0x32, 0x00, 0x1c, 0x33, 0x00, 0x7e, 0x33, 0x00, 0xe0, 0x33, 0x00, 0x42, 0x34, 0x00, 0xa4, 0x34, 0x00, 0x06, 0x35, 0x00, 0x68, 0x35, 0x00, 0xca, 0x35, 0x00, 0xff, 0xff, 0xff, 0x2c, 0x36, 0x00, 0x3e, 0x36, 0x00, 0x80, 0x36, 0x00, 0xc2, 0x36, 0x00, 0x04, 0x37, 0x00, 0x46, 0x37, 0x00, 0x88, 0x37, 0x00, 0xca, 0x37, 0x00, 0x24, 0x38, 0x00, 0x9d, 0x38, 0x00, 0xf9, 0x38, 0x00, 0x7d, 0x39, 0x00, 0xd7, 0x39, 0x00, 0x50, 0x3a, 0x00, 0xac, 0x3a, 0x00, 0x30, 0x3b, 0x00, 0x72, 0x3b, 0x00, 0xb4, 0x3b, 0x00, 0xf6, 0x3b, 0x00, 0x38, 0x3c, 0x00, 0x7a, 0x3c, 0x00, 0xbc, 0x3c, 0x00, 0xfe, 0x3c, 0x00, 0x40, 0x3d, 0x00, 0x3a, 0x3e, 0x00, 0x34, 0x3f, 0x00, 0x2e, 0x40, 0x00, 0x28, 0x41, 0x00, 0x22, 0x42, 0x00, 0x98, 0x43, 0x00, 0xea, 0x43, 0x00, 0x3c, 0x44, 0x00, 0x8e, 0x44, 0x00, 0xe0, 0x44, 0x00, 0x32, 0x45, 0x00, 0x84, 0x45, 0x00, 0x7e, 0x46, 0x00, 0x78, 0x47, 0x00, 0xba, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0x76, 0x48, 0x00, 0xf0, 0x48, 0x00, 0x6a, 0x49, 0x00, 0xe4, 0x49, 0x00, 0x5e, 0x4a, 0x00, 0xd8, 0x4a, 0x00, 0x52, 0x4b, 0x00, 0xcc, 0x4b, 0x00, 0x46, 0x4c, 0x00, 0xc0, 0x4c, 0x00, 0x3a, 0x4d, 0x00, 0xb4, 0x4d, 0x00, 0x2e, 0x4e, 0x00, 0xa8, 0x4e, 0x00, 0x22, 0x4f, 0x00, 0x9c, 0x4f, 0x00, 0x16, 0x50, 0x00, 0x90, 0x50, 0x00, 0x0a, 0x51, 0x00, 0x84, 0x51, 0x00, 0xfe, 0x51, 0x00, 0x78, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0x6c, 0x53, 0x00, 0xe6, 0x53, 0x00, 0x60, 0x54, 0x00, 0xda, 0x54, 0x00, 0x54, 0x55, 0x00, 0xce, 0x55, 0x00, 0x48, 0x56, 0x00, 0xc2, 0x56, 0x00, 0x3c, 0x57, 0x00, 0xb6, 0x57, 0x00, 0x30, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0x24, 0x59, 0x00, 0x9e, 0x59, 0x00, 0x18, 0x5a, 0x00, 0x92, 0x5a, 0x00, 0x0c, 0x5b, 0x00, 0x86, 0x5b, 0x00, 0x00, 0x5c, 0x00, 0x7a, 0x5c, 0x00, 0xf4, 0x5c, 0x00, 0x6e, 0x5d, 0x00, 0xe8, 0x5d, 0x00, 0x62, 0x5e, 0x00, 0xdc, 0x5e, 0x00, 0x56, 0x5f, 0x00, 0xd0, 0x5f, 0x00, 0x4a, 0x60, 0x00, 0xc4, 0x60, 0x00, 0x3e, 0x61, 0x00, 0xb8, 0x61, 0x00, 0x32, 0x62, 0x00, 0xac, 0x62, 0x00, 0x26, 0x63, 0x00, 0xa0, 0x63, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x94, 0x64, 0x00, 0x0e, 0x65, 0x00, 0x88, 0x65, 0x00, 0x02, 0x66, 0x00, 0x7c, 0x66, 0x00, 0xf6, 0x66, 0x00, 0x70, 0x67, 0x00, 0xea, 0x67, 0x00, 0x64, 0x68, 0x00, 0xde, 0x68, 0x00, 0x58, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0x4c, 0x6a, 0x00, 0xc6, 0x6a, 0x00, 0x40, 0x6b, 0x00, 0xba, 0x6b, 0x00, 0x34, 0x6c, 0x00, 0xae, 0x6c, 0x00, 0x28, 0x6d, 0x00, 0xa2, 0x6d, 0x00, 0x1c, 0x6e, 0x00, 0x96, 0x6e, 0x00, 0x10, 0x6f, 0x00, 0x8a, 0x6f, 0x00, 0x04, 0x70, 0x00, 0x7e, 0x70, 0x00, 0xf8, 0x70, 0x00, 0x72, 0x71, 0x00, 0xec, 0x71, 0x00, 0x66, 0x72, 0x00, 0xe0, 0x72, 0x00, 0x5a, 0x73, 0x00, 0xd4, 0x73, 0x00, 0x4e, 0x74, 0x00, 0xc8, 0x74, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0xbc, 0x75, 0x00, 0x36, 0x76, 0x00, 0xb0, 0x76, 0x00, 0x2a, 0x77, 0x00, 0xa4, 0x77, 0x00, 0x1e, 0x78, 0x00, 0x98, 0x78, 0x00, 0x12, 0x79, 0x00, 0x8c, 0x79, 0x00, 0x06, 0x7a, 0x00, 0x80, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0x74, 0x7b, 0x00, 0xe2, 0x7b, 0x00, 0x50, 0x7c, 0x00, 0xbe, 0x7c, 0x00, 0x2c, 0x7d, 0x00, 0x9a, 0x7d, 0x00, 0x08, 0x7e, 0x00, 0x76, 0x7e, 0x00, 0xe4, 0x7e, 0x00, 0x52, 0x7f, 0x00, 0xc0, 0x7f, 0x00, 0x2e, 0x80, 0x00, 0x9c, 0x80, 0x00, 0x0a, 0x81, 0x00, 0x78, 0x81, 0x00, 0xe6, 0x81, 0x00, 0x54, 0x82, 0x00, 0xc2, 0x82, 0x00, 0x30, 0x83, 0x00, 0x9e, 0x83, 0x00, 0x0c, 0x84, 0x00, 0x7a, 0x84, 0x00, 0xe8, 0x84, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0xc4, 0x85, 0x00, 0x32, 0x86, 0x00, 0xa0, 0x86, 0x00, 0x0e, 0x87, 0x00, 0x7c, 0x87, 0x00, 0xea, 0x87, 0x00, 0x58, 0x88, 0x00, 0xc6, 0x88, 0x00, 0x34, 0x89, 0x00, 0xa2, 0x89, 0x00, 0x10, 0x8a, 0x00, 0x7e, 0x8a, 0x00, 0xec, 0x8a, 0x00, 0x2e, 0x8b, 0x00, 0xac, 0x8b, 0x00, 0x2a, 0x8c, 0x00, 0xa8, 0x8c, 0x00, 0x26, 0x8d, 0x00, 0xa4, 0x8d, 0x00, 0x22, 0x8e, 0x00, 0xa0, 0x8e, 0x00, 0x1e, 0x8f, 0x00, 0x60, 0x8f, 0x00, 0xa2, 0x8f, 0x00, 0xe4, 0x8f, 0x00, 0x13, 0x90, 0x00, 0x42, 0x90, 0x00, 0x65, 0x90, 0x00, 0x88, 0x90, 0x00, 0xab, 0x90, 0x00, 0xce, 0x90, 0x00, 0xf1, 0x90, 0x00, 0x57, 0x91, 0x00, 0xbd, 0x91, 0x00, 0x23, 0x92, 0x00, 0x89, 0x92, 0x00, 0xef, 0x92, 0x00, 0x55, 0x93, 0x00, 0xbb, 0x93, 0x00, 0x21, 0x94, 0x00, 0x87, 0x94, 0x00, 0xed, 0x94, 0x00, 0x53, 0x95, 0x00, 0xb9, 0x95, 0x00, 0x1f, 0x96, 0x00, 0x85, 0x96, 0x00, 0xeb, 0x96, 0x00, 0x51, 0x97, 0x00, 0xb7, 0x97, 0x00, 0x1d, 0x98, 0x00, 0x83, 0x98, 0x00, 0xe9, 0x98, 0x00, 0x4f, 0x99, 0x00, 0xb5, 0x99, 0x00, 0x1b, 0x9a, 0x00, 0x81, 0x9a, 0x00, 0xe7, 0x9a, 0x00, 0x4d, 0x9b, 0x00, 0xb3, 0x9b, 0x00, 0x19, 0x9c, 0x00, 0x7f, 0x9c, 0x00, 0xe5, 0x9c, 0x00, 0x4b, 0x9d, 0x00, 0xb1, 0x9d, 0x00, 0x17, 0x9e, 0x00, 0x7d, 0x9e, 0x00, 0xe3, 0x9e, 0x00, 0x49, 0x9f, 0x00, 0xaf, 0x9f, 0x00, 0x15, 0xa0, 0x00, 0x7b, 0xa0, 0x00, 0xe1, 0xa0, 0x00, 0x47, 0xa1, 0x00, 0xad, 0xa1, 0x00, 0x13, 0xa2, 0x00, 0x79, 0xa2, 0x00, 0xdf, 0xa2, 0x00, 0x45, 0xa3, 0x00, 0xab, 0xa3, 0x00, 0x11, 0xa4, 0x00, 0x77, 0xa4, 0x00, 0xdd, 0xa4, 0x00, 0x43, 0xa5, 0x00, 0xa9, 0xa5, 0x00, 0x0f, 0xa6, 0x00, 0x75, 0xa6, 0x00, 0xdb, 0xa6, 0x00, 0x41, 0xa7, 0x00, 0xa7, 0xa7, 0x00, 0x0d, 0xa8, 0x00, 0x73, 0xa8, 0x00, 0xd9, 0xa8, 0x00, 0x3f, 0xa9, 0x00, 0xa5, 0xa9, 0x00, 0x0b, 0xaa, 0x00, 0x71, 0xaa, 0x00, 0xd7, 0xaa, 0x00, 0x3d, 0xab, 0x00, 0xa3, 0xab, 0x00, 0x09, 0xac, 0x00, 0x6f, 0xac, 0x00, 0xd5, 0xac, 0x00, 0x3b, 0xad, 0x00, 0xa1, 0xad, 0x00, 0x07, 0xae, 0x00, 0x6d, 0xae, 0x00, 0xd3, 0xae, 0x00, 0x39, 0xaf, 0x00, 0x9f, 0xaf, 0x00, 0x05, 0xb0, 0x00, 0x6b, 0xb0, 0x00, 0xd1, 0xb0, 0x00, 0x37, 0xb1, 0x00, 0x9d, 0xb1, 0x00, 0x03, 0xb2, 0x00, 0x69, 0xb2, 0x00, 0xcf, 0xb2, 0x00, 0x35, 0xb3, 0x00, 0x9b, 0xb3, 0x00, 0x01, 0xb4, 0x00, 0x67, 0xb4, 0x00, 0xcd, 0xb4, 0x00, 0x33, 0xb5, 0x00, 0x99, 0xb5, 0x00, 0xff, 0xb5, 0x00, 0x65, 0xb6, 0x00, 0xcb, 0xb6, 0x00, 0x31, 0xb7, 0x00, 0x97, 0xb7, 0x00, 0xfd, 0xb7, 0x00, 0x63, 0xb8, 0x00, 0xc9, 0xb8, 0x00, 0x2f, 0xb9, 0x00, 0x95, 0xb9, 0x00, 0xfb, 0xb9, 0x00, 0x61, 0xba, 0x00, 0xc7, 0xba, 0x00, 0x2d, 0xbb, 0x00, 0x93, 0xbb, 0x00, 0xf9, 0xbb, 0x00, 0x5f, 0xbc, 0x00, 0xc5, 0xbc, 0x00, 0x2b, 0xbd, 0x00, 0x91, 0xbd, 0x00, 0xf7, 0xbd, 0x00, 0x5d, 0xbe, 0x00, 0xc3, 0xbe, 0x00, 0x29, 0xbf, 0x00, 0x8f, 0xbf, 0x00, 0xf5, 0xbf, 0x00, 0x5b, 0xc0, 0x00, 0xc1, 0xc0, 0x00, 0x27, 0xc1, 0x00, 0x8d, 0xc1, 0x00, 0xf3, 0xc1, 0x00, 0x59, 0xc2, 0x00, 0xbf, 0xc2, 0x00, 0x25, 0xc3, 0x00, 0x8b, 0xc3, 0x00, 0xf1, 0xc3, 0x00, 0x57, 0xc4, 0x00, 0xbd, 0xc4, 0x00, 0x23, 0xc5, 0x00, 0x89, 0xc5, 0x00, 0xef, 0xc5, 0x00, 0x55, 0xc6, 0x00, 0xbb, 0xc6, 0x00, 0x21, 0xc7, 0x00, 0x87, 0xc7, 0x00, 0xed, 0xc7, 0x00, 0x53, 0xc8, 0x00, 0xb9, 0xc8, 0x00, 0x1f, 0xc9, 0x00, 0x85, 0xc9, 0x00, 0xeb, 0xc9, 0x00, 0x51, 0xca, 0x00, 0xb7, 0xca, 0x00, 0x1d, 0xcb, 0x00, 0x83, 0xcb, 0x00, 0xe9, 0xcb, 0x00, 0x4f, 0xcc, 0x00, 0xb5, 0xcc, 0x00, 0x1b, 0xcd, 0x00, 0x81, 0xcd, 0x00, 0xe7, 0xcd, 0x00, 0x4d, 0xce, 0x00, 0xb3, 0xce, 0x00, 0x19, 0xcf, 0x00, 0x7f, 0xcf, 0x00, 0xe5, 0xcf, 0x00, 0x4b, 0xd0, 0x00, 0xb1, 0xd0, 0x00, 0x17, 0xd1, 0x00, 0x7d, 0xd1, 0x00, 0xe3, 0xd1, 0x00, 0x49, 0xd2, 0x00, 0xaf, 0xd2, 0x00, 0x15, 0xd3, 0x00, 0x7b, 0xd3, 0x00, 0xe1, 0xd3, 0x00, 0x47, 0xd4, 0x00, 0xad, 0xd4, 0x00, 0x13, 0xd5, 0x00, 0x79, 0xd5, 0x00, 0xdf, 0xd5, 0x00, 0x45, 0xd6, 0x00, 0xab, 0xd6, 0x00, 0x11, 0xd7, 0x00, 0x77, 0xd7, 0x00, 0xdd, 0xd7, 0x00, 0x43, 0xd8, 0x00, 0xa9, 0xd8, 0x00, 0x0f, 0xd9, 0x00, 0x75, 0xd9, 0x00, 0xdb, 0xd9, 0x00, 0x41, 0xda, 0x00, 0xa7, 0xda, 0x00, 0x0d, 0xdb, 0x00, 0x73, 0xdb, 0x00, 0xd9, 0xdb, 0x00, 0x3f, 0xdc, 0x00, 0xa5, 0xdc, 0x00, 0x0b, 0xdd, 0x00, 0x71, 0xdd, 0x00, 0xd7, 0xdd, 0x00, 0x3d, 0xde, 0x00, 0xa3, 0xde, 0x00, 0x09, 0xdf, 0x00, 0x6f, 0xdf, 0x00, 0xd5, 0xdf, 0x00, 0x3b, 0xe0, 0x00, 0xa1, 0xe0, 0x00, 0x07, 0xe1, 0x00, 0x6d, 0xe1, 0x00, 0xd3, 0xe1, 0x00, 0x39, 0xe2, 0x00, 0x9f, 0xe2, 0x00, 0x05, 0xe3, 0x00, 0x6b, 0xe3, 0x00, 0xd1, 0xe3, 0x00, 0x37, 0xe4, 0x00, 0x9d, 0xe4, 0x00, 0x03, 0xe5, 0x00, 0x69, 0xe5, 0x00, 0xcf, 0xe5, 0x00, 0x35, 0xe6, 0x00, 0x9b, 0xe6, 0x00, 0x01, 0xe7, 0x00, 0x67, 0xe7, 0x00, 0xcd, 0xe7, 0x00, 0x33, 0xe8, 0x00, 0x99, 0xe8, 0x00, 0xff, 0xe8, 0x00, 0x65, 0xe9, 0x00, 0xcb, 0xe9, 0x00, 0x31, 0xea, 0x00, 0x97, 0xea, 0x00, 0xfd, 0xea, 0x00, 0x63, 0xeb, 0x00, 0xc9, 0xeb, 0x00, 0x2f, 0xec, 0x00, 0x95, 0xec, 0x00, 0xfb, 0xec, 0x00, 0x61, 0xed, 0x00, 0xc7, 0xed, 0x00, 0x2d, 0xee, 0x00, 0x93, 0xee, 0x00, 0xf9, 0xee, 0x00, 0x5f, 0xef, 0x00, 0xc5, 0xef, 0x00, 0x2b, 0xf0, 0x00, 0x91, 0xf0, 0x00, 0xf7, 0xf0, 0x00, 0x5d, 0xf1, 0x00, 0xc3, 0xf1, 0x00, 0x29, 0xf2, 0x00, 0x8f, 0xf2, 0x00, 0xf5, 0xf2, 0x00, 0x5b, 0xf3, 0x00, 0xc1, 0xf3, 0x00, 0x27, 0xf4, 0x00, 0x8d, 0xf4, 0x00, 0xf3, 0xf4, 0x00, 0x59, 0xf5, 0x00, 0xbf, 0xf5, 0x00, 0x25, 0xf6, 0x00, 0x8b, 0xf6, 0x00, 0xf1, 0xf6, 0x00, 0x57, 0xf7, 0x00, 0xbd, 0xf7, 0x00, 0x23, 0xf8, 0x00, 0x89, 0xf8, 0x00, 0xef, 0xf8, 0x00, 0x55, 0xf9, 0x00, 0xbb, 0xf9, 0x00, 0x21, 0xfa, 0x00, 0x87, 0xfa, 0x00, 0xed, 0xfa, 0x00, 0x53, 0xfb, 0x00, 0xb9, 0xfb, 0x00, 0x1f, 0xfc, 0x00, 0x85, 0xfc, 0x00, 0xeb, 0xfc, 0x00, 0x51, 0xfd, 0x00, 0xb7, 0xfd, 0x00, 0x1d, 0xfe, 0x00, 0x83, 0xfe, 0x00, 0xe9, 0xfe, 0x00, 0x4f, 0xff, 0x00, 0xb5, 0xff, 0x00, 0x1b, 0x00, 0x01, 0x81, 0x00, 0x01, 0xe7, 0x00, 0x01, 0x4d, 0x01, 0x01, 0xb3, 0x01, 0x01, 0x19, 0x02, 0x01, 0x7f, 0x02, 0x01, 0xe5, 0x02, 0x01, 0x4b, 0x03, 0x01, 0xb1, 0x03, 0x01, 0x17, 0x04, 0x01, 0x7d, 0x04, 0x01, 0xe3, 0x04, 0x01, 0x49, 0x05, 0x01, 0xaf, 0x05, 0x01, 0x15, 0x06, 0x01, 0x7b, 0x06, 0x01, 0xe1, 0x06, 0x01, 0x47, 0x07, 0x01, 0xad, 0x07, 0x01, 0x13, 0x08, 0x01, 0x79, 0x08, 0x01, 0xdf, 0x08, 0x01, 0x45, 0x09, 0x01, 0xab, 0x09, 0x01, 0x11, 0x0a, 0x01, 0x77, 0x0a, 0x01, 0xdd, 0x0a, 0x01, 0x43, 0x0b, 0x01, 0xa9, 0x0b, 0x01, 0x0f, 0x0c, 0x01, 0x75, 0x0c, 0x01, 0xdb, 0x0c, 0x01, 0x41, 0x0d, 0x01, 0xa7, 0x0d, 0x01, 0x0d, 0x0e, 0x01, 0x73, 0x0e, 0x01, 0xd9, 0x0e, 0x01, 0x3f, 0x0f, 0x01, 0xa5, 0x0f, 0x01, 0x0b, 0x10, 0x01, 0x71, 0x10, 0x01, 0xd7, 0x10, 0x01, 0x3d, 0x11, 0x01, 0xa3, 0x11, 0x01, 0x09, 0x12, 0x01, 0x6f, 0x12, 0x01, 0xd5, 0x12, 0x01, 0x3b, 0x13, 0x01, 0xa1, 0x13, 0x01, 0x07, 0x14, 0x01, 0x6d, 0x14, 0x01, 0xd3, 0x14, 0x01, 0x39, 0x15, 0x01, 0x9f, 0x15, 0x01, 0x05, 0x16, 0x01, 0x6b, 0x16, 0x01, 0xd1, 0x16, 0x01, 0x37, 0x17, 0x01, 0x9d, 0x17, 0x01, 0x03, 0x18, 0x01, 0x69, 0x18, 0x01, 0xcf, 0x18, 0x01, 0x35, 0x19, 0x01, 0x9b, 0x19, 0x01, 0x01, 0x1a, 0x01, 0x67, 0x1a, 0x01, 0xcd, 0x1a, 0x01, 0x33, 0x1b, 0x01, 0x99, 0x1b, 0x01, 0xff, 0x1b, 0x01, 0x65, 0x1c, 0x01, 0xcb, 0x1c, 0x01, 0x31, 0x1d, 0x01, 0x97, 0x1d, 0x01, 0xfd, 0x1d, 0x01, 0x63, 0x1e, 0x01, 0xc9, 0x1e, 0x01, 0x2f, 0x1f, 0x01, 0x95, 0x1f, 0x01, 0xfb, 0x1f, 0x01, 0x61, 0x20, 0x01, 0xc7, 0x20, 0x01, 0x2d, 0x21, 0x01, 0x93, 0x21, 0x01, 0xf9, 0x21, 0x01, 0x5f, 0x22, 0x01, 0xc5, 0x22, 0x01, 0x2b, 0x23, 0x01, 0x91, 0x23, 0x01, 0xf7, 0x23, 0x01, 0x5d, 0x24, 0x01, 0xc3, 0x24, 0x01, 0x29, 0x25, 0x01, 0x8f, 0x25, 0x01, 0xf5, 0x25, 0x01, 0x5b, 0x26, 0x01, 0xc1, 0x26, 0x01, 0x27, 0x27, 0x01, 0x8d, 0x27, 0x01, 0xf3, 0x27, 0x01, 0x59, 0x28, 0x01, 0xbf, 0x28, 0x01, 0x25, 0x29, 0x01, 0x8b, 0x29, 0x01, 0xf1, 0x29, 0x01, 0x57, 0x2a, 0x01, 0xbd, 0x2a, 0x01, 0x23, 0x2b, 0x01, 0x89, 0x2b, 0x01, 0xef, 0x2b, 0x01, 0x55, 0x2c, 0x01, 0xbb, 0x2c, 0x01, 0x21, 0x2d, 0x01, 0x87, 0x2d, 0x01, 0xed, 0x2d, 0x01, 0x53, 0x2e, 0x01, 0xb9, 0x2e, 0x01, 0x1f, 0x2f, 0x01, 0x85, 0x2f, 0x01, 0xeb, 0x2f, 0x01, 0x51, 0x30, 0x01, 0xb7, 0x30, 0x01, 0x1d, 0x31, 0x01, 0x83, 0x31, 0x01, 0xe9, 0x31, 0x01, 0x4f, 0x32, 0x01, 0xb5, 0x32, 0x01, 0x1b, 0x33, 0x01, 0x81, 0x33, 0x01, 0xe7, 0x33, 0x01, 0x4d, 0x34, 0x01, 0xb3, 0x34, 0x01, 0x19, 0x35, 0x01, 0x7f, 0x35, 0x01, 0xe5, 0x35, 0x01, 0x4b, 0x36, 0x01, 0xb1, 0x36, 0x01, 0x17, 0x37, 0x01, 0x7d, 0x37, 0x01, 0xe3, 0x37, 0x01, 0x49, 0x38, 0x01, 0xaf, 0x38, 0x01, 0x15, 0x39, 0x01, 0x7b, 0x39, 0x01, 0xe1, 0x39, 0x01, 0x47, 0x3a, 0x01, 0xad, 0x3a, 0x01, 0x13, 0x3b, 0x01, 0x79, 0x3b, 0x01, 0xdf, 0x3b, 0x01, 0x45, 0x3c, 0x01, 0xab, 0x3c, 0x01, 0x11, 0x3d, 0x01, 0x77, 0x3d, 0x01, 0xdd, 0x3d, 0x01, 0x43, 0x3e, 0x01, 0xa9, 0x3e, 0x01, 0x0f, 0x3f, 0x01, 0x75, 0x3f, 0x01, 0xdb, 0x3f, 0x01, 0x41, 0x40, 0x01, 0xa7, 0x40, 0x01, 0x0d, 0x41, 0x01, 0x73, 0x41, 0x01, 0xd9, 0x41, 0x01, 0x3f, 0x42, 0x01, 0xa5, 0x42, 0x01, 0x0b, 0x43, 0x01, 0x71, 0x43, 0x01, 0xd7, 0x43, 0x01, 0x3d, 0x44, 0x01, 0xa3, 0x44, 0x01, 0x09, 0x45, 0x01, 0x6f, 0x45, 0x01, 0xd5, 0x45, 0x01, 0x3b, 0x46, 0x01, 0xa1, 0x46, 0x01, 0x07, 0x47, 0x01, 0x6d, 0x47, 0x01, 0xd3, 0x47, 0x01, 0x39, 0x48, 0x01, 0x9f, 0x48, 0x01, 0x05, 0x49, 0x01, 0x6b, 0x49, 0x01, 0xd1, 0x49, 0x01, 0x37, 0x4a, 0x01, 0x9d, 0x4a, 0x01, 0x03, 0x4b, 0x01, 0x69, 0x4b, 0x01, 0xcf, 0x4b, 0x01, 0x35, 0x4c, 0x01, 0x9b, 0x4c, 0x01, 0x01, 0x4d, 0x01, 0x67, 0x4d, 0x01, 0xcd, 0x4d, 0x01, 0x33, 0x4e, 0x01, 0x99, 0x4e, 0x01, 0xff, 0x4e, 0x01, 0x65, 0x4f, 0x01, 0xcb, 0x4f, 0x01, 0x31, 0x50, 0x01, 0x97, 0x50, 0x01, 0xfd, 0x50, 0x01, 0x63, 0x51, 0x01, 0xc9, 0x51, 0x01, 0x2f, 0x52, 0x01, 0x95, 0x52, 0x01, 0xfb, 0x52, 0x01, 0x61, 0x53, 0x01, 0xc7, 0x53, 0x01, 0x2d, 0x54, 0x01, 0x93, 0x54, 0x01, 0xf9, 0x54, 0x01, 0x5f, 0x55, 0x01, 0xc5, 0x55, 0x01, 0x2b, 0x56, 0x01, 0x91, 0x56, 0x01, 0xf7, 0x56, 0x01, 0x5d, 0x57, 0x01, 0xc3, 0x57, 0x01, 0x29, 0x58, 0x01, 0x8f, 0x58, 0x01, 0xf5, 0x58, 0x01, 0x5b, 0x59, 0x01, 0xc1, 0x59, 0x01, 0x27, 0x5a, 0x01, 0x8d, 0x5a, 0x01, 0xf3, 0x5a, 0x01, 0x59, 0x5b, 0x01, 0xbf, 0x5b, 0x01, 0x25, 0x5c, 0x01, 0x8b, 0x5c, 0x01, 0xf1, 0x5c, 0x01, 0x57, 0x5d, 0x01, 0xbd, 0x5d, 0x01, 0x23, 0x5e, 0x01, 0x89, 0x5e, 0x01, 0xef, 0x5e, 0x01, 0x55, 0x5f, 0x01, 0xbb, 0x5f, 0x01, 0x21, 0x60, 0x01, 0x87, 0x60, 0x01, 0xed, 0x60, 0x01, 0x53, 0x61, 0x01, 0xb9, 0x61, 0x01, 0x1f, 0x62, 0x01, 0x85, 0x62, 0x01, 0xeb, 0x62, 0x01, 0x51, 0x63, 0x01, 0xb7, 0x63, 0x01, 0x1d, 0x64, 0x01, 0x83, 0x64, 0x01, 0xe9, 0x64, 0x01, 0x4f, 0x65, 0x01, 0xb5, 0x65, 0x01, 0x1b, 0x66, 0x01, 0x81, 0x66, 0x01, 0xe7, 0x66, 0x01, 0x4d, 0x67, 0x01, 0xb3, 0x67, 0x01, 0x19, 0x68, 0x01, 0x7f, 0x68, 0x01, 0xe5, 0x68, 0x01, 0x4b, 0x69, 0x01, 0xb1, 0x69, 0x01, 0x17, 0x6a, 0x01, 0x7d, 0x6a, 0x01, 0xe3, 0x6a, 0x01, 0x49, 0x6b, 0x01, 0xaf, 0x6b, 0x01, 0x15, 0x6c, 0x01, 0x7b, 0x6c, 0x01, 0xe1, 0x6c, 0x01, 0x47, 0x6d, 0x01, 0xad, 0x6d, 0x01, 0x13, 0x6e, 0x01, 0x79, 0x6e, 0x01, 0xdf, 0x6e, 0x01, 0x45, 0x6f, 0x01, 0xab, 0x6f, 0x01, 0x11, 0x70, 0x01, 0x77, 0x70, 0x01, 0xdd, 0x70, 0x01, 0x43, 0x71, 0x01, 0xa9, 0x71, 0x01, 0x0f, 0x72, 0x01, 0x75, 0x72, 0x01, 0xdb, 0x72, 0x01, 0x41, 0x73, 0x01, 0xa7, 0x73, 0x01, 0x0d, 0x74, 0x01, 0x73, 0x74, 0x01, 0xd9, 0x74, 0x01, 0x3f, 0x75, 0x01, 0xa5, 0x75, 0x01, 0x0b, 0x76, 0x01, 0x71, 0x76, 0x01, 0xd7, 0x76, 0x01, 0x3d, 0x77, 0x01, 0xa3, 0x77, 0x01, 0x09, 0x78, 0x01, 0x6f, 0x78, 0x01, 0xd5, 0x78, 0x01, 0x3b, 0x79, 0x01, 0xa1, 0x79, 0x01, 0x07, 0x7a, 0x01, 0x6d, 0x7a, 0x01, 0xd3, 0x7a, 0x01, 0x39, 0x7b, 0x01, 0x9f, 0x7b, 0x01, 0x05, 0x7c, 0x01, 0x6b, 0x7c, 0x01, 0xd1, 0x7c, 0x01, 0x37, 0x7d, 0x01, 0x9d, 0x7d, 0x01, 0x03, 0x7e, 0x01, 0x69, 0x7e, 0x01, 0xcf, 0x7e, 0x01, 0x35, 0x7f, 0x01, 0x9b, 0x7f, 0x01, 0x01, 0x80, 0x01, 0x67, 0x80, 0x01, 0xcd, 0x80, 0x01, 0x33, 0x81, 0x01, 0x99, 0x81, 0x01, 0xff, 0x81, 0x01, 0x65, 0x82, 0x01, 0xcb, 0x82, 0x01, 0x31, 0x83, 0x01, 0x97, 0x83, 0x01, 0xfd, 0x83, 0x01, 0x63, 0x84, 0x01, 0xc9, 0x84, 0x01, 0x2f, 0x85, 0x01, 0x95, 0x85, 0x01, 0xfb, 0x85, 0x01, 0x61, 0x86, 0x01, 0xc7, 0x86, 0x01, 0x2d, 0x87, 0x01, 0x93, 0x87, 0x01, 0xf9, 0x87, 0x01, 0x5f, 0x88, 0x01, 0xc5, 0x88, 0x01, 0x2b, 0x89, 0x01, 0x91, 0x89, 0x01, 0xf7, 0x89, 0x01, 0x5d, 0x8a, 0x01, 0xc3, 0x8a, 0x01, 0x29, 0x8b, 0x01, 0x8f, 0x8b, 0x01, 0xf5, 0x8b, 0x01, 0x5b, 0x8c, 0x01, 0xc1, 0x8c, 0x01, 0x27, 0x8d, 0x01, 0x8d, 0x8d, 0x01, 0xf3, 0x8d, 0x01, 0x59, 0x8e, 0x01, 0xbf, 0x8e, 0x01, 0x25, 0x8f, 0x01, 0x8b, 0x8f, 0x01, 0xf1, 0x8f, 0x01, 0x57, 0x90, 0x01, 0xbd, 0x90, 0x01, 0x23, 0x91, 0x01, 0x89, 0x91, 0x01, 0xef, 0x91, 0x01, 0x55, 0x92, 0x01, 0xbb, 0x92, 0x01, 0x21, 0x93, 0x01, 0x87, 0x93, 0x01, 0xed, 0x93, 0x01, 0x53, 0x94, 0x01, 0xb9, 0x94, 0x01, 0x1f, 0x95, 0x01, 0x85, 0x95, 0x01, 0xeb, 0x95, 0x01, 0x51, 0x96, 0x01, 0xb7, 0x96, 0x01, 0x1d, 0x97, 0x01, 0x83, 0x97, 0x01, 0xe9, 0x97, 0x01, 0x4f, 0x98, 0x01, 0xb5, 0x98, 0x01, 0x1b, 0x99, 0x01, 0x81, 0x99, 0x01, 0xe7, 0x99, 0x01, 0x4d, 0x9a, 0x01, 0xb3, 0x9a, 0x01, 0x19, 0x9b, 0x01, 0x7f, 0x9b, 0x01, 0xe5, 0x9b, 0x01, 0x4b, 0x9c, 0x01, 0xb1, 0x9c, 0x01, 0x17, 0x9d, 0x01, 0x7d, 0x9d, 0x01, 0xe3, 0x9d, 0x01, 0x49, 0x9e, 0x01, 0xaf, 0x9e, 0x01, 0x15, 0x9f, 0x01, 0x7b, 0x9f, 0x01, 0xe1, 0x9f, 0x01, 0x47, 0xa0, 0x01, 0xad, 0xa0, 0x01, 0x13, 0xa1, 0x01, 0x79, 0xa1, 0x01, 0xdf, 0xa1, 0x01, 0x45, 0xa2, 0x01, 0xab, 0xa2, 0x01, 0x11, 0xa3, 0x01, 0x77, 0xa3, 0x01, 0xdd, 0xa3, 0x01, 0x43, 0xa4, 0x01, 0xa9, 0xa4, 0x01, 0x0f, 0xa5, 0x01, 0x75, 0xa5, 0x01, 0xdb, 0xa5, 0x01, 0x41, 0xa6, 0x01, 0xa7, 0xa6, 0x01, 0x0d, 0xa7, 0x01, 0x73, 0xa7, 0x01, 0xd9, 0xa7, 0x01, 0x3f, 0xa8, 0x01, 0xa5, 0xa8, 0x01, 0x0b, 0xa9, 0x01, 0x71, 0xa9, 0x01, 0xd7, 0xa9, 0x01, 0x3d, 0xaa, 0x01, 0xa3, 0xaa, 0x01, 0x09, 0xab, 0x01, 0x6f, 0xab, 0x01, 0xd5, 0xab, 0x01, 0x3b, 0xac, 0x01, 0xa1, 0xac, 0x01, 0x07, 0xad, 0x01, 0x6d, 0xad, 0x01, 0xd3, 0xad, 0x01, 0x39, 0xae, 0x01, 0x9f, 0xae, 0x01, 0x05, 0xaf, 0x01, 0x6b, 0xaf, 0x01, 0xd1, 0xaf, 0x01, 0x37, 0xb0, 0x01, 0x9d, 0xb0, 0x01, 0x03, 0xb1, 0x01, 0x69, 0xb1, 0x01, 0xcf, 0xb1, 0x01, 0x35, 0xb2, 0x01, 0x9b, 0xb2, 0x01, 0x01, 0xb3, 0x01, 0x67, 0xb3, 0x01, 0xcd, 0xb3, 0x01, 0x33, 0xb4, 0x01, 0x99, 0xb4, 0x01, 0xff, 0xb4, 0x01, 0x65, 0xb5, 0x01, 0xcb, 0xb5, 0x01, 0x31, 0xb6, 0x01, 0x97, 0xb6, 0x01, 0xfd, 0xb6, 0x01, 0x63, 0xb7, 0x01, 0xc9, 0xb7, 0x01, 0x2f, 0xb8, 0x01, 0x95, 0xb8, 0x01, 0xfb, 0xb8, 0x01, 0x61, 0xb9, 0x01, 0xc7, 0xb9, 0x01, 0x2d, 0xba, 0x01, 0x93, 0xba, 0x01, 0xf9, 0xba, 0x01, 0x5f, 0xbb, 0x01, 0xc5, 0xbb, 0x01, 0x2b, 0xbc, 0x01, 0x91, 0xbc, 0x01, 0xf7, 0xbc, 0x01, 0x5d, 0xbd, 0x01, 0xc3, 0xbd, 0x01, 0x29, 0xbe, 0x01, 0x8f, 0xbe, 0x01, 0xf5, 0xbe, 0x01, 0x5b, 0xbf, 0x01, 0xc1, 0xbf, 0x01, 0x27, 0xc0, 0x01, 0x8d, 0xc0, 0x01, 0xf3, 0xc0, 0x01, 0x59, 0xc1, 0x01, 0xbf, 0xc1, 0x01, 0x25, 0xc2, 0x01, 0x8b, 0xc2, 0x01, 0xf1, 0xc2, 0x01, 0x57, 0xc3, 0x01, 0xbd, 0xc3, 0x01, 0x23, 0xc4, 0x01, 0x89, 0xc4, 0x01, 0xef, 0xc4, 0x01, 0x55, 0xc5, 0x01, 0xbb, 0xc5, 0x01, 0x21, 0xc6, 0x01, 0x87, 0xc6, 0x01, 0xed, 0xc6, 0x01, 0x53, 0xc7, 0x01, 0xb9, 0xc7, 0x01, 0x1f, 0xc8, 0x01, 0x85, 0xc8, 0x01, 0xeb, 0xc8, 0x01, 0x51, 0xc9, 0x01, 0xb7, 0xc9, 0x01, 0x1d, 0xca, 0x01, 0x83, 0xca, 0x01, 0xe9, 0xca, 0x01, 0x4f, 0xcb, 0x01, 0xb5, 0xcb, 0x01, 0x1b, 0xcc, 0x01, 0x1f, 0x04, 0x07, 0x04, 0x04, 0x02, 0x03, 0x10, 0x00, 0x00, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x0a, 0x06, 0x00, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x10, 0x00, 0x00, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x1f, 0x00, 0x08, 0x00, 0x06, 0x00, 0x03, 0x0a, 0x06, 0x00, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x1e, 0x0b, 0x06, 0x04, 0x04, 0x03, 0x04, 0x0c, 0x04, 0x00, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x13, 0xf8, 0x01, 0x87, 0xf9, 0x01, 0x87, 0xf9, 0x01, 0x35, 0xee, 0x01, 0xa9, 0xf2, 0x01, 0xa9, 0xf2, 0x01, 0x35, 0xee, 0x01, 0xa9, 0xf2, 0x01, 0xa9, 0xf2, 0x01, 0x1e, 0x04, 0x0b, 0x04, 0x08, 0x02, 0x06, 0x04, 0x06, 0x06, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x18, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x0a, 0x06, 0x00, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x08, 0x04, 0x04, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0xb7, 0x11, 0x02, 0x21, 0x17, 0x02, 0x09, 0x1d, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x03, 0x05, 0x08, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0x7c, 0x00, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x73, 0x30, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xf0, 0x3c, 0x03, 0x55, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0xff, 0x00, 0x03, 0x55, 0x55, 0xff, 0x00, 0x3d, 0x55, 0x55, 0xff, 0x00, 0xcd, 0x55, 0x55, 0xcf, 0xff, 0x0d, 0x55, 0x55, 0x73, 0x30, 0x3d, 0x55, 0x55, 0x73, 0xf0, 0xf5, 0x55, 0x55, 0x73, 0xf0, 0x35, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x7f, 0x55, 0x57, 0xff, 0x55, 0xff, 0xd5, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x0f, 0x00, 0xf0, 0xd5, 0x57, 0x30, 0xc3, 0x0c, 0xd5, 0x57, 0x00, 0x3c, 0x00, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x57, 0x3f, 0xff, 0xfc, 0xd5, 0x57, 0xf0, 0xc3, 0x0f, 0xd5, 0x55, 0x73, 0xff, 0xcd, 0x55, 0x55, 0xc3, 0xff, 0xc3, 0x55, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x03, 0x00, 0xc0, 0xd5, 0x57, 0x0c, 0x00, 0x30, 0xd5, 0x57, 0x00, 0x3c, 0x00, 0xd5, 0x55, 0xc0, 0xff, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x3f, 0x0f, 0xc3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x00, 0xf0, 0x0d, 0x55, 0x55, 0xff, 0x0f, 0xf5, 0x55, 0x57, 0x33, 0xfc, 0xcd, 0x55, 0x57, 0xf3, 0xfc, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x30, 0x00, 0x0c, 0xd5, 0x57, 0x0c, 0x00, 0x30, 0xd5, 0x57, 0x00, 0xff, 0x00, 0xd5, 0x5f, 0x03, 0xff, 0xc0, 0xf5, 0x5c, 0xc3, 0xff, 0xc3, 0x35, 0x5f, 0x3f, 0xff, 0xfc, 0xf5, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0xc3, 0xff, 0xc3, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x7f, 0x55, 0x57, 0xff, 0x55, 0xff, 0xd5, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x03, 0x00, 0xc0, 0xd5, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x30, 0x3c, 0x0c, 0xd5, 0x55, 0xcc, 0x3c, 0x33, 0xd5, 0x55, 0xcc, 0x3c, 0x33, 0x55, 0x55, 0xc3, 0xc3, 0xc3, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xd7, 0xf5, 0x55, 0x55, 0x5f, 0x55, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x5c, 0x3f, 0xff, 0xc3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x55, 0xff, 0xff, 0xf5, 0x55, 0x55, 0xc0, 0x00, 0x35, 0x55, 0x57, 0x30, 0x00, 0xcd, 0x55, 0x57, 0xf0, 0x00, 0xfd, 0x55, 0x55, 0x70, 0x00, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0x55, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0x70, 0x00, 0x3d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x70, 0x0c, 0xd5, 0x55, 0x57, 0xc0, 0xfc, 0xd5, 0x55, 0x55, 0xf0, 0x3f, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0x57, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0x70, 0x00, 0x3d, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x30, 0xcd, 0x55, 0x55, 0xfc, 0x3f, 0xf5, 0x55, 0x55, 0x70, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x70, 0x3f, 0xf5, 0x55, 0x55, 0xc0, 0x0f, 0xf5, 0x55, 0x7f, 0xc0, 0x0f, 0xf5, 0x5f, 0xc0, 0xc0, 0x0f, 0x55, 0x5f, 0xc0, 0xc0, 0xcf, 0xd5, 0x55, 0xc0, 0xc0, 0xcf, 0xd5, 0x57, 0xc0, 0x3c, 0xcf, 0xf5, 0x5f, 0xfc, 0x03, 0x0f, 0xf5, 0x5f, 0xff, 0xff, 0xf7, 0xd5, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x3c, 0x03, 0xc3, 0x55, 0x5c, 0xc3, 0x0c, 0x33, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0xc3, 0x0c, 0x33, 0x55, 0x57, 0x30, 0xf0, 0xcc, 0xd5, 0x55, 0xff, 0xff, 0xf0, 0xd5, 0x55, 0x73, 0x0c, 0x03, 0x55, 0x55, 0xcc, 0xfc, 0x0d, 0x55, 0x55, 0xfc, 0xff, 0x0d, 0x55, 0x55, 0x5c, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x55, 0xf5, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x00, 0xc3, 0x00, 0xd5, 0x57, 0x3f, 0xc3, 0xfc, 0xd5, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x5c, 0xcc, 0x35, 0x55, 0x55, 0x73, 0xff, 0xcd, 0x55, 0x55, 0x70, 0xfc, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xc0, 0x30, 0x03, 0x55, 0x55, 0xc0, 0xc0, 0x03, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xfc, 0x00, 0x03, 0x55, 0x55, 0xff, 0x03, 0xc3, 0x55, 0x55, 0x7f, 0x03, 0x3d, 0x55, 0x55, 0x5f, 0xff, 0x35, 0x55, 0x55, 0x5c, 0xcc, 0x0d, 0x55, 0x55, 0x57, 0x3c, 0x03, 0x55, 0x55, 0x57, 0x3c, 0x3f, 0x55, 0x55, 0x57, 0xff, 0xf5, 0x55, 0x55, 0x55, 0x7d, 0xfd, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0x7f, 0x55, 0x55, 0x55, 0xff, 0xff, 0xd5, 0x55, 0x55, 0xff, 0xff, 0xd5, 0x55, 0x55, 0xff, 0x00, 0x35, 0x55, 0x57, 0xf0, 0x00, 0x3d, 0x55, 0x57, 0xc0, 0x03, 0x03, 0x55, 0x57, 0x00, 0x3c, 0x03, 0x55, 0x57, 0x00, 0x00, 0x0f, 0x55, 0x57, 0x00, 0x00, 0x35, 0x55, 0x57, 0xc0, 0x03, 0xd5, 0x55, 0x55, 0x7f, 0xff, 0x55, 0x55, 0x55, 0xc0, 0xcf, 0x55, 0x55, 0x57, 0x30, 0xfd, 0x55, 0x55, 0x57, 0xf0, 0xfd, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x7d, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xf5, 0x55, 0x55, 0x5f, 0xfd, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0x00, 0x0d, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x0f, 0xc3, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0x70, 0x00, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x5c, 0x3c, 0xd5, 0x55, 0x55, 0x5f, 0x0f, 0xd5, 0x55, 0x55, 0x5c, 0xff, 0xd5, 0x55, 0x55, 0x70, 0x0f, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3c, 0x0f, 0x55, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0xc0, 0x00, 0xff, 0x55, 0x55, 0xc0, 0xf0, 0xff, 0x55, 0x55, 0x70, 0xcc, 0xfd, 0x55, 0x55, 0x5f, 0xcf, 0xd5, 0x55, 0x55, 0x5c, 0xcc, 0xd5, 0x55, 0x55, 0x5c, 0x3f, 0xd5, 0x55, 0x55, 0x5c, 0x0f, 0xd5, 0x55, 0x55, 0x70, 0x0f, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x55, 0xfd, 0x55, 0x55, 0x7f, 0xdf, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0xc3, 0x55, 0x55, 0xcc, 0x00, 0x03, 0x55, 0x55, 0x73, 0x00, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x73, 0x30, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0x7f, 0x55, 0x55, 0xff, 0xd5, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0xd5, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0x70, 0x00, 0x03, 0x55, 0x55, 0xc3, 0x00, 0x30, 0xd5, 0x55, 0xcc, 0xc0, 0xcc, 0xd5, 0x55, 0xc3, 0x00, 0x30, 0xd5, 0x57, 0xc0, 0x3f, 0x00, 0xd5, 0x57, 0x30, 0xff, 0xc3, 0x55, 0x55, 0xcf, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xc3, 0xfc, 0x03, 0x55, 0x55, 0xc3, 0xfc, 0x3c, 0xd5, 0x55, 0x7f, 0xfc, 0x37, 0xd5, 0x55, 0x5f, 0x7f, 0xd5, 0x55, 0x55, 0x55, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x3c, 0x03, 0xc3, 0x55, 0x5c, 0xf3, 0x0f, 0x33, 0x55, 0x5c, 0xff, 0x0f, 0xf3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x0f, 0xf0, 0x0d, 0x55, 0x55, 0xfc, 0x3f, 0xf5, 0x55, 0x55, 0xc3, 0xcc, 0x3d, 0x55, 0x55, 0x70, 0xfc, 0xf3, 0x55, 0x55, 0x70, 0xfc, 0xdf, 0x55, 0x55, 0x7f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xcd, 0x55, 0x5f, 0xff, 0xff, 0xfd, 0x55, 0x7f, 0xff, 0xff, 0xd5, 0x55, 0x70, 0x00, 0x03, 0xd5, 0x55, 0xff, 0xff, 0xfc, 0xd5, 0x55, 0xc0, 0x00, 0x0f, 0xd5, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0x7c, 0x00, 0x0c, 0xd5, 0x55, 0x5f, 0xff, 0xf0, 0x35, 0x55, 0x7f, 0x3f, 0xfc, 0x0d, 0x55, 0x7f, 0x3f, 0xfc, 0x0d, 0x55, 0x70, 0x00, 0x3c, 0x0d, 0x55, 0x7f, 0xff, 0xf0, 0x0d, 0x55, 0x5f, 0xff, 0xdf, 0xf5, 0x55, 0x7f, 0xdf, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0x55, 0x55, 0x55, 0x57, 0x35, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0xff, 0xff, 0x55, 0x55, 0x5f, 0xff, 0xff, 0x55, 0x55, 0x70, 0x00, 0x0f, 0x55, 0x55, 0x7f, 0xff, 0xf3, 0xfd, 0x55, 0xc0, 0x00, 0x0c, 0xc3, 0x55, 0xc0, 0x00, 0x03, 0xc3, 0x55, 0xc0, 0x00, 0x03, 0x03, 0x55, 0xf0, 0x03, 0x03, 0xc3, 0x55, 0xc3, 0xc0, 0x0f, 0xc3, 0x55, 0xc3, 0xc0, 0x3f, 0x0d, 0x55, 0x7f, 0xff, 0xfc, 0x35, 0x5d, 0xff, 0x3f, 0xf3, 0xd5, 0x5f, 0x00, 0x00, 0xfd, 0x55, 0x5f, 0xff, 0xff, 0x3d, 0x55, 0x55, 0xff, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xff, 0x55, 0x55, 0x7f, 0xff, 0xff, 0xd5, 0x55, 0xf0, 0x00, 0x03, 0xf5, 0x55, 0xcf, 0xff, 0xfc, 0xf5, 0x55, 0xf0, 0x00, 0x03, 0xff, 0x57, 0x0f, 0xc0, 0xfc, 0xf3, 0x57, 0x33, 0xc3, 0x3c, 0xdf, 0x57, 0x33, 0xc3, 0x3c, 0xd5, 0x57, 0x0f, 0xc0, 0xfc, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x35, 0x55, 0xff, 0xff, 0xfc, 0x0d, 0x57, 0xff, 0xcf, 0xf3, 0x0d, 0x5c, 0xff, 0xcf, 0xff, 0x0d, 0x57, 0x70, 0x00, 0x0c, 0x0d, 0x55, 0x7f, 0xff, 0xf7, 0xf5, 0x55, 0x57, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xf7, 0xfd, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xff, 0xf5, 0x55, 0x70, 0x00, 0xff, 0xff, 0x55, 0x7f, 0xfc, 0x03, 0xf3, 0x55, 0xf0, 0xff, 0xf0, 0xdf, 0x55, 0xf0, 0xf3, 0x0f, 0xd5, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xff, 0xf0, 0x33, 0x55, 0x57, 0x3f, 0xc0, 0xff, 0xd5, 0x57, 0xcf, 0xff, 0xfc, 0x35, 0x55, 0xff, 0x3f, 0xfc, 0x0d, 0x55, 0x7f, 0x3f, 0xf0, 0x0d, 0x55, 0x7f, 0x3f, 0xf0, 0x0d, 0x55, 0x70, 0x00, 0xf0, 0x0d, 0x55, 0x5f, 0xff, 0xdf, 0xf5, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x55, 0xf7, 0xd5, 0x55, 0x30, 0x1f, 0x01, 0x55, 0x40, 0x00, 0x00, 0x00, 0x15, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x11, 0x41, 0x50, 0x00, 0x00, 0x15, 0x55, 0x55, 0x54, 0x04, 0x10, 0x01, 0x55, 0x41, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa1, 0x14, 0x15, 0x54, 0x01, 0x11, 0x45, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa5, 0x54, 0x15, 0x54, 0x01, 0x55, 0x45, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa1, 0x14, 0x44, 0x11, 0x55, 0x55, 0x55, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x15, 0x40, 0x01, 0x55, 0x11, 0x56, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x95, 0x40, 0x01, 0x55, 0x55, 0x56, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x95, 0x55, 0x55, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x55, 0x50, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x01, 0x50, 0x55, 0x50, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x15, 0x55, 0x55, 0x54, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x02, 0x55, 0x55, 0x55, 0x00, 0x04, 0x00, 0x80, 0x28, 0x00, 0x00, 0xa0, 0x02, 0x01, 0x15, 0x55, 0x10, 0x04, 0x55, 0x80, 0x28, 0x00, 0x00, 0xa0, 0x02, 0x01, 0x15, 0x55, 0x01, 0x55, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x02, 0x55, 0x55, 0x55, 0x01, 0x01, 0x00, 0x80, 0xaa, 0xaa, 0xaa, 0xa8, 0x02, 0x00, 0x04, 0x01, 0x01, 0x55, 0x00, 0x82, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x04, 0x01, 0x00, 0x41, 0x00, 0x82, 0xaa, 0xaa, 0xaa, 0xaa, 0x02, 0x00, 0x04, 0x01, 0x55, 0x5a, 0xa5, 0x80, 0x95, 0x95, 0x80, 0x00, 0x02, 0x55, 0x54, 0x01, 0x00, 0x25, 0x58, 0x80, 0x95, 0x95, 0x85, 0x54, 0x0a, 0xaa, 0xa8, 0x01, 0x00, 0x26, 0x98, 0x80, 0x95, 0x95, 0x85, 0x54, 0x08, 0x00, 0x09, 0x55, 0x00, 0x25, 0x58, 0x80, 0x95, 0x95, 0xaa, 0xaa, 0x08, 0x88, 0x88, 0x00, 0x00, 0x20, 0x08, 0x95, 0x95, 0x95, 0x80, 0x02, 0x58, 0x88, 0x88, 0x00, 0xaa, 0xa0, 0x0a, 0x95, 0x95, 0x95, 0x80, 0x02, 0x58, 0x00, 0x0a, 0xaa, 0x04, 0x20, 0x08, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa9, 0x55, 0x58, 0x00, 0x00, 0x0a, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xaa, 0xa9, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0x42, 0x82, 0x20, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa6, 0x86, 0x26, 0x62, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x45, 0x86, 0x24, 0xa4, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xa4, 0xa1, 0x61, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x61, 0x40, 0xa2, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0xaa, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa9, 0x55, 0x69, 0x55, 0x6a, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x9a, 0xa9, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x59, 0x59, 0x6a, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x98, 0x49, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x95, 0x55, 0xaa, 0x95, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa5, 0x56, 0xaa, 0x40, 0x68, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa8, 0x0a, 0xa5, 0x55, 0x58, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa9, 0x5a, 0xa5, 0x55, 0x58, 0x00, 0x95, 0x5a, 0x69, 0xa5, 0x56, 0x02, 0xa5, 0x96, 0xa9, 0x69, 0x68, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x96, 0x5a, 0x69, 0xa5, 0x96, 0x54, 0x54, 0x54, 0x54, 0x54, 0x55, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x54, 0x54, 0x54, 0x54, 0x54, 0x55, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x30, 0x1f, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x15, 0x00, 0x00, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x55, 0x00, 0x01, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x40, 0x51, 0x55, 0x55, 0x15, 0x54, 0x00, 0x00, 0x15, 0x54, 0x55, 0x55, 0x45, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x40, 0x00, 0x44, 0x11, 0x10, 0x11, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x44, 0x04, 0x44, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x40, 0x00, 0x44, 0x15, 0x05, 0x41, 0x50, 0x05, 0x55, 0x55, 0x50, 0x05, 0x41, 0x50, 0x54, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x50, 0x40, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x50, 0x40, 0x01, 0x00, 0x01, 0x00, 0x17, 0xfc, 0x3f, 0xfc, 0x00, 0x43, 0xff, 0xc0, 0x01, 0x00, 0x01, 0x00, 0x1f, 0xf4, 0xff, 0xd4, 0x00, 0x4f, 0xfc, 0x40, 0x01, 0x55, 0x55, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x40, 0x01, 0x11, 0x11, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x40, 0x01, 0x00, 0x01, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xc0, 0x01, 0x05, 0x41, 0x00, 0xf0, 0xfc, 0x03, 0xff, 0xff, 0x00, 0x00, 0xc0, 0x01, 0x05, 0x41, 0x00, 0xf0, 0xf3, 0x0c, 0x71, 0xc7, 0x33, 0x30, 0xc0, 0xaa, 0xaa, 0xaa, 0xaa, 0xf0, 0xf3, 0x0d, 0x75, 0xd7, 0x33, 0x30, 0xea, 0x55, 0x55, 0x55, 0x55, 0xf0, 0xfc, 0x0d, 0x34, 0xd3, 0x33, 0x30, 0xd5, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x0d, 0x34, 0xc3, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x03, 0xff, 0xff, 0xaa, 0xaa, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 0xc0, 0x00, 0xfc, 0x0f, 0xc0, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x3a, 0xbf, 0xfa, 0xab, 0xff, 0xbf, 0xfb, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0xff, 0xff, 0xcf, 0xfc, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf0, 0x03, 0xff, 0x3f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xc0, 0x00, 0xfc, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x55, 0x51, 0x55, 0x55, 0x15, 0x54, 0x00, 0x00, 0x15, 0x10, 0x00, 0x00, 0x40, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x40, 0x11, 0x10, 0x11, 0x10, 0x04, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x40, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x15, 0x55, 0x55, 0x40, 0x15, 0x05, 0x41, 0x50, 0x05, 0x55, 0x55, 0x50, 0x00, 0x00, 0x00, 0x00, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf5, 0xff, 0xf0, 0x00, 0x0f, 0xff, 0x00, 0x50, 0x50, 0x50, 0x50, 0x3f, 0xc3, 0xff, 0x00, 0x14, 0x3f, 0xf4, 0x14, 0x55, 0x50, 0x55, 0x50, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x54, 0x55, 0x50, 0x55, 0x50, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x54, 0x55, 0x55, 0x55, 0x53, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x54, 0x40, 0x10, 0x40, 0x13, 0xc3, 0xf0, 0x0f, 0xff, 0xfc, 0x00, 0x03, 0x04, 0x50, 0x50, 0x50, 0x53, 0xc3, 0xcc, 0x31, 0xc7, 0x1c, 0xcc, 0xc3, 0x14, 0x40, 0x10, 0x40, 0x13, 0xc3, 0xcc, 0x35, 0xd7, 0x5c, 0xcc, 0xc3, 0x04, 0xaa, 0xaa, 0xaa, 0xab, 0xc3, 0xf0, 0x34, 0xd3, 0x4c, 0xcc, 0xc3, 0xaa, 0x55, 0x55, 0x55, 0x57, 0x00, 0x00, 0x34, 0xd3, 0x0c, 0x00, 0x03, 0x55, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x0f, 0xff, 0xfe, 0xaa, 0xab, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x3f, 0x00, 0x03, 0xf0, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xea, 0xff, 0xea, 0xaf, 0xfe, 0xff, 0xec, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf3, 0xff, 0xff, 0x3f, 0xf3, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x0f, 0xfc, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x03, 0xf0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xfd, 0x7d, 0x7f, 0x5d, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x5d, 0xd5, 0xd7, 0x75, 0xdd, 0xd5, 0x55, 0x55, 0x55, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x30, 0xcc, 0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0xc0, 0xff, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xc0, 0xc3, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0x3f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xfc, 0x3f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x03, 0xc0, 0x30, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0xf3, 0xff, 0xff, 0xcf, 0x00, 0x00, 0x0f, 0xf0, 0x70, 0x0f, 0x55, 0x55, 0xc3, 0x0c, 0x30, 0xc3, 0x55, 0x55, 0xf0, 0x0d, 0xc3, 0x30, 0xd5, 0xff, 0x7c, 0xcf, 0xf3, 0x3d, 0xff, 0x57, 0x0c, 0xc3, 0xc0, 0x3f, 0x5f, 0x03, 0x57, 0xcf, 0xf3, 0xd5, 0xc0, 0xf5, 0xfc, 0x03, 0xc0, 0x30, 0xdc, 0x0d, 0x5f, 0xff, 0xff, 0xf5, 0x70, 0x37, 0x0c, 0x03, 0x7f, 0xff, 0x5f, 0xf5, 0x5f, 0x55, 0x55, 0xf5, 0x5f, 0xf5, 0xff, 0xfd, 0x30, 0x1f, 0xa4, 0x00, 0xa4, 0x01, 0x90, 0x00, 0x64, 0x06, 0x40, 0x1a, 0x00, 0x16, 0xa9, 0x40, 0x09, 0x00, 0x40, 0x00, 0x10, 0x01, 0x00, 0x60, 0x01, 0x6a, 0x2a, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xaa, 0x00, 0xa5, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x01, 0x6a, 0x80, 0x00, 0x01, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x30, 0xc0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x00, 0x05, 0x94, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x15, 0x56, 0xa5, 0x55, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x15, 0x40, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x29, 0x50, 0x15, 0x68, 0x00, 0x40, 0x07, 0xf0, 0x0f, 0xc0, 0x10, 0x00, 0x0a, 0xa5, 0x6a, 0x80, 0x01, 0x00, 0x1f, 0xfc, 0x3f, 0xf0, 0x04, 0x00, 0x00, 0xaa, 0xa8, 0x00, 0x15, 0x00, 0x1f, 0xff, 0xff, 0xf0, 0x05, 0x40, 0x00, 0x0a, 0xa0, 0x00, 0x04, 0x00, 0x5c, 0x00, 0x00, 0x30, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xf0, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xc0, 0x33, 0x00, 0x00, 0xcc, 0x03, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x30, 0x03, 0xc0, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x0c, 0x30, 0x03, 0xc0, 0x0c, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x3c, 0x03, 0xc0, 0x3c, 0xff, 0xc0, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0xc3, 0xff, 0xff, 0xc3, 0x00, 0x00, 0x0f, 0xf0, 0x30, 0x0c, 0x00, 0x00, 0xcc, 0x30, 0x0c, 0x33, 0x00, 0x00, 0x30, 0x0c, 0xc3, 0x0f, 0x00, 0x00, 0x3f, 0x3f, 0xfc, 0xfc, 0x00, 0x00, 0xf0, 0xc3, 0xc0, 0x30, 0xc0, 0x00, 0x03, 0x3f, 0xfc, 0xc0, 0x00, 0x03, 0x0c, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0xfc, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x3f, 0xfc, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x30, 0x30, 0xc0, 0x00, 0x00, 0x3c, 0x3c, 0x00, 0x00, 0x03, 0x0c, 0x0c, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x0c, 0x30, 0x00, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xfd, 0x7d, 0x7f, 0x5d, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x5d, 0xd5, 0xd7, 0x75, 0xdd, 0xd5, 0x55, 0x55, 0x55, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x30, 0xcc, 0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0xc0, 0xff, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xc0, 0xc3, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x70, 0x0f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xf0, 0x0d, 0xc3, 0x30, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x0c, 0xc3, 0xc0, 0x3f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfc, 0x03, 0xc0, 0x30, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x0c, 0x03, 0x7f, 0xff, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xfd, 0x30, 0x1f, 0xa4, 0x00, 0xa4, 0x01, 0x90, 0x00, 0x64, 0x06, 0x40, 0x1a, 0x00, 0x16, 0xa9, 0x40, 0x09, 0x00, 0x40, 0x00, 0x10, 0x01, 0x00, 0x60, 0x01, 0x6a, 0x2a, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xaa, 0x00, 0xa5, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x01, 0x6a, 0x80, 0x00, 0x01, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x30, 0xc0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x00, 0x05, 0x94, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x15, 0x56, 0xa5, 0x55, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x15, 0x40, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x29, 0x50, 0x15, 0x68, 0x00, 0x40, 0x04, 0x00, 0x04, 0x00, 0x10, 0x00, 0x0a, 0xa5, 0x6a, 0x80, 0x01, 0x00, 0x14, 0x00, 0x05, 0x00, 0x04, 0x00, 0x00, 0xaa, 0xa8, 0x00, 0x15, 0x00, 0x15, 0x00, 0x15, 0x00, 0x05, 0x40, 0x00, 0x0a, 0xa0, 0x00, 0x04, 0x00, 0x54, 0x00, 0x05, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x30, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0c, 0xc3, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xc3, 0xc0, 0x30, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x30, 0x30, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x0c, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xfc, 0x00, 0xc3, 0x0f, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xc3, 0x00, 0xc3, 0x30, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xcc, 0xc3, 0x00, 0xff, 0x30, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xfc, 0x00, 0xc3, 0x30, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xc0, 0x00, 0xc3, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x3f, 0x0f, 0xcf, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0xcc, 0x0c, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0xcf, 0xcf, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0x0f, 0xcf, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x30, 0xcc, 0x33, 0x0c, 0xfc, 0xfc, 0x00, 0x00, 0xc0, 0x00, 0x00, 0xc3, 0x30, 0xcf, 0x33, 0xcc, 0xc0, 0xc3, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc3, 0x30, 0xcc, 0xf3, 0x3c, 0xfc, 0xc3, 0x00, 0x00, 0xfc, 0x00, 0x00, 0xfc, 0x30, 0xcc, 0x33, 0x0c, 0xc0, 0xfc, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc3, 0x0f, 0x0c, 0x33, 0x0c, 0xfc, 0xc3, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x1f, 0x05, 0x55, 0x55, 0x55, 0x55, 0x55, 0x54, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x05, 0x54, 0x55, 0x45, 0x51, 0x10, 0x00, 0x04, 0x04, 0x55, 0x44, 0x51, 0x11, 0x55, 0x44, 0x04, 0x44, 0x44, 0x51, 0x11, 0x00, 0x44, 0x04, 0x44, 0x44, 0x51, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x00, 0x00, 0x00, 0x05, 0x41, 0x10, 0x00, 0x00, 0x00, 0x00, 0x04, 0x41, 0x10, 0x00, 0x00, 0x10, 0x55, 0x05, 0x41, 0x10, 0x54, 0x00, 0x55, 0x45, 0x10, 0x11, 0x11, 0x01, 0x40, 0x55, 0x54, 0x10, 0x11, 0x11, 0x00, 0x10, 0x55, 0x54, 0x15, 0x51, 0x11, 0x41, 0x11, 0x51, 0x10, 0x04, 0x41, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x50, 0x50, 0x00, 0x00, 0x10, 0x01, 0x10, 0x55, 0x50, 0x55, 0x00, 0x55, 0x01, 0x10, 0x44, 0x51, 0x00, 0x51, 0x00, 0x41, 0x10, 0x40, 0x11, 0x04, 0x41, 0x11, 0x41, 0x10, 0x15, 0x41, 0x00, 0x41, 0x00, 0x41, 0x10, 0x10, 0x41, 0x00, 0x40, 0x41, 0x01, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x55, 0x55, 0x55, 0x55, 0x55, 0x41, 0x10, 0x40, 0x00, 0x00, 0x00, 0x00, 0x41, 0x10, 0x55, 0x55, 0x55, 0x55, 0x55, 0x41, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x15, 0x50, 0x00, 0x00, 0x00, 0x01, 0x55, 0x12, 0x0c, 0x57, 0xf5, 0x7d, 0x55, 0x50, 0x5f, 0xfd, 0xff, 0x55, 0x50, 0x5f, 0xff, 0xff, 0x55, 0x50, 0x5f, 0xff, 0xff, 0xd5, 0x50, 0x7c, 0x00, 0x00, 0xd5, 0x50, 0x70, 0x0f, 0xc3, 0xd5, 0x50, 0x70, 0x33, 0xc3, 0xd5, 0x50, 0x70, 0x33, 0xc3, 0xd5, 0x50, 0x70, 0x0f, 0xc3, 0xd5, 0x50, 0x5c, 0x00, 0x0f, 0x55, 0x50, 0x57, 0xff, 0xfd, 0x55, 0x50, 0x5c, 0x3c, 0x33, 0x55, 0x50, 0x12, 0x0c, 0x55, 0xfd, 0x5f, 0x55, 0x50, 0x57, 0xff, 0x7f, 0xd5, 0x50, 0x57, 0xff, 0xff, 0xd5, 0x50, 0x57, 0xff, 0xff, 0xf5, 0x50, 0x5f, 0x00, 0x00, 0x35, 0x50, 0x5c, 0x03, 0xc0, 0x35, 0x50, 0x5c, 0x0c, 0x30, 0xf5, 0x50, 0x5c, 0x00, 0x00, 0x35, 0x50, 0x5c, 0x0c, 0x0f, 0xf5, 0x50, 0x57, 0x33, 0x0f, 0xd5, 0x50, 0x55, 0xf3, 0xff, 0x35, 0x50, 0x55, 0xc3, 0xc3, 0xf5, 0x50, 0x12, 0x0c, 0x5f, 0xd5, 0x7f, 0xff, 0xf0, 0x7f, 0xf5, 0xff, 0x00, 0x30, 0x7f, 0xff, 0xff, 0x00, 0x30, 0x7f, 0xff, 0xff, 0x00, 0x30, 0x70, 0x00, 0x03, 0x00, 0x30, 0xc3, 0xf0, 0x3f, 0x00, 0x30, 0xcc, 0xf0, 0xcf, 0x00, 0x30, 0xcc, 0xf0, 0xcf, 0x00, 0x30, 0xc3, 0xf0, 0x3f, 0xff, 0xf0, 0x70, 0x0f, 0x00, 0xcd, 0x50, 0x5f, 0xff, 0xff, 0x35, 0x50, 0x70, 0x30, 0x3c, 0xd5, 0x50, 0x12, 0x0c, 0x55, 0xfd, 0x57, 0xd5, 0x50, 0x57, 0xff, 0xdf, 0xf5, 0x50, 0x57, 0xff, 0xff, 0xfd, 0x50, 0x55, 0xff, 0xff, 0xfd, 0x50, 0x57, 0xc0, 0x00, 0x0d, 0x50, 0x57, 0x00, 0x00, 0x0d, 0x50, 0x57, 0x00, 0x00, 0x0d, 0x50, 0x57, 0x0f, 0xf0, 0x0d, 0x50, 0x57, 0x00, 0x00, 0xcd, 0x50, 0x55, 0xc0, 0x03, 0x35, 0x50, 0x55, 0x7f, 0xff, 0xd5, 0x50, 0x55, 0xc3, 0xc3, 0xd5, 0x50, 0x12, 0x0c, 0x57, 0xf5, 0x5f, 0xd5, 0x50, 0x5f, 0xfd, 0x7f, 0xf5, 0x50, 0x5f, 0xff, 0xff, 0xf5, 0x50, 0x5f, 0xff, 0xff, 0xf5, 0x50, 0x5c, 0x00, 0x00, 0x35, 0x50, 0x70, 0x00, 0x00, 0x0d, 0x50, 0x70, 0x30, 0x0c, 0x0d, 0x50, 0x70, 0xc0, 0x03, 0x0d, 0x50, 0x70, 0x03, 0xc0, 0x0d, 0x50, 0x5c, 0x0f, 0xf0, 0x35, 0x50, 0x57, 0xff, 0xff, 0xd5, 0x50, 0x55, 0xcc, 0x33, 0x55, 0x50, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfa, 0xaa, 0xab, 0xc0, 0xff, 0xe5, 0x55, 0x5a, 0xc0, 0xff, 0xe5, 0x55, 0x5a, 0xc0, 0xff, 0x95, 0x55, 0x66, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0xaa, 0xaa, 0xab, 0xc0, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfe, 0xaa, 0xaa, 0xc0, 0xff, 0xfe, 0x55, 0x56, 0xc0, 0xff, 0xfe, 0x55, 0x56, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xea, 0xaa, 0xaa, 0xc0, 0xff, 0xea, 0xaa, 0xaa, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0xaa, 0xaa, 0xab, 0xc0, 0x08, 0x08, 0x7f, 0xf5, 0xff, 0xfd, 0xc3, 0x0d, 0xff, 0xfd, 0xff, 0xfd, 0xfc, 0xfd, 0x7f, 0xf5, 0x77, 0x75, 0x10, 0x03, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xc0, 0x03, 0x03, 0xff, 0xff, 0xff, 0xff, 0x10, 0x03, 0x55, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x03, 0x55, 0x55, 0xff, 0xff, 0x55, 0x08, 0x08, 0x55, 0x75, 0x55, 0x75, 0x55, 0x75, 0x5f, 0x75, 0x70, 0xf5, 0x70, 0xd5, 0x5f, 0x55, 0x55, 0x55, 0x08, 0x08, 0x55, 0x75, 0x55, 0x75, 0x55, 0x75, 0x5f, 0x75, 0x7f, 0xf5, 0x7f, 0xd5, 0x5f, 0x55, 0x55, 0x55, 0x08, 0x08, 0x55, 0xd5, 0x55, 0xf5, 0x55, 0xfd, 0x7d, 0xdd, 0xff, 0xd5, 0xff, 0x55, 0x7d, 0x55, 0x55, 0x55, 0x08, 0x08, 0x5f, 0xfd, 0x5d, 0x5d, 0x5d, 0x5d, 0x5d, 0x5d, 0xfd, 0xfd, 0xfd, 0xfd, 0xf5, 0xf5, 0x55, 0x55, 0x01, 0x01, 0x00, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x7f, 0xfd, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x5f, 0xfd, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x7f, 0xfd, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x5f, 0xfd, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x7f, 0xfd, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0x03, 0x5f, 0xfd, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x08, 0x08, 0x50, 0x05, 0x43, 0xc1, 0x00, 0x00, 0x30, 0xcc, 0x33, 0x0c, 0x00, 0x00, 0x43, 0xc1, 0x50, 0x05, 0x08, 0x08, 0xc0, 0x03, 0x33, 0xcc, 0x00, 0x30, 0x33, 0x0c, 0x30, 0xcc, 0x0c, 0x00, 0x33, 0xcc, 0xc0, 0x03, 0x08, 0x08, 0x57, 0xd5, 0x5c, 0x35, 0x5c, 0x35, 0xdc, 0x37, 0xd7, 0xd7, 0xdf, 0xf7, 0xfd, 0x7f, 0xf7, 0xdf, 0x04, 0x1f, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x02, 0x05, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0x06, 0x20, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0x20, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf7, 0xff, 0x5f, 0x5f, 0xd7, 0xff, 0x75, 0x5d, 0x55, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x57, 0xd5, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x55, 0x75, 0x75, 0x7f, 0xdf, 0xd5, 0x75, 0x75, 0x55, 0x75, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x55, 0x5f, 0xd5, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x08, 0x7f, 0x5f, 0x57, 0xd7, 0x57, 0xd5, 0x75, 0xdd, 0x77, 0x57, 0xdf, 0x75, 0xdd, 0x77, 0x57, 0xd7, 0x75, 0xdf, 0xf7, 0x55, 0x7d, 0x5f, 0x5d, 0x77, 0xf7, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x0c, 0x7f, 0x5f, 0x5d, 0x5d, 0xfd, 0xd5, 0x75, 0xdf, 0x7d, 0xd5, 0xdf, 0x75, 0xdf, 0xfd, 0xfd, 0xd7, 0x7f, 0xdd, 0xdd, 0xd5, 0x7f, 0x75, 0xdd, 0x5d, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7d, 0x75, 0x77, 0xf7, 0xf5, 0xd7, 0x75, 0x77, 0x57, 0x5d, 0xd7, 0x5d, 0xd7, 0xf7, 0x5d, 0xd7, 0x5d, 0xd7, 0x57, 0xf5, 0x7d, 0x57, 0x57, 0xf7, 0x5d, 0x55, 0x55, 0x55, 0x55, 0x55, 0x20, 0x0c, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xff, 0x55, 0xc3, 0x7d, 0x55, 0x55, 0x55, 0x70, 0x00, 0xd5, 0x70, 0xff, 0x55, 0x55, 0x55, 0xc0, 0x00, 0x35, 0x7c, 0x3f, 0xd5, 0x55, 0x57, 0x00, 0x03, 0x0d, 0x5f, 0xff, 0xff, 0xff, 0xfc, 0x03, 0x00, 0x0d, 0x70, 0x00, 0x03, 0xc0, 0x00, 0x00, 0x3f, 0xfd, 0x7f, 0xff, 0xfc, 0x30, 0x00, 0x00, 0xc0, 0x03, 0xc0, 0x00, 0x03, 0x30, 0x00, 0x03, 0x0f, 0xfc, 0xc0, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc0, 0x03, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x01, 0x01, 0x00, 0x10, 0x10, 0x55, 0x7d, 0x55, 0xf5, 0x55, 0xc3, 0x57, 0x0d, 0x55, 0xc0, 0xdc, 0x0d, 0x55, 0x70, 0xdc, 0x3d, 0x55, 0x5c, 0x30, 0x35, 0x55, 0x70, 0x00, 0xd5, 0x55, 0xc3, 0xfc, 0xd5, 0x55, 0xcf, 0xff, 0x35, 0x57, 0x0f, 0xff, 0x35, 0x57, 0x00, 0xfc, 0x35, 0x57, 0xc0 }; void EXTI0_IRQHandler() { //GPIO_SetBits(GPIOB, GPIO_Pin_14); //if (EXTI_GetITStatus(EXTI_Line0) != RESET) { if(started){ if(read){ read = 2; } read = 1; //GPIO_SetBits(GPIOB, GPIO_Pin_14); a = 0; acount = 0; // as[loops++] = a; //as[loops++] = acount; as[loops++] = hit; hit = 0; } EXTI_ClearITPendingBit(EXTI_Line0); //} //GPIO_ResetBits(GPIOB, GPIO_Pin_14); } void EXTI1_IRQHandler() { //hit++; //if (EXTI_GetITStatus(EXTI_Line1) != RESET) { if(read){ // a = a << 1; // GPIO_SetBits(GPIOB, GPIO_Pin_15); // a = a | (GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_8)); (GPIOD->IDR & GPIO_Pin_8) ? (a = ((a << 1)|1) ) : (a <<= 1); //GPIO_ResetBits(GPIOB, GPIO_Pin_15); acount++; // if(acount > 32){ // GPIO_SetBits(GPIOD, GPIO_Pin_15); // } if (acount ==32){ read = 0; //if((a & 0xff000000) != 0x03000000){ // GPIO_SetBits(GPIOD, GPIO_Pin_14); // } as[loops++] = a; a = 0xffffff & a; // index = (loops % 800) / 100; /* if(loops > 100){ loops = 0; index++; if (index > 7) index = 0; } for(i = 0; i < 105; i++){ v[0xe0 + i] = vs[index][i]; }*/ val = v[a++]; // as[loops++] = val; // as[loops++] = val; c = 0x80; if(val&c){ GPIO_SetBits(GPIOD, GPIO_Pin_4); }else{ GPIO_ResetBits(GPIOD, GPIO_Pin_4); } c = c >> 1; started = 1; } }else{ if(val&c){ GPIOD->BSRRL = GPIO_Pin_4; }else{ GPIOD->BSRRH = GPIO_Pin_4; } c = c >> 1; if(c==0){ c = 0x80; val = v[a++]; // as[loops++] = val; } //as[loops++] = 2; } EXTI_ClearITPendingBit(EXTI_Line1); //} } /** * @brief Main program. * @param None * @retval None */ uint32_t getAddress(); int main(void) { RCC_ClocksTypeDef RCC_Clocks; int l = 0; /* Initialize LEDs and User_Button on STM32F4-Discovery --------------------*/ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE); RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE); /* SysTick end of count event each 10ms */ // RCC_GetClocksFreq(&RCC_Clocks); // SysTick_Config(RCC_Clocks.HCLK_Frequency / 100); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_8 ; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_Init(GPIOD, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; GPIO_Init(GPIOD, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_13| GPIO_Pin_14| GPIO_Pin_15; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_Init(GPIOD, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14 | GPIO_Pin_15; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_Init(GPIOB, &GPIO_InitStructure); EXTILine0_Config(); GPIO_SetBits(GPIOD, GPIO_Pin_12); // GPIO_SetBits(GPIOD, GPIO_Pin_14); // GPIO_SetBits(GPIOD, GPIO_Pin_12); // GPIO_ResetBits(GPIOB, GPIO_Pin_14); //GPIO_SetBits(GPIOB, GPIO_Pin_14); vs[0] = v1; vs[1] = v2; vs[2] = v3; vs[3] = v2; vs[4] = v4; vs[5] = v5; vs[6] = v6; vs[7] = v7; while(1){ // GPIO_SetBits(GPIOB, GPIO_Pin_14); // GPIO_ResetBits(GPIOB, GPIO_Pin_14); // printf("here"); /* uint32_t a, j; uint8_t t, c, i; flag = 1; if(started) while(GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_0)){ l++; } a = getAddress(); // if(a < 0 || a > 200){ // GPIO_SetBits(GPIOD, GPIO_Pin_14); //} started = 1; while(flag){ t = v[a]; c = 0x80; for( i = 0; (i < 8); i++){ // if(a > 200){ // loops++; // } if(t&c){ GPIO_SetBits(GPIOD, GPIO_Pin_4); }else{ GPIO_ResetBits(GPIOD, GPIO_Pin_4); } // if(!flag) // break; c = c >> 1; // q = ; // while((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)== Bit_RESET) && (GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_9) == Bit_RESET)){} // while(GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11) && (GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_9) == Bit_RESET) ){} // l = 0; //while((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)== Bit_SET) && flag ){} // as[loops++] = q; // q = 0; while((!GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)) && flag ){ } // if((l++ % 100) == 99){ // if((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_9) != Bit_RESET)) // break; // } // as[loops++] = q; // q = 0; // l = 0; while(GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)){ //q++; } //as[loops++] = q; // if((l++ % 100) == 99){ // if((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_9) != Bit_RESET)) // break; // } // // for(j=0; j < 1000000; j++){ // } // } // if(flag) // loop++; } a++; } // as[loops++] = a; */ } } uint32_t getAddress(){ uint32_t a, i; a = 0; for(i = 0; i < 32; i++){ while(GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)== Bit_RESET){} //a++; a = a << 1; a = a + (GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_10)? 1:0); // if(i!=31) while(GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)){} } if((a & 0xff000000) != 0x03000000){ // GPIO_SetBits(GPIOD, GPIO_Pin_15); } // as[loops++] = a; return a & 0x00ffffff; } /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ ================================================ FILE: demos/nataliemain.c ================================================ /** ****************************************************************************** * @file main.c * @author MCD Application Team * @version V1.0.0 * @date 19-September-2011 * @brief Main program body ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * *

© COPYRIGHT 2011 STMicroelectronics

****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ //#include "main.h" #include "stm32f4_discovery.h" //#include "stm32f4xx_it.c" uint8_t flag; //#include /** @addtogroup STM32F4-Discovery_Demo * @{ */ int i; /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ //#define CLK GPIO_Pin_11 //#define ADDRESS GPIO_Pin_10 //#define E GPIO_Pin_9 EXTI_InitTypeDef EXTI_InitStructure; /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ //uint32_t a = 0; //int i; int index; int started = 0; /* Private function prototypes -----------------------------------------------*/ GPIO_InitTypeDef GPIO_InitStructure; /* Private functions ---------------------------------------------------------*/ void EXTILine0_Config(void) { GPIO_InitTypeDef GPIO_InitStructure; NVIC_InitTypeDef NVIC_InitStructure; /* Enable GPIOA clock */ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); /* Enable SYSCFG clock */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); /* Configure PA0 pin as input floating */ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; GPIO_Init(GPIOA, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1; GPIO_Init(GPIOA, &GPIO_InitStructure); /* Connect EXTI Line0 to PA0 pin */ SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOA, EXTI_PinSource0); /* Configure EXTI Line0 */ EXTI_InitStructure.EXTI_Line = EXTI_Line0; EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; EXTI_InitStructure.EXTI_LineCmd = ENABLE; EXTI_Init(&EXTI_InitStructure); /* Enable and set EXTI Line0 Interrupt to the lowest priority */ NVIC_InitStructure.NVIC_IRQChannel = EXTI0_IRQn; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x01; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x01; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOA, EXTI_PinSource1); /* Configure EXTI Line0 */ EXTI_InitStructure.EXTI_Line = EXTI_Line1; EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; EXTI_InitStructure.EXTI_LineCmd = ENABLE; EXTI_Init(&EXTI_InitStructure); /* Enable and set EXTI Line0 Interrupt to the lowest priority */ NVIC_InitStructure.NVIC_IRQChannel = EXTI1_IRQn; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x02; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x01; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); } int loops = 0; int hit = 0; int q; int as[2000]; int read = 1; uint32_t a = 0; int acount = 0; uint8_t val; uint8_t c; uint8_t *vs[8]; uint8_t v1[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0x29, 0xc0, 0xff, 0xca, 0x9f, 0x28, 0xc0, 0xff, 0xca, 0xa7, 0x67, 0xc0, 0xff, 0xda, 0xa8, 0xa7, 0xc0, 0xff, 0xda, 0xaa, 0xa3, 0xc0, 0xff, 0x2a, 0xaa, 0x9f, 0xc0, 0xff, 0x69, 0xaa, 0x8f, 0xc0, 0xff, 0x65, 0xaa, 0x8f, 0xc0, 0xfc, 0xa4, 0xaa, 0x7f, 0xc0, 0xfd, 0xa0, 0xaa, 0x7f, 0xc0, 0xf2, 0xa3, 0x6a, 0x7f, 0xc0, 0xf2, 0x9f, 0x6a, 0x3f, 0xc0, 0xfa, 0x8f, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0}; uint8_t v2[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0x6a, 0x7f, 0xc0, 0xff, 0xfd, 0xaa, 0x3f, 0xc0, 0xff, 0xf2, 0xaa, 0x3f, 0xc0, 0xff, 0xf6, 0xa9, 0xff, 0xc0, 0xff, 0xda, 0xa9, 0xff, 0xc0, 0xff, 0x2a, 0xa9, 0xff, 0xc0, 0xff, 0x6a, 0xa8, 0xff, 0xc0, 0xfc, 0xa4, 0xa8, 0xff, 0xc0, 0xfd, 0xa0, 0xa7, 0xff, 0xc0, 0xf2, 0x91, 0xa7, 0xff, 0xc0, 0xfa, 0x82, 0xa7, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0}; uint8_t v3[] = { 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfa, 0xaa, 0xab, 0xc0, 0xff, 0xfa, 0xaa, 0xaf, 0xc0, 0xff, 0xfa, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xea, 0xbf, 0xff, 0xc0, 0xff, 0xea, 0xff, 0xff, 0xc0, 0xff, 0xea, 0xff, 0xff, 0xc0, 0xff, 0xaa, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0}; uint8_t v4[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xaa, 0xff, 0xc0, 0xff, 0xff, 0xab, 0xff, 0xc0, 0xff, 0xfe, 0xab, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xff, 0xff, 0xc0, 0xff, 0xea, 0xff, 0xff, 0xc0, 0xff, 0xeb, 0xff, 0xff, 0xc0, 0xff, 0xeb, 0xff, 0xff, 0xc0, 0xff, 0xab, 0xea, 0xff, 0xc0, 0xff, 0xaa, 0xaa, 0xff, 0xc0, 0xff, 0xaa, 0xaa, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0 }; uint8_t v5[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xea, 0xff, 0xc0, 0xff, 0xff, 0xea, 0xff, 0xc0, 0xff, 0xff, 0xeb, 0xff, 0xc0, 0xff, 0xff, 0xeb, 0xff, 0xc0, 0xff, 0xff, 0xab, 0xff, 0xc0, 0xff, 0xff, 0xaf, 0xff, 0xc0, 0xff, 0xff, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xbf, 0xff, 0xc0, 0xff, 0xfe, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0}; uint8_t v6[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xaa, 0xaa, 0xc0, 0xff, 0xff, 0xaa, 0xaa, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfa, 0xaa, 0xff, 0xc0, 0xff, 0xfa, 0xab, 0xff, 0xc0, 0xff, 0xfa, 0xff, 0xff, 0xc0, 0xff, 0xea, 0xff, 0xff, 0xc0, 0xff, 0xea, 0xff, 0xff, 0xc0, 0xff, 0xea, 0xab, 0xff, 0xc0, 0xff, 0xaa, 0xab, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0}; uint8_t v7[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xeb, 0xff, 0xc0, 0xff, 0xff, 0xab, 0xff, 0xc0, 0xff, 0xfe, 0xab, 0xff, 0xc0, 0xfe, 0xaa, 0xaa, 0xab, 0xc0, 0xff, 0xaa, 0xaa, 0xbf, 0xc0, 0xff, 0xea, 0xab, 0xff, 0xc0, 0xff, 0xea, 0xab, 0xff, 0xc0, 0xff, 0xaa, 0xab, 0xff, 0xc0, 0xff, 0xaf, 0xab, 0xff, 0xc0, 0xfe, 0xff, 0xeb, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0}; uint8_t v[] = { 0x0a, 0xaa, 0x55, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0-f 0x00, 0xaa, 0x55, 0x03, 0x03, 0x03, 0x00, 0x00, 0x10, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //10-f 0x40, 0x00, 0x00, 0xc4, 0x00, 0x00, 0xdc, 0x00, 0x00, 0x0f, 0x01, 0x00, 0x91, 0x01, 0x00, 0x0d, //20 0x02, 0x00, 0x89, 0x02, 0x00, 0xd1, 0x02, 0x00, 0x1f, 0x06, 0x00, 0x67, 0x0f, 0x00, 0x67, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //40 0x41, 0x12, 0x00, 0xa7, 0x12, 0x00, 0x0d, 0x13, 0x00, 0x73, 0x13, 0x00, 0xd9, 0x13, 0x00, 0x3f, 0x14, 0x00, 0xa5, 0x14, 0x00, 0x0b, 0x15, 0x00, 0x71, 0x15, 0x00, 0xd7, 0x15, 0x00, 0x3d, 0x16, 0x00, 0xa3, 0x16, 0x00, 0x09, 0x17, 0x00, 0x6f, 0x17, 0x00, 0xd5, 0x17, 0x00, 0x3b, 0x18, 0x00, 0xa1, 0x18, 0x00, 0x07, 0x19, 0x00, 0x6d, 0x19, 0x00, 0xd3, 0x19, 0x00, 0x39, 0x1a, 0x00, 0x9f, //80 0x1a, 0x00, 0x05, 0x1b, 0x00, 0x6b, 0x1b, 0x00, 0xd1, 0x1b, 0x00, 0x37, 0x1c, 0x00, 0x9d, 0x1c, //90 0x00, 0x13, 0x1e, 0x00, 0x89, 0x1f, 0x00, 0xff, 0x20, 0x00, 0x75, 0x22, 0x00, 0xeb, 0x23, 0x00, 0x61, 0x25, 0x00, 0xd7, 0x26, 0x00, 0x4d, 0x28, 0x00, 0xeb, 0x28, 0x00, 0x89, 0x29, 0x00, 0x64, //b0 0x2a, 0x00, 0xa2, 0x2a, 0x00, 0xe0, 0x2a, 0x00, 0x1e, 0x2b, 0x00, 0x5c, 0x2b, 0x00, 0xce, 0x00, //c0 0x00, 0xce, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x44, 0x12, 0x34, 0x11, 0x15, //d0 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xaa, 0xa, 0xa0, 0x0, 0x0, 0x2a, 0x81, 0x80, 0x0, 0x0, 0x1a, 0x91, 0x80, 0x0, 0x0, 0x15, 0xa5, 0x80, 0x0, 0x0, 0x14, 0xa9, 0x80, 0x0, 0x0, 0x14, 0x2a, 0x80, 0x0, 0x0, 0x28, 0xa, 0x80, 0x0, 0x0, 0xaa, 0x2, 0x80, 0x0, 0x0, 0x0, 0x0, 0xa, 0xa9, 0x0, 0x0, 0x0, 0x1a, 0x19, 0x0, 0x0, 0x0, 0x2a, 0x9, 0x0, 0x0, 0x0, 0x1a, 0xa4, 0x0, 0x0, 0x0, 0x2, 0xa9, 0x0, 0x0, 0x0, 0x24, 0x2a, 0x0, 0x0, 0x0, 0x28, 0x29, 0x0, 0x0, 0x0, 0x2a, 0xa8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, // 0x0, 0xcf, 0xff, 0x0, 0x0, 0x0, 0x0, 0xcf, 0xff, 0x0, 0x0, 0x0, 0x0, // 0xcf, 0xff, 0x0, 0x0, 0xc, 0xff, 0xff, 0xff, 0x0, 0x0, 0xff, 0xff, // 0xff, 0xff, 0x0, 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, //0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, // 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, // 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, 0x0, 0x0, 0x0, 0xC0, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0x00, 0x00, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFA, 0xAA, 0xAB, 0xC0, 0xFF, 0xE5, 0x55, 0x5A, 0xC0, 0x00, 0xE5, 0x55, 0x5A, 0xC0, 0xFF, 0x95, 0x55, 0x66, 0xC0, 0xFF, 0xAA, 0xAA, 0xA6, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x8A, 0x28, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x8A, 0x28, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0xAA, 0xAA, 0xAB, 0xC0, 0x11, 0x15, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0x00, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFA, 0xAA, 0xAB, 0xC0, 0xFF, 0xE5, 0x55, 0x5A, 0xC0, 0xFF, 0xE5, 0x55, 0x5A, 0xC0, 0xFF, 0x95, 0x55, 0x66, 0xC0, 0xFF, 0xAA, 0xAA, 0xA6, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x8A, 0x28, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x8A, 0x28, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0xAA, 0xAA, 0xAB, 0xC0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};// 0x70, 0x2c, 0x00, 0x82, 0x2c, 0x00, 0x90, 0x2c, 0x00, 0x9e, 0x2c, 0x00, 0xb0, 0x2c, 0x00, 0xc2, 0x2c, 0x00, 0xd4, 0x2c, 0x00, 0xe6, 0x2c, 0x00, 0xe9, 0x2c, 0x00, 0x1b, 0x2d, 0x00, 0x4d, 0x2d, 0x00, 0x7f, 0x2d, 0x00, 0xb1, 0x2d, 0x00, 0xe3, 0x2d, 0x00, 0x15, 0x2e, 0x00, 0x27, 0x2e, 0x00, 0x39, 0x2e, 0x00, 0x4b, 0x2e, 0x00, 0x6c, 0x2e, 0x00, 0x73, 0x2e, 0x00, 0xb5, 0x2e, 0x00, 0xf7, 0x2e, 0x00, 0x21, 0x2f, 0x00, 0x5f, 0x2f, 0x00, 0xc1, 0x2f, 0x00, 0x02, 0x00, 0x06, 0x03, 0x04, 0x09, 0x0a, 0x05, 0x08, 0x07, 0x00, 0x00, 0x58, 0x00, 0x00, 0x32, 0x00, 0x00, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x10, 0x00, 0x00, 0x08, 0x00, 0x00, 0x50, 0x04, 0x00, 0x30, 0x02, 0x00, 0x20, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00, 0x50, 0x08, 0x00, 0x50, 0x11, 0x00, 0x00, 0x00, 0x28, 0x00, 0x40, 0x15, 0x00, 0x60, 0x12, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x45, 0x00, 0x00, 0x35, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x22, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00, 0x22, 0x00, 0x00, 0x13, 0x00, 0x01, 0x00, 0x02, 0x00, 0x50, 0x01, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x04, 0xff, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x02, 0xff, 0x01, 0x01, 0x00, 0x1e, 0x01, 0x00, 0x03, 0xff, 0x01, 0x01, 0x00, 0x2d, 0x01, 0x00, 0x04, 0xfe, 0x01, 0x01, 0x00, 0x3c, 0x01, 0x00, 0x05, 0xfe, 0x01, 0x01, 0x00, 0x4b, 0x02, 0x00, 0x06, 0xfe, 0x02, 0x02, 0x00, 0x5a, 0x02, 0x00, 0x07, 0xfd, 0x02, 0x02, 0x00, 0x63, 0x02, 0x00, 0x08, 0xfd, 0x02, 0x02, 0x00, 0x64, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0x00, 0x02, 0x04, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x02, 0xff, 0x01, 0x01, 0x00, 0x0f, 0x01, 0x00, 0x03, 0xff, 0x01, 0x01, 0x00, 0x19, 0x01, 0x00, 0x04, 0xfe, 0x01, 0x01, 0x00, 0x23, 0x01, 0x00, 0x05, 0xfe, 0x01, 0x02, 0x00, 0x2d, 0x02, 0x00, 0x06, 0xfe, 0x02, 0x02, 0x00, 0x37, 0x02, 0x00, 0x07, 0xfd, 0x02, 0x02, 0x00, 0x40, 0x02, 0x00, 0x08, 0xfd, 0x02, 0x02, 0x00, 0x41, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xc4, 0x2f, 0x00, 0xff, 0xff, 0xff, 0x06, 0x30, 0x00, 0x48, 0x30, 0x00, 0x8a, 0x30, 0x00, 0xcc, 0x30, 0x00, 0x0e, 0x31, 0x00, 0x50, 0x31, 0x00, 0x92, 0x31, 0x00, 0xd4, 0x31, 0x00, 0x16, 0x32, 0x00, 0xff, 0xff, 0xff, 0x58, 0x32, 0x00, 0xff, 0xff, 0xff, 0xba, 0x32, 0x00, 0x1c, 0x33, 0x00, 0x7e, 0x33, 0x00, 0xe0, 0x33, 0x00, 0x42, 0x34, 0x00, 0xa4, 0x34, 0x00, 0x06, 0x35, 0x00, 0x68, 0x35, 0x00, 0xca, 0x35, 0x00, 0xff, 0xff, 0xff, 0x2c, 0x36, 0x00, 0x3e, 0x36, 0x00, 0x80, 0x36, 0x00, 0xc2, 0x36, 0x00, 0x04, 0x37, 0x00, 0x46, 0x37, 0x00, 0x88, 0x37, 0x00, 0xca, 0x37, 0x00, 0x24, 0x38, 0x00, 0x9d, 0x38, 0x00, 0xf9, 0x38, 0x00, 0x7d, 0x39, 0x00, 0xd7, 0x39, 0x00, 0x50, 0x3a, 0x00, 0xac, 0x3a, 0x00, 0x30, 0x3b, 0x00, 0x72, 0x3b, 0x00, 0xb4, 0x3b, 0x00, 0xf6, 0x3b, 0x00, 0x38, 0x3c, 0x00, 0x7a, 0x3c, 0x00, 0xbc, 0x3c, 0x00, 0xfe, 0x3c, 0x00, 0x40, 0x3d, 0x00, 0x3a, 0x3e, 0x00, 0x34, 0x3f, 0x00, 0x2e, 0x40, 0x00, 0x28, 0x41, 0x00, 0x22, 0x42, 0x00, 0x98, 0x43, 0x00, 0xea, 0x43, 0x00, 0x3c, 0x44, 0x00, 0x8e, 0x44, 0x00, 0xe0, 0x44, 0x00, 0x32, 0x45, 0x00, 0x84, 0x45, 0x00, 0x7e, 0x46, 0x00, 0x78, 0x47, 0x00, 0xba, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0x76, 0x48, 0x00, 0xf0, 0x48, 0x00, 0x6a, 0x49, 0x00, 0xe4, 0x49, 0x00, 0x5e, 0x4a, 0x00, 0xd8, 0x4a, 0x00, 0x52, 0x4b, 0x00, 0xcc, 0x4b, 0x00, 0x46, 0x4c, 0x00, 0xc0, 0x4c, 0x00, 0x3a, 0x4d, 0x00, 0xb4, 0x4d, 0x00, 0x2e, 0x4e, 0x00, 0xa8, 0x4e, 0x00, 0x22, 0x4f, 0x00, 0x9c, 0x4f, 0x00, 0x16, 0x50, 0x00, 0x90, 0x50, 0x00, 0x0a, 0x51, 0x00, 0x84, 0x51, 0x00, 0xfe, 0x51, 0x00, 0x78, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0x6c, 0x53, 0x00, 0xe6, 0x53, 0x00, 0x60, 0x54, 0x00, 0xda, 0x54, 0x00, 0x54, 0x55, 0x00, 0xce, 0x55, 0x00, 0x48, 0x56, 0x00, 0xc2, 0x56, 0x00, 0x3c, 0x57, 0x00, 0xb6, 0x57, 0x00, 0x30, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0x24, 0x59, 0x00, 0x9e, 0x59, 0x00, 0x18, 0x5a, 0x00, 0x92, 0x5a, 0x00, 0x0c, 0x5b, 0x00, 0x86, 0x5b, 0x00, 0x00, 0x5c, 0x00, 0x7a, 0x5c, 0x00, 0xf4, 0x5c, 0x00, 0x6e, 0x5d, 0x00, 0xe8, 0x5d, 0x00, 0x62, 0x5e, 0x00, 0xdc, 0x5e, 0x00, 0x56, 0x5f, 0x00, 0xd0, 0x5f, 0x00, 0x4a, 0x60, 0x00, 0xc4, 0x60, 0x00, 0x3e, 0x61, 0x00, 0xb8, 0x61, 0x00, 0x32, 0x62, 0x00, 0xac, 0x62, 0x00, 0x26, 0x63, 0x00, 0xa0, 0x63, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x94, 0x64, 0x00, 0x0e, 0x65, 0x00, 0x88, 0x65, 0x00, 0x02, 0x66, 0x00, 0x7c, 0x66, 0x00, 0xf6, 0x66, 0x00, 0x70, 0x67, 0x00, 0xea, 0x67, 0x00, 0x64, 0x68, 0x00, 0xde, 0x68, 0x00, 0x58, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0x4c, 0x6a, 0x00, 0xc6, 0x6a, 0x00, 0x40, 0x6b, 0x00, 0xba, 0x6b, 0x00, 0x34, 0x6c, 0x00, 0xae, 0x6c, 0x00, 0x28, 0x6d, 0x00, 0xa2, 0x6d, 0x00, 0x1c, 0x6e, 0x00, 0x96, 0x6e, 0x00, 0x10, 0x6f, 0x00, 0x8a, 0x6f, 0x00, 0x04, 0x70, 0x00, 0x7e, 0x70, 0x00, 0xf8, 0x70, 0x00, 0x72, 0x71, 0x00, 0xec, 0x71, 0x00, 0x66, 0x72, 0x00, 0xe0, 0x72, 0x00, 0x5a, 0x73, 0x00, 0xd4, 0x73, 0x00, 0x4e, 0x74, 0x00, 0xc8, 0x74, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0xbc, 0x75, 0x00, 0x36, 0x76, 0x00, 0xb0, 0x76, 0x00, 0x2a, 0x77, 0x00, 0xa4, 0x77, 0x00, 0x1e, 0x78, 0x00, 0x98, 0x78, 0x00, 0x12, 0x79, 0x00, 0x8c, 0x79, 0x00, 0x06, 0x7a, 0x00, 0x80, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0x74, 0x7b, 0x00, 0xe2, 0x7b, 0x00, 0x50, 0x7c, 0x00, 0xbe, 0x7c, 0x00, 0x2c, 0x7d, 0x00, 0x9a, 0x7d, 0x00, 0x08, 0x7e, 0x00, 0x76, 0x7e, 0x00, 0xe4, 0x7e, 0x00, 0x52, 0x7f, 0x00, 0xc0, 0x7f, 0x00, 0x2e, 0x80, 0x00, 0x9c, 0x80, 0x00, 0x0a, 0x81, 0x00, 0x78, 0x81, 0x00, 0xe6, 0x81, 0x00, 0x54, 0x82, 0x00, 0xc2, 0x82, 0x00, 0x30, 0x83, 0x00, 0x9e, 0x83, 0x00, 0x0c, 0x84, 0x00, 0x7a, 0x84, 0x00, 0xe8, 0x84, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0xc4, 0x85, 0x00, 0x32, 0x86, 0x00, 0xa0, 0x86, 0x00, 0x0e, 0x87, 0x00, 0x7c, 0x87, 0x00, 0xea, 0x87, 0x00, 0x58, 0x88, 0x00, 0xc6, 0x88, 0x00, 0x34, 0x89, 0x00, 0xa2, 0x89, 0x00, 0x10, 0x8a, 0x00, 0x7e, 0x8a, 0x00, 0xec, 0x8a, 0x00, 0x2e, 0x8b, 0x00, 0xac, 0x8b, 0x00, 0x2a, 0x8c, 0x00, 0xa8, 0x8c, 0x00, 0x26, 0x8d, 0x00, 0xa4, 0x8d, 0x00, 0x22, 0x8e, 0x00, 0xa0, 0x8e, 0x00, 0x1e, 0x8f, 0x00, 0x60, 0x8f, 0x00, 0xa2, 0x8f, 0x00, 0xe4, 0x8f, 0x00, 0x13, 0x90, 0x00, 0x42, 0x90, 0x00, 0x65, 0x90, 0x00, 0x88, 0x90, 0x00, 0xab, 0x90, 0x00, 0xce, 0x90, 0x00, 0xf1, 0x90, 0x00, 0x57, 0x91, 0x00, 0xbd, 0x91, 0x00, 0x23, 0x92, 0x00, 0x89, 0x92, 0x00, 0xef, 0x92, 0x00, 0x55, 0x93, 0x00, 0xbb, 0x93, 0x00, 0x21, 0x94, 0x00, 0x87, 0x94, 0x00, 0xed, 0x94, 0x00, 0x53, 0x95, 0x00, 0xb9, 0x95, 0x00, 0x1f, 0x96, 0x00, 0x85, 0x96, 0x00, 0xeb, 0x96, 0x00, 0x51, 0x97, 0x00, 0xb7, 0x97, 0x00, 0x1d, 0x98, 0x00, 0x83, 0x98, 0x00, 0xe9, 0x98, 0x00, 0x4f, 0x99, 0x00, 0xb5, 0x99, 0x00, 0x1b, 0x9a, 0x00, 0x81, 0x9a, 0x00, 0xe7, 0x9a, 0x00, 0x4d, 0x9b, 0x00, 0xb3, 0x9b, 0x00, 0x19, 0x9c, 0x00, 0x7f, 0x9c, 0x00, 0xe5, 0x9c, 0x00, 0x4b, 0x9d, 0x00, 0xb1, 0x9d, 0x00, 0x17, 0x9e, 0x00, 0x7d, 0x9e, 0x00, 0xe3, 0x9e, 0x00, 0x49, 0x9f, 0x00, 0xaf, 0x9f, 0x00, 0x15, 0xa0, 0x00, 0x7b, 0xa0, 0x00, 0xe1, 0xa0, 0x00, 0x47, 0xa1, 0x00, 0xad, 0xa1, 0x00, 0x13, 0xa2, 0x00, 0x79, 0xa2, 0x00, 0xdf, 0xa2, 0x00, 0x45, 0xa3, 0x00, 0xab, 0xa3, 0x00, 0x11, 0xa4, 0x00, 0x77, 0xa4, 0x00, 0xdd, 0xa4, 0x00, 0x43, 0xa5, 0x00, 0xa9, 0xa5, 0x00, 0x0f, 0xa6, 0x00, 0x75, 0xa6, 0x00, 0xdb, 0xa6, 0x00, 0x41, 0xa7, 0x00, 0xa7, 0xa7, 0x00, 0x0d, 0xa8, 0x00, 0x73, 0xa8, 0x00, 0xd9, 0xa8, 0x00, 0x3f, 0xa9, 0x00, 0xa5, 0xa9, 0x00, 0x0b, 0xaa, 0x00, 0x71, 0xaa, 0x00, 0xd7, 0xaa, 0x00, 0x3d, 0xab, 0x00, 0xa3, 0xab, 0x00, 0x09, 0xac, 0x00, 0x6f, 0xac, 0x00, 0xd5, 0xac, 0x00, 0x3b, 0xad, 0x00, 0xa1, 0xad, 0x00, 0x07, 0xae, 0x00, 0x6d, 0xae, 0x00, 0xd3, 0xae, 0x00, 0x39, 0xaf, 0x00, 0x9f, 0xaf, 0x00, 0x05, 0xb0, 0x00, 0x6b, 0xb0, 0x00, 0xd1, 0xb0, 0x00, 0x37, 0xb1, 0x00, 0x9d, 0xb1, 0x00, 0x03, 0xb2, 0x00, 0x69, 0xb2, 0x00, 0xcf, 0xb2, 0x00, 0x35, 0xb3, 0x00, 0x9b, 0xb3, 0x00, 0x01, 0xb4, 0x00, 0x67, 0xb4, 0x00, 0xcd, 0xb4, 0x00, 0x33, 0xb5, 0x00, 0x99, 0xb5, 0x00, 0xff, 0xb5, 0x00, 0x65, 0xb6, 0x00, 0xcb, 0xb6, 0x00, 0x31, 0xb7, 0x00, 0x97, 0xb7, 0x00, 0xfd, 0xb7, 0x00, 0x63, 0xb8, 0x00, 0xc9, 0xb8, 0x00, 0x2f, 0xb9, 0x00, 0x95, 0xb9, 0x00, 0xfb, 0xb9, 0x00, 0x61, 0xba, 0x00, 0xc7, 0xba, 0x00, 0x2d, 0xbb, 0x00, 0x93, 0xbb, 0x00, 0xf9, 0xbb, 0x00, 0x5f, 0xbc, 0x00, 0xc5, 0xbc, 0x00, 0x2b, 0xbd, 0x00, 0x91, 0xbd, 0x00, 0xf7, 0xbd, 0x00, 0x5d, 0xbe, 0x00, 0xc3, 0xbe, 0x00, 0x29, 0xbf, 0x00, 0x8f, 0xbf, 0x00, 0xf5, 0xbf, 0x00, 0x5b, 0xc0, 0x00, 0xc1, 0xc0, 0x00, 0x27, 0xc1, 0x00, 0x8d, 0xc1, 0x00, 0xf3, 0xc1, 0x00, 0x59, 0xc2, 0x00, 0xbf, 0xc2, 0x00, 0x25, 0xc3, 0x00, 0x8b, 0xc3, 0x00, 0xf1, 0xc3, 0x00, 0x57, 0xc4, 0x00, 0xbd, 0xc4, 0x00, 0x23, 0xc5, 0x00, 0x89, 0xc5, 0x00, 0xef, 0xc5, 0x00, 0x55, 0xc6, 0x00, 0xbb, 0xc6, 0x00, 0x21, 0xc7, 0x00, 0x87, 0xc7, 0x00, 0xed, 0xc7, 0x00, 0x53, 0xc8, 0x00, 0xb9, 0xc8, 0x00, 0x1f, 0xc9, 0x00, 0x85, 0xc9, 0x00, 0xeb, 0xc9, 0x00, 0x51, 0xca, 0x00, 0xb7, 0xca, 0x00, 0x1d, 0xcb, 0x00, 0x83, 0xcb, 0x00, 0xe9, 0xcb, 0x00, 0x4f, 0xcc, 0x00, 0xb5, 0xcc, 0x00, 0x1b, 0xcd, 0x00, 0x81, 0xcd, 0x00, 0xe7, 0xcd, 0x00, 0x4d, 0xce, 0x00, 0xb3, 0xce, 0x00, 0x19, 0xcf, 0x00, 0x7f, 0xcf, 0x00, 0xe5, 0xcf, 0x00, 0x4b, 0xd0, 0x00, 0xb1, 0xd0, 0x00, 0x17, 0xd1, 0x00, 0x7d, 0xd1, 0x00, 0xe3, 0xd1, 0x00, 0x49, 0xd2, 0x00, 0xaf, 0xd2, 0x00, 0x15, 0xd3, 0x00, 0x7b, 0xd3, 0x00, 0xe1, 0xd3, 0x00, 0x47, 0xd4, 0x00, 0xad, 0xd4, 0x00, 0x13, 0xd5, 0x00, 0x79, 0xd5, 0x00, 0xdf, 0xd5, 0x00, 0x45, 0xd6, 0x00, 0xab, 0xd6, 0x00, 0x11, 0xd7, 0x00, 0x77, 0xd7, 0x00, 0xdd, 0xd7, 0x00, 0x43, 0xd8, 0x00, 0xa9, 0xd8, 0x00, 0x0f, 0xd9, 0x00, 0x75, 0xd9, 0x00, 0xdb, 0xd9, 0x00, 0x41, 0xda, 0x00, 0xa7, 0xda, 0x00, 0x0d, 0xdb, 0x00, 0x73, 0xdb, 0x00, 0xd9, 0xdb, 0x00, 0x3f, 0xdc, 0x00, 0xa5, 0xdc, 0x00, 0x0b, 0xdd, 0x00, 0x71, 0xdd, 0x00, 0xd7, 0xdd, 0x00, 0x3d, 0xde, 0x00, 0xa3, 0xde, 0x00, 0x09, 0xdf, 0x00, 0x6f, 0xdf, 0x00, 0xd5, 0xdf, 0x00, 0x3b, 0xe0, 0x00, 0xa1, 0xe0, 0x00, 0x07, 0xe1, 0x00, 0x6d, 0xe1, 0x00, 0xd3, 0xe1, 0x00, 0x39, 0xe2, 0x00, 0x9f, 0xe2, 0x00, 0x05, 0xe3, 0x00, 0x6b, 0xe3, 0x00, 0xd1, 0xe3, 0x00, 0x37, 0xe4, 0x00, 0x9d, 0xe4, 0x00, 0x03, 0xe5, 0x00, 0x69, 0xe5, 0x00, 0xcf, 0xe5, 0x00, 0x35, 0xe6, 0x00, 0x9b, 0xe6, 0x00, 0x01, 0xe7, 0x00, 0x67, 0xe7, 0x00, 0xcd, 0xe7, 0x00, 0x33, 0xe8, 0x00, 0x99, 0xe8, 0x00, 0xff, 0xe8, 0x00, 0x65, 0xe9, 0x00, 0xcb, 0xe9, 0x00, 0x31, 0xea, 0x00, 0x97, 0xea, 0x00, 0xfd, 0xea, 0x00, 0x63, 0xeb, 0x00, 0xc9, 0xeb, 0x00, 0x2f, 0xec, 0x00, 0x95, 0xec, 0x00, 0xfb, 0xec, 0x00, 0x61, 0xed, 0x00, 0xc7, 0xed, 0x00, 0x2d, 0xee, 0x00, 0x93, 0xee, 0x00, 0xf9, 0xee, 0x00, 0x5f, 0xef, 0x00, 0xc5, 0xef, 0x00, 0x2b, 0xf0, 0x00, 0x91, 0xf0, 0x00, 0xf7, 0xf0, 0x00, 0x5d, 0xf1, 0x00, 0xc3, 0xf1, 0x00, 0x29, 0xf2, 0x00, 0x8f, 0xf2, 0x00, 0xf5, 0xf2, 0x00, 0x5b, 0xf3, 0x00, 0xc1, 0xf3, 0x00, 0x27, 0xf4, 0x00, 0x8d, 0xf4, 0x00, 0xf3, 0xf4, 0x00, 0x59, 0xf5, 0x00, 0xbf, 0xf5, 0x00, 0x25, 0xf6, 0x00, 0x8b, 0xf6, 0x00, 0xf1, 0xf6, 0x00, 0x57, 0xf7, 0x00, 0xbd, 0xf7, 0x00, 0x23, 0xf8, 0x00, 0x89, 0xf8, 0x00, 0xef, 0xf8, 0x00, 0x55, 0xf9, 0x00, 0xbb, 0xf9, 0x00, 0x21, 0xfa, 0x00, 0x87, 0xfa, 0x00, 0xed, 0xfa, 0x00, 0x53, 0xfb, 0x00, 0xb9, 0xfb, 0x00, 0x1f, 0xfc, 0x00, 0x85, 0xfc, 0x00, 0xeb, 0xfc, 0x00, 0x51, 0xfd, 0x00, 0xb7, 0xfd, 0x00, 0x1d, 0xfe, 0x00, 0x83, 0xfe, 0x00, 0xe9, 0xfe, 0x00, 0x4f, 0xff, 0x00, 0xb5, 0xff, 0x00, 0x1b, 0x00, 0x01, 0x81, 0x00, 0x01, 0xe7, 0x00, 0x01, 0x4d, 0x01, 0x01, 0xb3, 0x01, 0x01, 0x19, 0x02, 0x01, 0x7f, 0x02, 0x01, 0xe5, 0x02, 0x01, 0x4b, 0x03, 0x01, 0xb1, 0x03, 0x01, 0x17, 0x04, 0x01, 0x7d, 0x04, 0x01, 0xe3, 0x04, 0x01, 0x49, 0x05, 0x01, 0xaf, 0x05, 0x01, 0x15, 0x06, 0x01, 0x7b, 0x06, 0x01, 0xe1, 0x06, 0x01, 0x47, 0x07, 0x01, 0xad, 0x07, 0x01, 0x13, 0x08, 0x01, 0x79, 0x08, 0x01, 0xdf, 0x08, 0x01, 0x45, 0x09, 0x01, 0xab, 0x09, 0x01, 0x11, 0x0a, 0x01, 0x77, 0x0a, 0x01, 0xdd, 0x0a, 0x01, 0x43, 0x0b, 0x01, 0xa9, 0x0b, 0x01, 0x0f, 0x0c, 0x01, 0x75, 0x0c, 0x01, 0xdb, 0x0c, 0x01, 0x41, 0x0d, 0x01, 0xa7, 0x0d, 0x01, 0x0d, 0x0e, 0x01, 0x73, 0x0e, 0x01, 0xd9, 0x0e, 0x01, 0x3f, 0x0f, 0x01, 0xa5, 0x0f, 0x01, 0x0b, 0x10, 0x01, 0x71, 0x10, 0x01, 0xd7, 0x10, 0x01, 0x3d, 0x11, 0x01, 0xa3, 0x11, 0x01, 0x09, 0x12, 0x01, 0x6f, 0x12, 0x01, 0xd5, 0x12, 0x01, 0x3b, 0x13, 0x01, 0xa1, 0x13, 0x01, 0x07, 0x14, 0x01, 0x6d, 0x14, 0x01, 0xd3, 0x14, 0x01, 0x39, 0x15, 0x01, 0x9f, 0x15, 0x01, 0x05, 0x16, 0x01, 0x6b, 0x16, 0x01, 0xd1, 0x16, 0x01, 0x37, 0x17, 0x01, 0x9d, 0x17, 0x01, 0x03, 0x18, 0x01, 0x69, 0x18, 0x01, 0xcf, 0x18, 0x01, 0x35, 0x19, 0x01, 0x9b, 0x19, 0x01, 0x01, 0x1a, 0x01, 0x67, 0x1a, 0x01, 0xcd, 0x1a, 0x01, 0x33, 0x1b, 0x01, 0x99, 0x1b, 0x01, 0xff, 0x1b, 0x01, 0x65, 0x1c, 0x01, 0xcb, 0x1c, 0x01, 0x31, 0x1d, 0x01, 0x97, 0x1d, 0x01, 0xfd, 0x1d, 0x01, 0x63, 0x1e, 0x01, 0xc9, 0x1e, 0x01, 0x2f, 0x1f, 0x01, 0x95, 0x1f, 0x01, 0xfb, 0x1f, 0x01, 0x61, 0x20, 0x01, 0xc7, 0x20, 0x01, 0x2d, 0x21, 0x01, 0x93, 0x21, 0x01, 0xf9, 0x21, 0x01, 0x5f, 0x22, 0x01, 0xc5, 0x22, 0x01, 0x2b, 0x23, 0x01, 0x91, 0x23, 0x01, 0xf7, 0x23, 0x01, 0x5d, 0x24, 0x01, 0xc3, 0x24, 0x01, 0x29, 0x25, 0x01, 0x8f, 0x25, 0x01, 0xf5, 0x25, 0x01, 0x5b, 0x26, 0x01, 0xc1, 0x26, 0x01, 0x27, 0x27, 0x01, 0x8d, 0x27, 0x01, 0xf3, 0x27, 0x01, 0x59, 0x28, 0x01, 0xbf, 0x28, 0x01, 0x25, 0x29, 0x01, 0x8b, 0x29, 0x01, 0xf1, 0x29, 0x01, 0x57, 0x2a, 0x01, 0xbd, 0x2a, 0x01, 0x23, 0x2b, 0x01, 0x89, 0x2b, 0x01, 0xef, 0x2b, 0x01, 0x55, 0x2c, 0x01, 0xbb, 0x2c, 0x01, 0x21, 0x2d, 0x01, 0x87, 0x2d, 0x01, 0xed, 0x2d, 0x01, 0x53, 0x2e, 0x01, 0xb9, 0x2e, 0x01, 0x1f, 0x2f, 0x01, 0x85, 0x2f, 0x01, 0xeb, 0x2f, 0x01, 0x51, 0x30, 0x01, 0xb7, 0x30, 0x01, 0x1d, 0x31, 0x01, 0x83, 0x31, 0x01, 0xe9, 0x31, 0x01, 0x4f, 0x32, 0x01, 0xb5, 0x32, 0x01, 0x1b, 0x33, 0x01, 0x81, 0x33, 0x01, 0xe7, 0x33, 0x01, 0x4d, 0x34, 0x01, 0xb3, 0x34, 0x01, 0x19, 0x35, 0x01, 0x7f, 0x35, 0x01, 0xe5, 0x35, 0x01, 0x4b, 0x36, 0x01, 0xb1, 0x36, 0x01, 0x17, 0x37, 0x01, 0x7d, 0x37, 0x01, 0xe3, 0x37, 0x01, 0x49, 0x38, 0x01, 0xaf, 0x38, 0x01, 0x15, 0x39, 0x01, 0x7b, 0x39, 0x01, 0xe1, 0x39, 0x01, 0x47, 0x3a, 0x01, 0xad, 0x3a, 0x01, 0x13, 0x3b, 0x01, 0x79, 0x3b, 0x01, 0xdf, 0x3b, 0x01, 0x45, 0x3c, 0x01, 0xab, 0x3c, 0x01, 0x11, 0x3d, 0x01, 0x77, 0x3d, 0x01, 0xdd, 0x3d, 0x01, 0x43, 0x3e, 0x01, 0xa9, 0x3e, 0x01, 0x0f, 0x3f, 0x01, 0x75, 0x3f, 0x01, 0xdb, 0x3f, 0x01, 0x41, 0x40, 0x01, 0xa7, 0x40, 0x01, 0x0d, 0x41, 0x01, 0x73, 0x41, 0x01, 0xd9, 0x41, 0x01, 0x3f, 0x42, 0x01, 0xa5, 0x42, 0x01, 0x0b, 0x43, 0x01, 0x71, 0x43, 0x01, 0xd7, 0x43, 0x01, 0x3d, 0x44, 0x01, 0xa3, 0x44, 0x01, 0x09, 0x45, 0x01, 0x6f, 0x45, 0x01, 0xd5, 0x45, 0x01, 0x3b, 0x46, 0x01, 0xa1, 0x46, 0x01, 0x07, 0x47, 0x01, 0x6d, 0x47, 0x01, 0xd3, 0x47, 0x01, 0x39, 0x48, 0x01, 0x9f, 0x48, 0x01, 0x05, 0x49, 0x01, 0x6b, 0x49, 0x01, 0xd1, 0x49, 0x01, 0x37, 0x4a, 0x01, 0x9d, 0x4a, 0x01, 0x03, 0x4b, 0x01, 0x69, 0x4b, 0x01, 0xcf, 0x4b, 0x01, 0x35, 0x4c, 0x01, 0x9b, 0x4c, 0x01, 0x01, 0x4d, 0x01, 0x67, 0x4d, 0x01, 0xcd, 0x4d, 0x01, 0x33, 0x4e, 0x01, 0x99, 0x4e, 0x01, 0xff, 0x4e, 0x01, 0x65, 0x4f, 0x01, 0xcb, 0x4f, 0x01, 0x31, 0x50, 0x01, 0x97, 0x50, 0x01, 0xfd, 0x50, 0x01, 0x63, 0x51, 0x01, 0xc9, 0x51, 0x01, 0x2f, 0x52, 0x01, 0x95, 0x52, 0x01, 0xfb, 0x52, 0x01, 0x61, 0x53, 0x01, 0xc7, 0x53, 0x01, 0x2d, 0x54, 0x01, 0x93, 0x54, 0x01, 0xf9, 0x54, 0x01, 0x5f, 0x55, 0x01, 0xc5, 0x55, 0x01, 0x2b, 0x56, 0x01, 0x91, 0x56, 0x01, 0xf7, 0x56, 0x01, 0x5d, 0x57, 0x01, 0xc3, 0x57, 0x01, 0x29, 0x58, 0x01, 0x8f, 0x58, 0x01, 0xf5, 0x58, 0x01, 0x5b, 0x59, 0x01, 0xc1, 0x59, 0x01, 0x27, 0x5a, 0x01, 0x8d, 0x5a, 0x01, 0xf3, 0x5a, 0x01, 0x59, 0x5b, 0x01, 0xbf, 0x5b, 0x01, 0x25, 0x5c, 0x01, 0x8b, 0x5c, 0x01, 0xf1, 0x5c, 0x01, 0x57, 0x5d, 0x01, 0xbd, 0x5d, 0x01, 0x23, 0x5e, 0x01, 0x89, 0x5e, 0x01, 0xef, 0x5e, 0x01, 0x55, 0x5f, 0x01, 0xbb, 0x5f, 0x01, 0x21, 0x60, 0x01, 0x87, 0x60, 0x01, 0xed, 0x60, 0x01, 0x53, 0x61, 0x01, 0xb9, 0x61, 0x01, 0x1f, 0x62, 0x01, 0x85, 0x62, 0x01, 0xeb, 0x62, 0x01, 0x51, 0x63, 0x01, 0xb7, 0x63, 0x01, 0x1d, 0x64, 0x01, 0x83, 0x64, 0x01, 0xe9, 0x64, 0x01, 0x4f, 0x65, 0x01, 0xb5, 0x65, 0x01, 0x1b, 0x66, 0x01, 0x81, 0x66, 0x01, 0xe7, 0x66, 0x01, 0x4d, 0x67, 0x01, 0xb3, 0x67, 0x01, 0x19, 0x68, 0x01, 0x7f, 0x68, 0x01, 0xe5, 0x68, 0x01, 0x4b, 0x69, 0x01, 0xb1, 0x69, 0x01, 0x17, 0x6a, 0x01, 0x7d, 0x6a, 0x01, 0xe3, 0x6a, 0x01, 0x49, 0x6b, 0x01, 0xaf, 0x6b, 0x01, 0x15, 0x6c, 0x01, 0x7b, 0x6c, 0x01, 0xe1, 0x6c, 0x01, 0x47, 0x6d, 0x01, 0xad, 0x6d, 0x01, 0x13, 0x6e, 0x01, 0x79, 0x6e, 0x01, 0xdf, 0x6e, 0x01, 0x45, 0x6f, 0x01, 0xab, 0x6f, 0x01, 0x11, 0x70, 0x01, 0x77, 0x70, 0x01, 0xdd, 0x70, 0x01, 0x43, 0x71, 0x01, 0xa9, 0x71, 0x01, 0x0f, 0x72, 0x01, 0x75, 0x72, 0x01, 0xdb, 0x72, 0x01, 0x41, 0x73, 0x01, 0xa7, 0x73, 0x01, 0x0d, 0x74, 0x01, 0x73, 0x74, 0x01, 0xd9, 0x74, 0x01, 0x3f, 0x75, 0x01, 0xa5, 0x75, 0x01, 0x0b, 0x76, 0x01, 0x71, 0x76, 0x01, 0xd7, 0x76, 0x01, 0x3d, 0x77, 0x01, 0xa3, 0x77, 0x01, 0x09, 0x78, 0x01, 0x6f, 0x78, 0x01, 0xd5, 0x78, 0x01, 0x3b, 0x79, 0x01, 0xa1, 0x79, 0x01, 0x07, 0x7a, 0x01, 0x6d, 0x7a, 0x01, 0xd3, 0x7a, 0x01, 0x39, 0x7b, 0x01, 0x9f, 0x7b, 0x01, 0x05, 0x7c, 0x01, 0x6b, 0x7c, 0x01, 0xd1, 0x7c, 0x01, 0x37, 0x7d, 0x01, 0x9d, 0x7d, 0x01, 0x03, 0x7e, 0x01, 0x69, 0x7e, 0x01, 0xcf, 0x7e, 0x01, 0x35, 0x7f, 0x01, 0x9b, 0x7f, 0x01, 0x01, 0x80, 0x01, 0x67, 0x80, 0x01, 0xcd, 0x80, 0x01, 0x33, 0x81, 0x01, 0x99, 0x81, 0x01, 0xff, 0x81, 0x01, 0x65, 0x82, 0x01, 0xcb, 0x82, 0x01, 0x31, 0x83, 0x01, 0x97, 0x83, 0x01, 0xfd, 0x83, 0x01, 0x63, 0x84, 0x01, 0xc9, 0x84, 0x01, 0x2f, 0x85, 0x01, 0x95, 0x85, 0x01, 0xfb, 0x85, 0x01, 0x61, 0x86, 0x01, 0xc7, 0x86, 0x01, 0x2d, 0x87, 0x01, 0x93, 0x87, 0x01, 0xf9, 0x87, 0x01, 0x5f, 0x88, 0x01, 0xc5, 0x88, 0x01, 0x2b, 0x89, 0x01, 0x91, 0x89, 0x01, 0xf7, 0x89, 0x01, 0x5d, 0x8a, 0x01, 0xc3, 0x8a, 0x01, 0x29, 0x8b, 0x01, 0x8f, 0x8b, 0x01, 0xf5, 0x8b, 0x01, 0x5b, 0x8c, 0x01, 0xc1, 0x8c, 0x01, 0x27, 0x8d, 0x01, 0x8d, 0x8d, 0x01, 0xf3, 0x8d, 0x01, 0x59, 0x8e, 0x01, 0xbf, 0x8e, 0x01, 0x25, 0x8f, 0x01, 0x8b, 0x8f, 0x01, 0xf1, 0x8f, 0x01, 0x57, 0x90, 0x01, 0xbd, 0x90, 0x01, 0x23, 0x91, 0x01, 0x89, 0x91, 0x01, 0xef, 0x91, 0x01, 0x55, 0x92, 0x01, 0xbb, 0x92, 0x01, 0x21, 0x93, 0x01, 0x87, 0x93, 0x01, 0xed, 0x93, 0x01, 0x53, 0x94, 0x01, 0xb9, 0x94, 0x01, 0x1f, 0x95, 0x01, 0x85, 0x95, 0x01, 0xeb, 0x95, 0x01, 0x51, 0x96, 0x01, 0xb7, 0x96, 0x01, 0x1d, 0x97, 0x01, 0x83, 0x97, 0x01, 0xe9, 0x97, 0x01, 0x4f, 0x98, 0x01, 0xb5, 0x98, 0x01, 0x1b, 0x99, 0x01, 0x81, 0x99, 0x01, 0xe7, 0x99, 0x01, 0x4d, 0x9a, 0x01, 0xb3, 0x9a, 0x01, 0x19, 0x9b, 0x01, 0x7f, 0x9b, 0x01, 0xe5, 0x9b, 0x01, 0x4b, 0x9c, 0x01, 0xb1, 0x9c, 0x01, 0x17, 0x9d, 0x01, 0x7d, 0x9d, 0x01, 0xe3, 0x9d, 0x01, 0x49, 0x9e, 0x01, 0xaf, 0x9e, 0x01, 0x15, 0x9f, 0x01, 0x7b, 0x9f, 0x01, 0xe1, 0x9f, 0x01, 0x47, 0xa0, 0x01, 0xad, 0xa0, 0x01, 0x13, 0xa1, 0x01, 0x79, 0xa1, 0x01, 0xdf, 0xa1, 0x01, 0x45, 0xa2, 0x01, 0xab, 0xa2, 0x01, 0x11, 0xa3, 0x01, 0x77, 0xa3, 0x01, 0xdd, 0xa3, 0x01, 0x43, 0xa4, 0x01, 0xa9, 0xa4, 0x01, 0x0f, 0xa5, 0x01, 0x75, 0xa5, 0x01, 0xdb, 0xa5, 0x01, 0x41, 0xa6, 0x01, 0xa7, 0xa6, 0x01, 0x0d, 0xa7, 0x01, 0x73, 0xa7, 0x01, 0xd9, 0xa7, 0x01, 0x3f, 0xa8, 0x01, 0xa5, 0xa8, 0x01, 0x0b, 0xa9, 0x01, 0x71, 0xa9, 0x01, 0xd7, 0xa9, 0x01, 0x3d, 0xaa, 0x01, 0xa3, 0xaa, 0x01, 0x09, 0xab, 0x01, 0x6f, 0xab, 0x01, 0xd5, 0xab, 0x01, 0x3b, 0xac, 0x01, 0xa1, 0xac, 0x01, 0x07, 0xad, 0x01, 0x6d, 0xad, 0x01, 0xd3, 0xad, 0x01, 0x39, 0xae, 0x01, 0x9f, 0xae, 0x01, 0x05, 0xaf, 0x01, 0x6b, 0xaf, 0x01, 0xd1, 0xaf, 0x01, 0x37, 0xb0, 0x01, 0x9d, 0xb0, 0x01, 0x03, 0xb1, 0x01, 0x69, 0xb1, 0x01, 0xcf, 0xb1, 0x01, 0x35, 0xb2, 0x01, 0x9b, 0xb2, 0x01, 0x01, 0xb3, 0x01, 0x67, 0xb3, 0x01, 0xcd, 0xb3, 0x01, 0x33, 0xb4, 0x01, 0x99, 0xb4, 0x01, 0xff, 0xb4, 0x01, 0x65, 0xb5, 0x01, 0xcb, 0xb5, 0x01, 0x31, 0xb6, 0x01, 0x97, 0xb6, 0x01, 0xfd, 0xb6, 0x01, 0x63, 0xb7, 0x01, 0xc9, 0xb7, 0x01, 0x2f, 0xb8, 0x01, 0x95, 0xb8, 0x01, 0xfb, 0xb8, 0x01, 0x61, 0xb9, 0x01, 0xc7, 0xb9, 0x01, 0x2d, 0xba, 0x01, 0x93, 0xba, 0x01, 0xf9, 0xba, 0x01, 0x5f, 0xbb, 0x01, 0xc5, 0xbb, 0x01, 0x2b, 0xbc, 0x01, 0x91, 0xbc, 0x01, 0xf7, 0xbc, 0x01, 0x5d, 0xbd, 0x01, 0xc3, 0xbd, 0x01, 0x29, 0xbe, 0x01, 0x8f, 0xbe, 0x01, 0xf5, 0xbe, 0x01, 0x5b, 0xbf, 0x01, 0xc1, 0xbf, 0x01, 0x27, 0xc0, 0x01, 0x8d, 0xc0, 0x01, 0xf3, 0xc0, 0x01, 0x59, 0xc1, 0x01, 0xbf, 0xc1, 0x01, 0x25, 0xc2, 0x01, 0x8b, 0xc2, 0x01, 0xf1, 0xc2, 0x01, 0x57, 0xc3, 0x01, 0xbd, 0xc3, 0x01, 0x23, 0xc4, 0x01, 0x89, 0xc4, 0x01, 0xef, 0xc4, 0x01, 0x55, 0xc5, 0x01, 0xbb, 0xc5, 0x01, 0x21, 0xc6, 0x01, 0x87, 0xc6, 0x01, 0xed, 0xc6, 0x01, 0x53, 0xc7, 0x01, 0xb9, 0xc7, 0x01, 0x1f, 0xc8, 0x01, 0x85, 0xc8, 0x01, 0xeb, 0xc8, 0x01, 0x51, 0xc9, 0x01, 0xb7, 0xc9, 0x01, 0x1d, 0xca, 0x01, 0x83, 0xca, 0x01, 0xe9, 0xca, 0x01, 0x4f, 0xcb, 0x01, 0xb5, 0xcb, 0x01, 0x1b, 0xcc, 0x01, 0x1f, 0x04, 0x07, 0x04, 0x04, 0x02, 0x03, 0x10, 0x00, 0x00, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x0a, 0x06, 0x00, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x10, 0x00, 0x00, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x1f, 0x00, 0x08, 0x00, 0x06, 0x00, 0x03, 0x0a, 0x06, 0x00, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x1e, 0x0b, 0x06, 0x04, 0x04, 0x03, 0x04, 0x0c, 0x04, 0x00, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x13, 0xf8, 0x01, 0x87, 0xf9, 0x01, 0x87, 0xf9, 0x01, 0x35, 0xee, 0x01, 0xa9, 0xf2, 0x01, 0xa9, 0xf2, 0x01, 0x35, 0xee, 0x01, 0xa9, 0xf2, 0x01, 0xa9, 0xf2, 0x01, 0x1e, 0x04, 0x0b, 0x04, 0x08, 0x02, 0x06, 0x04, 0x06, 0x06, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x18, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x0a, 0x06, 0x00, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x08, 0x04, 0x04, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0xb7, 0x11, 0x02, 0x21, 0x17, 0x02, 0x09, 0x1d, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x03, 0x05, 0x08, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0x7c, 0x00, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x73, 0x30, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xf0, 0x3c, 0x03, 0x55, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0xff, 0x00, 0x03, 0x55, 0x55, 0xff, 0x00, 0x3d, 0x55, 0x55, 0xff, 0x00, 0xcd, 0x55, 0x55, 0xcf, 0xff, 0x0d, 0x55, 0x55, 0x73, 0x30, 0x3d, 0x55, 0x55, 0x73, 0xf0, 0xf5, 0x55, 0x55, 0x73, 0xf0, 0x35, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x7f, 0x55, 0x57, 0xff, 0x55, 0xff, 0xd5, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x0f, 0x00, 0xf0, 0xd5, 0x57, 0x30, 0xc3, 0x0c, 0xd5, 0x57, 0x00, 0x3c, 0x00, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x57, 0x3f, 0xff, 0xfc, 0xd5, 0x57, 0xf0, 0xc3, 0x0f, 0xd5, 0x55, 0x73, 0xff, 0xcd, 0x55, 0x55, 0xc3, 0xff, 0xc3, 0x55, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x03, 0x00, 0xc0, 0xd5, 0x57, 0x0c, 0x00, 0x30, 0xd5, 0x57, 0x00, 0x3c, 0x00, 0xd5, 0x55, 0xc0, 0xff, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x3f, 0x0f, 0xc3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x00, 0xf0, 0x0d, 0x55, 0x55, 0xff, 0x0f, 0xf5, 0x55, 0x57, 0x33, 0xfc, 0xcd, 0x55, 0x57, 0xf3, 0xfc, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x30, 0x00, 0x0c, 0xd5, 0x57, 0x0c, 0x00, 0x30, 0xd5, 0x57, 0x00, 0xff, 0x00, 0xd5, 0x5f, 0x03, 0xff, 0xc0, 0xf5, 0x5c, 0xc3, 0xff, 0xc3, 0x35, 0x5f, 0x3f, 0xff, 0xfc, 0xf5, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0xc3, 0xff, 0xc3, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x7f, 0x55, 0x57, 0xff, 0x55, 0xff, 0xd5, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x03, 0x00, 0xc0, 0xd5, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x30, 0x3c, 0x0c, 0xd5, 0x55, 0xcc, 0x3c, 0x33, 0xd5, 0x55, 0xcc, 0x3c, 0x33, 0x55, 0x55, 0xc3, 0xc3, 0xc3, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xd7, 0xf5, 0x55, 0x55, 0x5f, 0x55, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x5c, 0x3f, 0xff, 0xc3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x55, 0xff, 0xff, 0xf5, 0x55, 0x55, 0xc0, 0x00, 0x35, 0x55, 0x57, 0x30, 0x00, 0xcd, 0x55, 0x57, 0xf0, 0x00, 0xfd, 0x55, 0x55, 0x70, 0x00, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0x55, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0x70, 0x00, 0x3d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x70, 0x0c, 0xd5, 0x55, 0x57, 0xc0, 0xfc, 0xd5, 0x55, 0x55, 0xf0, 0x3f, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0x57, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0x70, 0x00, 0x3d, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x30, 0xcd, 0x55, 0x55, 0xfc, 0x3f, 0xf5, 0x55, 0x55, 0x70, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x70, 0x3f, 0xf5, 0x55, 0x55, 0xc0, 0x0f, 0xf5, 0x55, 0x7f, 0xc0, 0x0f, 0xf5, 0x5f, 0xc0, 0xc0, 0x0f, 0x55, 0x5f, 0xc0, 0xc0, 0xcf, 0xd5, 0x55, 0xc0, 0xc0, 0xcf, 0xd5, 0x57, 0xc0, 0x3c, 0xcf, 0xf5, 0x5f, 0xfc, 0x03, 0x0f, 0xf5, 0x5f, 0xff, 0xff, 0xf7, 0xd5, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x3c, 0x03, 0xc3, 0x55, 0x5c, 0xc3, 0x0c, 0x33, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0xc3, 0x0c, 0x33, 0x55, 0x57, 0x30, 0xf0, 0xcc, 0xd5, 0x55, 0xff, 0xff, 0xf0, 0xd5, 0x55, 0x73, 0x0c, 0x03, 0x55, 0x55, 0xcc, 0xfc, 0x0d, 0x55, 0x55, 0xfc, 0xff, 0x0d, 0x55, 0x55, 0x5c, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x55, 0xf5, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x00, 0xc3, 0x00, 0xd5, 0x57, 0x3f, 0xc3, 0xfc, 0xd5, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x5c, 0xcc, 0x35, 0x55, 0x55, 0x73, 0xff, 0xcd, 0x55, 0x55, 0x70, 0xfc, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xc0, 0x30, 0x03, 0x55, 0x55, 0xc0, 0xc0, 0x03, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xfc, 0x00, 0x03, 0x55, 0x55, 0xff, 0x03, 0xc3, 0x55, 0x55, 0x7f, 0x03, 0x3d, 0x55, 0x55, 0x5f, 0xff, 0x35, 0x55, 0x55, 0x5c, 0xcc, 0x0d, 0x55, 0x55, 0x57, 0x3c, 0x03, 0x55, 0x55, 0x57, 0x3c, 0x3f, 0x55, 0x55, 0x57, 0xff, 0xf5, 0x55, 0x55, 0x55, 0x7d, 0xfd, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0x7f, 0x55, 0x55, 0x55, 0xff, 0xff, 0xd5, 0x55, 0x55, 0xff, 0xff, 0xd5, 0x55, 0x55, 0xff, 0x00, 0x35, 0x55, 0x57, 0xf0, 0x00, 0x3d, 0x55, 0x57, 0xc0, 0x03, 0x03, 0x55, 0x57, 0x00, 0x3c, 0x03, 0x55, 0x57, 0x00, 0x00, 0x0f, 0x55, 0x57, 0x00, 0x00, 0x35, 0x55, 0x57, 0xc0, 0x03, 0xd5, 0x55, 0x55, 0x7f, 0xff, 0x55, 0x55, 0x55, 0xc0, 0xcf, 0x55, 0x55, 0x57, 0x30, 0xfd, 0x55, 0x55, 0x57, 0xf0, 0xfd, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x7d, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xf5, 0x55, 0x55, 0x5f, 0xfd, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0x00, 0x0d, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x0f, 0xc3, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0x70, 0x00, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x5c, 0x3c, 0xd5, 0x55, 0x55, 0x5f, 0x0f, 0xd5, 0x55, 0x55, 0x5c, 0xff, 0xd5, 0x55, 0x55, 0x70, 0x0f, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3c, 0x0f, 0x55, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0xc0, 0x00, 0xff, 0x55, 0x55, 0xc0, 0xf0, 0xff, 0x55, 0x55, 0x70, 0xcc, 0xfd, 0x55, 0x55, 0x5f, 0xcf, 0xd5, 0x55, 0x55, 0x5c, 0xcc, 0xd5, 0x55, 0x55, 0x5c, 0x3f, 0xd5, 0x55, 0x55, 0x5c, 0x0f, 0xd5, 0x55, 0x55, 0x70, 0x0f, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x55, 0xfd, 0x55, 0x55, 0x7f, 0xdf, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0xc3, 0x55, 0x55, 0xcc, 0x00, 0x03, 0x55, 0x55, 0x73, 0x00, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x73, 0x30, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0x7f, 0x55, 0x55, 0xff, 0xd5, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0xd5, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0x70, 0x00, 0x03, 0x55, 0x55, 0xc3, 0x00, 0x30, 0xd5, 0x55, 0xcc, 0xc0, 0xcc, 0xd5, 0x55, 0xc3, 0x00, 0x30, 0xd5, 0x57, 0xc0, 0x3f, 0x00, 0xd5, 0x57, 0x30, 0xff, 0xc3, 0x55, 0x55, 0xcf, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xc3, 0xfc, 0x03, 0x55, 0x55, 0xc3, 0xfc, 0x3c, 0xd5, 0x55, 0x7f, 0xfc, 0x37, 0xd5, 0x55, 0x5f, 0x7f, 0xd5, 0x55, 0x55, 0x55, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x3c, 0x03, 0xc3, 0x55, 0x5c, 0xf3, 0x0f, 0x33, 0x55, 0x5c, 0xff, 0x0f, 0xf3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x0f, 0xf0, 0x0d, 0x55, 0x55, 0xfc, 0x3f, 0xf5, 0x55, 0x55, 0xc3, 0xcc, 0x3d, 0x55, 0x55, 0x70, 0xfc, 0xf3, 0x55, 0x55, 0x70, 0xfc, 0xdf, 0x55, 0x55, 0x7f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xcd, 0x55, 0x5f, 0xff, 0xff, 0xfd, 0x55, 0x7f, 0xff, 0xff, 0xd5, 0x55, 0x70, 0x00, 0x03, 0xd5, 0x55, 0xff, 0xff, 0xfc, 0xd5, 0x55, 0xc0, 0x00, 0x0f, 0xd5, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0x7c, 0x00, 0x0c, 0xd5, 0x55, 0x5f, 0xff, 0xf0, 0x35, 0x55, 0x7f, 0x3f, 0xfc, 0x0d, 0x55, 0x7f, 0x3f, 0xfc, 0x0d, 0x55, 0x70, 0x00, 0x3c, 0x0d, 0x55, 0x7f, 0xff, 0xf0, 0x0d, 0x55, 0x5f, 0xff, 0xdf, 0xf5, 0x55, 0x7f, 0xdf, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0x55, 0x55, 0x55, 0x57, 0x35, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0xff, 0xff, 0x55, 0x55, 0x5f, 0xff, 0xff, 0x55, 0x55, 0x70, 0x00, 0x0f, 0x55, 0x55, 0x7f, 0xff, 0xf3, 0xfd, 0x55, 0xc0, 0x00, 0x0c, 0xc3, 0x55, 0xc0, 0x00, 0x03, 0xc3, 0x55, 0xc0, 0x00, 0x03, 0x03, 0x55, 0xf0, 0x03, 0x03, 0xc3, 0x55, 0xc3, 0xc0, 0x0f, 0xc3, 0x55, 0xc3, 0xc0, 0x3f, 0x0d, 0x55, 0x7f, 0xff, 0xfc, 0x35, 0x5d, 0xff, 0x3f, 0xf3, 0xd5, 0x5f, 0x00, 0x00, 0xfd, 0x55, 0x5f, 0xff, 0xff, 0x3d, 0x55, 0x55, 0xff, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xff, 0x55, 0x55, 0x7f, 0xff, 0xff, 0xd5, 0x55, 0xf0, 0x00, 0x03, 0xf5, 0x55, 0xcf, 0xff, 0xfc, 0xf5, 0x55, 0xf0, 0x00, 0x03, 0xff, 0x57, 0x0f, 0xc0, 0xfc, 0xf3, 0x57, 0x33, 0xc3, 0x3c, 0xdf, 0x57, 0x33, 0xc3, 0x3c, 0xd5, 0x57, 0x0f, 0xc0, 0xfc, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x35, 0x55, 0xff, 0xff, 0xfc, 0x0d, 0x57, 0xff, 0xcf, 0xf3, 0x0d, 0x5c, 0xff, 0xcf, 0xff, 0x0d, 0x57, 0x70, 0x00, 0x0c, 0x0d, 0x55, 0x7f, 0xff, 0xf7, 0xf5, 0x55, 0x57, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xf7, 0xfd, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xff, 0xf5, 0x55, 0x70, 0x00, 0xff, 0xff, 0x55, 0x7f, 0xfc, 0x03, 0xf3, 0x55, 0xf0, 0xff, 0xf0, 0xdf, 0x55, 0xf0, 0xf3, 0x0f, 0xd5, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xff, 0xf0, 0x33, 0x55, 0x57, 0x3f, 0xc0, 0xff, 0xd5, 0x57, 0xcf, 0xff, 0xfc, 0x35, 0x55, 0xff, 0x3f, 0xfc, 0x0d, 0x55, 0x7f, 0x3f, 0xf0, 0x0d, 0x55, 0x7f, 0x3f, 0xf0, 0x0d, 0x55, 0x70, 0x00, 0xf0, 0x0d, 0x55, 0x5f, 0xff, 0xdf, 0xf5, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x55, 0xf7, 0xd5, 0x55, 0x30, 0x1f, 0x01, 0x55, 0x40, 0x00, 0x00, 0x00, 0x15, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x11, 0x41, 0x50, 0x00, 0x00, 0x15, 0x55, 0x55, 0x54, 0x04, 0x10, 0x01, 0x55, 0x41, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa1, 0x14, 0x15, 0x54, 0x01, 0x11, 0x45, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa5, 0x54, 0x15, 0x54, 0x01, 0x55, 0x45, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa1, 0x14, 0x44, 0x11, 0x55, 0x55, 0x55, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x15, 0x40, 0x01, 0x55, 0x11, 0x56, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x95, 0x40, 0x01, 0x55, 0x55, 0x56, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x95, 0x55, 0x55, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x55, 0x50, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x01, 0x50, 0x55, 0x50, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x15, 0x55, 0x55, 0x54, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x02, 0x55, 0x55, 0x55, 0x00, 0x04, 0x00, 0x80, 0x28, 0x00, 0x00, 0xa0, 0x02, 0x01, 0x15, 0x55, 0x10, 0x04, 0x55, 0x80, 0x28, 0x00, 0x00, 0xa0, 0x02, 0x01, 0x15, 0x55, 0x01, 0x55, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x02, 0x55, 0x55, 0x55, 0x01, 0x01, 0x00, 0x80, 0xaa, 0xaa, 0xaa, 0xa8, 0x02, 0x00, 0x04, 0x01, 0x01, 0x55, 0x00, 0x82, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x04, 0x01, 0x00, 0x41, 0x00, 0x82, 0xaa, 0xaa, 0xaa, 0xaa, 0x02, 0x00, 0x04, 0x01, 0x55, 0x5a, 0xa5, 0x80, 0x95, 0x95, 0x80, 0x00, 0x02, 0x55, 0x54, 0x01, 0x00, 0x25, 0x58, 0x80, 0x95, 0x95, 0x85, 0x54, 0x0a, 0xaa, 0xa8, 0x01, 0x00, 0x26, 0x98, 0x80, 0x95, 0x95, 0x85, 0x54, 0x08, 0x00, 0x09, 0x55, 0x00, 0x25, 0x58, 0x80, 0x95, 0x95, 0xaa, 0xaa, 0x08, 0x88, 0x88, 0x00, 0x00, 0x20, 0x08, 0x95, 0x95, 0x95, 0x80, 0x02, 0x58, 0x88, 0x88, 0x00, 0xaa, 0xa0, 0x0a, 0x95, 0x95, 0x95, 0x80, 0x02, 0x58, 0x00, 0x0a, 0xaa, 0x04, 0x20, 0x08, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa9, 0x55, 0x58, 0x00, 0x00, 0x0a, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xaa, 0xa9, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0x42, 0x82, 0x20, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa6, 0x86, 0x26, 0x62, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x45, 0x86, 0x24, 0xa4, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xa4, 0xa1, 0x61, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x61, 0x40, 0xa2, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0xaa, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa9, 0x55, 0x69, 0x55, 0x6a, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x9a, 0xa9, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x59, 0x59, 0x6a, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x98, 0x49, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x95, 0x55, 0xaa, 0x95, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa5, 0x56, 0xaa, 0x40, 0x68, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa8, 0x0a, 0xa5, 0x55, 0x58, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa9, 0x5a, 0xa5, 0x55, 0x58, 0x00, 0x95, 0x5a, 0x69, 0xa5, 0x56, 0x02, 0xa5, 0x96, 0xa9, 0x69, 0x68, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x96, 0x5a, 0x69, 0xa5, 0x96, 0x54, 0x54, 0x54, 0x54, 0x54, 0x55, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x54, 0x54, 0x54, 0x54, 0x54, 0x55, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x30, 0x1f, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x15, 0x00, 0x00, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x55, 0x00, 0x01, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x40, 0x51, 0x55, 0x55, 0x15, 0x54, 0x00, 0x00, 0x15, 0x54, 0x55, 0x55, 0x45, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x40, 0x00, 0x44, 0x11, 0x10, 0x11, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x44, 0x04, 0x44, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x40, 0x00, 0x44, 0x15, 0x05, 0x41, 0x50, 0x05, 0x55, 0x55, 0x50, 0x05, 0x41, 0x50, 0x54, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x50, 0x40, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x50, 0x40, 0x01, 0x00, 0x01, 0x00, 0x17, 0xfc, 0x3f, 0xfc, 0x00, 0x43, 0xff, 0xc0, 0x01, 0x00, 0x01, 0x00, 0x1f, 0xf4, 0xff, 0xd4, 0x00, 0x4f, 0xfc, 0x40, 0x01, 0x55, 0x55, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x40, 0x01, 0x11, 0x11, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x40, 0x01, 0x00, 0x01, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xc0, 0x01, 0x05, 0x41, 0x00, 0xf0, 0xfc, 0x03, 0xff, 0xff, 0x00, 0x00, 0xc0, 0x01, 0x05, 0x41, 0x00, 0xf0, 0xf3, 0x0c, 0x71, 0xc7, 0x33, 0x30, 0xc0, 0xaa, 0xaa, 0xaa, 0xaa, 0xf0, 0xf3, 0x0d, 0x75, 0xd7, 0x33, 0x30, 0xea, 0x55, 0x55, 0x55, 0x55, 0xf0, 0xfc, 0x0d, 0x34, 0xd3, 0x33, 0x30, 0xd5, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x0d, 0x34, 0xc3, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x03, 0xff, 0xff, 0xaa, 0xaa, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 0xc0, 0x00, 0xfc, 0x0f, 0xc0, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x3a, 0xbf, 0xfa, 0xab, 0xff, 0xbf, 0xfb, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0xff, 0xff, 0xcf, 0xfc, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf0, 0x03, 0xff, 0x3f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xc0, 0x00, 0xfc, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x55, 0x51, 0x55, 0x55, 0x15, 0x54, 0x00, 0x00, 0x15, 0x10, 0x00, 0x00, 0x40, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x40, 0x11, 0x10, 0x11, 0x10, 0x04, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x40, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x15, 0x55, 0x55, 0x40, 0x15, 0x05, 0x41, 0x50, 0x05, 0x55, 0x55, 0x50, 0x00, 0x00, 0x00, 0x00, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf5, 0xff, 0xf0, 0x00, 0x0f, 0xff, 0x00, 0x50, 0x50, 0x50, 0x50, 0x3f, 0xc3, 0xff, 0x00, 0x14, 0x3f, 0xf4, 0x14, 0x55, 0x50, 0x55, 0x50, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x54, 0x55, 0x50, 0x55, 0x50, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x54, 0x55, 0x55, 0x55, 0x53, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x54, 0x40, 0x10, 0x40, 0x13, 0xc3, 0xf0, 0x0f, 0xff, 0xfc, 0x00, 0x03, 0x04, 0x50, 0x50, 0x50, 0x53, 0xc3, 0xcc, 0x31, 0xc7, 0x1c, 0xcc, 0xc3, 0x14, 0x40, 0x10, 0x40, 0x13, 0xc3, 0xcc, 0x35, 0xd7, 0x5c, 0xcc, 0xc3, 0x04, 0xaa, 0xaa, 0xaa, 0xab, 0xc3, 0xf0, 0x34, 0xd3, 0x4c, 0xcc, 0xc3, 0xaa, 0x55, 0x55, 0x55, 0x57, 0x00, 0x00, 0x34, 0xd3, 0x0c, 0x00, 0x03, 0x55, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x0f, 0xff, 0xfe, 0xaa, 0xab, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x3f, 0x00, 0x03, 0xf0, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xea, 0xff, 0xea, 0xaf, 0xfe, 0xff, 0xec, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf3, 0xff, 0xff, 0x3f, 0xf3, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x0f, 0xfc, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x03, 0xf0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xfd, 0x7d, 0x7f, 0x5d, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x5d, 0xd5, 0xd7, 0x75, 0xdd, 0xd5, 0x55, 0x55, 0x55, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x30, 0xcc, 0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0xc0, 0xff, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xc0, 0xc3, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0x3f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xfc, 0x3f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x03, 0xc0, 0x30, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0xf3, 0xff, 0xff, 0xcf, 0x00, 0x00, 0x0f, 0xf0, 0x70, 0x0f, 0x55, 0x55, 0xc3, 0x0c, 0x30, 0xc3, 0x55, 0x55, 0xf0, 0x0d, 0xc3, 0x30, 0xd5, 0xff, 0x7c, 0xcf, 0xf3, 0x3d, 0xff, 0x57, 0x0c, 0xc3, 0xc0, 0x3f, 0x5f, 0x03, 0x57, 0xcf, 0xf3, 0xd5, 0xc0, 0xf5, 0xfc, 0x03, 0xc0, 0x30, 0xdc, 0x0d, 0x5f, 0xff, 0xff, 0xf5, 0x70, 0x37, 0x0c, 0x03, 0x7f, 0xff, 0x5f, 0xf5, 0x5f, 0x55, 0x55, 0xf5, 0x5f, 0xf5, 0xff, 0xfd, 0x30, 0x1f, 0xa4, 0x00, 0xa4, 0x01, 0x90, 0x00, 0x64, 0x06, 0x40, 0x1a, 0x00, 0x16, 0xa9, 0x40, 0x09, 0x00, 0x40, 0x00, 0x10, 0x01, 0x00, 0x60, 0x01, 0x6a, 0x2a, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xaa, 0x00, 0xa5, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x01, 0x6a, 0x80, 0x00, 0x01, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x30, 0xc0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x00, 0x05, 0x94, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x15, 0x56, 0xa5, 0x55, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x15, 0x40, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x29, 0x50, 0x15, 0x68, 0x00, 0x40, 0x07, 0xf0, 0x0f, 0xc0, 0x10, 0x00, 0x0a, 0xa5, 0x6a, 0x80, 0x01, 0x00, 0x1f, 0xfc, 0x3f, 0xf0, 0x04, 0x00, 0x00, 0xaa, 0xa8, 0x00, 0x15, 0x00, 0x1f, 0xff, 0xff, 0xf0, 0x05, 0x40, 0x00, 0x0a, 0xa0, 0x00, 0x04, 0x00, 0x5c, 0x00, 0x00, 0x30, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xf0, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xc0, 0x33, 0x00, 0x00, 0xcc, 0x03, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x30, 0x03, 0xc0, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x0c, 0x30, 0x03, 0xc0, 0x0c, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x3c, 0x03, 0xc0, 0x3c, 0xff, 0xc0, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0xc3, 0xff, 0xff, 0xc3, 0x00, 0x00, 0x0f, 0xf0, 0x30, 0x0c, 0x00, 0x00, 0xcc, 0x30, 0x0c, 0x33, 0x00, 0x00, 0x30, 0x0c, 0xc3, 0x0f, 0x00, 0x00, 0x3f, 0x3f, 0xfc, 0xfc, 0x00, 0x00, 0xf0, 0xc3, 0xc0, 0x30, 0xc0, 0x00, 0x03, 0x3f, 0xfc, 0xc0, 0x00, 0x03, 0x0c, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0xfc, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x3f, 0xfc, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x30, 0x30, 0xc0, 0x00, 0x00, 0x3c, 0x3c, 0x00, 0x00, 0x03, 0x0c, 0x0c, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x0c, 0x30, 0x00, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xfd, 0x7d, 0x7f, 0x5d, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x5d, 0xd5, 0xd7, 0x75, 0xdd, 0xd5, 0x55, 0x55, 0x55, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x30, 0xcc, 0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0xc0, 0xff, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xc0, 0xc3, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x70, 0x0f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xf0, 0x0d, 0xc3, 0x30, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x0c, 0xc3, 0xc0, 0x3f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfc, 0x03, 0xc0, 0x30, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x0c, 0x03, 0x7f, 0xff, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xfd, 0x30, 0x1f, 0xa4, 0x00, 0xa4, 0x01, 0x90, 0x00, 0x64, 0x06, 0x40, 0x1a, 0x00, 0x16, 0xa9, 0x40, 0x09, 0x00, 0x40, 0x00, 0x10, 0x01, 0x00, 0x60, 0x01, 0x6a, 0x2a, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xaa, 0x00, 0xa5, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x01, 0x6a, 0x80, 0x00, 0x01, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x30, 0xc0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x00, 0x05, 0x94, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x15, 0x56, 0xa5, 0x55, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x15, 0x40, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x29, 0x50, 0x15, 0x68, 0x00, 0x40, 0x04, 0x00, 0x04, 0x00, 0x10, 0x00, 0x0a, 0xa5, 0x6a, 0x80, 0x01, 0x00, 0x14, 0x00, 0x05, 0x00, 0x04, 0x00, 0x00, 0xaa, 0xa8, 0x00, 0x15, 0x00, 0x15, 0x00, 0x15, 0x00, 0x05, 0x40, 0x00, 0x0a, 0xa0, 0x00, 0x04, 0x00, 0x54, 0x00, 0x05, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x30, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0c, 0xc3, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xc3, 0xc0, 0x30, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x30, 0x30, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x0c, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xfc, 0x00, 0xc3, 0x0f, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xc3, 0x00, 0xc3, 0x30, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xcc, 0xc3, 0x00, 0xff, 0x30, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xfc, 0x00, 0xc3, 0x30, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xc0, 0x00, 0xc3, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x3f, 0x0f, 0xcf, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0xcc, 0x0c, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0xcf, 0xcf, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0x0f, 0xcf, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x30, 0xcc, 0x33, 0x0c, 0xfc, 0xfc, 0x00, 0x00, 0xc0, 0x00, 0x00, 0xc3, 0x30, 0xcf, 0x33, 0xcc, 0xc0, 0xc3, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc3, 0x30, 0xcc, 0xf3, 0x3c, 0xfc, 0xc3, 0x00, 0x00, 0xfc, 0x00, 0x00, 0xfc, 0x30, 0xcc, 0x33, 0x0c, 0xc0, 0xfc, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc3, 0x0f, 0x0c, 0x33, 0x0c, 0xfc, 0xc3, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x1f, 0x05, 0x55, 0x55, 0x55, 0x55, 0x55, 0x54, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x05, 0x54, 0x55, 0x45, 0x51, 0x10, 0x00, 0x04, 0x04, 0x55, 0x44, 0x51, 0x11, 0x55, 0x44, 0x04, 0x44, 0x44, 0x51, 0x11, 0x00, 0x44, 0x04, 0x44, 0x44, 0x51, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x00, 0x00, 0x00, 0x05, 0x41, 0x10, 0x00, 0x00, 0x00, 0x00, 0x04, 0x41, 0x10, 0x00, 0x00, 0x10, 0x55, 0x05, 0x41, 0x10, 0x54, 0x00, 0x55, 0x45, 0x10, 0x11, 0x11, 0x01, 0x40, 0x55, 0x54, 0x10, 0x11, 0x11, 0x00, 0x10, 0x55, 0x54, 0x15, 0x51, 0x11, 0x41, 0x11, 0x51, 0x10, 0x04, 0x41, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x50, 0x50, 0x00, 0x00, 0x10, 0x01, 0x10, 0x55, 0x50, 0x55, 0x00, 0x55, 0x01, 0x10, 0x44, 0x51, 0x00, 0x51, 0x00, 0x41, 0x10, 0x40, 0x11, 0x04, 0x41, 0x11, 0x41, 0x10, 0x15, 0x41, 0x00, 0x41, 0x00, 0x41, 0x10, 0x10, 0x41, 0x00, 0x40, 0x41, 0x01, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x55, 0x55, 0x55, 0x55, 0x55, 0x41, 0x10, 0x40, 0x00, 0x00, 0x00, 0x00, 0x41, 0x10, 0x55, 0x55, 0x55, 0x55, 0x55, 0x41, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x15, 0x50, 0x00, 0x00, 0x00, 0x01, 0x55, 0x12, 0x0c, 0x57, 0xf5, 0x7d, 0x55, 0x50, 0x5f, 0xfd, 0xff, 0x55, 0x50, 0x5f, 0xff, 0xff, 0x55, 0x50, 0x5f, 0xff, 0xff, 0xd5, 0x50, 0x7c, 0x00, 0x00, 0xd5, 0x50, 0x70, 0x0f, 0xc3, 0xd5, 0x50, 0x70, 0x33, 0xc3, 0xd5, 0x50, 0x70, 0x33, 0xc3, 0xd5, 0x50, 0x70, 0x0f, 0xc3, 0xd5, 0x50, 0x5c, 0x00, 0x0f, 0x55, 0x50, 0x57, 0xff, 0xfd, 0x55, 0x50, 0x5c, 0x3c, 0x33, 0x55, 0x50, 0x12, 0x0c, 0x55, 0xfd, 0x5f, 0x55, 0x50, 0x57, 0xff, 0x7f, 0xd5, 0x50, 0x57, 0xff, 0xff, 0xd5, 0x50, 0x57, 0xff, 0xff, 0xf5, 0x50, 0x5f, 0x00, 0x00, 0x35, 0x50, 0x5c, 0x03, 0xc0, 0x35, 0x50, 0x5c, 0x0c, 0x30, 0xf5, 0x50, 0x5c, 0x00, 0x00, 0x35, 0x50, 0x5c, 0x0c, 0x0f, 0xf5, 0x50, 0x57, 0x33, 0x0f, 0xd5, 0x50, 0x55, 0xf3, 0xff, 0x35, 0x50, 0x55, 0xc3, 0xc3, 0xf5, 0x50, 0x12, 0x0c, 0x5f, 0xd5, 0x7f, 0xff, 0xf0, 0x7f, 0xf5, 0xff, 0x00, 0x30, 0x7f, 0xff, 0xff, 0x00, 0x30, 0x7f, 0xff, 0xff, 0x00, 0x30, 0x70, 0x00, 0x03, 0x00, 0x30, 0xc3, 0xf0, 0x3f, 0x00, 0x30, 0xcc, 0xf0, 0xcf, 0x00, 0x30, 0xcc, 0xf0, 0xcf, 0x00, 0x30, 0xc3, 0xf0, 0x3f, 0xff, 0xf0, 0x70, 0x0f, 0x00, 0xcd, 0x50, 0x5f, 0xff, 0xff, 0x35, 0x50, 0x70, 0x30, 0x3c, 0xd5, 0x50, 0x12, 0x0c, 0x55, 0xfd, 0x57, 0xd5, 0x50, 0x57, 0xff, 0xdf, 0xf5, 0x50, 0x57, 0xff, 0xff, 0xfd, 0x50, 0x55, 0xff, 0xff, 0xfd, 0x50, 0x57, 0xc0, 0x00, 0x0d, 0x50, 0x57, 0x00, 0x00, 0x0d, 0x50, 0x57, 0x00, 0x00, 0x0d, 0x50, 0x57, 0x0f, 0xf0, 0x0d, 0x50, 0x57, 0x00, 0x00, 0xcd, 0x50, 0x55, 0xc0, 0x03, 0x35, 0x50, 0x55, 0x7f, 0xff, 0xd5, 0x50, 0x55, 0xc3, 0xc3, 0xd5, 0x50, 0x12, 0x0c, 0x57, 0xf5, 0x5f, 0xd5, 0x50, 0x5f, 0xfd, 0x7f, 0xf5, 0x50, 0x5f, 0xff, 0xff, 0xf5, 0x50, 0x5f, 0xff, 0xff, 0xf5, 0x50, 0x5c, 0x00, 0x00, 0x35, 0x50, 0x70, 0x00, 0x00, 0x0d, 0x50, 0x70, 0x30, 0x0c, 0x0d, 0x50, 0x70, 0xc0, 0x03, 0x0d, 0x50, 0x70, 0x03, 0xc0, 0x0d, 0x50, 0x5c, 0x0f, 0xf0, 0x35, 0x50, 0x57, 0xff, 0xff, 0xd5, 0x50, 0x55, 0xcc, 0x33, 0x55, 0x50, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfa, 0xaa, 0xab, 0xc0, 0xff, 0xe5, 0x55, 0x5a, 0xc0, 0xff, 0xe5, 0x55, 0x5a, 0xc0, 0xff, 0x95, 0x55, 0x66, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0xaa, 0xaa, 0xab, 0xc0, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfe, 0xaa, 0xaa, 0xc0, 0xff, 0xfe, 0x55, 0x56, 0xc0, 0xff, 0xfe, 0x55, 0x56, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xea, 0xaa, 0xaa, 0xc0, 0xff, 0xea, 0xaa, 0xaa, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0xaa, 0xaa, 0xab, 0xc0, 0x08, 0x08, 0x7f, 0xf5, 0xff, 0xfd, 0xc3, 0x0d, 0xff, 0xfd, 0xff, 0xfd, 0xfc, 0xfd, 0x7f, 0xf5, 0x77, 0x75, 0x10, 0x03, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xc0, 0x03, 0x03, 0xff, 0xff, 0xff, 0xff, 0x10, 0x03, 0x55, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x03, 0x55, 0x55, 0xff, 0xff, 0x55, 0x08, 0x08, 0x55, 0x75, 0x55, 0x75, 0x55, 0x75, 0x5f, 0x75, 0x70, 0xf5, 0x70, 0xd5, 0x5f, 0x55, 0x55, 0x55, 0x08, 0x08, 0x55, 0x75, 0x55, 0x75, 0x55, 0x75, 0x5f, 0x75, 0x7f, 0xf5, 0x7f, 0xd5, 0x5f, 0x55, 0x55, 0x55, 0x08, 0x08, 0x55, 0xd5, 0x55, 0xf5, 0x55, 0xfd, 0x7d, 0xdd, 0xff, 0xd5, 0xff, 0x55, 0x7d, 0x55, 0x55, 0x55, 0x08, 0x08, 0x5f, 0xfd, 0x5d, 0x5d, 0x5d, 0x5d, 0x5d, 0x5d, 0xfd, 0xfd, 0xfd, 0xfd, 0xf5, 0xf5, 0x55, 0x55, 0x01, 0x01, 0x00, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x7f, 0xfd, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x5f, 0xfd, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x7f, 0xfd, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x5f, 0xfd, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x7f, 0xfd, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0x03, 0x5f, 0xfd, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x08, 0x08, 0x50, 0x05, 0x43, 0xc1, 0x00, 0x00, 0x30, 0xcc, 0x33, 0x0c, 0x00, 0x00, 0x43, 0xc1, 0x50, 0x05, 0x08, 0x08, 0xc0, 0x03, 0x33, 0xcc, 0x00, 0x30, 0x33, 0x0c, 0x30, 0xcc, 0x0c, 0x00, 0x33, 0xcc, 0xc0, 0x03, 0x08, 0x08, 0x57, 0xd5, 0x5c, 0x35, 0x5c, 0x35, 0xdc, 0x37, 0xd7, 0xd7, 0xdf, 0xf7, 0xfd, 0x7f, 0xf7, 0xdf, 0x04, 0x1f, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x02, 0x05, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0x06, 0x20, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0x20, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf7, 0xff, 0x5f, 0x5f, 0xd7, 0xff, 0x75, 0x5d, 0x55, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x57, 0xd5, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x55, 0x75, 0x75, 0x7f, 0xdf, 0xd5, 0x75, 0x75, 0x55, 0x75, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x55, 0x5f, 0xd5, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x08, 0x7f, 0x5f, 0x57, 0xd7, 0x57, 0xd5, 0x75, 0xdd, 0x77, 0x57, 0xdf, 0x75, 0xdd, 0x77, 0x57, 0xd7, 0x75, 0xdf, 0xf7, 0x55, 0x7d, 0x5f, 0x5d, 0x77, 0xf7, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x0c, 0x7f, 0x5f, 0x5d, 0x5d, 0xfd, 0xd5, 0x75, 0xdf, 0x7d, 0xd5, 0xdf, 0x75, 0xdf, 0xfd, 0xfd, 0xd7, 0x7f, 0xdd, 0xdd, 0xd5, 0x7f, 0x75, 0xdd, 0x5d, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7d, 0x75, 0x77, 0xf7, 0xf5, 0xd7, 0x75, 0x77, 0x57, 0x5d, 0xd7, 0x5d, 0xd7, 0xf7, 0x5d, 0xd7, 0x5d, 0xd7, 0x57, 0xf5, 0x7d, 0x57, 0x57, 0xf7, 0x5d, 0x55, 0x55, 0x55, 0x55, 0x55, 0x20, 0x0c, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xff, 0x55, 0xc3, 0x7d, 0x55, 0x55, 0x55, 0x70, 0x00, 0xd5, 0x70, 0xff, 0x55, 0x55, 0x55, 0xc0, 0x00, 0x35, 0x7c, 0x3f, 0xd5, 0x55, 0x57, 0x00, 0x03, 0x0d, 0x5f, 0xff, 0xff, 0xff, 0xfc, 0x03, 0x00, 0x0d, 0x70, 0x00, 0x03, 0xc0, 0x00, 0x00, 0x3f, 0xfd, 0x7f, 0xff, 0xfc, 0x30, 0x00, 0x00, 0xc0, 0x03, 0xc0, 0x00, 0x03, 0x30, 0x00, 0x03, 0x0f, 0xfc, 0xc0, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc0, 0x03, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x01, 0x01, 0x00, 0x10, 0x10, 0x55, 0x7d, 0x55, 0xf5, 0x55, 0xc3, 0x57, 0x0d, 0x55, 0xc0, 0xdc, 0x0d, 0x55, 0x70, 0xdc, 0x3d, 0x55, 0x5c, 0x30, 0x35, 0x55, 0x70, 0x00, 0xd5, 0x55, 0xc3, 0xfc, 0xd5, 0x55, 0xcf, 0xff, 0x35, 0x57, 0x0f, 0xff, 0x35, 0x57, 0x00, 0xfc, 0x35, 0x57, 0xc0 }; //uint8_t v[] = { 0x0a, 0xaa, 0x55, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x55, 0x03, 0x03, 0x03, 0x00, 0x00, 0x10, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0xc4, 0x00, 0x00, 0xdc, 0x00, 0x00, 0x0f, 0x01, 0x00, 0x91, 0x01, 0x00, 0x0d, 0x02, 0x00, 0x89, 0x02, 0x00, 0xd1, 0x02, 0x00, 0x1f, 0x06, 0x00, 0x67, 0x0f, 0x00, 0x67, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x12, 0x00, 0xa7, 0x12, 0x00, 0x0d, 0x13, 0x00, 0x73, 0x13, 0x00, 0xd9, 0x13, 0x00, 0x3f, 0x14, 0x00, 0xa5, 0x14, 0x00, 0x0b, 0x15, 0x00, 0x71, 0x15, 0x00, 0xd7, 0x15, 0x00, 0x3d, 0x16, 0x00, 0xa3, 0x16, 0x00, 0x09, 0x17, 0x00, 0x6f, 0x17, 0x00, 0xd5, 0x17, 0x00, 0x3b, 0x18, 0x00, 0xa1, 0x18, 0x00, 0x07, 0x19, 0x00, 0x6d, 0x19, 0x00, 0xd3, 0x19, 0x00, 0x39, 0x1a, 0x00, 0x9f, 0x1a, 0x00, 0x05, 0x1b, 0x00, 0x6b, 0x1b, 0x00, 0xd1, 0x1b, 0x00, 0x37, 0x1c, 0x00, 0x9d, 0x1c, 0x00, 0x13, 0x1e, 0x00, 0x89, 0x1f, 0x00, 0xff, 0x20, 0x00, 0x75, 0x22, 0x00, 0xeb, 0x23, 0x00, 0x61, 0x25, 0x00, 0xd7, 0x26, 0x00, 0x4d, 0x28, 0x00, 0xeb, 0x28, 0x00, 0x89, 0x29, 0x00, 0x64, 0x2a, 0x00, 0xa2, 0x2a, 0x00, 0xe0, 0x2a, 0x00, 0x1e, 0x2b, 0x00, 0x5c, 0x2b, 0x00, 0xce, 0x00, 0x00, 0xf1, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x44, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};// 0x70, 0x2c, 0x00, 0x82, 0x2c, 0x00, 0x90, 0x2c, 0x00, 0x9e, 0x2c, 0x00, 0xb0, 0x2c, 0x00, 0xc2, 0x2c, 0x00, 0xd4, 0x2c, 0x00, 0xe6, 0x2c, 0x00, 0xe9, 0x2c, 0x00, 0x1b, 0x2d, 0x00, 0x4d, 0x2d, 0x00, 0x7f, 0x2d, 0x00, 0xb1, 0x2d, 0x00, 0xe3, 0x2d, 0x00, 0x15, 0x2e, 0x00, 0x27, 0x2e, 0x00, 0x39, 0x2e, 0x00, 0x4b, 0x2e, 0x00, 0x6c, 0x2e, 0x00, 0x73, 0x2e, 0x00, 0xb5, 0x2e, 0x00, 0xf7, 0x2e, 0x00, 0x21, 0x2f, 0x00, 0x5f, 0x2f, 0x00, 0xc1, 0x2f, 0x00, 0x02, 0x00, 0x06, 0x03, 0x04, 0x09, 0x0a, 0x05, 0x08, 0x07, 0x00, 0x00, 0x58, 0x00, 0x00, 0x32, 0x00, 0x00, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x10, 0x00, 0x00, 0x08, 0x00, 0x00, 0x50, 0x04, 0x00, 0x30, 0x02, 0x00, 0x20, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00, 0x50, 0x08, 0x00, 0x50, 0x11, 0x00, 0x00, 0x00, 0x28, 0x00, 0x40, 0x15, 0x00, 0x60, 0x12, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x45, 0x00, 0x00, 0x35, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x22, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00, 0x22, 0x00, 0x00, 0x13, 0x00, 0x01, 0x00, 0x02, 0x00, 0x50, 0x01, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x04, 0xff, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x02, 0xff, 0x01, 0x01, 0x00, 0x1e, 0x01, 0x00, 0x03, 0xff, 0x01, 0x01, 0x00, 0x2d, 0x01, 0x00, 0x04, 0xfe, 0x01, 0x01, 0x00, 0x3c, 0x01, 0x00, 0x05, 0xfe, 0x01, 0x01, 0x00, 0x4b, 0x02, 0x00, 0x06, 0xfe, 0x02, 0x02, 0x00, 0x5a, 0x02, 0x00, 0x07, 0xfd, 0x02, 0x02, 0x00, 0x63, 0x02, 0x00, 0x08, 0xfd, 0x02, 0x02, 0x00, 0x64, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0x00, 0x02, 0x04, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x02, 0xff, 0x01, 0x01, 0x00, 0x0f, 0x01, 0x00, 0x03, 0xff, 0x01, 0x01, 0x00, 0x19, 0x01, 0x00, 0x04, 0xfe, 0x01, 0x01, 0x00, 0x23, 0x01, 0x00, 0x05, 0xfe, 0x01, 0x02, 0x00, 0x2d, 0x02, 0x00, 0x06, 0xfe, 0x02, 0x02, 0x00, 0x37, 0x02, 0x00, 0x07, 0xfd, 0x02, 0x02, 0x00, 0x40, 0x02, 0x00, 0x08, 0xfd, 0x02, 0x02, 0x00, 0x41, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xc4, 0x2f, 0x00, 0xff, 0xff, 0xff, 0x06, 0x30, 0x00, 0x48, 0x30, 0x00, 0x8a, 0x30, 0x00, 0xcc, 0x30, 0x00, 0x0e, 0x31, 0x00, 0x50, 0x31, 0x00, 0x92, 0x31, 0x00, 0xd4, 0x31, 0x00, 0x16, 0x32, 0x00, 0xff, 0xff, 0xff, 0x58, 0x32, 0x00, 0xff, 0xff, 0xff, 0xba, 0x32, 0x00, 0x1c, 0x33, 0x00, 0x7e, 0x33, 0x00, 0xe0, 0x33, 0x00, 0x42, 0x34, 0x00, 0xa4, 0x34, 0x00, 0x06, 0x35, 0x00, 0x68, 0x35, 0x00, 0xca, 0x35, 0x00, 0xff, 0xff, 0xff, 0x2c, 0x36, 0x00, 0x3e, 0x36, 0x00, 0x80, 0x36, 0x00, 0xc2, 0x36, 0x00, 0x04, 0x37, 0x00, 0x46, 0x37, 0x00, 0x88, 0x37, 0x00, 0xca, 0x37, 0x00, 0x24, 0x38, 0x00, 0x9d, 0x38, 0x00, 0xf9, 0x38, 0x00, 0x7d, 0x39, 0x00, 0xd7, 0x39, 0x00, 0x50, 0x3a, 0x00, 0xac, 0x3a, 0x00, 0x30, 0x3b, 0x00, 0x72, 0x3b, 0x00, 0xb4, 0x3b, 0x00, 0xf6, 0x3b, 0x00, 0x38, 0x3c, 0x00, 0x7a, 0x3c, 0x00, 0xbc, 0x3c, 0x00, 0xfe, 0x3c, 0x00, 0x40, 0x3d, 0x00, 0x3a, 0x3e, 0x00, 0x34, 0x3f, 0x00, 0x2e, 0x40, 0x00, 0x28, 0x41, 0x00, 0x22, 0x42, 0x00, 0x98, 0x43, 0x00, 0xea, 0x43, 0x00, 0x3c, 0x44, 0x00, 0x8e, 0x44, 0x00, 0xe0, 0x44, 0x00, 0x32, 0x45, 0x00, 0x84, 0x45, 0x00, 0x7e, 0x46, 0x00, 0x78, 0x47, 0x00, 0xba, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0x76, 0x48, 0x00, 0xf0, 0x48, 0x00, 0x6a, 0x49, 0x00, 0xe4, 0x49, 0x00, 0x5e, 0x4a, 0x00, 0xd8, 0x4a, 0x00, 0x52, 0x4b, 0x00, 0xcc, 0x4b, 0x00, 0x46, 0x4c, 0x00, 0xc0, 0x4c, 0x00, 0x3a, 0x4d, 0x00, 0xb4, 0x4d, 0x00, 0x2e, 0x4e, 0x00, 0xa8, 0x4e, 0x00, 0x22, 0x4f, 0x00, 0x9c, 0x4f, 0x00, 0x16, 0x50, 0x00, 0x90, 0x50, 0x00, 0x0a, 0x51, 0x00, 0x84, 0x51, 0x00, 0xfe, 0x51, 0x00, 0x78, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0x6c, 0x53, 0x00, 0xe6, 0x53, 0x00, 0x60, 0x54, 0x00, 0xda, 0x54, 0x00, 0x54, 0x55, 0x00, 0xce, 0x55, 0x00, 0x48, 0x56, 0x00, 0xc2, 0x56, 0x00, 0x3c, 0x57, 0x00, 0xb6, 0x57, 0x00, 0x30, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0x24, 0x59, 0x00, 0x9e, 0x59, 0x00, 0x18, 0x5a, 0x00, 0x92, 0x5a, 0x00, 0x0c, 0x5b, 0x00, 0x86, 0x5b, 0x00, 0x00, 0x5c, 0x00, 0x7a, 0x5c, 0x00, 0xf4, 0x5c, 0x00, 0x6e, 0x5d, 0x00, 0xe8, 0x5d, 0x00, 0x62, 0x5e, 0x00, 0xdc, 0x5e, 0x00, 0x56, 0x5f, 0x00, 0xd0, 0x5f, 0x00, 0x4a, 0x60, 0x00, 0xc4, 0x60, 0x00, 0x3e, 0x61, 0x00, 0xb8, 0x61, 0x00, 0x32, 0x62, 0x00, 0xac, 0x62, 0x00, 0x26, 0x63, 0x00, 0xa0, 0x63, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x94, 0x64, 0x00, 0x0e, 0x65, 0x00, 0x88, 0x65, 0x00, 0x02, 0x66, 0x00, 0x7c, 0x66, 0x00, 0xf6, 0x66, 0x00, 0x70, 0x67, 0x00, 0xea, 0x67, 0x00, 0x64, 0x68, 0x00, 0xde, 0x68, 0x00, 0x58, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0x4c, 0x6a, 0x00, 0xc6, 0x6a, 0x00, 0x40, 0x6b, 0x00, 0xba, 0x6b, 0x00, 0x34, 0x6c, 0x00, 0xae, 0x6c, 0x00, 0x28, 0x6d, 0x00, 0xa2, 0x6d, 0x00, 0x1c, 0x6e, 0x00, 0x96, 0x6e, 0x00, 0x10, 0x6f, 0x00, 0x8a, 0x6f, 0x00, 0x04, 0x70, 0x00, 0x7e, 0x70, 0x00, 0xf8, 0x70, 0x00, 0x72, 0x71, 0x00, 0xec, 0x71, 0x00, 0x66, 0x72, 0x00, 0xe0, 0x72, 0x00, 0x5a, 0x73, 0x00, 0xd4, 0x73, 0x00, 0x4e, 0x74, 0x00, 0xc8, 0x74, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0xbc, 0x75, 0x00, 0x36, 0x76, 0x00, 0xb0, 0x76, 0x00, 0x2a, 0x77, 0x00, 0xa4, 0x77, 0x00, 0x1e, 0x78, 0x00, 0x98, 0x78, 0x00, 0x12, 0x79, 0x00, 0x8c, 0x79, 0x00, 0x06, 0x7a, 0x00, 0x80, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0x74, 0x7b, 0x00, 0xe2, 0x7b, 0x00, 0x50, 0x7c, 0x00, 0xbe, 0x7c, 0x00, 0x2c, 0x7d, 0x00, 0x9a, 0x7d, 0x00, 0x08, 0x7e, 0x00, 0x76, 0x7e, 0x00, 0xe4, 0x7e, 0x00, 0x52, 0x7f, 0x00, 0xc0, 0x7f, 0x00, 0x2e, 0x80, 0x00, 0x9c, 0x80, 0x00, 0x0a, 0x81, 0x00, 0x78, 0x81, 0x00, 0xe6, 0x81, 0x00, 0x54, 0x82, 0x00, 0xc2, 0x82, 0x00, 0x30, 0x83, 0x00, 0x9e, 0x83, 0x00, 0x0c, 0x84, 0x00, 0x7a, 0x84, 0x00, 0xe8, 0x84, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0xc4, 0x85, 0x00, 0x32, 0x86, 0x00, 0xa0, 0x86, 0x00, 0x0e, 0x87, 0x00, 0x7c, 0x87, 0x00, 0xea, 0x87, 0x00, 0x58, 0x88, 0x00, 0xc6, 0x88, 0x00, 0x34, 0x89, 0x00, 0xa2, 0x89, 0x00, 0x10, 0x8a, 0x00, 0x7e, 0x8a, 0x00, 0xec, 0x8a, 0x00, 0x2e, 0x8b, 0x00, 0xac, 0x8b, 0x00, 0x2a, 0x8c, 0x00, 0xa8, 0x8c, 0x00, 0x26, 0x8d, 0x00, 0xa4, 0x8d, 0x00, 0x22, 0x8e, 0x00, 0xa0, 0x8e, 0x00, 0x1e, 0x8f, 0x00, 0x60, 0x8f, 0x00, 0xa2, 0x8f, 0x00, 0xe4, 0x8f, 0x00, 0x13, 0x90, 0x00, 0x42, 0x90, 0x00, 0x65, 0x90, 0x00, 0x88, 0x90, 0x00, 0xab, 0x90, 0x00, 0xce, 0x90, 0x00, 0xf1, 0x90, 0x00, 0x57, 0x91, 0x00, 0xbd, 0x91, 0x00, 0x23, 0x92, 0x00, 0x89, 0x92, 0x00, 0xef, 0x92, 0x00, 0x55, 0x93, 0x00, 0xbb, 0x93, 0x00, 0x21, 0x94, 0x00, 0x87, 0x94, 0x00, 0xed, 0x94, 0x00, 0x53, 0x95, 0x00, 0xb9, 0x95, 0x00, 0x1f, 0x96, 0x00, 0x85, 0x96, 0x00, 0xeb, 0x96, 0x00, 0x51, 0x97, 0x00, 0xb7, 0x97, 0x00, 0x1d, 0x98, 0x00, 0x83, 0x98, 0x00, 0xe9, 0x98, 0x00, 0x4f, 0x99, 0x00, 0xb5, 0x99, 0x00, 0x1b, 0x9a, 0x00, 0x81, 0x9a, 0x00, 0xe7, 0x9a, 0x00, 0x4d, 0x9b, 0x00, 0xb3, 0x9b, 0x00, 0x19, 0x9c, 0x00, 0x7f, 0x9c, 0x00, 0xe5, 0x9c, 0x00, 0x4b, 0x9d, 0x00, 0xb1, 0x9d, 0x00, 0x17, 0x9e, 0x00, 0x7d, 0x9e, 0x00, 0xe3, 0x9e, 0x00, 0x49, 0x9f, 0x00, 0xaf, 0x9f, 0x00, 0x15, 0xa0, 0x00, 0x7b, 0xa0, 0x00, 0xe1, 0xa0, 0x00, 0x47, 0xa1, 0x00, 0xad, 0xa1, 0x00, 0x13, 0xa2, 0x00, 0x79, 0xa2, 0x00, 0xdf, 0xa2, 0x00, 0x45, 0xa3, 0x00, 0xab, 0xa3, 0x00, 0x11, 0xa4, 0x00, 0x77, 0xa4, 0x00, 0xdd, 0xa4, 0x00, 0x43, 0xa5, 0x00, 0xa9, 0xa5, 0x00, 0x0f, 0xa6, 0x00, 0x75, 0xa6, 0x00, 0xdb, 0xa6, 0x00, 0x41, 0xa7, 0x00, 0xa7, 0xa7, 0x00, 0x0d, 0xa8, 0x00, 0x73, 0xa8, 0x00, 0xd9, 0xa8, 0x00, 0x3f, 0xa9, 0x00, 0xa5, 0xa9, 0x00, 0x0b, 0xaa, 0x00, 0x71, 0xaa, 0x00, 0xd7, 0xaa, 0x00, 0x3d, 0xab, 0x00, 0xa3, 0xab, 0x00, 0x09, 0xac, 0x00, 0x6f, 0xac, 0x00, 0xd5, 0xac, 0x00, 0x3b, 0xad, 0x00, 0xa1, 0xad, 0x00, 0x07, 0xae, 0x00, 0x6d, 0xae, 0x00, 0xd3, 0xae, 0x00, 0x39, 0xaf, 0x00, 0x9f, 0xaf, 0x00, 0x05, 0xb0, 0x00, 0x6b, 0xb0, 0x00, 0xd1, 0xb0, 0x00, 0x37, 0xb1, 0x00, 0x9d, 0xb1, 0x00, 0x03, 0xb2, 0x00, 0x69, 0xb2, 0x00, 0xcf, 0xb2, 0x00, 0x35, 0xb3, 0x00, 0x9b, 0xb3, 0x00, 0x01, 0xb4, 0x00, 0x67, 0xb4, 0x00, 0xcd, 0xb4, 0x00, 0x33, 0xb5, 0x00, 0x99, 0xb5, 0x00, 0xff, 0xb5, 0x00, 0x65, 0xb6, 0x00, 0xcb, 0xb6, 0x00, 0x31, 0xb7, 0x00, 0x97, 0xb7, 0x00, 0xfd, 0xb7, 0x00, 0x63, 0xb8, 0x00, 0xc9, 0xb8, 0x00, 0x2f, 0xb9, 0x00, 0x95, 0xb9, 0x00, 0xfb, 0xb9, 0x00, 0x61, 0xba, 0x00, 0xc7, 0xba, 0x00, 0x2d, 0xbb, 0x00, 0x93, 0xbb, 0x00, 0xf9, 0xbb, 0x00, 0x5f, 0xbc, 0x00, 0xc5, 0xbc, 0x00, 0x2b, 0xbd, 0x00, 0x91, 0xbd, 0x00, 0xf7, 0xbd, 0x00, 0x5d, 0xbe, 0x00, 0xc3, 0xbe, 0x00, 0x29, 0xbf, 0x00, 0x8f, 0xbf, 0x00, 0xf5, 0xbf, 0x00, 0x5b, 0xc0, 0x00, 0xc1, 0xc0, 0x00, 0x27, 0xc1, 0x00, 0x8d, 0xc1, 0x00, 0xf3, 0xc1, 0x00, 0x59, 0xc2, 0x00, 0xbf, 0xc2, 0x00, 0x25, 0xc3, 0x00, 0x8b, 0xc3, 0x00, 0xf1, 0xc3, 0x00, 0x57, 0xc4, 0x00, 0xbd, 0xc4, 0x00, 0x23, 0xc5, 0x00, 0x89, 0xc5, 0x00, 0xef, 0xc5, 0x00, 0x55, 0xc6, 0x00, 0xbb, 0xc6, 0x00, 0x21, 0xc7, 0x00, 0x87, 0xc7, 0x00, 0xed, 0xc7, 0x00, 0x53, 0xc8, 0x00, 0xb9, 0xc8, 0x00, 0x1f, 0xc9, 0x00, 0x85, 0xc9, 0x00, 0xeb, 0xc9, 0x00, 0x51, 0xca, 0x00, 0xb7, 0xca, 0x00, 0x1d, 0xcb, 0x00, 0x83, 0xcb, 0x00, 0xe9, 0xcb, 0x00, 0x4f, 0xcc, 0x00, 0xb5, 0xcc, 0x00, 0x1b, 0xcd, 0x00, 0x81, 0xcd, 0x00, 0xe7, 0xcd, 0x00, 0x4d, 0xce, 0x00, 0xb3, 0xce, 0x00, 0x19, 0xcf, 0x00, 0x7f, 0xcf, 0x00, 0xe5, 0xcf, 0x00, 0x4b, 0xd0, 0x00, 0xb1, 0xd0, 0x00, 0x17, 0xd1, 0x00, 0x7d, 0xd1, 0x00, 0xe3, 0xd1, 0x00, 0x49, 0xd2, 0x00, 0xaf, 0xd2, 0x00, 0x15, 0xd3, 0x00, 0x7b, 0xd3, 0x00, 0xe1, 0xd3, 0x00, 0x47, 0xd4, 0x00, 0xad, 0xd4, 0x00, 0x13, 0xd5, 0x00, 0x79, 0xd5, 0x00, 0xdf, 0xd5, 0x00, 0x45, 0xd6, 0x00, 0xab, 0xd6, 0x00, 0x11, 0xd7, 0x00, 0x77, 0xd7, 0x00, 0xdd, 0xd7, 0x00, 0x43, 0xd8, 0x00, 0xa9, 0xd8, 0x00, 0x0f, 0xd9, 0x00, 0x75, 0xd9, 0x00, 0xdb, 0xd9, 0x00, 0x41, 0xda, 0x00, 0xa7, 0xda, 0x00, 0x0d, 0xdb, 0x00, 0x73, 0xdb, 0x00, 0xd9, 0xdb, 0x00, 0x3f, 0xdc, 0x00, 0xa5, 0xdc, 0x00, 0x0b, 0xdd, 0x00, 0x71, 0xdd, 0x00, 0xd7, 0xdd, 0x00, 0x3d, 0xde, 0x00, 0xa3, 0xde, 0x00, 0x09, 0xdf, 0x00, 0x6f, 0xdf, 0x00, 0xd5, 0xdf, 0x00, 0x3b, 0xe0, 0x00, 0xa1, 0xe0, 0x00, 0x07, 0xe1, 0x00, 0x6d, 0xe1, 0x00, 0xd3, 0xe1, 0x00, 0x39, 0xe2, 0x00, 0x9f, 0xe2, 0x00, 0x05, 0xe3, 0x00, 0x6b, 0xe3, 0x00, 0xd1, 0xe3, 0x00, 0x37, 0xe4, 0x00, 0x9d, 0xe4, 0x00, 0x03, 0xe5, 0x00, 0x69, 0xe5, 0x00, 0xcf, 0xe5, 0x00, 0x35, 0xe6, 0x00, 0x9b, 0xe6, 0x00, 0x01, 0xe7, 0x00, 0x67, 0xe7, 0x00, 0xcd, 0xe7, 0x00, 0x33, 0xe8, 0x00, 0x99, 0xe8, 0x00, 0xff, 0xe8, 0x00, 0x65, 0xe9, 0x00, 0xcb, 0xe9, 0x00, 0x31, 0xea, 0x00, 0x97, 0xea, 0x00, 0xfd, 0xea, 0x00, 0x63, 0xeb, 0x00, 0xc9, 0xeb, 0x00, 0x2f, 0xec, 0x00, 0x95, 0xec, 0x00, 0xfb, 0xec, 0x00, 0x61, 0xed, 0x00, 0xc7, 0xed, 0x00, 0x2d, 0xee, 0x00, 0x93, 0xee, 0x00, 0xf9, 0xee, 0x00, 0x5f, 0xef, 0x00, 0xc5, 0xef, 0x00, 0x2b, 0xf0, 0x00, 0x91, 0xf0, 0x00, 0xf7, 0xf0, 0x00, 0x5d, 0xf1, 0x00, 0xc3, 0xf1, 0x00, 0x29, 0xf2, 0x00, 0x8f, 0xf2, 0x00, 0xf5, 0xf2, 0x00, 0x5b, 0xf3, 0x00, 0xc1, 0xf3, 0x00, 0x27, 0xf4, 0x00, 0x8d, 0xf4, 0x00, 0xf3, 0xf4, 0x00, 0x59, 0xf5, 0x00, 0xbf, 0xf5, 0x00, 0x25, 0xf6, 0x00, 0x8b, 0xf6, 0x00, 0xf1, 0xf6, 0x00, 0x57, 0xf7, 0x00, 0xbd, 0xf7, 0x00, 0x23, 0xf8, 0x00, 0x89, 0xf8, 0x00, 0xef, 0xf8, 0x00, 0x55, 0xf9, 0x00, 0xbb, 0xf9, 0x00, 0x21, 0xfa, 0x00, 0x87, 0xfa, 0x00, 0xed, 0xfa, 0x00, 0x53, 0xfb, 0x00, 0xb9, 0xfb, 0x00, 0x1f, 0xfc, 0x00, 0x85, 0xfc, 0x00, 0xeb, 0xfc, 0x00, 0x51, 0xfd, 0x00, 0xb7, 0xfd, 0x00, 0x1d, 0xfe, 0x00, 0x83, 0xfe, 0x00, 0xe9, 0xfe, 0x00, 0x4f, 0xff, 0x00, 0xb5, 0xff, 0x00, 0x1b, 0x00, 0x01, 0x81, 0x00, 0x01, 0xe7, 0x00, 0x01, 0x4d, 0x01, 0x01, 0xb3, 0x01, 0x01, 0x19, 0x02, 0x01, 0x7f, 0x02, 0x01, 0xe5, 0x02, 0x01, 0x4b, 0x03, 0x01, 0xb1, 0x03, 0x01, 0x17, 0x04, 0x01, 0x7d, 0x04, 0x01, 0xe3, 0x04, 0x01, 0x49, 0x05, 0x01, 0xaf, 0x05, 0x01, 0x15, 0x06, 0x01, 0x7b, 0x06, 0x01, 0xe1, 0x06, 0x01, 0x47, 0x07, 0x01, 0xad, 0x07, 0x01, 0x13, 0x08, 0x01, 0x79, 0x08, 0x01, 0xdf, 0x08, 0x01, 0x45, 0x09, 0x01, 0xab, 0x09, 0x01, 0x11, 0x0a, 0x01, 0x77, 0x0a, 0x01, 0xdd, 0x0a, 0x01, 0x43, 0x0b, 0x01, 0xa9, 0x0b, 0x01, 0x0f, 0x0c, 0x01, 0x75, 0x0c, 0x01, 0xdb, 0x0c, 0x01, 0x41, 0x0d, 0x01, 0xa7, 0x0d, 0x01, 0x0d, 0x0e, 0x01, 0x73, 0x0e, 0x01, 0xd9, 0x0e, 0x01, 0x3f, 0x0f, 0x01, 0xa5, 0x0f, 0x01, 0x0b, 0x10, 0x01, 0x71, 0x10, 0x01, 0xd7, 0x10, 0x01, 0x3d, 0x11, 0x01, 0xa3, 0x11, 0x01, 0x09, 0x12, 0x01, 0x6f, 0x12, 0x01, 0xd5, 0x12, 0x01, 0x3b, 0x13, 0x01, 0xa1, 0x13, 0x01, 0x07, 0x14, 0x01, 0x6d, 0x14, 0x01, 0xd3, 0x14, 0x01, 0x39, 0x15, 0x01, 0x9f, 0x15, 0x01, 0x05, 0x16, 0x01, 0x6b, 0x16, 0x01, 0xd1, 0x16, 0x01, 0x37, 0x17, 0x01, 0x9d, 0x17, 0x01, 0x03, 0x18, 0x01, 0x69, 0x18, 0x01, 0xcf, 0x18, 0x01, 0x35, 0x19, 0x01, 0x9b, 0x19, 0x01, 0x01, 0x1a, 0x01, 0x67, 0x1a, 0x01, 0xcd, 0x1a, 0x01, 0x33, 0x1b, 0x01, 0x99, 0x1b, 0x01, 0xff, 0x1b, 0x01, 0x65, 0x1c, 0x01, 0xcb, 0x1c, 0x01, 0x31, 0x1d, 0x01, 0x97, 0x1d, 0x01, 0xfd, 0x1d, 0x01, 0x63, 0x1e, 0x01, 0xc9, 0x1e, 0x01, 0x2f, 0x1f, 0x01, 0x95, 0x1f, 0x01, 0xfb, 0x1f, 0x01, 0x61, 0x20, 0x01, 0xc7, 0x20, 0x01, 0x2d, 0x21, 0x01, 0x93, 0x21, 0x01, 0xf9, 0x21, 0x01, 0x5f, 0x22, 0x01, 0xc5, 0x22, 0x01, 0x2b, 0x23, 0x01, 0x91, 0x23, 0x01, 0xf7, 0x23, 0x01, 0x5d, 0x24, 0x01, 0xc3, 0x24, 0x01, 0x29, 0x25, 0x01, 0x8f, 0x25, 0x01, 0xf5, 0x25, 0x01, 0x5b, 0x26, 0x01, 0xc1, 0x26, 0x01, 0x27, 0x27, 0x01, 0x8d, 0x27, 0x01, 0xf3, 0x27, 0x01, 0x59, 0x28, 0x01, 0xbf, 0x28, 0x01, 0x25, 0x29, 0x01, 0x8b, 0x29, 0x01, 0xf1, 0x29, 0x01, 0x57, 0x2a, 0x01, 0xbd, 0x2a, 0x01, 0x23, 0x2b, 0x01, 0x89, 0x2b, 0x01, 0xef, 0x2b, 0x01, 0x55, 0x2c, 0x01, 0xbb, 0x2c, 0x01, 0x21, 0x2d, 0x01, 0x87, 0x2d, 0x01, 0xed, 0x2d, 0x01, 0x53, 0x2e, 0x01, 0xb9, 0x2e, 0x01, 0x1f, 0x2f, 0x01, 0x85, 0x2f, 0x01, 0xeb, 0x2f, 0x01, 0x51, 0x30, 0x01, 0xb7, 0x30, 0x01, 0x1d, 0x31, 0x01, 0x83, 0x31, 0x01, 0xe9, 0x31, 0x01, 0x4f, 0x32, 0x01, 0xb5, 0x32, 0x01, 0x1b, 0x33, 0x01, 0x81, 0x33, 0x01, 0xe7, 0x33, 0x01, 0x4d, 0x34, 0x01, 0xb3, 0x34, 0x01, 0x19, 0x35, 0x01, 0x7f, 0x35, 0x01, 0xe5, 0x35, 0x01, 0x4b, 0x36, 0x01, 0xb1, 0x36, 0x01, 0x17, 0x37, 0x01, 0x7d, 0x37, 0x01, 0xe3, 0x37, 0x01, 0x49, 0x38, 0x01, 0xaf, 0x38, 0x01, 0x15, 0x39, 0x01, 0x7b, 0x39, 0x01, 0xe1, 0x39, 0x01, 0x47, 0x3a, 0x01, 0xad, 0x3a, 0x01, 0x13, 0x3b, 0x01, 0x79, 0x3b, 0x01, 0xdf, 0x3b, 0x01, 0x45, 0x3c, 0x01, 0xab, 0x3c, 0x01, 0x11, 0x3d, 0x01, 0x77, 0x3d, 0x01, 0xdd, 0x3d, 0x01, 0x43, 0x3e, 0x01, 0xa9, 0x3e, 0x01, 0x0f, 0x3f, 0x01, 0x75, 0x3f, 0x01, 0xdb, 0x3f, 0x01, 0x41, 0x40, 0x01, 0xa7, 0x40, 0x01, 0x0d, 0x41, 0x01, 0x73, 0x41, 0x01, 0xd9, 0x41, 0x01, 0x3f, 0x42, 0x01, 0xa5, 0x42, 0x01, 0x0b, 0x43, 0x01, 0x71, 0x43, 0x01, 0xd7, 0x43, 0x01, 0x3d, 0x44, 0x01, 0xa3, 0x44, 0x01, 0x09, 0x45, 0x01, 0x6f, 0x45, 0x01, 0xd5, 0x45, 0x01, 0x3b, 0x46, 0x01, 0xa1, 0x46, 0x01, 0x07, 0x47, 0x01, 0x6d, 0x47, 0x01, 0xd3, 0x47, 0x01, 0x39, 0x48, 0x01, 0x9f, 0x48, 0x01, 0x05, 0x49, 0x01, 0x6b, 0x49, 0x01, 0xd1, 0x49, 0x01, 0x37, 0x4a, 0x01, 0x9d, 0x4a, 0x01, 0x03, 0x4b, 0x01, 0x69, 0x4b, 0x01, 0xcf, 0x4b, 0x01, 0x35, 0x4c, 0x01, 0x9b, 0x4c, 0x01, 0x01, 0x4d, 0x01, 0x67, 0x4d, 0x01, 0xcd, 0x4d, 0x01, 0x33, 0x4e, 0x01, 0x99, 0x4e, 0x01, 0xff, 0x4e, 0x01, 0x65, 0x4f, 0x01, 0xcb, 0x4f, 0x01, 0x31, 0x50, 0x01, 0x97, 0x50, 0x01, 0xfd, 0x50, 0x01, 0x63, 0x51, 0x01, 0xc9, 0x51, 0x01, 0x2f, 0x52, 0x01, 0x95, 0x52, 0x01, 0xfb, 0x52, 0x01, 0x61, 0x53, 0x01, 0xc7, 0x53, 0x01, 0x2d, 0x54, 0x01, 0x93, 0x54, 0x01, 0xf9, 0x54, 0x01, 0x5f, 0x55, 0x01, 0xc5, 0x55, 0x01, 0x2b, 0x56, 0x01, 0x91, 0x56, 0x01, 0xf7, 0x56, 0x01, 0x5d, 0x57, 0x01, 0xc3, 0x57, 0x01, 0x29, 0x58, 0x01, 0x8f, 0x58, 0x01, 0xf5, 0x58, 0x01, 0x5b, 0x59, 0x01, 0xc1, 0x59, 0x01, 0x27, 0x5a, 0x01, 0x8d, 0x5a, 0x01, 0xf3, 0x5a, 0x01, 0x59, 0x5b, 0x01, 0xbf, 0x5b, 0x01, 0x25, 0x5c, 0x01, 0x8b, 0x5c, 0x01, 0xf1, 0x5c, 0x01, 0x57, 0x5d, 0x01, 0xbd, 0x5d, 0x01, 0x23, 0x5e, 0x01, 0x89, 0x5e, 0x01, 0xef, 0x5e, 0x01, 0x55, 0x5f, 0x01, 0xbb, 0x5f, 0x01, 0x21, 0x60, 0x01, 0x87, 0x60, 0x01, 0xed, 0x60, 0x01, 0x53, 0x61, 0x01, 0xb9, 0x61, 0x01, 0x1f, 0x62, 0x01, 0x85, 0x62, 0x01, 0xeb, 0x62, 0x01, 0x51, 0x63, 0x01, 0xb7, 0x63, 0x01, 0x1d, 0x64, 0x01, 0x83, 0x64, 0x01, 0xe9, 0x64, 0x01, 0x4f, 0x65, 0x01, 0xb5, 0x65, 0x01, 0x1b, 0x66, 0x01, 0x81, 0x66, 0x01, 0xe7, 0x66, 0x01, 0x4d, 0x67, 0x01, 0xb3, 0x67, 0x01, 0x19, 0x68, 0x01, 0x7f, 0x68, 0x01, 0xe5, 0x68, 0x01, 0x4b, 0x69, 0x01, 0xb1, 0x69, 0x01, 0x17, 0x6a, 0x01, 0x7d, 0x6a, 0x01, 0xe3, 0x6a, 0x01, 0x49, 0x6b, 0x01, 0xaf, 0x6b, 0x01, 0x15, 0x6c, 0x01, 0x7b, 0x6c, 0x01, 0xe1, 0x6c, 0x01, 0x47, 0x6d, 0x01, 0xad, 0x6d, 0x01, 0x13, 0x6e, 0x01, 0x79, 0x6e, 0x01, 0xdf, 0x6e, 0x01, 0x45, 0x6f, 0x01, 0xab, 0x6f, 0x01, 0x11, 0x70, 0x01, 0x77, 0x70, 0x01, 0xdd, 0x70, 0x01, 0x43, 0x71, 0x01, 0xa9, 0x71, 0x01, 0x0f, 0x72, 0x01, 0x75, 0x72, 0x01, 0xdb, 0x72, 0x01, 0x41, 0x73, 0x01, 0xa7, 0x73, 0x01, 0x0d, 0x74, 0x01, 0x73, 0x74, 0x01, 0xd9, 0x74, 0x01, 0x3f, 0x75, 0x01, 0xa5, 0x75, 0x01, 0x0b, 0x76, 0x01, 0x71, 0x76, 0x01, 0xd7, 0x76, 0x01, 0x3d, 0x77, 0x01, 0xa3, 0x77, 0x01, 0x09, 0x78, 0x01, 0x6f, 0x78, 0x01, 0xd5, 0x78, 0x01, 0x3b, 0x79, 0x01, 0xa1, 0x79, 0x01, 0x07, 0x7a, 0x01, 0x6d, 0x7a, 0x01, 0xd3, 0x7a, 0x01, 0x39, 0x7b, 0x01, 0x9f, 0x7b, 0x01, 0x05, 0x7c, 0x01, 0x6b, 0x7c, 0x01, 0xd1, 0x7c, 0x01, 0x37, 0x7d, 0x01, 0x9d, 0x7d, 0x01, 0x03, 0x7e, 0x01, 0x69, 0x7e, 0x01, 0xcf, 0x7e, 0x01, 0x35, 0x7f, 0x01, 0x9b, 0x7f, 0x01, 0x01, 0x80, 0x01, 0x67, 0x80, 0x01, 0xcd, 0x80, 0x01, 0x33, 0x81, 0x01, 0x99, 0x81, 0x01, 0xff, 0x81, 0x01, 0x65, 0x82, 0x01, 0xcb, 0x82, 0x01, 0x31, 0x83, 0x01, 0x97, 0x83, 0x01, 0xfd, 0x83, 0x01, 0x63, 0x84, 0x01, 0xc9, 0x84, 0x01, 0x2f, 0x85, 0x01, 0x95, 0x85, 0x01, 0xfb, 0x85, 0x01, 0x61, 0x86, 0x01, 0xc7, 0x86, 0x01, 0x2d, 0x87, 0x01, 0x93, 0x87, 0x01, 0xf9, 0x87, 0x01, 0x5f, 0x88, 0x01, 0xc5, 0x88, 0x01, 0x2b, 0x89, 0x01, 0x91, 0x89, 0x01, 0xf7, 0x89, 0x01, 0x5d, 0x8a, 0x01, 0xc3, 0x8a, 0x01, 0x29, 0x8b, 0x01, 0x8f, 0x8b, 0x01, 0xf5, 0x8b, 0x01, 0x5b, 0x8c, 0x01, 0xc1, 0x8c, 0x01, 0x27, 0x8d, 0x01, 0x8d, 0x8d, 0x01, 0xf3, 0x8d, 0x01, 0x59, 0x8e, 0x01, 0xbf, 0x8e, 0x01, 0x25, 0x8f, 0x01, 0x8b, 0x8f, 0x01, 0xf1, 0x8f, 0x01, 0x57, 0x90, 0x01, 0xbd, 0x90, 0x01, 0x23, 0x91, 0x01, 0x89, 0x91, 0x01, 0xef, 0x91, 0x01, 0x55, 0x92, 0x01, 0xbb, 0x92, 0x01, 0x21, 0x93, 0x01, 0x87, 0x93, 0x01, 0xed, 0x93, 0x01, 0x53, 0x94, 0x01, 0xb9, 0x94, 0x01, 0x1f, 0x95, 0x01, 0x85, 0x95, 0x01, 0xeb, 0x95, 0x01, 0x51, 0x96, 0x01, 0xb7, 0x96, 0x01, 0x1d, 0x97, 0x01, 0x83, 0x97, 0x01, 0xe9, 0x97, 0x01, 0x4f, 0x98, 0x01, 0xb5, 0x98, 0x01, 0x1b, 0x99, 0x01, 0x81, 0x99, 0x01, 0xe7, 0x99, 0x01, 0x4d, 0x9a, 0x01, 0xb3, 0x9a, 0x01, 0x19, 0x9b, 0x01, 0x7f, 0x9b, 0x01, 0xe5, 0x9b, 0x01, 0x4b, 0x9c, 0x01, 0xb1, 0x9c, 0x01, 0x17, 0x9d, 0x01, 0x7d, 0x9d, 0x01, 0xe3, 0x9d, 0x01, 0x49, 0x9e, 0x01, 0xaf, 0x9e, 0x01, 0x15, 0x9f, 0x01, 0x7b, 0x9f, 0x01, 0xe1, 0x9f, 0x01, 0x47, 0xa0, 0x01, 0xad, 0xa0, 0x01, 0x13, 0xa1, 0x01, 0x79, 0xa1, 0x01, 0xdf, 0xa1, 0x01, 0x45, 0xa2, 0x01, 0xab, 0xa2, 0x01, 0x11, 0xa3, 0x01, 0x77, 0xa3, 0x01, 0xdd, 0xa3, 0x01, 0x43, 0xa4, 0x01, 0xa9, 0xa4, 0x01, 0x0f, 0xa5, 0x01, 0x75, 0xa5, 0x01, 0xdb, 0xa5, 0x01, 0x41, 0xa6, 0x01, 0xa7, 0xa6, 0x01, 0x0d, 0xa7, 0x01, 0x73, 0xa7, 0x01, 0xd9, 0xa7, 0x01, 0x3f, 0xa8, 0x01, 0xa5, 0xa8, 0x01, 0x0b, 0xa9, 0x01, 0x71, 0xa9, 0x01, 0xd7, 0xa9, 0x01, 0x3d, 0xaa, 0x01, 0xa3, 0xaa, 0x01, 0x09, 0xab, 0x01, 0x6f, 0xab, 0x01, 0xd5, 0xab, 0x01, 0x3b, 0xac, 0x01, 0xa1, 0xac, 0x01, 0x07, 0xad, 0x01, 0x6d, 0xad, 0x01, 0xd3, 0xad, 0x01, 0x39, 0xae, 0x01, 0x9f, 0xae, 0x01, 0x05, 0xaf, 0x01, 0x6b, 0xaf, 0x01, 0xd1, 0xaf, 0x01, 0x37, 0xb0, 0x01, 0x9d, 0xb0, 0x01, 0x03, 0xb1, 0x01, 0x69, 0xb1, 0x01, 0xcf, 0xb1, 0x01, 0x35, 0xb2, 0x01, 0x9b, 0xb2, 0x01, 0x01, 0xb3, 0x01, 0x67, 0xb3, 0x01, 0xcd, 0xb3, 0x01, 0x33, 0xb4, 0x01, 0x99, 0xb4, 0x01, 0xff, 0xb4, 0x01, 0x65, 0xb5, 0x01, 0xcb, 0xb5, 0x01, 0x31, 0xb6, 0x01, 0x97, 0xb6, 0x01, 0xfd, 0xb6, 0x01, 0x63, 0xb7, 0x01, 0xc9, 0xb7, 0x01, 0x2f, 0xb8, 0x01, 0x95, 0xb8, 0x01, 0xfb, 0xb8, 0x01, 0x61, 0xb9, 0x01, 0xc7, 0xb9, 0x01, 0x2d, 0xba, 0x01, 0x93, 0xba, 0x01, 0xf9, 0xba, 0x01, 0x5f, 0xbb, 0x01, 0xc5, 0xbb, 0x01, 0x2b, 0xbc, 0x01, 0x91, 0xbc, 0x01, 0xf7, 0xbc, 0x01, 0x5d, 0xbd, 0x01, 0xc3, 0xbd, 0x01, 0x29, 0xbe, 0x01, 0x8f, 0xbe, 0x01, 0xf5, 0xbe, 0x01, 0x5b, 0xbf, 0x01, 0xc1, 0xbf, 0x01, 0x27, 0xc0, 0x01, 0x8d, 0xc0, 0x01, 0xf3, 0xc0, 0x01, 0x59, 0xc1, 0x01, 0xbf, 0xc1, 0x01, 0x25, 0xc2, 0x01, 0x8b, 0xc2, 0x01, 0xf1, 0xc2, 0x01, 0x57, 0xc3, 0x01, 0xbd, 0xc3, 0x01, 0x23, 0xc4, 0x01, 0x89, 0xc4, 0x01, 0xef, 0xc4, 0x01, 0x55, 0xc5, 0x01, 0xbb, 0xc5, 0x01, 0x21, 0xc6, 0x01, 0x87, 0xc6, 0x01, 0xed, 0xc6, 0x01, 0x53, 0xc7, 0x01, 0xb9, 0xc7, 0x01, 0x1f, 0xc8, 0x01, 0x85, 0xc8, 0x01, 0xeb, 0xc8, 0x01, 0x51, 0xc9, 0x01, 0xb7, 0xc9, 0x01, 0x1d, 0xca, 0x01, 0x83, 0xca, 0x01, 0xe9, 0xca, 0x01, 0x4f, 0xcb, 0x01, 0xb5, 0xcb, 0x01, 0x1b, 0xcc, 0x01, 0x1f, 0x04, 0x07, 0x04, 0x04, 0x02, 0x03, 0x10, 0x00, 0x00, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x0a, 0x06, 0x00, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x10, 0x00, 0x00, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x1f, 0x00, 0x08, 0x00, 0x06, 0x00, 0x03, 0x0a, 0x06, 0x00, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x1e, 0x0b, 0x06, 0x04, 0x04, 0x03, 0x04, 0x0c, 0x04, 0x00, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x13, 0xf8, 0x01, 0x87, 0xf9, 0x01, 0x87, 0xf9, 0x01, 0x35, 0xee, 0x01, 0xa9, 0xf2, 0x01, 0xa9, 0xf2, 0x01, 0x35, 0xee, 0x01, 0xa9, 0xf2, 0x01, 0xa9, 0xf2, 0x01, 0x1e, 0x04, 0x0b, 0x04, 0x08, 0x02, 0x06, 0x04, 0x06, 0x06, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x18, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x0a, 0x06, 0x00, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x08, 0x04, 0x04, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0xb7, 0x11, 0x02, 0x21, 0x17, 0x02, 0x09, 0x1d, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x03, 0x05, 0x08, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0x7c, 0x00, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x73, 0x30, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xf0, 0x3c, 0x03, 0x55, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0xff, 0x00, 0x03, 0x55, 0x55, 0xff, 0x00, 0x3d, 0x55, 0x55, 0xff, 0x00, 0xcd, 0x55, 0x55, 0xcf, 0xff, 0x0d, 0x55, 0x55, 0x73, 0x30, 0x3d, 0x55, 0x55, 0x73, 0xf0, 0xf5, 0x55, 0x55, 0x73, 0xf0, 0x35, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x7f, 0x55, 0x57, 0xff, 0x55, 0xff, 0xd5, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x0f, 0x00, 0xf0, 0xd5, 0x57, 0x30, 0xc3, 0x0c, 0xd5, 0x57, 0x00, 0x3c, 0x00, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x57, 0x3f, 0xff, 0xfc, 0xd5, 0x57, 0xf0, 0xc3, 0x0f, 0xd5, 0x55, 0x73, 0xff, 0xcd, 0x55, 0x55, 0xc3, 0xff, 0xc3, 0x55, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x03, 0x00, 0xc0, 0xd5, 0x57, 0x0c, 0x00, 0x30, 0xd5, 0x57, 0x00, 0x3c, 0x00, 0xd5, 0x55, 0xc0, 0xff, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x3f, 0x0f, 0xc3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x00, 0xf0, 0x0d, 0x55, 0x55, 0xff, 0x0f, 0xf5, 0x55, 0x57, 0x33, 0xfc, 0xcd, 0x55, 0x57, 0xf3, 0xfc, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x30, 0x00, 0x0c, 0xd5, 0x57, 0x0c, 0x00, 0x30, 0xd5, 0x57, 0x00, 0xff, 0x00, 0xd5, 0x5f, 0x03, 0xff, 0xc0, 0xf5, 0x5c, 0xc3, 0xff, 0xc3, 0x35, 0x5f, 0x3f, 0xff, 0xfc, 0xf5, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0xc3, 0xff, 0xc3, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x7f, 0x55, 0x57, 0xff, 0x55, 0xff, 0xd5, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x03, 0x00, 0xc0, 0xd5, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x30, 0x3c, 0x0c, 0xd5, 0x55, 0xcc, 0x3c, 0x33, 0xd5, 0x55, 0xcc, 0x3c, 0x33, 0x55, 0x55, 0xc3, 0xc3, 0xc3, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xd7, 0xf5, 0x55, 0x55, 0x5f, 0x55, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x5c, 0x3f, 0xff, 0xc3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x55, 0xff, 0xff, 0xf5, 0x55, 0x55, 0xc0, 0x00, 0x35, 0x55, 0x57, 0x30, 0x00, 0xcd, 0x55, 0x57, 0xf0, 0x00, 0xfd, 0x55, 0x55, 0x70, 0x00, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0x55, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0x70, 0x00, 0x3d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x70, 0x0c, 0xd5, 0x55, 0x57, 0xc0, 0xfc, 0xd5, 0x55, 0x55, 0xf0, 0x3f, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0x57, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0x70, 0x00, 0x3d, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x30, 0xcd, 0x55, 0x55, 0xfc, 0x3f, 0xf5, 0x55, 0x55, 0x70, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x70, 0x3f, 0xf5, 0x55, 0x55, 0xc0, 0x0f, 0xf5, 0x55, 0x7f, 0xc0, 0x0f, 0xf5, 0x5f, 0xc0, 0xc0, 0x0f, 0x55, 0x5f, 0xc0, 0xc0, 0xcf, 0xd5, 0x55, 0xc0, 0xc0, 0xcf, 0xd5, 0x57, 0xc0, 0x3c, 0xcf, 0xf5, 0x5f, 0xfc, 0x03, 0x0f, 0xf5, 0x5f, 0xff, 0xff, 0xf7, 0xd5, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x3c, 0x03, 0xc3, 0x55, 0x5c, 0xc3, 0x0c, 0x33, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0xc3, 0x0c, 0x33, 0x55, 0x57, 0x30, 0xf0, 0xcc, 0xd5, 0x55, 0xff, 0xff, 0xf0, 0xd5, 0x55, 0x73, 0x0c, 0x03, 0x55, 0x55, 0xcc, 0xfc, 0x0d, 0x55, 0x55, 0xfc, 0xff, 0x0d, 0x55, 0x55, 0x5c, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x55, 0xf5, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x00, 0xc3, 0x00, 0xd5, 0x57, 0x3f, 0xc3, 0xfc, 0xd5, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x5c, 0xcc, 0x35, 0x55, 0x55, 0x73, 0xff, 0xcd, 0x55, 0x55, 0x70, 0xfc, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xc0, 0x30, 0x03, 0x55, 0x55, 0xc0, 0xc0, 0x03, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xfc, 0x00, 0x03, 0x55, 0x55, 0xff, 0x03, 0xc3, 0x55, 0x55, 0x7f, 0x03, 0x3d, 0x55, 0x55, 0x5f, 0xff, 0x35, 0x55, 0x55, 0x5c, 0xcc, 0x0d, 0x55, 0x55, 0x57, 0x3c, 0x03, 0x55, 0x55, 0x57, 0x3c, 0x3f, 0x55, 0x55, 0x57, 0xff, 0xf5, 0x55, 0x55, 0x55, 0x7d, 0xfd, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0x7f, 0x55, 0x55, 0x55, 0xff, 0xff, 0xd5, 0x55, 0x55, 0xff, 0xff, 0xd5, 0x55, 0x55, 0xff, 0x00, 0x35, 0x55, 0x57, 0xf0, 0x00, 0x3d, 0x55, 0x57, 0xc0, 0x03, 0x03, 0x55, 0x57, 0x00, 0x3c, 0x03, 0x55, 0x57, 0x00, 0x00, 0x0f, 0x55, 0x57, 0x00, 0x00, 0x35, 0x55, 0x57, 0xc0, 0x03, 0xd5, 0x55, 0x55, 0x7f, 0xff, 0x55, 0x55, 0x55, 0xc0, 0xcf, 0x55, 0x55, 0x57, 0x30, 0xfd, 0x55, 0x55, 0x57, 0xf0, 0xfd, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x7d, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xf5, 0x55, 0x55, 0x5f, 0xfd, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0x00, 0x0d, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x0f, 0xc3, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0x70, 0x00, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x5c, 0x3c, 0xd5, 0x55, 0x55, 0x5f, 0x0f, 0xd5, 0x55, 0x55, 0x5c, 0xff, 0xd5, 0x55, 0x55, 0x70, 0x0f, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3c, 0x0f, 0x55, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0xc0, 0x00, 0xff, 0x55, 0x55, 0xc0, 0xf0, 0xff, 0x55, 0x55, 0x70, 0xcc, 0xfd, 0x55, 0x55, 0x5f, 0xcf, 0xd5, 0x55, 0x55, 0x5c, 0xcc, 0xd5, 0x55, 0x55, 0x5c, 0x3f, 0xd5, 0x55, 0x55, 0x5c, 0x0f, 0xd5, 0x55, 0x55, 0x70, 0x0f, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x55, 0xfd, 0x55, 0x55, 0x7f, 0xdf, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0xc3, 0x55, 0x55, 0xcc, 0x00, 0x03, 0x55, 0x55, 0x73, 0x00, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x73, 0x30, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0x7f, 0x55, 0x55, 0xff, 0xd5, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0xd5, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0x70, 0x00, 0x03, 0x55, 0x55, 0xc3, 0x00, 0x30, 0xd5, 0x55, 0xcc, 0xc0, 0xcc, 0xd5, 0x55, 0xc3, 0x00, 0x30, 0xd5, 0x57, 0xc0, 0x3f, 0x00, 0xd5, 0x57, 0x30, 0xff, 0xc3, 0x55, 0x55, 0xcf, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xc3, 0xfc, 0x03, 0x55, 0x55, 0xc3, 0xfc, 0x3c, 0xd5, 0x55, 0x7f, 0xfc, 0x37, 0xd5, 0x55, 0x5f, 0x7f, 0xd5, 0x55, 0x55, 0x55, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x3c, 0x03, 0xc3, 0x55, 0x5c, 0xf3, 0x0f, 0x33, 0x55, 0x5c, 0xff, 0x0f, 0xf3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x0f, 0xf0, 0x0d, 0x55, 0x55, 0xfc, 0x3f, 0xf5, 0x55, 0x55, 0xc3, 0xcc, 0x3d, 0x55, 0x55, 0x70, 0xfc, 0xf3, 0x55, 0x55, 0x70, 0xfc, 0xdf, 0x55, 0x55, 0x7f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xcd, 0x55, 0x5f, 0xff, 0xff, 0xfd, 0x55, 0x7f, 0xff, 0xff, 0xd5, 0x55, 0x70, 0x00, 0x03, 0xd5, 0x55, 0xff, 0xff, 0xfc, 0xd5, 0x55, 0xc0, 0x00, 0x0f, 0xd5, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0x7c, 0x00, 0x0c, 0xd5, 0x55, 0x5f, 0xff, 0xf0, 0x35, 0x55, 0x7f, 0x3f, 0xfc, 0x0d, 0x55, 0x7f, 0x3f, 0xfc, 0x0d, 0x55, 0x70, 0x00, 0x3c, 0x0d, 0x55, 0x7f, 0xff, 0xf0, 0x0d, 0x55, 0x5f, 0xff, 0xdf, 0xf5, 0x55, 0x7f, 0xdf, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0x55, 0x55, 0x55, 0x57, 0x35, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0xff, 0xff, 0x55, 0x55, 0x5f, 0xff, 0xff, 0x55, 0x55, 0x70, 0x00, 0x0f, 0x55, 0x55, 0x7f, 0xff, 0xf3, 0xfd, 0x55, 0xc0, 0x00, 0x0c, 0xc3, 0x55, 0xc0, 0x00, 0x03, 0xc3, 0x55, 0xc0, 0x00, 0x03, 0x03, 0x55, 0xf0, 0x03, 0x03, 0xc3, 0x55, 0xc3, 0xc0, 0x0f, 0xc3, 0x55, 0xc3, 0xc0, 0x3f, 0x0d, 0x55, 0x7f, 0xff, 0xfc, 0x35, 0x5d, 0xff, 0x3f, 0xf3, 0xd5, 0x5f, 0x00, 0x00, 0xfd, 0x55, 0x5f, 0xff, 0xff, 0x3d, 0x55, 0x55, 0xff, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xff, 0x55, 0x55, 0x7f, 0xff, 0xff, 0xd5, 0x55, 0xf0, 0x00, 0x03, 0xf5, 0x55, 0xcf, 0xff, 0xfc, 0xf5, 0x55, 0xf0, 0x00, 0x03, 0xff, 0x57, 0x0f, 0xc0, 0xfc, 0xf3, 0x57, 0x33, 0xc3, 0x3c, 0xdf, 0x57, 0x33, 0xc3, 0x3c, 0xd5, 0x57, 0x0f, 0xc0, 0xfc, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x35, 0x55, 0xff, 0xff, 0xfc, 0x0d, 0x57, 0xff, 0xcf, 0xf3, 0x0d, 0x5c, 0xff, 0xcf, 0xff, 0x0d, 0x57, 0x70, 0x00, 0x0c, 0x0d, 0x55, 0x7f, 0xff, 0xf7, 0xf5, 0x55, 0x57, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xf7, 0xfd, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xff, 0xf5, 0x55, 0x70, 0x00, 0xff, 0xff, 0x55, 0x7f, 0xfc, 0x03, 0xf3, 0x55, 0xf0, 0xff, 0xf0, 0xdf, 0x55, 0xf0, 0xf3, 0x0f, 0xd5, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xff, 0xf0, 0x33, 0x55, 0x57, 0x3f, 0xc0, 0xff, 0xd5, 0x57, 0xcf, 0xff, 0xfc, 0x35, 0x55, 0xff, 0x3f, 0xfc, 0x0d, 0x55, 0x7f, 0x3f, 0xf0, 0x0d, 0x55, 0x7f, 0x3f, 0xf0, 0x0d, 0x55, 0x70, 0x00, 0xf0, 0x0d, 0x55, 0x5f, 0xff, 0xdf, 0xf5, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x55, 0xf7, 0xd5, 0x55, 0x30, 0x1f, 0x01, 0x55, 0x40, 0x00, 0x00, 0x00, 0x15, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x11, 0x41, 0x50, 0x00, 0x00, 0x15, 0x55, 0x55, 0x54, 0x04, 0x10, 0x01, 0x55, 0x41, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa1, 0x14, 0x15, 0x54, 0x01, 0x11, 0x45, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa5, 0x54, 0x15, 0x54, 0x01, 0x55, 0x45, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa1, 0x14, 0x44, 0x11, 0x55, 0x55, 0x55, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x15, 0x40, 0x01, 0x55, 0x11, 0x56, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x95, 0x40, 0x01, 0x55, 0x55, 0x56, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x95, 0x55, 0x55, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x55, 0x50, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x01, 0x50, 0x55, 0x50, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x15, 0x55, 0x55, 0x54, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x02, 0x55, 0x55, 0x55, 0x00, 0x04, 0x00, 0x80, 0x28, 0x00, 0x00, 0xa0, 0x02, 0x01, 0x15, 0x55, 0x10, 0x04, 0x55, 0x80, 0x28, 0x00, 0x00, 0xa0, 0x02, 0x01, 0x15, 0x55, 0x01, 0x55, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x02, 0x55, 0x55, 0x55, 0x01, 0x01, 0x00, 0x80, 0xaa, 0xaa, 0xaa, 0xa8, 0x02, 0x00, 0x04, 0x01, 0x01, 0x55, 0x00, 0x82, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x04, 0x01, 0x00, 0x41, 0x00, 0x82, 0xaa, 0xaa, 0xaa, 0xaa, 0x02, 0x00, 0x04, 0x01, 0x55, 0x5a, 0xa5, 0x80, 0x95, 0x95, 0x80, 0x00, 0x02, 0x55, 0x54, 0x01, 0x00, 0x25, 0x58, 0x80, 0x95, 0x95, 0x85, 0x54, 0x0a, 0xaa, 0xa8, 0x01, 0x00, 0x26, 0x98, 0x80, 0x95, 0x95, 0x85, 0x54, 0x08, 0x00, 0x09, 0x55, 0x00, 0x25, 0x58, 0x80, 0x95, 0x95, 0xaa, 0xaa, 0x08, 0x88, 0x88, 0x00, 0x00, 0x20, 0x08, 0x95, 0x95, 0x95, 0x80, 0x02, 0x58, 0x88, 0x88, 0x00, 0xaa, 0xa0, 0x0a, 0x95, 0x95, 0x95, 0x80, 0x02, 0x58, 0x00, 0x0a, 0xaa, 0x04, 0x20, 0x08, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa9, 0x55, 0x58, 0x00, 0x00, 0x0a, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xaa, 0xa9, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0x42, 0x82, 0x20, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa6, 0x86, 0x26, 0x62, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x45, 0x86, 0x24, 0xa4, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xa4, 0xa1, 0x61, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x61, 0x40, 0xa2, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0xaa, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa9, 0x55, 0x69, 0x55, 0x6a, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x9a, 0xa9, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x59, 0x59, 0x6a, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x98, 0x49, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x95, 0x55, 0xaa, 0x95, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa5, 0x56, 0xaa, 0x40, 0x68, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa8, 0x0a, 0xa5, 0x55, 0x58, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa9, 0x5a, 0xa5, 0x55, 0x58, 0x00, 0x95, 0x5a, 0x69, 0xa5, 0x56, 0x02, 0xa5, 0x96, 0xa9, 0x69, 0x68, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x96, 0x5a, 0x69, 0xa5, 0x96, 0x54, 0x54, 0x54, 0x54, 0x54, 0x55, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x54, 0x54, 0x54, 0x54, 0x54, 0x55, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x30, 0x1f, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x15, 0x00, 0x00, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x55, 0x00, 0x01, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x40, 0x51, 0x55, 0x55, 0x15, 0x54, 0x00, 0x00, 0x15, 0x54, 0x55, 0x55, 0x45, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x40, 0x00, 0x44, 0x11, 0x10, 0x11, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x44, 0x04, 0x44, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x40, 0x00, 0x44, 0x15, 0x05, 0x41, 0x50, 0x05, 0x55, 0x55, 0x50, 0x05, 0x41, 0x50, 0x54, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x50, 0x40, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x50, 0x40, 0x01, 0x00, 0x01, 0x00, 0x17, 0xfc, 0x3f, 0xfc, 0x00, 0x43, 0xff, 0xc0, 0x01, 0x00, 0x01, 0x00, 0x1f, 0xf4, 0xff, 0xd4, 0x00, 0x4f, 0xfc, 0x40, 0x01, 0x55, 0x55, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x40, 0x01, 0x11, 0x11, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x40, 0x01, 0x00, 0x01, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xc0, 0x01, 0x05, 0x41, 0x00, 0xf0, 0xfc, 0x03, 0xff, 0xff, 0x00, 0x00, 0xc0, 0x01, 0x05, 0x41, 0x00, 0xf0, 0xf3, 0x0c, 0x71, 0xc7, 0x33, 0x30, 0xc0, 0xaa, 0xaa, 0xaa, 0xaa, 0xf0, 0xf3, 0x0d, 0x75, 0xd7, 0x33, 0x30, 0xea, 0x55, 0x55, 0x55, 0x55, 0xf0, 0xfc, 0x0d, 0x34, 0xd3, 0x33, 0x30, 0xd5, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x0d, 0x34, 0xc3, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x03, 0xff, 0xff, 0xaa, 0xaa, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 0xc0, 0x00, 0xfc, 0x0f, 0xc0, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x3a, 0xbf, 0xfa, 0xab, 0xff, 0xbf, 0xfb, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0xff, 0xff, 0xcf, 0xfc, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf0, 0x03, 0xff, 0x3f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xc0, 0x00, 0xfc, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x55, 0x51, 0x55, 0x55, 0x15, 0x54, 0x00, 0x00, 0x15, 0x10, 0x00, 0x00, 0x40, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x40, 0x11, 0x10, 0x11, 0x10, 0x04, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x40, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x15, 0x55, 0x55, 0x40, 0x15, 0x05, 0x41, 0x50, 0x05, 0x55, 0x55, 0x50, 0x00, 0x00, 0x00, 0x00, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf5, 0xff, 0xf0, 0x00, 0x0f, 0xff, 0x00, 0x50, 0x50, 0x50, 0x50, 0x3f, 0xc3, 0xff, 0x00, 0x14, 0x3f, 0xf4, 0x14, 0x55, 0x50, 0x55, 0x50, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x54, 0x55, 0x50, 0x55, 0x50, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x54, 0x55, 0x55, 0x55, 0x53, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x54, 0x40, 0x10, 0x40, 0x13, 0xc3, 0xf0, 0x0f, 0xff, 0xfc, 0x00, 0x03, 0x04, 0x50, 0x50, 0x50, 0x53, 0xc3, 0xcc, 0x31, 0xc7, 0x1c, 0xcc, 0xc3, 0x14, 0x40, 0x10, 0x40, 0x13, 0xc3, 0xcc, 0x35, 0xd7, 0x5c, 0xcc, 0xc3, 0x04, 0xaa, 0xaa, 0xaa, 0xab, 0xc3, 0xf0, 0x34, 0xd3, 0x4c, 0xcc, 0xc3, 0xaa, 0x55, 0x55, 0x55, 0x57, 0x00, 0x00, 0x34, 0xd3, 0x0c, 0x00, 0x03, 0x55, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x0f, 0xff, 0xfe, 0xaa, 0xab, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x3f, 0x00, 0x03, 0xf0, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xea, 0xff, 0xea, 0xaf, 0xfe, 0xff, 0xec, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf3, 0xff, 0xff, 0x3f, 0xf3, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x0f, 0xfc, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x03, 0xf0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xfd, 0x7d, 0x7f, 0x5d, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x5d, 0xd5, 0xd7, 0x75, 0xdd, 0xd5, 0x55, 0x55, 0x55, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x30, 0xcc, 0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0xc0, 0xff, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xc0, 0xc3, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0x3f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xfc, 0x3f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x03, 0xc0, 0x30, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0xf3, 0xff, 0xff, 0xcf, 0x00, 0x00, 0x0f, 0xf0, 0x70, 0x0f, 0x55, 0x55, 0xc3, 0x0c, 0x30, 0xc3, 0x55, 0x55, 0xf0, 0x0d, 0xc3, 0x30, 0xd5, 0xff, 0x7c, 0xcf, 0xf3, 0x3d, 0xff, 0x57, 0x0c, 0xc3, 0xc0, 0x3f, 0x5f, 0x03, 0x57, 0xcf, 0xf3, 0xd5, 0xc0, 0xf5, 0xfc, 0x03, 0xc0, 0x30, 0xdc, 0x0d, 0x5f, 0xff, 0xff, 0xf5, 0x70, 0x37, 0x0c, 0x03, 0x7f, 0xff, 0x5f, 0xf5, 0x5f, 0x55, 0x55, 0xf5, 0x5f, 0xf5, 0xff, 0xfd, 0x30, 0x1f, 0xa4, 0x00, 0xa4, 0x01, 0x90, 0x00, 0x64, 0x06, 0x40, 0x1a, 0x00, 0x16, 0xa9, 0x40, 0x09, 0x00, 0x40, 0x00, 0x10, 0x01, 0x00, 0x60, 0x01, 0x6a, 0x2a, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xaa, 0x00, 0xa5, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x01, 0x6a, 0x80, 0x00, 0x01, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x30, 0xc0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x00, 0x05, 0x94, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x15, 0x56, 0xa5, 0x55, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x15, 0x40, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x29, 0x50, 0x15, 0x68, 0x00, 0x40, 0x07, 0xf0, 0x0f, 0xc0, 0x10, 0x00, 0x0a, 0xa5, 0x6a, 0x80, 0x01, 0x00, 0x1f, 0xfc, 0x3f, 0xf0, 0x04, 0x00, 0x00, 0xaa, 0xa8, 0x00, 0x15, 0x00, 0x1f, 0xff, 0xff, 0xf0, 0x05, 0x40, 0x00, 0x0a, 0xa0, 0x00, 0x04, 0x00, 0x5c, 0x00, 0x00, 0x30, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xf0, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xc0, 0x33, 0x00, 0x00, 0xcc, 0x03, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x30, 0x03, 0xc0, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x0c, 0x30, 0x03, 0xc0, 0x0c, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x3c, 0x03, 0xc0, 0x3c, 0xff, 0xc0, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0xc3, 0xff, 0xff, 0xc3, 0x00, 0x00, 0x0f, 0xf0, 0x30, 0x0c, 0x00, 0x00, 0xcc, 0x30, 0x0c, 0x33, 0x00, 0x00, 0x30, 0x0c, 0xc3, 0x0f, 0x00, 0x00, 0x3f, 0x3f, 0xfc, 0xfc, 0x00, 0x00, 0xf0, 0xc3, 0xc0, 0x30, 0xc0, 0x00, 0x03, 0x3f, 0xfc, 0xc0, 0x00, 0x03, 0x0c, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0xfc, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x3f, 0xfc, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x30, 0x30, 0xc0, 0x00, 0x00, 0x3c, 0x3c, 0x00, 0x00, 0x03, 0x0c, 0x0c, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x0c, 0x30, 0x00, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xfd, 0x7d, 0x7f, 0x5d, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x5d, 0xd5, 0xd7, 0x75, 0xdd, 0xd5, 0x55, 0x55, 0x55, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x30, 0xcc, 0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0xc0, 0xff, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xc0, 0xc3, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x70, 0x0f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xf0, 0x0d, 0xc3, 0x30, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x0c, 0xc3, 0xc0, 0x3f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfc, 0x03, 0xc0, 0x30, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x0c, 0x03, 0x7f, 0xff, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xfd, 0x30, 0x1f, 0xa4, 0x00, 0xa4, 0x01, 0x90, 0x00, 0x64, 0x06, 0x40, 0x1a, 0x00, 0x16, 0xa9, 0x40, 0x09, 0x00, 0x40, 0x00, 0x10, 0x01, 0x00, 0x60, 0x01, 0x6a, 0x2a, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xaa, 0x00, 0xa5, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x01, 0x6a, 0x80, 0x00, 0x01, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x30, 0xc0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x00, 0x05, 0x94, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x15, 0x56, 0xa5, 0x55, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x15, 0x40, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x29, 0x50, 0x15, 0x68, 0x00, 0x40, 0x04, 0x00, 0x04, 0x00, 0x10, 0x00, 0x0a, 0xa5, 0x6a, 0x80, 0x01, 0x00, 0x14, 0x00, 0x05, 0x00, 0x04, 0x00, 0x00, 0xaa, 0xa8, 0x00, 0x15, 0x00, 0x15, 0x00, 0x15, 0x00, 0x05, 0x40, 0x00, 0x0a, 0xa0, 0x00, 0x04, 0x00, 0x54, 0x00, 0x05, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x30, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0c, 0xc3, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xc3, 0xc0, 0x30, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x30, 0x30, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x0c, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xfc, 0x00, 0xc3, 0x0f, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xc3, 0x00, 0xc3, 0x30, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xcc, 0xc3, 0x00, 0xff, 0x30, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xfc, 0x00, 0xc3, 0x30, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xc0, 0x00, 0xc3, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x3f, 0x0f, 0xcf, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0xcc, 0x0c, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0xcf, 0xcf, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0x0f, 0xcf, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x30, 0xcc, 0x33, 0x0c, 0xfc, 0xfc, 0x00, 0x00, 0xc0, 0x00, 0x00, 0xc3, 0x30, 0xcf, 0x33, 0xcc, 0xc0, 0xc3, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc3, 0x30, 0xcc, 0xf3, 0x3c, 0xfc, 0xc3, 0x00, 0x00, 0xfc, 0x00, 0x00, 0xfc, 0x30, 0xcc, 0x33, 0x0c, 0xc0, 0xfc, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc3, 0x0f, 0x0c, 0x33, 0x0c, 0xfc, 0xc3, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x1f, 0x05, 0x55, 0x55, 0x55, 0x55, 0x55, 0x54, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x05, 0x54, 0x55, 0x45, 0x51, 0x10, 0x00, 0x04, 0x04, 0x55, 0x44, 0x51, 0x11, 0x55, 0x44, 0x04, 0x44, 0x44, 0x51, 0x11, 0x00, 0x44, 0x04, 0x44, 0x44, 0x51, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x00, 0x00, 0x00, 0x05, 0x41, 0x10, 0x00, 0x00, 0x00, 0x00, 0x04, 0x41, 0x10, 0x00, 0x00, 0x10, 0x55, 0x05, 0x41, 0x10, 0x54, 0x00, 0x55, 0x45, 0x10, 0x11, 0x11, 0x01, 0x40, 0x55, 0x54, 0x10, 0x11, 0x11, 0x00, 0x10, 0x55, 0x54, 0x15, 0x51, 0x11, 0x41, 0x11, 0x51, 0x10, 0x04, 0x41, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x50, 0x50, 0x00, 0x00, 0x10, 0x01, 0x10, 0x55, 0x50, 0x55, 0x00, 0x55, 0x01, 0x10, 0x44, 0x51, 0x00, 0x51, 0x00, 0x41, 0x10, 0x40, 0x11, 0x04, 0x41, 0x11, 0x41, 0x10, 0x15, 0x41, 0x00, 0x41, 0x00, 0x41, 0x10, 0x10, 0x41, 0x00, 0x40, 0x41, 0x01, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x55, 0x55, 0x55, 0x55, 0x55, 0x41, 0x10, 0x40, 0x00, 0x00, 0x00, 0x00, 0x41, 0x10, 0x55, 0x55, 0x55, 0x55, 0x55, 0x41, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x15, 0x50, 0x00, 0x00, 0x00, 0x01, 0x55, 0x12, 0x0c, 0x57, 0xf5, 0x7d, 0x55, 0x50, 0x5f, 0xfd, 0xff, 0x55, 0x50, 0x5f, 0xff, 0xff, 0x55, 0x50, 0x5f, 0xff, 0xff, 0xd5, 0x50, 0x7c, 0x00, 0x00, 0xd5, 0x50, 0x70, 0x0f, 0xc3, 0xd5, 0x50, 0x70, 0x33, 0xc3, 0xd5, 0x50, 0x70, 0x33, 0xc3, 0xd5, 0x50, 0x70, 0x0f, 0xc3, 0xd5, 0x50, 0x5c, 0x00, 0x0f, 0x55, 0x50, 0x57, 0xff, 0xfd, 0x55, 0x50, 0x5c, 0x3c, 0x33, 0x55, 0x50, 0x12, 0x0c, 0x55, 0xfd, 0x5f, 0x55, 0x50, 0x57, 0xff, 0x7f, 0xd5, 0x50, 0x57, 0xff, 0xff, 0xd5, 0x50, 0x57, 0xff, 0xff, 0xf5, 0x50, 0x5f, 0x00, 0x00, 0x35, 0x50, 0x5c, 0x03, 0xc0, 0x35, 0x50, 0x5c, 0x0c, 0x30, 0xf5, 0x50, 0x5c, 0x00, 0x00, 0x35, 0x50, 0x5c, 0x0c, 0x0f, 0xf5, 0x50, 0x57, 0x33, 0x0f, 0xd5, 0x50, 0x55, 0xf3, 0xff, 0x35, 0x50, 0x55, 0xc3, 0xc3, 0xf5, 0x50, 0x12, 0x0c, 0x5f, 0xd5, 0x7f, 0xff, 0xf0, 0x7f, 0xf5, 0xff, 0x00, 0x30, 0x7f, 0xff, 0xff, 0x00, 0x30, 0x7f, 0xff, 0xff, 0x00, 0x30, 0x70, 0x00, 0x03, 0x00, 0x30, 0xc3, 0xf0, 0x3f, 0x00, 0x30, 0xcc, 0xf0, 0xcf, 0x00, 0x30, 0xcc, 0xf0, 0xcf, 0x00, 0x30, 0xc3, 0xf0, 0x3f, 0xff, 0xf0, 0x70, 0x0f, 0x00, 0xcd, 0x50, 0x5f, 0xff, 0xff, 0x35, 0x50, 0x70, 0x30, 0x3c, 0xd5, 0x50, 0x12, 0x0c, 0x55, 0xfd, 0x57, 0xd5, 0x50, 0x57, 0xff, 0xdf, 0xf5, 0x50, 0x57, 0xff, 0xff, 0xfd, 0x50, 0x55, 0xff, 0xff, 0xfd, 0x50, 0x57, 0xc0, 0x00, 0x0d, 0x50, 0x57, 0x00, 0x00, 0x0d, 0x50, 0x57, 0x00, 0x00, 0x0d, 0x50, 0x57, 0x0f, 0xf0, 0x0d, 0x50, 0x57, 0x00, 0x00, 0xcd, 0x50, 0x55, 0xc0, 0x03, 0x35, 0x50, 0x55, 0x7f, 0xff, 0xd5, 0x50, 0x55, 0xc3, 0xc3, 0xd5, 0x50, 0x12, 0x0c, 0x57, 0xf5, 0x5f, 0xd5, 0x50, 0x5f, 0xfd, 0x7f, 0xf5, 0x50, 0x5f, 0xff, 0xff, 0xf5, 0x50, 0x5f, 0xff, 0xff, 0xf5, 0x50, 0x5c, 0x00, 0x00, 0x35, 0x50, 0x70, 0x00, 0x00, 0x0d, 0x50, 0x70, 0x30, 0x0c, 0x0d, 0x50, 0x70, 0xc0, 0x03, 0x0d, 0x50, 0x70, 0x03, 0xc0, 0x0d, 0x50, 0x5c, 0x0f, 0xf0, 0x35, 0x50, 0x57, 0xff, 0xff, 0xd5, 0x50, 0x55, 0xcc, 0x33, 0x55, 0x50, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfa, 0xaa, 0xab, 0xc0, 0xff, 0xe5, 0x55, 0x5a, 0xc0, 0xff, 0xe5, 0x55, 0x5a, 0xc0, 0xff, 0x95, 0x55, 0x66, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0xaa, 0xaa, 0xab, 0xc0, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfe, 0xaa, 0xaa, 0xc0, 0xff, 0xfe, 0x55, 0x56, 0xc0, 0xff, 0xfe, 0x55, 0x56, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xea, 0xaa, 0xaa, 0xc0, 0xff, 0xea, 0xaa, 0xaa, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0xaa, 0xaa, 0xab, 0xc0, 0x08, 0x08, 0x7f, 0xf5, 0xff, 0xfd, 0xc3, 0x0d, 0xff, 0xfd, 0xff, 0xfd, 0xfc, 0xfd, 0x7f, 0xf5, 0x77, 0x75, 0x10, 0x03, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xc0, 0x03, 0x03, 0xff, 0xff, 0xff, 0xff, 0x10, 0x03, 0x55, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x03, 0x55, 0x55, 0xff, 0xff, 0x55, 0x08, 0x08, 0x55, 0x75, 0x55, 0x75, 0x55, 0x75, 0x5f, 0x75, 0x70, 0xf5, 0x70, 0xd5, 0x5f, 0x55, 0x55, 0x55, 0x08, 0x08, 0x55, 0x75, 0x55, 0x75, 0x55, 0x75, 0x5f, 0x75, 0x7f, 0xf5, 0x7f, 0xd5, 0x5f, 0x55, 0x55, 0x55, 0x08, 0x08, 0x55, 0xd5, 0x55, 0xf5, 0x55, 0xfd, 0x7d, 0xdd, 0xff, 0xd5, 0xff, 0x55, 0x7d, 0x55, 0x55, 0x55, 0x08, 0x08, 0x5f, 0xfd, 0x5d, 0x5d, 0x5d, 0x5d, 0x5d, 0x5d, 0xfd, 0xfd, 0xfd, 0xfd, 0xf5, 0xf5, 0x55, 0x55, 0x01, 0x01, 0x00, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x7f, 0xfd, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x5f, 0xfd, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x7f, 0xfd, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x5f, 0xfd, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x7f, 0xfd, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0x03, 0x5f, 0xfd, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x08, 0x08, 0x50, 0x05, 0x43, 0xc1, 0x00, 0x00, 0x30, 0xcc, 0x33, 0x0c, 0x00, 0x00, 0x43, 0xc1, 0x50, 0x05, 0x08, 0x08, 0xc0, 0x03, 0x33, 0xcc, 0x00, 0x30, 0x33, 0x0c, 0x30, 0xcc, 0x0c, 0x00, 0x33, 0xcc, 0xc0, 0x03, 0x08, 0x08, 0x57, 0xd5, 0x5c, 0x35, 0x5c, 0x35, 0xdc, 0x37, 0xd7, 0xd7, 0xdf, 0xf7, 0xfd, 0x7f, 0xf7, 0xdf, 0x04, 0x1f, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x02, 0x05, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0x06, 0x20, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0x20, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf7, 0xff, 0x5f, 0x5f, 0xd7, 0xff, 0x75, 0x5d, 0x55, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x57, 0xd5, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x55, 0x75, 0x75, 0x7f, 0xdf, 0xd5, 0x75, 0x75, 0x55, 0x75, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x55, 0x5f, 0xd5, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x08, 0x7f, 0x5f, 0x57, 0xd7, 0x57, 0xd5, 0x75, 0xdd, 0x77, 0x57, 0xdf, 0x75, 0xdd, 0x77, 0x57, 0xd7, 0x75, 0xdf, 0xf7, 0x55, 0x7d, 0x5f, 0x5d, 0x77, 0xf7, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x0c, 0x7f, 0x5f, 0x5d, 0x5d, 0xfd, 0xd5, 0x75, 0xdf, 0x7d, 0xd5, 0xdf, 0x75, 0xdf, 0xfd, 0xfd, 0xd7, 0x7f, 0xdd, 0xdd, 0xd5, 0x7f, 0x75, 0xdd, 0x5d, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7d, 0x75, 0x77, 0xf7, 0xf5, 0xd7, 0x75, 0x77, 0x57, 0x5d, 0xd7, 0x5d, 0xd7, 0xf7, 0x5d, 0xd7, 0x5d, 0xd7, 0x57, 0xf5, 0x7d, 0x57, 0x57, 0xf7, 0x5d, 0x55, 0x55, 0x55, 0x55, 0x55, 0x20, 0x0c, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xff, 0x55, 0xc3, 0x7d, 0x55, 0x55, 0x55, 0x70, 0x00, 0xd5, 0x70, 0xff, 0x55, 0x55, 0x55, 0xc0, 0x00, 0x35, 0x7c, 0x3f, 0xd5, 0x55, 0x57, 0x00, 0x03, 0x0d, 0x5f, 0xff, 0xff, 0xff, 0xfc, 0x03, 0x00, 0x0d, 0x70, 0x00, 0x03, 0xc0, 0x00, 0x00, 0x3f, 0xfd, 0x7f, 0xff, 0xfc, 0x30, 0x00, 0x00, 0xc0, 0x03, 0xc0, 0x00, 0x03, 0x30, 0x00, 0x03, 0x0f, 0xfc, 0xc0, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc0, 0x03, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x01, 0x01, 0x00, 0x10, 0x10, 0x55, 0x7d, 0x55, 0xf5, 0x55, 0xc3, 0x57, 0x0d, 0x55, 0xc0, 0xdc, 0x0d, 0x55, 0x70, 0xdc, 0x3d, 0x55, 0x5c, 0x30, 0x35, 0x55, 0x70, 0x00, 0xd5, 0x55, 0xc3, 0xfc, 0xd5, 0x55, 0xcf, 0xff, 0x35, 0x57, 0x0f, 0xff, 0x35, 0x57, 0x00, 0xfc, 0x35, 0x57, 0xc0 }; void EXTI0_IRQHandler() { //GPIO_SetBits(GPIOB, GPIO_Pin_14); //if (EXTI_GetITStatus(EXTI_Line0) != RESET) { if(started){ if(read){ read = 2; } read = 1; //GPIO_SetBits(GPIOB, GPIO_Pin_14); a = 0; acount = 0; // as[loops++] = a; //as[loops++] = acount; as[loops++] = hit; hit = 0; } EXTI_ClearITPendingBit(EXTI_Line0); //} //GPIO_ResetBits(GPIOB, GPIO_Pin_14); } void EXTI1_IRQHandler() { //hit++; //if (EXTI_GetITStatus(EXTI_Line1) != RESET) { if(read){ // a = a << 1; // GPIO_SetBits(GPIOB, GPIO_Pin_15); // a = a | (GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_8)); (GPIOD->IDR & GPIO_Pin_8) ? (a = ((a << 1)|1) ) : (a <<= 1); //GPIO_ResetBits(GPIOB, GPIO_Pin_15); acount++; // if(acount > 32){ // GPIO_SetBits(GPIOD, GPIO_Pin_15); // } if (acount ==32){ read = 0; //if((a & 0xff000000) != 0x03000000){ // GPIO_SetBits(GPIOD, GPIO_Pin_14); // } as[loops++] = a; a = 0xffffff & a; // index = (loops % 800) / 100; if(loops > 100){ loops = 0; index++; if (index > 7) index = 0; } for(i = 0; i < 105; i++){ v[0xe0 + i] = vs[index][i]; } val = v[a++]; // as[loops++] = val; // as[loops++] = val; c = 0x80; if(val&c){ GPIO_SetBits(GPIOD, GPIO_Pin_4); }else{ GPIO_ResetBits(GPIOD, GPIO_Pin_4); } c = c >> 1; started = 1; } }else{ if(val&c){ GPIOD->BSRRL = GPIO_Pin_4; }else{ GPIOD->BSRRH = GPIO_Pin_4; } c = c >> 1; if(c==0){ c = 0x80; val = v[a++]; // as[loops++] = val; } //as[loops++] = 2; } EXTI_ClearITPendingBit(EXTI_Line1); //} } /** * @brief Main program. * @param None * @retval None */ uint32_t getAddress(); int main(void) { RCC_ClocksTypeDef RCC_Clocks; int l = 0; /* Initialize LEDs and User_Button on STM32F4-Discovery --------------------*/ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE); RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE); /* SysTick end of count event each 10ms */ // RCC_GetClocksFreq(&RCC_Clocks); // SysTick_Config(RCC_Clocks.HCLK_Frequency / 100); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_8 ; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_Init(GPIOD, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; GPIO_Init(GPIOD, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_13| GPIO_Pin_14| GPIO_Pin_15; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_Init(GPIOD, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14 | GPIO_Pin_15; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_Init(GPIOB, &GPIO_InitStructure); EXTILine0_Config(); GPIO_SetBits(GPIOD, GPIO_Pin_12); // GPIO_SetBits(GPIOD, GPIO_Pin_14); // GPIO_SetBits(GPIOD, GPIO_Pin_12); // GPIO_ResetBits(GPIOB, GPIO_Pin_14); //GPIO_SetBits(GPIOB, GPIO_Pin_14); vs[0] = v1; vs[1] = v2; vs[2] = v3; vs[3] = v2; vs[4] = v4; vs[5] = v5; vs[6] = v6; vs[7] = v7; while(1){ // GPIO_SetBits(GPIOB, GPIO_Pin_14); // GPIO_ResetBits(GPIOB, GPIO_Pin_14); // printf("here"); /* uint32_t a, j; uint8_t t, c, i; flag = 1; if(started) while(GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_0)){ l++; } a = getAddress(); // if(a < 0 || a > 200){ // GPIO_SetBits(GPIOD, GPIO_Pin_14); //} started = 1; while(flag){ t = v[a]; c = 0x80; for( i = 0; (i < 8); i++){ // if(a > 200){ // loops++; // } if(t&c){ GPIO_SetBits(GPIOD, GPIO_Pin_4); }else{ GPIO_ResetBits(GPIOD, GPIO_Pin_4); } // if(!flag) // break; c = c >> 1; // q = ; // while((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)== Bit_RESET) && (GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_9) == Bit_RESET)){} // while(GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11) && (GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_9) == Bit_RESET) ){} // l = 0; //while((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)== Bit_SET) && flag ){} // as[loops++] = q; // q = 0; while((!GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)) && flag ){ } // if((l++ % 100) == 99){ // if((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_9) != Bit_RESET)) // break; // } // as[loops++] = q; // q = 0; // l = 0; while(GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)){ //q++; } //as[loops++] = q; // if((l++ % 100) == 99){ // if((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_9) != Bit_RESET)) // break; // } // // for(j=0; j < 1000000; j++){ // } // } // if(flag) // loop++; } a++; } // as[loops++] = a; */ } } uint32_t getAddress(){ uint32_t a, i; a = 0; for(i = 0; i < 32; i++){ while(GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)== Bit_RESET){} //a++; a = a << 1; a = a + (GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_10)? 1:0); // if(i!=31) while(GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)){} } if((a & 0xff000000) != 0x03000000){ // GPIO_SetBits(GPIOD, GPIO_Pin_15); } // as[loops++] = a; return a & 0x00ffffff; } /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ ================================================ FILE: demos/nsdemomain.c ================================================ /** ****************************************************************************** * @file main.c * @author MCD Application Team * @version V1.0.0 * @date 19-September-2011 * @brief Main program body ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * *

© COPYRIGHT 2011 STMicroelectronics

****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ //#include "main.h" #include "stm32f4_discovery.h" //#include "stm32f4xx_it.c" uint8_t flag; //#include /** @addtogroup STM32F4-Discovery_Demo * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ //#define CLK GPIO_Pin_11 //#define ADDRESS GPIO_Pin_10 //#define E GPIO_Pin_9 EXTI_InitTypeDef EXTI_InitStructure; /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ //uint32_t a = 0; //int i; int started = 0; /* Private function prototypes -----------------------------------------------*/ GPIO_InitTypeDef GPIO_InitStructure; /* Private functions ---------------------------------------------------------*/ void EXTILine0_Config(void) { GPIO_InitTypeDef GPIO_InitStructure; NVIC_InitTypeDef NVIC_InitStructure; /* Enable GPIOA clock */ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); /* Enable SYSCFG clock */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); /* Configure PA0 pin as input floating */ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; GPIO_Init(GPIOA, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1; GPIO_Init(GPIOA, &GPIO_InitStructure); /* Connect EXTI Line0 to PA0 pin */ SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOA, EXTI_PinSource0); /* Configure EXTI Line0 */ EXTI_InitStructure.EXTI_Line = EXTI_Line0; EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; EXTI_InitStructure.EXTI_LineCmd = ENABLE; EXTI_Init(&EXTI_InitStructure); /* Enable and set EXTI Line0 Interrupt to the lowest priority */ NVIC_InitStructure.NVIC_IRQChannel = EXTI0_IRQn; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x01; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x01; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOA, EXTI_PinSource1); /* Configure EXTI Line0 */ EXTI_InitStructure.EXTI_Line = EXTI_Line1; EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; EXTI_InitStructure.EXTI_LineCmd = ENABLE; EXTI_Init(&EXTI_InitStructure); /* Enable and set EXTI Line0 Interrupt to the lowest priority */ NVIC_InitStructure.NVIC_IRQChannel = EXTI1_IRQn; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x02; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x01; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); } int loops = 0; int hit = 0; int q; int as[2000]; int read = 1; uint32_t a = 0; int acount = 0; uint8_t val; uint8_t c; uint8_t v[] = { 0x0a, 0xaa, 0x55, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0-f 0x00, 0xaa, 0x55, 0x03, 0x03, 0x03, 0x00, 0x00, 0x10, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //10-f 0x40, 0x00, 0x00, 0xc4, 0x00, 0x00, 0xdc, 0x00, 0x00, 0x0f, 0x01, 0x00, 0x91, 0x01, 0x00, 0x0d, //20 0x02, 0x00, 0x89, 0x02, 0x00, 0xd1, 0x02, 0x00, 0x1f, 0x06, 0x00, 0x67, 0x0f, 0x00, 0x67, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //40 0x41, 0x12, 0x00, 0xa7, 0x12, 0x00, 0x0d, 0x13, 0x00, 0x73, 0x13, 0x00, 0xd9, 0x13, 0x00, 0x3f, 0x14, 0x00, 0xa5, 0x14, 0x00, 0x0b, 0x15, 0x00, 0x71, 0x15, 0x00, 0xd7, 0x15, 0x00, 0x3d, 0x16, 0x00, 0xa3, 0x16, 0x00, 0x09, 0x17, 0x00, 0x6f, 0x17, 0x00, 0xd5, 0x17, 0x00, 0x3b, 0x18, 0x00, 0xa1, 0x18, 0x00, 0x07, 0x19, 0x00, 0x6d, 0x19, 0x00, 0xd3, 0x19, 0x00, 0x39, 0x1a, 0x00, 0x9f, //80 0x1a, 0x00, 0x05, 0x1b, 0x00, 0x6b, 0x1b, 0x00, 0xd1, 0x1b, 0x00, 0x37, 0x1c, 0x00, 0x9d, 0x1c, //90 0x00, 0x13, 0x1e, 0x00, 0x89, 0x1f, 0x00, 0xff, 0x20, 0x00, 0x75, 0x22, 0x00, 0xeb, 0x23, 0x00, 0x61, 0x25, 0x00, 0xd7, 0x26, 0x00, 0x4d, 0x28, 0x00, 0xeb, 0x28, 0x00, 0x89, 0x29, 0x00, 0x64, //b0 0x2a, 0x00, 0xa2, 0x2a, 0x00, 0xe0, 0x2a, 0x00, 0x1e, 0x2b, 0x00, 0x5c, 0x2b, 0x00, 0xce, 0x00, //c0 0x00, 0xce, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x44, 0x12, 0x34, 0x11, 0x15, //d0 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xaa, 0xa, 0xa0, 0x0, 0x0, 0x2a, 0x81, 0x80, 0x0, 0x0, 0x1a, 0x91, 0x80, 0x0, 0x0, 0x15, 0xa5, 0x80, 0x0, 0x0, 0x14, 0xa9, 0x80, 0x0, 0x0, 0x14, 0x2a, 0x80, 0x0, 0x0, 0x28, 0xa, 0x80, 0x0, 0x0, 0xaa, 0x2, 0x80, 0x0, 0x0, 0x0, 0x0, 0xa, 0xa9, 0x0, 0x0, 0x0, 0x1a, 0x19, 0x0, 0x0, 0x0, 0x2a, 0x9, 0x0, 0x0, 0x0, 0x1a, 0xa4, 0x0, 0x0, 0x0, 0x2, 0xa9, 0x0, 0x0, 0x0, 0x24, 0x2a, 0x0, 0x0, 0x0, 0x28, 0x29, 0x0, 0x0, 0x0, 0x2a, 0xa8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, // 0x0, 0xcf, 0xff, 0x0, 0x0, 0x0, 0x0, 0xcf, 0xff, 0x0, 0x0, 0x0, 0x0, // 0xcf, 0xff, 0x0, 0x0, 0xc, 0xff, 0xff, 0xff, 0x0, 0x0, 0xff, 0xff, // 0xff, 0xff, 0x0, 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, //0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, // 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, // 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, 0x0, 0x0, 0x0, 0xC0, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0x00, 0x00, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFA, 0xAA, 0xAB, 0xC0, 0xFF, 0xE5, 0x55, 0x5A, 0xC0, 0x00, 0xE5, 0x55, 0x5A, 0xC0, 0xFF, 0x95, 0x55, 0x66, 0xC0, 0xFF, 0xAA, 0xAA, 0xA6, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x8A, 0x28, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x8A, 0x28, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0xAA, 0xAA, 0xAB, 0xC0, 0x11, 0x15, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0x00, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFA, 0xAA, 0xAB, 0xC0, 0xFF, 0xE5, 0x55, 0x5A, 0xC0, 0xFF, 0xE5, 0x55, 0x5A, 0xC0, 0xFF, 0x95, 0x55, 0x66, 0xC0, 0xFF, 0xAA, 0xAA, 0xA6, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x8A, 0x28, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x8A, 0x28, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0xAA, 0xAA, 0xAB, 0xC0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};// 0x70, 0x2c, 0x00, 0x82, 0x2c, 0x00, 0x90, 0x2c, 0x00, 0x9e, 0x2c, 0x00, 0xb0, 0x2c, 0x00, 0xc2, 0x2c, 0x00, 0xd4, 0x2c, 0x00, 0xe6, 0x2c, 0x00, 0xe9, 0x2c, 0x00, 0x1b, 0x2d, 0x00, 0x4d, 0x2d, 0x00, 0x7f, 0x2d, 0x00, 0xb1, 0x2d, 0x00, 0xe3, 0x2d, 0x00, 0x15, 0x2e, 0x00, 0x27, 0x2e, 0x00, 0x39, 0x2e, 0x00, 0x4b, 0x2e, 0x00, 0x6c, 0x2e, 0x00, 0x73, 0x2e, 0x00, 0xb5, 0x2e, 0x00, 0xf7, 0x2e, 0x00, 0x21, 0x2f, 0x00, 0x5f, 0x2f, 0x00, 0xc1, 0x2f, 0x00, 0x02, 0x00, 0x06, 0x03, 0x04, 0x09, 0x0a, 0x05, 0x08, 0x07, 0x00, 0x00, 0x58, 0x00, 0x00, 0x32, 0x00, 0x00, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x10, 0x00, 0x00, 0x08, 0x00, 0x00, 0x50, 0x04, 0x00, 0x30, 0x02, 0x00, 0x20, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00, 0x50, 0x08, 0x00, 0x50, 0x11, 0x00, 0x00, 0x00, 0x28, 0x00, 0x40, 0x15, 0x00, 0x60, 0x12, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x45, 0x00, 0x00, 0x35, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x22, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00, 0x22, 0x00, 0x00, 0x13, 0x00, 0x01, 0x00, 0x02, 0x00, 0x50, 0x01, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x04, 0xff, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x02, 0xff, 0x01, 0x01, 0x00, 0x1e, 0x01, 0x00, 0x03, 0xff, 0x01, 0x01, 0x00, 0x2d, 0x01, 0x00, 0x04, 0xfe, 0x01, 0x01, 0x00, 0x3c, 0x01, 0x00, 0x05, 0xfe, 0x01, 0x01, 0x00, 0x4b, 0x02, 0x00, 0x06, 0xfe, 0x02, 0x02, 0x00, 0x5a, 0x02, 0x00, 0x07, 0xfd, 0x02, 0x02, 0x00, 0x63, 0x02, 0x00, 0x08, 0xfd, 0x02, 0x02, 0x00, 0x64, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0x00, 0x02, 0x04, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x02, 0xff, 0x01, 0x01, 0x00, 0x0f, 0x01, 0x00, 0x03, 0xff, 0x01, 0x01, 0x00, 0x19, 0x01, 0x00, 0x04, 0xfe, 0x01, 0x01, 0x00, 0x23, 0x01, 0x00, 0x05, 0xfe, 0x01, 0x02, 0x00, 0x2d, 0x02, 0x00, 0x06, 0xfe, 0x02, 0x02, 0x00, 0x37, 0x02, 0x00, 0x07, 0xfd, 0x02, 0x02, 0x00, 0x40, 0x02, 0x00, 0x08, 0xfd, 0x02, 0x02, 0x00, 0x41, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xc4, 0x2f, 0x00, 0xff, 0xff, 0xff, 0x06, 0x30, 0x00, 0x48, 0x30, 0x00, 0x8a, 0x30, 0x00, 0xcc, 0x30, 0x00, 0x0e, 0x31, 0x00, 0x50, 0x31, 0x00, 0x92, 0x31, 0x00, 0xd4, 0x31, 0x00, 0x16, 0x32, 0x00, 0xff, 0xff, 0xff, 0x58, 0x32, 0x00, 0xff, 0xff, 0xff, 0xba, 0x32, 0x00, 0x1c, 0x33, 0x00, 0x7e, 0x33, 0x00, 0xe0, 0x33, 0x00, 0x42, 0x34, 0x00, 0xa4, 0x34, 0x00, 0x06, 0x35, 0x00, 0x68, 0x35, 0x00, 0xca, 0x35, 0x00, 0xff, 0xff, 0xff, 0x2c, 0x36, 0x00, 0x3e, 0x36, 0x00, 0x80, 0x36, 0x00, 0xc2, 0x36, 0x00, 0x04, 0x37, 0x00, 0x46, 0x37, 0x00, 0x88, 0x37, 0x00, 0xca, 0x37, 0x00, 0x24, 0x38, 0x00, 0x9d, 0x38, 0x00, 0xf9, 0x38, 0x00, 0x7d, 0x39, 0x00, 0xd7, 0x39, 0x00, 0x50, 0x3a, 0x00, 0xac, 0x3a, 0x00, 0x30, 0x3b, 0x00, 0x72, 0x3b, 0x00, 0xb4, 0x3b, 0x00, 0xf6, 0x3b, 0x00, 0x38, 0x3c, 0x00, 0x7a, 0x3c, 0x00, 0xbc, 0x3c, 0x00, 0xfe, 0x3c, 0x00, 0x40, 0x3d, 0x00, 0x3a, 0x3e, 0x00, 0x34, 0x3f, 0x00, 0x2e, 0x40, 0x00, 0x28, 0x41, 0x00, 0x22, 0x42, 0x00, 0x98, 0x43, 0x00, 0xea, 0x43, 0x00, 0x3c, 0x44, 0x00, 0x8e, 0x44, 0x00, 0xe0, 0x44, 0x00, 0x32, 0x45, 0x00, 0x84, 0x45, 0x00, 0x7e, 0x46, 0x00, 0x78, 0x47, 0x00, 0xba, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0x76, 0x48, 0x00, 0xf0, 0x48, 0x00, 0x6a, 0x49, 0x00, 0xe4, 0x49, 0x00, 0x5e, 0x4a, 0x00, 0xd8, 0x4a, 0x00, 0x52, 0x4b, 0x00, 0xcc, 0x4b, 0x00, 0x46, 0x4c, 0x00, 0xc0, 0x4c, 0x00, 0x3a, 0x4d, 0x00, 0xb4, 0x4d, 0x00, 0x2e, 0x4e, 0x00, 0xa8, 0x4e, 0x00, 0x22, 0x4f, 0x00, 0x9c, 0x4f, 0x00, 0x16, 0x50, 0x00, 0x90, 0x50, 0x00, 0x0a, 0x51, 0x00, 0x84, 0x51, 0x00, 0xfe, 0x51, 0x00, 0x78, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0x6c, 0x53, 0x00, 0xe6, 0x53, 0x00, 0x60, 0x54, 0x00, 0xda, 0x54, 0x00, 0x54, 0x55, 0x00, 0xce, 0x55, 0x00, 0x48, 0x56, 0x00, 0xc2, 0x56, 0x00, 0x3c, 0x57, 0x00, 0xb6, 0x57, 0x00, 0x30, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0x24, 0x59, 0x00, 0x9e, 0x59, 0x00, 0x18, 0x5a, 0x00, 0x92, 0x5a, 0x00, 0x0c, 0x5b, 0x00, 0x86, 0x5b, 0x00, 0x00, 0x5c, 0x00, 0x7a, 0x5c, 0x00, 0xf4, 0x5c, 0x00, 0x6e, 0x5d, 0x00, 0xe8, 0x5d, 0x00, 0x62, 0x5e, 0x00, 0xdc, 0x5e, 0x00, 0x56, 0x5f, 0x00, 0xd0, 0x5f, 0x00, 0x4a, 0x60, 0x00, 0xc4, 0x60, 0x00, 0x3e, 0x61, 0x00, 0xb8, 0x61, 0x00, 0x32, 0x62, 0x00, 0xac, 0x62, 0x00, 0x26, 0x63, 0x00, 0xa0, 0x63, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x94, 0x64, 0x00, 0x0e, 0x65, 0x00, 0x88, 0x65, 0x00, 0x02, 0x66, 0x00, 0x7c, 0x66, 0x00, 0xf6, 0x66, 0x00, 0x70, 0x67, 0x00, 0xea, 0x67, 0x00, 0x64, 0x68, 0x00, 0xde, 0x68, 0x00, 0x58, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0x4c, 0x6a, 0x00, 0xc6, 0x6a, 0x00, 0x40, 0x6b, 0x00, 0xba, 0x6b, 0x00, 0x34, 0x6c, 0x00, 0xae, 0x6c, 0x00, 0x28, 0x6d, 0x00, 0xa2, 0x6d, 0x00, 0x1c, 0x6e, 0x00, 0x96, 0x6e, 0x00, 0x10, 0x6f, 0x00, 0x8a, 0x6f, 0x00, 0x04, 0x70, 0x00, 0x7e, 0x70, 0x00, 0xf8, 0x70, 0x00, 0x72, 0x71, 0x00, 0xec, 0x71, 0x00, 0x66, 0x72, 0x00, 0xe0, 0x72, 0x00, 0x5a, 0x73, 0x00, 0xd4, 0x73, 0x00, 0x4e, 0x74, 0x00, 0xc8, 0x74, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0xbc, 0x75, 0x00, 0x36, 0x76, 0x00, 0xb0, 0x76, 0x00, 0x2a, 0x77, 0x00, 0xa4, 0x77, 0x00, 0x1e, 0x78, 0x00, 0x98, 0x78, 0x00, 0x12, 0x79, 0x00, 0x8c, 0x79, 0x00, 0x06, 0x7a, 0x00, 0x80, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0x74, 0x7b, 0x00, 0xe2, 0x7b, 0x00, 0x50, 0x7c, 0x00, 0xbe, 0x7c, 0x00, 0x2c, 0x7d, 0x00, 0x9a, 0x7d, 0x00, 0x08, 0x7e, 0x00, 0x76, 0x7e, 0x00, 0xe4, 0x7e, 0x00, 0x52, 0x7f, 0x00, 0xc0, 0x7f, 0x00, 0x2e, 0x80, 0x00, 0x9c, 0x80, 0x00, 0x0a, 0x81, 0x00, 0x78, 0x81, 0x00, 0xe6, 0x81, 0x00, 0x54, 0x82, 0x00, 0xc2, 0x82, 0x00, 0x30, 0x83, 0x00, 0x9e, 0x83, 0x00, 0x0c, 0x84, 0x00, 0x7a, 0x84, 0x00, 0xe8, 0x84, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0xc4, 0x85, 0x00, 0x32, 0x86, 0x00, 0xa0, 0x86, 0x00, 0x0e, 0x87, 0x00, 0x7c, 0x87, 0x00, 0xea, 0x87, 0x00, 0x58, 0x88, 0x00, 0xc6, 0x88, 0x00, 0x34, 0x89, 0x00, 0xa2, 0x89, 0x00, 0x10, 0x8a, 0x00, 0x7e, 0x8a, 0x00, 0xec, 0x8a, 0x00, 0x2e, 0x8b, 0x00, 0xac, 0x8b, 0x00, 0x2a, 0x8c, 0x00, 0xa8, 0x8c, 0x00, 0x26, 0x8d, 0x00, 0xa4, 0x8d, 0x00, 0x22, 0x8e, 0x00, 0xa0, 0x8e, 0x00, 0x1e, 0x8f, 0x00, 0x60, 0x8f, 0x00, 0xa2, 0x8f, 0x00, 0xe4, 0x8f, 0x00, 0x13, 0x90, 0x00, 0x42, 0x90, 0x00, 0x65, 0x90, 0x00, 0x88, 0x90, 0x00, 0xab, 0x90, 0x00, 0xce, 0x90, 0x00, 0xf1, 0x90, 0x00, 0x57, 0x91, 0x00, 0xbd, 0x91, 0x00, 0x23, 0x92, 0x00, 0x89, 0x92, 0x00, 0xef, 0x92, 0x00, 0x55, 0x93, 0x00, 0xbb, 0x93, 0x00, 0x21, 0x94, 0x00, 0x87, 0x94, 0x00, 0xed, 0x94, 0x00, 0x53, 0x95, 0x00, 0xb9, 0x95, 0x00, 0x1f, 0x96, 0x00, 0x85, 0x96, 0x00, 0xeb, 0x96, 0x00, 0x51, 0x97, 0x00, 0xb7, 0x97, 0x00, 0x1d, 0x98, 0x00, 0x83, 0x98, 0x00, 0xe9, 0x98, 0x00, 0x4f, 0x99, 0x00, 0xb5, 0x99, 0x00, 0x1b, 0x9a, 0x00, 0x81, 0x9a, 0x00, 0xe7, 0x9a, 0x00, 0x4d, 0x9b, 0x00, 0xb3, 0x9b, 0x00, 0x19, 0x9c, 0x00, 0x7f, 0x9c, 0x00, 0xe5, 0x9c, 0x00, 0x4b, 0x9d, 0x00, 0xb1, 0x9d, 0x00, 0x17, 0x9e, 0x00, 0x7d, 0x9e, 0x00, 0xe3, 0x9e, 0x00, 0x49, 0x9f, 0x00, 0xaf, 0x9f, 0x00, 0x15, 0xa0, 0x00, 0x7b, 0xa0, 0x00, 0xe1, 0xa0, 0x00, 0x47, 0xa1, 0x00, 0xad, 0xa1, 0x00, 0x13, 0xa2, 0x00, 0x79, 0xa2, 0x00, 0xdf, 0xa2, 0x00, 0x45, 0xa3, 0x00, 0xab, 0xa3, 0x00, 0x11, 0xa4, 0x00, 0x77, 0xa4, 0x00, 0xdd, 0xa4, 0x00, 0x43, 0xa5, 0x00, 0xa9, 0xa5, 0x00, 0x0f, 0xa6, 0x00, 0x75, 0xa6, 0x00, 0xdb, 0xa6, 0x00, 0x41, 0xa7, 0x00, 0xa7, 0xa7, 0x00, 0x0d, 0xa8, 0x00, 0x73, 0xa8, 0x00, 0xd9, 0xa8, 0x00, 0x3f, 0xa9, 0x00, 0xa5, 0xa9, 0x00, 0x0b, 0xaa, 0x00, 0x71, 0xaa, 0x00, 0xd7, 0xaa, 0x00, 0x3d, 0xab, 0x00, 0xa3, 0xab, 0x00, 0x09, 0xac, 0x00, 0x6f, 0xac, 0x00, 0xd5, 0xac, 0x00, 0x3b, 0xad, 0x00, 0xa1, 0xad, 0x00, 0x07, 0xae, 0x00, 0x6d, 0xae, 0x00, 0xd3, 0xae, 0x00, 0x39, 0xaf, 0x00, 0x9f, 0xaf, 0x00, 0x05, 0xb0, 0x00, 0x6b, 0xb0, 0x00, 0xd1, 0xb0, 0x00, 0x37, 0xb1, 0x00, 0x9d, 0xb1, 0x00, 0x03, 0xb2, 0x00, 0x69, 0xb2, 0x00, 0xcf, 0xb2, 0x00, 0x35, 0xb3, 0x00, 0x9b, 0xb3, 0x00, 0x01, 0xb4, 0x00, 0x67, 0xb4, 0x00, 0xcd, 0xb4, 0x00, 0x33, 0xb5, 0x00, 0x99, 0xb5, 0x00, 0xff, 0xb5, 0x00, 0x65, 0xb6, 0x00, 0xcb, 0xb6, 0x00, 0x31, 0xb7, 0x00, 0x97, 0xb7, 0x00, 0xfd, 0xb7, 0x00, 0x63, 0xb8, 0x00, 0xc9, 0xb8, 0x00, 0x2f, 0xb9, 0x00, 0x95, 0xb9, 0x00, 0xfb, 0xb9, 0x00, 0x61, 0xba, 0x00, 0xc7, 0xba, 0x00, 0x2d, 0xbb, 0x00, 0x93, 0xbb, 0x00, 0xf9, 0xbb, 0x00, 0x5f, 0xbc, 0x00, 0xc5, 0xbc, 0x00, 0x2b, 0xbd, 0x00, 0x91, 0xbd, 0x00, 0xf7, 0xbd, 0x00, 0x5d, 0xbe, 0x00, 0xc3, 0xbe, 0x00, 0x29, 0xbf, 0x00, 0x8f, 0xbf, 0x00, 0xf5, 0xbf, 0x00, 0x5b, 0xc0, 0x00, 0xc1, 0xc0, 0x00, 0x27, 0xc1, 0x00, 0x8d, 0xc1, 0x00, 0xf3, 0xc1, 0x00, 0x59, 0xc2, 0x00, 0xbf, 0xc2, 0x00, 0x25, 0xc3, 0x00, 0x8b, 0xc3, 0x00, 0xf1, 0xc3, 0x00, 0x57, 0xc4, 0x00, 0xbd, 0xc4, 0x00, 0x23, 0xc5, 0x00, 0x89, 0xc5, 0x00, 0xef, 0xc5, 0x00, 0x55, 0xc6, 0x00, 0xbb, 0xc6, 0x00, 0x21, 0xc7, 0x00, 0x87, 0xc7, 0x00, 0xed, 0xc7, 0x00, 0x53, 0xc8, 0x00, 0xb9, 0xc8, 0x00, 0x1f, 0xc9, 0x00, 0x85, 0xc9, 0x00, 0xeb, 0xc9, 0x00, 0x51, 0xca, 0x00, 0xb7, 0xca, 0x00, 0x1d, 0xcb, 0x00, 0x83, 0xcb, 0x00, 0xe9, 0xcb, 0x00, 0x4f, 0xcc, 0x00, 0xb5, 0xcc, 0x00, 0x1b, 0xcd, 0x00, 0x81, 0xcd, 0x00, 0xe7, 0xcd, 0x00, 0x4d, 0xce, 0x00, 0xb3, 0xce, 0x00, 0x19, 0xcf, 0x00, 0x7f, 0xcf, 0x00, 0xe5, 0xcf, 0x00, 0x4b, 0xd0, 0x00, 0xb1, 0xd0, 0x00, 0x17, 0xd1, 0x00, 0x7d, 0xd1, 0x00, 0xe3, 0xd1, 0x00, 0x49, 0xd2, 0x00, 0xaf, 0xd2, 0x00, 0x15, 0xd3, 0x00, 0x7b, 0xd3, 0x00, 0xe1, 0xd3, 0x00, 0x47, 0xd4, 0x00, 0xad, 0xd4, 0x00, 0x13, 0xd5, 0x00, 0x79, 0xd5, 0x00, 0xdf, 0xd5, 0x00, 0x45, 0xd6, 0x00, 0xab, 0xd6, 0x00, 0x11, 0xd7, 0x00, 0x77, 0xd7, 0x00, 0xdd, 0xd7, 0x00, 0x43, 0xd8, 0x00, 0xa9, 0xd8, 0x00, 0x0f, 0xd9, 0x00, 0x75, 0xd9, 0x00, 0xdb, 0xd9, 0x00, 0x41, 0xda, 0x00, 0xa7, 0xda, 0x00, 0x0d, 0xdb, 0x00, 0x73, 0xdb, 0x00, 0xd9, 0xdb, 0x00, 0x3f, 0xdc, 0x00, 0xa5, 0xdc, 0x00, 0x0b, 0xdd, 0x00, 0x71, 0xdd, 0x00, 0xd7, 0xdd, 0x00, 0x3d, 0xde, 0x00, 0xa3, 0xde, 0x00, 0x09, 0xdf, 0x00, 0x6f, 0xdf, 0x00, 0xd5, 0xdf, 0x00, 0x3b, 0xe0, 0x00, 0xa1, 0xe0, 0x00, 0x07, 0xe1, 0x00, 0x6d, 0xe1, 0x00, 0xd3, 0xe1, 0x00, 0x39, 0xe2, 0x00, 0x9f, 0xe2, 0x00, 0x05, 0xe3, 0x00, 0x6b, 0xe3, 0x00, 0xd1, 0xe3, 0x00, 0x37, 0xe4, 0x00, 0x9d, 0xe4, 0x00, 0x03, 0xe5, 0x00, 0x69, 0xe5, 0x00, 0xcf, 0xe5, 0x00, 0x35, 0xe6, 0x00, 0x9b, 0xe6, 0x00, 0x01, 0xe7, 0x00, 0x67, 0xe7, 0x00, 0xcd, 0xe7, 0x00, 0x33, 0xe8, 0x00, 0x99, 0xe8, 0x00, 0xff, 0xe8, 0x00, 0x65, 0xe9, 0x00, 0xcb, 0xe9, 0x00, 0x31, 0xea, 0x00, 0x97, 0xea, 0x00, 0xfd, 0xea, 0x00, 0x63, 0xeb, 0x00, 0xc9, 0xeb, 0x00, 0x2f, 0xec, 0x00, 0x95, 0xec, 0x00, 0xfb, 0xec, 0x00, 0x61, 0xed, 0x00, 0xc7, 0xed, 0x00, 0x2d, 0xee, 0x00, 0x93, 0xee, 0x00, 0xf9, 0xee, 0x00, 0x5f, 0xef, 0x00, 0xc5, 0xef, 0x00, 0x2b, 0xf0, 0x00, 0x91, 0xf0, 0x00, 0xf7, 0xf0, 0x00, 0x5d, 0xf1, 0x00, 0xc3, 0xf1, 0x00, 0x29, 0xf2, 0x00, 0x8f, 0xf2, 0x00, 0xf5, 0xf2, 0x00, 0x5b, 0xf3, 0x00, 0xc1, 0xf3, 0x00, 0x27, 0xf4, 0x00, 0x8d, 0xf4, 0x00, 0xf3, 0xf4, 0x00, 0x59, 0xf5, 0x00, 0xbf, 0xf5, 0x00, 0x25, 0xf6, 0x00, 0x8b, 0xf6, 0x00, 0xf1, 0xf6, 0x00, 0x57, 0xf7, 0x00, 0xbd, 0xf7, 0x00, 0x23, 0xf8, 0x00, 0x89, 0xf8, 0x00, 0xef, 0xf8, 0x00, 0x55, 0xf9, 0x00, 0xbb, 0xf9, 0x00, 0x21, 0xfa, 0x00, 0x87, 0xfa, 0x00, 0xed, 0xfa, 0x00, 0x53, 0xfb, 0x00, 0xb9, 0xfb, 0x00, 0x1f, 0xfc, 0x00, 0x85, 0xfc, 0x00, 0xeb, 0xfc, 0x00, 0x51, 0xfd, 0x00, 0xb7, 0xfd, 0x00, 0x1d, 0xfe, 0x00, 0x83, 0xfe, 0x00, 0xe9, 0xfe, 0x00, 0x4f, 0xff, 0x00, 0xb5, 0xff, 0x00, 0x1b, 0x00, 0x01, 0x81, 0x00, 0x01, 0xe7, 0x00, 0x01, 0x4d, 0x01, 0x01, 0xb3, 0x01, 0x01, 0x19, 0x02, 0x01, 0x7f, 0x02, 0x01, 0xe5, 0x02, 0x01, 0x4b, 0x03, 0x01, 0xb1, 0x03, 0x01, 0x17, 0x04, 0x01, 0x7d, 0x04, 0x01, 0xe3, 0x04, 0x01, 0x49, 0x05, 0x01, 0xaf, 0x05, 0x01, 0x15, 0x06, 0x01, 0x7b, 0x06, 0x01, 0xe1, 0x06, 0x01, 0x47, 0x07, 0x01, 0xad, 0x07, 0x01, 0x13, 0x08, 0x01, 0x79, 0x08, 0x01, 0xdf, 0x08, 0x01, 0x45, 0x09, 0x01, 0xab, 0x09, 0x01, 0x11, 0x0a, 0x01, 0x77, 0x0a, 0x01, 0xdd, 0x0a, 0x01, 0x43, 0x0b, 0x01, 0xa9, 0x0b, 0x01, 0x0f, 0x0c, 0x01, 0x75, 0x0c, 0x01, 0xdb, 0x0c, 0x01, 0x41, 0x0d, 0x01, 0xa7, 0x0d, 0x01, 0x0d, 0x0e, 0x01, 0x73, 0x0e, 0x01, 0xd9, 0x0e, 0x01, 0x3f, 0x0f, 0x01, 0xa5, 0x0f, 0x01, 0x0b, 0x10, 0x01, 0x71, 0x10, 0x01, 0xd7, 0x10, 0x01, 0x3d, 0x11, 0x01, 0xa3, 0x11, 0x01, 0x09, 0x12, 0x01, 0x6f, 0x12, 0x01, 0xd5, 0x12, 0x01, 0x3b, 0x13, 0x01, 0xa1, 0x13, 0x01, 0x07, 0x14, 0x01, 0x6d, 0x14, 0x01, 0xd3, 0x14, 0x01, 0x39, 0x15, 0x01, 0x9f, 0x15, 0x01, 0x05, 0x16, 0x01, 0x6b, 0x16, 0x01, 0xd1, 0x16, 0x01, 0x37, 0x17, 0x01, 0x9d, 0x17, 0x01, 0x03, 0x18, 0x01, 0x69, 0x18, 0x01, 0xcf, 0x18, 0x01, 0x35, 0x19, 0x01, 0x9b, 0x19, 0x01, 0x01, 0x1a, 0x01, 0x67, 0x1a, 0x01, 0xcd, 0x1a, 0x01, 0x33, 0x1b, 0x01, 0x99, 0x1b, 0x01, 0xff, 0x1b, 0x01, 0x65, 0x1c, 0x01, 0xcb, 0x1c, 0x01, 0x31, 0x1d, 0x01, 0x97, 0x1d, 0x01, 0xfd, 0x1d, 0x01, 0x63, 0x1e, 0x01, 0xc9, 0x1e, 0x01, 0x2f, 0x1f, 0x01, 0x95, 0x1f, 0x01, 0xfb, 0x1f, 0x01, 0x61, 0x20, 0x01, 0xc7, 0x20, 0x01, 0x2d, 0x21, 0x01, 0x93, 0x21, 0x01, 0xf9, 0x21, 0x01, 0x5f, 0x22, 0x01, 0xc5, 0x22, 0x01, 0x2b, 0x23, 0x01, 0x91, 0x23, 0x01, 0xf7, 0x23, 0x01, 0x5d, 0x24, 0x01, 0xc3, 0x24, 0x01, 0x29, 0x25, 0x01, 0x8f, 0x25, 0x01, 0xf5, 0x25, 0x01, 0x5b, 0x26, 0x01, 0xc1, 0x26, 0x01, 0x27, 0x27, 0x01, 0x8d, 0x27, 0x01, 0xf3, 0x27, 0x01, 0x59, 0x28, 0x01, 0xbf, 0x28, 0x01, 0x25, 0x29, 0x01, 0x8b, 0x29, 0x01, 0xf1, 0x29, 0x01, 0x57, 0x2a, 0x01, 0xbd, 0x2a, 0x01, 0x23, 0x2b, 0x01, 0x89, 0x2b, 0x01, 0xef, 0x2b, 0x01, 0x55, 0x2c, 0x01, 0xbb, 0x2c, 0x01, 0x21, 0x2d, 0x01, 0x87, 0x2d, 0x01, 0xed, 0x2d, 0x01, 0x53, 0x2e, 0x01, 0xb9, 0x2e, 0x01, 0x1f, 0x2f, 0x01, 0x85, 0x2f, 0x01, 0xeb, 0x2f, 0x01, 0x51, 0x30, 0x01, 0xb7, 0x30, 0x01, 0x1d, 0x31, 0x01, 0x83, 0x31, 0x01, 0xe9, 0x31, 0x01, 0x4f, 0x32, 0x01, 0xb5, 0x32, 0x01, 0x1b, 0x33, 0x01, 0x81, 0x33, 0x01, 0xe7, 0x33, 0x01, 0x4d, 0x34, 0x01, 0xb3, 0x34, 0x01, 0x19, 0x35, 0x01, 0x7f, 0x35, 0x01, 0xe5, 0x35, 0x01, 0x4b, 0x36, 0x01, 0xb1, 0x36, 0x01, 0x17, 0x37, 0x01, 0x7d, 0x37, 0x01, 0xe3, 0x37, 0x01, 0x49, 0x38, 0x01, 0xaf, 0x38, 0x01, 0x15, 0x39, 0x01, 0x7b, 0x39, 0x01, 0xe1, 0x39, 0x01, 0x47, 0x3a, 0x01, 0xad, 0x3a, 0x01, 0x13, 0x3b, 0x01, 0x79, 0x3b, 0x01, 0xdf, 0x3b, 0x01, 0x45, 0x3c, 0x01, 0xab, 0x3c, 0x01, 0x11, 0x3d, 0x01, 0x77, 0x3d, 0x01, 0xdd, 0x3d, 0x01, 0x43, 0x3e, 0x01, 0xa9, 0x3e, 0x01, 0x0f, 0x3f, 0x01, 0x75, 0x3f, 0x01, 0xdb, 0x3f, 0x01, 0x41, 0x40, 0x01, 0xa7, 0x40, 0x01, 0x0d, 0x41, 0x01, 0x73, 0x41, 0x01, 0xd9, 0x41, 0x01, 0x3f, 0x42, 0x01, 0xa5, 0x42, 0x01, 0x0b, 0x43, 0x01, 0x71, 0x43, 0x01, 0xd7, 0x43, 0x01, 0x3d, 0x44, 0x01, 0xa3, 0x44, 0x01, 0x09, 0x45, 0x01, 0x6f, 0x45, 0x01, 0xd5, 0x45, 0x01, 0x3b, 0x46, 0x01, 0xa1, 0x46, 0x01, 0x07, 0x47, 0x01, 0x6d, 0x47, 0x01, 0xd3, 0x47, 0x01, 0x39, 0x48, 0x01, 0x9f, 0x48, 0x01, 0x05, 0x49, 0x01, 0x6b, 0x49, 0x01, 0xd1, 0x49, 0x01, 0x37, 0x4a, 0x01, 0x9d, 0x4a, 0x01, 0x03, 0x4b, 0x01, 0x69, 0x4b, 0x01, 0xcf, 0x4b, 0x01, 0x35, 0x4c, 0x01, 0x9b, 0x4c, 0x01, 0x01, 0x4d, 0x01, 0x67, 0x4d, 0x01, 0xcd, 0x4d, 0x01, 0x33, 0x4e, 0x01, 0x99, 0x4e, 0x01, 0xff, 0x4e, 0x01, 0x65, 0x4f, 0x01, 0xcb, 0x4f, 0x01, 0x31, 0x50, 0x01, 0x97, 0x50, 0x01, 0xfd, 0x50, 0x01, 0x63, 0x51, 0x01, 0xc9, 0x51, 0x01, 0x2f, 0x52, 0x01, 0x95, 0x52, 0x01, 0xfb, 0x52, 0x01, 0x61, 0x53, 0x01, 0xc7, 0x53, 0x01, 0x2d, 0x54, 0x01, 0x93, 0x54, 0x01, 0xf9, 0x54, 0x01, 0x5f, 0x55, 0x01, 0xc5, 0x55, 0x01, 0x2b, 0x56, 0x01, 0x91, 0x56, 0x01, 0xf7, 0x56, 0x01, 0x5d, 0x57, 0x01, 0xc3, 0x57, 0x01, 0x29, 0x58, 0x01, 0x8f, 0x58, 0x01, 0xf5, 0x58, 0x01, 0x5b, 0x59, 0x01, 0xc1, 0x59, 0x01, 0x27, 0x5a, 0x01, 0x8d, 0x5a, 0x01, 0xf3, 0x5a, 0x01, 0x59, 0x5b, 0x01, 0xbf, 0x5b, 0x01, 0x25, 0x5c, 0x01, 0x8b, 0x5c, 0x01, 0xf1, 0x5c, 0x01, 0x57, 0x5d, 0x01, 0xbd, 0x5d, 0x01, 0x23, 0x5e, 0x01, 0x89, 0x5e, 0x01, 0xef, 0x5e, 0x01, 0x55, 0x5f, 0x01, 0xbb, 0x5f, 0x01, 0x21, 0x60, 0x01, 0x87, 0x60, 0x01, 0xed, 0x60, 0x01, 0x53, 0x61, 0x01, 0xb9, 0x61, 0x01, 0x1f, 0x62, 0x01, 0x85, 0x62, 0x01, 0xeb, 0x62, 0x01, 0x51, 0x63, 0x01, 0xb7, 0x63, 0x01, 0x1d, 0x64, 0x01, 0x83, 0x64, 0x01, 0xe9, 0x64, 0x01, 0x4f, 0x65, 0x01, 0xb5, 0x65, 0x01, 0x1b, 0x66, 0x01, 0x81, 0x66, 0x01, 0xe7, 0x66, 0x01, 0x4d, 0x67, 0x01, 0xb3, 0x67, 0x01, 0x19, 0x68, 0x01, 0x7f, 0x68, 0x01, 0xe5, 0x68, 0x01, 0x4b, 0x69, 0x01, 0xb1, 0x69, 0x01, 0x17, 0x6a, 0x01, 0x7d, 0x6a, 0x01, 0xe3, 0x6a, 0x01, 0x49, 0x6b, 0x01, 0xaf, 0x6b, 0x01, 0x15, 0x6c, 0x01, 0x7b, 0x6c, 0x01, 0xe1, 0x6c, 0x01, 0x47, 0x6d, 0x01, 0xad, 0x6d, 0x01, 0x13, 0x6e, 0x01, 0x79, 0x6e, 0x01, 0xdf, 0x6e, 0x01, 0x45, 0x6f, 0x01, 0xab, 0x6f, 0x01, 0x11, 0x70, 0x01, 0x77, 0x70, 0x01, 0xdd, 0x70, 0x01, 0x43, 0x71, 0x01, 0xa9, 0x71, 0x01, 0x0f, 0x72, 0x01, 0x75, 0x72, 0x01, 0xdb, 0x72, 0x01, 0x41, 0x73, 0x01, 0xa7, 0x73, 0x01, 0x0d, 0x74, 0x01, 0x73, 0x74, 0x01, 0xd9, 0x74, 0x01, 0x3f, 0x75, 0x01, 0xa5, 0x75, 0x01, 0x0b, 0x76, 0x01, 0x71, 0x76, 0x01, 0xd7, 0x76, 0x01, 0x3d, 0x77, 0x01, 0xa3, 0x77, 0x01, 0x09, 0x78, 0x01, 0x6f, 0x78, 0x01, 0xd5, 0x78, 0x01, 0x3b, 0x79, 0x01, 0xa1, 0x79, 0x01, 0x07, 0x7a, 0x01, 0x6d, 0x7a, 0x01, 0xd3, 0x7a, 0x01, 0x39, 0x7b, 0x01, 0x9f, 0x7b, 0x01, 0x05, 0x7c, 0x01, 0x6b, 0x7c, 0x01, 0xd1, 0x7c, 0x01, 0x37, 0x7d, 0x01, 0x9d, 0x7d, 0x01, 0x03, 0x7e, 0x01, 0x69, 0x7e, 0x01, 0xcf, 0x7e, 0x01, 0x35, 0x7f, 0x01, 0x9b, 0x7f, 0x01, 0x01, 0x80, 0x01, 0x67, 0x80, 0x01, 0xcd, 0x80, 0x01, 0x33, 0x81, 0x01, 0x99, 0x81, 0x01, 0xff, 0x81, 0x01, 0x65, 0x82, 0x01, 0xcb, 0x82, 0x01, 0x31, 0x83, 0x01, 0x97, 0x83, 0x01, 0xfd, 0x83, 0x01, 0x63, 0x84, 0x01, 0xc9, 0x84, 0x01, 0x2f, 0x85, 0x01, 0x95, 0x85, 0x01, 0xfb, 0x85, 0x01, 0x61, 0x86, 0x01, 0xc7, 0x86, 0x01, 0x2d, 0x87, 0x01, 0x93, 0x87, 0x01, 0xf9, 0x87, 0x01, 0x5f, 0x88, 0x01, 0xc5, 0x88, 0x01, 0x2b, 0x89, 0x01, 0x91, 0x89, 0x01, 0xf7, 0x89, 0x01, 0x5d, 0x8a, 0x01, 0xc3, 0x8a, 0x01, 0x29, 0x8b, 0x01, 0x8f, 0x8b, 0x01, 0xf5, 0x8b, 0x01, 0x5b, 0x8c, 0x01, 0xc1, 0x8c, 0x01, 0x27, 0x8d, 0x01, 0x8d, 0x8d, 0x01, 0xf3, 0x8d, 0x01, 0x59, 0x8e, 0x01, 0xbf, 0x8e, 0x01, 0x25, 0x8f, 0x01, 0x8b, 0x8f, 0x01, 0xf1, 0x8f, 0x01, 0x57, 0x90, 0x01, 0xbd, 0x90, 0x01, 0x23, 0x91, 0x01, 0x89, 0x91, 0x01, 0xef, 0x91, 0x01, 0x55, 0x92, 0x01, 0xbb, 0x92, 0x01, 0x21, 0x93, 0x01, 0x87, 0x93, 0x01, 0xed, 0x93, 0x01, 0x53, 0x94, 0x01, 0xb9, 0x94, 0x01, 0x1f, 0x95, 0x01, 0x85, 0x95, 0x01, 0xeb, 0x95, 0x01, 0x51, 0x96, 0x01, 0xb7, 0x96, 0x01, 0x1d, 0x97, 0x01, 0x83, 0x97, 0x01, 0xe9, 0x97, 0x01, 0x4f, 0x98, 0x01, 0xb5, 0x98, 0x01, 0x1b, 0x99, 0x01, 0x81, 0x99, 0x01, 0xe7, 0x99, 0x01, 0x4d, 0x9a, 0x01, 0xb3, 0x9a, 0x01, 0x19, 0x9b, 0x01, 0x7f, 0x9b, 0x01, 0xe5, 0x9b, 0x01, 0x4b, 0x9c, 0x01, 0xb1, 0x9c, 0x01, 0x17, 0x9d, 0x01, 0x7d, 0x9d, 0x01, 0xe3, 0x9d, 0x01, 0x49, 0x9e, 0x01, 0xaf, 0x9e, 0x01, 0x15, 0x9f, 0x01, 0x7b, 0x9f, 0x01, 0xe1, 0x9f, 0x01, 0x47, 0xa0, 0x01, 0xad, 0xa0, 0x01, 0x13, 0xa1, 0x01, 0x79, 0xa1, 0x01, 0xdf, 0xa1, 0x01, 0x45, 0xa2, 0x01, 0xab, 0xa2, 0x01, 0x11, 0xa3, 0x01, 0x77, 0xa3, 0x01, 0xdd, 0xa3, 0x01, 0x43, 0xa4, 0x01, 0xa9, 0xa4, 0x01, 0x0f, 0xa5, 0x01, 0x75, 0xa5, 0x01, 0xdb, 0xa5, 0x01, 0x41, 0xa6, 0x01, 0xa7, 0xa6, 0x01, 0x0d, 0xa7, 0x01, 0x73, 0xa7, 0x01, 0xd9, 0xa7, 0x01, 0x3f, 0xa8, 0x01, 0xa5, 0xa8, 0x01, 0x0b, 0xa9, 0x01, 0x71, 0xa9, 0x01, 0xd7, 0xa9, 0x01, 0x3d, 0xaa, 0x01, 0xa3, 0xaa, 0x01, 0x09, 0xab, 0x01, 0x6f, 0xab, 0x01, 0xd5, 0xab, 0x01, 0x3b, 0xac, 0x01, 0xa1, 0xac, 0x01, 0x07, 0xad, 0x01, 0x6d, 0xad, 0x01, 0xd3, 0xad, 0x01, 0x39, 0xae, 0x01, 0x9f, 0xae, 0x01, 0x05, 0xaf, 0x01, 0x6b, 0xaf, 0x01, 0xd1, 0xaf, 0x01, 0x37, 0xb0, 0x01, 0x9d, 0xb0, 0x01, 0x03, 0xb1, 0x01, 0x69, 0xb1, 0x01, 0xcf, 0xb1, 0x01, 0x35, 0xb2, 0x01, 0x9b, 0xb2, 0x01, 0x01, 0xb3, 0x01, 0x67, 0xb3, 0x01, 0xcd, 0xb3, 0x01, 0x33, 0xb4, 0x01, 0x99, 0xb4, 0x01, 0xff, 0xb4, 0x01, 0x65, 0xb5, 0x01, 0xcb, 0xb5, 0x01, 0x31, 0xb6, 0x01, 0x97, 0xb6, 0x01, 0xfd, 0xb6, 0x01, 0x63, 0xb7, 0x01, 0xc9, 0xb7, 0x01, 0x2f, 0xb8, 0x01, 0x95, 0xb8, 0x01, 0xfb, 0xb8, 0x01, 0x61, 0xb9, 0x01, 0xc7, 0xb9, 0x01, 0x2d, 0xba, 0x01, 0x93, 0xba, 0x01, 0xf9, 0xba, 0x01, 0x5f, 0xbb, 0x01, 0xc5, 0xbb, 0x01, 0x2b, 0xbc, 0x01, 0x91, 0xbc, 0x01, 0xf7, 0xbc, 0x01, 0x5d, 0xbd, 0x01, 0xc3, 0xbd, 0x01, 0x29, 0xbe, 0x01, 0x8f, 0xbe, 0x01, 0xf5, 0xbe, 0x01, 0x5b, 0xbf, 0x01, 0xc1, 0xbf, 0x01, 0x27, 0xc0, 0x01, 0x8d, 0xc0, 0x01, 0xf3, 0xc0, 0x01, 0x59, 0xc1, 0x01, 0xbf, 0xc1, 0x01, 0x25, 0xc2, 0x01, 0x8b, 0xc2, 0x01, 0xf1, 0xc2, 0x01, 0x57, 0xc3, 0x01, 0xbd, 0xc3, 0x01, 0x23, 0xc4, 0x01, 0x89, 0xc4, 0x01, 0xef, 0xc4, 0x01, 0x55, 0xc5, 0x01, 0xbb, 0xc5, 0x01, 0x21, 0xc6, 0x01, 0x87, 0xc6, 0x01, 0xed, 0xc6, 0x01, 0x53, 0xc7, 0x01, 0xb9, 0xc7, 0x01, 0x1f, 0xc8, 0x01, 0x85, 0xc8, 0x01, 0xeb, 0xc8, 0x01, 0x51, 0xc9, 0x01, 0xb7, 0xc9, 0x01, 0x1d, 0xca, 0x01, 0x83, 0xca, 0x01, 0xe9, 0xca, 0x01, 0x4f, 0xcb, 0x01, 0xb5, 0xcb, 0x01, 0x1b, 0xcc, 0x01, 0x1f, 0x04, 0x07, 0x04, 0x04, 0x02, 0x03, 0x10, 0x00, 0x00, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x0a, 0x06, 0x00, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x10, 0x00, 0x00, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x1f, 0x00, 0x08, 0x00, 0x06, 0x00, 0x03, 0x0a, 0x06, 0x00, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x1e, 0x0b, 0x06, 0x04, 0x04, 0x03, 0x04, 0x0c, 0x04, 0x00, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x13, 0xf8, 0x01, 0x87, 0xf9, 0x01, 0x87, 0xf9, 0x01, 0x35, 0xee, 0x01, 0xa9, 0xf2, 0x01, 0xa9, 0xf2, 0x01, 0x35, 0xee, 0x01, 0xa9, 0xf2, 0x01, 0xa9, 0xf2, 0x01, 0x1e, 0x04, 0x0b, 0x04, 0x08, 0x02, 0x06, 0x04, 0x06, 0x06, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x18, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x0a, 0x06, 0x00, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x08, 0x04, 0x04, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0xb7, 0x11, 0x02, 0x21, 0x17, 0x02, 0x09, 0x1d, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x03, 0x05, 0x08, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0x7c, 0x00, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x73, 0x30, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xf0, 0x3c, 0x03, 0x55, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0xff, 0x00, 0x03, 0x55, 0x55, 0xff, 0x00, 0x3d, 0x55, 0x55, 0xff, 0x00, 0xcd, 0x55, 0x55, 0xcf, 0xff, 0x0d, 0x55, 0x55, 0x73, 0x30, 0x3d, 0x55, 0x55, 0x73, 0xf0, 0xf5, 0x55, 0x55, 0x73, 0xf0, 0x35, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x7f, 0x55, 0x57, 0xff, 0x55, 0xff, 0xd5, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x0f, 0x00, 0xf0, 0xd5, 0x57, 0x30, 0xc3, 0x0c, 0xd5, 0x57, 0x00, 0x3c, 0x00, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x57, 0x3f, 0xff, 0xfc, 0xd5, 0x57, 0xf0, 0xc3, 0x0f, 0xd5, 0x55, 0x73, 0xff, 0xcd, 0x55, 0x55, 0xc3, 0xff, 0xc3, 0x55, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x03, 0x00, 0xc0, 0xd5, 0x57, 0x0c, 0x00, 0x30, 0xd5, 0x57, 0x00, 0x3c, 0x00, 0xd5, 0x55, 0xc0, 0xff, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x3f, 0x0f, 0xc3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x00, 0xf0, 0x0d, 0x55, 0x55, 0xff, 0x0f, 0xf5, 0x55, 0x57, 0x33, 0xfc, 0xcd, 0x55, 0x57, 0xf3, 0xfc, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x30, 0x00, 0x0c, 0xd5, 0x57, 0x0c, 0x00, 0x30, 0xd5, 0x57, 0x00, 0xff, 0x00, 0xd5, 0x5f, 0x03, 0xff, 0xc0, 0xf5, 0x5c, 0xc3, 0xff, 0xc3, 0x35, 0x5f, 0x3f, 0xff, 0xfc, 0xf5, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0xc3, 0xff, 0xc3, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x7f, 0x55, 0x57, 0xff, 0x55, 0xff, 0xd5, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x03, 0x00, 0xc0, 0xd5, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x30, 0x3c, 0x0c, 0xd5, 0x55, 0xcc, 0x3c, 0x33, 0xd5, 0x55, 0xcc, 0x3c, 0x33, 0x55, 0x55, 0xc3, 0xc3, 0xc3, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xd7, 0xf5, 0x55, 0x55, 0x5f, 0x55, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x5c, 0x3f, 0xff, 0xc3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x55, 0xff, 0xff, 0xf5, 0x55, 0x55, 0xc0, 0x00, 0x35, 0x55, 0x57, 0x30, 0x00, 0xcd, 0x55, 0x57, 0xf0, 0x00, 0xfd, 0x55, 0x55, 0x70, 0x00, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0x55, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0x70, 0x00, 0x3d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x70, 0x0c, 0xd5, 0x55, 0x57, 0xc0, 0xfc, 0xd5, 0x55, 0x55, 0xf0, 0x3f, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0x57, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0x70, 0x00, 0x3d, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x30, 0xcd, 0x55, 0x55, 0xfc, 0x3f, 0xf5, 0x55, 0x55, 0x70, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x70, 0x3f, 0xf5, 0x55, 0x55, 0xc0, 0x0f, 0xf5, 0x55, 0x7f, 0xc0, 0x0f, 0xf5, 0x5f, 0xc0, 0xc0, 0x0f, 0x55, 0x5f, 0xc0, 0xc0, 0xcf, 0xd5, 0x55, 0xc0, 0xc0, 0xcf, 0xd5, 0x57, 0xc0, 0x3c, 0xcf, 0xf5, 0x5f, 0xfc, 0x03, 0x0f, 0xf5, 0x5f, 0xff, 0xff, 0xf7, 0xd5, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x3c, 0x03, 0xc3, 0x55, 0x5c, 0xc3, 0x0c, 0x33, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0xc3, 0x0c, 0x33, 0x55, 0x57, 0x30, 0xf0, 0xcc, 0xd5, 0x55, 0xff, 0xff, 0xf0, 0xd5, 0x55, 0x73, 0x0c, 0x03, 0x55, 0x55, 0xcc, 0xfc, 0x0d, 0x55, 0x55, 0xfc, 0xff, 0x0d, 0x55, 0x55, 0x5c, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x55, 0xf5, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x00, 0xc3, 0x00, 0xd5, 0x57, 0x3f, 0xc3, 0xfc, 0xd5, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x5c, 0xcc, 0x35, 0x55, 0x55, 0x73, 0xff, 0xcd, 0x55, 0x55, 0x70, 0xfc, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xc0, 0x30, 0x03, 0x55, 0x55, 0xc0, 0xc0, 0x03, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xfc, 0x00, 0x03, 0x55, 0x55, 0xff, 0x03, 0xc3, 0x55, 0x55, 0x7f, 0x03, 0x3d, 0x55, 0x55, 0x5f, 0xff, 0x35, 0x55, 0x55, 0x5c, 0xcc, 0x0d, 0x55, 0x55, 0x57, 0x3c, 0x03, 0x55, 0x55, 0x57, 0x3c, 0x3f, 0x55, 0x55, 0x57, 0xff, 0xf5, 0x55, 0x55, 0x55, 0x7d, 0xfd, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0x7f, 0x55, 0x55, 0x55, 0xff, 0xff, 0xd5, 0x55, 0x55, 0xff, 0xff, 0xd5, 0x55, 0x55, 0xff, 0x00, 0x35, 0x55, 0x57, 0xf0, 0x00, 0x3d, 0x55, 0x57, 0xc0, 0x03, 0x03, 0x55, 0x57, 0x00, 0x3c, 0x03, 0x55, 0x57, 0x00, 0x00, 0x0f, 0x55, 0x57, 0x00, 0x00, 0x35, 0x55, 0x57, 0xc0, 0x03, 0xd5, 0x55, 0x55, 0x7f, 0xff, 0x55, 0x55, 0x55, 0xc0, 0xcf, 0x55, 0x55, 0x57, 0x30, 0xfd, 0x55, 0x55, 0x57, 0xf0, 0xfd, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x7d, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xf5, 0x55, 0x55, 0x5f, 0xfd, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0x00, 0x0d, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x0f, 0xc3, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0x70, 0x00, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x5c, 0x3c, 0xd5, 0x55, 0x55, 0x5f, 0x0f, 0xd5, 0x55, 0x55, 0x5c, 0xff, 0xd5, 0x55, 0x55, 0x70, 0x0f, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3c, 0x0f, 0x55, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0xc0, 0x00, 0xff, 0x55, 0x55, 0xc0, 0xf0, 0xff, 0x55, 0x55, 0x70, 0xcc, 0xfd, 0x55, 0x55, 0x5f, 0xcf, 0xd5, 0x55, 0x55, 0x5c, 0xcc, 0xd5, 0x55, 0x55, 0x5c, 0x3f, 0xd5, 0x55, 0x55, 0x5c, 0x0f, 0xd5, 0x55, 0x55, 0x70, 0x0f, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x55, 0xfd, 0x55, 0x55, 0x7f, 0xdf, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0xc3, 0x55, 0x55, 0xcc, 0x00, 0x03, 0x55, 0x55, 0x73, 0x00, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x73, 0x30, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0x7f, 0x55, 0x55, 0xff, 0xd5, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0xd5, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0x70, 0x00, 0x03, 0x55, 0x55, 0xc3, 0x00, 0x30, 0xd5, 0x55, 0xcc, 0xc0, 0xcc, 0xd5, 0x55, 0xc3, 0x00, 0x30, 0xd5, 0x57, 0xc0, 0x3f, 0x00, 0xd5, 0x57, 0x30, 0xff, 0xc3, 0x55, 0x55, 0xcf, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xc3, 0xfc, 0x03, 0x55, 0x55, 0xc3, 0xfc, 0x3c, 0xd5, 0x55, 0x7f, 0xfc, 0x37, 0xd5, 0x55, 0x5f, 0x7f, 0xd5, 0x55, 0x55, 0x55, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x3c, 0x03, 0xc3, 0x55, 0x5c, 0xf3, 0x0f, 0x33, 0x55, 0x5c, 0xff, 0x0f, 0xf3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x0f, 0xf0, 0x0d, 0x55, 0x55, 0xfc, 0x3f, 0xf5, 0x55, 0x55, 0xc3, 0xcc, 0x3d, 0x55, 0x55, 0x70, 0xfc, 0xf3, 0x55, 0x55, 0x70, 0xfc, 0xdf, 0x55, 0x55, 0x7f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xcd, 0x55, 0x5f, 0xff, 0xff, 0xfd, 0x55, 0x7f, 0xff, 0xff, 0xd5, 0x55, 0x70, 0x00, 0x03, 0xd5, 0x55, 0xff, 0xff, 0xfc, 0xd5, 0x55, 0xc0, 0x00, 0x0f, 0xd5, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0x7c, 0x00, 0x0c, 0xd5, 0x55, 0x5f, 0xff, 0xf0, 0x35, 0x55, 0x7f, 0x3f, 0xfc, 0x0d, 0x55, 0x7f, 0x3f, 0xfc, 0x0d, 0x55, 0x70, 0x00, 0x3c, 0x0d, 0x55, 0x7f, 0xff, 0xf0, 0x0d, 0x55, 0x5f, 0xff, 0xdf, 0xf5, 0x55, 0x7f, 0xdf, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0x55, 0x55, 0x55, 0x57, 0x35, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0xff, 0xff, 0x55, 0x55, 0x5f, 0xff, 0xff, 0x55, 0x55, 0x70, 0x00, 0x0f, 0x55, 0x55, 0x7f, 0xff, 0xf3, 0xfd, 0x55, 0xc0, 0x00, 0x0c, 0xc3, 0x55, 0xc0, 0x00, 0x03, 0xc3, 0x55, 0xc0, 0x00, 0x03, 0x03, 0x55, 0xf0, 0x03, 0x03, 0xc3, 0x55, 0xc3, 0xc0, 0x0f, 0xc3, 0x55, 0xc3, 0xc0, 0x3f, 0x0d, 0x55, 0x7f, 0xff, 0xfc, 0x35, 0x5d, 0xff, 0x3f, 0xf3, 0xd5, 0x5f, 0x00, 0x00, 0xfd, 0x55, 0x5f, 0xff, 0xff, 0x3d, 0x55, 0x55, 0xff, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xff, 0x55, 0x55, 0x7f, 0xff, 0xff, 0xd5, 0x55, 0xf0, 0x00, 0x03, 0xf5, 0x55, 0xcf, 0xff, 0xfc, 0xf5, 0x55, 0xf0, 0x00, 0x03, 0xff, 0x57, 0x0f, 0xc0, 0xfc, 0xf3, 0x57, 0x33, 0xc3, 0x3c, 0xdf, 0x57, 0x33, 0xc3, 0x3c, 0xd5, 0x57, 0x0f, 0xc0, 0xfc, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x35, 0x55, 0xff, 0xff, 0xfc, 0x0d, 0x57, 0xff, 0xcf, 0xf3, 0x0d, 0x5c, 0xff, 0xcf, 0xff, 0x0d, 0x57, 0x70, 0x00, 0x0c, 0x0d, 0x55, 0x7f, 0xff, 0xf7, 0xf5, 0x55, 0x57, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xf7, 0xfd, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xff, 0xf5, 0x55, 0x70, 0x00, 0xff, 0xff, 0x55, 0x7f, 0xfc, 0x03, 0xf3, 0x55, 0xf0, 0xff, 0xf0, 0xdf, 0x55, 0xf0, 0xf3, 0x0f, 0xd5, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xff, 0xf0, 0x33, 0x55, 0x57, 0x3f, 0xc0, 0xff, 0xd5, 0x57, 0xcf, 0xff, 0xfc, 0x35, 0x55, 0xff, 0x3f, 0xfc, 0x0d, 0x55, 0x7f, 0x3f, 0xf0, 0x0d, 0x55, 0x7f, 0x3f, 0xf0, 0x0d, 0x55, 0x70, 0x00, 0xf0, 0x0d, 0x55, 0x5f, 0xff, 0xdf, 0xf5, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x55, 0xf7, 0xd5, 0x55, 0x30, 0x1f, 0x01, 0x55, 0x40, 0x00, 0x00, 0x00, 0x15, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x11, 0x41, 0x50, 0x00, 0x00, 0x15, 0x55, 0x55, 0x54, 0x04, 0x10, 0x01, 0x55, 0x41, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa1, 0x14, 0x15, 0x54, 0x01, 0x11, 0x45, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa5, 0x54, 0x15, 0x54, 0x01, 0x55, 0x45, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa1, 0x14, 0x44, 0x11, 0x55, 0x55, 0x55, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x15, 0x40, 0x01, 0x55, 0x11, 0x56, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x95, 0x40, 0x01, 0x55, 0x55, 0x56, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x95, 0x55, 0x55, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x55, 0x50, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x01, 0x50, 0x55, 0x50, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x15, 0x55, 0x55, 0x54, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x02, 0x55, 0x55, 0x55, 0x00, 0x04, 0x00, 0x80, 0x28, 0x00, 0x00, 0xa0, 0x02, 0x01, 0x15, 0x55, 0x10, 0x04, 0x55, 0x80, 0x28, 0x00, 0x00, 0xa0, 0x02, 0x01, 0x15, 0x55, 0x01, 0x55, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x02, 0x55, 0x55, 0x55, 0x01, 0x01, 0x00, 0x80, 0xaa, 0xaa, 0xaa, 0xa8, 0x02, 0x00, 0x04, 0x01, 0x01, 0x55, 0x00, 0x82, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x04, 0x01, 0x00, 0x41, 0x00, 0x82, 0xaa, 0xaa, 0xaa, 0xaa, 0x02, 0x00, 0x04, 0x01, 0x55, 0x5a, 0xa5, 0x80, 0x95, 0x95, 0x80, 0x00, 0x02, 0x55, 0x54, 0x01, 0x00, 0x25, 0x58, 0x80, 0x95, 0x95, 0x85, 0x54, 0x0a, 0xaa, 0xa8, 0x01, 0x00, 0x26, 0x98, 0x80, 0x95, 0x95, 0x85, 0x54, 0x08, 0x00, 0x09, 0x55, 0x00, 0x25, 0x58, 0x80, 0x95, 0x95, 0xaa, 0xaa, 0x08, 0x88, 0x88, 0x00, 0x00, 0x20, 0x08, 0x95, 0x95, 0x95, 0x80, 0x02, 0x58, 0x88, 0x88, 0x00, 0xaa, 0xa0, 0x0a, 0x95, 0x95, 0x95, 0x80, 0x02, 0x58, 0x00, 0x0a, 0xaa, 0x04, 0x20, 0x08, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa9, 0x55, 0x58, 0x00, 0x00, 0x0a, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xaa, 0xa9, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0x42, 0x82, 0x20, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa6, 0x86, 0x26, 0x62, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x45, 0x86, 0x24, 0xa4, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xa4, 0xa1, 0x61, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x61, 0x40, 0xa2, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0xaa, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa9, 0x55, 0x69, 0x55, 0x6a, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x9a, 0xa9, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x59, 0x59, 0x6a, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x98, 0x49, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x95, 0x55, 0xaa, 0x95, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa5, 0x56, 0xaa, 0x40, 0x68, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa8, 0x0a, 0xa5, 0x55, 0x58, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa9, 0x5a, 0xa5, 0x55, 0x58, 0x00, 0x95, 0x5a, 0x69, 0xa5, 0x56, 0x02, 0xa5, 0x96, 0xa9, 0x69, 0x68, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x96, 0x5a, 0x69, 0xa5, 0x96, 0x54, 0x54, 0x54, 0x54, 0x54, 0x55, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x54, 0x54, 0x54, 0x54, 0x54, 0x55, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x30, 0x1f, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x15, 0x00, 0x00, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x55, 0x00, 0x01, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x40, 0x51, 0x55, 0x55, 0x15, 0x54, 0x00, 0x00, 0x15, 0x54, 0x55, 0x55, 0x45, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x40, 0x00, 0x44, 0x11, 0x10, 0x11, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x44, 0x04, 0x44, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x40, 0x00, 0x44, 0x15, 0x05, 0x41, 0x50, 0x05, 0x55, 0x55, 0x50, 0x05, 0x41, 0x50, 0x54, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x50, 0x40, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x50, 0x40, 0x01, 0x00, 0x01, 0x00, 0x17, 0xfc, 0x3f, 0xfc, 0x00, 0x43, 0xff, 0xc0, 0x01, 0x00, 0x01, 0x00, 0x1f, 0xf4, 0xff, 0xd4, 0x00, 0x4f, 0xfc, 0x40, 0x01, 0x55, 0x55, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x40, 0x01, 0x11, 0x11, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x40, 0x01, 0x00, 0x01, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xc0, 0x01, 0x05, 0x41, 0x00, 0xf0, 0xfc, 0x03, 0xff, 0xff, 0x00, 0x00, 0xc0, 0x01, 0x05, 0x41, 0x00, 0xf0, 0xf3, 0x0c, 0x71, 0xc7, 0x33, 0x30, 0xc0, 0xaa, 0xaa, 0xaa, 0xaa, 0xf0, 0xf3, 0x0d, 0x75, 0xd7, 0x33, 0x30, 0xea, 0x55, 0x55, 0x55, 0x55, 0xf0, 0xfc, 0x0d, 0x34, 0xd3, 0x33, 0x30, 0xd5, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x0d, 0x34, 0xc3, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x03, 0xff, 0xff, 0xaa, 0xaa, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 0xc0, 0x00, 0xfc, 0x0f, 0xc0, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x3a, 0xbf, 0xfa, 0xab, 0xff, 0xbf, 0xfb, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0xff, 0xff, 0xcf, 0xfc, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf0, 0x03, 0xff, 0x3f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xc0, 0x00, 0xfc, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x55, 0x51, 0x55, 0x55, 0x15, 0x54, 0x00, 0x00, 0x15, 0x10, 0x00, 0x00, 0x40, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x40, 0x11, 0x10, 0x11, 0x10, 0x04, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x40, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x15, 0x55, 0x55, 0x40, 0x15, 0x05, 0x41, 0x50, 0x05, 0x55, 0x55, 0x50, 0x00, 0x00, 0x00, 0x00, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf5, 0xff, 0xf0, 0x00, 0x0f, 0xff, 0x00, 0x50, 0x50, 0x50, 0x50, 0x3f, 0xc3, 0xff, 0x00, 0x14, 0x3f, 0xf4, 0x14, 0x55, 0x50, 0x55, 0x50, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x54, 0x55, 0x50, 0x55, 0x50, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x54, 0x55, 0x55, 0x55, 0x53, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x54, 0x40, 0x10, 0x40, 0x13, 0xc3, 0xf0, 0x0f, 0xff, 0xfc, 0x00, 0x03, 0x04, 0x50, 0x50, 0x50, 0x53, 0xc3, 0xcc, 0x31, 0xc7, 0x1c, 0xcc, 0xc3, 0x14, 0x40, 0x10, 0x40, 0x13, 0xc3, 0xcc, 0x35, 0xd7, 0x5c, 0xcc, 0xc3, 0x04, 0xaa, 0xaa, 0xaa, 0xab, 0xc3, 0xf0, 0x34, 0xd3, 0x4c, 0xcc, 0xc3, 0xaa, 0x55, 0x55, 0x55, 0x57, 0x00, 0x00, 0x34, 0xd3, 0x0c, 0x00, 0x03, 0x55, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x0f, 0xff, 0xfe, 0xaa, 0xab, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x3f, 0x00, 0x03, 0xf0, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xea, 0xff, 0xea, 0xaf, 0xfe, 0xff, 0xec, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf3, 0xff, 0xff, 0x3f, 0xf3, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x0f, 0xfc, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x03, 0xf0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xfd, 0x7d, 0x7f, 0x5d, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x5d, 0xd5, 0xd7, 0x75, 0xdd, 0xd5, 0x55, 0x55, 0x55, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x30, 0xcc, 0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0xc0, 0xff, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xc0, 0xc3, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0x3f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xfc, 0x3f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x03, 0xc0, 0x30, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0xf3, 0xff, 0xff, 0xcf, 0x00, 0x00, 0x0f, 0xf0, 0x70, 0x0f, 0x55, 0x55, 0xc3, 0x0c, 0x30, 0xc3, 0x55, 0x55, 0xf0, 0x0d, 0xc3, 0x30, 0xd5, 0xff, 0x7c, 0xcf, 0xf3, 0x3d, 0xff, 0x57, 0x0c, 0xc3, 0xc0, 0x3f, 0x5f, 0x03, 0x57, 0xcf, 0xf3, 0xd5, 0xc0, 0xf5, 0xfc, 0x03, 0xc0, 0x30, 0xdc, 0x0d, 0x5f, 0xff, 0xff, 0xf5, 0x70, 0x37, 0x0c, 0x03, 0x7f, 0xff, 0x5f, 0xf5, 0x5f, 0x55, 0x55, 0xf5, 0x5f, 0xf5, 0xff, 0xfd, 0x30, 0x1f, 0xa4, 0x00, 0xa4, 0x01, 0x90, 0x00, 0x64, 0x06, 0x40, 0x1a, 0x00, 0x16, 0xa9, 0x40, 0x09, 0x00, 0x40, 0x00, 0x10, 0x01, 0x00, 0x60, 0x01, 0x6a, 0x2a, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xaa, 0x00, 0xa5, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x01, 0x6a, 0x80, 0x00, 0x01, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x30, 0xc0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x00, 0x05, 0x94, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x15, 0x56, 0xa5, 0x55, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x15, 0x40, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x29, 0x50, 0x15, 0x68, 0x00, 0x40, 0x07, 0xf0, 0x0f, 0xc0, 0x10, 0x00, 0x0a, 0xa5, 0x6a, 0x80, 0x01, 0x00, 0x1f, 0xfc, 0x3f, 0xf0, 0x04, 0x00, 0x00, 0xaa, 0xa8, 0x00, 0x15, 0x00, 0x1f, 0xff, 0xff, 0xf0, 0x05, 0x40, 0x00, 0x0a, 0xa0, 0x00, 0x04, 0x00, 0x5c, 0x00, 0x00, 0x30, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xf0, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xc0, 0x33, 0x00, 0x00, 0xcc, 0x03, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x30, 0x03, 0xc0, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x0c, 0x30, 0x03, 0xc0, 0x0c, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x3c, 0x03, 0xc0, 0x3c, 0xff, 0xc0, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0xc3, 0xff, 0xff, 0xc3, 0x00, 0x00, 0x0f, 0xf0, 0x30, 0x0c, 0x00, 0x00, 0xcc, 0x30, 0x0c, 0x33, 0x00, 0x00, 0x30, 0x0c, 0xc3, 0x0f, 0x00, 0x00, 0x3f, 0x3f, 0xfc, 0xfc, 0x00, 0x00, 0xf0, 0xc3, 0xc0, 0x30, 0xc0, 0x00, 0x03, 0x3f, 0xfc, 0xc0, 0x00, 0x03, 0x0c, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0xfc, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x3f, 0xfc, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x30, 0x30, 0xc0, 0x00, 0x00, 0x3c, 0x3c, 0x00, 0x00, 0x03, 0x0c, 0x0c, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x0c, 0x30, 0x00, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xfd, 0x7d, 0x7f, 0x5d, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x5d, 0xd5, 0xd7, 0x75, 0xdd, 0xd5, 0x55, 0x55, 0x55, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x30, 0xcc, 0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0xc0, 0xff, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xc0, 0xc3, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x70, 0x0f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xf0, 0x0d, 0xc3, 0x30, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x0c, 0xc3, 0xc0, 0x3f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfc, 0x03, 0xc0, 0x30, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x0c, 0x03, 0x7f, 0xff, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xfd, 0x30, 0x1f, 0xa4, 0x00, 0xa4, 0x01, 0x90, 0x00, 0x64, 0x06, 0x40, 0x1a, 0x00, 0x16, 0xa9, 0x40, 0x09, 0x00, 0x40, 0x00, 0x10, 0x01, 0x00, 0x60, 0x01, 0x6a, 0x2a, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xaa, 0x00, 0xa5, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x01, 0x6a, 0x80, 0x00, 0x01, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x30, 0xc0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x00, 0x05, 0x94, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x15, 0x56, 0xa5, 0x55, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x15, 0x40, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x29, 0x50, 0x15, 0x68, 0x00, 0x40, 0x04, 0x00, 0x04, 0x00, 0x10, 0x00, 0x0a, 0xa5, 0x6a, 0x80, 0x01, 0x00, 0x14, 0x00, 0x05, 0x00, 0x04, 0x00, 0x00, 0xaa, 0xa8, 0x00, 0x15, 0x00, 0x15, 0x00, 0x15, 0x00, 0x05, 0x40, 0x00, 0x0a, 0xa0, 0x00, 0x04, 0x00, 0x54, 0x00, 0x05, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x30, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0c, 0xc3, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xc3, 0xc0, 0x30, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x30, 0x30, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x0c, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xfc, 0x00, 0xc3, 0x0f, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xc3, 0x00, 0xc3, 0x30, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xcc, 0xc3, 0x00, 0xff, 0x30, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xfc, 0x00, 0xc3, 0x30, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xc0, 0x00, 0xc3, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x3f, 0x0f, 0xcf, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0xcc, 0x0c, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0xcf, 0xcf, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0x0f, 0xcf, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x30, 0xcc, 0x33, 0x0c, 0xfc, 0xfc, 0x00, 0x00, 0xc0, 0x00, 0x00, 0xc3, 0x30, 0xcf, 0x33, 0xcc, 0xc0, 0xc3, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc3, 0x30, 0xcc, 0xf3, 0x3c, 0xfc, 0xc3, 0x00, 0x00, 0xfc, 0x00, 0x00, 0xfc, 0x30, 0xcc, 0x33, 0x0c, 0xc0, 0xfc, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc3, 0x0f, 0x0c, 0x33, 0x0c, 0xfc, 0xc3, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x1f, 0x05, 0x55, 0x55, 0x55, 0x55, 0x55, 0x54, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x05, 0x54, 0x55, 0x45, 0x51, 0x10, 0x00, 0x04, 0x04, 0x55, 0x44, 0x51, 0x11, 0x55, 0x44, 0x04, 0x44, 0x44, 0x51, 0x11, 0x00, 0x44, 0x04, 0x44, 0x44, 0x51, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x00, 0x00, 0x00, 0x05, 0x41, 0x10, 0x00, 0x00, 0x00, 0x00, 0x04, 0x41, 0x10, 0x00, 0x00, 0x10, 0x55, 0x05, 0x41, 0x10, 0x54, 0x00, 0x55, 0x45, 0x10, 0x11, 0x11, 0x01, 0x40, 0x55, 0x54, 0x10, 0x11, 0x11, 0x00, 0x10, 0x55, 0x54, 0x15, 0x51, 0x11, 0x41, 0x11, 0x51, 0x10, 0x04, 0x41, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x50, 0x50, 0x00, 0x00, 0x10, 0x01, 0x10, 0x55, 0x50, 0x55, 0x00, 0x55, 0x01, 0x10, 0x44, 0x51, 0x00, 0x51, 0x00, 0x41, 0x10, 0x40, 0x11, 0x04, 0x41, 0x11, 0x41, 0x10, 0x15, 0x41, 0x00, 0x41, 0x00, 0x41, 0x10, 0x10, 0x41, 0x00, 0x40, 0x41, 0x01, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x55, 0x55, 0x55, 0x55, 0x55, 0x41, 0x10, 0x40, 0x00, 0x00, 0x00, 0x00, 0x41, 0x10, 0x55, 0x55, 0x55, 0x55, 0x55, 0x41, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x15, 0x50, 0x00, 0x00, 0x00, 0x01, 0x55, 0x12, 0x0c, 0x57, 0xf5, 0x7d, 0x55, 0x50, 0x5f, 0xfd, 0xff, 0x55, 0x50, 0x5f, 0xff, 0xff, 0x55, 0x50, 0x5f, 0xff, 0xff, 0xd5, 0x50, 0x7c, 0x00, 0x00, 0xd5, 0x50, 0x70, 0x0f, 0xc3, 0xd5, 0x50, 0x70, 0x33, 0xc3, 0xd5, 0x50, 0x70, 0x33, 0xc3, 0xd5, 0x50, 0x70, 0x0f, 0xc3, 0xd5, 0x50, 0x5c, 0x00, 0x0f, 0x55, 0x50, 0x57, 0xff, 0xfd, 0x55, 0x50, 0x5c, 0x3c, 0x33, 0x55, 0x50, 0x12, 0x0c, 0x55, 0xfd, 0x5f, 0x55, 0x50, 0x57, 0xff, 0x7f, 0xd5, 0x50, 0x57, 0xff, 0xff, 0xd5, 0x50, 0x57, 0xff, 0xff, 0xf5, 0x50, 0x5f, 0x00, 0x00, 0x35, 0x50, 0x5c, 0x03, 0xc0, 0x35, 0x50, 0x5c, 0x0c, 0x30, 0xf5, 0x50, 0x5c, 0x00, 0x00, 0x35, 0x50, 0x5c, 0x0c, 0x0f, 0xf5, 0x50, 0x57, 0x33, 0x0f, 0xd5, 0x50, 0x55, 0xf3, 0xff, 0x35, 0x50, 0x55, 0xc3, 0xc3, 0xf5, 0x50, 0x12, 0x0c, 0x5f, 0xd5, 0x7f, 0xff, 0xf0, 0x7f, 0xf5, 0xff, 0x00, 0x30, 0x7f, 0xff, 0xff, 0x00, 0x30, 0x7f, 0xff, 0xff, 0x00, 0x30, 0x70, 0x00, 0x03, 0x00, 0x30, 0xc3, 0xf0, 0x3f, 0x00, 0x30, 0xcc, 0xf0, 0xcf, 0x00, 0x30, 0xcc, 0xf0, 0xcf, 0x00, 0x30, 0xc3, 0xf0, 0x3f, 0xff, 0xf0, 0x70, 0x0f, 0x00, 0xcd, 0x50, 0x5f, 0xff, 0xff, 0x35, 0x50, 0x70, 0x30, 0x3c, 0xd5, 0x50, 0x12, 0x0c, 0x55, 0xfd, 0x57, 0xd5, 0x50, 0x57, 0xff, 0xdf, 0xf5, 0x50, 0x57, 0xff, 0xff, 0xfd, 0x50, 0x55, 0xff, 0xff, 0xfd, 0x50, 0x57, 0xc0, 0x00, 0x0d, 0x50, 0x57, 0x00, 0x00, 0x0d, 0x50, 0x57, 0x00, 0x00, 0x0d, 0x50, 0x57, 0x0f, 0xf0, 0x0d, 0x50, 0x57, 0x00, 0x00, 0xcd, 0x50, 0x55, 0xc0, 0x03, 0x35, 0x50, 0x55, 0x7f, 0xff, 0xd5, 0x50, 0x55, 0xc3, 0xc3, 0xd5, 0x50, 0x12, 0x0c, 0x57, 0xf5, 0x5f, 0xd5, 0x50, 0x5f, 0xfd, 0x7f, 0xf5, 0x50, 0x5f, 0xff, 0xff, 0xf5, 0x50, 0x5f, 0xff, 0xff, 0xf5, 0x50, 0x5c, 0x00, 0x00, 0x35, 0x50, 0x70, 0x00, 0x00, 0x0d, 0x50, 0x70, 0x30, 0x0c, 0x0d, 0x50, 0x70, 0xc0, 0x03, 0x0d, 0x50, 0x70, 0x03, 0xc0, 0x0d, 0x50, 0x5c, 0x0f, 0xf0, 0x35, 0x50, 0x57, 0xff, 0xff, 0xd5, 0x50, 0x55, 0xcc, 0x33, 0x55, 0x50, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfa, 0xaa, 0xab, 0xc0, 0xff, 0xe5, 0x55, 0x5a, 0xc0, 0xff, 0xe5, 0x55, 0x5a, 0xc0, 0xff, 0x95, 0x55, 0x66, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0xaa, 0xaa, 0xab, 0xc0, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfe, 0xaa, 0xaa, 0xc0, 0xff, 0xfe, 0x55, 0x56, 0xc0, 0xff, 0xfe, 0x55, 0x56, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xea, 0xaa, 0xaa, 0xc0, 0xff, 0xea, 0xaa, 0xaa, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0xaa, 0xaa, 0xab, 0xc0, 0x08, 0x08, 0x7f, 0xf5, 0xff, 0xfd, 0xc3, 0x0d, 0xff, 0xfd, 0xff, 0xfd, 0xfc, 0xfd, 0x7f, 0xf5, 0x77, 0x75, 0x10, 0x03, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xc0, 0x03, 0x03, 0xff, 0xff, 0xff, 0xff, 0x10, 0x03, 0x55, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x03, 0x55, 0x55, 0xff, 0xff, 0x55, 0x08, 0x08, 0x55, 0x75, 0x55, 0x75, 0x55, 0x75, 0x5f, 0x75, 0x70, 0xf5, 0x70, 0xd5, 0x5f, 0x55, 0x55, 0x55, 0x08, 0x08, 0x55, 0x75, 0x55, 0x75, 0x55, 0x75, 0x5f, 0x75, 0x7f, 0xf5, 0x7f, 0xd5, 0x5f, 0x55, 0x55, 0x55, 0x08, 0x08, 0x55, 0xd5, 0x55, 0xf5, 0x55, 0xfd, 0x7d, 0xdd, 0xff, 0xd5, 0xff, 0x55, 0x7d, 0x55, 0x55, 0x55, 0x08, 0x08, 0x5f, 0xfd, 0x5d, 0x5d, 0x5d, 0x5d, 0x5d, 0x5d, 0xfd, 0xfd, 0xfd, 0xfd, 0xf5, 0xf5, 0x55, 0x55, 0x01, 0x01, 0x00, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x7f, 0xfd, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x5f, 0xfd, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x7f, 0xfd, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x5f, 0xfd, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x7f, 0xfd, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0x03, 0x5f, 0xfd, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x08, 0x08, 0x50, 0x05, 0x43, 0xc1, 0x00, 0x00, 0x30, 0xcc, 0x33, 0x0c, 0x00, 0x00, 0x43, 0xc1, 0x50, 0x05, 0x08, 0x08, 0xc0, 0x03, 0x33, 0xcc, 0x00, 0x30, 0x33, 0x0c, 0x30, 0xcc, 0x0c, 0x00, 0x33, 0xcc, 0xc0, 0x03, 0x08, 0x08, 0x57, 0xd5, 0x5c, 0x35, 0x5c, 0x35, 0xdc, 0x37, 0xd7, 0xd7, 0xdf, 0xf7, 0xfd, 0x7f, 0xf7, 0xdf, 0x04, 0x1f, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x02, 0x05, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0x06, 0x20, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0x20, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf7, 0xff, 0x5f, 0x5f, 0xd7, 0xff, 0x75, 0x5d, 0x55, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x57, 0xd5, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x55, 0x75, 0x75, 0x7f, 0xdf, 0xd5, 0x75, 0x75, 0x55, 0x75, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x55, 0x5f, 0xd5, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x08, 0x7f, 0x5f, 0x57, 0xd7, 0x57, 0xd5, 0x75, 0xdd, 0x77, 0x57, 0xdf, 0x75, 0xdd, 0x77, 0x57, 0xd7, 0x75, 0xdf, 0xf7, 0x55, 0x7d, 0x5f, 0x5d, 0x77, 0xf7, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x0c, 0x7f, 0x5f, 0x5d, 0x5d, 0xfd, 0xd5, 0x75, 0xdf, 0x7d, 0xd5, 0xdf, 0x75, 0xdf, 0xfd, 0xfd, 0xd7, 0x7f, 0xdd, 0xdd, 0xd5, 0x7f, 0x75, 0xdd, 0x5d, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7d, 0x75, 0x77, 0xf7, 0xf5, 0xd7, 0x75, 0x77, 0x57, 0x5d, 0xd7, 0x5d, 0xd7, 0xf7, 0x5d, 0xd7, 0x5d, 0xd7, 0x57, 0xf5, 0x7d, 0x57, 0x57, 0xf7, 0x5d, 0x55, 0x55, 0x55, 0x55, 0x55, 0x20, 0x0c, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xff, 0x55, 0xc3, 0x7d, 0x55, 0x55, 0x55, 0x70, 0x00, 0xd5, 0x70, 0xff, 0x55, 0x55, 0x55, 0xc0, 0x00, 0x35, 0x7c, 0x3f, 0xd5, 0x55, 0x57, 0x00, 0x03, 0x0d, 0x5f, 0xff, 0xff, 0xff, 0xfc, 0x03, 0x00, 0x0d, 0x70, 0x00, 0x03, 0xc0, 0x00, 0x00, 0x3f, 0xfd, 0x7f, 0xff, 0xfc, 0x30, 0x00, 0x00, 0xc0, 0x03, 0xc0, 0x00, 0x03, 0x30, 0x00, 0x03, 0x0f, 0xfc, 0xc0, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc0, 0x03, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x01, 0x01, 0x00, 0x10, 0x10, 0x55, 0x7d, 0x55, 0xf5, 0x55, 0xc3, 0x57, 0x0d, 0x55, 0xc0, 0xdc, 0x0d, 0x55, 0x70, 0xdc, 0x3d, 0x55, 0x5c, 0x30, 0x35, 0x55, 0x70, 0x00, 0xd5, 0x55, 0xc3, 0xfc, 0xd5, 0x55, 0xcf, 0xff, 0x35, 0x57, 0x0f, 0xff, 0x35, 0x57, 0x00, 0xfc, 0x35, 0x57, 0xc0 }; //uint8_t v[] = { 0x0a, 0xaa, 0x55, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x55, 0x03, 0x03, 0x03, 0x00, 0x00, 0x10, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0xc4, 0x00, 0x00, 0xdc, 0x00, 0x00, 0x0f, 0x01, 0x00, 0x91, 0x01, 0x00, 0x0d, 0x02, 0x00, 0x89, 0x02, 0x00, 0xd1, 0x02, 0x00, 0x1f, 0x06, 0x00, 0x67, 0x0f, 0x00, 0x67, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x12, 0x00, 0xa7, 0x12, 0x00, 0x0d, 0x13, 0x00, 0x73, 0x13, 0x00, 0xd9, 0x13, 0x00, 0x3f, 0x14, 0x00, 0xa5, 0x14, 0x00, 0x0b, 0x15, 0x00, 0x71, 0x15, 0x00, 0xd7, 0x15, 0x00, 0x3d, 0x16, 0x00, 0xa3, 0x16, 0x00, 0x09, 0x17, 0x00, 0x6f, 0x17, 0x00, 0xd5, 0x17, 0x00, 0x3b, 0x18, 0x00, 0xa1, 0x18, 0x00, 0x07, 0x19, 0x00, 0x6d, 0x19, 0x00, 0xd3, 0x19, 0x00, 0x39, 0x1a, 0x00, 0x9f, 0x1a, 0x00, 0x05, 0x1b, 0x00, 0x6b, 0x1b, 0x00, 0xd1, 0x1b, 0x00, 0x37, 0x1c, 0x00, 0x9d, 0x1c, 0x00, 0x13, 0x1e, 0x00, 0x89, 0x1f, 0x00, 0xff, 0x20, 0x00, 0x75, 0x22, 0x00, 0xeb, 0x23, 0x00, 0x61, 0x25, 0x00, 0xd7, 0x26, 0x00, 0x4d, 0x28, 0x00, 0xeb, 0x28, 0x00, 0x89, 0x29, 0x00, 0x64, 0x2a, 0x00, 0xa2, 0x2a, 0x00, 0xe0, 0x2a, 0x00, 0x1e, 0x2b, 0x00, 0x5c, 0x2b, 0x00, 0xce, 0x00, 0x00, 0xf1, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x44, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};// 0x70, 0x2c, 0x00, 0x82, 0x2c, 0x00, 0x90, 0x2c, 0x00, 0x9e, 0x2c, 0x00, 0xb0, 0x2c, 0x00, 0xc2, 0x2c, 0x00, 0xd4, 0x2c, 0x00, 0xe6, 0x2c, 0x00, 0xe9, 0x2c, 0x00, 0x1b, 0x2d, 0x00, 0x4d, 0x2d, 0x00, 0x7f, 0x2d, 0x00, 0xb1, 0x2d, 0x00, 0xe3, 0x2d, 0x00, 0x15, 0x2e, 0x00, 0x27, 0x2e, 0x00, 0x39, 0x2e, 0x00, 0x4b, 0x2e, 0x00, 0x6c, 0x2e, 0x00, 0x73, 0x2e, 0x00, 0xb5, 0x2e, 0x00, 0xf7, 0x2e, 0x00, 0x21, 0x2f, 0x00, 0x5f, 0x2f, 0x00, 0xc1, 0x2f, 0x00, 0x02, 0x00, 0x06, 0x03, 0x04, 0x09, 0x0a, 0x05, 0x08, 0x07, 0x00, 0x00, 0x58, 0x00, 0x00, 0x32, 0x00, 0x00, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x10, 0x00, 0x00, 0x08, 0x00, 0x00, 0x50, 0x04, 0x00, 0x30, 0x02, 0x00, 0x20, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00, 0x50, 0x08, 0x00, 0x50, 0x11, 0x00, 0x00, 0x00, 0x28, 0x00, 0x40, 0x15, 0x00, 0x60, 0x12, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x45, 0x00, 0x00, 0x35, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x22, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00, 0x22, 0x00, 0x00, 0x13, 0x00, 0x01, 0x00, 0x02, 0x00, 0x50, 0x01, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x04, 0xff, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x02, 0xff, 0x01, 0x01, 0x00, 0x1e, 0x01, 0x00, 0x03, 0xff, 0x01, 0x01, 0x00, 0x2d, 0x01, 0x00, 0x04, 0xfe, 0x01, 0x01, 0x00, 0x3c, 0x01, 0x00, 0x05, 0xfe, 0x01, 0x01, 0x00, 0x4b, 0x02, 0x00, 0x06, 0xfe, 0x02, 0x02, 0x00, 0x5a, 0x02, 0x00, 0x07, 0xfd, 0x02, 0x02, 0x00, 0x63, 0x02, 0x00, 0x08, 0xfd, 0x02, 0x02, 0x00, 0x64, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0x00, 0x02, 0x04, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x02, 0xff, 0x01, 0x01, 0x00, 0x0f, 0x01, 0x00, 0x03, 0xff, 0x01, 0x01, 0x00, 0x19, 0x01, 0x00, 0x04, 0xfe, 0x01, 0x01, 0x00, 0x23, 0x01, 0x00, 0x05, 0xfe, 0x01, 0x02, 0x00, 0x2d, 0x02, 0x00, 0x06, 0xfe, 0x02, 0x02, 0x00, 0x37, 0x02, 0x00, 0x07, 0xfd, 0x02, 0x02, 0x00, 0x40, 0x02, 0x00, 0x08, 0xfd, 0x02, 0x02, 0x00, 0x41, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xc4, 0x2f, 0x00, 0xff, 0xff, 0xff, 0x06, 0x30, 0x00, 0x48, 0x30, 0x00, 0x8a, 0x30, 0x00, 0xcc, 0x30, 0x00, 0x0e, 0x31, 0x00, 0x50, 0x31, 0x00, 0x92, 0x31, 0x00, 0xd4, 0x31, 0x00, 0x16, 0x32, 0x00, 0xff, 0xff, 0xff, 0x58, 0x32, 0x00, 0xff, 0xff, 0xff, 0xba, 0x32, 0x00, 0x1c, 0x33, 0x00, 0x7e, 0x33, 0x00, 0xe0, 0x33, 0x00, 0x42, 0x34, 0x00, 0xa4, 0x34, 0x00, 0x06, 0x35, 0x00, 0x68, 0x35, 0x00, 0xca, 0x35, 0x00, 0xff, 0xff, 0xff, 0x2c, 0x36, 0x00, 0x3e, 0x36, 0x00, 0x80, 0x36, 0x00, 0xc2, 0x36, 0x00, 0x04, 0x37, 0x00, 0x46, 0x37, 0x00, 0x88, 0x37, 0x00, 0xca, 0x37, 0x00, 0x24, 0x38, 0x00, 0x9d, 0x38, 0x00, 0xf9, 0x38, 0x00, 0x7d, 0x39, 0x00, 0xd7, 0x39, 0x00, 0x50, 0x3a, 0x00, 0xac, 0x3a, 0x00, 0x30, 0x3b, 0x00, 0x72, 0x3b, 0x00, 0xb4, 0x3b, 0x00, 0xf6, 0x3b, 0x00, 0x38, 0x3c, 0x00, 0x7a, 0x3c, 0x00, 0xbc, 0x3c, 0x00, 0xfe, 0x3c, 0x00, 0x40, 0x3d, 0x00, 0x3a, 0x3e, 0x00, 0x34, 0x3f, 0x00, 0x2e, 0x40, 0x00, 0x28, 0x41, 0x00, 0x22, 0x42, 0x00, 0x98, 0x43, 0x00, 0xea, 0x43, 0x00, 0x3c, 0x44, 0x00, 0x8e, 0x44, 0x00, 0xe0, 0x44, 0x00, 0x32, 0x45, 0x00, 0x84, 0x45, 0x00, 0x7e, 0x46, 0x00, 0x78, 0x47, 0x00, 0xba, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0x76, 0x48, 0x00, 0xf0, 0x48, 0x00, 0x6a, 0x49, 0x00, 0xe4, 0x49, 0x00, 0x5e, 0x4a, 0x00, 0xd8, 0x4a, 0x00, 0x52, 0x4b, 0x00, 0xcc, 0x4b, 0x00, 0x46, 0x4c, 0x00, 0xc0, 0x4c, 0x00, 0x3a, 0x4d, 0x00, 0xb4, 0x4d, 0x00, 0x2e, 0x4e, 0x00, 0xa8, 0x4e, 0x00, 0x22, 0x4f, 0x00, 0x9c, 0x4f, 0x00, 0x16, 0x50, 0x00, 0x90, 0x50, 0x00, 0x0a, 0x51, 0x00, 0x84, 0x51, 0x00, 0xfe, 0x51, 0x00, 0x78, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0x6c, 0x53, 0x00, 0xe6, 0x53, 0x00, 0x60, 0x54, 0x00, 0xda, 0x54, 0x00, 0x54, 0x55, 0x00, 0xce, 0x55, 0x00, 0x48, 0x56, 0x00, 0xc2, 0x56, 0x00, 0x3c, 0x57, 0x00, 0xb6, 0x57, 0x00, 0x30, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0x24, 0x59, 0x00, 0x9e, 0x59, 0x00, 0x18, 0x5a, 0x00, 0x92, 0x5a, 0x00, 0x0c, 0x5b, 0x00, 0x86, 0x5b, 0x00, 0x00, 0x5c, 0x00, 0x7a, 0x5c, 0x00, 0xf4, 0x5c, 0x00, 0x6e, 0x5d, 0x00, 0xe8, 0x5d, 0x00, 0x62, 0x5e, 0x00, 0xdc, 0x5e, 0x00, 0x56, 0x5f, 0x00, 0xd0, 0x5f, 0x00, 0x4a, 0x60, 0x00, 0xc4, 0x60, 0x00, 0x3e, 0x61, 0x00, 0xb8, 0x61, 0x00, 0x32, 0x62, 0x00, 0xac, 0x62, 0x00, 0x26, 0x63, 0x00, 0xa0, 0x63, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x94, 0x64, 0x00, 0x0e, 0x65, 0x00, 0x88, 0x65, 0x00, 0x02, 0x66, 0x00, 0x7c, 0x66, 0x00, 0xf6, 0x66, 0x00, 0x70, 0x67, 0x00, 0xea, 0x67, 0x00, 0x64, 0x68, 0x00, 0xde, 0x68, 0x00, 0x58, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0x4c, 0x6a, 0x00, 0xc6, 0x6a, 0x00, 0x40, 0x6b, 0x00, 0xba, 0x6b, 0x00, 0x34, 0x6c, 0x00, 0xae, 0x6c, 0x00, 0x28, 0x6d, 0x00, 0xa2, 0x6d, 0x00, 0x1c, 0x6e, 0x00, 0x96, 0x6e, 0x00, 0x10, 0x6f, 0x00, 0x8a, 0x6f, 0x00, 0x04, 0x70, 0x00, 0x7e, 0x70, 0x00, 0xf8, 0x70, 0x00, 0x72, 0x71, 0x00, 0xec, 0x71, 0x00, 0x66, 0x72, 0x00, 0xe0, 0x72, 0x00, 0x5a, 0x73, 0x00, 0xd4, 0x73, 0x00, 0x4e, 0x74, 0x00, 0xc8, 0x74, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0xbc, 0x75, 0x00, 0x36, 0x76, 0x00, 0xb0, 0x76, 0x00, 0x2a, 0x77, 0x00, 0xa4, 0x77, 0x00, 0x1e, 0x78, 0x00, 0x98, 0x78, 0x00, 0x12, 0x79, 0x00, 0x8c, 0x79, 0x00, 0x06, 0x7a, 0x00, 0x80, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0x74, 0x7b, 0x00, 0xe2, 0x7b, 0x00, 0x50, 0x7c, 0x00, 0xbe, 0x7c, 0x00, 0x2c, 0x7d, 0x00, 0x9a, 0x7d, 0x00, 0x08, 0x7e, 0x00, 0x76, 0x7e, 0x00, 0xe4, 0x7e, 0x00, 0x52, 0x7f, 0x00, 0xc0, 0x7f, 0x00, 0x2e, 0x80, 0x00, 0x9c, 0x80, 0x00, 0x0a, 0x81, 0x00, 0x78, 0x81, 0x00, 0xe6, 0x81, 0x00, 0x54, 0x82, 0x00, 0xc2, 0x82, 0x00, 0x30, 0x83, 0x00, 0x9e, 0x83, 0x00, 0x0c, 0x84, 0x00, 0x7a, 0x84, 0x00, 0xe8, 0x84, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0xc4, 0x85, 0x00, 0x32, 0x86, 0x00, 0xa0, 0x86, 0x00, 0x0e, 0x87, 0x00, 0x7c, 0x87, 0x00, 0xea, 0x87, 0x00, 0x58, 0x88, 0x00, 0xc6, 0x88, 0x00, 0x34, 0x89, 0x00, 0xa2, 0x89, 0x00, 0x10, 0x8a, 0x00, 0x7e, 0x8a, 0x00, 0xec, 0x8a, 0x00, 0x2e, 0x8b, 0x00, 0xac, 0x8b, 0x00, 0x2a, 0x8c, 0x00, 0xa8, 0x8c, 0x00, 0x26, 0x8d, 0x00, 0xa4, 0x8d, 0x00, 0x22, 0x8e, 0x00, 0xa0, 0x8e, 0x00, 0x1e, 0x8f, 0x00, 0x60, 0x8f, 0x00, 0xa2, 0x8f, 0x00, 0xe4, 0x8f, 0x00, 0x13, 0x90, 0x00, 0x42, 0x90, 0x00, 0x65, 0x90, 0x00, 0x88, 0x90, 0x00, 0xab, 0x90, 0x00, 0xce, 0x90, 0x00, 0xf1, 0x90, 0x00, 0x57, 0x91, 0x00, 0xbd, 0x91, 0x00, 0x23, 0x92, 0x00, 0x89, 0x92, 0x00, 0xef, 0x92, 0x00, 0x55, 0x93, 0x00, 0xbb, 0x93, 0x00, 0x21, 0x94, 0x00, 0x87, 0x94, 0x00, 0xed, 0x94, 0x00, 0x53, 0x95, 0x00, 0xb9, 0x95, 0x00, 0x1f, 0x96, 0x00, 0x85, 0x96, 0x00, 0xeb, 0x96, 0x00, 0x51, 0x97, 0x00, 0xb7, 0x97, 0x00, 0x1d, 0x98, 0x00, 0x83, 0x98, 0x00, 0xe9, 0x98, 0x00, 0x4f, 0x99, 0x00, 0xb5, 0x99, 0x00, 0x1b, 0x9a, 0x00, 0x81, 0x9a, 0x00, 0xe7, 0x9a, 0x00, 0x4d, 0x9b, 0x00, 0xb3, 0x9b, 0x00, 0x19, 0x9c, 0x00, 0x7f, 0x9c, 0x00, 0xe5, 0x9c, 0x00, 0x4b, 0x9d, 0x00, 0xb1, 0x9d, 0x00, 0x17, 0x9e, 0x00, 0x7d, 0x9e, 0x00, 0xe3, 0x9e, 0x00, 0x49, 0x9f, 0x00, 0xaf, 0x9f, 0x00, 0x15, 0xa0, 0x00, 0x7b, 0xa0, 0x00, 0xe1, 0xa0, 0x00, 0x47, 0xa1, 0x00, 0xad, 0xa1, 0x00, 0x13, 0xa2, 0x00, 0x79, 0xa2, 0x00, 0xdf, 0xa2, 0x00, 0x45, 0xa3, 0x00, 0xab, 0xa3, 0x00, 0x11, 0xa4, 0x00, 0x77, 0xa4, 0x00, 0xdd, 0xa4, 0x00, 0x43, 0xa5, 0x00, 0xa9, 0xa5, 0x00, 0x0f, 0xa6, 0x00, 0x75, 0xa6, 0x00, 0xdb, 0xa6, 0x00, 0x41, 0xa7, 0x00, 0xa7, 0xa7, 0x00, 0x0d, 0xa8, 0x00, 0x73, 0xa8, 0x00, 0xd9, 0xa8, 0x00, 0x3f, 0xa9, 0x00, 0xa5, 0xa9, 0x00, 0x0b, 0xaa, 0x00, 0x71, 0xaa, 0x00, 0xd7, 0xaa, 0x00, 0x3d, 0xab, 0x00, 0xa3, 0xab, 0x00, 0x09, 0xac, 0x00, 0x6f, 0xac, 0x00, 0xd5, 0xac, 0x00, 0x3b, 0xad, 0x00, 0xa1, 0xad, 0x00, 0x07, 0xae, 0x00, 0x6d, 0xae, 0x00, 0xd3, 0xae, 0x00, 0x39, 0xaf, 0x00, 0x9f, 0xaf, 0x00, 0x05, 0xb0, 0x00, 0x6b, 0xb0, 0x00, 0xd1, 0xb0, 0x00, 0x37, 0xb1, 0x00, 0x9d, 0xb1, 0x00, 0x03, 0xb2, 0x00, 0x69, 0xb2, 0x00, 0xcf, 0xb2, 0x00, 0x35, 0xb3, 0x00, 0x9b, 0xb3, 0x00, 0x01, 0xb4, 0x00, 0x67, 0xb4, 0x00, 0xcd, 0xb4, 0x00, 0x33, 0xb5, 0x00, 0x99, 0xb5, 0x00, 0xff, 0xb5, 0x00, 0x65, 0xb6, 0x00, 0xcb, 0xb6, 0x00, 0x31, 0xb7, 0x00, 0x97, 0xb7, 0x00, 0xfd, 0xb7, 0x00, 0x63, 0xb8, 0x00, 0xc9, 0xb8, 0x00, 0x2f, 0xb9, 0x00, 0x95, 0xb9, 0x00, 0xfb, 0xb9, 0x00, 0x61, 0xba, 0x00, 0xc7, 0xba, 0x00, 0x2d, 0xbb, 0x00, 0x93, 0xbb, 0x00, 0xf9, 0xbb, 0x00, 0x5f, 0xbc, 0x00, 0xc5, 0xbc, 0x00, 0x2b, 0xbd, 0x00, 0x91, 0xbd, 0x00, 0xf7, 0xbd, 0x00, 0x5d, 0xbe, 0x00, 0xc3, 0xbe, 0x00, 0x29, 0xbf, 0x00, 0x8f, 0xbf, 0x00, 0xf5, 0xbf, 0x00, 0x5b, 0xc0, 0x00, 0xc1, 0xc0, 0x00, 0x27, 0xc1, 0x00, 0x8d, 0xc1, 0x00, 0xf3, 0xc1, 0x00, 0x59, 0xc2, 0x00, 0xbf, 0xc2, 0x00, 0x25, 0xc3, 0x00, 0x8b, 0xc3, 0x00, 0xf1, 0xc3, 0x00, 0x57, 0xc4, 0x00, 0xbd, 0xc4, 0x00, 0x23, 0xc5, 0x00, 0x89, 0xc5, 0x00, 0xef, 0xc5, 0x00, 0x55, 0xc6, 0x00, 0xbb, 0xc6, 0x00, 0x21, 0xc7, 0x00, 0x87, 0xc7, 0x00, 0xed, 0xc7, 0x00, 0x53, 0xc8, 0x00, 0xb9, 0xc8, 0x00, 0x1f, 0xc9, 0x00, 0x85, 0xc9, 0x00, 0xeb, 0xc9, 0x00, 0x51, 0xca, 0x00, 0xb7, 0xca, 0x00, 0x1d, 0xcb, 0x00, 0x83, 0xcb, 0x00, 0xe9, 0xcb, 0x00, 0x4f, 0xcc, 0x00, 0xb5, 0xcc, 0x00, 0x1b, 0xcd, 0x00, 0x81, 0xcd, 0x00, 0xe7, 0xcd, 0x00, 0x4d, 0xce, 0x00, 0xb3, 0xce, 0x00, 0x19, 0xcf, 0x00, 0x7f, 0xcf, 0x00, 0xe5, 0xcf, 0x00, 0x4b, 0xd0, 0x00, 0xb1, 0xd0, 0x00, 0x17, 0xd1, 0x00, 0x7d, 0xd1, 0x00, 0xe3, 0xd1, 0x00, 0x49, 0xd2, 0x00, 0xaf, 0xd2, 0x00, 0x15, 0xd3, 0x00, 0x7b, 0xd3, 0x00, 0xe1, 0xd3, 0x00, 0x47, 0xd4, 0x00, 0xad, 0xd4, 0x00, 0x13, 0xd5, 0x00, 0x79, 0xd5, 0x00, 0xdf, 0xd5, 0x00, 0x45, 0xd6, 0x00, 0xab, 0xd6, 0x00, 0x11, 0xd7, 0x00, 0x77, 0xd7, 0x00, 0xdd, 0xd7, 0x00, 0x43, 0xd8, 0x00, 0xa9, 0xd8, 0x00, 0x0f, 0xd9, 0x00, 0x75, 0xd9, 0x00, 0xdb, 0xd9, 0x00, 0x41, 0xda, 0x00, 0xa7, 0xda, 0x00, 0x0d, 0xdb, 0x00, 0x73, 0xdb, 0x00, 0xd9, 0xdb, 0x00, 0x3f, 0xdc, 0x00, 0xa5, 0xdc, 0x00, 0x0b, 0xdd, 0x00, 0x71, 0xdd, 0x00, 0xd7, 0xdd, 0x00, 0x3d, 0xde, 0x00, 0xa3, 0xde, 0x00, 0x09, 0xdf, 0x00, 0x6f, 0xdf, 0x00, 0xd5, 0xdf, 0x00, 0x3b, 0xe0, 0x00, 0xa1, 0xe0, 0x00, 0x07, 0xe1, 0x00, 0x6d, 0xe1, 0x00, 0xd3, 0xe1, 0x00, 0x39, 0xe2, 0x00, 0x9f, 0xe2, 0x00, 0x05, 0xe3, 0x00, 0x6b, 0xe3, 0x00, 0xd1, 0xe3, 0x00, 0x37, 0xe4, 0x00, 0x9d, 0xe4, 0x00, 0x03, 0xe5, 0x00, 0x69, 0xe5, 0x00, 0xcf, 0xe5, 0x00, 0x35, 0xe6, 0x00, 0x9b, 0xe6, 0x00, 0x01, 0xe7, 0x00, 0x67, 0xe7, 0x00, 0xcd, 0xe7, 0x00, 0x33, 0xe8, 0x00, 0x99, 0xe8, 0x00, 0xff, 0xe8, 0x00, 0x65, 0xe9, 0x00, 0xcb, 0xe9, 0x00, 0x31, 0xea, 0x00, 0x97, 0xea, 0x00, 0xfd, 0xea, 0x00, 0x63, 0xeb, 0x00, 0xc9, 0xeb, 0x00, 0x2f, 0xec, 0x00, 0x95, 0xec, 0x00, 0xfb, 0xec, 0x00, 0x61, 0xed, 0x00, 0xc7, 0xed, 0x00, 0x2d, 0xee, 0x00, 0x93, 0xee, 0x00, 0xf9, 0xee, 0x00, 0x5f, 0xef, 0x00, 0xc5, 0xef, 0x00, 0x2b, 0xf0, 0x00, 0x91, 0xf0, 0x00, 0xf7, 0xf0, 0x00, 0x5d, 0xf1, 0x00, 0xc3, 0xf1, 0x00, 0x29, 0xf2, 0x00, 0x8f, 0xf2, 0x00, 0xf5, 0xf2, 0x00, 0x5b, 0xf3, 0x00, 0xc1, 0xf3, 0x00, 0x27, 0xf4, 0x00, 0x8d, 0xf4, 0x00, 0xf3, 0xf4, 0x00, 0x59, 0xf5, 0x00, 0xbf, 0xf5, 0x00, 0x25, 0xf6, 0x00, 0x8b, 0xf6, 0x00, 0xf1, 0xf6, 0x00, 0x57, 0xf7, 0x00, 0xbd, 0xf7, 0x00, 0x23, 0xf8, 0x00, 0x89, 0xf8, 0x00, 0xef, 0xf8, 0x00, 0x55, 0xf9, 0x00, 0xbb, 0xf9, 0x00, 0x21, 0xfa, 0x00, 0x87, 0xfa, 0x00, 0xed, 0xfa, 0x00, 0x53, 0xfb, 0x00, 0xb9, 0xfb, 0x00, 0x1f, 0xfc, 0x00, 0x85, 0xfc, 0x00, 0xeb, 0xfc, 0x00, 0x51, 0xfd, 0x00, 0xb7, 0xfd, 0x00, 0x1d, 0xfe, 0x00, 0x83, 0xfe, 0x00, 0xe9, 0xfe, 0x00, 0x4f, 0xff, 0x00, 0xb5, 0xff, 0x00, 0x1b, 0x00, 0x01, 0x81, 0x00, 0x01, 0xe7, 0x00, 0x01, 0x4d, 0x01, 0x01, 0xb3, 0x01, 0x01, 0x19, 0x02, 0x01, 0x7f, 0x02, 0x01, 0xe5, 0x02, 0x01, 0x4b, 0x03, 0x01, 0xb1, 0x03, 0x01, 0x17, 0x04, 0x01, 0x7d, 0x04, 0x01, 0xe3, 0x04, 0x01, 0x49, 0x05, 0x01, 0xaf, 0x05, 0x01, 0x15, 0x06, 0x01, 0x7b, 0x06, 0x01, 0xe1, 0x06, 0x01, 0x47, 0x07, 0x01, 0xad, 0x07, 0x01, 0x13, 0x08, 0x01, 0x79, 0x08, 0x01, 0xdf, 0x08, 0x01, 0x45, 0x09, 0x01, 0xab, 0x09, 0x01, 0x11, 0x0a, 0x01, 0x77, 0x0a, 0x01, 0xdd, 0x0a, 0x01, 0x43, 0x0b, 0x01, 0xa9, 0x0b, 0x01, 0x0f, 0x0c, 0x01, 0x75, 0x0c, 0x01, 0xdb, 0x0c, 0x01, 0x41, 0x0d, 0x01, 0xa7, 0x0d, 0x01, 0x0d, 0x0e, 0x01, 0x73, 0x0e, 0x01, 0xd9, 0x0e, 0x01, 0x3f, 0x0f, 0x01, 0xa5, 0x0f, 0x01, 0x0b, 0x10, 0x01, 0x71, 0x10, 0x01, 0xd7, 0x10, 0x01, 0x3d, 0x11, 0x01, 0xa3, 0x11, 0x01, 0x09, 0x12, 0x01, 0x6f, 0x12, 0x01, 0xd5, 0x12, 0x01, 0x3b, 0x13, 0x01, 0xa1, 0x13, 0x01, 0x07, 0x14, 0x01, 0x6d, 0x14, 0x01, 0xd3, 0x14, 0x01, 0x39, 0x15, 0x01, 0x9f, 0x15, 0x01, 0x05, 0x16, 0x01, 0x6b, 0x16, 0x01, 0xd1, 0x16, 0x01, 0x37, 0x17, 0x01, 0x9d, 0x17, 0x01, 0x03, 0x18, 0x01, 0x69, 0x18, 0x01, 0xcf, 0x18, 0x01, 0x35, 0x19, 0x01, 0x9b, 0x19, 0x01, 0x01, 0x1a, 0x01, 0x67, 0x1a, 0x01, 0xcd, 0x1a, 0x01, 0x33, 0x1b, 0x01, 0x99, 0x1b, 0x01, 0xff, 0x1b, 0x01, 0x65, 0x1c, 0x01, 0xcb, 0x1c, 0x01, 0x31, 0x1d, 0x01, 0x97, 0x1d, 0x01, 0xfd, 0x1d, 0x01, 0x63, 0x1e, 0x01, 0xc9, 0x1e, 0x01, 0x2f, 0x1f, 0x01, 0x95, 0x1f, 0x01, 0xfb, 0x1f, 0x01, 0x61, 0x20, 0x01, 0xc7, 0x20, 0x01, 0x2d, 0x21, 0x01, 0x93, 0x21, 0x01, 0xf9, 0x21, 0x01, 0x5f, 0x22, 0x01, 0xc5, 0x22, 0x01, 0x2b, 0x23, 0x01, 0x91, 0x23, 0x01, 0xf7, 0x23, 0x01, 0x5d, 0x24, 0x01, 0xc3, 0x24, 0x01, 0x29, 0x25, 0x01, 0x8f, 0x25, 0x01, 0xf5, 0x25, 0x01, 0x5b, 0x26, 0x01, 0xc1, 0x26, 0x01, 0x27, 0x27, 0x01, 0x8d, 0x27, 0x01, 0xf3, 0x27, 0x01, 0x59, 0x28, 0x01, 0xbf, 0x28, 0x01, 0x25, 0x29, 0x01, 0x8b, 0x29, 0x01, 0xf1, 0x29, 0x01, 0x57, 0x2a, 0x01, 0xbd, 0x2a, 0x01, 0x23, 0x2b, 0x01, 0x89, 0x2b, 0x01, 0xef, 0x2b, 0x01, 0x55, 0x2c, 0x01, 0xbb, 0x2c, 0x01, 0x21, 0x2d, 0x01, 0x87, 0x2d, 0x01, 0xed, 0x2d, 0x01, 0x53, 0x2e, 0x01, 0xb9, 0x2e, 0x01, 0x1f, 0x2f, 0x01, 0x85, 0x2f, 0x01, 0xeb, 0x2f, 0x01, 0x51, 0x30, 0x01, 0xb7, 0x30, 0x01, 0x1d, 0x31, 0x01, 0x83, 0x31, 0x01, 0xe9, 0x31, 0x01, 0x4f, 0x32, 0x01, 0xb5, 0x32, 0x01, 0x1b, 0x33, 0x01, 0x81, 0x33, 0x01, 0xe7, 0x33, 0x01, 0x4d, 0x34, 0x01, 0xb3, 0x34, 0x01, 0x19, 0x35, 0x01, 0x7f, 0x35, 0x01, 0xe5, 0x35, 0x01, 0x4b, 0x36, 0x01, 0xb1, 0x36, 0x01, 0x17, 0x37, 0x01, 0x7d, 0x37, 0x01, 0xe3, 0x37, 0x01, 0x49, 0x38, 0x01, 0xaf, 0x38, 0x01, 0x15, 0x39, 0x01, 0x7b, 0x39, 0x01, 0xe1, 0x39, 0x01, 0x47, 0x3a, 0x01, 0xad, 0x3a, 0x01, 0x13, 0x3b, 0x01, 0x79, 0x3b, 0x01, 0xdf, 0x3b, 0x01, 0x45, 0x3c, 0x01, 0xab, 0x3c, 0x01, 0x11, 0x3d, 0x01, 0x77, 0x3d, 0x01, 0xdd, 0x3d, 0x01, 0x43, 0x3e, 0x01, 0xa9, 0x3e, 0x01, 0x0f, 0x3f, 0x01, 0x75, 0x3f, 0x01, 0xdb, 0x3f, 0x01, 0x41, 0x40, 0x01, 0xa7, 0x40, 0x01, 0x0d, 0x41, 0x01, 0x73, 0x41, 0x01, 0xd9, 0x41, 0x01, 0x3f, 0x42, 0x01, 0xa5, 0x42, 0x01, 0x0b, 0x43, 0x01, 0x71, 0x43, 0x01, 0xd7, 0x43, 0x01, 0x3d, 0x44, 0x01, 0xa3, 0x44, 0x01, 0x09, 0x45, 0x01, 0x6f, 0x45, 0x01, 0xd5, 0x45, 0x01, 0x3b, 0x46, 0x01, 0xa1, 0x46, 0x01, 0x07, 0x47, 0x01, 0x6d, 0x47, 0x01, 0xd3, 0x47, 0x01, 0x39, 0x48, 0x01, 0x9f, 0x48, 0x01, 0x05, 0x49, 0x01, 0x6b, 0x49, 0x01, 0xd1, 0x49, 0x01, 0x37, 0x4a, 0x01, 0x9d, 0x4a, 0x01, 0x03, 0x4b, 0x01, 0x69, 0x4b, 0x01, 0xcf, 0x4b, 0x01, 0x35, 0x4c, 0x01, 0x9b, 0x4c, 0x01, 0x01, 0x4d, 0x01, 0x67, 0x4d, 0x01, 0xcd, 0x4d, 0x01, 0x33, 0x4e, 0x01, 0x99, 0x4e, 0x01, 0xff, 0x4e, 0x01, 0x65, 0x4f, 0x01, 0xcb, 0x4f, 0x01, 0x31, 0x50, 0x01, 0x97, 0x50, 0x01, 0xfd, 0x50, 0x01, 0x63, 0x51, 0x01, 0xc9, 0x51, 0x01, 0x2f, 0x52, 0x01, 0x95, 0x52, 0x01, 0xfb, 0x52, 0x01, 0x61, 0x53, 0x01, 0xc7, 0x53, 0x01, 0x2d, 0x54, 0x01, 0x93, 0x54, 0x01, 0xf9, 0x54, 0x01, 0x5f, 0x55, 0x01, 0xc5, 0x55, 0x01, 0x2b, 0x56, 0x01, 0x91, 0x56, 0x01, 0xf7, 0x56, 0x01, 0x5d, 0x57, 0x01, 0xc3, 0x57, 0x01, 0x29, 0x58, 0x01, 0x8f, 0x58, 0x01, 0xf5, 0x58, 0x01, 0x5b, 0x59, 0x01, 0xc1, 0x59, 0x01, 0x27, 0x5a, 0x01, 0x8d, 0x5a, 0x01, 0xf3, 0x5a, 0x01, 0x59, 0x5b, 0x01, 0xbf, 0x5b, 0x01, 0x25, 0x5c, 0x01, 0x8b, 0x5c, 0x01, 0xf1, 0x5c, 0x01, 0x57, 0x5d, 0x01, 0xbd, 0x5d, 0x01, 0x23, 0x5e, 0x01, 0x89, 0x5e, 0x01, 0xef, 0x5e, 0x01, 0x55, 0x5f, 0x01, 0xbb, 0x5f, 0x01, 0x21, 0x60, 0x01, 0x87, 0x60, 0x01, 0xed, 0x60, 0x01, 0x53, 0x61, 0x01, 0xb9, 0x61, 0x01, 0x1f, 0x62, 0x01, 0x85, 0x62, 0x01, 0xeb, 0x62, 0x01, 0x51, 0x63, 0x01, 0xb7, 0x63, 0x01, 0x1d, 0x64, 0x01, 0x83, 0x64, 0x01, 0xe9, 0x64, 0x01, 0x4f, 0x65, 0x01, 0xb5, 0x65, 0x01, 0x1b, 0x66, 0x01, 0x81, 0x66, 0x01, 0xe7, 0x66, 0x01, 0x4d, 0x67, 0x01, 0xb3, 0x67, 0x01, 0x19, 0x68, 0x01, 0x7f, 0x68, 0x01, 0xe5, 0x68, 0x01, 0x4b, 0x69, 0x01, 0xb1, 0x69, 0x01, 0x17, 0x6a, 0x01, 0x7d, 0x6a, 0x01, 0xe3, 0x6a, 0x01, 0x49, 0x6b, 0x01, 0xaf, 0x6b, 0x01, 0x15, 0x6c, 0x01, 0x7b, 0x6c, 0x01, 0xe1, 0x6c, 0x01, 0x47, 0x6d, 0x01, 0xad, 0x6d, 0x01, 0x13, 0x6e, 0x01, 0x79, 0x6e, 0x01, 0xdf, 0x6e, 0x01, 0x45, 0x6f, 0x01, 0xab, 0x6f, 0x01, 0x11, 0x70, 0x01, 0x77, 0x70, 0x01, 0xdd, 0x70, 0x01, 0x43, 0x71, 0x01, 0xa9, 0x71, 0x01, 0x0f, 0x72, 0x01, 0x75, 0x72, 0x01, 0xdb, 0x72, 0x01, 0x41, 0x73, 0x01, 0xa7, 0x73, 0x01, 0x0d, 0x74, 0x01, 0x73, 0x74, 0x01, 0xd9, 0x74, 0x01, 0x3f, 0x75, 0x01, 0xa5, 0x75, 0x01, 0x0b, 0x76, 0x01, 0x71, 0x76, 0x01, 0xd7, 0x76, 0x01, 0x3d, 0x77, 0x01, 0xa3, 0x77, 0x01, 0x09, 0x78, 0x01, 0x6f, 0x78, 0x01, 0xd5, 0x78, 0x01, 0x3b, 0x79, 0x01, 0xa1, 0x79, 0x01, 0x07, 0x7a, 0x01, 0x6d, 0x7a, 0x01, 0xd3, 0x7a, 0x01, 0x39, 0x7b, 0x01, 0x9f, 0x7b, 0x01, 0x05, 0x7c, 0x01, 0x6b, 0x7c, 0x01, 0xd1, 0x7c, 0x01, 0x37, 0x7d, 0x01, 0x9d, 0x7d, 0x01, 0x03, 0x7e, 0x01, 0x69, 0x7e, 0x01, 0xcf, 0x7e, 0x01, 0x35, 0x7f, 0x01, 0x9b, 0x7f, 0x01, 0x01, 0x80, 0x01, 0x67, 0x80, 0x01, 0xcd, 0x80, 0x01, 0x33, 0x81, 0x01, 0x99, 0x81, 0x01, 0xff, 0x81, 0x01, 0x65, 0x82, 0x01, 0xcb, 0x82, 0x01, 0x31, 0x83, 0x01, 0x97, 0x83, 0x01, 0xfd, 0x83, 0x01, 0x63, 0x84, 0x01, 0xc9, 0x84, 0x01, 0x2f, 0x85, 0x01, 0x95, 0x85, 0x01, 0xfb, 0x85, 0x01, 0x61, 0x86, 0x01, 0xc7, 0x86, 0x01, 0x2d, 0x87, 0x01, 0x93, 0x87, 0x01, 0xf9, 0x87, 0x01, 0x5f, 0x88, 0x01, 0xc5, 0x88, 0x01, 0x2b, 0x89, 0x01, 0x91, 0x89, 0x01, 0xf7, 0x89, 0x01, 0x5d, 0x8a, 0x01, 0xc3, 0x8a, 0x01, 0x29, 0x8b, 0x01, 0x8f, 0x8b, 0x01, 0xf5, 0x8b, 0x01, 0x5b, 0x8c, 0x01, 0xc1, 0x8c, 0x01, 0x27, 0x8d, 0x01, 0x8d, 0x8d, 0x01, 0xf3, 0x8d, 0x01, 0x59, 0x8e, 0x01, 0xbf, 0x8e, 0x01, 0x25, 0x8f, 0x01, 0x8b, 0x8f, 0x01, 0xf1, 0x8f, 0x01, 0x57, 0x90, 0x01, 0xbd, 0x90, 0x01, 0x23, 0x91, 0x01, 0x89, 0x91, 0x01, 0xef, 0x91, 0x01, 0x55, 0x92, 0x01, 0xbb, 0x92, 0x01, 0x21, 0x93, 0x01, 0x87, 0x93, 0x01, 0xed, 0x93, 0x01, 0x53, 0x94, 0x01, 0xb9, 0x94, 0x01, 0x1f, 0x95, 0x01, 0x85, 0x95, 0x01, 0xeb, 0x95, 0x01, 0x51, 0x96, 0x01, 0xb7, 0x96, 0x01, 0x1d, 0x97, 0x01, 0x83, 0x97, 0x01, 0xe9, 0x97, 0x01, 0x4f, 0x98, 0x01, 0xb5, 0x98, 0x01, 0x1b, 0x99, 0x01, 0x81, 0x99, 0x01, 0xe7, 0x99, 0x01, 0x4d, 0x9a, 0x01, 0xb3, 0x9a, 0x01, 0x19, 0x9b, 0x01, 0x7f, 0x9b, 0x01, 0xe5, 0x9b, 0x01, 0x4b, 0x9c, 0x01, 0xb1, 0x9c, 0x01, 0x17, 0x9d, 0x01, 0x7d, 0x9d, 0x01, 0xe3, 0x9d, 0x01, 0x49, 0x9e, 0x01, 0xaf, 0x9e, 0x01, 0x15, 0x9f, 0x01, 0x7b, 0x9f, 0x01, 0xe1, 0x9f, 0x01, 0x47, 0xa0, 0x01, 0xad, 0xa0, 0x01, 0x13, 0xa1, 0x01, 0x79, 0xa1, 0x01, 0xdf, 0xa1, 0x01, 0x45, 0xa2, 0x01, 0xab, 0xa2, 0x01, 0x11, 0xa3, 0x01, 0x77, 0xa3, 0x01, 0xdd, 0xa3, 0x01, 0x43, 0xa4, 0x01, 0xa9, 0xa4, 0x01, 0x0f, 0xa5, 0x01, 0x75, 0xa5, 0x01, 0xdb, 0xa5, 0x01, 0x41, 0xa6, 0x01, 0xa7, 0xa6, 0x01, 0x0d, 0xa7, 0x01, 0x73, 0xa7, 0x01, 0xd9, 0xa7, 0x01, 0x3f, 0xa8, 0x01, 0xa5, 0xa8, 0x01, 0x0b, 0xa9, 0x01, 0x71, 0xa9, 0x01, 0xd7, 0xa9, 0x01, 0x3d, 0xaa, 0x01, 0xa3, 0xaa, 0x01, 0x09, 0xab, 0x01, 0x6f, 0xab, 0x01, 0xd5, 0xab, 0x01, 0x3b, 0xac, 0x01, 0xa1, 0xac, 0x01, 0x07, 0xad, 0x01, 0x6d, 0xad, 0x01, 0xd3, 0xad, 0x01, 0x39, 0xae, 0x01, 0x9f, 0xae, 0x01, 0x05, 0xaf, 0x01, 0x6b, 0xaf, 0x01, 0xd1, 0xaf, 0x01, 0x37, 0xb0, 0x01, 0x9d, 0xb0, 0x01, 0x03, 0xb1, 0x01, 0x69, 0xb1, 0x01, 0xcf, 0xb1, 0x01, 0x35, 0xb2, 0x01, 0x9b, 0xb2, 0x01, 0x01, 0xb3, 0x01, 0x67, 0xb3, 0x01, 0xcd, 0xb3, 0x01, 0x33, 0xb4, 0x01, 0x99, 0xb4, 0x01, 0xff, 0xb4, 0x01, 0x65, 0xb5, 0x01, 0xcb, 0xb5, 0x01, 0x31, 0xb6, 0x01, 0x97, 0xb6, 0x01, 0xfd, 0xb6, 0x01, 0x63, 0xb7, 0x01, 0xc9, 0xb7, 0x01, 0x2f, 0xb8, 0x01, 0x95, 0xb8, 0x01, 0xfb, 0xb8, 0x01, 0x61, 0xb9, 0x01, 0xc7, 0xb9, 0x01, 0x2d, 0xba, 0x01, 0x93, 0xba, 0x01, 0xf9, 0xba, 0x01, 0x5f, 0xbb, 0x01, 0xc5, 0xbb, 0x01, 0x2b, 0xbc, 0x01, 0x91, 0xbc, 0x01, 0xf7, 0xbc, 0x01, 0x5d, 0xbd, 0x01, 0xc3, 0xbd, 0x01, 0x29, 0xbe, 0x01, 0x8f, 0xbe, 0x01, 0xf5, 0xbe, 0x01, 0x5b, 0xbf, 0x01, 0xc1, 0xbf, 0x01, 0x27, 0xc0, 0x01, 0x8d, 0xc0, 0x01, 0xf3, 0xc0, 0x01, 0x59, 0xc1, 0x01, 0xbf, 0xc1, 0x01, 0x25, 0xc2, 0x01, 0x8b, 0xc2, 0x01, 0xf1, 0xc2, 0x01, 0x57, 0xc3, 0x01, 0xbd, 0xc3, 0x01, 0x23, 0xc4, 0x01, 0x89, 0xc4, 0x01, 0xef, 0xc4, 0x01, 0x55, 0xc5, 0x01, 0xbb, 0xc5, 0x01, 0x21, 0xc6, 0x01, 0x87, 0xc6, 0x01, 0xed, 0xc6, 0x01, 0x53, 0xc7, 0x01, 0xb9, 0xc7, 0x01, 0x1f, 0xc8, 0x01, 0x85, 0xc8, 0x01, 0xeb, 0xc8, 0x01, 0x51, 0xc9, 0x01, 0xb7, 0xc9, 0x01, 0x1d, 0xca, 0x01, 0x83, 0xca, 0x01, 0xe9, 0xca, 0x01, 0x4f, 0xcb, 0x01, 0xb5, 0xcb, 0x01, 0x1b, 0xcc, 0x01, 0x1f, 0x04, 0x07, 0x04, 0x04, 0x02, 0x03, 0x10, 0x00, 0x00, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x0a, 0x06, 0x00, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x10, 0x00, 0x00, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x1f, 0x00, 0x08, 0x00, 0x06, 0x00, 0x03, 0x0a, 0x06, 0x00, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x1e, 0x0b, 0x06, 0x04, 0x04, 0x03, 0x04, 0x0c, 0x04, 0x00, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x13, 0xf8, 0x01, 0x87, 0xf9, 0x01, 0x87, 0xf9, 0x01, 0x35, 0xee, 0x01, 0xa9, 0xf2, 0x01, 0xa9, 0xf2, 0x01, 0x35, 0xee, 0x01, 0xa9, 0xf2, 0x01, 0xa9, 0xf2, 0x01, 0x1e, 0x04, 0x0b, 0x04, 0x08, 0x02, 0x06, 0x04, 0x06, 0x06, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x18, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x0a, 0x06, 0x00, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x08, 0x04, 0x04, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0xb7, 0x11, 0x02, 0x21, 0x17, 0x02, 0x09, 0x1d, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x03, 0x05, 0x08, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0x7c, 0x00, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x73, 0x30, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xf0, 0x3c, 0x03, 0x55, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0xff, 0x00, 0x03, 0x55, 0x55, 0xff, 0x00, 0x3d, 0x55, 0x55, 0xff, 0x00, 0xcd, 0x55, 0x55, 0xcf, 0xff, 0x0d, 0x55, 0x55, 0x73, 0x30, 0x3d, 0x55, 0x55, 0x73, 0xf0, 0xf5, 0x55, 0x55, 0x73, 0xf0, 0x35, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x7f, 0x55, 0x57, 0xff, 0x55, 0xff, 0xd5, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x0f, 0x00, 0xf0, 0xd5, 0x57, 0x30, 0xc3, 0x0c, 0xd5, 0x57, 0x00, 0x3c, 0x00, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x57, 0x3f, 0xff, 0xfc, 0xd5, 0x57, 0xf0, 0xc3, 0x0f, 0xd5, 0x55, 0x73, 0xff, 0xcd, 0x55, 0x55, 0xc3, 0xff, 0xc3, 0x55, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x03, 0x00, 0xc0, 0xd5, 0x57, 0x0c, 0x00, 0x30, 0xd5, 0x57, 0x00, 0x3c, 0x00, 0xd5, 0x55, 0xc0, 0xff, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x3f, 0x0f, 0xc3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x00, 0xf0, 0x0d, 0x55, 0x55, 0xff, 0x0f, 0xf5, 0x55, 0x57, 0x33, 0xfc, 0xcd, 0x55, 0x57, 0xf3, 0xfc, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x30, 0x00, 0x0c, 0xd5, 0x57, 0x0c, 0x00, 0x30, 0xd5, 0x57, 0x00, 0xff, 0x00, 0xd5, 0x5f, 0x03, 0xff, 0xc0, 0xf5, 0x5c, 0xc3, 0xff, 0xc3, 0x35, 0x5f, 0x3f, 0xff, 0xfc, 0xf5, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0xc3, 0xff, 0xc3, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x7f, 0x55, 0x57, 0xff, 0x55, 0xff, 0xd5, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x03, 0x00, 0xc0, 0xd5, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x30, 0x3c, 0x0c, 0xd5, 0x55, 0xcc, 0x3c, 0x33, 0xd5, 0x55, 0xcc, 0x3c, 0x33, 0x55, 0x55, 0xc3, 0xc3, 0xc3, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xd7, 0xf5, 0x55, 0x55, 0x5f, 0x55, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x5c, 0x3f, 0xff, 0xc3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x55, 0xff, 0xff, 0xf5, 0x55, 0x55, 0xc0, 0x00, 0x35, 0x55, 0x57, 0x30, 0x00, 0xcd, 0x55, 0x57, 0xf0, 0x00, 0xfd, 0x55, 0x55, 0x70, 0x00, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0x55, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0x70, 0x00, 0x3d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x70, 0x0c, 0xd5, 0x55, 0x57, 0xc0, 0xfc, 0xd5, 0x55, 0x55, 0xf0, 0x3f, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0x57, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0x70, 0x00, 0x3d, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x30, 0xcd, 0x55, 0x55, 0xfc, 0x3f, 0xf5, 0x55, 0x55, 0x70, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x70, 0x3f, 0xf5, 0x55, 0x55, 0xc0, 0x0f, 0xf5, 0x55, 0x7f, 0xc0, 0x0f, 0xf5, 0x5f, 0xc0, 0xc0, 0x0f, 0x55, 0x5f, 0xc0, 0xc0, 0xcf, 0xd5, 0x55, 0xc0, 0xc0, 0xcf, 0xd5, 0x57, 0xc0, 0x3c, 0xcf, 0xf5, 0x5f, 0xfc, 0x03, 0x0f, 0xf5, 0x5f, 0xff, 0xff, 0xf7, 0xd5, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x3c, 0x03, 0xc3, 0x55, 0x5c, 0xc3, 0x0c, 0x33, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0xc3, 0x0c, 0x33, 0x55, 0x57, 0x30, 0xf0, 0xcc, 0xd5, 0x55, 0xff, 0xff, 0xf0, 0xd5, 0x55, 0x73, 0x0c, 0x03, 0x55, 0x55, 0xcc, 0xfc, 0x0d, 0x55, 0x55, 0xfc, 0xff, 0x0d, 0x55, 0x55, 0x5c, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x55, 0xf5, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x00, 0xc3, 0x00, 0xd5, 0x57, 0x3f, 0xc3, 0xfc, 0xd5, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x5c, 0xcc, 0x35, 0x55, 0x55, 0x73, 0xff, 0xcd, 0x55, 0x55, 0x70, 0xfc, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xc0, 0x30, 0x03, 0x55, 0x55, 0xc0, 0xc0, 0x03, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xfc, 0x00, 0x03, 0x55, 0x55, 0xff, 0x03, 0xc3, 0x55, 0x55, 0x7f, 0x03, 0x3d, 0x55, 0x55, 0x5f, 0xff, 0x35, 0x55, 0x55, 0x5c, 0xcc, 0x0d, 0x55, 0x55, 0x57, 0x3c, 0x03, 0x55, 0x55, 0x57, 0x3c, 0x3f, 0x55, 0x55, 0x57, 0xff, 0xf5, 0x55, 0x55, 0x55, 0x7d, 0xfd, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0x7f, 0x55, 0x55, 0x55, 0xff, 0xff, 0xd5, 0x55, 0x55, 0xff, 0xff, 0xd5, 0x55, 0x55, 0xff, 0x00, 0x35, 0x55, 0x57, 0xf0, 0x00, 0x3d, 0x55, 0x57, 0xc0, 0x03, 0x03, 0x55, 0x57, 0x00, 0x3c, 0x03, 0x55, 0x57, 0x00, 0x00, 0x0f, 0x55, 0x57, 0x00, 0x00, 0x35, 0x55, 0x57, 0xc0, 0x03, 0xd5, 0x55, 0x55, 0x7f, 0xff, 0x55, 0x55, 0x55, 0xc0, 0xcf, 0x55, 0x55, 0x57, 0x30, 0xfd, 0x55, 0x55, 0x57, 0xf0, 0xfd, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x7d, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xf5, 0x55, 0x55, 0x5f, 0xfd, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0x00, 0x0d, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x0f, 0xc3, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0x70, 0x00, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x5c, 0x3c, 0xd5, 0x55, 0x55, 0x5f, 0x0f, 0xd5, 0x55, 0x55, 0x5c, 0xff, 0xd5, 0x55, 0x55, 0x70, 0x0f, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3c, 0x0f, 0x55, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0xc0, 0x00, 0xff, 0x55, 0x55, 0xc0, 0xf0, 0xff, 0x55, 0x55, 0x70, 0xcc, 0xfd, 0x55, 0x55, 0x5f, 0xcf, 0xd5, 0x55, 0x55, 0x5c, 0xcc, 0xd5, 0x55, 0x55, 0x5c, 0x3f, 0xd5, 0x55, 0x55, 0x5c, 0x0f, 0xd5, 0x55, 0x55, 0x70, 0x0f, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x55, 0xfd, 0x55, 0x55, 0x7f, 0xdf, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0xc3, 0x55, 0x55, 0xcc, 0x00, 0x03, 0x55, 0x55, 0x73, 0x00, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x73, 0x30, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0x7f, 0x55, 0x55, 0xff, 0xd5, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0xd5, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0x70, 0x00, 0x03, 0x55, 0x55, 0xc3, 0x00, 0x30, 0xd5, 0x55, 0xcc, 0xc0, 0xcc, 0xd5, 0x55, 0xc3, 0x00, 0x30, 0xd5, 0x57, 0xc0, 0x3f, 0x00, 0xd5, 0x57, 0x30, 0xff, 0xc3, 0x55, 0x55, 0xcf, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xc3, 0xfc, 0x03, 0x55, 0x55, 0xc3, 0xfc, 0x3c, 0xd5, 0x55, 0x7f, 0xfc, 0x37, 0xd5, 0x55, 0x5f, 0x7f, 0xd5, 0x55, 0x55, 0x55, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x3c, 0x03, 0xc3, 0x55, 0x5c, 0xf3, 0x0f, 0x33, 0x55, 0x5c, 0xff, 0x0f, 0xf3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x0f, 0xf0, 0x0d, 0x55, 0x55, 0xfc, 0x3f, 0xf5, 0x55, 0x55, 0xc3, 0xcc, 0x3d, 0x55, 0x55, 0x70, 0xfc, 0xf3, 0x55, 0x55, 0x70, 0xfc, 0xdf, 0x55, 0x55, 0x7f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xcd, 0x55, 0x5f, 0xff, 0xff, 0xfd, 0x55, 0x7f, 0xff, 0xff, 0xd5, 0x55, 0x70, 0x00, 0x03, 0xd5, 0x55, 0xff, 0xff, 0xfc, 0xd5, 0x55, 0xc0, 0x00, 0x0f, 0xd5, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0x7c, 0x00, 0x0c, 0xd5, 0x55, 0x5f, 0xff, 0xf0, 0x35, 0x55, 0x7f, 0x3f, 0xfc, 0x0d, 0x55, 0x7f, 0x3f, 0xfc, 0x0d, 0x55, 0x70, 0x00, 0x3c, 0x0d, 0x55, 0x7f, 0xff, 0xf0, 0x0d, 0x55, 0x5f, 0xff, 0xdf, 0xf5, 0x55, 0x7f, 0xdf, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0x55, 0x55, 0x55, 0x57, 0x35, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0xff, 0xff, 0x55, 0x55, 0x5f, 0xff, 0xff, 0x55, 0x55, 0x70, 0x00, 0x0f, 0x55, 0x55, 0x7f, 0xff, 0xf3, 0xfd, 0x55, 0xc0, 0x00, 0x0c, 0xc3, 0x55, 0xc0, 0x00, 0x03, 0xc3, 0x55, 0xc0, 0x00, 0x03, 0x03, 0x55, 0xf0, 0x03, 0x03, 0xc3, 0x55, 0xc3, 0xc0, 0x0f, 0xc3, 0x55, 0xc3, 0xc0, 0x3f, 0x0d, 0x55, 0x7f, 0xff, 0xfc, 0x35, 0x5d, 0xff, 0x3f, 0xf3, 0xd5, 0x5f, 0x00, 0x00, 0xfd, 0x55, 0x5f, 0xff, 0xff, 0x3d, 0x55, 0x55, 0xff, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xff, 0x55, 0x55, 0x7f, 0xff, 0xff, 0xd5, 0x55, 0xf0, 0x00, 0x03, 0xf5, 0x55, 0xcf, 0xff, 0xfc, 0xf5, 0x55, 0xf0, 0x00, 0x03, 0xff, 0x57, 0x0f, 0xc0, 0xfc, 0xf3, 0x57, 0x33, 0xc3, 0x3c, 0xdf, 0x57, 0x33, 0xc3, 0x3c, 0xd5, 0x57, 0x0f, 0xc0, 0xfc, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x35, 0x55, 0xff, 0xff, 0xfc, 0x0d, 0x57, 0xff, 0xcf, 0xf3, 0x0d, 0x5c, 0xff, 0xcf, 0xff, 0x0d, 0x57, 0x70, 0x00, 0x0c, 0x0d, 0x55, 0x7f, 0xff, 0xf7, 0xf5, 0x55, 0x57, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xf7, 0xfd, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xff, 0xf5, 0x55, 0x70, 0x00, 0xff, 0xff, 0x55, 0x7f, 0xfc, 0x03, 0xf3, 0x55, 0xf0, 0xff, 0xf0, 0xdf, 0x55, 0xf0, 0xf3, 0x0f, 0xd5, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xff, 0xf0, 0x33, 0x55, 0x57, 0x3f, 0xc0, 0xff, 0xd5, 0x57, 0xcf, 0xff, 0xfc, 0x35, 0x55, 0xff, 0x3f, 0xfc, 0x0d, 0x55, 0x7f, 0x3f, 0xf0, 0x0d, 0x55, 0x7f, 0x3f, 0xf0, 0x0d, 0x55, 0x70, 0x00, 0xf0, 0x0d, 0x55, 0x5f, 0xff, 0xdf, 0xf5, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x55, 0xf7, 0xd5, 0x55, 0x30, 0x1f, 0x01, 0x55, 0x40, 0x00, 0x00, 0x00, 0x15, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x11, 0x41, 0x50, 0x00, 0x00, 0x15, 0x55, 0x55, 0x54, 0x04, 0x10, 0x01, 0x55, 0x41, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa1, 0x14, 0x15, 0x54, 0x01, 0x11, 0x45, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa5, 0x54, 0x15, 0x54, 0x01, 0x55, 0x45, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa1, 0x14, 0x44, 0x11, 0x55, 0x55, 0x55, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x15, 0x40, 0x01, 0x55, 0x11, 0x56, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x95, 0x40, 0x01, 0x55, 0x55, 0x56, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x95, 0x55, 0x55, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x55, 0x50, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x01, 0x50, 0x55, 0x50, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x15, 0x55, 0x55, 0x54, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x02, 0x55, 0x55, 0x55, 0x00, 0x04, 0x00, 0x80, 0x28, 0x00, 0x00, 0xa0, 0x02, 0x01, 0x15, 0x55, 0x10, 0x04, 0x55, 0x80, 0x28, 0x00, 0x00, 0xa0, 0x02, 0x01, 0x15, 0x55, 0x01, 0x55, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x02, 0x55, 0x55, 0x55, 0x01, 0x01, 0x00, 0x80, 0xaa, 0xaa, 0xaa, 0xa8, 0x02, 0x00, 0x04, 0x01, 0x01, 0x55, 0x00, 0x82, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x04, 0x01, 0x00, 0x41, 0x00, 0x82, 0xaa, 0xaa, 0xaa, 0xaa, 0x02, 0x00, 0x04, 0x01, 0x55, 0x5a, 0xa5, 0x80, 0x95, 0x95, 0x80, 0x00, 0x02, 0x55, 0x54, 0x01, 0x00, 0x25, 0x58, 0x80, 0x95, 0x95, 0x85, 0x54, 0x0a, 0xaa, 0xa8, 0x01, 0x00, 0x26, 0x98, 0x80, 0x95, 0x95, 0x85, 0x54, 0x08, 0x00, 0x09, 0x55, 0x00, 0x25, 0x58, 0x80, 0x95, 0x95, 0xaa, 0xaa, 0x08, 0x88, 0x88, 0x00, 0x00, 0x20, 0x08, 0x95, 0x95, 0x95, 0x80, 0x02, 0x58, 0x88, 0x88, 0x00, 0xaa, 0xa0, 0x0a, 0x95, 0x95, 0x95, 0x80, 0x02, 0x58, 0x00, 0x0a, 0xaa, 0x04, 0x20, 0x08, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa9, 0x55, 0x58, 0x00, 0x00, 0x0a, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xaa, 0xa9, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0x42, 0x82, 0x20, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa6, 0x86, 0x26, 0x62, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x45, 0x86, 0x24, 0xa4, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xa4, 0xa1, 0x61, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x61, 0x40, 0xa2, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0xaa, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa9, 0x55, 0x69, 0x55, 0x6a, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x9a, 0xa9, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x59, 0x59, 0x6a, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x98, 0x49, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x95, 0x55, 0xaa, 0x95, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa5, 0x56, 0xaa, 0x40, 0x68, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa8, 0x0a, 0xa5, 0x55, 0x58, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa9, 0x5a, 0xa5, 0x55, 0x58, 0x00, 0x95, 0x5a, 0x69, 0xa5, 0x56, 0x02, 0xa5, 0x96, 0xa9, 0x69, 0x68, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x96, 0x5a, 0x69, 0xa5, 0x96, 0x54, 0x54, 0x54, 0x54, 0x54, 0x55, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x54, 0x54, 0x54, 0x54, 0x54, 0x55, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x30, 0x1f, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x15, 0x00, 0x00, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x55, 0x00, 0x01, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x40, 0x51, 0x55, 0x55, 0x15, 0x54, 0x00, 0x00, 0x15, 0x54, 0x55, 0x55, 0x45, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x40, 0x00, 0x44, 0x11, 0x10, 0x11, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x44, 0x04, 0x44, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x40, 0x00, 0x44, 0x15, 0x05, 0x41, 0x50, 0x05, 0x55, 0x55, 0x50, 0x05, 0x41, 0x50, 0x54, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x50, 0x40, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x50, 0x40, 0x01, 0x00, 0x01, 0x00, 0x17, 0xfc, 0x3f, 0xfc, 0x00, 0x43, 0xff, 0xc0, 0x01, 0x00, 0x01, 0x00, 0x1f, 0xf4, 0xff, 0xd4, 0x00, 0x4f, 0xfc, 0x40, 0x01, 0x55, 0x55, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x40, 0x01, 0x11, 0x11, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x40, 0x01, 0x00, 0x01, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xc0, 0x01, 0x05, 0x41, 0x00, 0xf0, 0xfc, 0x03, 0xff, 0xff, 0x00, 0x00, 0xc0, 0x01, 0x05, 0x41, 0x00, 0xf0, 0xf3, 0x0c, 0x71, 0xc7, 0x33, 0x30, 0xc0, 0xaa, 0xaa, 0xaa, 0xaa, 0xf0, 0xf3, 0x0d, 0x75, 0xd7, 0x33, 0x30, 0xea, 0x55, 0x55, 0x55, 0x55, 0xf0, 0xfc, 0x0d, 0x34, 0xd3, 0x33, 0x30, 0xd5, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x0d, 0x34, 0xc3, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x03, 0xff, 0xff, 0xaa, 0xaa, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 0xc0, 0x00, 0xfc, 0x0f, 0xc0, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x3a, 0xbf, 0xfa, 0xab, 0xff, 0xbf, 0xfb, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0xff, 0xff, 0xcf, 0xfc, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf0, 0x03, 0xff, 0x3f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xc0, 0x00, 0xfc, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x55, 0x51, 0x55, 0x55, 0x15, 0x54, 0x00, 0x00, 0x15, 0x10, 0x00, 0x00, 0x40, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x40, 0x11, 0x10, 0x11, 0x10, 0x04, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x40, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x15, 0x55, 0x55, 0x40, 0x15, 0x05, 0x41, 0x50, 0x05, 0x55, 0x55, 0x50, 0x00, 0x00, 0x00, 0x00, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf5, 0xff, 0xf0, 0x00, 0x0f, 0xff, 0x00, 0x50, 0x50, 0x50, 0x50, 0x3f, 0xc3, 0xff, 0x00, 0x14, 0x3f, 0xf4, 0x14, 0x55, 0x50, 0x55, 0x50, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x54, 0x55, 0x50, 0x55, 0x50, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x54, 0x55, 0x55, 0x55, 0x53, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x54, 0x40, 0x10, 0x40, 0x13, 0xc3, 0xf0, 0x0f, 0xff, 0xfc, 0x00, 0x03, 0x04, 0x50, 0x50, 0x50, 0x53, 0xc3, 0xcc, 0x31, 0xc7, 0x1c, 0xcc, 0xc3, 0x14, 0x40, 0x10, 0x40, 0x13, 0xc3, 0xcc, 0x35, 0xd7, 0x5c, 0xcc, 0xc3, 0x04, 0xaa, 0xaa, 0xaa, 0xab, 0xc3, 0xf0, 0x34, 0xd3, 0x4c, 0xcc, 0xc3, 0xaa, 0x55, 0x55, 0x55, 0x57, 0x00, 0x00, 0x34, 0xd3, 0x0c, 0x00, 0x03, 0x55, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x0f, 0xff, 0xfe, 0xaa, 0xab, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x3f, 0x00, 0x03, 0xf0, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xea, 0xff, 0xea, 0xaf, 0xfe, 0xff, 0xec, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf3, 0xff, 0xff, 0x3f, 0xf3, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x0f, 0xfc, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x03, 0xf0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xfd, 0x7d, 0x7f, 0x5d, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x5d, 0xd5, 0xd7, 0x75, 0xdd, 0xd5, 0x55, 0x55, 0x55, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x30, 0xcc, 0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0xc0, 0xff, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xc0, 0xc3, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0x3f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xfc, 0x3f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x03, 0xc0, 0x30, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0xf3, 0xff, 0xff, 0xcf, 0x00, 0x00, 0x0f, 0xf0, 0x70, 0x0f, 0x55, 0x55, 0xc3, 0x0c, 0x30, 0xc3, 0x55, 0x55, 0xf0, 0x0d, 0xc3, 0x30, 0xd5, 0xff, 0x7c, 0xcf, 0xf3, 0x3d, 0xff, 0x57, 0x0c, 0xc3, 0xc0, 0x3f, 0x5f, 0x03, 0x57, 0xcf, 0xf3, 0xd5, 0xc0, 0xf5, 0xfc, 0x03, 0xc0, 0x30, 0xdc, 0x0d, 0x5f, 0xff, 0xff, 0xf5, 0x70, 0x37, 0x0c, 0x03, 0x7f, 0xff, 0x5f, 0xf5, 0x5f, 0x55, 0x55, 0xf5, 0x5f, 0xf5, 0xff, 0xfd, 0x30, 0x1f, 0xa4, 0x00, 0xa4, 0x01, 0x90, 0x00, 0x64, 0x06, 0x40, 0x1a, 0x00, 0x16, 0xa9, 0x40, 0x09, 0x00, 0x40, 0x00, 0x10, 0x01, 0x00, 0x60, 0x01, 0x6a, 0x2a, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xaa, 0x00, 0xa5, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x01, 0x6a, 0x80, 0x00, 0x01, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x30, 0xc0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x00, 0x05, 0x94, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x15, 0x56, 0xa5, 0x55, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x15, 0x40, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x29, 0x50, 0x15, 0x68, 0x00, 0x40, 0x07, 0xf0, 0x0f, 0xc0, 0x10, 0x00, 0x0a, 0xa5, 0x6a, 0x80, 0x01, 0x00, 0x1f, 0xfc, 0x3f, 0xf0, 0x04, 0x00, 0x00, 0xaa, 0xa8, 0x00, 0x15, 0x00, 0x1f, 0xff, 0xff, 0xf0, 0x05, 0x40, 0x00, 0x0a, 0xa0, 0x00, 0x04, 0x00, 0x5c, 0x00, 0x00, 0x30, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xf0, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xc0, 0x33, 0x00, 0x00, 0xcc, 0x03, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x30, 0x03, 0xc0, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x0c, 0x30, 0x03, 0xc0, 0x0c, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x3c, 0x03, 0xc0, 0x3c, 0xff, 0xc0, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0xc3, 0xff, 0xff, 0xc3, 0x00, 0x00, 0x0f, 0xf0, 0x30, 0x0c, 0x00, 0x00, 0xcc, 0x30, 0x0c, 0x33, 0x00, 0x00, 0x30, 0x0c, 0xc3, 0x0f, 0x00, 0x00, 0x3f, 0x3f, 0xfc, 0xfc, 0x00, 0x00, 0xf0, 0xc3, 0xc0, 0x30, 0xc0, 0x00, 0x03, 0x3f, 0xfc, 0xc0, 0x00, 0x03, 0x0c, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0xfc, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x3f, 0xfc, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x30, 0x30, 0xc0, 0x00, 0x00, 0x3c, 0x3c, 0x00, 0x00, 0x03, 0x0c, 0x0c, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x0c, 0x30, 0x00, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xfd, 0x7d, 0x7f, 0x5d, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x5d, 0xd5, 0xd7, 0x75, 0xdd, 0xd5, 0x55, 0x55, 0x55, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x30, 0xcc, 0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0xc0, 0xff, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xc0, 0xc3, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x70, 0x0f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xf0, 0x0d, 0xc3, 0x30, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x0c, 0xc3, 0xc0, 0x3f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfc, 0x03, 0xc0, 0x30, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x0c, 0x03, 0x7f, 0xff, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xfd, 0x30, 0x1f, 0xa4, 0x00, 0xa4, 0x01, 0x90, 0x00, 0x64, 0x06, 0x40, 0x1a, 0x00, 0x16, 0xa9, 0x40, 0x09, 0x00, 0x40, 0x00, 0x10, 0x01, 0x00, 0x60, 0x01, 0x6a, 0x2a, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xaa, 0x00, 0xa5, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x01, 0x6a, 0x80, 0x00, 0x01, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x30, 0xc0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x00, 0x05, 0x94, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x15, 0x56, 0xa5, 0x55, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x15, 0x40, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x29, 0x50, 0x15, 0x68, 0x00, 0x40, 0x04, 0x00, 0x04, 0x00, 0x10, 0x00, 0x0a, 0xa5, 0x6a, 0x80, 0x01, 0x00, 0x14, 0x00, 0x05, 0x00, 0x04, 0x00, 0x00, 0xaa, 0xa8, 0x00, 0x15, 0x00, 0x15, 0x00, 0x15, 0x00, 0x05, 0x40, 0x00, 0x0a, 0xa0, 0x00, 0x04, 0x00, 0x54, 0x00, 0x05, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x30, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0c, 0xc3, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xc3, 0xc0, 0x30, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x30, 0x30, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x0c, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xfc, 0x00, 0xc3, 0x0f, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xc3, 0x00, 0xc3, 0x30, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xcc, 0xc3, 0x00, 0xff, 0x30, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xfc, 0x00, 0xc3, 0x30, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xc0, 0x00, 0xc3, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x3f, 0x0f, 0xcf, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0xcc, 0x0c, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0xcf, 0xcf, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0x0f, 0xcf, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x30, 0xcc, 0x33, 0x0c, 0xfc, 0xfc, 0x00, 0x00, 0xc0, 0x00, 0x00, 0xc3, 0x30, 0xcf, 0x33, 0xcc, 0xc0, 0xc3, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc3, 0x30, 0xcc, 0xf3, 0x3c, 0xfc, 0xc3, 0x00, 0x00, 0xfc, 0x00, 0x00, 0xfc, 0x30, 0xcc, 0x33, 0x0c, 0xc0, 0xfc, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc3, 0x0f, 0x0c, 0x33, 0x0c, 0xfc, 0xc3, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x1f, 0x05, 0x55, 0x55, 0x55, 0x55, 0x55, 0x54, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x05, 0x54, 0x55, 0x45, 0x51, 0x10, 0x00, 0x04, 0x04, 0x55, 0x44, 0x51, 0x11, 0x55, 0x44, 0x04, 0x44, 0x44, 0x51, 0x11, 0x00, 0x44, 0x04, 0x44, 0x44, 0x51, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x00, 0x00, 0x00, 0x05, 0x41, 0x10, 0x00, 0x00, 0x00, 0x00, 0x04, 0x41, 0x10, 0x00, 0x00, 0x10, 0x55, 0x05, 0x41, 0x10, 0x54, 0x00, 0x55, 0x45, 0x10, 0x11, 0x11, 0x01, 0x40, 0x55, 0x54, 0x10, 0x11, 0x11, 0x00, 0x10, 0x55, 0x54, 0x15, 0x51, 0x11, 0x41, 0x11, 0x51, 0x10, 0x04, 0x41, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x50, 0x50, 0x00, 0x00, 0x10, 0x01, 0x10, 0x55, 0x50, 0x55, 0x00, 0x55, 0x01, 0x10, 0x44, 0x51, 0x00, 0x51, 0x00, 0x41, 0x10, 0x40, 0x11, 0x04, 0x41, 0x11, 0x41, 0x10, 0x15, 0x41, 0x00, 0x41, 0x00, 0x41, 0x10, 0x10, 0x41, 0x00, 0x40, 0x41, 0x01, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x55, 0x55, 0x55, 0x55, 0x55, 0x41, 0x10, 0x40, 0x00, 0x00, 0x00, 0x00, 0x41, 0x10, 0x55, 0x55, 0x55, 0x55, 0x55, 0x41, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x15, 0x50, 0x00, 0x00, 0x00, 0x01, 0x55, 0x12, 0x0c, 0x57, 0xf5, 0x7d, 0x55, 0x50, 0x5f, 0xfd, 0xff, 0x55, 0x50, 0x5f, 0xff, 0xff, 0x55, 0x50, 0x5f, 0xff, 0xff, 0xd5, 0x50, 0x7c, 0x00, 0x00, 0xd5, 0x50, 0x70, 0x0f, 0xc3, 0xd5, 0x50, 0x70, 0x33, 0xc3, 0xd5, 0x50, 0x70, 0x33, 0xc3, 0xd5, 0x50, 0x70, 0x0f, 0xc3, 0xd5, 0x50, 0x5c, 0x00, 0x0f, 0x55, 0x50, 0x57, 0xff, 0xfd, 0x55, 0x50, 0x5c, 0x3c, 0x33, 0x55, 0x50, 0x12, 0x0c, 0x55, 0xfd, 0x5f, 0x55, 0x50, 0x57, 0xff, 0x7f, 0xd5, 0x50, 0x57, 0xff, 0xff, 0xd5, 0x50, 0x57, 0xff, 0xff, 0xf5, 0x50, 0x5f, 0x00, 0x00, 0x35, 0x50, 0x5c, 0x03, 0xc0, 0x35, 0x50, 0x5c, 0x0c, 0x30, 0xf5, 0x50, 0x5c, 0x00, 0x00, 0x35, 0x50, 0x5c, 0x0c, 0x0f, 0xf5, 0x50, 0x57, 0x33, 0x0f, 0xd5, 0x50, 0x55, 0xf3, 0xff, 0x35, 0x50, 0x55, 0xc3, 0xc3, 0xf5, 0x50, 0x12, 0x0c, 0x5f, 0xd5, 0x7f, 0xff, 0xf0, 0x7f, 0xf5, 0xff, 0x00, 0x30, 0x7f, 0xff, 0xff, 0x00, 0x30, 0x7f, 0xff, 0xff, 0x00, 0x30, 0x70, 0x00, 0x03, 0x00, 0x30, 0xc3, 0xf0, 0x3f, 0x00, 0x30, 0xcc, 0xf0, 0xcf, 0x00, 0x30, 0xcc, 0xf0, 0xcf, 0x00, 0x30, 0xc3, 0xf0, 0x3f, 0xff, 0xf0, 0x70, 0x0f, 0x00, 0xcd, 0x50, 0x5f, 0xff, 0xff, 0x35, 0x50, 0x70, 0x30, 0x3c, 0xd5, 0x50, 0x12, 0x0c, 0x55, 0xfd, 0x57, 0xd5, 0x50, 0x57, 0xff, 0xdf, 0xf5, 0x50, 0x57, 0xff, 0xff, 0xfd, 0x50, 0x55, 0xff, 0xff, 0xfd, 0x50, 0x57, 0xc0, 0x00, 0x0d, 0x50, 0x57, 0x00, 0x00, 0x0d, 0x50, 0x57, 0x00, 0x00, 0x0d, 0x50, 0x57, 0x0f, 0xf0, 0x0d, 0x50, 0x57, 0x00, 0x00, 0xcd, 0x50, 0x55, 0xc0, 0x03, 0x35, 0x50, 0x55, 0x7f, 0xff, 0xd5, 0x50, 0x55, 0xc3, 0xc3, 0xd5, 0x50, 0x12, 0x0c, 0x57, 0xf5, 0x5f, 0xd5, 0x50, 0x5f, 0xfd, 0x7f, 0xf5, 0x50, 0x5f, 0xff, 0xff, 0xf5, 0x50, 0x5f, 0xff, 0xff, 0xf5, 0x50, 0x5c, 0x00, 0x00, 0x35, 0x50, 0x70, 0x00, 0x00, 0x0d, 0x50, 0x70, 0x30, 0x0c, 0x0d, 0x50, 0x70, 0xc0, 0x03, 0x0d, 0x50, 0x70, 0x03, 0xc0, 0x0d, 0x50, 0x5c, 0x0f, 0xf0, 0x35, 0x50, 0x57, 0xff, 0xff, 0xd5, 0x50, 0x55, 0xcc, 0x33, 0x55, 0x50, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfa, 0xaa, 0xab, 0xc0, 0xff, 0xe5, 0x55, 0x5a, 0xc0, 0xff, 0xe5, 0x55, 0x5a, 0xc0, 0xff, 0x95, 0x55, 0x66, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0xaa, 0xaa, 0xab, 0xc0, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfe, 0xaa, 0xaa, 0xc0, 0xff, 0xfe, 0x55, 0x56, 0xc0, 0xff, 0xfe, 0x55, 0x56, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xea, 0xaa, 0xaa, 0xc0, 0xff, 0xea, 0xaa, 0xaa, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0xaa, 0xaa, 0xab, 0xc0, 0x08, 0x08, 0x7f, 0xf5, 0xff, 0xfd, 0xc3, 0x0d, 0xff, 0xfd, 0xff, 0xfd, 0xfc, 0xfd, 0x7f, 0xf5, 0x77, 0x75, 0x10, 0x03, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xc0, 0x03, 0x03, 0xff, 0xff, 0xff, 0xff, 0x10, 0x03, 0x55, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x03, 0x55, 0x55, 0xff, 0xff, 0x55, 0x08, 0x08, 0x55, 0x75, 0x55, 0x75, 0x55, 0x75, 0x5f, 0x75, 0x70, 0xf5, 0x70, 0xd5, 0x5f, 0x55, 0x55, 0x55, 0x08, 0x08, 0x55, 0x75, 0x55, 0x75, 0x55, 0x75, 0x5f, 0x75, 0x7f, 0xf5, 0x7f, 0xd5, 0x5f, 0x55, 0x55, 0x55, 0x08, 0x08, 0x55, 0xd5, 0x55, 0xf5, 0x55, 0xfd, 0x7d, 0xdd, 0xff, 0xd5, 0xff, 0x55, 0x7d, 0x55, 0x55, 0x55, 0x08, 0x08, 0x5f, 0xfd, 0x5d, 0x5d, 0x5d, 0x5d, 0x5d, 0x5d, 0xfd, 0xfd, 0xfd, 0xfd, 0xf5, 0xf5, 0x55, 0x55, 0x01, 0x01, 0x00, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x7f, 0xfd, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x5f, 0xfd, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x7f, 0xfd, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x5f, 0xfd, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x7f, 0xfd, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0x03, 0x5f, 0xfd, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x08, 0x08, 0x50, 0x05, 0x43, 0xc1, 0x00, 0x00, 0x30, 0xcc, 0x33, 0x0c, 0x00, 0x00, 0x43, 0xc1, 0x50, 0x05, 0x08, 0x08, 0xc0, 0x03, 0x33, 0xcc, 0x00, 0x30, 0x33, 0x0c, 0x30, 0xcc, 0x0c, 0x00, 0x33, 0xcc, 0xc0, 0x03, 0x08, 0x08, 0x57, 0xd5, 0x5c, 0x35, 0x5c, 0x35, 0xdc, 0x37, 0xd7, 0xd7, 0xdf, 0xf7, 0xfd, 0x7f, 0xf7, 0xdf, 0x04, 0x1f, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x02, 0x05, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0x06, 0x20, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0x20, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf7, 0xff, 0x5f, 0x5f, 0xd7, 0xff, 0x75, 0x5d, 0x55, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x57, 0xd5, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x55, 0x75, 0x75, 0x7f, 0xdf, 0xd5, 0x75, 0x75, 0x55, 0x75, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x55, 0x5f, 0xd5, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x08, 0x7f, 0x5f, 0x57, 0xd7, 0x57, 0xd5, 0x75, 0xdd, 0x77, 0x57, 0xdf, 0x75, 0xdd, 0x77, 0x57, 0xd7, 0x75, 0xdf, 0xf7, 0x55, 0x7d, 0x5f, 0x5d, 0x77, 0xf7, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x0c, 0x7f, 0x5f, 0x5d, 0x5d, 0xfd, 0xd5, 0x75, 0xdf, 0x7d, 0xd5, 0xdf, 0x75, 0xdf, 0xfd, 0xfd, 0xd7, 0x7f, 0xdd, 0xdd, 0xd5, 0x7f, 0x75, 0xdd, 0x5d, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7d, 0x75, 0x77, 0xf7, 0xf5, 0xd7, 0x75, 0x77, 0x57, 0x5d, 0xd7, 0x5d, 0xd7, 0xf7, 0x5d, 0xd7, 0x5d, 0xd7, 0x57, 0xf5, 0x7d, 0x57, 0x57, 0xf7, 0x5d, 0x55, 0x55, 0x55, 0x55, 0x55, 0x20, 0x0c, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xff, 0x55, 0xc3, 0x7d, 0x55, 0x55, 0x55, 0x70, 0x00, 0xd5, 0x70, 0xff, 0x55, 0x55, 0x55, 0xc0, 0x00, 0x35, 0x7c, 0x3f, 0xd5, 0x55, 0x57, 0x00, 0x03, 0x0d, 0x5f, 0xff, 0xff, 0xff, 0xfc, 0x03, 0x00, 0x0d, 0x70, 0x00, 0x03, 0xc0, 0x00, 0x00, 0x3f, 0xfd, 0x7f, 0xff, 0xfc, 0x30, 0x00, 0x00, 0xc0, 0x03, 0xc0, 0x00, 0x03, 0x30, 0x00, 0x03, 0x0f, 0xfc, 0xc0, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc0, 0x03, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x01, 0x01, 0x00, 0x10, 0x10, 0x55, 0x7d, 0x55, 0xf5, 0x55, 0xc3, 0x57, 0x0d, 0x55, 0xc0, 0xdc, 0x0d, 0x55, 0x70, 0xdc, 0x3d, 0x55, 0x5c, 0x30, 0x35, 0x55, 0x70, 0x00, 0xd5, 0x55, 0xc3, 0xfc, 0xd5, 0x55, 0xcf, 0xff, 0x35, 0x57, 0x0f, 0xff, 0x35, 0x57, 0x00, 0xfc, 0x35, 0x57, 0xc0 }; void EXTI0_IRQHandler() { //GPIO_SetBits(GPIOB, GPIO_Pin_14); //if (EXTI_GetITStatus(EXTI_Line0) != RESET) { if(started){ if(read){ read = 2; } read = 1; //GPIO_SetBits(GPIOB, GPIO_Pin_14); a = 0; acount = 0; // as[loops++] = a; //as[loops++] = acount; as[loops++] = hit; hit = 0; } EXTI_ClearITPendingBit(EXTI_Line0); //} //GPIO_ResetBits(GPIOB, GPIO_Pin_14); } void EXTI1_IRQHandler() { //hit++; //if (EXTI_GetITStatus(EXTI_Line1) != RESET) { if(read){ // a = a << 1; // GPIO_SetBits(GPIOB, GPIO_Pin_15); // a = a | (GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_8)); (GPIOD->IDR & GPIO_Pin_8) ? (a = ((a << 1)|1) ) : (a <<= 1); //GPIO_ResetBits(GPIOB, GPIO_Pin_15); acount++; // if(acount > 32){ // GPIO_SetBits(GPIOD, GPIO_Pin_15); // } if (acount ==32){ read = 0; //if((a & 0xff000000) != 0x03000000){ // GPIO_SetBits(GPIOD, GPIO_Pin_14); // } as[loops++] = a; a = 0xffffff & a; val = v[a++]; // as[loops++] = val; // as[loops++] = val; c = 0x80; if(val&c){ GPIO_SetBits(GPIOD, GPIO_Pin_4); }else{ GPIO_ResetBits(GPIOD, GPIO_Pin_4); } c = c >> 1; started = 1; } }else{ if(val&c){ GPIOD->BSRRL = GPIO_Pin_4; }else{ GPIOD->BSRRH = GPIO_Pin_4; } c = c >> 1; if(c==0){ c = 0x80; val = v[a++]; // as[loops++] = val; } //as[loops++] = 2; } EXTI_ClearITPendingBit(EXTI_Line1); //} } /** * @brief Main program. * @param None * @retval None */ uint32_t getAddress(); int main(void) { RCC_ClocksTypeDef RCC_Clocks; int l = 0; /* Initialize LEDs and User_Button on STM32F4-Discovery --------------------*/ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE); RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE); /* SysTick end of count event each 10ms */ // RCC_GetClocksFreq(&RCC_Clocks); // SysTick_Config(RCC_Clocks.HCLK_Frequency / 100); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_8 ; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_Init(GPIOD, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; GPIO_Init(GPIOD, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_13| GPIO_Pin_14| GPIO_Pin_15; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_Init(GPIOD, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14 | GPIO_Pin_15; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_Init(GPIOB, &GPIO_InitStructure); EXTILine0_Config(); GPIO_SetBits(GPIOD, GPIO_Pin_12); // GPIO_SetBits(GPIOD, GPIO_Pin_14); // GPIO_SetBits(GPIOD, GPIO_Pin_12); // GPIO_ResetBits(GPIOB, GPIO_Pin_14); //GPIO_SetBits(GPIOB, GPIO_Pin_14); while(1){ // GPIO_SetBits(GPIOB, GPIO_Pin_14); // GPIO_ResetBits(GPIOB, GPIO_Pin_14); // printf("here"); /* uint32_t a, j; uint8_t t, c, i; flag = 1; if(started) while(GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_0)){ l++; } a = getAddress(); // if(a < 0 || a > 200){ // GPIO_SetBits(GPIOD, GPIO_Pin_14); //} started = 1; while(flag){ t = v[a]; c = 0x80; for( i = 0; (i < 8); i++){ // if(a > 200){ // loops++; // } if(t&c){ GPIO_SetBits(GPIOD, GPIO_Pin_4); }else{ GPIO_ResetBits(GPIOD, GPIO_Pin_4); } // if(!flag) // break; c = c >> 1; // q = ; // while((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)== Bit_RESET) && (GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_9) == Bit_RESET)){} // while(GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11) && (GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_9) == Bit_RESET) ){} // l = 0; //while((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)== Bit_SET) && flag ){} // as[loops++] = q; // q = 0; while((!GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)) && flag ){ } // if((l++ % 100) == 99){ // if((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_9) != Bit_RESET)) // break; // } // as[loops++] = q; // q = 0; // l = 0; while(GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)){ //q++; } //as[loops++] = q; // if((l++ % 100) == 99){ // if((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_9) != Bit_RESET)) // break; // } // // for(j=0; j < 1000000; j++){ // } // } // if(flag) // loop++; } a++; } // as[loops++] = a; */ } } uint32_t getAddress(){ uint32_t a, i; a = 0; for(i = 0; i < 32; i++){ while(GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)== Bit_RESET){} //a++; a = a << 1; a = a + (GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_10)? 1:0); // if(i!=31) while(GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_11)){} } if((a & 0xff000000) != 0x03000000){ // GPIO_SetBits(GPIOD, GPIO_Pin_15); } // as[loops++] = a; return a & 0x00ffffff; } /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ ================================================ FILE: devtools/itemmake/README ================================================ Tamagotchi Item Maker! Makes a flash image for a Tamagotchi item from a script. See the sample script as an example. The first command in the script must be "SOUND MULTIPLIER". This determines how fast or slow notes (sound) plays in your item. I recommend trying it as set, and tweaking the value if audio plays at the wrong speed. Low values are fast and high values are slow. The second command must be "IMAGE TABLE". This is a list of images used by the item. The first image must be the image with the text name of the item (which is displayed below it in the shop), and the second image must be the picture of the item. After that, anything goes. Images must be 16-colour bitmaps. After these two commands, "IMAGE" and "NOTE" commands are allowed. IMAGE commands display an image. The first parameter is the image name (do not include path or extension), and the second parameter is the amount of time the image is to be displayed for. The NOTE command plays a note. The first parameter is the image to display while playing the note, the second parameter is the note (letter name on a scale, no sharps or flats allowed). The final parameter is the length of the note. I recommend using 1 for the shortest note you need and setting the other values relative to this, and then tweaking the sound multiplier to adjust the length of the note. To make the flash image, call: itemmake.py scriptfile outputfile Questions? Comments? Contributions? Contact: natashenka@kwartzlab.ca / @natashenka ================================================ FILE: devtools/itemmake/itemmake.py ================================================ import sys import Image def tofourbit(a): #print a if ((a > -1) and (a < 1)): return 3; if ((a > 0) and (a < 8)): return 2; if ((a > 7) and (a < 10 )): return 1; if (a > 9): return 0; def conv(a): t = 0; t = t | (tofourbit(ord(a) & 0x0f) << 2) t = t | (tofourbit((ord(a) & 0xf0) >> 4)) return t def getnote(n): a = ["C", "D", "E", "F", "G", "A", "B", "HC", "HD", "HE", "HF", "HG"] q = a.index(str(n)) return q + 0x54 def imconv(path): s = "" tmp = 0 rol = 0 im = Image.open(path) i = 0 width = im.size[0] height = im.size[1] while ( i < (width * height) ): tmp = 0; for j in range(0, 4): tmp = tmp | tofourbit(im.getpixel(((i)%width, (i)/width))) i = i + 1 if j != 3: tmp = tmp * 4 #print tmp s = s + chr(tmp) #f = open("pic.txt", 'ab') r = "" r = r + chr(width) r = r + chr(height) r = r + s return r f = open(sys.argv[1], 'r') script = f.readlines() f.close() f = open("template.txt", 'rb') t = f.read() t = bytearray(t) f.close() sm = 0 if( script.pop(0).strip("\n\r") != "SOUND MULTIPLIER:"): print "error" script.pop(0) sm = int(script.pop(0).strip("\n\r")) print sm script.pop(0) if( script.pop(0).strip("\n\r") != "IMAGE TABLE:"): print "error" script.pop(0) i = script.pop(0).strip("\n\r") imagetable = [] while(i != ""): imagetable.append(i) i = script.pop(0).strip("\n\r") imdata = "" imptr = 0x50000 imptrptr = 0x4f1 t[0x2cc] = imptr & 0xff t[0x2cd] = (imptr & 0xff00) >> 8 t[0x2ce] = (imptr & 0xff0000) >> 16 d = imconv(imagetable[0]) timptr = imptr + len(d) t[0x2a8] = timptr & 0xff t[0x2a9] = (timptr & 0xff00) >> 8 t[0x2aa] = (timptr & 0xff0000) >> 16 for item in imagetable: d = imconv(item) imdata = imdata + d t[imptrptr] = imptr & 0xff t[imptrptr + 1] = (imptr & 0xff00) >> 8 t[imptrptr + 2] = (imptr & 0xff0000) >> 16 imptrptr = imptrptr + 3 imptr = imptr + len(d) for j in range(0, len(imdata)): t[0x50000 + 0x10 + j] = imdata[j] ftable = [] for item in imagetable: index = item.find('.') s = item[:index] s = s[s.rfind('\\')+1:] ftable.append(s) print ftable cbuf = "" on = True while on: command = script.pop(0).strip("\n\r") if(command == "IMAGE:"): script.pop(0).strip("\n\r") im, time = script.pop(0).strip("\n\r").split(' ') cbuf = cbuf + chr(ftable.index(im) + 0xb1) cbuf = cbuf + "\x80\x00\x00\x00" + chr(int(time, 16)) script.pop(0).strip("\n\r") if(command == "NOTE:"): script.pop(0).strip("\n\r") #print script.pop(0).strip("\n\r") im, note, time = script.pop(0).strip("\n\r").split(' ') b = "\xfe\xff" + chr(getnote(note)) + "\x00\x00\x00" cbuf = cbuf + chr(ftable.index(im) + 0xb1) + "\x80\x00\x00\x00\x01" b = b + "\xb0\x80\x00\x00\x00\x03" for j in range(0, sm * int(time, 16)): cbuf = cbuf + b script.pop(0).strip("\n\r") if(command == "END"): cbuf = cbuf + "\xff\xff" on = False for j in range(0, len(cbuf)): t[0x250c4 + j] = cbuf[j] f = open(sys.argv[2], 'wb') f.write(t) f.close() ================================================ FILE: devtools/itemmake/samplescript.txt ================================================ SOUND MULTIPLIER: 2 IMAGE TABLE: C:\Users\Natalie\Pictures\madworld\mad.bmp C:\Users\Natalie\Pictures\madworld\madi.bmp C:\Users\Natalie\Pictures\madworld\title.bmp C:\Users\Natalie\Pictures\madworld\tree1.bmp C:\Users\Natalie\Pictures\madworld\tree2.bmp C:\Users\Natalie\Pictures\madworld\tree3.bmp C:\Users\Natalie\Pictures\madworld\treeg1.bmp C:\Users\Natalie\Pictures\madworld\treeg2.bmp C:\Users\Natalie\Pictures\madworld\treeg3.bmp C:\Users\Natalie\Pictures\madworld\windowsit1.bmp C:\Users\Natalie\Pictures\madworld\windowsit2.bmp C:\Users\Natalie\Pictures\madworld\windowsit3.bmp C:\Users\Natalie\Pictures\madworld\windowclose.bmp C:\Users\Natalie\Pictures\madworld\windowclose2.bmp C:\Users\Natalie\Pictures\madworld\win1.bmp C:\Users\Natalie\Pictures\madworld\win0.bmp C:\Users\Natalie\Pictures\madworld\winvc2.bmp C:\Users\Natalie\Pictures\madworld\winvc.bmp C:\Users\Natalie\Pictures\madworld\hands2.bmp C:\Users\Natalie\Pictures\madworld\hands.bmp C:\Users\Natalie\Pictures\madworld\treewin2.bmp C:\Users\Natalie\Pictures\madworld\treewin.bmp C:\Users\Natalie\Pictures\madworld\candle1.bmp C:\Users\Natalie\Pictures\madworld\candle2.bmp C:\Users\Natalie\Pictures\madworld\candle3.bmp C:\Users\Natalie\Pictures\madworld\bday.bmp C:\Users\Natalie\Pictures\madworld\bday2.bmp C:\Users\Natalie\Pictures\madworld\wd6.bmp C:\Users\Natalie\Pictures\madworld\wd1.bmp C:\Users\Natalie\Pictures\madworld\wd2.bmp C:\Users\Natalie\Pictures\madworld\wd3.bmp C:\Users\Natalie\Pictures\madworld\wd4.bmp C:\Users\Natalie\Pictures\madworld\wd5.bmp C:\Users\Natalie\Pictures\madworld\ball2.bmp C:\Users\Natalie\Pictures\madworld\d1.bmp C:\Users\Natalie\Pictures\madworld\d2.bmp C:\Users\Natalie\Pictures\madworld\d3.bmp C:\Users\Natalie\Pictures\madworld\d4.bmp C:\Users\Natalie\Pictures\madworld\ball.bmp IMAGE: title 0x70 IMAGE: tree3 0x20 IMAGE: tree2 0x20 IMAGE: tree1 0x30 IMAGE: windowsit1 0x20 IMAGE: windowsit2 0x20 IMAGE: windowsit3 0x30 IMAGE: treeg1 0x20 IMAGE: treeg2 0x20 IMAGE: treeg3 0x30 #rif 1 4 repeat start NOTE: windowclose D 1 NOTE: windowclose2 D 1 NOTE: windowclose F 1 NOTE: windowclose2 F 1 NOTE: windowclose D 1 NOTE: windowclose2 D 1 NOTE: windowclose A 1 NOTE: windowclose2 A 2 NOTE: windowclose A 2 NOTE: windowclose2 F 3 NOTE: windowclose G 1 NOTE: windowclose2 G 2 NOTE: windowclose G 2 NOTE: windowclose2 E 3 NOTE: windowclose G 1 NOTE: windowclose2 G 2 NOTE: windowclose G 2 NOTE: windowclose2 F 1 NOTE: windowclose2 E 1 NOTE: windowclose2 D 3 NOTE: win0 D 1 NOTE: win1 D 1 NOTE: win0 F 1 NOTE: win1 F 1 NOTE: win0 D 1 NOTE: win1 D 1 NOTE: win0 A 1 NOTE: win1 A 2 NOTE: win0 A 2 NOTE: win1 F 3 NOTE: win0 G 1 NOTE: win1 G 2 NOTE: win0 G 2 NOTE: win1 E 3 NOTE: win0 G 1 NOTE: win1 G 2 NOTE: win0 G 2 NOTE: win1 F 1 NOTE: win0 E 1 NOTE: win1 D 3 NOTE: winvc D 1 NOTE: winvc2 D 1 NOTE: winvc F 1 NOTE: winvc2 F 1 NOTE: winvc D 1 NOTE: winvc2 D 1 NOTE: winvc A 1 NOTE: winvc2 A 2 NOTE: winvc A 2 NOTE: winvc2 F 3 NOTE: winvc G 1 NOTE: winvc2 G 2 NOTE: winvc G 2 NOTE: winvc2 E 3 NOTE: winvc G 1 NOTE: winvc2 G 2 NOTE: winvc G 2 NOTE: winvc2 F 1 NOTE: winvc E 1 NOTE: winvc2 D 3 NOTE: win0 D 1 NOTE: win1 D 1 NOTE: win0 F 1 NOTE: win1 F 1 NOTE: win0 D 1 NOTE: win1 D 1 NOTE: win0 A 1 NOTE: win1 A 2 NOTE: win0 A 2 NOTE: win1 F 3 NOTE: win0 G 1 NOTE: win1 G 2 NOTE: win0 G 2 NOTE: win1 E 3 NOTE: win0 G 1 NOTE: win1 G 2 NOTE: win0 G 2 NOTE: win1 F 1 NOTE: win0 E 1 NOTE: win1 D 3 #rif 1 4 repeat end NOTE: hands2 D 1 NOTE: hands D 1 NOTE: hands2 F 1 NOTE: hands F 1 NOTE: hands2 A 1 NOTE: hands A 1 NOTE: hands2 B 1 NOTE: hands G 1 IMAGE: hands 6 NOTE: hands2 G 1 NOTE: hands B 1 NOTE: hands2 B 1 NOTE: hands G 1 NOTE: hands2 G 1 NOTE: hands D 1 #begin IMAGE: hands2 6 NOTE: hands D 1 NOTE: hands2 F 1 NOTE: hands F 1 NOTE: hands2 A 1 NOTE: hands A 1 NOTE: hands2 B 1 NOTE: hands G 1 NOTE: hands G 1 NOTE: hands2 G 1 NOTE: hands B 1 NOTE: hands2 B 1 NOTE: hands G 1 NOTE: hands2 G 1 NOTE: hands D 1 NOTE: hands2 D 1 NOTE: hands D 1 NOTE: hands2 F 1 NOTE: hands F 1 NOTE: hands2 A 1 NOTE: hands A 1 NOTE: hands2 B 1 NOTE: hands G 1 IMAGE: hands 6 NOTE: hands2 G 1 NOTE: hands B 1 NOTE: hands2 B 1 NOTE: hands G 1 NOTE: hands2 G 1 NOTE: hands D 1 begin IMAGE: hands2 6 NOTE: hands D 1 NOTE: hands2 F 1 NOTE: hands F 1 NOTE: hands2 A 1 NOTE: hands A 1 NOTE: hands2 B 1 NOTE: hands G 1 NOTE: hands G 1 NOTE: hands2 G 1 NOTE: hands B 1 NOTE: hands2 B 1 NOTE: hands G 1 NOTE: hands2 G 1 NOTE: hands D 1 #mad world start IMAGE: hands2 15 NOTE: treewin F 5 NOTE: treewin2 D 7 IMAGE: treewin2 15 NOTE: hands F 5 NOTE: hands2 D 7 IMAGE: hands2 15 NOTE: treewin F 5 NOTE: treewin2 D 7 IMAGE: treewin2 15 NOTE: hands F 5 NOTE: hands2 D 7 #begin part 2 #rif 1 4 repeat start NOTE: candle1 D 1 NOTE: candle1 D 1 NOTE: candle1 F 1 NOTE: candle1 F 1 NOTE: candle2 D 1 NOTE: candle2 D 1 NOTE: candle2 A 1 NOTE: candle2 A 2 NOTE: candle3 A 2 NOTE: candle3 F 3 NOTE: candle3 G 1 NOTE: candle3 G 2 NOTE: bday G 2 NOTE: bday E 3 NOTE: bday G 1 NOTE: bday G 2 NOTE: bday2 G 2 NOTE: bday2 F 1 NOTE: bday2 E 1 NOTE: bday2 D 3 NOTE: windowclose D 1 NOTE: windowclose2 D 1 NOTE: windowclose F 1 NOTE: windowclose2 F 1 NOTE: windowclose D 1 NOTE: windowclose D 1 NOTE: windowclose2 A 1 NOTE: windowclose A 2 NOTE: windowclose2 A 2 NOTE: windowclose F 3 NOTE: windowclose2 G 1 NOTE: windowclose G 2 NOTE: windowclose2 G 2 NOTE: windowclose E 3 NOTE: windowclose G 1 NOTE: windowclose2 G 2 NOTE: windowclose G 2 NOTE: windowclose2 F 1 NOTE: windowclose E 1 NOTE: windowclose2 D 3 NOTE: winvc D 1 NOTE: winvc2 D 1 NOTE: winvc F 1 NOTE: winvc2 F 1 NOTE: winvc D 1 NOTE: winvc2 D 1 NOTE: winvc A 1 NOTE: winvc2 A 2 NOTE: winvc A 2 NOTE: winvc2 F 3 NOTE: winvc G 1 NOTE: winvc2 G 2 NOTE: winvc G 2 NOTE: winvc2 E 3 NOTE: winvc G 1 NOTE: winvc2 G 2 NOTE: winvc G 2 NOTE: winvc2 F 1 NOTE: winvc E 1 NOTE: winvc2 D 3 NOTE: windowclose2 D 1 NOTE: windowclose D 1 NOTE: windowclose F 1 NOTE: windowclose2 F 1 NOTE: windowclose D 1 NOTE: windowclose2 D 1 NOTE: windowclose A 1 NOTE: windowclose2 A 2 NOTE: windowclose A 2 NOTE: windowclose2 F 3 NOTE: windowclose G 1 NOTE: windowclose2 G 2 NOTE: windowclose G 2 NOTE: windowclose2 E 3 NOTE: windowclose G 1 NOTE: windowclose2 G 2 NOTE: windowclose G 2 NOTE: windowclose2 F 1 NOTE: windowclose E 1 NOTE: windowclose2 D 3 #rif 1 4 repeat end NOTE: wd1 D 1 NOTE: wd2 D 1 NOTE: wd3 F 1 NOTE: wd4 F 1 NOTE: wd5 A 1 NOTE: wd6 A 1 NOTE: wd1 B 1 NOTE: wd2 G 1 IMAGE: wd3 6 NOTE: wd4 G 1 NOTE: wd5 B 1 NOTE: wd6 B 1 NOTE: wd1 G 1 NOTE: wd2 G 1 NOTE: wd3 D 1 begin IMAGE: wd4 6 NOTE: wd5 D 1 NOTE: wd6 F 1 NOTE: wd1 F 1 NOTE: wd2 A 1 NOTE: wd3 A 1 NOTE: wd4 B 1 NOTE: wd5 G 1 NOTE: wd6 G 1 NOTE: wd1 G 1 NOTE: wd2 B 1 NOTE: wd3 B 1 NOTE: wd4 G 1 NOTE: wd5 G 1 NOTE: wd6 D 1 NOTE: wd1 D 1 NOTE: wd2 D 1 NOTE: wd3 F 1 NOTE: wd4 F 1 NOTE: wd5 A 1 NOTE: wd6 A 1 NOTE: wd1 B 1 NOTE: wd2 G 1 IMAGE: wd3 6 NOTE: wd4 G 1 NOTE: wd5 B 1 NOTE: wd6 B 1 NOTE: wd1 G 1 NOTE: wd2 G 1 NOTE: wd3 D 1 begin IMAGE: wd3 6 NOTE: wd4 D 1 NOTE: wd5 F 1 NOTE: wd6 F 1 NOTE: wd1 A 1 NOTE: wd1 A 1 NOTE: wd2 B 1 NOTE: wd3 G 1 NOTE: wd4 G 1 NOTE: wd5 G 1 NOTE: wd6 B 1 NOTE: wd1 B 1 NOTE: wd2 G 1 NOTE: wd3 G 1 NOTE: wd4 D 1 #mad world start IMAGE: wd4 15 NOTE: wd5 F 5 NOTE: wd6 D 7 IMAGE: hands2 15 NOTE: hands F 5 NOTE: hands2 D 7 IMAGE: hands2 15 NOTE: hands F 5 NOTE: hands2 D 7 IMAGE: hands2 15 NOTE: hands F 5 NOTE: hands2 D 7 IMAGE: ball 30 IMAGE: ball2 30 IMAGE: d1 10 IMAGE: d2 10 IMAGE: d3 10 IMAGE: d4 10 IMAGE: d1 10 IMAGE: d2 10 IMAGE: d3 10 IMAGE: d4 10 IMAGE: d1 10 IMAGE: d2 10 IMAGE: d3 10 IMAGE: d4 10 #begin end NOTE: hands2 D 1 NOTE: hands D 1 NOTE: hands2 F 1 NOTE: hands F 1 NOTE: hands2 A 1 NOTE: hands A 1 NOTE: hands2 B 1 NOTE: hands G 1 IMAGE: hands 6 NOTE: hands2 G 1 NOTE: hands B 1 NOTE: hands2 B 1 NOTE: hands G 1 NOTE: hands2 G 1 NOTE: hands D 1 #begin IMAGE: hands2 6 NOTE: hands D 1 NOTE: hands2 F 1 NOTE: hands F 1 NOTE: hands2 A 1 NOTE: hands A 1 NOTE: hands2 B 1 NOTE: hands G 1 NOTE: hands G 1 NOTE: hands2 G 1 NOTE: hands B 1 NOTE: hands2 B 1 NOTE: hands G 1 NOTE: hands2 G 1 NOTE: hands D 1 NOTE: hands2 D 1 NOTE: hands D 1 NOTE: hands2 F 1 NOTE: hands F 1 NOTE: hands2 A 1 NOTE: hands A 1 NOTE: hands2 B 1 NOTE: hands G 1 IMAGE: hands 6 NOTE: hands2 G 1 NOTE: hands B 1 NOTE: hands2 B 1 NOTE: hands G 1 NOTE: hands2 G 1 NOTE: hands D 1 begin IMAGE: hands2 6 NOTE: hands D 1 NOTE: hands2 F 1 NOTE: hands F 1 NOTE: hands2 A 1 NOTE: hands A 1 NOTE: hands2 B 1 NOTE: hands G 1 NOTE: hands G 1 NOTE: hands2 G 1 NOTE: hands B 1 NOTE: hands2 B 1 NOTE: hands G 1 NOTE: hands2 G 1 NOTE: hands D 1 #mad world start IMAGE: hands2 15 NOTE: hands F 5 NOTE: hands2 D 7 IMAGE: hands 15 NOTE: hands F 5 NOTE: hands2 D 7 IMAGE: wd1 15 NOTE: wd2 F 5 NOTE: wd3 D 7 IMAGE: wd4 15 NOTE: wd5 F 5 NOTE: wd6 D 7 IMAGE: treeg1 0x20 IMAGE: treeg2 0x20 IMAGE: treeg3 0x30 END ================================================ FILE: die/README ================================================ Repository for Tamagotchi chip photos! Files: logo.jpg -- close up of the only logo on the die tamatowntamago.jpg -- high resolution die photo Questions? Comments? Contributions? Contact: namely_audacious@hotmail.com / @natashenka ================================================ FILE: disassembler/README ================================================ Very rudimentary script to detect and disassemble GeneralPlus (SunPlus) bytecode in a binary Decodes 'standard'(according to GeneralPlus) and 'SunPlus' 6502 bytecode bytecode*.txt -- bytecode listings used for disassembly, can be changed in script bytecode.txt -- default SunPlus bytecode bytecodes.txt -- shrinkage mode bytecoder.txt -- reduce mode bytecoden.txt -- normal mode dissa.py -- the script testbinary.bin -- test binary, compiled using FortisIDE ================================================ FILE: disassembler/a.txt ================================================ assembly found, size 61 index 21253 AND (85) 85 85 AND (85) 85 85 AND (85) 90 149 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 170 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 106 0 assembly found, size 36 index 21315 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 assembly found, size 28 index 21352 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 170 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 106 0 assembly found, size 43 index 21545 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 ADC (86) 170 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 48 31 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 170 assembly found, size 28 index 21589 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 170 assembly found, size 80 index 21808 AND (85) 85 85 AND (85) 85 85 AND (85) 90 149 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 48 31 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 170 assembly found, size 53 index 21889 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 48 31 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 170 assembly found, size 35 index 21943 AND (85) 48 31 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 170 assembly found, size 27 index 21980 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 170 149 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 SEI (90) assembly found, size 47 index 22183 AND (85) 85 85 AND (85) 85 85 AND (85) 90 149 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 SEI (90) AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 96 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 101 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 96 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 101 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 88 LDY (48) 31 assembly found, size 31 index 22231 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 SEI (90) AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 96 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 101 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 96 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 101 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 88 LDY (48) 31 assembly found, size 46 index 29611 AND (85) 85 85 AND (85) 85 85 SBC (127) 255 245 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 48 ADC (31) 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 169 85 AND (85) 85 169 AND (85) 85 85 AND (85) 85 86 assembly found, size 30 index 29658 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 85 85 AND (85) 169 85 AND (85) 85 169 AND (85) 85 85 AND (85) 85 86 assembly found, size 30 index 32252 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 32 ORA (4) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 128 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 0 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 48 BPL (8) 0 BPL (8) 1 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 0 assembly found, size 27 index 50273 LDY (48) 31 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 BIT (17) 17 RTS (18) STX (169) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 68 ORA (68) 74 ADC (86) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 17 BIT (17) 25 PHA (66) BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 ORA (68) 68 assembly found, size 32 index 50899 BIT (17) 17 BIT (17) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 170 assembly found, size 33 index 51270 ROL (145) 17 BIT (17) 17 BIT (17) 17 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 assembly found, size 38 index 51634 ORA (68) 68 ORA (68) 68 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 assembly found, size 32 index 53778 JSR (16) 1 34 JSR (16) 1 34 JSR (16) 1 34 JSR (16) 1 34 JSR (16) 1 34 JSR (16) 1 34 JSR (16) 1 34 JSR (16) 1 34 JSR (16) 1 34 JSR (16) 1 34 JSR (16) 1 34 JSR (16) 1 34 JSR (16) 1 34 JSR (16) 1 34 JSR (16) 1 34 JSR (16) 1 34 JSR (16) 1 34 JSR (16) 1 34 JSR (16) 1 34 JSR (16) 1 34 JSR (16) 1 34 JSR (16) 1 34 JSR (16) 1 34 JSR (16) 85 98 AND (85) 85 98 AND (85) 85 98 AND (85) 85 98 AND (85) 85 98 AND (85) 85 98 AND (85) 85 98 AND (85) 85 98 AND (85) 0 170 assembly found, size 44 index 73396 EOR (14) 13 AND (85) 85 85 PLP (80) AND (85) 85 85 PLP (80) AND (85) 85 85 PLP (80) ADC (95) 85 95 PLP (80) ADC (95) 255 255 PLP (80) ADC (95) 255 255 PLP (80) ADC (95) 255 255 ROL (208) SBC (127) 63 207 ROL (208) LDA (124) 15 3 ROL (208) LDA (124) 192 51 ROL (208) TAY (112) EOR (15) 0 ROL (208) AND (92) 15 3 PLP (80) ADC (87) 255 253 PLP (80) EOR (14) 13 AND (85) 85 85 PLP (80) AND (85) 87 85 PLP (80) AND (85) 255 245 PLP (80) ADC (87) 12 13 PLP (80) AND (92) 0 3 PLP (80) AND (92) 0 3 PLP (80) ADC (95) 0 15 PLP (80) TAY (112) assembly found, size 28 index 73487 ROL (208) TAY (112) ASL (192) LDY (48) 208 AND (92) 63 195 PLP (80) ADC (87) 240 253 PLP (80) AND (85) 95 85 PLP (80) EOR (14) 13 AND (85) 85 85 PLP (80) AND (85) 85 85 PLP (80) AND (85) 253 245 PLP (80) AND (85) 87 85 PLP (80) ADC (87) 255 245 PLP (80) AND (92) 0 13 PLP (80) AND (92) 0 13 PLP (80) TAY (112) ASL (192) LSR (195) 80 112 assembly found, size 29 index 73641 PLP (80) ADC (95) 0 0 ROL (208) AND (85) 192 0 ROL (208) AND (85) 204 48 ROL (208) AND (85) 192 3 PLP (80) ADC (87) 15 13 PLP (80) ADC (95) 255 245 PLP (80) EOR (14) 13 AND (85) 85 85 PLP (80) AND (85) 85 85 PLP (80) AND (85) 85 85 PLP (80) LDA (125) 85 95 PLP (80) LSR (195) 127 112 ROL (208) LSR (195) 192 240 ROL (208) LDA (124) 0 15 PLP (80) TAY (112) assembly found, size 30 index 74123 ROL (208) CPX (115) 255 252 ROL (208) LDA (124) 0 3 ROL (208) TAY (112) ASL (192) LDY (48) 208 TAY (112) EOR (15) 0 ROL (208) LDA (124) 48 195 ROL (208) CPX (115) 255 252 ROL (208) LDA (125) 85 87 ROL (208) EOR (14) 13 AND (85) 85 85 PLP (80) AND (85) 85 85 PLP (80) AND (85) 85 85 PLP (80) AND (85) 85 117 PLP (80) ADC (95) 255 253 PLP (80) SBC (127) 255 255 PLP (80) assembly found, size 45 index 74785 SBC (63) 60 ROL (208) ASL (192) ASL (192) ASL (192) ROL (208) LDA (124) 204 207 PLP (80) ADC (87) 255 245 PLP (80) EOR (14) 13 AND (85) 85 85 PLP (80) AND (85) 85 85 PLP (80) AND (85) 85 85 PLP (80) AND (85) 85 85 PLP (80) AND (93) 85 87 PLP (80) LDA (125) 255 247 ROL (208) ADC (87) 0 13 PLP (80) AND (92) 0 3 PLP (80) AND (92) 0 3 PLP (80) AND (92) 192 51 PLP (80) LDA (124) 15 3 ROL (208) LSR (195) 255 252 LDY (48) 255 AND (85) 95 240 EOR (14) 13 AND (85) 85 85 PLP (80) AND (85) 253 85 PLP (80) ADC (95) 63 253 PLP (80) SBC (127) 204 255 PLP (80) assembly found, size 76 index 75003 ROL (208) LSR (195) 51 48 ROL (208) SBC (127) 0 63 PLP (80) AND (85) 255 213 PLP (80) EOR (14) 13 AND (85) 85 85 PLP (80) AND (85) 85 85 PLP (80) AND (85) 85 85 PLP (80) AND (85) 85 85 PLP (80) AND (85) 255 245 PLP (80) ADC (87) 63 205 PLP (80) AND (92) 63 3 PLP (80) AND (92) 60 3 PLP (80) AND (92) 15 3 PLP (80) AND (92) 0 3 PLP (80) AND (92) 192 51 PLP (80) CPX (115) 15 12 ROL (208) SBC (127) 255 255 ROL (208) EOR (14) 13 AND (85) 85 85 PLP (80) AND (85) 85 85 PLP (80) AND (85) 85 85 PLP (80) AND (85) 85 85 PLP (80) AND (85) 127 213 PLP (80) SBC (127) 240 255 ROL (208) TAY (112) INC (243) 48 208 CPX (115) 15 12 ROL (208) AND (92) 0 3 PLP (80) AND (92) 0 3 PLP (80) AND (92) 192 51 ROL (208) CPX (115) 15 12 ROL (208) SBC (127) 255 255 ROL (208) EOR (14) 13 AND (85) 85 85 PLP (80) AND (85) 95 245 PLP (80) AND (85) 240 15 PLP (80) ADC (87) 48 12 ROL (208) ADC (87) 15 240 ROL (208) AND (92) 192 3 LDY (48) 92 SBC (63) 252 LDY (48) 95 assembly found, size 37 index 75080 AND (85) 85 85 PLP (80) AND (85) 85 85 PLP (80) AND (85) 127 213 PLP (80) SBC (127) 240 255 ROL (208) TAY (112) INC (243) 48 208 CPX (115) 15 12 ROL (208) AND (92) 0 3 PLP (80) AND (92) 0 3 PLP (80) AND (92) 192 51 ROL (208) CPX (115) 15 12 ROL (208) SBC (127) 255 255 ROL (208) EOR (14) 13 AND (85) 85 85 PLP (80) AND (85) 95 245 PLP (80) AND (85) 240 15 PLP (80) ADC (87) 48 12 ROL (208) ADC (87) 15 240 ROL (208) AND (92) 192 3 LDY (48) 92 SBC (63) 252 LDY (48) 95 assembly found, size 42 index 75279 ORA (12) 55 ROL (208) ADC (87) 255 245 PLP (80) EOR (14) 13 AND (85) 127 85 PLP (80) AND (85) 115 85 PLP (80) AND (85) 127 85 PLP (80) AND (85) 93 85 PLP (80) ADC (95) 255 253 PLP (80) AND (92) 12 13 PLP (80) AND (92) 0 13 PLP (80) AND (92) 0 13 PLP (80) AND (92) 192 205 PLP (80) LDA (124) 63 15 PLP (80) SBC (127) 192 255 PLP (80) TAY (112) SBC (63) 3 PLP (80) SBC (127) 255 255 PLP (80) EOR (14) 13 ADC (87) 255 245 PLP (80) ADC (95) 243 253 PLP (80) SBC (127) 0 63 PLP (80) LDA (124) 0 15 PLP (80) TAY (112) assembly found, size 30 index 75361 PLP (80) SBC (127) 192 255 PLP (80) ASL (192) SBC (63) 0 ROL (208) ASL (192) CPX (51) 48 ROL (208) LSR (195) 48 255 PLP (80) SBC (127) 192 13 PLP (80) AND (92) 63 13 PLP (80) ADC (87) 192 245 PLP (80) AND (85) 255 213 PLP (80) EOR (14) 13 AND (85) 85 85 PLP (80) AND (85) 117 213 PLP (80) ADC (95) 127 223 PLP (80) SBC (119) 255 253 ROL (208) ADC (87) 255 253 PLP (80) assembly found, size 28 index 75433 ASL (192) CPX (51) 112 AND (92) 63 195 PLP (80) ADC (87) 240 253 PLP (80) AND (85) 95 85 PLP (80) EOR (14) 13 AND (85) 85 85 PLP (80) AND (85) 85 85 PLP (80) ADC (95) 85 125 PLP (80) SBC (127) 213 255 PLP (80) SBC (127) 247 255 PLP (80) ADC (95) 255 253 PLP (80) SBC (127) 255 255 PLP (80) SBC (127) 255 255 PLP (80) CPX (115) 255 243 PLP (80) TAY (112) assembly found, size 30 index 75588 ORA (12) 48 LSR (195) 0 12 LDY (48) 195 LDY (48) 204 LDY (48) 127 ASL (192) SBC (63) 208 AND (85) 192 53 PLP (80) AND (85) 127 213 PLP (80) EOR (14) 13 AND (85) 85 85 PLP (80) AND (85) 85 87 ROL (208) AND (85) 255 247 ROL (208) ADC (87) 255 255 PLP (80) ADC (95) 255 255 PLP (80) ADC (95) 0 15 ROL (208) LDA (124) 0 3 ROL (208) LDA (124) 0 3 ROL (208) LDA (124) 192 51 ROL (208) assembly found, size 101 index 81383 ORA (68) 68 ORA (68) 68 EOR (70) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 17 RTS (18) STX (161) 26 assembly found, size 50 index 81485 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 17 RTS (18) STX (161) 26 assembly found, size 100 index 81761 CLI (74) BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 BVS (26) 170 ROL (145) 17 BIT (17) 26 assembly found, size 49 index 81862 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 BIT (17) 17 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 ORA (68) 68 BVS (26) 170 ROL (145) 17 BIT (17) 26 [2, 2, 2, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 2, 2, 1, 2, 2, 3, 3, 2, 2, 2, 2, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 2, 2, 2, 2, 3, 2, 2, 3, 2, 2, 3, 3, 1, 1, 2, 2, 2, 3, 3, 3, 2, 2, 2, 2, 3, 3, 1, 1, 3, 3, 3, 2, 2, 2, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 2, 2, 2, 3, 3, 1, 2, 2, 3, 3, 1, 2, 2, 2, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 2, 2, 3, 3, 1, 2, 2, 3, 3, 1, 1, 2, 2, 2, 3, 3, 3, 2, 2, 1, 1, 1, 2, 2, 3, 3, 3, 2, 2, 2, 2, 3, 2, 2, 3, 1, 1, 1, 1, 1, 1] [105, 101, 117, 109, 125, 121, 97, 113, 41, 37, 53, 45, 61, 57, 33, 49, 10, 6, 22, 14, 30, 144, 176, 240, 36, 44, 48, 208, 16, 80, 112, 24, 216, 88, 184, 201, 197, 213, 205, 221, 217, 193, 209, 224, 228, 236, 192, 196, 204, 198, 214, 206, 222, 202, 136, 73, 69, 85, 77, 93, 89, 65, 81, 230, 246, 238, 254, 232, 200, 76, 108, 32, 169, 165, 181, 173, 189, 185, 161, 177, 162, 166, 182, 174, 190, 160, 164, 180, 172, 188, 74, 70, 86, 78, 94, 234, 9, 5, 21, 13, 29, 25, 1, 17, 72, 8, 104, 40, 42, 38, 54, 46, 62, 106, 102, 118, 110, 126, 64, 96, 233, 229, 245, 237, 253, 249, 225, 241, 56, 248, 120, 133, 149, 141, 157, 153, 129, 145, 134, 150, 142, 132, 148, 140, 170, 168, 186, 138, 154, 152] [86, 23, 31, 87, 95, 94, 22, 30, 84, 21, 29, 85, 93, 92, 20, 28, 192, 129, 137, 193, 201, 40, 56, 58, 17, 81, 24, 42, 8, 10, 26, 72, 106, 74, 120, 102, 39, 47, 103, 111, 110, 38, 46, 50, 51, 115, 34, 35, 99, 163, 171, 227, 235, 226, 96, 70, 7, 15, 71, 79, 78, 6, 14, 179, 187, 243, 251, 114, 98, 67, 83, 16, 116, 53, 61, 117, 125, 124, 52, 60, 176, 177, 185, 241, 249, 48, 49, 57, 113, 121, 194, 131, 139, 195, 203, 242, 68, 5, 13, 69, 77, 76, 4, 12, 66, 64, 82, 80, 208, 145, 153, 209, 217, 210, 147, 155, 211, 219, 2, 18, 118, 55, 63, 119, 127, 126, 54, 62, 88, 122, 90, 37, 45, 101, 109, 108, 36, 44, 161, 169, 225, 33, 41, 97, 240, 112, 248, 224, 232, 104] ================================================ FILE: disassembler/bytecode.txt ================================================ 001: ADC #dd ADC A,dd 69H 56H 2 2 cpu3 ; immediate 002: ADC aa ADC A,(aa) 65H 17H 2 3 cpu3 ; zero page 003: AND #dd AND A,dd 29H 54H 2 2 cpu3 ; immediate 004: AND aa AND A,(aa) 25H 15H 2 3 cpu3 ; zero page 005: BCC ?? JR NC,?? 90H 28H 2 2 cpu3 ; relative 006: BCS ?? JR C,?? B0H 38H 2 2 cpu3 ; relative 007: BEQ ?? JR Z,?? F0H 3AH 2 2 cpu3 ; relative 008: BIT aa BIT (aa) 24H 11H 2 3 cpu5 ; zero page 009: BIT aaaa BIT (aaaa) 2CH 51H 3 4 cpu5 ; absolute 010: BMI ?? JR M,?? 30H 18H 2 2 cpu3 ; relative 011: BNE ?? JR NZ,?? D0H 2AH 2 2 cpu3 ; relative 012: BPL ?? JR P,?? 10H 08H 2 2 cpu3 ; relative 013: BRK BRK 00H 00H 1 7 cpu3 ; implied 014: BVC ?? JR NOV,?? 50H 0AH 2 2 cpu3 ; relative 015: BVS ?? JR OV,?? 70H 1AH 2 2 cpu3 ; relative 016: CLC CCF 18H 48H 1 2 cpu3 ; implied 017: CLI EI 58H 4AH 1 2 cpu3 ; implied 018: CLV CVF B8H 78H 1 2 cpu3 ; implied 019: CMP #dd CP A,dd C9H 66H 2 2 cpu3 ; immediate 020: CMP aa CP A,(aa) C5H 27H 2 3 cpu3 ; zero page 021: CMP aa,X CP A,(aa+X) D5H 2FH 2 4 cpu3 ;zero page indexed x 022: CPX #dd CP X,dd E0H 32H 2 2 cpu3 ; immediate 023: CPX aa CP X,(aa) E4H 33H 2 3 cpu3 ; zero page 024: DEC aa DEC (aa) C6H A3H 2 5 cpu3 ; zero page 025: DEC aa,X DEC (aa+X) D6H ABH 2 6 cpu5 ;zero page indexed x 026: DEX DEC X CAH E2H 1 2 cpu3 ; implied 027: EOR #dd XOR A,dd 49H 46H 2 2 cpu3 ; immediate 028: EOR aa XOR A,(aa) 45H 07H 2 3 cpu3 ; zero page 029: EOR aa,X XOR A,(aa+X) 55H 0FH 2 4 cpu5 ;zero page indexed x 030: INC aa INC (aa) E6H B3H 2 5 cpu3 ; zero page 031: INX INC X E8H 72H 1 2 cpu3 ; implied 032: JMP aaaa JP aaaa 4CH 43H 3 3 cpu3 ; absolute 033: JMP (aaaa) JP (aaaa) 6CH 53H 3 5 cpu3 ; indirect absolut 034: JSR aaaa CALL aaaa 20H 10H 3 6 cpu3 ; absolute 035: LDA #dd LD A,dd A9H 74H 2 2 cpu3 ; immediate 036: LDA aa LD A,(aa) A5H 35H 2 3 cpu3 ; zero page 037: LDA aa,X LD A,(aa+X) B5H 3DH 2 4 cpu3 ;zero page indexed x 038: LDA aaaa LD A,(aaaa) ADH 75H 3 4 cpu3 ; absolute 039: LDA aaaa,X LD A,(aaaa+X) BDH 7DH 3 4 cpu3 ;absolute indexed x 040: LDA (aa,X) LD A,((aa+X)) A1H 34H 2 6 cpu3 ; indexed indirect x 041: LDX #dd LD X,dd A2H B0H 2 2 cpu3 ; immediate 042: LDX aa LD X,(aa) A6H B1H 2 3 cpu3 ; zero page 043: LDX aaaa LD X,(aaaa) AEH F1H 3 4 cpu5 ; absolute 044: NOP NOP EAH F2H 1 2 cpu3 ; implied 045: ORA #dd OR A,dd 09H 44H 2 2 cpu3 ; immediate 046: ORA aa OR A,(aa) 05H 05H 2 3 cpu3 ; zero page 047: PHA PUSH A 48H 42H 1 3 cpu3 ; implied 048: PHP PUSH F 08H 40H 1 3 cpu3 ; implied 049: PLA POP A 68H 52H 1 4 cpu3 ; implied 050: PLP POP F 28H 50H 1 4 cpu3 ; implied 051: ROL A ROL A 2AH D0H 1 2 cpu3 ; accumulator 052: ROL aa ROL (aa) 26H 91H 2 5 cpu3 ; zero page 053: ROR A ROR A 6AH D2H 1 2 cpu3 ; accumulator 054: ROR aa ROR (aa) 66H 93H 2 5 cpu3 ; zero page 055: RTI RETI 40H 02H 1 6 cpu3 ; implied 056: RTS RET 60H 12H 1 6 cpu3 ; implied 057: SBC #dd SBC A,dd E9H 76H 2 2 cpu3 ; immediate 058: SBC aa SBC A,(aa) E5H 37H 2 3 cpu3 ; zero page 059: SEC SCF 38H 58H 1 2 cpu3 ; implied 060: SEI DI 78H 5AH 1 2 cpu3 ; implied 061: STA aa LD (aa),A 85H 25H 2 3 cpu3 ; zero page 062: STA aa,X LD (aa+X),A 95H 2DH 2 4 cpu3 ;zero page indexed x 063: STA (aa,X) LD ((aa+X)),A 81H 24H 2 6 cpu3 ; indexed indirect x 064: STX aa LD (aa),X 86H A1H 2 3 cpu3 ; zero page 065: STX aaaa LD (aaaa),X 8EH E1H 3 4 cpu3 ; absolute 066: TAX LD X,A AAH F0H 1 2 cpu5 ; implied 067: TSX LD X,SP BAH F8H 1 2 cpu3 ; implied 068: TXA LD A,X 8AH E0H 1 2 cpu5 ; implied 069: TXS LD SP,X 9AH E8H 1 2 cpu3 ; implied ================================================ FILE: disassembler/bytecoden.txt ================================================ 001: ADC #dd ADC A,dd 69H 56H 2 2 cpu3 ; immediate 002: ADC aa ADC A,(aa) 65H 17H 2 3 cpu3 ; zero page 003: ADC aa,X ADC A,(aa+X) 75H 1FH 2 4 6502 ;zero page indexed x 004: ADC aaaa ADC A,(aaaa) 6DH 57H 3 4 6502 ; absolute 005: ADC aaaa,X ADC A,(aaaa+X) 7DH 5FH 3 4 6502 ;absolute indexed x 006: ADC aaaa,Y ADC A,(aaaa+Y) 79H 5EH 3 4 6502 ;absolute indexed y 007: ADC (aa,X) ADC A,((aa+X)) 61H 16H 2 6 6502 ; indexed indirect x 008: ADC (aa),Y ADC A,((aa)+Y) 71H 1EH 2 5 6502 ; indirect indexed y 009: AND #dd AND A,dd 29H 54H 2 2 cpu3 ; immediate 010: AND aa AND A,(aa) 25H 15H 2 3 cpu3 ; zero page 011: AND aa,X AND A,(aa+X) 35H 1DH 2 4 6502 ;zero page indexed x 012: AND aaaa AND A,(aaaa) 2DH 55H 3 4 6502 ; absolute 013: AND aaaa,X AND A,(aaaa+X) 3DH 5DH 3 4 6502 ;absolute indexed x 014: AND aaaa,Y AND A,(aaaa+Y) 39H 5CH 3 4 6502 ;absolute indexed y 015: AND (aa,X) AND A,((aa+X)) 21H 14H 2 6 6502 ; indexed indirect x 016: AND (aa),Y AND A,((aa)+Y) 31H 1CH 2 5 6502 ; indirect indexed y 017: ASL A ASL A 0AH C0H 1 2 6502 ; accumulator 018: ASL aa ASL (aa) 06H 81H 2 5 6502 ; zero page 019: ASL aa,X ASL (aa+X) 16H 89H 2 6 6502 ;zero page indexed x 020: ASL aaaa ASL (aaaa) 0EH C1H 3 6 6502 ; absolute 021: ASL aaaa,X ASL (aaaa+X) 1EH C9H 3 7 6502 ;absolute indexed x 022: BCC ?? JR NC,?? 90H 28H 2 2 cpu3 ; relative 023: BCS ?? JR C,?? B0H 38H 2 2 cpu3 ; relative 024: BEQ ?? JR Z,?? F0H 3AH 2 2 cpu3 ; relative 025: BIT aa BIT (aa) 24H 11H 2 3 cpu5 ; zero page 026: BIT aaaa BIT (aaaa) 2CH 51H 3 4 cpu5 ; absolute 027: BMI ?? JR M,?? 30H 18H 2 2 cpu3 ; relative 028: BNE ?? JR NZ,?? D0H 2AH 2 2 cpu3 ; relative 029: BPL ?? JR P,?? 10H 08H 2 2 cpu3 ; relative 030: BRK BRK 00H 00H 1 7 cpu3 ; implied 031: BVC ?? JR NOV,?? 50H 0AH 2 2 cpu3 ; relative 032: BVS ?? JR OV,?? 70H 1AH 2 2 cpu3 ; relative 033: CLC CCF 18H 48H 1 2 cpu3 ; implied 034: CLD CDF D8H 6AH 1 2 6502 ; implied 035: CLI EI 58H 4AH 1 2 cpu3 ; implied 036: CLV CVF B8H 78H 1 2 cpu3 ; implied 037: CMP #dd CP A,dd C9H 66H 2 2 cpu3 ; immediate 038: CMP aa CP A,(aa) C5H 27H 2 3 cpu3 ; zero page 039: CMP aa,X CP A,(aa+X) D5H 2FH 2 4 cpu3 ;zero page indexed x 040: CMP aaaa CP A,(aaaa) CDH 67H 3 4 6502 ; absolute 041: CMP aaaa,X CP A,(aaaa+X) DDH 6FH 3 4 6502 ;absolute indexed x 042: CMP aaaa,Y CP A,(aaaa+Y) D9H 6EH 3 4 6502 ;absolute indexed y 043: CMP (aa,X) CP A,((aa+X)) C1H 26H 2 6 6502 ; indexed indirect x 044: CMP (aa),Y CP A,((aa)+Y) D1H 2EH 2 5 6502 ; indirect indexed y 045: CPX #dd CP X,dd E0H 32H 2 2 cpu3 ; immediate 046: CPX aa CP X,(aa) E4H 33H 2 3 cpu3 ; zero page 047: CPX aaaa CP X,(aaaa) ECH 73H 3 4 6502 ; absolute 048: CPY #dd CP Y,dd C0H 22H 2 2 6502 ; immediate 049: CPY aa CP Y,(aa) C4H 23H 2 3 6502 ; zero page 050: CPY aaaa CP Y,(aaaa) CCH 63H 3 4 6502 ; absolute 051: DEC aa DEC (aa) C6H A3H 2 5 cpu3 ; zero page 052: DEC aa,X DEC (aa+X) D6H ABH 2 6 cpu5 ;zero page indexed x 053: DEC aaaa DEC (aaaa) CEH E3H 3 6 6502 ; absolute 054: DEC aaaa,X DEC (aaaa+X) DEH EBH 3 7 6502 ;absolute indexed x 055: DEX DEC X CAH E2H 1 2 cpu3 ; implied 056: DEY DEC Y 88H 60H 1 2 6502 ; implied 057: EOR #dd XOR A,dd 49H 46H 2 2 cpu3 ; immediate 058: EOR aa XOR A,(aa) 45H 07H 2 3 cpu3 ; zero page 059: EOR aa,X XOR A,(aa+X) 55H 0FH 2 4 cpu5 ;zero page indexed x 060: EOR aaaa XOR A,(aaaa) 4DH 47H 3 4 6502 ; absolute 061: EOR aaaa,X XOR A,(aaaa+X) 5DH 4FH 3 4 6502 ;absolute indexed x 062: EOR aaaa,Y XOR A,(aaaa+Y) 59H 4EH 3 4 6502 ;absolute indexed y 063: EOR (aa,X) XOR A,((aa+X)) 41H 06H 2 6 6502 ; indexed indirect x 064: EOR (aa),Y XOR A,((aa)+Y) 51H 0EH 2 5 6502 ; indirect indexed y 065: INC aa INC (aa) E6H B3H 2 5 cpu3 ; zero page 066: INC aa,X INC (aa+X) F6H BBH 2 6 6502 ;zero page indexed x 067: INC aaaa INC (aaaa) EEH F3H 3 6 6502 ; absolute 068: INC aaaa,X INC (aaaa+X) FEH FBH 3 7 6502 ;absolute indexed x 069: INX INC X E8H 72H 1 2 cpu3 ; implied 070: INY INC Y C8H 62H 1 2 6502 ; implied 071: JMP aaaa JP aaaa 4CH 43H 3 3 cpu3 ; absolute 072: JMP (aaaa) JP (aaaa) 6CH 53H 3 5 cpu3 ; indirect absolut 073: JSR aaaa CALL aaaa 20H 10H 3 6 cpu3 ; absolute 074: LDA #dd LD A,dd A9H 74H 2 2 cpu3 ; immediate 075: LDA aa LD A,(aa) A5H 35H 2 3 cpu3 ; zero page 076: LDA aa,X LD A,(aa+X) B5H 3DH 2 4 cpu3 ;zero page indexed x 077: LDA aaaa LD A,(aaaa) ADH 75H 3 4 cpu3 ; absolute 078: LDA aaaa,X LD A,(aaaa+X) BDH 7DH 3 4 cpu3 ;absolute indexed x 079: LDA aaaa,Y LD A,(aaaa+Y) B9H 7CH 3 4 6502 ;absolute indexed y 080: LDA (aa,X) LD A,((aa+X)) A1H 34H 2 6 cpu3 ; indexed indirect x 081: LDA (aa),Y LD A,((aa)+Y) B1H 3CH 2 5 6502 ; indirect indexed y 082: LDX #dd LD X,dd A2H B0H 2 2 cpu3 ; immediate 083: LDX aa LD X,(aa) A6H B1H 2 3 cpu3 ; zero page 084: LDX aa,Y LD X,(aa+Y) B6H B9H 2 4 6502 ;zero page indexed y 085: LDX aaaa LD X,(aaaa) AEH F1H 3 4 cpu5 ; absolute 086: LDX aaaa,Y LD X,(aaaa+Y) BEH F9H 3 4 6502 ;absolute indexed y 087: LDY #dd LD Y,dd A0H 30H 2 2 6502 ; immediate 088: LDY aa LD Y,(aa) A4H 31H 2 3 6502 ; zero page 089: LDY aa,X LD Y,(aa+X) B4H 39H 2 4 6502 ;zero page indexed x 090: LDY aaaa LD Y,(aaaa) ACH 71H 3 4 6502 ; absolute 091: LDY aaaa,X LD Y,(aaaa+X) BCH 79H 3 4 6502 ;absolute indexed x 092: LSR A LSR A 4AH C2H 1 2 6502 ; accumulator 093: LSR aa LSR (aa) 46H 83H 2 5 6502 ; zero page 094: LSR aa,X LSR (aa+X) 56H 8BH 2 6 6502 ;zero page indexed x 095: LSR aaaa LSR (aaaa) 4EH C3H 3 6 6502 ; absolute 096: LSR aaaa,X LSR (aaaa+X) 5EH CBH 3 7 6502 ;absolute indexed x 097: NOP NOP EAH F2H 1 2 cpu3 ; implied 098: ORA #dd OR A,dd 09H 44H 2 2 cpu3 ; immediate 099: ORA aa OR A,(aa) 05H 05H 2 3 cpu3 ; zero page 100: ORA aa,X OR A,(aa+X) 15H 0DH 2 4 6502 ;zero page indexed x 101: ORA aaaa OR A,(aaaa) 0DH 45H 3 4 6502 ; absolute 102: ORA aaaa,X OR A,(aaaa+X) 1DH 4DH 3 4 6502 ;absolute indexed x 103: ORA aaaa,Y OR A,(aaaa+Y) 19H 4CH 3 4 6502 ;absolute indexed y 104: ORA (aa,X) OR A,((aa+X)) 01H 04H 2 6 6502 ; indexed indirect x 105: ORA (aa),Y OR A,((aa)+Y) 11H 0CH 2 5 6502 ; indirect indexed y 106: PHA PUSH A 48H 42H 1 3 cpu3 ; implied 107: PHP PUSH F 08H 40H 1 3 cpu3 ; implied 108: PLA POP A 68H 52H 1 4 cpu3 ; implied 109: PLP POP F 28H 50H 1 4 cpu3 ; implied 110: ROL A ROL A 2AH D0H 1 2 cpu3 ; accumulator 111: ROL aa ROL (aa) 26H 91H 2 5 cpu3 ; zero page 112: ROL aa,X ROL (aa+X) 36H 99H 2 6 6502 ;zero page indexed x 113: ROL aaaa ROL (aaaa) 2EH D1H 3 6 6502 ; absolute 114: ROL aaaa,X ROL (aaaa+X) 3EH D9H 3 7 6502 ;absolute indexed x 115: ROR A ROR A 6AH D2H 1 2 cpu3 ; accumulator 116: ROR aa ROR (aa) 66H 93H 2 5 cpu3 ; zero page 117: ROR aa,X ROR (aa+X) 76H 9BH 2 6 6502 ;zero page indexed x 118: ROR aaaa ROR (aaaa) 6EH D3H 3 6 6502 ; absolute 119: ROR aaaa,X ROR (aaaa+X) 7EH DBH 3 7 6502 ;absolute indexed x 120: RTI RETI 40H 02H 1 6 cpu3 ; implied 121: RTS RET 60H 12H 1 6 cpu3 ; implied 122: SBC #dd SBC A,dd E9H 76H 2 2 cpu3 ; immediate 123: SBC aa SBC A,(aa) E5H 37H 2 3 cpu3 ; zero page 124: SBC aa,X SBC A,(aa+X) F5H 3FH 2 4 6502 ;zero page indexed x 125: SBC aaaa SBC A,(aaaa) EDH 77H 3 4 6502 ; absolute 126: SBC aaaa,X SBC A,(aaaa+X) FDH 7FH 3 4 6502 ;absolute indexed x 127: SBC aaaa,Y SBC A,(aaaa+Y) F9H 7EH 3 4 6502 ;absolute indexed y 128: SBC (aa,X) SBC A,((aa+X)) E1H 36H 2 6 6502 ; indexed indirect x 129: SBC (aa),Y SBC A,((aa)+Y) F1H 3EH 2 5 6502 ; indirect indexed y 130: SEC SCF 38H 58H 1 2 cpu3 ; implied 131: SED SDF F8H 7AH 1 2 6502 ; implied 132: SEI DI 78H 5AH 1 2 cpu3 ; implied 133: STA aa LD (aa),A 85H 25H 2 3 cpu3 ; zero page 134: STA aa,X LD (aa+X),A 95H 2DH 2 4 cpu3 ;zero page indexed x 135: STA aaaa LD (aaaa),A 8DH 65H 3 4 6502 ; absolute 136: STA aaaa,X LD (aaaa+X),A 9DH 6DH 3 5 6502 ;absolute indexed x 137: STA aaaa,Y LD (aaaa+Y),A 99H 6CH 3 5 6502 ;absolute indexed y 138: STA (aa,X) LD ((aa+X)),A 81H 24H 2 6 cpu3 ; indexed indirect x 139: STA (aa),Y LD ((aa)+Y),A 91H 2CH 2 6 6502 ; indirect indexed y 140: STX aa LD (aa),X 86H A1H 2 3 cpu3 ; zero page 141: STX aa,Y LD (aa+Y),X 96H A9H 2 4 6502 ;zero page indexed y 142: STX aaaa LD (aaaa),X 8EH E1H 3 4 cpu3 ; absolute 143: STY aa LD (aa),Y 84H 21H 2 3 6502 ; zero page 144: STY aa,X LD (aa+X),Y 94H 29H 2 4 6502 ;zero page indexed x 145: STY aaaa LD (aaaa),Y 8CH 61H 3 4 6502 ; absolute 146: TAX LD X,A AAH F0H 1 2 cpu5 ; implied 147: TAY LD Y,A A8H 70H 1 2 6502 ; implied 148: TSX LD X,SP BAH F8H 1 2 cpu3 ; implied 149: TXA LD A,X 8AH E0H 1 2 cpu5 ; implied 150: TXS LD SP,X 9AH E8H 1 2 cpu3 ; implied 151: TYA LD A,Y 98H 68H 1 2 6502 ; implied ================================================ FILE: disassembler/bytecoder.txt ================================================ NO: SYNTAX 6502: SYNTAX 2500: 6502 SUN b c type addressing modes 001: ADC #dd ADC A,dd 69H 56H 2 2 cpu3 ; immediate 002: ADC aa ADC A,(aa) 65H 17H 2 3 cpu3 ; zero page 003: AND #dd AND A,dd 29H 54H 2 2 cpu3 ; immediate 004: AND aa AND A,(aa) 25H 15H 2 3 cpu3 ; zero page 005: BCC ?? JR NC,?? 90H 28H 2 2 cpu3 ; relative 006: BCS ?? JR C,?? B0H 38H 2 2 cpu3 ; relative 007: BEQ ?? JR Z,?? F0H 3AH 2 2 cpu3 ; relative 008: BIT aa BIT (aa) 24H 11H 2 3 cpu5 ; zero page 009: BIT aaaa BIT (aaaa) 2CH 51H 3 4 cpu5 ; absolute 010: BMI ?? JR M,?? 30H 18H 2 2 cpu3 ; relative 011: BNE ?? JR NZ,?? D0H 2AH 2 2 cpu3 ; relative 012: BPL ?? JR P,?? 10H 08H 2 2 cpu3 ; relative 013: BRK BRK 00H 00H 1 7 cpu3 ; implied 014: BVC ?? JR NOV,?? 50H 0AH 2 2 cpu3 ; relative 015: BVS ?? JR OV,?? 70H 1AH 2 2 cpu3 ; relative 016: CLC CCF 18H 48H 1 2 cpu3 ; implied 017: CLI EI 58H 4AH 1 2 cpu3 ; implied 018: CLV CVF B8H 78H 1 2 cpu3 ; implied 019: CMP #dd CP A,dd C9H 66H 2 2 cpu3 ; immediate 020: CMP aa CP A,(aa) C5H 27H 2 3 cpu3 ; zero page 021: CMP aa,X CP A,(aa+X) D5H 2FH 2 4 cpu3 ;zero page indexed x 022: CPX #dd CP X,dd E0H 32H 2 2 cpu3 ; immediate 023: CPX aa CP X,(aa) E4H 33H 2 3 cpu3 ; zero page 024: DEC aa DEC (aa) C6H A3H 2 5 cpu3 ; zero page 025: DEC aa,X DEC (aa+X) D6H ABH 2 6 cpu5 ;zero page indexed x 026: DEX DEC X CAH E2H 1 2 cpu3 ; implied 027: EOR #dd XOR A,dd 49H 46H 2 2 cpu3 ; immediate 028: EOR aa XOR A,(aa) 45H 07H 2 3 cpu3 ; zero page 029: EOR aa,X XOR A,(aa+X) 55H 0FH 2 4 cpu5 ;zero page indexed x 030: INC aa INC (aa) E6H B3H 2 5 cpu3 ; zero page 031: INX INC X E8H 72H 1 2 cpu3 ; implied 032: JMP aaaa JP aaaa 4CH 43H 3 3 cpu3 ; absolute 033: JMP (aaaa) JP (aaaa) 6CH 53H 3 5 cpu3 ; indirect absolut 034: JSR aaaa CALL aaaa 20H 10H 3 6 cpu3 ; absolute 035: LDA #dd LD A,dd A9H 74H 2 2 cpu3 ; immediate 036: LDA aa LD A,(aa) A5H 35H 2 3 cpu3 ; zero page 037: LDA aa,X LD A,(aa+X) B5H 3DH 2 4 cpu3 ;zero page indexed x 038: LDA aaaa LD A,(aaaa) ADH 75H 3 4 cpu3 ; absolute 039: LDA aaaa,X LD A,(aaaa+X) BDH 7DH 3 4 cpu3 ;absolute indexed x 040: LDA (aa,X) LD A,((aa+X)) A1H 34H 2 6 cpu3 ; indexed indirect x 041: LDX #dd LD X,dd A2H B0H 2 2 cpu3 ; immediate 042: LDX aa LD X,(aa) A6H B1H 2 3 cpu3 ; zero page 043: LDX aaaa LD X,(aaaa) AEH F1H 3 4 cpu5 ; absolute 044: NOP NOP EAH F2H 1 2 cpu3 ; implied 045: ORA #dd OR A,dd 09H 44H 2 2 cpu3 ; immediate 046: ORA aa OR A,(aa) 05H 05H 2 3 cpu3 ; zero page 047: PHA PUSH A 48H 42H 1 3 cpu3 ; implied 048: PHP PUSH F 08H 40H 1 3 cpu3 ; implied 049: PLA POP A 68H 52H 1 4 cpu3 ; implied 050: PLP POP F 28H 50H 1 4 cpu3 ; implied 051: ROL A ROL A 2AH D0H 1 2 cpu3 ; accumulator 052: ROL aa ROL (aa) 26H 91H 2 5 cpu3 ; zero page 053: ROR A ROR A 6AH D2H 1 2 cpu3 ; accumulator 054: ROR aa ROR (aa) 66H 93H 2 5 cpu3 ; zero page 055: RTI RETI 40H 02H 1 6 cpu3 ; implied 056: RTS RET 60H 12H 1 6 cpu3 ; implied 057: SBC #dd SBC A,dd E9H 76H 2 2 cpu3 ; immediate 058: SBC aa SBC A,(aa) E5H 37H 2 3 cpu3 ; zero page 059: SEC SCF 38H 58H 1 2 cpu3 ; implied 060: SEI DI 78H 5AH 1 2 cpu3 ; implied 061: STA aa LD (aa),A 85H 25H 2 3 cpu3 ; zero page 062: STA aa,X LD (aa+X),A 95H 2DH 2 4 cpu3 ;zero page indexed x 063: STA (aa,X) LD ((aa+X)),A 81H 24H 2 6 cpu3 ; indexed indirect x 064: STX aa LD (aa),X 86H A1H 2 3 cpu3 ; zero page 065: STX aaaa LD (aaaa),X 8EH E1H 3 4 cpu3 ; absolute 066: TAX LD X,A AAH F0H 1 2 cpu5 ; implied 067: TSX LD X,SP BAH F8H 1 2 cpu3 ; implied 068: TXA LD A,X 8AH E0H 1 2 cpu5 ; implied 069: TXS LD SP,X 9AH E8H 1 2 cpu3 ; implied ================================================ FILE: disassembler/bytecodes.txt ================================================ NO: SYNTAX 6502: SYNTAX 2500: 6502 SUN b c type addressing modes 001: ADC #dd ADC A,dd 69H 56H 2 2 cpu3 ; immediate 002: ADC aa ADC A,(aa) 65H 17H 2 3 cpu3 ; zero page 003: AND #dd AND A,dd 29H 54H 2 2 cpu3 ; immediate 004: AND aa AND A,(aa) 25H 15H 2 3 cpu3 ; zero page 005: BCC ?? JR NC,?? 90H 28H 2 2 cpu3 ; relative 006: BCS ?? JR C,?? B0H 38H 2 2 cpu3 ; relative 007: BEQ ?? JR Z,?? F0H 3AH 2 2 cpu3 ; relative 008: BMI ?? JR M,?? 30H 18H 2 2 cpu3 ; relative 009: BNE ?? JR NZ,?? D0H 2AH 2 2 cpu3 ; relative 010: BPL ?? JR P,?? 10H 08H 2 2 cpu3 ; relative 011: BRK BRK 00H 00H 1 7 cpu3 ; implied 012: BVC ?? JR NOV,?? 50H 0AH 2 2 cpu3 ; relative 013: BVS ?? JR OV,?? 70H 1AH 2 2 cpu3 ; relative 014: CLC CCF 18H 48H 1 2 cpu3 ; implied 015: CLI EI 58H 4AH 1 2 cpu3 ; implied 016: CLV CVF B8H 78H 1 2 cpu3 ; implied 017: CMP #dd CP A,dd C9H 66H 2 2 cpu3 ; immediate 018: CMP aa CP A,(aa) C5H 27H 2 3 cpu3 ; zero page 019: CMP aa,X CP A,(aa+X) D5H 2FH 2 4 cpu3 ;zero page indexed x 020: CPX #dd CP X,dd E0H 32H 2 2 cpu3 ; immediate 021: CPX aa CP X,(aa) E4H 33H 2 3 cpu3 ; zero page 022: DEC aa DEC (aa) C6H A3H 2 5 cpu3 ; zero page 023: DEX DEC X CAH E2H 1 2 cpu3 ; implied 024: EOR #dd XOR A,dd 49H 46H 2 2 cpu3 ; immediate 025: EOR aa XOR A,(aa) 45H 07H 2 3 cpu3 ; zero page 026: INC aa INC (aa) E6H B3H 2 5 cpu3 ; zero page 027: INX INC X E8H 72H 1 2 cpu3 ; implied 028: JMP aaaa JP aaaa 4CH 43H 3 3 cpu3 ; absolute 029: JMP (aaaa) JP (aaaa) 6CH 53H 3 5 cpu3 ; indirect absolut 030: JSR aaaa CALL aaaa 20H 10H 3 6 cpu3 ; absolute 031: LDA #dd LD A,dd A9H 74H 2 2 cpu3 ; immediate 032: LDA aa LD A,(aa) A5H 35H 2 3 cpu3 ; zero page 033: LDA aa,X LD A,(aa+X) B5H 3DH 2 4 cpu3 ;zero page indexed x 034: LDA aaaa LD A,(aaaa) ADH 75H 3 4 cpu3 ; absolute 035: LDA aaaa,X LD A,(aaaa+X) BDH 7DH 3 4 cpu3 ;absolute indexed x 036: LDA (aa,X) LD A,((aa+X)) A1H 34H 2 6 cpu3 ; indexed indirect x 037: LDX #dd LD X,dd A2H B0H 2 2 cpu3 ; immediate 038: LDX aa LD X,(aa) A6H B1H 2 3 cpu3 ; zero page 039: NOP NOP EAH F2H 1 2 cpu3 ; implied 040: ORA #dd OR A,dd 09H 44H 2 2 cpu3 ; immediate 041: ORA aa OR A,(aa) 05H 05H 2 3 cpu3 ; zero page 042: PHA PUSH A 48H 42H 1 3 cpu3 ; implied 043: PHP PUSH F 08H 40H 1 3 cpu3 ; implied 044: PLA POP A 68H 52H 1 4 cpu3 ; implied 045: PLP POP F 28H 50H 1 4 cpu3 ; implied 046: ROL A ROL A 2AH D0H 1 2 cpu3 ; accumulator 047: ROL aa ROL (aa) 26H 91H 2 5 cpu3 ; zero page 048: ROR A ROR A 6AH D2H 1 2 cpu3 ; accumulator 049: ROR aa ROR (aa) 66H 93H 2 5 cpu3 ; zero page 050: RTI RETI 40H 02H 1 6 cpu3 ; implied 051: RTS RET 60H 12H 1 6 cpu3 ; implied 052: SBC #dd SBC A,dd E9H 76H 2 2 cpu3 ; immediate 053: SBC aa SBC A,(aa) E5H 37H 2 3 cpu3 ; zero page 054: SEC SCF 38H 58H 1 2 cpu3 ; implied 055: SEI DI 78H 5AH 1 2 cpu3 ; implied 056: STA aa LD (aa),A 85H 25H 2 3 cpu3 ; zero page 057: STA aa,X LD (aa+X),A 95H 2DH 2 4 cpu3 ;zero page indexed x 058: STA (aa,X) LD ((aa+X)),A 81H 24H 2 6 cpu3 ; indexed indirect x 059: STX aa LD (aa),X 86H A1H 2 3 cpu3 ; zero page 060: STX aaaa LD (aaaa),X 8EH E1H 3 4 cpu3 ; absolute 061: TSX LD X,SP BAH F8H 1 2 cpu3 ; implied 062: TXS LD SP,X 9AH E8H 1 2 cpu3 ; implied ================================================ FILE: disassembler/dissa.py ================================================ a = open("bytecoden.txt") f = a.read() f = f[f.find("001:"):] t = f.split() ops = [] o6502 = [] osun = [] b = [] index = 0 for item in t: if (len(item) ==3) and (item[2] == 'H') and (index != 2): o6502.append(int(item[:2], 16)) index = 2 elif (index == 1): ops.append(item) index = 57 elif (index == 2): osun.append(int(item[:2], 16)) #print "added sun" index = 3 elif (index == 3): b.append(int(item)) index = 4 #print "added b" elif (item.find(':') != -1): index = 1 #print len(osun) #print len(b) c = open("testbinary.bin", 'rb') code = c.read() osun.pop(ops.index("BRK")) b.pop(ops.index("BRK")) o6502.pop(ops.index("BRK")) ops.pop(ops.index("BRK")) #osun = o6502 #comment out for standard i = 0 while(i < len(code)): if (osun.count(ord(code[i])) != 0): run = 1 #print "inner " + str(i) ind = b[osun.index(ord(code[i]))] while osun.count(ord(code[i+ ind])) != 0: run = run + 1 ind = ind + b[osun.index(ord(code[i + ind]))] if( run > 25): print "assembly found, size " + str(run) + " index " + str(i) y = 0 for x in range(0, run): print ops[osun.index(ord(code[i + y]))], print "(" + str(osun[osun.index(ord(code[i + y]))]) + ")", #print b[osun.index(ord(code[i + y]))] for z in range(1, b[osun.index(ord(code[i + y]))]): print str(ord(code[i + y + z])), y = y + b[osun.index(ord(code[i + y]))] print " " i = i + run i = i + 1 print b print o6502 print osun ================================================ FILE: figure/Arduino/ClientSide/README.txt ================================================ ser.py -- ROM/Flash dump client serw.py -- Flash write client ================================================ FILE: figure/Arduino/ClientSide/ser.py ================================================ import serial import time #enter your device file arddev = 'COM5' baud = 9600 #setup - if a Serial object can't be created, a SerialException will be raised. while True: try: ser = serial.Serial(arddev, baud) #break out of while loop when connection is made break except serial.SerialException: print 'waiting for device ' + arddev + ' to be available' time.sleep(3) #read lines from serial device f = open("dump.txt", 'wb') while True: element = ser.read() f.write(element) f.flush() ================================================ FILE: figure/Arduino/ClientSide/serw.py ================================================ import serial import time #enter your device file arddev = 'COM5' baud = 115200 #setup - if a Serial object can't be created, a SerialException will be raised. while True: try: ser = serial.Serial(arddev, baud) #break out of while loop when connection is made break except serial.SerialException: print 'waiting for device ' + arddev + ' to be available' time.sleep(3) #read lines from serial device f = open("in.txt", 'rb') b = f.read() a = 0; while True: print ser.readline(); #ser.write(chr((a & 0xff0000) >> 16)) #ser.write(chr((a & 0xff00) >> 8)) #ser.write(chr(a & 0xff)) #ser.write('\x00'); #ser.write('\x00'); #ser.write('\x00'); for i in range(0, 256): print str(ord(b[a +i])) ser.write(str(ord(b[a +i])) + "\n") a = a + 256 #for i in range(0, 4): # print ser.readline() print "address", print a ================================================ FILE: figure/Arduino/GeneralPlusRomDump/GeneralPlusRomDump.ino ================================================ #define DATAOUT 11//MOSI #define DATAIN 12//MISO #define SPICLOCK 13//sck #define SLAVESELECT 10//ss //opcodes #define WREN 6 #define WRDI 4 #define RDSR 5 #define WRSR 1 #define READ 3 #define WRITE 2 byte eeprom_output_data; byte eeprom_input_data=0; byte clr; int address=0; int once = 0; //data buffer char buffer [128]; void fill_buffer() { for (int I=0;I<128;I++) { buffer[I]=I; } } char spi_transfer(volatile char data) { SPDR = data; // Start the transmission while (!(SPSR & (1<>8)); //send MSByte address first // spi_transfer((char)(EEPROM_address)); //send LSByte address for(j = 0; j < 0x80000; j++){ // data1 = spi_transfer(0x00); //data = spi_transfer(0x00); //get data byte //data2 = spi_transfer(0x00); //get data byte //data = spi_transfer(0xFF); // if( j%16 == 0){ // Serial.print("\n"); // Serial.print(j, HEX); // Serial.print( ": "); //} // delay(50); data = spi_transfer(0x00); //Serial.print("0x"); Serial.print((char)data); //Serial.print(" "); } digitalWrite(SLAVESELECT,HIGH); //release chip, signal end transfer // Serial.print(data,HEX); // Serial.print(" ");k // Serial.print(data2,HEX); // Serial.print(" "); // Serial.print(data1,HEX); // Serial.print(" \r\n"); Serial.print(" \n DONE"); return data; } void loop() { // Serial.print("loop 1\r\n"); if(once == 0) eeprom_output_data = read_eeprom(address); once = 100; // Serial.print("loop 2\r\n"); // Serial.print(eeprom_output_data,DEC); //Serial.print('\n',BYTE); //address++; //if (address == 128) //address = 0; delay(500); //pause for readability // digitalWrite(SPICLOCK, HIGH); // digitalWrite(DATAOUT, HIGH); } ================================================ FILE: figure/Arduino/GeneralPlusRomWrite/GeneralPlusRomWrite.ino ================================================ #define DATAOUT 11//MOSI #define DATAIN 12//MISO #define SPICLOCK 13//sck #define SLAVESELECT 10//ss //opcodes #define WREN 6 #define WRDI 4 #define RDSR 5 #define WRSR 1 #define READ 3 #define WRITE 2 byte eeprom_output_data; byte eeprom_input_data=0; byte clr; int address=0; long int once = 0; //data buffer char buffer [128]; void fill_buffer() { for (int I=0;I<128;I++) { buffer[I]=I; } } char spi_transfer(volatile char data) { SPDR = data; // Start the transmission while (!(SPSR & (1<>8)); //send MSByte address first // spi_transfer((char)(EEPROM_address)); //send LSByte address for(j = 0; j < 0x80000; j++){ // data1 = spi_transfer(0x00); //data = spi_transfer(0x00); //get data byte //data2 = spi_transfer(0x00); //get data byte //data = spi_transfer(0xFF); // if( j%16 == 0){ // Serial.print("\n"); // Serial.print(j, HEX); // Serial.print( ": "); //} // delay(50); data = spi_transfer(0x00); //Serial.print("0x"); Serial.print((char)data); //Serial.print(" "); } digitalWrite(SLAVESELECT,HIGH); //release chip, signal end transfer // Serial.print(data,HEX); // Serial.print(" ");k // Serial.print(data2,HEX); // Serial.print(" "); // Serial.print(data1,HEX); // Serial.print(" \r\n"); // Serial.print(" \n DONE"); return data; } void loop() { long int i; byte b[256]; Serial.println("ready"); for(i = 0; i < 256; i++){ b[i] = Serial.parseInt(); } // Serial.print("loop 1\r\n"); if((once %256) == 0){ // eeprom_output_data = read_eeprom(address); digitalWrite(SLAVESELECT,LOW); spi_transfer(0x06); //transmit read opcode digitalWrite(SLAVESELECT,HIGH); digitalWrite(SLAVESELECT,LOW); spi_transfer(0xd8); spi_transfer(once / 256); spi_transfer(0x00); spi_transfer(0x00); digitalWrite(SLAVESELECT,HIGH); delay(1000); } digitalWrite(SLAVESELECT,LOW); spi_transfer(0x06); //transmit read opcode digitalWrite(SLAVESELECT,HIGH); digitalWrite(SLAVESELECT,LOW); spi_transfer(0x2); spi_transfer(once / 256); spi_transfer(once % 256); spi_transfer(0); for(i = 0; i < 256; i++){ spi_transfer(b[i]); } digitalWrite(SLAVESELECT,HIGH); once++; // once = 100; // Serial.print("loop 2\r\n"); // Serial.print(eeprom_output_data,DEC); //Serial.print('\n',BYTE); //address++; //if (address == 128) //address = 0; // delay(500); //pause for readability // digitalWrite(SPICLOCK, HIGH); // digitalWrite(DATAOUT, HIGH); } ================================================ FILE: figure/Arduino/README.txt ================================================ GeneralPlusRomDump.pde -- Dumps a GeneralPlus Low Power SPI ROM GeneralPlusRomWrite.pde -- Dumps GeneralPlus SPI Flash ClientSide -- Client side scripts for dumps or writes ================================================ FILE: figure/README ================================================ Figure code /Arduino -- Arduino code to dump and write memory /ROMDump -- Actual ROM dumps /scripts -- Misc scripts /SignalPulls -- Code to determine when a figure is read ================================================ FILE: figure/ROMDump/README ================================================ ROM dumps /imgs/ - images extracted from the Memetchi figure dump /makikoimgs/ - images extracted from a Makiko figure dump - adds.txt contains addresses of images in figure dump /ROMDump - Memetchi figure dump /maikio - Makiko figure dump ================================================ FILE: figure/ROMDump/imgs/adds.txt ================================================ 20 20 img 0 at 2884 20 20 img 1 at 2986 20 20 img 2 at 3088 20 20 img 3 at 3190 20 20 img 4 at 3292 20 20 img 5 at 3394 20 20 img 6 at 3496 20 20 img 7 at 3598 20 20 img 8 at 3700 20 20 img 9 at 3802 20 20 img 10 at 3904 20 20 img 11 at 4006 20 20 img 12 at 4108 20 20 img 13 at 4210 20 20 img 14 at 4312 20 20 img 15 at 4414 20 20 img 16 at 4516 20 20 img 17 at 4618 20 20 img 18 at 4720 20 20 img 19 at 4822 20 20 img 20 at 4924 20 20 img 21 at 5026 20 20 img 22 at 5128 20 20 img 23 at 5230 20 20 img 24 at 5332 20 20 img 25 at 5434 48 31 Padded to 48 by 31 img 26 at 5808 48 31 Padded to 48 by 31 img 27 at 6182 48 31 Padded to 48 by 31 img 28 at 6556 48 31 Padded to 48 by 31 img 29 at 6930 48 31 Padded to 48 by 31 img 30 at 7304 48 31 Padded to 48 by 31 img 31 at 7678 48 31 Padded to 48 by 31 img 32 at 8052 48 31 Padded to 48 by 31 img 33 at 8426 48 13 Padded to 48 by 13 img 34 at 8584 48 13 Padded to 48 by 13 img 35 at 8742 28 31 Padded to 28 by 31 img 36 at 8961 18 12 img 37 at 9023 18 12 img 38 at 9085 18 12 img 39 at 9147 18 12 img 40 at 9209 18 12 img 41 at 9271 17 21 Padded to 20 by 21 img 42 at 9378 17 21 Padded to 20 by 21 img 43 at 9485 32 8 img 44 at 9551 32 8 img 45 at 9617 32 8 img 46 at 9683 32 8 img 47 at 9749 32 8 img 48 at 9815 32 8 img 49 at 9881 8 8 img 50 at 9899 8 8 img 51 at 9917 8 8 img 52 at 9935 8 8 img 53 at 9953 8 8 img 54 at 9971 1 1 Padded to 4 by 1 img 55 at 9974 12 12 img 56 at 10012 12 12 img 57 at 10050 12 12 img 58 at 10088 12 12 img 59 at 10126 12 12 img 60 at 10164 12 12 img 61 at 10202 12 12 img 62 at 10240 12 12 img 63 at 10278 12 12 img 64 at 10316 12 12 img 65 at 10354 48 31 Padded to 48 by 31 img 66 at 10728 1 1 Padded to 4 by 1 img 67 at 10731 16 16 img 68 at 10797 16 16 img 69 at 10863 16 16 img 70 at 10929 16 16 img 71 at 10995 16 16 img 72 at 11061 16 16 img 73 at 11127 16 16 img 74 at 11193 16 16 img 75 at 11259 16 16 img 76 at 11325 16 16 img 77 at 11391 30 12 img 78 at 11489 30 12 img 79 at 11587 30 12 img 80 at 11685 30 12 img 81 at 11783 30 12 img 82 at 11881 30 12 img 83 at 11979 30 12 img 84 at 12077 30 12 img 85 at 12175 30 12 img 86 at 12273 30 12 img 87 at 12371 17 25 Padded to 20 by 25 img 88 at 12498 20 19 Padded to 20 by 19 img 89 at 12595 20 19 Padded to 20 by 19 img 90 at 12692 20 19 Padded to 20 by 19 img 91 at 12789 20 19 Padded to 20 by 19 img 92 at 12886 20 19 Padded to 20 by 19 img 93 at 12983 19 18 Padded to 20 by 18 img 94 at 13075 20 18 Padded to 20 by 18 img 95 at 13167 20 18 Padded to 20 by 18 img 96 at 13259 7 31 Padded to 8 by 31 img 97 at 13323 31 17 Padded to 32 by 17 img 98 at 13461 48 31 Padded to 48 by 31 img 99 at 13835 48 31 Padded to 48 by 31 img 100 at 14209 48 31 Padded to 48 by 31 img 101 at 14583 48 31 Padded to 48 by 31 img 102 at 14957 48 22 Padded to 48 by 22 img 103 at 15223 48 31 Padded to 48 by 31 img 104 at 15597 48 31 Padded to 48 by 31 img 105 at 15971 48 31 Padded to 48 by 31 img 106 at 16345 48 31 Padded to 48 by 31 img 107 at 16719 48 15 Padded to 48 by 15 img 108 at 16901 48 15 Padded to 48 by 15 img 109 at 17083 48 31 Padded to 48 by 31 img 110 at 17457 48 31 Padded to 48 by 31 img 111 at 17831 48 3 Padded to 48 by 3 img 112 at 17869 25 24 img 113 at 18039 48 6 Padded to 48 by 6 img 114 at 18113 48 31 Padded to 48 by 31 img 115 at 18487 48 31 Padded to 48 by 31 img 116 at 18861 48 31 Padded to 48 by 31 img 117 at 19235 48 31 Padded to 48 by 31 img 118 at 19609 48 31 Padded to 48 by 31 img 119 at 19983 48 31 Padded to 48 by 31 img 120 at 20357 6 7 Padded to 8 by 7 img 121 at 20373 7 31 Padded to 8 by 31 img 122 at 20437 32 31 Padded to 32 by 31 img 123 at 20687 48 31 Padded to 48 by 31 img 124 at 21061 48 31 Padded to 48 by 31 img 125 at 21435 48 31 Padded to 48 by 31 img 126 at 21809 48 31 Padded to 48 by 31 img 127 at 22183 48 31 Padded to 48 by 31 img 128 at 22557 48 31 Padded to 48 by 31 img 129 at 22931 48 31 Padded to 48 by 31 img 130 at 23305 48 31 Padded to 48 by 31 img 131 at 23679 48 31 Padded to 48 by 31 img 132 at 24053 48 31 Padded to 48 by 31 img 133 at 24427 48 31 Padded to 48 by 31 img 134 at 24801 48 31 Padded to 48 by 31 img 135 at 25175 48 31 Padded to 48 by 31 img 136 at 25549 48 31 Padded to 48 by 31 img 137 at 25923 48 31 Padded to 48 by 31 img 138 at 26297 48 31 Padded to 48 by 31 img 139 at 26671 48 31 Padded to 48 by 31 img 140 at 27045 48 31 Padded to 48 by 31 img 141 at 27419 48 31 Padded to 48 by 31 img 142 at 27793 48 31 Padded to 48 by 31 img 143 at 28167 7 31 Padded to 8 by 31 img 144 at 28231 32 29 Padded to 32 by 29 img 145 at 28465 32 29 Padded to 32 by 29 img 146 at 28699 48 31 Padded to 48 by 31 img 147 at 29073 48 31 Padded to 48 by 31 img 148 at 29447 48 31 Padded to 48 by 31 img 149 at 29821 48 31 Padded to 48 by 31 img 150 at 30195 48 31 Padded to 48 by 31 img 151 at 30569 48 31 Padded to 48 by 31 img 152 at 30943 48 31 Padded to 48 by 31 img 153 at 31317 48 31 Padded to 48 by 31 img 154 at 31691 48 31 Padded to 48 by 31 img 155 at 32065 48 8 img 156 at 32163 48 22 Padded to 48 by 22 img 157 at 32429 48 22 Padded to 48 by 22 img 158 at 32695 48 22 Padded to 48 by 22 img 159 at 32961 48 22 Padded to 48 by 22 img 160 at 33227 48 7 Padded to 48 by 7 img 161 at 33313 48 7 Padded to 48 by 7 img 162 at 33399 48 31 Padded to 48 by 31 img 163 at 33773 48 31 Padded to 48 by 31 img 164 at 34147 20 6 Padded to 20 by 6 img 165 at 34179 48 31 Padded to 48 by 31 img 166 at 34553 35 26 Padded to 36 by 26 img 167 at 34789 35 26 Padded to 36 by 26 img 168 at 35025 16 15 Padded to 16 by 15 img 169 at 35087 16 15 Padded to 16 by 15 img 170 at 35149 16 15 Padded to 16 by 15 img 171 at 35211 16 15 Padded to 16 by 15 img 172 at 35273 16 15 Padded to 16 by 15 img 173 at 35335 16 15 Padded to 16 by 15 img 174 at 35397 16 15 Padded to 16 by 15 img 175 at 35459 16 15 Padded to 16 by 15 img 176 at 35521 16 15 Padded to 16 by 15 img 177 at 35583 16 15 Padded to 16 by 15 img 178 at 35645 16 15 Padded to 16 by 15 img 179 at 35707 16 15 Padded to 16 by 15 img 180 at 35769 16 15 Padded to 16 by 15 img 181 at 35831 16 15 Padded to 16 by 15 img 182 at 35893 16 15 Padded to 16 by 15 img 183 at 35955 16 15 Padded to 16 by 15 img 184 at 36017 16 15 Padded to 16 by 15 img 185 at 36079 16 15 Padded to 16 by 15 img 186 at 36141 16 15 Padded to 16 by 15 img 187 at 36203 16 15 Padded to 16 by 15 img 188 at 36265 16 15 Padded to 16 by 15 img 189 at 36327 16 15 Padded to 16 by 15 img 190 at 36389 16 15 Padded to 16 by 15 img 191 at 36451 16 15 Padded to 16 by 15 img 192 at 36513 16 15 Padded to 16 by 15 img 193 at 36575 16 15 Padded to 16 by 15 img 194 at 36637 16 15 Padded to 16 by 15 img 195 at 36699 16 15 Padded to 16 by 15 img 196 at 36761 16 15 Padded to 16 by 15 img 197 at 36823 16 15 Padded to 16 by 15 img 198 at 36885 16 15 Padded to 16 by 15 img 199 at 36947 16 15 Padded to 16 by 15 img 200 at 37009 16 15 Padded to 16 by 15 img 201 at 37071 16 15 Padded to 16 by 15 img 202 at 37133 16 15 Padded to 16 by 15 img 203 at 37195 16 15 Padded to 16 by 15 img 204 at 37257 24 31 Padded to 24 by 31 img 205 at 37445 24 15 Padded to 24 by 15 img 206 at 37537 16 19 Padded to 16 by 19 img 207 at 37615 30 31 Padded to 32 by 31 img 208 at 37865 30 31 Padded to 32 by 31 img 209 at 38115 30 31 Padded to 32 by 31 img 210 at 38365 30 31 Padded to 32 by 31 img 211 at 38615 30 31 Padded to 32 by 31 img 212 at 38865 4 7 Padded to 4 by 7 img 213 at 38874 4 7 Padded to 4 by 7 img 214 at 38883 4 7 Padded to 4 by 7 img 215 at 38892 4 7 Padded to 4 by 7 img 216 at 38901 48 31 Padded to 48 by 31 img 217 at 39275 48 31 Padded to 48 by 31 img 218 at 39649 19 7 Padded to 20 by 7 img 219 at 39686 13 7 Padded to 16 by 7 img 220 at 39716 13 7 Padded to 16 by 7 img 221 at 39746 19 7 Padded to 20 by 7 img 222 at 39783 48 31 Padded to 48 by 31 img 223 at 40157 4 4 img 224 at 40163 7 31 Padded to 8 by 31 img 225 at 40227 48 31 Padded to 48 by 31 img 226 at 40601 48 31 Padded to 48 by 31 img 227 at 40975 48 31 Padded to 48 by 31 img 228 at 41349 48 31 Padded to 48 by 31 img 229 at 41723 16 31 Padded to 16 by 31 img 230 at 41849 16 16 img 231 at 41915 16 16 img 232 at 41981 16 16 img 233 at 42047 16 16 img 234 at 42113 4 4 img 235 at 42119 4 4 img 236 at 42125 48 31 Padded to 48 by 31 img 237 at 42499 48 31 Padded to 48 by 31 img 238 at 42873 48 31 Padded to 48 by 31 img 239 at 43247 48 31 Padded to 48 by 31 img 240 at 43621 48 31 Padded to 48 by 31 img 241 at 43995 4 4 img 242 at 44001 4 4 img 243 at 44007 4 4 img 244 at 44013 48 31 Padded to 48 by 31 img 245 at 44387 48 31 Padded to 48 by 31 img 246 at 44761 48 8 img 247 at 44859 16 14 Padded to 16 by 14 img 248 at 44917 16 14 Padded to 16 by 14 img 249 at 44975 16 14 Padded to 16 by 14 img 250 at 45033 16 14 Padded to 16 by 14 img 251 at 45091 16 14 Padded to 16 by 14 img 252 at 45149 16 14 Padded to 16 by 14 img 253 at 45207 16 14 Padded to 16 by 14 img 254 at 45265 16 14 Padded to 16 by 14 img 255 at 45323 16 14 Padded to 16 by 14 img 256 at 45381 48 31 Padded to 48 by 31 img 257 at 45755 24 31 Padded to 24 by 31 img 258 at 45943 24 15 Padded to 24 by 15 img 259 at 46035 16 19 Padded to 16 by 19 img 260 at 46113 30 31 Padded to 32 by 31 img 261 at 46363 30 31 Padded to 32 by 31 img 262 at 46613 30 31 Padded to 32 by 31 img 263 at 46863 30 31 Padded to 32 by 31 img 264 at 47113 30 31 Padded to 32 by 31 img 265 at 47363 4 7 Padded to 4 by 7 img 266 at 47372 4 7 Padded to 4 by 7 img 267 at 47381 4 7 Padded to 4 by 7 img 268 at 47390 4 7 Padded to 4 by 7 img 269 at 47399 48 31 Padded to 48 by 31 img 270 at 47773 48 31 Padded to 48 by 31 img 271 at 48147 19 7 Padded to 20 by 7 img 272 at 48184 13 7 Padded to 16 by 7 img 273 at 48214 13 7 Padded to 16 by 7 img 274 at 48244 19 7 Padded to 20 by 7 img 275 at 48281 48 31 Padded to 48 by 31 img 276 at 48655 4 4 img 277 at 48661 7 31 Padded to 8 by 31 img 278 at 48725 48 31 Padded to 48 by 31 img 279 at 49099 48 31 Padded to 48 by 31 img 280 at 49473 48 31 Padded to 48 by 31 img 281 at 49847 48 31 Padded to 48 by 31 img 282 at 50221 48 31 Padded to 48 by 31 img 283 at 50595 48 31 Padded to 48 by 31 img 284 at 50969 48 31 Padded to 48 by 31 img 285 at 51343 16 16 img 286 at 51409 16 16 img 287 at 51475 16 16 img 288 at 51541 16 16 img 289 at 51607 48 31 Padded to 48 by 31 img 290 at 51981 48 31 Padded to 48 by 31 img 291 at 52355 48 31 Padded to 48 by 31 img 292 at 52729 48 31 Padded to 48 by 31 img 293 at 53103 48 31 Padded to 48 by 31 img 294 at 53477 4 4 img 295 at 53483 4 4 img 296 at 53489 4 4 img 297 at 53495 48 31 Padded to 48 by 31 img 298 at 53869 48 31 Padded to 48 by 31 img 299 at 54243 48 8 img 300 at 54341 16 14 Padded to 16 by 14 img 301 at 54399 16 14 Padded to 16 by 14 img 302 at 54457 16 14 Padded to 16 by 14 img 303 at 54515 16 14 Padded to 16 by 14 img 304 at 54573 16 14 Padded to 16 by 14 img 305 at 54631 16 14 Padded to 16 by 14 img 306 at 54689 16 14 Padded to 16 by 14 img 307 at 54747 16 14 Padded to 16 by 14 img 308 at 54805 16 14 Padded to 16 by 14 img 309 at 54863 48 31 Padded to 48 by 31 img 310 at 55237 24 31 Padded to 24 by 31 img 311 at 55425 24 15 Padded to 24 by 15 img 312 at 55517 16 19 Padded to 16 by 19 img 313 at 55595 30 31 Padded to 32 by 31 img 314 at 55845 30 31 Padded to 32 by 31 img 315 at 56095 30 31 Padded to 32 by 31 img 316 at 56345 30 31 Padded to 32 by 31 img 317 at 56595 30 31 Padded to 32 by 31 img 318 at 56845 4 7 Padded to 4 by 7 img 319 at 56854 4 7 Padded to 4 by 7 img 320 at 56863 4 7 Padded to 4 by 7 img 321 at 56872 4 7 Padded to 4 by 7 img 322 at 56881 48 31 Padded to 48 by 31 img 323 at 57255 48 31 Padded to 48 by 31 img 324 at 57629 19 7 Padded to 20 by 7 img 325 at 57666 13 7 Padded to 16 by 7 img 326 at 57696 13 7 Padded to 16 by 7 img 327 at 57726 19 7 Padded to 20 by 7 img 328 at 57763 48 31 Padded to 48 by 31 img 329 at 58137 4 4 img 330 at 58143 7 31 Padded to 8 by 31 img 331 at 58207 48 31 Padded to 48 by 31 img 332 at 58581 48 31 Padded to 48 by 31 img 333 at 58955 48 31 Padded to 48 by 31 img 334 at 59329 48 31 Padded to 48 by 31 img 335 at 59703 48 31 Padded to 48 by 31 img 336 at 60077 48 31 Padded to 48 by 31 img 337 at 60451 48 31 Padded to 48 by 31 img 338 at 60825 48 31 Padded to 48 by 31 img 339 at 61199 48 31 Padded to 48 by 31 img 340 at 61573 48 31 Padded to 48 by 31 img 341 at 61947 16 16 img 342 at 62013 16 16 img 343 at 62079 16 16 img 344 at 62145 16 16 img 345 at 62211 4 4 img 346 at 62217 4 4 img 347 at 62223 4 4 img 348 at 62229 4 4 img 349 at 62235 4 4 img 350 at 62241 48 31 Padded to 48 by 31 img 351 at 62615 48 31 Padded to 48 by 31 img 352 at 62989 48 8 img 353 at 63087 16 14 Padded to 16 by 14 img 354 at 63145 16 14 Padded to 16 by 14 img 355 at 63203 16 14 Padded to 16 by 14 img 356 at 63261 16 14 Padded to 16 by 14 img 357 at 63319 16 14 Padded to 16 by 14 img 358 at 63377 16 14 Padded to 16 by 14 img 359 at 63435 16 14 Padded to 16 by 14 img 360 at 63493 16 14 Padded to 16 by 14 img 361 at 63551 16 14 Padded to 16 by 14 img 362 at 63609 48 31 Padded to 48 by 31 img 363 at 63983 24 31 Padded to 24 by 31 img 364 at 64171 24 15 Padded to 24 by 15 img 365 at 64263 16 19 Padded to 16 by 19 img 366 at 64341 30 31 Padded to 32 by 31 img 367 at 64591 30 31 Padded to 32 by 31 img 368 at 64841 30 31 Padded to 32 by 31 img 369 at 65091 30 31 Padded to 32 by 31 img 370 at 65341 30 31 Padded to 32 by 31 img 371 at 65591 4 7 Padded to 4 by 7 img 372 at 65600 4 7 Padded to 4 by 7 img 373 at 65609 4 7 Padded to 4 by 7 img 374 at 65618 4 7 Padded to 4 by 7 img 375 at 65627 48 31 Padded to 48 by 31 img 376 at 66001 48 31 Padded to 48 by 31 img 377 at 66375 19 7 Padded to 20 by 7 img 378 at 66412 13 7 Padded to 16 by 7 img 379 at 66442 13 7 Padded to 16 by 7 img 380 at 66472 19 7 Padded to 20 by 7 img 381 at 66509 48 31 Padded to 48 by 31 img 382 at 66883 4 4 img 383 at 66889 7 31 Padded to 8 by 31 img 384 at 66953 48 31 Padded to 48 by 31 img 385 at 67327 48 31 Padded to 48 by 31 img 386 at 67701 48 31 Padded to 48 by 31 img 387 at 68075 48 31 Padded to 48 by 31 img 388 at 68449 48 31 Padded to 48 by 31 img 389 at 68823 48 31 Padded to 48 by 31 img 390 at 69197 48 31 Padded to 48 by 31 img 391 at 69571 48 31 Padded to 48 by 31 img 392 at 69945 48 31 Padded to 48 by 31 img 393 at 70319 26 15 Padded to 28 by 15 img 394 at 70426 24 12 img 395 at 70500 48 2 Padded to 48 by 2 img 396 at 70526 48 31 Padded to 48 by 31 img 397 at 70900 4 4 img 398 at 70906 4 4 img 399 at 70912 4 4 img 400 at 70918 4 4 img 401 at 70924 4 4 img 402 at 70930 4 4 img 403 at 70936 48 31 Padded to 48 by 31 img 404 at 71310 48 31 Padded to 48 by 31 img 405 at 71684 48 8 img 406 at 71782 16 14 Padded to 16 by 14 img 407 at 71840 16 14 Padded to 16 by 14 img 408 at 71898 16 14 Padded to 16 by 14 img 409 at 71956 16 14 Padded to 16 by 14 img 410 at 72014 16 14 Padded to 16 by 14 img 411 at 72072 16 14 Padded to 16 by 14 img 412 at 72130 16 14 Padded to 16 by 14 img 413 at 72188 16 14 Padded to 16 by 14 img 414 at 72246 16 14 Padded to 16 by 14 img 415 at 72304 48 31 Padded to 48 by 31 img 416 at 72678 14 13 Padded to 16 by 13 img 417 at 72732 14 13 Padded to 16 by 13 img 418 at 72786 14 13 Padded to 16 by 13 img 419 at 72840 14 13 Padded to 16 by 13 img 420 at 72894 14 13 Padded to 16 by 13 img 421 at 72948 14 13 Padded to 16 by 13 img 422 at 73002 14 13 Padded to 16 by 13 img 423 at 73056 14 13 Padded to 16 by 13 img 424 at 73110 14 13 Padded to 16 by 13 img 425 at 73164 14 13 Padded to 16 by 13 img 426 at 73218 14 13 Padded to 16 by 13 img 427 at 73272 14 13 Padded to 16 by 13 img 428 at 73326 14 13 Padded to 16 by 13 img 429 at 73380 14 13 Padded to 16 by 13 img 430 at 73434 14 13 Padded to 16 by 13 img 431 at 73488 14 13 Padded to 16 by 13 img 432 at 73542 14 13 Padded to 16 by 13 img 433 at 73596 14 13 Padded to 16 by 13 img 434 at 73650 14 13 Padded to 16 by 13 img 435 at 73704 14 13 Padded to 16 by 13 img 436 at 73758 14 13 Padded to 16 by 13 img 437 at 73812 14 13 Padded to 16 by 13 img 438 at 73866 14 13 Padded to 16 by 13 img 439 at 73920 14 13 Padded to 16 by 13 img 440 at 73974 14 13 Padded to 16 by 13 img 441 at 74028 14 13 Padded to 16 by 13 img 442 at 74082 14 13 Padded to 16 by 13 img 443 at 74136 14 13 Padded to 16 by 13 img 444 at 74190 14 13 Padded to 16 by 13 img 445 at 74244 14 13 Padded to 16 by 13 img 446 at 74298 14 13 Padded to 16 by 13 img 447 at 74352 14 13 Padded to 16 by 13 img 448 at 74406 14 13 Padded to 16 by 13 img 449 at 74460 14 13 Padded to 16 by 13 img 450 at 74514 14 13 Padded to 16 by 13 img 451 at 74568 14 13 Padded to 16 by 13 img 452 at 74622 14 13 Padded to 16 by 13 img 453 at 74676 14 13 Padded to 16 by 13 img 454 at 74730 14 13 Padded to 16 by 13 img 455 at 74784 14 13 Padded to 16 by 13 img 456 at 74838 14 13 Padded to 16 by 13 img 457 at 74892 14 13 Padded to 16 by 13 img 458 at 74946 14 13 Padded to 16 by 13 img 459 at 75000 14 13 Padded to 16 by 13 img 460 at 75054 32 17 Padded to 32 by 17 img 461 at 75192 32 17 Padded to 32 by 17 img 462 at 75330 48 31 Padded to 48 by 31 img 463 at 75704 48 31 Padded to 48 by 31 img 464 at 76078 45 27 Padded to 48 by 27 img 465 at 76404 45 27 Padded to 48 by 27 img 466 at 76730 30 25 Padded to 32 by 25 img 467 at 76932 30 25 Padded to 32 by 25 img 468 at 77134 48 31 Padded to 48 by 31 img 469 at 77508 48 31 Padded to 48 by 31 img 470 at 77882 48 31 Padded to 48 by 31 img 471 at 78256 48 31 Padded to 48 by 31 img 472 at 78630 14 11 Padded to 16 by 11 img 473 at 78676 48 31 Padded to 48 by 31 img 474 at 79050 48 31 Padded to 48 by 31 img 475 at 79424 7 31 Padded to 8 by 31 img 476 at 79488 22 16 img 477 at 79586 22 16 img 478 at 79684 7 31 Padded to 8 by 31 img 479 at 79748 48 7 Padded to 48 by 7 img 480 at 79834 48 6 Padded to 48 by 6 img 481 at 79908 48 6 Padded to 48 by 6 img 482 at 79982 9 8 img 483 at 80008 20 23 Padded to 20 by 23 img 484 at 80125 48 31 Padded to 48 by 31 img 485 at 80499 48 31 Padded to 48 by 31 img 486 at 80873 48 31 Padded to 48 by 31 img 487 at 81247 10 10 Padded to 12 by 10 img 488 at 81279 10 10 Padded to 12 by 10 img 489 at 81311 10 12 img 490 at 81349 10 12 img 491 at 81387 24 9 Padded to 24 by 9 img 492 at 81443 28 6 Padded to 28 by 6 img 493 at 81487 28 6 Padded to 28 by 6 img 494 at 81531 1 0 ================================================ FILE: figure/SignalPulls/README ================================================ Signal Pulls empire.txt -- Reads when doing USA tour (the NY tour version) signaldecode.py -- takes signal analyzer dump, and converts it to list of read addresses usatour.txt -- Reads when doing USA tour(Washington DC version) usatourbuy.txt -- Reads when buying USA tour ================================================ FILE: figure/SignalPulls/empire.txt ================================================ here Time [s],Packet ID,MOSI,MISO BREAK 1 2a8 2af2 2af4 2af8 2afc 2b00 2b04 2b08 2b0c 2b10 2b14 2b18 2b1c 2b20 2b24 2b28 2b2c 2b30 BREAK 1 2cc 2e06 2e08 2e10 2e18 2e20 2e28 2e30 2e38 2e40 2e48 2e50 2e58 2e60 BREAK 1 927 BREAK 1 d1 24a1 24a3 24a8 24ad 24b2 24b7 24bc 24c1 24c6 24cb 24d0 24d5 24da 24df 24e4 24e9 24ee 24f3 24f8 24fd 2502 2507 BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 162 92e 95b BREAK 1 24fc2 BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 24fc8 BREAK 1 4b5 9ce2 9ce4 9ce6 9ce8 9cea 9cec 9cee 9cf0 9cf2 9cf4 9cf6 9cf8 9cfa 9cfc 9cfe 9d00 9d02 9d04 9d06 9d08 9d0a 9d0c 9d0e 9d10 9d12 9d14 9d16 9d18 9d1a 9d1c 9d1e 9d20 BREAK 1 24fce BREAK 1 24fd4 BREAK 1 24fda BREAK 1 24fe0 BREAK 1 24fe6 BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 24fec BREAK 1 4b5 9ce2 9ce4 9ce6 9ce8 9cea 9cec 9cee 9cf0 9cf2 9cf4 9cf6 9cf8 9cfa 9cfc 9cfe 9d00 9d02 9d04 9d06 9d08 9d0a 9d0c 9d0e 9d10 9d12 9d14 9d16 9d18 9d1a 9d1c 9d1e 9d20 BREAK 1 24ff2 BREAK 1 24ff8 BREAK 1 24ffe BREAK 1 25004 BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 2500a BREAK 1 4b5 9ce2 9ce4 9ce6 9ce8 9cea 9cec 9cee 9cf0 9cf2 9cf4 9cf6 9cf8 9cfa 9cfc 9cfe 9d00 9d02 9d04 9d06 9d08 9d0a 9d0c 9d0e 9d10 9d12 9d14 9d16 9d18 9d1a 9d1c 9d1e 9d20 BREAK 1 25010 BREAK 1 25016 BREAK 1 2501c BREAK 1 25022 BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 25028 BREAK 1 4b5 9ce2 9ce4 9ce6 9ce8 9cea 9cec 9cee 9cf0 9cf2 9cf4 9cf6 9cf8 9cfa 9cfc 9cfe 9d00 9d02 9d04 9d06 9d08 9d0a 9d0c 9d0e 9d10 9d12 9d14 9d16 9d18 9d1a 9d1c 9d1e 9d20 BREAK 1 2502e BREAK 1 25034 BREAK 1 2503a BREAK 1 25040 BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 25046 BREAK 1 4b5 9ce2 9ce4 9ce6 9ce8 9cea 9cec 9cee 9cf0 9cf2 9cf4 9cf6 9cf8 9cfa 9cfc 9cfe 9d00 9d02 9d04 9d06 9d08 9d0a 9d0c 9d0e 9d10 9d12 9d14 9d16 9d18 9d1a 9d1c 9d1e 9d20 BREAK 1 2504c BREAK 1 25052 BREAK 1 25058 BREAK 1 2505e BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 25064 BREAK 1 4b5 9ce2 9ce4 9ce6 9ce8 9cea 9cec 9cee 9cf0 9cf2 9cf4 9cf6 9cf8 9cfa 9cfc 9cfe 9d00 9d02 9d04 9d06 9d08 9d0a 9d0c 9d0e 9d10 9d12 9d14 9d16 9d18 9d1a 9d1c 9d1e 9d20 BREAK 1 2506a BREAK 1 25070 BREAK 1 25076 BREAK 1 2507c BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 25082 BREAK 1 4b5 9ce2 9ce4 9ce6 9ce8 9cea 9cec 9cee 9cf0 9cf2 9cf4 9cf6 9cf8 9cfa 9cfc 9cfe 9d00 9d02 9d04 9d06 9d08 9d0a 9d0c 9d0e 9d10 9d12 9d14 9d16 9d18 9d1a 9d1c 9d1e 9d20 BREAK 1 25088 BREAK 1 2508e BREAK 1 25094 BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 2509a BREAK 1 4b5 9ce2 9ce4 9ce6 9ce8 9cea 9cec 9cee 9cf0 9cf2 9cf4 9cf6 9cf8 9cfa 9cfc 9cfe 9d00 9d02 9d04 9d06 9d08 9d0a 9d0c 9d0e 9d10 9d12 9d14 9d16 9d18 9d1a 9d1c 9d1e 9d20 BREAK 1 250a0 BREAK 1 250a6 BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 250ac BREAK 1 4b5 9ce2 9ce4 9ce6 9ce8 9cea 9cec 9cee 9cf0 9cf2 9cf4 9cf6 9cf8 9cfa 9cfc 9cfe 9d00 9d02 9d04 9d06 9d08 9d0a 9d0c 9d0e 9d10 9d12 9d14 9d16 9d18 9d1a 9d1c 9d1e 9d20 BREAK 1 250b2 BREAK 1 250b8 BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 250be BREAK 1 4b5 9ce2 9ce4 9ce6 9ce8 9cea 9cec 9cee 9cf0 9cf2 9cf4 9cf6 9cf8 9cfa 9cfc 9cfe 9d00 9d02 9d04 9d06 9d08 9d0a 9d0c 9d0e 9d10 9d12 9d14 9d16 9d18 9d1a 9d1c 9d1e 9d20 BREAK 1 250c4 BREAK 1 250ca BREAK 1 250d0 BREAK 1 4f1 abec abee abf6 abfa ac02 ac06 ac0e ac12 ac1a ac1e ac26 ac2a ac32 ac36 ac3e ac42 ac4a ac4e ac56 ac5a ac62 ac66 ac6e ac72 ac7a ac7e ac86 ac8a ac92 ac96 ac9e aca2 acaa acae acb6 acba acc2 acc6 acce acd2 acda acde ace6 acea acf2 acf6 acfe ad02 ad0a ad0e ad16 ad1a ad22 ad26 ad2e ad32 ad3a ad3e ad46 ad4a ad52 ad56 ad5e BREAK 1 250d6 BREAK 1 4f1 abec abee abf6 abfa ac02 ac06 ac0e ac12 ac1a ac1e ac26 ac2a ac32 ac36 ac3e ac42 ac4a ac4e ac56 ac5a ac62 ac66 ac6e ac72 ac7a ac7e ac86 ac8a ac92 ac96 ac9e aca2 acaa acae acb6 acba acc2 acc6 acce acd2 acda acde ace6 acea acf2 acf6 acfe ad02 ad0a ad0e ad16 ad1a ad22 ad26 ad2e ad32 ad3a ad3e ad46 ad4a ad52 ad56 ad5e BREAK 1 250dc BREAK 1 250e2 BREAK 1 4f1 abec abee abf6 abfa ac02 ac06 ac0e ac12 ac1a ac1e ac26 ac2a ac32 ac36 ac3e ac42 ac4a ac4e ac56 ac5a ac62 ac66 ac6e ac72 ac7a ac7e ac86 ac8a ac92 ac96 ac9e aca2 acaa acae acb6 acba acc2 acc6 acce acd2 acda acde ace6 acea acf2 acf6 acfe ad02 ad0a ad0e ad16 ad1a ad22 ad26 ad2e ad32 ad3a ad3e ad46 ad4a ad52 ad56 ad5e BREAK 1 250e8 BREAK 1 250ee BREAK 1 4f1 abec abee abf6 abfa ac02 ac06 ac0e ac12 ac1a ac1e ac26 ac2a ac32 ac36 ac3e ac42 ac4a ac4e ac56 ac5a ac62 ac66 ac6e ac72 ac7a ac7e ac86 ac8a ac92 ac96 ac9e aca2 acaa acae acb6 acba acc2 acc6 acce acd2 acda acde ace6 acea acf2 acf6 acfe ad02 ad0a ad0e ad16 ad1a ad22 ad26 ad2e ad32 ad3a ad3e ad46 ad4a ad52 ad56 ad5e BREAK 1 250f4 BREAK 1 250fa BREAK 1 4f1 abec abee abf6 abfa ac02 ac06 ac0e ac12 ac1a ac1e ac26 ac2a ac32 ac36 ac3e ac42 ac4a ac4e ac56 ac5a ac62 ac66 ac6e ac72 ac7a ac7e ac86 ac8a ac92 ac96 ac9e aca2 acaa acae acb6 acba acc2 acc6 acce acd2 acda acde ace6 acea acf2 acf6 acfe ad02 ad0a ad0e ad16 ad1a ad22 ad26 ad2e ad32 ad3a ad3e ad46 ad4a ad52 ad56 ad5e BREAK 1 25100 BREAK 1 25106 BREAK 1 4f1 abec abee abf6 abfa ac02 ac06 ac0e ac12 ac1a ac1e ac26 ac2a ac32 ac36 ac3e ac42 ac4a ac4e ac56 ac5a ac62 ac66 ac6e ac72 ac7a ac7e ac86 ac8a ac92 ac96 ac9e aca2 acaa acae acb6 acba acc2 acc6 acce acd2 acda acde ace6 acea acf2 acf6 acfe ad02 ad0a ad0e ad16 ad1a ad22 ad26 ad2e ad32 ad3a ad3e ad46 ad4a ad52 ad56 ad5e BREAK 1 2510c BREAK 1 25112 BREAK 1 4f1 abec abee abf6 abfa ac02 ac06 ac0e ac12 ac1a ac1e ac26 ac2a ac32 ac36 ac3e ac42 ac4a ac4e ac56 ac5a ac62 ac66 ac6e ac72 ac7a ac7e ac86 ac8a ac92 ac96 ac9e aca2 acaa acae acb6 acba acc2 acc6 acce acd2 acda acde ace6 acea acf2 acf6 acfe ad02 ad0a ad0e ad16 ad1a ad22 ad26 ad2e ad32 ad3a ad3e ad46 ad4a ad52 ad56 ad5e BREAK 1 25118 BREAK 1 2511e BREAK 1 4f1 abec abee abf6 abfa ac02 ac06 ac0e ac12 ac1a ac1e ac26 ac2a ac32 ac36 ac3e ac42 ac4a ac4e ac56 ac5a ac62 ac66 ac6e ac72 ac7a ac7e ac86 ac8a ac92 ac96 ac9e aca2 acaa acae acb6 acba acc2 acc6 acce acd2 acda acde ace6 acea acf2 acf6 acfe ad02 ad0a ad0e ad16 ad1a ad22 ad26 ad2e ad32 ad3a ad3e ad46 ad4a ad52 ad56 ad5e BREAK 1 25124 BREAK 1 2512a BREAK 1 4f1 abec abee abf6 abfa ac02 ac06 ac0e ac12 ac1a ac1e ac26 ac2a ac32 ac36 ac3e ac42 ac4a ac4e ac56 ac5a ac62 ac66 ac6e ac72 ac7a ac7e ac86 ac8a ac92 ac96 ac9e aca2 acaa acae acb6 acba acc2 acc6 acce acd2 acda acde ace6 acea acf2 acf6 acfe ad02 ad0a ad0e ad16 ad1a ad22 ad26 ad2e ad32 ad3a ad3e ad46 ad4a ad52 ad56 ad5e BREAK 1 25130 BREAK 1 25136 BREAK 1 2513c BREAK 1 4f1 abec abee abf6 abfa ac02 ac06 ac0e ac12 ac1a ac1e ac26 ac2a ac32 ac36 ac3e ac42 ac4a ac4e ac56 ac5a ac62 ac66 ac6e ac72 ac7a ac7e ac86 ac8a ac92 ac96 ac9e aca2 acaa acae acb6 acba acc2 acc6 acce acd2 acda acde ace6 acea acf2 acf6 acfe ad02 ad0a ad0e ad16 ad1a ad22 ad26 ad2e ad32 ad3a ad3e ad46 ad4a ad52 ad56 ad5e BREAK 1 25142 BREAK 1 25148 BREAK 1 4f1 abec abee abf6 abfa ac02 ac06 ac0e ac12 ac1a ac1e ac26 ac2a ac32 ac36 ac3e ac42 ac4a ac4e ac56 ac5a ac62 ac66 ac6e ac72 ac7a ac7e ac86 ac8a ac92 ac96 ac9e aca2 acaa acae acb6 acba acc2 acc6 acce acd2 acda acde ace6 acea acf2 acf6 acfe ad02 ad0a ad0e ad16 ad1a ad22 ad26 ad2e ad32 ad3a ad3e ad46 ad4a ad52 ad56 ad5e BREAK 1 2514e BREAK 1 25154 BREAK 1 2515a BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 25160 BREAK 1 25166 BREAK 1 2516c BREAK 1 25172 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 25178 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 2517e BREAK 1 25184 BREAK 1 2518a BREAK 1 25190 BREAK 1 25196 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 2519c BREAK 1 4fa af3a af54 af58 af5c af60 af64 af68 af6c af70 BREAK 1 251a2 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 251a8 BREAK 1 251ae BREAK 1 251b4 BREAK 1 251ba BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 251c0 BREAK 1 4fa af3a af3c af40 af44 af48 af4c af50 af54 af58 af5c af60 af64 af68 af6c af70 BREAK 1 251c6 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 251cc BREAK 1 251d2 BREAK 1 251d8 BREAK 1 251de BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 251e4 BREAK 1 4fd af74 af76 af7a af7e af82 af86 af8a af8e af92 af96 af9a af9e afa2 afa6 afaa BREAK 1 251ea BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 251f0 BREAK 1 251f6 BREAK 1 251fc BREAK 1 25202 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 25208 BREAK 1 2520e BREAK 1 4fd af74 af76 af7a af7e af82 af86 af8a af8e af92 af96 af9a af9e afa2 afa6 afaa BREAK 1 25214 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 2521a BREAK 1 25220 BREAK 1 25226 BREAK 1 2522c BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 25232 BREAK 1 25238 BREAK 1 500 afae afb0 afb4 afb8 afbc afc0 afc4 afc8 afcc afd0 afd4 afd8 afdc afe0 afe4 BREAK 1 2523e BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 25244 BREAK 1 2524a BREAK 1 25250 BREAK 1 25256 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 2525c BREAK 1 25262 BREAK 1 503 0 afe8 afea afee aff2 aff6 affa affe b002 b006 b00a b00e b012 b016 b01a b01e BREAK 1 25268 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 2526e BREAK 1 25274 BREAK 1 2527a BREAK 1 25280 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 25286 BREAK 1 2528c BREAK 1 506 b022 b024 b028 b02c b030 b034 b038 b03c b040 b044 b048 b04c b050 b054 b058 BREAK 1 25292 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 25298 BREAK 1 2529e BREAK 1 252a4 BREAK 1 252aa BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 252b0 BREAK 1 252b6 BREAK 1 509 b05c b05e b062 b066 b06a b06e b072 b076 b07a b07e b082 b086 b08a b08e b092 BREAK 1 252bc BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 252c2 BREAK 1 252c8 BREAK 1 252ce BREAK 1 252d4 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 252da BREAK 1 252e0 BREAK 1 50c b096 b098 b09c b0a0 b0a4 b0a8 b0ac b0b0 b0b4 b0b8 b0bc b0c0 b0c4 b0c8 b0cc BREAK 1 252e6 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 252ec BREAK 1 252f2 BREAK 1 252f8 BREAK 1 252fe BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 25304 BREAK 1 2530a BREAK 1 4fa af3a af3c af40 af44 af48 af4c af50 af54 af58 af5c af60 af64 af68 af6c af70 BREAK 1 25310 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 25316 BREAK 1 2531c BREAK 1 25322 BREAK 1 25328 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 2532e BREAK 1 25334 BREAK 1 500 afae afb0 afb4 afb8 afbc afc0 afc4 afc8 afcc afd0 afd4 afd8 afdc afe0 afe4 BREAK 1 2533a BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 25340 BREAK 1 25346 BREAK 1 2534c BREAK 1 25352 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 25358 BREAK 1 2535e BREAK 1 503 0 afe8 afea afee aff2 aff6 affa affe b002 b006 b00a b00e b012 b016 b01a b01e BREAK 1 25364 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 2536a BREAK 1 25370 BREAK 1 25376 BREAK 1 2537c BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 25382 BREAK 1 25388 BREAK 1 506 b022 b024 b028 b02c b030 b034 b038 b03c b040 b044 b048 b04c b050 b054 b058 BREAK 1 2538e BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 25394 BREAK 1 2539a BREAK 1 253a0 BREAK 1 253a6 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 253ac BREAK 1 253b2 BREAK 1 50f b0d0 b0d2 b0d6 b0da b0de b0e2 b0e6 b0ea b0ee b0f2 b0f6 b0fa b0fe b102 b106 BREAK 1 253b8 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 253be BREAK 1 253c4 BREAK 1 253ca BREAK 1 253d0 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 253d6 BREAK 1 253dc BREAK 1 512 b10a b10c b110 b114 b118 b11c b120 b124 b128 b12c b130 b134 b138 b13c b140 BREAK 1 253e2 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 253e8 BREAK 1 253ee BREAK 1 253f4 BREAK 1 253fa BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 25400 BREAK 1 25406 BREAK 1 50f b0d0 b0d2 b0d6 b0da b0de b0e2 b0e6 b0ea b0ee b0f2 b0f6 b0fa b0fe b102 b106 BREAK 1 2540c BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 25412 BREAK 1 25418 BREAK 1 2541e BREAK 1 25424 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 2542a BREAK 1 25430 BREAK 1 512 b10a b10c b110 b114 b118 b11c b120 b124 b128 b12c b130 b134 b138 b13c b140 BREAK 1 25436 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 2543c BREAK 1 25442 BREAK 1 25448 BREAK 1 2544e BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 25454 BREAK 1 2545a BREAK 1 50f b0d0 b0d2 b0d6 b0da b0de b0e2 b0e6 b0ea b0ee b0f2 b0f6 b0fa b0fe b102 b106 BREAK 1 25460 BREAK 1 25466 BREAK 1 515 b144 b146 b14e b152 b15a b15e b166 b16a b172 b176 b17e b182 b18a b18e b196 b19a b1a2 b1a6 b1ae b1b2 b1ba b1be b1c6 b1ca b1d2 b1d6 b1de b1e2 b1ea b1ee b1f6 b1fa b202 b206 b20e b212 b21a b21e b226 b22a b232 b236 b23e b242 b24a b24e b256 b25a b262 b266 b26e b272 b27a b27e b286 b28a b292 b296 b29e b2a2 b2aa b2ae b2b6 BREAK 1 2546c BREAK 1 25472 BREAK 1 512 b10a b10c b110 b114 b118 b11c b120 b124 b128 b12c b130 b134 b138 b13c b140 BREAK 1 25478 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 2547e BREAK 1 25484 BREAK 1 2548a BREAK 1 25490 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 25496 BREAK 1 2549c BREAK 1 50f b0d0 b0d2 b0d6 b0da b0de b0e2 b0e6 b0ea b0ee b0f2 b0f6 b0fa b0fe b102 b106 BREAK 1 254a2 BREAK 1 254a8 BREAK 1 515 b144 b146 b14e b152 b15a b15e b166 b16a b172 b176 b17e b182 b18a b18e b196 b19a b1a2 b1a6 b1ae b1b2 b1ba b1be b1c6 b1ca b1d2 b1d6 b1de b1e2 b1ea b1ee b1f6 b1fa b202 b206 b20e b212 b21a b21e b226 b22a b232 b236 b23e b242 b24a b24e b256 b25a b262 b266 b26e b272 b27a b27e b286 b28a b292 b296 b29e b2a2 b2aa b2ae b2b6 BREAK 1 254ae BREAK 1 512 b10a b10c b110 b114 b118 b11c b120 b124 b128 b12c b130 b134 b138 b13c b140 BREAK 1 254b4 BREAK 1 254ba BREAK 1 254c0 BREAK 1 254c6 BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 254cc 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 254d2 BREAK 1 254d8 BREAK 1 254de BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 254e4 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 254ea BREAK 1 254f0 BREAK 1 254f6 BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 254fc 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 25502 BREAK 1 25508 BREAK 1 2550e BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 25514 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 2551a BREAK 1 25520 BREAK 1 25526 BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 2552c 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 25532 BREAK 1 25538 BREAK 1 2553e BREAK 1 25544 BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 2554a 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 25550 BREAK 1 25556 BREAK 1 2555c BREAK 1 25562 BREAK 1 25568 BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 2556e 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 25574 BREAK 1 2557a BREAK 1 25580 BREAK 1 25586 BREAK 1 2558c BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 25592 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 25598 BREAK 1 2559e BREAK 1 255a4 BREAK 1 255aa BREAK 1 255b0 BREAK 1 255b6 BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 255bc 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 255c2 BREAK 1 255c8 BREAK 1 255ce BREAK 1 255d4 BREAK 1 255da BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 255e0 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 255e6 BREAK 1 255ec BREAK 1 255f2 BREAK 1 255f8 BREAK 1 255fe BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 25604 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 2560a BREAK 1 25610 BREAK 1 25616 BREAK 1 2561c BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 25622 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 25628 BREAK 1 2562e BREAK 1 25634 BREAK 1 2563a BREAK 1 25640 BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 25646 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 2564c BREAK 1 25652 BREAK 1 25658 BREAK 1 2565e BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 25664 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 2566a BREAK 1 25670 BREAK 1 25676 BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 2567c 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 25682 BREAK 1 25688 BREAK 1 2568e BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 25694 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 2569a BREAK 1 256a0 BREAK 1 256a6 BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 256ac 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 256b2 BREAK 1 256b8 BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 256be 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 256c4 BREAK 1 256ca BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 256d0 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 256d6 BREAK 1 256dc BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 256e2 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 256e8 BREAK 1 256ee BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 256f4 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 256fa BREAK 1 25700 BREAK 1 482 92ee 92f0 92f8 9300 9308 9310 9318 9320 9328 9330 9338 c0008 9340 f00008 9348 8 9350 9358 9360 9368 9370 8 9378 8 9380 8 9388 8 9390 8 9398 8 93a0 8 93a8 8 93b0 c00008 93b8 93c0 93c8 93d0 93d8 93e0 BREAK 1 25706 BREAK 1 47f 92a0 92a2 92a6 92aa 92ae 92b2 92b6 92ba 92be 92c2 92c6 92ca 92ce 92d2 92d6 92da 92de 92e2 92e6 92ea BREAK 1 2570c BREAK 1 25712 BREAK 1 482 92ee 92f0 92f8 9300 9308 9310 9318 9320 9328 9330 9338 c0008 9340 f00008 9348 8 9350 9358 9360 9368 9370 8 9378 8 9380 8 9388 8 9390 8 9398 8 93a0 8 93a8 8 93b0 c00008 93b8 93c0 93c8 93d0 93d8 93e0 BREAK 1 25718 BREAK 1 47f 92a0 92a2 92a6 92aa 92ae 92b2 92b6 92ba 92be 92c2 92c6 92ca 92ce 92d2 92d6 92da 92de 92e2 92e6 92ea BREAK 1 2571e BREAK 1 25724 BREAK 1 482 92ee 92f0 92f8 9300 9308 9310 9318 9320 9328 9330 9338 c0008 9340 f00008 9348 8 9350 9358 9360 9368 9370 8 9378 8 9380 8 9388 8 9390 8 9398 8 93a0 8 93a8 8 93b0 c00008 93b8 93c0 93c8 93d0 93d8 93e0 BREAK 1 2572a BREAK 1 47f 92a0 92a2 92a6 92aa 92ae 92b2 92b6 92ba 92be 92c2 92c6 92ca 92ce 92d2 92d6 92da 92de 92e2 92e6 92ea BREAK 1 25730 BREAK 1 25736 BREAK 1 482 92ee 92f0 92f8 9300 9308 9310 9318 9320 9328 9330 9338 c0008 9340 f00008 9348 8 9350 9358 9360 9368 9370 8 9378 8 9380 8 9388 8 9390 8 9398 8 93a0 8 93a8 8 93b0 c00008 93b8 93c0 93c8 93d0 93d8 93e0 BREAK 1 2573c BREAK 1 47f 92a0 92a2 92a6 92aa 92ae 92b2 92b6 92ba 92be 92c2 92c6 92ca 92ce 92d2 92d6 92da 92de 92e2 92e6 92ea BREAK 1 25742 BREAK 1 25748 BREAK 1 491 97d0 97d2 97d3 97d4 97d5 97d6 97d7 97d8 BREAK 1 2574e BREAK 1 25754 BREAK 1 482 92ee 92f0 92f8 9300 9308 9310 9318 9320 9328 9330 9338 c0008 9340 f00008 9348 8 9350 9358 9360 9368 9370 8 9378 8 9380 8 9388 8 9390 8 9398 8 93a0 8 93a8 8 93b0 c00008 93b8 93c0 93c8 93d0 93d8 93e0 BREAK 1 2575a BREAK 1 47f 92a0 92a2 92a6 92aa 92ae 92b2 92b6 92ba 92be 92c2 92c6 92ca 92ce 92d2 92d6 92da 92de 92e2 92e6 92ea BREAK 1 25760 BREAK 1 25766 BREAK 1 494 97d9 97db 97dc 97dd 97de 97df 97e0 97e1 BREAK 1 2576c BREAK 1 25772 BREAK 1 482 92ee 92f0 92f8 9300 9308 9310 9318 9320 9328 9330 9338 c0008 9340 f00008 9348 8 9350 9358 9360 9368 9370 8 9378 8 9380 8 9388 8 9390 8 9398 8 93a0 8 93a8 8 93b0 c00008 93b8 93c0 93c8 93d0 93d8 93e0 BREAK 1 25778 BREAK 1 47f 92a0 92a2 92a6 92aa 92ae 92b2 92b6 92ba 92be 92c2 92c6 92ca 92ce 92d2 92d6 92da 92de 92e2 92e6 92ea BREAK 1 2577e BREAK 1 25784 BREAK 1 497 97e2 97e4 97e5 97e6 97e7 97e8 97e9 97ea BREAK 1 2578a BREAK 1 25790 BREAK 1 485 93e8 93ea 93f2 93fa 9402 940a 9412 941a 9422 942a 9432 c0008 943a f00008 9442 8 944a 9452 945a 9462 946a 8 9472 8 947a 8008 9482 a22808 948a 9492 949a 94a2 94aa 94b2 94ba 94c2 94ca 94d2 94da BREAK 1 25796 BREAK 1 47f 92a0 92a2 92a6 92aa 92ae 92b2 92b6 92ba 92be 92c2 92c6 92ca 92ce 92d2 92d6 92da 92de 92e2 92e6 92ea BREAK 1 2579c BREAK 1 257a2 BREAK 1 49a 97eb 97ed 97ee 97ef 97f0 97f1 97f2 97f3 BREAK 1 257a8 BREAK 1 257ae BREAK 1 488 94e2 94e4 94ec c0008 94f4 f00008 94fc 8 9504 950c 9514 951c 9524 8 952c 8 9534 8 953c 8 9544 8 954c 8 9554 8 955c 8 9564 c00008 956c 9574 957c 9584 958c 9594 959c 95a4 95ac 95b4 95bc 95c4 95cc 95d4 BREAK 1 257b4 BREAK 1 47f 92a0 92a2 92a6 92aa 92ae 92b2 92b6 92ba 92be 92c2 92c6 92ca 92ce 92d2 92d6 92da 92de 92e2 92e6 92ea BREAK 1 257ba BREAK 1 257c0 BREAK 1 48b 95dc 95de 95e6 8 95ee 8 95f6 8 95fe 8 9606 8 960e 8 9616 8 961e 8 9626 c00008 962e 9636 963e 9646 964e 9656 965e 9666 966e 9676 967e 9686 968e 9696 969e 96a6 96ae 96b6 96be 96c6 96ce BREAK 1 257c6 BREAK 1 47f 92a0 92a2 92a6 92aa 92ae 92b2 92b6 92ba 92be 92c2 92c6 92ca 92ce 92d2 92d6 92da 92de 92e2 92e6 92ea BREAK 1 257cc BREAK 1 257d2 BREAK 1 48e 96d6 96d8 96e0 96e8 96f0 96f8 9700 9708 9710 9718 9720 9728 9730 9738 9740 9748 9750 9758 9760 9768 9770 9778 9780 9788 9790 9798 97a0 97a8 97b0 97b8 97c0 97c8 BREAK 1 257d8 BREAK 1 47f 92a0 92a2 92a6 92aa 92ae 92b2 92b6 92ba 92be 92c2 92c6 92ca 92ce 92d2 92d6 92da 92de 92e2 92e6 92ea BREAK 1 257de BREAK 1 257e4 BREAK 1 47f 92a0 92a2 92a6 92aa 92ae 92b2 92b6 92ba 92be 92c2 92c6 92ca 92ce 92d2 92d6 92da 92de 92e2 92e6 92ea BREAK 1 257ea BREAK 1 257f0 BREAK 1 49d 97f4 97f6 97fe 9802 980a 980e 9816 981a 9822 9826 982e 9832 983a 983e 9846 984a 9852 9856 985e 9862 986a 986e 9876 987a 9882 9886 988e 9892 989a 989e 98a6 98aa 98b2 98b6 98be 98c2 98ca 98ce 98d6 98da 98e2 98e6 98ee 98f2 98fa 98fe 9906 990a 9912 9916 991e 9922 992a 992e 9936 993a 9942 9946 994e 9952 995a 995e 9966 BREAK 1 257f6 BREAK 1 49d 97f4 97f6 97fe 9802 980a 980e 9816 981a 9822 9826 982e 9832 983a 983e 9846 984a 9852 9856 985e 9862 986a 986e 9876 987a 9882 9886 988e 9892 989a 989e 98a6 98aa 98b2 98b6 98be 98c2 98ca 98ce 98d6 98da 98e2 98e6 98ee 98f2 98fa 98fe 9906 990a 9912 9916 991e 9922 992a 992e 9936 993a 9942 9946 994e 9952 995a 995e 9966 BREAK 1 257fc BREAK 1 4a3 9ae0 9ae5 3009a 9aea 9aef 9af4 9af9 9afe 9b03 0 BREAK 1 25802 BREAK 1 49d 97f4 97f6 97fe 9802 980a 980e 9816 981a 9822 9826 982e 9832 983a 983e 9846 984a 9852 9856 985e 9862 986a 986e 9876 987a 9882 9886 988e 9892 989a 989e 98a6 98aa 98b2 98b6 98be 98c2 98ca 98ce 98d6 98da 98e2 98e6 98ee 98f2 98fa 98fe 9906 990a 9912 9916 991e 9922 992a 992e 9936 993a 9942 9946 994e 9952 995a 995e 9966 BREAK 1 25808 BREAK 1 4a3 9ae0 9ae3 3009a 9ae8 9aed 9af2 9af7 9afc 9b01 BREAK 1 2580e BREAK 1 49d 97f4 97f6 97fe 9802 980a 980e 9816 981a 9822 9826 982e 9832 983a 983e 9846 984a 9852 9856 985e 9862 986a 986e 9876 987a 9882 9886 988e 9892 989a 989e 98a6 98aa 98b2 98b6 98be 98c2 98ca 98ce 98d6 98da 98e2 98e6 98ee 98f2 98fa 98fe 9906 990a 9912 9916 991e 9922 992a 992e 9936 993a 9942 9946 994e 9952 995a 995e 9966 BREAK 1 25814 BREAK 1 4a3 9ae0 9ae2 3009a 9ae7 9aec 9af1 9af6 9afb 9b00 BREAK 1 2581a BREAK 1 49d 97f4 97f6 97fe 9802 980a 980e 9816 981a 9822 9826 982e 9832 983a 983e 9846 984a 9852 9856 985e 9862 986a 986e 9876 987a 9882 9886 988e 9892 989a 989e 98a6 98aa 98b2 98b6 98be 98c2 98ca 98ce 98d6 98da 98e2 98e6 98ee 98f2 98fa 98fe 9906 990a 9912 9916 991e 9922 992a 992e 9936 993a 9942 9946 994e 9952 995a 995e 9966 BREAK 1 25820 BREAK 1 4a3 9ae0 9ae2 3009a 9ae7 9aec 9af1 9af6 9afb 9b00 BREAK 1 25826 BREAK 1 49d 97f4 97f6 97fe 9802 980a 980e 9816 981a 9822 9826 982e 9832 983a 983e 9846 984a 9852 9856 985e 9862 986a 986e 9876 987a 9882 9886 988e 9892 989a 989e 98a6 98aa 98b2 98b6 98be 98c2 98ca 98ce 98d6 98da 98e2 98e6 98ee 98f2 98fa 98fe 9906 990a 9912 9916 991e 9922 992a 992e 9936 993a 9942 9946 994e 9952 995a 995e 9966 BREAK 1 2582c BREAK 1 4a3 9ae0 9ae2 3009a 9ae7 9aec 9af1 9af6 9afb 9b00 BREAK 1 25832 BREAK 1 49d 97f4 97f6 97fe 9802 980a 980e 9816 981a 9822 9826 982e 9832 983a 983e 9846 984a 9852 9856 985e 9862 986a 986e 9876 987a 9882 9886 988e 9892 989a 989e 98a6 98aa 98b2 98b6 98be 98c2 98ca 98ce 98d6 98da 98e2 98e6 98ee 98f2 98fa 98fe 9906 990a 9912 9916 991e 9922 992a 992e 9936 993a 9942 9946 994e 9952 995a 995e 9966 BREAK 1 25838 BREAK 1 4a3 9ae0 9ae2 3009a 9ae7 9aec 9af1 9af6 9afb 9b00 BREAK 1 2583e BREAK 1 49d 97f4 97f6 97fe 9802 980a 980e 9816 981a 9822 9826 982e 9832 983a 983e 9846 984a 9852 9856 985e 9862 986a 986e 9876 987a 9882 9886 988e 9892 989a 989e 98a6 98aa 98b2 98b6 98be 98c2 98ca 98ce 98d6 98da 98e2 98e6 98ee 98f2 98fa 98fe 9906 990a 9912 9916 991e 9922 992a 992e 9936 993a 9942 9946 994e 9952 995a 995e 9966 BREAK 1 25844 BREAK 1 4a3 9ae0 9ae2 3009a 9ae7 9aec 9af1 9af6 9afb 9b00 BREAK 1 2584a BREAK 1 49d 97f4 97f6 97fe 9802 980a 980e 9816 981a 9822 9826 982e 9832 983a 983e 9846 984a 9852 9856 985e 9862 986a 986e 9876 987a 9882 9886 988e 9892 989a 989e 98a6 98aa 98b2 98b6 98be 98c2 98ca 98ce 98d6 98da 98e2 98e6 98ee 98f2 98fa 98fe 9906 990a 9912 9916 991e 9922 992a 992e 9936 993a 9942 9946 994e 9952 995a 995e 9966 BREAK 1 25850 BREAK 1 4a3 9ae0 9ae2 3009a 9ae7 9aec 9af1 9af6 9afb 9b00 BREAK 1 25856 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 2585c BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 25862 BREAK 1 4a6 9b05 9b09 9b0d 9b11 9b15 9b19 9b1d 9b21 BREAK 1 25868 100300 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 2586e BREAK 1 4a6 9b05 9b08 9b0c 9b10 9b14 9b18 9b1c 9b20 BREAK 1 25874 100300 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 2587a BREAK 1 4a6 9b05 9b07 9b0b 9b0f 9b13 9b17 9b1b 9b1f BREAK 1 25880 100300 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 25886 BREAK 1 4a6 9b05 9b07 9b0b 9b0f 9b13 9b17 9b1b 9b1f BREAK 1 2588c 100300 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 25892 BREAK 1 4a6 9b05 9b07 9b0b 9b0f 9b13 9b17 9b1b 9b1f BREAK 1 25898 100300 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 2589e BREAK 1 4a6 9b05 9b07 9b0b 9b0f 9b13 9b17 9b1b 9b1f BREAK 1 258a4 100300 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 258aa BREAK 1 4a6 9b05 9b07 9b0b 9b0f 9b13 9b17 9b1b 9b1f BREAK 1 258b0 190300 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 258b6 BREAK 1 4a6 9b05 9b07 9b0b 9b0f 9b13 9b17 9b1b 9b1f BREAK 1 258bc 260300 BREAK 1 258c2 BREAK 1 4af 9b66 9b68 9b70 9b74 9b7c 9b80 9b88 9b8c 9b94 9b98 9ba0 9ba4 9bac 9bb0 9bb8 9bbc 9bc4 9bc8 9bd0 9bd4 9bdc 9be0 9be8 9bec 9bf4 9bf8 9c00 9c04 9c0c 9c10 9c18 9c1c 9c24 9c28 9c30 9c34 9c3c 9c40 9c48 9c4c 9c54 9c58 9c60 9c64 9c6c 9c70 9c78 9c7c 9c84 9c88 9c90 9c94 9c9c 9ca0 9ca8 9cac 9cb4 9cb8 9cc0 9cc4 9ccc 9cd0 9cd8 BREAK 1 258c8 BREAK 1 4af 9b66 9b68 9b70 9b74 9b7c 9b80 9b88 9b8c 9b94 9b98 9ba0 9ba4 9bac 9bb0 9bb8 9bbc 9bc4 9bc8 9bd0 9bd4 9bdc 9be0 9be8 9bec 9bf4 9bf8 9c00 9c04 9c0c 9c10 9c18 9c1c 9c24 9c28 9c30 9c34 9c3c 9c40 9c48 9c4c 9c54 9c58 9c60 9c64 9c6c 9c70 9c78 9c7c 9c84 9c88 9c90 9c94 9c9c 9ca0 9ca8 9cac 9cb4 9cb8 9cc0 9cc4 9ccc 9cd0 9cd8 BREAK 1 258ce BREAK 1 258d4 BREAK 1 4b2 9cdc 9cde 9cdf 9ce0 9ce1 BREAK 1 258da BREAK 1 4af 9b66 9b68 9b70 9b74 9b7c 9b80 9b88 9b8c 9b94 9b98 9ba0 9ba4 9bac 9bb0 9bb8 9bbc 9bc4 9bc8 9bd0 9bd4 9bdc 9be0 9be8 9bec 9bf4 9bf8 9c00 9c04 9c0c 9c10 9c18 9c1c 9c24 9c28 9c30 9c34 9c3c 9c40 9c48 9c4c 9c54 9c58 9c60 9c64 9c6c 9c70 9c78 9c7c 9c84 9c88 9c90 9c94 9c9c 9ca0 9ca8 9cac 9cb4 9cb8 9cc0 9cc4 9ccc 9cd0 9cd8 BREAK 1 258e0 BREAK 1 4af 9b66 9b68 9b70 9b74 9b7c 9b80 9b88 9b8c 9b94 9b98 9ba0 9ba4 9bac 9bb0 9bb8 9bbc 9bc4 9bc8 9bd0 9bd4 9bdc 9be0 9be8 9bec 9bf4 9bf8 9c00 9c04 9c0c 9c10 9c18 9c1c 9c24 9c28 9c30 9c34 9c3c 9c40 9c48 9c4c 9c54 9c58 9c60 9c64 9c6c 9c70 9c78 9c7c 9c84 9c88 9c90 9c94 9c9c 9ca0 9ca8 9cac 9cb4 9cb8 9cc0 9cc4 9ccc 9cd0 9cd8 BREAK 1 258e6 BREAK 1 258ec BREAK 1 4b2 9cdc 9cde 9cdf 9ce0 9ce1 BREAK 1 258f2 BREAK 1 4af 9b66 9b68 9b70 9b74 9b7c 9b80 9b88 9b8c 9b94 9b98 9ba0 9ba4 9bac 9bb0 9bb8 9bbc 9bc4 9bc8 9bd0 9bd4 9bdc 9be0 9be8 9bec 9bf4 9bf8 9c00 9c04 9c0c 9c10 9c18 9c1c 9c24 9c28 9c30 9c34 9c3c 9c40 9c48 9c4c 9c54 9c58 9c60 9c64 9c6c 9c70 9c78 9c7c 9c84 9c88 9c90 9c94 9c9c 9ca0 9ca8 9cac 9cb4 9cb8 9cc0 9cc4 9ccc 9cd0 9cd8 BREAK 1 258f8 BREAK 1 4af 9b66 9b68 9b70 9b74 9b7c 9b80 9b88 9b8c 9b94 9b98 9ba0 9ba4 9bac 9bb0 9bb8 9bbc 9bc4 9bc8 9bd0 9bd4 9bdc 9be0 9be8 9bec 9bf4 9bf8 9c00 9c04 9c0c 9c10 9c18 9c1c 9c24 9c28 9c30 9c34 9c3c 9c40 9c48 9c4c 9c54 9c58 9c60 9c64 9c6c 9c70 9c78 9c7c 9c84 9c88 9c90 9c94 9c9c 9ca0 9ca8 9cac 9cb4 9cb8 9cc0 9cc4 9ccc 9cd0 9cd8 BREAK 1 258fe BREAK 1 25904 BREAK 1 4b2 9cdc 9cde 9cdf 9ce0 9ce1 BREAK 1 2590a BREAK 1 25910 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25916 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 2591c BREAK 1 25922 BREAK 1 25928 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 2592e BREAK 1 25934 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 2593a BREAK 1 25940 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25946 BREAK 1 2594c BREAK 1 25952 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25958 BREAK 1 2595e BREAK 1 25964 BREAK 1 2596a BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25970 BREAK 1 25976 BREAK 1 2597c BREAK 1 25982 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25988 BREAK 1 2598e BREAK 1 25994 BREAK 1 2599a BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 259a0 BREAK 1 259a6 BREAK 1 259ac BREAK 1 259b2 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 259b8 BREAK 1 259be BREAK 1 259c4 BREAK 1 259ca BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 259d0 BREAK 1 259d6 BREAK 1 259dc BREAK 1 259e2 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 259e8 BREAK 1 259ee BREAK 1 259f4 BREAK 1 259fa BREAK 1 25a00 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25a06 BREAK 1 25a0c BREAK 1 25a12 BREAK 1 25a18 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25a1e BREAK 1 25a24 BREAK 1 25a2a BREAK 1 25a30 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25a36 BREAK 1 25a3c BREAK 1 25a42 BREAK 1 25a48 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25a4e BREAK 1 25a54 BREAK 1 25a5a BREAK 1 25a60 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25a66 BREAK 1 25a6c BREAK 1 25a72 BREAK 1 25a78 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25a7e BREAK 1 25a84 BREAK 1 25a8a BREAK 1 25a90 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25a96 BREAK 1 25a9c BREAK 1 25aa2 BREAK 1 25aa8 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25aae BREAK 1 25ab4 BREAK 1 25aba BREAK 1 25ac0 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25ac6 BREAK 1 25acc BREAK 1 25ad2 BREAK 1 25ad8 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25ade BREAK 1 25ae4 BREAK 1 25aea BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25af0 BREAK 1 25af6 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25afc BREAK 1 25b02 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25b08 BREAK 1 25b0e BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25b14 BREAK 1 25b1a BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25b20 BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25b26 BREAK 1 25b2c BREAK 1 25b32 BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25b38 BREAK 1 25b3e BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25b44 BREAK 1 25b4a BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25b50 BREAK 1 25b56 BREAK 1 25b5c BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25b62 BREAK 1 25b68 BREAK 1 25b6e BREAK 1 25b74 BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25b7a BREAK 1 25b80 BREAK 1 25b86 BREAK 1 25b8c BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25b92 BREAK 1 25b98 BREAK 1 25b9e BREAK 1 25ba4 BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25baa BREAK 1 25bb0 BREAK 1 25bb6 BREAK 1 25bbc BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25bc2 BREAK 1 25bc8 BREAK 1 25bce BREAK 1 25bd4 BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25bda BREAK 1 25be0 BREAK 1 25be6 BREAK 1 25bec BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25bf2 BREAK 1 25bf8 BREAK 1 25bfe BREAK 1 25c04 BREAK 1 25c0a BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25c10 BREAK 1 25c16 BREAK 1 25c1c BREAK 1 25c22 BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25c28 BREAK 1 25c2e BREAK 1 25c34 BREAK 1 25c3a BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25c40 BREAK 1 25c46 BREAK 1 25c4c BREAK 1 25c52 BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25c58 BREAK 1 25c5e BREAK 1 25c64 BREAK 1 25c6a BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25c70 BREAK 1 25c76 BREAK 1 25c7c BREAK 1 25c82 BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25c88 BREAK 1 25c8e BREAK 1 25c94 BREAK 1 25c9a BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25ca0 BREAK 1 25ca6 BREAK 1 25cac BREAK 1 25cb2 BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25cb8 BREAK 1 25cbe BREAK 1 25cc4 BREAK 1 25cca BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25cd0 BREAK 1 25cd6 BREAK 1 25cdc BREAK 1 25ce2 BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25ce8 BREAK 1 25cee BREAK 1 25cf4 BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25cfa BREAK 1 25d00 BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25d06 BREAK 1 25d0c BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25d12 BREAK 1 25d18 BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25d1e BREAK 1 25d24 BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25d2a BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25d30 BREAK 1 25d36 BREAK 1 25d3c BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25d42 BREAK 1 25d48 BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25d4e BREAK 1 25d54 BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25d5a BREAK 1 25d60 BREAK 1 25d66 BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25d6c BREAK 1 25d72 BREAK 1 25d78 BREAK 1 25d7e BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25d84 BREAK 1 25d8a BREAK 1 25d90 BREAK 1 25d96 BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25d9c BREAK 1 25da2 BREAK 1 25da8 BREAK 1 25dae BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25db4 BREAK 1 25dba BREAK 1 25dc0 BREAK 1 25dc6 BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25dcc BREAK 1 25dd2 BREAK 1 25dd8 BREAK 1 25dde BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25de4 BREAK 1 25dea BREAK 1 25df0 BREAK 1 25df6 BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25dfc BREAK 1 25e02 BREAK 1 25e08 BREAK 1 25e0e BREAK 1 25e14 BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25e1a BREAK 1 25e20 BREAK 1 25e26 BREAK 1 25e2c BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25e32 BREAK 1 25e38 BREAK 1 25e3e BREAK 1 25e44 BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25e4a BREAK 1 25e50 BREAK 1 25e56 BREAK 1 25e5c BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25e62 BREAK 1 25e68 BREAK 1 25e6e BREAK 1 25e74 BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25e7a BREAK 1 25e80 BREAK 1 25e86 BREAK 1 25e8c BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25e92 BREAK 1 25e98 BREAK 1 25e9e BREAK 1 25ea4 BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25eaa BREAK 1 25eb0 BREAK 1 25eb6 BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25ebc BREAK 1 25ec2 BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25ec8 BREAK 1 25ece BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25ed4 BREAK 1 25eda BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25ee0 BREAK 1 25ee6 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 25eec BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 25ef2 BREAK 1 25ef8 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 25efe BREAK 1 25f04 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 25f0a BREAK 1 25f10 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 25f16 BREAK 1 25f1c BREAK 1 25f22 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 25f28 BREAK 1 25f2e BREAK 1 25f34 BREAK 1 25f3a BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 25f40 BREAK 1 25f46 BREAK 1 25f4c BREAK 1 25f52 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 25f58 BREAK 1 25f5e BREAK 1 25f64 BREAK 1 25f6a BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 25f70 BREAK 1 25f76 BREAK 1 25f7c BREAK 1 25f82 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 25f88 BREAK 1 25f8e BREAK 1 25f94 BREAK 1 25f9a BREAK 1 4e5 aa64 aa67 aa6f aa73 aa7b aa7f aa87 aa8b aa93 aa97 aa9f aaa3 aaab aaaf aab7 aabb aac3 aac7 aacf aad3 aadb aadf aae7 aaeb aaf3 aaf7 aaff ab03 0 ab0b ab0f ab17 ab1b ab23 ab27 ab2f ab33 ab3b ab3f ab47 ab4b ab53 ab57 ab5f ab63 ab6b ab6f ab77 ab7b ab83 ab87 ab8f ab93 ab9b ab9f aba7 abab abb3 abb7 abbf abc3 abcb abcf abd7 BREAK 1 25fa0 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 25fa6 BREAK 1 25fac BREAK 1 25fb2 BREAK 1 25fb8 BREAK 1 4e5 aa64 aa68 aa70 aa74 aa7c aa80 aa88 aa8c aa94 aa98 aaa0 aaa4 aaac aab0 aab8 aabc aac4 aac8 aad0 aad4 aadc aae0 aae8 aaec aaf4 aaf8 ab00 ab04 ab0c ab10 ab18 ab1c ab24 ab28 ab30 ab34 ab3c ab40 ab48 ab4c ab54 ab58 ab60 ab64 ab6c ab70 ab78 ab7c ab84 ab88 ab90 ab94 ab9c aba0 aba8 abac abb4 abb8 abc0 abc4 abcc abd0 abd8 BREAK 1 25fbe BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 25fc4 BREAK 1 25fca BREAK 1 25fd0 BREAK 1 25fd6 BREAK 1 4e5 aa64 aa69 aa71 aa75 aa7d aa81 aa89 aa8d aa95 aa99 aaa1 aaa5 aaad aab1 aab9 aabd aac5 aac9 aad1 aad5 aadd aae1 aae9 aaed aaf5 aaf9 ab01 ab05 ab0d ab11 ab19 ab1d ab25 ab29 ab31 ab35 ab3d ab41 ab49 ab4d ab55 ab59 ab61 ab65 ab6d ab71 ab79 ab7d ab85 ab89 ab91 ab95 ab9d aba1 aba9 abad abb5 abb9 abc1 abc5 abcd abd1 abd9 BREAK 1 25fdc BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 25fe2 BREAK 1 25fe8 BREAK 1 25fee BREAK 1 25ff4 BREAK 1 4e5 aa64 aa6a aa72 aa76 aa7e aa82 aa8a aa8e aa96 aa9a aaa2 aaa6 aaae aab2 aaba aabe aac6 aaca aad2 aad6 aade aae2 aaea aaee aaf6 aafa ab02 ab06 ab0e ab12 ab1a ab1e ab26 ab2a ab32 ab36 ab3e ab42 ab4a ab4e ab56 ab5a ab62 ab66 ab6e ab72 ab7a ab7e ab86 ab8a ab92 ab96 ab9e aba2 abaa abae abb6 abba abc2 abc6 abce abd2 abda BREAK 1 25ffa BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 26000 BREAK 1 26006 BREAK 1 2600c BREAK 1 26012 BREAK 1 4e5 aa64 aa6b aa73 aa77 aa7f aa83 aa8b aa8f aa97 aa9b aaa3 aaa7 aaaf aab3 aabb aabf aac7 aacb aad3 aad7 aadf aae3 aaeb aaef aaf7 aafb ab03 0 ab07 ab0f ab13 ab1b ab1f ab27 ab2b ab33 ab37 ab3f ab43 ab4b ab4f ab57 ab5b ab63 ab67 ab6f ab73 ab7b ab7f ab87 ab8b ab93 ab97 ab9f aba3 abab abaf abb7 abbb abc3 abc7 abcf abd3 abdb BREAK 1 26018 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 2601e BREAK 1 26024 BREAK 1 2602a BREAK 1 26030 BREAK 1 4e5 aa64 aa6c aa74 aa78 aa80 aa84 aa8c aa90 aa98 aa9c aaa4 aaa8 aab0 aab4 aabc aac0 aac8 aacc aad4 aad8 aae0 aae4 aaec aaf0 aaf8 aafc ab04 ab08 ab10 ab14 ab1c ab20 ab28 ab2c ab34 ab38 ab40 ab44 ab4c ab50 ab58 ab5c ab64 ab68 ab70 ab74 ab7c ab80 ab88 ab8c ab94 ab98 aba0 aba4 abac abb0 abb8 abbc abc4 abc8 abd0 abd4 abdc BREAK 1 26036 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 2603c BREAK 1 26042 BREAK 1 26048 BREAK 1 2604e BREAK 1 4e5 aa64 aa6d aa75 aa79 aa81 aa85 aa8d aa91 aa99 aa9d aaa5 aaa9 aab1 aab5 aabd aac1 aac9 aacd aad5 aad9 aae1 aae5 aaed aaf1 aaf9 aafd ab05 ab09 ab11 ab15 ab1d ab21 ab29 ab2d ab35 ab39 ab41 ab45 ab4d ab51 ab59 ab5d ab65 ab69 ab71 ab75 ab7d ab81 ab89 ab8d ab95 ab99 aba1 aba5 abad abb1 abb9 abbd abc5 abc9 abd1 abd5 abdd BREAK 1 26054 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 2605a BREAK 1 26060 BREAK 1 26066 BREAK 1 2606c BREAK 1 4e5 aa64 aa6e aa76 aa7a aa82 aa86 aa8e aa92 aa9a aa9e aaa6 aaaa aab2 aab6 aabe aac2 aaca aace aad6 aada aae2 aae6 aaee aaf2 aafa aafe ab06 ab0a ab12 ab16 ab1e ab22 ab2a ab2e ab36 ab3a ab42 ab46 ab4e ab52 ab5a ab5e ab66 ab6a ab72 ab76 ab7e ab82 ab8a ab8e ab96 ab9a aba2 aba6 abae abb2 abba abbe abc6 abca abd2 abd6 abde BREAK 1 26072 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 26078 BREAK 1 2607e BREAK 1 26084 BREAK 1 2608a BREAK 1 4e5 aa64 aa6f aa77 aa7b aa83 aa87 aa8f aa93 aa9b aa9f aaa7 aaab aab3 aab7 aabf aac3 aacb aacf aad7 aadb aae3 aae7 aaef aaf3 aafb aaff ab07 ab0b ab13 ab17 ab1f ab23 ab2b ab2f ab37 ab3b ab43 ab47 ab4f ab53 ab5b ab5f ab67 ab6b ab73 ab77 ab7f ab83 ab8b ab8f ab97 ab9b aba3 aba7 abaf abb3 abbb abbf abc7 abcb abd3 abd7 abdf BREAK 1 26090 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 26096 BREAK 1 2609c BREAK 1 260a2 BREAK 1 260a8 BREAK 1 4e5 aa64 aa70 aa78 aa7c aa84 aa88 aa90 aa94 aa9c aaa0 aaa8 aaac aab4 aab8 aac0 aac4 aacc aad0 aad8 aadc aae4 aae8 aaf0 aaf4 aafc ab00 ab08 ab0c ab14 ab18 ab20 ab24 ab2c ab30 ab38 ab3c ab44 ab48 ab50 ab54 ab5c ab60 ab68 ab6c ab74 ab78 ab80 ab84 ab8c ab90 ab98 ab9c aba4 aba8 abb0 abb4 abbc abc0 abc8 abcc abd4 abd8 abe0 BREAK 1 260ae BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 260b4 BREAK 1 260ba BREAK 1 260c0 BREAK 1 260c6 BREAK 1 4e5 aa64 aa71 aa79 aa7d aa85 aa89 aa91 aa95 aa9d aaa1 aaa9 aaad aab5 aab9 aac1 aac5 aacd aad1 aad9 aadd aae5 aae9 aaf1 aaf5 aafd ab01 ab09 ab0d ab15 ab19 ab21 ab25 ab2d ab31 ab39 ab3d ab45 ab49 ab51 ab55 ab5d ab61 ab69 ab6d ab75 ab79 ab81 ab85 ab8d ab91 ab99 ab9d aba5 aba9 abb1 abb5 abbd abc1 abc9 abcd abd5 abd9 abe1 BREAK 1 260cc BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 260d2 BREAK 1 260d8 BREAK 1 260de BREAK 1 260e4 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 260ea BREAK 1 260f0 BREAK 1 260f6 BREAK 1 260fc BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 26102 BREAK 1 26108 BREAK 1 2610e BREAK 1 26114 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 2611a BREAK 1 26120 BREAK 1 26126 BREAK 1 2612c BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 26132 BREAK 1 26138 BREAK 1 2613e BREAK 1 26144 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 2614a BREAK 1 26150 BREAK 1 26156 BREAK 1 2615c BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 26162 BREAK 1 26168 BREAK 1 2616e BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 26174 BREAK 1 2617a BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 26180 BREAK 1 26186 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 2618c BREAK 1 26192 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 26198 BREAK 1 2619e BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 261a4 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 261aa BREAK 1 261b0 BREAK 1 261b6 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 261bc BREAK 1 261c2 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 261c8 BREAK 1 261ce BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 261d4 BREAK 1 261da BREAK 1 261e0 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 261e6 BREAK 1 261ec BREAK 1 261f2 BREAK 1 261f8 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 261fe BREAK 1 26204 BREAK 1 2620a BREAK 1 26210 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 26216 BREAK 1 2621c BREAK 1 26222 BREAK 1 26228 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 2622e BREAK 1 26234 BREAK 1 2623a BREAK 1 26240 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 26246 BREAK 1 2624c BREAK 1 26252 BREAK 1 26258 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 2625e BREAK 1 26264 BREAK 1 2626a BREAK 1 26270 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 26276 BREAK 1 2627c BREAK 1 26282 BREAK 1 26288 BREAK 1 2628e BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 26294 BREAK 1 2629a BREAK 1 262a0 BREAK 1 262a6 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 262ac BREAK 1 262b2 BREAK 1 262b8 BREAK 1 262be BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 262c4 BREAK 1 262ca BREAK 1 262d0 BREAK 1 262d6 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 262dc BREAK 1 262e2 BREAK 1 262e8 BREAK 1 262ee BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 262f4 BREAK 1 262fa BREAK 1 26300 BREAK 1 26306 BREAK 1 2630c BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 26312 BREAK 1 26318 BREAK 1 2631e BREAK 1 26324 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 2632a BREAK 1 26330 BREAK 1 26336 BREAK 1 2633c BREAK 1 26342 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 26348 BREAK 1 2634e BREAK 1 26354 BREAK 1 2635a BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 26360 BREAK 1 26366 BREAK 1 2636c BREAK 1 26372 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 26378 BREAK 1 2637e BREAK 1 26384 BREAK 1 2638a BREAK 1 26390 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 26396 BREAK 1 2639c BREAK 1 263a2 BREAK 1 263a8 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 263ae BREAK 1 263b4 BREAK 1 263ba BREAK 1 263c0 BREAK 1 263c6 BREAK 1 263cc BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 263d2 BREAK 1 4a9 9b23 9b25 9b29 9b2d 9b31 9b35 9b39 9b3d BREAK 1 263d8 200300 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 263de BREAK 1 4a9 9b23 9b25 9b29 9b2d 9b31 9b35 9b39 9b3d BREAK 1 263e4 100300 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 263ea BREAK 1 4a9 9b23 9b25 9b29 9b2d 9b31 9b35 9b39 9b3d BREAK 1 263f0 100300 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 263f6 BREAK 1 4a9 9b23 9b25 9b29 9b2d 9b31 9b35 9b39 9b3d BREAK 1 263fc 100300 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 26402 BREAK 1 4ac 9b41 9b43 3009b 9b48 9b4d 9b52 9b57 9b5c 9b61 BREAK 1 26408 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 2640e BREAK 1 4ac 9b41 9b43 3009b 9b48 9b4d 9b52 9b57 9b5c 9b61 BREAK 1 26414 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 2641a BREAK 1 4ac 9b41 9b43 3009b 9b48 9b4d 9b52 9b57 9b5c 9b61 BREAK 1 26420 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 26426 BREAK 1 4ac 9b41 9b44 3009b 9b49 9b4e 9b53 9b58 9b5d 9b62 BREAK 1 2642c BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 26432 BREAK 1 4ac 9b41 9b45 3009b 9b4a 9b4f 9b54 9b59 9b5e 9b63 BREAK 1 26438 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 2643e BREAK 1 4ac 9b41 9b47 3009b 9b4c 9b51 9b56 9b5b 9b60 9b65 BREAK 1 26444 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 2644a BREAK 1 26450 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 26456 BREAK 1 2645c BREAK 1 26462 BREAK 1 26468 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 2646e BREAK 1 26474 BREAK 1 50f b0d0 b0d2 b0d6 b0da b0de b0e2 b0e6 b0ea b0ee b0f2 b0f6 b0fa b0fe b102 b106 BREAK 1 2647a BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 26480 BREAK 1 26486 BREAK 1 2648c BREAK 1 26492 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 26498 BREAK 1 2649e BREAK 1 512 b10a b10c b110 b114 b118 b11c b120 b124 b128 b12c b130 b134 b138 b13c b140 BREAK 1 264a4 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 264aa BREAK 1 264b0 BREAK 1 264b6 BREAK 1 264bc BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 264c2 BREAK 1 264c8 BREAK 1 50f b0d0 b0d2 b0d6 b0da b0de b0e2 b0e6 b0ea b0ee b0f2 b0f6 b0fa b0fe b102 b106 BREAK 1 264ce BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 264d4 BREAK 1 264da BREAK 1 264e0 BREAK 1 264e6 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 264ec BREAK 1 264f2 BREAK 1 512 b10a b10c b110 b114 b118 b11c b120 b124 b128 b12c b130 b134 b138 b13c b140 BREAK 1 264f8 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 264fe BREAK 1 26504 BREAK 1 2650a BREAK 1 26510 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 26516 BREAK 1 2651c BREAK 1 500 afae afb0 afb4 afb8 afbc afc0 afc4 afc8 afcc afd0 afd4 afd8 afdc afe0 afe4 BREAK 1 26522 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 26528 BREAK 1 2652e BREAK 1 26534 BREAK 1 2653a BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 26540 BREAK 1 26546 BREAK 1 503 0 afe8 afea afee aff2 aff6 affa affe b002 b006 b00a b00e b012 b016 b01a b01e BREAK 1 2654c BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 26552 BREAK 1 26558 BREAK 1 2655e BREAK 1 26564 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 2656a BREAK 1 26570 BREAK 1 506 b022 b024 b028 b02c b030 b034 b038 b03c b040 b044 b048 b04c b050 b054 b058 BREAK 1 26576 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 2657c BREAK 1 26582 BREAK 1 26588 BREAK 1 2658e BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 26594 BREAK 1 2659a BREAK 1 509 b05c b05e b062 b066 b06a b06e b072 b076 b07a b07e b082 b086 b08a b08e b092 BREAK 1 265a0 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 265a6 BREAK 1 265ac BREAK 1 265b2 BREAK 1 265b8 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 265be BREAK 1 265c4 BREAK 1 50c b096 b098 b09c b0a0 b0a4 b0a8 b0ac b0b0 b0b4 b0b8 b0bc b0c0 b0c4 b0c8 b0cc BREAK 1 265ca BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 265d0 BREAK 1 265d6 BREAK 1 265dc BREAK 1 265e2 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 265e8 BREAK 1 265ee BREAK 1 4fa af3a af3c af40 af44 af48 af4c af50 af54 af58 af5c af60 af64 af68 af6c af70 BREAK 1 265f4 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 265fa BREAK 1 26600 BREAK 1 26606 BREAK 1 2660c BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 26612 BREAK 1 26618 BREAK 1 4fa af3a af3c af40 af44 af48 af4c af50 af54 af58 af5c af60 af64 af68 af6c af70 BREAK 1 2661e BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 26624 BREAK 1 2662a BREAK 1 26630 BREAK 1 26636 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 2663c BREAK 1 26642 BREAK 1 4fd af74 af76 af7a af7e af82 af86 af8a af8e af92 af96 af9a af9e afa2 afa6 afaa BREAK 1 26648 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 2664e BREAK 1 26654 BREAK 1 2665a BREAK 1 26660 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 26666 BREAK 1 2666c BREAK 1 4fd af74 af76 af7a af7e af82 af86 af8a af8e af92 af96 af9a af9e afa2 afa6 afaa BREAK 1 26672 BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 26678 BREAK 1 2667e BREAK 1 26684 BREAK 1 386 860000 6e06 6e08 6e0a 6e0c 6e0e 6e10 6e12 6e14 6e16 6e18 6e1a 6e1c 6e1e 6e20 6e22 6e24 6e26 6e28 6e2a 6e2c 6e2e 6e30 6e32 6e34 6e36 6e38 6e3a 6e3c 6e3e 6e40 6e42 6e44 BREAK 1 2668a BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 26690 BREAK 1 26696 BREAK 1 4b5 9ce2 9ce4 9ce6 9ce8 9cea 9cec 9cee 9cf0 9cf2 9cf4 9cf6 9cf8 9cfa 9cfc 9cfe 9d00 9d02 9d04 9d06 9d08 9d0a 9d0c 9d0e 9d10 9d12 9d14 9d16 9d18 9d1a 9d1c 9d1e 9d20 BREAK 1 2669c BREAK 1 266a2 BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c ================================================ FILE: figure/SignalPulls/signaldecode.py ================================================ f = open("clock.csv") l = [] t = 0 t= f.readline() print "here" print t while(True): try: t= f.readline() l.append(t.split(',')[3]) except: break for i in range(0, len(l)): #print i if int(l[i], 16) == 3: #print "read", a = (int(l[i+1], 16) << 16 ) | (int(l[i+2], 16) << 8 ) | int(l[i+3], 16) if (a == 1): print "BREAK" print "%x" % a ================================================ FILE: figure/SignalPulls/usatour.txt ================================================ here Time [s],Packet ID,MOSI,MISO BREAK 1 2a8 2af2//load usa logo 2af4 2af8 2afc 2b00 2b04 2b08 2b0c 2b10 2b14 2b18 2b1c 2b20 2b24 2b28 2b2c 2b30 BREAK 1 2cc 2e06//guess usa name 2e08 2e10 2e18 2e20 2e28 2e30 2e38 2e40 2e48 2e50 2e58 2e60 BREAK 1 927//single byte read (is this a code?) BREAK 1 d1// image 52 (tiny 2) 24a1 24a3 24a8 24ad 24b2 24b7 24bc 24c1 24c6 24cb 24d0 24d5 24da 24df 24e4 24e9 24ee 24f3 24f8 24fd 2502 2507 BREAK 1 ce 2436//open chest 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 162 //single byte, 01 92e// 3 bytes 04 04 08 95b // 3 bytes b2 4f 02 // pointer to below BREAK 1 24fc2 // 6 bytes BREAK 1 ce 2436//chest again 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 24fc8//6 bytes BREAK 1 4b5 9ce2 //map dot? 9ce4 9ce6 9ce8 9cea 9cec 9cee 9cf0 9cf2 9cf4 9cf6 9cf8 9cfa 9cfc 9cfe 9d00 9d02 9d04 9d06 9d08 9d0a 9d0c 9d0e 9d10 9d12 9d14 9d16 9d18 9d1a 9d1c 9d1e 9d20 BREAK 1 24fce BREAK 1 24fd4 BREAK 1 24fda BREAK 1 24fe0 BREAK 1 24fe6 BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 24fec BREAK 1 4b5 9ce2 9ce4 9ce6 9ce8 9cea 9cec 9cee 9cf0 9cf2 9cf4 9cf6 9cf8 9cfa 9cfc 9cfe 9d00 9d02 9d04 9d06 9d08 9d0a 9d0c 9d0e 9d10 9d12 9d14 9d16 9d18 9d1a 9d1c 9d1e 9d20 BREAK 1 24ff2 BREAK 1 24ff8 BREAK 1 24ffe BREAK 1 25004 BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 2500a BREAK 1 4b5 9ce2 9ce4 9ce6 9ce8 9cea 9cec 9cee 9cf0 9cf2 9cf4 9cf6 9cf8 9cfa 9cfc 9cfe 9d00 9d02 9d04 9d06 9d08 9d0a 9d0c 9d0e 9d10 9d12 9d14 9d16 9d18 9d1a 9d1c 9d1e 9d20 BREAK 1 25010 BREAK 1 25016 BREAK 1 2501c BREAK 1 25022 BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 25028 BREAK 1 4b5 9ce2 9ce4 9ce6 9ce8 9cea 9cec 9cee 9cf0 9cf2 9cf4 9cf6 9cf8 9cfa 9cfc 9cfe 9d00 9d02 9d04 9d06 9d08 9d0a 9d0c 9d0e 9d10 9d12 9d14 9d16 9d18 9d1a 9d1c 9d1e 9d20 BREAK 1 2502e BREAK 1 25034 BREAK 1 2503a BREAK 1 25040 BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 25046 BREAK 1 4b5 9ce2 9ce4 9ce6 9ce8 9cea 9cec 9cee 9cf0 9cf2 9cf4 9cf6 9cf8 9cfa 9cfc 9cfe 9d00 9d02 9d04 9d06 9d08 9d0a 9d0c 9d0e 9d10 9d12 9d14 9d16 9d18 9d1a 9d1c 9d1e 9d20 BREAK 1 2504c BREAK 1 25052 BREAK 1 25058 BREAK 1 2505e BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 25064 BREAK 1 4b5 9ce2 9ce4 9ce6 9ce8 9cea 9cec 9cee 9cf0 9cf2 9cf4 9cf6 9cf8 9cfa 9cfc 9cfe 9d00 9d02 9d04 9d06 9d08 9d0a 9d0c 9d0e 9d10 9d12 9d14 9d16 9d18 9d1a 9d1c 9d1e 9d20 BREAK 1 2506a BREAK 1 25070 BREAK 1 25076 BREAK 1 2507c BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 25082 BREAK 1 4b5 9ce2 9ce4 9ce6 9ce8 9cea 9cec 9cee 9cf0 9cf2 9cf4 9cf6 9cf8 9cfa 9cfc 9cfe 9d00 9d02 9d04 9d06 9d08 9d0a 9d0c 9d0e 9d10 9d12 9d14 9d16 9d18 9d1a 9d1c 9d1e 9d20 BREAK 1 25088 BREAK 1 2508e BREAK 1 25094 BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 2509a BREAK 1 4b5 9ce2 9ce4 9ce6 9ce8 9cea 9cec 9cee 9cf0 9cf2 9cf4 9cf6 9cf8 9cfa 9cfc 9cfe 9d00 9d02 9d04 9d06 9d08 9d0a 9d0c 9d0e 9d10 9d12 9d14 9d16 9d18 9d1a 9d1c 9d1e 9d20 BREAK 1 250a0 BREAK 1 250a6 BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 250ac BREAK 1 4b5 9ce2 9ce4 9ce6 9ce8 9cea 9cec 9cee 9cf0 9cf2 9cf4 9cf6 9cf8 9cfa 9cfc 9cfe 9d00 9d02 9d04 9d06 9d08 9d0a 9d0c 9d0e 9d10 9d12 9d14 9d16 9d18 9d1a 9d1c 9d1e 9d20 BREAK 1 250b2 BREAK 1 250b8 BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 250be BREAK 1 4b5 9ce2 9ce4 9ce6 9ce8 9cea 9cec 9cee 9cf0 9cf2 9cf4 9cf6 9cf8 9cfa 9cfc 9cfe 9d00 9d02 9d04 9d06 9d08 9d0a 9d0c 9d0e 9d10 9d12 9d14 9d16 9d18 9d1a 9d1c 9d1e 9d20 BREAK 1 250c4 BREAK 1 250ca BREAK 1 250d0 BREAK 1 4f1 abec//3d tour abee abf6 abfa ac02 ac06 ac0e ac12 ac1a ac1e ac26 ac2a ac32 ac36 ac3e ac42 ac4a ac4e ac56 ac5a ac62 ac66 ac6e ac72 ac7a ac7e ac86 ac8a ac92 ac96 ac9e aca2 acaa acae acb6 acba acc2 acc6 acce acd2 acda acde ace6 acea acf2 acf6 acfe ad02 ad0a ad0e ad16 ad1a ad22 ad26 ad2e ad32 ad3a ad3e ad46 ad4a ad52 ad56 ad5e BREAK 1 250d6 BREAK 1 4f1 abec abee abf6 abfa ac02 ac06 ac0e ac12 ac1a ac1e ac26 ac2a ac32 ac36 ac3e ac42 ac4a ac4e ac56 ac5a ac62 ac66 ac6e ac72 ac7a ac7e ac86 ac8a ac92 ac96 ac9e aca2 acaa acae acb6 acba acc2 acc6 acce acd2 acda acde ace6 acea acf2 acf6 acfe ad02 ad0a ad0e ad16 ad1a ad22 ad26 ad2e ad32 ad3a ad3e ad46 ad4a ad52 ad56 ad5e BREAK 1 250dc BREAK 1 250e2 BREAK 1 4f1 abec abee abf6 abfa ac02 ac06 ac0e ac12 ac1a ac1e ac26 ac2a ac32 ac36 ac3e ac42 ac4a ac4e ac56 ac5a ac62 ac66 ac6e ac72 ac7a ac7e ac86 ac8a ac92 ac96 ac9e aca2 acaa acae acb6 acba acc2 acc6 acce acd2 acda acde ace6 acea acf2 acf6 acfe ad02 ad0a ad0e ad16 ad1a ad22 ad26 ad2e ad32 ad3a ad3e ad46 ad4a ad52 ad56 ad5e BREAK 1 250e8 BREAK 1 250ee BREAK 1 4f1 abec abee abf6 abfa ac02 ac06 ac0e ac12 ac1a ac1e ac26 ac2a ac32 ac36 ac3e ac42 ac4a ac4e ac56 ac5a ac62 ac66 ac6e ac72 ac7a ac7e ac86 ac8a ac92 ac96 ac9e aca2 acaa acae acb6 acba acc2 acc6 acce acd2 acda acde ace6 acea acf2 acf6 acfe ad02 ad0a ad0e ad16 ad1a ad22 ad26 ad2e ad32 ad3a ad3e ad46 ad4a ad52 ad56 ad5e BREAK 1 250f4 BREAK 1 250fa BREAK 1 4f1 abec abee abf6 abfa ac02 ac06 ac0e ac12 ac1a ac1e ac26 ac2a ac32 ac36 ac3e ac42 ac4a ac4e ac56 ac5a ac62 ac66 ac6e ac72 ac7a ac7e ac86 ac8a ac92 ac96 ac9e aca2 acaa acae acb6 acba acc2 acc6 acce acd2 acda acde ace6 acea acf2 acf6 acfe ad02 ad0a ad0e ad16 ad1a ad22 ad26 ad2e ad32 ad3a ad3e ad46 ad4a ad52 ad56 ad5e BREAK 1 25100 BREAK 1 25106 BREAK 1 4f1 abec abee abf6 abfa ac02 ac06 ac0e ac12 ac1a ac1e ac26 ac2a ac32 ac36 ac3e ac42 ac4a ac4e ac56 ac5a ac62 ac66 ac6e ac72 ac7a ac7e ac86 ac8a ac92 ac96 ac9e aca2 acaa acae acb6 acba acc2 acc6 acce acd2 acda acde ace6 acea acf2 acf6 acfe ad02 ad0a ad0e ad16 ad1a ad22 ad26 ad2e ad32 ad3a ad3e ad46 ad4a ad52 ad56 ad5e BREAK 1 2510c BREAK 1 25112 BREAK 1 4f1 abec abee abf6 abfa ac02 ac06 ac0e ac12 ac1a ac1e ac26 ac2a ac32 ac36 ac3e ac42 ac4a ac4e ac56 ac5a ac62 ac66 ac6e ac72 ac7a ac7e ac86 ac8a ac92 ac96 ac9e aca2 acaa acae acb6 acba acc2 acc6 acce acd2 acda acde ace6 acea acf2 acf6 acfe ad02 ad0a ad0e ad16 ad1a ad22 ad26 ad2e ad32 ad3a ad3e ad46 ad4a ad52 ad56 ad5e BREAK 1 25118 BREAK 1 2511e BREAK 1 4f1 abec abee abf6 abfa ac02 ac06 ac0e ac12 ac1a ac1e ac26 ac2a ac32 ac36 ac3e ac42 ac4a ac4e ac56 ac5a ac62 ac66 ac6e ac72 ac7a ac7e ac86 ac8a ac92 ac96 ac9e aca2 acaa acae acb6 acba acc2 acc6 acce acd2 acda acde ace6 acea acf2 acf6 acfe ad02 ad0a ad0e ad16 ad1a ad22 ad26 ad2e ad32 ad3a ad3e ad46 ad4a ad52 ad56 ad5e BREAK 1 25124 BREAK 1 2512a BREAK 1 4f1 abec abee abf6 abfa ac02 ac06 ac0e ac12 ac1a ac1e ac26 ac2a ac32 ac36 ac3e ac42 ac4a ac4e ac56 ac5a ac62 ac66 ac6e ac72 ac7a ac7e ac86 ac8a ac92 ac96 ac9e aca2 acaa acae acb6 acba acc2 acc6 acce acd2 acda acde ace6 acea acf2 acf6 acfe ad02 ad0a ad0e ad16 ad1a ad22 ad26 ad2e ad32 ad3a ad3e ad46 ad4a ad52 ad56 ad5e BREAK 1 25130 BREAK 1 25136 BREAK 1 2513c BREAK 1 4f1 abec abee abf6 abfa ac02 ac06 ac0e ac12 ac1a ac1e ac26 ac2a ac32 ac36 ac3e ac42 ac4a ac4e ac56 ac5a ac62 ac66 ac6e ac72 ac7a ac7e ac86 ac8a ac92 ac96 ac9e aca2 acaa acae acb6 acba acc2 acc6 acce acd2 acda acde ace6 acea acf2 acf6 acfe ad02 ad0a ad0e ad16 ad1a ad22 ad26 ad2e ad32 ad3a ad3e ad46 ad4a ad52 ad56 ad5e BREAK 1 25142 BREAK 1 25148 BREAK 1 4f1 abec abee abf6 abfa ac02 ac06 ac0e ac12 ac1a ac1e ac26 ac2a ac32 ac36 ac3e ac42 ac4a ac4e ac56 ac5a ac62 ac66 ac6e ac72 ac7a ac7e ac86 ac8a ac92 ac96 ac9e aca2 acaa acae acb6 acba acc2 acc6 acce acd2 acda acde ace6 acea acf2 acf6 acfe ad02 ad0a ad0e ad16 ad1a ad22 ad26 ad2e ad32 ad3a ad3e ad46 ad4a ad52 ad56 ad5e BREAK 1 2514e BREAK 1 25154 BREAK 1 2515a BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 25160 BREAK 1 25166 BREAK 1 2516c BREAK 1 25172 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 25178 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 2517e BREAK 1 25184 BREAK 1 2518a BREAK 1 25190 BREAK 1 25196 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 2519c BREAK 1 4fa af3a af54 af58 af5c af60 af64 af68 af6c af70 BREAK 1 251a2 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 251a8 BREAK 1 251ae BREAK 1 251b4 BREAK 1 251ba BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 251c0 BREAK 1 4fa af3a af3c af40 af44 af48 af4c af50 af54 af58 af5c af60 af64 af68 af6c af70 BREAK 1 251c6 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 251cc BREAK 1 251d2 BREAK 1 251d8 BREAK 1 251de BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 251e4 BREAK 1 4fd af74 af76 af7a af7e af82 af86 af8a af8e af92 af96 af9a af9e afa2 afa6 afaa BREAK 1 251ea BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 251f0 BREAK 1 251f6 BREAK 1 251fc BREAK 1 25202 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 25208 BREAK 1 2520e BREAK 1 4fd af74 af76 af7a af7e af82 af86 af8a af8e af92 af96 af9a af9e afa2 afa6 afaa BREAK 1 25214 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 2521a BREAK 1 25220 BREAK 1 25226 BREAK 1 2522c BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 25232 BREAK 1 25238 BREAK 1 500 afae afb0 afb4 afb8 afbc afc0 afc4 afc8 afcc afd0 afd4 afd8 afdc afe0 afe4 BREAK 1 2523e BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 25244 BREAK 1 2524a BREAK 1 25250 BREAK 1 25256 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 2525c BREAK 1 25262 BREAK 1 503 0 afe8 afea afee aff2 aff6 affa affe b002 b006 b00a b00e b012 b016 b01a b01e BREAK 1 25268 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 2526e BREAK 1 25274 BREAK 1 2527a BREAK 1 25280 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 25286 BREAK 1 2528c BREAK 1 506 b022 b024 b028 b02c b030 b034 b038 b03c b040 b044 b048 b04c b050 b054 b058 BREAK 1 25292 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 25298 BREAK 1 2529e BREAK 1 252a4 BREAK 1 252aa BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 252b0 BREAK 1 252b6 BREAK 1 509 b05c b05e b062 b066 b06a b06e b072 b076 b07a b07e b082 b086 b08a b08e b092 BREAK 1 252bc BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 252c2 BREAK 1 252c8 BREAK 1 252ce BREAK 1 252d4 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 252da BREAK 1 252e0 BREAK 1 50c b096 b098 b09c b0a0 b0a4 b0a8 b0ac b0b0 b0b4 b0b8 b0bc b0c0 b0c4 b0c8 b0cc BREAK 1 252e6 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 252ec BREAK 1 252f2 BREAK 1 252f8 BREAK 1 252fe BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 25304 BREAK 1 2530a BREAK 1 4fa af3a af3c af40 af44 af48 af4c af50 af54 af58 af5c af60 af64 af68 af6c af70 BREAK 1 25310 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 25316 BREAK 1 2531c BREAK 1 25322 BREAK 1 25328 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 2532e BREAK 1 25334 BREAK 1 500 afae afb0 afb4 afb8 afbc afc0 afc4 afc8 afcc afd0 afd4 afd8 afdc afe0 afe4 BREAK 1 2533a BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 25340 BREAK 1 25346 BREAK 1 2534c BREAK 1 25352 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 25358 BREAK 1 2535e BREAK 1 503 0 afe8 afea afee aff2 aff6 affa affe b002 b006 b00a b00e b012 b016 b01a b01e BREAK 1 25364 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 2536a BREAK 1 25370 BREAK 1 25376 BREAK 1 2537c BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 25382 BREAK 1 25388 BREAK 1 506 b022 b024 b028 b02c b030 b034 b038 b03c b040 b044 b048 b04c b050 b054 b058 BREAK 1 2538e BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 25394 BREAK 1 2539a BREAK 1 253a0 BREAK 1 253a6 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 253ac BREAK 1 253b2 BREAK 1 50f b0d0 b0d2 b0d6 b0da b0de b0e2 b0e6 b0ea b0ee b0f2 b0f6 b0fa b0fe b102 b106 BREAK 1 253b8 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 253be BREAK 1 253c4 BREAK 1 253ca BREAK 1 253d0 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 253d6 BREAK 1 253dc BREAK 1 512 b10a b10c b110 b114 b118 b11c b120 b124 b128 b12c b130 b134 b138 b13c b140 BREAK 1 253e2 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 253e8 BREAK 1 253ee BREAK 1 253f4 BREAK 1 253fa BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 25400 BREAK 1 25406 BREAK 1 50f b0d0 b0d2 b0d6 b0da b0de b0e2 b0e6 b0ea b0ee b0f2 b0f6 b0fa b0fe b102 b106 BREAK 1 2540c BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 25412 BREAK 1 25418 BREAK 1 2541e BREAK 1 25424 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 2542a BREAK 1 25430 BREAK 1 512 b10a b10c b110 b114 b118 b11c b120 b124 b128 b12c b130 b134 b138 b13c b140 BREAK 1 25436 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 2543c BREAK 1 25442 BREAK 1 25448 BREAK 1 2544e BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 25454 BREAK 1 2545a BREAK 1 50f b0d0 b0d2 b0d6 b0da b0de b0e2 b0e6 b0ea b0ee b0f2 b0f6 b0fa b0fe b102 b106 BREAK 1 25460 BREAK 1 25466 BREAK 1 515 b144 b146 b14e b152 b15a b15e b166 b16a b172 b176 b17e b182 b18a b18e b196 b19a b1a2 b1a6 b1ae b1b2 b1ba b1be b1c6 b1ca b1d2 b1d6 b1de b1e2 b1ea b1ee b1f6 b1fa b202 b206 b20e b212 b21a b21e b226 b22a b232 b236 b23e b242 b24a b24e b256 b25a b262 b266 b26e b272 b27a b27e b286 b28a b292 b296 b29e b2a2 b2aa b2ae b2b6 BREAK 1 2546c BREAK 1 25472 BREAK 1 512 b10a b10c b110 b114 b118 b11c b120 b124 b128 b12c b130 b134 b138 b13c b140 BREAK 1 25478 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 2547e BREAK 1 25484 BREAK 1 2548a BREAK 1 25490 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 25496 BREAK 1 2549c BREAK 1 50f b0d0 b0d2 b0d6 b0da b0de b0e2 b0e6 b0ea b0ee b0f2 b0f6 b0fa b0fe b102 b106 BREAK 1 254a2 BREAK 1 254a8 BREAK 1 515 b144 b146 b14e b152 b15a b15e b166 b16a b172 b176 b17e b182 b18a b18e b196 b19a b1a2 b1a6 b1ae b1b2 b1ba b1be b1c6 b1ca b1d2 b1d6 b1de b1e2 b1ea b1ee b1f6 b1fa b202 b206 b20e b212 b21a b21e b226 b22a b232 b236 b23e b242 b24a b24e b256 b25a b262 b266 b26e b272 b27a b27e b286 b28a b292 b296 b29e b2a2 b2aa b2ae b2b6 BREAK 1 254ae BREAK 1 512 b10a b10c b110 b114 b118 b11c b120 b124 b128 b12c b130 b134 b138 b13c b140 BREAK 1 254b4 BREAK 1 254ba BREAK 1 254c0 BREAK 1 254c6 BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 254cc 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 254d2 BREAK 1 254d8 BREAK 1 254de BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 254e4 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 254ea BREAK 1 254f0 BREAK 1 254f6 BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 254fc 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 25502 BREAK 1 25508 BREAK 1 2550e BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 25514 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 2551a BREAK 1 25520 BREAK 1 25526 BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 2552c 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 25532 BREAK 1 25538 BREAK 1 2553e BREAK 1 25544 BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 2554a 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 25550 BREAK 1 25556 BREAK 1 2555c BREAK 1 25562 BREAK 1 25568 BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 2556e 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 25574 BREAK 1 2557a BREAK 1 25580 BREAK 1 25586 BREAK 1 2558c BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 25592 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 25598 BREAK 1 2559e BREAK 1 255a4 BREAK 1 255aa BREAK 1 255b0 BREAK 1 255b6 BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 255bc 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 255c2 BREAK 1 255c8 BREAK 1 255ce BREAK 1 255d4 BREAK 1 255da BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 255e0 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 255e6 BREAK 1 255ec BREAK 1 255f2 BREAK 1 255f8 BREAK 1 255fe BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 25604 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 2560a BREAK 1 25610 BREAK 1 25616 BREAK 1 2561c BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 25622 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 25628 BREAK 1 2562e BREAK 1 25634 BREAK 1 2563a BREAK 1 25640 BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 25646 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 2564c BREAK 1 25652 BREAK 1 25658 BREAK 1 2565e BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 25664 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 2566a BREAK 1 25670 BREAK 1 25676 BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 2567c 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 25682 BREAK 1 25688 BREAK 1 2568e BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 25694 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 2569a BREAK 1 256a0 BREAK 1 256a6 BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 256ac 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 256b2 BREAK 1 256b8 BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 256be 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 256c4 BREAK 1 256ca BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 256d0 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 256d6 BREAK 1 256dc BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 256e2 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 256e8 BREAK 1 256ee BREAK 1 479 9188 918a 9190 30091 9196 30091 919c 30091 91a2 30091 91a8 30091 91ae 30091 91b4 30091 91ba 30091 91c0 30091 91c6 30091 91cc 30091 91d2 30091 91d8 30091 91de 30091 91e4 30091 91ea 30091 91f0 30091 91f6 30091 91fc 30092 9202 30092 9208 30092 920e 30092 9214 30092 921a 30092 9220 30092 9226 30092 922c 30092 9232 30092 9238 30092 923e 30000 BREAK 1 256f4 30000 BREAK 1 47c 9244 9246 924c 9252 9258 925e 9264 926a 9270 9276 927c 9282 9288 928e 9294 929a BREAK 1 256fa BREAK 1 25700 BREAK 1 482 92ee 92f0 92f8 9300 9308 9310 9318 9320 9328 9330 9338 c0008 9340 f00008 9348 8 9350 9358 9360 9368 9370 8 9378 8 9380 8 9388 8 9390 8 9398 8 93a0 8 93a8 8 93b0 c00008 93b8 93c0 93c8 93d0 93d8 93e0 BREAK 1 25706 BREAK 1 47f 92a0 92a2 92a6 92aa 92ae 92b2 92b6 92ba 92be 92c2 92c6 92ca 92ce 92d2 92d6 92da 92de 92e2 92e6 92ea BREAK 1 2570c BREAK 1 25712 BREAK 1 482 92ee 92f0 92f8 9300 9308 9310 9318 9320 9328 9330 9338 c0008 9340 f00008 9348 8 9350 9358 9360 9368 9370 8 9378 8 9380 8 9388 8 9390 8 9398 8 93a0 8 93a8 8 93b0 c00008 93b8 93c0 93c8 93d0 93d8 93e0 BREAK 1 25718 BREAK 1 47f 92a0 92a2 92a6 92aa 92ae 92b2 92b6 92ba 92be 92c2 92c6 92ca 92ce 92d2 92d6 92da 92de 92e2 92e6 92ea BREAK 1 2571e BREAK 1 25724 BREAK 1 482 92ee 92f0 92f8 9300 9308 9310 9318 9320 9328 9330 9338 c0008 9340 f00008 9348 8 9350 9358 9360 9368 9370 8 9378 8 9380 8 9388 8 9390 8 9398 8 93a0 8 93a8 8 93b0 c00008 93b8 93c0 93c8 93d0 93d8 93e0 BREAK 1 2572a BREAK 1 47f 92a0 92a2 92a6 92aa 92ae 92b2 92b6 92ba 92be 92c2 92c6 92ca 92ce 92d2 92d6 92da 92de 92e2 92e6 92ea BREAK 1 25730 BREAK 1 25736 BREAK 1 482 92ee 92f0 92f8 9300 9308 9310 9318 9320 9328 9330 9338 c0008 9340 f00008 9348 8 9350 9358 9360 9368 9370 8 9378 8 9380 8 9388 8 9390 8 9398 8 93a0 8 93a8 8 93b0 c00008 93b8 93c0 93c8 93d0 93d8 93e0 BREAK 1 2573c BREAK 1 47f 92a0 92a2 92a6 92aa 92ae 92b2 92b6 92ba 92be 92c2 92c6 92ca 92ce 92d2 92d6 92da 92de 92e2 92e6 92ea BREAK 1 25742 BREAK 1 25748 BREAK 1 491 97d0 97d2 97d3 97d4 97d5 97d6 97d7 97d8 BREAK 1 2574e BREAK 1 25754 BREAK 1 482 92ee 92f0 92f8 9300 9308 9310 9318 9320 9328 9330 9338 c0008 9340 f00008 9348 8 9350 9358 9360 9368 9370 8 9378 8 9380 8 9388 8 9390 8 9398 8 93a0 8 93a8 8 93b0 c00008 93b8 93c0 93c8 93d0 93d8 93e0 BREAK 1 2575a BREAK 1 47f 92a0 92a2 92a6 92aa 92ae 92b2 92b6 92ba 92be 92c2 92c6 92ca 92ce 92d2 92d6 92da 92de 92e2 92e6 92ea BREAK 1 25760 BREAK 1 25766 BREAK 1 494 97d9 97db 97dc 97dd 97de 97df 97e0 97e1 BREAK 1 2576c BREAK 1 25772 BREAK 1 482 92ee 92f0 92f8 9300 9308 9310 9318 9320 9328 9330 9338 c0008 9340 f00008 9348 8 9350 9358 9360 9368 9370 8 9378 8 9380 8 9388 8 9390 8 9398 8 93a0 8 93a8 8 93b0 c00008 93b8 93c0 93c8 93d0 93d8 93e0 BREAK 1 25778 BREAK 1 47f 92a0 92a2 92a6 92aa 92ae 92b2 92b6 92ba 92be 92c2 92c6 92ca 92ce 92d2 92d6 92da 92de 92e2 92e6 92ea BREAK 1 2577e BREAK 1 25784 BREAK 1 497 97e2 97e4 97e5 97e6 97e7 97e8 97e9 97ea BREAK 1 2578a BREAK 1 25790 BREAK 1 485 93e8 93ea 93f2 93fa 9402 940a 9412 941a 9422 942a 9432 c0008 943a f00008 9442 8 944a 9452 945a 9462 946a 8 9472 8 947a 8008 9482 a22808 948a 9492 949a 94a2 94aa 94b2 94ba 94c2 94ca 94d2 94da BREAK 1 25796 BREAK 1 47f 92a0 92a2 92a6 92aa 92ae 92b2 92b6 92ba 92be 92c2 92c6 92ca 92ce 92d2 92d6 92da 92de 92e2 92e6 92ea BREAK 1 2579c BREAK 1 257a2 BREAK 1 49a 97eb 97ed 97ee 97ef 97f0 97f1 97f2 97f3 BREAK 1 257a8 BREAK 1 257ae BREAK 1 488 94e2 94e4 94ec c0008 94f4 f00008 94fc 8 9504 950c 9514 951c 9524 8 952c 8 9534 8 953c 8 9544 8 954c 8 9554 8 955c 8 9564 c00008 956c 9574 957c 9584 958c 9594 959c 95a4 95ac 95b4 95bc 95c4 95cc 95d4 BREAK 1 257b4 BREAK 1 47f 92a0 92a2 92a6 92aa 92ae 92b2 92b6 92ba 92be 92c2 92c6 92ca 92ce 92d2 92d6 92da 92de 92e2 92e6 92ea BREAK 1 257ba BREAK 1 257c0 BREAK 1 48b 95dc 95de 95e6 8 95ee 8 95f6 8 95fe 8 9606 8 960e 8 9616 8 961e 8 9626 c00008 962e 9636 963e 9646 964e 9656 965e 9666 966e 9676 967e 9686 968e 9696 969e 96a6 96ae 96b6 96be 96c6 96ce BREAK 1 257c6 BREAK 1 47f 92a0 92a2 92a6 92aa 92ae 92b2 92b6 92ba 92be 92c2 92c6 92ca 92ce 92d2 92d6 92da 92de 92e2 92e6 92ea BREAK 1 257cc BREAK 1 257d2 BREAK 1 48e 96d6 96d8 96e0 96e8 96f0 96f8 9700 9708 9710 9718 9720 9728 9730 9738 9740 9748 9750 9758 9760 9768 9770 9778 9780 9788 9790 9798 97a0 97a8 97b0 97b8 97c0 97c8 BREAK 1 257d8 BREAK 1 47f 92a0 92a2 92a6 92aa 92ae 92b2 92b6 92ba 92be 92c2 92c6 92ca 92ce 92d2 92d6 92da 92de 92e2 92e6 92ea BREAK 1 257de BREAK 1 257e4 BREAK 1 47f 92a0 92a2 92a6 92aa 92ae 92b2 92b6 92ba 92be 92c2 92c6 92ca 92ce 92d2 92d6 92da 92de 92e2 92e6 92ea BREAK 1 257ea BREAK 1 257f0 BREAK 1 49d 97f4 97f6 97fe 9802 980a 980e 9816 981a 9822 9826 982e 9832 983a 983e 9846 984a 9852 9856 985e 9862 986a 986e 9876 987a 9882 9886 988e 9892 989a 989e 98a6 98aa 98b2 98b6 98be 98c2 98ca 98ce 98d6 98da 98e2 98e6 98ee 98f2 98fa 98fe 9906 990a 9912 9916 991e 9922 992a 992e 9936 993a 9942 9946 994e 9952 995a 995e 9966 BREAK 1 257f6 BREAK 1 49d 97f4 97f6 97fe 9802 980a 980e 9816 981a 9822 9826 982e 9832 983a 983e 9846 984a 9852 9856 985e 9862 986a 986e 9876 987a 9882 9886 988e 9892 989a 989e 98a6 98aa 98b2 98b6 98be 98c2 98ca 98ce 98d6 98da 98e2 98e6 98ee 98f2 98fa 98fe 9906 990a 9912 9916 991e 9922 992a 992e 9936 993a 9942 9946 994e 9952 995a 995e 9966 BREAK 1 257fc BREAK 1 4a3 9ae0 9ae5 3009a 9aea 9aef 9af4 9af9 9afe 9b03 0 BREAK 1 25802 BREAK 1 49d 97f4 97f6 97fe 9802 980a 980e 9816 981a 9822 9826 982e 9832 983a 983e 9846 984a 9852 9856 985e 9862 986a 986e 9876 987a 9882 9886 988e 9892 989a 989e 98a6 98aa 98b2 98b6 98be 98c2 98ca 98ce 98d6 98da 98e2 98e6 98ee 98f2 98fa 98fe 9906 990a 9912 9916 991e 9922 992a 992e 9936 993a 9942 9946 994e 9952 995a 995e 9966 BREAK 1 25808 BREAK 1 4a3 9ae0 9ae3 3009a 9ae8 9aed 9af2 9af7 9afc 9b01 BREAK 1 2580e BREAK 1 49d 97f4 97f6 97fe 9802 980a 980e 9816 981a 9822 9826 982e 9832 983a 983e 9846 984a 9852 9856 985e 9862 986a 986e 9876 987a 9882 9886 988e 9892 989a 989e 98a6 98aa 98b2 98b6 98be 98c2 98ca 98ce 98d6 98da 98e2 98e6 98ee 98f2 98fa 98fe 9906 990a 9912 9916 991e 9922 992a 992e 9936 993a 9942 9946 994e 9952 995a 995e 9966 BREAK 1 25814 BREAK 1 4a3 9ae0 9ae2 3009a 9ae7 9aec 9af1 9af6 9afb 9b00 BREAK 1 2581a BREAK 1 49d 97f4 97f6 97fe 9802 980a 980e 9816 981a 9822 9826 982e 9832 983a 983e 9846 984a 9852 9856 985e 9862 986a 986e 9876 987a 9882 9886 988e 9892 989a 989e 98a6 98aa 98b2 98b6 98be 98c2 98ca 98ce 98d6 98da 98e2 98e6 98ee 98f2 98fa 98fe 9906 990a 9912 9916 991e 9922 992a 992e 9936 993a 9942 9946 994e 9952 995a 995e 9966 BREAK 1 25820 BREAK 1 4a3 9ae0 9ae2 3009a 9ae7 9aec 9af1 9af6 9afb 9b00 BREAK 1 25826 BREAK 1 49d 97f4 97f6 97fe 9802 980a 980e 9816 981a 9822 9826 982e 9832 983a 983e 9846 984a 9852 9856 985e 9862 986a 986e 9876 987a 9882 9886 988e 9892 989a 989e 98a6 98aa 98b2 98b6 98be 98c2 98ca 98ce 98d6 98da 98e2 98e6 98ee 98f2 98fa 98fe 9906 990a 9912 9916 991e 9922 992a 992e 9936 993a 9942 9946 994e 9952 995a 995e 9966 BREAK 1 2582c BREAK 1 4a3 9ae0 9ae2 3009a 9ae7 9aec 9af1 9af6 9afb 9b00 BREAK 1 25832 BREAK 1 49d 97f4 97f6 97fe 9802 980a 980e 9816 981a 9822 9826 982e 9832 983a 983e 9846 984a 9852 9856 985e 9862 986a 986e 9876 987a 9882 9886 988e 9892 989a 989e 98a6 98aa 98b2 98b6 98be 98c2 98ca 98ce 98d6 98da 98e2 98e6 98ee 98f2 98fa 98fe 9906 990a 9912 9916 991e 9922 992a 992e 9936 993a 9942 9946 994e 9952 995a 995e 9966 BREAK 1 25838 BREAK 1 4a3 9ae0 9ae2 3009a 9ae7 9aec 9af1 9af6 9afb 9b00 BREAK 1 2583e BREAK 1 49d 97f4 97f6 97fe 9802 980a 980e 9816 981a 9822 9826 982e 9832 983a 983e 9846 984a 9852 9856 985e 9862 986a 986e 9876 987a 9882 9886 988e 9892 989a 989e 98a6 98aa 98b2 98b6 98be 98c2 98ca 98ce 98d6 98da 98e2 98e6 98ee 98f2 98fa 98fe 9906 990a 9912 9916 991e 9922 992a 992e 9936 993a 9942 9946 994e 9952 995a 995e 9966 BREAK 1 25844 BREAK 1 4a3 9ae0 9ae2 3009a 9ae7 9aec 9af1 9af6 9afb 9b00 BREAK 1 2584a BREAK 1 49d 97f4 97f6 97fe 9802 980a 980e 9816 981a 9822 9826 982e 9832 983a 983e 9846 984a 9852 9856 985e 9862 986a 986e 9876 987a 9882 9886 988e 9892 989a 989e 98a6 98aa 98b2 98b6 98be 98c2 98ca 98ce 98d6 98da 98e2 98e6 98ee 98f2 98fa 98fe 9906 990a 9912 9916 991e 9922 992a 992e 9936 993a 9942 9946 994e 9952 995a 995e 9966 BREAK 1 25850 BREAK 1 4a3 9ae0 9ae2 3009a 9ae7 9aec 9af1 9af6 9afb 9b00 BREAK 1 25856 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 2585c BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 25862 BREAK 1 4a6 9b05 9b09 9b0d 9b11 9b15 9b19 9b1d 9b21 BREAK 1 25868 100300 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 2586e BREAK 1 4a6 9b05 9b08 9b0c 9b10 9b14 9b18 9b1c 9b20 BREAK 1 25874 100300 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 2587a BREAK 1 4a6 9b05 9b07 9b0b 9b0f 9b13 9b17 9b1b 9b1f BREAK 1 25880 100300 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 25886 BREAK 1 4a6 9b05 9b07 9b0b 9b0f 9b13 9b17 9b1b 9b1f BREAK 1 2588c 100300 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 25892 BREAK 1 4a6 9b05 9b07 9b0b 9b0f 9b13 9b17 9b1b 9b1f BREAK 1 25898 100300 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 2589e BREAK 1 4a6 9b05 9b07 9b0b 9b0f 9b13 9b17 9b1b 9b1f BREAK 1 258a4 100300 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 258aa BREAK 1 4a6 9b05 9b07 9b0b 9b0f 9b13 9b17 9b1b 9b1f BREAK 1 258b0 190300 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 258b6 BREAK 1 4a6 9b05 9b07 9b0b 9b0f 9b13 9b17 9b1b 9b1f BREAK 1 258bc 260300 BREAK 1 258c2 BREAK 1 4af 9b66 9b68 9b70 9b74 9b7c 9b80 9b88 9b8c 9b94 9b98 9ba0 9ba4 9bac 9bb0 9bb8 9bbc 9bc4 9bc8 9bd0 9bd4 9bdc 9be0 9be8 9bec 9bf4 9bf8 9c00 9c04 9c0c 9c10 9c18 9c1c 9c24 9c28 9c30 9c34 9c3c 9c40 9c48 9c4c 9c54 9c58 9c60 9c64 9c6c 9c70 9c78 9c7c 9c84 9c88 9c90 9c94 9c9c 9ca0 9ca8 9cac 9cb4 9cb8 9cc0 9cc4 9ccc 9cd0 9cd8 BREAK 1 258c8 BREAK 1 4af 9b66 9b68 9b70 9b74 9b7c 9b80 9b88 9b8c 9b94 9b98 9ba0 9ba4 9bac 9bb0 9bb8 9bbc 9bc4 9bc8 9bd0 9bd4 9bdc 9be0 9be8 9bec 9bf4 9bf8 9c00 9c04 9c0c 9c10 9c18 9c1c 9c24 9c28 9c30 9c34 9c3c 9c40 9c48 9c4c 9c54 9c58 9c60 9c64 9c6c 9c70 9c78 9c7c 9c84 9c88 9c90 9c94 9c9c 9ca0 9ca8 9cac 9cb4 9cb8 9cc0 9cc4 9ccc 9cd0 9cd8 BREAK 1 258ce BREAK 1 258d4 BREAK 1 4b2 9cdc 9cde 9cdf 9ce0 9ce1 BREAK 1 258da BREAK 1 4af 9b66 9b68 9b70 9b74 9b7c 9b80 9b88 9b8c 9b94 9b98 9ba0 9ba4 9bac 9bb0 9bb8 9bbc 9bc4 9bc8 9bd0 9bd4 9bdc 9be0 9be8 9bec 9bf4 9bf8 9c00 9c04 9c0c 9c10 9c18 9c1c 9c24 9c28 9c30 9c34 9c3c 9c40 9c48 9c4c 9c54 9c58 9c60 9c64 9c6c 9c70 9c78 9c7c 9c84 9c88 9c90 9c94 9c9c 9ca0 9ca8 9cac 9cb4 9cb8 9cc0 9cc4 9ccc 9cd0 9cd8 BREAK 1 258e0 BREAK 1 4af 9b66 9b68 9b70 9b74 9b7c 9b80 9b88 9b8c 9b94 9b98 9ba0 9ba4 9bac 9bb0 9bb8 9bbc 9bc4 9bc8 9bd0 9bd4 9bdc 9be0 9be8 9bec 9bf4 9bf8 9c00 9c04 9c0c 9c10 9c18 9c1c 9c24 9c28 9c30 9c34 9c3c 9c40 9c48 9c4c 9c54 9c58 9c60 9c64 9c6c 9c70 9c78 9c7c 9c84 9c88 9c90 9c94 9c9c 9ca0 9ca8 9cac 9cb4 9cb8 9cc0 9cc4 9ccc 9cd0 9cd8 BREAK 1 258e6 BREAK 1 258ec BREAK 1 4b2 9cdc 9cde 9cdf 9ce0 9ce1 BREAK 1 258f2 BREAK 1 4af 9b66 9b68 9b70 9b74 9b7c 9b80 9b88 9b8c 9b94 9b98 9ba0 9ba4 9bac 9bb0 9bb8 9bbc 9bc4 9bc8 9bd0 9bd4 9bdc 9be0 9be8 9bec 9bf4 9bf8 9c00 9c04 9c0c 9c10 9c18 9c1c 9c24 9c28 9c30 9c34 9c3c 9c40 9c48 9c4c 9c54 9c58 9c60 9c64 9c6c 9c70 9c78 9c7c 9c84 9c88 9c90 9c94 9c9c 9ca0 9ca8 9cac 9cb4 9cb8 9cc0 9cc4 9ccc 9cd0 9cd8 BREAK 1 258f8 BREAK 1 4af 9b66 9b68 9b70 9b74 9b7c 9b80 9b88 9b8c 9b94 9b98 9ba0 9ba4 9bac 9bb0 9bb8 9bbc 9bc4 9bc8 9bd0 9bd4 9bdc 9be0 9be8 9bec 9bf4 9bf8 9c00 9c04 9c0c 9c10 9c18 9c1c 9c24 9c28 9c30 9c34 9c3c 9c40 9c48 9c4c 9c54 9c58 9c60 9c64 9c6c 9c70 9c78 9c7c 9c84 9c88 9c90 9c94 9c9c 9ca0 9ca8 9cac 9cb4 9cb8 9cc0 9cc4 9ccc 9cd0 9cd8 BREAK 1 258fe BREAK 1 25904 BREAK 1 4b2 9cdc 9cde 9cdf 9ce0 9ce1 BREAK 1 2590a BREAK 1 25910 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25916 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 2591c BREAK 1 25922 BREAK 1 25928 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 2592e BREAK 1 25934 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 2593a BREAK 1 25940 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25946 BREAK 1 2594c BREAK 1 25952 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25958 BREAK 1 2595e BREAK 1 25964 BREAK 1 2596a BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25970 BREAK 1 25976 BREAK 1 2597c BREAK 1 25982 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25988 BREAK 1 2598e BREAK 1 25994 BREAK 1 2599a BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 259a0 BREAK 1 259a6 BREAK 1 259ac BREAK 1 259b2 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 259b8 BREAK 1 259be BREAK 1 259c4 BREAK 1 259ca BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 259d0 BREAK 1 259d6 BREAK 1 259dc BREAK 1 259e2 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 259e8 BREAK 1 259ee BREAK 1 259f4 BREAK 1 259fa BREAK 1 25a00 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25a06 BREAK 1 25a0c BREAK 1 25a12 BREAK 1 25a18 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25a1e BREAK 1 25a24 BREAK 1 25a2a BREAK 1 25a30 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25a36 BREAK 1 25a3c BREAK 1 25a42 BREAK 1 25a48 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25a4e BREAK 1 25a54 BREAK 1 25a5a BREAK 1 25a60 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25a66 BREAK 1 25a6c BREAK 1 25a72 BREAK 1 25a78 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25a7e BREAK 1 25a84 BREAK 1 25a8a BREAK 1 25a90 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25a96 BREAK 1 25a9c BREAK 1 25aa2 BREAK 1 25aa8 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25aae BREAK 1 25ab4 BREAK 1 25aba BREAK 1 25ac0 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25ac6 BREAK 1 25acc BREAK 1 25ad2 BREAK 1 25ad8 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25ade BREAK 1 25ae4 BREAK 1 25aea BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25af0 BREAK 1 25af6 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25afc BREAK 1 25b02 BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25b08 BREAK 1 25b0e BREAK 1 4d9 a48c a48e a496 a49a a4a2 a4a6 a4ae a4b2 a4ba a4be a4c6 a4ca a4d2 a4d6 a4de a4e2 a4ea a4ee a4f6 a4fa a502 a506 a50e a512 a51a a51e a526 a52a a532 a536 a53e a542 a54a a54e a556 a55a a562 a566 a56e a572 a57a a57e a586 a58a a592 a596 a59e a5a2 a5aa a5ae a5b6 a5ba a5c2 a5c6 a5ce a5d2 a5da a5de a5e6 a5ea a5f2 a5f6 a5fe BREAK 1 25b14 BREAK 1 25b1a BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25b20 BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25b26 BREAK 1 25b2c BREAK 1 25b32 BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25b38 BREAK 1 25b3e BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25b44 BREAK 1 25b4a BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25b50 BREAK 1 25b56 BREAK 1 25b5c BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25b62 BREAK 1 25b68 BREAK 1 25b6e BREAK 1 25b74 BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25b7a BREAK 1 25b80 BREAK 1 25b86 BREAK 1 25b8c BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25b92 BREAK 1 25b98 BREAK 1 25b9e BREAK 1 25ba4 BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25baa BREAK 1 25bb0 BREAK 1 25bb6 BREAK 1 25bbc BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25bc2 BREAK 1 25bc8 BREAK 1 25bce BREAK 1 25bd4 BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25bda BREAK 1 25be0 BREAK 1 25be6 BREAK 1 25bec BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25bf2 BREAK 1 25bf8 BREAK 1 25bfe BREAK 1 25c04 BREAK 1 25c0a BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25c10 BREAK 1 25c16 BREAK 1 25c1c BREAK 1 25c22 BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25c28 BREAK 1 25c2e BREAK 1 25c34 BREAK 1 25c3a BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25c40 BREAK 1 25c46 BREAK 1 25c4c BREAK 1 25c52 BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25c58 BREAK 1 25c5e BREAK 1 25c64 BREAK 1 25c6a BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25c70 BREAK 1 25c76 BREAK 1 25c7c BREAK 1 25c82 BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25c88 BREAK 1 25c8e BREAK 1 25c94 BREAK 1 25c9a BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25ca0 BREAK 1 25ca6 BREAK 1 25cac BREAK 1 25cb2 BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25cb8 BREAK 1 25cbe BREAK 1 25cc4 BREAK 1 25cca BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25cd0 BREAK 1 25cd6 BREAK 1 25cdc BREAK 1 25ce2 BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25ce8 BREAK 1 25cee BREAK 1 25cf4 BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25cfa BREAK 1 25d00 BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25d06 BREAK 1 25d0c BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25d12 BREAK 1 25d18 BREAK 1 4dc a602 a604 a60c a610 a618 a61c a624 a628 a630 a634 a63c a640 a648 a64c a654 a658 a660 a664 a66c a670 a678 a67c a684 a688 a690 a694 a69c a6a0 a6a8 a6ac a6b4 a6b8 a6c0 a6c4 a6cc a6d0 a6d8 a6dc a6e4 a6e8 a6f0 a6f4 a6fc a700 a708 a70c a714 a718 a720 a724 a72c a730 a738 a73c a744 a748 a750 a754 a75c a760 a768 a76c a774 BREAK 1 25d1e BREAK 1 25d24 BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25d2a BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25d30 BREAK 1 25d36 BREAK 1 25d3c BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25d42 BREAK 1 25d48 BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25d4e BREAK 1 25d54 BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25d5a BREAK 1 25d60 BREAK 1 25d66 BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25d6c BREAK 1 25d72 BREAK 1 25d78 BREAK 1 25d7e BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25d84 BREAK 1 25d8a BREAK 1 25d90 BREAK 1 25d96 BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25d9c BREAK 1 25da2 BREAK 1 25da8 BREAK 1 25dae BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25db4 BREAK 1 25dba BREAK 1 25dc0 BREAK 1 25dc6 BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25dcc BREAK 1 25dd2 BREAK 1 25dd8 BREAK 1 25dde BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25de4 BREAK 1 25dea BREAK 1 25df0 BREAK 1 25df6 BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25dfc BREAK 1 25e02 BREAK 1 25e08 BREAK 1 25e0e BREAK 1 25e14 BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25e1a BREAK 1 25e20 BREAK 1 25e26 BREAK 1 25e2c BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25e32 BREAK 1 25e38 BREAK 1 25e3e BREAK 1 25e44 BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25e4a BREAK 1 25e50 BREAK 1 25e56 BREAK 1 25e5c BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25e62 BREAK 1 25e68 BREAK 1 25e6e BREAK 1 25e74 BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25e7a BREAK 1 25e80 BREAK 1 25e86 BREAK 1 25e8c BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25e92 BREAK 1 25e98 BREAK 1 25e9e BREAK 1 25ea4 BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25eaa BREAK 1 25eb0 BREAK 1 25eb6 BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25ebc BREAK 1 25ec2 BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25ec8 BREAK 1 25ece BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25ed4 BREAK 1 25eda BREAK 1 4df a778 a77a a782 a786 a78e a792 a79a a79e a7a6 a7aa a7b2 a7b6 a7be a7c2 a7ca a7ce a7d6 a7da a7e2 a7e6 a7ee a7f2 a7fa a7fe a806 a80a a812 a816 a81e a822 a82a a82e a836 a83a a842 a846 a84e a852 a85a a85e a866 a86a a872 a876 a87e a882 a88a a88e a896 a89a a8a2 a8a6 a8ae a8b2 a8ba a8be a8c6 a8ca a8d2 a8d6 a8de a8e2 a8ea BREAK 1 25ee0 BREAK 1 25ee6 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 25eec BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 25ef2 BREAK 1 25ef8 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 25efe BREAK 1 25f04 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 25f0a BREAK 1 25f10 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 25f16 BREAK 1 25f1c BREAK 1 25f22 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 25f28 BREAK 1 25f2e BREAK 1 25f34 BREAK 1 25f3a BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 25f40 BREAK 1 25f46 BREAK 1 25f4c BREAK 1 25f52 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 25f58 BREAK 1 25f5e BREAK 1 25f64 BREAK 1 25f6a BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 25f70 BREAK 1 25f76 BREAK 1 25f7c BREAK 1 25f82 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 25f88 BREAK 1 25f8e BREAK 1 25f94 BREAK 1 25f9a BREAK 1 4e5 aa64 aa67 aa6f aa73 aa7b aa7f aa87 aa8b aa93 aa97 aa9f aaa3 aaab aaaf aab7 aabb aac3 aac7 aacf aad3 aadb aadf aae7 aaeb aaf3 aaf7 aaff ab03 0 ab0b ab0f ab17 ab1b ab23 ab27 ab2f ab33 ab3b ab3f ab47 ab4b ab53 ab57 ab5f ab63 ab6b ab6f ab77 ab7b ab83 ab87 ab8f ab93 ab9b ab9f aba7 abab abb3 abb7 abbf abc3 abcb abcf abd7 BREAK 1 25fa0 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 25fa6 BREAK 1 25fac BREAK 1 25fb2 BREAK 1 25fb8 BREAK 1 4e5 aa64 aa68 aa70 aa74 aa7c aa80 aa88 aa8c aa94 aa98 aaa0 aaa4 aaac aab0 aab8 aabc aac4 aac8 aad0 aad4 aadc aae0 aae8 aaec aaf4 aaf8 ab00 ab04 ab0c ab10 ab18 ab1c ab24 ab28 ab30 ab34 ab3c ab40 ab48 ab4c ab54 ab58 ab60 ab64 ab6c ab70 ab78 ab7c ab84 ab88 ab90 ab94 ab9c aba0 aba8 abac abb4 abb8 abc0 abc4 abcc abd0 abd8 BREAK 1 25fbe BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 25fc4 BREAK 1 25fca BREAK 1 25fd0 BREAK 1 25fd6 BREAK 1 4e5 aa64 aa69 aa71 aa75 aa7d aa81 aa89 aa8d aa95 aa99 aaa1 aaa5 aaad aab1 aab9 aabd aac5 aac9 aad1 aad5 aadd aae1 aae9 aaed aaf5 aaf9 ab01 ab05 ab0d ab11 ab19 ab1d ab25 ab29 ab31 ab35 ab3d ab41 ab49 ab4d ab55 ab59 ab61 ab65 ab6d ab71 ab79 ab7d ab85 ab89 ab91 ab95 ab9d aba1 aba9 abad abb5 abb9 abc1 abc5 abcd abd1 abd9 BREAK 1 25fdc BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 25fe2 BREAK 1 25fe8 BREAK 1 25fee BREAK 1 25ff4 BREAK 1 4e5 aa64 aa6a aa72 aa76 aa7e aa82 aa8a aa8e aa96 aa9a aaa2 aaa6 aaae aab2 aaba aabe aac6 aaca aad2 aad6 aade aae2 aaea aaee aaf6 aafa ab02 ab06 ab0e ab12 ab1a ab1e ab26 ab2a ab32 ab36 ab3e ab42 ab4a ab4e ab56 ab5a ab62 ab66 ab6e ab72 ab7a ab7e ab86 ab8a ab92 ab96 ab9e aba2 abaa abae abb6 abba abc2 abc6 abce abd2 abda BREAK 1 25ffa BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 26000 BREAK 1 26006 BREAK 1 2600c BREAK 1 26012 BREAK 1 4e5 aa64 aa6b aa73 aa77 aa7f aa83 aa8b aa8f aa97 aa9b aaa3 aaa7 aaaf aab3 aabb aabf aac7 aacb aad3 aad7 aadf aae3 aaeb aaef aaf7 aafb ab03 0 ab07 ab0f ab13 ab1b ab1f ab27 ab2b ab33 ab37 ab3f ab43 ab4b ab4f ab57 ab5b ab63 ab67 ab6f ab73 ab7b ab7f ab87 ab8b ab93 ab97 ab9f aba3 abab abaf abb7 abbb abc3 abc7 abcf abd3 abdb BREAK 1 26018 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 2601e BREAK 1 26024 BREAK 1 2602a BREAK 1 26030 BREAK 1 4e5 aa64 aa6c aa74 aa78 aa80 aa84 aa8c aa90 aa98 aa9c aaa4 aaa8 aab0 aab4 aabc aac0 aac8 aacc aad4 aad8 aae0 aae4 aaec aaf0 aaf8 aafc ab04 ab08 ab10 ab14 ab1c ab20 ab28 ab2c ab34 ab38 ab40 ab44 ab4c ab50 ab58 ab5c ab64 ab68 ab70 ab74 ab7c ab80 ab88 ab8c ab94 ab98 aba0 aba4 abac abb0 abb8 abbc abc4 abc8 abd0 abd4 abdc BREAK 1 26036 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 2603c BREAK 1 26042 BREAK 1 26048 BREAK 1 2604e BREAK 1 4e5 aa64 aa6d aa75 aa79 aa81 aa85 aa8d aa91 aa99 aa9d aaa5 aaa9 aab1 aab5 aabd aac1 aac9 aacd aad5 aad9 aae1 aae5 aaed aaf1 aaf9 aafd ab05 ab09 ab11 ab15 ab1d ab21 ab29 ab2d ab35 ab39 ab41 ab45 ab4d ab51 ab59 ab5d ab65 ab69 ab71 ab75 ab7d ab81 ab89 ab8d ab95 ab99 aba1 aba5 abad abb1 abb9 abbd abc5 abc9 abd1 abd5 abdd BREAK 1 26054 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 2605a BREAK 1 26060 BREAK 1 26066 BREAK 1 2606c BREAK 1 4e5 aa64 aa6e aa76 aa7a aa82 aa86 aa8e aa92 aa9a aa9e aaa6 aaaa aab2 aab6 aabe aac2 aaca aace aad6 aada aae2 aae6 aaee aaf2 aafa aafe ab06 ab0a ab12 ab16 ab1e ab22 ab2a ab2e ab36 ab3a ab42 ab46 ab4e ab52 ab5a ab5e ab66 ab6a ab72 ab76 ab7e ab82 ab8a ab8e ab96 ab9a aba2 aba6 abae abb2 abba abbe abc6 abca abd2 abd6 abde BREAK 1 26072 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 26078 BREAK 1 2607e BREAK 1 26084 BREAK 1 2608a BREAK 1 4e5 aa64 aa6f aa77 aa7b aa83 aa87 aa8f aa93 aa9b aa9f aaa7 aaab aab3 aab7 aabf aac3 aacb aacf aad7 aadb aae3 aae7 aaef aaf3 aafb aaff ab07 ab0b ab13 ab17 ab1f ab23 ab2b ab2f ab37 ab3b ab43 ab47 ab4f ab53 ab5b ab5f ab67 ab6b ab73 ab77 ab7f ab83 ab8b ab8f ab97 ab9b aba3 aba7 abaf abb3 abbb abbf abc7 abcb abd3 abd7 abdf BREAK 1 26090 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 26096 BREAK 1 2609c BREAK 1 260a2 BREAK 1 260a8 BREAK 1 4e5 aa64 aa70 aa78 aa7c aa84 aa88 aa90 aa94 aa9c aaa0 aaa8 aaac aab4 aab8 aac0 aac4 aacc aad0 aad8 aadc aae4 aae8 aaf0 aaf4 aafc ab00 ab08 ab0c ab14 ab18 ab20 ab24 ab2c ab30 ab38 ab3c ab44 ab48 ab50 ab54 ab5c ab60 ab68 ab6c ab74 ab78 ab80 ab84 ab8c ab90 ab98 ab9c aba4 aba8 abb0 abb4 abbc abc0 abc8 abcc abd4 abd8 abe0 BREAK 1 260ae BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 260b4 BREAK 1 260ba BREAK 1 260c0 BREAK 1 260c6 BREAK 1 4e5 aa64 aa71 aa79 aa7d aa85 aa89 aa91 aa95 aa9d aaa1 aaa9 aaad aab5 aab9 aac1 aac5 aacd aad1 aad9 aadd aae5 aae9 aaf1 aaf5 aafd ab01 ab09 ab0d ab15 ab19 ab21 ab25 ab2d ab31 ab39 ab3d ab45 ab49 ab51 ab55 ab5d ab61 ab69 ab6d ab75 ab79 ab81 ab85 ab8d ab91 ab99 ab9d aba5 aba9 abb1 abb5 abbd abc1 abc9 abcd abd5 abd9 abe1 BREAK 1 260cc BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 260d2 BREAK 1 260d8 BREAK 1 260de BREAK 1 260e4 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 260ea BREAK 1 260f0 BREAK 1 260f6 BREAK 1 260fc BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 26102 BREAK 1 26108 BREAK 1 2610e BREAK 1 26114 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 2611a BREAK 1 26120 BREAK 1 26126 BREAK 1 2612c BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 26132 BREAK 1 26138 BREAK 1 2613e BREAK 1 26144 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 2614a BREAK 1 26150 BREAK 1 26156 BREAK 1 2615c BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 26162 BREAK 1 26168 BREAK 1 2616e BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 26174 BREAK 1 2617a BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 26180 BREAK 1 26186 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 2618c BREAK 1 26192 BREAK 1 4e5 aa64 aa66 aa6e aa72 aa7a aa7e aa86 aa8a aa92 aa96 aa9e aaa2 aaaa aaae aab6 aaba aac2 aac6 aace aad2 aada aade aae6 aaea aaf2 aaf6 aafe ab02 ab0a ab0e ab16 ab1a ab22 ab26 ab2e ab32 ab3a ab3e ab46 ab4a ab52 ab56 ab5e ab62 ab6a ab6e ab76 ab7a ab82 ab86 ab8e ab92 ab9a ab9e aba6 abaa abb2 abb6 abbe abc2 abca abce abd6 BREAK 1 26198 BREAK 1 2619e BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 261a4 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 261aa BREAK 1 261b0 BREAK 1 261b6 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 261bc BREAK 1 261c2 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 261c8 BREAK 1 261ce BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 261d4 BREAK 1 261da BREAK 1 261e0 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 261e6 BREAK 1 261ec BREAK 1 261f2 BREAK 1 261f8 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 261fe BREAK 1 26204 BREAK 1 2620a BREAK 1 26210 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 26216 BREAK 1 2621c BREAK 1 26222 BREAK 1 26228 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 2622e BREAK 1 26234 BREAK 1 2623a BREAK 1 26240 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 26246 BREAK 1 2624c BREAK 1 26252 BREAK 1 26258 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 2625e BREAK 1 26264 BREAK 1 2626a BREAK 1 26270 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 26276 BREAK 1 2627c BREAK 1 26282 BREAK 1 26288 BREAK 1 2628e BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 26294 BREAK 1 2629a BREAK 1 262a0 BREAK 1 262a6 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 262ac BREAK 1 262b2 BREAK 1 262b8 BREAK 1 262be BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 262c4 BREAK 1 262ca BREAK 1 262d0 BREAK 1 262d6 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 262dc BREAK 1 262e2 BREAK 1 262e8 BREAK 1 262ee BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 262f4 BREAK 1 262fa BREAK 1 26300 BREAK 1 26306 BREAK 1 2630c BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 26312 BREAK 1 26318 BREAK 1 2631e BREAK 1 26324 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 2632a BREAK 1 26330 BREAK 1 26336 BREAK 1 2633c BREAK 1 26342 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 26348 BREAK 1 2634e BREAK 1 26354 BREAK 1 2635a BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 26360 BREAK 1 26366 BREAK 1 2636c BREAK 1 26372 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 26378 BREAK 1 2637e BREAK 1 26384 BREAK 1 2638a BREAK 1 26390 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 26396 BREAK 1 2639c BREAK 1 263a2 BREAK 1 263a8 BREAK 1 4e2 a8ee a8f0 a8f8 a8fc a904 a908 a910 a914 a91c a920 a928 a92c a934 a938 a940 a944 a94c a950 a958 a95c a964 a968 a970 a974 a97c a980 a988 a98c a994 a998 a9a0 a9a4 a9ac a9b0 a9b8 a9bc a9c4 a9c8 a9d0 a9d4 a9dc a9e0 a9e8 a9ec a9f4 a9f8 aa00 aa04 aa0c aa10 aa18 aa1c aa24 aa28 aa30 aa34 aa3c aa40 aa48 aa4c aa54 aa58 aa60 BREAK 1 263ae BREAK 1 263b4 BREAK 1 263ba BREAK 1 263c0 BREAK 1 263c6 BREAK 1 263cc BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 263d2 BREAK 1 4a9 9b23 9b25 9b29 9b2d 9b31 9b35 9b39 9b3d BREAK 1 263d8 200300 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 263de BREAK 1 4a9 9b23 9b25 9b29 9b2d 9b31 9b35 9b39 9b3d BREAK 1 263e4 100300 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 263ea BREAK 1 4a9 9b23 9b25 9b29 9b2d 9b31 9b35 9b39 9b3d BREAK 1 263f0 100300 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 263f6 BREAK 1 4a9 9b23 9b25 9b29 9b2d 9b31 9b35 9b39 9b3d BREAK 1 263fc 100300 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 26402 BREAK 1 4ac 9b41 9b43 3009b 9b48 9b4d 9b52 9b57 9b5c 9b61 BREAK 1 26408 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 2640e BREAK 1 4ac 9b41 9b43 3009b 9b48 9b4d 9b52 9b57 9b5c 9b61 BREAK 1 26414 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 2641a BREAK 1 4ac 9b41 9b43 3009b 9b48 9b4d 9b52 9b57 9b5c 9b61 BREAK 1 26420 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 26426 BREAK 1 4ac 9b41 9b44 3009b 9b49 9b4e 9b53 9b58 9b5d 9b62 BREAK 1 2642c BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 26432 BREAK 1 4ac 9b41 9b45 3009b 9b4a 9b4f 9b54 9b59 9b5e 9b63 BREAK 1 26438 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 2643e BREAK 1 4ac 9b41 9b47 3009b 9b4c 9b51 9b56 9b5b 9b60 9b65 BREAK 1 26444 BREAK 1 4a0 996a 996c 9974 9978 9980 9984 998c 9990 9998 999c 99a4 99a8 99b0 99b4 99bc 99c0 99c8 99cc 99d4 99d8 99e0 99e4 99ec 99f0 99f8 99fc 9a04 9a08 9a10 9a14 9a1c 9a20 9a28 9a2c 9a34 9a38 9a40 9a44 9a4c 9a50 9a58 9a5c 9a64 9a68 9a70 9a74 9a7c 9a80 9a88 9a8c 9a94 9a98 9aa0 9aa4 9aac 9ab0 9ab8 9abc 9ac4 9ac8 9ad0 9ad4 9adc BREAK 1 2644a BREAK 1 26450 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 26456 BREAK 1 2645c BREAK 1 26462 BREAK 1 26468 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 2646e BREAK 1 26474 BREAK 1 50f b0d0 b0d2 b0d6 b0da b0de b0e2 b0e6 b0ea b0ee b0f2 b0f6 b0fa b0fe b102 b106 BREAK 1 2647a BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 26480 BREAK 1 26486 BREAK 1 2648c BREAK 1 26492 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 26498 BREAK 1 2649e BREAK 1 512 b10a b10c b110 b114 b118 b11c b120 b124 b128 b12c b130 b134 b138 b13c b140 BREAK 1 264a4 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 264aa BREAK 1 264b0 BREAK 1 264b6 BREAK 1 264bc BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 264c2 BREAK 1 264c8 BREAK 1 50f b0d0 b0d2 b0d6 b0da b0de b0e2 b0e6 b0ea b0ee b0f2 b0f6 b0fa b0fe b102 b106 BREAK 1 264ce BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 264d4 BREAK 1 264da BREAK 1 264e0 BREAK 1 264e6 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 264ec BREAK 1 264f2 BREAK 1 512 b10a b10c b110 b114 b118 b11c b120 b124 b128 b12c b130 b134 b138 b13c b140 BREAK 1 264f8 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 264fe BREAK 1 26504 BREAK 1 2650a BREAK 1 26510 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 26516 BREAK 1 2651c BREAK 1 500 afae afb0 afb4 afb8 afbc afc0 afc4 afc8 afcc afd0 afd4 afd8 afdc afe0 afe4 BREAK 1 26522 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 26528 BREAK 1 2652e BREAK 1 26534 BREAK 1 2653a BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 26540 BREAK 1 26546 BREAK 1 503 0 afe8 afea afee aff2 aff6 affa affe b002 b006 b00a b00e b012 b016 b01a b01e BREAK 1 2654c BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 26552 BREAK 1 26558 BREAK 1 2655e BREAK 1 26564 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 2656a BREAK 1 26570 BREAK 1 506 b022 b024 b028 b02c b030 b034 b038 b03c b040 b044 b048 b04c b050 b054 b058 BREAK 1 26576 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 2657c BREAK 1 26582 BREAK 1 26588 BREAK 1 2658e BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 26594 BREAK 1 2659a BREAK 1 509 b05c b05e b062 b066 b06a b06e b072 b076 b07a b07e b082 b086 b08a b08e b092 BREAK 1 265a0 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 265a6 BREAK 1 265ac BREAK 1 265b2 BREAK 1 265b8 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 265be BREAK 1 265c4 BREAK 1 50c b096 b098 b09c b0a0 b0a4 b0a8 b0ac b0b0 b0b4 b0b8 b0bc b0c0 b0c4 b0c8 b0cc BREAK 1 265ca BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 265d0 BREAK 1 265d6 BREAK 1 265dc BREAK 1 265e2 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 265e8 BREAK 1 265ee BREAK 1 4fa af3a af3c af40 af44 af48 af4c af50 af54 af58 af5c af60 af64 af68 af6c af70 BREAK 1 265f4 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 265fa BREAK 1 26600 BREAK 1 26606 BREAK 1 2660c BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 26612 BREAK 1 26618 BREAK 1 4fa af3a af3c af40 af44 af48 af4c af50 af54 af58 af5c af60 af64 af68 af6c af70 BREAK 1 2661e BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 26624 BREAK 1 2662a BREAK 1 26630 BREAK 1 26636 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 2663c BREAK 1 26642 BREAK 1 4fd af74 af76 af7a af7e af82 af86 af8a af8e af92 af96 af9a af9e afa2 afa6 afaa BREAK 1 26648 BREAK 1 4f4 ad62 ad64 ad6c ad70 ad78 ad7c ad84 ad88 ad90 ad94 ad9c ada0 ada8 adac adb4 adb8 adc0 adc4 adcc add0 add8 addc ade4 ade8 adf0 adf4 adfc ae00 ae08 ae0c ae14 ae18 ae20 ae24 ae2c ae30 ae38 ae3c ae44 ae48 ae50 ae54 ae5c ae60 ae68 ae6c ae74 ae78 ae80 ae84 ae8c ae90 ae98 ae9c aea4 aea8 aeb0 aeb4 aebc aec0 aec8 aecc aed4 BREAK 1 2664e BREAK 1 26654 BREAK 1 2665a BREAK 1 26660 BREAK 1 4f7 aed8 aeda aee2 aee6 aeee aef2 aefa aefe af06 af0a af12 af16 af1e af22 af2a af2e af36 BREAK 1 26666 BREAK 1 2666c BREAK 1 4fd af74 af76 af7a af7e af82 af86 af8a af8e af92 af96 af9a af9e afa2 afa6 afaa BREAK 1 26672 BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 26678 BREAK 1 2667e BREAK 1 26684 BREAK 1 386 860000 6e06 6e08 6e0a 6e0c 6e0e 6e10 6e12 6e14 6e16 6e18 6e1a 6e1c 6e1e 6e20 6e22 6e24 6e26 6e28 6e2a 6e2c 6e2e 6e30 6e32 6e34 6e36 6e38 6e3a 6e3c 6e3e 6e40 6e42 6e44 BREAK 1 2668a BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 26690 BREAK 1 26696 BREAK 1 4b5 9ce2 9ce4 9ce6 9ce8 9cea 9cec 9cee 9cf0 9cf2 9cf4 9cf6 9cf8 9cfa 9cfc 9cfe 9d00 9d02 9d04 9d06 9d08 9d0a 9d0c 9d0e 9d10 9d12 9d14 9d16 9d18 9d1a 9d1c 9d1e 9d20 BREAK 1 2669c BREAK 1 266a2 BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c BREAK 1 ce 2436 2438 243d 2442 2447 244c 2451 2456 245b 2460 2465 246a 246f 2474 2479 247e 2483 2488 248d 2492 2497 249c ================================================ FILE: figure/SignalPulls/usatourbuy.txt ================================================ here Time [s],Packet ID,MOSI,MISO BREAK 1 bf 2300 2302 2307 230c 2311 2316 231b 2320 2325 232a 232f 2334 2339 BREAK 1 bc 2225 2227 222e 2235 223c 2243 224a 2251 2258 225f 2266 226d 2274 227b 2282 2289 2290 2297 229e 22a5 22ac 22b3 22ba 22c1 22c8 22cf 22d6 22dd 22e4 22eb 22f2 22f9 BREAK 1 c5 237c 237e 2383 2388 238d 2392 2397 239c 23a1 23a6 23ab 23b0 23b5 BREAK 1 bc 2225 2227 222e 2235 223c 2243 224a 2251 2258 225f 2266 226d 2274 227b 2282 2289 2290 2297 229e 22a5 22ac 22b3 22ba 22c1 22c8 22cf 22d6 22dd 22e4 22eb 22f2 22f9 BREAK 1 2a8 2af2 2af4 2af8 2afc 2b00 2b04 2b08 2b0c 2b10 2b14 2b18 2b1c 2b20 2b24 2b28 2b2c 2b30 BREAK 1 2cc 2e06 2e08 2e10 2e18 2e20 2e28 2e30 2e38 2e40 2e48 2e50 2e58 2e60 BREAK 1 163 BREAK 1 c5 237c 237e 2383 2388 238d 2392 2397 239c 23a1 23a6 23ab 23b0 23b5 BREAK 1 2a8 2af2 2af4 2af8 2afc 2b00 2b04 2b08 2b0c 2b10 2b14 2b18 2b1c 2b20 2b24 2b28 2b2c 2b30 BREAK 1 c5 237c 237e 2383 2388 238d 2392 2397 239c 23a1 23a6 23ab 23b0 23b5 BREAK 1 c5 237c 237e 2383 2388 238d 2392 2397 239c 23a1 23a6 23ab 23b0 23b5 BREAK 1 bc 2225 2227 222e 2235 223c 2243 224a 2251 2258 225f 2266 226d 2274 227b 2282 2289 2290 2297 229e 22a5 22ac 22b3 22ba 22c1 22c8 22cf 22d6 22dd 22e4 22eb 22f2 22f9 ================================================ FILE: figure/scripts/README ================================================ im.py -- extracts images from ROM dump ================================================ FILE: figure/scripts/im.py ================================================ import Image f = open("C:\\Users\\Natalie\\Downloads\\Tamagotchi-Hack-master\\figure\\ROMDump\\makiko", 'rb') a = f.read() s = "" #offset = 0x201292 #offset = 0x257010 #offset = 0x2AB139 offset = 0 a = a[offset:] num = 0 o = 0x1539 while True: width = ord(a[o]) #//while (width == 0): #// o = o + 1 #// width = ord(a[o]) height = ord(a[o+1]) print width, print height o = o + 2 if( height > 0x60): print "end" print o + offset break extra = 0 if( height > 0x60): print "end" print o + offset break if ((width) % 4 != 0): while ((width) % 4 != 0): width = width + 1 if ((height) % 4 != 0): #for t in range(0, (height) % 4): #height = height + 1 print "Padded to " + str(width) + " by " + str(height) s = "" for i in range(0, height*width/4 + 1): for j in range(0, 4): #print ord(a[i]) #print (0x03 << ((3- j)*2)) k = ord(a[i+o]) & (0x03 << ((3- j)*2)) l = ((k) >> ((3-j)*2)) s = s + chr(0xFF&(~(l*(255/4)))) o = o + height*width/4 #print s image = Image.fromstring( "L", (width, height), s, "raw", "L" ) print "img " + str(num) + " at " + str(o) image.save("../ROMDump/m/im-" + str(num) + ".bmp") num = num + 1 ================================================ FILE: figure/scripts/l.txt ================================================ 48 31 Padded to 48 by 31 img 0 at 5807 48 31 Padded to 48 by 31 img 1 at 6181 48 31 Padded to 48 by 31 img 2 at 6555 48 31 Padded to 48 by 31 img 3 at 6929 48 31 Padded to 48 by 31 img 4 at 7303 48 31 Padded to 48 by 31 img 5 at 7677 48 31 Padded to 48 by 31 img 6 at 8051 48 31 Padded to 48 by 31 img 7 at 8425 48 13 Padded to 48 by 13 img 8 at 8583 48 13 Padded to 48 by 13 img 9 at 8741 28 31 Padded to 28 by 31 img 10 at 8960 18 12 img 11 at 9022 18 12 img 12 at 9084 18 12 img 13 at 9146 18 12 img 14 at 9208 18 12 img 15 at 9270 17 21 Padded to 20 by 21 img 16 at 9377 17 21 Padded to 20 by 21 img 17 at 9484 32 8 img 18 at 9550 32 8 img 19 at 9616 32 8 img 20 at 9682 32 8 img 21 at 9748 32 8 img 22 at 9814 32 8 img 23 at 9880 8 8 img 24 at 9898 8 8 img 25 at 9916 8 8 img 26 at 9934 8 8 img 27 at 9952 8 8 img 28 at 9970 1 1 Padded to 4 by 1 img 29 at 9973 12 12 img 30 at 10011 12 12 img 31 at 10049 12 12 img 32 at 10087 12 12 img 33 at 10125 12 12 img 34 at 10163 12 12 img 35 at 10201 12 12 img 36 at 10239 12 12 img 37 at 10277 12 12 img 38 at 10315 12 12 img 39 at 10353 48 31 Padded to 48 by 31 img 40 at 10727 1 1 Padded to 4 by 1 img 41 at 10730 16 16 img 42 at 10796 16 16 img 43 at 10862 16 16 img 44 at 10928 16 16 img 45 at 10994 16 16 img 46 at 11060 16 16 img 47 at 11126 16 16 img 48 at 11192 16 16 img 49 at 11258 16 16 img 50 at 11324 16 16 img 51 at 11390 30 12 img 52 at 11488 30 12 img 53 at 11586 30 12 img 54 at 11684 30 12 img 55 at 11782 30 12 img 56 at 11880 30 12 img 57 at 11978 30 12 img 58 at 12076 30 12 img 59 at 12174 30 12 img 60 at 12272 30 12 img 61 at 12370 17 25 Padded to 20 by 25 img 62 at 12497 20 19 Padded to 20 by 19 img 63 at 12594 20 19 Padded to 20 by 19 img 64 at 12691 20 19 Padded to 20 by 19 img 65 at 12788 20 19 Padded to 20 by 19 img 66 at 12885 20 19 Padded to 20 by 19 img 67 at 12982 19 18 Padded to 20 by 18 img 68 at 13074 20 18 Padded to 20 by 18 img 69 at 13166 20 18 Padded to 20 by 18 img 70 at 13258 7 31 Padded to 8 by 31 img 71 at 13322 31 17 Padded to 32 by 17 img 72 at 13460 48 31 Padded to 48 by 31 img 73 at 13834 48 31 Padded to 48 by 31 img 74 at 14208 48 31 Padded to 48 by 31 img 75 at 14582 48 31 Padded to 48 by 31 img 76 at 14956 48 22 Padded to 48 by 22 img 77 at 15222 48 31 Padded to 48 by 31 img 78 at 15596 48 31 Padded to 48 by 31 img 79 at 15970 48 31 Padded to 48 by 31 img 80 at 16344 48 31 Padded to 48 by 31 img 81 at 16718 48 15 Padded to 48 by 15 img 82 at 16900 48 15 Padded to 48 by 15 img 83 at 17082 48 31 Padded to 48 by 31 img 84 at 17456 48 31 Padded to 48 by 31 img 85 at 17830 48 3 Padded to 48 by 3 img 86 at 17868 25 24 img 87 at 18038 48 6 Padded to 48 by 6 img 88 at 18112 48 31 Padded to 48 by 31 img 89 at 18486 48 31 Padded to 48 by 31 img 90 at 18860 48 31 Padded to 48 by 31 img 91 at 19234 48 31 Padded to 48 by 31 img 92 at 19608 48 31 Padded to 48 by 31 img 93 at 19982 48 31 Padded to 48 by 31 img 94 at 20356 6 7 Padded to 8 by 7 img 95 at 20372 7 31 Padded to 8 by 31 img 96 at 20436 32 31 Padded to 32 by 31 img 97 at 20686 48 31 Padded to 48 by 31 img 98 at 21060 48 31 Padded to 48 by 31 img 99 at 21434 48 31 Padded to 48 by 31 img 100 at 21808 48 31 Padded to 48 by 31 img 101 at 22182 48 31 Padded to 48 by 31 img 102 at 22556 48 31 Padded to 48 by 31 img 103 at 22930 48 31 Padded to 48 by 31 img 104 at 23304 48 31 Padded to 48 by 31 img 105 at 23678 48 31 Padded to 48 by 31 img 106 at 24052 48 31 Padded to 48 by 31 img 107 at 24426 48 31 Padded to 48 by 31 img 108 at 24800 48 31 Padded to 48 by 31 img 109 at 25174 48 31 Padded to 48 by 31 img 110 at 25548 48 31 Padded to 48 by 31 img 111 at 25922 48 31 Padded to 48 by 31 img 112 at 26296 48 31 Padded to 48 by 31 img 113 at 26670 48 31 Padded to 48 by 31 img 114 at 27044 48 31 Padded to 48 by 31 img 115 at 27418 48 31 Padded to 48 by 31 img 116 at 27792 48 31 Padded to 48 by 31 img 117 at 28166 7 31 Padded to 8 by 31 img 118 at 28230 32 29 Padded to 32 by 29 img 119 at 28464 32 29 Padded to 32 by 29 img 120 at 28698 48 31 Padded to 48 by 31 img 121 at 29072 48 31 Padded to 48 by 31 img 122 at 29446 48 31 Padded to 48 by 31 img 123 at 29820 48 31 Padded to 48 by 31 img 124 at 30194 48 31 Padded to 48 by 31 img 125 at 30568 48 31 Padded to 48 by 31 img 126 at 30942 48 31 Padded to 48 by 31 img 127 at 31316 48 31 Padded to 48 by 31 img 128 at 31690 48 31 Padded to 48 by 31 img 129 at 32064 48 8 img 130 at 32162 48 22 Padded to 48 by 22 img 131 at 32428 48 22 Padded to 48 by 22 img 132 at 32694 48 22 Padded to 48 by 22 img 133 at 32960 48 22 Padded to 48 by 22 img 134 at 33226 48 7 Padded to 48 by 7 img 135 at 33312 48 7 Padded to 48 by 7 img 136 at 33398 48 31 Padded to 48 by 31 img 137 at 33772 48 31 Padded to 48 by 31 img 138 at 34146 20 6 Padded to 20 by 6 img 139 at 34178 48 31 Padded to 48 by 31 img 140 at 34552 35 26 Padded to 36 by 26 img 141 at 34788 35 26 Padded to 36 by 26 img 142 at 35024 16 15 Padded to 16 by 15 img 143 at 35086 16 15 Padded to 16 by 15 img 144 at 35148 16 15 Padded to 16 by 15 img 145 at 35210 16 15 Padded to 16 by 15 img 146 at 35272 16 15 Padded to 16 by 15 img 147 at 35334 16 15 Padded to 16 by 15 img 148 at 35396 16 15 Padded to 16 by 15 img 149 at 35458 16 15 Padded to 16 by 15 img 150 at 35520 16 15 Padded to 16 by 15 img 151 at 35582 16 15 Padded to 16 by 15 img 152 at 35644 16 15 Padded to 16 by 15 img 153 at 35706 16 15 Padded to 16 by 15 img 154 at 35768 16 15 Padded to 16 by 15 img 155 at 35830 16 15 Padded to 16 by 15 img 156 at 35892 16 15 Padded to 16 by 15 img 157 at 35954 16 15 Padded to 16 by 15 img 158 at 36016 16 15 Padded to 16 by 15 img 159 at 36078 16 15 Padded to 16 by 15 img 160 at 36140 16 15 Padded to 16 by 15 img 161 at 36202 16 15 Padded to 16 by 15 img 162 at 36264 16 15 Padded to 16 by 15 img 163 at 36326 16 15 Padded to 16 by 15 img 164 at 36388 16 15 Padded to 16 by 15 img 165 at 36450 16 15 Padded to 16 by 15 img 166 at 36512 16 15 Padded to 16 by 15 img 167 at 36574 16 15 Padded to 16 by 15 img 168 at 36636 16 15 Padded to 16 by 15 img 169 at 36698 16 15 Padded to 16 by 15 img 170 at 36760 16 15 Padded to 16 by 15 img 171 at 36822 16 15 Padded to 16 by 15 img 172 at 36884 16 15 Padded to 16 by 15 img 173 at 36946 16 15 Padded to 16 by 15 img 174 at 37008 16 15 Padded to 16 by 15 img 175 at 37070 16 15 Padded to 16 by 15 img 176 at 37132 16 15 Padded to 16 by 15 img 177 at 37194 16 15 Padded to 16 by 15 img 178 at 37256 24 31 Padded to 24 by 31 img 179 at 37444 24 15 Padded to 24 by 15 img 180 at 37536 16 19 Padded to 16 by 19 img 181 at 37614 30 31 Padded to 32 by 31 img 182 at 37864 30 31 Padded to 32 by 31 img 183 at 38114 30 31 Padded to 32 by 31 img 184 at 38364 30 31 Padded to 32 by 31 img 185 at 38614 30 31 Padded to 32 by 31 img 186 at 38864 4 7 Padded to 4 by 7 img 187 at 38873 4 7 Padded to 4 by 7 img 188 at 38882 4 7 Padded to 4 by 7 img 189 at 38891 4 7 Padded to 4 by 7 img 190 at 38900 48 31 Padded to 48 by 31 img 191 at 39274 48 31 Padded to 48 by 31 img 192 at 39648 19 7 Padded to 20 by 7 img 193 at 39685 13 7 Padded to 16 by 7 img 194 at 39715 13 7 Padded to 16 by 7 img 195 at 39745 19 7 Padded to 20 by 7 img 196 at 39782 48 31 Padded to 48 by 31 img 197 at 40156 4 4 img 198 at 40162 7 31 Padded to 8 by 31 img 199 at 40226 48 31 Padded to 48 by 31 img 200 at 40600 48 31 Padded to 48 by 31 img 201 at 40974 48 31 Padded to 48 by 31 img 202 at 41348 48 31 Padded to 48 by 31 img 203 at 41722 16 31 Padded to 16 by 31 img 204 at 41848 16 16 img 205 at 41914 16 16 img 206 at 41980 16 16 img 207 at 42046 16 16 img 208 at 42112 4 4 img 209 at 42118 4 4 img 210 at 42124 48 31 Padded to 48 by 31 img 211 at 42498 48 31 Padded to 48 by 31 img 212 at 42872 48 31 Padded to 48 by 31 img 213 at 43246 48 31 Padded to 48 by 31 img 214 at 43620 48 31 Padded to 48 by 31 img 215 at 43994 4 4 img 216 at 44000 4 4 img 217 at 44006 4 4 img 218 at 44012 48 31 Padded to 48 by 31 img 219 at 44386 48 31 Padded to 48 by 31 img 220 at 44760 48 8 img 221 at 44858 16 14 Padded to 16 by 14 img 222 at 44916 16 14 Padded to 16 by 14 img 223 at 44974 16 14 Padded to 16 by 14 img 224 at 45032 16 14 Padded to 16 by 14 img 225 at 45090 16 14 Padded to 16 by 14 img 226 at 45148 16 14 Padded to 16 by 14 img 227 at 45206 16 14 Padded to 16 by 14 img 228 at 45264 16 14 Padded to 16 by 14 img 229 at 45322 16 14 Padded to 16 by 14 img 230 at 45380 48 31 Padded to 48 by 31 img 231 at 45754 24 31 Padded to 24 by 31 img 232 at 45942 24 15 Padded to 24 by 15 img 233 at 46034 16 19 Padded to 16 by 19 img 234 at 46112 30 31 Padded to 32 by 31 img 235 at 46362 30 31 Padded to 32 by 31 img 236 at 46612 30 31 Padded to 32 by 31 img 237 at 46862 30 31 Padded to 32 by 31 img 238 at 47112 30 31 Padded to 32 by 31 img 239 at 47362 4 7 Padded to 4 by 7 img 240 at 47371 4 7 Padded to 4 by 7 img 241 at 47380 4 7 Padded to 4 by 7 img 242 at 47389 4 7 Padded to 4 by 7 img 243 at 47398 48 31 Padded to 48 by 31 img 244 at 47772 48 31 Padded to 48 by 31 img 245 at 48146 19 7 Padded to 20 by 7 img 246 at 48183 13 7 Padded to 16 by 7 img 247 at 48213 13 7 Padded to 16 by 7 img 248 at 48243 19 7 Padded to 20 by 7 img 249 at 48280 48 31 Padded to 48 by 31 img 250 at 48654 4 4 img 251 at 48660 7 31 Padded to 8 by 31 img 252 at 48724 48 31 Padded to 48 by 31 img 253 at 49098 48 31 Padded to 48 by 31 img 254 at 49472 48 31 Padded to 48 by 31 img 255 at 49846 48 31 Padded to 48 by 31 img 256 at 50220 48 31 Padded to 48 by 31 img 257 at 50594 48 31 Padded to 48 by 31 img 258 at 50968 48 31 Padded to 48 by 31 img 259 at 51342 16 16 img 260 at 51408 16 16 img 261 at 51474 16 16 img 262 at 51540 16 16 img 263 at 51606 48 31 Padded to 48 by 31 img 264 at 51980 48 31 Padded to 48 by 31 img 265 at 52354 48 31 Padded to 48 by 31 img 266 at 52728 48 31 Padded to 48 by 31 img 267 at 53102 48 31 Padded to 48 by 31 img 268 at 53476 4 4 img 269 at 53482 4 4 img 270 at 53488 4 4 img 271 at 53494 48 31 Padded to 48 by 31 img 272 at 53868 48 31 Padded to 48 by 31 img 273 at 54242 48 8 img 274 at 54340 16 14 Padded to 16 by 14 img 275 at 54398 16 14 Padded to 16 by 14 img 276 at 54456 16 14 Padded to 16 by 14 img 277 at 54514 16 14 Padded to 16 by 14 img 278 at 54572 16 14 Padded to 16 by 14 img 279 at 54630 16 14 Padded to 16 by 14 img 280 at 54688 16 14 Padded to 16 by 14 img 281 at 54746 16 14 Padded to 16 by 14 img 282 at 54804 16 14 Padded to 16 by 14 img 283 at 54862 48 31 Padded to 48 by 31 img 284 at 55236 24 31 Padded to 24 by 31 img 285 at 55424 24 15 Padded to 24 by 15 img 286 at 55516 16 19 Padded to 16 by 19 img 287 at 55594 30 31 Padded to 32 by 31 img 288 at 55844 30 31 Padded to 32 by 31 img 289 at 56094 30 31 Padded to 32 by 31 img 290 at 56344 30 31 Padded to 32 by 31 img 291 at 56594 30 31 Padded to 32 by 31 img 292 at 56844 4 7 Padded to 4 by 7 img 293 at 56853 4 7 Padded to 4 by 7 img 294 at 56862 4 7 Padded to 4 by 7 img 295 at 56871 4 7 Padded to 4 by 7 img 296 at 56880 48 31 Padded to 48 by 31 img 297 at 57254 48 31 Padded to 48 by 31 img 298 at 57628 19 7 Padded to 20 by 7 img 299 at 57665 13 7 Padded to 16 by 7 img 300 at 57695 13 7 Padded to 16 by 7 img 301 at 57725 19 7 Padded to 20 by 7 img 302 at 57762 48 31 Padded to 48 by 31 img 303 at 58136 4 4 img 304 at 58142 7 31 Padded to 8 by 31 img 305 at 58206 48 31 Padded to 48 by 31 img 306 at 58580 48 31 Padded to 48 by 31 img 307 at 58954 48 31 Padded to 48 by 31 img 308 at 59328 48 31 Padded to 48 by 31 img 309 at 59702 48 31 Padded to 48 by 31 img 310 at 60076 48 31 Padded to 48 by 31 img 311 at 60450 48 31 Padded to 48 by 31 img 312 at 60824 48 31 Padded to 48 by 31 img 313 at 61198 48 31 Padded to 48 by 31 img 314 at 61572 48 31 Padded to 48 by 31 img 315 at 61946 16 16 img 316 at 62012 16 16 img 317 at 62078 16 16 img 318 at 62144 16 16 img 319 at 62210 4 4 img 320 at 62216 4 4 img 321 at 62222 4 4 img 322 at 62228 4 4 img 323 at 62234 4 4 img 324 at 62240 48 31 Padded to 48 by 31 img 325 at 62614 48 31 Padded to 48 by 31 img 326 at 62988 48 8 img 327 at 63086 16 14 Padded to 16 by 14 img 328 at 63144 16 14 Padded to 16 by 14 img 329 at 63202 16 14 Padded to 16 by 14 img 330 at 63260 16 14 Padded to 16 by 14 img 331 at 63318 16 14 Padded to 16 by 14 img 332 at 63376 16 14 Padded to 16 by 14 img 333 at 63434 16 14 Padded to 16 by 14 img 334 at 63492 16 14 Padded to 16 by 14 img 335 at 63550 16 14 Padded to 16 by 14 img 336 at 63608 48 31 Padded to 48 by 31 img 337 at 63982 24 31 Padded to 24 by 31 img 338 at 64170 24 15 Padded to 24 by 15 img 339 at 64262 16 19 Padded to 16 by 19 img 340 at 64340 30 31 Padded to 32 by 31 img 341 at 64590 30 31 Padded to 32 by 31 img 342 at 64840 30 31 Padded to 32 by 31 img 343 at 65090 30 31 Padded to 32 by 31 img 344 at 65340 30 31 Padded to 32 by 31 img 345 at 65590 4 7 Padded to 4 by 7 img 346 at 65599 4 7 Padded to 4 by 7 img 347 at 65608 4 7 Padded to 4 by 7 img 348 at 65617 4 7 Padded to 4 by 7 img 349 at 65626 48 31 Padded to 48 by 31 img 350 at 66000 48 31 Padded to 48 by 31 img 351 at 66374 19 7 Padded to 20 by 7 img 352 at 66411 13 7 Padded to 16 by 7 img 353 at 66441 13 7 Padded to 16 by 7 img 354 at 66471 19 7 Padded to 20 by 7 img 355 at 66508 48 31 Padded to 48 by 31 img 356 at 66882 4 4 img 357 at 66888 7 31 Padded to 8 by 31 img 358 at 66952 48 31 Padded to 48 by 31 img 359 at 67326 48 31 Padded to 48 by 31 img 360 at 67700 48 31 Padded to 48 by 31 img 361 at 68074 48 31 Padded to 48 by 31 img 362 at 68448 48 31 Padded to 48 by 31 img 363 at 68822 48 31 Padded to 48 by 31 img 364 at 69196 48 31 Padded to 48 by 31 img 365 at 69570 48 31 Padded to 48 by 31 img 366 at 69944 48 31 Padded to 48 by 31 img 367 at 70318 26 15 Padded to 28 by 15 img 368 at 70425 24 12 img 369 at 70499 48 2 Padded to 48 by 2 img 370 at 70525 48 31 Padded to 48 by 31 img 371 at 70899 4 4 img 372 at 70905 4 4 img 373 at 70911 4 4 img 374 at 70917 4 4 img 375 at 70923 4 4 img 376 at 70929 4 4 img 377 at 70935 48 31 Padded to 48 by 31 img 378 at 71309 48 31 Padded to 48 by 31 img 379 at 71683 48 8 img 380 at 71781 16 14 Padded to 16 by 14 img 381 at 71839 16 14 Padded to 16 by 14 img 382 at 71897 16 14 Padded to 16 by 14 img 383 at 71955 16 14 Padded to 16 by 14 img 384 at 72013 16 14 Padded to 16 by 14 img 385 at 72071 16 14 Padded to 16 by 14 img 386 at 72129 16 14 Padded to 16 by 14 img 387 at 72187 16 14 Padded to 16 by 14 img 388 at 72245 16 14 Padded to 16 by 14 img 389 at 72303 48 31 Padded to 48 by 31 img 390 at 72677 14 13 Padded to 16 by 13 img 391 at 72731 14 13 Padded to 16 by 13 img 392 at 72785 14 13 Padded to 16 by 13 img 393 at 72839 14 13 Padded to 16 by 13 img 394 at 72893 14 13 Padded to 16 by 13 img 395 at 72947 14 13 Padded to 16 by 13 img 396 at 73001 14 13 Padded to 16 by 13 img 397 at 73055 14 13 Padded to 16 by 13 img 398 at 73109 14 13 Padded to 16 by 13 img 399 at 73163 14 13 Padded to 16 by 13 img 400 at 73217 14 13 Padded to 16 by 13 img 401 at 73271 14 13 Padded to 16 by 13 img 402 at 73325 14 13 Padded to 16 by 13 img 403 at 73379 14 13 Padded to 16 by 13 img 404 at 73433 14 13 Padded to 16 by 13 img 405 at 73487 14 13 Padded to 16 by 13 img 406 at 73541 14 13 Padded to 16 by 13 img 407 at 73595 14 13 Padded to 16 by 13 img 408 at 73649 14 13 Padded to 16 by 13 img 409 at 73703 14 13 Padded to 16 by 13 img 410 at 73757 14 13 Padded to 16 by 13 img 411 at 73811 14 13 Padded to 16 by 13 img 412 at 73865 14 13 Padded to 16 by 13 img 413 at 73919 14 13 Padded to 16 by 13 img 414 at 73973 14 13 Padded to 16 by 13 img 415 at 74027 14 13 Padded to 16 by 13 img 416 at 74081 14 13 Padded to 16 by 13 img 417 at 74135 14 13 Padded to 16 by 13 img 418 at 74189 14 13 Padded to 16 by 13 img 419 at 74243 14 13 Padded to 16 by 13 img 420 at 74297 14 13 Padded to 16 by 13 img 421 at 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445 at 78255 48 31 Padded to 48 by 31 img 446 at 78629 14 11 Padded to 16 by 11 img 447 at 78675 48 31 Padded to 48 by 31 img 448 at 79049 48 31 Padded to 48 by 31 img 449 at 79423 7 31 Padded to 8 by 31 img 450 at 79487 22 16 img 451 at 79585 22 16 img 452 at 79683 7 31 Padded to 8 by 31 img 453 at 79747 48 7 Padded to 48 by 7 img 454 at 79833 48 6 Padded to 48 by 6 img 455 at 79907 48 6 Padded to 48 by 6 img 456 at 79981 9 8 img 457 at 80007 20 23 Padded to 20 by 23 img 458 at 80124 48 31 Padded to 48 by 31 img 459 at 80498 48 31 Padded to 48 by 31 img 460 at 80872 48 31 Padded to 48 by 31 img 461 at 81246 10 10 Padded to 12 by 10 img 462 at 81278 10 10 Padded to 12 by 10 img 463 at 81310 10 12 img 464 at 81348 10 12 img 465 at 81386 24 9 Padded to 24 by 9 img 466 at 81442 28 6 Padded to 28 by 6 img 467 at 81486 28 6 Padded to 28 by 6 img 468 at 81530 1 0 ================================================ FILE: figure-simulator/README ================================================ Code to simulate a memetchi figure. In progress. ================================================ FILE: figure-simulator/simulator.pde ================================================ #include DSPI0 spi; const int len = 200; uint8_t rgbSnd[len] = {0}; uint8_t rgbRcv[len] = {0}; uint8_t b[] ={0x40, 0x00, 0x00, 0xC4, 0x00, 0x00, 0xDC, 0x00, 0x00, 0x0F, 0x01, 0x00, 0x91, 0x01, 0x00, 0x0D, 0x02, 0x00, 0x89, 0x02, 0x00, 0xD1, 0x02, 0x00, 0x1F, 0x06, 0x00, 0x67, 0x0F, 0x00, 0x67, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x12, 0x00, 0xA7, 0x12, 0x00, 0x0D, 0x13, 0x00, 0x73, 0x13, 0x00, 0xD9, 0x13, 0x00, 0x3F, 0x14, 0x00, 0xA5, 0x14, 0x00, 0x0B, 0x15, 0x00, 0x71, 0x15, 0x00, 0xD7, 0x15, 0x00, 0x3D, 0x16, 0x00, 0xA3, 0x16, 0x00, 0x09, 0x17, 0x00, 0x6F, 0x17, 0x00, 0xD5, 0x17, 0x00, 0x3B, 0x18, 0x00, 0xA1, 0x18, 0x00, 0x07, 0x19, 0x00, 0x6D, 0x19, 0x00, 0xD3, 0x19, 0x00, 0x39, 0x1A, 0x00, 0x9F, 0x1A, 0x00, 0x05, 0x1B, 0x00, 0x6B, 0x1B, 0x00, 0xD1, 0x1B, 0x00, 0x37, 0x1C, 0x00, 0x9D, 0x1C, 0x00, 0x13, 0x1E, 0x00, 0x89, 0x1F, 0x00, 0xFF, 0x20, 0x00, 0x75, 0x22, 0x00, 0xEB, 0x23, 0x00, 0x61, 0x25, 0x00, 0xD7, 0x26, 0x00, 0x4D, 0x28, 0x00, 0xEB, 0x28, 0x00, 0x89, 0x29, 0x00, 0x64, 0x2A, 0x00, 0xA2, 0x2A, 0x00, 0xE0, 0x2A, 0x00, 0x1E, 0x2B, 0x00, 0x5C, 0x2B, 0x00, 0x9A, 0x2B, 0x00, 0x05, 0x2C, 0x00, 0x70, 0x2C, 0x00, 0x82, 0x2C, 0x00, 0x90, 0x2C, 0x00, 0x9E, 0x2C, 0x00, 0xB0, 0x2C, 0x00, 0xC2, 0x2C, 0x00, 0xD4, 0x2C}; int i; int yc = 0; int x=0; int y=0; void setup() { Serial.begin(9600); Serial.println("start"); spi.begin(); spi.setSpeed(600000); SPI2CONbits.ON = 0; rgbRcv[0] = SPI2BUF; SPI2CONbits.MSTEN = 0; SPI2CONbits.SSEN = 1; SPI2CONbits.CKP = 0; SPI2CONbits.CKE = 1; rgbSnd[4] = 0xaa; rgbSnd[5] = 0x55; rgbSnd[6] = 0x08; rgbSnd[11] = 0xaa; rgbSnd[12] = 0x55; rgbSnd[17] = 0x03; rgbSnd[18] = 0x03; rgbSnd[19] = 0x03; rgbSnd[20] = 0x00; rgbSnd[21] = 0x00; rgbSnd[22] = 0x10; rgbSnd[23] = 0x03; // rgbSnd[28] = 0x40; // rgbSnd[31] = 0xc4; // rgbSnd[34] = 0xdc; // rgbSnd[40] = while(i<96-28){ for(y = 0; y < 8; y++){ rgbSnd[28 + i] = b[yc++]; i++; } for(x = 0; x < 4; x++){ i++; } } rgbSnd[100] = 0xaa; rgbSnd[101] = 0x55; rgbSnd[106] = 0x9a; rgbSnd[107] = 0x2b; rgbSnd[108] = 0x00; rgbSnd[113] = 0x11; rgbSnd[114] = 0x15; rgbSnd[119] = 0xaa; rgbSnd[120] = 0x55; /// rgbSnd[140] = 0xff; SPI2CONbits.ON = 1; Serial.println("start 2"); } void loop() { for (i = 0; i < 150; i++) { rgbRcv[i] = spiComm(rgbSnd[i]); } for(i = 0; i < 150; i++) { Serial.print(i); Serial.print(" "); Serial.print(rgbSnd[i], HEX); Serial.print(" "); Serial.println(rgbRcv[i], HEX); } Serial.println("END"); } uint8_t spiComm(uint8_t bVal) { while ((SPI2STAT & (1 << _SPISTAT_SPITBE)) == 0) { } SPI2BUF = bVal; while ((SPI2STAT & (1 << _SPISTAT_SPIRBF)) == 0) { } return SPI2BUF; } ================================================ FILE: figure-simulator-discovery/.cproject ================================================ ================================================ FILE: figure-simulator-discovery/.project ================================================ spi org.eclipse.cdt.managedbuilder.core.genmakebuilder clean,full,incremental, ?name? org.eclipse.cdt.make.core.append_environment true org.eclipse.cdt.make.core.buildArguments org.eclipse.cdt.make.core.buildCommand make org.eclipse.cdt.make.core.buildLocation ${workspace_loc:/spi/Debug} org.eclipse.cdt.make.core.contents org.eclipse.cdt.make.core.activeConfigSettings org.eclipse.cdt.make.core.enableAutoBuild false org.eclipse.cdt.make.core.enableCleanBuild true org.eclipse.cdt.make.core.enableFullBuild true org.eclipse.cdt.make.core.stopOnError true org.eclipse.cdt.make.core.useDefaultBuildCmd true org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder full,incremental, org.eclipse.cdt.core.cnature org.eclipse.cdt.managedbuilder.core.managedBuildNature org.eclipse.cdt.managedbuilder.core.ScannerConfigNature ================================================ FILE: figure-simulator-discovery/.settings/com.atollic.truestudio.debug.hardware_device.prefs ================================================ #Sun Dec 16 21:31:24 EST 2012 BOARD=STM32F4_Discovery CODE_LOCATION=FLASH ENDIAN=Little-endian MCU=STM32F407VG MCU_VENDOR=STMicroelectronics MODEL=Lite PROBE=ST-LINK PROJECT_FORMAT_VERSION=2 TARGET=ARM\u00AE VERSION=3.3.0 eclipse.preferences.version=1 ================================================ FILE: figure-simulator-discovery/.settings/org.eclipse.cdt.managedbuilder.core.prefs ================================================ #Sat Dec 22 00:56:48 EST 2012 eclipse.preferences.version=1 environment/buildEnvironmentInclude/com.atollic.truestudio.configuration.release.560513466/CPATH/delimiter=; environment/buildEnvironmentInclude/com.atollic.truestudio.configuration.release.560513466/CPATH/operation=remove environment/buildEnvironmentInclude/com.atollic.truestudio.configuration.release.560513466/C_INCLUDE_PATH/delimiter=; environment/buildEnvironmentInclude/com.atollic.truestudio.configuration.release.560513466/C_INCLUDE_PATH/operation=remove environment/buildEnvironmentInclude/com.atollic.truestudio.configuration.release.560513466/append=true environment/buildEnvironmentInclude/com.atollic.truestudio.configuration.release.560513466/appendContributed=true environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.238007381/CPATH/delimiter=; environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.238007381/CPATH/operation=remove environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.238007381/C_INCLUDE_PATH/delimiter=; environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.238007381/C_INCLUDE_PATH/operation=remove environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.238007381/append=true environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.238007381/appendContributed=true environment/buildEnvironmentLibrary/com.atollic.truestudio.configuration.release.560513466/LIBRARY_PATH/delimiter=; environment/buildEnvironmentLibrary/com.atollic.truestudio.configuration.release.560513466/LIBRARY_PATH/operation=remove environment/buildEnvironmentLibrary/com.atollic.truestudio.configuration.release.560513466/append=true environment/buildEnvironmentLibrary/com.atollic.truestudio.configuration.release.560513466/appendContributed=true environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.238007381/LIBRARY_PATH/delimiter=; environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.238007381/LIBRARY_PATH/operation=remove environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.238007381/append=true environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.238007381/appendContributed=true ================================================ FILE: figure-simulator-discovery/Libraries/CMSIS/Include/arm_common_tables.h ================================================ /* ---------------------------------------------------------------------- * Copyright (C) 2010 ARM Limited. All rights reserved. * * $Date: 11. November 2010 * $Revision: V1.0.2 * * Project: CMSIS DSP Library * Title: arm_common_tables.h * * Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions * * Target Processor: Cortex-M4/Cortex-M3 * * Version 1.0.2 2010/11/11 * Documentation updated. * * Version 1.0.1 2010/10/05 * Production release and review comments incorporated. * * Version 1.0.0 2010/09/20 * Production release and review comments incorporated. * -------------------------------------------------------------------- */ #ifndef _ARM_COMMON_TABLES_H #define _ARM_COMMON_TABLES_H #include "arm_math.h" extern uint16_t armBitRevTable[256]; extern q15_t armRecipTableQ15[64]; extern q31_t armRecipTableQ31[64]; extern const q31_t realCoefAQ31[1024]; extern const q31_t realCoefBQ31[1024]; #endif /* ARM_COMMON_TABLES_H */ ================================================ FILE: figure-simulator-discovery/Libraries/CMSIS/Include/arm_math.h ================================================ /* ---------------------------------------------------------------------- * Copyright (C) 2010 ARM Limited. All rights reserved. * * $Date: 15. July 2011 * $Revision: V1.0.10 * * Project: CMSIS DSP Library * Title: arm_math.h * * Description: Public header file for CMSIS DSP Library * * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * * Version 1.0.10 2011/7/15 * Big Endian support added and Merged M0 and M3/M4 Source code. * * Version 1.0.3 2010/11/29 * Re-organized the CMSIS folders and updated documentation. * * Version 1.0.2 2010/11/11 * Documentation updated. * * Version 1.0.1 2010/10/05 * Production release and review comments incorporated. * * Version 1.0.0 2010/09/20 * Production release and review comments incorporated. * -------------------------------------------------------------------- */ /** \mainpage CMSIS DSP Software Library * * Introduction * * This user manual describes the CMSIS DSP software library, * a suite of common signal processing functions for use on Cortex-M processor based devices. * * The library is divided into a number of modules each covering a specific category: * - Basic math functions * - Fast math functions * - Complex math functions * - Filters * - Matrix functions * - Transforms * - Motor control functions * - Statistical functions * - Support functions * - Interpolation functions * * The library has separate functions for operating on 8-bit integers, 16-bit integers, * 32-bit integer and 32-bit floating-point values. * * Processor Support * * The library is completely written in C and is fully CMSIS compliant. * High performance is achieved through maximum use of Cortex-M4 intrinsics. * * The supplied library source code also builds and runs on the Cortex-M3 and Cortex-M0 processor, * with the DSP intrinsics being emulated through software. * * * Toolchain Support * * The library has been developed and tested with MDK-ARM version 4.21. * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. * * Using the Library * * The library installer contains prebuilt versions of the libraries in the Lib folder. * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) * * The library functions are declared in the public file arm_math.h which is placed in the Include folder. * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or * ARM_MATH_CM0 depending on the target processor in the application. * * Examples * * The library ships with a number of examples which demonstrate how to use the library functions. * * Building the Library * * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\DSP_Lib\Source\ARM folder. * - arm_cortexM0b_math.uvproj * - arm_cortexM0l_math.uvproj * - arm_cortexM3b_math.uvproj * - arm_cortexM3l_math.uvproj * - arm_cortexM4b_math.uvproj * - arm_cortexM4l_math.uvproj * - arm_cortexM4bf_math.uvproj * - arm_cortexM4lf_math.uvproj * * Each library project have differant pre-processor macros. * * ARM_MATH_CMx: * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target * and ARM_MATH_CM0 for building library on cortex-M0 target. * * ARM_MATH_BIG_ENDIAN: * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. * * ARM_MATH_MATRIX_CHECK: * Define macro for checking on the input and output sizes of matrices * * ARM_MATH_ROUNDING: * Define macro for rounding on support functions * * __FPU_PRESENT: * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries * * * The project can be built by opening the appropriate project in MDK-ARM 4.21 chain and defining the optional pre processor MACROs detailed above. * * Copyright Notice * * Copyright (C) 2010 ARM Limited. All rights reserved. */ /** * @defgroup groupMath Basic Math Functions */ /** * @defgroup groupFastMath Fast Math Functions * This set of functions provides a fast approximation to sine, cosine, and square root. * As compared to most of the other functions in the CMSIS math library, the fast math functions * operate on individual values and not arrays. * There are separate functions for Q15, Q31, and floating-point data. * */ /** * @defgroup groupCmplxMath Complex Math Functions * This set of functions operates on complex data vectors. * The data in the complex arrays is stored in an interleaved fashion * (real, imag, real, imag, ...). * In the API functions, the number of samples in a complex array refers * to the number of complex values; the array contains twice this number of * real values. */ /** * @defgroup groupFilters Filtering Functions */ /** * @defgroup groupMatrix Matrix Functions * * This set of functions provides basic matrix math operations. * The functions operate on matrix data structures. For example, * the type * definition for the floating-point matrix structure is shown * below: * 
 *     typedef struct
 *     {
 *       uint16_t numRows;     // number of rows of the matrix.
 *       uint16_t numCols;     // number of columns of the matrix.
 *       float32_t *pData;     // points to the data of the matrix.
 *     } arm_matrix_instance_f32;
 *
* There are similar definitions for Q15 and Q31 data types. * * The structure specifies the size of the matrix and then points to * an array of data. The array is of size numRows X numCols * and the values are arranged in row order. That is, the * matrix element (i, j) is stored at: * 
 *     pData[i*numCols + j]
 *
* * \par Init Functions * There is an associated initialization function for each type of matrix * data structure. * The initialization function sets the values of the internal structure fields. * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. * * \par * Use of the initialization function is optional. However, if initialization function is used * then the instance structure cannot be placed into a const data section. * To place the instance structure in a const data * section, manually initialize the data structure. For example: * 
 * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
 * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
 * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
 *
* where nRows specifies the number of rows, nColumns * specifies the number of columns, and pData points to the * data array. * * \par Size Checking * By default all of the matrix functions perform size checking on the input and * output matrices. For example, the matrix addition function verifies that the * two input matrices and the output matrix all have the same number of rows and * columns. If the size check fails the functions return: * 
 *     ARM_MATH_SIZE_MISMATCH
 *
* Otherwise the functions return * 
 *     ARM_MATH_SUCCESS
 *
* There is some overhead associated with this matrix size checking. * The matrix size checking is enabled via the #define * 
 *     ARM_MATH_MATRIX_CHECK
 *
* within the library project settings. By default this macro is defined * and size checking is enabled. By changing the project settings and * undefining this macro size checking is eliminated and the functions * run a bit faster. With size checking disabled the functions always * return ARM_MATH_SUCCESS. */ /** * @defgroup groupTransforms Transform Functions */ /** * @defgroup groupController Controller Functions */ /** * @defgroup groupStats Statistics Functions */ /** * @defgroup groupSupport Support Functions */ /** * @defgroup groupInterpolation Interpolation Functions * These functions perform 1- and 2-dimensional interpolation of data. * Linear interpolation is used for 1-dimensional data and * bilinear interpolation is used for 2-dimensional data. */ /** * @defgroup groupExamples Examples */ #ifndef _ARM_MATH_H #define _ARM_MATH_H #define __CMSIS_GENERIC /* disable NVIC and Systick functions */ #if defined (ARM_MATH_CM4) #include "core_cm4.h" #elif defined (ARM_MATH_CM3) #include "core_cm3.h" #elif defined (ARM_MATH_CM0) #include "core_cm0.h" #else #include "ARMCM4.h" #warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....." #endif #undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ #include "string.h" #include "math.h" #ifdef __cplusplus extern "C" { #endif /** * @brief Macros required for reciprocal calculation in Normalized LMS */ #define DELTA_Q31 (0x100) #define DELTA_Q15 0x5 #define INDEX_MASK 0x0000003F #define PI 3.14159265358979f /** * @brief Macros required for SINE and COSINE Fast math approximations */ #define TABLE_SIZE 256 #define TABLE_SPACING_Q31 0x800000 #define TABLE_SPACING_Q15 0x80 /** * @brief Macros required for SINE and COSINE Controller functions */ /* 1.31(q31) Fixed value of 2/360 */ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ #define INPUT_SPACING 0xB60B61 /** * @brief Error status returned by some functions in the library. */ typedef enum { ARM_MATH_SUCCESS = 0, /**< No error */ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ } arm_status; /** * @brief 8-bit fractional data type in 1.7 format. */ typedef int8_t q7_t; /** * @brief 16-bit fractional data type in 1.15 format. */ typedef int16_t q15_t; /** * @brief 32-bit fractional data type in 1.31 format. */ typedef int32_t q31_t; /** * @brief 64-bit fractional data type in 1.63 format. */ typedef int64_t q63_t; /** * @brief 32-bit floating-point type definition. */ typedef float float32_t; /** * @brief 64-bit floating-point type definition. */ typedef double float64_t; /** * @brief definition to read/write two 16 bit values. */ #define __SIMD32(addr) (*(int32_t **) & (addr)) #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) /** * @brief definition to pack two 16 bit values. */ #define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) #endif /** * @brief definition to pack four 8 bit values. */ #ifndef ARM_MATH_BIG_ENDIAN #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) #else #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) #endif /** * @brief Clips Q63 to Q31 values. */ static __INLINE q31_t clip_q63_to_q31( q63_t x) { return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; } /** * @brief Clips Q63 to Q15 values. */ static __INLINE q15_t clip_q63_to_q15( q63_t x) { return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); } /** * @brief Clips Q31 to Q7 values. */ static __INLINE q7_t clip_q31_to_q7( q31_t x) { return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; } /** * @brief Clips Q31 to Q15 values. */ static __INLINE q15_t clip_q31_to_q15( q31_t x) { return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; } /** * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. */ static __INLINE q63_t mult32x64( q63_t x, q31_t y) { return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + (((q63_t) (x >> 32) * y))); } #if defined (ARM_MATH_CM0) && defined ( __CC_ARM ) #define __CLZ __clz #endif #if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) static __INLINE uint32_t __CLZ(q31_t data); static __INLINE uint32_t __CLZ(q31_t data) { uint32_t count = 0; uint32_t mask = 0x80000000; while((data & mask) == 0) { count += 1u; mask = mask >> 1u; } return(count); } #endif /** * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type. */ static __INLINE uint32_t arm_recip_q31( q31_t in, q31_t * dst, q31_t * pRecipTable) { uint32_t out, tempVal; uint32_t index, i; uint32_t signBits; if(in > 0) { signBits = __CLZ(in) - 1; } else { signBits = __CLZ(-in) - 1; } /* Convert input sample to 1.31 format */ in = in << signBits; /* calculation of index for initial approximated Val */ index = (uint32_t) (in >> 24u); index = (index & INDEX_MASK); /* 1.31 with exp 1 */ out = pRecipTable[index]; /* calculation of reciprocal value */ /* running approximation for two iterations */ for (i = 0u; i < 2u; i++) { tempVal = (q31_t) (((q63_t) in * out) >> 31u); tempVal = 0x7FFFFFFF - tempVal; /* 1.31 with exp 1 */ //out = (q31_t) (((q63_t) out * tempVal) >> 30u); out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); } /* write output */ *dst = out; /* return num of signbits of out = 1/in value */ return (signBits + 1u); } /** * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type. */ static __INLINE uint32_t arm_recip_q15( q15_t in, q15_t * dst, q15_t * pRecipTable) { uint32_t out = 0, tempVal = 0; uint32_t index = 0, i = 0; uint32_t signBits = 0; if(in > 0) { signBits = __CLZ(in) - 17; } else { signBits = __CLZ(-in) - 17; } /* Convert input sample to 1.15 format */ in = in << signBits; /* calculation of index for initial approximated Val */ index = in >> 8; index = (index & INDEX_MASK); /* 1.15 with exp 1 */ out = pRecipTable[index]; /* calculation of reciprocal value */ /* running approximation for two iterations */ for (i = 0; i < 2; i++) { tempVal = (q15_t) (((q31_t) in * out) >> 15); tempVal = 0x7FFF - tempVal; /* 1.15 with exp 1 */ out = (q15_t) (((q31_t) out * tempVal) >> 14); } /* write output */ *dst = out; /* return num of signbits of out = 1/in value */ return (signBits + 1); } /* * @brief C custom defined intrinisic function for only M0 processors */ #if defined(ARM_MATH_CM0) static __INLINE q31_t __SSAT( q31_t x, uint32_t y) { int32_t posMax, negMin; uint32_t i; posMax = 1; for (i = 0; i < (y - 1); i++) { posMax = posMax * 2; } if(x > 0) { posMax = (posMax - 1); if(x > posMax) { x = posMax; } } else { negMin = -posMax; if(x < negMin) { x = negMin; } } return (x); } #endif /* end of ARM_MATH_CM0 */ /* * @brief C custom defined intrinsic function for M3 and M0 processors */ #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) /* * @brief C custom defined QADD8 for M3 and M0 processors */ static __INLINE q31_t __QADD8( q31_t x, q31_t y) { q31_t sum; q7_t r, s, t, u; r = (char) x; s = (char) y; r = __SSAT((q31_t) (r + s), 8); s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); sum = (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); return sum; } /* * @brief C custom defined QSUB8 for M3 and M0 processors */ static __INLINE q31_t __QSUB8( q31_t x, q31_t y) { q31_t sum; q31_t r, s, t, u; r = (char) x; s = (char) y; r = __SSAT((r - s), 8); s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; sum = (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF); return sum; } /* * @brief C custom defined QADD16 for M3 and M0 processors */ /* * @brief C custom defined QADD16 for M3 and M0 processors */ static __INLINE q31_t __QADD16( q31_t x, q31_t y) { q31_t sum; q31_t r, s; r = (short) x; s = (short) y; r = __SSAT(r + s, 16); s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); return sum; } /* * @brief C custom defined SHADD16 for M3 and M0 processors */ static __INLINE q31_t __SHADD16( q31_t x, q31_t y) { q31_t sum; q31_t r, s; r = (short) x; s = (short) y; r = ((r >> 1) + (s >> 1)); s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); return sum; } /* * @brief C custom defined QSUB16 for M3 and M0 processors */ static __INLINE q31_t __QSUB16( q31_t x, q31_t y) { q31_t sum; q31_t r, s; r = (short) x; s = (short) y; r = __SSAT(r - s, 16); s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); return sum; } /* * @brief C custom defined SHSUB16 for M3 and M0 processors */ static __INLINE q31_t __SHSUB16( q31_t x, q31_t y) { q31_t diff; q31_t r, s; r = (short) x; s = (short) y; r = ((r >> 1) - (s >> 1)); s = (((x >> 17) - (y >> 17)) << 16); diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); return diff; } /* * @brief C custom defined QASX for M3 and M0 processors */ static __INLINE q31_t __QASX( q31_t x, q31_t y) { q31_t sum = 0; sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) + clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16))); return sum; } /* * @brief C custom defined SHASX for M3 and M0 processors */ static __INLINE q31_t __SHASX( q31_t x, q31_t y) { q31_t sum; q31_t r, s; r = (short) x; s = (short) y; r = ((r >> 1) - (y >> 17)); s = (((x >> 17) + (s >> 1)) << 16); sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); return sum; } /* * @brief C custom defined QSAX for M3 and M0 processors */ static __INLINE q31_t __QSAX( q31_t x, q31_t y) { q31_t sum = 0; sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) + clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16))); return sum; } /* * @brief C custom defined SHSAX for M3 and M0 processors */ static __INLINE q31_t __SHSAX( q31_t x, q31_t y) { q31_t sum; q31_t r, s; r = (short) x; s = (short) y; r = ((r >> 1) + (y >> 17)); s = (((x >> 17) - (s >> 1)) << 16); sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); return sum; } /* * @brief C custom defined SMUSDX for M3 and M0 processors */ static __INLINE q31_t __SMUSDX( q31_t x, q31_t y) { return ((q31_t)(((short) x * (short) (y >> 16)) - ((short) (x >> 16) * (short) y))); } /* * @brief C custom defined SMUADX for M3 and M0 processors */ static __INLINE q31_t __SMUADX( q31_t x, q31_t y) { return ((q31_t)(((short) x * (short) (y >> 16)) + ((short) (x >> 16) * (short) y))); } /* * @brief C custom defined QADD for M3 and M0 processors */ static __INLINE q31_t __QADD( q31_t x, q31_t y) { return clip_q63_to_q31((q63_t) x + y); } /* * @brief C custom defined QSUB for M3 and M0 processors */ static __INLINE q31_t __QSUB( q31_t x, q31_t y) { return clip_q63_to_q31((q63_t) x - y); } /* * @brief C custom defined SMLAD for M3 and M0 processors */ static __INLINE q31_t __SMLAD( q31_t x, q31_t y, q31_t sum) { return (sum + ((short) (x >> 16) * (short) (y >> 16)) + ((short) x * (short) y)); } /* * @brief C custom defined SMLADX for M3 and M0 processors */ static __INLINE q31_t __SMLADX( q31_t x, q31_t y, q31_t sum) { return (sum + ((short) (x >> 16) * (short) (y)) + ((short) x * (short) (y >> 16))); } /* * @brief C custom defined SMLSDX for M3 and M0 processors */ static __INLINE q31_t __SMLSDX( q31_t x, q31_t y, q31_t sum) { return (sum - ((short) (x >> 16) * (short) (y)) + ((short) x * (short) (y >> 16))); } /* * @brief C custom defined SMLALD for M3 and M0 processors */ static __INLINE q63_t __SMLALD( q31_t x, q31_t y, q63_t sum) { return (sum + ((short) (x >> 16) * (short) (y >> 16)) + ((short) x * (short) y)); } /* * @brief C custom defined SMLALDX for M3 and M0 processors */ static __INLINE q63_t __SMLALDX( q31_t x, q31_t y, q63_t sum) { return (sum + ((short) (x >> 16) * (short) y)) + ((short) x * (short) (y >> 16)); } /* * @brief C custom defined SMUAD for M3 and M0 processors */ static __INLINE q31_t __SMUAD( q31_t x, q31_t y) { return (((x >> 16) * (y >> 16)) + (((x << 16) >> 16) * ((y << 16) >> 16))); } /* * @brief C custom defined SMUSD for M3 and M0 processors */ static __INLINE q31_t __SMUSD( q31_t x, q31_t y) { return (-((x >> 16) * (y >> 16)) + (((x << 16) >> 16) * ((y << 16) >> 16))); } #endif /* (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */ /** * @brief Instance structure for the Q7 FIR filter. */ typedef struct { uint16_t numTaps; /**< number of filter coefficients in the filter. */ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ } arm_fir_instance_q7; /** * @brief Instance structure for the Q15 FIR filter. */ typedef struct { uint16_t numTaps; /**< number of filter coefficients in the filter. */ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ } arm_fir_instance_q15; /** * @brief Instance structure for the Q31 FIR filter. */ typedef struct { uint16_t numTaps; /**< number of filter coefficients in the filter. */ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ } arm_fir_instance_q31; /** * @brief Instance structure for the floating-point FIR filter. */ typedef struct { uint16_t numTaps; /**< number of filter coefficients in the filter. */ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ } arm_fir_instance_f32; /** * @brief Processing function for the Q7 FIR filter. * @param[in] *S points to an instance of the Q7 FIR filter structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_fir_q7( const arm_fir_instance_q7 * S, q7_t * pSrc, q7_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q7 FIR filter. * @param[in,out] *S points to an instance of the Q7 FIR structure. * @param[in] numTaps Number of filter coefficients in the filter. * @param[in] *pCoeffs points to the filter coefficients. * @param[in] *pState points to the state buffer. * @param[in] blockSize number of samples that are processed. * @return none */ void arm_fir_init_q7( arm_fir_instance_q7 * S, uint16_t numTaps, q7_t * pCoeffs, q7_t * pState, uint32_t blockSize); /** * @brief Processing function for the Q15 FIR filter. * @param[in] *S points to an instance of the Q15 FIR structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_fir_q15( const arm_fir_instance_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. * @param[in] *S points to an instance of the Q15 FIR filter structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_fir_fast_q15( const arm_fir_instance_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q15 FIR filter. * @param[in,out] *S points to an instance of the Q15 FIR filter structure. * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. * @param[in] *pCoeffs points to the filter coefficients. * @param[in] *pState points to the state buffer. * @param[in] blockSize number of samples that are processed at a time. * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if * numTaps is not a supported value. */ arm_status arm_fir_init_q15( arm_fir_instance_q15 * S, uint16_t numTaps, q15_t * pCoeffs, q15_t * pState, uint32_t blockSize); /** * @brief Processing function for the Q31 FIR filter. * @param[in] *S points to an instance of the Q31 FIR filter structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_fir_q31( const arm_fir_instance_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. * @param[in] *S points to an instance of the Q31 FIR structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_fir_fast_q31( const arm_fir_instance_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q31 FIR filter. * @param[in,out] *S points to an instance of the Q31 FIR structure. * @param[in] numTaps Number of filter coefficients in the filter. * @param[in] *pCoeffs points to the filter coefficients. * @param[in] *pState points to the state buffer. * @param[in] blockSize number of samples that are processed at a time. * @return none. */ void arm_fir_init_q31( arm_fir_instance_q31 * S, uint16_t numTaps, q31_t * pCoeffs, q31_t * pState, uint32_t blockSize); /** * @brief Processing function for the floating-point FIR filter. * @param[in] *S points to an instance of the floating-point FIR structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_fir_f32( const arm_fir_instance_f32 * S, float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point FIR filter. * @param[in,out] *S points to an instance of the floating-point FIR filter structure. * @param[in] numTaps Number of filter coefficients in the filter. * @param[in] *pCoeffs points to the filter coefficients. * @param[in] *pState points to the state buffer. * @param[in] blockSize number of samples that are processed at a time. * @return none. */ void arm_fir_init_f32( arm_fir_instance_f32 * S, uint16_t numTaps, float32_t * pCoeffs, float32_t * pState, uint32_t blockSize); /** * @brief Instance structure for the Q15 Biquad cascade filter. */ typedef struct { int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ } arm_biquad_casd_df1_inst_q15; /** * @brief Instance structure for the Q31 Biquad cascade filter. */ typedef struct { uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ } arm_biquad_casd_df1_inst_q31; /** * @brief Instance structure for the floating-point Biquad cascade filter. */ typedef struct { uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ } arm_biquad_casd_df1_inst_f32; /** * @brief Processing function for the Q15 Biquad cascade filter. * @param[in] *S points to an instance of the Q15 Biquad cascade structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_biquad_cascade_df1_q15( const arm_biquad_casd_df1_inst_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q15 Biquad cascade filter. * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] *pCoeffs points to the filter coefficients. * @param[in] *pState points to the state buffer. * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format * @return none */ void arm_biquad_cascade_df1_init_q15( arm_biquad_casd_df1_inst_q15 * S, uint8_t numStages, q15_t * pCoeffs, q15_t * pState, int8_t postShift); /** * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. * @param[in] *S points to an instance of the Q15 Biquad cascade structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_biquad_cascade_df1_fast_q15( const arm_biquad_casd_df1_inst_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Processing function for the Q31 Biquad cascade filter * @param[in] *S points to an instance of the Q31 Biquad cascade structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_biquad_cascade_df1_q31( const arm_biquad_casd_df1_inst_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. * @param[in] *S points to an instance of the Q31 Biquad cascade structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_biquad_cascade_df1_fast_q31( const arm_biquad_casd_df1_inst_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q31 Biquad cascade filter. * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] *pCoeffs points to the filter coefficients. * @param[in] *pState points to the state buffer. * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format * @return none */ void arm_biquad_cascade_df1_init_q31( arm_biquad_casd_df1_inst_q31 * S, uint8_t numStages, q31_t * pCoeffs, q31_t * pState, int8_t postShift); /** * @brief Processing function for the floating-point Biquad cascade filter. * @param[in] *S points to an instance of the floating-point Biquad cascade structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_biquad_cascade_df1_f32( const arm_biquad_casd_df1_inst_f32 * S, float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point Biquad cascade filter. * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] *pCoeffs points to the filter coefficients. * @param[in] *pState points to the state buffer. * @return none */ void arm_biquad_cascade_df1_init_f32( arm_biquad_casd_df1_inst_f32 * S, uint8_t numStages, float32_t * pCoeffs, float32_t * pState); /** * @brief Instance structure for the floating-point matrix structure. */ typedef struct { uint16_t numRows; /**< number of rows of the matrix. */ uint16_t numCols; /**< number of columns of the matrix. */ float32_t *pData; /**< points to the data of the matrix. */ } arm_matrix_instance_f32; /** * @brief Instance structure for the Q15 matrix structure. */ typedef struct { uint16_t numRows; /**< number of rows of the matrix. */ uint16_t numCols; /**< number of columns of the matrix. */ q15_t *pData; /**< points to the data of the matrix. */ } arm_matrix_instance_q15; /** * @brief Instance structure for the Q31 matrix structure. */ typedef struct { uint16_t numRows; /**< number of rows of the matrix. */ uint16_t numCols; /**< number of columns of the matrix. */ q31_t *pData; /**< points to the data of the matrix. */ } arm_matrix_instance_q31; /** * @brief Floating-point matrix addition. * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure * @param[out] *pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_add_f32( const arm_matrix_instance_f32 * pSrcA, const arm_matrix_instance_f32 * pSrcB, arm_matrix_instance_f32 * pDst); /** * @brief Q15 matrix addition. * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure * @param[out] *pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_add_q15( const arm_matrix_instance_q15 * pSrcA, const arm_matrix_instance_q15 * pSrcB, arm_matrix_instance_q15 * pDst); /** * @brief Q31 matrix addition. * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure * @param[out] *pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_add_q31( const arm_matrix_instance_q31 * pSrcA, const arm_matrix_instance_q31 * pSrcB, arm_matrix_instance_q31 * pDst); /** * @brief Floating-point matrix transpose. * @param[in] *pSrc points to the input matrix * @param[out] *pDst points to the output matrix * @return The function returns either ARM_MATH_SIZE_MISMATCH * or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_trans_f32( const arm_matrix_instance_f32 * pSrc, arm_matrix_instance_f32 * pDst); /** * @brief Q15 matrix transpose. * @param[in] *pSrc points to the input matrix * @param[out] *pDst points to the output matrix * @return The function returns either ARM_MATH_SIZE_MISMATCH * or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_trans_q15( const arm_matrix_instance_q15 * pSrc, arm_matrix_instance_q15 * pDst); /** * @brief Q31 matrix transpose. * @param[in] *pSrc points to the input matrix * @param[out] *pDst points to the output matrix * @return The function returns either ARM_MATH_SIZE_MISMATCH * or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_trans_q31( const arm_matrix_instance_q31 * pSrc, arm_matrix_instance_q31 * pDst); /** * @brief Floating-point matrix multiplication * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure * @param[out] *pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_mult_f32( const arm_matrix_instance_f32 * pSrcA, const arm_matrix_instance_f32 * pSrcB, arm_matrix_instance_f32 * pDst); /** * @brief Q15 matrix multiplication * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure * @param[out] *pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_mult_q15( const arm_matrix_instance_q15 * pSrcA, const arm_matrix_instance_q15 * pSrcB, arm_matrix_instance_q15 * pDst, q15_t * pState); /** * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure * @param[out] *pDst points to output matrix structure * @param[in] *pState points to the array for storing intermediate results * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_mult_fast_q15( const arm_matrix_instance_q15 * pSrcA, const arm_matrix_instance_q15 * pSrcB, arm_matrix_instance_q15 * pDst, q15_t * pState); /** * @brief Q31 matrix multiplication * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure * @param[out] *pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_mult_q31( const arm_matrix_instance_q31 * pSrcA, const arm_matrix_instance_q31 * pSrcB, arm_matrix_instance_q31 * pDst); /** * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure * @param[out] *pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_mult_fast_q31( const arm_matrix_instance_q31 * pSrcA, const arm_matrix_instance_q31 * pSrcB, arm_matrix_instance_q31 * pDst); /** * @brief Floating-point matrix subtraction * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure * @param[out] *pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_sub_f32( const arm_matrix_instance_f32 * pSrcA, const arm_matrix_instance_f32 * pSrcB, arm_matrix_instance_f32 * pDst); /** * @brief Q15 matrix subtraction * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure * @param[out] *pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_sub_q15( const arm_matrix_instance_q15 * pSrcA, const arm_matrix_instance_q15 * pSrcB, arm_matrix_instance_q15 * pDst); /** * @brief Q31 matrix subtraction * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure * @param[out] *pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_sub_q31( const arm_matrix_instance_q31 * pSrcA, const arm_matrix_instance_q31 * pSrcB, arm_matrix_instance_q31 * pDst); /** * @brief Floating-point matrix scaling. * @param[in] *pSrc points to the input matrix * @param[in] scale scale factor * @param[out] *pDst points to the output matrix * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_scale_f32( const arm_matrix_instance_f32 * pSrc, float32_t scale, arm_matrix_instance_f32 * pDst); /** * @brief Q15 matrix scaling. * @param[in] *pSrc points to input matrix * @param[in] scaleFract fractional portion of the scale factor * @param[in] shift number of bits to shift the result by * @param[out] *pDst points to output matrix * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_scale_q15( const arm_matrix_instance_q15 * pSrc, q15_t scaleFract, int32_t shift, arm_matrix_instance_q15 * pDst); /** * @brief Q31 matrix scaling. * @param[in] *pSrc points to input matrix * @param[in] scaleFract fractional portion of the scale factor * @param[in] shift number of bits to shift the result by * @param[out] *pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_scale_q31( const arm_matrix_instance_q31 * pSrc, q31_t scaleFract, int32_t shift, arm_matrix_instance_q31 * pDst); /** * @brief Q31 matrix initialization. * @param[in,out] *S points to an instance of the floating-point matrix structure. * @param[in] nRows number of rows in the matrix. * @param[in] nColumns number of columns in the matrix. * @param[in] *pData points to the matrix data array. * @return none */ void arm_mat_init_q31( arm_matrix_instance_q31 * S, uint16_t nRows, uint16_t nColumns, q31_t *pData); /** * @brief Q15 matrix initialization. * @param[in,out] *S points to an instance of the floating-point matrix structure. * @param[in] nRows number of rows in the matrix. * @param[in] nColumns number of columns in the matrix. * @param[in] *pData points to the matrix data array. * @return none */ void arm_mat_init_q15( arm_matrix_instance_q15 * S, uint16_t nRows, uint16_t nColumns, q15_t *pData); /** * @brief Floating-point matrix initialization. * @param[in,out] *S points to an instance of the floating-point matrix structure. * @param[in] nRows number of rows in the matrix. * @param[in] nColumns number of columns in the matrix. * @param[in] *pData points to the matrix data array. * @return none */ void arm_mat_init_f32( arm_matrix_instance_f32 * S, uint16_t nRows, uint16_t nColumns, float32_t *pData); /** * @brief Instance structure for the Q15 PID Control. */ typedef struct { q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ #ifdef ARM_MATH_CM0 q15_t A1; q15_t A2; #else q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ #endif q15_t state[3]; /**< The state array of length 3. */ q15_t Kp; /**< The proportional gain. */ q15_t Ki; /**< The integral gain. */ q15_t Kd; /**< The derivative gain. */ } arm_pid_instance_q15; /** * @brief Instance structure for the Q31 PID Control. */ typedef struct { q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ q31_t A2; /**< The derived gain, A2 = Kd . */ q31_t state[3]; /**< The state array of length 3. */ q31_t Kp; /**< The proportional gain. */ q31_t Ki; /**< The integral gain. */ q31_t Kd; /**< The derivative gain. */ } arm_pid_instance_q31; /** * @brief Instance structure for the floating-point PID Control. */ typedef struct { float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ float32_t A2; /**< The derived gain, A2 = Kd . */ float32_t state[3]; /**< The state array of length 3. */ float32_t Kp; /**< The proportional gain. */ float32_t Ki; /**< The integral gain. */ float32_t Kd; /**< The derivative gain. */ } arm_pid_instance_f32; /** * @brief Initialization function for the floating-point PID Control. * @param[in,out] *S points to an instance of the PID structure. * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. * @return none. */ void arm_pid_init_f32( arm_pid_instance_f32 * S, int32_t resetStateFlag); /** * @brief Reset function for the floating-point PID Control. * @param[in,out] *S is an instance of the floating-point PID Control structure * @return none */ void arm_pid_reset_f32( arm_pid_instance_f32 * S); /** * @brief Initialization function for the Q31 PID Control. * @param[in,out] *S points to an instance of the Q15 PID structure. * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. * @return none. */ void arm_pid_init_q31( arm_pid_instance_q31 * S, int32_t resetStateFlag); /** * @brief Reset function for the Q31 PID Control. * @param[in,out] *S points to an instance of the Q31 PID Control structure * @return none */ void arm_pid_reset_q31( arm_pid_instance_q31 * S); /** * @brief Initialization function for the Q15 PID Control. * @param[in,out] *S points to an instance of the Q15 PID structure. * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. * @return none. */ void arm_pid_init_q15( arm_pid_instance_q15 * S, int32_t resetStateFlag); /** * @brief Reset function for the Q15 PID Control. * @param[in,out] *S points to an instance of the q15 PID Control structure * @return none */ void arm_pid_reset_q15( arm_pid_instance_q15 * S); /** * @brief Instance structure for the floating-point Linear Interpolate function. */ typedef struct { uint32_t nValues; float32_t x1; float32_t xSpacing; float32_t *pYData; /**< pointer to the table of Y values */ } arm_linear_interp_instance_f32; /** * @brief Instance structure for the floating-point bilinear interpolation function. */ typedef struct { uint16_t numRows; /**< number of rows in the data table. */ uint16_t numCols; /**< number of columns in the data table. */ float32_t *pData; /**< points to the data table. */ } arm_bilinear_interp_instance_f32; /** * @brief Instance structure for the Q31 bilinear interpolation function. */ typedef struct { uint16_t numRows; /**< number of rows in the data table. */ uint16_t numCols; /**< number of columns in the data table. */ q31_t *pData; /**< points to the data table. */ } arm_bilinear_interp_instance_q31; /** * @brief Instance structure for the Q15 bilinear interpolation function. */ typedef struct { uint16_t numRows; /**< number of rows in the data table. */ uint16_t numCols; /**< number of columns in the data table. */ q15_t *pData; /**< points to the data table. */ } arm_bilinear_interp_instance_q15; /** * @brief Instance structure for the Q15 bilinear interpolation function. */ typedef struct { uint16_t numRows; /**< number of rows in the data table. */ uint16_t numCols; /**< number of columns in the data table. */ q7_t *pData; /**< points to the data table. */ } arm_bilinear_interp_instance_q7; /** * @brief Q7 vector multiplication. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in each vector * @return none. */ void arm_mult_q7( q7_t * pSrcA, q7_t * pSrcB, q7_t * pDst, uint32_t blockSize); /** * @brief Q15 vector multiplication. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in each vector * @return none. */ void arm_mult_q15( q15_t * pSrcA, q15_t * pSrcB, q15_t * pDst, uint32_t blockSize); /** * @brief Q31 vector multiplication. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in each vector * @return none. */ void arm_mult_q31( q31_t * pSrcA, q31_t * pSrcB, q31_t * pDst, uint32_t blockSize); /** * @brief Floating-point vector multiplication. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in each vector * @return none. */ void arm_mult_f32( float32_t * pSrcA, float32_t * pSrcB, float32_t * pDst, uint32_t blockSize); /** * @brief Instance structure for the Q15 CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ q15_t *pTwiddle; /**< points to the twiddle factor table. */ uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ } arm_cfft_radix4_instance_q15; /** * @brief Instance structure for the Q31 CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ q31_t *pTwiddle; /**< points to the twiddle factor table. */ uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ } arm_cfft_radix4_instance_q31; /** * @brief Instance structure for the floating-point CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ float32_t *pTwiddle; /**< points to the twiddle factor table. */ uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ float32_t onebyfftLen; /**< value of 1/fftLen. */ } arm_cfft_radix4_instance_f32; /** * @brief Processing function for the Q15 CFFT/CIFFT. * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure. * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. * @return none. */ void arm_cfft_radix4_q15( const arm_cfft_radix4_instance_q15 * S, q15_t * pSrc); /** * @brief Initialization function for the Q15 CFFT/CIFFT. * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure. * @param[in] fftLen length of the FFT. * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. */ arm_status arm_cfft_radix4_init_q15( arm_cfft_radix4_instance_q15 * S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag); /** * @brief Processing function for the Q31 CFFT/CIFFT. * @param[in] *S points to an instance of the Q31 CFFT/CIFFT structure. * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. * @return none. */ void arm_cfft_radix4_q31( const arm_cfft_radix4_instance_q31 * S, q31_t * pSrc); /** * @brief Initialization function for the Q31 CFFT/CIFFT. * @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure. * @param[in] fftLen length of the FFT. * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. */ arm_status arm_cfft_radix4_init_q31( arm_cfft_radix4_instance_q31 * S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag); /** * @brief Processing function for the floating-point CFFT/CIFFT. * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure. * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. * @return none. */ void arm_cfft_radix4_f32( const arm_cfft_radix4_instance_f32 * S, float32_t * pSrc); /** * @brief Initialization function for the floating-point CFFT/CIFFT. * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure. * @param[in] fftLen length of the FFT. * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. */ arm_status arm_cfft_radix4_init_f32( arm_cfft_radix4_instance_f32 * S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag); /*---------------------------------------------------------------------- * Internal functions prototypes FFT function ----------------------------------------------------------------------*/ /** * @brief Core function for the floating-point CFFT butterfly process. * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. * @param[in] fftLen length of the FFT. * @param[in] *pCoef points to the twiddle coefficient buffer. * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. * @return none. */ void arm_radix4_butterfly_f32( float32_t * pSrc, uint16_t fftLen, float32_t * pCoef, uint16_t twidCoefModifier); /** * @brief Core function for the floating-point CIFFT butterfly process. * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. * @param[in] fftLen length of the FFT. * @param[in] *pCoef points to twiddle coefficient buffer. * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. * @param[in] onebyfftLen value of 1/fftLen. * @return none. */ void arm_radix4_butterfly_inverse_f32( float32_t * pSrc, uint16_t fftLen, float32_t * pCoef, uint16_t twidCoefModifier, float32_t onebyfftLen); /** * @brief In-place bit reversal function. * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. * @param[in] fftSize length of the FFT. * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table. * @param[in] *pBitRevTab points to the bit reversal table. * @return none. */ void arm_bitreversal_f32( float32_t *pSrc, uint16_t fftSize, uint16_t bitRevFactor, uint16_t *pBitRevTab); /** * @brief Core function for the Q31 CFFT butterfly process. * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. * @param[in] fftLen length of the FFT. * @param[in] *pCoef points to twiddle coefficient buffer. * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. * @return none. */ void arm_radix4_butterfly_q31( q31_t *pSrc, uint32_t fftLen, q31_t *pCoef, uint32_t twidCoefModifier); /** * @brief Core function for the Q31 CIFFT butterfly process. * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. * @param[in] fftLen length of the FFT. * @param[in] *pCoef points to twiddle coefficient buffer. * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. * @return none. */ void arm_radix4_butterfly_inverse_q31( q31_t * pSrc, uint32_t fftLen, q31_t * pCoef, uint32_t twidCoefModifier); /** * @brief In-place bit reversal function. * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. * @param[in] fftLen length of the FFT. * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table * @param[in] *pBitRevTab points to bit reversal table. * @return none. */ void arm_bitreversal_q31( q31_t * pSrc, uint32_t fftLen, uint16_t bitRevFactor, uint16_t *pBitRevTab); /** * @brief Core function for the Q15 CFFT butterfly process. * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type. * @param[in] fftLen length of the FFT. * @param[in] *pCoef16 points to twiddle coefficient buffer. * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. * @return none. */ void arm_radix4_butterfly_q15( q15_t *pSrc16, uint32_t fftLen, q15_t *pCoef16, uint32_t twidCoefModifier); /** * @brief Core function for the Q15 CIFFT butterfly process. * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type. * @param[in] fftLen length of the FFT. * @param[in] *pCoef16 points to twiddle coefficient buffer. * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. * @return none. */ void arm_radix4_butterfly_inverse_q15( q15_t *pSrc16, uint32_t fftLen, q15_t *pCoef16, uint32_t twidCoefModifier); /** * @brief In-place bit reversal function. * @param[in, out] *pSrc points to the in-place buffer of Q15 data type. * @param[in] fftLen length of the FFT. * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table * @param[in] *pBitRevTab points to bit reversal table. * @return none. */ void arm_bitreversal_q15( q15_t * pSrc, uint32_t fftLen, uint16_t bitRevFactor, uint16_t *pBitRevTab); /** * @brief Instance structure for the Q15 RFFT/RIFFT function. */ typedef struct { uint32_t fftLenReal; /**< length of the real FFT. */ uint32_t fftLenBy2; /**< length of the complex FFT. */ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ } arm_rfft_instance_q15; /** * @brief Instance structure for the Q31 RFFT/RIFFT function. */ typedef struct { uint32_t fftLenReal; /**< length of the real FFT. */ uint32_t fftLenBy2; /**< length of the complex FFT. */ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ } arm_rfft_instance_q31; /** * @brief Instance structure for the floating-point RFFT/RIFFT function. */ typedef struct { uint32_t fftLenReal; /**< length of the real FFT. */ uint16_t fftLenBy2; /**< length of the complex FFT. */ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ } arm_rfft_instance_f32; /** * @brief Processing function for the Q15 RFFT/RIFFT. * @param[in] *S points to an instance of the Q15 RFFT/RIFFT structure. * @param[in] *pSrc points to the input buffer. * @param[out] *pDst points to the output buffer. * @return none. */ void arm_rfft_q15( const arm_rfft_instance_q15 * S, q15_t * pSrc, q15_t * pDst); /** * @brief Initialization function for the Q15 RFFT/RIFFT. * @param[in, out] *S points to an instance of the Q15 RFFT/RIFFT structure. * @param[in] *S_CFFT points to an instance of the Q15 CFFT/CIFFT structure. * @param[in] fftLenReal length of the FFT. * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. */ arm_status arm_rfft_init_q15( arm_rfft_instance_q15 * S, arm_cfft_radix4_instance_q15 * S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag); /** * @brief Processing function for the Q31 RFFT/RIFFT. * @param[in] *S points to an instance of the Q31 RFFT/RIFFT structure. * @param[in] *pSrc points to the input buffer. * @param[out] *pDst points to the output buffer. * @return none. */ void arm_rfft_q31( const arm_rfft_instance_q31 * S, q31_t * pSrc, q31_t * pDst); /** * @brief Initialization function for the Q31 RFFT/RIFFT. * @param[in, out] *S points to an instance of the Q31 RFFT/RIFFT structure. * @param[in, out] *S_CFFT points to an instance of the Q31 CFFT/CIFFT structure. * @param[in] fftLenReal length of the FFT. * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. */ arm_status arm_rfft_init_q31( arm_rfft_instance_q31 * S, arm_cfft_radix4_instance_q31 * S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag); /** * @brief Initialization function for the floating-point RFFT/RIFFT. * @param[in,out] *S points to an instance of the floating-point RFFT/RIFFT structure. * @param[in,out] *S_CFFT points to an instance of the floating-point CFFT/CIFFT structure. * @param[in] fftLenReal length of the FFT. * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. */ arm_status arm_rfft_init_f32( arm_rfft_instance_f32 * S, arm_cfft_radix4_instance_f32 * S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag); /** * @brief Processing function for the floating-point RFFT/RIFFT. * @param[in] *S points to an instance of the floating-point RFFT/RIFFT structure. * @param[in] *pSrc points to the input buffer. * @param[out] *pDst points to the output buffer. * @return none. */ void arm_rfft_f32( const arm_rfft_instance_f32 * S, float32_t * pSrc, float32_t * pDst); /** * @brief Instance structure for the floating-point DCT4/IDCT4 function. */ typedef struct { uint16_t N; /**< length of the DCT4. */ uint16_t Nby2; /**< half of the length of the DCT4. */ float32_t normalize; /**< normalizing factor. */ float32_t *pTwiddle; /**< points to the twiddle factor table. */ float32_t *pCosFactor; /**< points to the cosFactor table. */ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ } arm_dct4_instance_f32; /** * @brief Initialization function for the floating-point DCT4/IDCT4. * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. * @param[in] N length of the DCT4. * @param[in] Nby2 half of the length of the DCT4. * @param[in] normalize normalizing factor. * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. */ arm_status arm_dct4_init_f32( arm_dct4_instance_f32 * S, arm_rfft_instance_f32 * S_RFFT, arm_cfft_radix4_instance_f32 * S_CFFT, uint16_t N, uint16_t Nby2, float32_t normalize); /** * @brief Processing function for the floating-point DCT4/IDCT4. * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. * @param[in] *pState points to state buffer. * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. * @return none. */ void arm_dct4_f32( const arm_dct4_instance_f32 * S, float32_t * pState, float32_t * pInlineBuffer); /** * @brief Instance structure for the Q31 DCT4/IDCT4 function. */ typedef struct { uint16_t N; /**< length of the DCT4. */ uint16_t Nby2; /**< half of the length of the DCT4. */ q31_t normalize; /**< normalizing factor. */ q31_t *pTwiddle; /**< points to the twiddle factor table. */ q31_t *pCosFactor; /**< points to the cosFactor table. */ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ } arm_dct4_instance_q31; /** * @brief Initialization function for the Q31 DCT4/IDCT4. * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure * @param[in] N length of the DCT4. * @param[in] Nby2 half of the length of the DCT4. * @param[in] normalize normalizing factor. * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. */ arm_status arm_dct4_init_q31( arm_dct4_instance_q31 * S, arm_rfft_instance_q31 * S_RFFT, arm_cfft_radix4_instance_q31 * S_CFFT, uint16_t N, uint16_t Nby2, q31_t normalize); /** * @brief Processing function for the Q31 DCT4/IDCT4. * @param[in] *S points to an instance of the Q31 DCT4 structure. * @param[in] *pState points to state buffer. * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. * @return none. */ void arm_dct4_q31( const arm_dct4_instance_q31 * S, q31_t * pState, q31_t * pInlineBuffer); /** * @brief Instance structure for the Q15 DCT4/IDCT4 function. */ typedef struct { uint16_t N; /**< length of the DCT4. */ uint16_t Nby2; /**< half of the length of the DCT4. */ q15_t normalize; /**< normalizing factor. */ q15_t *pTwiddle; /**< points to the twiddle factor table. */ q15_t *pCosFactor; /**< points to the cosFactor table. */ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ } arm_dct4_instance_q15; /** * @brief Initialization function for the Q15 DCT4/IDCT4. * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. * @param[in] N length of the DCT4. * @param[in] Nby2 half of the length of the DCT4. * @param[in] normalize normalizing factor. * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. */ arm_status arm_dct4_init_q15( arm_dct4_instance_q15 * S, arm_rfft_instance_q15 * S_RFFT, arm_cfft_radix4_instance_q15 * S_CFFT, uint16_t N, uint16_t Nby2, q15_t normalize); /** * @brief Processing function for the Q15 DCT4/IDCT4. * @param[in] *S points to an instance of the Q15 DCT4 structure. * @param[in] *pState points to state buffer. * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. * @return none. */ void arm_dct4_q15( const arm_dct4_instance_q15 * S, q15_t * pState, q15_t * pInlineBuffer); /** * @brief Floating-point vector addition. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in each vector * @return none. */ void arm_add_f32( float32_t * pSrcA, float32_t * pSrcB, float32_t * pDst, uint32_t blockSize); /** * @brief Q7 vector addition. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in each vector * @return none. */ void arm_add_q7( q7_t * pSrcA, q7_t * pSrcB, q7_t * pDst, uint32_t blockSize); /** * @brief Q15 vector addition. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in each vector * @return none. */ void arm_add_q15( q15_t * pSrcA, q15_t * pSrcB, q15_t * pDst, uint32_t blockSize); /** * @brief Q31 vector addition. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in each vector * @return none. */ void arm_add_q31( q31_t * pSrcA, q31_t * pSrcB, q31_t * pDst, uint32_t blockSize); /** * @brief Floating-point vector subtraction. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in each vector * @return none. */ void arm_sub_f32( float32_t * pSrcA, float32_t * pSrcB, float32_t * pDst, uint32_t blockSize); /** * @brief Q7 vector subtraction. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in each vector * @return none. */ void arm_sub_q7( q7_t * pSrcA, q7_t * pSrcB, q7_t * pDst, uint32_t blockSize); /** * @brief Q15 vector subtraction. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in each vector * @return none. */ void arm_sub_q15( q15_t * pSrcA, q15_t * pSrcB, q15_t * pDst, uint32_t blockSize); /** * @brief Q31 vector subtraction. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in each vector * @return none. */ void arm_sub_q31( q31_t * pSrcA, q31_t * pSrcB, q31_t * pDst, uint32_t blockSize); /** * @brief Multiplies a floating-point vector by a scalar. * @param[in] *pSrc points to the input vector * @param[in] scale scale factor to be applied * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in the vector * @return none. */ void arm_scale_f32( float32_t * pSrc, float32_t scale, float32_t * pDst, uint32_t blockSize); /** * @brief Multiplies a Q7 vector by a scalar. * @param[in] *pSrc points to the input vector * @param[in] scaleFract fractional portion of the scale value * @param[in] shift number of bits to shift the result by * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in the vector * @return none. */ void arm_scale_q7( q7_t * pSrc, q7_t scaleFract, int8_t shift, q7_t * pDst, uint32_t blockSize); /** * @brief Multiplies a Q15 vector by a scalar. * @param[in] *pSrc points to the input vector * @param[in] scaleFract fractional portion of the scale value * @param[in] shift number of bits to shift the result by * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in the vector * @return none. */ void arm_scale_q15( q15_t * pSrc, q15_t scaleFract, int8_t shift, q15_t * pDst, uint32_t blockSize); /** * @brief Multiplies a Q31 vector by a scalar. * @param[in] *pSrc points to the input vector * @param[in] scaleFract fractional portion of the scale value * @param[in] shift number of bits to shift the result by * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in the vector * @return none. */ void arm_scale_q31( q31_t * pSrc, q31_t scaleFract, int8_t shift, q31_t * pDst, uint32_t blockSize); /** * @brief Q7 vector absolute value. * @param[in] *pSrc points to the input buffer * @param[out] *pDst points to the output buffer * @param[in] blockSize number of samples in each vector * @return none. */ void arm_abs_q7( q7_t * pSrc, q7_t * pDst, uint32_t blockSize); /** * @brief Floating-point vector absolute value. * @param[in] *pSrc points to the input buffer * @param[out] *pDst points to the output buffer * @param[in] blockSize number of samples in each vector * @return none. */ void arm_abs_f32( float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Q15 vector absolute value. * @param[in] *pSrc points to the input buffer * @param[out] *pDst points to the output buffer * @param[in] blockSize number of samples in each vector * @return none. */ void arm_abs_q15( q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Q31 vector absolute value. * @param[in] *pSrc points to the input buffer * @param[out] *pDst points to the output buffer * @param[in] blockSize number of samples in each vector * @return none. */ void arm_abs_q31( q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Dot product of floating-point vectors. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[in] blockSize number of samples in each vector * @param[out] *result output result returned here * @return none. */ void arm_dot_prod_f32( float32_t * pSrcA, float32_t * pSrcB, uint32_t blockSize, float32_t * result); /** * @brief Dot product of Q7 vectors. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[in] blockSize number of samples in each vector * @param[out] *result output result returned here * @return none. */ void arm_dot_prod_q7( q7_t * pSrcA, q7_t * pSrcB, uint32_t blockSize, q31_t * result); /** * @brief Dot product of Q15 vectors. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[in] blockSize number of samples in each vector * @param[out] *result output result returned here * @return none. */ void arm_dot_prod_q15( q15_t * pSrcA, q15_t * pSrcB, uint32_t blockSize, q63_t * result); /** * @brief Dot product of Q31 vectors. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[in] blockSize number of samples in each vector * @param[out] *result output result returned here * @return none. */ void arm_dot_prod_q31( q31_t * pSrcA, q31_t * pSrcB, uint32_t blockSize, q63_t * result); /** * @brief Shifts the elements of a Q7 vector a specified number of bits. * @param[in] *pSrc points to the input vector * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in the vector * @return none. */ void arm_shift_q7( q7_t * pSrc, int8_t shiftBits, q7_t * pDst, uint32_t blockSize); /** * @brief Shifts the elements of a Q15 vector a specified number of bits. * @param[in] *pSrc points to the input vector * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in the vector * @return none. */ void arm_shift_q15( q15_t * pSrc, int8_t shiftBits, q15_t * pDst, uint32_t blockSize); /** * @brief Shifts the elements of a Q31 vector a specified number of bits. * @param[in] *pSrc points to the input vector * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in the vector * @return none. */ void arm_shift_q31( q31_t * pSrc, int8_t shiftBits, q31_t * pDst, uint32_t blockSize); /** * @brief Adds a constant offset to a floating-point vector. * @param[in] *pSrc points to the input vector * @param[in] offset is the offset to be added * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in the vector * @return none. */ void arm_offset_f32( float32_t * pSrc, float32_t offset, float32_t * pDst, uint32_t blockSize); /** * @brief Adds a constant offset to a Q7 vector. * @param[in] *pSrc points to the input vector * @param[in] offset is the offset to be added * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in the vector * @return none. */ void arm_offset_q7( q7_t * pSrc, q7_t offset, q7_t * pDst, uint32_t blockSize); /** * @brief Adds a constant offset to a Q15 vector. * @param[in] *pSrc points to the input vector * @param[in] offset is the offset to be added * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in the vector * @return none. */ void arm_offset_q15( q15_t * pSrc, q15_t offset, q15_t * pDst, uint32_t blockSize); /** * @brief Adds a constant offset to a Q31 vector. * @param[in] *pSrc points to the input vector * @param[in] offset is the offset to be added * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in the vector * @return none. */ void arm_offset_q31( q31_t * pSrc, q31_t offset, q31_t * pDst, uint32_t blockSize); /** * @brief Negates the elements of a floating-point vector. * @param[in] *pSrc points to the input vector * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in the vector * @return none. */ void arm_negate_f32( float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Negates the elements of a Q7 vector. * @param[in] *pSrc points to the input vector * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in the vector * @return none. */ void arm_negate_q7( q7_t * pSrc, q7_t * pDst, uint32_t blockSize); /** * @brief Negates the elements of a Q15 vector. * @param[in] *pSrc points to the input vector * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in the vector * @return none. */ void arm_negate_q15( q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Negates the elements of a Q31 vector. * @param[in] *pSrc points to the input vector * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in the vector * @return none. */ void arm_negate_q31( q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Copies the elements of a floating-point vector. * @param[in] *pSrc input pointer * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ void arm_copy_f32( float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Copies the elements of a Q7 vector. * @param[in] *pSrc input pointer * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ void arm_copy_q7( q7_t * pSrc, q7_t * pDst, uint32_t blockSize); /** * @brief Copies the elements of a Q15 vector. * @param[in] *pSrc input pointer * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ void arm_copy_q15( q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Copies the elements of a Q31 vector. * @param[in] *pSrc input pointer * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ void arm_copy_q31( q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Fills a constant value into a floating-point vector. * @param[in] value input value to be filled * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ void arm_fill_f32( float32_t value, float32_t * pDst, uint32_t blockSize); /** * @brief Fills a constant value into a Q7 vector. * @param[in] value input value to be filled * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ void arm_fill_q7( q7_t value, q7_t * pDst, uint32_t blockSize); /** * @brief Fills a constant value into a Q15 vector. * @param[in] value input value to be filled * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ void arm_fill_q15( q15_t value, q15_t * pDst, uint32_t blockSize); /** * @brief Fills a constant value into a Q31 vector. * @param[in] value input value to be filled * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ void arm_fill_q31( q31_t value, q31_t * pDst, uint32_t blockSize); /** * @brief Convolution of floating-point sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. * @return none. */ void arm_conv_f32( float32_t * pSrcA, uint32_t srcALen, float32_t * pSrcB, uint32_t srcBLen, float32_t * pDst); /** * @brief Convolution of Q15 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. * @return none. */ void arm_conv_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst); /** * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. * @return none. */ void arm_conv_fast_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst); /** * @brief Convolution of Q31 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. * @return none. */ void arm_conv_q31( q31_t * pSrcA, uint32_t srcALen, q31_t * pSrcB, uint32_t srcBLen, q31_t * pDst); /** * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. * @return none. */ void arm_conv_fast_q31( q31_t * pSrcA, uint32_t srcALen, q31_t * pSrcB, uint32_t srcBLen, q31_t * pDst); /** * @brief Convolution of Q7 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. * @return none. */ void arm_conv_q7( q7_t * pSrcA, uint32_t srcALen, q7_t * pSrcB, uint32_t srcBLen, q7_t * pDst); /** * @brief Partial convolution of floating-point sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_f32( float32_t * pSrcA, uint32_t srcALen, float32_t * pSrcB, uint32_t srcBLen, float32_t * pDst, uint32_t firstIndex, uint32_t numPoints); /** * @brief Partial convolution of Q15 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst, uint32_t firstIndex, uint32_t numPoints); /** * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_fast_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst, uint32_t firstIndex, uint32_t numPoints); /** * @brief Partial convolution of Q31 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_q31( q31_t * pSrcA, uint32_t srcALen, q31_t * pSrcB, uint32_t srcBLen, q31_t * pDst, uint32_t firstIndex, uint32_t numPoints); /** * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_fast_q31( q31_t * pSrcA, uint32_t srcALen, q31_t * pSrcB, uint32_t srcBLen, q31_t * pDst, uint32_t firstIndex, uint32_t numPoints); /** * @brief Partial convolution of Q7 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_q7( q7_t * pSrcA, uint32_t srcALen, q7_t * pSrcB, uint32_t srcBLen, q7_t * pDst, uint32_t firstIndex, uint32_t numPoints); /** * @brief Instance structure for the Q15 FIR decimator. */ typedef struct { uint8_t M; /**< decimation factor. */ uint16_t numTaps; /**< number of coefficients in the filter. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ } arm_fir_decimate_instance_q15; /** * @brief Instance structure for the Q31 FIR decimator. */ typedef struct { uint8_t M; /**< decimation factor. */ uint16_t numTaps; /**< number of coefficients in the filter. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ } arm_fir_decimate_instance_q31; /** * @brief Instance structure for the floating-point FIR decimator. */ typedef struct { uint8_t M; /**< decimation factor. */ uint16_t numTaps; /**< number of coefficients in the filter. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ } arm_fir_decimate_instance_f32; /** * @brief Processing function for the floating-point FIR decimator. * @param[in] *S points to an instance of the floating-point FIR decimator structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data * @param[in] blockSize number of input samples to process per call. * @return none */ void arm_fir_decimate_f32( const arm_fir_decimate_instance_f32 * S, float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point FIR decimator. * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. * @param[in] numTaps number of coefficients in the filter. * @param[in] M decimation factor. * @param[in] *pCoeffs points to the filter coefficients. * @param[in] *pState points to the state buffer. * @param[in] blockSize number of input samples to process per call. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * blockSize is not a multiple of M. */ arm_status arm_fir_decimate_init_f32( arm_fir_decimate_instance_f32 * S, uint16_t numTaps, uint8_t M, float32_t * pCoeffs, float32_t * pState, uint32_t blockSize); /** * @brief Processing function for the Q15 FIR decimator. * @param[in] *S points to an instance of the Q15 FIR decimator structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data * @param[in] blockSize number of input samples to process per call. * @return none */ void arm_fir_decimate_q15( const arm_fir_decimate_instance_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. * @param[in] *S points to an instance of the Q15 FIR decimator structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data * @param[in] blockSize number of input samples to process per call. * @return none */ void arm_fir_decimate_fast_q15( const arm_fir_decimate_instance_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q15 FIR decimator. * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. * @param[in] numTaps number of coefficients in the filter. * @param[in] M decimation factor. * @param[in] *pCoeffs points to the filter coefficients. * @param[in] *pState points to the state buffer. * @param[in] blockSize number of input samples to process per call. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * blockSize is not a multiple of M. */ arm_status arm_fir_decimate_init_q15( arm_fir_decimate_instance_q15 * S, uint16_t numTaps, uint8_t M, q15_t * pCoeffs, q15_t * pState, uint32_t blockSize); /** * @brief Processing function for the Q31 FIR decimator. * @param[in] *S points to an instance of the Q31 FIR decimator structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data * @param[in] blockSize number of input samples to process per call. * @return none */ void arm_fir_decimate_q31( const arm_fir_decimate_instance_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. * @param[in] *S points to an instance of the Q31 FIR decimator structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data * @param[in] blockSize number of input samples to process per call. * @return none */ void arm_fir_decimate_fast_q31( arm_fir_decimate_instance_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q31 FIR decimator. * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. * @param[in] numTaps number of coefficients in the filter. * @param[in] M decimation factor. * @param[in] *pCoeffs points to the filter coefficients. * @param[in] *pState points to the state buffer. * @param[in] blockSize number of input samples to process per call. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * blockSize is not a multiple of M. */ arm_status arm_fir_decimate_init_q31( arm_fir_decimate_instance_q31 * S, uint16_t numTaps, uint8_t M, q31_t * pCoeffs, q31_t * pState, uint32_t blockSize); /** * @brief Instance structure for the Q15 FIR interpolator. */ typedef struct { uint8_t L; /**< upsample factor. */ uint16_t phaseLength; /**< length of each polyphase filter component. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ } arm_fir_interpolate_instance_q15; /** * @brief Instance structure for the Q31 FIR interpolator. */ typedef struct { uint8_t L; /**< upsample factor. */ uint16_t phaseLength; /**< length of each polyphase filter component. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ } arm_fir_interpolate_instance_q31; /** * @brief Instance structure for the floating-point FIR interpolator. */ typedef struct { uint8_t L; /**< upsample factor. */ uint16_t phaseLength; /**< length of each polyphase filter component. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ } arm_fir_interpolate_instance_f32; /** * @brief Processing function for the Q15 FIR interpolator. * @param[in] *S points to an instance of the Q15 FIR interpolator structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of input samples to process per call. * @return none. */ void arm_fir_interpolate_q15( const arm_fir_interpolate_instance_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q15 FIR interpolator. * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. * @param[in] L upsample factor. * @param[in] numTaps number of filter coefficients in the filter. * @param[in] *pCoeffs points to the filter coefficient buffer. * @param[in] *pState points to the state buffer. * @param[in] blockSize number of input samples to process per call. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * the filter length numTaps is not a multiple of the interpolation factor L. */ arm_status arm_fir_interpolate_init_q15( arm_fir_interpolate_instance_q15 * S, uint8_t L, uint16_t numTaps, q15_t * pCoeffs, q15_t * pState, uint32_t blockSize); /** * @brief Processing function for the Q31 FIR interpolator. * @param[in] *S points to an instance of the Q15 FIR interpolator structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of input samples to process per call. * @return none. */ void arm_fir_interpolate_q31( const arm_fir_interpolate_instance_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q31 FIR interpolator. * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. * @param[in] L upsample factor. * @param[in] numTaps number of filter coefficients in the filter. * @param[in] *pCoeffs points to the filter coefficient buffer. * @param[in] *pState points to the state buffer. * @param[in] blockSize number of input samples to process per call. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * the filter length numTaps is not a multiple of the interpolation factor L. */ arm_status arm_fir_interpolate_init_q31( arm_fir_interpolate_instance_q31 * S, uint8_t L, uint16_t numTaps, q31_t * pCoeffs, q31_t * pState, uint32_t blockSize); /** * @brief Processing function for the floating-point FIR interpolator. * @param[in] *S points to an instance of the floating-point FIR interpolator structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of input samples to process per call. * @return none. */ void arm_fir_interpolate_f32( const arm_fir_interpolate_instance_f32 * S, float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point FIR interpolator. * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. * @param[in] L upsample factor. * @param[in] numTaps number of filter coefficients in the filter. * @param[in] *pCoeffs points to the filter coefficient buffer. * @param[in] *pState points to the state buffer. * @param[in] blockSize number of input samples to process per call. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * the filter length numTaps is not a multiple of the interpolation factor L. */ arm_status arm_fir_interpolate_init_f32( arm_fir_interpolate_instance_f32 * S, uint8_t L, uint16_t numTaps, float32_t * pCoeffs, float32_t * pState, uint32_t blockSize); /** * @brief Instance structure for the high precision Q31 Biquad cascade filter. */ typedef struct { uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ } arm_biquad_cas_df1_32x64_ins_q31; /** * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data * @param[in] blockSize number of samples to process. * @return none. */ void arm_biquad_cas_df1_32x64_q31( const arm_biquad_cas_df1_32x64_ins_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] *pCoeffs points to the filter coefficients. * @param[in] *pState points to the state buffer. * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format * @return none */ void arm_biquad_cas_df1_32x64_init_q31( arm_biquad_cas_df1_32x64_ins_q31 * S, uint8_t numStages, q31_t * pCoeffs, q63_t * pState, uint8_t postShift); /** * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. */ typedef struct { uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ } arm_biquad_cascade_df2T_instance_f32; /** * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. * @param[in] *S points to an instance of the filter data structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data * @param[in] blockSize number of samples to process. * @return none. */ void arm_biquad_cascade_df2T_f32( const arm_biquad_cascade_df2T_instance_f32 * S, float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. * @param[in,out] *S points to an instance of the filter data structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] *pCoeffs points to the filter coefficients. * @param[in] *pState points to the state buffer. * @return none */ void arm_biquad_cascade_df2T_init_f32( arm_biquad_cascade_df2T_instance_f32 * S, uint8_t numStages, float32_t * pCoeffs, float32_t * pState); /** * @brief Instance structure for the Q15 FIR lattice filter. */ typedef struct { uint16_t numStages; /**< number of filter stages. */ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ } arm_fir_lattice_instance_q15; /** * @brief Instance structure for the Q31 FIR lattice filter. */ typedef struct { uint16_t numStages; /**< number of filter stages. */ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ } arm_fir_lattice_instance_q31; /** * @brief Instance structure for the floating-point FIR lattice filter. */ typedef struct { uint16_t numStages; /**< number of filter stages. */ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ } arm_fir_lattice_instance_f32; /** * @brief Initialization function for the Q15 FIR lattice filter. * @param[in] *S points to an instance of the Q15 FIR lattice structure. * @param[in] numStages number of filter stages. * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. * @param[in] *pState points to the state buffer. The array is of length numStages. * @return none. */ void arm_fir_lattice_init_q15( arm_fir_lattice_instance_q15 * S, uint16_t numStages, q15_t * pCoeffs, q15_t * pState); /** * @brief Processing function for the Q15 FIR lattice filter. * @param[in] *S points to an instance of the Q15 FIR lattice structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_fir_lattice_q15( const arm_fir_lattice_instance_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q31 FIR lattice filter. * @param[in] *S points to an instance of the Q31 FIR lattice structure. * @param[in] numStages number of filter stages. * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. * @param[in] *pState points to the state buffer. The array is of length numStages. * @return none. */ void arm_fir_lattice_init_q31( arm_fir_lattice_instance_q31 * S, uint16_t numStages, q31_t * pCoeffs, q31_t * pState); /** * @brief Processing function for the Q31 FIR lattice filter. * @param[in] *S points to an instance of the Q31 FIR lattice structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data * @param[in] blockSize number of samples to process. * @return none. */ void arm_fir_lattice_q31( const arm_fir_lattice_instance_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point FIR lattice filter. * @param[in] *S points to an instance of the floating-point FIR lattice structure. * @param[in] numStages number of filter stages. * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. * @param[in] *pState points to the state buffer. The array is of length numStages. * @return none. */ void arm_fir_lattice_init_f32( arm_fir_lattice_instance_f32 * S, uint16_t numStages, float32_t * pCoeffs, float32_t * pState); /** * @brief Processing function for the floating-point FIR lattice filter. * @param[in] *S points to an instance of the floating-point FIR lattice structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data * @param[in] blockSize number of samples to process. * @return none. */ void arm_fir_lattice_f32( const arm_fir_lattice_instance_f32 * S, float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Instance structure for the Q15 IIR lattice filter. */ typedef struct { uint16_t numStages; /**< number of stages in the filter. */ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ } arm_iir_lattice_instance_q15; /** * @brief Instance structure for the Q31 IIR lattice filter. */ typedef struct { uint16_t numStages; /**< number of stages in the filter. */ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ } arm_iir_lattice_instance_q31; /** * @brief Instance structure for the floating-point IIR lattice filter. */ typedef struct { uint16_t numStages; /**< number of stages in the filter. */ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ } arm_iir_lattice_instance_f32; /** * @brief Processing function for the floating-point IIR lattice filter. * @param[in] *S points to an instance of the floating-point IIR lattice structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_iir_lattice_f32( const arm_iir_lattice_instance_f32 * S, float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point IIR lattice filter. * @param[in] *S points to an instance of the floating-point IIR lattice structure. * @param[in] numStages number of stages in the filter. * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. * @param[in] blockSize number of samples to process. * @return none. */ void arm_iir_lattice_init_f32( arm_iir_lattice_instance_f32 * S, uint16_t numStages, float32_t *pkCoeffs, float32_t *pvCoeffs, float32_t *pState, uint32_t blockSize); /** * @brief Processing function for the Q31 IIR lattice filter. * @param[in] *S points to an instance of the Q31 IIR lattice structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_iir_lattice_q31( const arm_iir_lattice_instance_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q31 IIR lattice filter. * @param[in] *S points to an instance of the Q31 IIR lattice structure. * @param[in] numStages number of stages in the filter. * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. * @param[in] blockSize number of samples to process. * @return none. */ void arm_iir_lattice_init_q31( arm_iir_lattice_instance_q31 * S, uint16_t numStages, q31_t *pkCoeffs, q31_t *pvCoeffs, q31_t *pState, uint32_t blockSize); /** * @brief Processing function for the Q15 IIR lattice filter. * @param[in] *S points to an instance of the Q15 IIR lattice structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_iir_lattice_q15( const arm_iir_lattice_instance_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q15 IIR lattice filter. * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. * @param[in] numStages number of stages in the filter. * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. * @param[in] blockSize number of samples to process per call. * @return none. */ void arm_iir_lattice_init_q15( arm_iir_lattice_instance_q15 * S, uint16_t numStages, q15_t *pkCoeffs, q15_t *pvCoeffs, q15_t *pState, uint32_t blockSize); /** * @brief Instance structure for the floating-point LMS filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ float32_t mu; /**< step size that controls filter coefficient updates. */ } arm_lms_instance_f32; /** * @brief Processing function for floating-point LMS filter. * @param[in] *S points to an instance of the floating-point LMS filter structure. * @param[in] *pSrc points to the block of input data. * @param[in] *pRef points to the block of reference data. * @param[out] *pOut points to the block of output data. * @param[out] *pErr points to the block of error data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_lms_f32( const arm_lms_instance_f32 * S, float32_t * pSrc, float32_t * pRef, float32_t * pOut, float32_t * pErr, uint32_t blockSize); /** * @brief Initialization function for floating-point LMS filter. * @param[in] *S points to an instance of the floating-point LMS filter structure. * @param[in] numTaps number of filter coefficients. * @param[in] *pCoeffs points to the coefficient buffer. * @param[in] *pState points to state buffer. * @param[in] mu step size that controls filter coefficient updates. * @param[in] blockSize number of samples to process. * @return none. */ void arm_lms_init_f32( arm_lms_instance_f32 * S, uint16_t numTaps, float32_t * pCoeffs, float32_t * pState, float32_t mu, uint32_t blockSize); /** * @brief Instance structure for the Q15 LMS filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ q15_t mu; /**< step size that controls filter coefficient updates. */ uint32_t postShift; /**< bit shift applied to coefficients. */ } arm_lms_instance_q15; /** * @brief Initialization function for the Q15 LMS filter. * @param[in] *S points to an instance of the Q15 LMS filter structure. * @param[in] numTaps number of filter coefficients. * @param[in] *pCoeffs points to the coefficient buffer. * @param[in] *pState points to the state buffer. * @param[in] mu step size that controls filter coefficient updates. * @param[in] blockSize number of samples to process. * @param[in] postShift bit shift applied to coefficients. * @return none. */ void arm_lms_init_q15( arm_lms_instance_q15 * S, uint16_t numTaps, q15_t * pCoeffs, q15_t * pState, q15_t mu, uint32_t blockSize, uint32_t postShift); /** * @brief Processing function for Q15 LMS filter. * @param[in] *S points to an instance of the Q15 LMS filter structure. * @param[in] *pSrc points to the block of input data. * @param[in] *pRef points to the block of reference data. * @param[out] *pOut points to the block of output data. * @param[out] *pErr points to the block of error data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_lms_q15( const arm_lms_instance_q15 * S, q15_t * pSrc, q15_t * pRef, q15_t * pOut, q15_t * pErr, uint32_t blockSize); /** * @brief Instance structure for the Q31 LMS filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ q31_t mu; /**< step size that controls filter coefficient updates. */ uint32_t postShift; /**< bit shift applied to coefficients. */ } arm_lms_instance_q31; /** * @brief Processing function for Q31 LMS filter. * @param[in] *S points to an instance of the Q15 LMS filter structure. * @param[in] *pSrc points to the block of input data. * @param[in] *pRef points to the block of reference data. * @param[out] *pOut points to the block of output data. * @param[out] *pErr points to the block of error data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_lms_q31( const arm_lms_instance_q31 * S, q31_t * pSrc, q31_t * pRef, q31_t * pOut, q31_t * pErr, uint32_t blockSize); /** * @brief Initialization function for Q31 LMS filter. * @param[in] *S points to an instance of the Q31 LMS filter structure. * @param[in] numTaps number of filter coefficients. * @param[in] *pCoeffs points to coefficient buffer. * @param[in] *pState points to state buffer. * @param[in] mu step size that controls filter coefficient updates. * @param[in] blockSize number of samples to process. * @param[in] postShift bit shift applied to coefficients. * @return none. */ void arm_lms_init_q31( arm_lms_instance_q31 * S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, q31_t mu, uint32_t blockSize, uint32_t postShift); /** * @brief Instance structure for the floating-point normalized LMS filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ float32_t mu; /**< step size that control filter coefficient updates. */ float32_t energy; /**< saves previous frame energy. */ float32_t x0; /**< saves previous input sample. */ } arm_lms_norm_instance_f32; /** * @brief Processing function for floating-point normalized LMS filter. * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. * @param[in] *pSrc points to the block of input data. * @param[in] *pRef points to the block of reference data. * @param[out] *pOut points to the block of output data. * @param[out] *pErr points to the block of error data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_lms_norm_f32( arm_lms_norm_instance_f32 * S, float32_t * pSrc, float32_t * pRef, float32_t * pOut, float32_t * pErr, uint32_t blockSize); /** * @brief Initialization function for floating-point normalized LMS filter. * @param[in] *S points to an instance of the floating-point LMS filter structure. * @param[in] numTaps number of filter coefficients. * @param[in] *pCoeffs points to coefficient buffer. * @param[in] *pState points to state buffer. * @param[in] mu step size that controls filter coefficient updates. * @param[in] blockSize number of samples to process. * @return none. */ void arm_lms_norm_init_f32( arm_lms_norm_instance_f32 * S, uint16_t numTaps, float32_t * pCoeffs, float32_t * pState, float32_t mu, uint32_t blockSize); /** * @brief Instance structure for the Q31 normalized LMS filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ q31_t mu; /**< step size that controls filter coefficient updates. */ uint8_t postShift; /**< bit shift applied to coefficients. */ q31_t *recipTable; /**< points to the reciprocal initial value table. */ q31_t energy; /**< saves previous frame energy. */ q31_t x0; /**< saves previous input sample. */ } arm_lms_norm_instance_q31; /** * @brief Processing function for Q31 normalized LMS filter. * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. * @param[in] *pSrc points to the block of input data. * @param[in] *pRef points to the block of reference data. * @param[out] *pOut points to the block of output data. * @param[out] *pErr points to the block of error data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_lms_norm_q31( arm_lms_norm_instance_q31 * S, q31_t * pSrc, q31_t * pRef, q31_t * pOut, q31_t * pErr, uint32_t blockSize); /** * @brief Initialization function for Q31 normalized LMS filter. * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. * @param[in] numTaps number of filter coefficients. * @param[in] *pCoeffs points to coefficient buffer. * @param[in] *pState points to state buffer. * @param[in] mu step size that controls filter coefficient updates. * @param[in] blockSize number of samples to process. * @param[in] postShift bit shift applied to coefficients. * @return none. */ void arm_lms_norm_init_q31( arm_lms_norm_instance_q31 * S, uint16_t numTaps, q31_t * pCoeffs, q31_t * pState, q31_t mu, uint32_t blockSize, uint8_t postShift); /** * @brief Instance structure for the Q15 normalized LMS filter. */ typedef struct { uint16_t numTaps; /**< Number of coefficients in the filter. */ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ q15_t mu; /**< step size that controls filter coefficient updates. */ uint8_t postShift; /**< bit shift applied to coefficients. */ q15_t *recipTable; /**< Points to the reciprocal initial value table. */ q15_t energy; /**< saves previous frame energy. */ q15_t x0; /**< saves previous input sample. */ } arm_lms_norm_instance_q15; /** * @brief Processing function for Q15 normalized LMS filter. * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. * @param[in] *pSrc points to the block of input data. * @param[in] *pRef points to the block of reference data. * @param[out] *pOut points to the block of output data. * @param[out] *pErr points to the block of error data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_lms_norm_q15( arm_lms_norm_instance_q15 * S, q15_t * pSrc, q15_t * pRef, q15_t * pOut, q15_t * pErr, uint32_t blockSize); /** * @brief Initialization function for Q15 normalized LMS filter. * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. * @param[in] numTaps number of filter coefficients. * @param[in] *pCoeffs points to coefficient buffer. * @param[in] *pState points to state buffer. * @param[in] mu step size that controls filter coefficient updates. * @param[in] blockSize number of samples to process. * @param[in] postShift bit shift applied to coefficients. * @return none. */ void arm_lms_norm_init_q15( arm_lms_norm_instance_q15 * S, uint16_t numTaps, q15_t * pCoeffs, q15_t * pState, q15_t mu, uint32_t blockSize, uint8_t postShift); /** * @brief Correlation of floating-point sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. * @return none. */ void arm_correlate_f32( float32_t * pSrcA, uint32_t srcALen, float32_t * pSrcB, uint32_t srcBLen, float32_t * pDst); /** * @brief Correlation of Q15 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. * @return none. */ void arm_correlate_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst); /** * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. * @return none. */ void arm_correlate_fast_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst); /** * @brief Correlation of Q31 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. * @return none. */ void arm_correlate_q31( q31_t * pSrcA, uint32_t srcALen, q31_t * pSrcB, uint32_t srcBLen, q31_t * pDst); /** * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. * @return none. */ void arm_correlate_fast_q31( q31_t * pSrcA, uint32_t srcALen, q31_t * pSrcB, uint32_t srcBLen, q31_t * pDst); /** * @brief Correlation of Q7 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. * @return none. */ void arm_correlate_q7( q7_t * pSrcA, uint32_t srcALen, q7_t * pSrcB, uint32_t srcBLen, q7_t * pDst); /** * @brief Instance structure for the floating-point sparse FIR filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ } arm_fir_sparse_instance_f32; /** * @brief Instance structure for the Q31 sparse FIR filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ } arm_fir_sparse_instance_q31; /** * @brief Instance structure for the Q15 sparse FIR filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ } arm_fir_sparse_instance_q15; /** * @brief Instance structure for the Q7 sparse FIR filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ } arm_fir_sparse_instance_q7; /** * @brief Processing function for the floating-point sparse FIR filter. * @param[in] *S points to an instance of the floating-point sparse FIR structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data * @param[in] *pScratchIn points to a temporary buffer of size blockSize. * @param[in] blockSize number of input samples to process per call. * @return none. */ void arm_fir_sparse_f32( arm_fir_sparse_instance_f32 * S, float32_t * pSrc, float32_t * pDst, float32_t * pScratchIn, uint32_t blockSize); /** * @brief Initialization function for the floating-point sparse FIR filter. * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. * @param[in] numTaps number of nonzero coefficients in the filter. * @param[in] *pCoeffs points to the array of filter coefficients. * @param[in] *pState points to the state buffer. * @param[in] *pTapDelay points to the array of offset times. * @param[in] maxDelay maximum offset time supported. * @param[in] blockSize number of samples that will be processed per block. * @return none */ void arm_fir_sparse_init_f32( arm_fir_sparse_instance_f32 * S, uint16_t numTaps, float32_t * pCoeffs, float32_t * pState, int32_t * pTapDelay, uint16_t maxDelay, uint32_t blockSize); /** * @brief Processing function for the Q31 sparse FIR filter. * @param[in] *S points to an instance of the Q31 sparse FIR structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data * @param[in] *pScratchIn points to a temporary buffer of size blockSize. * @param[in] blockSize number of input samples to process per call. * @return none. */ void arm_fir_sparse_q31( arm_fir_sparse_instance_q31 * S, q31_t * pSrc, q31_t * pDst, q31_t * pScratchIn, uint32_t blockSize); /** * @brief Initialization function for the Q31 sparse FIR filter. * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. * @param[in] numTaps number of nonzero coefficients in the filter. * @param[in] *pCoeffs points to the array of filter coefficients. * @param[in] *pState points to the state buffer. * @param[in] *pTapDelay points to the array of offset times. * @param[in] maxDelay maximum offset time supported. * @param[in] blockSize number of samples that will be processed per block. * @return none */ void arm_fir_sparse_init_q31( arm_fir_sparse_instance_q31 * S, uint16_t numTaps, q31_t * pCoeffs, q31_t * pState, int32_t * pTapDelay, uint16_t maxDelay, uint32_t blockSize); /** * @brief Processing function for the Q15 sparse FIR filter. * @param[in] *S points to an instance of the Q15 sparse FIR structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data * @param[in] *pScratchIn points to a temporary buffer of size blockSize. * @param[in] *pScratchOut points to a temporary buffer of size blockSize. * @param[in] blockSize number of input samples to process per call. * @return none. */ void arm_fir_sparse_q15( arm_fir_sparse_instance_q15 * S, q15_t * pSrc, q15_t * pDst, q15_t * pScratchIn, q31_t * pScratchOut, uint32_t blockSize); /** * @brief Initialization function for the Q15 sparse FIR filter. * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. * @param[in] numTaps number of nonzero coefficients in the filter. * @param[in] *pCoeffs points to the array of filter coefficients. * @param[in] *pState points to the state buffer. * @param[in] *pTapDelay points to the array of offset times. * @param[in] maxDelay maximum offset time supported. * @param[in] blockSize number of samples that will be processed per block. * @return none */ void arm_fir_sparse_init_q15( arm_fir_sparse_instance_q15 * S, uint16_t numTaps, q15_t * pCoeffs, q15_t * pState, int32_t * pTapDelay, uint16_t maxDelay, uint32_t blockSize); /** * @brief Processing function for the Q7 sparse FIR filter. * @param[in] *S points to an instance of the Q7 sparse FIR structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data * @param[in] *pScratchIn points to a temporary buffer of size blockSize. * @param[in] *pScratchOut points to a temporary buffer of size blockSize. * @param[in] blockSize number of input samples to process per call. * @return none. */ void arm_fir_sparse_q7( arm_fir_sparse_instance_q7 * S, q7_t * pSrc, q7_t * pDst, q7_t * pScratchIn, q31_t * pScratchOut, uint32_t blockSize); /** * @brief Initialization function for the Q7 sparse FIR filter. * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. * @param[in] numTaps number of nonzero coefficients in the filter. * @param[in] *pCoeffs points to the array of filter coefficients. * @param[in] *pState points to the state buffer. * @param[in] *pTapDelay points to the array of offset times. * @param[in] maxDelay maximum offset time supported. * @param[in] blockSize number of samples that will be processed per block. * @return none */ void arm_fir_sparse_init_q7( arm_fir_sparse_instance_q7 * S, uint16_t numTaps, q7_t * pCoeffs, q7_t * pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize); /* * @brief Floating-point sin_cos function. * @param[in] theta input value in degrees * @param[out] *pSinVal points to the processed sine output. * @param[out] *pCosVal points to the processed cos output. * @return none. */ void arm_sin_cos_f32( float32_t theta, float32_t *pSinVal, float32_t *pCcosVal); /* * @brief Q31 sin_cos function. * @param[in] theta scaled input value in degrees * @param[out] *pSinVal points to the processed sine output. * @param[out] *pCosVal points to the processed cosine output. * @return none. */ void arm_sin_cos_q31( q31_t theta, q31_t *pSinVal, q31_t *pCosVal); /** * @brief Floating-point complex conjugate. * @param[in] *pSrc points to the input vector * @param[out] *pDst points to the output vector * @param[in] numSamples number of complex samples in each vector * @return none. */ void arm_cmplx_conj_f32( float32_t * pSrc, float32_t * pDst, uint32_t numSamples); /** * @brief Q31 complex conjugate. * @param[in] *pSrc points to the input vector * @param[out] *pDst points to the output vector * @param[in] numSamples number of complex samples in each vector * @return none. */ void arm_cmplx_conj_q31( q31_t * pSrc, q31_t * pDst, uint32_t numSamples); /** * @brief Q15 complex conjugate. * @param[in] *pSrc points to the input vector * @param[out] *pDst points to the output vector * @param[in] numSamples number of complex samples in each vector * @return none. */ void arm_cmplx_conj_q15( q15_t * pSrc, q15_t * pDst, uint32_t numSamples); /** * @brief Floating-point complex magnitude squared * @param[in] *pSrc points to the complex input vector * @param[out] *pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector * @return none. */ void arm_cmplx_mag_squared_f32( float32_t * pSrc, float32_t * pDst, uint32_t numSamples); /** * @brief Q31 complex magnitude squared * @param[in] *pSrc points to the complex input vector * @param[out] *pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector * @return none. */ void arm_cmplx_mag_squared_q31( q31_t * pSrc, q31_t * pDst, uint32_t numSamples); /** * @brief Q15 complex magnitude squared * @param[in] *pSrc points to the complex input vector * @param[out] *pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector * @return none. */ void arm_cmplx_mag_squared_q15( q15_t * pSrc, q15_t * pDst, uint32_t numSamples); /** * @ingroup groupController */ /** * @defgroup PID PID Motor Control * * A Proportional Integral Derivative (PID) controller is a generic feedback control * loop mechanism widely used in industrial control systems. * A PID controller is the most commonly used type of feedback controller. * * This set of functions implements (PID) controllers * for Q15, Q31, and floating-point data types. The functions operate on a single sample * of data and each call to the function returns a single processed value. * S points to an instance of the PID control data structure. in * is the input sample value. The functions return the output value. * * \par Algorithm: * 
   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
   *    A0 = Kp + Ki + Kd
   *    A1 = (-Kp ) - (2 * Kd )
   *    A2 = Kd
* * \par * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant * * \par * \image html PID.gif "Proportional Integral Derivative Controller" * * \par * The PID controller calculates an "error" value as the difference between * the measured output and the reference input. * The controller attempts to minimize the error by adjusting the process control inputs. * The proportional value determines the reaction to the current error, * the integral value determines the reaction based on the sum of recent errors, * and the derivative value determines the reaction based on the rate at which the error has been changing. * * \par Instance Structure * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. * A separate instance structure must be defined for each PID Controller. * There are separate instance structure declarations for each of the 3 supported data types. * * \par Reset Functions * There is also an associated reset function for each data type which clears the state array. * * \par Initialization Functions * There is also an associated initialization function for each data type. * The initialization function performs the following operations: * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. * - Zeros out the values in the state buffer. * * \par * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. * * \par Fixed-Point Behavior * Care must be taken when using the fixed-point versions of the PID Controller functions. * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. * Refer to the function specific documentation below for usage guidelines. */ /** * @addtogroup PID * @{ */ /** * @brief Process function for the floating-point PID Control. * @param[in,out] *S is an instance of the floating-point PID Control structure * @param[in] in input sample to process * @return out processed output sample. */ static __INLINE float32_t arm_pid_f32( arm_pid_instance_f32 * S, float32_t in) { float32_t out; /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ out = (S->A0 * in) + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); /* Update state */ S->state[1] = S->state[0]; S->state[0] = in; S->state[2] = out; /* return to application */ return (out); } /** * @brief Process function for the Q31 PID Control. * @param[in,out] *S points to an instance of the Q31 PID Control structure * @param[in] in input sample to process * @return out processed output sample. * * Scaling and Overflow Behavior: * \par * The function is implemented using an internal 64-bit accumulator. * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. * Thus, if the accumulator result overflows it wraps around rather than clip. * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. */ static __INLINE q31_t arm_pid_q31( arm_pid_instance_q31 * S, q31_t in) { q63_t acc; q31_t out; /* acc = A0 * x[n] */ acc = (q63_t) S->A0 * in; /* acc += A1 * x[n-1] */ acc += (q63_t) S->A1 * S->state[0]; /* acc += A2 * x[n-2] */ acc += (q63_t) S->A2 * S->state[1]; /* convert output to 1.31 format to add y[n-1] */ out = (q31_t) (acc >> 31u); /* out += y[n-1] */ out += S->state[2]; /* Update state */ S->state[1] = S->state[0]; S->state[0] = in; S->state[2] = out; /* return to application */ return (out); } /** * @brief Process function for the Q15 PID Control. * @param[in,out] *S points to an instance of the Q15 PID Control structure * @param[in] in input sample to process * @return out processed output sample. * * Scaling and Overflow Behavior: * \par * The function is implemented using a 64-bit internal accumulator. * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. * Lastly, the accumulator is saturated to yield a result in 1.15 format. */ static __INLINE q15_t arm_pid_q15( arm_pid_instance_q15 * S, q15_t in) { q63_t acc; q15_t out; /* Implementation of PID controller */ #ifdef ARM_MATH_CM0 /* acc = A0 * x[n] */ acc = ((q31_t) S->A0 )* in ; #else /* acc = A0 * x[n] */ acc = (q31_t) __SMUAD(S->A0, in); #endif #ifdef ARM_MATH_CM0 /* acc += A1 * x[n-1] + A2 * x[n-2] */ acc += (q31_t) S->A1 * S->state[0] ; acc += (q31_t) S->A2 * S->state[1] ; #else /* acc += A1 * x[n-1] + A2 * x[n-2] */ acc = __SMLALD(S->A1, (q31_t)__SIMD32(S->state), acc); #endif /* acc += y[n-1] */ acc += (q31_t) S->state[2] << 15; /* saturate the output */ out = (q15_t) (__SSAT((acc >> 15), 16)); /* Update state */ S->state[1] = S->state[0]; S->state[0] = in; S->state[2] = out; /* return to application */ return (out); } /** * @} end of PID group */ /** * @brief Floating-point matrix inverse. * @param[in] *src points to the instance of the input floating-point matrix structure. * @param[out] *dst points to the instance of the output floating-point matrix structure. * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. */ arm_status arm_mat_inverse_f32( const arm_matrix_instance_f32 * src, arm_matrix_instance_f32 * dst); /** * @ingroup groupController */ /** * @defgroup clarke Vector Clarke Transform * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents * in the two-phase orthogonal stator axis Ialpha and Ibeta. * When Ialpha is superposed with Ia as shown in the figure below * \image html clarke.gif Stator current space vector and its components in (a,b). * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta * can be calculated using only Ia and Ib. * * The function operates on a single sample of data and each call to the function returns the processed output. * The library provides separate functions for Q31 and floating-point data types. * \par Algorithm * \image html clarkeFormula.gif * where Ia and Ib are the instantaneous stator phases and * pIalpha and pIbeta are the two coordinates of time invariant vector. * \par Fixed-Point Behavior * Care must be taken when using the Q31 version of the Clarke transform. * In particular, the overflow and saturation behavior of the accumulator used must be considered. * Refer to the function specific documentation below for usage guidelines. */ /** * @addtogroup clarke * @{ */ /** * * @brief Floating-point Clarke transform * @param[in] Ia input three-phase coordinate a * @param[in] Ib input three-phase coordinate b * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta * @return none. */ static __INLINE void arm_clarke_f32( float32_t Ia, float32_t Ib, float32_t * pIalpha, float32_t * pIbeta) { /* Calculate pIalpha using the equation, pIalpha = Ia */ *pIalpha = Ia; /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); } /** * @brief Clarke transform for Q31 version * @param[in] Ia input three-phase coordinate a * @param[in] Ib input three-phase coordinate b * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta * @return none. * * Scaling and Overflow Behavior: * \par * The function is implemented using an internal 32-bit accumulator. * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. * There is saturation on the addition, hence there is no risk of overflow. */ static __INLINE void arm_clarke_q31( q31_t Ia, q31_t Ib, q31_t * pIalpha, q31_t * pIbeta) { q31_t product1, product2; /* Temporary variables used to store intermediate results */ /* Calculating pIalpha from Ia by equation pIalpha = Ia */ *pIalpha = Ia; /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); /* pIbeta is calculated by adding the intermediate products */ *pIbeta = __QADD(product1, product2); } /** * @} end of clarke group */ /** * @brief Converts the elements of the Q7 vector to Q31 vector. * @param[in] *pSrc input pointer * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ void arm_q7_to_q31( q7_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @ingroup groupController */ /** * @defgroup inv_clarke Vector Inverse Clarke Transform * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. * * The function operates on a single sample of data and each call to the function returns the processed output. * The library provides separate functions for Q31 and floating-point data types. * \par Algorithm * \image html clarkeInvFormula.gif * where pIa and pIb are the instantaneous stator phases and * Ialpha and Ibeta are the two coordinates of time invariant vector. * \par Fixed-Point Behavior * Care must be taken when using the Q31 version of the Clarke transform. * In particular, the overflow and saturation behavior of the accumulator used must be considered. * Refer to the function specific documentation below for usage guidelines. */ /** * @addtogroup inv_clarke * @{ */ /** * @brief Floating-point Inverse Clarke transform * @param[in] Ialpha input two-phase orthogonal vector axis alpha * @param[in] Ibeta input two-phase orthogonal vector axis beta * @param[out] *pIa points to output three-phase coordinate a * @param[out] *pIb points to output three-phase coordinate b * @return none. */ static __INLINE void arm_inv_clarke_f32( float32_t Ialpha, float32_t Ibeta, float32_t * pIa, float32_t * pIb) { /* Calculating pIa from Ialpha by equation pIa = Ialpha */ *pIa = Ialpha; /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; } /** * @brief Inverse Clarke transform for Q31 version * @param[in] Ialpha input two-phase orthogonal vector axis alpha * @param[in] Ibeta input two-phase orthogonal vector axis beta * @param[out] *pIa points to output three-phase coordinate a * @param[out] *pIb points to output three-phase coordinate b * @return none. * * Scaling and Overflow Behavior: * \par * The function is implemented using an internal 32-bit accumulator. * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. * There is saturation on the subtraction, hence there is no risk of overflow. */ static __INLINE void arm_inv_clarke_q31( q31_t Ialpha, q31_t Ibeta, q31_t * pIa, q31_t * pIb) { q31_t product1, product2; /* Temporary variables used to store intermediate results */ /* Calculating pIa from Ialpha by equation pIa = Ialpha */ *pIa = Ialpha; /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); /* pIb is calculated by subtracting the products */ *pIb = __QSUB(product2, product1); } /** * @} end of inv_clarke group */ /** * @brief Converts the elements of the Q7 vector to Q15 vector. * @param[in] *pSrc input pointer * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ void arm_q7_to_q15( q7_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @ingroup groupController */ /** * @defgroup park Vector Park Transform * * Forward Park transform converts the input two-coordinate vector to flux and torque components. * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents * from the stationary to the moving reference frame and control the spatial relationship between * the stator vector current and rotor flux vector. * If we consider the d axis aligned with the rotor flux, the diagram below shows the * current vector and the relationship from the two reference frames: * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" * * The function operates on a single sample of data and each call to the function returns the processed output. * The library provides separate functions for Q31 and floating-point data types. * \par Algorithm * \image html parkFormula.gif * where Ialpha and Ibeta are the stator vector components, * pId and pIq are rotor vector components and cosVal and sinVal are the * cosine and sine values of theta (rotor flux position). * \par Fixed-Point Behavior * Care must be taken when using the Q31 version of the Park transform. * In particular, the overflow and saturation behavior of the accumulator used must be considered. * Refer to the function specific documentation below for usage guidelines. */ /** * @addtogroup park * @{ */ /** * @brief Floating-point Park transform * @param[in] Ialpha input two-phase vector coordinate alpha * @param[in] Ibeta input two-phase vector coordinate beta * @param[out] *pId points to output rotor reference frame d * @param[out] *pIq points to output rotor reference frame q * @param[in] sinVal sine value of rotation angle theta * @param[in] cosVal cosine value of rotation angle theta * @return none. * * The function implements the forward Park transform. * */ static __INLINE void arm_park_f32( float32_t Ialpha, float32_t Ibeta, float32_t * pId, float32_t * pIq, float32_t sinVal, float32_t cosVal) { /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ *pId = Ialpha * cosVal + Ibeta * sinVal; /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ *pIq = -Ialpha * sinVal + Ibeta * cosVal; } /** * @brief Park transform for Q31 version * @param[in] Ialpha input two-phase vector coordinate alpha * @param[in] Ibeta input two-phase vector coordinate beta * @param[out] *pId points to output rotor reference frame d * @param[out] *pIq points to output rotor reference frame q * @param[in] sinVal sine value of rotation angle theta * @param[in] cosVal cosine value of rotation angle theta * @return none. * * Scaling and Overflow Behavior: * \par * The function is implemented using an internal 32-bit accumulator. * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. * There is saturation on the addition and subtraction, hence there is no risk of overflow. */ static __INLINE void arm_park_q31( q31_t Ialpha, q31_t Ibeta, q31_t * pId, q31_t * pIq, q31_t sinVal, q31_t cosVal) { q31_t product1, product2; /* Temporary variables used to store intermediate results */ q31_t product3, product4; /* Temporary variables used to store intermediate results */ /* Intermediate product is calculated by (Ialpha * cosVal) */ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); /* Intermediate product is calculated by (Ibeta * sinVal) */ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); /* Intermediate product is calculated by (Ialpha * sinVal) */ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); /* Intermediate product is calculated by (Ibeta * cosVal) */ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); /* Calculate pId by adding the two intermediate products 1 and 2 */ *pId = __QADD(product1, product2); /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ *pIq = __QSUB(product4, product3); } /** * @} end of park group */ /** * @brief Converts the elements of the Q7 vector to floating-point vector. * @param[in] *pSrc is input pointer * @param[out] *pDst is output pointer * @param[in] blockSize is the number of samples to process * @return none. */ void arm_q7_to_float( q7_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @ingroup groupController */ /** * @defgroup inv_park Vector Inverse Park transform * Inverse Park transform converts the input flux and torque components to two-coordinate vector. * * The function operates on a single sample of data and each call to the function returns the processed output. * The library provides separate functions for Q31 and floating-point data types. * \par Algorithm * \image html parkInvFormula.gif * where pIalpha and pIbeta are the stator vector components, * Id and Iq are rotor vector components and cosVal and sinVal are the * cosine and sine values of theta (rotor flux position). * \par Fixed-Point Behavior * Care must be taken when using the Q31 version of the Park transform. * In particular, the overflow and saturation behavior of the accumulator used must be considered. * Refer to the function specific documentation below for usage guidelines. */ /** * @addtogroup inv_park * @{ */ /** * @brief Floating-point Inverse Park transform * @param[in] Id input coordinate of rotor reference frame d * @param[in] Iq input coordinate of rotor reference frame q * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta * @param[in] sinVal sine value of rotation angle theta * @param[in] cosVal cosine value of rotation angle theta * @return none. */ static __INLINE void arm_inv_park_f32( float32_t Id, float32_t Iq, float32_t * pIalpha, float32_t * pIbeta, float32_t sinVal, float32_t cosVal) { /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ *pIalpha = Id * cosVal - Iq * sinVal; /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ *pIbeta = Id * sinVal + Iq * cosVal; } /** * @brief Inverse Park transform for Q31 version * @param[in] Id input coordinate of rotor reference frame d * @param[in] Iq input coordinate of rotor reference frame q * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta * @param[in] sinVal sine value of rotation angle theta * @param[in] cosVal cosine value of rotation angle theta * @return none. * * Scaling and Overflow Behavior: * \par * The function is implemented using an internal 32-bit accumulator. * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. * There is saturation on the addition, hence there is no risk of overflow. */ static __INLINE void arm_inv_park_q31( q31_t Id, q31_t Iq, q31_t * pIalpha, q31_t * pIbeta, q31_t sinVal, q31_t cosVal) { q31_t product1, product2; /* Temporary variables used to store intermediate results */ q31_t product3, product4; /* Temporary variables used to store intermediate results */ /* Intermediate product is calculated by (Id * cosVal) */ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); /* Intermediate product is calculated by (Iq * sinVal) */ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); /* Intermediate product is calculated by (Id * sinVal) */ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); /* Intermediate product is calculated by (Iq * cosVal) */ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); /* Calculate pIalpha by using the two intermediate products 1 and 2 */ *pIalpha = __QSUB(product1, product2); /* Calculate pIbeta by using the two intermediate products 3 and 4 */ *pIbeta = __QADD(product4, product3); } /** * @} end of Inverse park group */ /** * @brief Converts the elements of the Q31 vector to floating-point vector. * @param[in] *pSrc is input pointer * @param[out] *pDst is output pointer * @param[in] blockSize is the number of samples to process * @return none. */ void arm_q31_to_float( q31_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @ingroup groupInterpolation */ /** * @defgroup LinearInterpolate Linear Interpolation * * Linear interpolation is a method of curve fitting using linear polynomials. * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line * * \par * \image html LinearInterp.gif "Linear interpolation" * * \par * A Linear Interpolate function calculates an output value(y), for the input(x) * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) * * \par Algorithm: * 
   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
   *       where x0, x1 are nearest values of input x
   *             y0, y1 are nearest values to output y
   *
* * \par * This set of functions implements Linear interpolation process * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single * sample of data and each call to the function returns a single processed value. * S points to an instance of the Linear Interpolate function data structure. * x is the input sample value. The functions returns the output value. * * \par * if x is outside of the table boundary, Linear interpolation returns first value of the table * if x is below input range and returns last value of table if x is above range. */ /** * @addtogroup LinearInterpolate * @{ */ /** * @brief Process function for the floating-point Linear Interpolation Function. * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure * @param[in] x input sample to process * @return y processed output sample. * */ static __INLINE float32_t arm_linear_interp_f32( arm_linear_interp_instance_f32 * S, float32_t x) { float32_t y; float32_t x0, x1; /* Nearest input values */ float32_t y0, y1; /* Nearest output values */ float32_t xSpacing = S->xSpacing; /* spacing between input values */ int32_t i; /* Index variable */ float32_t *pYData = S->pYData; /* pointer to output table */ /* Calculation of index */ i = (x - S->x1) / xSpacing; if(i < 0) { /* Iniatilize output for below specified range as least output value of table */ y = pYData[0]; } else if(i >= S->nValues) { /* Iniatilize output for above specified range as last output value of table */ y = pYData[S->nValues-1]; } else { /* Calculation of nearest input values */ x0 = S->x1 + i * xSpacing; x1 = S->x1 + (i +1) * xSpacing; /* Read of nearest output values */ y0 = pYData[i]; y1 = pYData[i + 1]; /* Calculation of output */ y = y0 + (x - x0) * ((y1 - y0)/(x1-x0)); } /* returns output value */ return (y); } /** * * @brief Process function for the Q31 Linear Interpolation Function. * @param[in] *pYData pointer to Q31 Linear Interpolation table * @param[in] x input sample to process * @param[in] nValues number of table values * @return y processed output sample. * * \par * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. * This function can support maximum of table size 2^12. * */ static __INLINE q31_t arm_linear_interp_q31(q31_t *pYData, q31_t x, uint32_t nValues) { q31_t y; /* output */ q31_t y0, y1; /* Nearest output values */ q31_t fract; /* fractional part */ int32_t index; /* Index to read nearest output values */ /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ index = ((x & 0xFFF00000) >> 20); if(index >= (nValues - 1)) { return(pYData[nValues - 1]); } else if(index < 0) { return(pYData[0]); } else { /* 20 bits for the fractional part */ /* shift left by 11 to keep fract in 1.31 format */ fract = (x & 0x000FFFFF) << 11; /* Read two nearest output values from the index in 1.31(q31) format */ y0 = pYData[index]; y1 = pYData[index + 1u]; /* Calculation of y0 * (1-fract) and y is in 2.30 format */ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ y += ((q31_t) (((q63_t) y1 * fract) >> 32)); /* Convert y to 1.31 format */ return (y << 1u); } } /** * * @brief Process function for the Q15 Linear Interpolation Function. * @param[in] *pYData pointer to Q15 Linear Interpolation table * @param[in] x input sample to process * @param[in] nValues number of table values * @return y processed output sample. * * \par * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. * This function can support maximum of table size 2^12. * */ static __INLINE q15_t arm_linear_interp_q15(q15_t *pYData, q31_t x, uint32_t nValues) { q63_t y; /* output */ q15_t y0, y1; /* Nearest output values */ q31_t fract; /* fractional part */ int32_t index; /* Index to read nearest output values */ /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ index = ((x & 0xFFF00000) >> 20u); if(index >= (nValues - 1)) { return(pYData[nValues - 1]); } else if(index < 0) { return(pYData[0]); } else { /* 20 bits for the fractional part */ /* fract is in 12.20 format */ fract = (x & 0x000FFFFF); /* Read two nearest output values from the index */ y0 = pYData[index]; y1 = pYData[index + 1u]; /* Calculation of y0 * (1-fract) and y is in 13.35 format */ y = ((q63_t) y0 * (0xFFFFF - fract)); /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ y += ((q63_t) y1 * (fract)); /* convert y to 1.15 format */ return (y >> 20); } } /** * * @brief Process function for the Q7 Linear Interpolation Function. * @param[in] *pYData pointer to Q7 Linear Interpolation table * @param[in] x input sample to process * @param[in] nValues number of table values * @return y processed output sample. * * \par * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. * This function can support maximum of table size 2^12. */ static __INLINE q7_t arm_linear_interp_q7(q7_t *pYData, q31_t x, uint32_t nValues) { q31_t y; /* output */ q7_t y0, y1; /* Nearest output values */ q31_t fract; /* fractional part */ int32_t index; /* Index to read nearest output values */ /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ index = ((x & 0xFFF00000) >> 20u); if(index >= (nValues - 1)) { return(pYData[nValues - 1]); } else if(index < 0) { return(pYData[0]); } else { /* 20 bits for the fractional part */ /* fract is in 12.20 format */ fract = (x & 0x000FFFFF); /* Read two nearest output values from the index and are in 1.7(q7) format */ y0 = pYData[index]; y1 = pYData[index + 1u]; /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ y = ((y0 * (0xFFFFF - fract))); /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ y += (y1 * fract); /* convert y to 1.7(q7) format */ return (y >> 20u); } } /** * @} end of LinearInterpolate group */ /** * @brief Fast approximation to the trigonometric sine function for floating-point data. * @param[in] x input value in radians. * @return sin(x). */ float32_t arm_sin_f32( float32_t x); /** * @brief Fast approximation to the trigonometric sine function for Q31 data. * @param[in] x Scaled input value in radians. * @return sin(x). */ q31_t arm_sin_q31( q31_t x); /** * @brief Fast approximation to the trigonometric sine function for Q15 data. * @param[in] x Scaled input value in radians. * @return sin(x). */ q15_t arm_sin_q15( q15_t x); /** * @brief Fast approximation to the trigonometric cosine function for floating-point data. * @param[in] x input value in radians. * @return cos(x). */ float32_t arm_cos_f32( float32_t x); /** * @brief Fast approximation to the trigonometric cosine function for Q31 data. * @param[in] x Scaled input value in radians. * @return cos(x). */ q31_t arm_cos_q31( q31_t x); /** * @brief Fast approximation to the trigonometric cosine function for Q15 data. * @param[in] x Scaled input value in radians. * @return cos(x). */ q15_t arm_cos_q15( q15_t x); /** * @ingroup groupFastMath */ /** * @defgroup SQRT Square Root * * Computes the square root of a number. * There are separate functions for Q15, Q31, and floating-point data types. * The square root function is computed using the Newton-Raphson algorithm. * This is an iterative algorithm of the form: * 
   *      x1 = x0 - f(x0)/f'(x0)
   *
* where x1 is the current estimate, * x0 is the previous estimate and * f'(x0) is the derivative of f() evaluated at x0. * For the square root function, the algorithm reduces to: * 
   *     x0 = in/2                         [initial guess]
   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
   *
*/ /** * @addtogroup SQRT * @{ */ /** * @brief Floating-point square root function. * @param[in] in input value. * @param[out] *pOut square root of input value. * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if * in is negative value and returns zero output for negative values. */ static __INLINE arm_status arm_sqrt_f32( float32_t in, float32_t *pOut) { if(in > 0) { // #if __FPU_USED #if (__FPU_USED == 1) && defined ( __CC_ARM ) *pOut = __sqrtf(in); #else *pOut = sqrtf(in); #endif return (ARM_MATH_SUCCESS); } else { *pOut = 0.0f; return (ARM_MATH_ARGUMENT_ERROR); } } /** * @brief Q31 square root function. * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. * @param[out] *pOut square root of input value. * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if * in is negative value and returns zero output for negative values. */ arm_status arm_sqrt_q31( q31_t in, q31_t *pOut); /** * @brief Q15 square root function. * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. * @param[out] *pOut square root of input value. * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if * in is negative value and returns zero output for negative values. */ arm_status arm_sqrt_q15( q15_t in, q15_t *pOut); /** * @} end of SQRT group */ /** * @brief floating-point Circular write function. */ static __INLINE void arm_circularWrite_f32( int32_t * circBuffer, int32_t L, uint16_t * writeOffset, int32_t bufferInc, const int32_t * src, int32_t srcInc, uint32_t blockSize) { uint32_t i = 0u; int32_t wOffset; /* Copy the value of Index pointer that points * to the current location where the input samples to be copied */ wOffset = *writeOffset; /* Loop over the blockSize */ i = blockSize; while(i > 0u) { /* copy the input sample to the circular buffer */ circBuffer[wOffset] = *src; /* Update the input pointer */ src += srcInc; /* Circularly update wOffset. Watch out for positive and negative value */ wOffset += bufferInc; if(wOffset >= L) wOffset -= L; /* Decrement the loop counter */ i--; } /* Update the index pointer */ *writeOffset = wOffset; } /** * @brief floating-point Circular Read function. */ static __INLINE void arm_circularRead_f32( int32_t * circBuffer, int32_t L, int32_t * readOffset, int32_t bufferInc, int32_t * dst, int32_t * dst_base, int32_t dst_length, int32_t dstInc, uint32_t blockSize) { uint32_t i = 0u; int32_t rOffset, dst_end; /* Copy the value of Index pointer that points * to the current location from where the input samples to be read */ rOffset = *readOffset; dst_end = (int32_t) (dst_base + dst_length); /* Loop over the blockSize */ i = blockSize; while(i > 0u) { /* copy the sample from the circular buffer to the destination buffer */ *dst = circBuffer[rOffset]; /* Update the input pointer */ dst += dstInc; if(dst == (int32_t *) dst_end) { dst = dst_base; } /* Circularly update rOffset. Watch out for positive and negative value */ rOffset += bufferInc; if(rOffset >= L) { rOffset -= L; } /* Decrement the loop counter */ i--; } /* Update the index pointer */ *readOffset = rOffset; } /** * @brief Q15 Circular write function. */ static __INLINE void arm_circularWrite_q15( q15_t * circBuffer, int32_t L, uint16_t * writeOffset, int32_t bufferInc, const q15_t * src, int32_t srcInc, uint32_t blockSize) { uint32_t i = 0u; int32_t wOffset; /* Copy the value of Index pointer that points * to the current location where the input samples to be copied */ wOffset = *writeOffset; /* Loop over the blockSize */ i = blockSize; while(i > 0u) { /* copy the input sample to the circular buffer */ circBuffer[wOffset] = *src; /* Update the input pointer */ src += srcInc; /* Circularly update wOffset. Watch out for positive and negative value */ wOffset += bufferInc; if(wOffset >= L) wOffset -= L; /* Decrement the loop counter */ i--; } /* Update the index pointer */ *writeOffset = wOffset; } /** * @brief Q15 Circular Read function. */ static __INLINE void arm_circularRead_q15( q15_t * circBuffer, int32_t L, int32_t * readOffset, int32_t bufferInc, q15_t * dst, q15_t * dst_base, int32_t dst_length, int32_t dstInc, uint32_t blockSize) { uint32_t i = 0; int32_t rOffset, dst_end; /* Copy the value of Index pointer that points * to the current location from where the input samples to be read */ rOffset = *readOffset; dst_end = (int32_t) (dst_base + dst_length); /* Loop over the blockSize */ i = blockSize; while(i > 0u) { /* copy the sample from the circular buffer to the destination buffer */ *dst = circBuffer[rOffset]; /* Update the input pointer */ dst += dstInc; if(dst == (q15_t *) dst_end) { dst = dst_base; } /* Circularly update wOffset. Watch out for positive and negative value */ rOffset += bufferInc; if(rOffset >= L) { rOffset -= L; } /* Decrement the loop counter */ i--; } /* Update the index pointer */ *readOffset = rOffset; } /** * @brief Q7 Circular write function. */ static __INLINE void arm_circularWrite_q7( q7_t * circBuffer, int32_t L, uint16_t * writeOffset, int32_t bufferInc, const q7_t * src, int32_t srcInc, uint32_t blockSize) { uint32_t i = 0u; int32_t wOffset; /* Copy the value of Index pointer that points * to the current location where the input samples to be copied */ wOffset = *writeOffset; /* Loop over the blockSize */ i = blockSize; while(i > 0u) { /* copy the input sample to the circular buffer */ circBuffer[wOffset] = *src; /* Update the input pointer */ src += srcInc; /* Circularly update wOffset. Watch out for positive and negative value */ wOffset += bufferInc; if(wOffset >= L) wOffset -= L; /* Decrement the loop counter */ i--; } /* Update the index pointer */ *writeOffset = wOffset; } /** * @brief Q7 Circular Read function. */ static __INLINE void arm_circularRead_q7( q7_t * circBuffer, int32_t L, int32_t * readOffset, int32_t bufferInc, q7_t * dst, q7_t * dst_base, int32_t dst_length, int32_t dstInc, uint32_t blockSize) { uint32_t i = 0; int32_t rOffset, dst_end; /* Copy the value of Index pointer that points * to the current location from where the input samples to be read */ rOffset = *readOffset; dst_end = (int32_t) (dst_base + dst_length); /* Loop over the blockSize */ i = blockSize; while(i > 0u) { /* copy the sample from the circular buffer to the destination buffer */ *dst = circBuffer[rOffset]; /* Update the input pointer */ dst += dstInc; if(dst == (q7_t *) dst_end) { dst = dst_base; } /* Circularly update rOffset. Watch out for positive and negative value */ rOffset += bufferInc; if(rOffset >= L) { rOffset -= L; } /* Decrement the loop counter */ i--; } /* Update the index pointer */ *readOffset = rOffset; } /** * @brief Sum of the squares of the elements of a Q31 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_power_q31( q31_t * pSrc, uint32_t blockSize, q63_t * pResult); /** * @brief Sum of the squares of the elements of a floating-point vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_power_f32( float32_t * pSrc, uint32_t blockSize, float32_t * pResult); /** * @brief Sum of the squares of the elements of a Q15 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_power_q15( q15_t * pSrc, uint32_t blockSize, q63_t * pResult); /** * @brief Sum of the squares of the elements of a Q7 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_power_q7( q7_t * pSrc, uint32_t blockSize, q31_t * pResult); /** * @brief Mean value of a Q7 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_mean_q7( q7_t * pSrc, uint32_t blockSize, q7_t * pResult); /** * @brief Mean value of a Q15 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_mean_q15( q15_t * pSrc, uint32_t blockSize, q15_t * pResult); /** * @brief Mean value of a Q31 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_mean_q31( q31_t * pSrc, uint32_t blockSize, q31_t * pResult); /** * @brief Mean value of a floating-point vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_mean_f32( float32_t * pSrc, uint32_t blockSize, float32_t * pResult); /** * @brief Variance of the elements of a floating-point vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_var_f32( float32_t * pSrc, uint32_t blockSize, float32_t * pResult); /** * @brief Variance of the elements of a Q31 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_var_q31( q31_t * pSrc, uint32_t blockSize, q63_t * pResult); /** * @brief Variance of the elements of a Q15 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_var_q15( q15_t * pSrc, uint32_t blockSize, q31_t * pResult); /** * @brief Root Mean Square of the elements of a floating-point vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_rms_f32( float32_t * pSrc, uint32_t blockSize, float32_t * pResult); /** * @brief Root Mean Square of the elements of a Q31 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_rms_q31( q31_t * pSrc, uint32_t blockSize, q31_t * pResult); /** * @brief Root Mean Square of the elements of a Q15 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_rms_q15( q15_t * pSrc, uint32_t blockSize, q15_t * pResult); /** * @brief Standard deviation of the elements of a floating-point vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_std_f32( float32_t * pSrc, uint32_t blockSize, float32_t * pResult); /** * @brief Standard deviation of the elements of a Q31 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_std_q31( q31_t * pSrc, uint32_t blockSize, q31_t * pResult); /** * @brief Standard deviation of the elements of a Q15 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_std_q15( q15_t * pSrc, uint32_t blockSize, q15_t * pResult); /** * @brief Floating-point complex magnitude * @param[in] *pSrc points to the complex input vector * @param[out] *pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector * @return none. */ void arm_cmplx_mag_f32( float32_t * pSrc, float32_t * pDst, uint32_t numSamples); /** * @brief Q31 complex magnitude * @param[in] *pSrc points to the complex input vector * @param[out] *pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector * @return none. */ void arm_cmplx_mag_q31( q31_t * pSrc, q31_t * pDst, uint32_t numSamples); /** * @brief Q15 complex magnitude * @param[in] *pSrc points to the complex input vector * @param[out] *pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector * @return none. */ void arm_cmplx_mag_q15( q15_t * pSrc, q15_t * pDst, uint32_t numSamples); /** * @brief Q15 complex dot product * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[in] numSamples number of complex samples in each vector * @param[out] *realResult real part of the result returned here * @param[out] *imagResult imaginary part of the result returned here * @return none. */ void arm_cmplx_dot_prod_q15( q15_t * pSrcA, q15_t * pSrcB, uint32_t numSamples, q31_t * realResult, q31_t * imagResult); /** * @brief Q31 complex dot product * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[in] numSamples number of complex samples in each vector * @param[out] *realResult real part of the result returned here * @param[out] *imagResult imaginary part of the result returned here * @return none. */ void arm_cmplx_dot_prod_q31( q31_t * pSrcA, q31_t * pSrcB, uint32_t numSamples, q63_t * realResult, q63_t * imagResult); /** * @brief Floating-point complex dot product * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[in] numSamples number of complex samples in each vector * @param[out] *realResult real part of the result returned here * @param[out] *imagResult imaginary part of the result returned here * @return none. */ void arm_cmplx_dot_prod_f32( float32_t * pSrcA, float32_t * pSrcB, uint32_t numSamples, float32_t * realResult, float32_t * imagResult); /** * @brief Q15 complex-by-real multiplication * @param[in] *pSrcCmplx points to the complex input vector * @param[in] *pSrcReal points to the real input vector * @param[out] *pCmplxDst points to the complex output vector * @param[in] numSamples number of samples in each vector * @return none. */ void arm_cmplx_mult_real_q15( q15_t * pSrcCmplx, q15_t * pSrcReal, q15_t * pCmplxDst, uint32_t numSamples); /** * @brief Q31 complex-by-real multiplication * @param[in] *pSrcCmplx points to the complex input vector * @param[in] *pSrcReal points to the real input vector * @param[out] *pCmplxDst points to the complex output vector * @param[in] numSamples number of samples in each vector * @return none. */ void arm_cmplx_mult_real_q31( q31_t * pSrcCmplx, q31_t * pSrcReal, q31_t * pCmplxDst, uint32_t numSamples); /** * @brief Floating-point complex-by-real multiplication * @param[in] *pSrcCmplx points to the complex input vector * @param[in] *pSrcReal points to the real input vector * @param[out] *pCmplxDst points to the complex output vector * @param[in] numSamples number of samples in each vector * @return none. */ void arm_cmplx_mult_real_f32( float32_t * pSrcCmplx, float32_t * pSrcReal, float32_t * pCmplxDst, uint32_t numSamples); /** * @brief Minimum value of a Q7 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *result is output pointer * @param[in] index is the array index of the minimum value in the input buffer. * @return none. */ void arm_min_q7( q7_t * pSrc, uint32_t blockSize, q7_t * result, uint32_t * index); /** * @brief Minimum value of a Q15 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output pointer * @param[in] *pIndex is the array index of the minimum value in the input buffer. * @return none. */ void arm_min_q15( q15_t * pSrc, uint32_t blockSize, q15_t * pResult, uint32_t * pIndex); /** * @brief Minimum value of a Q31 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output pointer * @param[out] *pIndex is the array index of the minimum value in the input buffer. * @return none. */ void arm_min_q31( q31_t * pSrc, uint32_t blockSize, q31_t * pResult, uint32_t * pIndex); /** * @brief Minimum value of a floating-point vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output pointer * @param[out] *pIndex is the array index of the minimum value in the input buffer. * @return none. */ void arm_min_f32( float32_t * pSrc, uint32_t blockSize, float32_t * pResult, uint32_t * pIndex); /** * @brief Maximum value of a Q7 vector. * @param[in] *pSrc points to the input buffer * @param[in] blockSize length of the input vector * @param[out] *pResult maximum value returned here * @param[out] *pIndex index of maximum value returned here * @return none. */ void arm_max_q7( q7_t * pSrc, uint32_t blockSize, q7_t * pResult, uint32_t * pIndex); /** * @brief Maximum value of a Q15 vector. * @param[in] *pSrc points to the input buffer * @param[in] blockSize length of the input vector * @param[out] *pResult maximum value returned here * @param[out] *pIndex index of maximum value returned here * @return none. */ void arm_max_q15( q15_t * pSrc, uint32_t blockSize, q15_t * pResult, uint32_t * pIndex); /** * @brief Maximum value of a Q31 vector. * @param[in] *pSrc points to the input buffer * @param[in] blockSize length of the input vector * @param[out] *pResult maximum value returned here * @param[out] *pIndex index of maximum value returned here * @return none. */ void arm_max_q31( q31_t * pSrc, uint32_t blockSize, q31_t * pResult, uint32_t * pIndex); /** * @brief Maximum value of a floating-point vector. * @param[in] *pSrc points to the input buffer * @param[in] blockSize length of the input vector * @param[out] *pResult maximum value returned here * @param[out] *pIndex index of maximum value returned here * @return none. */ void arm_max_f32( float32_t * pSrc, uint32_t blockSize, float32_t * pResult, uint32_t * pIndex); /** * @brief Q15 complex-by-complex multiplication * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[out] *pDst points to the output vector * @param[in] numSamples number of complex samples in each vector * @return none. */ void arm_cmplx_mult_cmplx_q15( q15_t * pSrcA, q15_t * pSrcB, q15_t * pDst, uint32_t numSamples); /** * @brief Q31 complex-by-complex multiplication * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[out] *pDst points to the output vector * @param[in] numSamples number of complex samples in each vector * @return none. */ void arm_cmplx_mult_cmplx_q31( q31_t * pSrcA, q31_t * pSrcB, q31_t * pDst, uint32_t numSamples); /** * @brief Floating-point complex-by-complex multiplication * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[out] *pDst points to the output vector * @param[in] numSamples number of complex samples in each vector * @return none. */ void arm_cmplx_mult_cmplx_f32( float32_t * pSrcA, float32_t * pSrcB, float32_t * pDst, uint32_t numSamples); /** * @brief Converts the elements of the floating-point vector to Q31 vector. * @param[in] *pSrc points to the floating-point input vector * @param[out] *pDst points to the Q31 output vector * @param[in] blockSize length of the input vector * @return none. */ void arm_float_to_q31( float32_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Converts the elements of the floating-point vector to Q15 vector. * @param[in] *pSrc points to the floating-point input vector * @param[out] *pDst points to the Q15 output vector * @param[in] blockSize length of the input vector * @return none */ void arm_float_to_q15( float32_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Converts the elements of the floating-point vector to Q7 vector. * @param[in] *pSrc points to the floating-point input vector * @param[out] *pDst points to the Q7 output vector * @param[in] blockSize length of the input vector * @return none */ void arm_float_to_q7( float32_t * pSrc, q7_t * pDst, uint32_t blockSize); /** * @brief Converts the elements of the Q31 vector to Q15 vector. * @param[in] *pSrc is input pointer * @param[out] *pDst is output pointer * @param[in] blockSize is the number of samples to process * @return none. */ void arm_q31_to_q15( q31_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Converts the elements of the Q31 vector to Q7 vector. * @param[in] *pSrc is input pointer * @param[out] *pDst is output pointer * @param[in] blockSize is the number of samples to process * @return none. */ void arm_q31_to_q7( q31_t * pSrc, q7_t * pDst, uint32_t blockSize); /** * @brief Converts the elements of the Q15 vector to floating-point vector. * @param[in] *pSrc is input pointer * @param[out] *pDst is output pointer * @param[in] blockSize is the number of samples to process * @return none. */ void arm_q15_to_float( q15_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Converts the elements of the Q15 vector to Q31 vector. * @param[in] *pSrc is input pointer * @param[out] *pDst is output pointer * @param[in] blockSize is the number of samples to process * @return none. */ void arm_q15_to_q31( q15_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Converts the elements of the Q15 vector to Q7 vector. * @param[in] *pSrc is input pointer * @param[out] *pDst is output pointer * @param[in] blockSize is the number of samples to process * @return none. */ void arm_q15_to_q7( q15_t * pSrc, q7_t * pDst, uint32_t blockSize); /** * @ingroup groupInterpolation */ /** * @defgroup BilinearInterpolate Bilinear Interpolation * * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. * The underlying function f(x, y) is sampled on a regular grid and the interpolation process * determines values between the grid points. * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. * Bilinear interpolation is often used in image processing to rescale images. * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. * * Algorithm * \par * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. * For floating-point, the instance structure is defined as: * 
   *   typedef struct
   *   {
   *     uint16_t numRows;
   *     uint16_t numCols;
   *     float32_t *pData;
   * } arm_bilinear_interp_instance_f32;
   *
* * \par * where numRows specifies the number of rows in the table; * numCols specifies the number of columns in the table; * and pData points to an array of size numRows*numCols values. * The data table pTable is organized in row order and the supplied data values fall on integer indexes. * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. * * \par * Let (x, y) specify the desired interpolation point. Then define: * 
   *     XF = floor(x)
   *     YF = floor(y)
   *
* \par * The interpolated output point is computed as: * 
   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
   *
* Note that the coordinates (x, y) contain integer and fractional components. * The integer components specify which portion of the table to use while the * fractional components control the interpolation processor. * * \par * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. */ /** * @addtogroup BilinearInterpolate * @{ */ /** * * @brief Floating-point bilinear interpolation. * @param[in,out] *S points to an instance of the interpolation structure. * @param[in] X interpolation coordinate. * @param[in] Y interpolation coordinate. * @return out interpolated value. */ static __INLINE float32_t arm_bilinear_interp_f32( const arm_bilinear_interp_instance_f32 * S, float32_t X, float32_t Y) { float32_t out; float32_t f00, f01, f10, f11; float32_t *pData = S->pData; int32_t xIndex, yIndex, index; float32_t xdiff, ydiff; float32_t b1, b2, b3, b4; xIndex = (int32_t) X; yIndex = (int32_t) Y; /* Care taken for table outside boundary */ /* Returns zero output when values are outside table boundary */ if(xIndex < 0 || xIndex > (S->numRows-1) || yIndex < 0 || yIndex > ( S->numCols-1)) { return(0); } /* Calculation of index for two nearest points in X-direction */ index = (xIndex - 1) + (yIndex-1) * S->numCols ; /* Read two nearest points in X-direction */ f00 = pData[index]; f01 = pData[index + 1]; /* Calculation of index for two nearest points in Y-direction */ index = (xIndex-1) + (yIndex) * S->numCols; /* Read two nearest points in Y-direction */ f10 = pData[index]; f11 = pData[index + 1]; /* Calculation of intermediate values */ b1 = f00; b2 = f01 - f00; b3 = f10 - f00; b4 = f00 - f01 - f10 + f11; /* Calculation of fractional part in X */ xdiff = X - xIndex; /* Calculation of fractional part in Y */ ydiff = Y - yIndex; /* Calculation of bi-linear interpolated output */ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; /* return to application */ return (out); } /** * * @brief Q31 bilinear interpolation. * @param[in,out] *S points to an instance of the interpolation structure. * @param[in] X interpolation coordinate in 12.20 format. * @param[in] Y interpolation coordinate in 12.20 format. * @return out interpolated value. */ static __INLINE q31_t arm_bilinear_interp_q31( arm_bilinear_interp_instance_q31 * S, q31_t X, q31_t Y) { q31_t out; /* Temporary output */ q31_t acc = 0; /* output */ q31_t xfract, yfract; /* X, Y fractional parts */ q31_t x1, x2, y1, y2; /* Nearest output values */ int32_t rI, cI; /* Row and column indices */ q31_t *pYData = S->pData; /* pointer to output table values */ uint32_t nCols = S->numCols; /* num of rows */ /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ rI = ((X & 0xFFF00000) >> 20u); /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ cI = ((Y & 0xFFF00000) >> 20u); /* Care taken for table outside boundary */ /* Returns zero output when values are outside table boundary */ if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) { return(0); } /* 20 bits for the fractional part */ /* shift left xfract by 11 to keep 1.31 format */ xfract = (X & 0x000FFFFF) << 11u; /* Read two nearest output values from the index */ x1 = pYData[(rI) + nCols * (cI)]; x2 = pYData[(rI) + nCols * (cI) + 1u]; /* 20 bits for the fractional part */ /* shift left yfract by 11 to keep 1.31 format */ yfract = (Y & 0x000FFFFF) << 11u; /* Read two nearest output values from the index */ y1 = pYData[(rI) + nCols * (cI + 1)]; y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); /* Convert acc to 1.31(q31) format */ return (acc << 2u); } /** * @brief Q15 bilinear interpolation. * @param[in,out] *S points to an instance of the interpolation structure. * @param[in] X interpolation coordinate in 12.20 format. * @param[in] Y interpolation coordinate in 12.20 format. * @return out interpolated value. */ static __INLINE q15_t arm_bilinear_interp_q15( arm_bilinear_interp_instance_q15 * S, q31_t X, q31_t Y) { q63_t acc = 0; /* output */ q31_t out; /* Temporary output */ q15_t x1, x2, y1, y2; /* Nearest output values */ q31_t xfract, yfract; /* X, Y fractional parts */ int32_t rI, cI; /* Row and column indices */ q15_t *pYData = S->pData; /* pointer to output table values */ uint32_t nCols = S->numCols; /* num of rows */ /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ rI = ((X & 0xFFF00000) >> 20); /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ cI = ((Y & 0xFFF00000) >> 20); /* Care taken for table outside boundary */ /* Returns zero output when values are outside table boundary */ if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) { return(0); } /* 20 bits for the fractional part */ /* xfract should be in 12.20 format */ xfract = (X & 0x000FFFFF); /* Read two nearest output values from the index */ x1 = pYData[(rI) + nCols * (cI)]; x2 = pYData[(rI) + nCols * (cI) + 1u]; /* 20 bits for the fractional part */ /* yfract should be in 12.20 format */ yfract = (Y & 0x000FFFFF); /* Read two nearest output values from the index */ y1 = pYData[(rI) + nCols * (cI + 1)]; y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); acc = ((q63_t) out * (0xFFFFF - yfract)); /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); acc += ((q63_t) out * (xfract)); /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); acc += ((q63_t) out * (yfract)); /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); acc += ((q63_t) out * (yfract)); /* acc is in 13.51 format and down shift acc by 36 times */ /* Convert out to 1.15 format */ return (acc >> 36); } /** * @brief Q7 bilinear interpolation. * @param[in,out] *S points to an instance of the interpolation structure. * @param[in] X interpolation coordinate in 12.20 format. * @param[in] Y interpolation coordinate in 12.20 format. * @return out interpolated value. */ static __INLINE q7_t arm_bilinear_interp_q7( arm_bilinear_interp_instance_q7 * S, q31_t X, q31_t Y) { q63_t acc = 0; /* output */ q31_t out; /* Temporary output */ q31_t xfract, yfract; /* X, Y fractional parts */ q7_t x1, x2, y1, y2; /* Nearest output values */ int32_t rI, cI; /* Row and column indices */ q7_t *pYData = S->pData; /* pointer to output table values */ uint32_t nCols = S->numCols; /* num of rows */ /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ rI = ((X & 0xFFF00000) >> 20); /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ cI = ((Y & 0xFFF00000) >> 20); /* Care taken for table outside boundary */ /* Returns zero output when values are outside table boundary */ if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) { return(0); } /* 20 bits for the fractional part */ /* xfract should be in 12.20 format */ xfract = (X & 0x000FFFFF); /* Read two nearest output values from the index */ x1 = pYData[(rI) + nCols * (cI)]; x2 = pYData[(rI) + nCols * (cI) + 1u]; /* 20 bits for the fractional part */ /* yfract should be in 12.20 format */ yfract = (Y & 0x000FFFFF); /* Read two nearest output values from the index */ y1 = pYData[(rI) + nCols * (cI + 1)]; y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ out = ((x1 * (0xFFFFF - xfract))); acc = (((q63_t) out * (0xFFFFF - yfract))); /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ out = ((x2 * (0xFFFFF - yfract))); acc += (((q63_t) out * (xfract))); /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ out = ((y1 * (0xFFFFF - xfract))); acc += (((q63_t) out * (yfract))); /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ out = ((y2 * (yfract))); acc += (((q63_t) out * (xfract))); /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ return (acc >> 40); } /** * @} end of BilinearInterpolate group */ #ifdef __cplusplus } #endif #endif /* _ARM_MATH_H */ /** * * End of file. */ ================================================ FILE: figure-simulator-discovery/Libraries/CMSIS/Include/core_cm4.h ================================================ /**************************************************************************//** * @file core_cm4.h * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File * @version V2.10 * @date 19. July 2011 * * @note * Copyright (C) 2009-2011 ARM Limited. All rights reserved. * * @par * ARM Limited (ARM) is supplying this software for use with Cortex-M * processor based microcontrollers. This file can be freely distributed * within development tools that are supporting such ARM based processors. * * @par * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * ******************************************************************************/ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #endif #ifdef __cplusplus extern "C" { #endif #ifndef __CORE_CM4_H_GENERIC #define __CORE_CM4_H_GENERIC /** \mainpage CMSIS Cortex-M4 This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. It consists of: - Cortex-M Core Register Definitions - Cortex-M functions - Cortex-M instructions - Cortex-M SIMD instructions The CMSIS Cortex-M4 Core Peripheral Access Layer contains C and assembly functions that ease access to the Cortex-M Core */ /** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions CMSIS violates following MISRA-C2004 Rules: - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \defgroup CMSIS_core_definitions CMSIS Core Definitions This file defines all structures and symbols for CMSIS core: - CMSIS version number - Cortex-M core - Cortex-M core Revision Number @{ */ /* CMSIS CM4 definitions */ #define __CM4_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ #define __CM4_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ #define __CORTEX_M (0x04) /*!< Cortex core */ #if defined ( __CC_ARM ) #define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #elif defined ( __ICCARM__ ) #define __ASM __asm /*!< asm keyword for IAR Compiler */ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ #elif defined ( __GNUC__ ) #define __ASM __asm /*!< asm keyword for GNU Compiler */ #define __INLINE inline /*!< inline keyword for GNU Compiler */ #elif defined ( __TASKING__ ) #define __ASM __asm /*!< asm keyword for TASKING Compiler */ #define __INLINE inline /*!< inline keyword for TASKING Compiler */ #endif /*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #if (__FPU_PRESENT == 1) #define __FPU_USED 1 #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0 #endif #else #define __FPU_USED 0 #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if (__FPU_PRESENT == 1) #define __FPU_USED 1 #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0 #endif #else #define __FPU_USED 0 #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if (__FPU_PRESENT == 1) #define __FPU_USED 1 #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0 #endif #else #define __FPU_USED 0 #endif #elif defined ( __TASKING__ ) /* add preprocessor checks to define __FPU_USED */ #define __FPU_USED 0 #endif #include /*!< standard types definitions */ #include /*!< Core Instruction Access */ #include /*!< Core Function Access */ #include /*!< Compiler specific SIMD Intrinsics */ #endif /* __CORE_CM4_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM4_H_DEPENDANT #define __CORE_CM4_H_DEPENDANT /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM4_REV #define __CM4_REV 0x0000 #warning "__CM4_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0 #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0 #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 4 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ #ifdef __cplusplus #define __I volatile /*!< defines 'read only' permissions */ #else #define __I volatile const /*!< defines 'read only' permissions */ #endif #define __O volatile /*!< defines 'write only' permissions */ #define __IO volatile /*!< defines 'read / write' permissions */ /*@} end of group CMSIS_core_definitions */ /******************************************************************************* * Register Abstraction ******************************************************************************/ /** \defgroup CMSIS_core_register CMSIS Core Register Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core FPU Register */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE CMSIS Core Type definitions for the Cortex-M Core Registers @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { #if (__CORTEX_M != 0x04) uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ #else uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ #endif uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ #if (__CORTEX_M != 0x04) uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ #else uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ #endif uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC CMSIS NVIC Type definitions for the Cortex-M NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24]; __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[24]; __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24]; __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24]; __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56]; __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644]; __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB CMSIS SCB Type definitions for the Cortex-M System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[5]; __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Registers Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* SCB Hard Fault Status Registers Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB Type definitions for the Cortex-M System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1]; __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ #define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick CMSIS SysTick Type definitions for the Cortex-M System Timer Registers @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM CMSIS ITM Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __O union { __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864]; __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15]; __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15]; __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */ #define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */ #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ /*@}*/ /* end of group CMSIS_ITM */ #if (__MPU_PRESENT == 1) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU CMSIS MPU Type definitions for the Cortex-M Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; /* MPU Type Register */ #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register */ #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register */ #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register */ #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register */ #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif #if (__FPU_PRESENT == 1) /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU CMSIS FPU Type definitions for the Cortex-M Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1]; __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ } FPU_Type; /* Floating-Point Context Control Register */ #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register */ #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register */ #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 */ #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 */ #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ /*@} end of group CMSIS_FPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug CMSIS Core Debug Type definitions for the Cortex-M Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register */ #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register */ #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register */ #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register @{ */ /* Memory mapping of Cortex-M4 Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if (__MPU_PRESENT == 1) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if (__FPU_PRESENT == 1) #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions @{ */ /** \brief Set Priority Grouping This function sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field */ static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping This function gets the priority grouping from NVIC Interrupt Controller. Priority grouping is SCB->AIRCR [10:8] PRIGROUP field. \return Priority grouping field */ static __INLINE uint32_t NVIC_GetPriorityGrouping(void) { return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ } /** \brief Enable External Interrupt This function enables a device specific interrupt in the NVIC interrupt controller. The interrupt number cannot be a negative value. \param [in] IRQn Number of the external interrupt to enable */ static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ } /** \brief Disable External Interrupt This function disables a device specific interrupt in the NVIC interrupt controller. The interrupt number cannot be a negative value. \param [in] IRQn Number of the external interrupt to disable */ static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ } /** \brief Get Pending Interrupt This function reads the pending register in the NVIC and returns the pending bit for the specified interrupt. \param [in] IRQn Number of the interrupt for get pending \return 0 Interrupt status is not pending \return 1 Interrupt status is pending */ static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ } /** \brief Set Pending Interrupt This function sets the pending bit for the specified interrupt. The interrupt number cannot be a negative value. \param [in] IRQn Number of the interrupt for set pending */ static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ } /** \brief Clear Pending Interrupt This function clears the pending bit for the specified interrupt. The interrupt number cannot be a negative value. \param [in] IRQn Number of the interrupt for clear pending */ static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ } /** \brief Get Active Interrupt This function reads the active register in NVIC and returns the active bit. \param [in] IRQn Number of the interrupt for get active \return 0 Interrupt status is not active \return 1 Interrupt status is active */ static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ } /** \brief Set Interrupt Priority This function sets the priority for the specified interrupt. The interrupt number can be positive to specify an external (device specific) interrupt, or negative to specify an internal (core) interrupt. Note: The priority cannot be set for every core interrupt. \param [in] IRQn Number of the interrupt for set priority \param [in] priority Priority to set */ static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if(IRQn < 0) { SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ else { NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ } /** \brief Get Interrupt Priority This function reads the priority for the specified interrupt. The interrupt number can be positive to specify an external (device specific) interrupt, or negative to specify an internal (core) interrupt. The returned priority value is automatically aligned to the implemented priority bits of the microcontroller. \param [in] IRQn Number of the interrupt for get priority \return Interrupt Priority */ static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) { if(IRQn < 0) { return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ else { return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ } /** \brief Encode Priority This function encodes the priority for an interrupt with the given priority group, preemptive priority value and sub priority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. The returned priority value can be used for NVIC_SetPriority(...) function \param [in] PriorityGroup Used priority group \param [in] PreemptPriority Preemptive priority value (starting from 0) \param [in] SubPriority Sub priority value (starting from 0) \return Encoded priority for the interrupt */ static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; return ( ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | ((SubPriority & ((1 << (SubPriorityBits )) - 1))) ); } /** \brief Decode Priority This function decodes an interrupt priority value with the given priority group to preemptive priority value and sub priority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. The priority value can be retrieved with NVIC_GetPriority(...) function \param [in] Priority Priority value \param [in] PriorityGroup Used priority group \param [out] pPreemptPriority Preemptive priority value (starting from 0) \param [out] pSubPriority Sub priority value (starting from 0) */ static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); } /** \brief System Reset This function initiate a system reset request to reset the MCU. */ static __INLINE void NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ while(1); /* wait until reset */ } /*@} end of CMSIS_Core_NVICFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions @{ */ #if (__Vendor_SysTickConfig == 0) /** \brief System Tick Configuration This function initialises the system tick timer and its interrupt and start the system tick timer. Counter is in free running mode to generate periodical interrupts. \param [in] ticks Number of ticks between two interrupts \return 0 Function succeeded \return 1 Function failed */ static __INLINE uint32_t SysTick_Config(uint32_t ticks) { if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ SysTick->VAL = 0; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions @{ */ extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */ #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ /** \brief ITM Send Character This function transmits a character via the ITM channel 0. It just returns when no debugger is connected that has booked the output. It is blocking when a debugger is connected, but the previous character send is not transmitted. \param [in] ch Character to transmit \return Character to transmit */ static __INLINE uint32_t ITM_SendChar (uint32_t ch) { if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0].u32 == 0); ITM->PORT[0].u8 = (uint8_t) ch; } return (ch); } /** \brief ITM Receive Character This function inputs a character via external variable ITM_RxBuffer. It just returns when no debugger is connected that has booked the output. It is blocking when a debugger is connected, but the previous character send is not transmitted. \return Received character \return -1 No character received */ static __INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character This function checks external variable ITM_RxBuffer whether a character is available or not. It returns '1' if a character is available and '0' if no character is available. \return 0 No character available \return 1 Character available */ static __INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #endif /* __CORE_CM4_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ #ifdef __cplusplus } #endif ================================================ FILE: figure-simulator-discovery/Libraries/CMSIS/Include/core_cm4_simd.h ================================================ /**************************************************************************//** * @file core_cm4_simd.h * @brief CMSIS Cortex-M4 SIMD Header File * @version V2.10 * @date 19. July 2011 * * @note * Copyright (C) 2010-2011 ARM Limited. All rights reserved. * * @par * ARM Limited (ARM) is supplying this software for use with Cortex-M * processor based microcontrollers. This file can be freely distributed * within development tools that are supporting such ARM based processors. * * @par * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * ******************************************************************************/ #ifdef __cplusplus extern "C" { #endif #ifndef __CORE_CM4_SIMD_H #define __CORE_CM4_SIMD_H /******************************************************************************* * Hardware Abstraction Layer ******************************************************************************/ /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ /* ARM armcc specific functions */ /*------ CM4 SOMD Intrinsics -----------------------------------------------------*/ #define __SADD8 __sadd8 #define __QADD8 __qadd8 #define __SHADD8 __shadd8 #define __UADD8 __uadd8 #define __UQADD8 __uqadd8 #define __UHADD8 __uhadd8 #define __SSUB8 __ssub8 #define __QSUB8 __qsub8 #define __SHSUB8 __shsub8 #define __USUB8 __usub8 #define __UQSUB8 __uqsub8 #define __UHSUB8 __uhsub8 #define __SADD16 __sadd16 #define __QADD16 __qadd16 #define __SHADD16 __shadd16 #define __UADD16 __uadd16 #define __UQADD16 __uqadd16 #define __UHADD16 __uhadd16 #define __SSUB16 __ssub16 #define __QSUB16 __qsub16 #define __SHSUB16 __shsub16 #define __USUB16 __usub16 #define __UQSUB16 __uqsub16 #define __UHSUB16 __uhsub16 #define __SASX __sasx #define __QASX __qasx #define __SHASX __shasx #define __UASX __uasx #define __UQASX __uqasx #define __UHASX __uhasx #define __SSAX __ssax #define __QSAX __qsax #define __SHSAX __shsax #define __USAX __usax #define __UQSAX __uqsax #define __UHSAX __uhsax #define __USAD8 __usad8 #define __USADA8 __usada8 #define __SSAT16 __ssat16 #define __USAT16 __usat16 #define __UXTB16 __uxtb16 #define __UXTAB16 __uxtab16 #define __SXTB16 __sxtb16 #define __SXTAB16 __sxtab16 #define __SMUAD __smuad #define __SMUADX __smuadx #define __SMLAD __smlad #define __SMLADX __smladx #define __SMLALD __smlald #define __SMLALDX __smlaldx #define __SMUSD __smusd #define __SMUSDX __smusdx #define __SMLSD __smlsd #define __SMLSDX __smlsdx #define __SMLSLD __smlsld #define __SMLSLDX __smlsldx #define __SEL __sel #define __QADD __qadd #define __QSUB __qsub #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ /* IAR iccarm specific functions */ #include /*------ CM4 SIMDDSP Intrinsics -----------------------------------------------------*/ /* intrinsic __SADD8 see intrinsics.h */ /* intrinsic __QADD8 see intrinsics.h */ /* intrinsic __SHADD8 see intrinsics.h */ /* intrinsic __UADD8 see intrinsics.h */ /* intrinsic __UQADD8 see intrinsics.h */ /* intrinsic __UHADD8 see intrinsics.h */ /* intrinsic __SSUB8 see intrinsics.h */ /* intrinsic __QSUB8 see intrinsics.h */ /* intrinsic __SHSUB8 see intrinsics.h */ /* intrinsic __USUB8 see intrinsics.h */ /* intrinsic __UQSUB8 see intrinsics.h */ /* intrinsic __UHSUB8 see intrinsics.h */ /* intrinsic __SADD16 see intrinsics.h */ /* intrinsic __QADD16 see intrinsics.h */ /* intrinsic __SHADD16 see intrinsics.h */ /* intrinsic __UADD16 see intrinsics.h */ /* intrinsic __UQADD16 see intrinsics.h */ /* intrinsic __UHADD16 see intrinsics.h */ /* intrinsic __SSUB16 see intrinsics.h */ /* intrinsic __QSUB16 see intrinsics.h */ /* intrinsic __SHSUB16 see intrinsics.h */ /* intrinsic __USUB16 see intrinsics.h */ /* intrinsic __UQSUB16 see intrinsics.h */ /* intrinsic __UHSUB16 see intrinsics.h */ /* intrinsic __SASX see intrinsics.h */ /* intrinsic __QASX see intrinsics.h */ /* intrinsic __SHASX see intrinsics.h */ /* intrinsic __UASX see intrinsics.h */ /* intrinsic __UQASX see intrinsics.h */ /* intrinsic __UHASX see intrinsics.h */ /* intrinsic __SSAX see intrinsics.h */ /* intrinsic __QSAX see intrinsics.h */ /* intrinsic __SHSAX see intrinsics.h */ /* intrinsic __USAX see intrinsics.h */ /* intrinsic __UQSAX see intrinsics.h */ /* intrinsic __UHSAX see intrinsics.h */ /* intrinsic __USAD8 see intrinsics.h */ /* intrinsic __USADA8 see intrinsics.h */ /* intrinsic __SSAT16 see intrinsics.h */ /* intrinsic __USAT16 see intrinsics.h */ /* intrinsic __UXTB16 see intrinsics.h */ /* intrinsic __SXTB16 see intrinsics.h */ /* intrinsic __UXTAB16 see intrinsics.h */ /* intrinsic __SXTAB16 see intrinsics.h */ /* intrinsic __SMUAD see intrinsics.h */ /* intrinsic __SMUADX see intrinsics.h */ /* intrinsic __SMLAD see intrinsics.h */ /* intrinsic __SMLADX see intrinsics.h */ /* intrinsic __SMLALD see intrinsics.h */ /* intrinsic __SMLALDX see intrinsics.h */ /* intrinsic __SMUSD see intrinsics.h */ /* intrinsic __SMUSDX see intrinsics.h */ /* intrinsic __SMLSD see intrinsics.h */ /* intrinsic __SMLSDX see intrinsics.h */ /* intrinsic __SMLSLD see intrinsics.h */ /* intrinsic __SMLSLDX see intrinsics.h */ /* intrinsic __SEL see intrinsics.h */ /* intrinsic __QADD see intrinsics.h */ /* intrinsic __QSUB see intrinsics.h */ /* intrinsic __PKHBT see intrinsics.h */ /* intrinsic __PKHTB see intrinsics.h */ /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ /* GNU gcc specific functions */ /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ __attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } #define __SSAT16(ARG1,ARG2) \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) #define __USAT16(ARG1,ARG2) \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) __attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTB16(uint32_t op1) { uint32_t result; __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTB16(uint32_t op1) { uint32_t result; __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } #define __SMLALD(ARG1,ARG2,ARG3) \ ({ \ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ }) #define __SMLALDX(ARG1,ARG2,ARG3) \ ({ \ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ }) __attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } #define __SMLSLD(ARG1,ARG2,ARG3) \ ({ \ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ }) #define __SMLSLDX(ARG1,ARG2,ARG3) \ ({ \ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ }) __attribute__( ( always_inline ) ) static __INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } #define __PKHBT(ARG1,ARG2,ARG3) \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ __RES; \ }) #define __PKHTB(ARG1,ARG2,ARG3) \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ if (ARG3 == 0) \ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ else \ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ __RES; \ }) /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ /* TASKING carm specific functions */ /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ /* not yet supported */ /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ #endif /*@} end of group CMSIS_SIMD_intrinsics */ #endif /* __CORE_CM4_SIMD_H */ #ifdef __cplusplus } #endif ================================================ FILE: figure-simulator-discovery/Libraries/CMSIS/Include/core_cmFunc.h ================================================ /**************************************************************************//** * @file core_cmFunc.h * @brief CMSIS Cortex-M Core Function Access Header File * @version V2.10 * @date 26. July 2011 * * @note * Copyright (C) 2009-2011 ARM Limited. All rights reserved. * * @par * ARM Limited (ARM) is supplying this software for use with Cortex-M * processor based microcontrollers. This file can be freely distributed * within development tools that are supporting such ARM based processors. * * @par * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * ******************************************************************************/ #ifndef __CORE_CMFUNC_H #define __CORE_CMFUNC_H /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ /* ARM armcc specific functions */ #if (__ARMCC_VERSION < 400677) #error "Please use ARM Compiler Toolchain V4.0.677 or later!" #endif /* intrinsic void __enable_irq(); */ /* intrinsic void __disable_irq(); */ /** \brief Get Control Register This function returns the content of the Control Register. \return Control Register value */ static __INLINE uint32_t __get_CONTROL(void) { register uint32_t __regControl __ASM("control"); return(__regControl); } /** \brief Set Control Register This function writes the given value to the Control Register. \param [in] control Control Register value to set */ static __INLINE void __set_CONTROL(uint32_t control) { register uint32_t __regControl __ASM("control"); __regControl = control; } /** \brief Get ISPR Register This function returns the content of the ISPR Register. \return ISPR Register value */ static __INLINE uint32_t __get_IPSR(void) { register uint32_t __regIPSR __ASM("ipsr"); return(__regIPSR); } /** \brief Get APSR Register This function returns the content of the APSR Register. \return APSR Register value */ static __INLINE uint32_t __get_APSR(void) { register uint32_t __regAPSR __ASM("apsr"); return(__regAPSR); } /** \brief Get xPSR Register This function returns the content of the xPSR Register. \return xPSR Register value */ static __INLINE uint32_t __get_xPSR(void) { register uint32_t __regXPSR __ASM("xpsr"); return(__regXPSR); } /** \brief Get Process Stack Pointer This function returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ static __INLINE uint32_t __get_PSP(void) { register uint32_t __regProcessStackPointer __ASM("psp"); return(__regProcessStackPointer); } /** \brief Set Process Stack Pointer This function assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ static __INLINE void __set_PSP(uint32_t topOfProcStack) { register uint32_t __regProcessStackPointer __ASM("psp"); __regProcessStackPointer = topOfProcStack; } /** \brief Get Main Stack Pointer This function returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ static __INLINE uint32_t __get_MSP(void) { register uint32_t __regMainStackPointer __ASM("msp"); return(__regMainStackPointer); } /** \brief Set Main Stack Pointer This function assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ static __INLINE void __set_MSP(uint32_t topOfMainStack) { register uint32_t __regMainStackPointer __ASM("msp"); __regMainStackPointer = topOfMainStack; } /** \brief Get Priority Mask This function returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ static __INLINE uint32_t __get_PRIMASK(void) { register uint32_t __regPriMask __ASM("primask"); return(__regPriMask); } /** \brief Set Priority Mask This function assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ static __INLINE void __set_PRIMASK(uint32_t priMask) { register uint32_t __regPriMask __ASM("primask"); __regPriMask = (priMask); } #if (__CORTEX_M >= 0x03) /** \brief Enable FIQ This function enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ #define __enable_fault_irq __enable_fiq /** \brief Disable FIQ This function disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ #define __disable_fault_irq __disable_fiq /** \brief Get Base Priority This function returns the current value of the Base Priority register. \return Base Priority register value */ static __INLINE uint32_t __get_BASEPRI(void) { register uint32_t __regBasePri __ASM("basepri"); return(__regBasePri); } /** \brief Set Base Priority This function assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ static __INLINE void __set_BASEPRI(uint32_t basePri) { register uint32_t __regBasePri __ASM("basepri"); __regBasePri = (basePri & 0xff); } /** \brief Get Fault Mask This function returns the current value of the Fault Mask register. \return Fault Mask register value */ static __INLINE uint32_t __get_FAULTMASK(void) { register uint32_t __regFaultMask __ASM("faultmask"); return(__regFaultMask); } /** \brief Set Fault Mask This function assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ static __INLINE void __set_FAULTMASK(uint32_t faultMask) { register uint32_t __regFaultMask __ASM("faultmask"); __regFaultMask = (faultMask & (uint32_t)1); } #endif /* (__CORTEX_M >= 0x03) */ #if (__CORTEX_M == 0x04) /** \brief Get FPSCR This function returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ static __INLINE uint32_t __get_FPSCR(void) { #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) register uint32_t __regfpscr __ASM("fpscr"); return(__regfpscr); #else return(0); #endif } /** \brief Set FPSCR This function assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ static __INLINE void __set_FPSCR(uint32_t fpscr) { #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) register uint32_t __regfpscr __ASM("fpscr"); __regfpscr = (fpscr); #endif } #endif /* (__CORTEX_M == 0x04) */ #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ /* IAR iccarm specific functions */ #include #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ /* GNU gcc specific functions */ /** \brief Enable IRQ Interrupts This function enables IRQ interrupts by clearing the I-bit in the CPSR. Can only be executed in Privileged modes. */ __attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void) { __ASM volatile ("cpsie i"); } /** \brief Disable IRQ Interrupts This function disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void) { __ASM volatile ("cpsid i"); } /** \brief Get Control Register This function returns the content of the Control Register. \return Control Register value */ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void) { uint32_t result; __ASM volatile ("MRS %0, control" : "=r" (result) ); return(result); } /** \brief Set Control Register This function writes the given value to the Control Register. \param [in] control Control Register value to set */ __attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control) { __ASM volatile ("MSR control, %0" : : "r" (control) ); } /** \brief Get ISPR Register This function returns the content of the ISPR Register. \return ISPR Register value */ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void) { uint32_t result; __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); return(result); } /** \brief Get APSR Register This function returns the content of the APSR Register. \return APSR Register value */ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void) { uint32_t result; __ASM volatile ("MRS %0, apsr" : "=r" (result) ); return(result); } /** \brief Get xPSR Register This function returns the content of the xPSR Register. \return xPSR Register value */ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void) { uint32_t result; __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); return(result); } /** \brief Get Process Stack Pointer This function returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void) { register uint32_t result; __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); return(result); } /** \brief Set Process Stack Pointer This function assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ __attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack) { __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); } /** \brief Get Main Stack Pointer This function returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void) { register uint32_t result; __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); return(result); } /** \brief Set Main Stack Pointer This function assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ __attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack) { __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); } /** \brief Get Priority Mask This function returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile ("MRS %0, primask" : "=r" (result) ); return(result); } /** \brief Set Priority Mask This function assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); } #if (__CORTEX_M >= 0x03) /** \brief Enable FIQ This function enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ __attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void) { __ASM volatile ("cpsie f"); } /** \brief Disable FIQ This function disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ __attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void) { __ASM volatile ("cpsid f"); } /** \brief Get Base Priority This function returns the current value of the Base Priority register. \return Base Priority register value */ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void) { uint32_t result; __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); return(result); } /** \brief Set Base Priority This function assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ __attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value) { __ASM volatile ("MSR basepri, %0" : : "r" (value) ); } /** \brief Get Fault Mask This function returns the current value of the Fault Mask register. \return Fault Mask register value */ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); return(result); } /** \brief Set Fault Mask This function assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ __attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask) { __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); } #endif /* (__CORTEX_M >= 0x03) */ #if (__CORTEX_M == 0x04) /** \brief Get FPSCR This function returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void) { #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) uint32_t result; __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); return(result); #else return(0); #endif } /** \brief Set FPSCR This function assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ __attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr) { #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); #endif } #endif /* (__CORTEX_M == 0x04) */ #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ /* TASKING carm specific functions */ /* * The CMSIS functions have been implemented as intrinsics in the compiler. * Please use "carm -?i" to get an up to date list of all instrinsics, * Including the CMSIS ones. */ #endif /*@} end of CMSIS_Core_RegAccFunctions */ #endif /* __CORE_CMFUNC_H */ ================================================ FILE: figure-simulator-discovery/Libraries/CMSIS/Include/core_cmInstr.h ================================================ /**************************************************************************//** * @file core_cmInstr.h * @brief CMSIS Cortex-M Core Instruction Access Header File * @version V2.10 * @date 19. July 2011 * * @note * Copyright (C) 2009-2011 ARM Limited. All rights reserved. * * @par * ARM Limited (ARM) is supplying this software for use with Cortex-M * processor based microcontrollers. This file can be freely distributed * within development tools that are supporting such ARM based processors. * * @par * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * ******************************************************************************/ #ifndef __CORE_CMINSTR_H #define __CORE_CMINSTR_H /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ */ #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ /* ARM armcc specific functions */ #if (__ARMCC_VERSION < 400677) #error "Please use ARM Compiler Toolchain V4.0.677 or later!" #endif /** \brief No Operation No Operation does nothing. This instruction can be used for code alignment purposes. */ #define __NOP __nop /** \brief Wait For Interrupt Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ #define __WFI __wfi /** \brief Wait For Event Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ #define __WFE __wfe /** \brief Send Event Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ #define __SEV __sev /** \brief Instruction Synchronization Barrier Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ #define __ISB() __isb(0xF) /** \brief Data Synchronization Barrier This function acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ #define __DSB() __dsb(0xF) /** \brief Data Memory Barrier This function ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ #define __DMB() __dmb(0xF) /** \brief Reverse byte order (32 bit) This function reverses the byte order in integer value. \param [in] value Value to reverse \return Reversed value */ #define __REV __rev /** \brief Reverse byte order (16 bit) This function reverses the byte order in two unsigned short values. \param [in] value Value to reverse \return Reversed value */ static __INLINE __ASM uint32_t __REV16(uint32_t value) { rev16 r0, r0 bx lr } /** \brief Reverse byte order in signed short value This function reverses the byte order in a signed short value with sign extension to integer. \param [in] value Value to reverse \return Reversed value */ static __INLINE __ASM int32_t __REVSH(int32_t value) { revsh r0, r0 bx lr } #if (__CORTEX_M >= 0x03) /** \brief Reverse bit order of value This function reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ #define __RBIT __rbit /** \brief LDR Exclusive (8 bit) This function performs a exclusive LDR command for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) /** \brief LDR Exclusive (16 bit) This function performs a exclusive LDR command for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) /** \brief LDR Exclusive (32 bit) This function performs a exclusive LDR command for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) /** \brief STR Exclusive (8 bit) This function performs a exclusive STR command for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXB(value, ptr) __strex(value, ptr) /** \brief STR Exclusive (16 bit) This function performs a exclusive STR command for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXH(value, ptr) __strex(value, ptr) /** \brief STR Exclusive (32 bit) This function performs a exclusive STR command for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXW(value, ptr) __strex(value, ptr) /** \brief Remove the exclusive lock This function removes the exclusive lock which is created by LDREX. */ #define __CLREX __clrex /** \brief Signed Saturate This function saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT __ssat /** \brief Unsigned Saturate This function saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ #define __USAT __usat /** \brief Count leading zeros This function counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ #define __CLZ __clz #endif /* (__CORTEX_M >= 0x03) */ #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ /* IAR iccarm specific functions */ #include #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ /* GNU gcc specific functions */ /** \brief No Operation No Operation does nothing. This instruction can be used for code alignment purposes. */ __attribute__( ( always_inline ) ) static __INLINE void __NOP(void) { __ASM volatile ("nop"); } /** \brief Wait For Interrupt Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ __attribute__( ( always_inline ) ) static __INLINE void __WFI(void) { __ASM volatile ("wfi"); } /** \brief Wait For Event Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ __attribute__( ( always_inline ) ) static __INLINE void __WFE(void) { __ASM volatile ("wfe"); } /** \brief Send Event Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ __attribute__( ( always_inline ) ) static __INLINE void __SEV(void) { __ASM volatile ("sev"); } /** \brief Instruction Synchronization Barrier Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ __attribute__( ( always_inline ) ) static __INLINE void __ISB(void) { __ASM volatile ("isb"); } /** \brief Data Synchronization Barrier This function acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __attribute__( ( always_inline ) ) static __INLINE void __DSB(void) { __ASM volatile ("dsb"); } /** \brief Data Memory Barrier This function ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ __attribute__( ( always_inline ) ) static __INLINE void __DMB(void) { __ASM volatile ("dmb"); } /** \brief Reverse byte order (32 bit) This function reverses the byte order in integer value. \param [in] value Value to reverse \return Reversed value */ __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value) { uint32_t result; __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); return(result); } /** \brief Reverse byte order (16 bit) This function reverses the byte order in two unsigned short values. \param [in] value Value to reverse \return Reversed value */ __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value) { uint32_t result; __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); return(result); } /** \brief Reverse byte order in signed short value This function reverses the byte order in a signed short value with sign extension to integer. \param [in] value Value to reverse \return Reversed value */ __attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value) { uint32_t result; __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); return(result); } #if (__CORTEX_M >= 0x03) /** \brief Reverse bit order of value This function reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ __attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); return(result); } /** \brief LDR Exclusive (8 bit) This function performs a exclusive LDR command for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr) { uint8_t result; __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); return(result); } /** \brief LDR Exclusive (16 bit) This function performs a exclusive LDR command for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr) { uint16_t result; __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); return(result); } /** \brief LDR Exclusive (32 bit) This function performs a exclusive LDR command for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); return(result); } /** \brief STR Exclusive (8 bit) This function performs a exclusive STR command for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) { uint32_t result; __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); return(result); } /** \brief STR Exclusive (16 bit) This function performs a exclusive STR command for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) { uint32_t result; __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); return(result); } /** \brief STR Exclusive (32 bit) This function performs a exclusive STR command for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); return(result); } /** \brief Remove the exclusive lock This function removes the exclusive lock which is created by LDREX. */ __attribute__( ( always_inline ) ) static __INLINE void __CLREX(void) { __ASM volatile ("clrex"); } /** \brief Signed Saturate This function saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT(ARG1,ARG2) \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) /** \brief Unsigned Saturate This function saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ #define __USAT(ARG1,ARG2) \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) /** \brief Count leading zeros This function counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ __attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value) { uint8_t result; __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); return(result); } #endif /* (__CORTEX_M >= 0x03) */ #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ /* TASKING carm specific functions */ /* * The CMSIS functions have been implemented as intrinsics in the compiler. * Please use "carm -?i" to get an up to date list of all intrinsics, * Including the CMSIS ones. */ #endif /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ #endif /* __CORE_CMINSTR_H */ ================================================ FILE: figure-simulator-discovery/Libraries/Device/STM32F4xx/Include/stm32f4xx.h ================================================ /** ****************************************************************************** * @file stm32f4xx.h * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32F4xx devices. * * The file is the unique include file that the application programmer * is using in the C source code, usually in main.c. This file contains: * - Configuration section that allows to select: * - The device used in the target application * - To use or not the peripherals drivers in application code(i.e. * code will be based on direct access to peripherals registers * rather than drivers API), this option is controlled by * "#define USE_STDPERIPH_DRIVER" * - To change few application-specific parameters such as the HSE * crystal frequency * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition * - Macros to access peripherals registers hardware * ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /** @addtogroup CMSIS * @{ */ /** @addtogroup stm32f4xx * @{ */ #ifndef __STM32F4xx_H #define __STM32F4xx_H #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ /** @addtogroup Library_configuration_section * @{ */ /* Uncomment the line below according to the target STM32 device used in your application */ #if !defined (STM32F4XX) #define STM32F4XX #endif /* Tip: To avoid modifying this file each time you need to switch between these devices, you can define the device in your toolchain compiler preprocessor. */ #if !defined (STM32F4XX) #error "Please select first the target STM32F4XX device used in your application (in stm32f4xx.h file)" #endif #if !defined (USE_STDPERIPH_DRIVER) /** * @brief Comment the line below if you will not use the peripherals drivers. In this case, these drivers will not be included and the application code will be based on direct access to peripherals registers */ /*#define USE_STDPERIPH_DRIVER*/ #endif /* USE_STDPERIPH_DRIVER */ /** * @brief In the following line adjust the value of External High Speed oscillator (HSE) used in your application Tip: To avoid modifying this file each time you need to use different HSE, you can define the HSE value in your toolchain compiler preprocessor. */ #if !defined (HSE_VALUE) #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ /** * @brief In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */ #if !defined (HSE_STARTUP_TIMEOUT) #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ #endif /* HSE_STARTUP_TIMEOUT */ #if !defined (HSI_VALUE) #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** * @brief STM32F4XX Standard Peripherals Library version number V1.0.2 */ #define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ #define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ #define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\ |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\ |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\ |(__STM32F4XX_STDPERIPH_VERSION_RC)) /** * @} */ /** @addtogroup Configuration_section_for_CMSIS * @{ */ /** * @brief Configuration of the Cortex-M4 Processor and Core Peripherals */ #define __CM4_REV 0x0001 /*!< Core revision r0p1 */ #define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ #define __FPU_PRESENT 1 /*!< FPU present */ /** * @brief STM32F4XX Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ typedef enum IRQn { /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ /****** STM32 specific Interrupt Numbers **********************************************************************/ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ FLASH_IRQn = 4, /*!< FLASH global Interrupt */ RCC_IRQn = 5, /*!< RCC global Interrupt */ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ USART1_IRQn = 37, /*!< USART1 global Interrupt */ USART2_IRQn = 38, /*!< USART2 global Interrupt */ USART3_IRQn = 39, /*!< USART3 global Interrupt */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ FSMC_IRQn = 48, /*!< FSMC global Interrupt */ SDIO_IRQn = 49, /*!< SDIO global Interrupt */ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ UART4_IRQn = 52, /*!< UART4 global Interrupt */ UART5_IRQn = 53, /*!< UART5 global Interrupt */ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ TIM7_IRQn = 55, /*!< TIM7 global interrupt */ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ ETH_IRQn = 61, /*!< Ethernet global Interrupt */ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ USART6_IRQn = 71, /*!< USART6 global interrupt */ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ DCMI_IRQn = 78, /*!< DCMI global interrupt */ CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ FPU_IRQn = 81 /*!< FPU global interrupt */ } IRQn_Type; /** * @} */ #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ #include "system_stm32f4xx.h" #include /** @addtogroup Exported_types * @{ */ /*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ typedef int32_t s32; typedef int16_t s16; typedef int8_t s8; typedef const int32_t sc32; /*!< Read Only */ typedef const int16_t sc16; /*!< Read Only */ typedef const int8_t sc8; /*!< Read Only */ typedef __IO int32_t vs32; typedef __IO int16_t vs16; typedef __IO int8_t vs8; typedef __I int32_t vsc32; /*!< Read Only */ typedef __I int16_t vsc16; /*!< Read Only */ typedef __I int8_t vsc8; /*!< Read Only */ typedef uint32_t u32; typedef uint16_t u16; typedef uint8_t u8; typedef const uint32_t uc32; /*!< Read Only */ typedef const uint16_t uc16; /*!< Read Only */ typedef const uint8_t uc8; /*!< Read Only */ typedef __IO uint32_t vu32; typedef __IO uint16_t vu16; typedef __IO uint8_t vu8; typedef __I uint32_t vuc32; /*!< Read Only */ typedef __I uint16_t vuc16; /*!< Read Only */ typedef __I uint8_t vuc8; /*!< Read Only */ typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; /** * @} */ /** @addtogroup Peripheral_registers_structures * @{ */ /** * @brief Analog to Digital Converter */ typedef struct { __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ } ADC_TypeDef; typedef struct { __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ __IO uint32_t CDR; /*!< ADC common regular data register for dual AND triple modes, Address offset: ADC1 base address + 0x308 */ } ADC_Common_TypeDef; /** * @brief Controller Area Network TxMailBox */ typedef struct { __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ __IO uint32_t TDLR; /*!< CAN mailbox data low register */ __IO uint32_t TDHR; /*!< CAN mailbox data high register */ } CAN_TxMailBox_TypeDef; /** * @brief Controller Area Network FIFOMailBox */ typedef struct { __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ } CAN_FIFOMailBox_TypeDef; /** * @brief Controller Area Network FilterRegister */ typedef struct { __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ } CAN_FilterRegister_TypeDef; /** * @brief Controller Area Network */ typedef struct { __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ uint32_t RESERVED2; /*!< Reserved, 0x208 */ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ uint32_t RESERVED3; /*!< Reserved, 0x210 */ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ uint32_t RESERVED4; /*!< Reserved, 0x218 */ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ } CAN_TypeDef; /** * @brief CRC calculation unit */ typedef struct { __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ uint8_t RESERVED0; /*!< Reserved, 0x05 */ uint16_t RESERVED1; /*!< Reserved, 0x06 */ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ } CRC_TypeDef; /** * @brief Digital to Analog Converter */ typedef struct { __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ } DAC_TypeDef; /** * @brief Debug MCU */ typedef struct { __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ }DBGMCU_TypeDef; /** * @brief DCMI */ typedef struct { __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ } DCMI_TypeDef; /** * @brief DMA Controller */ typedef struct { __IO uint32_t CR; /*!< DMA stream x configuration register */ __IO uint32_t NDTR; /*!< DMA stream x number of data register */ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ } DMA_Stream_TypeDef; typedef struct { __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ } DMA_TypeDef; /** * @brief Ethernet MAC */ typedef struct { __IO uint32_t MACCR; __IO uint32_t MACFFR; __IO uint32_t MACHTHR; __IO uint32_t MACHTLR; __IO uint32_t MACMIIAR; __IO uint32_t MACMIIDR; __IO uint32_t MACFCR; __IO uint32_t MACVLANTR; /* 8 */ uint32_t RESERVED0[2]; __IO uint32_t MACRWUFFR; /* 11 */ __IO uint32_t MACPMTCSR; uint32_t RESERVED1[2]; __IO uint32_t MACSR; /* 15 */ __IO uint32_t MACIMR; __IO uint32_t MACA0HR; __IO uint32_t MACA0LR; __IO uint32_t MACA1HR; __IO uint32_t MACA1LR; __IO uint32_t MACA2HR; __IO uint32_t MACA2LR; __IO uint32_t MACA3HR; __IO uint32_t MACA3LR; /* 24 */ uint32_t RESERVED2[40]; __IO uint32_t MMCCR; /* 65 */ __IO uint32_t MMCRIR; __IO uint32_t MMCTIR; __IO uint32_t MMCRIMR; __IO uint32_t MMCTIMR; /* 69 */ uint32_t RESERVED3[14]; __IO uint32_t MMCTGFSCCR; /* 84 */ __IO uint32_t MMCTGFMSCCR; uint32_t RESERVED4[5]; __IO uint32_t MMCTGFCR; uint32_t RESERVED5[10]; __IO uint32_t MMCRFCECR; __IO uint32_t MMCRFAECR; uint32_t RESERVED6[10]; __IO uint32_t MMCRGUFCR; uint32_t RESERVED7[334]; __IO uint32_t PTPTSCR; __IO uint32_t PTPSSIR; __IO uint32_t PTPTSHR; __IO uint32_t PTPTSLR; __IO uint32_t PTPTSHUR; __IO uint32_t PTPTSLUR; __IO uint32_t PTPTSAR; __IO uint32_t PTPTTHR; __IO uint32_t PTPTTLR; __IO uint32_t RESERVED8; __IO uint32_t PTPTSSR; uint32_t RESERVED9[565]; __IO uint32_t DMABMR; __IO uint32_t DMATPDR; __IO uint32_t DMARPDR; __IO uint32_t DMARDLAR; __IO uint32_t DMATDLAR; __IO uint32_t DMASR; __IO uint32_t DMAOMR; __IO uint32_t DMAIER; __IO uint32_t DMAMFBOCR; __IO uint32_t DMARSWTR; uint32_t RESERVED10[8]; __IO uint32_t DMACHTDR; __IO uint32_t DMACHRDR; __IO uint32_t DMACHTBAR; __IO uint32_t DMACHRBAR; } ETH_TypeDef; /** * @brief External Interrupt/Event Controller */ typedef struct { __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ } EXTI_TypeDef; /** * @brief FLASH Registers */ typedef struct { __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ __IO uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x14 */ } FLASH_TypeDef; /** * @brief Flexible Static Memory Controller */ typedef struct { __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ } FSMC_Bank1_TypeDef; /** * @brief Flexible Static Memory Controller Bank1E */ typedef struct { __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ } FSMC_Bank1E_TypeDef; /** * @brief Flexible Static Memory Controller Bank2 */ typedef struct { __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ uint32_t RESERVED0; /*!< Reserved, 0x70 */ __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ } FSMC_Bank2_TypeDef; /** * @brief Flexible Static Memory Controller Bank3 */ typedef struct { __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ uint32_t RESERVED0; /*!< Reserved, 0x90 */ __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ } FSMC_Bank3_TypeDef; /** * @brief Flexible Static Memory Controller Bank4 */ typedef struct { __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ } FSMC_Bank4_TypeDef; /** * @brief General Purpose I/O */ typedef struct { __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ } GPIO_TypeDef; /** * @brief System configuration controller */ typedef struct { __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ } SYSCFG_TypeDef; /** * @brief Inter-integrated Circuit Interface */ typedef struct { __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ uint16_t RESERVED0; /*!< Reserved, 0x02 */ __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ uint16_t RESERVED1; /*!< Reserved, 0x06 */ __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ uint16_t RESERVED2; /*!< Reserved, 0x0A */ __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ uint16_t RESERVED3; /*!< Reserved, 0x0E */ __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */ uint16_t RESERVED4; /*!< Reserved, 0x12 */ __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ uint16_t RESERVED5; /*!< Reserved, 0x16 */ __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ uint16_t RESERVED6; /*!< Reserved, 0x1A */ __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ uint16_t RESERVED7; /*!< Reserved, 0x1E */ __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ uint16_t RESERVED8; /*!< Reserved, 0x22 */ } I2C_TypeDef; /** * @brief Independent WATCHDOG */ typedef struct { __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ } IWDG_TypeDef; /** * @brief Power Control */ typedef struct { __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ } PWR_TypeDef; /** * @brief Reset and Clock Control */ typedef struct { __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ uint32_t RESERVED0; /*!< Reserved, 0x1C */ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ uint32_t RESERVED2; /*!< Reserved, 0x3C */ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ uint32_t RESERVED4; /*!< Reserved, 0x5C */ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ } RCC_TypeDef; /** * @brief Real-Time Clock */ typedef struct { __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ uint32_t RESERVED7; /*!< Reserved, 0x4C */ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ } RTC_TypeDef; /** * @brief SD host Interface */ typedef struct { __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ } SDIO_TypeDef; /** * @brief Serial Peripheral Interface */ typedef struct { __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ uint16_t RESERVED0; /*!< Reserved, 0x02 */ __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ uint16_t RESERVED1; /*!< Reserved, 0x06 */ __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */ uint16_t RESERVED2; /*!< Reserved, 0x0A */ __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ uint16_t RESERVED3; /*!< Reserved, 0x0E */ __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ uint16_t RESERVED4; /*!< Reserved, 0x12 */ __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ uint16_t RESERVED5; /*!< Reserved, 0x16 */ __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ uint16_t RESERVED6; /*!< Reserved, 0x1A */ __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ uint16_t RESERVED7; /*!< Reserved, 0x1E */ __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ uint16_t RESERVED8; /*!< Reserved, 0x22 */ } SPI_TypeDef; /** * @brief TIM */ typedef struct { __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ uint16_t RESERVED0; /*!< Reserved, 0x02 */ __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ uint16_t RESERVED1; /*!< Reserved, 0x06 */ __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ uint16_t RESERVED2; /*!< Reserved, 0x0A */ __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ uint16_t RESERVED3; /*!< Reserved, 0x0E */ __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */ uint16_t RESERVED4; /*!< Reserved, 0x12 */ __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ uint16_t RESERVED5; /*!< Reserved, 0x16 */ __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ uint16_t RESERVED6; /*!< Reserved, 0x1A */ __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ uint16_t RESERVED7; /*!< Reserved, 0x1E */ __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ uint16_t RESERVED8; /*!< Reserved, 0x22 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ uint16_t RESERVED9; /*!< Reserved, 0x2A */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ uint16_t RESERVED10; /*!< Reserved, 0x32 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ uint16_t RESERVED11; /*!< Reserved, 0x46 */ __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ uint16_t RESERVED12; /*!< Reserved, 0x4A */ __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ uint16_t RESERVED13; /*!< Reserved, 0x4E */ __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ uint16_t RESERVED14; /*!< Reserved, 0x52 */ } TIM_TypeDef; /** * @brief Universal Synchronous Asynchronous Receiver Transmitter */ typedef struct { __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */ uint16_t RESERVED0; /*!< Reserved, 0x02 */ __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */ uint16_t RESERVED1; /*!< Reserved, 0x06 */ __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ uint16_t RESERVED2; /*!< Reserved, 0x0A */ __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ uint16_t RESERVED3; /*!< Reserved, 0x0E */ __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ uint16_t RESERVED4; /*!< Reserved, 0x12 */ __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ uint16_t RESERVED5; /*!< Reserved, 0x16 */ __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ uint16_t RESERVED6; /*!< Reserved, 0x1A */ } USART_TypeDef; /** * @brief Window WATCHDOG */ typedef struct { __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ } WWDG_TypeDef; /** * @brief Crypto Processor */ typedef struct { __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */ __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ } CRYP_TypeDef; /** * @brief HASH */ typedef struct { __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ __IO uint32_t CSR[51]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1C0 */ } HASH_TypeDef; /** * @brief HASH */ typedef struct { __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ } RNG_TypeDef; /** * @} */ /** @addtogroup Peripheral_memory_map * @{ */ #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */ #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */ #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */ #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */ #define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */ #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */ #define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */ #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ #define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ /* Legacy defines */ #define SRAM_BASE SRAM1_BASE #define SRAM_BB_BASE SRAM1_BB_BASE /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) /*!< APB1 peripherals */ #define TIM2_BASE (APB1PERIPH_BASE + 0x0000) #define TIM3_BASE (APB1PERIPH_BASE + 0x0400) #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) #define TIM6_BASE (APB1PERIPH_BASE + 0x1000) #define TIM7_BASE (APB1PERIPH_BASE + 0x1400) #define TIM12_BASE (APB1PERIPH_BASE + 0x1800) #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) #define TIM14_BASE (APB1PERIPH_BASE + 0x2000) #define RTC_BASE (APB1PERIPH_BASE + 0x2800) #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) #define IWDG_BASE (APB1PERIPH_BASE + 0x3000) #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400) #define SPI2_BASE (APB1PERIPH_BASE + 0x3800) #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000) #define USART2_BASE (APB1PERIPH_BASE + 0x4400) #define USART3_BASE (APB1PERIPH_BASE + 0x4800) #define UART4_BASE (APB1PERIPH_BASE + 0x4C00) #define UART5_BASE (APB1PERIPH_BASE + 0x5000) #define I2C1_BASE (APB1PERIPH_BASE + 0x5400) #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) #define CAN1_BASE (APB1PERIPH_BASE + 0x6400) #define CAN2_BASE (APB1PERIPH_BASE + 0x6800) #define PWR_BASE (APB1PERIPH_BASE + 0x7000) #define DAC_BASE (APB1PERIPH_BASE + 0x7400) /*!< APB2 peripherals */ #define TIM1_BASE (APB2PERIPH_BASE + 0x0000) #define TIM8_BASE (APB2PERIPH_BASE + 0x0400) #define USART1_BASE (APB2PERIPH_BASE + 0x1000) #define USART6_BASE (APB2PERIPH_BASE + 0x1400) #define ADC1_BASE (APB2PERIPH_BASE + 0x2000) #define ADC2_BASE (APB2PERIPH_BASE + 0x2100) #define ADC3_BASE (APB2PERIPH_BASE + 0x2200) #define ADC_BASE (APB2PERIPH_BASE + 0x2300) #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) #define SPI1_BASE (APB2PERIPH_BASE + 0x3000) #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) #define TIM9_BASE (APB2PERIPH_BASE + 0x4000) #define TIM10_BASE (APB2PERIPH_BASE + 0x4400) #define TIM11_BASE (APB2PERIPH_BASE + 0x4800) /*!< AHB1 peripherals */ #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) #define CRC_BASE (AHB1PERIPH_BASE + 0x3000) #define RCC_BASE (AHB1PERIPH_BASE + 0x3800) #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) #define DMA1_Stream0_BASE (DMA1_BASE + 0x010) #define DMA1_Stream1_BASE (DMA1_BASE + 0x028) #define DMA1_Stream2_BASE (DMA1_BASE + 0x040) #define DMA1_Stream3_BASE (DMA1_BASE + 0x058) #define DMA1_Stream4_BASE (DMA1_BASE + 0x070) #define DMA1_Stream5_BASE (DMA1_BASE + 0x088) #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) #define DMA2_Stream0_BASE (DMA2_BASE + 0x010) #define DMA2_Stream1_BASE (DMA2_BASE + 0x028) #define DMA2_Stream2_BASE (DMA2_BASE + 0x040) #define DMA2_Stream3_BASE (DMA2_BASE + 0x058) #define DMA2_Stream4_BASE (DMA2_BASE + 0x070) #define DMA2_Stream5_BASE (DMA2_BASE + 0x088) #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) #define ETH_BASE (AHB1PERIPH_BASE + 0x8000) #define ETH_MAC_BASE (ETH_BASE) #define ETH_MMC_BASE (ETH_BASE + 0x0100) #define ETH_PTP_BASE (ETH_BASE + 0x0700) #define ETH_DMA_BASE (ETH_BASE + 0x1000) /*!< AHB2 peripherals */ #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) #define CRYP_BASE (AHB2PERIPH_BASE + 0x60000) #define HASH_BASE (AHB2PERIPH_BASE + 0x60400) #define RNG_BASE (AHB2PERIPH_BASE + 0x60800) /*!< FSMC Bankx registers base address */ #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /* Debug MCU registers base address */ #define DBGMCU_BASE ((uint32_t )0xE0042000) /** * @} */ /** @addtogroup Peripheral_declaration * @{ */ #define TIM2 ((TIM_TypeDef *) TIM2_BASE) #define TIM3 ((TIM_TypeDef *) TIM3_BASE) #define TIM4 ((TIM_TypeDef *) TIM4_BASE) #define TIM5 ((TIM_TypeDef *) TIM5_BASE) #define TIM6 ((TIM_TypeDef *) TIM6_BASE) #define TIM7 ((TIM_TypeDef *) TIM7_BASE) #define TIM12 ((TIM_TypeDef *) TIM12_BASE) #define TIM13 ((TIM_TypeDef *) TIM13_BASE) #define TIM14 ((TIM_TypeDef *) TIM14_BASE) #define RTC ((RTC_TypeDef *) RTC_BASE) #define WWDG ((WWDG_TypeDef *) WWDG_BASE) #define IWDG ((IWDG_TypeDef *) IWDG_BASE) #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) #define SPI2 ((SPI_TypeDef *) SPI2_BASE) #define SPI3 ((SPI_TypeDef *) SPI3_BASE) #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) #define USART2 ((USART_TypeDef *) USART2_BASE) #define USART3 ((USART_TypeDef *) USART3_BASE) #define UART4 ((USART_TypeDef *) UART4_BASE) #define UART5 ((USART_TypeDef *) UART5_BASE) #define I2C1 ((I2C_TypeDef *) I2C1_BASE) #define I2C2 ((I2C_TypeDef *) I2C2_BASE) #define I2C3 ((I2C_TypeDef *) I2C3_BASE) #define CAN1 ((CAN_TypeDef *) CAN1_BASE) #define CAN2 ((CAN_TypeDef *) CAN2_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) #define DAC ((DAC_TypeDef *) DAC_BASE) #define TIM1 ((TIM_TypeDef *) TIM1_BASE) #define TIM8 ((TIM_TypeDef *) TIM8_BASE) #define USART1 ((USART_TypeDef *) USART1_BASE) #define USART6 ((USART_TypeDef *) USART6_BASE) #define ADC ((ADC_Common_TypeDef *) ADC_BASE) #define ADC1 ((ADC_TypeDef *) ADC1_BASE) #define ADC2 ((ADC_TypeDef *) ADC2_BASE) #define ADC3 ((ADC_TypeDef *) ADC3_BASE) #define SDIO ((SDIO_TypeDef *) SDIO_BASE) #define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) #define EXTI ((EXTI_TypeDef *) EXTI_BASE) #define TIM9 ((TIM_TypeDef *) TIM9_BASE) #define TIM10 ((TIM_TypeDef *) TIM10_BASE) #define TIM11 ((TIM_TypeDef *) TIM11_BASE) #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) #define CRC ((CRC_TypeDef *) CRC_BASE) #define RCC ((RCC_TypeDef *) RCC_BASE) #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) #define DMA1 ((DMA_TypeDef *) DMA1_BASE) #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) #define ETH ((ETH_TypeDef *) ETH_BASE) #define DCMI ((DCMI_TypeDef *) DCMI_BASE) #define CRYP ((CRYP_TypeDef *) CRYP_BASE) #define HASH ((HASH_TypeDef *) HASH_BASE) #define RNG ((RNG_TypeDef *) RNG_BASE) #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) #define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) #define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) /** * @} */ /** @addtogroup Exported_constants * @{ */ /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ /******************************************************************************/ /* Peripheral Registers_Bits_Definition */ /******************************************************************************/ /******************************************************************************/ /* */ /* Analog to Digital Converter */ /* */ /******************************************************************************/ /******************** Bit definition for ADC_SR register ********************/ #define ADC_SR_AWD ((uint8_t)0x01) /*!
© COPYRIGHT 2012 STMicroelectronics
* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /** @addtogroup CMSIS * @{ */ /** @addtogroup stm32f4xx_system * @{ */ /** * @brief Define to prevent recursive inclusion */ #ifndef __SYSTEM_STM32F4XX_H #define __SYSTEM_STM32F4XX_H #ifdef __cplusplus extern "C" { #endif /** @addtogroup STM32F4xx_System_Includes * @{ */ /** * @} */ /** @addtogroup STM32F4xx_System_Exported_types * @{ */ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ /** * @} */ /** @addtogroup STM32F4xx_System_Exported_Constants * @{ */ /** * @} */ /** @addtogroup STM32F4xx_System_Exported_Macros * @{ */ /** * @} */ /** @addtogroup STM32F4xx_System_Exported_Functions * @{ */ extern void SystemInit(void); extern void SystemCoreClockUpdate(void); /** * @} */ #ifdef __cplusplus } #endif #endif /*__SYSTEM_STM32F4XX_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/Device/STM32F4xx/Release_Notes.html ================================================ Release Notes for STM32F4xx CMSIS


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Release Notes for STM32F4xx CMSIS

Copyright 2012 STMicroelectronics

 

Contents

  1. STM32F4xx CMSIS update History
  2. License

STM32F4xx CMSIS update History

V1.0.2 / 05-March-2012

Main Changes

  • All source files: license disclaimer text update and add link to the License file on ST Internet.

V1.0.1 / 28-December-2011

Main Changes

  • All source files: update disclaimer to add reference to the new license agreement
  • stm32f4xx.h
    • Correct bit definition: RCC_AHB2RSTR_HSAHRST changed to RCC_AHB2RSTR_HASHRST

V1.0.0 / 30-September-2011

Main Changes

  • First official release for STM32F40x/41x devices
  • Add startup file for TASKING toolchain
  • system_stm32f4xx.c: driver's comments update

V1.0.0RC2 / 26-September-2011

Main Changes

  • Official version (V1.0.0) Release Candidate2 for STM32F40x/41x devices
  • stm32f4xx.h
    • Add define for Cortex-M4 revision __CM4_REV
    • Correct RCC_CFGR_PPRE2_DIV16 bit (in RCC_CFGR register) value to 0x0000E000
    • Correct some bits definition to be in line with naming used in the Reference Manual (RM0090)
      • GPIO_OTYPER_IDR_x changed to GPIO_IDR_IDR_x
      • GPIO_OTYPER_ODR_x changed to GPIO_ODR_ODR_x
      • SYSCFG_PMC_MII_RMII changed to SYSCFG_PMC_MII_RMII_SEL
      • RCC_APB2RSTR_SPI1 changed to RCC_APB2RSTR_SPI1RST
      • DBGMCU_APB1_FZ_DBG_IWDEG_STOP changed to DBGMCU_APB1_FZ_DBG_IWDG_STOP
      • PWR_CR_PMODE changed to PWR_CR_VOS
      • PWR_CSR_REGRDY changed to PWR_CSR_VOSRDY
      • Add new define RCC_AHB1ENR_CCMDATARAMEN
      • Add new defines SRAM2_BASE, CCMDATARAM_BASE and BKPSRAM_BASE
    • GPIO_TypeDef structure: in the comment change AFR[2] address mapping to 0x20-0x24 instead of 0x24-0x28
  • system_stm32f4xx.c
    • SystemInit(): add code to enable the FPU
    • SetSysClock(): change PWR_CR_PMODE by PWR_CR_VOS
    • SystemInit_ExtMemCtl(): remove commented values
  • startup (for all compilers)
    • Delete code used to enable the FPU (moved to system_stm32f4xx.c file)
    • File’s header updated

V1.0.0RC1 / 25-August-2011

Main Changes

  • Official version (V1.0.0) Release Candidate1 for STM32F4xx devices

License

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:


Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

For complete documentation on STM32 Microcontrollers visit www.st.com/STM32

 

================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/Release_Notes.html ================================================ Release Notes for STM32F4xx Standard Peripherals Library Drivers

 

Back to Release page

Release Notes for STM32F4xx Standard Peripherals Library Drivers

Copyright 2012 STMicroelectronics

 

Contents

  1. STM32F4xx Standard Peripherals Library Drivers update History
  2. License

STM32F4xx Standard Peripherals Library Drivers  update History

V1.0.2 / 05-March-2012

Main Changes

  • All source files: license disclaimer text update and add link to the License file on ST Internet.
  • stm32f4xx_dcmi.c
    • DCMI_GetFlagStatus() function: fix test condition on RISR register, use if (dcmireg == 0x00) instead of if (dcmireg == 0x01)
  • stm32f4xx_pwr.c
    • PWR_PVDLevelConfig() function: remove value of the voltage threshold corresponding to each PVD detection level, user should refer to the electrical characteristics of the STM32 device datasheet to have the correct value

V1.0.1 / 28-December-2011

Main Changes

  • All source files: update disclaimer to add reference to the new license agreement
  • stm32f4xx_rtc.c: 
    • In RTC_FLAGS_MASK define: add RTC_FLAG_RECALPF and RTC_FLAG_SHPF
    • RTC_DeInit() function: add reset of the following registers: SHIFTR, CALR, ALRMASSR and ALRMBSSR
    • RTC_SetTime() and RTC_SetDate() functions: add test condition on BYPSHAD flag before to test RSF flag (when Bypass mode is enabled, the RSF bit is never set).

V1.0.0 / 30-September-2011

Main Changes

  • First official release for STM32F40x/41x devices
  • stm32f4xx_rtc.c: remove useless code from RTC_GetDate() function
  • stm32f4xx_rcc.c, stm32f4xx_spi.c, stm32f4xx_wwdg.c and stm32f4xx_syscfg.c: driver's comments update

V1.0.0RC2 / 26-September-2011

Main Changes

  • Official version (V1.0.0) Release Candidate1 for STM32F40x/STM32F41x devices
  • stm32f4xx_usart.h/.c
    • Update procedure to check on overrun error interrupt pending bit, defines for the following flag are added:
      • USART_IT_ORE_RX: this flag is set if overrun error interrupt occurs and RXNEIE bit is set
      • USART_IT_ORE_ER: this flag is set if overrun error interrupt occurs and EIE bit is set
  • stm32f4xx_tim.c
    • TIM_UpdateRequestConfig(): correct function header's comment 
    • TIM_ICInit(): add assert macros to test if the passed TIM parameter has channel 2, 3 or 4
  • stm32f4xx_pwr.h/.c
    • Rename PWR_FLAG_REGRDY constant to PWR_CSR_REGRDY
    • Rename PWR_FLAG_VOSRDY constant to PWR_CSR_VOSRDY
    • Rename PWR_HighPerformanceModeCmd(FunctionalState NewState) function to PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage)
  • stm32f4xx_rcc.h/.c
    • RCC_AHB1PeriphClockCmd(): add new constant RCC_AHB1Periph_CCMDATARAMEN as value for RCC_AHB1Periph parameter
  • stm32f4xx_spi.h
    • IS_I2S_EXT_PERIPH(): add check on I2S3ext peripheral

V1.0.0RC1 / 25-August-2011

Main Changes

  • Official version (V1.0.0) Release Candidate1 for STM32F4xx devices

License

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:


Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

For complete documentation on STM32 Microcontrollers visit www.st.com/STM32

 

================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/misc.h ================================================ /** ****************************************************************************** * @file misc.h * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file contains all the functions prototypes for the miscellaneous * firmware library functions (add-on to CMSIS functions). ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __MISC_H #define __MISC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup MISC * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief NVIC Init Structure definition */ typedef struct { uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. This parameter can be an enumerator of @ref IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file) */ uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel specified in NVIC_IRQChannel. This parameter can be a value between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table A lower priority value indicates a higher priority */ uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified in NVIC_IRQChannel. This parameter can be a value between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table A lower priority value indicates a higher priority */ FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel will be enabled or disabled. This parameter can be set either to ENABLE or DISABLE */ } NVIC_InitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup MISC_Exported_Constants * @{ */ /** @defgroup MISC_Vector_Table_Base * @{ */ #define NVIC_VectTab_RAM ((uint32_t)0x20000000) #define NVIC_VectTab_FLASH ((uint32_t)0x08000000) #define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ ((VECTTAB) == NVIC_VectTab_FLASH)) /** * @} */ /** @defgroup MISC_System_Low_Power * @{ */ #define NVIC_LP_SEVONPEND ((uint8_t)0x10) #define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) #define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) #define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ ((LP) == NVIC_LP_SLEEPDEEP) || \ ((LP) == NVIC_LP_SLEEPONEXIT)) /** * @} */ /** @defgroup MISC_Preemption_Priority_Group * @{ */ #define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ #define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ #define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ #define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ #define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ ((GROUP) == NVIC_PriorityGroup_1) || \ ((GROUP) == NVIC_PriorityGroup_2) || \ ((GROUP) == NVIC_PriorityGroup_3) || \ ((GROUP) == NVIC_PriorityGroup_4)) #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) #define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) /** * @} */ /** @defgroup MISC_SysTick_clock_source * @{ */ #define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) #define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); #ifdef __cplusplus } #endif #endif /* __MISC_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h ================================================ /** ****************************************************************************** * @file stm32f4xx_adc.h * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file contains all the functions prototypes for the ADC firmware * library. ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_ADC_H #define __STM32F4xx_ADC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup ADC * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief ADC Init structure definition */ typedef struct { uint32_t ADC_Resolution; /*!< Configures the ADC resolution dual mode. This parameter can be a value of @ref ADC_resolution */ FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in Scan (multichannels) or Single (one channel) mode. This parameter can be set to ENABLE or DISABLE */ FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in Continuous or Single mode. This parameter can be set to ENABLE or DISABLE. */ uint32_t ADC_ExternalTrigConvEdge; /*!< Select the external trigger edge and enable the trigger of a regular group. This parameter can be a value of @ref ADC_external_trigger_edge_for_regular_channels_conversion */ uint32_t ADC_ExternalTrigConv; /*!< Select the external event used to trigger the start of conversion of a regular group. This parameter can be a value of @ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */ uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right. This parameter can be a value of @ref ADC_data_align */ uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions that will be done using the sequencer for regular channel group. This parameter must range from 1 to 16. */ }ADC_InitTypeDef; /** * @brief ADC Common Init structure definition */ typedef struct { uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or multi mode. This parameter can be a value of @ref ADC_Common_mode */ uint32_t ADC_Prescaler; /*!< Select the frequency of the clock to the ADC. The clock is common for all the ADCs. This parameter can be a value of @ref ADC_Prescaler */ uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode. This parameter can be a value of @ref ADC_Direct_memory_access_mode_for_multi_mode */ uint32_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */ }ADC_CommonInitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup ADC_Exported_Constants * @{ */ #define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ ((PERIPH) == ADC2) || \ ((PERIPH) == ADC3)) /** @defgroup ADC_Common_mode * @{ */ #define ADC_Mode_Independent ((uint32_t)0x00000000) #define ADC_DualMode_RegSimult_InjecSimult ((uint32_t)0x00000001) #define ADC_DualMode_RegSimult_AlterTrig ((uint32_t)0x00000002) #define ADC_DualMode_InjecSimult ((uint32_t)0x00000005) #define ADC_DualMode_RegSimult ((uint32_t)0x00000006) #define ADC_DualMode_Interl ((uint32_t)0x00000007) #define ADC_DualMode_AlterTrig ((uint32_t)0x00000009) #define ADC_TripleMode_RegSimult_InjecSimult ((uint32_t)0x00000011) #define ADC_TripleMode_RegSimult_AlterTrig ((uint32_t)0x00000012) #define ADC_TripleMode_InjecSimult ((uint32_t)0x00000015) #define ADC_TripleMode_RegSimult ((uint32_t)0x00000016) #define ADC_TripleMode_Interl ((uint32_t)0x00000017) #define ADC_TripleMode_AlterTrig ((uint32_t)0x00000019) #define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \ ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \ ((MODE) == ADC_DualMode_InjecSimult) || \ ((MODE) == ADC_DualMode_RegSimult) || \ ((MODE) == ADC_DualMode_Interl) || \ ((MODE) == ADC_DualMode_AlterTrig) || \ ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \ ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \ ((MODE) == ADC_TripleMode_InjecSimult) || \ ((MODE) == ADC_TripleMode_RegSimult) || \ ((MODE) == ADC_TripleMode_Interl) || \ ((MODE) == ADC_TripleMode_AlterTrig)) /** * @} */ /** @defgroup ADC_Prescaler * @{ */ #define ADC_Prescaler_Div2 ((uint32_t)0x00000000) #define ADC_Prescaler_Div4 ((uint32_t)0x00010000) #define ADC_Prescaler_Div6 ((uint32_t)0x00020000) #define ADC_Prescaler_Div8 ((uint32_t)0x00030000) #define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \ ((PRESCALER) == ADC_Prescaler_Div4) || \ ((PRESCALER) == ADC_Prescaler_Div6) || \ ((PRESCALER) == ADC_Prescaler_Div8)) /** * @} */ /** @defgroup ADC_Direct_memory_access_mode_for_multi_mode * @{ */ #define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /* DMA mode disabled */ #define ADC_DMAAccessMode_1 ((uint32_t)0x00004000) /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/ #define ADC_DMAAccessMode_2 ((uint32_t)0x00008000) /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/ #define ADC_DMAAccessMode_3 ((uint32_t)0x0000C000) /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */ #define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \ ((MODE) == ADC_DMAAccessMode_1) || \ ((MODE) == ADC_DMAAccessMode_2) || \ ((MODE) == ADC_DMAAccessMode_3)) /** * @} */ /** @defgroup ADC_delay_between_2_sampling_phases * @{ */ #define ADC_TwoSamplingDelay_5Cycles ((uint32_t)0x00000000) #define ADC_TwoSamplingDelay_6Cycles ((uint32_t)0x00000100) #define ADC_TwoSamplingDelay_7Cycles ((uint32_t)0x00000200) #define ADC_TwoSamplingDelay_8Cycles ((uint32_t)0x00000300) #define ADC_TwoSamplingDelay_9Cycles ((uint32_t)0x00000400) #define ADC_TwoSamplingDelay_10Cycles ((uint32_t)0x00000500) #define ADC_TwoSamplingDelay_11Cycles ((uint32_t)0x00000600) #define ADC_TwoSamplingDelay_12Cycles ((uint32_t)0x00000700) #define ADC_TwoSamplingDelay_13Cycles ((uint32_t)0x00000800) #define ADC_TwoSamplingDelay_14Cycles ((uint32_t)0x00000900) #define ADC_TwoSamplingDelay_15Cycles ((uint32_t)0x00000A00) #define ADC_TwoSamplingDelay_16Cycles ((uint32_t)0x00000B00) #define ADC_TwoSamplingDelay_17Cycles ((uint32_t)0x00000C00) #define ADC_TwoSamplingDelay_18Cycles ((uint32_t)0x00000D00) #define ADC_TwoSamplingDelay_19Cycles ((uint32_t)0x00000E00) #define ADC_TwoSamplingDelay_20Cycles ((uint32_t)0x00000F00) #define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \ ((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \ ((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \ ((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \ ((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \ ((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \ ((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \ ((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \ ((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \ ((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \ ((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \ ((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \ ((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \ ((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \ ((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \ ((DELAY) == ADC_TwoSamplingDelay_20Cycles)) /** * @} */ /** @defgroup ADC_resolution * @{ */ #define ADC_Resolution_12b ((uint32_t)0x00000000) #define ADC_Resolution_10b ((uint32_t)0x01000000) #define ADC_Resolution_8b ((uint32_t)0x02000000) #define ADC_Resolution_6b ((uint32_t)0x03000000) #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \ ((RESOLUTION) == ADC_Resolution_10b) || \ ((RESOLUTION) == ADC_Resolution_8b) || \ ((RESOLUTION) == ADC_Resolution_6b)) /** * @} */ /** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion * @{ */ #define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000) #define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000) #define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000) #define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000) #define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \ ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \ ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \ ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling)) /** * @} */ /** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion * @{ */ #define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) #define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x01000000) #define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x02000000) #define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000) #define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x04000000) #define ADC_ExternalTrigConv_T2_CC4 ((uint32_t)0x05000000) #define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000) #define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000) #define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x08000000) #define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x09000000) #define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x0A000000) #define ADC_ExternalTrigConv_T5_CC2 ((uint32_t)0x0B000000) #define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x0C000000) #define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x0D000000) #define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x0E000000) #define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000) #define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \ ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \ ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ ((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \ ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \ ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11)) /** * @} */ /** @defgroup ADC_data_align * @{ */ #define ADC_DataAlign_Right ((uint32_t)0x00000000) #define ADC_DataAlign_Left ((uint32_t)0x00000800) #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ ((ALIGN) == ADC_DataAlign_Left)) /** * @} */ /** @defgroup ADC_channels * @{ */ #define ADC_Channel_0 ((uint8_t)0x00) #define ADC_Channel_1 ((uint8_t)0x01) #define ADC_Channel_2 ((uint8_t)0x02) #define ADC_Channel_3 ((uint8_t)0x03) #define ADC_Channel_4 ((uint8_t)0x04) #define ADC_Channel_5 ((uint8_t)0x05) #define ADC_Channel_6 ((uint8_t)0x06) #define ADC_Channel_7 ((uint8_t)0x07) #define ADC_Channel_8 ((uint8_t)0x08) #define ADC_Channel_9 ((uint8_t)0x09) #define ADC_Channel_10 ((uint8_t)0x0A) #define ADC_Channel_11 ((uint8_t)0x0B) #define ADC_Channel_12 ((uint8_t)0x0C) #define ADC_Channel_13 ((uint8_t)0x0D) #define ADC_Channel_14 ((uint8_t)0x0E) #define ADC_Channel_15 ((uint8_t)0x0F) #define ADC_Channel_16 ((uint8_t)0x10) #define ADC_Channel_17 ((uint8_t)0x11) #define ADC_Channel_18 ((uint8_t)0x12) #define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) #define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) #define ADC_Channel_Vbat ((uint8_t)ADC_Channel_18) #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \ ((CHANNEL) == ADC_Channel_1) || \ ((CHANNEL) == ADC_Channel_2) || \ ((CHANNEL) == ADC_Channel_3) || \ ((CHANNEL) == ADC_Channel_4) || \ ((CHANNEL) == ADC_Channel_5) || \ ((CHANNEL) == ADC_Channel_6) || \ ((CHANNEL) == ADC_Channel_7) || \ ((CHANNEL) == ADC_Channel_8) || \ ((CHANNEL) == ADC_Channel_9) || \ ((CHANNEL) == ADC_Channel_10) || \ ((CHANNEL) == ADC_Channel_11) || \ ((CHANNEL) == ADC_Channel_12) || \ ((CHANNEL) == ADC_Channel_13) || \ ((CHANNEL) == ADC_Channel_14) || \ ((CHANNEL) == ADC_Channel_15) || \ ((CHANNEL) == ADC_Channel_16) || \ ((CHANNEL) == ADC_Channel_17) || \ ((CHANNEL) == ADC_Channel_18)) /** * @} */ /** @defgroup ADC_sampling_times * @{ */ #define ADC_SampleTime_3Cycles ((uint8_t)0x00) #define ADC_SampleTime_15Cycles ((uint8_t)0x01) #define ADC_SampleTime_28Cycles ((uint8_t)0x02) #define ADC_SampleTime_56Cycles ((uint8_t)0x03) #define ADC_SampleTime_84Cycles ((uint8_t)0x04) #define ADC_SampleTime_112Cycles ((uint8_t)0x05) #define ADC_SampleTime_144Cycles ((uint8_t)0x06) #define ADC_SampleTime_480Cycles ((uint8_t)0x07) #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \ ((TIME) == ADC_SampleTime_15Cycles) || \ ((TIME) == ADC_SampleTime_28Cycles) || \ ((TIME) == ADC_SampleTime_56Cycles) || \ ((TIME) == ADC_SampleTime_84Cycles) || \ ((TIME) == ADC_SampleTime_112Cycles) || \ ((TIME) == ADC_SampleTime_144Cycles) || \ ((TIME) == ADC_SampleTime_480Cycles)) /** * @} */ /** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion * @{ */ #define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000) #define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000) #define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000) #define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000) #define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \ ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \ ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \ ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling)) /** * @} */ /** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion * @{ */ #define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00000000) #define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00010000) #define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00020000) #define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00030000) #define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00040000) #define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00050000) #define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000) #define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000) #define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000) #define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00090000) #define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x000A0000) #define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x000B0000) #define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x000C0000) #define ADC_ExternalTrigInjecConv_T8_CC3 ((uint32_t)0x000D0000) #define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x000E0000) #define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000) #define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15)) /** * @} */ /** @defgroup ADC_injected_channel_selection * @{ */ #define ADC_InjectedChannel_1 ((uint8_t)0x14) #define ADC_InjectedChannel_2 ((uint8_t)0x18) #define ADC_InjectedChannel_3 ((uint8_t)0x1C) #define ADC_InjectedChannel_4 ((uint8_t)0x20) #define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ ((CHANNEL) == ADC_InjectedChannel_2) || \ ((CHANNEL) == ADC_InjectedChannel_3) || \ ((CHANNEL) == ADC_InjectedChannel_4)) /** * @} */ /** @defgroup ADC_analog_watchdog_selection * @{ */ #define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) #define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) #define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) #define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) #define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) #define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) #define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) #define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ ((WATCHDOG) == ADC_AnalogWatchdog_None)) /** * @} */ /** @defgroup ADC_interrupts_definition * @{ */ #define ADC_IT_EOC ((uint16_t)0x0205) #define ADC_IT_AWD ((uint16_t)0x0106) #define ADC_IT_JEOC ((uint16_t)0x0407) #define ADC_IT_OVR ((uint16_t)0x201A) #define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) /** * @} */ /** @defgroup ADC_flags_definition * @{ */ #define ADC_FLAG_AWD ((uint8_t)0x01) #define ADC_FLAG_EOC ((uint8_t)0x02) #define ADC_FLAG_JEOC ((uint8_t)0x04) #define ADC_FLAG_JSTRT ((uint8_t)0x08) #define ADC_FLAG_STRT ((uint8_t)0x10) #define ADC_FLAG_OVR ((uint8_t)0x20) #define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00)) #define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \ ((FLAG) == ADC_FLAG_EOC) || \ ((FLAG) == ADC_FLAG_JEOC) || \ ((FLAG)== ADC_FLAG_JSTRT) || \ ((FLAG) == ADC_FLAG_STRT) || \ ((FLAG)== ADC_FLAG_OVR)) /** * @} */ /** @defgroup ADC_thresholds * @{ */ #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) /** * @} */ /** @defgroup ADC_injected_offset * @{ */ #define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) /** * @} */ /** @defgroup ADC_injected_length * @{ */ #define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) /** * @} */ /** @defgroup ADC_injected_rank * @{ */ #define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) /** * @} */ /** @defgroup ADC_regular_length * @{ */ #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) /** * @} */ /** @defgroup ADC_regular_rank * @{ */ #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) /** * @} */ /** @defgroup ADC_regular_discontinuous_mode_number * @{ */ #define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the ADC configuration to the default reset state *****/ void ADC_DeInit(void); /* Initialization and Configuration functions *********************************/ void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct); void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct); void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); /* Analog Watchdog configuration functions ************************************/ void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold); void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); /* Temperature Sensor, Vrefint and VBAT management functions ******************/ void ADC_TempSensorVrefintCmd(FunctionalState NewState); void ADC_VBATCmd(FunctionalState NewState); /* Regular Channels Configuration functions ***********************************/ void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); void ADC_SoftwareStartConv(ADC_TypeDef* ADCx); FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState); void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); uint32_t ADC_GetMultiModeConversionValue(void); /* Regular Channels DMA Configuration functions *******************************/ void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState); void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState); /* Injected channels Configuration functions **********************************/ void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge); void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx); FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); /* Interrupts and flags management functions **********************************/ void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); #ifdef __cplusplus } #endif #endif /*__STM32F4xx_ADC_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_can.h ================================================ /** ****************************************************************************** * @file stm32f4xx_can.h * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file contains all the functions prototypes for the CAN firmware * library. ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_CAN_H #define __STM32F4xx_CAN_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup CAN * @{ */ /* Exported types ------------------------------------------------------------*/ #define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \ ((PERIPH) == CAN2)) /** * @brief CAN init structure definition */ typedef struct { uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. It ranges from 1 to 1024. */ uint8_t CAN_Mode; /*!< Specifies the CAN operating mode. This parameter can be a value of @ref CAN_operating_mode */ uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta the CAN hardware is allowed to lengthen or shorten a bit to perform resynchronization. This parameter can be a value of @ref CAN_synchronisation_jump_width */ uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit Segment 1. This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2. This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode. This parameter can be set either to ENABLE or DISABLE. */ FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management. This parameter can be set either to ENABLE or DISABLE. */ FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. This parameter can be set either to ENABLE or DISABLE. */ FunctionalState CAN_NART; /*!< Enable or disable the non-automatic retransmission mode. This parameter can be set either to ENABLE or DISABLE. */ FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode. This parameter can be set either to ENABLE or DISABLE. */ FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority. This parameter can be set either to ENABLE or DISABLE. */ } CAN_InitTypeDef; /** * @brief CAN filter init structure definition */ typedef struct { uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit configuration, first one for a 16-bit configuration). This parameter can be a value between 0x0000 and 0xFFFF */ uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit configuration, second one for a 16-bit configuration). This parameter can be a value between 0x0000 and 0xFFFF */ uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, according to the mode (MSBs for a 32-bit configuration, first one for a 16-bit configuration). This parameter can be a value between 0x0000 and 0xFFFF */ uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, according to the mode (LSBs for a 32-bit configuration, second one for a 16-bit configuration). This parameter can be a value between 0x0000 and 0xFFFF */ uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. This parameter can be a value of @ref CAN_filter_FIFO */ uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized. This parameter can be a value of @ref CAN_filter_mode */ uint8_t CAN_FilterScale; /*!< Specifies the filter scale. This parameter can be a value of @ref CAN_filter_scale */ FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter. This parameter can be set either to ENABLE or DISABLE. */ } CAN_FilterInitTypeDef; /** * @brief CAN Tx message structure definition */ typedef struct { uint32_t StdId; /*!< Specifies the standard identifier. This parameter can be a value between 0 to 0x7FF. */ uint32_t ExtId; /*!< Specifies the extended identifier. This parameter can be a value between 0 to 0x1FFFFFFF. */ uint8_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. This parameter can be a value of @ref CAN_identifier_type */ uint8_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. This parameter can be a value of @ref CAN_remote_transmission_request */ uint8_t DLC; /*!< Specifies the length of the frame that will be transmitted. This parameter can be a value between 0 to 8 */ uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 to 0xFF. */ } CanTxMsg; /** * @brief CAN Rx message structure definition */ typedef struct { uint32_t StdId; /*!< Specifies the standard identifier. This parameter can be a value between 0 to 0x7FF. */ uint32_t ExtId; /*!< Specifies the extended identifier. This parameter can be a value between 0 to 0x1FFFFFFF. */ uint8_t IDE; /*!< Specifies the type of identifier for the message that will be received. This parameter can be a value of @ref CAN_identifier_type */ uint8_t RTR; /*!< Specifies the type of frame for the received message. This parameter can be a value of @ref CAN_remote_transmission_request */ uint8_t DLC; /*!< Specifies the length of the frame that will be received. This parameter can be a value between 0 to 8 */ uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to 0xFF. */ uint8_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. This parameter can be a value between 0 to 0xFF */ } CanRxMsg; /* Exported constants --------------------------------------------------------*/ /** @defgroup CAN_Exported_Constants * @{ */ /** @defgroup CAN_InitStatus * @{ */ #define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */ #define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */ /* Legacy defines */ #define CANINITFAILED CAN_InitStatus_Failed #define CANINITOK CAN_InitStatus_Success /** * @} */ /** @defgroup CAN_operating_mode * @{ */ #define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */ #define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */ #define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */ #define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */ #define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \ ((MODE) == CAN_Mode_LoopBack)|| \ ((MODE) == CAN_Mode_Silent) || \ ((MODE) == CAN_Mode_Silent_LoopBack)) /** * @} */ /** * @defgroup CAN_operating_mode * @{ */ #define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */ #define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */ #define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */ #define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\ ((MODE) == CAN_OperatingMode_Normal)|| \ ((MODE) == CAN_OperatingMode_Sleep)) /** * @} */ /** * @defgroup CAN_operating_mode_status * @{ */ #define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */ #define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */ /** * @} */ /** @defgroup CAN_synchronisation_jump_width * @{ */ #define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ #define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ #define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ #define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ #define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \ ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) /** * @} */ /** @defgroup CAN_time_quantum_in_bit_segment_1 * @{ */ #define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ #define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ #define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ #define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ #define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ #define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ #define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ #define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ #define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ #define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ #define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ #define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ #define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ #define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ #define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ #define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ #define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq) /** * @} */ /** @defgroup CAN_time_quantum_in_bit_segment_2 * @{ */ #define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ #define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ #define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ #define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ #define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ #define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ #define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ #define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ #define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq) /** * @} */ /** @defgroup CAN_clock_prescaler * @{ */ #define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) /** * @} */ /** @defgroup CAN_filter_number * @{ */ #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) /** * @} */ /** @defgroup CAN_filter_mode * @{ */ #define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */ #define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */ #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \ ((MODE) == CAN_FilterMode_IdList)) /** * @} */ /** @defgroup CAN_filter_scale * @{ */ #define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */ #define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */ #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \ ((SCALE) == CAN_FilterScale_32bit)) /** * @} */ /** @defgroup CAN_filter_FIFO * @{ */ #define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ #define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \ ((FIFO) == CAN_FilterFIFO1)) /* Legacy defines */ #define CAN_FilterFIFO0 CAN_Filter_FIFO0 #define CAN_FilterFIFO1 CAN_Filter_FIFO1 /** * @} */ /** @defgroup CAN_Start_bank_filter_for_slave_CAN * @{ */ #define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27)) /** * @} */ /** @defgroup CAN_Tx * @{ */ #define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) #define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) #define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) #define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) /** * @} */ /** @defgroup CAN_identifier_type * @{ */ #define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */ #define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */ #define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \ ((IDTYPE) == CAN_Id_Extended)) /* Legacy defines */ #define CAN_ID_STD CAN_Id_Standard #define CAN_ID_EXT CAN_Id_Extended /** * @} */ /** @defgroup CAN_remote_transmission_request * @{ */ #define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */ #define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */ #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote)) /* Legacy defines */ #define CAN_RTR_DATA CAN_RTR_Data #define CAN_RTR_REMOTE CAN_RTR_Remote /** * @} */ /** @defgroup CAN_transmit_constants * @{ */ #define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */ #define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */ #define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */ #define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */ /* Legacy defines */ #define CANTXFAILED CAN_TxStatus_Failed #define CANTXOK CAN_TxStatus_Ok #define CANTXPENDING CAN_TxStatus_Pending #define CAN_NO_MB CAN_TxStatus_NoMailBox /** * @} */ /** @defgroup CAN_receive_FIFO_number_constants * @{ */ #define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ #define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ #define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) /** * @} */ /** @defgroup CAN_sleep_constants * @{ */ #define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ #define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */ /* Legacy defines */ #define CANSLEEPFAILED CAN_Sleep_Failed #define CANSLEEPOK CAN_Sleep_Ok /** * @} */ /** @defgroup CAN_wake_up_constants * @{ */ #define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ #define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ /* Legacy defines */ #define CANWAKEUPFAILED CAN_WakeUp_Failed #define CANWAKEUPOK CAN_WakeUp_Ok /** * @} */ /** * @defgroup CAN_Error_Code_constants * @{ */ #define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */ #define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */ #define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */ #define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */ #define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ #define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */ #define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */ #define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */ /** * @} */ /** @defgroup CAN_flags * @{ */ /* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() and CAN_ClearFlag() functions. */ /* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. */ /* Transmit Flags */ #define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */ #define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */ #define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */ /* Receive Flags */ #define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */ #define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */ #define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */ #define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */ #define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */ #define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */ /* Operating Mode Flags */ #define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */ #define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */ /* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. In this case the SLAK bit can be polled.*/ /* Error Flags */ #define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */ #define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */ #define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */ #define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */ #define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \ ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \ ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \ ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \ ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \ ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \ ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \ ((FLAG) == CAN_FLAG_SLAK )) #define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \ ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \ ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\ ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \ ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK)) /** * @} */ /** @defgroup CAN_interrupts * @{ */ #define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/ /* Receive Interrupts */ #define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/ #define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/ #define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/ #define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/ #define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/ #define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/ /* Operating Mode Interrupts */ #define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/ #define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/ /* Error Interrupts */ #define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/ #define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/ #define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/ #define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/ #define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/ /* Flags named as Interrupts : kept only for FW compatibility */ #define CAN_IT_RQCP0 CAN_IT_TME #define CAN_IT_RQCP1 CAN_IT_TME #define CAN_IT_RQCP2 CAN_IT_TME #define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) #define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\ ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the CAN configuration to the default reset state *****/ void CAN_DeInit(CAN_TypeDef* CANx); /* Initialization and Configuration functions *********************************/ uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); void CAN_SlaveStartBank(uint8_t CAN_BankNumber); void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState); /* CAN Frames Transmission functions ******************************************/ uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); /* CAN Frames Reception functions *********************************************/ void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); /* Operation modes functions **************************************************/ uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode); uint8_t CAN_Sleep(CAN_TypeDef* CANx); uint8_t CAN_WakeUp(CAN_TypeDef* CANx); /* CAN Bus Error management functions *****************************************/ uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx); uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx); uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx); /* Interrupts and flags management functions **********************************/ void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); #ifdef __cplusplus } #endif #endif /* __STM32F4xx_CAN_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_crc.h ================================================ /** ****************************************************************************** * @file stm32f4xx_crc.h * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file contains all the functions prototypes for the CRC firmware * library. ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_CRC_H #define __STM32F4xx_CRC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup CRC * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup CRC_Exported_Constants * @{ */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ void CRC_ResetDR(void); uint32_t CRC_CalcCRC(uint32_t Data); uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); uint32_t CRC_GetCRC(void); void CRC_SetIDRegister(uint8_t IDValue); uint8_t CRC_GetIDRegister(void); #ifdef __cplusplus } #endif #endif /* __STM32F4xx_CRC_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_cryp.h ================================================ /** ****************************************************************************** * @file stm32f4xx_cryp.h * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file contains all the functions prototypes for the Cryptographic * processor(CRYP) firmware library. ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_CRYP_H #define __STM32F4xx_CRYP_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup CRYP * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief CRYP Init structure definition */ typedef struct { uint16_t CRYP_AlgoDir; /*!< Encrypt or Decrypt. This parameter can be a value of @ref CRYP_Algorithm_Direction */ uint16_t CRYP_AlgoMode; /*!< TDES-ECB, TDES-CBC, DES-ECB, DES-CBC, AES-ECB, AES-CBC, AES-CTR, AES-Key. This parameter can be a value of @ref CRYP_Algorithm_Mode */ uint16_t CRYP_DataType; /*!< 32-bit data, 16-bit data, bit data or bit-string. This parameter can be a value of @ref CRYP_Data_Type */ uint16_t CRYP_KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit key length. This parameter can be a value of @ref CRYP_Key_Size_for_AES_only */ }CRYP_InitTypeDef; /** * @brief CRYP Key(s) structure definition */ typedef struct { uint32_t CRYP_Key0Left; /*!< Key 0 Left */ uint32_t CRYP_Key0Right; /*!< Key 0 Right */ uint32_t CRYP_Key1Left; /*!< Key 1 left */ uint32_t CRYP_Key1Right; /*!< Key 1 Right */ uint32_t CRYP_Key2Left; /*!< Key 2 left */ uint32_t CRYP_Key2Right; /*!< Key 2 Right */ uint32_t CRYP_Key3Left; /*!< Key 3 left */ uint32_t CRYP_Key3Right; /*!< Key 3 Right */ }CRYP_KeyInitTypeDef; /** * @brief CRYP Initialization Vectors (IV) structure definition */ typedef struct { uint32_t CRYP_IV0Left; /*!< Init Vector 0 Left */ uint32_t CRYP_IV0Right; /*!< Init Vector 0 Right */ uint32_t CRYP_IV1Left; /*!< Init Vector 1 left */ uint32_t CRYP_IV1Right; /*!< Init Vector 1 Right */ }CRYP_IVInitTypeDef; /** * @brief CRYP context swapping structure definition */ typedef struct { /*!< Configuration */ uint32_t CR_bits9to2; /*!< KEY */ uint32_t CRYP_IV0LR; uint32_t CRYP_IV0RR; uint32_t CRYP_IV1LR; uint32_t CRYP_IV1RR; /*!< IV */ uint32_t CRYP_K0LR; uint32_t CRYP_K0RR; uint32_t CRYP_K1LR; uint32_t CRYP_K1RR; uint32_t CRYP_K2LR; uint32_t CRYP_K2RR; uint32_t CRYP_K3LR; uint32_t CRYP_K3RR; }CRYP_Context; /* Exported constants --------------------------------------------------------*/ /** @defgroup CRYP_Exported_Constants * @{ */ /** @defgroup CRYP_Algorithm_Direction * @{ */ #define CRYP_AlgoDir_Encrypt ((uint16_t)0x0000) #define CRYP_AlgoDir_Decrypt ((uint16_t)0x0004) #define IS_CRYP_ALGODIR(ALGODIR) (((ALGODIR) == CRYP_AlgoDir_Encrypt) || \ ((ALGODIR) == CRYP_AlgoDir_Decrypt)) /** * @} */ /** @defgroup CRYP_Algorithm_Mode * @{ */ /*!< TDES Modes */ #define CRYP_AlgoMode_TDES_ECB ((uint16_t)0x0000) #define CRYP_AlgoMode_TDES_CBC ((uint16_t)0x0008) /*!< DES Modes */ #define CRYP_AlgoMode_DES_ECB ((uint16_t)0x0010) #define CRYP_AlgoMode_DES_CBC ((uint16_t)0x0018) /*!< AES Modes */ #define CRYP_AlgoMode_AES_ECB ((uint16_t)0x0020) #define CRYP_AlgoMode_AES_CBC ((uint16_t)0x0028) #define CRYP_AlgoMode_AES_CTR ((uint16_t)0x0030) #define CRYP_AlgoMode_AES_Key ((uint16_t)0x0038) #define IS_CRYP_ALGOMODE(ALGOMODE) (((ALGOMODE) == CRYP_AlgoMode_TDES_ECB) || \ ((ALGOMODE) == CRYP_AlgoMode_TDES_CBC)|| \ ((ALGOMODE) == CRYP_AlgoMode_DES_ECB)|| \ ((ALGOMODE) == CRYP_AlgoMode_DES_CBC) || \ ((ALGOMODE) == CRYP_AlgoMode_AES_ECB) || \ ((ALGOMODE) == CRYP_AlgoMode_AES_CBC) || \ ((ALGOMODE) == CRYP_AlgoMode_AES_CTR) || \ ((ALGOMODE) == CRYP_AlgoMode_AES_Key)) /** * @} */ /** @defgroup CRYP_Data_Type * @{ */ #define CRYP_DataType_32b ((uint16_t)0x0000) #define CRYP_DataType_16b ((uint16_t)0x0040) #define CRYP_DataType_8b ((uint16_t)0x0080) #define CRYP_DataType_1b ((uint16_t)0x00C0) #define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DataType_32b) || \ ((DATATYPE) == CRYP_DataType_16b)|| \ ((DATATYPE) == CRYP_DataType_8b)|| \ ((DATATYPE) == CRYP_DataType_1b)) /** * @} */ /** @defgroup CRYP_Key_Size_for_AES_only * @{ */ #define CRYP_KeySize_128b ((uint16_t)0x0000) #define CRYP_KeySize_192b ((uint16_t)0x0100) #define CRYP_KeySize_256b ((uint16_t)0x0200) #define IS_CRYP_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KeySize_128b)|| \ ((KEYSIZE) == CRYP_KeySize_192b)|| \ ((KEYSIZE) == CRYP_KeySize_256b)) /** * @} */ /** @defgroup CRYP_flags_definition * @{ */ #define CRYP_FLAG_BUSY ((uint8_t)0x10) /*!< The CRYP core is currently processing a block of data or a key preparation (for AES decryption). */ #define CRYP_FLAG_IFEM ((uint8_t)0x01) /*!< Input Fifo Empty */ #define CRYP_FLAG_IFNF ((uint8_t)0x02) /*!< Input Fifo is Not Full */ #define CRYP_FLAG_INRIS ((uint8_t)0x22) /*!< Raw interrupt pending */ #define CRYP_FLAG_OFNE ((uint8_t)0x04) /*!< Input Fifo service raw interrupt status */ #define CRYP_FLAG_OFFU ((uint8_t)0x08) /*!< Output Fifo is Full */ #define CRYP_FLAG_OUTRIS ((uint8_t)0x21) /*!< Output Fifo service raw interrupt status */ #define IS_CRYP_GET_FLAG(FLAG) (((FLAG) == CRYP_FLAG_IFEM) || \ ((FLAG) == CRYP_FLAG_IFNF) || \ ((FLAG) == CRYP_FLAG_OFNE) || \ ((FLAG) == CRYP_FLAG_OFFU) || \ ((FLAG) == CRYP_FLAG_BUSY) || \ ((FLAG) == CRYP_FLAG_OUTRIS)|| \ ((FLAG) == CRYP_FLAG_INRIS)) /** * @} */ /** @defgroup CRYP_interrupts_definition * @{ */ #define CRYP_IT_INI ((uint8_t)0x01) /*!< IN Fifo Interrupt */ #define CRYP_IT_OUTI ((uint8_t)0x02) /*!< OUT Fifo Interrupt */ #define IS_CRYP_CONFIG_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00)) #define IS_CRYP_GET_IT(IT) (((IT) == CRYP_IT_INI) || ((IT) == CRYP_IT_OUTI)) /** * @} */ /** @defgroup CRYP_Encryption_Decryption_modes_definition * @{ */ #define MODE_ENCRYPT ((uint8_t)0x01) #define MODE_DECRYPT ((uint8_t)0x00) /** * @} */ /** @defgroup CRYP_DMA_transfer_requests * @{ */ #define CRYP_DMAReq_DataIN ((uint8_t)0x01) #define CRYP_DMAReq_DataOUT ((uint8_t)0x02) #define IS_CRYP_DMAREQ(DMAREQ) ((((DMAREQ) & (uint8_t)0xFC) == 0x00) && ((DMAREQ) != 0x00)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the CRYP configuration to the default reset state ****/ void CRYP_DeInit(void); /* CRYP Initialization and Configuration functions ****************************/ void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct); void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct); void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct); void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct); void CRYP_Cmd(FunctionalState NewState); /* CRYP Data processing functions *********************************************/ void CRYP_DataIn(uint32_t Data); uint32_t CRYP_DataOut(void); void CRYP_FIFOFlush(void); /* CRYP Context swapping functions ********************************************/ ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave, CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore); /* CRYP's DMA interface function **********************************************/ void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState); /* Interrupts and flags management functions **********************************/ void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState); ITStatus CRYP_GetITStatus(uint8_t CRYP_IT); FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG); /* High Level AES functions **************************************************/ ErrorStatus CRYP_AES_ECB(uint8_t Mode, uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t Ilength, uint8_t *Output); ErrorStatus CRYP_AES_CBC(uint8_t Mode, uint8_t InitVectors[16], uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t Ilength, uint8_t *Output); ErrorStatus CRYP_AES_CTR(uint8_t Mode, uint8_t InitVectors[16], uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t Ilength, uint8_t *Output); /* High Level TDES functions **************************************************/ ErrorStatus CRYP_TDES_ECB(uint8_t Mode, uint8_t Key[24], uint8_t *Input, uint32_t Ilength, uint8_t *Output); ErrorStatus CRYP_TDES_CBC(uint8_t Mode, uint8_t Key[24], uint8_t InitVectors[8], uint8_t *Input, uint32_t Ilength, uint8_t *Output); /* High Level DES functions **************************************************/ ErrorStatus CRYP_DES_ECB(uint8_t Mode, uint8_t Key[8], uint8_t *Input, uint32_t Ilength, uint8_t *Output); ErrorStatus CRYP_DES_CBC(uint8_t Mode, uint8_t Key[8], uint8_t InitVectors[8], uint8_t *Input,uint32_t Ilength, uint8_t *Output); #ifdef __cplusplus } #endif #endif /*__STM32F4xx_CRYP_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dac.h ================================================ /** ****************************************************************************** * @file stm32f4xx_dac.h * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file contains all the functions prototypes for the DAC firmware * library. ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_DAC_H #define __STM32F4xx_DAC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup DAC * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief DAC Init structure definition */ typedef struct { uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. This parameter can be a value of @ref DAC_trigger_selection */ uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves are generated, or whether no wave is generated. This parameter can be a value of @ref DAC_wave_generation */ uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or the maximum amplitude triangle generation for the DAC channel. This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. This parameter can be a value of @ref DAC_output_buffer */ }DAC_InitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup DAC_Exported_Constants * @{ */ /** @defgroup DAC_trigger_selection * @{ */ #define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */ #define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ #define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ #define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ #define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ #define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ #define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ #define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ #define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ ((TRIGGER) == DAC_Trigger_Software)) /** * @} */ /** @defgroup DAC_wave_generation * @{ */ #define DAC_WaveGeneration_None ((uint32_t)0x00000000) #define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) #define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) #define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ ((WAVE) == DAC_WaveGeneration_Noise) || \ ((WAVE) == DAC_WaveGeneration_Triangle)) /** * @} */ /** @defgroup DAC_lfsrunmask_triangleamplitude * @{ */ #define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ #define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ #define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ #define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ #define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ #define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ #define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ #define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ #define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ #define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ #define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ #define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ #define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ #define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ ((VALUE) == DAC_TriangleAmplitude_1) || \ ((VALUE) == DAC_TriangleAmplitude_3) || \ ((VALUE) == DAC_TriangleAmplitude_7) || \ ((VALUE) == DAC_TriangleAmplitude_15) || \ ((VALUE) == DAC_TriangleAmplitude_31) || \ ((VALUE) == DAC_TriangleAmplitude_63) || \ ((VALUE) == DAC_TriangleAmplitude_127) || \ ((VALUE) == DAC_TriangleAmplitude_255) || \ ((VALUE) == DAC_TriangleAmplitude_511) || \ ((VALUE) == DAC_TriangleAmplitude_1023) || \ ((VALUE) == DAC_TriangleAmplitude_2047) || \ ((VALUE) == DAC_TriangleAmplitude_4095)) /** * @} */ /** @defgroup DAC_output_buffer * @{ */ #define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) #define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ ((STATE) == DAC_OutputBuffer_Disable)) /** * @} */ /** @defgroup DAC_Channel_selection * @{ */ #define DAC_Channel_1 ((uint32_t)0x00000000) #define DAC_Channel_2 ((uint32_t)0x00000010) #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ ((CHANNEL) == DAC_Channel_2)) /** * @} */ /** @defgroup DAC_data_alignement * @{ */ #define DAC_Align_12b_R ((uint32_t)0x00000000) #define DAC_Align_12b_L ((uint32_t)0x00000004) #define DAC_Align_8b_R ((uint32_t)0x00000008) #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ ((ALIGN) == DAC_Align_12b_L) || \ ((ALIGN) == DAC_Align_8b_R)) /** * @} */ /** @defgroup DAC_wave_generation * @{ */ #define DAC_Wave_Noise ((uint32_t)0x00000040) #define DAC_Wave_Triangle ((uint32_t)0x00000080) #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ ((WAVE) == DAC_Wave_Triangle)) /** * @} */ /** @defgroup DAC_data * @{ */ #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) /** * @} */ /** @defgroup DAC_interrupts_definition * @{ */ #define DAC_IT_DMAUDR ((uint32_t)0x00002000) #define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) /** * @} */ /** @defgroup DAC_flags_definition * @{ */ #define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) #define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the DAC configuration to the default reset state *****/ void DAC_DeInit(void); /* DAC channels configuration: trigger, output buffer, data format functions */ void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); /* DMA management functions ***************************************************/ void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); /* Interrupts and flags management functions **********************************/ void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); #ifdef __cplusplus } #endif #endif /*__STM32F4xx_DAC_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dbgmcu.h ================================================ /** ****************************************************************************** * @file stm32f4xx_dbgmcu.h * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file contains all the functions prototypes for the DBGMCU firmware library. ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_DBGMCU_H #define __STM32F4xx_DBGMCU_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup DBGMCU * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup DBGMCU_Exported_Constants * @{ */ #define DBGMCU_SLEEP ((uint32_t)0x00000001) #define DBGMCU_STOP ((uint32_t)0x00000002) #define DBGMCU_STANDBY ((uint32_t)0x00000004) #define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00)) #define DBGMCU_TIM2_STOP ((uint32_t)0x00000001) #define DBGMCU_TIM3_STOP ((uint32_t)0x00000002) #define DBGMCU_TIM4_STOP ((uint32_t)0x00000004) #define DBGMCU_TIM5_STOP ((uint32_t)0x00000008) #define DBGMCU_TIM6_STOP ((uint32_t)0x00000010) #define DBGMCU_TIM7_STOP ((uint32_t)0x00000020) #define DBGMCU_TIM12_STOP ((uint32_t)0x00000040) #define DBGMCU_TIM13_STOP ((uint32_t)0x00000080) #define DBGMCU_TIM14_STOP ((uint32_t)0x00000100) #define DBGMCU_RTC_STOP ((uint32_t)0x00000400) #define DBGMCU_WWDG_STOP ((uint32_t)0x00000800) #define DBGMCU_IWDG_STOP ((uint32_t)0x00001000) #define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) #define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) #define DBGMCU_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000) #define DBGMCU_CAN1_STOP ((uint32_t)0x02000000) #define DBGMCU_CAN2_STOP ((uint32_t)0x04000000) #define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xF91FE200) == 0x00) && ((PERIPH) != 0x00)) #define DBGMCU_TIM1_STOP ((uint32_t)0x00000001) #define DBGMCU_TIM8_STOP ((uint32_t)0x00000002) #define DBGMCU_TIM9_STOP ((uint32_t)0x00010000) #define DBGMCU_TIM10_STOP ((uint32_t)0x00020000) #define DBGMCU_TIM11_STOP ((uint32_t)0x00040000) #define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8FFFC) == 0x00) && ((PERIPH) != 0x00)) /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ uint32_t DBGMCU_GetREVID(void); uint32_t DBGMCU_GetDEVID(void); void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); #ifdef __cplusplus } #endif #endif /* __STM32F4xx_DBGMCU_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dcmi.h ================================================ /** ****************************************************************************** * @file stm32f4xx_dcmi.h * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file contains all the functions prototypes for the DCMI firmware library. ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_DCMI_H #define __STM32F4xx_DCMI_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup DCMI * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief DCMI Init structure definition */ typedef struct { uint16_t DCMI_CaptureMode; /*!< Specifies the Capture Mode: Continuous or Snapshot. This parameter can be a value of @ref DCMI_Capture_Mode */ uint16_t DCMI_SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded. This parameter can be a value of @ref DCMI_Synchronization_Mode */ uint16_t DCMI_PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising. This parameter can be a value of @ref DCMI_PIXCK_Polarity */ uint16_t DCMI_VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low. This parameter can be a value of @ref DCMI_VSYNC_Polarity */ uint16_t DCMI_HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low. This parameter can be a value of @ref DCMI_HSYNC_Polarity */ uint16_t DCMI_CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4. This parameter can be a value of @ref DCMI_Capture_Rate */ uint16_t DCMI_ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit. This parameter can be a value of @ref DCMI_Extended_Data_Mode */ } DCMI_InitTypeDef; /** * @brief DCMI CROP Init structure definition */ typedef struct { uint16_t DCMI_VerticalStartLine; /*!< Specifies the Vertical start line count from which the image capture will start. This parameter can be a value between 0x00 and 0x1FFF */ uint16_t DCMI_HorizontalOffsetCount; /*!< Specifies the number of pixel clocks to count before starting a capture. This parameter can be a value between 0x00 and 0x3FFF */ uint16_t DCMI_VerticalLineCount; /*!< Specifies the number of lines to be captured from the starting point. This parameter can be a value between 0x00 and 0x3FFF */ uint16_t DCMI_CaptureCount; /*!< Specifies the number of pixel clocks to be captured from the starting point on the same line. This parameter can be a value between 0x00 and 0x3FFF */ } DCMI_CROPInitTypeDef; /** * @brief DCMI Embedded Synchronisation CODE Init structure definition */ typedef struct { uint8_t DCMI_FrameStartCode; /*!< Specifies the code of the frame start delimiter. */ uint8_t DCMI_LineStartCode; /*!< Specifies the code of the line start delimiter. */ uint8_t DCMI_LineEndCode; /*!< Specifies the code of the line end delimiter. */ uint8_t DCMI_FrameEndCode; /*!< Specifies the code of the frame end delimiter. */ } DCMI_CodesInitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup DCMI_Exported_Constants * @{ */ /** @defgroup DCMI_Capture_Mode * @{ */ #define DCMI_CaptureMode_Continuous ((uint16_t)0x0000) /*!< The received data are transferred continuously into the destination memory through the DMA */ #define DCMI_CaptureMode_SnapShot ((uint16_t)0x0002) /*!< Once activated, the interface waits for the start of frame and then transfers a single frame through the DMA */ #define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_CaptureMode_Continuous) || \ ((MODE) == DCMI_CaptureMode_SnapShot)) /** * @} */ /** @defgroup DCMI_Synchronization_Mode * @{ */ #define DCMI_SynchroMode_Hardware ((uint16_t)0x0000) /*!< Hardware synchronization data capture (frame/line start/stop) is synchronized with the HSYNC/VSYNC signals */ #define DCMI_SynchroMode_Embedded ((uint16_t)0x0010) /*!< Embedded synchronization data capture is synchronized with synchronization codes embedded in the data flow */ #define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SynchroMode_Hardware) || \ ((MODE) == DCMI_SynchroMode_Embedded)) /** * @} */ /** @defgroup DCMI_PIXCK_Polarity * @{ */ #define DCMI_PCKPolarity_Falling ((uint16_t)0x0000) /*!< Pixel clock active on Falling edge */ #define DCMI_PCKPolarity_Rising ((uint16_t)0x0020) /*!< Pixel clock active on Rising edge */ #define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPolarity_Falling) || \ ((POLARITY) == DCMI_PCKPolarity_Rising)) /** * @} */ /** @defgroup DCMI_VSYNC_Polarity * @{ */ #define DCMI_VSPolarity_Low ((uint16_t)0x0000) /*!< Vertical synchronization active Low */ #define DCMI_VSPolarity_High ((uint16_t)0x0080) /*!< Vertical synchronization active High */ #define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPolarity_Low) || \ ((POLARITY) == DCMI_VSPolarity_High)) /** * @} */ /** @defgroup DCMI_HSYNC_Polarity * @{ */ #define DCMI_HSPolarity_Low ((uint16_t)0x0000) /*!< Horizontal synchronization active Low */ #define DCMI_HSPolarity_High ((uint16_t)0x0040) /*!< Horizontal synchronization active High */ #define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPolarity_Low) || \ ((POLARITY) == DCMI_HSPolarity_High)) /** * @} */ /** @defgroup DCMI_Capture_Rate * @{ */ #define DCMI_CaptureRate_All_Frame ((uint16_t)0x0000) /*!< All frames are captured */ #define DCMI_CaptureRate_1of2_Frame ((uint16_t)0x0100) /*!< Every alternate frame captured */ #define DCMI_CaptureRate_1of4_Frame ((uint16_t)0x0200) /*!< One frame in 4 frames captured */ #define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CaptureRate_All_Frame) || \ ((RATE) == DCMI_CaptureRate_1of2_Frame) ||\ ((RATE) == DCMI_CaptureRate_1of4_Frame)) /** * @} */ /** @defgroup DCMI_Extended_Data_Mode * @{ */ #define DCMI_ExtendedDataMode_8b ((uint16_t)0x0000) /*!< Interface captures 8-bit data on every pixel clock */ #define DCMI_ExtendedDataMode_10b ((uint16_t)0x0400) /*!< Interface captures 10-bit data on every pixel clock */ #define DCMI_ExtendedDataMode_12b ((uint16_t)0x0800) /*!< Interface captures 12-bit data on every pixel clock */ #define DCMI_ExtendedDataMode_14b ((uint16_t)0x0C00) /*!< Interface captures 14-bit data on every pixel clock */ #define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_ExtendedDataMode_8b) || \ ((DATA) == DCMI_ExtendedDataMode_10b) ||\ ((DATA) == DCMI_ExtendedDataMode_12b) ||\ ((DATA) == DCMI_ExtendedDataMode_14b)) /** * @} */ /** @defgroup DCMI_interrupt_sources * @{ */ #define DCMI_IT_FRAME ((uint16_t)0x0001) #define DCMI_IT_OVF ((uint16_t)0x0002) #define DCMI_IT_ERR ((uint16_t)0x0004) #define DCMI_IT_VSYNC ((uint16_t)0x0008) #define DCMI_IT_LINE ((uint16_t)0x0010) #define IS_DCMI_CONFIG_IT(IT) ((((IT) & (uint16_t)0xFFE0) == 0x0000) && ((IT) != 0x0000)) #define IS_DCMI_GET_IT(IT) (((IT) == DCMI_IT_FRAME) || \ ((IT) == DCMI_IT_OVF) || \ ((IT) == DCMI_IT_ERR) || \ ((IT) == DCMI_IT_VSYNC) || \ ((IT) == DCMI_IT_LINE)) /** * @} */ /** @defgroup DCMI_Flags * @{ */ /** * @brief DCMI SR register */ #define DCMI_FLAG_HSYNC ((uint16_t)0x2001) #define DCMI_FLAG_VSYNC ((uint16_t)0x2002) #define DCMI_FLAG_FNE ((uint16_t)0x2004) /** * @brief DCMI RISR register */ #define DCMI_FLAG_FRAMERI ((uint16_t)0x0001) #define DCMI_FLAG_OVFRI ((uint16_t)0x0002) #define DCMI_FLAG_ERRRI ((uint16_t)0x0004) #define DCMI_FLAG_VSYNCRI ((uint16_t)0x0008) #define DCMI_FLAG_LINERI ((uint16_t)0x0010) /** * @brief DCMI MISR register */ #define DCMI_FLAG_FRAMEMI ((uint16_t)0x1001) #define DCMI_FLAG_OVFMI ((uint16_t)0x1002) #define DCMI_FLAG_ERRMI ((uint16_t)0x1004) #define DCMI_FLAG_VSYNCMI ((uint16_t)0x1008) #define DCMI_FLAG_LINEMI ((uint16_t)0x1010) #define IS_DCMI_GET_FLAG(FLAG) (((FLAG) == DCMI_FLAG_HSYNC) || \ ((FLAG) == DCMI_FLAG_VSYNC) || \ ((FLAG) == DCMI_FLAG_FNE) || \ ((FLAG) == DCMI_FLAG_FRAMERI) || \ ((FLAG) == DCMI_FLAG_OVFRI) || \ ((FLAG) == DCMI_FLAG_ERRRI) || \ ((FLAG) == DCMI_FLAG_VSYNCRI) || \ ((FLAG) == DCMI_FLAG_LINERI) || \ ((FLAG) == DCMI_FLAG_FRAMEMI) || \ ((FLAG) == DCMI_FLAG_OVFMI) || \ ((FLAG) == DCMI_FLAG_ERRMI) || \ ((FLAG) == DCMI_FLAG_VSYNCMI) || \ ((FLAG) == DCMI_FLAG_LINEMI)) #define IS_DCMI_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFE0) == 0x0000) && ((FLAG) != 0x0000)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the DCMI configuration to the default reset state ****/ void DCMI_DeInit(void); /* Initialization and Configuration functions *********************************/ void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct); void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct); void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct); void DCMI_CROPCmd(FunctionalState NewState); void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct); void DCMI_JPEGCmd(FunctionalState NewState); /* Image capture functions ****************************************************/ void DCMI_Cmd(FunctionalState NewState); void DCMI_CaptureCmd(FunctionalState NewState); uint32_t DCMI_ReadData(void); /* Interrupts and flags management functions **********************************/ void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState); FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG); void DCMI_ClearFlag(uint16_t DCMI_FLAG); ITStatus DCMI_GetITStatus(uint16_t DCMI_IT); void DCMI_ClearITPendingBit(uint16_t DCMI_IT); #ifdef __cplusplus } #endif #endif /*__STM32F4xx_DCMI_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma.h ================================================ /** ****************************************************************************** * @file stm32f4xx_dma.h * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file contains all the functions prototypes for the DMA firmware * library. ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_DMA_H #define __STM32F4xx_DMA_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup DMA * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief DMA Init structure definition */ typedef struct { uint32_t DMA_Channel; /*!< Specifies the channel used for the specified stream. This parameter can be a value of @ref DMA_channel */ uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Streamx. */ uint32_t DMA_Memory0BaseAddr; /*!< Specifies the memory 0 base address for DMAy Streamx. This memory is the default memory used when double buffer mode is not enabled. */ uint32_t DMA_DIR; /*!< Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. This parameter can be a value of @ref DMA_data_transfer_direction */ uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Stream. The data unit is equal to the configuration set in DMA_PeripheralDataSize or DMA_MemoryDataSize members depending in the transfer direction. */ uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register should be incremented or not. This parameter can be a value of @ref DMA_peripheral_incremented_mode */ uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register should be incremented or not. This parameter can be a value of @ref DMA_memory_incremented_mode */ uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. This parameter can be a value of @ref DMA_peripheral_data_size */ uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. This parameter can be a value of @ref DMA_memory_data_size */ uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Streamx. This parameter can be a value of @ref DMA_circular_normal_mode @note The circular buffer mode cannot be used if the memory-to-memory data transfer is configured on the selected Stream */ uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Streamx. This parameter can be a value of @ref DMA_priority_level */ uint32_t DMA_FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified Stream. This parameter can be a value of @ref DMA_fifo_direct_mode @note The Direct mode (FIFO mode disabled) cannot be used if the memory-to-memory data transfer is configured on the selected Stream */ uint32_t DMA_FIFOThreshold; /*!< Specifies the FIFO threshold level. This parameter can be a value of @ref DMA_fifo_threshold_level */ uint32_t DMA_MemoryBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. It specifies the amount of data to be transferred in a single non interruptable transaction. This parameter can be a value of @ref DMA_memory_burst @note The burst mode is possible only if the address Increment mode is enabled. */ uint32_t DMA_PeripheralBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. It specifies the amount of data to be transferred in a single non interruptable transaction. This parameter can be a value of @ref DMA_peripheral_burst @note The burst mode is possible only if the address Increment mode is enabled. */ }DMA_InitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup DMA_Exported_Constants * @{ */ #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \ ((PERIPH) == DMA1_Stream1) || \ ((PERIPH) == DMA1_Stream2) || \ ((PERIPH) == DMA1_Stream3) || \ ((PERIPH) == DMA1_Stream4) || \ ((PERIPH) == DMA1_Stream5) || \ ((PERIPH) == DMA1_Stream6) || \ ((PERIPH) == DMA1_Stream7) || \ ((PERIPH) == DMA2_Stream0) || \ ((PERIPH) == DMA2_Stream1) || \ ((PERIPH) == DMA2_Stream2) || \ ((PERIPH) == DMA2_Stream3) || \ ((PERIPH) == DMA2_Stream4) || \ ((PERIPH) == DMA2_Stream5) || \ ((PERIPH) == DMA2_Stream6) || \ ((PERIPH) == DMA2_Stream7)) #define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1) || \ ((CONTROLLER) == DMA2)) /** @defgroup DMA_channel * @{ */ #define DMA_Channel_0 ((uint32_t)0x00000000) #define DMA_Channel_1 ((uint32_t)0x02000000) #define DMA_Channel_2 ((uint32_t)0x04000000) #define DMA_Channel_3 ((uint32_t)0x06000000) #define DMA_Channel_4 ((uint32_t)0x08000000) #define DMA_Channel_5 ((uint32_t)0x0A000000) #define DMA_Channel_6 ((uint32_t)0x0C000000) #define DMA_Channel_7 ((uint32_t)0x0E000000) #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \ ((CHANNEL) == DMA_Channel_1) || \ ((CHANNEL) == DMA_Channel_2) || \ ((CHANNEL) == DMA_Channel_3) || \ ((CHANNEL) == DMA_Channel_4) || \ ((CHANNEL) == DMA_Channel_5) || \ ((CHANNEL) == DMA_Channel_6) || \ ((CHANNEL) == DMA_Channel_7)) /** * @} */ /** @defgroup DMA_data_transfer_direction * @{ */ #define DMA_DIR_PeripheralToMemory ((uint32_t)0x00000000) #define DMA_DIR_MemoryToPeripheral ((uint32_t)0x00000040) #define DMA_DIR_MemoryToMemory ((uint32_t)0x00000080) #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \ ((DIRECTION) == DMA_DIR_MemoryToPeripheral) || \ ((DIRECTION) == DMA_DIR_MemoryToMemory)) /** * @} */ /** @defgroup DMA_data_buffer_size * @{ */ #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) /** * @} */ /** @defgroup DMA_peripheral_incremented_mode * @{ */ #define DMA_PeripheralInc_Enable ((uint32_t)0x00000200) #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ ((STATE) == DMA_PeripheralInc_Disable)) /** * @} */ /** @defgroup DMA_memory_incremented_mode * @{ */ #define DMA_MemoryInc_Enable ((uint32_t)0x00000400) #define DMA_MemoryInc_Disable ((uint32_t)0x00000000) #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ ((STATE) == DMA_MemoryInc_Disable)) /** * @} */ /** @defgroup DMA_peripheral_data_size * @{ */ #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) #define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000800) #define DMA_PeripheralDataSize_Word ((uint32_t)0x00001000) #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ ((SIZE) == DMA_PeripheralDataSize_Word)) /** * @} */ /** @defgroup DMA_memory_data_size * @{ */ #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) #define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00002000) #define DMA_MemoryDataSize_Word ((uint32_t)0x00004000) #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ ((SIZE) == DMA_MemoryDataSize_Word )) /** * @} */ /** @defgroup DMA_circular_normal_mode * @{ */ #define DMA_Mode_Normal ((uint32_t)0x00000000) #define DMA_Mode_Circular ((uint32_t)0x00000100) #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal ) || \ ((MODE) == DMA_Mode_Circular)) /** * @} */ /** @defgroup DMA_priority_level * @{ */ #define DMA_Priority_Low ((uint32_t)0x00000000) #define DMA_Priority_Medium ((uint32_t)0x00010000) #define DMA_Priority_High ((uint32_t)0x00020000) #define DMA_Priority_VeryHigh ((uint32_t)0x00030000) #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_Low ) || \ ((PRIORITY) == DMA_Priority_Medium) || \ ((PRIORITY) == DMA_Priority_High) || \ ((PRIORITY) == DMA_Priority_VeryHigh)) /** * @} */ /** @defgroup DMA_fifo_direct_mode * @{ */ #define DMA_FIFOMode_Disable ((uint32_t)0x00000000) #define DMA_FIFOMode_Enable ((uint32_t)0x00000004) #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \ ((STATE) == DMA_FIFOMode_Enable)) /** * @} */ /** @defgroup DMA_fifo_threshold_level * @{ */ #define DMA_FIFOThreshold_1QuarterFull ((uint32_t)0x00000000) #define DMA_FIFOThreshold_HalfFull ((uint32_t)0x00000001) #define DMA_FIFOThreshold_3QuartersFull ((uint32_t)0x00000002) #define DMA_FIFOThreshold_Full ((uint32_t)0x00000003) #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \ ((THRESHOLD) == DMA_FIFOThreshold_HalfFull) || \ ((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \ ((THRESHOLD) == DMA_FIFOThreshold_Full)) /** * @} */ /** @defgroup DMA_memory_burst * @{ */ #define DMA_MemoryBurst_Single ((uint32_t)0x00000000) #define DMA_MemoryBurst_INC4 ((uint32_t)0x00800000) #define DMA_MemoryBurst_INC8 ((uint32_t)0x01000000) #define DMA_MemoryBurst_INC16 ((uint32_t)0x01800000) #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MemoryBurst_Single) || \ ((BURST) == DMA_MemoryBurst_INC4) || \ ((BURST) == DMA_MemoryBurst_INC8) || \ ((BURST) == DMA_MemoryBurst_INC16)) /** * @} */ /** @defgroup DMA_peripheral_burst * @{ */ #define DMA_PeripheralBurst_Single ((uint32_t)0x00000000) #define DMA_PeripheralBurst_INC4 ((uint32_t)0x00200000) #define DMA_PeripheralBurst_INC8 ((uint32_t)0x00400000) #define DMA_PeripheralBurst_INC16 ((uint32_t)0x00600000) #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \ ((BURST) == DMA_PeripheralBurst_INC4) || \ ((BURST) == DMA_PeripheralBurst_INC8) || \ ((BURST) == DMA_PeripheralBurst_INC16)) /** * @} */ /** @defgroup DMA_fifo_status_level * @{ */ #define DMA_FIFOStatus_Less1QuarterFull ((uint32_t)0x00000000 << 3) #define DMA_FIFOStatus_1QuarterFull ((uint32_t)0x00000001 << 3) #define DMA_FIFOStatus_HalfFull ((uint32_t)0x00000002 << 3) #define DMA_FIFOStatus_3QuartersFull ((uint32_t)0x00000003 << 3) #define DMA_FIFOStatus_Empty ((uint32_t)0x00000004 << 3) #define DMA_FIFOStatus_Full ((uint32_t)0x00000005 << 3) #define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \ ((STATUS) == DMA_FIFOStatus_HalfFull) || \ ((STATUS) == DMA_FIFOStatus_1QuarterFull) || \ ((STATUS) == DMA_FIFOStatus_3QuartersFull) || \ ((STATUS) == DMA_FIFOStatus_Full) || \ ((STATUS) == DMA_FIFOStatus_Empty)) /** * @} */ /** @defgroup DMA_flags_definition * @{ */ #define DMA_FLAG_FEIF0 ((uint32_t)0x10800001) #define DMA_FLAG_DMEIF0 ((uint32_t)0x10800004) #define DMA_FLAG_TEIF0 ((uint32_t)0x10000008) #define DMA_FLAG_HTIF0 ((uint32_t)0x10000010) #define DMA_FLAG_TCIF0 ((uint32_t)0x10000020) #define DMA_FLAG_FEIF1 ((uint32_t)0x10000040) #define DMA_FLAG_DMEIF1 ((uint32_t)0x10000100) #define DMA_FLAG_TEIF1 ((uint32_t)0x10000200) #define DMA_FLAG_HTIF1 ((uint32_t)0x10000400) #define DMA_FLAG_TCIF1 ((uint32_t)0x10000800) #define DMA_FLAG_FEIF2 ((uint32_t)0x10010000) #define DMA_FLAG_DMEIF2 ((uint32_t)0x10040000) #define DMA_FLAG_TEIF2 ((uint32_t)0x10080000) #define DMA_FLAG_HTIF2 ((uint32_t)0x10100000) #define DMA_FLAG_TCIF2 ((uint32_t)0x10200000) #define DMA_FLAG_FEIF3 ((uint32_t)0x10400000) #define DMA_FLAG_DMEIF3 ((uint32_t)0x11000000) #define DMA_FLAG_TEIF3 ((uint32_t)0x12000000) #define DMA_FLAG_HTIF3 ((uint32_t)0x14000000) #define DMA_FLAG_TCIF3 ((uint32_t)0x18000000) #define DMA_FLAG_FEIF4 ((uint32_t)0x20000001) #define DMA_FLAG_DMEIF4 ((uint32_t)0x20000004) #define DMA_FLAG_TEIF4 ((uint32_t)0x20000008) #define DMA_FLAG_HTIF4 ((uint32_t)0x20000010) #define DMA_FLAG_TCIF4 ((uint32_t)0x20000020) #define DMA_FLAG_FEIF5 ((uint32_t)0x20000040) #define DMA_FLAG_DMEIF5 ((uint32_t)0x20000100) #define DMA_FLAG_TEIF5 ((uint32_t)0x20000200) #define DMA_FLAG_HTIF5 ((uint32_t)0x20000400) #define DMA_FLAG_TCIF5 ((uint32_t)0x20000800) #define DMA_FLAG_FEIF6 ((uint32_t)0x20010000) #define DMA_FLAG_DMEIF6 ((uint32_t)0x20040000) #define DMA_FLAG_TEIF6 ((uint32_t)0x20080000) #define DMA_FLAG_HTIF6 ((uint32_t)0x20100000) #define DMA_FLAG_TCIF6 ((uint32_t)0x20200000) #define DMA_FLAG_FEIF7 ((uint32_t)0x20400000) #define DMA_FLAG_DMEIF7 ((uint32_t)0x21000000) #define DMA_FLAG_TEIF7 ((uint32_t)0x22000000) #define DMA_FLAG_HTIF7 ((uint32_t)0x24000000) #define DMA_FLAG_TCIF7 ((uint32_t)0x28000000) #define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \ (((FLAG) & 0xC082F082) == 0x00) && ((FLAG) != 0x00)) #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \ ((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \ ((FLAG) == DMA_FLAG_FEIF0) || ((FLAG) == DMA_FLAG_TCIF1) || \ ((FLAG) == DMA_FLAG_HTIF1) || ((FLAG) == DMA_FLAG_TEIF1) || \ ((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1) || \ ((FLAG) == DMA_FLAG_TCIF2) || ((FLAG) == DMA_FLAG_HTIF2) || \ ((FLAG) == DMA_FLAG_TEIF2) || ((FLAG) == DMA_FLAG_DMEIF2) || \ ((FLAG) == DMA_FLAG_FEIF2) || ((FLAG) == DMA_FLAG_TCIF3) || \ ((FLAG) == DMA_FLAG_HTIF3) || ((FLAG) == DMA_FLAG_TEIF3) || \ ((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3) || \ ((FLAG) == DMA_FLAG_TCIF4) || ((FLAG) == DMA_FLAG_HTIF4) || \ ((FLAG) == DMA_FLAG_TEIF4) || ((FLAG) == DMA_FLAG_DMEIF4) || \ ((FLAG) == DMA_FLAG_FEIF4) || ((FLAG) == DMA_FLAG_TCIF5) || \ ((FLAG) == DMA_FLAG_HTIF5) || ((FLAG) == DMA_FLAG_TEIF5) || \ ((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5) || \ ((FLAG) == DMA_FLAG_TCIF6) || ((FLAG) == DMA_FLAG_HTIF6) || \ ((FLAG) == DMA_FLAG_TEIF6) || ((FLAG) == DMA_FLAG_DMEIF6) || \ ((FLAG) == DMA_FLAG_FEIF6) || ((FLAG) == DMA_FLAG_TCIF7) || \ ((FLAG) == DMA_FLAG_HTIF7) || ((FLAG) == DMA_FLAG_TEIF7) || \ ((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7)) /** * @} */ /** @defgroup DMA_interrupt_enable_definitions * @{ */ #define DMA_IT_TC ((uint32_t)0x00000010) #define DMA_IT_HT ((uint32_t)0x00000008) #define DMA_IT_TE ((uint32_t)0x00000004) #define DMA_IT_DME ((uint32_t)0x00000002) #define DMA_IT_FE ((uint32_t)0x00000080) #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00)) /** * @} */ /** @defgroup DMA_interrupts_definitions * @{ */ #define DMA_IT_FEIF0 ((uint32_t)0x90000001) #define DMA_IT_DMEIF0 ((uint32_t)0x10001004) #define DMA_IT_TEIF0 ((uint32_t)0x10002008) #define DMA_IT_HTIF0 ((uint32_t)0x10004010) #define DMA_IT_TCIF0 ((uint32_t)0x10008020) #define DMA_IT_FEIF1 ((uint32_t)0x90000040) #define DMA_IT_DMEIF1 ((uint32_t)0x10001100) #define DMA_IT_TEIF1 ((uint32_t)0x10002200) #define DMA_IT_HTIF1 ((uint32_t)0x10004400) #define DMA_IT_TCIF1 ((uint32_t)0x10008800) #define DMA_IT_FEIF2 ((uint32_t)0x90010000) #define DMA_IT_DMEIF2 ((uint32_t)0x10041000) #define DMA_IT_TEIF2 ((uint32_t)0x10082000) #define DMA_IT_HTIF2 ((uint32_t)0x10104000) #define DMA_IT_TCIF2 ((uint32_t)0x10208000) #define DMA_IT_FEIF3 ((uint32_t)0x90400000) #define DMA_IT_DMEIF3 ((uint32_t)0x11001000) #define DMA_IT_TEIF3 ((uint32_t)0x12002000) #define DMA_IT_HTIF3 ((uint32_t)0x14004000) #define DMA_IT_TCIF3 ((uint32_t)0x18008000) #define DMA_IT_FEIF4 ((uint32_t)0xA0000001) #define DMA_IT_DMEIF4 ((uint32_t)0x20001004) #define DMA_IT_TEIF4 ((uint32_t)0x20002008) #define DMA_IT_HTIF4 ((uint32_t)0x20004010) #define DMA_IT_TCIF4 ((uint32_t)0x20008020) #define DMA_IT_FEIF5 ((uint32_t)0xA0000040) #define DMA_IT_DMEIF5 ((uint32_t)0x20001100) #define DMA_IT_TEIF5 ((uint32_t)0x20002200) #define DMA_IT_HTIF5 ((uint32_t)0x20004400) #define DMA_IT_TCIF5 ((uint32_t)0x20008800) #define DMA_IT_FEIF6 ((uint32_t)0xA0010000) #define DMA_IT_DMEIF6 ((uint32_t)0x20041000) #define DMA_IT_TEIF6 ((uint32_t)0x20082000) #define DMA_IT_HTIF6 ((uint32_t)0x20104000) #define DMA_IT_TCIF6 ((uint32_t)0x20208000) #define DMA_IT_FEIF7 ((uint32_t)0xA0400000) #define DMA_IT_DMEIF7 ((uint32_t)0x21001000) #define DMA_IT_TEIF7 ((uint32_t)0x22002000) #define DMA_IT_HTIF7 ((uint32_t)0x24004000) #define DMA_IT_TCIF7 ((uint32_t)0x28008000) #define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \ (((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \ (((IT) & 0x40820082) == 0x00)) #define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0) || \ ((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \ ((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1) || \ ((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1) || \ ((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1) || \ ((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2) || \ ((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \ ((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3) || \ ((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3) || \ ((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3) || \ ((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4) || \ ((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \ ((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5) || \ ((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5) || \ ((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5) || \ ((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6) || \ ((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \ ((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7) || \ ((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7) || \ ((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7)) /** * @} */ /** @defgroup DMA_peripheral_increment_offset * @{ */ #define DMA_PINCOS_Psize ((uint32_t)0x00000000) #define DMA_PINCOS_WordAligned ((uint32_t)0x00008000) #define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \ ((SIZE) == DMA_PINCOS_WordAligned)) /** * @} */ /** @defgroup DMA_flow_controller_definitions * @{ */ #define DMA_FlowCtrl_Memory ((uint32_t)0x00000000) #define DMA_FlowCtrl_Peripheral ((uint32_t)0x00000020) #define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \ ((CTRL) == DMA_FlowCtrl_Peripheral)) /** * @} */ /** @defgroup DMA_memory_targets_definitions * @{ */ #define DMA_Memory_0 ((uint32_t)0x00000000) #define DMA_Memory_1 ((uint32_t)0x00080000) #define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the DMA configuration to the default reset state *****/ void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx); /* Initialization and Configuration functions *********************************/ void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct); void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); /* Optional Configuration functions *******************************************/ void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos); void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl); /* Data Counter functions *****************************************************/ void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter); uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx); /* Double Buffer mode functions ***********************************************/ void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr, uint32_t DMA_CurrentMemory); void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr, uint32_t DMA_MemoryTarget); uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx); /* Interrupts and flags management functions **********************************/ FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx); uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx); FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState); ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); #ifdef __cplusplus } #endif #endif /*__STM32F4xx_DMA_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_exti.h ================================================ /** ****************************************************************************** * @file stm32f4xx_exti.h * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file contains all the functions prototypes for the EXTI firmware * library. ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_EXTI_H #define __STM32F4xx_EXTI_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup EXTI * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief EXTI mode enumeration */ typedef enum { EXTI_Mode_Interrupt = 0x00, EXTI_Mode_Event = 0x04 }EXTIMode_TypeDef; #define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) /** * @brief EXTI Trigger enumeration */ typedef enum { EXTI_Trigger_Rising = 0x08, EXTI_Trigger_Falling = 0x0C, EXTI_Trigger_Rising_Falling = 0x10 }EXTITrigger_TypeDef; #define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ ((TRIGGER) == EXTI_Trigger_Falling) || \ ((TRIGGER) == EXTI_Trigger_Rising_Falling)) /** * @brief EXTI Init Structure definition */ typedef struct { uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. This parameter can be any combination value of @ref EXTI_Lines */ EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. This parameter can be a value of @ref EXTIMode_TypeDef */ EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. This parameter can be a value of @ref EXTITrigger_TypeDef */ FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. This parameter can be set either to ENABLE or DISABLE */ }EXTI_InitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup EXTI_Exported_Constants * @{ */ /** @defgroup EXTI_Lines * @{ */ #define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ #define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ #define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ #define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ #define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ #define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ #define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ #define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ #define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ #define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ #define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ #define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ #define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ #define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ #define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ #define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ #define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ #define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ #define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */ #define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ #define EXTI_Line20 ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */ #define EXTI_Line21 ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ #define EXTI_Line22 ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to the RTC Wakeup event */ #define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00)) #define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \ ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) ||\ ((LINE) == EXTI_Line22)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the EXTI configuration to the default reset state *****/ void EXTI_DeInit(void); /* Initialization and Configuration functions *********************************/ void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); /* Interrupts and flags management functions **********************************/ FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); void EXTI_ClearFlag(uint32_t EXTI_Line); ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); void EXTI_ClearITPendingBit(uint32_t EXTI_Line); #ifdef __cplusplus } #endif #endif /* __STM32F4xx_EXTI_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash.h ================================================ /** ****************************************************************************** * @file stm32f4xx_flash.h * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file contains all the functions prototypes for the FLASH * firmware library. ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_FLASH_H #define __STM32F4xx_FLASH_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup FLASH * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief FLASH Status */ typedef enum { FLASH_BUSY = 1, FLASH_ERROR_PGS, FLASH_ERROR_PGP, FLASH_ERROR_PGA, FLASH_ERROR_WRP, FLASH_ERROR_PROGRAM, FLASH_ERROR_OPERATION, FLASH_COMPLETE }FLASH_Status; /* Exported constants --------------------------------------------------------*/ /** @defgroup FLASH_Exported_Constants * @{ */ /** @defgroup Flash_Latency * @{ */ #define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */ #define FLASH_Latency_1 ((uint8_t)0x0001) /*!< FLASH One Latency cycle */ #define FLASH_Latency_2 ((uint8_t)0x0002) /*!< FLASH Two Latency cycles */ #define FLASH_Latency_3 ((uint8_t)0x0003) /*!< FLASH Three Latency cycles */ #define FLASH_Latency_4 ((uint8_t)0x0004) /*!< FLASH Four Latency cycles */ #define FLASH_Latency_5 ((uint8_t)0x0005) /*!< FLASH Five Latency cycles */ #define FLASH_Latency_6 ((uint8_t)0x0006) /*!< FLASH Six Latency cycles */ #define FLASH_Latency_7 ((uint8_t)0x0007) /*!< FLASH Seven Latency cycles */ #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ ((LATENCY) == FLASH_Latency_1) || \ ((LATENCY) == FLASH_Latency_2) || \ ((LATENCY) == FLASH_Latency_3) || \ ((LATENCY) == FLASH_Latency_4) || \ ((LATENCY) == FLASH_Latency_5) || \ ((LATENCY) == FLASH_Latency_6) || \ ((LATENCY) == FLASH_Latency_7)) /** * @} */ /** @defgroup FLASH_Voltage_Range * @{ */ #define VoltageRange_1 ((uint8_t)0x00) /*!< Device operating range: 1.8V to 2.1V */ #define VoltageRange_2 ((uint8_t)0x01) /*!= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) ||\ (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F))) /** * @} */ /** @defgroup Option_Bytes_Write_Protection * @{ */ #define OB_WRP_Sector_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */ #define OB_WRP_Sector_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */ #define OB_WRP_Sector_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */ #define OB_WRP_Sector_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */ #define OB_WRP_Sector_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */ #define OB_WRP_Sector_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */ #define OB_WRP_Sector_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */ #define OB_WRP_Sector_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */ #define OB_WRP_Sector_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */ #define OB_WRP_Sector_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */ #define OB_WRP_Sector_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */ #define OB_WRP_Sector_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */ #define OB_WRP_Sector_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */ #define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) /** * @} */ /** @defgroup FLASH_Option_Bytes_Read_Protection * @{ */ #define OB_RDP_Level_0 ((uint8_t)0xAA) #define OB_RDP_Level_1 ((uint8_t)0x55) /*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2 it's no more possible to go back to level 1 or 0 */ #define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\ ((LEVEL) == OB_RDP_Level_1))/*||\ ((LEVEL) == OB_RDP_Level_2))*/ /** * @} */ /** @defgroup FLASH_Option_Bytes_IWatchdog * @{ */ #define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */ #define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */ #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) /** * @} */ /** @defgroup FLASH_Option_Bytes_nRST_STOP * @{ */ #define OB_STOP_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */ #define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) /** * @} */ /** @defgroup FLASH_Option_Bytes_nRST_STDBY * @{ */ #define OB_STDBY_NoRST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */ #define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) /** * @} */ /** @defgroup FLASH_BOR_Reset_Level * @{ */ #define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */ #define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */ #define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */ #define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */ #define IS_OB_BOR(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\ ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF)) /** * @} */ /** @defgroup FLASH_Interrupts * @{ */ #define FLASH_IT_EOP ((uint32_t)0x01000000) /*!< End of FLASH Operation Interrupt source */ #define FLASH_IT_ERR ((uint32_t)0x02000000) /*!< Error Interrupt source */ #define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000)) /** * @} */ /** @defgroup FLASH_Flags * @{ */ #define FLASH_FLAG_EOP ((uint32_t)0x00000001) /*!< FLASH End of Operation flag */ #define FLASH_FLAG_OPERR ((uint32_t)0x00000002) /*!< FLASH operation Error flag */ #define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ #define FLASH_FLAG_PGAERR ((uint32_t)0x00000020) /*!< FLASH Programming Alignment error flag */ #define FLASH_FLAG_PGPERR ((uint32_t)0x00000040) /*!< FLASH Programming Parallelism error flag */ #define FLASH_FLAG_PGSERR ((uint32_t)0x00000080) /*!< FLASH Programming Sequence error flag */ #define FLASH_FLAG_BSY ((uint32_t)0x00010000) /*!< FLASH Busy flag */ #define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF0C) == 0x00000000) && ((FLAG) != 0x00000000)) #define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \ ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \ ((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \ ((FLAG) == FLASH_FLAG_BSY)) /** * @} */ /** @defgroup FLASH_Program_Parallelism * @{ */ #define FLASH_PSIZE_BYTE ((uint32_t)0x00000000) #define FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100) #define FLASH_PSIZE_WORD ((uint32_t)0x00000200) #define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300) #define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF) /** * @} */ /** @defgroup FLASH_Keys * @{ */ #define RDP_KEY ((uint16_t)0x00A5) #define FLASH_KEY1 ((uint32_t)0x45670123) #define FLASH_KEY2 ((uint32_t)0xCDEF89AB) #define FLASH_OPT_KEY1 ((uint32_t)0x08192A3B) #define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F) /** * @} */ /** * @brief ACR register byte 0 (Bits[8:0]) base address */ #define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00) /** * @brief OPTCR register byte 3 (Bits[24:16]) base address */ #define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14) #define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15) #define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16) /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* FLASH Interface configuration functions ************************************/ void FLASH_SetLatency(uint32_t FLASH_Latency); void FLASH_PrefetchBufferCmd(FunctionalState NewState); void FLASH_InstructionCacheCmd(FunctionalState NewState); void FLASH_DataCacheCmd(FunctionalState NewState); void FLASH_InstructionCacheReset(void); void FLASH_DataCacheReset(void); /* FLASH Memory Programming functions *****************************************/ void FLASH_Unlock(void); void FLASH_Lock(void); FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange); FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange); FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data); FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data); /* Option Bytes Programming functions *****************************************/ void FLASH_OB_Unlock(void); void FLASH_OB_Lock(void); void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState); void FLASH_OB_RDPConfig(uint8_t OB_RDP); void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); void FLASH_OB_BORConfig(uint8_t OB_BOR); FLASH_Status FLASH_OB_Launch(void); uint8_t FLASH_OB_GetUser(void); uint16_t FLASH_OB_GetWRP(void); FlagStatus FLASH_OB_GetRDP(void); uint8_t FLASH_OB_GetBOR(void); /* Interrupts and flags management functions **********************************/ void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); void FLASH_ClearFlag(uint32_t FLASH_FLAG); FLASH_Status FLASH_GetStatus(void); FLASH_Status FLASH_WaitForLastOperation(void); #ifdef __cplusplus } #endif #endif /* __STM32F4xx_FLASH_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fsmc.h ================================================ /** ****************************************************************************** * @file stm32f4xx_fsmc.h * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file contains all the functions prototypes for the FSMC firmware * library. ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_FSMC_H #define __STM32F4xx_FSMC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup FSMC * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief Timing parameters For NOR/SRAM Banks */ typedef struct { uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure the duration of the address setup time. This parameter can be a value between 0 and 0xF. @note This parameter is not used with synchronous NOR Flash memories. */ uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure the duration of the address hold time. This parameter can be a value between 0 and 0xF. @note This parameter is not used with synchronous NOR Flash memories.*/ uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure the duration of the data setup time. This parameter can be a value between 0 and 0xFF. @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure the duration of the bus turnaround. This parameter can be a value between 0 and 0xF. @note This parameter is only used for multiplexed NOR Flash memories. */ uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. This parameter can be a value between 1 and 0xF. @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue to the memory before getting the first data. The parameter value depends on the memory type as shown below: - It must be set to 0 in case of a CRAM - It is don't care in asynchronous NOR, SRAM or ROM accesses - It may assume a value between 0 and 0xF in NOR Flash memories with synchronous burst mode enable */ uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. This parameter can be a value of @ref FSMC_Access_Mode */ }FSMC_NORSRAMTimingInitTypeDef; /** * @brief FSMC NOR/SRAM Init structure definition */ typedef struct { uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. This parameter can be a value of @ref FSMC_NORSRAM_Bank */ uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are multiplexed on the databus or not. This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to the corresponding memory bank. This parameter can be a value of @ref FSMC_Memory_Type */ uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. This parameter can be a value of @ref FSMC_Data_Width */ uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, valid only with synchronous burst Flash memories. This parameter can be a value of @ref FSMC_Burst_Access_Mode */ uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, valid only with asynchronous Flash memories. This parameter can be a value of @ref FSMC_AsynchronousWait */ uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing the Flash memory in burst mode. This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash memory, valid only when accessing Flash memories in burst mode. This parameter can be a value of @ref FSMC_Wrap_Mode */ uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one clock cycle before the wait state or during the wait state, valid only when accessing memories in burst mode. This parameter can be a value of @ref FSMC_Wait_Timing */ uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. This parameter can be a value of @ref FSMC_Write_Operation */ uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait signal, valid for Flash memory access in burst mode. This parameter can be a value of @ref FSMC_Wait_Signal */ uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode. This parameter can be a value of @ref FSMC_Extended_Mode */ uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation. This parameter can be a value of @ref FSMC_Write_Burst */ FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ }FSMC_NORSRAMInitTypeDef; /** * @brief Timing parameters For FSMC NAND and PCCARD Banks */ typedef struct { uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before the command assertion for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a value between 0 and 0xFF.*/ uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the command for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between 0x00 and 0xFF */ uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address (and data for write access) after the command deassertion for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between 0x00 and 0xFF */ uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the start of a NAND-Flash write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between 0x00 and 0xFF */ }FSMC_NAND_PCCARDTimingInitTypeDef; /** * @brief FSMC NAND Init structure definition */ typedef struct { uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used. This parameter can be a value of @ref FSMC_NAND_Bank */ uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. This parameter can be any value of @ref FSMC_Wait_feature */ uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. This parameter can be any value of @ref FSMC_Data_Width */ uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation. This parameter can be any value of @ref FSMC_ECC */ uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC. This parameter can be any value of @ref FSMC_ECC_Page_Size */ uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between CLE low and RE low. This parameter can be a value between 0 and 0xFF. */ uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between 0x0 and 0xFF */ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ }FSMC_NANDInitTypeDef; /** * @brief FSMC PCCARD Init structure definition */ typedef struct { uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. This parameter can be any value of @ref FSMC_Wait_feature */ uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between CLE low and RE low. This parameter can be a value between 0 and 0xFF. */ uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between 0x0 and 0xFF */ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ }FSMC_PCCARDInitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup FSMC_Exported_Constants * @{ */ /** @defgroup FSMC_NORSRAM_Bank * @{ */ #define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) #define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) #define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) #define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) /** * @} */ /** @defgroup FSMC_NAND_Bank * @{ */ #define FSMC_Bank2_NAND ((uint32_t)0x00000010) #define FSMC_Bank3_NAND ((uint32_t)0x00000100) /** * @} */ /** @defgroup FSMC_PCCARD_Bank * @{ */ #define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) /** * @} */ #define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ ((BANK) == FSMC_Bank1_NORSRAM2) || \ ((BANK) == FSMC_Bank1_NORSRAM3) || \ ((BANK) == FSMC_Bank1_NORSRAM4)) #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ ((BANK) == FSMC_Bank3_NAND)) #define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ ((BANK) == FSMC_Bank3_NAND) || \ ((BANK) == FSMC_Bank4_PCCARD)) #define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ ((BANK) == FSMC_Bank3_NAND) || \ ((BANK) == FSMC_Bank4_PCCARD)) /** @defgroup FSMC_NOR_SRAM_Controller * @{ */ /** @defgroup FSMC_Data_Address_Bus_Multiplexing * @{ */ #define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) #define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) #define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ ((MUX) == FSMC_DataAddressMux_Enable)) /** * @} */ /** @defgroup FSMC_Memory_Type * @{ */ #define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) #define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) #define FSMC_MemoryType_NOR ((uint32_t)0x00000008) #define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ ((MEMORY) == FSMC_MemoryType_NOR)) /** * @} */ /** @defgroup FSMC_Data_Width * @{ */ #define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) #define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) #define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ ((WIDTH) == FSMC_MemoryDataWidth_16b)) /** * @} */ /** @defgroup FSMC_Burst_Access_Mode * @{ */ #define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) #define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) #define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ ((STATE) == FSMC_BurstAccessMode_Enable)) /** * @} */ /** @defgroup FSMC_AsynchronousWait * @{ */ #define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000) #define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000) #define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \ ((STATE) == FSMC_AsynchronousWait_Enable)) /** * @} */ /** @defgroup FSMC_Wait_Signal_Polarity * @{ */ #define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) #define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) #define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ ((POLARITY) == FSMC_WaitSignalPolarity_High)) /** * @} */ /** @defgroup FSMC_Wrap_Mode * @{ */ #define FSMC_WrapMode_Disable ((uint32_t)0x00000000) #define FSMC_WrapMode_Enable ((uint32_t)0x00000400) #define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ ((MODE) == FSMC_WrapMode_Enable)) /** * @} */ /** @defgroup FSMC_Wait_Timing * @{ */ #define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) #define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) #define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) /** * @} */ /** @defgroup FSMC_Write_Operation * @{ */ #define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) #define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) #define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ ((OPERATION) == FSMC_WriteOperation_Enable)) /** * @} */ /** @defgroup FSMC_Wait_Signal * @{ */ #define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) #define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) #define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ ((SIGNAL) == FSMC_WaitSignal_Enable)) /** * @} */ /** @defgroup FSMC_Extended_Mode * @{ */ #define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) #define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) #define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ ((MODE) == FSMC_ExtendedMode_Enable)) /** * @} */ /** @defgroup FSMC_Write_Burst * @{ */ #define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) #define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) #define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ ((BURST) == FSMC_WriteBurst_Enable)) /** * @} */ /** @defgroup FSMC_Address_Setup_Time * @{ */ #define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) /** * @} */ /** @defgroup FSMC_Address_Hold_Time * @{ */ #define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) /** * @} */ /** @defgroup FSMC_Data_Setup_Time * @{ */ #define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) /** * @} */ /** @defgroup FSMC_Bus_Turn_around_Duration * @{ */ #define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) /** * @} */ /** @defgroup FSMC_CLK_Division * @{ */ #define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) /** * @} */ /** @defgroup FSMC_Data_Latency * @{ */ #define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) /** * @} */ /** @defgroup FSMC_Access_Mode * @{ */ #define FSMC_AccessMode_A ((uint32_t)0x00000000) #define FSMC_AccessMode_B ((uint32_t)0x10000000) #define FSMC_AccessMode_C ((uint32_t)0x20000000) #define FSMC_AccessMode_D ((uint32_t)0x30000000) #define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ ((MODE) == FSMC_AccessMode_B) || \ ((MODE) == FSMC_AccessMode_C) || \ ((MODE) == FSMC_AccessMode_D)) /** * @} */ /** * @} */ /** @defgroup FSMC_NAND_PCCARD_Controller * @{ */ /** @defgroup FSMC_Wait_feature * @{ */ #define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) #define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ ((FEATURE) == FSMC_Waitfeature_Enable)) /** * @} */ /** @defgroup FSMC_ECC * @{ */ #define FSMC_ECC_Disable ((uint32_t)0x00000000) #define FSMC_ECC_Enable ((uint32_t)0x00000040) #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ ((STATE) == FSMC_ECC_Enable)) /** * @} */ /** @defgroup FSMC_ECC_Page_Size * @{ */ #define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) #define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) #define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) #define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) #define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) #define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ ((SIZE) == FSMC_ECCPageSize_8192Bytes)) /** * @} */ /** @defgroup FSMC_TCLR_Setup_Time * @{ */ #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) /** * @} */ /** @defgroup FSMC_TAR_Setup_Time * @{ */ #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) /** * @} */ /** @defgroup FSMC_Setup_Time * @{ */ #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) /** * @} */ /** @defgroup FSMC_Wait_Setup_Time * @{ */ #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) /** * @} */ /** @defgroup FSMC_Hold_Setup_Time * @{ */ #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) /** * @} */ /** @defgroup FSMC_HiZ_Setup_Time * @{ */ #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) /** * @} */ /** @defgroup FSMC_Interrupt_sources * @{ */ #define FSMC_IT_RisingEdge ((uint32_t)0x00000008) #define FSMC_IT_Level ((uint32_t)0x00000010) #define FSMC_IT_FallingEdge ((uint32_t)0x00000020) #define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) #define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ ((IT) == FSMC_IT_Level) || \ ((IT) == FSMC_IT_FallingEdge)) /** * @} */ /** @defgroup FSMC_Flags * @{ */ #define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) #define FSMC_FLAG_Level ((uint32_t)0x00000002) #define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) #define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) #define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ ((FLAG) == FSMC_FLAG_Level) || \ ((FLAG) == FSMC_FLAG_FallingEdge) || \ ((FLAG) == FSMC_FLAG_FEMPT)) #define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) /** * @} */ /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* NOR/SRAM Controller functions **********************************************/ void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); /* NAND Controller functions **************************************************/ void FSMC_NANDDeInit(uint32_t FSMC_Bank); void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); uint32_t FSMC_GetECC(uint32_t FSMC_Bank); /* PCCARD Controller functions ************************************************/ void FSMC_PCCARDDeInit(void); void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); void FSMC_PCCARDCmd(FunctionalState NewState); /* Interrupts and flags management functions **********************************/ void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); #ifdef __cplusplus } #endif #endif /*__STM32F4xx_FSMC_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h ================================================ /** ****************************************************************************** * @file stm32f4xx_gpio.h * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file contains all the functions prototypes for the GPIO firmware * library. ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_GPIO_H #define __STM32F4xx_GPIO_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup GPIO * @{ */ /* Exported types ------------------------------------------------------------*/ #define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ ((PERIPH) == GPIOB) || \ ((PERIPH) == GPIOC) || \ ((PERIPH) == GPIOD) || \ ((PERIPH) == GPIOE) || \ ((PERIPH) == GPIOF) || \ ((PERIPH) == GPIOG) || \ ((PERIPH) == GPIOH) || \ ((PERIPH) == GPIOI)) /** * @brief GPIO Configuration Mode enumeration */ typedef enum { GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */ GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */ GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */ GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */ }GPIOMode_TypeDef; #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \ ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN)) /** * @brief GPIO Output type enumeration */ typedef enum { GPIO_OType_PP = 0x00, GPIO_OType_OD = 0x01 }GPIOOType_TypeDef; #define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD)) /** * @brief GPIO Output Maximum frequency enumeration */ typedef enum { GPIO_Speed_2MHz = 0x00, /*!< Low speed */ GPIO_Speed_25MHz = 0x01, /*!< Medium speed */ GPIO_Speed_50MHz = 0x02, /*!< Fast speed */ GPIO_Speed_100MHz = 0x03 /*!< High speed on 30 pF (80 MHz Output max speed on 15 pF) */ }GPIOSpeed_TypeDef; #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_2MHz) || ((SPEED) == GPIO_Speed_25MHz) || \ ((SPEED) == GPIO_Speed_50MHz)|| ((SPEED) == GPIO_Speed_100MHz)) /** * @brief GPIO Configuration PullUp PullDown enumeration */ typedef enum { GPIO_PuPd_NOPULL = 0x00, GPIO_PuPd_UP = 0x01, GPIO_PuPd_DOWN = 0x02 }GPIOPuPd_TypeDef; #define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \ ((PUPD) == GPIO_PuPd_DOWN)) /** * @brief GPIO Bit SET and Bit RESET enumeration */ typedef enum { Bit_RESET = 0, Bit_SET }BitAction; #define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) /** * @brief GPIO Init structure definition */ typedef struct { uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. This parameter can be any value of @ref GPIO_pins_define */ GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. This parameter can be a value of @ref GPIOMode_TypeDef */ GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. This parameter can be a value of @ref GPIOSpeed_TypeDef */ GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins. This parameter can be a value of @ref GPIOOType_TypeDef */ GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins. This parameter can be a value of @ref GPIOPuPd_TypeDef */ }GPIO_InitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup GPIO_Exported_Constants * @{ */ /** @defgroup GPIO_pins_define * @{ */ #define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ #define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ #define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ #define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ #define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ #define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ #define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ #define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ #define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ #define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ #define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ #define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ #define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ #define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ #define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ #define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ #define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ #define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) #define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ ((PIN) == GPIO_Pin_1) || \ ((PIN) == GPIO_Pin_2) || \ ((PIN) == GPIO_Pin_3) || \ ((PIN) == GPIO_Pin_4) || \ ((PIN) == GPIO_Pin_5) || \ ((PIN) == GPIO_Pin_6) || \ ((PIN) == GPIO_Pin_7) || \ ((PIN) == GPIO_Pin_8) || \ ((PIN) == GPIO_Pin_9) || \ ((PIN) == GPIO_Pin_10) || \ ((PIN) == GPIO_Pin_11) || \ ((PIN) == GPIO_Pin_12) || \ ((PIN) == GPIO_Pin_13) || \ ((PIN) == GPIO_Pin_14) || \ ((PIN) == GPIO_Pin_15)) /** * @} */ /** @defgroup GPIO_Pin_sources * @{ */ #define GPIO_PinSource0 ((uint8_t)0x00) #define GPIO_PinSource1 ((uint8_t)0x01) #define GPIO_PinSource2 ((uint8_t)0x02) #define GPIO_PinSource3 ((uint8_t)0x03) #define GPIO_PinSource4 ((uint8_t)0x04) #define GPIO_PinSource5 ((uint8_t)0x05) #define GPIO_PinSource6 ((uint8_t)0x06) #define GPIO_PinSource7 ((uint8_t)0x07) #define GPIO_PinSource8 ((uint8_t)0x08) #define GPIO_PinSource9 ((uint8_t)0x09) #define GPIO_PinSource10 ((uint8_t)0x0A) #define GPIO_PinSource11 ((uint8_t)0x0B) #define GPIO_PinSource12 ((uint8_t)0x0C) #define GPIO_PinSource13 ((uint8_t)0x0D) #define GPIO_PinSource14 ((uint8_t)0x0E) #define GPIO_PinSource15 ((uint8_t)0x0F) #define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ ((PINSOURCE) == GPIO_PinSource1) || \ ((PINSOURCE) == GPIO_PinSource2) || \ ((PINSOURCE) == GPIO_PinSource3) || \ ((PINSOURCE) == GPIO_PinSource4) || \ ((PINSOURCE) == GPIO_PinSource5) || \ ((PINSOURCE) == GPIO_PinSource6) || \ ((PINSOURCE) == GPIO_PinSource7) || \ ((PINSOURCE) == GPIO_PinSource8) || \ ((PINSOURCE) == GPIO_PinSource9) || \ ((PINSOURCE) == GPIO_PinSource10) || \ ((PINSOURCE) == GPIO_PinSource11) || \ ((PINSOURCE) == GPIO_PinSource12) || \ ((PINSOURCE) == GPIO_PinSource13) || \ ((PINSOURCE) == GPIO_PinSource14) || \ ((PINSOURCE) == GPIO_PinSource15)) /** * @} */ /** @defgroup GPIO_Alternat_function_selection_define * @{ */ /** * @brief AF 0 selection */ #define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ #define GPIO_AF_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ #define GPIO_AF_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ #define GPIO_AF_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ #define GPIO_AF_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ /** * @brief AF 1 selection */ #define GPIO_AF_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ #define GPIO_AF_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ /** * @brief AF 2 selection */ #define GPIO_AF_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ #define GPIO_AF_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ #define GPIO_AF_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ /** * @brief AF 3 selection */ #define GPIO_AF_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ #define GPIO_AF_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ #define GPIO_AF_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ #define GPIO_AF_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ /** * @brief AF 4 selection */ #define GPIO_AF_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ #define GPIO_AF_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ #define GPIO_AF_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ /** * @brief AF 5 selection */ #define GPIO_AF_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ #define GPIO_AF_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ /** * @brief AF 6 selection */ #define GPIO_AF_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ /** * @brief AF 7 selection */ #define GPIO_AF_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ #define GPIO_AF_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ #define GPIO_AF_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ #define GPIO_AF_I2S3ext ((uint8_t)0x07) /* I2S3ext Alternate Function mapping */ /** * @brief AF 8 selection */ #define GPIO_AF_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ #define GPIO_AF_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ #define GPIO_AF_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ /** * @brief AF 9 selection */ #define GPIO_AF_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ #define GPIO_AF_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ #define GPIO_AF_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ #define GPIO_AF_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ #define GPIO_AF_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ /** * @brief AF 10 selection */ #define GPIO_AF_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */ #define GPIO_AF_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */ /** * @brief AF 11 selection */ #define GPIO_AF_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ /** * @brief AF 12 selection */ #define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */ #define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */ #define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */ /** * @brief AF 13 selection */ #define GPIO_AF_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ /** * @brief AF 15 selection */ #define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ #define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \ ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \ ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \ ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \ ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \ ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \ ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \ ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \ ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \ ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \ ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \ ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \ ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_FSMC) || \ ((AF) == GPIO_AF_OTG_HS_FS) || ((AF) == GPIO_AF_SDIO) || \ ((AF) == GPIO_AF_DCMI) || ((AF) == GPIO_AF_EVENTOUT)) /** * @} */ /** @defgroup GPIO_Legacy * @{ */ #define GPIO_Mode_AIN GPIO_Mode_AN #define GPIO_AF_OTG1_FS GPIO_AF_OTG_FS #define GPIO_AF_OTG2_HS GPIO_AF_OTG_HS #define GPIO_AF_OTG2_FS GPIO_AF_OTG_HS_FS /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the GPIO configuration to the default reset state ****/ void GPIO_DeInit(GPIO_TypeDef* GPIOx); /* Initialization and Configuration functions *********************************/ void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); /* GPIO Read and Write functions **********************************************/ uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); /* GPIO Alternate functions configuration function ****************************/ void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF); #ifdef __cplusplus } #endif #endif /*__STM32F4xx_GPIO_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_hash.h ================================================ /** ****************************************************************************** * @file stm32f4xx_hash.h * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file contains all the functions prototypes for the HASH * firmware library. ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_HASH_H #define __STM32F4xx_HASH_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup HASH * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief HASH Init structure definition */ typedef struct { uint32_t HASH_AlgoSelection; /*!< SHA-1 or MD5. This parameter can be a value of @ref HASH_Algo_Selection */ uint32_t HASH_AlgoMode; /*!< HASH or HMAC. This parameter can be a value of @ref HASH_processor_Algorithm_Mode */ uint32_t HASH_DataType; /*!< 32-bit data, 16-bit data, 8-bit data or bit-string. This parameter can be a value of @ref HASH_Data_Type */ uint32_t HASH_HMACKeyType; /*!< HMAC Short key or HMAC Long Key. This parameter can be a value of @ref HASH_HMAC_Long_key_only_for_HMAC_mode */ }HASH_InitTypeDef; /** * @brief HASH message digest result structure definition */ typedef struct { uint32_t Data[5]; /*!< Message digest result : 5x 32bit words for SHA1 or 4x 32bit words for MD5 */ } HASH_MsgDigest; /** * @brief HASH context swapping structure definition */ typedef struct { uint32_t HASH_IMR; uint32_t HASH_STR; uint32_t HASH_CR; uint32_t HASH_CSR[51]; }HASH_Context; /* Exported constants --------------------------------------------------------*/ /** @defgroup HASH_Exported_Constants * @{ */ /** @defgroup HASH_Algo_Selection * @{ */ #define HASH_AlgoSelection_SHA1 ((uint16_t)0x0000) /*!< HASH function is SHA1 */ #define HASH_AlgoSelection_MD5 ((uint16_t)0x0080) /*!< HASH function is MD5 */ #define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || \ ((ALGOSELECTION) == HASH_AlgoSelection_MD5)) /** * @} */ /** @defgroup HASH_processor_Algorithm_Mode * @{ */ #define HASH_AlgoMode_HASH ((uint16_t)0x0000) /*!< Algorithm is HASH */ #define HASH_AlgoMode_HMAC ((uint16_t)0x0040) /*!< Algorithm is HMAC */ #define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || \ ((ALGOMODE) == HASH_AlgoMode_HMAC)) /** * @} */ /** @defgroup HASH_Data_Type * @{ */ #define HASH_DataType_32b ((uint16_t)0x0000) #define HASH_DataType_16b ((uint16_t)0x0010) #define HASH_DataType_8b ((uint16_t)0x0020) #define HASH_DataType_1b ((uint16_t)0x0030) #define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DataType_32b)|| \ ((DATATYPE) == HASH_DataType_16b)|| \ ((DATATYPE) == HASH_DataType_8b)|| \ ((DATATYPE) == HASH_DataType_1b)) /** * @} */ /** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode * @{ */ #define HASH_HMACKeyType_ShortKey ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */ #define HASH_HMACKeyType_LongKey ((uint32_t)0x00010000) /*!< HMAC Key is > 64 bytes */ #define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \ ((KEYTYPE) == HASH_HMACKeyType_LongKey)) /** * @} */ /** @defgroup Number_of_valid_bits_in_last_word_of_the_message * @{ */ #define IS_HASH_VALIDBITSNUMBER(VALIDBITS) ((VALIDBITS) <= 0x1F) /** * @} */ /** @defgroup HASH_interrupts_definition * @{ */ #define HASH_IT_DINI ((uint8_t)0x01) /*!< A new block can be entered into the input buffer (DIN)*/ #define HASH_IT_DCI ((uint8_t)0x02) /*!< Digest calculation complete */ #define IS_HASH_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00)) #define IS_HASH_GET_IT(IT) (((IT) == HASH_IT_DINI) || ((IT) == HASH_IT_DCI)) /** * @} */ /** @defgroup HASH_flags_definition * @{ */ #define HASH_FLAG_DINIS ((uint16_t)0x0001) /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer.*/ #define HASH_FLAG_DCIS ((uint16_t)0x0002) /*!< Digest calculation complete */ #define HASH_FLAG_DMAS ((uint16_t)0x0004) /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */ #define HASH_FLAG_BUSY ((uint16_t)0x0008) /*!< The hash core is Busy : processing a block of data */ #define HASH_FLAG_DINNE ((uint16_t)0x1000) /*!< DIN not empty : The input buffer contains at least one word of data */ #define IS_HASH_GET_FLAG(FLAG) (((FLAG) == HASH_FLAG_DINIS) || \ ((FLAG) == HASH_FLAG_DCIS) || \ ((FLAG) == HASH_FLAG_DMAS) || \ ((FLAG) == HASH_FLAG_BUSY) || \ ((FLAG) == HASH_FLAG_DINNE)) #define IS_HASH_CLEAR_FLAG(FLAG)(((FLAG) == HASH_FLAG_DINIS) || \ ((FLAG) == HASH_FLAG_DCIS)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the HASH configuration to the default reset state ****/ void HASH_DeInit(void); /* HASH Configuration function ************************************************/ void HASH_Init(HASH_InitTypeDef* HASH_InitStruct); void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct); void HASH_Reset(void); /* HASH Message Digest generation functions ***********************************/ void HASH_DataIn(uint32_t Data); uint8_t HASH_GetInFIFOWordsNbr(void); void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber); void HASH_StartDigest(void); void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest); /* HASH Context swapping functions ********************************************/ void HASH_SaveContext(HASH_Context* HASH_ContextSave); void HASH_RestoreContext(HASH_Context* HASH_ContextRestore); /* HASH's DMA interface function **********************************************/ void HASH_DMACmd(FunctionalState NewState); /* HASH Interrupts and flags management functions *****************************/ void HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState); FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG); void HASH_ClearFlag(uint16_t HASH_FLAG); ITStatus HASH_GetITStatus(uint8_t HASH_IT); void HASH_ClearITPendingBit(uint8_t HASH_IT); /* High Level SHA1 functions **************************************************/ ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]); ErrorStatus HMAC_SHA1(uint8_t *Key, uint32_t Keylen, uint8_t *Input, uint32_t Ilen, uint8_t Output[20]); /* High Level MD5 functions ***************************************************/ ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]); ErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen, uint8_t *Input, uint32_t Ilen, uint8_t Output[16]); #ifdef __cplusplus } #endif #endif /*__STM32F4xx_HASH_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_i2c.h ================================================ /** ****************************************************************************** * @file stm32f4xx_i2c.h * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file contains all the functions prototypes for the I2C firmware * library. ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_I2C_H #define __STM32F4xx_I2C_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup I2C * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief I2C Init structure definition */ typedef struct { uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency. This parameter must be set to a value lower than 400kHz */ uint16_t I2C_Mode; /*!< Specifies the I2C mode. This parameter can be a value of @ref I2C_mode */ uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle. This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address. This parameter can be a 7-bit or 10-bit address. */ uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement. This parameter can be a value of @ref I2C_acknowledgement */ uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. This parameter can be a value of @ref I2C_acknowledged_address */ }I2C_InitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup I2C_Exported_Constants * @{ */ #define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ ((PERIPH) == I2C2) || \ ((PERIPH) == I2C3)) /** @defgroup I2C_mode * @{ */ #define I2C_Mode_I2C ((uint16_t)0x0000) #define I2C_Mode_SMBusDevice ((uint16_t)0x0002) #define I2C_Mode_SMBusHost ((uint16_t)0x000A) #define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ ((MODE) == I2C_Mode_SMBusDevice) || \ ((MODE) == I2C_Mode_SMBusHost)) /** * @} */ /** @defgroup I2C_duty_cycle_in_fast_mode * @{ */ #define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ #define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ #define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ ((CYCLE) == I2C_DutyCycle_2)) /** * @} */ /** @defgroup I2C_acknowledgement * @{ */ #define I2C_Ack_Enable ((uint16_t)0x0400) #define I2C_Ack_Disable ((uint16_t)0x0000) #define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \ ((STATE) == I2C_Ack_Disable)) /** * @} */ /** @defgroup I2C_transfer_direction * @{ */ #define I2C_Direction_Transmitter ((uint8_t)0x00) #define I2C_Direction_Receiver ((uint8_t)0x01) #define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ ((DIRECTION) == I2C_Direction_Receiver)) /** * @} */ /** @defgroup I2C_acknowledged_address * @{ */ #define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) #define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) #define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) /** * @} */ /** @defgroup I2C_registers * @{ */ #define I2C_Register_CR1 ((uint8_t)0x00) #define I2C_Register_CR2 ((uint8_t)0x04) #define I2C_Register_OAR1 ((uint8_t)0x08) #define I2C_Register_OAR2 ((uint8_t)0x0C) #define I2C_Register_DR ((uint8_t)0x10) #define I2C_Register_SR1 ((uint8_t)0x14) #define I2C_Register_SR2 ((uint8_t)0x18) #define I2C_Register_CCR ((uint8_t)0x1C) #define I2C_Register_TRISE ((uint8_t)0x20) #define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ ((REGISTER) == I2C_Register_CR2) || \ ((REGISTER) == I2C_Register_OAR1) || \ ((REGISTER) == I2C_Register_OAR2) || \ ((REGISTER) == I2C_Register_DR) || \ ((REGISTER) == I2C_Register_SR1) || \ ((REGISTER) == I2C_Register_SR2) || \ ((REGISTER) == I2C_Register_CCR) || \ ((REGISTER) == I2C_Register_TRISE)) /** * @} */ /** @defgroup I2C_NACK_position * @{ */ #define I2C_NACKPosition_Next ((uint16_t)0x0800) #define I2C_NACKPosition_Current ((uint16_t)0xF7FF) #define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \ ((POSITION) == I2C_NACKPosition_Current)) /** * @} */ /** @defgroup I2C_SMBus_alert_pin_level * @{ */ #define I2C_SMBusAlert_Low ((uint16_t)0x2000) #define I2C_SMBusAlert_High ((uint16_t)0xDFFF) #define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \ ((ALERT) == I2C_SMBusAlert_High)) /** * @} */ /** @defgroup I2C_PEC_position * @{ */ #define I2C_PECPosition_Next ((uint16_t)0x0800) #define I2C_PECPosition_Current ((uint16_t)0xF7FF) #define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \ ((POSITION) == I2C_PECPosition_Current)) /** * @} */ /** @defgroup I2C_interrupts_definition * @{ */ #define I2C_IT_BUF ((uint16_t)0x0400) #define I2C_IT_EVT ((uint16_t)0x0200) #define I2C_IT_ERR ((uint16_t)0x0100) #define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) /** * @} */ /** @defgroup I2C_interrupts_definition * @{ */ #define I2C_IT_SMBALERT ((uint32_t)0x01008000) #define I2C_IT_TIMEOUT ((uint32_t)0x01004000) #define I2C_IT_PECERR ((uint32_t)0x01001000) #define I2C_IT_OVR ((uint32_t)0x01000800) #define I2C_IT_AF ((uint32_t)0x01000400) #define I2C_IT_ARLO ((uint32_t)0x01000200) #define I2C_IT_BERR ((uint32_t)0x01000100) #define I2C_IT_TXE ((uint32_t)0x06000080) #define I2C_IT_RXNE ((uint32_t)0x06000040) #define I2C_IT_STOPF ((uint32_t)0x02000010) #define I2C_IT_ADD10 ((uint32_t)0x02000008) #define I2C_IT_BTF ((uint32_t)0x02000004) #define I2C_IT_ADDR ((uint32_t)0x02000002) #define I2C_IT_SB ((uint32_t)0x02000001) #define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) #define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \ ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \ ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \ ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \ ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \ ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \ ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) /** * @} */ /** @defgroup I2C_flags_definition * @{ */ /** * @brief SR2 register flags */ #define I2C_FLAG_DUALF ((uint32_t)0x00800000) #define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) #define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) #define I2C_FLAG_GENCALL ((uint32_t)0x00100000) #define I2C_FLAG_TRA ((uint32_t)0x00040000) #define I2C_FLAG_BUSY ((uint32_t)0x00020000) #define I2C_FLAG_MSL ((uint32_t)0x00010000) /** * @brief SR1 register flags */ #define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) #define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) #define I2C_FLAG_PECERR ((uint32_t)0x10001000) #define I2C_FLAG_OVR ((uint32_t)0x10000800) #define I2C_FLAG_AF ((uint32_t)0x10000400) #define I2C_FLAG_ARLO ((uint32_t)0x10000200) #define I2C_FLAG_BERR ((uint32_t)0x10000100) #define I2C_FLAG_TXE ((uint32_t)0x10000080) #define I2C_FLAG_RXNE ((uint32_t)0x10000040) #define I2C_FLAG_STOPF ((uint32_t)0x10000010) #define I2C_FLAG_ADD10 ((uint32_t)0x10000008) #define I2C_FLAG_BTF ((uint32_t)0x10000004) #define I2C_FLAG_ADDR ((uint32_t)0x10000002) #define I2C_FLAG_SB ((uint32_t)0x10000001) #define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) #define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \ ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \ ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \ ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \ ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \ ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \ ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \ ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \ ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \ ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \ ((FLAG) == I2C_FLAG_SB)) /** * @} */ /** @defgroup I2C_Events * @{ */ /** =============================================================================== I2C Master Events (Events grouped in order of communication) =============================================================================== */ /** * @brief Communication start * * After sending the START condition (I2C_GenerateSTART() function) the master * has to wait for this event. It means that the Start condition has been correctly * released on the I2C bus (the bus is free, no other devices is communicating). * */ /* --EV5 */ #define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ /** * @brief Address Acknowledge * * After checking on EV5 (start condition correctly released on the bus), the * master sends the address of the slave(s) with which it will communicate * (I2C_Send7bitAddress() function, it also determines the direction of the communication: * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges * his address. If an acknowledge is sent on the bus, one of the following events will * be set: * * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED * event is set. * * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED * is set * * 3) In case of 10-Bit addressing mode, the master (just after generating the START * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() * function). Then master should wait on EV9. It means that the 10-bit addressing * header has been correctly sent on the bus. Then master should send the second part of * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master * should wait for event EV6. * */ /* --EV6 */ #define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ #define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ /* --EV9 */ #define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ /** * @brief Communication events * * If a communication is established (START condition generated and slave address * acknowledged) then the master has to check on one of the following events for * communication procedures: * * 1) Master Receiver mode: The master has to wait on the event EV7 then to read * the data received from the slave (I2C_ReceiveData() function). * * 2) Master Transmitter mode: The master has to send data (I2C_SendData() * function) then to wait on event EV8 or EV8_2. * These two events are similar: * - EV8 means that the data has been written in the data register and is * being shifted out. * - EV8_2 means that the data has been physically shifted out and output * on the bus. * In most cases, using EV8 is sufficient for the application. * Using EV8_2 leads to a slower communication but ensure more reliable test. * EV8_2 is also more suitable than EV8 for testing on the last data transmission * (before Stop condition generation). * * @note In case the user software does not guarantee that this event EV7 is * managed before the current byte end of transfer, then user may check on EV7 * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). * In this case the communication may be slower. * */ /* Master RECEIVER mode -----------------------------*/ /* --EV7 */ #define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ /* Master TRANSMITTER mode --------------------------*/ /* --EV8 */ #define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ /* --EV8_2 */ #define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ /** =============================================================================== I2C Slave Events (Events grouped in order of communication) =============================================================================== */ /** * @brief Communication start events * * Wait on one of these events at the start of the communication. It means that * the I2C peripheral detected a Start condition on the bus (generated by master * device) followed by the peripheral address. The peripheral generates an ACK * condition on the bus (if the acknowledge feature is enabled through function * I2C_AcknowledgeConfig()) and the events listed above are set : * * 1) In normal case (only one address managed by the slave), when the address * sent by the master matches the own address of the peripheral (configured by * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set * (where XXX could be TRANSMITTER or RECEIVER). * * 2) In case the address sent by the master matches the second address of the * peripheral (configured by the function I2C_OwnAddress2Config() and enabled * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED * (where XXX could be TRANSMITTER or RECEIVER) are set. * * 3) In case the address sent by the master is General Call (address 0x00) and * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. * */ /* --EV1 (all the events below are variants of EV1) */ /* 1) Case of One Single Address managed by the slave */ #define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ #define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ /* 2) Case of Dual address managed by the slave */ #define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ #define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ /* 3) Case of General Call enabled for the slave */ #define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ /** * @brief Communication events * * Wait on one of these events when EV1 has already been checked and: * * - Slave RECEIVER mode: * - EV2: When the application is expecting a data byte to be received. * - EV4: When the application is expecting the end of the communication: master * sends a stop condition and data transmission is stopped. * * - Slave Transmitter mode: * - EV3: When a byte has been transmitted by the slave and the application is expecting * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be * used when the user software doesn't guarantee the EV3 is managed before the * current byte end of transfer. * - EV3_2: When the master sends a NACK in order to tell slave that data transmission * shall end (before sending the STOP condition). In this case slave has to stop sending * data bytes and expect a Stop condition on the bus. * * @note In case the user software does not guarantee that the event EV2 is * managed before the current byte end of transfer, then user may check on EV2 * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). * In this case the communication may be slower. * */ /* Slave RECEIVER mode --------------------------*/ /* --EV2 */ #define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ /* --EV4 */ #define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ /* Slave TRANSMITTER mode -----------------------*/ /* --EV3 */ #define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ #define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ /* --EV3_2 */ #define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ /* =============================================================================== End of Events Description =============================================================================== */ #define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \ ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \ ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \ ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \ ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \ ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) /** * @} */ /** @defgroup I2C_own_address1 * @{ */ #define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) /** * @} */ /** @defgroup I2C_clock_speed * @{ */ #define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the I2C configuration to the default reset state *****/ void I2C_DeInit(I2C_TypeDef* I2Cx); /* Initialization and Configuration functions *********************************/ void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition); void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); /* Data transfers functions ***************************************************/ void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); /* PEC management functions ***************************************************/ void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); /* DMA transfers management functions *****************************************/ void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); /* Interrupts, events and flags management functions **************************/ uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); /* =============================================================================== I2C State Monitoring Functions =============================================================================== This I2C driver provides three different ways for I2C state monitoring depending on the application requirements and constraints: 1. Basic state monitoring (Using I2C_CheckEvent() function) ----------------------------------------------------------- It compares the status registers (SR1 and SR2) content to a given event (can be the combination of one or more flags). It returns SUCCESS if the current status includes the given flags and returns ERROR if one or more flags are missing in the current status. - When to use - This function is suitable for most applications as well as for startup activity since the events are fully described in the product reference manual (RM0090). - It is also suitable for users who need to define their own events. - Limitations - If an error occurs (ie. error flags are set besides to the monitored flags), the I2C_CheckEvent() function may return SUCCESS despite the communication hold or corrupted real state. In this case, it is advised to use error interrupts to monitor the error events and handle them in the interrupt IRQ handler. Note For error management, it is advised to use the following functions: - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. Where x is the peripheral instance (I2C1, I2C2 ...) - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the I2Cx_ER_IRQHandler() function in order to determine which error occurred. - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() and/or I2C_GenerateStop() in order to clear the error flag and source and return to correct communication status. 2. Advanced state monitoring (Using the function I2C_GetLastEvent()) -------------------------------------------------------------------- Using the function I2C_GetLastEvent() which returns the image of both status registers in a single word (uint32_t) (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1). - When to use - This function is suitable for the same applications above but it allows to overcome the mentioned limitation of I2C_GetFlagStatus() function. - The returned value could be compared to events already defined in this file or to custom values defined by user. This function is suitable when multiple flags are monitored at the same time. - At the opposite of I2C_CheckEvent() function, this function allows user to choose when an event is accepted (when all events flags are set and no other flags are set or just when the needed flags are set like I2C_CheckEvent() function. - Limitations - User may need to define his own events. - Same remark concerning the error management is applicable for this function if user decides to check only regular communication flags (and ignores error flags). 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus()) ----------------------------------------------------------------------- Using the function I2C_GetFlagStatus() which simply returns the status of one single flag (ie. I2C_FLAG_RXNE ...). - When to use - This function could be used for specific applications or in debug phase. - It is suitable when only one flag checking is needed (most I2C events are monitored through multiple flags). - Limitations: - When calling this function, the Status register is accessed. Some flags are cleared when the status register is accessed. So checking the status of one Flag, may clear other ones. - Function may need to be called twice or more in order to monitor one single event. */ /* =============================================================================== 1. Basic state monitoring =============================================================================== */ ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); /* =============================================================================== 2. Advanced state monitoring =============================================================================== */ uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); /* =============================================================================== 3. Flag-based state monitoring =============================================================================== */ FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); #ifdef __cplusplus } #endif #endif /*__STM32F4xx_I2C_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h ================================================ /** ****************************************************************************** * @file stm32f4xx_iwdg.h * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file contains all the functions prototypes for the IWDG * firmware library. ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_IWDG_H #define __STM32F4xx_IWDG_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup IWDG * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup IWDG_Exported_Constants * @{ */ /** @defgroup IWDG_WriteAccess * @{ */ #define IWDG_WriteAccess_Enable ((uint16_t)0x5555) #define IWDG_WriteAccess_Disable ((uint16_t)0x0000) #define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ ((ACCESS) == IWDG_WriteAccess_Disable)) /** * @} */ /** @defgroup IWDG_prescaler * @{ */ #define IWDG_Prescaler_4 ((uint8_t)0x00) #define IWDG_Prescaler_8 ((uint8_t)0x01) #define IWDG_Prescaler_16 ((uint8_t)0x02) #define IWDG_Prescaler_32 ((uint8_t)0x03) #define IWDG_Prescaler_64 ((uint8_t)0x04) #define IWDG_Prescaler_128 ((uint8_t)0x05) #define IWDG_Prescaler_256 ((uint8_t)0x06) #define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ ((PRESCALER) == IWDG_Prescaler_8) || \ ((PRESCALER) == IWDG_Prescaler_16) || \ ((PRESCALER) == IWDG_Prescaler_32) || \ ((PRESCALER) == IWDG_Prescaler_64) || \ ((PRESCALER) == IWDG_Prescaler_128)|| \ ((PRESCALER) == IWDG_Prescaler_256)) /** * @} */ /** @defgroup IWDG_Flag * @{ */ #define IWDG_FLAG_PVU ((uint16_t)0x0001) #define IWDG_FLAG_RVU ((uint16_t)0x0002) #define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) #define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Prescaler and Counter configuration functions ******************************/ void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); void IWDG_SetReload(uint16_t Reload); void IWDG_ReloadCounter(void); /* IWDG activation function ***************************************************/ void IWDG_Enable(void); /* Flag management function ***************************************************/ FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); #ifdef __cplusplus } #endif #endif /* __STM32F4xx_IWDG_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_pwr.h ================================================ /** ****************************************************************************** * @file stm32f4xx_pwr.h * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file contains all the functions prototypes for the PWR firmware * library. ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_PWR_H #define __STM32F4xx_PWR_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup PWR * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup PWR_Exported_Constants * @{ */ /** @defgroup PWR_PVD_detection_level * @{ */ #define PWR_PVDLevel_0 PWR_CR_PLS_LEV0 #define PWR_PVDLevel_1 PWR_CR_PLS_LEV1 #define PWR_PVDLevel_2 PWR_CR_PLS_LEV2 #define PWR_PVDLevel_3 PWR_CR_PLS_LEV3 #define PWR_PVDLevel_4 PWR_CR_PLS_LEV4 #define PWR_PVDLevel_5 PWR_CR_PLS_LEV5 #define PWR_PVDLevel_6 PWR_CR_PLS_LEV6 #define PWR_PVDLevel_7 PWR_CR_PLS_LEV7 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \ ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \ ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \ ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7)) /** * @} */ /** @defgroup PWR_Regulator_state_in_STOP_mode * @{ */ #define PWR_Regulator_ON ((uint32_t)0x00000000) #define PWR_Regulator_LowPower PWR_CR_LPDS #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ ((REGULATOR) == PWR_Regulator_LowPower)) /** * @} */ /** @defgroup PWR_STOP_mode_entry * @{ */ #define PWR_STOPEntry_WFI ((uint8_t)0x01) #define PWR_STOPEntry_WFE ((uint8_t)0x02) #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) /** @defgroup PWR_Regulator_Voltage_Scale * @{ */ #define PWR_Regulator_Voltage_Scale1 ((uint32_t)0x00004000) #define PWR_Regulator_Voltage_Scale2 ((uint32_t)0x00000000) #define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_Regulator_Voltage_Scale1) || ((VOLTAGE) == PWR_Regulator_Voltage_Scale2)) /** * @} */ /** @defgroup PWR_Flag * @{ */ #define PWR_FLAG_WU PWR_CSR_WUF #define PWR_FLAG_SB PWR_CSR_SBF #define PWR_FLAG_PVDO PWR_CSR_PVDO #define PWR_FLAG_BRR PWR_CSR_BRR #define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY /** @defgroup PWR_Flag_Legacy * @{ */ #define PWR_FLAG_REGRDY PWR_FLAG_VOSRDY /** * @} */ #define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) || \ ((FLAG) == PWR_FLAG_VOSRDY)) #define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the PWR configuration to the default reset state ******/ void PWR_DeInit(void); /* Backup Domain Access function **********************************************/ void PWR_BackupAccessCmd(FunctionalState NewState); /* PVD configuration functions ************************************************/ void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); void PWR_PVDCmd(FunctionalState NewState); /* WakeUp pins configuration functions ****************************************/ void PWR_WakeUpPinCmd(FunctionalState NewState); /* Main and Backup Regulators configuration functions *************************/ void PWR_BackupRegulatorCmd(FunctionalState NewState); void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage); /* FLASH Power Down configuration functions ***********************************/ void PWR_FlashPowerDownCmd(FunctionalState NewState); /* Low Power modes configuration functions ************************************/ void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); void PWR_EnterSTANDBYMode(void); /* Flags management functions *************************************************/ FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); void PWR_ClearFlag(uint32_t PWR_FLAG); #ifdef __cplusplus } #endif #endif /* __STM32F4xx_PWR_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h ================================================ /** ****************************************************************************** * @file stm32f4xx_rcc.h * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file contains all the functions prototypes for the RCC firmware library. ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_RCC_H #define __STM32F4xx_RCC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup RCC * @{ */ /* Exported types ------------------------------------------------------------*/ typedef struct { uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */ uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */ uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */ uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */ }RCC_ClocksTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup RCC_Exported_Constants * @{ */ /** @defgroup RCC_HSE_configuration * @{ */ #define RCC_HSE_OFF ((uint8_t)0x00) #define RCC_HSE_ON ((uint8_t)0x01) #define RCC_HSE_Bypass ((uint8_t)0x05) #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ ((HSE) == RCC_HSE_Bypass)) /** * @} */ /** @defgroup RCC_PLL_Clock_Source * @{ */ #define RCC_PLLSource_HSI ((uint32_t)0x00000000) #define RCC_PLLSource_HSE ((uint32_t)0x00400000) #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \ ((SOURCE) == RCC_PLLSource_HSE)) #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63) #define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) #define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15)) #define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) /** * @} */ /** @defgroup RCC_System_Clock_Source * @{ */ #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ ((SOURCE) == RCC_SYSCLKSource_HSE) || \ ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) /** * @} */ /** @defgroup RCC_AHB_Clock_Source * @{ */ #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ ((HCLK) == RCC_SYSCLK_Div512)) /** * @} */ /** @defgroup RCC_APB1_APB2_Clock_Source * @{ */ #define RCC_HCLK_Div1 ((uint32_t)0x00000000) #define RCC_HCLK_Div2 ((uint32_t)0x00001000) #define RCC_HCLK_Div4 ((uint32_t)0x00001400) #define RCC_HCLK_Div8 ((uint32_t)0x00001800) #define RCC_HCLK_Div16 ((uint32_t)0x00001C00) #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ ((PCLK) == RCC_HCLK_Div16)) /** * @} */ /** @defgroup RCC_Interrupt_Source * @{ */ #define RCC_IT_LSIRDY ((uint8_t)0x01) #define RCC_IT_LSERDY ((uint8_t)0x02) #define RCC_IT_HSIRDY ((uint8_t)0x04) #define RCC_IT_HSERDY ((uint8_t)0x08) #define RCC_IT_PLLRDY ((uint8_t)0x10) #define RCC_IT_PLLI2SRDY ((uint8_t)0x20) #define RCC_IT_CSS ((uint8_t)0x80) #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00)) #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ ((IT) == RCC_IT_PLLI2SRDY)) #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00)) /** * @} */ /** @defgroup RCC_LSE_Configuration * @{ */ #define RCC_LSE_OFF ((uint8_t)0x00) #define RCC_LSE_ON ((uint8_t)0x01) #define RCC_LSE_Bypass ((uint8_t)0x04) #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ ((LSE) == RCC_LSE_Bypass)) /** * @} */ /** @defgroup RCC_RTC_Clock_Source * @{ */ #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) #define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300) #define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300) #define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300) #define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300) #define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300) #define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300) #define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300) #define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300) #define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300) #define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300) #define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300) #define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300) #define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300) #define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300) #define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300) #define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300) #define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300) #define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300) #define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300) #define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300) #define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300) #define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300) #define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300) #define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300) #define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300) #define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300) #define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300) #define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300) #define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300) #define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300) #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ ((SOURCE) == RCC_RTCCLKSource_LSI) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div31)) /** * @} */ /** @defgroup RCC_I2S_Clock_Source * @{ */ #define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00) #define RCC_I2S2CLKSource_Ext ((uint8_t)0x01) #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext)) /** * @} */ /** @defgroup RCC_AHB1_Peripherals * @{ */ #define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001) #define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002) #define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004) #define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008) #define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010) #define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020) #define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040) #define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080) #define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100) #define RCC_AHB1Periph_CRC ((uint32_t)0x00001000) #define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000) #define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000) #define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000) #define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000) #define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000) #define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000) #define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000) #define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000) #define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000) #define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000) #define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000) #define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000) #define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000) #define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x818BEE00) == 0x00) && ((PERIPH) != 0x00)) #define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD9FEE00) == 0x00) && ((PERIPH) != 0x00)) #define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81986E00) == 0x00) && ((PERIPH) != 0x00)) /** * @} */ /** @defgroup RCC_AHB2_Peripherals * @{ */ #define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001) #define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010) #define RCC_AHB2Periph_HASH ((uint32_t)0x00000020) #define RCC_AHB2Periph_RNG ((uint32_t)0x00000040) #define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080) #define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00)) /** * @} */ /** @defgroup RCC_AHB3_Peripherals * @{ */ #define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001) #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00)) /** * @} */ /** @defgroup RCC_APB1_Peripherals * @{ */ #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) #define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) #define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) #define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) #define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) #define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) #define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) #define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) #define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) #define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) #define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000) #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) #define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) #define RCC_APB1Periph_PWR ((uint32_t)0x10000000) #define RCC_APB1Periph_DAC ((uint32_t)0x20000000) #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC9013600) == 0x00) && ((PERIPH) != 0x00)) /** * @} */ /** @defgroup RCC_APB2_Peripherals * @{ */ #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001) #define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002) #define RCC_APB2Periph_USART1 ((uint32_t)0x00000010) #define RCC_APB2Periph_USART6 ((uint32_t)0x00000020) #define RCC_APB2Periph_ADC ((uint32_t)0x00000100) #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100) #define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200) #define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400) #define RCC_APB2Periph_SDIO ((uint32_t)0x00000800) #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) #define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000) #define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000) #define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000) #define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000) #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A0CC) == 0x00) && ((PERIPH) != 0x00)) #define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A6CC) == 0x00) && ((PERIPH) != 0x00)) /** * @} */ /** @defgroup RCC_MCO1_Clock_Source_Prescaler * @{ */ #define RCC_MCO1Source_HSI ((uint32_t)0x00000000) #define RCC_MCO1Source_LSE ((uint32_t)0x00200000) #define RCC_MCO1Source_HSE ((uint32_t)0x00400000) #define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000) #define RCC_MCO1Div_1 ((uint32_t)0x00000000) #define RCC_MCO1Div_2 ((uint32_t)0x04000000) #define RCC_MCO1Div_3 ((uint32_t)0x05000000) #define RCC_MCO1Div_4 ((uint32_t)0x06000000) #define RCC_MCO1Div_5 ((uint32_t)0x07000000) #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \ ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK)) #define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \ ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \ ((DIV) == RCC_MCO1Div_5)) /** * @} */ /** @defgroup RCC_MCO2_Clock_Source_Prescaler * @{ */ #define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000) #define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000) #define RCC_MCO2Source_HSE ((uint32_t)0x80000000) #define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000) #define RCC_MCO2Div_1 ((uint32_t)0x00000000) #define RCC_MCO2Div_2 ((uint32_t)0x20000000) #define RCC_MCO2Div_3 ((uint32_t)0x28000000) #define RCC_MCO2Div_4 ((uint32_t)0x30000000) #define RCC_MCO2Div_5 ((uint32_t)0x38000000) #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \ ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK)) #define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \ ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \ ((DIV) == RCC_MCO2Div_5)) /** * @} */ /** @defgroup RCC_Flag * @{ */ #define RCC_FLAG_HSIRDY ((uint8_t)0x21) #define RCC_FLAG_HSERDY ((uint8_t)0x31) #define RCC_FLAG_PLLRDY ((uint8_t)0x39) #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) #define RCC_FLAG_LSERDY ((uint8_t)0x41) #define RCC_FLAG_LSIRDY ((uint8_t)0x61) #define RCC_FLAG_BORRST ((uint8_t)0x79) #define RCC_FLAG_PINRST ((uint8_t)0x7A) #define RCC_FLAG_PORRST ((uint8_t)0x7B) #define RCC_FLAG_SFTRST ((uint8_t)0x7C) #define RCC_FLAG_IWDGRST ((uint8_t)0x7D) #define RCC_FLAG_WWDGRST ((uint8_t)0x7E) #define RCC_FLAG_LPWRRST ((uint8_t)0x7F) #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \ ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \ ((FLAG) == RCC_FLAG_PLLI2SRDY)) #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the RCC clock configuration to the default reset state */ void RCC_DeInit(void); /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ void RCC_HSEConfig(uint8_t RCC_HSE); ErrorStatus RCC_WaitForHSEStartUp(void); void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); void RCC_HSICmd(FunctionalState NewState); void RCC_LSEConfig(uint8_t RCC_LSE); void RCC_LSICmd(FunctionalState NewState); void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ); void RCC_PLLCmd(FunctionalState NewState); void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR); void RCC_PLLI2SCmd(FunctionalState NewState); void RCC_ClockSecuritySystemCmd(FunctionalState NewState); void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div); void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div); /* System, AHB and APB busses clocks configuration functions ******************/ void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); uint8_t RCC_GetSYSCLKSource(void); void RCC_HCLKConfig(uint32_t RCC_SYSCLK); void RCC_PCLK1Config(uint32_t RCC_HCLK); void RCC_PCLK2Config(uint32_t RCC_HCLK); void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); /* Peripheral clocks configuration functions **********************************/ void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); void RCC_RTCCLKCmd(FunctionalState NewState); void RCC_BackupResetCmd(FunctionalState NewState); void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); /* Interrupts and flags management functions **********************************/ void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); void RCC_ClearFlag(void); ITStatus RCC_GetITStatus(uint8_t RCC_IT); void RCC_ClearITPendingBit(uint8_t RCC_IT); #ifdef __cplusplus } #endif #endif /* __STM32F4xx_RCC_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rng.h ================================================ /** ****************************************************************************** * @file stm32f4xx_rng.h * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file contains all the functions prototypes for the Random * Number Generator(RNG) firmware library. ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_RNG_H #define __STM32F4xx_RNG_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup RNG * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup RNG_Exported_Constants * @{ */ /** @defgroup RNG_flags_definition * @{ */ #define RNG_FLAG_DRDY ((uint8_t)0x0001) /*!< Data ready */ #define RNG_FLAG_CECS ((uint8_t)0x0002) /*!< Clock error current status */ #define RNG_FLAG_SECS ((uint8_t)0x0004) /*!< Seed error current status */ #define IS_RNG_GET_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_DRDY) || \ ((RNG_FLAG) == RNG_FLAG_CECS) || \ ((RNG_FLAG) == RNG_FLAG_SECS)) #define IS_RNG_CLEAR_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_CECS) || \ ((RNG_FLAG) == RNG_FLAG_SECS)) /** * @} */ /** @defgroup RNG_interrupts_definition * @{ */ #define RNG_IT_CEI ((uint8_t)0x20) /*!< Clock error interrupt */ #define RNG_IT_SEI ((uint8_t)0x40) /*!< Seed error interrupt */ #define IS_RNG_IT(IT) ((((IT) & (uint8_t)0x9F) == 0x00) && ((IT) != 0x00)) #define IS_RNG_GET_IT(RNG_IT) (((RNG_IT) == RNG_IT_CEI) || ((RNG_IT) == RNG_IT_SEI)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the RNG configuration to the default reset state *****/ void RNG_DeInit(void); /* Configuration function *****************************************************/ void RNG_Cmd(FunctionalState NewState); /* Get 32 bit Random number function ******************************************/ uint32_t RNG_GetRandomNumber(void); /* Interrupts and flags management functions **********************************/ void RNG_ITConfig(FunctionalState NewState); FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG); void RNG_ClearFlag(uint8_t RNG_FLAG); ITStatus RNG_GetITStatus(uint8_t RNG_IT); void RNG_ClearITPendingBit(uint8_t RNG_IT); #ifdef __cplusplus } #endif #endif /*__STM32F4xx_RNG_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rtc.h ================================================ /** ****************************************************************************** * @file stm32f4xx_rtc.h * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file contains all the functions prototypes for the RTC firmware * library. ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_RTC_H #define __STM32F4xx_RTC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup RTC * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief RTC Init structures definition */ typedef struct { uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format. This parameter can be a value of @ref RTC_Hour_Formats */ uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. This parameter must be set to a value lower than 0x7F */ uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. This parameter must be set to a value lower than 0x7FFF */ }RTC_InitTypeDef; /** * @brief RTC Time structure definition */ typedef struct { uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour. This parameter must be set to a value in the 0-12 range if the RTC_HourFormat_12 is selected or 0-23 range if the RTC_HourFormat_24 is selected. */ uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes. This parameter must be set to a value in the 0-59 range. */ uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds. This parameter must be set to a value in the 0-59 range. */ uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time. This parameter can be a value of @ref RTC_AM_PM_Definitions */ }RTC_TimeTypeDef; /** * @brief RTC Date structure definition */ typedef struct { uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay. This parameter can be a value of @ref RTC_WeekDay_Definitions */ uint8_t RTC_Month; /*!< Specifies the RTC Date Month (in BCD format). This parameter can be a value of @ref RTC_Month_Date_Definitions */ uint8_t RTC_Date; /*!< Specifies the RTC Date. This parameter must be set to a value in the 1-31 range. */ uint8_t RTC_Year; /*!< Specifies the RTC Date Year. This parameter must be set to a value in the 0-99 range. */ }RTC_DateTypeDef; /** * @brief RTC Alarm structure definition */ typedef struct { RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */ uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks. This parameter can be a value of @ref RTC_AlarmMask_Definitions */ uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range. If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */ }RTC_AlarmTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup RTC_Exported_Constants * @{ */ /** @defgroup RTC_Hour_Formats * @{ */ #define RTC_HourFormat_24 ((uint32_t)0x00000000) #define RTC_HourFormat_12 ((uint32_t)0x00000040) #define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \ ((FORMAT) == RTC_HourFormat_24)) /** * @} */ /** @defgroup RTC_Asynchronous_Predivider * @{ */ #define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F) /** * @} */ /** @defgroup RTC_Synchronous_Predivider * @{ */ #define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF) /** * @} */ /** @defgroup RTC_Time_Definitions * @{ */ #define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12)) #define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23) #define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59) #define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59) /** * @} */ /** @defgroup RTC_AM_PM_Definitions * @{ */ #define RTC_H12_AM ((uint8_t)0x00) #define RTC_H12_PM ((uint8_t)0x40) #define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM)) /** * @} */ /** @defgroup RTC_Year_Date_Definitions * @{ */ #define IS_RTC_YEAR(YEAR) ((YEAR) <= 99) /** * @} */ /** @defgroup RTC_Month_Date_Definitions * @{ */ /* Coded in BCD format */ #define RTC_Month_January ((uint8_t)0x01) #define RTC_Month_February ((uint8_t)0x02) #define RTC_Month_March ((uint8_t)0x03) #define RTC_Month_April ((uint8_t)0x04) #define RTC_Month_May ((uint8_t)0x05) #define RTC_Month_June ((uint8_t)0x06) #define RTC_Month_July ((uint8_t)0x07) #define RTC_Month_August ((uint8_t)0x08) #define RTC_Month_September ((uint8_t)0x09) #define RTC_Month_October ((uint8_t)0x10) #define RTC_Month_November ((uint8_t)0x11) #define RTC_Month_December ((uint8_t)0x12) #define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12)) #define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31)) /** * @} */ /** @defgroup RTC_WeekDay_Definitions * @{ */ #define RTC_Weekday_Monday ((uint8_t)0x01) #define RTC_Weekday_Tuesday ((uint8_t)0x02) #define RTC_Weekday_Wednesday ((uint8_t)0x03) #define RTC_Weekday_Thursday ((uint8_t)0x04) #define RTC_Weekday_Friday ((uint8_t)0x05) #define RTC_Weekday_Saturday ((uint8_t)0x06) #define RTC_Weekday_Sunday ((uint8_t)0x07) #define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ ((WEEKDAY) == RTC_Weekday_Tuesday) || \ ((WEEKDAY) == RTC_Weekday_Wednesday) || \ ((WEEKDAY) == RTC_Weekday_Thursday) || \ ((WEEKDAY) == RTC_Weekday_Friday) || \ ((WEEKDAY) == RTC_Weekday_Saturday) || \ ((WEEKDAY) == RTC_Weekday_Sunday)) /** * @} */ /** @defgroup RTC_Alarm_Definitions * @{ */ #define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31)) #define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ ((WEEKDAY) == RTC_Weekday_Tuesday) || \ ((WEEKDAY) == RTC_Weekday_Wednesday) || \ ((WEEKDAY) == RTC_Weekday_Thursday) || \ ((WEEKDAY) == RTC_Weekday_Friday) || \ ((WEEKDAY) == RTC_Weekday_Saturday) || \ ((WEEKDAY) == RTC_Weekday_Sunday)) /** * @} */ /** @defgroup RTC_AlarmDateWeekDay_Definitions * @{ */ #define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000) #define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000) #define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \ ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay)) /** * @} */ /** @defgroup RTC_AlarmMask_Definitions * @{ */ #define RTC_AlarmMask_None ((uint32_t)0x00000000) #define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000) #define RTC_AlarmMask_Hours ((uint32_t)0x00800000) #define RTC_AlarmMask_Minutes ((uint32_t)0x00008000) #define RTC_AlarmMask_Seconds ((uint32_t)0x00000080) #define RTC_AlarmMask_All ((uint32_t)0x80808080) #define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) /** * @} */ /** @defgroup RTC_Alarms_Definitions * @{ */ #define RTC_Alarm_A ((uint32_t)0x00000100) #define RTC_Alarm_B ((uint32_t)0x00000200) #define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B)) #define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET) /** * @} */ /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions * @{ */ #define RTC_AlarmSubSecondMask_All ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */ #define RTC_AlarmSubSecondMask_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm comparison. Only SS[0] is compared. */ #define RTC_AlarmSubSecondMask_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm comparison. Only SS[1:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm comparison. Only SS[2:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm comparison. Only SS[3:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm comparison. Only SS[4:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm comparison. Only SS[5:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm comparison. Only SS[6:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm comparison. Only SS[7:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm comparison. Only SS[8:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm comparison. Only SS[9:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm comparison. Only SS[10:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm comparison.Only SS[11:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm comparison. Only SS[12:0] are compared */ #define RTC_AlarmSubSecondMask_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm comparison.Only SS[13:0] are compared */ #define RTC_AlarmSubSecondMask_None ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match to activate alarm. */ #define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14) || \ ((MASK) == RTC_AlarmSubSecondMask_None)) /** * @} */ /** @defgroup RTC_Alarm_Sub_Seconds_Value * @{ */ #define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF) /** * @} */ /** @defgroup RTC_Wakeup_Timer_Definitions * @{ */ #define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000) #define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001) #define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002) #define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003) #define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004) #define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006) #define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \ ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \ ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \ ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \ ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \ ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits)) #define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) /** * @} */ /** @defgroup RTC_Time_Stamp_Edges_definitions * @{ */ #define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000) #define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008) #define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \ ((EDGE) == RTC_TimeStampEdge_Falling)) /** * @} */ /** @defgroup RTC_Output_selection_Definitions * @{ */ #define RTC_Output_Disable ((uint32_t)0x00000000) #define RTC_Output_AlarmA ((uint32_t)0x00200000) #define RTC_Output_AlarmB ((uint32_t)0x00400000) #define RTC_Output_WakeUp ((uint32_t)0x00600000) #define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \ ((OUTPUT) == RTC_Output_AlarmA) || \ ((OUTPUT) == RTC_Output_AlarmB) || \ ((OUTPUT) == RTC_Output_WakeUp)) /** * @} */ /** @defgroup RTC_Output_Polarity_Definitions * @{ */ #define RTC_OutputPolarity_High ((uint32_t)0x00000000) #define RTC_OutputPolarity_Low ((uint32_t)0x00100000) #define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \ ((POL) == RTC_OutputPolarity_Low)) /** * @} */ /** @defgroup RTC_Digital_Calibration_Definitions * @{ */ #define RTC_CalibSign_Positive ((uint32_t)0x00000000) #define RTC_CalibSign_Negative ((uint32_t)0x00000080) #define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \ ((SIGN) == RTC_CalibSign_Negative)) #define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20) /** * @} */ /** @defgroup RTC_Calib_Output_selection_Definitions * @{ */ #define RTC_CalibOutput_512Hz ((uint32_t)0x00000000) #define RTC_CalibOutput_1Hz ((uint32_t)0x00080000) #define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \ ((OUTPUT) == RTC_CalibOutput_1Hz)) /** * @} */ /** @defgroup RTC_Smooth_calib_period_Definitions * @{ */ #define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation period is 32s, else 2exp20 RTCCLK seconds */ #define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation period is 16s, else 2exp19 RTCCLK seconds */ #define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation period is 8s, else 2exp18 RTCCLK seconds */ #define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \ ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \ ((PERIOD) == RTC_SmoothCalibPeriod_8sec)) /** * @} */ /** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions * @{ */ #define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added during a X -second window = Y - CALM[8:0]. with Y = 512, 256, 128 when X = 32, 16, 8 */ #define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited during a 32-second window = CALM[8:0]. */ #define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \ ((PLUS) == RTC_SmoothCalibPlusPulses_Reset)) /** * @} */ /** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions * @{ */ #define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF) /** * @} */ /** @defgroup RTC_DayLightSaving_Definitions * @{ */ #define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000) #define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000) #define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \ ((SAVE) == RTC_DayLightSaving_ADD1H)) #define RTC_StoreOperation_Reset ((uint32_t)0x00000000) #define RTC_StoreOperation_Set ((uint32_t)0x00040000) #define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \ ((OPERATION) == RTC_StoreOperation_Set)) /** * @} */ /** @defgroup RTC_Tamper_Trigger_Definitions * @{ */ #define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000) #define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001) #define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000) #define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001) #define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \ ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \ ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \ ((TRIGGER) == RTC_TamperTrigger_HighLevel)) /** * @} */ /** @defgroup RTC_Tamper_Filter_Definitions * @{ */ #define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */ #define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2 consecutive samples at the active level */ #define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4 consecutive samples at the active level */ #define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8 consecutive samples at the active leve. */ #define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \ ((FILTER) == RTC_TamperFilter_2Sample) || \ ((FILTER) == RTC_TamperFilter_4Sample) || \ ((FILTER) == RTC_TamperFilter_8Sample)) /** * @} */ /** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions * @{ */ #define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ #define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */ #define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */ #define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */ #define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048 */ #define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024 */ #define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 512 */ #define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */ #define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256)) /** * @} */ /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions * @{ */ #define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ #define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */ #define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */ #define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */ #define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \ ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \ ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \ ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK)) /** * @} */ /** @defgroup RTC_Tamper_Pins_Definitions * @{ */ #define RTC_Tamper_1 RTC_TAFCR_TAMP1E #define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1)) /** * @} */ /** @defgroup RTC_Tamper_Pin_Selection * @{ */ #define RTC_TamperPin_PC13 ((uint32_t)0x00000000) #define RTC_TamperPin_PI8 ((uint32_t)0x00010000) #define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TamperPin_PC13) || \ ((PIN) == RTC_TamperPin_PI8)) /** * @} */ /** @defgroup RTC_TimeStamp_Pin_Selection * @{ */ #define RTC_TimeStampPin_PC13 ((uint32_t)0x00000000) #define RTC_TimeStampPin_PI8 ((uint32_t)0x00020000) #define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TimeStampPin_PC13) || \ ((PIN) == RTC_TimeStampPin_PI8)) /** * @} */ /** @defgroup RTC_Output_Type_ALARM_OUT * @{ */ #define RTC_OutputType_OpenDrain ((uint32_t)0x00000000) #define RTC_OutputType_PushPull ((uint32_t)0x00040000) #define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \ ((TYPE) == RTC_OutputType_PushPull)) /** * @} */ /** @defgroup RTC_Add_1_Second_Parameter_Definitions * @{ */ #define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000) #define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000) #define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \ ((SEL) == RTC_ShiftAdd1S_Set)) /** * @} */ /** @defgroup RTC_Substract_Fraction_Of_Second_Value * @{ */ #define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF) /** * @} */ /** @defgroup RTC_Backup_Registers_Definitions * @{ */ #define RTC_BKP_DR0 ((uint32_t)0x00000000) #define RTC_BKP_DR1 ((uint32_t)0x00000001) #define RTC_BKP_DR2 ((uint32_t)0x00000002) #define RTC_BKP_DR3 ((uint32_t)0x00000003) #define RTC_BKP_DR4 ((uint32_t)0x00000004) #define RTC_BKP_DR5 ((uint32_t)0x00000005) #define RTC_BKP_DR6 ((uint32_t)0x00000006) #define RTC_BKP_DR7 ((uint32_t)0x00000007) #define RTC_BKP_DR8 ((uint32_t)0x00000008) #define RTC_BKP_DR9 ((uint32_t)0x00000009) #define RTC_BKP_DR10 ((uint32_t)0x0000000A) #define RTC_BKP_DR11 ((uint32_t)0x0000000B) #define RTC_BKP_DR12 ((uint32_t)0x0000000C) #define RTC_BKP_DR13 ((uint32_t)0x0000000D) #define RTC_BKP_DR14 ((uint32_t)0x0000000E) #define RTC_BKP_DR15 ((uint32_t)0x0000000F) #define RTC_BKP_DR16 ((uint32_t)0x00000010) #define RTC_BKP_DR17 ((uint32_t)0x00000011) #define RTC_BKP_DR18 ((uint32_t)0x00000012) #define RTC_BKP_DR19 ((uint32_t)0x00000013) #define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \ ((BKP) == RTC_BKP_DR1) || \ ((BKP) == RTC_BKP_DR2) || \ ((BKP) == RTC_BKP_DR3) || \ ((BKP) == RTC_BKP_DR4) || \ ((BKP) == RTC_BKP_DR5) || \ ((BKP) == RTC_BKP_DR6) || \ ((BKP) == RTC_BKP_DR7) || \ ((BKP) == RTC_BKP_DR8) || \ ((BKP) == RTC_BKP_DR9) || \ ((BKP) == RTC_BKP_DR10) || \ ((BKP) == RTC_BKP_DR11) || \ ((BKP) == RTC_BKP_DR12) || \ ((BKP) == RTC_BKP_DR13) || \ ((BKP) == RTC_BKP_DR14) || \ ((BKP) == RTC_BKP_DR15) || \ ((BKP) == RTC_BKP_DR16) || \ ((BKP) == RTC_BKP_DR17) || \ ((BKP) == RTC_BKP_DR18) || \ ((BKP) == RTC_BKP_DR19)) /** * @} */ /** @defgroup RTC_Input_parameter_format_definitions * @{ */ #define RTC_Format_BIN ((uint32_t)0x000000000) #define RTC_Format_BCD ((uint32_t)0x000000001) #define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD)) /** * @} */ /** @defgroup RTC_Flags_Definitions * @{ */ #define RTC_FLAG_RECALPF ((uint32_t)0x00010000) #define RTC_FLAG_TAMP1F ((uint32_t)0x00002000) #define RTC_FLAG_TSOVF ((uint32_t)0x00001000) #define RTC_FLAG_TSF ((uint32_t)0x00000800) #define RTC_FLAG_WUTF ((uint32_t)0x00000400) #define RTC_FLAG_ALRBF ((uint32_t)0x00000200) #define RTC_FLAG_ALRAF ((uint32_t)0x00000100) #define RTC_FLAG_INITF ((uint32_t)0x00000040) #define RTC_FLAG_RSF ((uint32_t)0x00000020) #define RTC_FLAG_INITS ((uint32_t)0x00000010) #define RTC_FLAG_SHPF ((uint32_t)0x00000008) #define RTC_FLAG_WUTWF ((uint32_t)0x00000004) #define RTC_FLAG_ALRBWF ((uint32_t)0x00000002) #define RTC_FLAG_ALRAWF ((uint32_t)0x00000001) #define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \ ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \ ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \ ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \ ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \ ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_RECALPF) || \ ((FLAG) == RTC_FLAG_SHPF)) #define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET)) /** * @} */ /** @defgroup RTC_Interrupts_Definitions * @{ */ #define RTC_IT_TS ((uint32_t)0x00008000) #define RTC_IT_WUT ((uint32_t)0x00004000) #define RTC_IT_ALRB ((uint32_t)0x00002000) #define RTC_IT_ALRA ((uint32_t)0x00001000) #define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */ #define RTC_IT_TAMP1 ((uint32_t)0x00020000) #define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET)) #define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \ ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \ ((IT) == RTC_IT_TAMP1)) #define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFD0FFF) == (uint32_t)RESET)) /** * @} */ /** @defgroup RTC_Legacy * @{ */ #define RTC_DigitalCalibConfig RTC_CoarseCalibConfig #define RTC_DigitalCalibCmd RTC_CoarseCalibCmd /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the RTC configuration to the default reset state *****/ ErrorStatus RTC_DeInit(void); /* Initialization and Configuration functions *********************************/ ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct); void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct); void RTC_WriteProtectionCmd(FunctionalState NewState); ErrorStatus RTC_EnterInitMode(void); void RTC_ExitInitMode(void); ErrorStatus RTC_WaitForSynchro(void); ErrorStatus RTC_RefClockCmd(FunctionalState NewState); void RTC_BypassShadowCmd(FunctionalState NewState); /* Time and Date configuration functions **************************************/ ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct); void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); uint32_t RTC_GetSubSecond(void); ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct); void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); /* Alarms (Alarm A and Alarm B) configuration functions **********************/ void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct); void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState); void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask); uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm); /* WakeUp Timer configuration functions ***************************************/ void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock); void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter); uint32_t RTC_GetWakeUpCounter(void); ErrorStatus RTC_WakeUpCmd(FunctionalState NewState); /* Daylight Saving configuration functions ************************************/ void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation); uint32_t RTC_GetStoreOperation(void); /* Output pin Configuration function ******************************************/ void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity); /* Digital Calibration configuration functions *********************************/ ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value); ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState); void RTC_CalibOutputCmd(FunctionalState NewState); void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput); ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, uint32_t RTC_SmoothCalibPlusPulses, uint32_t RTC_SmouthCalibMinusPulsesValue); /* TimeStamp configuration functions ******************************************/ void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState); void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, RTC_DateTypeDef* RTC_StampDateStruct); uint32_t RTC_GetTimeStampSubSecond(void); /* Tampers configuration functions ********************************************/ void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger); void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState); void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter); void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq); void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration); void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState); void RTC_TamperPullUpCmd(FunctionalState NewState); /* Backup Data Registers configuration functions ******************************/ void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data); uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR); /* RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions ******************************************************************/ void RTC_TamperPinSelection(uint32_t RTC_TamperPin); void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin); void RTC_OutputTypeConfig(uint32_t RTC_OutputType); /* RTC_Shift_control_synchonisation_functions *********************************/ ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS); /* Interrupts and flags management functions **********************************/ void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState); FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG); void RTC_ClearFlag(uint32_t RTC_FLAG); ITStatus RTC_GetITStatus(uint32_t RTC_IT); void RTC_ClearITPendingBit(uint32_t RTC_IT); #ifdef __cplusplus } #endif #endif /*__STM32F4xx_RTC_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sdio.h ================================================ /** ****************************************************************************** * @file stm32f4xx_sdio.h * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file contains all the functions prototypes for the SDIO firmware * library. ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_SDIO_H #define __STM32F4xx_SDIO_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup SDIO * @{ */ /* Exported types ------------------------------------------------------------*/ typedef struct { uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. This parameter can be a value of @ref SDIO_Clock_Edge */ uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is enabled or disabled. This parameter can be a value of @ref SDIO_Clock_Bypass */ uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or disabled when the bus is idle. This parameter can be a value of @ref SDIO_Clock_Power_Save */ uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width. This parameter can be a value of @ref SDIO_Bus_Wide */ uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. This parameter can be a value between 0x00 and 0xFF. */ } SDIO_InitTypeDef; typedef struct { uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing the command to the command register */ uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */ uint32_t SDIO_Response; /*!< Specifies the SDIO response type. This parameter can be a value of @ref SDIO_Response_Type */ uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled. This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) is enabled or disabled. This parameter can be a value of @ref SDIO_CPSM_State */ } SDIO_CmdInitTypeDef; typedef struct { uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */ uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer. This parameter can be a value of @ref SDIO_Data_Block_Size */ uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer is a read or write. This parameter can be a value of @ref SDIO_Transfer_Direction */ uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode. This parameter can be a value of @ref SDIO_Transfer_Type */ uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) is enabled or disabled. This parameter can be a value of @ref SDIO_DPSM_State */ } SDIO_DataInitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup SDIO_Exported_Constants * @{ */ /** @defgroup SDIO_Clock_Edge * @{ */ #define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) #define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \ ((EDGE) == SDIO_ClockEdge_Falling)) /** * @} */ /** @defgroup SDIO_Clock_Bypass * @{ */ #define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) #define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \ ((BYPASS) == SDIO_ClockBypass_Enable)) /** * @} */ /** @defgroup SDIO_Clock_Power_Save * @{ */ #define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) #define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \ ((SAVE) == SDIO_ClockPowerSave_Enable)) /** * @} */ /** @defgroup SDIO_Bus_Wide * @{ */ #define SDIO_BusWide_1b ((uint32_t)0x00000000) #define SDIO_BusWide_4b ((uint32_t)0x00000800) #define SDIO_BusWide_8b ((uint32_t)0x00001000) #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \ ((WIDE) == SDIO_BusWide_8b)) /** * @} */ /** @defgroup SDIO_Hardware_Flow_Control * @{ */ #define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) #define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \ ((CONTROL) == SDIO_HardwareFlowControl_Enable)) /** * @} */ /** @defgroup SDIO_Power_State * @{ */ #define SDIO_PowerState_OFF ((uint32_t)0x00000000) #define SDIO_PowerState_ON ((uint32_t)0x00000003) #define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) /** * @} */ /** @defgroup SDIO_Interrupt_sources * @{ */ #define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) #define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) #define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) #define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) #define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) #define SDIO_IT_RXOVERR ((uint32_t)0x00000020) #define SDIO_IT_CMDREND ((uint32_t)0x00000040) #define SDIO_IT_CMDSENT ((uint32_t)0x00000080) #define SDIO_IT_DATAEND ((uint32_t)0x00000100) #define SDIO_IT_STBITERR ((uint32_t)0x00000200) #define SDIO_IT_DBCKEND ((uint32_t)0x00000400) #define SDIO_IT_CMDACT ((uint32_t)0x00000800) #define SDIO_IT_TXACT ((uint32_t)0x00001000) #define SDIO_IT_RXACT ((uint32_t)0x00002000) #define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) #define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) #define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) #define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) #define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) #define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) #define SDIO_IT_TXDAVL ((uint32_t)0x00100000) #define SDIO_IT_RXDAVL ((uint32_t)0x00200000) #define SDIO_IT_SDIOIT ((uint32_t)0x00400000) #define SDIO_IT_CEATAEND ((uint32_t)0x00800000) #define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00)) /** * @} */ /** @defgroup SDIO_Command_Index * @{ */ #define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) /** * @} */ /** @defgroup SDIO_Response_Type * @{ */ #define SDIO_Response_No ((uint32_t)0x00000000) #define SDIO_Response_Short ((uint32_t)0x00000040) #define SDIO_Response_Long ((uint32_t)0x000000C0) #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \ ((RESPONSE) == SDIO_Response_Short) || \ ((RESPONSE) == SDIO_Response_Long)) /** * @} */ /** @defgroup SDIO_Wait_Interrupt_State * @{ */ #define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */ #define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */ #define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */ #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \ ((WAIT) == SDIO_Wait_Pend)) /** * @} */ /** @defgroup SDIO_CPSM_State * @{ */ #define SDIO_CPSM_Disable ((uint32_t)0x00000000) #define SDIO_CPSM_Enable ((uint32_t)0x00000400) #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable)) /** * @} */ /** @defgroup SDIO_Response_Registers * @{ */ #define SDIO_RESP1 ((uint32_t)0x00000000) #define SDIO_RESP2 ((uint32_t)0x00000004) #define SDIO_RESP3 ((uint32_t)0x00000008) #define SDIO_RESP4 ((uint32_t)0x0000000C) #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \ ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4)) /** * @} */ /** @defgroup SDIO_Data_Length * @{ */ #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) /** * @} */ /** @defgroup SDIO_Data_Block_Size * @{ */ #define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) #define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) #define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) #define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) #define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) #define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) #define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) #define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) #define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) #define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) #define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) #define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) #define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) #define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) #define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \ ((SIZE) == SDIO_DataBlockSize_2b) || \ ((SIZE) == SDIO_DataBlockSize_4b) || \ ((SIZE) == SDIO_DataBlockSize_8b) || \ ((SIZE) == SDIO_DataBlockSize_16b) || \ ((SIZE) == SDIO_DataBlockSize_32b) || \ ((SIZE) == SDIO_DataBlockSize_64b) || \ ((SIZE) == SDIO_DataBlockSize_128b) || \ ((SIZE) == SDIO_DataBlockSize_256b) || \ ((SIZE) == SDIO_DataBlockSize_512b) || \ ((SIZE) == SDIO_DataBlockSize_1024b) || \ ((SIZE) == SDIO_DataBlockSize_2048b) || \ ((SIZE) == SDIO_DataBlockSize_4096b) || \ ((SIZE) == SDIO_DataBlockSize_8192b) || \ ((SIZE) == SDIO_DataBlockSize_16384b)) /** * @} */ /** @defgroup SDIO_Transfer_Direction * @{ */ #define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) #define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \ ((DIR) == SDIO_TransferDir_ToSDIO)) /** * @} */ /** @defgroup SDIO_Transfer_Type * @{ */ #define SDIO_TransferMode_Block ((uint32_t)0x00000000) #define SDIO_TransferMode_Stream ((uint32_t)0x00000004) #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \ ((MODE) == SDIO_TransferMode_Block)) /** * @} */ /** @defgroup SDIO_DPSM_State * @{ */ #define SDIO_DPSM_Disable ((uint32_t)0x00000000) #define SDIO_DPSM_Enable ((uint32_t)0x00000001) #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable)) /** * @} */ /** @defgroup SDIO_Flags * @{ */ #define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) #define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) #define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) #define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) #define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) #define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) #define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) #define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) #define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) #define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) #define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) #define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) #define SDIO_FLAG_TXACT ((uint32_t)0x00001000) #define SDIO_FLAG_RXACT ((uint32_t)0x00002000) #define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) #define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) #define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) #define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) #define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) #define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) #define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) #define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) #define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) #define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) #define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \ ((FLAG) == SDIO_FLAG_DCRCFAIL) || \ ((FLAG) == SDIO_FLAG_CTIMEOUT) || \ ((FLAG) == SDIO_FLAG_DTIMEOUT) || \ ((FLAG) == SDIO_FLAG_TXUNDERR) || \ ((FLAG) == SDIO_FLAG_RXOVERR) || \ ((FLAG) == SDIO_FLAG_CMDREND) || \ ((FLAG) == SDIO_FLAG_CMDSENT) || \ ((FLAG) == SDIO_FLAG_DATAEND) || \ ((FLAG) == SDIO_FLAG_STBITERR) || \ ((FLAG) == SDIO_FLAG_DBCKEND) || \ ((FLAG) == SDIO_FLAG_CMDACT) || \ ((FLAG) == SDIO_FLAG_TXACT) || \ ((FLAG) == SDIO_FLAG_RXACT) || \ ((FLAG) == SDIO_FLAG_TXFIFOHE) || \ ((FLAG) == SDIO_FLAG_RXFIFOHF) || \ ((FLAG) == SDIO_FLAG_TXFIFOF) || \ ((FLAG) == SDIO_FLAG_RXFIFOF) || \ ((FLAG) == SDIO_FLAG_TXFIFOE) || \ ((FLAG) == SDIO_FLAG_RXFIFOE) || \ ((FLAG) == SDIO_FLAG_TXDAVL) || \ ((FLAG) == SDIO_FLAG_RXDAVL) || \ ((FLAG) == SDIO_FLAG_SDIOIT) || \ ((FLAG) == SDIO_FLAG_CEATAEND)) #define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00)) #define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \ ((IT) == SDIO_IT_DCRCFAIL) || \ ((IT) == SDIO_IT_CTIMEOUT) || \ ((IT) == SDIO_IT_DTIMEOUT) || \ ((IT) == SDIO_IT_TXUNDERR) || \ ((IT) == SDIO_IT_RXOVERR) || \ ((IT) == SDIO_IT_CMDREND) || \ ((IT) == SDIO_IT_CMDSENT) || \ ((IT) == SDIO_IT_DATAEND) || \ ((IT) == SDIO_IT_STBITERR) || \ ((IT) == SDIO_IT_DBCKEND) || \ ((IT) == SDIO_IT_CMDACT) || \ ((IT) == SDIO_IT_TXACT) || \ ((IT) == SDIO_IT_RXACT) || \ ((IT) == SDIO_IT_TXFIFOHE) || \ ((IT) == SDIO_IT_RXFIFOHF) || \ ((IT) == SDIO_IT_TXFIFOF) || \ ((IT) == SDIO_IT_RXFIFOF) || \ ((IT) == SDIO_IT_TXFIFOE) || \ ((IT) == SDIO_IT_RXFIFOE) || \ ((IT) == SDIO_IT_TXDAVL) || \ ((IT) == SDIO_IT_RXDAVL) || \ ((IT) == SDIO_IT_SDIOIT) || \ ((IT) == SDIO_IT_CEATAEND)) #define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00)) /** * @} */ /** @defgroup SDIO_Read_Wait_Mode * @{ */ #define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000000) #define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000001) #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \ ((MODE) == SDIO_ReadWaitMode_DATA2)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the SDIO configuration to the default reset state ****/ void SDIO_DeInit(void); /* Initialization and Configuration functions *********************************/ void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); void SDIO_ClockCmd(FunctionalState NewState); void SDIO_SetPowerState(uint32_t SDIO_PowerState); uint32_t SDIO_GetPowerState(void); /* Command path state machine (CPSM) management functions *********************/ void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); uint8_t SDIO_GetCommandResponse(void); uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); /* Data path state machine (DPSM) management functions ************************/ void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); uint32_t SDIO_GetDataCounter(void); uint32_t SDIO_ReadData(void); void SDIO_WriteData(uint32_t Data); uint32_t SDIO_GetFIFOCount(void); /* SDIO IO Cards mode management functions ************************************/ void SDIO_StartSDIOReadWait(FunctionalState NewState); void SDIO_StopSDIOReadWait(FunctionalState NewState); void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); void SDIO_SetSDIOOperation(FunctionalState NewState); void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); /* CE-ATA mode management functions *******************************************/ void SDIO_CommandCompletionCmd(FunctionalState NewState); void SDIO_CEATAITCmd(FunctionalState NewState); void SDIO_SendCEATACmd(FunctionalState NewState); /* DMA transfers management functions *****************************************/ void SDIO_DMACmd(FunctionalState NewState); /* Interrupts and flags management functions **********************************/ void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState); FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG); void SDIO_ClearFlag(uint32_t SDIO_FLAG); ITStatus SDIO_GetITStatus(uint32_t SDIO_IT); void SDIO_ClearITPendingBit(uint32_t SDIO_IT); #ifdef __cplusplus } #endif #endif /* __STM32F4xx_SDIO_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_spi.h ================================================ /** ****************************************************************************** * @file stm32f4xx_spi.h * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file contains all the functions prototypes for the SPI * firmware library. ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_SPI_H #define __STM32F4xx_SPI_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup SPI * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief SPI Init structure definition */ typedef struct { uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. This parameter can be a value of @ref SPI_data_direction */ uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. This parameter can be a value of @ref SPI_mode */ uint16_t SPI_DataSize; /*!< Specifies the SPI data size. This parameter can be a value of @ref SPI_data_size */ uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. This parameter can be a value of @ref SPI_Clock_Polarity */ uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. This parameter can be a value of @ref SPI_Clock_Phase */ uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. This parameter can be a value of @ref SPI_Slave_Select_management */ uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be used to configure the transmit and receive SCK clock. This parameter can be a value of @ref SPI_BaudRate_Prescaler @note The communication clock is derived from the master clock. The slave clock does not need to be set. */ uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of @ref SPI_MSB_LSB_transmission */ uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ }SPI_InitTypeDef; /** * @brief I2S Init structure definition */ typedef struct { uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. This parameter can be a value of @ref I2S_Mode */ uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. This parameter can be a value of @ref I2S_Standard */ uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. This parameter can be a value of @ref I2S_Data_Format */ uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. This parameter can be a value of @ref I2S_MCLK_Output */ uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. This parameter can be a value of @ref I2S_Audio_Frequency */ uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. This parameter can be a value of @ref I2S_Clock_Polarity */ }I2S_InitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup SPI_Exported_Constants * @{ */ #define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ ((PERIPH) == SPI2) || \ ((PERIPH) == SPI3)) #define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \ ((PERIPH) == SPI2) || \ ((PERIPH) == SPI3) || \ ((PERIPH) == I2S2ext) || \ ((PERIPH) == I2S3ext)) #define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ ((PERIPH) == SPI3)) #define IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || \ ((PERIPH) == SPI3) || \ ((PERIPH) == I2S2ext) || \ ((PERIPH) == I2S3ext)) #define IS_I2S_EXT_PERIPH(PERIPH) (((PERIPH) == I2S2ext) || \ ((PERIPH) == I2S3ext)) /** @defgroup SPI_data_direction * @{ */ #define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) #define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) #define SPI_Direction_1Line_Rx ((uint16_t)0x8000) #define SPI_Direction_1Line_Tx ((uint16_t)0xC000) #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ ((MODE) == SPI_Direction_2Lines_RxOnly) || \ ((MODE) == SPI_Direction_1Line_Rx) || \ ((MODE) == SPI_Direction_1Line_Tx)) /** * @} */ /** @defgroup SPI_mode * @{ */ #define SPI_Mode_Master ((uint16_t)0x0104) #define SPI_Mode_Slave ((uint16_t)0x0000) #define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ ((MODE) == SPI_Mode_Slave)) /** * @} */ /** @defgroup SPI_data_size * @{ */ #define SPI_DataSize_16b ((uint16_t)0x0800) #define SPI_DataSize_8b ((uint16_t)0x0000) #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ ((DATASIZE) == SPI_DataSize_8b)) /** * @} */ /** @defgroup SPI_Clock_Polarity * @{ */ #define SPI_CPOL_Low ((uint16_t)0x0000) #define SPI_CPOL_High ((uint16_t)0x0002) #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ ((CPOL) == SPI_CPOL_High)) /** * @} */ /** @defgroup SPI_Clock_Phase * @{ */ #define SPI_CPHA_1Edge ((uint16_t)0x0000) #define SPI_CPHA_2Edge ((uint16_t)0x0001) #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ ((CPHA) == SPI_CPHA_2Edge)) /** * @} */ /** @defgroup SPI_Slave_Select_management * @{ */ #define SPI_NSS_Soft ((uint16_t)0x0200) #define SPI_NSS_Hard ((uint16_t)0x0000) #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ ((NSS) == SPI_NSS_Hard)) /** * @} */ /** @defgroup SPI_BaudRate_Prescaler * @{ */ #define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) #define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) #define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) #define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) #define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) #define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) #define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) #define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ ((PRESCALER) == SPI_BaudRatePrescaler_256)) /** * @} */ /** @defgroup SPI_MSB_LSB_transmission * @{ */ #define SPI_FirstBit_MSB ((uint16_t)0x0000) #define SPI_FirstBit_LSB ((uint16_t)0x0080) #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ ((BIT) == SPI_FirstBit_LSB)) /** * @} */ /** @defgroup SPI_I2S_Mode * @{ */ #define I2S_Mode_SlaveTx ((uint16_t)0x0000) #define I2S_Mode_SlaveRx ((uint16_t)0x0100) #define I2S_Mode_MasterTx ((uint16_t)0x0200) #define I2S_Mode_MasterRx ((uint16_t)0x0300) #define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ ((MODE) == I2S_Mode_SlaveRx) || \ ((MODE) == I2S_Mode_MasterTx)|| \ ((MODE) == I2S_Mode_MasterRx)) /** * @} */ /** @defgroup SPI_I2S_Standard * @{ */ #define I2S_Standard_Phillips ((uint16_t)0x0000) #define I2S_Standard_MSB ((uint16_t)0x0010) #define I2S_Standard_LSB ((uint16_t)0x0020) #define I2S_Standard_PCMShort ((uint16_t)0x0030) #define I2S_Standard_PCMLong ((uint16_t)0x00B0) #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ ((STANDARD) == I2S_Standard_MSB) || \ ((STANDARD) == I2S_Standard_LSB) || \ ((STANDARD) == I2S_Standard_PCMShort) || \ ((STANDARD) == I2S_Standard_PCMLong)) /** * @} */ /** @defgroup SPI_I2S_Data_Format * @{ */ #define I2S_DataFormat_16b ((uint16_t)0x0000) #define I2S_DataFormat_16bextended ((uint16_t)0x0001) #define I2S_DataFormat_24b ((uint16_t)0x0003) #define I2S_DataFormat_32b ((uint16_t)0x0005) #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ ((FORMAT) == I2S_DataFormat_16bextended) || \ ((FORMAT) == I2S_DataFormat_24b) || \ ((FORMAT) == I2S_DataFormat_32b)) /** * @} */ /** @defgroup SPI_I2S_MCLK_Output * @{ */ #define I2S_MCLKOutput_Enable ((uint16_t)0x0200) #define I2S_MCLKOutput_Disable ((uint16_t)0x0000) #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ ((OUTPUT) == I2S_MCLKOutput_Disable)) /** * @} */ /** @defgroup SPI_I2S_Audio_Frequency * @{ */ #define I2S_AudioFreq_192k ((uint32_t)192000) #define I2S_AudioFreq_96k ((uint32_t)96000) #define I2S_AudioFreq_48k ((uint32_t)48000) #define I2S_AudioFreq_44k ((uint32_t)44100) #define I2S_AudioFreq_32k ((uint32_t)32000) #define I2S_AudioFreq_22k ((uint32_t)22050) #define I2S_AudioFreq_16k ((uint32_t)16000) #define I2S_AudioFreq_11k ((uint32_t)11025) #define I2S_AudioFreq_8k ((uint32_t)8000) #define I2S_AudioFreq_Default ((uint32_t)2) #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ ((FREQ) <= I2S_AudioFreq_192k)) || \ ((FREQ) == I2S_AudioFreq_Default)) /** * @} */ /** @defgroup SPI_I2S_Clock_Polarity * @{ */ #define I2S_CPOL_Low ((uint16_t)0x0000) #define I2S_CPOL_High ((uint16_t)0x0008) #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ ((CPOL) == I2S_CPOL_High)) /** * @} */ /** @defgroup SPI_I2S_DMA_transfer_requests * @{ */ #define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) #define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) #define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) /** * @} */ /** @defgroup SPI_NSS_internal_software_management * @{ */ #define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) #define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) #define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ ((INTERNAL) == SPI_NSSInternalSoft_Reset)) /** * @} */ /** @defgroup SPI_CRC_Transmit_Receive * @{ */ #define SPI_CRC_Tx ((uint8_t)0x00) #define SPI_CRC_Rx ((uint8_t)0x01) #define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) /** * @} */ /** @defgroup SPI_direction_transmit_receive * @{ */ #define SPI_Direction_Rx ((uint16_t)0xBFFF) #define SPI_Direction_Tx ((uint16_t)0x4000) #define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ ((DIRECTION) == SPI_Direction_Tx)) /** * @} */ /** @defgroup SPI_I2S_interrupts_definition * @{ */ #define SPI_I2S_IT_TXE ((uint8_t)0x71) #define SPI_I2S_IT_RXNE ((uint8_t)0x60) #define SPI_I2S_IT_ERR ((uint8_t)0x50) #define I2S_IT_UDR ((uint8_t)0x53) #define SPI_I2S_IT_TIFRFE ((uint8_t)0x58) #define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ ((IT) == SPI_I2S_IT_RXNE) || \ ((IT) == SPI_I2S_IT_ERR)) #define SPI_I2S_IT_OVR ((uint8_t)0x56) #define SPI_IT_MODF ((uint8_t)0x55) #define SPI_IT_CRCERR ((uint8_t)0x54) #define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) #define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE)|| ((IT) == SPI_I2S_IT_TXE) || \ ((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \ ((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\ ((IT) == SPI_I2S_IT_TIFRFE)) /** * @} */ /** @defgroup SPI_I2S_flags_definition * @{ */ #define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) #define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) #define I2S_FLAG_CHSIDE ((uint16_t)0x0004) #define I2S_FLAG_UDR ((uint16_t)0x0008) #define SPI_FLAG_CRCERR ((uint16_t)0x0010) #define SPI_FLAG_MODF ((uint16_t)0x0020) #define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) #define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) #define SPI_I2S_FLAG_TIFRFE ((uint16_t)0x0100) #define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) #define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \ ((FLAG) == SPI_I2S_FLAG_TIFRFE)) /** * @} */ /** @defgroup SPI_CRC_polynomial * @{ */ #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) /** * @} */ /** @defgroup SPI_I2S_Legacy * @{ */ #define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx #define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx #define SPI_IT_TXE SPI_I2S_IT_TXE #define SPI_IT_RXNE SPI_I2S_IT_RXNE #define SPI_IT_ERR SPI_I2S_IT_ERR #define SPI_IT_OVR SPI_I2S_IT_OVR #define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE #define SPI_FLAG_TXE SPI_I2S_FLAG_TXE #define SPI_FLAG_OVR SPI_I2S_FLAG_OVR #define SPI_FLAG_BSY SPI_I2S_FLAG_BSY #define SPI_DeInit SPI_I2S_DeInit #define SPI_ITConfig SPI_I2S_ITConfig #define SPI_DMACmd SPI_I2S_DMACmd #define SPI_SendData SPI_I2S_SendData #define SPI_ReceiveData SPI_I2S_ReceiveData #define SPI_GetFlagStatus SPI_I2S_GetFlagStatus #define SPI_ClearFlag SPI_I2S_ClearFlag #define SPI_GetITStatus SPI_I2S_GetITStatus #define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the SPI configuration to the default reset state *****/ void SPI_I2S_DeInit(SPI_TypeDef* SPIx); /* Initialization and Configuration functions *********************************/ void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct); /* Data transfers functions ***************************************************/ void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); /* Hardware CRC Calculation functions *****************************************/ void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); void SPI_TransmitCRC(SPI_TypeDef* SPIx); uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); /* DMA transfers management functions *****************************************/ void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); /* Interrupts and flags management functions **********************************/ void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); #ifdef __cplusplus } #endif #endif /*__STM32F4xx_SPI_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_syscfg.h ================================================ /** ****************************************************************************** * @file stm32f4xx_syscfg.h * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file contains all the functions prototypes for the SYSCFG firmware * library. ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_SYSCFG_H #define __STM32F4xx_SYSCFG_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup SYSCFG * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup SYSCFG_Exported_Constants * @{ */ /** @defgroup SYSCFG_EXTI_Port_Sources * @{ */ #define EXTI_PortSourceGPIOA ((uint8_t)0x00) #define EXTI_PortSourceGPIOB ((uint8_t)0x01) #define EXTI_PortSourceGPIOC ((uint8_t)0x02) #define EXTI_PortSourceGPIOD ((uint8_t)0x03) #define EXTI_PortSourceGPIOE ((uint8_t)0x04) #define EXTI_PortSourceGPIOF ((uint8_t)0x05) #define EXTI_PortSourceGPIOG ((uint8_t)0x06) #define EXTI_PortSourceGPIOH ((uint8_t)0x07) #define EXTI_PortSourceGPIOI ((uint8_t)0x08) #define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \ ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \ ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \ ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \ ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \ ((PORTSOURCE) == EXTI_PortSourceGPIOF) || \ ((PORTSOURCE) == EXTI_PortSourceGPIOG) || \ ((PORTSOURCE) == EXTI_PortSourceGPIOH) || \ ((PORTSOURCE) == EXTI_PortSourceGPIOI)) /** * @} */ /** @defgroup SYSCFG_EXTI_Pin_Sources * @{ */ #define EXTI_PinSource0 ((uint8_t)0x00) #define EXTI_PinSource1 ((uint8_t)0x01) #define EXTI_PinSource2 ((uint8_t)0x02) #define EXTI_PinSource3 ((uint8_t)0x03) #define EXTI_PinSource4 ((uint8_t)0x04) #define EXTI_PinSource5 ((uint8_t)0x05) #define EXTI_PinSource6 ((uint8_t)0x06) #define EXTI_PinSource7 ((uint8_t)0x07) #define EXTI_PinSource8 ((uint8_t)0x08) #define EXTI_PinSource9 ((uint8_t)0x09) #define EXTI_PinSource10 ((uint8_t)0x0A) #define EXTI_PinSource11 ((uint8_t)0x0B) #define EXTI_PinSource12 ((uint8_t)0x0C) #define EXTI_PinSource13 ((uint8_t)0x0D) #define EXTI_PinSource14 ((uint8_t)0x0E) #define EXTI_PinSource15 ((uint8_t)0x0F) #define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \ ((PINSOURCE) == EXTI_PinSource1) || \ ((PINSOURCE) == EXTI_PinSource2) || \ ((PINSOURCE) == EXTI_PinSource3) || \ ((PINSOURCE) == EXTI_PinSource4) || \ ((PINSOURCE) == EXTI_PinSource5) || \ ((PINSOURCE) == EXTI_PinSource6) || \ ((PINSOURCE) == EXTI_PinSource7) || \ ((PINSOURCE) == EXTI_PinSource8) || \ ((PINSOURCE) == EXTI_PinSource9) || \ ((PINSOURCE) == EXTI_PinSource10) || \ ((PINSOURCE) == EXTI_PinSource11) || \ ((PINSOURCE) == EXTI_PinSource12) || \ ((PINSOURCE) == EXTI_PinSource13) || \ ((PINSOURCE) == EXTI_PinSource14) || \ ((PINSOURCE) == EXTI_PinSource15)) /** * @} */ /** @defgroup SYSCFG_Memory_Remap_Config * @{ */ #define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00) #define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01) #define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02) #define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03) #define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \ ((REMAP) == SYSCFG_MemoryRemap_FSMC)) /** * @} */ /** @defgroup SYSCFG_ETHERNET_Media_Interface * @{ */ #define SYSCFG_ETH_MediaInterface_MII ((uint32_t)0x00000000) #define SYSCFG_ETH_MediaInterface_RMII ((uint32_t)0x00000001) #define IS_SYSCFG_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == SYSCFG_ETH_MediaInterface_MII) || \ ((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ void SYSCFG_DeInit(void); void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap); void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex); void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface); void SYSCFG_CompensationCellCmd(FunctionalState NewState); FlagStatus SYSCFG_GetCompensationCellStatus(void); #ifdef __cplusplus } #endif #endif /*__STM32F4xx_SYSCFG_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_tim.h ================================================ /** ****************************************************************************** * @file stm32f4xx_tim.h * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file contains all the functions prototypes for the TIM firmware * library. ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_TIM_H #define __STM32F4xx_TIM_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup TIM * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief TIM Time Base Init structure definition * @note This structure is used with all TIMx except for TIM6 and TIM7. */ typedef struct { uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between 0x0000 and 0xFFFF */ uint16_t TIM_CounterMode; /*!< Specifies the counter mode. This parameter can be a value of @ref TIM_Counter_Mode */ uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active Auto-Reload Register at the next update event. This parameter must be a number between 0x0000 and 0xFFFF. */ uint16_t TIM_ClockDivision; /*!< Specifies the clock division. This parameter can be a value of @ref TIM_Clock_Division_CKD */ uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to: - the number of PWM periods in edge-aligned mode - the number of half PWM period in center-aligned mode This parameter must be a number between 0x00 and 0xFF. @note This parameter is valid only for TIM1 and TIM8. */ } TIM_TimeBaseInitTypeDef; /** * @brief TIM Output Compare Init structure definition */ typedef struct { uint16_t TIM_OCMode; /*!< Specifies the TIM mode. This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. This parameter can be a value of @ref TIM_Output_Compare_State */ uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. This parameter can be a value of @ref TIM_Output_Compare_N_State @note This parameter is valid only for TIM1 and TIM8. */ uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between 0x0000 and 0xFFFF */ uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. This parameter can be a value of @ref TIM_Output_Compare_Polarity */ uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. This parameter can be a value of @ref TIM_Output_Compare_N_Polarity @note This parameter is valid only for TIM1 and TIM8. */ uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_Idle_State @note This parameter is valid only for TIM1 and TIM8. */ uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State @note This parameter is valid only for TIM1 and TIM8. */ } TIM_OCInitTypeDef; /** * @brief TIM Input Capture Init structure definition */ typedef struct { uint16_t TIM_Channel; /*!< Specifies the TIM channel. This parameter can be a value of @ref TIM_Channel */ uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ uint16_t TIM_ICSelection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. This parameter can be a number between 0x0 and 0xF */ } TIM_ICInitTypeDef; /** * @brief BDTR structure definition * @note This structure is used only with TIM1 and TIM8. */ typedef struct { uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. This parameter can be a value of @ref TIM_Lock_level */ uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the switching-on of the outputs. This parameter can be a number between 0x00 and 0xFF */ uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. This parameter can be a value of @ref TIM_Break_Input_enable_disable */ uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. This parameter can be a value of @ref TIM_Break_Polarity */ uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ } TIM_BDTRInitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup TIM_Exported_constants * @{ */ #define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ ((PERIPH) == TIM2) || \ ((PERIPH) == TIM3) || \ ((PERIPH) == TIM4) || \ ((PERIPH) == TIM5) || \ ((PERIPH) == TIM6) || \ ((PERIPH) == TIM7) || \ ((PERIPH) == TIM8) || \ ((PERIPH) == TIM9) || \ ((PERIPH) == TIM10) || \ ((PERIPH) == TIM11) || \ ((PERIPH) == TIM12) || \ (((PERIPH) == TIM13) || \ ((PERIPH) == TIM14))) /* LIST1: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14 */ #define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ ((PERIPH) == TIM2) || \ ((PERIPH) == TIM3) || \ ((PERIPH) == TIM4) || \ ((PERIPH) == TIM5) || \ ((PERIPH) == TIM8) || \ ((PERIPH) == TIM9) || \ ((PERIPH) == TIM10) || \ ((PERIPH) == TIM11) || \ ((PERIPH) == TIM12) || \ ((PERIPH) == TIM13) || \ ((PERIPH) == TIM14)) /* LIST2: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9 and TIM12 */ #define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ ((PERIPH) == TIM2) || \ ((PERIPH) == TIM3) || \ ((PERIPH) == TIM4) || \ ((PERIPH) == TIM5) || \ ((PERIPH) == TIM8) || \ ((PERIPH) == TIM9) || \ ((PERIPH) == TIM12)) /* LIST3: TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 */ #define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ ((PERIPH) == TIM2) || \ ((PERIPH) == TIM3) || \ ((PERIPH) == TIM4) || \ ((PERIPH) == TIM5) || \ ((PERIPH) == TIM8)) /* LIST4: TIM1 and TIM8 */ #define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ ((PERIPH) == TIM8)) /* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */ #define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ ((PERIPH) == TIM2) || \ ((PERIPH) == TIM3) || \ ((PERIPH) == TIM4) || \ ((PERIPH) == TIM5) || \ ((PERIPH) == TIM6) || \ ((PERIPH) == TIM7) || \ ((PERIPH) == TIM8)) /* LIST6: TIM2, TIM5 and TIM11 */ #define IS_TIM_LIST6_PERIPH(TIMx)(((TIMx) == TIM2) || \ ((TIMx) == TIM5) || \ ((TIMx) == TIM11)) /** @defgroup TIM_Output_Compare_and_PWM_modes * @{ */ #define TIM_OCMode_Timing ((uint16_t)0x0000) #define TIM_OCMode_Active ((uint16_t)0x0010) #define TIM_OCMode_Inactive ((uint16_t)0x0020) #define TIM_OCMode_Toggle ((uint16_t)0x0030) #define TIM_OCMode_PWM1 ((uint16_t)0x0060) #define TIM_OCMode_PWM2 ((uint16_t)0x0070) #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ ((MODE) == TIM_OCMode_Active) || \ ((MODE) == TIM_OCMode_Inactive) || \ ((MODE) == TIM_OCMode_Toggle)|| \ ((MODE) == TIM_OCMode_PWM1) || \ ((MODE) == TIM_OCMode_PWM2)) #define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ ((MODE) == TIM_OCMode_Active) || \ ((MODE) == TIM_OCMode_Inactive) || \ ((MODE) == TIM_OCMode_Toggle)|| \ ((MODE) == TIM_OCMode_PWM1) || \ ((MODE) == TIM_OCMode_PWM2) || \ ((MODE) == TIM_ForcedAction_Active) || \ ((MODE) == TIM_ForcedAction_InActive)) /** * @} */ /** @defgroup TIM_One_Pulse_Mode * @{ */ #define TIM_OPMode_Single ((uint16_t)0x0008) #define TIM_OPMode_Repetitive ((uint16_t)0x0000) #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ ((MODE) == TIM_OPMode_Repetitive)) /** * @} */ /** @defgroup TIM_Channel * @{ */ #define TIM_Channel_1 ((uint16_t)0x0000) #define TIM_Channel_2 ((uint16_t)0x0004) #define TIM_Channel_3 ((uint16_t)0x0008) #define TIM_Channel_4 ((uint16_t)0x000C) #define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ ((CHANNEL) == TIM_Channel_2) || \ ((CHANNEL) == TIM_Channel_3) || \ ((CHANNEL) == TIM_Channel_4)) #define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ ((CHANNEL) == TIM_Channel_2)) #define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ ((CHANNEL) == TIM_Channel_2) || \ ((CHANNEL) == TIM_Channel_3)) /** * @} */ /** @defgroup TIM_Clock_Division_CKD * @{ */ #define TIM_CKD_DIV1 ((uint16_t)0x0000) #define TIM_CKD_DIV2 ((uint16_t)0x0100) #define TIM_CKD_DIV4 ((uint16_t)0x0200) #define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ ((DIV) == TIM_CKD_DIV2) || \ ((DIV) == TIM_CKD_DIV4)) /** * @} */ /** @defgroup TIM_Counter_Mode * @{ */ #define TIM_CounterMode_Up ((uint16_t)0x0000) #define TIM_CounterMode_Down ((uint16_t)0x0010) #define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) #define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) #define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ ((MODE) == TIM_CounterMode_Down) || \ ((MODE) == TIM_CounterMode_CenterAligned1) || \ ((MODE) == TIM_CounterMode_CenterAligned2) || \ ((MODE) == TIM_CounterMode_CenterAligned3)) /** * @} */ /** @defgroup TIM_Output_Compare_Polarity * @{ */ #define TIM_OCPolarity_High ((uint16_t)0x0000) #define TIM_OCPolarity_Low ((uint16_t)0x0002) #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ ((POLARITY) == TIM_OCPolarity_Low)) /** * @} */ /** @defgroup TIM_Output_Compare_N_Polarity * @{ */ #define TIM_OCNPolarity_High ((uint16_t)0x0000) #define TIM_OCNPolarity_Low ((uint16_t)0x0008) #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ ((POLARITY) == TIM_OCNPolarity_Low)) /** * @} */ /** @defgroup TIM_Output_Compare_State * @{ */ #define TIM_OutputState_Disable ((uint16_t)0x0000) #define TIM_OutputState_Enable ((uint16_t)0x0001) #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ ((STATE) == TIM_OutputState_Enable)) /** * @} */ /** @defgroup TIM_Output_Compare_N_State * @{ */ #define TIM_OutputNState_Disable ((uint16_t)0x0000) #define TIM_OutputNState_Enable ((uint16_t)0x0004) #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ ((STATE) == TIM_OutputNState_Enable)) /** * @} */ /** @defgroup TIM_Capture_Compare_State * @{ */ #define TIM_CCx_Enable ((uint16_t)0x0001) #define TIM_CCx_Disable ((uint16_t)0x0000) #define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ ((CCX) == TIM_CCx_Disable)) /** * @} */ /** @defgroup TIM_Capture_Compare_N_State * @{ */ #define TIM_CCxN_Enable ((uint16_t)0x0004) #define TIM_CCxN_Disable ((uint16_t)0x0000) #define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ ((CCXN) == TIM_CCxN_Disable)) /** * @} */ /** @defgroup TIM_Break_Input_enable_disable * @{ */ #define TIM_Break_Enable ((uint16_t)0x1000) #define TIM_Break_Disable ((uint16_t)0x0000) #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ ((STATE) == TIM_Break_Disable)) /** * @} */ /** @defgroup TIM_Break_Polarity * @{ */ #define TIM_BreakPolarity_Low ((uint16_t)0x0000) #define TIM_BreakPolarity_High ((uint16_t)0x2000) #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ ((POLARITY) == TIM_BreakPolarity_High)) /** * @} */ /** @defgroup TIM_AOE_Bit_Set_Reset * @{ */ #define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) #define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ ((STATE) == TIM_AutomaticOutput_Disable)) /** * @} */ /** @defgroup TIM_Lock_level * @{ */ #define TIM_LOCKLevel_OFF ((uint16_t)0x0000) #define TIM_LOCKLevel_1 ((uint16_t)0x0100) #define TIM_LOCKLevel_2 ((uint16_t)0x0200) #define TIM_LOCKLevel_3 ((uint16_t)0x0300) #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ ((LEVEL) == TIM_LOCKLevel_1) || \ ((LEVEL) == TIM_LOCKLevel_2) || \ ((LEVEL) == TIM_LOCKLevel_3)) /** * @} */ /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state * @{ */ #define TIM_OSSIState_Enable ((uint16_t)0x0400) #define TIM_OSSIState_Disable ((uint16_t)0x0000) #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ ((STATE) == TIM_OSSIState_Disable)) /** * @} */ /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state * @{ */ #define TIM_OSSRState_Enable ((uint16_t)0x0800) #define TIM_OSSRState_Disable ((uint16_t)0x0000) #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ ((STATE) == TIM_OSSRState_Disable)) /** * @} */ /** @defgroup TIM_Output_Compare_Idle_State * @{ */ #define TIM_OCIdleState_Set ((uint16_t)0x0100) #define TIM_OCIdleState_Reset ((uint16_t)0x0000) #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ ((STATE) == TIM_OCIdleState_Reset)) /** * @} */ /** @defgroup TIM_Output_Compare_N_Idle_State * @{ */ #define TIM_OCNIdleState_Set ((uint16_t)0x0200) #define TIM_OCNIdleState_Reset ((uint16_t)0x0000) #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ ((STATE) == TIM_OCNIdleState_Reset)) /** * @} */ /** @defgroup TIM_Input_Capture_Polarity * @{ */ #define TIM_ICPolarity_Rising ((uint16_t)0x0000) #define TIM_ICPolarity_Falling ((uint16_t)0x0002) #define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ ((POLARITY) == TIM_ICPolarity_Falling)|| \ ((POLARITY) == TIM_ICPolarity_BothEdge)) /** * @} */ /** @defgroup TIM_Input_Capture_Selection * @{ */ #define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ #define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively. */ #define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ ((SELECTION) == TIM_ICSelection_IndirectTI) || \ ((SELECTION) == TIM_ICSelection_TRC)) /** * @} */ /** @defgroup TIM_Input_Capture_Prescaler * @{ */ #define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ #define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ #define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ #define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ ((PRESCALER) == TIM_ICPSC_DIV2) || \ ((PRESCALER) == TIM_ICPSC_DIV4) || \ ((PRESCALER) == TIM_ICPSC_DIV8)) /** * @} */ /** @defgroup TIM_interrupt_sources * @{ */ #define TIM_IT_Update ((uint16_t)0x0001) #define TIM_IT_CC1 ((uint16_t)0x0002) #define TIM_IT_CC2 ((uint16_t)0x0004) #define TIM_IT_CC3 ((uint16_t)0x0008) #define TIM_IT_CC4 ((uint16_t)0x0010) #define TIM_IT_COM ((uint16_t)0x0020) #define TIM_IT_Trigger ((uint16_t)0x0040) #define TIM_IT_Break ((uint16_t)0x0080) #define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ ((IT) == TIM_IT_CC1) || \ ((IT) == TIM_IT_CC2) || \ ((IT) == TIM_IT_CC3) || \ ((IT) == TIM_IT_CC4) || \ ((IT) == TIM_IT_COM) || \ ((IT) == TIM_IT_Trigger) || \ ((IT) == TIM_IT_Break)) /** * @} */ /** @defgroup TIM_DMA_Base_address * @{ */ #define TIM_DMABase_CR1 ((uint16_t)0x0000) #define TIM_DMABase_CR2 ((uint16_t)0x0001) #define TIM_DMABase_SMCR ((uint16_t)0x0002) #define TIM_DMABase_DIER ((uint16_t)0x0003) #define TIM_DMABase_SR ((uint16_t)0x0004) #define TIM_DMABase_EGR ((uint16_t)0x0005) #define TIM_DMABase_CCMR1 ((uint16_t)0x0006) #define TIM_DMABase_CCMR2 ((uint16_t)0x0007) #define TIM_DMABase_CCER ((uint16_t)0x0008) #define TIM_DMABase_CNT ((uint16_t)0x0009) #define TIM_DMABase_PSC ((uint16_t)0x000A) #define TIM_DMABase_ARR ((uint16_t)0x000B) #define TIM_DMABase_RCR ((uint16_t)0x000C) #define TIM_DMABase_CCR1 ((uint16_t)0x000D) #define TIM_DMABase_CCR2 ((uint16_t)0x000E) #define TIM_DMABase_CCR3 ((uint16_t)0x000F) #define TIM_DMABase_CCR4 ((uint16_t)0x0010) #define TIM_DMABase_BDTR ((uint16_t)0x0011) #define TIM_DMABase_DCR ((uint16_t)0x0012) #define TIM_DMABase_OR ((uint16_t)0x0013) #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ ((BASE) == TIM_DMABase_CR2) || \ ((BASE) == TIM_DMABase_SMCR) || \ ((BASE) == TIM_DMABase_DIER) || \ ((BASE) == TIM_DMABase_SR) || \ ((BASE) == TIM_DMABase_EGR) || \ ((BASE) == TIM_DMABase_CCMR1) || \ ((BASE) == TIM_DMABase_CCMR2) || \ ((BASE) == TIM_DMABase_CCER) || \ ((BASE) == TIM_DMABase_CNT) || \ ((BASE) == TIM_DMABase_PSC) || \ ((BASE) == TIM_DMABase_ARR) || \ ((BASE) == TIM_DMABase_RCR) || \ ((BASE) == TIM_DMABase_CCR1) || \ ((BASE) == TIM_DMABase_CCR2) || \ ((BASE) == TIM_DMABase_CCR3) || \ ((BASE) == TIM_DMABase_CCR4) || \ ((BASE) == TIM_DMABase_BDTR) || \ ((BASE) == TIM_DMABase_DCR) || \ ((BASE) == TIM_DMABase_OR)) /** * @} */ /** @defgroup TIM_DMA_Burst_Length * @{ */ #define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) #define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) #define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) #define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) #define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) #define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) #define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) #define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) #define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) #define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) #define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) #define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) #define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) #define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) #define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) #define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) #define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) #define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ ((LENGTH) == TIM_DMABurstLength_18Transfers)) /** * @} */ /** @defgroup TIM_DMA_sources * @{ */ #define TIM_DMA_Update ((uint16_t)0x0100) #define TIM_DMA_CC1 ((uint16_t)0x0200) #define TIM_DMA_CC2 ((uint16_t)0x0400) #define TIM_DMA_CC3 ((uint16_t)0x0800) #define TIM_DMA_CC4 ((uint16_t)0x1000) #define TIM_DMA_COM ((uint16_t)0x2000) #define TIM_DMA_Trigger ((uint16_t)0x4000) #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) /** * @} */ /** @defgroup TIM_External_Trigger_Prescaler * @{ */ #define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) #define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) #define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) #define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) #define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) /** * @} */ /** @defgroup TIM_Internal_Trigger_Selection * @{ */ #define TIM_TS_ITR0 ((uint16_t)0x0000) #define TIM_TS_ITR1 ((uint16_t)0x0010) #define TIM_TS_ITR2 ((uint16_t)0x0020) #define TIM_TS_ITR3 ((uint16_t)0x0030) #define TIM_TS_TI1F_ED ((uint16_t)0x0040) #define TIM_TS_TI1FP1 ((uint16_t)0x0050) #define TIM_TS_TI2FP2 ((uint16_t)0x0060) #define TIM_TS_ETRF ((uint16_t)0x0070) #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ ((SELECTION) == TIM_TS_ITR1) || \ ((SELECTION) == TIM_TS_ITR2) || \ ((SELECTION) == TIM_TS_ITR3) || \ ((SELECTION) == TIM_TS_TI1F_ED) || \ ((SELECTION) == TIM_TS_TI1FP1) || \ ((SELECTION) == TIM_TS_TI2FP2) || \ ((SELECTION) == TIM_TS_ETRF)) #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ ((SELECTION) == TIM_TS_ITR1) || \ ((SELECTION) == TIM_TS_ITR2) || \ ((SELECTION) == TIM_TS_ITR3)) /** * @} */ /** @defgroup TIM_TIx_External_Clock_Source * @{ */ #define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) #define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) #define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) /** * @} */ /** @defgroup TIM_External_Trigger_Polarity * @{ */ #define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) #define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) #define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) /** * @} */ /** @defgroup TIM_Prescaler_Reload_Mode * @{ */ #define TIM_PSCReloadMode_Update ((uint16_t)0x0000) #define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) #define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ ((RELOAD) == TIM_PSCReloadMode_Immediate)) /** * @} */ /** @defgroup TIM_Forced_Action * @{ */ #define TIM_ForcedAction_Active ((uint16_t)0x0050) #define TIM_ForcedAction_InActive ((uint16_t)0x0040) #define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ ((ACTION) == TIM_ForcedAction_InActive)) /** * @} */ /** @defgroup TIM_Encoder_Mode * @{ */ #define TIM_EncoderMode_TI1 ((uint16_t)0x0001) #define TIM_EncoderMode_TI2 ((uint16_t)0x0002) #define TIM_EncoderMode_TI12 ((uint16_t)0x0003) #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ ((MODE) == TIM_EncoderMode_TI2) || \ ((MODE) == TIM_EncoderMode_TI12)) /** * @} */ /** @defgroup TIM_Event_Source * @{ */ #define TIM_EventSource_Update ((uint16_t)0x0001) #define TIM_EventSource_CC1 ((uint16_t)0x0002) #define TIM_EventSource_CC2 ((uint16_t)0x0004) #define TIM_EventSource_CC3 ((uint16_t)0x0008) #define TIM_EventSource_CC4 ((uint16_t)0x0010) #define TIM_EventSource_COM ((uint16_t)0x0020) #define TIM_EventSource_Trigger ((uint16_t)0x0040) #define TIM_EventSource_Break ((uint16_t)0x0080) #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) /** * @} */ /** @defgroup TIM_Update_Source * @{ */ #define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow or the setting of UG bit, or an update generation through the slave mode controller. */ #define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ ((SOURCE) == TIM_UpdateSource_Regular)) /** * @} */ /** @defgroup TIM_Output_Compare_Preload_State * @{ */ #define TIM_OCPreload_Enable ((uint16_t)0x0008) #define TIM_OCPreload_Disable ((uint16_t)0x0000) #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ ((STATE) == TIM_OCPreload_Disable)) /** * @} */ /** @defgroup TIM_Output_Compare_Fast_State * @{ */ #define TIM_OCFast_Enable ((uint16_t)0x0004) #define TIM_OCFast_Disable ((uint16_t)0x0000) #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ ((STATE) == TIM_OCFast_Disable)) /** * @} */ /** @defgroup TIM_Output_Compare_Clear_State * @{ */ #define TIM_OCClear_Enable ((uint16_t)0x0080) #define TIM_OCClear_Disable ((uint16_t)0x0000) #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ ((STATE) == TIM_OCClear_Disable)) /** * @} */ /** @defgroup TIM_Trigger_Output_Source * @{ */ #define TIM_TRGOSource_Reset ((uint16_t)0x0000) #define TIM_TRGOSource_Enable ((uint16_t)0x0010) #define TIM_TRGOSource_Update ((uint16_t)0x0020) #define TIM_TRGOSource_OC1 ((uint16_t)0x0030) #define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) #define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) #define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) #define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ ((SOURCE) == TIM_TRGOSource_Enable) || \ ((SOURCE) == TIM_TRGOSource_Update) || \ ((SOURCE) == TIM_TRGOSource_OC1) || \ ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ ((SOURCE) == TIM_TRGOSource_OC4Ref)) /** * @} */ /** @defgroup TIM_Slave_Mode * @{ */ #define TIM_SlaveMode_Reset ((uint16_t)0x0004) #define TIM_SlaveMode_Gated ((uint16_t)0x0005) #define TIM_SlaveMode_Trigger ((uint16_t)0x0006) #define TIM_SlaveMode_External1 ((uint16_t)0x0007) #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ ((MODE) == TIM_SlaveMode_Gated) || \ ((MODE) == TIM_SlaveMode_Trigger) || \ ((MODE) == TIM_SlaveMode_External1)) /** * @} */ /** @defgroup TIM_Master_Slave_Mode * @{ */ #define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) #define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ ((STATE) == TIM_MasterSlaveMode_Disable)) /** * @} */ /** @defgroup TIM_Remap * @{ */ #define TIM2_TIM8_TRGO ((uint16_t)0x0000) #define TIM2_ETH_PTP ((uint16_t)0x0400) #define TIM2_USBFS_SOF ((uint16_t)0x0800) #define TIM2_USBHS_SOF ((uint16_t)0x0C00) #define TIM5_GPIO ((uint16_t)0x0000) #define TIM5_LSI ((uint16_t)0x0040) #define TIM5_LSE ((uint16_t)0x0080) #define TIM5_RTC ((uint16_t)0x00C0) #define TIM11_GPIO ((uint16_t)0x0000) #define TIM11_HSE ((uint16_t)0x0002) #define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM2_TIM8_TRGO)||\ ((TIM_REMAP) == TIM2_ETH_PTP)||\ ((TIM_REMAP) == TIM2_USBFS_SOF)||\ ((TIM_REMAP) == TIM2_USBHS_SOF)||\ ((TIM_REMAP) == TIM5_GPIO)||\ ((TIM_REMAP) == TIM5_LSI)||\ ((TIM_REMAP) == TIM5_LSE)||\ ((TIM_REMAP) == TIM5_RTC)||\ ((TIM_REMAP) == TIM11_GPIO)||\ ((TIM_REMAP) == TIM11_HSE)) /** * @} */ /** @defgroup TIM_Flags * @{ */ #define TIM_FLAG_Update ((uint16_t)0x0001) #define TIM_FLAG_CC1 ((uint16_t)0x0002) #define TIM_FLAG_CC2 ((uint16_t)0x0004) #define TIM_FLAG_CC3 ((uint16_t)0x0008) #define TIM_FLAG_CC4 ((uint16_t)0x0010) #define TIM_FLAG_COM ((uint16_t)0x0020) #define TIM_FLAG_Trigger ((uint16_t)0x0040) #define TIM_FLAG_Break ((uint16_t)0x0080) #define TIM_FLAG_CC1OF ((uint16_t)0x0200) #define TIM_FLAG_CC2OF ((uint16_t)0x0400) #define TIM_FLAG_CC3OF ((uint16_t)0x0800) #define TIM_FLAG_CC4OF ((uint16_t)0x1000) #define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ ((FLAG) == TIM_FLAG_CC1) || \ ((FLAG) == TIM_FLAG_CC2) || \ ((FLAG) == TIM_FLAG_CC3) || \ ((FLAG) == TIM_FLAG_CC4) || \ ((FLAG) == TIM_FLAG_COM) || \ ((FLAG) == TIM_FLAG_Trigger) || \ ((FLAG) == TIM_FLAG_Break) || \ ((FLAG) == TIM_FLAG_CC1OF) || \ ((FLAG) == TIM_FLAG_CC2OF) || \ ((FLAG) == TIM_FLAG_CC3OF) || \ ((FLAG) == TIM_FLAG_CC4OF)) /** * @} */ /** @defgroup TIM_Input_Capture_Filer_Value * @{ */ #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) /** * @} */ /** @defgroup TIM_External_Trigger_Filter * @{ */ #define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) /** * @} */ /** @defgroup TIM_Legacy * @{ */ #define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer #define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers #define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers #define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers #define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers #define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers #define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers #define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers #define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers #define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers #define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers #define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers #define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers #define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers #define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers #define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers #define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers #define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* TimeBase management ********************************************************/ void TIM_DeInit(TIM_TypeDef* TIMx); void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter); void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload); uint32_t TIM_GetCounter(TIM_TypeDef* TIMx); uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); /* Output Compare management **************************************************/ void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1); void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2); void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3); void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4); void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); /* Input Capture management ***************************************************/ void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx); uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx); uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx); uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx); void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); /* Advanced-control timers (TIM1 and TIM8) specific features ******************/ void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); /* Interrupts, DMA and flags management ***************************************/ void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); /* Clocks management **********************************************************/ void TIM_InternalClockConfig(TIM_TypeDef* TIMx); void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t TIM_ICPolarity, uint16_t ICFilter); void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); /* Synchronization management *************************************************/ void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); /* Specific interface management **********************************************/ void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); /* Specific remapping management **********************************************/ void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap); #ifdef __cplusplus } #endif #endif /*__STM32F4xx_TIM_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_usart.h ================================================ /** ****************************************************************************** * @file stm32f4xx_usart.h * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file contains all the functions prototypes for the USART * firmware library. ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_USART_H #define __STM32F4xx_USART_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup USART * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief USART Init Structure definition */ typedef struct { uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. The baud rate is computed using the following formula: - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate))) - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */ uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of @ref USART_Word_Length */ uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. This parameter can be a value of @ref USART_Stop_Bits */ uint16_t USART_Parity; /*!< Specifies the parity mode. This parameter can be a value of @ref USART_Parity @note When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits). */ uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of @ref USART_Mode */ uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled or disabled. This parameter can be a value of @ref USART_Hardware_Flow_Control */ } USART_InitTypeDef; /** * @brief USART Clock Init Structure definition */ typedef struct { uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. This parameter can be a value of @ref USART_Clock */ uint16_t USART_CPOL; /*!< Specifies the steady state of the serial clock. This parameter can be a value of @ref USART_Clock_Polarity */ uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. This parameter can be a value of @ref USART_Clock_Phase */ uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of @ref USART_Last_Bit */ } USART_ClockInitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup USART_Exported_Constants * @{ */ #define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ ((PERIPH) == USART2) || \ ((PERIPH) == USART3) || \ ((PERIPH) == UART4) || \ ((PERIPH) == UART5) || \ ((PERIPH) == USART6)) #define IS_USART_1236_PERIPH(PERIPH) (((PERIPH) == USART1) || \ ((PERIPH) == USART2) || \ ((PERIPH) == USART3) || \ ((PERIPH) == USART6)) /** @defgroup USART_Word_Length * @{ */ #define USART_WordLength_8b ((uint16_t)0x0000) #define USART_WordLength_9b ((uint16_t)0x1000) #define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ ((LENGTH) == USART_WordLength_9b)) /** * @} */ /** @defgroup USART_Stop_Bits * @{ */ #define USART_StopBits_1 ((uint16_t)0x0000) #define USART_StopBits_0_5 ((uint16_t)0x1000) #define USART_StopBits_2 ((uint16_t)0x2000) #define USART_StopBits_1_5 ((uint16_t)0x3000) #define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ ((STOPBITS) == USART_StopBits_0_5) || \ ((STOPBITS) == USART_StopBits_2) || \ ((STOPBITS) == USART_StopBits_1_5)) /** * @} */ /** @defgroup USART_Parity * @{ */ #define USART_Parity_No ((uint16_t)0x0000) #define USART_Parity_Even ((uint16_t)0x0400) #define USART_Parity_Odd ((uint16_t)0x0600) #define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ ((PARITY) == USART_Parity_Even) || \ ((PARITY) == USART_Parity_Odd)) /** * @} */ /** @defgroup USART_Mode * @{ */ #define USART_Mode_Rx ((uint16_t)0x0004) #define USART_Mode_Tx ((uint16_t)0x0008) #define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) /** * @} */ /** @defgroup USART_Hardware_Flow_Control * @{ */ #define USART_HardwareFlowControl_None ((uint16_t)0x0000) #define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) #define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) #define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) #define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ (((CONTROL) == USART_HardwareFlowControl_None) || \ ((CONTROL) == USART_HardwareFlowControl_RTS) || \ ((CONTROL) == USART_HardwareFlowControl_CTS) || \ ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) /** * @} */ /** @defgroup USART_Clock * @{ */ #define USART_Clock_Disable ((uint16_t)0x0000) #define USART_Clock_Enable ((uint16_t)0x0800) #define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ ((CLOCK) == USART_Clock_Enable)) /** * @} */ /** @defgroup USART_Clock_Polarity * @{ */ #define USART_CPOL_Low ((uint16_t)0x0000) #define USART_CPOL_High ((uint16_t)0x0400) #define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) /** * @} */ /** @defgroup USART_Clock_Phase * @{ */ #define USART_CPHA_1Edge ((uint16_t)0x0000) #define USART_CPHA_2Edge ((uint16_t)0x0200) #define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) /** * @} */ /** @defgroup USART_Last_Bit * @{ */ #define USART_LastBit_Disable ((uint16_t)0x0000) #define USART_LastBit_Enable ((uint16_t)0x0100) #define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ ((LASTBIT) == USART_LastBit_Enable)) /** * @} */ /** @defgroup USART_Interrupt_definition * @{ */ #define USART_IT_PE ((uint16_t)0x0028) #define USART_IT_TXE ((uint16_t)0x0727) #define USART_IT_TC ((uint16_t)0x0626) #define USART_IT_RXNE ((uint16_t)0x0525) #define USART_IT_ORE_RX ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */ #define USART_IT_IDLE ((uint16_t)0x0424) #define USART_IT_LBD ((uint16_t)0x0846) #define USART_IT_CTS ((uint16_t)0x096A) #define USART_IT_ERR ((uint16_t)0x0060) #define USART_IT_ORE_ER ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */ #define USART_IT_NE ((uint16_t)0x0260) #define USART_IT_FE ((uint16_t)0x0160) /** @defgroup USART_Legacy * @{ */ #define USART_IT_ORE USART_IT_ORE_ER /** * @} */ #define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) #define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ ((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) || \ ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) #define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) /** * @} */ /** @defgroup USART_DMA_Requests * @{ */ #define USART_DMAReq_Tx ((uint16_t)0x0080) #define USART_DMAReq_Rx ((uint16_t)0x0040) #define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) /** * @} */ /** @defgroup USART_WakeUp_methods * @{ */ #define USART_WakeUp_IdleLine ((uint16_t)0x0000) #define USART_WakeUp_AddressMark ((uint16_t)0x0800) #define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ ((WAKEUP) == USART_WakeUp_AddressMark)) /** * @} */ /** @defgroup USART_LIN_Break_Detection_Length * @{ */ #define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) #define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) #define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ (((LENGTH) == USART_LINBreakDetectLength_10b) || \ ((LENGTH) == USART_LINBreakDetectLength_11b)) /** * @} */ /** @defgroup USART_IrDA_Low_Power * @{ */ #define USART_IrDAMode_LowPower ((uint16_t)0x0004) #define USART_IrDAMode_Normal ((uint16_t)0x0000) #define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ ((MODE) == USART_IrDAMode_Normal)) /** * @} */ /** @defgroup USART_Flags * @{ */ #define USART_FLAG_CTS ((uint16_t)0x0200) #define USART_FLAG_LBD ((uint16_t)0x0100) #define USART_FLAG_TXE ((uint16_t)0x0080) #define USART_FLAG_TC ((uint16_t)0x0040) #define USART_FLAG_RXNE ((uint16_t)0x0020) #define USART_FLAG_IDLE ((uint16_t)0x0010) #define USART_FLAG_ORE ((uint16_t)0x0008) #define USART_FLAG_NE ((uint16_t)0x0004) #define USART_FLAG_FE ((uint16_t)0x0002) #define USART_FLAG_PE ((uint16_t)0x0001) #define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) #define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) #define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 7500001)) #define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) #define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the USART configuration to the default reset state ***/ void USART_DeInit(USART_TypeDef* USARTx); /* Initialization and Configuration functions *********************************/ void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); void USART_StructInit(USART_InitTypeDef* USART_InitStruct); void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); /* Data transfers functions ***************************************************/ void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); uint16_t USART_ReceiveData(USART_TypeDef* USARTx); /* Multi-Processor Communication functions ************************************/ void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); /* LIN mode functions *********************************************************/ void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); void USART_SendBreak(USART_TypeDef* USARTx); /* Half-duplex mode function **************************************************/ void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); /* Smartcard mode functions ***************************************************/ void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); /* IrDA mode functions ********************************************************/ void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); /* DMA transfers management functions *****************************************/ void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); /* Interrupts and flags management functions **********************************/ void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); #ifdef __cplusplus } #endif #endif /* __STM32F4xx_USART_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_wwdg.h ================================================ /** ****************************************************************************** * @file stm32f4xx_wwdg.h * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file contains all the functions prototypes for the WWDG firmware * library. ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_WWDG_H #define __STM32F4xx_WWDG_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup WWDG * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup WWDG_Exported_Constants * @{ */ /** @defgroup WWDG_Prescaler * @{ */ #define WWDG_Prescaler_1 ((uint32_t)0x00000000) #define WWDG_Prescaler_2 ((uint32_t)0x00000080) #define WWDG_Prescaler_4 ((uint32_t)0x00000100) #define WWDG_Prescaler_8 ((uint32_t)0x00000180) #define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ ((PRESCALER) == WWDG_Prescaler_2) || \ ((PRESCALER) == WWDG_Prescaler_4) || \ ((PRESCALER) == WWDG_Prescaler_8)) #define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) #define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the WWDG configuration to the default reset state ****/ void WWDG_DeInit(void); /* Prescaler, Refresh window and Counter configuration functions **************/ void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); void WWDG_SetWindowValue(uint8_t WindowValue); void WWDG_EnableIT(void); void WWDG_SetCounter(uint8_t Counter); /* WWDG activation function ***************************************************/ void WWDG_Enable(uint8_t Counter); /* Interrupts and flags management functions **********************************/ FlagStatus WWDG_GetFlagStatus(void); void WWDG_ClearFlag(void); #ifdef __cplusplus } #endif #endif /* __STM32F4xx_WWDG_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/misc.c ================================================ /** ****************************************************************************** * @file misc.c * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file provides all the miscellaneous firmware functions (add-on * to CMSIS functions). * * @verbatim * * =================================================================== * How to configure Interrupts using driver * =================================================================== * * This section provide functions allowing to configure the NVIC interrupts (IRQ). * The Cortex-M4 exceptions are managed by CMSIS functions. * * 1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig() * function according to the following table. * The table below gives the allowed values of the pre-emption priority and subpriority according * to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function * ========================================================================================================================== * NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description * ========================================================================================================================== * NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority * | | | 4 bits for subpriority * -------------------------------------------------------------------------------------------------------------------------- * NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority * | | | 3 bits for subpriority * -------------------------------------------------------------------------------------------------------------------------- * NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority * | | | 2 bits for subpriority * -------------------------------------------------------------------------------------------------------------------------- * NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority * | | | 1 bits for subpriority * -------------------------------------------------------------------------------------------------------------------------- * NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority * | | | 0 bits for subpriority * ========================================================================================================================== * * 2. Enable and Configure the priority of the selected IRQ Channels using NVIC_Init() * * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * * @note IRQ priority order (sorted by highest to lowest priority): * - Lowest pre-emption priority * - Lowest subpriority * - Lowest hardware priority (IRQ number) * * @endverbatim * ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "misc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup MISC * @brief MISC driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup MISC_Private_Functions * @{ */ /** * @brief Configures the priority grouping: pre-emption priority and subpriority. * @param NVIC_PriorityGroup: specifies the priority grouping bits length. * This parameter can be one of the following values: * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority * 4 bits for subpriority * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority * 3 bits for subpriority * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority * 2 bits for subpriority * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority * 1 bits for subpriority * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority * 0 bits for subpriority * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) { /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; } /** * @brief Initializes the NVIC peripheral according to the specified * parameters in the NVIC_InitStruct. * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() * function should be called before. * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains * the configuration information for the specified NVIC peripheral. * @retval None */ void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) { uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) { /* Compute the Corresponding IRQ Priority --------------------------------*/ tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; tmppre = (0x4 - tmppriority); tmpsub = tmpsub >> tmppriority; tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub); tmppriority = tmppriority << 0x04; NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; /* Enable the Selected IRQ Channels --------------------------------------*/ NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); } else { /* Disable the Selected IRQ Channels -------------------------------------*/ NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); } } /** * @brief Sets the vector table location and Offset. * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. * This parameter can be one of the following values: * @arg NVIC_VectTab_RAM: Vector Table in internal SRAM. * @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH. * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200. * @retval None */ void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) { /* Check the parameters */ assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); assert_param(IS_NVIC_OFFSET(Offset)); SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); } /** * @brief Selects the condition for the system to enter low power mode. * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. * This parameter can be one of the following values: * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend. * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request. * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit. * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. * @retval None */ void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_NVIC_LP(LowPowerMode)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { SCB->SCR |= LowPowerMode; } else { SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); } } /** * @brief Configures the SysTick clock source. * @param SysTick_CLKSource: specifies the SysTick clock source. * This parameter can be one of the following values: * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. * @retval None */ void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) { /* Check the parameters */ assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); if (SysTick_CLKSource == SysTick_CLKSource_HCLK) { SysTick->CTRL |= SysTick_CLKSource_HCLK; } else { SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; } } /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c ================================================ /** ****************************************************************************** * @file stm32f4xx_adc.c * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) peripheral: * - Initialization and Configuration (in addition to ADC multi mode * selection) * - Analog Watchdog configuration * - Temperature Sensor & Vrefint (Voltage Reference internal) & VBAT * management * - Regular Channels Configuration * - Regular Channels DMA Configuration * - Injected channels Configuration * - Interrupts and flags management * * @verbatim * * =================================================================== * How to use this driver * =================================================================== * 1. Enable the ADC interface clock using * RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADCx, ENABLE); * * 2. ADC pins configuration * - Enable the clock for the ADC GPIOs using the following function: * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); * - Configure these ADC pins in analog mode using GPIO_Init(); * * 3. Configure the ADC Prescaler, conversion resolution and data * alignment using the ADC_Init() function. * 4. Activate the ADC peripheral using ADC_Cmd() function. * * Regular channels group configuration * ==================================== * - To configure the ADC regular channels group features, use * ADC_Init() and ADC_RegularChannelConfig() functions. * - To activate the continuous mode, use the ADC_continuousModeCmd() * function. * - To configurate and activate the Discontinuous mode, use the * ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions. * - To read the ADC converted values, use the ADC_GetConversionValue() * function. * * Multi mode ADCs Regular channels configuration * =============================================== * - Refer to "Regular channels group configuration" description to * configure the ADC1, ADC2 and ADC3 regular channels. * - Select the Multi mode ADC regular channels features (dual or * triple mode) using ADC_CommonInit() function and configure * the DMA mode using ADC_MultiModeDMARequestAfterLastTransferCmd() * functions. * - Read the ADCs converted values using the * ADC_GetMultiModeConversionValue() function. * * DMA for Regular channels group features configuration * ====================================================== * - To enable the DMA mode for regular channels group, use the * ADC_DMACmd() function. * - To enable the generation of DMA requests continuously at the end * of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd() * function. * * Injected channels group configuration * ===================================== * - To configure the ADC Injected channels group features, use * ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig() * functions. * - To activate the continuous mode, use the ADC_continuousModeCmd() * function. * - To activate the Injected Discontinuous mode, use the * ADC_InjectedDiscModeCmd() function. * - To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd() * function. * - To read the ADC converted values, use the ADC_GetInjectedConversionValue() * function. * * @endverbatim * ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_adc.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup ADC * @brief ADC driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* ADC DISCNUM mask */ #define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF) /* ADC AWDCH mask */ #define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0) /* ADC Analog watchdog enable mode mask */ #define CR1_AWDMode_RESET ((uint32_t)0xFF3FFDFF) /* CR1 register Mask */ #define CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF) /* ADC EXTEN mask */ #define CR2_EXTEN_RESET ((uint32_t)0xCFFFFFFF) /* ADC JEXTEN mask */ #define CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF) /* ADC JEXTSEL mask */ #define CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF) /* CR2 register Mask */ #define CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD) /* ADC SQx mask */ #define SQR3_SQ_SET ((uint32_t)0x0000001F) #define SQR2_SQ_SET ((uint32_t)0x0000001F) #define SQR1_SQ_SET ((uint32_t)0x0000001F) /* ADC L Mask */ #define SQR1_L_RESET ((uint32_t)0xFF0FFFFF) /* ADC JSQx mask */ #define JSQR_JSQ_SET ((uint32_t)0x0000001F) /* ADC JL mask */ #define JSQR_JL_SET ((uint32_t)0x00300000) #define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF) /* ADC SMPx mask */ #define SMPR1_SMP_SET ((uint32_t)0x00000007) #define SMPR2_SMP_SET ((uint32_t)0x00000007) /* ADC JDRx registers offset */ #define JDR_OFFSET ((uint8_t)0x28) /* ADC CDR register base address */ #define CDR_ADDRESS ((uint32_t)0x40012308) /* ADC CCR register Mask */ #define CR_CLEAR_MASK ((uint32_t)0xFFFC30E0) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup ADC_Private_Functions * @{ */ /** @defgroup ADC_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== Initialization and Configuration functions =============================================================================== This section provides functions allowing to: - Initialize and configure the ADC Prescaler - ADC Conversion Resolution (12bit..6bit) - Scan Conversion Mode (multichannels or one channel) for regular group - ADC Continuous Conversion Mode (Continuous or Single conversion) for regular group - External trigger Edge and source of regular group, - Converted data alignment (left or right) - The number of ADC conversions that will be done using the sequencer for regular channel group - Multi ADC mode selection - Direct memory access mode selection for multi ADC mode - Delay between 2 sampling phases (used in dual or triple interleaved modes) - Enable or disable the ADC peripheral @endverbatim * @{ */ /** * @brief Deinitializes all ADCs peripherals registers to their default reset * values. * @param None * @retval None */ void ADC_DeInit(void) { /* Enable all ADCs reset state */ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, ENABLE); /* Release all ADCs from reset state */ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, DISABLE); } /** * @brief Initializes the ADCx peripheral according to the specified parameters * in the ADC_InitStruct. * @note This function is used to configure the global features of the ADC ( * Resolution and Data Alignment), however, the rest of the configuration * parameters are specific to the regular channels group (scan mode * activation, continuous mode activation, External trigger source and * edge, number of conversion in the regular channels group sequencer). * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains * the configuration information for the specified ADC peripheral. * @retval None */ void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) { uint32_t tmpreg1 = 0; uint8_t tmpreg2 = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution)); assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge)); assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion)); /*---------------------------- ADCx CR1 Configuration -----------------*/ /* Get the ADCx CR1 value */ tmpreg1 = ADCx->CR1; /* Clear RES and SCAN bits */ tmpreg1 &= CR1_CLEAR_MASK; /* Configure ADCx: scan conversion mode and resolution */ /* Set SCAN bit according to ADC_ScanConvMode value */ /* Set RES bit according to ADC_Resolution value */ tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | \ ADC_InitStruct->ADC_Resolution); /* Write to ADCx CR1 */ ADCx->CR1 = tmpreg1; /*---------------------------- ADCx CR2 Configuration -----------------*/ /* Get the ADCx CR2 value */ tmpreg1 = ADCx->CR2; /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */ tmpreg1 &= CR2_CLEAR_MASK; /* Configure ADCx: external trigger event and edge, data alignment and continuous conversion mode */ /* Set ALIGN bit according to ADC_DataAlign value */ /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */ /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ /* Set CONT bit according to ADC_ContinuousConvMode value */ tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | \ ADC_InitStruct->ADC_ExternalTrigConv | ADC_InitStruct->ADC_ExternalTrigConvEdge | \ ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); /* Write to ADCx CR2 */ ADCx->CR2 = tmpreg1; /*---------------------------- ADCx SQR1 Configuration -----------------*/ /* Get the ADCx SQR1 value */ tmpreg1 = ADCx->SQR1; /* Clear L bits */ tmpreg1 &= SQR1_L_RESET; /* Configure ADCx: regular channel sequence length */ /* Set L bits according to ADC_NbrOfConversion value */ tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1); tmpreg1 |= ((uint32_t)tmpreg2 << 20); /* Write to ADCx SQR1 */ ADCx->SQR1 = tmpreg1; } /** * @brief Fills each ADC_InitStruct member with its default value. * @note This function is used to initialize the global features of the ADC ( * Resolution and Data Alignment), however, the rest of the configuration * parameters are specific to the regular channels group (scan mode * activation, continuous mode activation, External trigger source and * edge, number of conversion in the regular channels group sequencer). * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will * be initialized. * @retval None */ void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) { /* Initialize the ADC_Mode member */ ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b; /* initialize the ADC_ScanConvMode member */ ADC_InitStruct->ADC_ScanConvMode = DISABLE; /* Initialize the ADC_ContinuousConvMode member */ ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; /* Initialize the ADC_ExternalTrigConvEdge member */ ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; /* Initialize the ADC_ExternalTrigConv member */ ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; /* Initialize the ADC_DataAlign member */ ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; /* Initialize the ADC_NbrOfConversion member */ ADC_InitStruct->ADC_NbrOfConversion = 1; } /** * @brief Initializes the ADCs peripherals according to the specified parameters * in the ADC_CommonInitStruct. * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure * that contains the configuration information for All ADCs peripherals. * @retval None */ void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) { uint32_t tmpreg1 = 0; /* Check the parameters */ assert_param(IS_ADC_MODE(ADC_CommonInitStruct->ADC_Mode)); assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler)); assert_param(IS_ADC_DMA_ACCESS_MODE(ADC_CommonInitStruct->ADC_DMAAccessMode)); assert_param(IS_ADC_SAMPLING_DELAY(ADC_CommonInitStruct->ADC_TwoSamplingDelay)); /*---------------------------- ADC CCR Configuration -----------------*/ /* Get the ADC CCR value */ tmpreg1 = ADC->CCR; /* Clear MULTI, DELAY, DMA and ADCPRE bits */ tmpreg1 &= CR_CLEAR_MASK; /* Configure ADCx: Multi mode, Delay between two sampling time, ADC prescaler, and DMA access mode for multimode */ /* Set MULTI bits according to ADC_Mode value */ /* Set ADCPRE bits according to ADC_Prescaler value */ /* Set DMA bits according to ADC_DMAAccessMode value */ /* Set DELAY bits according to ADC_TwoSamplingDelay value */ tmpreg1 |= (uint32_t)(ADC_CommonInitStruct->ADC_Mode | ADC_CommonInitStruct->ADC_Prescaler | ADC_CommonInitStruct->ADC_DMAAccessMode | ADC_CommonInitStruct->ADC_TwoSamplingDelay); /* Write to ADC CCR */ ADC->CCR = tmpreg1; } /** * @brief Fills each ADC_CommonInitStruct member with its default value. * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure * which will be initialized. * @retval None */ void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) { /* Initialize the ADC_Mode member */ ADC_CommonInitStruct->ADC_Mode = ADC_Mode_Independent; /* initialize the ADC_Prescaler member */ ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div2; /* Initialize the ADC_DMAAccessMode member */ ADC_CommonInitStruct->ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled; /* Initialize the ADC_TwoSamplingDelay member */ ADC_CommonInitStruct->ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles; } /** * @brief Enables or disables the specified ADC peripheral. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param NewState: new state of the ADCx peripheral. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Set the ADON bit to wake up the ADC from power down mode */ ADCx->CR2 |= (uint32_t)ADC_CR2_ADON; } else { /* Disable the selected ADC peripheral */ ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON); } } /** * @} */ /** @defgroup ADC_Group2 Analog Watchdog configuration functions * @brief Analog Watchdog configuration functions * @verbatim =============================================================================== Analog Watchdog configuration functions =============================================================================== This section provides functions allowing to configure the Analog Watchdog (AWD) feature in the ADC. A typical configuration Analog Watchdog is done following these steps : 1. the ADC guarded channel(s) is (are) selected using the ADC_AnalogWatchdogSingleChannelConfig() function. 2. The Analog watchdog lower and higher threshold are configured using the ADC_AnalogWatchdogThresholdsConfig() function. 3. The Analog watchdog is enabled and configured to enable the check, on one or more channels, using the ADC_AnalogWatchdogCmd() function. @endverbatim * @{ */ /** * @brief Enables or disables the analog watchdog on single/all regular or * injected channels * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration. * This parameter can be one of the following values: * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog * @retval None */ void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); /* Get the old register value */ tmpreg = ADCx->CR1; /* Clear AWDEN, JAWDEN and AWDSGL bits */ tmpreg &= CR1_AWDMode_RESET; /* Set the analog watchdog enable mode */ tmpreg |= ADC_AnalogWatchdog; /* Store the new register value */ ADCx->CR1 = tmpreg; } /** * @brief Configures the high and low thresholds of the analog watchdog. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param HighThreshold: the ADC analog watchdog High threshold value. * This parameter must be a 12-bit value. * @param LowThreshold: the ADC analog watchdog Low threshold value. * This parameter must be a 12-bit value. * @retval None */ void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_THRESHOLD(HighThreshold)); assert_param(IS_ADC_THRESHOLD(LowThreshold)); /* Set the ADCx high threshold */ ADCx->HTR = HighThreshold; /* Set the ADCx low threshold */ ADCx->LTR = LowThreshold; } /** * @brief Configures the analog watchdog guarded single channel * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_Channel: the ADC channel to configure for the analog watchdog. * This parameter can be one of the following values: * @arg ADC_Channel_0: ADC Channel0 selected * @arg ADC_Channel_1: ADC Channel1 selected * @arg ADC_Channel_2: ADC Channel2 selected * @arg ADC_Channel_3: ADC Channel3 selected * @arg ADC_Channel_4: ADC Channel4 selected * @arg ADC_Channel_5: ADC Channel5 selected * @arg ADC_Channel_6: ADC Channel6 selected * @arg ADC_Channel_7: ADC Channel7 selected * @arg ADC_Channel_8: ADC Channel8 selected * @arg ADC_Channel_9: ADC Channel9 selected * @arg ADC_Channel_10: ADC Channel10 selected * @arg ADC_Channel_11: ADC Channel11 selected * @arg ADC_Channel_12: ADC Channel12 selected * @arg ADC_Channel_13: ADC Channel13 selected * @arg ADC_Channel_14: ADC Channel14 selected * @arg ADC_Channel_15: ADC Channel15 selected * @arg ADC_Channel_16: ADC Channel16 selected * @arg ADC_Channel_17: ADC Channel17 selected * @arg ADC_Channel_18: ADC Channel18 selected * @retval None */ void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_CHANNEL(ADC_Channel)); /* Get the old register value */ tmpreg = ADCx->CR1; /* Clear the Analog watchdog channel select bits */ tmpreg &= CR1_AWDCH_RESET; /* Set the Analog watchdog channel */ tmpreg |= ADC_Channel; /* Store the new register value */ ADCx->CR1 = tmpreg; } /** * @} */ /** @defgroup ADC_Group3 Temperature Sensor, Vrefint (Voltage Reference internal) * and VBAT (Voltage BATtery) management functions * @brief Temperature Sensor, Vrefint and VBAT management functions * @verbatim =============================================================================== Temperature Sensor, Vrefint and VBAT management functions =============================================================================== This section provides functions allowing to enable/ disable the internal connections between the ADC and the Temperature Sensor, the Vrefint and the Vbat sources. A typical configuration to get the Temperature sensor and Vrefint channels voltages is done following these steps : 1. Enable the internal connection of Temperature sensor and Vrefint sources with the ADC channels using ADC_TempSensorVrefintCmd() function. 2. Select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions 3. Get the voltage values, using ADC_GetConversionValue() or ADC_GetInjectedConversionValue(). A typical configuration to get the VBAT channel voltage is done following these steps : 1. Enable the internal connection of VBAT source with the ADC channel using ADC_VBATCmd() function. 2. Select the ADC_Channel_Vbat using ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions 3. Get the voltage value, using ADC_GetConversionValue() or ADC_GetInjectedConversionValue(). @endverbatim * @{ */ /** * @brief Enables or disables the temperature sensor and Vrefint channels. * @param NewState: new state of the temperature sensor and Vrefint channels. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_TempSensorVrefintCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the temperature sensor and Vrefint channel*/ ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE; } else { /* Disable the temperature sensor and Vrefint channel*/ ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE); } } /** * @brief Enables or disables the VBAT (Voltage Battery) channel. * @param NewState: new state of the VBAT channel. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_VBATCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the VBAT channel*/ ADC->CCR |= (uint32_t)ADC_CCR_VBATE; } else { /* Disable the VBAT channel*/ ADC->CCR &= (uint32_t)(~ADC_CCR_VBATE); } } /** * @} */ /** @defgroup ADC_Group4 Regular Channels Configuration functions * @brief Regular Channels Configuration functions * @verbatim =============================================================================== Regular Channels Configuration functions =============================================================================== This section provides functions allowing to manage the ADC's regular channels, it is composed of 2 sub sections : 1. Configuration and management functions for regular channels: This subsection provides functions allowing to configure the ADC regular channels : - Configure the rank in the regular group sequencer for each channel - Configure the sampling time for each channel - select the conversion Trigger for regular channels - select the desired EOC event behavior configuration - Activate the continuous Mode (*) - Activate the Discontinuous Mode Please Note that the following features for regular channels are configurated using the ADC_Init() function : - scan mode activation - continuous mode activation (**) - External trigger source - External trigger edge - number of conversion in the regular channels group sequencer. @note (*) and (**) are performing the same configuration 2. Get the conversion data: This subsection provides an important function in the ADC peripheral since it returns the converted data of the current regular channel. When the Conversion value is read, the EOC Flag is automatically cleared. @note For multi ADC mode, the last ADC1, ADC2 and ADC3 regular conversions results data (in the selected multi mode) can be returned in the same time using ADC_GetMultiModeConversionValue() function. @endverbatim * @{ */ /** * @brief Configures for the selected ADC regular channel its corresponding * rank in the sequencer and its sample time. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_Channel: the ADC channel to configure. * This parameter can be one of the following values: * @arg ADC_Channel_0: ADC Channel0 selected * @arg ADC_Channel_1: ADC Channel1 selected * @arg ADC_Channel_2: ADC Channel2 selected * @arg ADC_Channel_3: ADC Channel3 selected * @arg ADC_Channel_4: ADC Channel4 selected * @arg ADC_Channel_5: ADC Channel5 selected * @arg ADC_Channel_6: ADC Channel6 selected * @arg ADC_Channel_7: ADC Channel7 selected * @arg ADC_Channel_8: ADC Channel8 selected * @arg ADC_Channel_9: ADC Channel9 selected * @arg ADC_Channel_10: ADC Channel10 selected * @arg ADC_Channel_11: ADC Channel11 selected * @arg ADC_Channel_12: ADC Channel12 selected * @arg ADC_Channel_13: ADC Channel13 selected * @arg ADC_Channel_14: ADC Channel14 selected * @arg ADC_Channel_15: ADC Channel15 selected * @arg ADC_Channel_16: ADC Channel16 selected * @arg ADC_Channel_17: ADC Channel17 selected * @arg ADC_Channel_18: ADC Channel18 selected * @param Rank: The rank in the regular group sequencer. * This parameter must be between 1 to 16. * @param ADC_SampleTime: The sample time value to be set for the selected channel. * This parameter can be one of the following values: * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles * @retval None */ void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) { uint32_t tmpreg1 = 0, tmpreg2 = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_CHANNEL(ADC_Channel)); assert_param(IS_ADC_REGULAR_RANK(Rank)); assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ if (ADC_Channel > ADC_Channel_9) { /* Get the old register value */ tmpreg1 = ADCx->SMPR1; /* Calculate the mask to clear */ tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 10)); /* Clear the old sample time */ tmpreg1 &= ~tmpreg2; /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); /* Set the new sample time */ tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->SMPR1 = tmpreg1; } else /* ADC_Channel include in ADC_Channel_[0..9] */ { /* Get the old register value */ tmpreg1 = ADCx->SMPR2; /* Calculate the mask to clear */ tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel); /* Clear the old sample time */ tmpreg1 &= ~tmpreg2; /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); /* Set the new sample time */ tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->SMPR2 = tmpreg1; } /* For Rank 1 to 6 */ if (Rank < 7) { /* Get the old register value */ tmpreg1 = ADCx->SQR3; /* Calculate the mask to clear */ tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 1)); /* Clear the old SQx bits for the selected rank */ tmpreg1 &= ~tmpreg2; /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); /* Set the SQx bits for the selected rank */ tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->SQR3 = tmpreg1; } /* For Rank 7 to 12 */ else if (Rank < 13) { /* Get the old register value */ tmpreg1 = ADCx->SQR2; /* Calculate the mask to clear */ tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 7)); /* Clear the old SQx bits for the selected rank */ tmpreg1 &= ~tmpreg2; /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); /* Set the SQx bits for the selected rank */ tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->SQR2 = tmpreg1; } /* For Rank 13 to 16 */ else { /* Get the old register value */ tmpreg1 = ADCx->SQR1; /* Calculate the mask to clear */ tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 13)); /* Clear the old SQx bits for the selected rank */ tmpreg1 &= ~tmpreg2; /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); /* Set the SQx bits for the selected rank */ tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->SQR1 = tmpreg1; } } /** * @brief Enables the selected ADC software start conversion of the regular channels. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @retval None */ void ADC_SoftwareStartConv(ADC_TypeDef* ADCx) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Enable the selected ADC conversion for regular group */ ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART; } /** * @brief Gets the selected ADC Software start regular conversion Status. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @retval The new state of ADC software start conversion (SET or RESET). */ FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Check the status of SWSTART bit */ if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET) { /* SWSTART bit is set */ bitstatus = SET; } else { /* SWSTART bit is reset */ bitstatus = RESET; } /* Return the SWSTART bit status */ return bitstatus; } /** * @brief Enables or disables the EOC on each regular channel conversion * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param NewState: new state of the selected ADC EOC flag rising * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected ADC EOC rising on each regular channel conversion */ ADCx->CR2 |= (uint32_t)ADC_CR2_EOCS; } else { /* Disable the selected ADC EOC rising on each regular channel conversion */ ADCx->CR2 &= (uint32_t)(~ADC_CR2_EOCS); } } /** * @brief Enables or disables the ADC continuous conversion mode * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param NewState: new state of the selected ADC continuous conversion mode * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected ADC continuous conversion mode */ ADCx->CR2 |= (uint32_t)ADC_CR2_CONT; } else { /* Disable the selected ADC continuous conversion mode */ ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT); } } /** * @brief Configures the discontinuous mode for the selected ADC regular group * channel. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param Number: specifies the discontinuous mode regular channel count value. * This number must be between 1 and 8. * @retval None */ void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) { uint32_t tmpreg1 = 0; uint32_t tmpreg2 = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number)); /* Get the old register value */ tmpreg1 = ADCx->CR1; /* Clear the old discontinuous mode channel count */ tmpreg1 &= CR1_DISCNUM_RESET; /* Set the discontinuous mode channel count */ tmpreg2 = Number - 1; tmpreg1 |= tmpreg2 << 13; /* Store the new register value */ ADCx->CR1 = tmpreg1; } /** * @brief Enables or disables the discontinuous mode on regular group channel * for the specified ADC * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param NewState: new state of the selected ADC discontinuous mode on * regular group channel. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected ADC regular discontinuous mode */ ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN; } else { /* Disable the selected ADC regular discontinuous mode */ ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN); } } /** * @brief Returns the last ADCx conversion result data for regular channel. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @retval The Data conversion value. */ uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Return the selected ADC conversion value */ return (uint16_t) ADCx->DR; } /** * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results * data in the selected multi mode. * @param None * @retval The Data conversion value. * @note In dual mode, the value returned by this function is as following * Data[15:0] : these bits contain the regular data of ADC1. * Data[31:16]: these bits contain the regular data of ADC2. * @note In triple mode, the value returned by this function is as following * Data[15:0] : these bits contain alternatively the regular data of ADC1, ADC3 and ADC2. * Data[31:16]: these bits contain alternatively the regular data of ADC2, ADC1 and ADC3. */ uint32_t ADC_GetMultiModeConversionValue(void) { /* Return the multi mode conversion value */ return (*(__IO uint32_t *) CDR_ADDRESS); } /** * @} */ /** @defgroup ADC_Group5 Regular Channels DMA Configuration functions * @brief Regular Channels DMA Configuration functions * @verbatim =============================================================================== Regular Channels DMA Configuration functions =============================================================================== This section provides functions allowing to configure the DMA for ADC regular channels. Since converted regular channel values are stored into a unique data register, it is useful to use DMA for conversion of more than one regular channel. This avoids the loss of the data already stored in the ADC Data register. When the DMA mode is enabled (using the ADC_DMACmd() function), after each conversion of a regular channel, a DMA request is generated. Depending on the "DMA disable selection for Independent ADC mode" configuration (using the ADC_DMARequestAfterLastTransferCmd() function), at the end of the last DMA transfer, two possibilities are allowed: - No new DMA request is issued to the DMA controller (feature DISABLED) - Requests can continue to be generated (feature ENABLED). Depending on the "DMA disable selection for multi ADC mode" configuration (using the void ADC_MultiModeDMARequestAfterLastTransferCmd() function), at the end of the last DMA transfer, two possibilities are allowed: - No new DMA request is issued to the DMA controller (feature DISABLED) - Requests can continue to be generated (feature ENABLED). @endverbatim * @{ */ /** * @brief Enables or disables the specified ADC DMA request. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param NewState: new state of the selected ADC DMA transfer. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected ADC DMA request */ ADCx->CR2 |= (uint32_t)ADC_CR2_DMA; } else { /* Disable the selected ADC DMA request */ ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA); } } /** * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode) * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param NewState: new state of the selected ADC DMA request after last transfer. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected ADC DMA request after last transfer */ ADCx->CR2 |= (uint32_t)ADC_CR2_DDS; } else { /* Disable the selected ADC DMA request after last transfer */ ADCx->CR2 &= (uint32_t)(~ADC_CR2_DDS); } } /** * @brief Enables or disables the ADC DMA request after last transfer in multi ADC mode * @param NewState: new state of the selected ADC DMA request after last transfer. * This parameter can be: ENABLE or DISABLE. * @note if Enabled, DMA requests are issued as long as data are converted and * DMA mode for multi ADC mode (selected using ADC_CommonInit() function * by ADC_CommonInitStruct.ADC_DMAAccessMode structure member) is * ADC_DMAAccessMode_1, ADC_DMAAccessMode_2 or ADC_DMAAccessMode_3. * @retval None */ void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected ADC DMA request after last transfer */ ADC->CCR |= (uint32_t)ADC_CCR_DDS; } else { /* Disable the selected ADC DMA request after last transfer */ ADC->CCR &= (uint32_t)(~ADC_CCR_DDS); } } /** * @} */ /** @defgroup ADC_Group6 Injected channels Configuration functions * @brief Injected channels Configuration functions * @verbatim =============================================================================== Injected channels Configuration functions =============================================================================== This section provide functions allowing to configure the ADC Injected channels, it is composed of 2 sub sections : 1. Configuration functions for Injected channels: This subsection provides functions allowing to configure the ADC injected channels : - Configure the rank in the injected group sequencer for each channel - Configure the sampling time for each channel - Activate the Auto injected Mode - Activate the Discontinuous Mode - scan mode activation - External/software trigger source - External trigger edge - injected channels sequencer. 2. Get the Specified Injected channel conversion data: This subsection provides an important function in the ADC peripheral since it returns the converted data of the specific injected channel. @endverbatim * @{ */ /** * @brief Configures for the selected ADC injected channel its corresponding * rank in the sequencer and its sample time. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_Channel: the ADC channel to configure. * This parameter can be one of the following values: * @arg ADC_Channel_0: ADC Channel0 selected * @arg ADC_Channel_1: ADC Channel1 selected * @arg ADC_Channel_2: ADC Channel2 selected * @arg ADC_Channel_3: ADC Channel3 selected * @arg ADC_Channel_4: ADC Channel4 selected * @arg ADC_Channel_5: ADC Channel5 selected * @arg ADC_Channel_6: ADC Channel6 selected * @arg ADC_Channel_7: ADC Channel7 selected * @arg ADC_Channel_8: ADC Channel8 selected * @arg ADC_Channel_9: ADC Channel9 selected * @arg ADC_Channel_10: ADC Channel10 selected * @arg ADC_Channel_11: ADC Channel11 selected * @arg ADC_Channel_12: ADC Channel12 selected * @arg ADC_Channel_13: ADC Channel13 selected * @arg ADC_Channel_14: ADC Channel14 selected * @arg ADC_Channel_15: ADC Channel15 selected * @arg ADC_Channel_16: ADC Channel16 selected * @arg ADC_Channel_17: ADC Channel17 selected * @arg ADC_Channel_18: ADC Channel18 selected * @param Rank: The rank in the injected group sequencer. * This parameter must be between 1 to 4. * @param ADC_SampleTime: The sample time value to be set for the selected channel. * This parameter can be one of the following values: * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles * @retval None */ void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) { uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_CHANNEL(ADC_Channel)); assert_param(IS_ADC_INJECTED_RANK(Rank)); assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ if (ADC_Channel > ADC_Channel_9) { /* Get the old register value */ tmpreg1 = ADCx->SMPR1; /* Calculate the mask to clear */ tmpreg2 = SMPR1_SMP_SET << (3*(ADC_Channel - 10)); /* Clear the old sample time */ tmpreg1 &= ~tmpreg2; /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10)); /* Set the new sample time */ tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->SMPR1 = tmpreg1; } else /* ADC_Channel include in ADC_Channel_[0..9] */ { /* Get the old register value */ tmpreg1 = ADCx->SMPR2; /* Calculate the mask to clear */ tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel); /* Clear the old sample time */ tmpreg1 &= ~tmpreg2; /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); /* Set the new sample time */ tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->SMPR2 = tmpreg1; } /* Rank configuration */ /* Get the old register value */ tmpreg1 = ADCx->JSQR; /* Get JL value: Number = JL+1 */ tmpreg3 = (tmpreg1 & JSQR_JL_SET)>> 20; /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */ tmpreg2 = JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); /* Clear the old JSQx bits for the selected rank */ tmpreg1 &= ~tmpreg2; /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */ tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); /* Set the JSQx bits for the selected rank */ tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->JSQR = tmpreg1; } /** * @brief Configures the sequencer length for injected channels * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param Length: The sequencer length. * This parameter must be a number between 1 to 4. * @retval None */ void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length) { uint32_t tmpreg1 = 0; uint32_t tmpreg2 = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_INJECTED_LENGTH(Length)); /* Get the old register value */ tmpreg1 = ADCx->JSQR; /* Clear the old injected sequence length JL bits */ tmpreg1 &= JSQR_JL_RESET; /* Set the injected sequence length JL bits */ tmpreg2 = Length - 1; tmpreg1 |= tmpreg2 << 20; /* Store the new register value */ ADCx->JSQR = tmpreg1; } /** * @brief Set the injected channels conversion value offset * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_InjectedChannel: the ADC injected channel to set its offset. * This parameter can be one of the following values: * @arg ADC_InjectedChannel_1: Injected Channel1 selected * @arg ADC_InjectedChannel_2: Injected Channel2 selected * @arg ADC_InjectedChannel_3: Injected Channel3 selected * @arg ADC_InjectedChannel_4: Injected Channel4 selected * @param Offset: the offset value for the selected ADC injected channel * This parameter must be a 12bit value. * @retval None */ void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) { __IO uint32_t tmp = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); assert_param(IS_ADC_OFFSET(Offset)); tmp = (uint32_t)ADCx; tmp += ADC_InjectedChannel; /* Set the selected injected channel data offset */ *(__IO uint32_t *) tmp = (uint32_t)Offset; } /** * @brief Configures the ADCx external trigger for injected channels conversion. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. * This parameter can be one of the following values: * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected * @arg ADC_ExternalTrigInjecConv_T3_CC2: Timer3 capture compare2 selected * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected * @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected * @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected * @arg ADC_ExternalTrigInjecConv_T8_CC3: Timer8 capture compare3 selected * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected * @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected * @retval None */ void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); /* Get the old register value */ tmpreg = ADCx->CR2; /* Clear the old external event selection for injected group */ tmpreg &= CR2_JEXTSEL_RESET; /* Set the external event selection for injected group */ tmpreg |= ADC_ExternalTrigInjecConv; /* Store the new register value */ ADCx->CR2 = tmpreg; } /** * @brief Configures the ADCx external trigger edge for injected channels conversion. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger edge * to start injected conversion. * This parameter can be one of the following values: * @arg ADC_ExternalTrigInjecConvEdge_None: external trigger disabled for * injected conversion * @arg ADC_ExternalTrigInjecConvEdge_Rising: detection on rising edge * @arg ADC_ExternalTrigInjecConvEdge_Falling: detection on falling edge * @arg ADC_ExternalTrigInjecConvEdge_RisingFalling: detection on both rising * and falling edge * @retval None */ void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge)); /* Get the old register value */ tmpreg = ADCx->CR2; /* Clear the old external trigger edge for injected group */ tmpreg &= CR2_JEXTEN_RESET; /* Set the new external trigger edge for injected group */ tmpreg |= ADC_ExternalTrigInjecConvEdge; /* Store the new register value */ ADCx->CR2 = tmpreg; } /** * @brief Enables the selected ADC software start conversion of the injected channels. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @retval None */ void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Enable the selected ADC conversion for injected group */ ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART; } /** * @brief Gets the selected ADC Software start injected conversion Status. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @retval The new state of ADC software start injected conversion (SET or RESET). */ FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Check the status of JSWSTART bit */ if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET) { /* JSWSTART bit is set */ bitstatus = SET; } else { /* JSWSTART bit is reset */ bitstatus = RESET; } /* Return the JSWSTART bit status */ return bitstatus; } /** * @brief Enables or disables the selected ADC automatic injected group * conversion after regular one. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param NewState: new state of the selected ADC auto injected conversion * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected ADC automatic injected group conversion */ ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO; } else { /* Disable the selected ADC automatic injected group conversion */ ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO); } } /** * @brief Enables or disables the discontinuous mode for injected group * channel for the specified ADC * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param NewState: new state of the selected ADC discontinuous mode on injected * group channel. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected ADC injected discontinuous mode */ ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN; } else { /* Disable the selected ADC injected discontinuous mode */ ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN); } } /** * @brief Returns the ADC injected channel conversion result * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_InjectedChannel: the converted ADC injected channel. * This parameter can be one of the following values: * @arg ADC_InjectedChannel_1: Injected Channel1 selected * @arg ADC_InjectedChannel_2: Injected Channel2 selected * @arg ADC_InjectedChannel_3: Injected Channel3 selected * @arg ADC_InjectedChannel_4: Injected Channel4 selected * @retval The Data conversion value. */ uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel) { __IO uint32_t tmp = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); tmp = (uint32_t)ADCx; tmp += ADC_InjectedChannel + JDR_OFFSET; /* Returns the selected injected channel conversion data value */ return (uint16_t) (*(__IO uint32_t*) tmp); } /** * @} */ /** @defgroup ADC_Group7 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== Interrupts and flags management functions =============================================================================== This section provides functions allowing to configure the ADC Interrupts and to get the status and clear flags and Interrupts pending bits. Each ADC provides 4 Interrupts sources and 6 Flags which can be divided into 3 groups: I. Flags and Interrupts for ADC regular channels ================================================= Flags : ---------- 1. ADC_FLAG_OVR : Overrun detection when regular converted data are lost 2. ADC_FLAG_EOC : Regular channel end of conversion ==> to indicate (depending on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() ) the end of: ==> a regular CHANNEL conversion ==> sequence of regular GROUP conversions . 3. ADC_FLAG_STRT: Regular channel start ==> to indicate when regular CHANNEL conversion starts. Interrupts : ------------ 1. ADC_IT_OVR : specifies the interrupt source for Overrun detection event. 2. ADC_IT_EOC : specifies the interrupt source for Regular channel end of conversion event. II. Flags and Interrupts for ADC Injected channels ================================================= Flags : ---------- 1. ADC_FLAG_JEOC : Injected channel end of conversion ==> to indicate at the end of injected GROUP conversion 2. ADC_FLAG_JSTRT: Injected channel start ==> to indicate hardware when injected GROUP conversion starts. Interrupts : ------------ 1. ADC_IT_JEOC : specifies the interrupt source for Injected channel end of conversion event. III. General Flags and Interrupts for the ADC ================================================= Flags : ---------- 1. ADC_FLAG_AWD: Analog watchdog ==> to indicate if the converted voltage crosses the programmed thresholds values. Interrupts : ------------ 1. ADC_IT_AWD : specifies the interrupt source for Analog watchdog event. The user should identify which mode will be used in his application to manage the ADC controller events: Polling mode or Interrupt mode. In the Polling Mode it is advised to use the following functions: - ADC_GetFlagStatus() : to check if flags events occur. - ADC_ClearFlag() : to clear the flags events. In the Interrupt Mode it is advised to use the following functions: - ADC_ITConfig() : to enable or disable the interrupt source. - ADC_GetITStatus() : to check if Interrupt occurs. - ADC_ClearITPendingBit() : to clear the Interrupt pending Bit (corresponding Flag). @endverbatim * @{ */ /** * @brief Enables or disables the specified ADC interrupts. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. * This parameter can be one of the following values: * @arg ADC_IT_EOC: End of conversion interrupt mask * @arg ADC_IT_AWD: Analog watchdog interrupt mask * @arg ADC_IT_JEOC: End of injected conversion interrupt mask * @arg ADC_IT_OVR: Overrun interrupt enable * @param NewState: new state of the specified ADC interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) { uint32_t itmask = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); assert_param(IS_ADC_IT(ADC_IT)); /* Get the ADC IT index */ itmask = (uint8_t)ADC_IT; itmask = (uint32_t)0x01 << itmask; if (NewState != DISABLE) { /* Enable the selected ADC interrupts */ ADCx->CR1 |= itmask; } else { /* Disable the selected ADC interrupts */ ADCx->CR1 &= (~(uint32_t)itmask); } } /** * @brief Checks whether the specified ADC flag is set or not. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg ADC_FLAG_AWD: Analog watchdog flag * @arg ADC_FLAG_EOC: End of conversion flag * @arg ADC_FLAG_JEOC: End of injected group conversion flag * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag * @arg ADC_FLAG_STRT: Start of regular group conversion flag * @arg ADC_FLAG_OVR: Overrun flag * @retval The new state of ADC_FLAG (SET or RESET). */ FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); /* Check the status of the specified ADC flag */ if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET) { /* ADC_FLAG is set */ bitstatus = SET; } else { /* ADC_FLAG is reset */ bitstatus = RESET; } /* Return the ADC_FLAG status */ return bitstatus; } /** * @brief Clears the ADCx's pending flags. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_FLAG: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg ADC_FLAG_AWD: Analog watchdog flag * @arg ADC_FLAG_EOC: End of conversion flag * @arg ADC_FLAG_JEOC: End of injected group conversion flag * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag * @arg ADC_FLAG_STRT: Start of regular group conversion flag * @arg ADC_FLAG_OVR: Overrun flag * @retval None */ void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); /* Clear the selected ADC flags */ ADCx->SR = ~(uint32_t)ADC_FLAG; } /** * @brief Checks whether the specified ADC interrupt has occurred or not. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_IT: specifies the ADC interrupt source to check. * This parameter can be one of the following values: * @arg ADC_IT_EOC: End of conversion interrupt mask * @arg ADC_IT_AWD: Analog watchdog interrupt mask * @arg ADC_IT_JEOC: End of injected conversion interrupt mask * @arg ADC_IT_OVR: Overrun interrupt mask * @retval The new state of ADC_IT (SET or RESET). */ ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) { ITStatus bitstatus = RESET; uint32_t itmask = 0, enablestatus = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_IT(ADC_IT)); /* Get the ADC IT index */ itmask = ADC_IT >> 8; /* Get the ADC_IT enable bit status */ enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)) ; /* Check the status of the specified ADC interrupt */ if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus) { /* ADC_IT is set */ bitstatus = SET; } else { /* ADC_IT is reset */ bitstatus = RESET; } /* Return the ADC_IT status */ return bitstatus; } /** * @brief Clears the ADCx's interrupt pending bits. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_IT: specifies the ADC interrupt pending bit to clear. * This parameter can be one of the following values: * @arg ADC_IT_EOC: End of conversion interrupt mask * @arg ADC_IT_AWD: Analog watchdog interrupt mask * @arg ADC_IT_JEOC: End of injected conversion interrupt mask * @arg ADC_IT_OVR: Overrun interrupt mask * @retval None */ void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) { uint8_t itmask = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_IT(ADC_IT)); /* Get the ADC IT index */ itmask = (uint8_t)(ADC_IT >> 8); /* Clear the selected ADC interrupt pending bits */ ADCx->SR = ~(uint32_t)itmask; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c ================================================ /** ****************************************************************************** * @file stm32f4xx_can.c * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file provides firmware functions to manage the following * functionalities of the Controller area network (CAN) peripheral: * - Initialization and Configuration * - CAN Frames Transmission * - CAN Frames Reception * - Operation modes switch * - Error management * - Interrupts and flags * * @verbatim * * =================================================================== * How to use this driver * =================================================================== * 1. Enable the CAN controller interface clock using * RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE); for CAN1 * and RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE); for CAN2 * @note In case you are using CAN2 only, you have to enable the CAN1 clock. * * 2. CAN pins configuration * - Enable the clock for the CAN GPIOs using the following function: * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); * - Connect the involved CAN pins to AF9 using the following function * GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_CANx); * - Configure these CAN pins in alternate function mode by calling * the function GPIO_Init(); * * 3. Initialise and configure the CAN using CAN_Init() and * CAN_FilterInit() functions. * * 4. Transmit the desired CAN frame using CAN_Transmit() function. * * 5. Check the transmission of a CAN frame using CAN_TransmitStatus() * function. * * 6. Cancel the transmission of a CAN frame using CAN_CancelTransmit() * function. * * 7. Receive a CAN frame using CAN_Recieve() function. * * 8. Release the receive FIFOs using CAN_FIFORelease() function. * * 9. Return the number of pending received frames using * CAN_MessagePending() function. * * 10. To control CAN events you can use one of the following two methods: * - Check on CAN flags using the CAN_GetFlagStatus() function. * - Use CAN interrupts through the function CAN_ITConfig() at * initialization phase and CAN_GetITStatus() function into * interrupt routines to check if the event has occurred or not. * After checking on a flag you should clear it using CAN_ClearFlag() * function. And after checking on an interrupt event you should * clear it using CAN_ClearITPendingBit() function. * * * @endverbatim * ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_can.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup CAN * @brief CAN driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* CAN Master Control Register bits */ #define MCR_DBF ((uint32_t)0x00010000) /* software master reset */ /* CAN Mailbox Transmit Request */ #define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */ /* CAN Filter Master Register bits */ #define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */ /* Time out for INAK bit */ #define INAK_TIMEOUT ((uint32_t)0x0000FFFF) /* Time out for SLAK bit */ #define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) /* Flags in TSR register */ #define CAN_FLAGS_TSR ((uint32_t)0x08000000) /* Flags in RF1R register */ #define CAN_FLAGS_RF1R ((uint32_t)0x04000000) /* Flags in RF0R register */ #define CAN_FLAGS_RF0R ((uint32_t)0x02000000) /* Flags in MSR register */ #define CAN_FLAGS_MSR ((uint32_t)0x01000000) /* Flags in ESR register */ #define CAN_FLAGS_ESR ((uint32_t)0x00F00000) /* Mailboxes definition */ #define CAN_TXMAILBOX_0 ((uint8_t)0x00) #define CAN_TXMAILBOX_1 ((uint8_t)0x01) #define CAN_TXMAILBOX_2 ((uint8_t)0x02) #define CAN_MODE_MASK ((uint32_t) 0x00000003) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); /** @defgroup CAN_Private_Functions * @{ */ /** @defgroup CAN_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== Initialization and Configuration functions =============================================================================== This section provides functions allowing to - Initialize the CAN peripherals : Prescaler, operating mode, the maximum number of time quanta to perform resynchronization, the number of time quanta in Bit Segment 1 and 2 and many other modes. Refer to @ref CAN_InitTypeDef for more details. - Configures the CAN reception filter. - Select the start bank filter for slave CAN. - Enables or disables the Debug Freeze mode for CAN - Enables or disables the CAN Time Trigger Operation communication mode @endverbatim * @{ */ /** * @brief Deinitializes the CAN peripheral registers to their default reset values. * @param CANx: where x can be 1 or 2 to select the CAN peripheral. * @retval None. */ void CAN_DeInit(CAN_TypeDef* CANx) { /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); if (CANx == CAN1) { /* Enable CAN1 reset state */ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); /* Release CAN1 from reset state */ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); } else { /* Enable CAN2 reset state */ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); /* Release CAN2 from reset state */ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); } } /** * @brief Initializes the CAN peripheral according to the specified * parameters in the CAN_InitStruct. * @param CANx: where x can be 1 or 2 to select the CAN peripheral. * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that contains * the configuration information for the CAN peripheral. * @retval Constant indicates initialization succeed which will be * CAN_InitStatus_Failed or CAN_InitStatus_Success. */ uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) { uint8_t InitStatus = CAN_InitStatus_Failed; uint32_t wait_ack = 0x00000000; /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); /* Exit from sleep mode */ CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP); /* Request initialisation */ CANx->MCR |= CAN_MCR_INRQ ; /* Wait the acknowledge */ while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) { wait_ack++; } /* Check acknowledge */ if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) { InitStatus = CAN_InitStatus_Failed; } else { /* Set the time triggered communication mode */ if (CAN_InitStruct->CAN_TTCM == ENABLE) { CANx->MCR |= CAN_MCR_TTCM; } else { CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM; } /* Set the automatic bus-off management */ if (CAN_InitStruct->CAN_ABOM == ENABLE) { CANx->MCR |= CAN_MCR_ABOM; } else { CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM; } /* Set the automatic wake-up mode */ if (CAN_InitStruct->CAN_AWUM == ENABLE) { CANx->MCR |= CAN_MCR_AWUM; } else { CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM; } /* Set the no automatic retransmission */ if (CAN_InitStruct->CAN_NART == ENABLE) { CANx->MCR |= CAN_MCR_NART; } else { CANx->MCR &= ~(uint32_t)CAN_MCR_NART; } /* Set the receive FIFO locked mode */ if (CAN_InitStruct->CAN_RFLM == ENABLE) { CANx->MCR |= CAN_MCR_RFLM; } else { CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM; } /* Set the transmit FIFO priority */ if (CAN_InitStruct->CAN_TXFP == ENABLE) { CANx->MCR |= CAN_MCR_TXFP; } else { CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP; } /* Set the bit timing register */ CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \ ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \ ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \ ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \ ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); /* Request leave initialisation */ CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ; /* Wait the acknowledge */ wait_ack = 0; while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) { wait_ack++; } /* ...and check acknowledged */ if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) { InitStatus = CAN_InitStatus_Failed; } else { InitStatus = CAN_InitStatus_Success ; } } /* At this step, return the status of initialization */ return InitStatus; } /** * @brief Configures the CAN reception filter according to the specified * parameters in the CAN_FilterInitStruct. * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef structure that * contains the configuration information. * @retval None */ void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) { uint32_t filter_number_bit_pos = 0; /* Check the parameters */ assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber; /* Initialisation mode for the filter */ CAN1->FMR |= FMR_FINIT; /* Filter Deactivation */ CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos; /* Filter Scale */ if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) { /* 16-bit scale for the filter */ CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos; /* First 16-bit identifier and First 16-bit mask */ /* Or First 16-bit identifier and Second 16-bit identifier */ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); /* Second 16-bit identifier and Second 16-bit mask */ /* Or Third 16-bit identifier and Fourth 16-bit identifier */ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); } if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) { /* 32-bit scale for the filter */ CAN1->FS1R |= filter_number_bit_pos; /* 32-bit identifier or First 32-bit identifier */ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); /* 32-bit mask or Second 32-bit identifier */ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); } /* Filter Mode */ if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) { /*Id/Mask mode for the filter*/ CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos; } else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ { /*Identifier list mode for the filter*/ CAN1->FM1R |= (uint32_t)filter_number_bit_pos; } /* Filter FIFO assignment */ if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0) { /* FIFO 0 assignation for the filter */ CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos; } if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1) { /* FIFO 1 assignation for the filter */ CAN1->FFA1R |= (uint32_t)filter_number_bit_pos; } /* Filter activation */ if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) { CAN1->FA1R |= filter_number_bit_pos; } /* Leave the initialisation mode for the filter */ CAN1->FMR &= ~FMR_FINIT; } /** * @brief Fills each CAN_InitStruct member with its default value. * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which ill be initialized. * @retval None */ void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) { /* Reset CAN init structure parameters values */ /* Initialize the time triggered communication mode */ CAN_InitStruct->CAN_TTCM = DISABLE; /* Initialize the automatic bus-off management */ CAN_InitStruct->CAN_ABOM = DISABLE; /* Initialize the automatic wake-up mode */ CAN_InitStruct->CAN_AWUM = DISABLE; /* Initialize the no automatic retransmission */ CAN_InitStruct->CAN_NART = DISABLE; /* Initialize the receive FIFO locked mode */ CAN_InitStruct->CAN_RFLM = DISABLE; /* Initialize the transmit FIFO priority */ CAN_InitStruct->CAN_TXFP = DISABLE; /* Initialize the CAN_Mode member */ CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; /* Initialize the CAN_SJW member */ CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; /* Initialize the CAN_BS1 member */ CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; /* Initialize the CAN_BS2 member */ CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; /* Initialize the CAN_Prescaler member */ CAN_InitStruct->CAN_Prescaler = 1; } /** * @brief Select the start bank filter for slave CAN. * @param CAN_BankNumber: Select the start slave bank filter from 1..27. * @retval None */ void CAN_SlaveStartBank(uint8_t CAN_BankNumber) { /* Check the parameters */ assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber)); /* Enter Initialisation mode for the filter */ CAN1->FMR |= FMR_FINIT; /* Select the start slave bank */ CAN1->FMR &= (uint32_t)0xFFFFC0F1 ; CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8; /* Leave Initialisation mode for the filter */ CAN1->FMR &= ~FMR_FINIT; } /** * @brief Enables or disables the DBG Freeze for CAN. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. * @param NewState: new state of the CAN peripheral. * This parameter can be: ENABLE (CAN reception/transmission is frozen * during debug. Reception FIFOs can still be accessed/controlled normally) * or DISABLE (CAN is working during debug). * @retval None */ void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable Debug Freeze */ CANx->MCR |= MCR_DBF; } else { /* Disable Debug Freeze */ CANx->MCR &= ~MCR_DBF; } } /** * @brief Enables or disables the CAN Time TriggerOperation communication mode. * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be * sent over the CAN bus. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. * @param NewState: Mode new state. This parameter can be: ENABLE or DISABLE. * When enabled, Time stamp (TIME[15:0]) value is sent in the last two * data bytes of the 8-byte message: TIME[7:0] in data byte 6 and TIME[15:8] * in data byte 7. * @retval None */ void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the TTCM mode */ CANx->MCR |= CAN_MCR_TTCM; /* Set TGT bits */ CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT); CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT); CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT); } else { /* Disable the TTCM mode */ CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM); /* Reset TGT bits */ CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT); CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT); CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT); } } /** * @} */ /** @defgroup CAN_Group2 CAN Frames Transmission functions * @brief CAN Frames Transmission functions * @verbatim =============================================================================== CAN Frames Transmission functions =============================================================================== This section provides functions allowing to - Initiate and transmit a CAN frame message (if there is an empty mailbox). - Check the transmission status of a CAN Frame - Cancel a transmit request @endverbatim * @{ */ /** * @brief Initiates and transmits a CAN frame message. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. * @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data. * @retval The number of the mailbox that is used for transmission or * CAN_TxStatus_NoMailBox if there is no empty mailbox. */ uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) { uint8_t transmit_mailbox = 0; /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); assert_param(IS_CAN_IDTYPE(TxMessage->IDE)); assert_param(IS_CAN_RTR(TxMessage->RTR)); assert_param(IS_CAN_DLC(TxMessage->DLC)); /* Select one empty transmit mailbox */ if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) { transmit_mailbox = 0; } else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) { transmit_mailbox = 1; } else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) { transmit_mailbox = 2; } else { transmit_mailbox = CAN_TxStatus_NoMailBox; } if (transmit_mailbox != CAN_TxStatus_NoMailBox) { /* Set up the Id */ CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ; if (TxMessage->IDE == CAN_Id_Standard) { assert_param(IS_CAN_STDID(TxMessage->StdId)); CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \ TxMessage->RTR); } else { assert_param(IS_CAN_EXTID(TxMessage->ExtId)); CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \ TxMessage->IDE | \ TxMessage->RTR); } /* Set up the DLC */ TxMessage->DLC &= (uint8_t)0x0000000F; CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0; CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC; /* Set up the data field */ CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | ((uint32_t)TxMessage->Data[2] << 16) | ((uint32_t)TxMessage->Data[1] << 8) | ((uint32_t)TxMessage->Data[0])); CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | ((uint32_t)TxMessage->Data[6] << 16) | ((uint32_t)TxMessage->Data[5] << 8) | ((uint32_t)TxMessage->Data[4])); /* Request transmission */ CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ; } return transmit_mailbox; } /** * @brief Checks the transmission status of a CAN Frame. * @param CANx: where x can be 1 or 2 to select the CAN peripheral. * @param TransmitMailbox: the number of the mailbox that is used for transmission. * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, * CAN_TxStatus_Failed in an other case. */ uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) { uint32_t state = 0; /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); switch (TransmitMailbox) { case (CAN_TXMAILBOX_0): state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0); break; case (CAN_TXMAILBOX_1): state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1); break; case (CAN_TXMAILBOX_2): state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2); break; default: state = CAN_TxStatus_Failed; break; } switch (state) { /* transmit pending */ case (0x0): state = CAN_TxStatus_Pending; break; /* transmit failed */ case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed; break; case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed; break; case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed; break; /* transmit succeeded */ case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok; break; case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok; break; case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok; break; default: state = CAN_TxStatus_Failed; break; } return (uint8_t) state; } /** * @brief Cancels a transmit request. * @param CANx: where x can be 1 or 2 to select the CAN peripheral. * @param Mailbox: Mailbox number. * @retval None */ void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) { /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); /* abort transmission */ switch (Mailbox) { case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0; break; case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1; break; case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2; break; default: break; } } /** * @} */ /** @defgroup CAN_Group3 CAN Frames Reception functions * @brief CAN Frames Reception functions * @verbatim =============================================================================== CAN Frames Reception functions =============================================================================== This section provides functions allowing to - Receive a correct CAN frame - Release a specified receive FIFO (2 FIFOs are available) - Return the number of the pending received CAN frames @endverbatim * @{ */ /** * @brief Receives a correct CAN frame. * @param CANx: where x can be 1 or 2 to select the CAN peripheral. * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. * @param RxMessage: pointer to a structure receive frame which contains CAN Id, * CAN DLC, CAN data and FMI number. * @retval None */ void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) { /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); assert_param(IS_CAN_FIFO(FIFONumber)); /* Get the Id */ RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR; if (RxMessage->IDE == CAN_Id_Standard) { RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21); } else { RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3); } RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR; /* Get the DLC */ RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR; /* Get the FMI */ RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8); /* Get the data field */ RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR; RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8); RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16); RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24); RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR; RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8); RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16); RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24); /* Release the FIFO */ /* Release FIFO0 */ if (FIFONumber == CAN_FIFO0) { CANx->RF0R |= CAN_RF0R_RFOM0; } /* Release FIFO1 */ else /* FIFONumber == CAN_FIFO1 */ { CANx->RF1R |= CAN_RF1R_RFOM1; } } /** * @brief Releases the specified receive FIFO. * @param CANx: where x can be 1 or 2 to select the CAN peripheral. * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1. * @retval None */ void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) { /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); assert_param(IS_CAN_FIFO(FIFONumber)); /* Release FIFO0 */ if (FIFONumber == CAN_FIFO0) { CANx->RF0R |= CAN_RF0R_RFOM0; } /* Release FIFO1 */ else /* FIFONumber == CAN_FIFO1 */ { CANx->RF1R |= CAN_RF1R_RFOM1; } } /** * @brief Returns the number of pending received messages. * @param CANx: where x can be 1 or 2 to select the CAN peripheral. * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. * @retval NbMessage : which is the number of pending message. */ uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) { uint8_t message_pending=0; /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); assert_param(IS_CAN_FIFO(FIFONumber)); if (FIFONumber == CAN_FIFO0) { message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03); } else if (FIFONumber == CAN_FIFO1) { message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03); } else { message_pending = 0; } return message_pending; } /** * @} */ /** @defgroup CAN_Group4 CAN Operation modes functions * @brief CAN Operation modes functions * @verbatim =============================================================================== CAN Operation modes functions =============================================================================== This section provides functions allowing to select the CAN Operation modes - sleep mode - normal mode - initialization mode @endverbatim * @{ */ /** * @brief Selects the CAN Operation mode. * @param CAN_OperatingMode: CAN Operating Mode. * This parameter can be one of @ref CAN_OperatingMode_TypeDef enumeration. * @retval status of the requested mode which can be * - CAN_ModeStatus_Failed: CAN failed entering the specific mode * - CAN_ModeStatus_Success: CAN Succeed entering the specific mode */ uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode) { uint8_t status = CAN_ModeStatus_Failed; /* Timeout for INAK or also for SLAK bits*/ uint32_t timeout = INAK_TIMEOUT; /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode)); if (CAN_OperatingMode == CAN_OperatingMode_Initialization) { /* Request initialisation */ CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ); /* Wait the acknowledge */ while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0)) { timeout--; } if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) { status = CAN_ModeStatus_Failed; } else { status = CAN_ModeStatus_Success; } } else if (CAN_OperatingMode == CAN_OperatingMode_Normal) { /* Request leave initialisation and sleep mode and enter Normal mode */ CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ)); /* Wait the acknowledge */ while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0)) { timeout--; } if ((CANx->MSR & CAN_MODE_MASK) != 0) { status = CAN_ModeStatus_Failed; } else { status = CAN_ModeStatus_Success; } } else if (CAN_OperatingMode == CAN_OperatingMode_Sleep) { /* Request Sleep mode */ CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); /* Wait the acknowledge */ while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0)) { timeout--; } if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) { status = CAN_ModeStatus_Failed; } else { status = CAN_ModeStatus_Success; } } else { status = CAN_ModeStatus_Failed; } return (uint8_t) status; } /** * @brief Enters the Sleep (low power) mode. * @param CANx: where x can be 1 or 2 to select the CAN peripheral. * @retval CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed otherwise. */ uint8_t CAN_Sleep(CAN_TypeDef* CANx) { uint8_t sleepstatus = CAN_Sleep_Failed; /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); /* Request Sleep mode */ CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); /* Sleep mode status */ if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK) { /* Sleep mode not entered */ sleepstatus = CAN_Sleep_Ok; } /* return sleep mode status */ return (uint8_t)sleepstatus; } /** * @brief Wakes up the CAN peripheral from sleep mode . * @param CANx: where x can be 1 or 2 to select the CAN peripheral. * @retval CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed otherwise. */ uint8_t CAN_WakeUp(CAN_TypeDef* CANx) { uint32_t wait_slak = SLAK_TIMEOUT; uint8_t wakeupstatus = CAN_WakeUp_Failed; /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); /* Wake up request */ CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP; /* Sleep mode status */ while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00)) { wait_slak--; } if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK) { /* wake up done : Sleep mode exited */ wakeupstatus = CAN_WakeUp_Ok; } /* return wakeup status */ return (uint8_t)wakeupstatus; } /** * @} */ /** @defgroup CAN_Group5 CAN Bus Error management functions * @brief CAN Bus Error management functions * @verbatim =============================================================================== CAN Bus Error management functions =============================================================================== This section provides functions allowing to - Return the CANx's last error code (LEC) - Return the CANx Receive Error Counter (REC) - Return the LSB of the 9-bit CANx Transmit Error Counter(TEC). @note If TEC is greater than 255, The CAN is in bus-off state. @note if REC or TEC are greater than 96, an Error warning flag occurs. @note if REC or TEC are greater than 127, an Error Passive Flag occurs. @endverbatim * @{ */ /** * @brief Returns the CANx's last error code (LEC). * @param CANx: where x can be 1 or 2 to select the CAN peripheral. * @retval Error code: * - CAN_ERRORCODE_NoErr: No Error * - CAN_ERRORCODE_StuffErr: Stuff Error * - CAN_ERRORCODE_FormErr: Form Error * - CAN_ERRORCODE_ACKErr : Acknowledgment Error * - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error * - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error * - CAN_ERRORCODE_CRCErr: CRC Error * - CAN_ERRORCODE_SoftwareSetErr: Software Set Error */ uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx) { uint8_t errorcode=0; /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); /* Get the error code*/ errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC); /* Return the error code*/ return errorcode; } /** * @brief Returns the CANx Receive Error Counter (REC). * @note In case of an error during reception, this counter is incremented * by 1 or by 8 depending on the error condition as defined by the CAN * standard. After every successful reception, the counter is * decremented by 1 or reset to 120 if its value was higher than 128. * When the counter value exceeds 127, the CAN controller enters the * error passive state. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. * @retval CAN Receive Error Counter. */ uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx) { uint8_t counter=0; /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); /* Get the Receive Error Counter*/ counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24); /* Return the Receive Error Counter*/ return counter; } /** * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. * @retval LSB of the 9-bit CAN Transmit Error Counter. */ uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx) { uint8_t counter=0; /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16); /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ return counter; } /** * @} */ /** @defgroup CAN_Group6 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== Interrupts and flags management functions =============================================================================== This section provides functions allowing to configure the CAN Interrupts and to get the status and clear flags and Interrupts pending bits. The CAN provides 14 Interrupts sources and 15 Flags: =============== Flags : =============== The 15 flags can be divided on 4 groups: A. Transmit Flags ----------------------- CAN_FLAG_RQCP0, CAN_FLAG_RQCP1, CAN_FLAG_RQCP2 : Request completed MailBoxes 0, 1 and 2 Flags Set when when the last request (transmit or abort) has been performed. B. Receive Flags ----------------------- CAN_FLAG_FMP0, CAN_FLAG_FMP1 : FIFO 0 and 1 Message Pending Flags set to signal that messages are pending in the receive FIFO. These Flags are cleared only by hardware. CAN_FLAG_FF0, CAN_FLAG_FF1 : FIFO 0 and 1 Full Flags set when three messages are stored in the selected FIFO. CAN_FLAG_FOV0 CAN_FLAG_FOV1 : FIFO 0 and 1 Overrun Flags set when a new message has been received and passed the filter while the FIFO was full. C. Operating Mode Flags ----------------------- CAN_FLAG_WKU : Wake up Flag set to signal that a SOF bit has been detected while the CAN hardware was in Sleep mode. CAN_FLAG_SLAK : Sleep acknowledge Flag Set to signal that the CAN has entered Sleep Mode. D. Error Flags ----------------------- CAN_FLAG_EWG : Error Warning Flag Set when the warning limit has been reached (Receive Error Counter or Transmit Error Counter greater than 96). This Flag is cleared only by hardware. CAN_FLAG_EPV : Error Passive Flag Set when the Error Passive limit has been reached (Receive Error Counter or Transmit Error Counter greater than 127). This Flag is cleared only by hardware. CAN_FLAG_BOF : Bus-Off Flag set when CAN enters the bus-off state. The bus-off state is entered on TEC overflow, greater than 255. This Flag is cleared only by hardware. CAN_FLAG_LEC : Last error code Flag set If a message has been transferred (reception or transmission) with error, and the error code is hold. =============== Interrupts : =============== The 14 interrupts can be divided on 4 groups: A. Transmit interrupt ----------------------- CAN_IT_TME : Transmit mailbox empty Interrupt if enabled, this interrupt source is pending when no transmit request are pending for Tx mailboxes. B. Receive Interrupts ----------------------- CAN_IT_FMP0, CAN_IT_FMP1 : FIFO 0 and FIFO1 message pending Interrupts if enabled, these interrupt sources are pending when messages are pending in the receive FIFO. The corresponding interrupt pending bits are cleared only by hardware. CAN_IT_FF0, CAN_IT_FF1 : FIFO 0 and FIFO1 full Interrupts if enabled, these interrupt sources are pending when three messages are stored in the selected FIFO. CAN_IT_FOV0, CAN_IT_FOV1 : FIFO 0 and FIFO1 overrun Interrupts if enabled, these interrupt sources are pending when a new message has been received and passed the filter while the FIFO was full. C. Operating Mode Interrupts ------------------------------- CAN_IT_WKU : Wake-up Interrupt if enabled, this interrupt source is pending when a SOF bit has been detected while the CAN hardware was in Sleep mode. CAN_IT_SLK : Sleep acknowledge Interrupt if enabled, this interrupt source is pending when the CAN has entered Sleep Mode. D. Error Interrupts ----------------------- CAN_IT_EWG : Error warning Interrupt if enabled, this interrupt source is pending when the warning limit has been reached (Receive Error Counter or Transmit Error Counter=96). CAN_IT_EPV : Error passive Interrupt if enabled, this interrupt source is pending when the Error Passive limit has been reached (Receive Error Counter or Transmit Error Counter>127). CAN_IT_BOF : Bus-off Interrupt if enabled, this interrupt source is pending when CAN enters the bus-off state. The bus-off state is entered on TEC overflow, greater than 255. This Flag is cleared only by hardware. CAN_IT_LEC : Last error code Interrupt if enabled, this interrupt source is pending when a message has been transferred (reception or transmission) with error, and the error code is hold. CAN_IT_ERR : Error Interrupt if enabled, this interrupt source is pending when an error condition is pending. Managing the CAN controller events : ------------------------------------ The user should identify which mode will be used in his application to manage the CAN controller events: Polling mode or Interrupt mode. 1. In the Polling Mode it is advised to use the following functions: - CAN_GetFlagStatus() : to check if flags events occur. - CAN_ClearFlag() : to clear the flags events. 2. In the Interrupt Mode it is advised to use the following functions: - CAN_ITConfig() : to enable or disable the interrupt source. - CAN_GetITStatus() : to check if Interrupt occurs. - CAN_ClearITPendingBit() : to clear the Interrupt pending Bit (corresponding Flag). @note This function has no impact on CAN_IT_FMP0 and CAN_IT_FMP1 Interrupts pending bits since there are cleared only by hardware. @endverbatim * @{ */ /** * @brief Enables or disables the specified CANx interrupts. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled. * This parameter can be: * @arg CAN_IT_TME: Transmit mailbox empty Interrupt * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt * @arg CAN_IT_FF0: FIFO 0 full Interrupt * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt * @arg CAN_IT_FF1: FIFO 1 full Interrupt * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt * @arg CAN_IT_WKU: Wake-up Interrupt * @arg CAN_IT_SLK: Sleep acknowledge Interrupt * @arg CAN_IT_EWG: Error warning Interrupt * @arg CAN_IT_EPV: Error passive Interrupt * @arg CAN_IT_BOF: Bus-off Interrupt * @arg CAN_IT_LEC: Last error code Interrupt * @arg CAN_IT_ERR: Error Interrupt * @param NewState: new state of the CAN interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); assert_param(IS_CAN_IT(CAN_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected CANx interrupt */ CANx->IER |= CAN_IT; } else { /* Disable the selected CANx interrupt */ CANx->IER &= ~CAN_IT; } } /** * @brief Checks whether the specified CAN flag is set or not. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. * @param CAN_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag * @arg CAN_FLAG_FF0: FIFO 0 Full Flag * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag * @arg CAN_FLAG_FF1: FIFO 1 Full Flag * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag * @arg CAN_FLAG_WKU: Wake up Flag * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag * @arg CAN_FLAG_EWG: Error Warning Flag * @arg CAN_FLAG_EPV: Error Passive Flag * @arg CAN_FLAG_BOF: Bus-Off Flag * @arg CAN_FLAG_LEC: Last error code Flag * @retval The new state of CAN_FLAG (SET or RESET). */ FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); assert_param(IS_CAN_GET_FLAG(CAN_FLAG)); if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET) { /* Check the status of the specified CAN flag */ if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) { /* CAN_FLAG is set */ bitstatus = SET; } else { /* CAN_FLAG is reset */ bitstatus = RESET; } } else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET) { /* Check the status of the specified CAN flag */ if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) { /* CAN_FLAG is set */ bitstatus = SET; } else { /* CAN_FLAG is reset */ bitstatus = RESET; } } else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET) { /* Check the status of the specified CAN flag */ if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) { /* CAN_FLAG is set */ bitstatus = SET; } else { /* CAN_FLAG is reset */ bitstatus = RESET; } } else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET) { /* Check the status of the specified CAN flag */ if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) { /* CAN_FLAG is set */ bitstatus = SET; } else { /* CAN_FLAG is reset */ bitstatus = RESET; } } else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */ { /* Check the status of the specified CAN flag */ if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) { /* CAN_FLAG is set */ bitstatus = SET; } else { /* CAN_FLAG is reset */ bitstatus = RESET; } } /* Return the CAN_FLAG status */ return bitstatus; } /** * @brief Clears the CAN's pending flags. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. * @param CAN_FLAG: specifies the flag to clear. * This parameter can be one of the following values: * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag * @arg CAN_FLAG_FF0: FIFO 0 Full Flag * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag * @arg CAN_FLAG_FF1: FIFO 1 Full Flag * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag * @arg CAN_FLAG_WKU: Wake up Flag * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag * @arg CAN_FLAG_LEC: Last error code Flag * @retval None */ void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) { uint32_t flagtmp=0; /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG)); if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */ { /* Clear the selected CAN flags */ CANx->ESR = (uint32_t)RESET; } else /* MSR or TSR or RF0R or RF1R */ { flagtmp = CAN_FLAG & 0x000FFFFF; if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET) { /* Receive Flags */ CANx->RF0R = (uint32_t)(flagtmp); } else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET) { /* Receive Flags */ CANx->RF1R = (uint32_t)(flagtmp); } else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET) { /* Transmit Flags */ CANx->TSR = (uint32_t)(flagtmp); } else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */ { /* Operating mode Flags */ CANx->MSR = (uint32_t)(flagtmp); } } } /** * @brief Checks whether the specified CANx interrupt has occurred or not. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. * @param CAN_IT: specifies the CAN interrupt source to check. * This parameter can be one of the following values: * @arg CAN_IT_TME: Transmit mailbox empty Interrupt * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt * @arg CAN_IT_FF0: FIFO 0 full Interrupt * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt * @arg CAN_IT_FF1: FIFO 1 full Interrupt * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt * @arg CAN_IT_WKU: Wake-up Interrupt * @arg CAN_IT_SLK: Sleep acknowledge Interrupt * @arg CAN_IT_EWG: Error warning Interrupt * @arg CAN_IT_EPV: Error passive Interrupt * @arg CAN_IT_BOF: Bus-off Interrupt * @arg CAN_IT_LEC: Last error code Interrupt * @arg CAN_IT_ERR: Error Interrupt * @retval The current state of CAN_IT (SET or RESET). */ ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) { ITStatus itstatus = RESET; /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); assert_param(IS_CAN_IT(CAN_IT)); /* check the interrupt enable bit */ if((CANx->IER & CAN_IT) != RESET) { /* in case the Interrupt is enabled, .... */ switch (CAN_IT) { case CAN_IT_TME: /* Check CAN_TSR_RQCPx bits */ itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2); break; case CAN_IT_FMP0: /* Check CAN_RF0R_FMP0 bit */ itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0); break; case CAN_IT_FF0: /* Check CAN_RF0R_FULL0 bit */ itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0); break; case CAN_IT_FOV0: /* Check CAN_RF0R_FOVR0 bit */ itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0); break; case CAN_IT_FMP1: /* Check CAN_RF1R_FMP1 bit */ itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1); break; case CAN_IT_FF1: /* Check CAN_RF1R_FULL1 bit */ itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1); break; case CAN_IT_FOV1: /* Check CAN_RF1R_FOVR1 bit */ itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1); break; case CAN_IT_WKU: /* Check CAN_MSR_WKUI bit */ itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI); break; case CAN_IT_SLK: /* Check CAN_MSR_SLAKI bit */ itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI); break; case CAN_IT_EWG: /* Check CAN_ESR_EWGF bit */ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF); break; case CAN_IT_EPV: /* Check CAN_ESR_EPVF bit */ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF); break; case CAN_IT_BOF: /* Check CAN_ESR_BOFF bit */ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF); break; case CAN_IT_LEC: /* Check CAN_ESR_LEC bit */ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC); break; case CAN_IT_ERR: /* Check CAN_MSR_ERRI bit */ itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI); break; default: /* in case of error, return RESET */ itstatus = RESET; break; } } else { /* in case the Interrupt is not enabled, return RESET */ itstatus = RESET; } /* Return the CAN_IT status */ return itstatus; } /** * @brief Clears the CANx's interrupt pending bits. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. * @param CAN_IT: specifies the interrupt pending bit to clear. * This parameter can be one of the following values: * @arg CAN_IT_TME: Transmit mailbox empty Interrupt * @arg CAN_IT_FF0: FIFO 0 full Interrupt * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt * @arg CAN_IT_FF1: FIFO 1 full Interrupt * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt * @arg CAN_IT_WKU: Wake-up Interrupt * @arg CAN_IT_SLK: Sleep acknowledge Interrupt * @arg CAN_IT_EWG: Error warning Interrupt * @arg CAN_IT_EPV: Error passive Interrupt * @arg CAN_IT_BOF: Bus-off Interrupt * @arg CAN_IT_LEC: Last error code Interrupt * @arg CAN_IT_ERR: Error Interrupt * @retval None */ void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) { /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); assert_param(IS_CAN_CLEAR_IT(CAN_IT)); switch (CAN_IT) { case CAN_IT_TME: /* Clear CAN_TSR_RQCPx (rc_w1)*/ CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2; break; case CAN_IT_FF0: /* Clear CAN_RF0R_FULL0 (rc_w1)*/ CANx->RF0R = CAN_RF0R_FULL0; break; case CAN_IT_FOV0: /* Clear CAN_RF0R_FOVR0 (rc_w1)*/ CANx->RF0R = CAN_RF0R_FOVR0; break; case CAN_IT_FF1: /* Clear CAN_RF1R_FULL1 (rc_w1)*/ CANx->RF1R = CAN_RF1R_FULL1; break; case CAN_IT_FOV1: /* Clear CAN_RF1R_FOVR1 (rc_w1)*/ CANx->RF1R = CAN_RF1R_FOVR1; break; case CAN_IT_WKU: /* Clear CAN_MSR_WKUI (rc_w1)*/ CANx->MSR = CAN_MSR_WKUI; break; case CAN_IT_SLK: /* Clear CAN_MSR_SLAKI (rc_w1)*/ CANx->MSR = CAN_MSR_SLAKI; break; case CAN_IT_EWG: /* Clear CAN_MSR_ERRI (rc_w1) */ CANx->MSR = CAN_MSR_ERRI; /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ break; case CAN_IT_EPV: /* Clear CAN_MSR_ERRI (rc_w1) */ CANx->MSR = CAN_MSR_ERRI; /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ break; case CAN_IT_BOF: /* Clear CAN_MSR_ERRI (rc_w1) */ CANx->MSR = CAN_MSR_ERRI; /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ break; case CAN_IT_LEC: /* Clear LEC bits */ CANx->ESR = RESET; /* Clear CAN_MSR_ERRI (rc_w1) */ CANx->MSR = CAN_MSR_ERRI; break; case CAN_IT_ERR: /*Clear LEC bits */ CANx->ESR = RESET; /* Clear CAN_MSR_ERRI (rc_w1) */ CANx->MSR = CAN_MSR_ERRI; /* @note BOFF, EPVF and EWGF Flags are cleared by hardware depending on the CAN Bus status*/ break; default: break; } } /** * @} */ /** * @brief Checks whether the CAN interrupt has occurred or not. * @param CAN_Reg: specifies the CAN interrupt register to check. * @param It_Bit: specifies the interrupt source bit to check. * @retval The new state of the CAN Interrupt (SET or RESET). */ static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) { ITStatus pendingbitstatus = RESET; if ((CAN_Reg & It_Bit) != (uint32_t)RESET) { /* CAN_IT is set */ pendingbitstatus = SET; } else { /* CAN_IT is reset */ pendingbitstatus = RESET; } return pendingbitstatus; } /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_crc.c ================================================ /** ****************************************************************************** * @file stm32f4xx_crc.c * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file provides all the CRC firmware functions. ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_crc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup CRC * @brief CRC driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup CRC_Private_Functions * @{ */ /** * @brief Resets the CRC Data register (DR). * @param None * @retval None */ void CRC_ResetDR(void) { /* Reset CRC generator */ CRC->CR = CRC_CR_RESET; } /** * @brief Computes the 32-bit CRC of a given data word(32-bit). * @param Data: data word(32-bit) to compute its CRC * @retval 32-bit CRC */ uint32_t CRC_CalcCRC(uint32_t Data) { CRC->DR = Data; return (CRC->DR); } /** * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). * @param pBuffer: pointer to the buffer containing the data to be computed * @param BufferLength: length of the buffer to be computed * @retval 32-bit CRC */ uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) { uint32_t index = 0; for(index = 0; index < BufferLength; index++) { CRC->DR = pBuffer[index]; } return (CRC->DR); } /** * @brief Returns the current CRC value. * @param None * @retval 32-bit CRC */ uint32_t CRC_GetCRC(void) { return (CRC->DR); } /** * @brief Stores a 8-bit data in the Independent Data(ID) register. * @param IDValue: 8-bit value to be stored in the ID register * @retval None */ void CRC_SetIDRegister(uint8_t IDValue) { CRC->IDR = IDValue; } /** * @brief Returns the 8-bit data stored in the Independent Data(ID) register * @param None * @retval 8-bit value of the ID register */ uint8_t CRC_GetIDRegister(void) { return (CRC->IDR); } /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c ================================================ /** ****************************************************************************** * @file stm32f4xx_cryp.c * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file provides firmware functions to manage the following * functionalities of the Cryptographic processor (CRYP) peripheral: * - Initialization and Configuration functions * - Data treatment functions * - Context swapping functions * - DMA interface function * - Interrupts and flags management * * @verbatim * * =================================================================== * How to use this driver * =================================================================== * 1. Enable the CRYP controller clock using * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function. * * 2. Initialise the CRYP using CRYP_Init(), CRYP_KeyInit() and if * needed CRYP_IVInit(). * * 3. Flush the IN and OUT FIFOs by using CRYP_FIFOFlush() function. * * 4. Enable the CRYP controller using the CRYP_Cmd() function. * * 5. If using DMA for Data input and output transfer, * Activate the needed DMA Requests using CRYP_DMACmd() function * 6. If DMA is not used for data transfer, use CRYP_DataIn() and * CRYP_DataOut() functions to enter data to IN FIFO and get result * from OUT FIFO. * * 7. To control CRYP events you can use one of the following * two methods: * - Check on CRYP flags using the CRYP_GetFlagStatus() function. * - Use CRYP interrupts through the function CRYP_ITConfig() at * initialization phase and CRYP_GetITStatus() function into * interrupt routines in processing phase. * * 8. Save and restore Cryptographic processor context using * CRYP_SaveContext() and CRYP_RestoreContext() functions. * * * =================================================================== * Procedure to perform an encryption or a decryption * =================================================================== * * Initialization * =============== * 1. Initialize the peripheral using CRYP_Init(), CRYP_KeyInit() and * CRYP_IVInit functions: * - Configure the key size (128-, 192- or 256-bit, in the AES only) * - Enter the symmetric key * - Configure the data type * - In case of decryption in AES-ECB or AES-CBC, you must prepare * the key: configure the key preparation mode. Then Enable the CRYP * peripheral using CRYP_Cmd() function: the BUSY flag is set. * Wait until BUSY flag is reset : the key is prepared for decryption * - Configure the algorithm and chaining (the DES/TDES in ECB/CBC, the * AES in ECB/CBC/CTR) * - Configure the direction (encryption/decryption). * - Write the initialization vectors (in CBC or CTR modes only) * * 2. Flush the IN and OUT FIFOs using the CRYP_FIFOFlush() function * * * Basic Processing mode (polling mode) * ==================================== * 1. Enable the cryptographic processor using CRYP_Cmd() function. * * 2. Write the first blocks in the input FIFO (2 to 8 words) using * CRYP_DataIn() function. * * 3. Repeat the following sequence until the complete message has been * processed: * * a) Wait for flag CRYP_FLAG_OFNE occurs (using CRYP_GetFlagStatus() * function), then read the OUT-FIFO using CRYP_DataOut() function * (1 block or until the FIFO is empty) * * b) Wait for flag CRYP_FLAG_IFNF occurs, (using CRYP_GetFlagStatus() * function then write the IN FIFO using CRYP_DataIn() function * (1 block or until the FIFO is full) * * 4. At the end of the processing, CRYP_FLAG_BUSY flag will be reset and * both FIFOs are empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is * reset). You can disable the peripheral using CRYP_Cmd() function. * * Interrupts Processing mode * =========================== * In this mode, Processing is done when the data are transferred by the * CPU during interrupts. * * 1. Enable the interrupts CRYP_IT_INI and CRYP_IT_OUTI using * CRYP_ITConfig() function. * * 2. Enable the cryptographic processor using CRYP_Cmd() function. * * 3. In the CRYP_IT_INI interrupt handler : load the input message into the * IN FIFO using CRYP_DataIn() function . You can load 2 or 4 words at a * time, or load data until the IN FIFO is full. When the last word of * the message has been entered into the IN FIFO, disable the CRYP_IT_INI * interrupt (using CRYP_ITConfig() function). * * 4. In the CRYP_IT_OUTI interrupt handler : read the output message from * the OUT FIFO using CRYP_DataOut() function. You can read 1 block (2 or * 4 words) at a time or read data until the FIFO is empty. * When the last word has been read, INIM=0, BUSY=0 and both FIFOs are * empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is reset). * You can disable the CRYP_IT_OUTI interrupt (using CRYP_ITConfig() * function) and you can disable the peripheral using CRYP_Cmd() function. * * DMA Processing mode * ==================== * In this mode, Processing is done when the DMA is used to transfer the * data from/to the memory. * * 1. Configure the DMA controller to transfer the input data from the * memory using DMA_Init() function. * The transfer length is the length of the message. * As message padding is not managed by the peripheral, the message * length must be an entire number of blocks. The data are transferred * in burst mode. The burst length is 4 words in the AES and 2 or 4 * words in the DES/TDES. The DMA should be configured to set an * interrupt on transfer completion of the output data to indicate that * the processing is finished. * Refer to DMA peripheral driver for more details. * * 2. Enable the cryptographic processor using CRYP_Cmd() function. * Enable the DMA requests CRYP_DMAReq_DataIN and CRYP_DMAReq_DataOUT * using CRYP_DMACmd() function. * * 3. All the transfers and processing are managed by the DMA and the * cryptographic processor. The DMA transfer complete interrupt indicates * that the processing is complete. Both FIFOs are normally empty and * CRYP_FLAG_BUSY flag is reset. * * @endverbatim * ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_cryp.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup CRYP * @brief CRYP driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #define FLAG_MASK ((uint8_t)0x20) #define MAX_TIMEOUT ((uint16_t)0xFFFF) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup CRYP_Private_Functions * @{ */ /** @defgroup CRYP_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== Initialization and Configuration functions =============================================================================== This section provides functions allowing to - Initialize the cryptographic Processor using CRYP_Init() function - Encrypt or Decrypt - mode : TDES-ECB, TDES-CBC, DES-ECB, DES-CBC, AES-ECB, AES-CBC, AES-CTR, AES-Key - DataType : 32-bit data, 16-bit data, bit data or bit-string - Key Size (only in AES modes) - Configure the Encrypt or Decrypt Key using CRYP_KeyInit() function - Configure the Initialization Vectors(IV) for CBC and CTR modes using CRYP_IVInit() function. - Flushes the IN and OUT FIFOs : using CRYP_FIFOFlush() function. - Enable or disable the CRYP Processor using CRYP_Cmd() function @endverbatim * @{ */ /** * @brief Deinitializes the CRYP peripheral registers to their default reset values * @param None * @retval None */ void CRYP_DeInit(void) { /* Enable CRYP reset state */ RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, ENABLE); /* Release CRYP from reset state */ RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, DISABLE); } /** * @brief Initializes the CRYP peripheral according to the specified parameters * in the CRYP_InitStruct. * @param CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure that contains * the configuration information for the CRYP peripheral. * @retval None */ void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct) { /* Check the parameters */ assert_param(IS_CRYP_ALGOMODE(CRYP_InitStruct->CRYP_AlgoMode)); assert_param(IS_CRYP_DATATYPE(CRYP_InitStruct->CRYP_DataType)); assert_param(IS_CRYP_ALGODIR(CRYP_InitStruct->CRYP_AlgoDir)); /* Select Algorithm mode*/ CRYP->CR &= ~CRYP_CR_ALGOMODE; CRYP->CR |= CRYP_InitStruct->CRYP_AlgoMode; /* Select dataType */ CRYP->CR &= ~CRYP_CR_DATATYPE; CRYP->CR |= CRYP_InitStruct->CRYP_DataType; /* select Key size (used only with AES algorithm) */ if ((CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_ECB) || (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_CBC) || (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_CTR) || (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_Key)) { assert_param(IS_CRYP_KEYSIZE(CRYP_InitStruct->CRYP_KeySize)); CRYP->CR &= ~CRYP_CR_KEYSIZE; CRYP->CR |= CRYP_InitStruct->CRYP_KeySize; /* Key size and value must be configured once the key has been prepared */ } /* Select data Direction */ CRYP->CR &= ~CRYP_CR_ALGODIR; CRYP->CR |= CRYP_InitStruct->CRYP_AlgoDir; } /** * @brief Fills each CRYP_InitStruct member with its default value. * @param CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure which will * be initialized. * @retval None */ void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct) { /* Initialize the CRYP_AlgoDir member */ CRYP_InitStruct->CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; /* initialize the CRYP_AlgoMode member */ CRYP_InitStruct->CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB; /* initialize the CRYP_DataType member */ CRYP_InitStruct->CRYP_DataType = CRYP_DataType_32b; /* Initialize the CRYP_KeySize member */ CRYP_InitStruct->CRYP_KeySize = CRYP_KeySize_128b; } /** * @brief Initializes the CRYP Keys according to the specified parameters in * the CRYP_KeyInitStruct. * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that * contains the configuration information for the CRYP Keys. * @retval None */ void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct) { /* Key Initialisation */ CRYP->K0LR = CRYP_KeyInitStruct->CRYP_Key0Left; CRYP->K0RR = CRYP_KeyInitStruct->CRYP_Key0Right; CRYP->K1LR = CRYP_KeyInitStruct->CRYP_Key1Left; CRYP->K1RR = CRYP_KeyInitStruct->CRYP_Key1Right; CRYP->K2LR = CRYP_KeyInitStruct->CRYP_Key2Left; CRYP->K2RR = CRYP_KeyInitStruct->CRYP_Key2Right; CRYP->K3LR = CRYP_KeyInitStruct->CRYP_Key3Left; CRYP->K3RR = CRYP_KeyInitStruct->CRYP_Key3Right; } /** * @brief Fills each CRYP_KeyInitStruct member with its default value. * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure * which will be initialized. * @retval None */ void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct) { CRYP_KeyInitStruct->CRYP_Key0Left = 0; CRYP_KeyInitStruct->CRYP_Key0Right = 0; CRYP_KeyInitStruct->CRYP_Key1Left = 0; CRYP_KeyInitStruct->CRYP_Key1Right = 0; CRYP_KeyInitStruct->CRYP_Key2Left = 0; CRYP_KeyInitStruct->CRYP_Key2Right = 0; CRYP_KeyInitStruct->CRYP_Key3Left = 0; CRYP_KeyInitStruct->CRYP_Key3Right = 0; } /** * @brief Initializes the CRYP Initialization Vectors(IV) according to the * specified parameters in the CRYP_IVInitStruct. * @param CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef structure that contains * the configuration information for the CRYP Initialization Vectors(IV). * @retval None */ void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct) { CRYP->IV0LR = CRYP_IVInitStruct->CRYP_IV0Left; CRYP->IV0RR = CRYP_IVInitStruct->CRYP_IV0Right; CRYP->IV1LR = CRYP_IVInitStruct->CRYP_IV1Left; CRYP->IV1RR = CRYP_IVInitStruct->CRYP_IV1Right; } /** * @brief Fills each CRYP_IVInitStruct member with its default value. * @param CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef Initialization * Vectors(IV) structure which will be initialized. * @retval None */ void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct) { CRYP_IVInitStruct->CRYP_IV0Left = 0; CRYP_IVInitStruct->CRYP_IV0Right = 0; CRYP_IVInitStruct->CRYP_IV1Left = 0; CRYP_IVInitStruct->CRYP_IV1Right = 0; } /** * @brief Flushes the IN and OUT FIFOs (that is read and write pointers of the * FIFOs are reset) * @note The FIFOs must be flushed only when BUSY flag is reset. * @param None * @retval None */ void CRYP_FIFOFlush(void) { /* Reset the read and write pointers of the FIFOs */ CRYP->CR |= CRYP_CR_FFLUSH; } /** * @brief Enables or disables the CRYP peripheral. * @param NewState: new state of the CRYP peripheral. * This parameter can be: ENABLE or DISABLE. * @retval None */ void CRYP_Cmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the Cryptographic processor */ CRYP->CR |= CRYP_CR_CRYPEN; } else { /* Disable the Cryptographic processor */ CRYP->CR &= ~CRYP_CR_CRYPEN; } } /** * @} */ /** @defgroup CRYP_Group2 CRYP Data processing functions * @brief CRYP Data processing functions * @verbatim =============================================================================== CRYP Data processing functions =============================================================================== This section provides functions allowing the encryption and decryption operations: - Enter data to be treated in the IN FIFO : using CRYP_DataIn() function. - Get the data result from the OUT FIFO : using CRYP_DataOut() function. @endverbatim * @{ */ /** * @brief Writes data in the Data Input register (DIN). * @note After the DIN register has been read once or several times, * the FIFO must be flushed (using CRYP_FIFOFlush() function). * @param Data: data to write in Data Input register * @retval None */ void CRYP_DataIn(uint32_t Data) { CRYP->DR = Data; } /** * @brief Returns the last data entered into the output FIFO. * @param None * @retval Last data entered into the output FIFO. */ uint32_t CRYP_DataOut(void) { return CRYP->DOUT; } /** * @} */ /** @defgroup CRYP_Group3 Context swapping functions * @brief Context swapping functions * @verbatim =============================================================================== Context swapping functions =============================================================================== This section provides functions allowing to save and store CRYP Context It is possible to interrupt an encryption/ decryption/ key generation process to perform another processing with a higher priority, and to complete the interrupted process later on, when the higher-priority task is complete. To do so, the context of the interrupted task must be saved from the CRYP registers to memory, and then be restored from memory to the CRYP registers. 1. To save the current context, use CRYP_SaveContext() function 2. To restore the saved context, use CRYP_RestoreContext() function @endverbatim * @{ */ /** * @brief Saves the CRYP peripheral Context. * @note This function stops DMA transfer before to save the context. After * restoring the context, you have to enable the DMA again (if the DMA * was previously used). * @param CRYP_ContextSave: pointer to a CRYP_Context structure that contains * the repository for current context. * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that * contains the configuration information for the CRYP Keys. * @retval None */ ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave, CRYP_KeyInitTypeDef* CRYP_KeyInitStruct) { __IO uint32_t timeout = 0; uint32_t ckeckmask = 0, bitstatus; ErrorStatus status = ERROR; /* Stop DMA transfers on the IN FIFO by clearing the DIEN bit in the CRYP_DMACR */ CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DIEN; /* Wait until both the IN and OUT FIFOs are empty (IFEM=1 and OFNE=0 in the CRYP_SR register) and the BUSY bit is cleared. */ if ((CRYP->CR & (uint32_t)(CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGOMODE_TDES_CBC)) != (uint32_t)0 )/* TDES */ { ckeckmask = CRYP_SR_IFEM | CRYP_SR_BUSY ; } else /* AES or DES */ { ckeckmask = CRYP_SR_IFEM | CRYP_SR_BUSY | CRYP_SR_OFNE; } do { bitstatus = CRYP->SR & ckeckmask; timeout++; } while ((timeout != MAX_TIMEOUT) && (bitstatus != CRYP_SR_IFEM)); if ((CRYP->SR & ckeckmask) != CRYP_SR_IFEM) { status = ERROR; } else { /* Stop DMA transfers on the OUT FIFO by - writing the DOEN bit to 0 in the CRYP_DMACR register - and clear the CRYPEN bit. */ CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DOEN; CRYP->CR &= ~(uint32_t)CRYP_CR_CRYPEN; /* Save the current configuration (bits [9:2] in the CRYP_CR register) */ CRYP_ContextSave->CR_bits9to2 = CRYP->CR & (CRYP_CR_KEYSIZE | CRYP_CR_DATATYPE | CRYP_CR_ALGOMODE | CRYP_CR_ALGODIR); /* and, if not in ECB mode, the initialization vectors. */ CRYP_ContextSave->CRYP_IV0LR = CRYP->IV0LR; CRYP_ContextSave->CRYP_IV0RR = CRYP->IV0RR; CRYP_ContextSave->CRYP_IV1LR = CRYP->IV1LR; CRYP_ContextSave->CRYP_IV1RR = CRYP->IV1RR; /* save The key value */ CRYP_ContextSave->CRYP_K0LR = CRYP_KeyInitStruct->CRYP_Key0Left; CRYP_ContextSave->CRYP_K0RR = CRYP_KeyInitStruct->CRYP_Key0Right; CRYP_ContextSave->CRYP_K1LR = CRYP_KeyInitStruct->CRYP_Key1Left; CRYP_ContextSave->CRYP_K1RR = CRYP_KeyInitStruct->CRYP_Key1Right; CRYP_ContextSave->CRYP_K2LR = CRYP_KeyInitStruct->CRYP_Key2Left; CRYP_ContextSave->CRYP_K2RR = CRYP_KeyInitStruct->CRYP_Key2Right; CRYP_ContextSave->CRYP_K3LR = CRYP_KeyInitStruct->CRYP_Key3Left; CRYP_ContextSave->CRYP_K3RR = CRYP_KeyInitStruct->CRYP_Key3Right; /* When needed, save the DMA status (pointers for IN and OUT messages, number of remaining bytes, etc.) */ status = SUCCESS; } return status; } /** * @brief Restores the CRYP peripheral Context. * @note Since teh DMA transfer is stopped in CRYP_SaveContext() function, * after restoring the context, you have to enable the DMA again (if the * DMA was previously used). * @param CRYP_ContextRestore: pointer to a CRYP_Context structure that contains * the repository for saved context. * @note The data that were saved during context saving must be rewrited into * the IN FIFO. * @retval None */ void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore) { /* Configure the processor with the saved configuration */ CRYP->CR = CRYP_ContextRestore->CR_bits9to2; /* restore The key value */ CRYP->K0LR = CRYP_ContextRestore->CRYP_K0LR; CRYP->K0RR = CRYP_ContextRestore->CRYP_K0RR; CRYP->K1LR = CRYP_ContextRestore->CRYP_K1LR; CRYP->K1RR = CRYP_ContextRestore->CRYP_K1RR; CRYP->K2LR = CRYP_ContextRestore->CRYP_K2LR; CRYP->K2RR = CRYP_ContextRestore->CRYP_K2RR; CRYP->K3LR = CRYP_ContextRestore->CRYP_K3LR; CRYP->K3RR = CRYP_ContextRestore->CRYP_K3RR; /* and the initialization vectors. */ CRYP->IV0LR = CRYP_ContextRestore->CRYP_IV0LR; CRYP->IV0RR = CRYP_ContextRestore->CRYP_IV0RR; CRYP->IV1LR = CRYP_ContextRestore->CRYP_IV1LR; CRYP->IV1RR = CRYP_ContextRestore->CRYP_IV1RR; /* Enable the cryptographic processor */ CRYP->CR |= CRYP_CR_CRYPEN; } /** * @} */ /** @defgroup CRYP_Group4 CRYP's DMA interface Configuration function * @brief CRYP's DMA interface Configuration function * @verbatim =============================================================================== CRYP's DMA interface Configuration function =============================================================================== This section provides functions allowing to configure the DMA interface for CRYP data input and output transfer. When the DMA mode is enabled (using the CRYP_DMACmd() function), data can be transferred: - From memory to the CRYP IN FIFO using the DMA peripheral by enabling the CRYP_DMAReq_DataIN request. - From the CRYP OUT FIFO to the memory using the DMA peripheral by enabling the CRYP_DMAReq_DataOUT request. @endverbatim * @{ */ /** * @brief Enables or disables the CRYP DMA interface. * @param CRYP_DMAReq: specifies the CRYP DMA transfer request to be enabled or disabled. * This parameter can be any combination of the following values: * @arg CRYP_DMAReq_DataOUT: DMA for outgoing(Tx) data transfer * @arg CRYP_DMAReq_DataIN: DMA for incoming(Rx) data transfer * @param NewState: new state of the selected CRYP DMA transfer request. * This parameter can be: ENABLE or DISABLE. * @retval None */ void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_CRYP_DMAREQ(CRYP_DMAReq)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected CRYP DMA request */ CRYP->DMACR |= CRYP_DMAReq; } else { /* Disable the selected CRYP DMA request */ CRYP->DMACR &= (uint8_t)~CRYP_DMAReq; } } /** * @} */ /** @defgroup CRYP_Group5 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== Interrupts and flags management functions =============================================================================== This section provides functions allowing to configure the CRYP Interrupts and to get the status and Interrupts pending bits. The CRYP provides 2 Interrupts sources and 7 Flags: Flags : ------- 1. CRYP_FLAG_IFEM : Set when Input FIFO is empty. This Flag is cleared only by hardware. 2. CRYP_FLAG_IFNF : Set when Input FIFO is not full. This Flag is cleared only by hardware. 3. CRYP_FLAG_INRIS : Set when Input FIFO Raw interrupt is pending it gives the raw interrupt state prior to masking of the input FIFO service interrupt. This Flag is cleared only by hardware. 4. CRYP_FLAG_OFNE : Set when Output FIFO not empty. This Flag is cleared only by hardware. 5. CRYP_FLAG_OFFU : Set when Output FIFO is full. This Flag is cleared only by hardware. 6. CRYP_FLAG_OUTRIS : Set when Output FIFO Raw interrupt is pending it gives the raw interrupt state prior to masking of the output FIFO service interrupt. This Flag is cleared only by hardware. 7. CRYP_FLAG_BUSY : Set when the CRYP core is currently processing a block of data or a key preparation (for AES decryption). This Flag is cleared only by hardware. To clear it, the CRYP core must be disabled and the last processing has completed. Interrupts : ------------ 1. CRYP_IT_INI : The input FIFO service interrupt is asserted when there are less than 4 words in the input FIFO. This interrupt is associated to CRYP_FLAG_INRIS flag. @note This interrupt is cleared by performing write operations to the input FIFO until it holds 4 or more words. The input FIFO service interrupt INMIS is enabled with the CRYP enable bit. Consequently, when CRYP is disabled, the INMIS signal is low even if the input FIFO is empty. 2. CRYP_IT_OUTI : The output FIFO service interrupt is asserted when there is one or more (32-bit word) data items in the output FIFO. This interrupt is associated to CRYP_FLAG_OUTRIS flag. @note This interrupt is cleared by reading data from the output FIFO until there is no valid (32-bit) word left (that is, the interrupt follows the state of the OFNE (output FIFO not empty) flag). Managing the CRYP controller events : ------------------------------------ The user should identify which mode will be used in his application to manage the CRYP controller events: Polling mode or Interrupt mode. 1. In the Polling Mode it is advised to use the following functions: - CRYP_GetFlagStatus() : to check if flags events occur. @note The CRYPT flags do not need to be cleared since they are cleared as soon as the associated event are reset. 2. In the Interrupt Mode it is advised to use the following functions: - CRYP_ITConfig() : to enable or disable the interrupt source. - CRYP_GetITStatus() : to check if Interrupt occurs. @note The CRYPT interrupts have no pending bits, the interrupt is cleared as soon as the associated event is reset. @endverbatim * @{ */ /** * @brief Enables or disables the specified CRYP interrupts. * @param CRYP_IT: specifies the CRYP interrupt source to be enabled or disabled. * This parameter can be any combination of the following values: * @arg CRYP_IT_INI: Input FIFO interrupt * @arg CRYP_IT_OUTI: Output FIFO interrupt * @param NewState: new state of the specified CRYP interrupt. * This parameter can be: ENABLE or DISABLE. * @retval None */ void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_CRYP_CONFIG_IT(CRYP_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected CRYP interrupt */ CRYP->IMSCR |= CRYP_IT; } else { /* Disable the selected CRYP interrupt */ CRYP->IMSCR &= (uint8_t)~CRYP_IT; } } /** * @brief Checks whether the specified CRYP interrupt has occurred or not. * @note This function checks the status of the masked interrupt (i.e the * interrupt should be previously enabled). * @param CRYP_IT: specifies the CRYP (masked) interrupt source to check. * This parameter can be one of the following values: * @arg CRYP_IT_INI: Input FIFO interrupt * @arg CRYP_IT_OUTI: Output FIFO interrupt * @retval The new state of CRYP_IT (SET or RESET). */ ITStatus CRYP_GetITStatus(uint8_t CRYP_IT) { ITStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_CRYP_GET_IT(CRYP_IT)); /* Check the status of the specified CRYP interrupt */ if ((CRYP->MISR & CRYP_IT) != (uint8_t)RESET) { /* CRYP_IT is set */ bitstatus = SET; } else { /* CRYP_IT is reset */ bitstatus = RESET; } /* Return the CRYP_IT status */ return bitstatus; } /** * @brief Checks whether the specified CRYP flag is set or not. * @param CRYP_FLAG: specifies the CRYP flag to check. * This parameter can be one of the following values: * @arg CRYP_FLAG_IFEM: Input FIFO Empty flag. * @arg CRYP_FLAG_IFNF: Input FIFO Not Full flag. * @arg CRYP_FLAG_OFNE: Output FIFO Not Empty flag. * @arg CRYP_FLAG_OFFU: Output FIFO Full flag. * @arg CRYP_FLAG_BUSY: Busy flag. * @arg CRYP_FLAG_OUTRIS: Output FIFO raw interrupt flag. * @arg CRYP_FLAG_INRIS: Input FIFO raw interrupt flag. * @retval The new state of CRYP_FLAG (SET or RESET). */ FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG) { FlagStatus bitstatus = RESET; uint32_t tempreg = 0; /* Check the parameters */ assert_param(IS_CRYP_GET_FLAG(CRYP_FLAG)); /* check if the FLAG is in RISR register */ if ((CRYP_FLAG & FLAG_MASK) != 0x00) { tempreg = CRYP->RISR; } else /* The FLAG is in SR register */ { tempreg = CRYP->SR; } /* Check the status of the specified CRYP flag */ if ((tempreg & CRYP_FLAG ) != (uint8_t)RESET) { /* CRYP_FLAG is set */ bitstatus = SET; } else { /* CRYP_FLAG is reset */ bitstatus = RESET; } /* Return the CRYP_FLAG status */ return bitstatus; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c ================================================ /** ****************************************************************************** * @file stm32f4xx_cryp_aes.c * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file provides high level functions to encrypt and decrypt an * input message using AES in ECB/CBC/CTR modes. * It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP * peripheral. * * @verbatim * * =================================================================== * How to use this driver * =================================================================== * 1. Enable The CRYP controller clock using * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function. * * 2. Encrypt and decrypt using AES in ECB Mode using CRYP_AES_ECB() * function. * * 3. Encrypt and decrypt using AES in CBC Mode using CRYP_AES_CBC() * function. * * 4. Encrypt and decrypt using AES in CTR Mode using CRYP_AES_CTR() * function. * * @endverbatim * ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_cryp.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup CRYP * @brief CRYP driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #define AESBUSY_TIMEOUT ((uint32_t) 0x00010000) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup CRYP_Private_Functions * @{ */ /** @defgroup CRYP_Group6 High Level AES functions * @brief High Level AES functions * @verbatim =============================================================================== High Level AES functions =============================================================================== @endverbatim * @{ */ /** * @brief Encrypt and decrypt using AES in ECB Mode * @param Mode: encryption or decryption Mode. * This parameter can be one of the following values: * @arg MODE_ENCRYPT: Encryption * @arg MODE_DECRYPT: Decryption * @param Key: Key used for AES algorithm. * @param Keysize: length of the Key, must be a 128, 192 or 256. * @param Input: pointer to the Input buffer. * @param Ilength: length of the Input buffer, must be a multiple of 16. * @param Output: pointer to the returned buffer. * @retval An ErrorStatus enumeration value: * - SUCCESS: Operation done * - ERROR: Operation failed */ ErrorStatus CRYP_AES_ECB(uint8_t Mode, uint8_t* Key, uint16_t Keysize, uint8_t* Input, uint32_t Ilength, uint8_t* Output) { CRYP_InitTypeDef AES_CRYP_InitStructure; CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure; __IO uint32_t counter = 0; uint32_t busystatus = 0; ErrorStatus status = SUCCESS; uint32_t keyaddr = (uint32_t)Key; uint32_t inputaddr = (uint32_t)Input; uint32_t outputaddr = (uint32_t)Output; uint32_t i = 0; /* Crypto structures initialisation*/ CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure); switch(Keysize) { case 128: AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b; AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); break; case 192: AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b; AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); break; case 256: AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b; AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); break; default: break; } /*------------------ AES Decryption ------------------*/ if(Mode == MODE_DECRYPT) /* AES decryption */ { /* Flush IN/OUT FIFOs */ CRYP_FIFOFlush(); /* Crypto Init for Key preparation for decryption process */ AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_Key; AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_32b; CRYP_Init(&AES_CRYP_InitStructure); /* Key Initialisation */ CRYP_KeyInit(&AES_CRYP_KeyInitStructure); /* Enable Crypto processor */ CRYP_Cmd(ENABLE); /* wait until the Busy flag is RESET */ do { busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); counter++; }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); if (busystatus != RESET) { status = ERROR; } else { /* Crypto Init for decryption process */ AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; } } /*------------------ AES Encryption ------------------*/ else /* AES encryption */ { CRYP_KeyInit(&AES_CRYP_KeyInitStructure); /* Crypto Init for Encryption process */ AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; } AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_ECB; AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; CRYP_Init(&AES_CRYP_InitStructure); /* Flush IN/OUT FIFOs */ CRYP_FIFOFlush(); /* Enable Crypto processor */ CRYP_Cmd(ENABLE); for(i=0; ((i
© COPYRIGHT 2012 STMicroelectronics
* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_cryp.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup CRYP * @brief CRYP driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #define DESBUSY_TIMEOUT ((uint32_t) 0x00010000) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup CRYP_Private_Functions * @{ */ /** @defgroup CRYP_Group8 High Level DES functions * @brief High Level DES functions * @verbatim =============================================================================== High Level DES functions =============================================================================== @endverbatim * @{ */ /** * @brief Encrypt and decrypt using DES in ECB Mode * @param Mode: encryption or decryption Mode. * This parameter can be one of the following values: * @arg MODE_ENCRYPT: Encryption * @arg MODE_DECRYPT: Decryption * @param Key: Key used for DES algorithm. * @param Ilength: length of the Input buffer, must be a multiple of 8. * @param Input: pointer to the Input buffer. * @param Output: pointer to the returned buffer. * @retval An ErrorStatus enumeration value: * - SUCCESS: Operation done * - ERROR: Operation failed */ ErrorStatus CRYP_DES_ECB(uint8_t Mode, uint8_t Key[8], uint8_t *Input, uint32_t Ilength, uint8_t *Output) { CRYP_InitTypeDef DES_CRYP_InitStructure; CRYP_KeyInitTypeDef DES_CRYP_KeyInitStructure; __IO uint32_t counter = 0; uint32_t busystatus = 0; ErrorStatus status = SUCCESS; uint32_t keyaddr = (uint32_t)Key; uint32_t inputaddr = (uint32_t)Input; uint32_t outputaddr = (uint32_t)Output; uint32_t i = 0; /* Crypto structures initialisation*/ CRYP_KeyStructInit(&DES_CRYP_KeyInitStructure); /* Crypto Init for Encryption process */ if( Mode == MODE_ENCRYPT ) /* DES encryption */ { DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; } else/* if( Mode == MODE_DECRYPT )*/ /* DES decryption */ { DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; } DES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_DES_ECB; DES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; CRYP_Init(&DES_CRYP_InitStructure); /* Key Initialisation */ DES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; DES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); CRYP_KeyInit(& DES_CRYP_KeyInitStructure); /* Flush IN/OUT FIFO */ CRYP_FIFOFlush(); /* Enable Crypto processor */ CRYP_Cmd(ENABLE); for(i=0; ((i
© COPYRIGHT 2012 STMicroelectronics
* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_cryp.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup CRYP * @brief CRYP driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #define TDESBUSY_TIMEOUT ((uint32_t) 0x00010000) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup CRYP_Private_Functions * @{ */ /** @defgroup CRYP_Group7 High Level TDES functions * @brief High Level TDES functions * @verbatim =============================================================================== High Level TDES functions =============================================================================== @endverbatim * @{ */ /** * @brief Encrypt and decrypt using TDES in ECB Mode * @param Mode: encryption or decryption Mode. * This parameter can be one of the following values: * @arg MODE_ENCRYPT: Encryption * @arg MODE_DECRYPT: Decryption * @param Key: Key used for TDES algorithm. * @param Ilength: length of the Input buffer, must be a multiple of 8. * @param Input: pointer to the Input buffer. * @param Output: pointer to the returned buffer. * @retval An ErrorStatus enumeration value: * - SUCCESS: Operation done * - ERROR: Operation failed */ ErrorStatus CRYP_TDES_ECB(uint8_t Mode, uint8_t Key[24], uint8_t *Input, uint32_t Ilength, uint8_t *Output) { CRYP_InitTypeDef TDES_CRYP_InitStructure; CRYP_KeyInitTypeDef TDES_CRYP_KeyInitStructure; __IO uint32_t counter = 0; uint32_t busystatus = 0; ErrorStatus status = SUCCESS; uint32_t keyaddr = (uint32_t)Key; uint32_t inputaddr = (uint32_t)Input; uint32_t outputaddr = (uint32_t)Output; uint32_t i = 0; /* Crypto structures initialisation*/ CRYP_KeyStructInit(&TDES_CRYP_KeyInitStructure); /* Crypto Init for Encryption process */ if(Mode == MODE_ENCRYPT) /* TDES encryption */ { TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; } else /*if(Mode == MODE_DECRYPT)*/ /* TDES decryption */ { TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; } TDES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB; TDES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; CRYP_Init(&TDES_CRYP_InitStructure); /* Key Initialisation */ TDES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; TDES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; TDES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; TDES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; TDES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; TDES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); CRYP_KeyInit(& TDES_CRYP_KeyInitStructure); /* Flush IN/OUT FIFO */ CRYP_FIFOFlush(); /* Enable Crypto processor */ CRYP_Cmd(ENABLE); for(i=0; ((i
© COPYRIGHT 2012 STMicroelectronics
* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_dac.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup DAC * @brief DAC driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* CR register Mask */ #define CR_CLEAR_MASK ((uint32_t)0x00000FFE) /* DAC Dual Channels SWTRIG masks */ #define DUAL_SWTRIG_SET ((uint32_t)0x00000003) #define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC) /* DHR registers offsets */ #define DHR12R1_OFFSET ((uint32_t)0x00000008) #define DHR12R2_OFFSET ((uint32_t)0x00000014) #define DHR12RD_OFFSET ((uint32_t)0x00000020) /* DOR register offset */ #define DOR_OFFSET ((uint32_t)0x0000002C) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup DAC_Private_Functions * @{ */ /** @defgroup DAC_Group1 DAC channels configuration * @brief DAC channels configuration: trigger, output buffer, data format * @verbatim =============================================================================== DAC channels configuration: trigger, output buffer, data format =============================================================================== @endverbatim * @{ */ /** * @brief Deinitializes the DAC peripheral registers to their default reset values. * @param None * @retval None */ void DAC_DeInit(void) { /* Enable DAC reset state */ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); /* Release DAC from reset state */ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); } /** * @brief Initializes the DAC peripheral according to the specified parameters * in the DAC_InitStruct. * @param DAC_Channel: the selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains * the configuration information for the specified DAC channel. * @retval None */ void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) { uint32_t tmpreg1 = 0, tmpreg2 = 0; /* Check the DAC parameters */ assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); /*---------------------------- DAC CR Configuration --------------------------*/ /* Get the DAC CR value */ tmpreg1 = DAC->CR; /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel); /* Configure for the selected DAC channel: buffer output, trigger, wave generation, mask/amplitude for wave generation */ /* Set TSELx and TENx bits according to DAC_Trigger value */ /* Set WAVEx bits according to DAC_WaveGeneration value */ /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ /* Set BOFFx bit according to DAC_OutputBuffer value */ tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | \ DAC_InitStruct->DAC_OutputBuffer); /* Calculate CR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << DAC_Channel; /* Write to DAC CR */ DAC->CR = tmpreg1; } /** * @brief Fills each DAC_InitStruct member with its default value. * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will * be initialized. * @retval None */ void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) { /*--------------- Reset DAC init structure parameters values -----------------*/ /* Initialize the DAC_Trigger member */ DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; /* Initialize the DAC_WaveGeneration member */ DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; /* Initialize the DAC_OutputBuffer member */ DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; } /** * @brief Enables or disables the specified DAC channel. * @param DAC_Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @param NewState: new state of the DAC channel. * This parameter can be: ENABLE or DISABLE. * @note When the DAC channel is enabled the trigger source can no more be modified. * @retval None */ void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected DAC channel */ DAC->CR |= (DAC_CR_EN1 << DAC_Channel); } else { /* Disable the selected DAC channel */ DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel)); } } /** * @brief Enables or disables the selected DAC channel software trigger. * @param DAC_Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @param NewState: new state of the selected DAC channel software trigger. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable software trigger for the selected DAC channel */ DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4); } else { /* Disable software trigger for the selected DAC channel */ DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4)); } } /** * @brief Enables or disables simultaneously the two DAC channels software triggers. * @param NewState: new state of the DAC channels software triggers. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable software trigger for both DAC channels */ DAC->SWTRIGR |= DUAL_SWTRIG_SET; } else { /* Disable software trigger for both DAC channels */ DAC->SWTRIGR &= DUAL_SWTRIG_RESET; } } /** * @brief Enables or disables the selected DAC channel wave generation. * @param DAC_Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @param DAC_Wave: specifies the wave type to enable or disable. * This parameter can be one of the following values: * @arg DAC_Wave_Noise: noise wave generation * @arg DAC_Wave_Triangle: triangle wave generation * @param NewState: new state of the selected DAC channel wave generation. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_DAC_WAVE(DAC_Wave)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected wave generation for the selected DAC channel */ DAC->CR |= DAC_Wave << DAC_Channel; } else { /* Disable the selected wave generation for the selected DAC channel */ DAC->CR &= ~(DAC_Wave << DAC_Channel); } } /** * @brief Set the specified data holding register value for DAC channel1. * @param DAC_Align: Specifies the data alignment for DAC channel1. * This parameter can be one of the following values: * @arg DAC_Align_8b_R: 8bit right data alignment selected * @arg DAC_Align_12b_L: 12bit left data alignment selected * @arg DAC_Align_12b_R: 12bit right data alignment selected * @param Data: Data to be loaded in the selected data holding register. * @retval None */ void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) { __IO uint32_t tmp = 0; /* Check the parameters */ assert_param(IS_DAC_ALIGN(DAC_Align)); assert_param(IS_DAC_DATA(Data)); tmp = (uint32_t)DAC_BASE; tmp += DHR12R1_OFFSET + DAC_Align; /* Set the DAC channel1 selected data holding register */ *(__IO uint32_t *) tmp = Data; } /** * @brief Set the specified data holding register value for DAC channel2. * @param DAC_Align: Specifies the data alignment for DAC channel2. * This parameter can be one of the following values: * @arg DAC_Align_8b_R: 8bit right data alignment selected * @arg DAC_Align_12b_L: 12bit left data alignment selected * @arg DAC_Align_12b_R: 12bit right data alignment selected * @param Data: Data to be loaded in the selected data holding register. * @retval None */ void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) { __IO uint32_t tmp = 0; /* Check the parameters */ assert_param(IS_DAC_ALIGN(DAC_Align)); assert_param(IS_DAC_DATA(Data)); tmp = (uint32_t)DAC_BASE; tmp += DHR12R2_OFFSET + DAC_Align; /* Set the DAC channel2 selected data holding register */ *(__IO uint32_t *)tmp = Data; } /** * @brief Set the specified data holding register value for dual channel DAC. * @param DAC_Align: Specifies the data alignment for dual channel DAC. * This parameter can be one of the following values: * @arg DAC_Align_8b_R: 8bit right data alignment selected * @arg DAC_Align_12b_L: 12bit left data alignment selected * @arg DAC_Align_12b_R: 12bit right data alignment selected * @param Data2: Data for DAC Channel2 to be loaded in the selected data holding register. * @param Data1: Data for DAC Channel1 to be loaded in the selected data holding register. * @note In dual mode, a unique register access is required to write in both * DAC channels at the same time. * @retval None */ void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) { uint32_t data = 0, tmp = 0; /* Check the parameters */ assert_param(IS_DAC_ALIGN(DAC_Align)); assert_param(IS_DAC_DATA(Data1)); assert_param(IS_DAC_DATA(Data2)); /* Calculate and set dual DAC data holding register value */ if (DAC_Align == DAC_Align_8b_R) { data = ((uint32_t)Data2 << 8) | Data1; } else { data = ((uint32_t)Data2 << 16) | Data1; } tmp = (uint32_t)DAC_BASE; tmp += DHR12RD_OFFSET + DAC_Align; /* Set the dual DAC selected data holding register */ *(__IO uint32_t *)tmp = data; } /** * @brief Returns the last data output value of the selected DAC channel. * @param DAC_Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @retval The selected DAC channel data output value. */ uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) { __IO uint32_t tmp = 0; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); tmp = (uint32_t) DAC_BASE ; tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); /* Returns the DAC channel data output register value */ return (uint16_t) (*(__IO uint32_t*) tmp); } /** * @} */ /** @defgroup DAC_Group2 DMA management functions * @brief DMA management functions * @verbatim =============================================================================== DMA management functions =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables the specified DAC channel DMA request. * @note When enabled DMA1 is generated when an external trigger (EXTI Line9, * TIM2, TIM4, TIM5, TIM6, TIM7 or TIM8 but not a software trigger) occurs. * @param DAC_Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @param NewState: new state of the selected DAC channel DMA request. * This parameter can be: ENABLE or DISABLE. * @note The DAC channel1 is mapped on DMA1 Stream 5 channel7 which must be * already configured. * @note The DAC channel2 is mapped on DMA1 Stream 6 channel7 which must be * already configured. * @retval None */ void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected DAC channel DMA request */ DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel); } else { /* Disable the selected DAC channel DMA request */ DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel)); } } /** * @} */ /** @defgroup DAC_Group3 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== Interrupts and flags management functions =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables the specified DAC interrupts. * @param DAC_Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. * This parameter can be the following values: * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask * @note The DMA underrun occurs when a second external trigger arrives before the * acknowledgement for the first external trigger is received (first request). * @param NewState: new state of the specified DAC interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_FUNCTIONAL_STATE(NewState)); assert_param(IS_DAC_IT(DAC_IT)); if (NewState != DISABLE) { /* Enable the selected DAC interrupts */ DAC->CR |= (DAC_IT << DAC_Channel); } else { /* Disable the selected DAC interrupts */ DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel)); } } /** * @brief Checks whether the specified DAC flag is set or not. * @param DAC_Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @param DAC_FLAG: specifies the flag to check. * This parameter can be only of the following value: * @arg DAC_FLAG_DMAUDR: DMA underrun flag * @note The DMA underrun occurs when a second external trigger arrives before the * acknowledgement for the first external trigger is received (first request). * @retval The new state of DAC_FLAG (SET or RESET). */ FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_DAC_FLAG(DAC_FLAG)); /* Check the status of the specified DAC flag */ if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET) { /* DAC_FLAG is set */ bitstatus = SET; } else { /* DAC_FLAG is reset */ bitstatus = RESET; } /* Return the DAC_FLAG status */ return bitstatus; } /** * @brief Clears the DAC channel's pending flags. * @param DAC_Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @param DAC_FLAG: specifies the flag to clear. * This parameter can be of the following value: * @arg DAC_FLAG_DMAUDR: DMA underrun flag * @note The DMA underrun occurs when a second external trigger arrives before the * acknowledgement for the first external trigger is received (first request). * @retval None */ void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_DAC_FLAG(DAC_FLAG)); /* Clear the selected DAC flags */ DAC->SR = (DAC_FLAG << DAC_Channel); } /** * @brief Checks whether the specified DAC interrupt has occurred or not. * @param DAC_Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @param DAC_IT: specifies the DAC interrupt source to check. * This parameter can be the following values: * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask * @note The DMA underrun occurs when a second external trigger arrives before the * acknowledgement for the first external trigger is received (first request). * @retval The new state of DAC_IT (SET or RESET). */ ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT) { ITStatus bitstatus = RESET; uint32_t enablestatus = 0; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_DAC_IT(DAC_IT)); /* Get the DAC_IT enable bit status */ enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ; /* Check the status of the specified DAC interrupt */ if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus) { /* DAC_IT is set */ bitstatus = SET; } else { /* DAC_IT is reset */ bitstatus = RESET; } /* Return the DAC_IT status */ return bitstatus; } /** * @brief Clears the DAC channel's interrupt pending bits. * @param DAC_Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @param DAC_IT: specifies the DAC interrupt pending bit to clear. * This parameter can be the following values: * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask * @note The DMA underrun occurs when a second external trigger arrives before the * acknowledgement for the first external trigger is received (first request). * @retval None */ void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_DAC_IT(DAC_IT)); /* Clear the selected DAC interrupt pending bits */ DAC->SR = (DAC_IT << DAC_Channel); } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dbgmcu.c ================================================ /** ****************************************************************************** * @file stm32f4xx_dbgmcu.c * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file provides all the DBGMCU firmware functions. ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_dbgmcu.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup DBGMCU * @brief DBGMCU driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup DBGMCU_Private_Functions * @{ */ /** * @brief Returns the device revision identifier. * @param None * @retval Device revision identifier */ uint32_t DBGMCU_GetREVID(void) { return(DBGMCU->IDCODE >> 16); } /** * @brief Returns the device identifier. * @param None * @retval Device identifier */ uint32_t DBGMCU_GetDEVID(void) { return(DBGMCU->IDCODE & IDCODE_DEVID_MASK); } /** * @brief Configures low power mode behavior when the MCU is in Debug mode. * @param DBGMCU_Periph: specifies the low power mode. * This parameter can be any combination of the following values: * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode * @arg DBGMCU_STOP: Keep debugger connection during STOP mode * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode * @param NewState: new state of the specified low power mode in Debug mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { DBGMCU->CR |= DBGMCU_Periph; } else { DBGMCU->CR &= ~DBGMCU_Periph; } } /** * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode. * @param DBGMCU_Periph: specifies the APB1 peripheral. * This parameter can be any combination of the following values: * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted * @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped when Core is halted. * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted * @arg DBGMCU_I2C3_SMBUS_TIMEOUT: I2C3 SMBUS timeout mode stopped when Core is halted * @arg DBGMCU_CAN2_STOP: Debug CAN1 stopped when Core is halted * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted * This parameter can be: ENABLE or DISABLE. * @retval None */ void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { DBGMCU->APB1FZ |= DBGMCU_Periph; } else { DBGMCU->APB1FZ &= ~DBGMCU_Periph; } } /** * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode. * @param DBGMCU_Periph: specifies the APB2 peripheral. * This parameter can be any combination of the following values: * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted * @param NewState: new state of the specified peripheral in Debug mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { DBGMCU->APB2FZ |= DBGMCU_Periph; } else { DBGMCU->APB2FZ &= ~DBGMCU_Periph; } } /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c ================================================ /** ****************************************************************************** * @file stm32f4xx_dcmi.c * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file provides firmware functions to manage the following * functionalities of the DCMI peripheral: * - Initialization and Configuration * - Image capture functions * - Interrupts and flags management * * @verbatim * * * =================================================================== * How to use this driver * =================================================================== * * The sequence below describes how to use this driver to capture image * from a camera module connected to the DCMI Interface. * This sequence does not take into account the configuration of the * camera module, which should be made before to configure and enable * the DCMI to capture images. * * 1. Enable the clock for the DCMI and associated GPIOs using the following functions: * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_DCMI, ENABLE); * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); * * 2. DCMI pins configuration * - Connect the involved DCMI pins to AF13 using the following function * GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_DCMI); * - Configure these DCMI pins in alternate function mode by calling the function * GPIO_Init(); * * 3. Declare a DCMI_InitTypeDef structure, for example: * DCMI_InitTypeDef DCMI_InitStructure; * and fill the DCMI_InitStructure variable with the allowed values * of the structure member. * * 4. Initialize the DCMI interface by calling the function * DCMI_Init(&DCMI_InitStructure); * * 5. Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR * register to the destination memory buffer. * * 6. Enable DCMI interface using the function * DCMI_Cmd(ENABLE); * * 7. Start the image capture using the function * DCMI_CaptureCmd(ENABLE); * * 8. At this stage the DCMI interface waits for the first start of frame, * then a DMA request is generated continuously/once (depending on the * mode used, Continuous/Snapshot) to transfer the received data into * the destination memory. * * @note If you need to capture only a rectangular window from the received * image, you have to use the DCMI_CROPConfig() function to configure * the coordinates and size of the window to be captured, then enable * the Crop feature using DCMI_CROPCmd(ENABLE); * In this case, the Crop configuration should be made before to enable * and start the DCMI interface. * * @endverbatim * ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_dcmi.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup DCMI * @brief DCMI driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup DCMI_Private_Functions * @{ */ /** @defgroup DCMI_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== Initialization and Configuration functions =============================================================================== @endverbatim * @{ */ /** * @brief Deinitializes the DCMI registers to their default reset values. * @param None * @retval None */ void DCMI_DeInit(void) { DCMI->CR = 0x0; DCMI->IER = 0x0; DCMI->ICR = 0x1F; DCMI->ESCR = 0x0; DCMI->ESUR = 0x0; DCMI->CWSTRTR = 0x0; DCMI->CWSIZER = 0x0; } /** * @brief Initializes the DCMI according to the specified parameters in the DCMI_InitStruct. * @param DCMI_InitStruct: pointer to a DCMI_InitTypeDef structure that contains * the configuration information for the DCMI. * @retval None */ void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct) { uint32_t temp = 0x0; /* Check the parameters */ assert_param(IS_DCMI_CAPTURE_MODE(DCMI_InitStruct->DCMI_CaptureMode)); assert_param(IS_DCMI_SYNCHRO(DCMI_InitStruct->DCMI_SynchroMode)); assert_param(IS_DCMI_PCKPOLARITY(DCMI_InitStruct->DCMI_PCKPolarity)); assert_param(IS_DCMI_VSPOLARITY(DCMI_InitStruct->DCMI_VSPolarity)); assert_param(IS_DCMI_HSPOLARITY(DCMI_InitStruct->DCMI_HSPolarity)); assert_param(IS_DCMI_CAPTURE_RATE(DCMI_InitStruct->DCMI_CaptureRate)); assert_param(IS_DCMI_EXTENDED_DATA(DCMI_InitStruct->DCMI_ExtendedDataMode)); /* The DCMI configuration registers should be programmed correctly before enabling the CR_ENABLE Bit and the CR_CAPTURE Bit */ DCMI->CR &= ~(DCMI_CR_ENABLE | DCMI_CR_CAPTURE); /* Reset the old DCMI configuration */ temp = DCMI->CR; temp &= ~((uint32_t)DCMI_CR_CM | DCMI_CR_ESS | DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_EDM_0 | DCMI_CR_EDM_1); /* Sets the new configuration of the DCMI peripheral */ temp |= ((uint32_t)DCMI_InitStruct->DCMI_CaptureMode | DCMI_InitStruct->DCMI_SynchroMode | DCMI_InitStruct->DCMI_PCKPolarity | DCMI_InitStruct->DCMI_VSPolarity | DCMI_InitStruct->DCMI_HSPolarity | DCMI_InitStruct->DCMI_CaptureRate | DCMI_InitStruct->DCMI_ExtendedDataMode); DCMI->CR = temp; } /** * @brief Fills each DCMI_InitStruct member with its default value. * @param DCMI_InitStruct : pointer to a DCMI_InitTypeDef structure which will * be initialized. * @retval None */ void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct) { /* Set the default configuration */ DCMI_InitStruct->DCMI_CaptureMode = DCMI_CaptureMode_Continuous; DCMI_InitStruct->DCMI_SynchroMode = DCMI_SynchroMode_Hardware; DCMI_InitStruct->DCMI_PCKPolarity = DCMI_PCKPolarity_Falling; DCMI_InitStruct->DCMI_VSPolarity = DCMI_VSPolarity_Low; DCMI_InitStruct->DCMI_HSPolarity = DCMI_HSPolarity_Low; DCMI_InitStruct->DCMI_CaptureRate = DCMI_CaptureRate_All_Frame; DCMI_InitStruct->DCMI_ExtendedDataMode = DCMI_ExtendedDataMode_8b; } /** * @brief Initializes the DCMI peripheral CROP mode according to the specified * parameters in the DCMI_CROPInitStruct. * @note This function should be called before to enable and start the DCMI interface. * @param DCMI_CROPInitStruct: pointer to a DCMI_CROPInitTypeDef structure that * contains the configuration information for the DCMI peripheral CROP mode. * @retval None */ void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct) { /* Sets the CROP window coordinates */ DCMI->CWSTRTR = (uint32_t)((uint32_t)DCMI_CROPInitStruct->DCMI_HorizontalOffsetCount | ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalStartLine << 16)); /* Sets the CROP window size */ DCMI->CWSIZER = (uint32_t)(DCMI_CROPInitStruct->DCMI_CaptureCount | ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalLineCount << 16)); } /** * @brief Enables or disables the DCMI Crop feature. * @note This function should be called before to enable and start the DCMI interface. * @param NewState: new state of the DCMI Crop feature. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DCMI_CROPCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the DCMI Crop feature */ DCMI->CR |= (uint32_t)DCMI_CR_CROP; } else { /* Disable the DCMI Crop feature */ DCMI->CR &= ~(uint32_t)DCMI_CR_CROP; } } /** * @brief Sets the embedded synchronization codes * @param DCMI_CodesInitTypeDef: pointer to a DCMI_CodesInitTypeDef structure that * contains the embedded synchronization codes for the DCMI peripheral. * @retval None */ void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct) { DCMI->ESCR = (uint32_t)(DCMI_CodesInitStruct->DCMI_FrameStartCode | ((uint32_t)DCMI_CodesInitStruct->DCMI_LineStartCode << 8)| ((uint32_t)DCMI_CodesInitStruct->DCMI_LineEndCode << 16)| ((uint32_t)DCMI_CodesInitStruct->DCMI_FrameEndCode << 24)); } /** * @brief Enables or disables the DCMI JPEG format. * @note The Crop and Embedded Synchronization features cannot be used in this mode. * @param NewState: new state of the DCMI JPEG format. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DCMI_JPEGCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the DCMI JPEG format */ DCMI->CR |= (uint32_t)DCMI_CR_JPEG; } else { /* Disable the DCMI JPEG format */ DCMI->CR &= ~(uint32_t)DCMI_CR_JPEG; } } /** * @} */ /** @defgroup DCMI_Group2 Image capture functions * @brief Image capture functions * @verbatim =============================================================================== Image capture functions =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables the DCMI interface. * @param NewState: new state of the DCMI interface. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DCMI_Cmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the DCMI by setting ENABLE bit */ DCMI->CR |= (uint32_t)DCMI_CR_ENABLE; } else { /* Disable the DCMI by clearing ENABLE bit */ DCMI->CR &= ~(uint32_t)DCMI_CR_ENABLE; } } /** * @brief Enables or disables the DCMI Capture. * @param NewState: new state of the DCMI capture. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DCMI_CaptureCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the DCMI Capture */ DCMI->CR |= (uint32_t)DCMI_CR_CAPTURE; } else { /* Disable the DCMI Capture */ DCMI->CR &= ~(uint32_t)DCMI_CR_CAPTURE; } } /** * @brief Reads the data stored in the DR register. * @param None * @retval Data register value */ uint32_t DCMI_ReadData(void) { return DCMI->DR; } /** * @} */ /** @defgroup DCMI_Group3 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== Interrupts and flags management functions =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables the DCMI interface interrupts. * @param DCMI_IT: specifies the DCMI interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask * @arg DCMI_IT_OVF: Overflow interrupt mask * @arg DCMI_IT_ERR: Synchronization error interrupt mask * @arg DCMI_IT_VSYNC: VSYNC interrupt mask * @arg DCMI_IT_LINE: Line interrupt mask * @param NewState: new state of the specified DCMI interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DCMI_CONFIG_IT(DCMI_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the Interrupt sources */ DCMI->IER |= DCMI_IT; } else { /* Disable the Interrupt sources */ DCMI->IER &= (uint16_t)(~DCMI_IT); } } /** * @brief Checks whether the DCMI interface flag is set or not. * @param DCMI_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask * @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask * @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask * @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask * @arg DCMI_FLAG_LINERI: Line Raw flag mask * @arg DCMI_FLAG_FRAMEMI: Frame capture complete Masked flag mask * @arg DCMI_FLAG_OVFMI: Overflow Masked flag mask * @arg DCMI_FLAG_ERRMI: Synchronization error Masked flag mask * @arg DCMI_FLAG_VSYNCMI: VSYNC Masked flag mask * @arg DCMI_FLAG_LINEMI: Line Masked flag mask * @arg DCMI_FLAG_HSYNC: HSYNC flag mask * @arg DCMI_FLAG_VSYNC: VSYNC flag mask * @arg DCMI_FLAG_FNE: Fifo not empty flag mask * @retval The new state of DCMI_FLAG (SET or RESET). */ FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG) { FlagStatus bitstatus = RESET; uint32_t dcmireg, tempreg = 0; /* Check the parameters */ assert_param(IS_DCMI_GET_FLAG(DCMI_FLAG)); /* Get the DCMI register index */ dcmireg = (((uint16_t)DCMI_FLAG) >> 12); if (dcmireg == 0x00) /* The FLAG is in RISR register */ { tempreg= DCMI->RISR; } else if (dcmireg == 0x02) /* The FLAG is in SR register */ { tempreg = DCMI->SR; } else /* The FLAG is in MISR register */ { tempreg = DCMI->MISR; } if ((tempreg & DCMI_FLAG) != (uint16_t)RESET ) { bitstatus = SET; } else { bitstatus = RESET; } /* Return the DCMI_FLAG status */ return bitstatus; } /** * @brief Clears the DCMI's pending flags. * @param DCMI_FLAG: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask * @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask * @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask * @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask * @arg DCMI_FLAG_LINERI: Line Raw flag mask * @retval None */ void DCMI_ClearFlag(uint16_t DCMI_FLAG) { /* Check the parameters */ assert_param(IS_DCMI_CLEAR_FLAG(DCMI_FLAG)); /* Clear the flag by writing in the ICR register 1 in the corresponding Flag position*/ DCMI->ICR = DCMI_FLAG; } /** * @brief Checks whether the DCMI interrupt has occurred or not. * @param DCMI_IT: specifies the DCMI interrupt source to check. * This parameter can be one of the following values: * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask * @arg DCMI_IT_OVF: Overflow interrupt mask * @arg DCMI_IT_ERR: Synchronization error interrupt mask * @arg DCMI_IT_VSYNC: VSYNC interrupt mask * @arg DCMI_IT_LINE: Line interrupt mask * @retval The new state of DCMI_IT (SET or RESET). */ ITStatus DCMI_GetITStatus(uint16_t DCMI_IT) { ITStatus bitstatus = RESET; uint32_t itstatus = 0; /* Check the parameters */ assert_param(IS_DCMI_GET_IT(DCMI_IT)); itstatus = DCMI->MISR & DCMI_IT; /* Only masked interrupts are checked */ if ((itstatus != (uint16_t)RESET)) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears the DCMI's interrupt pending bits. * @param DCMI_IT: specifies the DCMI interrupt pending bit to clear. * This parameter can be any combination of the following values: * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask * @arg DCMI_IT_OVF: Overflow interrupt mask * @arg DCMI_IT_ERR: Synchronization error interrupt mask * @arg DCMI_IT_VSYNC: VSYNC interrupt mask * @arg DCMI_IT_LINE: Line interrupt mask * @retval None */ void DCMI_ClearITPendingBit(uint16_t DCMI_IT) { /* Clear the interrupt pending Bit by writing in the ICR register 1 in the corresponding pending Bit position*/ DCMI->ICR = DCMI_IT; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c ================================================ /** ****************************************************************************** * @file stm32f4xx_dma.c * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file provides firmware functions to manage the following * functionalities of the Direct Memory Access controller (DMA): * - Initialization and Configuration * - Data Counter * - Double Buffer mode configuration and command * - Interrupts and flags management * * @verbatim * * =================================================================== * How to use this driver * =================================================================== * 1. Enable The DMA controller clock using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA1, ENABLE) * function for DMA1 or using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2, ENABLE) * function for DMA2. * * 2. Enable and configure the peripheral to be connected to the DMA Stream * (except for internal SRAM / FLASH memories: no initialization is * necessary). * * 3. For a given Stream, program the required configuration through following parameters: * Source and Destination addresses, Transfer Direction, Transfer size, Source and Destination * data formats, Circular or Normal mode, Stream Priority level, Source and Destination * Incrementation mode, FIFO mode and its Threshold (if needed), Burst mode for Source and/or * Destination (if needed) using the DMA_Init() function. * To avoid filling un-nesecessary fields, you can call DMA_StructInit() function * to initialize a given structure with default values (reset values), the modify * only necessary fields (ie. Source and Destination addresses, Transfer size and Data Formats). * * 4. Enable the NVIC and the corresponding interrupt(s) using the function * DMA_ITConfig() if you need to use DMA interrupts. * * 5. Optionally, if the Circular mode is enabled, you can use the Double buffer mode by configuring * the second Memory address and the first Memory to be used through the function * DMA_DoubleBufferModeConfig(). Then enable the Double buffer mode through the function * DMA_DoubleBufferModeCmd(). These operations must be done before step 6. * * 6. Enable the DMA stream using the DMA_Cmd() function. * * 7. Activate the needed Stream Request using PPP_DMACmd() function for * any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...) * The function allowing this operation is provided in each PPP peripheral * driver (ie. SPI_DMACmd for SPI peripheral). * Once the Stream is enabled, it is not possible to modify its configuration * unless the stream is stopped and disabled. * After enabling the Stream, it is advised to monitor the EN bit status using * the function DMA_GetCmdStatus(). In case of configuration errors or bus errors * this bit will remain reset and all transfers on this Stream will remain on hold. * * 8. Optionally, you can configure the number of data to be transferred * when the Stream is disabled (ie. after each Transfer Complete event * or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter(). * And you can get the number of remaining data to be transferred using * the function DMA_GetCurrDataCounter() at run time (when the DMA Stream is * enabled and running). * * 9. To control DMA events you can use one of the following * two methods: * a- Check on DMA Stream flags using the function DMA_GetFlagStatus(). * b- Use DMA interrupts through the function DMA_ITConfig() at initialization * phase and DMA_GetITStatus() function into interrupt routines in * communication phase. * After checking on a flag you should clear it using DMA_ClearFlag() * function. And after checking on an interrupt event you should * clear it using DMA_ClearITPendingBit() function. * * 10. Optionally, if Circular mode and Double Buffer mode are enabled, you can modify * the Memory Addresses using the function DMA_MemoryTargetConfig(). Make sure that * the Memory Address to be modified is not the one currently in use by DMA Stream. * This condition can be monitored using the function DMA_GetCurrentMemoryTarget(). * * 11. Optionally, Pause-Resume operations may be performed: * The DMA_Cmd() function may be used to perform Pause-Resume operation. When a * transfer is ongoing, calling this function to disable the Stream will cause the * transfer to be paused. All configuration registers and the number of remaining * data will be preserved. When calling again this function to re-enable the Stream, * the transfer will be resumed from the point where it was paused. * * @note Memory-to-Memory transfer is possible by setting the address of the memory into * the Peripheral registers. In this mode, Circular mode and Double Buffer mode * are not allowed. * * @note The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is * possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set * Half-Word data size for the peripheral to access its data register and set Word data size * for the Memory to gain in access time. Each two Half-words will be packed and written in * a single access to a Word in the Memory). * * @note When FIFO is disabled, it is not allowed to configure different Data Sizes for Source * and Destination. In this case the Peripheral Data Size will be applied to both Source * and Destination. * * @endverbatim * ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_dma.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup DMA * @brief DMA driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Masks Definition */ #define TRANSFER_IT_ENABLE_MASK (uint32_t)(DMA_SxCR_TCIE | DMA_SxCR_HTIE | \ DMA_SxCR_TEIE | DMA_SxCR_DMEIE) #define DMA_Stream0_IT_MASK (uint32_t)(DMA_LISR_FEIF0 | DMA_LISR_DMEIF0 | \ DMA_LISR_TEIF0 | DMA_LISR_HTIF0 | \ DMA_LISR_TCIF0) #define DMA_Stream1_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 6) #define DMA_Stream2_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 16) #define DMA_Stream3_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 22) #define DMA_Stream4_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK | (uint32_t)0x20000000) #define DMA_Stream5_IT_MASK (uint32_t)(DMA_Stream1_IT_MASK | (uint32_t)0x20000000) #define DMA_Stream6_IT_MASK (uint32_t)(DMA_Stream2_IT_MASK | (uint32_t)0x20000000) #define DMA_Stream7_IT_MASK (uint32_t)(DMA_Stream3_IT_MASK | (uint32_t)0x20000000) #define TRANSFER_IT_MASK (uint32_t)0x0F3C0F3C #define HIGH_ISR_MASK (uint32_t)0x20000000 #define RESERVED_MASK (uint32_t)0x0F7D0F7D /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup DMA_Private_Functions * @{ */ /** @defgroup DMA_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== Initialization and Configuration functions =============================================================================== This subsection provides functions allowing to initialize the DMA Stream source and destination addresses, incrementation and data sizes, transfer direction, buffer size, circular/normal mode selection, memory-to-memory mode selection and Stream priority value. The DMA_Init() function follows the DMA configuration procedures as described in reference manual (RM0090) except the first point: waiting on EN bit to be reset. This condition should be checked by user application using the function DMA_GetCmdStatus() before calling the DMA_Init() function. @endverbatim * @{ */ /** * @brief Deinitialize the DMAy Streamx registers to their default reset values. * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @retval None */ void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx) { /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); /* Disable the selected DMAy Streamx */ DMAy_Streamx->CR &= ~((uint32_t)DMA_SxCR_EN); /* Reset DMAy Streamx control register */ DMAy_Streamx->CR = 0; /* Reset DMAy Streamx Number of Data to Transfer register */ DMAy_Streamx->NDTR = 0; /* Reset DMAy Streamx peripheral address register */ DMAy_Streamx->PAR = 0; /* Reset DMAy Streamx memory 0 address register */ DMAy_Streamx->M0AR = 0; /* Reset DMAy Streamx memory 1 address register */ DMAy_Streamx->M1AR = 0; /* Reset DMAy Streamx FIFO control register */ DMAy_Streamx->FCR = (uint32_t)0x00000021; /* Reset interrupt pending bits for the selected stream */ if (DMAy_Streamx == DMA1_Stream0) { /* Reset interrupt pending bits for DMA1 Stream0 */ DMA1->LIFCR = DMA_Stream0_IT_MASK; } else if (DMAy_Streamx == DMA1_Stream1) { /* Reset interrupt pending bits for DMA1 Stream1 */ DMA1->LIFCR = DMA_Stream1_IT_MASK; } else if (DMAy_Streamx == DMA1_Stream2) { /* Reset interrupt pending bits for DMA1 Stream2 */ DMA1->LIFCR = DMA_Stream2_IT_MASK; } else if (DMAy_Streamx == DMA1_Stream3) { /* Reset interrupt pending bits for DMA1 Stream3 */ DMA1->LIFCR = DMA_Stream3_IT_MASK; } else if (DMAy_Streamx == DMA1_Stream4) { /* Reset interrupt pending bits for DMA1 Stream4 */ DMA1->HIFCR = DMA_Stream4_IT_MASK; } else if (DMAy_Streamx == DMA1_Stream5) { /* Reset interrupt pending bits for DMA1 Stream5 */ DMA1->HIFCR = DMA_Stream5_IT_MASK; } else if (DMAy_Streamx == DMA1_Stream6) { /* Reset interrupt pending bits for DMA1 Stream6 */ DMA1->HIFCR = (uint32_t)DMA_Stream6_IT_MASK; } else if (DMAy_Streamx == DMA1_Stream7) { /* Reset interrupt pending bits for DMA1 Stream7 */ DMA1->HIFCR = DMA_Stream7_IT_MASK; } else if (DMAy_Streamx == DMA2_Stream0) { /* Reset interrupt pending bits for DMA2 Stream0 */ DMA2->LIFCR = DMA_Stream0_IT_MASK; } else if (DMAy_Streamx == DMA2_Stream1) { /* Reset interrupt pending bits for DMA2 Stream1 */ DMA2->LIFCR = DMA_Stream1_IT_MASK; } else if (DMAy_Streamx == DMA2_Stream2) { /* Reset interrupt pending bits for DMA2 Stream2 */ DMA2->LIFCR = DMA_Stream2_IT_MASK; } else if (DMAy_Streamx == DMA2_Stream3) { /* Reset interrupt pending bits for DMA2 Stream3 */ DMA2->LIFCR = DMA_Stream3_IT_MASK; } else if (DMAy_Streamx == DMA2_Stream4) { /* Reset interrupt pending bits for DMA2 Stream4 */ DMA2->HIFCR = DMA_Stream4_IT_MASK; } else if (DMAy_Streamx == DMA2_Stream5) { /* Reset interrupt pending bits for DMA2 Stream5 */ DMA2->HIFCR = DMA_Stream5_IT_MASK; } else if (DMAy_Streamx == DMA2_Stream6) { /* Reset interrupt pending bits for DMA2 Stream6 */ DMA2->HIFCR = DMA_Stream6_IT_MASK; } else { if (DMAy_Streamx == DMA2_Stream7) { /* Reset interrupt pending bits for DMA2 Stream7 */ DMA2->HIFCR = DMA_Stream7_IT_MASK; } } } /** * @brief Initializes the DMAy Streamx according to the specified parameters in * the DMA_InitStruct structure. * @note Before calling this function, it is recommended to check that the Stream * is actually disabled using the function DMA_GetCmdStatus(). * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); assert_param(IS_DMA_CHANNEL(DMA_InitStruct->DMA_Channel)); assert_param(IS_DMA_DIRECTION(DMA_InitStruct->DMA_DIR)); assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); assert_param(IS_DMA_FIFO_MODE_STATE(DMA_InitStruct->DMA_FIFOMode)); assert_param(IS_DMA_FIFO_THRESHOLD(DMA_InitStruct->DMA_FIFOThreshold)); assert_param(IS_DMA_MEMORY_BURST(DMA_InitStruct->DMA_MemoryBurst)); assert_param(IS_DMA_PERIPHERAL_BURST(DMA_InitStruct->DMA_PeripheralBurst)); /*------------------------- DMAy Streamx CR Configuration ------------------*/ /* Get the DMAy_Streamx CR value */ tmpreg = DMAy_Streamx->CR; /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ tmpreg &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ DMA_SxCR_DIR)); /* Configure DMAy Streamx: */ /* Set CHSEL bits according to DMA_CHSEL value */ /* Set DIR bits according to DMA_DIR value */ /* Set PINC bit according to DMA_PeripheralInc value */ /* Set MINC bit according to DMA_MemoryInc value */ /* Set PSIZE bits according to DMA_PeripheralDataSize value */ /* Set MSIZE bits according to DMA_MemoryDataSize value */ /* Set CIRC bit according to DMA_Mode value */ /* Set PL bits according to DMA_Priority value */ /* Set MBURST bits according to DMA_MemoryBurst value */ /* Set PBURST bits according to DMA_PeripheralBurst value */ tmpreg |= DMA_InitStruct->DMA_Channel | DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | DMA_InitStruct->DMA_Mode | DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_MemoryBurst | DMA_InitStruct->DMA_PeripheralBurst; /* Write to DMAy Streamx CR register */ DMAy_Streamx->CR = tmpreg; /*------------------------- DMAy Streamx FCR Configuration -----------------*/ /* Get the DMAy_Streamx FCR value */ tmpreg = DMAy_Streamx->FCR; /* Clear DMDIS and FTH bits */ tmpreg &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); /* Configure DMAy Streamx FIFO: Set DMDIS bits according to DMA_FIFOMode value Set FTH bits according to DMA_FIFOThreshold value */ tmpreg |= DMA_InitStruct->DMA_FIFOMode | DMA_InitStruct->DMA_FIFOThreshold; /* Write to DMAy Streamx CR */ DMAy_Streamx->FCR = tmpreg; /*------------------------- DMAy Streamx NDTR Configuration ----------------*/ /* Write to DMAy Streamx NDTR register */ DMAy_Streamx->NDTR = DMA_InitStruct->DMA_BufferSize; /*------------------------- DMAy Streamx PAR Configuration -----------------*/ /* Write to DMAy Streamx PAR */ DMAy_Streamx->PAR = DMA_InitStruct->DMA_PeripheralBaseAddr; /*------------------------- DMAy Streamx M0AR Configuration ----------------*/ /* Write to DMAy Streamx M0AR */ DMAy_Streamx->M0AR = DMA_InitStruct->DMA_Memory0BaseAddr; } /** * @brief Fills each DMA_InitStruct member with its default value. * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will * be initialized. * @retval None */ void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) { /*-------------- Reset DMA init structure parameters values ----------------*/ /* Initialize the DMA_Channel member */ DMA_InitStruct->DMA_Channel = 0; /* Initialize the DMA_PeripheralBaseAddr member */ DMA_InitStruct->DMA_PeripheralBaseAddr = 0; /* Initialize the DMA_Memory0BaseAddr member */ DMA_InitStruct->DMA_Memory0BaseAddr = 0; /* Initialize the DMA_DIR member */ DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralToMemory; /* Initialize the DMA_BufferSize member */ DMA_InitStruct->DMA_BufferSize = 0; /* Initialize the DMA_PeripheralInc member */ DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; /* Initialize the DMA_MemoryInc member */ DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; /* Initialize the DMA_PeripheralDataSize member */ DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; /* Initialize the DMA_MemoryDataSize member */ DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; /* Initialize the DMA_Mode member */ DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; /* Initialize the DMA_Priority member */ DMA_InitStruct->DMA_Priority = DMA_Priority_Low; /* Initialize the DMA_FIFOMode member */ DMA_InitStruct->DMA_FIFOMode = DMA_FIFOMode_Disable; /* Initialize the DMA_FIFOThreshold member */ DMA_InitStruct->DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull; /* Initialize the DMA_MemoryBurst member */ DMA_InitStruct->DMA_MemoryBurst = DMA_MemoryBurst_Single; /* Initialize the DMA_PeripheralBurst member */ DMA_InitStruct->DMA_PeripheralBurst = DMA_PeripheralBurst_Single; } /** * @brief Enables or disables the specified DMAy Streamx. * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @param NewState: new state of the DMAy Streamx. * This parameter can be: ENABLE or DISABLE. * * @note This function may be used to perform Pause-Resume operation. When a * transfer is ongoing, calling this function to disable the Stream will * cause the transfer to be paused. All configuration registers and the * number of remaining data will be preserved. When calling again this * function to re-enable the Stream, the transfer will be resumed from * the point where it was paused. * * @note After configuring the DMA Stream (DMA_Init() function) and enabling the * stream, it is recommended to check (or wait until) the DMA Stream is * effectively enabled. A Stream may remain disabled if a configuration * parameter is wrong. * After disabling a DMA Stream, it is also recommended to check (or wait * until) the DMA Stream is effectively disabled. If a Stream is disabled * while a data transfer is ongoing, the current data will be transferred * and the Stream will be effectively disabled only after the transfer of * this single data is finished. * * @retval None */ void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected DMAy Streamx by setting EN bit */ DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_EN; } else { /* Disable the selected DMAy Streamx by clearing EN bit */ DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_EN; } } /** * @brief Configures, when the PINC (Peripheral Increment address mode) bit is * set, if the peripheral address should be incremented with the data * size (configured with PSIZE bits) or by a fixed offset equal to 4 * (32-bit aligned addresses). * * @note This function has no effect if the Peripheral Increment mode is disabled. * * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @param DMA_Pincos: specifies the Peripheral increment offset size. * This parameter can be one of the following values: * @arg DMA_PINCOS_Psize: Peripheral address increment is done * accordingly to PSIZE parameter. * @arg DMA_PINCOS_WordAligned: Peripheral address increment offset is * fixed to 4 (32-bit aligned addresses). * @retval None */ void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos) { /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); assert_param(IS_DMA_PINCOS_SIZE(DMA_Pincos)); /* Check the needed Peripheral increment offset */ if(DMA_Pincos != DMA_PINCOS_Psize) { /* Configure DMA_SxCR_PINCOS bit with the input parameter */ DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PINCOS; } else { /* Clear the PINCOS bit: Peripheral address incremented according to PSIZE */ DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PINCOS; } } /** * @brief Configures, when the DMAy Streamx is disabled, the flow controller for * the next transactions (Peripheral or Memory). * * @note Before enabling this feature, check if the used peripheral supports * the Flow Controller mode or not. * * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @param DMA_FlowCtrl: specifies the DMA flow controller. * This parameter can be one of the following values: * @arg DMA_FlowCtrl_Memory: DMAy_Streamx transactions flow controller is * the DMA controller. * @arg DMA_FlowCtrl_Peripheral: DMAy_Streamx transactions flow controller * is the peripheral. * @retval None */ void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl) { /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); assert_param(IS_DMA_FLOW_CTRL(DMA_FlowCtrl)); /* Check the needed flow controller */ if(DMA_FlowCtrl != DMA_FlowCtrl_Memory) { /* Configure DMA_SxCR_PFCTRL bit with the input parameter */ DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PFCTRL; } else { /* Clear the PFCTRL bit: Memory is the flow controller */ DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PFCTRL; } } /** * @} */ /** @defgroup DMA_Group2 Data Counter functions * @brief Data Counter functions * @verbatim =============================================================================== Data Counter functions =============================================================================== This subsection provides function allowing to configure and read the buffer size (number of data to be transferred). The DMA data counter can be written only when the DMA Stream is disabled (ie. after transfer complete event). The following function can be used to write the Stream data counter value: - void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter); @note It is advised to use this function rather than DMA_Init() in situations where only the Data buffer needs to be reloaded. @note If the Source and Destination Data Sizes are different, then the value written in data counter, expressing the number of transfers, is relative to the number of transfers from the Peripheral point of view. ie. If Memory data size is Word, Peripheral data size is Half-Words, then the value to be configured in the data counter is the number of Half-Words to be transferred from/to the peripheral. The DMA data counter can be read to indicate the number of remaining transfers for the relative DMA Stream. This counter is decremented at the end of each data transfer and when the transfer is complete: - If Normal mode is selected: the counter is set to 0. - If Circular mode is selected: the counter is reloaded with the initial value (configured before enabling the DMA Stream) The following function can be used to read the Stream data counter value: - uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx); @endverbatim * @{ */ /** * @brief Writes the number of data units to be transferred on the DMAy Streamx. * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @param Counter: Number of data units to be transferred (from 0 to 65535) * Number of data items depends only on the Peripheral data format. * * @note If Peripheral data format is Bytes: number of data units is equal * to total number of bytes to be transferred. * * @note If Peripheral data format is Half-Word: number of data units is * equal to total number of bytes to be transferred / 2. * * @note If Peripheral data format is Word: number of data units is equal * to total number of bytes to be transferred / 4. * * @note In Memory-to-Memory transfer mode, the memory buffer pointed by * DMAy_SxPAR register is considered as Peripheral. * * @retval The number of remaining data units in the current DMAy Streamx transfer. */ void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter) { /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); /* Write the number of data units to be transferred */ DMAy_Streamx->NDTR = (uint16_t)Counter; } /** * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @retval The number of remaining data units in the current DMAy Streamx transfer. */ uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx) { /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); /* Return the number of remaining data units for DMAy Streamx */ return ((uint16_t)(DMAy_Streamx->NDTR)); } /** * @} */ /** @defgroup DMA_Group3 Double Buffer mode functions * @brief Double Buffer mode functions * @verbatim =============================================================================== Double Buffer mode functions =============================================================================== This subsection provides function allowing to configure and control the double buffer mode parameters. The Double Buffer mode can be used only when Circular mode is enabled. The Double Buffer mode cannot be used when transferring data from Memory to Memory. The Double Buffer mode allows to set two different Memory addresses from/to which the DMA controller will access alternatively (after completing transfer to/from target memory 0, it will start transfer to/from target memory 1). This allows to reduce software overhead for double buffering and reduce the CPU access time. Two functions must be called before calling the DMA_Init() function: - void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr, uint32_t DMA_CurrentMemory); - void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); DMA_DoubleBufferModeConfig() is called to configure the Memory 1 base address and the first Memory target from/to which the transfer will start after enabling the DMA Stream. Then DMA_DoubleBufferModeCmd() must be called to enable the Double Buffer mode (or disable it when it should not be used). Two functions can be called dynamically when the transfer is ongoing (or when the DMA Stream is stopped) to modify on of the target Memories addresses or to check wich Memory target is currently used: - void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr, uint32_t DMA_MemoryTarget); - uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx); DMA_MemoryTargetConfig() can be called to modify the base address of one of the two target Memories. The Memory of which the base address will be modified must not be currently be used by the DMA Stream (ie. if the DMA Stream is currently transferring from Memory 1 then you can only modify base address of target Memory 0 and vice versa). To check this condition, it is recommended to use the function DMA_GetCurrentMemoryTarget() which returns the index of the Memory target currently in use by the DMA Stream. @endverbatim * @{ */ /** * @brief Configures, when the DMAy Streamx is disabled, the double buffer mode * and the current memory target. * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @param Memory1BaseAddr: the base address of the second buffer (Memory 1) * @param DMA_CurrentMemory: specifies which memory will be first buffer for * the transactions when the Stream will be enabled. * This parameter can be one of the following values: * @arg DMA_Memory_0: Memory 0 is the current buffer. * @arg DMA_Memory_1: Memory 1 is the current buffer. * * @note Memory0BaseAddr is set by the DMA structure configuration in DMA_Init(). * * @retval None */ void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr, uint32_t DMA_CurrentMemory) { /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); assert_param(IS_DMA_CURRENT_MEM(DMA_CurrentMemory)); if (DMA_CurrentMemory != DMA_Memory_0) { /* Set Memory 1 as current memory address */ DMAy_Streamx->CR |= (uint32_t)(DMA_SxCR_CT); } else { /* Set Memory 0 as current memory address */ DMAy_Streamx->CR &= ~(uint32_t)(DMA_SxCR_CT); } /* Write to DMAy Streamx M1AR */ DMAy_Streamx->M1AR = Memory1BaseAddr; } /** * @brief Enables or disables the double buffer mode for the selected DMA stream. * @note This function can be called only when the DMA Stream is disabled. * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @param NewState: new state of the DMAy Streamx double buffer mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); /* Configure the Double Buffer mode */ if (NewState != DISABLE) { /* Enable the Double buffer mode */ DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_DBM; } else { /* Disable the Double buffer mode */ DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_DBM; } } /** * @brief Configures the Memory address for the next buffer transfer in double * buffer mode (for dynamic use). This function can be called when the * DMA Stream is enabled and when the transfer is ongoing. * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @param MemoryBaseAddr: The base address of the target memory buffer * @param DMA_MemoryTarget: Next memory target to be used. * This parameter can be one of the following values: * @arg DMA_Memory_0: To use the memory address 0 * @arg DMA_Memory_1: To use the memory address 1 * * @note It is not allowed to modify the Base Address of a target Memory when * this target is involved in the current transfer. ie. If the DMA Stream * is currently transferring to/from Memory 1, then it not possible to * modify Base address of Memory 1, but it is possible to modify Base * address of Memory 0. * To know which Memory is currently used, you can use the function * DMA_GetCurrentMemoryTarget(). * * @retval None */ void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr, uint32_t DMA_MemoryTarget) { /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); assert_param(IS_DMA_CURRENT_MEM(DMA_MemoryTarget)); /* Check the Memory target to be configured */ if (DMA_MemoryTarget != DMA_Memory_0) { /* Write to DMAy Streamx M1AR */ DMAy_Streamx->M1AR = MemoryBaseAddr; } else { /* Write to DMAy Streamx M0AR */ DMAy_Streamx->M0AR = MemoryBaseAddr; } } /** * @brief Returns the current memory target used by double buffer transfer. * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @retval The memory target number: 0 for Memory0 or 1 for Memory1. */ uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx) { uint32_t tmp = 0; /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); /* Get the current memory target */ if ((DMAy_Streamx->CR & DMA_SxCR_CT) != 0) { /* Current memory buffer used is Memory 1 */ tmp = 1; } else { /* Current memory buffer used is Memory 0 */ tmp = 0; } return tmp; } /** * @} */ /** @defgroup DMA_Group4 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== Interrupts and flags management functions =============================================================================== This subsection provides functions allowing to - Check the DMA enable status - Check the FIFO status - Configure the DMA Interrupts sources and check or clear the flags or pending bits status. 1. DMA Enable status: After configuring the DMA Stream (DMA_Init() function) and enabling the stream, it is recommended to check (or wait until) the DMA Stream is effectively enabled. A Stream may remain disabled if a configuration parameter is wrong. After disabling a DMA Stream, it is also recommended to check (or wait until) the DMA Stream is effectively disabled. If a Stream is disabled while a data transfer is ongoing, the current data will be transferred and the Stream will be effectively disabled only after this data transfer completion. To monitor this state it is possible to use the following function: - FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx); 2. FIFO Status: It is possible to monitor the FIFO status when a transfer is ongoing using the following function: - uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx); 3. DMA Interrupts and Flags: The user should identify which mode will be used in his application to manage the DMA controller events: Polling mode or Interrupt mode. Polling Mode ============= Each DMA stream can be managed through 4 event Flags: (x : DMA Stream number ) 1. DMA_FLAG_FEIFx : to indicate that a FIFO Mode Transfer Error event occurred. 2. DMA_FLAG_DMEIFx : to indicate that a Direct Mode Transfer Error event occurred. 3. DMA_FLAG_TEIFx : to indicate that a Transfer Error event occurred. 4. DMA_FLAG_HTIFx : to indicate that a Half-Transfer Complete event occurred. 5. DMA_FLAG_TCIFx : to indicate that a Transfer Complete event occurred . In this Mode it is advised to use the following functions: - FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); - void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); Interrupt Mode =============== Each DMA Stream can be managed through 4 Interrupts: Interrupt Source ---------------- 1. DMA_IT_FEIFx : specifies the interrupt source for the FIFO Mode Transfer Error event. 2. DMA_IT_DMEIFx : specifies the interrupt source for the Direct Mode Transfer Error event. 3. DMA_IT_TEIFx : specifies the interrupt source for the Transfer Error event. 4. DMA_IT_HTIFx : specifies the interrupt source for the Half-Transfer Complete event. 5. DMA_IT_TCIFx : specifies the interrupt source for the a Transfer Complete event. In this Mode it is advised to use the following functions: - void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState); - ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); - void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); @endverbatim * @{ */ /** * @brief Returns the status of EN bit for the specified DMAy Streamx. * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * * @note After configuring the DMA Stream (DMA_Init() function) and enabling * the stream, it is recommended to check (or wait until) the DMA Stream * is effectively enabled. A Stream may remain disabled if a configuration * parameter is wrong. * After disabling a DMA Stream, it is also recommended to check (or wait * until) the DMA Stream is effectively disabled. If a Stream is disabled * while a data transfer is ongoing, the current data will be transferred * and the Stream will be effectively disabled only after the transfer * of this single data is finished. * * @retval Current state of the DMAy Streamx (ENABLE or DISABLE). */ FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx) { FunctionalState state = DISABLE; /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); if ((DMAy_Streamx->CR & (uint32_t)DMA_SxCR_EN) != 0) { /* The selected DMAy Streamx EN bit is set (DMA is still transferring) */ state = ENABLE; } else { /* The selected DMAy Streamx EN bit is cleared (DMA is disabled and all transfers are complete) */ state = DISABLE; } return state; } /** * @brief Returns the current DMAy Streamx FIFO filled level. * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @retval The FIFO filling state. * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full * and not empty. * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. * - DMA_FIFOStatus_Empty: when FIFO is empty * - DMA_FIFOStatus_Full: when FIFO is full */ uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); /* Get the FIFO level bits */ tmpreg = (uint32_t)((DMAy_Streamx->FCR & DMA_SxFCR_FS)); return tmpreg; } /** * @brief Checks whether the specified DMAy Streamx flag is set or not. * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @param DMA_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag * @arg DMA_FLAG_TEIFx: Streamx transfer error flag * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag * Where x can be 0 to 7 to select the DMA Stream. * @retval The new state of DMA_FLAG (SET or RESET). */ FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG) { FlagStatus bitstatus = RESET; DMA_TypeDef* DMAy; uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); assert_param(IS_DMA_GET_FLAG(DMA_FLAG)); /* Determine the DMA to which belongs the stream */ if (DMAy_Streamx < DMA2_Stream0) { /* DMAy_Streamx belongs to DMA1 */ DMAy = DMA1; } else { /* DMAy_Streamx belongs to DMA2 */ DMAy = DMA2; } /* Check if the flag is in HISR or LISR */ if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET) { /* Get DMAy HISR register value */ tmpreg = DMAy->HISR; } else { /* Get DMAy LISR register value */ tmpreg = DMAy->LISR; } /* Mask the reserved bits */ tmpreg &= (uint32_t)RESERVED_MASK; /* Check the status of the specified DMA flag */ if ((tmpreg & DMA_FLAG) != (uint32_t)RESET) { /* DMA_FLAG is set */ bitstatus = SET; } else { /* DMA_FLAG is reset */ bitstatus = RESET; } /* Return the DMA_FLAG status */ return bitstatus; } /** * @brief Clears the DMAy Streamx's pending flags. * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @param DMA_FLAG: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag * @arg DMA_FLAG_TEIFx: Streamx transfer error flag * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag * Where x can be 0 to 7 to select the DMA Stream. * @retval None */ void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG) { DMA_TypeDef* DMAy; /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG)); /* Determine the DMA to which belongs the stream */ if (DMAy_Streamx < DMA2_Stream0) { /* DMAy_Streamx belongs to DMA1 */ DMAy = DMA1; } else { /* DMAy_Streamx belongs to DMA2 */ DMAy = DMA2; } /* Check if LIFCR or HIFCR register is targeted */ if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET) { /* Set DMAy HIFCR register clear flag bits */ DMAy->HIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK); } else { /* Set DMAy LIFCR register clear flag bits */ DMAy->LIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK); } } /** * @brief Enables or disables the specified DMAy Streamx interrupts. * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @param DMA_IT: specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask * @arg DMA_IT_TE: Transfer error interrupt mask * @arg DMA_IT_FE: FIFO error interrupt mask * @param NewState: new state of the specified DMA interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); assert_param(IS_DMA_CONFIG_IT(DMA_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); /* Check if the DMA_IT parameter contains a FIFO interrupt */ if ((DMA_IT & DMA_IT_FE) != 0) { if (NewState != DISABLE) { /* Enable the selected DMA FIFO interrupts */ DMAy_Streamx->FCR |= (uint32_t)DMA_IT_FE; } else { /* Disable the selected DMA FIFO interrupts */ DMAy_Streamx->FCR &= ~(uint32_t)DMA_IT_FE; } } /* Check if the DMA_IT parameter contains a Transfer interrupt */ if (DMA_IT != DMA_IT_FE) { if (NewState != DISABLE) { /* Enable the selected DMA transfer interrupts */ DMAy_Streamx->CR |= (uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK); } else { /* Disable the selected DMA transfer interrupts */ DMAy_Streamx->CR &= ~(uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK); } } } /** * @brief Checks whether the specified DMAy Streamx interrupt has occurred or not. * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @param DMA_IT: specifies the DMA interrupt source to check. * This parameter can be one of the following values: * @arg DMA_IT_TCIFx: Streamx transfer complete interrupt * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt * @arg DMA_IT_TEIFx: Streamx transfer error interrupt * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt * Where x can be 0 to 7 to select the DMA Stream. * @retval The new state of DMA_IT (SET or RESET). */ ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT) { ITStatus bitstatus = RESET; DMA_TypeDef* DMAy; uint32_t tmpreg = 0, enablestatus = 0; /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); assert_param(IS_DMA_GET_IT(DMA_IT)); /* Determine the DMA to which belongs the stream */ if (DMAy_Streamx < DMA2_Stream0) { /* DMAy_Streamx belongs to DMA1 */ DMAy = DMA1; } else { /* DMAy_Streamx belongs to DMA2 */ DMAy = DMA2; } /* Check if the interrupt enable bit is in the CR or FCR register */ if ((DMA_IT & TRANSFER_IT_MASK) != (uint32_t)RESET) { /* Get the interrupt enable position mask in CR register */ tmpreg = (uint32_t)((DMA_IT >> 11) & TRANSFER_IT_ENABLE_MASK); /* Check the enable bit in CR register */ enablestatus = (uint32_t)(DMAy_Streamx->CR & tmpreg); } else { /* Check the enable bit in FCR register */ enablestatus = (uint32_t)(DMAy_Streamx->FCR & DMA_IT_FE); } /* Check if the interrupt pending flag is in LISR or HISR */ if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET) { /* Get DMAy HISR register value */ tmpreg = DMAy->HISR ; } else { /* Get DMAy LISR register value */ tmpreg = DMAy->LISR ; } /* mask all reserved bits */ tmpreg &= (uint32_t)RESERVED_MASK; /* Check the status of the specified DMA interrupt */ if (((tmpreg & DMA_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) { /* DMA_IT is set */ bitstatus = SET; } else { /* DMA_IT is reset */ bitstatus = RESET; } /* Return the DMA_IT status */ return bitstatus; } /** * @brief Clears the DMAy Streamx's interrupt pending bits. * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @param DMA_IT: specifies the DMA interrupt pending bit to clear. * This parameter can be any combination of the following values: * @arg DMA_IT_TCIFx: Streamx transfer complete interrupt * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt * @arg DMA_IT_TEIFx: Streamx transfer error interrupt * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt * Where x can be 0 to 7 to select the DMA Stream. * @retval None */ void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT) { DMA_TypeDef* DMAy; /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); assert_param(IS_DMA_CLEAR_IT(DMA_IT)); /* Determine the DMA to which belongs the stream */ if (DMAy_Streamx < DMA2_Stream0) { /* DMAy_Streamx belongs to DMA1 */ DMAy = DMA1; } else { /* DMAy_Streamx belongs to DMA2 */ DMAy = DMA2; } /* Check if LIFCR or HIFCR register is targeted */ if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET) { /* Set DMAy HIFCR register clear interrupt bits */ DMAy->HIFCR = (uint32_t)(DMA_IT & RESERVED_MASK); } else { /* Set DMAy LIFCR register clear interrupt bits */ DMAy->LIFCR = (uint32_t)(DMA_IT & RESERVED_MASK); } } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c ================================================ /** ****************************************************************************** * @file stm32f4xx_exti.c * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file provides firmware functions to manage the following * functionalities of the EXTI peripheral: * - Initialization and Configuration * - Interrupts and flags management * * @verbatim * * =================================================================== * EXTI features * =================================================================== * * External interrupt/event lines are mapped as following: * 1- All available GPIO pins are connected to the 16 external * interrupt/event lines from EXTI0 to EXTI15. * 2- EXTI line 16 is connected to the PVD Output * 3- EXTI line 17 is connected to the RTC Alarm event * 4- EXTI line 18 is connected to the USB OTG FS Wakeup from suspend event * 5- EXTI line 19 is connected to the Ethernet Wakeup event * 6- EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event * 7- EXTI line 21 is connected to the RTC Tamper and Time Stamp events * 8- EXTI line 22 is connected to the RTC Wakeup event * * =================================================================== * How to use this driver * =================================================================== * * In order to use an I/O pin as an external interrupt source, follow * steps below: * 1- Configure the I/O in input mode using GPIO_Init() * 2- Select the input source pin for the EXTI line using SYSCFG_EXTILineConfig() * 3- Select the mode(interrupt, event) and configure the trigger * selection (Rising, falling or both) using EXTI_Init() * 4- Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init() * * @note SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx * registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); * * @endverbatim * ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_exti.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup EXTI * @brief EXTI driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup EXTI_Private_Functions * @{ */ /** @defgroup EXTI_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== Initialization and Configuration functions =============================================================================== @endverbatim * @{ */ /** * @brief Deinitializes the EXTI peripheral registers to their default reset values. * @param None * @retval None */ void EXTI_DeInit(void) { EXTI->IMR = 0x00000000; EXTI->EMR = 0x00000000; EXTI->RTSR = 0x00000000; EXTI->FTSR = 0x00000000; EXTI->PR = 0x007FFFFF; } /** * @brief Initializes the EXTI peripheral according to the specified * parameters in the EXTI_InitStruct. * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure * that contains the configuration information for the EXTI peripheral. * @retval None */ void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) { uint32_t tmp = 0; /* Check the parameters */ assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); tmp = (uint32_t)EXTI_BASE; if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) { /* Clear EXTI line configuration */ EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; tmp += EXTI_InitStruct->EXTI_Mode; *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; /* Clear Rising Falling edge configuration */ EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; /* Select the trigger for the selected external interrupts */ if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) { /* Rising Falling edge */ EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; } else { tmp = (uint32_t)EXTI_BASE; tmp += EXTI_InitStruct->EXTI_Trigger; *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; } } else { tmp += EXTI_InitStruct->EXTI_Mode; /* Disable the selected external lines */ *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; } } /** * @brief Fills each EXTI_InitStruct member with its reset value. * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will * be initialized. * @retval None */ void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) { EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; EXTI_InitStruct->EXTI_LineCmd = DISABLE; } /** * @brief Generates a Software interrupt on selected EXTI line. * @param EXTI_Line: specifies the EXTI line on which the software interrupt * will be generated. * This parameter can be any combination of EXTI_Linex where x can be (0..22) * @retval None */ void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) { /* Check the parameters */ assert_param(IS_EXTI_LINE(EXTI_Line)); EXTI->SWIER |= EXTI_Line; } /** * @} */ /** @defgroup EXTI_Group2 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== Interrupts and flags management functions =============================================================================== @endverbatim * @{ */ /** * @brief Checks whether the specified EXTI line flag is set or not. * @param EXTI_Line: specifies the EXTI line flag to check. * This parameter can be EXTI_Linex where x can be(0..22) * @retval The new state of EXTI_Line (SET or RESET). */ FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_GET_EXTI_LINE(EXTI_Line)); if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears the EXTI's line pending flags. * @param EXTI_Line: specifies the EXTI lines flags to clear. * This parameter can be any combination of EXTI_Linex where x can be (0..22) * @retval None */ void EXTI_ClearFlag(uint32_t EXTI_Line) { /* Check the parameters */ assert_param(IS_EXTI_LINE(EXTI_Line)); EXTI->PR = EXTI_Line; } /** * @brief Checks whether the specified EXTI line is asserted or not. * @param EXTI_Line: specifies the EXTI line to check. * This parameter can be EXTI_Linex where x can be(0..22) * @retval The new state of EXTI_Line (SET or RESET). */ ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) { ITStatus bitstatus = RESET; uint32_t enablestatus = 0; /* Check the parameters */ assert_param(IS_GET_EXTI_LINE(EXTI_Line)); enablestatus = EXTI->IMR & EXTI_Line; if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears the EXTI's line pending bits. * @param EXTI_Line: specifies the EXTI lines to clear. * This parameter can be any combination of EXTI_Linex where x can be (0..22) * @retval None */ void EXTI_ClearITPendingBit(uint32_t EXTI_Line) { /* Check the parameters */ assert_param(IS_EXTI_LINE(EXTI_Line)); EXTI->PR = EXTI_Line; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash.c ================================================ /** ****************************************************************************** * @file stm32f4xx_flash.c * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file provides firmware functions to manage the following * functionalities of the FLASH peripheral: * - FLASH Interface configuration * - FLASH Memory Programming * - Option Bytes Programming * - Interrupts and flags management * * @verbatim * * =================================================================== * How to use this driver * =================================================================== * * This driver provides functions to configure and program the FLASH * memory of all STM32F4xx devices. * These functions are split in 4 groups: * * 1. FLASH Interface configuration functions: this group includes the * management of the following features: * - Set the latency * - Enable/Disable the prefetch buffer * - Enable/Disable the Instruction cache and the Data cache * - Reset the Instruction cache and the Data cache * * 2. FLASH Memory Programming functions: this group includes all needed * functions to erase and program the main memory: * - Lock and Unlock the FLASH interface * - Erase function: Erase sector, erase all sectors * - Program functions: byte, half word, word and double word * * 3. Option Bytes Programming functions: this group includes all needed * functions to manage the Option Bytes: * - Set/Reset the write protection * - Set the Read protection Level * - Set the BOR level * - Program the user Option Bytes * - Launch the Option Bytes loader * * 4. Interrupts and flags management functions: this group * includes all needed functions to: * - Enable/Disable the FLASH interrupt sources * - Get flags status * - Clear flags * - Get FLASH operation status * - Wait for last FLASH operation * * @endverbatim * ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_flash.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup FLASH * @brief FLASH driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #define SECTOR_MASK ((uint32_t)0xFFFFFF07) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup FLASH_Private_Functions * @{ */ /** @defgroup FLASH_Group1 FLASH Interface configuration functions * @brief FLASH Interface configuration functions * @verbatim =============================================================================== FLASH Interface configuration functions =============================================================================== This group includes the following functions: - void FLASH_SetLatency(uint32_t FLASH_Latency) To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. +-------------------------------------------------------------------------------------+ | Latency | HCLK clock frequency (MHz) | | |---------------------------------------------------------------------| | | voltage range | voltage range | voltage range | voltage range | | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | |---------------|----------------|----------------|-----------------|-----------------| |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 | |---------------|----------------|----------------|-----------------|-----------------| |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 | |---------------|----------------|----------------|-----------------|-----------------| |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 | |---------------|----------------|----------------|-----------------|-----------------| |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 | |---------------|----------------|----------------|-----------------|-----------------| |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 | |---------------|----------------|----------------|-----------------|-----------------| |5WS(6CPU cycle)|120< HCLK <= 168|120< HCLK <= 144|90 < HCLK <= 108 |80 < HCLK <= 96 | |---------------|----------------|----------------|-----------------|-----------------| |6WS(7CPU cycle)| NA |144< HCLK <= 168|108 < HCLK <= 120|96 < HCLK <= 112 | |---------------|----------------|----------------|-----------------|-----------------| |7WS(8CPU cycle)| NA | NA |120 < HCLK <= 138|112 < HCLK <= 120| |***************|****************|****************|*****************|*****************|*****************************+ | | voltage range | voltage range | voltage range | voltage range | voltage range 2.7 V - 3.6 V | | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | with External Vpp = 9V | |---------------|----------------|----------------|-----------------|-----------------|-----------------------------| |Max Parallelism| x32 | x16 | x8 | x64 | |---------------|----------------|----------------|-----------------|-----------------|-----------------------------| |PSIZE[1:0] | 10 | 01 | 00 | 11 | +-------------------------------------------------------------------------------------------------------------------+ @note When VOS bit (in PWR_CR register) is reset to '0, the maximum value of HCLK is 144 MHz. You can use PWR_MainRegulatorModeConfig() function to set or reset this bit. - void FLASH_PrefetchBufferCmd(FunctionalState NewState) - void FLASH_InstructionCacheCmd(FunctionalState NewState) - void FLASH_DataCacheCmd(FunctionalState NewState) - void FLASH_InstructionCacheReset(void) - void FLASH_DataCacheReset(void) The unlock sequence is not needed for these functions. @endverbatim * @{ */ /** * @brief Sets the code latency value. * @param FLASH_Latency: specifies the FLASH Latency value. * This parameter can be one of the following values: * @arg FLASH_Latency_0: FLASH Zero Latency cycle * @arg FLASH_Latency_1: FLASH One Latency cycle * @arg FLASH_Latency_2: FLASH Two Latency cycles * @arg FLASH_Latency_3: FLASH Three Latency cycles * @arg FLASH_Latency_4: FLASH Four Latency cycles * @arg FLASH_Latency_5: FLASH Five Latency cycles * @arg FLASH_Latency_6: FLASH Six Latency cycles * @arg FLASH_Latency_7: FLASH Seven Latency cycles * @retval None */ void FLASH_SetLatency(uint32_t FLASH_Latency) { /* Check the parameters */ assert_param(IS_FLASH_LATENCY(FLASH_Latency)); /* Perform Byte access to FLASH_ACR[8:0] to set the Latency value */ *(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)FLASH_Latency; } /** * @brief Enables or disables the Prefetch Buffer. * @param NewState: new state of the Prefetch Buffer. * This parameter can be: ENABLE or DISABLE. * @retval None */ void FLASH_PrefetchBufferCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); /* Enable or disable the Prefetch Buffer */ if(NewState != DISABLE) { FLASH->ACR |= FLASH_ACR_PRFTEN; } else { FLASH->ACR &= (~FLASH_ACR_PRFTEN); } } /** * @brief Enables or disables the Instruction Cache feature. * @param NewState: new state of the Instruction Cache. * This parameter can be: ENABLE or DISABLE. * @retval None */ void FLASH_InstructionCacheCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if(NewState != DISABLE) { FLASH->ACR |= FLASH_ACR_ICEN; } else { FLASH->ACR &= (~FLASH_ACR_ICEN); } } /** * @brief Enables or disables the Data Cache feature. * @param NewState: new state of the Data Cache. * This parameter can be: ENABLE or DISABLE. * @retval None */ void FLASH_DataCacheCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if(NewState != DISABLE) { FLASH->ACR |= FLASH_ACR_DCEN; } else { FLASH->ACR &= (~FLASH_ACR_DCEN); } } /** * @brief Resets the Instruction Cache. * @note This function must be used only when the Instruction Cache is disabled. * @param None * @retval None */ void FLASH_InstructionCacheReset(void) { FLASH->ACR |= FLASH_ACR_ICRST; } /** * @brief Resets the Data Cache. * @note This function must be used only when the Data Cache is disabled. * @param None * @retval None */ void FLASH_DataCacheReset(void) { FLASH->ACR |= FLASH_ACR_DCRST; } /** * @} */ /** @defgroup FLASH_Group2 FLASH Memory Programming functions * @brief FLASH Memory Programming functions * @verbatim =============================================================================== FLASH Memory Programming functions =============================================================================== This group includes the following functions: - void FLASH_Unlock(void) - void FLASH_Lock(void) - FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange) - FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange) - FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data) - FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) - FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) - FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data) Any operation of erase or program should follow these steps: 1. Call the FLASH_Unlock() function to enable the FLASH control register access 2. Call the desired function to erase sector(s) or program data 3. Call the FLASH_Lock() function to disable the FLASH control register access (recommended to protect the FLASH memory against possible unwanted operation) @endverbatim * @{ */ /** * @brief Unlocks the FLASH control register access * @param None * @retval None */ void FLASH_Unlock(void) { if((FLASH->CR & FLASH_CR_LOCK) != RESET) { /* Authorize the FLASH Registers access */ FLASH->KEYR = FLASH_KEY1; FLASH->KEYR = FLASH_KEY2; } } /** * @brief Locks the FLASH control register access * @param None * @retval None */ void FLASH_Lock(void) { /* Set the LOCK Bit to lock the FLASH Registers access */ FLASH->CR |= FLASH_CR_LOCK; } /** * @brief Erases a specified FLASH Sector. * * @param FLASH_Sector: The Sector number to be erased. * This parameter can be a value between FLASH_Sector_0 and FLASH_Sector_11 * * @param VoltageRange: The device voltage range which defines the erase parallelism. * This parameter can be one of the following values: * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, * the operation will be done by byte (8-bit) * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, * the operation will be done by half word (16-bit) * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, * the operation will be done by word (32-bit) * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, * the operation will be done by double word (64-bit) * * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. */ FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange) { uint32_t tmp_psize = 0x0; FLASH_Status status = FLASH_COMPLETE; /* Check the parameters */ assert_param(IS_FLASH_SECTOR(FLASH_Sector)); assert_param(IS_VOLTAGERANGE(VoltageRange)); if(VoltageRange == VoltageRange_1) { tmp_psize = FLASH_PSIZE_BYTE; } else if(VoltageRange == VoltageRange_2) { tmp_psize = FLASH_PSIZE_HALF_WORD; } else if(VoltageRange == VoltageRange_3) { tmp_psize = FLASH_PSIZE_WORD; } else { tmp_psize = FLASH_PSIZE_DOUBLE_WORD; } /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); if(status == FLASH_COMPLETE) { /* if the previous operation is completed, proceed to erase the sector */ FLASH->CR &= CR_PSIZE_MASK; FLASH->CR |= tmp_psize; FLASH->CR &= SECTOR_MASK; FLASH->CR |= FLASH_CR_SER | FLASH_Sector; FLASH->CR |= FLASH_CR_STRT; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); /* if the erase operation is completed, disable the SER Bit */ FLASH->CR &= (~FLASH_CR_SER); FLASH->CR &= SECTOR_MASK; } /* Return the Erase Status */ return status; } /** * @brief Erases all FLASH Sectors. * * @param VoltageRange: The device voltage range which defines the erase parallelism. * This parameter can be one of the following values: * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, * the operation will be done by byte (8-bit) * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, * the operation will be done by half word (16-bit) * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, * the operation will be done by word (32-bit) * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, * the operation will be done by double word (64-bit) * * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. */ FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange) { uint32_t tmp_psize = 0x0; FLASH_Status status = FLASH_COMPLETE; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); assert_param(IS_VOLTAGERANGE(VoltageRange)); if(VoltageRange == VoltageRange_1) { tmp_psize = FLASH_PSIZE_BYTE; } else if(VoltageRange == VoltageRange_2) { tmp_psize = FLASH_PSIZE_HALF_WORD; } else if(VoltageRange == VoltageRange_3) { tmp_psize = FLASH_PSIZE_WORD; } else { tmp_psize = FLASH_PSIZE_DOUBLE_WORD; } if(status == FLASH_COMPLETE) { /* if the previous operation is completed, proceed to erase all sectors */ FLASH->CR &= CR_PSIZE_MASK; FLASH->CR |= tmp_psize; FLASH->CR |= FLASH_CR_MER; FLASH->CR |= FLASH_CR_STRT; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); /* if the erase operation is completed, disable the MER Bit */ FLASH->CR &= (~FLASH_CR_MER); } /* Return the Erase Status */ return status; } /** * @brief Programs a double word (64-bit) at a specified address. * @note This function must be used when the device voltage range is from * 2.7V to 3.6V and an External Vpp is present. * @param Address: specifies the address to be programmed. * @param Data: specifies the data to be programmed. * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. */ FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data) { FLASH_Status status = FLASH_COMPLETE; /* Check the parameters */ assert_param(IS_FLASH_ADDRESS(Address)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); if(status == FLASH_COMPLETE) { /* if the previous operation is completed, proceed to program the new data */ FLASH->CR &= CR_PSIZE_MASK; FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD; FLASH->CR |= FLASH_CR_PG; *(__IO uint64_t*)Address = Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); /* if the program operation is completed, disable the PG Bit */ FLASH->CR &= (~FLASH_CR_PG); } /* Return the Program Status */ return status; } /** * @brief Programs a word (32-bit) at a specified address. * @param Address: specifies the address to be programmed. * This parameter can be any address in Program memory zone or in OTP zone. * @note This function must be used when the device voltage range is from 2.7V to 3.6V. * @param Data: specifies the data to be programmed. * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. */ FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) { FLASH_Status status = FLASH_COMPLETE; /* Check the parameters */ assert_param(IS_FLASH_ADDRESS(Address)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); if(status == FLASH_COMPLETE) { /* if the previous operation is completed, proceed to program the new data */ FLASH->CR &= CR_PSIZE_MASK; FLASH->CR |= FLASH_PSIZE_WORD; FLASH->CR |= FLASH_CR_PG; *(__IO uint32_t*)Address = Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); /* if the program operation is completed, disable the PG Bit */ FLASH->CR &= (~FLASH_CR_PG); } /* Return the Program Status */ return status; } /** * @brief Programs a half word (16-bit) at a specified address. * @note This function must be used when the device voltage range is from 2.1V to 3.6V. * @param Address: specifies the address to be programmed. * This parameter can be any address in Program memory zone or in OTP zone. * @param Data: specifies the data to be programmed. * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. */ FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) { FLASH_Status status = FLASH_COMPLETE; /* Check the parameters */ assert_param(IS_FLASH_ADDRESS(Address)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); if(status == FLASH_COMPLETE) { /* if the previous operation is completed, proceed to program the new data */ FLASH->CR &= CR_PSIZE_MASK; FLASH->CR |= FLASH_PSIZE_HALF_WORD; FLASH->CR |= FLASH_CR_PG; *(__IO uint16_t*)Address = Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); /* if the program operation is completed, disable the PG Bit */ FLASH->CR &= (~FLASH_CR_PG); } /* Return the Program Status */ return status; } /** * @brief Programs a byte (8-bit) at a specified address. * @note This function can be used within all the device supply voltage ranges. * @param Address: specifies the address to be programmed. * This parameter can be any address in Program memory zone or in OTP zone. * @param Data: specifies the data to be programmed. * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. */ FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data) { FLASH_Status status = FLASH_COMPLETE; /* Check the parameters */ assert_param(IS_FLASH_ADDRESS(Address)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); if(status == FLASH_COMPLETE) { /* if the previous operation is completed, proceed to program the new data */ FLASH->CR &= CR_PSIZE_MASK; FLASH->CR |= FLASH_PSIZE_BYTE; FLASH->CR |= FLASH_CR_PG; *(__IO uint8_t*)Address = Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); /* if the program operation is completed, disable the PG Bit */ FLASH->CR &= (~FLASH_CR_PG); } /* Return the Program Status */ return status; } /** * @} */ /** @defgroup FLASH_Group3 Option Bytes Programming functions * @brief Option Bytes Programming functions * @verbatim =============================================================================== Option Bytes Programming functions =============================================================================== This group includes the following functions: - void FLASH_OB_Unlock(void) - void FLASH_OB_Lock(void) - void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) - void FLASH_OB_RDPConfig(uint8_t OB_RDP) - void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) - void FLASH_OB_BORConfig(uint8_t OB_BOR) - FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data) - FLASH_Status FLASH_OB_Launch(void) - uint32_t FLASH_OB_GetUser(void) - uint8_t FLASH_OB_GetWRP(void) - uint8_t FLASH_OB_GetRDP(void) - uint8_t FLASH_OB_GetBOR(void) Any operation of erase or program should follow these steps: 1. Call the FLASH_OB_Unlock() function to enable the FLASH option control register access 2. Call one or several functions to program the desired Option Bytes: - void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) => to Enable/Disable the desired sector write protection - void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read Protection Level - void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) => to configure the user Option Bytes. - void FLASH_OB_BORConfig(uint8_t OB_BOR) => to set the BOR Level 3. Once all needed Option Bytes to be programmed are correctly written, call the FLASH_OB_Launch() function to launch the Option Bytes programming process. @note When changing the IWDG mode from HW to SW or from SW to HW, a system reset is needed to make the change effective. 4. Call the FLASH_OB_Lock() function to disable the FLASH option control register access (recommended to protect the Option Bytes against possible unwanted operations) @endverbatim * @{ */ /** * @brief Unlocks the FLASH Option Control Registers access. * @param None * @retval None */ void FLASH_OB_Unlock(void) { if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET) { /* Authorizes the Option Byte register programming */ FLASH->OPTKEYR = FLASH_OPT_KEY1; FLASH->OPTKEYR = FLASH_OPT_KEY2; } } /** * @brief Locks the FLASH Option Control Registers access. * @param None * @retval None */ void FLASH_OB_Lock(void) { /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK; } /** * @brief Enables or disables the write protection of the desired sectors * @param OB_WRP: specifies the sector(s) to be write protected or unprotected. * This parameter can be one of the following values: * @arg OB_WRP: A value between OB_WRP_Sector0 and OB_WRP_Sector11 * @arg OB_WRP_Sector_All * @param Newstate: new state of the Write Protection. * This parameter can be: ENABLE or DISABLE. * @retval None */ void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) { FLASH_Status status = FLASH_COMPLETE; /* Check the parameters */ assert_param(IS_OB_WRP(OB_WRP)); assert_param(IS_FUNCTIONAL_STATE(NewState)); status = FLASH_WaitForLastOperation(); if(status == FLASH_COMPLETE) { if(NewState != DISABLE) { *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_WRP); } else { *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_WRP; } } } /** * @brief Sets the read protection level. * @param OB_RDP: specifies the read protection level. * This parameter can be one of the following values: * @arg OB_RDP_Level_0: No protection * @arg OB_RDP_Level_1: Read protection of the memory * @arg OB_RDP_Level_2: Full chip protection * * !!!Warning!!! When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 * * @retval None */ void FLASH_OB_RDPConfig(uint8_t OB_RDP) { FLASH_Status status = FLASH_COMPLETE; /* Check the parameters */ assert_param(IS_OB_RDP(OB_RDP)); status = FLASH_WaitForLastOperation(); if(status == FLASH_COMPLETE) { *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = OB_RDP; } } /** * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. * @param OB_IWDG: Selects the IWDG mode * This parameter can be one of the following values: * @arg OB_IWDG_SW: Software IWDG selected * @arg OB_IWDG_HW: Hardware IWDG selected * @param OB_STOP: Reset event when entering STOP mode. * This parameter can be one of the following values: * @arg OB_STOP_NoRST: No reset generated when entering in STOP * @arg OB_STOP_RST: Reset generated when entering in STOP * @param OB_STDBY: Reset event when entering Standby mode. * This parameter can be one of the following values: * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY * @arg OB_STDBY_RST: Reset generated when entering in STANDBY * @retval None */ void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) { uint8_t optiontmp = 0xFF; FLASH_Status status = FLASH_COMPLETE; /* Check the parameters */ assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); assert_param(IS_OB_STOP_SOURCE(OB_STOP)); assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); if(status == FLASH_COMPLETE) { /* Mask OPTLOCK, OPTSTRT and BOR_LEV bits */ optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0F); /* Update User Option Byte */ *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = OB_IWDG | (uint8_t)(OB_STDBY | (uint8_t)(OB_STOP | ((uint8_t)optiontmp))); } } /** * @brief Sets the BOR Level. * @param OB_BOR: specifies the Option Bytes BOR Reset Level. * This parameter can be one of the following values: * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V * @retval None */ void FLASH_OB_BORConfig(uint8_t OB_BOR) { /* Check the parameters */ assert_param(IS_OB_BOR(OB_BOR)); /* Set the BOR Level */ *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV); *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOR; } /** * @brief Launch the option byte loading. * @param None * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. */ FLASH_Status FLASH_OB_Launch(void) { FLASH_Status status = FLASH_COMPLETE; /* Set the OPTSTRT bit in OPTCR register */ *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); return status; } /** * @brief Returns the FLASH User Option Bytes values. * @param None * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1) * and RST_STDBY(Bit2). */ uint8_t FLASH_OB_GetUser(void) { /* Return the User Option Byte */ return (uint8_t)(FLASH->OPTCR >> 5); } /** * @brief Returns the FLASH Write Protection Option Bytes value. * @param None * @retval The FLASH Write Protection Option Bytes value */ uint16_t FLASH_OB_GetWRP(void) { /* Return the FLASH write protection Register value */ return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); } /** * @brief Returns the FLASH Read Protection level. * @param None * @retval FLASH ReadOut Protection Status: * - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set * - RESET, when OB_RDP_Level_0 is set */ FlagStatus FLASH_OB_GetRDP(void) { FlagStatus readstatus = RESET; if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) != (uint8_t)OB_RDP_Level_0)) { readstatus = SET; } else { readstatus = RESET; } return readstatus; } /** * @brief Returns the FLASH BOR level. * @param None * @retval The FLASH BOR level: * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V */ uint8_t FLASH_OB_GetBOR(void) { /* Return the FLASH BOR level */ return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C); } /** * @} */ /** @defgroup FLASH_Group4 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== Interrupts and flags management functions =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables the specified FLASH interrupts. * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg FLASH_IT_ERR: FLASH Error Interrupt * @arg FLASH_IT_EOP: FLASH end of operation Interrupt * @retval None */ void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FLASH_IT(FLASH_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if(NewState != DISABLE) { /* Enable the interrupt sources */ FLASH->CR |= FLASH_IT; } else { /* Disable the interrupt sources */ FLASH->CR &= ~(uint32_t)FLASH_IT; } } /** * @brief Checks whether the specified FLASH flag is set or not. * @param FLASH_FLAG: specifies the FLASH flag to check. * This parameter can be one of the following values: * @arg FLASH_FLAG_EOP: FLASH End of Operation flag * @arg FLASH_FLAG_OPERR: FLASH operation Error flag * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag * @arg FLASH_FLAG_BSY: FLASH Busy flag * @retval The new state of FLASH_FLAG (SET or RESET). */ FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)); if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } /* Return the new state of FLASH_FLAG (SET or RESET) */ return bitstatus; } /** * @brief Clears the FLASH's pending flags. * @param FLASH_FLAG: specifies the FLASH flags to clear. * This parameter can be any combination of the following values: * @arg FLASH_FLAG_EOP: FLASH End of Operation flag * @arg FLASH_FLAG_OPERR: FLASH operation Error flag * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag * @retval None */ void FLASH_ClearFlag(uint32_t FLASH_FLAG) { /* Check the parameters */ assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)); /* Clear the flags */ FLASH->SR = FLASH_FLAG; } /** * @brief Returns the FLASH Status. * @param None * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. */ FLASH_Status FLASH_GetStatus(void) { FLASH_Status flashstatus = FLASH_COMPLETE; if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) { flashstatus = FLASH_BUSY; } else { if((FLASH->SR & FLASH_FLAG_WRPERR) != (uint32_t)0x00) { flashstatus = FLASH_ERROR_WRP; } else { if((FLASH->SR & (uint32_t)0xEF) != (uint32_t)0x00) { flashstatus = FLASH_ERROR_PROGRAM; } else { if((FLASH->SR & FLASH_FLAG_OPERR) != (uint32_t)0x00) { flashstatus = FLASH_ERROR_OPERATION; } else { flashstatus = FLASH_COMPLETE; } } } } /* Return the FLASH Status */ return flashstatus; } /** * @brief Waits for a FLASH operation to complete. * @param None * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. */ FLASH_Status FLASH_WaitForLastOperation(void) { __IO FLASH_Status status = FLASH_COMPLETE; /* Check for the FLASH Status */ status = FLASH_GetStatus(); /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. Even if the FLASH operation fails, the BUSY flag will be reset and an error flag will be set */ while(status == FLASH_BUSY) { status = FLASH_GetStatus(); } /* Return the operation status */ return status; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c ================================================ /** ****************************************************************************** * @file stm32f4xx_fsmc.c * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file provides firmware functions to manage the following * functionalities of the FSMC peripheral: * - Interface with SRAM, PSRAM, NOR and OneNAND memories * - Interface with NAND memories * - Interface with 16-bit PC Card compatible memories * - Interrupts and flags management * ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_fsmc.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup FSMC * @brief FSMC driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* --------------------- FSMC registers bit mask ---------------------------- */ /* FSMC BCRx Mask */ #define BCR_MBKEN_SET ((uint32_t)0x00000001) #define BCR_MBKEN_RESET ((uint32_t)0x000FFFFE) #define BCR_FACCEN_SET ((uint32_t)0x00000040) /* FSMC PCRx Mask */ #define PCR_PBKEN_SET ((uint32_t)0x00000004) #define PCR_PBKEN_RESET ((uint32_t)0x000FFFFB) #define PCR_ECCEN_SET ((uint32_t)0x00000040) #define PCR_ECCEN_RESET ((uint32_t)0x000FFFBF) #define PCR_MEMORYTYPE_NAND ((uint32_t)0x00000008) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup FSMC_Private_Functions * @{ */ /** @defgroup FSMC_Group1 NOR/SRAM Controller functions * @brief NOR/SRAM Controller functions * @verbatim =============================================================================== NOR/SRAM Controller functions =============================================================================== The following sequence should be followed to configure the FSMC to interface with SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank: 1. Enable the clock for the FSMC and associated GPIOs using the following functions: RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); 2. FSMC pins configuration - Connect the involved FSMC pins to AF12 using the following function GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); - Configure these FSMC pins in alternate function mode by calling the function GPIO_Init(); 3. Declare a FSMC_NORSRAMInitTypeDef structure, for example: FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; and fill the FSMC_NORSRAMInitStructure variable with the allowed values of the structure member. 4. Initialize the NOR/SRAM Controller by calling the function FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); 5. Then enable the NOR/SRAM Bank, for example: FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE); 6. At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank. @endverbatim * @{ */ /** * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default * reset values. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 * @retval None */ void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank) { /* Check the parameter */ assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); /* FSMC_Bank1_NORSRAM1 */ if(FSMC_Bank == FSMC_Bank1_NORSRAM1) { FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; } /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */ else { FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; } FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; } /** * @brief Initializes the FSMC NOR/SRAM Banks according to the specified * parameters in the FSMC_NORSRAMInitStruct. * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef structure * that contains the configuration information for the FSMC NOR/SRAM * specified Banks. * @retval None */ void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) { /* Check the parameters */ assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank)); assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux)); assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType)); assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth)); assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode)); assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait)); assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity)); assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode)); assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive)); assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation)); assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal)); assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode)); assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime)); assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime)); assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime)); assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration)); assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision)); assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency)); assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); /* Bank1 NOR/SRAM control register configuration */ FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | FSMC_NORSRAMInitStruct->FSMC_MemoryType | FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait | FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | FSMC_NORSRAMInitStruct->FSMC_WrapMode | FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | FSMC_NORSRAMInitStruct->FSMC_WriteOperation | FSMC_NORSRAMInitStruct->FSMC_WaitSignal | FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | FSMC_NORSRAMInitStruct->FSMC_WriteBurst; if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) { FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_SET; } /* Bank1 NOR/SRAM timing register configuration */ FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) { assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime)); assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime)); assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime)); assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision)); assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency)); assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode)); FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )| (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) | (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) | FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; } else { FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; } } /** * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef structure * which will be initialized. * @retval None */ void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) { /* Reset NOR/SRAM Init structure parameters values */ FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF; FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF; FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF; FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF; FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF; FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF; FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF; FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF; FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF; FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF; FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; } /** * @brief Enables or disables the specified NOR/SRAM Memory Bank. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. * @retval None */ void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState) { assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_SET; } else { /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_RESET; } } /** * @} */ /** @defgroup FSMC_Group2 NAND Controller functions * @brief NAND Controller functions * @verbatim =============================================================================== NAND Controller functions =============================================================================== The following sequence should be followed to configure the FSMC to interface with 8-bit or 16-bit NAND memory connected to the NAND Bank: 1. Enable the clock for the FSMC and associated GPIOs using the following functions: RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); 2. FSMC pins configuration - Connect the involved FSMC pins to AF12 using the following function GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); - Configure these FSMC pins in alternate function mode by calling the function GPIO_Init(); 3. Declare a FSMC_NANDInitTypeDef structure, for example: FSMC_NANDInitTypeDef FSMC_NANDInitStructure; and fill the FSMC_NANDInitStructure variable with the allowed values of the structure member. 4. Initialize the NAND Controller by calling the function FSMC_NANDInit(&FSMC_NANDInitStructure); 5. Then enable the NAND Bank, for example: FSMC_NANDCmd(FSMC_Bank3_NAND, ENABLE); 6. At this stage you can read/write from/to the memory connected to the NAND Bank. @note To enable the Error Correction Code (ECC), you have to use the function FSMC_NANDECCCmd(FSMC_Bank3_NAND, ENABLE); and to get the current ECC value you have to use the function ECCval = FSMC_GetECC(FSMC_Bank3_NAND); @endverbatim * @{ */ /** * @brief Deinitializes the FSMC NAND Banks registers to their default reset values. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND * @retval None */ void FSMC_NANDDeInit(uint32_t FSMC_Bank) { /* Check the parameter */ assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); if(FSMC_Bank == FSMC_Bank2_NAND) { /* Set the FSMC_Bank2 registers to their reset values */ FSMC_Bank2->PCR2 = 0x00000018; FSMC_Bank2->SR2 = 0x00000040; FSMC_Bank2->PMEM2 = 0xFCFCFCFC; FSMC_Bank2->PATT2 = 0xFCFCFCFC; } /* FSMC_Bank3_NAND */ else { /* Set the FSMC_Bank3 registers to their reset values */ FSMC_Bank3->PCR3 = 0x00000018; FSMC_Bank3->SR3 = 0x00000040; FSMC_Bank3->PMEM3 = 0xFCFCFCFC; FSMC_Bank3->PATT3 = 0xFCFCFCFC; } } /** * @brief Initializes the FSMC NAND Banks according to the specified parameters * in the FSMC_NANDInitStruct. * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef structure that * contains the configuration information for the FSMC NAND specified Banks. * @retval None */ void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) { uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; /* Check the parameters */ assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank)); assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature)); assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth)); assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC)); assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize)); assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime)); assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime)); assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */ tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | PCR_MEMORYTYPE_NAND | FSMC_NANDInitStruct->FSMC_MemoryDataWidth | FSMC_NANDInitStruct->FSMC_ECC | FSMC_NANDInitStruct->FSMC_ECCPageSize | (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )| (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */ tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */ tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) { /* FSMC_Bank2_NAND registers configuration */ FSMC_Bank2->PCR2 = tmppcr; FSMC_Bank2->PMEM2 = tmppmem; FSMC_Bank2->PATT2 = tmppatt; } else { /* FSMC_Bank3_NAND registers configuration */ FSMC_Bank3->PCR3 = tmppcr; FSMC_Bank3->PMEM3 = tmppmem; FSMC_Bank3->PATT3 = tmppatt; } } /** * @brief Fills each FSMC_NANDInitStruct member with its default value. * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef structure which * will be initialized. * @retval None */ void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) { /* Reset NAND Init structure parameters values */ FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; } /** * @brief Enables or disables the specified NAND Memory Bank. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. * @retval None */ void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState) { assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ if(FSMC_Bank == FSMC_Bank2_NAND) { FSMC_Bank2->PCR2 |= PCR_PBKEN_SET; } else { FSMC_Bank3->PCR3 |= PCR_PBKEN_SET; } } else { /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ if(FSMC_Bank == FSMC_Bank2_NAND) { FSMC_Bank2->PCR2 &= PCR_PBKEN_RESET; } else { FSMC_Bank3->PCR3 &= PCR_PBKEN_RESET; } } } /** * @brief Enables or disables the FSMC NAND ECC feature. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND * @param NewState: new state of the FSMC NAND ECC feature. * This parameter can be: ENABLE or DISABLE. * @retval None */ void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState) { assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ if(FSMC_Bank == FSMC_Bank2_NAND) { FSMC_Bank2->PCR2 |= PCR_ECCEN_SET; } else { FSMC_Bank3->PCR3 |= PCR_ECCEN_SET; } } else { /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ if(FSMC_Bank == FSMC_Bank2_NAND) { FSMC_Bank2->PCR2 &= PCR_ECCEN_RESET; } else { FSMC_Bank3->PCR3 &= PCR_ECCEN_RESET; } } } /** * @brief Returns the error correction code register value. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND * @retval The Error Correction Code (ECC) value. */ uint32_t FSMC_GetECC(uint32_t FSMC_Bank) { uint32_t eccval = 0x00000000; if(FSMC_Bank == FSMC_Bank2_NAND) { /* Get the ECCR2 register value */ eccval = FSMC_Bank2->ECCR2; } else { /* Get the ECCR3 register value */ eccval = FSMC_Bank3->ECCR3; } /* Return the error correction code value */ return(eccval); } /** * @} */ /** @defgroup FSMC_Group3 PCCARD Controller functions * @brief PCCARD Controller functions * @verbatim =============================================================================== PCCARD Controller functions =============================================================================== The following sequence should be followed to configure the FSMC to interface with 16-bit PC Card compatible memory connected to the PCCARD Bank: 1. Enable the clock for the FSMC and associated GPIOs using the following functions: RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); 2. FSMC pins configuration - Connect the involved FSMC pins to AF12 using the following function GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); - Configure these FSMC pins in alternate function mode by calling the function GPIO_Init(); 3. Declare a FSMC_PCCARDInitTypeDef structure, for example: FSMC_PCCARDInitTypeDef FSMC_PCCARDInitStructure; and fill the FSMC_PCCARDInitStructure variable with the allowed values of the structure member. 4. Initialize the PCCARD Controller by calling the function FSMC_PCCARDInit(&FSMC_PCCARDInitStructure); 5. Then enable the PCCARD Bank: FSMC_PCCARDCmd(ENABLE); 6. At this stage you can read/write from/to the memory connected to the PCCARD Bank. @endverbatim * @{ */ /** * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values. * @param None * @retval None */ void FSMC_PCCARDDeInit(void) { /* Set the FSMC_Bank4 registers to their reset values */ FSMC_Bank4->PCR4 = 0x00000018; FSMC_Bank4->SR4 = 0x00000000; FSMC_Bank4->PMEM4 = 0xFCFCFCFC; FSMC_Bank4->PATT4 = 0xFCFCFCFC; FSMC_Bank4->PIO4 = 0xFCFCFCFC; } /** * @brief Initializes the FSMC PCCARD Bank according to the specified parameters * in the FSMC_PCCARDInitStruct. * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef structure * that contains the configuration information for the FSMC PCCARD Bank. * @retval None */ void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) { /* Check the parameters */ assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature)); assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime)); assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime)); assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime)); assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime)); assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime)); assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime)); /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */ FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature | FSMC_MemoryDataWidth_16b | (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) | (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13); /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */ FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */ FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */ FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime | (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) | (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)| (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); } /** * @brief Fills each FSMC_PCCARDInitStruct member with its default value. * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef structure * which will be initialized. * @retval None */ void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) { /* Reset PCCARD Init structure parameters values */ FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0; FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0; FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; } /** * @brief Enables or disables the PCCARD Memory Bank. * @param NewState: new state of the PCCARD Memory Bank. * This parameter can be: ENABLE or DISABLE. * @retval None */ void FSMC_PCCARDCmd(FunctionalState NewState) { assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ FSMC_Bank4->PCR4 |= PCR_PBKEN_SET; } else { /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ FSMC_Bank4->PCR4 &= PCR_PBKEN_RESET; } } /** * @} */ /** @defgroup FSMC_Group4 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== Interrupts and flags management functions =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables the specified FSMC interrupts. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. * @arg FSMC_IT_Level: Level edge detection interrupt. * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. * @param NewState: new state of the specified FSMC interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState) { assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); assert_param(IS_FSMC_IT(FSMC_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected FSMC_Bank2 interrupts */ if(FSMC_Bank == FSMC_Bank2_NAND) { FSMC_Bank2->SR2 |= FSMC_IT; } /* Enable the selected FSMC_Bank3 interrupts */ else if (FSMC_Bank == FSMC_Bank3_NAND) { FSMC_Bank3->SR3 |= FSMC_IT; } /* Enable the selected FSMC_Bank4 interrupts */ else { FSMC_Bank4->SR4 |= FSMC_IT; } } else { /* Disable the selected FSMC_Bank2 interrupts */ if(FSMC_Bank == FSMC_Bank2_NAND) { FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT; } /* Disable the selected FSMC_Bank3 interrupts */ else if (FSMC_Bank == FSMC_Bank3_NAND) { FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT; } /* Disable the selected FSMC_Bank4 interrupts */ else { FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; } } } /** * @brief Checks whether the specified FSMC flag is set or not. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD * @param FSMC_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag. * @arg FSMC_FLAG_Level: Level detection Flag. * @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag. * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. * @retval The new state of FSMC_FLAG (SET or RESET). */ FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) { FlagStatus bitstatus = RESET; uint32_t tmpsr = 0x00000000; /* Check the parameters */ assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG)); if(FSMC_Bank == FSMC_Bank2_NAND) { tmpsr = FSMC_Bank2->SR2; } else if(FSMC_Bank == FSMC_Bank3_NAND) { tmpsr = FSMC_Bank3->SR3; } /* FSMC_Bank4_PCCARD*/ else { tmpsr = FSMC_Bank4->SR4; } /* Get the flag status */ if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET ) { bitstatus = SET; } else { bitstatus = RESET; } /* Return the flag status */ return bitstatus; } /** * @brief Clears the FSMC's pending flags. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD * @param FSMC_FLAG: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag. * @arg FSMC_FLAG_Level: Level detection Flag. * @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag. * @retval None */ void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) { /* Check the parameters */ assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ; if(FSMC_Bank == FSMC_Bank2_NAND) { FSMC_Bank2->SR2 &= ~FSMC_FLAG; } else if(FSMC_Bank == FSMC_Bank3_NAND) { FSMC_Bank3->SR3 &= ~FSMC_FLAG; } /* FSMC_Bank4_PCCARD*/ else { FSMC_Bank4->SR4 &= ~FSMC_FLAG; } } /** * @brief Checks whether the specified FSMC interrupt has occurred or not. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD * @param FSMC_IT: specifies the FSMC interrupt source to check. * This parameter can be one of the following values: * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. * @arg FSMC_IT_Level: Level edge detection interrupt. * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. * @retval The new state of FSMC_IT (SET or RESET). */ ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) { ITStatus bitstatus = RESET; uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; /* Check the parameters */ assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); assert_param(IS_FSMC_GET_IT(FSMC_IT)); if(FSMC_Bank == FSMC_Bank2_NAND) { tmpsr = FSMC_Bank2->SR2; } else if(FSMC_Bank == FSMC_Bank3_NAND) { tmpsr = FSMC_Bank3->SR3; } /* FSMC_Bank4_PCCARD*/ else { tmpsr = FSMC_Bank4->SR4; } itstatus = tmpsr & FSMC_IT; itenable = tmpsr & (FSMC_IT >> 3); if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears the FSMC's interrupt pending bits. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD * @param FSMC_IT: specifies the interrupt pending bit to clear. * This parameter can be any combination of the following values: * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. * @arg FSMC_IT_Level: Level edge detection interrupt. * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. * @retval None */ void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) { /* Check the parameters */ assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); assert_param(IS_FSMC_IT(FSMC_IT)); if(FSMC_Bank == FSMC_Bank2_NAND) { FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); } else if(FSMC_Bank == FSMC_Bank3_NAND) { FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3); } /* FSMC_Bank4_PCCARD*/ else { FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3); } } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_gpio.c ================================================ /** ****************************************************************************** * @file stm32f4xx_gpio.c * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file provides firmware functions to manage the following * functionalities of the GPIO peripheral: * - Initialization and Configuration * - GPIO Read and Write * - GPIO Alternate functions configuration * * @verbatim * * =================================================================== * How to use this driver * =================================================================== * 1. Enable the GPIO AHB clock using the following function * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); * * 2. Configure the GPIO pin(s) using GPIO_Init() * Four possible configuration are available for each pin: * - Input: Floating, Pull-up, Pull-down. * - Output: Push-Pull (Pull-up, Pull-down or no Pull) * Open Drain (Pull-up, Pull-down or no Pull). * In output mode, the speed is configurable: 2 MHz, 25 MHz, * 50 MHz or 100 MHz. * - Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull) * Open Drain (Pull-up, Pull-down or no Pull). * - Analog: required mode when a pin is to be used as ADC channel * or DAC output. * * 3- Peripherals alternate function: * - For ADC and DAC, configure the desired pin in analog mode using * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN; * - For other peripherals (TIM, USART...): * - Connect the pin to the desired peripherals' Alternate * Function (AF) using GPIO_PinAFConfig() function * - Configure the desired pin in alternate function mode using * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF * - Select the type, pull-up/pull-down and output speed via * GPIO_PuPd, GPIO_OType and GPIO_Speed members * - Call GPIO_Init() function * * 4. To get the level of a pin configured in input mode use GPIO_ReadInputDataBit() * * 5. To set/reset the level of a pin configured in output mode use * GPIO_SetBits()/GPIO_ResetBits() * * 6. During and just after reset, the alternate functions are not * active and the GPIO pins are configured in input floating mode * (except JTAG pins). * * 7. The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as * general-purpose (PC14 and PC15, respectively) when the LSE * oscillator is off. The LSE has priority over the GPIO function. * * 8. The HSE oscillator pins OSC_IN/OSC_OUT can be used as * general-purpose PH0 and PH1, respectively, when the HSE * oscillator is off. The HSE has priority over the GPIO function. * * @endverbatim * ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_gpio.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup GPIO * @brief GPIO driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup GPIO_Private_Functions * @{ */ /** @defgroup GPIO_Group1 Initialization and Configuration * @brief Initialization and Configuration * @verbatim =============================================================================== Initialization and Configuration =============================================================================== @endverbatim * @{ */ /** * @brief Deinitializes the GPIOx peripheral registers to their default reset values. * @note By default, The GPIO pins are configured in input floating mode (except JTAG pins). * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. * @retval None */ void GPIO_DeInit(GPIO_TypeDef* GPIOx) { /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); if (GPIOx == GPIOA) { RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE); RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE); } else if (GPIOx == GPIOB) { RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE); RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE); } else if (GPIOx == GPIOC) { RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE); RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE); } else if (GPIOx == GPIOD) { RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE); RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE); } else if (GPIOx == GPIOE) { RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE); RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE); } else if (GPIOx == GPIOF) { RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE); RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE); } else if (GPIOx == GPIOG) { RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE); RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE); } else if (GPIOx == GPIOH) { RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE); RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE); } else { if (GPIOx == GPIOI) { RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE); RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE); } } } /** * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct. * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) { uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00; /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd)); /* -------------------------Configure the port pins---------------- */ /*-- GPIO Mode Configuration --*/ for (pinpos = 0x00; pinpos < 0x10; pinpos++) { pos = ((uint32_t)0x01) << pinpos; /* Get the port pins position */ currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; if (currentpin == pos) { GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2)); GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2)); if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF)) { /* Check Speed mode parameters */ assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); /* Speed mode configuration */ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2)); GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2)); /* Check Output mode parameters */ assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType)); /* Output mode configuration*/ GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ; GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos)); } /* Pull-up Pull down resistor configuration*/ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2)); GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2)); } } } /** * @brief Fills each GPIO_InitStruct member with its default value. * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized. * @retval None */ void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) { /* Reset GPIO init structure parameters values */ GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN; GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; GPIO_InitStruct->GPIO_OType = GPIO_OType_PP; GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL; } /** * @brief Locks GPIO Pins configuration registers. * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. * @note The configuration of the locked GPIO pins can no longer be modified * until the next reset. * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. * @param GPIO_Pin: specifies the port bit to be locked. * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @retval None */ void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { __IO uint32_t tmp = 0x00010000; /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Pin)); tmp |= GPIO_Pin; /* Set LCKK bit */ GPIOx->LCKR = tmp; /* Reset LCKK bit */ GPIOx->LCKR = GPIO_Pin; /* Set LCKK bit */ GPIOx->LCKR = tmp; /* Read LCKK bit*/ tmp = GPIOx->LCKR; /* Read LCKK bit*/ tmp = GPIOx->LCKR; } /** * @} */ /** @defgroup GPIO_Group2 GPIO Read and Write * @brief GPIO Read and Write * @verbatim =============================================================================== GPIO Read and Write =============================================================================== @endverbatim * @{ */ /** * @brief Reads the specified input port pin. * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_Pin_x where x can be (0..15). * @retval The input port pin value. */ uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { //uint8_t bitstatus = 0x00; /* Check the parameters */ //assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); //assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); //if ( return (GPIOx->IDR & GPIO_Pin) ? 0x01 : 0x00; // { // return (uint8_t)Bit_SET; // } //else //{ // return (uint8_t)Bit_RESET; //} //return bitstatus; } /** * @brief Reads the specified GPIO input data port. * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. * @retval GPIO input data port value. */ uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) { /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); return ((uint16_t)GPIOx->IDR); } /** * @brief Reads the specified output data port bit. * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_Pin_x where x can be (0..15). * @retval The output port pin value. */ uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { uint8_t bitstatus = 0x00; /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) { bitstatus = (uint8_t)Bit_SET; } else { bitstatus = (uint8_t)Bit_RESET; } return bitstatus; } /** * @brief Reads the specified GPIO output data port. * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. * @retval GPIO output data port value. */ uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) { /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); return ((uint16_t)GPIOx->ODR); } /** * @brief Sets the selected data port bits. * @note This functions uses GPIOx_BSRR register to allow atomic read/modify * accesses. In this way, there is no risk of an IRQ occurring between * the read and the modify access. * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. * @param GPIO_Pin: specifies the port bits to be written. * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @retval None */ void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { /* Check the parameters */ //assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); //assert_param(IS_GPIO_PIN(GPIO_Pin)); GPIOx->BSRRL = GPIO_Pin; } /** * @brief Clears the selected data port bits. * @note This functions uses GPIOx_BSRR register to allow atomic read/modify * accesses. In this way, there is no risk of an IRQ occurring between * the read and the modify access. * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. * @param GPIO_Pin: specifies the port bits to be written. * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @retval None */ void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { /* Check the parameters */ //assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); //assert_param(IS_GPIO_PIN(GPIO_Pin)); GPIOx->BSRRH = GPIO_Pin; } /** * @brief Sets or clears the selected data port bit. * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. * @param GPIO_Pin: specifies the port bit to be written. * This parameter can be one of GPIO_Pin_x where x can be (0..15). * @param BitVal: specifies the value to be written to the selected bit. * This parameter can be one of the BitAction enum values: * @arg Bit_RESET: to clear the port pin * @arg Bit_SET: to set the port pin * @retval None */ void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) { /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_BIT_ACTION(BitVal)); if (BitVal != Bit_RESET) { GPIOx->BSRRL = GPIO_Pin; } else { GPIOx->BSRRH = GPIO_Pin ; } } /** * @brief Writes data to the specified GPIO data port. * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. * @param PortVal: specifies the value to be written to the port output data register. * @retval None */ void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) { /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); GPIOx->ODR = PortVal; } /** * @brief Toggles the specified GPIO pins.. * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. * @param GPIO_Pin: Specifies the pins to be toggled. * @retval None */ void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); GPIOx->ODR ^= GPIO_Pin; } /** * @} */ /** @defgroup GPIO_Group3 GPIO Alternate functions configuration function * @brief GPIO Alternate functions configuration function * @verbatim =============================================================================== GPIO Alternate functions configuration function =============================================================================== @endverbatim * @{ */ /** * @brief Changes the mapping of the specified pin. * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. * @param GPIO_PinSource: specifies the pin for the Alternate function. * This parameter can be GPIO_PinSourcex where x can be (0..15). * @param GPIO_AFSelection: selects the pin to used as Alternate function. * This parameter can be one of the following values: * @arg GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset) * @arg GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset) * @arg GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset) * @arg GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset) * @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset) * @arg GPIO_AF_TIM1: Connect TIM1 pins to AF1 * @arg GPIO_AF_TIM2: Connect TIM2 pins to AF1 * @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2 * @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2 * @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2 * @arg GPIO_AF_TIM8: Connect TIM8 pins to AF3 * @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3 * @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3 * @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3 * @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4 * @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4 * @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4 * @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5 * @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5 * @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6 * @arg GPIO_AF_I2S3ext: Connect I2S3ext pins to AF7 * @arg GPIO_AF_USART1: Connect USART1 pins to AF7 * @arg GPIO_AF_USART2: Connect USART2 pins to AF7 * @arg GPIO_AF_USART3: Connect USART3 pins to AF7 * @arg GPIO_AF_UART4: Connect UART4 pins to AF8 * @arg GPIO_AF_UART5: Connect UART5 pins to AF8 * @arg GPIO_AF_USART6: Connect USART6 pins to AF8 * @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9 * @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9 * @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9 * @arg GPIO_AF_TIM13: Connect TIM13 pins to AF9 * @arg GPIO_AF_TIM14: Connect TIM14 pins to AF9 * @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10 * @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10 * @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11 * @arg GPIO_AF_FSMC: Connect FSMC pins to AF12 * @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12 * @arg GPIO_AF_SDIO: Connect SDIO pins to AF12 * @arg GPIO_AF_DCMI: Connect DCMI pins to AF13 * @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15 * @retval None */ void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF) { uint32_t temp = 0x00; uint32_t temp_2 = 0x00; /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); assert_param(IS_GPIO_AF(GPIO_AF)); temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp; GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c ================================================ /** ****************************************************************************** * @file stm32f4xx_hash.c * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file provides firmware functions to manage the following * functionalities of the HASH / HMAC Processor (HASH) peripheral: * - Initialization and Configuration functions * - Message Digest generation functions * - context swapping functions * - DMA interface function * - Interrupts and flags management * * @verbatim * * =================================================================== * How to use this driver * =================================================================== * HASH operation : * ---------------- * 1. Enable the HASH controller clock using * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE) function. * * 2. Initialise the HASH using HASH_Init() function. * * 3 . Reset the HASH processor core, so that the HASH will be ready * to compute he message digest of a new message by using * HASH_Reset() function. * * 4. Enable the HASH controller using the HASH_Cmd() function. * * 5. if using DMA for Data input transfer, Activate the DMA Request * using HASH_DMACmd() function * * 6. if DMA is not used for data transfer, use HASH_DataIn() function * to enter data to IN FIFO. * * * 7. Configure the Number of valid bits in last word of the message * using HASH_SetLastWordValidBitsNbr() function. * * 8. if the message length is not an exact multiple of 512 bits, * then the function HASH_StartDigest() must be called to * launch the computation of the final digest. * * 9. Once computed, the digest can be read using HASH_GetDigest() * function. * * 10. To control HASH events you can use one of the following * two methods: * a- Check on HASH flags using the HASH_GetFlagStatus() function. * b- Use HASH interrupts through the function HASH_ITConfig() at * initialization phase and HASH_GetITStatus() function into * interrupt routines in hashing phase. * After checking on a flag you should clear it using HASH_ClearFlag() * function. And after checking on an interrupt event you should * clear it using HASH_ClearITPendingBit() function. * * 11. Save and restore hash processor context using * HASH_SaveContext() and HASH_RestoreContext() functions. * * * * HMAC operation : * ---------------- * The HMAC algorithm is used for message authentication, by * irreversibly binding the message being processed to a key chosen * by the user. * For HMAC specifications, refer to "HMAC: keyed-hashing for message * authentication, H. Krawczyk, M. Bellare, R. Canetti, February 1997" * * Basically, the HMAC algorithm consists of two nested hash operations: * HMAC(message) = Hash[((key | pad) XOR 0x5C) | Hash(((key | pad) XOR 0x36) | message)] * where: * - "pad" is a sequence of zeroes needed to extend the key to the * length of the underlying hash function data block (that is * 512 bits for both the SHA-1 and MD5 hash algorithms) * - "|" represents the concatenation operator * * * To compute the HMAC, four different phases are required: * * 1. Initialise the HASH using HASH_Init() function to do HMAC * operation. * * 2. The key (to be used for the inner hash function) is then given * to the core. This operation follows the same mechanism as the * one used to send the message in the hash operation (that is, * by HASH_DataIn() function and, finally, * HASH_StartDigest() function. * * 3. Once the last word has been entered and computation has started, * the hash processor elaborates the key. It is then ready to * accept the message text using the same mechanism as the one * used to send the message in the hash operation. * * 4. After the first hash round, the hash processor returns "ready" * to indicate that it is ready to receive the key to be used for * the outer hash function (normally, this key is the same as the * one used for the inner hash function). When the last word of * the key is entered and computation starts, the HMAC result is * made available using HASH_GetDigest() function. * * * @endverbatim * ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hash.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup HASH * @brief HASH driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup HASH_Private_Functions * @{ */ /** @defgroup HASH_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== Initialization and Configuration functions =============================================================================== This section provides functions allowing to - Initialize the HASH peripheral - Configure the HASH Processor - MD5/SHA1, - HASH/HMAC, - datatype - HMAC Key (if mode = HMAC) - Reset the HASH Processor @endverbatim * @{ */ /** * @brief Deinitializes the HASH peripheral registers to their default reset values * @param None * @retval None */ void HASH_DeInit(void) { /* Enable HASH reset state */ RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, ENABLE); /* Release HASH from reset state */ RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, DISABLE); } /** * @brief Initializes the HASH peripheral according to the specified parameters * in the HASH_InitStruct structure. * @note the hash processor is reset when calling this function so that the * HASH will be ready to compute the message digest of a new message. * There is no need to call HASH_Reset() function. * @param HASH_InitStruct: pointer to a HASH_InitTypeDef structure that contains * the configuration information for the HASH peripheral. * @note The field HASH_HMACKeyType in HASH_InitTypeDef must be filled only * if the algorithm mode is HMAC. * @retval None */ void HASH_Init(HASH_InitTypeDef* HASH_InitStruct) { /* Check the parameters */ assert_param(IS_HASH_ALGOSELECTION(HASH_InitStruct->HASH_AlgoSelection)); assert_param(IS_HASH_DATATYPE(HASH_InitStruct->HASH_DataType)); assert_param(IS_HASH_ALGOMODE(HASH_InitStruct->HASH_AlgoMode)); /* Configure the Algorithm used, algorithm mode and the datatype */ HASH->CR &= ~ (HASH_CR_ALGO | HASH_CR_DATATYPE | HASH_CR_MODE); HASH->CR |= (HASH_InitStruct->HASH_AlgoSelection | \ HASH_InitStruct->HASH_DataType | \ HASH_InitStruct->HASH_AlgoMode); /* if algorithm mode is HMAC, set the Key */ if(HASH_InitStruct->HASH_AlgoMode == HASH_AlgoMode_HMAC) { assert_param(IS_HASH_HMAC_KEYTYPE(HASH_InitStruct->HASH_HMACKeyType)); HASH->CR &= ~HASH_CR_LKEY; HASH->CR |= HASH_InitStruct->HASH_HMACKeyType; } /* Reset the HASH processor core, so that the HASH will be ready to compute the message digest of a new message */ HASH->CR |= HASH_CR_INIT; } /** * @brief Fills each HASH_InitStruct member with its default value. * @param HASH_InitStruct : pointer to a HASH_InitTypeDef structure which will * be initialized. * @note The default values set are : Processor mode is HASH, Algorithm selected is SHA1, * Data type selected is 32b and HMAC Key Type is short key. * @retval None */ void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct) { /* Initialize the HASH_AlgoSelection member */ HASH_InitStruct->HASH_AlgoSelection = HASH_AlgoSelection_SHA1; /* Initialize the HASH_AlgoMode member */ HASH_InitStruct->HASH_AlgoMode = HASH_AlgoMode_HASH; /* Initialize the HASH_DataType member */ HASH_InitStruct->HASH_DataType = HASH_DataType_32b; /* Initialize the HASH_HMACKeyType member */ HASH_InitStruct->HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; } /** * @brief Resets the HASH processor core, so that the HASH will be ready * to compute the message digest of a new message. * @note Calling this function will clear the HASH_SR_DCIS (Digest calculation * completion interrupt status) bit corresponding to HASH_IT_DCI * interrupt and HASH_FLAG_DCIS flag. * @param None * @retval None */ void HASH_Reset(void) { /* Reset the HASH processor core */ HASH->CR |= HASH_CR_INIT; } /** * @} */ /** @defgroup HASH_Group2 Message Digest generation functions * @brief Message Digest generation functions * @verbatim =============================================================================== Message Digest generation functions =============================================================================== This section provides functions allowing the generation of message digest: - Push data in the IN FIFO : using HASH_DataIn() - Get the number of words set in IN FIFO, use HASH_GetInFIFOWordsNbr() - set the last word valid bits number using HASH_SetLastWordValidBitsNbr() - start digest calculation : using HASH_StartDigest() - Get the Digest message : using HASH_GetDigest() @endverbatim * @{ */ /** * @brief Configure the Number of valid bits in last word of the message * @param ValidNumber: Number of valid bits in last word of the message. * This parameter must be a number between 0 and 0x1F. * - 0x00: All 32 bits of the last data written are valid * - 0x01: Only bit [0] of the last data written is valid * - 0x02: Only bits[1:0] of the last data written are valid * - 0x03: Only bits[2:0] of the last data written are valid * - ... * - 0x1F: Only bits[30:0] of the last data written are valid * @note The Number of valid bits must be set before to start the message * digest competition (in Hash and HMAC) and key treatment(in HMAC). * @retval None */ void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber) { /* Check the parameters */ assert_param(IS_HASH_VALIDBITSNUMBER(ValidNumber)); /* Configure the Number of valid bits in last word of the message */ HASH->STR &= ~(HASH_STR_NBW); HASH->STR |= ValidNumber; } /** * @brief Writes data in the Data Input FIFO * @param Data: new data of the message to be processed. * @retval None */ void HASH_DataIn(uint32_t Data) { /* Write in the DIN register a new data */ HASH->DIN = Data; } /** * @brief Returns the number of words already pushed into the IN FIFO. * @param None * @retval The value of words already pushed into the IN FIFO. */ uint8_t HASH_GetInFIFOWordsNbr(void) { /* Return the value of NBW bits */ return ((HASH->CR & HASH_CR_NBW) >> 8); } /** * @brief Provides the message digest result. * @note In MD5 mode, Data[4] filed of HASH_MsgDigest structure is not used * and is read as zero. * @param HASH_MessageDigest: pointer to a HASH_MsgDigest structure which will * hold the message digest result * @retval None */ void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest) { /* Get the data field */ HASH_MessageDigest->Data[0] = HASH->HR[0]; HASH_MessageDigest->Data[1] = HASH->HR[1]; HASH_MessageDigest->Data[2] = HASH->HR[2]; HASH_MessageDigest->Data[3] = HASH->HR[3]; HASH_MessageDigest->Data[4] = HASH->HR[4]; } /** * @brief Starts the message padding and calculation of the final message * @param None * @retval None */ void HASH_StartDigest(void) { /* Start the Digest calculation */ HASH->STR |= HASH_STR_DCAL; } /** * @} */ /** @defgroup HASH_Group3 Context swapping functions * @brief Context swapping functions * @verbatim =============================================================================== Context swapping functions =============================================================================== This section provides functions allowing to save and store HASH Context It is possible to interrupt a HASH/HMAC process to perform another processing with a higher priority, and to complete the interrupted process later on, when the higher priority task is complete. To do so, the context of the interrupted task must be saved from the HASH registers to memory, and then be restored from memory to the HASH registers. 1. To save the current context, use HASH_SaveContext() function 2. To restore the saved context, use HASH_RestoreContext() function @endverbatim * @{ */ /** * @brief Save the Hash peripheral Context. * @note The context can be saved only when no block is currently being * processed. So user must wait for DINIS = 1 (the last block has been * processed and the input FIFO is empty) or NBW != 0 (the FIFO is not * full and no processing is ongoing). * @param HASH_ContextSave: pointer to a HASH_Context structure that contains * the repository for current context. * @retval None */ void HASH_SaveContext(HASH_Context* HASH_ContextSave) { uint8_t i = 0; /* save context registers */ HASH_ContextSave->HASH_IMR = HASH->IMR; HASH_ContextSave->HASH_STR = HASH->STR; HASH_ContextSave->HASH_CR = HASH->CR; for(i=0; i<=50;i++) { HASH_ContextSave->HASH_CSR[i] = HASH->CSR[i]; } } /** * @brief Restore the Hash peripheral Context. * @note After calling this function, user can restart the processing from the * point where it has been interrupted. * @param HASH_ContextRestore: pointer to a HASH_Context structure that contains * the repository for saved context. * @retval None */ void HASH_RestoreContext(HASH_Context* HASH_ContextRestore) { uint8_t i = 0; /* restore context registers */ HASH->IMR = HASH_ContextRestore->HASH_IMR; HASH->STR = HASH_ContextRestore->HASH_STR; HASH->CR = HASH_ContextRestore->HASH_CR; /* Initialize the hash processor */ HASH->CR |= HASH_CR_INIT; /* continue restoring context registers */ for(i=0; i<=50;i++) { HASH->CSR[i] = HASH_ContextRestore->HASH_CSR[i]; } } /** * @} */ /** @defgroup HASH_Group4 HASH's DMA interface Configuration function * @brief HASH's DMA interface Configuration function * @verbatim =============================================================================== HASH's DMA interface Configuration function =============================================================================== This section provides functions allowing to configure the DMA interface for HASH/ HMAC data input transfer. When the DMA mode is enabled (using the HASH_DMACmd() function), data can be sent to the IN FIFO using the DMA peripheral. @endverbatim * @{ */ /** * @brief Enables or disables the HASH DMA interface. * @note The DMA is disabled by hardware after the end of transfer. * @param NewState: new state of the selected HASH DMA transfer request. * This parameter can be: ENABLE or DISABLE. * @retval None */ void HASH_DMACmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the HASH DMA request */ HASH->CR |= HASH_CR_DMAE; } else { /* Disable the HASH DMA request */ HASH->CR &= ~HASH_CR_DMAE; } } /** * @} */ /** @defgroup HASH_Group5 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== Interrupts and flags management functions =============================================================================== This section provides functions allowing to configure the HASH Interrupts and to get the status and clear flags and Interrupts pending bits. The HASH provides 2 Interrupts sources and 5 Flags: Flags : ---------- 1. HASH_FLAG_DINIS : set when 16 locations are free in the Data IN FIFO which means that a new block (512 bit) can be entered into the input buffer. 2. HASH_FLAG_DCIS : set when Digest calculation is complete 3. HASH_FLAG_DMAS : set when HASH's DMA interface is enabled (DMAE=1) or a transfer is ongoing. This Flag is cleared only by hardware. 4. HASH_FLAG_BUSY : set when The hash core is processing a block of data This Flag is cleared only by hardware. 5. HASH_FLAG_DINNE : set when Data IN FIFO is not empty which means that the Data IN FIFO contains at least one word of data. This Flag is cleared only by hardware. Interrupts : ------------ 1. HASH_IT_DINI : if enabled, this interrupt source is pending when 16 locations are free in the Data IN FIFO which means that a new block (512 bit) can be entered into the input buffer. This interrupt source is cleared using HASH_ClearITPendingBit(HASH_IT_DINI) function. 2. HASH_IT_DCI : if enabled, this interrupt source is pending when Digest calculation is complete. This interrupt source is cleared using HASH_ClearITPendingBit(HASH_IT_DCI) function. Managing the HASH controller events : ------------------------------------ The user should identify which mode will be used in his application to manage the HASH controller events: Polling mode or Interrupt mode. 1. In the Polling Mode it is advised to use the following functions: - HASH_GetFlagStatus() : to check if flags events occur. - HASH_ClearFlag() : to clear the flags events. 2. In the Interrupt Mode it is advised to use the following functions: - HASH_ITConfig() : to enable or disable the interrupt source. - HASH_GetITStatus() : to check if Interrupt occurs. - HASH_ClearITPendingBit() : to clear the Interrupt pending Bit (corresponding Flag). @endverbatim * @{ */ /** * @brief Enables or disables the specified HASH interrupts. * @param HASH_IT: specifies the HASH interrupt source to be enabled or disabled. * This parameter can be any combination of the following values: * @arg HASH_IT_DINI: Data Input interrupt * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt * @param NewState: new state of the specified HASH interrupt. * This parameter can be: ENABLE or DISABLE. * @retval None */ void HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_HASH_IT(HASH_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected HASH interrupt */ HASH->IMR |= HASH_IT; } else { /* Disable the selected HASH interrupt */ HASH->IMR &= (uint8_t) ~HASH_IT; } } /** * @brief Checks whether the specified HASH flag is set or not. * @param HASH_FLAG: specifies the HASH flag to check. * This parameter can be one of the following values: * @arg HASH_FLAG_DINIS: Data input interrupt status flag * @arg HASH_FLAG_DCIS: Digest calculation completion interrupt status flag * @arg HASH_FLAG_BUSY: Busy flag * @arg HASH_FLAG_DMAS: DMAS Status flag * @arg HASH_FLAG_DINNE: Data Input register (DIN) not empty status flag * @retval The new state of HASH_FLAG (SET or RESET) */ FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG) { FlagStatus bitstatus = RESET; uint32_t tempreg = 0; /* Check the parameters */ assert_param(IS_HASH_GET_FLAG(HASH_FLAG)); /* check if the FLAG is in CR register */ if ((HASH_FLAG & HASH_FLAG_DINNE) != (uint16_t)RESET ) { tempreg = HASH->CR; } else /* The FLAG is in SR register */ { tempreg = HASH->SR; } /* Check the status of the specified HASH flag */ if ((tempreg & HASH_FLAG) != (uint16_t)RESET) { /* HASH is set */ bitstatus = SET; } else { /* HASH_FLAG is reset */ bitstatus = RESET; } /* Return the HASH_FLAG status */ return bitstatus; } /** * @brief Clears the HASH flags. * @param HASH_FLAG: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg HASH_FLAG_DINIS: Data Input Flag * @arg HASH_FLAG_DCIS: Digest Calculation Completion Flag * @retval None */ void HASH_ClearFlag(uint16_t HASH_FLAG) { /* Check the parameters */ assert_param(IS_HASH_CLEAR_FLAG(HASH_FLAG)); /* Clear the selected HASH flags */ HASH->SR = ~(uint32_t)HASH_FLAG; } /** * @brief Checks whether the specified HASH interrupt has occurred or not. * @param HASH_IT: specifies the HASH interrupt source to check. * This parameter can be one of the following values: * @arg HASH_IT_DINI: Data Input interrupt * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt * @retval The new state of HASH_IT (SET or RESET). */ ITStatus HASH_GetITStatus(uint8_t HASH_IT) { ITStatus bitstatus = RESET; uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_HASH_GET_IT(HASH_IT)); /* Check the status of the specified HASH interrupt */ tmpreg = HASH->SR; if (((HASH->IMR & tmpreg) & HASH_IT) != RESET) { /* HASH_IT is set */ bitstatus = SET; } else { /* HASH_IT is reset */ bitstatus = RESET; } /* Return the HASH_IT status */ return bitstatus; } /** * @brief Clears the HASH interrupt pending bit(s). * @param HASH_IT: specifies the HASH interrupt pending bit(s) to clear. * This parameter can be any combination of the following values: * @arg HASH_IT_DINI: Data Input interrupt * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt * @retval None */ void HASH_ClearITPendingBit(uint8_t HASH_IT) { /* Check the parameters */ assert_param(IS_HASH_IT(HASH_IT)); /* Clear the selected HASH interrupt pending bit */ HASH->SR = (uint8_t)~HASH_IT; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c ================================================ /** ****************************************************************************** * @file stm32f4xx_hash_md5.c * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file provides high level functions to compute the HASH MD5 and * HMAC MD5 Digest of an input message. * It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH * peripheral. * * @verbatim * * =================================================================== * How to use this driver * =================================================================== * 1. Enable The HASH controller clock using * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function. * * 2. Calculate the HASH MD5 Digest using HASH_MD5() function. * * 3. Calculate the HMAC MD5 Digest using HMAC_MD5() function. * * @endverbatim * ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hash.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup HASH * @brief HASH driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #define MD5BUSY_TIMEOUT ((uint32_t) 0x00010000) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup HASH_Private_Functions * @{ */ /** @defgroup HASH_Group7 High Level MD5 functions * @brief High Level MD5 Hash and HMAC functions * @verbatim =============================================================================== High Level MD5 Hash and HMAC functions =============================================================================== @endverbatim * @{ */ /** * @brief Compute the HASH MD5 digest. * @param Input: pointer to the Input buffer to be treated. * @param Ilen: length of the Input buffer. * @param Output: the returned digest * @retval An ErrorStatus enumeration value: * - SUCCESS: digest computation done * - ERROR: digest computation failed */ ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]) { HASH_InitTypeDef MD5_HASH_InitStructure; HASH_MsgDigest MD5_MessageDigest; __IO uint16_t nbvalidbitsdata = 0; uint32_t i = 0; __IO uint32_t counter = 0; uint32_t busystatus = 0; ErrorStatus status = SUCCESS; uint32_t inputaddr = (uint32_t)Input; uint32_t outputaddr = (uint32_t)Output; /* Number of valid bits in last word of the Input data */ nbvalidbitsdata = 8 * (Ilen % 4); /* HASH peripheral initialization */ HASH_DeInit(); /* HASH Configuration */ MD5_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_MD5; MD5_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH; MD5_HASH_InitStructure.HASH_DataType = HASH_DataType_8b; HASH_Init(&MD5_HASH_InitStructure); /* Configure the number of valid bits in last word of the data */ HASH_SetLastWordValidBitsNbr(nbvalidbitsdata); /* Write the Input block in the IN FIFO */ for(i=0; i 64) { /* HMAC long Key */ MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey; } else { /* HMAC short Key */ MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; } HASH_Init(&MD5_HASH_InitStructure); /* Configure the number of valid bits in last word of the Key */ HASH_SetLastWordValidBitsNbr(nbvalidbitskey); /* Write the Key */ for(i=0; i
© COPYRIGHT 2012 STMicroelectronics
* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hash.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup HASH * @brief HASH driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #define SHA1BUSY_TIMEOUT ((uint32_t) 0x00010000) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup HASH_Private_Functions * @{ */ /** @defgroup HASH_Group6 High Level SHA1 functions * @brief High Level SHA1 Hash and HMAC functions * @verbatim =============================================================================== High Level SHA1 Hash and HMAC functions =============================================================================== @endverbatim * @{ */ /** * @brief Compute the HASH SHA1 digest. * @param Input: pointer to the Input buffer to be treated. * @param Ilen: length of the Input buffer. * @param Output: the returned digest * @retval An ErrorStatus enumeration value: * - SUCCESS: digest computation done * - ERROR: digest computation failed */ ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]) { HASH_InitTypeDef SHA1_HASH_InitStructure; HASH_MsgDigest SHA1_MessageDigest; __IO uint16_t nbvalidbitsdata = 0; uint32_t i = 0; __IO uint32_t counter = 0; uint32_t busystatus = 0; ErrorStatus status = SUCCESS; uint32_t inputaddr = (uint32_t)Input; uint32_t outputaddr = (uint32_t)Output; /* Number of valid bits in last word of the Input data */ nbvalidbitsdata = 8 * (Ilen % 4); /* HASH peripheral initialization */ HASH_DeInit(); /* HASH Configuration */ SHA1_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_SHA1; SHA1_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH; SHA1_HASH_InitStructure.HASH_DataType = HASH_DataType_8b; HASH_Init(&SHA1_HASH_InitStructure); /* Configure the number of valid bits in last word of the data */ HASH_SetLastWordValidBitsNbr(nbvalidbitsdata); /* Write the Input block in the IN FIFO */ for(i=0; i 64) { /* HMAC long Key */ SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey; } else { /* HMAC short Key */ SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; } HASH_Init(&SHA1_HASH_InitStructure); /* Configure the number of valid bits in last word of the Key */ HASH_SetLastWordValidBitsNbr(nbvalidbitskey); /* Write the Key */ for(i=0; iGPIO_Mode = GPIO_Mode_AF * - Select the type, pull-up/pull-down and output speed via * GPIO_PuPd, GPIO_OType and GPIO_Speed members * - Call GPIO_Init() function * Recommended configuration is Push-Pull, Pull-up, Open-Drain. * Add an external pull up if necessary (typically 4.7 KOhm). * * 4. Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged * Address using the I2C_Init() function. * * 5. Optionally you can enable/configure the following parameters without * re-initialization (i.e there is no need to call again I2C_Init() function): * - Enable the acknowledge feature using I2C_AcknowledgeConfig() function * - Enable the dual addressing mode using I2C_DualAddressCmd() function * - Enable the general call using the I2C_GeneralCallCmd() function * - Enable the clock stretching using I2C_StretchClockCmd() function * - Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig() * function. * - Configure the NACK position for Master Receiver mode in case of * 2 bytes reception using the function I2C_NACKPositionConfig(). * - Enable the PEC Calculation using I2C_CalculatePEC() function * - For SMBus Mode: * - Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function * - Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function * * 6. Enable the NVIC and the corresponding interrupt using the function * I2C_ITConfig() if you need to use interrupt mode. * * 7. When using the DMA mode * - Configure the DMA using DMA_Init() function * - Active the needed channel Request using I2C_DMACmd() or * I2C_DMALastTransferCmd() function. * @note When using DMA mode, I2C interrupts may be used at the same time to * control the communication flow (Start/Stop/Ack... events and errors). * * 8. Enable the I2C using the I2C_Cmd() function. * * 9. Enable the DMA using the DMA_Cmd() function when using DMA mode in the * transfers. * * @endverbatim * ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_i2c.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup I2C * @brief I2C driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #define CR1_CLEAR_MASK ((uint16_t)0xFBF5) /*I2C_ClockSpeed)); assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle)); assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack)); assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); /*---------------------------- I2Cx CR2 Configuration ------------------------*/ /* Get the I2Cx CR2 value */ tmpreg = I2Cx->CR2; /* Clear frequency FREQ[5:0] bits */ tmpreg &= (uint16_t)~((uint16_t)I2C_CR2_FREQ); /* Get pclk1 frequency value */ RCC_GetClocksFreq(&rcc_clocks); pclk1 = rcc_clocks.PCLK1_Frequency; /* Set frequency bits depending on pclk1 value */ freqrange = (uint16_t)(pclk1 / 1000000); tmpreg |= freqrange; /* Write to I2Cx CR2 */ I2Cx->CR2 = tmpreg; /*---------------------------- I2Cx CCR Configuration ------------------------*/ /* Disable the selected I2C peripheral to configure TRISE */ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE); /* Reset tmpreg value */ /* Clear F/S, DUTY and CCR[11:0] bits */ tmpreg = 0; /* Configure speed in standard mode */ if (I2C_InitStruct->I2C_ClockSpeed <= 100000) { /* Standard mode speed calculate */ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); /* Test if CCR value is under 0x4*/ if (result < 0x04) { /* Set minimum allowed value */ result = 0x04; } /* Set speed value for standard mode */ tmpreg |= result; /* Set Maximum Rise Time for standard mode */ I2Cx->TRISE = freqrange + 1; } /* Configure speed in fast mode */ /* To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral input clock) must be a multiple of 10 MHz */ else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/ { if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) { /* Fast mode speed calculate: Tlow/Thigh = 2 */ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); } else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/ { /* Fast mode speed calculate: Tlow/Thigh = 16/9 */ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); /* Set DUTY bit */ result |= I2C_DutyCycle_16_9; } /* Test if CCR value is under 0x1*/ if ((result & I2C_CCR_CCR) == 0) { /* Set minimum allowed value */ result |= (uint16_t)0x0001; } /* Set speed value and set F/S bit for fast mode */ tmpreg |= (uint16_t)(result | I2C_CCR_FS); /* Set Maximum Rise Time for fast mode */ I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); } /* Write to I2Cx CCR */ I2Cx->CCR = tmpreg; /* Enable the selected I2C peripheral */ I2Cx->CR1 |= I2C_CR1_PE; /*---------------------------- I2Cx CR1 Configuration ------------------------*/ /* Get the I2Cx CR1 value */ tmpreg = I2Cx->CR1; /* Clear ACK, SMBTYPE and SMBUS bits */ tmpreg &= CR1_CLEAR_MASK; /* Configure I2Cx: mode and acknowledgement */ /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */ /* Set ACK bit according to I2C_Ack value */ tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); /* Write to I2Cx CR1 */ I2Cx->CR1 = tmpreg; /*---------------------------- I2Cx OAR1 Configuration -----------------------*/ /* Set I2Cx Own Address1 and acknowledged address */ I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); } /** * @brief Fills each I2C_InitStruct member with its default value. * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized. * @retval None */ void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) { /*---------------- Reset I2C init structure parameters values ----------------*/ /* initialize the I2C_ClockSpeed member */ I2C_InitStruct->I2C_ClockSpeed = 5000; /* Initialize the I2C_Mode member */ I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; /* Initialize the I2C_DutyCycle member */ I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; /* Initialize the I2C_OwnAddress1 member */ I2C_InitStruct->I2C_OwnAddress1 = 0; /* Initialize the I2C_Ack member */ I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; /* Initialize the I2C_AcknowledgedAddress member */ I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; } /** * @brief Enables or disables the specified I2C peripheral. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param NewState: new state of the I2Cx peripheral. * This parameter can be: ENABLE or DISABLE. * @retval None */ void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected I2C peripheral */ I2Cx->CR1 |= I2C_CR1_PE; } else { /* Disable the selected I2C peripheral */ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE); } } /** * @brief Generates I2Cx communication START condition. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param NewState: new state of the I2C START condition generation. * This parameter can be: ENABLE or DISABLE. * @retval None. */ void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Generate a START condition */ I2Cx->CR1 |= I2C_CR1_START; } else { /* Disable the START condition generation */ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_START); } } /** * @brief Generates I2Cx communication STOP condition. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param NewState: new state of the I2C STOP condition generation. * This parameter can be: ENABLE or DISABLE. * @retval None. */ void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Generate a STOP condition */ I2Cx->CR1 |= I2C_CR1_STOP; } else { /* Disable the STOP condition generation */ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_STOP); } } /** * @brief Transmits the address byte to select the slave device. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param Address: specifies the slave address which will be transmitted * @param I2C_Direction: specifies whether the I2C device will be a Transmitter * or a Receiver. * This parameter can be one of the following values * @arg I2C_Direction_Transmitter: Transmitter mode * @arg I2C_Direction_Receiver: Receiver mode * @retval None. */ void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_I2C_DIRECTION(I2C_Direction)); /* Test on the direction to set/reset the read/write bit */ if (I2C_Direction != I2C_Direction_Transmitter) { /* Set the address bit0 for read */ Address |= I2C_OAR1_ADD0; } else { /* Reset the address bit0 for write */ Address &= (uint8_t)~((uint8_t)I2C_OAR1_ADD0); } /* Send the address */ I2Cx->DR = Address; } /** * @brief Enables or disables the specified I2C acknowledge feature. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param NewState: new state of the I2C Acknowledgement. * This parameter can be: ENABLE or DISABLE. * @retval None. */ void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the acknowledgement */ I2Cx->CR1 |= I2C_CR1_ACK; } else { /* Disable the acknowledgement */ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ACK); } } /** * @brief Configures the specified I2C own address2. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param Address: specifies the 7bit I2C own address2. * @retval None. */ void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address) { uint16_t tmpreg = 0; /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); /* Get the old register value */ tmpreg = I2Cx->OAR2; /* Reset I2Cx Own address2 bit [7:1] */ tmpreg &= (uint16_t)~((uint16_t)I2C_OAR2_ADD2); /* Set I2Cx Own address2 */ tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); /* Store the new register value */ I2Cx->OAR2 = tmpreg; } /** * @brief Enables or disables the specified I2C dual addressing mode. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param NewState: new state of the I2C dual addressing mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable dual addressing mode */ I2Cx->OAR2 |= I2C_OAR2_ENDUAL; } else { /* Disable dual addressing mode */ I2Cx->OAR2 &= (uint16_t)~((uint16_t)I2C_OAR2_ENDUAL); } } /** * @brief Enables or disables the specified I2C general call feature. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param NewState: new state of the I2C General call. * This parameter can be: ENABLE or DISABLE. * @retval None */ void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable generall call */ I2Cx->CR1 |= I2C_CR1_ENGC; } else { /* Disable generall call */ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENGC); } } /** * @brief Enables or disables the specified I2C software reset. * @note When software reset is enabled, the I2C IOs are released (this can * be useful to recover from bus errors). * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param NewState: new state of the I2C software reset. * This parameter can be: ENABLE or DISABLE. * @retval None */ void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Peripheral under reset */ I2Cx->CR1 |= I2C_CR1_SWRST; } else { /* Peripheral not under reset */ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_SWRST); } } /** * @brief Enables or disables the specified I2C Clock stretching. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param NewState: new state of the I2Cx Clock stretching. * This parameter can be: ENABLE or DISABLE. * @retval None */ void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState == DISABLE) { /* Enable the selected I2C Clock stretching */ I2Cx->CR1 |= I2C_CR1_NOSTRETCH; } else { /* Disable the selected I2C Clock stretching */ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_NOSTRETCH); } } /** * @brief Selects the specified I2C fast mode duty cycle. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param I2C_DutyCycle: specifies the fast mode duty cycle. * This parameter can be one of the following values: * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2 * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9 * @retval None */ void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle)); if (I2C_DutyCycle != I2C_DutyCycle_16_9) { /* I2C fast mode Tlow/Thigh=2 */ I2Cx->CCR &= I2C_DutyCycle_2; } else { /* I2C fast mode Tlow/Thigh=16/9 */ I2Cx->CCR |= I2C_DutyCycle_16_9; } } /** * @brief Selects the specified I2C NACK position in master receiver mode. * @note This function is useful in I2C Master Receiver mode when the number * of data to be received is equal to 2. In this case, this function * should be called (with parameter I2C_NACKPosition_Next) before data * reception starts,as described in the 2-byte reception procedure * recommended in Reference Manual in Section: Master receiver. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param I2C_NACKPosition: specifies the NACK position. * This parameter can be one of the following values: * @arg I2C_NACKPosition_Next: indicates that the next byte will be the last * received byte. * @arg I2C_NACKPosition_Current: indicates that current byte is the last * received byte. * * @note This function configures the same bit (POS) as I2C_PECPositionConfig() * but is intended to be used in I2C mode while I2C_PECPositionConfig() * is intended to used in SMBUS mode. * * @retval None */ void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition)); /* Check the input parameter */ if (I2C_NACKPosition == I2C_NACKPosition_Next) { /* Next byte in shift register is the last received byte */ I2Cx->CR1 |= I2C_NACKPosition_Next; } else { /* Current byte in shift register is the last received byte */ I2Cx->CR1 &= I2C_NACKPosition_Current; } } /** * @brief Drives the SMBusAlert pin high or low for the specified I2C. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param I2C_SMBusAlert: specifies SMBAlert pin level. * This parameter can be one of the following values: * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low * @arg I2C_SMBusAlert_High: SMBAlert pin driven high * @retval None */ void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert)); if (I2C_SMBusAlert == I2C_SMBusAlert_Low) { /* Drive the SMBusAlert pin Low */ I2Cx->CR1 |= I2C_SMBusAlert_Low; } else { /* Drive the SMBusAlert pin High */ I2Cx->CR1 &= I2C_SMBusAlert_High; } } /** * @brief Enables or disables the specified I2C ARP. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param NewState: new state of the I2Cx ARP. * This parameter can be: ENABLE or DISABLE. * @retval None */ void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected I2C ARP */ I2Cx->CR1 |= I2C_CR1_ENARP; } else { /* Disable the selected I2C ARP */ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENARP); } } /** * @} */ /** @defgroup I2C_Group2 Data transfers functions * @brief Data transfers functions * @verbatim =============================================================================== Data transfers functions =============================================================================== @endverbatim * @{ */ /** * @brief Sends a data byte through the I2Cx peripheral. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param Data: Byte to be transmitted.. * @retval None */ void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); /* Write in the DR register the data to be sent */ I2Cx->DR = Data; } /** * @brief Returns the most recent received data by the I2Cx peripheral. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @retval The value of the received data. */ uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); /* Return the data in the DR register */ return (uint8_t)I2Cx->DR; } /** * @} */ /** @defgroup I2C_Group3 PEC management functions * @brief PEC management functions * @verbatim =============================================================================== PEC management functions =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables the specified I2C PEC transfer. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param NewState: new state of the I2C PEC transmission. * This parameter can be: ENABLE or DISABLE. * @retval None */ void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected I2C PEC transmission */ I2Cx->CR1 |= I2C_CR1_PEC; } else { /* Disable the selected I2C PEC transmission */ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PEC); } } /** * @brief Selects the specified I2C PEC position. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param I2C_PECPosition: specifies the PEC position. * This parameter can be one of the following values: * @arg I2C_PECPosition_Next: indicates that the next byte is PEC * @arg I2C_PECPosition_Current: indicates that current byte is PEC * * @note This function configures the same bit (POS) as I2C_NACKPositionConfig() * but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() * is intended to used in I2C mode. * * @retval None */ void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition)); if (I2C_PECPosition == I2C_PECPosition_Next) { /* Next byte in shift register is PEC */ I2Cx->CR1 |= I2C_PECPosition_Next; } else { /* Current byte in shift register is PEC */ I2Cx->CR1 &= I2C_PECPosition_Current; } } /** * @brief Enables or disables the PEC value calculation of the transferred bytes. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param NewState: new state of the I2Cx PEC value calculation. * This parameter can be: ENABLE or DISABLE. * @retval None */ void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected I2C PEC calculation */ I2Cx->CR1 |= I2C_CR1_ENPEC; } else { /* Disable the selected I2C PEC calculation */ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENPEC); } } /** * @brief Returns the PEC value for the specified I2C. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @retval The PEC value. */ uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); /* Return the selected I2C PEC value */ return ((I2Cx->SR2) >> 8); } /** * @} */ /** @defgroup I2C_Group4 DMA transfers management functions * @brief DMA transfers management functions * @verbatim =============================================================================== DMA transfers management functions =============================================================================== This section provides functions allowing to configure the I2C DMA channels requests. @endverbatim * @{ */ /** * @brief Enables or disables the specified I2C DMA requests. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param NewState: new state of the I2C DMA transfer. * This parameter can be: ENABLE or DISABLE. * @retval None */ void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected I2C DMA requests */ I2Cx->CR2 |= I2C_CR2_DMAEN; } else { /* Disable the selected I2C DMA requests */ I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_DMAEN); } } /** * @brief Specifies that the next DMA transfer is the last one. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param NewState: new state of the I2C DMA last transfer. * This parameter can be: ENABLE or DISABLE. * @retval None */ void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Next DMA transfer is the last transfer */ I2Cx->CR2 |= I2C_CR2_LAST; } else { /* Next DMA transfer is not the last transfer */ I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_LAST); } } /** * @} */ /** @defgroup I2C_Group5 Interrupts events and flags management functions * @brief Interrupts, events and flags management functions * @verbatim =============================================================================== Interrupts, events and flags management functions =============================================================================== This section provides functions allowing to configure the I2C Interrupts sources and check or clear the flags or pending bits status. The user should identify which mode will be used in his application to manage the communication: Polling mode, Interrupt mode or DMA mode. =============================================================================== I2C State Monitoring Functions =============================================================================== This I2C driver provides three different ways for I2C state monitoring depending on the application requirements and constraints: 1. Basic state monitoring (Using I2C_CheckEvent() function) ----------------------------------------------------------- It compares the status registers (SR1 and SR2) content to a given event (can be the combination of one or more flags). It returns SUCCESS if the current status includes the given flags and returns ERROR if one or more flags are missing in the current status. - When to use - This function is suitable for most applications as well as for startup activity since the events are fully described in the product reference manual (RM0090). - It is also suitable for users who need to define their own events. - Limitations - If an error occurs (ie. error flags are set besides to the monitored flags), the I2C_CheckEvent() function may return SUCCESS despite the communication hold or corrupted real state. In this case, it is advised to use error interrupts to monitor the error events and handle them in the interrupt IRQ handler. @note For error management, it is advised to use the following functions: - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. Where x is the peripheral instance (I2C1, I2C2 ...) - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the I2Cx_ER_IRQHandler() function in order to determine which error occurred. - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() and/or I2C_GenerateStop() in order to clear the error flag and source and return to correct communication status. 2. Advanced state monitoring (Using the function I2C_GetLastEvent()) -------------------------------------------------------------------- Using the function I2C_GetLastEvent() which returns the image of both status registers in a single word (uint32_t) (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1). - When to use - This function is suitable for the same applications above but it allows to overcome the mentioned limitation of I2C_GetFlagStatus() function. - The returned value could be compared to events already defined in the library (stm32f4xx_i2c.h) or to custom values defined by user. This function is suitable when multiple flags are monitored at the same time. - At the opposite of I2C_CheckEvent() function, this function allows user to choose when an event is accepted (when all events flags are set and no other flags are set or just when the needed flags are set like I2C_CheckEvent() function. - Limitations - User may need to define his own events. - Same remark concerning the error management is applicable for this function if user decides to check only regular communication flags (and ignores error flags). 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus()) ----------------------------------------------------------------------- Using the function I2C_GetFlagStatus() which simply returns the status of one single flag (ie. I2C_FLAG_RXNE ...). - When to use - This function could be used for specific applications or in debug phase. - It is suitable when only one flag checking is needed (most I2C events are monitored through multiple flags). - Limitations: - When calling this function, the Status register is accessed. Some flags are cleared when the status register is accessed. So checking the status of one Flag, may clear other ones. - Function may need to be called twice or more in order to monitor one single event. For detailed description of Events, please refer to section I2C_Events in stm32f4xx_i2c.h file. @endverbatim * @{ */ /** * @brief Reads the specified I2C register and returns its value. * @param I2C_Register: specifies the register to read. * This parameter can be one of the following values: * @arg I2C_Register_CR1: CR1 register. * @arg I2C_Register_CR2: CR2 register. * @arg I2C_Register_OAR1: OAR1 register. * @arg I2C_Register_OAR2: OAR2 register. * @arg I2C_Register_DR: DR register. * @arg I2C_Register_SR1: SR1 register. * @arg I2C_Register_SR2: SR2 register. * @arg I2C_Register_CCR: CCR register. * @arg I2C_Register_TRISE: TRISE register. * @retval The value of the read register. */ uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) { __IO uint32_t tmp = 0; /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_I2C_REGISTER(I2C_Register)); tmp = (uint32_t) I2Cx; tmp += I2C_Register; /* Return the selected register value */ return (*(__IO uint16_t *) tmp); } /** * @brief Enables or disables the specified I2C interrupts. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg I2C_IT_BUF: Buffer interrupt mask * @arg I2C_IT_EVT: Event interrupt mask * @arg I2C_IT_ERR: Error interrupt mask * @param NewState: new state of the specified I2C interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); assert_param(IS_I2C_CONFIG_IT(I2C_IT)); if (NewState != DISABLE) { /* Enable the selected I2C interrupts */ I2Cx->CR2 |= I2C_IT; } else { /* Disable the selected I2C interrupts */ I2Cx->CR2 &= (uint16_t)~I2C_IT; } } /* =============================================================================== 1. Basic state monitoring =============================================================================== */ /** * @brief Checks whether the last I2Cx Event is equal to the one passed * as parameter. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param I2C_EVENT: specifies the event to be checked. * This parameter can be one of the following values: * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED: EV1 * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED: EV1 * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED: EV1 * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED: EV1 * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED: EV1 * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED: EV2 * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF): EV2 * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL): EV2 * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED: EV3 * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF): EV3 * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL): EV3 * @arg I2C_EVENT_SLAVE_ACK_FAILURE: EV3_2 * @arg I2C_EVENT_SLAVE_STOP_DETECTED: EV4 * @arg I2C_EVENT_MASTER_MODE_SELECT: EV5 * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED: EV6 * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED: EV6 * @arg I2C_EVENT_MASTER_BYTE_RECEIVED: EV7 * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING: EV8 * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED: EV8_2 * @arg I2C_EVENT_MASTER_MODE_ADDRESS10: EV9 * * @note For detailed description of Events, please refer to section I2C_Events * in stm32f4xx_i2c.h file. * * @retval An ErrorStatus enumeration value: * - SUCCESS: Last event is equal to the I2C_EVENT * - ERROR: Last event is different from the I2C_EVENT */ ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT) { uint32_t lastevent = 0; uint32_t flag1 = 0, flag2 = 0; ErrorStatus status = ERROR; /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_I2C_EVENT(I2C_EVENT)); /* Read the I2Cx status register */ flag1 = I2Cx->SR1; flag2 = I2Cx->SR2; flag2 = flag2 << 16; /* Get the last event value from I2C status register */ lastevent = (flag1 | flag2) & FLAG_MASK; /* Check whether the last event contains the I2C_EVENT */ if ((lastevent & I2C_EVENT) == I2C_EVENT) { /* SUCCESS: last event is equal to I2C_EVENT */ status = SUCCESS; } else { /* ERROR: last event is different from I2C_EVENT */ status = ERROR; } /* Return status */ return status; } /* =============================================================================== 2. Advanced state monitoring =============================================================================== */ /** * @brief Returns the last I2Cx Event. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * * @note For detailed description of Events, please refer to section I2C_Events * in stm32f4xx_i2c.h file. * * @retval The last event */ uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx) { uint32_t lastevent = 0; uint32_t flag1 = 0, flag2 = 0; /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); /* Read the I2Cx status register */ flag1 = I2Cx->SR1; flag2 = I2Cx->SR2; flag2 = flag2 << 16; /* Get the last event value from I2C status register */ lastevent = (flag1 | flag2) & FLAG_MASK; /* Return status */ return lastevent; } /* =============================================================================== 3. Flag-based state monitoring =============================================================================== */ /** * @brief Checks whether the specified I2C flag is set or not. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param I2C_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg I2C_FLAG_DUALF: Dual flag (Slave mode) * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode) * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode) * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode) * @arg I2C_FLAG_TRA: Transmitter/Receiver flag * @arg I2C_FLAG_BUSY: Bus busy flag * @arg I2C_FLAG_MSL: Master/Slave flag * @arg I2C_FLAG_SMBALERT: SMBus Alert flag * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag * @arg I2C_FLAG_PECERR: PEC error in reception flag * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) * @arg I2C_FLAG_AF: Acknowledge failure flag * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) * @arg I2C_FLAG_BERR: Bus error flag * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter) * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode) * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode) * @arg I2C_FLAG_BTF: Byte transfer finished flag * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL" * Address matched flag (Slave mode)"ENDAD" * @arg I2C_FLAG_SB: Start bit flag (Master mode) * @retval The new state of I2C_FLAG (SET or RESET). */ FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) { FlagStatus bitstatus = RESET; __IO uint32_t i2creg = 0, i2cxbase = 0; /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); /* Get the I2Cx peripheral base address */ i2cxbase = (uint32_t)I2Cx; /* Read flag register index */ i2creg = I2C_FLAG >> 28; /* Get bit[23:0] of the flag */ I2C_FLAG &= FLAG_MASK; if(i2creg != 0) { /* Get the I2Cx SR1 register address */ i2cxbase += 0x14; } else { /* Flag in I2Cx SR2 Register */ I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); /* Get the I2Cx SR2 register address */ i2cxbase += 0x18; } if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) { /* I2C_FLAG is set */ bitstatus = SET; } else { /* I2C_FLAG is reset */ bitstatus = RESET; } /* Return the I2C_FLAG status */ return bitstatus; } /** * @brief Clears the I2Cx's pending flags. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param I2C_FLAG: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg I2C_FLAG_SMBALERT: SMBus Alert flag * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag * @arg I2C_FLAG_PECERR: PEC error in reception flag * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) * @arg I2C_FLAG_AF: Acknowledge failure flag * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) * @arg I2C_FLAG_BERR: Bus error flag * * @note STOPF (STOP detection) is cleared by software sequence: a read operation * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). * @note ADD10 (10-bit header sent) is cleared by software sequence: a read * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the * second byte of the address in DR register. * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a * read/write to I2C_DR register (I2C_SendData()). * @note ADDR (Address sent) is cleared by software sequence: a read operation to * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to * I2C_SR2 register ((void)(I2Cx->SR2)). * @note SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR * register (I2C_SendData()). * * @retval None */ void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) { uint32_t flagpos = 0; /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); /* Get the I2C flag position */ flagpos = I2C_FLAG & FLAG_MASK; /* Clear the selected I2C flag */ I2Cx->SR1 = (uint16_t)~flagpos; } /** * @brief Checks whether the specified I2C interrupt has occurred or not. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param I2C_IT: specifies the interrupt source to check. * This parameter can be one of the following values: * @arg I2C_IT_SMBALERT: SMBus Alert flag * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag * @arg I2C_IT_PECERR: PEC error in reception flag * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode) * @arg I2C_IT_AF: Acknowledge failure flag * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode) * @arg I2C_IT_BERR: Bus error flag * @arg I2C_IT_TXE: Data register empty flag (Transmitter) * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag * @arg I2C_IT_STOPF: Stop detection flag (Slave mode) * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode) * @arg I2C_IT_BTF: Byte transfer finished flag * @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL" * Address matched flag (Slave mode)"ENDAD" * @arg I2C_IT_SB: Start bit flag (Master mode) * @retval The new state of I2C_IT (SET or RESET). */ ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) { ITStatus bitstatus = RESET; uint32_t enablestatus = 0; /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_I2C_GET_IT(I2C_IT)); /* Check if the interrupt source is enabled or not */ enablestatus = (uint32_t)(((I2C_IT & ITEN_MASK) >> 16) & (I2Cx->CR2)) ; /* Get bit[23:0] of the flag */ I2C_IT &= FLAG_MASK; /* Check the status of the specified I2C flag */ if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) { /* I2C_IT is set */ bitstatus = SET; } else { /* I2C_IT is reset */ bitstatus = RESET; } /* Return the I2C_IT status */ return bitstatus; } /** * @brief Clears the I2Cx's interrupt pending bits. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param I2C_IT: specifies the interrupt pending bit to clear. * This parameter can be any combination of the following values: * @arg I2C_IT_SMBALERT: SMBus Alert interrupt * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt * @arg I2C_IT_PECERR: PEC error in reception interrupt * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode) * @arg I2C_IT_AF: Acknowledge failure interrupt * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode) * @arg I2C_IT_BERR: Bus error interrupt * * @note STOPF (STOP detection) is cleared by software sequence: a read operation * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). * @note ADD10 (10-bit header sent) is cleared by software sequence: a read * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second * byte of the address in I2C_DR register. * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a * read/write to I2C_DR register (I2C_SendData()). * @note ADDR (Address sent) is cleared by software sequence: a read operation to * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to * I2C_SR2 register ((void)(I2Cx->SR2)). * @note SB (Start Bit) is cleared by software sequence: a read operation to * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to * I2C_DR register (I2C_SendData()). * @retval None */ void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) { uint32_t flagpos = 0; /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_I2C_CLEAR_IT(I2C_IT)); /* Get the I2C flag position */ flagpos = I2C_IT & FLAG_MASK; /* Clear the selected I2C flag */ I2Cx->SR1 = (uint16_t)~flagpos; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c ================================================ /** ****************************************************************************** * @file stm32f4xx_iwdg.c * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file provides firmware functions to manage the following * functionalities of the Independent watchdog (IWDG) peripheral: * - Prescaler and Counter configuration * - IWDG activation * - Flag management * * @verbatim * * =================================================================== * IWDG features * =================================================================== * * The IWDG can be started by either software or hardware (configurable * through option byte). * * The IWDG is clocked by its own dedicated low-speed clock (LSI) and * thus stays active even if the main clock fails. * Once the IWDG is started, the LSI is forced ON and cannot be disabled * (LSI cannot be disabled too), and the counter starts counting down from * the reset value of 0xFFF. When it reaches the end of count value (0x000) * a system reset is generated. * The IWDG counter should be reloaded at regular intervals to prevent * an MCU reset. * * The IWDG is implemented in the VDD voltage domain that is still functional * in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). * * IWDGRST flag in RCC_CSR register can be used to inform when a IWDG * reset occurs. * * Min-max timeout value @32KHz (LSI): ~125us / ~32.7s * The IWDG timeout may vary due to LSI frequency dispersion. STM32F4xx * devices provide the capability to measure the LSI frequency (LSI clock * connected internally to TIM5 CH4 input capture). The measured value * can be used to have an IWDG timeout with an acceptable accuracy. * For more information, please refer to the STM32F4xx Reference manual * * * =================================================================== * How to use this driver * =================================================================== * 1. Enable write access to IWDG_PR and IWDG_RLR registers using * IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function * * 2. Configure the IWDG prescaler using IWDG_SetPrescaler() function * * 3. Configure the IWDG counter value using IWDG_SetReload() function. * This value will be loaded in the IWDG counter each time the counter * is reloaded, then the IWDG will start counting down from this value. * * 4. Start the IWDG using IWDG_Enable() function, when the IWDG is used * in software mode (no need to enable the LSI, it will be enabled * by hardware) * * 5. Then the application program must reload the IWDG counter at regular * intervals during normal operation to prevent an MCU reset, using * IWDG_ReloadCounter() function. * * @endverbatim * ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_iwdg.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup IWDG * @brief IWDG driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* KR register bit mask */ #define KR_KEY_RELOAD ((uint16_t)0xAAAA) #define KR_KEY_ENABLE ((uint16_t)0xCCCC) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup IWDG_Private_Functions * @{ */ /** @defgroup IWDG_Group1 Prescaler and Counter configuration functions * @brief Prescaler and Counter configuration functions * @verbatim =============================================================================== Prescaler and Counter configuration functions =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. * This parameter can be one of the following values: * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers * @retval None */ void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) { /* Check the parameters */ assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); IWDG->KR = IWDG_WriteAccess; } /** * @brief Sets IWDG Prescaler value. * @param IWDG_Prescaler: specifies the IWDG Prescaler value. * This parameter can be one of the following values: * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 * @retval None */ void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) { /* Check the parameters */ assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); IWDG->PR = IWDG_Prescaler; } /** * @brief Sets IWDG Reload value. * @param Reload: specifies the IWDG Reload value. * This parameter must be a number between 0 and 0x0FFF. * @retval None */ void IWDG_SetReload(uint16_t Reload) { /* Check the parameters */ assert_param(IS_IWDG_RELOAD(Reload)); IWDG->RLR = Reload; } /** * @brief Reloads IWDG counter with value defined in the reload register * (write access to IWDG_PR and IWDG_RLR registers disabled). * @param None * @retval None */ void IWDG_ReloadCounter(void) { IWDG->KR = KR_KEY_RELOAD; } /** * @} */ /** @defgroup IWDG_Group2 IWDG activation function * @brief IWDG activation function * @verbatim =============================================================================== IWDG activation function =============================================================================== @endverbatim * @{ */ /** * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). * @param None * @retval None */ void IWDG_Enable(void) { IWDG->KR = KR_KEY_ENABLE; } /** * @} */ /** @defgroup IWDG_Group3 Flag management function * @brief Flag management function * @verbatim =============================================================================== Flag management function =============================================================================== @endverbatim * @{ */ /** * @brief Checks whether the specified IWDG flag is set or not. * @param IWDG_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg IWDG_FLAG_PVU: Prescaler Value Update on going * @arg IWDG_FLAG_RVU: Reload Value Update on going * @retval The new state of IWDG_FLAG (SET or RESET). */ FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_IWDG_FLAG(IWDG_FLAG)); if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } /* Return the flag status */ return bitstatus; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_pwr.c ================================================ /** ****************************************************************************** * @file stm32f4xx_pwr.c * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: * - Backup Domain Access * - PVD configuration * - WakeUp pin configuration * - Main and Backup Regulators configuration * - FLASH Power Down configuration * - Low Power modes configuration * - Flags management * ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_pwr.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup PWR * @brief PWR driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* --------- PWR registers bit address in the alias region ---------- */ #define PWR_OFFSET (PWR_BASE - PERIPH_BASE) /* --- CR Register ---*/ /* Alias word address of DBP bit */ #define CR_OFFSET (PWR_OFFSET + 0x00) #define DBP_BitNumber 0x08 #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) /* Alias word address of PVDE bit */ #define PVDE_BitNumber 0x04 #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) /* Alias word address of FPDS bit */ #define FPDS_BitNumber 0x09 #define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4)) /* Alias word address of PMODE bit */ #define PMODE_BitNumber 0x0E #define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4)) /* --- CSR Register ---*/ /* Alias word address of EWUP bit */ #define CSR_OFFSET (PWR_OFFSET + 0x04) #define EWUP_BitNumber 0x08 #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) /* Alias word address of BRE bit */ #define BRE_BitNumber 0x09 #define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4)) /* ------------------ PWR registers bit mask ------------------------ */ /* CR register bit mask */ #define CR_DS_MASK ((uint32_t)0xFFFFFFFC) #define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup PWR_Private_Functions * @{ */ /** @defgroup PWR_Group1 Backup Domain Access function * @brief Backup Domain Access function * @verbatim =============================================================================== Backup Domain Access function =============================================================================== After reset, the backup domain (RTC registers, RTC backup data registers and backup SRAM) is protected against possible unwanted write accesses. To enable access to the RTC Domain and RTC registers, proceed as follows: - Enable the Power Controller (PWR) APB1 interface clock using the RCC_APB1PeriphClockCmd() function. - Enable access to RTC domain using the PWR_BackupAccessCmd() function. @endverbatim * @{ */ /** * @brief Deinitializes the PWR peripheral registers to their default reset values. * @param None * @retval None */ void PWR_DeInit(void) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); } /** * @brief Enables or disables access to the backup domain (RTC registers, RTC * backup data registers and backup SRAM). * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the * Backup Domain Access should be kept enabled. * @param NewState: new state of the access to the backup domain. * This parameter can be: ENABLE or DISABLE. * @retval None */ void PWR_BackupAccessCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; } /** * @} */ /** @defgroup PWR_Group2 PVD configuration functions * @brief PVD configuration functions * @verbatim =============================================================================== PVD configuration functions =============================================================================== - The PVD is used to monitor the VDD power supply by comparing it to a threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). - A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the PVD threshold. This event is internally connected to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers. - The PVD is stopped in Standby mode. @endverbatim * @{ */ /** * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). * @param PWR_PVDLevel: specifies the PVD detection level * This parameter can be one of the following values: * @arg PWR_PVDLevel_0 * @arg PWR_PVDLevel_1 * @arg PWR_PVDLevel_2 * @arg PWR_PVDLevel_3 * @arg PWR_PVDLevel_4 * @arg PWR_PVDLevel_5 * @arg PWR_PVDLevel_6 * @arg PWR_PVDLevel_7 * @note Refer to the electrical characteristics of your device datasheet for * more details about the voltage threshold corresponding to each * detection level. * @retval None */ void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); tmpreg = PWR->CR; /* Clear PLS[7:5] bits */ tmpreg &= CR_PLS_MASK; /* Set PLS[7:5] bits according to PWR_PVDLevel value */ tmpreg |= PWR_PVDLevel; /* Store the new value */ PWR->CR = tmpreg; } /** * @brief Enables or disables the Power Voltage Detector(PVD). * @param NewState: new state of the PVD. * This parameter can be: ENABLE or DISABLE. * @retval None */ void PWR_PVDCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; } /** * @} */ /** @defgroup PWR_Group3 WakeUp pin configuration functions * @brief WakeUp pin configuration functions * @verbatim =============================================================================== WakeUp pin configuration functions =============================================================================== - WakeUp pin is used to wakeup the system from Standby mode. This pin is forced in input pull down configuration and is active on rising edges. - There is only one WakeUp pin: WakeUp Pin 1 on PA.00. @endverbatim * @{ */ /** * @brief Enables or disables the WakeUp Pin functionality. * @param NewState: new state of the WakeUp Pin functionality. * This parameter can be: ENABLE or DISABLE. * @retval None */ void PWR_WakeUpPinCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; } /** * @} */ /** @defgroup PWR_Group4 Main and Backup Regulators configuration functions * @brief Main and Backup Regulators configuration functions * @verbatim =============================================================================== Main and Backup Regulators configuration functions =============================================================================== - The backup domain includes 4 Kbytes of backup SRAM accessible only from the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is retained even in Standby or VBAT mode when the low power backup regulator is enabled. It can be considered as an internal EEPROM when VBAT is always present. You can use the PWR_BackupRegulatorCmd() function to enable the low power backup regulator and use the PWR_GetFlagStatus(PWR_FLAG_BRR) to check if it is ready or not. - When the backup domain is supplied by VDD (analog switch connected to VDD) the backup SRAM is powered from VDD which replaces the VBAT power supply to save battery life. - The backup SRAM is not mass erased by an tamper event. It is read protected to prevent confidential data, such as cryptographic private key, from being accessed. The backup SRAM can be erased only through the Flash interface when a protection level change from level 1 to level 0 is requested. Refer to the description of Read protection (RDP) in the Flash programming manual. - The main internal regulator can be configured to have a tradeoff between performance and power consumption when the device does not operate at the maximum frequency. This is done through PWR_MainRegulatorModeConfig() function which configure VOS bit in PWR_CR register: - When this bit is set (Regulator voltage output Scale 1 mode selected) the System frequency can go up to 168 MHz. - When this bit is reset (Regulator voltage output Scale 2 mode selected) the System frequency can go up to 144 MHz. Refer to the datasheets for more details. @endverbatim * @{ */ /** * @brief Enables or disables the Backup Regulator. * @param NewState: new state of the Backup Regulator. * This parameter can be: ENABLE or DISABLE. * @retval None */ void PWR_BackupRegulatorCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)NewState; } /** * @brief Configures the main internal regulator output voltage. * @param PWR_Regulator_Voltage: specifies the regulator output voltage to achieve * a tradeoff between performance and power consumption when the device does * not operate at the maximum frequency (refer to the datasheets for more details). * This parameter can be one of the following values: * @arg PWR_Regulator_Voltage_Scale1: Regulator voltage output Scale 1 mode, * System frequency up to 168 MHz. * @arg PWR_Regulator_Voltage_Scale2: Regulator voltage output Scale 2 mode, * System frequency up to 144 MHz. * @retval None */ void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage) { /* Check the parameters */ assert_param(IS_PWR_REGULATOR_VOLTAGE(PWR_Regulator_Voltage)); if (PWR_Regulator_Voltage == PWR_Regulator_Voltage_Scale2) { PWR->CR &= ~PWR_Regulator_Voltage_Scale1; } else { PWR->CR |= PWR_Regulator_Voltage_Scale1; } } /** * @} */ /** @defgroup PWR_Group5 FLASH Power Down configuration functions * @brief FLASH Power Down configuration functions * @verbatim =============================================================================== FLASH Power Down configuration functions =============================================================================== - By setting the FPDS bit in the PWR_CR register by using the PWR_FlashPowerDownCmd() function, the Flash memory also enters power down mode when the device enters Stop mode. When the Flash memory is in power down mode, an additional startup delay is incurred when waking up from Stop mode. @endverbatim * @{ */ /** * @brief Enables or disables the Flash Power Down in STOP mode. * @param NewState: new state of the Flash power mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void PWR_FlashPowerDownCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)NewState; } /** * @} */ /** @defgroup PWR_Group6 Low Power modes configuration functions * @brief Low Power modes configuration functions * @verbatim =============================================================================== Low Power modes configuration functions =============================================================================== The devices feature 3 low-power modes: - Sleep mode: Cortex-M4 core stopped, peripherals kept running. - Stop mode: all clocks are stopped, regulator running, regulator in low power mode - Standby mode: 1.2V domain powered off. Sleep mode =========== - Entry: - The Sleep mode is entered by using the __WFI() or __WFE() functions. - Exit: - Any peripheral interrupt acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device from Sleep mode. Stop mode ========== In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI, and the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved. The voltage regulator can be configured either in normal or low-power mode. To minimize the consumption In Stop mode, FLASH can be powered off before entering the Stop mode. It can be switched on again by software after exiting the Stop mode using the PWR_FlashPowerDownCmd() function. - Entry: - The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,) function with regulator in LowPower or with Regulator ON. - Exit: - Any EXTI Line (Internal or External) configured in Interrupt/Event mode. Standby mode ============ The Standby mode allows to achieve the lowest power consumption. It is based on the Cortex-M4 deepsleep mode, with the voltage regulator disabled. The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also switched off. SRAM and register contents are lost except for the RTC registers, RTC backup registers, backup SRAM and Standby circuitry. The voltage regulator is OFF. - Entry: - The Standby mode is entered using the PWR_EnterSTANDBYMode() function. - Exit: - WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, tamper event, time-stamp event, external reset in NRST pin, IWDG reset. Auto-wakeup (AWU) from low-power mode ===================================== The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC Wakeup event, a tamper event, a time-stamp event, or a comparator event, without depending on an external interrupt (Auto-wakeup mode). - RTC auto-wakeup (AWU) from the Stop mode ---------------------------------------- - To wake up from the Stop mode with an RTC alarm event, it is necessary to: - Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt or Event modes) using the EXTI_Init() function. - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() and RTC_AlarmCmd() functions. - To wake up from the Stop mode with an RTC Tamper or time stamp event, it is necessary to: - Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt or Event modes) using the EXTI_Init() function. - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() function - Configure the RTC to detect the tamper or time stamp event using the RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() functions. - To wake up from the Stop mode with an RTC WakeUp event, it is necessary to: - Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt or Event modes) using the EXTI_Init() function. - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. - RTC auto-wakeup (AWU) from the Standby mode ------------------------------------------- - To wake up from the Standby mode with an RTC alarm event, it is necessary to: - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() and RTC_AlarmCmd() functions. - To wake up from the Standby mode with an RTC Tamper or time stamp event, it is necessary to: - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() function - Configure the RTC to detect the tamper or time stamp event using the RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() functions. - To wake up from the Standby mode with an RTC WakeUp event, it is necessary to: - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. @endverbatim * @{ */ /** * @brief Enters STOP mode. * * @note In Stop mode, all I/O pins keep the same state as in Run mode. * @note When exiting Stop mode by issuing an interrupt or a wakeup event, * the HSI RC oscillator is selected as system clock. * @note When the voltage regulator operates in low power mode, an additional * startup delay is incurred when waking up from Stop mode. * By keeping the internal regulator ON during Stop mode, the consumption * is higher although the startup time is reduced. * * @param PWR_Regulator: specifies the regulator state in STOP mode. * This parameter can be one of the following values: * @arg PWR_Regulator_ON: STOP mode with regulator ON * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction * @retval None */ void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_PWR_REGULATOR(PWR_Regulator)); assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); /* Select the regulator state in STOP mode ---------------------------------*/ tmpreg = PWR->CR; /* Clear PDDS and LPDSR bits */ tmpreg &= CR_DS_MASK; /* Set LPDSR bit according to PWR_Regulator value */ tmpreg |= PWR_Regulator; /* Store the new value */ PWR->CR = tmpreg; /* Set SLEEPDEEP bit of Cortex System Control Register */ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; /* Select STOP mode entry --------------------------------------------------*/ if(PWR_STOPEntry == PWR_STOPEntry_WFI) { /* Request Wait For Interrupt */ __WFI(); } else { /* Request Wait For Event */ __WFE(); } /* Reset SLEEPDEEP bit of Cortex System Control Register */ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); } /** * @brief Enters STANDBY mode. * @note In Standby mode, all I/O pins are high impedance except for: * - Reset pad (still available) * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC * Alarm out, or RTC clock calibration out. * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. * - WKUP pin 1 (PA0) if enabled. * @param None * @retval None */ void PWR_EnterSTANDBYMode(void) { /* Clear Wakeup flag */ PWR->CR |= PWR_CR_CWUF; /* Select STANDBY mode */ PWR->CR |= PWR_CR_PDDS; /* Set SLEEPDEEP bit of Cortex System Control Register */ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; /* This option is used to ensure that store operations are completed */ #if defined ( __CC_ARM ) __force_stores(); #endif /* Request Wait For Interrupt */ __WFI(); } /** * @} */ /** @defgroup PWR_Group7 Flags management functions * @brief Flags management functions * @verbatim =============================================================================== Flags management functions =============================================================================== @endverbatim * @{ */ /** * @brief Checks whether the specified PWR flag is set or not. * @param PWR_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event * was received from the WKUP pin or from the RTC alarm (Alarm A * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup. * An additional wakeup event is detected if the WKUP pin is enabled * (by setting the EWUP bit) when the WKUP pin level is already high. * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was * resumed from StandBy mode. * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled * by the PWR_PVDCmd() function. The PVD is stopped by Standby mode * For this reason, this bit is equal to 0 after Standby or reset * until the PVDE bit is set. * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset * when the device wakes up from Standby mode or by a system reset * or power reset. * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage * scaling output selection is ready. * @retval The new state of PWR_FLAG (SET or RESET). */ FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } /* Return the flag status */ return bitstatus; } /** * @brief Clears the PWR's pending flags. * @param PWR_FLAG: specifies the flag to clear. * This parameter can be one of the following values: * @arg PWR_FLAG_WU: Wake Up flag * @arg PWR_FLAG_SB: StandBy flag * @retval None */ void PWR_ClearFlag(uint32_t PWR_FLAG) { /* Check the parameters */ assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); PWR->CR |= PWR_FLAG << 2; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c ================================================ /** ****************************************************************************** * @file stm32f4xx_rcc.c * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file provides firmware functions to manage the following * functionalities of the Reset and clock control (RCC) peripheral: * - Internal/external clocks, PLL, CSS and MCO configuration * - System, AHB and APB busses clocks configuration * - Peripheral clocks configuration * - Interrupts and flags management * * @verbatim * * =================================================================== * RCC specific features * =================================================================== * * After reset the device is running from Internal High Speed oscillator * (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache * and I-Cache are disabled, and all peripherals are off except internal * SRAM, Flash and JTAG. * - There is no prescaler on High speed (AHB) and Low speed (APB) busses; * all peripherals mapped on these busses are running at HSI speed. * - The clock for all peripherals is switched off, except the SRAM and FLASH. * - All GPIOs are in input floating state, except the JTAG pins which * are assigned to be used for debug purpose. * * Once the device started from reset, the user application has to: * - Configure the clock source to be used to drive the System clock * (if the application needs higher frequency/performance) * - Configure the System clock frequency and Flash settings * - Configure the AHB and APB busses prescalers * - Enable the clock for the peripheral(s) to be used * - Configure the clock source(s) for peripherals which clocks are not * derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) * * @endverbatim * ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup RCC * @brief RCC driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* ------------ RCC registers bit address in the alias region ----------- */ #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) /* --- CR Register ---*/ /* Alias word address of HSION bit */ #define CR_OFFSET (RCC_OFFSET + 0x00) #define HSION_BitNumber 0x00 #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) /* Alias word address of CSSON bit */ #define CSSON_BitNumber 0x13 #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) /* Alias word address of PLLON bit */ #define PLLON_BitNumber 0x18 #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) /* Alias word address of PLLI2SON bit */ #define PLLI2SON_BitNumber 0x1A #define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4)) /* --- CFGR Register ---*/ /* Alias word address of I2SSRC bit */ #define CFGR_OFFSET (RCC_OFFSET + 0x08) #define I2SSRC_BitNumber 0x17 #define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4)) /* --- BDCR Register ---*/ /* Alias word address of RTCEN bit */ #define BDCR_OFFSET (RCC_OFFSET + 0x70) #define RTCEN_BitNumber 0x0F #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) /* Alias word address of BDRST bit */ #define BDRST_BitNumber 0x10 #define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) /* --- CSR Register ---*/ /* Alias word address of LSION bit */ #define CSR_OFFSET (RCC_OFFSET + 0x74) #define LSION_BitNumber 0x00 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) /* ---------------------- RCC registers bit mask ------------------------ */ /* CFGR register bit mask */ #define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF) #define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF) /* RCC Flag Mask */ #define FLAG_MASK ((uint8_t)0x1F) /* CR register byte 3 (Bits[23:16]) base address */ #define CR_BYTE3_ADDRESS ((uint32_t)0x40023802) /* CIR register byte 2 (Bits[15:8]) base address */ #define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01)) /* CIR register byte 3 (Bits[23:16]) base address */ #define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02)) /* BDCR register base address */ #define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup RCC_Private_Functions * @{ */ /** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions * @brief Internal and external clocks, PLL, CSS and MCO configuration functions * @verbatim =============================================================================== Internal/external clocks, PLL, CSS and MCO configuration functions =============================================================================== This section provide functions allowing to configure the internal/external clocks, PLLs, CSS and MCO pins. 1. HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through the PLL as System clock source. 2. LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC clock source. 3. HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or through the PLL as System clock source. Can be used also as RTC clock source. 4. LSE (low-speed external), 32 KHz oscillator used as RTC clock source. 5. PLL (clocked by HSI or HSE), featuring two different output clocks: - The first output is used to generate the high speed system clock (up to 168 MHz) - The second output is used to generate the clock for the USB OTG FS (48 MHz), the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). 6. PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve high-quality audio performance on the I2S interface. 7. CSS (Clock security system), once enable and if a HSE clock failure occurs (HSE used directly or through PLL as System clock source), the System clock is automatically switched to HSI and an interrupt is generated if enabled. The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. 8. MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL clock (through a configurable prescaler) on PA8 pin. 9. MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S clock (through a configurable prescaler) on PC9 pin. @endverbatim * @{ */ /** * @brief Resets the RCC clock configuration to the default reset state. * @note The default reset state of the clock configuration is given below: * - HSI ON and used as system clock source * - HSE, PLL and PLLI2S OFF * - AHB, APB1 and APB2 prescaler set to 1. * - CSS, MCO1 and MCO2 OFF * - All interrupts disabled * @note This function doesn't modify the configuration of the * - Peripheral clocks * - LSI, LSE and RTC clocks * @param None * @retval None */ void RCC_DeInit(void) { /* Set HSION bit */ RCC->CR |= (uint32_t)0x00000001; /* Reset CFGR register */ RCC->CFGR = 0x00000000; /* Reset HSEON, CSSON and PLLON bits */ RCC->CR &= (uint32_t)0xFEF6FFFF; /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x24003010; /* Reset HSEBYP bit */ RCC->CR &= (uint32_t)0xFFFBFFFF; /* Disable all interrupts */ RCC->CIR = 0x00000000; } /** * @brief Configures the External High Speed oscillator (HSE). * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application * software should wait on HSERDY flag to be set indicating that HSE clock * is stable and can be used to clock the PLL and/or system clock. * @note HSE state can not be changed if it is used directly or through the * PLL as system clock. In this case, you have to select another source * of the system clock then change the HSE state (ex. disable it). * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. * @note This function reset the CSSON bit, so if the Clock security system(CSS) * was previously enabled you have to enable it again after calling this * function. * @param RCC_HSE: specifies the new state of the HSE. * This parameter can be one of the following values: * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after * 6 HSE oscillator clock cycles. * @arg RCC_HSE_ON: turn ON the HSE oscillator * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock * @retval None */ void RCC_HSEConfig(uint8_t RCC_HSE) { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_HSE)); /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF; /* Set the new HSE configuration -------------------------------------------*/ *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE; } /** * @brief Waits for HSE start-up. * @note This functions waits on HSERDY flag to be set and return SUCCESS if * this flag is set, otherwise returns ERROR if the timeout is reached * and this flag is not set. The timeout value is defined by the constant * HSE_STARTUP_TIMEOUT in stm32f4xx.h file. You can tailor it depending * on the HSE crystal used in your application. * @param None * @retval An ErrorStatus enumeration value: * - SUCCESS: HSE oscillator is stable and ready to use * - ERROR: HSE oscillator not yet ready */ ErrorStatus RCC_WaitForHSEStartUp(void) { __IO uint32_t startupcounter = 0; ErrorStatus status = ERROR; FlagStatus hsestatus = RESET; /* Wait till HSE is ready and if Time out is reached exit */ do { hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); startupcounter++; } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET)); if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) { status = SUCCESS; } else { status = ERROR; } return (status); } /** * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. * @note The calibration is used to compensate for the variations in voltage * and temperature that influence the frequency of the internal HSI RC. * @param HSICalibrationValue: specifies the calibration trimming value. * This parameter must be a number between 0 and 0x1F. * @retval None */ void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); tmpreg = RCC->CR; /* Clear HSITRIM[4:0] bits */ tmpreg &= ~RCC_CR_HSITRIM; /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ tmpreg |= (uint32_t)HSICalibrationValue << 3; /* Store the new value */ RCC->CR = tmpreg; } /** * @brief Enables or disables the Internal High Speed oscillator (HSI). * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. * It is used (enabled by hardware) as system clock source after startup * from Reset, wakeup from STOP and STANDBY mode, or in case of failure * of the HSE used directly or indirectly as system clock (if the Clock * Security System CSS is enabled). * @note HSI can not be stopped if it is used as system clock source. In this case, * you have to select another source of the system clock then stop the HSI. * @note After enabling the HSI, the application software should wait on HSIRDY * flag to be set indicating that HSI clock is stable and can be used as * system clock source. * @param NewState: new state of the HSI. * This parameter can be: ENABLE or DISABLE. * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator * clock cycles. * @retval None */ void RCC_HSICmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; } /** * @brief Configures the External Low Speed oscillator (LSE). * @note As the LSE is in the Backup domain and write access is denied to * this domain after reset, you have to enable write access using * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE * (to be done once after reset). * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application * software should wait on LSERDY flag to be set indicating that LSE clock * is stable and can be used to clock the RTC. * @param RCC_LSE: specifies the new state of the LSE. * This parameter can be one of the following values: * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after * 6 LSE oscillator clock cycles. * @arg RCC_LSE_ON: turn ON the LSE oscillator * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock * @retval None */ void RCC_LSEConfig(uint8_t RCC_LSE) { /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_LSE)); /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ /* Reset LSEON bit */ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; /* Reset LSEBYP bit */ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ switch (RCC_LSE) { case RCC_LSE_ON: /* Set LSEON bit */ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON; break; case RCC_LSE_Bypass: /* Set LSEBYP and LSEON bits */ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; break; default: break; } } /** * @brief Enables or disables the Internal Low Speed oscillator (LSI). * @note After enabling the LSI, the application software should wait on * LSIRDY flag to be set indicating that LSI clock is stable and can * be used to clock the IWDG and/or the RTC. * @note LSI can not be disabled if the IWDG is running. * @param NewState: new state of the LSI. * This parameter can be: ENABLE or DISABLE. * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator * clock cycles. * @retval None */ void RCC_LSICmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; } /** * @brief Configures the main PLL clock source, multiplication and division factors. * @note This function must be used only when the main PLL is disabled. * * @param RCC_PLLSource: specifies the PLL entry clock source. * This parameter can be one of the following values: * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. * * @param PLLM: specifies the division factor for PLL VCO input clock * This parameter must be a number between 0 and 63. * @note You have to set the PLLM parameter correctly to ensure that the VCO input * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency * of 2 MHz to limit PLL jitter. * * @param PLLN: specifies the multiplication factor for PLL VCO output clock * This parameter must be a number between 192 and 432. * @note You have to set the PLLN parameter correctly to ensure that the VCO * output frequency is between 192 and 432 MHz. * * @param PLLP: specifies the division factor for main system clock (SYSCLK) * This parameter must be a number in the range {2, 4, 6, or 8}. * @note You have to set the PLLP parameter correctly to not exceed 168 MHz on * the System clock frequency. * * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks * This parameter must be a number between 4 and 15. * @note If the USB OTG FS is used in your application, you have to set the * PLLQ parameter correctly to have 48 MHz clock for the USB. However, * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work * correctly. * * @retval None */ void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ) { /* Check the parameters */ assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); assert_param(IS_RCC_PLLM_VALUE(PLLM)); assert_param(IS_RCC_PLLN_VALUE(PLLN)); assert_param(IS_RCC_PLLP_VALUE(PLLP)); assert_param(IS_RCC_PLLQ_VALUE(PLLQ)); RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) | (PLLQ << 24); } /** * @brief Enables or disables the main PLL. * @note After enabling the main PLL, the application software should wait on * PLLRDY flag to be set indicating that PLL clock is stable and can * be used as system clock source. * @note The main PLL can not be disabled if it is used as system clock source * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. * @param NewState: new state of the main PLL. This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_PLLCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; } /** * @brief Configures the PLLI2S clock multiplication and division factors. * * @note This function must be used only when the PLLI2S is disabled. * @note PLLI2S clock source is common with the main PLL (configured in * RCC_PLLConfig function ) * * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock * This parameter must be a number between 192 and 432. * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO * output frequency is between 192 and 432 MHz. * * @param PLLI2SR: specifies the division factor for I2S clock * This parameter must be a number between 2 and 7. * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz * on the I2S clock frequency. * * @retval None */ void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR) { /* Check the parameters */ assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN)); assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR)); RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28); } /** * @brief Enables or disables the PLLI2S. * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. * @param NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_PLLI2SCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState; } /** * @brief Enables or disables the Clock Security System. * @note If a failure is detected on the HSE oscillator clock, this oscillator * is automatically disabled and an interrupt is generated to inform the * software about the failure (Clock Security System Interrupt, CSSI), * allowing the MCU to perform rescue operations. The CSSI is linked to * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. * @param NewState: new state of the Clock Security System. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_ClockSecuritySystemCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; } /** * @brief Selects the clock source to output on MCO1 pin(PA8). * @note PA8 should be configured in alternate function mode. * @param RCC_MCO1Source: specifies the clock source to output. * This parameter can be one of the following values: * @arg RCC_MCO1Source_HSI: HSI clock selected as MCO1 source * @arg RCC_MCO1Source_LSE: LSE clock selected as MCO1 source * @arg RCC_MCO1Source_HSE: HSE clock selected as MCO1 source * @arg RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source * @param RCC_MCO1Div: specifies the MCO1 prescaler. * This parameter can be one of the following values: * @arg RCC_MCO1Div_1: no division applied to MCO1 clock * @arg RCC_MCO1Div_2: division by 2 applied to MCO1 clock * @arg RCC_MCO1Div_3: division by 3 applied to MCO1 clock * @arg RCC_MCO1Div_4: division by 4 applied to MCO1 clock * @arg RCC_MCO1Div_5: division by 5 applied to MCO1 clock * @retval None */ void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source)); assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div)); tmpreg = RCC->CFGR; /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */ tmpreg &= CFGR_MCO1_RESET_MASK; /* Select MCO1 clock source and prescaler */ tmpreg |= RCC_MCO1Source | RCC_MCO1Div; /* Store the new value */ RCC->CFGR = tmpreg; } /** * @brief Selects the clock source to output on MCO2 pin(PC9). * @note PC9 should be configured in alternate function mode. * @param RCC_MCO2Source: specifies the clock source to output. * This parameter can be one of the following values: * @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source * @arg RCC_MCO2Source_PLLI2SCLK: PLLI2S clock selected as MCO2 source * @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source * @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source * @param RCC_MCO2Div: specifies the MCO2 prescaler. * This parameter can be one of the following values: * @arg RCC_MCO2Div_1: no division applied to MCO2 clock * @arg RCC_MCO2Div_2: division by 2 applied to MCO2 clock * @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock * @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock * @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock * @retval None */ void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source)); assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div)); tmpreg = RCC->CFGR; /* Clear MCO2 and MCO2PRE[2:0] bits */ tmpreg &= CFGR_MCO2_RESET_MASK; /* Select MCO2 clock source and prescaler */ tmpreg |= RCC_MCO2Source | RCC_MCO2Div; /* Store the new value */ RCC->CFGR = tmpreg; } /** * @} */ /** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions * @brief System, AHB and APB busses clocks configuration functions * @verbatim =============================================================================== System, AHB and APB busses clocks configuration functions =============================================================================== This section provide functions allowing to configure the System, AHB, APB1 and APB2 busses clocks. 1. Several clock sources can be used to drive the System clock (SYSCLK): HSI, HSE and PLL. The AHB clock (HCLK) is derived from System clock through configurable prescaler and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through configurable prescalers and used to clock the peripherals mapped on these busses. You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks. @note All the peripheral clocks are derived from the System clock (SYSCLK) except: - I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or from an external clock mapped on the I2S_CKIN pin. You have to use RCC_I2SCLKConfig() function to configure this clock. - RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd() functions to configure this clock. - USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz to work correctly, while the SDIO require a frequency equal or lower than to 48. This clock is derived of the main PLL through PLLQ divider. - IWDG clock which is always the LSI clock. 2. The maximum frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 82 MHz and PCLK1 42 MHz. Depending on the device voltage range, the maximum frequency should be adapted accordingly: +-------------------------------------------------------------------------------------+ | Latency | HCLK clock frequency (MHz) | | |---------------------------------------------------------------------| | | voltage range | voltage range | voltage range | voltage range | | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | |---------------|----------------|----------------|-----------------|-----------------| |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 | |---------------|----------------|----------------|-----------------|-----------------| |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 | |---------------|----------------|----------------|-----------------|-----------------| |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 | |---------------|----------------|----------------|-----------------|-----------------| |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 | |---------------|----------------|----------------|-----------------|-----------------| |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 | |---------------|----------------|----------------|-----------------|-----------------| |5WS(6CPU cycle)|120< HCLK <= 168|120< HCLK <= 144|90 < HCLK <= 108 |80 < HCLK <= 96 | |---------------|----------------|----------------|-----------------|-----------------| |6WS(7CPU cycle)| NA |144< HCLK <= 168|108 < HCLK <= 120|96 < HCLK <= 112 | |---------------|----------------|----------------|-----------------|-----------------| |7WS(8CPU cycle)| NA | NA |120 < HCLK <= 138|112 < HCLK <= 120| +-------------------------------------------------------------------------------------+ @note When VOS bit (in PWR_CR register) is reset to '0, the maximum value of HCLK is 144 MHz. You can use PWR_MainRegulatorModeConfig() function to set or reset this bit. @endverbatim * @{ */ /** * @brief Configures the system clock (SYSCLK). * @note The HSI is used (enabled by hardware) as system clock source after * startup from Reset, wake-up from STOP and STANDBY mode, or in case * of failure of the HSE used directly or indirectly as system clock * (if the Clock Security System CSS is enabled). * @note A switch from one clock source to another occurs only if the target * clock source is ready (clock stable after startup delay or PLL locked). * If a clock source which is not yet ready is selected, the switch will * occur when the clock source will be ready. * You can use RCC_GetSYSCLKSource() function to know which clock is * currently used as system clock source. * @param RCC_SYSCLKSource: specifies the clock source used as system clock. * This parameter can be one of the following values: * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source * @retval None */ void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); tmpreg = RCC->CFGR; /* Clear SW[1:0] bits */ tmpreg &= ~RCC_CFGR_SW; /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ tmpreg |= RCC_SYSCLKSource; /* Store the new value */ RCC->CFGR = tmpreg; } /** * @brief Returns the clock source used as system clock. * @param None * @retval The clock source used as system clock. The returned value can be one * of the following: * - 0x00: HSI used as system clock * - 0x04: HSE used as system clock * - 0x08: PLL used as system clock */ uint8_t RCC_GetSYSCLKSource(void) { return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS)); } /** * @brief Configures the AHB clock (HCLK). * @note Depending on the device voltage range, the software has to set correctly * these bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above * "CPU, AHB and APB busses clocks configuration functions") * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from * the system clock (SYSCLK). * This parameter can be one of the following values: * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 * @retval None */ void RCC_HCLKConfig(uint32_t RCC_SYSCLK) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RCC_HCLK(RCC_SYSCLK)); tmpreg = RCC->CFGR; /* Clear HPRE[3:0] bits */ tmpreg &= ~RCC_CFGR_HPRE; /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ tmpreg |= RCC_SYSCLK; /* Store the new value */ RCC->CFGR = tmpreg; } /** * @brief Configures the Low Speed APB clock (PCLK1). * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from * the AHB clock (HCLK). * This parameter can be one of the following values: * @arg RCC_HCLK_Div1: APB1 clock = HCLK * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 * @retval None */ void RCC_PCLK1Config(uint32_t RCC_HCLK) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RCC_PCLK(RCC_HCLK)); tmpreg = RCC->CFGR; /* Clear PPRE1[2:0] bits */ tmpreg &= ~RCC_CFGR_PPRE1; /* Set PPRE1[2:0] bits according to RCC_HCLK value */ tmpreg |= RCC_HCLK; /* Store the new value */ RCC->CFGR = tmpreg; } /** * @brief Configures the High Speed APB clock (PCLK2). * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from * the AHB clock (HCLK). * This parameter can be one of the following values: * @arg RCC_HCLK_Div1: APB2 clock = HCLK * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 * @retval None */ void RCC_PCLK2Config(uint32_t RCC_HCLK) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RCC_PCLK(RCC_HCLK)); tmpreg = RCC->CFGR; /* Clear PPRE2[2:0] bits */ tmpreg &= ~RCC_CFGR_PPRE2; /* Set PPRE2[2:0] bits according to RCC_HCLK value */ tmpreg |= RCC_HCLK << 3; /* Store the new value */ RCC->CFGR = tmpreg; } /** * @brief Returns the frequencies of different on chip clocks; SYSCLK, HCLK, * PCLK1 and PCLK2. * * @note The system frequency computed by this function is not the real * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) * or HSI_VALUE(*) multiplied/divided by the PLL factors. * @note (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value * 16 MHz) but the real value may vary depending on the variations * in voltage and temperature. * @note (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value * 25 MHz), user has to ensure that HSE_VALUE is same as the real * frequency of the crystal used. Otherwise, this function may * have wrong result. * * @note The result of this function could be not correct when using fractional * value for HSE crystal. * * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold * the clocks frequencies. * * @note This function can be used by the user application to compute the * baudrate for the communication peripherals or configure other parameters. * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function * must be called to update the structure's field. Otherwise, any * configuration based on this function will be incorrect. * * @retval None */ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) { uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; switch (tmp) { case 0x00: /* HSI used as system clock source */ RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; break; case 0x04: /* HSE used as system clock source */ RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; break; case 0x08: /* PLL used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLP */ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; if (pllsource != 0) { /* HSE used as PLL clock source */ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); } else { /* HSI used as PLL clock source */ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); } pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; RCC_Clocks->SYSCLK_Frequency = pllvco/pllp; break; default: RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; break; } /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/ /* Get HCLK prescaler */ tmp = RCC->CFGR & RCC_CFGR_HPRE; tmp = tmp >> 4; presc = APBAHBPrescTable[tmp]; /* HCLK clock frequency */ RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; /* Get PCLK1 prescaler */ tmp = RCC->CFGR & RCC_CFGR_PPRE1; tmp = tmp >> 10; presc = APBAHBPrescTable[tmp]; /* PCLK1 clock frequency */ RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; /* Get PCLK2 prescaler */ tmp = RCC->CFGR & RCC_CFGR_PPRE2; tmp = tmp >> 13; presc = APBAHBPrescTable[tmp]; /* PCLK2 clock frequency */ RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; } /** * @} */ /** @defgroup RCC_Group3 Peripheral clocks configuration functions * @brief Peripheral clocks configuration functions * @verbatim =============================================================================== Peripheral clocks configuration functions =============================================================================== This section provide functions allowing to configure the Peripheral clocks. 1. The RTC clock which is derived from the LSI, LSE or HSE clock divided by 2 to 31. 2. After restart from Reset or wakeup from STANDBY, all peripherals are off except internal SRAM, Flash and JTAG. Before to start using a peripheral you have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd() , RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions. 3. To reset the peripherals configuration (to the default state after device reset) you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and RCC_APB1PeriphResetCmd() functions. 4. To further reduce power consumption in SLEEP mode the peripheral clocks can be disabled prior to executing the WFI or WFE instructions. You can do this using RCC_AHBPeriphClockLPModeCmd(), RCC_APB2PeriphClockLPModeCmd() and RCC_APB1PeriphClockLPModeCmd() functions. @endverbatim * @{ */ /** * @brief Configures the RTC clock (RTCCLK). * @note As the RTC clock configuration bits are in the Backup domain and write * access is denied to this domain after reset, you have to enable write * access using PWR_BackupAccessCmd(ENABLE) function before to configure * the RTC clock source (to be done once after reset). * @note Once the RTC clock is configured it can't be changed unless the * Backup domain is reset using RCC_BackupResetCmd() function, or by * a Power On Reset (POR). * * @param RCC_RTCCLKSource: specifies the RTC clock source. * This parameter can be one of the following values: * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock * @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected * as RTC clock, where x:[2,31] * * @note If the LSE or LSI is used as RTC clock source, the RTC continues to * work in STOP and STANDBY modes, and can be used as wakeup source. * However, when the HSE clock is used as RTC clock source, the RTC * cannot be used in STOP and STANDBY modes. * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as * RTC clock source). * * @retval None */ void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300) { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */ tmpreg = RCC->CFGR; /* Clear RTCPRE[4:0] bits */ tmpreg &= ~RCC_CFGR_RTCPRE; /* Configure HSE division factor for RTC clock */ tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF); /* Store the new value */ RCC->CFGR = tmpreg; } /* Select the RTC clock source */ RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF); } /** * @brief Enables or disables the RTC clock. * @note This function must be used only after the RTC clock source was selected * using the RCC_RTCCLKConfig function. * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_RTCCLKCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; } /** * @brief Forces or releases the Backup domain reset. * @note This function resets the RTC peripheral (including the backup registers) * and the RTC clock source selection in RCC_CSR register. * @note The BKPSRAM is not affected by this reset. * @param NewState: new state of the Backup domain reset. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_BackupResetCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; } /** * @brief Configures the I2S clock source (I2SCLK). * @note This function must be called before enabling the I2S APB clock. * @param RCC_I2SCLKSource: specifies the I2S clock source. * This parameter can be one of the following values: * @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin * used as I2S clock source * @retval None */ void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource) { /* Check the parameters */ assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource)); *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource; } /** * @brief Enables or disables the AHB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock. * This parameter can be any combination of the following values: * @arg RCC_AHB1Periph_GPIOA: GPIOA clock * @arg RCC_AHB1Periph_GPIOB: GPIOB clock * @arg RCC_AHB1Periph_GPIOC: GPIOC clock * @arg RCC_AHB1Periph_GPIOD: GPIOD clock * @arg RCC_AHB1Periph_GPIOE: GPIOE clock * @arg RCC_AHB1Periph_GPIOF: GPIOF clock * @arg RCC_AHB1Periph_GPIOG: GPIOG clock * @arg RCC_AHB1Periph_GPIOG: GPIOG clock * @arg RCC_AHB1Periph_GPIOI: GPIOI clock * @arg RCC_AHB1Periph_CRC: CRC clock * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock * @arg RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock * @arg RCC_AHB1Periph_DMA1: DMA1 clock * @arg RCC_AHB1Periph_DMA2: DMA2 clock * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { RCC->AHB1ENR |= RCC_AHB1Periph; } else { RCC->AHB1ENR &= ~RCC_AHB1Periph; } } /** * @brief Enables or disables the AHB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock. * This parameter can be any combination of the following values: * @arg RCC_AHB2Periph_DCMI: DCMI clock * @arg RCC_AHB2Periph_CRYP: CRYP clock * @arg RCC_AHB2Periph_HASH: HASH clock * @arg RCC_AHB2Periph_RNG: RNG clock * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { RCC->AHB2ENR |= RCC_AHB2Periph; } else { RCC->AHB2ENR &= ~RCC_AHB2Periph; } } /** * @brief Enables or disables the AHB3 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. * This parameter must be: RCC_AHB3Periph_FSMC * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { RCC->AHB3ENR |= RCC_AHB3Periph; } else { RCC->AHB3ENR &= ~RCC_AHB3Periph; } } /** * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. * This parameter can be any combination of the following values: * @arg RCC_APB1Periph_TIM2: TIM2 clock * @arg RCC_APB1Periph_TIM3: TIM3 clock * @arg RCC_APB1Periph_TIM4: TIM4 clock * @arg RCC_APB1Periph_TIM5: TIM5 clock * @arg RCC_APB1Periph_TIM6: TIM6 clock * @arg RCC_APB1Periph_TIM7: TIM7 clock * @arg RCC_APB1Periph_TIM12: TIM12 clock * @arg RCC_APB1Periph_TIM13: TIM13 clock * @arg RCC_APB1Periph_TIM14: TIM14 clock * @arg RCC_APB1Periph_WWDG: WWDG clock * @arg RCC_APB1Periph_SPI2: SPI2 clock * @arg RCC_APB1Periph_SPI3: SPI3 clock * @arg RCC_APB1Periph_USART2: USART2 clock * @arg RCC_APB1Periph_USART3: USART3 clock * @arg RCC_APB1Periph_UART4: UART4 clock * @arg RCC_APB1Periph_UART5: UART5 clock * @arg RCC_APB1Periph_I2C1: I2C1 clock * @arg RCC_APB1Periph_I2C2: I2C2 clock * @arg RCC_APB1Periph_I2C3: I2C3 clock * @arg RCC_APB1Periph_CAN1: CAN1 clock * @arg RCC_APB1Periph_CAN2: CAN2 clock * @arg RCC_APB1Periph_PWR: PWR clock * @arg RCC_APB1Periph_DAC: DAC clock * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { RCC->APB1ENR |= RCC_APB1Periph; } else { RCC->APB1ENR &= ~RCC_APB1Periph; } } /** * @brief Enables or disables the High Speed APB (APB2) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. * This parameter can be any combination of the following values: * @arg RCC_APB2Periph_TIM1: TIM1 clock * @arg RCC_APB2Periph_TIM8: TIM8 clock * @arg RCC_APB2Periph_USART1: USART1 clock * @arg RCC_APB2Periph_USART6: USART6 clock * @arg RCC_APB2Periph_ADC1: ADC1 clock * @arg RCC_APB2Periph_ADC2: ADC2 clock * @arg RCC_APB2Periph_ADC3: ADC3 clock * @arg RCC_APB2Periph_SDIO: SDIO clock * @arg RCC_APB2Periph_SPI1: SPI1 clock * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock * @arg RCC_APB2Periph_TIM9: TIM9 clock * @arg RCC_APB2Periph_TIM10: TIM10 clock * @arg RCC_APB2Periph_TIM11: TIM11 clock * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { RCC->APB2ENR |= RCC_APB2Periph; } else { RCC->APB2ENR &= ~RCC_APB2Periph; } } /** * @brief Forces or releases AHB1 peripheral reset. * @param RCC_AHB1Periph: specifies the AHB1 peripheral to reset. * This parameter can be any combination of the following values: * @arg RCC_AHB1Periph_GPIOA: GPIOA clock * @arg RCC_AHB1Periph_GPIOB: GPIOB clock * @arg RCC_AHB1Periph_GPIOC: GPIOC clock * @arg RCC_AHB1Periph_GPIOD: GPIOD clock * @arg RCC_AHB1Periph_GPIOE: GPIOE clock * @arg RCC_AHB1Periph_GPIOF: GPIOF clock * @arg RCC_AHB1Periph_GPIOG: GPIOG clock * @arg RCC_AHB1Periph_GPIOG: GPIOG clock * @arg RCC_AHB1Periph_GPIOI: GPIOI clock * @arg RCC_AHB1Periph_CRC: CRC clock * @arg RCC_AHB1Periph_DMA1: DMA1 clock * @arg RCC_AHB1Periph_DMA2: DMA2 clock * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock * * @param NewState: new state of the specified peripheral reset. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { RCC->AHB1RSTR |= RCC_AHB1Periph; } else { RCC->AHB1RSTR &= ~RCC_AHB1Periph; } } /** * @brief Forces or releases AHB2 peripheral reset. * @param RCC_AHB2Periph: specifies the AHB2 peripheral to reset. * This parameter can be any combination of the following values: * @arg RCC_AHB2Periph_DCMI: DCMI clock * @arg RCC_AHB2Periph_CRYP: CRYP clock * @arg RCC_AHB2Periph_HASH: HASH clock * @arg RCC_AHB2Periph_RNG: RNG clock * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock * @param NewState: new state of the specified peripheral reset. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { RCC->AHB2RSTR |= RCC_AHB2Periph; } else { RCC->AHB2RSTR &= ~RCC_AHB2Periph; } } /** * @brief Forces or releases AHB3 peripheral reset. * @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset. * This parameter must be: RCC_AHB3Periph_FSMC * @param NewState: new state of the specified peripheral reset. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { RCC->AHB3RSTR |= RCC_AHB3Periph; } else { RCC->AHB3RSTR &= ~RCC_AHB3Periph; } } /** * @brief Forces or releases Low Speed APB (APB1) peripheral reset. * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. * This parameter can be any combination of the following values: * @arg RCC_APB1Periph_TIM2: TIM2 clock * @arg RCC_APB1Periph_TIM3: TIM3 clock * @arg RCC_APB1Periph_TIM4: TIM4 clock * @arg RCC_APB1Periph_TIM5: TIM5 clock * @arg RCC_APB1Periph_TIM6: TIM6 clock * @arg RCC_APB1Periph_TIM7: TIM7 clock * @arg RCC_APB1Periph_TIM12: TIM12 clock * @arg RCC_APB1Periph_TIM13: TIM13 clock * @arg RCC_APB1Periph_TIM14: TIM14 clock * @arg RCC_APB1Periph_WWDG: WWDG clock * @arg RCC_APB1Periph_SPI2: SPI2 clock * @arg RCC_APB1Periph_SPI3: SPI3 clock * @arg RCC_APB1Periph_USART2: USART2 clock * @arg RCC_APB1Periph_USART3: USART3 clock * @arg RCC_APB1Periph_UART4: UART4 clock * @arg RCC_APB1Periph_UART5: UART5 clock * @arg RCC_APB1Periph_I2C1: I2C1 clock * @arg RCC_APB1Periph_I2C2: I2C2 clock * @arg RCC_APB1Periph_I2C3: I2C3 clock * @arg RCC_APB1Periph_CAN1: CAN1 clock * @arg RCC_APB1Periph_CAN2: CAN2 clock * @arg RCC_APB1Periph_PWR: PWR clock * @arg RCC_APB1Periph_DAC: DAC clock * @param NewState: new state of the specified peripheral reset. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { RCC->APB1RSTR |= RCC_APB1Periph; } else { RCC->APB1RSTR &= ~RCC_APB1Periph; } } /** * @brief Forces or releases High Speed APB (APB2) peripheral reset. * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. * This parameter can be any combination of the following values: * @arg RCC_APB2Periph_TIM1: TIM1 clock * @arg RCC_APB2Periph_TIM8: TIM8 clock * @arg RCC_APB2Periph_USART1: USART1 clock * @arg RCC_APB2Periph_USART6: USART6 clock * @arg RCC_APB2Periph_ADC1: ADC1 clock * @arg RCC_APB2Periph_ADC2: ADC2 clock * @arg RCC_APB2Periph_ADC3: ADC3 clock * @arg RCC_APB2Periph_SDIO: SDIO clock * @arg RCC_APB2Periph_SPI1: SPI1 clock * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock * @arg RCC_APB2Periph_TIM9: TIM9 clock * @arg RCC_APB2Periph_TIM10: TIM10 clock * @arg RCC_APB2Periph_TIM11: TIM11 clock * @param NewState: new state of the specified peripheral reset. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { RCC->APB2RSTR |= RCC_APB2Periph; } else { RCC->APB2RSTR &= ~RCC_APB2Periph; } } /** * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock. * This parameter can be any combination of the following values: * @arg RCC_AHB1Periph_GPIOA: GPIOA clock * @arg RCC_AHB1Periph_GPIOB: GPIOB clock * @arg RCC_AHB1Periph_GPIOC: GPIOC clock * @arg RCC_AHB1Periph_GPIOD: GPIOD clock * @arg RCC_AHB1Periph_GPIOE: GPIOE clock * @arg RCC_AHB1Periph_GPIOF: GPIOF clock * @arg RCC_AHB1Periph_GPIOG: GPIOG clock * @arg RCC_AHB1Periph_GPIOG: GPIOG clock * @arg RCC_AHB1Periph_GPIOI: GPIOI clock * @arg RCC_AHB1Periph_CRC: CRC clock * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock * @arg RCC_AHB1Periph_DMA1: DMA1 clock * @arg RCC_AHB1Periph_DMA2: DMA2 clock * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { RCC->AHB1LPENR |= RCC_AHB1Periph; } else { RCC->AHB1LPENR &= ~RCC_AHB1Periph; } } /** * @brief Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock. * This parameter can be any combination of the following values: * @arg RCC_AHB2Periph_DCMI: DCMI clock * @arg RCC_AHB2Periph_CRYP: CRYP clock * @arg RCC_AHB2Periph_HASH: HASH clock * @arg RCC_AHB2Periph_RNG: RNG clock * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { RCC->AHB2LPENR |= RCC_AHB2Periph; } else { RCC->AHB2LPENR &= ~RCC_AHB2Periph; } } /** * @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. * This parameter must be: RCC_AHB3Periph_FSMC * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { RCC->AHB3LPENR |= RCC_AHB3Periph; } else { RCC->AHB3LPENR &= ~RCC_AHB3Periph; } } /** * @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. * This parameter can be any combination of the following values: * @arg RCC_APB1Periph_TIM2: TIM2 clock * @arg RCC_APB1Periph_TIM3: TIM3 clock * @arg RCC_APB1Periph_TIM4: TIM4 clock * @arg RCC_APB1Periph_TIM5: TIM5 clock * @arg RCC_APB1Periph_TIM6: TIM6 clock * @arg RCC_APB1Periph_TIM7: TIM7 clock * @arg RCC_APB1Periph_TIM12: TIM12 clock * @arg RCC_APB1Periph_TIM13: TIM13 clock * @arg RCC_APB1Periph_TIM14: TIM14 clock * @arg RCC_APB1Periph_WWDG: WWDG clock * @arg RCC_APB1Periph_SPI2: SPI2 clock * @arg RCC_APB1Periph_SPI3: SPI3 clock * @arg RCC_APB1Periph_USART2: USART2 clock * @arg RCC_APB1Periph_USART3: USART3 clock * @arg RCC_APB1Periph_UART4: UART4 clock * @arg RCC_APB1Periph_UART5: UART5 clock * @arg RCC_APB1Periph_I2C1: I2C1 clock * @arg RCC_APB1Periph_I2C2: I2C2 clock * @arg RCC_APB1Periph_I2C3: I2C3 clock * @arg RCC_APB1Periph_CAN1: CAN1 clock * @arg RCC_APB1Periph_CAN2: CAN2 clock * @arg RCC_APB1Periph_PWR: PWR clock * @arg RCC_APB1Periph_DAC: DAC clock * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { RCC->APB1LPENR |= RCC_APB1Periph; } else { RCC->APB1LPENR &= ~RCC_APB1Periph; } } /** * @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. * This parameter can be any combination of the following values: * @arg RCC_APB2Periph_TIM1: TIM1 clock * @arg RCC_APB2Periph_TIM8: TIM8 clock * @arg RCC_APB2Periph_USART1: USART1 clock * @arg RCC_APB2Periph_USART6: USART6 clock * @arg RCC_APB2Periph_ADC1: ADC1 clock * @arg RCC_APB2Periph_ADC2: ADC2 clock * @arg RCC_APB2Periph_ADC3: ADC3 clock * @arg RCC_APB2Periph_SDIO: SDIO clock * @arg RCC_APB2Periph_SPI1: SPI1 clock * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock * @arg RCC_APB2Periph_TIM9: TIM9 clock * @arg RCC_APB2Periph_TIM10: TIM10 clock * @arg RCC_APB2Periph_TIM11: TIM11 clock * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { RCC->APB2LPENR |= RCC_APB2Periph; } else { RCC->APB2LPENR &= ~RCC_APB2Periph; } } /** * @} */ /** @defgroup RCC_Group4 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== Interrupts and flags management functions =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables the specified RCC interrupts. * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg RCC_IT_LSIRDY: LSI ready interrupt * @arg RCC_IT_LSERDY: LSE ready interrupt * @arg RCC_IT_HSIRDY: HSI ready interrupt * @arg RCC_IT_HSERDY: HSE ready interrupt * @arg RCC_IT_PLLRDY: main PLL ready interrupt * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt * @param NewState: new state of the specified RCC interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_IT(RCC_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */ *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; } else { /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */ *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; } } /** * @brief Checks whether the specified RCC flag is set or not. * @param RCC_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready * @arg RCC_FLAG_PLLRDY: main PLL clock ready * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset * @arg RCC_FLAG_PINRST: Pin reset * @arg RCC_FLAG_PORRST: POR/PDR reset * @arg RCC_FLAG_SFTRST: Software reset * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset * @arg RCC_FLAG_WWDGRST: Window Watchdog reset * @arg RCC_FLAG_LPWRRST: Low Power reset * @retval The new state of RCC_FLAG (SET or RESET). */ FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) { uint32_t tmp = 0; uint32_t statusreg = 0; FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_RCC_FLAG(RCC_FLAG)); /* Get the RCC register index */ tmp = RCC_FLAG >> 5; if (tmp == 1) /* The flag to check is in CR register */ { statusreg = RCC->CR; } else if (tmp == 2) /* The flag to check is in BDCR register */ { statusreg = RCC->BDCR; } else /* The flag to check is in CSR register */ { statusreg = RCC->CSR; } /* Get the flag position */ tmp = RCC_FLAG & FLAG_MASK; if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } /* Return the flag status */ return bitstatus; } /** * @brief Clears the RCC reset flags. * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST * @param None * @retval None */ void RCC_ClearFlag(void) { /* Set RMVF bit to clear the reset flags */ RCC->CSR |= RCC_CSR_RMVF; } /** * @brief Checks whether the specified RCC interrupt has occurred or not. * @param RCC_IT: specifies the RCC interrupt source to check. * This parameter can be one of the following values: * @arg RCC_IT_LSIRDY: LSI ready interrupt * @arg RCC_IT_LSERDY: LSE ready interrupt * @arg RCC_IT_HSIRDY: HSI ready interrupt * @arg RCC_IT_HSERDY: HSE ready interrupt * @arg RCC_IT_PLLRDY: main PLL ready interrupt * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt * @arg RCC_IT_CSS: Clock Security System interrupt * @retval The new state of RCC_IT (SET or RESET). */ ITStatus RCC_GetITStatus(uint8_t RCC_IT) { ITStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_RCC_GET_IT(RCC_IT)); /* Check the status of the specified RCC interrupt */ if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } /* Return the RCC_IT status */ return bitstatus; } /** * @brief Clears the RCC's interrupt pending bits. * @param RCC_IT: specifies the interrupt pending bit to clear. * This parameter can be any combination of the following values: * @arg RCC_IT_LSIRDY: LSI ready interrupt * @arg RCC_IT_LSERDY: LSE ready interrupt * @arg RCC_IT_HSIRDY: HSI ready interrupt * @arg RCC_IT_HSERDY: HSE ready interrupt * @arg RCC_IT_PLLRDY: main PLL ready interrupt * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt * @arg RCC_IT_CSS: Clock Security System interrupt * @retval None */ void RCC_ClearITPendingBit(uint8_t RCC_IT) { /* Check the parameters */ assert_param(IS_RCC_CLEAR_IT(RCC_IT)); /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt pending bits */ *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c ================================================ /** ****************************************************************************** * @file stm32f4xx_rng.c * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file provides firmware functions to manage the following * functionalities of the Random Number Generator (RNG) peripheral: * - Initialization and Configuration * - Get 32 bit Random number * - Interrupts and flags management * * @verbatim * * =================================================================== * How to use this driver * =================================================================== * 1. Enable The RNG controller clock using * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_RNG, ENABLE) function. * * 2. Activate the RNG peripheral using RNG_Cmd() function. * * 3. Wait until the 32 bit Random number Generator contains a valid * random data (using polling/interrupt mode). For more details, * refer to "Interrupts and flags management functions" module * description. * * 4. Get the 32 bit Random number using RNG_GetRandomNumber() function * * 5. To get another 32 bit Random number, go to step 3. * * * * @endverbatim * ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_rng.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup RNG * @brief RNG driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup RNG_Private_Functions * @{ */ /** @defgroup RNG_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== Initialization and Configuration functions =============================================================================== This section provides functions allowing to - Initialize the RNG peripheral - Enable or disable the RNG peripheral @endverbatim * @{ */ /** * @brief Deinitializes the RNG peripheral registers to their default reset values. * @param None * @retval None */ void RNG_DeInit(void) { /* Enable RNG reset state */ RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, ENABLE); /* Release RNG from reset state */ RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, DISABLE); } /** * @brief Enables or disables the RNG peripheral. * @param NewState: new state of the RNG peripheral. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RNG_Cmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the RNG */ RNG->CR |= RNG_CR_RNGEN; } else { /* Disable the RNG */ RNG->CR &= ~RNG_CR_RNGEN; } } /** * @} */ /** @defgroup RNG_Group2 Get 32 bit Random number function * @brief Get 32 bit Random number function * @verbatim =============================================================================== Get 32 bit Random number function =============================================================================== This section provides a function allowing to get the 32 bit Random number @note Before to call this function you have to wait till DRDY flag is set, using RNG_GetFlagStatus(RNG_FLAG_DRDY) function. @endverbatim * @{ */ /** * @brief Returns a 32-bit random number. * * @note Before to call this function you have to wait till DRDY (data ready) * flag is set, using RNG_GetFlagStatus(RNG_FLAG_DRDY) function. * @note Each time the the Random number data is read (using RNG_GetRandomNumber() * function), the RNG_FLAG_DRDY flag is automatically cleared. * @note In the case of a seed error, the generation of random numbers is * interrupted for as long as the SECS bit is '1'. If a number is * available in the RNG_DR register, it must not be used because it may * not have enough entropy. In this case, it is recommended to clear the * SEIS bit(using RNG_ClearFlag(RNG_FLAG_SECS) function), then disable * and enable the RNG peripheral (using RNG_Cmd() function) to * reinitialize and restart the RNG. * @note In the case of a clock error, the RNG is no more able to generate * random numbers because the PLL48CLK clock is not correct. User have * to check that the clock controller is correctly configured to provide * the RNG clock and clear the CEIS bit (using RNG_ClearFlag(RNG_FLAG_CECS) * function) . The clock error has no impact on the previously generated * random numbers, and the RNG_DR register contents can be used. * * @param None * @retval 32-bit random number. */ uint32_t RNG_GetRandomNumber(void) { /* Return the 32 bit random number from the DR register */ return RNG->DR; } /** * @} */ /** @defgroup RNG_Group3 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== Interrupts and flags management functions =============================================================================== This section provides functions allowing to configure the RNG Interrupts and to get the status and clear flags and Interrupts pending bits. The RNG provides 3 Interrupts sources and 3 Flags: Flags : ---------- 1. RNG_FLAG_DRDY : In the case of the RNG_DR register contains valid random data. it is cleared by reading the valid data (using RNG_GetRandomNumber() function). 2. RNG_FLAG_CECS : In the case of a seed error detection. 3. RNG_FLAG_SECS : In the case of a clock error detection. Interrupts : ------------ if enabled, an RNG interrupt is pending : 1. In the case of the RNG_DR register contains valid random data. This interrupt source is cleared once the RNG_DR register has been read (using RNG_GetRandomNumber() function) until a new valid value is computed. or 2. In the case of a seed error : One of the following faulty sequences has been detected: - More than 64 consecutive bits at the same value (0 or 1) - More than 32 consecutive alternance of 0 and 1 (0101010101...01) This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_SEI) function. or 3. In the case of a clock error : the PLL48CLK (RNG peripheral clock source) was not correctly detected (fPLL48CLK< fHCLK/16). This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_CEI) function. @note In this case, User have to check that the clock controller is correctly configured to provide the RNG clock. Managing the RNG controller events : ------------------------------------ The user should identify which mode will be used in his application to manage the RNG controller events: Polling mode or Interrupt mode. 1. In the Polling Mode it is advised to use the following functions: - RNG_GetFlagStatus() : to check if flags events occur. - RNG_ClearFlag() : to clear the flags events. @note RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag(). it is cleared only by reading the Random number data. 2. In the Interrupt Mode it is advised to use the following functions: - RNG_ITConfig() : to enable or disable the interrupt source. - RNG_GetITStatus() : to check if Interrupt occurs. - RNG_ClearITPendingBit() : to clear the Interrupt pending Bit (corresponding Flag). @endverbatim * @{ */ /** * @brief Enables or disables the RNG interrupt. * @note The RNG provides 3 interrupt sources, * - Computed data is ready event (DRDY), and * - Seed error Interrupt (SEI) and * - Clock error Interrupt (CEI), * all these interrupts sources are enabled by setting the IE bit in * CR register. However, each interrupt have its specific status bit * (see RNG_GetITStatus() function) and clear bit except the DRDY event * (see RNG_ClearITPendingBit() function). * @param NewState: new state of the RNG interrupt. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RNG_ITConfig(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the RNG interrupt */ RNG->CR |= RNG_CR_IE; } else { /* Disable the RNG interrupt */ RNG->CR &= ~RNG_CR_IE; } } /** * @brief Checks whether the specified RNG flag is set or not. * @param RNG_FLAG: specifies the RNG flag to check. * This parameter can be one of the following values: * @arg RNG_FLAG_DRDY: Data Ready flag. * @arg RNG_FLAG_CECS: Clock Error Current flag. * @arg RNG_FLAG_SECS: Seed Error Current flag. * @retval The new state of RNG_FLAG (SET or RESET). */ FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_RNG_GET_FLAG(RNG_FLAG)); /* Check the status of the specified RNG flag */ if ((RNG->SR & RNG_FLAG) != (uint8_t)RESET) { /* RNG_FLAG is set */ bitstatus = SET; } else { /* RNG_FLAG is reset */ bitstatus = RESET; } /* Return the RNG_FLAG status */ return bitstatus; } /** * @brief Clears the RNG flags. * @param RNG_FLAG: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg RNG_FLAG_CECS: Clock Error Current flag. * @arg RNG_FLAG_SECS: Seed Error Current flag. * @note RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag() function. * This flag is cleared only by reading the Random number data (using * RNG_GetRandomNumber() function). * @retval None */ void RNG_ClearFlag(uint8_t RNG_FLAG) { /* Check the parameters */ assert_param(IS_RNG_CLEAR_FLAG(RNG_FLAG)); /* Clear the selected RNG flags */ RNG->SR = ~(uint32_t)(((uint32_t)RNG_FLAG) << 4); } /** * @brief Checks whether the specified RNG interrupt has occurred or not. * @param RNG_IT: specifies the RNG interrupt source to check. * This parameter can be one of the following values: * @arg RNG_IT_CEI: Clock Error Interrupt. * @arg RNG_IT_SEI: Seed Error Interrupt. * @retval The new state of RNG_IT (SET or RESET). */ ITStatus RNG_GetITStatus(uint8_t RNG_IT) { ITStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_RNG_GET_IT(RNG_IT)); /* Check the status of the specified RNG interrupt */ if ((RNG->SR & RNG_IT) != (uint8_t)RESET) { /* RNG_IT is set */ bitstatus = SET; } else { /* RNG_IT is reset */ bitstatus = RESET; } /* Return the RNG_IT status */ return bitstatus; } /** * @brief Clears the RNG interrupt pending bit(s). * @param RNG_IT: specifies the RNG interrupt pending bit(s) to clear. * This parameter can be any combination of the following values: * @arg RNG_IT_CEI: Clock Error Interrupt. * @arg RNG_IT_SEI: Seed Error Interrupt. * @retval None */ void RNG_ClearITPendingBit(uint8_t RNG_IT) { /* Check the parameters */ assert_param(IS_RNG_IT(RNG_IT)); /* Clear the selected RNG interrupt pending bit */ RNG->SR = (uint8_t)~RNG_IT; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c ================================================ /** ****************************************************************************** * @file stm32f4xx_rtc.c * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file provides firmware functions to manage the following * functionalities of the Real-Time Clock (RTC) peripheral: * - Initialization * - Calendar (Time and Date) configuration * - Alarms (Alarm A and Alarm B) configuration * - WakeUp Timer configuration * - Daylight Saving configuration * - Output pin Configuration * - Coarse digital Calibration configuration * - Smooth digital Calibration configuration * - TimeStamp configuration * - Tampers configuration * - Backup Data Registers configuration * - Shift control synchronisation * - RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration * - Interrupts and flags management * * @verbatim * * =================================================================== * Backup Domain Operating Condition * =================================================================== * The real-time clock (RTC), the RTC backup registers, and the backup * SRAM (BKP SRAM) can be powered from the VBAT voltage when the main * VDD supply is powered off. * To retain the content of the RTC backup registers, backup SRAM, * and supply the RTC when VDD is turned off, VBAT pin can be connected * to an optional standby voltage supplied by a battery or by another * source. * * To allow the RTC to operate even when the main digital supply (VDD) * is turned off, the VBAT pin powers the following blocks: * 1 - The RTC * 2 - The LSE oscillator * 3 - The backup SRAM when the low power backup regulator is enabled * 4 - PC13 to PC15 I/Os, plus PI8 I/O (when available) * * When the backup domain is supplied by VDD (analog switch connected * to VDD), the following functions are available: * 1 - PC14 and PC15 can be used as either GPIO or LSE pins * 2 - PC13 can be used as a GPIO or as the RTC_AF1 pin * 3 - PI8 can be used as a GPIO or as the RTC_AF2 pin * * When the backup domain is supplied by VBAT (analog switch connected * to VBAT because VDD is not present), the following functions are available: * 1 - PC14 and PC15 can be used as LSE pins only * 2 - PC13 can be used as the RTC_AF1 pin * 3 - PI8 can be used as the RTC_AF2 pin * * =================================================================== * Backup Domain Reset * =================================================================== * The backup domain reset sets all RTC registers and the RCC_BDCR * register to their reset values. The BKPSRAM is not affected by this * reset. The only way of resetting the BKPSRAM is through the Flash * interface by requesting a protection level change from 1 to 0. * A backup domain reset is generated when one of the following events * occurs: * 1 - Software reset, triggered by setting the BDRST bit in the * RCC Backup domain control register (RCC_BDCR). You can use the * RCC_BackupResetCmd(). * 2 - VDD or VBAT power on, if both supplies have previously been * powered off. * * =================================================================== * Backup Domain Access * =================================================================== * After reset, the backup domain (RTC registers, RTC backup data * registers and backup SRAM) is protected against possible unwanted * write accesses. * To enable access to the RTC Domain and RTC registers, proceed as follows: * - Enable the Power Controller (PWR) APB1 interface clock using the * RCC_APB1PeriphClockCmd() function. * - Enable access to RTC domain using the PWR_BackupAccessCmd() function. * - Select the RTC clock source using the RCC_RTCCLKConfig() function. * - Enable RTC Clock using the RCC_RTCCLKCmd() function. * * =================================================================== * RTC Driver: how to use it * =================================================================== * - Enable the RTC domain access (see description in the section above) * - Configure the RTC Prescaler (Asynchronous and Synchronous) and * RTC hour format using the RTC_Init() function. * * Time and Date configuration * =========================== * - To configure the RTC Calendar (Time and Date) use the RTC_SetTime() * and RTC_SetDate() functions. * - To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate() * functions. * - Use the RTC_DayLightSavingConfig() function to add or sub one * hour to the RTC Calendar. * * Alarm configuration * =================== * - To configure the RTC Alarm use the RTC_SetAlarm() function. * - Enable the selected RTC Alarm using the RTC_AlarmCmd() function * - To read the RTC Alarm, use the RTC_GetAlarm() function. * - To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function. * * RTC Wakeup configuration * ======================== * - Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig() * function. * - Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() * function * - Enable the RTC WakeUp using the RTC_WakeUpCmd() function * - To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter() * function. * * Outputs configuration * ===================== * The RTC has 2 different outputs: * - AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B * and WaKeUp signals. * To output the selected RTC signal on RTC_AF1 pin, use the * RTC_OutputConfig() function. * - AFO_CALIB: this output is 512Hz signal or 1Hz . * To output the RTC Clock on RTC_AF1 pin, use the RTC_CalibOutputCmd() * function. * * Smooth digital Calibration configuration * ================================= * - Configure the RTC Original Digital Calibration Value and the corresponding * calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig() * function. * * Coarse digital Calibration configuration * ================================= * - Configure the RTC Coarse Calibration Value and the corresponding * sign using the RTC_CoarseCalibConfig() function. * - Enable the RTC Coarse Calibration using the RTC_CoarseCalibCmd() * function * * TimeStamp configuration * ======================= * - Configure the RTC_AF1 trigger and enables the RTC TimeStamp * using the RTC_TimeStampCmd() function. * - To read the RTC TimeStamp Time and Date register, use the * RTC_GetTimeStamp() function. * - To read the RTC TimeStamp SubSecond register, use the * RTC_GetTimeStampSubSecond() function. * - The TAMPER1 alternate function can be mapped either to RTC_AF1(PC13) * or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in * RTC_TAFCR register. You can use the RTC_TamperPinSelection() * function to select the corresponding pin. * * Tamper configuration * ==================== * - Enable the RTC Tamper using the RTC_TamperCmd() function. * - Configure the Tamper filter count using RTC_TamperFilterConfig() * function. * - Configure the RTC Tamper trigger Edge or Level according to the Tamper * filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig() function. * - Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig() * function. * - Configure the Tamper precharge or discharge duration using * RTC_TamperPinsPrechargeDuration() function. * - Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function. * - Enable the Time stamp on Tamper detection event using * RTC_TSOnTamperDetecCmd() function. * - The TIMESTAMP alternate function can be mapped to either RTC_AF1 * or RTC_AF2 depending on the value of the TSINSEL bit in the * RTC_TAFCR register. You can use the RTC_TimeStampPinSelection() * function to select the corresponding pin. * * Backup Data Registers configuration * =================================== * - To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister() * function. * - To read the RTC Backup Data registers, use the RTC_ReadBackupRegister() * function. * * =================================================================== * RTC and low power modes * =================================================================== * The MCU can be woken up from a low power mode by an RTC alternate * function. * The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), * RTC wakeup, RTC tamper event detection and RTC time stamp event detection. * These RTC alternate functions can wake up the system from the Stop * and Standby lowpower modes. * The system can also wake up from low power modes without depending * on an external interrupt (Auto-wakeup mode), by using the RTC alarm * or the RTC wakeup events. * The RTC provides a programmable time base for waking up from the * Stop or Standby mode at regular intervals. * Wakeup from STOP and Standby modes is possible only when the RTC * clock source is LSE or LSI. * * =================================================================== * Selection of RTC_AF1 alternate functions * =================================================================== * The RTC_AF1 pin (PC13) can be used for the following purposes: * - AFO_ALARM output * - AFO_CALIB output * - AFI_TAMPER * - AFI_TIMESTAMP * * +-------------------------------------------------------------------------------------------------------------+ * | Pin |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE | * | configuration | ENABLED | ENABLED | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM | * | and function | | | | | selection | selection |Configuration | * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| * | Alarm out | | | | | Don't | Don't | | * | output OD | 1 |Don't care|Don't care | Don't care | care | care | 0 | * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| * | Alarm out | | | | | Don't | Don't | | * | output PP | 1 |Don't care|Don't care | Don't care | care | care | 1 | * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| * | Calibration out | | | | | Don't | Don't | | * | output PP | 0 | 1 |Don't care | Don't care | care | care | Don't care | * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| * | TAMPER input | | | | | | Don't | | * | floating | 0 | 0 | 1 | 0 | 0 | care | Don't care | * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| * | TIMESTAMP and | | | | | | | | * | TAMPER input | 0 | 0 | 1 | 1 | 0 | 0 | Don't care | * | floating | | | | | | | | * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| * | TIMESTAMP input | | | | | Don't | | | * | floating | 0 | 0 | 0 | 1 | care | 0 | Don't care | * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| * | Standard GPIO | 0 | 0 | 0 | 0 | Don't care | Don't care | Don't care | * +-------------------------------------------------------------------------------------------------------------+ * * * =================================================================== * Selection of RTC_AF2 alternate functions * =================================================================== * The RTC_AF2 pin (PI8) can be used for the following purposes: * - AFI_TAMPER * - AFI_TIMESTAMP * * +---------------------------------------------------------------------------------------+ * | Pin |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE | * | configuration | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM | * | and function | | | selection | selection |Configuration | * |-----------------|-----------|--------------|------------|--------------|--------------| * | TAMPER input | | | | Don't | | * | floating | 1 | 0 | 1 | care | Don't care | * |-----------------|-----------|--------------|------------|--------------|--------------| * | TIMESTAMP and | | | | | | * | TAMPER input | 1 | 1 | 1 | 1 | Don't care | * | floating | | | | | | * |-----------------|-----------|--------------|------------|--------------|--------------| * | TIMESTAMP input | | | Don't | | | * | floating | 0 | 1 | care | 1 | Don't care | * |-----------------|-----------|--------------|------------|--------------|--------------| * | Standard GPIO | 0 | 0 | Don't care | Don't care | Don't care | * +---------------------------------------------------------------------------------------+ * * * @endverbatim * ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_rtc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup RTC * @brief RTC driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Masks Definition */ #define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) #define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) #define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) #define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F) #define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \ RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \ RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \ RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \ RTC_FLAG_RECALPF | RTC_FLAG_SHPF)) #define INITMODE_TIMEOUT ((uint32_t) 0x00010000) #define SYNCHRO_TIMEOUT ((uint32_t) 0x00020000) #define RECALPF_TIMEOUT ((uint32_t) 0x00020000) #define SHPF_TIMEOUT ((uint32_t) 0x00001000) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ static uint8_t RTC_ByteToBcd2(uint8_t Value); static uint8_t RTC_Bcd2ToByte(uint8_t Value); /* Private functions ---------------------------------------------------------*/ /** @defgroup RTC_Private_Functions * @{ */ /** @defgroup RTC_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== Initialization and Configuration functions =============================================================================== This section provide functions allowing to initialize and configure the RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers Write protection, enter and exit the RTC initialization mode, RTC registers synchronization check and reference clock detection enable. 1. The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is split into 2 programmable prescalers to minimize power consumption. - A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler. - When both prescalers are used, it is recommended to configure the asynchronous prescaler to a high value to minimize consumption. 2. All RTC registers are Write protected. Writing to the RTC registers is enabled by writing a key into the Write Protection register, RTC_WPR. 3. To Configure the RTC Calendar, user application should enter initialization mode. In this mode, the calendar counter is stopped and its value can be updated. When the initialization sequence is complete, the calendar restarts counting after 4 RTCCLK cycles. 4. To read the calendar through the shadow registers after Calendar initialization, calendar update or after wakeup from low power modes the software must first clear the RSF flag. The software must then wait until it is set again before reading the calendar, which means that the calendar registers have been correctly copied into the RTC_TR and RTC_DR shadow registers. The RTC_WaitForSynchro() function implements the above software sequence (RSF clear and RSF check). @endverbatim * @{ */ /** * @brief Deinitializes the RTC registers to their default reset values. * @note This function doesn't reset the RTC Clock source and RTC Backup Data * registers. * @param None * @retval An ErrorStatus enumeration value: * - SUCCESS: RTC registers are deinitialized * - ERROR: RTC registers are not deinitialized */ ErrorStatus RTC_DeInit(void) { __IO uint32_t wutcounter = 0x00; uint32_t wutwfstatus = 0x00; ErrorStatus status = ERROR; /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Set Initialization mode */ if (RTC_EnterInitMode() == ERROR) { status = ERROR; } else { /* Reset TR, DR and CR registers */ RTC->TR = (uint32_t)0x00000000; RTC->DR = (uint32_t)0x00002101; /* Reset All CR bits except CR[2:0] */ RTC->CR &= (uint32_t)0x00000007; /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ do { wutwfstatus = RTC->ISR & RTC_ISR_WUTWF; wutcounter++; } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); if ((RTC->ISR & RTC_ISR_WUTWF) == RESET) { status = ERROR; } else { /* Reset all RTC CR register bits */ RTC->CR &= (uint32_t)0x00000000; RTC->WUTR = (uint32_t)0x0000FFFF; RTC->PRER = (uint32_t)0x007F00FF; RTC->CALIBR = (uint32_t)0x00000000; RTC->ALRMAR = (uint32_t)0x00000000; RTC->ALRMBR = (uint32_t)0x00000000; RTC->SHIFTR = (uint32_t)0x00000000; RTC->CALR = (uint32_t)0x00000000; RTC->ALRMASSR = (uint32_t)0x00000000; RTC->ALRMBSSR = (uint32_t)0x00000000; /* Reset ISR register and exit initialization mode */ RTC->ISR = (uint32_t)0x00000000; /* Reset Tamper and alternate functions configuration register */ RTC->TAFCR = 0x00000000; if(RTC_WaitForSynchro() == ERROR) { status = ERROR; } else { status = SUCCESS; } } } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; return status; } /** * @brief Initializes the RTC registers according to the specified parameters * in RTC_InitStruct. * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains * the configuration information for the RTC peripheral. * @note The RTC Prescaler register is write protected and can be written in * initialization mode only. * @retval An ErrorStatus enumeration value: * - SUCCESS: RTC registers are initialized * - ERROR: RTC registers are not initialized */ ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct) { ErrorStatus status = ERROR; /* Check the parameters */ assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat)); assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv)); assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Set Initialization mode */ if (RTC_EnterInitMode() == ERROR) { status = ERROR; } else { /* Clear RTC CR FMT Bit */ RTC->CR &= ((uint32_t)~(RTC_CR_FMT)); /* Set RTC_CR register */ RTC->CR |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat)); /* Configure the RTC PRER */ RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv); RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16); /* Exit Initialization mode */ RTC_ExitInitMode(); status = SUCCESS; } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; return status; } /** * @brief Fills each RTC_InitStruct member with its default value. * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be * initialized. * @retval None */ void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct) { /* Initialize the RTC_HourFormat member */ RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24; /* Initialize the RTC_AsynchPrediv member */ RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F; /* Initialize the RTC_SynchPrediv member */ RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; } /** * @brief Enables or disables the RTC registers write protection. * @note All the RTC registers are write protected except for RTC_ISR[13:8], * RTC_TAFCR and RTC_BKPxR. * @note Writing a wrong key reactivates the write protection. * @note The protection mechanism is not affected by system reset. * @param NewState: new state of the write protection. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RTC_WriteProtectionCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; } else { /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; } } /** * @brief Enters the RTC Initialization mode. * @note The RTC Initialization mode is write protected, use the * RTC_WriteProtectionCmd(DISABLE) before calling this function. * @param None * @retval An ErrorStatus enumeration value: * - SUCCESS: RTC is in Init mode * - ERROR: RTC is not in Init mode */ ErrorStatus RTC_EnterInitMode(void) { __IO uint32_t initcounter = 0x00; ErrorStatus status = ERROR; uint32_t initstatus = 0x00; /* Check if the Initialization mode is set */ if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET) { /* Set the Initialization mode */ RTC->ISR = (uint32_t)RTC_INIT_MASK; /* Wait till RTC is in INIT state and if Time out is reached exit */ do { initstatus = RTC->ISR & RTC_ISR_INITF; initcounter++; } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00)); if ((RTC->ISR & RTC_ISR_INITF) != RESET) { status = SUCCESS; } else { status = ERROR; } } else { status = SUCCESS; } return (status); } /** * @brief Exits the RTC Initialization mode. * @note When the initialization sequence is complete, the calendar restarts * counting after 4 RTCCLK cycles. * @note The RTC Initialization mode is write protected, use the * RTC_WriteProtectionCmd(DISABLE) before calling this function. * @param None * @retval None */ void RTC_ExitInitMode(void) { /* Exit Initialization mode */ RTC->ISR &= (uint32_t)~RTC_ISR_INIT; } /** * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are * synchronized with RTC APB clock. * @note The RTC Resynchronization mode is write protected, use the * RTC_WriteProtectionCmd(DISABLE) before calling this function. * @note To read the calendar through the shadow registers after Calendar * initialization, calendar update or after wakeup from low power modes * the software must first clear the RSF flag. * The software must then wait until it is set again before reading * the calendar, which means that the calendar registers have been * correctly copied into the RTC_TR and RTC_DR shadow registers. * @param None * @retval An ErrorStatus enumeration value: * - SUCCESS: RTC registers are synchronised * - ERROR: RTC registers are not synchronised */ ErrorStatus RTC_WaitForSynchro(void) { __IO uint32_t synchrocounter = 0; ErrorStatus status = ERROR; uint32_t synchrostatus = 0x00; /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Clear RSF flag */ RTC->ISR &= (uint32_t)RTC_RSF_MASK; /* Wait the registers to be synchronised */ do { synchrostatus = RTC->ISR & RTC_ISR_RSF; synchrocounter++; } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00)); if ((RTC->ISR & RTC_ISR_RSF) != RESET) { status = SUCCESS; } else { status = ERROR; } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; return (status); } /** * @brief Enables or disables the RTC reference clock detection. * @param NewState: new state of the RTC reference clock. * This parameter can be: ENABLE or DISABLE. * @retval An ErrorStatus enumeration value: * - SUCCESS: RTC reference clock detection is enabled * - ERROR: RTC reference clock detection is disabled */ ErrorStatus RTC_RefClockCmd(FunctionalState NewState) { ErrorStatus status = ERROR; /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Set Initialization mode */ if (RTC_EnterInitMode() == ERROR) { status = ERROR; } else { if (NewState != DISABLE) { /* Enable the RTC reference clock detection */ RTC->CR |= RTC_CR_REFCKON; } else { /* Disable the RTC reference clock detection */ RTC->CR &= ~RTC_CR_REFCKON; } /* Exit Initialization mode */ RTC_ExitInitMode(); status = SUCCESS; } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; return status; } /** * @brief Enables or Disables the Bypass Shadow feature. * @note When the Bypass Shadow is enabled the calendar value are taken * directly from the Calendar counter. * @param NewState: new state of the Bypass Shadow feature. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RTC_BypassShadowCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; if (NewState != DISABLE) { /* Set the BYPSHAD bit */ RTC->CR |= (uint8_t)RTC_CR_BYPSHAD; } else { /* Reset the BYPSHAD bit */ RTC->CR &= (uint8_t)~RTC_CR_BYPSHAD; } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; } /** * @} */ /** @defgroup RTC_Group2 Time and Date configuration functions * @brief Time and Date configuration functions * @verbatim =============================================================================== Time and Date configuration functions =============================================================================== This section provide functions allowing to program and read the RTC Calendar (Time and Date). @endverbatim * @{ */ /** * @brief Set the RTC current time. * @param RTC_Format: specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_Format_BIN: Binary data format * @arg RTC_Format_BCD: BCD data format * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains * the time configuration information for the RTC. * @retval An ErrorStatus enumeration value: * - SUCCESS: RTC Time register is configured * - ERROR: RTC Time register is not configured */ ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) { uint32_t tmpreg = 0; ErrorStatus status = ERROR; /* Check the parameters */ assert_param(IS_RTC_FORMAT(RTC_Format)); if (RTC_Format == RTC_Format_BIN) { if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) { assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours)); assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); } else { RTC_TimeStruct->RTC_H12 = 0x00; assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours)); } assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes)); assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds)); } else { if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) { tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); assert_param(IS_RTC_HOUR12(tmpreg)); assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); } else { RTC_TimeStruct->RTC_H12 = 0x00; assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours))); } assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes))); assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds))); } /* Check the input parameters format */ if (RTC_Format != RTC_Format_BIN) { tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \ ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \ ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \ ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16)); } else { tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \ ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \ ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \ (((uint32_t)RTC_TimeStruct->RTC_H12) << 16)); } /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Set Initialization mode */ if (RTC_EnterInitMode() == ERROR) { status = ERROR; } else { /* Set the RTC_TR register */ RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); /* Exit Initialization mode */ RTC_ExitInitMode(); /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ if ((RTC->CR & RTC_CR_BYPSHAD) == RESET) { if (RTC_WaitForSynchro() == ERROR) { status = ERROR; } else { status = SUCCESS; } } else { status = SUCCESS; } } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; return status; } /** * @brief Fills each RTC_TimeStruct member with its default value * (Time = 00h:00min:00sec). * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be * initialized. * @retval None */ void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct) { /* Time = 00h:00min:00sec */ RTC_TimeStruct->RTC_H12 = RTC_H12_AM; RTC_TimeStruct->RTC_Hours = 0; RTC_TimeStruct->RTC_Minutes = 0; RTC_TimeStruct->RTC_Seconds = 0; } /** * @brief Get the RTC current Time. * @param RTC_Format: specifies the format of the returned parameters. * This parameter can be one of the following values: * @arg RTC_Format_BIN: Binary data format * @arg RTC_Format_BCD: BCD data format * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will * contain the returned current time configuration. * @retval None */ void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RTC_FORMAT(RTC_Format)); /* Get the RTC_TR register */ tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); /* Fill the structure fields with the read parameters */ RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16); RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8); RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); /* Check the input parameters format */ if (RTC_Format == RTC_Format_BIN) { /* Convert the structure parameters to Binary format */ RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes); RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds); } } /** * @brief Gets the RTC current Calendar Subseconds value. * @note This function freeze the Time and Date registers after reading the * SSR register. * @param None * @retval RTC current Calendar Subseconds value. */ uint32_t RTC_GetSubSecond(void) { uint32_t tmpreg = 0; /* Get subseconds values from the correspondent registers*/ tmpreg = (uint32_t)(RTC->SSR); /* Read DR register to unfroze calendar registers */ (void) (RTC->DR); return (tmpreg); } /** * @brief Set the RTC current date. * @param RTC_Format: specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_Format_BIN: Binary data format * @arg RTC_Format_BCD: BCD data format * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains * the date configuration information for the RTC. * @retval An ErrorStatus enumeration value: * - SUCCESS: RTC Date register is configured * - ERROR: RTC Date register is not configured */ ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) { uint32_t tmpreg = 0; ErrorStatus status = ERROR; /* Check the parameters */ assert_param(IS_RTC_FORMAT(RTC_Format)); if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10)) { RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A; } if (RTC_Format == RTC_Format_BIN) { assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year)); assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month)); assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date)); } else { assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year))); tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); assert_param(IS_RTC_MONTH(tmpreg)); tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); assert_param(IS_RTC_DATE(tmpreg)); } assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay)); /* Check the input parameters format */ if (RTC_Format != RTC_Format_BIN) { tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \ (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \ ((uint32_t)RTC_DateStruct->RTC_Date) | \ (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13)); } else { tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \ ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \ ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \ ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13)); } /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Set Initialization mode */ if (RTC_EnterInitMode() == ERROR) { status = ERROR; } else { /* Set the RTC_DR register */ RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK); /* Exit Initialization mode */ RTC_ExitInitMode(); /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ if ((RTC->CR & RTC_CR_BYPSHAD) == RESET) { if (RTC_WaitForSynchro() == ERROR) { status = ERROR; } else { status = SUCCESS; } } else { status = SUCCESS; } } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; return status; } /** * @brief Fills each RTC_DateStruct member with its default value * (Monday, January 01 xx00). * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be * initialized. * @retval None */ void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct) { /* Monday, January 01 xx00 */ RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday; RTC_DateStruct->RTC_Date = 1; RTC_DateStruct->RTC_Month = RTC_Month_January; RTC_DateStruct->RTC_Year = 0; } /** * @brief Get the RTC current date. * @param RTC_Format: specifies the format of the returned parameters. * This parameter can be one of the following values: * @arg RTC_Format_BIN: Binary data format * @arg RTC_Format_BCD: BCD data format * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will * contain the returned current date configuration. * @retval None */ void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RTC_FORMAT(RTC_Format)); /* Get the RTC_TR register */ tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); /* Fill the structure fields with the read parameters */ RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16); RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8); RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU)); RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13); /* Check the input parameters format */ if (RTC_Format == RTC_Format_BIN) { /* Convert the structure parameters to Binary format */ RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year); RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); } } /** * @} */ /** @defgroup RTC_Group3 Alarms configuration functions * @brief Alarms (Alarm A and Alarm B) configuration functions * @verbatim =============================================================================== Alarms (Alarm A and Alarm B) configuration functions =============================================================================== This section provide functions allowing to program and read the RTC Alarms. @endverbatim * @{ */ /** * @brief Set the specified RTC Alarm. * @note The Alarm register can only be written when the corresponding Alarm * is disabled (Use the RTC_AlarmCmd(DISABLE)). * @param RTC_Format: specifies the format of the returned parameters. * This parameter can be one of the following values: * @arg RTC_Format_BIN: Binary data format * @arg RTC_Format_BCD: BCD data format * @param RTC_Alarm: specifies the alarm to be configured. * This parameter can be one of the following values: * @arg RTC_Alarm_A: to select Alarm A * @arg RTC_Alarm_B: to select Alarm B * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that * contains the alarm configuration parameters. * @retval None */ void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RTC_FORMAT(RTC_Format)); assert_param(IS_RTC_ALARM(RTC_Alarm)); assert_param(IS_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask)); assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel)); if (RTC_Format == RTC_Format_BIN) { if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) { assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); } else { RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); } assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)); assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)); if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) { assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); } else { assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); } } else { if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) { tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours); assert_param(IS_RTC_HOUR12(tmpreg)); assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); } else { RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours))); } assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes))); assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds))); if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) { tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); } else { tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); } } /* Check the input parameters format */ if (RTC_Format != RTC_Format_BIN) { tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \ ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); } else { tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \ ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); } /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Configure the Alarm register */ if (RTC_Alarm == RTC_Alarm_A) { RTC->ALRMAR = (uint32_t)tmpreg; } else { RTC->ALRMBR = (uint32_t)tmpreg; } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; } /** * @brief Fills each RTC_AlarmStruct member with its default value * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = * all fields are masked). * @param RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which * will be initialized. * @retval None */ void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct) { /* Alarm Time Settings : Time = 00h:00mn:00sec */ RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM; RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0; RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0; RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0; /* Alarm Date Settings : Date = 1st day of the month */ RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date; RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1; /* Alarm Masks Settings : Mask = all fields are not masked */ RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None; } /** * @brief Get the RTC Alarm value and masks. * @param RTC_Format: specifies the format of the output parameters. * This parameter can be one of the following values: * @arg RTC_Format_BIN: Binary data format * @arg RTC_Format_BCD: BCD data format * @param RTC_Alarm: specifies the alarm to be read. * This parameter can be one of the following values: * @arg RTC_Alarm_A: to select Alarm A * @arg RTC_Alarm_B: to select Alarm B * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will * contains the output alarm configuration values. * @retval None */ void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RTC_FORMAT(RTC_Format)); assert_param(IS_RTC_ALARM(RTC_Alarm)); /* Get the RTC_ALRMxR register */ if (RTC_Alarm == RTC_Alarm_A) { tmpreg = (uint32_t)(RTC->ALRMAR); } else { tmpreg = (uint32_t)(RTC->ALRMBR); } /* Fill the structure with the read parameters */ RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \ RTC_ALRMAR_HU)) >> 16); RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \ RTC_ALRMAR_MNU)) >> 8); RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \ RTC_ALRMAR_SU)); RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16); RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24); RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All); if (RTC_Format == RTC_Format_BIN) { RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ RTC_AlarmTime.RTC_Hours); RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ RTC_AlarmTime.RTC_Minutes); RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ RTC_AlarmTime.RTC_Seconds); RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); } } /** * @brief Enables or disables the specified RTC Alarm. * @param RTC_Alarm: specifies the alarm to be configured. * This parameter can be any combination of the following values: * @arg RTC_Alarm_A: to select Alarm A * @arg RTC_Alarm_B: to select Alarm B * @param NewState: new state of the specified alarm. * This parameter can be: ENABLE or DISABLE. * @retval An ErrorStatus enumeration value: * - SUCCESS: RTC Alarm is enabled/disabled * - ERROR: RTC Alarm is not enabled/disabled */ ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState) { __IO uint32_t alarmcounter = 0x00; uint32_t alarmstatus = 0x00; ErrorStatus status = ERROR; /* Check the parameters */ assert_param(IS_RTC_CMD_ALARM(RTC_Alarm)); assert_param(IS_FUNCTIONAL_STATE(NewState)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Configure the Alarm state */ if (NewState != DISABLE) { RTC->CR |= (uint32_t)RTC_Alarm; status = SUCCESS; } else { /* Disable the Alarm in RTC_CR register */ RTC->CR &= (uint32_t)~RTC_Alarm; /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ do { alarmstatus = RTC->ISR & (RTC_Alarm >> 8); alarmcounter++; } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00)); if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET) { status = ERROR; } else { status = SUCCESS; } } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; return status; } /** * @brief Configure the RTC AlarmA/B Subseconds value and mask.* * @note This function is performed only when the Alarm is disabled. * @param RTC_Alarm: specifies the alarm to be configured. * This parameter can be one of the following values: * @arg RTC_Alarm_A: to select Alarm A * @arg RTC_Alarm_B: to select Alarm B * @param RTC_AlarmSubSecondValue: specifies the Subseconds value. * This parameter can be a value from 0 to 0x00007FFF. * @param RTC_AlarmSubSecondMask: specifies the Subseconds Mask. * This parameter can be any combination of the following values: * @arg RTC_AlarmSubSecondMask_All : All Alarm SS fields are masked. * There is no comparison on sub seconds for Alarm. * @arg RTC_AlarmSubSecondMask_SS14_1 : SS[14:1] are don't care in Alarm comparison. * Only SS[0] is compared * @arg RTC_AlarmSubSecondMask_SS14_2 : SS[14:2] are don't care in Alarm comparison. * Only SS[1:0] are compared * @arg RTC_AlarmSubSecondMask_SS14_3 : SS[14:3] are don't care in Alarm comparison. * Only SS[2:0] are compared * @arg RTC_AlarmSubSecondMask_SS14_4 : SS[14:4] are don't care in Alarm comparison. * Only SS[3:0] are compared * @arg RTC_AlarmSubSecondMask_SS14_5 : SS[14:5] are don't care in Alarm comparison. * Only SS[4:0] are compared * @arg RTC_AlarmSubSecondMask_SS14_6 : SS[14:6] are don't care in Alarm comparison. * Only SS[5:0] are compared * @arg RTC_AlarmSubSecondMask_SS14_7 : SS[14:7] are don't care in Alarm comparison. * Only SS[6:0] are compared * @arg RTC_AlarmSubSecondMask_SS14_8 : SS[14:8] are don't care in Alarm comparison. * Only SS[7:0] are compared * @arg RTC_AlarmSubSecondMask_SS14_9 : SS[14:9] are don't care in Alarm comparison. * Only SS[8:0] are compared * @arg RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison. * Only SS[9:0] are compared * @arg RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison. * Only SS[10:0] are compared * @arg RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison. * Only SS[11:0] are compared * @arg RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison. * Only SS[12:0] are compared * @arg RTC_AlarmSubSecondMask_SS14 : SS[14] is don't care in Alarm comparison. * Only SS[13:0] are compared * @arg RTC_AlarmSubSecondMask_None : SS[14:0] are compared and must match * to activate alarm * @retval None */ void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RTC_ALARM(RTC_Alarm)); assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue)); assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(RTC_AlarmSubSecondMask)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Configure the Alarm A or Alarm B SubSecond registers */ tmpreg = (uint32_t) (uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask); if (RTC_Alarm == RTC_Alarm_A) { /* Configure the AlarmA SubSecond register */ RTC->ALRMASSR = tmpreg; } else { /* Configure the Alarm B SubSecond register */ RTC->ALRMBSSR = tmpreg; } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; } /** * @brief Gets the RTC Alarm Subseconds value. * @param RTC_Alarm: specifies the alarm to be read. * This parameter can be one of the following values: * @arg RTC_Alarm_A: to select Alarm A * @arg RTC_Alarm_B: to select Alarm B * @param None * @retval RTC Alarm Subseconds value. */ uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm) { uint32_t tmpreg = 0; /* Get the RTC_ALRMxR register */ if (RTC_Alarm == RTC_Alarm_A) { tmpreg = (uint32_t)((RTC->ALRMASSR) & RTC_ALRMASSR_SS); } else { tmpreg = (uint32_t)((RTC->ALRMBSSR) & RTC_ALRMBSSR_SS); } return (tmpreg); } /** * @} */ /** @defgroup RTC_Group4 WakeUp Timer configuration functions * @brief WakeUp Timer configuration functions * @verbatim =============================================================================== WakeUp Timer configuration functions =============================================================================== This section provide functions allowing to program and read the RTC WakeUp. @endverbatim * @{ */ /** * @brief Configures the RTC Wakeup clock source. * @note The WakeUp Clock source can only be changed when the RTC WakeUp * is disabled (Use the RTC_WakeUpCmd(DISABLE)). * @param RTC_WakeUpClock: Wakeup Clock source. * This parameter can be one of the following values: * @arg RTC_WakeUpClock_RTCCLK_Div16: RTC Wakeup Counter Clock = RTCCLK/16 * @arg RTC_WakeUpClock_RTCCLK_Div8: RTC Wakeup Counter Clock = RTCCLK/8 * @arg RTC_WakeUpClock_RTCCLK_Div4: RTC Wakeup Counter Clock = RTCCLK/4 * @arg RTC_WakeUpClock_RTCCLK_Div2: RTC Wakeup Counter Clock = RTCCLK/2 * @arg RTC_WakeUpClock_CK_SPRE_16bits: RTC Wakeup Counter Clock = CK_SPRE * @arg RTC_WakeUpClock_CK_SPRE_17bits: RTC Wakeup Counter Clock = CK_SPRE * @retval None */ void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock) { /* Check the parameters */ assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Clear the Wakeup Timer clock source bits in CR register */ RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL; /* Configure the clock source */ RTC->CR |= (uint32_t)RTC_WakeUpClock; /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; } /** * @brief Configures the RTC Wakeup counter. * @note The RTC WakeUp counter can only be written when the RTC WakeUp * is disabled (Use the RTC_WakeUpCmd(DISABLE)). * @param RTC_WakeUpCounter: specifies the WakeUp counter. * This parameter can be a value from 0x0000 to 0xFFFF. * @retval None */ void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter) { /* Check the parameters */ assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Configure the Wakeup Timer counter */ RTC->WUTR = (uint32_t)RTC_WakeUpCounter; /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; } /** * @brief Returns the RTC WakeUp timer counter value. * @param None * @retval The RTC WakeUp Counter value. */ uint32_t RTC_GetWakeUpCounter(void) { /* Get the counter value */ return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT)); } /** * @brief Enables or Disables the RTC WakeUp timer. * @param NewState: new state of the WakeUp timer. * This parameter can be: ENABLE or DISABLE. * @retval None */ ErrorStatus RTC_WakeUpCmd(FunctionalState NewState) { __IO uint32_t wutcounter = 0x00; uint32_t wutwfstatus = 0x00; ErrorStatus status = ERROR; /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; if (NewState != DISABLE) { /* Enable the Wakeup Timer */ RTC->CR |= (uint32_t)RTC_CR_WUTE; status = SUCCESS; } else { /* Disable the Wakeup Timer */ RTC->CR &= (uint32_t)~RTC_CR_WUTE; /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ do { wutwfstatus = RTC->ISR & RTC_ISR_WUTWF; wutcounter++; } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); if ((RTC->ISR & RTC_ISR_WUTWF) == RESET) { status = ERROR; } else { status = SUCCESS; } } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; return status; } /** * @} */ /** @defgroup RTC_Group5 Daylight Saving configuration functions * @brief Daylight Saving configuration functions * @verbatim =============================================================================== Daylight Saving configuration functions =============================================================================== This section provide functions allowing to configure the RTC DayLight Saving. @endverbatim * @{ */ /** * @brief Adds or substract one hour from the current time. * @param RTC_DayLightSaveOperation: the value of hour adjustment. * This parameter can be one of the following values: * @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time) * @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time) * @param RTC_StoreOperation: Specifies the value to be written in the BCK bit * in CR register to store the operation. * This parameter can be one of the following values: * @arg RTC_StoreOperation_Reset: BCK Bit Reset * @arg RTC_StoreOperation_Set: BCK Bit Set * @retval None */ void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation) { /* Check the parameters */ assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving)); assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Clear the bits to be configured */ RTC->CR &= (uint32_t)~(RTC_CR_BCK); /* Configure the RTC_CR register */ RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation); /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; } /** * @brief Returns the RTC Day Light Saving stored operation. * @param None * @retval RTC Day Light Saving stored operation. * - RTC_StoreOperation_Reset * - RTC_StoreOperation_Set */ uint32_t RTC_GetStoreOperation(void) { return (RTC->CR & RTC_CR_BCK); } /** * @} */ /** @defgroup RTC_Group6 Output pin Configuration function * @brief Output pin Configuration function * @verbatim =============================================================================== Output pin Configuration function =============================================================================== This section provide functions allowing to configure the RTC Output source. @endverbatim * @{ */ /** * @brief Configures the RTC output source (AFO_ALARM). * @param RTC_Output: Specifies which signal will be routed to the RTC output. * This parameter can be one of the following values: * @arg RTC_Output_Disable: No output selected * @arg RTC_Output_AlarmA: signal of AlarmA mapped to output * @arg RTC_Output_AlarmB: signal of AlarmB mapped to output * @arg RTC_Output_WakeUp: signal of WakeUp mapped to output * @param RTC_OutputPolarity: Specifies the polarity of the output signal. * This parameter can be one of the following: * @arg RTC_OutputPolarity_High: The output pin is high when the * ALRAF/ALRBF/WUTF is high (depending on OSEL) * @arg RTC_OutputPolarity_Low: The output pin is low when the * ALRAF/ALRBF/WUTF is high (depending on OSEL) * @retval None */ void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity) { /* Check the parameters */ assert_param(IS_RTC_OUTPUT(RTC_Output)); assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Clear the bits to be configured */ RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL); /* Configure the output selection and polarity */ RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity); /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; } /** * @} */ /** @defgroup RTC_Group7 Digital Calibration configuration functions * @brief Coarse Calibration configuration functions * @verbatim =============================================================================== Digital Calibration configuration functions =============================================================================== @endverbatim * @{ */ /** * @brief Configures the Coarse calibration parameters. * @param RTC_CalibSign: specifies the sign of the coarse calibration value. * This parameter can be one of the following values: * @arg RTC_CalibSign_Positive: The value sign is positive * @arg RTC_CalibSign_Negative: The value sign is negative * @param Value: value of coarse calibration expressed in ppm (coded on 5 bits). * * @note This Calibration value should be between 0 and 63 when using negative * sign with a 2-ppm step. * * @note This Calibration value should be between 0 and 126 when using positive * sign with a 4-ppm step. * * @retval An ErrorStatus enumeration value: * - SUCCESS: RTC Coarse calibration are initialized * - ERROR: RTC Coarse calibration are not initialized */ ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value) { ErrorStatus status = ERROR; /* Check the parameters */ assert_param(IS_RTC_CALIB_SIGN(RTC_CalibSign)); assert_param(IS_RTC_CALIB_VALUE(Value)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Set Initialization mode */ if (RTC_EnterInitMode() == ERROR) { status = ERROR; } else { /* Set the coarse calibration value */ RTC->CALIBR = (uint32_t)(RTC_CalibSign | Value); /* Exit Initialization mode */ RTC_ExitInitMode(); status = SUCCESS; } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; return status; } /** * @brief Enables or disables the Coarse calibration process. * @param NewState: new state of the Coarse calibration. * This parameter can be: ENABLE or DISABLE. * @retval An ErrorStatus enumeration value: * - SUCCESS: RTC Coarse calibration are enabled/disabled * - ERROR: RTC Coarse calibration are not enabled/disabled */ ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState) { ErrorStatus status = ERROR; /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Set Initialization mode */ if (RTC_EnterInitMode() == ERROR) { status = ERROR; } else { if (NewState != DISABLE) { /* Enable the Coarse Calibration */ RTC->CR |= (uint32_t)RTC_CR_DCE; } else { /* Disable the Coarse Calibration */ RTC->CR &= (uint32_t)~RTC_CR_DCE; } /* Exit Initialization mode */ RTC_ExitInitMode(); status = SUCCESS; } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; return status; } /** * @brief Enables or disables the RTC clock to be output through the relative pin. * @param NewState: new state of the digital calibration Output. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RTC_CalibOutputCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; if (NewState != DISABLE) { /* Enable the RTC clock output */ RTC->CR |= (uint32_t)RTC_CR_COE; } else { /* Disable the RTC clock output */ RTC->CR &= (uint32_t)~RTC_CR_COE; } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; } /** * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). * @param RTC_CalibOutput : Select the Calibration output Selection . * This parameter can be one of the following values: * @arg RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz. * @arg RTC_CalibOutput_1Hz : A signal has a regular waveform at 1Hz. * @retval None */ void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput) { /* Check the parameters */ assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /*clear flags before config*/ RTC->CR &= (uint32_t)~(RTC_CR_COSEL); /* Configure the RTC_CR register */ RTC->CR |= (uint32_t)RTC_CalibOutput; /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; } /** * @brief Configures the Smooth Calibration Settings. * @param RTC_SmoothCalibPeriod : Select the Smooth Calibration Period. * This parameter can be can be one of the following values: * @arg RTC_SmoothCalibPeriod_32sec : The smooth calibration periode is 32s. * @arg RTC_SmoothCalibPeriod_16sec : The smooth calibration periode is 16s. * @arg RTC_SmoothCalibPeriod_8sec : The smooth calibartion periode is 8s. * @param RTC_SmoothCalibPlusPulses : Select to Set or reset the CALP bit. * This parameter can be one of the following values: * @arg RTC_SmoothCalibPlusPulses_Set : Add one RTCCLK puls every 2**11 pulses. * @arg RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added. * @param RTC_SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits. * This parameter can be one any value from 0 to 0x000001FF. * @retval An ErrorStatus enumeration value: * - SUCCESS: RTC Calib registers are configured * - ERROR: RTC Calib registers are not configured */ ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, uint32_t RTC_SmoothCalibPlusPulses, uint32_t RTC_SmouthCalibMinusPulsesValue) { ErrorStatus status = ERROR; uint32_t recalpfcount = 0; /* Check the parameters */ assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(RTC_SmoothCalibPeriod)); assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses)); assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* check if a calibration is pending*/ if ((RTC->ISR & RTC_ISR_RECALPF) != RESET) { /* wait until the Calibration is completed*/ while (((RTC->ISR & RTC_ISR_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT)) { recalpfcount++; } } /* check if the calibration pending is completed or if there is no calibration operation at all*/ if ((RTC->ISR & RTC_ISR_RECALPF) == RESET) { /* Configure the Smooth calibration settings */ RTC->CALR = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses | (uint32_t)RTC_SmouthCalibMinusPulsesValue); status = SUCCESS; } else { status = ERROR; } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; return (ErrorStatus)(status); } /** * @} */ /** @defgroup RTC_Group8 TimeStamp configuration functions * @brief TimeStamp configuration functions * @verbatim =============================================================================== TimeStamp configuration functions =============================================================================== @endverbatim * @{ */ /** * @brief Enables or Disables the RTC TimeStamp functionality with the * specified time stamp pin stimulating edge. * @param RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is * activated. * This parameter can be one of the following: * @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising * edge of the related pin. * @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the * falling edge of the related pin. * @param NewState: new state of the TimeStamp. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge)); assert_param(IS_FUNCTIONAL_STATE(NewState)); /* Get the RTC_CR register and clear the bits to be configured */ tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); /* Get the new configuration */ if (NewState != DISABLE) { tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE); } else { tmpreg |= (uint32_t)(RTC_TimeStampEdge); } /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Configure the Time Stamp TSEDGE and Enable bits */ RTC->CR = (uint32_t)tmpreg; /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; } /** * @brief Get the RTC TimeStamp value and masks. * @param RTC_Format: specifies the format of the output parameters. * This parameter can be one of the following values: * @arg RTC_Format_BIN: Binary data format * @arg RTC_Format_BCD: BCD data format * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will * contains the TimeStamp time values. * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will * contains the TimeStamp date values. * @retval None */ void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, RTC_DateTypeDef* RTC_StampDateStruct) { uint32_t tmptime = 0, tmpdate = 0; /* Check the parameters */ assert_param(IS_RTC_FORMAT(RTC_Format)); /* Get the TimeStamp time and date registers values */ tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK); tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK); /* Fill the Time structure fields with the read parameters */ RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16); RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8); RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); /* Fill the Date structure fields with the read parameters */ RTC_StampDateStruct->RTC_Year = 0; RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8); RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13); /* Check the input parameters format */ if (RTC_Format == RTC_Format_BIN) { /* Convert the Time structure parameters to Binary format */ RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours); RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes); RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds); /* Convert the Date structure parameters to Binary format */ RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month); RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date); RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay); } } /** * @brief Get the RTC timestamp Subseconds value. * @param None * @retval RTC current timestamp Subseconds value. */ uint32_t RTC_GetTimeStampSubSecond(void) { /* Get timestamp subseconds values from the correspondent registers */ return (uint32_t)(RTC->TSSSR); } /** * @} */ /** @defgroup RTC_Group9 Tampers configuration functions * @brief Tampers configuration functions * @verbatim =============================================================================== Tampers configuration functions =============================================================================== @endverbatim * @{ */ /** * @brief Configures the select Tamper pin edge. * @param RTC_Tamper: Selected tamper pin. * This parameter can be RTC_Tamper_1. * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that * stimulates tamper event. * This parameter can be one of the following values: * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event. * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event. * @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event. * @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event. * @retval None */ void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger) { /* Check the parameters */ assert_param(IS_RTC_TAMPER(RTC_Tamper)); assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger)); if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge) { /* Configure the RTC_TAFCR register */ RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1)); } else { /* Configure the RTC_TAFCR register */ RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1); } } /** * @brief Enables or Disables the Tamper detection. * @param RTC_Tamper: Selected tamper pin. * This parameter can be RTC_Tamper_1. * @param NewState: new state of the tamper pin. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RTC_TAMPER(RTC_Tamper)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected Tamper pin */ RTC->TAFCR |= (uint32_t)RTC_Tamper; } else { /* Disable the selected Tamper pin */ RTC->TAFCR &= (uint32_t)~RTC_Tamper; } } /** * @brief Configures the Tampers Filter. * @param RTC_TamperFilter: Specifies the tampers filter. * This parameter can be one of the following values: * @arg RTC_TamperFilter_Disable: Tamper filter is disabled. * @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive * samples at the active level * @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive * samples at the active level * @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive * samples at the active level * @retval None */ void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter) { /* Check the parameters */ assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter)); /* Clear TAMPFLT[1:0] bits in the RTC_TAFCR register */ RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFLT); /* Configure the RTC_TAFCR register */ RTC->TAFCR |= (uint32_t)RTC_TamperFilter; } /** * @brief Configures the Tampers Sampling Frequency. * @param RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency. * This parameter can be one of the following values: * @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled * with a frequency = RTCCLK / 32768 * @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled * with a frequency = RTCCLK / 16384 * @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled * with a frequency = RTCCLK / 8192 * @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled * with a frequency = RTCCLK / 4096 * @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled * with a frequency = RTCCLK / 2048 * @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled * with a frequency = RTCCLK / 1024 * @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled * with a frequency = RTCCLK / 512 * @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled * with a frequency = RTCCLK / 256 * @retval None */ void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq) { /* Check the parameters */ assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq)); /* Clear TAMPFREQ[2:0] bits in the RTC_TAFCR register */ RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFREQ); /* Configure the RTC_TAFCR register */ RTC->TAFCR |= (uint32_t)RTC_TamperSamplingFreq; } /** * @brief Configures the Tampers Pins input Precharge Duration. * @param RTC_TamperPrechargeDuration: Specifies the Tampers Pins input * Precharge Duration. * This parameter can be one of the following values: * @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle * @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle * @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle * @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle * @retval None */ void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration) { /* Check the parameters */ assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration)); /* Clear TAMPPRCH[1:0] bits in the RTC_TAFCR register */ RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPPRCH); /* Configure the RTC_TAFCR register */ RTC->TAFCR |= (uint32_t)RTC_TamperPrechargeDuration; } /** * @brief Enables or Disables the TimeStamp on Tamper Detection Event. * @note The timestamp is valid even the TSE bit in tamper control register * is reset. * @param NewState: new state of the timestamp on tamper event. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Save timestamp on tamper detection event */ RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPTS; } else { /* Tamper detection does not cause a timestamp to be saved */ RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPTS; } } /** * @brief Enables or Disables the Precharge of Tamper pin. * @param NewState: new state of tamper pull up. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RTC_TamperPullUpCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable precharge of the selected Tamper pin */ RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPPUDIS; } else { /* Disable precharge of the selected Tamper pin */ RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPPUDIS; } } /** * @} */ /** @defgroup RTC_Group10 Backup Data Registers configuration functions * @brief Backup Data Registers configuration functions * @verbatim =============================================================================== Backup Data Registers configuration functions =============================================================================== @endverbatim * @{ */ /** * @brief Writes a data in a specified RTC Backup data register. * @param RTC_BKP_DR: RTC Backup data Register number. * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to * specify the register. * @param Data: Data to be written in the specified RTC Backup data register. * @retval None */ void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data) { __IO uint32_t tmp = 0; /* Check the parameters */ assert_param(IS_RTC_BKP(RTC_BKP_DR)); tmp = RTC_BASE + 0x50; tmp += (RTC_BKP_DR * 4); /* Write the specified register */ *(__IO uint32_t *)tmp = (uint32_t)Data; } /** * @brief Reads data from the specified RTC Backup data Register. * @param RTC_BKP_DR: RTC Backup data Register number. * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to * specify the register. * @retval None */ uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR) { __IO uint32_t tmp = 0; /* Check the parameters */ assert_param(IS_RTC_BKP(RTC_BKP_DR)); tmp = RTC_BASE + 0x50; tmp += (RTC_BKP_DR * 4); /* Read the specified register */ return (*(__IO uint32_t *)tmp); } /** * @} */ /** @defgroup RTC_Group11 RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions * @brief RTC Tamper and TimeStamp Pins Selection and Output Type Config * configuration functions * @verbatim =============================================================================== RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions =============================================================================== @endverbatim * @{ */ /** * @brief Selects the RTC Tamper Pin. * @param RTC_TamperPin: specifies the RTC Tamper Pin. * This parameter can be one of the following values: * @arg RTC_TamperPin_PC13: PC13 is selected as RTC Tamper Pin. * @arg RTC_TamperPin_PI8: PI8 is selected as RTC Tamper Pin. * @retval None */ void RTC_TamperPinSelection(uint32_t RTC_TamperPin) { /* Check the parameters */ assert_param(IS_RTC_TAMPER_PIN(RTC_TamperPin)); RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPINSEL); RTC->TAFCR |= (uint32_t)(RTC_TamperPin); } /** * @brief Selects the RTC TimeStamp Pin. * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin. * This parameter can be one of the following values: * @arg RTC_TimeStampPin_PC13: PC13 is selected as RTC TimeStamp Pin. * @arg RTC_TimeStampPin_PI8: PI8 is selected as RTC TimeStamp Pin. * @retval None */ void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin) { /* Check the parameters */ assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TSINSEL); RTC->TAFCR |= (uint32_t)(RTC_TimeStampPin); } /** * @brief Configures the RTC Output Pin mode. * @param RTC_OutputType: specifies the RTC Output (PC13) pin mode. * This parameter can be one of the following values: * @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in * Open Drain mode. * @arg RTC_OutputType_PushPull: RTC Output (PC13) is configured in * Push Pull mode. * @retval None */ void RTC_OutputTypeConfig(uint32_t RTC_OutputType) { /* Check the parameters */ assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType)); RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE); RTC->TAFCR |= (uint32_t)(RTC_OutputType); } /** * @} */ /** @defgroup RTC_Group12 Shift control synchronisation functions * @brief Shift control synchronisation functions * @verbatim =============================================================================== Shift control synchronisation functions =============================================================================== @endverbatim * @{ */ /** * @brief Configures the Synchronization Shift Control Settings. * @note When REFCKON is set, firmware must not write to Shift control register * @param RTC_ShiftAdd1S : Select to add or not 1 second to the time Calendar. * This parameter can be one of the following values : * @arg RTC_ShiftAdd1S_Set : Add one second to the clock calendar. * @arg RTC_ShiftAdd1S_Reset: No effect. * @param RTC_ShiftSubFS: Select the number of Second Fractions to Substitute. * This parameter can be one any value from 0 to 0x7FFF. * @retval An ErrorStatus enumeration value: * - SUCCESS: RTC Shift registers are configured * - ERROR: RTC Shift registers are not configured */ ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS) { ErrorStatus status = ERROR; uint32_t shpfcount = 0; /* Check the parameters */ assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S)); assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Check if a Shift is pending*/ if ((RTC->ISR & RTC_ISR_SHPF) != RESET) { /* Wait until the shift is completed*/ while (((RTC->ISR & RTC_ISR_SHPF) != RESET) && (shpfcount != SHPF_TIMEOUT)) { shpfcount++; } } /* Check if the Shift pending is completed or if there is no Shift operation at all*/ if ((RTC->ISR & RTC_ISR_SHPF) == RESET) { /* check if the reference clock detection is disabled */ if((RTC->CR & RTC_CR_REFCKON) == RESET) { /* Configure the Shift settings */ RTC->SHIFTR = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S); if(RTC_WaitForSynchro() == ERROR) { status = ERROR; } else { status = SUCCESS; } } else { status = ERROR; } } else { status = ERROR; } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; return (ErrorStatus)(status); } /** * @} */ /** @defgroup RTC_Group13 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== Interrupts and flags management functions =============================================================================== All RTC interrupts are connected to the EXTI controller. - To enable the RTC Alarm interrupt, the following sequence is required: - Configure and enable the EXTI Line 17 in interrupt mode and select the rising edge sensitivity using the EXTI_Init() function. - Configure and enable the RTC_Alarm IRQ channel in the NVIC using the NVIC_Init() function. - Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) using the RTC_SetAlarm() and RTC_AlarmCmd() functions. - To enable the RTC Wakeup interrupt, the following sequence is required: - Configure and enable the EXTI Line 22 in interrupt mode and select the rising edge sensitivity using the EXTI_Init() function. - Configure and enable the RTC_WKUP IRQ channel in the NVIC using the NVIC_Init() function. - Configure the RTC to generate the RTC wakeup timer event using the RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. - To enable the RTC Tamper interrupt, the following sequence is required: - Configure and enable the EXTI Line 21 in interrupt mode and select the rising edge sensitivity using the EXTI_Init() function. - Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init() function. - Configure the RTC to detect the RTC tamper event using the RTC_TamperTriggerConfig() and RTC_TamperCmd() functions. - To enable the RTC TimeStamp interrupt, the following sequence is required: - Configure and enable the EXTI Line 21 in interrupt mode and select the rising edge sensitivity using the EXTI_Init() function. - Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init() function. - Configure the RTC to detect the RTC time-stamp event using the RTC_TimeStampCmd() functions. @endverbatim * @{ */ /** * @brief Enables or disables the specified RTC interrupts. * @param RTC_IT: specifies the RTC interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg RTC_IT_TS: Time Stamp interrupt mask * @arg RTC_IT_WUT: WakeUp Timer interrupt mask * @arg RTC_IT_ALRB: Alarm B interrupt mask * @arg RTC_IT_ALRA: Alarm A interrupt mask * @arg RTC_IT_TAMP: Tamper event interrupt mask * @param NewState: new state of the specified RTC interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RTC_CONFIG_IT(RTC_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; if (NewState != DISABLE) { /* Configure the Interrupts in the RTC_CR register */ RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE); /* Configure the Tamper Interrupt in the RTC_TAFCR */ RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE); } else { /* Configure the Interrupts in the RTC_CR register */ RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE); /* Configure the Tamper Interrupt in the RTC_TAFCR */ RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE); } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; } /** * @brief Checks whether the specified RTC flag is set or not. * @param RTC_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg RTC_FLAG_RECALPF: RECALPF event flag. * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag * @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag * @arg RTC_FLAG_TSF: Time Stamp event flag * @arg RTC_FLAG_WUTF: WakeUp Timer flag * @arg RTC_FLAG_ALRBF: Alarm B flag * @arg RTC_FLAG_ALRAF: Alarm A flag * @arg RTC_FLAG_INITF: Initialization mode flag * @arg RTC_FLAG_RSF: Registers Synchronized flag * @arg RTC_FLAG_INITS: Registers Configured flag * @arg RTC_FLAG_SHPF: Shift operation pending flag. * @arg RTC_FLAG_WUTWF: WakeUp Timer Write flag * @arg RTC_FLAG_ALRBWF: Alarm B Write flag * @arg RTC_FLAG_ALRAWF: Alarm A write flag * @retval The new state of RTC_FLAG (SET or RESET). */ FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG) { FlagStatus bitstatus = RESET; uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); /* Get all the flags */ tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK); /* Return the status of the flag */ if ((tmpreg & RTC_FLAG) != (uint32_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears the RTC's pending flags. * @param RTC_FLAG: specifies the RTC flag to clear. * This parameter can be any combination of the following values: * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag * @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag * @arg RTC_FLAG_TSF: Time Stamp event flag * @arg RTC_FLAG_WUTF: WakeUp Timer flag * @arg RTC_FLAG_ALRBF: Alarm B flag * @arg RTC_FLAG_ALRAF: Alarm A flag * @arg RTC_FLAG_RSF: Registers Synchronized flag * @retval None */ void RTC_ClearFlag(uint32_t RTC_FLAG) { /* Check the parameters */ assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); /* Clear the Flags in the RTC_ISR register */ RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); } /** * @brief Checks whether the specified RTC interrupt has occurred or not. * @param RTC_IT: specifies the RTC interrupt source to check. * This parameter can be one of the following values: * @arg RTC_IT_TS: Time Stamp interrupt * @arg RTC_IT_WUT: WakeUp Timer interrupt * @arg RTC_IT_ALRB: Alarm B interrupt * @arg RTC_IT_ALRA: Alarm A interrupt * @arg RTC_IT_TAMP1: Tamper 1 event interrupt * @retval The new state of RTC_IT (SET or RESET). */ ITStatus RTC_GetITStatus(uint32_t RTC_IT) { ITStatus bitstatus = RESET; uint32_t tmpreg = 0, enablestatus = 0; /* Check the parameters */ assert_param(IS_RTC_GET_IT(RTC_IT)); /* Get the TAMPER Interrupt enable bit and pending bit */ tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE)); /* Get the Interrupt enable Status */ enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & (RTC_IT >> 15))); /* Get the Interrupt pending bit */ tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4))); /* Get the status of the Interrupt */ if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET)) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears the RTC's interrupt pending bits. * @param RTC_IT: specifies the RTC interrupt pending bit to clear. * This parameter can be any combination of the following values: * @arg RTC_IT_TS: Time Stamp interrupt * @arg RTC_IT_WUT: WakeUp Timer interrupt * @arg RTC_IT_ALRB: Alarm B interrupt * @arg RTC_IT_ALRA: Alarm A interrupt * @arg RTC_IT_TAMP1: Tamper 1 event interrupt * @retval None */ void RTC_ClearITPendingBit(uint32_t RTC_IT) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RTC_CLEAR_IT(RTC_IT)); /* Get the RTC_ISR Interrupt pending bits mask */ tmpreg = (uint32_t)(RTC_IT >> 4); /* Clear the interrupt pending bits in the RTC_ISR register */ RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); } /** * @} */ /** * @brief Converts a 2 digit decimal to BCD format. * @param Value: Byte to be converted. * @retval Converted byte */ static uint8_t RTC_ByteToBcd2(uint8_t Value) { uint8_t bcdhigh = 0; while (Value >= 10) { bcdhigh++; Value -= 10; } return ((uint8_t)(bcdhigh << 4) | Value); } /** * @brief Convert from 2 digit BCD to Binary. * @param Value: BCD value to be converted. * @retval Converted word */ static uint8_t RTC_Bcd2ToByte(uint8_t Value) { uint8_t tmp = 0; tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; return (tmp + (Value & (uint8_t)0x0F)); } /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sdio.c ================================================ /** ****************************************************************************** * @file stm32f4xx_sdio.c * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file provides firmware functions to manage the following * functionalities of the Secure digital input/output interface (SDIO) * peripheral: * - Initialization and Configuration * - Command path state machine (CPSM) management * - Data path state machine (DPSM) management * - SDIO IO Cards mode management * - CE-ATA mode management * - DMA transfers management * - Interrupts and flags management * * @verbatim * * * =================================================================== * How to use this driver * =================================================================== * 1. The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output * of PLL (PLL48CLK). Before to start working with SDIO peripheral * make sure that the PLL is well configured. * The SDIO peripheral uses two clock signals: * - SDIO adapter clock (SDIOCLK = 48 MHz) * - APB2 bus clock (PCLK2) * PCLK2 and SDIO_CK clock frequencies must respect the following condition: * Frequenc(PCLK2) >= (3 / 8 x Frequency(SDIO_CK)) * * 2. Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE). * * 3. According to the SDIO mode, enable the GPIO clocks using * RCC_AHB1PeriphClockCmd() function. * The I/O can be one of the following configurations: * - 1-bit data length: SDIO_CMD, SDIO_CK and D0. * - 4-bit data length: SDIO_CMD, SDIO_CK and D[3:0]. * - 8-bit data length: SDIO_CMD, SDIO_CK and D[7:0]. * * 4. Peripheral's alternate function: * - Connect the pin to the desired peripherals' Alternate * Function (AF) using GPIO_PinAFConfig() function * - Configure the desired pin in alternate function by: * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF * - Select the type, pull-up/pull-down and output speed via * GPIO_PuPd, GPIO_OType and GPIO_Speed members * - Call GPIO_Init() function * * 5. Program the Clock Edge, Clock Bypass, Clock Power Save, Bus Wide, * hardware, flow control and the Clock Divider using the SDIO_Init() * function. * * 6. Enable the Power ON State using the SDIO_SetPowerState(SDIO_PowerState_ON) * function. * * 7. Enable the clock using the SDIO_ClockCmd() function. * * 8. Enable the NVIC and the corresponding interrupt using the function * SDIO_ITConfig() if you need to use interrupt mode. * * 9. When using the DMA mode * - Configure the DMA using DMA_Init() function * - Active the needed channel Request using SDIO_DMACmd() function * * 10. Enable the DMA using the DMA_Cmd() function, when using DMA mode. * * 11. To control the CPSM (Command Path State Machine) and send * commands to the card use the SDIO_SendCommand(), * SDIO_GetCommandResponse() and SDIO_GetResponse() functions. * First, user has to fill the command structure (pointer to * SDIO_CmdInitTypeDef) according to the selected command to be sent. * The parameters that should be filled are: * - Command Argument * - Command Index * - Command Response type * - Command Wait * - CPSM Status (Enable or Disable) * * To check if the command is well received, read the SDIO_CMDRESP * register using the SDIO_GetCommandResponse(). * The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the * SDIO_GetResponse() function. * * 12. To control the DPSM (Data Path State Machine) and send/receive * data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(), * SDIO_ReadData(), SDIO_WriteData() and SDIO_GetFIFOCount() functions. * * Read Operations * --------------- * a) First, user has to fill the data structure (pointer to * SDIO_DataInitTypeDef) according to the selected data type to * be received. * The parameters that should be filled are: * - Data TimeOut * - Data Length * - Data Block size * - Data Transfer direction: should be from card (To SDIO) * - Data Transfer mode * - DPSM Status (Enable or Disable) * * b) Configure the SDIO resources to receive the data from the card * according to selected transfer mode (Refer to Step 8, 9 and 10). * * c) Send the selected Read command (refer to step 11). * * d) Use the SDIO flags/interrupts to check the transfer status. * * Write Operations * --------------- * a) First, user has to fill the data structure (pointer to * SDIO_DataInitTypeDef) according to the selected data type to * be received. * The parameters that should be filled are: * - Data TimeOut * - Data Length * - Data Block size * - Data Transfer direction: should be to card (To CARD) * - Data Transfer mode * - DPSM Status (Enable or Disable) * * b) Configure the SDIO resources to send the data to the card * according to selected transfer mode (Refer to Step 8, 9 and 10). * * c) Send the selected Write command (refer to step 11). * * d) Use the SDIO flags/interrupts to check the transfer status. * * * @endverbatim * * ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_sdio.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup SDIO * @brief SDIO driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* ------------ SDIO registers bit address in the alias region ----------- */ #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) /* --- CLKCR Register ---*/ /* Alias word address of CLKEN bit */ #define CLKCR_OFFSET (SDIO_OFFSET + 0x04) #define CLKEN_BitNumber 0x08 #define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4)) /* --- CMD Register ---*/ /* Alias word address of SDIOSUSPEND bit */ #define CMD_OFFSET (SDIO_OFFSET + 0x0C) #define SDIOSUSPEND_BitNumber 0x0B #define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4)) /* Alias word address of ENCMDCOMPL bit */ #define ENCMDCOMPL_BitNumber 0x0C #define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4)) /* Alias word address of NIEN bit */ #define NIEN_BitNumber 0x0D #define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4)) /* Alias word address of ATACMD bit */ #define ATACMD_BitNumber 0x0E #define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) /* --- DCTRL Register ---*/ /* Alias word address of DMAEN bit */ #define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) #define DMAEN_BitNumber 0x03 #define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) /* Alias word address of RWSTART bit */ #define RWSTART_BitNumber 0x08 #define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4)) /* Alias word address of RWSTOP bit */ #define RWSTOP_BitNumber 0x09 #define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) /* Alias word address of RWMOD bit */ #define RWMOD_BitNumber 0x0A #define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4)) /* Alias word address of SDIOEN bit */ #define SDIOEN_BitNumber 0x0B #define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4)) /* ---------------------- SDIO registers bit mask ------------------------ */ /* --- CLKCR Register ---*/ /* CLKCR register clear mask */ #define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) /* --- PWRCTRL Register ---*/ /* SDIO PWRCTRL Mask */ #define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) /* --- DCTRL Register ---*/ /* SDIO DCTRL Clear Mask */ #define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) /* --- CMD Register ---*/ /* CMD Register clear mask */ #define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) /* SDIO RESP Registers Address */ #define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup SDIO_Private_Functions * @{ */ /** @defgroup SDIO_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== Initialization and Configuration functions =============================================================================== @endverbatim * @{ */ /** * @brief Deinitializes the SDIO peripheral registers to their default reset values. * @param None * @retval None */ void SDIO_DeInit(void) { RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, DISABLE); } /** * @brief Initializes the SDIO peripheral according to the specified * parameters in the SDIO_InitStruct. * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure * that contains the configuration information for the SDIO peripheral. * @retval None */ void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge)); assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass)); assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave)); assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide)); assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); /*---------------------------- SDIO CLKCR Configuration ------------------------*/ /* Get the SDIO CLKCR value */ tmpreg = SDIO->CLKCR; /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ tmpreg &= CLKCR_CLEAR_MASK; /* Set CLKDIV bits according to SDIO_ClockDiv value */ /* Set PWRSAV bit according to SDIO_ClockPowerSave value */ /* Set BYPASS bit according to SDIO_ClockBypass value */ /* Set WIDBUS bits according to SDIO_BusWide value */ /* Set NEGEDGE bits according to SDIO_ClockEdge value */ /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */ tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave | SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide | SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); /* Write to SDIO CLKCR */ SDIO->CLKCR = tmpreg; } /** * @brief Fills each SDIO_InitStruct member with its default value. * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which * will be initialized. * @retval None */ void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct) { /* SDIO_InitStruct members default value */ SDIO_InitStruct->SDIO_ClockDiv = 0x00; SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising; SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable; SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b; SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; } /** * @brief Enables or disables the SDIO Clock. * @param NewState: new state of the SDIO Clock. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SDIO_ClockCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState; } /** * @brief Sets the power status of the controller. * @param SDIO_PowerState: new state of the Power state. * This parameter can be one of the following values: * @arg SDIO_PowerState_OFF: SDIO Power OFF * @arg SDIO_PowerState_ON: SDIO Power ON * @retval None */ void SDIO_SetPowerState(uint32_t SDIO_PowerState) { /* Check the parameters */ assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState)); SDIO->POWER = SDIO_PowerState; } /** * @brief Gets the power status of the controller. * @param None * @retval Power status of the controller. The returned value can be one of the * following values: * - 0x00: Power OFF * - 0x02: Power UP * - 0x03: Power ON */ uint32_t SDIO_GetPowerState(void) { return (SDIO->POWER & (~PWR_PWRCTRL_MASK)); } /** * @} */ /** @defgroup SDIO_Group2 Command path state machine (CPSM) management functions * @brief Command path state machine (CPSM) management functions * @verbatim =============================================================================== Command path state machine (CPSM) management functions =============================================================================== This section provide functions allowing to program and read the Command path state machine (CPSM). @endverbatim * @{ */ /** * @brief Initializes the SDIO Command according to the specified * parameters in the SDIO_CmdInitStruct and send the command. * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef * structure that contains the configuration information for the SDIO * command. * @retval None */ void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex)); assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response)); assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait)); assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM)); /*---------------------------- SDIO ARG Configuration ------------------------*/ /* Set the SDIO Argument value */ SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; /*---------------------------- SDIO CMD Configuration ------------------------*/ /* Get the SDIO CMD value */ tmpreg = SDIO->CMD; /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */ tmpreg &= CMD_CLEAR_MASK; /* Set CMDINDEX bits according to SDIO_CmdIndex value */ /* Set WAITRESP bits according to SDIO_Response value */ /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */ /* Set CPSMEN bits according to SDIO_CPSM value */ tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM; /* Write to SDIO CMD */ SDIO->CMD = tmpreg; } /** * @brief Fills each SDIO_CmdInitStruct member with its default value. * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef * structure which will be initialized. * @retval None */ void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct) { /* SDIO_CmdInitStruct members default value */ SDIO_CmdInitStruct->SDIO_Argument = 0x00; SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; } /** * @brief Returns command index of last command for which response received. * @param None * @retval Returns the command index of the last command response received. */ uint8_t SDIO_GetCommandResponse(void) { return (uint8_t)(SDIO->RESPCMD); } /** * @brief Returns response received from the card for the last command. * @param SDIO_RESP: Specifies the SDIO response register. * This parameter can be one of the following values: * @arg SDIO_RESP1: Response Register 1 * @arg SDIO_RESP2: Response Register 2 * @arg SDIO_RESP3: Response Register 3 * @arg SDIO_RESP4: Response Register 4 * @retval The Corresponding response register value. */ uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) { __IO uint32_t tmp = 0; /* Check the parameters */ assert_param(IS_SDIO_RESP(SDIO_RESP)); tmp = SDIO_RESP_ADDR + SDIO_RESP; return (*(__IO uint32_t *) tmp); } /** * @} */ /** @defgroup SDIO_Group3 Data path state machine (DPSM) management functions * @brief Data path state machine (DPSM) management functions * @verbatim =============================================================================== Data path state machine (DPSM) management functions =============================================================================== This section provide functions allowing to program and read the Data path state machine (DPSM). @endverbatim * @{ */ /** * @brief Initializes the SDIO data path according to the specified * parameters in the SDIO_DataInitStruct. * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure * that contains the configuration information for the SDIO command. * @retval None */ void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength)); assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize)); assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir)); assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode)); assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM)); /*---------------------------- SDIO DTIMER Configuration ---------------------*/ /* Set the SDIO Data TimeOut value */ SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut; /*---------------------------- SDIO DLEN Configuration -----------------------*/ /* Set the SDIO DataLength value */ SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength; /*---------------------------- SDIO DCTRL Configuration ----------------------*/ /* Get the SDIO DCTRL value */ tmpreg = SDIO->DCTRL; /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */ tmpreg &= DCTRL_CLEAR_MASK; /* Set DEN bit according to SDIO_DPSM value */ /* Set DTMODE bit according to SDIO_TransferMode value */ /* Set DTDIR bit according to SDIO_TransferDir value */ /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */ tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; /* Write to SDIO DCTRL */ SDIO->DCTRL = tmpreg; } /** * @brief Fills each SDIO_DataInitStruct member with its default value. * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure * which will be initialized. * @retval None */ void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct) { /* SDIO_DataInitStruct members default value */ SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; SDIO_DataInitStruct->SDIO_DataLength = 0x00; SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; } /** * @brief Returns number of remaining data bytes to be transferred. * @param None * @retval Number of remaining data bytes to be transferred */ uint32_t SDIO_GetDataCounter(void) { return SDIO->DCOUNT; } /** * @brief Read one data word from Rx FIFO. * @param None * @retval Data received */ uint32_t SDIO_ReadData(void) { return SDIO->FIFO; } /** * @brief Write one data word to Tx FIFO. * @param Data: 32-bit data word to write. * @retval None */ void SDIO_WriteData(uint32_t Data) { SDIO->FIFO = Data; } /** * @brief Returns the number of words left to be written to or read from FIFO. * @param None * @retval Remaining number of words. */ uint32_t SDIO_GetFIFOCount(void) { return SDIO->FIFOCNT; } /** * @} */ /** @defgroup SDIO_Group4 SDIO IO Cards mode management functions * @brief SDIO IO Cards mode management functions * @verbatim =============================================================================== SDIO IO Cards mode management functions =============================================================================== This section provide functions allowing to program and read the SDIO IO Cards. @endverbatim * @{ */ /** * @brief Starts the SD I/O Read Wait operation. * @param NewState: new state of the Start SDIO Read Wait operation. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SDIO_StartSDIOReadWait(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState; } /** * @brief Stops the SD I/O Read Wait operation. * @param NewState: new state of the Stop SDIO Read Wait operation. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SDIO_StopSDIOReadWait(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState; } /** * @brief Sets one of the two options of inserting read wait interval. * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode. * This parameter can be: * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2 * @retval None */ void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) { /* Check the parameters */ assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode; } /** * @brief Enables or disables the SD I/O Mode Operation. * @param NewState: new state of SDIO specific operation. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SDIO_SetSDIOOperation(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState; } /** * @brief Enables or disables the SD I/O Mode suspend command sending. * @param NewState: new state of the SD I/O Mode suspend command. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState; } /** * @} */ /** @defgroup SDIO_Group5 CE-ATA mode management functions * @brief CE-ATA mode management functions * @verbatim =============================================================================== CE-ATA mode management functions =============================================================================== This section provide functions allowing to program and read the CE-ATA card. @endverbatim * @{ */ /** * @brief Enables or disables the command completion signal. * @param NewState: new state of command completion signal. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SDIO_CommandCompletionCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState; } /** * @brief Enables or disables the CE-ATA interrupt. * @param NewState: new state of CE-ATA interrupt. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SDIO_CEATAITCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1)); } /** * @brief Sends CE-ATA command (CMD61). * @param NewState: new state of CE-ATA command. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SDIO_SendCEATACmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState; } /** * @} */ /** @defgroup SDIO_Group6 DMA transfers management functions * @brief DMA transfers management functions * @verbatim =============================================================================== DMA transfers management functions =============================================================================== This section provide functions allowing to program SDIO DMA transfer. @endverbatim * @{ */ /** * @brief Enables or disables the SDIO DMA request. * @param NewState: new state of the selected SDIO DMA request. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SDIO_DMACmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState; } /** * @} */ /** @defgroup SDIO_Group7 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== Interrupts and flags management functions =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables the SDIO interrupts. * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled. * This parameter can be one or a combination of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide * bus mode interrupt * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt * @arg SDIO_IT_TXACT: Data transmit in progress interrupt * @arg SDIO_IT_RXACT: Data receive in progress interrupt * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt * @param NewState: new state of the specified SDIO interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_SDIO_IT(SDIO_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the SDIO interrupts */ SDIO->MASK |= SDIO_IT; } else { /* Disable the SDIO interrupts */ SDIO->MASK &= ~SDIO_IT; } } /** * @brief Checks whether the specified SDIO flag is set or not. * @param SDIO_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) * @arg SDIO_FLAG_CTIMEOUT: Command response timeout * @arg SDIO_FLAG_DTIMEOUT: Data timeout * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode. * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) * @arg SDIO_FLAG_CMDACT: Command transfer in progress * @arg SDIO_FLAG_TXACT: Data transmit in progress * @arg SDIO_FLAG_RXACT: Data receive in progress * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 * @retval The new state of SDIO_FLAG (SET or RESET). */ FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_SDIO_FLAG(SDIO_FLAG)); if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears the SDIO's pending flags. * @param SDIO_FLAG: specifies the flag to clear. * This parameter can be one or a combination of the following values: * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) * @arg SDIO_FLAG_CTIMEOUT: Command response timeout * @arg SDIO_FLAG_DTIMEOUT: Data timeout * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 * @retval None */ void SDIO_ClearFlag(uint32_t SDIO_FLAG) { /* Check the parameters */ assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG)); SDIO->ICR = SDIO_FLAG; } /** * @brief Checks whether the specified SDIO interrupt has occurred or not. * @param SDIO_IT: specifies the SDIO interrupt source to check. * This parameter can be one of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide * bus mode interrupt * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt * @arg SDIO_IT_TXACT: Data transmit in progress interrupt * @arg SDIO_IT_RXACT: Data receive in progress interrupt * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt * @retval The new state of SDIO_IT (SET or RESET). */ ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) { ITStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_SDIO_GET_IT(SDIO_IT)); if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears the SDIO's interrupt pending bits. * @param SDIO_IT: specifies the interrupt pending bit to clear. * This parameter can be one or a combination of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide * bus mode interrupt * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 * @retval None */ void SDIO_ClearITPendingBit(uint32_t SDIO_IT) { /* Check the parameters */ assert_param(IS_SDIO_CLEAR_IT(SDIO_IT)); SDIO->ICR = SDIO_IT; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c ================================================ /** ****************************************************************************** * @file stm32f4xx_spi.c * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file provides firmware functions to manage the following * functionalities of the Serial peripheral interface (SPI): * - Initialization and Configuration * - Data transfers functions * - Hardware CRC Calculation * - DMA transfers management * - Interrupts and flags management * * @verbatim * * * =================================================================== * How to use this driver * =================================================================== * * 1. Enable peripheral clock using the following functions * RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) for SPI1 * RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) for SPI2 * RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI3. * * 2. Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHB1PeriphClockCmd() * function. * In I2S mode, if an external clock source is used then the I2S CKIN pin GPIO * clock should also be enabled. * * 3. Peripherals alternate function: * - Connect the pin to the desired peripherals' Alternate * Function (AF) using GPIO_PinAFConfig() function * - Configure the desired pin in alternate function by: * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF * - Select the type, pull-up/pull-down and output speed via * GPIO_PuPd, GPIO_OType and GPIO_Speed members * - Call GPIO_Init() function * In I2S mode, if an external clock source is used then the I2S CKIN pin * should be also configured in Alternate function Push-pull pull-up mode. * * 4. Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave * Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() * function. * In I2S mode, program the Mode, Standard, Data Format, MCLK Output, Audio * frequency and Polarity using I2S_Init() function. * For I2S mode, make sure that either: * - I2S PLL is configured using the functions RCC_I2SCLKConfig(RCC_I2S2CLKSource_PLLI2S), * RCC_PLLI2SCmd(ENABLE) and RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY). * or * - External clock source is configured using the function * RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly the define constant * I2S_EXTERNAL_CLOCK_VAL in the stm32f4xx_conf.h file. * * 5. Enable the NVIC and the corresponding interrupt using the function * SPI_ITConfig() if you need to use interrupt mode. * * 6. When using the DMA mode * - Configure the DMA using DMA_Init() function * - Active the needed channel Request using SPI_I2S_DMACmd() function * * 7. Enable the SPI using the SPI_Cmd() function or enable the I2S using * I2S_Cmd(). * * 8. Enable the DMA using the DMA_Cmd() function when using DMA mode. * * 9. Optionally, you can enable/configure the following parameters without * re-initialization (i.e there is no need to call again SPI_Init() function): * - When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx) * is programmed as Data direction parameter using the SPI_Init() function * it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx * using the SPI_BiDirectionalLineConfig() function. * - When SPI_NSS_Soft is selected as Slave Select Management parameter * using the SPI_Init() function it can be possible to manage the * NSS internal signal using the SPI_NSSInternalSoftwareConfig() function. * - Reconfigure the data size using the SPI_DataSizeConfig() function * - Enable or disable the SS output using the SPI_SSOutputCmd() function * * 10. To use the CRC Hardware calculation feature refer to the Peripheral * CRC hardware Calculation subsection. * * * It is possible to use SPI in I2S full duplex mode, in this case, each SPI * peripheral is able to manage sending and receiving data simultaneously * using two data lines. Each SPI peripheral has an extended block called I2Sxext * (ie. I2S2ext for SPI2 and I2S3ext for SPI3). * The extension block is not a full SPI IP, it is used only as I2S slave to * implement full duplex mode. The extension block uses the same clock sources * as its master. * To configure I2S full duplex you have to: * * 1. Configure SPIx in I2S mode (I2S_Init() function) as described above. * * 2. Call the I2S_FullDuplexConfig() function using the same strucutre passed to * I2S_Init() function. * * 3. Call I2S_Cmd() for SPIx then for its extended block. * * 4. To configure interrupts or DMA requests and to get/clear flag status, * use I2Sxext instance for the extension block. * * Functions that can be called with I2Sxext instances are: * I2S_Cmd(), I2S_FullDuplexConfig(), SPI_I2S_ReceiveData(), SPI_I2S_SendData(), * SPI_I2S_DMACmd(), SPI_I2S_ITConfig(), SPI_I2S_GetFlagStatus(), SPI_I2S_ClearFlag(), * SPI_I2S_GetITStatus() and SPI_I2S_ClearITPendingBit(). * * Example: To use SPI3 in Full duplex mode (SPI3 is Master Tx, I2S3ext is Slave Rx): * * RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE); * I2S_StructInit(&I2SInitStruct); * I2SInitStruct.Mode = I2S_Mode_MasterTx; * I2S_Init(SPI3, &I2SInitStruct); * I2S_FullDuplexConfig(SPI3ext, &I2SInitStruct) * I2S_Cmd(SPI3, ENABLE); * I2S_Cmd(SPI3ext, ENABLE); * ... * while (SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET) * {} * SPI_I2S_SendData(SPI3, txdata[i]); * ... * while (SPI_I2S_GetFlagStatus(I2S3ext, SPI_FLAG_RXNE) == RESET) * {} * rxdata[i] = SPI_I2S_ReceiveData(I2S3ext); * ... * * * @note In I2S mode: if an external clock is used as source clock for the I2S, * then the define I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should * be enabled and set to the value of the source clock frequency (in Hz). * * @note In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd() * just after calling the function SPI_Init(). * * @endverbatim * ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_spi.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup SPI * @brief SPI driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* SPI registers Masks */ #define CR1_CLEAR_MASK ((uint16_t)0x3040) #define I2SCFGR_CLEAR_MASK ((uint16_t)0xF040) /* RCC PLLs masks */ #define PLLCFGR_PPLR_MASK ((uint32_t)0x70000000) #define PLLCFGR_PPLN_MASK ((uint32_t)0x00007FC0) #define SPI_CR2_FRF ((uint16_t)0x0010) #define SPI_SR_TIFRFE ((uint16_t)0x0100) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup SPI_Private_Functions * @{ */ /** @defgroup SPI_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== Initialization and Configuration functions =============================================================================== This section provides a set of functions allowing to initialize the SPI Direction, SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud Rate Prescaler, SPI First Bit and SPI CRC Polynomial. The SPI_Init() function follows the SPI configuration procedures for Master mode and Slave mode (details for these procedures are available in reference manual (RM0090)). @endverbatim * @{ */ /** * @brief Deinitialize the SPIx peripheral registers to their default reset values. * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 * in SPI mode or 2 or 3 in I2S mode. * * @note The extended I2S blocks (ie. I2S2ext and I2S3ext blocks) are deinitialized * when the relative I2S peripheral is deinitialized (the extended block's clock * is managed by the I2S peripheral clock). * * @retval None */ void SPI_I2S_DeInit(SPI_TypeDef* SPIx) { /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH(SPIx)); if (SPIx == SPI1) { /* Enable SPI1 reset state */ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); /* Release SPI1 from reset state */ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); } else if (SPIx == SPI2) { /* Enable SPI2 reset state */ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); /* Release SPI2 from reset state */ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); } else { if (SPIx == SPI3) { /* Enable SPI3 reset state */ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); /* Release SPI3 from reset state */ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); } } } /** * @brief Initializes the SPIx peripheral according to the specified * parameters in the SPI_InitStruct. * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that * contains the configuration information for the specified SPI peripheral. * @retval None */ void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) { uint16_t tmpreg = 0; /* check the parameters */ assert_param(IS_SPI_ALL_PERIPH(SPIx)); /* Check the SPI parameters */ assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); /*---------------------------- SPIx CR1 Configuration ------------------------*/ /* Get the SPIx CR1 value */ tmpreg = SPIx->CR1; /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ tmpreg &= CR1_CLEAR_MASK; /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler master/salve mode, CPOL and CPHA */ /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ /* Set LSBFirst bit according to SPI_FirstBit value */ /* Set BR bits according to SPI_BaudRatePrescaler value */ /* Set CPOL bit according to SPI_CPOL value */ /* Set CPHA bit according to SPI_CPHA value */ tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); /* Write to SPIx CR1 */ SPIx->CR1 = tmpreg; /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD); /*---------------------------- SPIx CRCPOLY Configuration --------------------*/ /* Write to SPIx CRCPOLY */ SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; } /** * @brief Initializes the SPIx peripheral according to the specified * parameters in the I2S_InitStruct. * @param SPIx: where x can be 2 or 3 to select the SPI peripheral (configured in I2S mode). * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that * contains the configuration information for the specified SPI peripheral * configured in I2S mode. * * @note The function calculates the optimal prescaler needed to obtain the most * accurate audio frequency (depending on the I2S clock source, the PLL values * and the product configuration). But in case the prescaler value is greater * than 511, the default value (0x02) will be configured instead. * * @note if an external clock is used as source clock for the I2S, then the define * I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should be enabled and set * to the value of the the source clock frequency (in Hz). * * @retval None */ void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) { uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; uint32_t tmp = 0, i2sclk = 0; #ifndef I2S_EXTERNAL_CLOCK_VAL uint32_t pllm = 0, plln = 0, pllr = 0; #endif /* I2S_EXTERNAL_CLOCK_VAL */ /* Check the I2S parameters */ assert_param(IS_SPI_23_PERIPH(SPIx)); assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ SPIx->I2SCFGR &= I2SCFGR_CLEAR_MASK; SPIx->I2SPR = 0x0002; /* Get the I2SCFGR register value */ tmpreg = SPIx->I2SCFGR; /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) { i2sodd = (uint16_t)0; i2sdiv = (uint16_t)2; } /* If the requested audio frequency is not the default, compute the prescaler */ else { /* Check the frame length (For the Prescaler computing) *******************/ if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) { /* Packet length is 16 bits */ packetlength = 1; } else { /* Packet length is 32 bits */ packetlength = 2; } /* Get I2S source Clock frequency ****************************************/ /* If an external I2S clock has to be used, this define should be set in the project configuration or in the stm32f4xx_conf.h file */ #ifdef I2S_EXTERNAL_CLOCK_VAL /* Set external clock as I2S clock source */ if ((RCC->CFGR & RCC_CFGR_I2SSRC) == 0) { RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC; } /* Set the I2S clock to the external clock value */ i2sclk = I2S_EXTERNAL_CLOCK_VAL; #else /* There is no define for External I2S clock source */ /* Set PLLI2S as I2S clock source */ if ((RCC->CFGR & RCC_CFGR_I2SSRC) != 0) { RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC; } /* Get the PLLI2SN value */ plln = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & \ (RCC_PLLI2SCFGR_PLLI2SN >> 6)); /* Get the PLLI2SR value */ pllr = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & \ (RCC_PLLI2SCFGR_PLLI2SR >> 28)); /* Get the PLLM value */ pllm = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); /* Get the I2S source clock value */ i2sclk = (uint32_t)(((HSE_VALUE / pllm) * plln) / pllr); #endif /* I2S_EXTERNAL_CLOCK_VAL */ /* Compute the Real divider depending on the MCLK output state, with a floating point */ if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) { /* MCLK output is enabled */ tmp = (uint16_t)(((((i2sclk / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); } else { /* MCLK output is disabled */ tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5); } /* Remove the flatting point */ tmp = tmp / 10; /* Check the parity of the divider */ i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); /* Compute the i2sdiv prescaler */ i2sdiv = (uint16_t)((tmp - i2sodd) / 2); /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ i2sodd = (uint16_t) (i2sodd << 8); } /* Test if the divider is 1 or 0 or greater than 0xFF */ if ((i2sdiv < 2) || (i2sdiv > 0xFF)) { /* Set the default values */ i2sdiv = 2; i2sodd = 0; } /* Write to SPIx I2SPR register the computed value */ SPIx->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); /* Configure the I2S with the SPI_InitStruct values */ tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \ (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ (uint16_t)I2S_InitStruct->I2S_CPOL)))); /* Write to SPIx I2SCFGR */ SPIx->I2SCFGR = tmpreg; } /** * @brief Fills each SPI_InitStruct member with its default value. * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized. * @retval None */ void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) { /*--------------- Reset SPI init structure parameters values -----------------*/ /* Initialize the SPI_Direction member */ SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; /* initialize the SPI_Mode member */ SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; /* initialize the SPI_DataSize member */ SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; /* Initialize the SPI_CPOL member */ SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; /* Initialize the SPI_CPHA member */ SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; /* Initialize the SPI_NSS member */ SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; /* Initialize the SPI_BaudRatePrescaler member */ SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; /* Initialize the SPI_FirstBit member */ SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; /* Initialize the SPI_CRCPolynomial member */ SPI_InitStruct->SPI_CRCPolynomial = 7; } /** * @brief Fills each I2S_InitStruct member with its default value. * @param I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized. * @retval None */ void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) { /*--------------- Reset I2S init structure parameters values -----------------*/ /* Initialize the I2S_Mode member */ I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; /* Initialize the I2S_Standard member */ I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; /* Initialize the I2S_DataFormat member */ I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; /* Initialize the I2S_MCLKOutput member */ I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; /* Initialize the I2S_AudioFreq member */ I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; /* Initialize the I2S_CPOL member */ I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; } /** * @brief Enables or disables the specified SPI peripheral. * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. * @param NewState: new state of the SPIx peripheral. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH(SPIx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected SPI peripheral */ SPIx->CR1 |= SPI_CR1_SPE; } else { /* Disable the selected SPI peripheral */ SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE); } } /** * @brief Enables or disables the specified SPI peripheral (in I2S mode). * @param SPIx: where x can be 2 or 3 to select the SPI peripheral (or I2Sxext * for full duplex mode). * @param NewState: new state of the SPIx peripheral. * This parameter can be: ENABLE or DISABLE. * @retval None */ void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_SPI_23_PERIPH_EXT(SPIx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected SPI peripheral (in I2S mode) */ SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE; } else { /* Disable the selected SPI peripheral in I2S mode */ SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE); } } /** * @brief Configures the data size for the selected SPI. * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. * @param SPI_DataSize: specifies the SPI data size. * This parameter can be one of the following values: * @arg SPI_DataSize_16b: Set data frame format to 16bit * @arg SPI_DataSize_8b: Set data frame format to 8bit * @retval None */ void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) { /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH(SPIx)); assert_param(IS_SPI_DATASIZE(SPI_DataSize)); /* Clear DFF bit */ SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b; /* Set new DFF bit value */ SPIx->CR1 |= SPI_DataSize; } /** * @brief Selects the data transfer direction in bidirectional mode for the specified SPI. * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. * @param SPI_Direction: specifies the data transfer direction in bidirectional mode. * This parameter can be one of the following values: * @arg SPI_Direction_Tx: Selects Tx transmission direction * @arg SPI_Direction_Rx: Selects Rx receive direction * @retval None */ void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) { /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH(SPIx)); assert_param(IS_SPI_DIRECTION(SPI_Direction)); if (SPI_Direction == SPI_Direction_Tx) { /* Set the Tx only mode */ SPIx->CR1 |= SPI_Direction_Tx; } else { /* Set the Rx only mode */ SPIx->CR1 &= SPI_Direction_Rx; } } /** * @brief Configures internally by software the NSS pin for the selected SPI. * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. * This parameter can be one of the following values: * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally * @retval None */ void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) { /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH(SPIx)); assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) { /* Set NSS pin internally by software */ SPIx->CR1 |= SPI_NSSInternalSoft_Set; } else { /* Reset NSS pin internally by software */ SPIx->CR1 &= SPI_NSSInternalSoft_Reset; } } /** * @brief Enables or disables the SS output for the selected SPI. * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. * @param NewState: new state of the SPIx SS output. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH(SPIx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected SPI SS output */ SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE; } else { /* Disable the selected SPI SS output */ SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE); } } /** * @brief Enables or disables the SPIx/I2Sx DMA interface. * * @note This function can be called only after the SPI_Init() function has * been called. * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA * are not taken into consideration and are configured by hardware * respectively to the TI mode requirements. * * @param SPIx: where x can be 1, 2 or 3 * @param NewState: new state of the selected SPI TI communication mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH(SPIx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the TI mode for the selected SPI peripheral */ SPIx->CR2 |= SPI_CR2_FRF; } else { /* Disable the TI mode for the selected SPI peripheral */ SPIx->CR2 &= (uint16_t)~SPI_CR2_FRF; } } /** * @brief Configures the full duplex mode for the I2Sx peripheral using its * extension I2Sxext according to the specified parameters in the * I2S_InitStruct. * @param I2Sxext: where x can be 2 or 3 to select the I2S peripheral extension block. * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that * contains the configuration information for the specified I2S peripheral * extension. * * @note The structure pointed by I2S_InitStruct parameter should be the same * used for the master I2S peripheral. In this case, if the master is * configured as transmitter, the slave will be receiver and vice versa. * Or you can force a different mode by modifying the field I2S_Mode to the * value I2S_SlaveRx or I2S_SlaveTx indepedently of the master configuration. * * @note The I2S full duplex extension can be configured in slave mode only. * * @retval None */ void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct) { uint16_t tmpreg = 0, tmp = 0; /* Check the I2S parameters */ assert_param(IS_I2S_EXT_PERIPH(I2Sxext)); assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ I2Sxext->I2SCFGR &= I2SCFGR_CLEAR_MASK; I2Sxext->I2SPR = 0x0002; /* Get the I2SCFGR register value */ tmpreg = I2Sxext->I2SCFGR; /* Get the mode to be configured for the extended I2S */ if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveTx)) { tmp = I2S_Mode_SlaveRx; } else { if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterRx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveRx)) { tmp = I2S_Mode_SlaveTx; } } /* Configure the I2S with the SPI_InitStruct values */ tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \ (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ (uint16_t)I2S_InitStruct->I2S_CPOL)))); /* Write to SPIx I2SCFGR */ I2Sxext->I2SCFGR = tmpreg; } /** * @} */ /** @defgroup SPI_Group2 Data transfers functions * @brief Data transfers functions * @verbatim =============================================================================== Data transfers functions =============================================================================== This section provides a set of functions allowing to manage the SPI data transfers In reception, data are received and then stored into an internal Rx buffer while In transmission, data are first stored into an internal Tx buffer before being transmitted. The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData() function and returns the Rx buffered value. Whereas a write access to the SPI_DR can be done using SPI_I2S_SendData() function and stores the written data into Tx buffer. @endverbatim * @{ */ /** * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. * @retval The value of the received data. */ uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) { /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); /* Return the data in the DR register */ return SPIx->DR; } /** * @brief Transmits a Data through the SPIx/I2Sx peripheral. * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. * @param Data: Data to be transmitted. * @retval None */ void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data) { /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); /* Write in the DR register the data to be sent */ SPIx->DR = Data; } /** * @} */ /** @defgroup SPI_Group3 Hardware CRC Calculation functions * @brief Hardware CRC Calculation functions * @verbatim =============================================================================== Hardware CRC Calculation functions =============================================================================== This section provides a set of functions allowing to manage the SPI CRC hardware calculation SPI communication using CRC is possible through the following procedure: 1. Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() function. 2. Enable the CRC calculation using the SPI_CalculateCRC() function. 3. Enable the SPI using the SPI_Cmd() function 4. Before writing the last data to the TX buffer, set the CRCNext bit using the SPI_TransmitCRC() function to indicate that after transmission of the last data, the CRC should be transmitted. 5. After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT bit is reset. The CRC is also received and compared against the SPI_RXCRCR value. If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt can be generated when the SPI_I2S_IT_ERR interrupt is enabled. @note It is advised not to read the calculated CRC values during the communication. @note When the SPI is in slave mode, be careful to enable CRC calculation only when the clock is stable, that is, when the clock is in the steady state. If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive to the SCK slave input clock as soon as CRCEN is set, and this, whatever the value of the SPE bit. @note With high bitrate frequencies, be careful when transmitting the CRC. As the number of used CPU cycles has to be as low as possible in the CRC transfer phase, it is forbidden to call software functions in the CRC transmission sequence to avoid errors in the last data and CRC reception. In fact, CRCNEXT bit has to be written before the end of the transmission/reception of the last data. @note For high bit rate frequencies, it is advised to use the DMA mode to avoid the degradation of the SPI speed performance due to CPU accesses impacting the SPI bandwidth. @note When the STM32F4xx is configured as slave and the NSS hardware mode is used, the NSS pin needs to be kept low between the data phase and the CRC phase. @note When the SPI is configured in slave mode with the CRC feature enabled, CRC calculation takes place even if a high level is applied on the NSS pin. This may happen for example in case of a multi-slave environment where the communication master addresses slaves alternately. @note Between a slave de-selection (high level on NSS) and a new slave selection (low level on NSS), the CRC value should be cleared on both master and slave sides in order to resynchronize the master and slave for their respective CRC calculation. @note To clear the CRC, follow the procedure below: 1. Disable SPI using the SPI_Cmd() function 2. Disable the CRC calculation using the SPI_CalculateCRC() function. 3. Enable the CRC calculation using the SPI_CalculateCRC() function. 4. Enable SPI using the SPI_Cmd() function. @endverbatim * @{ */ /** * @brief Enables or disables the CRC value calculation of the transferred bytes. * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. * @param NewState: new state of the SPIx CRC value calculation. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH(SPIx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected SPI CRC calculation */ SPIx->CR1 |= SPI_CR1_CRCEN; } else { /* Disable the selected SPI CRC calculation */ SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN); } } /** * @brief Transmit the SPIx CRC value. * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. * @retval None */ void SPI_TransmitCRC(SPI_TypeDef* SPIx) { /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH(SPIx)); /* Enable the selected SPI CRC transmission */ SPIx->CR1 |= SPI_CR1_CRCNEXT; } /** * @brief Returns the transmit or the receive CRC register value for the specified SPI. * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. * @param SPI_CRC: specifies the CRC register to be read. * This parameter can be one of the following values: * @arg SPI_CRC_Tx: Selects Tx CRC register * @arg SPI_CRC_Rx: Selects Rx CRC register * @retval The selected CRC register value.. */ uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) { uint16_t crcreg = 0; /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH(SPIx)); assert_param(IS_SPI_CRC(SPI_CRC)); if (SPI_CRC != SPI_CRC_Rx) { /* Get the Tx CRC register */ crcreg = SPIx->TXCRCR; } else { /* Get the Rx CRC register */ crcreg = SPIx->RXCRCR; } /* Return the selected CRC register */ return crcreg; } /** * @brief Returns the CRC Polynomial register value for the specified SPI. * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. * @retval The CRC Polynomial register value. */ uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) { /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH(SPIx)); /* Return the CRC polynomial register */ return SPIx->CRCPR; } /** * @} */ /** @defgroup SPI_Group4 DMA transfers management functions * @brief DMA transfers management functions * @verbatim =============================================================================== DMA transfers management functions =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables the SPIx/I2Sx DMA interface. * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. * This parameter can be any combination of the following values: * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request * @param NewState: new state of the selected SPI DMA transfer request. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq)); if (NewState != DISABLE) { /* Enable the selected SPI DMA requests */ SPIx->CR2 |= SPI_I2S_DMAReq; } else { /* Disable the selected SPI DMA requests */ SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; } } /** * @} */ /** @defgroup SPI_Group5 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== Interrupts and flags management functions =============================================================================== This section provides a set of functions allowing to configure the SPI Interrupts sources and check or clear the flags or pending bits status. The user should identify which mode will be used in his application to manage the communication: Polling mode, Interrupt mode or DMA mode. Polling Mode ============= In Polling Mode, the SPI/I2S communication can be managed by 9 flags: 1. SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register 2. SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register 3. SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI. 4. SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur 5. SPI_FLAG_MODF : to indicate if a Mode Fault error occur 6. SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur 7. I2S_FLAG_TIFRFE: to indicate a Frame Format error occurs. 8. I2S_FLAG_UDR: to indicate an Underrun error occurs. 9. I2S_FLAG_CHSIDE: to indicate Channel Side. @note Do not use the BSY flag to handle each data transmission or reception. It is better to use the TXE and RXNE flags instead. In this Mode it is advised to use the following functions: - FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); - void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); Interrupt Mode =============== In Interrupt Mode, the SPI communication can be managed by 3 interrupt sources and 7 pending bits: Pending Bits: ------------- 1. SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register 2. SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register 3. SPI_IT_CRCERR : to indicate if a CRC Calculation error occur (available in SPI mode only) 4. SPI_IT_MODF : to indicate if a Mode Fault error occur (available in SPI mode only) 5. SPI_I2S_IT_OVR : to indicate if an Overrun error occur 6. I2S_IT_UDR : to indicate an Underrun Error occurs (available in I2S mode only). 7. I2S_FLAG_TIFRFE : to indicate a Frame Format error occurs (available in TI mode only). Interrupt Source: ----------------- 1. SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty interrupt. 2. SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not empty interrupt. 3. SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt. In this Mode it is advised to use the following functions: - void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); - ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); DMA Mode ======== In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests: 1. SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request 2. SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request In this Mode it is advised to use the following function: - void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); @endverbatim * @{ */ /** * @brief Enables or disables the specified SPI/I2S interrupts. * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. * This parameter can be one of the following values: * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask * @arg SPI_I2S_IT_ERR: Error interrupt mask * @param NewState: new state of the specified SPI interrupt. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) { uint16_t itpos = 0, itmask = 0 ; /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); /* Get the SPI IT index */ itpos = SPI_I2S_IT >> 4; /* Set the IT mask */ itmask = (uint16_t)1 << (uint16_t)itpos; if (NewState != DISABLE) { /* Enable the selected SPI interrupt */ SPIx->CR2 |= itmask; } else { /* Disable the selected SPI interrupt */ SPIx->CR2 &= (uint16_t)~itmask; } } /** * @brief Checks whether the specified SPIx/I2Sx flag is set or not. * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. * @param SPI_I2S_FLAG: specifies the SPI flag to check. * This parameter can be one of the following values: * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. * @arg SPI_I2S_FLAG_BSY: Busy flag. * @arg SPI_I2S_FLAG_OVR: Overrun flag. * @arg SPI_FLAG_MODF: Mode Fault flag. * @arg SPI_FLAG_CRCERR: CRC Error flag. * @arg SPI_I2S_FLAG_TIFRFE: Format Error. * @arg I2S_FLAG_UDR: Underrun Error flag. * @arg I2S_FLAG_CHSIDE: Channel Side flag. * @retval The new state of SPI_I2S_FLAG (SET or RESET). */ FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); /* Check the status of the specified SPI flag */ if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) { /* SPI_I2S_FLAG is set */ bitstatus = SET; } else { /* SPI_I2S_FLAG is reset */ bitstatus = RESET; } /* Return the SPI_I2S_FLAG status */ return bitstatus; } /** * @brief Clears the SPIx CRC Error (CRCERR) flag. * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. * @param SPI_I2S_FLAG: specifies the SPI flag to clear. * This function clears only CRCERR flag. * @arg SPI_FLAG_CRCERR: CRC Error flag. * * @note OVR (OverRun error) flag is cleared by software sequence: a read * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read * operation to SPI_SR register (SPI_I2S_GetFlagStatus()). * @note UDR (UnderRun error) flag is cleared by a read operation to * SPI_SR register (SPI_I2S_GetFlagStatus()). * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). * * @retval None */ void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) { /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG)); /* Clear the selected SPI CRC Error (CRCERR) flag */ SPIx->SR = (uint16_t)~SPI_I2S_FLAG; } /** * @brief Checks whether the specified SPIx/I2Sx interrupt has occurred or not. * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. * @param SPI_I2S_IT: specifies the SPI interrupt source to check. * This parameter can be one of the following values: * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. * @arg SPI_I2S_IT_OVR: Overrun interrupt. * @arg SPI_IT_MODF: Mode Fault interrupt. * @arg SPI_IT_CRCERR: CRC Error interrupt. * @arg I2S_IT_UDR: Underrun interrupt. * @arg SPI_I2S_IT_TIFRFE: Format Error interrupt. * @retval The new state of SPI_I2S_IT (SET or RESET). */ ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) { ITStatus bitstatus = RESET; uint16_t itpos = 0, itmask = 0, enablestatus = 0; /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); /* Get the SPI_I2S_IT index */ itpos = 0x01 << (SPI_I2S_IT & 0x0F); /* Get the SPI_I2S_IT IT mask */ itmask = SPI_I2S_IT >> 4; /* Set the IT mask */ itmask = 0x01 << itmask; /* Get the SPI_I2S_IT enable bit status */ enablestatus = (SPIx->CR2 & itmask) ; /* Check the status of the specified SPI interrupt */ if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) { /* SPI_I2S_IT is set */ bitstatus = SET; } else { /* SPI_I2S_IT is reset */ bitstatus = RESET; } /* Return the SPI_I2S_IT status */ return bitstatus; } /** * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear. * This function clears only CRCERR interrupt pending bit. * @arg SPI_IT_CRCERR: CRC Error interrupt. * * @note OVR (OverRun Error) interrupt pending bit is cleared by software * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()). * @note UDR (UnderRun Error) interrupt pending bit is cleared by a read * operation to SPI_SR register (SPI_I2S_GetITStatus()). * @note MODF (Mode Fault) interrupt pending bit is cleared by software sequence: * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable * the SPI). * @retval None */ void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) { uint16_t itpos = 0; /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT)); /* Get the SPI_I2S IT index */ itpos = 0x01 << (SPI_I2S_IT & 0x0F); /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ SPIx->SR = (uint16_t)~itpos; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c ================================================ /** ****************************************************************************** * @file stm32f4xx_syscfg.c * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file provides firmware functions to manage the SYSCFG peripheral. * * @verbatim * * =================================================================== * How to use this driver * =================================================================== * * This driver provides functions for: * * 1. Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig() * * 2. Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig() * * 3. Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig() * * @note SYSCFG APB clock must be enabled to get write access to SYSCFG registers, * using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); * * @endverbatim * ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_syscfg.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup SYSCFG * @brief SYSCFG driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* ------------ RCC registers bit address in the alias region ----------- */ #define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) /* --- PMC Register ---*/ /* Alias word address of MII_RMII_SEL bit */ #define PMC_OFFSET (SYSCFG_OFFSET + 0x04) #define MII_RMII_SEL_BitNumber ((uint8_t)0x17) #define PMC_MII_RMII_SEL_BB (PERIPH_BB_BASE + (PMC_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) /* --- CMPCR Register ---*/ /* Alias word address of CMP_PD bit */ #define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20) #define CMP_PD_BitNumber ((uint8_t)0x00) #define CMPCR_CMP_PD_BB (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4)) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup SYSCFG_Private_Functions * @{ */ /** * @brief Deinitializes the Alternate Functions (remap and EXTI configuration) * registers to their default reset values. * @param None * @retval None */ void SYSCFG_DeInit(void) { RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE); } /** * @brief Changes the mapping of the specified pin. * @param SYSCFG_Memory: selects the memory remapping. * This parameter can be one of the following values: * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000 * @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000 * @arg SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM (112kB) mapped at 0x00000000 * @retval None */ void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap) { /* Check the parameters */ assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap)); SYSCFG->MEMRMP = SYSCFG_MemoryRemap; } /** * @brief Selects the GPIO pin used as EXTI Line. * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for * EXTI lines where x can be (A..I). * @param EXTI_PinSourcex: specifies the EXTI line to be configured. * This parameter can be EXTI_PinSourcex where x can be (0..15, except * for EXTI_PortSourceGPIOI x can be (0..11). * @retval None */ void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex) { uint32_t tmp = 0x00; /* Check the parameters */ assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx)); assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex)); tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)); SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp; SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03))); } /** * @brief Selects the ETHERNET media interface * @param SYSCFG_ETH_MediaInterface: specifies the Media Interface mode. * This parameter can be one of the following values: * @arg SYSCFG_ETH_MediaInterface_MII: MII mode selected * @arg SYSCFG_ETH_MediaInterface_RMII: RMII mode selected * @retval None */ void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface) { assert_param(IS_SYSCFG_ETH_MEDIA_INTERFACE(SYSCFG_ETH_MediaInterface)); /* Configure MII_RMII selection bit */ *(__IO uint32_t *) PMC_MII_RMII_SEL_BB = SYSCFG_ETH_MediaInterface; } /** * @brief Enables or disables the I/O Compensation Cell. * @note The I/O compensation cell can be used only when the device supply * voltage ranges from 2.4 to 3.6 V. * @param NewState: new state of the I/O Compensation Cell. * This parameter can be one of the following values: * @arg ENABLE: I/O compensation cell enabled * @arg DISABLE: I/O compensation cell power-down mode * @retval None */ void SYSCFG_CompensationCellCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CMPCR_CMP_PD_BB = (uint32_t)NewState; } /** * @brief Checks whether the I/O Compensation Cell ready flag is set or not. * @param None * @retval The new state of the I/O Compensation Cell ready flag (SET or RESET) */ FlagStatus SYSCFG_GetCompensationCellStatus(void) { FlagStatus bitstatus = RESET; if ((SYSCFG->CMPCR & SYSCFG_CMPCR_READY ) != (uint32_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c ================================================ /** ****************************************************************************** * @file stm32f4xx_tim.c * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file provides firmware functions to manage the following * functionalities of the TIM peripheral: * - TimeBase management * - Output Compare management * - Input Capture management * - Advanced-control timers (TIM1 and TIM8) specific features * - Interrupts, DMA and flags management * - Clocks management * - Synchronization management * - Specific interface management * - Specific remapping management * * @verbatim * * =================================================================== * How to use this driver * =================================================================== * This driver provides functions to configure and program the TIM * of all STM32F4xx devices. * These functions are split in 9 groups: * * 1. TIM TimeBase management: this group includes all needed functions * to configure the TM Timebase unit: * - Set/Get Prescaler * - Set/Get Autoreload * - Counter modes configuration * - Set Clock division * - Select the One Pulse mode * - Update Request Configuration * - Update Disable Configuration * - Auto-Preload Configuration * - Enable/Disable the counter * * 2. TIM Output Compare management: this group includes all needed * functions to configure the Capture/Compare unit used in Output * compare mode: * - Configure each channel, independently, in Output Compare mode * - Select the output compare modes * - Select the Polarities of each channel * - Set/Get the Capture/Compare register values * - Select the Output Compare Fast mode * - Select the Output Compare Forced mode * - Output Compare-Preload Configuration * - Clear Output Compare Reference * - Select the OCREF Clear signal * - Enable/Disable the Capture/Compare Channels * * 3. TIM Input Capture management: this group includes all needed * functions to configure the Capture/Compare unit used in * Input Capture mode: * - Configure each channel in input capture mode * - Configure Channel1/2 in PWM Input mode * - Set the Input Capture Prescaler * - Get the Capture/Compare values * * 4. Advanced-control timers (TIM1 and TIM8) specific features * - Configures the Break input, dead time, Lock level, the OSSI, * the OSSR State and the AOE(automatic output enable) * - Enable/Disable the TIM peripheral Main Outputs * - Select the Commutation event * - Set/Reset the Capture Compare Preload Control bit * * 5. TIM interrupts, DMA and flags management * - Enable/Disable interrupt sources * - Get flags status * - Clear flags/ Pending bits * - Enable/Disable DMA requests * - Configure DMA burst mode * - Select CaptureCompare DMA request * * 6. TIM clocks management: this group includes all needed functions * to configure the clock controller unit: * - Select internal/External clock * - Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx * * 7. TIM synchronization management: this group includes all needed * functions to configure the Synchronization unit: * - Select Input Trigger * - Select Output Trigger * - Select Master Slave Mode * - ETR Configuration when used as external trigger * * 8. TIM specific interface management, this group includes all * needed functions to use the specific TIM interface: * - Encoder Interface Configuration * - Select Hall Sensor * * 9. TIM specific remapping management includes the Remapping * configuration of specific timers * * @endverbatim * ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_tim.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup TIM * @brief TIM driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* ---------------------- TIM registers bit mask ------------------------ */ #define SMCR_ETR_MASK ((uint16_t)0x00FF) #define CCMR_OFFSET ((uint16_t)0x0018) #define CCER_CCE_SET ((uint16_t)0x0001) #define CCER_CCNE_SET ((uint16_t)0x0004) #define CCMR_OC13M_MASK ((uint16_t)0xFF8F) #define CCMR_OC24M_MASK ((uint16_t)0x8FFF) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter); static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter); static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter); static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter); /* Private functions ---------------------------------------------------------*/ /** @defgroup TIM_Private_Functions * @{ */ /** @defgroup TIM_Group1 TimeBase management functions * @brief TimeBase management functions * @verbatim =============================================================================== TimeBase management functions =============================================================================== =================================================================== TIM Driver: how to use it in Timing(Time base) Mode =================================================================== To use the Timer in Timing(Time base) mode, the following steps are mandatory: 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function 2. Fill the TIM_TimeBaseInitStruct with the desired parameters. 3. Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit with the corresponding configuration 4. Enable the NVIC if you need to generate the update interrupt. 5. Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update) 6. Call the TIM_Cmd(ENABLE) function to enable the TIM counter. Note1: All other functions can be used separately to modify, if needed, a specific feature of the Timer. @endverbatim * @{ */ /** * @brief Deinitializes the TIMx peripheral registers to their default reset values. * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @retval None */ void TIM_DeInit(TIM_TypeDef* TIMx) { /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); if (TIMx == TIM1) { RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); } else if (TIMx == TIM2) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); } else if (TIMx == TIM3) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); } else if (TIMx == TIM4) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); } else if (TIMx == TIM5) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); } else if (TIMx == TIM6) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); } else if (TIMx == TIM7) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); } else if (TIMx == TIM8) { RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); } else if (TIMx == TIM9) { RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); } else if (TIMx == TIM10) { RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); } else if (TIMx == TIM11) { RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); } else if (TIMx == TIM12) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE); } else if (TIMx == TIM13) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE); } else { if (TIMx == TIM14) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); } } } /** * @brief Initializes the TIMx Time Base Unit peripheral according to * the specified parameters in the TIM_TimeBaseInitStruct. * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure * that contains the configuration information for the specified TIM peripheral. * @retval None */ void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) { uint16_t tmpcr1 = 0; /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); tmpcr1 = TIMx->CR1; if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)|| (TIMx == TIM4) || (TIMx == TIM5)) { /* Select the Counter Mode */ tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS)); tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; } if((TIMx != TIM6) && (TIMx != TIM7)) { /* Set the clock division */ tmpcr1 &= (uint16_t)(~TIM_CR1_CKD); tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; } TIMx->CR1 = tmpcr1; /* Set the Autoreload value */ TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; /* Set the Prescaler value */ TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; if ((TIMx == TIM1) || (TIMx == TIM8)) { /* Set the Repetition Counter value */ TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; } /* Generate an update event to reload the Prescaler and the repetition counter(only for TIM1 and TIM8) value immediatly */ TIMx->EGR = TIM_PSCReloadMode_Immediate; } /** * @brief Fills each TIM_TimeBaseInitStruct member with its default value. * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef * structure which will be initialized. * @retval None */ void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) { /* Set the default configuration */ TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF; TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; } /** * @brief Configures the TIMx Prescaler. * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @param Prescaler: specifies the Prescaler Register value * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode * This parameter can be one of the following values: * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly. * @retval None */ void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) { /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); /* Set the Prescaler value */ TIMx->PSC = Prescaler; /* Set or reset the UG Bit */ TIMx->EGR = TIM_PSCReloadMode; } /** * @brief Specifies the TIMx Counter Mode to be used. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_CounterMode: specifies the Counter Mode to be used * This parameter can be one of the following values: * @arg TIM_CounterMode_Up: TIM Up Counting Mode * @arg TIM_CounterMode_Down: TIM Down Counting Mode * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 * @retval None */ void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) { uint16_t tmpcr1 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); tmpcr1 = TIMx->CR1; /* Reset the CMS and DIR Bits */ tmpcr1 &= (uint16_t)~(TIM_CR1_DIR | TIM_CR1_CMS); /* Set the Counter Mode */ tmpcr1 |= TIM_CounterMode; /* Write to TIMx CR1 register */ TIMx->CR1 = tmpcr1; } /** * @brief Sets the TIMx Counter Register value * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @param Counter: specifies the Counter register new value. * @retval None */ void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter) { /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); /* Set the Counter Register value */ TIMx->CNT = Counter; } /** * @brief Sets the TIMx Autoreload Register value * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @param Autoreload: specifies the Autoreload register new value. * @retval None */ void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload) { /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); /* Set the Autoreload Register value */ TIMx->ARR = Autoreload; } /** * @brief Gets the TIMx Counter value. * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @retval Counter Register value */ uint32_t TIM_GetCounter(TIM_TypeDef* TIMx) { /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); /* Get the Counter Register value */ return TIMx->CNT; } /** * @brief Gets the TIMx Prescaler value. * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @retval Prescaler Register value. */ uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) { /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); /* Get the Prescaler Register value */ return TIMx->PSC; } /** * @brief Enables or Disables the TIMx Update event. * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @param NewState: new state of the TIMx UDIS bit * This parameter can be: ENABLE or DISABLE. * @retval None */ void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Set the Update Disable Bit */ TIMx->CR1 |= TIM_CR1_UDIS; } else { /* Reset the Update Disable Bit */ TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS; } } /** * @brief Configures the TIMx Update Request Interrupt source. * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @param TIM_UpdateSource: specifies the Update source. * This parameter can be one of the following values: * @arg TIM_UpdateSource_Global: Source of update is the counter * overflow/underflow or the setting of UG bit, or an update * generation through the slave mode controller. * @arg TIM_UpdateSource_Regular: Source of update is counter overflow/underflow. * @retval None */ void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) { /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); if (TIM_UpdateSource != TIM_UpdateSource_Global) { /* Set the URS Bit */ TIMx->CR1 |= TIM_CR1_URS; } else { /* Reset the URS Bit */ TIMx->CR1 &= (uint16_t)~TIM_CR1_URS; } } /** * @brief Enables or disables TIMx peripheral Preload register on ARR. * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @param NewState: new state of the TIMx peripheral Preload register * This parameter can be: ENABLE or DISABLE. * @retval None */ void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Set the ARR Preload Bit */ TIMx->CR1 |= TIM_CR1_ARPE; } else { /* Reset the ARR Preload Bit */ TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE; } } /** * @brief Selects the TIMx's One Pulse Mode. * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @param TIM_OPMode: specifies the OPM Mode to be used. * This parameter can be one of the following values: * @arg TIM_OPMode_Single * @arg TIM_OPMode_Repetitive * @retval None */ void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) { /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); /* Reset the OPM Bit */ TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM; /* Configure the OPM Mode */ TIMx->CR1 |= TIM_OPMode; } /** * @brief Sets the TIMx Clock Division value. * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. * @param TIM_CKD: specifies the clock division value. * This parameter can be one of the following value: * @arg TIM_CKD_DIV1: TDTS = Tck_tim * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim * @retval None */ void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) { /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); assert_param(IS_TIM_CKD_DIV(TIM_CKD)); /* Reset the CKD Bits */ TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD); /* Set the CKD value */ TIMx->CR1 |= TIM_CKD; } /** * @brief Enables or disables the specified TIM peripheral. * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral. * @param NewState: new state of the TIMx peripheral. * This parameter can be: ENABLE or DISABLE. * @retval None */ void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the TIM Counter */ TIMx->CR1 |= TIM_CR1_CEN; } else { /* Disable the TIM Counter */ TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN; } } /** * @} */ /** @defgroup TIM_Group2 Output Compare management functions * @brief Output Compare management functions * @verbatim =============================================================================== Output Compare management functions =============================================================================== =================================================================== TIM Driver: how to use it in Output Compare Mode =================================================================== To use the Timer in Output Compare mode, the following steps are mandatory: 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function 2. Configure the TIM pins by configuring the corresponding GPIO pins 2. Configure the Time base unit as described in the first part of this driver, if needed, else the Timer will run with the default configuration: - Autoreload value = 0xFFFF - Prescaler value = 0x0000 - Counter mode = Up counting - Clock Division = TIM_CKD_DIV1 3. Fill the TIM_OCInitStruct with the desired parameters including: - The TIM Output Compare mode: TIM_OCMode - TIM Output State: TIM_OutputState - TIM Pulse value: TIM_Pulse - TIM Output Compare Polarity : TIM_OCPolarity 4. Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired channel with the corresponding configuration 5. Call the TIM_Cmd(ENABLE) function to enable the TIM counter. Note1: All other functions can be used separately to modify, if needed, a specific feature of the Timer. Note2: In case of PWM mode, this function is mandatory: TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE); Note3: If the corresponding interrupt or DMA request are needed, the user should: 1. Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). 2. Enable the corresponding interrupt (or DMA request) using the function TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) @endverbatim * @{ */ /** * @brief Initializes the TIMx Channel1 according to the specified parameters in * the TIM_OCInitStruct. * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains * the configuration information for the specified TIM peripheral. * @retval None */ void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) { uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; /* Reset the Output Compare Mode Bits */ tmpccmrx &= (uint16_t)~TIM_CCMR1_OC1M; tmpccmrx &= (uint16_t)~TIM_CCMR1_CC1S; /* Select the Output Compare Mode */ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; /* Reset the Output Polarity level */ tmpccer &= (uint16_t)~TIM_CCER_CC1P; /* Set the Output Compare Polarity */ tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; /* Set the Output State */ tmpccer |= TIM_OCInitStruct->TIM_OutputState; if((TIMx == TIM1) || (TIMx == TIM8)) { assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); /* Reset the Output N Polarity level */ tmpccer &= (uint16_t)~TIM_CCER_CC1NP; /* Set the Output N Polarity */ tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; /* Reset the Output N State */ tmpccer &= (uint16_t)~TIM_CCER_CC1NE; /* Set the Output N State */ tmpccer |= TIM_OCInitStruct->TIM_OutputNState; /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= (uint16_t)~TIM_CR2_OIS1; tmpcr2 &= (uint16_t)~TIM_CR2_OIS1N; /* Set the Output Idle state */ tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; /* Set the Output N Idle state */ tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Initializes the TIMx Channel2 according to the specified parameters * in the TIM_OCInitStruct. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM * peripheral. * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains * the configuration information for the specified TIM peripheral. * @retval None */ void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) { uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= (uint16_t)~TIM_CCMR1_OC2M; tmpccmrx &= (uint16_t)~TIM_CCMR1_CC2S; /* Select the Output Compare Mode */ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); /* Reset the Output Polarity level */ tmpccer &= (uint16_t)~TIM_CCER_CC2P; /* Set the Output Compare Polarity */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); /* Set the Output State */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); if((TIMx == TIM1) || (TIMx == TIM8)) { assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); /* Reset the Output N Polarity level */ tmpccer &= (uint16_t)~TIM_CCER_CC2NP; /* Set the Output N Polarity */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); /* Reset the Output N State */ tmpccer &= (uint16_t)~TIM_CCER_CC2NE; /* Set the Output N State */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= (uint16_t)~TIM_CR2_OIS2; tmpcr2 &= (uint16_t)~TIM_CR2_OIS2N; /* Set the Output Idle state */ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); /* Set the Output N Idle state */ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Initializes the TIMx Channel3 according to the specified parameters * in the TIM_OCInitStruct. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains * the configuration information for the specified TIM peripheral. * @retval None */ void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) { uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= (uint16_t)~TIM_CCMR2_OC3M; tmpccmrx &= (uint16_t)~TIM_CCMR2_CC3S; /* Select the Output Compare Mode */ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; /* Reset the Output Polarity level */ tmpccer &= (uint16_t)~TIM_CCER_CC3P; /* Set the Output Compare Polarity */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); /* Set the Output State */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); if((TIMx == TIM1) || (TIMx == TIM8)) { assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); /* Reset the Output N Polarity level */ tmpccer &= (uint16_t)~TIM_CCER_CC3NP; /* Set the Output N Polarity */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); /* Reset the Output N State */ tmpccer &= (uint16_t)~TIM_CCER_CC3NE; /* Set the Output N State */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= (uint16_t)~TIM_CR2_OIS3; tmpcr2 &= (uint16_t)~TIM_CR2_OIS3N; /* Set the Output Idle state */ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); /* Set the Output N Idle state */ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Initializes the TIMx Channel4 according to the specified parameters * in the TIM_OCInitStruct. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains * the configuration information for the specified TIM peripheral. * @retval None */ void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) { uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= (uint16_t)~TIM_CCMR2_OC4M; tmpccmrx &= (uint16_t)~TIM_CCMR2_CC4S; /* Select the Output Compare Mode */ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); /* Reset the Output Polarity level */ tmpccer &= (uint16_t)~TIM_CCER_CC4P; /* Set the Output Compare Polarity */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); /* Set the Output State */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); if((TIMx == TIM1) || (TIMx == TIM8)) { assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &=(uint16_t) ~TIM_CR2_OIS4; /* Set the Output Idle state */ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Fills each TIM_OCInitStruct member with its default value. * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will * be initialized. * @retval None */ void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) { /* Set the default configuration */ TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; TIM_OCInitStruct->TIM_Pulse = 0x00000000; TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; } /** * @brief Selects the TIM Output Compare Mode. * @note This function disables the selected channel before changing the Output * Compare Mode. If needed, user has to enable this channel using * TIM_CCxCmd() and TIM_CCxNCmd() functions. * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. * @param TIM_Channel: specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_Channel_1: TIM Channel 1 * @arg TIM_Channel_2: TIM Channel 2 * @arg TIM_Channel_3: TIM Channel 3 * @arg TIM_Channel_4: TIM Channel 4 * @param TIM_OCMode: specifies the TIM Output Compare Mode. * This parameter can be one of the following values: * @arg TIM_OCMode_Timing * @arg TIM_OCMode_Active * @arg TIM_OCMode_Toggle * @arg TIM_OCMode_PWM1 * @arg TIM_OCMode_PWM2 * @arg TIM_ForcedAction_Active * @arg TIM_ForcedAction_InActive * @retval None */ void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) { uint32_t tmp = 0; uint16_t tmp1 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); assert_param(IS_TIM_CHANNEL(TIM_Channel)); assert_param(IS_TIM_OCM(TIM_OCMode)); tmp = (uint32_t) TIMx; tmp += CCMR_OFFSET; tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel; /* Disable the Channel: Reset the CCxE Bit */ TIMx->CCER &= (uint16_t) ~tmp1; if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) { tmp += (TIM_Channel>>1); /* Reset the OCxM bits in the CCMRx register */ *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK; /* Configure the OCxM bits in the CCMRx register */ *(__IO uint32_t *) tmp |= TIM_OCMode; } else { tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; /* Reset the OCxM bits in the CCMRx register */ *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK; /* Configure the OCxM bits in the CCMRx register */ *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); } } /** * @brief Sets the TIMx Capture Compare1 Register value * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. * @param Compare1: specifies the Capture Compare1 register new value. * @retval None */ void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1) { /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); /* Set the Capture Compare1 Register value */ TIMx->CCR1 = Compare1; } /** * @brief Sets the TIMx Capture Compare2 Register value * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM * peripheral. * @param Compare2: specifies the Capture Compare2 register new value. * @retval None */ void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2) { /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); /* Set the Capture Compare2 Register value */ TIMx->CCR2 = Compare2; } /** * @brief Sets the TIMx Capture Compare3 Register value * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param Compare3: specifies the Capture Compare3 register new value. * @retval None */ void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3) { /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); /* Set the Capture Compare3 Register value */ TIMx->CCR3 = Compare3; } /** * @brief Sets the TIMx Capture Compare4 Register value * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param Compare4: specifies the Capture Compare4 register new value. * @retval None */ void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4) { /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); /* Set the Capture Compare4 Register value */ TIMx->CCR4 = Compare4; } /** * @brief Forces the TIMx output 1 waveform to active or inactive level. * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. * This parameter can be one of the following values: * @arg TIM_ForcedAction_Active: Force active level on OC1REF * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. * @retval None */ void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) { uint16_t tmpccmr1 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); tmpccmr1 = TIMx->CCMR1; /* Reset the OC1M Bits */ tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1M; /* Configure The Forced output Mode */ tmpccmr1 |= TIM_ForcedAction; /* Write to TIMx CCMR1 register */ TIMx->CCMR1 = tmpccmr1; } /** * @brief Forces the TIMx output 2 waveform to active or inactive level. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM * peripheral. * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. * This parameter can be one of the following values: * @arg TIM_ForcedAction_Active: Force active level on OC2REF * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. * @retval None */ void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) { uint16_t tmpccmr1 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); tmpccmr1 = TIMx->CCMR1; /* Reset the OC2M Bits */ tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2M; /* Configure The Forced output Mode */ tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); /* Write to TIMx CCMR1 register */ TIMx->CCMR1 = tmpccmr1; } /** * @brief Forces the TIMx output 3 waveform to active or inactive level. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. * This parameter can be one of the following values: * @arg TIM_ForcedAction_Active: Force active level on OC3REF * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. * @retval None */ void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) { uint16_t tmpccmr2 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); tmpccmr2 = TIMx->CCMR2; /* Reset the OC1M Bits */ tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3M; /* Configure The Forced output Mode */ tmpccmr2 |= TIM_ForcedAction; /* Write to TIMx CCMR2 register */ TIMx->CCMR2 = tmpccmr2; } /** * @brief Forces the TIMx output 4 waveform to active or inactive level. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. * This parameter can be one of the following values: * @arg TIM_ForcedAction_Active: Force active level on OC4REF * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. * @retval None */ void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) { uint16_t tmpccmr2 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); tmpccmr2 = TIMx->CCMR2; /* Reset the OC2M Bits */ tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4M; /* Configure The Forced output Mode */ tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); /* Write to TIMx CCMR2 register */ TIMx->CCMR2 = tmpccmr2; } /** * @brief Enables or disables the TIMx peripheral Preload register on CCR1. * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. * @param TIM_OCPreload: new state of the TIMx peripheral Preload register * This parameter can be one of the following values: * @arg TIM_OCPreload_Enable * @arg TIM_OCPreload_Disable * @retval None */ void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) { uint16_t tmpccmr1 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); tmpccmr1 = TIMx->CCMR1; /* Reset the OC1PE Bit */ tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC1PE); /* Enable or Disable the Output Compare Preload feature */ tmpccmr1 |= TIM_OCPreload; /* Write to TIMx CCMR1 register */ TIMx->CCMR1 = tmpccmr1; } /** * @brief Enables or disables the TIMx peripheral Preload register on CCR2. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM * peripheral. * @param TIM_OCPreload: new state of the TIMx peripheral Preload register * This parameter can be one of the following values: * @arg TIM_OCPreload_Enable * @arg TIM_OCPreload_Disable * @retval None */ void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) { uint16_t tmpccmr1 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); tmpccmr1 = TIMx->CCMR1; /* Reset the OC2PE Bit */ tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2PE); /* Enable or Disable the Output Compare Preload feature */ tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); /* Write to TIMx CCMR1 register */ TIMx->CCMR1 = tmpccmr1; } /** * @brief Enables or disables the TIMx peripheral Preload register on CCR3. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_OCPreload: new state of the TIMx peripheral Preload register * This parameter can be one of the following values: * @arg TIM_OCPreload_Enable * @arg TIM_OCPreload_Disable * @retval None */ void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) { uint16_t tmpccmr2 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); tmpccmr2 = TIMx->CCMR2; /* Reset the OC3PE Bit */ tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC3PE); /* Enable or Disable the Output Compare Preload feature */ tmpccmr2 |= TIM_OCPreload; /* Write to TIMx CCMR2 register */ TIMx->CCMR2 = tmpccmr2; } /** * @brief Enables or disables the TIMx peripheral Preload register on CCR4. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_OCPreload: new state of the TIMx peripheral Preload register * This parameter can be one of the following values: * @arg TIM_OCPreload_Enable * @arg TIM_OCPreload_Disable * @retval None */ void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) { uint16_t tmpccmr2 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); tmpccmr2 = TIMx->CCMR2; /* Reset the OC4PE Bit */ tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4PE); /* Enable or Disable the Output Compare Preload feature */ tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); /* Write to TIMx CCMR2 register */ TIMx->CCMR2 = tmpccmr2; } /** * @brief Configures the TIMx Output Compare 1 Fast feature. * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. * This parameter can be one of the following values: * @arg TIM_OCFast_Enable: TIM output compare fast enable * @arg TIM_OCFast_Disable: TIM output compare fast disable * @retval None */ void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) { uint16_t tmpccmr1 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; /* Reset the OC1FE Bit */ tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1FE; /* Enable or Disable the Output Compare Fast Bit */ tmpccmr1 |= TIM_OCFast; /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmr1; } /** * @brief Configures the TIMx Output Compare 2 Fast feature. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM * peripheral. * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. * This parameter can be one of the following values: * @arg TIM_OCFast_Enable: TIM output compare fast enable * @arg TIM_OCFast_Disable: TIM output compare fast disable * @retval None */ void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) { uint16_t tmpccmr1 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; /* Reset the OC2FE Bit */ tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2FE); /* Enable or Disable the Output Compare Fast Bit */ tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmr1; } /** * @brief Configures the TIMx Output Compare 3 Fast feature. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. * This parameter can be one of the following values: * @arg TIM_OCFast_Enable: TIM output compare fast enable * @arg TIM_OCFast_Disable: TIM output compare fast disable * @retval None */ void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) { uint16_t tmpccmr2 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); /* Get the TIMx CCMR2 register value */ tmpccmr2 = TIMx->CCMR2; /* Reset the OC3FE Bit */ tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3FE; /* Enable or Disable the Output Compare Fast Bit */ tmpccmr2 |= TIM_OCFast; /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmr2; } /** * @brief Configures the TIMx Output Compare 4 Fast feature. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. * This parameter can be one of the following values: * @arg TIM_OCFast_Enable: TIM output compare fast enable * @arg TIM_OCFast_Disable: TIM output compare fast disable * @retval None */ void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) { uint16_t tmpccmr2 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); /* Get the TIMx CCMR2 register value */ tmpccmr2 = TIMx->CCMR2; /* Reset the OC4FE Bit */ tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4FE); /* Enable or Disable the Output Compare Fast Bit */ tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmr2; } /** * @brief Clears or safeguards the OCREF1 signal on an external event * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. * This parameter can be one of the following values: * @arg TIM_OCClear_Enable: TIM Output clear enable * @arg TIM_OCClear_Disable: TIM Output clear disable * @retval None */ void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) { uint16_t tmpccmr1 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); tmpccmr1 = TIMx->CCMR1; /* Reset the OC1CE Bit */ tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1CE; /* Enable or Disable the Output Compare Clear Bit */ tmpccmr1 |= TIM_OCClear; /* Write to TIMx CCMR1 register */ TIMx->CCMR1 = tmpccmr1; } /** * @brief Clears or safeguards the OCREF2 signal on an external event * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM * peripheral. * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. * This parameter can be one of the following values: * @arg TIM_OCClear_Enable: TIM Output clear enable * @arg TIM_OCClear_Disable: TIM Output clear disable * @retval None */ void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) { uint16_t tmpccmr1 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); tmpccmr1 = TIMx->CCMR1; /* Reset the OC2CE Bit */ tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2CE; /* Enable or Disable the Output Compare Clear Bit */ tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); /* Write to TIMx CCMR1 register */ TIMx->CCMR1 = tmpccmr1; } /** * @brief Clears or safeguards the OCREF3 signal on an external event * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. * This parameter can be one of the following values: * @arg TIM_OCClear_Enable: TIM Output clear enable * @arg TIM_OCClear_Disable: TIM Output clear disable * @retval None */ void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) { uint16_t tmpccmr2 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); tmpccmr2 = TIMx->CCMR2; /* Reset the OC3CE Bit */ tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3CE; /* Enable or Disable the Output Compare Clear Bit */ tmpccmr2 |= TIM_OCClear; /* Write to TIMx CCMR2 register */ TIMx->CCMR2 = tmpccmr2; } /** * @brief Clears or safeguards the OCREF4 signal on an external event * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. * This parameter can be one of the following values: * @arg TIM_OCClear_Enable: TIM Output clear enable * @arg TIM_OCClear_Disable: TIM Output clear disable * @retval None */ void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) { uint16_t tmpccmr2 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); tmpccmr2 = TIMx->CCMR2; /* Reset the OC4CE Bit */ tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4CE; /* Enable or Disable the Output Compare Clear Bit */ tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); /* Write to TIMx CCMR2 register */ TIMx->CCMR2 = tmpccmr2; } /** * @brief Configures the TIMx channel 1 polarity. * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. * @param TIM_OCPolarity: specifies the OC1 Polarity * This parameter can be one of the following values: * @arg TIM_OCPolarity_High: Output Compare active high * @arg TIM_OCPolarity_Low: Output Compare active low * @retval None */ void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) { uint16_t tmpccer = 0; /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); tmpccer = TIMx->CCER; /* Set or Reset the CC1P Bit */ tmpccer &= (uint16_t)(~TIM_CCER_CC1P); tmpccer |= TIM_OCPolarity; /* Write to TIMx CCER register */ TIMx->CCER = tmpccer; } /** * @brief Configures the TIMx Channel 1N polarity. * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. * @param TIM_OCNPolarity: specifies the OC1N Polarity * This parameter can be one of the following values: * @arg TIM_OCNPolarity_High: Output Compare active high * @arg TIM_OCNPolarity_Low: Output Compare active low * @retval None */ void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) { uint16_t tmpccer = 0; /* Check the parameters */ assert_param(IS_TIM_LIST4_PERIPH(TIMx)); assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); tmpccer = TIMx->CCER; /* Set or Reset the CC1NP Bit */ tmpccer &= (uint16_t)~TIM_CCER_CC1NP; tmpccer |= TIM_OCNPolarity; /* Write to TIMx CCER register */ TIMx->CCER = tmpccer; } /** * @brief Configures the TIMx channel 2 polarity. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM * peripheral. * @param TIM_OCPolarity: specifies the OC2 Polarity * This parameter can be one of the following values: * @arg TIM_OCPolarity_High: Output Compare active high * @arg TIM_OCPolarity_Low: Output Compare active low * @retval None */ void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) { uint16_t tmpccer = 0; /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); tmpccer = TIMx->CCER; /* Set or Reset the CC2P Bit */ tmpccer &= (uint16_t)(~TIM_CCER_CC2P); tmpccer |= (uint16_t)(TIM_OCPolarity << 4); /* Write to TIMx CCER register */ TIMx->CCER = tmpccer; } /** * @brief Configures the TIMx Channel 2N polarity. * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. * @param TIM_OCNPolarity: specifies the OC2N Polarity * This parameter can be one of the following values: * @arg TIM_OCNPolarity_High: Output Compare active high * @arg TIM_OCNPolarity_Low: Output Compare active low * @retval None */ void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) { uint16_t tmpccer = 0; /* Check the parameters */ assert_param(IS_TIM_LIST4_PERIPH(TIMx)); assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); tmpccer = TIMx->CCER; /* Set or Reset the CC2NP Bit */ tmpccer &= (uint16_t)~TIM_CCER_CC2NP; tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); /* Write to TIMx CCER register */ TIMx->CCER = tmpccer; } /** * @brief Configures the TIMx channel 3 polarity. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_OCPolarity: specifies the OC3 Polarity * This parameter can be one of the following values: * @arg TIM_OCPolarity_High: Output Compare active high * @arg TIM_OCPolarity_Low: Output Compare active low * @retval None */ void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) { uint16_t tmpccer = 0; /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); tmpccer = TIMx->CCER; /* Set or Reset the CC3P Bit */ tmpccer &= (uint16_t)~TIM_CCER_CC3P; tmpccer |= (uint16_t)(TIM_OCPolarity << 8); /* Write to TIMx CCER register */ TIMx->CCER = tmpccer; } /** * @brief Configures the TIMx Channel 3N polarity. * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. * @param TIM_OCNPolarity: specifies the OC3N Polarity * This parameter can be one of the following values: * @arg TIM_OCNPolarity_High: Output Compare active high * @arg TIM_OCNPolarity_Low: Output Compare active low * @retval None */ void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) { uint16_t tmpccer = 0; /* Check the parameters */ assert_param(IS_TIM_LIST4_PERIPH(TIMx)); assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); tmpccer = TIMx->CCER; /* Set or Reset the CC3NP Bit */ tmpccer &= (uint16_t)~TIM_CCER_CC3NP; tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); /* Write to TIMx CCER register */ TIMx->CCER = tmpccer; } /** * @brief Configures the TIMx channel 4 polarity. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_OCPolarity: specifies the OC4 Polarity * This parameter can be one of the following values: * @arg TIM_OCPolarity_High: Output Compare active high * @arg TIM_OCPolarity_Low: Output Compare active low * @retval None */ void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) { uint16_t tmpccer = 0; /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); tmpccer = TIMx->CCER; /* Set or Reset the CC4P Bit */ tmpccer &= (uint16_t)~TIM_CCER_CC4P; tmpccer |= (uint16_t)(TIM_OCPolarity << 12); /* Write to TIMx CCER register */ TIMx->CCER = tmpccer; } /** * @brief Enables or disables the TIM Capture Compare Channel x. * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. * @param TIM_Channel: specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_Channel_1: TIM Channel 1 * @arg TIM_Channel_2: TIM Channel 2 * @arg TIM_Channel_3: TIM Channel 3 * @arg TIM_Channel_4: TIM Channel 4 * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. * @retval None */ void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) { uint16_t tmp = 0; /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); assert_param(IS_TIM_CHANNEL(TIM_Channel)); assert_param(IS_TIM_CCX(TIM_CCx)); tmp = CCER_CCE_SET << TIM_Channel; /* Reset the CCxE Bit */ TIMx->CCER &= (uint16_t)~ tmp; /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); } /** * @brief Enables or disables the TIM Capture Compare Channel xN. * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. * @param TIM_Channel: specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_Channel_1: TIM Channel 1 * @arg TIM_Channel_2: TIM Channel 2 * @arg TIM_Channel_3: TIM Channel 3 * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. * @retval None */ void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) { uint16_t tmp = 0; /* Check the parameters */ assert_param(IS_TIM_LIST4_PERIPH(TIMx)); assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); assert_param(IS_TIM_CCXN(TIM_CCxN)); tmp = CCER_CCNE_SET << TIM_Channel; /* Reset the CCxNE Bit */ TIMx->CCER &= (uint16_t) ~tmp; /* Set or reset the CCxNE Bit */ TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); } /** * @} */ /** @defgroup TIM_Group3 Input Capture management functions * @brief Input Capture management functions * @verbatim =============================================================================== Input Capture management functions =============================================================================== =================================================================== TIM Driver: how to use it in Input Capture Mode =================================================================== To use the Timer in Input Capture mode, the following steps are mandatory: 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function 2. Configure the TIM pins by configuring the corresponding GPIO pins 2. Configure the Time base unit as described in the first part of this driver, if needed, else the Timer will run with the default configuration: - Autoreload value = 0xFFFF - Prescaler value = 0x0000 - Counter mode = Up counting - Clock Division = TIM_CKD_DIV1 3. Fill the TIM_ICInitStruct with the desired parameters including: - TIM Channel: TIM_Channel - TIM Input Capture polarity: TIM_ICPolarity - TIM Input Capture selection: TIM_ICSelection - TIM Input Capture Prescaler: TIM_ICPrescaler - TIM Input CApture filter value: TIM_ICFilter 4. Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel with the corresponding configuration and to measure only frequency or duty cycle of the input signal, or, Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired channels with the corresponding configuration and to measure the frequency and the duty cycle of the input signal 5. Enable the NVIC or the DMA to read the measured frequency. 6. Enable the corresponding interrupt (or DMA request) to read the Captured value, using the function TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) 7. Call the TIM_Cmd(ENABLE) function to enable the TIM counter. 8. Use TIM_GetCapturex(TIMx); to read the captured value. Note1: All other functions can be used separately to modify, if needed, a specific feature of the Timer. @endverbatim * @{ */ /** * @brief Initializes the TIM peripheral according to the specified parameters * in the TIM_ICInitStruct. * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains * the configuration information for the specified TIM peripheral. * @retval None */ void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) { /* TI1 Configuration */ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, TIM_ICInitStruct->TIM_ICFilter); /* Set the Input Capture Prescaler value */ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); } else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) { /* TI2 Configuration */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, TIM_ICInitStruct->TIM_ICFilter); /* Set the Input Capture Prescaler value */ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); } else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) { /* TI3 Configuration */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, TIM_ICInitStruct->TIM_ICFilter); /* Set the Input Capture Prescaler value */ TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); } else { /* TI4 Configuration */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, TIM_ICInitStruct->TIM_ICFilter); /* Set the Input Capture Prescaler value */ TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); } } /** * @brief Fills each TIM_ICInitStruct member with its default value. * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will * be initialized. * @retval None */ void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) { /* Set the default configuration */ TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; TIM_ICInitStruct->TIM_ICFilter = 0x00; } /** * @brief Configures the TIM peripheral according to the specified parameters * in the TIM_ICInitStruct to measure an external PWM signal. * @param TIMx: where x can be 1, 2, 3, 4, 5,8, 9 or 12 to select the TIM * peripheral. * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains * the configuration information for the specified TIM peripheral. * @retval None */ void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) { uint16_t icoppositepolarity = TIM_ICPolarity_Rising; uint16_t icoppositeselection = TIM_ICSelection_DirectTI; /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); /* Select the Opposite Input Polarity */ if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) { icoppositepolarity = TIM_ICPolarity_Falling; } else { icoppositepolarity = TIM_ICPolarity_Rising; } /* Select the Opposite Input */ if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) { icoppositeselection = TIM_ICSelection_IndirectTI; } else { icoppositeselection = TIM_ICSelection_DirectTI; } if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) { /* TI1 Configuration */ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, TIM_ICInitStruct->TIM_ICFilter); /* Set the Input Capture Prescaler value */ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); /* TI2 Configuration */ TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); /* Set the Input Capture Prescaler value */ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); } else { /* TI2 Configuration */ TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, TIM_ICInitStruct->TIM_ICFilter); /* Set the Input Capture Prescaler value */ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); /* TI1 Configuration */ TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); /* Set the Input Capture Prescaler value */ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); } } /** * @brief Gets the TIMx Input Capture 1 value. * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. * @retval Capture Compare 1 Register value. */ uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx) { /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); /* Get the Capture 1 Register value */ return TIMx->CCR1; } /** * @brief Gets the TIMx Input Capture 2 value. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM * peripheral. * @retval Capture Compare 2 Register value. */ uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx) { /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); /* Get the Capture 2 Register value */ return TIMx->CCR2; } /** * @brief Gets the TIMx Input Capture 3 value. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @retval Capture Compare 3 Register value. */ uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx) { /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); /* Get the Capture 3 Register value */ return TIMx->CCR3; } /** * @brief Gets the TIMx Input Capture 4 value. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @retval Capture Compare 4 Register value. */ uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx) { /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); /* Get the Capture 4 Register value */ return TIMx->CCR4; } /** * @brief Sets the TIMx Input Capture 1 prescaler. * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. * This parameter can be one of the following values: * @arg TIM_ICPSC_DIV1: no prescaler * @arg TIM_ICPSC_DIV2: capture is done once every 2 events * @arg TIM_ICPSC_DIV4: capture is done once every 4 events * @arg TIM_ICPSC_DIV8: capture is done once every 8 events * @retval None */ void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) { /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); /* Reset the IC1PSC Bits */ TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC; /* Set the IC1PSC value */ TIMx->CCMR1 |= TIM_ICPSC; } /** * @brief Sets the TIMx Input Capture 2 prescaler. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM * peripheral. * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. * This parameter can be one of the following values: * @arg TIM_ICPSC_DIV1: no prescaler * @arg TIM_ICPSC_DIV2: capture is done once every 2 events * @arg TIM_ICPSC_DIV4: capture is done once every 4 events * @arg TIM_ICPSC_DIV8: capture is done once every 8 events * @retval None */ void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) { /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); /* Reset the IC2PSC Bits */ TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC; /* Set the IC2PSC value */ TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); } /** * @brief Sets the TIMx Input Capture 3 prescaler. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. * This parameter can be one of the following values: * @arg TIM_ICPSC_DIV1: no prescaler * @arg TIM_ICPSC_DIV2: capture is done once every 2 events * @arg TIM_ICPSC_DIV4: capture is done once every 4 events * @arg TIM_ICPSC_DIV8: capture is done once every 8 events * @retval None */ void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) { /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); /* Reset the IC3PSC Bits */ TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC; /* Set the IC3PSC value */ TIMx->CCMR2 |= TIM_ICPSC; } /** * @brief Sets the TIMx Input Capture 4 prescaler. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. * This parameter can be one of the following values: * @arg TIM_ICPSC_DIV1: no prescaler * @arg TIM_ICPSC_DIV2: capture is done once every 2 events * @arg TIM_ICPSC_DIV4: capture is done once every 4 events * @arg TIM_ICPSC_DIV8: capture is done once every 8 events * @retval None */ void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) { /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); /* Reset the IC4PSC Bits */ TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC; /* Set the IC4PSC value */ TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); } /** * @} */ /** @defgroup TIM_Group4 Advanced-control timers (TIM1 and TIM8) specific features * @brief Advanced-control timers (TIM1 and TIM8) specific features * @verbatim =============================================================================== Advanced-control timers (TIM1 and TIM8) specific features =============================================================================== =================================================================== TIM Driver: how to use the Break feature =================================================================== After configuring the Timer channel(s) in the appropriate Output Compare mode: 1. Fill the TIM_BDTRInitStruct with the desired parameters for the Timer Break Polarity, dead time, Lock level, the OSSI/OSSR State and the AOE(automatic output enable). 2. Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer 3. Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE) 4. Once the break even occurs, the Timer's output signals are put in reset state or in a known state (according to the configuration made in TIM_BDTRConfig() function). @endverbatim * @{ */ /** * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State * and the AOE(automatic output enable). * @param TIMx: where x can be 1 or 8 to select the TIM * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that * contains the BDTR Register configuration information for the TIM peripheral. * @retval None */ void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) { /* Check the parameters */ assert_param(IS_TIM_LIST4_PERIPH(TIMx)); assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | TIM_BDTRInitStruct->TIM_AutomaticOutput; } /** * @brief Fills each TIM_BDTRInitStruct member with its default value. * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which * will be initialized. * @retval None */ void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) { /* Set the default configuration */ TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; TIM_BDTRInitStruct->TIM_DeadTime = 0x00; TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; } /** * @brief Enables or disables the TIM peripheral Main Outputs. * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral. * @param NewState: new state of the TIM peripheral Main Outputs. * This parameter can be: ENABLE or DISABLE. * @retval None */ void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_TIM_LIST4_PERIPH(TIMx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the TIM Main Output */ TIMx->BDTR |= TIM_BDTR_MOE; } else { /* Disable the TIM Main Output */ TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE; } } /** * @brief Selects the TIM peripheral Commutation event. * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral * @param NewState: new state of the Commutation event. * This parameter can be: ENABLE or DISABLE. * @retval None */ void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_TIM_LIST4_PERIPH(TIMx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Set the COM Bit */ TIMx->CR2 |= TIM_CR2_CCUS; } else { /* Reset the COM Bit */ TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS; } } /** * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral * @param NewState: new state of the Capture Compare Preload Control bit * This parameter can be: ENABLE or DISABLE. * @retval None */ void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_TIM_LIST4_PERIPH(TIMx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Set the CCPC Bit */ TIMx->CR2 |= TIM_CR2_CCPC; } else { /* Reset the CCPC Bit */ TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC; } } /** * @} */ /** @defgroup TIM_Group5 Interrupts DMA and flags management functions * @brief Interrupts, DMA and flags management functions * @verbatim =============================================================================== Interrupts, DMA and flags management functions =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables the specified TIM interrupts. * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral. * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg TIM_IT_Update: TIM update Interrupt source * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source * @arg TIM_IT_COM: TIM Commutation Interrupt source * @arg TIM_IT_Trigger: TIM Trigger Interrupt source * @arg TIM_IT_Break: TIM Break Interrupt source * * @note For TIM6 and TIM7 only the parameter TIM_IT_Update can be used * @note For TIM9 and TIM12 only one of the following parameters can be used: TIM_IT_Update, * TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. * @note For TIM10, TIM11, TIM13 and TIM14 only one of the following parameters can * be used: TIM_IT_Update or TIM_IT_CC1 * @note TIM_IT_COM and TIM_IT_Break can be used only with TIM1 and TIM8 * * @param NewState: new state of the TIM interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_TIM_IT(TIM_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the Interrupt sources */ TIMx->DIER |= TIM_IT; } else { /* Disable the Interrupt sources */ TIMx->DIER &= (uint16_t)~TIM_IT; } } /** * @brief Configures the TIMx event to be generate by software. * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @param TIM_EventSource: specifies the event source. * This parameter can be one or more of the following values: * @arg TIM_EventSource_Update: Timer update Event source * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source * @arg TIM_EventSource_COM: Timer COM event source * @arg TIM_EventSource_Trigger: Timer Trigger Event source * @arg TIM_EventSource_Break: Timer Break event source * * @note TIM6 and TIM7 can only generate an update event. * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. * * @retval None */ void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) { /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); /* Set the event sources */ TIMx->EGR = TIM_EventSource; } /** * @brief Checks whether the specified TIM flag is set or not. * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @param TIM_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg TIM_FLAG_Update: TIM update Flag * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag * @arg TIM_FLAG_COM: TIM Commutation Flag * @arg TIM_FLAG_Trigger: TIM Trigger Flag * @arg TIM_FLAG_Break: TIM Break Flag * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag * * @note TIM6 and TIM7 can have only one update flag. * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. * * @retval The new state of TIM_FLAG (SET or RESET). */ FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) { ITStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears the TIMx's pending flags. * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @param TIM_FLAG: specifies the flag bit to clear. * This parameter can be any combination of the following values: * @arg TIM_FLAG_Update: TIM update Flag * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag * @arg TIM_FLAG_COM: TIM Commutation Flag * @arg TIM_FLAG_Trigger: TIM Trigger Flag * @arg TIM_FLAG_Break: TIM Break Flag * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag * * @note TIM6 and TIM7 can have only one update flag. * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. * * @retval None */ void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) { /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); /* Clear the flags */ TIMx->SR = (uint16_t)~TIM_FLAG; } /** * @brief Checks whether the TIM interrupt has occurred or not. * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @param TIM_IT: specifies the TIM interrupt source to check. * This parameter can be one of the following values: * @arg TIM_IT_Update: TIM update Interrupt source * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source * @arg TIM_IT_COM: TIM Commutation Interrupt source * @arg TIM_IT_Trigger: TIM Trigger Interrupt source * @arg TIM_IT_Break: TIM Break Interrupt source * * @note TIM6 and TIM7 can generate only an update interrupt. * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. * * @retval The new state of the TIM_IT(SET or RESET). */ ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) { ITStatus bitstatus = RESET; uint16_t itstatus = 0x0, itenable = 0x0; /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_TIM_GET_IT(TIM_IT)); itstatus = TIMx->SR & TIM_IT; itenable = TIMx->DIER & TIM_IT; if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears the TIMx's interrupt pending bits. * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @param TIM_IT: specifies the pending bit to clear. * This parameter can be any combination of the following values: * @arg TIM_IT_Update: TIM1 update Interrupt source * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source * @arg TIM_IT_COM: TIM Commutation Interrupt source * @arg TIM_IT_Trigger: TIM Trigger Interrupt source * @arg TIM_IT_Break: TIM Break Interrupt source * * @note TIM6 and TIM7 can generate only an update interrupt. * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. * * @retval None */ void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) { /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); /* Clear the IT pending Bit */ TIMx->SR = (uint16_t)~TIM_IT; } /** * @brief Configures the TIMx's DMA interface. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_DMABase: DMA Base address. * This parameter can be one of the following values: * @arg TIM_DMABase_CR1 * @arg TIM_DMABase_CR2 * @arg TIM_DMABase_SMCR * @arg TIM_DMABase_DIER * @arg TIM1_DMABase_SR * @arg TIM_DMABase_EGR * @arg TIM_DMABase_CCMR1 * @arg TIM_DMABase_CCMR2 * @arg TIM_DMABase_CCER * @arg TIM_DMABase_CNT * @arg TIM_DMABase_PSC * @arg TIM_DMABase_ARR * @arg TIM_DMABase_RCR * @arg TIM_DMABase_CCR1 * @arg TIM_DMABase_CCR2 * @arg TIM_DMABase_CCR3 * @arg TIM_DMABase_CCR4 * @arg TIM_DMABase_BDTR * @arg TIM_DMABase_DCR * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. * @retval None */ void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) { /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); /* Set the DMA Base and the DMA Burst Length */ TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; } /** * @brief Enables or disables the TIMx's DMA Requests. * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral. * @param TIM_DMASource: specifies the DMA Request sources. * This parameter can be any combination of the following values: * @arg TIM_DMA_Update: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_Trigger: TIM Trigger DMA source * @param NewState: new state of the DMA Request sources. * This parameter can be: ENABLE or DISABLE. * @retval None */ void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_TIM_LIST5_PERIPH(TIMx)); assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the DMA sources */ TIMx->DIER |= TIM_DMASource; } else { /* Disable the DMA sources */ TIMx->DIER &= (uint16_t)~TIM_DMASource; } } /** * @brief Selects the TIMx peripheral Capture Compare DMA source. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param NewState: new state of the Capture Compare DMA source * This parameter can be: ENABLE or DISABLE. * @retval None */ void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Set the CCDS Bit */ TIMx->CR2 |= TIM_CR2_CCDS; } else { /* Reset the CCDS Bit */ TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS; } } /** * @} */ /** @defgroup TIM_Group6 Clocks management functions * @brief Clocks management functions * @verbatim =============================================================================== Clocks management functions =============================================================================== @endverbatim * @{ */ /** * @brief Configures the TIMx internal Clock * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM * peripheral. * @retval None */ void TIM_InternalClockConfig(TIM_TypeDef* TIMx) { /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); /* Disable slave mode to clock the prescaler directly with the internal clock */ TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS; } /** * @brief Configures the TIMx Internal Trigger as External Clock * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM * peripheral. * @param TIM_InputTriggerSource: Trigger source. * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal Trigger 0 * @arg TIM_TS_ITR1: Internal Trigger 1 * @arg TIM_TS_ITR2: Internal Trigger 2 * @arg TIM_TS_ITR3: Internal Trigger 3 * @retval None */ void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) { /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); /* Select the Internal Trigger */ TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); /* Select the External clock mode1 */ TIMx->SMCR |= TIM_SlaveMode_External1; } /** * @brief Configures the TIMx Trigger as External Clock * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 * to select the TIM peripheral. * @param TIM_TIxExternalCLKSource: Trigger source. * This parameter can be one of the following values: * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 * @param TIM_ICPolarity: specifies the TIx Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @param ICFilter: specifies the filter value. * This parameter must be a value between 0x0 and 0xF. * @retval None */ void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t TIM_ICPolarity, uint16_t ICFilter) { /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); assert_param(IS_TIM_IC_FILTER(ICFilter)); /* Configure the Timer Input Clock Source */ if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) { TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); } else { TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); } /* Select the Trigger source */ TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); /* Select the External clock mode1 */ TIMx->SMCR |= TIM_SlaveMode_External1; } /** * @brief Configures the External clock Mode1 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. * This parameter can be one of the following values: * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. * @param TIM_ExtTRGPolarity: The external Trigger Polarity. * This parameter can be one of the following values: * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. * @param ExtTRGFilter: External Trigger Filter. * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) { uint16_t tmpsmcr = 0; /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); /* Configure the ETR Clock source */ TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; /* Reset the SMS Bits */ tmpsmcr &= (uint16_t)~TIM_SMCR_SMS; /* Select the External clock mode1 */ tmpsmcr |= TIM_SlaveMode_External1; /* Select the Trigger selection : ETRF */ tmpsmcr &= (uint16_t)~TIM_SMCR_TS; tmpsmcr |= TIM_TS_ETRF; /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; } /** * @brief Configures the External clock Mode2 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. * This parameter can be one of the following values: * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. * @param TIM_ExtTRGPolarity: The external Trigger Polarity. * This parameter can be one of the following values: * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. * @param ExtTRGFilter: External Trigger Filter. * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) { /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); /* Configure the ETR Clock source */ TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); /* Enable the External clock mode2 */ TIMx->SMCR |= TIM_SMCR_ECE; } /** * @} */ /** @defgroup TIM_Group7 Synchronization management functions * @brief Synchronization management functions * @verbatim =============================================================================== Synchronization management functions =============================================================================== =================================================================== TIM Driver: how to use it in synchronization Mode =================================================================== Case of two/several Timers ************************** 1. Configure the Master Timers using the following functions: - void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); - void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); 2. Configure the Slave Timers using the following functions: - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); Case of Timers and external trigger(ETR pin) ******************************************** 1. Configure the External trigger using this function: - void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); 2. Configure the Slave Timers using the following functions: - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); @endverbatim * @{ */ /** * @brief Selects the Input Trigger source * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 * to select the TIM peripheral. * @param TIM_InputTriggerSource: The Input Trigger source. * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal Trigger 0 * @arg TIM_TS_ITR1: Internal Trigger 1 * @arg TIM_TS_ITR2: Internal Trigger 2 * @arg TIM_TS_ITR3: Internal Trigger 3 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 * @arg TIM_TS_ETRF: External Trigger input * @retval None */ void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) { uint16_t tmpsmcr = 0; /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; /* Reset the TS Bits */ tmpsmcr &= (uint16_t)~TIM_SMCR_TS; /* Set the Input Trigger source */ tmpsmcr |= TIM_InputTriggerSource; /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; } /** * @brief Selects the TIMx Trigger Output Mode. * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral. * * @param TIM_TRGOSource: specifies the Trigger Output source. * This parameter can be one of the following values: * * - For all TIMx * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO) * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO) * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO) * * - For all TIMx except TIM6 and TIM7 * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag * is to be set, as soon as a capture or compare match occurs(TRGO) * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO) * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO) * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO) * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO) * * @retval None */ void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) { /* Check the parameters */ assert_param(IS_TIM_LIST5_PERIPH(TIMx)); assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); /* Reset the MMS Bits */ TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS; /* Select the TRGO source */ TIMx->CR2 |= TIM_TRGOSource; } /** * @brief Selects the TIMx Slave Mode. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral. * @param TIM_SlaveMode: specifies the Timer Slave Mode. * This parameter can be one of the following values: * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal(TRGI) reinitialize * the counter and triggers an update of the registers * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter * @retval None */ void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) { /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); /* Reset the SMS Bits */ TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS; /* Select the Slave Mode */ TIMx->SMCR |= TIM_SlaveMode; } /** * @brief Sets or Resets the TIMx Master/Slave Mode. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral. * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. * This parameter can be one of the following values: * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer * and its slaves (through TRGO) * @arg TIM_MasterSlaveMode_Disable: No action * @retval None */ void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) { /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); /* Reset the MSM Bit */ TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM; /* Set or Reset the MSM Bit */ TIMx->SMCR |= TIM_MasterSlaveMode; } /** * @brief Configures the TIMx External Trigger (ETR). * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. * This parameter can be one of the following values: * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. * @param TIM_ExtTRGPolarity: The external Trigger Polarity. * This parameter can be one of the following values: * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. * @param ExtTRGFilter: External Trigger Filter. * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) { uint16_t tmpsmcr = 0; /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); tmpsmcr = TIMx->SMCR; /* Reset the ETR Bits */ tmpsmcr &= SMCR_ETR_MASK; /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; } /** * @} */ /** @defgroup TIM_Group8 Specific interface management functions * @brief Specific interface management functions * @verbatim =============================================================================== Specific interface management functions =============================================================================== @endverbatim * @{ */ /** * @brief Configures the TIMx Encoder Interface. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM * peripheral. * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. * This parameter can be one of the following values: * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending * on the level of the other input. * @param TIM_IC1Polarity: specifies the IC1 Polarity * This parameter can be one of the following values: * @arg TIM_ICPolarity_Falling: IC Falling edge. * @arg TIM_ICPolarity_Rising: IC Rising edge. * @param TIM_IC2Polarity: specifies the IC2 Polarity * This parameter can be one of the following values: * @arg TIM_ICPolarity_Falling: IC Falling edge. * @arg TIM_ICPolarity_Rising: IC Rising edge. * @retval None */ void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) { uint16_t tmpsmcr = 0; uint16_t tmpccmr1 = 0; uint16_t tmpccer = 0; /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Set the encoder Mode */ tmpsmcr &= (uint16_t)~TIM_SMCR_SMS; tmpsmcr |= TIM_EncoderMode; /* Select the Capture Compare 1 and the Capture Compare 2 as input */ tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S); tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; /* Set the TI1 and the TI2 Polarities */ tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P); tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmr1; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Enables or disables the TIMx's Hall sensor interface. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM * peripheral. * @param NewState: new state of the TIMx Hall sensor interface. * This parameter can be: ENABLE or DISABLE. * @retval None */ void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Set the TI1S Bit */ TIMx->CR2 |= TIM_CR2_TI1S; } else { /* Reset the TI1S Bit */ TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S; } } /** * @} */ /** @defgroup TIM_Group9 Specific remapping management function * @brief Specific remapping management function * @verbatim =============================================================================== Specific remapping management function =============================================================================== @endverbatim * @{ */ /** * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities. * @param TIMx: where x can be 2, 5 or 11 to select the TIM peripheral. * @param TIM_Remap: specifies the TIM input remapping source. * This parameter can be one of the following values: * @arg TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default) * @arg TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trogger output. * @arg TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF. * @arg TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF. * @arg TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default) * @arg TIM5_LSI: TIM5 CH4 input is connected to LSI clock. * @arg TIM5_LSE: TIM5 CH4 input is connected to LSE clock. * @arg TIM5_RTC: TIM5 CH4 input is connected to RTC Output event. * @arg TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default) * @arg TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock * (HSE divided by a programmable prescaler) * @retval None */ void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap) { /* Check the parameters */ assert_param(IS_TIM_LIST6_PERIPH(TIMx)); assert_param(IS_TIM_REMAP(TIM_Remap)); /* Set the Timer remapping configuration */ TIMx->OR = TIM_Remap; } /** * @} */ /** * @brief Configure the TI1 as Input. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 * to select the TIM peripheral. * @param TIM_ICPolarity : The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge * @param TIM_ICSelection: specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. * @param TIM_ICFilter: Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter) { uint16_t tmpccmr1 = 0, tmpccer = 0; /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E; tmpccmr1 = TIMx->CCMR1; tmpccer = TIMx->CCER; /* Select the Input and set the filter */ tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_IC1F); tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); /* Select the Polarity and set the CC1E Bit */ tmpccer &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP); tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; TIMx->CCER = tmpccer; } /** * @brief Configure the TI2 as Input. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM * peripheral. * @param TIM_ICPolarity : The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge * @param TIM_ICSelection: specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. * @param TIM_ICFilter: Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter) { uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E; tmpccmr1 = TIMx->CCMR1; tmpccer = TIMx->CCER; tmp = (uint16_t)(TIM_ICPolarity << 4); /* Select the Input and set the filter */ tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F); tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); /* Select the Polarity and set the CC2E Bit */ tmpccer &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP); tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; TIMx->CCER = tmpccer; } /** * @brief Configure the TI3 as Input. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_ICPolarity : The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge * @param TIM_ICSelection: specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. * @param TIM_ICFilter: Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter) { uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; /* Disable the Channel 3: Reset the CC3E Bit */ TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E; tmpccmr2 = TIMx->CCMR2; tmpccer = TIMx->CCER; tmp = (uint16_t)(TIM_ICPolarity << 8); /* Select the Input and set the filter */ tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F); tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); /* Select the Polarity and set the CC3E Bit */ tmpccer &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP); tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; TIMx->CCER = tmpccer; } /** * @brief Configure the TI4 as Input. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_ICPolarity : The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge * @param TIM_ICSelection: specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. * @param TIM_ICFilter: Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter) { uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E; tmpccmr2 = TIMx->CCMR2; tmpccer = TIMx->CCER; tmp = (uint16_t)(TIM_ICPolarity << 12); /* Select the Input and set the filter */ tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F); tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); /* Select the Polarity and set the CC4E Bit */ tmpccer &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP); tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; TIMx->CCER = tmpccer ; } /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c ================================================ /** ****************************************************************************** * @file stm32f4xx_usart.c * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file provides firmware functions to manage the following * functionalities of the Universal synchronous asynchronous receiver * transmitter (USART): * - Initialization and Configuration * - Data transfers * - Multi-Processor Communication * - LIN mode * - Half-duplex mode * - Smartcard mode * - IrDA mode * - DMA transfers management * - Interrupts and flags management * * @verbatim * * =================================================================== * How to use this driver * =================================================================== * 1. Enable peripheral clock using the follwoing functions * RCC_APB2PeriphClockCmd(RCC_APB2Periph_USARTx, ENABLE) for USART1 and USART6 * RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE) for USART2, USART3, UART4 or UART5. * * 2. According to the USART mode, enable the GPIO clocks using * RCC_AHB1PeriphClockCmd() function. (The I/O can be TX, RX, CTS, * or/and SCLK). * * 3. Peripheral's alternate function: * - Connect the pin to the desired peripherals' Alternate * Function (AF) using GPIO_PinAFConfig() function * - Configure the desired pin in alternate function by: * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF * - Select the type, pull-up/pull-down and output speed via * GPIO_PuPd, GPIO_OType and GPIO_Speed members * - Call GPIO_Init() function * * 4. Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware * flow control and Mode(Receiver/Transmitter) using the USART_Init() * function. * * 5. For synchronous mode, enable the clock and program the polarity, * phase and last bit using the USART_ClockInit() function. * * 5. Enable the NVIC and the corresponding interrupt using the function * USART_ITConfig() if you need to use interrupt mode. * * 6. When using the DMA mode * - Configure the DMA using DMA_Init() function * - Active the needed channel Request using USART_DMACmd() function * * 7. Enable the USART using the USART_Cmd() function. * * 8. Enable the DMA using the DMA_Cmd() function, when using DMA mode. * * Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections * for more details * * In order to reach higher communication baudrates, it is possible to * enable the oversampling by 8 mode using the function USART_OverSampling8Cmd(). * This function should be called after enabling the USART clock (RCC_APBxPeriphClockCmd()) * and before calling the function USART_Init(). * * @endverbatim * ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_usart.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup USART * @brief USART driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /*!< USART CR1 register clear Mask ((~(uint16_t)0xE9F3)) */ #define CR1_CLEAR_MASK ((uint16_t)(USART_CR1_M | USART_CR1_PCE | \ USART_CR1_PS | USART_CR1_TE | \ USART_CR1_RE)) /*!< USART CR2 register clock bits clear Mask ((~(uint16_t)0xF0FF)) */ #define CR2_CLOCK_CLEAR_MASK ((uint16_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \ USART_CR2_CPHA | USART_CR2_LBCL)) /*!< USART CR3 register clear Mask ((~(uint16_t)0xFCFF)) */ #define CR3_CLEAR_MASK ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE)) /*!< USART Interrupts mask */ #define IT_MASK ((uint16_t)0x001F) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup USART_Private_Functions * @{ */ /** @defgroup USART_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== Initialization and Configuration functions =============================================================================== This subsection provides a set of functions allowing to initialize the USART in asynchronous and in synchronous modes. - For the asynchronous mode only these parameters can be configured: - Baud Rate - Word Length - Stop Bit - Parity: If the parity is enabled, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit. Depending on the frame length defined by the M bit (8-bits or 9-bits), the possible USART frame formats are as listed in the following table: +-------------------------------------------------------------+ | M bit | PCE bit | USART frame | |---------------------|---------------------------------------| | 0 | 0 | | SB | 8 bit data | STB | | |---------|-----------|---------------------------------------| | 0 | 1 | | SB | 7 bit data | PB | STB | | |---------|-----------|---------------------------------------| | 1 | 0 | | SB | 9 bit data | STB | | |---------|-----------|---------------------------------------| | 1 | 1 | | SB | 8 bit data | PB | STB | | +-------------------------------------------------------------+ - Hardware flow control - Receiver/transmitter modes The USART_Init() function follows the USART asynchronous configuration procedure (details for the procedure are available in reference manual (RM0090)). - For the synchronous mode in addition to the asynchronous mode parameters these parameters should be also configured: - USART Clock Enabled - USART polarity - USART phase - USART LastBit These parameters can be configured using the USART_ClockInit() function. @endverbatim * @{ */ /** * @brief Deinitializes the USARTx peripheral registers to their default reset values. * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * UART peripheral. * @retval None */ void USART_DeInit(USART_TypeDef* USARTx) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); if (USARTx == USART1) { RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); } else if (USARTx == USART2) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); } else if (USARTx == USART3) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); } else if (USARTx == UART4) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); } else if (USARTx == UART5) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); } else { if (USARTx == USART6) { RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE); } } } /** * @brief Initializes the USARTx peripheral according to the specified * parameters in the USART_InitStruct . * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * UART peripheral. * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that contains * the configuration information for the specified USART peripheral. * @retval None */ void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) { uint32_t tmpreg = 0x00, apbclock = 0x00; uint32_t integerdivider = 0x00; uint32_t fractionaldivider = 0x00; RCC_ClocksTypeDef RCC_ClocksStatus; /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */ if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) { assert_param(IS_USART_1236_PERIPH(USARTx)); } /*---------------------------- USART CR2 Configuration -----------------------*/ tmpreg = USARTx->CR2; /* Clear STOP[13:12] bits */ tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP); /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit : Set STOP[13:12] bits according to USART_StopBits value */ tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; /* Write to USART CR2 */ USARTx->CR2 = (uint16_t)tmpreg; /*---------------------------- USART CR1 Configuration -----------------------*/ tmpreg = USARTx->CR1; /* Clear M, PCE, PS, TE and RE bits */ tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK); /* Configure the USART Word Length, Parity and mode: Set the M bits according to USART_WordLength value Set PCE and PS bits according to USART_Parity value Set TE and RE bits according to USART_Mode value */ tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | USART_InitStruct->USART_Mode; /* Write to USART CR1 */ USARTx->CR1 = (uint16_t)tmpreg; /*---------------------------- USART CR3 Configuration -----------------------*/ tmpreg = USARTx->CR3; /* Clear CTSE and RTSE bits */ tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK); /* Configure the USART HFC : Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ tmpreg |= USART_InitStruct->USART_HardwareFlowControl; /* Write to USART CR3 */ USARTx->CR3 = (uint16_t)tmpreg; /*---------------------------- USART BRR Configuration -----------------------*/ /* Configure the USART Baud Rate */ RCC_GetClocksFreq(&RCC_ClocksStatus); if ((USARTx == USART1) || (USARTx == USART6)) { apbclock = RCC_ClocksStatus.PCLK2_Frequency; } else { apbclock = RCC_ClocksStatus.PCLK1_Frequency; } /* Determine the integer part */ if ((USARTx->CR1 & USART_CR1_OVER8) != 0) { /* Integer part computing in case Oversampling mode is 8 Samples */ integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); } else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */ { /* Integer part computing in case Oversampling mode is 16 Samples */ integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); } tmpreg = (integerdivider / 100) << 4; /* Determine the fractional part */ fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); /* Implement the fractional part in the register */ if ((USARTx->CR1 & USART_CR1_OVER8) != 0) { tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); } else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */ { tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); } /* Write to USART BRR register */ USARTx->BRR = (uint16_t)tmpreg; } /** * @brief Fills each USART_InitStruct member with its default value. * @param USART_InitStruct: pointer to a USART_InitTypeDef structure which will * be initialized. * @retval None */ void USART_StructInit(USART_InitTypeDef* USART_InitStruct) { /* USART_InitStruct members default value */ USART_InitStruct->USART_BaudRate = 9600; USART_InitStruct->USART_WordLength = USART_WordLength_8b; USART_InitStruct->USART_StopBits = USART_StopBits_1; USART_InitStruct->USART_Parity = USART_Parity_No ; USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; } /** * @brief Initializes the USARTx peripheral Clock according to the * specified parameters in the USART_ClockInitStruct . * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART peripheral. * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure that * contains the configuration information for the specified USART peripheral. * @note The Smart Card and Synchronous modes are not available for UART4 and UART5. * @retval None */ void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) { uint32_t tmpreg = 0x00; /* Check the parameters */ assert_param(IS_USART_1236_PERIPH(USARTx)); assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); /*---------------------------- USART CR2 Configuration -----------------------*/ tmpreg = USARTx->CR2; /* Clear CLKEN, CPOL, CPHA and LBCL bits */ tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK); /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ /* Set CLKEN bit according to USART_Clock value */ /* Set CPOL bit according to USART_CPOL value */ /* Set CPHA bit according to USART_CPHA value */ /* Set LBCL bit according to USART_LastBit value */ tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; /* Write to USART CR2 */ USARTx->CR2 = (uint16_t)tmpreg; } /** * @brief Fills each USART_ClockInitStruct member with its default value. * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure * which will be initialized. * @retval None */ void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) { /* USART_ClockInitStruct members default value */ USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; } /** * @brief Enables or disables the specified USART peripheral. * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * UART peripheral. * @param NewState: new state of the USARTx peripheral. * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected USART by setting the UE bit in the CR1 register */ USARTx->CR1 |= USART_CR1_UE; } else { /* Disable the selected USART by clearing the UE bit in the CR1 register */ USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_UE); } } /** * @brief Sets the system clock prescaler. * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * UART peripheral. * @param USART_Prescaler: specifies the prescaler clock. * @note The function is used for IrDA mode with UART4 and UART5. * @retval None */ void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); /* Clear the USART prescaler */ USARTx->GTPR &= USART_GTPR_GT; /* Set the USART prescaler */ USARTx->GTPR |= USART_Prescaler; } /** * @brief Enables or disables the USART's 8x oversampling mode. * @note This function has to be called before calling USART_Init() function * in order to have correct baudrate Divider value. * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * UART peripheral. * @param NewState: new state of the USART 8x oversampling mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */ USARTx->CR1 |= USART_CR1_OVER8; } else { /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */ USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_OVER8); } } /** * @brief Enables or disables the USART's one bit sampling method. * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * UART peripheral. * @param NewState: new state of the USART one bit sampling method. * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */ USARTx->CR3 |= USART_CR3_ONEBIT; } else { /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */ USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT); } } /** * @} */ /** @defgroup USART_Group2 Data transfers functions * @brief Data transfers functions * @verbatim =============================================================================== Data transfers functions =============================================================================== This subsection provides a set of functions allowing to manage the USART data transfers. During an USART reception, data shifts in least significant bit first through the RX pin. In this mode, the USART_DR register consists of a buffer (RDR) between the internal bus and the received shift register. When a transmission is taking place, a write instruction to the USART_DR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission. The read access of the USART_DR register can be done using the USART_ReceiveData() function and returns the RDR buffered value. Whereas a write access to the USART_DR can be done using USART_SendData() function and stores the written data into TDR buffer. @endverbatim * @{ */ /** * @brief Transmits single data through the USARTx peripheral. * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * UART peripheral. * @param Data: the data to transmit. * @retval None */ void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_USART_DATA(Data)); /* Transmit Data */ USARTx->DR = (Data & (uint16_t)0x01FF); } /** * @brief Returns the most recent received data by the USARTx peripheral. * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * UART peripheral. * @retval The received data. */ uint16_t USART_ReceiveData(USART_TypeDef* USARTx) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); /* Receive Data */ return (uint16_t)(USARTx->DR & (uint16_t)0x01FF); } /** * @} */ /** @defgroup USART_Group3 MultiProcessor Communication functions * @brief Multi-Processor Communication functions * @verbatim =============================================================================== Multi-Processor Communication functions =============================================================================== This subsection provides a set of functions allowing to manage the USART multiprocessor communication. For instance one of the USARTs can be the master, its TX output is connected to the RX input of the other USART. The others are slaves, their respective TX outputs are logically ANDed together and connected to the RX input of the master. USART multiprocessor communication is possible through the following procedure: 1. Program the Baud rate, Word length = 9 bits, Stop bits, Parity, Mode transmitter or Mode receiver and hardware flow control values using the USART_Init() function. 2. Configures the USART address using the USART_SetAddress() function. 3. Configures the wake up method (USART_WakeUp_IdleLine or USART_WakeUp_AddressMark) using USART_WakeUpConfig() function only for the slaves. 4. Enable the USART using the USART_Cmd() function. 5. Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() function. The USART Slave exit from mute mode when receive the wake up condition. @endverbatim * @{ */ /** * @brief Sets the address of the USART node. * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * UART peripheral. * @param USART_Address: Indicates the address of the USART node. * @retval None */ void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_USART_ADDRESS(USART_Address)); /* Clear the USART address */ USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_ADD); /* Set the USART address node */ USARTx->CR2 |= USART_Address; } /** * @brief Determines if the USART is in mute mode or not. * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * UART peripheral. * @param NewState: new state of the USART mute mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ USARTx->CR1 |= USART_CR1_RWU; } else { /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_RWU); } } /** * @brief Selects the USART WakeUp method. * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * UART peripheral. * @param USART_WakeUp: specifies the USART wakeup method. * This parameter can be one of the following values: * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection * @arg USART_WakeUp_AddressMark: WakeUp by an address mark * @retval None */ void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_USART_WAKEUP(USART_WakeUp)); USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_WAKE); USARTx->CR1 |= USART_WakeUp; } /** * @} */ /** @defgroup USART_Group4 LIN mode functions * @brief LIN mode functions * @verbatim =============================================================================== LIN mode functions =============================================================================== This subsection provides a set of functions allowing to manage the USART LIN Mode communication. In LIN mode, 8-bit data format with 1 stop bit is required in accordance with the LIN standard. Only this LIN Feature is supported by the USART IP: - LIN Master Synchronous Break send capability and LIN slave break detection capability : 13-bit break generation and 10/11 bit break detection USART LIN Master transmitter communication is possible through the following procedure: 1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, Mode transmitter or Mode receiver and hardware flow control values using the USART_Init() function. 2. Enable the USART using the USART_Cmd() function. 3. Enable the LIN mode using the USART_LINCmd() function. 4. Send the break character using USART_SendBreak() function. USART LIN Master receiver communication is possible through the following procedure: 1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, Mode transmitter or Mode receiver and hardware flow control values using the USART_Init() function. 2. Enable the USART using the USART_Cmd() function. 3. Configures the break detection length using the USART_LINBreakDetectLengthConfig() function. 4. Enable the LIN mode using the USART_LINCmd() function. @note In LIN mode, the following bits must be kept cleared: - CLKEN in the USART_CR2 register, - STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register. @endverbatim * @{ */ /** * @brief Sets the USART LIN Break detection length. * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * UART peripheral. * @param USART_LINBreakDetectLength: specifies the LIN break detection length. * This parameter can be one of the following values: * @arg USART_LINBreakDetectLength_10b: 10-bit break detection * @arg USART_LINBreakDetectLength_11b: 11-bit break detection * @retval None */ void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LBDL); USARTx->CR2 |= USART_LINBreakDetectLength; } /** * @brief Enables or disables the USART's LIN mode. * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * UART peripheral. * @param NewState: new state of the USART LIN mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ USARTx->CR2 |= USART_CR2_LINEN; } else { /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LINEN); } } /** * @brief Transmits break characters. * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * UART peripheral. * @retval None */ void USART_SendBreak(USART_TypeDef* USARTx) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); /* Send break characters */ USARTx->CR1 |= USART_CR1_SBK; } /** * @} */ /** @defgroup USART_Group5 Halfduplex mode function * @brief Half-duplex mode function * @verbatim =============================================================================== Half-duplex mode function =============================================================================== This subsection provides a set of functions allowing to manage the USART Half-duplex communication. The USART can be configured to follow a single-wire half-duplex protocol where the TX and RX lines are internally connected. USART Half duplex communication is possible through the following procedure: 1. Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter or Mode receiver and hardware flow control values using the USART_Init() function. 2. Configures the USART address using the USART_SetAddress() function. 3. Enable the USART using the USART_Cmd() function. 4. Enable the half duplex mode using USART_HalfDuplexCmd() function. @note The RX pin is no longer used @note In Half-duplex mode the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register. - SCEN and IREN bits in the USART_CR3 register. @endverbatim * @{ */ /** * @brief Enables or disables the USART's Half Duplex communication. * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * UART peripheral. * @param NewState: new state of the USART Communication. * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ USARTx->CR3 |= USART_CR3_HDSEL; } else { /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_HDSEL); } } /** * @} */ /** @defgroup USART_Group6 Smartcard mode functions * @brief Smartcard mode functions * @verbatim =============================================================================== Smartcard mode functions =============================================================================== This subsection provides a set of functions allowing to manage the USART Smartcard communication. The Smartcard interface is designed to support asynchronous protocol Smartcards as defined in the ISO 7816-3 standard. The USART can provide a clock to the smartcard through the SCLK output. In smartcard mode, SCLK is not associated to the communication but is simply derived from the internal peripheral input clock through a 5-bit prescaler. Smartcard communication is possible through the following procedure: 1. Configures the Smartcard Prescaler using the USART_SetPrescaler() function. 2. Configures the Smartcard Guard Time using the USART_SetGuardTime() function. 3. Program the USART clock using the USART_ClockInit() function as following: - USART Clock enabled - USART CPOL Low - USART CPHA on first edge - USART Last Bit Clock Enabled 4. Program the Smartcard interface using the USART_Init() function as following: - Word Length = 9 Bits - 1.5 Stop Bit - Even parity - BaudRate = 12096 baud - Hardware flow control disabled (RTS and CTS signals) - Tx and Rx enabled 5. Optionally you can enable the parity error interrupt using the USART_ITConfig() function 6. Enable the USART using the USART_Cmd() function. 7. Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function. 8. Enable the Smartcard interface using the USART_SmartCardCmd() function. Please refer to the ISO 7816-3 specification for more details. @note It is also possible to choose 0.5 stop bit for receiving but it is recommended to use 1.5 stop bits for both transmitting and receiving to avoid switching between the two configurations. @note In smartcard mode, the following bits must be kept cleared: - LINEN bit in the USART_CR2 register. - HDSEL and IREN bits in the USART_CR3 register. @note Smartcard mode is available on USART peripherals only (not available on UART4 and UART5 peripherals). @endverbatim * @{ */ /** * @brief Sets the specified USART guard time. * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or * UART peripheral. * @param USART_GuardTime: specifies the guard time. * @retval None */ void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime) { /* Check the parameters */ assert_param(IS_USART_1236_PERIPH(USARTx)); /* Clear the USART Guard time */ USARTx->GTPR &= USART_GTPR_PSC; /* Set the USART guard time */ USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); } /** * @brief Enables or disables the USART's Smart Card mode. * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or * UART peripheral. * @param NewState: new state of the Smart Card mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_USART_1236_PERIPH(USARTx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the SC mode by setting the SCEN bit in the CR3 register */ USARTx->CR3 |= USART_CR3_SCEN; } else { /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_SCEN); } } /** * @brief Enables or disables NACK transmission. * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or * UART peripheral. * @param NewState: new state of the NACK transmission. * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_USART_1236_PERIPH(USARTx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ USARTx->CR3 |= USART_CR3_NACK; } else { /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_NACK); } } /** * @} */ /** @defgroup USART_Group7 IrDA mode functions * @brief IrDA mode functions * @verbatim =============================================================================== IrDA mode functions =============================================================================== This subsection provides a set of functions allowing to manage the USART IrDA communication. IrDA is a half duplex communication protocol. If the Transmitter is busy, any data on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver is busy, data on the TX from the USART to IrDA will not be encoded by IrDA. While receiving data, transmission should be avoided as the data to be transmitted could be corrupted. IrDA communication is possible through the following procedure: 1. Program the Baud rate, Word length = 8 bits, Stop bits, Parity, Transmitter/Receiver modes and hardware flow control values using the USART_Init() function. 2. Enable the USART using the USART_Cmd() function. 3. Configures the IrDA pulse width by configuring the prescaler using the USART_SetPrescaler() function. 4. Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal mode using the USART_IrDAConfig() function. 5. Enable the IrDA using the USART_IrDACmd() function. @note A pulse of width less than two and greater than one PSC period(s) may or may not be rejected. @note The receiver set up time should be managed by software. The IrDA physical layer specification specifies a minimum of 10 ms delay between transmission and reception (IrDA is a half duplex protocol). @note In IrDA mode, the following bits must be kept cleared: - LINEN, STOP and CLKEN bits in the USART_CR2 register. - SCEN and HDSEL bits in the USART_CR3 register. @endverbatim * @{ */ /** * @brief Configures the USART's IrDA interface. * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * UART peripheral. * @param USART_IrDAMode: specifies the IrDA mode. * This parameter can be one of the following values: * @arg USART_IrDAMode_LowPower * @arg USART_IrDAMode_Normal * @retval None */ void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IRLP); USARTx->CR3 |= USART_IrDAMode; } /** * @brief Enables or disables the USART's IrDA interface. * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * UART peripheral. * @param NewState: new state of the IrDA mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ USARTx->CR3 |= USART_CR3_IREN; } else { /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IREN); } } /** * @} */ /** @defgroup USART_Group8 DMA transfers management functions * @brief DMA transfers management functions * @verbatim =============================================================================== DMA transfers management functions =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables the USART's DMA interface. * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * UART peripheral. * @param USART_DMAReq: specifies the DMA request. * This parameter can be any combination of the following values: * @arg USART_DMAReq_Tx: USART DMA transmit request * @arg USART_DMAReq_Rx: USART DMA receive request * @param NewState: new state of the DMA Request sources. * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_USART_DMAREQ(USART_DMAReq)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the DMA transfer for selected requests by setting the DMAT and/or DMAR bits in the USART CR3 register */ USARTx->CR3 |= USART_DMAReq; } else { /* Disable the DMA transfer for selected requests by clearing the DMAT and/or DMAR bits in the USART CR3 register */ USARTx->CR3 &= (uint16_t)~USART_DMAReq; } } /** * @} */ /** @defgroup USART_Group9 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== Interrupts and flags management functions =============================================================================== This subsection provides a set of functions allowing to configure the USART Interrupts sources, DMA channels requests and check or clear the flags or pending bits status. The user should identify which mode will be used in his application to manage the communication: Polling mode, Interrupt mode or DMA mode. Polling Mode ============= In Polling Mode, the SPI communication can be managed by 10 flags: 1. USART_FLAG_TXE : to indicate the status of the transmit buffer register 2. USART_FLAG_RXNE : to indicate the status of the receive buffer register 3. USART_FLAG_TC : to indicate the status of the transmit operation 4. USART_FLAG_IDLE : to indicate the status of the Idle Line 5. USART_FLAG_CTS : to indicate the status of the nCTS input 6. USART_FLAG_LBD : to indicate the status of the LIN break detection 7. USART_FLAG_NE : to indicate if a noise error occur 8. USART_FLAG_FE : to indicate if a frame error occur 9. USART_FLAG_PE : to indicate if a parity error occur 10. USART_FLAG_ORE : to indicate if an Overrun error occur In this Mode it is advised to use the following functions: - FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); - void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); Interrupt Mode =============== In Interrupt Mode, the USART communication can be managed by 8 interrupt sources and 10 pending bits: Pending Bits: ------------- 1. USART_IT_TXE : to indicate the status of the transmit buffer register 2. USART_IT_RXNE : to indicate the status of the receive buffer register 3. USART_IT_TC : to indicate the status of the transmit operation 4. USART_IT_IDLE : to indicate the status of the Idle Line 5. USART_IT_CTS : to indicate the status of the nCTS input 6. USART_IT_LBD : to indicate the status of the LIN break detection 7. USART_IT_NE : to indicate if a noise error occur 8. USART_IT_FE : to indicate if a frame error occur 9. USART_IT_PE : to indicate if a parity error occur 10. USART_IT_ORE : to indicate if an Overrun error occur Interrupt Source: ----------------- 1. USART_IT_TXE : specifies the interrupt source for the Tx buffer empty interrupt. 2. USART_IT_RXNE : specifies the interrupt source for the Rx buffer not empty interrupt. 3. USART_IT_TC : specifies the interrupt source for the Transmit complete interrupt. 4. USART_IT_IDLE : specifies the interrupt source for the Idle Line interrupt. 5. USART_IT_CTS : specifies the interrupt source for the CTS interrupt. 6. USART_IT_LBD : specifies the interrupt source for the LIN break detection interrupt. 7. USART_IT_PE : specifies the interrupt source for the parity error interrupt. 8. USART_IT_ERR : specifies the interrupt source for the errors interrupt. @note Some parameters are coded in order to use them as interrupt source or as pending bits. In this Mode it is advised to use the following functions: - void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); - ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); - void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); DMA Mode ======== In DMA Mode, the USART communication can be managed by 2 DMA Channel requests: 1. USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request 2. USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request In this Mode it is advised to use the following function: - void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); @endverbatim * @{ */ /** * @brief Enables or disables the specified USART interrupts. * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * UART peripheral. * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. * This parameter can be one of the following values: * @arg USART_IT_CTS: CTS change interrupt * @arg USART_IT_LBD: LIN Break detection interrupt * @arg USART_IT_TXE: Transmit Data Register empty interrupt * @arg USART_IT_TC: Transmission complete interrupt * @arg USART_IT_RXNE: Receive Data register not empty interrupt * @arg USART_IT_IDLE: Idle line detection interrupt * @arg USART_IT_PE: Parity Error interrupt * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) * @param NewState: new state of the specified USARTx interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState) { uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; uint32_t usartxbase = 0x00; /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_USART_CONFIG_IT(USART_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); /* The CTS interrupt is not available for UART4 and UART5 */ if (USART_IT == USART_IT_CTS) { assert_param(IS_USART_1236_PERIPH(USARTx)); } usartxbase = (uint32_t)USARTx; /* Get the USART register index */ usartreg = (((uint8_t)USART_IT) >> 0x05); /* Get the interrupt position */ itpos = USART_IT & IT_MASK; itmask = (((uint32_t)0x01) << itpos); if (usartreg == 0x01) /* The IT is in CR1 register */ { usartxbase += 0x0C; } else if (usartreg == 0x02) /* The IT is in CR2 register */ { usartxbase += 0x10; } else /* The IT is in CR3 register */ { usartxbase += 0x14; } if (NewState != DISABLE) { *(__IO uint32_t*)usartxbase |= itmask; } else { *(__IO uint32_t*)usartxbase &= ~itmask; } } /** * @brief Checks whether the specified USART flag is set or not. * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * UART peripheral. * @param USART_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) * @arg USART_FLAG_LBD: LIN Break detection flag * @arg USART_FLAG_TXE: Transmit data register empty flag * @arg USART_FLAG_TC: Transmission Complete flag * @arg USART_FLAG_RXNE: Receive data register not empty flag * @arg USART_FLAG_IDLE: Idle Line detection flag * @arg USART_FLAG_ORE: OverRun Error flag * @arg USART_FLAG_NE: Noise Error flag * @arg USART_FLAG_FE: Framing Error flag * @arg USART_FLAG_PE: Parity Error flag * @retval The new state of USART_FLAG (SET or RESET). */ FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_USART_FLAG(USART_FLAG)); /* The CTS flag is not available for UART4 and UART5 */ if (USART_FLAG == USART_FLAG_CTS) { assert_param(IS_USART_1236_PERIPH(USARTx)); } if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears the USARTx's pending flags. * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * UART peripheral. * @param USART_FLAG: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). * @arg USART_FLAG_LBD: LIN Break detection flag. * @arg USART_FLAG_TC: Transmission Complete flag. * @arg USART_FLAG_RXNE: Receive data register not empty flag. * * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun * error) and IDLE (Idle line detected) flags are cleared by software * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) * followed by a read operation to USART_DR register (USART_ReceiveData()). * @note RXNE flag can be also cleared by a read to the USART_DR register * (USART_ReceiveData()). * @note TC flag can be also cleared by software sequence: a read operation to * USART_SR register (USART_GetFlagStatus()) followed by a write operation * to USART_DR register (USART_SendData()). * @note TXE flag is cleared only by a write to the USART_DR register * (USART_SendData()). * * @retval None */ void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); /* The CTS flag is not available for UART4 and UART5 */ if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS) { assert_param(IS_USART_1236_PERIPH(USARTx)); } USARTx->SR = (uint16_t)~USART_FLAG; } /** * @brief Checks whether the specified USART interrupt has occurred or not. * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * UART peripheral. * @param USART_IT: specifies the USART interrupt source to check. * This parameter can be one of the following values: * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) * @arg USART_IT_LBD: LIN Break detection interrupt * @arg USART_IT_TXE: Transmit Data Register empty interrupt * @arg USART_IT_TC: Transmission complete interrupt * @arg USART_IT_RXNE: Receive Data register not empty interrupt * @arg USART_IT_IDLE: Idle line detection interrupt * @arg USART_IT_ORE_RX : OverRun Error interrupt if the RXNEIE bit is set * @arg USART_IT_ORE_ER : OverRun Error interrupt if the EIE bit is set * @arg USART_IT_NE: Noise Error interrupt * @arg USART_IT_FE: Framing Error interrupt * @arg USART_IT_PE: Parity Error interrupt * @retval The new state of USART_IT (SET or RESET). */ ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT) { uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; ITStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_USART_GET_IT(USART_IT)); /* The CTS interrupt is not available for UART4 and UART5 */ if (USART_IT == USART_IT_CTS) { assert_param(IS_USART_1236_PERIPH(USARTx)); } /* Get the USART register index */ usartreg = (((uint8_t)USART_IT) >> 0x05); /* Get the interrupt position */ itmask = USART_IT & IT_MASK; itmask = (uint32_t)0x01 << itmask; if (usartreg == 0x01) /* The IT is in CR1 register */ { itmask &= USARTx->CR1; } else if (usartreg == 0x02) /* The IT is in CR2 register */ { itmask &= USARTx->CR2; } else /* The IT is in CR3 register */ { itmask &= USARTx->CR3; } bitpos = USART_IT >> 0x08; bitpos = (uint32_t)0x01 << bitpos; bitpos &= USARTx->SR; if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears the USARTx's interrupt pending bits. * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * UART peripheral. * @param USART_IT: specifies the interrupt pending bit to clear. * This parameter can be one of the following values: * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) * @arg USART_IT_LBD: LIN Break detection interrupt * @arg USART_IT_TC: Transmission complete interrupt. * @arg USART_IT_RXNE: Receive Data register not empty interrupt. * * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun * error) and IDLE (Idle line detected) pending bits are cleared by * software sequence: a read operation to USART_SR register * (USART_GetITStatus()) followed by a read operation to USART_DR register * (USART_ReceiveData()). * @note RXNE pending bit can be also cleared by a read to the USART_DR register * (USART_ReceiveData()). * @note TC pending bit can be also cleared by software sequence: a read * operation to USART_SR register (USART_GetITStatus()) followed by a write * operation to USART_DR register (USART_SendData()). * @note TXE pending bit is cleared only by a write to the USART_DR register * (USART_SendData()). * * @retval None */ void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT) { uint16_t bitpos = 0x00, itmask = 0x00; /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_USART_CLEAR_IT(USART_IT)); /* The CTS interrupt is not available for UART4 and UART5 */ if (USART_IT == USART_IT_CTS) { assert_param(IS_USART_1236_PERIPH(USARTx)); } bitpos = USART_IT >> 0x08; itmask = ((uint16_t)0x01 << (uint16_t)bitpos); USARTx->SR = (uint16_t)~itmask; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c ================================================ /** ****************************************************************************** * @file stm32f4xx_wwdg.c * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief This file provides firmware functions to manage the following * functionalities of the Window watchdog (WWDG) peripheral: * - Prescaler, Refresh window and Counter configuration * - WWDG activation * - Interrupts and flags management * * @verbatim * * =================================================================== * WWDG features * =================================================================== * * Once enabled the WWDG generates a system reset on expiry of a programmed * time period, unless the program refreshes the counter (downcounter) * before to reach 0x3F value (i.e. a reset is generated when the counter * value rolls over from 0x40 to 0x3F). * An MCU reset is also generated if the counter value is refreshed * before the counter has reached the refresh window value. This * implies that the counter must be refreshed in a limited window. * * Once enabled the WWDG cannot be disabled except by a system reset. * * WWDGRST flag in RCC_CSR register can be used to inform when a WWDG * reset occurs. * * The WWDG counter input clock is derived from the APB clock divided * by a programmable prescaler. * * WWDG counter clock = PCLK1 / Prescaler * WWDG timeout = (WWDG counter clock) * (counter value) * * Min-max timeout value @42 MHz(PCLK1): ~97.5 us / ~49.9 ms * * =================================================================== * How to use this driver * =================================================================== * 1. Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) function * * 2. Configure the WWDG prescaler using WWDG_SetPrescaler() function * * 3. Configure the WWDG refresh window using WWDG_SetWindowValue() function * * 4. Set the WWDG counter value and start it using WWDG_Enable() function. * When the WWDG is enabled the counter value should be configured to * a value greater than 0x40 to prevent generating an immediate reset. * * 5. Optionally you can enable the Early wakeup interrupt which is * generated when the counter reach 0x40. * Once enabled this interrupt cannot be disabled except by a system reset. * * 6. Then the application program must refresh the WWDG counter at regular * intervals during normal operation to prevent an MCU reset, using * WWDG_SetCounter() function. This operation must occur only when * the counter value is lower than the refresh window value, * programmed using WWDG_SetWindowValue(). * * @endverbatim * ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_wwdg.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup WWDG * @brief WWDG driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* ----------- WWDG registers bit address in the alias region ----------- */ #define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE) /* Alias word address of EWI bit */ #define CFR_OFFSET (WWDG_OFFSET + 0x04) #define EWI_BitNumber 0x09 #define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4)) /* --------------------- WWDG registers bit mask ------------------------ */ /* CFR register bit mask */ #define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F) #define CFR_W_MASK ((uint32_t)0xFFFFFF80) #define BIT_MASK ((uint8_t)0x7F) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup WWDG_Private_Functions * @{ */ /** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions * @brief Prescaler, Refresh window and Counter configuration functions * @verbatim =============================================================================== Prescaler, Refresh window and Counter configuration functions =============================================================================== @endverbatim * @{ */ /** * @brief Deinitializes the WWDG peripheral registers to their default reset values. * @param None * @retval None */ void WWDG_DeInit(void) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); } /** * @brief Sets the WWDG Prescaler. * @param WWDG_Prescaler: specifies the WWDG Prescaler. * This parameter can be one of the following values: * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 * @retval None */ void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); /* Clear WDGTB[1:0] bits */ tmpreg = WWDG->CFR & CFR_WDGTB_MASK; /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ tmpreg |= WWDG_Prescaler; /* Store the new value */ WWDG->CFR = tmpreg; } /** * @brief Sets the WWDG window value. * @param WindowValue: specifies the window value to be compared to the downcounter. * This parameter value must be lower than 0x80. * @retval None */ void WWDG_SetWindowValue(uint8_t WindowValue) { __IO uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); /* Clear W[6:0] bits */ tmpreg = WWDG->CFR & CFR_W_MASK; /* Set W[6:0] bits according to WindowValue value */ tmpreg |= WindowValue & (uint32_t) BIT_MASK; /* Store the new value */ WWDG->CFR = tmpreg; } /** * @brief Enables the WWDG Early Wakeup interrupt(EWI). * @note Once enabled this interrupt cannot be disabled except by a system reset. * @param None * @retval None */ void WWDG_EnableIT(void) { *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; } /** * @brief Sets the WWDG counter value. * @param Counter: specifies the watchdog counter value. * This parameter must be a number between 0x40 and 0x7F (to prevent generating * an immediate reset) * @retval None */ void WWDG_SetCounter(uint8_t Counter) { /* Check the parameters */ assert_param(IS_WWDG_COUNTER(Counter)); /* Write to T[6:0] bits to configure the counter value, no need to do a read-modify-write; writing a 0 to WDGA bit does nothing */ WWDG->CR = Counter & BIT_MASK; } /** * @} */ /** @defgroup WWDG_Group2 WWDG activation functions * @brief WWDG activation functions * @verbatim =============================================================================== WWDG activation function =============================================================================== @endverbatim * @{ */ /** * @brief Enables WWDG and load the counter value. * @param Counter: specifies the watchdog counter value. * This parameter must be a number between 0x40 and 0x7F (to prevent generating * an immediate reset) * @retval None */ void WWDG_Enable(uint8_t Counter) { /* Check the parameters */ assert_param(IS_WWDG_COUNTER(Counter)); WWDG->CR = WWDG_CR_WDGA | Counter; } /** * @} */ /** @defgroup WWDG_Group3 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== Interrupts and flags management functions =============================================================================== @endverbatim * @{ */ /** * @brief Checks whether the Early Wakeup interrupt flag is set or not. * @param None * @retval The new state of the Early Wakeup interrupt flag (SET or RESET) */ FlagStatus WWDG_GetFlagStatus(void) { FlagStatus bitstatus = RESET; if ((WWDG->SR) != (uint32_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears Early Wakeup interrupt flag. * @param None * @retval None */ void WWDG_ClearFlag(void) { WWDG->SR = (uint32_t)RESET; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/README ================================================ Figure simulator for STM32F4 Discovery board. Builds with Atollic Questions? Comments? Contributions? Contact: namely_audacious@hotmail.com / @natashenka ================================================ FILE: figure-simulator-discovery/Utilities/STM32F4-Discovery/Release_Notes.html ================================================ Release Notes for STM32F4-Discovery Board Drivers


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Release Notes for STM32F4-Discovery Board Drivers

Copyright 2012 STMicroelectronics

 

Contents

  1. STM32F4-Discovery Board Drivers update History
  2. License

STM32F4-Discovery Board Drivers update History

For more information on the STM32F4-Discovery board visit www.st.com/stm32f4-discovery.

V1.1.1 / 14-May-2012

Main Changes

  • All source files: license disclaimer text update and add link to the License file on ST Internet.

V1.1.0 / 28-October-2011

Main Changes

  • Add PDM audio software decoding Library drivers, used to decode and reconstruct the audio signal produced by MP45DT02 MEMS microphone from STMicroelectronics. For more details about this Library, please refer to document "PDM audio software decoding on STM32 microcontrollers (AN3998)".
  • stm32f4_discovery_audio_codec.c/.h: update to use DMA instead of Interrupt in I2S communication with the external codec.

V1.0.0 / 19-September-2011

Main Changes

  • First official version of the STM32F4-Discovery Board Drivers

License

The PDM audio software decoding Library is licensed under MCD-ST Image SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:


Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Other STM32F4-Discovery board drivers are licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:


Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

For complete documentation on STMicroelectronics Microcontrollers visit www.st.com

 

================================================ FILE: figure-simulator-discovery/Utilities/STM32F4-Discovery/pdm_filter.h ================================================ /** ****************************************************************************** * @file pdm_filter.h * @author MCD Application Team * @version V1.1.1 * @date 14-May-2012 * @brief Header file for PDM audio software decoding Library. * This Library is used to decode and reconstruct the audio signal * produced by MP45DT02 MEMS microphone from STMicroelectronics. * For more details about this Library, please refer to document * "PDM audio software decoding on STM32 microcontrollers (AN3998)". ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Image SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_image_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __PDM_FILTER_H #define __PDM_FILTER_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include /* Exported types ------------------------------------------------------------*/ typedef struct { uint16_t Fs; float LP_HZ; float HP_HZ; uint16_t In_MicChannels; uint16_t Out_MicChannels; char InternalFilter[34]; } PDMFilter_InitStruct; /* Exported constants --------------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/ #define HTONS(A) ((((u16)(A) & 0xff00) >> 8) | \ (((u16)(A) & 0x00ff) << 8)) /* Exported functions ------------------------------------------------------- */ void PDM_Filter_Init(PDMFilter_InitStruct * Filter); int32_t PDM_Filter_64_MSB(uint8_t* data, uint16_t* dataOut, uint16_t MicGain, PDMFilter_InitStruct * Filter); int32_t PDM_Filter_80_MSB(uint8_t* data, uint16_t* dataOut, uint16_t MicGain, PDMFilter_InitStruct * Filter); int32_t PDM_Filter_64_LSB(uint8_t* data, uint16_t* dataOut, uint16_t MicGain, PDMFilter_InitStruct * Filter); int32_t PDM_Filter_80_LSB(uint8_t* data, uint16_t* dataOut, uint16_t MicGain, PDMFilter_InitStruct * Filter); #ifdef __cplusplus } #endif #endif /* __PDM_FILTER_H */ /*******************(C)COPYRIGHT 2011 STMicroelectronics *****END OF FILE******/ ================================================ FILE: figure-simulator-discovery/Utilities/STM32F4-Discovery/stm32f4_discovery.c ================================================ /** ****************************************************************************** * @file stm32f4_discovery.c * @author MCD Application Team * @version V1.1.1 * @date 14-May-2012 * @brief This file provides set of firmware functions to manage Leds and * push-button available on STM32F4-Discovery Kit from STMicroelectronics. ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4_discovery.h" /** @addtogroup Utilities * @{ */ /** @addtogroup STM32F4_DISCOVERY * @{ */ /** @defgroup STM32F4_DISCOVERY_LOW_LEVEL * @brief This file provides set of firmware functions to manage Leds and push-button * available on STM32F4-Discovery Kit from STMicroelectronics. * @{ */ /** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Private_TypesDefinitions * @{ */ /** * @} */ /** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Private_Defines * @{ */ /** * @} */ /** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Private_Macros * @{ */ /** * @} */ /** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Private_Variables * @{ */ GPIO_TypeDef* GPIO_PORT[LEDn] = {LED4_GPIO_PORT, LED3_GPIO_PORT, LED5_GPIO_PORT, LED6_GPIO_PORT}; const uint16_t GPIO_PIN[LEDn] = {LED4_PIN, LED3_PIN, LED5_PIN, LED6_PIN}; const uint32_t GPIO_CLK[LEDn] = {LED4_GPIO_CLK, LED3_GPIO_CLK, LED5_GPIO_CLK, LED6_GPIO_CLK}; GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {USER_BUTTON_GPIO_PORT }; const uint16_t BUTTON_PIN[BUTTONn] = {USER_BUTTON_PIN }; const uint32_t BUTTON_CLK[BUTTONn] = {USER_BUTTON_GPIO_CLK }; const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {USER_BUTTON_EXTI_LINE }; const uint8_t BUTTON_PORT_SOURCE[BUTTONn] = {USER_BUTTON_EXTI_PORT_SOURCE}; const uint8_t BUTTON_PIN_SOURCE[BUTTONn] = {USER_BUTTON_EXTI_PIN_SOURCE }; const uint8_t BUTTON_IRQn[BUTTONn] = {USER_BUTTON_EXTI_IRQn }; NVIC_InitTypeDef NVIC_InitStructure; /** * @} */ /** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Private_FunctionPrototypes * @{ */ /** * @} */ /** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Private_Functions * @{ */ /** * @brief Configures LED GPIO. * @param Led: Specifies the Led to be configured. * This parameter can be one of following parameters: * @arg LED4 * @arg LED3 * @arg LED5 * @arg LED6 * @retval None */ void STM_EVAL_LEDInit(Led_TypeDef Led) { GPIO_InitTypeDef GPIO_InitStructure; /* Enable the GPIO_LED Clock */ RCC_AHB1PeriphClockCmd(GPIO_CLK[Led], ENABLE); /* Configure the GPIO_LED pin */ GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led]; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure); } /** * @brief Turns selected LED On. * @param Led: Specifies the Led to be set on. * This parameter can be one of following parameters: * @arg LED4 * @arg LED3 * @arg LED5 * @arg LED6 * @retval None */ void STM_EVAL_LEDOn(Led_TypeDef Led) { GPIO_PORT[Led]->BSRRL = GPIO_PIN[Led]; } /** * @brief Turns selected LED Off. * @param Led: Specifies the Led to be set off. * This parameter can be one of following parameters: * @arg LED4 * @arg LED3 * @arg LED5 * @arg LED6 * @retval None */ void STM_EVAL_LEDOff(Led_TypeDef Led) { GPIO_PORT[Led]->BSRRH = GPIO_PIN[Led]; } /** * @brief Toggles the selected LED. * @param Led: Specifies the Led to be toggled. * This parameter can be one of following parameters: * @arg LED4 * @arg LED3 * @arg LED5 * @arg LED6 * @retval None */ void STM_EVAL_LEDToggle(Led_TypeDef Led) { GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led]; } /** * @brief Configures Button GPIO and EXTI Line. * @param Button: Specifies the Button to be configured. * This parameter should be: BUTTON_USER * @param Button_Mode: Specifies Button mode. * This parameter can be one of following parameters: * @arg BUTTON_MODE_GPIO: Button will be used as simple IO * @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt * generation capability * @retval None */ void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode) { GPIO_InitTypeDef GPIO_InitStructure; EXTI_InitTypeDef EXTI_InitStructure; NVIC_InitTypeDef NVIC_InitStructure; /* Enable the BUTTON Clock */ RCC_AHB1PeriphClockCmd(BUTTON_CLK[Button], ENABLE); RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); /* Configure Button pin as input */ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button]; GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure); if (Button_Mode == BUTTON_MODE_EXTI) { /* Connect Button EXTI Line to Button GPIO Pin */ SYSCFG_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]); /* Configure Button EXTI line */ EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button]; EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; EXTI_InitStructure.EXTI_LineCmd = ENABLE; EXTI_Init(&EXTI_InitStructure); /* Enable and set Button EXTI Interrupt to the lowest priority */ NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button]; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); } } /** * @brief Returns the selected Button state. * @param Button: Specifies the Button to be checked. * This parameter should be: BUTTON_USER * @retval The Button GPIO pin value. */ uint32_t STM_EVAL_PBGetState(Button_TypeDef Button) { return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]); } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Utilities/STM32F4-Discovery/stm32f4_discovery.h ================================================ /** ****************************************************************************** * @file stm32f4_discovery.h * @author MCD Application Team * @version V1.1.1 * @date 14-May-2012 * @brief This file contains definitions for STM32F4-Discovery Kit's Leds and * push-button hardware resources. ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4_DISCOVERY_H #define __STM32F4_DISCOVERY_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup Utilities * @{ */ /** @addtogroup STM32F4_DISCOVERY * @{ */ /** @addtogroup STM32F4_DISCOVERY_LOW_LEVEL * @{ */ /** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Types * @{ */ typedef enum { LED4 = 0, LED3 = 1, LED5 = 2, LED6 = 3 } Led_TypeDef; typedef enum { BUTTON_USER = 0, } Button_TypeDef; typedef enum { BUTTON_MODE_GPIO = 0, BUTTON_MODE_EXTI = 1 } ButtonMode_TypeDef; /** * @} */ /** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Constants * @{ */ /** @addtogroup STM32F4_DISCOVERY_LOW_LEVEL_LED * @{ */ #define LEDn 4 #define LED4_PIN GPIO_Pin_12 #define LED4_GPIO_PORT GPIOD #define LED4_GPIO_CLK RCC_AHB1Periph_GPIOD #define LED3_PIN GPIO_Pin_13 #define LED3_GPIO_PORT GPIOD #define LED3_GPIO_CLK RCC_AHB1Periph_GPIOD #define LED5_PIN GPIO_Pin_14 #define LED5_GPIO_PORT GPIOD #define LED5_GPIO_CLK RCC_AHB1Periph_GPIOD #define LED6_PIN GPIO_Pin_15 #define LED6_GPIO_PORT GPIOD #define LED6_GPIO_CLK RCC_AHB1Periph_GPIOD /** * @} */ /** @addtogroup STM32F4_DISCOVERY_LOW_LEVEL_BUTTON * @{ */ #define BUTTONn 1 /** * @brief Wakeup push-button */ #define USER_BUTTON_PIN GPIO_Pin_0 #define USER_BUTTON_GPIO_PORT GPIOA #define USER_BUTTON_GPIO_CLK RCC_AHB1Periph_GPIOA #define USER_BUTTON_EXTI_LINE EXTI_Line0 #define USER_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOA #define USER_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource0 #define USER_BUTTON_EXTI_IRQn EXTI0_IRQn /** * @} */ /** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Macros * @{ */ /** * @} */ /** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Functions * @{ */ void STM_EVAL_LEDInit(Led_TypeDef Led); void STM_EVAL_LEDOn(Led_TypeDef Led); void STM_EVAL_LEDOff(Led_TypeDef Led); void STM_EVAL_LEDToggle(Led_TypeDef Led); void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode); uint32_t STM_EVAL_PBGetState(Button_TypeDef Button); /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F4_DISCOVERY_H */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Utilities/STM32F4-Discovery/stm32f4_discovery_lis302dl.c ================================================ /** ****************************************************************************** * @file stm32f4_discovery_lis302dl.c * @author MCD Application Team * @version V1.1.1 * @date 14-May-2012 * @brief This file provides a set of functions needed to manage the LIS302DL * MEMS accelerometer available on STM32F4-Discovery Kit. ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4_discovery_lis302dl.h" /** @addtogroup Utilities * @{ */ /** @addtogroup STM32F4_DISCOVERY * @{ */ /** @addtogroup STM32F4_DISCOVERY_LIS302DL * @{ */ /** @defgroup STM32F4_DISCOVERY_LIS302DL_Private_TypesDefinitions * @{ */ /** * @} */ /** @defgroup STM32F4_DISCOVERY_LIS302DL_Private_Defines * @{ */ __IO uint32_t LIS302DLTimeout = LIS302DL_FLAG_TIMEOUT; /* Read/Write command */ #define READWRITE_CMD ((uint8_t)0x80) /* Multiple byte read/write command */ #define MULTIPLEBYTE_CMD ((uint8_t)0x40) /* Dummy Byte Send by the SPI Master device in order to generate the Clock to the Slave device */ #define DUMMY_BYTE ((uint8_t)0x00) /** * @} */ /** @defgroup STM32F4_DISCOVERY_LIS302DL_Private_Macros * @{ */ /** * @} */ /** @defgroup STM32F4_DISCOVERY_LIS302DL_Private_Variables * @{ */ /** * @} */ /** @defgroup STM32F4_DISCOVERY_LIS302DL_Private_FunctionPrototypes * @{ */ static uint8_t LIS302DL_SendByte(uint8_t byte); static void LIS302DL_LowLevel_Init(void); /** * @} */ /** @defgroup STM32F4_DISCOVERY_LIS302DL_Private_Functions * @{ */ /** * @brief Set LIS302DL Initialization. * @param LIS302DL_Config_Struct: pointer to a LIS302DL_Config_TypeDef structure * that contains the configuration setting for the LIS302DL. * @retval None */ void LIS302DL_Init(LIS302DL_InitTypeDef *LIS302DL_InitStruct) { uint8_t ctrl = 0x00; /* Configure the low level interface ---------------------------------------*/ LIS302DL_LowLevel_Init(); /* Configure MEMS: data rate, power mode, full scale, self test and axes */ ctrl = (uint8_t) (LIS302DL_InitStruct->Output_DataRate | LIS302DL_InitStruct->Power_Mode | \ LIS302DL_InitStruct->Full_Scale | LIS302DL_InitStruct->Self_Test | \ LIS302DL_InitStruct->Axes_Enable); /* Write value to MEMS CTRL_REG1 regsister */ LIS302DL_Write(&ctrl, LIS302DL_CTRL_REG1_ADDR, 1); } /** * @brief Set LIS302DL Internal High Pass Filter configuration. * @param LIS302DL_Filter_ConfigTypeDef: pointer to a LIS302DL_FilterConfig_TypeDef * structure that contains the configuration setting for the LIS302DL Filter. * @retval None */ void LIS302DL_FilterConfig(LIS302DL_FilterConfigTypeDef *LIS302DL_FilterConfigStruct) { uint8_t ctrl = 0x00; /* Read CTRL_REG2 register */ LIS302DL_Read(&ctrl, LIS302DL_CTRL_REG2_ADDR, 1); /* Clear high pass filter cut-off level, interrupt and data selection bits*/ ctrl &= (uint8_t)~(LIS302DL_FILTEREDDATASELECTION_OUTPUTREGISTER | \ LIS302DL_HIGHPASSFILTER_LEVEL_3 | \ LIS302DL_HIGHPASSFILTERINTERRUPT_1_2); /* Configure MEMS high pass filter cut-off level, interrupt and data selection bits */ ctrl |= (uint8_t)(LIS302DL_FilterConfigStruct->HighPassFilter_Data_Selection | \ LIS302DL_FilterConfigStruct->HighPassFilter_CutOff_Frequency | \ LIS302DL_FilterConfigStruct->HighPassFilter_Interrupt); /* Write value to MEMS CTRL_REG2 register */ LIS302DL_Write(&ctrl, LIS302DL_CTRL_REG2_ADDR, 1); } /** * @brief Set LIS302DL Interrupt configuration * @param LIS302DL_InterruptConfig_TypeDef: pointer to a LIS302DL_InterruptConfig_TypeDef * structure that contains the configuration setting for the LIS302DL Interrupt. * @retval None */ void LIS302DL_InterruptConfig(LIS302DL_InterruptConfigTypeDef *LIS302DL_IntConfigStruct) { uint8_t ctrl = 0x00; /* Read CLICK_CFG register */ LIS302DL_Read(&ctrl, LIS302DL_CLICK_CFG_REG_ADDR, 1); /* Configure latch Interrupt request, click interrupts and double click interrupts */ ctrl = (uint8_t)(LIS302DL_IntConfigStruct->Latch_Request| \ LIS302DL_IntConfigStruct->SingleClick_Axes | \ LIS302DL_IntConfigStruct->DoubleClick_Axes); /* Write value to MEMS CLICK_CFG register */ LIS302DL_Write(&ctrl, LIS302DL_CLICK_CFG_REG_ADDR, 1); } /** * @brief Change the lowpower mode for LIS302DL * @param LowPowerMode: new state for the lowpower mode. * This parameter can be one of the following values: * @arg LIS302DL_LOWPOWERMODE_POWERDOWN: Power down mode * @arg LIS302DL_LOWPOWERMODE_ACTIVE: Active mode * @retval None */ void LIS302DL_LowpowerCmd(uint8_t LowPowerMode) { uint8_t tmpreg; /* Read CTRL_REG1 register */ LIS302DL_Read(&tmpreg, LIS302DL_CTRL_REG1_ADDR, 1); /* Set new low power mode configuration */ tmpreg &= (uint8_t)~LIS302DL_LOWPOWERMODE_ACTIVE; tmpreg |= LowPowerMode; /* Write value to MEMS CTRL_REG1 regsister */ LIS302DL_Write(&tmpreg, LIS302DL_CTRL_REG1_ADDR, 1); } /** * @brief Data Rate command * @param DataRateValue: Data rate value * This parameter can be one of the following values: * @arg LIS302DL_DATARATE_100: 100 Hz output data rate * @arg LIS302DL_DATARATE_400: 400 Hz output data rate * @retval None */ void LIS302DL_DataRateCmd(uint8_t DataRateValue) { uint8_t tmpreg; /* Read CTRL_REG1 register */ LIS302DL_Read(&tmpreg, LIS302DL_CTRL_REG1_ADDR, 1); /* Set new Data rate configuration */ tmpreg &= (uint8_t)~LIS302DL_DATARATE_400; tmpreg |= DataRateValue; /* Write value to MEMS CTRL_REG1 regsister */ LIS302DL_Write(&tmpreg, LIS302DL_CTRL_REG1_ADDR, 1); } /** * @brief Change the Full Scale of LIS302DL * @param FS_value: new full scale value. * This parameter can be one of the following values: * @arg LIS302DL_FULLSCALE_2_3: +-2.3g * @arg LIS302DL_FULLSCALE_9_2: +-9.2g * @retval None */ void LIS302DL_FullScaleCmd(uint8_t FS_value) { uint8_t tmpreg; /* Read CTRL_REG1 register */ LIS302DL_Read(&tmpreg, LIS302DL_CTRL_REG1_ADDR, 1); /* Set new full scale configuration */ tmpreg &= (uint8_t)~LIS302DL_FULLSCALE_9_2; tmpreg |= FS_value; /* Write value to MEMS CTRL_REG1 regsister */ LIS302DL_Write(&tmpreg, LIS302DL_CTRL_REG1_ADDR, 1); } /** * @brief Reboot memory content of LIS302DL * @param None * @retval None */ void LIS302DL_RebootCmd(void) { uint8_t tmpreg; /* Read CTRL_REG2 register */ LIS302DL_Read(&tmpreg, LIS302DL_CTRL_REG2_ADDR, 1); /* Enable or Disable the reboot memory */ tmpreg |= LIS302DL_BOOT_REBOOTMEMORY; /* Write value to MEMS CTRL_REG2 regsister */ LIS302DL_Write(&tmpreg, LIS302DL_CTRL_REG2_ADDR, 1); } /** * @brief Writes one byte to the LIS302DL. * @param pBuffer : pointer to the buffer containing the data to be written to the LIS302DL. * @param WriteAddr : LIS302DL's internal address to write to. * @param NumByteToWrite: Number of bytes to write. * @retval None */ void LIS302DL_Write(uint8_t* pBuffer, uint8_t WriteAddr, uint16_t NumByteToWrite) { /* Configure the MS bit: - When 0, the address will remain unchanged in multiple read/write commands. - When 1, the address will be auto incremented in multiple read/write commands. */ if(NumByteToWrite > 0x01) { WriteAddr |= (uint8_t)MULTIPLEBYTE_CMD; } /* Set chip select Low at the start of the transmission */ LIS302DL_CS_LOW(); /* Send the Address of the indexed register */ LIS302DL_SendByte(WriteAddr); /* Send the data that will be written into the device (MSB First) */ while(NumByteToWrite >= 0x01) { LIS302DL_SendByte(*pBuffer); NumByteToWrite--; pBuffer++; } /* Set chip select High at the end of the transmission */ LIS302DL_CS_HIGH(); } /** * @brief Reads a block of data from the LIS302DL. * @param pBuffer : pointer to the buffer that receives the data read from the LIS302DL. * @param ReadAddr : LIS302DL's internal address to read from. * @param NumByteToRead : number of bytes to read from the LIS302DL. * @retval None */ void LIS302DL_Read(uint8_t* pBuffer, uint8_t ReadAddr, uint16_t NumByteToRead) { if(NumByteToRead > 0x01) { ReadAddr |= (uint8_t)(READWRITE_CMD | MULTIPLEBYTE_CMD); } else { ReadAddr |= (uint8_t)READWRITE_CMD; } /* Set chip select Low at the start of the transmission */ LIS302DL_CS_LOW(); /* Send the Address of the indexed register */ LIS302DL_SendByte(ReadAddr); /* Receive the data that will be read from the device (MSB First) */ while(NumByteToRead > 0x00) { /* Send dummy byte (0x00) to generate the SPI clock to LIS302DL (Slave device) */ *pBuffer = LIS302DL_SendByte(DUMMY_BYTE); NumByteToRead--; pBuffer++; } /* Set chip select High at the end of the transmission */ LIS302DL_CS_HIGH(); } /** * @brief Read LIS302DL output register, and calculate the acceleration * ACC[mg]=SENSITIVITY* (out_h*256+out_l)/16 (12 bit rappresentation) * @param s16 buffer to store data * @retval None */ void LIS302DL_ReadACC(int32_t* out) { uint8_t buffer[6]; uint8_t crtl, i = 0x00; LIS302DL_Read(&crtl, LIS302DL_CTRL_REG1_ADDR, 1); LIS302DL_Read(buffer, LIS302DL_OUT_X_ADDR, 6); switch(crtl & 0x20) { /* FS bit = 0 ==> Sensitivity typical value = 18milligals/digit*/ case 0x00: for(i=0; i<0x03; i++) { *out =(int32_t)(LIS302DL_SENSITIVITY_2_3G * (int8_t)buffer[2*i]); out++; } break; /* FS bit = 1 ==> Sensitivity typical value = 72milligals/digit*/ case 0x20: for(i=0; i<0x03; i++) { *out =(int32_t)(LIS302DL_SENSITIVITY_9_2G * (int8_t)buffer[2*i]); out++; } break; default: break; } } /** * @brief Initializes the low level interface used to drive the LIS302DL * @param None * @retval None */ static void LIS302DL_LowLevel_Init(void) { GPIO_InitTypeDef GPIO_InitStructure; SPI_InitTypeDef SPI_InitStructure; /* Enable the SPI periph */ RCC_APB2PeriphClockCmd(LIS302DL_SPI_CLK, ENABLE); /* Enable SCK, MOSI and MISO GPIO clocks */ RCC_AHB1PeriphClockCmd(LIS302DL_SPI_SCK_GPIO_CLK | LIS302DL_SPI_MISO_GPIO_CLK | LIS302DL_SPI_MOSI_GPIO_CLK, ENABLE); /* Enable CS GPIO clock */ RCC_AHB1PeriphClockCmd(LIS302DL_SPI_CS_GPIO_CLK, ENABLE); /* Enable INT1 GPIO clock */ RCC_AHB1PeriphClockCmd(LIS302DL_SPI_INT1_GPIO_CLK, ENABLE); /* Enable INT2 GPIO clock */ RCC_AHB1PeriphClockCmd(LIS302DL_SPI_INT2_GPIO_CLK, ENABLE); GPIO_PinAFConfig(LIS302DL_SPI_SCK_GPIO_PORT, LIS302DL_SPI_SCK_SOURCE, LIS302DL_SPI_SCK_AF); GPIO_PinAFConfig(LIS302DL_SPI_MISO_GPIO_PORT, LIS302DL_SPI_MISO_SOURCE, LIS302DL_SPI_MISO_AF); GPIO_PinAFConfig(LIS302DL_SPI_MOSI_GPIO_PORT, LIS302DL_SPI_MOSI_SOURCE, LIS302DL_SPI_MOSI_AF); GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; /* SPI SCK pin configuration */ GPIO_InitStructure.GPIO_Pin = LIS302DL_SPI_SCK_PIN; GPIO_Init(LIS302DL_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); /* SPI MOSI pin configuration */ GPIO_InitStructure.GPIO_Pin = LIS302DL_SPI_MOSI_PIN; GPIO_Init(LIS302DL_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); /* SPI MISO pin configuration */ GPIO_InitStructure.GPIO_Pin = LIS302DL_SPI_MISO_PIN; GPIO_Init(LIS302DL_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); /* SPI configuration -------------------------------------------------------*/ SPI_I2S_DeInit(LIS302DL_SPI); SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4; SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; SPI_InitStructure.SPI_CRCPolynomial = 7; SPI_InitStructure.SPI_Mode = SPI_Mode_Master; SPI_Init(LIS302DL_SPI, &SPI_InitStructure); /* Enable SPI1 */ SPI_Cmd(LIS302DL_SPI, ENABLE); /* Configure GPIO PIN for Lis Chip select */ GPIO_InitStructure.GPIO_Pin = LIS302DL_SPI_CS_PIN; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; GPIO_Init(LIS302DL_SPI_CS_GPIO_PORT, &GPIO_InitStructure); /* Deselect : Chip Select high */ GPIO_SetBits(LIS302DL_SPI_CS_GPIO_PORT, LIS302DL_SPI_CS_PIN); /* Configure GPIO PINs to detect Interrupts */ GPIO_InitStructure.GPIO_Pin = LIS302DL_SPI_INT1_PIN; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_Init(LIS302DL_SPI_INT1_GPIO_PORT, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Pin = LIS302DL_SPI_INT2_PIN; GPIO_Init(LIS302DL_SPI_INT2_GPIO_PORT, &GPIO_InitStructure); } /** * @brief Sends a Byte through the SPI interface and return the Byte received * from the SPI bus. * @param Byte : Byte send. * @retval The received byte value */ static uint8_t LIS302DL_SendByte(uint8_t byte) { /* Loop while DR register in not emplty */ LIS302DLTimeout = LIS302DL_FLAG_TIMEOUT; while (SPI_I2S_GetFlagStatus(LIS302DL_SPI, SPI_I2S_FLAG_TXE) == RESET) { if((LIS302DLTimeout--) == 0) return LIS302DL_TIMEOUT_UserCallback(); } /* Send a Byte through the SPI peripheral */ SPI_I2S_SendData(LIS302DL_SPI, byte); /* Wait to receive a Byte */ LIS302DLTimeout = LIS302DL_FLAG_TIMEOUT; while (SPI_I2S_GetFlagStatus(LIS302DL_SPI, SPI_I2S_FLAG_RXNE) == RESET) { if((LIS302DLTimeout--) == 0) return LIS302DL_TIMEOUT_UserCallback(); } /* Return the Byte read from the SPI bus */ return (uint8_t)SPI_I2S_ReceiveData(LIS302DL_SPI); } #ifdef USE_DEFAULT_TIMEOUT_CALLBACK /** * @brief Basic management of the timeout situation. * @param None. * @retval None. */ uint32_t LIS302DL_TIMEOUT_UserCallback(void) { /* Block communication and all processes */ while (1) { } } #endif /* USE_DEFAULT_TIMEOUT_CALLBACK */ /** * @} */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/Utilities/STM32F4-Discovery/stm32f4_discovery_lis302dl.h ================================================ /** ****************************************************************************** * @file stm32f4_discovery_lis302dl.h * @author MCD Application Team * @version V1.1.1 * @date 14-May-2012 * @brief This file contains all the functions prototypes for the stm32f4_discovery_lis302dl.c * firmware driver. ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4_DISCOVERY_LIS302DL_H #define __STM32F4_DISCOVERY_LIS302DL_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup Utilities * @{ */ /** @addtogroup STM32F4_DISCOVERY * @{ */ /** @addtogroup STM32F4_DISCOVERY_LIS302DL * @{ */ /** @defgroup STM32F4_DISCOVERY_LIS302DL_Exported_Types * @{ */ /* LIS302DL struct */ typedef struct { uint8_t Power_Mode; /* Power-down/Active Mode */ uint8_t Output_DataRate; /* OUT data rate 100 Hz / 400 Hz */ uint8_t Axes_Enable; /* Axes enable */ uint8_t Full_Scale; /* Full scale */ uint8_t Self_Test; /* Self test */ }LIS302DL_InitTypeDef; /* LIS302DL High Pass Filter struct */ typedef struct { uint8_t HighPassFilter_Data_Selection; /* Internal filter bypassed or data from internal filter send to output register*/ uint8_t HighPassFilter_CutOff_Frequency; /* High pass filter cut-off frequency */ uint8_t HighPassFilter_Interrupt; /* High pass filter enabled for Freefall/WakeUp #1 or #2 */ }LIS302DL_FilterConfigTypeDef; /* LIS302DL Interrupt struct */ typedef struct { uint8_t Latch_Request; /* Latch interrupt request into CLICK_SRC register*/ uint8_t SingleClick_Axes; /* Single Click Axes Interrupts */ uint8_t DoubleClick_Axes; /* Double Click Axes Interrupts */ }LIS302DL_InterruptConfigTypeDef; /** * @} */ /** @defgroup STM32F4_DISCOVERY_LIS302DL_Exported_Constants * @{ */ /* Uncomment the following line to use the default LIS302DL_TIMEOUT_UserCallback() function implemented in stm32f4_discovery_lis302dl.c file. LIS302DL_TIMEOUT_UserCallback() function is called whenever a timeout condition occure during communication (waiting transmit data register empty flag(TXE) or waiting receive data register is not empty flag (RXNE)). */ /* #define USE_DEFAULT_TIMEOUT_CALLBACK */ /* Maximum Timeout values for flags waiting loops. These timeouts are not based on accurate values, they just guarantee that the application will not remain stuck if the SPI communication is corrupted. You may modify these timeout values depending on CPU frequency and application conditions (interrupts routines ...). */ #define LIS302DL_FLAG_TIMEOUT ((uint32_t)0x1000) /** * @brief LIS302DL SPI Interface pins */ #define LIS302DL_SPI SPI1 #define LIS302DL_SPI_CLK RCC_APB2Periph_SPI1 #define LIS302DL_SPI_SCK_PIN GPIO_Pin_5 /* PA.05 */ #define LIS302DL_SPI_SCK_GPIO_PORT GPIOA /* GPIOA */ #define LIS302DL_SPI_SCK_GPIO_CLK RCC_AHB1Periph_GPIOA #define LIS302DL_SPI_SCK_SOURCE GPIO_PinSource5 #define LIS302DL_SPI_SCK_AF GPIO_AF_SPI1 #define LIS302DL_SPI_MISO_PIN GPIO_Pin_6 /* PA.6 */ #define LIS302DL_SPI_MISO_GPIO_PORT GPIOA /* GPIOA */ #define LIS302DL_SPI_MISO_GPIO_CLK RCC_AHB1Periph_GPIOA #define LIS302DL_SPI_MISO_SOURCE GPIO_PinSource6 #define LIS302DL_SPI_MISO_AF GPIO_AF_SPI1 #define LIS302DL_SPI_MOSI_PIN GPIO_Pin_7 /* PA.7 */ #define LIS302DL_SPI_MOSI_GPIO_PORT GPIOA /* GPIOA */ #define LIS302DL_SPI_MOSI_GPIO_CLK RCC_AHB1Periph_GPIOA #define LIS302DL_SPI_MOSI_SOURCE GPIO_PinSource7 #define LIS302DL_SPI_MOSI_AF GPIO_AF_SPI1 #define LIS302DL_SPI_CS_PIN GPIO_Pin_3 /* PE.03 */ #define LIS302DL_SPI_CS_GPIO_PORT GPIOE /* GPIOE */ #define LIS302DL_SPI_CS_GPIO_CLK RCC_AHB1Periph_GPIOE #define LIS302DL_SPI_INT1_PIN GPIO_Pin_0 /* PE.00 */ #define LIS302DL_SPI_INT1_GPIO_PORT GPIOE /* GPIOE */ #define LIS302DL_SPI_INT1_GPIO_CLK RCC_AHB1Periph_GPIOE #define LIS302DL_SPI_INT1_EXTI_LINE EXTI_Line0 #define LIS302DL_SPI_INT1_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE #define LIS302DL_SPI_INT1_EXTI_PIN_SOURCE EXTI_PinSource0 #define LIS302DL_SPI_INT1_EXTI_IRQn EXTI0_IRQn #define LIS302DL_SPI_INT2_PIN GPIO_Pin_1 /* PE.01 */ #define LIS302DL_SPI_INT2_GPIO_PORT GPIOE /* GPIOE */ #define LIS302DL_SPI_INT2_GPIO_CLK RCC_AHB1Periph_GPIOE #define LIS302DL_SPI_INT2_EXTI_LINE EXTI_Line1 #define LIS302DL_SPI_INT2_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE #define LIS302DL_SPI_INT2_EXTI_PIN_SOURCE EXTI_PinSource1 #define LIS302DL_SPI_INT2_EXTI_IRQn EXTI1_IRQn /******************************************************************************/ /*************************** START REGISTER MAPPING **************************/ /******************************************************************************/ /******************************************************************************* * WHO_AM_I Register: Device Identification Register * Read only register * Default value: 0x3B *******************************************************************************/ #define LIS302DL_WHO_AM_I_ADDR 0x0F /******************************************************************************* * CTRL_REG1 Register: Control Register 1 * Read Write register * Default value: 0x07 * 7 DR: Data Rate selection. * 0 - 100 Hz output data rate * 1 - 400 Hz output data rate * 6 PD: Power Down control. * 0 - power down mode * 1 - active mode * 5 FS: Full Scale selection. * 0 - Typical measurement range 2.3 * 1 - Typical measurement range 9.2 * 4:3 STP-STM Self Test Enable: * STP | STM | mode * ---------------------------- * 0 | 0 | Normal mode * 0 | 1 | Self Test M * 1 | 0 | Self Test P * 2 Zen: Z axis enable. * 0 - Z axis disabled * 1- Z axis enabled * 1 Yen: Y axis enable. * 0 - Y axis disabled * 1- Y axis enabled * 0 Xen: X axis enable. * 0 - X axis disabled * 1- X axis enabled ********************************************************************************/ #define LIS302DL_CTRL_REG1_ADDR 0x20 /******************************************************************************* * CTRL_REG2 Regsiter: Control Register 2 * Read Write register * Default value: 0x00 * 7 SIM: SPI Serial Interface Mode Selection. * 0 - 4 wire interface * 1 - 3 wire interface * 6 BOOT: Reboot memory content * 0 - normal mode * 1 - reboot memory content * 5 Reserved * 4 FDS: Filtered data selection. * 0 - internal filter bypassed * 1 - data from internal filter sent to output register * 3 HP FF_WU2: High pass filter enabled for FreeFall/WakeUp#2. * 0 - filter bypassed * 1 - filter enabled * 2 HP FF_WU1: High pass filter enabled for FreeFall/WakeUp#1. * 0 - filter bypassed * 1 - filter enabled * 1:0 HP coeff2-HP coeff1 High pass filter cut-off frequency (ft) configuration. * ft= ODR[hz]/6*HP coeff * HP coeff2 | HP coeff1 | HP coeff * ------------------------------------------- * 0 | 0 | 8 * 0 | 1 | 16 * 1 | 0 | 32 * 1 | 1 | 64 * HP coeff | ft[hz] | ft[hz] | * |ODR 100Hz | ODR 400Hz | * -------------------------------------------- * 00 | 2 | 8 | * 01 | 1 | 4 | * 10 | 0.5 | 2 | * 11 | 0.25 | 1 | *******************************************************************************/ #define LIS302DL_CTRL_REG2_ADDR 0x21 /******************************************************************************* * CTRL_REG3 Register: Interrupt Control Register * Read Write register * Default value: 0x00 * 7 IHL active: Interrupt active high/low. * 0 - active high * 1 - active low * 6 PP_OD: push-pull/open-drain. * 0 - push-pull * 1 - open-drain * 5:3 I2_CFG2 - I2_CFG0 Data signal on INT2 pad control bits * 2:0 I1_CFG2 - I1_CFG0 Data signal on INT1 pad control bits * I1(2)_CFG2 | I1(2)_CFG1 | I1(2)_CFG0 | INT1(2) Pad * ---------------------------------------------------------- * 0 | 0 | 0 | GND * 0 | 0 | 1 | FreeFall/WakeUp#1 * 0 | 1 | 0 | FreeFall/WakeUp#2 * 0 | 1 | 1 | FreeFall/WakeUp#1 or FreeFall/WakeUp#2 * 1 | 0 | 0 | Data ready * 1 | 1 | 1 | Click interrupt *******************************************************************************/ #define LIS302DL_CTRL_REG3_ADDR 0x22 /******************************************************************************* * HP_FILTER_RESET Register: Dummy register. Reading at this address zeroes * instantaneously the content of the internal high pass filter. If the high pass * filter is enabled all three axes are instantaneously set to 0g. * This allows to overcome the settling time of the high pass filter. * Read only register * Default value: Dummy *******************************************************************************/ #define LIS302DL_HP_FILTER_RESET_REG_ADDR 0x23 /******************************************************************************* * STATUS_REG Register: Status Register * Default value: 0x00 * 7 ZYXOR: X, Y and Z axis data overrun. * 0: no overrun has occurred * 1: new data has overwritten the previous one before it was read * 6 ZOR: Z axis data overrun. * 0: no overrun has occurred * 1: new data for Z-axis has overwritten the previous one before it was read * 5 yOR: y axis data overrun. * 0: no overrun has occurred * 1: new data for y-axis has overwritten the previous one before it was read * 4 XOR: X axis data overrun. * 0: no overrun has occurred * 1: new data for X-axis has overwritten the previous one before it was read * 3 ZYXDA: X, Y and Z axis new data available * 0: a new set of data is not yet available * 1: a new set of data is available * 2 ZDA: Z axis new data available. * 0: a new set of data is not yet available * 1: a new data for Z axis is available * 1 YDA: Y axis new data available * 0: a new set of data is not yet available * 1: a new data for Y axis is available * 0 XDA: X axis new data available * 0: a new set of data is not yet available * 1: a new data for X axis is available *******************************************************************************/ #define LIS302DL_STATUS_REG_ADDR 0x27 /******************************************************************************* * OUT_X Register: X-axis output Data * Read only register * Default value: output * 7:0 XD7-XD0: X-axis output Data *******************************************************************************/ #define LIS302DL_OUT_X_ADDR 0x29 /******************************************************************************* * OUT_Y Register: Y-axis output Data * Read only register * Default value: output * 7:0 YD7-YD0: Y-axis output Data *******************************************************************************/ #define LIS302DL_OUT_Y_ADDR 0x2B /******************************************************************************* * OUT_Z Register: Z-axis output Data * Read only register * Default value: output * 7:0 ZD7-ZD0: Z-axis output Data *******************************************************************************/ #define LIS302DL_OUT_Z_ADDR 0x2D /******************************************************************************* * FF_WW_CFG_1 Register: Configuration register for Interrupt 1 source. * Read write register * Default value: 0x00 * 7 AOI: AND/OR combination of Interrupt events. * 0: OR combination of interrupt events * 1: AND combination of interrupt events * 6 LIR: Latch/not latch interrupt request * 0: interrupt request not latched * 1: interrupt request latched * 5 ZHIE: Enable interrupt generation on Z high event. * 0: disable interrupt request * 1: enable interrupt request on measured accel. value higher than preset threshold * 4 ZLIE: Enable interrupt generation on Z low event. * 0: disable interrupt request * 1: enable interrupt request on measured accel. value lower than preset threshold * 3 YHIE: Enable interrupt generation on Y high event. * 0: disable interrupt request * 1: enable interrupt request on measured accel. value higher than preset threshold * 2 YLIE: Enable interrupt generation on Y low event. * 0: disable interrupt request * 1: enable interrupt request on measured accel. value lower than preset threshold * 1 XHIE: Enable interrupt generation on X high event. * 0: disable interrupt request * 1: enable interrupt request on measured accel. value higher than preset threshold * 0 XLIE: Enable interrupt generation on X low event. * 0: disable interrupt request * 1: enable interrupt request on measured accel. value lower than preset threshold *******************************************************************************/ #define LIS302DL_FF_WU_CFG1_REG_ADDR 0x30 /******************************************************************************* * FF_WU_SRC_1 Register: Interrupt 1 source register. * Reading at this address clears FF_WU_SRC_1 register and the FF, WU 1 interrupt * and allow the refreshment of data in the FF_WU_SRC_1 register if the latched option * was chosen. * Read only register * Default value: 0x00 * 7 Reserved * 6 IA: Interrupt active. * 0: no interrupt has been generated * 1: one or more interrupts have been generated * 5 ZH: Z high. * 0: no interrupt * 1: ZH event has occurred * 4 ZL: Z low. * 0: no interrupt * 1: ZL event has occurred * 3 YH: Y high. * 0: no interrupt * 1: YH event has occurred * 2 YL: Y low. * 0: no interrupt * 1: YL event has occurred * 1 YH: X high. * 0: no interrupt * 1: XH event has occurred * 0 YL: X low. * 0: no interrupt * 1: XL event has occurred *******************************************************************************/ #define LIS302DL_FF_WU_SRC1_REG_ADDR 0x31 /******************************************************************************* * FF_WU_THS_1 Register: Threshold register * Read Write register * Default value: 0x00 * 7 DCRM: Reset mode selection. * 0 - counter resetted * 1 - counter decremented * 6 THS6-THS0: Free-fall/wake-up threshold value. *******************************************************************************/ #define LIS302DL_FF_WU_THS1_REG_ADDR 0x32 /******************************************************************************* * FF_WU_DURATION_1 Register: duration Register * Read Write register * Default value: 0x00 * 7:0 D7-D0 Duration value. (Duration steps and maximum values depend on the ODR chosen) ******************************************************************************/ #define LIS302DL_FF_WU_DURATION1_REG_ADDR 0x33 /******************************************************************************* * FF_WW_CFG_2 Register: Configuration register for Interrupt 2 source. * Read write register * Default value: 0x00 * 7 AOI: AND/OR combination of Interrupt events. * 0: OR combination of interrupt events * 1: AND combination of interrupt events * 6 LIR: Latch/not latch interrupt request * 0: interrupt request not latched * 1: interrupt request latched * 5 ZHIE: Enable interrupt generation on Z high event. * 0: disable interrupt request * 1: enable interrupt request on measured accel. value higher than preset threshold * 4 ZLIE: Enable interrupt generation on Z low event. * 0: disable interrupt request * 1: enable interrupt request on measured accel. value lower than preset threshold * 3 YHIE: Enable interrupt generation on Y high event. * 0: disable interrupt request * 1: enable interrupt request on measured accel. value higher than preset threshold * 2 YLIE: Enable interrupt generation on Y low event. * 0: disable interrupt request * 1: enable interrupt request on measured accel. value lower than preset threshold * 1 XHIE: Enable interrupt generation on X high event. * 0: disable interrupt request * 1: enable interrupt request on measured accel. value higher than preset threshold * 0 XLIE: Enable interrupt generation on X low event. * 0: disable interrupt request * 1: enable interrupt request on measured accel. value lower than preset threshold *******************************************************************************/ #define LIS302DL_FF_WU_CFG2_REG_ADDR 0x34 /******************************************************************************* * FF_WU_SRC_2 Register: Interrupt 2 source register. * Reading at this address clears FF_WU_SRC_2 register and the FF, WU 2 interrupt * and allow the refreshment of data in the FF_WU_SRC_2 register if the latched option * was chosen. * Read only register * Default value: 0x00 * 7 Reserved * 6 IA: Interrupt active. * 0: no interrupt has been generated * 1: one or more interrupts have been generated * 5 ZH: Z high. * 0: no interrupt * 1: ZH event has occurred * 4 ZL: Z low. * 0: no interrupt * 1: ZL event has occurred * 3 YH: Y high. * 0: no interrupt * 1: YH event has occurred * 2 YL: Y low. * 0: no interrupt * 1: YL event has occurred * 1 YH: X high. * 0: no interrupt * 1: XH event has occurred * 0 YL: X low. * 0: no interrupt * 1: XL event has occurred *******************************************************************************/ #define LIS302DL_FF_WU_SRC2_REG_ADDR 0x35 /******************************************************************************* * FF_WU_THS_2 Register: Threshold register * Read Write register * Default value: 0x00 * 7 DCRM: Reset mode selection. * 0 - counter resetted * 1 - counter decremented * 6 THS6-THS0: Free-fall/wake-up threshold value. *******************************************************************************/ #define LIS302DL_FF_WU_THS2_REG_ADDR 0x36 /******************************************************************************* * FF_WU_DURATION_2 Register: duration Register * Read Write register * Default value: 0x00 * 7:0 D7-D0 Duration value. (Duration steps and maximum values depend on the ODR chosen) ******************************************************************************/ #define LIS302DL_FF_WU_DURATION2_REG_ADDR 0x37 /****************************************************************************** * CLICK_CFG Register: click Register * Read Write register * Default value: 0x00 * 7 Reserved * 6 LIR: Latch Interrupt request. * 0: interrupt request not latched * 1: interrupt request latched * 5 Double_Z: Enable interrupt generation on double click event on Z axis. * 0: disable interrupt request * 1: enable interrupt request * 4 Single_Z: Enable interrupt generation on single click event on Z axis. * 0: disable interrupt request * 1: enable interrupt request * 3 Double_Y: Enable interrupt generation on double click event on Y axis. * 0: disable interrupt request * 1: enable interrupt request * 2 Single_Y: Enable interrupt generation on single click event on Y axis. * 0: disable interrupt request * 1: enable interrupt request * 1 Double_X: Enable interrupt generation on double click event on X axis. * 0: disable interrupt request * 1: enable interrupt request * 0 Single_y: Enable interrupt generation on single click event on X axis. * 0: disable interrupt request * 1: enable interrupt request ******************************************************************************/ #define LIS302DL_CLICK_CFG_REG_ADDR 0x38 /****************************************************************************** * CLICK_SRC Register: click status Register * Read only register * Default value: 0x00 * 7 Reserved * 6 IA: Interrupt active. * 0: no interrupt has been generated * 1: one or more interrupts have been generated * 5 Double_Z: Double click on Z axis event. * 0: no interrupt * 1: Double Z event has occurred * 4 Single_Z: Z low. * 0: no interrupt * 1: Single Z event has occurred * 3 Double_Y: Y high. * 0: no interrupt * 1: Double Y event has occurred * 2 Single_Y: Y low. * 0: no interrupt * 1: Single Y event has occurred * 1 Double_X: X high. * 0: no interrupt * 1: Double X event has occurred * 0 Single_X: X low. * 0: no interrupt * 1: Single X event has occurred *******************************************************************************/ #define LIS302DL_CLICK_SRC_REG_ADDR 0x39 /******************************************************************************* * CLICK_THSY_X Register: Click threshold Y and X register * Read Write register * Default value: 0x00 * 7:4 THSy3-THSy0: Click threshold on Y axis, step 0.5g * 3:0 THSx3-THSx0: Click threshold on X axis, step 0.5g *******************************************************************************/ #define LIS302DL_CLICK_THSY_X_REG_ADDR 0x3B /******************************************************************************* * CLICK_THSZ Register: Click threshold Z register * Read Write register * Default value: 0x00 * 7:4 Reserved * 3:0 THSz3-THSz0: Click threshold on Z axis, step 0.5g *******************************************************************************/ #define LIS302DL_CLICK_THSZ_REG_ADDR 0x3C /******************************************************************************* * CLICK_TimeLimit Register: Time Limit register * Read Write register * Default value: 0x00 * 7:0 Dur7-Dur0: Time Limit value, step 0.5g *******************************************************************************/ #define LIS302DL_CLICK_TIMELIMIT_REG_ADDR 0x3D /******************************************************************************* * CLICK_Latency Register: Latency register * Read Write register * Default value: 0x00 * 7:0 Lat7-Lat0: Latency value, step 1msec *******************************************************************************/ #define LIS302DL_CLICK_LATENCY_REG_ADDR 0x3E /******************************************************************************* * CLICK_Window Register: Window register * Read Write register * Default value: 0x00 * 7:0 Win7-Win0: Window value, step 1msec *******************************************************************************/ #define LIS302DL_CLICK_WINDOW_REG_ADDR 0x3F /******************************************************************************/ /**************************** END REGISTER MAPPING ***************************/ /******************************************************************************/ #define LIS302DL_SENSITIVITY_2_3G 18 /* 18 mg/digit*/ #define LIS302DL_SENSITIVITY_9_2G 72 /* 72 mg/digit*/ /** @defgroup Data_Rate_selection * @{ */ #define LIS302DL_DATARATE_100 ((uint8_t)0x00) #define LIS302DL_DATARATE_400 ((uint8_t)0x80) /** * @} */ /** @defgroup Power_Mode_selection * @{ */ #define LIS302DL_LOWPOWERMODE_POWERDOWN ((uint8_t)0x00) #define LIS302DL_LOWPOWERMODE_ACTIVE ((uint8_t)0x40) /** * @} */ /** @defgroup Full_Scale_selection * @{ */ #define LIS302DL_FULLSCALE_2_3 ((uint8_t)0x00) #define LIS302DL_FULLSCALE_9_2 ((uint8_t)0x20) /** * @} */ /** @defgroup Self_Test_selection * @{ */ #define LIS302DL_SELFTEST_NORMAL ((uint8_t)0x00) #define LIS302DL_SELFTEST_P ((uint8_t)0x10) #define LIS302DL_SELFTEST_M ((uint8_t)0x08) /** * @} */ /** @defgroup Direction_XYZ_selection * @{ */ #define LIS302DL_X_ENABLE ((uint8_t)0x01) #define LIS302DL_Y_ENABLE ((uint8_t)0x02) #define LIS302DL_Z_ENABLE ((uint8_t)0x04) #define LIS302DL_XYZ_ENABLE ((uint8_t)0x07) /** * @} */ /** @defgroup SPI_Serial_Interface_Mode_selection * @{ */ #define LIS302DL_SERIALINTERFACE_4WIRE ((uint8_t)0x00) #define LIS302DL_SERIALINTERFACE_3WIRE ((uint8_t)0x80) /** * @} */ /** @defgroup Boot_Mode_selection * @{ */ #define LIS302DL_BOOT_NORMALMODE ((uint8_t)0x00) #define LIS302DL_BOOT_REBOOTMEMORY ((uint8_t)0x40) /** * @} */ /** @defgroup Filtered_Data_Selection_Mode_selection * @{ */ #define LIS302DL_FILTEREDDATASELECTION_BYPASSED ((uint8_t)0x00) #define LIS302DL_FILTEREDDATASELECTION_OUTPUTREGISTER ((uint8_t)0x20) /** * @} */ /** @defgroup High_Pass_Filter_Interrupt_selection * @{ */ #define LIS302DL_HIGHPASSFILTERINTERRUPT_OFF ((uint8_t)0x00) #define LIS302DL_HIGHPASSFILTERINTERRUPT_1 ((uint8_t)0x04) #define LIS302DL_HIGHPASSFILTERINTERRUPT_2 ((uint8_t)0x08) #define LIS302DL_HIGHPASSFILTERINTERRUPT_1_2 ((uint8_t)0x0C) /** * @} */ /** @defgroup High_Pass_Filter_selection * @{ */ #define LIS302DL_HIGHPASSFILTER_LEVEL_0 ((uint8_t)0x00) #define LIS302DL_HIGHPASSFILTER_LEVEL_1 ((uint8_t)0x01) #define LIS302DL_HIGHPASSFILTER_LEVEL_2 ((uint8_t)0x02) #define LIS302DL_HIGHPASSFILTER_LEVEL_3 ((uint8_t)0x03) /** * @} */ /** @defgroup latch_Interrupt_Request_selection * @{ */ #define LIS302DL_INTERRUPTREQUEST_NOTLATCHED ((uint8_t)0x00) #define LIS302DL_INTERRUPTREQUEST_LATCHED ((uint8_t)0x40) /** * @} */ /** @defgroup Click_Interrupt_XYZ_selection * @{ */ #define LIS302DL_CLICKINTERRUPT_XYZ_DISABLE ((uint8_t)0x00) #define LIS302DL_CLICKINTERRUPT_X_ENABLE ((uint8_t)0x01) #define LIS302DL_CLICKINTERRUPT_Y_ENABLE ((uint8_t)0x04) #define LIS302DL_CLICKINTERRUPT_Z_ENABLE ((uint8_t)0x10) #define LIS302DL_CLICKINTERRUPT_XYZ_ENABLE ((uint8_t)0x15) /** * @} */ /** @defgroup Double_Click_Interrupt_XYZ_selection * @{ */ #define LIS302DL_DOUBLECLICKINTERRUPT_XYZ_DISABLE ((uint8_t)0x00) #define LIS302DL_DOUBLECLICKINTERRUPT_X_ENABLE ((uint8_t)0x02) #define LIS302DL_DOUBLECLICKINTERRUPT_Y_ENABLE ((uint8_t)0x08) #define LIS302DL_DOUBLECLICKINTERRUPT_Z_ENABLE ((uint8_t)0x20) #define LIS302DL_DOUBLECLICKINTERRUPT_XYZ_ENABLE ((uint8_t)0x2A) /** * @} */ /** * @} */ /** @defgroup STM32F4_DISCOVERY_LIS302DL_Exported_Macros * @{ */ #define LIS302DL_CS_LOW() GPIO_ResetBits(LIS302DL_SPI_CS_GPIO_PORT, LIS302DL_SPI_CS_PIN) #define LIS302DL_CS_HIGH() GPIO_SetBits(LIS302DL_SPI_CS_GPIO_PORT, LIS302DL_SPI_CS_PIN) /** * @} */ /** @defgroup STM32F4_DISCOVERY_LIS302DL_Exported_Functions * @{ */ void LIS302DL_Init(LIS302DL_InitTypeDef *LIS302DL_InitStruct); void LIS302DL_InterruptConfig(LIS302DL_InterruptConfigTypeDef *LIS302DL_InterruptConfigStruct); void LIS302DL_FilterConfig(LIS302DL_FilterConfigTypeDef *LIS302DL_FilterConfigStruct); void LIS302DL_LowpowerCmd(uint8_t LowPowerMode); void LIS302DL_FullScaleCmd(uint8_t FS_value); void LIS302DL_DataRateCmd(uint8_t DataRateValue); void LIS302DL_RebootCmd(void); void LIS302DL_ReadACC(int32_t* out); void LIS302DL_Write(uint8_t* pBuffer, uint8_t WriteAddr, uint16_t NumByteToWrite); void LIS302DL_Read(uint8_t* pBuffer, uint8_t ReadAddr, uint16_t NumByteToRead); /* USER Callbacks: This is function for which prototype only is declared in MEMS accelerometre driver and that should be implemented into user applicaiton. */ /* LIS302DL_TIMEOUT_UserCallback() function is called whenever a timeout condition occure during communication (waiting transmit data register empty flag(TXE) or waiting receive data register is not empty flag (RXNE)). You can use the default timeout callback implementation by uncommenting the define USE_DEFAULT_TIMEOUT_CALLBACK in stm32f4_discovery_lis302dl.h file. Typically the user implementation of this callback should reset MEMS peripheral and re-initialize communication or in worst case reset all the application. */ uint32_t LIS302DL_TIMEOUT_UserCallback(void); #ifdef __cplusplus } #endif #endif /* __STM32F4_DISCOVERY_LIS302DL_H */ /** * @} */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/spi.elf.launch ================================================ ================================================ FILE: figure-simulator-discovery/src/main.c ================================================ /** ****************************************************************************** * @file main.c * @author MCD Application Team * @version V1.0.0 * @date 19-September-2011 * @brief Main program body ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * *

© COPYRIGHT 2011 STMicroelectronics

****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ //#include "main.h" #include "stm32f4_discovery.h" //#include "stm32f4xx_it.c" uint8_t flag; //#include /** @addtogroup STM32F4-Discovery_Demo * @{ */ int i; /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ //#define CLK GPIO_Pin_11 //#define ADDRESS GPIO_Pin_10 //#define E GPIO_Pin_9 EXTI_InitTypeDef EXTI_InitStructure; /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ //uint32_t a = 0; //int i; int index; int started = 0; /* Private function prototypes -----------------------------------------------*/ GPIO_InitTypeDef GPIO_InitStructure; /* Private functions ---------------------------------------------------------*/ void EXTILine0_Config(void) { GPIO_InitTypeDef GPIO_InitStructure; NVIC_InitTypeDef NVIC_InitStructure; /* Enable GPIOA clock */ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); /* Enable SYSCFG clock */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); /* Configure PA0 pin as input floating */ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; GPIO_Init(GPIOA, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1; GPIO_Init(GPIOA, &GPIO_InitStructure); /* Connect EXTI Line0 to PA0 pin */ SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOA, EXTI_PinSource0); /* Configure EXTI Line0 */ EXTI_InitStructure.EXTI_Line = EXTI_Line0; EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; EXTI_InitStructure.EXTI_LineCmd = ENABLE; EXTI_Init(&EXTI_InitStructure); /* Enable and set EXTI Line0 Interrupt to the lowest priority */ NVIC_InitStructure.NVIC_IRQChannel = EXTI0_IRQn; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x01; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x01; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOA, EXTI_PinSource1); /* Configure EXTI Line0 */ EXTI_InitStructure.EXTI_Line = EXTI_Line1; EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; EXTI_InitStructure.EXTI_LineCmd = ENABLE; EXTI_Init(&EXTI_InitStructure); /* Enable and set EXTI Line0 Interrupt to the lowest priority */ NVIC_InitStructure.NVIC_IRQChannel = EXTI1_IRQn; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x02; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x01; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); } int loops = 0; int hit = 0; int q; int as[2000]; int read = 1; uint32_t a = 0; int acount = 0; uint8_t val; uint8_t c; uint8_t *vs[8]; uint8_t v1[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0x29, 0xc0, 0xff, 0xca, 0x9f, 0x28, 0xc0, 0xff, 0xca, 0xa7, 0x67, 0xc0, 0xff, 0xda, 0xa8, 0xa7, 0xc0, 0xff, 0xda, 0xaa, 0xa3, 0xc0, 0xff, 0x2a, 0xaa, 0x9f, 0xc0, 0xff, 0x69, 0xaa, 0x8f, 0xc0, 0xff, 0x65, 0xaa, 0x8f, 0xc0, 0xfc, 0xa4, 0xaa, 0x7f, 0xc0, 0xfd, 0xa0, 0xaa, 0x7f, 0xc0, 0xf2, 0xa3, 0x6a, 0x7f, 0xc0, 0xf2, 0x9f, 0x6a, 0x3f, 0xc0, 0xfa, 0x8f, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0}; uint8_t v2[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0x6a, 0x7f, 0xc0, 0xff, 0xfd, 0xaa, 0x3f, 0xc0, 0xff, 0xf2, 0xaa, 0x3f, 0xc0, 0xff, 0xf6, 0xa9, 0xff, 0xc0, 0xff, 0xda, 0xa9, 0xff, 0xc0, 0xff, 0x2a, 0xa9, 0xff, 0xc0, 0xff, 0x6a, 0xa8, 0xff, 0xc0, 0xfc, 0xa4, 0xa8, 0xff, 0xc0, 0xfd, 0xa0, 0xa7, 0xff, 0xc0, 0xf2, 0x91, 0xa7, 0xff, 0xc0, 0xfa, 0x82, 0xa7, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0}; uint8_t v3[] = { 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfa, 0xaa, 0xab, 0xc0, 0xff, 0xfa, 0xaa, 0xaf, 0xc0, 0xff, 0xfa, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xea, 0xbf, 0xff, 0xc0, 0xff, 0xea, 0xff, 0xff, 0xc0, 0xff, 0xea, 0xff, 0xff, 0xc0, 0xff, 0xaa, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0}; uint8_t v4[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xaa, 0xff, 0xc0, 0xff, 0xff, 0xab, 0xff, 0xc0, 0xff, 0xfe, 0xab, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xff, 0xff, 0xc0, 0xff, 0xea, 0xff, 0xff, 0xc0, 0xff, 0xeb, 0xff, 0xff, 0xc0, 0xff, 0xeb, 0xff, 0xff, 0xc0, 0xff, 0xab, 0xea, 0xff, 0xc0, 0xff, 0xaa, 0xaa, 0xff, 0xc0, 0xff, 0xaa, 0xaa, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0 }; uint8_t v5[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xea, 0xff, 0xc0, 0xff, 0xff, 0xea, 0xff, 0xc0, 0xff, 0xff, 0xeb, 0xff, 0xc0, 0xff, 0xff, 0xeb, 0xff, 0xc0, 0xff, 0xff, 0xab, 0xff, 0xc0, 0xff, 0xff, 0xaf, 0xff, 0xc0, 0xff, 0xff, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xbf, 0xff, 0xc0, 0xff, 0xfe, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xfa, 0xbf, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0}; uint8_t v6[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xaa, 0xaa, 0xc0, 0xff, 0xff, 0xaa, 0xaa, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfe, 0xaf, 0xff, 0xc0, 0xff, 0xfa, 0xaa, 0xff, 0xc0, 0xff, 0xfa, 0xab, 0xff, 0xc0, 0xff, 0xfa, 0xff, 0xff, 0xc0, 0xff, 0xea, 0xff, 0xff, 0xc0, 0xff, 0xea, 0xff, 0xff, 0xc0, 0xff, 0xea, 0xab, 0xff, 0xc0, 0xff, 0xaa, 0xab, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0}; uint8_t v7[] = {0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xeb, 0xff, 0xc0, 0xff, 0xff, 0xab, 0xff, 0xc0, 0xff, 0xfe, 0xab, 0xff, 0xc0, 0xfe, 0xaa, 0xaa, 0xab, 0xc0, 0xff, 0xaa, 0xaa, 0xbf, 0xc0, 0xff, 0xea, 0xab, 0xff, 0xc0, 0xff, 0xea, 0xab, 0xff, 0xc0, 0xff, 0xaa, 0xab, 0xff, 0xc0, 0xff, 0xaf, 0xab, 0xff, 0xc0, 0xfe, 0xff, 0xeb, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0}; uint8_t v[] = { 0x0a, 0xaa, 0x55, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0-f 0x00, 0xaa, 0x55, 0x04, 0x0d, 0x04, 0x00, 0x00, 0x11, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //10-f // 0x00, 0xaa, 0x55, 0x04, 0x0d, 0x04, 0x04, 0x01, 0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 0x40, 0x00, 0x00, 0x55, 0x55, 0x55, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0x40, 0x00, 0x00, 0xc4, 0x00, 0x00, 0xdc, 0x00, 0x00, 0x0f, 0x01, 0x00, 0x91, 0x01, 0x00, 0x0d, //20 0x02, 0x00, 0x89, 0x02, 0x00, 0xd1, 0x02, 0x00, 0x1f, 0x06, 0x00, 0x67, 0x0f, 0x00, 0x67, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //40 0xf0, 0x03, 0x00, 0xf0, 0x03, 0x00, 0xf0, 0x03, 0x00, 0xf0, 0x03, 0x00, 0xd9, 0x13, 0x00, 0x3f, 0x14, 0x00, 0xa5, 0x14, 0x00, 0x0b, 0x15, 0x00, 0x71, 0x15, 0x00, 0xd7, 0x15, 0x00, 0x3d, 0x16, 0x00, 0xa3, 0x16, 0x00, 0x09, 0x17, 0x00, 0x6f, 0x17, 0x00, 0xd5, 0x17, 0x00, 0x3b, 0x18, 0x00, 0xa1, 0x18, 0x00, 0x07, 0x19, 0x00, 0x6d, 0x19, 0x00, 0xd3, 0x19, 0x00, 0x39, 0x1a, 0x00, 0x9f, //80 0x1a, 0x00, 0x05, 0x1b, 0x00, 0x6b, 0x1b, 0x00, 0xd1, 0x1b, 0x00, 0x37, 0x1c, 0x00, 0x9d, 0x1c, //90 0x00, 0x13, 0x1e, 0x00, 0x72, 0x05, 0x00, 0x72, 0x05, 0x00, 0x75, 0x22, 0x00, 0xeb, 0x23, 0x00, 0x61, 0x25, 0x00, 0xd7, 0x26, 0x00, 0xf4, 0x06, 0x00, 0xf4, 0x06, 0x00, 0x89, 0x29, 0x00, 0x64, //b0 0x2a, 0x00, 0xa2, 0x2a, 0x00, 0xe0, 0x2a, 0x00, 0x1e, 0x2b, 0x00, 0x5c, 0x2b, 0x00, 0xce, 0x00, //c0 0x00, 0xce, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x44, 0x12, 0x34, 0x30, 0x1f,// max:0x50, 0x20, //d0 0x2a, 0xaa, 0xaa, 0xaa, 0xa8, 0x01, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x2a, 0xaa, 0xaa, 0xaa, //e0 NATALIE PIC for bg 0xa8, 0x00, 0x6a, 0xaa, 0xaa, 0xaa, 0xa9, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0xa9, 0x00, 0x2a, 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0xa9, 0x00, 0x0a, 0x6a, 0xa8, 0x00, 0x00, 0x00, //100 0x2a, 0xaa, 0xaa, 0xaa, 0xa9, 0x00, 0x00, 0x2a, 0xaa, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0xa8, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xa4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6a, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6a, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0x90, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0xaa, 0xaa, 0xa0, 0x00, //1a0 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x01, 0xaa, 0xaa, 0xa4, 0x00, 0x00, 0x00, 0x1a, 0xa0, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0xa8, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x6a, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1a, 0x2a, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0xa4, 0x00, 0x00, 0x2a, 0x2a, 0xaa, 0xaa, 0xa0, //200 0x04, 0x2a, 0xaa, 0xaa, 0xa9, 0x00, 0x00, 0x6a, 0x2a, 0xaa, 0xaa, 0xa4, 0x0a, 0xaa, 0xaa, 0xa9, 0x00, 0x00, 0x00, 0xaa, 0x2a, 0xaa, 0xaa, 0xa8, 0x00, 0x1a, 0xaa, 0x80, 0x00, 0x00, 0x01, 0xaa, 0x1a, 0xaa, 0xaa, 0xaa, 0x00, 0x0a, 0xaa, 0x80, 0x00, 0x00, 0x02, 0xaa, 0x0a, 0xaa, 0xaa, 0xaa, 0x80, 0x0a, 0xaa, 0x90, 0x00, 0x00, 0x06, 0xaa, 0x0a, 0xaa, 0xaa, 0xaa, 0x90, 0x01, 0xaa, 0xa4, 0x00, 0x00, 0x1a, 0xaa, 0x8a, 0xaa, 0x86, 0xa8, 0x24, 0x00, 0xaa, 0x50, 0x00, 0x00, 0x6a, 0xaa, //250 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //260 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf4, 0x06, 0x00, 0xf4, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, //300 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //350 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //3f0 0x30, 0x1f, 0x2a, 0xaa, 0xaa, 0xaa, 0xa8, 0x01, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x2a, 0xaa, 0xaa, 0xaa, //400 NATALIE PIC for SPRITE 0xa8, 0x00, 0x6a, 0xaa, 0xaa, 0xaa, 0xa9, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0xa9, 0x00, 0x2a, 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0xa9, 0x00, 0x0a, 0x6a, 0xa8, 0x00, 0x00, 0x00, //422 0x2a, 0xaa, 0xaa, 0xaa, 0xa9, 0x00, 0x00, 0x2a, 0xaa, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0xa8, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xa4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6a, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6a, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x10, //4a2 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0x90, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0xaa, 0xaa, 0xa0, 0x00, //3c2 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x01, 0xaa, 0xaa, 0xa4, 0x00, 0x00, 0x00, 0x1a, 0xa0, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0xa8, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x01, 0x00, 0x00, //502 0x00, 0x00, 0x00, 0x0a, 0x6a, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1a, 0x2a, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0xa4, 0x00, 0x00, 0x2a, 0x2a, 0xaa, 0xaa, 0xa0, //522 0x04, 0x2a, 0xaa, 0xaa, 0xa9, 0x00, 0x00, 0x6a, 0x2a, 0xaa, 0xaa, 0xa4, 0x0a, 0xaa, 0xaa, 0xa9, 0x00, 0x00, 0x00, 0xaa, 0x2a, 0xaa, 0xaa, 0xa8, 0x00, 0x1a, 0xaa, 0x80, 0x00, 0x00, 0x01, 0xaa, 0x1a, 0xaa, 0xaa, 0xaa, 0x00, 0x0a, 0xaa, 0x80, 0x00, 0x00, 0x02, 0xaa, 0x0a, 0xaa, 0xaa, 0xaa, 0x80, 0x0a, 0xaa, 0x90, 0x00, 0x00, 0x06, 0xaa, 0x0a, 0xaa, 0xaa, 0xaa, 0x90, 0x01, 0xaa, 0xa4, 0x00, 0x00, 0x1a, 0xaa, 0x8a, 0xaa, 0x86, 0xa8, 0x24, 0x00, 0xaa, 0x50, 0x00, 0x00, 0x6a, 0xaa, //572 0x30, 0x1f, 0x2a, 0xaa, 0xaa, 0xaa, 0xa8, 0x01, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x2a, 0xaa, 0xaa, 0xaa, //582 NATALIE PIC GAME 0xa8, 0x00, 0x6a, 0xaa, 0xaa, 0xaa, 0xa9, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0xa9, 0x00, 0x2a, 0xaa,//594 0xaa, 0xa0, 0x00, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0xa9, 0x00, 0x0a, 0x6a, 0xa8, 0x00, 0x00, 0x00, //5a4 0x2a, 0xaa, 0xaa, 0xaa, 0xa9, 0x00, 0x00, 0x2a, 0xaa, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0xa8, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00,//5c4 0x00, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xa4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6a, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6a, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //604 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x10, // 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0x90, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0xaa, 0xaa, 0xa0, 0x00, // 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x01, 0xaa, 0xaa, 0xa4, 0x00, 0x00, 0x00, 0x1a, 0xa0, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0xa8, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x6a, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1a, 0x2a, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0xa4, 0x00, 0x00, 0x2a, 0x2a, 0xaa, 0xaa, 0xa0, //6a4 0x04, 0x2a, 0xaa, 0xaa, 0xa9, 0x00, 0x00, 0x6a, 0x2a, 0xaa, 0xaa, 0xa4, 0x0a, 0xaa, 0xaa, 0xa9, 0x00, 0x00, 0x00, 0xaa, 0x2a, 0xaa, 0xaa, 0xa8, 0x00, 0x1a, 0xaa, 0x80, 0x00, 0x00, 0x01, 0xaa,// 0x1a, 0xaa, 0xaa, 0xaa, 0x00, 0x0a, 0xaa, 0x80, 0x00, 0x00, 0x02, 0xaa, 0x0a, 0xaa, 0xaa, 0xaa, 0x80, 0x0a, 0xaa, 0x90, 0x00, 0x00, 0x06, 0xaa, 0x0a, 0xaa, 0xaa, 0xaa, 0x90, 0x01, 0xaa, 0xa4, 0x00, 0x00, 0x1a, 0xaa, 0x8a, 0xaa, 0x86, 0xa8, 0x24, 0x00, 0xaa, 0x50, 0x00, 0x00, 0x6a, 0xaa, // 6f4 0x30, 0x1f, 0x2a, 0xaa, 0xaa, 0xaa, 0xa8, 0x01, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x2a, 0xaa, 0xaa, 0xaa, //704 GAME TITLES 0xa8, 0x00, 0x6a, 0xaa, 0xaa, 0xaa, 0xa9, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0xa9, 0x00, 0x2a, 0xaa,//716 0xaa, 0xa0, 0x00, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0xa9, 0x00, 0x0a, 0x6a, 0xa8, 0x00, 0x00, 0x00, // 0x2a, 0xaa, 0xaa, 0xaa, 0xa9, 0x00, 0x00, 0x2a, 0xaa, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0xa8, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00,//746 0x00, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xa4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6a, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6a, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //604 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x10, // 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0x90, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0xaa, 0xaa, 0xa0, 0x00, // 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x01, 0xaa, 0xaa, 0xa4, 0x00, 0x00, 0x00, 0x1a, 0xa0, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0xa8, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x6a, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1a, 0x2a, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x00, 0x00, 0xa4, 0x00, 0x00, 0x2a, 0x2a, 0xaa, 0xaa, 0xa0, //6a4 0x04, 0x2a, 0xaa, 0xaa, 0xa9, 0x00, 0x00, 0x6a, 0x2a, 0xaa, 0xaa, 0xa4, 0x0a, 0xaa, 0xaa, 0xa9, 0x00, 0x00, 0x00, 0xaa, 0x2a, 0xaa, 0xaa, 0xa8, 0x00, 0x1a, 0xaa, 0x80, 0x00, 0x00, 0x01, 0xaa,// 0x1a, 0xaa, 0xaa, 0xaa, 0x00, 0x0a, 0xaa, 0x80, 0x00, 0x00, 0x02, 0xaa, 0x0a, 0xaa, 0xaa, 0xaa, 0x80, 0x0a, 0xaa, 0x90, 0x00, 0x00, 0x06, 0xaa, 0x0a, 0xaa, 0xaa, 0xaa, 0x90, 0x01, 0xaa, 0xa4, 0x00, 0x00, 0x1a, 0xaa, 0x8a, 0xaa, 0x86, 0xa8, 0x24, 0x00, 0xaa, 0x50, 0x00, 0x00, 0x6a, 0xaa, // 6f4 // 0x00, 0xcf, 0xff, 0x00, 0x00, 0x00, 0x00, 0xcf, 0xff, 0x00, 0x00, 0x00, 0x00, // 0xcf, 0xff, 0x00, 0x00, 0xc, 0xff, 0xff, 0xff, 0x00, 0x00, 0xff, 0xff, // 0xff, 0xff, 0x00, 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, //0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, // 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, // 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0x00, 0x00, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFA, 0xAA, 0xAB, 0xC0, 0xFF, 0xE5, 0x55, 0x5A, 0xC0, 0x00, 0xE5, 0x55, 0x5A, 0xC0, 0xFF, 0x95, 0x55, 0x66, 0xC0, 0xFF, 0xAA, 0xAA, 0xA6, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x8A, 0x28, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x8A, 0x28, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0xAA, 0xAA, 0xAB, 0xC0, 0x11, 0x15, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0x00, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFA, 0xAA, 0xAB, 0xC0, 0xFF, 0xE5, 0x55, 0x5A, 0xC0, 0xFF, 0xE5, 0x55, 0x5A, 0xC0, 0xFF, 0x95, 0x55, 0x66, 0xC0, 0xFF, 0xAA, 0xAA, 0xA6, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x8A, 0x28, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x8A, 0x28, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0x80, 0x00, 0x26, 0xC0, 0xFF, 0xAA, 0xAA, 0xAB, 0xC0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};// 0x70, 0x2c, 0x00, 0x82, 0x2c, 0x00, 0x90, 0x2c, 0x00, 0x9e, 0x2c, 0x00, 0xb0, 0x2c, 0x00, 0xc2, 0x2c, 0x00, 0xd4, 0x2c, 0x00, 0xe6, 0x2c, 0x00, 0xe9, 0x2c, 0x00, 0x1b, 0x2d, 0x00, 0x4d, 0x2d, 0x00, 0x7f, 0x2d, 0x00, 0xb1, 0x2d, 0x00, 0xe3, 0x2d, 0x00, 0x15, 0x2e, 0x00, 0x27, 0x2e, 0x00, 0x39, 0x2e, 0x00, 0x4b, 0x2e, 0x00, 0x6c, 0x2e, 0x00, 0x73, 0x2e, 0x00, 0xb5, 0x2e, 0x00, 0xf7, 0x2e, 0x00, 0x21, 0x2f, 0x00, 0x5f, 0x2f, 0x00, 0xc1, 0x2f, 0x00, 0x02, 0x00, 0x06, 0x03, 0x04, 0x09, 0x0a, 0x05, 0x08, 0x07, 0x00, 0x00, 0x58, 0x00, 0x00, 0x32, 0x00, 0x00, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x10, 0x00, 0x00, 0x08, 0x00, 0x00, 0x50, 0x04, 0x00, 0x30, 0x02, 0x00, 0x20, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00, 0x50, 0x08, 0x00, 0x50, 0x11, 0x00, 0x00, 0x00, 0x28, 0x00, 0x40, 0x15, 0x00, 0x60, 0x12, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x45, 0x00, 0x00, 0x35, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x22, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00, 0x22, 0x00, 0x00, 0x13, 0x00, 0x01, 0x00, 0x02, 0x00, 0x50, 0x01, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x04, 0xff, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x02, 0xff, 0x01, 0x01, 0x00, 0x1e, 0x01, 0x00, 0x03, 0xff, 0x01, 0x01, 0x00, 0x2d, 0x01, 0x00, 0x04, 0xfe, 0x01, 0x01, 0x00, 0x3c, 0x01, 0x00, 0x05, 0xfe, 0x01, 0x01, 0x00, 0x4b, 0x02, 0x00, 0x06, 0xfe, 0x02, 0x02, 0x00, 0x5a, 0x02, 0x00, 0x07, 0xfd, 0x02, 0x02, 0x00, 0x63, 0x02, 0x00, 0x08, 0xfd, 0x02, 0x02, 0x00, 0x64, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0x00, 0x02, 0x04, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x02, 0xff, 0x01, 0x01, 0x00, 0x0f, 0x01, 0x00, 0x03, 0xff, 0x01, 0x01, 0x00, 0x19, 0x01, 0x00, 0x04, 0xfe, 0x01, 0x01, 0x00, 0x23, 0x01, 0x00, 0x05, 0xfe, 0x01, 0x02, 0x00, 0x2d, 0x02, 0x00, 0x06, 0xfe, 0x02, 0x02, 0x00, 0x37, 0x02, 0x00, 0x07, 0xfd, 0x02, 0x02, 0x00, 0x40, 0x02, 0x00, 0x08, 0xfd, 0x02, 0x02, 0x00, 0x41, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xc4, 0x2f, 0x00, 0xff, 0xff, 0xff, 0x06, 0x30, 0x00, 0x48, 0x30, 0x00, 0x8a, 0x30, 0x00, 0xcc, 0x30, 0x00, 0x0e, 0x31, 0x00, 0x50, 0x31, 0x00, 0x92, 0x31, 0x00, 0xd4, 0x31, 0x00, 0x16, 0x32, 0x00, 0xff, 0xff, 0xff, 0x58, 0x32, 0x00, 0xff, 0xff, 0xff, 0xba, 0x32, 0x00, 0x1c, 0x33, 0x00, 0x7e, 0x33, 0x00, 0xe0, 0x33, 0x00, 0x42, 0x34, 0x00, 0xa4, 0x34, 0x00, 0x06, 0x35, 0x00, 0x68, 0x35, 0x00, 0xca, 0x35, 0x00, 0xff, 0xff, 0xff, 0x2c, 0x36, 0x00, 0x3e, 0x36, 0x00, 0x80, 0x36, 0x00, 0xc2, 0x36, 0x00, 0x04, 0x37, 0x00, 0x46, 0x37, 0x00, 0x88, 0x37, 0x00, 0xca, 0x37, 0x00, 0x24, 0x38, 0x00, 0x9d, 0x38, 0x00, 0xf9, 0x38, 0x00, 0x7d, 0x39, 0x00, 0xd7, 0x39, 0x00, 0x50, 0x3a, 0x00, 0xac, 0x3a, 0x00, 0x30, 0x3b, 0x00, 0x72, 0x3b, 0x00, 0xb4, 0x3b, 0x00, 0xf6, 0x3b, 0x00, 0x38, 0x3c, 0x00, 0x7a, 0x3c, 0x00, 0xbc, 0x3c, 0x00, 0xfe, 0x3c, 0x00, 0x40, 0x3d, 0x00, 0x3a, 0x3e, 0x00, 0x34, 0x3f, 0x00, 0x2e, 0x40, 0x00, 0x28, 0x41, 0x00, 0x22, 0x42, 0x00, 0x98, 0x43, 0x00, 0xea, 0x43, 0x00, 0x3c, 0x44, 0x00, 0x8e, 0x44, 0x00, 0xe0, 0x44, 0x00, 0x32, 0x45, 0x00, 0x84, 0x45, 0x00, 0x7e, 0x46, 0x00, 0x78, 0x47, 0x00, 0xba, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0x76, 0x48, 0x00, 0xf0, 0x48, 0x00, 0x6a, 0x49, 0x00, 0xe4, 0x49, 0x00, 0x5e, 0x4a, 0x00, 0xd8, 0x4a, 0x00, 0x52, 0x4b, 0x00, 0xcc, 0x4b, 0x00, 0x46, 0x4c, 0x00, 0xc0, 0x4c, 0x00, 0x3a, 0x4d, 0x00, 0xb4, 0x4d, 0x00, 0x2e, 0x4e, 0x00, 0xa8, 0x4e, 0x00, 0x22, 0x4f, 0x00, 0x9c, 0x4f, 0x00, 0x16, 0x50, 0x00, 0x90, 0x50, 0x00, 0x0a, 0x51, 0x00, 0x84, 0x51, 0x00, 0xfe, 0x51, 0x00, 0x78, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0x6c, 0x53, 0x00, 0xe6, 0x53, 0x00, 0x60, 0x54, 0x00, 0xda, 0x54, 0x00, 0x54, 0x55, 0x00, 0xce, 0x55, 0x00, 0x48, 0x56, 0x00, 0xc2, 0x56, 0x00, 0x3c, 0x57, 0x00, 0xb6, 0x57, 0x00, 0x30, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0x24, 0x59, 0x00, 0x9e, 0x59, 0x00, 0x18, 0x5a, 0x00, 0x92, 0x5a, 0x00, 0x0c, 0x5b, 0x00, 0x86, 0x5b, 0x00, 0x00, 0x5c, 0x00, 0x7a, 0x5c, 0x00, 0xf4, 0x5c, 0x00, 0x6e, 0x5d, 0x00, 0xe8, 0x5d, 0x00, 0x62, 0x5e, 0x00, 0xdc, 0x5e, 0x00, 0x56, 0x5f, 0x00, 0xd0, 0x5f, 0x00, 0x4a, 0x60, 0x00, 0xc4, 0x60, 0x00, 0x3e, 0x61, 0x00, 0xb8, 0x61, 0x00, 0x32, 0x62, 0x00, 0xac, 0x62, 0x00, 0x26, 0x63, 0x00, 0xa0, 0x63, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x94, 0x64, 0x00, 0x0e, 0x65, 0x00, 0x88, 0x65, 0x00, 0x02, 0x66, 0x00, 0x7c, 0x66, 0x00, 0xf6, 0x66, 0x00, 0x70, 0x67, 0x00, 0xea, 0x67, 0x00, 0x64, 0x68, 0x00, 0xde, 0x68, 0x00, 0x58, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0x4c, 0x6a, 0x00, 0xc6, 0x6a, 0x00, 0x40, 0x6b, 0x00, 0xba, 0x6b, 0x00, 0x34, 0x6c, 0x00, 0xae, 0x6c, 0x00, 0x28, 0x6d, 0x00, 0xa2, 0x6d, 0x00, 0x1c, 0x6e, 0x00, 0x96, 0x6e, 0x00, 0x10, 0x6f, 0x00, 0x8a, 0x6f, 0x00, 0x04, 0x70, 0x00, 0x7e, 0x70, 0x00, 0xf8, 0x70, 0x00, 0x72, 0x71, 0x00, 0xec, 0x71, 0x00, 0x66, 0x72, 0x00, 0xe0, 0x72, 0x00, 0x5a, 0x73, 0x00, 0xd4, 0x73, 0x00, 0x4e, 0x74, 0x00, 0xc8, 0x74, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0xbc, 0x75, 0x00, 0x36, 0x76, 0x00, 0xb0, 0x76, 0x00, 0x2a, 0x77, 0x00, 0xa4, 0x77, 0x00, 0x1e, 0x78, 0x00, 0x98, 0x78, 0x00, 0x12, 0x79, 0x00, 0x8c, 0x79, 0x00, 0x06, 0x7a, 0x00, 0x80, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0x74, 0x7b, 0x00, 0xe2, 0x7b, 0x00, 0x50, 0x7c, 0x00, 0xbe, 0x7c, 0x00, 0x2c, 0x7d, 0x00, 0x9a, 0x7d, 0x00, 0x08, 0x7e, 0x00, 0x76, 0x7e, 0x00, 0xe4, 0x7e, 0x00, 0x52, 0x7f, 0x00, 0xc0, 0x7f, 0x00, 0x2e, 0x80, 0x00, 0x9c, 0x80, 0x00, 0x0a, 0x81, 0x00, 0x78, 0x81, 0x00, 0xe6, 0x81, 0x00, 0x54, 0x82, 0x00, 0xc2, 0x82, 0x00, 0x30, 0x83, 0x00, 0x9e, 0x83, 0x00, 0x0c, 0x84, 0x00, 0x7a, 0x84, 0x00, 0xe8, 0x84, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0xc4, 0x85, 0x00, 0x32, 0x86, 0x00, 0xa0, 0x86, 0x00, 0x0e, 0x87, 0x00, 0x7c, 0x87, 0x00, 0xea, 0x87, 0x00, 0x58, 0x88, 0x00, 0xc6, 0x88, 0x00, 0x34, 0x89, 0x00, 0xa2, 0x89, 0x00, 0x10, 0x8a, 0x00, 0x7e, 0x8a, 0x00, 0xec, 0x8a, 0x00, 0x2e, 0x8b, 0x00, 0xac, 0x8b, 0x00, 0x2a, 0x8c, 0x00, 0xa8, 0x8c, 0x00, 0x26, 0x8d, 0x00, 0xa4, 0x8d, 0x00, 0x22, 0x8e, 0x00, 0xa0, 0x8e, 0x00, 0x1e, 0x8f, 0x00, 0x60, 0x8f, 0x00, 0xa2, 0x8f, 0x00, 0xe4, 0x8f, 0x00, 0x13, 0x90, 0x00, 0x42, 0x90, 0x00, 0x65, 0x90, 0x00, 0x88, 0x90, 0x00, 0xab, 0x90, 0x00, 0xce, 0x90, 0x00, 0xf1, 0x90, 0x00, 0x57, 0x91, 0x00, 0xbd, 0x91, 0x00, 0x23, 0x92, 0x00, 0x89, 0x92, 0x00, 0xef, 0x92, 0x00, 0x55, 0x93, 0x00, 0xbb, 0x93, 0x00, 0x21, 0x94, 0x00, 0x87, 0x94, 0x00, 0xed, 0x94, 0x00, 0x53, 0x95, 0x00, 0xb9, 0x95, 0x00, 0x1f, 0x96, 0x00, 0x85, 0x96, 0x00, 0xeb, 0x96, 0x00, 0x51, 0x97, 0x00, 0xb7, 0x97, 0x00, 0x1d, 0x98, 0x00, 0x83, 0x98, 0x00, 0xe9, 0x98, 0x00, 0x4f, 0x99, 0x00, 0xb5, 0x99, 0x00, 0x1b, 0x9a, 0x00, 0x81, 0x9a, 0x00, 0xe7, 0x9a, 0x00, 0x4d, 0x9b, 0x00, 0xb3, 0x9b, 0x00, 0x19, 0x9c, 0x00, 0x7f, 0x9c, 0x00, 0xe5, 0x9c, 0x00, 0x4b, 0x9d, 0x00, 0xb1, 0x9d, 0x00, 0x17, 0x9e, 0x00, 0x7d, 0x9e, 0x00, 0xe3, 0x9e, 0x00, 0x49, 0x9f, 0x00, 0xaf, 0x9f, 0x00, 0x15, 0xa0, 0x00, 0x7b, 0xa0, 0x00, 0xe1, 0xa0, 0x00, 0x47, 0xa1, 0x00, 0xad, 0xa1, 0x00, 0x13, 0xa2, 0x00, 0x79, 0xa2, 0x00, 0xdf, 0xa2, 0x00, 0x45, 0xa3, 0x00, 0xab, 0xa3, 0x00, 0x11, 0xa4, 0x00, 0x77, 0xa4, 0x00, 0xdd, 0xa4, 0x00, 0x43, 0xa5, 0x00, 0xa9, 0xa5, 0x00, 0x0f, 0xa6, 0x00, 0x75, 0xa6, 0x00, 0xdb, 0xa6, 0x00, 0x41, 0xa7, 0x00, 0xa7, 0xa7, 0x00, 0x0d, 0xa8, 0x00, 0x73, 0xa8, 0x00, 0xd9, 0xa8, 0x00, 0x3f, 0xa9, 0x00, 0xa5, 0xa9, 0x00, 0x0b, 0xaa, 0x00, 0x71, 0xaa, 0x00, 0xd7, 0xaa, 0x00, 0x3d, 0xab, 0x00, 0xa3, 0xab, 0x00, 0x09, 0xac, 0x00, 0x6f, 0xac, 0x00, 0xd5, 0xac, 0x00, 0x3b, 0xad, 0x00, 0xa1, 0xad, 0x00, 0x07, 0xae, 0x00, 0x6d, 0xae, 0x00, 0xd3, 0xae, 0x00, 0x39, 0xaf, 0x00, 0x9f, 0xaf, 0x00, 0x05, 0xb0, 0x00, 0x6b, 0xb0, 0x00, 0xd1, 0xb0, 0x00, 0x37, 0xb1, 0x00, 0x9d, 0xb1, 0x00, 0x03, 0xb2, 0x00, 0x69, 0xb2, 0x00, 0xcf, 0xb2, 0x00, 0x35, 0xb3, 0x00, 0x9b, 0xb3, 0x00, 0x01, 0xb4, 0x00, 0x67, 0xb4, 0x00, 0xcd, 0xb4, 0x00, 0x33, 0xb5, 0x00, 0x99, 0xb5, 0x00, 0xff, 0xb5, 0x00, 0x65, 0xb6, 0x00, 0xcb, 0xb6, 0x00, 0x31, 0xb7, 0x00, 0x97, 0xb7, 0x00, 0xfd, 0xb7, 0x00, 0x63, 0xb8, 0x00, 0xc9, 0xb8, 0x00, 0x2f, 0xb9, 0x00, 0x95, 0xb9, 0x00, 0xfb, 0xb9, 0x00, 0x61, 0xba, 0x00, 0xc7, 0xba, 0x00, 0x2d, 0xbb, 0x00, 0x93, 0xbb, 0x00, 0xf9, 0xbb, 0x00, 0x5f, 0xbc, 0x00, 0xc5, 0xbc, 0x00, 0x2b, 0xbd, 0x00, 0x91, 0xbd, 0x00, 0xf7, 0xbd, 0x00, 0x5d, 0xbe, 0x00, 0xc3, 0xbe, 0x00, 0x29, 0xbf, 0x00, 0x8f, 0xbf, 0x00, 0xf5, 0xbf, 0x00, 0x5b, 0xc0, 0x00, 0xc1, 0xc0, 0x00, 0x27, 0xc1, 0x00, 0x8d, 0xc1, 0x00, 0xf3, 0xc1, 0x00, 0x59, 0xc2, 0x00, 0xbf, 0xc2, 0x00, 0x25, 0xc3, 0x00, 0x8b, 0xc3, 0x00, 0xf1, 0xc3, 0x00, 0x57, 0xc4, 0x00, 0xbd, 0xc4, 0x00, 0x23, 0xc5, 0x00, 0x89, 0xc5, 0x00, 0xef, 0xc5, 0x00, 0x55, 0xc6, 0x00, 0xbb, 0xc6, 0x00, 0x21, 0xc7, 0x00, 0x87, 0xc7, 0x00, 0xed, 0xc7, 0x00, 0x53, 0xc8, 0x00, 0xb9, 0xc8, 0x00, 0x1f, 0xc9, 0x00, 0x85, 0xc9, 0x00, 0xeb, 0xc9, 0x00, 0x51, 0xca, 0x00, 0xb7, 0xca, 0x00, 0x1d, 0xcb, 0x00, 0x83, 0xcb, 0x00, 0xe9, 0xcb, 0x00, 0x4f, 0xcc, 0x00, 0xb5, 0xcc, 0x00, 0x1b, 0xcd, 0x00, 0x81, 0xcd, 0x00, 0xe7, 0xcd, 0x00, 0x4d, 0xce, 0x00, 0xb3, 0xce, 0x00, 0x19, 0xcf, 0x00, 0x7f, 0xcf, 0x00, 0xe5, 0xcf, 0x00, 0x4b, 0xd0, 0x00, 0xb1, 0xd0, 0x00, 0x17, 0xd1, 0x00, 0x7d, 0xd1, 0x00, 0xe3, 0xd1, 0x00, 0x49, 0xd2, 0x00, 0xaf, 0xd2, 0x00, 0x15, 0xd3, 0x00, 0x7b, 0xd3, 0x00, 0xe1, 0xd3, 0x00, 0x47, 0xd4, 0x00, 0xad, 0xd4, 0x00, 0x13, 0xd5, 0x00, 0x79, 0xd5, 0x00, 0xdf, 0xd5, 0x00, 0x45, 0xd6, 0x00, 0xab, 0xd6, 0x00, 0x11, 0xd7, 0x00, 0x77, 0xd7, 0x00, 0xdd, 0xd7, 0x00, 0x43, 0xd8, 0x00, 0xa9, 0xd8, 0x00, 0x0f, 0xd9, 0x00, 0x75, 0xd9, 0x00, 0xdb, 0xd9, 0x00, 0x41, 0xda, 0x00, 0xa7, 0xda, 0x00, 0x0d, 0xdb, 0x00, 0x73, 0xdb, 0x00, 0xd9, 0xdb, 0x00, 0x3f, 0xdc, 0x00, 0xa5, 0xdc, 0x00, 0x0b, 0xdd, 0x00, 0x71, 0xdd, 0x00, 0xd7, 0xdd, 0x00, 0x3d, 0xde, 0x00, 0xa3, 0xde, 0x00, 0x09, 0xdf, 0x00, 0x6f, 0xdf, 0x00, 0xd5, 0xdf, 0x00, 0x3b, 0xe0, 0x00, 0xa1, 0xe0, 0x00, 0x07, 0xe1, 0x00, 0x6d, 0xe1, 0x00, 0xd3, 0xe1, 0x00, 0x39, 0xe2, 0x00, 0x9f, 0xe2, 0x00, 0x05, 0xe3, 0x00, 0x6b, 0xe3, 0x00, 0xd1, 0xe3, 0x00, 0x37, 0xe4, 0x00, 0x9d, 0xe4, 0x00, 0x03, 0xe5, 0x00, 0x69, 0xe5, 0x00, 0xcf, 0xe5, 0x00, 0x35, 0xe6, 0x00, 0x9b, 0xe6, 0x00, 0x01, 0xe7, 0x00, 0x67, 0xe7, 0x00, 0xcd, 0xe7, 0x00, 0x33, 0xe8, 0x00, 0x99, 0xe8, 0x00, 0xff, 0xe8, 0x00, 0x65, 0xe9, 0x00, 0xcb, 0xe9, 0x00, 0x31, 0xea, 0x00, 0x97, 0xea, 0x00, 0xfd, 0xea, 0x00, 0x63, 0xeb, 0x00, 0xc9, 0xeb, 0x00, 0x2f, 0xec, 0x00, 0x95, 0xec, 0x00, 0xfb, 0xec, 0x00, 0x61, 0xed, 0x00, 0xc7, 0xed, 0x00, 0x2d, 0xee, 0x00, 0x93, 0xee, 0x00, 0xf9, 0xee, 0x00, 0x5f, 0xef, 0x00, 0xc5, 0xef, 0x00, 0x2b, 0xf0, 0x00, 0x91, 0xf0, 0x00, 0xf7, 0xf0, 0x00, 0x5d, 0xf1, 0x00, 0xc3, 0xf1, 0x00, 0x29, 0xf2, 0x00, 0x8f, 0xf2, 0x00, 0xf5, 0xf2, 0x00, 0x5b, 0xf3, 0x00, 0xc1, 0xf3, 0x00, 0x27, 0xf4, 0x00, 0x8d, 0xf4, 0x00, 0xf3, 0xf4, 0x00, 0x59, 0xf5, 0x00, 0xbf, 0xf5, 0x00, 0x25, 0xf6, 0x00, 0x8b, 0xf6, 0x00, 0xf1, 0xf6, 0x00, 0x57, 0xf7, 0x00, 0xbd, 0xf7, 0x00, 0x23, 0xf8, 0x00, 0x89, 0xf8, 0x00, 0xef, 0xf8, 0x00, 0x55, 0xf9, 0x00, 0xbb, 0xf9, 0x00, 0x21, 0xfa, 0x00, 0x87, 0xfa, 0x00, 0xed, 0xfa, 0x00, 0x53, 0xfb, 0x00, 0xb9, 0xfb, 0x00, 0x1f, 0xfc, 0x00, 0x85, 0xfc, 0x00, 0xeb, 0xfc, 0x00, 0x51, 0xfd, 0x00, 0xb7, 0xfd, 0x00, 0x1d, 0xfe, 0x00, 0x83, 0xfe, 0x00, 0xe9, 0xfe, 0x00, 0x4f, 0xff, 0x00, 0xb5, 0xff, 0x00, 0x1b, 0x00, 0x01, 0x81, 0x00, 0x01, 0xe7, 0x00, 0x01, 0x4d, 0x01, 0x01, 0xb3, 0x01, 0x01, 0x19, 0x02, 0x01, 0x7f, 0x02, 0x01, 0xe5, 0x02, 0x01, 0x4b, 0x03, 0x01, 0xb1, 0x03, 0x01, 0x17, 0x04, 0x01, 0x7d, 0x04, 0x01, 0xe3, 0x04, 0x01, 0x49, 0x05, 0x01, 0xaf, 0x05, 0x01, 0x15, 0x06, 0x01, 0x7b, 0x06, 0x01, 0xe1, 0x06, 0x01, 0x47, 0x07, 0x01, 0xad, 0x07, 0x01, 0x13, 0x08, 0x01, 0x79, 0x08, 0x01, 0xdf, 0x08, 0x01, 0x45, 0x09, 0x01, 0xab, 0x09, 0x01, 0x11, 0x0a, 0x01, 0x77, 0x0a, 0x01, 0xdd, 0x0a, 0x01, 0x43, 0x0b, 0x01, 0xa9, 0x0b, 0x01, 0x0f, 0x0c, 0x01, 0x75, 0x0c, 0x01, 0xdb, 0x0c, 0x01, 0x41, 0x0d, 0x01, 0xa7, 0x0d, 0x01, 0x0d, 0x0e, 0x01, 0x73, 0x0e, 0x01, 0xd9, 0x0e, 0x01, 0x3f, 0x0f, 0x01, 0xa5, 0x0f, 0x01, 0x0b, 0x10, 0x01, 0x71, 0x10, 0x01, 0xd7, 0x10, 0x01, 0x3d, 0x11, 0x01, 0xa3, 0x11, 0x01, 0x09, 0x12, 0x01, 0x6f, 0x12, 0x01, 0xd5, 0x12, 0x01, 0x3b, 0x13, 0x01, 0xa1, 0x13, 0x01, 0x07, 0x14, 0x01, 0x6d, 0x14, 0x01, 0xd3, 0x14, 0x01, 0x39, 0x15, 0x01, 0x9f, 0x15, 0x01, 0x05, 0x16, 0x01, 0x6b, 0x16, 0x01, 0xd1, 0x16, 0x01, 0x37, 0x17, 0x01, 0x9d, 0x17, 0x01, 0x03, 0x18, 0x01, 0x69, 0x18, 0x01, 0xcf, 0x18, 0x01, 0x35, 0x19, 0x01, 0x9b, 0x19, 0x01, 0x01, 0x1a, 0x01, 0x67, 0x1a, 0x01, 0xcd, 0x1a, 0x01, 0x33, 0x1b, 0x01, 0x99, 0x1b, 0x01, 0xff, 0x1b, 0x01, 0x65, 0x1c, 0x01, 0xcb, 0x1c, 0x01, 0x31, 0x1d, 0x01, 0x97, 0x1d, 0x01, 0xfd, 0x1d, 0x01, 0x63, 0x1e, 0x01, 0xc9, 0x1e, 0x01, 0x2f, 0x1f, 0x01, 0x95, 0x1f, 0x01, 0xfb, 0x1f, 0x01, 0x61, 0x20, 0x01, 0xc7, 0x20, 0x01, 0x2d, 0x21, 0x01, 0x93, 0x21, 0x01, 0xf9, 0x21, 0x01, 0x5f, 0x22, 0x01, 0xc5, 0x22, 0x01, 0x2b, 0x23, 0x01, 0x91, 0x23, 0x01, 0xf7, 0x23, 0x01, 0x5d, 0x24, 0x01, 0xc3, 0x24, 0x01, 0x29, 0x25, 0x01, 0x8f, 0x25, 0x01, 0xf5, 0x25, 0x01, 0x5b, 0x26, 0x01, 0xc1, 0x26, 0x01, 0x27, 0x27, 0x01, 0x8d, 0x27, 0x01, 0xf3, 0x27, 0x01, 0x59, 0x28, 0x01, 0xbf, 0x28, 0x01, 0x25, 0x29, 0x01, 0x8b, 0x29, 0x01, 0xf1, 0x29, 0x01, 0x57, 0x2a, 0x01, 0xbd, 0x2a, 0x01, 0x23, 0x2b, 0x01, 0x89, 0x2b, 0x01, 0xef, 0x2b, 0x01, 0x55, 0x2c, 0x01, 0xbb, 0x2c, 0x01, 0x21, 0x2d, 0x01, 0x87, 0x2d, 0x01, 0xed, 0x2d, 0x01, 0x53, 0x2e, 0x01, 0xb9, 0x2e, 0x01, 0x1f, 0x2f, 0x01, 0x85, 0x2f, 0x01, 0xeb, 0x2f, 0x01, 0x51, 0x30, 0x01, 0xb7, 0x30, 0x01, 0x1d, 0x31, 0x01, 0x83, 0x31, 0x01, 0xe9, 0x31, 0x01, 0x4f, 0x32, 0x01, 0xb5, 0x32, 0x01, 0x1b, 0x33, 0x01, 0x81, 0x33, 0x01, 0xe7, 0x33, 0x01, 0x4d, 0x34, 0x01, 0xb3, 0x34, 0x01, 0x19, 0x35, 0x01, 0x7f, 0x35, 0x01, 0xe5, 0x35, 0x01, 0x4b, 0x36, 0x01, 0xb1, 0x36, 0x01, 0x17, 0x37, 0x01, 0x7d, 0x37, 0x01, 0xe3, 0x37, 0x01, 0x49, 0x38, 0x01, 0xaf, 0x38, 0x01, 0x15, 0x39, 0x01, 0x7b, 0x39, 0x01, 0xe1, 0x39, 0x01, 0x47, 0x3a, 0x01, 0xad, 0x3a, 0x01, 0x13, 0x3b, 0x01, 0x79, 0x3b, 0x01, 0xdf, 0x3b, 0x01, 0x45, 0x3c, 0x01, 0xab, 0x3c, 0x01, 0x11, 0x3d, 0x01, 0x77, 0x3d, 0x01, 0xdd, 0x3d, 0x01, 0x43, 0x3e, 0x01, 0xa9, 0x3e, 0x01, 0x0f, 0x3f, 0x01, 0x75, 0x3f, 0x01, 0xdb, 0x3f, 0x01, 0x41, 0x40, 0x01, 0xa7, 0x40, 0x01, 0x0d, 0x41, 0x01, 0x73, 0x41, 0x01, 0xd9, 0x41, 0x01, 0x3f, 0x42, 0x01, 0xa5, 0x42, 0x01, 0x0b, 0x43, 0x01, 0x71, 0x43, 0x01, 0xd7, 0x43, 0x01, 0x3d, 0x44, 0x01, 0xa3, 0x44, 0x01, 0x09, 0x45, 0x01, 0x6f, 0x45, 0x01, 0xd5, 0x45, 0x01, 0x3b, 0x46, 0x01, 0xa1, 0x46, 0x01, 0x07, 0x47, 0x01, 0x6d, 0x47, 0x01, 0xd3, 0x47, 0x01, 0x39, 0x48, 0x01, 0x9f, 0x48, 0x01, 0x05, 0x49, 0x01, 0x6b, 0x49, 0x01, 0xd1, 0x49, 0x01, 0x37, 0x4a, 0x01, 0x9d, 0x4a, 0x01, 0x03, 0x4b, 0x01, 0x69, 0x4b, 0x01, 0xcf, 0x4b, 0x01, 0x35, 0x4c, 0x01, 0x9b, 0x4c, 0x01, 0x01, 0x4d, 0x01, 0x67, 0x4d, 0x01, 0xcd, 0x4d, 0x01, 0x33, 0x4e, 0x01, 0x99, 0x4e, 0x01, 0xff, 0x4e, 0x01, 0x65, 0x4f, 0x01, 0xcb, 0x4f, 0x01, 0x31, 0x50, 0x01, 0x97, 0x50, 0x01, 0xfd, 0x50, 0x01, 0x63, 0x51, 0x01, 0xc9, 0x51, 0x01, 0x2f, 0x52, 0x01, 0x95, 0x52, 0x01, 0xfb, 0x52, 0x01, 0x61, 0x53, 0x01, 0xc7, 0x53, 0x01, 0x2d, 0x54, 0x01, 0x93, 0x54, 0x01, 0xf9, 0x54, 0x01, 0x5f, 0x55, 0x01, 0xc5, 0x55, 0x01, 0x2b, 0x56, 0x01, 0x91, 0x56, 0x01, 0xf7, 0x56, 0x01, 0x5d, 0x57, 0x01, 0xc3, 0x57, 0x01, 0x29, 0x58, 0x01, 0x8f, 0x58, 0x01, 0xf5, 0x58, 0x01, 0x5b, 0x59, 0x01, 0xc1, 0x59, 0x01, 0x27, 0x5a, 0x01, 0x8d, 0x5a, 0x01, 0xf3, 0x5a, 0x01, 0x59, 0x5b, 0x01, 0xbf, 0x5b, 0x01, 0x25, 0x5c, 0x01, 0x8b, 0x5c, 0x01, 0xf1, 0x5c, 0x01, 0x57, 0x5d, 0x01, 0xbd, 0x5d, 0x01, 0x23, 0x5e, 0x01, 0x89, 0x5e, 0x01, 0xef, 0x5e, 0x01, 0x55, 0x5f, 0x01, 0xbb, 0x5f, 0x01, 0x21, 0x60, 0x01, 0x87, 0x60, 0x01, 0xed, 0x60, 0x01, 0x53, 0x61, 0x01, 0xb9, 0x61, 0x01, 0x1f, 0x62, 0x01, 0x85, 0x62, 0x01, 0xeb, 0x62, 0x01, 0x51, 0x63, 0x01, 0xb7, 0x63, 0x01, 0x1d, 0x64, 0x01, 0x83, 0x64, 0x01, 0xe9, 0x64, 0x01, 0x4f, 0x65, 0x01, 0xb5, 0x65, 0x01, 0x1b, 0x66, 0x01, 0x81, 0x66, 0x01, 0xe7, 0x66, 0x01, 0x4d, 0x67, 0x01, 0xb3, 0x67, 0x01, 0x19, 0x68, 0x01, 0x7f, 0x68, 0x01, 0xe5, 0x68, 0x01, 0x4b, 0x69, 0x01, 0xb1, 0x69, 0x01, 0x17, 0x6a, 0x01, 0x7d, 0x6a, 0x01, 0xe3, 0x6a, 0x01, 0x49, 0x6b, 0x01, 0xaf, 0x6b, 0x01, 0x15, 0x6c, 0x01, 0x7b, 0x6c, 0x01, 0xe1, 0x6c, 0x01, 0x47, 0x6d, 0x01, 0xad, 0x6d, 0x01, 0x13, 0x6e, 0x01, 0x79, 0x6e, 0x01, 0xdf, 0x6e, 0x01, 0x45, 0x6f, 0x01, 0xab, 0x6f, 0x01, 0x11, 0x70, 0x01, 0x77, 0x70, 0x01, 0xdd, 0x70, 0x01, 0x43, 0x71, 0x01, 0xa9, 0x71, 0x01, 0x0f, 0x72, 0x01, 0x75, 0x72, 0x01, 0xdb, 0x72, 0x01, 0x41, 0x73, 0x01, 0xa7, 0x73, 0x01, 0x0d, 0x74, 0x01, 0x73, 0x74, 0x01, 0xd9, 0x74, 0x01, 0x3f, 0x75, 0x01, 0xa5, 0x75, 0x01, 0x0b, 0x76, 0x01, 0x71, 0x76, 0x01, 0xd7, 0x76, 0x01, 0x3d, 0x77, 0x01, 0xa3, 0x77, 0x01, 0x09, 0x78, 0x01, 0x6f, 0x78, 0x01, 0xd5, 0x78, 0x01, 0x3b, 0x79, 0x01, 0xa1, 0x79, 0x01, 0x07, 0x7a, 0x01, 0x6d, 0x7a, 0x01, 0xd3, 0x7a, 0x01, 0x39, 0x7b, 0x01, 0x9f, 0x7b, 0x01, 0x05, 0x7c, 0x01, 0x6b, 0x7c, 0x01, 0xd1, 0x7c, 0x01, 0x37, 0x7d, 0x01, 0x9d, 0x7d, 0x01, 0x03, 0x7e, 0x01, 0x69, 0x7e, 0x01, 0xcf, 0x7e, 0x01, 0x35, 0x7f, 0x01, 0x9b, 0x7f, 0x01, 0x01, 0x80, 0x01, 0x67, 0x80, 0x01, 0xcd, 0x80, 0x01, 0x33, 0x81, 0x01, 0x99, 0x81, 0x01, 0xff, 0x81, 0x01, 0x65, 0x82, 0x01, 0xcb, 0x82, 0x01, 0x31, 0x83, 0x01, 0x97, 0x83, 0x01, 0xfd, 0x83, 0x01, 0x63, 0x84, 0x01, 0xc9, 0x84, 0x01, 0x2f, 0x85, 0x01, 0x95, 0x85, 0x01, 0xfb, 0x85, 0x01, 0x61, 0x86, 0x01, 0xc7, 0x86, 0x01, 0x2d, 0x87, 0x01, 0x93, 0x87, 0x01, 0xf9, 0x87, 0x01, 0x5f, 0x88, 0x01, 0xc5, 0x88, 0x01, 0x2b, 0x89, 0x01, 0x91, 0x89, 0x01, 0xf7, 0x89, 0x01, 0x5d, 0x8a, 0x01, 0xc3, 0x8a, 0x01, 0x29, 0x8b, 0x01, 0x8f, 0x8b, 0x01, 0xf5, 0x8b, 0x01, 0x5b, 0x8c, 0x01, 0xc1, 0x8c, 0x01, 0x27, 0x8d, 0x01, 0x8d, 0x8d, 0x01, 0xf3, 0x8d, 0x01, 0x59, 0x8e, 0x01, 0xbf, 0x8e, 0x01, 0x25, 0x8f, 0x01, 0x8b, 0x8f, 0x01, 0xf1, 0x8f, 0x01, 0x57, 0x90, 0x01, 0xbd, 0x90, 0x01, 0x23, 0x91, 0x01, 0x89, 0x91, 0x01, 0xef, 0x91, 0x01, 0x55, 0x92, 0x01, 0xbb, 0x92, 0x01, 0x21, 0x93, 0x01, 0x87, 0x93, 0x01, 0xed, 0x93, 0x01, 0x53, 0x94, 0x01, 0xb9, 0x94, 0x01, 0x1f, 0x95, 0x01, 0x85, 0x95, 0x01, 0xeb, 0x95, 0x01, 0x51, 0x96, 0x01, 0xb7, 0x96, 0x01, 0x1d, 0x97, 0x01, 0x83, 0x97, 0x01, 0xe9, 0x97, 0x01, 0x4f, 0x98, 0x01, 0xb5, 0x98, 0x01, 0x1b, 0x99, 0x01, 0x81, 0x99, 0x01, 0xe7, 0x99, 0x01, 0x4d, 0x9a, 0x01, 0xb3, 0x9a, 0x01, 0x19, 0x9b, 0x01, 0x7f, 0x9b, 0x01, 0xe5, 0x9b, 0x01, 0x4b, 0x9c, 0x01, 0xb1, 0x9c, 0x01, 0x17, 0x9d, 0x01, 0x7d, 0x9d, 0x01, 0xe3, 0x9d, 0x01, 0x49, 0x9e, 0x01, 0xaf, 0x9e, 0x01, 0x15, 0x9f, 0x01, 0x7b, 0x9f, 0x01, 0xe1, 0x9f, 0x01, 0x47, 0xa0, 0x01, 0xad, 0xa0, 0x01, 0x13, 0xa1, 0x01, 0x79, 0xa1, 0x01, 0xdf, 0xa1, 0x01, 0x45, 0xa2, 0x01, 0xab, 0xa2, 0x01, 0x11, 0xa3, 0x01, 0x77, 0xa3, 0x01, 0xdd, 0xa3, 0x01, 0x43, 0xa4, 0x01, 0xa9, 0xa4, 0x01, 0x0f, 0xa5, 0x01, 0x75, 0xa5, 0x01, 0xdb, 0xa5, 0x01, 0x41, 0xa6, 0x01, 0xa7, 0xa6, 0x01, 0x0d, 0xa7, 0x01, 0x73, 0xa7, 0x01, 0xd9, 0xa7, 0x01, 0x3f, 0xa8, 0x01, 0xa5, 0xa8, 0x01, 0x0b, 0xa9, 0x01, 0x71, 0xa9, 0x01, 0xd7, 0xa9, 0x01, 0x3d, 0xaa, 0x01, 0xa3, 0xaa, 0x01, 0x09, 0xab, 0x01, 0x6f, 0xab, 0x01, 0xd5, 0xab, 0x01, 0x3b, 0xac, 0x01, 0xa1, 0xac, 0x01, 0x07, 0xad, 0x01, 0x6d, 0xad, 0x01, 0xd3, 0xad, 0x01, 0x39, 0xae, 0x01, 0x9f, 0xae, 0x01, 0x05, 0xaf, 0x01, 0x6b, 0xaf, 0x01, 0xd1, 0xaf, 0x01, 0x37, 0xb0, 0x01, 0x9d, 0xb0, 0x01, 0x03, 0xb1, 0x01, 0x69, 0xb1, 0x01, 0xcf, 0xb1, 0x01, 0x35, 0xb2, 0x01, 0x9b, 0xb2, 0x01, 0x01, 0xb3, 0x01, 0x67, 0xb3, 0x01, 0xcd, 0xb3, 0x01, 0x33, 0xb4, 0x01, 0x99, 0xb4, 0x01, 0xff, 0xb4, 0x01, 0x65, 0xb5, 0x01, 0xcb, 0xb5, 0x01, 0x31, 0xb6, 0x01, 0x97, 0xb6, 0x01, 0xfd, 0xb6, 0x01, 0x63, 0xb7, 0x01, 0xc9, 0xb7, 0x01, 0x2f, 0xb8, 0x01, 0x95, 0xb8, 0x01, 0xfb, 0xb8, 0x01, 0x61, 0xb9, 0x01, 0xc7, 0xb9, 0x01, 0x2d, 0xba, 0x01, 0x93, 0xba, 0x01, 0xf9, 0xba, 0x01, 0x5f, 0xbb, 0x01, 0xc5, 0xbb, 0x01, 0x2b, 0xbc, 0x01, 0x91, 0xbc, 0x01, 0xf7, 0xbc, 0x01, 0x5d, 0xbd, 0x01, 0xc3, 0xbd, 0x01, 0x29, 0xbe, 0x01, 0x8f, 0xbe, 0x01, 0xf5, 0xbe, 0x01, 0x5b, 0xbf, 0x01, 0xc1, 0xbf, 0x01, 0x27, 0xc0, 0x01, 0x8d, 0xc0, 0x01, 0xf3, 0xc0, 0x01, 0x59, 0xc1, 0x01, 0xbf, 0xc1, 0x01, 0x25, 0xc2, 0x01, 0x8b, 0xc2, 0x01, 0xf1, 0xc2, 0x01, 0x57, 0xc3, 0x01, 0xbd, 0xc3, 0x01, 0x23, 0xc4, 0x01, 0x89, 0xc4, 0x01, 0xef, 0xc4, 0x01, 0x55, 0xc5, 0x01, 0xbb, 0xc5, 0x01, 0x21, 0xc6, 0x01, 0x87, 0xc6, 0x01, 0xed, 0xc6, 0x01, 0x53, 0xc7, 0x01, 0xb9, 0xc7, 0x01, 0x1f, 0xc8, 0x01, 0x85, 0xc8, 0x01, 0xeb, 0xc8, 0x01, 0x51, 0xc9, 0x01, 0xb7, 0xc9, 0x01, 0x1d, 0xca, 0x01, 0x83, 0xca, 0x01, 0xe9, 0xca, 0x01, 0x4f, 0xcb, 0x01, 0xb5, 0xcb, 0x01, 0x1b, 0xcc, 0x01, 0x1f, 0x04, 0x07, 0x04, 0x04, 0x02, 0x03, 0x10, 0x00, 0x00, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x0a, 0x06, 0x00, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x10, 0x00, 0x00, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x1f, 0x00, 0x08, 0x00, 0x06, 0x00, 0x03, 0x0a, 0x06, 0x00, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x1e, 0x0b, 0x06, 0x04, 0x04, 0x03, 0x04, 0x0c, 0x04, 0x00, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x13, 0xf8, 0x01, 0x87, 0xf9, 0x01, 0x87, 0xf9, 0x01, 0x35, 0xee, 0x01, 0xa9, 0xf2, 0x01, 0xa9, 0xf2, 0x01, 0x35, 0xee, 0x01, 0xa9, 0xf2, 0x01, 0xa9, 0xf2, 0x01, 0x1e, 0x04, 0x0b, 0x04, 0x08, 0x02, 0x06, 0x04, 0x06, 0x06, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x18, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x0a, 0x06, 0x00, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x08, 0x04, 0x04, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0xb7, 0x11, 0x02, 0x21, 0x17, 0x02, 0x09, 0x1d, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x03, 0x05, 0x08, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0x7c, 0x00, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x73, 0x30, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xf0, 0x3c, 0x03, 0x55, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0xff, 0x00, 0x03, 0x55, 0x55, 0xff, 0x00, 0x3d, 0x55, 0x55, 0xff, 0x00, 0xcd, 0x55, 0x55, 0xcf, 0xff, 0x0d, 0x55, 0x55, 0x73, 0x30, 0x3d, 0x55, 0x55, 0x73, 0xf0, 0xf5, 0x55, 0x55, 0x73, 0xf0, 0x35, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x7f, 0x55, 0x57, 0xff, 0x55, 0xff, 0xd5, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x0f, 0x00, 0xf0, 0xd5, 0x57, 0x30, 0xc3, 0x0c, 0xd5, 0x57, 0x00, 0x3c, 0x00, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x57, 0x3f, 0xff, 0xfc, 0xd5, 0x57, 0xf0, 0xc3, 0x0f, 0xd5, 0x55, 0x73, 0xff, 0xcd, 0x55, 0x55, 0xc3, 0xff, 0xc3, 0x55, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x03, 0x00, 0xc0, 0xd5, 0x57, 0x0c, 0x00, 0x30, 0xd5, 0x57, 0x00, 0x3c, 0x00, 0xd5, 0x55, 0xc0, 0xff, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x3f, 0x0f, 0xc3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x00, 0xf0, 0x0d, 0x55, 0x55, 0xff, 0x0f, 0xf5, 0x55, 0x57, 0x33, 0xfc, 0xcd, 0x55, 0x57, 0xf3, 0xfc, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x30, 0x00, 0x0c, 0xd5, 0x57, 0x0c, 0x00, 0x30, 0xd5, 0x57, 0x00, 0xff, 0x00, 0xd5, 0x5f, 0x03, 0xff, 0xc0, 0xf5, 0x5c, 0xc3, 0xff, 0xc3, 0x35, 0x5f, 0x3f, 0xff, 0xfc, 0xf5, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0xc3, 0xff, 0xc3, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x7f, 0x55, 0x57, 0xff, 0x55, 0xff, 0xd5, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x03, 0x00, 0xc0, 0xd5, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x30, 0x3c, 0x0c, 0xd5, 0x55, 0xcc, 0x3c, 0x33, 0xd5, 0x55, 0xcc, 0x3c, 0x33, 0x55, 0x55, 0xc3, 0xc3, 0xc3, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xd7, 0xf5, 0x55, 0x55, 0x5f, 0x55, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x5c, 0x3f, 0xff, 0xc3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x55, 0xff, 0xff, 0xf5, 0x55, 0x55, 0xc0, 0x00, 0x35, 0x55, 0x57, 0x30, 0x00, 0xcd, 0x55, 0x57, 0xf0, 0x00, 0xfd, 0x55, 0x55, 0x70, 0x00, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0x55, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0x70, 0x00, 0x3d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x70, 0x0c, 0xd5, 0x55, 0x57, 0xc0, 0xfc, 0xd5, 0x55, 0x55, 0xf0, 0x3f, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0x57, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0x70, 0x00, 0x3d, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x30, 0xcd, 0x55, 0x55, 0xfc, 0x3f, 0xf5, 0x55, 0x55, 0x70, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x70, 0x3f, 0xf5, 0x55, 0x55, 0xc0, 0x0f, 0xf5, 0x55, 0x7f, 0xc0, 0x0f, 0xf5, 0x5f, 0xc0, 0xc0, 0x0f, 0x55, 0x5f, 0xc0, 0xc0, 0xcf, 0xd5, 0x55, 0xc0, 0xc0, 0xcf, 0xd5, 0x57, 0xc0, 0x3c, 0xcf, 0xf5, 0x5f, 0xfc, 0x03, 0x0f, 0xf5, 0x5f, 0xff, 0xff, 0xf7, 0xd5, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x3c, 0x03, 0xc3, 0x55, 0x5c, 0xc3, 0x0c, 0x33, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0xc3, 0x0c, 0x33, 0x55, 0x57, 0x30, 0xf0, 0xcc, 0xd5, 0x55, 0xff, 0xff, 0xf0, 0xd5, 0x55, 0x73, 0x0c, 0x03, 0x55, 0x55, 0xcc, 0xfc, 0x0d, 0x55, 0x55, 0xfc, 0xff, 0x0d, 0x55, 0x55, 0x5c, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x55, 0xf5, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x00, 0xc3, 0x00, 0xd5, 0x57, 0x3f, 0xc3, 0xfc, 0xd5, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x5c, 0xcc, 0x35, 0x55, 0x55, 0x73, 0xff, 0xcd, 0x55, 0x55, 0x70, 0xfc, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xc0, 0x30, 0x03, 0x55, 0x55, 0xc0, 0xc0, 0x03, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xfc, 0x00, 0x03, 0x55, 0x55, 0xff, 0x03, 0xc3, 0x55, 0x55, 0x7f, 0x03, 0x3d, 0x55, 0x55, 0x5f, 0xff, 0x35, 0x55, 0x55, 0x5c, 0xcc, 0x0d, 0x55, 0x55, 0x57, 0x3c, 0x03, 0x55, 0x55, 0x57, 0x3c, 0x3f, 0x55, 0x55, 0x57, 0xff, 0xf5, 0x55, 0x55, 0x55, 0x7d, 0xfd, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0x7f, 0x55, 0x55, 0x55, 0xff, 0xff, 0xd5, 0x55, 0x55, 0xff, 0xff, 0xd5, 0x55, 0x55, 0xff, 0x00, 0x35, 0x55, 0x57, 0xf0, 0x00, 0x3d, 0x55, 0x57, 0xc0, 0x03, 0x03, 0x55, 0x57, 0x00, 0x3c, 0x03, 0x55, 0x57, 0x00, 0x00, 0x0f, 0x55, 0x57, 0x00, 0x00, 0x35, 0x55, 0x57, 0xc0, 0x03, 0xd5, 0x55, 0x55, 0x7f, 0xff, 0x55, 0x55, 0x55, 0xc0, 0xcf, 0x55, 0x55, 0x57, 0x30, 0xfd, 0x55, 0x55, 0x57, 0xf0, 0xfd, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x7d, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xf5, 0x55, 0x55, 0x5f, 0xfd, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0x00, 0x0d, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x0f, 0xc3, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0x70, 0x00, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x5c, 0x3c, 0xd5, 0x55, 0x55, 0x5f, 0x0f, 0xd5, 0x55, 0x55, 0x5c, 0xff, 0xd5, 0x55, 0x55, 0x70, 0x0f, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3c, 0x0f, 0x55, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0xc0, 0x00, 0xff, 0x55, 0x55, 0xc0, 0xf0, 0xff, 0x55, 0x55, 0x70, 0xcc, 0xfd, 0x55, 0x55, 0x5f, 0xcf, 0xd5, 0x55, 0x55, 0x5c, 0xcc, 0xd5, 0x55, 0x55, 0x5c, 0x3f, 0xd5, 0x55, 0x55, 0x5c, 0x0f, 0xd5, 0x55, 0x55, 0x70, 0x0f, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x55, 0xfd, 0x55, 0x55, 0x7f, 0xdf, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0xc3, 0x55, 0x55, 0xcc, 0x00, 0x03, 0x55, 0x55, 0x73, 0x00, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x73, 0x30, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0x7f, 0x55, 0x55, 0xff, 0xd5, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0xd5, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0x70, 0x00, 0x03, 0x55, 0x55, 0xc3, 0x00, 0x30, 0xd5, 0x55, 0xcc, 0xc0, 0xcc, 0xd5, 0x55, 0xc3, 0x00, 0x30, 0xd5, 0x57, 0xc0, 0x3f, 0x00, 0xd5, 0x57, 0x30, 0xff, 0xc3, 0x55, 0x55, 0xcf, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xc3, 0xfc, 0x03, 0x55, 0x55, 0xc3, 0xfc, 0x3c, 0xd5, 0x55, 0x7f, 0xfc, 0x37, 0xd5, 0x55, 0x5f, 0x7f, 0xd5, 0x55, 0x55, 0x55, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x3c, 0x03, 0xc3, 0x55, 0x5c, 0xf3, 0x0f, 0x33, 0x55, 0x5c, 0xff, 0x0f, 0xf3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x0f, 0xf0, 0x0d, 0x55, 0x55, 0xfc, 0x3f, 0xf5, 0x55, 0x55, 0xc3, 0xcc, 0x3d, 0x55, 0x55, 0x70, 0xfc, 0xf3, 0x55, 0x55, 0x70, 0xfc, 0xdf, 0x55, 0x55, 0x7f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xcd, 0x55, 0x5f, 0xff, 0xff, 0xfd, 0x55, 0x7f, 0xff, 0xff, 0xd5, 0x55, 0x70, 0x00, 0x03, 0xd5, 0x55, 0xff, 0xff, 0xfc, 0xd5, 0x55, 0xc0, 0x00, 0x0f, 0xd5, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0x7c, 0x00, 0x0c, 0xd5, 0x55, 0x5f, 0xff, 0xf0, 0x35, 0x55, 0x7f, 0x3f, 0xfc, 0x0d, 0x55, 0x7f, 0x3f, 0xfc, 0x0d, 0x55, 0x70, 0x00, 0x3c, 0x0d, 0x55, 0x7f, 0xff, 0xf0, 0x0d, 0x55, 0x5f, 0xff, 0xdf, 0xf5, 0x55, 0x7f, 0xdf, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0x55, 0x55, 0x55, 0x57, 0x35, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0xff, 0xff, 0x55, 0x55, 0x5f, 0xff, 0xff, 0x55, 0x55, 0x70, 0x00, 0x0f, 0x55, 0x55, 0x7f, 0xff, 0xf3, 0xfd, 0x55, 0xc0, 0x00, 0x0c, 0xc3, 0x55, 0xc0, 0x00, 0x03, 0xc3, 0x55, 0xc0, 0x00, 0x03, 0x03, 0x55, 0xf0, 0x03, 0x03, 0xc3, 0x55, 0xc3, 0xc0, 0x0f, 0xc3, 0x55, 0xc3, 0xc0, 0x3f, 0x0d, 0x55, 0x7f, 0xff, 0xfc, 0x35, 0x5d, 0xff, 0x3f, 0xf3, 0xd5, 0x5f, 0x00, 0x00, 0xfd, 0x55, 0x5f, 0xff, 0xff, 0x3d, 0x55, 0x55, 0xff, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xff, 0x55, 0x55, 0x7f, 0xff, 0xff, 0xd5, 0x55, 0xf0, 0x00, 0x03, 0xf5, 0x55, 0xcf, 0xff, 0xfc, 0xf5, 0x55, 0xf0, 0x00, 0x03, 0xff, 0x57, 0x0f, 0xc0, 0xfc, 0xf3, 0x57, 0x33, 0xc3, 0x3c, 0xdf, 0x57, 0x33, 0xc3, 0x3c, 0xd5, 0x57, 0x0f, 0xc0, 0xfc, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x35, 0x55, 0xff, 0xff, 0xfc, 0x0d, 0x57, 0xff, 0xcf, 0xf3, 0x0d, 0x5c, 0xff, 0xcf, 0xff, 0x0d, 0x57, 0x70, 0x00, 0x0c, 0x0d, 0x55, 0x7f, 0xff, 0xf7, 0xf5, 0x55, 0x57, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xf7, 0xfd, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xff, 0xf5, 0x55, 0x70, 0x00, 0xff, 0xff, 0x55, 0x7f, 0xfc, 0x03, 0xf3, 0x55, 0xf0, 0xff, 0xf0, 0xdf, 0x55, 0xf0, 0xf3, 0x0f, 0xd5, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xff, 0xf0, 0x33, 0x55, 0x57, 0x3f, 0xc0, 0xff, 0xd5, 0x57, 0xcf, 0xff, 0xfc, 0x35, 0x55, 0xff, 0x3f, 0xfc, 0x0d, 0x55, 0x7f, 0x3f, 0xf0, 0x0d, 0x55, 0x7f, 0x3f, 0xf0, 0x0d, 0x55, 0x70, 0x00, 0xf0, 0x0d, 0x55, 0x5f, 0xff, 0xdf, 0xf5, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x55, 0xf7, 0xd5, 0x55, 0x30, 0x1f, 0x01, 0x55, 0x40, 0x00, 0x00, 0x00, 0x15, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x11, 0x41, 0x50, 0x00, 0x00, 0x15, 0x55, 0x55, 0x54, 0x04, 0x10, 0x01, 0x55, 0x41, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa1, 0x14, 0x15, 0x54, 0x01, 0x11, 0x45, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa5, 0x54, 0x15, 0x54, 0x01, 0x55, 0x45, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa1, 0x14, 0x44, 0x11, 0x55, 0x55, 0x55, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x15, 0x40, 0x01, 0x55, 0x11, 0x56, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x95, 0x40, 0x01, 0x55, 0x55, 0x56, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x95, 0x55, 0x55, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x55, 0x50, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x01, 0x50, 0x55, 0x50, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x15, 0x55, 0x55, 0x54, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x02, 0x55, 0x55, 0x55, 0x00, 0x04, 0x00, 0x80, 0x28, 0x00, 0x00, 0xa0, 0x02, 0x01, 0x15, 0x55, 0x10, 0x04, 0x55, 0x80, 0x28, 0x00, 0x00, 0xa0, 0x02, 0x01, 0x15, 0x55, 0x01, 0x55, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x02, 0x55, 0x55, 0x55, 0x01, 0x01, 0x00, 0x80, 0xaa, 0xaa, 0xaa, 0xa8, 0x02, 0x00, 0x04, 0x01, 0x01, 0x55, 0x00, 0x82, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x04, 0x01, 0x00, 0x41, 0x00, 0x82, 0xaa, 0xaa, 0xaa, 0xaa, 0x02, 0x00, 0x04, 0x01, 0x55, 0x5a, 0xa5, 0x80, 0x95, 0x95, 0x80, 0x00, 0x02, 0x55, 0x54, 0x01, 0x00, 0x25, 0x58, 0x80, 0x95, 0x95, 0x85, 0x54, 0x0a, 0xaa, 0xa8, 0x01, 0x00, 0x26, 0x98, 0x80, 0x95, 0x95, 0x85, 0x54, 0x08, 0x00, 0x09, 0x55, 0x00, 0x25, 0x58, 0x80, 0x95, 0x95, 0xaa, 0xaa, 0x08, 0x88, 0x88, 0x00, 0x00, 0x20, 0x08, 0x95, 0x95, 0x95, 0x80, 0x02, 0x58, 0x88, 0x88, 0x00, 0xaa, 0xa0, 0x0a, 0x95, 0x95, 0x95, 0x80, 0x02, 0x58, 0x00, 0x0a, 0xaa, 0x04, 0x20, 0x08, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa9, 0x55, 0x58, 0x00, 0x00, 0x0a, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xaa, 0xa9, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0x42, 0x82, 0x20, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa6, 0x86, 0x26, 0x62, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x45, 0x86, 0x24, 0xa4, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xa4, 0xa1, 0x61, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x61, 0x40, 0xa2, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0xaa, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa9, 0x55, 0x69, 0x55, 0x6a, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x9a, 0xa9, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x59, 0x59, 0x6a, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x98, 0x49, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x95, 0x55, 0xaa, 0x95, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa5, 0x56, 0xaa, 0x40, 0x68, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa8, 0x0a, 0xa5, 0x55, 0x58, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa9, 0x5a, 0xa5, 0x55, 0x58, 0x00, 0x95, 0x5a, 0x69, 0xa5, 0x56, 0x02, 0xa5, 0x96, 0xa9, 0x69, 0x68, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x96, 0x5a, 0x69, 0xa5, 0x96, 0x54, 0x54, 0x54, 0x54, 0x54, 0x55, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x54, 0x54, 0x54, 0x54, 0x54, 0x55, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x30, 0x1f, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x15, 0x00, 0x00, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x55, 0x00, 0x01, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x40, 0x51, 0x55, 0x55, 0x15, 0x54, 0x00, 0x00, 0x15, 0x54, 0x55, 0x55, 0x45, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x40, 0x00, 0x44, 0x11, 0x10, 0x11, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x44, 0x04, 0x44, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x40, 0x00, 0x44, 0x15, 0x05, 0x41, 0x50, 0x05, 0x55, 0x55, 0x50, 0x05, 0x41, 0x50, 0x54, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x50, 0x40, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x50, 0x40, 0x01, 0x00, 0x01, 0x00, 0x17, 0xfc, 0x3f, 0xfc, 0x00, 0x43, 0xff, 0xc0, 0x01, 0x00, 0x01, 0x00, 0x1f, 0xf4, 0xff, 0xd4, 0x00, 0x4f, 0xfc, 0x40, 0x01, 0x55, 0x55, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x40, 0x01, 0x11, 0x11, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x40, 0x01, 0x00, 0x01, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xc0, 0x01, 0x05, 0x41, 0x00, 0xf0, 0xfc, 0x03, 0xff, 0xff, 0x00, 0x00, 0xc0, 0x01, 0x05, 0x41, 0x00, 0xf0, 0xf3, 0x0c, 0x71, 0xc7, 0x33, 0x30, 0xc0, 0xaa, 0xaa, 0xaa, 0xaa, 0xf0, 0xf3, 0x0d, 0x75, 0xd7, 0x33, 0x30, 0xea, 0x55, 0x55, 0x55, 0x55, 0xf0, 0xfc, 0x0d, 0x34, 0xd3, 0x33, 0x30, 0xd5, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x0d, 0x34, 0xc3, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x03, 0xff, 0xff, 0xaa, 0xaa, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 0xc0, 0x00, 0xfc, 0x0f, 0xc0, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x3a, 0xbf, 0xfa, 0xab, 0xff, 0xbf, 0xfb, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0xff, 0xff, 0xcf, 0xfc, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf0, 0x03, 0xff, 0x3f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xc0, 0x00, 0xfc, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x55, 0x51, 0x55, 0x55, 0x15, 0x54, 0x00, 0x00, 0x15, 0x10, 0x00, 0x00, 0x40, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x40, 0x11, 0x10, 0x11, 0x10, 0x04, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x40, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x15, 0x55, 0x55, 0x40, 0x15, 0x05, 0x41, 0x50, 0x05, 0x55, 0x55, 0x50, 0x00, 0x00, 0x00, 0x00, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf5, 0xff, 0xf0, 0x00, 0x0f, 0xff, 0x00, 0x50, 0x50, 0x50, 0x50, 0x3f, 0xc3, 0xff, 0x00, 0x14, 0x3f, 0xf4, 0x14, 0x55, 0x50, 0x55, 0x50, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x54, 0x55, 0x50, 0x55, 0x50, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x54, 0x55, 0x55, 0x55, 0x53, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x54, 0x40, 0x10, 0x40, 0x13, 0xc3, 0xf0, 0x0f, 0xff, 0xfc, 0x00, 0x03, 0x04, 0x50, 0x50, 0x50, 0x53, 0xc3, 0xcc, 0x31, 0xc7, 0x1c, 0xcc, 0xc3, 0x14, 0x40, 0x10, 0x40, 0x13, 0xc3, 0xcc, 0x35, 0xd7, 0x5c, 0xcc, 0xc3, 0x04, 0xaa, 0xaa, 0xaa, 0xab, 0xc3, 0xf0, 0x34, 0xd3, 0x4c, 0xcc, 0xc3, 0xaa, 0x55, 0x55, 0x55, 0x57, 0x00, 0x00, 0x34, 0xd3, 0x0c, 0x00, 0x03, 0x55, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x0f, 0xff, 0xfe, 0xaa, 0xab, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x3f, 0x00, 0x03, 0xf0, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xea, 0xff, 0xea, 0xaf, 0xfe, 0xff, 0xec, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf3, 0xff, 0xff, 0x3f, 0xf3, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x0f, 0xfc, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x03, 0xf0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xfd, 0x7d, 0x7f, 0x5d, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x5d, 0xd5, 0xd7, 0x75, 0xdd, 0xd5, 0x55, 0x55, 0x55, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x30, 0xcc, 0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0xc0, 0xff, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xc0, 0xc3, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0x3f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xfc, 0x3f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x03, 0xc0, 0x30, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0xf3, 0xff, 0xff, 0xcf, 0x00, 0x00, 0x0f, 0xf0, 0x70, 0x0f, 0x55, 0x55, 0xc3, 0x0c, 0x30, 0xc3, 0x55, 0x55, 0xf0, 0x0d, 0xc3, 0x30, 0xd5, 0xff, 0x7c, 0xcf, 0xf3, 0x3d, 0xff, 0x57, 0x0c, 0xc3, 0xc0, 0x3f, 0x5f, 0x03, 0x57, 0xcf, 0xf3, 0xd5, 0xc0, 0xf5, 0xfc, 0x03, 0xc0, 0x30, 0xdc, 0x0d, 0x5f, 0xff, 0xff, 0xf5, 0x70, 0x37, 0x0c, 0x03, 0x7f, 0xff, 0x5f, 0xf5, 0x5f, 0x55, 0x55, 0xf5, 0x5f, 0xf5, 0xff, 0xfd, 0x30, 0x1f, 0xa4, 0x00, 0xa4, 0x01, 0x90, 0x00, 0x64, 0x06, 0x40, 0x1a, 0x00, 0x16, 0xa9, 0x40, 0x09, 0x00, 0x40, 0x00, 0x10, 0x01, 0x00, 0x60, 0x01, 0x6a, 0x2a, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xaa, 0x00, 0xa5, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x01, 0x6a, 0x80, 0x00, 0x01, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x30, 0xc0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x00, 0x05, 0x94, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x15, 0x56, 0xa5, 0x55, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x15, 0x40, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x29, 0x50, 0x15, 0x68, 0x00, 0x40, 0x07, 0xf0, 0x0f, 0xc0, 0x10, 0x00, 0x0a, 0xa5, 0x6a, 0x80, 0x01, 0x00, 0x1f, 0xfc, 0x3f, 0xf0, 0x04, 0x00, 0x00, 0xaa, 0xa8, 0x00, 0x15, 0x00, 0x1f, 0xff, 0xff, 0xf0, 0x05, 0x40, 0x00, 0x0a, 0xa0, 0x00, 0x04, 0x00, 0x5c, 0x00, 0x00, 0x30, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xf0, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xc0, 0x33, 0x00, 0x00, 0xcc, 0x03, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x30, 0x03, 0xc0, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x0c, 0x30, 0x03, 0xc0, 0x0c, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x3c, 0x03, 0xc0, 0x3c, 0xff, 0xc0, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0xc3, 0xff, 0xff, 0xc3, 0x00, 0x00, 0x0f, 0xf0, 0x30, 0x0c, 0x00, 0x00, 0xcc, 0x30, 0x0c, 0x33, 0x00, 0x00, 0x30, 0x0c, 0xc3, 0x0f, 0x00, 0x00, 0x3f, 0x3f, 0xfc, 0xfc, 0x00, 0x00, 0xf0, 0xc3, 0xc0, 0x30, 0xc0, 0x00, 0x03, 0x3f, 0xfc, 0xc0, 0x00, 0x03, 0x0c, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0xfc, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x3f, 0xfc, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x30, 0x30, 0xc0, 0x00, 0x00, 0x3c, 0x3c, 0x00, 0x00, 0x03, 0x0c, 0x0c, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x0c, 0x30, 0x00, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xfd, 0x7d, 0x7f, 0x5d, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x5d, 0xd5, 0xd7, 0x75, 0xdd, 0xd5, 0x55, 0x55, 0x55, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x30, 0xcc, 0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0xc0, 0xff, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xc0, 0xc3, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x70, 0x0f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xf0, 0x0d, 0xc3, 0x30, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x0c, 0xc3, 0xc0, 0x3f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfc, 0x03, 0xc0, 0x30, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x0c, 0x03, 0x7f, 0xff, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xfd, 0x30, 0x1f, 0xa4, 0x00, 0xa4, 0x01, 0x90, 0x00, 0x64, 0x06, 0x40, 0x1a, 0x00, 0x16, 0xa9, 0x40, 0x09, 0x00, 0x40, 0x00, 0x10, 0x01, 0x00, 0x60, 0x01, 0x6a, 0x2a, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xaa, 0x00, 0xa5, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x01, 0x6a, 0x80, 0x00, 0x01, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x30, 0xc0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x00, 0x05, 0x94, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x15, 0x56, 0xa5, 0x55, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x15, 0x40, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x29, 0x50, 0x15, 0x68, 0x00, 0x40, 0x04, 0x00, 0x04, 0x00, 0x10, 0x00, 0x0a, 0xa5, 0x6a, 0x80, 0x01, 0x00, 0x14, 0x00, 0x05, 0x00, 0x04, 0x00, 0x00, 0xaa, 0xa8, 0x00, 0x15, 0x00, 0x15, 0x00, 0x15, 0x00, 0x05, 0x40, 0x00, 0x0a, 0xa0, 0x00, 0x04, 0x00, 0x54, 0x00, 0x05, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x30, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0c, 0xc3, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xc3, 0xc0, 0x30, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x30, 0x30, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x0c, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xfc, 0x00, 0xc3, 0x0f, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xc3, 0x00, 0xc3, 0x30, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xcc, 0xc3, 0x00, 0xff, 0x30, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xfc, 0x00, 0xc3, 0x30, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xc0, 0x00, 0xc3, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x3f, 0x0f, 0xcf, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0xcc, 0x0c, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0xcf, 0xcf, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0x0f, 0xcf, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x30, 0xcc, 0x33, 0x0c, 0xfc, 0xfc, 0x00, 0x00, 0xc0, 0x00, 0x00, 0xc3, 0x30, 0xcf, 0x33, 0xcc, 0xc0, 0xc3, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc3, 0x30, 0xcc, 0xf3, 0x3c, 0xfc, 0xc3, 0x00, 0x00, 0xfc, 0x00, 0x00, 0xfc, 0x30, 0xcc, 0x33, 0x0c, 0xc0, 0xfc, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc3, 0x0f, 0x0c, 0x33, 0x0c, 0xfc, 0xc3, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x1f, 0x05, 0x55, 0x55, 0x55, 0x55, 0x55, 0x54, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x05, 0x54, 0x55, 0x45, 0x51, 0x10, 0x00, 0x04, 0x04, 0x55, 0x44, 0x51, 0x11, 0x55, 0x44, 0x04, 0x44, 0x44, 0x51, 0x11, 0x00, 0x44, 0x04, 0x44, 0x44, 0x51, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x00, 0x00, 0x00, 0x05, 0x41, 0x10, 0x00, 0x00, 0x00, 0x00, 0x04, 0x41, 0x10, 0x00, 0x00, 0x10, 0x55, 0x05, 0x41, 0x10, 0x54, 0x00, 0x55, 0x45, 0x10, 0x11, 0x11, 0x01, 0x40, 0x55, 0x54, 0x10, 0x11, 0x11, 0x00, 0x10, 0x55, 0x54, 0x15, 0x51, 0x11, 0x41, 0x11, 0x51, 0x10, 0x04, 0x41, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x50, 0x50, 0x00, 0x00, 0x10, 0x01, 0x10, 0x55, 0x50, 0x55, 0x00, 0x55, 0x01, 0x10, 0x44, 0x51, 0x00, 0x51, 0x00, 0x41, 0x10, 0x40, 0x11, 0x04, 0x41, 0x11, 0x41, 0x10, 0x15, 0x41, 0x00, 0x41, 0x00, 0x41, 0x10, 0x10, 0x41, 0x00, 0x40, 0x41, 0x01, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x55, 0x55, 0x55, 0x55, 0x55, 0x41, 0x10, 0x40, 0x00, 0x00, 0x00, 0x00, 0x41, 0x10, 0x55, 0x55, 0x55, 0x55, 0x55, 0x41, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x15, 0x50, 0x00, 0x00, 0x00, 0x01, 0x55, 0x12, 0x0c, 0x57, 0xf5, 0x7d, 0x55, 0x50, 0x5f, 0xfd, 0xff, 0x55, 0x50, 0x5f, 0xff, 0xff, 0x55, 0x50, 0x5f, 0xff, 0xff, 0xd5, 0x50, 0x7c, 0x00, 0x00, 0xd5, 0x50, 0x70, 0x0f, 0xc3, 0xd5, 0x50, 0x70, 0x33, 0xc3, 0xd5, 0x50, 0x70, 0x33, 0xc3, 0xd5, 0x50, 0x70, 0x0f, 0xc3, 0xd5, 0x50, 0x5c, 0x00, 0x0f, 0x55, 0x50, 0x57, 0xff, 0xfd, 0x55, 0x50, 0x5c, 0x3c, 0x33, 0x55, 0x50, 0x12, 0x0c, 0x55, 0xfd, 0x5f, 0x55, 0x50, 0x57, 0xff, 0x7f, 0xd5, 0x50, 0x57, 0xff, 0xff, 0xd5, 0x50, 0x57, 0xff, 0xff, 0xf5, 0x50, 0x5f, 0x00, 0x00, 0x35, 0x50, 0x5c, 0x03, 0xc0, 0x35, 0x50, 0x5c, 0x0c, 0x30, 0xf5, 0x50, 0x5c, 0x00, 0x00, 0x35, 0x50, 0x5c, 0x0c, 0x0f, 0xf5, 0x50, 0x57, 0x33, 0x0f, 0xd5, 0x50, 0x55, 0xf3, 0xff, 0x35, 0x50, 0x55, 0xc3, 0xc3, 0xf5, 0x50, 0x12, 0x0c, 0x5f, 0xd5, 0x7f, 0xff, 0xf0, 0x7f, 0xf5, 0xff, 0x00, 0x30, 0x7f, 0xff, 0xff, 0x00, 0x30, 0x7f, 0xff, 0xff, 0x00, 0x30, 0x70, 0x00, 0x03, 0x00, 0x30, 0xc3, 0xf0, 0x3f, 0x00, 0x30, 0xcc, 0xf0, 0xcf, 0x00, 0x30, 0xcc, 0xf0, 0xcf, 0x00, 0x30, 0xc3, 0xf0, 0x3f, 0xff, 0xf0, 0x70, 0x0f, 0x00, 0xcd, 0x50, 0x5f, 0xff, 0xff, 0x35, 0x50, 0x70, 0x30, 0x3c, 0xd5, 0x50, 0x12, 0x0c, 0x55, 0xfd, 0x57, 0xd5, 0x50, 0x57, 0xff, 0xdf, 0xf5, 0x50, 0x57, 0xff, 0xff, 0xfd, 0x50, 0x55, 0xff, 0xff, 0xfd, 0x50, 0x57, 0xc0, 0x00, 0x0d, 0x50, 0x57, 0x00, 0x00, 0x0d, 0x50, 0x57, 0x00, 0x00, 0x0d, 0x50, 0x57, 0x0f, 0xf0, 0x0d, 0x50, 0x57, 0x00, 0x00, 0xcd, 0x50, 0x55, 0xc0, 0x03, 0x35, 0x50, 0x55, 0x7f, 0xff, 0xd5, 0x50, 0x55, 0xc3, 0xc3, 0xd5, 0x50, 0x12, 0x0c, 0x57, 0xf5, 0x5f, 0xd5, 0x50, 0x5f, 0xfd, 0x7f, 0xf5, 0x50, 0x5f, 0xff, 0xff, 0xf5, 0x50, 0x5f, 0xff, 0xff, 0xf5, 0x50, 0x5c, 0x00, 0x00, 0x35, 0x50, 0x70, 0x00, 0x00, 0x0d, 0x50, 0x70, 0x30, 0x0c, 0x0d, 0x50, 0x70, 0xc0, 0x03, 0x0d, 0x50, 0x70, 0x03, 0xc0, 0x0d, 0x50, 0x5c, 0x0f, 0xf0, 0x35, 0x50, 0x57, 0xff, 0xff, 0xd5, 0x50, 0x55, 0xcc, 0x33, 0x55, 0x50, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfa, 0xaa, 0xab, 0xc0, 0xff, 0xe5, 0x55, 0x5a, 0xc0, 0xff, 0xe5, 0x55, 0x5a, 0xc0, 0xff, 0x95, 0x55, 0x66, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0xaa, 0xaa, 0xab, 0xc0, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfe, 0xaa, 0xaa, 0xc0, 0xff, 0xfe, 0x55, 0x56, 0xc0, 0xff, 0xfe, 0x55, 0x56, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xea, 0xaa, 0xaa, 0xc0, 0xff, 0xea, 0xaa, 0xaa, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0xaa, 0xaa, 0xab, 0xc0, 0x08, 0x08, 0x7f, 0xf5, 0xff, 0xfd, 0xc3, 0x0d, 0xff, 0xfd, 0xff, 0xfd, 0xfc, 0xfd, 0x7f, 0xf5, 0x77, 0x75, 0x10, 0x03, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xc0, 0x03, 0x03, 0xff, 0xff, 0xff, 0xff, 0x10, 0x03, 0x55, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x03, 0x55, 0x55, 0xff, 0xff, 0x55, 0x08, 0x08, 0x55, 0x75, 0x55, 0x75, 0x55, 0x75, 0x5f, 0x75, 0x70, 0xf5, 0x70, 0xd5, 0x5f, 0x55, 0x55, 0x55, 0x08, 0x08, 0x55, 0x75, 0x55, 0x75, 0x55, 0x75, 0x5f, 0x75, 0x7f, 0xf5, 0x7f, 0xd5, 0x5f, 0x55, 0x55, 0x55, 0x08, 0x08, 0x55, 0xd5, 0x55, 0xf5, 0x55, 0xfd, 0x7d, 0xdd, 0xff, 0xd5, 0xff, 0x55, 0x7d, 0x55, 0x55, 0x55, 0x08, 0x08, 0x5f, 0xfd, 0x5d, 0x5d, 0x5d, 0x5d, 0x5d, 0x5d, 0xfd, 0xfd, 0xfd, 0xfd, 0xf5, 0xf5, 0x55, 0x55, 0x01, 0x01, 0x00, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x7f, 0xfd, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x5f, 0xfd, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x7f, 0xfd, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x5f, 0xfd, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x7f, 0xfd, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0x03, 0x5f, 0xfd, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x08, 0x08, 0x50, 0x05, 0x43, 0xc1, 0x00, 0x00, 0x30, 0xcc, 0x33, 0x0c, 0x00, 0x00, 0x43, 0xc1, 0x50, 0x05, 0x08, 0x08, 0xc0, 0x03, 0x33, 0xcc, 0x00, 0x30, 0x33, 0x0c, 0x30, 0xcc, 0x0c, 0x00, 0x33, 0xcc, 0xc0, 0x03, 0x08, 0x08, 0x57, 0xd5, 0x5c, 0x35, 0x5c, 0x35, 0xdc, 0x37, 0xd7, 0xd7, 0xdf, 0xf7, 0xfd, 0x7f, 0xf7, 0xdf, 0x04, 0x1f, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x02, 0x05, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0x06, 0x20, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0x20, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf7, 0xff, 0x5f, 0x5f, 0xd7, 0xff, 0x75, 0x5d, 0x55, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x57, 0xd5, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x55, 0x75, 0x75, 0x7f, 0xdf, 0xd5, 0x75, 0x75, 0x55, 0x75, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x55, 0x5f, 0xd5, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x08, 0x7f, 0x5f, 0x57, 0xd7, 0x57, 0xd5, 0x75, 0xdd, 0x77, 0x57, 0xdf, 0x75, 0xdd, 0x77, 0x57, 0xd7, 0x75, 0xdf, 0xf7, 0x55, 0x7d, 0x5f, 0x5d, 0x77, 0xf7, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x0c, 0x7f, 0x5f, 0x5d, 0x5d, 0xfd, 0xd5, 0x75, 0xdf, 0x7d, 0xd5, 0xdf, 0x75, 0xdf, 0xfd, 0xfd, 0xd7, 0x7f, 0xdd, 0xdd, 0xd5, 0x7f, 0x75, 0xdd, 0x5d, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7d, 0x75, 0x77, 0xf7, 0xf5, 0xd7, 0x75, 0x77, 0x57, 0x5d, 0xd7, 0x5d, 0xd7, 0xf7, 0x5d, 0xd7, 0x5d, 0xd7, 0x57, 0xf5, 0x7d, 0x57, 0x57, 0xf7, 0x5d, 0x55, 0x55, 0x55, 0x55, 0x55, 0x20, 0x0c, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xff, 0x55, 0xc3, 0x7d, 0x55, 0x55, 0x55, 0x70, 0x00, 0xd5, 0x70, 0xff, 0x55, 0x55, 0x55, 0xc0, 0x00, 0x35, 0x7c, 0x3f, 0xd5, 0x55, 0x57, 0x00, 0x03, 0x0d, 0x5f, 0xff, 0xff, 0xff, 0xfc, 0x03, 0x00, 0x0d, 0x70, 0x00, 0x03, 0xc0, 0x00, 0x00, 0x3f, 0xfd, 0x7f, 0xff, 0xfc, 0x30, 0x00, 0x00, 0xc0, 0x03, 0xc0, 0x00, 0x03, 0x30, 0x00, 0x03, 0x0f, 0xfc, 0xc0, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc0, 0x03, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x01, 0x01, 0x00, 0x10, 0x10, 0x55, 0x7d, 0x55, 0xf5, 0x55, 0xc3, 0x57, 0x0d, 0x55, 0xc0, 0xdc, 0x0d, 0x55, 0x70, 0xdc, 0x3d, 0x55, 0x5c, 0x30, 0x35, 0x55, 0x70, 0x00, 0xd5, 0x55, 0xc3, 0xfc, 0xd5, 0x55, 0xcf, 0xff, 0x35, 0x57, 0x0f, 0xff, 0x35, 0x57, 0x00, 0xfc, 0x35, 0x57, 0xc0 }; //uint8_t v[] = { 0x0a, 0xaa, 0x55, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x55, 0x03, 0x03, 0x03, 0x00, 0x00, 0x10, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0xc4, 0x00, 0x00, 0xdc, 0x00, 0x00, 0x0f, 0x01, 0x00, 0x91, 0x01, 0x00, 0x0d, 0x02, 0x00, 0x89, 0x02, 0x00, 0xd1, 0x02, 0x00, 0x1f, 0x06, 0x00, 0x67, 0x0f, 0x00, 0x67, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x12, 0x00, 0xa7, 0x12, 0x00, 0x0d, 0x13, 0x00, 0x73, 0x13, 0x00, 0xd9, 0x13, 0x00, 0x3f, 0x14, 0x00, 0xa5, 0x14, 0x00, 0x0b, 0x15, 0x00, 0x71, 0x15, 0x00, 0xd7, 0x15, 0x00, 0x3d, 0x16, 0x00, 0xa3, 0x16, 0x00, 0x09, 0x17, 0x00, 0x6f, 0x17, 0x00, 0xd5, 0x17, 0x00, 0x3b, 0x18, 0x00, 0xa1, 0x18, 0x00, 0x07, 0x19, 0x00, 0x6d, 0x19, 0x00, 0xd3, 0x19, 0x00, 0x39, 0x1a, 0x00, 0x9f, 0x1a, 0x00, 0x05, 0x1b, 0x00, 0x6b, 0x1b, 0x00, 0xd1, 0x1b, 0x00, 0x37, 0x1c, 0x00, 0x9d, 0x1c, 0x00, 0x13, 0x1e, 0x00, 0x89, 0x1f, 0x00, 0xff, 0x20, 0x00, 0x75, 0x22, 0x00, 0xeb, 0x23, 0x00, 0x61, 0x25, 0x00, 0xd7, 0x26, 0x00, 0x4d, 0x28, 0x00, 0xeb, 0x28, 0x00, 0x89, 0x29, 0x00, 0x64, 0x2a, 0x00, 0xa2, 0x2a, 0x00, 0xe0, 0x2a, 0x00, 0x1e, 0x2b, 0x00, 0x5c, 0x2b, 0x00, 0xce, 0x00, 0x00, 0xf1, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x44, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};// 0x70, 0x2c, 0x00, 0x82, 0x2c, 0x00, 0x90, 0x2c, 0x00, 0x9e, 0x2c, 0x00, 0xb0, 0x2c, 0x00, 0xc2, 0x2c, 0x00, 0xd4, 0x2c, 0x00, 0xe6, 0x2c, 0x00, 0xe9, 0x2c, 0x00, 0x1b, 0x2d, 0x00, 0x4d, 0x2d, 0x00, 0x7f, 0x2d, 0x00, 0xb1, 0x2d, 0x00, 0xe3, 0x2d, 0x00, 0x15, 0x2e, 0x00, 0x27, 0x2e, 0x00, 0x39, 0x2e, 0x00, 0x4b, 0x2e, 0x00, 0x6c, 0x2e, 0x00, 0x73, 0x2e, 0x00, 0xb5, 0x2e, 0x00, 0xf7, 0x2e, 0x00, 0x21, 0x2f, 0x00, 0x5f, 0x2f, 0x00, 0xc1, 0x2f, 0x00, 0x02, 0x00, 0x06, 0x03, 0x04, 0x09, 0x0a, 0x05, 0x08, 0x07, 0x00, 0x00, 0x58, 0x00, 0x00, 0x32, 0x00, 0x00, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x10, 0x00, 0x00, 0x08, 0x00, 0x00, 0x50, 0x04, 0x00, 0x30, 0x02, 0x00, 0x20, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00, 0x50, 0x08, 0x00, 0x50, 0x11, 0x00, 0x00, 0x00, 0x28, 0x00, 0x40, 0x15, 0x00, 0x60, 0x12, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x45, 0x00, 0x00, 0x35, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x22, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00, 0x22, 0x00, 0x00, 0x13, 0x00, 0x01, 0x00, 0x02, 0x00, 0x50, 0x01, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x04, 0xff, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x02, 0xff, 0x01, 0x01, 0x00, 0x1e, 0x01, 0x00, 0x03, 0xff, 0x01, 0x01, 0x00, 0x2d, 0x01, 0x00, 0x04, 0xfe, 0x01, 0x01, 0x00, 0x3c, 0x01, 0x00, 0x05, 0xfe, 0x01, 0x01, 0x00, 0x4b, 0x02, 0x00, 0x06, 0xfe, 0x02, 0x02, 0x00, 0x5a, 0x02, 0x00, 0x07, 0xfd, 0x02, 0x02, 0x00, 0x63, 0x02, 0x00, 0x08, 0xfd, 0x02, 0x02, 0x00, 0x64, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0x00, 0x02, 0x04, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x02, 0xff, 0x01, 0x01, 0x00, 0x0f, 0x01, 0x00, 0x03, 0xff, 0x01, 0x01, 0x00, 0x19, 0x01, 0x00, 0x04, 0xfe, 0x01, 0x01, 0x00, 0x23, 0x01, 0x00, 0x05, 0xfe, 0x01, 0x02, 0x00, 0x2d, 0x02, 0x00, 0x06, 0xfe, 0x02, 0x02, 0x00, 0x37, 0x02, 0x00, 0x07, 0xfd, 0x02, 0x02, 0x00, 0x40, 0x02, 0x00, 0x08, 0xfd, 0x02, 0x02, 0x00, 0x41, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xff, 0x03, 0x00, 0x10, 0xfc, 0x04, 0x04, 0x00, 0xc4, 0x2f, 0x00, 0xff, 0xff, 0xff, 0x06, 0x30, 0x00, 0x48, 0x30, 0x00, 0x8a, 0x30, 0x00, 0xcc, 0x30, 0x00, 0x0e, 0x31, 0x00, 0x50, 0x31, 0x00, 0x92, 0x31, 0x00, 0xd4, 0x31, 0x00, 0x16, 0x32, 0x00, 0xff, 0xff, 0xff, 0x58, 0x32, 0x00, 0xff, 0xff, 0xff, 0xba, 0x32, 0x00, 0x1c, 0x33, 0x00, 0x7e, 0x33, 0x00, 0xe0, 0x33, 0x00, 0x42, 0x34, 0x00, 0xa4, 0x34, 0x00, 0x06, 0x35, 0x00, 0x68, 0x35, 0x00, 0xca, 0x35, 0x00, 0xff, 0xff, 0xff, 0x2c, 0x36, 0x00, 0x3e, 0x36, 0x00, 0x80, 0x36, 0x00, 0xc2, 0x36, 0x00, 0x04, 0x37, 0x00, 0x46, 0x37, 0x00, 0x88, 0x37, 0x00, 0xca, 0x37, 0x00, 0x24, 0x38, 0x00, 0x9d, 0x38, 0x00, 0xf9, 0x38, 0x00, 0x7d, 0x39, 0x00, 0xd7, 0x39, 0x00, 0x50, 0x3a, 0x00, 0xac, 0x3a, 0x00, 0x30, 0x3b, 0x00, 0x72, 0x3b, 0x00, 0xb4, 0x3b, 0x00, 0xf6, 0x3b, 0x00, 0x38, 0x3c, 0x00, 0x7a, 0x3c, 0x00, 0xbc, 0x3c, 0x00, 0xfe, 0x3c, 0x00, 0x40, 0x3d, 0x00, 0x3a, 0x3e, 0x00, 0x34, 0x3f, 0x00, 0x2e, 0x40, 0x00, 0x28, 0x41, 0x00, 0x22, 0x42, 0x00, 0x98, 0x43, 0x00, 0xea, 0x43, 0x00, 0x3c, 0x44, 0x00, 0x8e, 0x44, 0x00, 0xe0, 0x44, 0x00, 0x32, 0x45, 0x00, 0x84, 0x45, 0x00, 0x7e, 0x46, 0x00, 0x78, 0x47, 0x00, 0xba, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0xfc, 0x47, 0x00, 0x76, 0x48, 0x00, 0xf0, 0x48, 0x00, 0x6a, 0x49, 0x00, 0xe4, 0x49, 0x00, 0x5e, 0x4a, 0x00, 0xd8, 0x4a, 0x00, 0x52, 0x4b, 0x00, 0xcc, 0x4b, 0x00, 0x46, 0x4c, 0x00, 0xc0, 0x4c, 0x00, 0x3a, 0x4d, 0x00, 0xb4, 0x4d, 0x00, 0x2e, 0x4e, 0x00, 0xa8, 0x4e, 0x00, 0x22, 0x4f, 0x00, 0x9c, 0x4f, 0x00, 0x16, 0x50, 0x00, 0x90, 0x50, 0x00, 0x0a, 0x51, 0x00, 0x84, 0x51, 0x00, 0xfe, 0x51, 0x00, 0x78, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0xf2, 0x52, 0x00, 0x6c, 0x53, 0x00, 0xe6, 0x53, 0x00, 0x60, 0x54, 0x00, 0xda, 0x54, 0x00, 0x54, 0x55, 0x00, 0xce, 0x55, 0x00, 0x48, 0x56, 0x00, 0xc2, 0x56, 0x00, 0x3c, 0x57, 0x00, 0xb6, 0x57, 0x00, 0x30, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0xaa, 0x58, 0x00, 0x24, 0x59, 0x00, 0x9e, 0x59, 0x00, 0x18, 0x5a, 0x00, 0x92, 0x5a, 0x00, 0x0c, 0x5b, 0x00, 0x86, 0x5b, 0x00, 0x00, 0x5c, 0x00, 0x7a, 0x5c, 0x00, 0xf4, 0x5c, 0x00, 0x6e, 0x5d, 0x00, 0xe8, 0x5d, 0x00, 0x62, 0x5e, 0x00, 0xdc, 0x5e, 0x00, 0x56, 0x5f, 0x00, 0xd0, 0x5f, 0x00, 0x4a, 0x60, 0x00, 0xc4, 0x60, 0x00, 0x3e, 0x61, 0x00, 0xb8, 0x61, 0x00, 0x32, 0x62, 0x00, 0xac, 0x62, 0x00, 0x26, 0x63, 0x00, 0xa0, 0x63, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x1a, 0x64, 0x00, 0x94, 0x64, 0x00, 0x0e, 0x65, 0x00, 0x88, 0x65, 0x00, 0x02, 0x66, 0x00, 0x7c, 0x66, 0x00, 0xf6, 0x66, 0x00, 0x70, 0x67, 0x00, 0xea, 0x67, 0x00, 0x64, 0x68, 0x00, 0xde, 0x68, 0x00, 0x58, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0xd2, 0x69, 0x00, 0x4c, 0x6a, 0x00, 0xc6, 0x6a, 0x00, 0x40, 0x6b, 0x00, 0xba, 0x6b, 0x00, 0x34, 0x6c, 0x00, 0xae, 0x6c, 0x00, 0x28, 0x6d, 0x00, 0xa2, 0x6d, 0x00, 0x1c, 0x6e, 0x00, 0x96, 0x6e, 0x00, 0x10, 0x6f, 0x00, 0x8a, 0x6f, 0x00, 0x04, 0x70, 0x00, 0x7e, 0x70, 0x00, 0xf8, 0x70, 0x00, 0x72, 0x71, 0x00, 0xec, 0x71, 0x00, 0x66, 0x72, 0x00, 0xe0, 0x72, 0x00, 0x5a, 0x73, 0x00, 0xd4, 0x73, 0x00, 0x4e, 0x74, 0x00, 0xc8, 0x74, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0x42, 0x75, 0x00, 0xbc, 0x75, 0x00, 0x36, 0x76, 0x00, 0xb0, 0x76, 0x00, 0x2a, 0x77, 0x00, 0xa4, 0x77, 0x00, 0x1e, 0x78, 0x00, 0x98, 0x78, 0x00, 0x12, 0x79, 0x00, 0x8c, 0x79, 0x00, 0x06, 0x7a, 0x00, 0x80, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0xfa, 0x7a, 0x00, 0x74, 0x7b, 0x00, 0xe2, 0x7b, 0x00, 0x50, 0x7c, 0x00, 0xbe, 0x7c, 0x00, 0x2c, 0x7d, 0x00, 0x9a, 0x7d, 0x00, 0x08, 0x7e, 0x00, 0x76, 0x7e, 0x00, 0xe4, 0x7e, 0x00, 0x52, 0x7f, 0x00, 0xc0, 0x7f, 0x00, 0x2e, 0x80, 0x00, 0x9c, 0x80, 0x00, 0x0a, 0x81, 0x00, 0x78, 0x81, 0x00, 0xe6, 0x81, 0x00, 0x54, 0x82, 0x00, 0xc2, 0x82, 0x00, 0x30, 0x83, 0x00, 0x9e, 0x83, 0x00, 0x0c, 0x84, 0x00, 0x7a, 0x84, 0x00, 0xe8, 0x84, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0x56, 0x85, 0x00, 0xc4, 0x85, 0x00, 0x32, 0x86, 0x00, 0xa0, 0x86, 0x00, 0x0e, 0x87, 0x00, 0x7c, 0x87, 0x00, 0xea, 0x87, 0x00, 0x58, 0x88, 0x00, 0xc6, 0x88, 0x00, 0x34, 0x89, 0x00, 0xa2, 0x89, 0x00, 0x10, 0x8a, 0x00, 0x7e, 0x8a, 0x00, 0xec, 0x8a, 0x00, 0x2e, 0x8b, 0x00, 0xac, 0x8b, 0x00, 0x2a, 0x8c, 0x00, 0xa8, 0x8c, 0x00, 0x26, 0x8d, 0x00, 0xa4, 0x8d, 0x00, 0x22, 0x8e, 0x00, 0xa0, 0x8e, 0x00, 0x1e, 0x8f, 0x00, 0x60, 0x8f, 0x00, 0xa2, 0x8f, 0x00, 0xe4, 0x8f, 0x00, 0x13, 0x90, 0x00, 0x42, 0x90, 0x00, 0x65, 0x90, 0x00, 0x88, 0x90, 0x00, 0xab, 0x90, 0x00, 0xce, 0x90, 0x00, 0xf1, 0x90, 0x00, 0x57, 0x91, 0x00, 0xbd, 0x91, 0x00, 0x23, 0x92, 0x00, 0x89, 0x92, 0x00, 0xef, 0x92, 0x00, 0x55, 0x93, 0x00, 0xbb, 0x93, 0x00, 0x21, 0x94, 0x00, 0x87, 0x94, 0x00, 0xed, 0x94, 0x00, 0x53, 0x95, 0x00, 0xb9, 0x95, 0x00, 0x1f, 0x96, 0x00, 0x85, 0x96, 0x00, 0xeb, 0x96, 0x00, 0x51, 0x97, 0x00, 0xb7, 0x97, 0x00, 0x1d, 0x98, 0x00, 0x83, 0x98, 0x00, 0xe9, 0x98, 0x00, 0x4f, 0x99, 0x00, 0xb5, 0x99, 0x00, 0x1b, 0x9a, 0x00, 0x81, 0x9a, 0x00, 0xe7, 0x9a, 0x00, 0x4d, 0x9b, 0x00, 0xb3, 0x9b, 0x00, 0x19, 0x9c, 0x00, 0x7f, 0x9c, 0x00, 0xe5, 0x9c, 0x00, 0x4b, 0x9d, 0x00, 0xb1, 0x9d, 0x00, 0x17, 0x9e, 0x00, 0x7d, 0x9e, 0x00, 0xe3, 0x9e, 0x00, 0x49, 0x9f, 0x00, 0xaf, 0x9f, 0x00, 0x15, 0xa0, 0x00, 0x7b, 0xa0, 0x00, 0xe1, 0xa0, 0x00, 0x47, 0xa1, 0x00, 0xad, 0xa1, 0x00, 0x13, 0xa2, 0x00, 0x79, 0xa2, 0x00, 0xdf, 0xa2, 0x00, 0x45, 0xa3, 0x00, 0xab, 0xa3, 0x00, 0x11, 0xa4, 0x00, 0x77, 0xa4, 0x00, 0xdd, 0xa4, 0x00, 0x43, 0xa5, 0x00, 0xa9, 0xa5, 0x00, 0x0f, 0xa6, 0x00, 0x75, 0xa6, 0x00, 0xdb, 0xa6, 0x00, 0x41, 0xa7, 0x00, 0xa7, 0xa7, 0x00, 0x0d, 0xa8, 0x00, 0x73, 0xa8, 0x00, 0xd9, 0xa8, 0x00, 0x3f, 0xa9, 0x00, 0xa5, 0xa9, 0x00, 0x0b, 0xaa, 0x00, 0x71, 0xaa, 0x00, 0xd7, 0xaa, 0x00, 0x3d, 0xab, 0x00, 0xa3, 0xab, 0x00, 0x09, 0xac, 0x00, 0x6f, 0xac, 0x00, 0xd5, 0xac, 0x00, 0x3b, 0xad, 0x00, 0xa1, 0xad, 0x00, 0x07, 0xae, 0x00, 0x6d, 0xae, 0x00, 0xd3, 0xae, 0x00, 0x39, 0xaf, 0x00, 0x9f, 0xaf, 0x00, 0x05, 0xb0, 0x00, 0x6b, 0xb0, 0x00, 0xd1, 0xb0, 0x00, 0x37, 0xb1, 0x00, 0x9d, 0xb1, 0x00, 0x03, 0xb2, 0x00, 0x69, 0xb2, 0x00, 0xcf, 0xb2, 0x00, 0x35, 0xb3, 0x00, 0x9b, 0xb3, 0x00, 0x01, 0xb4, 0x00, 0x67, 0xb4, 0x00, 0xcd, 0xb4, 0x00, 0x33, 0xb5, 0x00, 0x99, 0xb5, 0x00, 0xff, 0xb5, 0x00, 0x65, 0xb6, 0x00, 0xcb, 0xb6, 0x00, 0x31, 0xb7, 0x00, 0x97, 0xb7, 0x00, 0xfd, 0xb7, 0x00, 0x63, 0xb8, 0x00, 0xc9, 0xb8, 0x00, 0x2f, 0xb9, 0x00, 0x95, 0xb9, 0x00, 0xfb, 0xb9, 0x00, 0x61, 0xba, 0x00, 0xc7, 0xba, 0x00, 0x2d, 0xbb, 0x00, 0x93, 0xbb, 0x00, 0xf9, 0xbb, 0x00, 0x5f, 0xbc, 0x00, 0xc5, 0xbc, 0x00, 0x2b, 0xbd, 0x00, 0x91, 0xbd, 0x00, 0xf7, 0xbd, 0x00, 0x5d, 0xbe, 0x00, 0xc3, 0xbe, 0x00, 0x29, 0xbf, 0x00, 0x8f, 0xbf, 0x00, 0xf5, 0xbf, 0x00, 0x5b, 0xc0, 0x00, 0xc1, 0xc0, 0x00, 0x27, 0xc1, 0x00, 0x8d, 0xc1, 0x00, 0xf3, 0xc1, 0x00, 0x59, 0xc2, 0x00, 0xbf, 0xc2, 0x00, 0x25, 0xc3, 0x00, 0x8b, 0xc3, 0x00, 0xf1, 0xc3, 0x00, 0x57, 0xc4, 0x00, 0xbd, 0xc4, 0x00, 0x23, 0xc5, 0x00, 0x89, 0xc5, 0x00, 0xef, 0xc5, 0x00, 0x55, 0xc6, 0x00, 0xbb, 0xc6, 0x00, 0x21, 0xc7, 0x00, 0x87, 0xc7, 0x00, 0xed, 0xc7, 0x00, 0x53, 0xc8, 0x00, 0xb9, 0xc8, 0x00, 0x1f, 0xc9, 0x00, 0x85, 0xc9, 0x00, 0xeb, 0xc9, 0x00, 0x51, 0xca, 0x00, 0xb7, 0xca, 0x00, 0x1d, 0xcb, 0x00, 0x83, 0xcb, 0x00, 0xe9, 0xcb, 0x00, 0x4f, 0xcc, 0x00, 0xb5, 0xcc, 0x00, 0x1b, 0xcd, 0x00, 0x81, 0xcd, 0x00, 0xe7, 0xcd, 0x00, 0x4d, 0xce, 0x00, 0xb3, 0xce, 0x00, 0x19, 0xcf, 0x00, 0x7f, 0xcf, 0x00, 0xe5, 0xcf, 0x00, 0x4b, 0xd0, 0x00, 0xb1, 0xd0, 0x00, 0x17, 0xd1, 0x00, 0x7d, 0xd1, 0x00, 0xe3, 0xd1, 0x00, 0x49, 0xd2, 0x00, 0xaf, 0xd2, 0x00, 0x15, 0xd3, 0x00, 0x7b, 0xd3, 0x00, 0xe1, 0xd3, 0x00, 0x47, 0xd4, 0x00, 0xad, 0xd4, 0x00, 0x13, 0xd5, 0x00, 0x79, 0xd5, 0x00, 0xdf, 0xd5, 0x00, 0x45, 0xd6, 0x00, 0xab, 0xd6, 0x00, 0x11, 0xd7, 0x00, 0x77, 0xd7, 0x00, 0xdd, 0xd7, 0x00, 0x43, 0xd8, 0x00, 0xa9, 0xd8, 0x00, 0x0f, 0xd9, 0x00, 0x75, 0xd9, 0x00, 0xdb, 0xd9, 0x00, 0x41, 0xda, 0x00, 0xa7, 0xda, 0x00, 0x0d, 0xdb, 0x00, 0x73, 0xdb, 0x00, 0xd9, 0xdb, 0x00, 0x3f, 0xdc, 0x00, 0xa5, 0xdc, 0x00, 0x0b, 0xdd, 0x00, 0x71, 0xdd, 0x00, 0xd7, 0xdd, 0x00, 0x3d, 0xde, 0x00, 0xa3, 0xde, 0x00, 0x09, 0xdf, 0x00, 0x6f, 0xdf, 0x00, 0xd5, 0xdf, 0x00, 0x3b, 0xe0, 0x00, 0xa1, 0xe0, 0x00, 0x07, 0xe1, 0x00, 0x6d, 0xe1, 0x00, 0xd3, 0xe1, 0x00, 0x39, 0xe2, 0x00, 0x9f, 0xe2, 0x00, 0x05, 0xe3, 0x00, 0x6b, 0xe3, 0x00, 0xd1, 0xe3, 0x00, 0x37, 0xe4, 0x00, 0x9d, 0xe4, 0x00, 0x03, 0xe5, 0x00, 0x69, 0xe5, 0x00, 0xcf, 0xe5, 0x00, 0x35, 0xe6, 0x00, 0x9b, 0xe6, 0x00, 0x01, 0xe7, 0x00, 0x67, 0xe7, 0x00, 0xcd, 0xe7, 0x00, 0x33, 0xe8, 0x00, 0x99, 0xe8, 0x00, 0xff, 0xe8, 0x00, 0x65, 0xe9, 0x00, 0xcb, 0xe9, 0x00, 0x31, 0xea, 0x00, 0x97, 0xea, 0x00, 0xfd, 0xea, 0x00, 0x63, 0xeb, 0x00, 0xc9, 0xeb, 0x00, 0x2f, 0xec, 0x00, 0x95, 0xec, 0x00, 0xfb, 0xec, 0x00, 0x61, 0xed, 0x00, 0xc7, 0xed, 0x00, 0x2d, 0xee, 0x00, 0x93, 0xee, 0x00, 0xf9, 0xee, 0x00, 0x5f, 0xef, 0x00, 0xc5, 0xef, 0x00, 0x2b, 0xf0, 0x00, 0x91, 0xf0, 0x00, 0xf7, 0xf0, 0x00, 0x5d, 0xf1, 0x00, 0xc3, 0xf1, 0x00, 0x29, 0xf2, 0x00, 0x8f, 0xf2, 0x00, 0xf5, 0xf2, 0x00, 0x5b, 0xf3, 0x00, 0xc1, 0xf3, 0x00, 0x27, 0xf4, 0x00, 0x8d, 0xf4, 0x00, 0xf3, 0xf4, 0x00, 0x59, 0xf5, 0x00, 0xbf, 0xf5, 0x00, 0x25, 0xf6, 0x00, 0x8b, 0xf6, 0x00, 0xf1, 0xf6, 0x00, 0x57, 0xf7, 0x00, 0xbd, 0xf7, 0x00, 0x23, 0xf8, 0x00, 0x89, 0xf8, 0x00, 0xef, 0xf8, 0x00, 0x55, 0xf9, 0x00, 0xbb, 0xf9, 0x00, 0x21, 0xfa, 0x00, 0x87, 0xfa, 0x00, 0xed, 0xfa, 0x00, 0x53, 0xfb, 0x00, 0xb9, 0xfb, 0x00, 0x1f, 0xfc, 0x00, 0x85, 0xfc, 0x00, 0xeb, 0xfc, 0x00, 0x51, 0xfd, 0x00, 0xb7, 0xfd, 0x00, 0x1d, 0xfe, 0x00, 0x83, 0xfe, 0x00, 0xe9, 0xfe, 0x00, 0x4f, 0xff, 0x00, 0xb5, 0xff, 0x00, 0x1b, 0x00, 0x01, 0x81, 0x00, 0x01, 0xe7, 0x00, 0x01, 0x4d, 0x01, 0x01, 0xb3, 0x01, 0x01, 0x19, 0x02, 0x01, 0x7f, 0x02, 0x01, 0xe5, 0x02, 0x01, 0x4b, 0x03, 0x01, 0xb1, 0x03, 0x01, 0x17, 0x04, 0x01, 0x7d, 0x04, 0x01, 0xe3, 0x04, 0x01, 0x49, 0x05, 0x01, 0xaf, 0x05, 0x01, 0x15, 0x06, 0x01, 0x7b, 0x06, 0x01, 0xe1, 0x06, 0x01, 0x47, 0x07, 0x01, 0xad, 0x07, 0x01, 0x13, 0x08, 0x01, 0x79, 0x08, 0x01, 0xdf, 0x08, 0x01, 0x45, 0x09, 0x01, 0xab, 0x09, 0x01, 0x11, 0x0a, 0x01, 0x77, 0x0a, 0x01, 0xdd, 0x0a, 0x01, 0x43, 0x0b, 0x01, 0xa9, 0x0b, 0x01, 0x0f, 0x0c, 0x01, 0x75, 0x0c, 0x01, 0xdb, 0x0c, 0x01, 0x41, 0x0d, 0x01, 0xa7, 0x0d, 0x01, 0x0d, 0x0e, 0x01, 0x73, 0x0e, 0x01, 0xd9, 0x0e, 0x01, 0x3f, 0x0f, 0x01, 0xa5, 0x0f, 0x01, 0x0b, 0x10, 0x01, 0x71, 0x10, 0x01, 0xd7, 0x10, 0x01, 0x3d, 0x11, 0x01, 0xa3, 0x11, 0x01, 0x09, 0x12, 0x01, 0x6f, 0x12, 0x01, 0xd5, 0x12, 0x01, 0x3b, 0x13, 0x01, 0xa1, 0x13, 0x01, 0x07, 0x14, 0x01, 0x6d, 0x14, 0x01, 0xd3, 0x14, 0x01, 0x39, 0x15, 0x01, 0x9f, 0x15, 0x01, 0x05, 0x16, 0x01, 0x6b, 0x16, 0x01, 0xd1, 0x16, 0x01, 0x37, 0x17, 0x01, 0x9d, 0x17, 0x01, 0x03, 0x18, 0x01, 0x69, 0x18, 0x01, 0xcf, 0x18, 0x01, 0x35, 0x19, 0x01, 0x9b, 0x19, 0x01, 0x01, 0x1a, 0x01, 0x67, 0x1a, 0x01, 0xcd, 0x1a, 0x01, 0x33, 0x1b, 0x01, 0x99, 0x1b, 0x01, 0xff, 0x1b, 0x01, 0x65, 0x1c, 0x01, 0xcb, 0x1c, 0x01, 0x31, 0x1d, 0x01, 0x97, 0x1d, 0x01, 0xfd, 0x1d, 0x01, 0x63, 0x1e, 0x01, 0xc9, 0x1e, 0x01, 0x2f, 0x1f, 0x01, 0x95, 0x1f, 0x01, 0xfb, 0x1f, 0x01, 0x61, 0x20, 0x01, 0xc7, 0x20, 0x01, 0x2d, 0x21, 0x01, 0x93, 0x21, 0x01, 0xf9, 0x21, 0x01, 0x5f, 0x22, 0x01, 0xc5, 0x22, 0x01, 0x2b, 0x23, 0x01, 0x91, 0x23, 0x01, 0xf7, 0x23, 0x01, 0x5d, 0x24, 0x01, 0xc3, 0x24, 0x01, 0x29, 0x25, 0x01, 0x8f, 0x25, 0x01, 0xf5, 0x25, 0x01, 0x5b, 0x26, 0x01, 0xc1, 0x26, 0x01, 0x27, 0x27, 0x01, 0x8d, 0x27, 0x01, 0xf3, 0x27, 0x01, 0x59, 0x28, 0x01, 0xbf, 0x28, 0x01, 0x25, 0x29, 0x01, 0x8b, 0x29, 0x01, 0xf1, 0x29, 0x01, 0x57, 0x2a, 0x01, 0xbd, 0x2a, 0x01, 0x23, 0x2b, 0x01, 0x89, 0x2b, 0x01, 0xef, 0x2b, 0x01, 0x55, 0x2c, 0x01, 0xbb, 0x2c, 0x01, 0x21, 0x2d, 0x01, 0x87, 0x2d, 0x01, 0xed, 0x2d, 0x01, 0x53, 0x2e, 0x01, 0xb9, 0x2e, 0x01, 0x1f, 0x2f, 0x01, 0x85, 0x2f, 0x01, 0xeb, 0x2f, 0x01, 0x51, 0x30, 0x01, 0xb7, 0x30, 0x01, 0x1d, 0x31, 0x01, 0x83, 0x31, 0x01, 0xe9, 0x31, 0x01, 0x4f, 0x32, 0x01, 0xb5, 0x32, 0x01, 0x1b, 0x33, 0x01, 0x81, 0x33, 0x01, 0xe7, 0x33, 0x01, 0x4d, 0x34, 0x01, 0xb3, 0x34, 0x01, 0x19, 0x35, 0x01, 0x7f, 0x35, 0x01, 0xe5, 0x35, 0x01, 0x4b, 0x36, 0x01, 0xb1, 0x36, 0x01, 0x17, 0x37, 0x01, 0x7d, 0x37, 0x01, 0xe3, 0x37, 0x01, 0x49, 0x38, 0x01, 0xaf, 0x38, 0x01, 0x15, 0x39, 0x01, 0x7b, 0x39, 0x01, 0xe1, 0x39, 0x01, 0x47, 0x3a, 0x01, 0xad, 0x3a, 0x01, 0x13, 0x3b, 0x01, 0x79, 0x3b, 0x01, 0xdf, 0x3b, 0x01, 0x45, 0x3c, 0x01, 0xab, 0x3c, 0x01, 0x11, 0x3d, 0x01, 0x77, 0x3d, 0x01, 0xdd, 0x3d, 0x01, 0x43, 0x3e, 0x01, 0xa9, 0x3e, 0x01, 0x0f, 0x3f, 0x01, 0x75, 0x3f, 0x01, 0xdb, 0x3f, 0x01, 0x41, 0x40, 0x01, 0xa7, 0x40, 0x01, 0x0d, 0x41, 0x01, 0x73, 0x41, 0x01, 0xd9, 0x41, 0x01, 0x3f, 0x42, 0x01, 0xa5, 0x42, 0x01, 0x0b, 0x43, 0x01, 0x71, 0x43, 0x01, 0xd7, 0x43, 0x01, 0x3d, 0x44, 0x01, 0xa3, 0x44, 0x01, 0x09, 0x45, 0x01, 0x6f, 0x45, 0x01, 0xd5, 0x45, 0x01, 0x3b, 0x46, 0x01, 0xa1, 0x46, 0x01, 0x07, 0x47, 0x01, 0x6d, 0x47, 0x01, 0xd3, 0x47, 0x01, 0x39, 0x48, 0x01, 0x9f, 0x48, 0x01, 0x05, 0x49, 0x01, 0x6b, 0x49, 0x01, 0xd1, 0x49, 0x01, 0x37, 0x4a, 0x01, 0x9d, 0x4a, 0x01, 0x03, 0x4b, 0x01, 0x69, 0x4b, 0x01, 0xcf, 0x4b, 0x01, 0x35, 0x4c, 0x01, 0x9b, 0x4c, 0x01, 0x01, 0x4d, 0x01, 0x67, 0x4d, 0x01, 0xcd, 0x4d, 0x01, 0x33, 0x4e, 0x01, 0x99, 0x4e, 0x01, 0xff, 0x4e, 0x01, 0x65, 0x4f, 0x01, 0xcb, 0x4f, 0x01, 0x31, 0x50, 0x01, 0x97, 0x50, 0x01, 0xfd, 0x50, 0x01, 0x63, 0x51, 0x01, 0xc9, 0x51, 0x01, 0x2f, 0x52, 0x01, 0x95, 0x52, 0x01, 0xfb, 0x52, 0x01, 0x61, 0x53, 0x01, 0xc7, 0x53, 0x01, 0x2d, 0x54, 0x01, 0x93, 0x54, 0x01, 0xf9, 0x54, 0x01, 0x5f, 0x55, 0x01, 0xc5, 0x55, 0x01, 0x2b, 0x56, 0x01, 0x91, 0x56, 0x01, 0xf7, 0x56, 0x01, 0x5d, 0x57, 0x01, 0xc3, 0x57, 0x01, 0x29, 0x58, 0x01, 0x8f, 0x58, 0x01, 0xf5, 0x58, 0x01, 0x5b, 0x59, 0x01, 0xc1, 0x59, 0x01, 0x27, 0x5a, 0x01, 0x8d, 0x5a, 0x01, 0xf3, 0x5a, 0x01, 0x59, 0x5b, 0x01, 0xbf, 0x5b, 0x01, 0x25, 0x5c, 0x01, 0x8b, 0x5c, 0x01, 0xf1, 0x5c, 0x01, 0x57, 0x5d, 0x01, 0xbd, 0x5d, 0x01, 0x23, 0x5e, 0x01, 0x89, 0x5e, 0x01, 0xef, 0x5e, 0x01, 0x55, 0x5f, 0x01, 0xbb, 0x5f, 0x01, 0x21, 0x60, 0x01, 0x87, 0x60, 0x01, 0xed, 0x60, 0x01, 0x53, 0x61, 0x01, 0xb9, 0x61, 0x01, 0x1f, 0x62, 0x01, 0x85, 0x62, 0x01, 0xeb, 0x62, 0x01, 0x51, 0x63, 0x01, 0xb7, 0x63, 0x01, 0x1d, 0x64, 0x01, 0x83, 0x64, 0x01, 0xe9, 0x64, 0x01, 0x4f, 0x65, 0x01, 0xb5, 0x65, 0x01, 0x1b, 0x66, 0x01, 0x81, 0x66, 0x01, 0xe7, 0x66, 0x01, 0x4d, 0x67, 0x01, 0xb3, 0x67, 0x01, 0x19, 0x68, 0x01, 0x7f, 0x68, 0x01, 0xe5, 0x68, 0x01, 0x4b, 0x69, 0x01, 0xb1, 0x69, 0x01, 0x17, 0x6a, 0x01, 0x7d, 0x6a, 0x01, 0xe3, 0x6a, 0x01, 0x49, 0x6b, 0x01, 0xaf, 0x6b, 0x01, 0x15, 0x6c, 0x01, 0x7b, 0x6c, 0x01, 0xe1, 0x6c, 0x01, 0x47, 0x6d, 0x01, 0xad, 0x6d, 0x01, 0x13, 0x6e, 0x01, 0x79, 0x6e, 0x01, 0xdf, 0x6e, 0x01, 0x45, 0x6f, 0x01, 0xab, 0x6f, 0x01, 0x11, 0x70, 0x01, 0x77, 0x70, 0x01, 0xdd, 0x70, 0x01, 0x43, 0x71, 0x01, 0xa9, 0x71, 0x01, 0x0f, 0x72, 0x01, 0x75, 0x72, 0x01, 0xdb, 0x72, 0x01, 0x41, 0x73, 0x01, 0xa7, 0x73, 0x01, 0x0d, 0x74, 0x01, 0x73, 0x74, 0x01, 0xd9, 0x74, 0x01, 0x3f, 0x75, 0x01, 0xa5, 0x75, 0x01, 0x0b, 0x76, 0x01, 0x71, 0x76, 0x01, 0xd7, 0x76, 0x01, 0x3d, 0x77, 0x01, 0xa3, 0x77, 0x01, 0x09, 0x78, 0x01, 0x6f, 0x78, 0x01, 0xd5, 0x78, 0x01, 0x3b, 0x79, 0x01, 0xa1, 0x79, 0x01, 0x07, 0x7a, 0x01, 0x6d, 0x7a, 0x01, 0xd3, 0x7a, 0x01, 0x39, 0x7b, 0x01, 0x9f, 0x7b, 0x01, 0x05, 0x7c, 0x01, 0x6b, 0x7c, 0x01, 0xd1, 0x7c, 0x01, 0x37, 0x7d, 0x01, 0x9d, 0x7d, 0x01, 0x03, 0x7e, 0x01, 0x69, 0x7e, 0x01, 0xcf, 0x7e, 0x01, 0x35, 0x7f, 0x01, 0x9b, 0x7f, 0x01, 0x01, 0x80, 0x01, 0x67, 0x80, 0x01, 0xcd, 0x80, 0x01, 0x33, 0x81, 0x01, 0x99, 0x81, 0x01, 0xff, 0x81, 0x01, 0x65, 0x82, 0x01, 0xcb, 0x82, 0x01, 0x31, 0x83, 0x01, 0x97, 0x83, 0x01, 0xfd, 0x83, 0x01, 0x63, 0x84, 0x01, 0xc9, 0x84, 0x01, 0x2f, 0x85, 0x01, 0x95, 0x85, 0x01, 0xfb, 0x85, 0x01, 0x61, 0x86, 0x01, 0xc7, 0x86, 0x01, 0x2d, 0x87, 0x01, 0x93, 0x87, 0x01, 0xf9, 0x87, 0x01, 0x5f, 0x88, 0x01, 0xc5, 0x88, 0x01, 0x2b, 0x89, 0x01, 0x91, 0x89, 0x01, 0xf7, 0x89, 0x01, 0x5d, 0x8a, 0x01, 0xc3, 0x8a, 0x01, 0x29, 0x8b, 0x01, 0x8f, 0x8b, 0x01, 0xf5, 0x8b, 0x01, 0x5b, 0x8c, 0x01, 0xc1, 0x8c, 0x01, 0x27, 0x8d, 0x01, 0x8d, 0x8d, 0x01, 0xf3, 0x8d, 0x01, 0x59, 0x8e, 0x01, 0xbf, 0x8e, 0x01, 0x25, 0x8f, 0x01, 0x8b, 0x8f, 0x01, 0xf1, 0x8f, 0x01, 0x57, 0x90, 0x01, 0xbd, 0x90, 0x01, 0x23, 0x91, 0x01, 0x89, 0x91, 0x01, 0xef, 0x91, 0x01, 0x55, 0x92, 0x01, 0xbb, 0x92, 0x01, 0x21, 0x93, 0x01, 0x87, 0x93, 0x01, 0xed, 0x93, 0x01, 0x53, 0x94, 0x01, 0xb9, 0x94, 0x01, 0x1f, 0x95, 0x01, 0x85, 0x95, 0x01, 0xeb, 0x95, 0x01, 0x51, 0x96, 0x01, 0xb7, 0x96, 0x01, 0x1d, 0x97, 0x01, 0x83, 0x97, 0x01, 0xe9, 0x97, 0x01, 0x4f, 0x98, 0x01, 0xb5, 0x98, 0x01, 0x1b, 0x99, 0x01, 0x81, 0x99, 0x01, 0xe7, 0x99, 0x01, 0x4d, 0x9a, 0x01, 0xb3, 0x9a, 0x01, 0x19, 0x9b, 0x01, 0x7f, 0x9b, 0x01, 0xe5, 0x9b, 0x01, 0x4b, 0x9c, 0x01, 0xb1, 0x9c, 0x01, 0x17, 0x9d, 0x01, 0x7d, 0x9d, 0x01, 0xe3, 0x9d, 0x01, 0x49, 0x9e, 0x01, 0xaf, 0x9e, 0x01, 0x15, 0x9f, 0x01, 0x7b, 0x9f, 0x01, 0xe1, 0x9f, 0x01, 0x47, 0xa0, 0x01, 0xad, 0xa0, 0x01, 0x13, 0xa1, 0x01, 0x79, 0xa1, 0x01, 0xdf, 0xa1, 0x01, 0x45, 0xa2, 0x01, 0xab, 0xa2, 0x01, 0x11, 0xa3, 0x01, 0x77, 0xa3, 0x01, 0xdd, 0xa3, 0x01, 0x43, 0xa4, 0x01, 0xa9, 0xa4, 0x01, 0x0f, 0xa5, 0x01, 0x75, 0xa5, 0x01, 0xdb, 0xa5, 0x01, 0x41, 0xa6, 0x01, 0xa7, 0xa6, 0x01, 0x0d, 0xa7, 0x01, 0x73, 0xa7, 0x01, 0xd9, 0xa7, 0x01, 0x3f, 0xa8, 0x01, 0xa5, 0xa8, 0x01, 0x0b, 0xa9, 0x01, 0x71, 0xa9, 0x01, 0xd7, 0xa9, 0x01, 0x3d, 0xaa, 0x01, 0xa3, 0xaa, 0x01, 0x09, 0xab, 0x01, 0x6f, 0xab, 0x01, 0xd5, 0xab, 0x01, 0x3b, 0xac, 0x01, 0xa1, 0xac, 0x01, 0x07, 0xad, 0x01, 0x6d, 0xad, 0x01, 0xd3, 0xad, 0x01, 0x39, 0xae, 0x01, 0x9f, 0xae, 0x01, 0x05, 0xaf, 0x01, 0x6b, 0xaf, 0x01, 0xd1, 0xaf, 0x01, 0x37, 0xb0, 0x01, 0x9d, 0xb0, 0x01, 0x03, 0xb1, 0x01, 0x69, 0xb1, 0x01, 0xcf, 0xb1, 0x01, 0x35, 0xb2, 0x01, 0x9b, 0xb2, 0x01, 0x01, 0xb3, 0x01, 0x67, 0xb3, 0x01, 0xcd, 0xb3, 0x01, 0x33, 0xb4, 0x01, 0x99, 0xb4, 0x01, 0xff, 0xb4, 0x01, 0x65, 0xb5, 0x01, 0xcb, 0xb5, 0x01, 0x31, 0xb6, 0x01, 0x97, 0xb6, 0x01, 0xfd, 0xb6, 0x01, 0x63, 0xb7, 0x01, 0xc9, 0xb7, 0x01, 0x2f, 0xb8, 0x01, 0x95, 0xb8, 0x01, 0xfb, 0xb8, 0x01, 0x61, 0xb9, 0x01, 0xc7, 0xb9, 0x01, 0x2d, 0xba, 0x01, 0x93, 0xba, 0x01, 0xf9, 0xba, 0x01, 0x5f, 0xbb, 0x01, 0xc5, 0xbb, 0x01, 0x2b, 0xbc, 0x01, 0x91, 0xbc, 0x01, 0xf7, 0xbc, 0x01, 0x5d, 0xbd, 0x01, 0xc3, 0xbd, 0x01, 0x29, 0xbe, 0x01, 0x8f, 0xbe, 0x01, 0xf5, 0xbe, 0x01, 0x5b, 0xbf, 0x01, 0xc1, 0xbf, 0x01, 0x27, 0xc0, 0x01, 0x8d, 0xc0, 0x01, 0xf3, 0xc0, 0x01, 0x59, 0xc1, 0x01, 0xbf, 0xc1, 0x01, 0x25, 0xc2, 0x01, 0x8b, 0xc2, 0x01, 0xf1, 0xc2, 0x01, 0x57, 0xc3, 0x01, 0xbd, 0xc3, 0x01, 0x23, 0xc4, 0x01, 0x89, 0xc4, 0x01, 0xef, 0xc4, 0x01, 0x55, 0xc5, 0x01, 0xbb, 0xc5, 0x01, 0x21, 0xc6, 0x01, 0x87, 0xc6, 0x01, 0xed, 0xc6, 0x01, 0x53, 0xc7, 0x01, 0xb9, 0xc7, 0x01, 0x1f, 0xc8, 0x01, 0x85, 0xc8, 0x01, 0xeb, 0xc8, 0x01, 0x51, 0xc9, 0x01, 0xb7, 0xc9, 0x01, 0x1d, 0xca, 0x01, 0x83, 0xca, 0x01, 0xe9, 0xca, 0x01, 0x4f, 0xcb, 0x01, 0xb5, 0xcb, 0x01, 0x1b, 0xcc, 0x01, 0x1f, 0x04, 0x07, 0x04, 0x04, 0x02, 0x03, 0x10, 0x00, 0x00, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x81, 0xcc, 0x01, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x0a, 0x06, 0x00, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x93, 0xcf, 0x01, 0xeb, 0xd1, 0x01, 0xeb, 0xd1, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x67, 0xd4, 0x01, 0x33, 0xd8, 0x01, 0x33, 0xd8, 0x01, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x10, 0x00, 0x00, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x3b, 0xdc, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x05, 0xdf, 0x01, 0x1f, 0x00, 0x08, 0x00, 0x06, 0x00, 0x03, 0x0a, 0x06, 0x00, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x67, 0xe3, 0x01, 0x8f, 0xe5, 0x01, 0x8f, 0xe5, 0x01, 0x1e, 0x0b, 0x06, 0x04, 0x04, 0x03, 0x04, 0x0c, 0x04, 0x00, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x59, 0xe8, 0x01, 0x2f, 0xeb, 0x01, 0x2f, 0xeb, 0x01, 0x13, 0xf8, 0x01, 0x87, 0xf9, 0x01, 0x87, 0xf9, 0x01, 0x35, 0xee, 0x01, 0xa9, 0xf2, 0x01, 0xa9, 0xf2, 0x01, 0x35, 0xee, 0x01, 0xa9, 0xf2, 0x01, 0xa9, 0xf2, 0x01, 0x1e, 0x04, 0x0b, 0x04, 0x08, 0x02, 0x06, 0x04, 0x06, 0x06, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x01, 0xfb, 0x01, 0x77, 0x00, 0x02, 0xab, 0x05, 0x02, 0x18, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x0a, 0x06, 0x00, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0xd3, 0x07, 0x02, 0x3f, 0x0b, 0x02, 0x3f, 0x0b, 0x02, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x08, 0x04, 0x04, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0xb7, 0x11, 0x02, 0x21, 0x17, 0x02, 0x09, 0x1d, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x11, 0x0f, 0x02, 0xf1, 0x13, 0x02, 0xcd, 0x19, 0x02, 0x1f, 0x0b, 0x06, 0x08, 0x04, 0x06, 0x03, 0x03, 0x05, 0x08, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0xc1, 0x1f, 0x02, 0x25, 0x22, 0x02, 0x83, 0x24, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3c, 0xc3, 0xcc, 0xd5, 0x57, 0x3f, 0x03, 0xf0, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0x7c, 0x00, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x73, 0x30, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xf0, 0x3c, 0x03, 0x55, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0xff, 0x00, 0x03, 0x55, 0x55, 0xff, 0x00, 0x3d, 0x55, 0x55, 0xff, 0x00, 0xcd, 0x55, 0x55, 0xcf, 0xff, 0x0d, 0x55, 0x55, 0x73, 0x30, 0x3d, 0x55, 0x55, 0x73, 0xf0, 0xf5, 0x55, 0x55, 0x73, 0xf0, 0x35, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x7f, 0x55, 0x57, 0xff, 0x55, 0xff, 0xd5, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x0f, 0x00, 0xf0, 0xd5, 0x57, 0x30, 0xc3, 0x0c, 0xd5, 0x57, 0x00, 0x3c, 0x00, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x57, 0x3f, 0xff, 0xfc, 0xd5, 0x57, 0xf0, 0xc3, 0x0f, 0xd5, 0x55, 0x73, 0xff, 0xcd, 0x55, 0x55, 0xc3, 0xff, 0xc3, 0x55, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x03, 0x00, 0xc0, 0xd5, 0x57, 0x0c, 0x00, 0x30, 0xd5, 0x57, 0x00, 0x3c, 0x00, 0xd5, 0x55, 0xc0, 0xff, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xcc, 0xff, 0x33, 0x55, 0x55, 0xfc, 0xff, 0x3f, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x3f, 0x0f, 0xc3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x00, 0xf0, 0x0d, 0x55, 0x55, 0xff, 0x0f, 0xf5, 0x55, 0x57, 0x33, 0xfc, 0xcd, 0x55, 0x57, 0xf3, 0xfc, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x30, 0x00, 0x0c, 0xd5, 0x57, 0x0c, 0x00, 0x30, 0xd5, 0x57, 0x00, 0xff, 0x00, 0xd5, 0x5f, 0x03, 0xff, 0xc0, 0xf5, 0x5c, 0xc3, 0xff, 0xc3, 0x35, 0x5f, 0x3f, 0xff, 0xfc, 0xf5, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0xc3, 0xff, 0xc3, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x7f, 0x55, 0x57, 0xff, 0x55, 0xff, 0xd5, 0x57, 0xff, 0xff, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x03, 0x00, 0xc0, 0xd5, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x30, 0x3c, 0x0c, 0xd5, 0x55, 0xcc, 0x3c, 0x33, 0xd5, 0x55, 0xcc, 0x3c, 0x33, 0x55, 0x55, 0xc3, 0xc3, 0xc3, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0x70, 0xff, 0x0d, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xd7, 0xf5, 0x55, 0x55, 0x5f, 0x55, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x5c, 0x3f, 0xff, 0xc3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x55, 0xff, 0xff, 0xf5, 0x55, 0x55, 0xc0, 0x00, 0x35, 0x55, 0x57, 0x30, 0x00, 0xcd, 0x55, 0x57, 0xf0, 0x00, 0xfd, 0x55, 0x55, 0x70, 0x00, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0x55, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0x70, 0x00, 0x3d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x70, 0x0c, 0xd5, 0x55, 0x57, 0xc0, 0xfc, 0xd5, 0x55, 0x55, 0xf0, 0x3f, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0x57, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0xcf, 0x0f, 0x55, 0x55, 0xc0, 0x3f, 0x0f, 0x55, 0x55, 0x70, 0x00, 0x3d, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x30, 0xcd, 0x55, 0x55, 0xfc, 0x3f, 0xf5, 0x55, 0x55, 0x70, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x5f, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x70, 0x3f, 0xf5, 0x55, 0x55, 0xc0, 0x0f, 0xf5, 0x55, 0x7f, 0xc0, 0x0f, 0xf5, 0x5f, 0xc0, 0xc0, 0x0f, 0x55, 0x5f, 0xc0, 0xc0, 0xcf, 0xd5, 0x55, 0xc0, 0xc0, 0xcf, 0xd5, 0x57, 0xc0, 0x3c, 0xcf, 0xf5, 0x5f, 0xfc, 0x03, 0x0f, 0xf5, 0x5f, 0xff, 0xff, 0xf7, 0xd5, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x3c, 0x03, 0xc3, 0x55, 0x5c, 0xc3, 0x0c, 0x33, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x5c, 0xc3, 0x0c, 0x33, 0x55, 0x57, 0x30, 0xf0, 0xcc, 0xd5, 0x55, 0xff, 0xff, 0xf0, 0xd5, 0x55, 0x73, 0x0c, 0x03, 0x55, 0x55, 0xcc, 0xfc, 0x0d, 0x55, 0x55, 0xfc, 0xff, 0x0d, 0x55, 0x55, 0x5c, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x55, 0xf5, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xd7, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x57, 0x00, 0xc3, 0x00, 0xd5, 0x57, 0x3f, 0xc3, 0xfc, 0xd5, 0x57, 0x00, 0x00, 0x00, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x5c, 0xcc, 0x35, 0x55, 0x55, 0x73, 0xff, 0xcd, 0x55, 0x55, 0x70, 0xfc, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x57, 0xf5, 0x55, 0x55, 0x7f, 0xdf, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xc0, 0x30, 0x03, 0x55, 0x55, 0xc0, 0xc0, 0x03, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xfc, 0x00, 0x03, 0x55, 0x55, 0xff, 0x03, 0xc3, 0x55, 0x55, 0x7f, 0x03, 0x3d, 0x55, 0x55, 0x5f, 0xff, 0x35, 0x55, 0x55, 0x5c, 0xcc, 0x0d, 0x55, 0x55, 0x57, 0x3c, 0x03, 0x55, 0x55, 0x57, 0x3c, 0x3f, 0x55, 0x55, 0x57, 0xff, 0xf5, 0x55, 0x55, 0x55, 0x7d, 0xfd, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0x7f, 0x55, 0x55, 0x55, 0xff, 0xff, 0xd5, 0x55, 0x55, 0xff, 0xff, 0xd5, 0x55, 0x55, 0xff, 0x00, 0x35, 0x55, 0x57, 0xf0, 0x00, 0x3d, 0x55, 0x57, 0xc0, 0x03, 0x03, 0x55, 0x57, 0x00, 0x3c, 0x03, 0x55, 0x57, 0x00, 0x00, 0x0f, 0x55, 0x57, 0x00, 0x00, 0x35, 0x55, 0x57, 0xc0, 0x03, 0xd5, 0x55, 0x55, 0x7f, 0xff, 0x55, 0x55, 0x55, 0xc0, 0xcf, 0x55, 0x55, 0x57, 0x30, 0xfd, 0x55, 0x55, 0x57, 0xf0, 0xfd, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x7d, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xf5, 0x55, 0x55, 0x5f, 0xfd, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x70, 0x00, 0x0d, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x0f, 0xc3, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0x70, 0x00, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x5c, 0x3c, 0xd5, 0x55, 0x55, 0x5f, 0x0f, 0xd5, 0x55, 0x55, 0x5c, 0xff, 0xd5, 0x55, 0x55, 0x70, 0x0f, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xd5, 0xf5, 0x55, 0x55, 0x7f, 0xf7, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xfd, 0x55, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0xf0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3c, 0x0f, 0x55, 0x55, 0xc0, 0xc3, 0x03, 0x55, 0x55, 0xc0, 0x00, 0xff, 0x55, 0x55, 0xc0, 0xf0, 0xff, 0x55, 0x55, 0x70, 0xcc, 0xfd, 0x55, 0x55, 0x5f, 0xcf, 0xd5, 0x55, 0x55, 0x5c, 0xcc, 0xd5, 0x55, 0x55, 0x5c, 0x3f, 0xd5, 0x55, 0x55, 0x5c, 0x0f, 0xd5, 0x55, 0x55, 0x70, 0x0f, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5f, 0x55, 0xfd, 0x55, 0x55, 0x7f, 0xdf, 0xff, 0x55, 0x55, 0xff, 0xff, 0xff, 0x55, 0x55, 0xff, 0xff, 0xfd, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x03, 0x55, 0x55, 0xc0, 0x3f, 0xc3, 0x55, 0x55, 0xcc, 0x00, 0x03, 0x55, 0x55, 0x73, 0x00, 0x0d, 0x55, 0x55, 0x5f, 0xff, 0xf5, 0x55, 0x55, 0x73, 0x30, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x73, 0xf3, 0x35, 0x55, 0x55, 0x7f, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xdf, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0x55, 0x7f, 0x55, 0x55, 0xff, 0xd5, 0xff, 0xd5, 0x55, 0xff, 0xff, 0xff, 0xd5, 0x55, 0x7f, 0xff, 0xff, 0x55, 0x55, 0x70, 0x00, 0x03, 0x55, 0x55, 0xc3, 0x00, 0x30, 0xd5, 0x55, 0xcc, 0xc0, 0xcc, 0xd5, 0x55, 0xc3, 0x00, 0x30, 0xd5, 0x57, 0xc0, 0x3f, 0x00, 0xd5, 0x57, 0x30, 0xff, 0xc3, 0x55, 0x55, 0xcf, 0xff, 0xfd, 0x55, 0x55, 0x70, 0xc3, 0x0d, 0x55, 0x55, 0xc3, 0xfc, 0x03, 0x55, 0x55, 0xc3, 0xfc, 0x3c, 0xd5, 0x55, 0x7f, 0xfc, 0x37, 0xd5, 0x55, 0x5f, 0x7f, 0xd5, 0x55, 0x55, 0x55, 0x5f, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x57, 0xf5, 0x55, 0x57, 0xff, 0x5f, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0xff, 0xff, 0xfd, 0x55, 0x57, 0x00, 0x00, 0x0d, 0x55, 0x5c, 0x3c, 0x03, 0xc3, 0x55, 0x5c, 0xf3, 0x0f, 0x33, 0x55, 0x5c, 0xff, 0x0f, 0xf3, 0x55, 0x5c, 0x00, 0x00, 0x03, 0x55, 0x57, 0x0f, 0xf0, 0x0d, 0x55, 0x55, 0xfc, 0x3f, 0xf5, 0x55, 0x55, 0xc3, 0xcc, 0x3d, 0x55, 0x55, 0x70, 0xfc, 0xf3, 0x55, 0x55, 0x70, 0xfc, 0xdf, 0x55, 0x55, 0x7f, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x57, 0xd7, 0xd5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfd, 0x55, 0x55, 0xff, 0xff, 0xcd, 0x55, 0x5f, 0xff, 0xff, 0xfd, 0x55, 0x7f, 0xff, 0xff, 0xd5, 0x55, 0x70, 0x00, 0x03, 0xd5, 0x55, 0xff, 0xff, 0xfc, 0xd5, 0x55, 0xc0, 0x00, 0x0f, 0xd5, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0x7c, 0x00, 0x0c, 0xd5, 0x55, 0x5f, 0xff, 0xf0, 0x35, 0x55, 0x7f, 0x3f, 0xfc, 0x0d, 0x55, 0x7f, 0x3f, 0xfc, 0x0d, 0x55, 0x70, 0x00, 0x3c, 0x0d, 0x55, 0x7f, 0xff, 0xf0, 0x0d, 0x55, 0x5f, 0xff, 0xdf, 0xf5, 0x55, 0x7f, 0xdf, 0xf5, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0x55, 0x55, 0x55, 0x57, 0x35, 0x55, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0xff, 0xff, 0x55, 0x55, 0x5f, 0xff, 0xff, 0x55, 0x55, 0x70, 0x00, 0x0f, 0x55, 0x55, 0x7f, 0xff, 0xf3, 0xfd, 0x55, 0xc0, 0x00, 0x0c, 0xc3, 0x55, 0xc0, 0x00, 0x03, 0xc3, 0x55, 0xc0, 0x00, 0x03, 0x03, 0x55, 0xf0, 0x03, 0x03, 0xc3, 0x55, 0xc3, 0xc0, 0x0f, 0xc3, 0x55, 0xc3, 0xc0, 0x3f, 0x0d, 0x55, 0x7f, 0xff, 0xfc, 0x35, 0x5d, 0xff, 0x3f, 0xf3, 0xd5, 0x5f, 0x00, 0x00, 0xfd, 0x55, 0x5f, 0xff, 0xff, 0x3d, 0x55, 0x55, 0xff, 0xff, 0xf5, 0x55, 0x55, 0x7f, 0xff, 0x55, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xff, 0xff, 0x55, 0x55, 0x7f, 0xff, 0xff, 0xd5, 0x55, 0xf0, 0x00, 0x03, 0xf5, 0x55, 0xcf, 0xff, 0xfc, 0xf5, 0x55, 0xf0, 0x00, 0x03, 0xff, 0x57, 0x0f, 0xc0, 0xfc, 0xf3, 0x57, 0x33, 0xc3, 0x3c, 0xdf, 0x57, 0x33, 0xc3, 0x3c, 0xd5, 0x57, 0x0f, 0xc0, 0xfc, 0xd5, 0x55, 0xc0, 0x3c, 0x03, 0x35, 0x55, 0xff, 0xff, 0xfc, 0x0d, 0x57, 0xff, 0xcf, 0xf3, 0x0d, 0x5c, 0xff, 0xcf, 0xff, 0x0d, 0x57, 0x70, 0x00, 0x0c, 0x0d, 0x55, 0x7f, 0xff, 0xf7, 0xf5, 0x55, 0x57, 0xff, 0xf5, 0x55, 0x55, 0x5f, 0xf7, 0xfd, 0x55, 0x14, 0x14, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xfd, 0x55, 0x55, 0x5f, 0xff, 0xff, 0xf5, 0x55, 0x70, 0x00, 0xff, 0xff, 0x55, 0x7f, 0xfc, 0x03, 0xf3, 0x55, 0xf0, 0xff, 0xf0, 0xdf, 0x55, 0xf0, 0xf3, 0x0f, 0xd5, 0x55, 0xf0, 0xf3, 0x03, 0x55, 0x55, 0xf0, 0xfc, 0x03, 0x55, 0x55, 0xc0, 0x00, 0x0f, 0x55, 0x55, 0xff, 0xf0, 0x33, 0x55, 0x57, 0x3f, 0xc0, 0xff, 0xd5, 0x57, 0xcf, 0xff, 0xfc, 0x35, 0x55, 0xff, 0x3f, 0xfc, 0x0d, 0x55, 0x7f, 0x3f, 0xf0, 0x0d, 0x55, 0x7f, 0x3f, 0xf0, 0x0d, 0x55, 0x70, 0x00, 0xf0, 0x0d, 0x55, 0x5f, 0xff, 0xdf, 0xf5, 0x55, 0x57, 0xff, 0xd5, 0x55, 0x55, 0x55, 0xf7, 0xd5, 0x55, 0x30, 0x1f, 0x01, 0x55, 0x40, 0x00, 0x00, 0x00, 0x15, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x11, 0x41, 0x50, 0x00, 0x00, 0x15, 0x55, 0x55, 0x54, 0x04, 0x10, 0x01, 0x55, 0x41, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa1, 0x14, 0x15, 0x54, 0x01, 0x11, 0x45, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa5, 0x54, 0x15, 0x54, 0x01, 0x55, 0x45, 0x5a, 0xaa, 0x80, 0x56, 0xaa, 0xa1, 0x14, 0x44, 0x11, 0x55, 0x55, 0x55, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x15, 0x40, 0x01, 0x55, 0x11, 0x56, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x95, 0x40, 0x01, 0x55, 0x55, 0x56, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x95, 0x55, 0x55, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0x55, 0x50, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x01, 0x50, 0x55, 0x50, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 0x15, 0x55, 0x55, 0x54, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x02, 0x55, 0x55, 0x55, 0x00, 0x04, 0x00, 0x80, 0x28, 0x00, 0x00, 0xa0, 0x02, 0x01, 0x15, 0x55, 0x10, 0x04, 0x55, 0x80, 0x28, 0x00, 0x00, 0xa0, 0x02, 0x01, 0x15, 0x55, 0x01, 0x55, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x02, 0x55, 0x55, 0x55, 0x01, 0x01, 0x00, 0x80, 0xaa, 0xaa, 0xaa, 0xa8, 0x02, 0x00, 0x04, 0x01, 0x01, 0x55, 0x00, 0x82, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x04, 0x01, 0x00, 0x41, 0x00, 0x82, 0xaa, 0xaa, 0xaa, 0xaa, 0x02, 0x00, 0x04, 0x01, 0x55, 0x5a, 0xa5, 0x80, 0x95, 0x95, 0x80, 0x00, 0x02, 0x55, 0x54, 0x01, 0x00, 0x25, 0x58, 0x80, 0x95, 0x95, 0x85, 0x54, 0x0a, 0xaa, 0xa8, 0x01, 0x00, 0x26, 0x98, 0x80, 0x95, 0x95, 0x85, 0x54, 0x08, 0x00, 0x09, 0x55, 0x00, 0x25, 0x58, 0x80, 0x95, 0x95, 0xaa, 0xaa, 0x08, 0x88, 0x88, 0x00, 0x00, 0x20, 0x08, 0x95, 0x95, 0x95, 0x80, 0x02, 0x58, 0x88, 0x88, 0x00, 0xaa, 0xa0, 0x0a, 0x95, 0x95, 0x95, 0x80, 0x02, 0x58, 0x00, 0x0a, 0xaa, 0x04, 0x20, 0x08, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa9, 0x55, 0x58, 0x00, 0x00, 0x0a, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xaa, 0xa9, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 0x42, 0x82, 0x20, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa6, 0x86, 0x26, 0x62, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x45, 0x86, 0x24, 0xa4, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xa4, 0xa1, 0x61, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x61, 0x40, 0xa2, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0xaa, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa9, 0x55, 0x69, 0x55, 0x6a, 0x02, 0xaa, 0xaa, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x9a, 0xa9, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x59, 0x59, 0x6a, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x98, 0x49, 0xaa, 0xaa, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0x95, 0x55, 0xaa, 0x95, 0xa8, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa5, 0x56, 0xaa, 0x40, 0x68, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa8, 0x0a, 0xa5, 0x55, 0x58, 0x00, 0x95, 0x55, 0x69, 0x55, 0x56, 0x02, 0xa9, 0x5a, 0xa5, 0x55, 0x58, 0x00, 0x95, 0x5a, 0x69, 0xa5, 0x56, 0x02, 0xa5, 0x96, 0xa9, 0x69, 0x68, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x96, 0x5a, 0x69, 0xa5, 0x96, 0x54, 0x54, 0x54, 0x54, 0x54, 0x55, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x54, 0x54, 0x54, 0x54, 0x54, 0x55, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x96, 0x59, 0x69, 0x65, 0x96, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x30, 0x1f, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x15, 0x00, 0x00, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x55, 0x00, 0x01, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x40, 0x51, 0x55, 0x55, 0x15, 0x54, 0x00, 0x00, 0x15, 0x54, 0x55, 0x55, 0x45, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x40, 0x00, 0x44, 0x11, 0x10, 0x11, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x44, 0x04, 0x44, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x04, 0x40, 0x00, 0x44, 0x15, 0x05, 0x41, 0x50, 0x05, 0x55, 0x55, 0x50, 0x05, 0x41, 0x50, 0x54, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x50, 0x40, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x50, 0x40, 0x01, 0x00, 0x01, 0x00, 0x17, 0xfc, 0x3f, 0xfc, 0x00, 0x43, 0xff, 0xc0, 0x01, 0x00, 0x01, 0x00, 0x1f, 0xf4, 0xff, 0xd4, 0x00, 0x4f, 0xfc, 0x40, 0x01, 0x55, 0x55, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x40, 0x01, 0x11, 0x11, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x40, 0x01, 0x00, 0x01, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xc0, 0x01, 0x05, 0x41, 0x00, 0xf0, 0xfc, 0x03, 0xff, 0xff, 0x00, 0x00, 0xc0, 0x01, 0x05, 0x41, 0x00, 0xf0, 0xf3, 0x0c, 0x71, 0xc7, 0x33, 0x30, 0xc0, 0xaa, 0xaa, 0xaa, 0xaa, 0xf0, 0xf3, 0x0d, 0x75, 0xd7, 0x33, 0x30, 0xea, 0x55, 0x55, 0x55, 0x55, 0xf0, 0xfc, 0x0d, 0x34, 0xd3, 0x33, 0x30, 0xd5, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x0d, 0x34, 0xc3, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x03, 0xff, 0xff, 0xaa, 0xaa, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 0xc0, 0x00, 0xfc, 0x0f, 0xc0, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x3a, 0xbf, 0xfa, 0xab, 0xff, 0xbf, 0xfb, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0xff, 0xff, 0xcf, 0xfc, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf0, 0x03, 0xff, 0x3f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xc0, 0x00, 0xfc, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x55, 0x51, 0x55, 0x55, 0x15, 0x54, 0x00, 0x00, 0x15, 0x10, 0x00, 0x00, 0x40, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x40, 0x11, 0x10, 0x11, 0x10, 0x04, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x40, 0x11, 0x00, 0x01, 0x10, 0x04, 0x00, 0x00, 0x10, 0x15, 0x55, 0x55, 0x40, 0x15, 0x05, 0x41, 0x50, 0x05, 0x55, 0x55, 0x50, 0x00, 0x00, 0x00, 0x00, 0x01, 0x05, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf5, 0xff, 0xf0, 0x00, 0x0f, 0xff, 0x00, 0x50, 0x50, 0x50, 0x50, 0x3f, 0xc3, 0xff, 0x00, 0x14, 0x3f, 0xf4, 0x14, 0x55, 0x50, 0x55, 0x50, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x54, 0x55, 0x50, 0x55, 0x50, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x54, 0x55, 0x55, 0x55, 0x53, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x54, 0x40, 0x10, 0x40, 0x13, 0xc3, 0xf0, 0x0f, 0xff, 0xfc, 0x00, 0x03, 0x04, 0x50, 0x50, 0x50, 0x53, 0xc3, 0xcc, 0x31, 0xc7, 0x1c, 0xcc, 0xc3, 0x14, 0x40, 0x10, 0x40, 0x13, 0xc3, 0xcc, 0x35, 0xd7, 0x5c, 0xcc, 0xc3, 0x04, 0xaa, 0xaa, 0xaa, 0xab, 0xc3, 0xf0, 0x34, 0xd3, 0x4c, 0xcc, 0xc3, 0xaa, 0x55, 0x55, 0x55, 0x57, 0x00, 0x00, 0x34, 0xd3, 0x0c, 0x00, 0x03, 0x55, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x0f, 0xff, 0xfe, 0xaa, 0xab, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x3f, 0x00, 0x03, 0xf0, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xea, 0xff, 0xea, 0xaf, 0xfe, 0xff, 0xec, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf3, 0xff, 0xff, 0x3f, 0xf3, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x0f, 0xfc, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x03, 0xf0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xfd, 0x7d, 0x7f, 0x5d, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x5d, 0xd5, 0xd7, 0x75, 0xdd, 0xd5, 0x55, 0x55, 0x55, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x30, 0xcc, 0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0xc0, 0xff, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xc0, 0xc3, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0x3f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xfc, 0x3f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x03, 0xc0, 0x30, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0xf3, 0xff, 0xff, 0xcf, 0x00, 0x00, 0x0f, 0xf0, 0x70, 0x0f, 0x55, 0x55, 0xc3, 0x0c, 0x30, 0xc3, 0x55, 0x55, 0xf0, 0x0d, 0xc3, 0x30, 0xd5, 0xff, 0x7c, 0xcf, 0xf3, 0x3d, 0xff, 0x57, 0x0c, 0xc3, 0xc0, 0x3f, 0x5f, 0x03, 0x57, 0xcf, 0xf3, 0xd5, 0xc0, 0xf5, 0xfc, 0x03, 0xc0, 0x30, 0xdc, 0x0d, 0x5f, 0xff, 0xff, 0xf5, 0x70, 0x37, 0x0c, 0x03, 0x7f, 0xff, 0x5f, 0xf5, 0x5f, 0x55, 0x55, 0xf5, 0x5f, 0xf5, 0xff, 0xfd, 0x30, 0x1f, 0xa4, 0x00, 0xa4, 0x01, 0x90, 0x00, 0x64, 0x06, 0x40, 0x1a, 0x00, 0x16, 0xa9, 0x40, 0x09, 0x00, 0x40, 0x00, 0x10, 0x01, 0x00, 0x60, 0x01, 0x6a, 0x2a, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xaa, 0x00, 0xa5, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x01, 0x6a, 0x80, 0x00, 0x01, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x30, 0xc0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x00, 0x05, 0x94, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x15, 0x56, 0xa5, 0x55, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x15, 0x40, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x29, 0x50, 0x15, 0x68, 0x00, 0x40, 0x07, 0xf0, 0x0f, 0xc0, 0x10, 0x00, 0x0a, 0xa5, 0x6a, 0x80, 0x01, 0x00, 0x1f, 0xfc, 0x3f, 0xf0, 0x04, 0x00, 0x00, 0xaa, 0xa8, 0x00, 0x15, 0x00, 0x1f, 0xff, 0xff, 0xf0, 0x05, 0x40, 0x00, 0x0a, 0xa0, 0x00, 0x04, 0x00, 0x5c, 0x00, 0x00, 0x30, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xf0, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xc0, 0x33, 0x00, 0x00, 0xcc, 0x03, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x30, 0x03, 0xc0, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x0c, 0x30, 0x03, 0xc0, 0x0c, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x3c, 0x03, 0xc0, 0x3c, 0xff, 0xc0, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0xc3, 0xff, 0xff, 0xc3, 0x00, 0x00, 0x0f, 0xf0, 0x30, 0x0c, 0x00, 0x00, 0xcc, 0x30, 0x0c, 0x33, 0x00, 0x00, 0x30, 0x0c, 0xc3, 0x0f, 0x00, 0x00, 0x3f, 0x3f, 0xfc, 0xfc, 0x00, 0x00, 0xf0, 0xc3, 0xc0, 0x30, 0xc0, 0x00, 0x03, 0x3f, 0xfc, 0xc0, 0x00, 0x03, 0x0c, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0xfc, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x3f, 0xfc, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x30, 0x30, 0xc0, 0x00, 0x00, 0x3c, 0x3c, 0x00, 0x00, 0x03, 0x0c, 0x0c, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x0c, 0x30, 0x00, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf5, 0xfd, 0x7d, 0x7f, 0x5d, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x5d, 0xd5, 0xd7, 0x75, 0xdd, 0xd5, 0x55, 0x55, 0x55, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x30, 0xcc, 0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xf0, 0xc0, 0xff, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xc0, 0xc3, 0x30, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0xfc, 0xc3, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x70, 0x0f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xf0, 0x0d, 0xc3, 0x30, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x0c, 0xc3, 0xc0, 0x3f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xfc, 0x03, 0xc0, 0x30, 0xd5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0x0c, 0x03, 0x7f, 0xff, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xfd, 0x30, 0x1f, 0xa4, 0x00, 0xa4, 0x01, 0x90, 0x00, 0x64, 0x06, 0x40, 0x1a, 0x00, 0x16, 0xa9, 0x40, 0x09, 0x00, 0x40, 0x00, 0x10, 0x01, 0x00, 0x60, 0x01, 0x6a, 0x2a, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xaa, 0x00, 0xa5, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x01, 0x6a, 0x80, 0x00, 0x01, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x30, 0xc0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x00, 0x05, 0x94, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x30, 0xc0, 0x00, 0x15, 0x56, 0xa5, 0x55, 0x40, 0x03, 0x03, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x02, 0xaa, 0xaa, 0x80, 0x00, 0x00, 0xfc, 0x03, 0xf0, 0x30, 0xc0, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x54, 0x00, 0x00, 0x15, 0x40, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x29, 0x50, 0x15, 0x68, 0x00, 0x40, 0x04, 0x00, 0x04, 0x00, 0x10, 0x00, 0x0a, 0xa5, 0x6a, 0x80, 0x01, 0x00, 0x14, 0x00, 0x05, 0x00, 0x04, 0x00, 0x00, 0xaa, 0xa8, 0x00, 0x15, 0x00, 0x15, 0x00, 0x15, 0x00, 0x05, 0x40, 0x00, 0x0a, 0xa0, 0x00, 0x04, 0x00, 0x54, 0x00, 0x05, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x30, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0c, 0xc3, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xc3, 0xc0, 0x30, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x30, 0x30, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x0c, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xfc, 0x00, 0xc3, 0x0f, 0x0f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xc3, 0x00, 0xc3, 0x30, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xcc, 0xc3, 0x00, 0xff, 0x30, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xfc, 0x00, 0xc3, 0x30, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x30, 0xcc, 0xc0, 0x00, 0xc3, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x3f, 0x0f, 0xcf, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0xcc, 0x0c, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0xcf, 0xcf, 0xcc, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x3f, 0x0c, 0x0c, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0x0f, 0xcf, 0xcf, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x30, 0xcc, 0x33, 0x0c, 0xfc, 0xfc, 0x00, 0x00, 0xc0, 0x00, 0x00, 0xc3, 0x30, 0xcf, 0x33, 0xcc, 0xc0, 0xc3, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc3, 0x30, 0xcc, 0xf3, 0x3c, 0xfc, 0xc3, 0x00, 0x00, 0xfc, 0x00, 0x00, 0xfc, 0x30, 0xcc, 0x33, 0x0c, 0xc0, 0xfc, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc3, 0x0f, 0x0c, 0x33, 0x0c, 0xfc, 0xc3, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x1f, 0x05, 0x55, 0x55, 0x55, 0x55, 0x55, 0x54, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x05, 0x54, 0x55, 0x45, 0x51, 0x10, 0x00, 0x04, 0x04, 0x55, 0x44, 0x51, 0x11, 0x55, 0x44, 0x04, 0x44, 0x44, 0x51, 0x11, 0x00, 0x44, 0x04, 0x44, 0x44, 0x51, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x00, 0x00, 0x00, 0x05, 0x41, 0x10, 0x00, 0x00, 0x00, 0x00, 0x04, 0x41, 0x10, 0x00, 0x00, 0x10, 0x55, 0x05, 0x41, 0x10, 0x54, 0x00, 0x55, 0x45, 0x10, 0x11, 0x11, 0x01, 0x40, 0x55, 0x54, 0x10, 0x11, 0x11, 0x00, 0x10, 0x55, 0x54, 0x15, 0x51, 0x11, 0x41, 0x11, 0x51, 0x10, 0x04, 0x41, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x50, 0x50, 0x00, 0x00, 0x10, 0x01, 0x10, 0x55, 0x50, 0x55, 0x00, 0x55, 0x01, 0x10, 0x44, 0x51, 0x00, 0x51, 0x00, 0x41, 0x10, 0x40, 0x11, 0x04, 0x41, 0x11, 0x41, 0x10, 0x15, 0x41, 0x00, 0x41, 0x00, 0x41, 0x10, 0x10, 0x41, 0x00, 0x40, 0x41, 0x01, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x55, 0x55, 0x55, 0x55, 0x55, 0x41, 0x10, 0x40, 0x00, 0x00, 0x00, 0x00, 0x41, 0x10, 0x55, 0x55, 0x55, 0x55, 0x55, 0x41, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x15, 0x50, 0x00, 0x00, 0x00, 0x01, 0x55, 0x12, 0x0c, 0x57, 0xf5, 0x7d, 0x55, 0x50, 0x5f, 0xfd, 0xff, 0x55, 0x50, 0x5f, 0xff, 0xff, 0x55, 0x50, 0x5f, 0xff, 0xff, 0xd5, 0x50, 0x7c, 0x00, 0x00, 0xd5, 0x50, 0x70, 0x0f, 0xc3, 0xd5, 0x50, 0x70, 0x33, 0xc3, 0xd5, 0x50, 0x70, 0x33, 0xc3, 0xd5, 0x50, 0x70, 0x0f, 0xc3, 0xd5, 0x50, 0x5c, 0x00, 0x0f, 0x55, 0x50, 0x57, 0xff, 0xfd, 0x55, 0x50, 0x5c, 0x3c, 0x33, 0x55, 0x50, 0x12, 0x0c, 0x55, 0xfd, 0x5f, 0x55, 0x50, 0x57, 0xff, 0x7f, 0xd5, 0x50, 0x57, 0xff, 0xff, 0xd5, 0x50, 0x57, 0xff, 0xff, 0xf5, 0x50, 0x5f, 0x00, 0x00, 0x35, 0x50, 0x5c, 0x03, 0xc0, 0x35, 0x50, 0x5c, 0x0c, 0x30, 0xf5, 0x50, 0x5c, 0x00, 0x00, 0x35, 0x50, 0x5c, 0x0c, 0x0f, 0xf5, 0x50, 0x57, 0x33, 0x0f, 0xd5, 0x50, 0x55, 0xf3, 0xff, 0x35, 0x50, 0x55, 0xc3, 0xc3, 0xf5, 0x50, 0x12, 0x0c, 0x5f, 0xd5, 0x7f, 0xff, 0xf0, 0x7f, 0xf5, 0xff, 0x00, 0x30, 0x7f, 0xff, 0xff, 0x00, 0x30, 0x7f, 0xff, 0xff, 0x00, 0x30, 0x70, 0x00, 0x03, 0x00, 0x30, 0xc3, 0xf0, 0x3f, 0x00, 0x30, 0xcc, 0xf0, 0xcf, 0x00, 0x30, 0xcc, 0xf0, 0xcf, 0x00, 0x30, 0xc3, 0xf0, 0x3f, 0xff, 0xf0, 0x70, 0x0f, 0x00, 0xcd, 0x50, 0x5f, 0xff, 0xff, 0x35, 0x50, 0x70, 0x30, 0x3c, 0xd5, 0x50, 0x12, 0x0c, 0x55, 0xfd, 0x57, 0xd5, 0x50, 0x57, 0xff, 0xdf, 0xf5, 0x50, 0x57, 0xff, 0xff, 0xfd, 0x50, 0x55, 0xff, 0xff, 0xfd, 0x50, 0x57, 0xc0, 0x00, 0x0d, 0x50, 0x57, 0x00, 0x00, 0x0d, 0x50, 0x57, 0x00, 0x00, 0x0d, 0x50, 0x57, 0x0f, 0xf0, 0x0d, 0x50, 0x57, 0x00, 0x00, 0xcd, 0x50, 0x55, 0xc0, 0x03, 0x35, 0x50, 0x55, 0x7f, 0xff, 0xd5, 0x50, 0x55, 0xc3, 0xc3, 0xd5, 0x50, 0x12, 0x0c, 0x57, 0xf5, 0x5f, 0xd5, 0x50, 0x5f, 0xfd, 0x7f, 0xf5, 0x50, 0x5f, 0xff, 0xff, 0xf5, 0x50, 0x5f, 0xff, 0xff, 0xf5, 0x50, 0x5c, 0x00, 0x00, 0x35, 0x50, 0x70, 0x00, 0x00, 0x0d, 0x50, 0x70, 0x30, 0x0c, 0x0d, 0x50, 0x70, 0xc0, 0x03, 0x0d, 0x50, 0x70, 0x03, 0xc0, 0x0d, 0x50, 0x5c, 0x0f, 0xf0, 0x35, 0x50, 0x57, 0xff, 0xff, 0xd5, 0x50, 0x55, 0xcc, 0x33, 0x55, 0x50, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfa, 0xaa, 0xab, 0xc0, 0xff, 0xe5, 0x55, 0x5a, 0xc0, 0xff, 0xe5, 0x55, 0x5a, 0xc0, 0xff, 0x95, 0x55, 0x66, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0xaa, 0xaa, 0xab, 0xc0, 0x11, 0x15, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xff, 0xfe, 0xaa, 0xaa, 0xc0, 0xff, 0xfe, 0x55, 0x56, 0xc0, 0xff, 0xfe, 0x55, 0x56, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xf9, 0x55, 0x5b, 0xc0, 0xff, 0xea, 0xaa, 0xaa, 0xc0, 0xff, 0xea, 0xaa, 0xaa, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0xaa, 0xaa, 0xa6, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x8a, 0x28, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0x80, 0x00, 0x26, 0xc0, 0xff, 0xaa, 0xaa, 0xab, 0xc0, 0x08, 0x08, 0x7f, 0xf5, 0xff, 0xfd, 0xc3, 0x0d, 0xff, 0xfd, 0xff, 0xfd, 0xfc, 0xfd, 0x7f, 0xf5, 0x77, 0x75, 0x10, 0x03, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xc0, 0x03, 0x03, 0xff, 0xff, 0xff, 0xff, 0x10, 0x03, 0x55, 0xff, 0xff, 0x55, 0x55, 0xc0, 0x03, 0x55, 0x55, 0xff, 0xff, 0x55, 0x08, 0x08, 0x55, 0x75, 0x55, 0x75, 0x55, 0x75, 0x5f, 0x75, 0x70, 0xf5, 0x70, 0xd5, 0x5f, 0x55, 0x55, 0x55, 0x08, 0x08, 0x55, 0x75, 0x55, 0x75, 0x55, 0x75, 0x5f, 0x75, 0x7f, 0xf5, 0x7f, 0xd5, 0x5f, 0x55, 0x55, 0x55, 0x08, 0x08, 0x55, 0xd5, 0x55, 0xf5, 0x55, 0xfd, 0x7d, 0xdd, 0xff, 0xd5, 0xff, 0x55, 0x7d, 0x55, 0x55, 0x55, 0x08, 0x08, 0x5f, 0xfd, 0x5d, 0x5d, 0x5d, 0x5d, 0x5d, 0x5d, 0xfd, 0xfd, 0xfd, 0xfd, 0xf5, 0xf5, 0x55, 0x55, 0x01, 0x01, 0x00, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0xf3, 0x55, 0x55, 0x55, 0x55, 0x7c, 0x03, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x7f, 0xfd, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x5f, 0xfd, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x7f, 0xfd, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0x03, 0x55, 0x55, 0x5f, 0xfd, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x18, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xfd, 0x55, 0x55, 0x7f, 0xfd, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0x03, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0xf3, 0x55, 0x55, 0x7c, 0xf3, 0x7c, 0x03, 0x55, 0x55, 0x7c, 0x03, 0x5f, 0xfd, 0x55, 0x55, 0x5f, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x08, 0x08, 0x50, 0x05, 0x43, 0xc1, 0x00, 0x00, 0x30, 0xcc, 0x33, 0x0c, 0x00, 0x00, 0x43, 0xc1, 0x50, 0x05, 0x08, 0x08, 0xc0, 0x03, 0x33, 0xcc, 0x00, 0x30, 0x33, 0x0c, 0x30, 0xcc, 0x0c, 0x00, 0x33, 0xcc, 0xc0, 0x03, 0x08, 0x08, 0x57, 0xd5, 0x5c, 0x35, 0x5c, 0x35, 0xdc, 0x37, 0xd7, 0xd7, 0xdf, 0xf7, 0xfd, 0x7f, 0xf7, 0xdf, 0x04, 0x1f, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57, 0x02, 0x05, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0x06, 0x20, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0xc3, 0xf0, 0xc3, 0xf0, 0xfc, 0x30, 0xfc, 0x30, 0x20, 0x08, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x57, 0xf7, 0xff, 0x5f, 0x5f, 0xd7, 0xff, 0x75, 0x5d, 0x55, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x57, 0xd5, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x55, 0x75, 0x75, 0x7f, 0xdf, 0xd5, 0x75, 0x75, 0x55, 0x75, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x55, 0x5f, 0xd5, 0x75, 0x75, 0xdd, 0x75, 0x75, 0x75, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x08, 0x7f, 0x5f, 0x57, 0xd7, 0x57, 0xd5, 0x75, 0xdd, 0x77, 0x57, 0xdf, 0x75, 0xdd, 0x77, 0x57, 0xd7, 0x75, 0xdf, 0xf7, 0x55, 0x7d, 0x5f, 0x5d, 0x77, 0xf7, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x14, 0x0c, 0x7f, 0x5f, 0x5d, 0x5d, 0xfd, 0xd5, 0x75, 0xdf, 0x7d, 0xd5, 0xdf, 0x75, 0xdf, 0xfd, 0xfd, 0xd7, 0x7f, 0xdd, 0xdd, 0xd5, 0x7f, 0x75, 0xdd, 0x5d, 0xfd, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7d, 0x75, 0x77, 0xf7, 0xf5, 0xd7, 0x75, 0x77, 0x57, 0x5d, 0xd7, 0x5d, 0xd7, 0xf7, 0x5d, 0xd7, 0x5d, 0xd7, 0x57, 0xf5, 0x7d, 0x57, 0x57, 0xf7, 0x5d, 0x55, 0x55, 0x55, 0x55, 0x55, 0x20, 0x0c, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0x55, 0x55, 0x55, 0x55, 0x5f, 0xff, 0x55, 0xc3, 0x7d, 0x55, 0x55, 0x55, 0x70, 0x00, 0xd5, 0x70, 0xff, 0x55, 0x55, 0x55, 0xc0, 0x00, 0x35, 0x7c, 0x3f, 0xd5, 0x55, 0x57, 0x00, 0x03, 0x0d, 0x5f, 0xff, 0xff, 0xff, 0xfc, 0x03, 0x00, 0x0d, 0x70, 0x00, 0x03, 0xc0, 0x00, 0x00, 0x3f, 0xfd, 0x7f, 0xff, 0xfc, 0x30, 0x00, 0x00, 0xc0, 0x03, 0xc0, 0x00, 0x03, 0x30, 0x00, 0x03, 0x0f, 0xfc, 0xc0, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc0, 0x03, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x01, 0x01, 0x00, 0x10, 0x10, 0x55, 0x7d, 0x55, 0xf5, 0x55, 0xc3, 0x57, 0x0d, 0x55, 0xc0, 0xdc, 0x0d, 0x55, 0x70, 0xdc, 0x3d, 0x55, 0x5c, 0x30, 0x35, 0x55, 0x70, 0x00, 0xd5, 0x55, 0xc3, 0xfc, 0xd5, 0x55, 0xcf, 0xff, 0x35, 0x57, 0x0f, 0xff, 0x35, 0x57, 0x00, 0xfc, 0x35, 0x57, 0xc0 }; void EXTI0_IRQHandler() { //GPIO_SetBits(GPIOB, GPIO_Pin_14); //if (EXTI_GetITStatus(EXTI_Line0) != RESET) { if(started){ if(loops > 2000){ loops = 0; } read = 1; //GPIO_SetBits(GPIOB, GPIO_Pin_14); a = 0; acount = 0; // as[loops++] = a; //as[loops++] = acount; as[loops++] = hit; hit = 0; } EXTI_ClearITPendingBit(EXTI_Line0); //} //GPIO_ResetBits(GPIOB, GPIO_Pin_14); } void EXTI1_IRQHandler() { //hit++; //if (EXTI_GetITStatus(EXTI_Line1) != RESET) { if(read){ // a = a << 1; // GPIO_SetBits(GPIOB, GPIO_Pin_15); // a = a | (GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_8)); (GPIOD->IDR & GPIO_Pin_8) ? (a = ((a << 1)|1) ) : (a <<= 1); //GPIO_ResetBits(GPIOB, GPIO_Pin_15); acount++; // if(acount > 32){ // GPIO_SetBits(GPIOD, GPIO_Pin_15); // } if (acount ==32){ read = 0; //if((a & 0xff000000) != 0x03000000){ // GPIO_SetBits(GPIOD, GPIO_Pin_14); // } as[loops++] = a; a = 0xffffff & a; // index = (loops % 800) / 100; /* if(loops > 100){ loops = 0; index++; if (index > 7) index = 0; } for(i = 0; i < 105; i++){ v[0xe0 + i] = vs[index][i]; }*/ val = v[a++]; // as[loops++] = val; // as[loops++] = val; c = 0x80; if(val&c){ GPIO_SetBits(GPIOD, GPIO_Pin_4); }else{ GPIO_ResetBits(GPIOD, GPIO_Pin_4); } c = c >> 1; started = 1; } }else{ if(val&c){ GPIOD->BSRRL = GPIO_Pin_4; }else{ GPIOD->BSRRH = GPIO_Pin_4; } c = c >> 1; if(c==0){ c = 0x80; val = v[a++]; // as[loops++] = val; } //as[loops++] = 2; } EXTI_ClearITPendingBit(EXTI_Line1); //} } /** * @brief Main program. * @param None * @retval None */ uint32_t getAddress(); int main(void) { RCC_ClocksTypeDef RCC_Clocks; int l = 0; /* Initialize LEDs and User_Button on STM32F4-Discovery --------------------*/ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE); RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE); /* SysTick end of count event each 10ms */ // RCC_GetClocksFreq(&RCC_Clocks); // SysTick_Config(RCC_Clocks.HCLK_Frequency / 100); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_8 ; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_Init(GPIOD, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; GPIO_Init(GPIOD, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_13| GPIO_Pin_14| GPIO_Pin_15; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_Init(GPIOD, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14 | GPIO_Pin_15; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_Init(GPIOB, &GPIO_InitStructure); EXTILine0_Config(); GPIO_SetBits(GPIOD, GPIO_Pin_12); // GPIO_SetBits(GPIOD, GPIO_Pin_14); // GPIO_SetBits(GPIOD, GPIO_Pin_12); // GPIO_ResetBits(GPIOB, GPIO_Pin_14); //GPIO_SetBits(GPIOB, GPIO_Pin_14); vs[0] = v1; vs[1] = v2; vs[2] = v3; vs[3] = v2; vs[4] = v4; vs[5] = v5; vs[6] = v6; vs[7] = v7; while(1){ } } /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/src/startup_stm32f4xx.s ================================================ /** ****************************************************************************** * @file startup_stm32f4xx.s * @author MCD Application Team * @version V1.0.2 * @date 05-March-2012 * @brief STM32F4xx Devices vector table for Atollic TrueSTUDIO toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, * - Set the vector table entries with the exceptions ISR address * - Configure the clock system and the external SRAM mounted on * STM324xG-EVAL board to be used as data memory (optional, * to be enabled by user) * - Branches to main in the C library (which eventually * calls main()). * After Reset the Cortex-M4 processor is in Thread mode, * priority is Privileged, and the Stack is set to Main. ****************************************************************************** * @attention * *

© COPYRIGHT 2012 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ .syntax unified .cpu cortex-m3 .fpu softvfp .thumb .global g_pfnVectors .global Default_Handler /* start address for the initialization values of the .data section. defined in linker script */ .word _sidata /* start address for the .data section. defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata /* start address for the .bss section. defined in linker script */ .word _sbss /* end address for the .bss section. defined in linker script */ .word _ebss /* stack used for SystemInit_ExtMemCtl; always internal RAM used */ /** * @brief This is the code that gets called when the processor first * starts execution following a reset event. Only the absolutely * necessary set is performed, after which the application * supplied main() routine is called. * @param None * @retval : None */ .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 b LoopCopyDataInit CopyDataInit: ldr r3, =_sidata ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 LoopCopyDataInit: ldr r0, =_sdata ldr r3, =_edata adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit ldr r2, =_sbss b LoopFillZerobss /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 str r3, [r2], #4 LoopFillZerobss: ldr r3, = _ebss cmp r2, r3 bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ bl main bx lr .size Reset_Handler, .-Reset_Handler /** * @brief This is the code that gets called when the processor receives an * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. * @param None * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler /****************************************************************************** * * The minimal vector table for a Cortex M3. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. * *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack .word Reset_Handler .word NMI_Handler .word HardFault_Handler .word MemManage_Handler .word BusFault_Handler .word UsageFault_Handler .word 0 .word 0 .word 0 .word 0 .word SVC_Handler .word DebugMon_Handler .word 0 .word PendSV_Handler .word SysTick_Handler /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog */ .word PVD_IRQHandler /* PVD through EXTI Line detection */ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ .word FLASH_IRQHandler /* FLASH */ .word RCC_IRQHandler /* RCC */ .word EXTI0_IRQHandler /* EXTI Line0 */ .word EXTI1_IRQHandler /* EXTI Line1 */ .word EXTI2_IRQHandler /* EXTI Line2 */ .word EXTI3_IRQHandler /* EXTI Line3 */ .word EXTI4_IRQHandler /* EXTI Line4 */ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ .word CAN1_TX_IRQHandler /* CAN1 TX */ .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ .word CAN1_SCE_IRQHandler /* CAN1 SCE */ .word EXTI9_5_IRQHandler /* External Line[9:5]s */ .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ .word TIM2_IRQHandler /* TIM2 */ .word TIM3_IRQHandler /* TIM3 */ .word TIM4_IRQHandler /* TIM4 */ .word I2C1_EV_IRQHandler /* I2C1 Event */ .word I2C1_ER_IRQHandler /* I2C1 Error */ .word I2C2_EV_IRQHandler /* I2C2 Event */ .word I2C2_ER_IRQHandler /* I2C2 Error */ .word SPI1_IRQHandler /* SPI1 */ .word SPI2_IRQHandler /* SPI2 */ .word USART1_IRQHandler /* USART1 */ .word USART2_IRQHandler /* USART2 */ .word USART3_IRQHandler /* USART3 */ .word EXTI15_10_IRQHandler /* External Line[15:10]s */ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ .word FSMC_IRQHandler /* FSMC */ .word SDIO_IRQHandler /* SDIO */ .word TIM5_IRQHandler /* TIM5 */ .word SPI3_IRQHandler /* SPI3 */ .word UART4_IRQHandler /* UART4 */ .word UART5_IRQHandler /* UART5 */ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ .word TIM7_IRQHandler /* TIM7 */ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ .word ETH_IRQHandler /* Ethernet */ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ .word CAN2_TX_IRQHandler /* CAN2 TX */ .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ .word CAN2_SCE_IRQHandler /* CAN2 SCE */ .word OTG_FS_IRQHandler /* USB OTG FS */ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ .word USART6_IRQHandler /* USART6 */ .word I2C3_EV_IRQHandler /* I2C3 event */ .word I2C3_ER_IRQHandler /* I2C3 error */ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ .word OTG_HS_IRQHandler /* USB OTG HS */ .word DCMI_IRQHandler /* DCMI */ .word CRYP_IRQHandler /* CRYP crypto */ .word HASH_RNG_IRQHandler /* Hash and Rng */ .word FPU_IRQHandler /* FPU */ /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. * As they are weak aliases, any function with the same name will override * this definition. * *******************************************************************************/ .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler .weak HardFault_Handler .thumb_set HardFault_Handler,Default_Handler .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler .weak BusFault_Handler .thumb_set BusFault_Handler,Default_Handler .weak UsageFault_Handler .thumb_set UsageFault_Handler,Default_Handler .weak SVC_Handler .thumb_set SVC_Handler,Default_Handler .weak DebugMon_Handler .thumb_set DebugMon_Handler,Default_Handler .weak PendSV_Handler .thumb_set PendSV_Handler,Default_Handler .weak SysTick_Handler .thumb_set SysTick_Handler,Default_Handler .weak WWDG_IRQHandler .thumb_set WWDG_IRQHandler,Default_Handler .weak PVD_IRQHandler .thumb_set PVD_IRQHandler,Default_Handler .weak TAMP_STAMP_IRQHandler .thumb_set TAMP_STAMP_IRQHandler,Default_Handler .weak RTC_WKUP_IRQHandler .thumb_set RTC_WKUP_IRQHandler,Default_Handler .weak FLASH_IRQHandler .thumb_set FLASH_IRQHandler,Default_Handler .weak RCC_IRQHandler .thumb_set RCC_IRQHandler,Default_Handler .weak EXTI0_IRQHandler .thumb_set EXTI0_IRQHandler,Default_Handler .weak EXTI1_IRQHandler .thumb_set EXTI1_IRQHandler,Default_Handler .weak EXTI2_IRQHandler .thumb_set EXTI2_IRQHandler,Default_Handler .weak EXTI3_IRQHandler .thumb_set EXTI3_IRQHandler,Default_Handler .weak EXTI4_IRQHandler .thumb_set EXTI4_IRQHandler,Default_Handler .weak DMA1_Stream0_IRQHandler .thumb_set DMA1_Stream0_IRQHandler,Default_Handler .weak DMA1_Stream1_IRQHandler .thumb_set DMA1_Stream1_IRQHandler,Default_Handler .weak DMA1_Stream2_IRQHandler .thumb_set DMA1_Stream2_IRQHandler,Default_Handler .weak DMA1_Stream3_IRQHandler .thumb_set DMA1_Stream3_IRQHandler,Default_Handler .weak DMA1_Stream4_IRQHandler .thumb_set DMA1_Stream4_IRQHandler,Default_Handler .weak DMA1_Stream5_IRQHandler .thumb_set DMA1_Stream5_IRQHandler,Default_Handler .weak DMA1_Stream6_IRQHandler .thumb_set DMA1_Stream6_IRQHandler,Default_Handler .weak ADC_IRQHandler .thumb_set ADC_IRQHandler,Default_Handler .weak CAN1_TX_IRQHandler .thumb_set CAN1_TX_IRQHandler,Default_Handler .weak CAN1_RX0_IRQHandler .thumb_set CAN1_RX0_IRQHandler,Default_Handler .weak CAN1_RX1_IRQHandler .thumb_set CAN1_RX1_IRQHandler,Default_Handler .weak CAN1_SCE_IRQHandler .thumb_set CAN1_SCE_IRQHandler,Default_Handler .weak EXTI9_5_IRQHandler .thumb_set EXTI9_5_IRQHandler,Default_Handler .weak TIM1_BRK_TIM9_IRQHandler .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler .weak TIM1_UP_TIM10_IRQHandler .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler .weak TIM1_TRG_COM_TIM11_IRQHandler .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler .weak TIM1_CC_IRQHandler .thumb_set TIM1_CC_IRQHandler,Default_Handler .weak TIM2_IRQHandler .thumb_set TIM2_IRQHandler,Default_Handler .weak TIM3_IRQHandler .thumb_set TIM3_IRQHandler,Default_Handler .weak TIM4_IRQHandler .thumb_set TIM4_IRQHandler,Default_Handler .weak I2C1_EV_IRQHandler .thumb_set I2C1_EV_IRQHandler,Default_Handler .weak I2C1_ER_IRQHandler .thumb_set I2C1_ER_IRQHandler,Default_Handler .weak I2C2_EV_IRQHandler .thumb_set I2C2_EV_IRQHandler,Default_Handler .weak I2C2_ER_IRQHandler .thumb_set I2C2_ER_IRQHandler,Default_Handler .weak SPI1_IRQHandler .thumb_set SPI1_IRQHandler,Default_Handler .weak SPI2_IRQHandler .thumb_set SPI2_IRQHandler,Default_Handler .weak USART1_IRQHandler .thumb_set USART1_IRQHandler,Default_Handler .weak USART2_IRQHandler .thumb_set USART2_IRQHandler,Default_Handler .weak USART3_IRQHandler .thumb_set USART3_IRQHandler,Default_Handler .weak EXTI15_10_IRQHandler .thumb_set EXTI15_10_IRQHandler,Default_Handler .weak RTC_Alarm_IRQHandler .thumb_set RTC_Alarm_IRQHandler,Default_Handler .weak OTG_FS_WKUP_IRQHandler .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler .weak TIM8_BRK_TIM12_IRQHandler .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler .weak TIM8_UP_TIM13_IRQHandler .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler .weak TIM8_TRG_COM_TIM14_IRQHandler .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler .weak TIM8_CC_IRQHandler .thumb_set TIM8_CC_IRQHandler,Default_Handler .weak DMA1_Stream7_IRQHandler .thumb_set DMA1_Stream7_IRQHandler,Default_Handler .weak FSMC_IRQHandler .thumb_set FSMC_IRQHandler,Default_Handler .weak SDIO_IRQHandler .thumb_set SDIO_IRQHandler,Default_Handler .weak TIM5_IRQHandler .thumb_set TIM5_IRQHandler,Default_Handler .weak SPI3_IRQHandler .thumb_set SPI3_IRQHandler,Default_Handler .weak UART4_IRQHandler .thumb_set UART4_IRQHandler,Default_Handler .weak UART5_IRQHandler .thumb_set UART5_IRQHandler,Default_Handler .weak TIM6_DAC_IRQHandler .thumb_set TIM6_DAC_IRQHandler,Default_Handler .weak TIM7_IRQHandler .thumb_set TIM7_IRQHandler,Default_Handler .weak DMA2_Stream0_IRQHandler .thumb_set DMA2_Stream0_IRQHandler,Default_Handler .weak DMA2_Stream1_IRQHandler .thumb_set DMA2_Stream1_IRQHandler,Default_Handler .weak DMA2_Stream2_IRQHandler .thumb_set DMA2_Stream2_IRQHandler,Default_Handler .weak DMA2_Stream3_IRQHandler .thumb_set DMA2_Stream3_IRQHandler,Default_Handler .weak DMA2_Stream4_IRQHandler .thumb_set DMA2_Stream4_IRQHandler,Default_Handler .weak ETH_IRQHandler .thumb_set ETH_IRQHandler,Default_Handler .weak ETH_WKUP_IRQHandler .thumb_set ETH_WKUP_IRQHandler,Default_Handler .weak CAN2_TX_IRQHandler .thumb_set CAN2_TX_IRQHandler,Default_Handler .weak CAN2_RX0_IRQHandler .thumb_set CAN2_RX0_IRQHandler,Default_Handler .weak CAN2_RX1_IRQHandler .thumb_set CAN2_RX1_IRQHandler,Default_Handler .weak CAN2_SCE_IRQHandler .thumb_set CAN2_SCE_IRQHandler,Default_Handler .weak OTG_FS_IRQHandler .thumb_set OTG_FS_IRQHandler,Default_Handler .weak DMA2_Stream5_IRQHandler .thumb_set DMA2_Stream5_IRQHandler,Default_Handler .weak DMA2_Stream6_IRQHandler .thumb_set DMA2_Stream6_IRQHandler,Default_Handler .weak DMA2_Stream7_IRQHandler .thumb_set DMA2_Stream7_IRQHandler,Default_Handler .weak USART6_IRQHandler .thumb_set USART6_IRQHandler,Default_Handler .weak I2C3_EV_IRQHandler .thumb_set I2C3_EV_IRQHandler,Default_Handler .weak I2C3_ER_IRQHandler .thumb_set I2C3_ER_IRQHandler,Default_Handler .weak OTG_HS_EP1_OUT_IRQHandler .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler .weak OTG_HS_EP1_IN_IRQHandler .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler .weak OTG_HS_WKUP_IRQHandler .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler .weak OTG_HS_IRQHandler .thumb_set OTG_HS_IRQHandler,Default_Handler .weak DCMI_IRQHandler .thumb_set DCMI_IRQHandler,Default_Handler .weak CRYP_IRQHandler .thumb_set CRYP_IRQHandler,Default_Handler .weak HASH_RNG_IRQHandler .thumb_set HASH_RNG_IRQHandler,Default_Handler .weak FPU_IRQHandler .thumb_set FPU_IRQHandler,Default_Handler /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/src/stm32f4xx_conf.h ================================================ /** ***************************************************************************** ** ** File : stm32f4xx_conf.h ** ** Abstract : STM32F4xx library configuration file ** ** Environment : Atollic TrueSTUDIO(R) ** STMicroelectronics STM32F4xx Standard Peripherals Library ** ** Distribution: The file is distributed as is, without any warranty ** of any kind. ** ** (c)Copyright Atollic AB. ** You may use this file as-is or modify it according to the needs of your ** project. Distribution of this file (unmodified or modified) is not ** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the ** rights to distribute the assembled, compiled & linked contents of this ** file as part of an application binary file, provided that it is built ** using the Atollic TrueSTUDIO(R) toolchain. ** ** ***************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_CONF_H #define __STM32F4xx_CONF_H /* Includes ------------------------------------------------------------------*/ /* Uncomment the line below to enable peripheral header file inclusion */ #include "stm32f4xx_adc.h" #include "stm32f4xx_can.h" #include "stm32f4xx_crc.h" #include "stm32f4xx_cryp.h" #include "stm32f4xx_dac.h" #include "stm32f4xx_dbgmcu.h" #include "stm32f4xx_dcmi.h" #include "stm32f4xx_dma.h" #include "stm32f4xx_exti.h" #include "stm32f4xx_flash.h" #include "stm32f4xx_fsmc.h" #include "stm32f4xx_hash.h" #include "stm32f4xx_gpio.h" #include "stm32f4xx_i2c.h" #include "stm32f4xx_iwdg.h" #include "stm32f4xx_pwr.h" #include "stm32f4xx_rcc.h" #include "stm32f4xx_rng.h" #include "stm32f4xx_rtc.h" #include "stm32f4xx_sdio.h" #include "stm32f4xx_spi.h" #include "stm32f4xx_syscfg.h" #include "stm32f4xx_tim.h" #include "stm32f4xx_usart.h" #include "stm32f4xx_wwdg.h" #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* If an external clock source is used, then the value of the following define should be set to the value of the external clock source, else, if no external clock is used, keep this define commented */ /*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ /* Uncomment the line below to expanse the "assert_param" macro in the Standard Peripheral Library drivers code */ /* #define USE_FULL_ASSERT 1 */ /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT /** * @brief The assert_param macro is used for function's parameters check. * @param expr: If expr is false, it calls assert_failed function * which reports the name of the source file and the source * line number of the call that failed. * If expr is true, it returns no value. * @retval None */ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ void assert_failed(uint8_t* file, uint32_t line); #else #define assert_param(expr) ((void)0) #endif /* USE_FULL_ASSERT */ #endif /* __STM32F45x_CONF_H */ ================================================ FILE: figure-simulator-discovery/src/stm32f4xx_it.c ================================================ /** ***************************************************************************** ** ** File : stm32f4xx_it.c ** ** Abstract : Main Interrupt Service Routines. ** This file provides template for all exceptions handler and ** peripherals interrupt service routine. ** ** Environment : Atollic TrueSTUDIO(R) ** STMicroelectronics STM32F4xx Standard Peripherals Library ** ** Distribution: The file is distributed as is, without any warranty ** of any kind. ** ** (c)Copyright Atollic AB. ** You may use this file as-is or modify it according to the needs of your ** project. Distribution of this file (unmodified or modified) is not ** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the ** rights to distribute the assembled, compiled & linked contents of this ** file as part of an application binary file, provided that it is built ** using the Atollic TrueSTUDIO(R) toolchain. ** ** ***************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_it.h" /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /******************************************************************************/ /* Cortex-M4 Processor Exceptions Handlers */ /******************************************************************************/ /** * @brief This function handles NMI exception. * @param None * @retval None */ void NMI_Handler(void) { } /** * @brief This function handles Hard Fault exception. * @param None * @retval None */ void HardFault_Handler(void) { /* Go to infinite loop when Hard Fault exception occurs */ while (1) { } } /** * @brief This function handles Memory Manage exception. * @param None * @retval None */ void MemManage_Handler(void) { /* Go to infinite loop when Memory Manage exception occurs */ while (1) { } } /** * @brief This function handles Bus Fault exception. * @param None * @retval None */ void BusFault_Handler(void) { /* Go to infinite loop when Bus Fault exception occurs */ while (1) { } } /** * @brief This function handles Usage Fault exception. * @param None * @retval None */ void UsageFault_Handler(void) { /* Go to infinite loop when Usage Fault exception occurs */ while (1) { } } /** * @brief This function handles SVCall exception. * @param None * @retval None */ void SVC_Handler(void) { } /** * @brief This function handles Debug Monitor exception. * @param None * @retval None */ void DebugMon_Handler(void) { } /** * @brief This function handles PendSVC exception. * @param None * @retval None */ void PendSV_Handler(void) { } /** * @brief This function handles SysTick Handler. * @param None * @retval None */ void SysTick_Handler(void) { } /******************************************************************************/ /* STM32F4xx Peripherals Interrupt Handlers */ /* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ /* available peripheral interrupt handler's name please refer to the startup */ /* file (startup_stm32f4xx.s). */ /******************************************************************************/ /** * @brief This function handles PPP interrupt request. * @param None * @retval None */ /*void PPP_IRQHandler(void) { }*/ ================================================ FILE: figure-simulator-discovery/src/stm32f4xx_it.h ================================================ /** ***************************************************************************** ** ** File : stm32f4xx_it.h ** ** Abstract : Main Interrupt Service Routines. ** This file provides template for all exceptions handler and ** peripherals interrupt service routine. ** ** Environment : Atollic TrueSTUDIO(R) ** STMicroelectronics STM32F4xx Standard Peripherals Library ** ** Distribution: The file is distributed as is, without any warranty ** of any kind. ** ** (c)Copyright Atollic AB. ** You may use this file as-is or modify it according to the needs of your ** project. Distribution of this file (unmodified or modified) is not ** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the ** rights to distribute the assembled, compiled & linked contents of this ** file as part of an application binary file, provided that it is built ** using the Atollic TrueSTUDIO(R) toolchain. ** ** ***************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_IT_H #define __STM32F4xx_IT_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ void NMI_Handler(void); void HardFault_Handler(void); void MemManage_Handler(void); void BusFault_Handler(void); void UsageFault_Handler(void); void SVC_Handler(void); void DebugMon_Handler(void); void PendSV_Handler(void); void SysTick_Handler(void); #ifdef __cplusplus } #endif #endif /* __STM32F4xx_IT_H */ ================================================ FILE: figure-simulator-discovery/src/system_stm32f4xx.c ================================================ /** ****************************************************************************** * @file system_stm32f4xx.c * @author MCD Application Team * @version V1.0.0 * @date 19-September-2011 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. * This file contains the system clock configuration for STM32F4xx devices, * and is generated by the clock configuration tool * stm32f4xx_Clock_Configuration_V1.0.0.xls * * 1. This file provides two functions and one global variable to be called from * user application: * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier * and Divider factors, AHB/APBx prescalers and Flash settings), * depending on the configuration made in the clock xls tool. * This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32f4xx.s" file. * * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used * by the user application to setup the SysTick * timer or configure other parameters. * * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must * be called whenever the core clock is changed * during program execution. * * 2. After each device reset the HSI (16 MHz) is used as system clock source. * Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to * configure the system clock before to branch to main program. * * 3. If the system clock source selected by user fails to startup, the SystemInit() * function will do nothing and HSI still used as system clock source. User can * add some code to deal with this issue inside the SetSysClock() function. * * 4. The default value of HSE crystal is set to 8 MHz, refer to "HSE_VALUE" define * in "stm32f4xx.h" file. When HSE is used as system clock source, directly or * through PLL, and you are using different crystal you have to adapt the HSE * value to your own configuration. * * 5. This file configures the system clock as follows: *============================================================================= *============================================================================= * Supported STM32F4xx device revision | Rev A *----------------------------------------------------------------------------- * System Clock source | PLL (HSE) *----------------------------------------------------------------------------- * SYSCLK(Hz) | 168000000 *----------------------------------------------------------------------------- * HCLK(Hz) | 168000000 *----------------------------------------------------------------------------- * AHB Prescaler | 1 *----------------------------------------------------------------------------- * APB1 Prescaler | 4 *----------------------------------------------------------------------------- * APB2 Prescaler | 2 *----------------------------------------------------------------------------- * HSE Frequency(Hz) | 8000000 *----------------------------------------------------------------------------- * PLL_M | 8 *----------------------------------------------------------------------------- * PLL_N | 336 *----------------------------------------------------------------------------- * PLL_P | 2 *----------------------------------------------------------------------------- * PLL_Q | 7 *----------------------------------------------------------------------------- * PLLI2S_N | NA *----------------------------------------------------------------------------- * PLLI2S_R | NA *----------------------------------------------------------------------------- * I2S input clock | NA *----------------------------------------------------------------------------- * VDD(V) | 3.3 *----------------------------------------------------------------------------- * High Performance mode | Enabled *----------------------------------------------------------------------------- * Flash Latency(WS) | 5 *----------------------------------------------------------------------------- * Prefetch Buffer | OFF *----------------------------------------------------------------------------- * Instruction cache | ON *----------------------------------------------------------------------------- * Data cache | ON *----------------------------------------------------------------------------- * Require 48MHz for USB OTG FS, | Enabled * SDIO and RNG clock | *----------------------------------------------------------------------------- *============================================================================= ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * *

© COPYRIGHT 2011 STMicroelectronics

****************************************************************************** */ /** @addtogroup CMSIS * @{ */ /** @addtogroup stm32f4xx_system * @{ */ /** @addtogroup STM32F4xx_System_Private_Includes * @{ */ #include "stm32f4xx.h" /** * @} */ /** @addtogroup STM32F4xx_System_Private_TypesDefinitions * @{ */ /** * @} */ /** @addtogroup STM32F4xx_System_Private_Defines * @{ */ /*!< Uncomment the following line if you need to use external SRAM mounted on STM324xG_EVAL board as data memory */ /* #define DATA_IN_ExtSRAM */ /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ /* #define VECT_TAB_SRAM */ #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ #define PLL_M 8 #define PLL_N 500 /* SYSCLK = PLL_VCO / PLL_P */ #define PLL_P 2 /* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ #define PLL_Q 7 /** * @} */ /** @addtogroup STM32F4xx_System_Private_Macros * @{ */ /** * @} */ /** @addtogroup STM32F4xx_System_Private_Variables * @{ */ uint32_t SystemCoreClock = 168000000; __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} */ /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes * @{ */ static void SetSysClock(void); #ifdef DATA_IN_ExtSRAM static void SystemInit_ExtMemCtl(void); #endif /* DATA_IN_ExtSRAM */ /** * @} */ /** @addtogroup STM32F4xx_System_Private_Functions * @{ */ /** * @brief Setup the microcontroller system * Initialize the Embedded Flash Interface, the PLL and update the * SystemFrequency variable. * @param None * @retval None */ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ RCC->CR |= (uint32_t)0x00000001; /* Reset CFGR register */ RCC->CFGR = 0x00000000; /* Reset HSEON, CSSON and PLLON bits */ RCC->CR &= (uint32_t)0xFEF6FFFF; /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x24003010; /* Reset HSEBYP bit */ RCC->CR &= (uint32_t)0xFFFBFFFF; /* Disable all interrupts */ RCC->CIR = 0x00000000; #ifdef DATA_IN_ExtSRAM SystemInit_ExtMemCtl(); #endif /* DATA_IN_ExtSRAM */ /* Configure the System clock source, PLL Multiplier and Divider factors, AHB/APBx prescalers and Flash settings ----------------------------------*/ SetSysClock(); /* Configure the Vector Table location add offset address ------------------*/ #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ #endif } /** * @brief Update SystemCoreClock variable according to Clock Register Values. * The SystemCoreClock variable contains the core clock (HCLK), it can * be used by the user application to setup the SysTick timer or configure * other parameters. * * @note Each time the core clock (HCLK) changes, this function must be called * to update SystemCoreClock variable value. Otherwise, any configuration * based on this variable will be incorrect. * * @note - The system frequency computed by this function is not the real * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: * * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) * * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) * * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) * or HSI_VALUE(*) multiplied/divided by the PLL factors. * * (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value * 16 MHz) but the real value may vary depending on the variations * in voltage and temperature. * * (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value * 25 MHz), user has to ensure that HSE_VALUE is same as the real * frequency of the crystal used. Otherwise, this function may * have wrong result. * * - The result of this function could be not correct when using fractional * value for HSE crystal. * * @param None * @retval None */ void SystemCoreClockUpdate(void) { uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; switch (tmp) { case 0x00: /* HSI used as system clock source */ SystemCoreClock = HSI_VALUE; break; case 0x04: /* HSE used as system clock source */ SystemCoreClock = HSE_VALUE; break; case 0x08: /* PLL used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N SYSCLK = PLL_VCO / PLL_P */ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; if (pllsource != 0) { /* HSE used as PLL clock source */ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); } else { /* HSI used as PLL clock source */ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); } pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; SystemCoreClock = pllvco/pllp; break; default: SystemCoreClock = HSI_VALUE; break; } /* Compute HCLK frequency --------------------------------------------------*/ /* Get HCLK prescaler */ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; /* HCLK frequency */ SystemCoreClock >>= tmp; } /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings * @Note This function should be called only once the RCC clock configuration * is reset to the default reset state (done in SystemInit() function). * @param None * @retval None */ static void SetSysClock(void) { /******************************************************************************/ /* PLL (clocked by HSE) used as System clock source */ /******************************************************************************/ __IO uint32_t StartUpCounter = 0, HSEStatus = 0; /* Enable HSE */ RCC->CR |= ((uint32_t)RCC_CR_HSEON); /* Wait till HSE is ready and if Time out is reached exit */ do { HSEStatus = RCC->CR & RCC_CR_HSERDY; StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); if ((RCC->CR & RCC_CR_HSERDY) != RESET) { HSEStatus = (uint32_t)0x01; } else { HSEStatus = (uint32_t)0x00; } if (HSEStatus == (uint32_t)0x01) { /* Enable high performance mode, System frequency up to 168 MHz */ RCC->APB1ENR |= RCC_APB1ENR_PWREN; PWR->CR |= PWR_CR_PMODE; /* HCLK = SYSCLK / 1*/ RCC->CFGR |= RCC_CFGR_HPRE_DIV1; /* PCLK2 = HCLK / 2*/ RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; /* PCLK1 = HCLK / 4*/ RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; /* Configure the main PLL */ RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); /* Enable the main PLL */ RCC->CR |= RCC_CR_PLLON; /* Wait till the main PLL is ready */ while((RCC->CR & RCC_CR_PLLRDY) == 0) { } /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS; /* Select the main PLL as system clock source */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); RCC->CFGR |= RCC_CFGR_SW_PLL; /* Wait till the main PLL is used as system clock source */ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); { } } else { /* If HSE fails to start-up, the application will have wrong clock configuration. User can add here some code to deal with this error */ } } /** * @brief Setup the external memory controller. Called in startup_stm32f4xx.s * before jump to __main * @param None * @retval None */ #ifdef DATA_IN_ExtSRAM /** * @brief Setup the external memory controller. * Called in startup_stm32f4xx.s before jump to main. * This function configures the external SRAM mounted on STM324xG_EVAL board * This SRAM will be used as program data memory (including heap and stack). * @param None * @retval None */ void SystemInit_ExtMemCtl(void) { /*-- GPIOs Configuration -----------------------------------------------------*/ /* +-------------------+--------------------+------------------+------------------+ + SRAM pins assignment + +-------------------+--------------------+------------------+------------------+ | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | | PD4 <-> FSMC_NOE | PE3 <-> FSMC_A19 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | | PD5 <-> FSMC_NWE | PE4 <-> FSMC_A20 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | | PD8 <-> FSMC_D13 | PE7 <-> FSMC_D4 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | | PD9 <-> FSMC_D14 | PE8 <-> FSMC_D5 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | | PD10 <-> FSMC_D15 | PE9 <-> FSMC_D6 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | | PD11 <-> FSMC_A16 | PE10 <-> FSMC_D7 | PF13 <-> FSMC_A7 |------------------+ | PD12 <-> FSMC_A17 | PE11 <-> FSMC_D8 | PF14 <-> FSMC_A8 | | PD13 <-> FSMC_A18 | PE12 <-> FSMC_D9 | PF15 <-> FSMC_A9 | | PD14 <-> FSMC_D0 | PE13 <-> FSMC_D10 |------------------+ | PD15 <-> FSMC_D1 | PE14 <-> FSMC_D11 | | | PE15 <-> FSMC_D12 | +-------------------+--------------------+ */ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ RCC->AHB1ENR = 0x00000078; /* Connect PDx pins to FSMC Alternate function */ GPIOD->AFR[0] = 0x00cc00cc; GPIOD->AFR[1] = 0xcc0ccccc; /* Configure PDx pins in Alternate function mode */ GPIOD->MODER = 0xaaaa0a0a; /* Configure PDx pins speed to 100 MHz */ GPIOD->OSPEEDR = 0xffff0f0f; /* Configure PDx pins Output type to push-pull */ GPIOD->OTYPER = 0x00000000; /* No pull-up, pull-down for PDx pins */ GPIOD->PUPDR = 0x00000000; /* Connect PEx pins to FSMC Alternate function */ GPIOE->AFR[0] = 0xc00cc0cc; GPIOE->AFR[1] = 0xcccccccc; /* Configure PEx pins in Alternate function mode */ GPIOE->MODER = 0xaaaa828a; /* Configure PEx pins speed to 100 MHz */ GPIOE->OSPEEDR = 0xffffc3cf; /* Configure PEx pins Output type to push-pull */ GPIOE->OTYPER = 0x00000000; /* No pull-up, pull-down for PEx pins */ GPIOE->PUPDR = 0x00000000; /* Connect PFx pins to FSMC Alternate function */ GPIOF->AFR[0] = 0x00cccccc; GPIOF->AFR[1] = 0xcccc0000; /* Configure PFx pins in Alternate function mode */ GPIOF->MODER = 0xaa000aaa; /* Configure PFx pins speed to 100 MHz */ GPIOF->OSPEEDR = 0xff000fff; /* Configure PFx pins Output type to push-pull */ GPIOF->OTYPER = 0x00000000; /* No pull-up, pull-down for PFx pins */ GPIOF->PUPDR = 0x00000000; /* Connect PGx pins to FSMC Alternate function */ GPIOG->AFR[0] = 0x00cccccc; GPIOG->AFR[1] = 0x000000c0; /* Configure PGx pins in Alternate function mode */ GPIOG->MODER = 0x00080aaa; /* Configure PGx pins speed to 100 MHz */ GPIOG->OSPEEDR = 0x000c0fff; /* Configure PGx pins Output type to push-pull */ GPIOG->OTYPER = 0x00000000; /* No pull-up, pull-down for PGx pins */ GPIOG->PUPDR = 0x00000000; /*-- FSMC Configuration ------------------------------------------------------*/ /* Enable the FSMC interface clock */ RCC->AHB3ENR = 0x00000001; /* Configure and enable Bank1_SRAM2 */ FSMC_Bank1->BTCR[2] = 0x00001015; FSMC_Bank1->BTCR[3] = 0x00010603;//0x00010400; FSMC_Bank1E->BWTR[2] = 0x0fffffff; /* Bank1_SRAM2 is configured as follow: p.FSMC_AddressSetupTime = 3;//0; p.FSMC_AddressHoldTime = 0; p.FSMC_DataSetupTime = 6;//4; p.FSMC_BusTurnAroundDuration = 1; p.FSMC_CLKDivision = 0; p.FSMC_DataLatency = 0; p.FSMC_AccessMode = FSMC_AccessMode_A; FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; */ } #endif /* DATA_IN_ExtSRAM */ /** * @} */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ ================================================ FILE: figure-simulator-discovery/src/tiny_printf.c ================================================ /** ***************************************************************************** ** ** File : tiny_printf.c ** ** Abstract : Atollic TrueSTUDIO Minimal printf/sprintf/fprintf ** and puts/fputs ** ** The argument contains a format string that may include ** conversion specifications. Each conversion specification ** is introduced by the character %, and ends with a ** conversion specifier. ** ** The following conversion specifiers are supported ** cdisuxX% ** ** Usage: ** c character ** d,i signed integer (-sign added, + sign not supported) ** s character string ** u unsigned integer as decimal ** x,X unsigned integer as hexadecimal (uppercase letter) ** % % is written (conversion specification is '%%') ** ** Note: ** Character padding is not supported ** ** Environment : Atollic TrueSTUDIO ** ** Distribution: The file is distributed as is, without any warranty ** of any kind. ** ** (c)Copyright Atollic AB. ** You may use this file as-is or modify it according to the needs of your ** project. Distribution of this file (unmodified or modified) is not ** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the ** rights to distribute the assembled, compiled & linked contents of this ** file as part of an application binary file, provided that it is built ** using the Atollic TrueSTUDIO(R) Pro toolchain. ** ***************************************************************************** */ /* Includes */ #include #include #include /* External function prototypes (defined in syscalls.c) */ extern int _write(int fd, char *str, int len); /* Private function prototypes */ void ts_itoa(char **buf, unsigned int d, int base); int ts_formatstring(char *buf, const char *fmt, va_list va); int ts_formatlength(const char *fmt, va_list va); /* Private functions */ /** **--------------------------------------------------------------------------- ** Abstract: Convert integer to ascii ** Returns: void **--------------------------------------------------------------------------- */ void ts_itoa(char **buf, unsigned int d, int base) { int div = 1; while (d/div >= base) div *= base; while (div != 0) { int num = d/div; d = d%div; div /= base; if (num > 9) *((*buf)++) = (num-10) + 'A'; else *((*buf)++) = num + '0'; } } /** **--------------------------------------------------------------------------- ** Abstract: Writes arguments va to buffer buf according to format fmt ** Returns: Length of string **--------------------------------------------------------------------------- */ int ts_formatstring(char *buf, const char *fmt, va_list va) { char *start_buf = buf; while(*fmt) { /* Character needs formating? */ if (*fmt == '%') { switch (*(++fmt)) { case 'c': *buf++ = va_arg(va, int); break; case 'd': case 'i': { signed int val = va_arg(va, signed int); if (val < 0) { val *= -1; *buf++ = '-'; } ts_itoa(&buf, val, 10); } break; case 's': { char * arg = va_arg(va, char *); while (*arg) { *buf++ = *arg++; } } break; case 'u': ts_itoa(&buf, va_arg(va, unsigned int), 10); break; case 'x': case 'X': ts_itoa(&buf, va_arg(va, int), 16); break; case '%': *buf++ = '%'; break; } fmt++; } /* Else just copy */ else { *buf++ = *fmt++; } } *buf = 0; return (int)(buf - start_buf); } /** **--------------------------------------------------------------------------- ** Abstract: Calculate maximum length of the resulting string from the ** format string and va_list va ** Returns: Maximum length **--------------------------------------------------------------------------- */ int ts_formatlength(const char *fmt, va_list va) { int length = 0; while (*fmt) { if (*fmt == '%') { ++fmt; switch (*fmt) { case 'c': va_arg(va, int); ++length; break; case 'd': case 'i': case 'u': /* 32 bits integer is max 11 characters with minus sign */ length += 11; va_arg(va, int); break; case 's': { char * str = va_arg(va, char *); while (*str++) ++length; } break; case 'x': case 'X': /* 32 bits integer as hex is max 8 characters */ length += 8; va_arg(va, unsigned int); break; default: ++length; break; } } else { ++length; } ++fmt; } return length; } /** **=========================================================================== ** Abstract: Loads data from the given locations and writes them to the ** given character string according to the format parameter. ** Returns: Number of bytes written **=========================================================================== */ int sprintf(char *buf, const char *fmt, ...) { int length; va_list va; va_start(va, fmt); length = ts_formatstring(buf, fmt, va); va_end(va); return length; } /** **=========================================================================== ** Abstract: Loads data from the given locations and writes them to the ** given file stream according to the format parameter. ** Returns: Number of bytes written **=========================================================================== */ int fprintf(FILE * stream, const char *fmt, ...) { int length = 0; va_list va; va_start(va, fmt); length = ts_formatlength(fmt, va); va_end(va); { char buf[length]; va_start(va, fmt); length = ts_formatstring(buf, fmt, va); length = _write(stream->_file, buf, length); va_end(va); } return length; } /** **=========================================================================== ** Abstract: Loads data from the given locations and writes them to the ** standard output according to the format parameter. ** Returns: Number of bytes written ** **=========================================================================== */ int printf(const char *fmt, ...) { int length = 0; va_list va; va_start(va, fmt); length = ts_formatlength(fmt, va); va_end(va); { char buf[length]; va_start(va, fmt); length = ts_formatstring(buf, fmt, va); length = _write(1, buf, length); va_end(va); } return length; } /** **=========================================================================== ** Abstract: fputs writes the string at s (but without the trailing null) to ** the file or stream identified by fp. ** Returns: If successful, the result is 0; otherwise, the result is EOF. ** **=========================================================================== */ int fputs(const char *s, FILE *fp) { int length = strlen(s); int wlen = 0; int res; wlen = _write((fp->_file), (char*)s, length); wlen += _write((fp->_file), "\n", 1); if (wlen == (length+1)) { res = 0; } else { res = EOF; } return res; } /** **=========================================================================== ** Abstract: puts writes the string at s (followed by a newline, instead of ** the trailing null) to the standard output stream. ** Returns: If successful, the result is a nonnegative integer; otherwise, ** the result is EOF. ** **=========================================================================== */ int puts(const char *s) { int length = strlen(s); int numbytes = 0; int res; numbytes = _write(1, (char*)s, length); numbytes += _write(1, "\n", 1); if (numbytes == (length+1)) { res = 0; } else { res = EOF; } return res; } ================================================ FILE: figure-simulator-discovery/stm32f4_flash.ld ================================================ /* ***************************************************************************** ** ** File : stm32_flash.ld ** ** Abstract : Linker script for STM32F407VG Device with ** 1024KByte FLASH, 128KByte RAM ** ** Set heap size, stack size and stack location according ** to application requirements. ** ** Set memory bank area and size if external memory is used. ** ** Target : STMicroelectronics STM32 ** ** Environment : Atollic TrueSTUDIO(R) ** ** Distribution: The file is distributed as is, without any warranty ** of any kind. ** ** (c)Copyright Atollic AB. ** You may use this file as-is or modify it according to the needs of your ** project. Distribution of this file (unmodified or modified) is not ** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the ** rights to distribute the assembled, compiled & linked contents of this ** file as part of an application binary file, provided that it is built ** using the Atollic TrueSTUDIO(R) toolchain. ** ***************************************************************************** */ /* Entry Point */ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = 0x20020000; /* end of 128K RAM */ /* Generate a link error if heap and stack don't fit into RAM */ _Min_Heap_Size = 0; /* required amount of heap */ _Min_Stack_Size = 0x400; /* required amount of stack */ /* Specify the memory areas */ MEMORY { FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K CCMRAM (rw) : ORIGIN = 0x10000000, LENGTH = 64K } /* Define output sections */ SECTIONS { /* The startup code goes first into FLASH */ .isr_vector : { . = ALIGN(4); KEEP(*(.isr_vector)) /* Startup code */ . = ALIGN(4); } >FLASH /* The program code and other data goes into FLASH */ .text : { . = ALIGN(4); *(.text) /* .text sections (code) */ *(.text*) /* .text* sections (code) */ *(.rodata) /* .rodata sections (constants, strings, etc.) */ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ *(.glue_7) /* glue arm to thumb code */ *(.glue_7t) /* glue thumb to arm code */ *(.eh_frame) KEEP (*(.init)) KEEP (*(.fini)) . = ALIGN(4); _etext = .; /* define a global symbols at end of code */ } >FLASH .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH .ARM : { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) KEEP (*(.fini_array*)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH /* used by the startup to initialize data */ _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ *(.data) /* .data sections */ *(.data*) /* .data* sections */ . = ALIGN(4); _edata = .; /* define a global symbol at data end */ } >RAM AT> FLASH _siccmram = LOADADDR(.ccmram); /* CCM-RAM section * * IMPORTANT NOTE! * If initialized variables will be placed in this section, * the startup code needs to be modified to copy the init-values. */ .ccmram : { . = ALIGN(4); _sccmram = .; /* create a global symbol at ccmram start */ *(.ccmram) *(.ccmram*) . = ALIGN(4); _eccmram = .; /* create a global symbol at ccmram end */ } >CCMRAM AT> FLASH /* Uninitialized data section */ . = ALIGN(4); .bss : { /* This is used by the startup in order to initialize the .bss secion */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) *(.bss*) *(COMMON) . = ALIGN(4); _ebss = .; /* define a global symbol at bss end */ __bss_end__ = _ebss; } >RAM /* User_heap_stack section, used to check that there is enough RAM left */ ._user_heap_stack : { . = ALIGN(4); PROVIDE ( end = . ); PROVIDE ( _end = . ); . = . + _Min_Heap_Size; . = . + _Min_Stack_Size; . = ALIGN(4); } >RAM /* MEMORY_bank1 section, code must be located here explicitly */ /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */ .memory_b1_text : { *(.mb1text) /* .mb1text sections (code) */ *(.mb1text*) /* .mb1text* sections (code) */ *(.mb1rodata) /* read-only data (constants) */ *(.mb1rodata*) } >MEMORY_B1 /* Remove information from the standard libraries */ /DISCARD/ : { libc.a ( * ) libm.a ( * ) libgcc.a ( * ) } .ARM.attributes 0 : { *(.ARM.attributes) } } ================================================ FILE: imageformats/README ================================================ Repository for Tamagotchi image coverters! conv.py -- converts a 16 bit bitmap to a Tamagotchi image Questions? Comments? Contributions? Contact: namely_audacious@hotmail.com / @natashenka ================================================ FILE: imageformats/conv.py ================================================ s = "" tmp = 0 rol = 0 import Image im = Image.open("../../../pictures/harlem/title.bmp") def tofourbit(a): #print a if ((a > -1) and (a < 1)): return 3; if ((a > 0) and (a < 8)): return 2; if ((a > 7) and (a < 10 )): return 1; if (a > 9): return 0; def conv(a): t = 0; t = t | (tofourbit(ord(a) & 0x0f) << 2) t = t | (tofourbit((ord(a) & 0xf0) >> 4)) return t i = 0 width = im.size[0] height = im.size[1] while ( i < (width * height) ): tmp = 0; #print "start" #if( (i + 1)% 17) == 0: # tmp = tmp | tofourbit(im.getpixel(((i)%17, (i)/17))) # i = i + 1 # tmp = tmp << 6 #else: if(1): for j in range(0, 4): tmp = tmp | tofourbit(im.getpixel(((i)%width, (i)/width))) i = i + 1 if j != 3: tmp = tmp * 4 #print tmp #print tmp s = s + chr(tmp) f = open("pic.txt", 'ab') f.write(chr(width)) f.write(chr(height)) f.write(s) print len(s) ================================================ FILE: slides/recon.ppt ================================================ [File too large to display: 34.5 MB]