[
  {
    "path": ".github/ISSUE_TEMPLATE/issue-description.md",
    "content": "---\nname: Issue description\nabout: Please report issue by this template\ntitle: ''\nlabels: ''\nassignees: ''\n\n---\n\n0. Could you send email to xianjun.jiao@ugent.be to introduce your self?\n\n1. Our image is used directly or you build your own image?\n\n2. What is your own modification?\n\n3. Versions: OS, Vivado, openwifi/openwifi-hw repo branch and commit revision\n\n4. Board/hardware type\n\n5. WiFi channel number\n\n6. Steps to reproduce the issue, and the related error message, screenshot, etc\n\n7. Describe your debug efforts by Linux native tools, such as tcpdump and \"cat /proc/interrupts\"\n\n8. Describe your debug efforts by: https://github.com/open-sdr/openwifi/blob/master/doc/README.md#Debug-methods\n\n9. Any other thing we need to know for helping you better? \n"
  },
  {
    "path": ".gitmodules",
    "content": "[submodule \"adi-linux\"]\n\tpath = adi-linux\n\turl = https://github.com/analogdevicesinc/linux.git\n[submodule \"adi-linux-64\"]\n\tpath = adi-linux-64\n\turl = https://github.com/analogdevicesinc/linux.git\n"
  },
  {
    "path": "CONTRIBUTING.md",
    "content": "<!--\nAuthor: Xianjun jiao\nSPDX-FileCopyrightText: 2019 UGent\nSPDX-License-Identifier: AGPL-3.0-or-later\n-->\n\nCLA([Individual](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/openwifi-Individual.pdf), [Entity](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/openwifi-Entity.pdf)) needs to be signed and sent to Filip.Louagie@UGent.be before you contributing.\n\nCLA is generated by the [Project Harmony](http://www.harmonyagreements.org/index.html).\n"
  },
  {
    "path": "LICENSE",
    "content": "                    GNU AFFERO GENERAL PUBLIC LICENSE\n                       Version 3, 19 November 2007\n\n Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>\n Everyone is permitted to copy and distribute verbatim copies\n of this license document, but changing it is not allowed.\n\n                            Preamble\n\n  The GNU Affero General Public License is a free, copyleft license for\nsoftware and other kinds of works, specifically designed to ensure\ncooperation with the community in the case of network server software.\n\n  The licenses for most software and other practical works are designed\nto take away your freedom to share and change the works.  By contrast,\nour General Public Licenses are intended to guarantee your freedom to\nshare and change all versions of a program--to make sure it remains free\nsoftware for all its users.\n\n  When we speak of free software, we are referring to freedom, not\nprice.  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If the Program does not specify a version number of the\nGNU Affero General Public License, you may choose any version ever published\nby the Free Software Foundation.\n\n  If the Program specifies that a proxy can decide which future\nversions of the GNU Affero General Public License can be used, that proxy's\npublic statement of acceptance of a version permanently authorizes you\nto choose that version for the Program.\n\n  Later license versions may give you additional or different\npermissions.  However, no additional obligations are imposed on any\nauthor or copyright holder as a result of your choosing to follow a\nlater version.\n\n  15. Disclaimer of Warranty.\n\n  THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY\nAPPLICABLE LAW.  EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT\nHOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM \"AS IS\" WITHOUT WARRANTY\nOF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,\nTHE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\nPURPOSE.  THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM\nIS WITH YOU.  SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF\nALL NECESSARY SERVICING, REPAIR OR CORRECTION.\n\n  16. Limitation of Liability.\n\n  IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING\nWILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS\nTHE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY\nGENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE\nUSE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF\nDATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD\nPARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),\nEVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF\nSUCH DAMAGES.\n\n  17. Interpretation of Sections 15 and 16.\n\n  If the disclaimer of warranty and limitation of liability provided\nabove cannot be given local legal effect according to their terms,\nreviewing courts shall apply local law that most closely approximates\nan absolute waiver of all civil liability in connection with the\nProgram, unless a warranty or assumption of liability accompanies a\ncopy of the Program in return for a fee.\n\n                     END OF TERMS AND CONDITIONS\n\n            How to Apply These Terms to Your New Programs\n\n  If you develop a new program, and you want it to be of the greatest\npossible use to the public, the best way to achieve this is to make it\nfree software which everyone can redistribute and change under these terms.\n\n  To do so, attach the following notices to the program.  It is safest\nto attach them to the start of each source file to most effectively\nstate the exclusion of warranty; and each file should have at least\nthe \"copyright\" line and a pointer to where the full notice is found.\n\n    <one line to give the program's name and a brief idea of what it does.>\n    Copyright (C) <year>  <name of author>\n\n    This program is free software: you can redistribute it and/or modify\n    it under the terms of the GNU Affero General Public License as published by\n    the Free Software Foundation, either version 3 of the License, or\n    (at your option) any later version.\n\n    This program is distributed in the hope that it will be useful,\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n    GNU Affero General Public License for more details.\n\n    You should have received a copy of the GNU Affero General Public License\n    along with this program.  If not, see <http://www.gnu.org/licenses/>.\n\nAlso add information on how to contact you by electronic and paper mail.\n\n  If your software can interact with users remotely through a computer\nnetwork, you should also make sure that it provides a way for users to\nget its source.  For example, if your program is a web application, its\ninterface could display a \"Source\" link that leads users to an archive\nof the code.  There are many ways you could offer source, and different\nsolutions will be better for different programs; see section 13 for the\nspecific requirements.\n\n  You should also get your employer (if you work as a programmer) or school,\nif any, to sign a \"copyright disclaimer\" for the program, if necessary.\nFor more information on this, and how to apply and follow the GNU AGPL, see\n<http://www.gnu.org/licenses/>.\n"
  },
  {
    "path": "LICENSES/AGPL-3.0-or-later.txt",
    "content": "                    GNU AFFERO GENERAL PUBLIC LICENSE\n                       Version 3, 19 November 2007\n\n Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>\n Everyone is permitted to copy and distribute verbatim copies\n of this license document, but changing it is not allowed.\n\n                            Preamble\n\n  The GNU Affero General Public License is a free, copyleft license for\nsoftware and other kinds of works, specifically designed to ensure\ncooperation with the community in the case of network server software.\n\n  The licenses for most software and other practical works are designed\nto take away your freedom to share and change the works.  By contrast,\nour General Public Licenses are intended to guarantee your freedom to\nshare and change all versions of a program--to make sure it remains free\nsoftware for all its users.\n\n  When we speak of free software, we are referring to freedom, not\nprice.  Our General Public Licenses are designed to make sure that you\nhave the freedom to distribute copies of free software (and charge for\nthem if you wish), that you receive source code or can get it if you\nwant it, that you can change the software or use pieces of it in new\nfree programs, and that you know you can do these things.\n\n  Developers that use our General Public Licenses protect your rights\nwith two steps: (1) assert copyright on the software, and (2) offer\nyou this License which gives you legal permission to copy, distribute\nand/or modify the software.\n\n  A secondary benefit of defending all users' freedom is that\nimprovements made in alternate versions of the program, if they\nreceive widespread use, become available for other developers to\nincorporate.  Many developers of free software are heartened and\nencouraged by the resulting cooperation.  However, in the case of\nsoftware used on network servers, this result may fail to come about.\nThe GNU General Public License permits making a modified version and\nletting the public access it on a server without ever releasing its\nsource code to the public.\n\n  The GNU Affero General Public License is designed specifically to\nensure that, in such cases, the modified source code becomes available\nto the community.  It requires the operator of a network server to\nprovide the source code of the modified version running there to the\nusers of that server.  Therefore, public use of a modified version, on\na publicly accessible server, gives the public access to the source\ncode of the modified version.\n\n  An older license, called the Affero General Public License and\npublished by Affero, was designed to accomplish similar goals.  This is\na different license, not a version of the Affero GPL, but Affero has\nreleased a new version of the Affero GPL which permits relicensing under\nthis license.\n\n  The precise terms and conditions for copying, distribution and\nmodification follow.\n\n                       TERMS AND CONDITIONS\n\n  0. Definitions.\n\n  \"This License\" refers to version 3 of the GNU Affero General Public License.\n\n  \"Copyright\" also means copyright-like laws that apply to other kinds of\nworks, such as semiconductor masks.\n\n  \"The Program\" refers to any copyrightable work licensed under this\nLicense.  Each licensee is addressed as \"you\".  \"Licensees\" and\n\"recipients\" may be individuals or organizations.\n\n  To \"modify\" a work means to copy from or adapt all or part of the work\nin a fashion requiring copyright permission, other than the making of an\nexact copy.  The resulting work is called a \"modified version\" of the\nearlier work or a work \"based on\" the earlier work.\n\n  A \"covered work\" means either the unmodified Program or a work based\non the Program.\n\n  To \"propagate\" a work means to do anything with it that, without\npermission, would make you directly or secondarily liable for\ninfringement under applicable copyright law, except executing it on a\ncomputer or modifying a private copy.  Propagation includes copying,\ndistribution (with or without modification), making available to the\npublic, and in some countries other activities as well.\n\n  To \"convey\" a work means any kind of propagation that enables other\nparties to make or receive copies.  Mere interaction with a user through\na computer network, with no transfer of a copy, is not conveying.\n\n  An interactive user interface displays \"Appropriate Legal Notices\"\nto the extent that it includes a convenient and prominently visible\nfeature that (1) displays an appropriate copyright notice, and (2)\ntells the user that there is no warranty for the work (except to the\nextent that warranties are provided), that licensees may convey the\nwork under this License, and how to view a copy of this License.  If\nthe interface presents a list of user commands or options, such as a\nmenu, a prominent item in the list meets this criterion.\n\n  1. Source Code.\n\n  The \"source code\" for a work means the preferred form of the work\nfor making modifications to it.  \"Object code\" means any non-source\nform of a work.\n\n  A \"Standard Interface\" means an interface that either is an official\nstandard defined by a recognized standards body, or, in the case of\ninterfaces specified for a particular programming language, one that\nis widely used among developers working in that language.\n\n  The \"System Libraries\" of an executable work include anything, other\nthan the work as a whole, that (a) is included in the normal form of\npackaging a Major Component, but which is not part of that Major\nComponent, and (b) serves only to enable use of the work with that\nMajor Component, or to implement a Standard Interface for which an\nimplementation is available to the public in source code form.  A\n\"Major Component\", in this context, means a major essential component\n(kernel, window system, and so on) of the specific operating system\n(if any) on which the executable work runs, or a compiler used to\nproduce the work, or an object code interpreter used to run it.\n\n  The \"Corresponding Source\" for a work in object code form means all\nthe source code needed to generate, install, and (for an executable\nwork) run the object code and to modify the work, including scripts to\ncontrol those activities.  However, it does not include the work's\nSystem Libraries, or general-purpose tools or generally available free\nprograms which are used unmodified in performing those activities but\nwhich are not part of the work.  For example, Corresponding Source\nincludes interface definition files associated with source files for\nthe work, and the source code for shared libraries and dynamically\nlinked subprograms that the work is specifically designed to require,\nsuch as by intimate data communication or control flow between those\nsubprograms and other parts of the work.\n\n  The Corresponding Source need not include anything that users\ncan regenerate automatically from other parts of the Corresponding\nSource.\n\n  The Corresponding Source for a work in source code form is that\nsame work.\n\n  2. Basic Permissions.\n\n  All rights granted under this License are granted for the term of\ncopyright on the Program, and are irrevocable provided the stated\nconditions are met.  This License explicitly affirms your unlimited\npermission to run the unmodified Program.  The output from running a\ncovered work is covered by this License only if the output, given its\ncontent, constitutes a covered work.  This License acknowledges your\nrights of fair use or other equivalent, as provided by copyright law.\n\n  You may make, run and propagate covered works that you do not\nconvey, without conditions so long as your license otherwise remains\nin force.  You may convey covered works to others for the sole purpose\nof having them make modifications exclusively for you, or provide you\nwith facilities for running those works, provided that you comply with\nthe terms of this License in conveying all material for which you do\nnot control copyright.  Those thus making or running the covered works\nfor you must do so exclusively on your behalf, under your direction\nand control, on terms that prohibit them from making any copies of\nyour copyrighted material outside their relationship with you.\n\n  Conveying under any other circumstances is permitted solely under\nthe conditions stated below.  Sublicensing is not allowed; section 10\nmakes it unnecessary.\n\n  3. Protecting Users' Legal Rights From Anti-Circumvention Law.\n\n  No covered work shall be deemed part of an effective technological\nmeasure under any applicable law fulfilling obligations under article\n11 of the WIPO copyright treaty adopted on 20 December 1996, or\nsimilar laws prohibiting or restricting circumvention of such\nmeasures.\n\n  When you convey a covered work, you waive any legal power to forbid\ncircumvention of technological measures to the extent such circumvention\nis effected by exercising rights under this License with respect to\nthe covered work, and you disclaim any intention to limit operation or\nmodification of the work as a means of enforcing, against the work's\nusers, your or third parties' legal rights to forbid circumvention of\ntechnological measures.\n\n  4. Conveying Verbatim Copies.\n\n  You may convey verbatim copies of the Program's source code as you\nreceive it, in any medium, provided that you conspicuously and\nappropriately publish on each copy an appropriate copyright notice;\nkeep intact all notices stating that this License and any\nnon-permissive terms added in accord with section 7 apply to the code;\nkeep intact all notices of the absence of any warranty; and give all\nrecipients a copy of this License along with the Program.\n\n  You may charge any price or no price for each copy that you convey,\nand you may offer support or warranty protection for a fee.\n\n  5. Conveying Modified Source Versions.\n\n  You may convey a work based on the Program, or the modifications to\nproduce it from the Program, in the form of source code under the\nterms of section 4, provided that you also meet all of these conditions:\n\n    a) The work must carry prominent notices stating that you modified\n    it, and giving a relevant date.\n\n    b) The work must carry prominent notices stating that it is\n    released under this License and any conditions added under section\n    7.  This requirement modifies the requirement in section 4 to\n    \"keep intact all notices\".\n\n    c) You must license the entire work, as a whole, under this\n    License to anyone who comes into possession of a copy.  This\n    License will therefore apply, along with any applicable section 7\n    additional terms, to the whole of the work, and all its parts,\n    regardless of how they are packaged.  This License gives no\n    permission to license the work in any other way, but it does not\n    invalidate such permission if you have separately received it.\n\n    d) If the work has interactive user interfaces, each must display\n    Appropriate Legal Notices; however, if the Program has interactive\n    interfaces that do not display Appropriate Legal Notices, your\n    work need not make them do so.\n\n  A compilation of a covered work with other separate and independent\nworks, which are not by their nature extensions of the covered work,\nand which are not combined with it such as to form a larger program,\nin or on a volume of a storage or distribution medium, is called an\n\"aggregate\" if the compilation and its resulting copyright are not\nused to limit the access or legal rights of the compilation's users\nbeyond what the individual works permit.  Inclusion of a covered work\nin an aggregate does not cause this License to apply to the other\nparts of the aggregate.\n\n  6. Conveying Non-Source Forms.\n\n  You may convey a covered work in object code form under the terms\nof sections 4 and 5, provided that you also convey the\nmachine-readable Corresponding Source under the terms of this License,\nin one of these ways:\n\n    a) Convey the object code in, or embodied in, a physical product\n    (including a physical distribution medium), accompanied by the\n    Corresponding Source fixed on a durable physical medium\n    customarily used for software interchange.\n\n    b) Convey the object code in, or embodied in, a physical product\n    (including a physical distribution medium), accompanied by a\n    written offer, valid for at least three years and valid for as\n    long as you offer spare parts or customer support for that product\n    model, to give anyone who possesses the object code either (1) a\n    copy of the Corresponding Source for all the software in the\n    product that is covered by this License, on a durable physical\n    medium customarily used for software interchange, for a price no\n    more than your reasonable cost of physically performing this\n    conveying of source, or (2) access to copy the\n    Corresponding Source from a network server at no charge.\n\n    c) Convey individual copies of the object code with a copy of the\n    written offer to provide the Corresponding Source.  This\n    alternative is allowed only occasionally and noncommercially, and\n    only if you received the object code with such an offer, in accord\n    with subsection 6b.\n\n    d) Convey the object code by offering access from a designated\n    place (gratis or for a charge), and offer equivalent access to the\n    Corresponding Source in the same way through the same place at no\n    further charge.  You need not require recipients to copy the\n    Corresponding Source along with the object code.  If the place to\n    copy the object code is a network server, the Corresponding Source\n    may be on a different server (operated by you or a third party)\n    that supports equivalent copying facilities, provided you maintain\n    clear directions next to the object code saying where to find the\n    Corresponding Source.  Regardless of what server hosts the\n    Corresponding Source, you remain obligated to ensure that it is\n    available for as long as needed to satisfy these requirements.\n\n    e) Convey the object code using peer-to-peer transmission, provided\n    you inform other peers where the object code and Corresponding\n    Source of the work are being offered to the general public at no\n    charge under subsection 6d.\n\n  A separable portion of the object code, whose source code is excluded\nfrom the Corresponding Source as a System Library, need not be\nincluded in conveying the object code work.\n\n  A \"User Product\" is either (1) a \"consumer product\", which means any\ntangible personal property which is normally used for personal, family,\nor household purposes, or (2) anything designed or sold for incorporation\ninto a dwelling.  In determining whether a product is a consumer product,\ndoubtful cases shall be resolved in favor of coverage.  For a particular\nproduct received by a particular user, \"normally used\" refers to a\ntypical or common use of that class of product, regardless of the status\nof the particular user or of the way in which the particular user\nactually uses, or expects or is expected to use, the product.  A product\nis a consumer product regardless of whether the product has substantial\ncommercial, industrial or non-consumer uses, unless such uses represent\nthe only significant mode of use of the product.\n\n  \"Installation Information\" for a User Product means any methods,\nprocedures, authorization keys, or other information required to install\nand execute modified versions of a covered work in that User Product from\na modified version of its Corresponding Source.  The information must\nsuffice to ensure that the continued functioning of the modified object\ncode is in no case prevented or interfered with solely because\nmodification has been made.\n\n  If you convey an object code work under this section in, or with, or\nspecifically for use in, a User Product, and the conveying occurs as\npart of a transaction in which the right of possession and use of the\nUser Product is transferred to the recipient in perpetuity or for a\nfixed term (regardless of how the transaction is characterized), the\nCorresponding Source conveyed under this section must be accompanied\nby the Installation Information.  But this requirement does not apply\nif neither you nor any third party retains the ability to install\nmodified object code on the User Product (for example, the work has\nbeen installed in ROM).\n\n  The requirement to provide Installation Information does not include a\nrequirement to continue to provide support service, warranty, or updates\nfor a work that has been modified or installed by the recipient, or for\nthe User Product in which it has been modified or installed.  Access to a\nnetwork may be denied when the modification itself materially and\nadversely affects the operation of the network or violates the rules and\nprotocols for communication across the network.\n\n  Corresponding Source conveyed, and Installation Information provided,\nin accord with this section must be in a format that is publicly\ndocumented (and with an implementation available to the public in\nsource code form), and must require no special password or key for\nunpacking, reading or copying.\n\n  7. Additional Terms.\n\n  \"Additional permissions\" are terms that supplement the terms of this\nLicense by making exceptions from one or more of its conditions.\nAdditional permissions that are applicable to the entire Program shall\nbe treated as though they were included in this License, to the extent\nthat they are valid under applicable law.  If additional permissions\napply only to part of the Program, that part may be used separately\nunder those permissions, but the entire Program remains governed by\nthis License without regard to the additional permissions.\n\n  When you convey a copy of a covered work, you may at your option\nremove any additional permissions from that copy, or from any part of\nit.  (Additional permissions may be written to require their own\nremoval in certain cases when you modify the work.)  You may place\nadditional permissions on material, added by you to a covered work,\nfor which you have or can give appropriate copyright permission.\n\n  Notwithstanding any other provision of this License, for material you\nadd to a covered work, you may (if authorized by the copyright holders of\nthat material) supplement the terms of this License with terms:\n\n    a) Disclaiming warranty or limiting liability differently from the\n    terms of sections 15 and 16 of this License; or\n\n    b) Requiring preservation of specified reasonable legal notices or\n    author attributions in that material or in the Appropriate Legal\n    Notices displayed by works containing it; or\n\n    c) Prohibiting misrepresentation of the origin of that material, or\n    requiring that modified versions of such material be marked in\n    reasonable ways as different from the original version; or\n\n    d) Limiting the use for publicity purposes of names of licensors or\n    authors of the material; or\n\n    e) Declining to grant rights under trademark law for use of some\n    trade names, trademarks, or service marks; or\n\n    f) Requiring indemnification of licensors and authors of that\n    material by anyone who conveys the material (or modified versions of\n    it) with contractual assumptions of liability to the recipient, for\n    any liability that these contractual assumptions directly impose on\n    those licensors and authors.\n\n  All other non-permissive additional terms are considered \"further\nrestrictions\" within the meaning of section 10.  If the Program as you\nreceived it, or any part of it, contains a notice stating that it is\ngoverned by this License along with a term that is a further\nrestriction, you may remove that term.  If a license document contains\na further restriction but permits relicensing or conveying under this\nLicense, you may add to a covered work material governed by the terms\nof that license document, provided that the further restriction does\nnot survive such relicensing or conveying.\n\n  If you add terms to a covered work in accord with this section, you\nmust place, in the relevant source files, a statement of the\nadditional terms that apply to those files, or a notice indicating\nwhere to find the applicable terms.\n\n  Additional terms, permissive or non-permissive, may be stated in the\nform of a separately written license, or stated as exceptions;\nthe above requirements apply either way.\n\n  8. Termination.\n\n  You may not propagate or modify a covered work except as expressly\nprovided under this License.  Any attempt otherwise to propagate or\nmodify it is void, and will automatically terminate your rights under\nthis License (including any patent licenses granted under the third\nparagraph of section 11).\n\n  However, if you cease all violation of this License, then your\nlicense from a particular copyright holder is reinstated (a)\nprovisionally, unless and until the copyright holder explicitly and\nfinally terminates your license, and (b) permanently, if the copyright\nholder fails to notify you of the violation by some reasonable means\nprior to 60 days after the cessation.\n\n  Moreover, your license from a particular copyright holder is\nreinstated permanently if the copyright holder notifies you of the\nviolation by some reasonable means, this is the first time you have\nreceived notice of violation of this License (for any work) from that\ncopyright holder, and you cure the violation prior to 30 days after\nyour receipt of the notice.\n\n  Termination of your rights under this section does not terminate the\nlicenses of parties who have received copies or rights from you under\nthis License.  If your rights have been terminated and not permanently\nreinstated, you do not qualify to receive new licenses for the same\nmaterial under section 10.\n\n  9. Acceptance Not Required for Having Copies.\n\n  You are not required to accept this License in order to receive or\nrun a copy of the Program.  Ancillary propagation of a covered work\noccurring solely as a consequence of using peer-to-peer transmission\nto receive a copy likewise does not require acceptance.  However,\nnothing other than this License grants you permission to propagate or\nmodify any covered work.  These actions infringe copyright if you do\nnot accept this License.  Therefore, by modifying or propagating a\ncovered work, you indicate your acceptance of this License to do so.\n\n  10. Automatic Licensing of Downstream Recipients.\n\n  Each time you convey a covered work, the recipient automatically\nreceives a license from the original licensors, to run, modify and\npropagate that work, subject to this License.  You are not responsible\nfor enforcing compliance by third parties with this License.\n\n  An \"entity transaction\" is a transaction transferring control of an\norganization, or substantially all assets of one, or subdividing an\norganization, or merging organizations.  If propagation of a covered\nwork results from an entity transaction, each party to that\ntransaction who receives a copy of the work also receives whatever\nlicenses to the work the party's predecessor in interest had or could\ngive under the previous paragraph, plus a right to possession of the\nCorresponding Source of the work from the predecessor in interest, if\nthe predecessor has it or can get it with reasonable efforts.\n\n  You may not impose any further restrictions on the exercise of the\nrights granted or affirmed under this License.  For example, you may\nnot impose a license fee, royalty, or other charge for exercise of\nrights granted under this License, and you may not initiate litigation\n(including a cross-claim or counterclaim in a lawsuit) alleging that\nany patent claim is infringed by making, using, selling, offering for\nsale, or importing the Program or any portion of it.\n\n  11. Patents.\n\n  A \"contributor\" is a copyright holder who authorizes use under this\nLicense of the Program or a work on which the Program is based.  The\nwork thus licensed is called the contributor's \"contributor version\".\n\n  A contributor's \"essential patent claims\" are all patent claims\nowned or controlled by the contributor, whether already acquired or\nhereafter acquired, that would be infringed by some manner, permitted\nby this License, of making, using, or selling its contributor version,\nbut do not include claims that would be infringed only as a\nconsequence of further modification of the contributor version.  For\npurposes of this definition, \"control\" includes the right to grant\npatent sublicenses in a manner consistent with the requirements of\nthis License.\n\n  Each contributor grants you a non-exclusive, worldwide, royalty-free\npatent license under the contributor's essential patent claims, to\nmake, use, sell, offer for sale, import and otherwise run, modify and\npropagate the contents of its contributor version.\n\n  In the following three paragraphs, a \"patent license\" is any express\nagreement or commitment, however denominated, not to enforce a patent\n(such as an express permission to practice a patent or covenant not to\nsue for patent infringement).  To \"grant\" such a patent license to a\nparty means to make such an agreement or commitment not to enforce a\npatent against the party.\n\n  If you convey a covered work, knowingly relying on a patent license,\nand the Corresponding Source of the work is not available for anyone\nto copy, free of charge and under the terms of this License, through a\npublicly available network server or other readily accessible means,\nthen you must either (1) cause the Corresponding Source to be so\navailable, or (2) arrange to deprive yourself of the benefit of the\npatent license for this particular work, or (3) arrange, in a manner\nconsistent with the requirements of this License, to extend the patent\nlicense to downstream recipients.  \"Knowingly relying\" means you have\nactual knowledge that, but for the patent license, your conveying the\ncovered work in a country, or your recipient's use of the covered work\nin a country, would infringe one or more identifiable patents in that\ncountry that you have reason to believe are valid.\n\n  If, pursuant to or in connection with a single transaction or\narrangement, you convey, or propagate by procuring conveyance of, a\ncovered work, and grant a patent license to some of the parties\nreceiving the covered work authorizing them to use, propagate, modify\nor convey a specific copy of the covered work, then the patent license\nyou grant is automatically extended to all recipients of the covered\nwork and works based on it.\n\n  A patent license is \"discriminatory\" if it does not include within\nthe scope of its coverage, prohibits the exercise of, or is\nconditioned on the non-exercise of one or more of the rights that are\nspecifically granted under this License.  You may not convey a covered\nwork if you are a party to an arrangement with a third party that is\nin the business of distributing software, under which you make payment\nto the third party based on the extent of your activity of conveying\nthe work, and under which the third party grants, to any of the\nparties who would receive the covered work from you, a discriminatory\npatent license (a) in connection with copies of the covered work\nconveyed by you (or copies made from those copies), or (b) primarily\nfor and in connection with specific products or compilations that\ncontain the covered work, unless you entered into that arrangement,\nor that patent license was granted, prior to 28 March 2007.\n\n  Nothing in this License shall be construed as excluding or limiting\nany implied license or other defenses to infringement that may\notherwise be available to you under applicable patent law.\n\n  12. No Surrender of Others' Freedom.\n\n  If conditions are imposed on you (whether by court order, agreement or\notherwise) that contradict the conditions of this License, they do not\nexcuse you from the conditions of this License.  If you cannot convey a\ncovered work so as to satisfy simultaneously your obligations under this\nLicense and any other pertinent obligations, then as a consequence you may\nnot convey it at all.  For example, if you agree to terms that obligate you\nto collect a royalty for further conveying from those to whom you convey\nthe Program, the only way you could satisfy both those terms and this\nLicense would be to refrain entirely from conveying the Program.\n\n  13. Remote Network Interaction; Use with the GNU General Public License.\n\n  Notwithstanding any other provision of this License, if you modify the\nProgram, your modified version must prominently offer all users\ninteracting with it remotely through a computer network (if your version\nsupports such interaction) an opportunity to receive the Corresponding\nSource of your version by providing access to the Corresponding Source\nfrom a network server at no charge, through some standard or customary\nmeans of facilitating copying of software.  This Corresponding Source\nshall include the Corresponding Source for any work covered by version 3\nof the GNU General Public License that is incorporated pursuant to the\nfollowing paragraph.\n\n  Notwithstanding any other provision of this License, you have\npermission to link or combine any covered work with a work licensed\nunder version 3 of the GNU General Public License into a single\ncombined work, and to convey the resulting work.  The terms of this\nLicense will continue to apply to the part which is the covered work,\nbut the work with which it is combined will remain governed by version\n3 of the GNU General Public License.\n\n  14. Revised Versions of this License.\n\n  The Free Software Foundation may publish revised and/or new versions of\nthe GNU Affero General Public License from time to time.  Such new versions\nwill be similar in spirit to the present version, but may differ in detail to\naddress new problems or concerns.\n\n  Each version is given a distinguishing version number.  If the\nProgram specifies that a certain numbered version of the GNU Affero General\nPublic License \"or any later version\" applies to it, you have the\noption of following the terms and conditions either of that numbered\nversion or of any later version published by the Free Software\nFoundation.  If the Program does not specify a version number of the\nGNU Affero General Public License, you may choose any version ever published\nby the Free Software Foundation.\n\n  If the Program specifies that a proxy can decide which future\nversions of the GNU Affero General Public License can be used, that proxy's\npublic statement of acceptance of a version permanently authorizes you\nto choose that version for the Program.\n\n  Later license versions may give you additional or different\npermissions.  However, no additional obligations are imposed on any\nauthor or copyright holder as a result of your choosing to follow a\nlater version.\n\n  15. Disclaimer of Warranty.\n\n  THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY\nAPPLICABLE LAW.  EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT\nHOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM \"AS IS\" WITHOUT WARRANTY\nOF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,\nTHE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\nPURPOSE.  THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM\nIS WITH YOU.  SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF\nALL NECESSARY SERVICING, REPAIR OR CORRECTION.\n\n  16. Limitation of Liability.\n\n  IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING\nWILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS\nTHE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY\nGENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE\nUSE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF\nDATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD\nPARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),\nEVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF\nSUCH DAMAGES.\n\n  17. Interpretation of Sections 15 and 16.\n\n  If the disclaimer of warranty and limitation of liability provided\nabove cannot be given local legal effect according to their terms,\nreviewing courts shall apply local law that most closely approximates\nan absolute waiver of all civil liability in connection with the\nProgram, unless a warranty or assumption of liability accompanies a\ncopy of the Program in return for a fee.\n\n                     END OF TERMS AND CONDITIONS\n\n            How to Apply These Terms to Your New Programs\n\n  If you develop a new program, and you want it to be of the greatest\npossible use to the public, the best way to achieve this is to make it\nfree software which everyone can redistribute and change under these terms.\n\n  To do so, attach the following notices to the program.  It is safest\nto attach them to the start of each source file to most effectively\nstate the exclusion of warranty; and each file should have at least\nthe \"copyright\" line and a pointer to where the full notice is found.\n\n    <one line to give the program's name and a brief idea of what it does.>\n    Copyright (C) <year>  <name of author>\n\n    This program is free software: you can redistribute it and/or modify\n    it under the terms of the GNU Affero General Public License as published by\n    the Free Software Foundation, either version 3 of the License, or\n    (at your option) any later version.\n\n    This program is distributed in the hope that it will be useful,\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n    GNU Affero General Public License for more details.\n\n    You should have received a copy of the GNU Affero General Public License\n    along with this program.  If not, see <http://www.gnu.org/licenses/>.\n\nAlso add information on how to contact you by electronic and paper mail.\n\n  If your software can interact with users remotely through a computer\nnetwork, you should also make sure that it provides a way for users to\nget its source.  For example, if your program is a web application, its\ninterface could display a \"Source\" link that leads users to an archive\nof the code.  There are many ways you could offer source, and different\nsolutions will be better for different programs; see section 13 for the\nspecific requirements.\n\n  You should also get your employer (if you work as a programmer) or school,\nif any, to sign a \"copyright disclaimer\" for the program, if necessary.\nFor more information on this, and how to apply and follow the GNU AGPL, see\n<http://www.gnu.org/licenses/>.\n"
  },
  {
    "path": "LICENSES/BSD-3-Clause.txt",
    "content": "Modified BSD license (no advertisement clause):\n\nCopyright (c) 2002-2017, Jouni Malinen <j@w1.fi> and contributors\nAll Rights Reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are\nmet:\n\n1. Redistributions of source code must retain the above copyright\n   notice, this list of conditions and the following disclaimer.\n\n2. Redistributions in binary form must reproduce the above copyright\n   notice, this list of conditions and the following disclaimer in the\n   documentation and/or other materials provided with the distribution.\n\n3. Neither the name(s) of the above-listed copyright holder(s) nor the\n   names of its contributors may be used to endorse or promote products\n   derived from this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n\"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\nLIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\nA PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\nOWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\nSPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\nLIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\nDATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\nTHEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\nOF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n"
  },
  {
    "path": "LICENSES/GPL-2.0-or-later.txt",
    "content": "\nGNU GENERAL PUBLIC LICENSE\nVersion 2, June 1991\n\nCopyright (C) 1989, 1991 Free Software Foundation, Inc.\n51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA\n\nEveryone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed.\n\nPreamble\n\nThe licenses for most software are designed to take away your freedom to share and change it. By contrast, the GNU General Public License is intended to guarantee your freedom to share and change free software--to make sure the software is free for all its users. This General Public License applies to most of the Free Software Foundation's software and to any other program whose authors commit to using it. (Some other Free Software Foundation software is covered by the GNU Lesser General Public License instead.) You can apply it to your programs, too.\n\nWhen we speak of free software, we are referring to freedom, not price. Our General Public Licenses are designed to make sure that you have the freedom to distribute copies of free software (and charge for this service if you wish), that you receive source code or can get it if you want it, that you can change the software or use pieces of it in new free programs; and that you know you can do these things.\n\nTo protect your rights, we need to make restrictions that forbid anyone to deny you these rights or to ask you to surrender the rights. These restrictions translate to certain responsibilities for you if you distribute copies of the software, or if you modify it.\n\nFor example, if you distribute copies of such a program, whether gratis or for a fee, you must give the recipients all the rights that you have. You must make sure that they, too, receive or can get the source code. And you must show them these terms so they know their rights.\n\nWe protect your rights with two steps: (1) copyright the software, and (2) offer you this license which gives you legal permission to copy, distribute and/or modify the software.\n\nAlso, for each author's protection and ours, we want to make certain that everyone understands that there is no warranty for this free software. If the software is modified by someone else and passed on, we want its recipients to know that what they have is not the original, so that any problems introduced by others will not reflect on the original authors' reputations.\n\nFinally, any free program is threatened constantly by software patents. We wish to avoid the danger that redistributors of a free program will individually obtain patent licenses, in effect making the program proprietary. To prevent this, we have made it clear that any patent must be licensed for everyone's free use or not licensed at all.\n\nThe precise terms and conditions for copying, distribution and modification follow.\n\nTERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION\n\n    0. This License applies to any program or other work which contains a notice placed by the copyright holder saying it may be distributed under the terms of this General Public License. The \"Program\", below, refers to any such program or work, and a \"work based on the Program\" means either the Program or any derivative work under copyright law: that is to say, a work containing the Program or a portion of it, either verbatim or with modifications and/or translated into another language. (Hereinafter, translation is included without limitation in the term \"modification\".) Each licensee is addressed as \"you\".\n\n    Activities other than copying, distribution and modification are not covered by this License; they are outside its scope. The act of running the Program is not restricted, and the output from the Program is covered only if its contents constitute a work based on the Program (independent of having been made by running the Program). Whether that is true depends on what the Program does.\n    1. You may copy and distribute verbatim copies of the Program's source code as you receive it, in any medium, provided that you conspicuously and appropriately publish on each copy an appropriate copyright notice and disclaimer of warranty; keep intact all the notices that refer to this License and to the absence of any warranty; and give any other recipients of the Program a copy of this License along with the Program.\n\n    You may charge a fee for the physical act of transferring a copy, and you may at your option offer warranty protection in exchange for a fee.\n    2. You may modify your copy or copies of the Program or any portion of it, thus forming a work based on the Program, and copy and distribute such modifications or work under the terms of Section 1 above, provided that you also meet all of these conditions:\n        a) You must cause the modified files to carry prominent notices stating that you changed the files and the date of any change.\n        b) You must cause any work that you distribute or publish, that in whole or in part contains or is derived from the Program or any part thereof, to be licensed as a whole at no charge to all third parties under the terms of this License.\n        c) If the modified program normally reads commands interactively when run, you must cause it, when started running for such interactive use in the most ordinary way, to print or display an announcement including an appropriate copyright notice and a notice that there is no warranty (or else, saying that you provide a warranty) and that users may redistribute the program under these conditions, and telling the user how to view a copy of this License. (Exception: if the Program itself is interactive but does not normally print such an announcement, your work based on the Program is not required to print an announcement.)\n\n    These requirements apply to the modified work as a whole. If identifiable sections of that work are not derived from the Program, and can be reasonably considered independent and separate works in themselves, then this License, and its terms, do not apply to those sections when you distribute them as separate works. But when you distribute the same sections as part of a whole which is a work based on the Program, the distribution of the whole must be on the terms of this License, whose permissions for other licensees extend to the entire whole, and thus to each and every part regardless of who wrote it.\n\n    Thus, it is not the intent of this section to claim rights or contest your rights to work written entirely by you; rather, the intent is to exercise the right to control the distribution of derivative or collective works based on the Program.\n\n    In addition, mere aggregation of another work not based on the Program with the Program (or with a work based on the Program) on a volume of a storage or distribution medium does not bring the other work under the scope of this License.\n    3. You may copy and distribute the Program (or a work based on it, under Section 2) in object code or executable form under the terms of Sections 1 and 2 above provided that you also do one of the following:\n        a) Accompany it with the complete corresponding machine-readable source code, which must be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or,\n        b) Accompany it with a written offer, valid for at least three years, to give any third party, for a charge no more than your cost of physically performing source distribution, a complete machine-readable copy of the corresponding source code, to be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or,\n        c) Accompany it with the information you received as to the offer to distribute corresponding source code. (This alternative is allowed only for noncommercial distribution and only if you received the program in object code or executable form with such an offer, in accord with Subsection b above.)\n\n    The source code for a work means the preferred form of the work for making modifications to it. For an executable work, complete source code means all the source code for all modules it contains, plus any associated interface definition files, plus the scripts used to control compilation and installation of the executable. However, as a special exception, the source code distributed need not include anything that is normally distributed (in either source or binary form) with the major components (compiler, kernel, and so on) of the operating system on which the executable runs, unless that component itself accompanies the executable.\n\n    If distribution of executable or object code is made by offering access to copy from a designated place, then offering equivalent access to copy the source code from the same place counts as distribution of the source code, even though third parties are not compelled to copy the source along with the object code.\n    4. You may not copy, modify, sublicense, or distribute the Program except as expressly provided under this License. Any attempt otherwise to copy, modify, sublicense or distribute the Program is void, and will automatically terminate your rights under this License. However, parties who have received copies, or rights, from you under this License will not have their licenses terminated so long as such parties remain in full compliance.\n    5. You are not required to accept this License, since you have not signed it. However, nothing else grants you permission to modify or distribute the Program or its derivative works. These actions are prohibited by law if you do not accept this License. Therefore, by modifying or distributing the Program (or any work based on the Program), you indicate your acceptance of this License to do so, and all its terms and conditions for copying, distributing or modifying the Program or works based on it.\n    6. Each time you redistribute the Program (or any work based on the Program), the recipient automatically receives a license from the original licensor to copy, distribute or modify the Program subject to these terms and conditions. You may not impose any further restrictions on the recipients' exercise of the rights granted herein. You are not responsible for enforcing compliance by third parties to this License.\n    7. If, as a consequence of a court judgment or allegation of patent infringement or for any other reason (not limited to patent issues), conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this License, they do not excuse you from the conditions of this License. If you cannot distribute so as to satisfy simultaneously your obligations under this License and any other pertinent obligations, then as a consequence you may not distribute the Program at all. For example, if a patent license would not permit royalty-free redistribution of the Program by all those who receive copies directly or indirectly through you, then the only way you could satisfy both it and this License would be to refrain entirely from distribution of the Program.\n\n    If any portion of this section is held invalid or unenforceable under any particular circumstance, the balance of the section is intended to apply and the section as a whole is intended to apply in other circumstances.\n\n    It is not the purpose of this section to induce you to infringe any patents or other property right claims or to contest validity of any such claims; this section has the sole purpose of protecting the integrity of the free software distribution system, which is implemented by public license practices. Many people have made generous contributions to the wide range of software distributed through that system in reliance on consistent application of that system; it is up to the author/donor to decide if he or she is willing to distribute software through any other system and a licensee cannot impose that choice.\n\n    This section is intended to make thoroughly clear what is believed to be a consequence of the rest of this License.\n    8. If the distribution and/or use of the Program is restricted in certain countries either by patents or by copyrighted interfaces, the original copyright holder who places the Program under this License may add an explicit geographical distribution limitation excluding those countries, so that distribution is permitted only in or among countries not thus excluded. In such case, this License incorporates the limitation as if written in the body of this License.\n    9. The Free Software Foundation may publish revised and/or new versions of the General Public License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns.\n\n    Each version is given a distinguishing version number. If the Program specifies a version number of this License which applies to it and \"any later version\", you have the option of following the terms and conditions either of that version or of any later version published by the Free Software Foundation. If the Program does not specify a version number of this License, you may choose any version ever published by the Free Software Foundation.\n    10. If you wish to incorporate parts of the Program into other free programs whose distribution conditions are different, write to the author to ask for permission. For software which is copyrighted by the Free Software Foundation, write to the Free Software Foundation; we sometimes make exceptions for this. Our decision will be guided by the two goals of preserving the free status of all derivatives of our free software and of promoting the sharing and reuse of software generally.\n\n    NO WARRANTY\n    11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM \"AS IS\" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION.\n    12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\n\nEND OF TERMS AND CONDITIONS\n\nHow to Apply These Terms to Your New Programs\n\nIf you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it free software which everyone can redistribute and change under these terms.\n\nTo do so, attach the following notices to the program. It is safest to attach them to the start of each source file to most effectively convey the exclusion of warranty; and each file should have at least the \"copyright\" line and a pointer to where the full notice is found.\n\n<one line to give the program's name and an idea of what it does.>\nCopyright (C) <yyyy> <name of author>\n\nThis program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.\n\nThis program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.\n\nYou should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.\n\nAlso add information on how to contact you by electronic and paper mail.\n\nIf the program is interactive, make it output a short notice like this when it starts in an interactive mode:\n\nGnomovision version 69, Copyright (C) year name of author Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. This is free software, and you are welcome to redistribute it under certain conditions; type `show c' for details.\n\nThe hypothetical commands `show w' and `show c' should show the appropriate parts of the General Public License. Of course, the commands you use may be called something other than `show w' and `show c'; they could even be mouse-clicks or menu items--whatever suits your program.\n\nYou should also get your employer (if you work as a programmer) or your school, if any, to sign a \"copyright disclaimer\" for the program, if necessary. Here is a sample; alter the names:\n\nYoyodyne, Inc., hereby disclaims all copyright interest in the program `Gnomovision' (which makes passes at compilers) written by James Hacker.\n\n<signature of Ty Coon>, 1 April 1989 Ty Coon, President of Vice\n\nThis General Public License does not permit incorporating your program into proprietary programs. If your program is a subroutine library, you may consider it more useful to permit linking proprietary applications with the library. If this is what you want to do, use the GNU Lesser General Public License instead of this License.\nStandard License Header\n\n<one line to give the program's name and an idea of what it does.>\nCopyright (C) <yyyy> <name of author>\n\nThis program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.\n\nThis program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.\n\nYou should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.\n\n"
  },
  {
    "path": "LICENSES/ISC.txt",
    "content": "Copyright <YEAR> <OWNER>\n\nPermission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n"
  },
  {
    "path": "README.md",
    "content": "<!--\nAuthor: Xianjun jiao, Michael Mehari, Wei Liu\nSPDX-FileCopyrightText: 2019 UGent\nSPDX-License-Identifier: AGPL-3.0-or-later\n-->\n\n# openwifi\n<img src=\"./openwifi-arch.jpg\" width=\"900\">\n\n**openwifi:** Linux mac80211 compatible full-stack IEEE802.11/Wi-Fi design based on SDR (Software Defined Radio).\n\n- We remain committed to open source, which is our foundation. To access advanced features and dedicated support, consider a **SUBSCRIPTION**. More info on https://openwifi.tech\n\n[[Download img and Quick start](#Download-img-and-Quick-start)] [[known issue](doc/known_issue/notter.md)] [[**Tips for Windows users**](https://github.com/open-sdr/openwifi/discussions/341)]\n\nThis repository includes Linux driver and software. **openwifi-hw** repository has the FPGA design. It is **YOUR RESPONSIBILITY** to follow your **LOCAL SPECTRUM REGULATION** or use **CABLE** to avoid potential interference over the air.\n\n[[Project document](doc/README.md)]\n[[Application notes](doc/app_notes/README.md)]\n[[Videos](doc/videos.md)]\n[[Publications and How to Cite](doc/publications.md)]\n[[maillist](https://lists.ugent.be/wws/subscribe/openwifi)]\n\nOpenwifi code has dual licenses. [AGPLv3](https://github.com/open-sdr/openwifi/blob/master/LICENSE) is the opensource license. For non-opensource and advanced feature license, please fill a contact form on https://openwifi.tech. Openwifi project also leverages some 3rd party modules. It is user's duty to check and follow licenses of those modules according to the purpose/usage. You can find [an example explanation from Analog Devices](https://github.com/analogdevicesinc/hdl/blob/master/LICENSE) for this compound license conditions. [[How to contribute]](https://github.com/open-sdr/openwifi/blob/master/CONTRIBUTING.md). \n\n**Features:**\n\n- 802.11a/g/n [[IEEE 802.11n (Wi-Fi 4)](doc/app_notes/ieee80211n.md)]\n- 20MHz bandwidth; [70 MHz to 6 GHz frequency range](doc/README.md#let-openwifi-work-at-arbitrary-frequency)\n- Mode tested: [Ad-hoc](doc/app_notes/ad-hoc-two-sdr.md); [Station; AP](doc/app_notes/ap-client-two-sdr.md), Monitor\n- [DCF (CSMA/CA) low MAC layer in FPGA (10us SIFS is achieved)](doc/app_notes/frequent_trick.md)\n- [802.11 packet injection and fuzzing](doc/app_notes/inject_80211.md)\n- [CSI](doc/app_notes/csi.md): Channel State Information, freq offset, equalizer to computer\n- [CSI fuzzer](doc/app_notes/csi_fuzzer.md): Create artificial channel response in WiFi transmitter\n- [CSI radar](doc/app_notes/radar-self-csi.md): Moving detection. Joint radar and communication\n- [[IQ capture](doc/app_notes/iq.md)]: real-time AGC, RSSI, IQ sample to computer. [[Dual antenna version](doc/app_notes/iq_2ant.md)]\n- [Configurable channel access priority parameters](doc/app_notes/frequent_trick.md):\n  - CCA threshold, receiver sensitivity, etc\n  - duration of RTS/CTS, CTS-to-self\n  - SIFS/DIFS/xIFS/slot-time/CW/etc\n- [Time slicing based on MAC address (time gated/scheduled FPGA queues)](https://doc.ilabt.imec.be/ilabt/wilab/tutorials/openwifi.html#sdr-tx-time-slicing)\n- Easy to change bandwidth and [frequency](doc/README.md#let-openwifi-work-at-arbitrary-frequency): \n  - 2MHz for 802.11ah in sub-GHz\n  - 10MHz for 802.11p/vehicle in 5.9GHz\n- **802.11ax** and more advanced features, check: https://openwifi.tech\n\n**Performance (best case: aggregation/AMPDU on):**\n- iperf: TCP 40~50Mbps; UDP 50Mbps\n- EVM -38dB; MCS0 sensitivity -92dBm; MCS7 -73dBm. (FMCOMMS2 2.4GHz; cable and OTA test)\n\n**Supported SDR platforms:**\n\nboard_name|Description|Vivado license\n----------|-----------|--------------\nzc706_fmcs2|[Xilinx ZC706 board](https://www.xilinx.com/products/boards-and-kits/ek-z7-zc706-g.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Need\nzed_fmcs2|[Xilinx zed board](https://www.xilinx.com/products/boards-and-kits/1-8dyf-11.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|**NO** need\nadrv9364z7020|[ADRV9364-Z7020 + ADRV1CRR-BOB](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/adrv9364-z7020.html)|**NO** need\nadrv9361z7035|[ADRV9361-Z7035 + ADRV1CRR-BOB/FMC](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/ADRV9361-Z7035.html)|Need\nzc702_fmcs2|[Xilinx ZC702 board](https://www.xilinx.com/products/boards-and-kits/ek-z7-zc702-g.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|**NO** need\nantsdr|[MicroPhase](https://github.com/MicroPhase/) enhanced ADALM-PLUTO [Notes](kernel_boot/boards/antsdr/notes.md)|**NO** need\ne310v2|[MicroPhase](https://github.com/MicroPhase/) new antsdr [Notes](kernel_boot/boards/e310v2/README.md)|**NO** need\nantsdr_e200|[MicroPhase](https://github.com/MicroPhase/) enhanced ADALM-PLUTO (smaller/cheaper) [Notes](kernel_boot/boards/antsdr_e200/README.md)|**NO** need\nsdrpi|[HexSDR](https://github.com/HexSDR/) SDR in Raspberry Pi size [Notes](kernel_boot/boards/sdrpi/notes.md)|**NO** need\nzcu102_fmcs2|[Xilinx ZCU102 board](https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Need\nneptunesdr|Low cost Zynq 7020 + AD9361 board (Unofficial!)|**NO** need\nLibreSDR|[Low cost Zynq 7020 + AD9361 board (Unofficial!)](https://github.com/pavelyazev/openwifi-libresdr)|**NO** need\n\n- Check [Porting guide](#Porting-guide) for your new board if it isn't in the list.\n- board_name is used to identify FPGA design in openwifi-hw/boards/ and FPGA image in openwifi-hw-img/boards\n- Don't have any boards? Or you like JTAG boot instead of SD card? Check our test bed [w-iLab.t](https://doc.ilabt.imec.be/ilabt/wilab/tutorials/openwifi.html) tutorial.\n\n[[Download img and Quick start](#Download-img-and-Quick-start)]\n[[Basic operations](#Basic-operations)]\n[[Update FPGA](#Update-FPGA)]\n[[Update Driver](#Update-Driver)]\n[[Update sdrctl](#Update-sdrctl)]\n[[Update Misc Helpers](#Update-Misc-Helpers)]\n\n[[Build openwifi Linux img from scratch](#Build-openwifi-Linux-img-from-scratch)]\n[[Special note for 11b](#Special-note-for-11b)]\n[[Porting guide](#Porting-guide)]\n[[Project document](doc/README.md)]\n[[Application notes](doc/app_notes/README.md)]\n\n## Download img and Quick start\n- Download [openwifi img](https://users.ugent.be/~xjiao/openwifi-1.5.0-shahecheng.img.xz), unzip and burn it into a SD card (>=16GB). After this operation, the SD card should have two partitions: BOOT and rootfs. To flash the SD card, SD card tool software (such as Startup Disk Creator in Ubuntu) or dd command can be used:\n  ```\n  sudo dd bs=512 count=31116288 if=openwifi-xyz.img of=/dev/your_sdcard_dev\n  (To have correct count value, better to check the .img file actual situation by \"fdisk -l img_filename\")\n  ```\n- Config the **correct files in the BOOT partition** according to the **board you have** by operation on your computer: \n  - Copy files in **BOOT/openwifi/board_name** to the base directory of BOOT partition.\n  - Delete the **rootfs/root/kernel_modules** directory (if exist).\n  - Delete the **rootfs/etc/network/interfaces.new** directory (if exist).\n- Insert the SD card to the board. Configure the board in SD booting mode. Connect antennas. Power on. \n- Login to the board from your PC (PC Ethernet should have IP 192.168.10.1) with password **openwifi**.\n  ```\n  ssh root@192.168.10.122\n  ```\n- If not successful, check [known issue](doc/known_issue/notter.md)\n- Then, run openwifi AP and the on board webserver\n  ```\n  raspi-config --expand-rootfs (Only needed when your SD card > 16GB. Run and reboot)\n  ./openwifi/setup_once.sh (Reboot the board. Only need to run once for new board)\n  cd openwifi\n  ./wgd.sh\n  ./fosdem.sh\n  (Use \"./wgd.sh 1\" to enable experimental AMPDU aggregation on top of 11n)\n  (Use \"./fosdem-11ag.sh\" to force 11a/g mode)\n  ```\n  **NOTE** adrv9361z7035 has ultra low TX power in 5GHz. Move **CLOSER** when you use that board in 5GHz!!!\n- After you see the \"openwifi\" SSID on your device (Phone/Laptop/etc), connect it (If not get 192.168.13.* IP automatically, check [known issue](doc/known_issue/notter.md)). Browser to 192.168.13.1 on your device, you should see the webpage hosted by the webserver on board.\n  - Note 1: If your device doesn't support 5GHz (ch44), please change the **hostapd-openwifi.conf** on board and re-run fosdem.sh.\n  - Note 2: After ~2 hours, the Viterbi decoder will halt (Xilinx Evaluation License). Just reload FPGA ([method](doc/app_notes/drv_fpga_dynamic_loading.md)) or simply power cycle the board if it happens. (If output of \"./sdrctl dev sdr0 get reg rx 20\" is always the same, it means the decoder halts)\n- To give the Wi-Fi client internet access, configure routing/NAT **on the PC**:\n  ```\n  sudo sysctl -w net.ipv4.ip_forward=1\n  sudo iptables -t nat -A POSTROUTING -o NICY -j MASQUERADE\n  sudo ip route add 192.168.13.0/24 via 192.168.10.122 dev ethX\n  ```\n  **ethX** is the PC NIC name connecting the board ethernet. **NICY** is the PC NIC name connecting internet (WiFi or another ethernet).\n  \n  If you want, uncommenting \"net.ipv4.ip_forward=1\" in /etc/sysctl.conf to make IP forwarding persistent on PC.\n- To monitor **real-time CSI (Chip State Information)**, such as timestamp, frequency offset, channel state, equalizer, please refer to [[CSI notes](doc/app_notes/csi.md)].\n\n## Basic operations\nThe board actually is an Linux/Ubuntu computer which is running **hostapd** to offer Wi-Fi AP functionality over the Wi-Fi Network Interface (NIC). The NIC is implemented by openwifi-hw FPGA design. We use the term **\"On board\"** to indicate that the commands should be executed after ssh login to the board. **\"On PC\"** means the commands should run on PC.\n- Bring up the openwifi NIC sdr0:\n  ```\n  cd ~/openwifi && ./wgd.sh\n  (Use \"./wgd.sh 1\" to enable experimental AMPDU aggregation)\n  ```\n- Use openwifi as client to connect other AP (Change wpa-connect.conf on board firstly):\n  ```\n  route del default gw 192.168.10.1\n  wpa_supplicant -i sdr0 -c wpa-connect.conf &\n  dhclient sdr0\n  ```\n- Use openwifi in ad-hoc mode: Please check **sdr-ad-hoc-up.sh**, **sdr-ad-hoc-join.sh** and [this app note](./doc/app_notes/ad-hoc-two-sdr.md).\n- Use openwifi in monitor mode: Please check **monitor_ch.sh** and [this app note](./doc/app_notes/inject_80211.md).\n- The Linux native Wi-Fi tools/Apps (iwconfig/ifconfig/iwlist/iw/hostapd/wpa_supplicant/etc) can run over openwifi NIC in the same way as commercial Wi-Fi chip. \n- **sdrctl** is a dedicated tool to access openwifi driver/FPGA, please check [project document](./doc/README.md) for more information. \n\n## Update FPGA\n\nSince the pre-built SD card image might not have the latest bug-fixes/updates, it is recommended to always copy the latest files in the [user_space](./user_space) directory on to the board. Then update the FPGA&Driver according to the Quick start of [this app note](doc/app_notes/radar-self-csi.md#quick-start). Following instructions are doing the same thing with extra info for environment setup.\n\n(Check [Driver and FPGA dynamic reloading app note](./doc/app_notes/drv_fpga_dynamic_loading.md) for better understanding of updating FPGA and driver files without rebooting/power-cycle)\n\n- Install Vivado 2021.1. Make sure install Vitis as well. You should have this directory: your_Xilinx_install_directory/Vitis (NOT Vitis_HLS!)\n  - If the Vitis is not installed, you can add it by running \"Xilinx Design Tools --> Add Design Tools for Devices 2021.1\" from Xilinx program group/menu in your OS start menu.\n- Setup environment variables (use absolute path):\n  ```\n  export XILINX_DIR=your_Xilinx_install_directory\n  (Example: export XILINX_DIR=/opt/Xilinx. The Xilinx directory should include sth like: Downloads, Vitis, etc.)\n  export OPENWIFI_HW_IMG_DIR=your_openwifi-hw-img_directory\n  (The directory where you get the open-sdr/openwifi-hw-img repo via git clone)\n  export BOARD_NAME=your_board_name\n  ```\n- Pick the FPGA bitstream from openwifi-hw-img, generate system_top.bit.bin and transfer it on board via ssh channel:\n  ```\n  cd openwifi/user_space; ./boot_bin_gen.sh $XILINX_DIR $BOARD_NAME $OPENWIFI_HW_IMG_DIR/boards/$BOARD_NAME/sdk/system_top.xsa\n  scp ./system_top.bit.bin root@192.168.10.122:openwifi/\n  ```\n- Now the system_top.bit.bin is onboard in /root/openwifi/ directory. When wgd.sh runs onboard from that directory, it will discover the FPGA img file system_top.bit.bin and load it before loading driver .ko files.\n\n## Update Driver\n\nSince the pre-built SD card image might not have the latest bug-fixes/updates, it is recommended to always copy the latest files in the [user_space](./user_space) directory on to the board. Then update the FPGA&Driver according to the Quick start of [this app note](doc/app_notes/radar-self-csi.md#quick-start). Following instructions are doing the same thing with extra info for environment setup.\n\n(Check [Driver and FPGA dynamic reloading app note](./doc/app_notes/drv_fpga_dynamic_loading.md) for better understanding of updating FPGA and driver files without rebooting/power-cycle)\n\n- Prepare Analog Devices Linux kernel source code (only need to run once):\n  ```\n  sudo apt install flex bison libssl-dev device-tree-compiler u-boot-tools -y\n  cd openwifi/user_space; ./prepare_kernel.sh $XILINX_DIR ARCH_BIT\n  (For Zynq 7000, ARCH_BIT should be 32, for Zynq MPSoC, ARCH_BIT should be 64)\n  ```\n- Compile the latest openwifi driver\n  ```\n  cd openwifi/driver; ./make_all.sh $XILINX_DIR ARCH_BIT\n  (For Zynq 7000, ARCH_BIT should be 32, for Zynq MPSoC, ARCH_BIT should be 64)\n  (More arguments (max 5) beyond above two will be converted to \"#define argument\" in pre_def.h for conditional compiling)\n  ```\n- Copy the driver files to the board via ssh channel\n  ```\n  cd openwifi/driver; scp `find ./ -name \\*.ko` root@192.168.10.122:openwifi/\n  ```\n  Now you can use **wgd.sh** on board to load the new openwifi driver. **wgd.sh** also tries to reload FPGA img if system_top.bit.bin presents in the same directory. \n  Find more information in [Driver and FPGA dynamic reloading app note](./doc/app_notes/drv_fpga_dynamic_loading.md).\n  \n  **Note**: If you have symbol or version error while loadng the driver, it could be because the kernel in the SD card image is too old. In this case, you need put the linux kernel image generated by prepare_kernel.sh (check [[Update Driver](#Update-Driver)]) to the BOOT partition of SD card. The kernel image file name: adi-linux/arch/arm/boot/uImage (32bit); adi-linux-64/arch/arm64/boot/Image (64bit).\n\n## Update sdrctl\n- Copy the sdrctl source files to the board via ssh channel\n  ```\n  cd openwifi/user_space/sdrctl_src; scp `find ./ -name \\*` root@192.168.10.122:openwifi/sdrctl_src/\n  ```\n- Compile the sdrctl **on board**:\n  ```\n  cd ~/openwifi/sdrctl_src/ && make clean && make && cp sdrctl ../ && cd ..\n  ```\n## Update Misc Helpers\n\n- Check [Driver and FPGA dynamic reloading app note](./doc/app_notes/drv_fpga_dynamic_loading.md) for more convenient way of updating FPGA and driver files without rebooting/power-cycle.\n- Update new kernel, modules and devicetree to the board\n  - Prepare in the host PC (run scripts in the user_space directory)\n    - `prepare_kernel.sh`\n    - `boot_bin_gen.sh`\n    - `transfer_kernel_image_module_to_board.sh`\n  - Run on board (in the /root/ directory)\n    - `populate_kernel_image_module_reboot.sh`\n    \n      If kernel version is changed, you should run this script again after rebooting. Because the first time run it with old kernel will not setup correct liked directory name for the new kernel version.\n  - Suggest also update the Linux rootfs (https://wiki.analog.com/resources/tools-software/linux-software/kuiper-linux/update)\n    - `git clone https://github.com/analogdevicesinc/linux_image_ADI-scripts.git` on board\n    - `apt update`\n    - `adi_update_tools.sh`\n- Update new drivers .ko files to the board\n  - Prepare in the host PC\n    - `make_all.sh` (in the driver directory)\n    - `transfer_driver_userspace_to_board.sh`\n  - Run on board (in the /root/ directory)\n    - `populate_driver_userspace.sh`\n- FPGA and driver on board update scripts\n  - Setup [ftp server](https://ubuntu.com/server/docs/service-ftp) on PC, allow anonymous and change ftp root directory to the openwifi directory.\n  - On board:\n  ```\n  ./sdcard_boot_update.sh $BOARD_NAME\n  (Above command downloads uImage, BOOT.BIN and devicetree.dtb, then copy them into boot partition. Remember to power cycle)\n  ./wgd.sh remote\n  (Above command downloads driver files, and brings up sdr0)\n  ```\n- Access the board disk/rootfs like a disk: \n   - On PC: \"File manager --> Connect to Server...\", input: sftp://root@192.168.10.122/root\n   - Input password \"openwifi\"\n\n## Build openwifi Linux image from scratch\n- For the ADI Kuiper image, please check [kuiper.md](./doc/img_build_instruction/kuiper.md)\n\n## Special note for 11b\n\nOpenwifi only applies OFDM as its modulation scheme and as a result, it is not backward compatible with 802.11b clients or modes of operation. This is usually the case during beacon transmission, connection establishment, and robust communication.\n\nAs a solution to this problem, openwifi can be fully controlled only if communicating with APs/clients instantiated using hostapd/wpa_supplicant userspace programs respectively.\n\nFor hostapd program, 802.11b rates can be suppressed using configuration commands (i.e. supported_rates, basic_rates) and an example configuration file is provided (i.e. hostapd-openwifi.conf). One small caveat to this one comes from fullMAC Wi-Fi cards as they must implement the *NL80211_TXRATE_LEGACY* NetLink handler at the device driver level.\n\nOn the other hand, the wpa_supplicant program on the client side (commercial Wi-Fi dongle/board) cannot suppress 802.11b rates out of the box in 2.4GHz band, so there will be an issue when connecting openwifi (OFDM only). A patched wpa_supplicant should be used at the client side.\n```\nsudo apt-get install libssl1.0-dev\ncd openwifi/user_space; ./build_wpa_supplicant_wo11b.sh\n```\n## Porting guide\n\nThis section explains the porting work by showing the differences between openwifi and Analog Devices reference design. openwifi is based on 2021_r1 of [HDL Reference Designs](https://github.com/analogdevicesinc/hdl).\n- Open the fmcomms2 + zc706 reference design at hdl/projects/fmcomms2/zc706 (Please read Analog Devices help)\n- Open the openwifi design zc706_fmcs2 at openwifi-hw/boards/zc706_fmcs2 (Please read openwifi-hw repository)\n- \"Open Block Design\", you will see the differences between openwifi and the reference design. Both in \"diagram\" and in \"Address Editor\".\n- The address/interrupts of FPGA blocks hooked to the ARM bus should be put/aligned to the devicetree file openwifi/kernel_boot/boards/zc706_fmcs2/devicetree.dts. Linux will parse the devicetree.dtb when booting to know information of attached device (FPGA blocks in our case).\n- We use dtc command to get devicetree.dts converted from devicetree.dtb in [Analog Devices Linux image](https://wiki.analog.com/resources/tools-software/linux-software/zynq_images), then do modification according to what we have added/modified to the reference design.\n- Please learn the script in [[Build openwifi Linux img from scratch](#Build-openwifi-Linux-img-from-scratch)] to understand how we generate devicetree.dtb, BOOT.BIN, Linux kernel and put them together to build the full SD card image.\n\n## License\n\nThis project is available as open source under the terms of the AGPL 3.0 Or later. However, some elements are being licensed under GPL 2-0 or later and BSD 3 license . For accurate information, please check individual files.\n\n## Funding\n\nThis project received funding through [ORCA project](https://www.orca-project.eu/). ORCA project is funded by the EU's Horizon2020 programme under agreement number 732174.\n\nThis project received funding through [NGI Zero Core](https://nlnet.nl/core/), a fund established by [NLnet](https://nlnet.nl/) with financial support from the European Commission's [Next Generation Internet](https://ngi.eu/) program. Learn more at the NLnet project pages: [802.11n feature of openwifi](https://nlnet.nl/project/OpenWifi-80211n/), [openwifi: 802.11a/g/n maturity](https://nlnet.nl/project/OpenWifi-maturity/), [Extensive openwifi support for OpenWRT](https://nlnet.nl/project/OpenWifi-OpenWRT/)\n\n"
  },
  {
    "path": "doc/README.md",
    "content": "<!--\nAuthor: Xianjun jiao, Michael Mehari, Wei Liu\nSPDX-FileCopyrightText: 2019 UGent\nSPDX-License-Identifier: AGPL-3.0-or-later\n-->\n\n\n# Openwifi document\n<img src=\"./openwifi-detail.jpg\" width=\"1100\">\n\nAbove figure shows software and hardware/FPGA modules that compose the openwifi design. The module name is equal/similar to the source code file name. Driver module source codes are in openwifi/driver/. FPGA module source codes are in openwifi-hw repository. The user space tool sdrctl source code are in openwifi/user_space/sdrctl_src/. [Sysfs](https://man7.org/linux/man-pages/man5/sysfs.5.html) is another channel that is offered to do userspace-driver communication by mapping driver variables to virtual files. Check [this app note](app_notes/driver_stat.md#Sysfs-explanation) for further explanation.\n\n- [Driver and software overall principle](#Driver-and-software-overall-principle)\n- [sdrctl command](#sdrctl-command)\n- [Rx packet flow and filtering config](#Rx-packet-flow-and-filtering-config)\n- [Tx packet flow and config](#Tx-packet-flow-and-config)\n- [Understand the timestamp of WiFi packet](#Understand-the-timestamp-of-WiFi-packet)\n- [Regulation and channel config](#Regulation-and-channel-config)\n- [Analog and digital frequency design](#Analog-and-digital-frequency-design)\n- [Debug methods](#Debug-methods)\n- [Test mode driver](#Test-mode-driver)\n- [Application notes](app_notes/README.md)\n\n## Driver and software overall principle\n\n[Linux mac80211 subsystem](https://www.kernel.org/doc/html/v4.16/driver-api/80211/mac80211.html), as a part of [Linux wireless](https://wireless.wiki.kernel.org/en/developers/documentation/mac80211), defines a set of APIs ([ieee80211_ops](https://www.kernel.org/doc/html/v4.9/80211/mac80211.html#c.ieee80211_ops)) to rule the Wi-Fi chip driver behavior. SoftMAC Wi-Fi chip driver implements (subset of) those APIs. That is why Linux can support so many Wi-Fi chips of different chip vendors. Different mode (AP/Client/ad-hoc/mesh) might need different set of APIs\n\nopenwifi driver (sdr.c) implements following APIs of ieee80211_ops:\n-\t**tx**. It is called when upper layer has a packet to send\n-\t**start**. It is called when NIC up. (ifconfig sdr0 up)\n-\t**stop**. It is called when NIC down. (ifconfig sdr0 down)\n-\t**add_interface**. It is called when NIC is created\n-\t**remove_interface**. It is called when NIC is deleted\n-\t**config**. It is called when upper layer wants to change channel/frequency (like the scan operation)\n-\t**set_antenna**. Set/select the tx/rx antenna\n-\t**get_antenna**. Read the current tx/rx antenna idx/combination\n-\t**bss_info_changed**. It is called when upper layer believe some BSS parameters need to be changed (BSSID, TX power, beacon interval, etc)\n-\t**conf_tx**. It is called when upper layer needs to config/change some tx parameters (AIFS, CW_MIN, CW_MAX, TXOP, etc)\n-\t**prepare_multicast**. It is called when upper layer needs to prepare multicast, currently only a empty function hook is present.\n-\t**configure_filter**. It is called when upper layer wants to config/change the [frame filtering](#Rx-packet-flow-and-filtering-config) rule in FPGA.\n-\t**rfkill_poll**. It is called when upper layer wants to know the RF status (ON/OFF).\n-\t**get_tsf**. It is called when upper layer wants to get 64bit FPGA timer value (TSF - Timing synchronization function) \n-\t**set_tsf**. It is called when upper layer wants to set 64bit FPGA timer value\n-\t**reset_tsf**. It is called when upper layer wants to reset 64bit FPGA timer value\n-\t**set_rts_threshold**. It is called when upper layer wants to change the threshold (packet length) for turning on RTS mechanism\n-\t**ampdu_action**. AMPDU (Aggregated Mac PDU) related operations\n-\t**testmode_cmd**. It is called when upper layer has test command for us. [sdrctl command](#sdrctl-command) message is handled by this function.\n\nAbove APIs are called by upper layer (Linux mac80211 subsystem). When they are called, the driver (sdr.c) will do necessary job via openwifi FPGA implementation. If necessary, the driver will call other component drivers, like tx_intf_api/rx_intf_api/openofdm_tx_api/openofdm_rx_api/xpu_api, for help.\n\nAfter receiving a packet from the air, FPGA will raise interrupt (if the frame filtering rule allows) to Linux, then the function openwifi_rx_interrupt() of openwifi driver (sdr.c) will be triggered. In that function, ieee80211_rx_irqsafe() API is used to give the packet and related information (timestamp, rssi, etc) to upper layer.\n\nThe packet sending is initiated by upper layer towards openwifi driver. After the packet is sent by the driver over FPGA to the air, the upper layer will expect a sending report from the driver. Each time FPGA sends a packet, an interrupt will be raised to Linux and trigger openwifi_tx_interrupt(). This function will report the sending result (failed? succeeded? number of retransmissions, etc.) to upper layer via ieee80211_tx_status_irqsafe() API.\n\n## sdrctl command\n\nBesides the Linux native Wi-Fi control programs, such as ifconfig/iw/iwconfig/iwlist/wpa_supplicant/hostapd/etc, openwifi offers a user space tool sdrctl to access openwifi specific functionalities, such as time sharing of the interface between two network slices, arbitrary Tx/Rx frequency, Tx attenuation, etc. you may find more details of the slicing mechanism [here](https://doc.ilabt.imec.be/ilabt/wilab/tutorials/openwifi.html#sdr-tx-time-slicing).\n\nsdrctl is implemented as nl80211 testmode command and communicates with openwifi driver (function openwifi_testmode_cmd() in sdrctl_intf.c) via Linux nl80211--cfg80211--mac80211 path \n\n### Get and set a parameter\n```\nsdrctl dev sdr0 get para_name\nsdrctl dev sdr0 set para_name value \n```\npara_name|meaning|comment\n---------|-------|----\nslice_idx|the slice that will be set/get|0 to 3. After finishing all slice config, **set slice_idx to 4** to synchronize all slices. Otherwise the start/end of different slices have different actual time\naddr|target MAC address of tx slice_idx|32bit. for address 6c:fd:b9:4c:b1:c1, you set b94cb1c1\nslice_total|tx slice_idx cycle length in us|for length 50ms, you set 49999\nslice_start|tx slice_idx cycle start time in us|for start at 10ms, you set 10000\nslice_end|  tx slice_idx cycle end   time in us|for end   at 40ms, you set 39999\ntsf| sets TSF value| it requires two values \"high_TSF low_TSF\". Decimal\n\n### Get and set a register of a module\n```\nsdrctl dev sdr0 get reg module_name reg_idx\nsdrctl dev sdr0 set reg module_name reg_idx reg_value \n```\nmodule_name **drv_rx**/**drv_tx**/**drv_xpu**/**rf** refers to the corresponding driver functionality. Related registers are defined in sdr.h. Search drv_rx_reg_val/drv_tx_reg_val/drv_xpu_reg_val/rf_reg_val to see their functionalities.\n\nmodule_name **rx_intf**/**tx_intf**/**rx**/**tx**/**xpu** FPGA modules (rx_intf/tx_intf/openofdm_rx/openofdm_tx/xpu). Related register addresses are defined in hw_def.h and mapped to slv_regX in .v file (X is the register index). Check rx_intf/tx_intf/openofdm_rx/openofdm_tx/xpu.c and .v files to see their functionalities.\n\nmodule name **rf** refers to RF (ad9xxx front-end). The agent register rf_reg_val is defined in sdr.h.\n\nPlease be aware that some registers are set by driver in real-time (instructed by Linux mac80211), so be careful when set them manually.\n\nmodule_name: **drv_rx** (for full list, search drv_rx_reg_val in sdr.c)\n\nreg_idx|meaning|comment\n-------|-------|----\n0|receiver action threshold|receiver will not react (short preamble search and further) if the signal strength is less than this threshold. N means -NdBm\n4|rx antenna selection|0:rx1, 1:rx2\n7|dmesg print control|please check Debug methods section in this page\n\n(In the **comment** column, you may get a list of **decimalvalue(0xhexvalue):explanation** for a register, only use the **decimalvalue** in the sdrctl command)\n\nmodule_name: **drv_tx** (for full list, search drv_tx_reg_val in sdr.c)\n\nreg_idx|meaning|comment\n-------|-------|----\n0|override Linux rate control of non-ht TX unicast data packet|0:auto by Linux, 4:6M, 5:9M, 6:12M, 7:18M, 8:24M, 9:36M, 10:48M, 11:54M\n1|override Linux rate control of ht TX unicast data packet|0:auto by Linux, 4:6.5M, 5:13M, 6:19.5M,7:26M, 8:39M, 9:52M, 10:58.5M, 11:65M (add 16 to these values for short GI rate)\n2|override Linux rate control of vht (11ac)|not implemented yet\n3|override Linux rate control of he (11ax)|not implemented yet\n4|tx antenna selection|0:tx1, 1:tx2\n7|dmesg print control|please check Debug methods section in this page\n\nmodule_name: **drv_xpu** (for full list, search drv_xpu_reg_val in sdr.c)\n\nreg_idx|meaning|comment\n-------|-------|----\n0|LBT/CCA threshold|0: automatic threshold by ad9361_rf_set_channel(). others -- N means -NdBm fixed threshold\n7|git revision when build the driver|return the git revision in hex format\n\nmodule_name: **rf**\n\nreg_idx|meaning|comment\n-------|-------|----\n0|TX attenuation in dB\\*1000|example: set to 3000 for 3dB attenuation\n1|TX frequency in MHz|example: set to 5000 for 5GHz -- override Linux channenl tuning/control\n5|RX frequency in MHz|example: set to 4000 for 4GHz -- override Linux channenl tuning/control\n\nmodule_name: **rx_intf** (for full list, check rx_intf.c and **slv_reg** in rx_intf.v)\n\nreg_idx|meaning|comment\n-------|-------|----\n0|reset|each bit is connected to rx_intf.v internal sub-module. 1 -- reset; 0 -- normal\n1|trigger for ILA debug|bit4 and bit0. Please check slv_reg1 in rx_intf.v\n2|enable/disable rx interrupt|256(0x100):disable, 0:enable\n3|get loopback I/Q from tx_intf|256(0x100):from tx_intf, 0:from ad9361 ADC\n4|baseband clock and IQ fifo in/out control|no use anymore -- for old bb rf independent mode\n5|control/config dma to cpu|check rx_intf.v slv_reg5\n6|abnormal packet length threshold|bit31-16 to store the threshold. if the packet length is not in the range of 14 to threshold, terminate the dma to cpu\n7|source selection of rx dma to cpu|check rx_intf.v slv_reg7\n8|reserved|reserved\n9|number of dma symbol to cpu|only valid in manual mode (slv_reg5[5]==1). normally the dma is set automatically by the received packet length\n10|rx adc fifo reading control|check rx_intf.v slv_reg10\n11|rx digital I/Q gain|number of bit shift to left. default 4 in rx_intf.c: rx_intf_api->RX_INTF_REG_BB_GAIN_write(4)\n12|timeout/reset control of dma to cpu|check rx_intf.v slv_reg12\n13|delay from RX DMA complete to RX packet interrupt to cpu|unit 0.1us\n16|rx antenna selection|0:ant0, 1:ant1. default 0\n\nmodule_name: **tx_intf** (for full list, check tx_intf.c and **slv_reg** in tx_intf.v)\n\nreg_idx|meaning|comment\n-------|-------|----\n0|reset|each bit is connected to tx_intf.v internal sub-module. 1 -- reset; 0 -- normal\n1|DUC config or tx arbitrary IQ write port|DUC is removed already. Now it is used to write arbitrary IQ to tx_intf for test purpose\n2|phy tx auto start config|check tx_intf.v slv_reg2\n4|CTS to Self config|auto set by cts_reg in openwifi_tx of sdr.c. bit31: enable/disable, bit30: rate selection: 1: use traffic rate, 0: manual rate in bit7-4, bit23-8: duration field\n5|csi fuzzer config|check CSI fuzzer app note\n6|CTS to Self sending delay (for SIFS)|unit 0.1us. bit13-0 for 2.4GHz, bit29-16 for 5GHz\n7|tx arbitrary IQ config|check tx_intf.v slv_reg7\n8|tx config per packet|automatically set per packet in openwifi_tx() via tx_intf_api->TX_INTF_REG_TX_CONFIG_write(tx_config)\n9|reserved|reserved\n10|dac input and dma control|check tx_intf.v slv_reg10\n11|threshold for FPGA fifo almost full|driver(sdr.c) read 1bit flag in slv_reg21 (4bit in total for 4 queue) to know the FPGA fifo/queue is almost full.\n12|threshold to pause openofdm_tx|unit: number of sample. back pressure flow control for I/Q generation speed of openofdm_tx\n13|tx I/Q digital gain before dac|find the optimal value (and test record) in tx_intf.c: tx_intf_api->TX_INTF_REG_BB_GAIN_write\n14|tx interrupt config|196612(0x30004):disable, 4:enable. check tx_intv.v slv_reg14\n15|ampdu action config|set automatically in driver (sdr.c) by openwifi_ampdu_action()\n16|tx antenna selection and cdd control|bit1: 0 or 1 to select ant0 or 1. bit4: 1 to enable simple cdd (two antennas have 1 sample tx delay)\n17|phy config per packet|aggregation/rate/GI/ht/non-ht/etc. automatically set by driver tx_intf_api->TX_INTF_REG_PHY_HDR_CONFIG_write(phy_hdr_config)\n21|queue almost full flag|4bit for 4 queue. criteria is the threshold in slv_reg11. check by tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read() in sdr.c\n22|tx status0 per pkt sent|cw,num_slot_random,linux_prio,tx_queue_idx,bd_wr_idx,num_retrans -- per pkt info read by tx interrupt after the pkt sent\n23|tx status1 per pkt sent|blk_ack_resp_ssn, pkt_cnt -- per pkt info read by tx interrupt after the pkt sent\n24|tx status2 per pkt sent|blk_ack_bitmap_low -- per pkt info read by tx interrupt after the pkt sent\n25|tx status3 per pkt sent|blk_ack_bitmap_high -- per pkt info read by tx interrupt after the pkt sent\n26|FPGA tx queue runtime length|bit6-0: queue0; bit14-8: queue1; bit22-16: queue2; bit30-24: queue3\n\nmodule_name: **rx** (for full list, check openofdm_rx.c and **slv_reg** in openofdm_rx.v)\n\nreg_idx|meaning|comment\n-------|-------|----\n0|reset|each bit is connected to openofdm_rx.v internal sub-module. 1 -- reset; 0 -- normal\n1|misc settings|bit0: 1--force smoothing; 0--auto by ht header. bit4: 1--disable all smoothing; 0--let bit0 decide. bit8: 0--high sensitivity sync short; 1--less fake sync short. bit12: 0--watchdog runs regardless power trigger; 1--runs only when power trigger. bit13: 0--watchdog runs regardless state; 1--runs only when state <= S_DECODE_SIGNAL. bit16: 0--enable watchdog eq monitor; 1--disable eq monitor\n2|power trigger and dc detection threshold|bit10-0: signal level below this threshold won't trigger demodulation. the unit is rssi_half_db, check rssi_half_db_to_rssi_dbm()/rssi_dbm_to_rssi_half_db() in sdr.c to see the relation to rssi dBm. bit23-16: threshold to prevent dc (or low frequency interference) triggered demodulation\n3|minimum plateau used for short preamble detection|initialized by openofdm_rx.c: openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write\n4|soft decoding flag and abnormal packet length threshold|bit0 for soft decoding: 0--hard; 1--soft. bit31-16: if the packet length is longer this threshold, terminate demodulation. bit15-12: minimum packet length threshold to terminate demodulation\n5|fft_win_shift and small eq monitor threshold|bit3-0: fft window shift (default 4). bit9-4: threshold of how many very small eq out is counted to decide whether reset receiver\n17|selector for watchdog event counter|0--phase_offset(sync_short) too big. 1--too many eq out small values. 2--dc is detected (threshold slv_reg2[23:16]). 3--packet too short. 4--packet too long.\n18|sync_short phase_offset (frequency offset) threshold|watchdog will reset receiver if phase_offset is above the threshold\n19|sync_short phase_offset override|bit31: 1--enable override; 0--disable. bit15-0: value to be set (SIGNED value!)\n20|history of PHY rx state|read only. If the last digit readback is always 3, it means the Viterbi decoder stops working\n21|read back Fc_in_MHz and sync_short phase_offset|bit31-16: Fc_in_MHz. bit15-0: phase_offset\n30|read back watchdog event counter(selected by reg 17)|write to this register, the event counter (selected by reg 17) will be cleared\n31|git revision when build the receiver|returned register value means git revision in hex format\n\nmodule_name: **tx** (for full list, check openofdm_tx.c and **slv_reg** in openofdm_tx.v)\n\nreg_idx|meaning|comment\n-------|-------|----\n0|reset|each bit is connected to openofdm_tx.v internal sub-module. 1 -- reset; 0 -- normal\n1|pilot scrambler initial state|lowest 7 bits are used. 127(0x7F) by default in openofdm_tx.c\n2|data  scrambler initial state|lowest 7 bits are used. 127(0x7F) by default in openofdm_tx.c\n20|reserved|reserved\n\nmodule_name: **xpu** (for full list, check xpu.c and **slv_reg** in xpu.v)\n\nreg_idx|meaning|comment\n-------|-------|----\n0|reset|each bit is connected to xpu.v internal sub-module. 1 -- reset; 0 -- normal\n1|rx packet and I/Q config when tx|bit0 0: auto control (auto self-rx-IQ-mute when tx), 1:manual control by bit31 (1 self-IQ-mute; 0 unmute). bit2 0: rx packet filtering is configured by Linux, 1: no rx packet filtering, send all to Linux\n2|TSF timer low  32bit write|only write this register won't trigger the TSF timer reload. should use together with register for high 31bit\n3|TSF timer high 31bit write|falling edge of register MSB will trigger the TSF timer reload, which means write '1' then '0' to bit31 (bit30-0 for TSF)\n4|band, channel and ERP short slot setting|for CSMA engine config. set automatically by Linux. manual set could be overrided unless you change sdr.c. Channel means frequency in MHz\n5|DIFS and backoff advance (us), abnormal pkt length threshold|advance (us) for tx preparation before the end of DIFS/backoff. bit7-0:DIFS advance, bit15-8: backoff advance. bit31-16: if the packet length is not in the range of 14 to this threshold, terminate pkt filtering procedure\n6|multi purpose CSMA settings|bit7-0: forced channel idle (us) after decoding done to avoid false alarm caused by strong \"AGC tail\" signal. bit31: NAV disable, bit30: DIFS disable, bit29: EIFS disable, bit28: dynamic CW disable (when disable, CW is taken from bit19-16). (value 1 -- forced disable; 0 -- normal/enable)\n7|RSSI and ad9361 gpio/gain delay setting (sync with IQ rssi)|bit26-16: offset for rssi report to Linux; bit6-0 delay (number of sample) of ad9361 gpio/gain to sync with IQ sample rssi/amplitude\n8|RSSI threshold for CCA (channel idle/busy)|set by ad9361_rf_set_channel automatically. the unit is rssi_half_db, check rssi_half_db_to_rssi_dbm()/rssi_dbm_to_rssi_half_db() in sdr.c to see the relation to rssi dBm\n9|some low MAC time setting|bit31 0:auto, 1:manual. When manual, bit6-0: PHY rx delay, bit13-7: SIFS, bit18-14: slot time, bit23-19: ofdm symbol time, bit30-24: preamble+SIG time. unit us. check xpu.v (search slv_reg9)\n10|BB RF delay setting|unit 0.1us. bit7-0: BB RF delay, bit14-8: RF end extended time on top of the delay. bit22-16: delay between bb tx start to RF tx on (lo or port control via spi). bit30-24: delay between bb tx end to RF tx off. check xpu.v (search slv_reg10)\n11|ACK control and max num retransmission|bit4: 0:normal ACK tx/reply, 1:disable auto ACK tx/reply in FPGA. bit5: 0:normal ACK rx from peer, 1:not expecting ACK rx from peer. bit3-0: if bit3==0, the number of retransmission is decided by Linux. if bit3==1, the max num retransmission is taken from bit2-0\n12|AMPDU control|bit0: indicate low MAC start to receive AMPDU. bit4-1: tid. bit31: tid enable (by default, tid is not enabled and we decode AMPDU of all tid)\n13|spi controller config|1: disable spi control and Tx RF is always on; 0: enable spi control and Tx RF only on (lo/port) when pkt sending\n16|setting when wait for ACK in 2.4GHz|unit 0.1us. bit14-0: OFDM decoding timeout (after detect PHY header), bit30-16: timeout for PHY header detection, bit31: 0: FCS valid is not needed for ACK packet, 1: FCS valid is needed for ACK packet\n17|setting when wait for ACK in 5GHz|unit 0.1us. bit14-0: OFDM decoding timeout (after detect PHY header), bit30-16: timeout for PHY header detection, bit31: 0: FCS valid is not needed for ACK packet, 1: FCS valid is needed for ACK packet\n18|setting for sending ACK|unit 0.1us. bit14-0: ACK sending delay in 2.4GHz, bit30-16: ACK sending delay in 5GHz\n19|CW min and max setting for 4 FPGA queues|bit3-0: CW min for queue 0, bit7-4: CW max for queue 0, bit11-8: CW min for queue 1, bit15-12: CW max for queue 1, bit19-16: CW min for queue 2, bit23-20: CW max for queue 2, bit27-24: CW min for queue 3, bit31-28: CW max for queue 3. automatically decided by Linux via openwifi_conf_tx of sdr.c\n20|slice/queue-tx-gate total cycle length|bit21-20: queue selection. bit19-0: total cycle length in us\n21|slice/queue-tx-gate start time in the cycle|bit21-20: queue selection. bit19-0: start time in us\n22|slice/queue-tx-gate end time in the cycle|bit21-20: queue selection. bit19-0: end time in us\n26|CTS to RTS setting|bit15-0: extra duration, bit20-16: rate/MCS, bit31: 0:enable CTStoRTS 1:disable CTStoRTS\n27|FPGA packet filter config|bit13-0 passing/filter config. bit24-16 dropping config. check openwifi_configure_filter in sdr.c. also [mac80211 frame filtering](https://www.kernel.org/doc/html/v4.9/80211/mac80211.html#frame-filtering)\n28|BSSID address low  32bit for BSSID filtering|auto set by xpu_api->XPU_REG_BSSID_FILTER_LOW_write in openwifi_bss_info_changed of sdr.c\n29|BSSID address high 16bit for BSSID filtering|auto set by xpu_api->XPU_REG_BSSID_FILTER_HIGH_write in openwifi_bss_info_changed of sdr.c\n30|MAC address low  32bit|auto set by XPU_REG_MAC_ADDR_write in sdr.c\n31|MAC address high 16bit|auto set by XPU_REG_MAC_ADDR_write in sdr.c\n57|rssi_half_db read back together with channel idle and other CSMA states|Check slv_reg57 in xpu.v. Use rssi_openwifi_show.sh and rssi_ad9361_show.sh together for RSSI checking.\n58|TSF runtime value low  32bit|read only\n59|TSF runtime value high 32bit|read only\n62|addr2 of rx packet read back|bit31-0 are from bit47-16 of addr2 field in the received packet\n63|git revision when build the FPGA|returned register value means git revision in hex format\n\n## Rx packet flow and filtering config\n\nAfter FPGA receives a packet, no matter the FCS/CRC is correct or not it will raise interrupt to Linux if the frame filtering rule allows (See also [mac80211 frame filtering](https://www.kernel.org/doc/html/v4.9/80211/mac80211.html#frame-filtering)). openwifi_rx_interrupt() function in sdr.c serves the interrupt and gives the necessary information to upper layer (Linux mac80211 subsystem) via ieee80211_rx_irqsafe.\n\n- frame filtering\n\nThe FPGA frame filtering configuration is done by function openwifi_configure_filter() in sdr.c. The filter_flag together with **HIGH_PRIORITY_DISCARD_FLAG** finally go to pkt_filter_ctl.v of xpu module in FPGA, and control how FPGA does frame filtering. Openwifi has the capability to capture all received packets even if the CRC is wrong. You just need to set the NIC to monitor mode by iwconfig command (check monitor_ch.sh in user_space directory). In monitor mode, all received packets (including control packet, like ACK) will be given to Linux mac80211. \n\n- main rx interrupt operations in openwifi_rx_interrupt()\n  - get raw content from DMA buffer. When Linux receives interrupt from FPGA rx_intf module, the content has been ready in Linux DMA buffer\n  - parse extra information inserted by FPGA in the DMA buffer\n    - TSF timer value\n    - raw RSSI value that will be converted to actual RSSI in dBm by different correction in different bands/channels\n    - packet length and MCS\n    - FCS is valid or not\n  - send packet pointer (skb) and necessary extra information to upper layer via ieee80211_rx_irqsafe()\n\n## Tx packet flow and config\n\nLinux mac80211 subsystem calls openwifi_tx() to initiate a packet sending. \n\n- main operations in openwifi_tx()\n  - get necessary information from the packet header (struct ieee80211_hdr) for future FPGA configuration\n    - packet length and MCS\n    - unicast or broadcast? does it need ACK? how many retransmissions at most are allowed to be tried by FPGA in case ACK is not received in time?\n    - which driver-ring/queue (time slice) in FPGA the packet should go?\n    - should RTS-CTS be used? (Send RTS and wait for CTS before actually send the data packet)\n    - should CTS-to-self be used? (Send CTS-to-self packet before sending the data packet. You can force this on by force_use_cts_protect = true;)\n    - should a sequence number be inserted to the packet at the driver/chip level?\n  - maintain sequence number (ring->bd_wr_idx) for internal use (cross check between FPGA, openwifi_tx and openwifi_tx_interrupt)\n  - config FPGA register according to the above information to help FPGA do correct actions (generate PHY header, etc) according to the packet specific requirement.\n  - fire DMA transmission from Linux to one of FPGA tx queues. The packet may not be sent immediately if there are still some packets in FPGA tx queue (FPGA does the queue packet transmission according to channel and low MAC CSMA state)\n    \nEach time when FPGA sends a packet, an interrupt will be raised to Linux reporting the packet sending result. This interrupt handler is openwifi_tx_interrupt().\n\n- main operations in openwifi_tx_interrupt()\n  - get necessary information/status of the packet just sent by FPGA\n    - packet length and sequence number to capture abnormal situation (cross checking between FPGA, openwifi_tx and openwifi_tx_interrupt)\n    - packet sending result: packet is sent successfully (FPGA receives ACK for this packet) or not. How many retransmissions have been done (in case FPGA doesn't receive ACK in time, FPGA will do retransmission according to CSMA/CA low MAC state)\n  - send above information to upper layer (Linux mac80211 subsystem) via ieee80211_tx_status_irqsafe()\n\n## Understand the timestamp of WiFi packet\n\nThe TSF timestamp shown in the usual wireshark snapshot is reported by openwifi Linux driver towards Linux mac80211 framework.\n![](https://user-images.githubusercontent.com/5212105/270659135-44a048ae-773f-48a7-bf3f-76ffc3ee399a.jpg)\n\nThis TSF timestamp is attached to the DMA of the received packet in FPGA by reading the TSF timier (defined by 802.11 standard and implemented in FPGA) value while PHY header is received: [FPGA code snip](https://github.com/open-sdr/openwifi-hw/blob/14b1e840591f470ee945844cd3bb51a95d7da09f/ip/rx_intf/src/rx_intf_pl_to_m_axis.v#L201).\n\nThen openwifi driver report this timestamp value (together with the corresponding packet) to Linux via:\nhttps://github.com/open-sdr/openwifi/blob/0ce2e6b86ade2f6164a373b2e98d075eb7eecd9e/driver/sdr.c#L530\n\nTo match the openwifi side channel collected data (CSI, IQ sample, etc.) to the TSF timestamp of the packet, please check: https://github.com/open-sdr/openwifi/discussions/344\n\n## Regulation and channel config\n\nSDR is a powerful tool for research. It is the user's responsibility to align with local spectrum regulation when doing OTA (Over The Air) test, or do the test via cable (conducted test), or in a chamber to avoid any potential interference.\n\nThis section explains how openwifi config the frequency/channel range and change it driven by Linux. The frequency overriding method is also offered by openwifi to allow the system working in any frequency in 70MHz-6GHz.\n\n### Frequency range\n\nWhen openwifi driver is loaded, openwifi_dev_probe() will be executed. Following two lines configure the frequency range:\n```\ndev->wiphy->regulatory_flags = xxx\nwiphy_apply_custom_regulatory(dev->wiphy, &sdr_regd);\n```\nsdr_regd is the predefined variable in sdr.h. You can search the definition/meaning of its type: struct ieee80211_regdomain. \n\n### Supported channel\n\nThe supported channel list is defined in openwifi_2GHz_channels and openwifi_5GHz_channels in sdr.h. If you change the number of supported channels, make sure you also change the frequency range in sdr_regd accordingly and also array size of the following two fields in the struct openwifi_priv:\n```\nstruct ieee80211_channel channels_2GHz[14];\nstruct ieee80211_channel channels_5GHz[53];\n```\nFinally, the supported channel list is transferred to Linux mac80211 when openwifi driver is loaded by following two lines in openwifi_dev_probe():\n```\ndev->wiphy->bands[NL80211_BAND_2GHZ] = &(priv->band_2GHz);\ndev->wiphy->bands[NL80211_BAND_5GHZ] = &(priv->band_5GHz);\n```\n\n### Real-time channel setting and restrict the channel\n\nLinux mac80211 (struct ieee80211_ops openwifi_ops in sdr.c) uses the \"config\" API to configure channel frequency and some other parameters in real-time (such as during scanning or channel setting by iwconfig). It is hooked to openwifi_config() in sdr.c, and supports only frequency setting currently. The real execution of frequency setting falls to ad9361_rf_set_channel() via the \"set_chan\" field of struct openwifi_rf_ops ad9361_rf_ops in sdr.c. Besides tuning RF front-end (AD9361), the ad9361_rf_set_channel() also handles AD9361 calibration (if the tuning step size >= 100MHz), RSSI compensation for different frequencies and FPGA configurations (SIFS, etc) for different bands.\n\nIf you don't want openwifi node to change the channel anymore (even the Linux asks to do so), use the script user_space/set_restrict_freq.sh to limit the frequency.\n```\n./set_restrict_freq abcd\n```\nAbove will limit the frequency to abcdMHz. For instance, after you setup the working system in channel 44 and you don't want the node to tune to other channel (occasionally driven by Linux scanning for example), input 5220 as argument to the script.\n```\n./set_restrict_freq 0\n```\nAbove will remove the limitation. Linux driven channel tuning will be recovered.\n\n### Let openwifi work at arbitrary frequency\n\nBefore setting a non-standard frequency to the system, a normal working system should be setup in normal/legal WiFi frequency, which should be as close as possible to the target non-standard frequency. Then use **set_restrict_freq.sh** (see above) to force upper layer to stay at that normal WiFi frequency (no scanning anymore). After this, you can set actual RF frequency to any frequency in 70MHz-6GHz (without notifying upper layer).\n```\n./sdrctl dev sdr0 set reg rf 1 3500 \n```\nAbove will set the Tx frequency to 3.5GHz.\n\n```\n./sdrctl dev sdr0 set reg rf 5 3500 \n```\nAbove will set the Rx frequency to 3.5GHz.\n\n## Analog and digital frequency design\n\nOpenwifi has adopted a new RF/baseband frequency and sampling design instead of the original \"offset tuning\" to achieve better EVM, spectrum mask conformance, sensitivity and RSSI measurement accuracy. The AD9361 is set to FDD working mode with the same Tx and Rx frequency. Realtime AD9361 Tx chain control is done via FPGA SPI interface (openwifi-hw/ip/xpu/src/spi.v) to achieve self-interference free (when Rx) and fast Tx/Rx turn around time (0.6us). The AD9361 Tx lo (local oscillator) or RF switch is turned on before the Tx packet and turned off after the Tx packet. so that there isn't any Tx lo noise leakage during Rx period. The IQ sampling rate between AD9361 and FPGA is 40Msps. It is converted to 20Msps via decimation/interpolation inside FPGA to WiFi baseband transceiver.\n\nFollowing figure shows the detailed configuration point in AD9361, driver (.c file) and related FPGA modules (.v file).\n![](./rf-digital-if-chain-config.jpg)\n\nThe openwifi FPGA baseband clock is driven by AD9361 clock, so there won't be any clock drifting/slight-mismatching between RF and baseband as shown in the following picture.\n![](./bb-clk.jpg)\n\n## Debug methods\n\n### dmesg\n\nTo debug/see the basic driver behaviour via printk in the sdr.c, you could turn on **dmesg** message printing by \n```\n./sdrctl dev sdr0 set reg drv_tx 7 X\n./sdrctl dev sdr0 set reg drv_rx 7 X\n\nThe bit in value X controls what type of information will be printed to the dmesg (0--no print; 1--print).\nbit0: error   message\nbit1: regular message for unicast packet (openwifi_tx/openwifi_tx_interrupt/openwifi_rx_interrupt)\nbit2: regular message for broadcast packet\nbit3: regular queue stop/wake-up message due to too much traffic\n\nFor example, regular message for unicast packet and error message\n./sdrctl dev sdr0 set reg drv_tx 7 3\n./sdrctl dev sdr0 set reg drv_rx 7 3\n\nFor example, error message only:\n./sdrctl dev sdr0 set reg drv_tx 7 1\n./sdrctl dev sdr0 set reg drv_rx 7 1\n```\nand use **dmesg** command in Linux to see those messages. Regular printing includes tx/rx packet information when a packet is sent or received. Error printing has WARNING information if something abnormal happens. You can search \"printk\" in sdr.c to see all the printing points.\n\n### tx printing example\n```\nsdr,sdr openwifi_tx: 70B RC0 10M FC0040 DI0000 ADDRffffffffffff/6655443322aa/ffffffffffff flag4001201e QoS00 SC20_1 retr1 ack0 prio0 q0 wr19 rd18\n```\n- printing from sdr driver, openwifi_tx function\n- 70B: packet size (length field in SIGNAL)\n- RC0: rate of the packet. enum mac80211_rate_control_flags in Linux kernel mac80211.h\n- 10M: rate 1Mbps. This 802.11b rate will be converted to 6Mbps, because openwifi supports only OFDM rate.\n- FC0040: Frame Control field. Example: FC0208 means type data, subtype data, to DS 0, from DS 1 (a packet from AP to client)\n- DI0000: Duration/ID field\n- ADDR: address fields addr1/2/3. Target MAC address ffffffffffff (broadcast), source MAC address 6655443322aa (openwifi)\n- flag4001201e: flags field from Linux mac80211 struct ieee80211_tx_info (first fragment? need ACK? need sequence number insertion? etc.)\n- QoS00: QoS control byte related to the packet (from Linux mac80211)\n- SC20_1: sequence number 20 is set to the header of the packet. 1 means that it is set by driver (under request of Linux mac80211)\n- retr1: retr1 means no retransmission is needed. retr6 means the maximum number of transmissions for this packet is 6 (set by Linux mac80211)\n- ack0: ack0 means the packet doesn't need ACK; ack1 means the packet needs ACK. (set by Linux mac80211)\n- prio0: priority queue 0 for this packet (0:VO voice, 1:VI video, 2:BE best effort and 3:BK background). check prio in openwifi_tx() of sdr.c (set by Linux mac80211)\n- q0: the packet goes to FPGA queue 0. (You can change the mapping between Linux priority and FPGA queue in sdr.c)\n- wr19 rd18: the write/read index of buffer (shared buffer between the active openwifi_tx and background openwifi_tx_interrupt/FPGA)\n  \n### tx interrupt printing example\n```\nsdr,sdr openwifi_tx_interrupt: tx_result [nof_retx 1 pass 1] SC20 prio0 q0 wr20 rd19 num_slot0 cw0 hwq len00000000 no_room_flag0\n```\n- printing from sdr driver, openwifi_tx_interrupt function\n- tx_result [nof_retx 1 pass 1]: nof_retx 1 means the total number of transmission is 1. pass 1 indicates ACK is received. (0 means not)\n- SC20: sequence number 20\n- prio, q, wr, rd: these fields can be interpreted the same way as the print in openwifi_tx function\n- num_slot: tells how many slots the CSMA/CA state machine waited until the packet is sent in the last tx attempt\n- cw: the exponent of the Contention Window for this packet. 6 means the CW size 64. If the contention phase is never entered, CW is 0\n- hwq len: the current FPGA queue length (number of pkt left in the queue).8bit per queue. see tx_intf register 26 in the register table section.\n- no_room_flag: the DMA room of FPGA queue is almost run out. 1bit per queue. see tx_intf register 21 in the register table section.\n\n### rx printing example\n```\nsdr,sdr openwifi_rx: 270B ht0aggr0/0 sgi0 240M FC0080 DI0000 ADDRffffffffffff/00c88b113f5f/00c88b113f5f SC2133 fcs1 buf_idx10 -78dBm\n```\n- printing from sdr driver, openwifi_rx_interrupt function\n- 270B: packet size (length field in SIGNAL)\n- ht0: ht0 means 11a/g (legacy); ht1 means 11n (ht)\n- aggr0/0: the 1st digit means the packet is from a AMPDU packet (1) or not (0). the 2nd digit means the packet is the last packet of a AMPDU packet (1) or not (0)\n- sgi0: 0 means normal GI (Guard Interval); 1 means short GI\n- 240M:  rate 24Mbps\n- FC0080: Frame Control field. Example: FC0108 means type data, subtype data, to DS 1, from DS 0 (a packet client to openwifi AP)\n- DI0000: Duration/ID field\n- ADDR: address fields addr1/2/3. Target MAC address ffffffffffff (broadcast), source MAC address 00c88b113f5f\n- SC2133: sequence number 2133 from the header of the packet\n- fcs1: FCS/CRC is OK. (fcs0 means bad CRC)\n- buf_idx10: the rx packet is from DMA buffer with index 10\n- -78dBm: signal strength of this received packet (after calibration)\n\n### Native Linux tools\n\nFor analysis/debug, many native Linux tools you still could rely on. Such as tcpdump, tshark, etc.\n\n### Debug FPGA\n\nFor FPGA itself, FPGA developer could use Xilinx ILA tools to analyze FPGA signals (https://github.com/open-sdr/openwifi-hw/issues/39). Spying on those state machines in xpu/tx_intf/rx_intf would be very helpful for understanding/debugging Wi-Fi low level functionalities.\n\n## Test mode driver\n\nWhile loading the openwifi driver by \"insmod sdr.ko\", a test_mode argument can be specified (You can also specify the test_mode value to wgd.sh or fosdem.sh). It will enable some experimental feataures (such as AMPDU aggregation):\n```\ninsmod sdr.ko test_mode=value\n```\nIt is implemented by the global static variable test_mode in sdr.c.\n\nSupported test_mode value definitions:\n- bit0: AMPDU/aggregation is ON (1) or OFF (0 -- default OFF)\n"
  },
  {
    "path": "doc/app_notes/40mhz.png.license",
    "content": "# Author: Xianjun jiao\n\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n"
  },
  {
    "path": "doc/app_notes/README.md",
    "content": "<!--\nAuthor: Xianjun jiao\nSPDX-FileCopyrightText: 2019 UGent\nSPDX-License-Identifier: AGPL-3.0-or-later\n-->\n\nApplication notes collect many small topics about using openwifi in different scenarios/modes.\n\n- [Use openwifi on the w-iLab.t testbed remotely](https://doc.ilabt.imec.be/ilabt/wilab/tutorials/openwifi.html)\n- [Communication between two SDR boards under AP and client mode](ap-client-two-sdr.md)\n- [Communication between two SDR boards under ad-hoc mode](ad-hoc-two-sdr.md)\n- [From CSI (Channel State Information) to CSI (Chip State Information)](csi.md)\n- [WiFi CSI radar via self CSI capturing](radar-self-csi.md)\n- [Capture IQ sample, AGC gain, RSSI with many types of trigger condition](iq.md)\n- [ACK timing verification by IQ capture](iq_ack_timing.md)\n- [Capture dual antenna TX/RX IQ for multi-purpose (capture collision)](iq_2ant.md)\n- [WiFi packet, CSI and IQ sample self loopback test (over-the-air and FPGA internal)](packet-iq-self-loopback-test.md)\n- [IEEE 802.11n (Wi-Fi 4)](ieee80211n.md)\n- [802.11 packet injection and fuzzing](inject_80211.md)\n- [CSI fuzzer](csi_fuzzer.md)\n- [Access counter/statistics in FPGA](perf_counter.md)\n- [Access counter/statistics in driver](driver_stat.md)\n- [Frequent/usual trick on controlling Gain/Att/Frequency/CCA/LBT/CSMA/CW/Sensitivity/etc](frequent_trick.md)\n- [Driver and FPGA dynamic reloading](drv_fpga_dynamic_loading.md)\n- [owfuzz: a WiFi protocol fuzzing tool using openwifi.](https://github.com/alipay/WiFi-Protocol-Fuzzing-Tool) [[**Vulnerabilities**]](https://github.com/alipay/Owfuzz#discovered-vulnerabilities)\n- [Build FPGA with High-Level Synthesis modules](hls.md)\n"
  },
  {
    "path": "doc/app_notes/ad-hoc-two-sdr.md",
    "content": "<!--\nAuthor: Xianjun jiao\nSPDX-FileCopyrightText: 2019 UGent\nSPDX-License-Identifier: AGPL-3.0-or-later\n-->\n\n**NOTE** the terminal session mentioned in the following text can also be setup via USB-UART instead of Ethernet.\n\n**NOTE** adrv9361z7035 has ultra low TX power in 5GHz. Move **CLOSER** when you use that board in 5GHz!!!\n\n- Power on two SDR boards. Call one board \"adhoc1\" and the other \"adhoc2\". On each board, the TX and RX antenna should vertical/orthogonal to each other as much as possible to gain a good TX/RX isolation.\n- Connect a computer to the adhoc1 via Ethernet cable. The computer should have static IP 192.168.10.1. Open a terminal on the computer, and then in the terminal:\n  ```\n  ssh root@192.168.10.122\n  (password: openwifi)\n  service network-manager stop\n  cd openwifi\n  ./wgd.sh\n  (Wait for the script completed)\n  ifconfig sdr0 up\n  ./sdr-ad-hoc-up.sh sdr0 44 192.168.13.1\n  (Above command setup ad-hoc network at channel 44 with static IP assigned to sdr0 NIC)\n  iwconfig sdr0\n  ```\n- You should see output like:\n  ```\n  sdr0    IEEE 802.11  ESSID:\"sdr-ad-hoc\"  \n          Mode:Ad-Hoc  Frequency:5.22 GHz  Cell: 92:CA:14:27:1E:B0   \n          Tx-Power=20 dBm   \n          Retry short limit:7   RTS thr:off   Fragment thr:off\n          Encryption key:off\n          Power Management:off\n  ```\n  If you see \"Cell: Not-Associated\", please wait and run \"iwconfig sdr0\" again until a randomly generated Cell ID appears.\n\n- Connect another computer to the adhoc2 via Ethernet cable. The computer should have static IP 192.168.10.1. Open a terminal on the computer, and then in the terminal:\n  ```\n  ssh root@192.168.10.122\n  (password: openwifi)\n  service network-manager stop\n  cd openwifi\n  ./wgd.sh\n  ifconfig sdr0 up\n  ./sdr-ad-hoc-up.sh sdr0 44 192.168.13.2\n  iwconfig sdr0\n  ```\n- You should see output like:\n  ```\n  sdr0    IEEE 802.11  ESSID:\"sdr-ad-hoc\"  \n          Mode:Ad-Hoc  Frequency:5.22 GHz  Cell: 92:CA:14:27:1E:B0   \n          Tx-Power=20 dBm   \n          Retry short limit:7   RTS thr:off   Fragment thr:off\n          Encryption key:off\n          Power Management:off\n  ```\n  The \"Cell: 92:CA:14:27:1E:B0\" should be the same as adhoc1, because the later joined node should discover the Cell ID of the existing network and join/get it automatically. If not, please adjust the antenna/distance and re-run the commands.\n\n  Now the communication link should be already setup between the two ad-hoc nodes, and you can ping each other.\n"
  },
  {
    "path": "doc/app_notes/ap-client-two-sdr.md",
    "content": "<!--\nAuthor: Xianjun jiao\nSPDX-FileCopyrightText: 2019 UGent\nSPDX-License-Identifier: AGPL-3.0-or-later\n-->\n\n**NOTE** the terminal session mentioned in the following text can also be setup via USB-UART instead of Ethernet.\n\n**NOTE** adrv9361z7035 has ultra low TX power in 5GHz. Move **CLOSER** when you use that board in 5GHz!!!\n\n- Power on two SDR boards. Call one board \"AP board\" and the other \"client board\". On each board, the TX and RX antenna should vertical/orthogonal to each other as much as possible to gain a good TX/RX isolation.\n- Connect a computer to the AP board via Ethernet cable. The computer should have static IP 192.168.10.1. Open a terminal on the computer, and then in the terminal:\n  ```\n  ssh root@192.168.10.122\n  (password: openwifi)\n  cd openwifi\n  ./fosdem.sh\n  (It will create a WiFi AP by hostapd program with config file: hostapd-openwifi.conf)\n  (Wait for the script completed)\n  cat /proc/interrupts\n  (Execute the \"cat ...\" command for several times)\n  (You should see the number of \"sdr,tx_itrpt1\" grows, because it sends the \"openwifi\" beacon periodically)\n  ```\n- Connect another computer to the client board via Ethernet cable. The computer should have static IP 192.168.10.1. Open a terminal on the computer, and then in the terminal:\n  ```\n  ssh root@192.168.10.122\n  (password: openwifi)\n  service network-manager stop\n  cd openwifi\n  ./wgd.sh\n  (Wait for the script completed)\n  ifconfig sdr0 up\n  iwlist sdr0 scan\n  (The \"openwifi\" AP should be listed in the scanning results)\n  wpa_supplicant -i sdr0 -c wpa-openwifi.conf\n  (\"iwconfig sdr0 essid openwifi\" could also work. Less info compared to wpa_supplicant)\n  ```\n  If wpa-openwifi.conf is not on board, please create it with [this content](../../user_space/wpa-openwifi.conf).\n- Now the client is trying to associate with the AP. You should see like:\n  ```\n  root@analog:~/openwifi# wpa_supplicant -i sdr0 -c wpa-openwifi.conf \n  Successfully initialized wpa_supplicant\n  sdr0: CTRL-EVENT-SCAN-STARTED \n  sdr0: SME: Trying to authenticate with 66:55:44:33:22:8c (SSID='openwifi' freq=5220 MHz)\n  sdr0: Trying to associate with 66:55:44:33:22:8c (SSID='openwifi' freq=5220 MHz)\n  sdr0: Associated with 66:55:44:33:22:8c\n  sdr0: CTRL-EVENT-CONNECTED - Connection to 66:55:44:33:22:8c completed [id=0 id_str=]\n  ```\n  The AP board terminal should print like:\n  ```\n  ...\n  sdr0: STA 66:55:44:33:22:4c IEEE 802.11: authenticated\n  sdr0: STA 66:55:44:33:22:4c IEEE 802.11: associated (aid 1)\n  sdr0: AP-STA-CONNECTED 66:55:44:33:22:4c\n  sdr0: STA 66:55:44:33:22:4c RADIUS: starting accounting session 613E16DE-00000000\n  ```\n  If not, please adjust antenna/distance and re-run the commands on the client side.\n\n- After association is done, in another terminal of client (**DO NOT** terminate wpa_supplicant in the original client terminal!):\n  ```\n  dhclient sdr0\n  (Wait for it completed)\n  ifconfig sdr0\n  (Now you should see the IP address like 192.168.13.x allocated by AP)\n  ping 192.168.13.1\n  (Ping the AP)\n  ```\n  Now the communication link should be already setup between the AP and the client.\n"
  },
  {
    "path": "doc/app_notes/csi-architecture.jpg.license",
    "content": "# Author: Xianjun jiao\n\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n"
  },
  {
    "path": "doc/app_notes/csi-information-format.jpg.license",
    "content": "# Author: Xianjun jiao\n\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n"
  },
  {
    "path": "doc/app_notes/csi-screen-shot.jpg.license",
    "content": "# Author: Xianjun jiao\n\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n"
  },
  {
    "path": "doc/app_notes/csi.md",
    "content": "<!--\nAuthor: Xianjun jiao\nSPDX-FileCopyrightText: 2019 UGent\nSPDX-License-Identifier: AGPL-3.0-or-later\n-->\n\n\nWe extend the **CSI** (Channel State Information) to **CSI** (Chip State Information)!\n\n(This app note shows general CSI collection. To use self-Tx CSI in full duplex mode as **RADAR**, please refer to [WiFi CSI radar via self CSI capturing](radar-self-csi.md))\n\n## Quick start\n- Power on the SDR board.\n- Connect a computer to the SDR board via Ethernet cable. The computer should have static IP 192.168.10.1. Open a terminal on the computer, and then in the terminal:\n  ```\n  ssh root@192.168.10.122\n  (password: openwifi)\n  cd openwifi\n  ./wgd.sh\n  (Wait for the script completed)\n  ./monitor_ch.sh sdr0 11\n  (Monitor on channel 11. You can change 11 to other channel that is busy)\n  insmod side_ch.ko\n  ./side_ch_ctl g\n  ```\n  You should see on board outputs like:\n  ```\n  loop 64 side info count 61\n  loop 128 side info count 99\n  ...\n  ```\n  If the second number (61, 99, ...) is not zero and keeps increasing, that means the CSI (Chip State Information) is going to the computer smoothly.\n  \n- On your computer (NOT in ssh!), run:\n  ```\n  cd openwifi/user_space/side_ch_ctl_src\n  python3 side_info_display.py\n  ```\n  You might need to install beforehand: \"sudo apt install python3-numpy python3-matplotlib python3-tk\". Now you should see 3 figures showing run-time **frequency offset**, **channel state/response** and **constellation form equalizer**. Meanwhile the python script prints the **timestamp**.\n  ![](./csi-screen-shot.jpg)\n  \n  While running, all information is also stored into a file **side_info.txt**. A matlab script **test_side_info_file_display.m** is offered to help you do analysis on the Chip State Information offline.\n\n## Understand the CSI feature\n  The CSI information is extracted via the openwifi **side channel** infrastructure. This figure explains the related modules (also related source code file name) and how the information goes from the SDR board to the computer.\n  ![](./csi-architecture.jpg)\n\n  The CSI information format is shown in this figure.\n  ![](./csi-information-format.jpg)\n\n  For each element, the actual size is 64bit.\n  - timestamp: 64bit TSF timer value, which is the same timestamp value shown by other sniffer software, like tcpdump, wireshark or openwifi printing in dmesg.\n  - freq_offset: Only the 1st 16bit is used.\n  - csi (channel state/response) and equalizer: Only the first two 16bit are used for I/Q of channel response and equalizer output. The remaining two 16bit are reserved for future multi-antenna cases.\n  \n  The python and Matlab scripts are recommended for you to understand the CSI packet format precisely.\n\n## Config the capture condition and interval\n  The quick start guide will monitor all CSI information of all packets decoded by the WiFi ofdm receiver. To monitor only specific packets that match the specific conditions: FC (Frame Control), addr1 (target MAC address), addr2 (source MAC address), configuration command should be issued before executing \"**side_ch_ctl g**\". The configuration command is realized by feeding a different parameter to \"**side_ch_ctl**\". \n  \n  A quick example: Capture only CSI of those packets from the device with MAC address 56:5b:01:ec:e2:8f\n  ```\n  ./side_ch_ctl wh1h4001\n  ./side_ch_ctl wh7h01ece28f\n  (01ece28f are the last 32 bits of MAC address 56:5b:01:ec:e2:8f)\n  ./side_ch_ctl g\n  ```\n  The parameter string format is explained in detail:\n  ```\n  whXhY\n  ```\n  The X is the register index, and the Y is the value in hex format. The remaining \"w\", \"h\" and \"h\" should be kept untouched.\n  - To turn on conditional capture, X should be 1. For Y: bit11~bit0 should be 001(hex), bit12: on/off of FC match, bit13: on/off of addr1 match, bit14 : on/off of addr2 match. Examples:\n  ```\n  Turn on FC only match:\n  ./side_ch_ctl wh1h1001\n  (1001 is the value in hex format)\n  Turn on addr2 (source address) only match:\n  ./side_ch_ctl wh1h4001\n  \n  Turn on both FC and addr1 (target address) match:\n  ./side_ch_ctl wh1h3001\n  \n  Turn off conditional capture (all packets will be captured):\n  ./side_ch_ctl wh1h0001\n  ```\n  - To specify the condition matching target (when that type of match is turned on by above command):\n  ```\n  Specify the FC matching target:\n  ./side_ch_ctl wh5hY\n  (Y is the FC value in hex format)\n  Specify the addr1 (target address) matching target:\n  ./side_ch_ctl wh6hY\n  \n  Specify the addr2 (source address) matching target:\n  ./side_ch_ctl wh7hY\n  (Y is the MAC address in hex format. Only the last 32 bits are needed. Example: for 56:5b:01:ec:e2:8f, 01ece28f should be input.)\n  ```  \n  The command \"**side_ch_ctl g**\" will perform CSI capture every 100ms until you press ctrl+C. To use a different capture interval:\n  ```\n  side_ch_ctl gN\n  ```\n  The interval will become N*1ms\n\n## Config the num_eq\n  The num_eq (number of equalizer output) is configurable in case you don't need so many equalizer information. The valid value is 0~8. You should align the num_eq value at the side_ch.ko, side_info_display.py and test_side_info_file_display.m. \n  - When insert the kernel module, use:\n  ```\n  insmod side_ch.ko num_eq_init=3\n  ```\n  You can replace 3 by number 0~8. (8 is the default value. You don't need to specify it like in the Quick start section)\n  - When launch the python script, use:\n  ```\n  side_info_display.py 3\n  ```\n  - When use the Matlab script, please change the num_eq variable in the script to 3 (3 is just an example).\n\n## Compile the side channel driver and user space program\n  - side_ch.ko\n  ```\n  $OPENWIFI_DIR/driver/side_ch/make_driver.sh $OPENWIFI_DIR $XILINX_DIR ARCH_BIT\n(For Zynq 7000, ARCH_BIT should be 32, for Zynq MPSoC, ARCH_BIT should be 64)\n  ```\n  - side_ch_ctl (take user_space/side_ch_ctl_src/side_ch_ctl.c and compile it on board!)\n  ```\n  gcc -o side_ch_ctl side_ch_ctl.c\n  ```\n\n## Run the CSI together with modes other than monitor\n  The openwifi CSI feature could run with not only monitor mode but also other modes, such as AP-Client or ad-hoc mode. After the communication functionality is fully up in those modes, you can start CSI feature from \"**insmod side_ch.ko**\" and \"**./side_ch_ctl g**\" on board as described in the previous sections to extract CSI to your computer.\n\n## Map the CSI information to the WiFi packet\n  Please check this discussion: https://github.com/open-sdr/openwifi/discussions/344\n  \n  If you want to relate the CSI information to the WiFi packet, you need to capture WiFi packets (tcpdump/wireshark/etc) while capturing CSI. Then you can match the timestamp (TSF timer value) between WiFi packet and CSI information, because this is the unique same identity of a Wifi packet and related CSI information.\n  \n  Please learn the python and Matlab script to extract CSI information per packet according to your requirement.\n"
  },
  {
    "path": "doc/app_notes/csi_fuzzer.md",
    "content": "<!--\nAuthor: Xianjun jiao\nSPDX-FileCopyrightText: 2021 UGent\nSPDX-License-Identifier: AGPL-3.0-or-later\n-->\n\n- [ACM WiSec 2021. Openwifi CSI fuzzer for authorized sensing and covert channels](https://dl.acm.org/doi/pdf/10.1145/3448300.3468255)\n- [Privacy Protection in WiFi Sensing via CSI Fuzzing](https://ieeexplore.ieee.org/abstract/document/10818006)\n\nCSI (Channel State Information) of WiFi systems is available in some WiFi chips and can be used for sensing the environment (keystrokes, people, object) passively and secretly.\n\n## Concept\n\nHow could a CSI fuzzer stop unauthorized sensing?\n\n![](./csi-fuzzer-system-before-vs-now.png)\n\nCSI fuzzer implementation principle.\n\n![](./csi-fuzzer-principle.png)\n\n## Demo instructions\n\nThanks to the full-duplex capability and CSI extraction feature of openwifi, you can monitor the artificial channel response via [side channel](./csi.md) by Tx-Rx over the air coupling without affecting the normal operation/traffic of openwifi. Before fuzzing the CSI, please follow [WiFi CSI radar via self CSI capturing](radar-self-csi.md) app note to setup normal self CSI monitoring.\n\nThen, start another ssh session to the openwifi board:\n```\nssh root@192.168.10.122\n(password: openwifi)\n\ncd openwifi\n\n./csi_fuzzer_scan.sh 1\n(CSI fuzzer applies possible artificial CSI by scanning all values)\n(csi_fuzzer.sh is called. Please read both scripts to understand these commands)\n```\n\nNow you should see that CSI keeps changing like in this [video](https://youtu.be/aOPYwT77Qdw).\n\n# Further explanation on parameters\n\nCSI fuzzer in openwifi system architecture and related commands.\n\n![](./csi-fuzzer-implementation.png)\n\n# Example fuzzed CSI\n\nCSI self-monitoring before fuzzing.\n\n![](./csi-fuzzer-beacon-ant-back-0.jpg)\n\nCSI self-monitoring after  fuzzing command: `./csi_fuzzer.sh 1 45 0 13`\n\n![](./csi-fuzzer-beacon-ant-back-1-45-0-13.jpg)\n\n`csi_fuzzer_scan.sh` can scan the c1 and c2 in different styles/modes by calling `csi_fuzzer.sh`.\n"
  },
  {
    "path": "doc/app_notes/driver_stat.md",
    "content": "Comprehensive statistics are offered at the driver level via the [Linux sysfs](https://en.wikipedia.org/wiki/Sysfs#:~:text=sysfs%20is%20a%20pseudo%20file,user%20space%20through%20virtual%20files.).\n\n[[Quick start](#Quick-start)]\n[[Sysfs explanation](#Sysfs-explanation)]\n[[Statistics variable file meaning](#Statistics-variable-file-meaning)]\n\nAll operations should be done on board in openwifi directory, not in host PC.\n\n## Quick start\n\nEnable the driver level statistics (after openwifi up and running)\n```\n./stat_enable.sh\n```\nShow the statistics\n```\n./tx_stat_show.sh\n./tx_prio_queue_show.sh\n./rx_stat_show.sh\n./rx_gain_show.sh\n```\nClear the stattistics\n```\n./tx_stat_show.sh clear\n./tx_prio_queue_show.sh clear\n./rx_stat_show.sh clear\n```\nLet rx_stat_show.sh calculate PER (Packet Error Rate) by giving the number of packet sent at the peer (30000 packets for example):\n```\n./rx_stat_show.sh 30000\n```\nTo only show the statistics for the link with a specific peer node\n```\n./set_rx_target_sender_mac_addr.sh c83caf93\n(If the peer node MAC address is 00:80:c8:3c:af:93)\n```\nTo show the statistics of all (not filtered by the peer node MAC address)\n```\n./set_rx_target_sender_mac_addr.sh 0\n```\nTo show the peer node MAC address for statistics\n```\n./set_rx_target_sender_mac_addr.sh\n```\nTo see the statistics of ACK packet, run this before above scripts\n```\n./set_rx_monitor_all.sh\n```\nDisable the statistics of ACK packet, run this before above scripts\n```\n./set_rx_monitor_all.sh 0\n```\nDisable the driver level statistics (after openwifi up and running)\n```\n./stat_enable.sh 0\n```\n\n## Sysfs explanation\n\nFor user, as you can check in those scripts above, the sysfs is a set of files that can be operated in the command line for communicating with kernel module. You can find these files on zcu102 board at\n```\n/sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\n```\nOn othe boards at\n```\n/sys/devices/soc0/fpga-axi@0/fpga-axi@0:sdr\n```\n\n## Statistics variable file meaning\n\nThese statistics names are the same as the file names (in those scripts) and variable names in the sdr.c. Do search these names in sdr.c to understand exact meaning of these statistics.\n\n- tx_stat_show.sh\n\n  name|meaning\n  ------------|----------------------\n  tx_data_pkt_need_ack_num_total     | number of tx data packet reported in openwifi_tx_interrupt() (both fail and succeed)\n  tx_data_pkt_need_ack_num_total_fail| number of tx data packet reported in openwifi_tx_interrupt() (fail -- no ACK received)\n  tx_data_pkt_need_ack_num_retx      | number of tx data packet reported in openwifi_tx_interrupt() at different number of retransmission (both fail and succeed)\n  tx_data_pkt_need_ack_num_retx_fail | number of tx data packet reported in openwifi_tx_interrupt() at different number of retransmission (fail -- no ACK received)\n  tx_data_pkt_mcs_realtime           | MCS (10*Mbps) of tx data packet reported in openwifi_tx_interrupt() (both fail and succeed)\n  tx_data_pkt_fail_mcs_realtime      | MCS (10*Mbps) of tx data packet reported in openwifi_tx_interrupt() (fail -- no ACK received)\n  tx_mgmt_pkt_need_ack_num_total     | number of tx management packet reported in openwifi_tx_interrupt() (both fail and succeed)\n  tx_mgmt_pkt_need_ack_num_total_fail| number of tx management packet reported in openwifi_tx_interrupt() (fail -- no ACK received)\n  tx_mgmt_pkt_need_ack_num_retx      | number of tx management packet reported in openwifi_tx_interrupt() at different number of retransmission (both fail and succeed)\n  tx_mgmt_pkt_need_ack_num_retx_fail | number of tx management packet reported in openwifi_tx_interrupt() at different number of retransmission (fail -- no ACK received)\n  tx_mgmt_pkt_mcs_realtime           | MCS (10*Mbps) of tx management packet reported in openwifi_tx_interrupt() (both fail and succeed)\n  tx_mgmt_pkt_fail_mcs_realtime      | MCS (10*Mbps) of tx management packet reported in openwifi_tx_interrupt() (fail -- no ACK received)\n\n- tx_prio_queue_show.sh\n\n  tx_prio_queue_show.sh will show 4 rows. Each row is corresponding one Linux-prio and one FPGA queue. Each row has 12 elements. Elements' name will not be displayed in the command line.\n\n  Element name|meaning\n  ------------|----------------------\n  tx_prio_num            | number of tx packet from Linux prio N to openwifi_tx()\n  tx_prio_interrupt_num  | number of tx packet from Linux prio N recorded in openwifi_tx_interrupt()\n  tx_prio_stop0_fake_num | number of Linux prio N stopped attempt in the 1st place of openwfii_tx(), fake alarm\n  tx_prio_stop0_real_num | number of Linux prio N stopped attempt in the 1st place of openwfii_tx(), real stop\n  tx_prio_stop1_num      | number of Linux prio N stopped in the 2nd place of openwfii_tx()\n  tx_prio_wakeup_num     | number of Linux prio N waked up in openwifi_tx_interrupt()\n  tx_queue_num           | number of tx packet for FPGA queue N to openwifi_tx()\n  tx_queue_interrupt_num | number of tx packet for FPGA queue N recorded in openwifi_tx_interrupt()\n  tx_queue_stop0_fake_num| number of FPGA queue N stopped attempt in the 1st place of openwfii_tx(), fake alarm\n  tx_queue_stop0_real_num| number of FPGA queue N stopped attempt in the 1st place of openwfii_tx(), real stop\n  tx_queue_stop1_num     | number of FPGA queue N stopped in the 2nd place of openwfii_tx()\n  tx_queue_wakeup_num    | number of FPGA queue N waked up in openwifi_tx_interrupt()\n\n- rx_stat_show.sh\n\n  name|meaning\n  ------------|----------------------\n  rx_data_pkt_num_total               | number of rx data packet with both FCS ok and failed\n  rx_data_pkt_num_fail                | number of rx data packet with FCS failed\n  rx_mgmt_pkt_num_total               | number of rx management packet with both FCS ok and failed\n  rx_mgmt_pkt_num_fail                | number of rx management packet with FCS failed\n  rx_ack_pkt_num_total                | number of rx ACK packet with both FCS ok and failed\n  rx_ack_pkt_num_fail                 | number of rx ACK packet with FCS failed\n  rx_data_pkt_mcs_realtime            | MCS (10*Mbps) of rx data packet with both FCS ok and failed\n  rx_data_pkt_fail_mcs_realtime       | MCS (10*Mbps) of rx data packet with FCS failed\n  rx_mgmt_pkt_mcs_realtime            | MCS (10*Mbps) of rx management packet with both FCS ok and failed\n  rx_mgmt_pkt_fail_mcs_realtime       | MCS (10*Mbps) of rx management packet with FCS failed\n  rx_ack_pkt_mcs_realtime             | MCS (10*Mbps) of rx ACK packet with both FCS ok and failed\n  rx_data_ok_agc_gain_value_realtime  | agc gain value of rx data packet with FCS ok\n  rx_data_fail_agc_gain_value_realtime| agc gain value of rx data packet with FCS failed\n  rx_mgmt_ok_agc_gain_value_realtime  | agc gain value of rx management packet with FCS ok\n  rx_mgmt_fail_agc_gain_value_realtime| agc gain value of rx management packet with FCS failed\n  rx_ack_ok_agc_gain_value_realtime   | agc gain value of rx ACK packet with FCS ok\n\n- rx_gain_show.sh\n\n  name|meaning\n  ------------|----------------------\n  rx_data_ok_agc_gain_value_realtime  | agc gain value of rx data packet with FCS ok\n  rx_data_fail_agc_gain_value_realtime| agc gain value of rx data packet with FCS failed\n  rx_mgmt_ok_agc_gain_value_realtime  | agc gain value of rx management packet with FCS ok\n  rx_mgmt_fail_agc_gain_value_realtime| agc gain value of rx management packet with FCS failed\n  rx_ack_ok_agc_gain_value_realtime   | agc gain value of rx ACK packet with FCS ok\n  \n  Note: gain value here is always 14 dB higher than set_rx_gain_auto.sh/set_rx_gain_manual.sh at 5220MHz. 5dB higher at 2.4GHz.\n"
  },
  {
    "path": "doc/app_notes/drv_fpga_dynamic_loading.md",
    "content": "The **wgd.sh** (running on board) supports reloading driver and/or FPGA image dynamically without rebooting/power-cycle. It can work in a \nflexible way. \n\nThe purpose of this feature is to help you easily reload driver and FPGA built from your branch/version/variant/modification, and switch/run different driver and FPGA of different branch/version/variant/modification without rebooting. To enjoy this feature, always ensure your onboard openwifi/files are the latest files in [user_space](../../user_space)).\n\n- [[Reload driver only](#Reload-driver-only)]\n- [[Reload driver and FPGA](#Reload-driver-and-FPGA)]\n- [[Reload driver and FPGA in target directory](#Reload-driver-and-FPGA-in-target-directory)]\n- [[Reload driver and FPGA from a single package file](#Reload-driver-and-FPGA-from-a-single-package-file)] -- **RECOMMENDED!**\n- [[Suggested practice to generate driver FPGA variants](#Suggested-practice-to-generate-driver-FPGA-variants)]\n- [[Detailed full usage info](#Detailed-full-usage-info)]\n\nNote: Make sure you have compiled driver before. Check [Update Driver](../../README.md#update-driver).\n\n## Reload driver only\nThis is the original way. To let **wgd.sh** only loads the driver without touching FPGA, please ensure FPGA image file **system_top.bit.bin** is **NOT** \npresent in the directory. If wgd.sh can not find the FPGA image, it will skip reloading it.\n\n## Reload driver and FPGA\n- Generate the reloadable FPGA file **system_top.bit.bin**. In the Linux host computer:\n  ```\n  cd openwifi/user_space\n  ./drv_and_fpga_package_gen.sh $OPENWIFI_HW_IMG_DIR $XILINX_DIR $BOARD_NAME\n  ```\n  Then **system_top.bit.bin** will be generated in openwifi/user_space.\n\n- Put **system_top.bit.bin** on board in the same directory as wgd.sh and other driver files (.ko)\n- Run **wgd.sh** on board as usual\n\n## Reload driver and FPGA in target directory\nPut **system_top.bit.bin** on board together with other driver files (.ko) in a directory ($TARGET_DIR), then run on board:\n```\n./wgd.sh $TARGET_DIR\n```\nIn this way, different versions/variants of driver/FPGA can be put in different directories. Then **wgd.sh** can be used to switch \nbetween them without rebooting/power-cycle.\n\n## Reload driver and FPGA from a single package file\nThe openwifi/user_space/**drv_and_fpga_package_gen.sh** also generates a single package file **drv_and_fpga.tar.gz**, which includes driver files (.ko), \nFPGA image and many other source files with rich infos that are related.\n\nYou can switch to your own branch/version/variant, build the single package file via **drv_and_fpga_package_gen.sh**, rename it with a more meaningful name (such as add version or variant info as postfix), put the renamed **drv_and_fpga_MEANINGFUL_POSTFIX.tar.gz** on board in the same directory as **wgd.sh**, and let **wgd.sh** load it:\n```\n./wgd.sh ./drv_and_fpga_MEANINGFUL_POSTFIX.tar.gz\n```\nIn this way, different version/variants of driver/FPGA can be switched by **wgd.sh** without rebooting/power-cycle.\n\n## Suggested practice to generate driver FPGA variants\nThere are several ways to generate variants of the single driver-FPGA package file. For example:\n\n- Switch/create another branch for openwifi and openwifi-hw, work/modify there, then generate the single package file via **drv_and_fpga_package_gen.sh**. This package is the branch specific, so renaming the package name to a more meaningful one would be good practice.\n- In the same branch, set different arguments (finally macro definitions in .h and .v files) via conditional compiling to enable/disable different driver and FPGA code blocks/functionalities, then generate the single package file via **drv_and_fpga_package_gen.sh**. Rename the package to remind you which conditions are ON/OFF.\n    - Check \"Conditional compile by verilog macro\" in openwifi-hw README for FPGA design\n    - Input more arguments (max 5) to driver building script \"make_all.sh $XILINX_DIR ARCH_BIT\". Those arguments will be converted to \"#define argument\" in pre_def.h for driver conditional compiling. **Attention:** **drv_and_fpga_package_gen.sh** currently only call **make_all.sh** without extra arguments. If you have conditional compiling arguments, do not forget to put them into **drv_and_fpga_package_gen.sh** as extra arguments of **make_all.sh**.\n\n## Detailed full usage info\nRun the \"./wgd.sh -h\" on board or open wgd.sh to see full usage info:\n```\nusage:\n  Script for load (or download+load) different driver and FPGA img without rebooting\n  no  argument: Load .ko driver files and FPGA img (if system_top.bit.bin exist) in current dir with test_mode=0.\n  1st argument: If it is a NUMBER, it will be assigned to test_mode. Then load everything from current dir.\n  1st argument: If it is a string called \"remote\", it will download driver/FPGA and load everything.\n  - 2nd argument (if exist) is the target directory name for downloading and reloading\n  - 3rd argument (if exist) is the value for test_mode\n  1st argument: neither NUMBER nor \"remote\" nor a .tar.gz file, it is regarded as a directory and load everything from it.\n  - 2nd argument (if exist) is the value for test_mode\n  1st argument: a .tar.gz file, it will be unpacked then load from that unpacked directory\n  - 2nd argument (if exist) is the value for test_mode\n```\n"
  },
  {
    "path": "doc/app_notes/frequent_trick.md",
    "content": "Some usual/frequent control trick over the openwifi FPGA. You need to do these controls on board in the openwifi directory.\n\n[[CCA LBT threshold and disable](#CCA-LBT-threshold-and-disable)]\n[[Retransmission and ACK control](#Retransmission-and-ACK-control)]\n[[NAV DIFS EIFS CW disable and enable](#NAV-DIFS-EIFS-CW-disable-and-enable)]\n[[CW max and min config](#CW-max-and-min-config)]\n\n[[Rx gain config](#Rx-gain-config)]\n[[Tx power config](#Tx-power-config)]\n[[Tx Lo and port config](#Tx-Lo-and-port-config)]\n[[Antenna selection](#Antenna-selection)]\n[[Restrict the frequency](#Restrict-the-frequency)]\n[[Receiver sensitivity control](#Receiver-sensitivity-control)]\n\n[[Tx rate config](#Tx-rate-config)]\n[[Arbitrary Tx IQ sample](#Arbitrary-Tx-IQ-sample)]\n\n## CCA LBT threshold and disable\n\nIn normal operation, different threshold is set to FPGA according to the different calibration of different frequency/channel by driver automatically. Show the current LBT threshold in FPGA:\n```\n./set_lbt_th.sh\ndmesg\n```\nIt shows: \"sdr,sdr FPGA LBT threshold 166(-62dBm). The last_auto_fpga_lbt_th 166(-62dBm). rssi corr 145\". Check rssi_half_db_to_rssi_dbm()/rssi_dbm_to_rssi_half_db() in sdr.c to see the relation to rssi dBm.\n\nOverride a new threshold -NNdBm to FPGA, for example -70dBm:\n```\n./set_lbt_th.sh 70\ndmesg\n```\nAbove will disable the automatic CCA threshold setting from the openwifi driver.\n\nRecover the driver automatic control on the threshold:\n```\n./set_lbt_th.sh 0\ndmesg\n```\nDisable the CCA by setting a very strong level as threshold, for example -1dBm:\n```\n./set_lbt_th.sh 1\ndmesg\n```\nAfter above command, the CCA engine will always believe the channel is idle, because the rx signal strength not likely could exceed -1dBm.\n  \n## Retransmission and ACK control\n\nThe best way of override the maximum number of re-transmission for a Tx packet is doing it in the driver openwifi_tx() function. \n```\nretry_limit_hw_value = ( retry_limit_raw==0?0:((retry_limit_raw - 1)&0xF) );\n```\nOverride retry_limit_hw_value to 0 to disable re-transmission. Override it to 1 means that let FPGA do maximum 1 time re-transmission.\n\nThe FPGA also has a register to override the re-transmission and ACK behavior. Check the current register value.\n```\n./sdrctl dev sdr0 get reg xpu 11\n```\nWhen operate this register, make sure you only change the relevant bits and leave other bits untouched, because other bits have other purposes. Also check the xpu register 11 in the [project document](../README.md)\n\nTo override the maximum number of re-transmission, set bit3 to 1, and set the value (0 ~ 7) to bit2 ~ 0. Example, override the maximum number of re-transmission to 1\n```\n./sdrctl dev sdr0 set reg xpu 11 9\n```\n9 in binary form is 01001.\n\nTo disable the ACK TX after receiving a packet, set bit4 to 1:\n```\n./sdrctl dev sdr0 set reg xpu 11 16\n```\nIf we want to preserve the above re-transmission overriding setting while disable ACK Tx:\n```\n./sdrctl dev sdr0 set reg xpu 11 25\n```\n25 in binary form is 11001. the 1001 of bit3 to 1 is untouched.\n\nDisabling ACK TX might be useful for monitor mode and packet injection.\n\nTo disable the ACK RX after sending a packet, set bit5 to 1:\n```\n./sdrctl dev sdr0 set reg xpu 11 32\n```\n\nTo disable both ACK Tx and Rx:\n```\n./sdrctl dev sdr0 set reg xpu 11 48\n```\n  \n## NAV DIFS EIFS CW disable and enable\n\nTo check the current NAV/DIFS/EIFS/CW disable status, just run\n```\n./nav_disable.sh\n./difs_disable.sh\n./eifs_disable.sh\n./cw_disable.sh\n```\nIf NAV is disabled, the openwifi will always assume the NAV (Network Allocation Vector) is already counting down to 0. If DIFS/EIFS is disabled, when the CSMA engine needs to wait for DIFS/EIFS, it won't wait anymore. If CW is disabled, the contention window is fixed to 0, and there won't be any number of slots for random backoff procedure. To disable them, just input 1 as the script argument.\n```\n./nav_disable.sh 1\n./difs_disable.sh 1\n./eifs_disable.sh 1\n./cw_disable.sh 1\n```\nTo enable them, just input 0 as the script argument.\n```\n./nav_disable.sh 0\n./difs_disable.sh 0\n./eifs_disable.sh 0\n./cw_disable.sh 0\n```\n\n## CW max and min config\n\nWhen the openwifi NIC bring up (as AP/Client/ad-hoc/etc), Linux will configure the CW (Contention Window) max and min value for FPGA queue 3 ~ 0 via openwifi_conf_tx() in the openwifi driver. You can check the current CW configuration in FPGA (set by Linux).\n```\n./cw_max_min_cfg.sh\n```\nIt will show sth like\n```\nFPGA  cw max min for q3 to q0: 1023 15; 63 15; 15 7; 7 3\nFPGA  cw max min for q3 to q0: a4644332\n```\nThe CW max and min for q3 ~ 0  are a4, 64, 43, 32 (in hex). Example explanation for q3: in hex the configuration is a4, which means 10 and 4 in the logarithmic domain, (2^10)-1=1023 and (2^4)-1=15 in the linear domain.\n\nTo override the CW max and min for queue 3 ~ 0, for example 2047 31; 63 31; 15 7; 7 3, just map it to a hex string b5654332 for queue 3 ~ 0 and give it as the script argument:\n```\n./cw_max_min_cfg.sh b5654332\n```\nIt will show sth like\n```\nFPGA  cw max min for q3 to q0: 2047 31; 63 31; 15 7; 7 3\nFPGA  cw max min for q3 to q0: b5654332\nSYSFS cw max min for q3 to q0: 2047 31; 63 31; 15 7; 7 3\nSYSFS cw max min for q3 to q0: b5654332\n```\nTo give the control back to Linux\n```\n./cw_max_min_cfg.sh 0\n```\nBe careful that above command won't bring the Linux CW max min setting back to FPGA automatically, because Linux normally only call the setting function openwifi_conf_tx() for 1 time when the NIC is started. So either you write down the Linux setting by checking it at the beginning, and set it back via cw_max_min_cfg.sh before giving it argument 0, or re-load the NIC/driver to trigger the Linux setting action for the NIC.\n  \n## Rx gain config\n\nIn normal operation, you don't need to do Rx gain control manually, because it is controled by the AD9361 AGC function. For optimization/experiment purpose, you might want to use the manual rx gain control, you can run\n```\n./set_rx_gain_manual.sh 30\n```\nAbove command will turn the automatic gain control mode to manual gain control mode, and set 30dB to the Rx gain module.\n\nBring it back to the automatic gain control mode\n```\n./set_rx_gain_auto.sh\n```\nTo find out a good reference about a manual Rx gain setting for the current link/peer, you can set it to automatic mode and then run\n```\n./stat_enable.sh\n```\nonce and then\n```\n./rx_gain_show.sh\n```\nfor multiple times to check the actual AGC gain vlaue for received packet as explained in this [Access counter/statistics in driver](driver_stat.md). Then you can set the AGC gain value as argument to the **set_rx_gain_manual.sh** with the corret **offset**! For example, if **rx_gain_show.sh** reports a AGC gain value 34 for many successfully received data packets, and you want to use it as a manual gain setting, you need to set\n```\n./set_rx_gain_manual.sh 20\n```\nif the current working channel is 5220MHz (34 - 14dB offset = 20). You need to set\n```\n./set_rx_gain_manual.sh 29\n```\nif the current working channel is in 2.4GHz  (34 - 5dB offset = 29). \n  \n## Tx power config\n```\n./sdrctl dev sdr0 set reg rf 0 20000\n```\nAbove command will set Tx power attenuation to 20dB (20*1000). By default it is 0dB.\n\nIf you want an initial attenuation 20dB while loading and bringing up the openwifi NIC, please use the **init_tx_att** argument for the sdr.ko.\n```\ninsmod sdr.ko init_tx_att=20000\n```\nYou can change above driver loading action at the end of **wgd.sh**.\n\nThe initial Tx attenuation might be useful when you connect two SDR boards directly by cable. Even though, you shouldn't not connect them during the setup phase (bring up the AP or client), because the initialization/tuning of AD9361 might generate big Tx power and kill the other AD9361's Rx. Only connect two SDR boards by cable after both sides have been setup and the attenuation setting takes effect.\n\nTo increase the Tx power, you can consider add external PA like [this](https://github.com/open-sdr/openwifi/issues/53#issuecomment-767621478). Or increase the value of register 13 of tx_intf (check [README](../README.md)).\n\nRead the register value:\n```\n./sdrctl dev sdr0 get reg tx_intf 13\n```\n\nSet the register value to N (a number larger than the value read back above):\n```\n./sdrctl dev sdr0 set reg tx_intf 13 N\n```\nBigger value in that register could hurt the Tx EVM and long packet signal. You need to fine tune it for your case.\n\n## Tx Lo and port config\n\nIn normal operation, the Tx Lo and RF port are controled by FPGA automatically during signal Tx. To check the current Tx Lo and RF port switch status\n```\n./set_tx_port.sh\n./set_tx_lo.sh\n```\nGive argument **1** to above scripts to turn them **ON**, **0** for **OFF**.\n\nTo turn off automatic Tx Lo control from FPGA and leave Tx Lo always ON:\n```\n./sdrctl dev sdr0 set reg xpu 13 1\n```\n  \n## Antenna selection\n  \nBy default, the 1st Tx and Rx antennas are used (tx0 and rx0). You can change the tx antenna to tx1 by\n```\n./sdrctl dev sdr0 set reg drv_tx 4 1\n```\nChange the tx antenna back to tx0 by\n```\n./sdrctl dev sdr0 set reg drv_tx 4 0\n```\nChange the rx antenna to rx1 and rx0 by\n```\n./sdrctl dev sdr0 set reg drv_rx 4 1\n./sdrctl dev sdr0 set reg drv_rx 4 0\n```\n\n## Restrict the frequency\n\nSince the AD9361 frequency tuning could generate big unwanted Tx noise, and it could damage the other AD9361 Rx during the test via cable, a restricted frequency can be set to avoid the possible frequency tuning (such as the background scan of Wifi). For example, you want the AD9361 works only in 5220Mhz:\n```\n./set_restrict_freq.sh 5220\n```\nAbove command will fix the AD9361 in 5220MHz and let driver ignore frequency tuning request other than 5220MHz. The restriction can be removed by:\n```\n./set_restrict_freq.sh 0\n```\nTo let openwifi work at arbitrary frequency, please check [Let openwifi work at arbitrary frequency](../README.md#let-openwifi-work-at-arbitrary-frequency)\n\n## Receiver sensitivity control\n\nSometimes too good sensitivity could be a bad thing. WiFi receiver could be \"attracted\" by many weak signal/packet in the background, and has less \"attention\" to its real communication target (client/AP). Openwifi has offered a way to make the receiver less sensitive by setting a threshold. When the received signal is lower than this threshold, the receiver will not try to search the WiFi short preamble, i.e. ignore it. For example, if you want to set -70dBm as the threshold, use:\n```\n./sdrctl dev sdr0 set reg drv_rx 0 70\n```\n\n## Tx rate config\n  \nBy default, the Linux rate adaptation algorithm **minstrel_ht** set the packet rate/MCS automatically via openwifi_tx() function.\n```\nrate_hw_value = ieee80211_get_tx_rate(dev, info)->hw_value;\n```\nTo override the Linux automatic control for non-ht packet\n```\n./sdrctl dev sdr0 set reg drv_tx 0 N\n```\nValue N: 0 for Linux auto control; 4 ~ 11 for 6M, 9M, 12M, 18M, 24M, 36M, 48M, 54M.\n\nTo override the Linux automatic control for ht packet\n```\n./sdrctl dev sdr0 set reg drv_tx 1 N\n```\nValue N: 0 for Linux auto control; 4 ~ 11 for 6.5M, 13M, 19.5M, 26M, 39M, 52M, 58.5M, 65M. By default, the normal GI is used. To use the short GI, you need to add 16 to the target value N.\n  \n## Arbitrary Tx IQ sample\n  \nArbitrary IQ sample can be written to tx_intf and sent for test purposes. Currently maximum 512 samples, which is decided by the FIFO size in tx_iq_intf.v.\n\nTo verify this feature, firstly bring up the sdr0 NIC and put it into non-Tx mode, such as monitor mode. Then setup IQ capture in loopback mode, for example FPGA internal. (Check IQ capture App note for more details)\n```\ninsmod side_ch.ko iq_len_init=8187\n# Make sure to set the Tx local oscillator always on (as XPU is not aware of the transmission)\n./sdrctl dev sdr0 set reg xpu 13 1\n# Set 100 to register 11. It means the pre trigger length is 100, so we mainly capture IQ after trigger condition is met\n./side_ch_ctl wh11d100\n# Set 3 to register 8 -- set trigger condition to tx_intf_iq0_non_zero in tx_intf\n./side_ch_ctl wh8d3\n# Set the loopback mode to FPGA internal\n./side_ch_ctl wh5h4\n./side_ch_ctl g0\n```\n\nRun `python3 iq_capture.py 8187` on the host PC to wait for IQ capture by FPGA. After FPGA hits the IQ capture trigger condition, this host PC Python script will display and save the captured IQ.\n\nOpen another ssh session to the board. Make sure you have an arbitrary_iq_gen directory, tx_intf_iq_data_to_sysfs.sh and tx_intf_iq_send.sh (from user_space directory in the host PC) on board. Then run:\n```\n# Send the example IQ data to driver sysfs, and read back for check\n./tx_intf_iq_data_to_sysfs.sh\n# Write the IQ data from driver to FPGA, and send once\n./tx_intf_iq_send.sh\n```\n\nAbove scripts will send one time IQ. So you should see the captured IQ plot pop up. You can further check/process iq.txt in Matlab by `test_iq_file_display.m`.\n\nThe related tx_intf registers and tx_iq_intf ports\ntx_intf register|tx_iq_intf port|explanation\n----------------|---------------|-----------\nslv_reg7 bit0   |tx_arbitrary_iq_mode| 0:Normal operation; 1:Arbitrary IQ mode\nslv_reg7 bit1   |tx_arbitrary_iq_tx_trigger| jumping from 0 to 1 will trigger one time Tx of IQ in the tx_iq_intf FIFO\nslv_reg1 bit31~0|tx_arbitrary_iq_in|The driver writes IQ (32bit=I+Q) via this port one by one into the FIFO\n\nThe script `tx_intf_iq_send.sh` will trigger driver operations via `tx_intf_iq_ctl_store` function in `sysfs_intf.c`:\n- Switch to arbitrary IQ mode via slv_reg7 bit0\n- Write IQ data one by one to the tx_intf FIFO via slv_reg1\n- Trigger one time Tx of IQ data via slv_reg7 bit1\n"
  },
  {
    "path": "doc/app_notes/guard-interval.png.license",
    "content": "# Author: Michael Mehari\n\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n"
  },
  {
    "path": "doc/app_notes/hls.md",
    "content": "<!--\nAuthor: Thijs Havinga\nSPDX-FileCopyrightText: 2019 UGent\nSPDX-License-Identifier: AGPL-3.0-or-later\n-->\n\nFCCM2023 Poster: [Thijs Havinga, et al. Accelerating FPGA-Based Wi-Fi Transceiver Design and Prototyping by High-Level Synthesis](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/Thijs-FCCM2023-poster.jpg)\n\n[Longer/detailed info about the poster](https://arxiv.org/abs/2305.13351)\n\nIn order to speed up or ease FPGA development, it is possible to use High-Level Synthesis (HLS) for creating core baseband processing modules of openwifi. We have already programmed the receiver modules channel estimation and equalization in C++ and converted to Verilog using Vitis HLS. In order to use openwifi with these HLS modules, follow the [build instructions](#build-instructions).\nIn order to modify these modules within Vitis HLS, follow [the instructions below](#modify-the-code-using-vitis-hls). \n\n## Build instructions\n\nFollow the [Build FPGA](https://github.com/open-sdr/openwifi-hw#build-fpga) instructions till before generating ip_repo. In order to switch to the HLS-version of openofdm_rx, use the following commands:\n\n```\ncd ip/openofdm_rx\ngit checkout dot11zynq_hls\n```\n\nNow continue with the instructions. Before generating the bitstream, update the openofdm_rx IP by making sure it is selected under \"IP Status\" and click \"Upgrade Selected\". Afterwards, continue with the instructions to generate the bitstream.\n\n## Modify the code using Vitis HLS\nWhen in the `openwifi-hw` folder, make sure to run:\n```\n./get_ip_openofdm_rx.sh\ncd ip/openofdm_rx\ngit checkout dot11zynq_hls\n```\nThen start Vitis HLS and create a new project. Import either all source files (except those ending on '_test.cpp') in the [ch_gain_cal](https://github.com/open-sdr/openofdm/tree/dot11zynq_hls/hls/ch_gain_cal) or [equalizer](https://github.com/open-sdr/openofdm/tree/dot11zynq_hls/hls/equalizer) folder to modify the channel estimation or equalizer module, respectively. Choose either 'equalizer' or 'ch_gain_cal' as top-level module. Next, select `equalizer_test.cpp` or `ch_gain_cal_test.cpp` as testbench file. In 'Part selection', select the right part corresponding to your board. \n\nAfter modifying the code and making sure C simulation and cosimulation is running fine, select 'Export RTL', which will generate a ZIP file with a folder `hdl/verilog` containing the generated Verilog files. Replace the current folder `openwifi-hw/ip/openofdm_rx/hls/equalizer/hdl/verilog/` (or `.../ch_gain_cal/hdl/verilog`) with this folder and change the `openofdm_rx.tcl` file to include the newly generated Verilog files. See [here](https://github.com/open-sdr/openofdm/blob/dot11zynq_hls/openofdm_rx.tcl#L268) for an example. If you modified the top-level function arguments, you will need to interface them accordingly in [dot11.v](https://github.com/open-sdr/openofdm/blob/dot11zynq_hls/verilog/dot11.v).\n\nNow follow the [Build FPGA](https://github.com/open-sdr/openwifi-hw#build-fpga) instructions, starting at the step \"Generate ip_repo for the top level FPGA project\". It will then use the modified .tcl file to include the correct files for your modified HLS module and build the FPGA using it.\n\nA similar approach can be followed to create other HLS modules, where you would need to execute these steps in the folder of the IP to be modified and integrate the modules in the corresponding top-level Verilog file.\n"
  },
  {
    "path": "doc/app_notes/ieee80211n.md",
    "content": "<!--\nAuthor: Michael Mehari\nSPDX-FileCopyrightText: 2019 UGent\nSPDX-License-Identifier: AGPL-3.0-or-later\n-->\n\n## IEEE 802.11n (Wi-Fi 4)\n\nThe 4th generation of Wi-Fi (i.e. 802.11n-2009) is a generation leap over its predecessor Wi-Fi 3 (i.e. 802.11g-2003). It was coined as high throughput (HT) since it improves both the physical layer and the MAC layer.\n\n### PHY layer improvements\nAt the physical layer, 5 major improvements were amended on top of Wi-Fi 3 and this has increased the throughput from 54Mbps to 600Mbps.\n\n#### More subcarriers\nWi-Fi 3 utilizes 48 OFDM data subcarriers and Wi-Fi 4 increased this number to 52, thereby increasing the throughput to 52/48 * 54Mbps = 58.5Mbps.\n\n![](./subcarriers.png)\n\n#### Forward error correction\nThe most efficient coding rate used in Wi-Fi 3 was 3/4 but Wi-Fi increased this value to 5/6 by squeezing more bits. This has increased the throughput to (5/6)/(3/4) * 58.5Mbps = 65Mbps.\n\n#### Guard interval\nAs a measure to combat inter-symbol interference (ISA), Wi-Fi 3 utilizes 800nsec of guard interval between consecutive OFDM symbols. Wi-Fi 4 shortens this value to 400nsec, and this has increased the throughput to 4usec/3.6usec * 65Mbps = 72.2Mbps.\n\n![](./guard-interval.png)\n\n#### MIMO\nWi-Fi 4 was the first to introduce MIMO and standardized 4x4 spatial streams. This has quadrupled the throughput to 4*72.2Mbps = 288.9Mbps.\n\n![](./mimo.png)\n\n#### 40MHz bandwidth\nThe last thing Wi-Fi 4 introduced to the physical layer is a 40MHz bandwidth utilizing 108 OFDM data subcarriers. This has increased the throughput to 108/52 * 288.8Mbps = 600 Mbps.\n\n![](./40mhz.png)\n\n### MAC layer improvements\n\nOn top of the PHY layer improvements, Wi-Fi 4 also introduced frame aggregation at the MAC layer to ease the medium access contention. Two types of frame aggregation are used in Wi-Fi 4; A-MPDU and A-MSDU. While A-MSDU is efficient in medium occupation, a single packet error will make the whole frame unusable and require complete retransmission. However, A-MPDU aggregates multiple MPDUs by adding headers to each packet and a single packet error only requires single packet retransmission. As such, A-MPDU gained traction.\n\n![](./mpdu-aggr.png)\n\n\n## Supported openwifi 802.11n amendments\n\n- 52 subcarriers\n- 5/6 code rates\n- 400nsec short guard interval.\n\nCurrent theoretical throughput = 72.2Mbps.\n\n## To be supported openwifi 802.11n amendments\n- Frame aggregation\n\n## Not supported openwifi 802.11n amendments\n\n- MIMO\n- 40MHz bandwidth\n"
  },
  {
    "path": "doc/app_notes/inject_80211.md",
    "content": "<!--\nAuthor: Michael Mehari, Xianjun Jiao\nSPDX-FileCopyrightText: 2019 UGent\nSPDX-License-Identifier: AGPL-3.0-or-later\n-->\n\n## 802.11 packet injection and fuzzing\n\nThe Linux wireless networking stack (i.e. driver, mac80211, cfg80211, net_dev, user app) is a robust implementation supporting a plethora of wireless devices. As robust as it is, it also has a drawback when it comes to single-layer testing and manual/total control mode (fuzzing). \n\nPing and Iperf are well established performance measurement tools. However, using such tools to measure 802.11 PHY performance can be misleading, simply because they touch multiple layers in the network stack. \n\nLuckily, the mac80211 Linux subsystem provides packet injection functionality when the NIC is in the monitor mode and it allows us to have finer control for physical layer testing and/or fuzzing.\n\nBesides the traditional fuzzing tool (like scapy), we have adapted a [packetspammer](https://github.com/gnychis/packetspammer) application, which is originally written by Andy Green <andy@warmcat.com> and maintained by George Nychis <gnychis@gmail.com>, to show how to inject packets and control the FPGA behavior.\n\n### Build inject_80211 on board\nUserspace program to inject 802.11 packets through mac80211 supported (softmac) wireless devices.\n\nLogin/ssh to the board and setup internet connection according to the Quick Start. Then\n```\ncd openwifi/inject_80211\nmake\n```\n### Customize the packet content\nTo customize the packet, following piece of the inject_80211.c needs to be changed:\n```\n/* IEEE80211 header */\nstatic u8 ieee_hdr_data[] =\n{\n\t0x08, 0x02, 0x00, 0x00,\n\t0x66, 0x55, 0x44, 0x33, 0x22, 0x11,\n\t0x66, 0x55, 0x44, 0x33, 0x22, 0x22,\n\t0x66, 0x55, 0x44, 0x33, 0x22, 0x33,\n\t0x10, 0x86,\n};\n\nstatic u8 ieee_hdr_mgmt[] =\n{\n\t0x00, 0x00, 0x00, 0x00,\n\t0x66, 0x55, 0x44, 0x33, 0x22, 0x11,\n\t0x66, 0x55, 0x44, 0x33, 0x22, 0x22,\n\t0x66, 0x55, 0x44, 0x33, 0x22, 0x33,\n\t0x10, 0x86,\n};\n\nstatic u8 ieee_hdr_ack_cts[] =\n{\n\t0xd4, 0x00, 0x00, 0x00,\n\t0x66, 0x55, 0x44, 0x33, 0x22, 0x11,\n};\n\nstatic u8 ieee_hdr_rts[] =\n{\n\t0xb4, 0x00, 0x00, 0x00,\n\t0x66, 0x55, 0x44, 0x33, 0x22, 0x11,\n\t0x66, 0x55, 0x44, 0x33, 0x22, 0x22,\n};\n```\nNote: The byte/bit order might not be intuitive when comparing with the standard.\n\n### FPGA behavior control\n- ACK and retransmission after FPGA sends packet\n\nIn openwifi_tx of sdr.c, many FPGA behaviors can be controled. Generally they are controled by the information from upper layer (Linux mac80211), but you can override them in driver (sdr.c)\n\nIf 802.11 ACK is expected from the peer after the packet is sent by FPGA, variable **pkt_need_ack** should be overridden to 1. In this case, the FPGA will try to receive ACK, and report the sending status (ACK is received or not) to upper layer (Linux mac80211)\n\nThe maximum times of transmission for the packet can be controled by variable **retry_limit_raw**. If no ACK is received after the packet is sent, FPGA will try retransmissions automatically if retry_limit_raw>1.\n\n- ACK after FPGA receives packet in monitor mode\n\nEven in monitor mode, openwifi FPGA still sends ACK after the packet is received, if the conditions are met: MAC address is matched, it is a data frame, etc. To disable this automatic ACK generation, the register 11 of xpu should be set to 16:\n```\nsdrctl dev sdr0 set reg xpu 11 16 \n```\n\n### Options of program inject_80211\n```\n-m/--hw_mode <hardware operation mode> (a,g,n)\n-r/--rate_index <rate/MCS index> (0,1,2,3,4,5,6,7)\n-t/--packet_type (m/c/d/r for management/control/data/reserved)\n-e/--sub_type (hex value. example:\n     8/A/B/C for Beacon/Disassociation/Authentication/Deauth, when packet_type m\n     A/B/C/D for PS-Poll/RTS/CTS/ACK, when packet_type c\n     0/1/2/8 for Data/Data+CF-Ack/Data+CF-Poll/QoS-Data, when packet_type d)\n-a/--addr1 <the last byte of addr1 in hex>\n-b/--addr2 <the last byte of addr2 in hex>\n-i/--sgi_flag (0,1)\n-n/--num_packets <number of packets>\n-s/--payload_size <payload size in bytes>\n-d/--delay <delay between packets in usec>\n-h   this menu\n```\n\n### Example:\nLogin/ssh to the board, Then\n```\ncd openwifi\n./wgd.sh\n./monitor_ch.sh sdr0 11\n(Above will turn sdr0 into the monitor mode and monitor on channel 11)\n./inject_80211/inject_80211 -m n -r 0 -n 10 -s 64 sdr0\n(Above will inject 10 802.11n packets at 6.5Mbps bitrate and 64bytes size via NIC sdr0)\n```\nWhen above injection command is running, you could see the injected packets with wireshark (or other packet sniffer) on another WiFi device monitoring channel 11.\n\nOr add extra virtual monitor interface on top of sdr0, and inject packets:\n```\niw dev sdr0 interface add mon0 type monitor && ifconfig mon0 up\n./inject_80211/inject_80211 -m n -r 0 -n 10 -s 64 mon0     # Inject 10 802.11n packets at 6.5Mbps bitrate and 64bytes size\n```\n\n### Link performance test\n\nTo make a profound experimental analysis on the physical layer performance, we can rely on automation scripts.\n\nThe following script will inject 100 802.11n packets at different bitrates and payload sizes.\n\n```\n#!/bin/bash\n\nHW_MODE='n'\nCOUNT=100\nDELAY=1000\nRATE=( 0 1 2 3 4 5 6 7 )\nSIZE=( $(seq -s' ' 50 100 1450) ) # paload size in bytes\nIF=\"mon0\"\n\nfor (( i = 0 ; i < ${#PAYLOAD[@]} ; i++ )) do\n\tfor (( j = 0 ; j < ${#RATE[@]} ; j++ )) do\n\t\tinject_80211 -m $HW_MODE -n $COUNT -d $DELAY -r ${RATE[$j]} -s ${SIZE[$i]} $IF\n\t\tsleep 1\n\tdone\ndone\n\n```\n\nOn the receiver side, we can use tcpdump to collect the pcap traces.\n\n```\niw dev sdr0 interface add mon0 type monitor && ifconfig mon0 up\ntcpdump -i mon0 -w trace.pcap 'wlan addr1 ff:ff:ff:ff:ff:ff and wlan addr2 66:55:44:33:22:11'\n```\n\nWlan addresses *ff:ff:ff:ff:ff:ff* and *66:55:44:33:22:11* are specific to our injector application.\n\nNext, we analyze the collected pcap traces using the analysis tool provided.\n\n```\nanalyze_80211 trace.pcap\n```\n\nAn excerpt from a sample analysis looks the following\n\n```\nHW MODE\tRATE(Mbps)\tSGI\tSIZE(bytes)\tCOUNT\tDuration(sec)\n=======\t==========\t===\t===========\t=====\t=============\n802.11n\t6.5           \tOFF\t54\t\t100\t0.11159\n802.11n\t13.0\t\tOFF\t54\t\t100\t0.11264\n802.11n\t19.5\t\tOFF\t54\t\t100\t0.11156\n802.11n\t26.0\t\tOFF\t54\t    \t100\t0.11268\n802.11n\t39.0\t\tOFF\t54\t    \t100\t0.11333\n802.11n\t52.0\t\tOFF\t54\t    \t100\t0.11149\n802.11n\t58.5\t\tOFF\t54\t    \t100\t0.11469\n802.11n\t65.0\t\tOFF\t54\t    \t100\t0.11408\n```\n\n"
  },
  {
    "path": "doc/app_notes/iq-architecture.jpg.license",
    "content": "# Author: Xianjun jiao\n\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n"
  },
  {
    "path": "doc/app_notes/iq-capture-parameter.jpg.license",
    "content": "# Author: Xianjun jiao\n\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n"
  },
  {
    "path": "doc/app_notes/iq-information-format.jpg.license",
    "content": "# Author: Xianjun jiao\n\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n"
  },
  {
    "path": "doc/app_notes/iq-screen-shot.jpg.license",
    "content": "# Author: Xianjun jiao\n\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n"
  },
  {
    "path": "doc/app_notes/iq.md",
    "content": "<!--\nAuthor: Xianjun jiao\nSPDX-FileCopyrightText: 2019 UGent\nSPDX-License-Identifier: AGPL-3.0-or-later\n-->\n\n\nWe implement the **IQ sample capture** with interesting extensions: many **trigger conditions**; **RSSI**, RF chip **AGC** **status (lock/unlock)** and **gain**, Frequency offset FPGA vs Actual(floating point python algorithm based on IQ).\n\n(By default, openwifi Rx baseband is muted during self Tx, to unmute Rx baseband and capture self Tx signal you need to run \"./sdrctl dev sdr0 set reg xpu 1 1\" after the test running)\n\n[[Quick start](#Quick-start)]\n[[Understand the IQ capture feature](#Understand-the-IQ-capture-feature)]\n[[Config the IQ capture and interval](#Config-the-IQ-capture-and-interval)]\n[[Config the iq_len](#Config-the-iq_len)]\n\n[[Examine frequency offset estimation FPGA VS Python](#Examine-frequency-offset-estimation-FPGA-VS-Python)]\n[[Calculate SNR based on IQ](#Calculate-SNR-based-on-IQ)]\n\n[[Compile the side channel driver and user space program](#Compile-the-side-channel-driver-and-user-space-program)]\n[[Run the IQ capture together with modes other than monitor](#Run-the-IQ-capture-together-with-modes-other-than-monitor)]\n[[Map the IQ information to the WiFi packet](#Map-the-IQ-information-to-the-WiFi-packet)]\n\n## Quick start\n- Power on the SDR board.\n- Connect a computer to the SDR board via Ethernet cable. The computer should have static IP 192.168.10.1. Open a terminal on the computer, and then in the terminal:\n  ```\n  ssh root@192.168.10.122\n  (password: openwifi)\n  cd openwifi\n  ./wgd.sh\n  (Wait for the script completed)\n  ./monitor_ch.sh sdr0 11\n  (Monitor on channel 11. You can change 11 to other channel that is busy)\n  insmod side_ch.ko iq_len_init=8187\n  (for smaller FPGA (7Z020), iq_len_init should be <4096, like 4095, instead of 8187)\n  \n  ./side_ch_ctl wh3h01\n  (Enable the IQ capture and configure the IQ data source)\n\n  ./side_ch_ctl wh11d4094\n  (Above command is needed only when you run with zed, adrv9364z7020, zc702 board)\n  \n  ./side_ch_ctl g\n  ```\n  You should see on board outputs like:\n  ```\n  loop 64 side info count 61\n  loop 128 side info count 99\n  ...\n  ```\n  If the second number (side info count 61, 99, ...) keeps increasing, that means the trigger condition is met from time to time and the IQ sample is going to the computer smoothly.\n  \n- Open another terminal on the computer, and run:\n  ```\n  cd openwifi/user_space/side_ch_ctl_src\n  python3 iq_capture.py\n  (for zed, adrv9364z7020, zc702 board, add argument that euqals to iq_len_init, like 4095)\n  ```\n  You might need to install beforehand: \"sudo apt install python3-numpy python3-matplotlib python3-tk\". Now you should see 3 figures showing run-time **IQ sample**, **AGC gain and lock status** and **RSSI (uncalibrated)**. Meanwhile the python script prints the **timestamp**.\n  ![](./iq-screen-shot.jpg)\n  \n  While running, all information is also stored into a file **iq.txt**. A matlab script **test_iq_file_display.m** is offered to help you do analysis on the IQ Information offline. For zed, adrv9364z7020, zc702 board, do not forget to change the **iq_len** in the matlab script to 4095.\n\n## Understand the IQ capture feature\n  The IQ information is extracted via the openwifi **side channel** infrastructure. This figure explains the related modules (also related source code file name) and how the information goes from the SDR board to the computer.\n  ![](./iq-architecture.jpg)\n\n  The IQ information format is shown in this figure.\n  ![](./iq-information-format.jpg)\n\n  For each element, the actual size is 64bit.\n  - timestamp: 64bit TSF timer value when the capture is triggered.\n  - IQ\n    - The first two 16bit are used for I/Q sample from the antenna currently used\n    - The 3rd 16bit is AD9361 AGC gain (bit7 -- lock/unlock; bit6~0 -- gain value)\n    - The 4th 16bit is RSSI (half dB, uncalibrated). Please check xpu.v and sdr.c to understand how the raw RSSI value is finally calibrated and reported to Linux mac80211.\n    \n  The python and Matlab scripts are recommended for you to understand the IQ packet format precisely.\n\n## Config the IQ capture and interval\n  The quick start guide captures a period of history IQ when the packet FCS checksum is checked by Wifi receiver (no matter pass or fail). To initiate the capture with different trigger conditions and length, configuration commands should be issued before executing \"**side_ch_ctl g**\". The configuration command is realized by feeding a different parameter to \"**side_ch_ctl**\". The main parameters that are configurable are explained in this figure.\n  ![](./iq-capture-parameter.jpg)\n  \n  **iq_len** is the number of IQ samples captured per trigger condition met. The capture is started from the time **pre_trigger_len** IQ samples before the trigger moment. **iq_len** is set only one time when you insert the side_ch.ko. Please check the next section for **iq_len** configuration. This section introduces the setting of pre_trigger_len and trigger condition.\n  - pre_trigger_len\n  ```\n  ./side_ch_ctl wh11dY\n  ```\n  The parameter **Y** specifies the pre_trigger_len. Valid range 0 ~ 8190. It is limited by the FPGA fifo size. For **small FPGA** (zed_fmcs2, adrv9364z7020, zc702), the valid range is 0 ~ **4094**.\n  - trigger condition\n  ```\n  ./side_ch_ctl wh8dY\n  ```\n  The parameter **Y** specifies the trigger condition. Valid range 0 ~ 31, which is explained in this table.\n  \n  value|meaning\n  -----|-------\n  0 |receiver gives FCS checksum result. no matter pass/fail. Or free run\n  1 |receiver gives FCS checksum result. pass\n  2 |receiver gives FCS checksum result. fail\n  3 |the tx_intf_iq0 becomes non zero (the 1st I/Q out)\n  4 |receiver gives SIGNAL field checksum result. pass\n  5 |receiver gives SIGNAL field checksum result. fail\n  6 |receiver gives SIGNAL field checksum result. no matter pass/fail. HT packet\n  7 |receiver gives SIGNAL field checksum result. no matter pass/fail. non-HT packet\n  8 |receiver gives  long preamble detected\n  9 |receiver gives short preamble detected\n  10|RSSI (half dB uncalibrated) goes above the threshold\n  11|RSSI (half dB uncalibrated) goes below the threshold\n  12|AD9361 AGC from lock to unlock\n  13|AD9361 AGC from unlock to lock\n  14|AD9361 AGC gain goes above the threshold\n  15|AD9361 AGC gain goes below the threshold\n  16|tx_control_state_hit when xpu tx_control_state hit the specified value (by side_ch_ctl wh5)\n  17|phy_tx_done signal from openofdm tx core\n  18|positive edge of tx_bb_is_ongoing from xpu core\n  19|negative edge of tx_bb_is_ongoing from xpu core\n  20|positive edge of tx_rf_is_ongoing from xpu core\n  21|negative edge of tx_rf_is_ongoing from xpu core\n  22|phy_tx_started and this tx packet needs ACK\n  23|phy_tx_done and this tx packet needs ACK\n  24|both tx_control_state and phy_type (0 Legacy; 1 HT; 2 HE) hit (by side_ch_ctl wh5)\n  25|addr1 and/or addr2 are matched. Please check the related addr1/2 match config in CSI app note\n  26|positive edge of tx_rf_is_ongoing and this tx packet needs ACK\n  27|negative edge of tx_rf_is_ongoing and this tx packet needs ACK\n  28|tx_bb_is_ongoing and I/Q amplitude from the other antenna is above rssi_or_iq_th\n  29|tx_rf_is_ongoing and I/Q amplitude from the other antenna is above rssi_or_iq_th\n  30|start tx, meanwhile I/Q amplitude from the other antenna is above rssi_or_iq_th\n  31|start tx and need for ACK, meanwhile I/Q amplitude from the other antenna is above rssi_or_iq_th\n  \n  Hardware register 5 has fields for multi-purpose. bit0 for free running mode. bit7~4 for tx_control_state target value. bit 9~8 for phy_type. For example, set target tx_control_state to SEND_BLK_ACK (3) and phy_type to HE (2):\n  ```\n  ./side_ch_ctl wh5h230\n  ```\n\n  If free running is wanted (alway trigger), please use the following two commands together.\n  ```\n  ./side_ch_ctl wh8d0\n  ./side_ch_ctl wh5d1\n  ```\n  \n  To set the RSSI threshold\n  ```\n  ./side_ch_ctl wh9dY\n  ```\n  The parameter **Y** specifies the RSSI threshold. Valid range 0 ~ 2047.\n  \n  To set the AGC gain threshold\n  ```\n  ./side_ch_ctl wh10dY\n  ```\n  The parameter **Y** specifies the AGC gain threshold. Valid range 0 ~ 127.\n  \n  The command \"**side_ch_ctl g**\" will perform IQ capture every 100ms until you press ctrl+C. To use a different capture interval:\n  ```\n  side_ch_ctl gN\n  ```\n  The interval will become N*1ms\n\n## Examine frequency offset estimation FPGA VS Python\n  The script **iq_capture_freq_offset.py** can show the FPGA estimated frequency offset and the actual frequency offset calculated by floating point python algorithm. If they are very different, you could try to override the FPGA frequency estimation module by **user_space/receiver_phase_offset_override.sh** with the result from the python algorithm.\n\n  **DO NOT FORGET** to change **LUT_SIZE** in the **iq_capture_freq_offset.py** if you are testing 80211ax.\n\n  To use the **iq_capture_freq_offset.py**, here is an example command sequence (also available at the beginning of **iq_capture_freq_offset.py**):\n  - On board, insert the module with iq length 1500 and set: pre trigger length 1497, the MAC address of the peer, the self MAC address, enable the MAC address match, trigger condition 25 (both addr1 and addr2 match), starting capture.\n    ```\n    insmod side_ch.ko iq_len_init=1500\n    ./side_ch_ctl wh11d1497\n    ./side_ch_ctl wh7h635c982f\n    ./side_ch_ctl wh6h44332236\n    ./side_ch_ctl wh1h6001\n    ./side_ch_ctl wh8d25\n    ./side_ch_ctl g0\n    ```\n    In the case of totally clean/non-standard channel, long preamble detected can also be used as trigger condition:\n    ```\n    insmod side_ch.ko iq_len_init=1500\n    ./side_ch_ctl wh11d1497\n    ./side_ch_ctl wh8d8\n    ./side_ch_ctl g0\n    ```\n  - On host PC:\n    ```\n    python3 iq_capture_freq_offset.py 1500\n    ```\n  It will print phase_offset value (FPGA VS python) in the shell, and plot some real-time figures.\n\n## Calculate SNR based on IQ\n  After the IQ is captured and the .mat file has been generated by **test_iq_file_display.m**, **show_iq_snr.m** can be used to calculate the SNR (Signal to Noise Ratio) based on the .mat file in Matlab.\n\n  It is recommended to do this SNR check with single signal/packet source in a very clean (such as cable test in non-standard channels) environment. Otherwise the SNR statistics over variant link status is less meaningful.\n\n  - The 1st step is running with .mat file as the only argument in Matlab:\n    ```\n    show_iq_snr(mat_file_name)\n    ```\n    It will show a figure of relative RSSI change (dB). You should decide the middle value which is roughly the middle point between the high RSSI (signal) and low RSSI.\n  - The 2nd step is running with .mat file and the middle value as arguments in Matlab:\n    ```\n    show_iq_snr(mat_file_name, middle_value)\n    ```\n    It will show the SNR in Matlab command line, and plot the figure with signal and noise regions identified.\n\n## Config the iq_len\n  The **iq_len** (number of IQ sample per capture) is configurable in case you want less IQ samples per capture so that it can be triggered more times during a specific analysis period. The valid value is 1~**8187**. For **small FPGA** (zed_fmcs2, adrv9364z7020, zc702), the valid range is 0 ~ **4095**. It is independent from pre_trigger_len, and it can be less than pre_trigger_len if you want. You should align the **iq_len** value at the side_ch.ko, iq_capture.py and test_iq_file_display.m. \n  - When insert the kernel module, use:\n  ```\n  insmod side_ch.ko iq_len_init=3000\n  ```\n  Here 3000 is an example. **ATTENTION:** You need to specify **iq_len_init** explicitly to turn on IQ capture, which will turn off the default CSI mode. Insert the side_ch.ko without any parameter will run the default CSI mode.\n  - When launch the python script, use:\n  ```\n  python3 iq_capture.py 3000\n  ```\n  - When use the matlab script, please change the **iq_len** variable in the script to 3000.\n\n## Compile the side channel driver and user space program\n  - side_ch.ko\n  ```\n  $OPENWIFI_DIR/driver/side_ch/make_driver.sh $OPENWIFI_DIR $XILINX_DIR ARCH_BIT\n(For Zynq 7000, ARCH_BIT should be 32, for Zynq MPSoC, ARCH_BIT should be 64)\n  ```\n  - side_ch_ctl (take user_space/side_ch_ctl_src/side_ch_ctl.c and compile it on board!)\n  ```\n  gcc -o side_ch_ctl side_ch_ctl.c\n  ```\n\n## Run the IQ capture together with modes other than monitor\n  The openwifi IQ capture feature could run with not only monitor mode but also other modes, such as AP-Client or ad-hoc mode. After the communication functionality is fully up in those modes, you can start IQ capture from \"**insmod side_ch.ko**\" and \"**./side_ch_ctl g**\" on board as described in the previous sections to extract IQ information to your computer.\n\n## Map the IQ information to the WiFi packet\n  Recent tutorial: https://github.com/open-sdr/openwifi/discussions/344\n\n  Old text:\n\n  If you want to relate the IQ information to the WiFi packet, you need to capture WiFi packets (tcpdump/wireshark/etc) while capturing IQ. Then you can relate the timestamp between WiFi packet and IQ information. Please be noticed that the timestamp in the IQ information is the moment when capture is triggered, which could be different from the timestamp reported in the packet capture program. But since they share the same time base (TSF timer), you can relate them easily by analyzing the WiFi packet and IQ sample sequence.\n  \n  Please learn the python and Matlab script to extract IQ information per capture according to your requirement.\n"
  },
  {
    "path": "doc/app_notes/iq_2ant-screen-shot.jpg.license",
    "content": "# Author: Xianjun jiao\n\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n"
  },
  {
    "path": "doc/app_notes/iq_2ant-setup.png.license",
    "content": "# Author: Xianjun jiao\n\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n"
  },
  {
    "path": "doc/app_notes/iq_2ant.md",
    "content": "<!--\nAuthor: Xianjun jiao\nSPDX-FileCopyrightText: 2019 UGent\nSPDX-License-Identifier: AGPL-3.0-or-later\n-->\n\n\nInstead of [**normal IQ sample capture**](iq.md), this app note introduces how to enable the I/Q capture for dual antennas. Besides the I/Q from the main antenna (that is selected by baseband), the I/Q samples from the other antenna (monitoring antenna) is captured as well (coherently synchronized) in this dual antenna mode. You are suggested to read the [**normal IQ sample capture**](iq.md) to understand how we use the side channel to capture I/Q samples by different trigger conditions.\n\n(By default, openwifi Rx baseband is muted during self Tx, to unmute Rx baseband and capture self Tx signal you need to run \"./sdrctl dev sdr0 set reg xpu 1 1\" after the test running)\n\nThis feature also support capturing TX I/Q (loopback) to test the baseband transmitter.\n\n- [[Quick start for collision capture](#Quick-start-for-collision-capture)]\n- [[Quick start for TX IQ capture in trigger mode](#Quick-start-for-TX-IQ-capture-in-trigger-mode)]\n- [[Quick start for TX IQ capture in free running mode](#Quick-start-for-TX-IQ-capture-in-free-running-mode)]\n\n## Quick start for collision capture\n![](./iq_2ant-setup.png)\n\n  The main antenna rx0 (by default selected by baseband if you do not select explicitly by set_ant.sh) is always used for communication and I/Q capture. Meanwhile, the other antenna (rx1 -- monitoring antenna) will be also available for capturing rx I/Q if you are using AD9361 based RF board, such as fmcomms2/3 and adrv9361z7035, by turning on the **dual antenna capture** mode. In this case, you can place the other antenna (rx1) close to the communication peer (for example, the other WiFi node) to capture the potential collision by monitoring rx1 I/Q. The nature of collision is that both sides of a communication link are trying to do transmission at the same time.\n  \n  The collision capture steps:\n  - Change rx1 AGC to manual mode instead of fast_attack in rf_init.sh by:\n  ```\n  echo manual > in_voltage1_gain_control_mode\n  ```\n  - Change rx1 gain to a low level, such as 20, by:\n  ```\n  echo 20 > in_voltage1_hardwaregain\n  ```\n  - Use the new rf_init.sh script to boot up the SDR board, and setup the working scenario.\n  - Setup the side channel:\n  ```\n  insmod side_ch.ko iq_len_init=8187\n  (iq_len_init should be <4096, like 4095, if smaller FPGA, like z7020, is used)\n  ./side_ch_ctl wh11d2000\n  (Set a smaller pre_trigger_len 2000, because we want to see what happens after the trigger instead of long period stored before the trigger)\n  ```\n  - Put the other antenna (rx1) close to the peer WiFi node, set trigger condition to 23 (baseband tx done)\n  ```\n  ./side_ch_ctl wh8d23\n  ```\n  - Enable the **dual antenna capture** mode\n  ```\n  ./side_ch_ctl wh3h11\n  ```\n  - Run some traffic between the SDR board and the peer WiFi node, and start the user space I/Q capture program\n  ```\n  ./side_ch_ctl g\n  ```\n  If the printed \"**side info count**\" is increasing, it means the trigger condition is met from time to time.\n  - On remote computer, run\n  ```\n  python3 iq_capture_2ant.py\n  (if smaller FPGA, like z7020, is used, add a argument that equals to iq_len_init, like 4095)\n  ```\n  Above script will plot the real-time rx0 and rx1 I/Q captured each time the trigger condition is met. . \n  ![](./iq_2ant-screen-shot.jpg)\n  In the above example, the upper half shows the signal received from the main antenna (self tx is not seen because of self muting in FPGA), the lower half shows not only the rx signal from the monitoring antenna but also the tx signal from the main antenna due to coupling.\n  Meanwhile the script also prints the maximum amplitude of the rx0 and rx1 I/Q samples. Check the 3rd column that is displayed by the script: Those small value printing indicate noise (most probably, because the rx1 gain is very low). The big value printing indicates a packet from rx1 (although rx1 has very low gain, rx1 is very close to the peer WiFi node). Go through the noise and the packet max I/Q amplitude numbers from rx1 printing (the 3rd column), and decide a threshold value that is significantly higher than the noise but less than those big values (packets).\n  - Set trigger condition to 29, which means that rx1 I/Q is found larger than a threshold while SDR is transmitting -- this means a collision condition is captured because rx1 I/Q implies the transmitting from the peer WiFi node. The threshold value is decided in the previous step (2500 is assumed here).\n  ```\n  (Quit side_ch_ctl by Ctrl+C)\n  ./side_ch_ctl wh8d29\n  ./side_ch_ctl wh9d2500\n  ./side_ch_ctl g\n  ```\n  - Now the trigger condition can capture the case where both sides happen to transmit in an overlapped duration. If the  printed \"**side info count**\" is increasing, it means the collision happens from time to time.\n  - You can also see it via iq_capture_2ant.py or do offline analysis by test_iq_2ant_file_display.m \n  - Check the **iq1** signal in FPGA ILA/probe (triggered by signal \"iq_trigger\") for further debug if you want to know what exactly happened when collision is captured.\n\n## Quick start for TX IQ capture in trigger mode\n\nTo capture the TX I/Q (baseband loopback), a scenario where openwifi will do TX needs to be set up. Such as beacon TX when openwifi act as AP, or [packet injection](inject_80211.md).\n\nThe example command sequence on board and explanations are as follows.\n```\ncd openwifi\n./fosdem.sh\ninsmod side_ch.ko iq_len_init=511\n(511 I/Q samples cover the short, long preamble and some OFDM symbols. Change it according to your case)\n./side_ch_ctl wh11d1\n(1 sample before the trigger met will be captured. So most of the I/Q will be captured after trigger met)\n./side_ch_ctl wh8d16\n(trigger condition 16: phy_tx_started signal from openofdm tx core)\n./side_ch_ctl wh5h2\n(I/Q source selection: 2--openofdm_tx core; 4--tx_intf)\n./side_ch_ctl wh3h11\n./side_ch_ctl g1\n```\nOn computer:\n```\nopenwifi/user_space/side_ch_ctl_src/python3 iq_capture_2ant.py 511\n\n```\n\n## Quick start for TX IQ capture in free running mode\n\n```\ncd openwifi\n./fosdem.sh\ninsmod side_ch.ko iq_len_init=511\n(511 I/Q samples cover the short, long preamble and some OFDM symbols. Change it according to your case)\n./side_ch_ctl wh11d1\n(1 sample before the trigger met will be captured. So most of the I/Q will be captured after trigger met)\n./side_ch_ctl wh8d0\n(trigger condition 0 is needed for free running mode)\n./side_ch_ctl wh5h3\n(I/Q source selection: 3--openofdm_tx core; 5--tx_intf)\n./side_ch_ctl wh3h11\n./side_ch_ctl g1\n```\nOn computer:\n```\nopenwifi/user_space/side_ch_ctl_src/python3 iq_capture_2ant.py 511\n\n```\n"
  },
  {
    "path": "doc/app_notes/iq_ack_timing.md",
    "content": "<!--\nAuthor: Xianjun jiao\nSPDX-FileCopyrightText: 2023 UGent\nSPDX-License-Identifier: AGPL-3.0-or-later\n-->\n\nThsi app note show how to measure the ACK timing based on [**IQ sample capture**](iq.md)\n\n## Quick start\n- Setup a normal communication link between the SDR board and other devices. (Check Quick start guide in README or other app notes)\n- Setup IQ capture triggered by the event of ACK sending.\n  ```\n  ./sdrctl dev sdr0 set reg xpu 1 1\n\n  insmod side_ch.ko iq_len_init=8187\n  (For smaller FPGA (7Z020), iq_len_init should be <4096, like 4095, instead of 8187)\n  \n  ./side_ch_ctl wh11d4096\n  (For smaller FPGA (7Z020), 4094 should be 2048)\n\n  ./side_ch_ctl wh3h21\n  (Enable the IQ capture and configure the correct IQ data composition for ACK timing check)\n  \n  ./side_ch_ctl wh5h20\n  ./side_ch_ctl wh8d16\n\n  ./side_ch_ctl g0\n  ```\n  The 1st command keeps the receiver always ON to monitor incoming packet and ACK sent by its own. The second and the 3rd command set the capture length and pre trigger length. \n  \n  The 4th command sets the target tx_control_state to SEND_DFL_ACK (check tx_control.v) -- the value is defined at bit 7~4, so 0x2 becomes 0x20. \n  Other useful state values: SEND_BLK_ACK 0x30, RECV_ACK 0x60. Other state, such as RECV_ACK_WAIT_SIG_VALID/0x50, is not recommended, otherwise the Matlab analysis script needs to be changed accordingly.\n  \n  The next command sets the trigger condition to the tx_control_state_hit (index 16. check side_ch_control.v), which means that when the real-time tx_control_state is equal \n  to the target set by previous command, IQ capture will be performed once.\n\n  The trigger condition could also be the combination of tx_control_state and PHY type (0 - Legacy; 1 - HT; 2 - HE) of the received packet. This allows us to monitor \n  the specific ACK Tx GAP after receiving the packet with the specific PHY type. To use this, PHY type should be put into the position of \"x\", and trigger condition index \n  should be 24 instead of 16.\n  ```\n  ./side_ch_ctl wh5hx20\n  ./side_ch_ctl wh8d24\n  ```\n\n- You should see on board outputs like (Be sure running traffics to trigger ACK event!):\n  ```\n  loop 64 side info count 3\n  loop 128 side info count 5\n  ...\n  ```\n  If the second number (side info count 61, 99, ...) keeps increasing, that means the trigger condition is met from time to time and the IQ sample is going to the computer smoothly.\n  \n- Open another terminal on the computer, and run:\n  ```\n  cd openwifi/user_space/side_ch_ctl_src\n  python3 iq_capture.py\n  (for zed, adrv9364z7020, zc702 board, add argument that euqals to iq_len_init, like 4095)\n  ```\n  While running traffic, you should see 3 figures popped up with run-time **IQ sample**, **AGC gain and lock status** and **RSSI (uncalibrated)**. Meanwhile the python script prints the **timestamp**. In the IQ sample window, IQ samples of two packets are expected in the central position spaced by +/-16us (320 samples), which is the ACK timing.\n  \n  ![](./iq-ack-timing-screen-shot.jpg)\n  \n  While running, all information is also stored into a file **iq.txt**. \n\n## Test methodology\n  The timing of ACK openwifi sent becomes complicated due to different decoding latency of incoming packet when there are different number of bytes/bits in the last OFDM symbol. We should check this after any change that potentially affects the decoding latency.\n\n  To test this, another openwifi board can be used as a client, and sends packets with different numbers of bytes in the last OFDM symbol through all MCSs. Check \n  [this app note](frequent_trick.md#Tx-rate-config) for overriding MCS. The following bash script can be used to send packets in different packet sizes (20 to 60 bytes in this example). DO NOT forget to set up the capture on board and launch the \"python3 iq_capture.py\" on the computer before running the following commands.\n  ```\n  for nbyte in {20..60}; do ping 192.168.13.1 -s $nbyte -c 1; sleep 0.3; done\n  ```\n\n  Or use any other device/test-box that can send out packet with specified MCS and size towards openwifi board.\n\n## Analyze the ACK timing by Matlab script and Wireshark\n  A matlab script **test_iq_file_ack_timing_display.m** is offered to help you do analysis on the ACK timing based on **iq.txt**. For boards with small FPGA (7020), do not forget to give 4095 (**iq_len**) as the 1st argument.\n  ```\n  test_iq_file_ack_timing_display(8187);\n  ```\n  Figure 1 shows the timestamp of all received packets. Figure 2~4 shows the IQ sample and related signals of a specific capture. Figure 5 shows the GAP between a received ACK and the packet sent by openwifi -- Rx ACK GAP. Figure 6 shows the GAP between a received packet and the ACK sent by openwifi -- Tx ACK GAP. Normally they should around 16us. \"-1\" means no such an event is observed at that capture.\n  \n  ![](./iq-ack-timing-matlab-tx-ack-gap.jpg)\n  \n  Above figure shows that there are two abnormal GAPs for Tx ACK. One is around 12us (Cap idx 2), the other is -1 (Cap idx 11).\n\n  To look into the details of the capture index 2, that capture index should be given as the 2nd parameter to the Matlab script.\n  ```\n  test_iq_file_ack_timing_display(8187, 2);\n  ```\n  \n  ![](./iq-ack-timing-matlab-tx-ack-iq.jpg)\n  \n  From above figure, it was discovered that the DC power caused by AGC action before the actual ACK packet is regarded as the beginning of the ACK packet, that is why the GAP calculation result is smaller. This bug has been fixed already in the Matlab analysis script. Following figure shows the fixed analysis result.\n  \n  ![](./iq-ack-timing-matlab-tx-ack-gap-fixed.jpg)\n\n  To relate the captured IQ snapshot (with ACK timing in it) with the detailed packet information in Wireshark, please check this discussion on github: https://github.com/open-sdr/openwifi/discussions/344 ."
  },
  {
    "path": "doc/app_notes/mimo.png.license",
    "content": "# Author: Michael Mehari\n\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\n"
  },
  {
    "path": "doc/app_notes/mpdu-aggr.png.license",
    "content": "# Author: Michael Mehari\n\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\n"
  },
  {
    "path": "doc/app_notes/packet-iq-self-loopback-test.md",
    "content": "<!--\nAuthor: Xianjun Jiao\nSPDX-FileCopyrightText: 2022 UGent\nSPDX-License-Identifier: AGPL-3.0-or-later\n-->\n\nOne super power of the openwifi platform is \"**Full Duplex**\" which means that openwifi baseband can receive its own TX signal.\nThis makes the IQ sample, WiFi packet and CSI self loopback test possible. Reading the normal [IQ sample capture app note](iq.md) and [CSI radar app note](radar-self-csi.md) will help if you have issue or want to understand openwifi side channel (for IQ and CSI) deeper.\n![](./openwifi-loopback-principle.jpg)\n\n[[IQ self loopback quick start](#IQ-self-loopback-quick-start)]\n[[Check the packet loopback on board](#Check-the-packet-loopback-on-board)]\n[[IQ self loopback config](#IQ-self-loopback-config)]\n[[CSI FPGA self loopback quick start](#CSI-FPGA-self-loopback-quick-start)]\n\n## IQ self loopback quick start\n(Please replace the IQ length **8187** by **4095** if you use low end FPGA board: zedboard/adrv9464z7020/antsdr/zc702/sdrpi)\n- Power on the SDR board.\n- Put the Tx and Rx antenna as close as possible.\n- Connect a computer to the SDR board via Ethernet cable. The computer should have static IP 192.168.10.1. Open a terminal on the computer, and then in the terminal:\n  ```\n  # ssh into the SDR board, password: openwifi\n  ssh root@192.168.10.122\n  cd openwifi\n  # Bring up the openwifi NIC sdr0\n  ./wgd.sh\n\n  # Setup monitor mode in WiFi channel 44. You should find a channel as clean as possible in your location. Note that some channels don't work, so stick to 44 or 48 for now.\n  ./monitor_ch.sh sdr0 44\n\n  # Turn off CCA by setting a very high threshold that make the CSMA engine always think the channel is idle (no incoming signal is higher than this threshold)\n  ./sdrctl dev sdr0 set reg xpu 8 1000\n  \n  # Load side channel kernel module with buffer lenght of 8187 (replace this with 4095 when using low end FPGA board)\n  insmod side_ch.ko iq_len_init=8187\n  \n  # Set 100 to register 11. It means the pre trigger length is 100, so we mainly capture IQ after trigger condition is met\n  ./side_ch_ctl wh11d100\n  # Set 16 to register 8 -- set trigger condition to phy_tx_started signal from openofdm tx core\n  ./side_ch_ctl wh8d16\n  # Unmute the baseband self-receiving to receive openwifi own TX signal/packet -- important for self loopback!\n  ./sdrctl dev sdr0 set reg xpu 1 1\n  # Set the loopback mode to over-the-air\n  ./side_ch_ctl wh5h0\n  (./side_ch_ctl wh5h4 for FPGA internal loopback)\n  # Relay the FPGA IQ capture to the host computer that will show the captured IQ later on)\n  ./side_ch_ctl g0\n  ```\n  You should see on outputs like:\n  ```\n  loop 22848 side info count 0\n  loop 22912 side info count 0\n  ...\n  ```\n  Now the count is always 0, because we haven't instructed openwifi to send packet for loopback test.\n  \n- Leave above ssh session untouched. Open a new ssh session to the board from your computer. Then run on board:\n  ```\n  cd openwifi/inject_80211/\n  make\n  # Build our example packet injection program\n  ./inject_80211 -m n -r 5 -n 1 sdr0\n  # Inject one packet to openwifi sdr0 NIC\n  ```\n  Normally in the previous ssh session, the count becomes 1. It means one packet (of IQ sample) is sent and captured via loopback over the air.\n  \n  If 1 is not seen, you can try to put the receiver into reset state, so it won't block the system in case it runs into dead state\n  ```\n  ./sdrctl dev sdr0 set reg rx 0 1\n  ```\n\n- On your computer (NOT ssh onboard!), run:\n  ```\n  cd openwifi/user_space/side_ch_ctl_src\n  python3 iq_capture.py 8187\n  ```\n  You might need to install beforehand: \"sudo apt install python3-numpy python3-matplotlib python3-tk\".\n  \n- Leave the above host session untouched. Let's go to the second ssh session (packet injection), and do single packet Tx again:\n  ```\n  ./inject_80211 -m n -r 5 -n 1 sdr0\n  ```\n  Normally in the 1st ssh session, the count becomes 2. You should also see IQ sample capture figures like this:\n  ![](./openwifi-iq-loopback.jpg)\n  \n- Stop the python3 script, which plots above, in the host session. A file **iq.txt** is generated. You can use the Matlab script test_iq_file_display.m \nto do further offline analysis, or feed the IQ sample to the openwifi receiver simulation, etc.\n\n## Check the packet loopback on board\n\n- While signal/packet is looped back, you can capture it on board via normal sniffer program for further check/analysis on the packet (bit/byte level instead of IQ level), such as tcpdump or tshark.\n  A new ssh session to the board should be opened to do this before running the packet injection:\n  ```\n  tcpdump -i sdr0\n  ```\n  Run the packet injection \"./inject_80211 -m n -r 5 -n 1 sdr0\" in another session, you should see the packet information printed by tcpdump from self over-the-air loopback. In case you put the receiver into reset state in the previous IQ loopback, you should put the receiver back to normal for packet loopback (otherwise the receiver won't decode the IQ signal back to packet):\n  ```\n  ./sdrctl dev sdr0 set reg rx 0 0\n  ```\n  \n- You can also see the openwifi printk message of Rx packet (self Tx looped back) while the packet comes to the openwifi Rx interrupt.\n  A new ssh session to the board should be opened to do this before running the packet injection:\n  ```\n  cd openwifi\n  ./sdrctl dev sdr0 set reg drv_rx 7 7\n  ./sdrctl dev sdr0 set reg drv_tx 7 7\n  # Turn on the openwifi Tx/Rx printk logging\n  ```\n  Stop the \"./side_ch_ctl g0\" in the very first ssh session. Run the packet injection, then check the printk message:\n  ```\n  ./inject_80211/inject_80211 -m n -r 5 -n 1 sdr0\n  dmesg\n  ```\n  You should see the printk message of packet Tx and Rx from the openwifi driver (sdr.c).\n\n## IQ self loopback config\n\n- By default, the loopback is via the air (from Tx antenna to Rx antenna). FPGA inernal loopback option is offered to have IQ sample and packet without \n  any interference. To have FPGA internal loopback, replace the \"./side_ch_ctl wh5h0\" during setup (the very 1st ssh session) by:\n  ```\n  ./side_ch_ctl wh5h4\n  ```\n- Lots of packet injection parameters can be set: number of packet, type (data/control/management), MCS/rate, size, interval, etc. Please run the packet injection\n  program without any arguments to see the help.\n  \n- Besides the packet Tx via injection over monitor mode for loopback test, normal WiFi mode (AP/Client/ad-hoc) can also run together with self loopback. \n  For instance, run **fosdem.sh** instead of **wgd.sh** to setup an openwifi AP that will transmit beacons. The wgd.sh can also be replaced with other scenario\n  setup scripts. Please check [Application notes](README.md)\n\n- To understand deeper of all above commands/settings, please refer to [Capture IQ sample, AGC gain, RSSI with many types of trigger condition](iq.md) and\n  [Capture dual antenna TX/RX IQ for multi-purpose (capture collision)](iq_2ant.md)\n  \n## CSI FPGA self loopback quick start\n\nThis section will show how to connect the WiFi OFDM transmitter to the receiver directly inside FPGA, and show the ideal CSI/constellation/frequency-offset. (For CSI over the air loopback, please refer to [CSI radar app note](radar-self-csi.md))\n\nCommand sequence on board:\n```\ncd openwifi\n./wgd.sh\n./monitor_ch.sh sdr0 6\ninsmod side_ch.ko\n./side_ch_ctl g\n```\nOpen another ssh session on board, then:\n```\ncd openwifi\n./sdrctl dev sdr0 set reg rx_intf 3 256\n(Above command let the FPGA Tx IQ come to receiver directly. Set 256 back to 0 to let receiver back connect to AD9361 RF frontend)\n./sdrctl dev sdr0 set reg rx 5 768\n(Disable the receiver FFT window shift. By default it is 1 (768+1) -- good for multipath, overfitting for direct loopback)\n./inject_80211/inject_80211 -m n -r 7 -n 99999 -s 1400 -d 1000000 sdr0\n(Transmit 802.11n MCS7 1400Byte packet every second)\n```\n\nCommand on computer:\n```\ncd openwifi/user_space/side_ch_ctl_src\npython3 side_info_display.py\n```\nNow you should see the following screenshot that shows the CSI/constellation/frequency-offset over this in-FPGA ideal channel.\n![](./openwifi-csi-fpga-loopback.jpg)\n"
  },
  {
    "path": "doc/app_notes/perf_counter.md",
    "content": "<!--\nAuthor: Xianjun jiao\nSPDX-FileCopyrightText: 2019 UGent\nSPDX-License-Identifier: AGPL-3.0-or-later\n-->\n\nCounter/statistics (number of TX packet, RX packet, watchdog event, etc.) in FPGA is offered via register write/read.\n\n[[PHY RX TX event counter in side channel](#PHY-RX-TX-event-counter-in-side-channel)]\n[[PHY RX watchdog event counter in openofdm rx](#PHY-RX-watchdog-event-counter-in-openofdm-rx)]\n\n## PHY RX watchdog event counter in openofdm rx\nThere is a signal_watchdog module inside openofdm_rx to detect the abnormal signal as early as possible, so that the receiver will not be busy with fake/abnormal signal for long time. (If the receiver is attracted by fake/abnormal signal easily, it could miss the normal/target packet).\n\nTo access the watchdog event counter in openofdm_rx, [sdrctl command](../README.md#sdrctl-command) is used.\n\nTo select the event you are interested in:\n```\nsdrctl dev sdr0 set reg rx 17 event_type\n```\nThe event_type options:\n- 0: phase_offset(sync_short) too big\n- 1: Too many equalizer out small values\n- 2: DC/slow-sine-wave is detected\n- 3: Packet too short\n- 4: Packet too long\n\nTo read the event counter (selected by register 17 above):\n```\nsdrctl dev sdr0 get reg rx 30\n```\nWrite any value to above register 30 will clear the selected event counter (by register 17).\n\n## PHY RX TX event counter in side channel\nThe 1st step is alway loading the side channel kernel module:\n```\ninsmod side_ch.ko\n```\n\nThe register write command is:\n```\n./side_ch_ctl whXdY\nX -- register index\nY -- decimal value to be written\n./side_ch_ctl whXhY\nX -- register index\nY -- hex value to be written (useful for MAC address)\n```\nWrite register 26~31 with arbitrary value to reset the corresponding counter to 0.\n\nThe register read command is:\n```\n./side_ch_ctl rhX\nX -- register index\n```\n\n**Register definition:**\n\nThe register 26~31 readback value represents the number of event happened. Each register has two event sources that can be selected via bit in register 19.\n\nregister idx|source selection reg19|event\n------------|----------------------|-----------\n26          |reg19[0] == 0         |short_preamble_detected\n26          |reg19[0] == 1         |phy_tx_start\n27          |reg19[4] == 0         |long_preamble_detected\n27          |reg19[4] == 1         |phy_tx_done\n28          |reg19[8] == 0         |pkt_header_valid_strobe\n28          |reg19[8] == 1         |rssi_above_th\n29          |reg19[12] == 0        |pkt_header_valid_strobe&pkt_header_valid\n29          |reg19[12] == 1        |gain_change\n30          |reg19[16] == 0        |((fcs_in_strobe&addr2_match)&pkt_for_me)&is_data\n30          |reg19[16] == 1        |agc_lock\n31          |reg19[20] == 0        |(((fcs_in_strobe&fcs_ok)&addr2_match)&pkt_for_me)&is_data\n31          |reg19[20] == 1        |tx_pkt_need_ack\n\nNote: fcs_in_strobe means decoding is done (not necessarily CRC is correct); fcs_ok 1 means CRC correct; fcs_ok 0 means CRC not correct.\n\nNote: addr2_match means addr2 matches to the register (addr2_target) value; pkt_for_me means addr1 matches self mac addr; is_data means the packet type is data.\n\nConfiguration register:\n\nregister idx|meaning               |note\n------------|----------------------|-----------\n7           |addr2 target value    |fcs event always needs addr2 match\n9           |threshold for event rssi_above_th|check auto_lbt_th in ad9361_rf_set_channel of sdr.c to estimate a proper value\n\nNote: addr2 (source/sender's MAC address) target setting uses only 32bit. For address 6c:fd:b9:4c:b1:c1, you set b94cb1c1\n\nNote: read register 62 of xpu for some addr2 captured by the receiver\n"
  },
  {
    "path": "doc/app_notes/radar-self-csi.md",
    "content": "<!--\nAuthor: Xianjun jiao\nSPDX-FileCopyrightText: 2019 UGent\nSPDX-License-Identifier: AGPL-3.0-or-later\n-->\n\nOne super power of the openwifi platform is \"**Full Duplex**\" which means that openwifi baseband can receive its own TX signal. Just like a radar! This brings a unique capability of \"**joint radar and communication**\" to openwifi. For instance, put two directional antennas to openwifi TX and RX, and the **CSI** (Channel State Information) of the self-TX signal will refect the change of the target object.\n ![](./openwifi-radar.jpg)\n ![](./sensing.png)\n\n(See this https://github.com/open-sdr/openwifi/discussions/344 to understand how to map the collected data to the packet via the TSF timestamp)\n\n## Quick start\n- Power on the SDR board.\n- Connect a computer to the SDR board via Ethernet cable. The computer should have static IP 192.168.10.1. Open a terminal on the computer, and then in the terminal:\n  ```\n  ssh root@192.168.10.122\n  (password: openwifi)\n  ```\n- On computer, build the latest driver and FPGA package after clone/update openwifi and openwifi-hw-img repository:\n  ```\n  export XILINX_DIR=your_Xilinx_install_directory\n  (Example: export XILINX_DIR=/opt/Xilinx. The Xilinx directory should include sth like: Downloads, Vitis, etc.)\n  export OPENWIFI_HW_IMG_DIR=your_openwifi-hw-img_directory\n  (The directory where you get the open-sdr/openwifi-hw-img repo via git clone)\n  export BOARD_NAME=your_board_name\n  (Check the BOARD_NAME definitions in README)\n\n  cd openwifi/user_space\n  ./drv_and_fpga_package_gen.sh $OPENWIFI_HW_IMG_DIR $XILINX_DIR $BOARD_NAME\n  scp drv_and_fpga.tar.gz root@192.168.10.122:openwifi/\n  scp ./side_ch_ctl_src/side_ch_ctl.c root@192.168.10.122:openwifi/\n  scp ./inject_80211/* root@192.168.10.122:openwifi/inject_80211/\n  ```\n- On SDR board (/root/openwifi directory):\n  ```\n  cd /root/openwifi/\n  ./wgd.sh drv_and_fpga.tar.gz\n  ./monitor_ch.sh sdr0 1\n  insmod ./drv_and_fpga/side_ch.ko\n  gcc -o side_ch_ctl side_ch_ctl.c\n  ./side_ch_ctl wh1h4001\n  ./side_ch_ctl wh7h4433225a\n  (Above two commands ensure receiving CSI only from XX:XX:44:33:22:5a, which will be set by our own packet injector later)\n  ./sdrctl dev sdr0 set reg xpu 1 1\n  (Above unmute the baseband self-receiving to receive openwifi own TX signal/packet)\n  ./side_ch_ctl g0\n  ```\n- Open another ssh session on SDR board:\n  ```\n  cd /root/openwifi/inject_80211\n  make\n  ./inject_80211 -m g -r 4 -t d -e 0 -b 5a -n 99999999 -s 20 -d 1000 sdr0\n\n  (Above command injects the 802.11a/g packet, for 802.11n packet please use:\n  ./inject_80211 -m n -r 4 -t d -e 8 -b 5a -n 99999999 -s 20 -d 1000 sdr0)\n  ```\n- Now you should see the increasing numbers in the previous ssh terminal of the SDR board.\n- On your computer (NOT ssh session!), run:\n  ```\n  cd openwifi/user_space/side_ch_ctl_src\n  python3 side_info_display.py 8 waterfall\n  ```\n  You might need to install beforehand: \"sudo apt install python3-numpy python3-matplotlib python3-tk\". Now you should see figures showing run-time **CSI**, **CSI waterfall**, **Equalizer out** and **frequency offset**. The following photo shows the CSI change in the waterfall plot when I left my seat in front of two directional antennas (Tx/Rx antenna).\n  ![](./sensing.png)\n  \n  While running, all CSI data is also stored into a file **side_info.txt**. A matlab script **test_side_info_file_display.m** is offered to help you do CSI analysis offline. In this case, run **test_side_info_file_display** in Matlab.\n  ![](./csi-screen-shot-radar-matlab.jpg)\n  \nPlease learn the python and Matlab script for CSI data structure per packet according to your requirement.\n  \nDo read the [normal CSI app note](csi.md) to understand the basic implementation architecture.\n"
  },
  {
    "path": "doc/app_notes/subcarriers.png.license",
    "content": "# Author: Michael Mehari\n\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\n"
  },
  {
    "path": "doc/asic/skywater-130-pdk-and-asic-considerations.md",
    "content": "Hello,\r\n\r\nThe skywater PDK and free MPW shuttle are interesting.  And indeed we are asked many times to consider sky130 or other ASIC process MPW.\r\n\r\nWe do agree that building a real openwifi chip will probably (or not) mean a lot for the community, user and the world.\r\n\r\nBut, due to our limited bandwidth, currently we are focusing on making the openwifi IP more stable/mature/as-good-as COTS WiFi chip by using the FPGA verification platform, so we haven’t found time to take a look at a real WiFi chip design yet. \r\n\r\nWiFi chips could be as cheap as 0.5USD, but it doesn't mean the WiFi chip is simple. This is contrary to many people’s minds. I tried to explain the complexity of the WiFi chip in some videos, such as the FOSDEM and Libreplanet videos on this page: https://github.com/open-sdr/openwifi/blob/master/doc/videos.md . The WiFi chip is cheap only because they are sold so many per year. From this perspective, the WiFi chip is really an essential tiny thing of the modern world.\r\n\r\nBut we are definitely glad to support/answer-questions if someone else could jump in and do a solid analysis on the ASIC design effort. Some hints:\r\n\r\n1 . The info and communication hub is our github: https://github.com/open-sdr/openwifi . The FPGA code is in https://github.com/open-sdr/openwifi-hw .\r\n\r\n2 . The best way to get full picture and further info (resource/power/clock-speed/etc) of the openwifi FPGA design is downloading Xilinx Vivado (version is listed on our github) tool chain, and go through our full FPGA build procedure (README of openwifi-hw: https://github.com/open-sdr/openwifi-hw/blob/master/README.md ), where you will see the full system block diagram: not only the openwifi IP, but also all interfacing/peripheral IP around. Of course many of them are Xilinx/Analog-Devices specific.\r\n\r\n3 . You don’t need to pay any fee for Xilinx Vivado, if you chose the FPGA boards (the full list of supported FPGA board is in the README of openwifi: https://github.com/open-sdr/openwifi/blob/master/README.md ) that has 7020 FPGA, because Xilinx offer free offer for that small scale FPGA.\r\n\r\n4 . Try to find out all the vendor/3rd-part (Xilinx/Analog-Devices/etc) IPs, and evaluate/estimate how big the efforts will be if they need to be turned into sky130 or other ASIC design. As far as I remember (not full list), inside openwifi IP, we use these IP cores from Xilinx:\r\n- FFT\r\n- Viterbi decoder\r\n- FIFO\r\n- dual port RAM\r\n- ROM\r\n- FIR filter\r\n- AXI stream DMA\r\n- AXI lite bus\r\n- integer divider\r\n- integer multiplexer\r\n- etc. \r\n\r\nI guess most of them need to be ported if we go for a real chip. \r\n\r\n5 . Also outside openwifi IP, there are interfacing/peripheral IPs from Xilinx/Analog-Devices, which can be seen if you create and open the openwifi project block diagram in Vivado (follow the openwifi-hw README). Two special things: RF and ARM processor interconnection. \r\n- Currently the RF front-end is AD9361 (off-FPGA), which is not a dedicated WiFi front-end (2.4GH/5GHz only). Instead, AD9361 is a quite expensive front-end that supports 70M~6GHz for SDR (Software Defined Radio) applications. So of course, there will be dedicated AD9361 interfacing IPs from Analog Devices (open source as well: https://github.com/analogdevicesinc/hdl, but the license situation is complicated: https://github.com/analogdevicesinc/hdl/blob/master/LICENSE )\r\n- Unlike usual WiFi chips that work with processors via USB/PCIe/SDIO/etc bus, openwifi IP interconnects to the ARM processor via AXI bus. This brings us some unique benefits, such as low latency, but it also makes the IP quite platform dependent. \r\n\r\n6 . Last but not least, considering the efforts (seems big) needed for a real openwifi ASIC, we believe that some bigger/stronger organizations (like foundation/company/person), that have rich experience on IP/licensing analysis and ASIC design, could set up an initiative to work on this openwifi chip activity. Of course, we will be more than happy to join and support it. But to be honest, the openwifi team has very limited ASIC design experiences, and we mainly focus on FPGA for now (due to the bandwidth: personal resource, funding, etc.)\r\n\r\nFurther discussions/ideas? Feel free to reach out to us!\r\n\r\nBest regards,\r\n\r\nXianjun\r\n\r\n"
  },
  {
    "path": "doc/cite-openwifi-github-code.md",
    "content": "```\n@electronic{openwifigithub,\n            author = {Jiao, Xianjun and Liu, Wei and Mehari, Michael and Thijs, Havinga and Muhammad, Aslam and Chen, Baiheng},\n            title = {open-source IEEE802.11/Wi-Fi baseband chip/FPGA design},\n            url = {https://github.com/open-sdr},\n            year = {2023},\n}\n```\n"
  },
  {
    "path": "doc/cite-openwifi-vtc-paper.md",
    "content": "```\n@inproceedings{jiao2020openwifi,\n  title={openwifi: a free and open-source IEEE802. 11 SDR implementation on SoC},\n  author={Jiao, Xianjun and Liu, Wei and Mehari, Michael and Aslam, Muhammad and Moerman, Ingrid},\n  booktitle={2020 IEEE 91st Vehicular Technology Conference (VTC2020-Spring)},\n  pages={1--2},\n  year={2020},\n  organization={IEEE}\n}\n```\n"
  },
  {
    "path": "doc/img_build_instruction/kuiper.md",
    "content": "**IMPORTANT pre-conditions**:\n- Install Vivado 2022.2. Make sure install Vitis as well. You should have this directory: your_Xilinx_install_directory/Vitis (NOT Vitis_HLS!)\n  - If the Vitis is not installed, you can add it by running \"Xilinx Design Tools --> Add Design Tools for Devices 2022.2\" from Xilinx program group/menu in your OS start menu, or Help menu of Vivado.\n- SD card at least with 16GB\n- Install packages: `sudo apt install flex bison libssl-dev device-tree-compiler u-boot-tools -y`\n\n[[Use openwifi prebuilt img](#Use-openwifi-prebuilt-img)]\n[[Build SD card from scratch](#Build-SD-card-from-scratch)]\n[[Use existing SD card on new board](#Use-existing-SD-card-on-new-board)]\n\n## Use openwifi prebuilt img\n\nDownload openwifi pre-built img (see [Quick start](../../README.md#quick-start)), and extract it to .img file.\n\nUse dd command to flash the SD card. (Or other software like Startup Disk Creator in Ubuntu)\n```\nsudo dd bs=512 count=31116288 if=openwifi-xyz.img of=/dev/your_sdcard_dev\n```\nTo have correct count value, better to check the .img file actual situation by \"fdisk -l img_filename\" (check the number of sectors).\n\nThen start from the 2nd step of the [Quick start](../../README.md#quick-start) in README.\n\n## Build SD card from scratch\n\nDownload \"13 December 2023 release (2022_r2)\" (image_2023-12-13-ADI-Kuiper-full.zip) from https://wiki.analog.com/resources/tools-software/linux-software/kuiper-linux?redirect=1\n\nExtract it to .img file.\n\nUse dd command to flash the SD card. (Or other software like Startup Disk Creator in Ubuntu)\n```\nsudo dd bs=512 count=24182784 if=2023-12-13-ADI-Kuiper-full.img of=/dev/your_sdcard_dev\n```\n\n(To have correct count value, better to check the .img file actual situation by \"fdisk -l img_filename\" (check the number of sectors). While making .img from SD card, check the SD card dev instead)\n\nMount the BOOT and rootfs partition of SD card to your computer.\n\nChange the SD card file: Add following into rootfs/etc/network/interfaces\n```\n# The loopback interface\nauto lo\niface lo inet loopback\nauto eth0\niface eth0 inet static\n\n#your static IP\naddress 192.168.10.122\n\n#your gateway IP\ngateway 192.168.10.1\nnetmask 255.255.255.0\n\n#your network address \"family\"\nnetwork 192.168.10.0\nbroadcast 192.168.10.255\n```\n\nChange the SD card file: Add following into rootfs/etc/sysctl.conf\n```\nnet.ipv4.ip_forward=1\n```\n\nChange the SD card file: Add following into rootfs/etc/systemd/system.conf\n```\nDefaultTimeoutStopSec=2s\n```\n\nPut the openwifi/kernel_boot/10-network-device.rules into rootfs/etc/udev/rules.d/\n\nRun **update_sdcard.sh** from openwifi/user_space directory to further prepare the SD card. The last argument $SDCARD_DIR of the script is the directory (mounting point) on your computer that has BOOT and rootfs directories/partitions.\n\nThe script will build and put following things into the SD card:\n  - Linux kernel image file ([Update Driver](../../README.md#Update-Driver)): \n    - adi-linux-64/arch/arm64/boot/Image (64bit)\n    - adi-linux/arch/arm/boot/uImage (32bit)\n  - devicetree file:\n    - openwifi/kernel_boot/boards/zcu102_fmcs2/system.dtb (64bit)\n    - openwifi/kernel_boot/boards/$BOARD_NAME/devicetree.dtb (32bit)\n  - BOOT.BIN ([Update FPGA](../../README.md#Update-FPGA)):\n    - openwifi/kernel_boot/boards/$BOARD_NAME/output_boot_bin/BOOT.BIN\n  - openwifi driver ([Update Driver](../../README.md#Update-Driver)).\n  - openwifi/user_space files and openwifi/webserver files\n\nAfter **update_sdcard.sh** finishes, please do the 2nd step \"Config the correct files ...\" in [Quick start](../../README.md#quick-start). Then power on the board with the SD card, connect the board to your host PC (static IP 192.168.10.1) via ethernet, and ssh to the board with password **\"analog\"**\n```\nssh root@192.168.10.122\n```\n\nThen change password to \"openwifi\" via \"passwd\" command onbard.\n\nEnlarge the onboard SD disk space, and reboot (https://github.com/analogdevicesinc/adi-kuiper-gen/releases)\n```\nraspi-config --expand-rootfs\nreboot now\n```\nSetup routing/NAT **on the PC** for your board -- this internet connection is **important** for post installation/config.\n```\nsudo sysctl -w net.ipv4.ip_forward=1\nsudo iptables -t nat -A POSTROUTING -o NICY -j MASQUERADE\nsudo ip route add 192.168.13.0/24 via 192.168.10.122 dev ethX\n```\n**ethX** is the PC NIC name connecting the board ethernet. **NICY** is the PC NIC name connecting internet (WiFi or another ethernet).\n\nIf you want, uncommenting \"net.ipv4.ip_forward=1\" in /etc/sysctl.conf to make IP forwarding persistent on PC.\n\nTest the connectivity. Run on board (in the ssh session):\n```\nroute add default gw 192.168.10.1\nping IP_YOU_KNOW_ON_YOUR_NETWORK\n```\nIf there is issue with the connectivity (ping can not reach the target), it needs to be solved before going to the next step.\n\nDo misc configurations/installations in the ssh session onboard:\n```\n(You might need to set correct data and time by: date -s)\nsudo apt update\nchmod +x /root/openwifi/*.sh\n\n# install and setup dhcp server\nsudo apt-get -y install isc-dhcp-server\ncp /root/openwifi/dhcpd.conf /etc/dhcp/dhcpd.conf\n\n# install hostapd and other useful tools\nsudo apt-get -y install hostapd\nsudo apt-get -y install tcpdump\nsudo apt-get -y install webfs\nsudo apt-get -y install iperf\nsudo apt-get -y install iperf3\nsudo apt-get -y install libpcap-dev\nsudo apt-get -y install bridge-utils\n\n# build on board tools\nsudo apt-get -y install libnl-3-dev\nsudo apt-get -y install libnl-genl-3-dev\ncd /root/openwifi/sdrctl_src\nmake clean\nmake\ncp sdrctl ../\ncd /root/openwifi/side_ch_ctl_src/\ngcc -o side_ch_ctl side_ch_ctl.c\ncp side_ch_ctl ../\ncd /root/openwifi/inject_80211/\nmake clean\nmake\ncd ..\n```\n\nRun openwifi in the ssh session onboard:\n```\n/root/openwifi/setup_once.sh (Only need to run once for new board)\ncd /root/openwifi\n./wgd.sh\nifconfig sdr0 up\niwlist sdr0 scan\n./fosdem.sh\n```\n\n## Use existing SD card on new board\n\nJust operate the existing/working SD card of the old board on your computer starting from the 2nd step of the [Quick start](../../README.md#quick-start) in README. Then start using the SD card on the new board.\n"
  },
  {
    "path": "doc/known_issue/notter.md",
    "content": "# Known issue\n\n- [Network issue in quick start](#Network-issue-in-quick-start)\n- [EXT4 fs error rootfs issue](#EXT4-fs-error-rootfs-issue)\n- [EXT4 fs error rootfs issue while booting on zcu102](#EXT4-fs-error-rootfs-issue-while-booting-on-zcu102)\n- [antsdr e200 UART console](#antsdr-e200-UART-console)\n- [Client can not get IP](#Client-can-not-get-IP)\n- [No space left on device](#No-space-left-on-device)\n- [Ping issue due to hostname resolving issue caused by DNS server change](#Ping-issue-due-to-hostname-resolving-issue-caused-by-DNS-server-change)\n- [FMCOMMS board eeprom issue causes Linux crash](#FMCOMMS-board-eeprom-issue-causes-Linux-crash)\n- [Not booting due to SPI flash](#Not-booting-due-to-SPI-flash)\n- [Kernel compiling issue like GCC plugins](#Kernel-compiling-issue-like-GCC-plugins)\n- [Missing libidn.so.11 while run boot_bin_gen.sh](#Missing-libidn.so.11-while-run-boot_bin_gen.sh)\n- [Zcu102 booting kernel panic due to RTC](#Zcu102-booting-kernel-panic-due-to-RTC)\n- [Kernel panic due to hardware capacitor and current load](#Kernel-panic-due-to-hardware-capacitor-and-current-load)\n- [lightdm memory leakage leads to issue after long run](#lightdm-memory-leakage-leads-to-issue-after-long-run)\n- [Wrong memory size on adrv9361z7035 SoM](#Wrong-memory-size-on-adrv9361z7035-SoM)\n- [Unsupported PRODUCT_ID 0xFF](#Unsupported-PRODUCT_ID-0xFF)\n\n## Network issue in quick star\n\n- OS: Ubuntu 22 LTS\n- image: [openwifi img](https://drive.google.com/file/d/1fb8eJGJAntOciCiGFVLfQs7m7ucRtSWD/view?usp=share_link)\n\nIf can't ssh to the board via Ethernet for the 1st time, you might need to delete /etc/network/interfaces.new on SD card (on your computer).\n\nIf still can't ssh the board via Ethernet, you should use UART console (/dev/ttyUSBx, /dev/ttyCH341USBx, etc.) to monitor what happened during booting.\n\n## EXT4 fs error rootfs issue\n\nSometimes, the 1st booting after flashing SD card might encounter \"EXT4-fs error (device mmcblk0p2): ...\" error on neptunesdr, changing SD card flashing tool might solve this issue. Some tool candidates:\n- gnome-disks\n- Startup Disk Creator\n- win32diskimager\n\n## EXT4 fs error rootfs issue while booting on zcu102\n\nIssue description: same SD card can boot normally on some zcu102 boards but not on some boards else.\n\nMany reportings on internet (while booting zcu102):\n```\nKernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(179,2)\n...\n---[ end Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(179,2) ]---\n```\n\nNeed to add following blocks into the mmc entry or sdhci entry of the zcu102 devicetree:\n```\nxlnx,has-cd = <0x1>;\nxlnx,has-power = <0x0>;\nxlnx,has-wp = <0x1>;\ndisable-wp;\nno-1-8-v;\nbroken-cd;\nxlnx,mio-bank = <1>;\n/* Do not run SD in HS mode from bootloader */\nsdhci-caps-mask = <0 0x200000>;\nsdhci-caps = <0 0>;\nmax-frequency = <19000000>;\n```\nSuspect the main reason: sdcard speed needs to be limited by above.\n\nMight be due to that the sd card interface degrades and becomes unstable after years.\n\n## antsdr e200 UART console\n\nIf can't see the UART console in Linux (/dev/ttyUSB0 or /dev/ttyCH341USB0), according to https://github.com/juliagoda/CH341SER, you might need to do `sudo apt remove brltty`\n\n## Client can not get IP\n\nIf the client can not get IP from the openwifi AP, just re-run \"service isc-dhcp-server restart\" on board and do re-connect from the client.\n\n## No space left on device\nIt might be due to too many dmesg/log/journal, disk becomes full. \n```\nsystemd-journald[5694]: Failed to open system journal: No space left on device\n```\nYou can try following operations.\n```\nsystemd-tmpfiles --clean\nsudo systemd-tmpfiles --remove\nrm /var/log/* -rf\napt --autoremove purge rsyslog\n```\nAdd followings into `/etc/systemd/journald.conf`\n```\nSystemMaxUse=64M\nStorage=volatile\nRuntimeMaxUse=64M\nForwardToConsole=no\nForwardToWall=no\n```\n\n## Ping issue due to hostname resolving issue caused by DNS server change\n\nYou might need to change nameserver to 8.8.8.8 in /etc/resolv.conf on board.\n\n## FMCOMMS board eeprom issue causes Linux crash\n\nSome FMCOMMS2/3/4/x boards shipped with wrong/empty eeprom, so that on some platform (like ZCU102) it causes issues like Linux crash. You can follow https://github.com/analogdevicesinc/fru_tools to reprogram the eeprom.\n- Insert the FMCOMMS board on a platform (such as 32bit zed/zc706/zc702/etc) that can boot and boot into Linux\n- On board Linux:\n  ```\n  git clone https://github.com/analogdevicesinc/fru_tools.git\n  cd fru_tools/\n  make\n  find /sys -name eeprom\n  (It might return like: /sys/devices/soc0/fpga-axi@0/41620000.i2c/i2c-0/0-0050/eeprom)\n  fru-dump -i /sys/devices/soc0/fpga-axi@0/41620000.i2c/i2c-0/0-0050/eeprom -b\n  ```\n- If there is issue, you will see some \"mismatch\" warning like:\n  ```\n  read 256 bytes from /sys/devices/soc0/fpga-axi@0/41620000.i2c/i2c-0/0-0050/eeprom\n  fru_dump 0.8.1.7, built 04Aug2022\n  FRU Version number mismatch 0xff should be 0x01\n  ```\n- To reprogram the eeprom (FMCOMMS4 as an example):\n  ```\n  fru-dump -i ./masterfiles/AD-FMCOMMS4-EBZ-FRU.bin -o /sys/devices/soc0/fpga-axi@0/41620000.i2c/i2c-0/0-0050/eeprom\n  ```\n- Reboot the board, and try to read eeprom again, correct information should be shown like:\n  ```\n  fru-dump -i /sys/devices/soc0/fpga-axi@0/41620000.i2c/i2c-0/0-0050/eeprom -b\n  read 256 bytes from /sys/devices/soc0/fpga-axi@0/41620000.i2c/i2c-0/0-0050/eeprom\n  Date of Man\t: Mon Jul 22 20:23:00 2013\n  Manufacturer\t: Analog Devices\n  Product Name\t: AD9364 RF Eval/Software Dev Kit\n  Serial Number\t: 00045\n  Part Number\t: AD-FMCOMMS4-EBZ\n  FRU File ID\t: Empty Field\n  PCB Rev \t: C\n  PCB ID  \t: FMCOMMSFMC04A\n  BOM Rev \t: 1\n  ```\n\n## Not booting due to SPI flash\n\nBefore loading content on SD card, the on board SPI flash controls some configurations, such as the kernel file and AD9361 crystal frequency (ad9361_ext_refclk=0x2625a8b). When (suspect) there is an issue, the SPI flash can be restored to default by interrupting booting (hitting enter before Linux loading in the UART console), then\n```\nZynq> env default -a\n## Resetting to default environment\nZynq> saveenv\nSaving Environment to SPI Flash...\nSF: Detected n25q256a with page size 256 Bytes, erase size 4 KiB, total 32 MiB\nErasing SPI flash...Writing to SPI flash...done\n```\n\n## Kernel compiling issue like GCC plugins\n\nSometimes after the GNU/GCC tool chain update in the host PC or the slightly kernel update (such as 5.15.0 --> 5.15.36), it might prompt user to select among some new options while compiling kernel like:\n```\n...\nXen guest support on ARM (XEN) [N/y/?] n\nUse a unique stack canary value for each task (STACKPROTECTOR_PER_TASK) [Y/n/?] (NEW) n\n*\n* GCC plugins\n*\nGCC plugins (GCC_PLUGINS) [Y/n/?] (NEW) n\n...\n```\nIn these cases, the best/safest way is to chose **n** and **weakest** options. Otherwise the compiling might fail or potential issues might happen.\n\n## Missing libidn.so.11 while run boot_bin_gen.sh\n\nYou might need to prepare/fake libidn.so.11 by\n```\nsudo ln -s  /usr/lib/x86_64-linux-gnu/libidn.so.12.6.3 /usr/lib/x86_64-linux-gnu/libidn.so.11\n```\nPlease check/confirm what is the exact **libidn.so.12.6.3** in your system.\n\n## Zcu102 booting kernel panic due to RTC\n\nhttps://github.com/open-sdr/openwifi/issues/366\n\n## Kernel panic due to hardware capacitor and current load\n\nhttps://github.com/open-sdr/openwifi/issues/457\n\n## lightdm memory leakage leads to issue after long run\n\nBetter to disable lightdm via systemctl\n\n## Wrong memory size on adrv9361z7035 SoM\n\nhttps://github.com/open-sdr/openwifi/issues/404 reports that Linux only sees half memory size than the actual DDR memory size in the hardware.\n\nThe root cause is the old/wrong u-boot.elf hard coded the memory size as 512MB. It is already fixed to the correct 1GB (0x40000000): https://github.com/analogdevicesinc/u-boot-xlnx/blob/master/arch/arm/dts/zynq-adrv9361.dts\n\nThe solution is re-building u-boot.elf from https://github.com/analogdevicesinc/u-boot-xlnx and re-generating BOOT.BIN for adrv9361z7035 SoM.\n\nSteps to re-build u-boot.elf for adrv9361z7035 SoM:\n\n```\ngit clone https://github.com/analogdevicesinc/u-boot-xlnx.git\ncd u-boot-xlnx\nsource environment_setting.sh (could be XILINX_DIR/Vitis/2022.2/settings64.sh or directory of your tool chain)\nexport ARCH=arm\nexport CROSS_COMPILE=arm-linux-gnueabihf-\nmake zynq_adrv9361_defconfig\nmake -j8\nmake u-boot.elf\n```\n\n## Unsupported PRODUCT_ID 0xFF\n\nhttps://ez.analog.com/microcontroller-no-os-drivers/f/q-a/101813/ad9361-spi32766-0-ad9361_probe-unsupported-product_id-0xff/303302\n\nhttps://wiki.analog.com/resources/tools-software/linux-software/fru_dump\n\n"
  },
  {
    "path": "doc/openwifi-detail.jpg.license",
    "content": "\n# Author: Xianjun jiao\n\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n"
  },
  {
    "path": "doc/publications.md",
    "content": "<!--\nAuthor: Xianjun jiao\nSPDX-FileCopyrightText: 2021 UGent\nSPDX-License-Identifier: AGPL-3.0-or-later\n-->\n\nIf openwifi is one of your references, please cite the VTC2020 paper: [LaTex example](cite-openwifi-vtc-paper.md)\n\nYou can also cite openwifi github code: [LaTex example](cite-openwifi-github-code.md).\n\nPublications in category:\n- [Feature Functionality and System](#Feature-Functionality-and-System)\n- [TSN Time Sensitive Network and RT Real Time](#TSN-Time-Sensitive-Network-and-RT-Real-Time)\n- [CSI Sensing and Security](#CSI-Sensing-and-Security)\n- [WiFi and Cellular 5G 6G](#WiFi-and-Cellular-5G-6G)\n\n## Feature Functionality and System\n- [Xianjun Jiao, et al. openwifi: a free and open-source IEEE802.11 SDR implementation on SoC. VTC2020 spring Antwerp](https://www.orca-project.eu/wp-content/uploads/sites/4/2020/03/openwifi-vtc-antwerp-PID1249076.pdf)\n- [Cedric Den Haese, The initial 802.11n 2*2 MIMO and diversity (CSD/Combining) work. UGent master thesis 2021](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/Cedric_Den_Haese_masterproef.pdf)\n- [Paul Zanna, et al. A novel method for utilizing RF information from IEEE 802.11 frames in Software Defined Networks. MethodsX 2021](https://www.sciencedirect.com/science/article/pii/S2215016121003368)\n- [Thijs Havinga, et al. WIP: Achieving Self-Interference-Free Operation on SDR Platform with Critical TDD Turnaround Time. WoWMoM 2022](http://hdl.handle.net/1854/LU-8765231)\n- [Yingshuo Xi, Baiming Zhang. High-Throughput Open Source Viterbi Decoder for OpenWiFi. 2022 KU Leuven master thesis](https://github.com/BaimingZhang26213/viterbi_decoder)\n- [Merkebu Girmay, et al. Technology recognition and traffic characterization for wireless technologies in ITS band. Vehicular Communications Volume 39, February 2023, 100563](https://doi.org/10.1016/j.vehcom.2022.100563)\n- [Thijs Havinga, et al. Accelerating FPGA-Based Wi-Fi Transceiver Design and Prototyping by High-Level Synthesis. FCCM 2023](http://hdl.handle.net/1854/LU-01H54J3830HK78ZDAH29ZEDJHY), [[Longer/detailed info about the poster](https://arxiv.org/abs/2305.13351)]\n- [Merkebu Girmay, et al. Intelligent Spectrum Sharing Between LTE and Wi-Fi Networks using Muted MBSFN Subframes. WAMICON 2023](https://ieeexplore.ieee.org/abstract/document/10124903)\n- [Thijs Havinga, et al. Improved TDD operation on Software-Defined Radio platforms towards future wireless standards. Computer Communications, Volume 209, 1 September 2023, Pages 178-187](https://doi.org/10.1016/j.comcom.2023.06.026)\n- [Yuyang Du, et al. The Power of Large Language Models for Wireless Communication System Development: A Case Study on FPGA Platforms. arxiv, Submitted on 14 Jul 2023 (v1), last revised 5 Sep 2023 (this version, v2)](https://arxiv.org/abs/2307.07319)\n- [Muhammad Aslam, et al. A novel hardware efficient design for IEEE 802.11ax compliant OFDMA transceiver](https://www.sciencedirect.com/science/article/pii/S0140366424000926?dgcid=coauthor)\n- [Trio Adiono, et al. FPGA Implementation of SFO for OFDM-based Network Enabled Li-Fi System. IEEE ISCAS 2024](https://ieeexplore.ieee.org/abstract/document/10557957)\n- [Trio Adiono, et al. A Scalable Design of A Full-Stack Real-Time OFDM Baseband Processor for Network-Enabled VLC Systems. IEEE Access 2024](https://ieeexplore.ieee.org/document/10589620)\n- [Roni Fagerholm, FPGA-based DECT-2020 New Radio Packet Detection. Master thesis, Aalto University, 30 September 2024](https://aaltodoc.aalto.fi/server/api/core/bitstreams/a5105c46-f4c6-4034-8024-96ed9e440feb/content)\n- [Hao Zhou, et al. Large Language Model (LLM) for Telecommunications: A Comprehensive Survey on Principles, Key Techniques, and Opportunities. IEEE Communications Surveys & Tutorials 2024](https://ieeexplore.ieee.org/document/10685369)\n- [Thijs Havinga, et al. Experimental Study Towards Efficient Interference Avoidance Using Wi-Fi 6 OFDMA on SDR, IEEE INFOCOM 2024](https://ieeexplore.ieee.org/document/10620761)\n- [Thijs Havinga, et al. Wi-Fi 6 Cross-Technology Interference Detection and Mitigation by OFDMA: an Experimental Study. EuCNC & 6G Summit 2025](http://hdl.handle.net/1854/LU-01JZ0477NE4D3DQV6R8JCCBFJB)\n- [Shyam Krishnan Venkateswaran, et al. Target wake time in IEEE 802.11 WLANs: Survey, challenges, and opportunities. Computer Communications, 2025](https://www.sciencedirect.com/science/article/pii/S0140366425000842)\n- [Baiheng Chen, et al. An Experimental Study of Wi-Fi Joint Transmission With Multiple Openwifi Access Points, IEEE WCNC, 2025](https://ieeexplore.ieee.org/document/10978612)\n- [Maksymilian, et al. Coordinated Spatial Reuse Scheduling With Machine Learning in IEEE 802.11 MAPC Networks. arXiv 2025](https://arxiv.org/abs/2505.07278), [Slides on IEEE 802.11 standardization conf, Warsaw, 2025](https://mentor.ieee.org/802.11/dcn/25/11-25-0710-01-aiml-mapc-c-sr-scheduling-with-multi-armed-bandits-revisited.pptx)\n- [Yanzhuo Yu, et al. DOA System Based on an Eight-Channel Circular Array and Wi-Fi, Proceedings of the 3rd International Conference on Internet of Things, Communication and Intelligent Technology, 27 May 2025](https://link.springer.com/chapter/10.1007/978-981-96-2767-7_37)\n- [Thijs, et al. Fine-Grained Coordinated OFDMA With Fiber Backhaul Enabled by openwifi and White Rabbit, Best paper award, ACM (mobicom) WiNTECH 2025.](https://arxiv.org/abs/2507.10210)\n- [Robbe Gaeremynck, et al.Openwifi and sub-20 MHz Co-OFDMA. WNG (Wireless Next Generation) SC, IEEE 802 Plenary session, Madrid, Spain, July 27 – August 1, 2025](https://mentor.ieee.org/802.11/dcn/25/11-25-1039-00-0wng-openwifi-and-sub-20-mhz-co-ofdma.pptx)\n- [Thijs, et al. Cross-Technology Interference awareness for multi-user OFDMA scheduling in IEEE 802.11ax, Ad Hoc Networks, Volume 181, 104057, 1 February 2026](https://doi.org/10.1016/j.adhoc.2025.104057)\n- [Yibin Shen, et al. Law: Towards Consistent Low Latency in 802.11 Home Networks, USENIX NSDI 2026](https://zilimeng.com/papers/law-nsdi26.pdf)\n- [Thijs, Flexible and Real-Time Interference Mitigation Techniques for Reliable Wireless Communication Using Software-Defined Radio, PhD dissertation, Gent University, 2025](http://hdl.handle.net/1854/LU-01KC11QRHFPRGD3WA9YQFSA7RZ)\n- [Holger Santillan-Carranza, et al. FPGA-Based Simulation of Open Wi-Fi Service Using the Analog Devices SDR Platform, INGENIO 9(1):26-33, January 2026](https://www.researchgate.net/publication/400217316_FPGA-Based_Simulation_of_Open_Wi-Fi_Service_Using_the_Analog_Devices_SDR_Platform)\n- [Yuhao Chen et al. WiLD: Learning-based Wireless Loss Diagnosis for Congestion Control with Ultra-low Kernel Overhead, IEEE Transactions on Network and Service Management, 13 February 2026](https://ieeexplore.ieee.org/abstract/document/11396390)\n\n## TSN Time Sensitive Network and RT Real Time\n- [Jetmir Haxhibeqiri, et al. Enabling TSN over IEEE 802.11: Low-overhead Time Synchronization for Wi-Fi Clients. ICIT2021](https://biblio.ugent.be/publication/8700714/file/8700715.pdf)\n- [Ingrid Moerman, et al. Wireless Time-Sensitive Networks: When Every Microsecond Counts. Microwaves&RF, 2021](https://www.mwrf.com/technologies/systems/article/21164984/wireless-timesensitive-networks-when-every-microsecond-counts)\n- [Muhammad Aslam, et al. High precision time synchronization on Wi-Fi based multi-hop network. CNERT2021](https://biblio.ugent.be/publication/8709058/file/8709060.pdf)\n- [Ingrid Moerman, et al. Interoperable Time-Sensitive Networking Towards 6G (invited presentation)](https://biblio.ugent.be/publication/8719532/file/8719533.pdf)\n- [Lihao Zhang, et al. A Just-In-Time Networking Framework for Minimizing Request-Response Latency of Wireless Time-Sensitive Applications. IEEE Internet of Things Journal, Volume: 10, Issue: 8, 15 April 2023](https://ieeexplore.ieee.org/document/9984846)\n- [Jetmir Haxhibeqiri, et al. Enabling TSN over IEEE 802.11: Low-overhead Time Synchronization for Wi-Fi Clients. 22nd IEEE International Conference on Industrial Technology (ICIT) 2021](https://ieeexplore.ieee.org/document/9453686)\n- [Jetmir Haxhibeqiri, et al. Bringing Time-Sensitive Networking to Wireless Professional Private Networks. Wireless Personal Communications 2021](https://link.springer.com/article/10.1007/s11277-021-09056-0)\n- [Muhammad Aslam, et al. Hardware Efficient Clock Synchronization across Wi-Fi and Ethernet Based Network Using PTP. IEEE Transactions on Industrial Informatics 2021](https://ieeexplore.ieee.org/document/9573364)\n- [Zelin Yun, et al. RT-WiFi on Software-Defined Radio: Design and Implementation. RTAS 2022 paper and demo](https://ieeexplore.ieee.org/document/9804669)\n- [Pablo Avila-Campos, et al. Beacon-Based Wireless TSN Association. 2022 IEEE INFOCOM](https://imec-publications.be/bitstream/handle/20.500.12860/40111/8126_acc.pdf?sequence=2)\n- [Pablo Avila-Campos, et al. Impactless Beacon-Based Wireless TSN Association Procedure. 2022 IEEE 18th International Conference on Factory Communication Systems (WFCS)](https://ieeexplore.ieee.org/abstract/document/9779186)\n- [Jetmir Haxhibeqiri, et al. Safety-related Applications over Wireless Time-Sensitive Networks. IEEE ETFA 2022](https://biblio.ugent.be/publication/8770625/file/8770627.pdf)\n- [Pablo Avila-Campos, et al. Removing the Wires in Time-Sensitive Networks. 2022 61st FITCE International Congress Future Telecommunications: Infrastructure and Sustainability (FITCE)](https://ieeexplore.ieee.org/abstract/document/9934268)\n- [Pablo Avila-Campos, et al. Periodic Control Traffic Support in a Wireless Time-Sensitive Network. 2022 13th International Conference on Network of the Future (NoF)](https://ieeexplore.ieee.org/document/9942586)\n- [Gilson Miranda, et al. The Quality-Aware and Vertical-Tailored Management of Wireless Time-Sensitive Networks. IEEE Internet of Things Magazine ( Volume: 5, Issue: 4, December 2022)](https://ieeexplore.ieee.org/abstract/document/10012491)\n- [Gilson Miranda, et al. Enabling Time-Sensitive Network Management Over Multi-Domain Wired/Wi-Fi Networks. IEEE Transactions on Network and Service Management, 2023)](https://ieeexplore.ieee.org/document/10121738)\n- [Jetmir Haxhibeqiri, et al. To update or not: Dynamic traffic classification for high priority traffic in wireless TSN. IEEE WFCS2023](http://hdl.handle.net/1854/LU-01GZNGJFAJQRM3NX7FY5VRB4MR)\n- [Pablo Avila-Campos, et al. Residual Service Time Optimization for legacy Wireless-TSN end nodes. 2023 19th International Conference on Wireless and Mobile Computing, Networking and Communications (WiMob). p.466-471](https://ieeexplore.ieee.org/document/10187722)\n- [Dirk Dahlhaus, et al. Towards Functional Safety in Dynamic Distributed Systems. Journal of Mobile Multimedia, Vol. 20 1, 1–24.](https://biblio.ugent.be/publication/01HGD7JAZY0YAQ1T13HQV35JC0/file/01HGD7PD2WRP9QW7J1G964Z6Y7.pdf)\n- [Kouros Zanbour, et al. A Comprehensive Survey of Wireless Time-Sensitive Networking (TSN): Architecture, Technologies, Applications, and Open Issues. arXiv, 2 Dec 2023](https://arxiv.org/abs/2312.01204)\n- [Jetmir Haxhibeqiri, et al. Coordinated Spatial Reuse for WiFi Networks: A Centralized Approach. IEEE 20th International Conference on Factory Communication Systems (WFCS) 2024](https://ieeexplore.ieee.org/document/10540785/)\n- [Jetmir Haxhibeqiri, et al. Coordinated SR and Restricted TWT for Time Sensitive Applications in WiFi 7 Networks. IEEE Communications Magazine 2024](https://ieeexplore.ieee.org/document/10634074/)\n- [Ozgur Ozkaya, et al. Simulating and Validating openwifi W-TSN in ns-3, IEEE 20th International Conference on Factory Communication Systems (WFCS) 2024](https://ieeexplore.ieee.org/document/10540899)\n- [Pablo Avila-Campos, et al. Impactless association methods for wi-fi based time-sensitive networks. Wireless Networks Journal, 2024](https://dl.acm.org/doi/10.1007/s11276-024-03681-w)\n- [Pablo Avila-Campos, et al. Unlocking Mobility for Wi-Fi-based Wireless Time-Sensitive Networks. IEEE Access, 2024](https://ieeexplore.ieee.org/document/10443947)\n- [Analog Devices, AN-2597: An OFDM-Based HDL Reference Modem Using the AD936x RF Transceivers. November, 2024](https://www.analog.com/en/resources/app-notes/an-2597.html)\n- [Tianyu Zhang, et al. A Survey on Industrial Internet of Things (IIoT) Testbeds for Connectivity Research. arXiv 2024](https://arxiv.org/abs/2404.17485)\n- [Louis Adriaens, High-Precision Wireless Synchronization: When Wi-Fi meets UWB. IEEE/SICE International Symposium on System Integration (SII) 2025](https://ieeexplore.ieee.org/document/10870915)\n- [Yongchao Dang, Open Radio Intelligent Controller based Wireless Time Sensitive Networking for Industry 5.0. TechRxiv 2025](https://www.techrxiv.org/doi/full/10.36227/techrxiv.173750009.95972083)\n- [Pablo Avila-Campos, et al. Traffic Pattern-Based Scheduling for Wireless Non-TSN End Nodes. 2025 IEEE 21st International Conference on Factory Communication Systems (WFCS)](https://ieeexplore.ieee.org/document/11077621)\n- [S. Xu and L. Zhang, et al. A Hybrid TDMA/CSMA Protocol for Time-Sensitive Traffic in Robot Applications. arXiv, Sep. 2025](https://arxiv.org/abs/2509.06119v1)\n- [Ingrid Moerman, et al. Deterministic communications - An end-to-end system point of view (invited presentation). Symposium on Future Network/6G challenges, Future Networks World Forum 2025](http://hdl.handle.net/1854/LU-01K9YE9V3NNKFTBDBW1D09EM6A)\n- [Ingrid Moerman, et al. The role of wireless in end-to-end Deterministic Connected Systems. Plenary talk at Workshop on Communication Networks and Power Systems, 28 Nov. 2025 (WCNPS’25)](http://hdl.handle.net/1854/LU-01KBCXDFS273CRGHB8TZTS8YB8)\n- [Jetmir Haxhibeqiri, et al. Distributed Multi-link Operation (MLO) for Frame Replication in Wireless Time-Sensitive Networking. The 8th International Conference on Advanced Communication Technologies and Networking (CommNet) 2025](https://ieeexplore.ieee.org/abstract/document/11288880)\n\n## CSI Sensing and Security\n- [Marco Cominelli, et al. CSI MURDER. ORCA project opencall 2019](https://ans.unibs.it/projects/csi-murder/)\n- [Marco Cominelli, et al. IEEE 802.11 CSI randomization to preserve location privacy: An empirical evaluation in different scenarios. ELSEVIER Computer Networks, 2021](https://www.sciencedirect.com/science/article/abs/pii/S138912862100102X)\n- [Xianjun Jiao, et al. Openwifi CSI fuzzer for authorized sensing and covert channels. ACM WiSec 2021](https://dl.acm.org/doi/pdf/10.1145/3448300.3468255)\n- [Hongjian Cao, et al. OWFuzz: WiFi Protocol Fuzzing Tool Based on OpenWiFi. Blackhat asia 2021](https://www.blackhat.com/asia-21/arsenal/schedule/#owfuzz-wifi-protocol-fuzzing-tool-based-on-openwifi-22569), [[**code**]](https://github.com/alipay/Owfuzz)\n- [Steven Heijse, IEEE 802.11 Physical Layer Fuzzing Using OpenWifi. UGent master thesis 2021](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/Steven_Heijse_masterproef.pdf)\n- [Jasper Devreker, Developing IEEE 802.11 PHY fuzzing capabilities using the open source Openwifi project. UGent master thesis 2022](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/Jasper_Devreker_masterproef.pdf)\n- [Thomas Schuddinck, Cybersecurity: Breaking IEEE 802.11 Devices at the Physical Layer. UGent master thesis 2022](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/Thomas_Schuddinck_masterproef.pdf)\n- [Seppe Dejonckheere, The design of a CSI sensing authorisation mechanism using the open source Openwifi project. UGnet master thesis 2022](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/Seppe_Dejonckheere_masterproef.pdf)\n- [Marco Cominelli, et al. On the properties of device-free multi-point CSI localization and its obfuscation. ELSEVIER Computer Communications, 2022](https://www.sciencedirect.com/science/article/pii/S014036642200086X)\n- [Renato Lo Cigno, et al. Integrating CSI Sensing in Wireless Networks: Challenges to Privacy and Countermeasures. IEEE Network, 2022](https://ieeexplore.ieee.org/document/9919763)\n- [Renato Lo Cigno, et al. AntiSense: Standard-compliant CSI obfuscation against unauthorized Wi-Fi sensing. ELSEVIER Computer Communications, 2022](https://www.sciencedirect.com/science/article/pii/S0140366421004916)\n- [Mathy Vanhoef, et al. Testing and Improving the Correctness of Wi-Fi Frame Injection. ACM WiSec 2023](https://papers.mathyvanhoef.com/wisec2023-wifi-injection.pdf)\n- [Wen Liu, et al. A New Paradigm for Device-free Indoor Localization: Deep Learning with Error Vector Spectrum in Wi-Fi Systems. PIMRC 2023](https://arxiv.org/pdf/2304.06490.pdf)\n- [Paul Zanna, et al. Preventing Attacks on Wireless Networks Using SDN Controlled OODA Loops and Cyber Kill Chains. Sensors 2022, 22(23), 9481](https://www.mdpi.com/1986552)\n- [Hayoung Seong, et al. Practical Covert Wireless Unidirectional Communication in IEEE 802.11 Environment, IEEE Internet of Things Journal ( Volume: 10, Issue: 2, 15 January 2023)](https://ieeexplore.ieee.org/abstract/document/9881568)\n- [Fan Qi, et al. Deep Learning-based CSI Feedback in Wi-Fi Systems, arxiv, 2024](https://arxiv.org/pdf/2407.05905)\n- [Lorenzo Ghiro, et al. Wi-Fi Localization Obfuscation: An implementation in openwifi. ELSEVIER Computer Communications, 2023](http://www.sciencedirect.com/science/article/pii/S0140366423001111)\n- [Andreas Toftegaard Kristensen, et al. Monostatic Multi-Target Wi-Fi-Based Breathing Rate Sensing Using Openwifi, IEEE Wireless Communications and Networking Conference (WCNC) 2024](https://ieeexplore.ieee.org/document/10570912)\n- [Andreas Toftegaard Kristensen, et al. An SDR-Based Monostatic Wi-Fi System with Analog Self-Interference Cancellation for Sensing, arXiv, 11 DEC 2024](https://arxiv.org/abs/2412.08612) [[**block diagram**](AnSIC-sensing-correction.png)]\n- [Jesus A. Armenta-Garcia, et al. Wireless sensing applications with Wi-Fi Channel State Information, preprocessing techniques, and detection algorithms: A survey. Computer Communications Volume 224, 1 August 2024](https://www.sciencedirect.com/science/article/abs/pii/S0140366424002214?via%3Dihub)\n- [Tianyang Zhang, et al. Privacy Protection in WiFi Sensing via CSI Fuzzing, 2024 IEEE/ACM Symposium on Edge Computing (SEC), 04-07 December 2024](https://ieeexplore.ieee.org/abstract/document/10818006)\n- [Xianjun Jiao, et al. Single-Input-Multiple-Output Wi-Fi Radar for Vital Signal Sensing and Device Tracking, IEEE 5th International Symposium on Joint Communications & Sensing (JC&S) 2025](https://biblio.ugent.be/publication/01JMVPSR8AR08RRW9MC15FPF58)\n- [Renato Lo Cigno, et al. Communication and Sensing: Wireless PHY-Layer Threats to Security and Privacy for IoT Systems and Possible Countermeasures. information, MDPI, 2025](https://www.mdpi.com/2078-2489/16/1/31)\n- [Zhiming Chu, et al. Defeating CSI obfuscation mechanisms: A study on unauthorized Wi-Fi Sensing in wireless sensor network. Computer Networks, Volume 263, May 2025](https://www.sciencedirect.com/science/article/abs/pii/S1389128625001768)\n- [Xinyu Liu, et al. Integration of Person Identification and Respiratory Monitoring Based on Reconfigurable Intelligent Surface. IEEE Sensors Journal, 06 June 2025](https://ieeexplore.ieee.org/abstract/document/11027648)\n- [Zhiming Chu, et al. Privacy-preserving WiFi sensing in WSNs via CSI obfuscation. Computers & Security Volume 157, October 2025, 104594](https://doi.org/10.1016/j.cose.2025.104594)\n- [Stepan Mazokha, et al. Real-time Device Fingerprinting and Re-identification in GNUradio, Proceedings of the 15th GNU Radio Conference, 2025](https://events.gnuradio.org/event/26/contributions/773/attachments/229/665/gr-mobrffi_paper_v1.2.pdf)\n\n## WiFi and Cellular 5G 6G\n- [Luca Baldesi, et al. ChARM: NextG Spectrum Sharing Through Data-Driven Real-Time O-RAN Dynamic Control. INFOCOM 2022](https://ece.northeastern.edu/wineslab/papers/BaldesiInfocom22.pdf)\n- [Christian Arendt, et al. Empowering the Convergence of Wi-Fi and 5G for Future Private 6G Networks. 28th European Wireless Conference 2023](https://ieeexplore.ieee.org/document/10461434)\n- [Liangdong Wei, et al. An Experimental Evaluation of ACK-based Passive Bandwidth Estimation Methods in Ad Hoc Networks, 9th International Conference on Computer and Communications (ICCC) 2023](https://ieeexplore.ieee.org/document/10507541)\n\n**Openwifi was born in ORCA project (EU's Horizon2020 programme under agreement number 732174).**\n"
  },
  {
    "path": "doc/rf-digital-if-chain-config.jpg.license",
    "content": "\n# Author: Xianjun jiao\n\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n"
  },
  {
    "path": "doc/rf-digital-if-chain-spectrum.jpg.license",
    "content": "\n# Author: Xianjun jiao\n\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n"
  },
  {
    "path": "doc/videos.md",
    "content": "- The 1st public demo video [[Youtube](https://youtu.be/NpjEaszd5u4)], [[link for CHN user](https://www.zhihu.com/zvideo/1280659393378041856)]\n- FOSDEM2020 presentation [[Youtube](https://youtu.be/Mq48cGthk7M)], [[link for CHN user](https://www.zhihu.com/zvideo/1280673506397425664)]\n- Low latency for gaming and general introduction [[Youtube](https://youtu.be/Notn9X482LI)], [[link for CHN user](https://www.zhihu.com/zvideo/1273823153371385856)]\n- CSI (Channel State Information) [[Youtube](https://youtu.be/DanB1ClVamU)], [[link for CHN user](https://www.zhihu.com/zvideo/1297662571618148352)]\n- FOSDEM2021 presentation [[Flash back](https://twitter.com/jxjputaoshu/status/1358462741703491584?s=20)], [[link for CHN user](https://www.zhihu.com/zvideo/1340748826311974912)]; [[Presentation](https://video.fosdem.org/2021/D.radio/fsr_openwifi_opensource_wifi_chip.webm)], [[link for CHN user](https://www.zhihu.com/zvideo/1345036055104360448)]\n- FSF Libreplanet 2021 presentation [[Official](https://media.libreplanet.org/u/libreplanet/m/openwifi-project-the-dawn-of-the-free-libre-wifi-chip/)], [[LinuxReviews](https://linuxreviews.org/Openwifi_project:_The_dawn_of_the_free/libre_WiFi_chip)], [[link for CHN user](https://www.zhihu.com/zvideo/1373649688906883072)]\n- Openwifi industrial real-time high reliable low latency applications (EU Horizon 2020 SHOP4CF project) [[Youtube](https://youtu.be/p7zkkdMvPNc)], [[link for CHN user](https://www.zhihu.com/zvideo/1378413483944538113)]\n- WiFi CSI Radar: Joint communication and sensing [[Youtube](https://youtu.be/PUwpJuHZDhg)], [[link for CHN user](https://www.bilibili.com/video/BV1a94y1W7XL/?share_source=copy_web&vd_source=587e4ed61021396d31fd3a09c077969f)]\n- CSI fuzzer [[Youtube](https://youtu.be/aOPYwT77Qdw)], [[link for CHN user](https://www.zhihu.com/zvideo/1378409348163506177)], and ACM WiSec interview [[Youtube](https://youtu.be/ZOCV78aTaQg)], [[link for CHN user](https://www.bilibili.com/video/BV1Mo4y1C76t?share_source=copy_web)]\n- NGI zero, nlnet online session on future of European open hardware [[Session](https://nlnet.nl/news/2021/20210507-NGI-Zero-workshop-open-hardware.html)], [[Original record](https://archive.org/details/ngiforum-open-hardware-workshop-ngizero)], [[Youtube](https://youtu.be/m9Tw5VuHAfk)], [[link for CHN user](https://www.zhihu.com/zvideo/1379302398096285696)]\n- High Precision Time Synchronization on Wi-Fi based Multi-Hop Network [[Youtube](https://youtu.be/m5ryRArbdC8)], [[link for CHN user](https://www.zhihu.com/zvideo/1418222775224492032)]\n- FOSDEM2022 presentation [[Presentation](https://video.fosdem.org/2022/D.radio/radio_openwifi.webm)], [[link for CHN user](https://www.bilibili.com/video/BV12b4y1j7YK?share_source=copy_web)]\n- [Find the corresponding Wi-Fi packet in wireshark after openwifi CSI/IQ capture](https://github.com/open-sdr/openwifi/discussions/344) [[Youtube](https://youtu.be/iiiINz7XTGA)], [[link for CHN user](https://www.bilibili.com/video/BV13w411Y7GX/?share_source=copy_web&vd_source=587e4ed61021396d31fd3a09c077969f)]\n- CCC GPN22 DanielAW, How a Wifi chip works internally [[link](https://media.ccc.de/v/gpn22-380-how-a-wifi-chip-works-internally)]\n- FSiC2024, An opensource Wi-Fi chip, What, Why and How? [[link](https://wiki.f-si.org/index.php?title=An_opensource_Wi-Fi_chip,_What,_Why_and_How%3F)]\n"
  },
  {
    "path": "driver/Makefile",
    "content": "# Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be\n\nobj-m += sdr.o openofdm_rx/openofdm_rx.o openofdm_tx/openofdm_tx.o tx_intf/tx_intf.o rx_intf/rx_intf.o xpu/xpu.o\n\nall:\n\tmake -C $(KDIR) M=$(PWD) modules\n\t# ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-\n\nclean:\n\trm -f *.ko *.o *.mod.o *.mod.c *.symvers *.order\n"
  },
  {
    "path": "driver/hw_def.h",
    "content": "// Author: Xianjun jiao, Michael Mehari, Wei Liu\n// SPDX-FileCopyrightText: 2019 UGent\n// SPDX-License-Identifier: AGPL-3.0-or-later\n\n// #ifndef __HW_DEF_H_FILE__\n// #define __HW_DEF_H_FILE__\nconst char *sdr_compatible_str = \"sdr,sdr\";\n\nenum openwifi_hardware_type {\n  ZYNQ_AD9361 = 0,\n  ZYNQMP_AD9361 = 1,\n  RFSOC4X2 = 2,\n  UNKNOWN_HARDWARE,\n};\n\nenum openwifi_fpga_type {\n  SMALL_FPGA = 0,\n  LARGE_FPGA = 1,\n};\n\n//we choose 3822=(5160+2484)/2 for calibration to avoid treating 5140 as 2.4GHz\n#define OPENWIFI_FREQ_MHz_TH_FOR_2_4GHZ_5GHZ 3822\n\nenum openwifi_band {\n  BAND_900M = 0,\n  BAND_2_4GHZ,\n  BAND_3_65GHZ,\n  BAND_5_0GHZ,\n  //use this BAND_5_8GHZ to represent all frequencies above OPENWIFI_FREQ_TH_FOR_2_4GHZ_5GHZ\n  BAND_5_8GHZ,\n  BAND_5_9GHZ,\n  BAND_60GHZ,\n};\n\n// ------------------------------------tx interface----------------------------------------\nconst char *tx_intf_compatible_str = \"sdr,tx_intf\";\n\n#define TX_INTF_REG_MULTI_RST_ADDR                 (0*4)\n#define TX_INTF_REG_ARBITRARY_IQ_ADDR              (1*4)\n#define TX_INTF_REG_WIFI_TX_MODE_ADDR              (2*4)\n#define TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR         (4*4)\n#define TX_INTF_REG_CSI_FUZZER_ADDR                (5*4)\n#define TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_ADDR  (6*4)\n#define TX_INTF_REG_ARBITRARY_IQ_CTL_ADDR          (7*4)\n#define TX_INTF_REG_TX_CONFIG_ADDR                 (8*4)\n#define TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR      (9*4)\n#define TX_INTF_REG_CFG_DATA_TO_ANT_ADDR           (10*4)\n#define TX_INTF_REG_S_AXIS_FIFO_TH_ADDR            (11*4)\n#define TX_INTF_REG_TX_HOLD_THRESHOLD_ADDR         (12*4)\n#define TX_INTF_REG_BB_GAIN_ADDR                   (13*4)\n#define TX_INTF_REG_INTERRUPT_SEL_ADDR             (14*4)\n#define TX_INTF_REG_AMPDU_ACTION_CONFIG_ADDR       (15*4)\n#define TX_INTF_REG_ANT_SEL_ADDR                   (16*4)\n#define TX_INTF_REG_PHY_HDR_CONFIG_ADDR            (17*4)\n#define TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_ADDR       (21*4)\n#define TX_INTF_REG_PKT_INFO1_ADDR                 (22*4)\n#define TX_INTF_REG_PKT_INFO2_ADDR                 (23*4)\n#define TX_INTF_REG_PKT_INFO3_ADDR                 (24*4)\n#define TX_INTF_REG_PKT_INFO4_ADDR                 (25*4)\n#define TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_ADDR     (26*4)\n\n#define TX_INTF_NUM_ANTENNA                        2\n#define TX_INTF_NUM_BYTE_PER_DMA_SYMBOL            (64/8)\n#define TX_INTF_NUM_BYTE_PER_DMA_SYMBOL_IN_BITS    3\n\nenum tx_intf_mode {\n  TX_INTF_AXIS_LOOP_BACK = 0,\n  TX_INTF_BYPASS,\n  TX_INTF_BW_20MHZ_AT_0MHZ_ANT0,\n  TX_INTF_BW_20MHZ_AT_0MHZ_ANT1,\n  TX_INTF_BW_20MHZ_AT_0MHZ_ANT_BOTH,\n  TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0,\n  TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0,\n  TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1,\n  TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1,\n};\n\nconst int tx_intf_fo_mapping[] = {0, 0, 0, 0, 0, -10, 10, -10, 10};\nconst u32 dma_symbol_fifo_size_hw_queue[] = {4*1024, 4*1024, 4*1024, 4*1024}; // !!!make sure align to fifo in tx_intf_s_axis.v\n\nstruct tx_intf_driver_api {\n  u32 (*hw_init)(enum tx_intf_mode mode, u32 tx_config, u32 num_dma_symbol_to_ps, enum openwifi_fpga_type fpga_type);\n\n  u32 (*reg_read)(u32 reg);\n  void (*reg_write)(u32 reg, u32 value);\n\n  u32 (*TX_INTF_REG_MULTI_RST_read)(void);\n  u32 (*TX_INTF_REG_ARBITRARY_IQ_read)(void);\n  u32 (*TX_INTF_REG_WIFI_TX_MODE_read)(void);\n  u32 (*TX_INTF_REG_CTS_TOSELF_CONFIG_read)(void);\n  u32 (*TX_INTF_REG_CSI_FUZZER_read)(void);\n  u32 (*TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read)(void);\n  u32 (*TX_INTF_REG_ARBITRARY_IQ_CTL_read)(void);\n  u32 (*TX_INTF_REG_TX_CONFIG_read)(void);\n  u32 (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read)(void);\n  u32 (*TX_INTF_REG_CFG_DATA_TO_ANT_read)(void);\n  u32 (*TX_INTF_REG_S_AXIS_FIFO_TH_read)(void);\n  u32 (*TX_INTF_REG_TX_HOLD_THRESHOLD_read)(void);\n  u32 (*TX_INTF_REG_INTERRUPT_SEL_read)(void);\n  u32 (*TX_INTF_REG_AMPDU_ACTION_CONFIG_read)(void);\n  u32 (*TX_INTF_REG_BB_GAIN_read)(void);\n  u32 (*TX_INTF_REG_ANT_SEL_read)(void);\n  u32 (*TX_INTF_REG_PHY_HDR_CONFIG_read)(void);\n  u32 (*TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read)(void);\n  u32 (*TX_INTF_REG_PKT_INFO1_read)(void);\n  u32 (*TX_INTF_REG_PKT_INFO2_read)(void);\n  u32 (*TX_INTF_REG_PKT_INFO3_read)(void);\n  u32 (*TX_INTF_REG_PKT_INFO4_read)(void);\n  u32 (*TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read)(void);\n\n  void (*TX_INTF_REG_MULTI_RST_write)(u32 value);\n  void (*TX_INTF_REG_ARBITRARY_IQ_write)(u32 value);\n  void (*TX_INTF_REG_WIFI_TX_MODE_write)(u32 value);\n  void (*TX_INTF_REG_CTS_TOSELF_CONFIG_write)(u32 value);\n  void (*TX_INTF_REG_CSI_FUZZER_write)(u32 value);\n  void (*TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write)(u32 value);\n  void (*TX_INTF_REG_ARBITRARY_IQ_CTL_write)(u32 value);\n  void (*TX_INTF_REG_TX_CONFIG_write)(u32 value);\n  void (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write)(u32 value);\n  void (*TX_INTF_REG_CFG_DATA_TO_ANT_write)(u32 value);\n  void (*TX_INTF_REG_S_AXIS_FIFO_TH_write)(u32 value);\n  void (*TX_INTF_REG_TX_HOLD_THRESHOLD_write)(u32 value);\n  void (*TX_INTF_REG_INTERRUPT_SEL_write)(u32 value);\n  void (*TX_INTF_REG_AMPDU_ACTION_CONFIG_write)(u32 value);\n  void (*TX_INTF_REG_BB_GAIN_write)(u32 value);\n  void (*TX_INTF_REG_ANT_SEL_write)(u32 value);\n  void (*TX_INTF_REG_PHY_HDR_CONFIG_write)(u32 value);\n  void (*TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write)(u32 value);\n  void (*TX_INTF_REG_PKT_INFO1_write)(u32 value);\n  void (*TX_INTF_REG_PKT_INFO2_write)(u32 value);\n  void (*TX_INTF_REG_PKT_INFO3_write)(u32 value);\n  void (*TX_INTF_REG_PKT_INFO4_write)(u32 value);\n};\n\n// ------------------------------------rx interface----------------------------------------\nconst char *rx_intf_compatible_str = \"sdr,rx_intf\";\n\n#define RX_INTF_REG_MULTI_RST_ADDR                 (0*4)\n#define RX_INTF_REG_MIXER_CFG_ADDR                 (1*4)\n#define RX_INTF_REG_INTERRUPT_TEST_ADDR            (2*4)\n#define RX_INTF_REG_IQ_SRC_SEL_ADDR                (3*4)\n#define RX_INTF_REG_IQ_CTRL_ADDR                   (4*4)\n#define RX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR    (5*4)\n#define RX_INTF_REG_START_TRANS_TO_PS_ADDR         (6*4)\n#define RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_ADDR (7*4)\n#define RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR      (8*4)\n#define RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR      (9*4)\n#define RX_INTF_REG_CFG_DATA_TO_ANT_ADDR           (10*4)\n#define RX_INTF_REG_BB_GAIN_ADDR                   (11*4)\n#define RX_INTF_REG_TLAST_TIMEOUT_TOP_ADDR         (12*4)\n#define RX_INTF_REG_S2MM_INTR_DELAY_COUNT_ADDR     (13*4)\n#define RX_INTF_REG_ANT_SEL_ADDR                   (16*4)\n\n#define RX_INTF_NUM_ANTENNA                        2\n#define RX_INTF_NUM_BYTE_PER_DMA_SYMBOL            (64/8)\n#define RX_INTF_NUM_BYTE_PER_DMA_SYMBOL_IN_BITS    3\n\nenum rx_intf_mode {\n  RX_INTF_AXIS_LOOP_BACK = 0,\n  RX_INTF_BYPASS,\n  RX_INTF_BW_20MHZ_AT_0MHZ_ANT0,\n  RX_INTF_BW_20MHZ_AT_0MHZ_ANT1,\n  RX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0,\n  RX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1,\n  RX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0,\n  RX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1,\n};\n\nconst int rx_intf_fo_mapping[] = {0,0,0,0,-10,-10,10,10};\n\nstruct rx_intf_driver_api {\n  u32 io_start;\n  u32 base_addr;\n  \n  u32 (*hw_init)(enum rx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps);\n\n  u32 (*reg_read)(u32 reg);\n  void (*reg_write)(u32 reg, u32 value);\n\n  u32 (*RX_INTF_REG_MULTI_RST_read)(void);\n  u32 (*RX_INTF_REG_MIXER_CFG_read)(void);\n  u32 (*RX_INTF_REG_IQ_SRC_SEL_read)(void);\n  u32 (*RX_INTF_REG_IQ_CTRL_read)(void);\n  u32 (*RX_INTF_REG_START_TRANS_TO_PS_MODE_read)(void);\n  u32 (*RX_INTF_REG_START_TRANS_TO_PS_read)(void);\n  u32 (*RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_read)(void);\n  u32 (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read)(void);\n  u32 (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read)(void);\n  u32 (*RX_INTF_REG_CFG_DATA_TO_ANT_read)(void);\n  u32 (*RX_INTF_REG_ANT_SEL_read)(void);\n  u32 (*RX_INTF_REG_INTERRUPT_TEST_read)(void);\n  void (*RX_INTF_REG_MULTI_RST_write)(u32 value);\n  void (*RX_INTF_REG_MIXER_CFG_write)(u32 value);\n  void (*RX_INTF_REG_IQ_SRC_SEL_write)(u32 value);\n  void (*RX_INTF_REG_IQ_CTRL_write)(u32 value);\n  void (*RX_INTF_REG_START_TRANS_TO_PS_MODE_write)(u32 value);\n  void (*RX_INTF_REG_START_TRANS_TO_PS_write)(u32 value);\n  void (*RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write)(u32 value);\n  void (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write)(u32 value);\n  void (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write)(u32 value);\n  void (*RX_INTF_REG_CFG_DATA_TO_ANT_write)(u32 value);\n  void (*RX_INTF_REG_BB_GAIN_write)(u32 value);\n  void (*RX_INTF_REG_ANT_SEL_write)(u32 value);\n  void (*RX_INTF_REG_INTERRUPT_TEST_write)(u32 value);\n\n  void (*RX_INTF_REG_M_AXIS_RST_write)(u32 value);\n  void (*RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write)(u32 value);\n  void (*RX_INTF_REG_TLAST_TIMEOUT_TOP_write)(u32 value);\n};\n\n// ----------------------------------openofdm rx-------------------------------\nconst char *openofdm_rx_compatible_str = \"sdr,openofdm_rx\";\n\n#define OPENOFDM_RX_REG_MULTI_RST_ADDR     (0*4)\n#define OPENOFDM_RX_REG_ENABLE_ADDR        (1*4)\n#define OPENOFDM_RX_REG_POWER_THRES_ADDR   (2*4)\n#define OPENOFDM_RX_REG_MIN_PLATEAU_ADDR   (3*4)\n#define OPENOFDM_RX_REG_SOFT_DECODING_ADDR (4*4)\n#define OPENOFDM_RX_REG_FFT_WIN_SHIFT_ADDR (5*4)\n#define OPENOFDM_RX_REG_PHASE_OFFSET_ABS_TH_ADDR (18*4)\n#define OPENOFDM_RX_REG_STATE_HISTORY_ADDR (20*4)\n\nenum openofdm_rx_mode {\n  OPENOFDM_RX_TEST = 0,\n  OPENOFDM_RX_NORMAL,\n};\n\n#define OPENOFDM_RX_POWER_THRES_INIT 124\n// Above 118 is based on these test result (2022-03-09)\n// FMCOMMS3\n// 2437M\n// 11a/g BPSK 6M, Rx sensitivity level dmesg report -85dBm\n// priv->rssi_correction = 153; rssi_half_db/2 = 153-85=68; rssi_half_db = 136\n// 5180M\n// 11a/g BPSK 6m, Rx sensitivity level dmesg report -84dBm\n// priv->rssi_correction = 145; rssi_half_db/2 = 145-84=61; rssi_half_db = 122\n// 5320M\n// 11a/g BPSK 6m, Rx sensitivity level dmesg report -86dBm\n// priv->rssi_correction = 148; rssi_half_db/2 = 148-86=62; rssi_half_db = 124\n\n// FMCOMMS2\n// 2437M\n// 11a/g BPSK 6M, Rx sensitivity level dmesg report -80dBm\n// priv->rssi_correction = 153; rssi_half_db/2 = 153-80=73; rssi_half_db = 146\n// 5180M\n// 11a/g BPSK 6m, Rx sensitivity level dmesg report -83dBm\n// priv->rssi_correction = 145; rssi_half_db/2 = 145-83=62; rssi_half_db = 124\n// 5320M\n// 11a/g BPSK 6m, Rx sensitivity level dmesg report -86dBm\n// priv->rssi_correction = 148; rssi_half_db/2 = 148-86=62; rssi_half_db = 124\n\n// #define OPENOFDM_RX_RSSI_DBM_TH_DEFAULT (-85) //-85 will remove lots of false alarm. the best openwifi reported sensitivity is like -90/-92 (set it manually if conductive test with wifi tester)\n#define OPENOFDM_RX_RSSI_DBM_TH_DEFAULT (-95) //due to performance is much better (can work around -90dBm), lower it from -85dBm to -95dBm\n#define OPENOFDM_RX_DC_RUNNING_SUM_TH_INIT 64\n#define OPENOFDM_RX_MIN_PLATEAU_INIT 100\n#define OPENOFDM_RX_FFT_WIN_SHIFT_INIT 4\n#define OPENOFDM_RX_SMALL_EQ_OUT_COUNTER_TH 48\n#define OPENOFDM_RX_PHASE_OFFSET_ABS_TH 11\n\n#define OPENWIFI_MAX_SIGNAL_LEN_TH 1700 //Packet longer  than this threshold will result in receiver early termination. It goes to openofdm_rx/xpu/rx_intf\n\n#define OPENWIFI_MIN_SIGNAL_LEN_TH 14   //Packet shorter than this threshold will result in receiver early termination. It goes to openofdm_rx/xpu/rx_intf\n                                        //due to CRC32, at least 4 bytes needed to push out expected CRC result\n\nstruct openofdm_rx_driver_api {\n  u32 (*hw_init)(enum openofdm_rx_mode mode);\n\n  u32 (*reg_read)(u32 reg);\n  void (*reg_write)(u32 reg, u32 value);\n\n  u32 (*OPENOFDM_RX_REG_STATE_HISTORY_read)(void);\n\n  void (*OPENOFDM_RX_REG_MULTI_RST_write)(u32 value);\n  void (*OPENOFDM_RX_REG_ENABLE_write)(u32 value);\n  void (*OPENOFDM_RX_REG_POWER_THRES_write)(u32 value);\n  void (*OPENOFDM_RX_REG_MIN_PLATEAU_write)(u32 value);\n  void (*OPENOFDM_RX_REG_SOFT_DECODING_write)(u32 value);\n  void (*OPENOFDM_RX_REG_FFT_WIN_SHIFT_write)(u32 value);\n  void (*OPENOFDM_RX_REG_PHASE_OFFSET_ABS_TH_write)(u32 value);\n};\n\n// ---------------------------------------openofdm tx-------------------------------\nconst char *openofdm_tx_compatible_str = \"sdr,openofdm_tx\";\n\n#define OPENOFDM_TX_REG_MULTI_RST_ADDR                 (0*4)\n#define OPENOFDM_TX_REG_INIT_PILOT_STATE_ADDR          (1*4)\n#define OPENOFDM_TX_REG_INIT_DATA_STATE_ADDR           (2*4)\n\nenum openofdm_tx_mode {\n  OPENOFDM_TX_TEST = 0,\n  OPENOFDM_TX_NORMAL,\n};\n\nstruct openofdm_tx_driver_api {\n  u32 (*hw_init)(enum openofdm_tx_mode mode);\n\n  u32 (*reg_read)(u32 reg);\n  void (*reg_write)(u32 reg, u32 value);\n\n  void (*OPENOFDM_TX_REG_MULTI_RST_write)(u32 value);\n  void (*OPENOFDM_TX_REG_INIT_PILOT_STATE_write)(u32 value);\n  void (*OPENOFDM_TX_REG_INIT_DATA_STATE_write)(u32 value);\n};\n\n// ---------------------------------------xpu low MAC controller-------------------------------\n\n// extra filter flag together with enum ieee80211_filter_flags in mac80211.h\n#define UNICAST_FOR_US     (1<<9)\n#define BROADCAST_ALL_ONE  (1<<10)\n#define BROADCAST_ALL_ZERO (1<<11)\n#define MY_BEACON          (1<<12)\n#define MONITOR_ALL        (1<<13)\n\nconst char *xpu_compatible_str = \"sdr,xpu\";\n\n#define XPU_REG_MULTI_RST_ADDR                (0*4)\n#define XPU_REG_SRC_SEL_ADDR                  (1*4)\n#define XPU_REG_TSF_LOAD_VAL_LOW_ADDR         (2*4)\n#define XPU_REG_TSF_LOAD_VAL_HIGH_ADDR        (3*4)\n#define XPU_REG_BAND_CHANNEL_ADDR             (4*4)\n#define XPU_REG_DIFS_ADVANCE_ADDR             (5*4)\n#define XPU_REG_FORCE_IDLE_MISC_ADDR          (6*4)\n#define XPU_REG_RSSI_DB_CFG_ADDR              (7*4)\n#define XPU_REG_LBT_TH_ADDR                   (8*4)\n#define XPU_REG_CSMA_DEBUG_ADDR               (9*4)\n#define XPU_REG_BB_RF_DELAY_ADDR             (10*4)\n#define XPU_REG_ACK_CTL_MAX_NUM_RETRANS_ADDR  (11*4)\n#define XPU_REG_AMPDU_ACTION_ADDR            (12*4)\n#define XPU_REG_SPI_DISABLE_ADDR            (13*4)\n#define XPU_REG_RECV_ACK_COUNT_TOP0_ADDR      (16*4)\n#define XPU_REG_RECV_ACK_COUNT_TOP1_ADDR      (17*4)\n#define XPU_REG_SEND_ACK_WAIT_TOP_ADDR        (18*4)\n#define XPU_REG_CSMA_CFG_ADDR                 (19*4)\n\n#define XPU_REG_SLICE_COUNT_TOTAL_ADDR    (20*4)\n#define XPU_REG_SLICE_COUNT_START_ADDR    (21*4)\n#define XPU_REG_SLICE_COUNT_END_ADDR      (22*4)\n\n#define XPU_REG_CTS_TO_RTS_CONFIG_ADDR    (26*4)\n#define XPU_REG_FILTER_FLAG_ADDR          (27*4)\n#define XPU_REG_BSSID_FILTER_LOW_ADDR     (28*4)\n#define XPU_REG_BSSID_FILTER_HIGH_ADDR    (29*4)\n#define XPU_REG_MAC_ADDR_LOW_ADDR         (30*4)\n#define XPU_REG_MAC_ADDR_HIGH_ADDR        (31*4)\n\n#define XPU_REG_TSF_RUNTIME_VAL_LOW_ADDR  (58*4)\n#define XPU_REG_TSF_RUNTIME_VAL_HIGH_ADDR (59*4)\n\n#define XPU_REG_MAC_ADDR_READ_BACK_ADDR   (62*4)\n#define XPU_REG_FPGA_GIT_REV_ADDR         (63*4)\n\nenum xpu_mode {\n  XPU_TEST = 0,\n  XPU_NORMAL,\n};\n\nstruct xpu_driver_api {\n  u32 (*hw_init)(enum xpu_mode mode);\n\n  u32 (*reg_read)(u32 reg);\n  void (*reg_write)(u32 reg, u32 value);\n\n  void (*XPU_REG_MULTI_RST_write)(u32 value);\n  u32  (*XPU_REG_MULTI_RST_read)(void);\n\n  void (*XPU_REG_SRC_SEL_write)(u32 value);\n  u32  (*XPU_REG_SRC_SEL_read)(void);\n\n  void (*XPU_REG_RECV_ACK_COUNT_TOP0_write)(u32 value);\n  u32  (*XPU_REG_RECV_ACK_COUNT_TOP0_read)(void);\n\n  void (*XPU_REG_RECV_ACK_COUNT_TOP1_write)(u32 value);\n  u32  (*XPU_REG_RECV_ACK_COUNT_TOP1_read)(void);\n\n  void (*XPU_REG_SEND_ACK_WAIT_TOP_write)(u32 value);\n  u32  (*XPU_REG_SEND_ACK_WAIT_TOP_read)(void);\n\n  void (*XPU_REG_ACK_FC_FILTER_write)(u32 value);\n  u32  (*XPU_REG_ACK_FC_FILTER_read)(void);\n\n  void (*XPU_REG_CTS_TO_RTS_CONFIG_write)(u32 value);\n  u32  (*XPU_REG_CTS_TO_RTS_CONFIG_read)(void);\n\n  void (*XPU_REG_FILTER_FLAG_write)(u32 value);\n  u32  (*XPU_REG_FILTER_FLAG_read)(void);\n\n  void (*XPU_REG_MAC_ADDR_LOW_write)(u32 value);\n  u32  (*XPU_REG_MAC_ADDR_LOW_read)(void);\n\n  void (*XPU_REG_MAC_ADDR_HIGH_write)(u32 value);\n  u32  (*XPU_REG_MAC_ADDR_HIGH_read)(void);\n\n  void (*XPU_REG_BSSID_FILTER_LOW_write)(u32 value);\n  u32  (*XPU_REG_BSSID_FILTER_LOW_read)(void);\n\n  void (*XPU_REG_BSSID_FILTER_HIGH_write)(u32 value);\n  u32  (*XPU_REG_BSSID_FILTER_HIGH_read)(void);\n\n  void (*XPU_REG_BAND_CHANNEL_write)(u32 value);\n  u32  (*XPU_REG_BAND_CHANNEL_read)(void);\n\n  void (*XPU_REG_DIFS_ADVANCE_write)(u32 value);\n  u32  (*XPU_REG_DIFS_ADVANCE_read)(void);\n\n  void (*XPU_REG_FORCE_IDLE_MISC_write)(u32 value);\n  u32  (*XPU_REG_FORCE_IDLE_MISC_read)(void);\n\n  u32  (*XPU_REG_TRX_STATUS_read)(void);\n  u32  (*XPU_REG_TX_RESULT_read)(void);\n\n  u32  (*XPU_REG_TSF_RUNTIME_VAL_LOW_read)(void);\n  u32  (*XPU_REG_TSF_RUNTIME_VAL_HIGH_read)(void);\n\n  void (*XPU_REG_TSF_LOAD_VAL_LOW_write)(u32 value);\n  void (*XPU_REG_TSF_LOAD_VAL_HIGH_write)(u32 value);\n  void (*XPU_REG_TSF_LOAD_VAL_write)(u32 high_value, u32 low_value);\n\n  u32  (*XPU_REG_FC_DI_read)(void);\n  u32  (*XPU_REG_ADDR1_LOW_read)(void);\n  u32  (*XPU_REG_ADDR1_HIGH_read)(void);\n  u32  (*XPU_REG_ADDR2_LOW_read)(void);\n  u32  (*XPU_REG_ADDR2_HIGH_read)(void);\n\n  void (*XPU_REG_LBT_TH_write)(u32 value);\n  u32  (*XPU_REG_LBT_TH_read)(void);\n\n  void (*XPU_REG_RSSI_DB_CFG_write)(u32 value);\n  u32  (*XPU_REG_RSSI_DB_CFG_read)(void);\n\n  void (*XPU_REG_CSMA_DEBUG_write)(u32 value);\n  u32  (*XPU_REG_CSMA_DEBUG_read)(void);\n\n  void (*XPU_REG_CSMA_CFG_write)(u32 value);\n  u32  (*XPU_REG_CSMA_CFG_read)(void);\n\n  void (*XPU_REG_SLICE_COUNT_TOTAL_write)(u32 value);\n  void (*XPU_REG_SLICE_COUNT_START_write)(u32 value);\n  void (*XPU_REG_SLICE_COUNT_END_write)(u32 value);\n  void (*XPU_REG_SLICE_COUNT_TOTAL1_write)(u32 value);\n  void (*XPU_REG_SLICE_COUNT_START1_write)(u32 value);\n  void (*XPU_REG_SLICE_COUNT_END1_write)(u32 value);\n\n  u32 (*XPU_REG_SLICE_COUNT_TOTAL_read)(void);\n  u32 (*XPU_REG_SLICE_COUNT_START_read)(void);\n  u32 (*XPU_REG_SLICE_COUNT_END_read)(void);\n  u32 (*XPU_REG_SLICE_COUNT_TOTAL1_read)(void);\n  u32 (*XPU_REG_SLICE_COUNT_START1_read)(void);\n  u32 (*XPU_REG_SLICE_COUNT_END1_read)(void);\n\n  void (*XPU_REG_BB_RF_DELAY_write)(u32 value);\n  \n  void (*XPU_REG_ACK_CTL_MAX_NUM_RETRANS_write)(u32 value);\n  u32  (*XPU_REG_ACK_CTL_MAX_NUM_RETRANS_read)(void);\n\n  void (*XPU_REG_SPI_DISABLE_write)(u32 value); \n  u32  (*XPU_REG_SPI_DISABLE_read)(void);\n\n  void (*XPU_REG_AMPDU_ACTION_write)(u32 value);\n  u32  (*XPU_REG_AMPDU_ACTION_read)(void);\n\n  void (*XPU_REG_MAC_ADDR_write)(u8 *mac_addr);\n};\n\n// #endif\n"
  },
  {
    "path": "driver/make_all.sh",
    "content": "#!/bin/bash\n\n# Author: Xianjun jiao\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\nprint_usage () {\n    echo \"You must enter at least 2 arguments: \\$XILINX_DIR ARCH_BIT(32 or 64)\"\n    echo \"Further arguments (maximum 5) will be converted to #define argument in pre_def.h\"\n    echo \" \"\n}\n\nprint_usage\n\nif [ \"$#\" -lt 2 ]; then\n    exit 1\nfi\n\nOPENWIFI_DIR=$(pwd)/../\nXILINX_DIR=$1\nARCH_OPTION=$2\n\necho OPENWIFI_DIR $OPENWIFI_DIR\necho XILINX_DIR $XILINX_DIR\necho ARCH_OPTION $ARCH_OPTION\n\nif [ -f \"$OPENWIFI_DIR/LICENSE\" ]; then\n    echo \"\\$OPENWIFI_DIR is found!\"\nelse\n    echo \"\\$OPENWIFI_DIR is not correct. Please check!\"\n    exit 1\nfi\n\nif [ -d \"$XILINX_DIR/Vitis\" ]; then\n    echo \"\\$XILINX_DIR is found!\"\nelse\n    echo \"\\$XILINX_DIR is not correct. Please check!\"\n    exit 1\nfi\n\nif [ \"$ARCH_OPTION\" != \"32\" ] && [ \"$ARCH_OPTION\" != \"64\" ]; then\n    echo \"\\$ARCH_OPTION is not correct. Should be 32 or 64. Please check!\"\n    exit 1\nelse\n    echo \"\\$ARCH_OPTION is valid!\"\nfi\n\nXILINX_ENV_FILE=$XILINX_DIR/Vitis/2022.2/settings64.sh\necho \"Expect env file $XILINX_ENV_FILE\"\n\nif [ -f \"$XILINX_ENV_FILE\" ]; then\n    echo \"$XILINX_ENV_FILE is found!\"\nelse\n    echo \"$XILINX_ENV_FILE is not correct. Please check!\"\n    exit 1\nfi\n\necho \"#define USE_NEW_RX_INTERRUPT 1\" > pre_def.h\nif [[ -n $3 ]]; then\n    DEFINE1=$3\n    echo DEFINE1 $DEFINE1\n    echo \"#define $DEFINE1\" >> pre_def.h\nfi\nif [[ -n $4 ]]; then\n    DEFINE2=$4\n    echo DEFINE2 $DEFINE2\n    echo \"#define $DEFINE2\" >> pre_def.h\nfi\nif [[ -n $5 ]]; then\n    DEFINE3=$5\n    echo DEFINE3 $DEFINE3\n    echo \"#define $DEFINE3\" >> pre_def.h\nfi\nif [[ -n $6 ]]; then\n    DEFINE4=$6\n    echo DEFINE4 $DEFINE4\n    echo \"#define $DEFINE4\" >> pre_def.h\nfi\nif [[ -n $7 ]]; then\n    DEFINE5=$7\n    echo DEFINE5 $DEFINE5\n    echo \"#define $DEFINE5\" >> pre_def.h\nfi\n\nsource $XILINX_ENV_FILE\n\nif [ \"$ARCH_OPTION\" == \"64\" ]; then\n    LINUX_KERNEL_SRC_DIR=$OPENWIFI_DIR/adi-linux-64/\n    ARCH=\"arm64\"\n    CROSS_COMPILE=\"aarch64-linux-gnu-\"\nelse\n    LINUX_KERNEL_SRC_DIR=$OPENWIFI_DIR/adi-linux/\n    ARCH=\"arm\"\n    CROSS_COMPILE=\"arm-linux-gnueabihf-\"\nfi\n\n# check if user entered the right path to analog device linux\nif [ -d \"$LINUX_KERNEL_SRC_DIR\" ]; then\n    echo \"setup linux kernel path ${LINUX_KERNEL_SRC_DIR}\"\nelse\n    echo \"Error: path to adi linux: ${LINUX_KERNEL_SRC_DIR} not found. Can not continue.\"\n    exit 1\nfi\n\nset -x\n\nhome_dir=$(pwd)\n\ncd $OPENWIFI_DIR/driver/\nif git log -1; then\n    echo \"#define GIT_REV 0x\"$(git log -1 --pretty=%h) > git_rev.h\nelse\n    echo \"#define GIT_REV 0xFFFFFFFF\" > git_rev.h\nfi\ncd $OPENWIFI_DIR/driver/openofdm_tx\nmake KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE\ncd $OPENWIFI_DIR/driver/openofdm_rx\nmake KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE\ncd $OPENWIFI_DIR/driver/tx_intf\nmake KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE\ncd $OPENWIFI_DIR/driver/rx_intf\nmake KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE\ncd $OPENWIFI_DIR/driver/xpu\nmake KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE\n# cd $OPENWIFI_DIR/driver/ad9361\n# make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE\n\ncd $OPENWIFI_DIR/driver/side_ch\n./make_driver.sh $XILINX_DIR $ARCH_OPTION\n\ncd $OPENWIFI_DIR/driver/\nmake KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE\n\ncd $home_dir\n"
  },
  {
    "path": "driver/openofdm_rx/Makefile",
    "content": "# by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be\n\nobj-m += openofdm_rx.o\n\nall:\n\tmake -C $(KDIR) M=$(PWD) modules \n\t# ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-\n\nclean:\n\trm -f *.ko *.o *.mod.o *.mod.c *.symvers *.order\n"
  },
  {
    "path": "driver/openofdm_rx/openofdm_rx.c",
    "content": "/*\n * Author: Xianjun jiao, Michael Mehari, Wei Liu\n * SPDX-FileCopyrightText: 2019 UGent\n * SPDX-License-Identifier: AGPL-3.0-or-later\n*/\n\n#include <linux/bitops.h>\n#include <linux/dmapool.h>\n#include <linux/dma/xilinx_dma.h>\n#include <linux/init.h>\n#include <linux/interrupt.h>\n#include <linux/io.h>\n#include <linux/iopoll.h>\n#include <linux/module.h>\n#include <linux/of_address.h>\n#include <linux/of_dma.h>\n#include <linux/of_platform.h>\n#include <linux/of_irq.h>\n#include <linux/slab.h>\n#include <linux/clk.h>\n#include <linux/io-64-nonatomic-lo-hi.h>\n#include <linux/delay.h>\n\n#include \"../hw_def.h\"\n\nstatic void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design\n\n/* IO accessors */\nstatic inline u32 reg_read(u32 reg)\n{\n\treturn ioread32(base_addr + reg);\n}\n\nstatic inline void reg_write(u32 reg, u32 value)\n{\n\tiowrite32(value, base_addr + reg);\n}\n\nstatic inline u32 OPENOFDM_RX_REG_STATE_HISTORY_read(void){\n\treturn reg_read(OPENOFDM_RX_REG_STATE_HISTORY_ADDR);\n}\n\nstatic inline void OPENOFDM_RX_REG_MULTI_RST_write(u32 Data) {\n\treg_write(OPENOFDM_RX_REG_MULTI_RST_ADDR, Data);\n}\nstatic inline void OPENOFDM_RX_REG_ENABLE_write(u32 Data) {\n\treg_write(OPENOFDM_RX_REG_ENABLE_ADDR, Data);\n}\nstatic inline void OPENOFDM_RX_REG_POWER_THRES_write(u32 Data) {\n\treg_write(OPENOFDM_RX_REG_POWER_THRES_ADDR, Data);\n}\nstatic inline void OPENOFDM_RX_REG_MIN_PLATEAU_write(u32 Data) {\n\treg_write(OPENOFDM_RX_REG_MIN_PLATEAU_ADDR, Data);\n}\nstatic inline void OPENOFDM_RX_REG_SOFT_DECODING_write(u32 Data) {\n\treg_write(OPENOFDM_RX_REG_SOFT_DECODING_ADDR, Data);\n}\nstatic inline void OPENOFDM_RX_REG_FFT_WIN_SHIFT_write(u32 Data) {\n\treg_write(OPENOFDM_RX_REG_FFT_WIN_SHIFT_ADDR, Data);\n}\nstatic inline void OPENOFDM_RX_REG_PHASE_OFFSET_ABS_TH_write(u32 Data) {\n\treg_write(OPENOFDM_RX_REG_PHASE_OFFSET_ABS_TH_ADDR, Data);\n}\nstatic const struct of_device_id dev_of_ids[] = {\n\t{ .compatible = \"sdr,openofdm_rx\", },\n\t{}\n};\nMODULE_DEVICE_TABLE(of, dev_of_ids);\n\nstatic struct openofdm_rx_driver_api openofdm_rx_driver_api_inst;\nstruct openofdm_rx_driver_api *openofdm_rx_api = &openofdm_rx_driver_api_inst;\nEXPORT_SYMBOL(openofdm_rx_api);\n\nstatic inline u32 hw_init(enum openofdm_rx_mode mode){\n\tint err=0, i;\n\n\tprintk(\"%s hw_init mode %d\\n\", openofdm_rx_compatible_str, mode);\n\n\tswitch(mode)\n\t{\n\t\tcase OPENOFDM_RX_TEST:\n\t\t{\n\t\t\tprintk(\"%s hw_init mode OPENOFDM_RX_TEST\\n\", openofdm_rx_compatible_str);\n\t\t\tbreak;\n\t\t}\n\t\tcase OPENOFDM_RX_NORMAL:\n\t\t{\n\t\t\tprintk(\"%s hw_init mode OPENOFDM_RX_NORMAL\\n\", openofdm_rx_compatible_str);\n\t\t\tbreak;\n\t\t}\n\t\tdefault:\n\t\t{\n\t\t\tprintk(\"%s hw_init mode %d is wrong!\\n\", openofdm_rx_compatible_str, mode);\n\t\t\terr=1;\n\t\t}\n\t}\n\tprintk(\"%s hw_init input: power_thres %d dc_running_sum_th %d min_plateau %d\\n\", openofdm_rx_compatible_str, OPENOFDM_RX_POWER_THRES_INIT, OPENOFDM_RX_DC_RUNNING_SUM_TH_INIT, OPENOFDM_RX_MIN_PLATEAU_INIT);\n\n\t// 1) power threshold configuration and reset\n  openofdm_rx_api->OPENOFDM_RX_REG_ENABLE_write(1); //bit1 of slv_reg1: force ht smoothing to have better sensitivity\n\t\n  // Remove OPENOFDM_RX_REG_POWER_THRES_write to avoid hw_init call in openwifi_start causing inconsistency\n  // openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write((OPENOFDM_RX_DC_RUNNING_SUM_TH_INIT<<16)|OPENOFDM_RX_POWER_THRES_INIT); // turn on signal watchdog by default\n\t\n  openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write(OPENOFDM_RX_MIN_PLATEAU_INIT);\n\topenofdm_rx_api->OPENOFDM_RX_REG_SOFT_DECODING_write((OPENWIFI_MAX_SIGNAL_LEN_TH<<16)|(OPENWIFI_MIN_SIGNAL_LEN_TH<<12)|1); //bit1 enable soft decoding; bit15~12 min pkt length threshold; bit31~16 max pkt length threshold\n\topenofdm_rx_api->OPENOFDM_RX_REG_FFT_WIN_SHIFT_write((OPENOFDM_RX_SMALL_EQ_OUT_COUNTER_TH<<4)|OPENOFDM_RX_FFT_WIN_SHIFT_INIT);\n  openofdm_rx_api->OPENOFDM_RX_REG_PHASE_OFFSET_ABS_TH_write(OPENOFDM_RX_PHASE_OFFSET_ABS_TH);\n\n\t//rst\n\tfor (i=0;i<8;i++)\n\t\topenofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0);\n\tfor (i=0;i<32;i++)\n\t\topenofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0xFFFFFFFF);\n\tfor (i=0;i<8;i++)\n\t\topenofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0);\n\n\tprintk(\"%s hw_init err %d\\n\", openofdm_rx_compatible_str, err);\n\n\treturn(err);\n}\n\nstatic int dev_probe(struct platform_device *pdev)\n{\n\tstruct device_node *np = pdev->dev.of_node;\n\tstruct resource *io;\n\tint err=1;\n\n\tprintk(\"\\n\");\n\n\tif (np) {\n\t\tconst struct of_device_id *match;\n\n\t\tmatch = of_match_node(dev_of_ids, np);\n\t\tif (match) {\n\t\t\tprintk(\"%s dev_probe match!\\n\", openofdm_rx_compatible_str);\n\t\t\terr = 0;\n\t\t}\n\t}\n\n\tif (err)\n\t\treturn err;\n\n\topenofdm_rx_api->hw_init=hw_init;\n\n\topenofdm_rx_api->reg_read=reg_read;\n\topenofdm_rx_api->reg_write=reg_write;\n\n\topenofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write=OPENOFDM_RX_REG_MULTI_RST_write;\n\topenofdm_rx_api->OPENOFDM_RX_REG_ENABLE_write=OPENOFDM_RX_REG_ENABLE_write;\n\topenofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write=OPENOFDM_RX_REG_POWER_THRES_write;\n\topenofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write=OPENOFDM_RX_REG_MIN_PLATEAU_write;\n\topenofdm_rx_api->OPENOFDM_RX_REG_SOFT_DECODING_write=OPENOFDM_RX_REG_SOFT_DECODING_write;\n\topenofdm_rx_api->OPENOFDM_RX_REG_FFT_WIN_SHIFT_write=OPENOFDM_RX_REG_FFT_WIN_SHIFT_write;\n\topenofdm_rx_api->OPENOFDM_RX_REG_PHASE_OFFSET_ABS_TH_write=OPENOFDM_RX_REG_PHASE_OFFSET_ABS_TH_write;\n\n\t/* Request and map I/O memory */\n\tio = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n\tbase_addr = devm_ioremap_resource(&pdev->dev, io);\n\tif (IS_ERR(base_addr))\n\t\treturn PTR_ERR(base_addr);\n\n\tprintk(\"%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\\n\", openofdm_rx_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc);\n\tprintk(\"%s dev_probe base_addr 0x%08x\\n\", openofdm_rx_compatible_str,(u32)base_addr);\n\tprintk(\"%s dev_probe openofdm_rx_driver_api_inst 0x%08x\\n\", openofdm_rx_compatible_str, (u32)&openofdm_rx_driver_api_inst);\n\tprintk(\"%s dev_probe             openofdm_rx_api 0x%08x\\n\", openofdm_rx_compatible_str, (u32)openofdm_rx_api);\n\n\tprintk(\"%s dev_probe succeed!\\n\", openofdm_rx_compatible_str);\n\n\terr = hw_init(OPENOFDM_RX_NORMAL);\n\n\treturn err;\n}\n\nstatic int dev_remove(struct platform_device *pdev)\n{\n\tprintk(\"\\n\");\n\n\tprintk(\"%s dev_remove base_addr 0x%08x\\n\", openofdm_rx_compatible_str,(u32)base_addr);\n\tprintk(\"%s dev_remove openofdm_rx_driver_api_inst 0x%08x\\n\", openofdm_rx_compatible_str, (u32)&openofdm_rx_driver_api_inst);\n\tprintk(\"%s dev_remove             openofdm_rx_api 0x%08x\\n\", openofdm_rx_compatible_str, (u32)openofdm_rx_api);\n\n\tprintk(\"%s dev_remove succeed!\\n\", openofdm_rx_compatible_str);\n\treturn 0;\n}\n\nstatic struct platform_driver dev_driver = {\n\t.driver = {\n\t\t.name = \"sdr,openofdm_rx\",\n\t\t.owner = THIS_MODULE,\n\t\t.of_match_table = dev_of_ids,\n\t},\n\t.probe = dev_probe,\n\t.remove = dev_remove,\n};\n\nmodule_platform_driver(dev_driver);\n\nMODULE_AUTHOR(\"Xianjun Jiao\");\nMODULE_DESCRIPTION(\"sdr,openofdm_rx\");\nMODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "driver/openofdm_tx/Makefile",
    "content": "# by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be\n\nobj-m += openofdm_tx.o\n\nall:\n\tmake -C $(KDIR) M=$(PWD) modules\n\t# ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-\n\nclean:\n\trm -f *.ko *.o *.mod.o *.mod.c *.symvers *.order\n"
  },
  {
    "path": "driver/openofdm_tx/openofdm_tx.c",
    "content": "/*\n * axi lite register access driver\n * Author: Xianjun jiao, Michael Mehari, Wei Liu\n * SPDX-FileCopyrightText: 2019 UGent\n * SPDX-License-Identifier: AGPL-3.0-or-later\n*/\n\n#include <linux/bitops.h>\n#include <linux/dmapool.h>\n#include <linux/dma/xilinx_dma.h>\n#include <linux/init.h>\n#include <linux/interrupt.h>\n#include <linux/io.h>\n#include <linux/iopoll.h>\n#include <linux/module.h>\n#include <linux/of_address.h>\n#include <linux/of_dma.h>\n#include <linux/of_platform.h>\n#include <linux/of_irq.h>\n#include <linux/slab.h>\n#include <linux/clk.h>\n#include <linux/io-64-nonatomic-lo-hi.h>\n#include <linux/delay.h>\n\n#include \"../hw_def.h\"\n\nstatic void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design\n\n/* IO accessors */\nstatic inline u32 reg_read(u32 reg)\n{\n\treturn ioread32(base_addr + reg);\n}\n\nstatic inline void reg_write(u32 reg, u32 value)\n{\n\tiowrite32(value, base_addr + reg);\n}\n\nstatic inline void OPENOFDM_TX_REG_MULTI_RST_write(u32 Data) {\n\treg_write(OPENOFDM_TX_REG_MULTI_RST_ADDR, Data);\n}\n\nstatic inline void OPENOFDM_TX_REG_INIT_PILOT_STATE_write(u32 Data) {\n\treg_write(OPENOFDM_TX_REG_INIT_PILOT_STATE_ADDR, Data);\n}\n\nstatic inline void OPENOFDM_TX_REG_INIT_DATA_STATE_write(u32 Data) {\n\treg_write(OPENOFDM_TX_REG_INIT_DATA_STATE_ADDR, Data);\n}\n\nstatic const struct of_device_id dev_of_ids[] = {\n\t{ .compatible = \"sdr,openofdm_tx\", },\n\t{}\n};\nMODULE_DEVICE_TABLE(of, dev_of_ids);\n\nstatic struct openofdm_tx_driver_api openofdm_tx_driver_api_inst;\nstruct openofdm_tx_driver_api *openofdm_tx_api = &openofdm_tx_driver_api_inst;\nEXPORT_SYMBOL(openofdm_tx_api);\n\nstatic inline u32 hw_init(enum openofdm_tx_mode mode){\n\tint err=0, i;\n\n\tprintk(\"%s hw_init mode %d\\n\", openofdm_tx_compatible_str, mode);\n\n\tswitch(mode)\n\t{\n\t\tcase OPENOFDM_TX_TEST:\n\t\t\tprintk(\"%s hw_init mode OPENOFDM_TX_TEST\\n\", openofdm_tx_compatible_str);\n\t\t\tbreak;\n\n\t\tcase OPENOFDM_TX_NORMAL:\n\t\t\tprintk(\"%s hw_init mode OPENOFDM_TX_NORMAL\\n\", openofdm_tx_compatible_str);\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tprintk(\"%s hw_init mode %d is wrong!\\n\", openofdm_tx_compatible_str, mode);\n\t\t\terr=1;\n\t}\n\n\t//rst\n\tfor (i=0;i<8;i++)\n\t\topenofdm_tx_api->OPENOFDM_TX_REG_MULTI_RST_write(0);\n\tfor (i=0;i<32;i++)\n\t\topenofdm_tx_api->OPENOFDM_TX_REG_MULTI_RST_write(0xFFFFFFFF);\n\tfor (i=0;i<8;i++)\n\t\topenofdm_tx_api->OPENOFDM_TX_REG_MULTI_RST_write(0);\n\n\topenofdm_tx_api->OPENOFDM_TX_REG_INIT_PILOT_STATE_write(0x7F);\n\topenofdm_tx_api->OPENOFDM_TX_REG_INIT_DATA_STATE_write(0x7F);\n\n\tprintk(\"%s hw_init err %d\\n\", openofdm_tx_compatible_str, err);\n\treturn(err);\n}\n\nstatic int dev_probe(struct platform_device *pdev)\n{\n\tstruct device_node *np = pdev->dev.of_node;\n\tstruct resource *io;\n\tint err=1;\n\n\tprintk(\"\\n\");\n\n\tif (np) {\n\t\tconst struct of_device_id *match;\n\n\t\tmatch = of_match_node(dev_of_ids, np);\n\t\tif (match) {\n\t\t\tprintk(\"%s dev_probe match!\\n\", openofdm_tx_compatible_str);\n\t\t\terr = 0;\n\t\t}\n\t}\n\n\tif (err)\n\t\treturn err;\n\n\topenofdm_tx_api->hw_init=hw_init;\n\n\topenofdm_tx_api->reg_read=reg_read;\n\topenofdm_tx_api->reg_write=reg_write;\n\n\topenofdm_tx_api->OPENOFDM_TX_REG_MULTI_RST_write=OPENOFDM_TX_REG_MULTI_RST_write;\n\topenofdm_tx_api->OPENOFDM_TX_REG_INIT_PILOT_STATE_write=OPENOFDM_TX_REG_INIT_PILOT_STATE_write;\n\topenofdm_tx_api->OPENOFDM_TX_REG_INIT_DATA_STATE_write=OPENOFDM_TX_REG_INIT_DATA_STATE_write;\n\t\n\t/* Request and map I/O memory */\n\tio = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n\tbase_addr = devm_ioremap_resource(&pdev->dev, io);\n\tif (IS_ERR(base_addr))\n\t\treturn PTR_ERR(base_addr);\n\n\tprintk(\"%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\\n\", openofdm_tx_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc);\n\tprintk(\"%s dev_probe base_addr 0x%08x\\n\", openofdm_tx_compatible_str,(u32)base_addr);\n\tprintk(\"%s dev_probe openofdm_tx_driver_api_inst 0x%08x\\n\", openofdm_tx_compatible_str, (u32)&openofdm_tx_driver_api_inst);\n\tprintk(\"%s dev_probe             openofdm_tx_api 0x%08x\\n\", openofdm_tx_compatible_str, (u32)openofdm_tx_api);\n\n\tprintk(\"%s dev_probe succeed!\\n\", openofdm_tx_compatible_str);\n\n\terr = hw_init(OPENOFDM_TX_NORMAL);\n\n\treturn err;\n}\n\nstatic int dev_remove(struct platform_device *pdev)\n{\n\tprintk(\"\\n\");\n\n\tprintk(\"%s dev_remove base_addr 0x%08x\\n\", openofdm_tx_compatible_str,(u32)base_addr);\n\tprintk(\"%s dev_remove openofdm_tx_driver_api_inst 0x%08x\\n\", openofdm_tx_compatible_str, (u32)&openofdm_tx_driver_api_inst);\n\tprintk(\"%s dev_remove             openofdm_tx_api 0x%08x\\n\", openofdm_tx_compatible_str, (u32)openofdm_tx_api);\n\n\tprintk(\"%s dev_remove succeed!\\n\", openofdm_tx_compatible_str);\n\treturn 0;\n}\n\nstatic struct platform_driver dev_driver = {\n\t.driver = {\n\t\t.name = \"sdr,openofdm_tx\",\n\t\t.owner = THIS_MODULE,\n\t\t.of_match_table = dev_of_ids,\n\t},\n\t.probe = dev_probe,\n\t.remove = dev_remove,\n};\n\nmodule_platform_driver(dev_driver);\n\nMODULE_AUTHOR(\"Xianjun Jiao\");\nMODULE_DESCRIPTION(\"sdr,openofdm_tx\");\nMODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "driver/rx_intf/Makefile",
    "content": "# by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be\n\nobj-m += rx_intf.o\n\nall:\n\tmake -C $(KDIR) M=$(PWD) modules\n\t# ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-\n\nclean:\n\trm -f *.ko *.o *.mod.o *.mod.c *.symvers *.order\n"
  },
  {
    "path": "driver/rx_intf/rx_intf.c",
    "content": "/*\n * axi lite register access driver\n * Author: Xianjun Jiao, Michael Mehari, Wei Liu\n * SPDX-FileCopyrightText: 2019 UGent\n * SPDX-License-Identifier: AGPL-3.0-or-later\n*/\n\n#include <linux/bitops.h>\n#include <linux/dmapool.h>\n#include <linux/dma/xilinx_dma.h>\n#include <linux/init.h>\n#include <linux/interrupt.h>\n#include <linux/io.h>\n#include <linux/iopoll.h>\n#include <linux/module.h>\n#include <linux/of_address.h>\n#include <linux/of_dma.h>\n#include <linux/of_platform.h>\n#include <linux/of_irq.h>\n#include <linux/slab.h>\n#include <linux/clk.h>\n#include <linux/io-64-nonatomic-lo-hi.h>\n\n#include \"../hw_def.h\"\n\nstatic void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design\n\n/* IO accessors */\nstatic inline u32 reg_read(u32 reg)\n{\n\treturn ioread32(base_addr + reg);\n}\n\nstatic inline void reg_write(u32 reg, u32 value)\n{\n\tiowrite32(value, base_addr + reg);\n}\n\nstatic inline u32 RX_INTF_REG_MULTI_RST_read(void){\n\treturn reg_read(RX_INTF_REG_MULTI_RST_ADDR);\n}\n\nstatic inline u32 RX_INTF_REG_MIXER_CFG_read(void){\n\treturn reg_read(RX_INTF_REG_MIXER_CFG_ADDR);\n}\n\nstatic inline u32 RX_INTF_REG_IQ_SRC_SEL_read(void){\n\treturn reg_read(RX_INTF_REG_IQ_SRC_SEL_ADDR);\n}\n\nstatic inline u32 RX_INTF_REG_IQ_CTRL_read(void){\n\treturn reg_read(RX_INTF_REG_IQ_CTRL_ADDR);\n}\n\nstatic inline u32 RX_INTF_REG_START_TRANS_TO_PS_MODE_read(void){\n\treturn reg_read(RX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR);\n}\n\nstatic inline u32 RX_INTF_REG_START_TRANS_TO_PS_read(void){\n\treturn reg_read(RX_INTF_REG_START_TRANS_TO_PS_ADDR);\n}\n\nstatic inline u32 RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_read(void){\n\treturn reg_read(RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_ADDR);\n}\n\nstatic inline u32 RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read(void){\n\treturn reg_read(RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR);\n}\n\nstatic inline u32 RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read(void){\n\treturn reg_read(RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR);\n}\n\nstatic inline u32 RX_INTF_REG_CFG_DATA_TO_ANT_read(void){\n\treturn reg_read(RX_INTF_REG_CFG_DATA_TO_ANT_ADDR);\n}\n\nstatic inline u32 RX_INTF_REG_ANT_SEL_read(void){\n\treturn reg_read(RX_INTF_REG_ANT_SEL_ADDR);\n}\n\nstatic inline u32 RX_INTF_REG_INTERRUPT_TEST_read(void) {\n\treturn reg_read(RX_INTF_REG_INTERRUPT_TEST_ADDR);\n}\n\nstatic inline void RX_INTF_REG_MULTI_RST_write(u32 value){\n\treg_write(RX_INTF_REG_MULTI_RST_ADDR, value);\n}\n\nstatic inline void RX_INTF_REG_M_AXIS_RST_write(u32 value){\n\tu32 reg_val;\n\n\tif (value==0) {\n\t\treg_val = RX_INTF_REG_MULTI_RST_read();\n\t\treg_val = ( reg_val&(~(1<<4)) );\n\t\tRX_INTF_REG_MULTI_RST_write(reg_val);\n\t} else {\n\t\treg_val = RX_INTF_REG_MULTI_RST_read();\n\t\treg_val = ( reg_val|(1<<4) );\n\t\tRX_INTF_REG_MULTI_RST_write(reg_val);\n\t}\n}\n\nstatic inline void RX_INTF_REG_MIXER_CFG_write(u32 value){\n\treg_write(RX_INTF_REG_MIXER_CFG_ADDR, value);\n}\n\nstatic inline void RX_INTF_REG_IQ_SRC_SEL_write(u32 value){\n\treg_write(RX_INTF_REG_IQ_SRC_SEL_ADDR, value);\n}\n\nstatic inline void RX_INTF_REG_IQ_CTRL_write(u32 value){\n\treg_write(RX_INTF_REG_IQ_CTRL_ADDR, value);\n}\n\nstatic inline void RX_INTF_REG_START_TRANS_TO_PS_MODE_write(u32 value){\n\treg_write(RX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR, value);\n}\n\nstatic inline void RX_INTF_REG_START_TRANS_TO_PS_write(u32 value){\n\treg_write(RX_INTF_REG_START_TRANS_TO_PS_ADDR, value);\n}\n\nstatic inline void RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write(u32 value){\n\treg_write(RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_ADDR, value);\n}\n\nstatic inline void RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write(u32 value){\n\treg_write(RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR, value);\n}\n\nstatic inline void RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(u32 value){\n\treg_write(RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR, value);\n}\n\nstatic inline void RX_INTF_REG_CFG_DATA_TO_ANT_write(u32 value){\n\treg_write(RX_INTF_REG_CFG_DATA_TO_ANT_ADDR, value);\n}\n\nstatic inline void RX_INTF_REG_BB_GAIN_write(u32 value) {\n\treg_write(RX_INTF_REG_BB_GAIN_ADDR, value);\n}\n\nstatic inline void RX_INTF_REG_ANT_SEL_write(u32 value){\n\treg_write(RX_INTF_REG_ANT_SEL_ADDR, value);\n}\n\nstatic inline void RX_INTF_REG_INTERRUPT_TEST_write(u32 value) {\n\treg_write(RX_INTF_REG_INTERRUPT_TEST_ADDR, value);\n}\n\nstatic inline void RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write(u32 value) {\n\treg_write(RX_INTF_REG_S2MM_INTR_DELAY_COUNT_ADDR, value);\n}\n\nstatic inline void RX_INTF_REG_TLAST_TIMEOUT_TOP_write(u32 value) {\n\treg_write(RX_INTF_REG_TLAST_TIMEOUT_TOP_ADDR, value);\n}\n\nstatic const struct of_device_id dev_of_ids[] = {\n\t{ .compatible = \"sdr,rx_intf\", },\n\t{}\n};\nMODULE_DEVICE_TABLE(of, dev_of_ids);\n\nstatic struct rx_intf_driver_api rx_intf_driver_api_inst;\nstruct rx_intf_driver_api *rx_intf_api = &rx_intf_driver_api_inst;\nEXPORT_SYMBOL(rx_intf_api);\n\nstatic inline u32 hw_init(enum rx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps){\n\tint err=0, i;\n\tu32 reg_val, mixer_cfg=0, ant_sel=0;\n\n\tprintk(\"%s hw_init mode %d\\n\", rx_intf_compatible_str, mode);\n\n\trx_intf_api->RX_INTF_REG_TLAST_TIMEOUT_TOP_write(7000);\n\t\n\t//rst\n\tfor (i=0;i<8;i++)\n\t\trx_intf_api->RX_INTF_REG_MULTI_RST_write(0);\n\tfor (i=0;i<32;i++)\n\t\trx_intf_api->RX_INTF_REG_MULTI_RST_write(0xFFFFFFFF);\n\tfor (i=0;i<8;i++)\n\t\trx_intf_api->RX_INTF_REG_MULTI_RST_write(0);\n\n\trx_intf_api->RX_INTF_REG_M_AXIS_RST_write(1); // hold M AXIS in reset status. will be released when openwifi_start\n\n\tswitch(mode)\n\t{\n\t\tcase RX_INTF_AXIS_LOOP_BACK:\n\t\t\tprintk(\"%s hw_init mode RX_INTF_AXIS_LOOP_BACK\\n\", rx_intf_compatible_str);\n\t\t\t//setting the path and mode. This must be done before our dma end reset\n\t\t\trx_intf_api->RX_INTF_REG_IQ_SRC_SEL_write(0x15);\n\t\t\trx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write(1);\n\t\t\trx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_write(0x37);// endless mode to support sg DMA loop back, start 1 trans from sw trigger\n\n\t\t\trx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write(num_dma_symbol_to_pl);\n\t\t\trx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(num_dma_symbol_to_ps);\n\n\t\t\t// put bb_en to constant 1\n\t\t\treg_val = rx_intf_api->RX_INTF_REG_IQ_CTRL_read();\n\t\t\treg_val = (reg_val|0x8);\n\t\t\trx_intf_api->RX_INTF_REG_IQ_CTRL_write(reg_val);\n\n\t\t\t// connect axis slave and master directly for loopback\n\t\t\trx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_write(0x1037);\n\n\t\t\t// reset dma end point in our design\n\t\t\treg_val = rx_intf_api->RX_INTF_REG_MULTI_RST_read();\n\t\t\treg_val = (reg_val&(~0x14) );\n\t\t\trx_intf_api->RX_INTF_REG_MULTI_RST_write(reg_val);\n\t\t\treg_val = reg_val|(0x14);\n\t\t\trx_intf_api->RX_INTF_REG_MULTI_RST_write(reg_val);\n\t\t\treg_val = reg_val&(~0x14);\n\t\t\trx_intf_api->RX_INTF_REG_MULTI_RST_write(reg_val);\n\n\t\t\t//start 1 trans now from our m_axis to ps dma\n\t\t\trx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write(0);\n\t\t\trx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write(1);\n\t\t\trx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write(0);\n\t\t\tbreak;\n\n\t\tcase RX_INTF_BW_20MHZ_AT_0MHZ_ANT0:\n\t\t\tprintk(\"%s hw_init mode DDC_BW_20MHZ_AT_0MHZ\\n\", rx_intf_compatible_str);\n\t\t\tmixer_cfg = 0x300200F4;\n\t\t\tant_sel=0;\n\t\t\tbreak;\n\n\t\tcase RX_INTF_BW_20MHZ_AT_0MHZ_ANT1:\n\t\t\tprintk(\"%s hw_init mode DDC_BW_20MHZ_AT_0MHZ\\n\", rx_intf_compatible_str);\n\t\t\tmixer_cfg = 0x300200F4;\n\t\t\tant_sel=1;\n\t\t\tbreak;\n\n\t\tcase RX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0:\n\t\t\tprintk(\"%s hw_init mode DDC_BW_20MHZ_AT_N_10MHZ\\n\", rx_intf_compatible_str);\n\t\t\tmixer_cfg = 0x300202F6;\n\t\t\tant_sel=0;\n\t\t\tbreak;\n\n\t\tcase RX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1:\n\t\t\tprintk(\"%s hw_init mode DDC_BW_20MHZ_AT_N_10MHZ\\n\", rx_intf_compatible_str);\n\t\t\tmixer_cfg = 0x300202F6;\n\t\t\tant_sel=1;\n\t\t\tbreak;\n\n\t\tcase RX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0:\n\t\t\tprintk(\"%s hw_init mode DDC_BW_20MHZ_AT_P_10MHZ\\n\", rx_intf_compatible_str);\n\t\t\tmixer_cfg = 0x3001F602;\n\t\t\tant_sel=0;\n\t\t\tbreak;\n\n\t\tcase RX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1:\n\t\t\tprintk(\"%s hw_init mode DDC_BW_20MHZ_AT_P_10MHZ\\n\", rx_intf_compatible_str);\n\t\t\tmixer_cfg = 0x3001F602;\n\t\t\tant_sel=1;\n\t\t\tbreak;\n\n\t\tcase RX_INTF_BYPASS:\n\t\t\tprintk(\"%s hw_init mode DDC_BYPASS\\n\", rx_intf_compatible_str);\n\t\t\tmixer_cfg = 0x3001F602;\n\t\t\tbreak;\n\t\t\n\t\tdefault:\n\t\t\tprintk(\"%s hw_init mode %d is wrong!\\n\", rx_intf_compatible_str, mode);\n\t\t\terr=1;\n\t}\n\n\tif (mode!=RX_INTF_AXIS_LOOP_BACK) {\n\t\t// rx_intf_api->RX_INTF_REG_MIXER_CFG_write(mixer_cfg); --now rx doesn't have mixer anymore\n\t\t// 0x000202F6 for: wifi ant0: -10MHz; wifi ant1: +10MHz; zigbee 4 ch ant0: -2, -7, -12, -17MHz; zigbee 4 ch ant1: +3, +8, +13, +18MHz\n\t\t// 0x0001F602 for: wifi ant0: +10MHz; wifi ant1: -10MHz; zigbee 4 ch ant0: +3, +8, +13, +18MHz; zigbee 4 ch ant1: -2, -7, -12, -17MHz\n\t\t// 0x0001F206 for: wifi ant0: -10MHz; wifi ant1: +10MHz; zigbee 4 ch ant0: +3, +8, +13, +18MHz; zigbee 4 ch ant1: -2, -7, -12, -17MHz\n\t\t// 0x2101F602 for: wifi gain 4;   zigbee gain 2\n\t\t// 0xFE01F602 for: wifi gain 1/2; zigbee gain 1/4\n\t\t// bits definitions:\n\t\t// wifi ch selection:     ant0 bit1~0; ant1 bit 9~8; ch offset: 0-0MHz; 1-5MHz; 2-10MHz; 3-15MHz(severe distortion)\n\t\t// wifi ch +/- selection: ant0 bit2; ant1 bit 10; 0-positive; 1-negative\n\t\t// zigbee 2M mixer +/- selection:        ant0   bit3; ant1    bit 11; 0-positive; 1-negative\n\t\t// zigbee secondary mixer +/- selection: ant0 bit4~7; ant1 bit 12~15; 0-positive; 1-negative\n\t\t// zigbee ch slip offset:                ant0  bit16; ant1     bit17; 0-select ch offset 0, 5, 10, 15; 1-select ch offset 5 10 15 20\n\t\t// wifi gain: bit31~28; number of bits shifted to left in 2'complement code\n\t\t// zigb gain: bit27~24; number of bits shifted to left in 2'complement code\n\t\t// max amplitude calibration info (agc low, ddc w/o gain adj 0x0001F602): 5GHz, max amplitude 1.26e4. According to simulation, schr shrink 1bit should be enough\n\t\t\n\t\trx_intf_api->RX_INTF_REG_MULTI_RST_write(0);\n\t\trx_intf_api->RX_INTF_REG_M_AXIS_RST_write(1); // hold M AXIS in reset status. will be released when openwifi_start\n\t\t\n\t\t//rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_write(0x000);\n\t\trx_intf_api->RX_INTF_REG_INTERRUPT_TEST_write(0x100);\n\t\t//0x000-normal; 0x100-sig and fcs valid are controlled by bit4 and bit0;\n\t\t//0x111-sig and fcs high; 0x110-sig high fcs low; 0x101-sig low fcs high; 0x100-sig and fcs low\n\n\t\trx_intf_api->RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write(30*10); // delayed interrupt, counter clock 10MHz is assumed\n\t\t\n\t\trx_intf_api->RX_INTF_REG_IQ_CTRL_write(0);\n\t\trx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_write(0x10025); //now bit 5 should be 1 to let pl_to_m_axis_intf decide num_dma_symbol_to_ps automatically\n\t\t//rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_write(0x00025); //bit16 enable_m_axis_auto_rst\n\t\t//bit2-0: source of M AXIS transfer trigger\n\t\t//\t\t -0 fcs_valid_from_acc\n\t\t//\t\t -1 sig_valid_from_acc\n\t\t//\t\t -2 sig_invalid_from_acc\n\t\t//\t\t -3 start_1trans_s_axis_tlast_trigger\n\t\t//\t\t -4 start_1trans_s_axis_tready_trigger\n\t\t//\t\t -5 internal state machine together with bit5 1. By parsing signal field, num_dma_symbol_to_ps can be decided automatically\n\t\t//\t\t -6 start_1trans_monitor_dma_to_ps_start_trigger\n\t\t//\t\t -7 start_1trans_ext_trigger\n\t\t//bit3:  1-fcs valid and invalid both connected; 0-only fcs valid connected (fcs_invalid_mode)\n\t\t//bit4:  1-num_dma_symbol_to_pl from monitor; 0-num_dma_symbol_to_pl from slv_reg8\n\t\t//bit5:  1-num_dma_symbol_to_ps from monitor; 0-num_dma_symbol_to_ps from slv_reg9\n\t\t//bit6:  1-pl_to_m_axis_intf will try to send both ht and non-ht; 0-only send non-ht\n\t\t//bit8:  1-endless S AXIS; 0-normal\n\t\t//bit9:  1-endless M AXIS; 0-normal\n\t\t//bit12: 1-direct loop back; 0-normal\n\t\t//bit16: 1-auto m_axis rst (sig_valid_from_acc|sig_invalid_from_acc|ht_sig_valid|ht_sig_invalid|ht_unsupported); 0-normal\n\t\t//bit24: 1-disable m_axis fifo_rst_by_fcs_invalid; 0-enable\n\t\t//bit29,28: sig_valid_mode. 0- non-ht sig valid; 1- ht sig valid other- both\n\t\trx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write(OPENWIFI_MAX_SIGNAL_LEN_TH<<16); //bit31~16 max pkt length threshold\n\t\trx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write(0);\n\t\t// 0-wifi_rx packet out; 1-loopback from input of wifi_rx\n\t\t\n\t\trx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write(num_dma_symbol_to_pl);\n\t\trx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(num_dma_symbol_to_ps);\n\t\trx_intf_api->RX_INTF_REG_CFG_DATA_TO_ANT_write(1<<8);\n\t\trx_intf_api->RX_INTF_REG_BB_GAIN_write(4);\n\n    // Remove RX_INTF_REG_ANT_SEL_write to avoid hw_init call in openwifi_start causing inconsistency\n\t\t// rx_intf_api->RX_INTF_REG_ANT_SEL_write(ant_sel);\n\n\t\trx_intf_api->RX_INTF_REG_MULTI_RST_write(0x14);//rst m/s axis\n\t\trx_intf_api->RX_INTF_REG_MULTI_RST_write(0);\n\t\trx_intf_api->RX_INTF_REG_M_AXIS_RST_write(1); // hold M AXIS in reset status. will be released when openwifi_start\n\t}\n\n\tif (mode==RX_INTF_BYPASS) {\n\t\trx_intf_api->RX_INTF_REG_CFG_DATA_TO_ANT_write(0x10); //bit4 bypass enable\n\t}\n\n\tprintk(\"%s hw_init err %d\\n\", rx_intf_compatible_str, err);\n\treturn(err);\n}\n\nstatic int dev_probe(struct platform_device *pdev)\n{\n\tstruct device_node *np = pdev->dev.of_node;\n\tstruct resource *io;\n\tint err=1;\n\n\tprintk(\"\\n\");\n\n\tif (np) {\n\t\tconst struct of_device_id *match;\n\n\t\tmatch = of_match_node(dev_of_ids, np);\n\t\tif (match) {\n\t\t\tprintk(\"%s dev_probe match!\\n\", rx_intf_compatible_str);\n\t\t\terr = 0;\n\t\t}\n\t}\n\n\tif (err)\n\t\treturn err;\n\n\trx_intf_api->hw_init=hw_init;\n\n\trx_intf_api->reg_read=reg_read;\n\trx_intf_api->reg_write=reg_write;\n\n\trx_intf_api->RX_INTF_REG_MULTI_RST_read=RX_INTF_REG_MULTI_RST_read;\n\trx_intf_api->RX_INTF_REG_MIXER_CFG_read=RX_INTF_REG_MIXER_CFG_read;\n\trx_intf_api->RX_INTF_REG_IQ_SRC_SEL_read=RX_INTF_REG_IQ_SRC_SEL_read;\n\trx_intf_api->RX_INTF_REG_IQ_CTRL_read=RX_INTF_REG_IQ_CTRL_read;\n\trx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_read=RX_INTF_REG_START_TRANS_TO_PS_MODE_read;\n\trx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_read=RX_INTF_REG_START_TRANS_TO_PS_read;\n\trx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_read=RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_read;\n\trx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read=RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read;\n\trx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read=RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read;\n\trx_intf_api->RX_INTF_REG_CFG_DATA_TO_ANT_read=RX_INTF_REG_CFG_DATA_TO_ANT_read;\n\trx_intf_api->RX_INTF_REG_ANT_SEL_read=RX_INTF_REG_ANT_SEL_read;\n\trx_intf_api->RX_INTF_REG_INTERRUPT_TEST_read=RX_INTF_REG_INTERRUPT_TEST_read;\n\n\trx_intf_api->RX_INTF_REG_MULTI_RST_write=RX_INTF_REG_MULTI_RST_write;\n\trx_intf_api->RX_INTF_REG_M_AXIS_RST_write=RX_INTF_REG_M_AXIS_RST_write;\n\trx_intf_api->RX_INTF_REG_MIXER_CFG_write=RX_INTF_REG_MIXER_CFG_write;\n\trx_intf_api->RX_INTF_REG_IQ_SRC_SEL_write=RX_INTF_REG_IQ_SRC_SEL_write;\n\trx_intf_api->RX_INTF_REG_IQ_CTRL_write=RX_INTF_REG_IQ_CTRL_write;\n\trx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_write=RX_INTF_REG_START_TRANS_TO_PS_MODE_write;\n\trx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write=RX_INTF_REG_START_TRANS_TO_PS_write;\n\trx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write=RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write;\n\trx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write=RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write;\n\trx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write=RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write;\n\trx_intf_api->RX_INTF_REG_CFG_DATA_TO_ANT_write=RX_INTF_REG_CFG_DATA_TO_ANT_write;\n\trx_intf_api->RX_INTF_REG_BB_GAIN_write=RX_INTF_REG_BB_GAIN_write;\n\trx_intf_api->RX_INTF_REG_ANT_SEL_write=RX_INTF_REG_ANT_SEL_write;\n\trx_intf_api->RX_INTF_REG_INTERRUPT_TEST_write=RX_INTF_REG_INTERRUPT_TEST_write;\n\n\trx_intf_api->RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write=RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write;\n\trx_intf_api->RX_INTF_REG_TLAST_TIMEOUT_TOP_write=RX_INTF_REG_TLAST_TIMEOUT_TOP_write;\n\n\t/* Request and map I/O memory */\n\tio = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n\tbase_addr = devm_ioremap_resource(&pdev->dev, io);\n\tif (IS_ERR(base_addr))\n\t\treturn PTR_ERR(base_addr);\n\n\trx_intf_api->io_start = io->start;\n\trx_intf_api->base_addr = (u32)base_addr;\n\n\tprintk(\"%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\\n\", rx_intf_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc);\n\tprintk(\"%s dev_probe base_addr 0x%08x\\n\", rx_intf_compatible_str,(u32)base_addr);\n\tprintk(\"%s dev_probe rx_intf_driver_api_inst 0x%08x\\n\", rx_intf_compatible_str, (u32)(&rx_intf_driver_api_inst) );\n\tprintk(\"%s dev_probe             rx_intf_api 0x%08x\\n\", rx_intf_compatible_str, (u32)rx_intf_api);\n\n\tprintk(\"%s dev_probe succeed!\\n\", rx_intf_compatible_str);\n\n\t//err = hw_init(DDC_CURRENT_CH_OFFSET_CFG,8,8);\n\terr = hw_init(RX_INTF_BW_20MHZ_AT_0MHZ_ANT0,8,8);\n\n\treturn err;\n}\n\nstatic int dev_remove(struct platform_device *pdev)\n{\n\tprintk(\"\\n\");\n\n\tprintk(\"%s dev_remove base_addr 0x%08x\\n\", rx_intf_compatible_str, (u32)base_addr);\n\tprintk(\"%s dev_remove rx_intf_driver_api_inst 0x%08x\\n\", rx_intf_compatible_str, (u32)(&rx_intf_driver_api_inst) );\n\tprintk(\"%s dev_remove             rx_intf_api 0x%08x\\n\", rx_intf_compatible_str, (u32)rx_intf_api);\n\n\tprintk(\"%s dev_remove succeed!\\n\", rx_intf_compatible_str);\n\treturn 0;\n}\n\nstatic struct platform_driver dev_driver = {\n\t.driver = {\n\t\t.name = \"sdr,rx_intf\",\n\t\t.owner = THIS_MODULE,\n\t\t.of_match_table = dev_of_ids,\n\t},\n\t.probe = dev_probe,\n\t.remove = dev_remove,\n};\n\nmodule_platform_driver(dev_driver);\n\nMODULE_AUTHOR(\"Xianjun Jiao\");\nMODULE_DESCRIPTION(\"sdr,rx_intf\");\nMODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "driver/sdr.c",
    "content": "// Author: Xianjun Jiao, Michael Mehari, Wei Liu, Jetmir Haxhibeqiri, Pablo Avila Campos\n// SPDX-FileCopyrightText: 2022 UGent\n// SPDX-License-Identifier: AGPL-3.0-or-later\n\n#include <linux/bitops.h>\n#include <linux/dmapool.h>\n#include <linux/io.h>\n#include <linux/iopoll.h>\n#include <linux/of_address.h>\n#include <linux/of_platform.h>\n#include <linux/of_irq.h>\n#include <linux/slab.h>\n#include <linux/clk.h>\n#include <linux/io-64-nonatomic-lo-hi.h>\n\n#include <linux/delay.h>\n#include <linux/interrupt.h>\n\n#include <linux/dmaengine.h>\n#include <linux/slab.h>\n#include <linux/delay.h>\n#include <linux/etherdevice.h>\n\n#include <linux/init.h>\n#include <linux/kthread.h>\n#include <linux/module.h>\n#include <linux/of_dma.h>\n#include <linux/platform_device.h>\n#include <linux/random.h>\n#include <linux/slab.h>\n#include <linux/wait.h>\n#include <linux/sched/task.h>\n#include <linux/dma/xilinx_dma.h>\n#include <linux/spi/spi.h>\n#include <net/mac80211.h>\n\n#include <linux/clk.h>\n#include <linux/clkdev.h>\n#include <linux/clk-provider.h>\n\n#include <linux/iio/iio.h>\n#include <linux/iio/sysfs.h>\n\n#include <linux/gpio.h>\n#include <linux/leds.h>\n\n// #include <linux/time.h>\n\n#define IIO_AD9361_USE_PRIVATE_H_\n#include <../../drivers/iio/adc/ad9361_regs.h>\n#include <../../drivers/iio/adc/ad9361.h>\n#include <../../drivers/iio/adc/ad9361_private.h>\n#include <../../drivers/iio/frequency/cf_axi_dds.h>\n\n#include \"../user_space/sdrctl_src/nl80211_testmode_def.h\"\n#include \"hw_def.h\"\n#include \"sdr.h\"\n#include \"git_rev.h\"\n\n#ifndef RFSoC4x2\nextern int ad9361_do_calib_run(struct ad9361_rf_phy *phy, u32 cal, int arg); \nextern int cf_axi_dds_datasel(struct cf_axi_dds_state *st, int channel, enum dds_data_select sel);\nextern struct ad9361_rf_phy* ad9361_spi_to_phy(struct spi_device *spi);\nextern int ad9361_tx_mute(struct ad9361_rf_phy *phy, u32 state);\nextern int ad9361_ctrl_outs_setup(struct ad9361_rf_phy *phy, struct ctrl_outs_control *ctrl);\nextern int ad9361_set_tx_atten(struct ad9361_rf_phy *phy, u32 atten_mdb, bool tx1, bool tx2, bool immed);\nextern int ad9361_spi_read(struct spi_device *spi, u32 reg);\nextern int ad9361_get_tx_atten(struct ad9361_rf_phy *phy, u32 tx_num);\n#else\nint ad9361_do_calib_run(struct ad9361_rf_phy *phy, u32 cal, int arg){return(0);}; \nint cf_axi_dds_datasel(struct cf_axi_dds_state *st, int channel, enum dds_data_select sel){return(0);}; \nstruct ad9361_rf_phy* ad9361_spi_to_phy(struct spi_device *spi){return(0);}; \nint ad9361_tx_mute(struct ad9361_rf_phy *phy, u32 state){return(0);}; \nint ad9361_ctrl_outs_setup(struct ad9361_rf_phy *phy, struct ctrl_outs_control *ctrl){return(0);}; \nint ad9361_set_tx_atten(struct ad9361_rf_phy *phy, u32 atten_mdb, bool tx1, bool tx2, bool immed){return(0);}; \nint ad9361_spi_read(struct spi_device *spi, u32 reg){return(0);}; \nint ad9361_get_tx_atten(struct ad9361_rf_phy *phy, u32 tx_num){return(0);};\n#endif\nstatic struct ad9361_rf_phy ad9361_phy_fake;\nstatic struct ad9361_rf_phy_state ad9361_phy_state_fake;\n\n// driver API of component driver\nextern struct tx_intf_driver_api *tx_intf_api;\nextern struct rx_intf_driver_api *rx_intf_api;\nextern struct openofdm_tx_driver_api *openofdm_tx_api;\nextern struct openofdm_rx_driver_api *openofdm_rx_api;\nextern struct xpu_driver_api *xpu_api;\n\nu32 gen_mpdu_crc(u8 *data_in, u32 num_bytes);\nu8 gen_mpdu_delim_crc(u16 m);\nu32 reverse32(u32 d);\nstatic int openwifi_set_antenna(struct ieee80211_hw *dev, u32 tx_ant, u32 rx_ant);\nstatic int openwifi_get_antenna(struct ieee80211_hw *dev, u32 *tx_ant, u32 *rx_ant);\nint rssi_half_db_to_rssi_dbm(int rssi_half_db, int rssi_correction);\nint rssi_dbm_to_rssi_half_db(int rssi_dbm, int rssi_correction);\nint rssi_correction_lookup_table(u32 freq_MHz);\nvoid ad9361_tx_calibration(struct openwifi_priv *priv, u32 actual_tx_lo);\nvoid openwifi_rf_rx_update_after_tuning(struct openwifi_priv *priv, u32 actual_rx_lo);\nstatic void ad9361_rf_set_channel(struct ieee80211_hw *dev, struct ieee80211_conf *conf);\nstatic void rfsoc_rf_set_channel(struct ieee80211_hw *dev, struct ieee80211_conf *conf);\n\n#include \"sdrctl_intf.c\"\n#include \"sysfs_intf.c\"\n\n// bit0: aggregation enable(1)/disable(0); \n// bit1: tx offset tuning enable(0)/disable(1). NO USE ANY MORE\n// bit1: short GI enable(1)/disable(0); \nstatic int test_mode = 0; \n// Internal indication variables after parsing test_mode\nstatic bool AGGR_ENABLE = false;\nstatic bool TX_OFFSET_TUNING_ENABLE = false;\n\nstatic int init_tx_att = 0;\n\nMODULE_AUTHOR(\"Xianjun Jiao\");\nMODULE_DESCRIPTION(\"SDR driver\");\nMODULE_LICENSE(\"GPL v2\");\n\nmodule_param(test_mode, int, 0);\nMODULE_PARM_DESC(myint, \"test_mode. bit0: aggregation enable(1)/disable(0)\");\n\nmodule_param(init_tx_att, int, 0);\nMODULE_PARM_DESC(myint, \"init_tx_att. TX attenuation in dB*1000  example: set to 3000 for 3dB attenuation\");\n\n// ---------------rfkill---------------------------------------\nstatic bool openwifi_is_radio_enabled(struct openwifi_priv *priv)\n{\n  int reg;\n\n  if (priv->tx_intf_cfg==TX_INTF_BW_20MHZ_AT_0MHZ_ANT0 || priv->tx_intf_cfg==TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0 || priv->tx_intf_cfg==TX_INTF_BW_20MHZ_AT_0MHZ_ANT_BOTH)\n    reg = ad9361_get_tx_atten(priv->ad9361_phy, 1);\n  else\n    reg = ad9361_get_tx_atten(priv->ad9361_phy, 2);\n\n  // if (reg == (AD9361_RADIO_ON_TX_ATT+priv->rf_reg_val[RF_TX_REG_IDX_ATT]))\n  if (reg < AD9361_RADIO_OFF_TX_ATT)\n    return true;// 0 off, 1 on\n  return false;\n}\n\nvoid openwifi_rfkill_init(struct ieee80211_hw *hw)\n{\n  struct openwifi_priv *priv = hw->priv;\n\n  priv->rfkill_off = openwifi_is_radio_enabled(priv);\n  printk(\"%s openwifi_rfkill_init: wireless switch is %s\\n\", sdr_compatible_str, priv->rfkill_off ? \"on\" : \"off\");\n  wiphy_rfkill_set_hw_state(hw->wiphy, !priv->rfkill_off);\n  wiphy_rfkill_start_polling(hw->wiphy);\n}\n\nvoid openwifi_rfkill_poll(struct ieee80211_hw *hw)\n{\n  bool enabled;\n  struct openwifi_priv *priv = hw->priv;\n\n  enabled = openwifi_is_radio_enabled(priv);\n  // printk(\"%s openwifi_rfkill_poll: wireless radio switch turned %s\\n\", sdr_compatible_str, enabled ? \"on\" : \"off\");\n  if (unlikely(enabled != priv->rfkill_off)) {\n    priv->rfkill_off = enabled;\n    printk(\"%s openwifi_rfkill_poll: WARNING wireless radio switch turned %s\\n\", sdr_compatible_str, enabled ? \"on\" : \"off\");\n    wiphy_rfkill_set_hw_state(hw->wiphy, !enabled);\n  }\n}\n\nvoid openwifi_rfkill_exit(struct ieee80211_hw *hw)\n{\n  printk(\"%s openwifi_rfkill_exit\\n\", sdr_compatible_str);\n  wiphy_rfkill_stop_polling(hw->wiphy);\n}\n//----------------rfkill end-----------------------------------\n\ninline int rssi_dbm_to_rssi_half_db(int rssi_dbm, int rssi_correction)\n{\n  return ((rssi_correction+rssi_dbm)<<1);\n}\n\ninline u8 freq_MHz_to_band(u32 freq_MHz)\n{\n  //we choose 3822=(5160+2484)/2 for calibration to avoid treating 5140 as 2.4GHz\n  if (freq_MHz < OPENWIFI_FREQ_MHz_TH_FOR_2_4GHZ_5GHZ) {\n    return(BAND_2_4GHZ);\n  } else {//use this BAND_5_8GHZ to represent all frequencies above OPENWIFI_FREQ_TH_FOR_2_4GHZ_5GHZ\n    return(BAND_5_8GHZ);\n  }\n}\n\ninline int rssi_correction_lookup_table(u32 freq_MHz)\n{\n  int rssi_correction;\n\n  if (freq_MHz<2412) {\n    rssi_correction = 153;\n  } else if (freq_MHz<=2484) {\n    rssi_correction = 153;\n  // } else if (freq_MHz<5160) {\n  } else if (freq_MHz<OPENWIFI_FREQ_MHz_TH_FOR_2_4GHZ_5GHZ) { //use middle point (5160+2484)/2 for calibration to avoid treating 5140 as 2.4GHz\n    rssi_correction = 153;\n  } else if (freq_MHz<=5240) {\n    rssi_correction = 145;\n  } else if (freq_MHz<=5320) {\n    rssi_correction = 145;\n  } else {\n    rssi_correction = 145;\n  }\n\n  return rssi_correction;\n}\n\ninline void ad9361_tx_calibration(struct openwifi_priv *priv, u32 actual_tx_lo)\n{\n  // struct timespec64 tv;\n  // unsigned long time_before = 0; \n  // unsigned long time_after = 0;\n  u32 spi_disable; \n\n  priv->last_tx_quad_cal_lo = actual_tx_lo; \n  // do_gettimeofday(&tv);\n  // time_before = tv.tv_usec + ((u64)1000000ull)*((u64)tv.tv_sec );\n  spi_disable = xpu_api->XPU_REG_SPI_DISABLE_read(); // backup current fpga spi disable state\n  xpu_api->XPU_REG_SPI_DISABLE_write(1); // disable FPGA SPI module\n  ad9361_do_calib_run(priv->ad9361_phy, TX_QUAD_CAL, (int)priv->ad9361_phy->state->last_tx_quad_cal_phase); \n  xpu_api->XPU_REG_SPI_DISABLE_write(spi_disable); // restore original SPI disable state \n  // do_gettimeofday(&tv);\n  // time_after = tv.tv_usec + ((u64)1000000ull)*((u64)tv.tv_sec );\n\n  // printk(\"%s ad9361_tx_calibration %dMHz tx_quad_cal duration %lu us\\n\", sdr_compatible_str, actual_tx_lo, time_after-time_before);\n  printk(\"%s ad9361_tx_calibration %dMHz tx_quad_cal duration unknown us\\n\", sdr_compatible_str, actual_tx_lo);\n}\n\ninline void openwifi_rf_rx_update_after_tuning(struct openwifi_priv *priv, u32 actual_rx_lo)\n{\n  int static_lbt_th, auto_lbt_th, fpga_lbt_th, receiver_rssi_dbm_th, receiver_rssi_th;\n\n  // get rssi correction value from lookup table\n  priv->rssi_correction = rssi_correction_lookup_table(actual_rx_lo);\n\n  // set appropriate lbt threshold\n  auto_lbt_th = rssi_dbm_to_rssi_half_db(-62, priv->rssi_correction); // -62dBm\n  static_lbt_th = rssi_dbm_to_rssi_half_db(-(priv->drv_xpu_reg_val[DRV_XPU_REG_IDX_LBT_TH]), priv->rssi_correction);\n  fpga_lbt_th = (priv->drv_xpu_reg_val[DRV_XPU_REG_IDX_LBT_TH]==0?auto_lbt_th:static_lbt_th);\n  xpu_api->XPU_REG_LBT_TH_write(fpga_lbt_th);\n  priv->last_auto_fpga_lbt_th = auto_lbt_th;\n\n  // Set rssi_half_db threshold (-85dBm equivalent) to receiver. Receiver will not react to signal lower than this rssi. See test records (OPENOFDM_RX_POWER_THRES_INIT in hw_def.h)\n  receiver_rssi_dbm_th = (priv->drv_rx_reg_val[DRV_RX_REG_IDX_DEMOD_TH]==0?OPENOFDM_RX_RSSI_DBM_TH_DEFAULT:(-priv->drv_rx_reg_val[DRV_RX_REG_IDX_DEMOD_TH]));\n  receiver_rssi_th = rssi_dbm_to_rssi_half_db(receiver_rssi_dbm_th, priv->rssi_correction);\n  openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write((OPENOFDM_RX_DC_RUNNING_SUM_TH_INIT<<16)|receiver_rssi_th);\n\n  xpu_api->XPU_REG_BAND_CHANNEL_write( (priv->use_short_slot<<24)|(priv->band<<16)|actual_rx_lo );\n\n  printk(\"%s openwifi_rf_rx_update_after_tuning %dMHz rssi_correction %d fpga_lbt_th %d(%ddBm) auto %d static %d receiver th %d(%ddBm)\\n\", sdr_compatible_str,\n  actual_rx_lo, priv->rssi_correction, fpga_lbt_th, rssi_half_db_to_rssi_dbm(fpga_lbt_th, priv->rssi_correction), auto_lbt_th, static_lbt_th, receiver_rssi_th, receiver_rssi_dbm_th);\n}\n\nstatic void rfsoc_rf_set_channel(struct ieee80211_hw *dev,\n          struct ieee80211_conf *conf)\n{\n\n}\n\nstatic void ad9361_rf_set_channel(struct ieee80211_hw *dev,\n          struct ieee80211_conf *conf)\n{\n\n  struct openwifi_priv *priv = dev->priv;\n  u32 actual_rx_lo;\n  u32 actual_tx_lo;\n  u32 diff_tx_lo; \n  bool change_flag;\n\n  actual_rx_lo = conf->chandef.chan->center_freq - priv->rx_freq_offset_to_lo_MHz;\n  change_flag = (actual_rx_lo != priv->actual_rx_lo);\n\n  printk(\"%s ad9361_rf_set_channel target %dMHz rx offset %dMHz current %dMHz change flag %d\\n\", sdr_compatible_str, \n  conf->chandef.chan->center_freq, priv->rx_freq_offset_to_lo_MHz, priv->actual_rx_lo, change_flag);\n\n  // if (change_flag && priv->rf_reg_val[RF_TX_REG_IDX_FREQ_MHZ]==0 && priv->rf_reg_val[RF_RX_REG_IDX_FREQ_MHZ]==0) {\n  if (change_flag) {\n    actual_tx_lo = conf->chandef.chan->center_freq - priv->tx_freq_offset_to_lo_MHz;\n    diff_tx_lo = priv->last_tx_quad_cal_lo > actual_tx_lo ? priv->last_tx_quad_cal_lo - actual_tx_lo : actual_tx_lo - priv->last_tx_quad_cal_lo;\n\n    printk(\"%s ad9361_rf_set_channel target %dMHz tx offset %dMHz current %dMHz diff_tx_lo %dMHz\\n\", sdr_compatible_str, \n    conf->chandef.chan->center_freq, priv->tx_freq_offset_to_lo_MHz, priv->actual_tx_lo, diff_tx_lo);\n\n    // -------------------Tx Lo tuning-------------------\n    clk_set_rate(priv->ad9361_phy->clks[TX_RFPLL], ( ((u64)1000000ull)*((u64)actual_tx_lo) )>>1);\n    priv->actual_tx_lo = actual_tx_lo;\n\n    // -------------------Rx Lo tuning-------------------\n    clk_set_rate(priv->ad9361_phy->clks[RX_RFPLL], ( ((u64)1000000ull)*((u64)actual_rx_lo) )>>1);\n    priv->actual_rx_lo = actual_rx_lo;\n\n    priv->band = freq_MHz_to_band(actual_rx_lo);\n    \n    // call Tx Quadrature calibration if frequency change is more than 100MHz \n    if (diff_tx_lo > 100)\n      ad9361_tx_calibration(priv, actual_tx_lo);\n\n    openwifi_rf_rx_update_after_tuning(priv, actual_rx_lo);\n    printk(\"%s ad9361_rf_set_channel %dMHz done\\n\", sdr_compatible_str,conf->chandef.chan->center_freq);\n  }\n}\n\nconst struct openwifi_rf_ops ad9361_rf_ops = {\n  .name    = \"ad9361\",\n//  .init    = ad9361_rf_init,\n//  .stop    = ad9361_rf_stop,\n  .set_chan  = ad9361_rf_set_channel,\n//  .calc_rssi  = ad9361_rf_calc_rssi,\n};\n\nconst struct openwifi_rf_ops rfsoc4x2_rf_ops = {\n  .name    = \"rfsoc4x2\",\n//  .init    = ad9361_rf_init,\n//  .stop    = ad9361_rf_stop,\n  .set_chan  = rfsoc_rf_set_channel,\n//  .calc_rssi  = ad9361_rf_calc_rssi,\n};\n\nu16 reverse16(u16 d) {\n  union u16_byte2 tmp0, tmp1;\n  tmp0.a = d;\n  tmp1.c[0] = tmp0.c[1];\n  tmp1.c[1] = tmp0.c[0];\n  return(tmp1.a);\n}\n\nu32 reverse32(u32 d) {\n  union u32_byte4 tmp0, tmp1;\n  tmp0.a = d;\n  tmp1.c[0] = tmp0.c[3];\n  tmp1.c[1] = tmp0.c[2];\n  tmp1.c[2] = tmp0.c[1];\n  tmp1.c[3] = tmp0.c[0];\n  return(tmp1.a);\n}\n\nstatic int openwifi_init_tx_ring(struct openwifi_priv *priv, int ring_idx)\n{\n  struct openwifi_ring *ring = &(priv->tx_ring[ring_idx]);\n  int i;\n\n  ring->stop_flag = -1;\n  ring->bd_wr_idx = 0;\n  ring->bd_rd_idx = 0;\n  ring->bds = kmalloc(sizeof(struct openwifi_buffer_descriptor)*NUM_TX_BD,GFP_KERNEL);\n  if (ring->bds==NULL) {\n    printk(\"%s openwifi_init_tx_ring: WARNING Cannot allocate TX ring\\n\",sdr_compatible_str);\n    return -ENOMEM;\n  }\n\n  for (i = 0; i < NUM_TX_BD; i++) {\n    ring->bds[i].skb_linked=NULL; // for tx, skb is from upper layer\n    //at first right after skb allocated, head, data, tail are the same.\n    ring->bds[i].dma_mapping_addr = 0; // for tx, mapping is done after skb is received from upper layer in tx routine\n    ring->bds[i].seq_no = 0xffff; // invalid value\n    ring->bds[i].prio = 0xff; // invalid value\n    ring->bds[i].len_mpdu = 0; // invalid value\n  }\n\n  return 0;\n}\n\nstatic void openwifi_free_tx_ring(struct openwifi_priv *priv, int ring_idx)\n{\n  struct openwifi_ring *ring = &(priv->tx_ring[ring_idx]);\n  int i;\n\n  ring->stop_flag = -1;\n  ring->bd_wr_idx = 0;\n  ring->bd_rd_idx = 0;\n  for (i = 0; i < NUM_TX_BD; i++) {\n    if (ring->bds[i].skb_linked == 0 && ring->bds[i].dma_mapping_addr == 0)\n      continue;\n    if (ring->bds[i].dma_mapping_addr != 0)\n      dma_unmap_single(priv->tx_chan->device->dev, ring->bds[i].dma_mapping_addr,ring->bds[i].skb_linked->len, DMA_MEM_TO_DEV);\n//    if (ring->bds[i].skb_linked!=NULL)\n//      dev_kfree_skb(ring->bds[i].skb_linked); // only use dev_kfree_skb when there is exception\n    if ( (ring->bds[i].dma_mapping_addr != 0 && ring->bds[i].skb_linked == 0) ||\n         (ring->bds[i].dma_mapping_addr == 0 && ring->bds[i].skb_linked != 0))\n      printk(\"%s openwifi_free_tx_ring: WARNING ring %d i %d skb_linked %p dma_mapping_addr %08x\\n\", sdr_compatible_str, \n      ring_idx, i, (void*)(ring->bds[i].skb_linked), (unsigned int)(ring->bds[i].dma_mapping_addr));\n\n    ring->bds[i].skb_linked=NULL;\n    ring->bds[i].dma_mapping_addr = 0;\n    ring->bds[i].seq_no = 0xffff; // invalid value\n    ring->bds[i].prio = 0xff; // invalid value\n    ring->bds[i].len_mpdu = 0; // invalid value\n  }\n  if (ring->bds)\n    kfree(ring->bds);\n  ring->bds = NULL;\n}\n\nstatic int openwifi_init_rx_ring(struct openwifi_priv *priv)\n{\n  int i;\n  u8 *pdata_tmp;\n\n  priv->rx_cyclic_buf = dma_alloc_coherent(priv->rx_chan->device->dev,RX_BD_BUF_SIZE*NUM_RX_BD,&priv->rx_cyclic_buf_dma_mapping_addr,GFP_KERNEL);\n  if (!priv->rx_cyclic_buf) {\n    printk(\"%s openwifi_init_rx_ring: WARNING dma_alloc_coherent failed!\\n\", sdr_compatible_str);\n    dma_free_coherent(priv->rx_chan->device->dev,RX_BD_BUF_SIZE*NUM_RX_BD,priv->rx_cyclic_buf,priv->rx_cyclic_buf_dma_mapping_addr);\n    return(-1);\n  }\n\n  // Set tsft_low and tsft_high to 0. If they are not zero, it means there is a packet in the buffer by DMA\n  for (i=0; i<NUM_RX_BD; i++) {\n    pdata_tmp = priv->rx_cyclic_buf + i*RX_BD_BUF_SIZE; // our header insertion is at the beginning\n    (*((u16*)(pdata_tmp+10))) = 0;\n  }\n  printk(\"%s openwifi_init_rx_ring: NUM_RX_BD %d RX_BD_BUF_SIZE %d pkt existing flag are cleared!\\n\", sdr_compatible_str,\n  NUM_RX_BD, RX_BD_BUF_SIZE);\n\n  return 0;\n}\n\nstatic void openwifi_free_rx_ring(struct openwifi_priv *priv)\n{\n  if (priv->rx_cyclic_buf)\n    dma_free_coherent(priv->rx_chan->device->dev,RX_BD_BUF_SIZE*NUM_RX_BD,priv->rx_cyclic_buf,priv->rx_cyclic_buf_dma_mapping_addr);\n\n  priv->rx_cyclic_buf_dma_mapping_addr = 0;\n  priv->rx_cyclic_buf = 0;\n}\n\nstatic int rx_dma_setup(struct ieee80211_hw *dev){\n  struct openwifi_priv *priv = dev->priv;\n  struct dma_device *rx_dev = priv->rx_chan->device;\n\n  priv->rxd = rx_dev->device_prep_dma_cyclic(priv->rx_chan,priv->rx_cyclic_buf_dma_mapping_addr,RX_BD_BUF_SIZE*NUM_RX_BD,RX_BD_BUF_SIZE,DMA_DEV_TO_MEM,DMA_CTRL_ACK|DMA_PREP_INTERRUPT);\n  if (!(priv->rxd)) {\n    openwifi_free_rx_ring(priv);\n    printk(\"%s rx_dma_setup: WARNING rx_dev->device_prep_dma_cyclic %p\\n\", sdr_compatible_str, (void*)(priv->rxd));\n    return(-1);\n  }\n  priv->rxd->callback = 0;\n  priv->rxd->callback_param = 0;\n\n  priv->rx_cookie = priv->rxd->tx_submit(priv->rxd);\n\n  if (dma_submit_error(priv->rx_cookie)) {\n    printk(\"%s rx_dma_setup: WARNING dma_submit_error(rx_cookie) %d\\n\", sdr_compatible_str, (u32)(priv->rx_cookie));\n    return(-1);\n  }\n\n  dma_async_issue_pending(priv->rx_chan);\n  return(0);\n}\n\ninline int rssi_half_db_to_rssi_dbm(int rssi_half_db, int rssi_correction) \n{\n  int rssi_db, rssi_dbm;\n\n  rssi_db = (rssi_half_db>>1);\n\n  rssi_dbm = rssi_db - rssi_correction;\n  \n  rssi_dbm = (rssi_dbm < (-128)? (-128) : rssi_dbm);\n  \n  return rssi_dbm;\n}\n\nstatic irqreturn_t openwifi_rx_interrupt(int irq, void *dev_id)\n{\n  struct ieee80211_hw *dev = dev_id;\n  struct openwifi_priv *priv = dev->priv;\n  struct ieee80211_rx_status rx_status = {0};\n  struct sk_buff *skb;\n  struct ieee80211_hdr *hdr;\n  u32 addr1_low32, addr2_low32=0, addr3_low32=0, len, rate_idx, tsft_low, tsft_high, loop_count=0;//, fc_di;\n  bool ht_flag, short_gi, ht_aggr, ht_aggr_last;\n  // u32 dma_driver_buf_idx_mod;\n  u8 *pdata_tmp;\n  u8 fcs_ok;//, target_buf_idx;//, phy_rx_sn_hw;\n  s8 signal, phase_offset;\n  u16 agc_status_and_pkt_exist_flag, rssi_half_db, addr1_high16, addr2_high16=0, addr3_high16=0, seq_no=0;\n  bool content_ok, len_overflow, is_unicast;\n\n#ifdef USE_NEW_RX_INTERRUPT\n  int i;\n  spin_lock(&priv->lock);\n  for (i=0; i<NUM_RX_BD; i++) {\n    pdata_tmp = priv->rx_cyclic_buf + i*RX_BD_BUF_SIZE;\n    agc_status_and_pkt_exist_flag = (*((u16*)(pdata_tmp+10))); //check rx_intf_pl_to_m_axis.v. FPGA TODO: add pkt exist 1bit flag next to gpio_status_lock_by_sig_valid\n    if ( agc_status_and_pkt_exist_flag==0 ) // no packet in the buffer\n      continue;\n#else\n  static u8 target_buf_idx_old = 0;\n  spin_lock(&priv->lock);\n  while(1) { // loop all rx buffers that have new rx packets\n    pdata_tmp = priv->rx_cyclic_buf + target_buf_idx_old*RX_BD_BUF_SIZE; // our header insertion is at the beginning\n    agc_status_and_pkt_exist_flag = (*((u16*)(pdata_tmp+10)));\n    if ( agc_status_and_pkt_exist_flag==0 ) // no packet in the buffer\n      break;\n#endif\n\n    tsft_low =     (*((u32*)(pdata_tmp+0 )));\n    tsft_high =    (*((u32*)(pdata_tmp+4 )));\n    rssi_half_db = (*((u16*)(pdata_tmp+8 )));\n    len =          (*((u16*)(pdata_tmp+12)));\n\n    len_overflow = (len>(RX_BD_BUF_SIZE-16)?true:false);\n\n    rate_idx =     (*((u16*)(pdata_tmp+14)));\n    ht_flag  =     ((rate_idx&0x10)!=0);\n    short_gi =     ((rate_idx&0x20)!=0);\n    ht_aggr  =     (ht_flag & ((rate_idx&0x40)!=0));\n    ht_aggr_last = (ht_flag & ((rate_idx&0x80)!=0));\n    phase_offset = (rate_idx>>8);\n    rate_idx =     (rate_idx&0x1F);\n\n    fcs_ok = ( len_overflow?0:(*(( u8*)(pdata_tmp+16+len-1))) );\n\n    //phy_rx_sn_hw = (fcs_ok&(NUM_RX_BD-1));\n    // phy_rx_sn_hw = (fcs_ok&0x7f);//0x7f is FPGA limitation\n    // dma_driver_buf_idx_mod = (state.residue&0x7f);\n    fcs_ok = ((fcs_ok&0x80)!=0);\n\n    if ( (len>=14 && (!len_overflow)) && (rate_idx>=8 && rate_idx<=23)) {\n      // if ( phy_rx_sn_hw!=dma_driver_buf_idx_mod) {\n      //   printk(\"%s openwifi_rx: WARNING sn %d next buf_idx %d!\\n\", sdr_compatible_str,phy_rx_sn_hw,dma_driver_buf_idx_mod);\n      // }\n      content_ok = true;\n    } else {\n      printk(\"%s openwifi_rx: WARNING content! len%d overflow%d rate_idx%d\\n\", sdr_compatible_str, \n      len, len_overflow, rate_idx);\n      content_ok = false;\n    }\n\n    signal = rssi_half_db_to_rssi_dbm(rssi_half_db, priv->rssi_correction);\n\n    hdr = (struct ieee80211_hdr *)(pdata_tmp+16);\n    if (len>=20) {\n      addr2_low32  = *((u32*)(hdr->addr2+2));\n      addr2_high16 = *((u16*)(hdr->addr2));\n    }\n\n    addr1_low32  = *((u32*)(hdr->addr1+2));\n    addr1_high16 = *((u16*)(hdr->addr1));\n\n    if ( priv->drv_rx_reg_val[DRV_RX_REG_IDX_PRINT_CFG]&DMESG_LOG_ANY ) {\n      if (len>=26) {\n        addr3_low32  = *((u32*)(hdr->addr3+2));\n        addr3_high16 = *((u16*)(hdr->addr3));\n      }\n      if (len>=28)\n        seq_no = ( (hdr->seq_ctrl&IEEE80211_SCTL_SEQ)>>4 );\n\n      is_unicast = (addr1_low32!=0xffffffff || addr1_high16!=0xffff);\n\n      if ( (( is_unicast)&&(priv->drv_rx_reg_val[DRV_RX_REG_IDX_PRINT_CFG]&DMESG_LOG_UNICAST))   ||\n           ((!is_unicast)&&(priv->drv_rx_reg_val[DRV_RX_REG_IDX_PRINT_CFG]&DMESG_LOG_BROADCAST)) ||\n         ((  fcs_ok==0)&&(priv->drv_rx_reg_val[DRV_RX_REG_IDX_PRINT_CFG]&DMESG_LOG_ERROR)) )\n        printk(\"%s openwifi_rx: %dB ht%daggr%d/%d sgi%d %dM FC%04x DI%04x ADDR%04x%08x/%04x%08x/%04x%08x SC%d fcs%d buf_idx%d %ddBm fo %d\\n\", sdr_compatible_str,\n          len, ht_flag, ht_aggr, ht_aggr_last, short_gi, wifi_rate_table[rate_idx], hdr->frame_control, hdr->duration_id, \n          reverse16(addr1_high16), reverse32(addr1_low32), reverse16(addr2_high16), reverse32(addr2_low32), reverse16(addr3_high16), reverse32(addr3_low32), \n#ifdef USE_NEW_RX_INTERRUPT\n          seq_no, fcs_ok, i, signal, phase_offset);\n#else\n          seq_no, fcs_ok, target_buf_idx_old, signal, phase_offset);\n#endif\n    }\n    \n    // priv->phy_rx_sn_hw_old = phy_rx_sn_hw;\n    if (content_ok) {\n      skb = dev_alloc_skb(len);\n      if (skb) {\n        skb_put_data(skb,pdata_tmp+16,len);\n\n        rx_status.antenna = priv->runtime_rx_ant_cfg;\n        // def in ieee80211_rate openwifi_rates 0~11. 0~3 11b(1M~11M), 4~11 11a/g(6M~54M)\n        rx_status.rate_idx = wifi_rate_table_mapping[rate_idx];\n        rx_status.signal = signal;\n\n        rx_status.freq = dev->conf.chandef.chan->center_freq;\n        // rx_status.freq = priv->actual_rx_lo;\n        rx_status.band = dev->conf.chandef.chan->band;\n        // rx_status.band = (rx_status.freq<2500?NL80211_BAND_2GHZ:NL80211_BAND_5GHZ);\n        \n        rx_status.mactime = ( ( (u64)tsft_low ) | ( ((u64)tsft_high)<<32 ) );\n        rx_status.flag |= RX_FLAG_MACTIME_START;\n        if (!fcs_ok)\n          rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;\n        if (rate_idx <= 15)\n          rx_status.encoding = RX_ENC_LEGACY;\n        else\n          rx_status.encoding = RX_ENC_HT;\n        rx_status.bw = RATE_INFO_BW_20;\n        if (short_gi)\n          rx_status.enc_flags |= RX_ENC_FLAG_SHORT_GI;\n        if(ht_aggr)\n        {\n          rx_status.ampdu_reference = priv->ampdu_reference;\n          rx_status.flag |= RX_FLAG_AMPDU_DETAILS | RX_FLAG_AMPDU_LAST_KNOWN;\n          if (ht_aggr_last)\n            rx_status.flag |= RX_FLAG_AMPDU_IS_LAST;\n        }\n\n        memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status)); // put rx_status into skb->cb, from now on skb->cb is not dma_dsts any more.\n        ieee80211_rx_irqsafe(dev, skb); // call mac80211 function\n\n        // printk(\"%s openwifi_rx: addr1_low32 %08x self addr %08x\\n\", sdr_compatible_str, addr1_low32, ( *( (u32*)(priv->mac_addr+2) ) ));\n        if (addr1_low32 == ( *( (u32*)(priv->mac_addr+2) ) ) && priv->stat.stat_enable) {\n          agc_status_and_pkt_exist_flag = (agc_status_and_pkt_exist_flag&0x7f);\n          if (len>=20) {// rx stat\n            if (addr2_low32 == priv->stat.rx_target_sender_mac_addr || priv->stat.rx_target_sender_mac_addr==0) {\n              if ( ieee80211_is_data(hdr->frame_control) ) {\n                priv->stat.rx_data_pkt_mcs_realtime = rate_idx;\n                priv->stat.rx_data_pkt_num_total++;\n                if (!fcs_ok) {\n                  priv->stat.rx_data_pkt_num_fail++;\n                  priv->stat.rx_data_pkt_fail_mcs_realtime = rate_idx;\n                  priv->stat.rx_data_fail_agc_gain_value_realtime = agc_status_and_pkt_exist_flag;\n                } else {\n                  priv->stat.rx_data_ok_agc_gain_value_realtime = agc_status_and_pkt_exist_flag;\n                }\n              } else if ( ieee80211_is_mgmt(hdr->frame_control) ) {\n                priv->stat.rx_mgmt_pkt_mcs_realtime = rate_idx;\n                priv->stat.rx_mgmt_pkt_num_total++;\n                if (!fcs_ok) {\n                  priv->stat.rx_mgmt_pkt_num_fail++;\n                  priv->stat.rx_mgmt_pkt_fail_mcs_realtime = rate_idx;\n                  priv->stat.rx_mgmt_fail_agc_gain_value_realtime = agc_status_and_pkt_exist_flag;\n                } else {\n                  priv->stat.rx_mgmt_ok_agc_gain_value_realtime = agc_status_and_pkt_exist_flag;\n                }\n              }\n            }\n          } else if ( ieee80211_is_ack(hdr->frame_control) ) {\n            priv->stat.rx_ack_pkt_mcs_realtime = rate_idx;\n            priv->stat.rx_ack_pkt_num_total++;\n            if (!fcs_ok) {\n              priv->stat.rx_ack_pkt_num_fail++;\n            } else {\n              priv->stat.rx_ack_ok_agc_gain_value_realtime = agc_status_and_pkt_exist_flag;\n            }\n          }\n        }\n      } else\n        printk(\"%s openwifi_rx: WARNING dev_alloc_skb failed!\\n\", sdr_compatible_str);\n\n      if(ht_aggr_last)\n        priv->ampdu_reference++;\n    }\n    (*((u16*)(pdata_tmp+10))) = 0; // clear the field (set by rx_intf_pl_to_m_axis.v) to indicate the packet has been processed\n    loop_count++;\n#ifndef USE_NEW_RX_INTERRUPT\n    target_buf_idx_old=((target_buf_idx_old+1)&(NUM_RX_BD-1)); \n#endif\n  }\n\n  if ( loop_count!=1 && (priv->drv_rx_reg_val[DRV_RX_REG_IDX_PRINT_CFG]&DMESG_LOG_ERROR) )\n    printk(\"%s openwifi_rx: WARNING loop_count %d\\n\", sdr_compatible_str,loop_count);\n  \n// openwifi_rx_out:\n  spin_unlock(&priv->lock);\n  return IRQ_HANDLED;\n}\n\nstatic irqreturn_t openwifi_tx_interrupt(int irq, void *dev_id)\n{\n  struct ieee80211_hw *dev = dev_id;\n  struct openwifi_priv *priv = dev->priv;\n  struct openwifi_ring *ring, *drv_ring_tmp;\n  struct sk_buff *skb;\n  struct ieee80211_tx_info *info;\n  struct ieee80211_hdr *hdr;\n  u32 reg_val1, hw_queue_len, reg_val2, dma_fifo_no_room_flag, num_slot_random, cw, loop_count=0, addr1_low32, mcs_for_sysfs;\n  u16 seq_no, pkt_cnt, blk_ack_ssn, start_idx;\n  u8 nof_retx=-1, last_bd_rd_idx, i, prio, queue_idx, nof_retx_stat;\n  u64 blk_ack_bitmap;\n  // u16 prio_rd_idx_store[64]={0};\n  bool tx_fail=false, fpga_queue_has_room=false;\n  bool use_ht_aggr, pkt_need_ack, use_ht_rate, prio_wake_up_flag = false;\n\n  spin_lock(&priv->lock);\n\n  while(1) { // loop all packets that have been sent by FPGA\n    reg_val1 = tx_intf_api->TX_INTF_REG_PKT_INFO1_read();\n        reg_val2 = tx_intf_api->TX_INTF_REG_PKT_INFO2_read();\n    blk_ack_bitmap = (tx_intf_api->TX_INTF_REG_PKT_INFO3_read() | ((u64)tx_intf_api->TX_INTF_REG_PKT_INFO4_read())<<32);\n\n    if (reg_val1!=0xFFFFFFFF) {\n      nof_retx = (reg_val1&0xF);\n      last_bd_rd_idx = ((reg_val1>>5)&(NUM_TX_BD-1));\n      prio = ((reg_val1>>17)&0x3);\n      num_slot_random = ((reg_val1>>19)&0x1FF);\n      //num_slot_random = ((0xFF80000 &reg_val1)>>(2+5+NUM_BIT_MAX_PHY_TX_SN+NUM_BIT_MAX_NUM_HW_QUEUE));\n      cw = ((reg_val1>>28)&0xF);\n      //cw = ((0xF0000000 & reg_val1) >> 28);\n      if(cw > 10) {\n        cw = 10 ;\n        num_slot_random += 512 ; \n      }\n      pkt_cnt = (reg_val2&0x3F);\n      blk_ack_ssn = ((reg_val2>>6)&0xFFF);\n\n      queue_idx = ((reg_val1>>15)&(MAX_NUM_HW_QUEUE-1));\n      dma_fifo_no_room_flag = tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read();\n      hw_queue_len = tx_intf_api->TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read();\n      // check which linux prio is stopped by this queue (queue_idx)\n      for (i=0; i<MAX_NUM_SW_QUEUE; i++) {\n        drv_ring_tmp = &(priv->tx_ring[i]);\n        if ( drv_ring_tmp->stop_flag == prio ) {\n\n          if ( ((dma_fifo_no_room_flag>>i)&1)==0 && (NUM_TX_BD-((hw_queue_len>>(i*8))&0xFF))>=RING_ROOM_THRESHOLD )\n            fpga_queue_has_room=true;\n          else\n            fpga_queue_has_room=false;\n\n          // Wake up Linux queue due to the current fpga queue releases some room\n          if( priv->drv_tx_reg_val[DRV_TX_REG_IDX_PRINT_CFG]&DMESG_LOG_NORMAL_QUEUE_STOP )\n            printk(\"%s openwifi_tx_interrupt: WARNING ieee80211_wake_queue prio%d i%d queue%d no room flag%x hwq len%08x wr%d rd%d\\n\", sdr_compatible_str,\n                    prio, i, queue_idx, dma_fifo_no_room_flag, hw_queue_len, drv_ring_tmp->bd_wr_idx, last_bd_rd_idx);\n            \n          if (fpga_queue_has_room) {\n            prio_wake_up_flag = true;\n            drv_ring_tmp->stop_flag = -1;\n\n            if (priv->stat.stat_enable) {\n              priv->stat.tx_prio_wakeup_num[prio]++;\n              priv->stat.tx_queue_wakeup_num[i]++;\n            }\n          } else {\n            if( priv->drv_tx_reg_val[DRV_TX_REG_IDX_PRINT_CFG]&DMESG_LOG_NORMAL_QUEUE_STOP )\n              printk(\"%s openwifi_tx_interrupt: WARNING no room! prio_wake_up_flag%d\\n\", sdr_compatible_str, prio_wake_up_flag);\n          }\n        }\n      }\n      if (prio_wake_up_flag)\n        ieee80211_wake_queue(dev, prio);\n\n      if (priv->stat.stat_enable) {\n        priv->stat.tx_prio_interrupt_num[prio] = priv->stat.tx_prio_interrupt_num[prio] + pkt_cnt;\n        priv->stat.tx_queue_interrupt_num[queue_idx] = priv->stat.tx_queue_interrupt_num[queue_idx] + pkt_cnt;\n      }\n\n      ring = &(priv->tx_ring[queue_idx]);\n      for(i = 1; i <= pkt_cnt; i++)\n      {\n        ring->bd_rd_idx = (last_bd_rd_idx + i - pkt_cnt + 64)%64;\n        seq_no = ring->bds[ring->bd_rd_idx].seq_no;\n\n        if (seq_no == 0xffff) {// it has been forced cleared by the openwifi_tx (due to out-of-order Tx of different queues to the air?)\n          printk(\"%s openwifi_tx_interrupt: WARNING wr%d rd%d last_bd_rd_idx%d i%d pkt_cnt%d prio%d fpga q%d hwq len%d bd prio%d len_mpdu%d seq_no%d skb_linked%p dma_mapping_addr%u\\n\", sdr_compatible_str,\n          ring->bd_wr_idx, ring->bd_rd_idx, last_bd_rd_idx, i, pkt_cnt, prio, queue_idx, hw_queue_len, ring->bds[ring->bd_rd_idx].prio, ring->bds[ring->bd_rd_idx].len_mpdu, seq_no, ring->bds[ring->bd_rd_idx].skb_linked, (long long int)(ring->bds[ring->bd_rd_idx].dma_mapping_addr));\n          continue;\n        }\n\n        skb = ring->bds[ring->bd_rd_idx].skb_linked;\n\n        dma_unmap_single(priv->tx_chan->device->dev,ring->bds[ring->bd_rd_idx].dma_mapping_addr,\n            skb->len, DMA_MEM_TO_DEV);\n\n        info = IEEE80211_SKB_CB(skb);\n        use_ht_aggr = ((info->flags&IEEE80211_TX_CTL_AMPDU)!=0);\n        ieee80211_tx_info_clear_status(info);\n\n        // Aggregation packet\n        if (use_ht_aggr)\n        {\n          start_idx = (seq_no>=blk_ack_ssn) ? (seq_no-blk_ack_ssn) : (seq_no+((~blk_ack_ssn+1)&0x0FFF));\n          tx_fail = (((blk_ack_bitmap>>start_idx)&0x1)==0);\n          info->flags |= IEEE80211_TX_STAT_AMPDU;\n          info->status.ampdu_len = 1;\n          info->status.ampdu_ack_len = (tx_fail == true) ? 0 : 1;\n\n          skb_pull(skb, LEN_MPDU_DELIM);\n          //skb_trim(skb, num_byte_pad_skb);\n        }\n        // Normal packet\n        else\n        {\n          tx_fail = ((blk_ack_bitmap&0x1)==0);\n          info->flags &= (~IEEE80211_TX_CTL_AMPDU);\n        }\n\n        pkt_need_ack = (!(info->flags & IEEE80211_TX_CTL_NO_ACK));\n        // do statistics for data packet that needs ack\n        hdr = (struct ieee80211_hdr *)skb->data;\n        addr1_low32  = *((u32*)(hdr->addr1+2));\n        if ( priv->stat.stat_enable && pkt_need_ack && (addr1_low32 == priv->stat.rx_target_sender_mac_addr || priv->stat.rx_target_sender_mac_addr==0) ) {\n          use_ht_rate = (((info->control.rates[0].flags)&IEEE80211_TX_RC_MCS)!=0);\n          mcs_for_sysfs = ieee80211_get_tx_rate(dev, info)->hw_value;\n          if (use_ht_rate)\n            mcs_for_sysfs = (mcs_for_sysfs | 0x80000000);\n          \n          if ( ieee80211_is_data(hdr->frame_control) ) {\n            nof_retx_stat = (nof_retx<=5?nof_retx:5);\n\n            priv->stat.tx_data_pkt_need_ack_num_total++;\n            priv->stat.tx_data_pkt_mcs_realtime = mcs_for_sysfs;\n            priv->stat.tx_data_pkt_need_ack_num_retx[nof_retx_stat]++;\n            if (tx_fail) {\n              priv->stat.tx_data_pkt_need_ack_num_total_fail++;\n              priv->stat.tx_data_pkt_fail_mcs_realtime = mcs_for_sysfs;\n              priv->stat.tx_data_pkt_need_ack_num_retx_fail[nof_retx_stat]++;\n            }\n          } else if ( ieee80211_is_mgmt(hdr->frame_control) ) {\n            nof_retx_stat = (nof_retx<=2?nof_retx:2);\n\n            priv->stat.tx_mgmt_pkt_need_ack_num_total++;\n            priv->stat.tx_mgmt_pkt_mcs_realtime = mcs_for_sysfs;\n            priv->stat.tx_mgmt_pkt_need_ack_num_retx[nof_retx_stat]++;\n            if (tx_fail) {\n              priv->stat.tx_mgmt_pkt_need_ack_num_total_fail++;\n              priv->stat.tx_mgmt_pkt_fail_mcs_realtime = mcs_for_sysfs;\n              priv->stat.tx_mgmt_pkt_need_ack_num_retx_fail[nof_retx_stat]++;\n            }\n          }\n        }\n\n        if ( tx_fail == false )\n          info->flags |= IEEE80211_TX_STAT_ACK;\n\n        info->status.rates[0].count = nof_retx + 1; //according to our test, the 1st rate is the most important. we only do retry on the 1st rate\n        info->status.rates[1].idx = -1;\n        // info->status.rates[2].idx = -1;\n        // info->status.rates[3].idx = -1;//in mac80211.h: #define IEEE80211_TX_MAX_RATES  4\n        info->status.antenna = priv->runtime_tx_ant_cfg;\n\n        if ( ( (!pkt_need_ack)&&(priv->drv_tx_reg_val[DRV_TX_REG_IDX_PRINT_CFG]&DMESG_LOG_BROADCAST) ) || ( (pkt_need_ack)&&(priv->drv_tx_reg_val[DRV_TX_REG_IDX_PRINT_CFG]&DMESG_LOG_UNICAST) ) ){\n          printk(\"%s openwifi_tx_interrupt: tx_result [nof_retx %d pass %d] SC%d prio%d q%d wr%d rd%d num_slot%d cw%d hwq len%08x no_room_flag%x\\n\", sdr_compatible_str,\n          nof_retx+1, !tx_fail, seq_no, prio, queue_idx, ring->bd_wr_idx, ring->bd_rd_idx, num_slot_random, cw, hw_queue_len, dma_fifo_no_room_flag);\n        }\n\n        ieee80211_tx_status_irqsafe(dev, skb);\n\n        ring->bds[ring->bd_rd_idx].prio = 0xff; // invalid value\n        ring->bds[ring->bd_rd_idx].len_mpdu = 0; // invalid value\n        ring->bds[ring->bd_rd_idx].seq_no = 0xffff;\n        ring->bds[ring->bd_rd_idx].skb_linked = NULL;\n        ring->bds[ring->bd_rd_idx].dma_mapping_addr = 0;\n      }\n      \n      loop_count++;\n      \n      // printk(\"%s openwifi_tx_interrupt: loop %d prio %d rd %d\\n\", sdr_compatible_str, loop_count, prio, ring->bd_rd_idx);\n\n    } else\n      break;\n  }\n  if ( loop_count!=1 && ((priv->drv_tx_reg_val[DRV_TX_REG_IDX_PRINT_CFG])&DMESG_LOG_ERROR) )\n    printk(\"%s openwifi_tx_interrupt: WARNING loop_count %d\\n\", sdr_compatible_str, loop_count);\n\n  spin_unlock(&priv->lock);\n  return IRQ_HANDLED;\n}\n\nu32 crc_table[16] = {0x4DBDF21C, 0x500AE278, 0x76D3D2D4, 0x6B64C2B0, 0x3B61B38C, 0x26D6A3E8, 0x000F9344, 0x1DB88320, 0xA005713C, 0xBDB26158, 0x9B6B51F4, 0x86DC4190, 0xD6D930AC, 0xCB6E20C8, 0xEDB71064, 0xF0000000};\nu32 gen_mpdu_crc(u8 *data_in, u32 num_bytes)\n{\n  u32 i, crc = 0;\n  u8 idx;\n  for( i = 0; i < num_bytes; i++)\n  {\n    idx = (crc & 0x0F) ^ (data_in[i] & 0x0F);\n    crc = (crc >> 4) ^ crc_table[idx];\n\n    idx = (crc & 0x0F) ^ ((data_in[i] >> 4) & 0x0F);\n    crc = (crc >> 4) ^ crc_table[idx];\n  }\n\n  return crc;\n}\n\nu8 gen_mpdu_delim_crc(u16 m)\n{\n  u8 i, temp, c[8] = {1, 1, 1, 1, 1, 1, 1, 1}, mpdu_delim_crc;\n\n  for (i = 0; i < 16; i++)\n  {\n    temp = c[7] ^ ((m >> i) & 0x01);\n\n    c[7] = c[6];\n    c[6] = c[5];\n    c[5] = c[4];\n    c[4] = c[3];\n    c[3] = c[2];\n    c[2] = c[1] ^ temp;\n    c[1] = c[0] ^ temp;\n    c[0] = temp;\n  }\n  mpdu_delim_crc = ((~c[7] & 0x01) << 0) | ((~c[6] & 0x01) << 1) | ((~c[5] & 0x01) << 2) | ((~c[4] & 0x01) << 3) | ((~c[3] & 0x01) << 4) | ((~c[2] & 0x01) << 5) | ((~c[1] & 0x01) << 6) | ((~c[0] & 0x01) << 7);\n\n  return mpdu_delim_crc;\n}\n\nstatic inline struct gpio_led_data * //please align with the implementation in leds-gpio.c\n      cdev_to_gpio_led_data(struct led_classdev *led_cdev)\n{\n  return container_of(led_cdev, struct gpio_led_data, cdev);\n}\n\ninline int calc_n_ofdm(int num_octet, int n_dbps)\n{\n  int num_bit, num_ofdm_sym;\n  \n  num_bit      = 22+num_octet*8;\n  num_ofdm_sym = (num_bit/n_dbps) + ((num_bit%n_dbps)!=0);\n\n  return (num_ofdm_sym);\n}\n\ninline __le16 gen_ht_duration_id(__le16 frame_control, __le16 aid, u8 qos_hdr, bool use_ht_aggr, u8 rate_hw_value, u16 sifs) \n{\n// COTS wifi ht QoS data duration field analysis (lots of capture):\n\n// ht non-aggr QoS data: 44, type 2 (data frame) sub-type 8 (1000) 21.7/52/57.8/58.5/65Mbps\n// ack     ht 36 + 4*[(22+14*8)/78] = 36 + 4*2 = 44\n// ack legacy 20 + 4*[(22+14*8)/72] = 20 + 4*2 = 28\n\n// ht non-aggr QoS data: 60, type 2 (data frame) sub-type 8 (1000) 6.5Mbps\n// ack     ht 36 + 4*[(22+14*8)/26] = 36 + 4*6 = 60\n// ack legacy 20 + 4*[(22+14*8)/24] = 20 + 4*6 = 44\n\n// ht     aggr QoS data: 52, type 2 (data frame) sub-type 8 (1000) 19.5/28.9/39/57.8/65/72.2Mbps\n// ack     ht 36 + 4*[(22+32*8)/78] = 36 + 4*4 = 52\n// ack legacy 20 + 4*[(22+32*8)/72] = 20 + 4*4 = 36\n\n// ht     aggr QoS data: 60, type 2 (data frame) sub-type 8 (1000) 13/14.4Mbps\n// ack     ht 36 + 4*[(22+32*8)/52] = 36 + 4*6 = 60\n// ack legacy 20 + 4*[(22+32*8)/48] = 20 + 4*6 = 44\n\n// ht and legacy rate mapping is ont one on one, instead it is modulation combined with coding rate\n// modulate  coding  ht-mcs ht-n_dbps legacy-mcs legacy-n_dbps\n// BPSK      1/2     0      26        4          24\n// QPSK      1/2     1      52        6          48\n// QPSK      3/4     2      78        7          72\n// 16QAM     1/2     3      104       8          96\n// 16QAM     3/4     4      156       9          144\n// 64QAM     2/3     5      208       10         192\n// 64QAM     3/4     6      234       11         216\n\n// conclusion: duration is: assume ack/blk-ack uses legacy, plus SIFS\n\n// other observation: ht always use QoS data, not data (sub-type)\n// other observation: management/control frame always in non-ht\n\n  __le16 dur = 0;\n  u16 n_dbps;\n  int num_octet, num_ofdm_sym;\n\n  if (ieee80211_is_pspoll(frame_control)) {\n    dur = (aid|0xc000);\n  } else if (ieee80211_is_data_qos(frame_control) && (~(qos_hdr&IEEE80211_QOS_CTL_ACK_POLICY_NOACK))) {\n    rate_hw_value = (rate_hw_value>6?6:rate_hw_value);\n    n_dbps = (rate_hw_value==0?wifi_n_dbps_table[4]:wifi_n_dbps_table[rate_hw_value+5]);\n    num_octet = (use_ht_aggr?32:14); //32 bytes for compressed block ack; 14 bytes for normal ack\n    num_ofdm_sym = calc_n_ofdm(num_octet, n_dbps);\n    dur = sifs + 20 + 4*num_ofdm_sym; // 20us legacy preamble\n    // printk(\"%s gen_ht_duration_id: num_octet %d n_dbps %d num_ofdm_sym %d dur %d\\n\", sdr_compatible_str, \n    // num_octet, n_dbps, num_ofdm_sym, dur);\n  } else {\n    printk(\"%s openwifi_tx: WARNING gen_ht_duration_id wrong pkt type!\\n\", sdr_compatible_str);\n  }\n\n  return dur;\n}\n\ninline void report_pkt_loss_due_to_driver_drop(struct ieee80211_hw *dev, struct sk_buff *skb)\n{\n  struct openwifi_priv *priv = dev->priv;\n  struct ieee80211_tx_info *info;\n\n  info = IEEE80211_SKB_CB(skb);\n  ieee80211_tx_info_clear_status(info);\n  info->status.rates[0].count = 1;\n  info->status.rates[1].idx = -1;\n  info->status.antenna = priv->runtime_tx_ant_cfg;\n  ieee80211_tx_status_irqsafe(dev, skb);\n}\n\nstatic void openwifi_tx(struct ieee80211_hw *dev,\n           struct ieee80211_tx_control *control,\n           struct sk_buff *skb)\n{\n  struct openwifi_priv *priv = dev->priv;\n  unsigned long flags;\n  struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);\n  struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;\n  struct openwifi_ring *ring = NULL;\n  struct sk_buff *skb_new; // temp skb for internal use\n  struct ieee80211_tx_info *info_skipped;\n  dma_addr_t dma_mapping_addr;\n  unsigned int i, j, empty_bd_idx = 0;\n  u16 rate_signal_value, len_mpdu, len_psdu, num_dma_symbol, len_mpdu_delim_pad=0, num_byte_pad;\n  u32 num_dma_byte, addr1_low32, addr2_low32=0, addr3_low32=0, tx_config, cts_reg=0, phy_hdr_config;//, openofdm_state_history;\n  u16 addr1_high16, addr2_high16=0, addr3_high16=0, sc, seq_no=0, cts_duration=0, sifs, ack_duration=0, traffic_pkt_duration, n_dbps;\n  u8 cts_rate_hw_value=0, cts_rate_signal_value=0, rate_hw_value, pkt_need_ack, retry_limit_raw,use_short_gi,*dma_buf,retry_limit_hw_value,rc_flags,qos_hdr,prio,queue_idx,drv_ring_idx;\n  bool drv_seqno=false, use_rts_cts, use_cts_protect, ht_aggr_start=false, use_ht_rate, use_ht_aggr, cts_use_traffic_rate=false, force_use_cts_protect=false;\n  __le16 frame_control,duration_id;\n  u32 dma_fifo_no_room_flag, hw_queue_len, delay_count=0;\n  u16 aid = 0;\n  enum dma_status status;\n\n  static u32 addr1_low32_prev = -1;\n  static u8 rate_hw_value_prev = -1;\n  static u8 pkt_need_ack_prev = -1;\n  static u16 addr1_high16_prev = -1;\n  static __le16 duration_id_prev = -1;\n  static u8 prio_prev = -1;\n  static u8 retry_limit_raw_prev = -1;\n  static u8 use_short_gi_prev = -1;\n\n  // static bool led_status=0;\n  // struct gpio_led_data *led_dat = cdev_to_gpio_led_data(priv->led[3]);\n\n  // if ( (priv->phy_tx_sn&7) ==0 ) {\n  //   openofdm_state_history = openofdm_rx_api->OPENOFDM_RX_REG_STATE_HISTORY_read();\n  //   if (openofdm_state_history!=openofdm_state_history_old){\n  //     led_status = (~led_status);\n  //     openofdm_state_history_old = openofdm_state_history;\n  //     gpiod_set_value(led_dat->gpiod, led_status);\n  //   }\n  // }\n\n  if (skb->data_len>0) {// more data are not in linear data area skb->data\n    printk(\"%s openwifi_tx: WARNING skb->data_len>0\\n\", sdr_compatible_str);\n    goto openwifi_tx_early_out;\n  }\n\n  len_mpdu = skb->len;\n\n  // get Linux priority/queue setting info and target mac address\n  prio = skb_get_queue_mapping(skb);\n  if (prio >= MAX_NUM_HW_QUEUE) {\n    printk(\"%s openwifi_tx: WARNING prio%d\\n\", sdr_compatible_str, prio);\n    goto openwifi_tx_early_out;\n  }\n\n  addr1_low32  = *((u32*)(hdr->addr1+2));\n\n  // ---- DO your idea here! Map Linux/SW \"prio\" to driver \"drv_ring_idx\" (then 1on1 to FPGA queue_idx) ---\n  if (priv->slice_idx == 0xFFFFFFFF) {// use Linux default prio setting, if there isn't any slice config\n    drv_ring_idx = prio;\n  } else {// customized prio to drv_ring_idx mapping\n    // check current packet belonging to which slice/hw-queue\n    for (i=0; i<MAX_NUM_HW_QUEUE; i++) {\n      if ( priv->dest_mac_addr_queue_map[i] == addr1_low32 ) {\n        break;\n      }\n    }\n    drv_ring_idx = (i>=MAX_NUM_HW_QUEUE?prio:i); // if no address is hit\n  }\n\n  ring = &(priv->tx_ring[drv_ring_idx]);\n\n  spin_lock_irqsave(&priv->lock, flags);\n  if (ring->bds[ring->bd_wr_idx].seq_no != 0xffff) { // not cleared yet by interrupt\n    for (i=1; i<NUM_TX_BD; i++) {\n      if (ring->bds[(ring->bd_wr_idx+i)&(NUM_TX_BD-1)].seq_no == 0xffff) {\n        empty_bd_idx = i;\n        break;\n      }\n    }\n    hw_queue_len = tx_intf_api->TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read();\n    if (empty_bd_idx) { // clear all bds before the empty bd and report failure to Linux\n      if (priv->stat.stat_enable) {\n        priv->stat.tx_prio_stop0_fake_num[prio]++;\n        priv->stat.tx_queue_stop0_fake_num[drv_ring_idx]++;\n      }\n      for (i=0; i<empty_bd_idx; i++) {\n        j = ( (ring->bd_wr_idx+i)&(NUM_TX_BD-1) );\n        printk(\"%s openwifi_tx: WARNING fake stop queue empty_bd_idx%d i%d lnx prio%d map to q%d stop%d hwq len%d wr%d rd%d bd prio%d len_mpdu%d seq_no%d skb_linked%p dma_mapping_addr%u\\n\", sdr_compatible_str,\n        empty_bd_idx, i, prio, drv_ring_idx, ring->stop_flag, hw_queue_len, ring->bd_wr_idx, ring->bd_rd_idx, ring->bds[j].prio, ring->bds[j].len_mpdu, ring->bds[j].seq_no, ring->bds[j].skb_linked,(long long int)(ring->bds[j].dma_mapping_addr));\n        // tell Linux this skb failed\n        skb_new = ring->bds[j].skb_linked;\n        dma_unmap_single(priv->tx_chan->device->dev,ring->bds[j].dma_mapping_addr,\n              skb_new->len, DMA_MEM_TO_DEV);\n        info_skipped = IEEE80211_SKB_CB(skb_new);\n        ieee80211_tx_info_clear_status(info_skipped);\n        info_skipped->status.rates[0].count = 1;\n        info_skipped->status.rates[1].idx = -1;\n        info_skipped->status.antenna = priv->runtime_tx_ant_cfg;\n        ieee80211_tx_status_irqsafe(dev, skb_new);\n\n        ring->bds[j].prio = 0xff; // invalid value\n        ring->bds[j].len_mpdu = 0; // invalid value\n        ring->bds[j].seq_no = 0xffff;\n        ring->bds[j].skb_linked = NULL;\n        ring->bds[j].dma_mapping_addr = 0;\n\n      }\n      if (ring->stop_flag != -1) { //the interrupt seems will never come, we need to wake up the queue in case the interrupt will never wake it up\n        ieee80211_wake_queue(dev, ring->stop_flag);\n        ring->stop_flag = -1;\n      }\n    } else {\n      j = ring->bd_wr_idx;\n      printk(\"%s openwifi_tx: WARNING real stop queue lnx prio%d map to q%d stop%d hwq len%d wr%d rd%d bd prio%d len_mpdu%d seq_no%d skb_linked%p dma_mapping_addr%u\\n\", sdr_compatible_str,\n      prio, drv_ring_idx, ring->stop_flag, hw_queue_len, ring->bd_wr_idx, ring->bd_rd_idx, ring->bds[j].prio, ring->bds[j].len_mpdu, ring->bds[j].seq_no, ring->bds[j].skb_linked, (long long int)(ring->bds[j].dma_mapping_addr));\n\n      ieee80211_stop_queue(dev, prio); // here we should stop those prio related to the queue idx flag set in TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read\n      ring->stop_flag = prio;\n      if (priv->stat.stat_enable) {\n        priv->stat.tx_prio_stop0_real_num[prio]++;\n        priv->stat.tx_queue_stop0_real_num[drv_ring_idx]++;\n      }\n\n      spin_unlock_irqrestore(&priv->lock, flags);\n      goto openwifi_tx_early_out;\n    }\n  }\n  spin_unlock_irqrestore(&priv->lock, flags);\n  // -------------------- end of Map Linux/SW \"prio\" to driver \"drv_ring_idx\" ------------------\n\n  // get other info from packet header\n  addr1_high16 = *((u16*)(hdr->addr1));\n  if (len_mpdu>=20) {\n    addr2_low32  = *((u32*)(hdr->addr2+2));\n    addr2_high16 = *((u16*)(hdr->addr2));\n  }\n  if (len_mpdu>=26) {\n    addr3_low32  = *((u32*)(hdr->addr3+2));\n    addr3_high16 = *((u16*)(hdr->addr3));\n  }\n\n  frame_control=hdr->frame_control;\n  pkt_need_ack = (!(info->flags&IEEE80211_TX_CTL_NO_ACK));\n\n  retry_limit_raw = info->control.rates[0].count;\n\n  rc_flags = info->control.rates[0].flags;\n  use_rts_cts = ((rc_flags&IEEE80211_TX_RC_USE_RTS_CTS)!=0);\n  use_cts_protect = ((rc_flags&IEEE80211_TX_RC_USE_CTS_PROTECT)!=0);\n  use_ht_rate = ((rc_flags&IEEE80211_TX_RC_MCS)!=0);\n  use_short_gi = ((rc_flags&IEEE80211_TX_RC_SHORT_GI)!=0);\n  use_ht_aggr = ((info->flags&IEEE80211_TX_CTL_AMPDU)!=0);\n  qos_hdr = (*(ieee80211_get_qos_ctl(hdr)));\n\n  // get Linux rate (MCS) setting\n  rate_hw_value = ieee80211_get_tx_rate(dev, info)->hw_value;\n  // drv_tx_reg_val[DRV_TX_REG_IDX_RATE]\n  // override rate legacy: 4:6M,   5:9M,  6:12M,  7:18M, 8:24M, 9:36M, 10:48M,   11:54M\n  // drv_tx_reg_val[DRV_TX_REG_IDX_RATE_HT] \n  // override rate     ht: 4:6.5M, 5:13M, 6:19.5M,7:26M, 8:39M, 9:52M, 10:58.5M, 11:65M\n  if ( ieee80211_is_data(hdr->frame_control) ) {//rate override command\n    if (use_ht_rate && priv->drv_tx_reg_val[DRV_TX_REG_IDX_RATE_HT]>0) {\n      rate_hw_value = (priv->drv_tx_reg_val[DRV_TX_REG_IDX_RATE_HT]&0xF)-4;\n      use_short_gi  = ((priv->drv_tx_reg_val[DRV_TX_REG_IDX_RATE_HT]&0x10)==0x10);\n    } else if ((!use_ht_rate) && priv->drv_tx_reg_val[DRV_TX_REG_IDX_RATE]>0)\n      rate_hw_value = (priv->drv_tx_reg_val[DRV_TX_REG_IDX_RATE]&0xF);\n    // TODO: need to map rate_hw_value back to info->control.rates[0].idx!!!\n  }\n\n  // Workaround for a FPGA bug: if aggr happens on ht mcs 0, the tx core will never end, running eneless and stuck the low MAC!\n  if (use_ht_aggr && rate_hw_value==0)\n    rate_hw_value = 1;\n\n  // sifs = (priv->actual_rx_lo<2500?10:16);\n  sifs = 16; // for ofdm, sifs is always 16\n\n  if (control != NULL) { // get aid for gen_ht_duration_id only when control->sta is not NULL\n    if (control->sta != NULL) {\n      aid = control->sta->aid;\n    }\n  }\n\n  if (use_ht_rate) {\n    // printk(\"%s openwifi_tx: rate_hw_value %d aggr %d sifs %d\\n\", sdr_compatible_str, rate_hw_value, use_ht_aggr, sifs);\n    hdr->duration_id = gen_ht_duration_id(frame_control, aid, qos_hdr, use_ht_aggr, rate_hw_value, sifs); //linux only do it for 11a/g, not for 11n and later\n  }\n  duration_id = hdr->duration_id;\n\n  if (use_rts_cts)\n    printk(\"%s openwifi_tx: WARNING sn %d use_rts_cts is not supported!\\n\", sdr_compatible_str, ring->bd_wr_idx);\n\n  if (use_cts_protect) {\n    cts_rate_hw_value = ieee80211_get_rts_cts_rate(dev, info)->hw_value;\n    cts_duration = le16_to_cpu(ieee80211_ctstoself_duration(dev,info->control.vif,len_mpdu,info));\n  } else if (force_use_cts_protect) { // could override mac80211 setting here.\n    cts_rate_hw_value = 4; //wifi_mcs_table_11b_force_up[] translate it to 1011(6M)\n    if (pkt_need_ack)\n      ack_duration = 44;//assume the ack we wait use 6Mbps: 4*ceil((22+14*8)/24) + 20(preamble+SIGNAL)\n    \n    n_dbps = (use_ht_rate?wifi_n_dbps_ht_table[rate_hw_value+4]:wifi_n_dbps_table[rate_hw_value]);\n    traffic_pkt_duration = (use_ht_rate?36:20) + 4*calc_n_ofdm(len_mpdu, n_dbps);\n    cts_duration = traffic_pkt_duration + sifs + pkt_need_ack*(sifs+ack_duration);\n  }\n\n// this is 11b stuff\n//  if (info->flags&IEEE80211_TX_RC_USE_SHORT_PREAMBLE)\n//    printk(\"%s openwifi_tx: WARNING IEEE80211_TX_RC_USE_SHORT_PREAMBLE\\n\", sdr_compatible_str);\n\n  if (len_mpdu>=28) {\n    if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {\n      if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) {\n        priv->seqno += 0x10;\n        drv_seqno = true;\n      }\n      hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);\n      hdr->seq_ctrl |= cpu_to_le16(priv->seqno);\n    }\n    sc = hdr->seq_ctrl;\n    seq_no = (sc&IEEE80211_SCTL_SEQ)>>4;\n  }\n\n    // printk(\"%s openwifi_tx: rate&try: %d %d %03x; %d %d %03x; %d %d %03x; %d %d %03x\\n\", sdr_compatible_str,\n    //   info->status.rates[0].idx,info->status.rates[0].count,info->status.rates[0].flags,\n    //   info->status.rates[1].idx,info->status.rates[1].count,info->status.rates[1].flags,\n    //   info->status.rates[2].idx,info->status.rates[2].count,info->status.rates[2].flags,\n    //   info->status.rates[3].idx,info->status.rates[3].count,info->status.rates[3].flags);\n\n  // -----------end of preprocess some info from header and skb----------------\n\n  // /* HW will perform RTS-CTS when only RTS flags is set.\n  //  * HW will perform CTS-to-self when both RTS and CTS flags are set.\n  //  * RTS rate and RTS duration will be used also for CTS-to-self.\n  //  */\n  // if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {\n  //   tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;\n  //   rts_duration = ieee80211_rts_duration(dev, priv->vif[0], // assume all vif have the same config\n  //           len_mpdu, info);\n  //   printk(\"%s openwifi_tx: rc_flags & IEEE80211_TX_RC_USE_RTS_CTS\\n\", sdr_compatible_str);\n  // } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {\n  //   tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;\n  //   rts_duration = ieee80211_ctstoself_duration(dev, priv->vif[0], // assume all vif have the same config\n  //           len_mpdu, info);\n  //   printk(\"%s openwifi_tx: rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT\\n\", sdr_compatible_str);\n  // }\n\n  if(use_ht_aggr)\n  {\n    if(ieee80211_is_data_qos(frame_control) == false)\n    {\n      printk(\"%s openwifi_tx: WARNING packet is not QoS packet!\\n\", sdr_compatible_str);\n      goto openwifi_tx_early_out;\n    }\n\n    // psdu = [ MPDU DEL | MPDU | CRC | MPDU padding ]\n    len_mpdu_delim_pad = ((len_mpdu + LEN_PHY_CRC)%4 == 0) ? 0 :(4 - (len_mpdu + LEN_PHY_CRC)%4);\n    len_psdu = LEN_MPDU_DELIM + len_mpdu + LEN_PHY_CRC + len_mpdu_delim_pad;\n\n    if( (addr1_low32 != addr1_low32_prev) || (addr1_high16 != addr1_high16_prev) || (duration_id != duration_id_prev) || \n      (rate_hw_value != rate_hw_value_prev) || (use_short_gi != use_short_gi_prev) || \n      (prio != prio_prev) || (retry_limit_raw != retry_limit_raw_prev) || (pkt_need_ack != pkt_need_ack_prev) )\n    {\n      addr1_low32_prev = addr1_low32;\n      addr1_high16_prev = addr1_high16;\n      duration_id_prev = duration_id;\n      rate_hw_value_prev = rate_hw_value;\n      use_short_gi_prev = use_short_gi;\n      prio_prev = prio;\n      retry_limit_raw_prev = retry_limit_raw;\n      pkt_need_ack_prev = pkt_need_ack;\n\n      ht_aggr_start = true;\n    }\n  }\n  else\n  {\n    // psdu = [ MPDU ]\n    len_psdu = len_mpdu;\n    \n    // // Don't need to reset _prev variables every time when it is not ht aggr qos data. Reason:\n    // // 1. In 99.9999% cases, the ht always use qos data and goes to prio/queue_idx 2. By not resetting the variable to -1, we can have continuous aggregation packet operation in FPGA queue 2.\n    // // 2. In other words, the aggregation operation for queue 2 in FPGA won't be interrupted by other non aggregation packets (control/management/beacon/etc.) that go to queue 0 (or other queues than 2).\n    // // 3. From wired domain and upper level ( DSCP, AC (0~3), WMM management, 802.11D service classes and user priority (UP) ) to chip/FPGA queue index, thre should be some (complicated) mapping relationship.\n    // // 4. More decent design is setting these aggregation flags (ht_aggr_start) per queue/prio here in driver. But since now only queue 2 and 0 are used (data goes to queue 2, others go to queue 0) in normal (most) cases, let's not go to the decent (complicated) solution immediately.\n    // addr1_low32_prev = -1;\n    // addr1_high16_prev = -1;\n    // duration_id_prev = -1;\n    // use_short_gi_prev = -1;\n    // rate_hw_value_prev = -1;\n    // prio_prev = -1;\n    // retry_limit_raw_prev = -1;\n    // pkt_need_ack_prev = -1;\n  }\n  num_dma_symbol = (len_psdu>>TX_INTF_NUM_BYTE_PER_DMA_SYMBOL_IN_BITS) + ((len_psdu&(TX_INTF_NUM_BYTE_PER_DMA_SYMBOL-1))!=0);\n\n  if ( ( (!pkt_need_ack)&&(priv->drv_tx_reg_val[DRV_TX_REG_IDX_PRINT_CFG]&DMESG_LOG_BROADCAST) ) || ( (pkt_need_ack)&&(priv->drv_tx_reg_val[DRV_TX_REG_IDX_PRINT_CFG]&DMESG_LOG_UNICAST) ) ) \n    printk(\"%s openwifi_tx: %dB RC%x %dM FC%04x DI%04x ADDR%04x%08x/%04x%08x/%04x%08x flag%08x QoS%02x SC%d_%d retr%d ack%d prio%d q%d wr%d rd%d\\n\", sdr_compatible_str,\n      len_mpdu, rc_flags, (use_ht_rate == false ? wifi_rate_all[rate_hw_value] : wifi_rate_all[rate_hw_value + 12]),frame_control,duration_id, \n      reverse16(addr1_high16), reverse32(addr1_low32), reverse16(addr2_high16), reverse32(addr2_low32), reverse16(addr3_high16), reverse32(addr3_low32),\n      info->flags, qos_hdr, seq_no, drv_seqno, retry_limit_raw, pkt_need_ack, prio, drv_ring_idx,\n      // use_rts_cts,use_cts_protect|force_use_cts_protect,wifi_rate_all[cts_rate_hw_value],cts_duration,\n      ring->bd_wr_idx,ring->bd_rd_idx);\n\n  // check whether the packet is bigger than DMA buffer size\n  num_dma_byte = (num_dma_symbol<<TX_INTF_NUM_BYTE_PER_DMA_SYMBOL_IN_BITS);\n  if (num_dma_byte > TX_BD_BUF_SIZE) {\n    printk(\"%s openwifi_tx: WARNING sn %d num_dma_byte > TX_BD_BUF_SIZE\\n\", sdr_compatible_str, ring->bd_wr_idx);\n    goto openwifi_tx_early_out;\n  }\n\n  // Copy MPDU delimiter and padding into sk_buff\n  if(use_ht_aggr)\n  {\n    // when skb does not have enough headroom, skb_push will cause kernel panic. headroom needs to be extended if necessary\n    if (skb_headroom(skb)<LEN_MPDU_DELIM) {// in case original skb headroom is not enough to host MPDU delimiter\n      printk(\"%s openwifi_tx: WARNING(AGGR) sn %d skb_headroom(skb) %d < LEN_MPDU_DELIM %d\\n\", sdr_compatible_str, ring->bd_wr_idx, skb_headroom(skb), LEN_MPDU_DELIM);\n      if ((skb_new = skb_realloc_headroom(skb, LEN_MPDU_DELIM)) == NULL) {\n        printk(\"%s openwifi_tx: WARNING sn %d skb_realloc_headroom failed!\\n\", sdr_compatible_str, ring->bd_wr_idx);\n        goto openwifi_tx_early_out;\n      }\n      if (skb->sk != NULL)\n        skb_set_owner_w(skb_new, skb->sk);\n      dev_kfree_skb(skb);\n      skb = skb_new;\n    }\n    skb_push( skb, LEN_MPDU_DELIM );\n    dma_buf = skb->data;\n\n    // fill in MPDU delimiter\n    *((u16*)(dma_buf+0)) = ((u16)(len_mpdu+LEN_PHY_CRC) << 4) & 0xFFF0;\n    *((u8 *)(dma_buf+2)) = gen_mpdu_delim_crc(*((u16 *)dma_buf));\n    *((u8 *)(dma_buf+3)) = 0x4e;\n\n    // Extend sk_buff to hold CRC + MPDU padding + empty MPDU delimiter\n    num_byte_pad = num_dma_byte - (LEN_MPDU_DELIM + len_mpdu);\n    if (skb_tailroom(skb)<num_byte_pad) {// in case original skb tailroom is not enough to host num_byte_pad\n      printk(\"%s openwifi_tx: WARNING(AGGR) sn %d skb_tailroom(skb) %d < num_byte_pad %d!\\n\", sdr_compatible_str, ring->bd_wr_idx, skb_tailroom(skb), num_byte_pad);\n      if ((skb_new = skb_copy_expand(skb, skb_headroom(skb), num_byte_pad, GFP_KERNEL)) == NULL) {\n        printk(\"%s openwifi_tx: WARNING(AGGR) sn %d skb_copy_expand failed!\\n\", sdr_compatible_str, ring->bd_wr_idx);\n        goto openwifi_tx_early_out;\n      }\n      if (skb->sk != NULL)\n        skb_set_owner_w(skb_new, skb->sk);\n      dev_kfree_skb(skb);\n      skb = skb_new;\n    }\n    skb_put( skb, num_byte_pad );\n\n    // fill in MPDU CRC\n    *((u32*)(dma_buf+LEN_MPDU_DELIM+len_mpdu)) = gen_mpdu_crc(dma_buf+LEN_MPDU_DELIM, len_mpdu);\n\n    // fill in MPDU delimiter padding\n    memset(dma_buf+LEN_MPDU_DELIM+len_mpdu+LEN_PHY_CRC, 0, len_mpdu_delim_pad);\n\n    // num_dma_byte is on 8-byte boundary and len_psdu is on 4 byte boundary.\n    // If they have different lengths, add \"empty MPDU delimiter\" for alignment\n    if(num_dma_byte == len_psdu + 4)\n    {\n      *((u32*)(dma_buf+len_psdu)) = 0x4e140000;\n      len_psdu = num_dma_byte;\n    }\n  }\n  else\n  {\n    // Extend sk_buff to hold padding\n    num_byte_pad = num_dma_byte - len_mpdu;\n    if (skb_tailroom(skb)<num_byte_pad) {// in case original skb tailroom is not enough to host num_byte_pad\n      printk(\"%s openwifi_tx: WARNING sn %d skb_tailroom(skb) %d < num_byte_pad %d!\\n\", sdr_compatible_str, ring->bd_wr_idx, skb_tailroom(skb), num_byte_pad);\n      if ((skb_new = skb_copy_expand(skb, skb_headroom(skb), num_byte_pad, GFP_KERNEL)) == NULL) {\n        printk(\"%s openwifi_tx: WARNING sn %d skb_copy_expand failed!\\n\", sdr_compatible_str, ring->bd_wr_idx);\n        goto openwifi_tx_early_out;\n      }\n      if (skb->sk != NULL)\n        skb_set_owner_w(skb_new, skb->sk);\n      dev_kfree_skb(skb);\n      skb = skb_new;\n    }\n    skb_put( skb, num_byte_pad );\n\n    dma_buf = skb->data;\n  }\n//  for(i = 0; i <= num_dma_symbol; i++)\n//    printk(\"%16llx\\n\", (*(u64*)(&(dma_buf[i*8]))));\n\n  retry_limit_hw_value = ( retry_limit_raw==0?0:((retry_limit_raw - 1)&0xF) );\n\n  queue_idx = drv_ring_idx; // from driver ring idx to FPGA queue_idx mapping\n\n  if (use_cts_protect || force_use_cts_protect) {\n    rate_signal_value = (use_ht_rate ? rate_hw_value : wifi_mcs_table_11b_force_up[rate_hw_value]);\n    cts_rate_signal_value = wifi_mcs_table_11b_force_up[cts_rate_hw_value];\n    cts_reg = ((use_cts_protect|force_use_cts_protect)<<31 | cts_use_traffic_rate<<30 | cts_duration<<8 | cts_rate_signal_value<<4 | rate_signal_value);\n  }\n  phy_hdr_config = ( ht_aggr_start<<20 | rate_hw_value<<16 | use_ht_rate<<15 | use_short_gi<<14 | use_ht_aggr<<13 | len_psdu );\n  tx_config = ( prio<<26 | ring->bd_wr_idx<<20 | queue_idx<<18 | retry_limit_hw_value<<14 | pkt_need_ack<<13 | num_dma_symbol );\n\n  /* We must be sure that tx_flags is written last because the HW\n   * looks at it to check if the rest of data is valid or not\n   */\n  //wmb();\n  // entry->flags = cpu_to_le32(tx_flags);\n  /* We must be sure this has been written before following HW\n   * register write, because this write will make the HW attempts\n   * to DMA the just-written data\n   */\n  //wmb();\n\n  spin_lock_irqsave(&priv->lock, flags); // from now on, we'd better avoid interrupt because ring->stop_flag is shared with interrupt\n\n  // -------------check whether FPGA dma fifo and queue (queue_idx) has enough room-------------\n  dma_fifo_no_room_flag = tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read();\n  hw_queue_len = tx_intf_api->TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read();\n  if ( ((dma_fifo_no_room_flag>>queue_idx)&1) || ((NUM_TX_BD-((hw_queue_len>>(queue_idx*8))&0xFF))<=RING_ROOM_THRESHOLD)  || ring->stop_flag>=0 ) {\n    if( priv->drv_tx_reg_val[DRV_TX_REG_IDX_PRINT_CFG]&DMESG_LOG_NORMAL_QUEUE_STOP )\n      printk(\"%s openwifi_tx: WARNING ieee80211_stop_queue prio%d queue%d no room flag%x hwq len%08x request%d wr%d rd%d\\n\", sdr_compatible_str,\n              prio, queue_idx, dma_fifo_no_room_flag, hw_queue_len, num_dma_symbol, ring->bd_wr_idx, ring->bd_rd_idx);\n\n    ieee80211_stop_queue(dev, prio); // here we should stop those prio related to the queue idx flag set in TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read\n    ring->stop_flag = prio;\n    if (priv->stat.stat_enable) {\n      priv->stat.tx_prio_stop1_num[prio]++;\n      priv->stat.tx_queue_stop1_num[queue_idx]++;\n    }\n    // goto openwifi_tx_early_out_after_lock;\n  }\n  // --------end of check whether FPGA fifo (queue_idx) has enough room------------\n\n  status = dma_async_is_tx_complete(priv->tx_chan, priv->tx_cookie, NULL, NULL);\n  while(delay_count<100 && status!=DMA_COMPLETE) {\n    status = dma_async_is_tx_complete(priv->tx_chan, priv->tx_cookie, NULL, NULL);\n    delay_count++;\n    udelay(4);\n    // udelay(priv->stat.dbg_ch1);\n  }\n  if (status!=DMA_COMPLETE) {\n    printk(\"%s openwifi_tx: WARNING status!=DMA_COMPLETE\\n\", sdr_compatible_str);\n    goto openwifi_tx_early_out_after_lock;\n  }\n\n//-------------------------fire skb DMA to hardware----------------------------------\n  dma_mapping_addr = dma_map_single(priv->tx_chan->device->dev, dma_buf,\n         num_dma_byte, DMA_MEM_TO_DEV);\n\n  if (dma_mapping_error(priv->tx_chan->device->dev,dma_mapping_addr)) {\n    // dev_err(priv->tx_chan->device->dev, \"sdr,sdr openwifi_tx: WARNING TX DMA mapping error\\n\");\n    printk(\"%s openwifi_tx: WARNING sn %d TX DMA mapping error\\n\", sdr_compatible_str, ring->bd_wr_idx);\n    goto openwifi_tx_early_out_after_lock;\n  }\n\n  sg_init_table(&(priv->tx_sg), 1); // only need to be initialized once in openwifi_start\n  sg_dma_address( &(priv->tx_sg) ) = dma_mapping_addr;\n  sg_dma_len( &(priv->tx_sg) ) = num_dma_byte;\n  \n  tx_intf_api->TX_INTF_REG_CTS_TOSELF_CONFIG_write(cts_reg);\n  tx_intf_api->TX_INTF_REG_TX_CONFIG_write(tx_config);\n  tx_intf_api->TX_INTF_REG_PHY_HDR_CONFIG_write(phy_hdr_config);\n  priv->txd = priv->tx_chan->device->device_prep_slave_sg(priv->tx_chan, &(priv->tx_sg),1,DMA_MEM_TO_DEV, DMA_CTRL_ACK | DMA_PREP_INTERRUPT, NULL);\n  if (!(priv->txd)) {\n    printk(\"%s openwifi_tx: WARNING sn %d device_prep_slave_sg %p\\n\", sdr_compatible_str, ring->bd_wr_idx, (void*)(priv->txd));\n    goto openwifi_tx_after_dma_mapping;\n  }\n\n  priv->tx_cookie = priv->txd->tx_submit(priv->txd);\n\n  if (dma_submit_error(priv->tx_cookie)) {\n    printk(\"%s openwifi_tx: WARNING sn %d dma_submit_error(tx_cookie) %d\\n\", sdr_compatible_str, ring->bd_wr_idx, (u32)(priv->tx_cookie));\n    goto openwifi_tx_after_dma_mapping;\n  }\n\n  // seems everything is ok. let's mark this pkt in bd descriptor ring\n  ring->bds[ring->bd_wr_idx].prio = prio;\n  ring->bds[ring->bd_wr_idx].len_mpdu = len_mpdu;\n  ring->bds[ring->bd_wr_idx].seq_no = seq_no;\n  ring->bds[ring->bd_wr_idx].skb_linked = skb;\n  ring->bds[ring->bd_wr_idx].dma_mapping_addr = dma_mapping_addr;\n\n  ring->bd_wr_idx = ((ring->bd_wr_idx+1)&(NUM_TX_BD-1));\n\n  dma_async_issue_pending(priv->tx_chan);\n\n  spin_unlock_irqrestore(&priv->lock, flags);\n\n  if (priv->stat.stat_enable) {\n    priv->stat.tx_prio_num[prio]++;\n    priv->stat.tx_queue_num[queue_idx]++;\n  }\n\n  return;\n\nopenwifi_tx_after_dma_mapping:\n  dma_unmap_single(priv->tx_chan->device->dev, dma_mapping_addr, num_dma_byte, DMA_MEM_TO_DEV);\n\nopenwifi_tx_early_out_after_lock:\n  spin_unlock_irqrestore(&priv->lock, flags);\n  report_pkt_loss_due_to_driver_drop(dev, skb);\n  // dev_kfree_skb(skb);\n  // printk(\"%s openwifi_tx: WARNING openwifi_tx_after_dma_mapping phy_tx_sn %d queue %d\\n\", sdr_compatible_str,priv->phy_tx_sn,queue_idx);\n  return;\n\nopenwifi_tx_early_out:\n  report_pkt_loss_due_to_driver_drop(dev, skb);\n  // dev_kfree_skb(skb);\n  // printk(\"%s openwifi_tx: WARNING openwifi_tx_early_out phy_tx_sn %d queue %d\\n\", sdr_compatible_str,priv->phy_tx_sn,queue_idx);\n}\n\nstatic int openwifi_set_antenna(struct ieee80211_hw *dev, u32 tx_ant, u32 rx_ant)\n{\n  struct openwifi_priv *priv = dev->priv;\n  u8 fpga_tx_ant_setting, target_rx_ant;\n  u32 atten_mdb_tx0, atten_mdb_tx1;\n  struct ctrl_outs_control ctrl_out;\n  int ret;\n  \n  printk(\"%s openwifi_set_antenna: tx_ant%d rx_ant%d\\n\",sdr_compatible_str,tx_ant,rx_ant);\n\n  if (tx_ant >= 4 || tx_ant == 0) {\n    return -EINVAL;\n  } else if (rx_ant >= 3 || rx_ant == 0) {\n    return -EINVAL;\n  }\n\n  fpga_tx_ant_setting = ((tx_ant<=2)?(tx_ant):(tx_ant+16));\n  target_rx_ant = ((rx_ant&1)?0:1);\n\n  // try rf chip setting firstly, only update internal state variable when rf chip succeed\n  atten_mdb_tx0 = ((tx_ant&1)?(AD9361_RADIO_ON_TX_ATT+priv->rf_reg_val[RF_TX_REG_IDX_ATT]):AD9361_RADIO_OFF_TX_ATT);\n  atten_mdb_tx1 = ((tx_ant&2)?(AD9361_RADIO_ON_TX_ATT+priv->rf_reg_val[RF_TX_REG_IDX_ATT]):AD9361_RADIO_OFF_TX_ATT);\n  ret = ad9361_set_tx_atten(priv->ad9361_phy, atten_mdb_tx0, true, false, true);\n  if (ret < 0) {\n    printk(\"%s openwifi_set_antenna: WARNING ad9361_set_tx_atten ant0 %d FAIL!\\n\",sdr_compatible_str, atten_mdb_tx0);\n    return -EINVAL;\n  } else {\n    printk(\"%s openwifi_set_antenna: ad9361_set_tx_atten ant0 %d OK\\n\",sdr_compatible_str, atten_mdb_tx0);\n  }\n  ret = ad9361_set_tx_atten(priv->ad9361_phy, atten_mdb_tx1, false, true, true);\n  if (ret < 0) {\n    printk(\"%s openwifi_set_antenna: WARNING ad9361_set_tx_atten ant1 %d FAIL!\\n\",sdr_compatible_str, atten_mdb_tx1);\n    return -EINVAL;\n  } else {\n    printk(\"%s openwifi_set_antenna: ad9361_set_tx_atten ant1 %d OK\\n\",sdr_compatible_str, atten_mdb_tx1);\n  }\n\n  ctrl_out.en_mask = priv->ctrl_out.en_mask;\n  ctrl_out.index = (target_rx_ant==0?AD9361_CTRL_OUT_INDEX_ANT0:AD9361_CTRL_OUT_INDEX_ANT1);\n  ret = ad9361_ctrl_outs_setup(priv->ad9361_phy, &(ctrl_out));\n  if (ret < 0) {\n    printk(\"%s openwifi_set_antenna: WARNING ad9361_ctrl_outs_setup en_mask 0x%02x index 0x%02x FAIL!\\n\",sdr_compatible_str, ctrl_out.en_mask, ctrl_out.index);\n    return -EINVAL;\n  } else {\n    printk(\"%s openwifi_set_antenna: ad9361_ctrl_outs_setup en_mask 0x%02x index 0x%02x\\n\",sdr_compatible_str, ctrl_out.en_mask, ctrl_out.index);\n  }\n\n  tx_intf_api->TX_INTF_REG_ANT_SEL_write(fpga_tx_ant_setting);\n  ret = tx_intf_api->TX_INTF_REG_ANT_SEL_read();\n  if (ret != fpga_tx_ant_setting) {\n    printk(\"%s openwifi_set_antenna: WARNING TX_INTF_REG_ANT_SEL_write target %d read back %d\\n\",sdr_compatible_str, fpga_tx_ant_setting, ret);\n    return -EINVAL;\n  } else {\n    printk(\"%s openwifi_set_antenna: TX_INTF_REG_ANT_SEL_write value %d\\n\",sdr_compatible_str, ret);\n  }\n\n  rx_intf_api->RX_INTF_REG_ANT_SEL_write(target_rx_ant);\n  ret = rx_intf_api->RX_INTF_REG_ANT_SEL_read();\n  if (ret != target_rx_ant) {\n    printk(\"%s openwifi_set_antenna: WARNING RX_INTF_REG_ANT_SEL_write target %d read back %d\\n\",sdr_compatible_str, target_rx_ant, ret);\n    return -EINVAL;\n  } else {\n    printk(\"%s openwifi_set_antenna: RX_INTF_REG_ANT_SEL_write value %d\\n\",sdr_compatible_str, ret);\n  }\n\n  // update internal state variable\n  priv->runtime_tx_ant_cfg = tx_ant;\n  priv->runtime_rx_ant_cfg = rx_ant;\n\n  if (TX_OFFSET_TUNING_ENABLE)\n    priv->tx_intf_cfg = ((tx_ant&1)?TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0:TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1);//NO USE\n  else {\n    if (tx_ant == 3)\n      priv->tx_intf_cfg = TX_INTF_BW_20MHZ_AT_0MHZ_ANT_BOTH;\n    else\n      priv->tx_intf_cfg = ((tx_ant&1)?TX_INTF_BW_20MHZ_AT_0MHZ_ANT0:TX_INTF_BW_20MHZ_AT_0MHZ_ANT1);\n  }\n\n  priv->rx_intf_cfg = (target_rx_ant==0?RX_INTF_BW_20MHZ_AT_0MHZ_ANT0:RX_INTF_BW_20MHZ_AT_0MHZ_ANT1);\n  priv->ctrl_out.index=ctrl_out.index;\n\n  priv->tx_freq_offset_to_lo_MHz = tx_intf_fo_mapping[priv->tx_intf_cfg];\n  priv->rx_freq_offset_to_lo_MHz = rx_intf_fo_mapping[priv->rx_intf_cfg];\n\n  return 0;\n}\nstatic int openwifi_get_antenna(struct ieee80211_hw *dev, u32 *tx_ant, u32 *rx_ant)\n{\n  struct openwifi_priv *priv = dev->priv;\n\n  *tx_ant = priv->runtime_tx_ant_cfg;\n  *rx_ant = priv->runtime_rx_ant_cfg;\n\n  printk(\"%s openwifi_get_antenna: tx_ant%d rx_ant%d\\n\",sdr_compatible_str, *tx_ant, *rx_ant);\n\n  printk(\"%s openwifi_get_antenna: drv tx cfg %d offset %d drv rx cfg %d offset %d drv ctrl_out sel %x\\n\",sdr_compatible_str,\n  priv->tx_intf_cfg, priv->tx_freq_offset_to_lo_MHz, priv->rx_intf_cfg, priv->rx_freq_offset_to_lo_MHz, priv->ctrl_out.index);\n  \n  printk(\"%s openwifi_get_antenna: fpga tx sel %d rx sel %d\\n\", sdr_compatible_str, \n  tx_intf_api->TX_INTF_REG_ANT_SEL_read(), rx_intf_api->RX_INTF_REG_ANT_SEL_read());\n  \n  printk(\"%s openwifi_get_antenna: rf tx att0 %d tx att1 %d ctrl_out sel %x\\n\", sdr_compatible_str, \n  ad9361_get_tx_atten(priv->ad9361_phy, 1), ad9361_get_tx_atten(priv->ad9361_phy, 2), ad9361_spi_read(priv->ad9361_phy->spi, REG_CTRL_OUTPUT_POINTER));\n\n  return 0;\n}\n\nstatic int openwifi_start(struct ieee80211_hw *dev)\n{\n  struct openwifi_priv *priv = dev->priv;\n  int ret, i;\n  u32 reg;\n\n  for (i=0; i<MAX_NUM_VIF; i++) {\n    priv->vif[i] = NULL;\n  }\n\n  // //keep software registers persistent between NIC down and up for multiple times\n  /*memset(priv->drv_tx_reg_val, 0, sizeof(priv->drv_tx_reg_val));\n  memset(priv->drv_rx_reg_val, 0, sizeof(priv->drv_rx_reg_val));\n  memset(priv->drv_xpu_reg_val, 0, sizeof(priv->drv_xpu_reg_val));\n  memset(priv->rf_reg_val,0,sizeof(priv->rf_reg_val));\n  priv->drv_xpu_reg_val[DRV_XPU_REG_IDX_GIT_REV] = GIT_REV;*/\n\n  //turn on radio\n  openwifi_set_antenna(dev, priv->runtime_tx_ant_cfg, priv->runtime_rx_ant_cfg);\n  reg = ad9361_get_tx_atten(priv->ad9361_phy, ((priv->runtime_tx_ant_cfg==1 || priv->runtime_tx_ant_cfg==3)?1:2));\n  if (reg == (AD9361_RADIO_ON_TX_ATT+priv->rf_reg_val[RF_TX_REG_IDX_ATT])) {\n    priv->rfkill_off = 1;// 0 off, 1 on\n    printk(\"%s openwifi_start: rfkill radio on\\n\",sdr_compatible_str);\n  }\n  else\n    printk(\"%s openwifi_start: WARNING rfkill radio on failed. tx att read %d require %d\\n\",sdr_compatible_str, reg, AD9361_RADIO_ON_TX_ATT+priv->rf_reg_val[RF_TX_REG_IDX_ATT]);\n\n  rx_intf_api->hw_init(priv->rx_intf_cfg,8,8);\n  tx_intf_api->hw_init(priv->tx_intf_cfg,8,8,priv->fpga_type);\n  openofdm_tx_api->hw_init(priv->openofdm_tx_cfg);\n  openofdm_rx_api->hw_init(priv->openofdm_rx_cfg);\n  xpu_api->hw_init(priv->xpu_cfg);\n\n  xpu_api->XPU_REG_MAC_ADDR_write(priv->mac_addr);\n\n  printk(\"%s openwifi_start: rx_intf_cfg %d openofdm_rx_cfg %d tx_intf_cfg %d openofdm_tx_cfg %d\\n\",sdr_compatible_str, priv->rx_intf_cfg, priv->openofdm_rx_cfg, priv->tx_intf_cfg, priv->openofdm_tx_cfg);\n  printk(\"%s openwifi_start: rx_freq_offset_to_lo_MHz %d tx_freq_offset_to_lo_MHz %d\\n\",sdr_compatible_str, priv->rx_freq_offset_to_lo_MHz, priv->tx_freq_offset_to_lo_MHz);\n\n  tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write(0x30004); //disable tx interrupt\n  rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_write(0x100); // disable rx interrupt by interrupt test mode\n  rx_intf_api->RX_INTF_REG_M_AXIS_RST_write(1); // hold M AXIS in reset status\n\n  // priv->rx_chan = dma_request_slave_channel(&(priv->pdev->dev), \"rx_dma_s2mm\");\n  priv->rx_chan = dma_request_chan(&(priv->pdev->dev), \"rx_dma_s2mm\");\n  if (IS_ERR(priv->rx_chan) || priv->rx_chan==NULL) {\n    ret = PTR_ERR(priv->rx_chan);\n    if (ret != -EPROBE_DEFER) {\n      pr_err(\"%s openwifi_start: No Rx channel ret %d priv->rx_chan 0x%p\\n\",sdr_compatible_str, ret, priv->rx_chan);\n      goto err_dma;\n    }\n  }\n\n  // priv->tx_chan = dma_request_slave_channel(&(priv->pdev->dev), \"tx_dma_mm2s\");\n  priv->tx_chan = dma_request_chan(&(priv->pdev->dev), \"tx_dma_mm2s\");\n  if (IS_ERR(priv->tx_chan) || priv->tx_chan==NULL) {\n    ret = PTR_ERR(priv->tx_chan);\n    if (ret != -EPROBE_DEFER) {\n      pr_err(\"%s openwifi_start: No Tx channel ret %d priv->tx_chan 0x%p\\n\",sdr_compatible_str, ret, priv->tx_chan);\n      goto err_dma;\n    }\n  }\n  printk(\"%s openwifi_start: DMA channel setup successfully. priv->rx_chan 0x%p priv->tx_chan 0x%p\\n\",sdr_compatible_str, priv->rx_chan, priv->tx_chan);\n\n  ret = openwifi_init_rx_ring(priv);\n  if (ret) {\n    printk(\"%s openwifi_start: openwifi_init_rx_ring ret %d\\n\", sdr_compatible_str,ret);\n    goto err_free_rings;\n  }\n\n  priv->seqno=0;\n  for (i=0; i<MAX_NUM_SW_QUEUE; i++) {\n    if ((ret = openwifi_init_tx_ring(priv, i))) {\n      printk(\"%s openwifi_start: openwifi_init_tx_ring %d ret %d\\n\", sdr_compatible_str, i, ret);\n      goto err_free_rings;\n    }\n  }\n\n  if ( (ret = rx_dma_setup(dev)) ) {\n    printk(\"%s openwifi_start: rx_dma_setup ret %d\\n\", sdr_compatible_str,ret);\n    goto err_free_rings;\n  }\n\n  priv->irq_rx = irq_of_parse_and_map(priv->pdev->dev.of_node, 1);\n  ret = request_irq(priv->irq_rx, openwifi_rx_interrupt,\n      IRQF_SHARED, \"sdr,rx_pkt_intr\", dev);\n  if (ret) {\n    wiphy_err(dev->wiphy, \"openwifi_start:failed to register IRQ handler openwifi_rx_interrupt\\n\");\n    goto err_free_rings;\n  } else {\n    printk(\"%s openwifi_start: irq_rx %d\\n\", sdr_compatible_str, priv->irq_rx);\n  }\n\n  priv->irq_tx = irq_of_parse_and_map(priv->pdev->dev.of_node, 3);\n  ret = request_irq(priv->irq_tx, openwifi_tx_interrupt,\n      IRQF_SHARED, \"sdr,tx_itrpt\", dev);\n  if (ret) {\n    wiphy_err(dev->wiphy, \"openwifi_start: failed to register IRQ handler openwifi_tx_interrupt\\n\");\n    goto err_free_rings;\n  } else {\n    printk(\"%s openwifi_start: irq_tx %d\\n\", sdr_compatible_str, priv->irq_tx);\n  }\n\n  rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_write(0x000); // enable rx interrupt get normal fcs valid pass through ddc to ARM\n  tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write(0x4); //enable tx interrupt\n  rx_intf_api->RX_INTF_REG_M_AXIS_RST_write(0); // release M AXIS\n  xpu_api->XPU_REG_TSF_LOAD_VAL_write(0,0); // reset tsf timer\n\n  priv->stat.csma_cfg0 = xpu_api->XPU_REG_FORCE_IDLE_MISC_read();\n\n  // disable ad9361 auto calibration and enable openwifi fpga spi control\n  priv->ad9361_phy->state->auto_cal_en = false;   // turn off auto Tx quadrature calib.\n  priv->ad9361_phy->state->manual_tx_quad_cal_en = true;  // turn on manual Tx quadrature calib.\n  xpu_api->XPU_REG_SPI_DISABLE_write(0);\n\n// normal_out:\n  printk(\"%s openwifi_start: normal end\\n\", sdr_compatible_str);\n  return 0;\n\nerr_free_rings:\n  openwifi_free_rx_ring(priv);\n  for (i=0; i<MAX_NUM_SW_QUEUE; i++)\n    openwifi_free_tx_ring(priv, i);\n\nerr_dma:\n  ret = -1;\n  printk(\"%s openwifi_start: abnormal end ret %d\\n\", sdr_compatible_str, ret);\n  return ret;\n}\n\nstatic void openwifi_stop(struct ieee80211_hw *dev)\n{\n  struct openwifi_priv *priv = dev->priv;\n  u32 reg, reg1;\n  int i;\n\n  // enable ad9361 auto calibration and disable openwifi fpga spi control\n  priv->ad9361_phy->state->auto_cal_en = true;   // turn on auto Tx quadrature calib.\n  priv->ad9361_phy->state->manual_tx_quad_cal_en = false;  // turn off manual Tx quadrature calib.\n  xpu_api->XPU_REG_SPI_DISABLE_write(1);\n\n  //turn off radio\n  #if 1\n  ad9361_tx_mute(priv->ad9361_phy, 1);\n  reg = ad9361_get_tx_atten(priv->ad9361_phy, 2);\n  reg1 = ad9361_get_tx_atten(priv->ad9361_phy, 1);\n  if (reg == AD9361_RADIO_OFF_TX_ATT && reg1 == AD9361_RADIO_OFF_TX_ATT ) {\n    priv->rfkill_off = 0;// 0 off, 1 on\n    printk(\"%s openwifi_stop: rfkill radio off\\n\",sdr_compatible_str);\n  }\n  else\n    printk(\"%s openwifi_stop: WARNING rfkill radio off failed. tx att read %d %d require %d\\n\",sdr_compatible_str, reg, reg1, AD9361_RADIO_OFF_TX_ATT);\n  #endif\n\n  //ieee80211_stop_queue(dev, 0);\n  tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write(0x30004); //disable tx interrupt\n  rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_write(0x100); // disable fcs_valid by interrupt test mode\n  rx_intf_api->RX_INTF_REG_M_AXIS_RST_write(1); // hold M AXIS in reset status\n\n  for (i=0; i<MAX_NUM_VIF; i++) {\n    priv->vif[i] = NULL;\n  }\n\n  openwifi_free_rx_ring(priv);\n  for (i=0; i<MAX_NUM_SW_QUEUE; i++)\n    openwifi_free_tx_ring(priv, i);\n\n  pr_info(\"%s openwifi_stop: dropped channel %s\\n\", sdr_compatible_str, dma_chan_name(priv->rx_chan));\n  dmaengine_terminate_all(priv->rx_chan);\n  dma_release_channel(priv->rx_chan);\n  pr_info(\"%s openwifi_stop: dropped channel %s\\n\", sdr_compatible_str, dma_chan_name(priv->tx_chan));\n  dmaengine_terminate_all(priv->tx_chan);\n  dma_release_channel(priv->tx_chan);\n\n  //priv->rf->stop(dev);\n\n  free_irq(priv->irq_rx, dev);\n  free_irq(priv->irq_tx, dev);\n\n// normal_out:\n  printk(\"%s openwifi_stop\\n\", sdr_compatible_str);\n}\n\nstatic u64 openwifi_get_tsf(struct ieee80211_hw *dev,\n         struct ieee80211_vif *vif)\n{\n  u32 tsft_low, tsft_high;\n\n  tsft_low = xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read();\n  tsft_high = xpu_api->XPU_REG_TSF_RUNTIME_VAL_HIGH_read();\n  //printk(\"%s openwifi_get_tsf: %08x%08x\\n\", sdr_compatible_str,tsft_high,tsft_low);\n  return( ( (u64)tsft_low ) | ( ((u64)tsft_high)<<32 ) );\n}\n\nstatic void openwifi_set_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u64 tsf)\n{\n  u32 tsft_high = ((tsf >> 32)&0xffffffff);\n  u32 tsft_low  = (tsf&0xffffffff);\n  xpu_api->XPU_REG_TSF_LOAD_VAL_write(tsft_high,tsft_low);\n  printk(\"%s openwifi_set_tsf: %08x%08x\\n\", sdr_compatible_str,tsft_high,tsft_low);\n}\n\nstatic void openwifi_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)\n{\n  xpu_api->XPU_REG_TSF_LOAD_VAL_write(0,0);\n  printk(\"%s openwifi_reset_tsf\\n\", sdr_compatible_str);\n}\n\nstatic int openwifi_set_rts_threshold(struct ieee80211_hw *hw, u32 value)\n{\n  printk(\"%s openwifi_set_rts_threshold WARNING value %d\\n\", sdr_compatible_str,value);\n  return(0);\n}\n\nstatic void openwifi_beacon_work(struct work_struct *work)\n{\n  struct openwifi_vif *vif_priv =\n    container_of(work, struct openwifi_vif, beacon_work.work);\n  struct ieee80211_vif *vif =\n    container_of((void *)vif_priv, struct ieee80211_vif, drv_priv);\n  struct ieee80211_hw *dev = vif_priv->dev;\n  struct ieee80211_mgmt *mgmt;\n  struct sk_buff *skb;\n\n  /* don't overflow the tx ring */\n  if (ieee80211_queue_stopped(dev, 0))\n    goto resched;\n\n  /* grab a fresh beacon */\n  skb = ieee80211_beacon_get(dev, vif);\n  if (!skb)\n    goto resched;\n\n  /*\n   * update beacon timestamp w/ TSF value\n   * TODO: make hardware update beacon timestamp\n   */\n  mgmt = (struct ieee80211_mgmt *)skb->data;\n  mgmt->u.beacon.timestamp = cpu_to_le64(openwifi_get_tsf(dev, vif));\n\n  /* TODO: use actual beacon queue */\n  skb_set_queue_mapping(skb, 0);\n  openwifi_tx(dev, NULL, skb);\n\nresched:\n  /*\n   * schedule next beacon\n   * TODO: use hardware support for beacon timing\n   */\n  schedule_delayed_work(&vif_priv->beacon_work, usecs_to_jiffies(1024 * vif->bss_conf.beacon_int));\n  // printk(\"%s openwifi_beacon_work beacon_int %d\\n\", sdr_compatible_str, vif->bss_conf.beacon_int);\n}\n\nstatic int openwifi_add_interface(struct ieee80211_hw *dev,\n         struct ieee80211_vif *vif)\n{\n  int i;\n  struct openwifi_priv *priv = dev->priv;\n  struct openwifi_vif *vif_priv;\n\n  switch (vif->type) {\n  case NL80211_IFTYPE_AP:\n  case NL80211_IFTYPE_STATION:\n  case NL80211_IFTYPE_ADHOC:\n  case NL80211_IFTYPE_MONITOR:\n  case NL80211_IFTYPE_MESH_POINT:\n    break;\n  default:\n    return -EOPNOTSUPP;\n  }\n  // let's support more than 1 interface\n  for (i=0; i<MAX_NUM_VIF; i++) {\n    if (priv->vif[i] == NULL)\n      break;\n  }\n\n  printk(\"%s openwifi_add_interface start. vif for loop result %d\\n\", sdr_compatible_str, i);\n\n  if (i==MAX_NUM_VIF)\n    return -EBUSY;\n\n  priv->vif[i] = vif;\n  \n  /* Initialize driver private area */\n  vif_priv = (struct openwifi_vif *)&vif->drv_priv;\n  vif_priv->idx = i;\n\n  vif_priv->dev = dev;\n  INIT_DELAYED_WORK(&vif_priv->beacon_work, openwifi_beacon_work);\n  vif_priv->enable_beacon = false;\n\n  priv->mac_addr[0] = vif->addr[0];\n  priv->mac_addr[1] = vif->addr[1];\n  priv->mac_addr[2] = vif->addr[2];\n  priv->mac_addr[3] = vif->addr[3];\n  priv->mac_addr[4] = vif->addr[4];\n  priv->mac_addr[5] = vif->addr[5];\n  xpu_api->XPU_REG_MAC_ADDR_write(priv->mac_addr); // set mac addr in fpga\n\n  printk(\"%s openwifi_add_interface end with vif idx %d addr %02x:%02x:%02x:%02x:%02x:%02x\\n\", sdr_compatible_str,vif_priv->idx,\n  vif->addr[0],vif->addr[1],vif->addr[2],vif->addr[3],vif->addr[4],vif->addr[5]);\n\n  return 0;\n}\n\nstatic void openwifi_remove_interface(struct ieee80211_hw *dev,\n             struct ieee80211_vif *vif)\n{\n  struct openwifi_vif *vif_priv;\n  struct openwifi_priv *priv = dev->priv;\n  \n  vif_priv = (struct openwifi_vif *)&vif->drv_priv;\n  priv->vif[vif_priv->idx] = NULL;\n  printk(\"%s openwifi_remove_interface vif idx %d\\n\", sdr_compatible_str, vif_priv->idx);\n}\n\nstatic int openwifi_config(struct ieee80211_hw *dev, u32 changed)\n{\n  struct openwifi_priv *priv = dev->priv;\n  struct ieee80211_conf *conf = &dev->conf;\n  static struct ieee80211_conf channel_conf_tmp;\n  static struct ieee80211_channel channel_tmp;\n\n  channel_conf_tmp.chandef.chan = (&channel_tmp);\n\n  if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {\n    if ( priv->stat.restrict_freq_mhz>0 && (conf->chandef.chan->center_freq != priv->stat.restrict_freq_mhz) ) {\n      printk(\"%s openwifi_config avoid Linux requested freq %dMHz (restrict freq %dMHz)\\n\", sdr_compatible_str, \n      conf->chandef.chan->center_freq, priv->stat.restrict_freq_mhz);\n\n      channel_conf_tmp.chandef.chan->center_freq = priv->stat.restrict_freq_mhz;\n      priv->rf->set_chan(dev, &channel_conf_tmp);\n    } else {\n      priv->rf->set_chan(dev, conf);\n    }\n  } else\n    printk(\"%s openwifi_config changed flag %08x\\n\", sdr_compatible_str, changed);\n    \n  return 0;\n}\n\nstatic void openwifi_bss_info_changed(struct ieee80211_hw *dev,\n             struct ieee80211_vif *vif,\n             struct ieee80211_bss_conf *info,\n             u32 changed)\n{\n  struct openwifi_priv *priv = dev->priv;\n  struct openwifi_vif *vif_priv;\n  u32 bssid_low, bssid_high;\n\n  vif_priv = (struct openwifi_vif *)&vif->drv_priv;\n\n  //be careful: we don have valid chip, so registers addresses in priv->map->BSSID[0] are not valid! should not print it!\n  //printk(\"%s openwifi_bss_info_changed map bssid %02x%02x%02x%02x%02x%02x\\n\",sdr_compatible_str,priv->map->BSSID[0],priv->map->BSSID[1],priv->map->BSSID[2],priv->map->BSSID[3],priv->map->BSSID[4],priv->map->BSSID[5]);\n  if (changed & BSS_CHANGED_BSSID) {\n    printk(\"%s openwifi_bss_info_changed BSS_CHANGED_BSSID %02x%02x%02x%02x%02x%02x\\n\",sdr_compatible_str,info->bssid[0],info->bssid[1],info->bssid[2],info->bssid[3],info->bssid[4],info->bssid[5]);\n    // write new bssid to our HW, and do not change bssid filter\n    //u32 bssid_filter_high = xpu_api->XPU_REG_BSSID_FILTER_HIGH_read();\n    bssid_low = ( *( (u32*)(info->bssid) ) );\n    bssid_high = ( *( (u16*)(info->bssid+4) ) );\n\n    //bssid_filter_high = (bssid_filter_high&0x80000000);\n    //bssid_high = (bssid_high|bssid_filter_high);\n    xpu_api->XPU_REG_BSSID_FILTER_LOW_write(bssid_low);\n    xpu_api->XPU_REG_BSSID_FILTER_HIGH_write(bssid_high);\n  }\n\n  if (changed & BSS_CHANGED_BEACON_INT) {\n    printk(\"%s openwifi_bss_info_changed WARNING BSS_CHANGED_BEACON_INT %x\\n\",sdr_compatible_str,info->beacon_int);\n  }\n\n  if (changed & BSS_CHANGED_TXPOWER)\n    printk(\"%s openwifi_bss_info_changed WARNING BSS_CHANGED_TXPOWER %x\\n\",sdr_compatible_str,info->txpower);\n\n  if (changed & BSS_CHANGED_ERP_CTS_PROT)\n    printk(\"%s openwifi_bss_info_changed WARNING BSS_CHANGED_ERP_CTS_PROT %x\\n\",sdr_compatible_str,info->use_cts_prot);\n\n  if (changed & BSS_CHANGED_BASIC_RATES)\n    printk(\"%s openwifi_bss_info_changed WARNING BSS_CHANGED_BASIC_RATES %x\\n\",sdr_compatible_str,info->basic_rates);\n\n  if (changed & (BSS_CHANGED_ERP_SLOT | BSS_CHANGED_ERP_PREAMBLE)) {\n    printk(\"%s openwifi_bss_info_changed WARNING BSS_CHANGED_ERP_SLOT %d BSS_CHANGED_ERP_PREAMBLE %d short slot %d\\n\",sdr_compatible_str,\n    changed&BSS_CHANGED_ERP_SLOT,changed&BSS_CHANGED_ERP_PREAMBLE,info->use_short_slot);\n    if (info->use_short_slot && priv->use_short_slot==false) {\n      priv->use_short_slot=true;\n      xpu_api->XPU_REG_BAND_CHANNEL_write( (priv->use_short_slot<<24)|(priv->band<<16)|priv->actual_rx_lo );\n    } else if ((!info->use_short_slot) && priv->use_short_slot==true) {\n      priv->use_short_slot=false;\n      xpu_api->XPU_REG_BAND_CHANNEL_write( (priv->use_short_slot<<24)|(priv->band<<16)|priv->actual_rx_lo );\n    }\n  }\n\n  if (changed & BSS_CHANGED_BEACON_ENABLED) {\n    printk(\"%s openwifi_bss_info_changed WARNING BSS_CHANGED_BEACON_ENABLED\\n\",sdr_compatible_str);\n    vif_priv->enable_beacon = info->enable_beacon;\n  }\n\n  if (changed & (BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_BEACON)) {\n    cancel_delayed_work_sync(&vif_priv->beacon_work);\n    if (vif_priv->enable_beacon) {\n      schedule_work(&vif_priv->beacon_work.work);\n      printk(\"%s openwifi_bss_info_changed WARNING enable_beacon\\n\",sdr_compatible_str);\n    }\n    printk(\"%s openwifi_bss_info_changed WARNING BSS_CHANGED_BEACON_ENABLED %d BSS_CHANGED_BEACON %d\\n\",sdr_compatible_str,\n    changed&BSS_CHANGED_BEACON_ENABLED,changed&BSS_CHANGED_BEACON);\n  }\n}\n// helper function\nu32 log2val(u32 val){\n  u32 ret_val = 0 ;\n  while(val>1){\n    val = val >> 1 ;\n    ret_val ++ ;\n  }\n  return ret_val ;\n}\n\nstatic int openwifi_conf_tx(struct ieee80211_hw *dev, struct ieee80211_vif *vif, u16 queue,\n        const struct ieee80211_tx_queue_params *params)\n{\n  struct openwifi_priv *priv = dev->priv;\n  u32 reg_val, cw_min_exp, cw_max_exp; \n  \n  if (priv->stat.cw_max_min_cfg == 0) {\n    printk(\"%s openwifi_conf_tx: [queue %d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d, aifs and txop ignored\\n\",\n      sdr_compatible_str,queue,params->aifs,params->cw_min,params->cw_max,params->txop);\n\n    reg_val=xpu_api->XPU_REG_CSMA_CFG_read();\n    cw_min_exp = (log2val(params->cw_min + 1) & 0x0F);\n    cw_max_exp = (log2val(params->cw_max + 1) & 0x0F);\n    switch(queue){\n      case 0: reg_val = ( (reg_val & 0xFFFFFF00) | ((cw_min_exp | (cw_max_exp << 4)) << 0) );  break; \n      case 1: reg_val = ( (reg_val & 0xFFFF00FF) | ((cw_min_exp | (cw_max_exp << 4)) << 8) );  break; \n      case 2: reg_val = ( (reg_val & 0xFF00FFFF) | ((cw_min_exp | (cw_max_exp << 4)) << 16) ); break; \n      case 3: reg_val = ( (reg_val & 0x00FFFFFF) | ((cw_min_exp | (cw_max_exp << 4)) << 24) ); break;\n      default: printk(\"%s openwifi_conf_tx: WARNING queue %d does not exist\",sdr_compatible_str, queue); return(0);\n    }\n  } else {\n    reg_val = priv->stat.cw_max_min_cfg;\n    printk(\"%s openwifi_conf_tx: override cw max min for q3 to q0: %d %d; %d %d; %d %d; %d %d\\n\",\n      sdr_compatible_str,\n      (1<<((reg_val>>28)&0xF))-1, \n      (1<<((reg_val>>24)&0xF))-1, \n      (1<<((reg_val>>20)&0xF))-1, \n      (1<<((reg_val>>16)&0xF))-1, \n      (1<<((reg_val>>12)&0xF))-1, \n      (1<<((reg_val>> 8)&0xF))-1, \n      (1<<((reg_val>> 4)&0xF))-1, \n      (1<<((reg_val>> 0)&0xF))-1);\n  }\n  xpu_api->XPU_REG_CSMA_CFG_write(reg_val);\n  return(0);\n}\n\nstatic u64 openwifi_prepare_multicast(struct ieee80211_hw *dev,\n             struct netdev_hw_addr_list *mc_list)\n{\n  printk(\"%s openwifi_prepare_multicast\\n\", sdr_compatible_str);\n  return netdev_hw_addr_list_count(mc_list);\n}\n\nstatic void openwifi_configure_filter(struct ieee80211_hw *dev,\n             unsigned int changed_flags,\n             unsigned int *total_flags,\n             u64 multicast)\n{\n  struct openwifi_priv *priv = dev->priv;\n  u32 filter_flag;\n\n  (*total_flags) &= SDR_SUPPORTED_FILTERS;\n  (*total_flags) |= FIF_ALLMULTI; //because we need to pass all multicast (no matter it is for us or not) to upper layer\n\n  filter_flag = (*total_flags);\n\n  filter_flag = (filter_flag|UNICAST_FOR_US|BROADCAST_ALL_ONE|BROADCAST_ALL_ZERO);\n  //filter_flag = (filter_flag|UNICAST_FOR_US|BROADCAST_ALL_ONE|BROADCAST_ALL_ZERO|MONITOR_ALL); // all pkt will be delivered to arm\n\n  //if (priv->vif[0]->type == NL80211_IFTYPE_MONITOR)\n  if ((filter_flag&0xf0) == 0xf0) //FIF_BCN_PRBRESP_PROMISC/FIF_CONTROL/FIF_OTHER_BSS/FIF_PSPOLL are set means monitor mode  \n    filter_flag = (filter_flag|MONITOR_ALL);\n  else\n    filter_flag = (filter_flag&(~MONITOR_ALL));\n\n  if ( !(filter_flag&FIF_BCN_PRBRESP_PROMISC) )\n    filter_flag = (filter_flag|MY_BEACON);\n\n  filter_flag = (filter_flag|FIF_PSPOLL);\n\n  if (priv->stat.rx_monitor_all)\n    filter_flag = (filter_flag|MONITOR_ALL);\n\n  xpu_api->XPU_REG_FILTER_FLAG_write(filter_flag|HIGH_PRIORITY_DISCARD_FLAG);\n  //xpu_api->XPU_REG_FILTER_FLAG_write(filter_flag); //do not discard any pkt\n\n  printk(\"%s openwifi_configure_filter MON %d M_BCN %d BST0 %d BST1 %d UST %d PB_RQ %d PS_PL %d O_BSS %d CTL %d BCN_PRP %d PCP_FL %d FCS_FL %d ALL_MUT %d\\n\", sdr_compatible_str, \n  (filter_flag>>13)&1,(filter_flag>>12)&1,(filter_flag>>11)&1,(filter_flag>>10)&1,(filter_flag>>9)&1,(filter_flag>>8)&1,(filter_flag>>7)&1,(filter_flag>>6)&1,(filter_flag>>5)&1,(filter_flag>>4)&1,(filter_flag>>3)&1,(filter_flag>>2)&1,(filter_flag>>1)&1);\n}\n\nstatic int openwifi_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_ampdu_params *params)\n{\n  struct ieee80211_sta *sta = params->sta;\n  enum ieee80211_ampdu_mlme_action action = params->action;\n  // struct openwifi_priv *priv = hw->priv;\n  u16 max_tx_bytes, buf_size;\n  u32 ampdu_action_config;\n\n  if (!AGGR_ENABLE) {\n    return -EOPNOTSUPP;\n  }\n\n  switch (action)\n  {\n    case IEEE80211_AMPDU_TX_START:\n      ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, params->tid);\n      printk(\"%s openwifi_ampdu_action: start TX aggregation. tid %d\\n\", sdr_compatible_str, params->tid);\n      break;\n    case IEEE80211_AMPDU_TX_STOP_CONT:\n    case IEEE80211_AMPDU_TX_STOP_FLUSH:\n    case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:\n      ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, params->tid);\n      printk(\"%s openwifi_ampdu_action: stop TX aggregation. tid %d\\n\", sdr_compatible_str, params->tid);\n      break;\n    case IEEE80211_AMPDU_TX_OPERATIONAL:\n      buf_size = 4;\n//      buf_size = (params->buf_size) - 1;\n      max_tx_bytes = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + sta->ht_cap.ampdu_factor)) - 1;\n      ampdu_action_config = ( sta->ht_cap.ampdu_density<<24 | buf_size<<16 | max_tx_bytes );\n      tx_intf_api->TX_INTF_REG_AMPDU_ACTION_CONFIG_write(ampdu_action_config);\n      printk(\"%s openwifi_ampdu_action: TX operational. tid %d max_tx_bytes %d ampdu_density %d buf_size %d\\n\", \n      sdr_compatible_str, params->tid, max_tx_bytes, sta->ht_cap.ampdu_density, buf_size);\n      break;\n    case IEEE80211_AMPDU_RX_START:\n      printk(\"%s openwifi_ampdu_action: start RX aggregation. tid %d\\n\", sdr_compatible_str, params->tid);\n      break;\n    case IEEE80211_AMPDU_RX_STOP:\n      printk(\"%s openwifi_ampdu_action: stop RX aggregation. tid %d\\n\", sdr_compatible_str, params->tid);\n      break;\n    default:\n      return -EOPNOTSUPP;\n  }\n\n  return 0;\n}\n\nstatic const struct ieee80211_ops openwifi_ops = {\n  .tx             = openwifi_tx,\n  .start         = openwifi_start,\n  .stop         = openwifi_stop,\n  .add_interface     = openwifi_add_interface,\n  .remove_interface  = openwifi_remove_interface,\n  .config         = openwifi_config,\n  .set_antenna       = openwifi_set_antenna,\n  .get_antenna       = openwifi_get_antenna,\n  .bss_info_changed  = openwifi_bss_info_changed,\n  .conf_tx       = openwifi_conf_tx,\n  .prepare_multicast = openwifi_prepare_multicast,\n  .configure_filter  = openwifi_configure_filter,\n  .rfkill_poll     = openwifi_rfkill_poll,\n  .get_tsf       = openwifi_get_tsf,\n  .set_tsf       = openwifi_set_tsf,\n  .reset_tsf       = openwifi_reset_tsf,\n  .set_rts_threshold = openwifi_set_rts_threshold,\n  .ampdu_action      = openwifi_ampdu_action,\n  .testmode_cmd     = openwifi_testmode_cmd,\n};\n\nstatic const struct of_device_id openwifi_dev_of_ids[] = {\n  { .compatible = \"sdr,sdr\", },\n  {}\n};\nMODULE_DEVICE_TABLE(of, openwifi_dev_of_ids);\n\nstatic int custom_match_spi_dev(struct device *dev, const void *data)\n{\n  const char *name = data;\n\n  bool ret = sysfs_streq(name, dev->of_node->name);\n  printk(\"%s custom_match_spi_dev %s %s %d\\n\", sdr_compatible_str,name, dev->of_node->name, ret);\n  return ret;\n}\n\nstatic int custom_match_platform_dev(struct device *dev, const void *data)\n{\n  struct platform_device *plat_dev = to_platform_device(dev);\n  const char *name = data;\n  char *name_in_sys_bus_platform_devices = strstr(plat_dev->name, name);\n  bool match_flag = (name_in_sys_bus_platform_devices != NULL);\n\n  if (match_flag) {\n    printk(\"%s custom_match_platform_dev %s\\n\", sdr_compatible_str,plat_dev->name);\n  }\n  return(match_flag);\n}\n\nstatic int openwifi_dev_probe(struct platform_device *pdev)\n{\n  struct ieee80211_hw *dev;\n  struct openwifi_priv *priv;\n  struct device_node *dt_node;\n  int err=1, rand_val;\n  const char *fpga_model;\n  u32 reg, i;//, reg1;\n\n  struct device_node *np = pdev->dev.of_node;\n\n  struct device *tmp_dev;\n  struct platform_device *tmp_pdev;\n  struct iio_dev *tmp_indio_dev;\n  // struct gpio_leds_priv *tmp_led_priv;\n\n  printk(\"\\n\");\n\n  if (np) {\n    const struct of_device_id *match;\n\n    match = of_match_node(openwifi_dev_of_ids, np);\n    if (match) {\n      printk(\"%s openwifi_dev_probe: match!\\n\", sdr_compatible_str);\n      err = 0;\n    }\n  }\n\n  if (err)\n    return err;\n\n  dev = ieee80211_alloc_hw(sizeof(*priv), &openwifi_ops);\n  if (!dev) {\n    printk(KERN_ERR \"%s openwifi_dev_probe: ieee80211 alloc failed\\n\",sdr_compatible_str);\n    err = -ENOMEM;\n    goto err_free_dev;\n  }\n\n  priv = dev->priv;\n  priv->pdev = pdev;\n\n  err = of_property_read_string(of_find_node_by_path(\"/\"), \"model\", &fpga_model);\n  if(err < 0) {\n    priv->hardware_type = UNKNOWN_HARDWARE;\n    priv->fpga_type = SMALL_FPGA;\n    printk(\"%s openwifi_dev_probe: WARNING unknown openwifi FPGA model %d\\n\",sdr_compatible_str, err);\n    printk(\"%s openwifi_dev_probe: Try to detect TI lmk04828. If it exist, treate the board as RFSoC4x2\\n\",sdr_compatible_str);\n    dt_node = of_find_node_by_name(NULL, \"lmk\");\n    if (dt_node != NULL) {\n      printk(\"%s openwifi_dev_probe: found device tree node name %s\\n\",sdr_compatible_str, dt_node->name);\n      priv->hardware_type = RFSOC4X2;\n      priv->fpga_type = LARGE_FPGA;\n    } else {\n      printk(\"%s openwifi_dev_probe: WARNING device tree lmk node is not detected! %d\\n\",sdr_compatible_str, err);\n    }\n  } else {\n    if(strstr(fpga_model, \"ZCU102\") != NULL) {\n      priv->hardware_type = ZYNQMP_AD9361;\n    } else {\n      priv->hardware_type = ZYNQ_AD9361;\n    }\n\n    // LARGE FPGAs (i.e. ZCU102, Z7035, ZC706)\n    if(strstr(fpga_model, \"ZCU102\") != NULL || strstr(fpga_model, \"Z7035\") != NULL || strstr(fpga_model, \"ZC706\") != NULL) {\n      priv->fpga_type = LARGE_FPGA;\n    // SMALL FPGA: (i.e. ZED, ZC702, Z7020)\n    }//  else if(strstr(fpga_model, \"ZED\") != NULL || strstr(fpga_model, \"ZC702\") != NULL || strstr(fpga_model, \"Z7020\") != NULL) {\n    else { // ALL others are SAMLL_FPGA\n      priv->fpga_type = SMALL_FPGA;\n    }\n  }\n\n  priv->actual_rx_lo = 1000; //Some value aligned with rf_init/rf_init_11n.sh that is not WiFi channel to force ad9361_rf_set_channel execution triggered by Linux\n  priv->actual_tx_lo = 1000; //Some value aligned with rf_init/rf_init_11n.sh that is not WiFi channel to force ad9361_rf_set_channel execution triggered by Linux\n  priv->band = freq_MHz_to_band(priv->actual_rx_lo);\n  priv->use_short_slot = false; //this can be changed by openwifi_bss_info_changed: BSS_CHANGED_ERP_SLOT\n  priv->ampdu_reference = 0;\n  priv->last_tx_quad_cal_lo = 1000;\n\n  if (priv->hardware_type != RFSOC4X2) {\n    // //-------------find ad9361-phy driver for lo/channel control---------------\n    tmp_dev = bus_find_device( &spi_bus_type, NULL, \"ad9361-phy\", custom_match_spi_dev );\n    if (tmp_dev == NULL) {\n      printk(KERN_ERR \"%s find_dev ad9361-phy failed\\n\",sdr_compatible_str);\n      err = -ENODEV;\n      goto err_free_dev;\n    }\n    printk(\"%s bus_find_device ad9361-phy: %s. driver_data pointer %p\\n\", sdr_compatible_str, ((struct spi_device*)tmp_dev)->modalias, (void*)(((struct spi_device*)tmp_dev)->dev.driver_data));\n    if (((struct spi_device*)tmp_dev)->dev.driver_data == NULL) {\n      printk(KERN_ERR \"%s find_dev ad9361-phy failed. dev.driver_data == NULL\\n\",sdr_compatible_str);\n      err = -ENODEV;\n      goto err_free_dev;\n    }\n    \n    priv->ad9361_phy = ad9361_spi_to_phy((struct spi_device*)tmp_dev);\n    if (!(priv->ad9361_phy)) {\n      printk(KERN_ERR \"%s ad9361_spi_to_phy failed\\n\",sdr_compatible_str);\n      err = -ENODEV;\n      goto err_free_dev;\n    }\n    printk(\"%s ad9361_spi_to_phy ad9361-phy: %s\\n\", sdr_compatible_str, priv->ad9361_phy->spi->modalias);\n\n    // //-------------find driver: axi_ad9361 hdl ref design module, dac channel---------------\n    tmp_dev = bus_find_device( &platform_bus_type, NULL, \"cf-ad9361-dds-core-lpc\", custom_match_platform_dev );\n    if (!tmp_dev) {\n      printk(KERN_ERR \"%s bus_find_device platform_bus_type cf-ad9361-dds-core-lpc failed\\n\",sdr_compatible_str);\n      err = -ENODEV;\n      goto err_free_dev;\n    }\n\n    tmp_pdev = to_platform_device(tmp_dev);\n    if (!tmp_pdev) {\n      printk(KERN_ERR \"%s to_platform_device failed\\n\",sdr_compatible_str);\n      err = -ENODEV;\n      goto err_free_dev;\n    }\n\n    tmp_indio_dev = platform_get_drvdata(tmp_pdev);\n    if (!tmp_indio_dev) {\n      printk(KERN_ERR \"%s platform_get_drvdata failed\\n\",sdr_compatible_str);\n      err = -ENODEV;\n      goto err_free_dev;\n    }\n\n    priv->dds_st = iio_priv(tmp_indio_dev);\n    if (!(priv->dds_st)) {\n      printk(KERN_ERR \"%s iio_priv failed\\n\",sdr_compatible_str);\n      err = -ENODEV;\n      goto err_free_dev;\n    }\n    printk(\"%s openwifi_dev_probe: cf-ad9361-dds-core-lpc dds_st->version %08x chip_info->name %s\\n\",sdr_compatible_str,priv->dds_st->version,priv->dds_st->chip_info->name);\n    cf_axi_dds_datasel(priv->dds_st, -1, DATA_SEL_DMA);\n    printk(\"%s openwifi_dev_probe: cf_axi_dds_datasel DATA_SEL_DMA\\n\",sdr_compatible_str);\n\n    // //-------------find driver: axi_ad9361 hdl ref design module, adc channel---------------\n    // turn off radio by muting tx\n    // ad9361_tx_mute(priv->ad9361_phy, 1);\n    // reg = ad9361_get_tx_atten(priv->ad9361_phy, 2);\n    // reg1 = ad9361_get_tx_atten(priv->ad9361_phy, 1);\n    // if (reg == AD9361_RADIO_OFF_TX_ATT && reg1 == AD9361_RADIO_OFF_TX_ATT ) {\n    //   priv->rfkill_off = 0;// 0 off, 1 on\n    //   printk(\"%s openwifi_dev_probe: rfkill radio off\\n\",sdr_compatible_str);\n    // }\n    // else\n    //   printk(\"%s openwifi_dev_probe: WARNING rfkill radio off failed. tx att read %d %d require %d\\n\",sdr_compatible_str, reg, reg1, AD9361_RADIO_OFF_TX_ATT);\n  } else { //construct a fake ad9361_phy as a temporary solution\n    priv->ad9361_phy = &ad9361_phy_fake;\n    priv->ad9361_phy->state = &ad9361_phy_state_fake;\n  }\n\n  // //-----------------------------parse the test_mode input--------------------------------\n  if (test_mode&1)\n    AGGR_ENABLE = true;\n  \n  // if (test_mode&2)\n  //   TX_OFFSET_TUNING_ENABLE = false;\n\n  priv->rssi_correction = rssi_correction_lookup_table(5220);//5220MHz. this will be set in real-time by _rf_set_channel()\n  priv->last_auto_fpga_lbt_th = rssi_dbm_to_rssi_half_db(-78, priv->rssi_correction);//-78dBm. a magic value. just to avoid uninitialized\n\n  //priv->rf_bw = 20000000; // Signal quality issue! NOT use for now. 20MHz or 40MHz. 40MHz need ddc/duc. 20MHz works in bypass mode\n  priv->rf_bw = 40000000; // 20MHz or 40MHz. 40MHz need ddc/duc. 20MHz works in bypass mode\n\n  priv->xpu_cfg = XPU_NORMAL;\n\n  priv->openofdm_tx_cfg = OPENOFDM_TX_NORMAL;\n  priv->openofdm_rx_cfg = OPENOFDM_RX_NORMAL;\n\n  printk(\"%s openwifi_dev_probe: priv->rf_bw == %dHz. bool for 20000000 %d, 40000000 %d\\n\",sdr_compatible_str, priv->rf_bw, (priv->rf_bw==20000000) , (priv->rf_bw==40000000) );\n  if (priv->rf_bw == 20000000) { //DO NOT USE. Not used for long time.\n    priv->rx_intf_cfg = RX_INTF_BYPASS;\n    priv->tx_intf_cfg = TX_INTF_BYPASS;\n    //priv->rx_freq_offset_to_lo_MHz = 0;\n    //priv->tx_freq_offset_to_lo_MHz = 0;\n  } else if (priv->rf_bw == 40000000) {\n    //priv->rx_intf_cfg = RX_INTF_BW_20MHZ_AT_P_10MHZ; //work\n    //priv->tx_intf_cfg = TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1; //work\n\n    // // test ddc at central, duc at central+10M. It works. And also change rx BW from 40MHz to 20MHz in rf_init.sh. Rx sampling rate is still 40Msps\n    priv->rx_intf_cfg = RX_INTF_BW_20MHZ_AT_0MHZ_ANT0;\n    if (TX_OFFSET_TUNING_ENABLE)\n      priv->tx_intf_cfg = TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0; // Let's use rx0 tx0 as default mode, because it works for both 9361 and 9364\n    else\n      priv->tx_intf_cfg = TX_INTF_BW_20MHZ_AT_0MHZ_ANT0;\n    // // try another antenna option\n    //priv->rx_intf_cfg = RX_INTF_BW_20MHZ_AT_0MHZ_ANT1;\n    //priv->tx_intf_cfg = TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0;\n    \n    #if 0\n    if (priv->rx_intf_cfg == DDC_BW_20MHZ_AT_N_10MHZ) {\n      priv->rx_freq_offset_to_lo_MHz = -10;\n    } else if (priv->rx_intf_cfg == DDC_BW_20MHZ_AT_P_10MHZ) {\n      priv->rx_freq_offset_to_lo_MHz = 10;\n    } else if (priv->rx_intf_cfg == DDC_BW_20MHZ_AT_0MHZ) {\n      priv->rx_freq_offset_to_lo_MHz = 0;\n    } else {\n      printk(\"%s openwifi_dev_probe: Warning! priv->rx_intf_cfg == %d\\n\",sdr_compatible_str,priv->rx_intf_cfg);\n    }\n    #endif\n  } else {\n    printk(\"%s openwifi_dev_probe: Warning! priv->rf_bw == %dHz (should be 20000000 or 40000000)\\n\",sdr_compatible_str, priv->rf_bw);\n    err = -EBADRQC;\n    goto err_free_dev;\n  }\n\n  printk(\"%s openwifi_dev_probe: test_mode %x AGGR_ENABLE %d TX_OFFSET_TUNING_ENABLE %d init_tx_att %d\\n\", sdr_compatible_str, test_mode, AGGR_ENABLE, TX_OFFSET_TUNING_ENABLE, init_tx_att);\n\n  priv->runtime_tx_ant_cfg = ((priv->tx_intf_cfg==TX_INTF_BW_20MHZ_AT_0MHZ_ANT0 || priv->tx_intf_cfg==TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0)?1:(priv->tx_intf_cfg==TX_INTF_BW_20MHZ_AT_0MHZ_ANT_BOTH?3:2));\n  priv->runtime_rx_ant_cfg = (priv->rx_intf_cfg==RX_INTF_BW_20MHZ_AT_0MHZ_ANT0?1:2);\n\n  priv->ctrl_out.en_mask=AD9361_CTRL_OUT_EN_MASK;\n  priv->ctrl_out.index  =(priv->rx_intf_cfg==RX_INTF_BW_20MHZ_AT_0MHZ_ANT0?AD9361_CTRL_OUT_INDEX_ANT0:AD9361_CTRL_OUT_INDEX_ANT1);\n\n  memset(priv->drv_rx_reg_val,0,sizeof(priv->drv_rx_reg_val));\n  memset(priv->drv_tx_reg_val,0,sizeof(priv->drv_tx_reg_val));\n  memset(priv->drv_xpu_reg_val,0,sizeof(priv->drv_xpu_reg_val));\n  memset(priv->rf_reg_val,0,sizeof(priv->rf_reg_val));\n\n  priv->rf_reg_val[RF_TX_REG_IDX_ATT] = init_tx_att;\n\n  //let's by default turn radio on when probing\n  err = openwifi_set_antenna(dev, priv->runtime_tx_ant_cfg, priv->runtime_rx_ant_cfg);\n  if (err) {\n    printk(\"%s openwifi_dev_probe: WARNING openwifi_set_antenna FAIL %d\\n\",sdr_compatible_str, err);\n    err = -EIO;\n    goto err_free_dev;\n  }\n  reg = ad9361_spi_read(priv->ad9361_phy->spi, REG_CTRL_OUTPUT_POINTER);\n  printk(\"%s openwifi_dev_probe: ad9361_spi_read REG_CTRL_OUTPUT_POINTER 0x%02x\\n\",sdr_compatible_str, reg);\n  reg = ad9361_spi_read(priv->ad9361_phy->spi, REG_CTRL_OUTPUT_ENABLE);\n  printk(\"%s openwifi_dev_probe: ad9361_spi_read REG_CTRL_OUTPUT_ENABLE 0x%02x\\n\",sdr_compatible_str, reg);\n\n  reg = ad9361_get_tx_atten(priv->ad9361_phy, ((priv->runtime_tx_ant_cfg==1 || priv->runtime_tx_ant_cfg==3)?1:2));\n  if (reg == (AD9361_RADIO_ON_TX_ATT+priv->rf_reg_val[RF_TX_REG_IDX_ATT])) {\n    priv->rfkill_off = 1;// 0 off, 1 on\n    printk(\"%s openwifi_dev_probe: rfkill radio on\\n\",sdr_compatible_str);\n  } else\n    printk(\"%s openwifi_dev_probe: WARNING rfkill radio on failed. tx att read %d require %d\\n\",sdr_compatible_str, reg, AD9361_RADIO_ON_TX_ATT+priv->rf_reg_val[RF_TX_REG_IDX_ATT]);\n\n  priv->drv_xpu_reg_val[DRV_XPU_REG_IDX_GIT_REV] = GIT_REV;\n\n  // //set ad9361 in certain mode\n  #if 0\n  err = ad9361_set_trx_clock_chain_freq(priv->ad9361_phy,priv->rf_bw);\n  printk(\"%s openwifi_dev_probe: ad9361_set_trx_clock_chain_freq %dHz err %d\\n\",sdr_compatible_str, priv->rf_bw,err);\n  err = ad9361_update_rf_bandwidth(priv->ad9361_phy,priv->rf_bw,priv->rf_bw);\n  printk(\"%s openwifi_dev_probe: ad9361_update_rf_bandwidth %dHz err %d\\n\",sdr_compatible_str, priv->rf_bw,err);\n\n  rx_intf_api->hw_init(priv->rx_intf_cfg,8,8);\n  tx_intf_api->hw_init(priv->tx_intf_cfg,8,8,priv->fpga_type);\n  openofdm_tx_api->hw_init(priv->openofdm_tx_cfg);\n  openofdm_rx_api->hw_init(priv->openofdm_rx_cfg);\n  printk(\"%s openwifi_dev_probe: rx_intf_cfg %d openofdm_rx_cfg %d tx_intf_cfg %d openofdm_tx_cfg %d\\n\",sdr_compatible_str, priv->rx_intf_cfg, priv->openofdm_rx_cfg, priv->tx_intf_cfg, priv->openofdm_tx_cfg);\n  printk(\"%s openwifi_dev_probe: rx_freq_offset_to_lo_MHz %d tx_freq_offset_to_lo_MHz %d\\n\",sdr_compatible_str, priv->rx_freq_offset_to_lo_MHz, priv->tx_freq_offset_to_lo_MHz);\n  #endif\n\n  dev->max_rates = 1; //maximum number of alternate rate retry stages the hw can handle.\n\n  SET_IEEE80211_DEV(dev, &pdev->dev);\n  platform_set_drvdata(pdev, dev);\n\n  BUILD_BUG_ON(sizeof(priv->rates_2GHz) != sizeof(openwifi_2GHz_rates));\n  BUILD_BUG_ON(sizeof(priv->rates_5GHz) != sizeof(openwifi_5GHz_rates));\n  BUILD_BUG_ON(sizeof(priv->channels_2GHz) != sizeof(openwifi_2GHz_channels));\n  BUILD_BUG_ON(sizeof(priv->channels_5GHz) != sizeof(openwifi_5GHz_channels));\n\n  memcpy(priv->rates_2GHz, openwifi_2GHz_rates, sizeof(openwifi_2GHz_rates));\n  memcpy(priv->rates_5GHz, openwifi_5GHz_rates, sizeof(openwifi_5GHz_rates));\n  memcpy(priv->channels_2GHz, openwifi_2GHz_channels, sizeof(openwifi_2GHz_channels));\n  memcpy(priv->channels_5GHz, openwifi_5GHz_channels, sizeof(openwifi_5GHz_channels));\n\n  priv->band_2GHz.band = NL80211_BAND_2GHZ;\n  priv->band_2GHz.channels = priv->channels_2GHz;\n  priv->band_2GHz.n_channels = ARRAY_SIZE(priv->channels_2GHz);\n  priv->band_2GHz.bitrates = priv->rates_2GHz;\n  priv->band_2GHz.n_bitrates = ARRAY_SIZE(priv->rates_2GHz);\n  priv->band_2GHz.ht_cap.ht_supported = true;\n\n  if (test_mode&2)\n    priv->band_2GHz.ht_cap.cap = IEEE80211_HT_CAP_SGI_20; //SGI -- short GI seems bring unnecessary stability issue\n  \n  if (AGGR_ENABLE) {\n    priv->band_2GHz.ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_8K;\n    priv->band_2GHz.ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_2;\n  }\n  memset(&priv->band_2GHz.ht_cap.mcs, 0, sizeof(priv->band_2GHz.ht_cap.mcs));\n  priv->band_2GHz.ht_cap.mcs.rx_mask[0] = 0xff;\n  priv->band_2GHz.ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;\n  dev->wiphy->bands[NL80211_BAND_2GHZ] = &(priv->band_2GHz);\n\n  priv->band_5GHz.band = NL80211_BAND_5GHZ;\n  priv->band_5GHz.channels = priv->channels_5GHz;\n  priv->band_5GHz.n_channels = ARRAY_SIZE(priv->channels_5GHz);\n  priv->band_5GHz.bitrates = priv->rates_5GHz;\n  priv->band_5GHz.n_bitrates = ARRAY_SIZE(priv->rates_5GHz);\n  priv->band_5GHz.ht_cap.ht_supported = true;\n\n  if (test_mode&2)\n    priv->band_5GHz.ht_cap.cap = IEEE80211_HT_CAP_SGI_20; //SGI -- short GI seems bring unnecessary stability issue\n  \n  if (AGGR_ENABLE) {\n    priv->band_5GHz.ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_8K;\n    priv->band_5GHz.ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_2;\n  }\n  memset(&priv->band_5GHz.ht_cap.mcs, 0, sizeof(priv->band_5GHz.ht_cap.mcs));\n  priv->band_5GHz.ht_cap.mcs.rx_mask[0] = 0xff;\n  priv->band_5GHz.ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;\n  dev->wiphy->bands[NL80211_BAND_5GHZ] = &(priv->band_5GHz);\n\n  printk(\"%s openwifi_dev_probe: band_2GHz.n_channels %d n_bitrates %d band_5GHz.n_channels %d n_bitrates %d\\n\",sdr_compatible_str,\n  priv->band_2GHz.n_channels,priv->band_2GHz.n_bitrates,priv->band_5GHz.n_channels,priv->band_5GHz.n_bitrates);\n\n  // ieee80211_hw_set(dev, HOST_BROADCAST_PS_BUFFERING); // remove this because we don't want: mac80211.h: host buffers frame for PS and we fetch them via ieee80211_get_buffered_bc()\n  ieee80211_hw_set(dev, RX_INCLUDES_FCS);\n  ieee80211_hw_set(dev, BEACON_TX_STATUS);//mac80211.h: The device/driver provides TX status for sent beacons.\n\n  ieee80211_hw_set(dev, REPORTS_TX_ACK_STATUS);//mac80211.h: Hardware can provide ack status reports of Tx frames to the stack\n\n  // * @IEEE80211_HW_AP_LINK_PS: When operating in AP mode the device\n  // *  autonomously manages the PS status of connected stations. When\n  // *  this flag is set mac80211 will not trigger PS mode for connected\n  // *  stations based on the PM bit of incoming frames.\n  // *  Use ieee80211_start_ps()/ieee8021_end_ps() to manually configure\n  // *  the PS mode of connected stations.\n  ieee80211_hw_set(dev, AP_LINK_PS);\n\n  if (AGGR_ENABLE) {\n    ieee80211_hw_set(dev, AMPDU_AGGREGATION);\n  }\n\n  dev->extra_tx_headroom = LEN_MPDU_DELIM;\n\n  dev->vif_data_size = sizeof(struct openwifi_vif);\n  dev->wiphy->interface_modes = \n      BIT(NL80211_IFTYPE_MONITOR)|\n      BIT(NL80211_IFTYPE_P2P_GO) |\n      BIT(NL80211_IFTYPE_P2P_CLIENT) |\n      BIT(NL80211_IFTYPE_AP) |\n      BIT(NL80211_IFTYPE_STATION) |\n      BIT(NL80211_IFTYPE_ADHOC) |\n      BIT(NL80211_IFTYPE_MESH_POINT) |\n      BIT(NL80211_IFTYPE_OCB);\n  dev->wiphy->iface_combinations = &openwifi_if_comb;\n  dev->wiphy->n_iface_combinations = 1;\n\n  dev->wiphy->available_antennas_tx = NUM_TX_ANT_MASK;\n  dev->wiphy->available_antennas_rx = NUM_RX_ANT_MASK;\n\n  dev->wiphy->regulatory_flags = (REGULATORY_STRICT_REG|REGULATORY_CUSTOM_REG); // use our own config within strict regulation\n  //dev->wiphy->regulatory_flags = REGULATORY_CUSTOM_REG; // use our own config\n  wiphy_apply_custom_regulatory(dev->wiphy, &sdr_regd);\n\n  /* we declare to MAC80211 all the queues except for beacon queue\n   * that will be eventually handled by DRV.\n   * TX rings are arranged in such a way that lower is the IDX,\n   * higher is the priority, in order to achieve direct mapping\n   * with mac80211, however the beacon queue is an exception and it\n   * is mapped on the highst tx ring IDX.\n   */\n  dev->queues = MAX_NUM_HW_QUEUE;\n\n  ieee80211_hw_set(dev, SIGNAL_DBM);\n\n  wiphy_ext_feature_set(dev->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);\n\n  if (priv->hardware_type == RFSOC4X2) {\n    priv->rf = &rfsoc4x2_rf_ops;\n  } else {\n    priv->rf = &ad9361_rf_ops;\n  }\n\n  memset(priv->dest_mac_addr_queue_map,0,sizeof(priv->dest_mac_addr_queue_map));\n  priv->slice_idx = 0xFFFFFFFF;\n\n  sg_init_table(&(priv->tx_sg), 1);\n\n  get_random_bytes(&rand_val, sizeof(rand_val));\n    rand_val%=250;\n  priv->mac_addr[0]=0x66;  priv->mac_addr[1]=0x55;  priv->mac_addr[2]=0x44;  priv->mac_addr[3]=0x33;  priv->mac_addr[4]=0x22;\n  priv->mac_addr[5]=rand_val+1;\n  //priv->mac_addr[5]=0x11;\n  if (!is_valid_ether_addr(priv->mac_addr)) {\n    printk(KERN_WARNING \"%s openwifi_dev_probe: WARNING Invalid hwaddr! Using randomly generated MAC addr\\n\",sdr_compatible_str);\n    eth_random_addr(priv->mac_addr);\n  }\n  printk(\"%s openwifi_dev_probe: mac_addr %02x:%02x:%02x:%02x:%02x:%02x\\n\",sdr_compatible_str,priv->mac_addr[0],priv->mac_addr[1],priv->mac_addr[2],priv->mac_addr[3],priv->mac_addr[4],priv->mac_addr[5]);\n  SET_IEEE80211_PERM_ADDR(dev, priv->mac_addr);\n\n  spin_lock_init(&priv->lock);\n\n  err = ieee80211_register_hw(dev);\n  if (err) {\n    pr_err(KERN_ERR \"%s openwifi_dev_probe: WARNING Cannot register device\\n\",sdr_compatible_str);\n    err = -EIO;\n    goto err_free_dev;\n  } else {\n    printk(\"%s openwifi_dev_probe: ieee80211_register_hw %d\\n\",sdr_compatible_str, err);\n  }\n\n  // create sysfs for arbitrary iq setting\n  sysfs_bin_attr_init(&priv->bin_iq);\n  priv->bin_iq.attr.name = \"tx_intf_iq_data\";\n  priv->bin_iq.attr.mode = S_IWUSR | S_IRUGO;\n  priv->bin_iq.write = openwifi_tx_intf_bin_iq_write;\n  priv->bin_iq.read = openwifi_tx_intf_bin_iq_read;\n  priv->bin_iq.size = 4096;\n  err = sysfs_create_bin_file(&pdev->dev.kobj, &priv->bin_iq);\n  printk(\"%s openwifi_dev_probe: sysfs_create_bin_file %d\\n\",sdr_compatible_str, err);\n  if (err < 0)\n    goto err_free_dev;\n\n  priv->tx_intf_arbitrary_iq_num = 0;\n  // priv->tx_intf_arbitrary_iq[0] = 1;\n  // priv->tx_intf_arbitrary_iq[1] = 2;\n\n  err = sysfs_create_group(&pdev->dev.kobj, &tx_intf_attribute_group);\n  printk(\"%s openwifi_dev_probe: sysfs_create_group tx_intf_attribute_group %d\\n\",sdr_compatible_str, err);\n  if (err < 0)\n    goto err_free_dev;\n  priv->tx_intf_iq_ctl = 0;\n\n  // create sysfs for stat\n  err = sysfs_create_group(&pdev->dev.kobj, &stat_attribute_group);\n  printk(\"%s openwifi_dev_probe: sysfs_create_group stat_attribute_group %d\\n\",sdr_compatible_str, err);\n  if (err < 0)\n    goto err_free_dev;\n\n  priv->stat.stat_enable = 0; // by default disable\n  \n  for (i=0; i<MAX_NUM_SW_QUEUE; i++) {\n    priv->stat.tx_prio_num[i] = 0;\n    priv->stat.tx_prio_interrupt_num[i] = 0;\n    priv->stat.tx_prio_stop0_fake_num[i] = 0;\n    priv->stat.tx_prio_stop0_real_num[i] = 0;\n    priv->stat.tx_prio_stop1_num[i] = 0;\n    priv->stat.tx_prio_wakeup_num[i] = 0;\n  }\n  for (i=0; i<MAX_NUM_HW_QUEUE; i++) {\n    priv->stat.tx_queue_num[i] = 0;\n    priv->stat.tx_queue_interrupt_num[i] = 0;\n    priv->stat.tx_queue_stop0_fake_num[i] = 0;\n    priv->stat.tx_queue_stop0_real_num[i] = 0;\n    priv->stat.tx_queue_stop1_num[i] = 0;\n    priv->stat.tx_queue_wakeup_num[i] = 0;\n  }\n    \n  priv->stat.tx_data_pkt_need_ack_num_total = 0;\n  priv->stat.tx_data_pkt_need_ack_num_total_fail = 0;\n  for (i=0; i<6; i++) {\n    priv->stat.tx_data_pkt_need_ack_num_retx[i] = 0;\n    priv->stat.tx_data_pkt_need_ack_num_retx_fail[i] = 0;\n  }\n  priv->stat.tx_data_pkt_mcs_realtime = 0;\n  priv->stat.tx_data_pkt_fail_mcs_realtime = 0;\n\n  priv->stat.tx_mgmt_pkt_need_ack_num_total = 0;\n  priv->stat.tx_mgmt_pkt_need_ack_num_total_fail = 0;\n  for (i=0; i<3; i++) {\n    priv->stat.tx_mgmt_pkt_need_ack_num_retx[i] = 0;\n    priv->stat.tx_mgmt_pkt_need_ack_num_retx_fail[i] = 0;\n  }\n  priv->stat.tx_mgmt_pkt_mcs_realtime = 0;\n  priv->stat.tx_mgmt_pkt_fail_mcs_realtime = 0;\n\n  priv->stat.rx_monitor_all = 0;\n  priv->stat.rx_target_sender_mac_addr = 0;\n  priv->stat.rx_data_ok_agc_gain_value_realtime = 0;\n  priv->stat.rx_data_fail_agc_gain_value_realtime = 0;\n  priv->stat.rx_mgmt_ok_agc_gain_value_realtime = 0;\n  priv->stat.rx_mgmt_fail_agc_gain_value_realtime = 0;\n  priv->stat.rx_ack_ok_agc_gain_value_realtime = 0;\n\n  priv->stat.rx_monitor_all = 0;\n  priv->stat.rx_data_pkt_num_total = 0;\n  priv->stat.rx_data_pkt_num_fail = 0;\n  priv->stat.rx_mgmt_pkt_num_total = 0;\n  priv->stat.rx_mgmt_pkt_num_fail = 0;\n  priv->stat.rx_ack_pkt_num_total = 0;\n  priv->stat.rx_ack_pkt_num_fail = 0;\n\n  priv->stat.rx_data_pkt_mcs_realtime = 0;\n  priv->stat.rx_data_pkt_fail_mcs_realtime = 0;\n  priv->stat.rx_mgmt_pkt_mcs_realtime = 0;\n  priv->stat.rx_mgmt_pkt_fail_mcs_realtime = 0;\n  priv->stat.rx_ack_pkt_mcs_realtime = 0;\n\n  priv->stat.restrict_freq_mhz = 0;\n\n  priv->stat.csma_cfg0 = 0;\n  priv->stat.cw_max_min_cfg = 0;\n\n  priv->stat.dbg_ch0 = 0;\n  priv->stat.dbg_ch1 = 0;\n  priv->stat.dbg_ch2 = 0;\n\n  // // //--------------------hook leds (not complete yet)--------------------------------\n  // tmp_dev = bus_find_device( &platform_bus_type, NULL, \"leds\", custom_match_platform_dev ); //leds is the name in devicetree, not \"compatible\" field\n  // if (!tmp_dev) {\n  //   printk(KERN_ERR \"%s bus_find_device platform_bus_type leds-gpio failed\\n\",sdr_compatible_str);\n  //   err = -ENOMEM;\n  //   goto err_free_dev;\n  // }\n\n  // tmp_pdev = to_platform_device(tmp_dev);\n  // if (!tmp_pdev) {\n  //   printk(KERN_ERR \"%s to_platform_device failed for leds-gpio\\n\",sdr_compatible_str);\n  //   err = -ENOMEM;\n  //   goto err_free_dev;\n  // }\n\n  // tmp_led_priv = platform_get_drvdata(tmp_pdev);\n  // if (!tmp_led_priv) {\n  //   printk(KERN_ERR \"%s platform_get_drvdata failed for leds-gpio\\n\",sdr_compatible_str);\n  //   err = -ENOMEM;\n  //   goto err_free_dev;\n  // }\n  // printk(\"%s openwifi_dev_probe: leds-gpio detect %d leds!\\n\",sdr_compatible_str, tmp_led_priv->num_leds);\n  // if (tmp_led_priv->num_leds!=4){\n  //   printk(KERN_ERR \"%s WARNING we expect 4 leds, but actual %d leds\\n\",sdr_compatible_str,tmp_led_priv->num_leds);\n  //   err = -ENOMEM;\n  //   goto err_free_dev;\n  // }\n  // gpiod_set_value(tmp_led_priv->leds[0].gpiod, 1);//light it\n  // gpiod_set_value(tmp_led_priv->leds[3].gpiod, 0);//black it\n  // priv->num_led = tmp_led_priv->num_leds;\n  // priv->led[0] = &(tmp_led_priv->leds[0].cdev);\n  // priv->led[1] = &(tmp_led_priv->leds[1].cdev);\n  // priv->led[2] = &(tmp_led_priv->leds[2].cdev);\n  // priv->led[3] = &(tmp_led_priv->leds[3].cdev);\n\n  // snprintf(priv->led_name[0], OPENWIFI_LED_MAX_NAME_LEN, \"openwifi-%s::radio\", wiphy_name(dev->wiphy));\n  // snprintf(priv->led_name[1], OPENWIFI_LED_MAX_NAME_LEN, \"openwifi-%s::assoc\", wiphy_name(dev->wiphy));\n  // snprintf(priv->led_name[2], OPENWIFI_LED_MAX_NAME_LEN, \"openwifi-%s::tx\", wiphy_name(dev->wiphy));\n  // snprintf(priv->led_name[3], OPENWIFI_LED_MAX_NAME_LEN, \"openwifi-%s::rx\", wiphy_name(dev->wiphy));\n  \n  wiphy_info(dev->wiphy, \"hwaddr %pm, FPGA %s\\n\",\n       priv->mac_addr, priv->rf->name);\n\n  openwifi_rfkill_init(dev);\n  return 0;\n\n err_free_dev:\n  ieee80211_free_hw(dev);\n\n  return err;\n}\n\nstatic int openwifi_dev_remove(struct platform_device *pdev)\n{\n  struct ieee80211_hw *dev = platform_get_drvdata(pdev);\n  struct openwifi_priv *priv = dev->priv;\n\n  if (!dev) {\n    pr_info(\"%s openwifi_dev_remove: dev %p\\n\", sdr_compatible_str, (void*)dev);\n    return(-1);\n  }\n\n  sysfs_remove_bin_file(&pdev->dev.kobj, &priv->bin_iq);\n  sysfs_remove_group(&pdev->dev.kobj, &tx_intf_attribute_group);\n  sysfs_remove_group(&pdev->dev.kobj, &stat_attribute_group);\n\n  openwifi_rfkill_exit(dev);\n  ieee80211_unregister_hw(dev);\n  ieee80211_free_hw(dev);\n  return(0);\n}\n\nstatic struct platform_driver openwifi_dev_driver = {\n  .driver = {\n    .name = \"sdr,sdr\",\n    .owner = THIS_MODULE,\n    .of_match_table = openwifi_dev_of_ids,\n  },\n  .probe = openwifi_dev_probe,\n  .remove = openwifi_dev_remove,\n};\n\nmodule_platform_driver(openwifi_dev_driver);\n"
  },
  {
    "path": "driver/sdr.h",
    "content": "// Author: Xianjun Jiao, Michael Mehari, Wei Liu\n// SPDX-FileCopyrightText: 2019 UGent\n// SPDX-License-Identifier: AGPL-3.0-or-later\n\n#ifndef OPENWIFI_SDR\n#define OPENWIFI_SDR\n\n#include \"pre_def.h\"\n\n// -------------------for leds--------------------------------\nstruct gpio_led_data { //please always align with the leds-gpio.c in linux kernel\n  struct led_classdev cdev;\n  struct gpio_desc *gpiod;\n  u8 can_sleep;\n  u8 blinking;\n  gpio_blink_set_t platform_gpio_blink_set;\n};\n\nstruct gpio_leds_priv { //please always align with the leds-gpio.c in linux kernel\n  int num_leds;\n  struct gpio_led_data leds[];\n};\n\nstruct openwifi_rf_ops {\n  char *name;\n//  void (*init)(struct ieee80211_hw *);\n//  void (*stop)(struct ieee80211_hw *);\n  void (*set_chan)(struct ieee80211_hw *, struct ieee80211_conf *);\n//  u8 (*calc_rssi)(u8 agc, u8 sq);\n};\n\nstruct openwifi_buffer_descriptor {\n  // u32 num_dma_byte;\n  // u32 sn;\n  // u32 hw_queue_idx;\n  // u32 retry_limit;\n  // u32 need_ack;\n  u8 prio;\n  u16 len_mpdu;\n  u16 seq_no;\n  struct sk_buff *skb_linked;\n  dma_addr_t dma_mapping_addr;\n  // u32 reserved;\n} __packed;\n\nstruct openwifi_ring {\n  struct openwifi_buffer_descriptor *bds;\n  u32 bd_wr_idx;\n  u32 bd_rd_idx;\n  int stop_flag; // -1: normal run; X>=0: stop due to queueX full\n  // u32 num_dma_symbol_request;\n  // u32 reserved;\n} __packed;\n\nstruct openwifi_vif {\n  struct ieee80211_hw *dev;\n\n  int idx; // this vif's idx on the dev\n\n  /* beaconing */\n  struct delayed_work beacon_work;\n  bool enable_beacon;\n};\n\nunion u32_byte4 {\n  u32 a;\n  u8 c[4];\n};\nunion u16_byte2 {\n  u16 a;\n  u8 c[2];\n};\n\n#define MAX_NUM_LED 4\n#define OPENWIFI_LED_MAX_NAME_LEN 32\n\n#define NUM_TX_ANT_MASK 3\n#define NUM_RX_ANT_MASK 3\n\n// -------------sdrctl reg category-----------------\nenum sdrctl_reg_cat {\n  SDRCTL_REG_CAT_NO_USE = 0,\n  SDRCTL_REG_CAT_RF,\n  SDRCTL_REG_CAT_RX_INTF,\n  SDRCTL_REG_CAT_TX_INTF,\n  SDRCTL_REG_CAT_RX,\n  SDRCTL_REG_CAT_TX,\n  SDRCTL_REG_CAT_XPU,\n  SDRCTL_REG_CAT_DRV_RX,\n  SDRCTL_REG_CAT_DRV_TX,\n  SDRCTL_REG_CAT_DRV_XPU,\n};\n\n// ------------ software and RF reg definition ------------\n#define MAX_NUM_DRV_REG            8\n#define DRV_TX_REG_IDX_RATE        0\n#define DRV_TX_REG_IDX_RATE_HT     1\n#define DRV_TX_REG_IDX_RATE_VHT    2\n#define DRV_TX_REG_IDX_RATE_HE     3\n#define DRV_TX_REG_IDX_ANT_CFG     4\n#define DRV_TX_REG_IDX_PRINT_CFG   (MAX_NUM_DRV_REG-1)\n\n#define DRV_RX_REG_IDX_DEMOD_TH    0\n#define DRV_RX_REG_IDX_ANT_CFG     4\n#define DRV_RX_REG_IDX_PRINT_CFG   (MAX_NUM_DRV_REG-1)\n\n#define DRV_XPU_REG_IDX_LBT_TH     0\n#define DRV_XPU_REG_IDX_GIT_REV    (MAX_NUM_DRV_REG-1)\n\n#define MAX_NUM_RF_REG             8\n#define RF_TX_REG_IDX_ATT          0\n#define RF_TX_REG_IDX_FREQ_MHZ     1\n#define RF_RX_REG_IDX_GAIN         4\n#define RF_RX_REG_IDX_FREQ_MHZ     5\n// ------end of software and RF reg definition ------------\n\n// -------------dmesg printk control flag------------------\n#define DMESG_LOG_ERROR (1<<0)\n#define DMESG_LOG_UNICAST (1<<1)\n#define DMESG_LOG_BROADCAST (1<<2)\n#define DMESG_LOG_NORMAL_QUEUE_STOP (1<<3)\n#define DMESG_LOG_ANY (0xF)\n// ------end of dmesg printk control flag------------------\n\n#define MAX_NUM_VIF 4\n\n#define LEN_PHY_CRC 4\n#define LEN_MPDU_DELIM 4\n\n#define MAX_NUM_HW_QUEUE 4 // number of queue in FPGA\n#define MAX_NUM_SW_QUEUE 4 // number of queue in Linux, depends on the number we report by dev->queues in openwifi_dev_probe\n\n#define RING_ROOM_THRESHOLD (2+MAX_NUM_SW_QUEUE) // MAX_NUM_SW_QUEUE is for the room of MAX_NUM_SW_QUEUE last packets from MAX_NUM_SW_QUEUE queue before stop\n#define NUM_BIT_NUM_TX_BD 6\n#define NUM_TX_BD (1<<NUM_BIT_NUM_TX_BD) // !!! should align to the fifo size in tx_bit_intf.v\n\n#ifdef USE_NEW_RX_INTERRUPT\n#define NUM_RX_BD 64\n#else\n#define NUM_RX_BD 16\n#endif\n\n#define TX_BD_BUF_SIZE (8192)\n#define RX_BD_BUF_SIZE (2048)\n\n#define NUM_BIT_MAX_NUM_HW_QUEUE 2\n#define NUM_BIT_MAX_PHY_TX_SN 10 // decrease 12 to 10 to reserve 2 bits storing related linux prio idx\n#define MAX_PHY_TX_SN ((1<<NUM_BIT_MAX_PHY_TX_SN)-1)\n\n#define AD9361_RADIO_OFF_TX_ATT 89750 //please align with ad9361.c\n#define AD9361_RADIO_ON_TX_ATT 000    //please align with rf_init.sh\n#define AD9361_CTRL_OUT_EN_MASK (0xFF) \n#define AD9361_CTRL_OUT_INDEX_ANT0 (0x16) \n#define AD9361_CTRL_OUT_INDEX_ANT1 (0x17) \n\n#define SDR_SUPPORTED_FILTERS  \\\n  (FIF_ALLMULTI |        \\\n  FIF_BCN_PRBRESP_PROMISC |  \\\n  FIF_CONTROL |        \\\n  FIF_OTHER_BSS |        \\\n  FIF_PSPOLL |        \\\n  FIF_PROBE_REQ)\n\n#define HIGH_PRIORITY_DISCARD_FLAG ((~0x040)<<16) // don't force drop OTHER_BSS by high priority discard\n//#define HIGH_PRIORITY_DISCARD_FLAG ((~0x140)<<16) // don't force drop OTHER_BSS and PROB_REQ by high priority discard\n\n/* 5G chan 36 - chan 64*/\n#define SDR_5GHZ_CH36_64 REG_RULE(5150-10, 5350+10, 80, 0, 20, 0)\n/* 5G chan 32 - chan 173*/\n#define SDR_5GHZ_CH32_173 REG_RULE(5160-10, 5865+10, 80, 0, 20, 0)\n/* 5G chan 36 - chan 48*/\n#define SDR_5GHZ_CH36_48 REG_RULE(5150-10, 5270+10, 80, 0, 20, 0)\n\n/*\n *Only these channels all allow active\n *scan on all world regulatory domains\n */\n#define SDR_2GHZ_CH01_13  REG_RULE(2412-10, 2472+10, 40, 0, 20, NL80211_RRF_NO_CCK) // disable 11b\n#define SDR_2GHZ_CH01_14  REG_RULE(2412-10, 2484+10, 40, 0, 20, NL80211_RRF_NO_CCK) // disable 11b\n\n// regulatory.h alpha2\n//  *  00 - World regulatory domain\n//  *  99 - built by driver but a specific alpha2 cannot be determined\n//  *  98 - result of an intersection between two regulatory domains\n//  *  97 - regulatory domain has not yet been configured\nstatic const struct ieee80211_regdomain sdr_regd = { // for wiphy_apply_custom_regulatory\n  .n_reg_rules = 2,\n  .alpha2 = \"99\",\n  .dfs_region = NL80211_DFS_ETSI,\n  .reg_rules = {\n    //SDR_2GHZ_CH01_13,\n    //SDR_5GHZ_CH36_48, //Avoid radar!\n    SDR_2GHZ_CH01_14,\n    // SDR_5GHZ_CH36_64,\n    SDR_5GHZ_CH32_173,\n    }\n};\n\n#define CHAN2G(_channel, _freq, _flags) { \\\n  .band      = NL80211_BAND_2GHZ, \\\n  .hw_value    = (_channel), \\\n  .center_freq    = (_freq), \\\n  .flags      = (_flags), \\\n  .max_antenna_gain  = 0, \\\n  .max_power    = 0, \\\n}\n\n#define CHAN5G(_channel, _freq, _flags) { \\\n  .band      = NL80211_BAND_5GHZ, \\\n  .hw_value    = (_channel), \\\n  .center_freq    = (_freq), \\\n  .flags      = (_flags), \\\n  .max_antenna_gain  = 0, \\\n  .max_power    = 0, \\\n}\n\nstatic const struct ieee80211_rate openwifi_5GHz_rates[] = {\n  { .bitrate = 10,  .hw_value = 0,  .flags = 0},\n  { .bitrate = 20,  .hw_value = 1,  .flags = 0},\n  { .bitrate = 55,  .hw_value = 2,  .flags = 0},\n  { .bitrate = 110, .hw_value = 3,  .flags = 0},\n  { .bitrate = 60,  .hw_value = 4,  .flags = IEEE80211_RATE_MANDATORY_A},\n  { .bitrate = 90,  .hw_value = 5,  .flags = IEEE80211_RATE_MANDATORY_A},\n  { .bitrate = 120, .hw_value = 6,  .flags = IEEE80211_RATE_MANDATORY_A},\n  { .bitrate = 180, .hw_value = 7,  .flags = IEEE80211_RATE_MANDATORY_A},\n  { .bitrate = 240, .hw_value = 8,  .flags = IEEE80211_RATE_MANDATORY_A},\n  { .bitrate = 360, .hw_value = 9,  .flags = IEEE80211_RATE_MANDATORY_A},\n  { .bitrate = 480, .hw_value = 10, .flags = IEEE80211_RATE_MANDATORY_A},\n  { .bitrate = 540, .hw_value = 11, .flags = IEEE80211_RATE_MANDATORY_A},\n};\n\nstatic const struct ieee80211_rate openwifi_2GHz_rates[] = {\n  { .bitrate = 10,  .hw_value = 0,  .flags = 0},\n  { .bitrate = 20,  .hw_value = 1,  .flags = 0},\n  { .bitrate = 55,  .hw_value = 2,  .flags = 0},\n  { .bitrate = 110, .hw_value = 3,  .flags = 0},\n  { .bitrate = 60,  .hw_value = 4,  .flags = IEEE80211_RATE_MANDATORY_G|IEEE80211_RATE_ERP_G},\n  { .bitrate = 90,  .hw_value = 5,  .flags = IEEE80211_RATE_MANDATORY_G|IEEE80211_RATE_ERP_G},\n  { .bitrate = 120, .hw_value = 6,  .flags = IEEE80211_RATE_MANDATORY_G|IEEE80211_RATE_ERP_G},\n  { .bitrate = 180, .hw_value = 7,  .flags = IEEE80211_RATE_MANDATORY_G|IEEE80211_RATE_ERP_G},\n  { .bitrate = 240, .hw_value = 8,  .flags = IEEE80211_RATE_MANDATORY_G|IEEE80211_RATE_ERP_G},\n  { .bitrate = 360, .hw_value = 9,  .flags = IEEE80211_RATE_MANDATORY_G|IEEE80211_RATE_ERP_G},\n  { .bitrate = 480, .hw_value = 10, .flags = IEEE80211_RATE_MANDATORY_G|IEEE80211_RATE_ERP_G},\n  { .bitrate = 540, .hw_value = 11, .flags = IEEE80211_RATE_MANDATORY_G|IEEE80211_RATE_ERP_G},\n};\n\nstatic const struct ieee80211_channel openwifi_2GHz_channels[] = {\n  CHAN2G(1, 2412, 0),\n  CHAN2G(2, 2417, 0),\n  CHAN2G(3, 2422, 0),\n  CHAN2G(4, 2427, 0),\n  CHAN2G(5, 2432, 0),\n  CHAN2G(6, 2437, 0),\n  CHAN2G(7, 2442, 0),\n  CHAN2G(8, 2447, 0),\n  CHAN2G(9, 2452, 0),\n  CHAN2G(10, 2457, 0),\n  CHAN2G(11, 2462, 0),\n  CHAN2G(12, 2467, 0),\n  CHAN2G(13, 2472, 0),\n  // CHAN2G(14, 2484, 0),\n};\n\nstatic const struct ieee80211_channel openwifi_5GHz_channels[] = {\n  // CHAN5G(32, 5160, 0),\n  // CHAN5G(34, 5170, 0),\n  CHAN5G(36, 5180, 0),\n  CHAN5G(38, 5190, 0),\n  CHAN5G(40, 5200, 0),\n  CHAN5G(42, 5210, 0),\n  CHAN5G(44, 5220, 0),\n  CHAN5G(46, 5230, 0),\n  CHAN5G(48, 5240, 0),\n  // CHAN5G( 50, 5250, IEEE80211_CHAN_RADAR),\n  CHAN5G( 52, 5260, IEEE80211_CHAN_RADAR),\n  // CHAN5G( 54, 5270, IEEE80211_CHAN_RADAR),\n  CHAN5G( 56, 5280, IEEE80211_CHAN_RADAR),\n  // CHAN5G( 58, 5290, IEEE80211_CHAN_RADAR),\n  CHAN5G( 60, 5300, IEEE80211_CHAN_RADAR),\n  // CHAN5G( 62, 5310, IEEE80211_CHAN_RADAR),\n  CHAN5G( 64, 5320, IEEE80211_CHAN_RADAR),\n  // CHAN5G( 68, 5340, IEEE80211_CHAN_RADAR),\n  // CHAN5G( 96, 5480, IEEE80211_CHAN_RADAR),\n  // CHAN5G(100, 5500, IEEE80211_CHAN_RADAR),\n  // CHAN5G(102, 5510, IEEE80211_CHAN_RADAR),\n  // CHAN5G(104, 5520, IEEE80211_CHAN_RADAR),\n  // CHAN5G(106, 5530, IEEE80211_CHAN_RADAR),\n  // CHAN5G(108, 5540, IEEE80211_CHAN_RADAR),\n  // CHAN5G(110, 5550, IEEE80211_CHAN_RADAR),\n  // CHAN5G(112, 5560, IEEE80211_CHAN_RADAR),\n  // CHAN5G(114, 5570, IEEE80211_CHAN_RADAR),\n  // CHAN5G(116, 5580, IEEE80211_CHAN_RADAR),\n  // CHAN5G(118, 5590, IEEE80211_CHAN_RADAR),\n  // CHAN5G(120, 5600, IEEE80211_CHAN_RADAR),\n  // CHAN5G(122, 5610, IEEE80211_CHAN_RADAR),\n  // CHAN5G(124, 5620, IEEE80211_CHAN_RADAR),\n  // CHAN5G(126, 5630, IEEE80211_CHAN_RADAR),\n  // CHAN5G(128, 5640, IEEE80211_CHAN_RADAR),\n  // CHAN5G(132, 5660, IEEE80211_CHAN_RADAR),\n  // CHAN5G(134, 5670, IEEE80211_CHAN_RADAR),\n  // CHAN5G(136, 5680, IEEE80211_CHAN_RADAR),\n  // CHAN5G(138, 5690, IEEE80211_CHAN_RADAR),\n  // CHAN5G(140, 5700, IEEE80211_CHAN_RADAR),\n  // CHAN5G(142, 5710, IEEE80211_CHAN_RADAR),\n  // CHAN5G(144, 5720, IEEE80211_CHAN_RADAR),\n  // CHAN5G(149, 5745, IEEE80211_CHAN_RADAR),\n  // CHAN5G(151, 5755, IEEE80211_CHAN_RADAR),\n  // CHAN5G(153, 5765, IEEE80211_CHAN_RADAR),\n  // CHAN5G(155, 5775, IEEE80211_CHAN_RADAR),\n  // CHAN5G(157, 5785, IEEE80211_CHAN_RADAR),\n  // CHAN5G(159, 5795, IEEE80211_CHAN_RADAR),\n  // CHAN5G(161, 5805, IEEE80211_CHAN_RADAR),\n  // // CHAN5G(163, 5815, IEEE80211_CHAN_RADAR),\n  // CHAN5G(165, 5825, IEEE80211_CHAN_RADAR),\n  // CHAN5G(167, 5835, IEEE80211_CHAN_RADAR),\n  // CHAN5G(169, 5845, IEEE80211_CHAN_RADAR),\n  // CHAN5G(171, 5855, IEEE80211_CHAN_RADAR),\n  // CHAN5G(173, 5865, IEEE80211_CHAN_RADAR),\n};\n\nstatic const struct ieee80211_iface_limit openwifi_if_limits[] = {\n  { .max = MAX_NUM_VIF,  .types = BIT(NL80211_IFTYPE_STATION) },\n  { .max = MAX_NUM_VIF,  .types =\n#ifdef CONFIG_MAC80211_MESH\n                                  BIT(NL80211_IFTYPE_MESH_POINT) |\n#endif\n                                  BIT(NL80211_IFTYPE_AP)},\n};\n\nstatic const struct ieee80211_iface_combination openwifi_if_comb = {\n  .limits = openwifi_if_limits,\n  .n_limits = ARRAY_SIZE(openwifi_if_limits),\n  .max_interfaces = MAX_NUM_VIF,\n  .num_different_channels = 1,\n  .radar_detect_widths =  BIT(NL80211_CHAN_WIDTH_20_NOHT) |\n                          BIT(NL80211_CHAN_WIDTH_20) |\n                          BIT(NL80211_CHAN_WIDTH_40) |\n                          BIT(NL80211_CHAN_WIDTH_80),\n};\n\nstatic const u8  wifi_rate_table_mapping[24] =     { 0,  0,  0,   0,  0,  0,   0,   0,  10,   8,   6,   4,  11,   9,   7,  5,   0,    1,   2,   3,   4,   5,   6,   7};\nstatic const u16 wifi_rate_table[24] =             { 0,  0,  0,   0,  0,  0,   0,   0, 480, 240, 120,  60, 540, 360, 180, 90,  65,  130, 195, 260, 390, 520, 585, 650};\nstatic const u16 wifi_rate_all[20] =               {10, 20, 55, 110, 60, 90, 120, 180, 240, 360, 480, 540,  65, 130, 195, 260, 390, 520, 585, 650};\nstatic const u8  wifi_mcs_table_11b_force_up[16] = {11, 11, 11,  11, 11, 15,  10,  14,   9,  13,   8,  12,   0,   0,   0,  0};\nstatic const u16 wifi_n_dbps_table[16] =           {24, 24, 24,  24, 24, 36,  48,  72,  96, 144, 192, 216,   0,   0,   0,  0};\nstatic const u16 wifi_n_dbps_ht_table[16] =        {26, 26, 26,  26, 26, 52,  78, 104, 156, 208, 234, 260,   0,   0,   0,  0};\n// static const u8 wifi_mcs_table[8] =             {6,9,12,18,24,36,48,54};\n// static const u8 wifi_mcs_table_phy_tx[8]    =   {11,15,10,14,9,13,8,12};\n\n// ===== copy from adi-linux/drivers/iio/frequency/cf_axi_dds.c =====\nstruct cf_axi_dds_state {\n  struct device               *dev_spi;\n  struct clk                  *clk;\n  struct cf_axi_dds_chip_info  *chip_info;\n  struct gpio_desc            *plddrbypass_gpio;\n  struct gpio_desc            *interpolation_gpio;\n\n  bool                        standalone;\n  bool                        dp_disable;\n  bool                        enable;\n  bool                        pl_dma_fifo_en;\n  enum fifo_ctrl              gpio_dma_fifo_ctrl;\n\n  struct iio_info              iio_info;\n  size_t                      regs_size;\n  void __iomem                *regs;\n  void __iomem                *slave_regs;\n  void __iomem                *master_regs;\n  u64                          dac_clk;\n  unsigned int                ddr_dds_interp_en;\n  unsigned int                cached_freq[16];\n  unsigned int                version;\n  unsigned int                have_slave_channels;\n  unsigned int                interpolation_factor;\n  struct notifier_block       clk_nb;\n};\n// ===== end of copy from adi-linux/drivers/iio/frequency/cf_axi_dds.c =====\n\nstruct openwifi_stat {\n  u32 stat_enable;\n\n  u32 tx_prio_num[MAX_NUM_SW_QUEUE];\n  u32 tx_prio_interrupt_num[MAX_NUM_SW_QUEUE];\n  u32 tx_prio_stop0_fake_num[MAX_NUM_SW_QUEUE];\n  u32 tx_prio_stop0_real_num[MAX_NUM_SW_QUEUE];\n  u32 tx_prio_stop1_num[MAX_NUM_SW_QUEUE];\n  u32 tx_prio_wakeup_num[MAX_NUM_SW_QUEUE];\n\n  u32 tx_queue_num[MAX_NUM_HW_QUEUE];\n  u32 tx_queue_interrupt_num[MAX_NUM_HW_QUEUE];\n  u32 tx_queue_stop0_fake_num[MAX_NUM_HW_QUEUE];\n  u32 tx_queue_stop0_real_num[MAX_NUM_HW_QUEUE];\n  u32 tx_queue_stop1_num[MAX_NUM_HW_QUEUE];\n  u32 tx_queue_wakeup_num[MAX_NUM_HW_QUEUE];\n  \n  u32 tx_data_pkt_need_ack_num_total;\n  u32 tx_data_pkt_need_ack_num_total_fail;\n\n  u32 tx_data_pkt_need_ack_num_retx[6];\n  u32 tx_data_pkt_need_ack_num_retx_fail[6];\n\n  u32 tx_data_pkt_mcs_realtime;\n  u32 tx_data_pkt_fail_mcs_realtime;\n\n  u32 tx_mgmt_pkt_need_ack_num_total;\n  u32 tx_mgmt_pkt_need_ack_num_total_fail;\n  \n  u32 tx_mgmt_pkt_need_ack_num_retx[3];\n  u32 tx_mgmt_pkt_need_ack_num_retx_fail[3];\n\n  u32 tx_mgmt_pkt_mcs_realtime;\n  u32 tx_mgmt_pkt_fail_mcs_realtime;\n\n  u32 rx_target_sender_mac_addr;\n  u32 rx_data_ok_agc_gain_value_realtime;\n  u32 rx_data_fail_agc_gain_value_realtime;\n  u32 rx_mgmt_ok_agc_gain_value_realtime;\n  u32 rx_mgmt_fail_agc_gain_value_realtime;\n  u32 rx_ack_ok_agc_gain_value_realtime;\n\n  u32 rx_monitor_all;\n  u32 rx_data_pkt_num_total;\n  u32 rx_data_pkt_num_fail;\n  u32 rx_mgmt_pkt_num_total;\n  u32 rx_mgmt_pkt_num_fail;\n  u32 rx_ack_pkt_num_total;\n  u32 rx_ack_pkt_num_fail;\n\n  u32 rx_data_pkt_mcs_realtime;\n  u32 rx_data_pkt_fail_mcs_realtime;\n  u32 rx_mgmt_pkt_mcs_realtime;\n  u32 rx_mgmt_pkt_fail_mcs_realtime;\n  u32 rx_ack_pkt_mcs_realtime;\n\n  u32 restrict_freq_mhz;\n\n  u32 csma_cfg0;\n  u32 cw_max_min_cfg;\n\n  u32 dbg_ch0;\n  u32 dbg_ch1;\n  u32 dbg_ch2;\n};\n\n#define RX_DMA_CYCLIC_MODE\nstruct openwifi_priv {\n  struct platform_device       *pdev;\n  struct ieee80211_vif         *vif[MAX_NUM_VIF];\n\n  const struct openwifi_rf_ops *rf;\n  enum openwifi_hardware_type  hardware_type;\n  enum openwifi_fpga_type      fpga_type;\n\n  struct cf_axi_dds_state      *dds_st;  //axi_ad9361 hdl ref design module, dac channel\n  struct axiadc_state          *adc_st;      //axi_ad9361 hdl ref design module, adc channel\n  struct ad9361_rf_phy         *ad9361_phy; //ad9361 chip\n  struct ctrl_outs_control     ctrl_out;\n\n  int rx_freq_offset_to_lo_MHz;\n  int tx_freq_offset_to_lo_MHz;\n  u32 rf_bw;\n  u32 actual_rx_lo;\n  u32 actual_tx_lo;\n  u32 last_tx_quad_cal_lo;\n\n  struct ieee80211_rate           rates_2GHz[12];\n  struct ieee80211_rate           rates_5GHz[12];\n  struct ieee80211_channel        channels_2GHz[13];\n  struct ieee80211_channel        channels_5GHz[11];\n  struct ieee80211_supported_band band_2GHz;\n  struct ieee80211_supported_band band_5GHz;\n  bool rfkill_off;\n  u8   runtime_tx_ant_cfg;\n  u8   runtime_rx_ant_cfg;\n\n  int  rssi_correction; // dynamic RSSI correction according to current channel in _rf_set_channel()\n  \n  enum rx_intf_mode     rx_intf_cfg;\n  enum tx_intf_mode     tx_intf_cfg;\n  enum openofdm_rx_mode openofdm_rx_cfg;\n  enum openofdm_tx_mode openofdm_tx_cfg;\n  enum xpu_mode         xpu_cfg;\n\n  int irq_rx;\n  int irq_tx;\n\n  // u32 call_counter;\n  u8                             *rx_cyclic_buf;\n  dma_addr_t                     rx_cyclic_buf_dma_mapping_addr;\n  struct dma_chan                *rx_chan;\n  struct dma_async_tx_descriptor *rxd;\n  dma_cookie_t                   rx_cookie;\n\n  struct openwifi_ring           tx_ring[MAX_NUM_SW_QUEUE];\n  struct scatterlist             tx_sg;\n  struct dma_chan                *tx_chan;\n  struct dma_async_tx_descriptor *txd;\n  dma_cookie_t                   tx_cookie;\n  // struct completion tx_dma_complete;\n  // bool openwifi_tx_first_time_run;\n\n  // int phy_tx_sn;\n  u32 slice_idx;\n  u32 dest_mac_addr_queue_map[MAX_NUM_HW_QUEUE];\n  u8  mac_addr[ETH_ALEN];\n  u16 seqno;\n\n  bool use_short_slot;\n  u8   band;\n\n  u32 ampdu_reference;\n\n  u32 drv_rx_reg_val[MAX_NUM_DRV_REG];\n  u32 drv_tx_reg_val[MAX_NUM_DRV_REG];\n  u32 drv_xpu_reg_val[MAX_NUM_DRV_REG];\n  int rf_reg_val[MAX_NUM_RF_REG];\n  int last_auto_fpga_lbt_th;\n\n  struct bin_attribute bin_iq;\n  u32                  tx_intf_arbitrary_iq[512];\n  u16                  tx_intf_arbitrary_iq_num;\n  u8                   tx_intf_iq_ctl;\n\n  struct openwifi_stat stat;\n  // u8 num_led;\n  // struct led_classdev *led[MAX_NUM_LED];//zc706 has 4 user leds. please find openwifi_dev_probe to see how we get them.\n  // char led_name[MAX_NUM_LED][OPENWIFI_LED_MAX_NAME_LEN];\n\n  spinlock_t lock;\n};\n\n#endif /* OPENWIFI_SDR */\n"
  },
  {
    "path": "driver/sdrctl_intf.c",
    "content": "// Author: Xianjun Jiao, Michael Mehari, Wei Liu\n// SPDX-FileCopyrightText: 2019 UGent\n// SPDX-License-Identifier: AGPL-3.0-or-later\n\nstatic int openwifi_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, void *data, int len)\n{\n  static struct ieee80211_conf channel_conf_tmp;\n  static struct ieee80211_channel channel_tmp;\n  struct openwifi_priv *priv = hw->priv;\n  struct nlattr *tb[OPENWIFI_ATTR_MAX + 1];\n  struct sk_buff *skb;\n  int err;\n  u32 tmp=-1, reg_cat, reg_addr, reg_val, reg_addr_idx, tsft_high, tsft_low;\n  int tmp_int;\n\n  err = nla_parse(tb, OPENWIFI_ATTR_MAX, data, len, openwifi_testmode_policy, NULL);\n  if (err)\n    return err;\n\n  if (!tb[OPENWIFI_ATTR_CMD])\n    return -EINVAL;\n\n  channel_conf_tmp.chandef.chan = (&channel_tmp);\n\n  switch (nla_get_u32(tb[OPENWIFI_ATTR_CMD])) {\n  case OPENWIFI_CMD_SET_GAP:\n    if (!tb[OPENWIFI_ATTR_GAP])\n      return -EINVAL;\n    tmp = nla_get_u32(tb[OPENWIFI_ATTR_GAP]);\n    printk(\"%s XPU_REG_CSMA_CFG_write %08x (Check openwifi_conf_tx() in sdr.c to understand)\\n\", sdr_compatible_str, tmp);\n    xpu_api->XPU_REG_CSMA_CFG_write(tmp); // unit us\n    return 0;\n  case OPENWIFI_CMD_GET_GAP:\n    skb = (struct sk_buff *)cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));\n    if (!skb)\n      return -ENOMEM;\n    tmp = xpu_api->XPU_REG_CSMA_CFG_read();\n    if (nla_put_u32(skb, OPENWIFI_ATTR_GAP, tmp))\n      goto nla_put_failure;\n    return cfg80211_testmode_reply(skb);\n  case OPENWIFI_CMD_SET_SLICE_IDX:\n    if (!tb[OPENWIFI_ATTR_SLICE_IDX])\n      return -EINVAL;\n    tmp = nla_get_u32(tb[OPENWIFI_ATTR_SLICE_IDX]);\n    printk(\"%s set openwifi slice_idx in hex: %08x\\n\", sdr_compatible_str, tmp);\n    if (tmp == MAX_NUM_HW_QUEUE) {\n      printk(\"%s set openwifi slice_idx reset all queue counter.\\n\", sdr_compatible_str);\n      xpu_api->XPU_REG_MULTI_RST_write(1<<7); //bit7 reset the counter for all queues at the same time\n      xpu_api->XPU_REG_MULTI_RST_write(0<<7); \n    } else {\n      priv->slice_idx = tmp;\n    }\n    return 0;\n  case OPENWIFI_CMD_GET_SLICE_IDX:\n    skb = (struct sk_buff *)cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));\n    if (!skb)\n      return -ENOMEM;\n    tmp = priv->slice_idx;\n    if (nla_put_u32(skb, OPENWIFI_ATTR_SLICE_IDX, tmp))\n      goto nla_put_failure;\n    printk(\"%s get openwifi slice_idx in hex: %08x\\n\", sdr_compatible_str, tmp);\n    return cfg80211_testmode_reply(skb);\n  case OPENWIFI_CMD_SET_ADDR:\n    if (!tb[OPENWIFI_ATTR_ADDR])\n      return -EINVAL;\n    tmp = nla_get_u32(tb[OPENWIFI_ATTR_ADDR]);\n    if (priv->slice_idx>=MAX_NUM_HW_QUEUE) {\n      printk(\"%s set openwifi slice_target_mac_addr(low32) WARNING: current slice idx %d is invalid!\\n\", sdr_compatible_str, priv->slice_idx);\n      return -EOPNOTSUPP;\n    } else {\n      printk(\"%s set openwifi slice_target_mac_addr(low32) in hex: %08x to slice %d\\n\", sdr_compatible_str, tmp, priv->slice_idx);\n      priv->dest_mac_addr_queue_map[priv->slice_idx] = reverse32(tmp);\n    }\n    return 0;\n  case OPENWIFI_CMD_GET_ADDR:\n    skb = (struct sk_buff *)cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));\n    if (!skb)\n      return -ENOMEM;\n    if (priv->slice_idx>=MAX_NUM_HW_QUEUE) {\n      tmp = -1;\n    } else {\n      tmp = reverse32(priv->dest_mac_addr_queue_map[priv->slice_idx]);\n    }\n    if (nla_put_u32(skb, OPENWIFI_ATTR_ADDR, tmp))\n      goto nla_put_failure;\n    printk(\"%s get openwifi slice_target_mac_addr(low32) in hex: %08x of slice %d\\n\", sdr_compatible_str, tmp, priv->slice_idx);\n    return cfg80211_testmode_reply(skb);\n\n  case OPENWIFI_CMD_SET_SLICE_TOTAL:\n    if (!tb[OPENWIFI_ATTR_SLICE_TOTAL])\n      return -EINVAL;\n    tmp = nla_get_u32(tb[OPENWIFI_ATTR_SLICE_TOTAL]);\n    if (priv->slice_idx>=MAX_NUM_HW_QUEUE) {\n      printk(\"%s set SLICE_TOTAL(duration) WARNING: current slice idx %d is invalid!\\n\", sdr_compatible_str, priv->slice_idx);\n      return -EOPNOTSUPP;\n    } else {\n      printk(\"%s set SLICE_TOTAL(duration) %d usec to slice %d\\n\", sdr_compatible_str, tmp, priv->slice_idx);\n      xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((priv->slice_idx<<20)|tmp);\n    }\n    return 0;\n  case OPENWIFI_CMD_GET_SLICE_TOTAL:\n    skb = (struct sk_buff *)cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));\n    if (!skb)\n      return -ENOMEM;\n    tmp = (xpu_api->XPU_REG_SLICE_COUNT_TOTAL_read());\n    printk(\"%s get SLICE_TOTAL(duration) %d usec of slice %d\\n\", sdr_compatible_str, tmp&0xFFFFF, tmp>>20);\n    if (nla_put_u32(skb, OPENWIFI_ATTR_SLICE_TOTAL, tmp))\n      goto nla_put_failure;\n    return cfg80211_testmode_reply(skb);\n\n  case OPENWIFI_CMD_SET_SLICE_START:\n    if (!tb[OPENWIFI_ATTR_SLICE_START])\n      return -EINVAL;\n    tmp = nla_get_u32(tb[OPENWIFI_ATTR_SLICE_START]);\n    if (priv->slice_idx>=MAX_NUM_HW_QUEUE) {\n      printk(\"%s set SLICE_START(duration) WARNING: current slice idx %d is invalid!\\n\", sdr_compatible_str, priv->slice_idx);\n      return -EOPNOTSUPP;\n    } else {\n      printk(\"%s set SLICE_START(duration) %d usec to slice %d\\n\", sdr_compatible_str, tmp, priv->slice_idx);\n      xpu_api->XPU_REG_SLICE_COUNT_START_write((priv->slice_idx<<20)|tmp);\n    }\n    return 0;\n  case OPENWIFI_CMD_GET_SLICE_START:\n    skb = (struct sk_buff *)cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));\n    if (!skb)\n      return -ENOMEM;\n    tmp = (xpu_api->XPU_REG_SLICE_COUNT_START_read());\n    printk(\"%s get SLICE_START(duration) %d usec of slice %d\\n\", sdr_compatible_str, tmp&0xFFFFF, tmp>>20);\n    if (nla_put_u32(skb, OPENWIFI_ATTR_SLICE_START, tmp))\n      goto nla_put_failure;\n    return cfg80211_testmode_reply(skb);\n\n  case OPENWIFI_CMD_SET_SLICE_END:\n    if (!tb[OPENWIFI_ATTR_SLICE_END])\n      return -EINVAL;\n    tmp = nla_get_u32(tb[OPENWIFI_ATTR_SLICE_END]);\n    if (priv->slice_idx>=MAX_NUM_HW_QUEUE) {\n      printk(\"%s set SLICE_END(duration) WARNING: current slice idx %d is invalid!\\n\", sdr_compatible_str, priv->slice_idx);\n      return -EOPNOTSUPP;\n    } else {\n      printk(\"%s set SLICE_END(duration) %d usec to slice %d\\n\", sdr_compatible_str, tmp, priv->slice_idx);\n      xpu_api->XPU_REG_SLICE_COUNT_END_write((priv->slice_idx<<20)|tmp);\n    }\n    return 0;\n  case OPENWIFI_CMD_GET_SLICE_END:\n    skb = (struct sk_buff *)cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));\n    if (!skb)\n      return -ENOMEM;\n    tmp = (xpu_api->XPU_REG_SLICE_COUNT_END_read());\n    printk(\"%s get SLICE_END(duration) %d usec of slice %d\\n\", sdr_compatible_str, tmp&0xFFFFF, tmp>>20);\n    if (nla_put_u32(skb, OPENWIFI_ATTR_SLICE_END, tmp))\n      goto nla_put_failure;\n    return cfg80211_testmode_reply(skb);\n\n  // case OPENWIFI_CMD_SET_SLICE_TOTAL1:\n  //   if (!tb[OPENWIFI_ATTR_SLICE_TOTAL1])\n  //     return -EINVAL;\n  //   tmp = nla_get_u32(tb[OPENWIFI_ATTR_SLICE_TOTAL1]);\n  //   printk(\"%s set SLICE_TOTAL1(duration) to %d usec\\n\", sdr_compatible_str, tmp);\n  //   // xpu_api->XPU_REG_SLICE_COUNT_TOTAL1_write(tmp);\n  //   return 0;\n  // case OPENWIFI_CMD_GET_SLICE_TOTAL1:\n  //   skb = cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));\n  //   if (!skb)\n  //     return -ENOMEM;\n  //   // tmp = (xpu_api->XPU_REG_SLICE_COUNT_TOTAL1_read());\n  //   if (nla_put_u32(skb, OPENWIFI_ATTR_SLICE_TOTAL1, tmp))\n  //     goto nla_put_failure;\n  //   return cfg80211_testmode_reply(skb);\n\n  // case OPENWIFI_CMD_SET_SLICE_START1:\n  //   if (!tb[OPENWIFI_ATTR_SLICE_START1])\n  //     return -EINVAL;\n  //   tmp = nla_get_u32(tb[OPENWIFI_ATTR_SLICE_START1]);\n  //   printk(\"%s set SLICE_START1(duration) to %d usec\\n\", sdr_compatible_str, tmp);\n  //   // xpu_api->XPU_REG_SLICE_COUNT_START1_write(tmp);\n  //   return 0;\n  // case OPENWIFI_CMD_GET_SLICE_START1:\n  //   skb = cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));\n  //   if (!skb)\n  //     return -ENOMEM;\n  //   // tmp = (xpu_api->XPU_REG_SLICE_COUNT_START1_read());\n  //   if (nla_put_u32(skb, OPENWIFI_ATTR_SLICE_START1, tmp))\n  //     goto nla_put_failure;\n  //   return cfg80211_testmode_reply(skb);\n\n  // case OPENWIFI_CMD_SET_SLICE_END1:\n  //   if (!tb[OPENWIFI_ATTR_SLICE_END1])\n  //     return -EINVAL;\n  //   tmp = nla_get_u32(tb[OPENWIFI_ATTR_SLICE_END1]);\n  //   printk(\"%s set SLICE_END1(duration) to %d usec\\n\", sdr_compatible_str, tmp);\n  //   // xpu_api->XPU_REG_SLICE_COUNT_END1_write(tmp);\n  //   return 0;\n  // case OPENWIFI_CMD_GET_SLICE_END1:\n  //   skb = cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));\n  //   if (!skb)\n  //     return -ENOMEM;\n  //   // tmp = (xpu_api->XPU_REG_SLICE_COUNT_END1_read());\n  //   if (nla_put_u32(skb, OPENWIFI_ATTR_SLICE_END1, tmp))\n  //     goto nla_put_failure;\n  //   return cfg80211_testmode_reply(skb);\n\n  case OPENWIFI_CMD_SET_RSSI_TH:\n    if (!tb[OPENWIFI_ATTR_RSSI_TH])\n      return -EINVAL;\n    tmp = nla_get_u32(tb[OPENWIFI_ATTR_RSSI_TH]);\n    // printk(\"%s set RSSI_TH to %d\\n\", sdr_compatible_str, tmp);\n    // xpu_api->XPU_REG_LBT_TH_write(tmp);\n    // return 0;\n    printk(\"%s WARNING Please use command: sdrctl dev sdr0 set reg drv_xpu 0 reg_value! (1~2047, 0 means AUTO)!\\n\", sdr_compatible_str);\n    return -EOPNOTSUPP;\n  case OPENWIFI_CMD_GET_RSSI_TH:\n    skb = (struct sk_buff *)cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));\n    if (!skb)\n      return -ENOMEM;\n    tmp_int = rssi_half_db_to_rssi_dbm(xpu_api->XPU_REG_LBT_TH_read(), priv->rssi_correction); //rssi_dbm\n    tmp = (-tmp_int);\n    if (nla_put_u32(skb, OPENWIFI_ATTR_RSSI_TH, tmp))\n      goto nla_put_failure;\n    return cfg80211_testmode_reply(skb);\n\n  case OPENWIFI_CMD_SET_TSF:\n    printk(\"openwifi_set_tsf_1\");\n    if ( (!tb[OPENWIFI_ATTR_HIGH_TSF]) || (!tb[OPENWIFI_ATTR_LOW_TSF]) )\n        return -EINVAL;\n    printk(\"openwifi_set_tsf_2\");\n    tsft_high = nla_get_u32(tb[OPENWIFI_ATTR_HIGH_TSF]);\n    tsft_low  = nla_get_u32(tb[OPENWIFI_ATTR_LOW_TSF]);\n    xpu_api->XPU_REG_TSF_LOAD_VAL_write(tsft_high,tsft_low);\n    printk(\"%s openwifi_set_tsf: %08x%08x\\n\", sdr_compatible_str,tsft_high,tsft_low);\n    return 0;\n\n  case REG_CMD_SET:\n    if ( (!tb[REG_ATTR_ADDR]) || (!tb[REG_ATTR_VAL]) )\n      return -EINVAL;\n    reg_addr = nla_get_u32(tb[REG_ATTR_ADDR]);\n    reg_val  = nla_get_u32(tb[REG_ATTR_VAL]);\n    reg_cat = ((reg_addr>>16)&0xFFFF);\n    reg_addr = (reg_addr&0xFFFF);\n    reg_addr_idx = (reg_addr>>2);\n    printk(\"%s recv set cmd reg cat %d addr %08x val %08x idx %d\\n\", sdr_compatible_str, reg_cat, reg_addr, reg_val, reg_addr_idx);\n    if (reg_cat==SDRCTL_REG_CAT_RF) {\n      // printk(\"%s WARNING reg cat 1 (rf) is not supported yet!\\n\", sdr_compatible_str);\n      // return -EOPNOTSUPP;\n      if (reg_addr_idx>=0 && reg_addr_idx<MAX_NUM_RF_REG) {\n        priv->rf_reg_val[reg_addr_idx]=reg_val;\n        if (reg_addr_idx==RF_TX_REG_IDX_ATT) {//change the tx ON att (if a RF chain is ON)\n          tmp = ad9361_get_tx_atten(priv->ad9361_phy, 1);\n          printk(\"%s ad9361_get_tx_atten ant0 %d\\n\",sdr_compatible_str, tmp);\n          if (tmp<AD9361_RADIO_OFF_TX_ATT) {\n            err = ad9361_set_tx_atten(priv->ad9361_phy, AD9361_RADIO_ON_TX_ATT+reg_val, true, false, true);\n            if (err < 0) {\n              printk(\"%s WARNING ad9361_set_tx_atten ant0 %d FAIL!\\n\",sdr_compatible_str, AD9361_RADIO_ON_TX_ATT+reg_val);\n              return -EIO;\n            } else {\n              printk(\"%s ad9361_set_tx_atten ant0 %d OK\\n\",sdr_compatible_str, AD9361_RADIO_ON_TX_ATT+reg_val);\n            }\n          }\n          tmp = ad9361_get_tx_atten(priv->ad9361_phy, 2);\n          printk(\"%s ad9361_get_tx_atten ant1 %d\\n\",sdr_compatible_str, tmp);\n          if (tmp<AD9361_RADIO_OFF_TX_ATT) {\n            err = ad9361_set_tx_atten(priv->ad9361_phy, AD9361_RADIO_ON_TX_ATT+reg_val, false, true, true);\n            if (err < 0) {\n              printk(\"%s WARNING ad9361_set_tx_atten ant1 %d FAIL!\\n\",sdr_compatible_str, AD9361_RADIO_ON_TX_ATT+reg_val);\n              return -EIO;\n            } else {\n              printk(\"%s ad9361_set_tx_atten ant1 %d OK\\n\",sdr_compatible_str, AD9361_RADIO_ON_TX_ATT+reg_val);\n            }\n          }\n        } else if (reg_addr_idx==RF_TX_REG_IDX_FREQ_MHZ || reg_addr_idx==RF_RX_REG_IDX_FREQ_MHZ) { // apply the tx and rx fo\n          channel_conf_tmp.chandef.chan->center_freq = reg_val;\n          ad9361_rf_set_channel(hw, &channel_conf_tmp);\n          priv->stat.restrict_freq_mhz = reg_val;\n          // clk_set_rate(priv->ad9361_phy->clks[TX_RFPLL], ( ((u64)1000000ull)*((u64)priv->rf_reg_val[RF_TX_REG_IDX_FREQ_MHZ]) )>>1 );\n          // ad9361_tx_calibration(priv, priv->rf_reg_val[RF_TX_REG_IDX_FREQ_MHZ]);\n          // printk(\"%s clk_set_rate TX_RFPLL %dMHz done\\n\",sdr_compatible_str, priv->rf_reg_val[RF_TX_REG_IDX_FREQ_MHZ]);\n        } \n        // else if (reg_addr_idx==RF_RX_REG_IDX_FREQ_MHZ) { // apply the rx fo\n        //   channel_conf_tmp.chandef.chan->center_freq = reg_val;\n        //   ad9361_rf_set_channel(hw, &channel_conf_tmp);\n        //   // clk_set_rate(priv->ad9361_phy->clks[RX_RFPLL], ( ((u64)1000000ull)*((u64)priv->rf_reg_val[RF_RX_REG_IDX_FREQ_MHZ]) )>>1 );\n        //   // openwifi_rf_rx_update_after_tuning(priv, priv->rf_reg_val[RF_RX_REG_IDX_FREQ_MHZ]);\n        //   // printk(\"%s clk_set_rate RX_RFPLL %dMHz done\\n\",sdr_compatible_str, priv->rf_reg_val[RF_RX_REG_IDX_FREQ_MHZ]);\n        // }\n      } else {\n        printk(\"%s WARNING reg_addr_idx %d is out of range!\\n\", sdr_compatible_str, reg_addr_idx);\n        return -EOPNOTSUPP;\n      }\n    }\n    else if (reg_cat==SDRCTL_REG_CAT_RX_INTF)\n      rx_intf_api->reg_write(reg_addr,reg_val);\n    else if (reg_cat==SDRCTL_REG_CAT_TX_INTF)\n      tx_intf_api->reg_write(reg_addr,reg_val);\n    else if (reg_cat==SDRCTL_REG_CAT_RX)\n      openofdm_rx_api->reg_write(reg_addr,reg_val);\n    else if (reg_cat==SDRCTL_REG_CAT_TX)\n      openofdm_tx_api->reg_write(reg_addr,reg_val);\n    else if (reg_cat==SDRCTL_REG_CAT_XPU)\n      xpu_api->reg_write(reg_addr,reg_val);\n    else if (reg_cat==SDRCTL_REG_CAT_DRV_RX) {\n      if (reg_addr_idx>=0 && reg_addr_idx<MAX_NUM_DRV_REG) {\n        if (reg_addr_idx==DRV_RX_REG_IDX_ANT_CFG) {\n          tmp = openwifi_set_antenna(hw, (priv->drv_tx_reg_val[reg_addr_idx]==0?1:2), (reg_val==0?1:2));\n          if (tmp) {\n            printk(\"%s WARNING openwifi_set_antenna return %d!\\n\", sdr_compatible_str, tmp);\n            return -EIO;\n          } else {\n            priv->drv_rx_reg_val[reg_addr_idx]=reg_val;\n          }\n        } else {\n          priv->drv_rx_reg_val[reg_addr_idx]=reg_val;\n          if (reg_addr_idx==DRV_RX_REG_IDX_DEMOD_TH) {\n            openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write((OPENOFDM_RX_DC_RUNNING_SUM_TH_INIT<<16)|rssi_dbm_to_rssi_half_db((reg_val==0?OPENOFDM_RX_RSSI_DBM_TH_DEFAULT:(-reg_val)), priv->rssi_correction));\n          }\n        }\n      } else {\n        printk(\"%s WARNING reg_addr_idx %d is out of range!\\n\", sdr_compatible_str, reg_addr_idx);\n        return -EOPNOTSUPP;\n      }\n    }\n    else if (reg_cat==SDRCTL_REG_CAT_DRV_TX) {\n      if (reg_addr_idx>=0 && reg_addr_idx<MAX_NUM_DRV_REG) {\n        if ((reg_addr_idx == DRV_TX_REG_IDX_RATE || reg_addr_idx == DRV_TX_REG_IDX_RATE_HT) &&\n            (reg_val != 0 && (!((reg_val&0xF)>=4 && (reg_val&0xF)<=11)) ) ) {\n          printk(\"%s WARNING rate override value should be 0 or 4~11!\\n\", sdr_compatible_str);\n          return -EOPNOTSUPP;\n        } else {\n          if (reg_addr_idx==DRV_TX_REG_IDX_ANT_CFG) {\n            tmp = openwifi_set_antenna(hw, reg_val+1, priv->drv_rx_reg_val[reg_addr_idx]+1);\n            if (tmp) {\n              printk(\"%s WARNING openwifi_set_antenna return %d!\\n\", sdr_compatible_str, tmp);\n              return -EIO;\n            } else {\n              priv->drv_tx_reg_val[reg_addr_idx]=reg_val;\n            }\n          } else {\n            priv->drv_tx_reg_val[reg_addr_idx]=reg_val;\n          }\n        }\n      } else {\n        printk(\"%s WARNING reg_addr_idx %d is out of range!\\n\", sdr_compatible_str, reg_addr_idx);\n        return -EOPNOTSUPP;\n      }\n    }\n    else if (reg_cat==SDRCTL_REG_CAT_DRV_XPU) {\n      if (reg_addr_idx>=0 && reg_addr_idx<MAX_NUM_DRV_REG) {\n        priv->drv_xpu_reg_val[reg_addr_idx]=reg_val;\n        if (reg_addr_idx==DRV_XPU_REG_IDX_LBT_TH) {\n          if (reg_val) {\n            tmp_int = (-reg_val); // rssi_dbm\n            tmp = rssi_dbm_to_rssi_half_db(tmp_int, priv->rssi_correction);\n            xpu_api->XPU_REG_LBT_TH_write( tmp );\n            printk(\"%s override FPGA LBT threshold to %d(%ddBm). The last_auto_fpga_lbt_th %d(%ddBm). rssi corr %d (%d/%dMHz)\\n\", sdr_compatible_str, tmp, tmp_int, priv->last_auto_fpga_lbt_th, rssi_half_db_to_rssi_dbm(priv->last_auto_fpga_lbt_th, priv->rssi_correction), priv->rssi_correction, priv->actual_tx_lo, priv->actual_rx_lo);\n          } else {\n            xpu_api->XPU_REG_LBT_TH_write(priv->last_auto_fpga_lbt_th);\n            printk(\"%s Restore last_auto_fpga_lbt_th %d(%ddBm) to FPGA. ad9361_rf_set_channel will take control. rssi corr %d (%d/%dMHz)\\n\", sdr_compatible_str, priv->last_auto_fpga_lbt_th, rssi_half_db_to_rssi_dbm(priv->last_auto_fpga_lbt_th, priv->rssi_correction), priv->rssi_correction, priv->actual_tx_lo, priv->actual_rx_lo);\n          }\n        }\n      } else {\n        printk(\"%s WARNING reg_addr_idx %d is out of range!\\n\", sdr_compatible_str, reg_addr_idx);\n        return -EOPNOTSUPP;\n      }\n    }\n    else {\n      printk(\"%s WARNING reg cat %d is not supported yet!\\n\", sdr_compatible_str, reg_cat);\n      return -EOPNOTSUPP;\n    }\n    \n    return 0;\n  case REG_CMD_GET:\n    skb = (struct sk_buff *)cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));\n    if (!skb)\n      return -ENOMEM;\n    reg_addr = nla_get_u32(tb[REG_ATTR_ADDR]);\n    reg_cat = ((reg_addr>>16)&0xFFFF);\n    reg_addr = (reg_addr&0xFFFF);\n    reg_addr_idx = (reg_addr>>2);\n    printk(\"%s recv get cmd reg cat %d addr %08x idx %d\\n\", sdr_compatible_str, reg_cat, reg_addr, reg_addr_idx);\n    if (reg_cat==SDRCTL_REG_CAT_RF) {\n      // printk(\"%s WARNING reg cat 1 (rf) is not supported yet!\\n\", sdr_compatible_str);\n      // tmp = 0xFFFFFFFF;\n      // return -EOPNOTSUPP;\n      if (reg_addr_idx>=0 && reg_addr_idx<MAX_NUM_RF_REG) {\n        tmp = priv->rf_reg_val[reg_addr_idx];\n      } else {\n        printk(\"%s WARNING reg_addr_idx %d is out of range!\\n\", sdr_compatible_str, reg_addr_idx);\n        return -EOPNOTSUPP;\n      }\n    }\n    else if (reg_cat==SDRCTL_REG_CAT_RX_INTF)\n      tmp = rx_intf_api->reg_read(reg_addr);\n    else if (reg_cat==SDRCTL_REG_CAT_TX_INTF)\n      tmp = tx_intf_api->reg_read(reg_addr);\n    else if (reg_cat==SDRCTL_REG_CAT_RX)\n      tmp = openofdm_rx_api->reg_read(reg_addr);\n    else if (reg_cat==SDRCTL_REG_CAT_TX)\n      tmp = openofdm_tx_api->reg_read(reg_addr);\n    else if (reg_cat==SDRCTL_REG_CAT_XPU)\n      tmp = xpu_api->reg_read(reg_addr);\n    else if (reg_cat==SDRCTL_REG_CAT_DRV_RX) {\n      if (reg_addr_idx>=0 && reg_addr_idx<MAX_NUM_DRV_REG) {\n        tmp = priv->drv_rx_reg_val[reg_addr_idx];\n        if (reg_addr_idx==DRV_RX_REG_IDX_ANT_CFG)\n          openwifi_get_antenna(hw, &tsft_high, &tsft_low);\n      } else {\n        printk(\"%s WARNING reg_addr_idx %d is out of range!\\n\", sdr_compatible_str, reg_addr_idx);\n        return -EOPNOTSUPP;\n      }\n    }\n    else if (reg_cat==SDRCTL_REG_CAT_DRV_TX) {\n      if (reg_addr_idx>=0 && reg_addr_idx<MAX_NUM_DRV_REG) {\n        tmp = priv->drv_tx_reg_val[reg_addr_idx];\n        if (reg_addr_idx==DRV_TX_REG_IDX_ANT_CFG)\n          openwifi_get_antenna(hw, &tsft_high, &tsft_low);\n      } else {\n        printk(\"%s WARNING reg_addr_idx %d is out of range!\\n\", sdr_compatible_str, reg_addr_idx);\n        return -EOPNOTSUPP;\n      }\n    }\n    else if (reg_cat==SDRCTL_REG_CAT_DRV_XPU) {\n      if (reg_addr_idx>=0 && reg_addr_idx<MAX_NUM_DRV_REG) {\n        if (reg_addr_idx==DRV_XPU_REG_IDX_LBT_TH) {\n          tmp = xpu_api->XPU_REG_LBT_TH_read();//rssi_half_db\n          tmp_int = rssi_half_db_to_rssi_dbm(tmp, priv->rssi_correction); //rssi_dbm\n          printk(\"%s FPGA LBT threshold %d(%ddBm). The last_auto_fpga_lbt_th %d(%ddBm). rssi corr %d (%d/%dMHz)\\n\", sdr_compatible_str, tmp, tmp_int, priv->last_auto_fpga_lbt_th, rssi_half_db_to_rssi_dbm(priv->last_auto_fpga_lbt_th, priv->rssi_correction), priv->rssi_correction, priv->actual_tx_lo, priv->actual_rx_lo);\n        }\n        tmp = priv->drv_xpu_reg_val[reg_addr_idx];\n      } else {\n        printk(\"%s WARNING reg_addr_idx %d is out of range!\\n\", sdr_compatible_str, reg_addr_idx);\n        return -EOPNOTSUPP;\n      }\n    }\n    else {\n      printk(\"%s WARNING reg cat %d is not supported yet!\\n\", sdr_compatible_str, reg_cat);\n      return -EOPNOTSUPP;\n    }\n\n    if (nla_put_u32(skb, REG_ATTR_VAL, tmp))\n      goto nla_put_failure;\n    return cfg80211_testmode_reply(skb);\n\n  default:\n    return -EOPNOTSUPP;\n  }\n\n nla_put_failure:\n  dev_kfree_skb(skb);\n  return -ENOBUFS;\n}\n"
  },
  {
    "path": "driver/side_ch/Makefile",
    "content": "# by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be\n\nobj-m += side_ch.o\n# obj-m += axidmatest.o\n\nall:\n\tmake -C $(KDIR) M=$(PWD) modules\n\t# ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-\n\nclean:\n\trm -f *.ko *.o *.mod.o *.mod.c *.symvers *.order\n"
  },
  {
    "path": "driver/side_ch/make_driver.sh",
    "content": "#!/bin/bash\n\n# Author: Xianjun Jiao, Wei Liu\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\nif [ \"$#\" -ne 2 ]; then\n    echo \"You must enter exactly 2 arguments: \\$XILINX_DIR ARCH_BIT(32 or 64)\"\n    exit 1\nfi\n\nOPENWIFI_DIR=$(pwd)/../../\nXILINX_DIR=$1\nARCH_OPTION=$2\n\nif [ -f \"$OPENWIFI_DIR/LICENSE\" ]; then\n    echo \"\\$OPENWIFI_DIR is found!\"\nelse\n    echo \"\\$OPENWIFI_DIR is not correct. Please check!\"\n    exit 1\nfi\n\nif [ -d \"$XILINX_DIR/Vitis\" ]; then\n    echo \"\\$XILINX_DIR is found!\"\nelse\n    echo \"\\$XILINX_DIR is not correct. Please check!\"\n    exit 1\nfi\n\nif [ \"$ARCH_OPTION\" != \"32\" ] && [ \"$ARCH_OPTION\" != \"64\" ]; then\n    echo \"\\$ARCH_OPTION is not correct. Should be 32 or 64. Please check!\"\n    exit 1\nelse\n    echo \"\\$ARCH_OPTION is valid!\"\nfi\n\nXILINX_ENV_FILE=$XILINX_DIR/Vitis/2022.2/settings64.sh\necho \"Expect env file $XILINX_ENV_FILE\"\n\nsource $XILINX_ENV_FILE\nif [ \"$ARCH_OPTION\" == \"64\" ]; then\n    LINUX_KERNEL_SRC_DIR=$OPENWIFI_DIR/adi-linux-64/\n    ARCH=\"arm64\"\n    CROSS_COMPILE=\"aarch64-linux-gnu-\"\nelse\n    LINUX_KERNEL_SRC_DIR=$OPENWIFI_DIR/adi-linux/\n    ARCH=\"arm\"\n    CROSS_COMPILE=\"arm-linux-gnueabihf-\"\nfi\n\n# check if user entered the right path to analog device linux\nif [ -d \"$LINUX_KERNEL_SRC_DIR\" ]; then\n    echo \" setup linux kernel path ${LINUX_KERNEL_SRC_DIR}\"\nelse\n    echo \"Error: path to adi linux: ${LINUX_KERNEL_SRC_DIR} not found. Can not continue.\"\n    exit 1\nfi\n\nset -x\n\nhome_dir=$(pwd)\n\ncd $OPENWIFI_DIR/driver/side_ch\nmake KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE\n\ncd $home_dir\n"
  },
  {
    "path": "driver/side_ch/side_ch.c",
    "content": "/*\n * openwifi side channel driver\n * Author: Xianjun Jiao\n * SPDX-FileCopyrightText: 2019 UGent\n * SPDX-License-Identifier: AGPL-3.0-or-later\n*/\n\n#include <linux/bitops.h>\n#include <linux/dmapool.h>\n#include <linux/dma/xilinx_dma.h>\n#include <linux/init.h>\n#include <linux/interrupt.h>\n#include <linux/io.h>\n#include <linux/iopoll.h>\n#include <linux/module.h>\n#include <linux/of_address.h>\n#include <linux/of_dma.h>\n#include <linux/of_platform.h>\n#include <linux/of_irq.h>\n#include <linux/slab.h>\n#include <linux/clk.h>\n#include <linux/io-64-nonatomic-lo-hi.h>\n#include <linux/delay.h>\n#include <linux/dmaengine.h>\n\n#include <net/sock.h>\n#include <linux/netlink.h>\n#include <linux/skbuff.h>\n\n#include \"side_ch.h\"\n\nstatic int num_eq_init = 8; // should be 0~8\nstatic int iq_len_init = 0; //if iq_len>0, iq capture enabled, csi disabled\n\nmodule_param(num_eq_init, int, 0);\nMODULE_PARM_DESC(num_eq_init, \"num_eq_init. 0~8. number of equalizer output (52 each) appended to CSI\");\n\nmodule_param(iq_len_init, int, 0);\nMODULE_PARM_DESC(iq_len_init, \"iq_len_init. if iq_len_init>0, iq capture enabled, csi disabled\");\n\nstatic void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design\n\nstruct dma_chan *chan_to_pl = NULL;\nstruct dma_chan *chan_to_ps = NULL;\nu8 *side_info_buf = NULL;\ndma_cookie_t chan_to_ps_cookie;\nconst int max_side_info_buf_size = MAX_NUM_DMA_SYMBOL*8;\n\n/* IO accessors */\nstatic inline u32 reg_read(u32 reg)\n{\n\treturn ioread32(base_addr + reg);\n}\n\nstatic inline void reg_write(u32 reg, u32 value)\n{\n\tiowrite32(value, base_addr + reg);\n}\n\nstatic inline void SIDE_CH_REG_MULTI_RST_write(u32 Data) {\n\treg_write(SIDE_CH_REG_MULTI_RST_ADDR, Data);\n}\n\nstatic inline u32 SIDE_CH_REG_CONFIG_read(void){\n\treturn reg_read(SIDE_CH_REG_CONFIG_ADDR);\n}\n\nstatic inline void SIDE_CH_REG_CONFIG_write(u32 value){\n\treg_write(SIDE_CH_REG_CONFIG_ADDR, value);\n}\n\nstatic inline u32 SIDE_CH_REG_NUM_DMA_SYMBOL_read(void){\n\treturn reg_read(SIDE_CH_REG_NUM_DMA_SYMBOL_ADDR);\n}\n\nstatic inline void SIDE_CH_REG_NUM_DMA_SYMBOL_write(u32 value){\n\treg_write(SIDE_CH_REG_NUM_DMA_SYMBOL_ADDR, value);\n}\n\nstatic inline u32 SIDE_CH_REG_IQ_CAPTURE_read(void){\n\treturn reg_read(SIDE_CH_REG_IQ_CAPTURE_ADDR);\n}\n\nstatic inline void SIDE_CH_REG_IQ_CAPTURE_write(u32 value){\n\treg_write(SIDE_CH_REG_IQ_CAPTURE_ADDR, value);\n}\n\nstatic inline u32 SIDE_CH_REG_NUM_EQ_read(void){\n\treturn reg_read(SIDE_CH_REG_NUM_EQ_ADDR);\n}\n\nstatic inline void SIDE_CH_REG_NUM_EQ_write(u32 value){\n\treg_write(SIDE_CH_REG_NUM_EQ_ADDR, value);\n}\n\nstatic inline u32 SIDE_CH_REG_FC_TARGET_read(void){\n\treturn reg_read(SIDE_CH_REG_FC_TARGET_ADDR);\n}\n\nstatic inline void SIDE_CH_REG_FC_TARGET_write(u32 value){\n\treg_write(SIDE_CH_REG_FC_TARGET_ADDR, value);\n}\n\nstatic inline u32 SIDE_CH_REG_ADDR1_TARGET_read(void){\n\treturn reg_read(SIDE_CH_REG_ADDR1_TARGET_ADDR);\n}\n\nstatic inline void SIDE_CH_REG_ADDR1_TARGET_write(u32 value){\n\treg_write(SIDE_CH_REG_ADDR1_TARGET_ADDR, value);\n}\n\nstatic inline u32 SIDE_CH_REG_ADDR2_TARGET_read(void){\n\treturn reg_read(SIDE_CH_REG_ADDR2_TARGET_ADDR);\n}\n\nstatic inline void SIDE_CH_REG_ADDR2_TARGET_write(u32 value){\n\treg_write(SIDE_CH_REG_ADDR2_TARGET_ADDR, value);\n}\n\nstatic inline u32 SIDE_CH_REG_IQ_TRIGGER_read(void){\n\treturn reg_read(SIDE_CH_REG_IQ_TRIGGER_ADDR);\n}\n\nstatic inline void SIDE_CH_REG_IQ_TRIGGER_write(u32 value){\n\treg_write(SIDE_CH_REG_IQ_TRIGGER_ADDR, value);\n}\n\nstatic inline u32 SIDE_CH_REG_RSSI_TH_read(void){\n\treturn reg_read(SIDE_CH_REG_RSSI_TH_ADDR);\n}\n\nstatic inline void SIDE_CH_REG_RSSI_TH_write(u32 value){\n\treg_write(SIDE_CH_REG_RSSI_TH_ADDR, value);\n}\n\nstatic inline u32 SIDE_CH_REG_GAIN_TH_read(void){\n\treturn reg_read(SIDE_CH_REG_GAIN_TH_ADDR);\n}\n\nstatic inline void SIDE_CH_REG_GAIN_TH_write(u32 value){\n\treg_write(SIDE_CH_REG_GAIN_TH_ADDR, value);\n}\n\nstatic inline u32 SIDE_CH_REG_PRE_TRIGGER_LEN_read(void){\n\treturn reg_read(SIDE_CH_REG_PRE_TRIGGER_LEN_ADDR);\n}\n\nstatic inline void SIDE_CH_REG_PRE_TRIGGER_LEN_write(u32 value){\n\treg_write(SIDE_CH_REG_PRE_TRIGGER_LEN_ADDR, value);\n}\n\nstatic inline u32 SIDE_CH_REG_IQ_LEN_read(void){\n\treturn reg_read(SIDE_CH_REG_IQ_LEN_ADDR);\n}\n\nstatic inline void SIDE_CH_REG_IQ_LEN_write(u32 value){\n\treg_write(SIDE_CH_REG_IQ_LEN_ADDR, value);\n}\n\nstatic inline u32 SIDE_CH_REG_M_AXIS_DATA_COUNT_read(void){\n\treturn reg_read(SIDE_CH_REG_M_AXIS_DATA_COUNT_ADDR);\n}\n\nstatic inline void SIDE_CH_REG_M_AXIS_DATA_COUNT_write(u32 value){\n\treg_write(SIDE_CH_REG_M_AXIS_DATA_COUNT_ADDR, value);\n}\n\nstatic const struct of_device_id dev_of_ids[] = {\n\t{ .compatible = \"sdr,side_ch\", },\n\t{}\n};\nMODULE_DEVICE_TABLE(of, dev_of_ids);\n\nstatic void chan_to_ps_callback(void *completion)\n{\n\tcomplete(completion);\n}\n\n#if 0\nstatic void chan_to_pl_callback(void *completion)\n{\n\tcomplete(completion);\n}\n\nstatic int dma_loopback_test(int num_test, int num_dma_symbol) {\n\tint i, err = 0;\n\n\t// -----------dma loop back test-------------------------\n\tenum dma_status status;\n\tenum dma_ctrl_flags flags;\n\tu8 *src_buf, *dst_buf;\n\t// int num_dma_symbol = 16;\n\tint test_buf_size = num_dma_symbol*8;\n\tdma_addr_t src_buf_dma;\n\tdma_addr_t dst_buf_dma;\n\tstruct dma_device *chan_to_pl_dev = chan_to_pl->device;\n\tstruct dma_device *chan_to_ps_dev = chan_to_ps->device;\n\tstruct scatterlist chan_to_pl_sg[1];\n\tstruct scatterlist chan_to_ps_sg[1];\n\tdma_cookie_t chan_to_pl_cookie;\n\tdma_cookie_t chan_to_ps_cookie;\n\tstruct completion chan_to_pl_cmp;\n\tstruct completion chan_to_ps_cmp;\n\tstruct dma_async_tx_descriptor *chan_to_pl_d = NULL;\n\tstruct dma_async_tx_descriptor *chan_to_ps_d = NULL;\n\tunsigned long chan_to_ps_tmo =\tmsecs_to_jiffies(300000);\n\tunsigned long chan_to_pl_tmo =  msecs_to_jiffies(30000);\n\tint test_idx;\n\n\tfor (test_idx=0; test_idx<num_test; test_idx++) {\n\t\tprintk(\"%s test_idx %d\\n\", side_ch_compatible_str, test_idx);\n\t\t//set number of dma symbols expected to pl and ps\n\t\tSIDE_CH_REG_NUM_DMA_SYMBOL_write((num_dma_symbol<<16)|num_dma_symbol);\n\n\t\tsrc_buf = kmalloc(test_buf_size, GFP_KERNEL);\n\t\tif (!src_buf)\n\t\t\tgoto err_src_buf;\n\t\t\n\t\tdst_buf = kmalloc(test_buf_size, GFP_KERNEL);\n\t\tif (!dst_buf)\n\t\t\tgoto err_dst_buf;\n\n\t\t// test buf init\n\t\tfor (i=0; i<test_buf_size; i++) {\n\t\t\tsrc_buf[i] = (test_idx+test_buf_size-i-1);\n\t\t\tdst_buf[i] = 0;\n\t\t}\n\n\t\tset_user_nice(current, 10);\n\t\tflags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;\n\n\t\tsrc_buf_dma = dma_map_single(chan_to_pl_dev->dev, src_buf, test_buf_size, DMA_MEM_TO_DEV);\n\t\tif (dma_mapping_error(chan_to_pl_dev->dev, src_buf_dma)) {\n\t\t\tprintk(\"%s dma_loopback_test WARNING chan_to_pl_dev DMA mapping error\\n\", side_ch_compatible_str);\n\t\t\tgoto err_src_buf_dma_mapping;\n\t\t}\n\n\t\tdst_buf_dma = dma_map_single(chan_to_ps_dev->dev, dst_buf, test_buf_size, DMA_DEV_TO_MEM);\n\t\tif (dma_mapping_error(chan_to_ps_dev->dev, dst_buf_dma)) {\n\t\t\tprintk(\"%s dma_loopback_test WARNING chan_to_ps_dev DMA mapping error\\n\", side_ch_compatible_str);\n\t\t\tgoto err_dst_buf_dma_mapping;\n\t\t}\n\n\t\tsg_init_table(chan_to_ps_sg, 1);\n\t\tsg_init_table(chan_to_pl_sg, 1);\n\n\t\tsg_dma_address(&chan_to_ps_sg[0]) = dst_buf_dma;\n\t\tsg_dma_address(&chan_to_pl_sg[0]) = src_buf_dma;\n\n\t\tsg_dma_len(&chan_to_ps_sg[0]) = test_buf_size;\n\t\tsg_dma_len(&chan_to_pl_sg[0]) = test_buf_size;\n\n\t\tchan_to_ps_d = chan_to_ps_dev->device_prep_slave_sg(chan_to_ps, chan_to_ps_sg, 1, DMA_DEV_TO_MEM, flags, NULL);\n\t\tchan_to_pl_d = chan_to_pl_dev->device_prep_slave_sg(chan_to_pl, chan_to_pl_sg, 1, DMA_MEM_TO_DEV, flags, NULL);\n\n\t\tif (!chan_to_ps_d || !chan_to_pl_d) {\n\t\t\tprintk(\"%s dma_loopback_test WARNING !chan_to_ps_d || !chan_to_pl_d\\n\", side_ch_compatible_str);\n\t\t\tgoto err_dst_buf_with_unmap;\n\t\t}\n\n\t\tinit_completion(&chan_to_pl_cmp);\n\t\tchan_to_pl_d->callback = chan_to_pl_callback;\n\t\tchan_to_pl_d->callback_param = &chan_to_pl_cmp;\n\t\tchan_to_pl_cookie = chan_to_pl_d->tx_submit(chan_to_pl_d);\n\n\t\tinit_completion(&chan_to_ps_cmp);\n\t\tchan_to_ps_d->callback = chan_to_ps_callback;\n\t\tchan_to_ps_d->callback_param = &chan_to_ps_cmp;\n\t\tchan_to_ps_cookie = chan_to_ps_d->tx_submit(chan_to_ps_d);\n\n\t\tif (dma_submit_error(chan_to_pl_cookie) ||\tdma_submit_error(chan_to_ps_cookie)) {\n\t\t\tprintk(\"%s dma_loopback_test WARNING dma_submit_error\\n\", side_ch_compatible_str);\n\t\t\tgoto err_dst_buf_with_unmap;\n\t\t}\n\n\t\tdma_async_issue_pending(chan_to_pl);\n\t\tdma_async_issue_pending(chan_to_ps);\n\n\t\tchan_to_pl_tmo = wait_for_completion_timeout(&chan_to_pl_cmp, chan_to_pl_tmo);\n\n\t\tstatus = dma_async_is_tx_complete(chan_to_pl, chan_to_pl_cookie, NULL, NULL);\n\t\tif (chan_to_pl_tmo == 0) {\n\t\t\tprintk(\"%s dma_loopback_test chan_to_pl_tmo == 0\\n\", side_ch_compatible_str);\n\t\t\tgoto err_dst_buf_with_unmap;\n\t\t} else if (status != DMA_COMPLETE) {\n\t\t\tprintk(\"%s dma_loopback_test chan_to_pl status != DMA_COMPLETE\\n\", side_ch_compatible_str);\n\t\t\tgoto err_dst_buf_with_unmap;\n\t\t}\n\n\t\tchan_to_ps_tmo = wait_for_completion_timeout(&chan_to_ps_cmp, chan_to_ps_tmo);\n\t\tstatus = dma_async_is_tx_complete(chan_to_ps, chan_to_ps_cookie, NULL, NULL);\n\t\tif (chan_to_ps_tmo == 0) {\n\t\t\tprintk(\"%s dma_loopback_test chan_to_ps_tmo == 0\\n\", side_ch_compatible_str);\n\t\t\tgoto err_dst_buf_with_unmap;\n\t\t} else if (status != DMA_COMPLETE) {\n\t\t\tprintk(\"%s dma_loopback_test chan_to_ps status != DMA_COMPLETE\\n\", side_ch_compatible_str);\n\t\t\tgoto err_dst_buf_with_unmap;\n\t\t}\n\n\t\tdma_unmap_single(chan_to_pl_dev->dev, src_buf_dma, test_buf_size, DMA_MEM_TO_DEV);\n\t\tdma_unmap_single(chan_to_ps_dev->dev, dst_buf_dma, test_buf_size, DMA_DEV_TO_MEM);\n\n\t\t// test buf verification\n\t\tfor (i=0; i<test_buf_size; i++) {\n\t\t\t//printk(\"%d \", dst_buf[i]);\n\t\t\tif ( dst_buf[i] != ((test_idx+test_buf_size-i-1)%256) )\n\t\t\t\tbreak;\n\t\t}\n\t\tprintk(\"\\n\");\n\t\tprintk(\"%s dma_loopback_test buf verification end idx %d (test_buf_size %d)\\n\", side_ch_compatible_str, i, test_buf_size);\n\n\t\tkfree(src_buf);\n\t\tkfree(dst_buf);\n\t}\n\n\tprintk(\"%s dma_loopback_test err %d\\n\", side_ch_compatible_str, err);\n\treturn(err);\n\nerr_dst_buf_with_unmap:\n\tdma_unmap_single(chan_to_ps_dev->dev, dst_buf_dma, test_buf_size, DMA_DEV_TO_MEM);\n\t\nerr_dst_buf_dma_mapping:\n\tdma_unmap_single(chan_to_pl_dev->dev, src_buf_dma, test_buf_size, DMA_MEM_TO_DEV);\n\nerr_src_buf_dma_mapping:\n\nerr_dst_buf:\n\terr = -4;\n\tkfree((void*)dst_buf);\n\nerr_src_buf:\n\terr = -3;\n\tkfree(src_buf);\n\n\treturn(err);\n}\n#endif\n\nstatic int init_side_channel(void) {\n\tside_info_buf = kmalloc(max_side_info_buf_size, GFP_KERNEL);\n\tif (!side_info_buf)\n\t\treturn(-1);\n\n\treturn(0);\n}\n\nstatic int get_side_info(int num_eq, int iq_len) {\n\t// int err = 0;//, i;\n\tstruct scatterlist chan_to_ps_sg[1];\n\tenum dma_status status;\n\tenum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;\n\tint num_dma_symbol, num_dma_symbol_per_trans, side_info_buf_size;\n\tdma_addr_t side_info_buf_dma;\n\tstruct dma_device *chan_to_ps_dev = chan_to_ps->device;\n\tstruct completion chan_to_ps_cmp;\n\tstruct dma_async_tx_descriptor *chan_to_ps_d = NULL;\n\tunsigned long chan_to_ps_tmo =\tmsecs_to_jiffies(100);\n\n\tif (side_info_buf==NULL) {\n\t\tprintk(\"%s get_side_info WARNING side_info_buf==NULL\\n\", side_ch_compatible_str);\n\t\treturn(-1);\n\t}\n\n\tstatus = dma_async_is_tx_complete(chan_to_ps, chan_to_ps_cookie, NULL, NULL);\n\tif (status!=DMA_COMPLETE) {\n\t\tprintk(\"%s get_side_info WARNING status!=DMA_COMPLETE\\n\", side_ch_compatible_str);\n\t\treturn(-1);\n\t}\n\n\tset_user_nice(current, 10);\n\n\tif (iq_len>0)\n\t\tnum_dma_symbol_per_trans = 1+iq_len;\n\telse\n\t\tnum_dma_symbol_per_trans = HEADER_LEN + CSI_LEN + num_eq*EQUALIZER_LEN;\n\t//set number of dma symbols expected to ps\n\tnum_dma_symbol = SIDE_CH_REG_M_AXIS_DATA_COUNT_read();\n\t// printk(\"%s get_side_info m axis data count %d per trans %d\\n\", side_ch_compatible_str, num_dma_symbol, num_dma_symbol_per_trans);\n\tnum_dma_symbol = num_dma_symbol_per_trans*(num_dma_symbol/num_dma_symbol_per_trans);\n\t// printk(\"%s get_side_info actual num dma symbol %d\\n\", side_ch_compatible_str, num_dma_symbol);\n\tif (num_dma_symbol == 0)\n\t\treturn(-2);\n\n\tside_info_buf_size = num_dma_symbol*8;\n\tside_info_buf_dma = dma_map_single(chan_to_ps_dev->dev, side_info_buf, side_info_buf_size, DMA_DEV_TO_MEM);\n\tif (dma_mapping_error(chan_to_ps_dev->dev, side_info_buf_dma)) {\n\t\tprintk(\"%s get_side_info WARNING chan_to_ps_dev DMA mapping error\\n\", side_ch_compatible_str);\n\t\treturn(-3);\n\t}\n\n\tsg_init_table(chan_to_ps_sg, 1);\n\tsg_dma_address(&chan_to_ps_sg[0]) = side_info_buf_dma;\n\tsg_dma_len(&chan_to_ps_sg[0]) = side_info_buf_size;\n\n\tchan_to_ps_d = chan_to_ps_dev->device_prep_slave_sg(chan_to_ps, chan_to_ps_sg, 1, DMA_DEV_TO_MEM, flags, NULL);\n\tif (!chan_to_ps_d) {\n\t\tprintk(\"%s get_side_info WARNING !chan_to_ps_d\\n\", side_ch_compatible_str);\n\t\tgoto err_dst_buf_with_unmap;\n\t}\n\n\tinit_completion(&chan_to_ps_cmp);\n\tchan_to_ps_d->callback = chan_to_ps_callback;\n\tchan_to_ps_d->callback_param = &chan_to_ps_cmp;\n\n\tchan_to_ps_cookie = chan_to_ps_d->tx_submit(chan_to_ps_d);\n\tif (dma_submit_error(chan_to_ps_cookie)) {\n\t\tprintk(\"%s get_side_info WARNING dma_submit_error\\n\", side_ch_compatible_str);\n\t\tgoto err_dst_buf_with_unmap;\n\t}\n\n\tSIDE_CH_REG_NUM_DMA_SYMBOL_write(num_dma_symbol); //dma from fpga will start automatically\n\n\tdma_async_issue_pending(chan_to_ps);\n\n\tchan_to_ps_tmo = wait_for_completion_timeout(&chan_to_ps_cmp, chan_to_ps_tmo);\n\tstatus = dma_async_is_tx_complete(chan_to_ps, chan_to_ps_cookie, NULL, NULL);\n\tif (chan_to_ps_tmo == 0) {\n\t\tprintk(\"%s get_side_info WARNING chan_to_ps_tmo == 0\\n\", side_ch_compatible_str);\n\t\tgoto err_dst_buf_with_unmap;\n\t} else if (status != DMA_COMPLETE) {\n\t\tprintk(\"%s get_side_info WARNING chan_to_ps status != DMA_COMPLETE\\n\", side_ch_compatible_str);\n\t\tgoto err_dst_buf_with_unmap;\n\t}\n\n\tdma_unmap_single(chan_to_ps_dev->dev, side_info_buf_dma, side_info_buf_size, DMA_DEV_TO_MEM);\n\treturn(side_info_buf_size);\n\nerr_dst_buf_with_unmap:\n\tdma_unmap_single(chan_to_ps_dev->dev, side_info_buf_dma, side_info_buf_size, DMA_DEV_TO_MEM);\n\treturn(-100);\n}\n\n// -----------------netlink recv and send-----------------\n// should align with side_ch_ctl.c in user_space\n#define ACTION_INVALID       0\n#define ACTION_REG_WRITE     1\n#define ACTION_REG_READ      2\n#define ACTION_SIDE_INFO_GET 3\n\n#define REG_TYPE_INVALID     0\n#define REG_TYPE_HARDWARE    1\n#define REG_TYPE_SOFTWARE    2\n\n// #define NETLINK_USER 31\nstruct sock *nl_sk = NULL;\nstatic void side_ch_nl_recv_msg(struct sk_buff *skb) {\n\tstruct nlmsghdr *nlh;\n\tint pid;\n\tstruct sk_buff *skb_out;\n\tint msg_size;\n\tint *msg=(int*)side_info_buf;\n\tint action_flag, reg_type, reg_idx;\n\tu32 reg_val, *cmd_buf;\n\tint res;\n\n\t// printk(KERN_INFO \"Entering: %s\\n\", __FUNCTION__);\n\n\t// msg_size=strlen(msg);\n\n\tnlh=(struct nlmsghdr*)skb->data;\n\tcmd_buf = (u32*)nlmsg_data(nlh);\n\t// printk(KERN_INFO \"Netlink received msg payload:%s\\n\",(char*)nlmsg_data(nlh));\n\taction_flag = cmd_buf[0];\n    reg_type = cmd_buf[1];\n    reg_idx = cmd_buf[2];\n    reg_val = cmd_buf[3];\n\t// printk(\"%s recv msg: len %d action_flag %d reg_type %d reg_idx %d reg_val %u\\n\", side_ch_compatible_str, nlmsg_len(nlh), action_flag, reg_type, reg_idx, reg_val);\n\n\tpid = nlh->nlmsg_pid; /*pid of sending process */\n\n\tif (action_flag==ACTION_SIDE_INFO_GET) {\n\t\tres = get_side_info(num_eq_init, iq_len_init);\n\t\t// printk(KERN_INFO \"%s recv msg: get_side_info(%d,%d) res %d\\n\", side_ch_compatible_str, num_eq_init, iq_len_init, res);\n\t\tif (res>0) {\n\t\t\tmsg_size = res;\n\t\t\t// printk(\"%s recv msg: %d %d %d %d %d %d %d %d\\n\", side_ch_compatible_str, msg[0], msg[1], msg[2], msg[3], msg[4], msg[5], msg[6], msg[7]);\n\t\t} else {\n\t\t\tmsg_size = 4;\n\t\t\tmsg[0] = -2;\n\t\t}\n\t} else if (action_flag==ACTION_REG_READ) {\n\t\tmsg_size = 4;\n\t\t// if (reg_idx<0 || reg_idx>31) {\n\t\t// \tmsg[0] = -3;\n\t\t// \tprintk(\"%s recv msg: invalid reg_idx\\n\", side_ch_compatible_str);\n\t\t// } else {\n\t\t\tmsg[0] = reg_read(reg_idx*4);\n\t\t// }\n\t} else if (action_flag==ACTION_REG_WRITE) {\n\t\tmsg_size = 4;\n\t\t// if (reg_idx<0 || reg_idx>31) {\n\t\t// \tmsg[0] = -4;\n\t\t// \tprintk(\"%s recv msg: invalid reg_idx\\n\", side_ch_compatible_str);\n\t\t// } else {\n\t\t\tmsg[0] = 0;\n\t\t\treg_write(reg_idx*4, reg_val);\n\t\t// }\n\t} else {\n\t\tmsg_size = 4;\n\t\tmsg[0] = -1;\n\t\tprintk(\"%s recv msg: invalid action_flag\\n\", side_ch_compatible_str);\n\t}\n\n\tskb_out = nlmsg_new(msg_size,0);\n\tif(!skb_out)\n\t{\n\t\tprintk(KERN_ERR \"Failed to allocate new skb\\n\");\n\t\treturn;\n\t} \n\tnlh=nlmsg_put(skb_out,0,0,NLMSG_DONE,msg_size,0);  \n\tNETLINK_CB(skb_out).dst_group = 0; /* not in mcast group */\n\n\tmemcpy(nlmsg_data(nlh),msg,msg_size);\n\n\tres=nlmsg_unicast(nl_sk,skb_out,pid);\n\n\tif(res<0)\n\t\tprintk(KERN_INFO \"Error while sending bak to user\\n\");\n}\n\nstatic int dev_probe(struct platform_device *pdev) {\n\tstruct netlink_kernel_cfg cfg = {\n\t\t.input = side_ch_nl_recv_msg,\n\t};\n\n\tstruct device_node *np = pdev->dev.of_node;\n\tstruct resource *io;\n\tint err=1, i;\n\n\tprintk(\"\\n\");\n\n\tif (np) {\n\t\tconst struct of_device_id *match;\n\n\t\tmatch = of_match_node(dev_of_ids, np);\n\t\tif (match) {\n\t\t\tprintk(\"%s dev_probe: match!\\n\", side_ch_compatible_str);\n\t\t\terr = 0;\n\t\t}\n\t}\n\n\tif (err)\n\t\treturn err;\n\n\t/* Request and map I/O memory */\n\tio = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n\tbase_addr = devm_ioremap_resource(&pdev->dev, io);\n\tif (IS_ERR(base_addr))\n\t\treturn PTR_ERR(base_addr);\n\n\tprintk(\"%s dev_probe: io start 0x%p end 0x%p name %s flags 0x%08x desc %s\\n\", side_ch_compatible_str, (void*)io->start, (void*)io->end, io->name, (u32)io->flags, (char*)io->desc);\n\tprintk(\"%s dev_probe: base_addr 0x%p\\n\", side_ch_compatible_str, base_addr);\n\n\tprintk(\"%s dev_probe: succeed!\\n\", side_ch_compatible_str);\n\n\t// --------------initialize netlink--------------\n\t//nl_sk = netlink_kernel_create(&init_net, NETLINK_USER, &cfg);\n\tnl_sk = netlink_kernel_create(&init_net, NETLINK_USERSOCK, &cfg);\n\tif(!nl_sk) {\n\t\tprintk(KERN_ALERT \"%s dev_probe: Error creating socket.\\n\", side_ch_compatible_str);\n\t\treturn -10;\n\t}\n\n\t//-----------------initialize fpga----------------\n\tprintk(\"%s dev_probe: num_eq_init %d iq_len_init %d\\n\",side_ch_compatible_str, num_eq_init, iq_len_init);\n\t\n\t// disable potential any action from side channel\n\tSIDE_CH_REG_MULTI_RST_write(4);\n\t// SIDE_CH_REG_CONFIG_write(0X6001); // match addr1 and addr2; bit12 FC; bit13 addr1; bit14 addr2\n\tSIDE_CH_REG_CONFIG_write(0x7001); // the most strict condition to prevent side channel action\n\tSIDE_CH_REG_IQ_TRIGGER_write(10); // set iq trigger to rssi, which will never happen when rssi_th is 0\n\tSIDE_CH_REG_NUM_EQ_write(num_eq_init);      // capture CSI + 8*equalizer by default\n\tif (iq_len_init>0) {//initialize the side channel into iq capture mode\n\t\t//Max UDP 65507 bytes; (65507/8)-1 = 8187\n\t\tif (iq_len_init>8187) {\n\t\t\tiq_len_init = 8187;\n\t\t\tprintk(\"%s dev_probe: limit iq_len_init to 8187!\\n\",side_ch_compatible_str);\n\t\t}\n\t\tSIDE_CH_REG_IQ_CAPTURE_write(1);\n\t\tSIDE_CH_REG_PRE_TRIGGER_LEN_write(8190);\n\t\tSIDE_CH_REG_IQ_LEN_write(iq_len_init);\n\t\tSIDE_CH_REG_IQ_TRIGGER_write(0); // trigger is set to fcs ok/nok (both)\n\t}\n\n\tSIDE_CH_REG_CONFIG_write(0x0001); // allow all packets by default; bit12 FC; bit13 addr1; bit14 addr2\n\n\t//rst\n\tfor (i=0;i<8;i++)\n\t\tSIDE_CH_REG_MULTI_RST_write(0);\n\tfor (i=0;i<32;i++)\n\t\tSIDE_CH_REG_MULTI_RST_write(0xFFFFFFFF);\n\tfor (i=0;i<8;i++)\n\t\tSIDE_CH_REG_MULTI_RST_write(0);\n\t\n\t// chan_to_pl = dma_request_slave_channel(&(pdev->dev), \"rx_dma_mm2s\");\n\t// if (IS_ERR(chan_to_pl)) {\n\t// \terr = PTR_ERR(chan_to_pl);\n\t// \tpr_err(\"%s dev_probe: No channel to PL. %d\\n\",side_ch_compatible_str,err);\n\t// \tgoto free_chan_to_pl;\n\t// }\n\n\tchan_to_ps = dma_request_chan(&(pdev->dev), \"tx_dma_s2mm\");\n\tif (IS_ERR(chan_to_ps) || chan_to_ps==NULL) {\n\t\terr = PTR_ERR(chan_to_ps);\n\t\tif (err != -EPROBE_DEFER) {\n\t\t\tpr_err(\"%s dev_probe: No chan_to_ps ret %d chan_to_ps 0x%p\\n\",side_ch_compatible_str, err, chan_to_ps);\n\t\t\tgoto free_chan_to_ps;\n\t\t}\n\t}\n\n\tprintk(\"%s dev_probe: DMA channel setup successfully. chan_to_pl 0x%p chan_to_ps 0x%p\\n\",side_ch_compatible_str, chan_to_pl, chan_to_ps);\n\n\t// res = dma_loopback_test(3, 512);\n\t// printk(KERN_INFO \"dma_loopback_test(3, 512) res %d\\n\", res);\n\n\terr = init_side_channel();\n\tprintk(\"%s dev_probe: init_side_channel() err %d\\n\",side_ch_compatible_str, err);\n\n\treturn(err);\n\n\t// err = dma_loopback_test(7, 512);\n\t// if (err == 0)\n\t// \treturn(err);\n\t// else\n\t// \tdma_release_channel(chan_to_ps);\n\nfree_chan_to_ps:\n\terr = -2;\n\tdma_release_channel(chan_to_ps);\n\treturn err;\n\n// free_chan_to_pl:\n// \terr = -1;\n// \tdma_release_channel(chan_to_pl);\n// \treturn err;\n}\n\nstatic int dev_remove(struct platform_device *pdev)\n{\n\tprintk(\"\\n\");\n\n\tprintk(\"%s dev_remove: release nl_sk\\n\", side_ch_compatible_str);\n\tnetlink_kernel_release(nl_sk);\n\n\t// pr_info(\"%s dev_remove: dropped chan_to_pl 0x%p\\n\", side_ch_compatible_str, chan_to_pl);\n\t// if (chan_to_pl != NULL) {\n\t// \tpr_info(\"%s dev_remove: dropped channel %s\\n\", side_ch_compatible_str, dma_chan_name(chan_to_pl));\n\t// \t// dmaengine_terminate_all(chan_to_pl); //this also terminate sdr.ko. do not use\n\t// \tdma_release_channel(chan_to_pl);\n\t// }\n\n\tpr_info(\"%s dev_remove: dropped chan_to_ps 0x%p\\n\", side_ch_compatible_str, chan_to_ps);\n\tif (chan_to_pl != NULL) {\n\t\tpr_info(\"%s dev_remove: dropped channel %s\\n\", side_ch_compatible_str, dma_chan_name(chan_to_ps));\n\t\t// dmaengine_terminate_all(chan_to_ps); //this also terminate sdr.ko. do not use\n\t\tdma_release_channel(chan_to_ps);\n\t}\n\n\tif (side_info_buf != NULL)\n\t\tkfree(side_info_buf);\n\t\n\tprintk(\"%s dev_remove: base_addr 0x%p\\n\", side_ch_compatible_str, base_addr);\n\tprintk(\"%s dev_remove: succeed!\\n\", side_ch_compatible_str);\n\treturn 0;\n}\n\nstatic struct platform_driver dev_driver = {\n\t.driver = {\n\t\t.name = \"sdr,side_ch\",\n\t\t.owner = THIS_MODULE,\n\t\t.of_match_table = dev_of_ids,\n\t},\n\t.probe = dev_probe,\n\t.remove = dev_remove,\n};\n\nmodule_platform_driver(dev_driver);\n\nMODULE_AUTHOR(\"Xianjun Jiao\");\nMODULE_DESCRIPTION(\"sdr,side_ch\");\nMODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "driver/side_ch/side_ch.h",
    "content": "// Author: Xianjun Jiao\n// SPDX-FileCopyrightText: 2019 UGent\n// SPDX-License-Identifier: AGPL-3.0-or-later\n\n// ---------------------------------------side channel-------------------------------\nconst char *side_ch_compatible_str = \"sdr,side_ch\";\n\n//align with side_ch_control.v and all related user space, remote files\n#define CSI_LEN 56 // length of single CSI\n#define EQUALIZER_LEN (56-4) // for non HT, four {32767,32767} will be padded to achieve 52 (non HT should have 48)\n#define HEADER_LEN 2 //timestamp and frequency offset\n\n#define MAX_NUM_DMA_SYMBOL                         8192   //align with side_ch.v side_ch.h\n\n#define SIDE_CH_REG_MULTI_RST_ADDR                 (0*4)\n#define SIDE_CH_REG_CONFIG_ADDR                    (1*4)\n#define SIDE_CH_REG_NUM_DMA_SYMBOL_ADDR            (2*4) //low 16bit to PS; high 16bit to PL\n#define SIDE_CH_REG_IQ_CAPTURE_ADDR                (3*4)\n#define SIDE_CH_REG_NUM_EQ_ADDR                    (4*4)\n#define SIDE_CH_REG_FC_TARGET_ADDR                 (5*4)\n#define SIDE_CH_REG_ADDR1_TARGET_ADDR              (6*4)\n#define SIDE_CH_REG_ADDR2_TARGET_ADDR              (7*4)\n#define SIDE_CH_REG_IQ_TRIGGER_ADDR                (8*4)\n#define SIDE_CH_REG_RSSI_TH_ADDR                   (9*4)\n#define SIDE_CH_REG_GAIN_TH_ADDR                   (10*4)\n#define SIDE_CH_REG_PRE_TRIGGER_LEN_ADDR           (11*4)\n#define SIDE_CH_REG_IQ_LEN_ADDR                    (12*4)\n\n#define SIDE_CH_REG_M_AXIS_DATA_COUNT_ADDR         (20*4)\n"
  },
  {
    "path": "driver/sysfs_intf.c",
    "content": "// Author: Xianjun Jiao, Michael Mehari, Wei Liu\n// SPDX-FileCopyrightText: 2019 UGent\n// SPDX-License-Identifier: AGPL-3.0-or-later\n\n// #define TX_INTF_IQ_WRITE_TXT_FORMAT 1//while using TXT format, the txt file size should <= 4096!!!\n#define TX_INTF_IQ_WRITE_BIN_FORMAT 1\n\n#ifdef TX_INTF_IQ_WRITE_TXT_FORMAT\nstatic int is_valid_iq_number(int c) {\n\tif (c==32 || (c>=44 && c<=57))\n\t\treturn(1);\n\telse\n\t\treturn(0);\n}\n\nstatic ssize_t openwifi_tx_intf_bin_iq_write(struct file *filp, struct kobject *kobj,\n\t\t       struct bin_attribute *bin_attr,\n\t\t       char *buf, loff_t off, size_t count)\n{\n\tstruct platform_device *pdev = to_platform_device(kobj_to_dev(kobj));\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\tint ret, i, q, num_iq;\n\tchar *line;\n\tchar *ptr = buf;\n\n\tprintk(\"%s openwifi_tx_intf_bin_iq_write: count %d\\n\", sdr_compatible_str, (int)count);\n\n\tnum_iq = 0;\n\tline = ptr;\n\twhile (1) {\n\t\tret = sscanf(line, \"%d,%d\\n\", &i, &q);\n\t\tif (ret == 0) {\n\t\t\tprintk(\"%s openwifi_tx_intf_bin_iq_write: sscanf ret 0\\n\", sdr_compatible_str);\n\t\t\tbreak;\n\t\t} else if (ret != 2) {\n\t\t\tprintk(\"%s openwifi_tx_intf_bin_iq_write: sscanf ret %d i %d q %d num_iq %d\\n\", sdr_compatible_str, ret, i, q, num_iq);\n\t\t\treturn -EINVAL;\n\t\t}\n\t\t\n\t\tpriv->tx_intf_arbitrary_iq[num_iq] = ( (q<<16)|(i&0xFFFF) );\n\t\tnum_iq++;\n\t\tif (num_iq == 512) {\n\t\t\tprintk(\"%s openwifi_tx_intf_bin_iq_write: num_iq reach 512\\n\", sdr_compatible_str);\n\t\t\tbreak;\n\t\t}\n\n\t\t//go to the next line\n\t\twhile(is_valid_iq_number(ptr[0]))\n\t\t\tptr++;\n\t\twhile( (is_valid_iq_number(ptr[0])==0)&&(ptr[0]!=0) )\n\t\t\tptr++;\n\t\tif (ptr[0] == 0) {\n\t\t\tprintk(\"%s openwifi_tx_intf_bin_iq_write: ptr[0] == 0\\n\", sdr_compatible_str);\n\t\t\tbreak;\n\t\t}\n\t\tline = ptr;\n\t}\n\tpriv->tx_intf_arbitrary_iq_num = num_iq;\n\n\tprintk(\"%s openwifi_tx_intf_bin_iq_write: num_iq %d\\n\", sdr_compatible_str, num_iq);\n\t//print i/q\n\tfor (i=0; i<num_iq; i++)\n\t\tprintk(\"%d %d\\n\", (short)(priv->tx_intf_arbitrary_iq[i]&0xffff), (short)((priv->tx_intf_arbitrary_iq[i]>>16)&0xffff) );\n\t\n\treturn count;\n}\n#else\nstatic ssize_t openwifi_tx_intf_bin_iq_write(struct file *filp, struct kobject *kobj,\n\t\t       struct bin_attribute *bin_attr,\n\t\t       char *buf, loff_t off, size_t count)\n{\n\tstruct platform_device *pdev = to_platform_device(kobj_to_dev(kobj));\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\tint num_iq, i;\n\n\tprintk(\"%s openwifi_tx_intf_bin_iq_write: count %d\\n\", sdr_compatible_str, (int)count);\n\n\tif ((count%4) != 0) {\n\t\tprintk(\"%s openwifi_tx_intf_bin_iq_write: count is not integer times of 4!\\n\", sdr_compatible_str);\n\t\treturn -EINVAL;\n\t}\n\n\tnum_iq = count/4;\n\tpriv->tx_intf_arbitrary_iq_num = num_iq;\n\n\tfor (i=0; i<num_iq; i++) {\n\t\tpriv->tx_intf_arbitrary_iq[i] = (*((u32*)(buf+(i*4))));\n\t}\n\n\t// printk(\"%s openwifi_tx_intf_bin_iq_write: num_iq %d\\n\", sdr_compatible_str, num_iq);\n\t// //print i/q\n\t// for (i=0; i<num_iq; i++)\n\t// \tprintk(\"%d %d\\n\", (short)(priv->tx_intf_arbitrary_iq[i]&0xffff), (short)((priv->tx_intf_arbitrary_iq[i]>>16)&0xffff) );\n\t\n\treturn count;\n}\n#endif\n\nstatic ssize_t openwifi_tx_intf_bin_iq_read(struct file *filp, struct kobject *kobj,\n\t\t       struct bin_attribute *bin_attr,\n\t\t       char *buf, loff_t off, size_t count)\n{\n\tstruct platform_device *pdev = to_platform_device(kobj_to_dev(kobj));\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\tint num_iq, ret_size, i;\n\n\tif (off)\n\t\treturn 0;\n\n\tnum_iq = priv->tx_intf_arbitrary_iq_num;\n\n\t// printk(\"%s openwifi_tx_intf_bin_iq_read: num_iq %d\\n\", sdr_compatible_str, num_iq);\n\t// //print i/q\n\t// for (i=0; i<num_iq; i++)\n\t// \tprintk(\"%d %d\\n\", (short)(priv->tx_intf_arbitrary_iq[i]&0xffff), (short)((priv->tx_intf_arbitrary_iq[i]>>16)&0xffff) );\n\n\tret_size = sprintf(buf, \"%d\\n\", num_iq);\n\tif (num_iq==0 || num_iq>512) {\n\t\tret_size = ret_size + sprintf(buf+ret_size, \"num_iq is wrong!\\n\");\n\t\treturn ret_size;\n\t}\n\n\t//print i\n\tfor (i=0; i<num_iq; i++)\n\t\tret_size = ret_size + sprintf(buf+ret_size, \"%d \", (short)(priv->tx_intf_arbitrary_iq[i]&0xffff) );\n\tret_size = ret_size + sprintf(buf+ret_size, \"\\n\");\n\t\n\t//print q\n\tfor (i=0; i<num_iq; i++)\n\t\tret_size = ret_size + sprintf(buf+ret_size, \"%d \", (short)((priv->tx_intf_arbitrary_iq[i]>>16)&0xffff) );\n\tret_size = ret_size + sprintf(buf+ret_size, \"\\n\");\n\n\treturn ret_size;\n}\n\nstatic ssize_t tx_intf_iq_ctl_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\t\n\treturn sprintf(buf, \"%u\\n\", priv->tx_intf_iq_ctl);\n}\nstatic ssize_t tx_intf_iq_ctl_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tint i;\n\tint ret = kstrtol(buf, 10, &readin);\n\n\tpriv->tx_intf_iq_ctl = readin;\n\n\ttx_intf_api->TX_INTF_REG_ARBITRARY_IQ_CTL_write(1); // switch to iq mode\n\tprintk(\"%s tx_intf_iq_ctl_store: Will send %d I/Q\\n\", sdr_compatible_str, priv->tx_intf_arbitrary_iq_num);\n\tfor (i=0; i<priv->tx_intf_arbitrary_iq_num; i++) {\n\t\ttx_intf_api->TX_INTF_REG_ARBITRARY_IQ_write(priv->tx_intf_arbitrary_iq[i]);\n\t}\n\ttx_intf_api->TX_INTF_REG_ARBITRARY_IQ_CTL_write(3); // start send\n\ttx_intf_api->TX_INTF_REG_ARBITRARY_IQ_CTL_write(0);\n\n\treturn ret ? ret : len;\n}\n\nstatic DEVICE_ATTR(tx_intf_iq_ctl, S_IRUGO | S_IWUSR, tx_intf_iq_ctl_show, tx_intf_iq_ctl_store);\nstatic struct attribute *tx_intf_attributes[] = {\n\t&dev_attr_tx_intf_iq_ctl.attr,\n\tNULL,\n};\nstatic const struct attribute_group tx_intf_attribute_group = {\n\t.attrs = tx_intf_attributes,\n};\n\nstatic ssize_t stat_enable_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\t\n\treturn sprintf(buf, \"%u\\n\", priv->stat.stat_enable);\n}\nstatic ssize_t stat_enable_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin);\n\n\tpriv->stat.stat_enable = readin;\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t tx_prio_queue_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tu32 i, ret_size = 0;\n\n\tfor (i=0; i<MAX_NUM_SW_QUEUE; i++) {\n\t\tret_size = ret_size + sprintf(buf+ret_size, \"%u %u %u %u %u %u %u %u %u %u %u %u\\n\", \n\t\tpriv->stat.tx_prio_num[i],\n\t\tpriv->stat.tx_prio_interrupt_num[i], \n\t\tpriv->stat.tx_prio_stop0_fake_num[i], \n\t\tpriv->stat.tx_prio_stop0_real_num[i],\n\t\tpriv->stat.tx_prio_stop1_num[i],\n\t\tpriv->stat.tx_prio_wakeup_num[i],\n\t\tpriv->stat.tx_queue_num[i],\n\t\tpriv->stat.tx_queue_interrupt_num[i],\n\t\tpriv->stat.tx_queue_stop0_fake_num[i],\n\t\tpriv->stat.tx_queue_stop0_real_num[i],\n\t\tpriv->stat.tx_queue_stop1_num[i],\n\t\tpriv->stat.tx_queue_wakeup_num[i]);\n\t}\n\t\n\treturn ret_size;\n}\nstatic ssize_t tx_prio_queue_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tu32 i;\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin);\n\n\tfor (i=0; i<MAX_NUM_SW_QUEUE; i++) {\n\t\tpriv->stat.tx_prio_num[i] = 0;\n\t\tpriv->stat.tx_prio_interrupt_num[i] = 0;\n\t\tpriv->stat.tx_prio_stop0_fake_num[i] = 0;\n\t\tpriv->stat.tx_prio_stop0_real_num[i] = 0;\n\t\tpriv->stat.tx_prio_stop1_num[i] = 0;\n\t\tpriv->stat.tx_prio_wakeup_num[i] = 0;\n\t}\n\tfor (i=0; i<MAX_NUM_HW_QUEUE; i++) {\n\t\tpriv->stat.tx_queue_num[i] = 0;\n\t\tpriv->stat.tx_queue_interrupt_num[i] = 0;\n\t\tpriv->stat.tx_queue_stop0_fake_num[i] = 0;\n\t\tpriv->stat.tx_queue_stop0_real_num[i] = 0;\n\t\tpriv->stat.tx_queue_stop1_num[i] = 0;\n\t\tpriv->stat.tx_queue_wakeup_num[i] = 0;\n\t}\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t tx_data_pkt_need_ack_num_total_fail_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\t\n\treturn sprintf(buf, \"%u\\n\", priv->stat.tx_data_pkt_need_ack_num_total_fail);\n}\nstatic ssize_t tx_data_pkt_need_ack_num_total_fail_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin);\n\n\tpriv->stat.tx_data_pkt_need_ack_num_total_fail = readin;\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t tx_data_pkt_need_ack_num_total_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\t\n\treturn sprintf(buf, \"%u\\n\", priv->stat.tx_data_pkt_need_ack_num_total);\n}\nstatic ssize_t tx_data_pkt_need_ack_num_total_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin);\n\n\tpriv->stat.tx_data_pkt_need_ack_num_total = readin;\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t tx_mgmt_pkt_need_ack_num_total_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\t\n\treturn sprintf(buf, \"%u\\n\", priv->stat.tx_mgmt_pkt_need_ack_num_total);\n}\nstatic ssize_t tx_mgmt_pkt_need_ack_num_total_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin);\n\n\tpriv->stat.tx_mgmt_pkt_need_ack_num_total = readin;\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t tx_mgmt_pkt_need_ack_num_total_fail_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\t\n\treturn sprintf(buf, \"%u\\n\", priv->stat.tx_mgmt_pkt_need_ack_num_total_fail);\n}\nstatic ssize_t tx_mgmt_pkt_need_ack_num_total_fail_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin);\n\n\tpriv->stat.tx_mgmt_pkt_need_ack_num_total_fail = readin;\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t tx_data_pkt_need_ack_num_retx_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\t\n\treturn sprintf(buf, \"%u %u %u %u %u %u\\n\", \n\t\t\t\t\tpriv->stat.tx_data_pkt_need_ack_num_retx[0], \n\t\t\t\t\tpriv->stat.tx_data_pkt_need_ack_num_retx[1], \n\t\t\t\t\tpriv->stat.tx_data_pkt_need_ack_num_retx[2], \n\t\t\t\t\tpriv->stat.tx_data_pkt_need_ack_num_retx[3], \n\t\t\t\t\tpriv->stat.tx_data_pkt_need_ack_num_retx[4], \n\t\t\t\t\tpriv->stat.tx_data_pkt_need_ack_num_retx[5]);\n}\nstatic ssize_t tx_data_pkt_need_ack_num_retx_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin), i;\n\n\tfor (i=0; i<6; i++)\n\t\tpriv->stat.tx_data_pkt_need_ack_num_retx[i] = readin;\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t tx_mgmt_pkt_need_ack_num_retx_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\t\n\treturn sprintf(buf, \"%u %u %u\\n\", \n\t\t\t\tpriv->stat.tx_mgmt_pkt_need_ack_num_retx[0],\n\t\t\t\tpriv->stat.tx_mgmt_pkt_need_ack_num_retx[1],\n\t\t\t\tpriv->stat.tx_mgmt_pkt_need_ack_num_retx[2]);\n}\nstatic ssize_t tx_mgmt_pkt_need_ack_num_retx_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin), i;\n\n\tfor (i=0; i<3; i++)\n\t\tpriv->stat.tx_mgmt_pkt_need_ack_num_retx[i] = readin;\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t tx_data_pkt_need_ack_num_retx_fail_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\t\n\treturn sprintf(buf, \"%u %u %u %u %u %u\\n\", \n\t\t\t\tpriv->stat.tx_data_pkt_need_ack_num_retx_fail[0],\n\t\t\t\tpriv->stat.tx_data_pkt_need_ack_num_retx_fail[1],\n\t\t\t\tpriv->stat.tx_data_pkt_need_ack_num_retx_fail[2],\n\t\t\t\tpriv->stat.tx_data_pkt_need_ack_num_retx_fail[3],\n\t\t\t\tpriv->stat.tx_data_pkt_need_ack_num_retx_fail[4],\n\t\t\t\tpriv->stat.tx_data_pkt_need_ack_num_retx_fail[5]);\n}\nstatic ssize_t tx_data_pkt_need_ack_num_retx_fail_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin), i;\n\n\tfor (i=0; i<6; i++)\n\t\tpriv->stat.tx_data_pkt_need_ack_num_retx_fail[i] = readin;\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t tx_mgmt_pkt_need_ack_num_retx_fail_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\t\n\treturn sprintf(buf, \"%u %u %u\\n\", \n\t\t\t\tpriv->stat.tx_mgmt_pkt_need_ack_num_retx_fail[0], \n\t\t\t\tpriv->stat.tx_mgmt_pkt_need_ack_num_retx_fail[1], \n\t\t\t\tpriv->stat.tx_mgmt_pkt_need_ack_num_retx_fail[2]);\n}\nstatic ssize_t tx_mgmt_pkt_need_ack_num_retx_fail_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin), i;\n\n\tfor (i=0; i<3; i++)\n\t\tpriv->stat.tx_mgmt_pkt_need_ack_num_retx_fail[i] = readin;\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t tx_data_pkt_mcs_realtime_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tbool use_ht_rate = ((priv->stat.tx_data_pkt_mcs_realtime&0x80000000)!=0);\n\tu32 rate_hw_value = (priv->stat.tx_data_pkt_mcs_realtime&0x7fffffff);\n\t\n\treturn sprintf(buf, \"%uM\\n\", (use_ht_rate == false ? wifi_rate_all[rate_hw_value] : wifi_rate_all[rate_hw_value + 12]));\n}\nstatic ssize_t tx_data_pkt_mcs_realtime_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin);\n\n\tpriv->stat.tx_data_pkt_mcs_realtime = readin;\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t tx_mgmt_pkt_mcs_realtime_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tbool use_ht_rate = ((priv->stat.tx_mgmt_pkt_mcs_realtime&0x80000000)!=0);\n\tu32 rate_hw_value = (priv->stat.tx_mgmt_pkt_mcs_realtime&0x7fffffff);\n\t\n\treturn sprintf(buf, \"%uM\\n\", (use_ht_rate == false ? wifi_rate_all[rate_hw_value] : wifi_rate_all[rate_hw_value + 12]));\n}\nstatic ssize_t tx_mgmt_pkt_mcs_realtime_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin);\n\n\tpriv->stat.tx_mgmt_pkt_mcs_realtime = readin;\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t tx_mgmt_pkt_fail_mcs_realtime_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tbool use_ht_rate = ((priv->stat.tx_mgmt_pkt_fail_mcs_realtime&0x80000000)!=0);\n\tu32 rate_hw_value = (priv->stat.tx_mgmt_pkt_fail_mcs_realtime&0x7fffffff);\n\t\n\treturn sprintf(buf, \"%uM\\n\", (use_ht_rate == false ? wifi_rate_all[rate_hw_value] : wifi_rate_all[rate_hw_value + 12]));\n}\nstatic ssize_t tx_mgmt_pkt_fail_mcs_realtime_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin);\n\n\tpriv->stat.tx_mgmt_pkt_fail_mcs_realtime = readin;\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t tx_data_pkt_fail_mcs_realtime_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tbool use_ht_rate = ((priv->stat.tx_data_pkt_fail_mcs_realtime&0x80000000)!=0);\n\tu32 rate_hw_value = (priv->stat.tx_data_pkt_fail_mcs_realtime&0x7fffffff);\n\t\n\treturn sprintf(buf, \"%uM\\n\", (use_ht_rate == false ? wifi_rate_all[rate_hw_value] : wifi_rate_all[rate_hw_value + 12]));\n}\nstatic ssize_t tx_data_pkt_fail_mcs_realtime_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin);\n\n\tpriv->stat.tx_data_pkt_fail_mcs_realtime = readin;\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t rx_target_sender_mac_addr_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\t\n\treturn sprintf(buf, \"%08x\\n\", reverse32(priv->stat.rx_target_sender_mac_addr));\n}\nstatic ssize_t rx_target_sender_mac_addr_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tu32 readin;\n\tu32 ret = kstrtouint(buf, 16, &readin);\n\n\tpriv->stat.rx_target_sender_mac_addr = reverse32(readin);\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t rx_data_ok_agc_gain_value_realtime_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\t\n\treturn sprintf(buf, \"%u\\n\", priv->stat.rx_data_ok_agc_gain_value_realtime);\n}\nstatic ssize_t rx_data_ok_agc_gain_value_realtime_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin);\n\n\tpriv->stat.rx_data_ok_agc_gain_value_realtime = readin;\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t rx_mgmt_ok_agc_gain_value_realtime_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\t\n\treturn sprintf(buf, \"%u\\n\", priv->stat.rx_mgmt_ok_agc_gain_value_realtime);\n}\nstatic ssize_t rx_mgmt_ok_agc_gain_value_realtime_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin);\n\n\tpriv->stat.rx_mgmt_ok_agc_gain_value_realtime = readin;\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t rx_data_fail_agc_gain_value_realtime_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\t\n\treturn sprintf(buf, \"%u\\n\", priv->stat.rx_data_fail_agc_gain_value_realtime);\n}\nstatic ssize_t rx_data_fail_agc_gain_value_realtime_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin);\n\n\tpriv->stat.rx_data_fail_agc_gain_value_realtime = readin;\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t rx_mgmt_fail_agc_gain_value_realtime_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\t\n\treturn sprintf(buf, \"%u\\n\", priv->stat.rx_mgmt_fail_agc_gain_value_realtime);\n}\nstatic ssize_t rx_mgmt_fail_agc_gain_value_realtime_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin);\n\n\tpriv->stat.rx_mgmt_fail_agc_gain_value_realtime = readin;\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t rx_ack_ok_agc_gain_value_realtime_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\t\n\treturn sprintf(buf, \"%u\\n\", priv->stat.rx_ack_ok_agc_gain_value_realtime);\n}\nstatic ssize_t rx_ack_ok_agc_gain_value_realtime_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin);\n\n\tpriv->stat.rx_ack_ok_agc_gain_value_realtime = readin;\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t rx_monitor_all_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\t\n\treturn sprintf(buf, \"%u\\n\", priv->stat.rx_monitor_all);\n}\nstatic ssize_t rx_monitor_all_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin);\n\tu32 filter_flag;\n\n\tpriv->stat.rx_monitor_all = readin;\n\n\tfilter_flag = xpu_api->XPU_REG_FILTER_FLAG_read();\n\tif (readin>0) {// set to fpga\n\t\tfilter_flag = (filter_flag|MONITOR_ALL);\n\t} else {\n\t\tfilter_flag = (filter_flag&(~MONITOR_ALL));\n\t}\n\txpu_api->XPU_REG_FILTER_FLAG_write(filter_flag);\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t rx_data_pkt_num_total_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\t\n\treturn sprintf(buf, \"%u\\n\", priv->stat.rx_data_pkt_num_total);\n}\nstatic ssize_t rx_data_pkt_num_total_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin);\n\n\tpriv->stat.rx_data_pkt_num_total = readin;\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t rx_data_pkt_num_fail_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\t\n\treturn sprintf(buf, \"%u\\n\", priv->stat.rx_data_pkt_num_fail);\n}\nstatic ssize_t rx_data_pkt_num_fail_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin);\n\n\tpriv->stat.rx_data_pkt_num_fail = readin;\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t rx_mgmt_pkt_num_total_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\t\n\treturn sprintf(buf, \"%u\\n\", priv->stat.rx_mgmt_pkt_num_total);\n}\nstatic ssize_t rx_mgmt_pkt_num_total_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin);\n\n\tpriv->stat.rx_mgmt_pkt_num_total = readin;\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t rx_mgmt_pkt_num_fail_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\t\n\treturn sprintf(buf, \"%u\\n\", priv->stat.rx_mgmt_pkt_num_fail);\n}\nstatic ssize_t rx_mgmt_pkt_num_fail_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin);\n\n\tpriv->stat.rx_mgmt_pkt_num_fail = readin;\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t rx_ack_pkt_num_total_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\t\n\treturn sprintf(buf, \"%u\\n\", priv->stat.rx_ack_pkt_num_total);\n}\nstatic ssize_t rx_ack_pkt_num_total_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin);\n\n\tpriv->stat.rx_ack_pkt_num_total = readin;\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t rx_ack_pkt_num_fail_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\t\n\treturn sprintf(buf, \"%u\\n\", priv->stat.rx_ack_pkt_num_fail);\n}\nstatic ssize_t rx_ack_pkt_num_fail_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin);\n\n\tpriv->stat.rx_ack_pkt_num_fail = readin;\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t rx_data_pkt_mcs_realtime_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\treturn sprintf(buf, \"%uM\\n\", wifi_rate_table[priv->stat.rx_data_pkt_mcs_realtime]);\n}\nstatic ssize_t rx_data_pkt_mcs_realtime_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin);\n\n\tpriv->stat.rx_data_pkt_mcs_realtime = readin;\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t rx_data_pkt_fail_mcs_realtime_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\treturn sprintf(buf, \"%uM\\n\", wifi_rate_table[priv->stat.rx_data_pkt_fail_mcs_realtime]);\n}\nstatic ssize_t rx_data_pkt_fail_mcs_realtime_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin);\n\n\tpriv->stat.rx_data_pkt_fail_mcs_realtime = readin;\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t rx_mgmt_pkt_mcs_realtime_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\treturn sprintf(buf, \"%uM\\n\", wifi_rate_table[priv->stat.rx_mgmt_pkt_mcs_realtime]);\n}\nstatic ssize_t rx_mgmt_pkt_mcs_realtime_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin);\n\n\tpriv->stat.rx_mgmt_pkt_mcs_realtime = readin;\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t rx_mgmt_pkt_fail_mcs_realtime_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\treturn sprintf(buf, \"%uM\\n\", wifi_rate_table[priv->stat.rx_mgmt_pkt_fail_mcs_realtime]);\n}\nstatic ssize_t rx_mgmt_pkt_fail_mcs_realtime_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin);\n\n\tpriv->stat.rx_mgmt_pkt_fail_mcs_realtime = readin;\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t rx_ack_pkt_mcs_realtime_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\treturn sprintf(buf, \"%uM\\n\", wifi_rate_table[priv->stat.rx_ack_pkt_mcs_realtime]);\n}\nstatic ssize_t rx_ack_pkt_mcs_realtime_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin);\n\n\tpriv->stat.rx_ack_pkt_mcs_realtime = readin;\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t restrict_freq_mhz_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\t\n\treturn sprintf(buf, \"%u\\n\", priv->stat.restrict_freq_mhz);\n}\nstatic ssize_t restrict_freq_mhz_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n  static struct ieee80211_conf channel_conf_tmp;\n  static struct ieee80211_channel channel_tmp;\n\n  long readin;\n\tu32 ret = kstrtol(buf, 10, &readin);\n\n  channel_conf_tmp.chandef.chan = (&channel_tmp);\n\n\tpriv->stat.restrict_freq_mhz = readin;\n\n  channel_conf_tmp.chandef.chan->center_freq = priv->stat.restrict_freq_mhz;\n  ad9361_rf_set_channel(dev, &channel_conf_tmp);\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t csma_cfg0_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tu32 reg_val;\n\n\treg_val = xpu_api->XPU_REG_FORCE_IDLE_MISC_read();\n\tpriv->stat.csma_cfg0 = reg_val;\n\t\n\treturn sprintf(buf, \"nav_disable %d difs_disable %d eifs_disable %d eifs_by_rx_fail_disable %d eifs_by_tx_fail_disable %d cw_override %d cw override val %d wait_after_decode_top %d\\n\", \n\t\t\t\t\t(reg_val>>31)&1, \n\t\t\t\t\t(reg_val>>30)&1, \n\t\t\t\t\t(reg_val>>29)&1, \n          (reg_val>>27)&1, \n          (reg_val>>26)&1, \n\t\t\t\t\t(reg_val>>28)&1, \n\t\t\t\t\t(reg_val>>16)&0xf, \n\t\t\t\t\t(reg_val>>0)&0xff);\n}\nstatic ssize_t csma_cfg0_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tu32 disable_flag, idx_from_msb, reg_val;\n\tu32 readin;\n\tu32 ret = kstrtouint(buf, 16, &readin);\n\n\tdisable_flag =  (readin&0xf);\n\tidx_from_msb = ((readin>>4)&0xf);\n\n\treg_val = xpu_api->XPU_REG_FORCE_IDLE_MISC_read();\n\n\tif (disable_flag)\n\t\treg_val = (reg_val|(1<<(31-idx_from_msb)));\n\telse\n\t\treg_val = (reg_val&(~(1<<(31-idx_from_msb))));\n\n\txpu_api->XPU_REG_FORCE_IDLE_MISC_write(reg_val);\n\n\tpriv->stat.csma_cfg0 = reg_val;\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t cw_max_min_cfg_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tu32 ret_size, reg_val;\n\n\treg_val = xpu_api->XPU_REG_CSMA_CFG_read();\n\n\tret_size = sprintf(buf, \"FPGA  cw max min for q3 to q0: %d %d; %d %d; %d %d; %d %d\\n\",\n\t\t\t\t\t\t(1<<((reg_val>>28)&0xF))-1, \n\t\t\t\t\t\t(1<<((reg_val>>24)&0xF))-1, \n\t\t\t\t\t\t(1<<((reg_val>>20)&0xF))-1, \n\t\t\t\t\t\t(1<<((reg_val>>16)&0xF))-1, \n\t\t\t\t\t\t(1<<((reg_val>>12)&0xF))-1, \n\t\t\t\t\t\t(1<<((reg_val>> 8)&0xF))-1, \n\t\t\t\t\t\t(1<<((reg_val>> 4)&0xF))-1, \n\t\t\t\t\t\t(1<<((reg_val>> 0)&0xF))-1);\n\tret_size = ret_size + sprintf(buf+ret_size, \"FPGA  cw max min for q3 to q0: %08x\\n\",reg_val);\n\n\tif (priv->stat.cw_max_min_cfg) {\n\t\treg_val = priv->stat.cw_max_min_cfg;\n\t\tret_size = ret_size + sprintf(buf+ret_size, \"SYSFS cw max min for q3 to q0: %d %d; %d %d; %d %d; %d %d\\n\",\n\t\t\t\t\t\t(1<<((reg_val>>28)&0xF))-1, \n\t\t\t\t\t\t(1<<((reg_val>>24)&0xF))-1, \n\t\t\t\t\t\t(1<<((reg_val>>20)&0xF))-1, \n\t\t\t\t\t\t(1<<((reg_val>>16)&0xF))-1, \n\t\t\t\t\t\t(1<<((reg_val>>12)&0xF))-1, \n\t\t\t\t\t\t(1<<((reg_val>> 8)&0xF))-1, \n\t\t\t\t\t\t(1<<((reg_val>> 4)&0xF))-1, \n\t\t\t\t\t\t(1<<((reg_val>> 0)&0xF))-1);\n\t\tret_size = ret_size + sprintf(buf+ret_size, \"SYSFS cw max min for q3 to q0: %08x\\n\",reg_val);\n\t}\n\n\treturn ret_size;\n}\n\nstatic ssize_t cw_max_min_cfg_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tu32 readin;\n\tu32 ret = kstrtouint(buf, 16, &readin);\n\n\t// printk(\"%s %d\\n\", buf, readin);\n\n\tpriv->stat.cw_max_min_cfg = readin;\n\tif (readin)\n\t\txpu_api->XPU_REG_CSMA_CFG_write(readin);\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t dbg_ch0_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\t\n\treturn sprintf(buf, \"%u\\n\", priv->stat.dbg_ch0);\n}\nstatic ssize_t dbg_ch0_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin);\n\n\tpriv->stat.dbg_ch0 = readin;\n\n\t// xpu_api->XPU_REG_DIFS_ADVANCE_write((readin<<16)|2); //us. bit31~16 max pkt length threshold\n\t// rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write(readin<<16); //bit31~16 max pkt length threshold\n\t// openofdm_rx_api->OPENOFDM_RX_REG_SOFT_DECODING_write((readin<<16)|1); //bit1 enable soft decoding; bit31~16 max pkt length threshold\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t dbg_ch1_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\t\n\treturn sprintf(buf, \"%u\\n\", priv->stat.dbg_ch1);\n}\nstatic ssize_t dbg_ch1_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin);\n\n\tpriv->stat.dbg_ch1 = readin;\n\n\treturn ret ? ret : len;\n}\n\nstatic ssize_t dbg_ch2_show(struct device *input_dev, struct device_attribute *attr, char *buf) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\t\n\treturn sprintf(buf, \"%u\\n\", priv->stat.dbg_ch2);\n}\nstatic ssize_t dbg_ch2_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len) \n{\n\tstruct platform_device *pdev = to_platform_device(input_dev);\n\tstruct ieee80211_hw *dev = platform_get_drvdata(pdev);\n\tstruct openwifi_priv *priv = dev->priv;\n\n\tlong readin;\n\tu32 ret = kstrtol(buf, 10, &readin);\n\n\tpriv->stat.dbg_ch2 = readin;\n\n\treturn ret ? ret : len;\n}\n\nstatic DEVICE_ATTR(stat_enable, S_IRUGO | S_IWUSR, stat_enable_show, stat_enable_store);\nstatic DEVICE_ATTR(tx_prio_queue, S_IRUGO | S_IWUSR, tx_prio_queue_show, tx_prio_queue_store);\nstatic DEVICE_ATTR(tx_data_pkt_need_ack_num_total, S_IRUGO | S_IWUSR, tx_data_pkt_need_ack_num_total_show, tx_data_pkt_need_ack_num_total_store);\nstatic DEVICE_ATTR(tx_data_pkt_need_ack_num_total_fail, S_IRUGO | S_IWUSR, tx_data_pkt_need_ack_num_total_fail_show, tx_data_pkt_need_ack_num_total_fail_store);\nstatic DEVICE_ATTR(tx_data_pkt_need_ack_num_retx, S_IRUGO | S_IWUSR, tx_data_pkt_need_ack_num_retx_show, tx_data_pkt_need_ack_num_retx_store);\nstatic DEVICE_ATTR(tx_data_pkt_need_ack_num_retx_fail, S_IRUGO | S_IWUSR, tx_data_pkt_need_ack_num_retx_fail_show, tx_data_pkt_need_ack_num_retx_fail_store);\n\nstatic DEVICE_ATTR(tx_data_pkt_mcs_realtime, S_IRUGO | S_IWUSR, tx_data_pkt_mcs_realtime_show, tx_data_pkt_mcs_realtime_store);\nstatic DEVICE_ATTR(tx_data_pkt_fail_mcs_realtime, S_IRUGO | S_IWUSR, tx_data_pkt_fail_mcs_realtime_show, tx_data_pkt_fail_mcs_realtime_store);\n\nstatic DEVICE_ATTR(tx_mgmt_pkt_need_ack_num_total, S_IRUGO | S_IWUSR, tx_mgmt_pkt_need_ack_num_total_show, tx_mgmt_pkt_need_ack_num_total_store);\nstatic DEVICE_ATTR(tx_mgmt_pkt_need_ack_num_total_fail, S_IRUGO | S_IWUSR, tx_mgmt_pkt_need_ack_num_total_fail_show, tx_mgmt_pkt_need_ack_num_total_fail_store);\nstatic DEVICE_ATTR(tx_mgmt_pkt_need_ack_num_retx, S_IRUGO | S_IWUSR, tx_mgmt_pkt_need_ack_num_retx_show, tx_mgmt_pkt_need_ack_num_retx_store);\nstatic DEVICE_ATTR(tx_mgmt_pkt_need_ack_num_retx_fail, S_IRUGO | S_IWUSR, tx_mgmt_pkt_need_ack_num_retx_fail_show, tx_mgmt_pkt_need_ack_num_retx_fail_store);\n\nstatic DEVICE_ATTR(tx_mgmt_pkt_mcs_realtime, S_IRUGO | S_IWUSR, tx_mgmt_pkt_mcs_realtime_show, tx_mgmt_pkt_mcs_realtime_store);\nstatic DEVICE_ATTR(tx_mgmt_pkt_fail_mcs_realtime, S_IRUGO | S_IWUSR, tx_mgmt_pkt_fail_mcs_realtime_show, tx_mgmt_pkt_fail_mcs_realtime_store);\n\nstatic DEVICE_ATTR(rx_target_sender_mac_addr, S_IRUGO | S_IWUSR, rx_target_sender_mac_addr_show, rx_target_sender_mac_addr_store);\nstatic DEVICE_ATTR(rx_data_ok_agc_gain_value_realtime, S_IRUGO | S_IWUSR, rx_data_ok_agc_gain_value_realtime_show, rx_data_ok_agc_gain_value_realtime_store);\nstatic DEVICE_ATTR(rx_data_fail_agc_gain_value_realtime, S_IRUGO | S_IWUSR, rx_data_fail_agc_gain_value_realtime_show, rx_data_fail_agc_gain_value_realtime_store);\nstatic DEVICE_ATTR(rx_mgmt_ok_agc_gain_value_realtime, S_IRUGO | S_IWUSR, rx_mgmt_ok_agc_gain_value_realtime_show, rx_mgmt_ok_agc_gain_value_realtime_store);\nstatic DEVICE_ATTR(rx_mgmt_fail_agc_gain_value_realtime, S_IRUGO | S_IWUSR, rx_mgmt_fail_agc_gain_value_realtime_show, rx_mgmt_fail_agc_gain_value_realtime_store);\nstatic DEVICE_ATTR(rx_ack_ok_agc_gain_value_realtime, S_IRUGO | S_IWUSR, rx_ack_ok_agc_gain_value_realtime_show, rx_ack_ok_agc_gain_value_realtime_store);\n\nstatic DEVICE_ATTR(rx_monitor_all, S_IRUGO | S_IWUSR, rx_monitor_all_show, rx_monitor_all_store);\nstatic DEVICE_ATTR(rx_data_pkt_num_total, S_IRUGO | S_IWUSR, rx_data_pkt_num_total_show, rx_data_pkt_num_total_store);\nstatic DEVICE_ATTR(rx_data_pkt_num_fail, S_IRUGO | S_IWUSR, rx_data_pkt_num_fail_show, rx_data_pkt_num_fail_store);\nstatic DEVICE_ATTR(rx_mgmt_pkt_num_total, S_IRUGO | S_IWUSR, rx_mgmt_pkt_num_total_show, rx_mgmt_pkt_num_total_store);\nstatic DEVICE_ATTR(rx_mgmt_pkt_num_fail, S_IRUGO | S_IWUSR, rx_mgmt_pkt_num_fail_show, rx_mgmt_pkt_num_fail_store);\nstatic DEVICE_ATTR(rx_ack_pkt_num_total, S_IRUGO | S_IWUSR, rx_ack_pkt_num_total_show, rx_ack_pkt_num_total_store);\nstatic DEVICE_ATTR(rx_ack_pkt_num_fail, S_IRUGO | S_IWUSR, rx_ack_pkt_num_fail_show, rx_ack_pkt_num_fail_store);\n\nstatic DEVICE_ATTR(rx_data_pkt_mcs_realtime, S_IRUGO | S_IWUSR, rx_data_pkt_mcs_realtime_show, rx_data_pkt_mcs_realtime_store);\nstatic DEVICE_ATTR(rx_data_pkt_fail_mcs_realtime, S_IRUGO | S_IWUSR, rx_data_pkt_fail_mcs_realtime_show, rx_data_pkt_fail_mcs_realtime_store);\nstatic DEVICE_ATTR(rx_mgmt_pkt_mcs_realtime, S_IRUGO | S_IWUSR, rx_mgmt_pkt_mcs_realtime_show, rx_mgmt_pkt_mcs_realtime_store);\nstatic DEVICE_ATTR(rx_mgmt_pkt_fail_mcs_realtime, S_IRUGO | S_IWUSR, rx_mgmt_pkt_fail_mcs_realtime_show, rx_mgmt_pkt_fail_mcs_realtime_store);\nstatic DEVICE_ATTR(rx_ack_pkt_mcs_realtime, S_IRUGO | S_IWUSR, rx_ack_pkt_mcs_realtime_show, rx_ack_pkt_mcs_realtime_store);\n\nstatic DEVICE_ATTR(restrict_freq_mhz, S_IRUGO | S_IWUSR, restrict_freq_mhz_show, restrict_freq_mhz_store);\n\nstatic DEVICE_ATTR(csma_cfg0, S_IRUGO | S_IWUSR, csma_cfg0_show, csma_cfg0_store);\nstatic DEVICE_ATTR(cw_max_min_cfg, S_IRUGO | S_IWUSR, cw_max_min_cfg_show, cw_max_min_cfg_store);\n\nstatic DEVICE_ATTR(dbg_ch0, S_IRUGO | S_IWUSR, dbg_ch0_show, dbg_ch0_store);\nstatic DEVICE_ATTR(dbg_ch1, S_IRUGO | S_IWUSR, dbg_ch1_show, dbg_ch1_store);\nstatic DEVICE_ATTR(dbg_ch2, S_IRUGO | S_IWUSR, dbg_ch2_show, dbg_ch2_store);\n\nstatic struct attribute *stat_attributes[] = {\n\t&dev_attr_stat_enable.attr,\n\n\t&dev_attr_tx_prio_queue.attr,\n\n\t&dev_attr_tx_data_pkt_need_ack_num_total.attr,\n\t&dev_attr_tx_data_pkt_need_ack_num_total_fail.attr,\n\n\t&dev_attr_tx_data_pkt_need_ack_num_retx.attr,\n\t&dev_attr_tx_data_pkt_need_ack_num_retx_fail.attr,\n\n\t&dev_attr_tx_data_pkt_mcs_realtime.attr,\n\t&dev_attr_tx_data_pkt_fail_mcs_realtime.attr,\n\n\t&dev_attr_tx_mgmt_pkt_need_ack_num_total.attr,\n\t&dev_attr_tx_mgmt_pkt_need_ack_num_total_fail.attr,\n\n\t&dev_attr_tx_mgmt_pkt_need_ack_num_retx.attr,\n\t&dev_attr_tx_mgmt_pkt_need_ack_num_retx_fail.attr,\n\n\t&dev_attr_tx_mgmt_pkt_mcs_realtime.attr,\n\t&dev_attr_tx_mgmt_pkt_fail_mcs_realtime.attr,\n\n\t&dev_attr_rx_target_sender_mac_addr.attr,\n\t&dev_attr_rx_data_ok_agc_gain_value_realtime.attr,\n\t&dev_attr_rx_data_fail_agc_gain_value_realtime.attr,\n\t&dev_attr_rx_mgmt_ok_agc_gain_value_realtime.attr,\n\t&dev_attr_rx_mgmt_fail_agc_gain_value_realtime.attr,\n\t&dev_attr_rx_ack_ok_agc_gain_value_realtime.attr,\n\n\t&dev_attr_rx_monitor_all.attr,\n\t&dev_attr_rx_data_pkt_num_total.attr,\n\t&dev_attr_rx_data_pkt_num_fail.attr,\n\t&dev_attr_rx_mgmt_pkt_num_total.attr,\n\t&dev_attr_rx_mgmt_pkt_num_fail.attr,\n\t&dev_attr_rx_ack_pkt_num_total.attr,\n\t&dev_attr_rx_ack_pkt_num_fail.attr,\n\n\t&dev_attr_rx_data_pkt_mcs_realtime.attr,\n\t&dev_attr_rx_data_pkt_fail_mcs_realtime.attr,\n\t&dev_attr_rx_mgmt_pkt_mcs_realtime.attr,\n\t&dev_attr_rx_mgmt_pkt_fail_mcs_realtime.attr,\n\t&dev_attr_rx_ack_pkt_mcs_realtime.attr,\n\n\t&dev_attr_restrict_freq_mhz.attr,\n\n\t&dev_attr_csma_cfg0.attr,\n\t&dev_attr_cw_max_min_cfg.attr,\n\n\t&dev_attr_dbg_ch0.attr,\n\t&dev_attr_dbg_ch1.attr,\n\t&dev_attr_dbg_ch2.attr,\n\n\tNULL,\n};\nstatic const struct attribute_group stat_attribute_group = {\n\t.attrs = stat_attributes,\n};\n"
  },
  {
    "path": "driver/tx_intf/Makefile",
    "content": "# by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be\n\nobj-m += tx_intf.o\n\nall:\n\tmake -C $(KDIR) M=$(PWD) modules\n\t# ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-\n\nclean:\n\trm -f *.ko *.o *.mod.o *.mod.c *.symvers *.order\n"
  },
  {
    "path": "driver/tx_intf/tx_intf.c",
    "content": "/*\n * axi lite register access driver\n * Author: Xianjun Jiao, Michael Mehari, Wei Liu\n * SPDX-FileCopyrightText: 2019 UGent\n * SPDX-License-Identifier: AGPL-3.0-or-later\n*/\n\n#include <linux/bitops.h>\n#include <linux/dmapool.h>\n#include <linux/dma/xilinx_dma.h>\n#include <linux/init.h>\n#include <linux/interrupt.h>\n#include <linux/io.h>\n#include <linux/iopoll.h>\n#include <linux/module.h>\n#include <linux/of_address.h>\n#include <linux/of_dma.h>\n#include <linux/of_platform.h>\n#include <linux/of_irq.h>\n#include <linux/slab.h>\n#include <linux/clk.h>\n#include <linux/io-64-nonatomic-lo-hi.h>\n\n#include \"../hw_def.h\"\n\nstatic void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design\n\n/* IO accessors */\nstatic inline u32 reg_read(u32 reg)\n{\n  return ioread32(base_addr + reg);\n}\n\nstatic inline void reg_write(u32 reg, u32 value)\n{\n  iowrite32(value, base_addr + reg);\n}\n\nstatic inline u32 TX_INTF_REG_MULTI_RST_read(void){\n  return reg_read(TX_INTF_REG_MULTI_RST_ADDR);\n}\n\nstatic inline u32 TX_INTF_REG_ARBITRARY_IQ_read(void){\n  return reg_read(TX_INTF_REG_ARBITRARY_IQ_ADDR);\n}\n\nstatic inline u32 TX_INTF_REG_WIFI_TX_MODE_read(void){\n  return reg_read(TX_INTF_REG_WIFI_TX_MODE_ADDR);\n}\n\nstatic inline u32 TX_INTF_REG_CTS_TOSELF_CONFIG_read(void){\n  return reg_read(TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR);\n}\n\nstatic inline u32 TX_INTF_REG_CSI_FUZZER_read(void){\n  return reg_read(TX_INTF_REG_CSI_FUZZER_ADDR);\n}\n\nstatic inline u32 TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read(void){\n  return reg_read(TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_ADDR);\n}\n\nstatic inline u32 TX_INTF_REG_ARBITRARY_IQ_CTL_read(void){\n  return reg_read(TX_INTF_REG_ARBITRARY_IQ_CTL_ADDR);\n}\n\nstatic inline u32 TX_INTF_REG_TX_CONFIG_read(void){\n  return reg_read(TX_INTF_REG_TX_CONFIG_ADDR);\n}\n\nstatic inline u32 TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read(void){\n  return reg_read(TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR);\n}\n\nstatic inline u32 TX_INTF_REG_CFG_DATA_TO_ANT_read(void){\n  return reg_read(TX_INTF_REG_CFG_DATA_TO_ANT_ADDR);\n}\n\nstatic inline u32 TX_INTF_REG_S_AXIS_FIFO_TH_read(void){\n  return reg_read(TX_INTF_REG_S_AXIS_FIFO_TH_ADDR);\n}\n\nstatic inline u32 TX_INTF_REG_TX_HOLD_THRESHOLD_read(void){\n  return reg_read(TX_INTF_REG_TX_HOLD_THRESHOLD_ADDR);\n}\n\nstatic inline u32 TX_INTF_REG_INTERRUPT_SEL_read(void){\n  return reg_read(TX_INTF_REG_INTERRUPT_SEL_ADDR);\n}\n\nstatic inline u32 TX_INTF_REG_AMPDU_ACTION_CONFIG_read(void){\n  return reg_read(TX_INTF_REG_AMPDU_ACTION_CONFIG_ADDR);\n}\n\nstatic inline u32 TX_INTF_REG_BB_GAIN_read(void){\n  return reg_read(TX_INTF_REG_BB_GAIN_ADDR);\n}\n\nstatic inline u32 TX_INTF_REG_ANT_SEL_read(void){\n  return reg_read(TX_INTF_REG_ANT_SEL_ADDR);\n}\n\nstatic inline u32 TX_INTF_REG_PHY_HDR_CONFIG_read(void){\n  return reg_read(TX_INTF_REG_PHY_HDR_CONFIG_ADDR);\n}\n\nstatic inline u32 TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read(void){\n  return reg_read(TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_ADDR);\n}\n\nstatic inline u32 TX_INTF_REG_PKT_INFO1_read(void){\n  return reg_read(TX_INTF_REG_PKT_INFO1_ADDR);\n}\n\nstatic inline u32 TX_INTF_REG_PKT_INFO2_read(void){\n  return reg_read(TX_INTF_REG_PKT_INFO2_ADDR);\n}\n\nstatic inline u32 TX_INTF_REG_PKT_INFO3_read(void){\n  return reg_read(TX_INTF_REG_PKT_INFO3_ADDR);\n}\n\nstatic inline u32 TX_INTF_REG_PKT_INFO4_read(void){\n  return reg_read(TX_INTF_REG_PKT_INFO4_ADDR);\n}\n\nstatic inline u32 TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read(void){\n  return reg_read(TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_ADDR);\n}\n\n//--------------------------------------------------------\n\nstatic inline void TX_INTF_REG_MULTI_RST_write(u32 value){\n  reg_write(TX_INTF_REG_MULTI_RST_ADDR, value);\n}\n\nstatic inline void TX_INTF_REG_ARBITRARY_IQ_write(u32 value){\n  reg_write(TX_INTF_REG_ARBITRARY_IQ_ADDR, value);\n}\n\nstatic inline void TX_INTF_REG_WIFI_TX_MODE_write(u32 value){\n  reg_write(TX_INTF_REG_WIFI_TX_MODE_ADDR, value);\n}\n\nstatic inline void TX_INTF_REG_CTS_TOSELF_CONFIG_write(u32 value){\n  reg_write(TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR, value);\n}\n\nstatic inline void TX_INTF_REG_CSI_FUZZER_write(u32 value){\n  reg_write(TX_INTF_REG_CSI_FUZZER_ADDR, value);\n}\n\nstatic inline void TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write(u32 value){\n  reg_write(TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_ADDR, value);\n}\n\nstatic inline void TX_INTF_REG_ARBITRARY_IQ_CTL_write(u32 value){\n  reg_write(TX_INTF_REG_ARBITRARY_IQ_CTL_ADDR, value);\n}\n\nstatic inline void TX_INTF_REG_TX_CONFIG_write(u32 value){\n  reg_write(TX_INTF_REG_TX_CONFIG_ADDR, value);\n}\n\nstatic inline void TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(u32 value){\n  reg_write(TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR, value);\n}\n\nstatic inline void TX_INTF_REG_CFG_DATA_TO_ANT_write(u32 value){\n  reg_write(TX_INTF_REG_CFG_DATA_TO_ANT_ADDR, value);\n}\n\nstatic inline void TX_INTF_REG_S_AXIS_FIFO_TH_write(u32 value){\n  reg_write(TX_INTF_REG_S_AXIS_FIFO_TH_ADDR, value);\n}\n\nstatic inline void TX_INTF_REG_TX_HOLD_THRESHOLD_write(u32 value){\n  reg_write(TX_INTF_REG_TX_HOLD_THRESHOLD_ADDR, value);\n}\n\nstatic inline void TX_INTF_REG_INTERRUPT_SEL_write(u32 value){\n  reg_write(TX_INTF_REG_INTERRUPT_SEL_ADDR, value);\n}\n\nstatic inline void TX_INTF_REG_AMPDU_ACTION_CONFIG_write(u32 value){\n  reg_write(TX_INTF_REG_AMPDU_ACTION_CONFIG_ADDR, value);\n}\n\nstatic inline void TX_INTF_REG_BB_GAIN_write(u32 value){\n  reg_write(TX_INTF_REG_BB_GAIN_ADDR, value);\n}\n\nstatic inline void TX_INTF_REG_ANT_SEL_write(u32 value){\n  reg_write(TX_INTF_REG_ANT_SEL_ADDR, value);\n}\n\nstatic inline void TX_INTF_REG_PHY_HDR_CONFIG_write(u32 value){\n  reg_write(TX_INTF_REG_PHY_HDR_CONFIG_ADDR, value);\n}\n\nstatic inline void TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write(u32 value){\n  reg_write(TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_ADDR, value);\n}\n\nstatic inline void TX_INTF_REG_PKT_INFO1_write(u32 value){\n  reg_write(TX_INTF_REG_PKT_INFO1_ADDR,value);\n}\n\nstatic inline void TX_INTF_REG_PKT_INFO2_write(u32 value){\n  reg_write(TX_INTF_REG_PKT_INFO2_ADDR,value);\n}\n\nstatic inline void TX_INTF_REG_PKT_INFO3_write(u32 value){\n  reg_write(TX_INTF_REG_PKT_INFO3_ADDR,value);\n}\n\nstatic inline void TX_INTF_REG_PKT_INFO4_write(u32 value){\n  reg_write(TX_INTF_REG_PKT_INFO4_ADDR,value);\n}\n\nstatic const struct of_device_id dev_of_ids[] = {\n  { .compatible = \"sdr,tx_intf\", },\n  {}\n};\nMODULE_DEVICE_TABLE(of, dev_of_ids);\n\nstatic struct tx_intf_driver_api tx_intf_driver_api_inst;\nstruct tx_intf_driver_api *tx_intf_api = &tx_intf_driver_api_inst;\nEXPORT_SYMBOL(tx_intf_api);\n\nstatic inline u32 hw_init(enum tx_intf_mode mode, u32 tx_config, u32 num_dma_symbol_to_ps, enum openwifi_fpga_type fpga_type){\n  int err=0, i;\n  u32 mixer_cfg=0, ant_sel=0;\n\n  printk(\"%s hw_init mode %d\\n\", tx_intf_compatible_str, mode);\n\n  //rst\n  for (i=0;i<8;i++)\n    tx_intf_api->TX_INTF_REG_MULTI_RST_write(0);\n  for (i=0;i<32;i++)\n    tx_intf_api->TX_INTF_REG_MULTI_RST_write(0xFFFFFFFF);\n  for (i=0;i<8;i++)\n    tx_intf_api->TX_INTF_REG_MULTI_RST_write(0);\n\n  if(fpga_type == LARGE_FPGA)  // LARGE FPGA: MAX_NUM_DMA_SYMBOL = 8192\n    // tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(8192-(210*5)); // threshold is for room to hold the last 4 packets from 4 queue before stop\n    tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(8192-(210*2));\n  else if(fpga_type == SMALL_FPGA)  // SMALL FPGA: MAX_NUM_DMA_SYMBOL = 4096\n    // tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(4096-(210*5)); // threshold is for room to hold the last 4 packets from 4 queue before stop\n    tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(4096-(210*2));\n\n  switch(mode)\n  {\n    case TX_INTF_AXIS_LOOP_BACK:\n      printk(\"%s hw_init mode TX_INTF_AXIS_LOOP_BACK\\n\", tx_intf_compatible_str);\n      break;\n\n    case TX_INTF_BW_20MHZ_AT_0MHZ_ANT0:\n      printk(\"%s hw_init mode TX_INTF_BW_20MHZ_AT_0MHZ_ANT0\\n\", tx_intf_compatible_str);\n      mixer_cfg = 0x2001F400;\n      ant_sel=1;\n      break;\n\n    case TX_INTF_BW_20MHZ_AT_0MHZ_ANT_BOTH:\n      printk(\"%s hw_init mode TX_INTF_BW_20MHZ_AT_0MHZ_ANT_BOTH\\n\", tx_intf_compatible_str);\n      mixer_cfg = 0x2001F400;\n      ant_sel=0x11;\n      break;\n\n    case TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0:\n      printk(\"%s hw_init mode TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0\\n\", tx_intf_compatible_str);\n      mixer_cfg = 0x2001F602;\n      ant_sel=1;\n      break;\n\n    case TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0:\n      printk(\"%s hw_init mode TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0\\n\", tx_intf_compatible_str);\n      mixer_cfg = 0x200202F6;\n      ant_sel=1;\n      break;\n\n    case TX_INTF_BW_20MHZ_AT_0MHZ_ANT1:\n      printk(\"%s hw_init mode TX_INTF_BW_20MHZ_AT_0MHZ_ANT1\\n\", tx_intf_compatible_str);\n      mixer_cfg = 0x2001F400;\n      ant_sel=2;\n      break;\n\n    case TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1:\n      printk(\"%s hw_init mode TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1\\n\", tx_intf_compatible_str);\n      mixer_cfg = 0x2001F602;\n      ant_sel=2;\n      break;\n\n    case TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1:\n      printk(\"%s hw_init mode TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1\\n\", tx_intf_compatible_str);\n      mixer_cfg = 0x200202F6;\n      ant_sel=2;\n      break;\n\n    case TX_INTF_BYPASS:\n      printk(\"%s hw_init mode TX_INTF_BYPASS\\n\", tx_intf_compatible_str);\n      mixer_cfg = 0x200202F6;\n      ant_sel=2;\n      break;\n    \n    default:\n      printk(\"%s hw_init mode %d is wrong!\\n\", tx_intf_compatible_str, mode);\n      err=1;\n  }\n\n  if (mode!=TX_INTF_AXIS_LOOP_BACK) {\n    tx_intf_api->TX_INTF_REG_MULTI_RST_write(0);\n    tx_intf_api->TX_INTF_REG_CSI_FUZZER_write(0);\n    tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write( ((16*10)<<16)|(16*10) );//high 16bit 5GHz; low 16 bit 2.4GHz. counter speed 10MHz is assumed\n  \n    // Remove TX_INTF_REG_TX_CONFIG_write to avoid hw_init call in openwifi_start causing inconsistency\n    // tx_intf_api->TX_INTF_REG_TX_CONFIG_write(tx_config);\n\n    tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(num_dma_symbol_to_ps);\n    tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write(0);\n    tx_intf_api->TX_INTF_REG_TX_HOLD_THRESHOLD_write(420);\n    tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write(0x4); //.src_sel(slv_reg14[2:0]), 0-s00_axis_tlast,1-ap_start,2-tx_start_from_acc,3-tx_end_from_acc,4-tx_try_complete from xpu\n    tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write(0x30004); //disable interrupt\n\n    // tx_intf_api->TX_INTF_REG_BB_GAIN_write(100); // value for old design with DUC (FIR + MIXER) -- obsolete due to DUC removal\n    // New test on new design (unified RF BB clock; No DUC)\n    // 5220MHz bb_gain power   EVM\n        //         400     -6dBm   -34/35\n        //         350     -7.2dBm -34/35/36\n        //         300     -8.5dBm -35/36/37 EVM\n\n        // 2437MHz bb_gain power    EVM\n        //         400     -3.2dBm -36/37\n        //         350     -4.4dBm -37/38/39\n        //         300     -5.7dBm -39/40\n        //         less    less    -40/41/42!\n\n    // According to above and more detailed test:\n    // Need to be 290. Otherwise some ofdm symbol's EVM jump high, when there are lots of ofdm symbols in one WiFi packet\n\n    // 2022-03-04 detailed test result:\n    // bb_gain 290 work for 11a/g all mcs\n    // bb_gain 290 work for 11n mcs 1~7 (aggr and non aggr)\n    // bb_gain 290 destroy  11n mcs 0 long (MTU 1500) tx pkt due to high PAPR (Peak to Average Power Ratio)!\n    // bb_gain 250 work for 11n mcs 0\n    // So, a conservative bb_gain 250 should be used\n    tx_intf_api->TX_INTF_REG_BB_GAIN_write(250);\n\n    // Remove TX_INTF_REG_ANT_SEL_write to avoid hw_init call in openwifi_start causing inconsistency\n    // tx_intf_api->TX_INTF_REG_ANT_SEL_write(ant_sel);\n\n    tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_write((1<<3)|(2<<4));\n    tx_intf_api->TX_INTF_REG_MULTI_RST_write(0x434);\n    tx_intf_api->TX_INTF_REG_MULTI_RST_write(0);\n  }\n\n  // if (mode == TX_INTF_BYPASS) {\n  //   tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write(0x100); //slv_reg10[8] -- bit 8 not used anymore. only bit0/1 are still reserved. \n  // }\n\n  printk(\"%s hw_init err %d\\n\", tx_intf_compatible_str, err);\n  return(err);\n}\n\nstatic int dev_probe(struct platform_device *pdev)\n{\n  struct device_node *np = pdev->dev.of_node;\n  struct resource *io;\n  int err=1;\n\n  printk(\"\\n\");\n\n  if (np) {\n    const struct of_device_id *match;\n\n    match = of_match_node(dev_of_ids, np);\n    if (match) {\n      printk(\"%s dev_probe match!\\n\", tx_intf_compatible_str);\n      err = 0;\n    }\n  }\n\n  if (err)\n    return err;\n\n  tx_intf_api->hw_init=hw_init;\n\n  tx_intf_api->reg_read=reg_read;\n  tx_intf_api->reg_write=reg_write;\n\n  tx_intf_api->TX_INTF_REG_MULTI_RST_read=TX_INTF_REG_MULTI_RST_read;\n  tx_intf_api->TX_INTF_REG_ARBITRARY_IQ_read=TX_INTF_REG_ARBITRARY_IQ_read;\n  tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_read=TX_INTF_REG_WIFI_TX_MODE_read;\n  tx_intf_api->TX_INTF_REG_CTS_TOSELF_CONFIG_read=TX_INTF_REG_CTS_TOSELF_CONFIG_read;\n  tx_intf_api->TX_INTF_REG_CSI_FUZZER_read=TX_INTF_REG_CSI_FUZZER_read;\n  tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read=TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read;\n  tx_intf_api->TX_INTF_REG_ARBITRARY_IQ_CTL_read=TX_INTF_REG_ARBITRARY_IQ_CTL_read;\n  tx_intf_api->TX_INTF_REG_TX_CONFIG_read=TX_INTF_REG_TX_CONFIG_read;\n  tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read;\n  tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_read=TX_INTF_REG_CFG_DATA_TO_ANT_read;\n  tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_read=TX_INTF_REG_S_AXIS_FIFO_TH_read;\n  tx_intf_api->TX_INTF_REG_TX_HOLD_THRESHOLD_read=TX_INTF_REG_TX_HOLD_THRESHOLD_read;\n  tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_read=TX_INTF_REG_INTERRUPT_SEL_read;\n  tx_intf_api->TX_INTF_REG_AMPDU_ACTION_CONFIG_read=TX_INTF_REG_AMPDU_ACTION_CONFIG_read;\n  tx_intf_api->TX_INTF_REG_BB_GAIN_read=TX_INTF_REG_BB_GAIN_read;\n  tx_intf_api->TX_INTF_REG_ANT_SEL_read=TX_INTF_REG_ANT_SEL_read;\n  tx_intf_api->TX_INTF_REG_PHY_HDR_CONFIG_read=TX_INTF_REG_PHY_HDR_CONFIG_read;\n  tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read=TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read;\n  tx_intf_api->TX_INTF_REG_PKT_INFO1_read=TX_INTF_REG_PKT_INFO1_read;\n  tx_intf_api->TX_INTF_REG_PKT_INFO2_read=TX_INTF_REG_PKT_INFO2_read;\n  tx_intf_api->TX_INTF_REG_PKT_INFO3_read=TX_INTF_REG_PKT_INFO3_read;\n  tx_intf_api->TX_INTF_REG_PKT_INFO4_read=TX_INTF_REG_PKT_INFO4_read;\n  tx_intf_api->TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read=TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read;\n\n  tx_intf_api->TX_INTF_REG_MULTI_RST_write=TX_INTF_REG_MULTI_RST_write;\n  tx_intf_api->TX_INTF_REG_ARBITRARY_IQ_write=TX_INTF_REG_ARBITRARY_IQ_write;\n  tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_write=TX_INTF_REG_WIFI_TX_MODE_write;\n  tx_intf_api->TX_INTF_REG_CTS_TOSELF_CONFIG_write=TX_INTF_REG_CTS_TOSELF_CONFIG_write;\n  tx_intf_api->TX_INTF_REG_CSI_FUZZER_write=TX_INTF_REG_CSI_FUZZER_write;\n  tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write=TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write;\n  tx_intf_api->TX_INTF_REG_ARBITRARY_IQ_CTL_write=TX_INTF_REG_ARBITRARY_IQ_CTL_write;\n  tx_intf_api->TX_INTF_REG_TX_CONFIG_write=TX_INTF_REG_TX_CONFIG_write;\n  tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write;\n  tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write=TX_INTF_REG_CFG_DATA_TO_ANT_write;\n  tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write=TX_INTF_REG_S_AXIS_FIFO_TH_write;\n  tx_intf_api->TX_INTF_REG_TX_HOLD_THRESHOLD_write=TX_INTF_REG_TX_HOLD_THRESHOLD_write;\n  tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write=TX_INTF_REG_INTERRUPT_SEL_write;\n  tx_intf_api->TX_INTF_REG_AMPDU_ACTION_CONFIG_write=TX_INTF_REG_AMPDU_ACTION_CONFIG_write;\n  tx_intf_api->TX_INTF_REG_BB_GAIN_write=TX_INTF_REG_BB_GAIN_write;\n  tx_intf_api->TX_INTF_REG_ANT_SEL_write=TX_INTF_REG_ANT_SEL_write;\n  tx_intf_api->TX_INTF_REG_PHY_HDR_CONFIG_write=TX_INTF_REG_PHY_HDR_CONFIG_write;\n  tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write=TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write;\n  tx_intf_api->TX_INTF_REG_PKT_INFO1_write=TX_INTF_REG_PKT_INFO1_write;\n  tx_intf_api->TX_INTF_REG_PKT_INFO2_write=TX_INTF_REG_PKT_INFO2_write;\n  tx_intf_api->TX_INTF_REG_PKT_INFO3_write=TX_INTF_REG_PKT_INFO3_write;\n  tx_intf_api->TX_INTF_REG_PKT_INFO4_write=TX_INTF_REG_PKT_INFO4_write;\n\n  /* Request and map I/O memory */\n  io = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n  base_addr = devm_ioremap_resource(&pdev->dev, io);\n  if (IS_ERR(base_addr))\n    return PTR_ERR(base_addr);\n\n  printk(\"%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\\n\", tx_intf_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc);\n  printk(\"%s dev_probe base_addr 0x%p\\n\", tx_intf_compatible_str,(void*)base_addr);\n  printk(\"%s dev_probe tx_intf_driver_api_inst 0x%p\\n\", tx_intf_compatible_str, (void*)(&tx_intf_driver_api_inst) );\n  printk(\"%s dev_probe             tx_intf_api 0x%p\\n\", tx_intf_compatible_str, (void*)tx_intf_api);\n\n  printk(\"%s dev_probe succeed!\\n\", tx_intf_compatible_str);\n\n  //err = hw_init(TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1, 8, 8, SMALL_FPGA);\n  //err = hw_init(TX_INTF_BYPASS, 8, 8, SMALL_FPGA);\n  err = hw_init(TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1, 8, 8, SMALL_FPGA); // make sure dac is connected to original ad9361 dma\n\n  return err;\n}\n\nstatic int dev_remove(struct platform_device *pdev)\n{\n  printk(\"\\n\");\n\n  printk(\"%s dev_remove base_addr 0x%p\\n\", tx_intf_compatible_str,(void*)base_addr);\n  printk(\"%s dev_remove tx_intf_driver_api_inst 0x%p\\n\", tx_intf_compatible_str, (void*)(&tx_intf_driver_api_inst) );\n  printk(\"%s dev_remove             tx_intf_api 0x%p\\n\", tx_intf_compatible_str, (void*)tx_intf_api);\n\n  printk(\"%s dev_remove succeed!\\n\", tx_intf_compatible_str);\n  return 0;\n}\n\nstatic struct platform_driver dev_driver = {\n  .driver = {\n    .name = \"sdr,tx_intf\",\n    .owner = THIS_MODULE,\n    .of_match_table = dev_of_ids,\n  },\n  .probe = dev_probe,\n  .remove = dev_remove,\n};\n\nmodule_platform_driver(dev_driver);\n\nMODULE_AUTHOR(\"Xianjun Jiao\");\nMODULE_DESCRIPTION(\"sdr,tx_intf\");\nMODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "driver/xilinx_dma/README.md",
    "content": "<!--\nAuthor: Xianjun Jiao\nSPDX-FileCopyrightText: 2021 UGent\nSPDX-License-Identifier: AGPL-3.0-or-later\n-->\nWe don't maintain our own (modified) xilinx dma driver anymore! The original xilinx dma driver in the Linux kernel tree can be used.\n\n===============Following are obsolete content=================\n\nCurrently used driver xilinx_dma-orig.c is based on 552d3f11e374ca0d435aa93a571507819eabdda2 of https://github.com/Xilinx/linux-xlnx )\n\ninstruction to generate our customized xilinx dma driver:\n\n./make_xilinx_dma.sh\n\ninstruction to generate our customized xilinx dma test program:\n\n./make_xilinx_dma_test.sh\n\ntest dma driver on board: login to zc706, then:\n\n    rm axidmatest.ko\n    wget ftp://192.168.10.1/driver/xilinx_dma/axidmatest.ko\n    rm ddc.ko\n    wget ftp://192.168.10.1/driver/ddc/ddc.ko\n    rm xilinx_dma.ko\n    wget ftp://192.168.10.1/driver/xilinx_dma/xilinx_dma.ko\n    rmmod axidmatest\n    rmmod ddc\n    rmmod xilinx_dma\n    insmod xilinx_dma.ko\n    insmod ddc.ko\n    insmod axidmatest.ko\n    dmesg -c\n\ndmesg will show test result printed by \"insmod axidmatest.ko\". Like this:\n\n    root@analog:~#     dmesg -c\n    xilinx_dmatest: dropped channel dma5chan0\n    xilinx_dmatest: dropped channel dma5chan1\n\n    sdr,ddc dev_remove base_addr 0xf14e0000\n    sdr,ddc dev_remove ddc_driver_api_inst 0xbf032284\n    sdr,ddc dev_remove             ddc_api 0xbf032284\n    sdr,ddc dev_remove succeed!\n    xilinx-vdma 43000000.axivdma: Xilinx AXI VDMA Engine Driver Probed!!\n    xilinx-vdma 80400000.dma: Xilinx AXI DMA Engine Driver Probed!!\n    xilinx-vdma 80410000.dma: Xilinx AXI DMA Engine Driver Probed!!\n\n    sdr,ddc dev_probe match!\n    sdr,ddc dev_probe io start 0x83c20000 end 0x83c2ffff name /fpga-axi@0/rx_intf@83c20000 flags 0x00000200 desc 0x00000000\n    sdr,ddc dev_probe base_addr 0xf18e0000\n    sdr,ddc dev_probe ddc_driver_api_inst 0xbf0e1284\n    sdr,ddc dev_probe             ddc_api 0xbf0e1284\n    sdr,ddc dev_probe reset tsf timer\n    sdr,ddc dev_probe tsf timer runtime read 1 33007 100015us\n    sdr,ddc dev_probe succeed!\n    sdr,ddc hw_init mode 0\n    sdr,ddc hw_init mode DDC_AXIS_LOOP_BACK\n    sdr,ddc hw_init err 0\n    dmatest: Started 1 threads using dma5chan0 dma5chan1\n    align 3\n    sdr,ddc hw_init mode 0\n    sdr,ddc hw_init mode DDC_AXIS_LOOP_BACK\n    sdr,ddc hw_init err 0\n    tx_tmo 99 status 0 len 6448 DMA_COMPLETE 0\n    dma5chan0-dma5c: verifying source buffer...\n    dma5chan0-dma5c: verifying dest buffer...\n    dma5chan0-dma5c: #0: No errors with \n    src_off=0x448 dst_off=0x568 len=0x1930\n    align 3\n    sdr,ddc hw_init mode 0\n    sdr,ddc hw_init mode DDC_AXIS_LOOP_BACK\n    sdr,ddc hw_init err 0\n    tx_tmo 100 status 0 len 3248 DMA_COMPLETE 0\n    dma5chan0-dma5c: verifying source buffer...\n    dma5chan0-dma5c: verifying dest buffer...\n    dma5chan0-dma5c: #1: No errors with \n    src_off=0x458 dst_off=0xf08 len=0xcb0\n    align 3\n    sdr,ddc hw_init mode 0\n    sdr,ddc hw_init mode DDC_AXIS_LOOP_BACK\n    sdr,ddc hw_init err 0\n    tx_tmo 100 status 0 len 8112 DMA_COMPLETE 0\n    dma5chan0-dma5c: verifying source buffer...\n    dma5chan0-dma5c: verifying dest buffer...\n    dma5chan0-dma5c: #2: No errors with \n    src_off=0x10 dst_off=0x20 len=0x1fb0\n    align 3\n    sdr,ddc hw_init mode 0\n    sdr,ddc hw_init mode DDC_AXIS_LOOP_BACK\n    sdr,ddc hw_init err 0\n    tx_tmo 100 status 0 len 840 DMA_COMPLETE 0\n    dma5chan0-dma5c: verifying source buffer...\n    dma5chan0-dma5c: verifying dest buffer...\n    dma5chan0-dma5c: #3: No errors with \n    src_off=0x1890 dst_off=0x1268 len=0x348\n    align 3\n    sdr,ddc hw_init mode 0\n    sdr,ddc hw_init mode DDC_AXIS_LOOP_BACK\n    sdr,ddc hw_init err 0\n    tx_tmo 100 status 0 len 7816 DMA_COMPLETE 0\n    dma5chan0-dma5c: verifying source buffer...\n    dma5chan0-dma5c: verifying dest buffer...\n    dma5chan0-dma5c: #4: No errors with \n    src_off=0x80 dst_off=0x168 len=0x1e88\n    dma5chan0-dma5c: terminating after 5 tests, 0 failures (status 0)\n\n"
  },
  {
    "path": "driver/xilinx_dma/make_xilinx_dma.sh",
    "content": "#!/bin/bash\n\n# Author: Xianjun Jiao\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\nif [ \"$#\" -ne 2 ]; then\n    echo \"You must enter exactly 2 arguments: \\$XILINX_DIR \\$ARCH(32 or 64)\"\n    exit 1\nfi\n\nWORKDIR=$PWD\nOPENWIFI_DIR=$(pwd)/../../\nXILINX_DIR=$1\nARCH_OPTION=$2\n\nset -x\n\nif [ -f \"$OPENWIFI_DIR/LICENSE\" ]; then\n    echo \"\\$OPENWIFI_DIR is found!\"\nelse\n    echo \"\\$OPENWIFI_DIR is not correct. Please check!\"\n    exit 1\nfi\n\nif [ -d \"$XILINX_DIR/SDK\" ]; then\n    echo \"\\$XILINX_DIR is found!\"\nelse\n    echo \"\\$XILINX_DIR is not correct. Please check!\"\n    exit 1\nfi\n\nif [ \"$ARCH_OPTION\" != \"32\" ] && [ \"$ARCH_OPTION\" != \"64\" ]; then\n    echo \"\\$ARCH_OPTION is not correct. Should be 32 or 64. Please check!\"\n    exit 1\nelse\n    echo \"\\$ARCH_OPTION is valid!\"\nfi\n\nsource $XILINX_DIR/SDK/2018.3/settings64.sh\nif [ \"$ARCH_OPTION\" == \"64\" ]; then\n    KDIR=$OPENWIFI_DIR/adi-linux-64/\n    export ARCH=arm64\n    export CROSS_COMPILE=aarch64-linux-gnu-\nelse\n    KDIR=$OPENWIFI_DIR/adi-linux/\n    export ARCH=arm\n    export CROSS_COMPILE=arm-linux-gnueabihf-\nfi\n\nSUBMODULE=xilinx_dma\n\ncp $KDIR/drivers/dma/xilinx/xilinx_dma.c $KDIR/drivers/dma/xilinx/xilinx_dma.c.bak\ncp xilinx_dma.c $KDIR/drivers/dma/xilinx -rf\ncd $KDIR\nmake $KDIR/drivers/dma/xilinx/$SUBMODULE.ko\ncp $KDIR/drivers/dma/xilinx/$SUBMODULE.ko $WORKDIR -rf\n# cp $KDIR/drivers/dma/xilinx/xilinx_dma.c.bak $KDIR/drivers/dma/xilinx/xilinx_dma.c\ncd $WORKDIR\nls $SUBMODULE.ko\n"
  },
  {
    "path": "driver/xilinx_dma/xilinx_dma.c",
    "content": "/*\n * DMA driver for Xilinx Video DMA Engine\n * SPDX-FileCopyrightText: Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved\n * Based on the Freescale DMA driver\n * Modified by Xianjun Jiao\n * SPDX-License-Identifier: GPL-2.0-or-later\n * \n * Description:\n * The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP\n * core that provides high-bandwidth direct memory access between memory\n * and AXI4-Stream type video target peripherals. The core provides efficient\n * two dimensional DMA operations with independent asynchronous read (S2MM)\n * and write (MM2S) channel operation. It can be configured to have either\n * one channel or two channels. If configured as two channels, one is to\n * transmit to the video device (MM2S) and another is to receive from the\n * video device (S2MM). Initialization, status, interrupt and management\n * registers are accessed through an AXI4-Lite slave interface.\n *\n * The AXI Direct Memory Access (AXI DMA) core is a soft Xilinx IP core that\n * provides high-bandwidth one dimensional direct memory access between memory\n * and AXI4-Stream target peripherals. It supports one receive and one\n * transmit channel, both of them optional at synthesis time.\n *\n * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory\n * Access (DMA) between a memory-mapped source address and a memory-mapped\n * destination address.\n *\n * This program is free software: you can redistribute it and/or modify\n * it under the terms of the GNU General Public License as published by\n * the Free Software Foundation, either version 2 of the License, or\n * (at your option) any later version.\n */\n\n#include <linux/bitops.h>\n#include <linux/dmapool.h>\n#include <linux/dma/xilinx_dma.h>\n#include <linux/init.h>\n#include <linux/interrupt.h>\n#include <linux/io.h>\n#include <linux/iopoll.h>\n#include <linux/module.h>\n#include <linux/of_address.h>\n#include <linux/of_dma.h>\n#include <linux/of_platform.h>\n#include <linux/of_irq.h>\n#include <linux/slab.h>\n#include <linux/clk.h>\n#include <linux/io-64-nonatomic-lo-hi.h>\n\n#include \"../dmaengine.h\"\n\n/* Register/Descriptor Offsets */\n#define XILINX_DMA_MM2S_CTRL_OFFSET\t\t0x0000\n#define XILINX_DMA_S2MM_CTRL_OFFSET\t\t0x0030\n#define XILINX_VDMA_MM2S_DESC_OFFSET\t\t0x0050\n#define XILINX_VDMA_S2MM_DESC_OFFSET\t\t0x00a0\n\n/* Control Registers */\n#define XILINX_DMA_REG_DMACR\t\t\t0x0000\n#define XILINX_DMA_DMACR_DELAY_MAX\t\t0xff\n#define XILINX_DMA_DMACR_DELAY_SHIFT\t\t24\n#define XILINX_DMA_DMACR_FRAME_COUNT_MAX\t0xff\n#define XILINX_DMA_DMACR_FRAME_COUNT_SHIFT\t16\n#define XILINX_DMA_DMACR_ERR_IRQ\t\tBIT(14)\n#define XILINX_DMA_DMACR_DLY_CNT_IRQ\t\tBIT(13)\n#define XILINX_DMA_DMACR_FRM_CNT_IRQ\t\tBIT(12)\n#define XILINX_DMA_DMACR_MASTER_SHIFT\t\t8\n#define XILINX_DMA_DMACR_FSYNCSRC_SHIFT\t5\n#define XILINX_DMA_DMACR_FRAMECNT_EN\t\tBIT(4)\n#define XILINX_DMA_DMACR_GENLOCK_EN\t\tBIT(3)\n#define XILINX_DMA_DMACR_RESET\t\t\tBIT(2)\n#define XILINX_DMA_DMACR_CIRC_EN\t\tBIT(1)\n#define XILINX_DMA_DMACR_RUNSTOP\t\tBIT(0)\n#define XILINX_DMA_DMACR_FSYNCSRC_MASK\t\tGENMASK(6, 5)\n\n#define XILINX_DMA_REG_DMASR\t\t\t0x0004\n#define XILINX_DMA_DMASR_EOL_LATE_ERR\t\tBIT(15)\n#define XILINX_DMA_DMASR_ERR_IRQ\t\tBIT(14)\n#define XILINX_DMA_DMASR_DLY_CNT_IRQ\t\tBIT(13)\n#define XILINX_DMA_DMASR_FRM_CNT_IRQ\t\tBIT(12)\n#define XILINX_DMA_DMASR_SOF_LATE_ERR\t\tBIT(11)\n#define XILINX_DMA_DMASR_SG_DEC_ERR\t\tBIT(10)\n#define XILINX_DMA_DMASR_SG_SLV_ERR\t\tBIT(9)\n#define XILINX_DMA_DMASR_EOF_EARLY_ERR\t\tBIT(8)\n#define XILINX_DMA_DMASR_SOF_EARLY_ERR\t\tBIT(7)\n#define XILINX_DMA_DMASR_DMA_DEC_ERR\t\tBIT(6)\n#define XILINX_DMA_DMASR_DMA_SLAVE_ERR\t\tBIT(5)\n#define XILINX_DMA_DMASR_DMA_INT_ERR\t\tBIT(4)\n#define XILINX_DMA_DMASR_IDLE\t\t\tBIT(1)\n#define XILINX_DMA_DMASR_HALTED\t\tBIT(0)\n#define XILINX_DMA_DMASR_DELAY_MASK\t\tGENMASK(31, 24)\n#define XILINX_DMA_DMASR_FRAME_COUNT_MASK\tGENMASK(23, 16)\n\n#define XILINX_DMA_REG_CURDESC\t\t\t0x0008\n#define XILINX_DMA_REG_TAILDESC\t\t0x0010\n#define XILINX_DMA_REG_REG_INDEX\t\t0x0014\n#define XILINX_DMA_REG_FRMSTORE\t\t0x0018\n#define XILINX_DMA_REG_THRESHOLD\t\t0x001c\n#define XILINX_DMA_REG_FRMPTR_STS\t\t0x0024\n#define XILINX_DMA_REG_PARK_PTR\t\t0x0028\n#define XILINX_DMA_PARK_PTR_WR_REF_SHIFT\t8\n#define XILINX_DMA_PARK_PTR_WR_REF_MASK\t\tGENMASK(12, 8)\n#define XILINX_DMA_PARK_PTR_RD_REF_SHIFT\t0\n#define XILINX_DMA_PARK_PTR_RD_REF_MASK\t\tGENMASK(4, 0)\n#define XILINX_DMA_REG_VDMA_VERSION\t\t0x002c\n\n/* Register Direct Mode Registers */\n#define XILINX_DMA_REG_VSIZE\t\t\t0x0000\n#define XILINX_DMA_REG_HSIZE\t\t\t0x0004\n\n#define XILINX_DMA_REG_FRMDLY_STRIDE\t\t0x0008\n#define XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT\t24\n#define XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT\t0\n\n#define XILINX_VDMA_REG_START_ADDRESS(n)\t(0x000c + 4 * (n))\n#define XILINX_VDMA_REG_START_ADDRESS_64(n)\t(0x000c + 8 * (n))\n\n#define XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP\t0x00ec\n#define XILINX_VDMA_ENABLE_VERTICAL_FLIP\tBIT(0)\n\n/* HW specific definitions */\n#define XILINX_DMA_MAX_CHANS_PER_DEVICE\t0x20\n\n#define XILINX_DMA_DMAXR_ALL_IRQ_MASK\t\\\n\t\t(XILINX_DMA_DMASR_FRM_CNT_IRQ | \\\n\t\t XILINX_DMA_DMASR_DLY_CNT_IRQ | \\\n\t\t XILINX_DMA_DMASR_ERR_IRQ)\n\n#define XILINX_DMA_DMASR_ALL_ERR_MASK\t\\\n\t\t(XILINX_DMA_DMASR_EOL_LATE_ERR | \\\n\t\t XILINX_DMA_DMASR_SOF_LATE_ERR | \\\n\t\t XILINX_DMA_DMASR_SG_DEC_ERR | \\\n\t\t XILINX_DMA_DMASR_SG_SLV_ERR | \\\n\t\t XILINX_DMA_DMASR_EOF_EARLY_ERR | \\\n\t\t XILINX_DMA_DMASR_SOF_EARLY_ERR | \\\n\t\t XILINX_DMA_DMASR_DMA_DEC_ERR | \\\n\t\t XILINX_DMA_DMASR_DMA_SLAVE_ERR | \\\n\t\t XILINX_DMA_DMASR_DMA_INT_ERR)\n\n/*\n * Recoverable errors are DMA Internal error, SOF Early, EOF Early\n * and SOF Late. They are only recoverable when C_FLUSH_ON_FSYNC\n * is enabled in the h/w system.\n */\n#define XILINX_DMA_DMASR_ERR_RECOVER_MASK\t\\\n\t\t(XILINX_DMA_DMASR_SOF_LATE_ERR | \\\n\t\t XILINX_DMA_DMASR_EOF_EARLY_ERR | \\\n\t\t XILINX_DMA_DMASR_SOF_EARLY_ERR | \\\n\t\t XILINX_DMA_DMASR_DMA_INT_ERR)\n\n/* Axi VDMA Flush on Fsync bits */\n#define XILINX_DMA_FLUSH_S2MM\t\t3\n#define XILINX_DMA_FLUSH_MM2S\t\t2\n#define XILINX_DMA_FLUSH_BOTH\t\t1\n\n/* Delay loop counter to prevent hardware failure */\n#define XILINX_DMA_LOOP_COUNT\t\t1000000\n\n/* AXI DMA Specific Registers/Offsets */\n#define XILINX_DMA_REG_SRCDSTADDR\t0x18\n#define XILINX_DMA_REG_BTT\t\t0x28\n\n/* AXI DMA Specific Masks/Bit fields */\n#define XILINX_DMA_MAX_TRANS_LEN_MIN\t8\n#define XILINX_DMA_MAX_TRANS_LEN_MAX\t23\n#define XILINX_DMA_V2_MAX_TRANS_LEN_MAX\t26\n#define XILINX_DMA_CR_COALESCE_MAX\tGENMASK(23, 16)\n#define XILINX_DMA_CR_CYCLIC_BD_EN_MASK\tBIT(4)\n#define XILINX_DMA_CR_COALESCE_SHIFT\t16\n#define XILINX_DMA_BD_SOP\t\tBIT(27)\n#define XILINX_DMA_BD_EOP\t\tBIT(26)\n#define XILINX_DMA_COALESCE_MAX\t\t255\n#define XILINX_DMA_NUM_DESCS\t\t255\n#define XILINX_DMA_NUM_APP_WORDS\t5\n\n/* Multi-Channel DMA Descriptor offsets*/\n#define XILINX_DMA_MCRX_CDESC(x)\t(0x40 + (x-1) * 0x20)\n#define XILINX_DMA_MCRX_TDESC(x)\t(0x48 + (x-1) * 0x20)\n\n/* Multi-Channel DMA Masks/Shifts */\n#define XILINX_DMA_BD_HSIZE_MASK\tGENMASK(15, 0)\n#define XILINX_DMA_BD_STRIDE_MASK\tGENMASK(15, 0)\n#define XILINX_DMA_BD_VSIZE_MASK\tGENMASK(31, 19)\n#define XILINX_DMA_BD_TDEST_MASK\tGENMASK(4, 0)\n#define XILINX_DMA_BD_STRIDE_SHIFT\t0\n#define XILINX_DMA_BD_VSIZE_SHIFT\t19\n\n/* AXI CDMA Specific Registers/Offsets */\n#define XILINX_CDMA_REG_SRCADDR\t\t0x18\n#define XILINX_CDMA_REG_DSTADDR\t\t0x20\n\n/* AXI CDMA Specific Masks */\n#define XILINX_CDMA_CR_SGMODE          BIT(3)\n\n/**\n * struct xilinx_vdma_desc_hw - Hardware Descriptor\n * @next_desc: Next Descriptor Pointer @0x00\n * @pad1: Reserved @0x04\n * @buf_addr: Buffer address @0x08\n * @buf_addr_msb: MSB of Buffer address @0x0C\n * @vsize: Vertical Size @0x10\n * @hsize: Horizontal Size @0x14\n * @stride: Number of bytes between the first\n *\t    pixels of each horizontal line @0x18\n */\nstruct xilinx_vdma_desc_hw {\n\tu32 next_desc;\n\tu32 pad1;\n\tu32 buf_addr;\n\tu32 buf_addr_msb;\n\tu32 vsize;\n\tu32 hsize;\n\tu32 stride;\n} __aligned(64);\n\n/**\n * struct xilinx_axidma_desc_hw - Hardware Descriptor for AXI DMA\n * @next_desc: Next Descriptor Pointer @0x00\n * @next_desc_msb: MSB of Next Descriptor Pointer @0x04\n * @buf_addr: Buffer address @0x08\n * @buf_addr_msb: MSB of Buffer address @0x0C\n * @mcdma_control: Control field for mcdma @0x10\n * @vsize_stride: Vsize and Stride field for mcdma @0x14\n * @control: Control field @0x18\n * @status: Status field @0x1C\n * @app: APP Fields @0x20 - 0x30\n */\nstruct xilinx_axidma_desc_hw {\n\tu32 next_desc;\n\tu32 next_desc_msb;\n\tu32 buf_addr;\n\tu32 buf_addr_msb;\n\tu32 mcdma_control;\n\tu32 vsize_stride;\n\tu32 control;\n\tu32 status;\n\tu32 app[XILINX_DMA_NUM_APP_WORDS];\n} __aligned(64);\n\n/**\n * struct xilinx_cdma_desc_hw - Hardware Descriptor\n * @next_desc: Next Descriptor Pointer @0x00\n * @next_desc_msb: Next Descriptor Pointer MSB @0x04\n * @src_addr: Source address @0x08\n * @src_addr_msb: Source address MSB @0x0C\n * @dest_addr: Destination address @0x10\n * @dest_addr_msb: Destination address MSB @0x14\n * @control: Control field @0x18\n * @status: Status field @0x1C\n */\nstruct xilinx_cdma_desc_hw {\n\tu32 next_desc;\n\tu32 next_desc_msb;\n\tu32 src_addr;\n\tu32 src_addr_msb;\n\tu32 dest_addr;\n\tu32 dest_addr_msb;\n\tu32 control;\n\tu32 status;\n} __aligned(64);\n\n/**\n * struct xilinx_vdma_tx_segment - Descriptor segment\n * @hw: Hardware descriptor\n * @node: Node in the descriptor segments list\n * @phys: Physical address of segment\n */\nstruct xilinx_vdma_tx_segment {\n\tstruct xilinx_vdma_desc_hw hw;\n\tstruct list_head node;\n\tdma_addr_t phys;\n} __aligned(64);\n\n/**\n * struct xilinx_axidma_tx_segment - Descriptor segment\n * @hw: Hardware descriptor\n * @node: Node in the descriptor segments list\n * @phys: Physical address of segment\n */\nstruct xilinx_axidma_tx_segment {\n\tstruct xilinx_axidma_desc_hw hw;\n\tstruct list_head node;\n\tdma_addr_t phys;\n} __aligned(64);\n\n/**\n * struct xilinx_cdma_tx_segment - Descriptor segment\n * @hw: Hardware descriptor\n * @node: Node in the descriptor segments list\n * @phys: Physical address of segment\n */\nstruct xilinx_cdma_tx_segment {\n\tstruct xilinx_cdma_desc_hw hw;\n\tstruct list_head node;\n\tdma_addr_t phys;\n} __aligned(64);\n\n/**\n * struct xilinx_dma_tx_descriptor - Per Transaction structure\n * @async_tx: Async transaction descriptor\n * @segments: TX segments list\n * @node: Node in the channel descriptors list\n * @cyclic: Check for cyclic transfers.\n */\nstruct xilinx_dma_tx_descriptor {\n\tstruct dma_async_tx_descriptor async_tx;\n\tstruct list_head segments;\n\tstruct list_head node;\n\tbool cyclic;\n};\n\n/**\n * struct xilinx_dma_chan - Driver specific DMA channel structure\n * @xdev: Driver specific device structure\n * @ctrl_offset: Control registers offset\n * @desc_offset: TX descriptor registers offset\n * @lock: Descriptor operation lock\n * @pending_list: Descriptors waiting\n * @active_list: Descriptors ready to submit\n * @done_list: Complete descriptors\n * @free_seg_list: Free descriptors\n * @common: DMA common channel\n * @desc_pool: Descriptors pool\n * @dev: The dma device\n * @irq: Channel IRQ\n * @id: Channel ID\n * @direction: Transfer direction\n * @num_frms: Number of frames\n * @has_sg: Support scatter transfers\n * @cyclic: Check for cyclic transfers.\n * @genlock: Support genlock mode\n * @err: Channel has errors\n * @idle: Check for channel idle\n * @tasklet: Cleanup work after irq\n * @config: Device configuration info\n * @flush_on_fsync: Flush on Frame sync\n * @desc_pendingcount: Descriptor pending count\n * @ext_addr: Indicates 64 bit addressing is supported by dma channel\n * @desc_submitcount: Descriptor h/w submitted count\n * @residue: Residue for AXI DMA\n * @seg_v: Statically allocated segments base\n * @seg_p: Physical allocated segments base\n * @cyclic_seg_v: Statically allocated segment base for cyclic transfers\n * @cyclic_seg_p: Physical allocated segments base for cyclic dma\n * @start_transfer: Differentiate b/w DMA IP's transfer\n * @stop_transfer: Differentiate b/w DMA IP's quiesce\n * @tdest: TDEST value for mcdma\n * @has_vflip: S2MM vertical flip\n */\nstruct xilinx_dma_chan {\n\tstruct xilinx_dma_device *xdev;\n\tu32 ctrl_offset;\n\tu32 desc_offset;\n\tspinlock_t lock;\n\tstruct list_head pending_list;\n\tstruct list_head active_list;\n\tstruct list_head done_list;\n\tstruct list_head free_seg_list;\n\tstruct dma_chan common;\n\tstruct dma_pool *desc_pool;\n\tstruct device *dev;\n\tint irq;\n\tint id;\n\tenum dma_transfer_direction direction;\n\tint num_frms;\n\tbool has_sg;\n\tbool cyclic;\n\tbool genlock;\n\tbool err;\n\tbool idle;\n\tstruct tasklet_struct tasklet;\n\tstruct xilinx_vdma_config config;\n\tbool flush_on_fsync;\n\tu32 desc_pendingcount;\n\tbool ext_addr;\n\tu32 desc_submitcount;\n\tu32 residue;\n\tstruct xilinx_axidma_tx_segment *seg_v;\n\tdma_addr_t seg_p;\n\tstruct xilinx_axidma_tx_segment *cyclic_seg_v;\n\tdma_addr_t cyclic_seg_p;\n\tvoid (*start_transfer)(struct xilinx_dma_chan *chan);\n\tint (*stop_transfer)(struct xilinx_dma_chan *chan);\n\tu16 tdest;\n\tbool has_vflip;\n\tu32 buf_idx; // each irq this value increase 1. in cyclic mode, we use residue return this idx via device_tx_status/xilinx_dma_tx_status\n};\n\n/**\n * enum xdma_ip_type - DMA IP type.\n *\n * @XDMA_TYPE_AXIDMA: Axi dma ip.\n * @XDMA_TYPE_CDMA: Axi cdma ip.\n * @XDMA_TYPE_VDMA: Axi vdma ip.\n *\n */\nenum xdma_ip_type {\n\tXDMA_TYPE_AXIDMA = 0,\n\tXDMA_TYPE_CDMA,\n\tXDMA_TYPE_VDMA,\n};\n\nstruct xilinx_dma_config {\n\tenum xdma_ip_type dmatype;\n\tint (*clk_init)(struct platform_device *pdev, struct clk **axi_clk,\n\t\t\tstruct clk **tx_clk, struct clk **txs_clk,\n\t\t\tstruct clk **rx_clk, struct clk **rxs_clk);\n};\n\n/**\n * struct xilinx_dma_device - DMA device structure\n * @regs: I/O mapped base address\n * @dev: Device Structure\n * @common: DMA device structure\n * @chan: Driver specific DMA channel\n * @has_sg: Specifies whether Scatter-Gather is present or not\n * @mcdma: Specifies whether Multi-Channel is present or not\n * @flush_on_fsync: Flush on frame sync\n * @ext_addr: Indicates 64 bit addressing is supported by dma device\n * @pdev: Platform device structure pointer\n * @dma_config: DMA config structure\n * @axi_clk: DMA Axi4-lite interface clock\n * @tx_clk: DMA mm2s clock\n * @txs_clk: DMA mm2s stream clock\n * @rx_clk: DMA s2mm clock\n * @rxs_clk: DMA s2mm stream clock\n * @nr_channels: Number of channels DMA device supports\n * @chan_id: DMA channel identifier\n * @max_buffer_len: Max buffer length\n */\nstruct xilinx_dma_device {\n\tvoid __iomem *regs;\n\tstruct device *dev;\n\tstruct dma_device common;\n\tstruct xilinx_dma_chan *chan[XILINX_DMA_MAX_CHANS_PER_DEVICE];\n\tbool has_sg;\n\tbool mcdma;\n\tu32 flush_on_fsync;\n\tbool ext_addr;\n\tstruct platform_device  *pdev;\n\tconst struct xilinx_dma_config *dma_config;\n\tstruct clk *axi_clk;\n\tstruct clk *tx_clk;\n\tstruct clk *txs_clk;\n\tstruct clk *rx_clk;\n\tstruct clk *rxs_clk;\n\tu32 nr_channels;\n\tu32 chan_id;\n\tu32 max_buffer_len;\n};\n\n/* Macros */\n#define to_xilinx_chan(chan) \\\n\tcontainer_of(chan, struct xilinx_dma_chan, common)\n#define to_dma_tx_descriptor(tx) \\\n\tcontainer_of(tx, struct xilinx_dma_tx_descriptor, async_tx)\n#define xilinx_dma_poll_timeout(chan, reg, val, cond, delay_us, timeout_us) \\\n\treadl_poll_timeout(chan->xdev->regs + chan->ctrl_offset + reg, val, \\\n\t\t\t   cond, delay_us, timeout_us)\n\n/* IO accessors */\nstatic inline u32 dma_read(struct xilinx_dma_chan *chan, u32 reg)\n{\n\treturn ioread32(chan->xdev->regs + reg);\n}\n\nstatic inline void dma_write(struct xilinx_dma_chan *chan, u32 reg, u32 value)\n{\n\tiowrite32(value, chan->xdev->regs + reg);\n}\n\nstatic inline void vdma_desc_write(struct xilinx_dma_chan *chan, u32 reg,\n\t\t\t\t   u32 value)\n{\n\tdma_write(chan, chan->desc_offset + reg, value);\n}\n\nstatic inline u32 dma_ctrl_read(struct xilinx_dma_chan *chan, u32 reg)\n{\n\treturn dma_read(chan, chan->ctrl_offset + reg);\n}\n\nstatic inline void dma_ctrl_write(struct xilinx_dma_chan *chan, u32 reg,\n\t\t\t\t   u32 value)\n{\n\tdma_write(chan, chan->ctrl_offset + reg, value);\n}\n\nstatic inline void dma_ctrl_clr(struct xilinx_dma_chan *chan, u32 reg,\n\t\t\t\t u32 clr)\n{\n\tdma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) & ~clr);\n}\n\nstatic inline void dma_ctrl_set(struct xilinx_dma_chan *chan, u32 reg,\n\t\t\t\t u32 set)\n{\n\tdma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) | set);\n}\n\n/**\n * vdma_desc_write_64 - 64-bit descriptor write\n * @chan: Driver specific VDMA channel\n * @reg: Register to write\n * @value_lsb: lower address of the descriptor.\n * @value_msb: upper address of the descriptor.\n *\n * Since vdma driver is trying to write to a register offset which is not a\n * multiple of 64 bits(ex : 0x5c), we are writing as two separate 32 bits\n * instead of a single 64 bit register write.\n */\nstatic inline void vdma_desc_write_64(struct xilinx_dma_chan *chan, u32 reg,\n\t\t\t\t      u32 value_lsb, u32 value_msb)\n{\n\t/* Write the lsb 32 bits*/\n\twritel(value_lsb, chan->xdev->regs + chan->desc_offset + reg);\n\n\t/* Write the msb 32 bits */\n\twritel(value_msb, chan->xdev->regs + chan->desc_offset + reg + 4);\n}\n\nstatic inline void dma_writeq(struct xilinx_dma_chan *chan, u32 reg, u64 value)\n{\n\tlo_hi_writeq(value, chan->xdev->regs + chan->ctrl_offset + reg);\n}\n\nstatic inline void xilinx_write(struct xilinx_dma_chan *chan, u32 reg,\n\t\t\t\tdma_addr_t addr)\n{\n\tif (chan->ext_addr)\n\t\tdma_writeq(chan, reg, addr);\n\telse\n\t\tdma_ctrl_write(chan, reg, addr);\n}\n\nstatic inline void xilinx_axidma_buf(struct xilinx_dma_chan *chan,\n\t\t\t\t     struct xilinx_axidma_desc_hw *hw,\n\t\t\t\t     dma_addr_t buf_addr, size_t sg_used,\n\t\t\t\t     size_t period_len)\n{\n\tif (chan->ext_addr) {\n\t\thw->buf_addr = lower_32_bits(buf_addr + sg_used + period_len);\n\t\thw->buf_addr_msb = upper_32_bits(buf_addr + sg_used +\n\t\t\t\t\t\t period_len);\n\t} else {\n\t\thw->buf_addr = buf_addr + sg_used + period_len;\n\t}\n}\n\n/* -----------------------------------------------------------------------------\n * Descriptors and segments alloc and free\n */\n\n/**\n * xilinx_vdma_alloc_tx_segment - Allocate transaction segment\n * @chan: Driver specific DMA channel\n *\n * Return: The allocated segment on success and NULL on failure.\n */\nstatic struct xilinx_vdma_tx_segment *\nxilinx_vdma_alloc_tx_segment(struct xilinx_dma_chan *chan)\n{\n\tstruct xilinx_vdma_tx_segment *segment;\n\tdma_addr_t phys;\n\n\tsegment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys);\n\tif (!segment)\n\t\treturn NULL;\n\n\tsegment->phys = phys;\n\n\treturn segment;\n}\n\n/**\n * xilinx_cdma_alloc_tx_segment - Allocate transaction segment\n * @chan: Driver specific DMA channel\n *\n * Return: The allocated segment on success and NULL on failure.\n */\nstatic struct xilinx_cdma_tx_segment *\nxilinx_cdma_alloc_tx_segment(struct xilinx_dma_chan *chan)\n{\n\tstruct xilinx_cdma_tx_segment *segment;\n\tdma_addr_t phys;\n\n\tsegment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys);\n\tif (!segment)\n\t\treturn NULL;\n\n\tsegment->phys = phys;\n\n\treturn segment;\n}\n\n/**\n * xilinx_axidma_alloc_tx_segment - Allocate transaction segment\n * @chan: Driver specific DMA channel\n *\n * Return: The allocated segment on success and NULL on failure.\n */\nstatic struct xilinx_axidma_tx_segment *\nxilinx_axidma_alloc_tx_segment(struct xilinx_dma_chan *chan)\n{\n\tstruct xilinx_axidma_tx_segment *segment = NULL;\n\tunsigned long flags;\n\n\tspin_lock_irqsave(&chan->lock, flags);\n\tif (!list_empty(&chan->free_seg_list)) {\n\t\tsegment = list_first_entry(&chan->free_seg_list,\n\t\t\t\t\t   struct xilinx_axidma_tx_segment,\n\t\t\t\t\t   node);\n\t\tlist_del(&segment->node);\n\t}\n\tspin_unlock_irqrestore(&chan->lock, flags);\n\n\treturn segment;\n}\n\nstatic void xilinx_dma_clean_hw_desc(struct xilinx_axidma_desc_hw *hw)\n{\n\tu32 next_desc = hw->next_desc;\n\tu32 next_desc_msb = hw->next_desc_msb;\n\n\tmemset(hw, 0, sizeof(struct xilinx_axidma_desc_hw));\n\n\thw->next_desc = next_desc;\n\thw->next_desc_msb = next_desc_msb;\n}\n\n/**\n * xilinx_dma_free_tx_segment - Free transaction segment\n * @chan: Driver specific DMA channel\n * @segment: DMA transaction segment\n */\nstatic void xilinx_dma_free_tx_segment(struct xilinx_dma_chan *chan,\n\t\t\t\tstruct xilinx_axidma_tx_segment *segment)\n{\n\txilinx_dma_clean_hw_desc(&segment->hw);\n\n\tlist_add_tail(&segment->node, &chan->free_seg_list);\n}\n\n/**\n * xilinx_cdma_free_tx_segment - Free transaction segment\n * @chan: Driver specific DMA channel\n * @segment: DMA transaction segment\n */\nstatic void xilinx_cdma_free_tx_segment(struct xilinx_dma_chan *chan,\n\t\t\t\tstruct xilinx_cdma_tx_segment *segment)\n{\n\tdma_pool_free(chan->desc_pool, segment, segment->phys);\n}\n\n/**\n * xilinx_vdma_free_tx_segment - Free transaction segment\n * @chan: Driver specific DMA channel\n * @segment: DMA transaction segment\n */\nstatic void xilinx_vdma_free_tx_segment(struct xilinx_dma_chan *chan,\n\t\t\t\t\tstruct xilinx_vdma_tx_segment *segment)\n{\n\tdma_pool_free(chan->desc_pool, segment, segment->phys);\n}\n\n/**\n * xilinx_dma_tx_descriptor - Allocate transaction descriptor\n * @chan: Driver specific DMA channel\n *\n * Return: The allocated descriptor on success and NULL on failure.\n */\nstatic struct xilinx_dma_tx_descriptor *\nxilinx_dma_alloc_tx_descriptor(struct xilinx_dma_chan *chan)\n{\n\tstruct xilinx_dma_tx_descriptor *desc;\n\n\tdesc = kzalloc(sizeof(*desc), GFP_KERNEL);\n\tif (!desc)\n\t\treturn NULL;\n\n\tINIT_LIST_HEAD(&desc->segments);\n\n\treturn desc;\n}\n\n/**\n * xilinx_dma_free_tx_descriptor - Free transaction descriptor\n * @chan: Driver specific DMA channel\n * @desc: DMA transaction descriptor\n */\nstatic void\nxilinx_dma_free_tx_descriptor(struct xilinx_dma_chan *chan,\n\t\t\t       struct xilinx_dma_tx_descriptor *desc)\n{\n\tstruct xilinx_vdma_tx_segment *segment, *next;\n\tstruct xilinx_cdma_tx_segment *cdma_segment, *cdma_next;\n\tstruct xilinx_axidma_tx_segment *axidma_segment, *axidma_next;\n\n\tif (!desc)\n\t\treturn;\n\n\tif (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {\n\t\tlist_for_each_entry_safe(segment, next, &desc->segments, node) {\n\t\t\tlist_del(&segment->node);\n\t\t\txilinx_vdma_free_tx_segment(chan, segment);\n\t\t}\n\t} else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {\n\t\tlist_for_each_entry_safe(cdma_segment, cdma_next,\n\t\t\t\t\t &desc->segments, node) {\n\t\t\tlist_del(&cdma_segment->node);\n\t\t\txilinx_cdma_free_tx_segment(chan, cdma_segment);\n\t\t}\n\t} else {\n\t\tlist_for_each_entry_safe(axidma_segment, axidma_next,\n\t\t\t\t\t &desc->segments, node) {\n\t\t\tlist_del(&axidma_segment->node);\n\t\t\txilinx_dma_free_tx_segment(chan, axidma_segment);\n\t\t}\n\t}\n\n\tkfree(desc);\n}\n\n/* Required functions */\n\n/**\n * xilinx_dma_free_desc_list - Free descriptors list\n * @chan: Driver specific DMA channel\n * @list: List to parse and delete the descriptor\n */\nstatic void xilinx_dma_free_desc_list(struct xilinx_dma_chan *chan,\n\t\t\t\t\tstruct list_head *list)\n{\n\tstruct xilinx_dma_tx_descriptor *desc, *next;\n\n\tlist_for_each_entry_safe(desc, next, list, node) {\n\t\tlist_del(&desc->node);\n\t\txilinx_dma_free_tx_descriptor(chan, desc);\n\t}\n}\n\n/**\n * xilinx_dma_free_descriptors - Free channel descriptors\n * @chan: Driver specific DMA channel\n */\nstatic void xilinx_dma_free_descriptors(struct xilinx_dma_chan *chan)\n{\n\tunsigned long flags;\n\n\tspin_lock_irqsave(&chan->lock, flags);\n\n\txilinx_dma_free_desc_list(chan, &chan->pending_list);\n\txilinx_dma_free_desc_list(chan, &chan->done_list);\n\txilinx_dma_free_desc_list(chan, &chan->active_list);\n\n\tspin_unlock_irqrestore(&chan->lock, flags);\n}\n\n/**\n * xilinx_dma_free_chan_resources - Free channel resources\n * @dchan: DMA channel\n */\nstatic void xilinx_dma_free_chan_resources(struct dma_chan *dchan)\n{\n\tstruct xilinx_dma_chan *chan = to_xilinx_chan(dchan);\n\tunsigned long flags;\n\n\tdev_dbg(chan->dev, \"Free all channel resources.\\n\");\n\n\txilinx_dma_free_descriptors(chan);\n\n\tif (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {\n\t\tspin_lock_irqsave(&chan->lock, flags);\n\t\tINIT_LIST_HEAD(&chan->free_seg_list);\n\t\tspin_unlock_irqrestore(&chan->lock, flags);\n\n\t\t/* Free memory that is allocated for BD */\n\t\tdma_free_coherent(chan->dev, sizeof(*chan->seg_v) *\n\t\t\t\t  XILINX_DMA_NUM_DESCS, chan->seg_v,\n\t\t\t\t  chan->seg_p);\n\n\t\t/* Free Memory that is allocated for cyclic DMA Mode */\n\t\tdma_free_coherent(chan->dev, sizeof(*chan->cyclic_seg_v),\n\t\t\t\t  chan->cyclic_seg_v, chan->cyclic_seg_p);\n\t}\n\n\tif (chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA) {\n\t\tdma_pool_destroy(chan->desc_pool);\n\t\tchan->desc_pool = NULL;\n\t}\n}\n\n/**\n * xilinx_dma_chan_handle_cyclic - Cyclic dma callback\n * @chan: Driver specific dma channel\n * @desc: dma transaction descriptor\n * @flags: flags for spin lock\n */\nstatic void xilinx_dma_chan_handle_cyclic(struct xilinx_dma_chan *chan,\n\t\t\t\t\t  struct xilinx_dma_tx_descriptor *desc,\n\t\t\t\t\t  unsigned long *flags)\n{\n\tdma_async_tx_callback callback;\n\tvoid *callback_param;\n\n\tcallback = desc->async_tx.callback;\n\tcallback_param = desc->async_tx.callback_param;\n\tif (callback) {\n\t\tspin_unlock_irqrestore(&chan->lock, *flags);\n\t\tcallback(callback_param);\n\t\tspin_lock_irqsave(&chan->lock, *flags);\n\t}\n}\n\n/**\n * xilinx_dma_chan_desc_cleanup - Clean channel descriptors\n * @chan: Driver specific DMA channel\n */\nstatic void xilinx_dma_chan_desc_cleanup(struct xilinx_dma_chan *chan)\n{\n\tstruct xilinx_dma_tx_descriptor *desc, *next;\n\tunsigned long flags;\n\n\tspin_lock_irqsave(&chan->lock, flags);\n\n\tlist_for_each_entry_safe(desc, next, &chan->done_list, node) {\n\t\tstruct dmaengine_desc_callback cb;\n\n\t\tif (desc->cyclic) {\n\t\t\txilinx_dma_chan_handle_cyclic(chan, desc, &flags);\n\t\t\tbreak;\n\t\t}\n\n\t\t/* Remove from the list of running transactions */\n\t\tlist_del(&desc->node);\n\n\t\t/* Run the link descriptor callback function */\n\t\tdmaengine_desc_get_callback(&desc->async_tx, &cb);\n\t\tif (dmaengine_desc_callback_valid(&cb)) {\n\t\t\tspin_unlock_irqrestore(&chan->lock, flags);\n\t\t\tdmaengine_desc_callback_invoke(&cb, NULL);\n\t\t\tspin_lock_irqsave(&chan->lock, flags);\n\t\t}\n\n\t\t/* Run any dependencies, then free the descriptor */\n\t\tdma_run_dependencies(&desc->async_tx);\n\t\txilinx_dma_free_tx_descriptor(chan, desc);\n\t}\n\n\tspin_unlock_irqrestore(&chan->lock, flags);\n}\n\n/**\n * xilinx_dma_do_tasklet - Schedule completion tasklet\n * @data: Pointer to the Xilinx DMA channel structure\n */\nstatic void xilinx_dma_do_tasklet(unsigned long data)\n{\n\tstruct xilinx_dma_chan *chan = (struct xilinx_dma_chan *)data;\n\n\txilinx_dma_chan_desc_cleanup(chan);\n}\n\n/**\n * xilinx_dma_alloc_chan_resources - Allocate channel resources\n * @dchan: DMA channel\n *\n * Return: '0' on success and failure value on error\n */\nstatic int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan)\n{\n\tstruct xilinx_dma_chan *chan = to_xilinx_chan(dchan);\n\tint i;\n\n\t/* Has this channel already been allocated? */\n\tif (chan->desc_pool)\n\t\treturn 0;\n\n\t/*\n\t * We need the descriptor to be aligned to 64bytes\n\t * for meeting Xilinx VDMA specification requirement.\n\t */\n\tif (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {\n\t\t/* Allocate the buffer descriptors. */\n\t\tchan->seg_v = dma_zalloc_coherent(chan->dev,\n\t\t\t\t\t\t  sizeof(*chan->seg_v) *\n\t\t\t\t\t\t  XILINX_DMA_NUM_DESCS,\n\t\t\t\t\t\t  &chan->seg_p, GFP_KERNEL);\n\t\tif (!chan->seg_v) {\n\t\t\tdev_err(chan->dev,\n\t\t\t\t\"unable to allocate channel %d descriptors\\n\",\n\t\t\t\tchan->id);\n\t\t\treturn -ENOMEM;\n\t\t}\n\t\t/*\n\t\t * For cyclic DMA mode we need to program the tail Descriptor\n\t\t * register with a value which is not a part of the BD chain\n\t\t * so allocating a desc segment during channel allocation for\n\t\t * programming tail descriptor.\n\t\t */\n\t\tchan->cyclic_seg_v = dma_zalloc_coherent(chan->dev,\n\t\t\t\t\tsizeof(*chan->cyclic_seg_v),\n\t\t\t\t\t&chan->cyclic_seg_p, GFP_KERNEL);\n\t\tif (!chan->cyclic_seg_v) {\n\t\t\tdev_err(chan->dev,\n\t\t\t\t\"unable to allocate desc segment for cyclic DMA\\n\");\n\t\t\tdma_free_coherent(chan->dev, sizeof(*chan->seg_v) *\n\t\t\t\tXILINX_DMA_NUM_DESCS, chan->seg_v,\n\t\t\t\tchan->seg_p);\n\t\t\treturn -ENOMEM;\n\t\t}\n\t\tchan->cyclic_seg_v->phys = chan->cyclic_seg_p;\n\n\t\tfor (i = 0; i < XILINX_DMA_NUM_DESCS; i++) {\n\t\t\tchan->seg_v[i].hw.next_desc =\n\t\t\tlower_32_bits(chan->seg_p + sizeof(*chan->seg_v) *\n\t\t\t\t((i + 1) % XILINX_DMA_NUM_DESCS));\n\t\t\tchan->seg_v[i].hw.next_desc_msb =\n\t\t\tupper_32_bits(chan->seg_p + sizeof(*chan->seg_v) *\n\t\t\t\t((i + 1) % XILINX_DMA_NUM_DESCS));\n\t\t\tchan->seg_v[i].phys = chan->seg_p +\n\t\t\t\tsizeof(*chan->seg_v) * i;\n\t\t\tlist_add_tail(&chan->seg_v[i].node,\n\t\t\t\t      &chan->free_seg_list);\n\t\t}\n\t} else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {\n\t\tchan->desc_pool = dma_pool_create(\"xilinx_cdma_desc_pool\",\n\t\t\t\t   chan->dev,\n\t\t\t\t   sizeof(struct xilinx_cdma_tx_segment),\n\t\t\t\t   __alignof__(struct xilinx_cdma_tx_segment),\n\t\t\t\t   0);\n\t} else {\n\t\tchan->desc_pool = dma_pool_create(\"xilinx_vdma_desc_pool\",\n\t\t\t\t     chan->dev,\n\t\t\t\t     sizeof(struct xilinx_vdma_tx_segment),\n\t\t\t\t     __alignof__(struct xilinx_vdma_tx_segment),\n\t\t\t\t     0);\n\t}\n\n\tif (!chan->desc_pool &&\n\t    (chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA)) {\n\t\tdev_err(chan->dev,\n\t\t\t\"unable to allocate channel %d descriptor pool\\n\",\n\t\t\tchan->id);\n\t\treturn -ENOMEM;\n\t}\n\n\tdma_cookie_init(dchan);\n\n\tif (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {\n\t\t/* For AXI DMA resetting once channel will reset the\n\t\t * other channel as well so enable the interrupts here.\n\t\t */\n\t\tdma_ctrl_set(chan, XILINX_DMA_REG_DMACR,\n\t\t\t      XILINX_DMA_DMAXR_ALL_IRQ_MASK);\n\t}\n\n\tif ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg)\n\t\tdma_ctrl_set(chan, XILINX_DMA_REG_DMACR,\n\t\t\t     XILINX_CDMA_CR_SGMODE);\n\n\treturn 0;\n}\n\n/**\n * xilinx_dma_tx_status - Get DMA transaction status\n * @dchan: DMA channel\n * @cookie: Transaction identifier\n * @txstate: Transaction state\n *\n * Return: DMA transaction status\n */\nstatic enum dma_status xilinx_dma_tx_status(struct dma_chan *dchan,\n\t\t\t\t\tdma_cookie_t cookie,\n\t\t\t\t\tstruct dma_tx_state *txstate)\n{\n\tstruct xilinx_dma_chan *chan = to_xilinx_chan(dchan);\n\tstruct xilinx_dma_tx_descriptor *desc;\n\tstruct xilinx_axidma_tx_segment *segment;\n\tstruct xilinx_axidma_desc_hw *hw;\n\tenum dma_status ret;\n\tunsigned long flags;\n\tu32 residue = 0;\n\n\tret = dma_cookie_status(dchan, cookie, txstate);\n\tif (ret == DMA_COMPLETE || !txstate)\n\t\treturn ret;\n\n\tif (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {\n\t\tspin_lock_irqsave(&chan->lock, flags);\n\n\t\tdesc = list_last_entry(&chan->active_list,\n\t\t\t\t       struct xilinx_dma_tx_descriptor, node);\n\t\tif (chan->has_sg) {\n\t\t\tlist_for_each_entry(segment, &desc->segments, node) {\n\t\t\t\thw = &segment->hw;\n\t\t\t\tresidue += (hw->control - hw->status) &\n\t\t\t\t\t   chan->xdev->max_buffer_len;\n\t\t\t}\n\t\t}\n\t\tspin_unlock_irqrestore(&chan->lock, flags);\n\n\t\tchan->residue = residue;\n\t\tif (chan->cyclic)\n\t\t\tdma_set_residue(txstate, chan->buf_idx);\n\t\telse\n\t\t\tdma_set_residue(txstate, chan->residue);\n\t}\n\n\treturn ret;\n}\n\n/**\n * xilinx_dma_stop_transfer - Halt DMA channel\n * @chan: Driver specific DMA channel\n *\n * Return: '0' on success and failure value on error\n */\nstatic int xilinx_dma_stop_transfer(struct xilinx_dma_chan *chan)\n{\n\tu32 val;\n\n\tdma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP);\n\n\t/* Wait for the hardware to halt */\n\treturn xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,\n\t\t\t\t       val & XILINX_DMA_DMASR_HALTED, 0,\n\t\t\t\t       XILINX_DMA_LOOP_COUNT);\n}\n\n/**\n * xilinx_cdma_stop_transfer - Wait for the current transfer to complete\n * @chan: Driver specific DMA channel\n *\n * Return: '0' on success and failure value on error\n */\nstatic int xilinx_cdma_stop_transfer(struct xilinx_dma_chan *chan)\n{\n\tu32 val;\n\n\treturn xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,\n\t\t\t\t       val & XILINX_DMA_DMASR_IDLE, 0,\n\t\t\t\t       XILINX_DMA_LOOP_COUNT);\n}\n\n/**\n * xilinx_dma_start - Start DMA channel\n * @chan: Driver specific DMA channel\n */\nstatic void xilinx_dma_start(struct xilinx_dma_chan *chan)\n{\n\tint err;\n\tu32 val;\n\n\tdma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP);\n\n\t/* Wait for the hardware to start */\n\terr = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,\n\t\t\t\t      !(val & XILINX_DMA_DMASR_HALTED), 0,\n\t\t\t\t      XILINX_DMA_LOOP_COUNT);\n\n\tif (err) {\n\t\tdev_err(chan->dev, \"Cannot start channel %p: %x\\n\",\n\t\t\tchan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));\n\n\t\tchan->err = true;\n\t}\n}\n\n/**\n * xilinx_vdma_start_transfer - Starts VDMA transfer\n * @chan: Driver specific channel struct pointer\n */\nstatic void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan)\n{\n\tstruct xilinx_vdma_config *config = &chan->config;\n\tstruct xilinx_dma_tx_descriptor *desc, *tail_desc;\n\tu32 reg, j;\n\tstruct xilinx_vdma_tx_segment *tail_segment;\n\n\t/* This function was invoked with lock held */\n\tif (chan->err)\n\t\treturn;\n\n\tif (!chan->idle)\n\t\treturn;\n\n\tif (list_empty(&chan->pending_list))\n\t\treturn;\n\n\tdesc = list_first_entry(&chan->pending_list,\n\t\t\t\tstruct xilinx_dma_tx_descriptor, node);\n\ttail_desc = list_last_entry(&chan->pending_list,\n\t\t\t\t    struct xilinx_dma_tx_descriptor, node);\n\n\ttail_segment = list_last_entry(&tail_desc->segments,\n\t\t\t\t       struct xilinx_vdma_tx_segment, node);\n\n\t/*\n\t * If hardware is idle, then all descriptors on the running lists are\n\t * done, start new transfers\n\t */\n\tif (chan->has_sg)\n\t\tdma_ctrl_write(chan, XILINX_DMA_REG_CURDESC,\n\t\t\t\tdesc->async_tx.phys);\n\n\t/* Configure the hardware using info in the config structure */\n\tif (chan->has_vflip) {\n\t\treg = dma_read(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP);\n\t\treg &= ~XILINX_VDMA_ENABLE_VERTICAL_FLIP;\n\t\treg |= config->vflip_en;\n\t\tdma_write(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP,\n\t\t\t  reg);\n\t}\n\n\treg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);\n\n\tif (config->frm_cnt_en)\n\t\treg |= XILINX_DMA_DMACR_FRAMECNT_EN;\n\telse\n\t\treg &= ~XILINX_DMA_DMACR_FRAMECNT_EN;\n\n\t/*\n\t * With SG, start with circular mode, so that BDs can be fetched.\n\t * In direct register mode, if not parking, enable circular mode\n\t */\n\tif (chan->has_sg || !config->park)\n\t\treg |= XILINX_DMA_DMACR_CIRC_EN;\n\n\tif (config->park)\n\t\treg &= ~XILINX_DMA_DMACR_CIRC_EN;\n\n\tdma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);\n\n\tj = chan->desc_submitcount;\n\treg = dma_read(chan, XILINX_DMA_REG_PARK_PTR);\n\tif (chan->direction == DMA_MEM_TO_DEV) {\n\t\treg &= ~XILINX_DMA_PARK_PTR_RD_REF_MASK;\n\t\treg |= j << XILINX_DMA_PARK_PTR_RD_REF_SHIFT;\n\t} else {\n\t\treg &= ~XILINX_DMA_PARK_PTR_WR_REF_MASK;\n\t\treg |= j << XILINX_DMA_PARK_PTR_WR_REF_SHIFT;\n\t}\n\tdma_write(chan, XILINX_DMA_REG_PARK_PTR, reg);\n\n\t/* Start the hardware */\n\txilinx_dma_start(chan);\n\n\tif (chan->err)\n\t\treturn;\n\n\t/* Start the transfer */\n\tif (chan->has_sg) {\n\t\tdma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC,\n\t\t\t\ttail_segment->phys);\n\t\tlist_splice_tail_init(&chan->pending_list, &chan->active_list);\n\t\tchan->desc_pendingcount = 0;\n\t} else {\n\t\tstruct xilinx_vdma_tx_segment *segment, *last = NULL;\n\t\tint i = 0;\n\n\t\tif (chan->desc_submitcount < chan->num_frms)\n\t\t\ti = chan->desc_submitcount;\n\n\t\tlist_for_each_entry(segment, &desc->segments, node) {\n\t\t\tif (chan->ext_addr)\n\t\t\t\tvdma_desc_write_64(chan,\n\t\t\t\t\tXILINX_VDMA_REG_START_ADDRESS_64(i++),\n\t\t\t\t\tsegment->hw.buf_addr,\n\t\t\t\t\tsegment->hw.buf_addr_msb);\n\t\t\telse\n\t\t\t\tvdma_desc_write(chan,\n\t\t\t\t\tXILINX_VDMA_REG_START_ADDRESS(i++),\n\t\t\t\t\tsegment->hw.buf_addr);\n\n\t\t\tlast = segment;\n\t\t}\n\n\t\tif (!last)\n\t\t\treturn;\n\n\t\t/* HW expects these parameters to be same for one transaction */\n\t\tvdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize);\n\t\tvdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE,\n\t\t\t\tlast->hw.stride);\n\t\tvdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize);\n\n\t\tchan->desc_submitcount++;\n\t\tchan->desc_pendingcount--;\n\t\tlist_del(&desc->node);\n\t\tlist_add_tail(&desc->node, &chan->active_list);\n\t\tif (chan->desc_submitcount == chan->num_frms)\n\t\t\tchan->desc_submitcount = 0;\n\t}\n\n\tchan->idle = false;\n}\n\n/**\n * xilinx_cdma_start_transfer - Starts cdma transfer\n * @chan: Driver specific channel struct pointer\n */\nstatic void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan)\n{\n\tstruct xilinx_dma_tx_descriptor *head_desc, *tail_desc;\n\tstruct xilinx_cdma_tx_segment *tail_segment;\n\tu32 ctrl_reg = dma_read(chan, XILINX_DMA_REG_DMACR);\n\n\tif (chan->err)\n\t\treturn;\n\n\tif (!chan->idle)\n\t\treturn;\n\n\tif (list_empty(&chan->pending_list))\n\t\treturn;\n\n\thead_desc = list_first_entry(&chan->pending_list,\n\t\t\t\t     struct xilinx_dma_tx_descriptor, node);\n\ttail_desc = list_last_entry(&chan->pending_list,\n\t\t\t\t    struct xilinx_dma_tx_descriptor, node);\n\ttail_segment = list_last_entry(&tail_desc->segments,\n\t\t\t\t       struct xilinx_cdma_tx_segment, node);\n\n\tif (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) {\n\t\tctrl_reg &= ~XILINX_DMA_CR_COALESCE_MAX;\n\t\tctrl_reg |= chan->desc_pendingcount <<\n\t\t\t\tXILINX_DMA_CR_COALESCE_SHIFT;\n\t\tdma_ctrl_write(chan, XILINX_DMA_REG_DMACR, ctrl_reg);\n\t}\n\n\tif (chan->has_sg) {\n\t\tdma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,\n\t\t\t     XILINX_CDMA_CR_SGMODE);\n\n\t\tdma_ctrl_set(chan, XILINX_DMA_REG_DMACR,\n\t\t\t     XILINX_CDMA_CR_SGMODE);\n\n\t\txilinx_write(chan, XILINX_DMA_REG_CURDESC,\n\t\t\t     head_desc->async_tx.phys);\n\n\t\t/* Update tail ptr register which will start the transfer */\n\t\txilinx_write(chan, XILINX_DMA_REG_TAILDESC,\n\t\t\t     tail_segment->phys);\n\t} else {\n\t\t/* In simple mode */\n\t\tstruct xilinx_cdma_tx_segment *segment;\n\t\tstruct xilinx_cdma_desc_hw *hw;\n\n\t\tsegment = list_first_entry(&head_desc->segments,\n\t\t\t\t\t   struct xilinx_cdma_tx_segment,\n\t\t\t\t\t   node);\n\n\t\thw = &segment->hw;\n\n\t\txilinx_write(chan, XILINX_CDMA_REG_SRCADDR, (dma_addr_t)\n\t\t\t     ((u64)hw->src_addr_msb << 32 | hw->src_addr));\n\t\txilinx_write(chan, XILINX_CDMA_REG_DSTADDR, (dma_addr_t)\n\t\t\t     ((u64)hw->dest_addr_msb << 32 | hw->dest_addr));\n\n\t\t/* Start the transfer */\n\t\tdma_ctrl_write(chan, XILINX_DMA_REG_BTT,\n\t\t\t\thw->control & chan->xdev->max_buffer_len);\n\t}\n\n\tlist_splice_tail_init(&chan->pending_list, &chan->active_list);\n\tchan->desc_pendingcount = 0;\n\tchan->idle = false;\n}\n\n/**\n * xilinx_dma_start_transfer - Starts DMA transfer\n * @chan: Driver specific channel struct pointer\n */\nstatic void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)\n{\n\tstruct xilinx_dma_tx_descriptor *head_desc, *tail_desc;\n\tstruct xilinx_axidma_tx_segment *tail_segment;\n\tu32 reg;\n\n\tif (chan->err)\n\t\treturn;\n\n\tif (!chan->idle)\n\t\treturn;\n\n\tif (list_empty(&chan->pending_list))\n\t\treturn;\n\n\thead_desc = list_first_entry(&chan->pending_list,\n\t\t\t\t     struct xilinx_dma_tx_descriptor, node);\n\ttail_desc = list_last_entry(&chan->pending_list,\n\t\t\t\t    struct xilinx_dma_tx_descriptor, node);\n\ttail_segment = list_last_entry(&tail_desc->segments,\n\t\t\t\t       struct xilinx_axidma_tx_segment, node);\n\n\treg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);\n\n\tif (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) {\n\t\treg &= ~XILINX_DMA_CR_COALESCE_MAX;\n\t\treg |= chan->desc_pendingcount <<\n\t\t\t\t  XILINX_DMA_CR_COALESCE_SHIFT;\n\t\tdma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);\n\t}\n\n\tif (chan->has_sg && !chan->xdev->mcdma)\n\t\txilinx_write(chan, XILINX_DMA_REG_CURDESC,\n\t\t\t     head_desc->async_tx.phys);\n\n\tif (chan->has_sg && chan->xdev->mcdma) {\n\t\tif (chan->direction == DMA_MEM_TO_DEV) {\n\t\t\tdma_ctrl_write(chan, XILINX_DMA_REG_CURDESC,\n\t\t\t\t       head_desc->async_tx.phys);\n\t\t} else {\n\t\t\tif (!chan->tdest) {\n\t\t\t\tdma_ctrl_write(chan, XILINX_DMA_REG_CURDESC,\n\t\t\t\t       head_desc->async_tx.phys);\n\t\t\t} else {\n\t\t\t\tdma_ctrl_write(chan,\n\t\t\t\t\tXILINX_DMA_MCRX_CDESC(chan->tdest),\n\t\t\t\t       head_desc->async_tx.phys);\n\t\t\t}\n\t\t}\n\t}\n\n\txilinx_dma_start(chan);\n\n\tif (chan->err)\n\t\treturn;\n\n\t/* Start the transfer */\n\tif (chan->has_sg && !chan->xdev->mcdma) {\n\t\tif (chan->cyclic)\n\t\t\txilinx_write(chan, XILINX_DMA_REG_TAILDESC,\n\t\t\t\t     chan->cyclic_seg_v->phys);\n\t\telse\n\t\t\txilinx_write(chan, XILINX_DMA_REG_TAILDESC,\n\t\t\t\t     tail_segment->phys);\n\t} else if (chan->has_sg && chan->xdev->mcdma) {\n\t\tif (chan->direction == DMA_MEM_TO_DEV) {\n\t\t\tdma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC,\n\t\t\t       tail_segment->phys);\n\t\t} else {\n\t\t\tif (!chan->tdest) {\n\t\t\t\tdma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC,\n\t\t\t\t\t       tail_segment->phys);\n\t\t\t} else {\n\t\t\t\tdma_ctrl_write(chan,\n\t\t\t\t\tXILINX_DMA_MCRX_TDESC(chan->tdest),\n\t\t\t\t\ttail_segment->phys);\n\t\t\t}\n\t\t}\n\t} else {\n\t\tstruct xilinx_axidma_tx_segment *segment;\n\t\tstruct xilinx_axidma_desc_hw *hw;\n\n\t\tsegment = list_first_entry(&head_desc->segments,\n\t\t\t\t\t   struct xilinx_axidma_tx_segment,\n\t\t\t\t\t   node);\n\t\thw = &segment->hw;\n\n\t\txilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR, hw->buf_addr);\n\n\t\t/* Start the transfer */\n\t\tdma_ctrl_write(chan, XILINX_DMA_REG_BTT,\n\t\t\t       hw->control & chan->xdev->max_buffer_len);\n\t}\n\n\tlist_splice_tail_init(&chan->pending_list, &chan->active_list);\n\tchan->desc_pendingcount = 0;\n\tchan->idle = false;\n}\n\n/**\n * xilinx_dma_issue_pending - Issue pending transactions\n * @dchan: DMA channel\n */\nstatic void xilinx_dma_issue_pending(struct dma_chan *dchan)\n{\n\tstruct xilinx_dma_chan *chan = to_xilinx_chan(dchan);\n\tunsigned long flags;\n\n\tspin_lock_irqsave(&chan->lock, flags);\n\tchan->start_transfer(chan);\n\tspin_unlock_irqrestore(&chan->lock, flags);\n}\n\n/**\n * xilinx_dma_complete_descriptor - Mark the active descriptor as complete\n * @chan : xilinx DMA channel\n *\n * CONTEXT: hardirq\n */\nstatic void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan)\n{\n\tstruct xilinx_dma_tx_descriptor *desc, *next;\n\n\t/* This function was invoked with lock held */\n\tif (list_empty(&chan->active_list))\n\t\treturn;\n\n\tlist_for_each_entry_safe(desc, next, &chan->active_list, node) {\n\t\tlist_del(&desc->node);\n\t\tif (!desc->cyclic)\n\t\t\tdma_cookie_complete(&desc->async_tx);\n\t\tlist_add_tail(&desc->node, &chan->done_list);\n\t}\n}\n\n/**\n * xilinx_dma_reset - Reset DMA channel\n * @chan: Driver specific DMA channel\n *\n * Return: '0' on success and failure value on error\n */\nstatic int xilinx_dma_reset(struct xilinx_dma_chan *chan)\n{\n\tint err;\n\tu32 tmp;\n\n\tdma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RESET);\n\n\t/* Wait for the hardware to finish reset */\n\terr = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMACR, tmp,\n\t\t\t\t      !(tmp & XILINX_DMA_DMACR_RESET), 0,\n\t\t\t\t      XILINX_DMA_LOOP_COUNT);\n\n\tif (err) {\n\t\tdev_err(chan->dev, \"reset timeout, cr %x, sr %x\\n\",\n\t\t\tdma_ctrl_read(chan, XILINX_DMA_REG_DMACR),\n\t\t\tdma_ctrl_read(chan, XILINX_DMA_REG_DMASR));\n\t\treturn -ETIMEDOUT;\n\t}\n\n\tchan->err = false;\n\tchan->idle = true;\n\tchan->desc_submitcount = 0;\n\n\treturn err;\n}\n\n/**\n * xilinx_dma_chan_reset - Reset DMA channel and enable interrupts\n * @chan: Driver specific DMA channel\n *\n * Return: '0' on success and failure value on error\n */\nstatic int xilinx_dma_chan_reset(struct xilinx_dma_chan *chan)\n{\n\tint err;\n\n\t/* Reset VDMA */\n\terr = xilinx_dma_reset(chan);\n\tif (err)\n\t\treturn err;\n\n\t/* Enable interrupts */\n\tdma_ctrl_set(chan, XILINX_DMA_REG_DMACR,\n\t\t      XILINX_DMA_DMAXR_ALL_IRQ_MASK);\n\n\treturn 0;\n}\n\n/**\n * xilinx_dma_irq_handler - DMA Interrupt handler\n * @irq: IRQ number\n * @data: Pointer to the Xilinx DMA channel structure\n *\n * Return: IRQ_HANDLED/IRQ_NONE\n */\nstatic irqreturn_t xilinx_dma_irq_handler(int irq, void *data)\n{\n\tstruct xilinx_dma_chan *chan = data;\n\tu32 status;\n\n\t/* Read the status and ack the interrupts. */\n\tstatus = dma_ctrl_read(chan, XILINX_DMA_REG_DMASR);\n\tif (!(status & XILINX_DMA_DMAXR_ALL_IRQ_MASK))\n\t\treturn IRQ_NONE;\n\n\tdma_ctrl_write(chan, XILINX_DMA_REG_DMASR,\n\t\t\tstatus & XILINX_DMA_DMAXR_ALL_IRQ_MASK);\n\n\tif (status & XILINX_DMA_DMASR_ERR_IRQ) {\n\t\t/*\n\t\t * An error occurred. If C_FLUSH_ON_FSYNC is enabled and the\n\t\t * error is recoverable, ignore it. Otherwise flag the error.\n\t\t *\n\t\t * Only recoverable errors can be cleared in the DMASR register,\n\t\t * make sure not to write to other error bits to 1.\n\t\t */\n\t\tu32 errors = status & XILINX_DMA_DMASR_ALL_ERR_MASK;\n\n\t\tdma_ctrl_write(chan, XILINX_DMA_REG_DMASR,\n\t\t\t\terrors & XILINX_DMA_DMASR_ERR_RECOVER_MASK);\n\n\t\tif (!chan->flush_on_fsync ||\n\t\t    (errors & ~XILINX_DMA_DMASR_ERR_RECOVER_MASK)) {\n\t\t\tdev_err(chan->dev,\n\t\t\t\t\"Channel %p has errors %x, cdr %x tdr %x\\n\",\n\t\t\t\tchan, errors,\n\t\t\t\tdma_ctrl_read(chan, XILINX_DMA_REG_CURDESC),\n\t\t\t\tdma_ctrl_read(chan, XILINX_DMA_REG_TAILDESC));\n\t\t\tchan->err = true;\n\t\t}\n\t}\n\n\tif (status & XILINX_DMA_DMASR_DLY_CNT_IRQ) {\n\t\t/*\n\t\t * Device takes too long to do the transfer when user requires\n\t\t * responsiveness.\n\t\t */\n\t\tdev_dbg(chan->dev, \"Inter-packet latency too long\\n\");\n\t}\n\n\tif (status & XILINX_DMA_DMASR_FRM_CNT_IRQ) {\n\t\tspin_lock(&chan->lock);\n\t\txilinx_dma_complete_descriptor(chan);\n\t\tchan->idle = true;\n\t\tchan->start_transfer(chan);\n\t\tchan->buf_idx++;\n\t\tspin_unlock(&chan->lock);\n\t}\n\n\ttasklet_schedule(&chan->tasklet);\n\treturn IRQ_HANDLED;\n}\n\n/**\n * append_desc_queue - Queuing descriptor\n * @chan: Driver specific dma channel\n * @desc: dma transaction descriptor\n */\nstatic void append_desc_queue(struct xilinx_dma_chan *chan,\n\t\t\t      struct xilinx_dma_tx_descriptor *desc)\n{\n\tstruct xilinx_vdma_tx_segment *tail_segment;\n\tstruct xilinx_dma_tx_descriptor *tail_desc;\n\tstruct xilinx_axidma_tx_segment *axidma_tail_segment;\n\tstruct xilinx_cdma_tx_segment *cdma_tail_segment;\n\n\tif (list_empty(&chan->pending_list))\n\t\tgoto append;\n\n\t/*\n\t * Add the hardware descriptor to the chain of hardware descriptors\n\t * that already exists in memory.\n\t */\n\ttail_desc = list_last_entry(&chan->pending_list,\n\t\t\t\t    struct xilinx_dma_tx_descriptor, node);\n\tif (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {\n\t\ttail_segment = list_last_entry(&tail_desc->segments,\n\t\t\t\t\t       struct xilinx_vdma_tx_segment,\n\t\t\t\t\t       node);\n\t\ttail_segment->hw.next_desc = (u32)desc->async_tx.phys;\n\t} else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {\n\t\tcdma_tail_segment = list_last_entry(&tail_desc->segments,\n\t\t\t\t\t\tstruct xilinx_cdma_tx_segment,\n\t\t\t\t\t\tnode);\n\t\tcdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys;\n\t} else {\n\t\taxidma_tail_segment = list_last_entry(&tail_desc->segments,\n\t\t\t\t\t       struct xilinx_axidma_tx_segment,\n\t\t\t\t\t       node);\n\t\taxidma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys;\n\t}\n\n\t/*\n\t * Add the software descriptor and all children to the list\n\t * of pending transactions\n\t */\nappend:\n\tlist_add_tail(&desc->node, &chan->pending_list);\n\tchan->desc_pendingcount++;\n\n\tif (chan->has_sg && (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA)\n\t    && unlikely(chan->desc_pendingcount > chan->num_frms)) {\n\t\tdev_dbg(chan->dev, \"desc pendingcount is too high\\n\");\n\t\tchan->desc_pendingcount = chan->num_frms;\n\t}\n}\n\n/**\n * xilinx_dma_tx_submit - Submit DMA transaction\n * @tx: Async transaction descriptor\n *\n * Return: cookie value on success and failure value on error\n */\nstatic dma_cookie_t xilinx_dma_tx_submit(struct dma_async_tx_descriptor *tx)\n{\n\tstruct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx);\n\tstruct xilinx_dma_chan *chan = to_xilinx_chan(tx->chan);\n\tdma_cookie_t cookie;\n\tunsigned long flags;\n\tint err;\n\n\tif (chan->cyclic) {\n\t\txilinx_dma_free_tx_descriptor(chan, desc);\n\t\treturn -EBUSY;\n\t}\n\n\tif (chan->err) {\n\t\t/*\n\t\t * If reset fails, need to hard reset the system.\n\t\t * Channel is no longer functional\n\t\t */\n\t\terr = xilinx_dma_chan_reset(chan);\n\t\tif (err < 0)\n\t\t\treturn err;\n\t}\n\n\tspin_lock_irqsave(&chan->lock, flags);\n\n\tcookie = dma_cookie_assign(tx);\n\n\t/* Put this transaction onto the tail of the pending queue */\n\tappend_desc_queue(chan, desc);\n\n\tif (desc->cyclic)\n\t\tchan->cyclic = true;\n\n\tspin_unlock_irqrestore(&chan->lock, flags);\n\n\treturn cookie;\n}\n\n/**\n * xilinx_vdma_dma_prep_interleaved - prepare a descriptor for a\n *\tDMA_SLAVE transaction\n * @dchan: DMA channel\n * @xt: Interleaved template pointer\n * @flags: transfer ack flags\n *\n * Return: Async transaction descriptor on success and NULL on failure\n */\nstatic struct dma_async_tx_descriptor *\nxilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan,\n\t\t\t\t struct dma_interleaved_template *xt,\n\t\t\t\t unsigned long flags)\n{\n\tstruct xilinx_dma_chan *chan = to_xilinx_chan(dchan);\n\tstruct xilinx_dma_tx_descriptor *desc;\n\tstruct xilinx_vdma_tx_segment *segment;\n\tstruct xilinx_vdma_desc_hw *hw;\n\n\tif (!is_slave_direction(xt->dir))\n\t\treturn NULL;\n\n\tif (!xt->numf || !xt->sgl[0].size)\n\t\treturn NULL;\n\n\tif (xt->frame_size != 1)\n\t\treturn NULL;\n\n\t/* Allocate a transaction descriptor. */\n\tdesc = xilinx_dma_alloc_tx_descriptor(chan);\n\tif (!desc)\n\t\treturn NULL;\n\n\tdma_async_tx_descriptor_init(&desc->async_tx, &chan->common);\n\tdesc->async_tx.tx_submit = xilinx_dma_tx_submit;\n\tasync_tx_ack(&desc->async_tx);\n\n\t/* Allocate the link descriptor from DMA pool */\n\tsegment = xilinx_vdma_alloc_tx_segment(chan);\n\tif (!segment)\n\t\tgoto error;\n\n\t/* Fill in the hardware descriptor */\n\thw = &segment->hw;\n\thw->vsize = xt->numf;\n\thw->hsize = xt->sgl[0].size;\n\thw->stride = (xt->sgl[0].icg + xt->sgl[0].size) <<\n\t\t\tXILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT;\n\thw->stride |= chan->config.frm_dly <<\n\t\t\tXILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT;\n\n\tif (xt->dir != DMA_MEM_TO_DEV) {\n\t\tif (chan->ext_addr) {\n\t\t\thw->buf_addr = lower_32_bits(xt->dst_start);\n\t\t\thw->buf_addr_msb = upper_32_bits(xt->dst_start);\n\t\t} else {\n\t\t\thw->buf_addr = xt->dst_start;\n\t\t}\n\t} else {\n\t\tif (chan->ext_addr) {\n\t\t\thw->buf_addr = lower_32_bits(xt->src_start);\n\t\t\thw->buf_addr_msb = upper_32_bits(xt->src_start);\n\t\t} else {\n\t\t\thw->buf_addr = xt->src_start;\n\t\t}\n\t}\n\n\t/* Insert the segment into the descriptor segments list. */\n\tlist_add_tail(&segment->node, &desc->segments);\n\n\t/* Link the last hardware descriptor with the first. */\n\tsegment = list_first_entry(&desc->segments,\n\t\t\t\t   struct xilinx_vdma_tx_segment, node);\n\tdesc->async_tx.phys = segment->phys;\n\n\treturn &desc->async_tx;\n\nerror:\n\txilinx_dma_free_tx_descriptor(chan, desc);\n\treturn NULL;\n}\n\n/**\n * xilinx_cdma_prep_memcpy - prepare descriptors for a memcpy transaction\n * @dchan: DMA channel\n * @dma_dst: destination address\n * @dma_src: source address\n * @len: transfer length\n * @flags: transfer ack flags\n *\n * Return: Async transaction descriptor on success and NULL on failure\n */\nstatic struct dma_async_tx_descriptor *\nxilinx_cdma_prep_memcpy(struct dma_chan *dchan, dma_addr_t dma_dst,\n\t\t\tdma_addr_t dma_src, size_t len, unsigned long flags)\n{\n\tstruct xilinx_dma_chan *chan = to_xilinx_chan(dchan);\n\tstruct xilinx_dma_tx_descriptor *desc;\n\tstruct xilinx_cdma_tx_segment *segment;\n\tstruct xilinx_cdma_desc_hw *hw;\n\n\tif (!len || len > chan->xdev->max_buffer_len)\n\t\treturn NULL;\n\n\tdesc = xilinx_dma_alloc_tx_descriptor(chan);\n\tif (!desc)\n\t\treturn NULL;\n\n\tdma_async_tx_descriptor_init(&desc->async_tx, &chan->common);\n\tdesc->async_tx.tx_submit = xilinx_dma_tx_submit;\n\n\t/* Allocate the link descriptor from DMA pool */\n\tsegment = xilinx_cdma_alloc_tx_segment(chan);\n\tif (!segment)\n\t\tgoto error;\n\n\thw = &segment->hw;\n\thw->control = len;\n\thw->src_addr = dma_src;\n\thw->dest_addr = dma_dst;\n\tif (chan->ext_addr) {\n\t\thw->src_addr_msb = upper_32_bits(dma_src);\n\t\thw->dest_addr_msb = upper_32_bits(dma_dst);\n\t}\n\n\t/* Insert the segment into the descriptor segments list. */\n\tlist_add_tail(&segment->node, &desc->segments);\n\n\tdesc->async_tx.phys = segment->phys;\n\thw->next_desc = segment->phys;\n\n\treturn &desc->async_tx;\n\nerror:\n\txilinx_dma_free_tx_descriptor(chan, desc);\n\treturn NULL;\n}\n\n/**\n * xilinx_cdma_prep_sg - prepare descriptors for a memory sg transaction\n * @dchan: DMA channel\n * @dst_sg: Destination scatter list\n * @dst_sg_len: Number of entries in destination scatter list\n * @src_sg: Source scatter list\n * @src_sg_len: Number of entries in source scatter list\n * @flags: transfer ack flags\n *\n * Return: Async transaction descriptor on success and NULL on failure\n */\nstatic struct dma_async_tx_descriptor *xilinx_cdma_prep_sg(\n\t\t\tstruct dma_chan *dchan, struct scatterlist *dst_sg,\n\t\t\tunsigned int dst_sg_len, struct scatterlist *src_sg,\n\t\t\tunsigned int src_sg_len, unsigned long flags)\n{\n\tstruct xilinx_dma_chan *chan = to_xilinx_chan(dchan);\n\tstruct xilinx_dma_tx_descriptor *desc;\n\tstruct xilinx_cdma_tx_segment *segment, *prev = NULL;\n\tstruct xilinx_cdma_desc_hw *hw;\n\tsize_t len, dst_avail, src_avail;\n\tdma_addr_t dma_dst, dma_src;\n\n\tif (unlikely(dst_sg_len == 0 || src_sg_len == 0))\n\t\treturn NULL;\n\n\tif (unlikely(dst_sg == NULL || src_sg == NULL))\n\t\treturn NULL;\n\n\tdesc = xilinx_dma_alloc_tx_descriptor(chan);\n\tif (!desc)\n\t\treturn NULL;\n\n\tdma_async_tx_descriptor_init(&desc->async_tx, &chan->common);\n\tdesc->async_tx.tx_submit = xilinx_dma_tx_submit;\n\n\tdst_avail = sg_dma_len(dst_sg);\n\tsrc_avail = sg_dma_len(src_sg);\n\t/*\n\t * loop until there is either no more source or no more destination\n\t * scatterlist entry\n\t */\n\twhile (true) {\n\t\tlen = min_t(size_t, src_avail, dst_avail);\n\t\tlen = min_t(size_t, len, chan->xdev->max_buffer_len);\n\t\tif (len == 0)\n\t\t\tgoto fetch;\n\n\t\t/* Allocate the link descriptor from DMA pool */\n\t\tsegment = xilinx_cdma_alloc_tx_segment(chan);\n\t\tif (!segment)\n\t\t\tgoto error;\n\n\t\tdma_dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) -\n\t\t\tdst_avail;\n\t\tdma_src = sg_dma_address(src_sg) + sg_dma_len(src_sg) -\n\t\t\tsrc_avail;\n\t\thw = &segment->hw;\n\t\thw->control = len;\n\t\thw->src_addr = dma_src;\n\t\thw->dest_addr = dma_dst;\n\t\tif (chan->ext_addr) {\n\t\t\thw->src_addr_msb = upper_32_bits(dma_src);\n\t\t\thw->dest_addr_msb = upper_32_bits(dma_dst);\n\t\t}\n\n\t\tif (prev)\n\t\t\tprev->hw.next_desc = segment->phys;\n\n\t\tprev = segment;\n\t\tdst_avail -= len;\n\t\tsrc_avail -= len;\n\t\tlist_add_tail(&segment->node, &desc->segments);\n\nfetch:\n\t\t/* Fetch the next dst scatterlist entry */\n\t\tif (dst_avail == 0) {\n\t\t\tif (dst_sg_len == 0)\n\t\t\t\tbreak;\n\t\t\tdst_sg = sg_next(dst_sg);\n\t\t\tif (dst_sg == NULL)\n\t\t\t\tbreak;\n\t\t\tdst_sg_len--;\n\t\t\tdst_avail = sg_dma_len(dst_sg);\n\t\t}\n\t\t/* Fetch the next src scatterlist entry */\n\t\tif (src_avail == 0) {\n\t\t\tif (src_sg_len == 0)\n\t\t\t\tbreak;\n\t\t\tsrc_sg = sg_next(src_sg);\n\t\t\tif (src_sg == NULL)\n\t\t\t\tbreak;\n\t\t\tsrc_sg_len--;\n\t\t\tsrc_avail = sg_dma_len(src_sg);\n\t\t}\n\t}\n\n\t/* Link the last hardware descriptor with the first. */\n\tsegment = list_first_entry(&desc->segments,\n\t\t\t\tstruct xilinx_cdma_tx_segment, node);\n\tdesc->async_tx.phys = segment->phys;\n\tprev->hw.next_desc = segment->phys;\n\n\treturn &desc->async_tx;\n\nerror:\n\txilinx_dma_free_tx_descriptor(chan, desc);\n\treturn NULL;\n}\n\n/**\n * xilinx_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction\n * @dchan: DMA channel\n * @sgl: scatterlist to transfer to/from\n * @sg_len: number of entries in @scatterlist\n * @direction: DMA direction\n * @flags: transfer ack flags\n * @context: APP words of the descriptor\n *\n * Return: Async transaction descriptor on success and NULL on failure\n */\nstatic struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg(\n\tstruct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,\n\tenum dma_transfer_direction direction, unsigned long flags,\n\tvoid *context)\n{\n\tstruct xilinx_dma_chan *chan = to_xilinx_chan(dchan);\n\tstruct xilinx_dma_tx_descriptor *desc;\n\tstruct xilinx_axidma_tx_segment *segment = NULL;\n\tu32 *app_w = (u32 *)context;\n\tstruct scatterlist *sg;\n\tsize_t copy;\n\tsize_t sg_used;\n\tunsigned int i;\n\n\tif (!is_slave_direction(direction))\n\t\treturn NULL;\n\n\t/* Allocate a transaction descriptor. */\n\tdesc = xilinx_dma_alloc_tx_descriptor(chan);\n\tif (!desc)\n\t\treturn NULL;\n\n\tdma_async_tx_descriptor_init(&desc->async_tx, &chan->common);\n\tdesc->async_tx.tx_submit = xilinx_dma_tx_submit;\n\n\t/* Build transactions using information in the scatter gather list */\n\tfor_each_sg(sgl, sg, sg_len, i) {\n\t\tsg_used = 0;\n\n\t\t/* Loop until the entire scatterlist entry is used */\n\t\twhile (sg_used < sg_dma_len(sg)) {\n\t\t\tstruct xilinx_axidma_desc_hw *hw;\n\n\t\t\t/* Get a free segment */\n\t\t\tsegment = xilinx_axidma_alloc_tx_segment(chan);\n\t\t\tif (!segment)\n\t\t\t\tgoto error;\n\n\t\t\t/*\n\t\t\t * Calculate the maximum number of bytes to transfer,\n\t\t\t * making sure it is less than the hw limit\n\t\t\t */\n\t\t\tcopy = min_t(size_t, sg_dma_len(sg) - sg_used,\n\t\t\t\t     chan->xdev->max_buffer_len);\n\t\t\thw = &segment->hw;\n\n\t\t\t/* Fill in the descriptor */\n\t\t\txilinx_axidma_buf(chan, hw, sg_dma_address(sg),\n\t\t\t\t\t  sg_used, 0);\n\n\t\t\thw->control = copy;\n\n\t\t\tif (chan->direction == DMA_MEM_TO_DEV) {\n\t\t\t\tif (app_w)\n\t\t\t\t\tmemcpy(hw->app, app_w, sizeof(u32) *\n\t\t\t\t\t       XILINX_DMA_NUM_APP_WORDS);\n\t\t\t}\n\n\t\t\tsg_used += copy;\n\n\t\t\t/*\n\t\t\t * Insert the segment into the descriptor segments\n\t\t\t * list.\n\t\t\t */\n\t\t\tlist_add_tail(&segment->node, &desc->segments);\n\t\t}\n\t}\n\n\tsegment = list_first_entry(&desc->segments,\n\t\t\t\t   struct xilinx_axidma_tx_segment, node);\n\tdesc->async_tx.phys = segment->phys;\n\n\t/* For the last DMA_MEM_TO_DEV transfer, set EOP */\n\tif (chan->direction == DMA_MEM_TO_DEV) {\n\t\tsegment->hw.control |= XILINX_DMA_BD_SOP;\n\t\tsegment = list_last_entry(&desc->segments,\n\t\t\t\t\t  struct xilinx_axidma_tx_segment,\n\t\t\t\t\t  node);\n\t\tsegment->hw.control |= XILINX_DMA_BD_EOP;\n\t}\n\n\treturn &desc->async_tx;\n\nerror:\n\txilinx_dma_free_tx_descriptor(chan, desc);\n\treturn NULL;\n}\n\n/**\n * xilinx_dma_prep_dma_cyclic - prepare descriptors for a DMA_SLAVE transaction\n * @dchan: DMA channel\n * @buf_addr: Physical address of the buffer\n * @buf_len: Total length of the cyclic buffers\n * @period_len: length of individual cyclic buffer\n * @direction: DMA direction\n * @flags: transfer ack flags\n *\n * Return: Async transaction descriptor on success and NULL on failure\n */\nstatic struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic(\n\tstruct dma_chan *dchan, dma_addr_t buf_addr, size_t buf_len,\n\tsize_t period_len, enum dma_transfer_direction direction,\n\tunsigned long flags)\n{\n\tstruct xilinx_dma_chan *chan = to_xilinx_chan(dchan);\n\tstruct xilinx_dma_tx_descriptor *desc;\n\tstruct xilinx_axidma_tx_segment *segment, *head_segment, *prev = NULL;\n\tsize_t copy, sg_used;\n\tunsigned int num_periods;\n\tint i;\n\tu32 reg;\n\n\tif (!period_len)\n\t\treturn NULL;\n\n\tnum_periods = buf_len / period_len;\n\n\tif (!num_periods)\n\t\treturn NULL;\n\n\tif (!is_slave_direction(direction))\n\t\treturn NULL;\n\n\t/* Allocate a transaction descriptor. */\n\tdesc = xilinx_dma_alloc_tx_descriptor(chan);\n\tif (!desc)\n\t\treturn NULL;\n\n\tchan->direction = direction;\n\tdma_async_tx_descriptor_init(&desc->async_tx, &chan->common);\n\tdesc->async_tx.tx_submit = xilinx_dma_tx_submit;\n\n\tchan->buf_idx = 0;\n\n\tfor (i = 0; i < num_periods; ++i) {\n\t\tsg_used = 0;\n\n\t\twhile (sg_used < period_len) {\n\t\t\tstruct xilinx_axidma_desc_hw *hw;\n\n\t\t\t/* Get a free segment */\n\t\t\tsegment = xilinx_axidma_alloc_tx_segment(chan);\n\t\t\tif (!segment)\n\t\t\t\tgoto error;\n\n\t\t\t/*\n\t\t\t * Calculate the maximum number of bytes to transfer,\n\t\t\t * making sure it is less than the hw limit\n\t\t\t */\n\t\t\tcopy = min_t(size_t, period_len - sg_used,\n\t\t\t\t     chan->xdev->max_buffer_len);\n\t\t\thw = &segment->hw;\n\t\t\txilinx_axidma_buf(chan, hw, buf_addr, sg_used,\n\t\t\t\t\t  period_len * i);\n\t\t\thw->control = copy;\n\n\t\t\tif (prev)\n\t\t\t\tprev->hw.next_desc = segment->phys;\n\n\t\t\tprev = segment;\n\t\t\tsg_used += copy;\n\n\t\t\t/*\n\t\t\t * Insert the segment into the descriptor segments\n\t\t\t * list.\n\t\t\t */\n\t\t\tlist_add_tail(&segment->node, &desc->segments);\n\t\t}\n\t}\n\n\thead_segment = list_first_entry(&desc->segments,\n\t\t\t\t   struct xilinx_axidma_tx_segment, node);\n\tdesc->async_tx.phys = head_segment->phys;\n\n\tdesc->cyclic = true;\n\treg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);\n\treg |= XILINX_DMA_CR_CYCLIC_BD_EN_MASK;\n\tdma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);\n\n\tsegment = list_last_entry(&desc->segments,\n\t\t\t\t  struct xilinx_axidma_tx_segment,\n\t\t\t\t  node);\n\tsegment->hw.next_desc = (u32) head_segment->phys;\n\n\t/* For the last DMA_MEM_TO_DEV transfer, set EOP */\n\tif (direction == DMA_MEM_TO_DEV) {\n\t\thead_segment->hw.control |= XILINX_DMA_BD_SOP;\n\t\tsegment->hw.control |= XILINX_DMA_BD_EOP;\n\t}\n\n\treturn &desc->async_tx;\n\nerror:\n\txilinx_dma_free_tx_descriptor(chan, desc);\n\treturn NULL;\n}\n\n/**\n * xilinx_dma_prep_interleaved - prepare a descriptor for a\n *\tDMA_SLAVE transaction\n * @dchan: DMA channel\n * @xt: Interleaved template pointer\n * @flags: transfer ack flags\n *\n * Return: Async transaction descriptor on success and NULL on failure\n */\nstatic struct dma_async_tx_descriptor *\nxilinx_dma_prep_interleaved(struct dma_chan *dchan,\n\t\t\t\t struct dma_interleaved_template *xt,\n\t\t\t\t unsigned long flags)\n{\n\tstruct xilinx_dma_chan *chan = to_xilinx_chan(dchan);\n\tstruct xilinx_dma_tx_descriptor *desc;\n\tstruct xilinx_axidma_tx_segment *segment;\n\tstruct xilinx_axidma_desc_hw *hw;\n\n\tif (!is_slave_direction(xt->dir))\n\t\treturn NULL;\n\n\tif (!xt->numf || !xt->sgl[0].size)\n\t\treturn NULL;\n\n\tif (xt->frame_size != 1)\n\t\treturn NULL;\n\n\t/* Allocate a transaction descriptor. */\n\tdesc = xilinx_dma_alloc_tx_descriptor(chan);\n\tif (!desc)\n\t\treturn NULL;\n\n\tchan->direction = xt->dir;\n\tdma_async_tx_descriptor_init(&desc->async_tx, &chan->common);\n\tdesc->async_tx.tx_submit = xilinx_dma_tx_submit;\n\n\t/* Get a free segment */\n\tsegment = xilinx_axidma_alloc_tx_segment(chan);\n\tif (!segment)\n\t\tgoto error;\n\n\thw = &segment->hw;\n\n\t/* Fill in the descriptor */\n\tif (xt->dir != DMA_MEM_TO_DEV)\n\t\thw->buf_addr = xt->dst_start;\n\telse\n\t\thw->buf_addr = xt->src_start;\n\n\thw->mcdma_control = chan->tdest & XILINX_DMA_BD_TDEST_MASK;\n\thw->vsize_stride = (xt->numf << XILINX_DMA_BD_VSIZE_SHIFT) &\n\t\t\t    XILINX_DMA_BD_VSIZE_MASK;\n\thw->vsize_stride |= (xt->sgl[0].icg + xt->sgl[0].size) &\n\t\t\t    XILINX_DMA_BD_STRIDE_MASK;\n\thw->control = xt->sgl[0].size & XILINX_DMA_BD_HSIZE_MASK;\n\n\t/*\n\t * Insert the segment into the descriptor segments\n\t * list.\n\t */\n\tlist_add_tail(&segment->node, &desc->segments);\n\n\n\tsegment = list_first_entry(&desc->segments,\n\t\t\t\t   struct xilinx_axidma_tx_segment, node);\n\tdesc->async_tx.phys = segment->phys;\n\n\t/* For the last DMA_MEM_TO_DEV transfer, set EOP */\n\tif (xt->dir == DMA_MEM_TO_DEV) {\n\t\tsegment->hw.control |= XILINX_DMA_BD_SOP;\n\t\tsegment = list_last_entry(&desc->segments,\n\t\t\t\t\t  struct xilinx_axidma_tx_segment,\n\t\t\t\t\t  node);\n\t\tsegment->hw.control |= XILINX_DMA_BD_EOP;\n\t}\n\n\treturn &desc->async_tx;\n\nerror:\n\txilinx_dma_free_tx_descriptor(chan, desc);\n\treturn NULL;\n}\n\n/**\n * xilinx_dma_terminate_all - Halt the channel and free descriptors\n * @dchan: Driver specific DMA Channel pointer\n *\n * Return: '0' always.\n */\nstatic int xilinx_dma_terminate_all(struct dma_chan *dchan)\n{\n\tstruct xilinx_dma_chan *chan = to_xilinx_chan(dchan);\n\tu32 reg;\n\tint err;\n\n\tif (!chan->cyclic) {\n\t\terr = chan->stop_transfer(chan);\n\t\tif (err) {\n\t\t\tdev_err(chan->dev, \"Cannot stop channel %p: %x\\n\",\n\t\t\t\tchan, dma_ctrl_read(chan,\n\t\t\t\tXILINX_DMA_REG_DMASR));\n\t\t\tchan->err = true;\n\t\t}\n\t}\n\n\txilinx_dma_chan_reset(chan);\n\t/* Remove and free all of the descriptors in the lists */\n\txilinx_dma_free_descriptors(chan);\n\tchan->idle = true;\n\n\tif (chan->cyclic) {\n\t\treg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);\n\t\treg &= ~XILINX_DMA_CR_CYCLIC_BD_EN_MASK;\n\t\tdma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);\n\t\tchan->cyclic = false;\n\t}\n\n\tif ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg)\n\t\tdma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,\n\t\t\t     XILINX_CDMA_CR_SGMODE);\n\n\treturn 0;\n}\n\n/**\n * xilinx_dma_channel_set_config - Configure VDMA channel\n * Run-time configuration for Axi VDMA, supports:\n * . halt the channel\n * . configure interrupt coalescing and inter-packet delay threshold\n * . start/stop parking\n * . enable genlock\n *\n * @dchan: DMA channel\n * @cfg: VDMA device configuration pointer\n *\n * Return: '0' on success and failure value on error\n */\nint xilinx_vdma_channel_set_config(struct dma_chan *dchan,\n\t\t\t\t\tstruct xilinx_vdma_config *cfg)\n{\n\tstruct xilinx_dma_chan *chan = to_xilinx_chan(dchan);\n\tu32 dmacr;\n\n\tif (cfg->reset)\n\t\treturn xilinx_dma_chan_reset(chan);\n\n\tdmacr = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);\n\n\tchan->config.frm_dly = cfg->frm_dly;\n\tchan->config.park = cfg->park;\n\n\t/* genlock settings */\n\tchan->config.gen_lock = cfg->gen_lock;\n\tchan->config.master = cfg->master;\n\n\tif (cfg->gen_lock && chan->genlock) {\n\t\tdmacr |= XILINX_DMA_DMACR_GENLOCK_EN;\n\t\tdmacr |= cfg->master << XILINX_DMA_DMACR_MASTER_SHIFT;\n\t}\n\n\tchan->config.frm_cnt_en = cfg->frm_cnt_en;\n\tchan->config.vflip_en = cfg->vflip_en;\n\n\tif (cfg->park)\n\t\tchan->config.park_frm = cfg->park_frm;\n\telse\n\t\tchan->config.park_frm = -1;\n\n\tchan->config.coalesc = cfg->coalesc;\n\tchan->config.delay = cfg->delay;\n\n\tif (cfg->coalesc <= XILINX_DMA_DMACR_FRAME_COUNT_MAX) {\n\t\tdmacr |= cfg->coalesc << XILINX_DMA_DMACR_FRAME_COUNT_SHIFT;\n\t\tchan->config.coalesc = cfg->coalesc;\n\t}\n\n\tif (cfg->delay <= XILINX_DMA_DMACR_DELAY_MAX) {\n\t\tdmacr |= cfg->delay << XILINX_DMA_DMACR_DELAY_SHIFT;\n\t\tchan->config.delay = cfg->delay;\n\t}\n\n\t/* FSync Source selection */\n\tdmacr &= ~XILINX_DMA_DMACR_FSYNCSRC_MASK;\n\tdmacr |= cfg->ext_fsync << XILINX_DMA_DMACR_FSYNCSRC_SHIFT;\n\n\tdma_ctrl_write(chan, XILINX_DMA_REG_DMACR, dmacr);\n\n\treturn 0;\n}\nEXPORT_SYMBOL(xilinx_vdma_channel_set_config);\n\n/* -----------------------------------------------------------------------------\n * Probe and remove\n */\n\n/**\n * xilinx_dma_chan_remove - Per Channel remove function\n * @chan: Driver specific DMA channel\n */\nstatic void xilinx_dma_chan_remove(struct xilinx_dma_chan *chan)\n{\n\t/* Disable all interrupts */\n\tdma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,\n\t\t      XILINX_DMA_DMAXR_ALL_IRQ_MASK);\n\n\tif (chan->irq > 0)\n\t\tfree_irq(chan->irq, chan);\n\n\ttasklet_kill(&chan->tasklet);\n\n\tlist_del(&chan->common.device_node);\n}\n\nstatic int axidma_clk_init(struct platform_device *pdev, struct clk **axi_clk,\n\t\t\t    struct clk **tx_clk, struct clk **rx_clk,\n\t\t\t    struct clk **sg_clk, struct clk **tmp_clk)\n{\n\tint err;\n\n\t*tmp_clk = NULL;\n\n\t*axi_clk = devm_clk_get(&pdev->dev, \"s_axi_lite_aclk\");\n\tif (IS_ERR(*axi_clk)) {\n\t\terr = PTR_ERR(*axi_clk);\n\t\tdev_err(&pdev->dev, \"failed to get axi_aclk (%d)\\n\", err);\n\t\treturn err;\n\t}\n\n\t*tx_clk = devm_clk_get(&pdev->dev, \"m_axi_mm2s_aclk\");\n\tif (IS_ERR(*tx_clk))\n\t\t*tx_clk = NULL;\n\n\t*rx_clk = devm_clk_get(&pdev->dev, \"m_axi_s2mm_aclk\");\n\tif (IS_ERR(*rx_clk))\n\t\t*rx_clk = NULL;\n\n\t*sg_clk = devm_clk_get(&pdev->dev, \"m_axi_sg_aclk\");\n\tif (IS_ERR(*sg_clk))\n\t\t*sg_clk = NULL;\n\n\terr = clk_prepare_enable(*axi_clk);\n\tif (err) {\n\t\tdev_err(&pdev->dev, \"failed to enable axi_clk (%d)\\n\", err);\n\t\treturn err;\n\t}\n\n\terr = clk_prepare_enable(*tx_clk);\n\tif (err) {\n\t\tdev_err(&pdev->dev, \"failed to enable tx_clk (%d)\\n\", err);\n\t\tgoto err_disable_axiclk;\n\t}\n\n\terr = clk_prepare_enable(*rx_clk);\n\tif (err) {\n\t\tdev_err(&pdev->dev, \"failed to enable rx_clk (%d)\\n\", err);\n\t\tgoto err_disable_txclk;\n\t}\n\n\terr = clk_prepare_enable(*sg_clk);\n\tif (err) {\n\t\tdev_err(&pdev->dev, \"failed to enable sg_clk (%d)\\n\", err);\n\t\tgoto err_disable_rxclk;\n\t}\n\n\treturn 0;\n\nerr_disable_rxclk:\n\tclk_disable_unprepare(*rx_clk);\nerr_disable_txclk:\n\tclk_disable_unprepare(*tx_clk);\nerr_disable_axiclk:\n\tclk_disable_unprepare(*axi_clk);\n\n\treturn err;\n}\n\nstatic int axicdma_clk_init(struct platform_device *pdev, struct clk **axi_clk,\n\t\t\t    struct clk **dev_clk, struct clk **tmp_clk,\n\t\t\t    struct clk **tmp1_clk, struct clk **tmp2_clk)\n{\n\tint err;\n\n\t*tmp_clk = NULL;\n\t*tmp1_clk = NULL;\n\t*tmp2_clk = NULL;\n\n\t*axi_clk = devm_clk_get(&pdev->dev, \"s_axi_lite_aclk\");\n\tif (IS_ERR(*axi_clk)) {\n\t\terr = PTR_ERR(*axi_clk);\n\t\tdev_err(&pdev->dev, \"failed to get axi_clk (%d)\\n\", err);\n\t\treturn err;\n\t}\n\n\t*dev_clk = devm_clk_get(&pdev->dev, \"m_axi_aclk\");\n\tif (IS_ERR(*dev_clk)) {\n\t\terr = PTR_ERR(*dev_clk);\n\t\tdev_err(&pdev->dev, \"failed to get dev_clk (%d)\\n\", err);\n\t\treturn err;\n\t}\n\n\terr = clk_prepare_enable(*axi_clk);\n\tif (err) {\n\t\tdev_err(&pdev->dev, \"failed to enable axi_clk (%d)\\n\", err);\n\t\treturn err;\n\t}\n\n\terr = clk_prepare_enable(*dev_clk);\n\tif (err) {\n\t\tdev_err(&pdev->dev, \"failed to enable dev_clk (%d)\\n\", err);\n\t\tgoto err_disable_axiclk;\n\t}\n\n\treturn 0;\n\nerr_disable_axiclk:\n\tclk_disable_unprepare(*axi_clk);\n\n\treturn err;\n}\n\nstatic int axivdma_clk_init(struct platform_device *pdev, struct clk **axi_clk,\n\t\t\t    struct clk **tx_clk, struct clk **txs_clk,\n\t\t\t    struct clk **rx_clk, struct clk **rxs_clk)\n{\n\tint err;\n\n\t*axi_clk = devm_clk_get(&pdev->dev, \"s_axi_lite_aclk\");\n\tif (IS_ERR(*axi_clk)) {\n\t\terr = PTR_ERR(*axi_clk);\n\t\tdev_err(&pdev->dev, \"failed to get axi_aclk (%d)\\n\", err);\n\t\treturn err;\n\t}\n\n\t*tx_clk = devm_clk_get(&pdev->dev, \"m_axi_mm2s_aclk\");\n\tif (IS_ERR(*tx_clk))\n\t\t*tx_clk = NULL;\n\n\t*txs_clk = devm_clk_get(&pdev->dev, \"m_axis_mm2s_aclk\");\n\tif (IS_ERR(*txs_clk))\n\t\t*txs_clk = NULL;\n\n\t*rx_clk = devm_clk_get(&pdev->dev, \"m_axi_s2mm_aclk\");\n\tif (IS_ERR(*rx_clk))\n\t\t*rx_clk = NULL;\n\n\t*rxs_clk = devm_clk_get(&pdev->dev, \"s_axis_s2mm_aclk\");\n\tif (IS_ERR(*rxs_clk))\n\t\t*rxs_clk = NULL;\n\n\terr = clk_prepare_enable(*axi_clk);\n\tif (err) {\n\t\tdev_err(&pdev->dev, \"failed to enable axi_clk (%d)\\n\", err);\n\t\treturn err;\n\t}\n\n\terr = clk_prepare_enable(*tx_clk);\n\tif (err) {\n\t\tdev_err(&pdev->dev, \"failed to enable tx_clk (%d)\\n\", err);\n\t\tgoto err_disable_axiclk;\n\t}\n\n\terr = clk_prepare_enable(*txs_clk);\n\tif (err) {\n\t\tdev_err(&pdev->dev, \"failed to enable txs_clk (%d)\\n\", err);\n\t\tgoto err_disable_txclk;\n\t}\n\n\terr = clk_prepare_enable(*rx_clk);\n\tif (err) {\n\t\tdev_err(&pdev->dev, \"failed to enable rx_clk (%d)\\n\", err);\n\t\tgoto err_disable_txsclk;\n\t}\n\n\terr = clk_prepare_enable(*rxs_clk);\n\tif (err) {\n\t\tdev_err(&pdev->dev, \"failed to enable rxs_clk (%d)\\n\", err);\n\t\tgoto err_disable_rxclk;\n\t}\n\n\treturn 0;\n\nerr_disable_rxclk:\n\tclk_disable_unprepare(*rx_clk);\nerr_disable_txsclk:\n\tclk_disable_unprepare(*txs_clk);\nerr_disable_txclk:\n\tclk_disable_unprepare(*tx_clk);\nerr_disable_axiclk:\n\tclk_disable_unprepare(*axi_clk);\n\n\treturn err;\n}\n\nstatic void xdma_disable_allclks(struct xilinx_dma_device *xdev)\n{\n\tclk_disable_unprepare(xdev->rxs_clk);\n\tclk_disable_unprepare(xdev->rx_clk);\n\tclk_disable_unprepare(xdev->txs_clk);\n\tclk_disable_unprepare(xdev->tx_clk);\n\tclk_disable_unprepare(xdev->axi_clk);\n}\n\n/**\n * xilinx_dma_chan_probe - Per Channel Probing\n * It get channel features from the device tree entry and\n * initialize special channel handling routines\n *\n * @xdev: Driver specific device structure\n * @node: Device node\n * @chan_id: DMA Channel id\n *\n * Return: '0' on success and failure value on error\n */\nstatic int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,\n\t\t\t\t  struct device_node *node, int chan_id)\n{\n\tstruct xilinx_dma_chan *chan;\n\tbool has_dre = false;\n\tu32 value, width;\n\tint err;\n\n\t/* Allocate and initialize the channel structure */\n\tchan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL);\n\tif (!chan)\n\t\treturn -ENOMEM;\n\n\tchan->dev = xdev->dev;\n\tchan->xdev = xdev;\n\tchan->has_sg = xdev->has_sg;\n\tchan->desc_pendingcount = 0x0;\n\tchan->ext_addr = xdev->ext_addr;\n\t/* This variable ensures that descriptors are not\n\t * Submitted when dma engine is in progress. This variable is\n\t * Added to avoid polling for a bit in the status register to\n\t * Know dma state in the driver hot path.\n\t */\n\tchan->idle = true;\n\n\tspin_lock_init(&chan->lock);\n\tINIT_LIST_HEAD(&chan->pending_list);\n\tINIT_LIST_HEAD(&chan->done_list);\n\tINIT_LIST_HEAD(&chan->active_list);\n\tINIT_LIST_HEAD(&chan->free_seg_list);\n\n\t/* Retrieve the channel properties from the device tree */\n\thas_dre = of_property_read_bool(node, \"xlnx,include-dre\");\n\n\tchan->genlock = of_property_read_bool(node, \"xlnx,genlock-mode\");\n\n\terr = of_property_read_u32(node, \"xlnx,datawidth\", &value);\n\tif (err) {\n\t\tdev_err(xdev->dev, \"missing xlnx,datawidth property\\n\");\n\t\treturn err;\n\t}\n\twidth = value >> 3; /* Convert bits to bytes */\n\n\t/* If data width is greater than 8 bytes, DRE is not in hw */\n\tif (width > 8)\n\t\thas_dre = false;\n\n\tif (!has_dre)\n\t\txdev->common.copy_align = fls(width - 1);\n\n\tif (of_device_is_compatible(node, \"xlnx,axi-vdma-mm2s-channel\") ||\n\t    of_device_is_compatible(node, \"xlnx,axi-dma-mm2s-channel\") ||\n\t    of_device_is_compatible(node, \"xlnx,axi-cdma-channel\")) {\n\t\tchan->direction = DMA_MEM_TO_DEV;\n\t\tchan->id = chan_id;\n\t\tchan->tdest = chan_id;\n\t\txdev->common.directions = BIT(DMA_MEM_TO_DEV);\n\n\t\tchan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET;\n\t\tif (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {\n\t\t\tchan->desc_offset = XILINX_VDMA_MM2S_DESC_OFFSET;\n\t\t\tchan->config.park = 1;\n\n\t\t\tif (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH ||\n\t\t\t    xdev->flush_on_fsync == XILINX_DMA_FLUSH_MM2S)\n\t\t\t\tchan->flush_on_fsync = true;\n\t\t}\n\t} else if (of_device_is_compatible(node,\n\t\t\t\t\t   \"xlnx,axi-vdma-s2mm-channel\") ||\n\t\t   of_device_is_compatible(node,\n\t\t\t\t\t   \"xlnx,axi-dma-s2mm-channel\")) {\n\t\tchan->direction = DMA_DEV_TO_MEM;\n\t\tchan->id = chan_id;\n\t\tchan->tdest = chan_id - xdev->nr_channels;\n\t\txdev->common.directions |= BIT(DMA_DEV_TO_MEM);\n\t\tchan->has_vflip = of_property_read_bool(node,\n\t\t\t\t\t\"xlnx,enable-vert-flip\");\n\t\tif (chan->has_vflip) {\n\t\t\tchan->config.vflip_en = dma_read(chan,\n\t\t\t\tXILINX_VDMA_REG_ENABLE_VERTICAL_FLIP) &\n\t\t\t\tXILINX_VDMA_ENABLE_VERTICAL_FLIP;\n\t\t}\n\n\t\tchan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET;\n\t\tif (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {\n\t\t\tchan->desc_offset = XILINX_VDMA_S2MM_DESC_OFFSET;\n\t\t\tchan->config.park = 1;\n\n\t\t\tif (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH ||\n\t\t\t    xdev->flush_on_fsync == XILINX_DMA_FLUSH_S2MM)\n\t\t\t\tchan->flush_on_fsync = true;\n\t\t}\n\t} else {\n\t\tdev_err(xdev->dev, \"Invalid channel compatible node\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\t/* Request the interrupt */\n\tchan->irq = irq_of_parse_and_map(node, 0);\n\terr = request_irq(chan->irq, xilinx_dma_irq_handler, IRQF_SHARED,\n\t\t\t  \"xilinx-dma-controller\", chan);\n\tif (err) {\n\t\tdev_err(xdev->dev, \"unable to request IRQ %d\\n\", chan->irq);\n\t\treturn err;\n\t}\n\n\tif (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {\n\t\tchan->start_transfer = xilinx_dma_start_transfer;\n\t\tchan->stop_transfer = xilinx_dma_stop_transfer;\n\t} else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {\n\t\tchan->start_transfer = xilinx_cdma_start_transfer;\n\t\tchan->stop_transfer = xilinx_cdma_stop_transfer;\n\t} else {\n\t\tchan->start_transfer = xilinx_vdma_start_transfer;\n\t\tchan->stop_transfer = xilinx_dma_stop_transfer;\n\t}\n\n\t/* Initialize the tasklet */\n\ttasklet_init(&chan->tasklet, xilinx_dma_do_tasklet,\n\t\t\t(unsigned long)chan);\n\n\t/*\n\t * Initialize the DMA channel and add it to the DMA engine channels\n\t * list.\n\t */\n\tchan->common.device = &xdev->common;\n\n\tlist_add_tail(&chan->common.device_node, &xdev->common.channels);\n\txdev->chan[chan->id] = chan;\n\n\t/* Reset the channel */\n\terr = xilinx_dma_chan_reset(chan);\n\tif (err < 0) {\n\t\tdev_err(xdev->dev, \"Reset channel failed\\n\");\n\t\treturn err;\n\t}\n\n\treturn 0;\n}\n\n/**\n * xilinx_dma_child_probe - Per child node probe\n * It get number of dma-channels per child node from\n * device-tree and initializes all the channels.\n *\n * @xdev: Driver specific device structure\n * @node: Device node\n *\n * Return: 0 always.\n */\nstatic int xilinx_dma_child_probe(struct xilinx_dma_device *xdev,\n\t\t\t\t    struct device_node *node)\n{\n\tint ret, i, nr_channels = 1;\n\n\tret = of_property_read_u32(node, \"dma-channels\", &nr_channels);\n\tif ((ret < 0) && xdev->mcdma)\n\t\tdev_warn(xdev->dev, \"missing dma-channels property\\n\");\n\n\tfor (i = 0; i < nr_channels; i++)\n\t\txilinx_dma_chan_probe(xdev, node, xdev->chan_id++);\n\n\txdev->nr_channels += nr_channels;\n\n\treturn 0;\n}\n\n/**\n * of_dma_xilinx_xlate - Translation function\n * @dma_spec: Pointer to DMA specifier as found in the device tree\n * @ofdma: Pointer to DMA controller data\n *\n * Return: DMA channel pointer on success and NULL on error\n */\nstatic struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec,\n\t\t\t\t\t\tstruct of_dma *ofdma)\n{\n\tstruct xilinx_dma_device *xdev = ofdma->of_dma_data;\n\tint chan_id = dma_spec->args[0];\n\n\tif (chan_id >= xdev->nr_channels || !xdev->chan[chan_id])\n\t\treturn NULL;\n\n\treturn dma_get_slave_channel(&xdev->chan[chan_id]->common);\n}\n\nstatic const struct xilinx_dma_config axidma_config = {\n\t.dmatype = XDMA_TYPE_AXIDMA,\n\t.clk_init = axidma_clk_init,\n};\n\nstatic const struct xilinx_dma_config axicdma_config = {\n\t.dmatype = XDMA_TYPE_CDMA,\n\t.clk_init = axicdma_clk_init,\n};\n\nstatic const struct xilinx_dma_config axivdma_config = {\n\t.dmatype = XDMA_TYPE_VDMA,\n\t.clk_init = axivdma_clk_init,\n};\n\nstatic const struct of_device_id xilinx_dma_of_ids[] = {\n\t{ .compatible = \"xlnx,axi-dma-1.00.a\", .data = &axidma_config },\n\t{ .compatible = \"xlnx,axi-cdma-1.00.a\", .data = &axicdma_config },\n\t{ .compatible = \"xlnx,axi-vdma-1.00.a\", .data = &axivdma_config },\n\t{}\n};\nMODULE_DEVICE_TABLE(of, xilinx_dma_of_ids);\n\n/**\n * xilinx_dma_probe - Driver probe function\n * @pdev: Pointer to the platform_device structure\n *\n * Return: '0' on success and failure value on error\n */\nstatic int xilinx_dma_probe(struct platform_device *pdev)\n{\n\tint (*clk_init)(struct platform_device *, struct clk **, struct clk **,\n\t\t\tstruct clk **, struct clk **, struct clk **)\n\t\t\t\t\t= axivdma_clk_init;\n\tstruct device_node *node = pdev->dev.of_node;\n\tstruct xilinx_dma_device *xdev;\n\tstruct device_node *child, *np = pdev->dev.of_node;\n\tstruct resource *io;\n\tu32 num_frames, addr_width, len_width;\n\tint i, err;\n\n\t/* Allocate and initialize the DMA engine structure */\n\txdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL);\n\tif (!xdev)\n\t\treturn -ENOMEM;\n\n\txdev->dev = &pdev->dev;\n\tif (np) {\n\t\tconst struct of_device_id *match;\n\n\t\tmatch = of_match_node(xilinx_dma_of_ids, np);\n\t\tif (match && match->data) {\n\t\t\txdev->dma_config = match->data;\n\t\t\tclk_init = xdev->dma_config->clk_init;\n\t\t}\n\t}\n\n\terr = clk_init(pdev, &xdev->axi_clk, &xdev->tx_clk, &xdev->txs_clk,\n\t\t       &xdev->rx_clk, &xdev->rxs_clk);\n\tif (err)\n\t\treturn err;\n\n\t/* Request and map I/O memory */\n\tio = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n\txdev->regs = devm_ioremap_resource(&pdev->dev, io);\n\tif (IS_ERR(xdev->regs))\n\t\treturn PTR_ERR(xdev->regs);\n\n\t/* Retrieve the DMA engine properties from the device tree */\n\txdev->has_sg = of_property_read_bool(node, \"xlnx,include-sg\");\n\txdev->max_buffer_len = GENMASK(XILINX_DMA_MAX_TRANS_LEN_MAX - 1, 0);\n\n\tif (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {\n\t\txdev->mcdma = of_property_read_bool(node, \"xlnx,mcdma\");\n\t\tif (!of_property_read_u32(node, \"xlnx,sg-length-width\",\n\t\t\t\t\t  &len_width)) {\n\t\t\tif (len_width < XILINX_DMA_MAX_TRANS_LEN_MIN ||\n\t\t\t    len_width > XILINX_DMA_V2_MAX_TRANS_LEN_MAX) {\n\t\t\t\tdev_warn(xdev->dev,\n\t\t\t\t\t \"invalid xlnx,sg-length-width property value using default width\\n\");\n\t\t\t} else {\n\t\t\t\tif (len_width > XILINX_DMA_MAX_TRANS_LEN_MAX)\n\t\t\t\t\tdev_warn(xdev->dev, \"Please ensure that IP supports buffer length > 23 bits\\n\");\n\n\t\t\t\txdev->max_buffer_len = GENMASK(len_width - 1, 0);\n\t\t\t}\n\t\t}\n\t}\n\n\tif (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {\n\t\terr = of_property_read_u32(node, \"xlnx,num-fstores\",\n\t\t\t\t\t   &num_frames);\n\t\tif (err < 0) {\n\t\t\tdev_err(xdev->dev,\n\t\t\t\t\"missing xlnx,num-fstores property\\n\");\n\t\t\treturn err;\n\t\t}\n\n\t\terr = of_property_read_u32(node, \"xlnx,flush-fsync\",\n\t\t\t\t\t   &xdev->flush_on_fsync);\n\t\tif (err < 0)\n\t\t\tdev_warn(xdev->dev,\n\t\t\t\t \"missing xlnx,flush-fsync property\\n\");\n\t}\n\n\terr = of_property_read_u32(node, \"xlnx,addrwidth\", &addr_width);\n\tif (err < 0)\n\t\tdev_warn(xdev->dev, \"missing xlnx,addrwidth property\\n\");\n\n\tif (addr_width > 32)\n\t\txdev->ext_addr = true;\n\telse\n\t\txdev->ext_addr = false;\n\n\t/* Set the dma mask bits */\n\tdma_set_mask(xdev->dev, DMA_BIT_MASK(addr_width));\n\n\t/* Initialize the DMA engine */\n\txdev->common.dev = &pdev->dev;\n\n\tINIT_LIST_HEAD(&xdev->common.channels);\n\tif (!(xdev->dma_config->dmatype == XDMA_TYPE_CDMA)) {\n\t\tdma_cap_set(DMA_SLAVE, xdev->common.cap_mask);\n\t\tdma_cap_set(DMA_PRIVATE, xdev->common.cap_mask);\n\t}\n\n\txdev->common.dst_addr_widths = BIT(addr_width / 8);\n\txdev->common.src_addr_widths = BIT(addr_width / 8);\n\txdev->common.device_alloc_chan_resources =\n\t\t\t\txilinx_dma_alloc_chan_resources;\n\txdev->common.device_free_chan_resources =\n\t\t\t\txilinx_dma_free_chan_resources;\n\txdev->common.device_terminate_all = xilinx_dma_terminate_all;\n\txdev->common.device_tx_status = xilinx_dma_tx_status;\n\txdev->common.device_issue_pending = xilinx_dma_issue_pending;\n\tif (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {\n\t\tdma_cap_set(DMA_CYCLIC, xdev->common.cap_mask);\n\t\txdev->common.device_prep_slave_sg = xilinx_dma_prep_slave_sg;\n\t\txdev->common.device_prep_dma_cyclic =\n\t\t\t\t\t  xilinx_dma_prep_dma_cyclic;\n\t\txdev->common.device_prep_interleaved_dma =\n\t\t\t\t\txilinx_dma_prep_interleaved;\n\t\t/* Residue calculation is supported by only AXI DMA */\n\t\txdev->common.residue_granularity =\n\t\t\t\t\t  DMA_RESIDUE_GRANULARITY_SEGMENT;\n\t} else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {\n\t\tdma_cap_set(DMA_MEMCPY, xdev->common.cap_mask);\n\t\tdma_cap_set(DMA_SG, xdev->common.cap_mask);\n\t\txdev->common.device_prep_dma_memcpy = xilinx_cdma_prep_memcpy;\n\t\txdev->common.device_prep_dma_sg = xilinx_cdma_prep_sg;\n\t} else {\n\t\txdev->common.device_prep_interleaved_dma =\n\t\t\t\txilinx_vdma_dma_prep_interleaved;\n\t}\n\n\tplatform_set_drvdata(pdev, xdev);\n\n\t/* Initialize the channels */\n\tfor_each_child_of_node(node, child) {\n\t\terr = xilinx_dma_child_probe(xdev, child);\n\t\tif (err < 0)\n\t\t\tgoto disable_clks;\n\t}\n\n\tif (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {\n\t\tfor (i = 0; i < xdev->nr_channels; i++)\n\t\t\tif (xdev->chan[i])\n\t\t\t\txdev->chan[i]->num_frms = num_frames;\n\t}\n\n\t/* Register the DMA engine with the core */\n\tdma_async_device_register(&xdev->common);\n\n\terr = of_dma_controller_register(node, of_dma_xilinx_xlate,\n\t\t\t\t\t xdev);\n\tif (err < 0) {\n\t\tdev_err(&pdev->dev, \"Unable to register DMA to DT\\n\");\n\t\tdma_async_device_unregister(&xdev->common);\n\t\tgoto error;\n\t}\n\n\tif (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA)\n\t\tdev_info(&pdev->dev, \"Xilinx AXI DMA Engine Driver Probed!!\\n\");\n\telse if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA)\n\t\tdev_info(&pdev->dev, \"Xilinx AXI CDMA Engine Driver Probed!!\\n\");\n\telse\n\t\tdev_info(&pdev->dev, \"Xilinx AXI VDMA Engine Driver Probed!!\\n\");\n\n\treturn 0;\n\ndisable_clks:\n\txdma_disable_allclks(xdev);\nerror:\n\tfor (i = 0; i < xdev->nr_channels; i++)\n\t\tif (xdev->chan[i])\n\t\t\txilinx_dma_chan_remove(xdev->chan[i]);\n\n\treturn err;\n}\n\n/**\n * xilinx_dma_remove - Driver remove function\n * @pdev: Pointer to the platform_device structure\n *\n * Return: Always '0'\n */\nstatic int xilinx_dma_remove(struct platform_device *pdev)\n{\n\tstruct xilinx_dma_device *xdev = platform_get_drvdata(pdev);\n\tint i;\n\n\tof_dma_controller_free(pdev->dev.of_node);\n\n\tdma_async_device_unregister(&xdev->common);\n\n\tfor (i = 0; i < xdev->nr_channels; i++)\n\t\tif (xdev->chan[i])\n\t\t\txilinx_dma_chan_remove(xdev->chan[i]);\n\n\txdma_disable_allclks(xdev);\n\n\treturn 0;\n}\n\nstatic struct platform_driver xilinx_vdma_driver = {\n\t.driver = {\n\t\t.name = \"xilinx-vdma\",\n\t\t.of_match_table = xilinx_dma_of_ids,\n\t},\n\t.probe = xilinx_dma_probe,\n\t.remove = xilinx_dma_remove,\n};\n\nmodule_platform_driver(xilinx_vdma_driver);\n\nMODULE_AUTHOR(\"Xilinx, Inc. and Xianjun Jiao\");\nMODULE_DESCRIPTION(\"Xilinx VDMA driver\");\nMODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "driver/xpu/Makefile",
    "content": "# by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be\n\nobj-m += xpu.o\n\nall:\n\tmake -C $(KDIR) M=$(PWD) modules\n\t# ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-\n\nclean:\n\trm -f *.ko *.o *.mod.o *.mod.c *.symvers *.order\n\n"
  },
  {
    "path": "driver/xpu/xpu.c",
    "content": "/*\n * axi lite register access driver\n * Author: Xianjun Jiao, Michael Mehari, Wei Liu\n * SPDX-FileCopyrightText: 2019 UGent\n * SPDX-License-Identifier: AGPL-3.0-or-later\n*/\n\n#include <linux/bitops.h>\n#include <linux/dmapool.h>\n#include <linux/dma/xilinx_dma.h>\n#include <linux/init.h>\n#include <linux/interrupt.h>\n#include <linux/io.h>\n#include <linux/iopoll.h>\n#include <linux/module.h>\n#include <linux/of_address.h>\n#include <linux/of_dma.h>\n#include <linux/of_platform.h>\n#include <linux/of_irq.h>\n#include <linux/slab.h>\n#include <linux/clk.h>\n#include <linux/io-64-nonatomic-lo-hi.h>\n#include <linux/delay.h>\n#include <net/mac80211.h>\n\n#include \"../hw_def.h\"\n\nstatic void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design\n\n/* IO accessors */\nstatic inline u32 reg_read(u32 reg)\n{\n\treturn ioread32(base_addr + reg);\n}\n\nstatic inline void reg_write(u32 reg, u32 value)\n{\n\tiowrite32(value, base_addr + reg);\n}\n\nstatic inline void XPU_REG_MULTI_RST_write(u32 Data) {\n\treg_write(XPU_REG_MULTI_RST_ADDR, Data);\n}\n\nstatic inline u32 XPU_REG_MULTI_RST_read(void){\n\treturn reg_read(XPU_REG_MULTI_RST_ADDR);\n}\n\nstatic inline void XPU_REG_SRC_SEL_write(u32 Data) {\n\treg_write(XPU_REG_SRC_SEL_ADDR, Data);\n}\n\nstatic inline u32 XPU_REG_SRC_SEL_read(void){\n\treturn reg_read(XPU_REG_SRC_SEL_ADDR);\n}\n\nstatic inline void XPU_REG_RECV_ACK_COUNT_TOP0_write(u32 Data) {\n\treg_write(XPU_REG_RECV_ACK_COUNT_TOP0_ADDR, Data);\n}\n\nstatic inline u32 XPU_REG_RECV_ACK_COUNT_TOP0_read(void){\n\treturn reg_read(XPU_REG_RECV_ACK_COUNT_TOP0_ADDR);\n}\n\nstatic inline void XPU_REG_RECV_ACK_COUNT_TOP1_write(u32 Data) {\n\treg_write(XPU_REG_RECV_ACK_COUNT_TOP1_ADDR, Data);\n}\n\nstatic inline u32 XPU_REG_RECV_ACK_COUNT_TOP1_read(void){\n\treturn reg_read(XPU_REG_RECV_ACK_COUNT_TOP1_ADDR);\n}\n\nstatic inline void XPU_REG_SEND_ACK_WAIT_TOP_write(u32 Data) {\n\treg_write(XPU_REG_SEND_ACK_WAIT_TOP_ADDR, Data);\n}\n\nstatic inline u32 XPU_REG_SEND_ACK_WAIT_TOP_read(void){\n\treturn reg_read(XPU_REG_SEND_ACK_WAIT_TOP_ADDR);\n}\n\nstatic inline void XPU_REG_FILTER_FLAG_write(u32 Data) {\n\treg_write(XPU_REG_FILTER_FLAG_ADDR, Data);\n}\n\nstatic inline u32 XPU_REG_FILTER_FLAG_read(void){\n\treturn reg_read(XPU_REG_FILTER_FLAG_ADDR);\n}\n\nstatic inline void XPU_REG_CTS_TO_RTS_CONFIG_write(u32 Data) {\n\treg_write(XPU_REG_CTS_TO_RTS_CONFIG_ADDR, Data);\n}\n\nstatic inline u32 XPU_REG_CTS_TO_RTS_CONFIG_read(void){\n\treturn reg_read(XPU_REG_CTS_TO_RTS_CONFIG_ADDR);\n}\n\nstatic inline void XPU_REG_MAC_ADDR_LOW_write(u32 Data) {\n\treg_write(XPU_REG_MAC_ADDR_LOW_ADDR, Data);\n}\n\nstatic inline u32 XPU_REG_MAC_ADDR_LOW_read(void){\n\treturn reg_read(XPU_REG_MAC_ADDR_LOW_ADDR);\n}\n\nstatic inline void XPU_REG_MAC_ADDR_HIGH_write(u32 Data) {\n\treg_write(XPU_REG_MAC_ADDR_HIGH_ADDR, Data);\n}\n\nstatic inline u32 XPU_REG_MAC_ADDR_HIGH_read(void){\n\treturn reg_read(XPU_REG_MAC_ADDR_HIGH_ADDR);\n}\n\nstatic inline void XPU_REG_BSSID_FILTER_LOW_write(u32 Data) {\n\treg_write(XPU_REG_BSSID_FILTER_LOW_ADDR, Data);\n}\n\nstatic inline u32 XPU_REG_BSSID_FILTER_LOW_read(void){\n\treturn reg_read(XPU_REG_BSSID_FILTER_LOW_ADDR);\n}\n\nstatic inline void XPU_REG_BSSID_FILTER_HIGH_write(u32 Data) {\n\treg_write(XPU_REG_BSSID_FILTER_HIGH_ADDR, Data);\n}\n\nstatic inline u32 XPU_REG_BSSID_FILTER_HIGH_read(void){\n\treturn reg_read(XPU_REG_BSSID_FILTER_HIGH_ADDR);\n}\n\nstatic inline void XPU_REG_BAND_CHANNEL_write(u32 Data) {\n\treg_write(XPU_REG_BAND_CHANNEL_ADDR, Data);\n}\n\nstatic inline u32 XPU_REG_BAND_CHANNEL_read(void){\n\treturn reg_read(XPU_REG_BAND_CHANNEL_ADDR);\n}\n\nstatic inline void XPU_REG_DIFS_ADVANCE_write(u32 Data) {\n\treg_write(XPU_REG_DIFS_ADVANCE_ADDR, Data);\n}\n\nstatic inline u32 XPU_REG_DIFS_ADVANCE_read(void){\n\treturn reg_read(XPU_REG_DIFS_ADVANCE_ADDR);\n}\n\nstatic inline void XPU_REG_FORCE_IDLE_MISC_write(u32 Data) {\n\treg_write(XPU_REG_FORCE_IDLE_MISC_ADDR, Data);\n}\n\nstatic inline u32 XPU_REG_FORCE_IDLE_MISC_read(void){\n\treturn reg_read(XPU_REG_FORCE_IDLE_MISC_ADDR);\n}\n\nstatic inline u32 XPU_REG_TSF_RUNTIME_VAL_LOW_read(void){\n\treturn reg_read(XPU_REG_TSF_RUNTIME_VAL_LOW_ADDR);\n}\n\nstatic inline u32 XPU_REG_TSF_RUNTIME_VAL_HIGH_read(void){\n\treturn reg_read(XPU_REG_TSF_RUNTIME_VAL_HIGH_ADDR);\n}\n\nstatic inline void XPU_REG_TSF_LOAD_VAL_LOW_write(u32 value){\n\treg_write(XPU_REG_TSF_LOAD_VAL_LOW_ADDR, value);\n}\n\nstatic inline void XPU_REG_TSF_LOAD_VAL_HIGH_write(u32 value){\n\treg_write(XPU_REG_TSF_LOAD_VAL_HIGH_ADDR, value);\n}\n\nstatic inline void XPU_REG_TSF_LOAD_VAL_write(u32 high_value, u32 low_value){\n\tXPU_REG_TSF_LOAD_VAL_LOW_write(low_value);\n\tXPU_REG_TSF_LOAD_VAL_HIGH_write(high_value|0x80000000); // msb high\n\tXPU_REG_TSF_LOAD_VAL_HIGH_write(high_value&(~0x80000000)); // msb low\n}\n\nstatic inline void XPU_REG_LBT_TH_write(u32 value) {\n\treg_write(XPU_REG_LBT_TH_ADDR, value);\n}\n\nstatic inline u32 XPU_REG_RSSI_DB_CFG_read(void){\n\treturn reg_read(XPU_REG_RSSI_DB_CFG_ADDR);\n}\n\nstatic inline void XPU_REG_RSSI_DB_CFG_write(u32 Data) {\n\treg_write(XPU_REG_RSSI_DB_CFG_ADDR, Data);\n}\n\nstatic inline u32 XPU_REG_LBT_TH_read(void){\n\treturn reg_read(XPU_REG_LBT_TH_ADDR);\n}\n\nstatic inline void XPU_REG_CSMA_DEBUG_write(u32 value){\n\treg_write(XPU_REG_CSMA_DEBUG_ADDR, value);\n}\n\nstatic inline u32 XPU_REG_CSMA_DEBUG_read(void){\n\treturn reg_read(XPU_REG_CSMA_DEBUG_ADDR);\n}\n\nstatic inline void XPU_REG_CSMA_CFG_write(u32 value){\n\treg_write(XPU_REG_CSMA_CFG_ADDR, value);\n}\n\nstatic inline u32 XPU_REG_CSMA_CFG_read(void){\n\treturn reg_read(XPU_REG_CSMA_CFG_ADDR);\n}\n\nstatic inline void XPU_REG_SLICE_COUNT_TOTAL_write(u32 value){\n\treg_write(XPU_REG_SLICE_COUNT_TOTAL_ADDR, value);\n}\nstatic inline void XPU_REG_SLICE_COUNT_START_write(u32 value){\n\treg_write(XPU_REG_SLICE_COUNT_START_ADDR, value);\n}\nstatic inline void XPU_REG_SLICE_COUNT_END_write(u32 value){\n\treg_write(XPU_REG_SLICE_COUNT_END_ADDR, value);\n}\n\n\nstatic inline u32 XPU_REG_SLICE_COUNT_TOTAL_read(void){\n\treturn reg_read(XPU_REG_SLICE_COUNT_TOTAL_ADDR);\n}\nstatic inline u32 XPU_REG_SLICE_COUNT_START_read(void){\n\treturn reg_read(XPU_REG_SLICE_COUNT_START_ADDR);\n}\nstatic inline u32 XPU_REG_SLICE_COUNT_END_read(void){\n\treturn reg_read(XPU_REG_SLICE_COUNT_END_ADDR);\n}\n\nstatic inline void XPU_REG_BB_RF_DELAY_write(u32 value){\n\treg_write(XPU_REG_BB_RF_DELAY_ADDR, value);\n}\n\nstatic inline void XPU_REG_ACK_CTL_MAX_NUM_RETRANS_write(u32 value){\n\treg_write(XPU_REG_ACK_CTL_MAX_NUM_RETRANS_ADDR, value);\n}\nstatic inline u32 XPU_REG_ACK_CTL_MAX_NUM_RETRANS_read(void){\n\treturn reg_read(XPU_REG_ACK_CTL_MAX_NUM_RETRANS_ADDR);\n}\n\nstatic inline void XPU_REG_AMPDU_ACTION_write(u32 Data) {\n\treg_write(XPU_REG_AMPDU_ACTION_ADDR, Data);\n}\n\nstatic inline u32 XPU_REG_AMPDU_ACTION_read(void){\n\treturn reg_read(XPU_REG_AMPDU_ACTION_ADDR);\n}\n\nstatic inline void XPU_REG_SPI_DISABLE_write(u32 Data) {\n\treg_write(XPU_REG_SPI_DISABLE_ADDR, Data);\n}\n\nstatic inline u32 XPU_REG_SPI_DISABLE_read(void){\n\treturn reg_read(XPU_REG_SPI_DISABLE_ADDR);\n}\n\nstatic inline void XPU_REG_MAC_ADDR_write(u8 *mac_addr) {//, u32 en_flag){\n\tXPU_REG_MAC_ADDR_LOW_write( *( (u32*)(mac_addr) ) );\n\tXPU_REG_MAC_ADDR_HIGH_write( *( (u16*)(mac_addr + 4) ) );\n\t#if 0\n\tif (en_flag) {\n\t\tXPU_REG_MAC_ADDR_HIGH_write( (*( (u16*)(mac_addr + 4) )) | 0x80000000 ); // 0x80000000 by default we turn on mac addr filter\n\t} else {\n\t\tXPU_REG_MAC_ADDR_HIGH_write( (*( (u16*)(mac_addr + 4) )) & 0x7FFFFFFF );\n\t}\n\t#endif\n}\n\nstatic const struct of_device_id dev_of_ids[] = {\n\t{ .compatible = \"sdr,xpu\", },\n\t{}\n};\nMODULE_DEVICE_TABLE(of, dev_of_ids);\n\nstatic struct xpu_driver_api xpu_driver_api_inst;\nstruct xpu_driver_api *xpu_api = &xpu_driver_api_inst;\nEXPORT_SYMBOL(xpu_api);\n\nstatic inline u32 hw_init(enum xpu_mode mode){\n\tint err=0, i, rssi_half_db_th, rssi_half_db_offset, agc_gain_delay;\n\t// u32 filter_flag = 0;\n\n\tprintk(\"%s hw_init mode %d\\n\", xpu_compatible_str, mode);\n\n\t//rst\n\tfor (i=0;i<8;i++)\n\t\txpu_api->XPU_REG_MULTI_RST_write(0);\n\tfor (i=0;i<32;i++)\n\t\txpu_api->XPU_REG_MULTI_RST_write(0xFFFFFFFF);\n\tfor (i=0;i<8;i++)\n\t\txpu_api->XPU_REG_MULTI_RST_write(0);\n\n\t// http://www.studioreti.it/slide/802-11-Frame_E_C.pdf\n\t// https://mrncciew.com/2014/10/14/cwap-802-11-phy-ppdu/\n\t// https://mrncciew.com/2014/09/27/cwap-mac-header-frame-control/\n\t// https://mrncciew.com/2014/10/25/cwap-mac-header-durationid/\n\t// https://mrncciew.com/2014/11/01/cwap-mac-header-sequence-control/\n\t// https://witestlab.poly.edu/blog/802-11-wireless-lan-2/\n\t// phy_rx byte idx: \n\t// 5(3 sig + 2 service), -- PHY\n\t// 2 frame control, 2 duration/conn ID, --MAC PDU\n\t// 6 receiver address, 6 destination address, 6 transmitter address\n\t// 2 sequence control\n\t// 6 source address\n\t// reg_val = 5 + 0;\n\t// xpu_api->XPU_REG_PHY_RX_PKT_READ_OFFSET_write(reg_val);\n\t// printk(\"%s hw_init XPU_REG_PHY_RX_PKT_READ_OFFSET_write %d\\n\", xpu_compatible_str, reg_val);\n\n\t// by default turn off filter, because all register are zeros\n\t// let's filter out packet according to: enum ieee80211_filter_flags at: https://www.kernel.org/doc/html/v4.9/80211/mac80211.html\n\t#if 0 // define in FPGA\n    localparam [13:0]   FIF_ALLMULTI =           14b00000000000010, //get all mac addr like 01:00:5E:xx:xx:xx and 33:33:xx:xx:xx:xx through to ARM\n                        FIF_FCSFAIL =            14b00000000000100, //not support\n                        FIF_PLCPFAIL =           14b00000000001000, //not support\n                        FIF_BCN_PRBRESP_PROMISC= 14b00000000010000, \n                        FIF_CONTROL =            14b00000000100000,\n                        FIF_OTHER_BSS =          14b00000001000000, \n                        FIF_PSPOLL =             14b00000010000000,\n                        FIF_PROBE_REQ =          14b00000100000000,\n                        UNICAST_FOR_US =         14b00001000000000,\n                        BROADCAST_ALL_ONE =      14b00010000000000,\n                        BROADCAST_ALL_ZERO =     14b00100000000000,\n                        MY_BEACON          =     14b01000000000000,\n                        MONITOR_ALL =            14b10000000000000;\n\t#endif\n\t\n  // Remove XPU_REG_FILTER_FLAG_write to avoid hw_init call in openwifi_start causing inconsistency\n  // filter_flag = (FIF_ALLMULTI|FIF_FCSFAIL|FIF_PLCPFAIL|FIF_BCN_PRBRESP_PROMISC|FIF_CONTROL|FIF_OTHER_BSS|FIF_PSPOLL|FIF_PROBE_REQ|UNICAST_FOR_US|BROADCAST_ALL_ONE|BROADCAST_ALL_ZERO|MY_BEACON|MONITOR_ALL);\n\t// xpu_api->XPU_REG_FILTER_FLAG_write(filter_flag);\n\n\txpu_api->XPU_REG_CTS_TO_RTS_CONFIG_write(0xB<<16);//6M 1011:0xB\n\n\t// after send data frame wait for ACK, this will be set in real time in function ad9361_rf_set_channel\n\t// xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2)*10)<<16) | 10 ); // high 16 bits to cover sig valid of ACK packet, low 16 bits is adjustment of fcs valid waiting time.  let's add 2us for those device that is really \"slow\"!\n\t// xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( 6*10 ); // +6 = 16us for 5GHz\n\n\t//xpu_api->XPU_REG_ACK_CTL_MAX_NUM_RETRANS_write(3); // if this > 0, it will override mac80211 set value, and set static retransmission limit\n\t\n\t// From CMW measurement: lo up 1us before the packet; lo down 0.4us after the packet/RF port switches 1.2us before and 0.2us after\n\txpu_api->XPU_REG_BB_RF_DELAY_write((16<<24)|(0<<16)|(26<<8)|9); // calibrated by ila and spectrum analyzer (trigger mode)\n\n\t// setup time schedule of all queues. all time open.\n\tfor (i=0; i<4; i++) {\n\t\txpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((i<<20)|16);//total 16us\n\t\txpu_api->XPU_REG_SLICE_COUNT_START_write((i<<20)|0); //start 0us\n\t\txpu_api->XPU_REG_SLICE_COUNT_END_write((i<<20)|16);  //end   16us\n\t}\n\n\t// all slice sync rest\n\txpu_api->XPU_REG_MULTI_RST_write(1<<7); //bit7 reset the counter for all queues at the same time\n\txpu_api->XPU_REG_MULTI_RST_write(0<<7); \n\t\n\tswitch(mode)\n\t{\n\t\tcase XPU_TEST:\n\t\t\tprintk(\"%s hw_init mode XPU_TEST\\n\", xpu_compatible_str);\n\t\t\tbreak;\n\n\t\tcase XPU_NORMAL:\n\t\t\tprintk(\"%s hw_init mode XPU_NORMAL\\n\", xpu_compatible_str);\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tprintk(\"%s hw_init mode %d is wrong!\\n\", xpu_compatible_str, mode);\n\t\t\terr=1;\n\t}\n  // Remove this XPU_REG_BAND_CHANNEL_write in xpu.c, because\n  // 1. the 44 for channel field is out dated. Now the channel actually should be frequency in MHz\n  // 2. PROBLEM! this hw_init call in openwifi_start will cause lossing consistency between XPU register and\n  // (priv->use_short_slot<<24)|(priv->band<<16)|(priv->actual_rx_lo)\n\t// xpu_api->XPU_REG_BAND_CHANNEL_write((false<<24)|(BAND_5_8GHZ<<16)|44);//use_short_slot==false; 5.8GHz; channel 44 -- default setting to sync with priv->band/channel/use_short_slot\n\n\tagc_gain_delay = 39; //samples\n\trssi_half_db_offset = 75<<1;\n\txpu_api->XPU_REG_RSSI_DB_CFG_write(0x80000000|((rssi_half_db_offset<<16)|agc_gain_delay) );\n\txpu_api->XPU_REG_RSSI_DB_CFG_write((~0x80000000)&((rssi_half_db_offset<<16)|agc_gain_delay) );\n\t\n\t//rssi_half_db_th = 70<<1; // with splitter\n\trssi_half_db_th = 87<<1; // -62dBm\n\txpu_api->XPU_REG_LBT_TH_write(rssi_half_db_th); // set IQ rssi th step .5dB to xxx and enable it\n\n  // control the duration to force ch_idle after decoding a packet due to imperfection of agc and signals\n  // (1<<26) to disable eifs_trigger_by_last_tx_fail by default (standard does not ask so)\n\txpu_api->XPU_REG_FORCE_IDLE_MISC_write((1<<26)|75);\n\n\t//xpu_api->XPU_REG_CSMA_DEBUG_write((1<<31)|(20<<24)|(4<<19)|(3<<14)|(10<<7)|(5));\n\txpu_api->XPU_REG_CSMA_DEBUG_write(0);\n\t\n\t// xpu_api->XPU_REG_CSMA_CFG_write(268435459);  // Linux will do config for each queue via openwifi_conf_tx\n\t// xpu_api->XPU_REG_CSMA_CFG_write(0xe0000000); // Linux will do config for each queue via openwifi_conf_tx\n\n//\t// ------- assume 2.4 and 5GHz have the same SIFS (6us signal extension) --------\n\txpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((16+25+7-3+8-2)<<16)|((16+25+7-3+8-2)<<0) ); //+7 according to the ACK timing check by IQ sample: iq_ack_timing.md. -3 after Colvin LLR. +8 after new faster dac intf. -2 calibration in Oct. 2024\n\txpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (1<<31) | (((51+2+2)*10 + 15)<<16) | (10+3) );//2.4GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M). +3 after Colvin LLR\n\txpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (1<<31) | (((51+2+2)*10 + 15)<<16) | (10+3) );//5GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M). +3 after Colvin LLR\n//\t// ------- assume 2.4 and 5GHz have different SIFS --------\n\t// xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((16+23)<<16)|(0+23) );\n\t// xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (1<<31) | (((45+2+2)*10 + 15)<<16) | 10 );//2.4GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)\n\t// xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (1<<31) | (((51+2+2)*10 + 15)<<16) | 10 );//5GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)\n\n\txpu_api->XPU_REG_DIFS_ADVANCE_write((OPENWIFI_MAX_SIGNAL_LEN_TH<<16)|2); //us. bit31~16 max pkt length threshold\n\n\tprintk(\"%s hw_init err %d\\n\", xpu_compatible_str, err);\n\treturn(err);\n}\n\nstatic int dev_probe(struct platform_device *pdev)\n{\n\tstruct device_node *np = pdev->dev.of_node;\n\tstruct resource *io;\n\tu32 test_us0, test_us1, test_us2;\n\tint err=1;\n\n\tprintk(\"\\n\");\n\n\tif (np) {\n\t\tconst struct of_device_id *match;\n\n\t\tmatch = of_match_node(dev_of_ids, np);\n\t\tif (match) {\n\t\t\tprintk(\"%s dev_probe match!\\n\", xpu_compatible_str);\n\t\t\terr = 0;\n\t\t}\n\t}\n\n\tif (err)\n\t\treturn err;\n\n\txpu_api->hw_init=hw_init;\n\n\txpu_api->reg_read=reg_read;\n\txpu_api->reg_write=reg_write;\n\n\txpu_api->XPU_REG_MULTI_RST_write=XPU_REG_MULTI_RST_write;\n\txpu_api->XPU_REG_MULTI_RST_read=XPU_REG_MULTI_RST_read;\n\txpu_api->XPU_REG_SRC_SEL_write=XPU_REG_SRC_SEL_write;\n\txpu_api->XPU_REG_SRC_SEL_read=XPU_REG_SRC_SEL_read;\n\n\txpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write=XPU_REG_RECV_ACK_COUNT_TOP0_write;\n\txpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_read=XPU_REG_RECV_ACK_COUNT_TOP0_read;\n\txpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write=XPU_REG_RECV_ACK_COUNT_TOP1_write;\n\txpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_read=XPU_REG_RECV_ACK_COUNT_TOP1_read;\n\txpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write=XPU_REG_SEND_ACK_WAIT_TOP_write;\n\txpu_api->XPU_REG_SEND_ACK_WAIT_TOP_read=XPU_REG_SEND_ACK_WAIT_TOP_read;\n\txpu_api->XPU_REG_MAC_ADDR_LOW_write=XPU_REG_MAC_ADDR_LOW_write;\n\txpu_api->XPU_REG_MAC_ADDR_LOW_read=XPU_REG_MAC_ADDR_LOW_read;\n\txpu_api->XPU_REG_MAC_ADDR_HIGH_write=XPU_REG_MAC_ADDR_HIGH_write;\n\txpu_api->XPU_REG_MAC_ADDR_HIGH_read=XPU_REG_MAC_ADDR_HIGH_read;\n\n\txpu_api->XPU_REG_FILTER_FLAG_write=XPU_REG_FILTER_FLAG_write;\n\txpu_api->XPU_REG_FILTER_FLAG_read=XPU_REG_FILTER_FLAG_read;\n\txpu_api->XPU_REG_CTS_TO_RTS_CONFIG_write=XPU_REG_CTS_TO_RTS_CONFIG_write;\n\txpu_api->XPU_REG_CTS_TO_RTS_CONFIG_read=XPU_REG_CTS_TO_RTS_CONFIG_read;\n\txpu_api->XPU_REG_BSSID_FILTER_LOW_write=XPU_REG_BSSID_FILTER_LOW_write;\n\txpu_api->XPU_REG_BSSID_FILTER_LOW_read=XPU_REG_BSSID_FILTER_LOW_read;\n\txpu_api->XPU_REG_BSSID_FILTER_HIGH_write=XPU_REG_BSSID_FILTER_HIGH_write;\n\txpu_api->XPU_REG_BSSID_FILTER_HIGH_read=XPU_REG_BSSID_FILTER_HIGH_read;\n\n\txpu_api->XPU_REG_BAND_CHANNEL_write=XPU_REG_BAND_CHANNEL_write;\n\txpu_api->XPU_REG_BAND_CHANNEL_read=XPU_REG_BAND_CHANNEL_read;\n\n\txpu_api->XPU_REG_DIFS_ADVANCE_write=XPU_REG_DIFS_ADVANCE_write;\n\txpu_api->XPU_REG_DIFS_ADVANCE_read=XPU_REG_DIFS_ADVANCE_read;\n\n\txpu_api->XPU_REG_FORCE_IDLE_MISC_write=XPU_REG_FORCE_IDLE_MISC_write;\n\txpu_api->XPU_REG_FORCE_IDLE_MISC_read=XPU_REG_FORCE_IDLE_MISC_read;\n\n\txpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read=XPU_REG_TSF_RUNTIME_VAL_LOW_read;\n\txpu_api->XPU_REG_TSF_RUNTIME_VAL_HIGH_read=XPU_REG_TSF_RUNTIME_VAL_HIGH_read;\n\txpu_api->XPU_REG_TSF_LOAD_VAL_LOW_write=XPU_REG_TSF_LOAD_VAL_LOW_write;\n\txpu_api->XPU_REG_TSF_LOAD_VAL_HIGH_write=XPU_REG_TSF_LOAD_VAL_HIGH_write;\n\txpu_api->XPU_REG_TSF_LOAD_VAL_write=XPU_REG_TSF_LOAD_VAL_write;\n\t\n\txpu_api->XPU_REG_LBT_TH_write=XPU_REG_LBT_TH_write;\n\txpu_api->XPU_REG_LBT_TH_read=XPU_REG_LBT_TH_read;\n\n\txpu_api->XPU_REG_RSSI_DB_CFG_read=XPU_REG_RSSI_DB_CFG_read;\n\txpu_api->XPU_REG_RSSI_DB_CFG_write=XPU_REG_RSSI_DB_CFG_write;\n\n\txpu_api->XPU_REG_CSMA_DEBUG_write=XPU_REG_CSMA_DEBUG_write;\n\txpu_api->XPU_REG_CSMA_DEBUG_read=XPU_REG_CSMA_DEBUG_read;\n\n\txpu_api->XPU_REG_CSMA_CFG_write=XPU_REG_CSMA_CFG_write;\n\txpu_api->XPU_REG_CSMA_CFG_read=XPU_REG_CSMA_CFG_read;\n\n\txpu_api->XPU_REG_SLICE_COUNT_TOTAL_write=XPU_REG_SLICE_COUNT_TOTAL_write;\n\txpu_api->XPU_REG_SLICE_COUNT_START_write=XPU_REG_SLICE_COUNT_START_write;\n\txpu_api->XPU_REG_SLICE_COUNT_END_write=XPU_REG_SLICE_COUNT_END_write;\n\n\txpu_api->XPU_REG_SLICE_COUNT_TOTAL_read=XPU_REG_SLICE_COUNT_TOTAL_read;\n\txpu_api->XPU_REG_SLICE_COUNT_START_read=XPU_REG_SLICE_COUNT_START_read;\n\txpu_api->XPU_REG_SLICE_COUNT_END_read=XPU_REG_SLICE_COUNT_END_read;\n\n\txpu_api->XPU_REG_BB_RF_DELAY_write=XPU_REG_BB_RF_DELAY_write;\n\n\txpu_api->XPU_REG_ACK_CTL_MAX_NUM_RETRANS_write=XPU_REG_ACK_CTL_MAX_NUM_RETRANS_write;\n\txpu_api->XPU_REG_ACK_CTL_MAX_NUM_RETRANS_read=XPU_REG_ACK_CTL_MAX_NUM_RETRANS_read;\n\n\txpu_api->XPU_REG_AMPDU_ACTION_write=XPU_REG_AMPDU_ACTION_write;\n\txpu_api->XPU_REG_AMPDU_ACTION_read=XPU_REG_AMPDU_ACTION_read;\n\n\txpu_api->XPU_REG_SPI_DISABLE_write=XPU_REG_SPI_DISABLE_write;\n\txpu_api->XPU_REG_SPI_DISABLE_read=XPU_REG_SPI_DISABLE_read;\t\n\n\txpu_api->XPU_REG_MAC_ADDR_write=XPU_REG_MAC_ADDR_write;\n\n\t/* Request and map I/O memory */\n\tio = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n\tbase_addr = devm_ioremap_resource(&pdev->dev, io);\n\tif (IS_ERR(base_addr))\n\t\treturn PTR_ERR(base_addr);\n\n\tprintk(\"%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\\n\", xpu_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc);\n\tprintk(\"%s dev_probe base_addr 0x%08x\\n\", xpu_compatible_str,(u32)base_addr);\n\tprintk(\"%s dev_probe xpu_driver_api_inst 0x%08x\\n\", xpu_compatible_str, (u32)&xpu_driver_api_inst);\n\tprintk(\"%s dev_probe             xpu_api 0x%08x\\n\", xpu_compatible_str, (u32)xpu_api);\n\n\tprintk(\"%s dev_probe reset tsf timer\\n\", xpu_compatible_str);\n\txpu_api->XPU_REG_TSF_LOAD_VAL_write(0,0);\n\ttest_us0 = xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read();\n\tmdelay(33);\n\ttest_us1 = xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read();\n\tmdelay(67);\n\ttest_us2 = xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read();\n\tprintk(\"%s dev_probe XPU_REG_TSF_RUNTIME_VAL_LOW_read %d %d %dus\\n\", xpu_compatible_str, test_us0, test_us1, test_us2);\n\n\tprintk(\"%s dev_probe succeed!\\n\", xpu_compatible_str);\n\n\terr = hw_init(XPU_NORMAL);\n\n\treturn err;\n}\n\nstatic int dev_remove(struct platform_device *pdev)\n{\n\tprintk(\"\\n\");\n\n\tprintk(\"%s dev_remove base_addr 0x%08x\\n\", xpu_compatible_str,(u32)base_addr);\n\tprintk(\"%s dev_remove xpu_driver_api_inst 0x%08x\\n\", xpu_compatible_str, (u32)&xpu_driver_api_inst);\n\tprintk(\"%s dev_remove             xpu_api 0x%08x\\n\", xpu_compatible_str, (u32)xpu_api);\n\n\tprintk(\"%s dev_remove succeed!\\n\", xpu_compatible_str);\n\treturn 0;\n}\n\nstatic struct platform_driver dev_driver = {\n\t.driver = {\n\t\t.name = \"sdr,xpu\",\n\t\t.owner = THIS_MODULE,\n\t\t.of_match_table = dev_of_ids,\n\t},\n\t.probe = dev_probe,\n\t.remove = dev_remove,\n};\n\nmodule_platform_driver(dev_driver);\n\nMODULE_AUTHOR(\"Xianjun Jiao\");\nMODULE_DESCRIPTION(\"sdr,xpu\");\nMODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "kernel_boot/10-network-device.rules",
    "content": "SUBSYSTEM==\"net\", ACTION==\"add\", ATTR{address}==\"66:55:44:33:22:*\", NAME=\"sdr0\"\n"
  },
  {
    "path": "kernel_boot/70-persistent-net.rules",
    "content": "SUBSYSTEM==\"net\", ACTION==\"add\", DRIVERS==\"?*\", ATTR{address}==\"66:55:44:33:22:*\", ATTR{dev_id}==\"0x0\", ATTR{type}==\"1\", KERNEL==\"wlan*\", NAME=\"sdr0\"\n"
  },
  {
    "path": "kernel_boot/ad9361.patch",
    "content": "diff --git a/drivers/iio/adc/ad9361.c b/drivers/iio/adc/ad9361.c\nindex 91f166675024..8403edc6f482 100644\n--- a/drivers/iio/adc/ad9361.c\n+++ b/drivers/iio/adc/ad9361.c\n@@ -1234,7 +1234,7 @@ static int ad9361_load_mixer_gm_subtable(struct ad9361_rf_phy *phy)\n \treturn 0;\n }\n \n-static int ad9361_set_tx_atten(struct ad9361_rf_phy *phy, u32 atten_mdb,\n+int ad9361_set_tx_atten(struct ad9361_rf_phy *phy, u32 atten_mdb,\n \t\t\t       bool tx1, bool tx2, bool immed)\n {\n \tu8 buf[2];\n@@ -1266,8 +1266,9 @@ static int ad9361_set_tx_atten(struct ad9361_rf_phy *phy, u32 atten_mdb,\n \n \treturn ret;\n }\n+EXPORT_SYMBOL(ad9361_set_tx_atten);\n \n-static int ad9361_get_tx_atten(struct ad9361_rf_phy *phy, u32 tx_num)\n+int ad9361_get_tx_atten(struct ad9361_rf_phy *phy, u32 tx_num)\n {\n \tu8 buf[2];\n \tint ret = 0;\n@@ -1285,6 +1286,7 @@ static int ad9361_get_tx_atten(struct ad9361_rf_phy *phy, u32 tx_num)\n \n \treturn code;\n }\n+EXPORT_SYMBOL(ad9361_get_tx_atten);\n \n int ad9361_tx_mute(struct ad9361_rf_phy *phy, u32 state)\n {\n@@ -3449,6 +3451,8 @@ static int ad9361_gc_setup(struct ad9361_rf_phy *phy, struct gain_control *ctrl)\n \t\t\t  AGCLL_MAX_INCREASE(~0),  reg);\n \n \t/* Fast AGC - Peak Detectors and Final Settling */\n+  ad9361_spi_writef(spi, REG_AGC_LOCK_LEVEL, ENABLE_DIG_SAT_OVRG, ctrl->f_agc_dig_sat_ovrg_en);\n+\n \treg = ctrl->f_agc_lpf_final_settling_steps;\n \treg = clamp_t(u32, reg, 0U, 3U);\n \tad9361_spi_writef(spi, REG_FAST_ENERGY_LOST_THRESH,\n@@ -3744,7 +3748,7 @@ static int ad9361_get_auxadc(struct ad9361_rf_phy *phy)\n   // Setup Control Outs\n   //************************************************************\n \n-static int ad9361_ctrl_outs_setup(struct ad9361_rf_phy *phy,\n+int ad9361_ctrl_outs_setup(struct ad9361_rf_phy *phy,\n \t\t\t\t  struct ctrl_outs_control *ctrl)\n {\n \tstruct spi_device *spi = phy->spi;\n@@ -3754,6 +3758,7 @@ static int ad9361_ctrl_outs_setup(struct ad9361_rf_phy *phy,\n \tad9361_spi_write(spi, REG_CTRL_OUTPUT_POINTER, ctrl->index); // Ctrl Out index\n \treturn ad9361_spi_write(spi, REG_CTRL_OUTPUT_ENABLE, ctrl->en_mask); // Ctrl Out [7:0] output enable\n }\n+EXPORT_SYMBOL(ad9361_ctrl_outs_setup);\n   //************************************************************\n   // Setup GPO\n   //************************************************************\n@@ -5252,7 +5257,7 @@ static int ad9361_setup(struct ad9361_rf_phy *phy)\n \n }\n \n-static int ad9361_do_calib_run(struct ad9361_rf_phy *phy, u32 cal, int arg)\n+int ad9361_do_calib_run(struct ad9361_rf_phy *phy, u32 cal, int arg)\n {\n \tstruct ad9361_rf_phy_state *st = phy->state;\n \tint ret;\n@@ -5285,6 +5290,7 @@ static int ad9361_do_calib_run(struct ad9361_rf_phy *phy, u32 cal, int arg)\n \n \treturn ret;\n }\n+EXPORT_SYMBOL(ad9361_do_calib_run);\n \n static int ad9361_update_rf_bandwidth(struct ad9361_rf_phy *phy,\n \t\t\t\t     u32 rf_rx_bw, u32 rf_tx_bw)\n@@ -8906,6 +8912,8 @@ static struct ad9361_phy_platform_data\n \tad9361_of_get_u32(iodev, np, \"adi,fagc-lock-level-gain-increase-upper-limit\", 5,\n \t\t\t&pdata->gain_ctrl.f_agc_lock_level_gain_increase_upper_limit); /* 0x118 0..63 */\n \t\t/* Fast AGC - Peak Detectors and Final Settling */\n+  ad9361_of_get_bool(iodev, np, \"adi,fagc-dig-sat-ovrg-enable\",\n+\t    &pdata->gain_ctrl.f_agc_dig_sat_ovrg_en); /* 0x101:7 (full table) */\n \tad9361_of_get_u32(iodev, np, \"adi,fagc-lpf-final-settling-steps\", 1,\n \t\t\t&pdata->gain_ctrl.f_agc_lpf_final_settling_steps); /* 0x112:6 0..3 (Post Lock Level Step)*/\n \tad9361_of_get_u32(iodev, np, \"adi,fagc-lmt-final-settling-steps\", 1,\n"
  },
  {
    "path": "kernel_boot/ad9361_conv.patch",
    "content": "diff --git a/drivers/iio/adc/ad9361_conv.c b/drivers/iio/adc/ad9361_conv.c\nindex 1902e7d07501..ef421dbd5e70 100644\n--- a/drivers/iio/adc/ad9361_conv.c\n+++ b/drivers/iio/adc/ad9361_conv.c\n@@ -449,7 +449,8 @@ static int ad9361_dig_tune_delay(struct ad9361_rf_phy *phy,\n \t\t\t\t unsigned long max_freq,\n \t\t\t\t enum dig_tune_flags flags, bool tx)\n {\n-\tstatic const unsigned int rates[3] = {25000000U, 40000000U, 61440000U};\n+\t// static const unsigned int rates[3] = {25000000U, 40000000U, 61440000U};\n+\tstatic const unsigned int rates[3] = {25000000U, 40000000U, 40000000U};\n \tstruct axiadc_converter *conv = spi_get_drvdata(phy->spi);\n \tunsigned int s0, s1, c0, c1;\n \tunsigned int i, j, r;\n"
  },
  {
    "path": "kernel_boot/ad9361_private.patch",
    "content": "diff --git a/drivers/iio/adc/ad9361_private.h b/drivers/iio/adc/ad9361_private.h\nindex dfffc4fa88a9..99dadf844614 100644\n--- a/drivers/iio/adc/ad9361_private.h\n+++ b/drivers/iio/adc/ad9361_private.h\n@@ -127,6 +127,7 @@ struct gain_control {\n \tu8 f_agc_lp_thresh_increment_steps; /* 0x117 1..8 */\n \n \t/* Fast AGC - Lock Level */\n+  bool f_agc_dig_sat_ovrg_en; /* 0x101:7 Enable digital saturation cause gain decrease */\n \tu8 f_agc_lock_level; /* NOT USED: 0x101 0..-127 dBFS same as agc_inner_thresh_high */\n \tbool f_agc_lock_level_lmt_gain_increase_en; /* 0x111:6 */\n \tu8 f_agc_lock_level_gain_increase_upper_limit; /* 0x118 0..63 */\n"
  },
  {
    "path": "kernel_boot/axi_hdmi_crtc.patch",
    "content": "diff --git a/drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_crtc.c b/drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_crtc.c\nindex e8241767b9f9..37809fc10bde 100644\n--- a/drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_crtc.c\n+++ b/drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_crtc.c\n@@ -54,7 +54,7 @@ static struct dma_async_tx_descriptor *axi_hdmi_vdma_prep_interleaved_desc(\n \t\tmemset(&vdma_config, 0, sizeof(vdma_config));\n \t\tvdma_config.park = 1;\n \t\tvdma_config.coalesc = 0xff;\n-\t\txilinx_vdma_channel_set_config(axi_hdmi_crtc->dma, &vdma_config);\n+\t\t// xilinx_vdma_channel_set_config(axi_hdmi_crtc->dma, &vdma_config);\n \t}\n #endif\n \n"
  },
  {
    "path": "kernel_boot/boards/adrv9361z7035/devicetree.dts",
    "content": "/dts-v1/;\n\n/ {\n\t#address-cells = <0x1>;\n\t#size-cells = <0x1>;\n\tcompatible = \"xlnx,zynq-7000\";\n\tinterrupt-parent = <0x1>;\n\tmodel = \"Analog Devices ADRV9361-Z7035 (Z7035/AD9361)\";\n\n\tcpus {\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0x0>;\n\t\t\tclocks = <0x2 0x3>;\n\t\t\tclock-latency = <0x3e8>;\n\t\t\tcpu0-supply = <0x3>;\n\t\t\toperating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0x1>;\n\t\t\tclocks = <0x2 0x3>;\n\t\t};\n\t};\n\n\tfpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <0x4>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tranges;\n\t};\n\n\tpmu@f8891000 {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0x0 0x5 0x4 0x0 0x6 0x4>;\n\t\tinterrupt-parent = <0x1>;\n\t\treg = <0xf8891000 0x1000 0xf8893000 0x1000>;\n\t};\n\n\tfixedregulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <0xf4240>;\n\t\tregulator-max-microvolt = <0xf4240>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t\tlinux,phandle = <0x3>;\n\t\tphandle = <0x3>;\n\t};\n\n\tamba {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tinterrupt-parent = <0x1>;\n\t\tranges;\n\n\t\tadc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0x0 0x7 0x4>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tclocks = <0x2 0xc>;\n\t\t};\n\n\t\tcan@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x13 0x2 0x24>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0x0 0x1c 0x4>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x14 0x2 0x25>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0x0 0x33 0x4>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tclocks = <0x2 0x2a>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <0x2>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x14 0x4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t\tlinux,phandle = <0x6>;\n\t\t\tphandle = <0x6>;\n\t\t};\n\n\t\ti2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x26>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x19 0x4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t};\n\n\t\ti2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x27>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x30 0x4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t};\n\n\t\tinterrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <0x3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xf8f01000 0x1000 0xf8f00100 0x100>;\n\t\t\tlinux,phandle = <0x1>;\n\t\t\tphandle = <0x1>;\n\t\t};\n\n\t\tcache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xf8f02000 0x1000>;\n\t\t\tinterrupts = <0x0 0x2 0x4>;\n\t\t\tarm,data-latency = <0x3 0x2 0x2>;\n\t\t\tarm,tag-latency = <0x2 0x2 0x2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <0x2>;\n\t\t};\n\n\t\tmemory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x3 0x4>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t};\n\n\t\tserial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x17 0x2 0x28>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xe0000000 0x1000>;\n\t\t\tinterrupts = <0x0 0x1b 0x4>;\n\t\t};\n\n\t\tserial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"okay\";\n\t\t\tclocks = <0x2 0x18 0x2 0x29>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xe0001000 0x1000>;\n\t\t\tinterrupts = <0x0 0x32 0x4>;\n\t\t};\n\n\t\tspi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x1a 0x4>;\n\t\t\tclocks = <0x2 0x19 0x2 0x22>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\n\t\t\tad9361-phy@0 {\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x0>;\n\t\t\t\t#clock-cells = <0x1>;\n\t\t\t\tcompatible = \"adi,ad9361\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tspi-cpha;\n\t\t\t\tspi-max-frequency = <0x989680>;\n\t\t\t\tclocks = <0x5 0x0>;\n\t\t\t\tclock-names = \"ad9361_ext_refclk\";\n\t\t\t\tclock-output-names = \"rx_sampl_clk\", \"tx_sampl_clk\";\n\t\t\t\tadi,digital-interface-tune-skip-mode = <0x0>;\n\t\t\t\tadi,pp-tx-swap-enable;\n\t\t\t\tadi,pp-rx-swap-enable;\n\t\t\t\tadi,rx-frame-pulse-mode-enable;\n\t\t\t\tadi,lvds-mode-enable;\n\t\t\t\tadi,lvds-bias-mV = <0x96>;\n\t\t\t\tadi,lvds-rx-onchip-termination-enable;\n\t\t\t\tadi,rx-data-delay = <0x4>;\n\t\t\t\tadi,tx-fb-clock-delay = <0x7>;\n\t\t\t\tadi,xo-disable-use-ext-refclk-enable;\n\t\t\t\tadi,2rx-2tx-mode-enable;\n\t\t\t\tadi,frequency-division-duplex-mode-enable;\n\t\t\t\tadi,rx-rf-port-input-select = <0x0>;\n\t\t\t\tadi,tx-rf-port-input-select = <0x0>;\n\t\t\t\tadi,tx-attenuation-mdB = <0x2710>;\n\t\t\t\tadi,tx-lo-powerdown-managed-enable;\n\t\t\t\tadi,rf-rx-bandwidth-hz = <0x112a880>;\n\t\t\t\tadi,rf-tx-bandwidth-hz = <0x112a880>;\n\t\t\t\tadi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;\n\t\t\t\tadi,tx-synthesizer-frequency-hz = <0x0 0x92080880>;\n\t\t\t\tadi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;\n\t\t\t\tadi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;\n\t\t\t\tadi,gc-rx1-mode = <0x2>;\n\t\t\t\tadi,gc-rx2-mode = <0x2>;\n\t\t\t\tadi,gc-adc-ovr-sample-size = <0x4>;\n\t\t\t\tadi,gc-adc-small-overload-thresh = <0x2f>;\n\t\t\t\tadi,gc-adc-large-overload-thresh = <0x3a>;\n\t\t\t\tadi,gc-lmt-overload-high-thresh = <0x320>;\n\t\t\t\tadi,gc-lmt-overload-low-thresh = <0x2c0>;\n\t\t\t\tadi,gc-dec-pow-measurement-duration = <0x2000>;\n\t\t\t\tadi,gc-low-power-thresh = <0x18>;\n\t\t\t\tadi,mgc-inc-gain-step = <0x2>;\n\t\t\t\tadi,mgc-dec-gain-step = <0x2>;\n\t\t\t\tadi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;\n\t\t\t\tadi,agc-attack-delay-extra-margin-us = <0x1>;\n\t\t\t\tadi,agc-outer-thresh-high = <0x5>;\n\t\t\t\tadi,agc-outer-thresh-high-dec-steps = <0x2>;\n\t\t\t\tadi,agc-inner-thresh-high = <0xa>;\n\t\t\t\tadi,agc-inner-thresh-high-dec-steps = <0x1>;\n\t\t\t\tadi,agc-inner-thresh-low = <0xc>;\n\t\t\t\tadi,agc-inner-thresh-low-inc-steps = <0x1>;\n\t\t\t\tadi,agc-outer-thresh-low = <0x12>;\n\t\t\t\tadi,agc-outer-thresh-low-inc-steps = <0x2>;\n\t\t\t\tadi,agc-adc-small-overload-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-adc-large-overload-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-adc-large-overload-inc-steps = <0x7>;\n\t\t\t\tadi,agc-lmt-overload-large-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-lmt-overload-small-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-lmt-overload-large-inc-steps = <0x7>;\n\t\t\t\tadi,agc-gain-update-interval-us = <0x3e8>;\n\t\t\t\tadi,fagc-dec-pow-measurement-duration = <0x10>;\n        adi,fagc-adc-large-overload-inc-steps = <0x07>;\n\t\t\t\tadi,fagc-lp-thresh-increment-steps = <0x1>;\n\t\t\t\tadi,fagc-lp-thresh-increment-time = <0x5>;\n\t\t\t\tadi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;\n        adi,fagc-dig-sat-ovrg-enable;\n\t\t\t\tadi,fagc-final-overrange-count = <0x3>;\n\t\t\t\tadi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;\n\t\t\t\tadi,fagc-lmt-final-settling-steps = <0x1>;\n\t\t\t\tadi,fagc-lock-level = <0xa>;\n\t\t\t\tadi,fagc-lock-level-gain-increase-upper-limit = <0x5>;\n\t\t\t\tadi,fagc-lock-level-lmt-gain-increase-enable;\n\t\t\t\tadi,fagc-lpf-final-settling-steps = <0x1>;\n\t\t\t\tadi,fagc-optimized-gain-offset = <0x5>;\n\t\t\t\tadi,fagc-power-measurement-duration-in-state5 = <0x10>;\n\t\t\t\tadi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;\n\t\t\t\tadi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;\n\t\t\t\tadi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;\n\t\t\t\tadi,fagc-rst-gla-large-adc-overload-enable;\n\t\t\t\tadi,fagc-rst-gla-large-lmt-overload-enable;\n\t\t\t\tadi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;\n\t\t\t\tadi,fagc-state-wait-time-ns = <0x104>;\n\t\t\t\tadi,fagc-use-last-lock-level-for-set-gain-enable;\n\t\t\t\tadi,rssi-restart-mode = <0x3>;\n\t\t\t\tadi,rssi-delay = <0x1>;\n\t\t\t\tadi,rssi-wait = <0x1>;\n\t\t\t\tadi,rssi-duration = <0x3e8>;\n\t\t\t\tadi,ctrl-outs-index = <0x0>;\n\t\t\t\tadi,ctrl-outs-enable-mask = <0xff>;\n\t\t\t\tadi,temp-sense-measurement-interval-ms = <0x3e8>;\n\t\t\t\tadi,temp-sense-offset-signed = <0xce>;\n\t\t\t\tadi,temp-sense-periodic-measurement-enable;\n\t\t\t\tadi,aux-dac-manual-mode-enable;\n\t\t\t\tadi,aux-dac1-default-value-mV = <0x0>;\n\t\t\t\tadi,aux-dac1-rx-delay-us = <0x0>;\n\t\t\t\tadi,aux-dac1-tx-delay-us = <0x0>;\n\t\t\t\tadi,aux-dac2-default-value-mV = <0x0>;\n\t\t\t\tadi,aux-dac2-rx-delay-us = <0x0>;\n\t\t\t\tadi,aux-dac2-tx-delay-us = <0x0>;\n\t\t\t\ten_agc-gpios = <0x6 0x62 0x0>;\n\t\t\t\tsync-gpios = <0x6 0x63 0x0>;\n\t\t\t\treset-gpios = <0x6 0x64 0x0>;\n\t\t\t\tenable-gpios = <0x6 0x65 0x0>;\n\t\t\t\ttxnrx-gpios = <0x6 0x66 0x0>;\n\t\t\t\tlinux,phandle = <0xc>;\n\t\t\t\tphandle = <0xc>;\n\t\t\t};\n\t\t};\n\n\t\tspi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x31 0x4>;\n\t\t\tclocks = <0x2 0x1a 0x2 0x23>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t};\n\n\t\tspi@e000d000 {\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tclocks = <0x2 0xa 0x2 0x2b>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x13 0x4>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\tis-dual = <0x0>;\n\t\t\tnum-cs = <0x1>;\n\n\t\t\tps7-qspi@0 {\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t\tspi-tx-bus-width = <0x1>;\n\t\t\t\tspi-rx-bus-width = <0x4>;\n\t\t\t\tcompatible = \"n25q256a\", \"jedec,spi-nor\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tspi-max-frequency = <0x2faf080>;\n\n\t\t\t\tpartition@qspi-fsbl-uboot {\n\t\t\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\t\t\treg = <0x0 0xe0000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-uboot-env {\n\t\t\t\t\tlabel = \"qspi-uboot-env\";\n\t\t\t\t\treg = <0xe0000 0x20000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-linux {\n\t\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\t\treg = <0x100000 0x500000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-device-tree {\n\t\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\t\treg = <0x600000 0x20000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-rootfs {\n\t\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\t\treg = <0x620000 0xce0000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-bitstream {\n\t\t\t\t\tlabel = \"qspi-bitstream\";\n\t\t\t\t\treg = <0x1300000 0xd00000>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tmemory-controller@e000e000 {\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x1>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"aclk\";\n\t\t\tclocks = <0x2 0xb 0x2 0x2c>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x12 0x4>;\n\t\t\tranges;\n\t\t\treg = <0xe000e000 0x1000>;\n\n\t\t\tflash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\n\t\t\tflash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x2000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\t\t};\n\n\t\tethernet@e000b000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupts = <0x0 0x16 0x4>;\n\t\t\tclocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\tphy-handle = <0x7>;\n\t\t\tphy-mode = \"rgmii-id\";\n\n\t\t\tphy@0 {\n\t\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tmarvell,reg-init = <0x3 0x10 0xff00 0x1e 0x3 0x11 0xfff0 0x0>;\n\t\t\t\tlinux,phandle = <0x7>;\n\t\t\t\tphandle = <0x7>;\n\t\t\t};\n\t\t};\n\n\t\tethernet@e000c000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0x0 0x2d 0x4>;\n\t\t\tclocks = <0x2 0x1f 0x2 0x1f 0x2 0xe>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t};\n\n\t\tmmc@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <0x2 0x15 0x2 0x20>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x18 0x4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t\tdisable-wp;\n\t\t};\n\n\t\tmmc@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <0x2 0x16 0x2 0x21>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x2f 0x4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t};\n\n\t\tslcr@f8000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\", \"simple-mfd\";\n\t\t\treg = <0xf8000000 0x1000>;\n\t\t\tranges;\n\t\t\tlinux,phandle = <0x8>;\n\t\t\tphandle = <0x8>;\n\n\t\t\tclkc@100 {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <0x1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\", \"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\", \"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\", \"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\", \"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\", \"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\", \"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\", \"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\", \"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\", \"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t\tps-clk-frequency = <0x1fca055>;\n\t\t\t\tlinux,phandle = <0x2>;\n\t\t\t\tphandle = <0x2>;\n\t\t\t};\n\n\t\t\trstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <0x1>;\n\t\t\t\tsyscon = <0x8>;\n\t\t\t};\n\n\t\t\tpinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <0x8>;\n\t\t\t};\n\t\t};\n\n\t\tdmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\", \"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\tinterrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>;\n\t\t\t#dma-cells = <0x1>;\n\t\t\t#dma-channels = <0x8>;\n\t\t\t#dma-requests = <0x4>;\n\t\t\tclocks = <0x2 0x1b>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t};\n\n\t\tdevcfg@f8007000 {\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x8 0x4>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tclocks = <0x2 0xc 0x2 0xf 0x2 0x10 0x2 0x11 0x2 0x12>;\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tsyscon = <0x8>;\n\t\t\tlinux,phandle = <0x4>;\n\t\t\tphandle = <0x4>;\n\t\t};\n\n\t\tefuse@f800d000 {\n\t\t\tcompatible = \"xlnx,zynq-efuse\";\n\t\t\treg = <0xf800d000 0x20>;\n\t\t};\n\n\t\ttimer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <0x1 0xb 0x301>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tclocks = <0x2 0x4>;\n\t\t};\n\n\t\ttimer@f8001000 {\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <0x2 0x6>;\n\t\t\treg = <0xf8001000 0x1000>;\n\t\t};\n\n\t\ttimer@f8002000 {\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <0x2 0x6>;\n\t\t\treg = <0xf8002000 0x1000>;\n\t\t};\n\n\t\ttimer@f8f00600 {\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x1 0xd 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <0x2 0x4>;\n\t\t};\n\n\t\tusb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"okay\";\n\t\t\tclocks = <0x2 0x1c>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x15 0x4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t\tdr_mode = \"host\";\n\t\t\txlnx,phy-reset-gpio = <0x6 0x7 0x0>;\n\t\t};\n\n\t\tusb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x1d>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x2c 0x4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog@f8005000 {\n\t\t\tclocks = <0x2 0x2d>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x9 0x1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <0xa>;\n\t\t};\n\t};\n\n\taliases {\n\t\tethernet0 = \"/amba/ethernet@e000b000\";\n\t\tserial0 = \"/amba/serial@e0001000\";\n\t};\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x40000000>;\n\t};\n\n\tchosen {\n\t\tlinux,stdout-path = \"/amba@0/uart@E0001000\";\n\t};\n\n\tclocks {\n\n\t\tclock@0 {\n\t\t\t#clock-cells = <0x0>;\n\t\t\tcompatible = \"adjustable-clock\";\n\t\t\tclock-frequency = <0x2625a00>;\n\t\t\tclock-accuracy = <0x30d40>;\n\t\t\tclock-output-names = \"XO_40MHz\";\n\t\t\tlinux,phandle = <0x9>;\n\t\t\tphandle = <0x9>;\n\t\t};\n\n\t\tclock@2 {\n\t\t\t#clock-cells = <0x0>;\n\t\t\tcompatible = \"fixed-clock\";\n\t\t\tclock-frequency = <0x16e3600>;\n\t\t\tclock-output-names = \"24MHz\";\n\t\t\tlinux,phandle = <0xa>;\n\t\t\tphandle = <0xa>;\n\t\t};\n\t};\n\n\tad9361-refclk-gpio-gate@0 {\n\t\t#clock-cells = <0x0>;\n\t\tcompatible = \"gpio-gate-clock\";\n\t\tclocks = <0x9>;\n\t\tenable-gpios = <0x6 0x69 0x0>;\n\t\tclk-set-rate-parent-enable;\n\t\tclock-output-names = \"ad9361_ext_refclk\";\n\t\tlinux,phandle = <0x5>;\n\t\tphandle = <0x5>;\n\t};\n\n\tusb-ulpe-gpio-gate@0 {\n\t\t#clock-cells = <0x0>;\n\t\tcompatible = \"gpio-gate-clock\";\n\t\tclocks = <0xa>;\n\t\tenable-gpios = <0x6 0x9 0x1>;\n\t};\n\n\tfpga-axi@0 {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tranges;\n\n\t\ti2c@41600000 {\n\t\t\tcompatible = \"xlnx,axi-iic-1.02.a\", \"xlnx,xps-iic-2.00.a\";\n\t\t\treg = <0x41600000 0x10000>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x3a 0x4>;\n\t\t\tclocks = <0x2 0xf>;\n\t\t\tclock-names = \"pclk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\n\t\t\tadm1166@68 {\n\t\t\t\tcompatible = \"adi,adm1166\";\n\t\t\t\treg = <0x68>;\n\t\t\t};\n\n\t\t\tad7291-bob@2f {\n\t\t\t\tcompatible = \"adi,ad7291\";\n\t\t\t\treg = <0x2f>;\n\t\t\t};\n\n\t\t\teeprom@50 {\n\t\t\t\tcompatible = \"at24,24c32\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\n\t\t// dma@7c400000 {\n\t\t// \tcompatible = \"adi,axi-dmac-1.00.a\";\n\t\t// \treg = <0x7c400000 0x10000>;\n\t\t// \t#dma-cells = <0x1>;\n\t\t// \tinterrupts = <0x0 0x39 0x0>;\n\t\t// \tclocks = <0x2 0x10>;\n\t\t// \tlinux,phandle = <0xb>;\n\t\t// \tphandle = <0xb>;\n\n\t\t// \tadi,channels {\n\t\t// \t\t#size-cells = <0x0>;\n\t\t// \t\t#address-cells = <0x1>;\n\n\t\t// \t\tdma-channel@0 {\n\t\t// \t\t\treg = <0x0>;\n\t\t// \t\t\tadi,source-bus-width = <0x40>;\n\t\t// \t\t\tadi,source-bus-type = <0x2>;\n\t\t// \t\t\tadi,destination-bus-width = <0x40>;\n\t\t// \t\t\tadi,destination-bus-type = <0x0>;\n\t\t// \t\t};\n\t\t// \t};\n\t\t// };\n\n\t\t// dma@7c420000 {\n\t\t// \tcompatible = \"adi,axi-dmac-1.00.a\";\n\t\t// \treg = <0x7c420000 0x10000>;\n\t\t// \t#dma-cells = <0x1>;\n\t\t// \tinterrupts = <0x0 0x38 0x0>;\n\t\t// \tclocks = <0x2 0x10>;\n\t\t// \tlinux,phandle = <0xd>;\n\t\t// \tphandle = <0xd>;\n\n\t\t// \tadi,channels {\n\t\t// \t\t#size-cells = <0x0>;\n\t\t// \t\t#address-cells = <0x1>;\n\n\t\t// \t\tdma-channel@0 {\n\t\t// \t\t\treg = <0x0>;\n\t\t// \t\t\tadi,source-bus-width = <0x40>;\n\t\t// \t\t\tadi,source-bus-type = <0x0>;\n\t\t// \t\t\tadi,destination-bus-width = <0x40>;\n\t\t// \t\t\tadi,destination-bus-type = <0x2>;\n\t\t// \t\t};\n\t\t// \t};\n\t\t// };\n\n\t\tsdr: sdr {\n\t\t\tcompatible =\"sdr,sdr\";\n\t\t\tdmas = <&rx_dma 1\n\t\t\t\t\t&tx_dma 0>;\n\t\t\tdma-names = \"rx_dma_s2mm\", \"tx_dma_mm2s\";\n\t\t\tinterrupt-names = \"not_valid_anymore\", \"rx_pkt_intr\", \"tx_itrpt\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 29 1 0 30 1 0 33 1 0 34 1>;\n\t\t} ;\n\n\t\taxidmatest_1: axidmatest@1 {\n\t\t\tcompatible =\"xlnx,axi-dma-test-1.00.a\";\n\t\t\tdmas = <&rx_dma 0\n\t\t\t\t&rx_dma 1>;\n\t\t\tdma-names = \"axidma0\", \"axidma1\";\n\t\t} ;\n\n\t\ttx_dma: dma@80400000 {\n\t\t\t#dma-cells = <1>;\n\t\t\tclock-names = \"s_axi_lite_aclk\", \"m_axi_sg_aclk\", \"m_axi_mm2s_aclk\", \"m_axi_s2mm_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"xlnx,axi-dma-1.00.a\";\n\t\t\tinterrupt-names = \"mm2s_introut\", \"s2mm_introut\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 35 4 0 36 4>;\n\t\t\treg = <0x80400000 0x10000>;\n\t\t\txlnx,addrwidth = <0x20>;\n\t\t\txlnx,include-sg ;\n\t\t\txlnx,sg-length-width = <0xe>;\n\t\t\tdma-channel@80400000 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-mm2s-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 35 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x0>;\n\t\t\t};\n\t\t\tdma-channel@80400030 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-s2mm-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 36 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x0>;\n\t\t\t};\n\t\t};\n\t\t\n\t\trx_dma: dma@80410000 {\n\t\t\t#dma-cells = <1>;\n\t\t\tclock-names = \"s_axi_lite_aclk\", \"m_axi_sg_aclk\", \"m_axi_mm2s_aclk\", \"m_axi_s2mm_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"xlnx,axi-dma-1.00.a\";\n\t\t\t//dma-coherent ;\n\t\t\tinterrupt-names = \"mm2s_introut\", \"s2mm_introut\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 31 4 0 32 4>;\n\t\t\treg = <0x80410000 0x10000>;\n\t\t\txlnx,addrwidth = <0x20>;\n\t\t\txlnx,include-sg ;\n\t\t\txlnx,sg-length-width = <0xe>;\n\t\t\tdma-channel@80410000 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-mm2s-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 31 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x1>;\n\t\t\t};\n\t\t\tdma-channel@80410030 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-s2mm-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 32 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x1>;\n\t\t\t};\n\t\t};\n\n\t\ttx_intf_0: tx_intf@83c00000 {\n\t\t\tclock-names = \"s00_axi_aclk\", \"s00_axis_aclk\";//, \"s01_axis_aclk\", \"m00_axis_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"sdr,tx_intf\";\n\t\t\tinterrupt-names = \"tx_itrpt\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 34 1>;\n\t\t\treg = <0x83c00000 0x10000>;\n\t\t\txlnx,s00-axi-addr-width = <0x7>;\n\t\t\txlnx,s00-axi-data-width = <0x20>;\n\t\t};\n\n\t\trx_intf_0: rx_intf@83c20000 {\n\t\t\tclock-names = \"s00_axi_aclk\", \"m00_axis_aclk\";//, \"s00_axis_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>;\n\t\t\tcompatible = \"sdr,rx_intf\";\n\t\t\tinterrupt-names = \"not_valid_anymore\", \"rx_pkt_intr\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 29 1 0 30 1>;\n\t\t\treg = <0x83c20000 0x10000>;\n\t\t\txlnx,s00-axi-addr-width = <0x7>;\n\t\t\txlnx,s00-axi-data-width = <0x20>;\n\t\t};\n\n\t\topenofdm_tx_0: openofdm_tx@83c10000 {\n\t\t\tclock-names = \"clk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,openofdm_tx\";\n\t\t\treg = <0x83c10000 0x10000>;\n\t\t};\n\n\t\topenofdm_rx_0: openofdm_rx@83c30000 {\n\t\t\tclock-names = \"clk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,openofdm_rx\";\n\t\t\treg = <0x83c30000 0x10000>;\n\t\t};\n\n\t\txpu_0: xpu@83c40000 {\n\t\t\tclock-names = \"s00_axi_aclk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,xpu\";\n\t\t\treg = <0x83c40000 0x10000>;\n\t\t};\n\n\t\tside_ch_0: side_ch@83c50000 {\n\t\t\tclock-names = \"s00_axi_aclk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,side_ch\";\n\t\t\treg = <0x83c50000 0x10000>;\n\t\t\tdmas = <&rx_dma 0\n\t\t\t\t\t&tx_dma 1>;\n\t\t\tdma-names = \"rx_dma_mm2s\", \"tx_dma_s2mm\";\n\t\t};\n\n\t\tcf-ad9361-lpc@79020000 {\n\t\t\tcompatible = \"adi,axi-ad9361-6.00.a\";\n\t\t\treg = <0x79020000 0x6000>;\n\t\t\t// dmas = <0xb 0x0>;\n\t\t\t// dma-names = \"rx\";\n\t\t\tspibus-connected = <0xc>;\n\t\t};\n\n\t\tcf-ad9361-dds-core-lpc@79024000 {\n\t\t\tcompatible = \"adi,axi-ad9361-dds-6.00.a\";\n\t\t\treg = <0x79024000 0x1000>;\n\t\t\tclocks = <0xc 0xd>;\n\t\t\tclock-names = \"sampl_clk\";\n\t\t\t// dmas = <0xd 0x0>;\n\t\t\t// dma-names = \"tx\";\n\t\t};\n\n\t\tmwipcore@43c00000 {\n\t\t\tcompatible = \"mathworks,mwipcore-axi4lite-v1.00\";\n\t\t\treg = <0x43c00000 0xffff>;\n\t\t};\n\n\t\t/*axi-sysid-0@45000000 {\n\t\t\tcompatible = \"adi,axi-sysid-1.00.a\";\n\t\t\treg = <0x45000000 0x10000>;\n\t\t};*/\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled0 {\n\t\t\tlabel = \"led0:green\";\n\t\t\tgpios = <0x6 0x3a 0x0>;\n\t\t};\n\n\t\tled1 {\n\t\t\tlabel = \"led1:green\";\n\t\t\tgpios = <0x6 0x3b 0x0>;\n\t\t};\n\n\t\tled2 {\n\t\t\tlabel = \"led2:green\";\n\t\t\tgpios = <0x6 0x3c 0x0>;\n\t\t};\n\n\t\tled3 {\n\t\t\tlabel = \"led3:green\";\n\t\t\tgpios = <0x6 0x3d 0x0>;\n\t\t};\n\t};\n\n\tgpio_keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x0>;\n\t\tautorepeat;\n\n\t\tpb0 {\n\t\t\tlabel = \"Left\";\n\t\t\tlinux,code = <0x69>;\n\t\t\tgpios = <0x6 0x36 0x0>;\n\t\t};\n\n\t\tpb1 {\n\t\t\tlabel = \"Right\";\n\t\t\tlinux,code = <0x6a>;\n\t\t\tgpios = <0x6 0x37 0x0>;\n\t\t};\n\n\t\tpb2 {\n\t\t\tlabel = \"Up\";\n\t\t\tlinux,code = <0x67>;\n\t\t\tgpios = <0x6 0x38 0x0>;\n\t\t};\n\n\t\tpb3 {\n\t\t\tlabel = \"Down\";\n\t\t\tlinux,code = <0x6c>;\n\t\t\tgpios = <0x6 0x39 0x0>;\n\t\t};\n\n\t\tsw0 {\n\t\t\tlabel = \"SW0\";\n\t\t\tlinux,input-type = <0x5>;\n\t\t\tlinux,code = <0x0>;\n\t\t\tgpios = <0x6 0x3e 0x0>;\n\t\t};\n\n\t\tsw1 {\n\t\t\tlabel = \"SW1\";\n\t\t\tlinux,input-type = <0x5>;\n\t\t\tlinux,code = <0x1>;\n\t\t\tgpios = <0x6 0x3f 0x0>;\n\t\t};\n\n\t\tsw2 {\n\t\t\tlabel = \"SW2\";\n\t\t\tlinux,input-type = <0x5>;\n\t\t\tlinux,code = <0x2>;\n\t\t\tgpios = <0x6 0x40 0x0>;\n\t\t};\n\n\t\tsw3 {\n\t\t\tlabel = \"SW3\";\n\t\t\tlinux,input-type = <0x5>;\n\t\t\tlinux,code = <0x3>;\n\t\t\tgpios = <0x6 0x41 0x0>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "kernel_boot/boards/adrv9361z7035_fmc/devicetree.dts",
    "content": "/dts-v1/;\n\n/ {\n\t#address-cells = <0x1>;\n\t#size-cells = <0x1>;\n\tcompatible = \"xlnx,zynq-7000\";\n\tinterrupt-parent = <0x1>;\n\tmodel = \"Analog Devices ADRV9361-Z7035 (Z7035/AD9361)\";\n\n\tcpus {\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0x0>;\n\t\t\tclocks = <0x2 0x3>;\n\t\t\tclock-latency = <0x3e8>;\n\t\t\tcpu0-supply = <0x3>;\n\t\t\toperating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0x1>;\n\t\t\tclocks = <0x2 0x3>;\n\t\t};\n\t};\n\n\tfpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <0x4>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tranges;\n\t};\n\n\tpmu@f8891000 {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0x0 0x5 0x4 0x0 0x6 0x4>;\n\t\tinterrupt-parent = <0x1>;\n\t\treg = <0xf8891000 0x1000 0xf8893000 0x1000>;\n\t};\n\n\tfixedregulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <0xf4240>;\n\t\tregulator-max-microvolt = <0xf4240>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t\tlinux,phandle = <0x3>;\n\t\tphandle = <0x3>;\n\t};\n\n\tamba {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tinterrupt-parent = <0x1>;\n\t\tranges;\n\n\t\tadc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0x0 0x7 0x4>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tclocks = <0x2 0xc>;\n\t\t};\n\n\t\tcan@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x13 0x2 0x24>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0x0 0x1c 0x4>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x14 0x2 0x25>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0x0 0x33 0x4>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tclocks = <0x2 0x2a>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <0x2>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x14 0x4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t\tlinux,phandle = <0x6>;\n\t\t\tphandle = <0x6>;\n\t\t};\n\n\t\ti2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x26>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x19 0x4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t};\n\n\t\ti2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x27>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x30 0x4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t};\n\n\t\tinterrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <0x3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xf8f01000 0x1000 0xf8f00100 0x100>;\n\t\t\tlinux,phandle = <0x1>;\n\t\t\tphandle = <0x1>;\n\t\t};\n\n\t\tcache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xf8f02000 0x1000>;\n\t\t\tinterrupts = <0x0 0x2 0x4>;\n\t\t\tarm,data-latency = <0x3 0x2 0x2>;\n\t\t\tarm,tag-latency = <0x2 0x2 0x2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <0x2>;\n\t\t};\n\n\t\tmemory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x3 0x4>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t};\n\n\t\tserial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x17 0x2 0x28>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xe0000000 0x1000>;\n\t\t\tinterrupts = <0x0 0x1b 0x4>;\n\t\t};\n\n\t\tserial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"okay\";\n\t\t\tclocks = <0x2 0x18 0x2 0x29>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xe0001000 0x1000>;\n\t\t\tinterrupts = <0x0 0x32 0x4>;\n\t\t};\n\n\t\tspi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x1a 0x4>;\n\t\t\tclocks = <0x2 0x19 0x2 0x22>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\n\t\t\tad9361-phy@0 {\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x0>;\n\t\t\t\t#clock-cells = <0x1>;\n\t\t\t\tcompatible = \"adi,ad9361\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tspi-cpha;\n\t\t\t\tspi-max-frequency = <0x989680>;\n\t\t\t\tclocks = <0x5 0x0>;\n\t\t\t\tclock-names = \"ad9361_ext_refclk\";\n\t\t\t\tclock-output-names = \"rx_sampl_clk\", \"tx_sampl_clk\";\n\t\t\t\tadi,digital-interface-tune-skip-mode = <0x0>;\n\t\t\t\tadi,pp-tx-swap-enable;\n\t\t\t\tadi,pp-rx-swap-enable;\n\t\t\t\tadi,rx-frame-pulse-mode-enable;\n\t\t\t\tadi,lvds-mode-enable;\n\t\t\t\tadi,lvds-bias-mV = <0x96>;\n\t\t\t\tadi,lvds-rx-onchip-termination-enable;\n\t\t\t\tadi,rx-data-delay = <0x4>;\n\t\t\t\tadi,tx-fb-clock-delay = <0x7>;\n\t\t\t\tadi,xo-disable-use-ext-refclk-enable;\n\t\t\t\tadi,2rx-2tx-mode-enable;\n\t\t\t\tadi,frequency-division-duplex-mode-enable;\n\t\t\t\tadi,rx-rf-port-input-select = <0x0>;\n\t\t\t\tadi,tx-rf-port-input-select = <0x0>;\n\t\t\t\tadi,tx-attenuation-mdB = <0x2710>;\n\t\t\t\tadi,tx-lo-powerdown-managed-enable;\n\t\t\t\tadi,rf-rx-bandwidth-hz = <0x112a880>;\n\t\t\t\tadi,rf-tx-bandwidth-hz = <0x112a880>;\n\t\t\t\tadi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;\n\t\t\t\tadi,tx-synthesizer-frequency-hz = <0x0 0x92080880>;\n\t\t\t\tadi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;\n\t\t\t\tadi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;\n\t\t\t\tadi,gc-rx1-mode = <0x2>;\n\t\t\t\tadi,gc-rx2-mode = <0x2>;\n\t\t\t\tadi,gc-adc-ovr-sample-size = <0x4>;\n\t\t\t\tadi,gc-adc-small-overload-thresh = <0x2f>;\n\t\t\t\tadi,gc-adc-large-overload-thresh = <0x3a>;\n\t\t\t\tadi,gc-lmt-overload-high-thresh = <0x320>;\n\t\t\t\tadi,gc-lmt-overload-low-thresh = <0x2c0>;\n\t\t\t\tadi,gc-dec-pow-measurement-duration = <0x2000>;\n\t\t\t\tadi,gc-low-power-thresh = <0x18>;\n\t\t\t\tadi,mgc-inc-gain-step = <0x2>;\n\t\t\t\tadi,mgc-dec-gain-step = <0x2>;\n\t\t\t\tadi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;\n\t\t\t\tadi,agc-attack-delay-extra-margin-us = <0x1>;\n\t\t\t\tadi,agc-outer-thresh-high = <0x5>;\n\t\t\t\tadi,agc-outer-thresh-high-dec-steps = <0x2>;\n\t\t\t\tadi,agc-inner-thresh-high = <0xa>;\n\t\t\t\tadi,agc-inner-thresh-high-dec-steps = <0x1>;\n\t\t\t\tadi,agc-inner-thresh-low = <0xc>;\n\t\t\t\tadi,agc-inner-thresh-low-inc-steps = <0x1>;\n\t\t\t\tadi,agc-outer-thresh-low = <0x12>;\n\t\t\t\tadi,agc-outer-thresh-low-inc-steps = <0x2>;\n\t\t\t\tadi,agc-adc-small-overload-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-adc-large-overload-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-adc-large-overload-inc-steps = <0x7>;\n\t\t\t\tadi,agc-lmt-overload-large-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-lmt-overload-small-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-lmt-overload-large-inc-steps = <0x7>;\n\t\t\t\tadi,agc-gain-update-interval-us = <0x3e8>;\n\t\t\t\tadi,fagc-dec-pow-measurement-duration = <0x10>;\n        adi,fagc-adc-large-overload-inc-steps = <0x07>;\n\t\t\t\tadi,fagc-lp-thresh-increment-steps = <0x1>;\n\t\t\t\tadi,fagc-lp-thresh-increment-time = <0x5>;\n\t\t\t\tadi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;\n        adi,fagc-dig-sat-ovrg-enable;\n\t\t\t\tadi,fagc-final-overrange-count = <0x3>;\n\t\t\t\tadi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;\n\t\t\t\tadi,fagc-lmt-final-settling-steps = <0x1>;\n\t\t\t\tadi,fagc-lock-level = <0xa>;\n\t\t\t\tadi,fagc-lock-level-gain-increase-upper-limit = <0x5>;\n\t\t\t\tadi,fagc-lock-level-lmt-gain-increase-enable;\n\t\t\t\tadi,fagc-lpf-final-settling-steps = <0x1>;\n\t\t\t\tadi,fagc-optimized-gain-offset = <0x5>;\n\t\t\t\tadi,fagc-power-measurement-duration-in-state5 = <0x10>;\n\t\t\t\tadi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;\n\t\t\t\tadi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;\n\t\t\t\tadi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;\n\t\t\t\tadi,fagc-rst-gla-large-adc-overload-enable;\n\t\t\t\tadi,fagc-rst-gla-large-lmt-overload-enable;\n\t\t\t\tadi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;\n\t\t\t\tadi,fagc-state-wait-time-ns = <0x104>;\n\t\t\t\tadi,fagc-use-last-lock-level-for-set-gain-enable;\n\t\t\t\tadi,rssi-restart-mode = <0x3>;\n\t\t\t\tadi,rssi-delay = <0x1>;\n\t\t\t\tadi,rssi-wait = <0x1>;\n\t\t\t\tadi,rssi-duration = <0x3e8>;\n\t\t\t\tadi,ctrl-outs-index = <0x0>;\n\t\t\t\tadi,ctrl-outs-enable-mask = <0xff>;\n\t\t\t\tadi,temp-sense-measurement-interval-ms = <0x3e8>;\n\t\t\t\tadi,temp-sense-offset-signed = <0xce>;\n\t\t\t\tadi,temp-sense-periodic-measurement-enable;\n\t\t\t\tadi,aux-dac-manual-mode-enable;\n\t\t\t\tadi,aux-dac1-default-value-mV = <0x0>;\n\t\t\t\tadi,aux-dac1-rx-delay-us = <0x0>;\n\t\t\t\tadi,aux-dac1-tx-delay-us = <0x0>;\n\t\t\t\tadi,aux-dac2-default-value-mV = <0x0>;\n\t\t\t\tadi,aux-dac2-rx-delay-us = <0x0>;\n\t\t\t\tadi,aux-dac2-tx-delay-us = <0x0>;\n\t\t\t\ten_agc-gpios = <0x6 0x62 0x0>;\n\t\t\t\tsync-gpios = <0x6 0x63 0x0>;\n\t\t\t\treset-gpios = <0x6 0x64 0x0>;\n\t\t\t\tenable-gpios = <0x6 0x65 0x0>;\n\t\t\t\ttxnrx-gpios = <0x6 0x66 0x0>;\n\t\t\t\tlinux,phandle = <0x10>;\n\t\t\t\tphandle = <0x10>;\n\t\t\t};\n\n\t\t\tad9517@1 {\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x0>;\n\t\t\t\t#clock-cells = <0x1>;\n\t\t\t\tcompatible = \"adi,ad9517-3\";\n\t\t\t\treg = <0x1>;\n\t\t\t\tspi-max-frequency = <0x989680>;\n\t\t\t\tclocks = <0x7 0x7>;\n\t\t\t\tclock-names = \"refclk\", \"clkin\";\n\t\t\t\tclock-output-names = \"out0\", \"out1\", \"out2\", \"out3\", \"out4\", \"out5\", \"out6\", \"out7\";\n\t\t\t\tfirmware = \"pzsdr-fmc-ad9517.stp\";\n\t\t\t};\n\t\t};\n\n\t\tspi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x31 0x4>;\n\t\t\tclocks = <0x2 0x1a 0x2 0x23>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t};\n\n\t\tspi@e000d000 {\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tclocks = <0x2 0xa 0x2 0x2b>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x13 0x4>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\tis-dual = <0x0>;\n\t\t\tnum-cs = <0x1>;\n\n\t\t\tps7-qspi@0 {\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t\tspi-tx-bus-width = <0x1>;\n\t\t\t\tspi-rx-bus-width = <0x4>;\n\t\t\t\tcompatible = \"n25q256a\", \"jedec,spi-nor\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tspi-max-frequency = <0x2faf080>;\n\n\t\t\t\tpartition@qspi-fsbl-uboot {\n\t\t\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\t\t\treg = <0x0 0xe0000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-uboot-env {\n\t\t\t\t\tlabel = \"qspi-uboot-env\";\n\t\t\t\t\treg = <0xe0000 0x20000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-linux {\n\t\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\t\treg = <0x100000 0x500000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-device-tree {\n\t\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\t\treg = <0x600000 0x20000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-rootfs {\n\t\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\t\treg = <0x620000 0xce0000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-bitstream {\n\t\t\t\t\tlabel = \"qspi-bitstream\";\n\t\t\t\t\treg = <0x1300000 0xd00000>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tmemory-controller@e000e000 {\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x1>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"aclk\";\n\t\t\tclocks = <0x2 0xb 0x2 0x2c>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x12 0x4>;\n\t\t\tranges;\n\t\t\treg = <0xe000e000 0x1000>;\n\n\t\t\tflash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\n\t\t\tflash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x2000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\t\t};\n\n\t\tethernet@e000b000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupts = <0x0 0x16 0x4>;\n\t\t\tclocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\tphy-handle = <0x8>;\n\t\t\tphy-mode = \"rgmii-id\";\n\n\t\t\tphy@0 {\n\t\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tmarvell,reg-init = <0x3 0x10 0xff00 0x1e 0x3 0x11 0xfff0 0x0>;\n\t\t\t\tlinux,phandle = <0x8>;\n\t\t\t\tphandle = <0x8>;\n\t\t\t};\n\t\t};\n\n\t\tethernet@e000c000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupts = <0x0 0x2d 0x4>;\n\t\t\tclocks = <0x2 0x1f 0x2 0x1f 0x2 0xe>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\tphy-handle = <0x9>;\n\t\t\tphy-mode = \"gmii\";\n\n\t\t\tphy@1 {\n\t\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\t\treg = <0x1>;\n\t\t\t\tmarvell,reg-init = <0x3 0x10 0xff00 0x1e 0x3 0x11 0xfff0 0x0>;\n\t\t\t\tlinux,phandle = <0x9>;\n\t\t\t\tphandle = <0x9>;\n\t\t\t};\n\n\t\t\tgmiitorgmii@8 {\n\t\t\t\tcompatible = \"xlnx,gmii-to-rgmii-1.0\";\n\t\t\t\treg = <0x8>;\n\t\t\t\tphy-handle = <0x9>;\n\t\t\t};\n\t\t};\n\n\t\tmmc@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <0x2 0x15 0x2 0x20>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x18 0x4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t\tdisable-wp;\n\t\t};\n\n\t\tmmc@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <0x2 0x16 0x2 0x21>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x2f 0x4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t};\n\n\t\tslcr@f8000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\", \"simple-mfd\";\n\t\t\treg = <0xf8000000 0x1000>;\n\t\t\tranges;\n\t\t\tlinux,phandle = <0xa>;\n\t\t\tphandle = <0xa>;\n\n\t\t\tclkc@100 {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <0x1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\", \"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\", \"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\", \"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\", \"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\", \"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\", \"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\", \"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\", \"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\", \"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t\tps-clk-frequency = <0x1fca055>;\n\t\t\t\tlinux,phandle = <0x2>;\n\t\t\t\tphandle = <0x2>;\n\t\t\t};\n\n\t\t\trstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <0x1>;\n\t\t\t\tsyscon = <0xa>;\n\t\t\t};\n\n\t\t\tpinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <0xa>;\n\t\t\t};\n\t\t};\n\n\t\tdmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\", \"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\tinterrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>;\n\t\t\t#dma-cells = <0x1>;\n\t\t\t#dma-channels = <0x8>;\n\t\t\t#dma-requests = <0x4>;\n\t\t\tclocks = <0x2 0x1b>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t\tlinux,phandle = <0x15>;\n\t\t\tphandle = <0x15>;\n\t\t};\n\n\t\tdevcfg@f8007000 {\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x8 0x4>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tclocks = <0x2 0xc 0x2 0xf 0x2 0x10 0x2 0x11 0x2 0x12>;\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tsyscon = <0xa>;\n\t\t\tlinux,phandle = <0x4>;\n\t\t\tphandle = <0x4>;\n\t\t};\n\n\t\tefuse@f800d000 {\n\t\t\tcompatible = \"xlnx,zynq-efuse\";\n\t\t\treg = <0xf800d000 0x20>;\n\t\t};\n\n\t\ttimer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <0x1 0xb 0x301>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tclocks = <0x2 0x4>;\n\t\t};\n\n\t\ttimer@f8001000 {\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <0x2 0x6>;\n\t\t\treg = <0xf8001000 0x1000>;\n\t\t};\n\n\t\ttimer@f8002000 {\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <0x2 0x6>;\n\t\t\treg = <0xf8002000 0x1000>;\n\t\t};\n\n\t\ttimer@f8f00600 {\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x1 0xd 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <0x2 0x4>;\n\t\t};\n\n\t\tusb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"okay\";\n\t\t\tclocks = <0x2 0x1c>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x15 0x4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t\tdr_mode = \"host\";\n\t\t\txlnx,phy-reset-gpio = <0x6 0x7 0x0>;\n\t\t};\n\n\t\tusb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x1d>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x2c 0x4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog@f8005000 {\n\t\t\tclocks = <0x2 0x2d>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x9 0x1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <0xa>;\n\t\t};\n\t};\n\n\taliases {\n\t\tethernet0 = \"/amba/ethernet@e000b000\";\n\t\tserial0 = \"/amba/serial@e0001000\";\n\t\tethernet1 = \"/amba/ethernet@e000c000\";\n\t};\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x40000000>;\n\t};\n\n\tchosen {\n\t\tlinux,stdout-path = \"/amba@0/uart@E0001000\";\n\t};\n\n\tclocks {\n\n\t\tclock@0 {\n\t\t\t#clock-cells = <0x0>;\n\t\t\tcompatible = \"adjustable-clock\";\n\t\t\tclock-frequency = <0x2625a00>;\n\t\t\tclock-accuracy = <0x30d40>;\n\t\t\tclock-output-names = \"XO_40MHz\";\n\t\t\tlinux,phandle = <0xb>;\n\t\t\tphandle = <0xb>;\n\t\t};\n\n\t\tclock@2 {\n\t\t\t#clock-cells = <0x0>;\n\t\t\tcompatible = \"fixed-clock\";\n\t\t\tclock-frequency = <0x16e3600>;\n\t\t\tclock-output-names = \"24MHz\";\n\t\t\tlinux,phandle = <0xc>;\n\t\t\tphandle = <0xc>;\n\t\t};\n\n\t\tclock@3 {\n\t\t\t#clock-cells = <0x0>;\n\t\t\tcompatible = \"fixed-clock\";\n\t\t\tclock-frequency = <0x17d7840>;\n\t\t\tclock-output-names = \"ad9517_refclk\";\n\t\t\tlinux,phandle = <0x7>;\n\t\t\tphandle = <0x7>;\n\t\t};\n\n\t\taudio_clock {\n\t\t\tcompatible = \"fixed-clock\";\n\t\t\t#clock-cells = <0x0>;\n\t\t\tclock-frequency = <0xbb8000>;\n\t\t\tlinux,phandle = <0xe>;\n\t\t\tphandle = <0xe>;\n\t\t};\n\t};\n\n\tad9361-refclk-gpio-gate@0 {\n\t\t#clock-cells = <0x0>;\n\t\tcompatible = \"gpio-gate-clock\";\n\t\tclocks = <0xb>;\n\t\tenable-gpios = <0x6 0x69 0x0>;\n\t\tclk-set-rate-parent-enable;\n\t\tclock-output-names = \"ad9361_ext_refclk\";\n\t\tlinux,phandle = <0x5>;\n\t\tphandle = <0x5>;\n\t};\n\n\tusb-ulpe-gpio-gate@0 {\n\t\t#clock-cells = <0x0>;\n\t\tcompatible = \"gpio-gate-clock\";\n\t\tclocks = <0xc>;\n\t\tenable-gpios = <0x6 0x9 0x1>;\n\t};\n\n\tfpga-axi@0 {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tranges;\n\n\t\ti2c@41600000 {\n\t\t\tcompatible = \"xlnx,axi-iic-1.02.a\", \"xlnx,xps-iic-2.00.a\";\n\t\t\treg = <0x41600000 0x10000>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x3a 0x4>;\n\t\t\tclocks = <0x2 0xf>;\n\t\t\tclock-names = \"pclk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\n\t\t\tadm1166@68 {\n\t\t\t\tcompatible = \"adi,adm1166\";\n\t\t\t\treg = <0x68>;\n\t\t\t};\n\n\t\t\ti2cswitch@74 {\n\t\t\t\tcompatible = \"nxp,pca9548\";\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x0>;\n\t\t\t\treg = <0x70>;\n\n\t\t\t\ti2c@0 {\n\t\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t\t#size-cells = <0x0>;\n\t\t\t\t\treg = <0x0>;\n\t\t\t\t};\n\n\t\t\t\ti2c@1 {\n\t\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t\t#size-cells = <0x0>;\n\t\t\t\t\treg = <0x1>;\n\t\t\t\t};\n\n\t\t\t\ti2c@2 {\n\t\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t\t#size-cells = <0x0>;\n\t\t\t\t\treg = <0x2>;\n\n\t\t\t\t\tadv7511@39 {\n\t\t\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\t\t\treg = <0x39 0x3f>;\n\t\t\t\t\t\treg-names = \"primary\", \"edid\";\n\t\t\t\t\t\tadi,input-depth = <0x8>;\n\t\t\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\t\t\tadi,input-style = <0x1>;\n\t\t\t\t\t\tadi,input-justification = \"left\";\n\t\t\t\t\t\tadi,clock-delay = <0x0>;\n\t\t\t\t\t\t#sound-dai-cells = <0x0>;\n\t\t\t\t\t\tlinux,phandle = <0x17>;\n\t\t\t\t\t\tphandle = <0x17>;\n\n\t\t\t\t\t\tports {\n\t\t\t\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t\t\t\t#size-cells = <0x0>;\n\n\t\t\t\t\t\t\tport@0 {\n\t\t\t\t\t\t\t\treg = <0x0>;\n\n\t\t\t\t\t\t\t\tendpoint {\n\t\t\t\t\t\t\t\t\tremote-endpoint = <0xd>;\n\t\t\t\t\t\t\t\t\tlinux,phandle = <0x14>;\n\t\t\t\t\t\t\t\t\tphandle = <0x14>;\n\t\t\t\t\t\t\t\t};\n\t\t\t\t\t\t\t};\n\n\t\t\t\t\t\t\tport@1 {\n\t\t\t\t\t\t\t\treg = <0x1>;\n\t\t\t\t\t\t\t};\n\t\t\t\t\t\t};\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\ti2c@3 {\n\t\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t\t#size-cells = <0x0>;\n\t\t\t\t\treg = <0x3>;\n\n\t\t\t\t\tadau1761@3b {\n\t\t\t\t\t\tcompatible = \"adi,adau1761\";\n\t\t\t\t\t\treg = <0x3b>;\n\t\t\t\t\t\tclocks = <0xe>;\n\t\t\t\t\t\tclock-names = \"mclk\";\n\t\t\t\t\t\t#sound-dai-cells = <0x0>;\n\t\t\t\t\t\tlinux,phandle = <0x19>;\n\t\t\t\t\t\tphandle = <0x19>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\ti2c@4 {\n\t\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t\t#size-cells = <0x0>;\n\t\t\t\t\treg = <0x4>;\n\t\t\t\t};\n\n\t\t\t\ti2c@5 {\n\t\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t\t#size-cells = <0x0>;\n\t\t\t\t\treg = <0x5>;\n\n\t\t\t\t\teeprom@50 {\n\t\t\t\t\t\tcompatible = \"at24,24c32\";\n\t\t\t\t\t\treg = <0x50>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\ti2c@6 {\n\t\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t\t#size-cells = <0x0>;\n\t\t\t\t\treg = <0x6>;\n\n\t\t\t\t\tad7291@2f {\n\t\t\t\t\t\tcompatible = \"adi,ad7291\";\n\t\t\t\t\t\treg = <0x2f>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\ti2c@7 {\n\t\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t\t#size-cells = <0x0>;\n\t\t\t\t\treg = <0x7>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tdma@7c400000 {\n\t\t\tcompatible = \"adi,axi-dmac-1.00.a\";\n\t\t\treg = <0x7c400000 0x10000>;\n\t\t\t#dma-cells = <0x1>;\n\t\t\tinterrupts = <0x0 0x39 0x0>;\n\t\t\tclocks = <0x2 0x10>;\n\t\t\tlinux,phandle = <0xf>;\n\t\t\tphandle = <0xf>;\n\n\t\t\tadi,channels {\n\t\t\t\t#size-cells = <0x0>;\n\t\t\t\t#address-cells = <0x1>;\n\n\t\t\t\tdma-channel@0 {\n\t\t\t\t\treg = <0x0>;\n\t\t\t\t\tadi,source-bus-width = <0x40>;\n\t\t\t\t\tadi,source-bus-type = <0x2>;\n\t\t\t\t\tadi,destination-bus-width = <0x40>;\n\t\t\t\t\tadi,destination-bus-type = <0x0>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tdma@7c420000 {\n\t\t\tcompatible = \"adi,axi-dmac-1.00.a\";\n\t\t\treg = <0x7c420000 0x10000>;\n\t\t\t#dma-cells = <0x1>;\n\t\t\tinterrupts = <0x0 0x38 0x0>;\n\t\t\tclocks = <0x2 0x10>;\n\t\t\tlinux,phandle = <0x11>;\n\t\t\tphandle = <0x11>;\n\n\t\t\tadi,channels {\n\t\t\t\t#size-cells = <0x0>;\n\t\t\t\t#address-cells = <0x1>;\n\n\t\t\t\tdma-channel@0 {\n\t\t\t\t\treg = <0x0>;\n\t\t\t\t\tadi,source-bus-width = <0x40>;\n\t\t\t\t\tadi,source-bus-type = <0x0>;\n\t\t\t\t\tadi,destination-bus-width = <0x40>;\n\t\t\t\t\tadi,destination-bus-type = <0x2>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tsdr: sdr {\n\t\t\tcompatible =\"sdr,sdr\";\n\t\t\tdmas = <&rx_dma 0\n\t\t\t\t\t&rx_dma 1\n\t\t\t\t\t&tx_dma 0\n\t\t\t\t\t&tx_dma 1>;\n\t\t\tdma-names = \"rx_dma_mm2s\", \"rx_dma_s2mm\", \"tx_dma_mm2s\", \"tx_dma_s2mm\";\n\t\t\tinterrupt-names = \"not_valid_anymore\", \"rx_pkt_intr\", \"tx_itrpt0\", \"tx_itrpt1\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 29 1 0 30 1 0 33 1 0 34 1>;\n\t\t} ;\n\n\t\taxidmatest_1: axidmatest@1 {\n\t\t\tcompatible =\"xlnx,axi-dma-test-1.00.a\";\n\t\t\tdmas = <&rx_dma 0\n\t\t\t\t&rx_dma 1>;\n\t\t\tdma-names = \"axidma0\", \"axidma1\";\n\t\t} ;\n\n\t\ttx_dma: dma@80400000 {\n\t\t\t#dma-cells = <1>;\n\t\t\tclock-names = \"s_axi_lite_aclk\", \"m_axi_sg_aclk\", \"m_axi_mm2s_aclk\", \"m_axi_s2mm_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"xlnx,axi-dma-1.00.a\";\n\t\t\tinterrupt-names = \"mm2s_introut\", \"s2mm_introut\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 35 4 0 36 4>;\n\t\t\treg = <0x80400000 0x10000>;\n\t\t\txlnx,addrwidth = <0x20>;\n\t\t\txlnx,include-sg ;\n\t\t\txlnx,sg-length-width = <0xe>;\n\t\t\tdma-channel@80400000 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-mm2s-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 35 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x0>;\n\t\t\t};\n\t\t\tdma-channel@80400030 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-s2mm-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 36 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x0>;\n\t\t\t};\n\t\t};\n\t\t\n\t\trx_dma: dma@80410000 {\n\t\t\t#dma-cells = <1>;\n\t\t\tclock-names = \"s_axi_lite_aclk\", \"m_axi_sg_aclk\", \"m_axi_mm2s_aclk\", \"m_axi_s2mm_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"xlnx,axi-dma-1.00.a\";\n\t\t\t//dma-coherent ;\n\t\t\tinterrupt-names = \"mm2s_introut\", \"s2mm_introut\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 31 4 0 32 4>;\n\t\t\treg = <0x80410000 0x10000>;\n\t\t\txlnx,addrwidth = <0x20>;\n\t\t\txlnx,include-sg ;\n\t\t\txlnx,sg-length-width = <0xe>;\n\t\t\tdma-channel@80410000 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-mm2s-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 31 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x1>;\n\t\t\t};\n\t\t\tdma-channel@80410030 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-s2mm-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 32 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x1>;\n\t\t\t};\n\t\t};\n\n\t\ttx_intf_0: tx_intf@83c00000 {\n\t\t\tclock-names = \"s00_axi_aclk\", \"s00_axis_aclk\", \"s01_axis_aclk\", \"m00_axis_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"sdr,tx_intf\";\n\t\t\tinterrupt-names = \"tx_itrpt0\", \"tx_itrpt1\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 33 1 0 34 1>;\n\t\t\treg = <0x83c00000 0x10000>;\n\t\t\txlnx,s00-axi-addr-width = <0x7>;\n\t\t\txlnx,s00-axi-data-width = <0x20>;\n\t\t};\n\n\t\trx_intf_0: rx_intf@83c20000 {\n\t\t\tclock-names = \"s00_axi_aclk\", \"s00_axis_aclk\", \"m00_axis_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"sdr,rx_intf\";\n\t\t\tinterrupt-names = \"not_valid_anymore\", \"rx_pkt_intr\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 29 1 0 30 1>;\n\t\t\treg = <0x83c20000 0x10000>;\n\t\t\txlnx,s00-axi-addr-width = <0x7>;\n\t\t\txlnx,s00-axi-data-width = <0x20>;\n\t\t};\n\n\t\topenofdm_tx_0: openofdm_tx@83c10000 {\n\t\t\tclock-names = \"clk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,openofdm_tx\";\n\t\t\treg = <0x83c10000 0x10000>;\n\t\t};\n\n\t\topenofdm_rx_0: openofdm_rx@83c30000 {\n\t\t\tclock-names = \"clk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,openofdm_rx\";\n\t\t\treg = <0x83c30000 0x10000>;\n\t\t};\n\n\t\txpu_0: xpu@83c40000 {\n\t\t\tclock-names = \"s00_axi_aclk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,xpu\";\n\t\t\treg = <0x83c40000 0x10000>;\n\t\t};\n\n\t\tcf-ad9361-lpc@79020000 {\n\t\t\tcompatible = \"adi,axi-ad9361-6.00.a\";\n\t\t\treg = <0x79020000 0x6000>;\n\t\t\tdmas = <0xf 0x0>;\n\t\t\tdma-names = \"rx\";\n\t\t\tspibus-connected = <0x10>;\n\t\t};\n\n\t\tcf-ad9361-dds-core-lpc@79024000 {\n\t\t\tcompatible = \"adi,axi-ad9361-dds-6.00.a\";\n\t\t\treg = <0x79024000 0x1000>;\n\t\t\tclocks = <0x10 0xd>;\n\t\t\tclock-names = \"sampl_clk\";\n\t\t\tdmas = <0x11 0x0>;\n\t\t\tdma-names = \"tx\";\n\t\t};\n\n\t\tmwipcore@43c00000 {\n\t\t\tcompatible = \"mathworks,mwipcore-axi4lite-v1.00\";\n\t\t\treg = <0x43c00000 0xffff>;\n\t\t};\n\n\t\t/*axi-sysid-0@45000000 {\n\t\t\tcompatible = \"adi,axi-sysid-1.00.a\";\n\t\t\treg = <0x45000000 0x10000>;\n\t\t};*/\n\n\t\tdma@43000000 {\n\t\t\tcompatible = \"adi,axi-dmac-1.00.a\";\n\t\t\treg = <0x43000000 0x10000>;\n\t\t\t#dma-cells = <0x1>;\n\t\t\tinterrupts = <0x0 0x3b 0x0>;\n\t\t\tclocks = <0x2 0x10>;\n\t\t\tlinux,phandle = <0x12>;\n\t\t\tphandle = <0x12>;\n\n\t\t\tadi,channels {\n\t\t\t\t#size-cells = <0x0>;\n\t\t\t\t#address-cells = <0x1>;\n\n\t\t\t\tdma-channel@0 {\n\t\t\t\t\treg = <0x0>;\n\t\t\t\t\tadi,source-bus-width = <0x40>;\n\t\t\t\t\tadi,source-bus-type = <0x0>;\n\t\t\t\t\tadi,destination-bus-width = <0x40>;\n\t\t\t\t\tadi,destination-bus-type = <0x1>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\taxi-clkgen@79000000 {\n\t\t\tcompatible = \"adi,axi-clkgen-2.00.a\";\n\t\t\treg = <0x79000000 0x10000>;\n\t\t\t#clock-cells = <0x0>;\n\t\t\tclocks = <0x2 0x10>;\n\t\t\tlinux,phandle = <0x13>;\n\t\t\tphandle = <0x13>;\n\t\t};\n\n\t\taxi_hdmi@70e00000 {\n\t\t\tcompatible = \"adi,axi-hdmi-tx-1.00.a\";\n\t\t\treg = <0x70e00000 0x10000>;\n\t\t\tdmas = <0x12 0x0>;\n\t\t\tdma-names = \"video\";\n\t\t\tclocks = <0x13>;\n\n\t\t\tport {\n\n\t\t\t\tendpoint {\n\t\t\t\t\tremote-endpoint = <0x14>;\n\t\t\t\t\tlinux,phandle = <0xd>;\n\t\t\t\t\tphandle = <0xd>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\taxi-spdif-tx@75c00000 {\n\t\t\tcompatible = \"adi,axi-spdif-tx-1.00.a\";\n\t\t\treg = <0x75c00000 0x1000>;\n\t\t\tdmas = <0x15 0x0>;\n\t\t\tdma-names = \"tx\";\n\t\t\tclocks = <0x2 0xf 0xe>;\n\t\t\tclock-names = \"axi\", \"ref\";\n\t\t\t#sound-dai-cells = <0x0>;\n\t\t\tlinux,phandle = <0x16>;\n\t\t\tphandle = <0x16>;\n\t\t};\n\n\t\taxi-i2s@77600000 {\n\t\t\tcompatible = \"adi,axi-i2s-1.00.a\";\n\t\t\treg = <0x77600000 0x1000>;\n\t\t\tdmas = <0x15 0x1 0x15 0x2>;\n\t\t\tdma-names = \"tx\", \"rx\";\n\t\t\tclocks = <0x2 0xf 0xe>;\n\t\t\tclock-names = \"axi\", \"ref\";\n\t\t\t#sound-dai-cells = <0x0>;\n\t\t\tlinux,phandle = <0x18>;\n\t\t\tphandle = <0x18>;\n\t\t};\n\t};\n\n\tadv7511_hdmi_snd {\n\t\tcompatible = \"simple-audio-card\";\n\t\tsimple-audio-card,name = \"HDMI monitor\";\n\t\tsimple-audio-card,widgets = \"Speaker\", \"Speaker\";\n\t\tsimple-audio-card,routing = \"Speaker\", \"TX\";\n\n\t\tsimple-audio-card,dai-link@0 {\n\t\t\tformat = \"spdif\";\n\n\t\t\tcpu {\n\t\t\t\tsound-dai = <0x16>;\n\t\t\t\tframe-master;\n\t\t\t\tbitclock-master;\n\t\t\t};\n\n\t\t\tcodec {\n\t\t\t\tsound-dai = <0x17>;\n\t\t\t};\n\t\t};\n\t};\n\n\tzed_sound {\n\t\tcompatible = \"simple-audio-card\";\n\t\tsimple-audio-card,name = \"ZED ADAU1761\";\n\t\tsimple-audio-card,widgets = \"Microphone\", \"Mic In\", \"Headphone\", \"Headphone Out\", \"Line\", \"Line In\", \"Line\", \"Line Out\";\n\t\tsimple-audio-card,routing = \"Line Out\", \"LOUT\", \"Line Out\", \"ROUT\", \"Headphone Out\", \"LHP\", \"Headphone Out\", \"RHP\", \"Mic In\", \"MICBIAS\", \"LINN\", \"Mic In\", \"RINN\", \"Mic In\", \"LAUX\", \"Line In\", \"RAUX\", \"Line In\";\n\n\t\tsimple-audio-card,dai-link@0 {\n\t\t\tformat = \"i2s\";\n\n\t\t\tcpu {\n\t\t\t\tsound-dai = <0x18>;\n\t\t\t\tframe-master;\n\t\t\t\tbitclock-master;\n\t\t\t};\n\n\t\t\tcodec {\n\t\t\t\tsound-dai = <0x19>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled0 {\n\t\t\tlabel = \"led0:red\";\n\t\t\tgpios = <0x6 0x3d 0x0>;\n\t\t};\n\n\t\tled1 {\n\t\t\tlabel = \"led1:red\";\n\t\t\tgpios = <0x6 0x3b 0x0>;\n\t\t};\n\n\t\tled2 {\n\t\t\tlabel = \"led2:red\";\n\t\t\tgpios = <0x6 0x3a 0x0>;\n\t\t};\n\n\t\tled3 {\n\t\t\tlabel = \"led3:red\";\n\t\t\tgpios = <0x6 0x3c 0x0>;\n\t\t};\n\t};\n\n\tgpio_keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x0>;\n\t\tautorepeat;\n\n\t\tbt0 {\n\t\t\tlabel = \"BT0\";\n\t\t\tlinux,code = <0x69>;\n\t\t\tgpios = <0x6 0x36 0x0>;\n\t\t};\n\n\t\tbt1 {\n\t\t\tlabel = \"BT1\";\n\t\t\tlinux,code = <0x6a>;\n\t\t\tgpios = <0x6 0x37 0x0>;\n\t\t};\n\n\t\tbt2 {\n\t\t\tlabel = \"BT2\";\n\t\t\tlinux,code = <0x1c>;\n\t\t\tgpios = <0x6 0x38 0x0>;\n\t\t};\n\n\t\tbt3 {\n\t\t\tlabel = \"BT3\";\n\t\t\tlinux,code = <0x1>;\n\t\t\tgpios = <0x6 0x39 0x0>;\n\t\t};\n\n\t\tsw0 {\n\t\t\tlabel = \"SW0\";\n\t\t\tlinux,input-type = <0x5>;\n\t\t\tlinux,code = <0x0>;\n\t\t\tgpios = <0x6 0x41 0x0>;\n\t\t};\n\n\t\tsw1 {\n\t\t\tlabel = \"SW1\";\n\t\t\tlinux,input-type = <0x5>;\n\t\t\tlinux,code = <0x1>;\n\t\t\tgpios = <0x6 0x3e 0x0>;\n\t\t};\n\n\t\tsw2 {\n\t\t\tlabel = \"SW2\";\n\t\t\tlinux,input-type = <0x5>;\n\t\t\tlinux,code = <0x2>;\n\t\t\tgpios = <0x6 0x40 0x0>;\n\t\t};\n\n\t\tsw3 {\n\t\t\tlabel = \"SW3\";\n\t\t\tlinux,input-type = <0x5>;\n\t\t\tlinux,code = <0x3>;\n\t\t\tgpios = <0x6 0x3f 0x0>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "kernel_boot/boards/adrv9364z7020/devicetree.dts",
    "content": "/dts-v1/;\n\n/ {\n\t#address-cells = <0x01>;\n\t#size-cells = <0x01>;\n\tcompatible = \"xlnx,zynq-7000\";\n\tinterrupt-parent = <0x01>;\n\tmodel = \"Analog Devices ADRV9364-Z7020 (Z7020/AD9364)\";\n\n\tcpus {\n\t\t#address-cells = <0x01>;\n\t\t#size-cells = <0x00>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0x00>;\n\t\t\tclocks = <0x02 0x03>;\n\t\t\tclock-latency = <0x3e8>;\n\t\t\tcpu0-supply = <0x03>;\n\t\t\toperating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>;\n\t\t\tphandle = <0x11>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0x01>;\n\t\t\tclocks = <0x02 0x03>;\n\t\t\tphandle = <0x13>;\n\t\t};\n\t};\n\n\tfpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <0x04>;\n\t\t#address-cells = <0x01>;\n\t\t#size-cells = <0x01>;\n\t\tranges;\n\t\tphandle = <0x19>;\n\t};\n\n\tpmu@f8891000 {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0x00 0x05 0x04 0x00 0x06 0x04>;\n\t\tinterrupt-parent = <0x01>;\n\t\treg = <0xf8891000 0x1000 0xf8893000 0x1000>;\n\t};\n\n\tfixedregulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <0xf4240>;\n\t\tregulator-max-microvolt = <0xf4240>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t\tphandle = <0x03>;\n\t};\n\n\treplicator {\n\t\tcompatible = \"arm,coresight-static-replicator\";\n\t\tclocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;\n\t\tclock-names = \"apb_pclk\\0dbg_trc\\0dbg_apb\";\n\n\t\tout-ports {\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\n\t\t\tport@0 {\n\t\t\t\treg = <0x00>;\n\n\t\t\t\tendpoint {\n\t\t\t\t\tremote-endpoint = <0x05>;\n\t\t\t\t\tphandle = <0x0d>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tport@1 {\n\t\t\t\treg = <0x01>;\n\n\t\t\t\tendpoint {\n\t\t\t\t\tremote-endpoint = <0x06>;\n\t\t\t\t\tphandle = <0x0c>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tin-ports {\n\n\t\t\tport {\n\n\t\t\t\tendpoint {\n\t\t\t\t\tremote-endpoint = <0x07>;\n\t\t\t\t\tphandle = <0x0e>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\taxi {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x01>;\n\t\t#size-cells = <0x01>;\n\t\tinterrupt-parent = <0x01>;\n\t\tranges;\n\t\tphandle = <0x1a>;\n\n\t\tadc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0x00 0x07 0x04>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tclocks = <0x02 0x0c>;\n\t\t\tphandle = <0x1b>;\n\t\t};\n\n\t\tcan@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x02 0x13 0x02 0x24>;\n\t\t\tclock-names = \"can_clk\\0pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0x00 0x1c 0x04>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tphandle = <0x1c>;\n\t\t};\n\n\t\tcan@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x02 0x14 0x02 0x25>;\n\t\t\tclock-names = \"can_clk\\0pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0x00 0x33 0x04>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tphandle = <0x1d>;\n\t\t};\n\n\t\tgpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <0x02>;\n\t\t\tclocks = <0x02 0x2a>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <0x02>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x14 0x04>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t\tphandle = <0x09>;\n\t\t};\n\n\t\ti2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x02 0x26>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x19 0x04>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tphandle = <0x1e>;\n\t\t};\n\n\t\ti2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x02 0x27>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x30 0x04>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tphandle = <0x1f>;\n\t\t};\n\n\t\tinterrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <0x03>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xf8f01000 0x1000 0xf8f00100 0x100>;\n\t\t\tphandle = <0x01>;\n\t\t};\n\n\t\tcache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xf8f02000 0x1000>;\n\t\t\tinterrupts = <0x00 0x02 0x04>;\n\t\t\tarm,data-latency = <0x03 0x02 0x02>;\n\t\t\tarm,tag-latency = <0x02 0x02 0x02>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <0x02>;\n\t\t\tphandle = <0x20>;\n\t\t};\n\n\t\tmemory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t\tphandle = <0x21>;\n\t\t};\n\n\t\tocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x03 0x04>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t\tphandle = <0x22>;\n\t\t};\n\n\t\tserial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\\0cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x02 0x17 0x02 0x28>;\n\t\t\tclock-names = \"uart_clk\\0pclk\";\n\t\t\treg = <0xe0000000 0x1000>;\n\t\t\tinterrupts = <0x00 0x1b 0x04>;\n\t\t\tphandle = <0x23>;\n\t\t};\n\n\t\tserial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\\0cdns,uart-r1p8\";\n\t\t\tstatus = \"okay\";\n\t\t\tclocks = <0x02 0x18 0x02 0x29>;\n\t\t\tclock-names = \"uart_clk\\0pclk\";\n\t\t\treg = <0xe0001000 0x1000>;\n\t\t\tinterrupts = <0x00 0x32 0x04>;\n\t\t\tphandle = <0x24>;\n\t\t};\n\n\t\tspi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x1a 0x04>;\n\t\t\tclocks = <0x02 0x19 0x02 0x22>;\n\t\t\tclock-names = \"ref_clk\\0pclk\";\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tphandle = <0x25>;\n\n\t\t\tad9361-phy@0 {\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x0>;\n\t\t\t\t#clock-cells = <0x1>;\n\t\t\t\tcompatible = \"adi,ad9361\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tspi-cpha;\n\t\t\t\tspi-max-frequency = <0x989680>;\n\t\t\t\tclocks = <0x08 0x00>;\n\t\t\t\tclock-names = \"ad9361_ext_refclk\";\n\t\t\t\tclock-output-names = \"rx_sampl_clk\", \"tx_sampl_clk\";\n\t\t\t\tadi,digital-interface-tune-skip-mode = <0x0>;\n\t\t\t\tadi,pp-tx-swap-enable;\n\t\t\t\tadi,pp-rx-swap-enable;\n\t\t\t\tadi,rx-frame-pulse-mode-enable;\n\t\t\t\tadi,lvds-mode-enable;\n\t\t\t\tadi,lvds-bias-mV = <0x96>;\n\t\t\t\tadi,lvds-rx-onchip-termination-enable;\n\t\t\t\tadi,rx-data-delay = <0x4>;\n\t\t\t\tadi,tx-fb-clock-delay = <0x7>;\n\t\t\t\tadi,xo-disable-use-ext-refclk-enable;\n\t\t\t\tadi,2rx-2tx-mode-enable;\n\t\t\t\tadi,frequency-division-duplex-mode-enable;\n\t\t\t\tadi,rx-rf-port-input-select = <0x0>;\n\t\t\t\tadi,tx-rf-port-input-select = <0x0>;\n\t\t\t\tadi,tx-attenuation-mdB = <0x2710>;\n\t\t\t\tadi,tx-lo-powerdown-managed-enable;\n\t\t\t\tadi,rf-rx-bandwidth-hz = <0x112a880>;\n\t\t\t\tadi,rf-tx-bandwidth-hz = <0x112a880>;\n\t\t\t\tadi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;\n\t\t\t\tadi,tx-synthesizer-frequency-hz = <0x0 0x92080880>;\n\t\t\t\tadi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;\n\t\t\t\tadi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;\n\t\t\t\tadi,gc-rx1-mode = <0x2>;\n\t\t\t\tadi,gc-rx2-mode = <0x2>;\n\t\t\t\tadi,gc-adc-ovr-sample-size = <0x4>;\n\t\t\t\tadi,gc-adc-small-overload-thresh = <0x2f>;\n\t\t\t\tadi,gc-adc-large-overload-thresh = <0x3a>;\n\t\t\t\tadi,gc-lmt-overload-high-thresh = <0x320>;\n\t\t\t\tadi,gc-lmt-overload-low-thresh = <0x2c0>;\n\t\t\t\tadi,gc-dec-pow-measurement-duration = <0x2000>;\n\t\t\t\tadi,gc-low-power-thresh = <0x18>;\n\t\t\t\tadi,mgc-inc-gain-step = <0x2>;\n\t\t\t\tadi,mgc-dec-gain-step = <0x2>;\n\t\t\t\tadi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;\n\t\t\t\tadi,agc-attack-delay-extra-margin-us = <0x1>;\n\t\t\t\tadi,agc-outer-thresh-high = <0x5>;\n\t\t\t\tadi,agc-outer-thresh-high-dec-steps = <0x2>;\n\t\t\t\tadi,agc-inner-thresh-high = <0xa>;\n\t\t\t\tadi,agc-inner-thresh-high-dec-steps = <0x1>;\n\t\t\t\tadi,agc-inner-thresh-low = <0xc>;\n\t\t\t\tadi,agc-inner-thresh-low-inc-steps = <0x1>;\n\t\t\t\tadi,agc-outer-thresh-low = <0x12>;\n\t\t\t\tadi,agc-outer-thresh-low-inc-steps = <0x2>;\n\t\t\t\tadi,agc-adc-small-overload-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-adc-large-overload-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-adc-large-overload-inc-steps = <0x7>;\n\t\t\t\tadi,agc-lmt-overload-large-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-lmt-overload-small-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-lmt-overload-large-inc-steps = <0x7>;\n\t\t\t\tadi,agc-gain-update-interval-us = <0x3e8>;\n\t\t\t\tadi,fagc-dec-pow-measurement-duration = <0x10>;\n        adi,fagc-adc-large-overload-inc-steps = <0x07>;\n\t\t\t\tadi,fagc-lp-thresh-increment-steps = <0x1>;\n\t\t\t\tadi,fagc-lp-thresh-increment-time = <0x5>;\n\t\t\t\tadi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;\n        adi,fagc-dig-sat-ovrg-enable;\n\t\t\t\tadi,fagc-final-overrange-count = <0x3>;\n\t\t\t\tadi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;\n\t\t\t\tadi,fagc-lmt-final-settling-steps = <0x1>;\n\t\t\t\tadi,fagc-lock-level = <0xa>;\n\t\t\t\tadi,fagc-lock-level-gain-increase-upper-limit = <0x5>;\n\t\t\t\tadi,fagc-lock-level-lmt-gain-increase-enable;\n\t\t\t\tadi,fagc-lpf-final-settling-steps = <0x1>;\n\t\t\t\tadi,fagc-optimized-gain-offset = <0x5>;\n\t\t\t\tadi,fagc-power-measurement-duration-in-state5 = <0x10>;\n\t\t\t\tadi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;\n\t\t\t\tadi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;\n\t\t\t\tadi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;\n\t\t\t\tadi,fagc-rst-gla-large-adc-overload-enable;\n\t\t\t\tadi,fagc-rst-gla-large-lmt-overload-enable;\n\t\t\t\tadi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;\n\t\t\t\tadi,fagc-state-wait-time-ns = <0x104>;\n\t\t\t\tadi,fagc-use-last-lock-level-for-set-gain-enable;\n\t\t\t\tadi,rssi-restart-mode = <0x3>;\n\t\t\t\tadi,rssi-delay = <0x1>;\n\t\t\t\tadi,rssi-wait = <0x1>;\n\t\t\t\tadi,rssi-duration = <0x3e8>;\n\t\t\t\tadi,ctrl-outs-index = <0x0>;\n\t\t\t\tadi,ctrl-outs-enable-mask = <0xff>;\n\t\t\t\tadi,temp-sense-measurement-interval-ms = <0x3e8>;\n\t\t\t\tadi,temp-sense-offset-signed = <0xce>;\n\t\t\t\tadi,temp-sense-periodic-measurement-enable;\n\t\t\t\tadi,aux-dac-manual-mode-enable;\n\t\t\t\tadi,aux-dac1-default-value-mV = <0x0>;\n\t\t\t\tadi,aux-dac1-rx-delay-us = <0x0>;\n\t\t\t\tadi,aux-dac1-tx-delay-us = <0x0>;\n\t\t\t\tadi,aux-dac2-default-value-mV = <0x0>;\n\t\t\t\tadi,aux-dac2-rx-delay-us = <0x0>;\n\t\t\t\tadi,aux-dac2-tx-delay-us = <0x0>;\n\t\t\t\ten_agc-gpios = <0x09 0x62 0x0>;\n\t\t\t\tsync-gpios = <0x09 0x63 0x0>;\n\t\t\t\treset-gpios = <0x09 0x64 0x0>;\n\t\t\t\tenable-gpios = <0x09 0x65 0x0>;\n\t\t\t\ttxnrx-gpios = <0x09 0x66 0x0>;\n\t\t\t\tphandle = <0x17>;\n\t\t\t};\n\t\t};\n\n\t\tspi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x31 0x04>;\n\t\t\tclocks = <0x02 0x1a 0x02 0x23>;\n\t\t\tclock-names = \"ref_clk\\0pclk\";\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tphandle = <0x26>;\n\t\t};\n\n\t\tspi@e000d000 {\n\t\t\tclock-names = \"ref_clk\\0pclk\";\n\t\t\tclocks = <0x02 0x0a 0x02 0x2b>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x13 0x04>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tis-dual = <0x00>;\n\t\t\tnum-cs = <0x01>;\n\t\t\tphandle = <0x27>;\n\n\t\t\tps7-qspi@0 {\n\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t#size-cells = <0x01>;\n\t\t\t\tspi-tx-bus-width = <0x01>;\n\t\t\t\tspi-rx-bus-width = <0x04>;\n\t\t\t\tcompatible = \"n25q256a\\0jedec,spi-nor\";\n\t\t\t\treg = <0x00>;\n\t\t\t\tspi-max-frequency = <0x2faf080>;\n\t\t\t\tphandle = <0x28>;\n\n\t\t\t\tpartition@qspi-fsbl-uboot {\n\t\t\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\t\t\treg = <0x00 0xe0000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-uboot-env {\n\t\t\t\t\tlabel = \"qspi-uboot-env\";\n\t\t\t\t\treg = <0xe0000 0x20000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-linux {\n\t\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\t\treg = <0x100000 0x500000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-device-tree {\n\t\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\t\treg = <0x600000 0x20000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-rootfs {\n\t\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\t\treg = <0x620000 0xce0000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-bitstream {\n\t\t\t\t\tlabel = \"qspi-bitstream\";\n\t\t\t\t\treg = <0x1300000 0xd00000>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tmemory-controller@e000e000 {\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x01>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\\0apb_pclk\";\n\t\t\tclocks = <0x02 0x0b 0x02 0x2c>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\\0arm,primecell\";\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x12 0x04>;\n\t\t\tranges;\n\t\t\treg = <0xe000e000 0x1000>;\n\t\t\tphandle = <0x29>;\n\n\t\t\tflash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t#size-cells = <0x01>;\n\t\t\t\tphandle = <0x2a>;\n\t\t\t};\n\n\t\t\tflash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x2000000>;\n\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t#size-cells = <0x01>;\n\t\t\t\tphandle = <0x2b>;\n\t\t\t};\n\t\t};\n\n\t\tethernet@e000b000 {\n\t\t\tcompatible = \"cdns,zynq-gem\\0cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupts = <0x00 0x16 0x04>;\n\t\t\tclocks = <0x02 0x1e 0x02 0x1e 0x02 0x0d>;\n\t\t\tclock-names = \"pclk\\0hclk\\0tx_clk\";\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tphy-handle = <0x0a>;\n\t\t\tphy-mode = \"rgmii-id\";\n\t\t\tphandle = <0x2c>;\n\n\t\t\tphy@0 {\n\t\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\t\treg = <0x00>;\n\t\t\t\tmarvell,reg-init = <0x03 0x10 0xff00 0x1e 0x03 0x11 0xfff0 0x00>;\n\t\t\t\tphandle = <0x0a>;\n\t\t\t};\n\t\t};\n\n\t\tethernet@e000c000 {\n\t\t\tcompatible = \"cdns,zynq-gem\\0cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0x00 0x2d 0x04>;\n\t\t\tclocks = <0x02 0x1f 0x02 0x1f 0x02 0x0e>;\n\t\t\tclock-names = \"pclk\\0hclk\\0tx_clk\";\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tphandle = <0x2d>;\n\t\t};\n\n\t\tmmc@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"clk_xin\\0clk_ahb\";\n\t\t\tclocks = <0x02 0x15 0x02 0x20>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x18 0x04>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t\tdisable-wp;\n\t\t\tphandle = <0x2e>;\n\t\t};\n\n\t\tmmc@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\\0clk_ahb\";\n\t\t\tclocks = <0x02 0x16 0x02 0x21>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x2f 0x04>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t\tphandle = <0x2f>;\n\t\t};\n\n\t\tslcr@f8000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x01>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\\0syscon\\0simple-mfd\";\n\t\t\treg = <0xf8000000 0x1000>;\n\t\t\tranges;\n\t\t\tphandle = <0x0b>;\n\n\t\t\tclkc@100 {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <0x01>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0x0f>;\n\t\t\t\tclock-output-names = \"armpll\\0ddrpll\\0iopll\\0cpu_6or4x\\0cpu_3or2x\\0cpu_2x\\0cpu_1x\\0ddr2x\\0ddr3x\\0dci\\0lqspi\\0smc\\0pcap\\0gem0\\0gem1\\0fclk0\\0fclk1\\0fclk2\\0fclk3\\0can0\\0can1\\0sdio0\\0sdio1\\0uart0\\0uart1\\0spi0\\0spi1\\0dma\\0usb0_aper\\0usb1_aper\\0gem0_aper\\0gem1_aper\\0sdio0_aper\\0sdio1_aper\\0spi0_aper\\0spi1_aper\\0can0_aper\\0can1_aper\\0i2c0_aper\\0i2c1_aper\\0uart0_aper\\0uart1_aper\\0gpio_aper\\0lqspi_aper\\0smc_aper\\0swdt\\0dbg_trc\\0dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t\tps-clk-frequency = <0x1fca055>;\n\t\t\t\tphandle = <0x02>;\n\t\t\t};\n\n\t\t\trstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <0x01>;\n\t\t\t\tsyscon = <0x0b>;\n\t\t\t\tphandle = <0x30>;\n\t\t\t};\n\n\t\t\tpinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <0x0b>;\n\t\t\t\tphandle = <0x31>;\n\t\t\t};\n\t\t};\n\n\t\tdmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\\0arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupt-names = \"abort\\0dma0\\0dma1\\0dma2\\0dma3\\0dma4\\0dma5\\0dma6\\0dma7\";\n\t\t\tinterrupts = <0x00 0x0d 0x04 0x00 0x0e 0x04 0x00 0x0f 0x04 0x00 0x10 0x04 0x00 0x11 0x04 0x00 0x28 0x04 0x00 0x29 0x04 0x00 0x2a 0x04 0x00 0x2b 0x04>;\n\t\t\t#dma-cells = <0x01>;\n\t\t\t#dma-channels = <0x08>;\n\t\t\t#dma-requests = <0x04>;\n\t\t\tclocks = <0x02 0x1b>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t\tphandle = <0x32>;\n\t\t};\n\n\t\tdevcfg@f8007000 {\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x08 0x04>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tclocks = <0x02 0x0c 0x02 0x0f 0x02 0x10 0x02 0x11 0x02 0x12>;\n\t\t\tclock-names = \"ref_clk\\0fclk0\\0fclk1\\0fclk2\\0fclk3\";\n\t\t\tsyscon = <0x0b>;\n\t\t\tphandle = <0x04>;\n\t\t};\n\n\t\tefuse@f800d000 {\n\t\t\tcompatible = \"xlnx,zynq-efuse\";\n\t\t\treg = <0xf800d000 0x20>;\n\t\t\tphandle = <0x33>;\n\t\t};\n\n\t\ttimer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <0x01 0x0b 0x301>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tclocks = <0x02 0x04>;\n\t\t\tphandle = <0x34>;\n\t\t};\n\n\t\ttimer@f8001000 {\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x0a 0x04 0x00 0x0b 0x04 0x00 0x0c 0x04>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <0x02 0x06>;\n\t\t\treg = <0xf8001000 0x1000>;\n\t\t\tphandle = <0x35>;\n\t\t};\n\n\t\ttimer@f8002000 {\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x25 0x04 0x00 0x26 0x04 0x00 0x27 0x04>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <0x02 0x06>;\n\t\t\treg = <0xf8002000 0x1000>;\n\t\t\tphandle = <0x36>;\n\t\t};\n\n\t\ttimer@f8f00600 {\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x01 0x0d 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <0x02 0x04>;\n\t\t\tphandle = <0x37>;\n\t\t};\n\n\t\tusb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\\0chipidea,usb2\";\n\t\t\tstatus = \"okay\";\n\t\t\tclocks = <0x02 0x1c>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x15 0x04>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t\tdr_mode = \"host\";\n\t\t\txlnx,phy-reset-gpio = <0x09 0x07 0x00>;\n\t\t\tphandle = <0x38>;\n\t\t};\n\n\t\tusb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\\0chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x02 0x1d>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x2c 0x04>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t\tphandle = <0x39>;\n\t\t};\n\n\t\twatchdog@f8005000 {\n\t\t\tclocks = <0x02 0x2d>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x09 0x01>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <0x0a>;\n\t\t\tphandle = <0x3a>;\n\t\t};\n\n\t\tetb@f8801000 {\n\t\t\tcompatible = \"arm,coresight-etb10\\0arm,primecell\";\n\t\t\treg = <0xf8801000 0x1000>;\n\t\t\tclocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;\n\t\t\tclock-names = \"apb_pclk\\0dbg_trc\\0dbg_apb\";\n\n\t\t\tin-ports {\n\n\t\t\t\tport {\n\n\t\t\t\t\tendpoint {\n\t\t\t\t\t\tremote-endpoint = <0x0c>;\n\t\t\t\t\t\tphandle = <0x06>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\ttpiu@f8803000 {\n\t\t\tcompatible = \"arm,coresight-tpiu\\0arm,primecell\";\n\t\t\treg = <0xf8803000 0x1000>;\n\t\t\tclocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;\n\t\t\tclock-names = \"apb_pclk\\0dbg_trc\\0dbg_apb\";\n\n\t\t\tin-ports {\n\n\t\t\t\tport {\n\n\t\t\t\t\tendpoint {\n\t\t\t\t\t\tremote-endpoint = <0x0d>;\n\t\t\t\t\t\tphandle = <0x05>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tfunnel@f8804000 {\n\t\t\tcompatible = \"arm,coresight-static-funnel\\0arm,primecell\";\n\t\t\treg = <0xf8804000 0x1000>;\n\t\t\tclocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;\n\t\t\tclock-names = \"apb_pclk\\0dbg_trc\\0dbg_apb\";\n\n\t\t\tout-ports {\n\n\t\t\t\tport {\n\n\t\t\t\t\tendpoint {\n\t\t\t\t\t\tremote-endpoint = <0x0e>;\n\t\t\t\t\t\tphandle = <0x07>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tin-ports {\n\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t#size-cells = <0x00>;\n\n\t\t\t\tport@0 {\n\t\t\t\t\treg = <0x00>;\n\n\t\t\t\t\tendpoint {\n\t\t\t\t\t\tremote-endpoint = <0x0f>;\n\t\t\t\t\t\tphandle = <0x12>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tport@1 {\n\t\t\t\t\treg = <0x01>;\n\n\t\t\t\t\tendpoint {\n\t\t\t\t\t\tremote-endpoint = <0x10>;\n\t\t\t\t\t\tphandle = <0x14>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tport@2 {\n\t\t\t\t\treg = <0x02>;\n\n\t\t\t\t\tendpoint {\n\t\t\t\t\t\tphandle = <0x3b>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tptm@f889c000 {\n\t\t\tcompatible = \"arm,coresight-etm3x\\0arm,primecell\";\n\t\t\treg = <0xf889c000 0x1000>;\n\t\t\tclocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;\n\t\t\tclock-names = \"apb_pclk\\0dbg_trc\\0dbg_apb\";\n\t\t\tcpu = <0x11>;\n\n\t\t\tout-ports {\n\n\t\t\t\tport {\n\n\t\t\t\t\tendpoint {\n\t\t\t\t\t\tremote-endpoint = <0x12>;\n\t\t\t\t\t\tphandle = <0x0f>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tptm@f889d000 {\n\t\t\tcompatible = \"arm,coresight-etm3x\\0arm,primecell\";\n\t\t\treg = <0xf889d000 0x1000>;\n\t\t\tclocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;\n\t\t\tclock-names = \"apb_pclk\\0dbg_trc\\0dbg_apb\";\n\t\t\tcpu = <0x13>;\n\n\t\t\tout-ports {\n\n\t\t\t\tport {\n\n\t\t\t\t\tendpoint {\n\t\t\t\t\t\tremote-endpoint = <0x14>;\n\t\t\t\t\t\tphandle = <0x10>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\taliases {\n\t\tethernet0 = \"/axi/ethernet@e000b000\";\n\t\tserial0 = \"/axi/serial@e0001000\";\n\t\tphandle = <0x3c>;\n\t};\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x00 0x40000000>;\n\t};\n\n\tchosen {\n\t\tstdout-path = \"/amba@0/uart@E0001000\";\n\t};\n\n\tclocks {\n\n\t\tclock@0 {\n\t\t\t#clock-cells = <0x00>;\n\t\t\tcompatible = \"adjustable-clock\";\n\t\t\tclock-frequency = <0x2625a00>;\n\t\t\tclock-accuracy = <0x30d40>;\n\t\t\tclock-output-names = \"ad9364_ext_refclk\";\n\t\t\tphandle = <0x08>;\n\t\t};\n\n\t\tclock@1 {\n\t\t\t#clock-cells = <0x00>;\n\t\t\tcompatible = \"fixed-clock\";\n\t\t\tclock-frequency = <0x16e3600>;\n\t\t\tclock-output-names = \"24MHz\";\n\t\t\tphandle = <0x15>;\n\t\t};\n\t};\n\n\tusb-ulpi-gpio-gate@0 {\n\t\tcompatible = \"gpio-gate-clock\";\n\t\tclocks = <0x15>;\n\t\t#clock-cells = <0x00>;\n\t\tenable-gpios = <0x09 0x09 0x01>;\n\t\tphandle = <0x3d>;\n\t};\n\n\tfpga-axi@0 {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x01>;\n\t\t#size-cells = <0x01>;\n\t\tranges;\n\t\tphandle = <0x3e>;\n\n\t\ti2c@41600000 {\n\t\t\tcompatible = \"xlnx,axi-iic-1.02.a\\0xlnx,xps-iic-2.00.a\";\n\t\t\treg = <0x41600000 0x10000>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x3a 0x04>;\n\t\t\tclocks = <0x02 0x0f>;\n\t\t\tclock-names = \"pclk\";\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tphandle = <0x3f>;\n\n\t\t\tad7291@20 {\n\t\t\t\tcompatible = \"adi,ad7291\";\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tad7291-bob@2C {\n\t\t\t\tcompatible = \"adi,ad7291\";\n\t\t\t\treg = <0x2c>;\n\t\t\t};\n\n\t\t\teeprom@50 {\n\t\t\t\tcompatible = \"at24,24c32\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\n\t\t// dma@7c400000 {\n\t\t// \tcompatible = \"adi,axi-dmac-1.00.a\";\n\t\t// \treg = <0x7c400000 0x10000>;\n\t\t// \t#dma-cells = <0x01>;\n\t\t// \tinterrupts = <0x00 0x39 0x04>;\n\t\t// \tclocks = <0x02 0x10>;\n\t\t// \tphandle = <0x16>;\n\n\t\t// \tadi,channels {\n\t\t// \t\t#size-cells = <0x00>;\n\t\t// \t\t#address-cells = <0x01>;\n\n\t\t// \t\tdma-channel@0 {\n\t\t// \t\t\treg = <0x00>;\n\t\t// \t\t\tadi,source-bus-width = <0x40>;\n\t\t// \t\t\tadi,source-bus-type = <0x02>;\n\t\t// \t\t\tadi,destination-bus-width = <0x40>;\n\t\t// \t\t\tadi,destination-bus-type = <0x00>;\n\t\t// \t\t};\n\t\t// \t};\n\t\t// };\n\n\t\t// dma@7c420000 {\n\t\t// \tcompatible = \"adi,axi-dmac-1.00.a\";\n\t\t// \treg = <0x7c420000 0x10000>;\n\t\t// \t#dma-cells = <0x01>;\n\t\t// \tinterrupts = <0x00 0x38 0x04>;\n\t\t// \tclocks = <0x02 0x10>;\n\t\t// \tphandle = <0x18>;\n\n\t\t// \tadi,channels {\n\t\t// \t\t#size-cells = <0x00>;\n\t\t// \t\t#address-cells = <0x01>;\n\n\t\t// \t\tdma-channel@0 {\n\t\t// \t\t\treg = <0x00>;\n\t\t// \t\t\tadi,source-bus-width = <0x40>;\n\t\t// \t\t\tadi,source-bus-type = <0x00>;\n\t\t// \t\t\tadi,destination-bus-width = <0x40>;\n\t\t// \t\t\tadi,destination-bus-type = <0x02>;\n\t\t// \t\t};\n\t\t// \t};\n\t\t// };\n\n\t\tsdr: sdr {\n\t\t\tcompatible =\"sdr,sdr\";\n\t\t\tdmas = <&rx_dma 1\n\t\t\t\t\t&tx_dma 0>;\n\t\t\tdma-names = \"rx_dma_s2mm\", \"tx_dma_mm2s\";\n\t\t\tinterrupt-names = \"not_valid_anymore\", \"rx_pkt_intr\", \"tx_itrpt\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 29 1 0 30 1 0 33 1 0 34 1>;\n\t\t} ;\n\n\t\t// axidmatest_1: axidmatest@1 {\n\t\t// \tcompatible =\"xlnx,axi-dma-test-1.00.a\";\n\t\t// \tdmas = <&rx_dma 0\n\t\t// \t\t&rx_dma 1>;\n\t\t// \tdma-names = \"axidma0\", \"axidma1\";\n\t\t// } ;\n\n\t\ttx_dma: dma@80400000 {\n\t\t\t#dma-cells = <1>;\n\t\t\tclock-names = \"s_axi_lite_aclk\", \"m_axi_sg_aclk\", \"m_axi_mm2s_aclk\", \"m_axi_s2mm_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"xlnx,axi-dma-1.00.a\";\n\t\t\tinterrupt-names = \"mm2s_introut\", \"s2mm_introut\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 35 4 0 36 4>;\n\t\t\treg = <0x80400000 0x10000>;\n\t\t\txlnx,addrwidth = <0x20>;\n\t\t\txlnx,include-sg ;\n\t\t\txlnx,sg-length-width = <0xe>;\n\t\t\tdma-channel@80400000 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-mm2s-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 35 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x0>;\n\t\t\t};\n\t\t\tdma-channel@80400030 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-s2mm-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 36 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x0>;\n\t\t\t};\n\t\t};\n\t\t\n\t\trx_dma: dma@80410000 {\n\t\t\t#dma-cells = <1>;\n\t\t\tclock-names = \"s_axi_lite_aclk\", \"m_axi_sg_aclk\", \"m_axi_mm2s_aclk\", \"m_axi_s2mm_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"xlnx,axi-dma-1.00.a\";\n\t\t\t//dma-coherent ;\n\t\t\tinterrupt-names = \"mm2s_introut\", \"s2mm_introut\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 31 4 0 32 4>;\n\t\t\treg = <0x80410000 0x10000>;\n\t\t\txlnx,addrwidth = <0x20>;\n\t\t\txlnx,include-sg ;\n\t\t\txlnx,sg-length-width = <0xe>;\n\t\t\tdma-channel@80410000 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-mm2s-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 31 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x1>;\n\t\t\t};\n\t\t\tdma-channel@80410030 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-s2mm-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 32 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x1>;\n\t\t\t};\n\t\t};\n\n\t\ttx_intf_0: tx_intf@83c00000 {\n\t\t\tclock-names = \"s00_axi_aclk\", \"s00_axis_aclk\";//, \"s01_axis_aclk\", \"m00_axis_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"sdr,tx_intf\";\n\t\t\tinterrupt-names = \"tx_itrpt\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 34 1>;\n\t\t\treg = <0x83c00000 0x10000>;\n\t\t\txlnx,s00-axi-addr-width = <0x7>;\n\t\t\txlnx,s00-axi-data-width = <0x20>;\n\t\t};\n\n\t\trx_intf_0: rx_intf@83c20000 {\n\t\t\tclock-names = \"s00_axi_aclk\", \"m00_axis_aclk\";//, \"s00_axis_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>;\n\t\t\tcompatible = \"sdr,rx_intf\";\n\t\t\tinterrupt-names = \"not_valid_anymore\", \"rx_pkt_intr\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 29 1 0 30 1>;\n\t\t\treg = <0x83c20000 0x10000>;\n\t\t\txlnx,s00-axi-addr-width = <0x7>;\n\t\t\txlnx,s00-axi-data-width = <0x20>;\n\t\t};\n\n\t\topenofdm_tx_0: openofdm_tx@83c10000 {\n\t\t\tclock-names = \"clk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,openofdm_tx\";\n\t\t\treg = <0x83c10000 0x10000>;\n\t\t};\n\n\t\topenofdm_rx_0: openofdm_rx@83c30000 {\n\t\t\tclock-names = \"clk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,openofdm_rx\";\n\t\t\treg = <0x83c30000 0x10000>;\n\t\t};\n\n\t\txpu_0: xpu@83c40000 {\n\t\t\tclock-names = \"s00_axi_aclk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,xpu\";\n\t\t\treg = <0x83c40000 0x10000>;\n\t\t};\n\n\t\tside_ch_0: side_ch@83c50000 {\n\t\t\tclock-names = \"s00_axi_aclk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,side_ch\";\n\t\t\treg = <0x83c50000 0x10000>;\n\t\t\tdmas = <&rx_dma 0\n\t\t\t\t\t&tx_dma 1>;\n\t\t\tdma-names = \"rx_dma_mm2s\", \"tx_dma_s2mm\";\n\t\t};\n\n\t\tcf-ad9361-lpc@79020000 {\n\t\t\tcompatible = \"adi,axi-ad9361-6.00.a\";\n\t\t\treg = <0x79020000 0x6000>;\n\t\t\t// dmas = <0x16 0x00>;\n\t\t\t// dma-names = \"rx\";\n\t\t\tspibus-connected = <0x17>;\n\t\t\tphandle = <0x40>;\n\t\t};\n\n\t\tcf-ad9361-dds-core-lpc@79024000 {\n\t\t\tcompatible = \"adi,axi-ad9361-dds-6.00.a\";\n\t\t\treg = <0x79024000 0x1000>;\n\t\t\tclocks = <0x17 0x0d>;\n\t\t\tclock-names = \"sampl_clk\";\n\t\t\t// dmas = <0x18 0x00>;\n\t\t\t// dma-names = \"tx\";\n\t\t\tphandle = <0x41>;\n\t\t};\n\n\t\tmwipcore@43c00000 {\n\t\t\tcompatible = \"mathworks,mwipcore-axi4lite-v1.00\";\n\t\t\treg = <0x43c00000 0xffff>;\n\t\t};\n\n\t\t// axi-sysid-0@45000000 {\n\t\t// \tcompatible = \"adi,axi-sysid-1.00.a\";\n\t\t// \treg = <0x45000000 0x10000>;\n\t\t// \tphandle = <0x42>;\n\t\t// };\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled0 {\n\t\t\tlabel = \"led0:green\";\n\t\t\tgpios = <0x09 0x3a 0x00>;\n\t\t};\n\n\t\tled1 {\n\t\t\tlabel = \"led1:green\";\n\t\t\tgpios = <0x09 0x3b 0x00>;\n\t\t};\n\n\t\tled2 {\n\t\t\tlabel = \"led2:green\";\n\t\t\tgpios = <0x09 0x3c 0x00>;\n\t\t};\n\n\t\tled3 {\n\t\t\tlabel = \"led3:green\";\n\t\t\tgpios = <0x09 0x3d 0x00>;\n\t\t};\n\t};\n\n\tgpio_keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <0x01>;\n\t\t#size-cells = <0x00>;\n\t\tautorepeat;\n\n\t\tpb0 {\n\t\t\tlabel = \"Left\";\n\t\t\tlinux,code = <0x69>;\n\t\t\tgpios = <0x09 0x36 0x00>;\n\t\t};\n\n\t\tpb1 {\n\t\t\tlabel = \"Right\";\n\t\t\tlinux,code = <0x6a>;\n\t\t\tgpios = <0x09 0x37 0x00>;\n\t\t};\n\n\t\tpb2 {\n\t\t\tlabel = \"Up\";\n\t\t\tlinux,code = <0x67>;\n\t\t\tgpios = <0x09 0x38 0x00>;\n\t\t};\n\n\t\tpb3 {\n\t\t\tlabel = \"Down\";\n\t\t\tlinux,code = <0x6c>;\n\t\t\tgpios = <0x09 0x39 0x00>;\n\t\t};\n\n\t\tsw0 {\n\t\t\tlabel = \"SW0\";\n\t\t\tlinux,input-type = <0x05>;\n\t\t\tlinux,code = <0x0d>;\n\t\t\tgpios = <0x09 0x3e 0x00>;\n\t\t};\n\n\t\tsw1 {\n\t\t\tlabel = \"SW1\";\n\t\t\tlinux,input-type = <0x05>;\n\t\t\tlinux,code = <0x01>;\n\t\t\tgpios = <0x09 0x3f 0x00>;\n\t\t};\n\n\t\tsw2 {\n\t\t\tlabel = \"SW2\";\n\t\t\tlinux,input-type = <0x05>;\n\t\t\tlinux,code = <0x02>;\n\t\t\tgpios = <0x09 0x40 0x00>;\n\t\t};\n\n\t\tsw3 {\n\t\t\tlabel = \"SW3\";\n\t\t\tlinux,input-type = <0x05>;\n\t\t\tlinux,code = <0x03>;\n\t\t\tgpios = <0x09 0x41 0x00>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "kernel_boot/boards/antsdr/devicetree.dts",
    "content": "/dts-v1/;\n\n/ {\n\t#address-cells = <0x1>;\n\t#size-cells = <0x1>;\n\tcompatible = \"xlnx,zynq-7000\";\n\tinterrupt-parent = <0x1>;\n\tmodel = \"MicroPhase ANTSDR-E310 (Z7020/AD9361 Z7020/AD9363)\";\n\n\tcpus {\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0x0>;\n\t\t\tclocks = <0x2 0x3>;\n\t\t\tclock-latency = <0x3e8>;\n\t\t\tcpu0-supply = <0x3>;\n\t\t\toperating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0x1>;\n\t\t\tclocks = <0x2 0x3>;\n\t\t};\n\t};\n\n\tfpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <0x4>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tranges;\n\t};\n\n\tpmu@f8891000 {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0x0 0x5 0x4 0x0 0x6 0x4>;\n\t\tinterrupt-parent = <0x1>;\n\t\treg = <0xf8891000 0x1000 0xf8893000 0x1000>;\n\t};\n\n\tfixedregulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <0xf4240>;\n\t\tregulator-max-microvolt = <0xf4240>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t\tlinux,phandle = <0x3>;\n\t\tphandle = <0x3>;\n\t};\n\n\tamba {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tinterrupt-parent = <0x1>;\n\t\tranges;\n\n\t\tadc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0x0 0x7 0x4>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tclocks = <0x2 0xc>;\n\t\t};\n\n\t\tcan@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x13 0x2 0x24>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0x0 0x1c 0x4>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x14 0x2 0x25>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0x0 0x33 0x4>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tclocks = <0x2 0x2a>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <0x2>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x14 0x4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t\tlinux,phandle = <0x6>;\n\t\t\tphandle = <0x6>;\n\t\t};\n\n\t\ti2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x26>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x19 0x4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t};\n\n\t\ti2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x27>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x30 0x4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t};\n\n\t\tinterrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <0x3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xf8f01000 0x1000 0xf8f00100 0x100>;\n\t\t\tlinux,phandle = <0x1>;\n\t\t\tphandle = <0x1>;\n\t\t};\n\n\t\tcache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xf8f02000 0x1000>;\n\t\t\tinterrupts = <0x0 0x2 0x4>;\n\t\t\tarm,data-latency = <0x3 0x2 0x2>;\n\t\t\tarm,tag-latency = <0x2 0x2 0x2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <0x2>;\n\t\t};\n\n\t\tmemory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x3 0x4>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t};\n\n\t\tserial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x17 0x2 0x28>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xe0000000 0x1000>;\n\t\t\tinterrupts = <0x0 0x1b 0x4>;\n\t\t};\n\n\t\tserial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"okay\";\n\t\t\tclocks = <0x2 0x18 0x2 0x29>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xe0001000 0x1000>;\n\t\t\tinterrupts = <0x0 0x32 0x4>;\n\t\t};\n\n\t\tspi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x1a 0x4>;\n\t\t\tclocks = <0x2 0x19 0x2 0x22>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\n\t\t\tad9361-phy@0 {\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x0>;\n\t\t\t\t#clock-cells = <0x1>;\n\t\t\t\tcompatible = \"adi,ad9361\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tspi-cpha;\n\t\t\t\tspi-max-frequency = <0x989680>;\n\t\t\t\tclocks = <0x5 0x0>;\n\t\t\t\tclock-names = \"ad9364_ext_refclk\";\n\t\t\t\tclock-output-names = \"rx_sampl_clk\", \"tx_sampl_clk\";\n\t\t\t\tadi,digital-interface-tune-skip-mode = <0x0>;\n\t\t\t\tadi,pp-tx-swap-enable;\n\t\t\t\tadi,pp-rx-swap-enable;\n\t\t\t\tadi,rx-frame-pulse-mode-enable;\n\t\t\t\tadi,lvds-mode-enable;\n\t\t\t\tadi,lvds-bias-mV = <0x96>;\n\t\t\t\tadi,lvds-rx-onchip-termination-enable;\n\t\t\t\tadi,rx-data-delay = <0x4>;\n\t\t\t\tadi,tx-fb-clock-delay = <0x7>;\n\t\t\t\tadi,xo-disable-use-ext-refclk-enable;\n\t\t\t\tadi,2rx-2tx-mode-enable;\n\t\t\t\tadi,frequency-division-duplex-mode-enable;\n\t\t\t\tadi,rx-rf-port-input-select = <0x0>;\n\t\t\t\tadi,tx-rf-port-input-select = <0x0>;\n\t\t\t\tadi,tx-attenuation-mdB = <0x2710>;\n\t\t\t\tadi,tx-lo-powerdown-managed-enable;\n\t\t\t\tadi,rf-rx-bandwidth-hz = <0x112a880>;\n\t\t\t\tadi,rf-tx-bandwidth-hz = <0x112a880>;\n\t\t\t\tadi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;\n\t\t\t\tadi,tx-synthesizer-frequency-hz = <0x0 0x92080880>;\n\t\t\t\tadi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;\n\t\t\t\tadi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;\n\t\t\t\tadi,gc-rx1-mode = <0x2>;\n\t\t\t\tadi,gc-rx2-mode = <0x2>;\n\t\t\t\tadi,gc-adc-ovr-sample-size = <0x4>;\n\t\t\t\tadi,gc-adc-small-overload-thresh = <0x2f>;\n\t\t\t\tadi,gc-adc-large-overload-thresh = <0x3a>;\n\t\t\t\tadi,gc-lmt-overload-high-thresh = <0x320>;\n\t\t\t\tadi,gc-lmt-overload-low-thresh = <0x2c0>;\n\t\t\t\tadi,gc-dec-pow-measurement-duration = <0x2000>;\n\t\t\t\tadi,gc-low-power-thresh = <0x18>;\n\t\t\t\tadi,mgc-inc-gain-step = <0x2>;\n\t\t\t\tadi,mgc-dec-gain-step = <0x2>;\n\t\t\t\tadi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;\n\t\t\t\tadi,agc-attack-delay-extra-margin-us = <0x1>;\n\t\t\t\tadi,agc-outer-thresh-high = <0x5>;\n\t\t\t\tadi,agc-outer-thresh-high-dec-steps = <0x2>;\n\t\t\t\tadi,agc-inner-thresh-high = <0xa>;\n\t\t\t\tadi,agc-inner-thresh-high-dec-steps = <0x1>;\n\t\t\t\tadi,agc-inner-thresh-low = <0xc>;\n\t\t\t\tadi,agc-inner-thresh-low-inc-steps = <0x1>;\n\t\t\t\tadi,agc-outer-thresh-low = <0x12>;\n\t\t\t\tadi,agc-outer-thresh-low-inc-steps = <0x2>;\n\t\t\t\tadi,agc-adc-small-overload-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-adc-large-overload-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-adc-large-overload-inc-steps = <0x7>;\n\t\t\t\tadi,agc-lmt-overload-large-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-lmt-overload-small-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-lmt-overload-large-inc-steps = <0x7>;\n\t\t\t\tadi,agc-gain-update-interval-us = <0x3e8>;\n\t\t\t\tadi,fagc-dec-pow-measurement-duration = <0x10>;\n        adi,fagc-adc-large-overload-inc-steps = <0x07>;\n\t\t\t\tadi,fagc-lp-thresh-increment-steps = <0x1>;\n\t\t\t\tadi,fagc-lp-thresh-increment-time = <0x5>;\n\t\t\t\tadi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;\n        adi,fagc-dig-sat-ovrg-enable;\n\t\t\t\tadi,fagc-final-overrange-count = <0x3>;\n\t\t\t\tadi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;\n\t\t\t\tadi,fagc-lmt-final-settling-steps = <0x1>;\n\t\t\t\tadi,fagc-lock-level = <0xa>;\n\t\t\t\tadi,fagc-lock-level-gain-increase-upper-limit = <0x5>;\n\t\t\t\tadi,fagc-lock-level-lmt-gain-increase-enable;\n\t\t\t\tadi,fagc-lpf-final-settling-steps = <0x1>;\n\t\t\t\tadi,fagc-optimized-gain-offset = <0x5>;\n\t\t\t\tadi,fagc-power-measurement-duration-in-state5 = <0x10>;\n\t\t\t\tadi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;\n\t\t\t\tadi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;\n\t\t\t\tadi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;\n\t\t\t\tadi,fagc-rst-gla-large-adc-overload-enable;\n\t\t\t\tadi,fagc-rst-gla-large-lmt-overload-enable;\n\t\t\t\tadi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;\n\t\t\t\tadi,fagc-state-wait-time-ns = <0x104>;\n\t\t\t\tadi,fagc-use-last-lock-level-for-set-gain-enable;\n\t\t\t\tadi,rssi-restart-mode = <0x3>;\n\t\t\t\tadi,rssi-delay = <0x1>;\n\t\t\t\tadi,rssi-wait = <0x1>;\n\t\t\t\tadi,rssi-duration = <0x3e8>;\n\t\t\t\tadi,ctrl-outs-index = <0x0>;\n\t\t\t\tadi,ctrl-outs-enable-mask = <0xff>;\n\t\t\t\tadi,temp-sense-measurement-interval-ms = <0x3e8>;\n\t\t\t\tadi,temp-sense-offset-signed = <0xce>;\n\t\t\t\tadi,temp-sense-periodic-measurement-enable;\n\t\t\t\tadi,aux-dac-manual-mode-enable;\n\t\t\t\tadi,aux-dac1-default-value-mV = <0x0>;\n\t\t\t\tadi,aux-dac1-rx-delay-us = <0x0>;\n\t\t\t\tadi,aux-dac1-tx-delay-us = <0x0>;\n\t\t\t\tadi,aux-dac2-default-value-mV = <0x0>;\n\t\t\t\tadi,aux-dac2-rx-delay-us = <0x0>;\n\t\t\t\tadi,aux-dac2-tx-delay-us = <0x0>;\n\t\t\t\ten_agc-gpios = <0x6 0x62 0x0>;\n\t\t\t\tsync-gpios = <0x6 0x63 0x0>;\n\t\t\t\treset-gpios = <0x6 0x64 0x0>;\n\t\t\t\tenable-gpios = <0x6 0x65 0x0>;\n\t\t\t\ttxnrx-gpios = <0x6 0x66 0x0>;\n\t\t\t\tlinux,phandle = <0xb>;\n\t\t\t\tphandle = <0xb>;\n\t\t\t};\n\t\t};\n\n\t\tspi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x31 0x4>;\n\t\t\tclocks = <0x2 0x1a 0x2 0x23>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t};\n\n\t\tspi@e000d000 {\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tclocks = <0x2 0xa 0x2 0x2b>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x13 0x4>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\tis-dual = <0x0>;\n\t\t\tnum-cs = <0x1>;\n\n\t\t\tps7-qspi@0 {\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t\tspi-tx-bus-width = <0x1>;\n\t\t\t\tspi-rx-bus-width = <0x4>;\n\t\t\t\tcompatible = \"n25q256a\", \"jedec,spi-nor\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tspi-max-frequency = <0x2faf080>;\n\n\t\t\t\tpartition@qspi-fsbl-uboot {\n\t\t\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\t\t\treg = <0x0 0xe0000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-uboot-env {\n\t\t\t\t\tlabel = \"qspi-uboot-env\";\n\t\t\t\t\treg = <0xe0000 0x20000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-linux {\n\t\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\t\treg = <0x100000 0x500000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-device-tree {\n\t\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\t\treg = <0x600000 0x20000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-rootfs {\n\t\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\t\treg = <0x620000 0xce0000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-bitstream {\n\t\t\t\t\tlabel = \"qspi-bitstream\";\n\t\t\t\t\treg = <0x1300000 0xd00000>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tmemory-controller@e000e000 {\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x1>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"aclk\";\n\t\t\tclocks = <0x2 0xb 0x2 0x2c>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x12 0x4>;\n\t\t\tranges;\n\t\t\treg = <0xe000e000 0x1000>;\n\n\t\t\tflash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\n\t\t\tflash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x2000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\t\t};\n\n\t\tethernet@e000b000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupts = <0x0 0x16 0x4>;\n\t\t\tclocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\tphy-handle = <0x7>;\n\t\t\tphy-mode = \"rgmii-id\";\n\n\t\t\tphy@0 {\n\t\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tmarvell,reg-init = <0x3 0x10 0xff00 0x1e 0x3 0x11 0xfff0 0x0>;\n\t\t\t\tlinux,phandle = <0x7>;\n\t\t\t\tphandle = <0x7>;\n\t\t\t};\n\t\t};\n\n\t\tethernet@e000c000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0x0 0x2d 0x4>;\n\t\t\tclocks = <0x2 0x1f 0x2 0x1f 0x2 0xe>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t};\n\n\t\tmmc@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <0x2 0x15 0x2 0x20>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x18 0x4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t\tdisable-wp;\n\t\t};\n\n\t\tmmc@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <0x2 0x16 0x2 0x21>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x2f 0x4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t};\n\n\t\tslcr@f8000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\", \"simple-mfd\";\n\t\t\treg = <0xf8000000 0x1000>;\n\t\t\tranges;\n\t\t\tlinux,phandle = <0x8>;\n\t\t\tphandle = <0x8>;\n\n\t\t\tclkc@100 {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <0x1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\", \"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\", \"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\", \"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\", \"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\", \"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\", \"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\", \"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\", \"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\", \"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t\tps-clk-frequency = <0x1fca055>;\n\t\t\t\tlinux,phandle = <0x2>;\n\t\t\t\tphandle = <0x2>;\n\t\t\t};\n\n\t\t\trstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <0x1>;\n\t\t\t\tsyscon = <0x8>;\n\t\t\t};\n\n\t\t\tpinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <0x8>;\n\t\t\t};\n\t\t};\n\n\t\tdmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\", \"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\tinterrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>;\n\t\t\t#dma-cells = <0x1>;\n\t\t\t#dma-channels = <0x8>;\n\t\t\t#dma-requests = <0x4>;\n\t\t\tclocks = <0x2 0x1b>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t};\n\n\t\tdevcfg@f8007000 {\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x8 0x4>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tclocks = <0x2 0xc 0x2 0xf 0x2 0x10 0x2 0x11 0x2 0x12>;\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tsyscon = <0x8>;\n\t\t\tlinux,phandle = <0x4>;\n\t\t\tphandle = <0x4>;\n\t\t};\n\n\t\tefuse@f800d000 {\n\t\t\tcompatible = \"xlnx,zynq-efuse\";\n\t\t\treg = <0xf800d000 0x20>;\n\t\t};\n\n\t\ttimer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <0x1 0xb 0x301>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tclocks = <0x2 0x4>;\n\t\t};\n\n\t\ttimer@f8001000 {\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <0x2 0x6>;\n\t\t\treg = <0xf8001000 0x1000>;\n\t\t};\n\n\t\ttimer@f8002000 {\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <0x2 0x6>;\n\t\t\treg = <0xf8002000 0x1000>;\n\t\t};\n\n\t\ttimer@f8f00600 {\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x1 0xd 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <0x2 0x4>;\n\t\t};\n\n\t\tusb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"okay\";\n\t\t\tclocks = <0x2 0x1c>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x15 0x4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t\tdr_mode = \"host\";\n\t\t\txlnx,phy-reset-gpio = <0x6 0x7 0x0>;\n\t\t};\n\n\t\tusb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x1d>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x2c 0x4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog@f8005000 {\n\t\t\tclocks = <0x2 0x2d>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x9 0x1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <0xa>;\n\t\t};\n\t};\n\n\taliases {\n\t\tethernet0 = \"/amba/ethernet@e000b000\";\n\t\tserial0 = \"/amba/serial@e0001000\";\n\t};\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x40000000>;\n\t};\n\n\tchosen {\n\t\tlinux,stdout-path = \"/amba@0/uart@E0001000\";\n\t};\n\n\tclocks {\n\n\t\tclock@0 {\n\t\t\t#clock-cells = <0x0>;\n\t\t\tcompatible = \"adjustable-clock\";\n\t\t\tclock-frequency = <0x2625a00>;\n\t\t\tclock-accuracy = <0x30d40>;\n\t\t\tclock-output-names = \"ad9364_ext_refclk\";\n\t\t\tlinux,phandle = <0x5>;\n\t\t\tphandle = <0x5>;\n\t\t};\n\n\t\tclock@1 {\n\t\t\t#clock-cells = <0x0>;\n\t\t\tcompatible = \"fixed-clock\";\n\t\t\tclock-frequency = <0x16e3600>;\n\t\t\tclock-output-names = \"24MHz\";\n\t\t\tlinux,phandle = <0x9>;\n\t\t\tphandle = <0x9>;\n\t\t};\n\t};\n\n\tusb-ulpi-gpio-gate@0 {\n\t\tcompatible = \"gpio-gate-clock\";\n\t\tclocks = <0x9>;\n\t\t#clock-cells = <0x0>;\n\t\tenable-gpios = <0x6 0x9 0x1>;\n\t};\n\n\tfpga-axi@0 {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tranges;\n\n\t\ti2c@41600000 {\n\t\t\tcompatible = \"xlnx,axi-iic-1.02.a\", \"xlnx,xps-iic-2.00.a\";\n\t\t\treg = <0x41600000 0x10000>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x3a 0x4>;\n\t\t\tclocks = <0x2 0xf>;\n\t\t\tclock-names = \"pclk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\n\t\t\tad7291@20 {\n\t\t\t\tcompatible = \"adi,ad7291\";\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tad7291-bob@2C {\n\t\t\t\tcompatible = \"adi,ad7291\";\n\t\t\t\treg = <0x2c>;\n\t\t\t};\n\n\t\t\teeprom@50 {\n\t\t\t\tcompatible = \"at24,24c32\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\n\t\t// dma@7c400000 {\n\t\t// \tcompatible = \"adi,axi-dmac-1.00.a\";\n\t\t// \treg = <0x7c400000 0x10000>;\n\t\t// \t#dma-cells = <0x1>;\n\t\t// \tinterrupts = <0x0 0x39 0x0>;\n\t\t// \tclocks = <0x2 0x10>;\n\t\t// \tlinux,phandle = <0xa>;\n\t\t// \tphandle = <0xa>;\n\n\t\t// \tadi,channels {\n\t\t// \t\t#size-cells = <0x0>;\n\t\t// \t\t#address-cells = <0x1>;\n\n\t\t// \t\tdma-channel@0 {\n\t\t// \t\t\treg = <0x0>;\n\t\t// \t\t\tadi,source-bus-width = <0x40>;\n\t\t// \t\t\tadi,source-bus-type = <0x2>;\n\t\t// \t\t\tadi,destination-bus-width = <0x40>;\n\t\t// \t\t\tadi,destination-bus-type = <0x0>;\n\t\t// \t\t};\n\t\t// \t};\n\t\t// };\n\n\t\t// dma@7c420000 {\n\t\t// \tcompatible = \"adi,axi-dmac-1.00.a\";\n\t\t// \treg = <0x7c420000 0x10000>;\n\t\t// \t#dma-cells = <0x1>;\n\t\t// \tinterrupts = <0x0 0x38 0x0>;\n\t\t// \tclocks = <0x2 0x10>;\n\t\t// \tlinux,phandle = <0xc>;\n\t\t// \tphandle = <0xc>;\n\n\t\t// \tadi,channels {\n\t\t// \t\t#size-cells = <0x0>;\n\t\t// \t\t#address-cells = <0x1>;\n\n\t\t// \t\tdma-channel@0 {\n\t\t// \t\t\treg = <0x0>;\n\t\t// \t\t\tadi,source-bus-width = <0x40>;\n\t\t// \t\t\tadi,source-bus-type = <0x0>;\n\t\t// \t\t\tadi,destination-bus-width = <0x40>;\n\t\t// \t\t\tadi,destination-bus-type = <0x2>;\n\t\t// \t\t};\n\t\t// \t};\n\t\t// };\n\n\t\tsdr: sdr {\n\t\t\tcompatible =\"sdr,sdr\";\n\t\t\tdmas = <&rx_dma 1\n\t\t\t\t\t&tx_dma 0>;\n\t\t\tdma-names = \"rx_dma_s2mm\", \"tx_dma_mm2s\";\n\t\t\tinterrupt-names = \"not_valid_anymore\", \"rx_pkt_intr\", \"tx_itrpt\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 29 1 0 30 1 0 33 1 0 34 1>;\n\t\t} ;\n\n\t\taxidmatest_1: axidmatest@1 {\n\t\t\tcompatible =\"xlnx,axi-dma-test-1.00.a\";\n\t\t\tdmas = <&rx_dma 0\n\t\t\t\t&rx_dma 1>;\n\t\t\tdma-names = \"axidma0\", \"axidma1\";\n\t\t} ;\n\n\t\ttx_dma: dma@80400000 {\n\t\t\t#dma-cells = <1>;\n\t\t\tclock-names = \"s_axi_lite_aclk\", \"m_axi_sg_aclk\", \"m_axi_mm2s_aclk\", \"m_axi_s2mm_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"xlnx,axi-dma-1.00.a\";\n\t\t\tinterrupt-names = \"mm2s_introut\", \"s2mm_introut\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 35 4 0 36 4>;\n\t\t\treg = <0x80400000 0x10000>;\n\t\t\txlnx,addrwidth = <0x20>;\n\t\t\txlnx,include-sg ;\n\t\t\txlnx,sg-length-width = <0xe>;\n\t\t\tdma-channel@80400000 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-mm2s-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 35 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x0>;\n\t\t\t};\n\t\t\tdma-channel@80400030 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-s2mm-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 36 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x0>;\n\t\t\t};\n\t\t};\n\t\t\n\t\trx_dma: dma@80410000 {\n\t\t\t#dma-cells = <1>;\n\t\t\tclock-names = \"s_axi_lite_aclk\", \"m_axi_sg_aclk\", \"m_axi_mm2s_aclk\", \"m_axi_s2mm_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"xlnx,axi-dma-1.00.a\";\n\t\t\t//dma-coherent ;\n\t\t\tinterrupt-names = \"mm2s_introut\", \"s2mm_introut\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 31 4 0 32 4>;\n\t\t\treg = <0x80410000 0x10000>;\n\t\t\txlnx,addrwidth = <0x20>;\n\t\t\txlnx,include-sg ;\n\t\t\txlnx,sg-length-width = <0xe>;\n\t\t\tdma-channel@80410000 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-mm2s-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 31 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x1>;\n\t\t\t};\n\t\t\tdma-channel@80410030 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-s2mm-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 32 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x1>;\n\t\t\t};\n\t\t};\n\n\t\ttx_intf_0: tx_intf@83c00000 {\n\t\t\tclock-names = \"s00_axi_aclk\", \"s00_axis_aclk\";//, \"s01_axis_aclk\", \"m00_axis_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"sdr,tx_intf\";\n\t\t\tinterrupt-names = \"tx_itrpt\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 34 1>;\n\t\t\treg = <0x83c00000 0x10000>;\n\t\t\txlnx,s00-axi-addr-width = <0x7>;\n\t\t\txlnx,s00-axi-data-width = <0x20>;\n\t\t};\n\n\t\trx_intf_0: rx_intf@83c20000 {\n\t\t\tclock-names = \"s00_axi_aclk\", \"m00_axis_aclk\";//, \"s00_axis_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>;\n\t\t\tcompatible = \"sdr,rx_intf\";\n\t\t\tinterrupt-names = \"not_valid_anymore\", \"rx_pkt_intr\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 29 1 0 30 1>;\n\t\t\treg = <0x83c20000 0x10000>;\n\t\t\txlnx,s00-axi-addr-width = <0x7>;\n\t\t\txlnx,s00-axi-data-width = <0x20>;\n\t\t};\n\n\t\topenofdm_tx_0: openofdm_tx@83c10000 {\n\t\t\tclock-names = \"clk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,openofdm_tx\";\n\t\t\treg = <0x83c10000 0x10000>;\n\t\t};\n\n\t\topenofdm_rx_0: openofdm_rx@83c30000 {\n\t\t\tclock-names = \"clk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,openofdm_rx\";\n\t\t\treg = <0x83c30000 0x10000>;\n\t\t};\n\n\t\txpu_0: xpu@83c40000 {\n\t\t\tclock-names = \"s00_axi_aclk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,xpu\";\n\t\t\treg = <0x83c40000 0x10000>;\n\t\t};\n\n\t\tside_ch_0: side_ch@83c50000 {\n\t\t\tclock-names = \"s00_axi_aclk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,side_ch\";\n\t\t\treg = <0x83c50000 0x10000>;\n\t\t\tdmas = <&rx_dma 0\n\t\t\t\t\t&tx_dma 1>;\n\t\t\tdma-names = \"rx_dma_mm2s\", \"tx_dma_s2mm\";\n\t\t};\n\n\t\tcf-ad9361-lpc@79020000 {\n\t\t\tcompatible = \"adi,axi-ad9361-6.00.a\";\n\t\t\treg = <0x79020000 0x6000>;\n\t\t\t// dmas = <0xa 0x0>;\n\t\t\t// dma-names = \"rx\";\n\t\t\tspibus-connected = <0xb>;\n\t\t};\n\n\t\tcf-ad9361-dds-core-lpc@79024000 {\n\t\t\tcompatible = \"adi,axi-ad9361-dds-6.00.a\";\n\t\t\treg = <0x79024000 0x1000>;\n\t\t\tclocks = <0xb 0xd>;\n\t\t\tclock-names = \"sampl_clk\";\n\t\t\t// dmas = <0xc 0x0>;\n\t\t\t// dma-names = \"tx\";\n\t\t};\n\n\t\tmwipcore@43c00000 {\n\t\t\tcompatible = \"mathworks,mwipcore-axi4lite-v1.00\";\n\t\t\treg = <0x43c00000 0xffff>;\n\t\t};\n\n\t\t/*axi-sysid-0@45000000 {\n\t\t\tcompatible = \"adi,axi-sysid-1.00.a\";\n\t\t\treg = <0x45000000 0x10000>;\n\t\t};*/\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled0 {\n\t\t\tlabel = \"led0:green\";\n\t\t\tgpios = <0x6 0xF 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tgpio_keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x0>;\n\t\tautorepeat;\n\n\t\tsw1 {\n\t\t\tlabel = \"SW1\";\n\t\t\tlinux,input-type = <0x5>;\n\t\t\tlinux,code = <0x3>;\n\t\t\tgpios = <0x6 0xE 0x0>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "kernel_boot/boards/antsdr/notes.md",
    "content": "# antsdr for openwifi-hw\n\n## Introduction\n[ANTSDR](https://github.com/MicroPhase/antsdr-fw) is a SDR hardware platform based on [xilinx zynq7020](https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html) and [adi ad936x](https://www.analog.com/en/products/ad9361.html). It could be used as a traditional SDR device such as PlutoSDR or FMCOMMS2/3/4 with Xilinx evaluation board, and it also be used as hardware platform to support openwifi.\n\n<!--\nThis README file will give the instructions about how to make the openwifi-hw project for antsdr in the [antsdr branch](https://github.com/MicroPhase/openwifi-hw/tree/antsdr) of openwifi-hw project.\n-->\n<!--\nAbove should be unnecessary, because antsdr will be in the master in the future.\n-->\n\n## Work to be done\nThe antsdr has RF switch in the front-end, for now, the RF switch is fixed at a higer range, which will isolation the frequency below 3GHz and pass the frequency at 3GHz~6GHz. \nFor future work, it can add the rf swicth control in the devicetree, and this will change the rf switch with the frequency change.\n"
  },
  {
    "path": "kernel_boot/boards/antsdr_e200/README.md",
    "content": "# ANTSDR-E200\n\nANTSDR-E200 is similar to MicroPhase ANTSDR-E310 device. \n\nANTSDR-E200 has a smaller size and some differences in hardware structure. The ethernet is placed at the PL side.\n\n![e200_struct](README.assets/e200_struct.svg)\n\nSince the performance of the zynq processor is not very strong, the Ethernet cannot run at a very high bandwidth. For some SDR applications, the Ethernet may be required to transmit baseband signals above 20MSPS sample rate. In this case, the bandwidth of the Ethernet  will reach 80MB/s. If the Ethernet on the PS side wants to run at this bandwidth, it will take up a lot of CPU resources and the bandwidth is still difficult to meet. For this reason, we moved the network port to the PL side.\n\nBut this has no effect on IIO-based SDR drivers, because we still use ZYNQ's GEM controller. O(∩_∩)O\n\nWhen we moved the ethernet to PL, the ANTSDR-E200 could support UHD driver, If anyone is interested in this, you can refer to our project [antsdr_uhd](https://github.com/MicroPhase/antsdr_uhd). \n\n"
  },
  {
    "path": "kernel_boot/boards/antsdr_e200/devicetree.dts",
    "content": "/dts-v1/;\n\n/ {\n\t#address-cells = <0x1>;\n\t#size-cells = <0x1>;\n\tcompatible = \"xlnx,zynq-7000\";\n\tinterrupt-parent = <0x1>;\n\tmodel = \"ANTSDR-E200\";\n\n\tcpus {\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0x0>;\n\t\t\tclocks = <0x2 0x3>;\n\t\t\tclock-latency = <0x3e8>;\n\t\t\tcpu0-supply = <0x3>;\n\t\t\toperating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0x1>;\n\t\t\tclocks = <0x2 0x3>;\n\t\t};\n\t};\n\n\tfpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <0x4>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tranges;\n\t};\n\n\tpmu@f8891000 {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0x0 0x5 0x4 0x0 0x6 0x4>;\n\t\tinterrupt-parent = <0x1>;\n\t\treg = <0xf8891000 0x1000 0xf8893000 0x1000>;\n\t};\n\n\tfixedregulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <0xf4240>;\n\t\tregulator-max-microvolt = <0xf4240>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t\tlinux,phandle = <0x3>;\n\t\tphandle = <0x3>;\n\t};\n\n\tamba {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tinterrupt-parent = <0x1>;\n\t\tranges;\n\n\t\tadc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0x0 0x7 0x4>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tclocks = <0x2 0xc>;\n\t\t};\n\n\t\tcan@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x13 0x2 0x24>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0x0 0x1c 0x4>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x14 0x2 0x25>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0x0 0x33 0x4>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tclocks = <0x2 0x2a>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <0x2>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x14 0x4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t\tlinux,phandle = <0x6>;\n\t\t\tphandle = <0x6>;\n\t\t};\n\n\t\ti2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x26>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x19 0x4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t};\n\n\t\ti2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x27>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x30 0x4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t};\n\n\t\tinterrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <0x3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xf8f01000 0x1000 0xf8f00100 0x100>;\n\t\t\tlinux,phandle = <0x1>;\n\t\t\tphandle = <0x1>;\n\t\t};\n\n\t\tcache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xf8f02000 0x1000>;\n\t\t\tinterrupts = <0x0 0x2 0x4>;\n\t\t\tarm,data-latency = <0x3 0x2 0x2>;\n\t\t\tarm,tag-latency = <0x2 0x2 0x2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <0x2>;\n\t\t};\n\n\t\tmemory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x3 0x4>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t};\n\n\t\tserial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"okay\";\n\t\t\tclocks = <0x2 0x17 0x2 0x28>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xe0000000 0x1000>;\n\t\t\tinterrupts = <0x0 0x1b 0x4>;\n\t\t};\n\n\t\tserial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"okay\";\n\t\t\tclocks = <0x2 0x18 0x2 0x29>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xe0001000 0x1000>;\n\t\t\tinterrupts = <0x0 0x32 0x4>;\n\t\t};\n\n\t\tspi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x1a 0x4>;\n\t\t\tclocks = <0x2 0x19 0x2 0x22>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\n\t\t\tad9361-phy@0 {\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x0>;\n\t\t\t\t#clock-cells = <0x1>;\n\t\t\t\tcompatible = \"adi,ad9361\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tspi-cpha;\n\t\t\t\tspi-max-frequency = <0x989680>;\n\t\t\t\tclocks = <0x5 0x0>;\n\t\t\t\tclock-names = \"ad9364_ext_refclk\";\n\t\t\t\tclock-output-names = \"rx_sampl_clk\", \"tx_sampl_clk\";\n\t\t\t\tadi,digital-interface-tune-skip-mode = <0x0>;\n\t\t\t\tadi,pp-tx-swap-enable;\n\t\t\t\tadi,pp-rx-swap-enable;\n\t\t\t\tadi,rx-frame-pulse-mode-enable;\n\t\t\t\tadi,lvds-mode-enable;\n\t\t\t\tadi,lvds-bias-mV = <0x96>;\n\t\t\t\tadi,lvds-rx-onchip-termination-enable;\n\t\t\t\tadi,rx-data-delay = <0x4>;\n\t\t\t\tadi,tx-fb-clock-delay = <0x7>;\n\t\t\t\tadi,xo-disable-use-ext-refclk-enable;\n\t\t\t\tadi,2rx-2tx-mode-enable;\n\t\t\t\tadi,frequency-division-duplex-mode-enable;\n\t\t\t\tadi,rx-rf-port-input-select = <0x0>;\n\t\t\t\tadi,tx-rf-port-input-select = <0x0>;\n\t\t\t\tadi,tx-attenuation-mdB = <0x2710>;\n\t\t\t\tadi,tx-lo-powerdown-managed-enable;\n\t\t\t\tadi,rf-rx-bandwidth-hz = <0x112a880>;\n\t\t\t\tadi,rf-tx-bandwidth-hz = <0x112a880>;\n\t\t\t\tadi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;\n\t\t\t\tadi,tx-synthesizer-frequency-hz = <0x0 0x92080880>;\n\t\t\t\tadi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;\n\t\t\t\tadi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;\n\t\t\t\tadi,gc-rx1-mode = <0x2>;\n\t\t\t\tadi,gc-rx2-mode = <0x2>;\n\t\t\t\tadi,gc-adc-ovr-sample-size = <0x4>;\n\t\t\t\tadi,gc-adc-small-overload-thresh = <0x2f>;\n\t\t\t\tadi,gc-adc-large-overload-thresh = <0x3a>;\n\t\t\t\tadi,gc-lmt-overload-high-thresh = <0x320>;\n\t\t\t\tadi,gc-lmt-overload-low-thresh = <0x2c0>;\n\t\t\t\tadi,gc-dec-pow-measurement-duration = <0x2000>;\n\t\t\t\tadi,gc-low-power-thresh = <0x18>;\n\t\t\t\tadi,mgc-inc-gain-step = <0x2>;\n\t\t\t\tadi,mgc-dec-gain-step = <0x2>;\n\t\t\t\tadi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;\n\t\t\t\tadi,agc-attack-delay-extra-margin-us = <0x1>;\n\t\t\t\tadi,agc-outer-thresh-high = <0x5>;\n\t\t\t\tadi,agc-outer-thresh-high-dec-steps = <0x2>;\n\t\t\t\tadi,agc-inner-thresh-high = <0xa>;\n\t\t\t\tadi,agc-inner-thresh-high-dec-steps = <0x1>;\n\t\t\t\tadi,agc-inner-thresh-low = <0xc>;\n\t\t\t\tadi,agc-inner-thresh-low-inc-steps = <0x1>;\n\t\t\t\tadi,agc-outer-thresh-low = <0x12>;\n\t\t\t\tadi,agc-outer-thresh-low-inc-steps = <0x2>;\n\t\t\t\tadi,agc-adc-small-overload-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-adc-large-overload-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-adc-large-overload-inc-steps = <0x7>;\n\t\t\t\tadi,agc-lmt-overload-large-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-lmt-overload-small-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-lmt-overload-large-inc-steps = <0x7>;\n\t\t\t\tadi,agc-gain-update-interval-us = <0x3e8>;\n\t\t\t\tadi,fagc-dec-pow-measurement-duration = <0x10>;\n        adi,fagc-adc-large-overload-inc-steps = <0x07>;\n\t\t\t\tadi,fagc-lp-thresh-increment-steps = <0x1>;\n\t\t\t\tadi,fagc-lp-thresh-increment-time = <0x5>;\n\t\t\t\tadi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;\n        adi,fagc-dig-sat-ovrg-enable;\n\t\t\t\tadi,fagc-final-overrange-count = <0x3>;\n\t\t\t\tadi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;\n\t\t\t\tadi,fagc-lmt-final-settling-steps = <0x1>;\n\t\t\t\tadi,fagc-lock-level = <0xa>;\n\t\t\t\tadi,fagc-lock-level-gain-increase-upper-limit = <0x5>;\n\t\t\t\tadi,fagc-lock-level-lmt-gain-increase-enable;\n\t\t\t\tadi,fagc-lpf-final-settling-steps = <0x1>;\n\t\t\t\tadi,fagc-optimized-gain-offset = <0x5>;\n\t\t\t\tadi,fagc-power-measurement-duration-in-state5 = <0x10>;\n\t\t\t\tadi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;\n\t\t\t\tadi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;\n\t\t\t\tadi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;\n\t\t\t\tadi,fagc-rst-gla-large-adc-overload-enable;\n\t\t\t\tadi,fagc-rst-gla-large-lmt-overload-enable;\n\t\t\t\tadi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;\n\t\t\t\tadi,fagc-state-wait-time-ns = <0x104>;\n\t\t\t\tadi,fagc-use-last-lock-level-for-set-gain-enable;\n\t\t\t\tadi,rssi-restart-mode = <0x3>;\n\t\t\t\tadi,rssi-delay = <0x1>;\n\t\t\t\tadi,rssi-wait = <0x1>;\n\t\t\t\tadi,rssi-duration = <0x3e8>;\n\t\t\t\tadi,ctrl-outs-index = <0x0>;\n\t\t\t\tadi,ctrl-outs-enable-mask = <0xff>;\n\t\t\t\tadi,temp-sense-measurement-interval-ms = <0x3e8>;\n\t\t\t\tadi,temp-sense-offset-signed = <0xce>;\n\t\t\t\tadi,temp-sense-periodic-measurement-enable;\n\t\t\t\tadi,aux-dac-manual-mode-enable;\n\t\t\t\tadi,aux-dac1-default-value-mV = <0x0>;\n\t\t\t\tadi,aux-dac1-rx-delay-us = <0x0>;\n\t\t\t\tadi,aux-dac1-tx-delay-us = <0x0>;\n\t\t\t\tadi,aux-dac2-default-value-mV = <0x0>;\n\t\t\t\tadi,aux-dac2-rx-delay-us = <0x0>;\n\t\t\t\tadi,aux-dac2-tx-delay-us = <0x0>;\n\t\t\t\ten_agc-gpios = <0x6 0x62 0x0>;\n\t\t\t\tsync-gpios = <0x6 0x63 0x0>;\n\t\t\t\treset-gpios = <0x6 0x64 0x0>;\n\t\t\t\tenable-gpios = <0x6 0x65 0x0>;\n\t\t\t\ttxnrx-gpios = <0x6 0x66 0x0>;\n\t\t\t\tlinux,phandle = <0xb>;\n\t\t\t\tphandle = <0xb>;\n\t\t\t};\n\t\t};\n\n\t\tspi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x31 0x4>;\n\t\t\tclocks = <0x2 0x1a 0x2 0x23>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t};\n\n\t\tspi@e000d000 {\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tclocks = <0x2 0xa 0x2 0x2b>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x13 0x4>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\tis-dual = <0x0>;\n\t\t\tnum-cs = <0x1>;\n\n\t\t\tps7-qspi@0 {\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t\tspi-tx-bus-width = <0x1>;\n\t\t\t\tspi-rx-bus-width = <0x4>;\n\t\t\t\tcompatible = \"n25q256a\", \"jedec,spi-nor\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tspi-max-frequency = <0x2faf080>;\n\n\t\t\t\tpartition@qspi-fsbl-uboot {\n\t\t\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\t\t\treg = <0x0 0xe0000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-uboot-env {\n\t\t\t\t\tlabel = \"qspi-uboot-env\";\n\t\t\t\t\treg = <0xe0000 0x20000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-linux {\n\t\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\t\treg = <0x100000 0x500000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-device-tree {\n\t\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\t\treg = <0x600000 0x20000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-rootfs {\n\t\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\t\treg = <0x620000 0xce0000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-bitstream {\n\t\t\t\t\tlabel = \"qspi-bitstream\";\n\t\t\t\t\treg = <0x1300000 0xd00000>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tmemory-controller@e000e000 {\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x1>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"aclk\";\n\t\t\tclocks = <0x2 0xb 0x2 0x2c>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x12 0x4>;\n\t\t\tranges;\n\t\t\treg = <0xe000e000 0x1000>;\n\n\t\t\tflash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\n\t\t\tflash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x2000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\t\t};\n\n\t\tethernet@e000b000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupts = <0x0 0x16 0x4>;\n\t\t\tclocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\tphy-handle = <&phy0>;\n\t\t\tphy-mode = \"rgmii-id\";\n\t\t\txlnx,has-mdio = <0x1>;\n\t\t\tgmii2rgmii-phy-handle = <&gmii_to_rgmii_0>;\n\n\t\t\tphy0: phy@1 {\n\t\t\t\tcompatible = \"ethernet-phy-id011c.c916\";\n\t\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\t\treg = <0x1>;\n\t\t\t};\n\n\t\t\tgmii_to_rgmii_0:  gmiitorgmii@8 {\n\t\t\t\tcompatible = \"xlnx,gmii-to-rgmii-1.0\";\n\t\t\t\treg = <0x8>;\n\t\t\t\tphy-handle = <&phy0>;\n\t\t\t};\n\t\t};\n\n\t\tethernet@e000c000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0x0 0x2d 0x4>;\n\t\t\tclocks = <0x2 0x1f 0x2 0x1f 0x2 0xe>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t};\n\n\t\tmmc@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <0x2 0x15 0x2 0x20>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x18 0x4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t\tdisable-wp;\n\t\t};\n\n\t\tmmc@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <0x2 0x16 0x2 0x21>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x2f 0x4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t};\n\n\t\tslcr@f8000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\", \"simple-mfd\";\n\t\t\treg = <0xf8000000 0x1000>;\n\t\t\tranges;\n\t\t\tlinux,phandle = <0x8>;\n\t\t\tphandle = <0x8>;\n\n\t\t\tclkc@100 {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <0x1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\", \"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\", \"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\", \"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\", \"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\", \"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\", \"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\", \"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\", \"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\", \"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t\tps-clk-frequency = <0x1fca055>;\n\t\t\t\tlinux,phandle = <0x2>;\n\t\t\t\tphandle = <0x2>;\n\t\t\t};\n\n\t\t\trstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <0x1>;\n\t\t\t\tsyscon = <0x8>;\n\t\t\t};\n\n\t\t\tpinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <0x8>;\n\t\t\t};\n\t\t};\n\n\t\tdmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\", \"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\tinterrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>;\n\t\t\t#dma-cells = <0x1>;\n\t\t\t#dma-channels = <0x8>;\n\t\t\t#dma-requests = <0x4>;\n\t\t\tclocks = <0x2 0x1b>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t};\n\n\t\tdevcfg@f8007000 {\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x8 0x4>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tclocks = <0x2 0xc 0x2 0xf 0x2 0x10 0x2 0x11 0x2 0x12>;\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tsyscon = <0x8>;\n\t\t\tlinux,phandle = <0x4>;\n\t\t\tphandle = <0x4>;\n\t\t};\n\n\t\tefuse@f800d000 {\n\t\t\tcompatible = \"xlnx,zynq-efuse\";\n\t\t\treg = <0xf800d000 0x20>;\n\t\t};\n\n\t\ttimer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <0x1 0xb 0x301>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tclocks = <0x2 0x4>;\n\t\t};\n\n\t\ttimer@f8001000 {\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <0x2 0x6>;\n\t\t\treg = <0xf8001000 0x1000>;\n\t\t};\n\n\t\ttimer@f8002000 {\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <0x2 0x6>;\n\t\t\treg = <0xf8002000 0x1000>;\n\t\t};\n\n\t\ttimer@f8f00600 {\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x1 0xd 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <0x2 0x4>;\n\t\t};\n\n\t\tusb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x1c>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x15 0x4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t\tdr_mode = \"host\";\n\t\t\txlnx,phy-reset-gpio = <0x6 0x7 0x0>;\n\t\t};\n\n\t\tusb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x1d>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x2c 0x4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog@f8005000 {\n\t\t\tclocks = <0x2 0x2d>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x9 0x1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <0xa>;\n\t\t};\n\t};\n\n\taliases {\n\t\tethernet0 = \"/amba/ethernet@e000b000\";\n\t\tserial0 = \"/amba/serial@e0000000\";\n\t};\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x20000000>;\n\t};\n\n\tchosen {\n\t\tlinux,stdout-path = \"/amba@0/uart@E0000000\";\n\t};\n\n\tclocks {\n\n\t\tclock@0 {\n\t\t\t#clock-cells = <0x0>;\n\t\t\tcompatible = \"adjustable-clock\";\n\t\t\tclock-frequency = <0x2625a00>;\n\t\t\tclock-accuracy = <0x30d40>;\n\t\t\tclock-output-names = \"ad9364_ext_refclk\";\n\t\t\tlinux,phandle = <0x5>;\n\t\t\tphandle = <0x5>;\n\t\t};\n\n\t\tclock@1 {\n\t\t\t#clock-cells = <0x0>;\n\t\t\tcompatible = \"fixed-clock\";\n\t\t\tclock-frequency = <0x16e3600>;\n\t\t\tclock-output-names = \"24MHz\";\n\t\t\tlinux,phandle = <0x9>;\n\t\t\tphandle = <0x9>;\n\t\t};\n\t};\n\n\tusb-ulpi-gpio-gate@0 {\n\t\tcompatible = \"gpio-gate-clock\";\n\t\tclocks = <0x9>;\n\t\t#clock-cells = <0x0>;\n\t\tenable-gpios = <0x6 0x9 0x1>;\n\t};\n\n\tfpga-axi@0 {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tranges;\n\n\t\ti2c@41600000 {\n\t\t\tcompatible = \"xlnx,axi-iic-1.02.a\", \"xlnx,xps-iic-2.00.a\";\n\t\t\treg = <0x41600000 0x10000>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x3a 0x4>;\n\t\t\tclocks = <0x2 0xf>;\n\t\t\tclock-names = \"pclk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\n\t\t\tad7291@20 {\n\t\t\t\tcompatible = \"adi,ad7291\";\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tad7291-bob@2C {\n\t\t\t\tcompatible = \"adi,ad7291\";\n\t\t\t\treg = <0x2c>;\n\t\t\t};\n\n\t\t\teeprom@50 {\n\t\t\t\tcompatible = \"at24,24c32\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\n\t\t// dma@7c400000 {\n\t\t// \tcompatible = \"adi,axi-dmac-1.00.a\";\n\t\t// \treg = <0x7c400000 0x10000>;\n\t\t// \t#dma-cells = <0x1>;\n\t\t// \tinterrupts = <0x0 0x39 0x0>;\n\t\t// \tclocks = <0x2 0x10>;\n\t\t// \tlinux,phandle = <0xa>;\n\t\t// \tphandle = <0xa>;\n\n\t\t// \tadi,channels {\n\t\t// \t\t#size-cells = <0x0>;\n\t\t// \t\t#address-cells = <0x1>;\n\n\t\t// \t\tdma-channel@0 {\n\t\t// \t\t\treg = <0x0>;\n\t\t// \t\t\tadi,source-bus-width = <0x40>;\n\t\t// \t\t\tadi,source-bus-type = <0x2>;\n\t\t// \t\t\tadi,destination-bus-width = <0x40>;\n\t\t// \t\t\tadi,destination-bus-type = <0x0>;\n\t\t// \t\t};\n\t\t// \t};\n\t\t// };\n\n\t\t// dma@7c420000 {\n\t\t// \tcompatible = \"adi,axi-dmac-1.00.a\";\n\t\t// \treg = <0x7c420000 0x10000>;\n\t\t// \t#dma-cells = <0x1>;\n\t\t// \tinterrupts = <0x0 0x38 0x0>;\n\t\t// \tclocks = <0x2 0x10>;\n\t\t// \tlinux,phandle = <0xc>;\n\t\t// \tphandle = <0xc>;\n\n\t\t// \tadi,channels {\n\t\t// \t\t#size-cells = <0x0>;\n\t\t// \t\t#address-cells = <0x1>;\n\n\t\t// \t\tdma-channel@0 {\n\t\t// \t\t\treg = <0x0>;\n\t\t// \t\t\tadi,source-bus-width = <0x40>;\n\t\t// \t\t\tadi,source-bus-type = <0x0>;\n\t\t// \t\t\tadi,destination-bus-width = <0x40>;\n\t\t// \t\t\tadi,destination-bus-type = <0x2>;\n\t\t// \t\t};\n\t\t// \t};\n\t\t// };\n\n\t\tsdr: sdr {\n\t\t\tcompatible =\"sdr,sdr\";\n\t\t\tdmas = <&rx_dma 1\n\t\t\t\t\t&tx_dma 0>;\n\t\t\tdma-names = \"rx_dma_s2mm\", \"tx_dma_mm2s\";\n\t\t\tinterrupt-names = \"not_valid_anymore\", \"rx_pkt_intr\", \"tx_itrpt\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 29 1 0 30 1 0 33 1 0 34 1>;\n\t\t} ;\n\n\t\taxidmatest_1: axidmatest@1 {\n\t\t\tcompatible =\"xlnx,axi-dma-test-1.00.a\";\n\t\t\tdmas = <&rx_dma 0\n\t\t\t\t&rx_dma 1>;\n\t\t\tdma-names = \"axidma0\", \"axidma1\";\n\t\t} ;\n\n\t\ttx_dma: dma@80400000 {\n\t\t\t#dma-cells = <1>;\n\t\t\tclock-names = \"s_axi_lite_aclk\", \"m_axi_sg_aclk\", \"m_axi_mm2s_aclk\", \"m_axi_s2mm_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"xlnx,axi-dma-1.00.a\";\n\t\t\tinterrupt-names = \"mm2s_introut\", \"s2mm_introut\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 35 4 0 36 4>;\n\t\t\treg = <0x80400000 0x10000>;\n\t\t\txlnx,addrwidth = <0x20>;\n\t\t\txlnx,include-sg ;\n\t\t\txlnx,sg-length-width = <0xe>;\n\t\t\tdma-channel@80400000 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-mm2s-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 35 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x0>;\n\t\t\t};\n\t\t\tdma-channel@80400030 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-s2mm-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 36 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x0>;\n\t\t\t};\n\t\t};\n\t\t\n\t\trx_dma: dma@80410000 {\n\t\t\t#dma-cells = <1>;\n\t\t\tclock-names = \"s_axi_lite_aclk\", \"m_axi_sg_aclk\", \"m_axi_mm2s_aclk\", \"m_axi_s2mm_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"xlnx,axi-dma-1.00.a\";\n\t\t\t//dma-coherent ;\n\t\t\tinterrupt-names = \"mm2s_introut\", \"s2mm_introut\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 31 4 0 32 4>;\n\t\t\treg = <0x80410000 0x10000>;\n\t\t\txlnx,addrwidth = <0x20>;\n\t\t\txlnx,include-sg ;\n\t\t\txlnx,sg-length-width = <0xe>;\n\t\t\tdma-channel@80410000 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-mm2s-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 31 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x1>;\n\t\t\t};\n\t\t\tdma-channel@80410030 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-s2mm-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 32 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x1>;\n\t\t\t};\n\t\t};\n\n\t\ttx_intf_0: tx_intf@83c00000 {\n\t\t\tclock-names = \"s00_axi_aclk\", \"s00_axis_aclk\";//, \"s01_axis_aclk\", \"m00_axis_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"sdr,tx_intf\";\n\t\t\tinterrupt-names = \"tx_itrpt\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 34 1>;\n\t\t\treg = <0x83c00000 0x10000>;\n\t\t\txlnx,s00-axi-addr-width = <0x7>;\n\t\t\txlnx,s00-axi-data-width = <0x20>;\n\t\t};\n\n\t\trx_intf_0: rx_intf@83c20000 {\n\t\t\tclock-names = \"s00_axi_aclk\", \"m00_axis_aclk\";//, \"s00_axis_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>;\n\t\t\tcompatible = \"sdr,rx_intf\";\n\t\t\tinterrupt-names = \"not_valid_anymore\", \"rx_pkt_intr\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 29 1 0 30 1>;\n\t\t\treg = <0x83c20000 0x10000>;\n\t\t\txlnx,s00-axi-addr-width = <0x7>;\n\t\t\txlnx,s00-axi-data-width = <0x20>;\n\t\t};\n\n\t\topenofdm_tx_0: openofdm_tx@83c10000 {\n\t\t\tclock-names = \"clk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,openofdm_tx\";\n\t\t\treg = <0x83c10000 0x10000>;\n\t\t};\n\n\t\topenofdm_rx_0: openofdm_rx@83c30000 {\n\t\t\tclock-names = \"clk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,openofdm_rx\";\n\t\t\treg = <0x83c30000 0x10000>;\n\t\t};\n\n\t\txpu_0: xpu@83c40000 {\n\t\t\tclock-names = \"s00_axi_aclk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,xpu\";\n\t\t\treg = <0x83c40000 0x10000>;\n\t\t};\n\n\t\tside_ch_0: side_ch@83c50000 {\n\t\t\tclock-names = \"s00_axi_aclk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,side_ch\";\n\t\t\treg = <0x83c50000 0x10000>;\n\t\t\tdmas = <&rx_dma 0\n\t\t\t\t\t&tx_dma 1>;\n\t\t\tdma-names = \"rx_dma_mm2s\", \"tx_dma_s2mm\";\n\t\t};\n\n\t\tcf-ad9361-lpc@79020000 {\n\t\t\tcompatible = \"adi,axi-ad9361-6.00.a\";\n\t\t\treg = <0x79020000 0x6000>;\n\t\t\t// dmas = <0xa 0x0>;\n\t\t\t// dma-names = \"rx\";\n\t\t\tspibus-connected = <0xb>;\n\t\t};\n\n\t\tcf-ad9361-dds-core-lpc@79024000 {\n\t\t\tcompatible = \"adi,axi-ad9361-dds-6.00.a\";\n\t\t\treg = <0x79024000 0x1000>;\n\t\t\tclocks = <0xb 0xd>;\n\t\t\tclock-names = \"sampl_clk\";\n\t\t\t// dmas = <0xc 0x0>;\n\t\t\t// dma-names = \"tx\";\n\t\t};\n\n\t\tmwipcore@43c00000 {\n\t\t\tcompatible = \"mathworks,mwipcore-axi4lite-v1.00\";\n\t\t\treg = <0x43c00000 0xffff>;\n\t\t};\n\n\t\t/*axi-sysid-0@45000000 {\n\t\t\tcompatible = \"adi,axi-sysid-1.00.a\";\n\t\t\treg = <0x45000000 0x10000>;\n\t\t};*/\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled0 {\n\t\t\tlabel = \"led0:green\";\n\t\t\tgpios = <0x6 0x0 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n};\n"
  },
  {
    "path": "kernel_boot/boards/e310v2/README.md",
    "content": "# ANTSDR-E310V2\n\n**AntSDR E310V2** is a powerful and versatile  software-defined radio (SDR) platform. It is a low-cost, easy-to-use  system for developing, testing, and deploying wireless communication  solutions such as LTE, GSM, and Wi-Fi. With its wide range of supported  frequencies and modulation schemes, it’s possible to easily experiment  with various wireless technologies.\n\n![struct](README.assets/struct.png)\n\nBased on the  original version, we have optimized the RF performance, added a GPS  module, increased an external 10M/PPS input interface, and used a VCXO.  The combination of VCXO and external reference input with DAC can  generate a more accurate and stable clock. In addition, the Ethernet on  the PL makes it possible for E310V2 to be compatible with UHD for higher bandwidth transmission.\n\n If you are interested in using UHD with E310V2, you can find more information in our [repository](https://github.com/MicroPhase/antsdr_uhd).\n\n"
  },
  {
    "path": "kernel_boot/boards/e310v2/devicetree.dts",
    "content": "/dts-v1/;\n\n/ {\n\t#address-cells = <0x01>;\n\t#size-cells = <0x01>;\n\tcompatible = \"xlnx,zynq-7000\";\n\tinterrupt-parent = <0x01>;\n\tmodel = \"ANTSDR-E310V2\";\n\n\tcpus {\n\t\t#address-cells = <0x01>;\n\t\t#size-cells = <0x00>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0x00>;\n\t\t\tclocks = <0x02 0x03>;\n\t\t\tclock-latency = <0x3e8>;\n\t\t\tcpu0-supply = <0x03>;\n\t\t\toperating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>;\n\t\t\tphandle = <0x11>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0x01>;\n\t\t\tclocks = <0x02 0x03>;\n\t\t\tphandle = <0x13>;\n\t\t};\n\t};\n\n\tfpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <0x04>;\n\t\t#address-cells = <0x01>;\n\t\t#size-cells = <0x01>;\n\t\tranges;\n\t\tphandle = <0x19>;\n\t};\n\n\tpmu@f8891000 {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0x00 0x05 0x04 0x00 0x06 0x04>;\n\t\tinterrupt-parent = <0x01>;\n\t\treg = <0xf8891000 0x1000 0xf8893000 0x1000>;\n\t};\n\n\tfixedregulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <0xf4240>;\n\t\tregulator-max-microvolt = <0xf4240>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t\tphandle = <0x03>;\n\t};\n\n\treplicator {\n\t\tcompatible = \"arm,coresight-static-replicator\";\n\t\tclocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;\n\t\tclock-names = \"apb_pclk\\0dbg_trc\\0dbg_apb\";\n\n\t\tout-ports {\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\n\t\t\tport@0 {\n\t\t\t\treg = <0x00>;\n\n\t\t\t\tendpoint {\n\t\t\t\t\tremote-endpoint = <0x05>;\n\t\t\t\t\tphandle = <0x0d>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tport@1 {\n\t\t\t\treg = <0x01>;\n\n\t\t\t\tendpoint {\n\t\t\t\t\tremote-endpoint = <0x06>;\n\t\t\t\t\tphandle = <0x0c>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tin-ports {\n\n\t\t\tport {\n\n\t\t\t\tendpoint {\n\t\t\t\t\tremote-endpoint = <0x07>;\n\t\t\t\t\tphandle = <0x0e>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\taxi {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x01>;\n\t\t#size-cells = <0x01>;\n\t\tinterrupt-parent = <0x01>;\n\t\tranges;\n\t\tphandle = <0x1a>;\n\n\t\tadc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0x00 0x07 0x04>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tclocks = <0x02 0x0c>;\n\t\t\tphandle = <0x1b>;\n\t\t};\n\n\t\tcan@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x02 0x13 0x02 0x24>;\n\t\t\tclock-names = \"can_clk\\0pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0x00 0x1c 0x04>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tphandle = <0x1c>;\n\t\t};\n\n\t\tcan@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x02 0x14 0x02 0x25>;\n\t\t\tclock-names = \"can_clk\\0pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0x00 0x33 0x04>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tphandle = <0x1d>;\n\t\t};\n\n\t\tgpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <0x02>;\n\t\t\tclocks = <0x02 0x2a>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <0x02>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x14 0x04>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t\tphandle = <0x09>;\n\t\t};\n\n\t\ti2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x02 0x26>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x19 0x04>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tphandle = <0x1e>;\n\t\t};\n\n\t\ti2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x02 0x27>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x30 0x04>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tphandle = <0x1f>;\n\t\t};\n\n\t\tinterrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <0x03>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xf8f01000 0x1000 0xf8f00100 0x100>;\n\t\t\tphandle = <0x01>;\n\t\t};\n\n\t\tcache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xf8f02000 0x1000>;\n\t\t\tinterrupts = <0x00 0x02 0x04>;\n\t\t\tarm,data-latency = <0x03 0x02 0x02>;\n\t\t\tarm,tag-latency = <0x02 0x02 0x02>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <0x02>;\n\t\t\tphandle = <0x20>;\n\t\t};\n\n\t\tmemory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t\tphandle = <0x21>;\n\t\t};\n\n\t\tocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x03 0x04>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t\tphandle = <0x22>;\n\t\t};\n\n\t\tserial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\\0cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x02 0x17 0x02 0x28>;\n\t\t\tclock-names = \"uart_clk\\0pclk\";\n\t\t\treg = <0xe0000000 0x1000>;\n\t\t\tinterrupts = <0x00 0x1b 0x04>;\n\t\t\tphandle = <0x23>;\n\t\t};\n\n\t\tserial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\\0cdns,uart-r1p8\";\n\t\t\tstatus = \"okay\";\n\t\t\tclocks = <0x02 0x18 0x02 0x29>;\n\t\t\tclock-names = \"uart_clk\\0pclk\";\n\t\t\treg = <0xe0001000 0x1000>;\n\t\t\tinterrupts = <0x00 0x32 0x04>;\n\t\t\tphandle = <0x24>;\n\t\t};\n\n\t\tspi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x1a 0x04>;\n\t\t\tclocks = <0x02 0x19 0x02 0x22>;\n\t\t\tclock-names = \"ref_clk\\0pclk\";\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tphandle = <0x25>;\n\n\t\t\tad9361-phy@0 {\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x0>;\n\t\t\t\t#clock-cells = <0x1>;\n\t\t\t\tcompatible = \"adi,ad9361\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tspi-cpha;\n\t\t\t\tspi-max-frequency = <0x989680>;\n\t\t\t\tclocks = <0x08 0x00>;\n\t\t\t\tclock-names = \"ad9361_ext_refclk\";\n\t\t\t\tclock-output-names = \"rx_sampl_clk\", \"tx_sampl_clk\";\n\t\t\t\tadi,digital-interface-tune-skip-mode = <0x0>;\n\t\t\t\tadi,pp-tx-swap-enable;\n\t\t\t\tadi,pp-rx-swap-enable;\n\t\t\t\tadi,rx-frame-pulse-mode-enable;\n\t\t\t\tadi,lvds-mode-enable;\n\t\t\t\tadi,lvds-bias-mV = <0x96>;\n\t\t\t\tadi,lvds-rx-onchip-termination-enable;\n\t\t\t\tadi,rx-data-delay = <0x4>;\n\t\t\t\tadi,tx-fb-clock-delay = <0x7>;\n\t\t\t\tadi,xo-disable-use-ext-refclk-enable;\n\t\t\t\tadi,2rx-2tx-mode-enable;\n\t\t\t\tadi,frequency-division-duplex-mode-enable;\n\t\t\t\tadi,rx-rf-port-input-select = <0x0>;\n\t\t\t\tadi,tx-rf-port-input-select = <0x0>;\n\t\t\t\tadi,tx-attenuation-mdB = <0x2710>;\n\t\t\t\tadi,tx-lo-powerdown-managed-enable;\n\t\t\t\tadi,rf-rx-bandwidth-hz = <0x112a880>;\n\t\t\t\tadi,rf-tx-bandwidth-hz = <0x112a880>;\n\t\t\t\tadi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;\n\t\t\t\tadi,tx-synthesizer-frequency-hz = <0x0 0x92080880>;\n\t\t\t\tadi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;\n\t\t\t\tadi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;\n\t\t\t\tadi,gc-rx1-mode = <0x2>;\n\t\t\t\tadi,gc-rx2-mode = <0x2>;\n\t\t\t\tadi,gc-adc-ovr-sample-size = <0x4>;\n\t\t\t\tadi,gc-adc-small-overload-thresh = <0x2f>;\n\t\t\t\tadi,gc-adc-large-overload-thresh = <0x3a>;\n\t\t\t\tadi,gc-lmt-overload-high-thresh = <0x320>;\n\t\t\t\tadi,gc-lmt-overload-low-thresh = <0x2c0>;\n\t\t\t\tadi,gc-dec-pow-measurement-duration = <0x2000>;\n\t\t\t\tadi,gc-low-power-thresh = <0x18>;\n\t\t\t\tadi,mgc-inc-gain-step = <0x2>;\n\t\t\t\tadi,mgc-dec-gain-step = <0x2>;\n\t\t\t\tadi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;\n\t\t\t\tadi,agc-attack-delay-extra-margin-us = <0x1>;\n\t\t\t\tadi,agc-outer-thresh-high = <0x5>;\n\t\t\t\tadi,agc-outer-thresh-high-dec-steps = <0x2>;\n\t\t\t\tadi,agc-inner-thresh-high = <0xa>;\n\t\t\t\tadi,agc-inner-thresh-high-dec-steps = <0x1>;\n\t\t\t\tadi,agc-inner-thresh-low = <0xc>;\n\t\t\t\tadi,agc-inner-thresh-low-inc-steps = <0x1>;\n\t\t\t\tadi,agc-outer-thresh-low = <0x12>;\n\t\t\t\tadi,agc-outer-thresh-low-inc-steps = <0x2>;\n\t\t\t\tadi,agc-adc-small-overload-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-adc-large-overload-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-adc-large-overload-inc-steps = <0x7>;\n\t\t\t\tadi,agc-lmt-overload-large-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-lmt-overload-small-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-lmt-overload-large-inc-steps = <0x7>;\n\t\t\t\tadi,agc-gain-update-interval-us = <0x3e8>;\n\t\t\t\tadi,fagc-dec-pow-measurement-duration = <0x10>;\n        adi,fagc-adc-large-overload-inc-steps = <0x07>;\n\t\t\t\tadi,fagc-lp-thresh-increment-steps = <0x1>;\n\t\t\t\tadi,fagc-lp-thresh-increment-time = <0x5>;\n\t\t\t\tadi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;\n        adi,fagc-dig-sat-ovrg-enable;\n\t\t\t\tadi,fagc-final-overrange-count = <0x3>;\n\t\t\t\tadi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;\n\t\t\t\tadi,fagc-lmt-final-settling-steps = <0x1>;\n\t\t\t\tadi,fagc-lock-level = <0xa>;\n\t\t\t\tadi,fagc-lock-level-gain-increase-upper-limit = <0x5>;\n\t\t\t\tadi,fagc-lock-level-lmt-gain-increase-enable;\n\t\t\t\tadi,fagc-lpf-final-settling-steps = <0x1>;\n\t\t\t\tadi,fagc-optimized-gain-offset = <0x5>;\n\t\t\t\tadi,fagc-power-measurement-duration-in-state5 = <0x10>;\n\t\t\t\tadi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;\n\t\t\t\tadi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;\n\t\t\t\tadi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;\n\t\t\t\tadi,fagc-rst-gla-large-adc-overload-enable;\n\t\t\t\tadi,fagc-rst-gla-large-lmt-overload-enable;\n\t\t\t\tadi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;\n\t\t\t\tadi,fagc-state-wait-time-ns = <0x104>;\n\t\t\t\tadi,fagc-use-last-lock-level-for-set-gain-enable;\n\t\t\t\tadi,rssi-restart-mode = <0x3>;\n\t\t\t\tadi,rssi-delay = <0x1>;\n\t\t\t\tadi,rssi-wait = <0x1>;\n\t\t\t\tadi,rssi-duration = <0x3e8>;\n\t\t\t\tadi,ctrl-outs-index = <0x0>;\n\t\t\t\tadi,ctrl-outs-enable-mask = <0xff>;\n\t\t\t\tadi,temp-sense-measurement-interval-ms = <0x3e8>;\n\t\t\t\tadi,temp-sense-offset-signed = <0xce>;\n\t\t\t\tadi,temp-sense-periodic-measurement-enable;\n\t\t\t\tadi,aux-dac-manual-mode-enable;\n\t\t\t\tadi,aux-dac1-default-value-mV = <0x0>;\n\t\t\t\tadi,aux-dac1-rx-delay-us = <0x0>;\n\t\t\t\tadi,aux-dac1-tx-delay-us = <0x0>;\n\t\t\t\tadi,aux-dac2-default-value-mV = <0x0>;\n\t\t\t\tadi,aux-dac2-rx-delay-us = <0x0>;\n\t\t\t\tadi,aux-dac2-tx-delay-us = <0x0>;\n\t\t\t\ten_agc-gpios = <0x09 0x62 0x0>;\n\t\t\t\tsync-gpios = <0x09 0x63 0x0>;\n\t\t\t\treset-gpios = <0x09 0x64 0x0>;\n\t\t\t\tenable-gpios = <0x09 0x65 0x0>;\n\t\t\t\ttxnrx-gpios = <0x09 0x66 0x0>;\n\t\t\t\tphandle = <0x17>;\n\t\t\t};\n\t\t};\n\n\t\tspi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x31 0x04>;\n\t\t\tclocks = <0x02 0x1a 0x02 0x23>;\n\t\t\tclock-names = \"ref_clk\\0pclk\";\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tphandle = <0x26>;\n\t\t};\n\n\t\tspi@e000d000 {\n\t\t\tclock-names = \"ref_clk\\0pclk\";\n\t\t\tclocks = <0x02 0x0a 0x02 0x2b>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x13 0x04>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tis-dual = <0x00>;\n\t\t\tnum-cs = <0x01>;\n\t\t\tphandle = <0x27>;\n\n\t\t\tps7-qspi@0 {\n\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t#size-cells = <0x01>;\n\t\t\t\tspi-tx-bus-width = <0x01>;\n\t\t\t\tspi-rx-bus-width = <0x04>;\n\t\t\t\tcompatible = \"n25q256a\\0jedec,spi-nor\";\n\t\t\t\treg = <0x00>;\n\t\t\t\tspi-max-frequency = <0x2faf080>;\n\t\t\t\tphandle = <0x28>;\n\n\t\t\t\tpartition@qspi-fsbl-uboot {\n\t\t\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\t\t\treg = <0x00 0xe0000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-uboot-env {\n\t\t\t\t\tlabel = \"qspi-uboot-env\";\n\t\t\t\t\treg = <0xe0000 0x20000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-linux {\n\t\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\t\treg = <0x100000 0x500000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-device-tree {\n\t\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\t\treg = <0x600000 0x20000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-rootfs {\n\t\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\t\treg = <0x620000 0xce0000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-bitstream {\n\t\t\t\t\tlabel = \"qspi-bitstream\";\n\t\t\t\t\treg = <0x1300000 0xd00000>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tmemory-controller@e000e000 {\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x01>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\\0apb_pclk\";\n\t\t\tclocks = <0x02 0x0b 0x02 0x2c>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\\0arm,primecell\";\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x12 0x04>;\n\t\t\tranges;\n\t\t\treg = <0xe000e000 0x1000>;\n\t\t\tphandle = <0x29>;\n\n\t\t\tflash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t#size-cells = <0x01>;\n\t\t\t\tphandle = <0x2a>;\n\t\t\t};\n\n\t\t\tflash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x2000000>;\n\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t#size-cells = <0x01>;\n\t\t\t\tphandle = <0x2b>;\n\t\t\t};\n\t\t};\n\n\t\tethernet@e000b000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupts = <0x0 0x16 0x4>;\n\t\t\tclocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\tphy-handle = <&phy0>;\n\t\t\tphy-mode = \"rgmii-id\";\n\t\t\txlnx,has-mdio = <0x1>;\n\t\t\tgmii2rgmii-phy-handle = <&gmii_to_rgmii_0>;\n\n\t\t\tphy0: phy@1 {\n\t\t\t\tcompatible = \"ethernet-phy-id011c.c916\";\n\t\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\t\treg = <0x1>;\n\t\t\t};\n\n\t\t\tgmii_to_rgmii_0:  gmiitorgmii@8 {\n\t\t\t\tcompatible = \"xlnx,gmii-to-rgmii-1.0\";\n\t\t\t\treg = <0x8>;\n\t\t\t\tphy-handle = <&phy0>;\n\t\t\t};\n\t\t};\n\n\t\tethernet@e000c000 {\n\t\t\tcompatible = \"cdns,zynq-gem\\0cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0x00 0x2d 0x04>;\n\t\t\tclocks = <0x02 0x1f 0x02 0x1f 0x02 0x0e>;\n\t\t\tclock-names = \"pclk\\0hclk\\0tx_clk\";\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tphandle = <0x2d>;\n\t\t};\n\n\t\tmmc@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"clk_xin\\0clk_ahb\";\n\t\t\tclocks = <0x02 0x15 0x02 0x20>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x18 0x04>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t\tdisable-wp;\n\t\t\tphandle = <0x2e>;\n\t\t};\n\n\t\tmmc@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\\0clk_ahb\";\n\t\t\tclocks = <0x02 0x16 0x02 0x21>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x2f 0x04>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t\tphandle = <0x2f>;\n\t\t};\n\n\t\tslcr@f8000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x01>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\\0syscon\\0simple-mfd\";\n\t\t\treg = <0xf8000000 0x1000>;\n\t\t\tranges;\n\t\t\tphandle = <0x0b>;\n\n\t\t\tclkc@100 {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <0x01>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0x0f>;\n\t\t\t\tclock-output-names = \"armpll\\0ddrpll\\0iopll\\0cpu_6or4x\\0cpu_3or2x\\0cpu_2x\\0cpu_1x\\0ddr2x\\0ddr3x\\0dci\\0lqspi\\0smc\\0pcap\\0gem0\\0gem1\\0fclk0\\0fclk1\\0fclk2\\0fclk3\\0can0\\0can1\\0sdio0\\0sdio1\\0uart0\\0uart1\\0spi0\\0spi1\\0dma\\0usb0_aper\\0usb1_aper\\0gem0_aper\\0gem1_aper\\0sdio0_aper\\0sdio1_aper\\0spi0_aper\\0spi1_aper\\0can0_aper\\0can1_aper\\0i2c0_aper\\0i2c1_aper\\0uart0_aper\\0uart1_aper\\0gpio_aper\\0lqspi_aper\\0smc_aper\\0swdt\\0dbg_trc\\0dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t\tps-clk-frequency = <0x1fca055>;\n\t\t\t\tphandle = <0x02>;\n\t\t\t};\n\n\t\t\trstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <0x01>;\n\t\t\t\tsyscon = <0x0b>;\n\t\t\t\tphandle = <0x30>;\n\t\t\t};\n\n\t\t\tpinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <0x0b>;\n\t\t\t\tphandle = <0x31>;\n\t\t\t};\n\t\t};\n\n\t\tdmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\\0arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupt-names = \"abort\\0dma0\\0dma1\\0dma2\\0dma3\\0dma4\\0dma5\\0dma6\\0dma7\";\n\t\t\tinterrupts = <0x00 0x0d 0x04 0x00 0x0e 0x04 0x00 0x0f 0x04 0x00 0x10 0x04 0x00 0x11 0x04 0x00 0x28 0x04 0x00 0x29 0x04 0x00 0x2a 0x04 0x00 0x2b 0x04>;\n\t\t\t#dma-cells = <0x01>;\n\t\t\t#dma-channels = <0x08>;\n\t\t\t#dma-requests = <0x04>;\n\t\t\tclocks = <0x02 0x1b>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t\tphandle = <0x32>;\n\t\t};\n\n\t\tdevcfg@f8007000 {\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x08 0x04>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tclocks = <0x02 0x0c 0x02 0x0f 0x02 0x10 0x02 0x11 0x02 0x12>;\n\t\t\tclock-names = \"ref_clk\\0fclk0\\0fclk1\\0fclk2\\0fclk3\";\n\t\t\tsyscon = <0x0b>;\n\t\t\tphandle = <0x04>;\n\t\t};\n\n\t\tefuse@f800d000 {\n\t\t\tcompatible = \"xlnx,zynq-efuse\";\n\t\t\treg = <0xf800d000 0x20>;\n\t\t\tphandle = <0x33>;\n\t\t};\n\n\t\ttimer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <0x01 0x0b 0x301>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tclocks = <0x02 0x04>;\n\t\t\tphandle = <0x34>;\n\t\t};\n\n\t\ttimer@f8001000 {\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x0a 0x04 0x00 0x0b 0x04 0x00 0x0c 0x04>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <0x02 0x06>;\n\t\t\treg = <0xf8001000 0x1000>;\n\t\t\tphandle = <0x35>;\n\t\t};\n\n\t\ttimer@f8002000 {\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x25 0x04 0x00 0x26 0x04 0x00 0x27 0x04>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <0x02 0x06>;\n\t\t\treg = <0xf8002000 0x1000>;\n\t\t\tphandle = <0x36>;\n\t\t};\n\n\t\ttimer@f8f00600 {\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x01 0x0d 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <0x02 0x04>;\n\t\t\tphandle = <0x37>;\n\t\t};\n\n\t\tusb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\\0chipidea,usb2\";\n\t\t\tstatus = \"okay\";\n\t\t\tclocks = <0x02 0x1c>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x15 0x04>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t\tdr_mode = \"host\";\n\t\t\txlnx,phy-reset-gpio = <0x09 0x07 0x00>;\n\t\t\tphandle = <0x38>;\n\t\t};\n\n\t\tusb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\\0chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x02 0x1d>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x2c 0x04>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t\tphandle = <0x39>;\n\t\t};\n\n\t\twatchdog@f8005000 {\n\t\t\tclocks = <0x02 0x2d>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x09 0x01>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <0x0a>;\n\t\t\tphandle = <0x3a>;\n\t\t};\n\n\t\tetb@f8801000 {\n\t\t\tcompatible = \"arm,coresight-etb10\\0arm,primecell\";\n\t\t\treg = <0xf8801000 0x1000>;\n\t\t\tclocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;\n\t\t\tclock-names = \"apb_pclk\\0dbg_trc\\0dbg_apb\";\n\n\t\t\tin-ports {\n\n\t\t\t\tport {\n\n\t\t\t\t\tendpoint {\n\t\t\t\t\t\tremote-endpoint = <0x0c>;\n\t\t\t\t\t\tphandle = <0x06>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\ttpiu@f8803000 {\n\t\t\tcompatible = \"arm,coresight-tpiu\\0arm,primecell\";\n\t\t\treg = <0xf8803000 0x1000>;\n\t\t\tclocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;\n\t\t\tclock-names = \"apb_pclk\\0dbg_trc\\0dbg_apb\";\n\n\t\t\tin-ports {\n\n\t\t\t\tport {\n\n\t\t\t\t\tendpoint {\n\t\t\t\t\t\tremote-endpoint = <0x0d>;\n\t\t\t\t\t\tphandle = <0x05>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tfunnel@f8804000 {\n\t\t\tcompatible = \"arm,coresight-static-funnel\\0arm,primecell\";\n\t\t\treg = <0xf8804000 0x1000>;\n\t\t\tclocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;\n\t\t\tclock-names = \"apb_pclk\\0dbg_trc\\0dbg_apb\";\n\n\t\t\tout-ports {\n\n\t\t\t\tport {\n\n\t\t\t\t\tendpoint {\n\t\t\t\t\t\tremote-endpoint = <0x0e>;\n\t\t\t\t\t\tphandle = <0x07>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tin-ports {\n\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t#size-cells = <0x00>;\n\n\t\t\t\tport@0 {\n\t\t\t\t\treg = <0x00>;\n\n\t\t\t\t\tendpoint {\n\t\t\t\t\t\tremote-endpoint = <0x0f>;\n\t\t\t\t\t\tphandle = <0x12>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tport@1 {\n\t\t\t\t\treg = <0x01>;\n\n\t\t\t\t\tendpoint {\n\t\t\t\t\t\tremote-endpoint = <0x10>;\n\t\t\t\t\t\tphandle = <0x14>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tport@2 {\n\t\t\t\t\treg = <0x02>;\n\n\t\t\t\t\tendpoint {\n\t\t\t\t\t\tphandle = <0x3b>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tptm@f889c000 {\n\t\t\tcompatible = \"arm,coresight-etm3x\\0arm,primecell\";\n\t\t\treg = <0xf889c000 0x1000>;\n\t\t\tclocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;\n\t\t\tclock-names = \"apb_pclk\\0dbg_trc\\0dbg_apb\";\n\t\t\tcpu = <0x11>;\n\n\t\t\tout-ports {\n\n\t\t\t\tport {\n\n\t\t\t\t\tendpoint {\n\t\t\t\t\t\tremote-endpoint = <0x12>;\n\t\t\t\t\t\tphandle = <0x0f>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tptm@f889d000 {\n\t\t\tcompatible = \"arm,coresight-etm3x\\0arm,primecell\";\n\t\t\treg = <0xf889d000 0x1000>;\n\t\t\tclocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;\n\t\t\tclock-names = \"apb_pclk\\0dbg_trc\\0dbg_apb\";\n\t\t\tcpu = <0x13>;\n\n\t\t\tout-ports {\n\n\t\t\t\tport {\n\n\t\t\t\t\tendpoint {\n\t\t\t\t\t\tremote-endpoint = <0x14>;\n\t\t\t\t\t\tphandle = <0x10>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\taliases {\n\t\tethernet0 = \"/axi/ethernet@e000b000\";\n\t\tserial0 = \"/axi/serial@e0001000\";\n\t\tphandle = <0x3c>;\n\t};\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x00 0x40000000>;\n\t};\n\n\tchosen {\n\t\tstdout-path = \"/amba@0/uart@E0001000\";\n\t};\n\n\tclocks {\n\n\t\tclock@0 {\n\t\t\t#clock-cells = <0x00>;\n\t\t\tcompatible = \"adjustable-clock\";\n\t\t\tclock-frequency = <0x2625a00>;\n\t\t\tclock-accuracy = <0x30d40>;\n\t\t\tclock-output-names = \"ad9364_ext_refclk\";\n\t\t\tphandle = <0x08>;\n\t\t};\n\n\t\tclock@1 {\n\t\t\t#clock-cells = <0x00>;\n\t\t\tcompatible = \"fixed-clock\";\n\t\t\tclock-frequency = <0x16e3600>;\n\t\t\tclock-output-names = \"24MHz\";\n\t\t\tphandle = <0x15>;\n\t\t};\n\t};\n\n\tusb-ulpi-gpio-gate@0 {\n\t\tcompatible = \"gpio-gate-clock\";\n\t\tclocks = <0x15>;\n\t\t#clock-cells = <0x00>;\n\t\tenable-gpios = <0x09 0x09 0x01>;\n\t\tphandle = <0x3d>;\n\t};\n\n\tfpga-axi@0 {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x01>;\n\t\t#size-cells = <0x01>;\n\t\tranges;\n\t\tphandle = <0x3e>;\n\n\t\ti2c@41600000 {\n\t\t\tcompatible = \"xlnx,axi-iic-1.02.a\\0xlnx,xps-iic-2.00.a\";\n\t\t\treg = <0x41600000 0x10000>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x3a 0x04>;\n\t\t\tclocks = <0x02 0x0f>;\n\t\t\tclock-names = \"pclk\";\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tphandle = <0x3f>;\n\n\t\t\tad7291@20 {\n\t\t\t\tcompatible = \"adi,ad7291\";\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tad7291-bob@2C {\n\t\t\t\tcompatible = \"adi,ad7291\";\n\t\t\t\treg = <0x2c>;\n\t\t\t};\n\n\t\t\teeprom@50 {\n\t\t\t\tcompatible = \"at24,24c32\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\n\t\t// dma@7c400000 {\n\t\t// \tcompatible = \"adi,axi-dmac-1.00.a\";\n\t\t// \treg = <0x7c400000 0x10000>;\n\t\t// \t#dma-cells = <0x01>;\n\t\t// \tinterrupts = <0x00 0x39 0x04>;\n\t\t// \tclocks = <0x02 0x10>;\n\t\t// \tphandle = <0x16>;\n\n\t\t// \tadi,channels {\n\t\t// \t\t#size-cells = <0x00>;\n\t\t// \t\t#address-cells = <0x01>;\n\n\t\t// \t\tdma-channel@0 {\n\t\t// \t\t\treg = <0x00>;\n\t\t// \t\t\tadi,source-bus-width = <0x40>;\n\t\t// \t\t\tadi,source-bus-type = <0x02>;\n\t\t// \t\t\tadi,destination-bus-width = <0x40>;\n\t\t// \t\t\tadi,destination-bus-type = <0x00>;\n\t\t// \t\t};\n\t\t// \t};\n\t\t// };\n\n\t\t// dma@7c420000 {\n\t\t// \tcompatible = \"adi,axi-dmac-1.00.a\";\n\t\t// \treg = <0x7c420000 0x10000>;\n\t\t// \t#dma-cells = <0x01>;\n\t\t// \tinterrupts = <0x00 0x38 0x04>;\n\t\t// \tclocks = <0x02 0x10>;\n\t\t// \tphandle = <0x18>;\n\n\t\t// \tadi,channels {\n\t\t// \t\t#size-cells = <0x00>;\n\t\t// \t\t#address-cells = <0x01>;\n\n\t\t// \t\tdma-channel@0 {\n\t\t// \t\t\treg = <0x00>;\n\t\t// \t\t\tadi,source-bus-width = <0x40>;\n\t\t// \t\t\tadi,source-bus-type = <0x00>;\n\t\t// \t\t\tadi,destination-bus-width = <0x40>;\n\t\t// \t\t\tadi,destination-bus-type = <0x02>;\n\t\t// \t\t};\n\t\t// \t};\n\t\t// };\n\n\t\tsdr: sdr {\n\t\t\tcompatible =\"sdr,sdr\";\n\t\t\tdmas = <&rx_dma 1\n\t\t\t\t\t&tx_dma 0>;\n\t\t\tdma-names = \"rx_dma_s2mm\", \"tx_dma_mm2s\";\n\t\t\tinterrupt-names = \"not_valid_anymore\", \"rx_pkt_intr\", \"tx_itrpt\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 29 1 0 30 1 0 33 1 0 34 1>;\n\t\t} ;\n\n\t\t// axidmatest_1: axidmatest@1 {\n\t\t// \tcompatible =\"xlnx,axi-dma-test-1.00.a\";\n\t\t// \tdmas = <&rx_dma 0\n\t\t// \t\t&rx_dma 1>;\n\t\t// \tdma-names = \"axidma0\", \"axidma1\";\n\t\t// } ;\n\n\t\ttx_dma: dma@80400000 {\n\t\t\t#dma-cells = <1>;\n\t\t\tclock-names = \"s_axi_lite_aclk\", \"m_axi_sg_aclk\", \"m_axi_mm2s_aclk\", \"m_axi_s2mm_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"xlnx,axi-dma-1.00.a\";\n\t\t\tinterrupt-names = \"mm2s_introut\", \"s2mm_introut\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 35 4 0 36 4>;\n\t\t\treg = <0x80400000 0x10000>;\n\t\t\txlnx,addrwidth = <0x20>;\n\t\t\txlnx,include-sg ;\n\t\t\txlnx,sg-length-width = <0xe>;\n\t\t\tdma-channel@80400000 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-mm2s-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 35 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x0>;\n\t\t\t};\n\t\t\tdma-channel@80400030 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-s2mm-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 36 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x0>;\n\t\t\t};\n\t\t};\n\t\t\n\t\trx_dma: dma@80410000 {\n\t\t\t#dma-cells = <1>;\n\t\t\tclock-names = \"s_axi_lite_aclk\", \"m_axi_sg_aclk\", \"m_axi_mm2s_aclk\", \"m_axi_s2mm_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"xlnx,axi-dma-1.00.a\";\n\t\t\t//dma-coherent ;\n\t\t\tinterrupt-names = \"mm2s_introut\", \"s2mm_introut\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 31 4 0 32 4>;\n\t\t\treg = <0x80410000 0x10000>;\n\t\t\txlnx,addrwidth = <0x20>;\n\t\t\txlnx,include-sg ;\n\t\t\txlnx,sg-length-width = <0xe>;\n\t\t\tdma-channel@80410000 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-mm2s-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 31 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x1>;\n\t\t\t};\n\t\t\tdma-channel@80410030 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-s2mm-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 32 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x1>;\n\t\t\t};\n\t\t};\n\n\t\ttx_intf_0: tx_intf@83c00000 {\n\t\t\tclock-names = \"s00_axi_aclk\", \"s00_axis_aclk\";//, \"s01_axis_aclk\", \"m00_axis_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"sdr,tx_intf\";\n\t\t\tinterrupt-names = \"tx_itrpt\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 34 1>;\n\t\t\treg = <0x83c00000 0x10000>;\n\t\t\txlnx,s00-axi-addr-width = <0x7>;\n\t\t\txlnx,s00-axi-data-width = <0x20>;\n\t\t};\n\n\t\trx_intf_0: rx_intf@83c20000 {\n\t\t\tclock-names = \"s00_axi_aclk\", \"m00_axis_aclk\";//, \"s00_axis_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>;\n\t\t\tcompatible = \"sdr,rx_intf\";\n\t\t\tinterrupt-names = \"not_valid_anymore\", \"rx_pkt_intr\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 29 1 0 30 1>;\n\t\t\treg = <0x83c20000 0x10000>;\n\t\t\txlnx,s00-axi-addr-width = <0x7>;\n\t\t\txlnx,s00-axi-data-width = <0x20>;\n\t\t};\n\n\t\topenofdm_tx_0: openofdm_tx@83c10000 {\n\t\t\tclock-names = \"clk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,openofdm_tx\";\n\t\t\treg = <0x83c10000 0x10000>;\n\t\t};\n\n\t\topenofdm_rx_0: openofdm_rx@83c30000 {\n\t\t\tclock-names = \"clk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,openofdm_rx\";\n\t\t\treg = <0x83c30000 0x10000>;\n\t\t};\n\n\t\txpu_0: xpu@83c40000 {\n\t\t\tclock-names = \"s00_axi_aclk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,xpu\";\n\t\t\treg = <0x83c40000 0x10000>;\n\t\t};\n\n\t\tside_ch_0: side_ch@83c50000 {\n\t\t\tclock-names = \"s00_axi_aclk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,side_ch\";\n\t\t\treg = <0x83c50000 0x10000>;\n\t\t\tdmas = <&rx_dma 0\n\t\t\t\t\t&tx_dma 1>;\n\t\t\tdma-names = \"rx_dma_mm2s\", \"tx_dma_s2mm\";\n\t\t};\n\n\t\tcf-ad9361-lpc@79020000 {\n\t\t\tcompatible = \"adi,axi-ad9361-6.00.a\";\n\t\t\treg = <0x79020000 0x6000>;\n\t\t\t// dmas = <0x16 0x00>;\n\t\t\t// dma-names = \"rx\";\n\t\t\tspibus-connected = <0x17>;\n\t\t\tphandle = <0x40>;\n\t\t};\n\n\t\tcf-ad9361-dds-core-lpc@79024000 {\n\t\t\tcompatible = \"adi,axi-ad9361-dds-6.00.a\";\n\t\t\treg = <0x79024000 0x1000>;\n\t\t\tclocks = <0x17 0x0d>;\n\t\t\tclock-names = \"sampl_clk\";\n\t\t\t// dmas = <0x18 0x00>;\n\t\t\t// dma-names = \"tx\";\n\t\t\tphandle = <0x41>;\n\t\t};\n\n\t\tmwipcore@43c00000 {\n\t\t\tcompatible = \"mathworks,mwipcore-axi4lite-v1.00\";\n\t\t\treg = <0x43c00000 0xffff>;\n\t\t};\n\n\t\t// axi-sysid-0@45000000 {\n\t\t// \tcompatible = \"adi,axi-sysid-1.00.a\";\n\t\t// \treg = <0x45000000 0x10000>;\n\t\t// \tphandle = <0x42>;\n\t\t// };\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled0 {\n\t\t\tlabel = \"led0:green\";\n\t\t\tgpios = <0x09 0x15 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t};\n\n\n};\n"
  },
  {
    "path": "kernel_boot/boards/neptunesdr/devicetree.dts",
    "content": "/dts-v1/;\n\n/ {\n\t#address-cells = <0x01>;\n\t#size-cells = <0x01>;\n\tcompatible = \"xlnx,zynq-7000\";\n\tinterrupt-parent = <0x01>;\n\tmodel = \"neptunesdr\";\n\n\tcpus {\n\t\t#address-cells = <0x01>;\n\t\t#size-cells = <0x00>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0x00>;\n\t\t\tclocks = <0x02 0x03>;\n\t\t\tclock-latency = <0x3e8>;\n\t\t\tcpu0-supply = <0x03>;\n\t\t\toperating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>;\n\t\t\tphandle = <0x11>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0x01>;\n\t\t\tclocks = <0x02 0x03>;\n\t\t\tphandle = <0x13>;\n\t\t};\n\t};\n\n\tfpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <0x04>;\n\t\t#address-cells = <0x01>;\n\t\t#size-cells = <0x01>;\n\t\tranges;\n\t\tphandle = <0x19>;\n\t};\n\n\tpmu@f8891000 {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0x00 0x05 0x04 0x00 0x06 0x04>;\n\t\tinterrupt-parent = <0x01>;\n\t\treg = <0xf8891000 0x1000 0xf8893000 0x1000>;\n\t};\n\n\tfixedregulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <0xf4240>;\n\t\tregulator-max-microvolt = <0xf4240>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t\tphandle = <0x03>;\n\t};\n\n\treplicator {\n\t\tcompatible = \"arm,coresight-static-replicator\";\n\t\tclocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;\n\t\tclock-names = \"apb_pclk\\0dbg_trc\\0dbg_apb\";\n\n\t\tout-ports {\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\n\t\t\tport@0 {\n\t\t\t\treg = <0x00>;\n\n\t\t\t\tendpoint {\n\t\t\t\t\tremote-endpoint = <0x05>;\n\t\t\t\t\tphandle = <0x0d>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tport@1 {\n\t\t\t\treg = <0x01>;\n\n\t\t\t\tendpoint {\n\t\t\t\t\tremote-endpoint = <0x06>;\n\t\t\t\t\tphandle = <0x0c>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tin-ports {\n\n\t\t\tport {\n\n\t\t\t\tendpoint {\n\t\t\t\t\tremote-endpoint = <0x07>;\n\t\t\t\t\tphandle = <0x0e>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\taxi {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x01>;\n\t\t#size-cells = <0x01>;\n\t\tinterrupt-parent = <0x01>;\n\t\tranges;\n\t\tphandle = <0x1a>;\n\n\t\tadc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0x00 0x07 0x04>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tclocks = <0x02 0x0c>;\n\t\t\tphandle = <0x1b>;\n\t\t};\n\n\t\tcan@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x02 0x13 0x02 0x24>;\n\t\t\tclock-names = \"can_clk\\0pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0x00 0x1c 0x04>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tphandle = <0x1c>;\n\t\t};\n\n\t\tcan@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x02 0x14 0x02 0x25>;\n\t\t\tclock-names = \"can_clk\\0pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0x00 0x33 0x04>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tphandle = <0x1d>;\n\t\t};\n\n\t\tgpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <0x02>;\n\t\t\tclocks = <0x02 0x2a>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <0x02>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x14 0x04>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t\tphandle = <0x09>;\n\t\t};\n\n\t\ti2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x02 0x26>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x19 0x04>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tphandle = <0x1e>;\n\t\t};\n\n\t\ti2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x02 0x27>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x30 0x04>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tphandle = <0x1f>;\n\t\t};\n\n\t\tinterrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <0x03>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xf8f01000 0x1000 0xf8f00100 0x100>;\n\t\t\tphandle = <0x01>;\n\t\t};\n\n\t\tcache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xf8f02000 0x1000>;\n\t\t\tinterrupts = <0x00 0x02 0x04>;\n\t\t\tarm,data-latency = <0x03 0x02 0x02>;\n\t\t\tarm,tag-latency = <0x02 0x02 0x02>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <0x02>;\n\t\t\tphandle = <0x20>;\n\t\t};\n\n\t\tmemory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t\tphandle = <0x21>;\n\t\t};\n\n\t\tocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x03 0x04>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t\tphandle = <0x22>;\n\t\t};\n\n\t\tserial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\\0cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x02 0x17 0x02 0x28>;\n\t\t\tclock-names = \"uart_clk\\0pclk\";\n\t\t\treg = <0xe0000000 0x1000>;\n\t\t\tinterrupts = <0x00 0x1b 0x04>;\n\t\t\tphandle = <0x23>;\n\t\t};\n\n\t\tserial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\\0cdns,uart-r1p8\";\n\t\t\tstatus = \"okay\";\n\t\t\tclocks = <0x02 0x18 0x02 0x29>;\n\t\t\tclock-names = \"uart_clk\\0pclk\";\n\t\t\treg = <0xe0001000 0x1000>;\n\t\t\tinterrupts = <0x00 0x32 0x04>;\n\t\t\tphandle = <0x24>;\n\t\t};\n\n\t\tspi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x1a 0x04>;\n\t\t\tclocks = <0x02 0x19 0x02 0x22>;\n\t\t\tclock-names = \"ref_clk\\0pclk\";\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tphandle = <0x25>;\n\n\t\t\tad9361-phy@0 {\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x0>;\n\t\t\t\t#clock-cells = <0x1>;\n\t\t\t\tcompatible = \"adi,ad9361\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tspi-cpha;\n\t\t\t\tspi-max-frequency = <0x989680>;\n\t\t\t\tclocks = <0x08 0x00>;\n\t\t\t\tclock-names = \"ad9361_ext_refclk\";\n\t\t\t\tclock-output-names = \"rx_sampl_clk\", \"tx_sampl_clk\";\n\t\t\t\tadi,digital-interface-tune-skip-mode = <0x0>;\n\t\t\t\tadi,pp-tx-swap-enable;\n\t\t\t\tadi,pp-rx-swap-enable;\n\t\t\t\tadi,rx-frame-pulse-mode-enable;\n\t\t\t\tadi,lvds-mode-enable;\n\t\t\t\tadi,lvds-bias-mV = <0x96>;\n\t\t\t\tadi,lvds-rx-onchip-termination-enable;\n\t\t\t\tadi,rx-data-delay = <0x4>;\n\t\t\t\tadi,tx-fb-clock-delay = <0x7>;\n\t\t\t\tadi,xo-disable-use-ext-refclk-enable;\n\t\t\t\tadi,2rx-2tx-mode-enable;\n\t\t\t\tadi,frequency-division-duplex-mode-enable;\n\t\t\t\tadi,rx-rf-port-input-select = <0x0>;\n\t\t\t\tadi,tx-rf-port-input-select = <0x0>;\n\t\t\t\tadi,tx-attenuation-mdB = <0x2710>;\n\t\t\t\tadi,tx-lo-powerdown-managed-enable;\n\t\t\t\tadi,rf-rx-bandwidth-hz = <0x112a880>;\n\t\t\t\tadi,rf-tx-bandwidth-hz = <0x112a880>;\n\t\t\t\tadi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;\n\t\t\t\tadi,tx-synthesizer-frequency-hz = <0x0 0x92080880>;\n\t\t\t\tadi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;\n\t\t\t\tadi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;\n\t\t\t\tadi,gc-rx1-mode = <0x2>;\n\t\t\t\tadi,gc-rx2-mode = <0x2>;\n\t\t\t\tadi,gc-adc-ovr-sample-size = <0x4>;\n\t\t\t\tadi,gc-adc-small-overload-thresh = <0x2f>;\n\t\t\t\tadi,gc-adc-large-overload-thresh = <0x3a>;\n\t\t\t\tadi,gc-lmt-overload-high-thresh = <0x320>;\n\t\t\t\tadi,gc-lmt-overload-low-thresh = <0x2c0>;\n\t\t\t\tadi,gc-dec-pow-measurement-duration = <0x2000>;\n\t\t\t\tadi,gc-low-power-thresh = <0x18>;\n\t\t\t\tadi,mgc-inc-gain-step = <0x2>;\n\t\t\t\tadi,mgc-dec-gain-step = <0x2>;\n\t\t\t\tadi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;\n\t\t\t\tadi,agc-attack-delay-extra-margin-us = <0x1>;\n\t\t\t\tadi,agc-outer-thresh-high = <0x5>;\n\t\t\t\tadi,agc-outer-thresh-high-dec-steps = <0x2>;\n\t\t\t\tadi,agc-inner-thresh-high = <0xa>;\n\t\t\t\tadi,agc-inner-thresh-high-dec-steps = <0x1>;\n\t\t\t\tadi,agc-inner-thresh-low = <0xc>;\n\t\t\t\tadi,agc-inner-thresh-low-inc-steps = <0x1>;\n\t\t\t\tadi,agc-outer-thresh-low = <0x12>;\n\t\t\t\tadi,agc-outer-thresh-low-inc-steps = <0x2>;\n\t\t\t\tadi,agc-adc-small-overload-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-adc-large-overload-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-adc-large-overload-inc-steps = <0x7>;\n\t\t\t\tadi,agc-lmt-overload-large-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-lmt-overload-small-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-lmt-overload-large-inc-steps = <0x7>;\n\t\t\t\tadi,agc-gain-update-interval-us = <0x3e8>;\n\t\t\t\tadi,fagc-dec-pow-measurement-duration = <0x10>;\n        adi,fagc-adc-large-overload-inc-steps = <0x07>;\n\t\t\t\tadi,fagc-lp-thresh-increment-steps = <0x1>;\n\t\t\t\tadi,fagc-lp-thresh-increment-time = <0x5>;\n\t\t\t\tadi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;\n        adi,fagc-dig-sat-ovrg-enable;\n\t\t\t\tadi,fagc-final-overrange-count = <0x3>;\n\t\t\t\tadi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;\n\t\t\t\tadi,fagc-lmt-final-settling-steps = <0x1>;\n\t\t\t\tadi,fagc-lock-level = <0xa>;\n\t\t\t\tadi,fagc-lock-level-gain-increase-upper-limit = <0x5>;\n\t\t\t\tadi,fagc-lock-level-lmt-gain-increase-enable;\n\t\t\t\tadi,fagc-lpf-final-settling-steps = <0x1>;\n\t\t\t\tadi,fagc-optimized-gain-offset = <0x5>;\n\t\t\t\tadi,fagc-power-measurement-duration-in-state5 = <0x10>;\n\t\t\t\tadi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;\n\t\t\t\tadi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;\n\t\t\t\tadi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;\n\t\t\t\tadi,fagc-rst-gla-large-adc-overload-enable;\n\t\t\t\tadi,fagc-rst-gla-large-lmt-overload-enable;\n\t\t\t\tadi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;\n\t\t\t\tadi,fagc-state-wait-time-ns = <0x104>;\n\t\t\t\tadi,fagc-use-last-lock-level-for-set-gain-enable;\n\t\t\t\tadi,rssi-restart-mode = <0x3>;\n\t\t\t\tadi,rssi-delay = <0x1>;\n\t\t\t\tadi,rssi-wait = <0x1>;\n\t\t\t\tadi,rssi-duration = <0x3e8>;\n\t\t\t\tadi,ctrl-outs-index = <0x0>;\n\t\t\t\tadi,ctrl-outs-enable-mask = <0xff>;\n\t\t\t\tadi,temp-sense-measurement-interval-ms = <0x3e8>;\n\t\t\t\tadi,temp-sense-offset-signed = <0xce>;\n\t\t\t\tadi,temp-sense-periodic-measurement-enable;\n\t\t\t\tadi,aux-dac-manual-mode-enable;\n\t\t\t\tadi,aux-dac1-default-value-mV = <0x0>;\n\t\t\t\tadi,aux-dac1-rx-delay-us = <0x0>;\n\t\t\t\tadi,aux-dac1-tx-delay-us = <0x0>;\n\t\t\t\tadi,aux-dac2-default-value-mV = <0x0>;\n\t\t\t\tadi,aux-dac2-rx-delay-us = <0x0>;\n\t\t\t\tadi,aux-dac2-tx-delay-us = <0x0>;\n\t\t\t\ten_agc-gpios = <0x09 0x62 0x0>;\n\t\t\t\tsync-gpios = <0x09 0x63 0x0>;\n\t\t\t\treset-gpios = <0x09 0x64 0x0>;\n\t\t\t\tenable-gpios = <0x09 0x65 0x0>;\n\t\t\t\ttxnrx-gpios = <0x09 0x66 0x0>;\n\t\t\t\tphandle = <0x17>;\n\t\t\t};\n\t\t};\n\n\t\tspi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x31 0x04>;\n\t\t\tclocks = <0x02 0x1a 0x02 0x23>;\n\t\t\tclock-names = \"ref_clk\\0pclk\";\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tphandle = <0x26>;\n\t\t};\n\n\t\tspi@e000d000 {\n\t\t\tclock-names = \"ref_clk\\0pclk\";\n\t\t\tclocks = <0x02 0x0a 0x02 0x2b>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x13 0x04>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tis-dual = <0x00>;\n\t\t\tnum-cs = <0x01>;\n\t\t\tphandle = <0x27>;\n\n\t\t\tps7-qspi@0 {\n\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t#size-cells = <0x01>;\n\t\t\t\tspi-tx-bus-width = <0x01>;\n\t\t\t\tspi-rx-bus-width = <0x04>;\n\t\t\t\tcompatible = \"n25q256a\\0jedec,spi-nor\";\n\t\t\t\treg = <0x00>;\n\t\t\t\tspi-max-frequency = <0x2faf080>;\n\t\t\t\tphandle = <0x28>;\n\n\t\t\t\tpartition@qspi-fsbl-uboot {\n\t\t\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\t\t\treg = <0x00 0xe0000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-uboot-env {\n\t\t\t\t\tlabel = \"qspi-uboot-env\";\n\t\t\t\t\treg = <0xe0000 0x20000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-linux {\n\t\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\t\treg = <0x100000 0x500000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-device-tree {\n\t\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\t\treg = <0x600000 0x20000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-rootfs {\n\t\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\t\treg = <0x620000 0xce0000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-bitstream {\n\t\t\t\t\tlabel = \"qspi-bitstream\";\n\t\t\t\t\treg = <0x1300000 0xd00000>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tmemory-controller@e000e000 {\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x01>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\\0apb_pclk\";\n\t\t\tclocks = <0x02 0x0b 0x02 0x2c>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\\0arm,primecell\";\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x12 0x04>;\n\t\t\tranges;\n\t\t\treg = <0xe000e000 0x1000>;\n\t\t\tphandle = <0x29>;\n\n\t\t\tflash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t#size-cells = <0x01>;\n\t\t\t\tphandle = <0x2a>;\n\t\t\t};\n\n\t\t\tflash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x2000000>;\n\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t#size-cells = <0x01>;\n\t\t\t\tphandle = <0x2b>;\n\t\t\t};\n\t\t};\n\n\t\tethernet@e000b000 {\n\t\t\tcompatible = \"cdns,zynq-gem\\0cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupts = <0x00 0x16 0x04>;\n\t\t\tclocks = <0x02 0x1e 0x02 0x1e 0x02 0x0d>;\n\t\t\tclock-names = \"pclk\\0hclk\\0tx_clk\";\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tphy-handle = <0x0a>;\n\t\t\tphy-mode = \"rgmii-id\";\n\t\t\tphandle = <0x2c>;\n\n\t\t\tphy@0 {\n\t\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\t\treg = <0x00>;\n\t\t\t\tmarvell,reg-init = <0x03 0x10 0xff00 0x1e 0x03 0x11 0xfff0 0x00>;\n\t\t\t\tphandle = <0x0a>;\n\t\t\t};\n\t\t};\n\n\t\tethernet@e000c000 {\n\t\t\tcompatible = \"cdns,zynq-gem\\0cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0x00 0x2d 0x04>;\n\t\t\tclocks = <0x02 0x1f 0x02 0x1f 0x02 0x0e>;\n\t\t\tclock-names = \"pclk\\0hclk\\0tx_clk\";\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tphandle = <0x2d>;\n\t\t};\n\n\t\tmmc@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"clk_xin\\0clk_ahb\";\n\t\t\tclocks = <0x02 0x15 0x02 0x20>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x18 0x04>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t\tdisable-wp;\n\t\t\tphandle = <0x2e>;\n\t\t};\n\n\t\tmmc@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\\0clk_ahb\";\n\t\t\tclocks = <0x02 0x16 0x02 0x21>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x2f 0x04>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t\tphandle = <0x2f>;\n\t\t};\n\n\t\tslcr@f8000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x01>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\\0syscon\\0simple-mfd\";\n\t\t\treg = <0xf8000000 0x1000>;\n\t\t\tranges;\n\t\t\tphandle = <0x0b>;\n\n\t\t\tclkc@100 {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <0x01>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0x0f>;\n\t\t\t\tclock-output-names = \"armpll\\0ddrpll\\0iopll\\0cpu_6or4x\\0cpu_3or2x\\0cpu_2x\\0cpu_1x\\0ddr2x\\0ddr3x\\0dci\\0lqspi\\0smc\\0pcap\\0gem0\\0gem1\\0fclk0\\0fclk1\\0fclk2\\0fclk3\\0can0\\0can1\\0sdio0\\0sdio1\\0uart0\\0uart1\\0spi0\\0spi1\\0dma\\0usb0_aper\\0usb1_aper\\0gem0_aper\\0gem1_aper\\0sdio0_aper\\0sdio1_aper\\0spi0_aper\\0spi1_aper\\0can0_aper\\0can1_aper\\0i2c0_aper\\0i2c1_aper\\0uart0_aper\\0uart1_aper\\0gpio_aper\\0lqspi_aper\\0smc_aper\\0swdt\\0dbg_trc\\0dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t\tps-clk-frequency = <0x1fca055>;\n\t\t\t\tphandle = <0x02>;\n\t\t\t};\n\n\t\t\trstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <0x01>;\n\t\t\t\tsyscon = <0x0b>;\n\t\t\t\tphandle = <0x30>;\n\t\t\t};\n\n\t\t\tpinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <0x0b>;\n\t\t\t\tphandle = <0x31>;\n\t\t\t};\n\t\t};\n\n\t\tdmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\\0arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupt-names = \"abort\\0dma0\\0dma1\\0dma2\\0dma3\\0dma4\\0dma5\\0dma6\\0dma7\";\n\t\t\tinterrupts = <0x00 0x0d 0x04 0x00 0x0e 0x04 0x00 0x0f 0x04 0x00 0x10 0x04 0x00 0x11 0x04 0x00 0x28 0x04 0x00 0x29 0x04 0x00 0x2a 0x04 0x00 0x2b 0x04>;\n\t\t\t#dma-cells = <0x01>;\n\t\t\t#dma-channels = <0x08>;\n\t\t\t#dma-requests = <0x04>;\n\t\t\tclocks = <0x02 0x1b>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t\tphandle = <0x32>;\n\t\t};\n\n\t\tdevcfg@f8007000 {\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x08 0x04>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tclocks = <0x02 0x0c 0x02 0x0f 0x02 0x10 0x02 0x11 0x02 0x12>;\n\t\t\tclock-names = \"ref_clk\\0fclk0\\0fclk1\\0fclk2\\0fclk3\";\n\t\t\tsyscon = <0x0b>;\n\t\t\tphandle = <0x04>;\n\t\t};\n\n\t\tefuse@f800d000 {\n\t\t\tcompatible = \"xlnx,zynq-efuse\";\n\t\t\treg = <0xf800d000 0x20>;\n\t\t\tphandle = <0x33>;\n\t\t};\n\n\t\ttimer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <0x01 0x0b 0x301>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tclocks = <0x02 0x04>;\n\t\t\tphandle = <0x34>;\n\t\t};\n\n\t\ttimer@f8001000 {\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x0a 0x04 0x00 0x0b 0x04 0x00 0x0c 0x04>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <0x02 0x06>;\n\t\t\treg = <0xf8001000 0x1000>;\n\t\t\tphandle = <0x35>;\n\t\t};\n\n\t\ttimer@f8002000 {\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x25 0x04 0x00 0x26 0x04 0x00 0x27 0x04>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <0x02 0x06>;\n\t\t\treg = <0xf8002000 0x1000>;\n\t\t\tphandle = <0x36>;\n\t\t};\n\n\t\ttimer@f8f00600 {\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x01 0x0d 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <0x02 0x04>;\n\t\t\tphandle = <0x37>;\n\t\t};\n\n\t\tusb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\\0chipidea,usb2\";\n\t\t\tstatus = \"okay\";\n\t\t\tclocks = <0x02 0x1c>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x15 0x04>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t\tdr_mode = \"host\";\n\t\t\txlnx,phy-reset-gpio = <0x09 0x07 0x00>;\n\t\t\tphandle = <0x38>;\n\t\t};\n\n\t\tusb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\\0chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x02 0x1d>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x2c 0x04>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t\tphandle = <0x39>;\n\t\t};\n\n\t\twatchdog@f8005000 {\n\t\t\tclocks = <0x02 0x2d>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x09 0x01>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <0x0a>;\n\t\t\tphandle = <0x3a>;\n\t\t};\n\n\t\tetb@f8801000 {\n\t\t\tcompatible = \"arm,coresight-etb10\\0arm,primecell\";\n\t\t\treg = <0xf8801000 0x1000>;\n\t\t\tclocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;\n\t\t\tclock-names = \"apb_pclk\\0dbg_trc\\0dbg_apb\";\n\n\t\t\tin-ports {\n\n\t\t\t\tport {\n\n\t\t\t\t\tendpoint {\n\t\t\t\t\t\tremote-endpoint = <0x0c>;\n\t\t\t\t\t\tphandle = <0x06>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\ttpiu@f8803000 {\n\t\t\tcompatible = \"arm,coresight-tpiu\\0arm,primecell\";\n\t\t\treg = <0xf8803000 0x1000>;\n\t\t\tclocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;\n\t\t\tclock-names = \"apb_pclk\\0dbg_trc\\0dbg_apb\";\n\n\t\t\tin-ports {\n\n\t\t\t\tport {\n\n\t\t\t\t\tendpoint {\n\t\t\t\t\t\tremote-endpoint = <0x0d>;\n\t\t\t\t\t\tphandle = <0x05>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tfunnel@f8804000 {\n\t\t\tcompatible = \"arm,coresight-static-funnel\\0arm,primecell\";\n\t\t\treg = <0xf8804000 0x1000>;\n\t\t\tclocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;\n\t\t\tclock-names = \"apb_pclk\\0dbg_trc\\0dbg_apb\";\n\n\t\t\tout-ports {\n\n\t\t\t\tport {\n\n\t\t\t\t\tendpoint {\n\t\t\t\t\t\tremote-endpoint = <0x0e>;\n\t\t\t\t\t\tphandle = <0x07>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tin-ports {\n\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t#size-cells = <0x00>;\n\n\t\t\t\tport@0 {\n\t\t\t\t\treg = <0x00>;\n\n\t\t\t\t\tendpoint {\n\t\t\t\t\t\tremote-endpoint = <0x0f>;\n\t\t\t\t\t\tphandle = <0x12>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tport@1 {\n\t\t\t\t\treg = <0x01>;\n\n\t\t\t\t\tendpoint {\n\t\t\t\t\t\tremote-endpoint = <0x10>;\n\t\t\t\t\t\tphandle = <0x14>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tport@2 {\n\t\t\t\t\treg = <0x02>;\n\n\t\t\t\t\tendpoint {\n\t\t\t\t\t\tphandle = <0x3b>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tptm@f889c000 {\n\t\t\tcompatible = \"arm,coresight-etm3x\\0arm,primecell\";\n\t\t\treg = <0xf889c000 0x1000>;\n\t\t\tclocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;\n\t\t\tclock-names = \"apb_pclk\\0dbg_trc\\0dbg_apb\";\n\t\t\tcpu = <0x11>;\n\n\t\t\tout-ports {\n\n\t\t\t\tport {\n\n\t\t\t\t\tendpoint {\n\t\t\t\t\t\tremote-endpoint = <0x12>;\n\t\t\t\t\t\tphandle = <0x0f>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tptm@f889d000 {\n\t\t\tcompatible = \"arm,coresight-etm3x\\0arm,primecell\";\n\t\t\treg = <0xf889d000 0x1000>;\n\t\t\tclocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;\n\t\t\tclock-names = \"apb_pclk\\0dbg_trc\\0dbg_apb\";\n\t\t\tcpu = <0x13>;\n\n\t\t\tout-ports {\n\n\t\t\t\tport {\n\n\t\t\t\t\tendpoint {\n\t\t\t\t\t\tremote-endpoint = <0x14>;\n\t\t\t\t\t\tphandle = <0x10>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\taliases {\n\t\tethernet0 = \"/axi/ethernet@e000b000\";\n\t\tserial0 = \"/axi/serial@e0001000\";\n\t\tphandle = <0x3c>;\n\t};\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x00 0x20000000>;\n\t};\n\n\tchosen {\n\t\tstdout-path = \"/amba@0/uart@E0001000\";\n\t};\n\n\tclocks {\n\n\t\tclock@0 {\n\t\t\t#clock-cells = <0x00>;\n\t\t\tcompatible = \"adjustable-clock\";\n\t\t\tclock-frequency = <0x2625a00>;\n\t\t\tclock-accuracy = <0x30d40>;\n\t\t\tclock-output-names = \"ad9364_ext_refclk\";\n\t\t\tphandle = <0x08>;\n\t\t};\n\n\t\tclock@1 {\n\t\t\t#clock-cells = <0x00>;\n\t\t\tcompatible = \"fixed-clock\";\n\t\t\tclock-frequency = <0x16e3600>;\n\t\t\tclock-output-names = \"24MHz\";\n\t\t\tphandle = <0x15>;\n\t\t};\n\t};\n\n\tusb-ulpi-gpio-gate@0 {\n\t\tcompatible = \"gpio-gate-clock\";\n\t\tclocks = <0x15>;\n\t\t#clock-cells = <0x00>;\n\t\tenable-gpios = <0x09 0x09 0x01>;\n\t\tphandle = <0x3d>;\n\t};\n\n\tfpga-axi@0 {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x01>;\n\t\t#size-cells = <0x01>;\n\t\tranges;\n\t\tphandle = <0x3e>;\n\n\t\ti2c@41600000 {\n\t\t\tcompatible = \"xlnx,axi-iic-1.02.a\\0xlnx,xps-iic-2.00.a\";\n\t\t\treg = <0x41600000 0x10000>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x3a 0x04>;\n\t\t\tclocks = <0x02 0x0f>;\n\t\t\tclock-names = \"pclk\";\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tphandle = <0x3f>;\n\n\t\t\tad7291@20 {\n\t\t\t\tcompatible = \"adi,ad7291\";\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tad7291-bob@2C {\n\t\t\t\tcompatible = \"adi,ad7291\";\n\t\t\t\treg = <0x2c>;\n\t\t\t};\n\n\t\t\teeprom@50 {\n\t\t\t\tcompatible = \"at24,24c32\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\n\t\t// dma@7c400000 {\n\t\t// \tcompatible = \"adi,axi-dmac-1.00.a\";\n\t\t// \treg = <0x7c400000 0x10000>;\n\t\t// \t#dma-cells = <0x01>;\n\t\t// \tinterrupts = <0x00 0x39 0x04>;\n\t\t// \tclocks = <0x02 0x10>;\n\t\t// \tphandle = <0x16>;\n\n\t\t// \tadi,channels {\n\t\t// \t\t#size-cells = <0x00>;\n\t\t// \t\t#address-cells = <0x01>;\n\n\t\t// \t\tdma-channel@0 {\n\t\t// \t\t\treg = <0x00>;\n\t\t// \t\t\tadi,source-bus-width = <0x40>;\n\t\t// \t\t\tadi,source-bus-type = <0x02>;\n\t\t// \t\t\tadi,destination-bus-width = <0x40>;\n\t\t// \t\t\tadi,destination-bus-type = <0x00>;\n\t\t// \t\t};\n\t\t// \t};\n\t\t// };\n\n\t\t// dma@7c420000 {\n\t\t// \tcompatible = \"adi,axi-dmac-1.00.a\";\n\t\t// \treg = <0x7c420000 0x10000>;\n\t\t// \t#dma-cells = <0x01>;\n\t\t// \tinterrupts = <0x00 0x38 0x04>;\n\t\t// \tclocks = <0x02 0x10>;\n\t\t// \tphandle = <0x18>;\n\n\t\t// \tadi,channels {\n\t\t// \t\t#size-cells = <0x00>;\n\t\t// \t\t#address-cells = <0x01>;\n\n\t\t// \t\tdma-channel@0 {\n\t\t// \t\t\treg = <0x00>;\n\t\t// \t\t\tadi,source-bus-width = <0x40>;\n\t\t// \t\t\tadi,source-bus-type = <0x00>;\n\t\t// \t\t\tadi,destination-bus-width = <0x40>;\n\t\t// \t\t\tadi,destination-bus-type = <0x02>;\n\t\t// \t\t};\n\t\t// \t};\n\t\t// };\n\n\t\tsdr: sdr {\n\t\t\tcompatible =\"sdr,sdr\";\n\t\t\tdmas = <&rx_dma 1\n\t\t\t\t\t&tx_dma 0>;\n\t\t\tdma-names = \"rx_dma_s2mm\", \"tx_dma_mm2s\";\n\t\t\tinterrupt-names = \"not_valid_anymore\", \"rx_pkt_intr\", \"tx_itrpt\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 29 1 0 30 1 0 33 1 0 34 1>;\n\t\t} ;\n\n\t\t// axidmatest_1: axidmatest@1 {\n\t\t// \tcompatible =\"xlnx,axi-dma-test-1.00.a\";\n\t\t// \tdmas = <&rx_dma 0\n\t\t// \t\t&rx_dma 1>;\n\t\t// \tdma-names = \"axidma0\", \"axidma1\";\n\t\t// } ;\n\n\t\ttx_dma: dma@80400000 {\n\t\t\t#dma-cells = <1>;\n\t\t\tclock-names = \"s_axi_lite_aclk\", \"m_axi_sg_aclk\", \"m_axi_mm2s_aclk\", \"m_axi_s2mm_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"xlnx,axi-dma-1.00.a\";\n\t\t\tinterrupt-names = \"mm2s_introut\", \"s2mm_introut\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 35 4 0 36 4>;\n\t\t\treg = <0x80400000 0x10000>;\n\t\t\txlnx,addrwidth = <0x20>;\n\t\t\txlnx,include-sg ;\n\t\t\txlnx,sg-length-width = <0xe>;\n\t\t\tdma-channel@80400000 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-mm2s-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 35 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x0>;\n\t\t\t};\n\t\t\tdma-channel@80400030 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-s2mm-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 36 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x0>;\n\t\t\t};\n\t\t};\n\t\t\n\t\trx_dma: dma@80410000 {\n\t\t\t#dma-cells = <1>;\n\t\t\tclock-names = \"s_axi_lite_aclk\", \"m_axi_sg_aclk\", \"m_axi_mm2s_aclk\", \"m_axi_s2mm_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"xlnx,axi-dma-1.00.a\";\n\t\t\t//dma-coherent ;\n\t\t\tinterrupt-names = \"mm2s_introut\", \"s2mm_introut\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 31 4 0 32 4>;\n\t\t\treg = <0x80410000 0x10000>;\n\t\t\txlnx,addrwidth = <0x20>;\n\t\t\txlnx,include-sg ;\n\t\t\txlnx,sg-length-width = <0xe>;\n\t\t\tdma-channel@80410000 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-mm2s-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 31 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x1>;\n\t\t\t};\n\t\t\tdma-channel@80410030 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-s2mm-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 32 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x1>;\n\t\t\t};\n\t\t};\n\n\t\ttx_intf_0: tx_intf@83c00000 {\n\t\t\tclock-names = \"s00_axi_aclk\", \"s00_axis_aclk\";//, \"s01_axis_aclk\", \"m00_axis_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"sdr,tx_intf\";\n\t\t\tinterrupt-names = \"tx_itrpt\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 34 1>;\n\t\t\treg = <0x83c00000 0x10000>;\n\t\t\txlnx,s00-axi-addr-width = <0x7>;\n\t\t\txlnx,s00-axi-data-width = <0x20>;\n\t\t};\n\n\t\trx_intf_0: rx_intf@83c20000 {\n\t\t\tclock-names = \"s00_axi_aclk\", \"m00_axis_aclk\";//, \"s00_axis_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>;\n\t\t\tcompatible = \"sdr,rx_intf\";\n\t\t\tinterrupt-names = \"not_valid_anymore\", \"rx_pkt_intr\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 29 1 0 30 1>;\n\t\t\treg = <0x83c20000 0x10000>;\n\t\t\txlnx,s00-axi-addr-width = <0x7>;\n\t\t\txlnx,s00-axi-data-width = <0x20>;\n\t\t};\n\n\t\topenofdm_tx_0: openofdm_tx@83c10000 {\n\t\t\tclock-names = \"clk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,openofdm_tx\";\n\t\t\treg = <0x83c10000 0x10000>;\n\t\t};\n\n\t\topenofdm_rx_0: openofdm_rx@83c30000 {\n\t\t\tclock-names = \"clk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,openofdm_rx\";\n\t\t\treg = <0x83c30000 0x10000>;\n\t\t};\n\n\t\txpu_0: xpu@83c40000 {\n\t\t\tclock-names = \"s00_axi_aclk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,xpu\";\n\t\t\treg = <0x83c40000 0x10000>;\n\t\t};\n\n\t\tside_ch_0: side_ch@83c50000 {\n\t\t\tclock-names = \"s00_axi_aclk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,side_ch\";\n\t\t\treg = <0x83c50000 0x10000>;\n\t\t\tdmas = <&rx_dma 0\n\t\t\t\t\t&tx_dma 1>;\n\t\t\tdma-names = \"rx_dma_mm2s\", \"tx_dma_s2mm\";\n\t\t};\n\n\t\tcf-ad9361-lpc@79020000 {\n\t\t\tcompatible = \"adi,axi-ad9361-6.00.a\";\n\t\t\treg = <0x79020000 0x6000>;\n\t\t\t// dmas = <0x16 0x00>;\n\t\t\t// dma-names = \"rx\";\n\t\t\tspibus-connected = <0x17>;\n\t\t\tphandle = <0x40>;\n\t\t};\n\n\t\tcf-ad9361-dds-core-lpc@79024000 {\n\t\t\tcompatible = \"adi,axi-ad9361-dds-6.00.a\";\n\t\t\treg = <0x79024000 0x1000>;\n\t\t\tclocks = <0x17 0x0d>;\n\t\t\tclock-names = \"sampl_clk\";\n\t\t\t// dmas = <0x18 0x00>;\n\t\t\t// dma-names = \"tx\";\n\t\t\tphandle = <0x41>;\n\t\t};\n\n\t\tmwipcore@43c00000 {\n\t\t\tcompatible = \"mathworks,mwipcore-axi4lite-v1.00\";\n\t\t\treg = <0x43c00000 0xffff>;\n\t\t};\n\n\t\t// axi-sysid-0@45000000 {\n\t\t// \tcompatible = \"adi,axi-sysid-1.00.a\";\n\t\t// \treg = <0x45000000 0x10000>;\n\t\t// \tphandle = <0x42>;\n\t\t// };\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled0 {\n\t\t\tlabel = \"led0:green\";\n\t\t\tgpios = <0x09 0x3a 0x00>;\n\t\t};\n\n\t\tled1 {\n\t\t\tlabel = \"led1:green\";\n\t\t\tgpios = <0x09 0x3b 0x00>;\n\t\t};\n\n\t\tled2 {\n\t\t\tlabel = \"led2:green\";\n\t\t\tgpios = <0x09 0x3c 0x00>;\n\t\t};\n\n\t\tled3 {\n\t\t\tlabel = \"led3:green\";\n\t\t\tgpios = <0x09 0x3d 0x00>;\n\t\t};\n\t};\n\n\tgpio_keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <0x01>;\n\t\t#size-cells = <0x00>;\n\t\tautorepeat;\n\n\t\tpb0 {\n\t\t\tlabel = \"Left\";\n\t\t\tlinux,code = <0x69>;\n\t\t\tgpios = <0x09 0x36 0x00>;\n\t\t};\n\n\t\tpb1 {\n\t\t\tlabel = \"Right\";\n\t\t\tlinux,code = <0x6a>;\n\t\t\tgpios = <0x09 0x37 0x00>;\n\t\t};\n\n\t\tpb2 {\n\t\t\tlabel = \"Up\";\n\t\t\tlinux,code = <0x67>;\n\t\t\tgpios = <0x09 0x38 0x00>;\n\t\t};\n\n\t\tpb3 {\n\t\t\tlabel = \"Down\";\n\t\t\tlinux,code = <0x6c>;\n\t\t\tgpios = <0x09 0x39 0x00>;\n\t\t};\n\n\t\tsw0 {\n\t\t\tlabel = \"SW0\";\n\t\t\tlinux,input-type = <0x05>;\n\t\t\tlinux,code = <0x0d>;\n\t\t\tgpios = <0x09 0x3e 0x00>;\n\t\t};\n\n\t\tsw1 {\n\t\t\tlabel = \"SW1\";\n\t\t\tlinux,input-type = <0x05>;\n\t\t\tlinux,code = <0x01>;\n\t\t\tgpios = <0x09 0x3f 0x00>;\n\t\t};\n\n\t\tsw2 {\n\t\t\tlabel = \"SW2\";\n\t\t\tlinux,input-type = <0x05>;\n\t\t\tlinux,code = <0x02>;\n\t\t\tgpios = <0x09 0x40 0x00>;\n\t\t};\n\n\t\tsw3 {\n\t\t\tlabel = \"SW3\";\n\t\t\tlinux,input-type = <0x05>;\n\t\t\tlinux,code = <0x03>;\n\t\t\tgpios = <0x09 0x41 0x00>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "kernel_boot/boards/sdrpi/devicetree.dts",
    "content": "/dts-v1/;\n\n/ {\n\t#address-cells = <0x1>;\n\t#size-cells = <0x1>;\n\tcompatible = \"xlnx,zynq-7000\";\n\tinterrupt-parent = <0x1>;\n\tmodel = \"HexSDR sdrpi (7z020+ad9361 SDR smart platform with GPSTCXO and RF AP)\";\n\n\tcpus {\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0x0>;\n\t\t\tclocks = <0x2 0x3>;\n\t\t\tclock-latency = <0x3e8>;\n\t\t\tcpu0-supply = <0x3>;\n\t\t\toperating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0x1>;\n\t\t\tclocks = <0x2 0x3>;\n\t\t};\n\t};\n\n\tfpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <0x4>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tranges;\n\t};\n\n\tpmu@f8891000 {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0x0 0x5 0x4 0x0 0x6 0x4>;\n\t\tinterrupt-parent = <0x1>;\n\t\treg = <0xf8891000 0x1000 0xf8893000 0x1000>;\n\t};\n\n\tfixedregulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <0xf4240>;\n\t\tregulator-max-microvolt = <0xf4240>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t\tlinux,phandle = <0x3>;\n\t\tphandle = <0x3>;\n\t};\n\n\tamba {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tinterrupt-parent = <0x1>;\n\t\tranges;\n\n\t\tadc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0x0 0x7 0x4>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tclocks = <0x2 0xc>;\n\t\t};\n\n\t\tcan@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x13 0x2 0x24>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0x0 0x1c 0x4>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x14 0x2 0x25>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0x0 0x33 0x4>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tclocks = <0x2 0x2a>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <0x2>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x14 0x4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t\tlinux,phandle = <0x6>;\n\t\t\tphandle = <0x6>;\n\t\t};\n\n\t\ti2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x26>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x19 0x4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t};\n\n\t\ti2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x27>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x30 0x4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t};\n\n\t\tinterrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <0x3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xf8f01000 0x1000 0xf8f00100 0x100>;\n\t\t\tlinux,phandle = <0x1>;\n\t\t\tphandle = <0x1>;\n\t\t};\n\n\t\tcache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xf8f02000 0x1000>;\n\t\t\tinterrupts = <0x0 0x2 0x4>;\n\t\t\tarm,data-latency = <0x3 0x2 0x2>;\n\t\t\tarm,tag-latency = <0x2 0x2 0x2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <0x2>;\n\t\t};\n\n\t\tmemory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x3 0x4>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t};\n\n\t\tserial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x17 0x2 0x28>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xe0000000 0x1000>;\n\t\t\tinterrupts = <0x0 0x1b 0x4>;\n\t\t};\n\n\t\tserial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"okay\";\n\t\t\tclocks = <0x2 0x18 0x2 0x29>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xe0001000 0x1000>;\n\t\t\tinterrupts = <0x0 0x32 0x4>;\n\t\t};\n\n\t\tspi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x1a 0x4>;\n\t\t\tclocks = <0x2 0x19 0x2 0x22>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\n\t\t\tad9361-phy@0 {\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x0>;\n\t\t\t\t#clock-cells = <0x1>;\n\t\t\t\tcompatible = \"adi,ad9361\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tspi-cpha;\n\t\t\t\tspi-max-frequency = <0x989680>;\n\t\t\t\tclocks = <0x5 0x0>;\n\t\t\t\tclock-names = \"ad9364_ext_refclk\";\n\t\t\t\tclock-output-names = \"rx_sampl_clk\", \"tx_sampl_clk\";\n\t\t\t\tadi,digital-interface-tune-skip-mode = <0x0>;\n\t\t\t\tadi,pp-tx-swap-enable;\n\t\t\t\tadi,pp-rx-swap-enable;\n\t\t\t\tadi,rx-frame-pulse-mode-enable;\n\t\t\t\tadi,lvds-mode-enable;\n\t\t\t\tadi,lvds-bias-mV = <0x96>;\n\t\t\t\tadi,lvds-rx-onchip-termination-enable;\n\t\t\t\tadi,rx-data-delay = <0x4>;\n\t\t\t\tadi,tx-fb-clock-delay = <0x7>;\n\t\t\t\tadi,xo-disable-use-ext-refclk-enable;\n\t\t\t\tadi,2rx-2tx-mode-enable;\n\t\t\t\tadi,frequency-division-duplex-mode-enable;\n\t\t\t\tadi,rx-rf-port-input-select = <0x0>;\n\t\t\t\tadi,tx-rf-port-input-select = <0x0>;\n\t\t\t\tadi,tx-attenuation-mdB = <0x2710>;\n\t\t\t\tadi,tx-lo-powerdown-managed-enable;\n\t\t\t\tadi,rf-rx-bandwidth-hz = <0x112a880>;\n\t\t\t\tadi,rf-tx-bandwidth-hz = <0x112a880>;\n\t\t\t\tadi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;\n\t\t\t\tadi,tx-synthesizer-frequency-hz = <0x0 0x92080880>;\n\t\t\t\tadi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;\n\t\t\t\tadi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;\n\t\t\t\tadi,gc-rx1-mode = <0x2>;\n\t\t\t\tadi,gc-rx2-mode = <0x2>;\n\t\t\t\tadi,gc-adc-ovr-sample-size = <0x4>;\n\t\t\t\tadi,gc-adc-small-overload-thresh = <0x2f>;\n\t\t\t\tadi,gc-adc-large-overload-thresh = <0x3a>;\n\t\t\t\tadi,gc-lmt-overload-high-thresh = <0x320>;\n\t\t\t\tadi,gc-lmt-overload-low-thresh = <0x2c0>;\n\t\t\t\tadi,gc-dec-pow-measurement-duration = <0x2000>;\n\t\t\t\tadi,gc-low-power-thresh = <0x18>;\n\t\t\t\tadi,mgc-inc-gain-step = <0x2>;\n\t\t\t\tadi,mgc-dec-gain-step = <0x2>;\n\t\t\t\tadi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;\n\t\t\t\tadi,agc-attack-delay-extra-margin-us = <0x1>;\n\t\t\t\tadi,agc-outer-thresh-high = <0x5>;\n\t\t\t\tadi,agc-outer-thresh-high-dec-steps = <0x2>;\n\t\t\t\tadi,agc-inner-thresh-high = <0xa>;\n\t\t\t\tadi,agc-inner-thresh-high-dec-steps = <0x1>;\n\t\t\t\tadi,agc-inner-thresh-low = <0xc>;\n\t\t\t\tadi,agc-inner-thresh-low-inc-steps = <0x1>;\n\t\t\t\tadi,agc-outer-thresh-low = <0x12>;\n\t\t\t\tadi,agc-outer-thresh-low-inc-steps = <0x2>;\n\t\t\t\tadi,agc-adc-small-overload-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-adc-large-overload-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-adc-large-overload-inc-steps = <0x7>;\n\t\t\t\tadi,agc-lmt-overload-large-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-lmt-overload-small-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-lmt-overload-large-inc-steps = <0x7>;\n\t\t\t\tadi,agc-gain-update-interval-us = <0x3e8>;\n\t\t\t\tadi,fagc-dec-pow-measurement-duration = <0x10>;\n        adi,fagc-adc-large-overload-inc-steps = <0x07>;\n\t\t\t\tadi,fagc-lp-thresh-increment-steps = <0x1>;\n\t\t\t\tadi,fagc-lp-thresh-increment-time = <0x5>;\n\t\t\t\tadi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;\n        adi,fagc-dig-sat-ovrg-enable;\n\t\t\t\tadi,fagc-final-overrange-count = <0x3>;\n\t\t\t\tadi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;\n\t\t\t\tadi,fagc-lmt-final-settling-steps = <0x1>;\n\t\t\t\tadi,fagc-lock-level = <0xa>;\n\t\t\t\tadi,fagc-lock-level-gain-increase-upper-limit = <0x5>;\n\t\t\t\tadi,fagc-lock-level-lmt-gain-increase-enable;\n\t\t\t\tadi,fagc-lpf-final-settling-steps = <0x1>;\n\t\t\t\tadi,fagc-optimized-gain-offset = <0x5>;\n\t\t\t\tadi,fagc-power-measurement-duration-in-state5 = <0x10>;\n\t\t\t\tadi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;\n\t\t\t\tadi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;\n\t\t\t\tadi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;\n\t\t\t\tadi,fagc-rst-gla-large-adc-overload-enable;\n\t\t\t\tadi,fagc-rst-gla-large-lmt-overload-enable;\n\t\t\t\tadi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;\n\t\t\t\tadi,fagc-state-wait-time-ns = <0x104>;\n\t\t\t\tadi,fagc-use-last-lock-level-for-set-gain-enable;\n\t\t\t\tadi,rssi-restart-mode = <0x3>;\n\t\t\t\tadi,rssi-delay = <0x1>;\n\t\t\t\tadi,rssi-wait = <0x1>;\n\t\t\t\tadi,rssi-duration = <0x3e8>;\n\t\t\t\tadi,ctrl-outs-index = <0x0>;\n\t\t\t\tadi,ctrl-outs-enable-mask = <0xff>;\n\t\t\t\tadi,temp-sense-measurement-interval-ms = <0x3e8>;\n\t\t\t\tadi,temp-sense-offset-signed = <0xce>;\n\t\t\t\tadi,temp-sense-periodic-measurement-enable;\n\t\t\t\tadi,aux-dac-manual-mode-enable;\n\t\t\t\tadi,aux-dac1-default-value-mV = <0x0>;\n\t\t\t\tadi,aux-dac1-rx-delay-us = <0x0>;\n\t\t\t\tadi,aux-dac1-tx-delay-us = <0x0>;\n\t\t\t\tadi,aux-dac2-default-value-mV = <0x0>;\n\t\t\t\tadi,aux-dac2-rx-delay-us = <0x0>;\n\t\t\t\tadi,aux-dac2-tx-delay-us = <0x0>;\n\t\t\t\ten_agc-gpios = <0x6 0x62 0x0>;\n\t\t\t\tsync-gpios = <0x6 0x63 0x0>;\n\t\t\t\treset-gpios = <0x6 0x64 0x0>;\n\t\t\t\tenable-gpios = <0x6 0x65 0x0>;\n\t\t\t\ttxnrx-gpios = <0x6 0x66 0x0>;\n\t\t\t\tlinux,phandle = <0xb>;\n\t\t\t\tphandle = <0xb>;\n\t\t\t};\n\t\t};\n\n\t\tspi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x31 0x4>;\n\t\t\tclocks = <0x2 0x1a 0x2 0x23>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t};\n\n\t\tspi@e000d000 {\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tclocks = <0x2 0xa 0x2 0x2b>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x13 0x4>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\tis-dual = <0x0>;\n\t\t\tnum-cs = <0x1>;\n\n\t\t\tps7-qspi@0 {\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t\tspi-tx-bus-width = <0x1>;\n\t\t\t\tspi-rx-bus-width = <0x4>;\n\t\t\t\tcompatible = \"n25q256a\", \"jedec,spi-nor\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tspi-max-frequency = <0x2faf080>;\n\n\t\t\t\tpartition@qspi-fsbl-uboot {\n\t\t\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\t\t\treg = <0x0 0xe0000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-uboot-env {\n\t\t\t\t\tlabel = \"qspi-uboot-env\";\n\t\t\t\t\treg = <0xe0000 0x20000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-linux {\n\t\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\t\treg = <0x100000 0x500000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-device-tree {\n\t\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\t\treg = <0x600000 0x20000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-rootfs {\n\t\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\t\treg = <0x620000 0xce0000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@qspi-bitstream {\n\t\t\t\t\tlabel = \"qspi-bitstream\";\n\t\t\t\t\treg = <0x1300000 0xd00000>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tmemory-controller@e000e000 {\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x1>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"aclk\";\n\t\t\tclocks = <0x2 0xb 0x2 0x2c>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x12 0x4>;\n\t\t\tranges;\n\t\t\treg = <0xe000e000 0x1000>;\n\n\t\t\tflash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\n\t\t\tflash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x2000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\t\t};\n\n\t\tethernet@e000b000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupts = <0x0 0x16 0x4>;\n\t\t\tclocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\tphy-handle = <0x7>;\n\t\t\tphy-mode = \"rgmii-id\";\n\n\t\t\tphy@0 {\n\t\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tmarvell,reg-init = <0x3 0x10 0xff00 0x1e 0x3 0x11 0xfff0 0x0>;\n\t\t\t\tlinux,phandle = <0x7>;\n\t\t\t\tphandle = <0x7>;\n\t\t\t};\n\t\t};\n\n \n\t\tethernet@e000c000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupts = <0x0 0x2d 0x4>;\n\t\t\tclocks = <0x2 0x1f 0x2 0x1f 0x2 0xe>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\tphy-mode = \"gmii\";\n\t\t\tphy-handle = <&phy1>;\n\n\t\t\tphy1: phy@0{\n\t\t\t\treg = <0>; \n\t\t\t};\t\n\t\t};\n \n \n\t\tmmc@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <0x2 0x15 0x2 0x20>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x18 0x4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t\tdisable-wp;\n\t\t};\n\n\t\tmmc@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <0x2 0x16 0x2 0x21>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x2f 0x4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t};\n\n\t\tslcr@f8000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\", \"simple-mfd\";\n\t\t\treg = <0xf8000000 0x1000>;\n\t\t\tranges;\n\t\t\tlinux,phandle = <0x8>;\n\t\t\tphandle = <0x8>;\n\n\t\t\tclkc@100 {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <0x1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\", \"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\", \"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\", \"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\", \"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\", \"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\", \"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\", \"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\", \"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\", \"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t\tps-clk-frequency = <0x1fca055>;\n\t\t\t\tlinux,phandle = <0x2>;\n\t\t\t\tphandle = <0x2>;\n\t\t\t};\n\n\t\t\trstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <0x1>;\n\t\t\t\tsyscon = <0x8>;\n\t\t\t};\n\n\t\t\tpinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <0x8>;\n\t\t\t};\n\t\t};\n\n\t\tdmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\", \"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\tinterrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>;\n\t\t\t#dma-cells = <0x1>;\n\t\t\t#dma-channels = <0x8>;\n\t\t\t#dma-requests = <0x4>;\n\t\t\tclocks = <0x2 0x1b>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t};\n\n\t\tdevcfg@f8007000 {\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x8 0x4>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tclocks = <0x2 0xc 0x2 0xf 0x2 0x10 0x2 0x11 0x2 0x12>;\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tsyscon = <0x8>;\n\t\t\tlinux,phandle = <0x4>;\n\t\t\tphandle = <0x4>;\n\t\t};\n\n\t\tefuse@f800d000 {\n\t\t\tcompatible = \"xlnx,zynq-efuse\";\n\t\t\treg = <0xf800d000 0x20>;\n\t\t};\n\n\t\ttimer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <0x1 0xb 0x301>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tclocks = <0x2 0x4>;\n\t\t};\n\n\t\ttimer@f8001000 {\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <0x2 0x6>;\n\t\t\treg = <0xf8001000 0x1000>;\n\t\t};\n\n\t\ttimer@f8002000 {\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <0x2 0x6>;\n\t\t\treg = <0xf8002000 0x1000>;\n\t\t};\n\n\t\ttimer@f8f00600 {\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x1 0xd 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <0x2 0x4>;\n\t\t};\n\n\t\tusb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"okay\";\n\t\t\tclocks = <0x2 0x1c>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x15 0x4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t\tdr_mode = \"host\";\n\t\t\txlnx,phy-reset-gpio = <0x6 0x7 0x0>;\n\t\t};\n\n\t\tusb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x1d>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x2c 0x4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog@f8005000 {\n\t\t\tclocks = <0x2 0x2d>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x9 0x1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <0xa>;\n\t\t};\n\t};\n\n\taliases {\n\t\tethernet0 = \"/amba/ethernet@e000b000\";\n\t\tserial0 = \"/amba/serial@e0001000\";\n\t};\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x40000000>;\n\t};\n\n\tchosen {\n\t\tlinux,stdout-path = \"/amba@0/uart@E0001000\";\n\t};\n\n\tclocks {\n\n\t\tclock@0 {\n\t\t\t#clock-cells = <0x0>;\n\t\t\tcompatible = \"adjustable-clock\";\n\t\t\tclock-frequency = <0x2625a00>;\n\t\t\tclock-accuracy = <0x30d40>;\n\t\t\tclock-output-names = \"ad9364_ext_refclk\";\n\t\t\tlinux,phandle = <0x5>;\n\t\t\tphandle = <0x5>;\n\t\t};\n\n\t\tclock@1 {\n\t\t\t#clock-cells = <0x0>;\n\t\t\tcompatible = \"fixed-clock\";\n\t\t\tclock-frequency = <0x16e3600>;\n\t\t\tclock-output-names = \"24MHz\";\n\t\t\tlinux,phandle = <0x9>;\n\t\t\tphandle = <0x9>;\n\t\t};\n\t};\n\n\tusb-ulpi-gpio-gate@0 {\n\t\tcompatible = \"gpio-gate-clock\";\n\t\tclocks = <0x9>;\n\t\t#clock-cells = <0x0>;\n\t\tenable-gpios = <0x6 0x9 0x1>;\n\t};\n\n\tfpga-axi@0 {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tranges;\n\n\t\ti2c@41600000 {\n\t\t\tcompatible = \"xlnx,axi-iic-1.02.a\", \"xlnx,xps-iic-2.00.a\";\n\t\t\treg = <0x41600000 0x10000>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x3a 0x4>;\n\t\t\tclocks = <0x2 0xf>;\n\t\t\tclock-names = \"pclk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\n\t\t\tad7291@20 {\n\t\t\t\tcompatible = \"adi,ad7291\";\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tad7291-bob@2C {\n\t\t\t\tcompatible = \"adi,ad7291\";\n\t\t\t\treg = <0x2c>;\n\t\t\t};\n\n\t\t\teeprom@50 {\n\t\t\t\tcompatible = \"at24,24c32\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\n\t\t// dma@7c400000 {\n\t\t// \tcompatible = \"adi,axi-dmac-1.00.a\";\n\t\t// \treg = <0x7c400000 0x10000>;\n\t\t// \t#dma-cells = <0x1>;\n\t\t// \tinterrupts = <0x0 0x39 0x0>;\n\t\t// \tclocks = <0x2 0x10>;\n\t\t// \tlinux,phandle = <0xa>;\n\t\t// \tphandle = <0xa>;\n\n\t\t// \tadi,channels {\n\t\t// \t\t#size-cells = <0x0>;\n\t\t// \t\t#address-cells = <0x1>;\n\n\t\t// \t\tdma-channel@0 {\n\t\t// \t\t\treg = <0x0>;\n\t\t// \t\t\tadi,source-bus-width = <0x40>;\n\t\t// \t\t\tadi,source-bus-type = <0x2>;\n\t\t// \t\t\tadi,destination-bus-width = <0x40>;\n\t\t// \t\t\tadi,destination-bus-type = <0x0>;\n\t\t// \t\t};\n\t\t// \t};\n\t\t// };\n\n\t\t// dma@7c420000 {\n\t\t// \tcompatible = \"adi,axi-dmac-1.00.a\";\n\t\t// \treg = <0x7c420000 0x10000>;\n\t\t// \t#dma-cells = <0x1>;\n\t\t// \tinterrupts = <0x0 0x38 0x0>;\n\t\t// \tclocks = <0x2 0x10>;\n\t\t// \tlinux,phandle = <0xc>;\n\t\t// \tphandle = <0xc>;\n\n\t\t// \tadi,channels {\n\t\t// \t\t#size-cells = <0x0>;\n\t\t// \t\t#address-cells = <0x1>;\n\n\t\t// \t\tdma-channel@0 {\n\t\t// \t\t\treg = <0x0>;\n\t\t// \t\t\tadi,source-bus-width = <0x40>;\n\t\t// \t\t\tadi,source-bus-type = <0x0>;\n\t\t// \t\t\tadi,destination-bus-width = <0x40>;\n\t\t// \t\t\tadi,destination-bus-type = <0x2>;\n\t\t// \t\t};\n\t\t// \t};\n\t\t// };\n\n\t\tsdr: sdr {\n\t\t\tcompatible =\"sdr,sdr\";\n\t\t\tdmas = <&rx_dma 1\n\t\t\t\t\t&tx_dma 0>;\n\t\t\tdma-names = \"rx_dma_s2mm\", \"tx_dma_mm2s\";\n\t\t\tinterrupt-names = \"not_valid_anymore\", \"rx_pkt_intr\", \"tx_itrpt\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 29 1 0 30 1 0 33 1 0 34 1>;\n\t\t} ;\n\n\t\taxidmatest_1: axidmatest@1 {\n\t\t\tcompatible =\"xlnx,axi-dma-test-1.00.a\";\n\t\t\tdmas = <&rx_dma 0\n\t\t\t\t&rx_dma 1>;\n\t\t\tdma-names = \"axidma0\", \"axidma1\";\n\t\t} ;\n\n\t\ttx_dma: dma@80400000 {\n\t\t\t#dma-cells = <1>;\n\t\t\tclock-names = \"s_axi_lite_aclk\", \"m_axi_sg_aclk\", \"m_axi_mm2s_aclk\", \"m_axi_s2mm_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"xlnx,axi-dma-1.00.a\";\n\t\t\tinterrupt-names = \"mm2s_introut\", \"s2mm_introut\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 35 4 0 36 4>;\n\t\t\treg = <0x80400000 0x10000>;\n\t\t\txlnx,addrwidth = <0x20>;\n\t\t\txlnx,include-sg ;\n\t\t\txlnx,sg-length-width = <0xe>;\n\t\t\tdma-channel@80400000 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-mm2s-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 35 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x0>;\n\t\t\t};\n\t\t\tdma-channel@80400030 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-s2mm-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 36 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x0>;\n\t\t\t};\n\t\t};\n\t\t\n\t\trx_dma: dma@80410000 {\n\t\t\t#dma-cells = <1>;\n\t\t\tclock-names = \"s_axi_lite_aclk\", \"m_axi_sg_aclk\", \"m_axi_mm2s_aclk\", \"m_axi_s2mm_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"xlnx,axi-dma-1.00.a\";\n\t\t\t//dma-coherent ;\n\t\t\tinterrupt-names = \"mm2s_introut\", \"s2mm_introut\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 31 4 0 32 4>;\n\t\t\treg = <0x80410000 0x10000>;\n\t\t\txlnx,addrwidth = <0x20>;\n\t\t\txlnx,include-sg ;\n\t\t\txlnx,sg-length-width = <0xe>;\n\t\t\tdma-channel@80410000 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-mm2s-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 31 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x1>;\n\t\t\t};\n\t\t\tdma-channel@80410030 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-s2mm-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 32 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x1>;\n\t\t\t};\n\t\t};\n\n\t\ttx_intf_0: tx_intf@83c00000 {\n\t\t\tclock-names = \"s00_axi_aclk\", \"s00_axis_aclk\";//, \"s01_axis_aclk\", \"m00_axis_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"sdr,tx_intf\";\n\t\t\tinterrupt-names = \"tx_itrpt\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 34 1>;\n\t\t\treg = <0x83c00000 0x10000>;\n\t\t\txlnx,s00-axi-addr-width = <0x7>;\n\t\t\txlnx,s00-axi-data-width = <0x20>;\n\t\t};\n\n\t\trx_intf_0: rx_intf@83c20000 {\n\t\t\tclock-names = \"s00_axi_aclk\", \"m00_axis_aclk\";//, \"s00_axis_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>;\n\t\t\tcompatible = \"sdr,rx_intf\";\n\t\t\tinterrupt-names = \"not_valid_anymore\", \"rx_pkt_intr\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 29 1 0 30 1>;\n\t\t\treg = <0x83c20000 0x10000>;\n\t\t\txlnx,s00-axi-addr-width = <0x7>;\n\t\t\txlnx,s00-axi-data-width = <0x20>;\n\t\t};\n\n\t\topenofdm_tx_0: openofdm_tx@83c10000 {\n\t\t\tclock-names = \"clk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,openofdm_tx\";\n\t\t\treg = <0x83c10000 0x10000>;\n\t\t};\n\n\t\topenofdm_rx_0: openofdm_rx@83c30000 {\n\t\t\tclock-names = \"clk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,openofdm_rx\";\n\t\t\treg = <0x83c30000 0x10000>;\n\t\t};\n\n\t\txpu_0: xpu@83c40000 {\n\t\t\tclock-names = \"s00_axi_aclk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,xpu\";\n\t\t\treg = <0x83c40000 0x10000>;\n\t\t};\n\n\t\tside_ch_0: side_ch@83c50000 {\n\t\t\tclock-names = \"s00_axi_aclk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,side_ch\";\n\t\t\treg = <0x83c50000 0x10000>;\n\t\t\tdmas = <&rx_dma 0\n\t\t\t\t\t&tx_dma 1>;\n\t\t\tdma-names = \"rx_dma_mm2s\", \"tx_dma_s2mm\";\n\t\t};\n\n\t\tcf-ad9361-lpc@79020000 {\n\t\t\tcompatible = \"adi,axi-ad9361-6.00.a\";\n\t\t\treg = <0x79020000 0x6000>;\n\t\t\t// dmas = <0xa 0x0>;\n\t\t\t// dma-names = \"rx\";\n\t\t\tspibus-connected = <0xb>;\n\t\t};\n\n\t\tcf-ad9361-dds-core-lpc@79024000 {\n\t\t\tcompatible = \"adi,axi-ad9361-dds-6.00.a\";\n\t\t\treg = <0x79024000 0x1000>;\n\t\t\tclocks = <0xb 0xd>;\n\t\t\tclock-names = \"sampl_clk\";\n\t\t\t// dmas = <0xc 0x0>;\n\t\t\t// dma-names = \"tx\";\n\t\t};\n\n\t\tmwipcore@43c00000 {\n\t\t\tcompatible = \"mathworks,mwipcore-axi4lite-v1.00\";\n\t\t\treg = <0x43c00000 0xffff>;\n\t\t};\n\n\t\t/*axi-sysid-0@45000000 {\n\t\t\tcompatible = \"adi,axi-sysid-1.00.a\";\n\t\t\treg = <0x45000000 0x10000>;\n\t\t};*/\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled0 {\n\t\t\tlabel = \"led0:green\";\n\t\t\tgpios = <0x6 0xF 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n//\tgpio_keys {\n//\t\tcompatible = \"gpio-keys\";\n//\t\t#address-cells = <0x1>;\n//\t\t#size-cells = <0x0>;\n//\t\tautorepeat;\n//\n//\t\tsw1 {\n//\t\t\tlabel = \"SW1\";\n//\t\t\tlinux,input-type = <0x5>;\n//\t\t\tlinux,code = <0x3>;\n//\t\t\tgpios = <0x6 0xE 0x0>;\n//\t\t};\n//\t};\n};\n"
  },
  {
    "path": "kernel_boot/boards/sdrpi/notes.md",
    "content": "# sdrpi for openwifi\n\n## Introduction\n[SDRPi](https://github.com/hexsdr/) is a smart and powerful SDR platform according Raspberry Pi size,which is based on [xilinx zynq7020](https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html) and [adi ad936x](https://www.analog.com/en/products/ad9361.html). \n\n\n\nHareware feature is : ZYNQ 7Z020CLG400 ,1GB DDR3 memory fo PS, 1G Ethernet RJ45 for PS,1G Ethernet RJ45 for PL, USB OTG(act as USB host or USB SLAVE ), dual USB uarts for PS and PL,on board USB to JTAG debuger,TF card , bootable QSPI FLASH and also external 27 IO pins from PL bank in 3.3v vatage with enable this board connect to other boards or modules. AD9361 RF design is based FMCOMMS3 with RF amplifier additionally.It also has a Ublox m8t GPS module and 40MHZ VCXO.\n\n\n\n\nIt could be used as a traditional SDR device such as PlutoSDR or FMCOMMS2/3/4 with Xilinx evaluation board, and it also be used as hardware platform to support openwifi.\n\n\n"
  },
  {
    "path": "kernel_boot/boards/zc702_fmcs2/devicetree.dts",
    "content": "/dts-v1/;\n\n/ {\n\t#address-cells = <0x01>;\n\t#size-cells = <0x01>;\n\tcompatible = \"xlnx,zynq-7000\";\n\tinterrupt-parent = <0x01>;\n\tmodel = \"Xilinx Zynq ZC702\";\n\n\tcpus {\n\t\t#address-cells = <0x01>;\n\t\t#size-cells = <0x00>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0x00>;\n\t\t\tclocks = <0x02 0x03>;\n\t\t\tclock-latency = <0x3e8>;\n\t\t\tcpu0-supply = <0x03>;\n\t\t\toperating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>;\n\t\t\tphandle = <0x12>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0x01>;\n\t\t\tclocks = <0x02 0x03>;\n\t\t\tphandle = <0x14>;\n\t\t};\n\t};\n\n\tfpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <0x04>;\n\t\t#address-cells = <0x01>;\n\t\t#size-cells = <0x01>;\n\t\tranges;\n\t\tphandle = <0x21>;\n\t};\n\n\tpmu@f8891000 {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0x00 0x05 0x04 0x00 0x06 0x04>;\n\t\tinterrupt-parent = <0x01>;\n\t\treg = <0xf8891000 0x1000 0xf8893000 0x1000>;\n\t};\n\n\tfixedregulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <0xf4240>;\n\t\tregulator-max-microvolt = <0xf4240>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t\tphandle = <0x03>;\n\t};\n\n\treplicator {\n\t\tcompatible = \"arm,coresight-static-replicator\";\n\t\tclocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;\n\t\tclock-names = \"apb_pclk\\0dbg_trc\\0dbg_apb\";\n\n\t\tout-ports {\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\n\t\t\tport@0 {\n\t\t\t\treg = <0x00>;\n\n\t\t\t\tendpoint {\n\t\t\t\t\tremote-endpoint = <0x05>;\n\t\t\t\t\tphandle = <0x0e>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tport@1 {\n\t\t\t\treg = <0x01>;\n\n\t\t\t\tendpoint {\n\t\t\t\t\tremote-endpoint = <0x06>;\n\t\t\t\t\tphandle = <0x0d>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tin-ports {\n\n\t\t\tport {\n\n\t\t\t\tendpoint {\n\t\t\t\t\tremote-endpoint = <0x07>;\n\t\t\t\t\tphandle = <0x0f>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\taxi {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x01>;\n\t\t#size-cells = <0x01>;\n\t\tinterrupt-parent = <0x01>;\n\t\tranges;\n\t\tphandle = <0x22>;\n\n\t\tadc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0x00 0x07 0x04>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tclocks = <0x02 0x0c>;\n\t\t\tphandle = <0x23>;\n\t\t};\n\n\t\tcan@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x02 0x13 0x02 0x24>;\n\t\t\tclock-names = \"can_clk\\0pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0x00 0x1c 0x04>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tphandle = <0x24>;\n\t\t};\n\n\t\tcan@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x02 0x14 0x02 0x25>;\n\t\t\tclock-names = \"can_clk\\0pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0x00 0x33 0x04>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tphandle = <0x25>;\n\t\t};\n\n\t\tgpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <0x02>;\n\t\t\tclocks = <0x02 0x2a>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <0x02>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x14 0x04>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t\tphandle = <0x09>;\n\t\t};\n\n\t\ti2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x02 0x26>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x19 0x04>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tphandle = <0x26>;\n\t\t};\n\n\t\ti2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x02 0x27>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x30 0x04>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tphandle = <0x27>;\n\t\t};\n\n\t\tinterrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <0x03>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xf8f01000 0x1000 0xf8f00100 0x100>;\n\t\t\tphandle = <0x01>;\n\t\t};\n\n\t\tcache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xf8f02000 0x1000>;\n\t\t\tinterrupts = <0x00 0x02 0x04>;\n\t\t\tarm,data-latency = <0x03 0x02 0x02>;\n\t\t\tarm,tag-latency = <0x02 0x02 0x02>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <0x02>;\n\t\t\tphandle = <0x28>;\n\t\t};\n\n\t\tmemory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t\tphandle = <0x29>;\n\t\t};\n\n\t\tocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x03 0x04>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t\tphandle = <0x2a>;\n\t\t};\n\n\t\tserial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\\0cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x02 0x17 0x02 0x28>;\n\t\t\tclock-names = \"uart_clk\\0pclk\";\n\t\t\treg = <0xe0000000 0x1000>;\n\t\t\tinterrupts = <0x00 0x1b 0x04>;\n\t\t\tphandle = <0x2b>;\n\t\t};\n\n\t\tserial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\\0cdns,uart-r1p8\";\n\t\t\tstatus = \"okay\";\n\t\t\tclocks = <0x02 0x18 0x02 0x29>;\n\t\t\tclock-names = \"uart_clk\\0pclk\";\n\t\t\treg = <0xe0001000 0x1000>;\n\t\t\tinterrupts = <0x00 0x32 0x04>;\n\t\t\tphandle = <0x2c>;\n\t\t};\n\n\t\tspi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x1a 0x04>;\n\t\t\tclocks = <0x02 0x19 0x02 0x22>;\n\t\t\tclock-names = \"ref_clk\\0pclk\";\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tphandle = <0x2d>;\n\n\t\t\tad9361-phy@0 {\n\t\t\t\tcompatible = \"adi,ad9361\";\n\t\t\t\treg = <0x00>;\n\t\t\t\tspi-cpha;\n\t\t\t\tspi-max-frequency = <0x989680>;\n\t\t\t\tclocks = <0x08 0x00>;\n\t\t\t\tclock-names = \"ad9361_ext_refclk\";\n\t\t\t\tclock-output-names = \"rx_sampl_clk\\0tx_sampl_clk\";\n\t\t\t\t#clock-cells = <0x01>;\n\t\t\t\tadi,digital-interface-tune-skip-mode = <0x00>;\n\t\t\t\tadi,pp-tx-swap-enable;\n\t\t\t\tadi,pp-rx-swap-enable;\n\t\t\t\tadi,rx-frame-pulse-mode-enable;\n\t\t\t\tadi,lvds-mode-enable;\n\t\t\t\tadi,lvds-bias-mV = <0x96>;\n\t\t\t\tadi,lvds-rx-onchip-termination-enable;\n\t\t\t\tadi,rx-data-delay = <0x04>;\n\t\t\t\tadi,tx-fb-clock-delay = <0x07>;\n\t\t\t\tadi,dcxo-coarse-and-fine-tune = <0x08 0x1720>;\n\t\t\t\tadi,2rx-2tx-mode-enable;\n\t\t\t\tadi,frequency-division-duplex-mode-enable;\n\t\t\t\tadi,rx-rf-port-input-select = <0x00>;\n\t\t\t\tadi,tx-rf-port-input-select = <0x00>;\n\t\t\t\tadi,tx-attenuation-mdB = <0x2710>;\n\t\t\t\tadi,tx-lo-powerdown-managed-enable;\n\t\t\t\tadi,rf-rx-bandwidth-hz = <0x112a880>;\n\t\t\t\tadi,rf-tx-bandwidth-hz = <0x112a880>;\n\t\t\t\tadi,rx-synthesizer-frequency-hz = <0x00 0x8f0d1800>;\n\t\t\t\tadi,tx-synthesizer-frequency-hz = <0x00 0x92080880>;\n\t\t\t\tadi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;\n\t\t\t\tadi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;\n\t\t\t\tadi,gc-rx1-mode = <0x02>;\n\t\t\t\tadi,gc-rx2-mode = <0x02>;\n\t\t\t\tadi,gc-adc-ovr-sample-size = <0x04>;\n\t\t\t\tadi,gc-adc-small-overload-thresh = <0x2f>;\n\t\t\t\tadi,gc-adc-large-overload-thresh = <0x3a>;\n\t\t\t\tadi,gc-lmt-overload-high-thresh = <0x320>;\n\t\t\t\tadi,gc-lmt-overload-low-thresh = <0x2c0>;\n\t\t\t\tadi,gc-dec-pow-measurement-duration = <0x2000>;\n\t\t\t\tadi,gc-low-power-thresh = <0x18>;\n\t\t\t\tadi,mgc-inc-gain-step = <0x02>;\n\t\t\t\tadi,mgc-dec-gain-step = <0x02>;\n\t\t\t\tadi,mgc-split-table-ctrl-inp-gain-mode = <0x00>;\n\t\t\t\tadi,agc-attack-delay-extra-margin-us = <0x01>;\n\t\t\t\tadi,agc-outer-thresh-high = <0x05>;\n\t\t\t\tadi,agc-outer-thresh-high-dec-steps = <0x02>;\n\t\t\t\tadi,agc-inner-thresh-high = <0x0a>;\n\t\t\t\tadi,agc-inner-thresh-high-dec-steps = <0x01>;\n\t\t\t\tadi,agc-inner-thresh-low = <0x0c>;\n\t\t\t\tadi,agc-inner-thresh-low-inc-steps = <0x01>;\n\t\t\t\tadi,agc-outer-thresh-low = <0x12>;\n\t\t\t\tadi,agc-outer-thresh-low-inc-steps = <0x02>;\n\t\t\t\tadi,agc-adc-small-overload-exceed-counter = <0x0a>;\n\t\t\t\tadi,agc-adc-large-overload-exceed-counter = <0x0a>;\n\t\t\t\tadi,agc-adc-large-overload-inc-steps = <0x07>;\n\t\t\t\tadi,agc-lmt-overload-large-exceed-counter = <0x0a>;\n\t\t\t\tadi,agc-lmt-overload-small-exceed-counter = <0x0a>;\n\t\t\t\tadi,agc-lmt-overload-large-inc-steps = <0x07>;\n\t\t\t\tadi,agc-gain-update-interval-us = <0x3e8>;\n\t\t\t\tadi,fagc-dec-pow-measurement-duration = <0x10>;\n        adi,fagc-adc-large-overload-inc-steps = <0x07>;\n\t\t\t\tadi,fagc-lp-thresh-increment-steps = <0x01>;\n\t\t\t\tadi,fagc-lp-thresh-increment-time = <0x05>;\n\t\t\t\tadi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x08>;\n        adi,fagc-dig-sat-ovrg-enable;\n\t\t\t\tadi,fagc-final-overrange-count = <0x03>;\n\t\t\t\tadi,fagc-gain-index-type-after-exit-rx-mode = <0x00>;\n\t\t\t\tadi,fagc-lmt-final-settling-steps = <0x01>;\n\t\t\t\tadi,fagc-lock-level = <0x0a>;\n\t\t\t\tadi,fagc-lock-level-gain-increase-upper-limit = <0x05>;\n\t\t\t\tadi,fagc-lock-level-lmt-gain-increase-enable;\n\t\t\t\tadi,fagc-lpf-final-settling-steps = <0x01>;\n\t\t\t\tadi,fagc-optimized-gain-offset = <0x05>;\n\t\t\t\tadi,fagc-power-measurement-duration-in-state5 = <0x10>;\n\t\t\t\tadi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;\n\t\t\t\tadi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0x0a>;\n\t\t\t\tadi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x00>;\n\t\t\t\tadi,fagc-rst-gla-large-adc-overload-enable;\n\t\t\t\tadi,fagc-rst-gla-large-lmt-overload-enable;\n\t\t\t\tadi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0x0a>;\n\t\t\t\tadi,fagc-state-wait-time-ns = <0x104>;\n\t\t\t\tadi,fagc-use-last-lock-level-for-set-gain-enable;\n\t\t\t\tadi,rssi-restart-mode = <0x03>;\n\t\t\t\tadi,rssi-delay = <0x01>;\n\t\t\t\tadi,rssi-wait = <0x01>;\n\t\t\t\tadi,rssi-duration = <0x3e8>;\n\t\t\t\tadi,ctrl-outs-index = <0x00>;\n\t\t\t\tadi,ctrl-outs-enable-mask = <0xff>;\n\t\t\t\tadi,temp-sense-measurement-interval-ms = <0x3e8>;\n\t\t\t\tadi,temp-sense-offset-signed = <0xce>;\n\t\t\t\tadi,temp-sense-periodic-measurement-enable;\n\t\t\t\tadi,aux-dac-manual-mode-enable;\n\t\t\t\tadi,aux-dac1-default-value-mV = <0x00>;\n\t\t\t\tadi,aux-dac1-rx-delay-us = <0x00>;\n\t\t\t\tadi,aux-dac1-tx-delay-us = <0x00>;\n\t\t\t\tadi,aux-dac2-default-value-mV = <0x00>;\n\t\t\t\tadi,aux-dac2-rx-delay-us = <0x00>;\n\t\t\t\tadi,aux-dac2-tx-delay-us = <0x00>;\n\t\t\t\ten_agc-gpios = <0x09 0x62 0x00>;\n\t\t\t\tsync-gpios = <0x09 0x63 0x00>;\n\t\t\t\treset-gpios = <0x09 0x64 0x00>;\n\t\t\t\tenable-gpios = <0x09 0x65 0x00>;\n\t\t\t\ttxnrx-gpios = <0x09 0x66 0x00>;\n\t\t\t\tphandle = <0x1d>;\n\t\t\t};\n\t\t};\n\n\t\tspi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x31 0x04>;\n\t\t\tclocks = <0x02 0x1a 0x02 0x23>;\n\t\t\tclock-names = \"ref_clk\\0pclk\";\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tphandle = <0x2e>;\n\n\t\t\tadf4351-udc-tx-pmod@0 {\n\t\t\t\tcompatible = \"adi,adf4351\";\n\t\t\t\treg = <0x00>;\n\t\t\t\tspi-max-frequency = <0x989680>;\n\t\t\t\tclocks = <0x0a>;\n\t\t\t\tclock-names = \"clkin\";\n\t\t\t\tadi,channel-spacing = <0xf4240>;\n\t\t\t\tadi,power-up-frequency = <0x160dc080>;\n\t\t\t\tadi,phase-detector-polarity-positive-enable;\n\t\t\t\tadi,charge-pump-current = <0x9c4>;\n\t\t\t\tadi,output-power = <0x03>;\n\t\t\t\tadi,mute-till-lock-enable;\n\t\t\t\tadi,muxout-select = <0x06>;\n\t\t\t\tgpios = <0x09 0x68 0x00>;\n\t\t\t\tphandle = <0x2f>;\n\t\t\t};\n\n\t\t\tadf4351-udc-rx-pmod@1 {\n\t\t\t\tcompatible = \"adi,adf4351\";\n\t\t\t\treg = <0x01>;\n\t\t\t\tspi-max-frequency = <0x989680>;\n\t\t\t\tclocks = <0x0a>;\n\t\t\t\tclock-names = \"clkin\";\n\t\t\t\tadi,channel-spacing = <0xf4240>;\n\t\t\t\tadi,power-up-frequency = <0x1443fd00>;\n\t\t\t\tadi,phase-detector-polarity-positive-enable;\n\t\t\t\tadi,charge-pump-current = <0x9c4>;\n\t\t\t\tadi,output-power = <0x03>;\n\t\t\t\tadi,mute-till-lock-enable;\n\t\t\t\tadi,muxout-select = <0x06>;\n\t\t\t\tgpios = <0x09 0x67 0x00>;\n\t\t\t\tphandle = <0x30>;\n\t\t\t};\n\t\t};\n\n\t\tspi@e000d000 {\n\t\t\tclock-names = \"ref_clk\\0pclk\";\n\t\t\tclocks = <0x02 0x0a 0x02 0x2b>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x13 0x04>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tis-dual = <0x00>;\n\t\t\tnum-cs = <0x01>;\n\t\t\tphandle = <0x31>;\n\n\t\t\tps7-qspi@0 {\n\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t#size-cells = <0x01>;\n\t\t\t\tcompatible = \"n25q128a11\";\n\t\t\t\treg = <0x00>;\n\t\t\t\tspi-tx-bus-width = <0x01>;\n\t\t\t\tspi-rx-bus-width = <0x04>;\n\t\t\t\tspi-max-frequency = <0x2faf080>;\n\t\t\t\tphandle = <0x32>;\n\n\t\t\t\tpartition@0 {\n\t\t\t\t\tlabel = \"boot\";\n\t\t\t\t\treg = <0x00 0x500000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@500000 {\n\t\t\t\t\tlabel = \"bootenv\";\n\t\t\t\t\treg = <0x500000 0x20000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@520000 {\n\t\t\t\t\tlabel = \"config\";\n\t\t\t\t\treg = <0x520000 0x20000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@540000 {\n\t\t\t\t\tlabel = \"image\";\n\t\t\t\t\treg = <0x540000 0xa80000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@fc0000 {\n\t\t\t\t\tlabel = \"spare\";\n\t\t\t\t\treg = <0xfc0000 0x00>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tmemory-controller@e000e000 {\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x01>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\\0apb_pclk\";\n\t\t\tclocks = <0x02 0x0b 0x02 0x2c>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\\0arm,primecell\";\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x12 0x04>;\n\t\t\tranges;\n\t\t\treg = <0xe000e000 0x1000>;\n\t\t\tphandle = <0x33>;\n\n\t\t\tflash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t#size-cells = <0x01>;\n\t\t\t\tphandle = <0x34>;\n\t\t\t};\n\n\t\t\tflash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x2000000>;\n\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t#size-cells = <0x01>;\n\t\t\t\tphandle = <0x35>;\n\t\t\t};\n\t\t};\n\n\t\tethernet@e000b000 {\n\t\t\tcompatible = \"cdns,zynq-gem\\0cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupts = <0x00 0x16 0x04>;\n\t\t\tclocks = <0x02 0x1e 0x02 0x1e 0x02 0x0d>;\n\t\t\tclock-names = \"pclk\\0hclk\\0tx_clk\";\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tphy-handle = <0x0b>;\n\t\t\tphy-mode = \"rgmii-id\";\n\t\t\tphandle = <0x36>;\n\n\t\t\tphy@7 {\n\t\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\t\treg = <0x07>;\n\t\t\t\tphandle = <0x0b>;\n\t\t\t};\n\t\t};\n\n\t\tethernet@e000c000 {\n\t\t\tcompatible = \"cdns,zynq-gem\\0cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0x00 0x2d 0x04>;\n\t\t\tclocks = <0x02 0x1f 0x02 0x1f 0x02 0x0e>;\n\t\t\tclock-names = \"pclk\\0hclk\\0tx_clk\";\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tphandle = <0x37>;\n\t\t};\n\n\t\tmmc@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"clk_xin\\0clk_ahb\";\n\t\t\tclocks = <0x02 0x15 0x02 0x20>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x18 0x04>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t\tphandle = <0x38>;\n\t\t};\n\n\t\tmmc@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\\0clk_ahb\";\n\t\t\tclocks = <0x02 0x16 0x02 0x21>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x2f 0x04>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t\tphandle = <0x39>;\n\t\t};\n\n\t\tslcr@f8000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x01>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\\0syscon\\0simple-mfd\";\n\t\t\treg = <0xf8000000 0x1000>;\n\t\t\tranges;\n\t\t\tphandle = <0x0c>;\n\n\t\t\tclkc@100 {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <0x01>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0x0f>;\n\t\t\t\tclock-output-names = \"armpll\\0ddrpll\\0iopll\\0cpu_6or4x\\0cpu_3or2x\\0cpu_2x\\0cpu_1x\\0ddr2x\\0ddr3x\\0dci\\0lqspi\\0smc\\0pcap\\0gem0\\0gem1\\0fclk0\\0fclk1\\0fclk2\\0fclk3\\0can0\\0can1\\0sdio0\\0sdio1\\0uart0\\0uart1\\0spi0\\0spi1\\0dma\\0usb0_aper\\0usb1_aper\\0gem0_aper\\0gem1_aper\\0sdio0_aper\\0sdio1_aper\\0spi0_aper\\0spi1_aper\\0can0_aper\\0can1_aper\\0i2c0_aper\\0i2c1_aper\\0uart0_aper\\0uart1_aper\\0gpio_aper\\0lqspi_aper\\0smc_aper\\0swdt\\0dbg_trc\\0dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t\tps-clk-frequency = <0x1fca055>;\n\t\t\t\tphandle = <0x02>;\n\t\t\t};\n\n\t\t\trstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <0x01>;\n\t\t\t\tsyscon = <0x0c>;\n\t\t\t\tphandle = <0x3a>;\n\t\t\t};\n\n\t\t\tpinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <0x0c>;\n\t\t\t\tphandle = <0x3b>;\n\t\t\t};\n\t\t};\n\n\t\tdmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\\0arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupt-names = \"abort\\0dma0\\0dma1\\0dma2\\0dma3\\0dma4\\0dma5\\0dma6\\0dma7\";\n\t\t\tinterrupts = <0x00 0x0d 0x04 0x00 0x0e 0x04 0x00 0x0f 0x04 0x00 0x10 0x04 0x00 0x11 0x04 0x00 0x28 0x04 0x00 0x29 0x04 0x00 0x2a 0x04 0x00 0x2b 0x04>;\n\t\t\t#dma-cells = <0x01>;\n\t\t\t#dma-channels = <0x08>;\n\t\t\t#dma-requests = <0x04>;\n\t\t\tclocks = <0x02 0x1b>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t\tphandle = <0x1a>;\n\t\t};\n\n\t\tdevcfg@f8007000 {\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x08 0x04>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tclocks = <0x02 0x0c 0x02 0x0f 0x02 0x10 0x02 0x11 0x02 0x12>;\n\t\t\tclock-names = \"ref_clk\\0fclk0\\0fclk1\\0fclk2\\0fclk3\";\n\t\t\tsyscon = <0x0c>;\n\t\t\tphandle = <0x04>;\n\t\t};\n\n\t\tefuse@f800d000 {\n\t\t\tcompatible = \"xlnx,zynq-efuse\";\n\t\t\treg = <0xf800d000 0x20>;\n\t\t\tphandle = <0x3c>;\n\t\t};\n\n\t\ttimer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <0x01 0x0b 0x301>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tclocks = <0x02 0x04>;\n\t\t\tphandle = <0x3d>;\n\t\t};\n\n\t\ttimer@f8001000 {\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x0a 0x04 0x00 0x0b 0x04 0x00 0x0c 0x04>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <0x02 0x06>;\n\t\t\treg = <0xf8001000 0x1000>;\n\t\t\tphandle = <0x3e>;\n\t\t};\n\n\t\ttimer@f8002000 {\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x25 0x04 0x00 0x26 0x04 0x00 0x27 0x04>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <0x02 0x06>;\n\t\t\treg = <0xf8002000 0x1000>;\n\t\t\tphandle = <0x3f>;\n\t\t};\n\n\t\ttimer@f8f00600 {\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x01 0x0d 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <0x02 0x04>;\n\t\t\tphandle = <0x40>;\n\t\t};\n\n\t\tusb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\\0chipidea,usb2\";\n\t\t\tstatus = \"okay\";\n\t\t\tclocks = <0x02 0x1c>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x15 0x04>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t\tdr_mode = \"host\";\n\t\t\txlnx,phy-reset-gpio = <0x09 0x07 0x00>;\n\t\t\tphandle = <0x41>;\n\t\t};\n\n\t\tusb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\\0chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x02 0x1d>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x2c 0x04>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t\tphandle = <0x42>;\n\t\t};\n\n\t\twatchdog@f8005000 {\n\t\t\tclocks = <0x02 0x2d>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x09 0x01>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <0x0a>;\n\t\t\tphandle = <0x43>;\n\t\t};\n\n\t\tetb@f8801000 {\n\t\t\tcompatible = \"arm,coresight-etb10\\0arm,primecell\";\n\t\t\treg = <0xf8801000 0x1000>;\n\t\t\tclocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;\n\t\t\tclock-names = \"apb_pclk\\0dbg_trc\\0dbg_apb\";\n\n\t\t\tin-ports {\n\n\t\t\t\tport {\n\n\t\t\t\t\tendpoint {\n\t\t\t\t\t\tremote-endpoint = <0x0d>;\n\t\t\t\t\t\tphandle = <0x06>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\ttpiu@f8803000 {\n\t\t\tcompatible = \"arm,coresight-tpiu\\0arm,primecell\";\n\t\t\treg = <0xf8803000 0x1000>;\n\t\t\tclocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;\n\t\t\tclock-names = \"apb_pclk\\0dbg_trc\\0dbg_apb\";\n\n\t\t\tin-ports {\n\n\t\t\t\tport {\n\n\t\t\t\t\tendpoint {\n\t\t\t\t\t\tremote-endpoint = <0x0e>;\n\t\t\t\t\t\tphandle = <0x05>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tfunnel@f8804000 {\n\t\t\tcompatible = \"arm,coresight-static-funnel\\0arm,primecell\";\n\t\t\treg = <0xf8804000 0x1000>;\n\t\t\tclocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;\n\t\t\tclock-names = \"apb_pclk\\0dbg_trc\\0dbg_apb\";\n\n\t\t\tout-ports {\n\n\t\t\t\tport {\n\n\t\t\t\t\tendpoint {\n\t\t\t\t\t\tremote-endpoint = <0x0f>;\n\t\t\t\t\t\tphandle = <0x07>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tin-ports {\n\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t#size-cells = <0x00>;\n\n\t\t\t\tport@0 {\n\t\t\t\t\treg = <0x00>;\n\n\t\t\t\t\tendpoint {\n\t\t\t\t\t\tremote-endpoint = <0x10>;\n\t\t\t\t\t\tphandle = <0x13>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tport@1 {\n\t\t\t\t\treg = <0x01>;\n\n\t\t\t\t\tendpoint {\n\t\t\t\t\t\tremote-endpoint = <0x11>;\n\t\t\t\t\t\tphandle = <0x15>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tport@2 {\n\t\t\t\t\treg = <0x02>;\n\n\t\t\t\t\tendpoint {\n\t\t\t\t\t\tphandle = <0x44>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tptm@f889c000 {\n\t\t\tcompatible = \"arm,coresight-etm3x\\0arm,primecell\";\n\t\t\treg = <0xf889c000 0x1000>;\n\t\t\tclocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;\n\t\t\tclock-names = \"apb_pclk\\0dbg_trc\\0dbg_apb\";\n\t\t\tcpu = <0x12>;\n\n\t\t\tout-ports {\n\n\t\t\t\tport {\n\n\t\t\t\t\tendpoint {\n\t\t\t\t\t\tremote-endpoint = <0x13>;\n\t\t\t\t\t\tphandle = <0x10>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tptm@f889d000 {\n\t\t\tcompatible = \"arm,coresight-etm3x\\0arm,primecell\";\n\t\t\treg = <0xf889d000 0x1000>;\n\t\t\tclocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;\n\t\t\tclock-names = \"apb_pclk\\0dbg_trc\\0dbg_apb\";\n\t\t\tcpu = <0x14>;\n\n\t\t\tout-ports {\n\n\t\t\t\tport {\n\n\t\t\t\t\tendpoint {\n\t\t\t\t\t\tremote-endpoint = <0x15>;\n\t\t\t\t\t\tphandle = <0x11>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\taliases {\n\t\tethernet0 = \"/axi/ethernet@e000b000\";\n\t\tserial0 = \"/axi/serial@e0001000\";\n\t\tphandle = <0x45>;\n\t};\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x00 0x40000000>;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait\";\n\t\tstdout-path = \"/amba@0/uart@E0001000\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tds12 {\n\t\t\tlabel = \"ds12:green\";\n\t\t\tgpios = <0x09 0x08 0x00>;\n\t\t};\n\n\t\tds15 {\n\t\t\tlabel = \"ds15:green\";\n\t\t\tgpios = <0x09 0x3a 0x00>;\n\t\t};\n\n\t\tds16 {\n\t\t\tlabel = \"ds16:green\";\n\t\t\tgpios = <0x09 0x3b 0x00>;\n\t\t};\n\n\t\tds17 {\n\t\t\tlabel = \"ds17:green\";\n\t\t\tgpios = <0x09 0x3c 0x00>;\n\t\t};\n\n\t\tds18 {\n\t\t\tlabel = \"ds18:green\";\n\t\t\tgpios = <0x09 0x3d 0x00>;\n\t\t};\n\n\t\tds19 {\n\t\t\tlabel = \"ds19:green\";\n\t\t\tgpios = <0x09 0x3e 0x00>;\n\t\t};\n\n\t\tds20 {\n\t\t\tlabel = \"ds20:green\";\n\t\t\tgpios = <0x09 0x3f 0x00>;\n\t\t};\n\n\t\tds21 {\n\t\t\tlabel = \"ds21:green\";\n\t\t\tgpios = <0x09 0x40 0x00>;\n\t\t};\n\n\t\tds22 {\n\t\t\tlabel = \"ds22:green\";\n\t\t\tgpios = <0x09 0x41 0x00>;\n\t\t};\n\n\t\tds23 {\n\t\t\tlabel = \"ds23:green\";\n\t\t\tgpios = <0x09 0x0a 0x00>;\n\t\t};\n\t};\n\n\tgpio_keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <0x01>;\n\t\t#size-cells = <0x00>;\n\t\tautorepeat;\n\n\t\tsw5 {\n\t\t\tlabel = \"Left\";\n\t\t\tlinux,code = <0x69>;\n\t\t\tgpios = <0x09 0x36 0x00>;\n\t\t};\n\n\t\tsw7 {\n\t\t\tlabel = \"Right\";\n\t\t\tlinux,code = <0x6a>;\n\t\t\tgpios = <0x09 0x37 0x00>;\n\t\t};\n\n\t\tsw15_0 {\n\t\t\tlabel = \"SW15_0\";\n\t\t\tlinux,code = <0x0d>;\n\t\t\tlinux,input-type = <0x05>;\n\t\t\tgpios = <0x09 0x38 0x00>;\n\t\t};\n\n\t\tsw15_1 {\n\t\t\tlabel = \"SW15_1\";\n\t\t\tlinux,code = <0x01>;\n\t\t\tlinux,input-type = <0x05>;\n\t\t\tgpios = <0x09 0x39 0x00>;\n\t\t};\n\n\t\tsw13 {\n\t\t\tlabel = \"Select\";\n\t\t\tlinux,code = <0x1c>;\n\t\t\tgpios = <0x09 0x0e 0x00>;\n\t\t};\n\n\t\tsw14 {\n\t\t\tlabel = \"SW14\";\n\t\t\tlinux,code = <0x01>;\n\t\t\tgpios = <0x09 0x0c 0x00>;\n\t\t};\n\t};\n\n\tfpga-axi@0 {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x01>;\n\t\t#size-cells = <0x01>;\n\t\tranges;\n\t\tphandle = <0x46>;\n\n\t\ti2c@41600000 {\n\t\t\tcompatible = \"xlnx,axi-iic-1.02.a\\0xlnx,xps-iic-2.00.a\";\n\t\t\treg = <0x41600000 0x10000>;\n\t\t\tinterrupt-parent = <0x01>;\n\t\t\tinterrupts = <0x00 0x3a 0x04>;\n\t\t\tclocks = <0x02 0x0f>;\n\t\t\tclock-names = \"pclk\";\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\n\t\t\tmux@74 {\n\t\t\t\tcompatible = \"pca9548\";\n\t\t\t\treg = <0x74>;\n\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t#size-cells = <0x00>;\n\n\t\t\t\ti2c@1 {\n\t\t\t\t\t#size-cells = <0x00>;\n\t\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t\treg = <0x01>;\n\n\t\t\t\t\tadv7511@39 {\n\t\t\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\t\t\treg = <0x39 0x3f>;\n\t\t\t\t\t\treg-names = \"primary\\0edid\";\n\t\t\t\t\t\tadi,input-depth = <0x08>;\n\t\t\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\t\t\tadi,input-style = <0x01>;\n\t\t\t\t\t\tadi,input-justification = \"right\";\n\t\t\t\t\t\tadi,clock-delay = <0x00>;\n\t\t\t\t\t\t#sound-dai-cells = <0x01>;\n\t\t\t\t\t\tphandle = <0x20>;\n\n\t\t\t\t\t\tports {\n\t\t\t\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t\t\t\t#size-cells = <0x00>;\n\n\t\t\t\t\t\t\tport@0 {\n\t\t\t\t\t\t\t\treg = <0x00>;\n\n\t\t\t\t\t\t\t\tendpoint {\n\t\t\t\t\t\t\t\t\tremote-endpoint = <0x16>;\n\t\t\t\t\t\t\t\t\tphandle = <0x19>;\n\t\t\t\t\t\t\t\t};\n\t\t\t\t\t\t\t};\n\n\t\t\t\t\t\t\tport@1 {\n\t\t\t\t\t\t\t\treg = <0x01>;\n\t\t\t\t\t\t\t};\n\t\t\t\t\t\t};\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\ti2c@4 {\n\t\t\t\t\t#size-cells = <0x00>;\n\t\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t\treg = <0x04>;\n\n\t\t\t\t\trtc@51 {\n\t\t\t\t\t\tcompatible = \"rtc8564\";\n\t\t\t\t\t\treg = <0x51>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\ti2c@5 {\n\t\t\t\t\t#size-cells = <0x00>;\n\t\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t\treg = <0x05>;\n\t\t\t\t\tphandle = <0x47>;\n\n\t\t\t\t\tad7291@2f {\n\t\t\t\t\t\tcompatible = \"adi,ad7291\";\n\t\t\t\t\t\treg = <0x2f>;\n\t\t\t\t\t};\n\n\t\t\t\t\teeprom@50 {\n\t\t\t\t\t\tcompatible = \"at24,24c02\";\n\t\t\t\t\t\treg = <0x50>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n/*\n\t\tdma@43000000 {\n\t\t\tcompatible = \"adi,axi-dmac-1.00.a\";\n\t\t\treg = <0x43000000 0x10000>;\n\t\t\t#dma-cells = <0x01>;\n\t\t\tinterrupts = <0x00 0x3b 0x04>;\n\t\t\tclocks = <0x02 0x10>;\n\t\t\tphandle = <0x17>;\n\n\t\t\tadi,channels {\n\t\t\t\t#size-cells = <0x00>;\n\t\t\t\t#address-cells = <0x01>;\n\n\t\t\t\tdma-channel@0 {\n\t\t\t\t\treg = <0x00>;\n\t\t\t\t\tadi,source-bus-width = <0x40>;\n\t\t\t\t\tadi,source-bus-type = <0x00>;\n\t\t\t\t\tadi,destination-bus-width = <0x40>;\n\t\t\t\t\tadi,destination-bus-type = <0x01>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\taxi-clkgen@79000000 {\n\t\t\tcompatible = \"adi,axi-clkgen-2.00.a\";\n\t\t\treg = <0x79000000 0x10000>;\n\t\t\t#clock-cells = <0x00>;\n\t\t\tclocks = <0x02 0x0f 0x02 0x10>;\n\t\t\tclock-names = \"s_axi_aclk\\0clkin1\";\n\t\t\tphandle = <0x18>;\n\t\t};\n\n\t\taxi_hdmi@70e00000 {\n\t\t\tcompatible = \"adi,axi-hdmi-tx-1.00.a\";\n\t\t\treg = <0x70e00000 0x10000>;\n\t\t\tdmas = <0x17 0x00>;\n\t\t\tdma-names = \"video\";\n\t\t\tclocks = <0x18>;\n\n\t\t\tport {\n\n\t\t\t\tendpoint {\n\t\t\t\t\tremote-endpoint = <0x19>;\n\t\t\t\t\tphandle = <0x16>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\taxi-spdif-tx@75c00000 {\n\t\t\tcompatible = \"adi,axi-spdif-tx-1.00.a\";\n\t\t\treg = <0x75c00000 0x1000>;\n\t\t\tdmas = <0x1a 0x00>;\n\t\t\tdma-names = \"tx\";\n\t\t\tclocks = <0x02 0x0f 0x1b>;\n\t\t\tclock-names = \"axi\\0ref\";\n\t\t\t#sound-dai-cells = <0x00>;\n\t\t\tphandle = <0x1f>;\n\t\t};\n\n\t\taxi-sysid-0@45000000 {\n\t\t\tcompatible = \"adi,axi-sysid-1.00.a\";\n\t\t\treg = <0x45000000 0x10000>;\n\t\t\tphandle = <0x48>;\n\t\t};\n\n\t\tdma@7c400000 {\n\t\t\tcompatible = \"adi,axi-dmac-1.00.a\";\n\t\t\treg = <0x7c400000 0x10000>;\n\t\t\t#dma-cells = <0x01>;\n\t\t\tinterrupts = <0x00 0x39 0x04>;\n\t\t\tclocks = <0x02 0x10>;\n\t\t\tphandle = <0x1c>;\n\n\t\t\tadi,channels {\n\t\t\t\t#size-cells = <0x00>;\n\t\t\t\t#address-cells = <0x01>;\n\n\t\t\t\tdma-channel@0 {\n\t\t\t\t\treg = <0x00>;\n\t\t\t\t\tadi,source-bus-width = <0x40>;\n\t\t\t\t\tadi,source-bus-type = <0x02>;\n\t\t\t\t\tadi,destination-bus-width = <0x40>;\n\t\t\t\t\tadi,destination-bus-type = <0x00>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tdma@7c420000 {\n\t\t\tcompatible = \"adi,axi-dmac-1.00.a\";\n\t\t\treg = <0x7c420000 0x10000>;\n\t\t\t#dma-cells = <0x01>;\n\t\t\tinterrupts = <0x00 0x38 0x04>;\n\t\t\tclocks = <0x02 0x10>;\n\t\t\tphandle = <0x1e>;\n\n\t\t\tadi,channels {\n\t\t\t\t#size-cells = <0x00>;\n\t\t\t\t#address-cells = <0x01>;\n\n\t\t\t\tdma-channel@0 {\n\t\t\t\t\treg = <0x00>;\n\t\t\t\t\tadi,source-bus-width = <0x40>;\n\t\t\t\t\tadi,source-bus-type = <0x00>;\n\t\t\t\t\tadi,destination-bus-width = <0x40>;\n\t\t\t\t\tadi,destination-bus-type = <0x02>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n*/\n\t\tsdr: sdr {\n\t\t\tcompatible =\"sdr,sdr\";\n\t\t\tdmas = <&rx_dma 1\n\t\t\t\t\t&tx_dma 0>;\n\t\t\tdma-names = \"rx_dma_s2mm\", \"tx_dma_mm2s\";\n\t\t\tinterrupt-names = \"not_valid_anymore\", \"rx_pkt_intr\", \"tx_itrpt\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 29 1 0 30 1 0 33 1 0 34 1>;\n\t\t} ;\n\n\t\taxidmatest_1: axidmatest@1 {\n\t\t\tcompatible =\"xlnx,axi-dma-test-1.00.a\";\n\t\t\tdmas = <&rx_dma 0\n\t\t\t\t&rx_dma 1>;\n\t\t\tdma-names = \"axidma0\", \"axidma1\";\n\t\t} ;\n\n\t\ttx_dma: dma@80400000 {\n\t\t\t#dma-cells = <1>;\n\t\t\tclock-names = \"s_axi_lite_aclk\", \"m_axi_sg_aclk\", \"m_axi_mm2s_aclk\", \"m_axi_s2mm_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"xlnx,axi-dma-1.00.a\";\n\t\t\tinterrupt-names = \"mm2s_introut\", \"s2mm_introut\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 35 4 0 36 4>;\n\t\t\treg = <0x80400000 0x10000>;\n\t\t\txlnx,addrwidth = <0x20>;\n\t\t\txlnx,include-sg ;\n\t\t\txlnx,sg-length-width = <0xe>;\n\t\t\tdma-channel@80400000 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-mm2s-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 35 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x0>;\n\t\t\t};\n\t\t\tdma-channel@80400030 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-s2mm-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 36 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x0>;\n\t\t\t};\n\t\t};\n\t\t\n\t\trx_dma: dma@80410000 {\n\t\t\t#dma-cells = <1>;\n\t\t\tclock-names = \"s_axi_lite_aclk\", \"m_axi_sg_aclk\", \"m_axi_mm2s_aclk\", \"m_axi_s2mm_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"xlnx,axi-dma-1.00.a\";\n\t\t\t//dma-coherent ;\n\t\t\tinterrupt-names = \"mm2s_introut\", \"s2mm_introut\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 31 4 0 32 4>;\n\t\t\treg = <0x80410000 0x10000>;\n\t\t\txlnx,addrwidth = <0x20>;\n\t\t\txlnx,include-sg ;\n\t\t\txlnx,sg-length-width = <0xe>;\n\t\t\tdma-channel@80410000 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-mm2s-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 31 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x1>;\n\t\t\t};\n\t\t\tdma-channel@80410030 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-s2mm-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 32 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x1>;\n\t\t\t};\n\t\t};\n\n\t\ttx_intf_0: tx_intf@83c00000 {\n\t\t\tclock-names = \"s00_axi_aclk\", \"s00_axis_aclk\";//, \"s01_axis_aclk\", \"m00_axis_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"sdr,tx_intf\";\n\t\t\tinterrupt-names = \"tx_itrpt\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 34 1>;\n\t\t\treg = <0x83c00000 0x10000>;\n\t\t\txlnx,s00-axi-addr-width = <0x7>;\n\t\t\txlnx,s00-axi-data-width = <0x20>;\n\t\t};\n\n\t\trx_intf_0: rx_intf@83c20000 {\n\t\t\tclock-names = \"s00_axi_aclk\", \"m00_axis_aclk\";//, \"s00_axis_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>;\n\t\t\tcompatible = \"sdr,rx_intf\";\n\t\t\tinterrupt-names = \"not_valid_anymore\", \"rx_pkt_intr\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 29 1 0 30 1>;\n\t\t\treg = <0x83c20000 0x10000>;\n\t\t\txlnx,s00-axi-addr-width = <0x7>;\n\t\t\txlnx,s00-axi-data-width = <0x20>;\n\t\t};\n\n\t\topenofdm_tx_0: openofdm_tx@83c10000 {\n\t\t\tclock-names = \"clk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,openofdm_tx\";\n\t\t\treg = <0x83c10000 0x10000>;\n\t\t};\n\n\t\topenofdm_rx_0: openofdm_rx@83c30000 {\n\t\t\tclock-names = \"clk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,openofdm_rx\";\n\t\t\treg = <0x83c30000 0x10000>;\n\t\t};\n\n\t\txpu_0: xpu@83c40000 {\n\t\t\tclock-names = \"s00_axi_aclk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,xpu\";\n\t\t\treg = <0x83c40000 0x10000>;\n\t\t};\n\n\t\tside_ch_0: side_ch@83c50000 {\n\t\t\tclock-names = \"s00_axi_aclk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,side_ch\";\n\t\t\treg = <0x83c50000 0x10000>;\n\t\t\tdmas = <&rx_dma 0\n\t\t\t\t\t&tx_dma 1>;\n\t\t\tdma-names = \"rx_dma_mm2s\", \"tx_dma_s2mm\";\n\t\t};\n\n\t\tcf-ad9361-lpc@79020000 {\n\t\t\tcompatible = \"adi,axi-ad9361-6.00.a\";\n\t\t\treg = <0x79020000 0x6000>;\n\t\t\t// dmas = <0x1c 0x00>;\n\t\t\t// dma-names = \"rx\";\n\t\t\tspibus-connected = <0x1d>;\n\t\t\tphandle = <0x49>;\n\t\t};\n\n\t\tcf-ad9361-dds-core-lpc@79024000 {\n\t\t\tcompatible = \"adi,axi-ad9361-dds-6.00.a\";\n\t\t\treg = <0x79024000 0x1000>;\n\t\t\tclocks = <0x1d 0x0d>;\n\t\t\tclock-names = \"sampl_clk\";\n\t\t\t// dmas = <0x1e 0x00>;\n\t\t\t// dma-names = \"tx\";\n\t\t\tphandle = <0x4a>;\n\t\t};\n\t};\n/*\n\taudio_clock {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x00>;\n\t\tclock-frequency = <0xbb8000>;\n\t\tphandle = <0x1b>;\n\t};\n\n\tadv7511_hdmi_snd {\n\t\tcompatible = \"simple-audio-card\";\n\t\tsimple-audio-card,name = \"HDMI monitor\";\n\t\tsimple-audio-card,widgets = \"Speaker\\0Speaker\";\n\t\tsimple-audio-card,routing = \"Speaker\\0TX\";\n\n\t\tsimple-audio-card,dai-link@0 {\n\t\t\tformat = \"spdif\";\n\n\t\t\tcpu {\n\t\t\t\tsound-dai = <0x1f>;\n\t\t\t\tframe-master;\n\t\t\t\tbitclock-master;\n\t\t\t};\n\n\t\t\tcodec {\n\t\t\t\tsound-dai = <0x20 0x01>;\n\t\t\t};\n\t\t};\n\t};\n*/\n\tclocks {\n\n\t\tclock@0 {\n\t\t\tcompatible = \"fixed-clock\";\n\t\t\tclock-frequency = <0x2625a00>;\n\t\t\tclock-output-names = \"ad9361_ext_refclk\";\n\t\t\t#clock-cells = <0x00>;\n\t\t\tphandle = <0x08>;\n\t\t};\n\n\t\tclock@1 {\n\t\t\tcompatible = \"fixed-clock\";\n\t\t\tclock-frequency = <0x17d7840>;\n\t\t\tclock-output-names = \"refclk\";\n\t\t\t#clock-cells = <0x00>;\n\t\t\tphandle = <0x0a>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "kernel_boot/boards/zc706_fmcs2/devicetree.dts",
    "content": "/dts-v1/;\n\n/ {\n\t#address-cells = <0x1>;\n\t#size-cells = <0x1>;\n\tcompatible = \"xlnx,zynq-7000\";\n\tinterrupt-parent = <0x1>;\n\tmodel = \"Xilinx Zynq ZC706\";\n\n\tcpus {\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0x0>;\n\t\t\tclocks = <0x2 0x3>;\n\t\t\tclock-latency = <0x3e8>;\n\t\t\tcpu0-supply = <0x3>;\n\t\t\toperating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0x1>;\n\t\t\tclocks = <0x2 0x3>;\n\t\t};\n\t};\n\n\tfpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <0x4>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tranges;\n\t};\n\n\tpmu@f8891000 {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0x0 0x5 0x4 0x0 0x6 0x4>;\n\t\tinterrupt-parent = <0x1>;\n\t\treg = <0xf8891000 0x1000 0xf8893000 0x1000>;\n\t};\n\n\tfixedregulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <0xf4240>;\n\t\tregulator-max-microvolt = <0xf4240>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t\tlinux,phandle = <0x3>;\n\t\tphandle = <0x3>;\n\t};\n\n\tamba {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tinterrupt-parent = <0x1>;\n\t\tranges;\n\n\t\tadc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0x0 0x7 0x4>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tclocks = <0x2 0xc>;\n\t\t};\n\n\t\tcan@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x13 0x2 0x24>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0x0 0x1c 0x4>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x14 0x2 0x25>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0x0 0x33 0x4>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tclocks = <0x2 0x2a>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <0x2>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x14 0x4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t\tlinux,phandle = <0x6>;\n\t\t\tphandle = <0x6>;\n\t\t};\n\n\t\ti2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x26>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x19 0x4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t};\n\n\t\ti2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x27>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x30 0x4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t};\n\n\t\tinterrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <0x3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xf8f01000 0x1000 0xf8f00100 0x100>;\n\t\t\tlinux,phandle = <0x1>;\n\t\t\tphandle = <0x1>;\n\t\t};\n\n\t\tcache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xf8f02000 0x1000>;\n\t\t\tinterrupts = <0x0 0x2 0x4>;\n\t\t\tarm,data-latency = <0x3 0x2 0x2>;\n\t\t\tarm,tag-latency = <0x2 0x2 0x2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <0x2>;\n\t\t};\n\n\t\tmemory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x3 0x4>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t};\n\n\t\tserial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x17 0x2 0x28>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xe0000000 0x1000>;\n\t\t\tinterrupts = <0x0 0x1b 0x4>;\n\t\t};\n\n\t\tserial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"okay\";\n\t\t\tclocks = <0x2 0x18 0x2 0x29>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xe0001000 0x1000>;\n\t\t\tinterrupts = <0x0 0x32 0x4>;\n\t\t};\n\n\t\tspi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x1a 0x4>;\n\t\t\tclocks = <0x2 0x19 0x2 0x22>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\n\t\t\tad9361-phy@0 {\n\t\t\t\tcompatible = \"adi,ad9361\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tspi-cpha;\n\t\t\t\tspi-max-frequency = <0x989680>;\n\t\t\t\tclocks = <0x5 0x0>;\n\t\t\t\tclock-names = \"ad9361_ext_refclk\";\n\t\t\t\tclock-output-names = \"rx_sampl_clk\", \"tx_sampl_clk\";\n\t\t\t\t#clock-cells = <0x1>;\n\t\t\t\tadi,digital-interface-tune-skip-mode = <0x0>;\n\t\t\t\tadi,pp-tx-swap-enable;\n\t\t\t\tadi,pp-rx-swap-enable;\n\t\t\t\tadi,rx-frame-pulse-mode-enable;\n\t\t\t\tadi,lvds-mode-enable;\n\t\t\t\tadi,lvds-bias-mV = <0x96>;\n\t\t\t\tadi,lvds-rx-onchip-termination-enable;\n\t\t\t\tadi,rx-data-delay = <0x4>;\n\t\t\t\tadi,tx-fb-clock-delay = <0x7>;\n\t\t\t\tadi,dcxo-coarse-and-fine-tune = <0x8 0x1720>;\n\t\t\t\tadi,2rx-2tx-mode-enable;\n\t\t\t\tadi,frequency-division-duplex-mode-enable;\n\t\t\t\tadi,rx-rf-port-input-select = <0x0>;\n\t\t\t\tadi,tx-rf-port-input-select = <0x0>;\n\t\t\t\tadi,tx-attenuation-mdB = <0x2710>;\n\t\t\t\tadi,tx-lo-powerdown-managed-enable;\n\t\t\t\tadi,rf-rx-bandwidth-hz = <0x112a880>;\n\t\t\t\tadi,rf-tx-bandwidth-hz = <0x112a880>;\n\t\t\t\tadi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;\n\t\t\t\tadi,tx-synthesizer-frequency-hz = <0x0 0x92080880>;\n\t\t\t\tadi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;\n\t\t\t\tadi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;\n\t\t\t\tadi,gc-rx1-mode = <0x2>;\n\t\t\t\tadi,gc-rx2-mode = <0x2>;\n\t\t\t\tadi,gc-adc-ovr-sample-size = <0x4>;\n\t\t\t\tadi,gc-adc-small-overload-thresh = <0x2f>;\n\t\t\t\tadi,gc-adc-large-overload-thresh = <0x3a>;\n\t\t\t\tadi,gc-lmt-overload-high-thresh = <0x320>;\n\t\t\t\tadi,gc-lmt-overload-low-thresh = <0x2c0>;\n\t\t\t\tadi,gc-dec-pow-measurement-duration = <0x2000>;\n\t\t\t\tadi,gc-low-power-thresh = <0x18>;\n\t\t\t\tadi,mgc-inc-gain-step = <0x2>;\n\t\t\t\tadi,mgc-dec-gain-step = <0x2>;\n\t\t\t\tadi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;\n\t\t\t\tadi,agc-attack-delay-extra-margin-us = <0x1>;\n\t\t\t\tadi,agc-outer-thresh-high = <0x5>;\n\t\t\t\tadi,agc-outer-thresh-high-dec-steps = <0x2>;\n\t\t\t\tadi,agc-inner-thresh-high = <0xa>;\n\t\t\t\tadi,agc-inner-thresh-high-dec-steps = <0x1>;\n\t\t\t\tadi,agc-inner-thresh-low = <0xc>;\n\t\t\t\tadi,agc-inner-thresh-low-inc-steps = <0x1>;\n\t\t\t\tadi,agc-outer-thresh-low = <0x12>;\n\t\t\t\tadi,agc-outer-thresh-low-inc-steps = <0x2>;\n\t\t\t\tadi,agc-adc-small-overload-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-adc-large-overload-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-adc-large-overload-inc-steps = <0x7>;\n\t\t\t\tadi,agc-lmt-overload-large-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-lmt-overload-small-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-lmt-overload-large-inc-steps = <0x7>;\n\t\t\t\tadi,agc-gain-update-interval-us = <0x3e8>;\n\t\t\t\tadi,fagc-dec-pow-measurement-duration = <0x10>;\n        adi,fagc-adc-large-overload-inc-steps = <0x07>;\n\t\t\t\tadi,fagc-lp-thresh-increment-steps = <0x1>;\n\t\t\t\tadi,fagc-lp-thresh-increment-time = <0x5>;\n\t\t\t\tadi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;\n        adi,fagc-dig-sat-ovrg-enable;\n\t\t\t\tadi,fagc-final-overrange-count = <0x3>;\n\t\t\t\tadi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;\n\t\t\t\tadi,fagc-lmt-final-settling-steps = <0x1>;\n\t\t\t\tadi,fagc-lock-level = <0xa>;\n\t\t\t\tadi,fagc-lock-level-gain-increase-upper-limit = <0x5>;\n\t\t\t\tadi,fagc-lock-level-lmt-gain-increase-enable;\n\t\t\t\tadi,fagc-lpf-final-settling-steps = <0x1>;\n\t\t\t\tadi,fagc-optimized-gain-offset = <0x5>;\n\t\t\t\tadi,fagc-power-measurement-duration-in-state5 = <0x10>;\n\t\t\t\tadi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;\n\t\t\t\tadi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;\n\t\t\t\tadi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;\n\t\t\t\tadi,fagc-rst-gla-large-adc-overload-enable;\n\t\t\t\tadi,fagc-rst-gla-large-lmt-overload-enable;\n\t\t\t\tadi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;\n\t\t\t\tadi,fagc-state-wait-time-ns = <0x104>;\n\t\t\t\tadi,fagc-use-last-lock-level-for-set-gain-enable;\n\t\t\t\tadi,rssi-restart-mode = <0x3>;\n\t\t\t\tadi,rssi-delay = <0x1>;\n\t\t\t\tadi,rssi-wait = <0x1>;\n\t\t\t\tadi,rssi-duration = <0x3e8>;\n\t\t\t\tadi,ctrl-outs-index = <0x0>;\n\t\t\t\tadi,ctrl-outs-enable-mask = <0xff>;\n\t\t\t\tadi,temp-sense-measurement-interval-ms = <0x3e8>;\n\t\t\t\tadi,temp-sense-offset-signed = <0xce>;\n\t\t\t\tadi,temp-sense-periodic-measurement-enable;\n\t\t\t\tadi,aux-dac-manual-mode-enable;\n\t\t\t\tadi,aux-dac1-default-value-mV = <0x0>;\n\t\t\t\tadi,aux-dac1-rx-delay-us = <0x0>;\n\t\t\t\tadi,aux-dac1-tx-delay-us = <0x0>;\n\t\t\t\tadi,aux-dac2-default-value-mV = <0x0>;\n\t\t\t\tadi,aux-dac2-rx-delay-us = <0x0>;\n\t\t\t\tadi,aux-dac2-tx-delay-us = <0x0>;\n\t\t\t\ten_agc-gpios = <0x6 0x62 0x0>;\n\t\t\t\tsync-gpios = <0x6 0x63 0x0>;\n\t\t\t\treset-gpios = <0x6 0x64 0x0>;\n\t\t\t\tenable-gpios = <0x6 0x65 0x0>;\n\t\t\t\ttxnrx-gpios = <0x6 0x66 0x0>;\n\t\t\t\tlinux,phandle = <0x11>;\n\t\t\t\tphandle = <0x11>;\n\t\t\t};\n\t\t};\n\n\t\tspi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x31 0x4>;\n\t\t\tclocks = <0x2 0x1a 0x2 0x23>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\n\t\t\tadf4351-udc-tx-pmod@0 {\n\t\t\t\tcompatible = \"adi,adf4351\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tspi-max-frequency = <0x989680>;\n\t\t\t\tclocks = <0x7>;\n\t\t\t\tclock-names = \"clkin\";\n\t\t\t\tadi,channel-spacing = <0xf4240>;\n\t\t\t\tadi,power-up-frequency = <0x160dc080>;\n\t\t\t\tadi,phase-detector-polarity-positive-enable;\n\t\t\t\tadi,charge-pump-current = <0x9c4>;\n\t\t\t\tadi,output-power = <0x3>;\n\t\t\t\tadi,mute-till-lock-enable;\n\t\t\t\tadi,muxout-select = <0x6>;\n\t\t\t\tgpios = <0x6 0x68 0x0>;\n\t\t\t};\n\n\t\t\tadf4351-udc-rx-pmod@1 {\n\t\t\t\tcompatible = \"adi,adf4351\";\n\t\t\t\treg = <0x1>;\n\t\t\t\tspi-max-frequency = <0x989680>;\n\t\t\t\tclocks = <0x7>;\n\t\t\t\tclock-names = \"clkin\";\n\t\t\t\tadi,channel-spacing = <0xf4240>;\n\t\t\t\tadi,power-up-frequency = <0x1443fd00>;\n\t\t\t\tadi,phase-detector-polarity-positive-enable;\n\t\t\t\tadi,charge-pump-current = <0x9c4>;\n\t\t\t\tadi,output-power = <0x3>;\n\t\t\t\tadi,mute-till-lock-enable;\n\t\t\t\tadi,muxout-select = <0x6>;\n\t\t\t\tgpios = <0x6 0x67 0x0>;\n\t\t\t};\n\t\t};\n\n\t\tspi@e000d000 {\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tclocks = <0x2 0xa 0x2 0x2b>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x13 0x4>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\tis-dual = <0x1>;\n\t\t\tnum-cs = <0x1>;\n\n\t\t\tps7-qspi@0 {\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t\tspi-tx-bus-width = <0x1>;\n\t\t\t\tspi-rx-bus-width = <0x4>;\n\t\t\t\tcompatible = \"n25q128a11\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tspi-max-frequency = <0x2faf080>;\n\n\t\t\t\tpartition@0 {\n\t\t\t\t\tlabel = \"boot\";\n\t\t\t\t\treg = <0x0 0x500000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@500000 {\n\t\t\t\t\tlabel = \"bootenv\";\n\t\t\t\t\treg = <0x500000 0x20000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@520000 {\n\t\t\t\t\tlabel = \"config\";\n\t\t\t\t\treg = <0x520000 0x20000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@540000 {\n\t\t\t\t\tlabel = \"image\";\n\t\t\t\t\treg = <0x540000 0xa80000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@fc0000 {\n\t\t\t\t\tlabel = \"spare\";\n\t\t\t\t\treg = <0xfc0000 0x0>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tmemory-controller@e000e000 {\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x1>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"aclk\";\n\t\t\tclocks = <0x2 0xb 0x2 0x2c>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x12 0x4>;\n\t\t\tranges;\n\t\t\treg = <0xe000e000 0x1000>;\n\n\t\t\tflash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\n\t\t\tflash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x2000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\t\t};\n\n\t\tethernet@e000b000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupts = <0x0 0x16 0x4>;\n\t\t\tclocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\tphy-handle = <0x8>;\n\t\t\tphy-mode = \"rgmii-id\";\n\n\t\t\tphy@7 {\n\t\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\t\treg = <0x7>;\n\t\t\t\tlinux,phandle = <0x8>;\n\t\t\t\tphandle = <0x8>;\n\t\t\t};\n\t\t};\n\n\t\tethernet@e000c000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0x0 0x2d 0x4>;\n\t\t\tclocks = <0x2 0x1f 0x2 0x1f 0x2 0xe>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t};\n\n\t\tmmc@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <0x2 0x15 0x2 0x20>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x18 0x4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t};\n\n\t\tmmc@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <0x2 0x16 0x2 0x21>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x2f 0x4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t};\n\n\t\tslcr@f8000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\", \"simple-mfd\";\n\t\t\treg = <0xf8000000 0x1000>;\n\t\t\tranges;\n\t\t\tlinux,phandle = <0x9>;\n\t\t\tphandle = <0x9>;\n\n\t\t\tclkc@100 {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <0x1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\", \"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\", \"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\", \"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\", \"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\", \"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\", \"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\", \"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\", \"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\", \"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t\tps-clk-frequency = <0x1fca055>;\n\t\t\t\tlinux,phandle = <0x2>;\n\t\t\t\tphandle = <0x2>;\n\t\t\t};\n\n\t\t\trstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <0x1>;\n\t\t\t\tsyscon = <0x9>;\n\t\t\t};\n\n\t\t\tpinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <0x9>;\n\t\t\t};\n\t\t};\n\n\t\tdmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\", \"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\tinterrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>;\n\t\t\t#dma-cells = <0x1>;\n\t\t\t#dma-channels = <0x8>;\n\t\t\t#dma-requests = <0x4>;\n\t\t\tclocks = <0x2 0x1b>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t\tlinux,phandle = <0xe>;\n\t\t\tphandle = <0xe>;\n\t\t};\n\n\t\tdevcfg@f8007000 {\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x8 0x4>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tclocks = <0x2 0xc 0x2 0xf 0x2 0x10 0x2 0x11 0x2 0x12>;\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tsyscon = <0x9>;\n\t\t\tlinux,phandle = <0x4>;\n\t\t\tphandle = <0x4>;\n\t\t};\n\n\t\tefuse@f800d000 {\n\t\t\tcompatible = \"xlnx,zynq-efuse\";\n\t\t\treg = <0xf800d000 0x20>;\n\t\t};\n\n\t\ttimer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <0x1 0xb 0x301>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tclocks = <0x2 0x4>;\n\t\t};\n\n\t\ttimer@f8001000 {\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <0x2 0x6>;\n\t\t\treg = <0xf8001000 0x1000>;\n\t\t};\n\n\t\ttimer@f8002000 {\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <0x2 0x6>;\n\t\t\treg = <0xf8002000 0x1000>;\n\t\t};\n\n\t\ttimer@f8f00600 {\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x1 0xd 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <0x2 0x4>;\n\t\t};\n\n\t\tusb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"okay\";\n\t\t\tclocks = <0x2 0x1c>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x15 0x4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t\tdr_mode = \"host\";\n\t\t\txlnx,phy-reset-gpio = <0x6 0x7 0x0>;\n\t\t};\n\n\t\tusb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x1d>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x2c 0x4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog@f8005000 {\n\t\t\tclocks = <0x2 0x2d>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x9 0x1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <0xa>;\n\t\t};\n\t};\n\n\taliases {\n\t\tethernet0 = \"/amba/ethernet@e000b000\";\n\t\tserial0 = \"/amba/serial@e0001000\";\n\t};\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x40000000>;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait\";\n\t\tlinux,stdout-path = \"/amba@0/uart@E0001000\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tds8 {\n\t\t\tlabel = \"ds12:green\";\n\t\t\tgpios = <0x6 0x3d 0x0>;\n\t\t\t//gpios = <0x6 7 0x0>;//according to zc706 board, do not know why real gpio_bd[7] here becomes 0x3d\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds9 {\n\t\t\tlabel = \"ds15:green\";\n\t\t\tgpios = <0x6 0x3e 0x0>;\n\t\t\t//gpios = <0x6 8 0x0>;//according to zc706 board, do not know why real gpio_bd[7] here becomes 0x3e\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds10 {\n\t\t\tlabel = \"ds16:green\";\n\t\t\tgpios = <0x6 0x3f 0x0>;\n\t\t\t//gpios = <0x6 9 0x0>;//according to zc706 board, do not know why real gpio_bd[7] here becomes 0x3f\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds35 {\n\t\t\tlabel = \"ds17:green\";\n\t\t\tgpios = <0x6 0x40 0x0>;\n\t\t\t//gpios = <0x6 10 0x0>;//according to zc706 board, do not know why real gpio_bd[7] here becomes 0x40\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tgpio_keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x0>;\n\t\tautorepeat;\n\n\t\tsw7 {\n\t\t\tlabel = \"Left\";\n\t\t\tlinux,code = <0x69>;\n\t\t\tgpios = <0x6 0x3a 0x0>;\n\t\t};\n\n\t\tsw8 {\n\t\t\tlabel = \"Right\";\n\t\t\tlinux,code = <0x6a>;\n\t\t\tgpios = <0x6 0x3c 0x0>;\n\t\t};\n\n\t\tsw9 {\n\t\t\tlabel = \"Select\";\n\t\t\tlinux,code = <0x1c>;\n\t\t\tgpios = <0x6 0x3b 0x0>;\n\t\t};\n\t};\n\n\tfpga-axi@0 {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tranges;\n\n\t\ti2c@41600000 {\n\t\t\tcompatible = \"xlnx,axi-iic-1.02.a\", \"xlnx,xps-iic-2.00.a\";\n\t\t\treg = <0x41600000 0x10000>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x3a 0x4>;\n\t\t\tclocks = <0x2 0xf>;\n\t\t\tclock-names = \"pclk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\n\t\t\ti2cswitch@74 {\n\t\t\t\tcompatible = \"nxp,pca9548\";\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x0>;\n\t\t\t\treg = <0x74>;\n\n\t\t\t\ti2c@0 {\n\t\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t\t#size-cells = <0x0>;\n\t\t\t\t\treg = <0x0>;\n\n\t\t\t\t\tosc@5d {\n\t\t\t\t\t\tcompatible = \"si570\";\n\t\t\t\t\t\ttemperature-stability = <0x32>;\n\t\t\t\t\t\treg = <0x5d>;\n\t\t\t\t\t\tfactory-fout = <0x9502f90>;\n\t\t\t\t\t\tinitial-fout = <0x8d9ee20>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\ti2c@1 {\n\t\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t\t#size-cells = <0x0>;\n\t\t\t\t\treg = <0x1>;\n\n\t\t\t\t\tadv7511 {\n\t\t\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\t\t\treg = <0x39 0x3f>;\n\t\t\t\t\t\treg-names = \"primary\", \"edid\";\n\t\t\t\t\t\tadi,input-depth = <0x8>;\n\t\t\t\t\t\tadi,input-colorspace = \"rgb\";\n\t\t\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\t\t\tadi,clock-delay = <0x0>;\n\t\t\t\t\t\t#sound-dai-cells = <0x0>;\n\t\t\t\t\t\tlinux,phandle = <0x14>;\n\t\t\t\t\t\tphandle = <0x14>;\n\n\t\t\t\t\t\tports {\n\t\t\t\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t\t\t\t#size-cells = <0x0>;\n\n\t\t\t\t\t\t\tport@0 {\n\t\t\t\t\t\t\t\treg = <0x0>;\n\n\t\t\t\t\t\t\t\tendpoint {\n\t\t\t\t\t\t\t\t\tremote-endpoint = <0xa>;\n\t\t\t\t\t\t\t\t\tlinux,phandle = <0xd>;\n\t\t\t\t\t\t\t\t\tphandle = <0xd>;\n\t\t\t\t\t\t\t\t};\n\t\t\t\t\t\t\t};\n\n\t\t\t\t\t\t\tport@1 {\n\t\t\t\t\t\t\t\treg = <0x1>;\n\t\t\t\t\t\t\t};\n\t\t\t\t\t\t};\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\ti2c@2 {\n\t\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t\t#size-cells = <0x0>;\n\t\t\t\t\treg = <0x2>;\n\n\t\t\t\t\teeprom@54 {\n\t\t\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\t\t\treg = <0x54>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\ti2c@3 {\n\t\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t\t#size-cells = <0x0>;\n\t\t\t\t\treg = <0x3>;\n\n\t\t\t\t\tgpio@21 {\n\t\t\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\t\t\treg = <0x21>;\n\t\t\t\t\t\tgpio-controller;\n\t\t\t\t\t\t#gpio-cells = <0x2>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\ti2c@4 {\n\t\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t\t#size-cells = <0x0>;\n\t\t\t\t\treg = <0x4>;\n\n\t\t\t\t\trtc@54 {\n\t\t\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\t\t\treg = <0x51>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\ti2c@6 {\n\t\t\t\t\t#size-cells = <0x0>;\n\t\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t\treg = <0x6>;\n\n\t\t\t\t\tad7291@2f {\n\t\t\t\t\t\tcompatible = \"adi,ad7291\";\n\t\t\t\t\t\treg = <0x2f>;\n\t\t\t\t\t};\n\n\t\t\t\t\teeprom@50 {\n\t\t\t\t\t\tcompatible = \"at24,24c02\";\n\t\t\t\t\t\treg = <0x50>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\t// dma@43000000 {\n\t\t// \tcompatible = \"adi,axi-dmac-1.00.a\";\n\t\t// \treg = <0x43000000 0x10000>;\n\t\t// \t#dma-cells = <0x1>;\n\t\t// \tinterrupts = <0x0 0x3b 0x0>;\n\t\t// \tclocks = <0x2 0x10>;\n\t\t// \tlinux,phandle = <0xb>;\n\t\t// \tphandle = <0xb>;\n\n\t\t// \tadi,channels {\n\t\t// \t\t#size-cells = <0x0>;\n\t\t// \t\t#address-cells = <0x1>;\n\n\t\t// \t\tdma-channel@0 {\n\t\t// \t\t\treg = <0x0>;\n\t\t// \t\t\tadi,source-bus-width = <0x40>;\n\t\t// \t\t\tadi,source-bus-type = <0x0>;\n\t\t// \t\t\tadi,destination-bus-width = <0x40>;\n\t\t// \t\t\tadi,destination-bus-type = <0x1>;\n\t\t// \t\t};\n\t\t// \t};\n\t\t// };\n\n\t\t// axi-clkgen@79000000 {\n\t\t// \tcompatible = \"adi,axi-clkgen-2.00.a\";\n\t\t// \treg = <0x79000000 0x10000>;\n\t\t// \t#clock-cells = <0x0>;\n\t\t// \tclocks = <0x2 0x10>;\n\t\t// \tlinux,phandle = <0xc>;\n\t\t// \tphandle = <0xc>;\n\t\t// };\n\n\t\t// axi_hdmi@70e00000 {\n\t\t// \tcompatible = \"adi,axi-hdmi-tx-1.00.a\";\n\t\t// \treg = <0x70e00000 0x10000>;\n\t\t// \tdmas = <0xb 0x0>;\n\t\t// \tdma-names = \"video\";\n\t\t// \tclocks = <0xc>;\n\t\t// \tadi,is-rgb;\n\n\t\t// \tport {\n\n\t\t// \t\tendpoint {\n\t\t// \t\t\tremote-endpoint = <0xd>;\n\t\t// \t\t\tlinux,phandle = <0xa>;\n\t\t// \t\t\tphandle = <0xa>;\n\t\t// \t\t};\n\t\t// \t};\n\t\t// };\n\n\t\t// axi-spdif-tx@75c00000 {\n\t\t// \tcompatible = \"adi,axi-spdif-tx-1.00.a\";\n\t\t// \treg = <0x75c00000 0x1000>;\n\t\t// \tdmas = <0xe 0x0>;\n\t\t// \tdma-names = \"tx\";\n\t\t// \tclocks = <0x2 0xf 0xf>;\n\t\t// \tclock-names = \"axi\", \"ref\";\n\t\t// \t#sound-dai-cells = <0x0>;\n\t\t// \tlinux,phandle = <0x13>;\n\t\t// \tphandle = <0x13>;\n\t\t// };\n\n\t\t/*axi-sysid-0@45000000 {\n\t\t\tcompatible = \"adi,axi-sysid-1.00.a\";\n\t\t\treg = <0x45000000 0x10000>;\n\t\t};*/\n\n\t\t// dma@7c400000 {\n\t\t// \tcompatible = \"adi,axi-dmac-1.00.a\";\n\t\t// \treg = <0x7c400000 0x10000>;\n\t\t// \t#dma-cells = <0x1>;\n\t\t// \tinterrupts = <0x0 0x39 0x0>;\n\t\t// \tclocks = <0x2 0x10>;\n\t\t// \tlinux,phandle = <0x10>;\n\t\t// \tphandle = <0x10>;\n\n\t\t// \tadi,channels {\n\t\t// \t\t#size-cells = <0x0>;\n\t\t// \t\t#address-cells = <0x1>;\n\n\t\t// \t\tdma-channel@0 {\n\t\t// \t\t\treg = <0x0>;\n\t\t// \t\t\tadi,source-bus-width = <0x40>;\n\t\t// \t\t\tadi,source-bus-type = <0x2>;\n\t\t// \t\t\tadi,destination-bus-width = <0x40>;\n\t\t// \t\t\tadi,destination-bus-type = <0x0>;\n\t\t// \t\t};\n\t\t// \t};\n\t\t// };\n\n\t\t// dma@7c420000 {\n\t\t// \tcompatible = \"adi,axi-dmac-1.00.a\";\n\t\t// \treg = <0x7c420000 0x10000>;\n\t\t// \t#dma-cells = <0x1>;\n\t\t// \tinterrupts = <0x0 0x38 0x0>;\n\t\t// \tclocks = <0x2 0x10>;\n\t\t// \tlinux,phandle = <0x12>;\n\t\t// \tphandle = <0x12>;\n\n\t\t// \tadi,channels {\n\t\t// \t\t#size-cells = <0x0>;\n\t\t// \t\t#address-cells = <0x1>;\n\n\t\t// \t\tdma-channel@0 {\n\t\t// \t\t\treg = <0x0>;\n\t\t// \t\t\tadi,source-bus-width = <0x40>;\n\t\t// \t\t\tadi,source-bus-type = <0x0>;\n\t\t// \t\t\tadi,destination-bus-width = <0x40>;\n\t\t// \t\t\tadi,destination-bus-type = <0x2>;\n\t\t// \t\t};\n\t\t// \t};\n\t\t// };\n\n\t\tsdr: sdr {\n\t\t\tcompatible =\"sdr,sdr\";\n\t\t\tdmas = <&rx_dma 1\n\t\t\t\t\t&tx_dma 0>;\n\t\t\tdma-names = \"rx_dma_s2mm\", \"tx_dma_mm2s\";\n\t\t\tinterrupt-names = \"not_valid_anymore\", \"rx_pkt_intr\", \"tx_itrpt\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 29 1 0 30 1 0 33 1 0 34 1>;\n\t\t} ;\n\n\t\taxidmatest_1: axidmatest@1 {\n\t\t\tcompatible =\"xlnx,axi-dma-test-1.00.a\";\n\t\t\tdmas = <&rx_dma 0\n\t\t\t\t&rx_dma 1>;\n\t\t\tdma-names = \"axidma0\", \"axidma1\";\n\t\t} ;\n\n\t\ttx_dma: dma@80400000 {\n\t\t\t#dma-cells = <1>;\n\t\t\tclock-names = \"s_axi_lite_aclk\", \"m_axi_sg_aclk\", \"m_axi_mm2s_aclk\", \"m_axi_s2mm_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"xlnx,axi-dma-1.00.a\";\n\t\t\tinterrupt-names = \"mm2s_introut\", \"s2mm_introut\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 35 4 0 36 4>;\n\t\t\treg = <0x80400000 0x10000>;\n\t\t\txlnx,addrwidth = <0x20>;\n\t\t\txlnx,include-sg ;\n\t\t\txlnx,sg-length-width = <0xe>;\n\t\t\tdma-channel@80400000 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-mm2s-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 35 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x0>;\n\t\t\t};\n\t\t\tdma-channel@80400030 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-s2mm-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 36 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x0>;\n\t\t\t};\n\t\t};\n\t\t\n\t\trx_dma: dma@80410000 {\n\t\t\t#dma-cells = <1>;\n\t\t\tclock-names = \"s_axi_lite_aclk\", \"m_axi_sg_aclk\", \"m_axi_mm2s_aclk\", \"m_axi_s2mm_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"xlnx,axi-dma-1.00.a\";\n\t\t\t//dma-coherent ;\n\t\t\tinterrupt-names = \"mm2s_introut\", \"s2mm_introut\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 31 4 0 32 4>;\n\t\t\treg = <0x80410000 0x10000>;\n\t\t\txlnx,addrwidth = <0x20>;\n\t\t\txlnx,include-sg ;\n\t\t\txlnx,sg-length-width = <0xe>;\n\t\t\tdma-channel@80410000 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-mm2s-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 31 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x1>;\n\t\t\t};\n\t\t\tdma-channel@80410030 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-s2mm-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 32 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x1>;\n\t\t\t};\n\t\t};\n\n\t\ttx_intf_0: tx_intf@83c00000 {\n\t\t\tclock-names = \"s00_axi_aclk\", \"s00_axis_aclk\";//, \"s01_axis_aclk\", \"m00_axis_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"sdr,tx_intf\";\n\t\t\tinterrupt-names = \"tx_itrpt\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 34 1>;\n\t\t\treg = <0x83c00000 0x10000>;\n\t\t\txlnx,s00-axi-addr-width = <0x7>;\n\t\t\txlnx,s00-axi-data-width = <0x20>;\n\t\t};\n\n\t\trx_intf_0: rx_intf@83c20000 {\n\t\t\tclock-names = \"s00_axi_aclk\", \"m00_axis_aclk\";//, \"s00_axis_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>;\n\t\t\tcompatible = \"sdr,rx_intf\";\n\t\t\tinterrupt-names = \"not_valid_anymore\", \"rx_pkt_intr\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 29 1 0 30 1>;\n\t\t\treg = <0x83c20000 0x10000>;\n\t\t\txlnx,s00-axi-addr-width = <0x7>;\n\t\t\txlnx,s00-axi-data-width = <0x20>;\n\t\t};\n\n\t\topenofdm_tx_0: openofdm_tx@83c10000 {\n\t\t\tclock-names = \"clk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,openofdm_tx\";\n\t\t\treg = <0x83c10000 0x10000>;\n\t\t};\n\n\t\topenofdm_rx_0: openofdm_rx@83c30000 {\n\t\t\tclock-names = \"clk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,openofdm_rx\";\n\t\t\treg = <0x83c30000 0x10000>;\n\t\t};\n\n\t\txpu_0: xpu@83c40000 {\n\t\t\tclock-names = \"s00_axi_aclk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,xpu\";\n\t\t\treg = <0x83c40000 0x10000>;\n\t\t};\n\n\t\tside_ch_0: side_ch@83c50000 {\n\t\t\tclock-names = \"s00_axi_aclk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,side_ch\";\n\t\t\treg = <0x83c50000 0x10000>;\n\t\t\tdmas = <&rx_dma 0\n\t\t\t\t\t&tx_dma 1>;\n\t\t\tdma-names = \"rx_dma_mm2s\", \"tx_dma_s2mm\";\n\t\t};\n\n\t\tcf-ad9361-lpc@79020000 {\n\t\t\tcompatible = \"adi,axi-ad9361-6.00.a\";\n\t\t\treg = <0x79020000 0x6000>;\n\t\t\t// dmas = <0x10 0x0>;\n\t\t\t// dma-names = \"rx\";\n\t\t\tspibus-connected = <0x11>;\n\t\t};\n\n\t\tcf-ad9361-dds-core-lpc@79024000 {\n\t\t\tcompatible = \"adi,axi-ad9361-dds-6.00.a\";\n\t\t\treg = <0x79024000 0x1000>;\n\t\t\tclocks = <0x11 0xd>;\n\t\t\tclock-names = \"sampl_clk\";\n\t\t\t// dmas = <0x12 0x0>;\n\t\t\t// dma-names = \"tx\";\n\t\t};\n\n\t\tmwipcore@43c00000 {\n\t\t\tcompatible = \"mathworks,mwipcore-axi4lite-v1.00\";\n\t\t\treg = <0x43c00000 0xffff>;\n\t\t};\n\t};\n\n\taudio_clock {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <0xbb8000>;\n\t\tlinux,phandle = <0xf>;\n\t\tphandle = <0xf>;\n\t};\n\n\tadv7511_hdmi_snd {\n\t\tcompatible = \"simple-audio-card\";\n\t\tsimple-audio-card,name = \"HDMI monitor\";\n\t\tsimple-audio-card,widgets = \"Speaker\", \"Speaker\";\n\t\tsimple-audio-card,routing = \"Speaker\", \"TX\";\n\n\t\tsimple-audio-card,dai-link@0 {\n\t\t\tformat = \"spdif\";\n\n\t\t\tcpu {\n\t\t\t\tsound-dai = <0x13>;\n\t\t\t\tframe-master;\n\t\t\t\tbitclock-master;\n\t\t\t};\n\n\t\t\tcodec {\n\t\t\t\tsound-dai = <0x14>;\n\t\t\t};\n\t\t};\n\t};\n\n\tclocks {\n\n\t\tclock@0 {\n\t\t\tcompatible = \"fixed-clock\";\n\t\t\tclock-frequency = <0x2625a00>;\n\t\t\tclock-output-names = \"ad9361_ext_refclk\";\n\t\t\t#clock-cells = <0x0>;\n\t\t\tlinux,phandle = <0x5>;\n\t\t\tphandle = <0x5>;\n\t\t};\n\n\t\tclock@1 {\n\t\t\tcompatible = \"fixed-clock\";\n\t\t\tclock-frequency = <0x17d7840>;\n\t\t\tclock-output-names = \"refclk\";\n\t\t\t#clock-cells = <0x0>;\n\t\t\tlinux,phandle = <0x7>;\n\t\t\tphandle = <0x7>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "kernel_boot/boards/zcu102_fmcs2/system.dts",
    "content": "/dts-v1/;\n\n/ {\n\tcompatible = \"xlnx,zynqmp-zcu102-rev1.0\\0xlnx,zynqmp-zcu102\\0xlnx,zynqmp\";\n\t#address-cells = <0x02>;\n\t#size-cells = <0x02>;\n\tmodel = \"ZynqMP ZCU102 Rev1.0\";\n\n\tcpus {\n\t\t#address-cells = <0x01>;\n\t\t#size-cells = <0x00>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <0x01>;\n\t\t\treg = <0x00>;\n\t\t\tcpu-idle-states = <0x02>;\n\t\t\tclocks = <0x03 0x0a>;\n\t\t\tphandle = <0x3f>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x01>;\n\t\t\toperating-points-v2 = <0x01>;\n\t\t\tcpu-idle-states = <0x02>;\n\t\t\tphandle = <0x40>;\n\t\t};\n\n\t\tcpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x02>;\n\t\t\toperating-points-v2 = <0x01>;\n\t\t\tcpu-idle-states = <0x02>;\n\t\t\tphandle = <0x41>;\n\t\t};\n\n\t\tcpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x03>;\n\t\t\toperating-points-v2 = <0x01>;\n\t\t\tcpu-idle-states = <0x02>;\n\t\t\tphandle = <0x42>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tcpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <0x12c>;\n\t\t\t\texit-latency-us = <0x258>;\n\t\t\t\tmin-residency-us = <0x2710>;\n\t\t\t\tphandle = <0x02>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu-opp-table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\tphandle = <0x01>;\n\n\t\topp00 {\n\t\t\topp-hz = <0x00 0x47868bf4>;\n\t\t\topp-microvolt = <0xf4240>;\n\t\t\tclock-latency-ns = <0x7a120>;\n\t\t};\n\n\t\topp01 {\n\t\t\topp-hz = <0x00 0x23c345fa>;\n\t\t\topp-microvolt = <0xf4240>;\n\t\t\tclock-latency-ns = <0x7a120>;\n\t\t};\n\n\t\topp02 {\n\t\t\topp-hz = <0x00 0x17d783fc>;\n\t\t\topp-microvolt = <0xf4240>;\n\t\t\tclock-latency-ns = <0x7a120>;\n\t\t};\n\n\t\topp03 {\n\t\t\topp-hz = <0x00 0x11e1a2fd>;\n\t\t\topp-microvolt = <0xf4240>;\n\t\t\tclock-latency-ns = <0x7a120>;\n\t\t};\n\t};\n\n\tzynqmp_ipi {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <0x04>;\n\t\tinterrupts = <0x00 0x23 0x04>;\n\t\txlnx,ipi-id = <0x00>;\n\t\t#address-cells = <0x02>;\n\t\t#size-cells = <0x02>;\n\t\tranges;\n\t\tphandle = <0x43>;\n\n\t\tmailbox@ff990400 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\treg = <0x00 0xff9905c0 0x00 0x20 0x00 0xff9905e0 0x00 0x20 0x00 0xff990e80 0x00 0x20 0x00 0xff990ea0 0x00 0x20>;\n\t\t\treg-names = \"local_request_region\\0local_response_region\\0remote_request_region\\0remote_response_region\";\n\t\t\t#mbox-cells = <0x01>;\n\t\t\txlnx,ipi-id = <0x04>;\n\t\t\tphandle = <0x05>;\n\t\t};\n\t};\n\n\tdcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"okay\";\n\t\tu-boot,dm-pre-reloc;\n\t\tphandle = <0x44>;\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <0x04>;\n\t\tinterrupts = <0x00 0x8f 0x04 0x00 0x90 0x04 0x00 0x91 0x04 0x00 0x92 0x04>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tfirmware {\n\n\t\tzynqmp-firmware {\n\t\t\tcompatible = \"xlnx,zynqmp-firmware\";\n\t\t\t#power-domain-cells = <0x01>;\n\t\t\tmethod = \"smc\";\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tphandle = <0x0c>;\n\n\t\t\tzynqmp-power {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <0x04>;\n\t\t\t\tinterrupts = <0x00 0x23 0x04>;\n\t\t\t\tmboxes = <0x05 0x00 0x05 0x01>;\n\t\t\t\tmbox-names = \"tx\\0rx\";\n\t\t\t\tphandle = <0x45>;\n\t\t\t};\n\n\t\t\tnvmem_firmware {\n\t\t\t\tcompatible = \"xlnx,zynqmp-nvmem-fw\";\n\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t#size-cells = <0x01>;\n\n\t\t\t\tsoc_revision@0 {\n\t\t\t\t\treg = <0x00 0x04>;\n\t\t\t\t\tphandle = <0x1e>;\n\t\t\t\t};\n\n\t\t\t\tefuse_dna@c {\n\t\t\t\t\treg = <0x0c 0x0c>;\n\t\t\t\t\tphandle = <0x46>;\n\t\t\t\t};\n\n\t\t\t\tefuse_usr0@20 {\n\t\t\t\t\treg = <0x20 0x04>;\n\t\t\t\t\tphandle = <0x47>;\n\t\t\t\t};\n\n\t\t\t\tefuse_usr1@24 {\n\t\t\t\t\treg = <0x24 0x04>;\n\t\t\t\t\tphandle = <0x48>;\n\t\t\t\t};\n\n\t\t\t\tefuse_usr2@28 {\n\t\t\t\t\treg = <0x28 0x04>;\n\t\t\t\t\tphandle = <0x49>;\n\t\t\t\t};\n\n\t\t\t\tefuse_usr3@2c {\n\t\t\t\t\treg = <0x2c 0x04>;\n\t\t\t\t\tphandle = <0x4a>;\n\t\t\t\t};\n\n\t\t\t\tefuse_usr4@30 {\n\t\t\t\t\treg = <0x30 0x04>;\n\t\t\t\t\tphandle = <0x4b>;\n\t\t\t\t};\n\n\t\t\t\tefuse_usr5@34 {\n\t\t\t\t\treg = <0x34 0x04>;\n\t\t\t\t\tphandle = <0x4c>;\n\t\t\t\t};\n\n\t\t\t\tefuse_usr6@38 {\n\t\t\t\t\treg = <0x38 0x04>;\n\t\t\t\t\tphandle = <0x4d>;\n\t\t\t\t};\n\n\t\t\t\tefuse_usr7@3c {\n\t\t\t\t\treg = <0x3c 0x04>;\n\t\t\t\t\tphandle = <0x4e>;\n\t\t\t\t};\n\n\t\t\t\tefuse_miscusr@40 {\n\t\t\t\t\treg = <0x40 0x04>;\n\t\t\t\t\tphandle = <0x4f>;\n\t\t\t\t};\n\n\t\t\t\tefuse_chash@50 {\n\t\t\t\t\treg = <0x50 0x04>;\n\t\t\t\t\tphandle = <0x50>;\n\t\t\t\t};\n\n\t\t\t\tefuse_pufmisc@54 {\n\t\t\t\t\treg = <0x54 0x04>;\n\t\t\t\t\tphandle = <0x51>;\n\t\t\t\t};\n\n\t\t\t\tefuse_sec@58 {\n\t\t\t\t\treg = <0x58 0x04>;\n\t\t\t\t\tphandle = <0x52>;\n\t\t\t\t};\n\n\t\t\t\tefuse_spkid@5c {\n\t\t\t\t\treg = <0x5c 0x04>;\n\t\t\t\t\tphandle = <0x53>;\n\t\t\t\t};\n\n\t\t\t\tefuse_ppk0hash@a0 {\n\t\t\t\t\treg = <0xa0 0x30>;\n\t\t\t\t\tphandle = <0x54>;\n\t\t\t\t};\n\n\t\t\t\tefuse_ppk1hash@d0 {\n\t\t\t\t\treg = <0xd0 0x30>;\n\t\t\t\t\tphandle = <0x55>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpcap {\n\t\t\t\tcompatible = \"xlnx,zynqmp-pcap-fpga\";\n\t\t\t\tclock-names = \"ref_clk\";\n\t\t\t\tclocks = <0x03 0x29>;\n\t\t\t\tphandle = <0x0b>;\n\t\t\t};\n\n\t\t\tzynqmp-aes {\n\t\t\t\tcompatible = \"xlnx,zynqmp-aes\";\n\t\t\t\tphandle = <0x56>;\n\t\t\t};\n\n\t\t\treset-controller {\n\t\t\t\tcompatible = \"xlnx,zynqmp-reset\";\n\t\t\t\t#reset-cells = <0x01>;\n\t\t\t\tphandle = <0x1c>;\n\t\t\t};\n\n\t\t\tpinctrl {\n\t\t\t\tcompatible = \"xlnx,zynqmp-pinctrl\";\n\t\t\t\tstatus = \"okay\";\n\t\t\t\tphandle = <0x57>;\n\n\t\t\t\ti2c0-default {\n\t\t\t\t\tphandle = <0x12>;\n\n\t\t\t\t\tmux {\n\t\t\t\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\t\t\t\tfunction = \"i2c0\";\n\t\t\t\t\t};\n\n\t\t\t\t\tconf {\n\t\t\t\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\t\t\t\tbias-pull-up;\n\t\t\t\t\t\tslew-rate = <0x01>;\n\t\t\t\t\t\tpower-source = <0x01>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\ti2c0-gpio {\n\t\t\t\t\tphandle = <0x13>;\n\n\t\t\t\t\tmux {\n\t\t\t\t\t\tgroups = \"gpio0_14_grp\\0gpio0_15_grp\";\n\t\t\t\t\t\tfunction = \"gpio0\";\n\t\t\t\t\t};\n\n\t\t\t\t\tconf {\n\t\t\t\t\t\tgroups = \"gpio0_14_grp\\0gpio0_15_grp\";\n\t\t\t\t\t\tslew-rate = <0x01>;\n\t\t\t\t\t\tpower-source = <0x01>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\ti2c1-default {\n\t\t\t\t\tphandle = <0x15>;\n\n\t\t\t\t\tmux {\n\t\t\t\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\t\t\t\tfunction = \"i2c1\";\n\t\t\t\t\t};\n\n\t\t\t\t\tconf {\n\t\t\t\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\t\t\t\tbias-pull-up;\n\t\t\t\t\t\tslew-rate = <0x01>;\n\t\t\t\t\t\tpower-source = <0x01>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\ti2c1-gpio {\n\t\t\t\t\tphandle = <0x16>;\n\n\t\t\t\t\tmux {\n\t\t\t\t\t\tgroups = \"gpio0_16_grp\\0gpio0_17_grp\";\n\t\t\t\t\t\tfunction = \"gpio0\";\n\t\t\t\t\t};\n\n\t\t\t\t\tconf {\n\t\t\t\t\t\tgroups = \"gpio0_16_grp\\0gpio0_17_grp\";\n\t\t\t\t\t\tslew-rate = <0x01>;\n\t\t\t\t\t\tpower-source = <0x01>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tuart0-default {\n\t\t\t\t\tphandle = <0x21>;\n\n\t\t\t\t\tmux {\n\t\t\t\t\t\tgroups = \"uart0_4_grp\";\n\t\t\t\t\t\tfunction = \"uart0\";\n\t\t\t\t\t};\n\n\t\t\t\t\tconf {\n\t\t\t\t\t\tgroups = \"uart0_4_grp\";\n\t\t\t\t\t\tslew-rate = <0x01>;\n\t\t\t\t\t\tpower-source = <0x01>;\n\t\t\t\t\t};\n\n\t\t\t\t\tconf-rx {\n\t\t\t\t\t\tpins = \"MIO18\";\n\t\t\t\t\t\tbias-high-impedance;\n\t\t\t\t\t};\n\n\t\t\t\t\tconf-tx {\n\t\t\t\t\t\tpins = \"MIO19\";\n\t\t\t\t\t\tbias-disable;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tuart1-default {\n\t\t\t\t\tphandle = <0x22>;\n\n\t\t\t\t\tmux {\n\t\t\t\t\t\tgroups = \"uart1_5_grp\";\n\t\t\t\t\t\tfunction = \"uart1\";\n\t\t\t\t\t};\n\n\t\t\t\t\tconf {\n\t\t\t\t\t\tgroups = \"uart1_5_grp\";\n\t\t\t\t\t\tslew-rate = <0x01>;\n\t\t\t\t\t\tpower-source = <0x01>;\n\t\t\t\t\t};\n\n\t\t\t\t\tconf-rx {\n\t\t\t\t\t\tpins = \"MIO21\";\n\t\t\t\t\t\tbias-high-impedance;\n\t\t\t\t\t};\n\n\t\t\t\t\tconf-tx {\n\t\t\t\t\t\tpins = \"MIO20\";\n\t\t\t\t\t\tbias-disable;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tusb0-default {\n\t\t\t\t\tphandle = <0x24>;\n\n\t\t\t\t\tmux {\n\t\t\t\t\t\tgroups = \"usb0_0_grp\";\n\t\t\t\t\t\tfunction = \"usb0\";\n\t\t\t\t\t};\n\n\t\t\t\t\tconf {\n\t\t\t\t\t\tgroups = \"usb0_0_grp\";\n\t\t\t\t\t\tslew-rate = <0x01>;\n\t\t\t\t\t\tpower-source = <0x01>;\n\t\t\t\t\t};\n\n\t\t\t\t\tconf-rx {\n\t\t\t\t\t\tpins = \"MIO52\\0MIO53\\0MIO55\";\n\t\t\t\t\t\tbias-high-impedance;\n\t\t\t\t\t};\n\n\t\t\t\t\tconf-tx {\n\t\t\t\t\t\tpins = \"MIO54\\0MIO56\\0MIO57\\0MIO58\\0MIO59\\0MIO60\\0MIO61\\0MIO62\\0MIO63\";\n\t\t\t\t\t\tbias-disable;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tgem3-default {\n\t\t\t\t\tphandle = <0x10>;\n\n\t\t\t\t\tmux {\n\t\t\t\t\t\tfunction = \"ethernet3\";\n\t\t\t\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\t\t\t};\n\n\t\t\t\t\tconf {\n\t\t\t\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\t\t\t\tslew-rate = <0x01>;\n\t\t\t\t\t\tpower-source = <0x01>;\n\t\t\t\t\t};\n\n\t\t\t\t\tconf-rx {\n\t\t\t\t\t\tpins = \"MIO70\\0MIO71\\0MIO72\\0MIO73\\0MIO74\\0MIO75\";\n\t\t\t\t\t\tbias-high-impedance;\n\t\t\t\t\t\tlow-power-disable;\n\t\t\t\t\t};\n\n\t\t\t\t\tconf-tx {\n\t\t\t\t\t\tpins = \"MIO64\\0MIO65\\0MIO66\\0MIO67\\0MIO68\\0MIO69\";\n\t\t\t\t\t\tbias-disable;\n\t\t\t\t\t\tlow-power-enable;\n\t\t\t\t\t};\n\n\t\t\t\t\tmux-mdio {\n\t\t\t\t\t\tfunction = \"mdio3\";\n\t\t\t\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\t\t\t};\n\n\t\t\t\t\tconf-mdio {\n\t\t\t\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\t\t\t\tslew-rate = <0x01>;\n\t\t\t\t\t\tpower-source = <0x01>;\n\t\t\t\t\t\tbias-disable;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tcan1-default {\n\t\t\t\t\tphandle = <0x0d>;\n\n\t\t\t\t\tmux {\n\t\t\t\t\t\tfunction = \"can1\";\n\t\t\t\t\t\tgroups = \"can1_6_grp\";\n\t\t\t\t\t};\n\n\t\t\t\t\tconf {\n\t\t\t\t\t\tgroups = \"can1_6_grp\";\n\t\t\t\t\t\tslew-rate = <0x01>;\n\t\t\t\t\t\tpower-source = <0x01>;\n\t\t\t\t\t};\n\n\t\t\t\t\tconf-rx {\n\t\t\t\t\t\tpins = \"MIO25\";\n\t\t\t\t\t\tbias-high-impedance;\n\t\t\t\t\t};\n\n\t\t\t\t\tconf-tx {\n\t\t\t\t\t\tpins = \"MIO24\";\n\t\t\t\t\t\tbias-disable;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tsdhci1-default {\n\t\t\t\t\tphandle = <0x1f>;\n\n\t\t\t\t\tmux {\n\t\t\t\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\t\t\t\tfunction = \"sdio1\";\n\t\t\t\t\t};\n\n\t\t\t\t\tconf {\n\t\t\t\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\t\t\t\tslew-rate = <0x01>;\n\t\t\t\t\t\tpower-source = <0x01>;\n\t\t\t\t\t\tbias-disable;\n\t\t\t\t\t};\n\n\t\t\t\t\tmux-cd {\n\t\t\t\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\t\t\t\tfunction = \"sdio1_cd\";\n\t\t\t\t\t};\n\n\t\t\t\t\tconf-cd {\n\t\t\t\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\t\t\t\tbias-high-impedance;\n\t\t\t\t\t\tbias-pull-up;\n\t\t\t\t\t\tslew-rate = <0x01>;\n\t\t\t\t\t\tpower-source = <0x01>;\n\t\t\t\t\t};\n\n\t\t\t\t\tmux-wp {\n\t\t\t\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\t\t\t\tfunction = \"sdio1_wp\";\n\t\t\t\t\t};\n\n\t\t\t\t\tconf-wp {\n\t\t\t\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\t\t\t\tbias-high-impedance;\n\t\t\t\t\t\tbias-pull-up;\n\t\t\t\t\t\tslew-rate = <0x01>;\n\t\t\t\t\t\tpower-source = <0x01>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tgpio-default {\n\t\t\t\t\tphandle = <0x11>;\n\n\t\t\t\t\tmux-sw {\n\t\t\t\t\t\tfunction = \"gpio0\";\n\t\t\t\t\t\tgroups = \"gpio0_22_grp\\0gpio0_23_grp\";\n\t\t\t\t\t};\n\n\t\t\t\t\tconf-sw {\n\t\t\t\t\t\tgroups = \"gpio0_22_grp\\0gpio0_23_grp\";\n\t\t\t\t\t\tslew-rate = <0x01>;\n\t\t\t\t\t\tpower-source = <0x01>;\n\t\t\t\t\t};\n\n\t\t\t\t\tmux-msp {\n\t\t\t\t\t\tfunction = \"gpio0\";\n\t\t\t\t\t\tgroups = \"gpio0_13_grp\\0gpio0_38_grp\";\n\t\t\t\t\t};\n\n\t\t\t\t\tconf-msp {\n\t\t\t\t\t\tgroups = \"gpio0_13_grp\\0gpio0_38_grp\";\n\t\t\t\t\t\tslew-rate = <0x01>;\n\t\t\t\t\t\tpower-source = <0x01>;\n\t\t\t\t\t};\n\n\t\t\t\t\tconf-pull-up {\n\t\t\t\t\t\tpins = \"MIO22\\0MIO23\";\n\t\t\t\t\t\tbias-pull-up;\n\t\t\t\t\t};\n\n\t\t\t\t\tconf-pull-none {\n\t\t\t\t\t\tpins = \"MIO13\\0MIO38\";\n\t\t\t\t\t\tbias-disable;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tsha384 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-keccak-384\";\n\t\t\t\tphandle = <0x58>;\n\t\t\t};\n\n\t\t\tzynqmp-rsa {\n\t\t\t\tcompatible = \"xlnx,zynqmp-rsa\";\n\t\t\t\tphandle = <0x59>;\n\t\t\t};\n\n\t\t\tgpio {\n\t\t\t\tcompatible = \"xlnx,zynqmp-gpio-modepin\";\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <0x02>;\n\t\t\t\tphandle = <0x23>;\n\t\t\t};\n\n\t\t\tclock-controller {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <0x01>;\n\t\t\t\tcompatible = \"xlnx,zynqmp-clk\";\n\t\t\t\tclocks = <0x06 0x07 0x08 0x09 0x0a>;\n\t\t\t\tclock-names = \"pss_ref_clk\\0video_clk\\0pss_alt_ref_clk\\0aux_ref_clk\\0gt_crx_ref_clk\";\n\t\t\t\tphandle = <0x03>;\n\t\t\t};\n\t\t};\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <0x04>;\n\t\tinterrupts = <0x01 0x0d 0xf08 0x01 0x0e 0xf08 0x01 0x0b 0xf08 0x01 0x0a 0xf08>;\n\t};\n\n\tedac {\n\t\tcompatible = \"arm,cortex-a53-edac\";\n\t};\n\n\tfpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <0x0b>;\n\t\t#address-cells = <0x02>;\n\t\t#size-cells = <0x02>;\n\t\tranges;\n\t\tphandle = <0x5a>;\n\t};\n\n\tsmmu@fd800000 {\n\t\tcompatible = \"arm,mmu-500\";\n\t\treg = <0x00 0xfd800000 0x00 0x20000>;\n\t\t#iommu-cells = <0x01>;\n\t\tstatus = \"disabled\";\n\t\t#global-interrupts = <0x01>;\n\t\tinterrupt-parent = <0x04>;\n\t\tinterrupts = <0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04>;\n\t\tphandle = <0x0e>;\n\t};\n\n\taxi {\n\t\tcompatible = \"simple-bus\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#address-cells = <0x02>;\n\t\t#size-cells = <0x02>;\n\t\tranges;\n\t\tphandle = <0x5b>;\n\n\t\tcan@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\\0pclk\";\n\t\t\treg = <0x00 0xff060000 0x00 0x1000>;\n\t\t\tinterrupts = <0x00 0x17 0x04>;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <0x0c 0x2f>;\n\t\t\tclocks = <0x03 0x3f 0x03 0x1f>;\n\t\t\tphandle = <0x5c>;\n\t\t};\n\n\t\tcan@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"can_clk\\0pclk\";\n\t\t\treg = <0x00 0xff070000 0x00 0x1000>;\n\t\t\tinterrupts = <0x00 0x18 0x04>;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <0x0c 0x30>;\n\t\t\tclocks = <0x03 0x40 0x03 0x1f>;\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <0x0d>;\n\t\t\tphandle = <0x5d>;\n\t\t};\n\n\t\tcci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x00 0xfd6e0000 0x00 0x9000>;\n\t\t\tranges = <0x00 0x00 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x01>;\n\t\t\tphandle = <0x5e>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <0x04>;\n\t\t\t\tinterrupts = <0x00 0x7b 0x04 0x00 0x7b 0x04 0x00 0x7b 0x04 0x00 0x7b 0x04 0x00 0x7b 0x04>;\n\t\t\t};\n\t\t};\n\n\t\tdma@fd500000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x00 0xfd500000 0x00 0x1000>;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x7c 0x04>;\n\t\t\tclock-names = \"clk_main\\0clk_apb\";\n\t\t\txlnx,bus-width = <0x80>;\n\t\t\t#stream-id-cells = <0x01>;\n\t\t\tiommus = <0x0e 0x14e8>;\n\t\t\tpower-domains = <0x0c 0x2a>;\n\t\t\tclocks = <0x03 0x13 0x03 0x1f>;\n\t\t\tphandle = <0x5f>;\n\t\t};\n\n\t\tdma@fd510000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x00 0xfd510000 0x00 0x1000>;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x7d 0x04>;\n\t\t\tclock-names = \"clk_main\\0clk_apb\";\n\t\t\txlnx,bus-width = <0x80>;\n\t\t\t#stream-id-cells = <0x01>;\n\t\t\tiommus = <0x0e 0x14e9>;\n\t\t\tpower-domains = <0x0c 0x2a>;\n\t\t\tclocks = <0x03 0x13 0x03 0x1f>;\n\t\t\tphandle = <0x60>;\n\t\t};\n\n\t\tdma@fd520000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x00 0xfd520000 0x00 0x1000>;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x7e 0x04>;\n\t\t\tclock-names = \"clk_main\\0clk_apb\";\n\t\t\txlnx,bus-width = <0x80>;\n\t\t\t#stream-id-cells = <0x01>;\n\t\t\tiommus = <0x0e 0x14ea>;\n\t\t\tpower-domains = <0x0c 0x2a>;\n\t\t\tclocks = <0x03 0x13 0x03 0x1f>;\n\t\t\tphandle = <0x61>;\n\t\t};\n\n\t\tdma@fd530000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x00 0xfd530000 0x00 0x1000>;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x7f 0x04>;\n\t\t\tclock-names = \"clk_main\\0clk_apb\";\n\t\t\txlnx,bus-width = <0x80>;\n\t\t\t#stream-id-cells = <0x01>;\n\t\t\tiommus = <0x0e 0x14eb>;\n\t\t\tpower-domains = <0x0c 0x2a>;\n\t\t\tclocks = <0x03 0x13 0x03 0x1f>;\n\t\t\tphandle = <0x62>;\n\t\t};\n\n\t\tdma@fd540000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x00 0xfd540000 0x00 0x1000>;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x80 0x04>;\n\t\t\tclock-names = \"clk_main\\0clk_apb\";\n\t\t\txlnx,bus-width = <0x80>;\n\t\t\t#stream-id-cells = <0x01>;\n\t\t\tiommus = <0x0e 0x14ec>;\n\t\t\tpower-domains = <0x0c 0x2a>;\n\t\t\tclocks = <0x03 0x13 0x03 0x1f>;\n\t\t\tphandle = <0x63>;\n\t\t};\n\n\t\tdma@fd550000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x00 0xfd550000 0x00 0x1000>;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x81 0x04>;\n\t\t\tclock-names = \"clk_main\\0clk_apb\";\n\t\t\txlnx,bus-width = <0x80>;\n\t\t\t#stream-id-cells = <0x01>;\n\t\t\tiommus = <0x0e 0x14ed>;\n\t\t\tpower-domains = <0x0c 0x2a>;\n\t\t\tclocks = <0x03 0x13 0x03 0x1f>;\n\t\t\tphandle = <0x64>;\n\t\t};\n\n\t\tdma@fd560000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x00 0xfd560000 0x00 0x1000>;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x82 0x04>;\n\t\t\tclock-names = \"clk_main\\0clk_apb\";\n\t\t\txlnx,bus-width = <0x80>;\n\t\t\t#stream-id-cells = <0x01>;\n\t\t\tiommus = <0x0e 0x14ee>;\n\t\t\tpower-domains = <0x0c 0x2a>;\n\t\t\tclocks = <0x03 0x13 0x03 0x1f>;\n\t\t\tphandle = <0x65>;\n\t\t};\n\n\t\tdma@fd570000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x00 0xfd570000 0x00 0x1000>;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x83 0x04>;\n\t\t\tclock-names = \"clk_main\\0clk_apb\";\n\t\t\txlnx,bus-width = <0x80>;\n\t\t\t#stream-id-cells = <0x01>;\n\t\t\tiommus = <0x0e 0x14ef>;\n\t\t\tpower-domains = <0x0c 0x2a>;\n\t\t\tclocks = <0x03 0x13 0x03 0x1f>;\n\t\t\tphandle = <0x66>;\n\t\t};\n\n\t\tinterrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\";\n\t\t\t#interrupt-cells = <0x03>;\n\t\t\treg = <0x00 0xf9010000 0x00 0x10000 0x00 0xf9020000 0x00 0x20000 0x00 0xf9040000 0x00 0x20000 0x00 0xf9060000 0x00 0x20000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x01 0x09 0xf04>;\n\t\t\tphandle = <0x04>;\n\t\t};\n\n\t\tgpu@fd4b0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"arm,mali-400\\0arm,mali-utgard\";\n\t\t\treg = <0x00 0xfd4b0000 0x00 0x10000>;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x84 0x04>;\n\t\t\tinterrupt-names = \"IRQGP\\0IRQGPMMU\\0IRQPP0\\0IRQPPMMU0\\0IRQPP1\\0IRQPPMMU1\";\n\t\t\tclock-names = \"gpu\\0gpu_pp0\\0gpu_pp1\";\n\t\t\tpower-domains = <0x0c 0x3a>;\n\t\t\tclocks = <0x03 0x18 0x03 0x19 0x03 0x1a>;\n\t\t\tphandle = <0x67>;\n\t\t};\n\n\t\tdma@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x00 0xffa80000 0x00 0x1000>;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x4d 0x04>;\n\t\t\tclock-names = \"clk_main\\0clk_apb\";\n\t\t\txlnx,bus-width = <0x40>;\n\t\t\t#stream-id-cells = <0x01>;\n\t\t\tpower-domains = <0x0c 0x2b>;\n\t\t\tclocks = <0x03 0x44 0x03 0x1f>;\n\t\t\tphandle = <0x68>;\n\t\t};\n\n\t\tdma@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x00 0xffa90000 0x00 0x1000>;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x4e 0x04>;\n\t\t\tclock-names = \"clk_main\\0clk_apb\";\n\t\t\txlnx,bus-width = <0x40>;\n\t\t\t#stream-id-cells = <0x01>;\n\t\t\tpower-domains = <0x0c 0x2b>;\n\t\t\tclocks = <0x03 0x44 0x03 0x1f>;\n\t\t\tphandle = <0x69>;\n\t\t};\n\n\t\tdma@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x00 0xffaa0000 0x00 0x1000>;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x4f 0x04>;\n\t\t\tclock-names = \"clk_main\\0clk_apb\";\n\t\t\txlnx,bus-width = <0x40>;\n\t\t\t#stream-id-cells = <0x01>;\n\t\t\tpower-domains = <0x0c 0x2b>;\n\t\t\tclocks = <0x03 0x44 0x03 0x1f>;\n\t\t\tphandle = <0x6a>;\n\t\t};\n\n\t\tdma@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x00 0xffab0000 0x00 0x1000>;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x50 0x04>;\n\t\t\tclock-names = \"clk_main\\0clk_apb\";\n\t\t\txlnx,bus-width = <0x40>;\n\t\t\t#stream-id-cells = <0x01>;\n\t\t\tpower-domains = <0x0c 0x2b>;\n\t\t\tclocks = <0x03 0x44 0x03 0x1f>;\n\t\t\tphandle = <0x6b>;\n\t\t};\n\n\t\tdma@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x00 0xffac0000 0x00 0x1000>;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x51 0x04>;\n\t\t\tclock-names = \"clk_main\\0clk_apb\";\n\t\t\txlnx,bus-width = <0x40>;\n\t\t\t#stream-id-cells = <0x01>;\n\t\t\tpower-domains = <0x0c 0x2b>;\n\t\t\tclocks = <0x03 0x44 0x03 0x1f>;\n\t\t\tphandle = <0x6c>;\n\t\t};\n\n\t\tdma@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x00 0xffad0000 0x00 0x1000>;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x52 0x04>;\n\t\t\tclock-names = \"clk_main\\0clk_apb\";\n\t\t\txlnx,bus-width = <0x40>;\n\t\t\t#stream-id-cells = <0x01>;\n\t\t\tpower-domains = <0x0c 0x2b>;\n\t\t\tclocks = <0x03 0x44 0x03 0x1f>;\n\t\t\tphandle = <0x6d>;\n\t\t};\n\n\t\tdma@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x00 0xffae0000 0x00 0x1000>;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x53 0x04>;\n\t\t\tclock-names = \"clk_main\\0clk_apb\";\n\t\t\txlnx,bus-width = <0x40>;\n\t\t\t#stream-id-cells = <0x01>;\n\t\t\tpower-domains = <0x0c 0x2b>;\n\t\t\tclocks = <0x03 0x44 0x03 0x1f>;\n\t\t\tphandle = <0x6e>;\n\t\t};\n\n\t\tdma@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x00 0xffaf0000 0x00 0x1000>;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x54 0x04>;\n\t\t\tclock-names = \"clk_main\\0clk_apb\";\n\t\t\txlnx,bus-width = <0x40>;\n\t\t\t#stream-id-cells = <0x01>;\n\t\t\tpower-domains = <0x0c 0x2b>;\n\t\t\tclocks = <0x03 0x44 0x03 0x1f>;\n\t\t\tphandle = <0x6f>;\n\t\t};\n\n\t\tmemory-controller@fd070000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ddrc-2.40a\";\n\t\t\treg = <0x00 0xfd070000 0x00 0x30000>;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x70 0x04>;\n\t\t\tphandle = <0x70>;\n\t\t};\n\n\t\tnand-controller@ff100000 {\n\t\t\tcompatible = \"xlnx,zynqmp-nand-controller\\0arasan,nfc-v3p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x00 0xff100000 0x00 0x1000>;\n\t\t\tclock-names = \"controller\\0bus\";\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x0e 0x04>;\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\t#stream-id-cells = <0x01>;\n\t\t\tiommus = <0x0e 0x872>;\n\t\t\tpower-domains = <0x0c 0x2c>;\n\t\t\tclocks = <0x03 0x3c 0x03 0x1f>;\n\t\t\tphandle = <0x71>;\n\t\t};\n\n\t\tethernet@ff0b0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\\0cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x39 0x04 0x00 0x39 0x04>;\n\t\t\treg = <0x00 0xff0b0000 0x00 0x1000>;\n\t\t\tclock-names = \"pclk\\0hclk\\0tx_clk\\0rx_clk\\0tsu_clk\";\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\t#stream-id-cells = <0x01>;\n\t\t\tiommus = <0x0e 0x874>;\n\t\t\tpower-domains = <0x0c 0x1d>;\n\t\t\tclocks = <0x03 0x1f 0x03 0x68 0x03 0x2d 0x03 0x31 0x03 0x2c>;\n\t\t\tphandle = <0x72>;\n\t\t};\n\n\t\tethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\\0cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x3b 0x04 0x00 0x3b 0x04>;\n\t\t\treg = <0x00 0xff0c0000 0x00 0x1000>;\n\t\t\tclock-names = \"pclk\\0hclk\\0tx_clk\\0rx_clk\\0tsu_clk\";\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\t#stream-id-cells = <0x01>;\n\t\t\tiommus = <0x0e 0x875>;\n\t\t\tpower-domains = <0x0c 0x1e>;\n\t\t\tclocks = <0x03 0x1f 0x03 0x69 0x03 0x2e 0x03 0x32 0x03 0x2c>;\n\t\t\tphandle = <0x73>;\n\t\t};\n\n\t\tethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\\0cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x3d 0x04 0x00 0x3d 0x04>;\n\t\t\treg = <0x00 0xff0d0000 0x00 0x1000>;\n\t\t\tclock-names = \"pclk\\0hclk\\0tx_clk\\0rx_clk\\0tsu_clk\";\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\t#stream-id-cells = <0x01>;\n\t\t\tiommus = <0x0e 0x876>;\n\t\t\tpower-domains = <0x0c 0x1f>;\n\t\t\tclocks = <0x03 0x1f 0x03 0x6a 0x03 0x2f 0x03 0x33 0x03 0x2c>;\n\t\t\tphandle = <0x74>;\n\t\t};\n\n\t\tethernet@ff0e0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\\0cdns,gem\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x3f 0x04 0x00 0x3f 0x04>;\n\t\t\treg = <0x00 0xff0e0000 0x00 0x1000>;\n\t\t\tclock-names = \"pclk\\0hclk\\0tx_clk\\0rx_clk\\0tsu_clk\";\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\t#stream-id-cells = <0x01>;\n\t\t\tiommus = <0x0e 0x877>;\n\t\t\tpower-domains = <0x0c 0x20>;\n\t\t\tclocks = <0x03 0x1f 0x03 0x6b 0x03 0x30 0x03 0x34 0x03 0x2c>;\n\t\t\tphy-handle = <0x0f>;\n\t\t\tphy-mode = \"rgmii-id\";\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <0x10>;\n\t\t\tphandle = <0x75>;\n\n\t\t\tethernet-phy@c {\n\t\t\t\treg = <0x0c>;\n\t\t\t\tti,rx-internal-delay = <0x08>;\n\t\t\t\tti,tx-internal-delay = <0x0a>;\n\t\t\t\tti,fifo-depth = <0x01>;\n\t\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\t\tphandle = <0x0f>;\n\t\t\t};\n\t\t};\n\n\t\tgpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\t#gpio-cells = <0x02>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x10 0x04>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <0x02>;\n\t\t\treg = <0x00 0xff0a0000 0x00 0x1000>;\n\t\t\tpower-domains = <0x0c 0x2e>;\n\t\t\tclocks = <0x03 0x1f>;\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <0x11>;\n\t\t\tphandle = <0x14>;\n\t\t};\n\n\t\ti2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x11 0x04>;\n\t\t\treg = <0x00 0xff020000 0x00 0x1000>;\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tpower-domains = <0x0c 0x25>;\n\t\t\tclocks = <0x03 0x3d>;\n\t\t\tclock-frequency = <0x61a80>;\n\t\t\tpinctrl-names = \"default\\0gpio\";\n\t\t\tpinctrl-0 = <0x12>;\n\t\t\tpinctrl-1 = <0x13>;\n\t\t\tscl-gpios = <0x14 0x0e 0x00>;\n\t\t\tsda-gpios = <0x14 0x0f 0x00>;\n\t\t\tphandle = <0x76>;\n\n\t\t\tgpio@20 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x20>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <0x02>;\n\t\t\t\tgpio-line-names = \"PS_GTR_LAN_SEL0\\0PS_GTR_LAN_SEL1\\0PS_GTR_LAN_SEL2\\0PS_GTR_LAN_SEL3\\0PCI_CLK_DIR_SEL\\0IIC_MUX_RESET_B\\0GEM3_EXP_RESET_B\\0\\0\\0\\0\\0\\0\\0\\0\\0\";\n\t\t\t\tphandle = <0x77>;\n\n\t\t\t\tgtr-sel0-hog {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0x00 0x00>;\n\t\t\t\t\toutput-low;\n\t\t\t\t\tline-name = \"sel0\";\n\t\t\t\t};\n\n\t\t\t\tgtr-sel1-hog {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0x01 0x00>;\n\t\t\t\t\toutput-high;\n\t\t\t\t\tline-name = \"sel1\";\n\t\t\t\t};\n\n\t\t\t\tgtr-sel2-hog {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0x02 0x00>;\n\t\t\t\t\toutput-high;\n\t\t\t\t\tline-name = \"sel2\";\n\t\t\t\t};\n\n\t\t\t\tgtr-sel3-hog {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0x03 0x00>;\n\t\t\t\t\toutput-high;\n\t\t\t\t\tline-name = \"sel3\";\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <0x02>;\n\t\t\t\tgpio-line-names = \"VCCPSPLL_EN\\0MGTRAVCC_EN\\0MGTRAVTT_EN\\0VCCPSDDRPLL_EN\\0MIO26_PMU_INPUT_LS\\0PL_PMBUS_ALERT\\0PS_PMBUS_ALERT\\0MAXIM_PMBUS_ALERT\\0PL_DDR4_VTERM_EN\\0PL_DDR4_VPP_2V5_EN\\0PS_DIMM_VDDQ_TO_PSVCCO_ON\\0PS_DIMM_SUSPEND_EN\\0PS_DDR4_VTERM_EN\\0PS_DDR4_VPP_2V5_EN\\0\\0\";\n\t\t\t\tphandle = <0x78>;\n\t\t\t};\n\n\t\t\ti2c-mux@75 {\n\t\t\t\tcompatible = \"nxp,pca9544\";\n\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t#size-cells = <0x00>;\n\t\t\t\treg = <0x75>;\n\n\t\t\t\ti2c@0 {\n\t\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t\t#size-cells = <0x00>;\n\t\t\t\t\treg = <0x00>;\n\n\t\t\t\t\tina226@40 {\n\t\t\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t\t\t#io-channel-cells = <0x01>;\n\t\t\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\t\t\treg = <0x40>;\n\t\t\t\t\t\tshunt-resistor = <0x1388>;\n\t\t\t\t\t\tphandle = <0x2a>;\n\t\t\t\t\t};\n\n\t\t\t\t\tina226@41 {\n\t\t\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t\t\t#io-channel-cells = <0x01>;\n\t\t\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\t\t\treg = <0x41>;\n\t\t\t\t\t\tshunt-resistor = <0x1388>;\n\t\t\t\t\t\tphandle = <0x2b>;\n\t\t\t\t\t};\n\n\t\t\t\t\tina226@42 {\n\t\t\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t\t\t#io-channel-cells = <0x01>;\n\t\t\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\t\t\treg = <0x42>;\n\t\t\t\t\t\tshunt-resistor = <0x1388>;\n\t\t\t\t\t\tphandle = <0x2c>;\n\t\t\t\t\t};\n\n\t\t\t\t\tina226@43 {\n\t\t\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t\t\t#io-channel-cells = <0x01>;\n\t\t\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\t\t\treg = <0x43>;\n\t\t\t\t\t\tshunt-resistor = <0x1388>;\n\t\t\t\t\t\tphandle = <0x2d>;\n\t\t\t\t\t};\n\n\t\t\t\t\tina226@44 {\n\t\t\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t\t\t#io-channel-cells = <0x01>;\n\t\t\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\t\t\treg = <0x44>;\n\t\t\t\t\t\tshunt-resistor = <0x1388>;\n\t\t\t\t\t\tphandle = <0x2e>;\n\t\t\t\t\t};\n\n\t\t\t\t\tina226@45 {\n\t\t\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t\t\t#io-channel-cells = <0x01>;\n\t\t\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\t\t\treg = <0x45>;\n\t\t\t\t\t\tshunt-resistor = <0x1388>;\n\t\t\t\t\t\tphandle = <0x2f>;\n\t\t\t\t\t};\n\n\t\t\t\t\tina226@46 {\n\t\t\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t\t\t#io-channel-cells = <0x01>;\n\t\t\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\t\t\treg = <0x46>;\n\t\t\t\t\t\tshunt-resistor = <0x1388>;\n\t\t\t\t\t\tphandle = <0x30>;\n\t\t\t\t\t};\n\n\t\t\t\t\tina226@47 {\n\t\t\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t\t\t#io-channel-cells = <0x01>;\n\t\t\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\t\t\treg = <0x47>;\n\t\t\t\t\t\tshunt-resistor = <0x1388>;\n\t\t\t\t\t\tphandle = <0x31>;\n\t\t\t\t\t};\n\n\t\t\t\t\tina226@4a {\n\t\t\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t\t\t#io-channel-cells = <0x01>;\n\t\t\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\t\t\treg = <0x4a>;\n\t\t\t\t\t\tshunt-resistor = <0x1388>;\n\t\t\t\t\t\tphandle = <0x32>;\n\t\t\t\t\t};\n\n\t\t\t\t\tina226@4b {\n\t\t\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t\t\t#io-channel-cells = <0x01>;\n\t\t\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\t\t\treg = <0x4b>;\n\t\t\t\t\t\tshunt-resistor = <0x1388>;\n\t\t\t\t\t\tphandle = <0x33>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\ti2c@1 {\n\t\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t\t#size-cells = <0x00>;\n\t\t\t\t\treg = <0x01>;\n\n\t\t\t\t\tina226@40 {\n\t\t\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t\t\t#io-channel-cells = <0x01>;\n\t\t\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\t\t\treg = <0x40>;\n\t\t\t\t\t\tshunt-resistor = <0x7d0>;\n\t\t\t\t\t\tphandle = <0x34>;\n\t\t\t\t\t};\n\n\t\t\t\t\tina226@41 {\n\t\t\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t\t\t#io-channel-cells = <0x01>;\n\t\t\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\t\t\treg = <0x41>;\n\t\t\t\t\t\tshunt-resistor = <0x1388>;\n\t\t\t\t\t\tphandle = <0x35>;\n\t\t\t\t\t};\n\n\t\t\t\t\tina226@42 {\n\t\t\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t\t\t#io-channel-cells = <0x01>;\n\t\t\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\t\t\treg = <0x42>;\n\t\t\t\t\t\tshunt-resistor = <0x1388>;\n\t\t\t\t\t\tphandle = <0x36>;\n\t\t\t\t\t};\n\n\t\t\t\t\tina226@43 {\n\t\t\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t\t\t#io-channel-cells = <0x01>;\n\t\t\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\t\t\treg = <0x43>;\n\t\t\t\t\t\tshunt-resistor = <0x1388>;\n\t\t\t\t\t\tphandle = <0x37>;\n\t\t\t\t\t};\n\n\t\t\t\t\tina226@44 {\n\t\t\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t\t\t#io-channel-cells = <0x01>;\n\t\t\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\t\t\treg = <0x44>;\n\t\t\t\t\t\tshunt-resistor = <0x1388>;\n\t\t\t\t\t\tphandle = <0x38>;\n\t\t\t\t\t};\n\n\t\t\t\t\tina226@45 {\n\t\t\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t\t\t#io-channel-cells = <0x01>;\n\t\t\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\t\t\treg = <0x45>;\n\t\t\t\t\t\tshunt-resistor = <0x1388>;\n\t\t\t\t\t\tphandle = <0x39>;\n\t\t\t\t\t};\n\n\t\t\t\t\tina226@46 {\n\t\t\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t\t\t#io-channel-cells = <0x01>;\n\t\t\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\t\t\treg = <0x46>;\n\t\t\t\t\t\tshunt-resistor = <0x1388>;\n\t\t\t\t\t\tphandle = <0x3a>;\n\t\t\t\t\t};\n\n\t\t\t\t\tina226@47 {\n\t\t\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t\t\t#io-channel-cells = <0x01>;\n\t\t\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\t\t\treg = <0x47>;\n\t\t\t\t\t\tshunt-resistor = <0x1388>;\n\t\t\t\t\t\tphandle = <0x3b>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\ti2c@2 {\n\t\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t\t#size-cells = <0x00>;\n\t\t\t\t\treg = <0x02>;\n\n\t\t\t\t\tmax15301@a {\n\t\t\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\t\t\treg = <0x0a>;\n\t\t\t\t\t};\n\n\t\t\t\t\tmax15303@b {\n\t\t\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\t\t\treg = <0x0b>;\n\t\t\t\t\t};\n\n\t\t\t\t\tmax15303@10 {\n\t\t\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\t\t\treg = <0x10>;\n\t\t\t\t\t};\n\n\t\t\t\t\tmax15301@13 {\n\t\t\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\t\t\treg = <0x13>;\n\t\t\t\t\t};\n\n\t\t\t\t\tmax15303@14 {\n\t\t\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\t\t\treg = <0x14>;\n\t\t\t\t\t};\n\n\t\t\t\t\tmax15303@15 {\n\t\t\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\t\t\treg = <0x15>;\n\t\t\t\t\t};\n\n\t\t\t\t\tmax15303@16 {\n\t\t\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\t\t\treg = <0x16>;\n\t\t\t\t\t};\n\n\t\t\t\t\tmax15303@17 {\n\t\t\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\t\t\treg = <0x17>;\n\t\t\t\t\t};\n\n\t\t\t\t\tmax15301@18 {\n\t\t\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\t\t\treg = <0x18>;\n\t\t\t\t\t};\n\n\t\t\t\t\tmax15303@1a {\n\t\t\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\t\t\treg = <0x1a>;\n\t\t\t\t\t};\n\n\t\t\t\t\tmax15303@1d {\n\t\t\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\t\t\treg = <0x1d>;\n\t\t\t\t\t};\n\n\t\t\t\t\tmax20751@72 {\n\t\t\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\t\t\treg = <0x72>;\n\t\t\t\t\t};\n\n\t\t\t\t\tmax20751@73 {\n\t\t\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\t\t\treg = <0x73>;\n\t\t\t\t\t};\n\n\t\t\t\t\tmax15303@1b {\n\t\t\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\t\t\treg = <0x1b>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\ti2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x12 0x04>;\n\t\t\treg = <0x00 0xff030000 0x00 0x1000>;\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tpower-domains = <0x0c 0x26>;\n\t\t\tclocks = <0x03 0x3e>;\n\t\t\tclock-frequency = <0x61a80>;\n\t\t\tpinctrl-names = \"default\\0gpio\";\n\t\t\tpinctrl-0 = <0x15>;\n\t\t\tpinctrl-1 = <0x16>;\n\t\t\tscl-gpios = <0x14 0x10 0x00>;\n\t\t\tsda-gpios = <0x14 0x11 0x00>;\n\t\t\tphandle = <0x79>;\n\n\t\t\ti2c-mux@74 {\n\t\t\t\tcompatible = \"nxp,pca9548\";\n\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t#size-cells = <0x00>;\n\t\t\t\treg = <0x74>;\n\n\t\t\t\ti2c@0 {\n\t\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t\t#size-cells = <0x00>;\n\t\t\t\t\treg = <0x00>;\n\n\t\t\t\t\teeprom@54 {\n\t\t\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\t\t\treg = <0x54>;\n\t\t\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t\t\t#size-cells = <0x01>;\n\t\t\t\t\t\tphandle = <0x7a>;\n\n\t\t\t\t\t\tboard-sn@0 {\n\t\t\t\t\t\t\treg = <0x00 0x14>;\n\t\t\t\t\t\t\tphandle = <0x7b>;\n\t\t\t\t\t\t};\n\n\t\t\t\t\t\teth-mac@20 {\n\t\t\t\t\t\t\treg = <0x20 0x06>;\n\t\t\t\t\t\t\tphandle = <0x7c>;\n\t\t\t\t\t\t};\n\n\t\t\t\t\t\tboard-name@d0 {\n\t\t\t\t\t\t\treg = <0xd0 0x06>;\n\t\t\t\t\t\t\tphandle = <0x7d>;\n\t\t\t\t\t\t};\n\n\t\t\t\t\t\tboard-revision@e0 {\n\t\t\t\t\t\t\treg = <0xe0 0x03>;\n\t\t\t\t\t\t\tphandle = <0x7e>;\n\t\t\t\t\t\t};\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\ti2c@1 {\n\t\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t\t#size-cells = <0x00>;\n\t\t\t\t\treg = <0x01>;\n\n\t\t\t\t\tclock-generator@36 {\n\t\t\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\t\t\treg = <0x36>;\n\t\t\t\t\t\t#clock-cells = <0x02>;\n\t\t\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t\t\t#size-cells = <0x00>;\n\t\t\t\t\t\tclocks = <0x17>;\n\t\t\t\t\t\tclock-names = \"xtal\";\n\t\t\t\t\t\tclock-output-names = \"si5341\";\n\t\t\t\t\t\tphandle = <0x1b>;\n\n\t\t\t\t\t\tout@0 {\n\t\t\t\t\t\t\treg = <0x00>;\n\t\t\t\t\t\t\talways-on;\n\t\t\t\t\t\t\tphandle = <0x7f>;\n\t\t\t\t\t\t};\n\n\t\t\t\t\t\tout@2 {\n\t\t\t\t\t\t\treg = <0x02>;\n\t\t\t\t\t\t\talways-on;\n\t\t\t\t\t\t\tphandle = <0x80>;\n\t\t\t\t\t\t};\n\n\t\t\t\t\t\tout@3 {\n\t\t\t\t\t\t\treg = <0x03>;\n\t\t\t\t\t\t\talways-on;\n\t\t\t\t\t\t\tphandle = <0x81>;\n\t\t\t\t\t\t};\n\n\t\t\t\t\t\tout@4 {\n\t\t\t\t\t\t\treg = <0x04>;\n\t\t\t\t\t\t\talways-on;\n\t\t\t\t\t\t\tphandle = <0x82>;\n\t\t\t\t\t\t};\n\n\t\t\t\t\t\tout@5 {\n\t\t\t\t\t\t\treg = <0x05>;\n\t\t\t\t\t\t\talways-on;\n\t\t\t\t\t\t\tphandle = <0x83>;\n\t\t\t\t\t\t};\n\n\t\t\t\t\t\tout@6 {\n\t\t\t\t\t\t\treg = <0x06>;\n\t\t\t\t\t\t\talways-on;\n\t\t\t\t\t\t\tphandle = <0x84>;\n\t\t\t\t\t\t};\n\n\t\t\t\t\t\tout@7 {\n\t\t\t\t\t\t\treg = <0x07>;\n\t\t\t\t\t\t\talways-on;\n\t\t\t\t\t\t\tphandle = <0x85>;\n\t\t\t\t\t\t};\n\n\t\t\t\t\t\tout@9 {\n\t\t\t\t\t\t\treg = <0x09>;\n\t\t\t\t\t\t\talways-on;\n\t\t\t\t\t\t\tphandle = <0x86>;\n\t\t\t\t\t\t};\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\ti2c@2 {\n\t\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t\t#size-cells = <0x00>;\n\t\t\t\t\treg = <0x02>;\n\n\t\t\t\t\tclock-generator@5d {\n\t\t\t\t\t\t#clock-cells = <0x00>;\n\t\t\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\t\t\treg = <0x5d>;\n\t\t\t\t\t\ttemperature-stability = <0x32>;\n\t\t\t\t\t\tfactory-fout = <0x11e1a300>;\n\t\t\t\t\t\tclock-frequency = <0x11e1a300>;\n\t\t\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t\t\t\tphandle = <0x87>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\ti2c@3 {\n\t\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t\t#size-cells = <0x00>;\n\t\t\t\t\treg = <0x03>;\n\n\t\t\t\t\tclock-generator@5d {\n\t\t\t\t\t\t#clock-cells = <0x00>;\n\t\t\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\t\t\treg = <0x5d>;\n\t\t\t\t\t\ttemperature-stability = <0x32>;\n\t\t\t\t\t\tfactory-fout = <0x9502f90>;\n\t\t\t\t\t\tclock-frequency = <0x8d9ee20>;\n\t\t\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t\t\t\tphandle = <0x88>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\ti2c@4 {\n\t\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t\t#size-cells = <0x00>;\n\t\t\t\t\treg = <0x04>;\n\n\t\t\t\t\tclock-generator@69 {\n\t\t\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\t\t\treg = <0x69>;\n\t\t\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t\t\t#size-cells = <0x00>;\n\t\t\t\t\t\t#clock-cells = <0x01>;\n\t\t\t\t\t\tclocks = <0x18>;\n\t\t\t\t\t\tclock-names = \"xtal\";\n\t\t\t\t\t\tclock-output-names = \"si5328\";\n\t\t\t\t\t\tphandle = <0x89>;\n\n\t\t\t\t\t\tclk0@0 {\n\t\t\t\t\t\t\treg = <0x00>;\n\t\t\t\t\t\t\tclock-frequency = <0x19bfcc0>;\n\t\t\t\t\t\t\tphandle = <0x8a>;\n\t\t\t\t\t\t};\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\n\t\t\ti2c-mux@75 {\n\t\t\t\tcompatible = \"nxp,pca9548\";\n\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t#size-cells = <0x00>;\n\t\t\t\treg = <0x75>;\n\n\t\t\t\ti2c@0 {\n\t\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t\t#size-cells = <0x00>;\n\t\t\t\t\treg = <0x00>;\n\n\t\t\t\t\tad7291@2f {\n\t\t\t\t\t\tcompatible = \"adi,ad7291\";\n\t\t\t\t\t\treg = <0x2f>;\n\t\t\t\t\t};\n\n\t\t\t\t\teeprom@50 {\n\t\t\t\t\t\tcompatible = \"at24,24c02\";\n\t\t\t\t\t\treg = <0x50>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\ti2c@1 {\n\t\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t\t#size-cells = <0x00>;\n\t\t\t\t\treg = <0x01>;\n\t\t\t\t};\n\n\t\t\t\ti2c@2 {\n\t\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t\t#size-cells = <0x00>;\n\t\t\t\t\treg = <0x02>;\n\t\t\t\t};\n\n\t\t\t\ti2c@3 {\n\t\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t\t#size-cells = <0x00>;\n\t\t\t\t\treg = <0x03>;\n\t\t\t\t};\n\n\t\t\t\ti2c@4 {\n\t\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t\t#size-cells = <0x00>;\n\t\t\t\t\treg = <0x04>;\n\t\t\t\t};\n\n\t\t\t\ti2c@5 {\n\t\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t\t#size-cells = <0x00>;\n\t\t\t\t\treg = <0x05>;\n\t\t\t\t};\n\n\t\t\t\ti2c@6 {\n\t\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t\t#size-cells = <0x00>;\n\t\t\t\t\treg = <0x06>;\n\t\t\t\t};\n\n\t\t\t\ti2c@7 {\n\t\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t\t#size-cells = <0x00>;\n\t\t\t\t\treg = <0x07>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tmemory-controller@ff960000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ocmc-1.0\";\n\t\t\treg = <0x00 0xff960000 0x00 0x1000>;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x0a 0x04>;\n\t\t\tphandle = <0x8b>;\n\t\t};\n\n\t\tperf-monitor@ffa00000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x00 0xffa00000 0x00 0x10000>;\n\t\t\tinterrupts = <0x00 0x19 0x04>;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\txlnx,enable-profile = <0x00>;\n\t\t\txlnx,enable-trace = <0x00>;\n\t\t\txlnx,num-monitor-slots = <0x01>;\n\t\t\txlnx,enable-event-count = <0x01>;\n\t\t\txlnx,enable-event-log = <0x01>;\n\t\t\txlnx,have-sampled-metric-cnt = <0x01>;\n\t\t\txlnx,num-of-counters = <0x08>;\n\t\t\txlnx,metric-count-width = <0x20>;\n\t\t\txlnx,metrics-sample-count-width = <0x20>;\n\t\t\txlnx,global-count-width = <0x20>;\n\t\t\txlnx,metric-count-scale = <0x01>;\n\t\t\tclocks = <0x03 0x1f>;\n\t\t\tphandle = <0x8c>;\n\t\t};\n\n\t\tperf-monitor@fd0b0000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x00 0xfd0b0000 0x00 0x10000>;\n\t\t\tinterrupts = <0x00 0x7b 0x04>;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\txlnx,enable-profile = <0x00>;\n\t\t\txlnx,enable-trace = <0x00>;\n\t\t\txlnx,num-monitor-slots = <0x06>;\n\t\t\txlnx,enable-event-count = <0x01>;\n\t\t\txlnx,enable-event-log = <0x00>;\n\t\t\txlnx,have-sampled-metric-cnt = <0x01>;\n\t\t\txlnx,num-of-counters = <0x0a>;\n\t\t\txlnx,metric-count-width = <0x20>;\n\t\t\txlnx,metrics-sample-count-width = <0x20>;\n\t\t\txlnx,global-count-width = <0x20>;\n\t\t\txlnx,metric-count-scale = <0x01>;\n\t\t\tclocks = <0x03 0x1c>;\n\t\t\tphandle = <0x8d>;\n\t\t};\n\n\t\tperf-monitor@fd490000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x00 0xfd490000 0x00 0x10000>;\n\t\t\tinterrupts = <0x00 0x7b 0x04>;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\txlnx,enable-profile = <0x00>;\n\t\t\txlnx,enable-trace = <0x00>;\n\t\t\txlnx,num-monitor-slots = <0x01>;\n\t\t\txlnx,enable-event-count = <0x01>;\n\t\t\txlnx,enable-event-log = <0x00>;\n\t\t\txlnx,have-sampled-metric-cnt = <0x01>;\n\t\t\txlnx,num-of-counters = <0x08>;\n\t\t\txlnx,metric-count-width = <0x20>;\n\t\t\txlnx,metrics-sample-count-width = <0x20>;\n\t\t\txlnx,global-count-width = <0x20>;\n\t\t\txlnx,metric-count-scale = <0x01>;\n\t\t\tclocks = <0x03 0x1c>;\n\t\t\tphandle = <0x8e>;\n\t\t};\n\n\t\tperf-monitor@ffa10000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x00 0xffa10000 0x00 0x10000>;\n\t\t\tinterrupts = <0x00 0x19 0x04>;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\txlnx,enable-profile = <0x00>;\n\t\t\txlnx,enable-trace = <0x00>;\n\t\t\txlnx,num-monitor-slots = <0x01>;\n\t\t\txlnx,enable-event-count = <0x01>;\n\t\t\txlnx,enable-event-log = <0x01>;\n\t\t\txlnx,have-sampled-metric-cnt = <0x01>;\n\t\t\txlnx,num-of-counters = <0x08>;\n\t\t\txlnx,metric-count-width = <0x20>;\n\t\t\txlnx,metrics-sample-count-width = <0x20>;\n\t\t\txlnx,global-count-width = <0x20>;\n\t\t\txlnx,metric-count-scale = <0x01>;\n\t\t\tclocks = <0x03 0x1f>;\n\t\t\tphandle = <0x8f>;\n\t\t};\n\n\t\tpcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"okay\";\n\t\t\t#address-cells = <0x03>;\n\t\t\t#size-cells = <0x02>;\n\t\t\t#interrupt-cells = <0x01>;\n\t\t\tmsi-controller;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x76 0x04 0x00 0x75 0x04 0x00 0x74 0x04 0x00 0x73 0x04 0x00 0x72 0x04>;\n\t\t\tinterrupt-names = \"misc\\0dummy\\0intx\\0msi1\\0msi0\";\n\t\t\tmsi-parent = <0x19>;\n\t\t\treg = <0x00 0xfd0e0000 0x00 0x1000 0x00 0xfd480000 0x00 0x1000 0x80 0x00 0x00 0x1000000>;\n\t\t\treg-names = \"breg\\0pcireg\\0cfg\";\n\t\t\tranges = <0x2000000 0x00 0xe0000000 0x00 0xe0000000 0x00 0x10000000 0x43000000 0x06 0x00 0x06 0x00 0x02 0x00>;\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tinterrupt-map-mask = <0x00 0x00 0x00 0x07>;\n\t\t\tinterrupt-map = <0x00 0x00 0x00 0x01 0x1a 0x01 0x00 0x00 0x00 0x02 0x1a 0x02 0x00 0x00 0x00 0x03 0x1a 0x03 0x00 0x00 0x00 0x04 0x1a 0x04>;\n\t\t\t#stream-id-cells = <0x01>;\n\t\t\tiommus = <0x0e 0x4d0>;\n\t\t\tpower-domains = <0x0c 0x3b>;\n\t\t\tclocks = <0x03 0x17>;\n\t\t\tphandle = <0x19>;\n\n\t\t\tlegacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0x00>;\n\t\t\t\t#interrupt-cells = <0x01>;\n\t\t\t\tphandle = <0x1a>;\n\t\t\t};\n\t\t};\n\n\t\tspi@ff0f0000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-qspi-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"ref_clk\\0pclk\";\n\t\t\tinterrupts = <0x00 0x0f 0x04>;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tnum-cs = <0x01>;\n\t\t\treg = <0x00 0xff0f0000 0x00 0x1000 0x00 0xc0000000 0x00 0x8000000>;\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\t#stream-id-cells = <0x01>;\n\t\t\tiommus = <0x0e 0x873>;\n\t\t\tpower-domains = <0x0c 0x2d>;\n\t\t\tclocks = <0x03 0x35 0x03 0x1f>;\n\t\t\tis-dual = <0x01>;\n\t\t\tphandle = <0x90>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\\0jedec,spi-nor\";\n\t\t\t\t#address-cells = <0x01>;\n\t\t\t\t#size-cells = <0x01>;\n\t\t\t\treg = <0x00>;\n\t\t\t\tspi-tx-bus-width = <0x01>;\n\t\t\t\tspi-rx-bus-width = <0x04>;\n\t\t\t\tspi-max-frequency = <0x66ff300>;\n\n\t\t\t\tpartition@0 {\n\t\t\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\t\t\treg = <0x00 0x100000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@100000 {\n\t\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\t\treg = <0x100000 0x500000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@600000 {\n\t\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\t\treg = <0x600000 0x20000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@620000 {\n\t\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\t\treg = <0x620000 0x5e0000>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tphy@fd400000 {\n\t\t\tcompatible = \"xlnx,zynqmp-psgtr-v1.1\";\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x00 0xfd400000 0x00 0x40000 0x00 0xfd3d0000 0x00 0x1000>;\n\t\t\treg-names = \"serdes\\0siou\";\n\t\t\t#phy-cells = <0x04>;\n\t\t\tclocks = <0x1b 0x00 0x05 0x1b 0x00 0x03 0x1b 0x00 0x02 0x1b 0x00 0x00>;\n\t\t\tclock-names = \"ref0\\0ref1\\0ref2\\0ref3\";\n\t\t\tphandle = <0x1d>;\n\t\t};\n\n\t\trtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x00 0xffa60000 0x00 0x100>;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x1a 0x04 0x00 0x1b 0x04>;\n\t\t\tinterrupt-names = \"alarm\\0sec\";\n\t\t\tcalibration = <0x7fff>;\n\t\t\tphandle = <0x91>;\n\t\t};\n\n\t\tahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x00 0xfd0c0000 0x00 0x2000>;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x85 0x04>;\n\t\t\tpower-domains = <0x0c 0x1c>;\n\t\t\tresets = <0x1c 0x10>;\n\t\t\t#stream-id-cells = <0x04>;\n\t\t\tclocks = <0x03 0x16>;\n\t\t\tceva,p0-cominit-params = <0x18401828>;\n\t\t\tceva,p0-comwake-params = <0x614080e>;\n\t\t\tceva,p0-burst-params = <0x13084a06>;\n\t\t\tceva,p0-retry-params = <0x96a43ffc>;\n\t\t\tceva,p1-cominit-params = <0x18401828>;\n\t\t\tceva,p1-comwake-params = <0x614080e>;\n\t\t\tceva,p1-burst-params = <0x13084a06>;\n\t\t\tceva,p1-retry-params = <0x96a43ffc>;\n\t\t\tphy-names = \"sata-phy\";\n\t\t\tphys = <0x1d 0x03 0x01 0x01 0x01>;\n\t\t\tphandle = <0x92>;\n\t\t};\n\n\t\tmmc@ff160000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\\0arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n      xlnx,has-cd = <0x1>;\n      xlnx,has-power = <0x0>;\n      xlnx,has-wp = <0x1>;\n      disable-wp;\n      no-1-8-v;\n      broken-cd;\n      xlnx,mio-bank = <1>;\n      /* Do not run SD in HS mode from bootloader */\n      sdhci-caps-mask = <0 0x200000>;\n      sdhci-caps = <0 0>;\n      max-frequency = <19000000>;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x30 0x04>;\n\t\t\treg = <0x00 0xff160000 0x00 0x1000>;\n\t\t\tclock-names = \"clk_xin\\0clk_ahb\";\n\t\t\txlnx,device_id = <0x00>;\n\t\t\t#stream-id-cells = <0x01>;\n\t\t\tiommus = <0x0e 0x870>;\n\t\t\tnvmem-cells = <0x1e>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\t\t\t#clock-cells = <0x01>;\n\t\t\tclock-output-names = \"clk_out_sd0\\0clk_in_sd0\";\n\t\t\tpower-domains = <0x0c 0x27>;\n\t\t\tclocks = <0x03 0x36 0x03 0x1f>;\n\t\t\tphandle = <0x93>;\n\t\t};\n\n\t\tmmc@ff170000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\\0arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n      xlnx,has-cd = <0x1>;\n      xlnx,has-power = <0x0>;\n      xlnx,has-wp = <0x1>;\n      disable-wp;\n      no-1-8-v;\n      broken-cd;\n      xlnx,mio-bank = <1>;\n      /* Do not run SD in HS mode from bootloader */\n      sdhci-caps-mask = <0 0x200000>;\n      sdhci-caps = <0 0>;\n      max-frequency = <19000000>;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x31 0x04>;\n\t\t\treg = <0x00 0xff170000 0x00 0x1000>;\n\t\t\tclock-names = \"clk_xin\\0clk_ahb\";\n\t\t\txlnx,device_id = <0x01>;\n\t\t\t#stream-id-cells = <0x01>;\n\t\t\tiommus = <0x0e 0x871>;\n\t\t\tnvmem-cells = <0x1e>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\t\t\t#clock-cells = <0x01>;\n\t\t\tclock-output-names = \"clk_out_sd1\\0clk_in_sd1\";\n\t\t\tpower-domains = <0x0c 0x28>;\n\t\t\tclocks = <0x03 0x37 0x03 0x1f>;\n\t\t\t// no-1-8-v;\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <0x1f>;\n\t\t\t// xlnx,mio-bank = <0x01>;\n\t\t\tphandle = <0x94>;\n\t\t};\n\n\t\tspi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x13 0x04>;\n\t\t\treg = <0x00 0xff040000 0x00 0x1000>;\n\t\t\tclock-names = \"ref_clk\\0pclk\";\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tpower-domains = <0x0c 0x23>;\n\t\t\tclocks = <0x03 0x3a 0x03 0x1f>;\n\t\t\tphandle = <0x95>;\n\n\t\t\tad9361-phy@0 {\n\t\t\t\tcompatible = \"adi,ad9361\";\n\t\t\t\treg = <0x00>;\n\t\t\t\tspi-cpha;\n\t\t\t\tspi-max-frequency = <0x989680>;\n\t\t\t\tclocks = <0x20 0x00>;\n\t\t\t\tclock-names = \"ad9361_ext_refclk\";\n\t\t\t\tclock-output-names = \"rx_sampl_clk\\0tx_sampl_clk\";\n\t\t\t\t#clock-cells = <0x01>;\n\t\t\t\tadi,digital-interface-tune-skip-mode = <0x00>;\n\t\t\t\tadi,pp-tx-swap-enable;\n\t\t\t\tadi,pp-rx-swap-enable;\n\t\t\t\tadi,rx-frame-pulse-mode-enable;\n\t\t\t\tadi,lvds-mode-enable;\n\t\t\t\tadi,lvds-bias-mV = <0x96>;\n\t\t\t\tadi,lvds-rx-onchip-termination-enable;\n\t\t\t\tadi,rx-data-delay = <0x04>;\n\t\t\t\tadi,tx-fb-clock-delay = <0x07>;\n\t\t\t\tadi,dcxo-coarse-and-fine-tune = <0x08 0x1720>;\n\t\t\t\tadi,2rx-2tx-mode-enable;\n\t\t\t\tadi,frequency-division-duplex-mode-enable;\n\t\t\t\tadi,rx-rf-port-input-select = <0x00>;\n\t\t\t\tadi,tx-rf-port-input-select = <0x00>;\n\t\t\t\tadi,tx-attenuation-mdB = <0x2710>;\n\t\t\t\tadi,tx-lo-powerdown-managed-enable;\n\t\t\t\tadi,rf-rx-bandwidth-hz = <0x112a880>;\n\t\t\t\tadi,rf-tx-bandwidth-hz = <0x112a880>;\n\t\t\t\tadi,rx-synthesizer-frequency-hz = <0x00 0x8f0d1800>;\n\t\t\t\tadi,tx-synthesizer-frequency-hz = <0x00 0x92080880>;\n\t\t\t\tadi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;\n\t\t\t\tadi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;\n\t\t\t\tadi,gc-rx1-mode = <0x02>;\n\t\t\t\tadi,gc-rx2-mode = <0x02>;\n\t\t\t\tadi,gc-adc-ovr-sample-size = <0x04>;\n\t\t\t\tadi,gc-adc-small-overload-thresh = <0x2f>;\n\t\t\t\tadi,gc-adc-large-overload-thresh = <0x3a>;\n\t\t\t\tadi,gc-lmt-overload-high-thresh = <0x320>;\n\t\t\t\tadi,gc-lmt-overload-low-thresh = <0x2c0>;\n\t\t\t\tadi,gc-dec-pow-measurement-duration = <0x2000>;\n\t\t\t\tadi,gc-low-power-thresh = <0x18>;\n\t\t\t\tadi,mgc-inc-gain-step = <0x02>;\n\t\t\t\tadi,mgc-dec-gain-step = <0x02>;\n\t\t\t\tadi,mgc-split-table-ctrl-inp-gain-mode = <0x00>;\n\t\t\t\tadi,agc-attack-delay-extra-margin-us = <0x01>;\n\t\t\t\tadi,agc-outer-thresh-high = <0x05>;\n\t\t\t\tadi,agc-outer-thresh-high-dec-steps = <0x02>;\n\t\t\t\tadi,agc-inner-thresh-high = <0x0a>;\n\t\t\t\tadi,agc-inner-thresh-high-dec-steps = <0x01>;\n\t\t\t\tadi,agc-inner-thresh-low = <0x0c>;\n\t\t\t\tadi,agc-inner-thresh-low-inc-steps = <0x01>;\n\t\t\t\tadi,agc-outer-thresh-low = <0x12>;\n\t\t\t\tadi,agc-outer-thresh-low-inc-steps = <0x02>;\n\t\t\t\tadi,agc-adc-small-overload-exceed-counter = <0x0a>;\n\t\t\t\tadi,agc-adc-large-overload-exceed-counter = <0x0a>;\n\t\t\t\tadi,agc-adc-large-overload-inc-steps = <0x07>;\n\t\t\t\tadi,agc-lmt-overload-large-exceed-counter = <0x0a>;\n\t\t\t\tadi,agc-lmt-overload-small-exceed-counter = <0x0a>;\n\t\t\t\tadi,agc-lmt-overload-large-inc-steps = <0x07>;\n\t\t\t\tadi,agc-gain-update-interval-us = <0x3e8>;\n\t\t\t\tadi,fagc-dec-pow-measurement-duration = <0x10>;\n        adi,fagc-adc-large-overload-inc-steps = <0x07>;\n\t\t\t\tadi,fagc-lp-thresh-increment-steps = <0x01>;\n\t\t\t\tadi,fagc-lp-thresh-increment-time = <0x05>;\n\t\t\t\tadi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x08>;\n        adi,fagc-dig-sat-ovrg-enable;\n\t\t\t\tadi,fagc-final-overrange-count = <0x03>;\n\t\t\t\tadi,fagc-gain-index-type-after-exit-rx-mode = <0x00>;\n\t\t\t\tadi,fagc-lmt-final-settling-steps = <0x01>;\n\t\t\t\tadi,fagc-lock-level = <0x0a>;\n\t\t\t\tadi,fagc-lock-level-gain-increase-upper-limit = <0x05>;\n\t\t\t\tadi,fagc-lock-level-lmt-gain-increase-enable;\n\t\t\t\tadi,fagc-lpf-final-settling-steps = <0x01>;\n\t\t\t\tadi,fagc-optimized-gain-offset = <0x05>;\n\t\t\t\tadi,fagc-power-measurement-duration-in-state5 = <0x10>;\n\t\t\t\tadi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;\n\t\t\t\tadi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0x0a>;\n\t\t\t\tadi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x00>;\n\t\t\t\tadi,fagc-rst-gla-large-adc-overload-enable;\n\t\t\t\tadi,fagc-rst-gla-large-lmt-overload-enable;\n\t\t\t\tadi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0x0a>;\n\t\t\t\tadi,fagc-state-wait-time-ns = <0x104>;\n\t\t\t\tadi,fagc-use-last-lock-level-for-set-gain-enable;\n\t\t\t\tadi,rssi-restart-mode = <0x03>;\n\t\t\t\tadi,rssi-delay = <0x01>;\n\t\t\t\tadi,rssi-wait = <0x01>;\n\t\t\t\tadi,rssi-duration = <0x3e8>;\n\t\t\t\tadi,ctrl-outs-index = <0x00>;\n\t\t\t\tadi,ctrl-outs-enable-mask = <0xff>;\n\t\t\t\tadi,temp-sense-measurement-interval-ms = <0x3e8>;\n\t\t\t\tadi,temp-sense-offset-signed = <0xce>;\n\t\t\t\tadi,temp-sense-periodic-measurement-enable;\n\t\t\t\tadi,aux-dac-manual-mode-enable;\n\t\t\t\tadi,aux-dac1-default-value-mV = <0x00>;\n\t\t\t\tadi,aux-dac1-rx-delay-us = <0x00>;\n\t\t\t\tadi,aux-dac1-tx-delay-us = <0x00>;\n\t\t\t\tadi,aux-dac2-default-value-mV = <0x00>;\n\t\t\t\tadi,aux-dac2-rx-delay-us = <0x00>;\n\t\t\t\tadi,aux-dac2-tx-delay-us = <0x00>;\n\t\t\t\ten_agc-gpios = <0x14 0x7a 0x00>;\n\t\t\t\tsync-gpios = <0x14 0x7b 0x00>;\n\t\t\t\treset-gpios = <0x14 0x7c 0x00>;\n\t\t\t\tenable-gpios = <0x14 0x7d 0x00>;\n\t\t\t\ttxnrx-gpios = <0x14 0x7e 0x00>;\n\t\t\t\tphandle = <0x3d>;\n\t\t\t};\n\t\t};\n\n\t\tspi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x14 0x04>;\n\t\t\treg = <0x00 0xff050000 0x00 0x1000>;\n\t\t\tclock-names = \"ref_clk\\0pclk\";\n\t\t\t#address-cells = <0x01>;\n\t\t\t#size-cells = <0x00>;\n\t\t\tpower-domains = <0x0c 0x24>;\n\t\t\tclocks = <0x03 0x3b 0x03 0x1f>;\n\t\t\tphandle = <0x96>;\n\t\t};\n\n\t\ttimer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x24 0x04 0x00 0x25 0x04 0x00 0x26 0x04>;\n\t\t\treg = <0x00 0xff110000 0x00 0x1000>;\n\t\t\ttimer-width = <0x20>;\n\t\t\tpower-domains = <0x0c 0x18>;\n\t\t\tclocks = <0x03 0x1f>;\n\t\t\tphandle = <0x97>;\n\t\t};\n\n\t\ttimer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x27 0x04 0x00 0x28 0x04 0x00 0x29 0x04>;\n\t\t\treg = <0x00 0xff120000 0x00 0x1000>;\n\t\t\ttimer-width = <0x20>;\n\t\t\tpower-domains = <0x0c 0x19>;\n\t\t\tclocks = <0x03 0x1f>;\n\t\t\tphandle = <0x98>;\n\t\t};\n\n\t\ttimer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x2a 0x04 0x00 0x2b 0x04 0x00 0x2c 0x04>;\n\t\t\treg = <0x00 0xff130000 0x00 0x1000>;\n\t\t\ttimer-width = <0x20>;\n\t\t\tpower-domains = <0x0c 0x1a>;\n\t\t\tclocks = <0x03 0x1f>;\n\t\t\tphandle = <0x99>;\n\t\t};\n\n\t\ttimer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x2d 0x04 0x00 0x2e 0x04 0x00 0x2f 0x04>;\n\t\t\treg = <0x00 0xff140000 0x00 0x1000>;\n\t\t\ttimer-width = <0x20>;\n\t\t\tpower-domains = <0x0c 0x1b>;\n\t\t\tclocks = <0x03 0x1f>;\n\t\t\tphandle = <0x9a>;\n\t\t};\n\n\t\tserial@ff000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"cdns,uart-r1p12\\0xlnx,xuartps\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x15 0x04>;\n\t\t\treg = <0x00 0xff000000 0x00 0x1000>;\n\t\t\tclock-names = \"uart_clk\\0pclk\";\n\t\t\tpower-domains = <0x0c 0x21>;\n\t\t\tclocks = <0x03 0x38 0x03 0x1f>;\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <0x21>;\n\t\t\tphandle = <0x9b>;\n\t\t};\n\n\t\tserial@ff010000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"cdns,uart-r1p12\\0xlnx,xuartps\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x16 0x04>;\n\t\t\treg = <0x00 0xff010000 0x00 0x1000>;\n\t\t\tclock-names = \"uart_clk\\0pclk\";\n\t\t\tpower-domains = <0x0c 0x22>;\n\t\t\tclocks = <0x03 0x39 0x03 0x1f>;\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <0x22>;\n\t\t\tphandle = <0x9c>;\n\t\t};\n\n\t\tusb0@ff9d0000 {\n\t\t\t#address-cells = <0x02>;\n\t\t\t#size-cells = <0x02>;\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x00 0xff9d0000 0x00 0x100>;\n\t\t\tclock-names = \"bus_clk\\0ref_clk\";\n\t\t\tpower-domains = <0x0c 0x16>;\n\t\t\tresets = <0x1c 0x3b 0x1c 0x3d 0x1c 0x3f>;\n\t\t\treset-names = \"usb_crst\\0usb_hibrst\\0usb_apbrst\";\n\t\t\treset-gpio = <0x23 0x01 0x00>;\n\t\t\tranges;\n\t\t\tnvmem-cells = <0x1e>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\t\t\tclocks = <0x03 0x20 0x03 0x22>;\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <0x24>;\n\t\t\tphandle = <0x9d>;\n\n\t\t\tdwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"okay\";\n\t\t\t\treg = <0x00 0xfe200000 0x00 0x40000>;\n\t\t\t\tinterrupt-parent = <0x04>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\\0otg\\0hiber\";\n\t\t\t\tinterrupts = <0x00 0x41 0x04 0x00 0x45 0x04 0x00 0x4b 0x04>;\n\t\t\t\t#stream-id-cells = <0x01>;\n\t\t\t\tiommus = <0x0e 0x860>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,enable_guctl1_resume_quirk;\n\t\t\t\tsnps,enable_guctl1_ipd_quirk;\n\t\t\t\tsnps,xhci-stream-quirk;\n\t\t\t\tdr_mode = \"otg\";\n\t\t\t\tsnps,usb3_lpm_capable;\n\t\t\t\tphy-names = \"usb3-phy\";\n\t\t\t\tphys = <0x1d 0x02 0x04 0x00 0x02>;\n\t\t\t\tmaximum-speed = \"super-speed\";\n\t\t\t\tphandle = <0x9e>;\n\t\t\t};\n\t\t};\n\n\t\tusb1@ff9e0000 {\n\t\t\t#address-cells = <0x02>;\n\t\t\t#size-cells = <0x02>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x00 0xff9e0000 0x00 0x100>;\n\t\t\tclock-names = \"bus_clk\\0ref_clk\";\n\t\t\tpower-domains = <0x0c 0x17>;\n\t\t\tresets = <0x1c 0x3c 0x1c 0x3e 0x1c 0x40>;\n\t\t\treset-names = \"usb_crst\\0usb_hibrst\\0usb_apbrst\";\n\t\t\tranges;\n\t\t\tnvmem-cells = <0x1e>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\t\t\tclocks = <0x03 0x21 0x03 0x22>;\n\t\t\tphandle = <0x9f>;\n\n\t\t\tdwc3@fe300000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x00 0xfe300000 0x00 0x40000>;\n\t\t\t\tinterrupt-parent = <0x04>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\\0otg\\0hiber\";\n\t\t\t\tinterrupts = <0x00 0x46 0x04 0x00 0x4a 0x04 0x00 0x4c 0x04>;\n\t\t\t\t#stream-id-cells = <0x01>;\n\t\t\t\tiommus = <0x0e 0x861>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,enable_guctl1_resume_quirk;\n\t\t\t\tsnps,enable_guctl1_ipd_quirk;\n\t\t\t\tsnps,xhci-stream-quirk;\n\t\t\t\tphandle = <0xa0>;\n\t\t\t};\n\t\t};\n\n\t\twatchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x71 0x01>;\n\t\t\treg = <0x00 0xfd4d0000 0x00 0x1000>;\n\t\t\ttimeout-sec = <0x3c>;\n\t\t\treset-on-timeout;\n\t\t\tclocks = <0x03 0x4b>;\n\t\t\tphandle = <0xa1>;\n\t\t};\n\n\t\twatchdog@ff150000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x34 0x01>;\n\t\t\treg = <0x00 0xff150000 0x00 0x1000>;\n\t\t\ttimeout-sec = <0x0a>;\n\t\t\tclocks = <0x03 0x70>;\n\t\t\tphandle = <0xa2>;\n\t\t};\n\n\t\tams@ffa50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ams\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tinterrupts = <0x00 0x38 0x04>;\n\t\t\tinterrupt-names = \"ams-irq\";\n\t\t\treg = <0x00 0xffa50000 0x00 0x800>;\n\t\t\treg-names = \"ams-base\";\n\t\t\t#address-cells = <0x02>;\n\t\t\t#size-cells = <0x02>;\n\t\t\t#io-channel-cells = <0x01>;\n\t\t\tranges;\n\t\t\tclocks = <0x03 0x46>;\n\t\t\tphandle = <0xa3>;\n\n\t\t\tams_ps@ffa50800 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-ps\";\n\t\t\t\tstatus = \"okay\";\n\t\t\t\treg = <0x00 0xffa50800 0x00 0x400>;\n\t\t\t\tphandle = <0xa4>;\n\t\t\t};\n\n\t\t\tams_pl@ffa50c00 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-pl\";\n\t\t\t\tstatus = \"okay\";\n\t\t\t\treg = <0x00 0xffa50c00 0x00 0x400>;\n\t\t\t\tphandle = <0xa5>;\n\t\t\t};\n\t\t};\n\n\t\tdma-controller@fd4c0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dpdma\";\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x00 0xfd4c0000 0x00 0x1000>;\n\t\t\tinterrupts = <0x00 0x7a 0x04>;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\tclock-names = \"axi_clk\";\n\t\t\tpower-domains = <0x0c 0x29>;\n\t\t\tdma-channels = <0x06>;\n\t\t\t#stream-id-cells = <0x01>;\n\t\t\tiommus = <0x0e 0xce4>;\n\t\t\t#dma-cells = <0x01>;\n\t\t\tclocks = <0x03 0x14>;\n\t\t\tphandle = <0x25>;\n\t\t};\n\n\t\tdisplay@fd4a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dpsub-1.7\";\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x00 0xfd4a0000 0x00 0x1000 0x00 0xfd4aa000 0x00 0x1000 0x00 0xfd4ab000 0x00 0x1000 0x00 0xfd4ac000 0x00 0x1000>;\n\t\t\treg-names = \"dp\\0blend\\0av_buf\\0aud\";\n\t\t\tinterrupts = <0x00 0x77 0x04>;\n\t\t\tinterrupt-parent = <0x04>;\n\t\t\t#stream-id-cells = <0x01>;\n\t\t\tiommus = <0x0e 0xce3>;\n\t\t\tclock-names = \"dp_apb_clk\\0dp_aud_clk\\0dp_vtc_pixel_clk_in\";\n\t\t\tpower-domains = <0x0c 0x29>;\n\t\t\tresets = <0x1c 0x03>;\n\t\t\tdma-names = \"vid0\\0vid1\\0vid2\\0gfx0\";\n\t\t\tdmas = <0x25 0x00 0x25 0x01 0x25 0x02 0x25 0x03>;\n\t\t\tclocks = <0x26 0x03 0x11 0x03 0x10>;\n\t\t\tphy-names = \"dp-phy0\";\n\t\t\tphys = <0x1d 0x01 0x06 0x00 0x03>;\n\t\t\tphandle = <0xa6>;\n\n\t\t\ti2c-bus {\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_codec0 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-codec\";\n\t\t\t\tclock-names = \"aud_clk\";\n\t\t\t\tclocks = <0x03 0x11>;\n\t\t\t\tstatus = \"okay\";\n\t\t\t\tphandle = <0x29>;\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_pcm0 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\t\t\tdmas = <0x25 0x04>;\n\t\t\t\tdma-names = \"tx\";\n\t\t\t\tstatus = \"okay\";\n\t\t\t\tphandle = <0x27>;\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_pcm1 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\t\t\tdmas = <0x25 0x05>;\n\t\t\t\tdma-names = \"tx\";\n\t\t\t\tstatus = \"okay\";\n\t\t\t\tphandle = <0x28>;\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_card {\n\t\t\t\tcompatible = \"xlnx,dp-snd-card\";\n\t\t\t\txlnx,dp-snd-pcm = <0x27 0x28>;\n\t\t\t\txlnx,dp-snd-codec = <0x29>;\n\t\t\t\tstatus = \"okay\";\n\t\t\t\tphandle = <0xa7>;\n\t\t\t};\n\t\t};\n\t};\n\n\tfclk0 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <0x03 0x47>;\n\t\tphandle = <0xa8>;\n\t};\n\n\tfclk1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <0x03 0x48>;\n\t\tphandle = <0xa9>;\n\t};\n\n\tfclk2 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <0x03 0x49>;\n\t\tphandle = <0xaa>;\n\t};\n\n\tfclk3 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <0x03 0x4a>;\n\t\tphandle = <0xab>;\n\t};\n\n\tpss_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x00>;\n\t\tclock-frequency = <0x1fca055>;\n\t\tphandle = <0x06>;\n\t};\n\n\tvideo_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x00>;\n\t\tclock-frequency = <0x19bfcc0>;\n\t\tphandle = <0x07>;\n\t};\n\n\tpss_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x00>;\n\t\tclock-frequency = <0x00>;\n\t\tphandle = <0x08>;\n\t};\n\n\tgt_crx_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x00>;\n\t\tclock-frequency = <0x66ff300>;\n\t\tphandle = <0x0a>;\n\t};\n\n\taux_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x00>;\n\t\tclock-frequency = <0x19bfcc0>;\n\t\tphandle = <0x09>;\n\t};\n\n\tdp_aclk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x00>;\n\t\tclock-frequency = <0x5f5e100>;\n\t\tclock-accuracy = <0x64>;\n\t\tphandle = <0x26>;\n\t};\n\n\taliases {\n\t\tethernet0 = \"/axi/ethernet@ff0e0000\";\n\t\tgpio0 = \"/axi/gpio@ff0a0000\";\n\t\ti2c0 = \"/axi/i2c@ff020000\";\n\t\ti2c1 = \"/axi/i2c@ff030000\";\n\t\tmmc0 = \"/axi/mmc@ff170000\";\n\t\trtc0 = \"/axi/rtc@ffa60000\";\n\t\tserial0 = \"/axi/serial@ff000000\";\n\t\tserial1 = \"/axi/serial@ff010000\";\n\t\tserial2 = \"/dcc\";\n\t\tspi0 = \"/axi/spi@ff0f0000\";\n\t\tusb0 = \"/axi/usb0@ff9d0000\";\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t\txlnx,eeprom = \"/axi/i2c@ff030000/i2c-mux@74/i2c@0/eeprom@54\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x00 0x00 0x00 0x80000000 0x08 0x00 0x00 0x80000000>;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <0x14 0x16 0x00>;\n\t\t\tlinux,code = <0x6c>;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <0x14 0x17 0x00>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <0x2a 0x00 0x2a 0x01 0x2a 0x02 0x2a 0x03>;\n\t};\n\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <0x2b 0x00 0x2b 0x01 0x2b 0x02 0x2b 0x03>;\n\t};\n\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <0x2c 0x00 0x2c 0x01 0x2c 0x02 0x2c 0x03>;\n\t};\n\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <0x2d 0x00 0x2d 0x01 0x2d 0x02 0x2d 0x03>;\n\t};\n\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <0x2e 0x00 0x2e 0x01 0x2e 0x02 0x2e 0x03>;\n\t};\n\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <0x2f 0x00 0x2f 0x01 0x2f 0x02 0x2f 0x03>;\n\t};\n\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <0x30 0x00 0x30 0x01 0x30 0x02 0x30 0x03>;\n\t};\n\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <0x31 0x00 0x31 0x01 0x31 0x02 0x31 0x03>;\n\t};\n\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <0x32 0x00 0x32 0x01 0x32 0x02 0x32 0x03>;\n\t};\n\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <0x33 0x00 0x33 0x01 0x33 0x02 0x33 0x03>;\n\t};\n\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <0x34 0x00 0x34 0x01 0x34 0x02 0x34 0x03>;\n\t};\n\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <0x35 0x00 0x35 0x01 0x35 0x02 0x35 0x03>;\n\t};\n\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <0x36 0x00 0x36 0x01 0x36 0x02 0x36 0x03>;\n\t};\n\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <0x37 0x00 0x37 0x01 0x37 0x02 0x37 0x03>;\n\t};\n\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <0x38 0x00 0x38 0x01 0x38 0x02 0x38 0x03>;\n\t};\n\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <0x39 0x00 0x39 0x01 0x39 0x02 0x39 0x03>;\n\t};\n\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <0x3a 0x00 0x3a 0x01 0x3a 0x02 0x3a 0x03>;\n\t};\n\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <0x3b 0x00 0x3b 0x01 0x3b 0x02 0x3b 0x03>;\n\t};\n\n\tref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x00>;\n\t\tclock-frequency = <0x2dc6c00>;\n\t\tphandle = <0x17>;\n\t};\n\n\trefhdmi {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x00>;\n\t\tclock-frequency = <0x6cfd9c8>;\n\t\tphandle = <0x18>;\n\t};\n\n\tfpga-axi@0 {\n\t\tinterrupt-parent = <0x04>;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x01>;\n\t\t#size-cells = <0x01>;\n\t\tranges = <0x00 0x00 0x00 0xffffffff>;\n\t\tphandle = <0xac>;\n\n\t\t// dma@9c400000 {\n\t\t// \tcompatible = \"adi,axi-dmac-1.00.a\";\n\t\t// \treg = <0x9c400000 0x10000>;\n\t\t// \t#dma-cells = <0x01>;\n\t\t// \t#clock-cells = <0x00>;\n\t\t// \tinterrupts = <0x00 0x6d 0x04>;\n\t\t// \tclocks = <0x03 0x47>;\n\t\t// \tphandle = <0x3c>;\n\n\t\t// \tadi,channels {\n\t\t// \t\t#size-cells = <0x00>;\n\t\t// \t\t#address-cells = <0x01>;\n\n\t\t// \t\tdma-channel@0 {\n\t\t// \t\t\treg = <0x00>;\n\t\t// \t\t\tadi,source-bus-width = <0x40>;\n\t\t// \t\t\tadi,source-bus-type = <0x02>;\n\t\t// \t\t\tadi,destination-bus-width = <0x40>;\n\t\t// \t\t\tadi,destination-bus-type = <0x00>;\n\t\t// \t\t};\n\t\t// \t};\n\t\t// };\n\n\t\t// dma@9c420000 {\n\t\t// \tcompatible = \"adi,axi-dmac-1.00.a\";\n\t\t// \treg = <0x9c420000 0x10000>;\n\t\t// \t#dma-cells = <0x01>;\n\t\t// \t#clock-cells = <0x00>;\n\t\t// \tinterrupts = <0x00 0x6c 0x04>;\n\t\t// \tclocks = <0x03 0x47>;\n\t\t// \tphandle = <0x3e>;\n\n\t\t// \tadi,channels {\n\t\t// \t\t#size-cells = <0x00>;\n\t\t// \t\t#address-cells = <0x01>;\n\n\t\t// \t\tdma-channel@0 {\n\t\t// \t\t\treg = <0x00>;\n\t\t// \t\t\tadi,source-bus-width = <0x40>;\n\t\t// \t\t\tadi,source-bus-type = <0x00>;\n\t\t// \t\t\tadi,destination-bus-width = <0x40>;\n\t\t// \t\t\tadi,destination-bus-type = <0x02>;\n\t\t// \t\t};\n\t\t// \t};\n\t\t// };\n\n\t\tsdr: sdr {\n\t\t\tcompatible =\"sdr,sdr\";\n\t\t\tdmas = <&rx_dma 1\n\t\t\t\t\t&tx_dma 0>;\n\t\t\tdma-names = \"rx_dma_s2mm\", \"tx_dma_mm2s\";\n\t\t\tinterrupt-names = \"not_valid_anymore\", \"rx_pkt_intr\", \"tx_itrpt_useless\", \"tx_itrpt\";\n\t\t\tinterrupts = <0 89 1 0 90 1 0 93 1 0 94 1>;\n\t\t} ;\n\n\t\taxidmatest_1: axidmatest@1 {\n\t\t\tcompatible =\"xlnx,axi-dma-test-1.00.a\";\n\t\t\tdmas = <&rx_dma 0\n\t\t\t\t    &rx_dma 1>;\n\t\t\tdma-names = \"axidma0\", \"axidma1\";\n\t\t} ;\n\n\t\topenwifi_ip_axi_bram_ctrl_0: axi_bram_ctrl@b0000000 {\n\t\t\tclock-names = \"s_axi_aclk\";\n\t\t\tclocks = <0x3 0x49>;\n\t\t\tcompatible = \"xlnx,axi-bram-ctrl-4.1\";\n\t\t\treg = <0x0 0xb0000000 0x0 0x80000>;\n\t\t\txlnx,bram-addr-width = <0x10>;\n\t\t\txlnx,bram-inst-mode = \"EXTERNAL\";\n\t\t\txlnx,ecc = <0x0>;\n\t\t\txlnx,ecc-onoff-reset-value = <0x0>;\n\t\t\txlnx,ecc-type = <0x0>;\n\t\t\txlnx,fault-inject = <0x0>;\n\t\t\txlnx,memory-depth = <0x10000>;\n\t\t\txlnx,rd-cmd-optimization = <0x1>;\n\t\t\txlnx,read-latency = <0x1>;\n\t\t\txlnx,s-axi-ctrl-addr-width = <0x20>;\n\t\t\txlnx,s-axi-ctrl-data-width = <0x20>;\n\t\t\txlnx,s-axi-id-width = <0x10>;\n\t\t\txlnx,s-axi-supports-narrow-burst = <0x1>;\n\t\t\txlnx,single-port-bram = <0x1>;\n\t\t};\n\n\t\ttx_dma: dma@a0000000 {\n\t\t\t#dma-cells = <1>;\n\t\t\tclock-names = \"s_axi_lite_aclk\", \"m_axi_sg_aclk\", \"m_axi_mm2s_aclk\", \"m_axi_s2mm_aclk\";\n\t\t\tclocks = <0x3 0x49>, <0x3 0x49>, <0x3 0x49>, <0x3 0x49>;\n\t\t\tcompatible = \"xlnx,axi-dma-1.00.a\";\n\t\t\tinterrupt-names = \"mm2s_introut\", \"s2mm_introut\";\n\t\t\tinterrupts = <0 95 4 0 96 4>;\n\t\t\treg = <0xa0000000 0x10000>;\n\t\t\txlnx,addrwidth = <0x28>;\n\t\t\txlnx,include-sg ;\n\t\t\txlnx,sg-length-width = <0xe>;\n\t\t\tdma-channel@a0000000 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-mm2s-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 95 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x0>;\n\t\t\t};\n\t\t\tdma-channel@a0000030 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-s2mm-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 96 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x0>;\n\t\t\t};\n\t\t};\n\t\t\n\t\trx_dma: dma@a0010000 {\n\t\t\t#dma-cells = <1>;\n\t\t\tclock-names = \"s_axi_lite_aclk\", \"m_axi_sg_aclk\", \"m_axi_mm2s_aclk\", \"m_axi_s2mm_aclk\";\n\t\t\tclocks = <0x3 0x49>, <0x3 0x49>, <0x3 0x49>, <0x3 0x49>;\n\t\t\tcompatible = \"xlnx,axi-dma-1.00.a\";\n\t\t\t//dma-coherent ;\n\t\t\tinterrupt-names = \"mm2s_introut\", \"s2mm_introut\";\n\t\t\tinterrupts = <0 91 4 0 92 4>;\n\t\t\treg = <0xa0010000 0x10000>;\n\t\t\txlnx,addrwidth = <0x28>;\n\t\t\txlnx,include-sg ;\n\t\t\txlnx,sg-length-width = <0xe>;\n\t\t\tdma-channel@a0010000 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-mm2s-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 91 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x1>;\n\t\t\t};\n\t\t\tdma-channel@a0010030 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-s2mm-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 92 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x1>;\n\t\t\t};\n\t\t};\n\n\t\ttx_intf_0: tx_intf@a0060000 {\n\t\t\tclock-names = \"s00_axi_aclk\", \"s00_axis_aclk\";//, \"s01_axis_aclk\", \"m00_axis_aclk\";\n\t\t\tclocks = <0x3 0x49>, <0x3 0x49>;//, <0x3 0x49>, <0x3 0x49>;\n\t\t\tcompatible = \"sdr,tx_intf\";\n\t\t\tinterrupt-names = \"tx_itrpt\";\n\t\t\tinterrupts = <0 94 1>;\n\t\t\treg = <0xa0060000 0x10000>;\n\t\t\txlnx,s00-axi-addr-width = <0x7>;\n\t\t\txlnx,s00-axi-data-width = <0x20>;\n\t\t};\n\n\t\trx_intf_0: rx_intf@a0040000 {\n\t\t\tclock-names = \"s00_axi_aclk\", \"m00_axis_aclk\";//, \"s00_axis_aclk\";\n\t\t\tclocks = <0x3 0x49>, <0x3 0x49>;//, <0x3 0x49>;\n\t\t\tcompatible = \"sdr,rx_intf\";\n\t\t\tinterrupt-names = \"not_valid_anymore\", \"rx_pkt_intr\";\n\t\t\tinterrupts = <0 89 1 0 90 1>;\n\t\t\treg = <0xa0040000 0x10000>;\n\t\t\txlnx,s00-axi-addr-width = <0x7>;\n\t\t\txlnx,s00-axi-data-width = <0x20>;\n\t\t};\n\n\t\topenofdm_tx_0: openofdm_tx@a0030000 {\n\t\t\tclock-names = \"clk\";\n\t\t\tclocks = <0x3 0x49>;\n\t\t\tcompatible = \"sdr,openofdm_tx\";\n\t\t\treg = <0xa0030000 0x10000>;\n\t\t};\n\n\t\topenofdm_rx_0: openofdm_rx@a0020000 {\n\t\t\tclock-names = \"clk\";\n\t\t\tclocks = <0x3 0x49>;\n\t\t\tcompatible = \"sdr,openofdm_rx\";\n\t\t\treg = <0xa0020000 0x10000>;\n\t\t};\n\n\t\txpu_0: xpu@a0070000 {\n\t\t\tclock-names = \"s00_axi_aclk\";\n\t\t\tclocks = <0x3 0x49>;\n\t\t\tcompatible = \"sdr,xpu\";\n\t\t\treg = <0xa0070000 0x10000>;\n\t\t};\n\n\t\tside_ch_0: side_ch@a0050000 {\n\t\t\tclock-names = \"s00_axi_aclk\";\n\t\t\tclocks = <0x3 0x49>;\n\t\t\tcompatible = \"sdr,side_ch\";\n\t\t\treg = <0xa0050000 0x10000>;\n\t\t\tdmas = <&rx_dma 0\n\t\t\t\t\t&tx_dma 1>;\n\t\t\tdma-names = \"rx_dma_mm2s\", \"tx_dma_s2mm\";\n\t\t};\n\n\t\tcf-ad9361-lpc@99020000 {\n\t\t\tcompatible = \"adi,axi-ad9361-6.00.a\";\n\t\t\treg = <0x99020000 0x6000>;\n\t\t\t// dmas = <0x3c 0x00>;\n\t\t\t// dma-names = \"rx\";\n\t\t\tspibus-connected = <0x3d>;\n\t\t\tphandle = <0xad>;\n\t\t};\n\n\t\tcf-ad9361-dds-core-lpc@99024000 {\n\t\t\tcompatible = \"adi,axi-ad9361-dds-6.00.a\";\n\t\t\treg = <0x99024000 0x1000>;\n\t\t\tclocks = <0x3d 0x0d>;\n\t\t\tclock-names = \"sampl_clk\";\n\t\t\t// dmas = <0x3e 0x00>;\n\t\t\t// dma-names = \"tx\";\n\t\t\tphandle = <0xae>;\n\t\t};\n\n\t\t// axi-sysid-0@85000000 {\n\t\t// \tcompatible = \"adi,axi-sysid-1.00.a\";\n\t\t// \treg = <0x85000000 0x10000>;\n\t\t// \tphandle = <0xaf>;\n\t\t// };\n\t};\n\n\tclocks {\n\n\t\tclock@0 {\n\t\t\tcompatible = \"fixed-clock\";\n\t\t\tclock-frequency = <0x2625a00>;\n\t\t\tclock-output-names = \"ad9361_ext_refclk\";\n\t\t\t#clock-cells = <0x00>;\n\t\t\tphandle = <0x20>;\n\t\t};\n\t};\n\n\t__symbols__ {\n\t\tcpu0 = \"/cpus/cpu@0\";\n\t\tcpu1 = \"/cpus/cpu@1\";\n\t\tcpu2 = \"/cpus/cpu@2\";\n\t\tcpu3 = \"/cpus/cpu@3\";\n\t\tCPU_SLEEP_0 = \"/cpus/idle-states/cpu-sleep-0\";\n\t\tcpu_opp_table = \"/cpu-opp-table\";\n\t\tzynqmp_ipi = \"/zynqmp_ipi\";\n\t\tipi_mailbox_pmu1 = \"/zynqmp_ipi/mailbox@ff990400\";\n\t\tdcc = \"/dcc\";\n\t\tzynqmp_firmware = \"/firmware/zynqmp-firmware\";\n\t\tzynqmp_power = \"/firmware/zynqmp-firmware/zynqmp-power\";\n\t\tsoc_revision = \"/firmware/zynqmp-firmware/nvmem_firmware/soc_revision@0\";\n\t\tefuse_dna = \"/firmware/zynqmp-firmware/nvmem_firmware/efuse_dna@c\";\n\t\tefuse_usr0 = \"/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr0@20\";\n\t\tefuse_usr1 = \"/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr1@24\";\n\t\tefuse_usr2 = \"/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr2@28\";\n\t\tefuse_usr3 = \"/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr3@2c\";\n\t\tefuse_usr4 = \"/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr4@30\";\n\t\tefuse_usr5 = \"/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr5@34\";\n\t\tefuse_usr6 = \"/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr6@38\";\n\t\tefuse_usr7 = \"/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr7@3c\";\n\t\tefuse_miscusr = \"/firmware/zynqmp-firmware/nvmem_firmware/efuse_miscusr@40\";\n\t\tefuse_chash = \"/firmware/zynqmp-firmware/nvmem_firmware/efuse_chash@50\";\n\t\tefuse_pufmisc = \"/firmware/zynqmp-firmware/nvmem_firmware/efuse_pufmisc@54\";\n\t\tefuse_sec = \"/firmware/zynqmp-firmware/nvmem_firmware/efuse_sec@58\";\n\t\tefuse_spkid = \"/firmware/zynqmp-firmware/nvmem_firmware/efuse_spkid@5c\";\n\t\tefuse_ppk0hash = \"/firmware/zynqmp-firmware/nvmem_firmware/efuse_ppk0hash@a0\";\n\t\tefuse_ppk1hash = \"/firmware/zynqmp-firmware/nvmem_firmware/efuse_ppk1hash@d0\";\n\t\tzynqmp_pcap = \"/firmware/zynqmp-firmware/pcap\";\n\t\txlnx_aes = \"/firmware/zynqmp-firmware/zynqmp-aes\";\n\t\tzynqmp_reset = \"/firmware/zynqmp-firmware/reset-controller\";\n\t\tpinctrl0 = \"/firmware/zynqmp-firmware/pinctrl\";\n\t\tpinctrl_i2c0_default = \"/firmware/zynqmp-firmware/pinctrl/i2c0-default\";\n\t\tpinctrl_i2c0_gpio = \"/firmware/zynqmp-firmware/pinctrl/i2c0-gpio\";\n\t\tpinctrl_i2c1_default = \"/firmware/zynqmp-firmware/pinctrl/i2c1-default\";\n\t\tpinctrl_i2c1_gpio = \"/firmware/zynqmp-firmware/pinctrl/i2c1-gpio\";\n\t\tpinctrl_uart0_default = \"/firmware/zynqmp-firmware/pinctrl/uart0-default\";\n\t\tpinctrl_uart1_default = \"/firmware/zynqmp-firmware/pinctrl/uart1-default\";\n\t\tpinctrl_usb0_default = \"/firmware/zynqmp-firmware/pinctrl/usb0-default\";\n\t\tpinctrl_gem3_default = \"/firmware/zynqmp-firmware/pinctrl/gem3-default\";\n\t\tpinctrl_can1_default = \"/firmware/zynqmp-firmware/pinctrl/can1-default\";\n\t\tpinctrl_sdhci1_default = \"/firmware/zynqmp-firmware/pinctrl/sdhci1-default\";\n\t\tpinctrl_gpio_default = \"/firmware/zynqmp-firmware/pinctrl/gpio-default\";\n\t\txlnx_keccak_384 = \"/firmware/zynqmp-firmware/sha384\";\n\t\txlnx_rsa = \"/firmware/zynqmp-firmware/zynqmp-rsa\";\n\t\tmodepin_gpio = \"/firmware/zynqmp-firmware/gpio\";\n\t\tzynqmp_clk = \"/firmware/zynqmp-firmware/clock-controller\";\n\t\tfpga_full = \"/fpga-full\";\n\t\tsmmu = \"/smmu@fd800000\";\n\t\tamba = \"/axi\";\n\t\tcan0 = \"/axi/can@ff060000\";\n\t\tcan1 = \"/axi/can@ff070000\";\n\t\tcci = \"/axi/cci@fd6e0000\";\n\t\tfpd_dma_chan1 = \"/axi/dma@fd500000\";\n\t\tfpd_dma_chan2 = \"/axi/dma@fd510000\";\n\t\tfpd_dma_chan3 = \"/axi/dma@fd520000\";\n\t\tfpd_dma_chan4 = \"/axi/dma@fd530000\";\n\t\tfpd_dma_chan5 = \"/axi/dma@fd540000\";\n\t\tfpd_dma_chan6 = \"/axi/dma@fd550000\";\n\t\tfpd_dma_chan7 = \"/axi/dma@fd560000\";\n\t\tfpd_dma_chan8 = \"/axi/dma@fd570000\";\n\t\tgic = \"/axi/interrupt-controller@f9010000\";\n\t\tgpu = \"/axi/gpu@fd4b0000\";\n\t\tlpd_dma_chan1 = \"/axi/dma@ffa80000\";\n\t\tlpd_dma_chan2 = \"/axi/dma@ffa90000\";\n\t\tlpd_dma_chan3 = \"/axi/dma@ffaa0000\";\n\t\tlpd_dma_chan4 = \"/axi/dma@ffab0000\";\n\t\tlpd_dma_chan5 = \"/axi/dma@ffac0000\";\n\t\tlpd_dma_chan6 = \"/axi/dma@ffad0000\";\n\t\tlpd_dma_chan7 = \"/axi/dma@ffae0000\";\n\t\tlpd_dma_chan8 = \"/axi/dma@ffaf0000\";\n\t\tmc = \"/axi/memory-controller@fd070000\";\n\t\tnand0 = \"/axi/nand-controller@ff100000\";\n\t\tgem0 = \"/axi/ethernet@ff0b0000\";\n\t\tgem1 = \"/axi/ethernet@ff0c0000\";\n\t\tgem2 = \"/axi/ethernet@ff0d0000\";\n\t\tgem3 = \"/axi/ethernet@ff0e0000\";\n\t\tphyc = \"/axi/ethernet@ff0e0000/ethernet-phy@c\";\n\t\tgpio = \"/axi/gpio@ff0a0000\";\n\t\ti2c0 = \"/axi/i2c@ff020000\";\n\t\ttca6416_u97 = \"/axi/i2c@ff020000/gpio@20\";\n\t\ttca6416_u61 = \"/axi/i2c@ff020000/gpio@21\";\n\t\tu76 = \"/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@40\";\n\t\tu77 = \"/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@41\";\n\t\tu78 = \"/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@42\";\n\t\tu87 = \"/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@43\";\n\t\tu85 = \"/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@44\";\n\t\tu86 = \"/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@45\";\n\t\tu93 = \"/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@46\";\n\t\tu88 = \"/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@47\";\n\t\tu15 = \"/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@4a\";\n\t\tu92 = \"/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@4b\";\n\t\tu79 = \"/axi/i2c@ff020000/i2c-mux@75/i2c@1/ina226@40\";\n\t\tu81 = \"/axi/i2c@ff020000/i2c-mux@75/i2c@1/ina226@41\";\n\t\tu80 = \"/axi/i2c@ff020000/i2c-mux@75/i2c@1/ina226@42\";\n\t\tu84 = \"/axi/i2c@ff020000/i2c-mux@75/i2c@1/ina226@43\";\n\t\tu16 = \"/axi/i2c@ff020000/i2c-mux@75/i2c@1/ina226@44\";\n\t\tu65 = \"/axi/i2c@ff020000/i2c-mux@75/i2c@1/ina226@45\";\n\t\tu74 = \"/axi/i2c@ff020000/i2c-mux@75/i2c@1/ina226@46\";\n\t\tu75 = \"/axi/i2c@ff020000/i2c-mux@75/i2c@1/ina226@47\";\n\t\ti2c1 = \"/axi/i2c@ff030000\";\n\t\teeprom = \"/axi/i2c@ff030000/i2c-mux@74/i2c@0/eeprom@54\";\n\t\tboard_sn = \"/axi/i2c@ff030000/i2c-mux@74/i2c@0/eeprom@54/board-sn@0\";\n\t\teth_mac = \"/axi/i2c@ff030000/i2c-mux@74/i2c@0/eeprom@54/eth-mac@20\";\n\t\tboard_name = \"/axi/i2c@ff030000/i2c-mux@74/i2c@0/eeprom@54/board-name@d0\";\n\t\tboard_revision = \"/axi/i2c@ff030000/i2c-mux@74/i2c@0/eeprom@54/board-revision@e0\";\n\t\tsi5341 = \"/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36\";\n\t\tsi5341_0 = \"/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@0\";\n\t\tsi5341_2 = \"/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@2\";\n\t\tsi5341_3 = \"/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@3\";\n\t\tsi5341_4 = \"/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@4\";\n\t\tsi5341_5 = \"/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@5\";\n\t\tsi5341_6 = \"/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@6\";\n\t\tsi5341_7 = \"/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@7\";\n\t\tsi5341_9 = \"/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@9\";\n\t\tsi570_1 = \"/axi/i2c@ff030000/i2c-mux@74/i2c@2/clock-generator@5d\";\n\t\tsi570_2 = \"/axi/i2c@ff030000/i2c-mux@74/i2c@3/clock-generator@5d\";\n\t\tsi5328 = \"/axi/i2c@ff030000/i2c-mux@74/i2c@4/clock-generator@69\";\n\t\tsi5328_clk = \"/axi/i2c@ff030000/i2c-mux@74/i2c@4/clock-generator@69/clk0@0\";\n\t\tocm = \"/axi/memory-controller@ff960000\";\n\t\tperf_monitor_ocm = \"/axi/perf-monitor@ffa00000\";\n\t\tperf_monitor_ddr = \"/axi/perf-monitor@fd0b0000\";\n\t\tperf_monitor_cci = \"/axi/perf-monitor@fd490000\";\n\t\tperf_monitor_lpd = \"/axi/perf-monitor@ffa10000\";\n\t\tpcie = \"/axi/pcie@fd0e0000\";\n\t\tpcie_intc = \"/axi/pcie@fd0e0000/legacy-interrupt-controller\";\n\t\tqspi = \"/axi/spi@ff0f0000\";\n\t\tpsgtr = \"/axi/phy@fd400000\";\n\t\trtc = \"/axi/rtc@ffa60000\";\n\t\tsata = \"/axi/ahci@fd0c0000\";\n\t\tsdhci0 = \"/axi/mmc@ff160000\";\n\t\tsdhci1 = \"/axi/mmc@ff170000\";\n\t\tspi0 = \"/axi/spi@ff040000\";\n\t\tadc0_ad9361 = \"/axi/spi@ff040000/ad9361-phy@0\";\n\t\tspi1 = \"/axi/spi@ff050000\";\n\t\tttc0 = \"/axi/timer@ff110000\";\n\t\tttc1 = \"/axi/timer@ff120000\";\n\t\tttc2 = \"/axi/timer@ff130000\";\n\t\tttc3 = \"/axi/timer@ff140000\";\n\t\tuart0 = \"/axi/serial@ff000000\";\n\t\tuart1 = \"/axi/serial@ff010000\";\n\t\tusb0 = \"/axi/usb0@ff9d0000\";\n\t\tdwc3_0 = \"/axi/usb0@ff9d0000/dwc3@fe200000\";\n\t\tusb1 = \"/axi/usb1@ff9e0000\";\n\t\tdwc3_1 = \"/axi/usb1@ff9e0000/dwc3@fe300000\";\n\t\twatchdog0 = \"/axi/watchdog@fd4d0000\";\n\t\tlpd_watchdog = \"/axi/watchdog@ff150000\";\n\t\txilinx_ams = \"/axi/ams@ffa50000\";\n\t\tams_ps = \"/axi/ams@ffa50000/ams_ps@ffa50800\";\n\t\tams_pl = \"/axi/ams@ffa50000/ams_pl@ffa50c00\";\n\t\tzynqmp_dpdma = \"/axi/dma-controller@fd4c0000\";\n\t\tzynqmp_dpsub = \"/axi/display@fd4a0000\";\n\t\tzynqmp_dp_snd_codec0 = \"/axi/display@fd4a0000/zynqmp_dp_snd_codec0\";\n\t\tzynqmp_dp_snd_pcm0 = \"/axi/display@fd4a0000/zynqmp_dp_snd_pcm0\";\n\t\tzynqmp_dp_snd_pcm1 = \"/axi/display@fd4a0000/zynqmp_dp_snd_pcm1\";\n\t\tzynqmp_dp_snd_card0 = \"/axi/display@fd4a0000/zynqmp_dp_snd_card\";\n\t\tfclk0 = \"/fclk0\";\n\t\tfclk1 = \"/fclk1\";\n\t\tfclk2 = \"/fclk2\";\n\t\tfclk3 = \"/fclk3\";\n\t\tpss_ref_clk = \"/pss_ref_clk\";\n\t\tvideo_clk = \"/video_clk\";\n\t\tpss_alt_ref_clk = \"/pss_alt_ref_clk\";\n\t\tgt_crx_ref_clk = \"/gt_crx_ref_clk\";\n\t\taux_ref_clk = \"/aux_ref_clk\";\n\t\tdp_aclk = \"/dp_aclk\";\n\t\tref48 = \"/ref48M\";\n\t\trefhdmi = \"/refhdmi\";\n\t\tfpga_axi = \"/fpga-axi@0\";\n\t\trx_dma = \"/fpga-axi@0/dma@9c400000\";\n\t\ttx_dma = \"/fpga-axi@0/dma@9c420000\";\n\t\tcf_ad9361_adc_core_0 = \"/fpga-axi@0/cf-ad9361-lpc@99020000\";\n\t\tcf_ad9361_dac_core_0 = \"/fpga-axi@0/cf-ad9361-dds-core-lpc@99024000\";\n\t\taxi_sysid_0 = \"/fpga-axi@0/axi-sysid-0@85000000\";\n\t\tad9361_clkin = \"/clocks/clock@0\";\n\t};\n};\n"
  },
  {
    "path": "kernel_boot/boards/zed_fmcs2/devicetree.dts",
    "content": "/dts-v1/;\n\n/ {\n\t#address-cells = <0x1>;\n\t#size-cells = <0x1>;\n\tcompatible = \"xlnx,zynq-7000\";\n\tinterrupt-parent = <0x1>;\n\tmodel = \"Xilinx Zynq ZED\";\n\n\tcpus {\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0x0>;\n\t\t\tclocks = <0x2 0x3>;\n\t\t\tclock-latency = <0x3e8>;\n\t\t\tcpu0-supply = <0x3>;\n\t\t\toperating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0x1>;\n\t\t\tclocks = <0x2 0x3>;\n\t\t};\n\t};\n\n\tfpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <0x4>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tranges;\n\t};\n\n\tpmu@f8891000 {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0x0 0x5 0x4 0x0 0x6 0x4>;\n\t\tinterrupt-parent = <0x1>;\n\t\treg = <0xf8891000 0x1000 0xf8893000 0x1000>;\n\t};\n\n\tfixedregulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <0xf4240>;\n\t\tregulator-max-microvolt = <0xf4240>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t\tlinux,phandle = <0x3>;\n\t\tphandle = <0x3>;\n\t};\n\n\tamba {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tinterrupt-parent = <0x1>;\n\t\tranges;\n\n\t\tadc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0x0 0x7 0x4>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tclocks = <0x2 0xc>;\n\t\t};\n\n\t\tcan@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x13 0x2 0x24>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0x0 0x1c 0x4>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x14 0x2 0x25>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0x0 0x33 0x4>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tclocks = <0x2 0x2a>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <0x2>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x14 0x4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t\tlinux,phandle = <0x6>;\n\t\t\tphandle = <0x6>;\n\t\t};\n\n\t\ti2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x26>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x19 0x4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t};\n\n\t\ti2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x27>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x30 0x4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t};\n\n\t\tinterrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <0x3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xf8f01000 0x1000 0xf8f00100 0x100>;\n\t\t\tlinux,phandle = <0x1>;\n\t\t\tphandle = <0x1>;\n\t\t};\n\n\t\tcache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xf8f02000 0x1000>;\n\t\t\tinterrupts = <0x0 0x2 0x4>;\n\t\t\tarm,data-latency = <0x3 0x2 0x2>;\n\t\t\tarm,tag-latency = <0x2 0x2 0x2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <0x2>;\n\t\t};\n\n\t\tmemory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x3 0x4>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t};\n\n\t\tserial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x17 0x2 0x28>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xe0000000 0x1000>;\n\t\t\tinterrupts = <0x0 0x1b 0x4>;\n\t\t};\n\n\t\tserial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"okay\";\n\t\t\tclocks = <0x2 0x18 0x2 0x29>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xe0001000 0x1000>;\n\t\t\tinterrupts = <0x0 0x32 0x4>;\n\t\t};\n\n\t\tspi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x1a 0x4>;\n\t\t\tclocks = <0x2 0x19 0x2 0x22>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\n\t\t\tad9361-phy@0 {\n\t\t\t\tcompatible = \"adi,ad9361\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tspi-cpha;\n\t\t\t\tspi-max-frequency = <0x989680>;\n\t\t\t\tclocks = <0x5 0x0>;\n\t\t\t\tclock-names = \"ad9361_ext_refclk\";\n\t\t\t\tclock-output-names = \"rx_sampl_clk\", \"tx_sampl_clk\";\n\t\t\t\t#clock-cells = <0x1>;\n\t\t\t\tadi,digital-interface-tune-skip-mode = <0x0>;\n\t\t\t\tadi,pp-tx-swap-enable;\n\t\t\t\tadi,pp-rx-swap-enable;\n\t\t\t\tadi,rx-frame-pulse-mode-enable;\n\t\t\t\tadi,lvds-mode-enable;\n\t\t\t\tadi,lvds-bias-mV = <0x96>;\n\t\t\t\tadi,lvds-rx-onchip-termination-enable;\n\t\t\t\tadi,rx-data-delay = <0x4>;\n\t\t\t\tadi,tx-fb-clock-delay = <0x7>;\n\t\t\t\tadi,dcxo-coarse-and-fine-tune = <0x8 0x1720>;\n\t\t\t\tadi,2rx-2tx-mode-enable;\n\t\t\t\tadi,frequency-division-duplex-mode-enable;\n\t\t\t\tadi,rx-rf-port-input-select = <0x0>;\n\t\t\t\tadi,tx-rf-port-input-select = <0x0>;\n\t\t\t\tadi,tx-attenuation-mdB = <0x2710>;\n\t\t\t\tadi,tx-lo-powerdown-managed-enable;\n\t\t\t\tadi,rf-rx-bandwidth-hz = <0x112a880>;\n\t\t\t\tadi,rf-tx-bandwidth-hz = <0x112a880>;\n\t\t\t\tadi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;\n\t\t\t\tadi,tx-synthesizer-frequency-hz = <0x0 0x92080880>;\n\t\t\t\tadi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;\n\t\t\t\tadi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;\n\t\t\t\tadi,gc-rx1-mode = <0x2>;\n\t\t\t\tadi,gc-rx2-mode = <0x2>;\n\t\t\t\tadi,gc-adc-ovr-sample-size = <0x4>;\n\t\t\t\tadi,gc-adc-small-overload-thresh = <0x2f>;\n\t\t\t\tadi,gc-adc-large-overload-thresh = <0x3a>;\n\t\t\t\tadi,gc-lmt-overload-high-thresh = <0x320>;\n\t\t\t\tadi,gc-lmt-overload-low-thresh = <0x2c0>;\n\t\t\t\tadi,gc-dec-pow-measurement-duration = <0x2000>;\n\t\t\t\tadi,gc-low-power-thresh = <0x18>;\n\t\t\t\tadi,mgc-inc-gain-step = <0x2>;\n\t\t\t\tadi,mgc-dec-gain-step = <0x2>;\n\t\t\t\tadi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;\n\t\t\t\tadi,agc-attack-delay-extra-margin-us = <0x1>;\n\t\t\t\tadi,agc-outer-thresh-high = <0x5>;\n\t\t\t\tadi,agc-outer-thresh-high-dec-steps = <0x2>;\n\t\t\t\tadi,agc-inner-thresh-high = <0xa>;\n\t\t\t\tadi,agc-inner-thresh-high-dec-steps = <0x1>;\n\t\t\t\tadi,agc-inner-thresh-low = <0xc>;\n\t\t\t\tadi,agc-inner-thresh-low-inc-steps = <0x1>;\n\t\t\t\tadi,agc-outer-thresh-low = <0x12>;\n\t\t\t\tadi,agc-outer-thresh-low-inc-steps = <0x2>;\n\t\t\t\tadi,agc-adc-small-overload-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-adc-large-overload-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-adc-large-overload-inc-steps = <0x7>;\n\t\t\t\tadi,agc-lmt-overload-large-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-lmt-overload-small-exceed-counter = <0xa>;\n\t\t\t\tadi,agc-lmt-overload-large-inc-steps = <0x7>;\n\t\t\t\tadi,agc-gain-update-interval-us = <0x3e8>;\n\t\t\t\tadi,fagc-dec-pow-measurement-duration = <0x10>;\n        adi,fagc-adc-large-overload-inc-steps = <0x07>;\n\t\t\t\tadi,fagc-lp-thresh-increment-steps = <0x1>;\n\t\t\t\tadi,fagc-lp-thresh-increment-time = <0x5>;\n\t\t\t\tadi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;\n        adi,fagc-dig-sat-ovrg-enable;\n\t\t\t\tadi,fagc-final-overrange-count = <0x3>;\n\t\t\t\tadi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;\n\t\t\t\tadi,fagc-lmt-final-settling-steps = <0x1>;\n\t\t\t\tadi,fagc-lock-level = <0xa>;\n\t\t\t\tadi,fagc-lock-level-gain-increase-upper-limit = <0x5>;\n\t\t\t\tadi,fagc-lock-level-lmt-gain-increase-enable;\n\t\t\t\tadi,fagc-lpf-final-settling-steps = <0x1>;\n\t\t\t\tadi,fagc-optimized-gain-offset = <0x5>;\n\t\t\t\tadi,fagc-power-measurement-duration-in-state5 = <0x10>;\n\t\t\t\tadi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;\n\t\t\t\tadi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;\n\t\t\t\tadi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;\n\t\t\t\tadi,fagc-rst-gla-large-adc-overload-enable;\n\t\t\t\tadi,fagc-rst-gla-large-lmt-overload-enable;\n\t\t\t\tadi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;\n\t\t\t\tadi,fagc-state-wait-time-ns = <0x104>;\n\t\t\t\tadi,fagc-use-last-lock-level-for-set-gain-enable;\n\t\t\t\tadi,rssi-restart-mode = <0x3>;\n\t\t\t\tadi,rssi-delay = <0x1>;\n\t\t\t\tadi,rssi-wait = <0x1>;\n\t\t\t\tadi,rssi-duration = <0x3e8>;\n\t\t\t\tadi,ctrl-outs-index = <0x0>;\n\t\t\t\tadi,ctrl-outs-enable-mask = <0xff>;\n\t\t\t\tadi,temp-sense-measurement-interval-ms = <0x3e8>;\n\t\t\t\tadi,temp-sense-offset-signed = <0xce>;\n\t\t\t\tadi,temp-sense-periodic-measurement-enable;\n\t\t\t\tadi,aux-dac-manual-mode-enable;\n\t\t\t\tadi,aux-dac1-default-value-mV = <0x0>;\n\t\t\t\tadi,aux-dac1-rx-delay-us = <0x0>;\n\t\t\t\tadi,aux-dac1-tx-delay-us = <0x0>;\n\t\t\t\tadi,aux-dac2-default-value-mV = <0x0>;\n\t\t\t\tadi,aux-dac2-rx-delay-us = <0x0>;\n\t\t\t\tadi,aux-dac2-tx-delay-us = <0x0>;\n\t\t\t\ten_agc-gpios = <0x6 0x62 0x0>;\n\t\t\t\tsync-gpios = <0x6 0x63 0x0>;\n\t\t\t\treset-gpios = <0x6 0x64 0x0>;\n\t\t\t\tenable-gpios = <0x6 0x65 0x0>;\n\t\t\t\ttxnrx-gpios = <0x6 0x66 0x0>;\n\t\t\t\tlinux,phandle = <0x11>;\n\t\t\t\tphandle = <0x11>;\n\t\t\t};\n\t\t};\n\n\t\tspi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x31 0x4>;\n\t\t\tclocks = <0x2 0x1a 0x2 0x23>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\n\t\t\tadf4351-udc-tx-pmod@0 {\n\t\t\t\tcompatible = \"adi,adf4351\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tspi-max-frequency = <0x989680>;\n\t\t\t\tclocks = <0x7>;\n\t\t\t\tclock-names = \"clkin\";\n\t\t\t\tadi,channel-spacing = <0xf4240>;\n\t\t\t\tadi,power-up-frequency = <0x160dc080>;\n\t\t\t\tadi,phase-detector-polarity-positive-enable;\n\t\t\t\tadi,charge-pump-current = <0x9c4>;\n\t\t\t\tadi,output-power = <0x3>;\n\t\t\t\tadi,mute-till-lock-enable;\n\t\t\t\tadi,muxout-select = <0x6>;\n\t\t\t\tgpios = <0x6 0x68 0x0>;\n\t\t\t};\n\n\t\t\tadf4351-udc-rx-pmod@1 {\n\t\t\t\tcompatible = \"adi,adf4351\";\n\t\t\t\treg = <0x1>;\n\t\t\t\tspi-max-frequency = <0x989680>;\n\t\t\t\tclocks = <0x7>;\n\t\t\t\tclock-names = \"clkin\";\n\t\t\t\tadi,channel-spacing = <0xf4240>;\n\t\t\t\tadi,power-up-frequency = <0x1443fd00>;\n\t\t\t\tadi,phase-detector-polarity-positive-enable;\n\t\t\t\tadi,charge-pump-current = <0x9c4>;\n\t\t\t\tadi,output-power = <0x3>;\n\t\t\t\tadi,mute-till-lock-enable;\n\t\t\t\tadi,muxout-select = <0x6>;\n\t\t\t\tgpios = <0x6 0x67 0x0>;\n\t\t\t};\n\t\t};\n\n\t\tspi@e000d000 {\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tclocks = <0x2 0xa 0x2 0x2b>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x13 0x4>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\tis-dual = <0x0>;\n\t\t\tnum-cs = <0x1>;\n\n\t\t\tps7-qspi@0 {\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t\tcompatible = \"n25q128a11\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tspi-max-frequency = <0x2faf080>;\n\n\t\t\t\tpartition@0 {\n\t\t\t\t\tlabel = \"boot\";\n\t\t\t\t\treg = <0x0 0x500000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@500000 {\n\t\t\t\t\tlabel = \"bootenv\";\n\t\t\t\t\treg = <0x500000 0x20000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@520000 {\n\t\t\t\t\tlabel = \"config\";\n\t\t\t\t\treg = <0x520000 0x20000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@540000 {\n\t\t\t\t\tlabel = \"image\";\n\t\t\t\t\treg = <0x540000 0xa80000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@fc0000 {\n\t\t\t\t\tlabel = \"spare\";\n\t\t\t\t\treg = <0xfc0000 0x0>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tmemory-controller@e000e000 {\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x1>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"aclk\";\n\t\t\tclocks = <0x2 0xb 0x2 0x2c>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x12 0x4>;\n\t\t\tranges;\n\t\t\treg = <0xe000e000 0x1000>;\n\n\t\t\tflash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\n\t\t\tflash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x2000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\t\t};\n\n\t\tethernet@e000b000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupts = <0x0 0x16 0x4>;\n\t\t\tclocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\tphy-handle = <0x8>;\n\t\t\tphy-mode = \"rgmii-id\";\n\n\t\t\tphy@0 {\n\t\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tmarvell,reg-init = <0x3 0x10 0xff00 0x1e 0x3 0x11 0xfff0 0xa>;\n\t\t\t\tlinux,phandle = <0x8>;\n\t\t\t\tphandle = <0x8>;\n\t\t\t};\n\t\t};\n\n\t\tethernet@e000c000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0x0 0x2d 0x4>;\n\t\t\tclocks = <0x2 0x1f 0x2 0x1f 0x2 0xe>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t};\n\n\t\tmmc@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <0x2 0x15 0x2 0x20>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x18 0x4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t};\n\n\t\tmmc@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <0x2 0x16 0x2 0x21>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x2f 0x4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t};\n\n\t\tslcr@f8000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\", \"simple-mfd\";\n\t\t\treg = <0xf8000000 0x1000>;\n\t\t\tranges;\n\t\t\tlinux,phandle = <0x9>;\n\t\t\tphandle = <0x9>;\n\n\t\t\tclkc@100 {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <0x1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\", \"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\", \"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\", \"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\", \"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\", \"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\", \"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\", \"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\", \"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\", \"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t\tps-clk-frequency = <0x1fca055>;\n\t\t\t\tlinux,phandle = <0x2>;\n\t\t\t\tphandle = <0x2>;\n\t\t\t};\n\n\t\t\trstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <0x1>;\n\t\t\t\tsyscon = <0x9>;\n\t\t\t};\n\n\t\t\tpinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <0x9>;\n\t\t\t};\n\t\t};\n\n\t\tdmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\", \"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\tinterrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>;\n\t\t\t#dma-cells = <0x1>;\n\t\t\t#dma-channels = <0x8>;\n\t\t\t#dma-requests = <0x4>;\n\t\t\tclocks = <0x2 0x1b>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t\tlinux,phandle = <0xf>;\n\t\t\tphandle = <0xf>;\n\t\t};\n\n\t\tdevcfg@f8007000 {\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x8 0x4>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tclocks = <0x2 0xc 0x2 0xf 0x2 0x10 0x2 0x11 0x2 0x12>;\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tsyscon = <0x9>;\n\t\t\tlinux,phandle = <0x4>;\n\t\t\tphandle = <0x4>;\n\t\t};\n\n\t\tefuse@f800d000 {\n\t\t\tcompatible = \"xlnx,zynq-efuse\";\n\t\t\treg = <0xf800d000 0x20>;\n\t\t};\n\n\t\ttimer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <0x1 0xb 0x301>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tclocks = <0x2 0x4>;\n\t\t};\n\n\t\ttimer@f8001000 {\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <0x2 0x6>;\n\t\t\treg = <0xf8001000 0x1000>;\n\t\t};\n\n\t\ttimer@f8002000 {\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <0x2 0x6>;\n\t\t\treg = <0xf8002000 0x1000>;\n\t\t};\n\n\t\ttimer@f8f00600 {\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x1 0xd 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <0x2 0x4>;\n\t\t};\n\n\t\tusb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"okay\";\n\t\t\tclocks = <0x2 0x1c>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x15 0x4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t\tdr_mode = \"host\";\n\t\t\txlnx,phy-reset-gpio = <0x6 0x55 0x0>;\n\t\t};\n\n\t\tusb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <0x2 0x1d>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x2c 0x4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog@f8005000 {\n\t\t\tclocks = <0x2 0x2d>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x9 0x1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <0xa>;\n\t\t};\n\t};\n\n\taliases {\n\t\tethernet0 = \"/amba/ethernet@e000b000\";\n\t\tserial0 = \"/amba/serial@e0001000\";\n\t};\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x20000000>;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait\";\n\t\tlinux,stdout-path = \"/amba@0/uart@E0001000\";\n\t};\n\n\tfpga-axi@0 {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tranges;\n/*\n\t\ti2c@41600000 {\n\t\t\tcompatible = \"xlnx,axi-iic-1.01.b\", \"xlnx,xps-iic-2.00.a\";\n\t\t\treg = <0x41600000 0x10000>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x3a 0x4>;\n\t\t\tclocks = <0x2 0xf>;\n\t\t\tclock-names = \"pclk\";\n\t\t\t#size-cells = <0x0>;\n\t\t\t#address-cells = <0x1>;\n\n\t\t\tadv7511@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39 0x3f>;\n\t\t\t\treg-names = \"primary\", \"edid\";\n\t\t\t\tadi,input-depth = <0x8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <0x1>;\n\t\t\t\tadi,input-justification = \"right\";\n\t\t\t\tadi,clock-delay = <0x0>;\n\t\t\t\t#sound-dai-cells = <0x0>;\n\t\t\t\tlinux,phandle = <0x14>;\n\t\t\t\tphandle = <0x14>;\n\n\t\t\t\tports {\n\t\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t\t#size-cells = <0x0>;\n\n\t\t\t\t\tport@0 {\n\t\t\t\t\t\treg = <0x0>;\n\n\t\t\t\t\t\tendpoint {\n\t\t\t\t\t\t\tremote-endpoint = <0xa>;\n\t\t\t\t\t\t\tlinux,phandle = <0xe>;\n\t\t\t\t\t\t\tphandle = <0xe>;\n\t\t\t\t\t\t};\n\t\t\t\t\t};\n\n\t\t\t\t\tport@1 {\n\t\t\t\t\t\treg = <0x1>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tadau1761@3b {\n\t\t\t\tcompatible = \"adi,adau1761\";\n\t\t\t\treg = <0x3b>;\n\t\t\t\tclocks = <0xb>;\n\t\t\t\tclock-names = \"mclk\";\n\t\t\t\t#sound-dai-cells = <0x0>;\n\t\t\t\tlinux,phandle = <0x16>;\n\t\t\t\tphandle = <0x16>;\n\t\t\t};\n\t\t};\n\n\t\tdma@43000000 {\n\t\t\tcompatible = \"adi,axi-dmac-1.00.a\";\n\t\t\treg = <0x43000000 0x10000>;\n\t\t\t#dma-cells = <0x1>;\n\t\t\tinterrupts = <0x0 0x3b 0x0>;\n\t\t\tclocks = <0x2 0x10>;\n\t\t\tlinux,phandle = <0xc>;\n\t\t\tphandle = <0xc>;\n\n\t\t\tadi,channels {\n\t\t\t\t#size-cells = <0x0>;\n\t\t\t\t#address-cells = <0x1>;\n\n\t\t\t\tdma-channel@0 {\n\t\t\t\t\treg = <0x0>;\n\t\t\t\t\tadi,source-bus-width = <0x40>;\n\t\t\t\t\tadi,source-bus-type = <0x0>;\n\t\t\t\t\tadi,destination-bus-width = <0x40>;\n\t\t\t\t\tadi,destination-bus-type = <0x1>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\taxi-clkgen@79000000 {\n\t\t\tcompatible = \"adi,axi-clkgen-2.00.a\";\n\t\t\treg = <0x79000000 0x10000>;\n\t\t\t#clock-cells = <0x0>;\n\t\t\tclocks = <0x2 0x10>;\n\t\t\tlinux,phandle = <0xd>;\n\t\t\tphandle = <0xd>;\n\t\t};\n\n\t\taxi_hdmi@70e00000 {\n\t\t\tcompatible = \"adi,axi-hdmi-tx-1.00.a\";\n\t\t\treg = <0x70e00000 0x10000>;\n\t\t\tdmas = <0xc 0x0>;\n\t\t\tdma-names = \"video\";\n\t\t\tclocks = <0xd>;\n\n\t\t\tport {\n\n\t\t\t\tendpoint {\n\t\t\t\t\tremote-endpoint = <0xe>;\n\t\t\t\t\tlinux,phandle = <0xa>;\n\t\t\t\t\tphandle = <0xa>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\taxi-spdif-tx@75c00000 {\n\t\t\tcompatible = \"adi,axi-spdif-tx-1.00.a\";\n\t\t\treg = <0x75c00000 0x1000>;\n\t\t\tdmas = <0xf 0x0>;\n\t\t\tdma-names = \"tx\";\n\t\t\tclocks = <0x2 0xf 0xb>;\n\t\t\tclock-names = \"axi\", \"ref\";\n\t\t\t#sound-dai-cells = <0x0>;\n\t\t\tlinux,phandle = <0x13>;\n\t\t\tphandle = <0x13>;\n\t\t};\n\n\t\taxi-i2s@77600000 {\n\t\t\tcompatible = \"adi,axi-i2s-1.00.a\";\n\t\t\treg = <0x77600000 0x1000>;\n\t\t\tdmas = <0xf 0x1 0xf 0x2>;\n\t\t\tdma-names = \"tx\", \"rx\";\n\t\t\tclocks = <0x2 0xf 0xb>;\n\t\t\tclock-names = \"axi\", \"ref\";\n\t\t\t#sound-dai-cells = <0x0>;\n\t\t\tlinux,phandle = <0x15>;\n\t\t\tphandle = <0x15>;\n\t\t};\n\n\t\taxi-sysid-0@45000000 {\n\t\t\tcompatible = \"adi,axi-sysid-1.00.a\";\n\t\t\treg = <0x45000000 0x10000>;\n\t\t};*/\n\n\t\ti2c@41620000 {\n\t\t\tcompatible = \"xlnx,axi-iic-1.01.b\", \"xlnx,xps-iic-2.00.a\";\n\t\t\treg = <0x41620000 0x10000>;\n\t\t\tinterrupt-parent = <0x1>;\n\t\t\tinterrupts = <0x0 0x37 0x4>;\n\t\t\tclocks = <0x2 0xf>;\n\t\t\tclock-names = \"pclk\";\n\t\t\t#size-cells = <0x0>;\n\t\t\t#address-cells = <0x1>;\n\n\t\t\tad7291@2f {\n\t\t\t\tcompatible = \"adi,ad7291\";\n\t\t\t\treg = <0x2f>;\n\t\t\t};\n\n\t\t\teeprom@50 {\n\t\t\t\tcompatible = \"at24,24c02\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\n\t\t// dma@7c400000 {\n\t\t// \tcompatible = \"adi,axi-dmac-1.00.a\";\n\t\t// \treg = <0x7c400000 0x10000>;\n\t\t// \t#dma-cells = <0x1>;\n\t\t// \tinterrupts = <0x0 0x39 0x0>;\n\t\t// \tclocks = <0x2 0x10>;\n\t\t// \tlinux,phandle = <0x10>;\n\t\t// \tphandle = <0x10>;\n\n\t\t// \tadi,channels {\n\t\t// \t\t#size-cells = <0x0>;\n\t\t// \t\t#address-cells = <0x1>;\n\n\t\t// \t\tdma-channel@0 {\n\t\t// \t\t\treg = <0x0>;\n\t\t// \t\t\tadi,source-bus-width = <0x40>;\n\t\t// \t\t\tadi,source-bus-type = <0x2>;\n\t\t// \t\t\tadi,destination-bus-width = <0x40>;\n\t\t// \t\t\tadi,destination-bus-type = <0x0>;\n\t\t// \t\t};\n\t\t// \t};\n\t\t// };\n\n\t\t// dma@7c420000 {\n\t\t// \tcompatible = \"adi,axi-dmac-1.00.a\";\n\t\t// \treg = <0x7c420000 0x10000>;\n\t\t// \t#dma-cells = <0x1>;\n\t\t// \tinterrupts = <0x0 0x38 0x0>;\n\t\t// \tclocks = <0x2 0x10>;\n\t\t// \tlinux,phandle = <0x12>;\n\t\t// \tphandle = <0x12>;\n\n\t\t// \tadi,channels {\n\t\t// \t\t#size-cells = <0x0>;\n\t\t// \t\t#address-cells = <0x1>;\n\n\t\t// \t\tdma-channel@0 {\n\t\t// \t\t\treg = <0x0>;\n\t\t// \t\t\tadi,source-bus-width = <0x40>;\n\t\t// \t\t\tadi,source-bus-type = <0x0>;\n\t\t// \t\t\tadi,destination-bus-width = <0x40>;\n\t\t// \t\t\tadi,destination-bus-type = <0x2>;\n\t\t// \t\t};\n\t\t// \t};\n\t\t// };\n\n\t\tsdr: sdr {\n\t\t\tcompatible =\"sdr,sdr\";\n\t\t\tdmas = <&rx_dma 1\n\t\t\t\t\t&tx_dma 0>;\n\t\t\tdma-names = \"rx_dma_s2mm\", \"tx_dma_mm2s\";\n\t\t\tinterrupt-names = \"not_valid_anymore\", \"rx_pkt_intr\", \"tx_itrpt\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 29 1 0 30 1 0 33 1 0 34 1>;\n\t\t} ;\n\n\t\taxidmatest_1: axidmatest@1 {\n\t\t\tcompatible =\"xlnx,axi-dma-test-1.00.a\";\n\t\t\tdmas = <&rx_dma 0\n\t\t\t\t&rx_dma 1>;\n\t\t\tdma-names = \"axidma0\", \"axidma1\";\n\t\t} ;\n\n\t\ttx_dma: dma@80400000 {\n\t\t\t#dma-cells = <1>;\n\t\t\tclock-names = \"s_axi_lite_aclk\", \"m_axi_sg_aclk\", \"m_axi_mm2s_aclk\", \"m_axi_s2mm_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"xlnx,axi-dma-1.00.a\";\n\t\t\tinterrupt-names = \"mm2s_introut\", \"s2mm_introut\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 35 4 0 36 4>;\n\t\t\treg = <0x80400000 0x10000>;\n\t\t\txlnx,addrwidth = <0x20>;\n\t\t\txlnx,include-sg ;\n\t\t\txlnx,sg-length-width = <0xe>;\n\t\t\tdma-channel@80400000 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-mm2s-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 35 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x0>;\n\t\t\t};\n\t\t\tdma-channel@80400030 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-s2mm-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 36 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x0>;\n\t\t\t};\n\t\t};\n\t\t\n\t\trx_dma: dma@80410000 {\n\t\t\t#dma-cells = <1>;\n\t\t\tclock-names = \"s_axi_lite_aclk\", \"m_axi_sg_aclk\", \"m_axi_mm2s_aclk\", \"m_axi_s2mm_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"xlnx,axi-dma-1.00.a\";\n\t\t\t//dma-coherent ;\n\t\t\tinterrupt-names = \"mm2s_introut\", \"s2mm_introut\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 31 4 0 32 4>;\n\t\t\treg = <0x80410000 0x10000>;\n\t\t\txlnx,addrwidth = <0x20>;\n\t\t\txlnx,include-sg ;\n\t\t\txlnx,sg-length-width = <0xe>;\n\t\t\tdma-channel@80410000 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-mm2s-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 31 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x1>;\n\t\t\t};\n\t\t\tdma-channel@80410030 {\n\t\t\t\tcompatible = \"xlnx,axi-dma-s2mm-channel\";\n\t\t\t\tdma-channels = <0x1>;\n\t\t\t\tinterrupts = <0 32 4>;\n\t\t\t\txlnx,datawidth = <0x40>;\n\t\t\t\txlnx,device-id = <0x1>;\n\t\t\t};\n\t\t};\n\n\t\ttx_intf_0: tx_intf@83c00000 {\n\t\t\tclock-names = \"s00_axi_aclk\", \"s00_axis_aclk\";//, \"s01_axis_aclk\", \"m00_axis_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>, <0x2 0x11>;\n\t\t\tcompatible = \"sdr,tx_intf\";\n\t\t\tinterrupt-names = \"tx_itrpt\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 34 1>;\n\t\t\treg = <0x83c00000 0x10000>;\n\t\t\txlnx,s00-axi-addr-width = <0x7>;\n\t\t\txlnx,s00-axi-data-width = <0x20>;\n\t\t};\n\n\t\trx_intf_0: rx_intf@83c20000 {\n\t\t\tclock-names = \"s00_axi_aclk\", \"m00_axis_aclk\";//, \"s00_axis_aclk\";\n\t\t\tclocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>;\n\t\t\tcompatible = \"sdr,rx_intf\";\n\t\t\tinterrupt-names = \"not_valid_anymore\", \"rx_pkt_intr\";\n\t\t\tinterrupt-parent = <1>;\n\t\t\tinterrupts = <0 29 1 0 30 1>;\n\t\t\treg = <0x83c20000 0x10000>;\n\t\t\txlnx,s00-axi-addr-width = <0x7>;\n\t\t\txlnx,s00-axi-data-width = <0x20>;\n\t\t};\n\n\t\topenofdm_tx_0: openofdm_tx@83c10000 {\n\t\t\tclock-names = \"clk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,openofdm_tx\";\n\t\t\treg = <0x83c10000 0x10000>;\n\t\t};\n\n\t\topenofdm_rx_0: openofdm_rx@83c30000 {\n\t\t\tclock-names = \"clk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,openofdm_rx\";\n\t\t\treg = <0x83c30000 0x10000>;\n\t\t};\n\n\t\txpu_0: xpu@83c40000 {\n\t\t\tclock-names = \"s00_axi_aclk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,xpu\";\n\t\t\treg = <0x83c40000 0x10000>;\n\t\t};\n\n\t\tside_ch_0: side_ch@83c50000 {\n\t\t\tclock-names = \"s00_axi_aclk\";\n\t\t\tclocks = <0x2 0x11>;\n\t\t\tcompatible = \"sdr,side_ch\";\n\t\t\treg = <0x83c50000 0x10000>;\n\t\t\tdmas = <&rx_dma 0\n\t\t\t\t\t&tx_dma 1>;\n\t\t\tdma-names = \"rx_dma_mm2s\", \"tx_dma_s2mm\";\n\t\t};\n\n\t\tcf-ad9361-lpc@79020000 {\n\t\t\tcompatible = \"adi,axi-ad9361-6.00.a\";\n\t\t\treg = <0x79020000 0x6000>;\n\t\t\t// dmas = <0x10 0x0>;\n\t\t\t// dma-names = \"rx\";\n\t\t\tspibus-connected = <0x11>;\n\t\t};\n\n\t\tcf-ad9361-dds-core-lpc@79024000 {\n\t\t\tcompatible = \"adi,axi-ad9361-dds-6.00.a\";\n\t\t\treg = <0x79024000 0x1000>;\n\t\t\tclocks = <0x11 0xd>;\n\t\t\tclock-names = \"sampl_clk\";\n\t\t\t// dmas = <0x12 0x0>;\n\t\t\t// dma-names = \"tx\";\n\t\t};\n\t};\n\n/*\n\taudio_clock {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <0xbb8000>;\n\t\tlinux,phandle = <0xb>;\n\t\tphandle = <0xb>;\n\t};\n\n\tadv7511_hdmi_snd {\n\t\tcompatible = \"simple-audio-card\";\n\t\tsimple-audio-card,name = \"HDMI monitor\";\n\t\tsimple-audio-card,widgets = \"Speaker\", \"Speaker\";\n\t\tsimple-audio-card,routing = \"Speaker\", \"TX\";\n\n\t\tsimple-audio-card,dai-link@0 {\n\t\t\tformat = \"spdif\";\n\n\t\t\tcpu {\n\t\t\t\tsound-dai = <0x13>;\n\t\t\t\tframe-master;\n\t\t\t\tbitclock-master;\n\t\t\t};\n\n\t\t\tcodec {\n\t\t\t\tsound-dai = <0x14>;\n\t\t\t};\n\t\t};\n\t};\n\n\tzed_sound {\n\t\tcompatible = \"simple-audio-card\";\n\t\tsimple-audio-card,name = \"ZED ADAU1761\";\n\t\tsimple-audio-card,widgets = \"Microphone\", \"Mic In\", \"Headphone\", \"Headphone Out\", \"Line\", \"Line In\", \"Line\", \"Line Out\";\n\t\tsimple-audio-card,routing = \"Line Out\", \"LOUT\", \"Line Out\", \"ROUT\", \"Headphone Out\", \"LHP\", \"Headphone Out\", \"RHP\", \"Mic In\", \"MICBIAS\", \"LINN\", \"Mic In\", \"RINN\", \"Mic In\", \"LAUX\", \"Line In\", \"RAUX\", \"Line In\";\n\n\t\tsimple-audio-card,dai-link@0 {\n\t\t\tformat = \"i2s\";\n\n\t\t\tcpu {\n\t\t\t\tsound-dai = <0x15>;\n\t\t\t\tframe-master;\n\t\t\t\tbitclock-master;\n\t\t\t};\n\n\t\t\tcodec {\n\t\t\t\tsound-dai = <0x16>;\n\t\t\t};\n\t\t};\n\t};\n*/\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tld0 {\n\t\t\tlabel = \"ld0:red\";\n\t\t\tgpios = <0x6 0x49 0x0>;\n\t\t};\n\n\t\tld1 {\n\t\t\tlabel = \"ld1:red\";\n\t\t\tgpios = <0x6 0x4a 0x0>;\n\t\t};\n\n\t\tld2 {\n\t\t\tlabel = \"ld2:red\";\n\t\t\tgpios = <0x6 0x4b 0x0>;\n\t\t};\n\n\t\tld3 {\n\t\t\tlabel = \"ld3:red\";\n\t\t\tgpios = <0x6 0x4c 0x0>;\n\t\t};\n\n\t\tld4 {\n\t\t\tlabel = \"ld4:red\";\n\t\t\tgpios = <0x6 0x4d 0x0>;\n\t\t};\n\n\t\tld5 {\n\t\t\tlabel = \"ld5:red\";\n\t\t\tgpios = <0x6 0x4e 0x0>;\n\t\t};\n\n\t\tld6 {\n\t\t\tlabel = \"ld6:red\";\n\t\t\tgpios = <0x6 0x4f 0x0>;\n\t\t};\n\n\t\tld7 {\n\t\t\tlabel = \"ld7:red\";\n\t\t\tgpios = <0x6 0x50 0x0>;\n\t\t};\n\t};\n\n\tclocks {\n\n\t\tclock@0 {\n\t\t\tcompatible = \"fixed-clock\";\n\t\t\tclock-frequency = <0x2625a00>;\n\t\t\tclock-output-names = \"ad9361_ext_refclk\";\n\t\t\t#clock-cells = <0x0>;\n\t\t\tlinux,phandle = <0x5>;\n\t\t\tphandle = <0x5>;\n\t\t};\n\n\t\tclock@1 {\n\t\t\tcompatible = \"fixed-clock\";\n\t\t\tclock-frequency = <0x17d7840>;\n\t\t\tclock-output-names = \"refclk\";\n\t\t\t#clock-cells = <0x0>;\n\t\t\tlinux,phandle = <0x7>;\n\t\t\tphandle = <0x7>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "kernel_boot/build_boot_bin.sh",
    "content": "#!/bin/bash\nset -ex\n\nHDF_FILE=$1\nUBOOT_FILE=$2\nBUILD_DIR=build_boot_bin\nOUTPUT_DIR=output_boot_bin\n\nusage () {\n\techo \"usage: $0 system_top.<hdf/xsa> u-boot.elf [output-archive]\"\n\texit 1\n}\n\ndepends () {\n\techo Xilinx $1 must be installed and in your PATH\n\techo try: source /opt/Xilinx/Vivado/201x.x/settings64.sh\n\texit 1\n}\n\n### Check command line parameters\necho $HDF_FILE | grep -q \".hdf\\|.xsa\" || usage\necho $UBOOT_FILE | grep -q -e \".elf\" -e \"uboot\" -e \"u-boot\"|| usage\n\nif [ ! -f $HDF_FILE ]; then\n\techo $HDF_FILE: File not found!\n\tusage\nfi\n\nif [ ! -f $UBOOT_FILE ]; then\n\techo $UBOOT_FILE: File not found!\n\tusage\nfi\n\n### Check for required Xilinx tools (xcst is equivalent with 'xsdk -batch')\ncommand -v xsct >/dev/null 2>&1 || depends xsct\ncommand -v bootgen >/dev/null 2>&1 || depends bootgen\n\nrm -Rf $BUILD_DIR $OUTPUT_DIR\nmkdir -p $OUTPUT_DIR\nmkdir -p $BUILD_DIR\n\ncp $HDF_FILE $BUILD_DIR/\ncp $UBOOT_FILE $OUTPUT_DIR/u-boot.elf\ncp $HDF_FILE $OUTPUT_DIR/\n\n### Create create_fsbl_project.tcl file used by xsct to create the fsbl.\necho \"hsi open_hw_design `basename $HDF_FILE`\" > $BUILD_DIR/create_fsbl_project.tcl\necho 'set cpu_name [lindex [hsi get_cells -filter {IP_TYPE==PROCESSOR}] 0]' >> $BUILD_DIR/create_fsbl_project.tcl\n### The fsbl creating flow is different starting with 2019.2 Xilinx version\nif [[ \"$HDF_FILE\" =~ \".hdf\" ]];then\n\techo 'sdk setws ./build/sdk' >> $BUILD_DIR/create_fsbl_project.tcl\n\techo \"sdk createhw -name hw_0 -hwspec `basename $HDF_FILE`\" >> $BUILD_DIR/create_fsbl_project.tcl\n\techo 'sdk createapp -name fsbl -hwproject hw_0 -proc $cpu_name -os standalone -lang C -app {Zynq FSBL}' >> $BUILD_DIR/create_fsbl_project.tcl\n\techo 'configapp -app fsbl build-config release' >> $BUILD_DIR/create_fsbl_project.tcl\n\techo 'sdk projects -build -type all' >> $BUILD_DIR/create_fsbl_project.tcl\n\n\tFSBL_PATH=\"$BUILD_DIR/build/sdk/fsbl/Release/fsbl.elf\"\n\tSYSTEM_TOP_BIT_PATH=\"$BUILD_DIR/build/sdk/hw_0/system_top.bit\"\nelse\n\techo 'platform create -name hw0 -hw system_top.xsa -os standalone -out ./build/sdk -proc $cpu_name' >> $BUILD_DIR/create_fsbl_project.tcl\n\techo 'platform generate' >> $BUILD_DIR/create_fsbl_project.tcl\n\n\tFSBL_PATH=\"$BUILD_DIR/build/sdk/hw0/export/hw0/sw/hw0/boot/fsbl.elf\"\n\tSYSTEM_TOP_BIT_PATH=\"$BUILD_DIR/build/sdk/hw0/hw/system_top.bit\"\nfi\n\n### Create zynq.bif file used by bootgen\necho 'the_ROM_image:' > $OUTPUT_DIR/zynq.bif\necho '{' >> $OUTPUT_DIR/zynq.bif\necho '[bootloader] fsbl.elf' >> $OUTPUT_DIR/zynq.bif\necho 'system_top.bit' >> $OUTPUT_DIR/zynq.bif\necho 'u-boot.elf' >> $OUTPUT_DIR/zynq.bif\necho '}' >> $OUTPUT_DIR/zynq.bif\n\n### Build fsbl.elf\n(\n\tcd $BUILD_DIR\n\txsct create_fsbl_project.tcl\n)\n\n### Copy fsbl and system_top.bit into the output folder\ncp $FSBL_PATH $OUTPUT_DIR/fsbl.elf\ncp $SYSTEM_TOP_BIT_PATH $OUTPUT_DIR/system_top.bit\n\n### Build BOOT.BIN\n(\n\tcd $OUTPUT_DIR\n\tbootgen -arch zynq -image zynq.bif -o BOOT.BIN -w\n)\n\n### Optionally tar.gz the entire output folder with the name given in argument 3\nif [ ${#3} -ne 0 ]; then\n\ttar czvf $3.tar.gz $OUTPUT_DIR\nfi\n"
  },
  {
    "path": "kernel_boot/build_zynqmp_boot_bin.sh",
    "content": "#!/bin/bash\nset -ex\n\nXSA_FILE=$1\nUBOOT_FILE=$2\nATF_FILE=${3:-download}\nBUILD_DIR=build_boot_bin\nOUTPUT_DIR=output_boot_bin\n\nusage () {\n\techo \"usage: $0 filename.xsa u-boot.elf  (download | bl31.elf | <path-to-arm-trusted-firmware-source>) [output-archive]\"\n\texit 1\n}\n\ndepends () {\n\techo \"Xilinx $1 must be installed and in your PATH\"\n\techo \"try: source /opt/Xilinx/Vivado/202x.x/settings64.sh\"\n\texit 1\n}\n\n### Check command line parameters\necho $XSA_FILE | grep -q \".xsa\" || usage\necho $UBOOT_FILE | grep -q -e \".elf\" -e \"uboot\" -e \"u-boot\" || usage\n\nif [ ! -f $XSA_FILE ]; then\n\techo $XSA_FILE: File not found!\n\tusage\nfi\n\nif [ ! -f $UBOOT_FILE ]; then\n    echo $UBOOT_FILE: File not found!\n    usage\nfi\n\n### Check for required Xilinx tools (starting with 2019.2 there is no hsi anymore)\ncommand -v xsct >/dev/null 2>&1 || depends xsct\ncommand -v bootgen >/dev/null 2>&1 || depends bootgen\n\nrm -Rf $BUILD_DIR $OUTPUT_DIR\nmkdir -p $OUTPUT_DIR\nmkdir -p $BUILD_DIR\n\n# 2020.1 use bf72e4d494f3be10665b94c0e88766eb2096ef71\n# 2021.2 use 799131a3b063f6f24f87baa74e46906c076aebcd\n# 2022.2 use 5ebf70ea38e4626637568352b644acbffe3b13c1\n# 2023.1 use c7385e021c0b95a025f2c78384d57224e0120401\n# 2023.2 use 04013814718e870261f27256216cd7da3eda6a5d\n\ntool_version=$(vitis -v | grep -o \"Vitis v20[1-9][0-9]\\.[0-9] (64-bit)\" | grep -o \"v20[1-9][0-9]\\.[0-9]\")\nif [[ \"$tool_version\" != \"v20\"[1-9][0-9]\".\"[0-9] ]] ; then\n\techo \"Could not determine Vitis version\"\n\texit 1\nfi\natf_version=xilinx-$tool_version\n\nif [[ \"$atf_version\" == \"xilinx-v2021.1\" ]];then atf_version=\"xlnx_rebase_v2.4_2021.1\";fi\nif [[ \"$atf_version\" == \"xilinx-v2021.1.1\" ]];then atf_version=\"xlnx_rebase_v2.4_2021.1_update1\";fi\nif [[ \"$atf_version\" == \"xilinx-v2021.2\" ]];then atf_version=\"xilinx-v2021.2\";fi\nif [[ \"$atf_version\" == \"xilinx-v2022.2\" ]];then atf_version=\"xilinx-v2022.2\";fi\nif [[ \"$atf_version\" == \"xilinx-v2023.1\" ]];then atf_version=\"xilinx-v2023.1\";fi\nif [[ \"$atf_version\" == \"xilinx-v2023.2\" ]];then atf_version=\"xilinx-v2023.2\";fi\n\nif [[ \"$4\" == \"uart1\" ]];then console=\"cadence1\";else console=\"cadence0\";fi\n\n### Check if ATF_FILE is .elf or path to arm-trusted-firmware\nif [ \"$ATF_FILE\" != \"\" ] && [ -d $ATF_FILE ]; then\n### Build arm-trusted-firmware bl31.elf\n(\n\tcd $ATF_FILE\n\tmake distclean\n\tgit checkout $atf_version\n\tmake CROSS_COMPILE=aarch64-linux-gnu- PLAT=zynqmp RESET_TO_BL31=1 ZYNQMP_CONSOLE=$console\n)\n\tcp $ATF_FILE/build/zynqmp/release/bl31/bl31.elf $OUTPUT_DIR/bl31.elf\nelif [ \"$ATF_FILE\" == \"download\" ]; then\n(\n\tcommand -v git >/dev/null 2>&1 || depends git\n\tcd $BUILD_DIR\n\tgit clone https://github.com/Xilinx/arm-trusted-firmware.git\n\tcd arm-trusted-firmware\n\tgit checkout $atf_version\n\tmake CROSS_COMPILE=aarch64-linux-gnu- PLAT=zynqmp RESET_TO_BL31=1 ZYNQMP_CONSOLE=$console\n)\n\tcp $BUILD_DIR/arm-trusted-firmware/build/zynqmp/release/bl31/bl31.elf $OUTPUT_DIR/bl31.elf\nelse\n\techo $ATF_FILE | grep -q -e \"bl31.elf\" || usage\n\tif [ ! -f $ATF_FILE ]; then\n\t\techo $ATF_FILE: File not found!\n\t\tusage\n\tfi\n\tcp $ATF_FILE $OUTPUT_DIR/bl31.elf\nfi\n\ncp \"$XSA_FILE\" \"$BUILD_DIR/\"\ncp \"$UBOOT_FILE\" \"$OUTPUT_DIR/u-boot.elf\"\ncp \"$XSA_FILE\" \"$OUTPUT_DIR/\"\n\n### Get basename of xsa and bit file\nXSA_FILE_BASENAME=\"$(basename $XSA_FILE)\"\nXSA_FILE_BASENAME_WO_EXT=\"$(basename $XSA_FILE .xsa)\"\nBIT_FILE_BASENAME=\"$XSA_FILE_BASENAME_WO_EXT.bit\"\n\n### Create create_fsbl_project.tcl file used by xsct to create the fsbl.\necho \"hsi open_hw_design $XSA_FILE_BASENAME\" > $BUILD_DIR/create_fsbl_project.tcl\necho 'set cpu_name [lindex [hsi get_cells -filter {IP_TYPE==PROCESSOR}] 0]' >> $BUILD_DIR/create_fsbl_project.tcl\necho \"platform create -name hw0 -hw $XSA_FILE_BASENAME -os standalone -out ./build/sdk -proc \\$cpu_name\" >> $BUILD_DIR/create_fsbl_project.tcl\necho 'platform generate' >> $BUILD_DIR/create_fsbl_project.tcl\n\nFSBL_PATH=\"$BUILD_DIR/build/sdk/hw0/export/hw0/sw/hw0/boot/fsbl.elf\"\nSYSTEM_TOP_BIT_PATH=\"$BUILD_DIR/build/sdk/hw0/hw/$BIT_FILE_BASENAME\"\nPMUFW_PATH=\"$BUILD_DIR/build/sdk/hw0/export/hw0/sw/hw0/boot/pmufw.elf\"\n\n### Create zynq.bif file used by bootgen\necho \"the_ROM_image:\" > $OUTPUT_DIR/zynq.bif\necho \"{\" >> $OUTPUT_DIR/zynq.bif\necho \"[bootloader,destination_cpu=a53-0] fsbl.elf\" >> $OUTPUT_DIR/zynq.bif\necho \"[pmufw_image] pmufw.elf\" >> $OUTPUT_DIR/zynq.bif\necho \"[destination_device=pl] $BIT_FILE_BASENAME\" >> $OUTPUT_DIR/zynq.bif\necho \"[destination_cpu=a53-0,exception_level=el-3,trustzone] bl31.elf\" >> $OUTPUT_DIR/zynq.bif\necho \"[destination_cpu=a53-0, exception_level=el-2] u-boot.elf\" >> $OUTPUT_DIR/zynq.bif\necho \"}\" >> $OUTPUT_DIR/zynq.bif\n\n### Build fsbl.elf & pmufw.elf\n(\n\tcd $BUILD_DIR\n\txsct create_fsbl_project.tcl\n)\n### Copy fsbl and $BIT_FILE_BASENAME into the output folder\ncp \"$FSBL_PATH\" \"$OUTPUT_DIR/fsbl.elf\"\ncp \"$SYSTEM_TOP_BIT_PATH\" \"$OUTPUT_DIR/$BIT_FILE_BASENAME\"\ncp \"$PMUFW_PATH\" \"$OUTPUT_DIR/pmufw.elf\"\n\n### Build BOOT.BIN\n(\n\tcd $OUTPUT_DIR\n\tbootgen -arch zynqmp -image zynq.bif -o BOOT.BIN -w\n)\n\n### Optionally tar.gz the entire output folder with the name given in argument 4/5\nif [[ ( $4 == \"uart\"* && ${#5} -ne 0 ) ]]; then\n\ttar czvf $5.tar.gz $OUTPUT_DIR\nfi\n\nif [[ ( ${#4} -ne 0 && $4 != \"uart\"* && ${#5} -eq 0 ) ]]; then\n        tar czvf $4.tar.gz $OUTPUT_DIR\nfi\n"
  },
  {
    "path": "kernel_boot/kernel_config",
    "content": "#\n# Automatically generated file; DO NOT EDIT.\n# Linux/arm 5.15.36 Kernel Configuration\n#\nCONFIG_KERNEL_ALL_ADI_DRIVERS=y\nCONFIG_CLK_ALL_ADI_DRIVERS=y\nCONFIG_HWMON_ALL_ADI_DRIVERS=y\nCONFIG_IIO_ALL_ADI_DRIVERS=y\nCONFIG_INPUT_ALL_ADI_DRIVERS=y\nCONFIG_MEDIA_ALL_ADI_DRIVERS=y\nCONFIG_USB_ALL_ADI_DRIVERS=y\nCONFIG_SND_SOC_ALL_ADI_CODECS=y\nCONFIG_CC_VERSION_TEXT=\"arm-xilinx-linux-gnueabi-gcc.real (GCC) 10.2.0\"\nCONFIG_CC_IS_GCC=y\nCONFIG_GCC_VERSION=100200\nCONFIG_CLANG_VERSION=0\nCONFIG_AS_IS_GNU=y\nCONFIG_AS_VERSION=23500\nCONFIG_LD_IS_BFD=y\nCONFIG_LD_VERSION=23500\nCONFIG_LLD_VERSION=0\nCONFIG_CC_CAN_LINK=y\nCONFIG_CC_CAN_LINK_STATIC=y\nCONFIG_CC_HAS_ASM_GOTO=y\nCONFIG_CC_HAS_ASM_INLINE=y\nCONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y\nCONFIG_IRQ_WORK=y\nCONFIG_BUILDTIME_TABLE_SORT=y\n\n#\n# General setup\n#\nCONFIG_INIT_ENV_ARG_LIMIT=32\n# CONFIG_COMPILE_TEST is not set\n# CONFIG_WERROR is not set\nCONFIG_LOCALVERSION=\"\"\nCONFIG_LOCALVERSION_AUTO=y\nCONFIG_BUILD_SALT=\"\"\nCONFIG_HAVE_KERNEL_GZIP=y\nCONFIG_HAVE_KERNEL_LZMA=y\nCONFIG_HAVE_KERNEL_XZ=y\nCONFIG_HAVE_KERNEL_LZO=y\nCONFIG_HAVE_KERNEL_LZ4=y\nCONFIG_KERNEL_GZIP=y\n# CONFIG_KERNEL_LZMA is not set\n# CONFIG_KERNEL_XZ is not set\n# CONFIG_KERNEL_LZO is not set\n# CONFIG_KERNEL_LZ4 is not set\nCONFIG_DEFAULT_INIT=\"\"\nCONFIG_DEFAULT_HOSTNAME=\"(none)\"\nCONFIG_SWAP=y\nCONFIG_SYSVIPC=y\nCONFIG_SYSVIPC_SYSCTL=y\n# CONFIG_POSIX_MQUEUE is not set\n# CONFIG_WATCH_QUEUE is not set\nCONFIG_CROSS_MEMORY_ATTACH=y\nCONFIG_USELIB=y\n# CONFIG_AUDIT is not set\nCONFIG_HAVE_ARCH_AUDITSYSCALL=y\n\n#\n# IRQ subsystem\n#\nCONFIG_GENERIC_IRQ_PROBE=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_MIGRATION=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_GENERIC_IRQ_IPI=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_SPARSE_IRQ=y\n# CONFIG_GENERIC_IRQ_DEBUGFS is not set\n# end of IRQ subsystem\n\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_ARCH_HAS_TICK_BROADCAST=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\n\n#\n# Timers subsystem\n#\nCONFIG_TICK_ONESHOT=y\nCONFIG_HZ_PERIODIC=y\n# CONFIG_NO_HZ_IDLE is not set\n# CONFIG_NO_HZ_FULL is not set\n# CONFIG_NO_HZ is not set\nCONFIG_HIGH_RES_TIMERS=y\n# end of Timers subsystem\n\nCONFIG_BPF=y\nCONFIG_HAVE_EBPF_JIT=y\n\n#\n# BPF subsystem\n#\n# CONFIG_BPF_SYSCALL is not set\n# CONFIG_BPF_JIT is not set\nCONFIG_USERMODE_DRIVER=y\n# end of BPF subsystem\n\n# CONFIG_PREEMPT_NONE is not set\n# CONFIG_PREEMPT_VOLUNTARY is not set\nCONFIG_PREEMPT=y\nCONFIG_PREEMPT_COUNT=y\nCONFIG_PREEMPTION=y\n# CONFIG_SCHED_CORE is not set\n\n#\n# CPU/Task time and stats accounting\n#\nCONFIG_TICK_CPU_ACCOUNTING=y\n# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set\n# CONFIG_IRQ_TIME_ACCOUNTING is not set\n# CONFIG_BSD_PROCESS_ACCT is not set\n# CONFIG_TASKSTATS is not set\n# CONFIG_PSI is not set\n# end of CPU/Task time and stats accounting\n\nCONFIG_CPU_ISOLATION=y\n\n#\n# RCU Subsystem\n#\nCONFIG_TREE_RCU=y\nCONFIG_PREEMPT_RCU=y\n# CONFIG_RCU_EXPERT is not set\nCONFIG_SRCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_TASKS_RCU_GENERIC=y\nCONFIG_TASKS_RCU=y\nCONFIG_RCU_STALL_COMMON=y\nCONFIG_RCU_NEED_SEGCBLIST=y\n# end of RCU Subsystem\n\nCONFIG_IKCONFIG=y\nCONFIG_IKCONFIG_PROC=y\n# CONFIG_IKHEADERS is not set\nCONFIG_LOG_BUF_SHIFT=15\nCONFIG_LOG_CPU_MAX_BUF_SHIFT=12\nCONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13\n# CONFIG_PRINTK_INDEX is not set\nCONFIG_GENERIC_SCHED_CLOCK=y\n\n#\n# Scheduler features\n#\n# end of Scheduler features\n\nCONFIG_CGROUPS=y\n# CONFIG_MEMCG is not set\n# CONFIG_BLK_CGROUP is not set\n# CONFIG_CGROUP_SCHED is not set\n# CONFIG_CGROUP_PIDS is not set\n# CONFIG_CGROUP_RDMA is not set\n# CONFIG_CGROUP_FREEZER is not set\n# CONFIG_CPUSETS is not set\n# CONFIG_CGROUP_DEVICE is not set\n# CONFIG_CGROUP_CPUACCT is not set\n# CONFIG_CGROUP_PERF is not set\n# CONFIG_CGROUP_MISC is not set\n# CONFIG_CGROUP_DEBUG is not set\nCONFIG_NAMESPACES=y\nCONFIG_UTS_NS=y\nCONFIG_IPC_NS=y\nCONFIG_USER_NS=y\nCONFIG_PID_NS=y\nCONFIG_NET_NS=y\n# CONFIG_CHECKPOINT_RESTORE is not set\n# CONFIG_SCHED_AUTOGROUP is not set\n# CONFIG_SYSFS_DEPRECATED is not set\n# CONFIG_RELAY is not set\nCONFIG_BLK_DEV_INITRD=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_RD_GZIP=y\n# CONFIG_RD_BZIP2 is not set\n# CONFIG_RD_LZMA is not set\n# CONFIG_RD_XZ is not set\n# CONFIG_RD_LZO is not set\n# CONFIG_RD_LZ4 is not set\nCONFIG_RD_ZSTD=y\n# CONFIG_BOOT_CONFIG is not set\nCONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y\n# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set\nCONFIG_LD_ORPHAN_WARN=y\nCONFIG_SYSCTL=y\nCONFIG_HAVE_UID16=y\nCONFIG_EXPERT=y\nCONFIG_UID16=y\nCONFIG_MULTIUSER=y\n# CONFIG_SGETMASK_SYSCALL is not set\nCONFIG_SYSFS_SYSCALL=y\nCONFIG_FHANDLE=y\nCONFIG_POSIX_TIMERS=y\nCONFIG_PRINTK=y\nCONFIG_BUG=y\nCONFIG_ELF_CORE=y\nCONFIG_BASE_FULL=y\nCONFIG_FUTEX=y\nCONFIG_FUTEX_PI=y\nCONFIG_HAVE_FUTEX_CMPXCHG=y\nCONFIG_EPOLL=y\nCONFIG_SIGNALFD=y\nCONFIG_TIMERFD=y\nCONFIG_EVENTFD=y\nCONFIG_SHMEM=y\nCONFIG_AIO=y\nCONFIG_IO_URING=y\nCONFIG_ADVISE_SYSCALLS=y\nCONFIG_MEMBARRIER=y\nCONFIG_KALLSYMS=y\n# CONFIG_KALLSYMS_ALL is not set\nCONFIG_KALLSYMS_BASE_RELATIVE=y\n# CONFIG_USERFAULTFD is not set\nCONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y\nCONFIG_KCMP=y\nCONFIG_RSEQ=y\n# CONFIG_DEBUG_RSEQ is not set\nCONFIG_EMBEDDED=y\nCONFIG_HAVE_PERF_EVENTS=y\nCONFIG_PERF_USE_VMALLOC=y\n# CONFIG_PC104 is not set\n\n#\n# Kernel Performance Events And Counters\n#\nCONFIG_PERF_EVENTS=y\n# CONFIG_DEBUG_PERF_USE_VMALLOC is not set\n# end of Kernel Performance Events And Counters\n\nCONFIG_VM_EVENT_COUNTERS=y\nCONFIG_COMPAT_BRK=y\nCONFIG_SLAB=y\n# CONFIG_SLUB is not set\n# CONFIG_SLOB is not set\nCONFIG_SLAB_MERGE_DEFAULT=y\n# CONFIG_SLAB_FREELIST_RANDOM is not set\n# CONFIG_SLAB_FREELIST_HARDENED is not set\n# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set\nCONFIG_SYSTEM_DATA_VERIFICATION=y\n# CONFIG_PROFILING is not set\n# end of General setup\n\nCONFIG_ARM=y\nCONFIG_ARM_HAS_SG_CHAIN=y\nCONFIG_SYS_SUPPORTS_APM_EMULATION=y\nCONFIG_HAVE_PROC_CPU=y\nCONFIG_STACKTRACE_SUPPORT=y\nCONFIG_LOCKDEP_SUPPORT=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_GENERIC_HWEIGHT=y\nCONFIG_GENERIC_CALIBRATE_DELAY=y\nCONFIG_ARCH_SUPPORTS_UPROBES=y\nCONFIG_ARM_PATCH_PHYS_VIRT=y\nCONFIG_GENERIC_BUG=y\nCONFIG_PGTABLE_LEVELS=2\n\n#\n# System Type\n#\nCONFIG_MMU=y\nCONFIG_ARCH_MMAP_RND_BITS_MIN=8\nCONFIG_ARCH_MMAP_RND_BITS_MAX=16\nCONFIG_ARCH_MULTIPLATFORM=y\n# CONFIG_ARCH_EP93XX is not set\n# CONFIG_ARCH_FOOTBRIDGE is not set\n# CONFIG_ARCH_IOP32X is not set\n# CONFIG_ARCH_IXP4XX is not set\n# CONFIG_ARCH_DOVE is not set\n# CONFIG_ARCH_PXA is not set\n# CONFIG_ARCH_RPC is not set\n# CONFIG_ARCH_SA1100 is not set\n# CONFIG_ARCH_S3C24XX is not set\n# CONFIG_ARCH_OMAP1 is not set\n\n#\n# Multiple platform selection\n#\n\n#\n# CPU Core family selection\n#\n# CONFIG_ARCH_MULTI_V6 is not set\nCONFIG_ARCH_MULTI_V7=y\nCONFIG_ARCH_MULTI_V6_V7=y\n# end of Multiple platform selection\n\n# CONFIG_ARCH_VIRT is not set\n# CONFIG_ARCH_ACTIONS is not set\n# CONFIG_ARCH_ALPINE is not set\n# CONFIG_ARCH_ARTPEC is not set\n# CONFIG_ARCH_ASPEED is not set\n# CONFIG_ARCH_AT91 is not set\n# CONFIG_ARCH_BCM is not set\n# CONFIG_ARCH_BERLIN is not set\n# CONFIG_ARCH_DIGICOLOR is not set\n# CONFIG_ARCH_EXYNOS is not set\n# CONFIG_ARCH_HIGHBANK is not set\n# CONFIG_ARCH_HISI is not set\n# CONFIG_ARCH_MXC is not set\n# CONFIG_ARCH_KEYSTONE is not set\n# CONFIG_ARCH_MEDIATEK is not set\n# CONFIG_ARCH_MESON is not set\n# CONFIG_ARCH_MILBEAUT is not set\n# CONFIG_ARCH_MMP is not set\n# CONFIG_ARCH_MSTARV7 is not set\n# CONFIG_ARCH_MVEBU is not set\n# CONFIG_ARCH_NPCM is not set\n\n#\n# TI OMAP/AM/DM/DRA Family\n#\n# CONFIG_ARCH_OMAP3 is not set\n# CONFIG_ARCH_OMAP4 is not set\n# CONFIG_SOC_OMAP5 is not set\n# CONFIG_SOC_AM33XX is not set\n# CONFIG_SOC_AM43XX is not set\n# CONFIG_SOC_DRA7XX is not set\n# end of TI OMAP/AM/DM/DRA Family\n\n# CONFIG_ARCH_QCOM is not set\n# CONFIG_ARCH_RDA is not set\n# CONFIG_ARCH_REALTEK is not set\n# CONFIG_ARCH_REALVIEW is not set\n# CONFIG_ARCH_ROCKCHIP is not set\n# CONFIG_ARCH_S5PV210 is not set\n# CONFIG_ARCH_RENESAS is not set\n# CONFIG_ARCH_INTEL_SOCFPGA is not set\n# CONFIG_PLAT_SPEAR is not set\n# CONFIG_ARCH_STI is not set\n# CONFIG_ARCH_STM32 is not set\n# CONFIG_ARCH_SUNXI is not set\n# CONFIG_ARCH_TEGRA is not set\n# CONFIG_ARCH_UNIPHIER is not set\n# CONFIG_ARCH_U8500 is not set\n# CONFIG_ARCH_VEXPRESS is not set\n# CONFIG_ARCH_WM8850 is not set\nCONFIG_ARCH_ZYNQ=y\n\n#\n# Xilinx Specific Options\n#\nCONFIG_XILINX_PREFETCH=y\n# CONFIG_XILINX_RESET_CODE is not set\n# end of Xilinx Specific Options\n\n#\n# Processor Type\n#\nCONFIG_CPU_V7=y\nCONFIG_CPU_THUMB_CAPABLE=y\nCONFIG_CPU_32v6K=y\nCONFIG_CPU_32v7=y\nCONFIG_CPU_ABRT_EV7=y\nCONFIG_CPU_PABRT_V7=y\nCONFIG_CPU_CACHE_V7=y\nCONFIG_CPU_CACHE_VIPT=y\nCONFIG_CPU_COPY_V6=y\nCONFIG_CPU_TLB_V7=y\nCONFIG_CPU_HAS_ASID=y\nCONFIG_CPU_CP15=y\nCONFIG_CPU_CP15_MMU=y\n\n#\n# Processor Features\n#\n# CONFIG_ARM_LPAE is not set\nCONFIG_ARM_THUMB=y\n# CONFIG_ARM_THUMBEE is not set\nCONFIG_ARM_VIRT_EXT=y\nCONFIG_SWP_EMULATE=y\n# CONFIG_CPU_BIG_ENDIAN is not set\n# CONFIG_CPU_ICACHE_DISABLE is not set\n# CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND is not set\n# CONFIG_CPU_BPREDICT_DISABLE is not set\nCONFIG_CPU_SPECTRE=y\nCONFIG_HARDEN_BRANCH_PREDICTOR=y\n# CONFIG_HARDEN_BRANCH_HISTORY is not set\nCONFIG_KUSER_HELPERS=y\n# CONFIG_VDSO is not set\nCONFIG_OUTER_CACHE=y\nCONFIG_OUTER_CACHE_SYNC=y\nCONFIG_MIGHT_HAVE_CACHE_L2X0=y\nCONFIG_CACHE_L2X0=y\n# CONFIG_CACHE_L2X0_PMU is not set\nCONFIG_PL310_ERRATA_588369=y\nCONFIG_PL310_ERRATA_727915=y\n# CONFIG_PL310_ERRATA_753970 is not set\nCONFIG_PL310_ERRATA_769419=y\nCONFIG_ARM_L1_CACHE_SHIFT_6=y\nCONFIG_ARM_L1_CACHE_SHIFT=6\nCONFIG_ARM_DMA_MEM_BUFFERABLE=y\nCONFIG_ARM_HEAVY_MB=y\nCONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y\nCONFIG_DEBUG_ALIGN_RODATA=y\n# CONFIG_ARM_ERRATA_430973 is not set\n# CONFIG_ARM_ERRATA_643719 is not set\n# CONFIG_ARM_ERRATA_720789 is not set\nCONFIG_ARM_ERRATA_754322=y\nCONFIG_ARM_ERRATA_754327=y\nCONFIG_ARM_ERRATA_764369=y\nCONFIG_ARM_ERRATA_775420=y\n# CONFIG_ARM_ERRATA_798181 is not set\n# CONFIG_ARM_ERRATA_773022 is not set\n# CONFIG_ARM_ERRATA_818325_852422 is not set\n# CONFIG_ARM_ERRATA_821420 is not set\n# CONFIG_ARM_ERRATA_825619 is not set\n# CONFIG_ARM_ERRATA_857271 is not set\n# CONFIG_ARM_ERRATA_852421 is not set\n# CONFIG_ARM_ERRATA_852423 is not set\n# CONFIG_ARM_ERRATA_857272 is not set\n# end of System Type\n\n#\n# Bus support\n#\n# CONFIG_ARM_ERRATA_814220 is not set\n# end of Bus support\n\n#\n# Kernel Features\n#\nCONFIG_HAVE_SMP=y\nCONFIG_SMP=y\nCONFIG_SMP_ON_UP=y\nCONFIG_ARM_CPU_TOPOLOGY=y\nCONFIG_SCHED_MC=y\nCONFIG_SCHED_SMT=y\nCONFIG_HAVE_ARM_SCU=y\n# CONFIG_HAVE_ARM_ARCH_TIMER is not set\nCONFIG_HAVE_ARM_TWD=y\n# CONFIG_MCPM is not set\n# CONFIG_BIG_LITTLE is not set\nCONFIG_VMSPLIT_3G=y\n# CONFIG_VMSPLIT_3G_OPT is not set\n# CONFIG_VMSPLIT_2G is not set\n# CONFIG_VMSPLIT_1G is not set\nCONFIG_PAGE_OFFSET=0xC0000000\nCONFIG_NR_CPUS=4\nCONFIG_HOTPLUG_CPU=y\n# CONFIG_ARM_PSCI is not set\nCONFIG_ARCH_NR_GPIO=1024\nCONFIG_HZ_FIXED=0\nCONFIG_HZ_100=y\n# CONFIG_HZ_200 is not set\n# CONFIG_HZ_250 is not set\n# CONFIG_HZ_300 is not set\n# CONFIG_HZ_500 is not set\n# CONFIG_HZ_1000 is not set\nCONFIG_HZ=100\nCONFIG_SCHED_HRTICK=y\n# CONFIG_THUMB2_KERNEL is not set\nCONFIG_ARM_PATCH_IDIV=y\nCONFIG_AEABI=y\n# CONFIG_OABI_COMPAT is not set\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_FLATMEM_ENABLE=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_HIGHMEM=y\n# CONFIG_HIGHPTE is not set\nCONFIG_CPU_SW_DOMAIN_PAN=y\nCONFIG_HW_PERF_EVENTS=y\nCONFIG_ARCH_WANT_GENERAL_HUGETLB=y\nCONFIG_ARM_MODULE_PLTS=y\nCONFIG_FORCE_MAX_ZONEORDER=11\nCONFIG_ALIGNMENT_TRAP=y\n# CONFIG_UACCESS_WITH_MEMCPY is not set\n# CONFIG_PARAVIRT is not set\n# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set\n# CONFIG_XEN is not set\n# end of Kernel Features\n\n#\n# Boot options\n#\nCONFIG_USE_OF=y\nCONFIG_ATAGS=y\n# CONFIG_DEPRECATED_PARAM_STRUCT is not set\nCONFIG_ZBOOT_ROM_TEXT=0x0\nCONFIG_ZBOOT_ROM_BSS=0x0\n# CONFIG_ARM_APPENDED_DTB is not set\nCONFIG_CMDLINE=\"console=ttyPS0,115200n8 root=/dev/ram rw initrd=0x00800000,16M earlyprintk mtdparts=physmap-flash.0:512K(nor-fsbl),512K(nor-u-boot),5M(nor-linux),9M(nor-user),1M(nor-scratch),-(nor-rootfs)\"\nCONFIG_CMDLINE_FROM_BOOTLOADER=y\n# CONFIG_CMDLINE_EXTEND is not set\n# CONFIG_CMDLINE_FORCE is not set\n# CONFIG_KEXEC is not set\n# CONFIG_CRASH_DUMP is not set\nCONFIG_AUTO_ZRELADDR=y\n# CONFIG_EFI is not set\n# end of Boot options\n\n#\n# CPU Power Management\n#\n\n#\n# CPU Frequency scaling\n#\n# CONFIG_CPU_FREQ is not set\n# end of CPU Frequency scaling\n\n#\n# CPU Idle\n#\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_GOV_LADDER=y\nCONFIG_CPU_IDLE_GOV_MENU=y\n# CONFIG_CPU_IDLE_GOV_TEO is not set\n\n#\n# ARM CPU Idle Drivers\n#\n# CONFIG_ARM_CPUIDLE is not set\nCONFIG_ARM_ZYNQ_CPUIDLE=y\n# end of ARM CPU Idle Drivers\n# end of CPU Idle\n# end of CPU Power Management\n\n#\n# Floating point emulation\n#\n\n#\n# At least one emulation must be selected\n#\nCONFIG_VFP=y\nCONFIG_VFPv3=y\nCONFIG_NEON=y\n# CONFIG_KERNEL_MODE_NEON is not set\n# end of Floating point emulation\n\n#\n# Power management options\n#\nCONFIG_SUSPEND=y\nCONFIG_SUSPEND_FREEZER=y\n# CONFIG_SUSPEND_SKIP_SYNC is not set\n# CONFIG_HIBERNATION is not set\nCONFIG_PM_SLEEP=y\nCONFIG_PM_SLEEP_SMP=y\n# CONFIG_PM_AUTOSLEEP is not set\n# CONFIG_PM_WAKELOCKS is not set\nCONFIG_PM=y\n# CONFIG_PM_DEBUG is not set\n# CONFIG_APM_EMULATION is not set\nCONFIG_PM_CLK=y\n# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set\nCONFIG_CPU_PM=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARM_CPU_SUSPEND=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\n# end of Power management options\n\n# CONFIG_ARM_CRYPTO is not set\nCONFIG_AS_VFP_VMRS_FPINST=y\n\n#\n# General architecture-dependent options\n#\n# CONFIG_KPROBES is not set\n# CONFIG_JUMP_LABEL is not set\nCONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y\nCONFIG_ARCH_USE_BUILTIN_BSWAP=y\nCONFIG_HAVE_KPROBES=y\nCONFIG_HAVE_KRETPROBES=y\nCONFIG_HAVE_OPTPROBES=y\nCONFIG_HAVE_NMI=y\nCONFIG_TRACE_IRQFLAGS_SUPPORT=y\nCONFIG_HAVE_ARCH_TRACEHOOK=y\nCONFIG_HAVE_DMA_CONTIGUOUS=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_ARCH_HAS_FORTIFY_SOURCE=y\nCONFIG_ARCH_HAS_KEEPINITRD=y\nCONFIG_ARCH_HAS_SET_MEMORY=y\nCONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y\nCONFIG_HAVE_RSEQ=y\nCONFIG_HAVE_HW_BREAKPOINT=y\nCONFIG_HAVE_PERF_REGS=y\nCONFIG_HAVE_PERF_USER_STACK_DUMP=y\nCONFIG_HAVE_ARCH_JUMP_LABEL=y\nCONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y\nCONFIG_ARCH_WANT_IPC_PARSE_VERSION=y\nCONFIG_HAVE_ARCH_SECCOMP=y\nCONFIG_HAVE_ARCH_SECCOMP_FILTER=y\nCONFIG_SECCOMP=y\nCONFIG_SECCOMP_FILTER=y\n# CONFIG_SECCOMP_CACHE_DEBUG is not set\nCONFIG_HAVE_STACKPROTECTOR=y\nCONFIG_STACKPROTECTOR=y\nCONFIG_STACKPROTECTOR_STRONG=y\nCONFIG_LTO_NONE=y\nCONFIG_HAVE_CONTEXT_TRACKING=y\nCONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y\nCONFIG_HAVE_IRQ_TIME_ACCOUNTING=y\nCONFIG_HAVE_MOD_ARCH_SPECIFIC=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_ARCH_HAS_ELF_RANDOMIZE=y\nCONFIG_HAVE_ARCH_MMAP_RND_BITS=y\nCONFIG_HAVE_EXIT_THREAD=y\nCONFIG_ARCH_MMAP_RND_BITS=8\nCONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_OLD_SIGACTION=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y\nCONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y\nCONFIG_STRICT_KERNEL_RWX=y\nCONFIG_ARCH_HAS_STRICT_MODULE_RWX=y\nCONFIG_STRICT_MODULE_RWX=y\nCONFIG_ARCH_HAS_PHYS_TO_DMA=y\n# CONFIG_LOCK_EVENT_COUNTS is not set\nCONFIG_ARCH_WANT_LD_ORPHAN_WARN=y\nCONFIG_HAVE_ARCH_PFN_VALID=y\n\n#\n# GCOV-based kernel profiling\n#\n# CONFIG_GCOV_KERNEL is not set\nCONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y\n# end of GCOV-based kernel profiling\n\nCONFIG_HAVE_GCC_PLUGINS=y\n# CONFIG_GCC_PLUGINS is not set\n# end of General architecture-dependent options\n\nCONFIG_RT_MUTEXES=y\nCONFIG_BASE_SMALL=0\nCONFIG_MODULES=y\n# CONFIG_MODULE_FORCE_LOAD is not set\nCONFIG_MODULE_UNLOAD=y\nCONFIG_MODULE_FORCE_UNLOAD=y\nCONFIG_MODVERSIONS=y\n# CONFIG_MODULE_SRCVERSION_ALL is not set\n# CONFIG_MODULE_SIG is not set\nCONFIG_MODULE_COMPRESS_NONE=y\n# CONFIG_MODULE_COMPRESS_GZIP is not set\n# CONFIG_MODULE_COMPRESS_XZ is not set\n# CONFIG_MODULE_COMPRESS_ZSTD is not set\n# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set\nCONFIG_MODPROBE_PATH=\"/sbin/modprobe\"\n# CONFIG_TRIM_UNUSED_KSYMS is not set\nCONFIG_MODULES_TREE_LOOKUP=y\nCONFIG_BLOCK=y\n# CONFIG_BLK_DEV_BSGLIB is not set\n# CONFIG_BLK_DEV_INTEGRITY is not set\n# CONFIG_BLK_DEV_ZONED is not set\n# CONFIG_BLK_WBT is not set\nCONFIG_BLK_DEBUG_FS=y\n# CONFIG_BLK_SED_OPAL is not set\n# CONFIG_BLK_INLINE_ENCRYPTION is not set\n\n#\n# Partition Types\n#\n# CONFIG_PARTITION_ADVANCED is not set\nCONFIG_MSDOS_PARTITION=y\nCONFIG_EFI_PARTITION=y\n# end of Partition Types\n\nCONFIG_BLK_PM=y\n\n#\n# IO Schedulers\n#\nCONFIG_MQ_IOSCHED_DEADLINE=y\nCONFIG_MQ_IOSCHED_KYBER=y\n# CONFIG_IOSCHED_BFQ is not set\n# end of IO Schedulers\n\nCONFIG_ASN1=y\nCONFIG_UNINLINE_SPIN_UNLOCK=y\nCONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y\nCONFIG_FREEZER=y\n\n#\n# Executable file formats\n#\nCONFIG_BINFMT_ELF=y\n# CONFIG_BINFMT_ELF_FDPIC is not set\nCONFIG_ELFCORE=y\n# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set\nCONFIG_BINFMT_SCRIPT=y\nCONFIG_ARCH_HAS_BINFMT_FLAT=y\n# CONFIG_BINFMT_FLAT is not set\nCONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y\n# CONFIG_BINFMT_MISC is not set\nCONFIG_COREDUMP=y\n# end of Executable file formats\n\n#\n# Memory Management options\n#\nCONFIG_SELECT_MEMORY_MODEL=y\nCONFIG_FLATMEM_MANUAL=y\n# CONFIG_SPARSEMEM_MANUAL is not set\nCONFIG_FLATMEM=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_MEMORY_ISOLATION=y\nCONFIG_SPLIT_PTLOCK_CPUS=4\n# CONFIG_COMPACTION is not set\n# CONFIG_PAGE_REPORTING is not set\nCONFIG_MIGRATION=y\nCONFIG_CONTIG_ALLOC=y\nCONFIG_BOUNCE=y\n# CONFIG_KSM is not set\nCONFIG_DEFAULT_MMAP_MIN_ADDR=4096\n# CONFIG_CLEANCACHE is not set\n# CONFIG_FRONTSWAP is not set\nCONFIG_CMA=y\n# CONFIG_CMA_DEBUG is not set\n# CONFIG_CMA_DEBUGFS is not set\n# CONFIG_CMA_SYSFS is not set\nCONFIG_CMA_AREAS=7\n# CONFIG_ZPOOL is not set\n# CONFIG_ZSMALLOC is not set\nCONFIG_GENERIC_EARLY_IOREMAP=y\n# CONFIG_IDLE_PAGE_TRACKING is not set\n# CONFIG_PERCPU_STATS is not set\n# CONFIG_GUP_TEST is not set\nCONFIG_KMAP_LOCAL=y\nCONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y\n\n#\n# Data Access Monitoring\n#\n# CONFIG_DAMON is not set\n# end of Data Access Monitoring\n# end of Memory Management options\n\nCONFIG_NET=y\nCONFIG_NET_INGRESS=y\nCONFIG_SKB_EXTENSIONS=y\n\n#\n# Networking options\n#\nCONFIG_PACKET=y\n# CONFIG_PACKET_DIAG is not set\nCONFIG_UNIX=y\nCONFIG_UNIX_SCM=y\nCONFIG_AF_UNIX_OOB=y\n# CONFIG_UNIX_DIAG is not set\n# CONFIG_TLS is not set\nCONFIG_XFRM=y\n# CONFIG_XFRM_USER is not set\n# CONFIG_XFRM_INTERFACE is not set\n# CONFIG_XFRM_SUB_POLICY is not set\n# CONFIG_XFRM_MIGRATE is not set\n# CONFIG_XFRM_STATISTICS is not set\n# CONFIG_NET_KEY is not set\nCONFIG_INET=y\nCONFIG_IP_MULTICAST=y\n# CONFIG_IP_ADVANCED_ROUTER is not set\nCONFIG_IP_PNP=y\nCONFIG_IP_PNP_DHCP=y\nCONFIG_IP_PNP_BOOTP=y\nCONFIG_IP_PNP_RARP=y\nCONFIG_NET_IPIP=y\n# CONFIG_NET_IPGRE_DEMUX is not set\nCONFIG_NET_IP_TUNNEL=y\nCONFIG_IP_MROUTE_COMMON=y\nCONFIG_IP_MROUTE=y\n# CONFIG_IP_PIMSM_V1 is not set\n# CONFIG_IP_PIMSM_V2 is not set\n# CONFIG_SYN_COOKIES is not set\nCONFIG_NET_IPVTI=y\n# CONFIG_NET_FOU is not set\n# CONFIG_NET_FOU_IP_TUNNELS is not set\n# CONFIG_INET_AH is not set\n# CONFIG_INET_ESP is not set\n# CONFIG_INET_IPCOMP is not set\nCONFIG_INET_TUNNEL=y\nCONFIG_INET_DIAG=y\nCONFIG_INET_TCP_DIAG=y\n# CONFIG_INET_UDP_DIAG is not set\n# CONFIG_INET_RAW_DIAG is not set\n# CONFIG_INET_DIAG_DESTROY is not set\n# CONFIG_TCP_CONG_ADVANCED is not set\nCONFIG_TCP_CONG_CUBIC=y\nCONFIG_DEFAULT_TCP_CONG=\"cubic\"\n# CONFIG_TCP_MD5SIG is not set\nCONFIG_IPV6=y\n# CONFIG_IPV6_ROUTER_PREF is not set\n# CONFIG_IPV6_OPTIMISTIC_DAD is not set\n# CONFIG_INET6_AH is not set\n# CONFIG_INET6_ESP is not set\n# CONFIG_INET6_IPCOMP is not set\n# CONFIG_IPV6_MIP6 is not set\nCONFIG_IPV6_ILA=y\n# CONFIG_IPV6_VTI is not set\nCONFIG_IPV6_SIT=y\n# CONFIG_IPV6_SIT_6RD is not set\nCONFIG_IPV6_NDISC_NODETYPE=y\n# CONFIG_IPV6_TUNNEL is not set\n# CONFIG_IPV6_MULTIPLE_TABLES is not set\n# CONFIG_IPV6_MROUTE is not set\n# CONFIG_IPV6_SEG6_LWTUNNEL is not set\n# CONFIG_IPV6_SEG6_HMAC is not set\n# CONFIG_IPV6_RPL_LWTUNNEL is not set\n# CONFIG_IPV6_IOAM6_LWTUNNEL is not set\nCONFIG_MPTCP=y\nCONFIG_INET_MPTCP_DIAG=y\nCONFIG_MPTCP_IPV6=y\n# CONFIG_NETWORK_SECMARK is not set\nCONFIG_NET_PTP_CLASSIFY=y\nCONFIG_NETWORK_PHY_TIMESTAMPING=y\nCONFIG_NETFILTER=y\nCONFIG_NETFILTER_ADVANCED=y\n# CONFIG_BRIDGE_NETFILTER is not set\n\n#\n# Core Netfilter Configuration\n#\nCONFIG_NETFILTER_INGRESS=y\nCONFIG_NETFILTER_NETLINK=y\nCONFIG_NETFILTER_FAMILY_BRIDGE=y\n# CONFIG_NETFILTER_NETLINK_ACCT is not set\n# CONFIG_NETFILTER_NETLINK_QUEUE is not set\nCONFIG_NETFILTER_NETLINK_LOG=y\n# CONFIG_NETFILTER_NETLINK_OSF is not set\nCONFIG_NF_CONNTRACK=m\nCONFIG_NF_LOG_SYSLOG=y\nCONFIG_NF_CONNTRACK_MARK=y\n# CONFIG_NF_CONNTRACK_ZONES is not set\nCONFIG_NF_CONNTRACK_PROCFS=y\n# CONFIG_NF_CONNTRACK_EVENTS is not set\n# CONFIG_NF_CONNTRACK_TIMEOUT is not set\n# CONFIG_NF_CONNTRACK_TIMESTAMP is not set\n# CONFIG_NF_CONNTRACK_LABELS is not set\nCONFIG_NF_CT_PROTO_DCCP=y\nCONFIG_NF_CT_PROTO_SCTP=y\nCONFIG_NF_CT_PROTO_UDPLITE=y\n# CONFIG_NF_CONNTRACK_AMANDA is not set\n# CONFIG_NF_CONNTRACK_FTP is not set\n# CONFIG_NF_CONNTRACK_H323 is not set\n# CONFIG_NF_CONNTRACK_IRC is not set\n# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set\n# CONFIG_NF_CONNTRACK_SNMP is not set\n# CONFIG_NF_CONNTRACK_PPTP is not set\n# CONFIG_NF_CONNTRACK_SANE is not set\n# CONFIG_NF_CONNTRACK_SIP is not set\n# CONFIG_NF_CONNTRACK_TFTP is not set\nCONFIG_NF_CT_NETLINK=m\n# CONFIG_NETFILTER_NETLINK_GLUE_CT is not set\n# CONFIG_NF_NAT is not set\n# CONFIG_NF_TABLES is not set\nCONFIG_NETFILTER_XTABLES=y\n\n#\n# Xtables combined modules\n#\nCONFIG_NETFILTER_XT_MARK=y\nCONFIG_NETFILTER_XT_CONNMARK=m\n\n#\n# Xtables targets\n#\nCONFIG_NETFILTER_XT_TARGET_CHECKSUM=y\n# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set\n# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set\n# CONFIG_NETFILTER_XT_TARGET_DSCP is not set\n# CONFIG_NETFILTER_XT_TARGET_HL is not set\n# CONFIG_NETFILTER_XT_TARGET_HMARK is not set\n# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set\n# CONFIG_NETFILTER_XT_TARGET_LED is not set\nCONFIG_NETFILTER_XT_TARGET_LOG=y\n# CONFIG_NETFILTER_XT_TARGET_MARK is not set\n# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set\n# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set\n# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set\n# CONFIG_NETFILTER_XT_TARGET_TEE is not set\n# CONFIG_NETFILTER_XT_TARGET_TPROXY is not set\n# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set\n# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set\n\n#\n# Xtables matches\n#\n# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set\n# CONFIG_NETFILTER_XT_MATCH_BPF is not set\n# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set\n# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set\n# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set\n# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set\n# CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set\n# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set\nCONFIG_NETFILTER_XT_MATCH_CONNMARK=m\nCONFIG_NETFILTER_XT_MATCH_CONNTRACK=m\n# CONFIG_NETFILTER_XT_MATCH_CPU is not set\n# CONFIG_NETFILTER_XT_MATCH_DCCP is not set\n# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set\n# CONFIG_NETFILTER_XT_MATCH_DSCP is not set\n# CONFIG_NETFILTER_XT_MATCH_ECN is not set\n# CONFIG_NETFILTER_XT_MATCH_ESP is not set\n# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set\n# CONFIG_NETFILTER_XT_MATCH_HELPER is not set\n# CONFIG_NETFILTER_XT_MATCH_HL is not set\n# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set\n# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set\n# CONFIG_NETFILTER_XT_MATCH_L2TP is not set\n# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set\nCONFIG_NETFILTER_XT_MATCH_LIMIT=y\nCONFIG_NETFILTER_XT_MATCH_MAC=y\n# CONFIG_NETFILTER_XT_MATCH_MARK is not set\nCONFIG_NETFILTER_XT_MATCH_MULTIPORT=y\n# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set\n# CONFIG_NETFILTER_XT_MATCH_OSF is not set\n# CONFIG_NETFILTER_XT_MATCH_OWNER is not set\n# CONFIG_NETFILTER_XT_MATCH_POLICY is not set\n# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set\n# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set\n# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set\n# CONFIG_NETFILTER_XT_MATCH_REALM is not set\n# CONFIG_NETFILTER_XT_MATCH_RECENT is not set\n# CONFIG_NETFILTER_XT_MATCH_SCTP is not set\n# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set\nCONFIG_NETFILTER_XT_MATCH_STATE=m\n# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set\n# CONFIG_NETFILTER_XT_MATCH_STRING is not set\n# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set\n# CONFIG_NETFILTER_XT_MATCH_TIME is not set\n# CONFIG_NETFILTER_XT_MATCH_U32 is not set\n# end of Core Netfilter Configuration\n\n# CONFIG_IP_SET is not set\n# CONFIG_IP_VS is not set\n\n#\n# IP: Netfilter Configuration\n#\nCONFIG_NF_DEFRAG_IPV4=m\n# CONFIG_NF_SOCKET_IPV4 is not set\n# CONFIG_NF_TPROXY_IPV4 is not set\n# CONFIG_NF_DUP_IPV4 is not set\n# CONFIG_NF_LOG_ARP is not set\n# CONFIG_NF_LOG_IPV4 is not set\nCONFIG_NF_REJECT_IPV4=y\nCONFIG_IP_NF_IPTABLES=y\n# CONFIG_IP_NF_MATCH_AH is not set\n# CONFIG_IP_NF_MATCH_ECN is not set\n# CONFIG_IP_NF_MATCH_RPFILTER is not set\n# CONFIG_IP_NF_MATCH_TTL is not set\nCONFIG_IP_NF_FILTER=y\nCONFIG_IP_NF_TARGET_REJECT=y\n# CONFIG_IP_NF_TARGET_SYNPROXY is not set\n# CONFIG_IP_NF_NAT is not set\nCONFIG_IP_NF_MANGLE=y\n# CONFIG_IP_NF_TARGET_CLUSTERIP is not set\n# CONFIG_IP_NF_TARGET_ECN is not set\n# CONFIG_IP_NF_TARGET_TTL is not set\n# CONFIG_IP_NF_RAW is not set\n# CONFIG_IP_NF_ARPTABLES is not set\n# end of IP: Netfilter Configuration\n\n#\n# IPv6: Netfilter Configuration\n#\n# CONFIG_NF_SOCKET_IPV6 is not set\n# CONFIG_NF_TPROXY_IPV6 is not set\n# CONFIG_NF_DUP_IPV6 is not set\nCONFIG_NF_REJECT_IPV6=y\nCONFIG_NF_LOG_IPV6=y\nCONFIG_IP6_NF_IPTABLES=y\n# CONFIG_IP6_NF_MATCH_AH is not set\n# CONFIG_IP6_NF_MATCH_EUI64 is not set\n# CONFIG_IP6_NF_MATCH_FRAG is not set\n# CONFIG_IP6_NF_MATCH_OPTS is not set\n# CONFIG_IP6_NF_MATCH_HL is not set\n# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set\n# CONFIG_IP6_NF_MATCH_MH is not set\n# CONFIG_IP6_NF_MATCH_RPFILTER is not set\n# CONFIG_IP6_NF_MATCH_RT is not set\n# CONFIG_IP6_NF_MATCH_SRH is not set\n# CONFIG_IP6_NF_TARGET_HL is not set\nCONFIG_IP6_NF_FILTER=y\nCONFIG_IP6_NF_TARGET_REJECT=y\n# CONFIG_IP6_NF_TARGET_SYNPROXY is not set\nCONFIG_IP6_NF_MANGLE=y\n# CONFIG_IP6_NF_RAW is not set\n# CONFIG_IP6_NF_NAT is not set\n# end of IPv6: Netfilter Configuration\n\nCONFIG_NF_DEFRAG_IPV6=m\n# CONFIG_NF_CONNTRACK_BRIDGE is not set\nCONFIG_BRIDGE_NF_EBTABLES=y\n# CONFIG_BRIDGE_EBT_BROUTE is not set\nCONFIG_BRIDGE_EBT_T_FILTER=y\nCONFIG_BRIDGE_EBT_T_NAT=y\n# CONFIG_BRIDGE_EBT_802_3 is not set\n# CONFIG_BRIDGE_EBT_AMONG is not set\n# CONFIG_BRIDGE_EBT_ARP is not set\n# CONFIG_BRIDGE_EBT_IP is not set\n# CONFIG_BRIDGE_EBT_IP6 is not set\n# CONFIG_BRIDGE_EBT_LIMIT is not set\n# CONFIG_BRIDGE_EBT_MARK is not set\n# CONFIG_BRIDGE_EBT_PKTTYPE is not set\n# CONFIG_BRIDGE_EBT_STP is not set\n# CONFIG_BRIDGE_EBT_VLAN is not set\n# CONFIG_BRIDGE_EBT_ARPREPLY is not set\n# CONFIG_BRIDGE_EBT_DNAT is not set\nCONFIG_BRIDGE_EBT_MARK_T=y\n# CONFIG_BRIDGE_EBT_REDIRECT is not set\n# CONFIG_BRIDGE_EBT_SNAT is not set\n# CONFIG_BRIDGE_EBT_LOG is not set\n# CONFIG_BRIDGE_EBT_NFLOG is not set\nCONFIG_BPFILTER=y\nCONFIG_BPFILTER_UMH=m\n# CONFIG_IP_DCCP is not set\n# CONFIG_IP_SCTP is not set\n# CONFIG_RDS is not set\n# CONFIG_TIPC is not set\n# CONFIG_ATM is not set\n# CONFIG_L2TP is not set\nCONFIG_STP=y\nCONFIG_BRIDGE=y\nCONFIG_BRIDGE_IGMP_SNOOPING=y\nCONFIG_BRIDGE_VLAN_FILTERING=y\n# CONFIG_BRIDGE_MRP is not set\n# CONFIG_BRIDGE_CFM is not set\nCONFIG_NET_DSA=y\n# CONFIG_NET_DSA_TAG_AR9331 is not set\n# CONFIG_NET_DSA_TAG_BRCM is not set\n# CONFIG_NET_DSA_TAG_BRCM_LEGACY is not set\n# CONFIG_NET_DSA_TAG_BRCM_PREPEND is not set\n# CONFIG_NET_DSA_TAG_HELLCREEK is not set\n# CONFIG_NET_DSA_TAG_GSWIP is not set\n# CONFIG_NET_DSA_TAG_DSA is not set\n# CONFIG_NET_DSA_TAG_EDSA is not set\n# CONFIG_NET_DSA_TAG_MTK is not set\n# CONFIG_NET_DSA_TAG_KSZ is not set\n# CONFIG_NET_DSA_TAG_RTL4_A is not set\n# CONFIG_NET_DSA_TAG_OCELOT is not set\n# CONFIG_NET_DSA_TAG_OCELOT_8021Q is not set\n# CONFIG_NET_DSA_TAG_QCA is not set\n# CONFIG_NET_DSA_TAG_LAN9303 is not set\n# CONFIG_NET_DSA_TAG_SJA1105 is not set\n# CONFIG_NET_DSA_TAG_TRAILER is not set\n# CONFIG_NET_DSA_TAG_XRS700X is not set\nCONFIG_VLAN_8021Q=m\n# CONFIG_VLAN_8021Q_GVRP is not set\n# CONFIG_VLAN_8021Q_MVRP is not set\n# CONFIG_DECNET is not set\nCONFIG_LLC=y\n# CONFIG_LLC2 is not set\n# CONFIG_ATALK is not set\n# CONFIG_X25 is not set\n# CONFIG_LAPB is not set\n# CONFIG_PHONET is not set\n# CONFIG_6LOWPAN is not set\nCONFIG_IEEE802154=y\n# CONFIG_IEEE802154_NL802154_EXPERIMENTAL is not set\nCONFIG_IEEE802154_SOCKET=y\nCONFIG_MAC802154=y\n# CONFIG_NET_SCHED is not set\n# CONFIG_DCB is not set\nCONFIG_DNS_RESOLVER=y\nCONFIG_BATMAN_ADV=y\nCONFIG_BATMAN_ADV_BATMAN_V=y\nCONFIG_BATMAN_ADV_BLA=y\nCONFIG_BATMAN_ADV_DAT=y\n# CONFIG_BATMAN_ADV_NC is not set\nCONFIG_BATMAN_ADV_MCAST=y\n# CONFIG_BATMAN_ADV_DEBUG is not set\n# CONFIG_OPENVSWITCH is not set\n# CONFIG_VSOCKETS is not set\n# CONFIG_NETLINK_DIAG is not set\n# CONFIG_MPLS is not set\n# CONFIG_NET_NSH is not set\n# CONFIG_HSR is not set\nCONFIG_NET_SWITCHDEV=y\n# CONFIG_NET_L3_MASTER_DEV is not set\n# CONFIG_QRTR is not set\n# CONFIG_NET_NCSI is not set\nCONFIG_PCPU_DEV_REFCNT=y\nCONFIG_RPS=y\nCONFIG_RFS_ACCEL=y\nCONFIG_SOCK_RX_QUEUE_MAPPING=y\nCONFIG_XPS=y\n# CONFIG_CGROUP_NET_PRIO is not set\n# CONFIG_CGROUP_NET_CLASSID is not set\nCONFIG_NET_RX_BUSY_POLL=y\nCONFIG_BQL=y\nCONFIG_NET_FLOW_LIMIT=y\n\n#\n# Network testing\n#\n# CONFIG_NET_PKTGEN is not set\n# end of Network testing\n# end of Networking options\n\n# CONFIG_HAMRADIO is not set\n# CONFIG_CAN is not set\n# CONFIG_BT is not set\n# CONFIG_AF_RXRPC is not set\n# CONFIG_AF_KCM is not set\n# CONFIG_MCTP is not set\nCONFIG_WIRELESS=y\nCONFIG_WEXT_CORE=y\nCONFIG_WEXT_PROC=y\nCONFIG_CFG80211=y\nCONFIG_NL80211_TESTMODE=y\nCONFIG_CFG80211_DEVELOPER_WARNINGS=y\nCONFIG_CFG80211_CERTIFICATION_ONUS=y\nCONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y\nCONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y\nCONFIG_CFG80211_EXTRA_REGDB_KEYDIR=\"\"\n# CONFIG_CFG80211_REG_CELLULAR_HINTS is not set\n# CONFIG_CFG80211_REG_RELAX_NO_IR is not set\nCONFIG_CFG80211_DEFAULT_PS=y\nCONFIG_CFG80211_DEBUGFS=y\nCONFIG_CFG80211_CRDA_SUPPORT=y\nCONFIG_CFG80211_WEXT=y\nCONFIG_MAC80211=y\nCONFIG_MAC80211_HAS_RC=y\nCONFIG_MAC80211_RC_MINSTREL=y\nCONFIG_MAC80211_RC_DEFAULT_MINSTREL=y\nCONFIG_MAC80211_RC_DEFAULT=\"minstrel_ht\"\nCONFIG_MAC80211_MESH=y\nCONFIG_MAC80211_LEDS=y\nCONFIG_MAC80211_DEBUGFS=y\nCONFIG_MAC80211_MESSAGE_TRACING=y\nCONFIG_MAC80211_DEBUG_MENU=y\n# CONFIG_MAC80211_NOINLINE is not set\nCONFIG_MAC80211_VERBOSE_DEBUG=y\nCONFIG_MAC80211_MLME_DEBUG=y\nCONFIG_MAC80211_STA_DEBUG=y\nCONFIG_MAC80211_HT_DEBUG=y\n# CONFIG_MAC80211_OCB_DEBUG is not set\n# CONFIG_MAC80211_IBSS_DEBUG is not set\nCONFIG_MAC80211_PS_DEBUG=y\n# CONFIG_MAC80211_MPL_DEBUG is not set\n# CONFIG_MAC80211_MPATH_DEBUG is not set\n# CONFIG_MAC80211_MHWMP_DEBUG is not set\n# CONFIG_MAC80211_MESH_SYNC_DEBUG is not set\n# CONFIG_MAC80211_MESH_CSA_DEBUG is not set\n# CONFIG_MAC80211_MESH_PS_DEBUG is not set\n# CONFIG_MAC80211_TDLS_DEBUG is not set\nCONFIG_MAC80211_DEBUG_COUNTERS=y\nCONFIG_MAC80211_STA_HASH_MAX_SIZE=0\n# CONFIG_RFKILL is not set\n# CONFIG_NET_9P is not set\n# CONFIG_CAIF is not set\n# CONFIG_CEPH_LIB is not set\n# CONFIG_NFC is not set\n# CONFIG_PSAMPLE is not set\n# CONFIG_NET_IFE is not set\nCONFIG_LWTUNNEL=y\nCONFIG_LWTUNNEL_BPF=y\nCONFIG_DST_CACHE=y\nCONFIG_GRO_CELLS=y\nCONFIG_NET_SELFTESTS=y\nCONFIG_NET_DEVLINK=y\n# CONFIG_FAILOVER is not set\nCONFIG_ETHTOOL_NETLINK=y\n\n#\n# Device Drivers\n#\nCONFIG_ARM_AMBA=y\nCONFIG_HAVE_PCI=y\n# CONFIG_PCI is not set\n# CONFIG_PCCARD is not set\n\n#\n# Generic Driver Options\n#\n# CONFIG_UEVENT_HELPER is not set\nCONFIG_DEVTMPFS=y\nCONFIG_DEVTMPFS_MOUNT=y\nCONFIG_STANDALONE=y\nCONFIG_PREVENT_FIRMWARE_BUILD=y\n\n#\n# Firmware loader\n#\nCONFIG_FW_LOADER=y\nCONFIG_EXTRA_FIRMWARE=\"ad9467_intbypass_ad9517.stp ad9517.stp ad9517_fmcomms6.stp adau1761.bin imageon_edid.bin pzsdr-fmc-ad9517.stp Mykonos_M3.bin TaliseStream.bin TaliseTDDArmFirmware.bin TaliseTxArmFirmware.bin TaliseRxArmFirmware.bin Navassa_EvaluationFw.bin RxGainTable.csv RxGainTable_GainCompensated.csv ORxGainTable.csv TxAttenTable.csv Navassa_Stream.bin Navassa_CMOS_profile.json Navassa_LVDS_profile.json Navassa_CMOS_profile_adrv9003.json Navassa_LVDS_profile_adrv9003.json\"\nCONFIG_EXTRA_FIRMWARE_DIR=\"./firmware\"\n# CONFIG_FW_LOADER_USER_HELPER is not set\n# CONFIG_FW_LOADER_COMPRESS is not set\nCONFIG_FW_CACHE=y\n# end of Firmware loader\n\nCONFIG_ALLOW_DEV_COREDUMP=y\n# CONFIG_DEBUG_DRIVER is not set\n# CONFIG_DEBUG_DEVRES is not set\n# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set\n# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_CPU_VULNERABILITIES=y\nCONFIG_SOC_BUS=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_I2C=y\nCONFIG_REGMAP_SPI=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_DMA_SHARED_BUFFER=y\n# CONFIG_DMA_FENCE_TRACE is not set\nCONFIG_GENERIC_ARCH_TOPOLOGY=y\n# end of Generic Driver Options\n\n#\n# Bus devices\n#\n# CONFIG_BRCMSTB_GISB_ARB is not set\n# CONFIG_MOXTET is not set\n# CONFIG_VEXPRESS_CONFIG is not set\n# CONFIG_MHI_BUS is not set\n# end of Bus devices\n\nCONFIG_CONNECTOR=y\nCONFIG_PROC_EVENTS=y\n\n#\n# Firmware Drivers\n#\n\n#\n# ARM System Control and Management Interface Protocol\n#\n# CONFIG_ARM_SCMI_PROTOCOL is not set\n# end of ARM System Control and Management Interface Protocol\n\n# CONFIG_FIRMWARE_MEMMAP is not set\n# CONFIG_FW_CFG_SYSFS is not set\n# CONFIG_TRUSTED_FOUNDATIONS is not set\n# CONFIG_GOOGLE_FIRMWARE is not set\nCONFIG_HAVE_ARM_SMCCC=y\n\n#\n# Tegra firmware driver\n#\n# end of Tegra firmware driver\n# end of Firmware Drivers\n\n# CONFIG_GNSS is not set\nCONFIG_MTD=y\n# CONFIG_MTD_TESTS is not set\n\n#\n# Partition parsers\n#\n# CONFIG_MTD_AR7_PARTS is not set\nCONFIG_MTD_CMDLINE_PARTS=y\nCONFIG_MTD_OF_PARTS=y\n# CONFIG_MTD_AFS_PARTS is not set\n# CONFIG_MTD_REDBOOT_PARTS is not set\n# end of Partition parsers\n\n#\n# User Modules And Translation Layers\n#\nCONFIG_MTD_BLKDEVS=y\nCONFIG_MTD_BLOCK=y\n\n#\n# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK.\n#\n# CONFIG_FTL is not set\n# CONFIG_NFTL is not set\n# CONFIG_INFTL is not set\n# CONFIG_RFD_FTL is not set\n# CONFIG_SSFDC is not set\n# CONFIG_SM_FTL is not set\n# CONFIG_MTD_OOPS is not set\n# CONFIG_MTD_SWAP is not set\n# CONFIG_MTD_PARTITIONED_MASTER is not set\n\n#\n# RAM/ROM/Flash chip drivers\n#\nCONFIG_MTD_CFI=y\n# CONFIG_MTD_JEDECPROBE is not set\nCONFIG_MTD_GEN_PROBE=y\n# CONFIG_MTD_CFI_ADV_OPTIONS is not set\nCONFIG_MTD_MAP_BANK_WIDTH_1=y\nCONFIG_MTD_MAP_BANK_WIDTH_2=y\nCONFIG_MTD_MAP_BANK_WIDTH_4=y\nCONFIG_MTD_CFI_I1=y\nCONFIG_MTD_CFI_I2=y\n# CONFIG_MTD_CFI_INTELEXT is not set\nCONFIG_MTD_CFI_AMDSTD=y\n# CONFIG_MTD_CFI_STAA is not set\nCONFIG_MTD_CFI_UTIL=y\n# CONFIG_MTD_RAM is not set\n# CONFIG_MTD_ROM is not set\n# CONFIG_MTD_ABSENT is not set\n# end of RAM/ROM/Flash chip drivers\n\n#\n# Mapping drivers for chip access\n#\n# CONFIG_MTD_COMPLEX_MAPPINGS is not set\nCONFIG_MTD_PHYSMAP=y\n# CONFIG_MTD_PHYSMAP_COMPAT is not set\nCONFIG_MTD_PHYSMAP_OF=y\n# CONFIG_MTD_PHYSMAP_VERSATILE is not set\n# CONFIG_MTD_PHYSMAP_GEMINI is not set\n# CONFIG_MTD_PHYSMAP_IXP4XX is not set\n# CONFIG_MTD_PLATRAM is not set\n# end of Mapping drivers for chip access\n\n#\n# Self-contained MTD device drivers\n#\n# CONFIG_MTD_DATAFLASH is not set\n# CONFIG_MTD_MCHP23K256 is not set\n# CONFIG_MTD_MCHP48L640 is not set\n# CONFIG_MTD_SST25L is not set\n# CONFIG_MTD_SLRAM is not set\n# CONFIG_MTD_PHRAM is not set\n# CONFIG_MTD_MTDRAM is not set\n# CONFIG_MTD_BLOCK2MTD is not set\n\n#\n# Disk-On-Chip Device Drivers\n#\n# CONFIG_MTD_DOCG3 is not set\n# end of Self-contained MTD device drivers\n\n#\n# NAND\n#\n# CONFIG_MTD_ONENAND is not set\n# CONFIG_MTD_RAW_NAND is not set\n# CONFIG_MTD_SPI_NAND is not set\n\n#\n# ECC engine support\n#\n# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set\n# CONFIG_MTD_NAND_ECC_SW_BCH is not set\n# end of ECC engine support\n# end of NAND\n\n#\n# LPDDR & LPDDR2 PCM memory drivers\n#\n# CONFIG_MTD_LPDDR is not set\n# CONFIG_MTD_LPDDR2_NVM is not set\n# end of LPDDR & LPDDR2 PCM memory drivers\n\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y\n# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set\nCONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y\n# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set\n# CONFIG_MTD_UBI is not set\n# CONFIG_MTD_HYPERBUS is not set\nCONFIG_DTC=y\nCONFIG_OF=y\n# CONFIG_OF_UNITTEST is not set\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_DYNAMIC=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_RESERVED_MEM=y\nCONFIG_OF_RESOLVE=y\nCONFIG_OF_OVERLAY=y\nCONFIG_OF_CONFIGFS=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\n# CONFIG_PARPORT is not set\nCONFIG_BLK_DEV=y\n# CONFIG_BLK_DEV_NULL_BLK is not set\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_DEV_LOOP_MIN_COUNT=8\n# CONFIG_BLK_DEV_CRYPTOLOOP is not set\n# CONFIG_BLK_DEV_DRBD is not set\n# CONFIG_BLK_DEV_NBD is not set\nCONFIG_BLK_DEV_RAM=y\nCONFIG_BLK_DEV_RAM_COUNT=16\nCONFIG_BLK_DEV_RAM_SIZE=16384\n# CONFIG_CDROM_PKTCDVD is not set\n# CONFIG_ATA_OVER_ETH is not set\n# CONFIG_BLK_DEV_RBD is not set\n\n#\n# NVME Support\n#\n# CONFIG_NVME_FC is not set\n# CONFIG_NVME_TCP is not set\n# CONFIG_NVME_TARGET is not set\n# end of NVME Support\n\n#\n# Misc devices\n#\nCONFIG_AD525X_DPOT=y\nCONFIG_AD525X_DPOT_I2C=y\nCONFIG_AD525X_DPOT_SPI=y\nCONFIG_ADI_AXI_DATA_OFFLOAD=y\nCONFIG_ADI_AXI_TDD=y\n# CONFIG_DUMMY_IRQ is not set\n# CONFIG_ICS932S401 is not set\n# CONFIG_ENCLOSURE_SERVICES is not set\n# CONFIG_APDS9802ALS is not set\n# CONFIG_ISL29003 is not set\n# CONFIG_ISL29020 is not set\n# CONFIG_SENSORS_TSL2550 is not set\n# CONFIG_SENSORS_BH1770 is not set\n# CONFIG_SENSORS_APDS990X is not set\n# CONFIG_HMC6352 is not set\n# CONFIG_DS1682 is not set\n# CONFIG_LATTICE_ECP3_CONFIG is not set\n# CONFIG_SRAM is not set\n# CONFIG_XILINX_SDFEC is not set\n# CONFIG_XILINX_FLEX_PM is not set\n# CONFIG_XILINX_TRAFGEN is not set\n# CONFIG_HISI_HIKEY_USB is not set\n# CONFIG_XILINX_JESD204B is not set\n# CONFIG_C2PORT is not set\n\n#\n# EEPROM support\n#\nCONFIG_EEPROM_AT24=y\nCONFIG_EEPROM_AT25=y\n# CONFIG_EEPROM_LEGACY is not set\n# CONFIG_EEPROM_MAX6875 is not set\n# CONFIG_EEPROM_93CX6 is not set\n# CONFIG_EEPROM_93XX46 is not set\n# CONFIG_EEPROM_IDT_89HPESX is not set\n# CONFIG_EEPROM_EE1004 is not set\n# end of EEPROM support\n\n#\n# Texas Instruments shared transport line discipline\n#\n# CONFIG_TI_ST is not set\n# end of Texas Instruments shared transport line discipline\n\n# CONFIG_SENSORS_LIS3_SPI is not set\n# CONFIG_SENSORS_LIS3_I2C is not set\n# CONFIG_ALTERA_STAPL is not set\n\n#\n# MathWorks IP Drivers\n#\nCONFIG_MATHWORKS_IP_CORE=y\nCONFIG_MWIPCORE=y\nCONFIG_MWIPCORE_DMA_STREAMING=y\nCONFIG_MWIPCORE_IIO_STREAMING=y\nCONFIG_MWIPCORE_IIO_MM=y\nCONFIG_MWIPCORE_IIO_SHAREDMEM=y\nCONFIG_MATHWORKS_GENERIC_OF=y\n# end of MathWorks IP Drivers\n\n# CONFIG_ECHO is not set\n# CONFIG_MISC_RTSX_USB is not set\n# CONFIG_PVPANIC is not set\n# end of Misc devices\n\n#\n# SCSI device support\n#\nCONFIG_SCSI_MOD=y\n# CONFIG_RAID_ATTRS is not set\nCONFIG_SCSI_COMMON=y\nCONFIG_SCSI=y\nCONFIG_SCSI_DMA=y\nCONFIG_SCSI_PROC_FS=y\n\n#\n# SCSI support type (disk, tape, CD-ROM)\n#\nCONFIG_BLK_DEV_SD=y\n# CONFIG_CHR_DEV_ST is not set\n# CONFIG_BLK_DEV_SR is not set\nCONFIG_CHR_DEV_SG=y\n# CONFIG_BLK_DEV_BSG is not set\n# CONFIG_CHR_DEV_SCH is not set\n# CONFIG_SCSI_CONSTANTS is not set\n# CONFIG_SCSI_LOGGING is not set\n# CONFIG_SCSI_SCAN_ASYNC is not set\n\n#\n# SCSI Transports\n#\n# CONFIG_SCSI_SPI_ATTRS is not set\n# CONFIG_SCSI_FC_ATTRS is not set\n# CONFIG_SCSI_ISCSI_ATTRS is not set\n# CONFIG_SCSI_SAS_ATTRS is not set\n# CONFIG_SCSI_SAS_LIBSAS is not set\n# CONFIG_SCSI_SRP_ATTRS is not set\n# end of SCSI Transports\n\nCONFIG_SCSI_LOWLEVEL=y\n# CONFIG_ISCSI_TCP is not set\n# CONFIG_ISCSI_BOOT_SYSFS is not set\n# CONFIG_SCSI_UFSHCD is not set\n# CONFIG_SCSI_DEBUG is not set\n# CONFIG_SCSI_DH is not set\n# end of SCSI device support\n\n# CONFIG_ATA is not set\n# CONFIG_MD is not set\n# CONFIG_TARGET_CORE is not set\nCONFIG_NETDEVICES=y\nCONFIG_MII=y\nCONFIG_NET_CORE=y\n# CONFIG_BONDING is not set\n# CONFIG_DUMMY is not set\n# CONFIG_WIREGUARD is not set\n# CONFIG_EQUALIZER is not set\n# CONFIG_NET_TEAM is not set\n# CONFIG_MACVLAN is not set\n# CONFIG_IPVLAN is not set\n# CONFIG_VXLAN is not set\n# CONFIG_GENEVE is not set\n# CONFIG_BAREUDP is not set\n# CONFIG_GTP is not set\nCONFIG_MACSEC=y\n# CONFIG_NETCONSOLE is not set\nCONFIG_TUN=y\n# CONFIG_TUN_VNET_CROSS_LE is not set\n# CONFIG_VETH is not set\n# CONFIG_NLMON is not set\n\n#\n# Distributed Switch Architecture drivers\n#\n# CONFIG_B53 is not set\n# CONFIG_NET_DSA_BCM_SF2 is not set\n# CONFIG_NET_DSA_LOOP is not set\n# CONFIG_NET_DSA_LANTIQ_GSWIP is not set\n# CONFIG_NET_DSA_MT7530 is not set\n# CONFIG_NET_DSA_MV88E6060 is not set\n# CONFIG_NET_DSA_MICROCHIP_KSZ9477 is not set\n# CONFIG_NET_DSA_MICROCHIP_KSZ8795 is not set\n# CONFIG_NET_DSA_MV88E6XXX is not set\n# CONFIG_NET_DSA_MSCC_SEVILLE is not set\n# CONFIG_NET_DSA_AR9331 is not set\n# CONFIG_NET_DSA_SJA1105 is not set\n# CONFIG_NET_DSA_XRS700X_I2C is not set\n# CONFIG_NET_DSA_XRS700X_MDIO is not set\n# CONFIG_NET_DSA_QCA8K is not set\n# CONFIG_NET_DSA_REALTEK_SMI is not set\n# CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set\n# CONFIG_NET_DSA_SMSC_LAN9303_MDIO is not set\n# CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set\n# CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set\n# end of Distributed Switch Architecture drivers\n\nCONFIG_ETHERNET=y\nCONFIG_NET_VENDOR_ALACRITECH=y\n# CONFIG_ALTERA_TSE is not set\nCONFIG_NET_VENDOR_AMAZON=y\nCONFIG_NET_VENDOR_AQUANTIA=y\nCONFIG_NET_VENDOR_ARC=y\n# CONFIG_NET_VENDOR_BROADCOM is not set\nCONFIG_NET_VENDOR_CADENCE=y\nCONFIG_MACB=y\nCONFIG_MACB_USE_HWSTAMP=y\nCONFIG_NET_VENDOR_CAVIUM=y\n# CONFIG_NET_VENDOR_CIRRUS is not set\nCONFIG_NET_VENDOR_CORTINA=y\n# CONFIG_GEMINI_ETHERNET is not set\n# CONFIG_DM9000 is not set\n# CONFIG_DNET is not set\nCONFIG_NET_VENDOR_EZCHIP=y\n# CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set\n# CONFIG_NET_VENDOR_FARADAY is not set\nCONFIG_NET_VENDOR_GOOGLE=y\nCONFIG_NET_VENDOR_HISILICON=y\n# CONFIG_HIX5HD2_GMAC is not set\n# CONFIG_HISI_FEMAC is not set\n# CONFIG_HIP04_ETH is not set\n# CONFIG_HNS_DSAF is not set\n# CONFIG_HNS_ENET is not set\nCONFIG_NET_VENDOR_HUAWEI=y\n# CONFIG_NET_VENDOR_INTEL is not set\nCONFIG_NET_VENDOR_ADI=y\nCONFIG_ADIN1110=y\nCONFIG_NET_VENDOR_LITEX=y\n# CONFIG_LITEX_LITEETH is not set\n# CONFIG_NET_VENDOR_MARVELL is not set\nCONFIG_NET_VENDOR_MELLANOX=y\n# CONFIG_MLXSW_CORE is not set\n# CONFIG_MLXFW is not set\n# CONFIG_NET_VENDOR_MICREL is not set\n# CONFIG_NET_VENDOR_MICROCHIP is not set\nCONFIG_NET_VENDOR_MICROSEMI=y\n# CONFIG_MSCC_OCELOT_SWITCH is not set\nCONFIG_NET_VENDOR_MICROSOFT=y\nCONFIG_NET_VENDOR_NI=y\n# CONFIG_NI_XGE_MANAGEMENT_ENET is not set\n# CONFIG_NET_VENDOR_NATSEMI is not set\nCONFIG_NET_VENDOR_NETRONOME=y\n# CONFIG_ETHOC is not set\nCONFIG_NET_VENDOR_PENSANDO=y\nCONFIG_NET_VENDOR_QUALCOMM=y\n# CONFIG_QCA7000_SPI is not set\n# CONFIG_QCOM_EMAC is not set\n# CONFIG_RMNET is not set\nCONFIG_NET_VENDOR_RENESAS=y\nCONFIG_NET_VENDOR_ROCKER=y\nCONFIG_NET_VENDOR_SAMSUNG=y\n# CONFIG_SXGBE_ETH is not set\n# CONFIG_NET_VENDOR_SEEQ is not set\nCONFIG_NET_VENDOR_SOLARFLARE=y\n# CONFIG_NET_VENDOR_SMSC is not set\nCONFIG_NET_VENDOR_SOCIONEXT=y\n# CONFIG_NET_VENDOR_STMICRO is not set\nCONFIG_NET_VENDOR_SYNOPSYS=y\n# CONFIG_DWC_XLGMAC is not set\n# CONFIG_NET_VENDOR_VIA is not set\n# CONFIG_NET_VENDOR_WIZNET is not set\nCONFIG_NET_VENDOR_XILINX=y\n# CONFIG_XILINX_EMACLITE is not set\n# CONFIG_XILINX_AXI_EMAC is not set\n# CONFIG_XILINX_LL_TEMAC is not set\nCONFIG_PHYLINK=y\nCONFIG_PHYLIB=y\nCONFIG_SWPHY=y\n# CONFIG_LED_TRIGGER_PHY is not set\nCONFIG_FIXED_PHY=y\n# CONFIG_SFP is not set\n\n#\n# MII PHY device drivers\n#\n# CONFIG_AMD_PHY is not set\nCONFIG_ADIN_PHY=y\nCONFIG_ADIN1100_PHY=y\n# CONFIG_AQUANTIA_PHY is not set\nCONFIG_AX88796B_PHY=y\n# CONFIG_BROADCOM_PHY is not set\n# CONFIG_BCM54140_PHY is not set\n# CONFIG_BCM7XXX_PHY is not set\n# CONFIG_BCM84881_PHY is not set\n# CONFIG_BCM87XX_PHY is not set\n# CONFIG_CICADA_PHY is not set\n# CONFIG_CORTINA_PHY is not set\n# CONFIG_DAVICOM_PHY is not set\n# CONFIG_ICPLUS_PHY is not set\n# CONFIG_LXT_PHY is not set\n# CONFIG_INTEL_XWAY_PHY is not set\n# CONFIG_LSI_ET1011C_PHY is not set\nCONFIG_MARVELL_PHY=y\n# CONFIG_MARVELL_10G_PHY is not set\n# CONFIG_MARVELL_88X2222_PHY is not set\n# CONFIG_MAXLINEAR_GPHY is not set\n# CONFIG_MEDIATEK_GE_PHY is not set\n# CONFIG_MICREL_PHY is not set\n# CONFIG_MICROCHIP_PHY is not set\n# CONFIG_MICROCHIP_T1_PHY is not set\n# CONFIG_MICROSEMI_PHY is not set\n# CONFIG_MOTORCOMM_PHY is not set\n# CONFIG_NATIONAL_PHY is not set\n# CONFIG_NXP_C45_TJA11XX_PHY is not set\n# CONFIG_NXP_TJA11XX_PHY is not set\n# CONFIG_AT803X_PHY is not set\n# CONFIG_QSEMI_PHY is not set\n# CONFIG_REALTEK_PHY is not set\n# CONFIG_RENESAS_PHY is not set\n# CONFIG_ROCKCHIP_PHY is not set\n# CONFIG_SMSC_PHY is not set\n# CONFIG_STE10XP is not set\n# CONFIG_TERANETICS_PHY is not set\n# CONFIG_DP83822_PHY is not set\n# CONFIG_DP83TC811_PHY is not set\n# CONFIG_DP83848_PHY is not set\n# CONFIG_DP83867_PHY is not set\n# CONFIG_DP83869_PHY is not set\n# CONFIG_VITESSE_PHY is not set\n# CONFIG_XILINX_PHY is not set\nCONFIG_XILINX_GMII2RGMII=y\n# CONFIG_MICREL_KS8995MA is not set\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_BUS=y\nCONFIG_FWNODE_MDIO=y\nCONFIG_OF_MDIO=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MDIO_BITBANG=y\n# CONFIG_MDIO_BCM_UNIMAC is not set\n# CONFIG_MDIO_GPIO is not set\n# CONFIG_MDIO_HISI_FEMAC is not set\n# CONFIG_MDIO_MVUSB is not set\n# CONFIG_MDIO_MSCC_MIIM is not set\n# CONFIG_MDIO_IPQ4019 is not set\n# CONFIG_MDIO_IPQ8064 is not set\n\n#\n# MDIO Multiplexers\n#\n# CONFIG_MDIO_BUS_MUX_GPIO is not set\n# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set\n# CONFIG_MDIO_BUS_MUX_MMIOREG is not set\n\n#\n# PCS device drivers\n#\n# CONFIG_PCS_XPCS is not set\n# end of PCS device drivers\n\n# CONFIG_PPP is not set\n# CONFIG_SLIP is not set\nCONFIG_USB_NET_DRIVERS=y\n# CONFIG_USB_CATC is not set\n# CONFIG_USB_KAWETH is not set\n# CONFIG_USB_PEGASUS is not set\n# CONFIG_USB_RTL8150 is not set\n# CONFIG_USB_RTL8152 is not set\n# CONFIG_USB_LAN78XX is not set\nCONFIG_USB_USBNET=y\nCONFIG_USB_NET_AX8817X=y\nCONFIG_USB_NET_AX88179_178A=y\nCONFIG_USB_NET_CDCETHER=y\n# CONFIG_USB_NET_CDC_EEM is not set\nCONFIG_USB_NET_CDC_NCM=y\n# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set\n# CONFIG_USB_NET_CDC_MBIM is not set\n# CONFIG_USB_NET_DM9601 is not set\n# CONFIG_USB_NET_SR9700 is not set\n# CONFIG_USB_NET_SR9800 is not set\n# CONFIG_USB_NET_SMSC75XX is not set\n# CONFIG_USB_NET_SMSC95XX is not set\n# CONFIG_USB_NET_GL620A is not set\nCONFIG_USB_NET_NET1080=y\n# CONFIG_USB_NET_PLUSB is not set\n# CONFIG_USB_NET_MCS7830 is not set\n# CONFIG_USB_NET_RNDIS_HOST is not set\nCONFIG_USB_NET_CDC_SUBSET_ENABLE=y\nCONFIG_USB_NET_CDC_SUBSET=y\n# CONFIG_USB_ALI_M5632 is not set\n# CONFIG_USB_AN2720 is not set\nCONFIG_USB_BELKIN=y\nCONFIG_USB_ARMLINUX=y\n# CONFIG_USB_EPSON2888 is not set\n# CONFIG_USB_KC2190 is not set\nCONFIG_USB_NET_ZAURUS=y\n# CONFIG_USB_NET_CX82310_ETH is not set\n# CONFIG_USB_NET_KALMIA is not set\n# CONFIG_USB_NET_QMI_WWAN is not set\n# CONFIG_USB_NET_INT51X1 is not set\n# CONFIG_USB_IPHETH is not set\n# CONFIG_USB_SIERRA_NET is not set\n# CONFIG_USB_VL600 is not set\n# CONFIG_USB_NET_CH9200 is not set\n# CONFIG_USB_NET_AQC111 is not set\n# CONFIG_USB_RTL8153_ECM is not set\n# CONFIG_WLAN is not set\n# CONFIG_WAN is not set\nCONFIG_IEEE802154_DRIVERS=y\n# CONFIG_IEEE802154_FAKELB is not set\n# CONFIG_IEEE802154_AT86RF230 is not set\n# CONFIG_IEEE802154_MRF24J40 is not set\n# CONFIG_IEEE802154_CC2520 is not set\n# CONFIG_IEEE802154_ATUSB is not set\nCONFIG_IEEE802154_ADF7242=y\n# CONFIG_IEEE802154_CA8210 is not set\n# CONFIG_IEEE802154_MCR20A is not set\n# CONFIG_IEEE802154_HWSIM is not set\n\n#\n# Wireless WAN\n#\n# CONFIG_WWAN is not set\n# end of Wireless WAN\n\n# CONFIG_NETDEVSIM is not set\n# CONFIG_NET_FAILOVER is not set\n# CONFIG_ISDN is not set\n\n#\n# Input device support\n#\nCONFIG_INPUT=y\nCONFIG_INPUT_LEDS=y\nCONFIG_INPUT_FF_MEMLESS=y\nCONFIG_INPUT_SPARSEKMAP=y\n# CONFIG_INPUT_MATRIXKMAP is not set\n\n#\n# Userland interfaces\n#\n# CONFIG_INPUT_MOUSEDEV is not set\n# CONFIG_INPUT_JOYDEV is not set\nCONFIG_INPUT_EVDEV=y\n# CONFIG_INPUT_EVBUG is not set\n\n#\n# Input Device Drivers\n#\nCONFIG_INPUT_KEYBOARD=y\n# CONFIG_KEYBOARD_ADC is not set\nCONFIG_KEYBOARD_ADP5520=y\nCONFIG_KEYBOARD_ADP5588=y\nCONFIG_KEYBOARD_ADP5589=y\nCONFIG_KEYBOARD_ATKBD=y\n# CONFIG_KEYBOARD_QT1050 is not set\n# CONFIG_KEYBOARD_QT1070 is not set\n# CONFIG_KEYBOARD_QT2160 is not set\n# CONFIG_KEYBOARD_DLINK_DIR685 is not set\n# CONFIG_KEYBOARD_LKKBD is not set\nCONFIG_KEYBOARD_GPIO=y\n# CONFIG_KEYBOARD_GPIO_POLLED is not set\n# CONFIG_KEYBOARD_TCA6416 is not set\n# CONFIG_KEYBOARD_TCA8418 is not set\n# CONFIG_KEYBOARD_MATRIX is not set\n# CONFIG_KEYBOARD_LM8323 is not set\n# CONFIG_KEYBOARD_LM8333 is not set\n# CONFIG_KEYBOARD_MAX7359 is not set\n# CONFIG_KEYBOARD_MCS is not set\n# CONFIG_KEYBOARD_MPR121 is not set\n# CONFIG_KEYBOARD_NEWTON is not set\n# CONFIG_KEYBOARD_OPENCORES is not set\n# CONFIG_KEYBOARD_SAMSUNG is not set\n# CONFIG_KEYBOARD_STOWAWAY is not set\n# CONFIG_KEYBOARD_SUNKBD is not set\n# CONFIG_KEYBOARD_OMAP4 is not set\n# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set\n# CONFIG_KEYBOARD_XTKBD is not set\n# CONFIG_KEYBOARD_CAP11XX is not set\n# CONFIG_KEYBOARD_BCM is not set\nCONFIG_INPUT_MOUSE=y\nCONFIG_MOUSE_PS2=y\nCONFIG_MOUSE_PS2_ALPS=y\nCONFIG_MOUSE_PS2_BYD=y\nCONFIG_MOUSE_PS2_LOGIPS2PP=y\nCONFIG_MOUSE_PS2_SYNAPTICS=y\nCONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y\nCONFIG_MOUSE_PS2_CYPRESS=y\nCONFIG_MOUSE_PS2_TRACKPOINT=y\n# CONFIG_MOUSE_PS2_ELANTECH is not set\n# CONFIG_MOUSE_PS2_SENTELIC is not set\n# CONFIG_MOUSE_PS2_TOUCHKIT is not set\nCONFIG_MOUSE_PS2_FOCALTECH=y\nCONFIG_MOUSE_PS2_SMBUS=y\n# CONFIG_MOUSE_SERIAL is not set\n# CONFIG_MOUSE_APPLETOUCH is not set\n# CONFIG_MOUSE_BCM5974 is not set\n# CONFIG_MOUSE_CYAPA is not set\n# CONFIG_MOUSE_ELAN_I2C is not set\n# CONFIG_MOUSE_VSXXXAA is not set\n# CONFIG_MOUSE_GPIO is not set\n# CONFIG_MOUSE_SYNAPTICS_I2C is not set\n# CONFIG_MOUSE_SYNAPTICS_USB is not set\n# CONFIG_INPUT_JOYSTICK is not set\n# CONFIG_INPUT_TABLET is not set\nCONFIG_INPUT_TOUCHSCREEN=y\nCONFIG_TOUCHSCREEN_ADS7846=y\nCONFIG_TOUCHSCREEN_AD7877=y\nCONFIG_TOUCHSCREEN_AD7879=y\nCONFIG_TOUCHSCREEN_AD7879_I2C=y\nCONFIG_TOUCHSCREEN_AD7879_SPI=y\n# CONFIG_TOUCHSCREEN_ADC is not set\n# CONFIG_TOUCHSCREEN_AR1021_I2C is not set\n# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set\n# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set\n# CONFIG_TOUCHSCREEN_BU21013 is not set\n# CONFIG_TOUCHSCREEN_BU21029 is not set\n# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set\n# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set\n# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set\n# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set\n# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set\n# CONFIG_TOUCHSCREEN_DYNAPRO is not set\n# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set\n# CONFIG_TOUCHSCREEN_EETI is not set\n# CONFIG_TOUCHSCREEN_EGALAX is not set\n# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set\n# CONFIG_TOUCHSCREEN_EXC3000 is not set\n# CONFIG_TOUCHSCREEN_FUJITSU is not set\n# CONFIG_TOUCHSCREEN_GOODIX is not set\n# CONFIG_TOUCHSCREEN_HIDEEP is not set\n# CONFIG_TOUCHSCREEN_HYCON_HY46XX is not set\n# CONFIG_TOUCHSCREEN_ILI210X is not set\n# CONFIG_TOUCHSCREEN_ILITEK is not set\n# CONFIG_TOUCHSCREEN_S6SY761 is not set\n# CONFIG_TOUCHSCREEN_GUNZE is not set\n# CONFIG_TOUCHSCREEN_EKTF2127 is not set\n# CONFIG_TOUCHSCREEN_ELAN is not set\n# CONFIG_TOUCHSCREEN_ELO is not set\n# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set\n# CONFIG_TOUCHSCREEN_WACOM_I2C is not set\n# CONFIG_TOUCHSCREEN_MAX11801 is not set\n# CONFIG_TOUCHSCREEN_MCS5000 is not set\n# CONFIG_TOUCHSCREEN_MMS114 is not set\n# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set\n# CONFIG_TOUCHSCREEN_MSG2638 is not set\n# CONFIG_TOUCHSCREEN_MTOUCH is not set\n# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set\n# CONFIG_TOUCHSCREEN_INEXIO is not set\n# CONFIG_TOUCHSCREEN_MK712 is not set\n# CONFIG_TOUCHSCREEN_PENMOUNT is not set\n# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set\n# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set\n# CONFIG_TOUCHSCREEN_TOUCHWIN is not set\n# CONFIG_TOUCHSCREEN_PIXCIR is not set\n# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set\n# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set\n# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set\n# CONFIG_TOUCHSCREEN_TSC_SERIO is not set\n# CONFIG_TOUCHSCREEN_TSC2004 is not set\n# CONFIG_TOUCHSCREEN_TSC2005 is not set\n# CONFIG_TOUCHSCREEN_TSC2007 is not set\n# CONFIG_TOUCHSCREEN_RM_TS is not set\n# CONFIG_TOUCHSCREEN_SILEAD is not set\n# CONFIG_TOUCHSCREEN_SIS_I2C is not set\n# CONFIG_TOUCHSCREEN_ST1232 is not set\n# CONFIG_TOUCHSCREEN_STMFTS is not set\n# CONFIG_TOUCHSCREEN_SUR40 is not set\n# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set\n# CONFIG_TOUCHSCREEN_SX8654 is not set\n# CONFIG_TOUCHSCREEN_TPS6507X is not set\n# CONFIG_TOUCHSCREEN_ZET6223 is not set\n# CONFIG_TOUCHSCREEN_ZFORCE is not set\n# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set\n# CONFIG_TOUCHSCREEN_IQS5XX is not set\n# CONFIG_TOUCHSCREEN_ZINITIX is not set\nCONFIG_INPUT_MISC=y\nCONFIG_INPUT_AD714X=y\nCONFIG_INPUT_AD714X_I2C=y\nCONFIG_INPUT_AD714X_SPI=y\n# CONFIG_INPUT_ATMEL_CAPTOUCH is not set\n# CONFIG_INPUT_BMA150 is not set\n# CONFIG_INPUT_E3X0_BUTTON is not set\n# CONFIG_INPUT_MMA8450 is not set\n# CONFIG_INPUT_GPIO_BEEPER is not set\n# CONFIG_INPUT_GPIO_DECODER is not set\n# CONFIG_INPUT_GPIO_VIBRA is not set\n# CONFIG_INPUT_ATI_REMOTE2 is not set\n# CONFIG_INPUT_KEYSPAN_REMOTE is not set\n# CONFIG_INPUT_KXTJ9 is not set\n# CONFIG_INPUT_POWERMATE is not set\n# CONFIG_INPUT_YEALINK is not set\n# CONFIG_INPUT_CM109 is not set\n# CONFIG_INPUT_REGULATOR_HAPTIC is not set\n# CONFIG_INPUT_UINPUT is not set\nCONFIG_INPUT_PCF8574=y\n# CONFIG_INPUT_PWM_BEEPER is not set\n# CONFIG_INPUT_PWM_VIBRA is not set\nCONFIG_INPUT_GPIO_ROTARY_ENCODER=y\n# CONFIG_INPUT_DA7280_HAPTICS is not set\n# CONFIG_INPUT_ADXL34X is not set\n# CONFIG_INPUT_IMS_PCU is not set\n# CONFIG_INPUT_IQS269A is not set\n# CONFIG_INPUT_IQS626A is not set\n# CONFIG_INPUT_CMA3000 is not set\n# CONFIG_INPUT_DRV260X_HAPTICS is not set\n# CONFIG_INPUT_DRV2665_HAPTICS is not set\n# CONFIG_INPUT_DRV2667_HAPTICS is not set\n# CONFIG_RMI4_CORE is not set\n\n#\n# Hardware I/O ports\n#\nCONFIG_SERIO=y\nCONFIG_SERIO_SERPORT=y\n# CONFIG_SERIO_AMBAKMI is not set\nCONFIG_SERIO_LIBPS2=y\n# CONFIG_SERIO_RAW is not set\n# CONFIG_SERIO_ALTERA_PS2 is not set\n# CONFIG_SERIO_PS2MULT is not set\n# CONFIG_SERIO_ARC_PS2 is not set\n# CONFIG_SERIO_APBPS2 is not set\n# CONFIG_SERIO_GPIO_PS2 is not set\n# CONFIG_USERIO is not set\n# CONFIG_GAMEPORT is not set\n# end of Hardware I/O ports\n# end of Input device support\n\n#\n# Character devices\n#\nCONFIG_TTY=y\nCONFIG_VT=y\nCONFIG_CONSOLE_TRANSLATIONS=y\nCONFIG_VT_CONSOLE=y\nCONFIG_VT_CONSOLE_SLEEP=y\nCONFIG_HW_CONSOLE=y\nCONFIG_VT_HW_CONSOLE_BINDING=y\nCONFIG_UNIX98_PTYS=y\n# CONFIG_LEGACY_PTYS is not set\nCONFIG_LDISC_AUTOLOAD=y\n\n#\n# Serial drivers\n#\nCONFIG_SERIAL_EARLYCON=y\n# CONFIG_SERIAL_8250 is not set\n\n#\n# Non-8250 serial port support\n#\n# CONFIG_SERIAL_AMBA_PL010 is not set\n# CONFIG_SERIAL_AMBA_PL011 is not set\n# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set\n# CONFIG_SERIAL_MAX3100 is not set\n# CONFIG_SERIAL_MAX310X is not set\n# CONFIG_SERIAL_UARTLITE is not set\nCONFIG_SERIAL_CORE=y\nCONFIG_SERIAL_CORE_CONSOLE=y\n# CONFIG_SERIAL_SIFIVE is not set\n# CONFIG_SERIAL_SCCNXP is not set\n# CONFIG_SERIAL_SC16IS7XX is not set\n# CONFIG_SERIAL_BCM63XX is not set\n# CONFIG_SERIAL_ALTERA_JTAGUART is not set\n# CONFIG_SERIAL_ALTERA_UART is not set\nCONFIG_SERIAL_XILINX_PS_UART=y\nCONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y\n# CONFIG_SERIAL_ARC is not set\n# CONFIG_SERIAL_FSL_LPUART is not set\n# CONFIG_SERIAL_FSL_LINFLEXUART is not set\n# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set\n# CONFIG_SERIAL_ST_ASC is not set\n# CONFIG_SERIAL_SPRD is not set\n# end of Serial drivers\n\n# CONFIG_SERIAL_NONSTANDARD is not set\n# CONFIG_N_GSM is not set\n# CONFIG_NULL_TTY is not set\n# CONFIG_HVC_DCC is not set\n# CONFIG_SERIAL_DEV_BUS is not set\n# CONFIG_TTY_PRINTK is not set\n# CONFIG_VIRTIO_CONSOLE is not set\n# CONFIG_IPMI_HANDLER is not set\n# CONFIG_HW_RANDOM is not set\nCONFIG_DEVMEM=y\n# CONFIG_TCG_TPM is not set\n# CONFIG_XILLYBUS is not set\n# CONFIG_XILLYUSB is not set\nCONFIG_AXI_INTR_MONITOR=y\n# CONFIG_RANDOM_TRUST_BOOTLOADER is not set\n# end of Character devices\n\n#\n# I2C support\n#\nCONFIG_I2C=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_COMPAT=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_I2C_MUX=y\n\n#\n# Multiplexer I2C Chip support\n#\n# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set\n# CONFIG_I2C_MUX_GPIO is not set\nCONFIG_I2C_MUX_GPMUX=y\nCONFIG_I2C_MUX_LTC4306=y\n# CONFIG_I2C_MUX_PCA9541 is not set\nCONFIG_I2C_MUX_PCA954x=y\n# CONFIG_I2C_MUX_PINCTRL is not set\n# CONFIG_I2C_MUX_REG is not set\n# CONFIG_I2C_DEMUX_PINCTRL is not set\n# CONFIG_I2C_MUX_MLXCPLD is not set\n# end of Multiplexer I2C Chip support\n\nCONFIG_I2C_HELPER_AUTO=y\nCONFIG_I2C_ALGOBIT=y\n\n#\n# I2C Hardware Bus support\n#\n\n#\n# I2C system bus drivers (mostly embedded / system-on-chip)\n#\nCONFIG_I2C_CADENCE=y\n# CONFIG_I2C_CBUS_GPIO is not set\n# CONFIG_I2C_DESIGNWARE_PLATFORM is not set\n# CONFIG_I2C_EMEV2 is not set\nCONFIG_I2C_GPIO=y\n# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set\n# CONFIG_I2C_NOMADIK is not set\n# CONFIG_I2C_OCORES is not set\n# CONFIG_I2C_PCA_PLATFORM is not set\n# CONFIG_I2C_RK3X is not set\n# CONFIG_I2C_SIMTEC is not set\nCONFIG_I2C_XILINX=y\n\n#\n# External I2C/SMBus adapter drivers\n#\n# CONFIG_I2C_DIOLAN_U2C is not set\n# CONFIG_I2C_CP2615 is not set\n# CONFIG_I2C_ROBOTFUZZ_OSIF is not set\n# CONFIG_I2C_TAOS_EVM is not set\n# CONFIG_I2C_TINY_USB is not set\n\n#\n# Other I2C/SMBus bus drivers\n#\n# CONFIG_I2C_VIRTIO is not set\n# end of I2C Hardware Bus support\n\n# CONFIG_I2C_STUB is not set\n# CONFIG_I2C_SLAVE is not set\n# CONFIG_I2C_DEBUG_CORE is not set\n# CONFIG_I2C_DEBUG_ALGO is not set\n# CONFIG_I2C_DEBUG_BUS is not set\n# end of I2C support\n\n# CONFIG_I3C is not set\nCONFIG_SPI=y\n# CONFIG_SPI_DEBUG is not set\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\n\n#\n# SPI Master Controller Drivers\n#\n# CONFIG_SPI_ALTERA is not set\nCONFIG_SPI_AXI_SPI_ENGINE=y\nCONFIG_SPI_BITBANG=y\nCONFIG_SPI_CADENCE=y\n# CONFIG_SPI_CADENCE_QUADSPI is not set\n# CONFIG_SPI_DESIGNWARE is not set\n# CONFIG_SPI_NXP_FLEXSPI is not set\n# CONFIG_SPI_GPIO is not set\n# CONFIG_SPI_FSL_SPI is not set\n# CONFIG_SPI_OC_TINY is not set\n# CONFIG_SPI_PL022 is not set\n# CONFIG_SPI_ROCKCHIP is not set\n# CONFIG_SPI_SC18IS602 is not set\n# CONFIG_SPI_SIFIVE is not set\n# CONFIG_SPI_MXIC is not set\nCONFIG_SPI_XCOMM=y\nCONFIG_SPI_AD9250FMC=y\nCONFIG_SPI_XILINX=y\nCONFIG_SPI_ZYNQ_QSPI=y\n# CONFIG_SPI_ZYNQ_QSPI_DUAL_STACKED is not set\n# CONFIG_SPI_ZYNQMP_GQSPI is not set\n# CONFIG_SPI_AMD is not set\n\n#\n# SPI Multiplexer support\n#\n# CONFIG_SPI_MUX is not set\n\n#\n# SPI Protocol Masters\n#\nCONFIG_SPI_SPIDEV=y\n# CONFIG_SPI_LOOPBACK_TEST is not set\n# CONFIG_SPI_TLE62X0 is not set\n# CONFIG_SPI_SLAVE is not set\nCONFIG_SPI_DYNAMIC=y\n# CONFIG_SPMI is not set\n# CONFIG_HSI is not set\nCONFIG_PPS=y\n# CONFIG_PPS_DEBUG is not set\n# CONFIG_NTP_PPS is not set\n\n#\n# PPS clients support\n#\n# CONFIG_PPS_CLIENT_KTIMER is not set\n# CONFIG_PPS_CLIENT_LDISC is not set\n# CONFIG_PPS_CLIENT_GPIO is not set\n\n#\n# PPS generators support\n#\n\n#\n# PTP clock support\n#\nCONFIG_PTP_1588_CLOCK=y\nCONFIG_PTP_1588_CLOCK_OPTIONAL=y\n# CONFIG_DP83640_PHY is not set\n# CONFIG_PTP_1588_CLOCK_INES is not set\n# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set\n# CONFIG_PTP_1588_CLOCK_IDTCM is not set\n# CONFIG_PTP_1588_CLOCK_XILINX is not set\n# end of PTP clock support\n\nCONFIG_PINCTRL=y\nCONFIG_PINMUX=y\nCONFIG_PINCONF=y\nCONFIG_GENERIC_PINCONF=y\n# CONFIG_DEBUG_PINCTRL is not set\n# CONFIG_PINCTRL_MCP23S08 is not set\n# CONFIG_PINCTRL_SINGLE is not set\n# CONFIG_PINCTRL_SX150X is not set\n# CONFIG_PINCTRL_STMFX is not set\nCONFIG_PINCTRL_ZYNQ=y\n# CONFIG_PINCTRL_OCELOT is not set\n# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set\n\n#\n# Renesas pinctrl drivers\n#\n# end of Renesas pinctrl drivers\n\nCONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_FASTPATH_LIMIT=512\nCONFIG_OF_GPIO=y\nCONFIG_GPIOLIB_IRQCHIP=y\n# CONFIG_DEBUG_GPIO is not set\nCONFIG_GPIO_SYSFS=y\nCONFIG_GPIO_CDEV=y\nCONFIG_GPIO_CDEV_V1=y\n\n#\n# Memory mapped GPIO drivers\n#\n# CONFIG_GPIO_74XX_MMIO is not set\n# CONFIG_GPIO_ALTERA is not set\n# CONFIG_GPIO_CADENCE is not set\n# CONFIG_GPIO_DWAPB is not set\n# CONFIG_GPIO_FTGPIO010 is not set\n# CONFIG_GPIO_GENERIC_PLATFORM is not set\n# CONFIG_GPIO_GRGPIO is not set\n# CONFIG_GPIO_HLWD is not set\n# CONFIG_GPIO_LOGICVC is not set\n# CONFIG_GPIO_MB86S7X is not set\n# CONFIG_GPIO_MPC8XXX is not set\n# CONFIG_GPIO_PL061 is not set\n# CONFIG_GPIO_SAMA5D2_PIOBU is not set\n# CONFIG_GPIO_SIFIVE is not set\n# CONFIG_GPIO_SYSCON is not set\n# CONFIG_GPIO_XILINX is not set\n# CONFIG_GPIO_ZEVIO is not set\nCONFIG_GPIO_ZYNQ=y\n# CONFIG_GPIO_AMD_FCH is not set\n# end of Memory mapped GPIO drivers\n\n#\n# I2C GPIO expanders\n#\nCONFIG_GPIO_ADP5588=y\nCONFIG_GPIO_ADP5588_IRQ=y\n# CONFIG_GPIO_ADNP is not set\n# CONFIG_GPIO_GW_PLD is not set\n# CONFIG_GPIO_MAX7300 is not set\n# CONFIG_GPIO_MAX732X is not set\nCONFIG_GPIO_PCA953X=y\n# CONFIG_GPIO_PCA953X_IRQ is not set\n# CONFIG_GPIO_PCA9570 is not set\n# CONFIG_GPIO_PCF857X is not set\n# CONFIG_GPIO_SLG7XL45106 is not set\n# CONFIG_GPIO_TPIC2810 is not set\n# end of I2C GPIO expanders\n\n#\n# MFD GPIO expanders\n#\nCONFIG_GPIO_ADP5520=y\n# CONFIG_HTC_EGPIO is not set\n# end of MFD GPIO expanders\n\n#\n# SPI GPIO expanders\n#\n# CONFIG_GPIO_74X164 is not set\nCONFIG_GPIO_ADI_DAQ1=y\n# CONFIG_GPIO_MAX3191X is not set\n# CONFIG_GPIO_MAX7301 is not set\n# CONFIG_GPIO_MC33880 is not set\n# CONFIG_GPIO_PISOSR is not set\n# CONFIG_GPIO_XRA1403 is not set\n# end of SPI GPIO expanders\n\n#\n# USB GPIO expanders\n#\n# end of USB GPIO expanders\n\n#\n# Virtual GPIO drivers\n#\n# CONFIG_GPIO_AGGREGATOR is not set\n# CONFIG_GPIO_MOCKUP is not set\n# end of Virtual GPIO drivers\n\n# CONFIG_W1 is not set\nCONFIG_POWER_RESET=y\n# CONFIG_POWER_RESET_BRCMKONA is not set\n# CONFIG_POWER_RESET_BRCMSTB is not set\nCONFIG_POWER_RESET_GPIO=y\n# CONFIG_POWER_RESET_GPIO_RESTART is not set\nCONFIG_POWER_RESET_LTC2952=y\n# CONFIG_POWER_RESET_REGULATOR is not set\nCONFIG_POWER_RESET_RESTART=y\n# CONFIG_POWER_RESET_VERSATILE is not set\n# CONFIG_POWER_RESET_SYSCON is not set\n# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set\n# CONFIG_SYSCON_REBOOT_MODE is not set\n# CONFIG_NVMEM_REBOOT_MODE is not set\nCONFIG_POWER_SUPPLY=y\n# CONFIG_POWER_SUPPLY_DEBUG is not set\nCONFIG_POWER_SUPPLY_HWMON=y\n# CONFIG_PDA_POWER is not set\n# CONFIG_GENERIC_ADC_BATTERY is not set\n# CONFIG_TEST_POWER is not set\nCONFIG_CHARGER_ADP5061=y\n# CONFIG_BATTERY_CW2015 is not set\n# CONFIG_BATTERY_DS2780 is not set\n# CONFIG_BATTERY_DS2781 is not set\n# CONFIG_BATTERY_DS2782 is not set\n# CONFIG_BATTERY_SBS is not set\n# CONFIG_CHARGER_SBS is not set\n# CONFIG_MANAGER_SBS is not set\n# CONFIG_BATTERY_BQ27XXX is not set\n# CONFIG_BATTERY_MAX17040 is not set\n# CONFIG_BATTERY_MAX17042 is not set\n# CONFIG_CHARGER_ISP1704 is not set\n# CONFIG_CHARGER_MAX8903 is not set\n# CONFIG_CHARGER_LP8727 is not set\n# CONFIG_CHARGER_GPIO is not set\n# CONFIG_CHARGER_MANAGER is not set\nCONFIG_CHARGER_LT3651=y\nCONFIG_CHARGER_LTC4162L=y\n# CONFIG_CHARGER_DETECTOR_MAX14656 is not set\n# CONFIG_CHARGER_BQ2415X is not set\n# CONFIG_CHARGER_BQ24190 is not set\n# CONFIG_CHARGER_BQ24257 is not set\n# CONFIG_CHARGER_BQ24735 is not set\n# CONFIG_CHARGER_BQ2515X is not set\n# CONFIG_CHARGER_BQ25890 is not set\n# CONFIG_CHARGER_BQ25980 is not set\n# CONFIG_CHARGER_BQ256XX is not set\n# CONFIG_CHARGER_SMB347 is not set\nCONFIG_BATTERY_GAUGE_LTC2941=y\n# CONFIG_BATTERY_GOLDFISH is not set\n# CONFIG_BATTERY_RT5033 is not set\n# CONFIG_CHARGER_RT9455 is not set\n# CONFIG_CHARGER_UCS1002 is not set\n# CONFIG_CHARGER_BD99954 is not set\nCONFIG_HWMON=y\nCONFIG_HWMON_VID=y\n# CONFIG_HWMON_DEBUG_CHIP is not set\n\n#\n# Native drivers\n#\nCONFIG_SENSORS_AD7314=y\nCONFIG_SENSORS_AD7414=y\nCONFIG_SENSORS_AD7418=y\nCONFIG_SENSORS_ADM1021=y\nCONFIG_SENSORS_ADM1025=y\nCONFIG_SENSORS_ADM1026=y\nCONFIG_SENSORS_ADM1029=y\nCONFIG_SENSORS_ADM1031=y\nCONFIG_SENSORS_ADM1177=y\nCONFIG_SENSORS_ADM9240=y\nCONFIG_SENSORS_ADT7X10=y\nCONFIG_SENSORS_ADT7310=y\nCONFIG_SENSORS_ADT7410=y\nCONFIG_SENSORS_ADT7411=y\nCONFIG_SENSORS_ADT7462=y\nCONFIG_SENSORS_ADT7470=y\nCONFIG_SENSORS_ADT7475=y\n# CONFIG_SENSORS_AHT10 is not set\n# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set\n# CONFIG_SENSORS_AS370 is not set\n# CONFIG_SENSORS_ASC7621 is not set\nCONFIG_SENSORS_AXI_FAN_CONTROL=y\n# CONFIG_SENSORS_ASPEED is not set\n# CONFIG_SENSORS_ATXP1 is not set\n# CONFIG_SENSORS_CORSAIR_CPRO is not set\n# CONFIG_SENSORS_CORSAIR_PSU is not set\n# CONFIG_SENSORS_DS620 is not set\n# CONFIG_SENSORS_DS1621 is not set\n# CONFIG_SENSORS_F71805F is not set\n# CONFIG_SENSORS_F71882FG is not set\n# CONFIG_SENSORS_F75375S is not set\n# CONFIG_SENSORS_FTSTEUTATES is not set\n# CONFIG_SENSORS_GL518SM is not set\n# CONFIG_SENSORS_GL520SM is not set\n# CONFIG_SENSORS_G760A is not set\n# CONFIG_SENSORS_G762 is not set\n# CONFIG_SENSORS_GPIO_FAN is not set\n# CONFIG_SENSORS_HIH6130 is not set\n# CONFIG_SENSORS_IIO_HWMON is not set\n# CONFIG_SENSORS_IT87 is not set\nCONFIG_SENSORS_JC42=y\n# CONFIG_SENSORS_POWR1220 is not set\n# CONFIG_SENSORS_LINEAGE is not set\nCONFIG_SENSORS_LTC2945=y\nCONFIG_SENSORS_LTC2947=y\nCONFIG_SENSORS_LTC2947_I2C=y\nCONFIG_SENSORS_LTC2947_SPI=y\nCONFIG_SENSORS_LTC2990=y\nCONFIG_SENSORS_LTC2992=y\nCONFIG_SENSORS_LTC4151=y\nCONFIG_SENSORS_LTC4215=y\nCONFIG_SENSORS_LTC4222=y\nCONFIG_SENSORS_LTC4245=y\nCONFIG_SENSORS_LTC4260=y\nCONFIG_SENSORS_LTC4261=y\n# CONFIG_SENSORS_MAX1111 is not set\n# CONFIG_SENSORS_MAX127 is not set\n# CONFIG_SENSORS_MAX16065 is not set\n# CONFIG_SENSORS_MAX1619 is not set\n# CONFIG_SENSORS_MAX1668 is not set\n# CONFIG_SENSORS_MAX197 is not set\n# CONFIG_SENSORS_MAX31722 is not set\n# CONFIG_SENSORS_MAX31730 is not set\n# CONFIG_SENSORS_MAX31760 is not set\nCONFIG_MAX31827=y\n# CONFIG_SENSORS_MAX6620 is not set\n# CONFIG_SENSORS_MAX6621 is not set\n# CONFIG_SENSORS_MAX6639 is not set\n# CONFIG_SENSORS_MAX6642 is not set\n# CONFIG_SENSORS_MAX6650 is not set\n# CONFIG_SENSORS_MAX6697 is not set\n# CONFIG_SENSORS_MAX31790 is not set\n# CONFIG_SENSORS_MCP3021 is not set\n# CONFIG_SENSORS_TC654 is not set\n# CONFIG_SENSORS_TPS23861 is not set\n# CONFIG_SENSORS_MR75203 is not set\n# CONFIG_SENSORS_ADCXX is not set\n# CONFIG_SENSORS_LM63 is not set\n# CONFIG_SENSORS_LM70 is not set\n# CONFIG_SENSORS_LM73 is not set\n# CONFIG_SENSORS_LM75 is not set\n# CONFIG_SENSORS_LM77 is not set\n# CONFIG_SENSORS_LM78 is not set\n# CONFIG_SENSORS_LM80 is not set\n# CONFIG_SENSORS_LM83 is not set\n# CONFIG_SENSORS_LM85 is not set\nCONFIG_SENSORS_LM87=y\nCONFIG_SENSORS_LM90=y\n# CONFIG_SENSORS_LM92 is not set\n# CONFIG_SENSORS_LM93 is not set\n# CONFIG_SENSORS_LM95234 is not set\n# CONFIG_SENSORS_LM95241 is not set\n# CONFIG_SENSORS_LM95245 is not set\n# CONFIG_SENSORS_PC87360 is not set\n# CONFIG_SENSORS_PC87427 is not set\n# CONFIG_SENSORS_NTC_THERMISTOR is not set\n# CONFIG_SENSORS_NCT6683 is not set\n# CONFIG_SENSORS_NCT6775 is not set\n# CONFIG_SENSORS_NCT7802 is not set\n# CONFIG_SENSORS_NCT7904 is not set\n# CONFIG_SENSORS_NPCM7XX is not set\n# CONFIG_SENSORS_NZXT_KRAKEN2 is not set\n# CONFIG_SENSORS_OCC_P8_I2C is not set\n# CONFIG_SENSORS_PCF8591 is not set\nCONFIG_PMBUS=y\nCONFIG_SENSORS_PMBUS=y\nCONFIG_SENSORS_ADM1266=y\nCONFIG_SENSORS_ADM1275=y\n# CONFIG_SENSORS_BEL_PFE is not set\n# CONFIG_SENSORS_BPA_RS600 is not set\n# CONFIG_SENSORS_FSP_3Y is not set\n# CONFIG_SENSORS_IBM_CFFPS is not set\n# CONFIG_SENSORS_DPS920AB is not set\n# CONFIG_SENSORS_INSPUR_IPSPS is not set\n# CONFIG_SENSORS_IR35221 is not set\n# CONFIG_SENSORS_IR36021 is not set\n# CONFIG_SENSORS_IR38064 is not set\n# CONFIG_SENSORS_IRPS5401 is not set\n# CONFIG_SENSORS_ISL68137 is not set\n# CONFIG_SENSORS_LM25066 is not set\nCONFIG_SENSORS_LTC2978=y\nCONFIG_SENSORS_LTC2978_REGULATOR=y\nCONFIG_SENSORS_LTC3815=y\n# CONFIG_SENSORS_MAX15301 is not set\n# CONFIG_SENSORS_MAX16064 is not set\n# CONFIG_SENSORS_MAX16601 is not set\n# CONFIG_SENSORS_MAX20730 is not set\n# CONFIG_SENSORS_MAX20751 is not set\n# CONFIG_SENSORS_MAX31785 is not set\n# CONFIG_SENSORS_MAX34440 is not set\n# CONFIG_SENSORS_MAX8688 is not set\n# CONFIG_SENSORS_MP2888 is not set\n# CONFIG_SENSORS_MP2975 is not set\n# CONFIG_SENSORS_PIM4328 is not set\n# CONFIG_SENSORS_PM6764TR is not set\n# CONFIG_SENSORS_PXE1610 is not set\n# CONFIG_SENSORS_Q54SJ108A2 is not set\n# CONFIG_SENSORS_STPDDC60 is not set\n# CONFIG_SENSORS_TPS40422 is not set\n# CONFIG_SENSORS_TPS53679 is not set\n# CONFIG_SENSORS_TPS544 is not set\nCONFIG_SENSORS_UCD9000=y\nCONFIG_SENSORS_UCD9200=y\n# CONFIG_SENSORS_XDPE122 is not set\n# CONFIG_SENSORS_ZL6100 is not set\n# CONFIG_SENSORS_PWM_FAN is not set\n# CONFIG_SENSORS_SBTSI is not set\n# CONFIG_SENSORS_SBRMI is not set\n# CONFIG_SENSORS_SHT15 is not set\n# CONFIG_SENSORS_SHT21 is not set\n# CONFIG_SENSORS_SHT3x is not set\n# CONFIG_SENSORS_SHT4x is not set\n# CONFIG_SENSORS_SHTC1 is not set\n# CONFIG_SENSORS_DME1737 is not set\n# CONFIG_SENSORS_EMC1403 is not set\n# CONFIG_SENSORS_EMC2103 is not set\n# CONFIG_SENSORS_EMC6W201 is not set\n# CONFIG_SENSORS_SMSC47M1 is not set\n# CONFIG_SENSORS_SMSC47M192 is not set\n# CONFIG_SENSORS_SMSC47B397 is not set\n# CONFIG_SENSORS_SCH5627 is not set\n# CONFIG_SENSORS_SCH5636 is not set\n# CONFIG_SENSORS_STTS751 is not set\n# CONFIG_SENSORS_SMM665 is not set\n# CONFIG_SENSORS_ADC128D818 is not set\n# CONFIG_SENSORS_ADS7828 is not set\n# CONFIG_SENSORS_ADS7871 is not set\n# CONFIG_SENSORS_AMC6821 is not set\n# CONFIG_SENSORS_INA209 is not set\n# CONFIG_SENSORS_INA2XX is not set\n# CONFIG_SENSORS_INA3221 is not set\n# CONFIG_SENSORS_TC74 is not set\n# CONFIG_SENSORS_THMC50 is not set\n# CONFIG_SENSORS_TMP102 is not set\n# CONFIG_SENSORS_TMP103 is not set\n# CONFIG_SENSORS_TMP108 is not set\n# CONFIG_SENSORS_TMP401 is not set\n# CONFIG_SENSORS_TMP421 is not set\n# CONFIG_SENSORS_TMP513 is not set\n# CONFIG_SENSORS_VT1211 is not set\n# CONFIG_SENSORS_W83773G is not set\n# CONFIG_SENSORS_W83781D is not set\n# CONFIG_SENSORS_W83791D is not set\n# CONFIG_SENSORS_W83792D is not set\n# CONFIG_SENSORS_W83793 is not set\n# CONFIG_SENSORS_W83795 is not set\n# CONFIG_SENSORS_W83L785TS is not set\n# CONFIG_SENSORS_W83L786NG is not set\n# CONFIG_SENSORS_W83627HF is not set\n# CONFIG_SENSORS_W83627EHF is not set\nCONFIG_THERMAL=y\n# CONFIG_THERMAL_NETLINK is not set\n# CONFIG_THERMAL_STATISTICS is not set\nCONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0\nCONFIG_THERMAL_HWMON=y\nCONFIG_THERMAL_OF=y\n# CONFIG_THERMAL_WRITABLE_TRIPS is not set\nCONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y\n# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set\n# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set\n# CONFIG_THERMAL_GOV_FAIR_SHARE is not set\nCONFIG_THERMAL_GOV_STEP_WISE=y\n# CONFIG_THERMAL_GOV_BANG_BANG is not set\n# CONFIG_THERMAL_GOV_USER_SPACE is not set\n# CONFIG_CPU_THERMAL is not set\n# CONFIG_THERMAL_EMULATION is not set\n# CONFIG_THERMAL_MMIO is not set\n# CONFIG_GENERIC_ADC_THERMAL is not set\nCONFIG_WATCHDOG=y\nCONFIG_WATCHDOG_CORE=y\n# CONFIG_WATCHDOG_NOWAYOUT is not set\nCONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y\nCONFIG_WATCHDOG_OPEN_TIMEOUT=0\n# CONFIG_WATCHDOG_SYSFS is not set\n# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set\n\n#\n# Watchdog Pretimeout Governors\n#\n# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set\n\n#\n# Watchdog Device Drivers\n#\n# CONFIG_SOFT_WATCHDOG is not set\n# CONFIG_GPIO_WATCHDOG is not set\nCONFIG_XILINX_WATCHDOG=y\n# CONFIG_ZIIRAVE_WATCHDOG is not set\n# CONFIG_ARM_SP805_WATCHDOG is not set\nCONFIG_CADENCE_WATCHDOG=y\n# CONFIG_FTWDT010_WATCHDOG is not set\n# CONFIG_DW_WATCHDOG is not set\n# CONFIG_MAX63XX_WATCHDOG is not set\n# CONFIG_ARM_SMC_WATCHDOG is not set\n# CONFIG_MEN_A21_WDT is not set\n\n#\n# USB-based Watchdog Cards\n#\n# CONFIG_USBPCWATCHDOG is not set\nCONFIG_SSB_POSSIBLE=y\n# CONFIG_SSB is not set\nCONFIG_BCMA_POSSIBLE=y\n# CONFIG_BCMA is not set\n\n#\n# Multifunction device drivers\n#\n# CONFIG_MFD_ACT8945A is not set\n# CONFIG_MFD_AS3711 is not set\n# CONFIG_MFD_AS3722 is not set\nCONFIG_PMIC_ADP5520=y\n# CONFIG_MFD_AAT2870_CORE is not set\n# CONFIG_MFD_ATMEL_FLEXCOM is not set\n# CONFIG_MFD_ATMEL_HLCDC is not set\n# CONFIG_MFD_BCM590XX is not set\n# CONFIG_MFD_BD9571MWV is not set\n# CONFIG_MFD_AXP20X_I2C is not set\n# CONFIG_MFD_MADERA is not set\n# CONFIG_MFD_ASIC3 is not set\n# CONFIG_PMIC_DA903X is not set\n# CONFIG_MFD_DA9052_SPI is not set\n# CONFIG_MFD_DA9052_I2C is not set\n# CONFIG_MFD_DA9055 is not set\n# CONFIG_MFD_DA9062 is not set\n# CONFIG_MFD_DA9063 is not set\n# CONFIG_MFD_DA9150 is not set\n# CONFIG_MFD_DLN2 is not set\n# CONFIG_MFD_GATEWORKS_GSC is not set\n# CONFIG_MFD_MC13XXX_SPI is not set\n# CONFIG_MFD_MC13XXX_I2C is not set\n# CONFIG_MFD_MP2629 is not set\n# CONFIG_MFD_HI6421_PMIC is not set\n# CONFIG_HTC_PASIC3 is not set\n# CONFIG_HTC_I2CPLD is not set\n# CONFIG_MFD_IQS62X is not set\n# CONFIG_MFD_KEMPLD is not set\n# CONFIG_MFD_88PM800 is not set\n# CONFIG_MFD_88PM805 is not set\n# CONFIG_MFD_88PM860X is not set\n# CONFIG_MFD_MAX14577 is not set\n# CONFIG_MFD_MAX77620 is not set\n# CONFIG_MFD_MAX77650 is not set\n# CONFIG_MFD_MAX77686 is not set\n# CONFIG_MFD_MAX77693 is not set\n# CONFIG_MFD_MAX77843 is not set\n# CONFIG_MFD_MAX8907 is not set\n# CONFIG_MFD_MAX8925 is not set\n# CONFIG_MFD_MAX8997 is not set\n# CONFIG_MFD_MAX8998 is not set\n# CONFIG_MFD_MT6360 is not set\n# CONFIG_MFD_MT6397 is not set\n# CONFIG_MFD_MENF21BMC is not set\n# CONFIG_EZX_PCAP is not set\n# CONFIG_MFD_CPCAP is not set\n# CONFIG_MFD_VIPERBOARD is not set\n# CONFIG_MFD_NTXEC is not set\n# CONFIG_MFD_RETU is not set\n# CONFIG_MFD_PCF50633 is not set\n# CONFIG_MFD_PM8XXX is not set\n# CONFIG_MFD_RT4831 is not set\n# CONFIG_MFD_RT5033 is not set\n# CONFIG_MFD_RC5T583 is not set\n# CONFIG_MFD_RK808 is not set\n# CONFIG_MFD_RN5T618 is not set\n# CONFIG_MFD_SEC_CORE is not set\n# CONFIG_MFD_SI476X_CORE is not set\n# CONFIG_MFD_SM501 is not set\n# CONFIG_MFD_SKY81452 is not set\n# CONFIG_MFD_STMPE is not set\nCONFIG_MFD_SYSCON=y\n# CONFIG_MFD_TI_AM335X_TSCADC is not set\n# CONFIG_MFD_LP3943 is not set\n# CONFIG_MFD_LP8788 is not set\n# CONFIG_MFD_TI_LMU is not set\n# CONFIG_MFD_PALMAS is not set\n# CONFIG_TPS6105X is not set\n# CONFIG_TPS65010 is not set\n# CONFIG_TPS6507X is not set\n# CONFIG_MFD_TPS65086 is not set\n# CONFIG_MFD_TPS65090 is not set\n# CONFIG_MFD_TPS65217 is not set\n# CONFIG_MFD_TI_LP873X is not set\n# CONFIG_MFD_TI_LP87565 is not set\n# CONFIG_MFD_TPS65218 is not set\n# CONFIG_MFD_TPS6586X is not set\n# CONFIG_MFD_TPS65910 is not set\n# CONFIG_MFD_TPS65912_I2C is not set\n# CONFIG_MFD_TPS65912_SPI is not set\n# CONFIG_MFD_TPS80031 is not set\n# CONFIG_TWL4030_CORE is not set\n# CONFIG_TWL6040_CORE is not set\n# CONFIG_MFD_WL1273_CORE is not set\n# CONFIG_MFD_LM3533 is not set\n# CONFIG_MFD_TC3589X is not set\n# CONFIG_MFD_T7L66XB is not set\n# CONFIG_MFD_TC6387XB is not set\n# CONFIG_MFD_TC6393XB is not set\n# CONFIG_MFD_TQMX86 is not set\n# CONFIG_MFD_LOCHNAGAR is not set\n# CONFIG_MFD_ARIZONA_I2C is not set\n# CONFIG_MFD_ARIZONA_SPI is not set\n# CONFIG_MFD_WM8400 is not set\n# CONFIG_MFD_WM831X_I2C is not set\n# CONFIG_MFD_WM831X_SPI is not set\n# CONFIG_MFD_WM8350_I2C is not set\n# CONFIG_MFD_WM8994 is not set\n# CONFIG_MFD_ROHM_BD718XX is not set\n# CONFIG_MFD_ROHM_BD70528 is not set\n# CONFIG_MFD_ROHM_BD71828 is not set\n# CONFIG_MFD_ROHM_BD957XMUF is not set\n# CONFIG_MFD_STPMIC1 is not set\n# CONFIG_MFD_STMFX is not set\n# CONFIG_MFD_ATC260X_I2C is not set\n# CONFIG_MFD_QCOM_PM8008 is not set\n# CONFIG_MFD_INTEL_M10_BMC is not set\n# CONFIG_MFD_RSMU_I2C is not set\n# CONFIG_MFD_RSMU_SPI is not set\n# end of Multifunction device drivers\n\nCONFIG_REGULATOR=y\n# CONFIG_REGULATOR_DEBUG is not set\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\n# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set\n# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set\n# CONFIG_REGULATOR_88PG86X is not set\n# CONFIG_REGULATOR_ACT8865 is not set\nCONFIG_REGULATOR_AD5398=y\n# CONFIG_REGULATOR_DA9121 is not set\n# CONFIG_REGULATOR_DA9210 is not set\n# CONFIG_REGULATOR_DA9211 is not set\n# CONFIG_REGULATOR_FAN53555 is not set\n# CONFIG_REGULATOR_FAN53880 is not set\n# CONFIG_REGULATOR_GPIO is not set\n# CONFIG_REGULATOR_ISL9305 is not set\n# CONFIG_REGULATOR_ISL6271A is not set\n# CONFIG_REGULATOR_LP3971 is not set\n# CONFIG_REGULATOR_LP3972 is not set\n# CONFIG_REGULATOR_LP872X is not set\n# CONFIG_REGULATOR_LP8755 is not set\nCONFIG_REGULATOR_LTC3589=y\nCONFIG_REGULATOR_LTC3676=y\n# CONFIG_REGULATOR_MAX1586 is not set\n# CONFIG_REGULATOR_MAX8649 is not set\n# CONFIG_REGULATOR_MAX8660 is not set\n# CONFIG_REGULATOR_MAX8893 is not set\n# CONFIG_REGULATOR_MAX8952 is not set\n# CONFIG_REGULATOR_MAX8973 is not set\n# CONFIG_REGULATOR_MAX77826 is not set\n# CONFIG_REGULATOR_MCP16502 is not set\n# CONFIG_REGULATOR_MP5416 is not set\n# CONFIG_REGULATOR_MP8859 is not set\n# CONFIG_REGULATOR_MP886X is not set\n# CONFIG_REGULATOR_MPQ7920 is not set\n# CONFIG_REGULATOR_MT6311 is not set\n# CONFIG_REGULATOR_PCA9450 is not set\n# CONFIG_REGULATOR_PF8X00 is not set\n# CONFIG_REGULATOR_PFUZE100 is not set\n# CONFIG_REGULATOR_PV88060 is not set\n# CONFIG_REGULATOR_PV88080 is not set\n# CONFIG_REGULATOR_PV88090 is not set\n# CONFIG_REGULATOR_PWM is not set\n# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set\n# CONFIG_REGULATOR_RT4801 is not set\n# CONFIG_REGULATOR_RT6160 is not set\n# CONFIG_REGULATOR_RT6245 is not set\n# CONFIG_REGULATOR_RTQ2134 is not set\n# CONFIG_REGULATOR_RTMV20 is not set\n# CONFIG_REGULATOR_RTQ6752 is not set\n# CONFIG_REGULATOR_SLG51000 is not set\n# CONFIG_REGULATOR_SY8106A is not set\n# CONFIG_REGULATOR_SY8824X is not set\n# CONFIG_REGULATOR_SY8827N is not set\n# CONFIG_REGULATOR_TPS51632 is not set\n# CONFIG_REGULATOR_TPS62360 is not set\n# CONFIG_REGULATOR_TPS65023 is not set\n# CONFIG_REGULATOR_TPS6507X is not set\n# CONFIG_REGULATOR_TPS65132 is not set\n# CONFIG_REGULATOR_TPS6524X is not set\n# CONFIG_REGULATOR_VCTRL is not set\n# CONFIG_RC_CORE is not set\nCONFIG_CEC_CORE=y\nCONFIG_MEDIA_CEC_SUPPORT=y\n# CONFIG_CEC_CH7322 is not set\n# CONFIG_CEC_GPIO is not set\n# CONFIG_USB_PULSE8_CEC is not set\n# CONFIG_USB_RAINSHADOW_CEC is not set\nCONFIG_MEDIA_SUPPORT=y\n# CONFIG_MEDIA_SUPPORT_FILTER is not set\n# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set\n\n#\n# Media device types\n#\nCONFIG_MEDIA_CAMERA_SUPPORT=y\nCONFIG_MEDIA_ANALOG_TV_SUPPORT=y\nCONFIG_MEDIA_DIGITAL_TV_SUPPORT=y\nCONFIG_MEDIA_RADIO_SUPPORT=y\nCONFIG_MEDIA_SDR_SUPPORT=y\nCONFIG_MEDIA_PLATFORM_SUPPORT=y\nCONFIG_MEDIA_TEST_SUPPORT=y\n# end of Media device types\n\n#\n# Media core support\n#\nCONFIG_VIDEO_DEV=y\nCONFIG_MEDIA_CONTROLLER=y\nCONFIG_DVB_CORE=y\n# end of Media core support\n\n#\n# Video4Linux options\n#\nCONFIG_VIDEO_V4L2=y\nCONFIG_VIDEO_V4L2_I2C=y\nCONFIG_VIDEO_V4L2_SUBDEV_API=y\nCONFIG_VIDEO_ADV_DEBUG=y\n# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set\n# CONFIG_V4L2_FLASH_LED_CLASS is not set\nCONFIG_V4L2_FWNODE=y\nCONFIG_V4L2_ASYNC=y\n# end of Video4Linux options\n\n#\n# Media controller options\n#\n# CONFIG_MEDIA_CONTROLLER_DVB is not set\n# end of Media controller options\n\n#\n# Digital TV options\n#\n# CONFIG_DVB_MMAP is not set\nCONFIG_DVB_NET=y\nCONFIG_DVB_MAX_ADAPTERS=16\nCONFIG_DVB_DYNAMIC_MINORS=y\n# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set\n# CONFIG_DVB_ULE_DEBUG is not set\n# end of Digital TV options\n\n#\n# Media drivers\n#\nCONFIG_MEDIA_USB_SUPPORT=y\n\n#\n# Webcam devices\n#\nCONFIG_USB_VIDEO_CLASS=y\nCONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y\nCONFIG_USB_GSPCA=y\n# CONFIG_USB_M5602 is not set\n# CONFIG_USB_STV06XX is not set\n# CONFIG_USB_GL860 is not set\n# CONFIG_USB_GSPCA_BENQ is not set\n# CONFIG_USB_GSPCA_CONEX is not set\n# CONFIG_USB_GSPCA_CPIA1 is not set\n# CONFIG_USB_GSPCA_DTCS033 is not set\n# CONFIG_USB_GSPCA_ETOMS is not set\n# CONFIG_USB_GSPCA_FINEPIX is not set\n# CONFIG_USB_GSPCA_JEILINJ is not set\n# CONFIG_USB_GSPCA_JL2005BCD is not set\n# CONFIG_USB_GSPCA_KINECT is not set\n# CONFIG_USB_GSPCA_KONICA is not set\n# CONFIG_USB_GSPCA_MARS is not set\n# CONFIG_USB_GSPCA_MR97310A is not set\n# CONFIG_USB_GSPCA_NW80X is not set\n# CONFIG_USB_GSPCA_OV519 is not set\n# CONFIG_USB_GSPCA_OV534 is not set\n# CONFIG_USB_GSPCA_OV534_9 is not set\n# CONFIG_USB_GSPCA_PAC207 is not set\n# CONFIG_USB_GSPCA_PAC7302 is not set\n# CONFIG_USB_GSPCA_PAC7311 is not set\n# CONFIG_USB_GSPCA_SE401 is not set\n# CONFIG_USB_GSPCA_SN9C2028 is not set\n# CONFIG_USB_GSPCA_SN9C20X is not set\n# CONFIG_USB_GSPCA_SONIXB is not set\n# CONFIG_USB_GSPCA_SONIXJ is not set\n# CONFIG_USB_GSPCA_SPCA500 is not set\n# CONFIG_USB_GSPCA_SPCA501 is not set\n# CONFIG_USB_GSPCA_SPCA505 is not set\n# CONFIG_USB_GSPCA_SPCA506 is not set\n# CONFIG_USB_GSPCA_SPCA508 is not set\n# CONFIG_USB_GSPCA_SPCA561 is not set\n# CONFIG_USB_GSPCA_SPCA1528 is not set\n# CONFIG_USB_GSPCA_SQ905 is not set\n# CONFIG_USB_GSPCA_SQ905C is not set\n# CONFIG_USB_GSPCA_SQ930X is not set\n# CONFIG_USB_GSPCA_STK014 is not set\n# CONFIG_USB_GSPCA_STK1135 is not set\n# CONFIG_USB_GSPCA_STV0680 is not set\n# CONFIG_USB_GSPCA_SUNPLUS is not set\n# CONFIG_USB_GSPCA_T613 is not set\n# CONFIG_USB_GSPCA_TOPRO is not set\n# CONFIG_USB_GSPCA_TOUPTEK is not set\n# CONFIG_USB_GSPCA_TV8532 is not set\n# CONFIG_USB_GSPCA_VC032X is not set\n# CONFIG_USB_GSPCA_VICAM is not set\n# CONFIG_USB_GSPCA_XIRLINK_CIT is not set\n# CONFIG_USB_GSPCA_ZC3XX is not set\n# CONFIG_USB_PWC is not set\n# CONFIG_VIDEO_CPIA2 is not set\n# CONFIG_USB_ZR364XX is not set\n# CONFIG_USB_STKWEBCAM is not set\n# CONFIG_USB_S2255 is not set\n# CONFIG_VIDEO_USBTV is not set\n\n#\n# Analog TV USB devices\n#\n# CONFIG_VIDEO_PVRUSB2 is not set\n# CONFIG_VIDEO_HDPVR is not set\n# CONFIG_VIDEO_STK1160_COMMON is not set\n# CONFIG_VIDEO_GO7007 is not set\n\n#\n# Analog/digital TV USB devices\n#\n# CONFIG_VIDEO_AU0828 is not set\n# CONFIG_VIDEO_CX231XX is not set\n\n#\n# Digital TV USB devices\n#\n# CONFIG_DVB_USB_V2 is not set\n# CONFIG_SMS_USB_DRV is not set\n# CONFIG_DVB_B2C2_FLEXCOP_USB is not set\n# CONFIG_DVB_AS102 is not set\n\n#\n# Webcam, TV (analog/digital) USB devices\n#\n# CONFIG_VIDEO_EM28XX is not set\n\n#\n# Software defined radio USB devices\n#\n# CONFIG_USB_AIRSPY is not set\n# CONFIG_USB_HACKRF is not set\n# CONFIG_USB_MSI2500 is not set\nCONFIG_RADIO_ADAPTERS=y\n# CONFIG_RADIO_SI470X is not set\n# CONFIG_RADIO_SI4713 is not set\n# CONFIG_USB_MR800 is not set\n# CONFIG_USB_DSBR is not set\n# CONFIG_RADIO_SHARK is not set\n# CONFIG_RADIO_SHARK2 is not set\n# CONFIG_USB_KEENE is not set\n# CONFIG_USB_RAREMONO is not set\n# CONFIG_USB_MA901 is not set\n# CONFIG_RADIO_TEA5764 is not set\n# CONFIG_RADIO_SAA7706H is not set\n# CONFIG_RADIO_TEF6862 is not set\n# CONFIG_RADIO_WL1273 is not set\nCONFIG_VIDEOBUF2_CORE=y\nCONFIG_VIDEOBUF2_V4L2=y\nCONFIG_VIDEOBUF2_MEMOPS=y\nCONFIG_VIDEOBUF2_DMA_CONTIG=y\nCONFIG_VIDEOBUF2_VMALLOC=y\nCONFIG_V4L_PLATFORM_DRIVERS=y\n# CONFIG_VIDEO_CADENCE is not set\n# CONFIG_VIDEO_ASPEED is not set\n# CONFIG_VIDEO_MUX is not set\nCONFIG_VIDEO_AXI_HDMI_RX=y\n# CONFIG_VIDEO_IMAGEON_BRIDGE is not set\n# CONFIG_VIDEO_XILINX is not set\n# CONFIG_V4L_MEM2MEM_DRIVERS is not set\nCONFIG_ADI_AXI_VIDEO_FRAME_BUFFER=y\n# CONFIG_DVB_PLATFORM_DRIVERS is not set\n# CONFIG_SDR_PLATFORM_DRIVERS is not set\n\n#\n# MMC/SDIO DVB adapters\n#\n# CONFIG_SMS_SDIO_DRV is not set\n# CONFIG_V4L_TEST_DRIVERS is not set\n# CONFIG_DVB_TEST_DRIVERS is not set\n# end of Media drivers\n\n#\n# Media ancillary drivers\n#\nCONFIG_MEDIA_ATTACH=y\n\n#\n# Audio decoders, processors and mixers\n#\n# CONFIG_VIDEO_TVAUDIO is not set\n# CONFIG_VIDEO_TDA7432 is not set\n# CONFIG_VIDEO_TDA9840 is not set\n# CONFIG_VIDEO_TDA1997X is not set\n# CONFIG_VIDEO_TEA6415C is not set\n# CONFIG_VIDEO_TEA6420 is not set\n# CONFIG_VIDEO_MSP3400 is not set\n# CONFIG_VIDEO_CS3308 is not set\n# CONFIG_VIDEO_CS5345 is not set\n# CONFIG_VIDEO_CS53L32A is not set\n# CONFIG_VIDEO_TLV320AIC23B is not set\n# CONFIG_VIDEO_UDA1342 is not set\n# CONFIG_VIDEO_WM8775 is not set\n# CONFIG_VIDEO_WM8739 is not set\n# CONFIG_VIDEO_VP27SMPX is not set\n# CONFIG_VIDEO_SONY_BTF_MPX is not set\n# end of Audio decoders, processors and mixers\n\n#\n# RDS decoders\n#\n# CONFIG_VIDEO_SAA6588 is not set\n# end of RDS decoders\n\n#\n# Video decoders\n#\nCONFIG_VIDEO_ADV7180=y\nCONFIG_VIDEO_ADV7183=y\nCONFIG_VIDEO_ADV748X=y\nCONFIG_VIDEO_ADV7604=y\nCONFIG_VIDEO_ADV7604_CEC=y\nCONFIG_VIDEO_ADV7842=y\nCONFIG_VIDEO_ADV7842_CEC=y\n# CONFIG_VIDEO_BT819 is not set\n# CONFIG_VIDEO_BT856 is not set\n# CONFIG_VIDEO_BT866 is not set\n# CONFIG_VIDEO_KS0127 is not set\n# CONFIG_VIDEO_ML86V7667 is not set\n# CONFIG_VIDEO_SAA7110 is not set\n# CONFIG_VIDEO_SAA711X is not set\n# CONFIG_VIDEO_TC358743 is not set\n# CONFIG_VIDEO_TVP514X is not set\n# CONFIG_VIDEO_TVP5150 is not set\n# CONFIG_VIDEO_TVP7002 is not set\n# CONFIG_VIDEO_TW2804 is not set\n# CONFIG_VIDEO_TW9903 is not set\n# CONFIG_VIDEO_TW9906 is not set\n# CONFIG_VIDEO_TW9910 is not set\n# CONFIG_VIDEO_VPX3220 is not set\n# CONFIG_VIDEO_MAX9286 is not set\n\n#\n# Video and audio decoders\n#\n# CONFIG_VIDEO_SAA717X is not set\n# CONFIG_VIDEO_CX25840 is not set\n# end of Video decoders\n\n#\n# Video encoders\n#\n# CONFIG_VIDEO_SAA7127 is not set\n# CONFIG_VIDEO_SAA7185 is not set\nCONFIG_VIDEO_ADV7170=y\nCONFIG_VIDEO_ADV7175=y\nCONFIG_VIDEO_ADV7343=y\nCONFIG_VIDEO_ADV7393=y\nCONFIG_VIDEO_AD9389B=y\n# CONFIG_VIDEO_AK881X is not set\n# CONFIG_VIDEO_THS8200 is not set\n# end of Video encoders\n\n#\n# Video improvement chips\n#\n# CONFIG_VIDEO_UPD64031A is not set\n# CONFIG_VIDEO_UPD64083 is not set\n# end of Video improvement chips\n\n# CONFIG_VIDEO_AP1302 is not set\n\n#\n# Audio/Video compression chips\n#\n# CONFIG_VIDEO_SAA6752HS is not set\n# end of Audio/Video compression chips\n\n#\n# SDR tuner chips\n#\n# CONFIG_SDR_MAX2175 is not set\n# end of SDR tuner chips\n\n#\n# Miscellaneous helper chips\n#\n# CONFIG_VIDEO_THS7303 is not set\n# CONFIG_VIDEO_M52790 is not set\n# CONFIG_VIDEO_I2C is not set\n# CONFIG_VIDEO_ST_MIPID02 is not set\n# end of Miscellaneous helper chips\n\n#\n# Camera sensor devices\n#\nCONFIG_VIDEO_ADDI9036=y\n# CONFIG_VIDEO_HI556 is not set\n# CONFIG_VIDEO_IMX208 is not set\n# CONFIG_VIDEO_IMX214 is not set\n# CONFIG_VIDEO_IMX219 is not set\n# CONFIG_VIDEO_IMX258 is not set\n# CONFIG_VIDEO_IMX274 is not set\n# CONFIG_VIDEO_IMX290 is not set\n# CONFIG_VIDEO_IMX319 is not set\n# CONFIG_VIDEO_IMX334 is not set\n# CONFIG_VIDEO_IMX335 is not set\n# CONFIG_VIDEO_IMX355 is not set\n# CONFIG_VIDEO_IMX412 is not set\n# CONFIG_VIDEO_OV02A10 is not set\n# CONFIG_VIDEO_OV2640 is not set\n# CONFIG_VIDEO_OV2659 is not set\n# CONFIG_VIDEO_OV2680 is not set\n# CONFIG_VIDEO_OV2685 is not set\n# CONFIG_VIDEO_OV5640 is not set\n# CONFIG_VIDEO_OV5645 is not set\n# CONFIG_VIDEO_OV5647 is not set\n# CONFIG_VIDEO_OV5648 is not set\n# CONFIG_VIDEO_OV6650 is not set\n# CONFIG_VIDEO_OV5670 is not set\n# CONFIG_VIDEO_OV5675 is not set\n# CONFIG_VIDEO_OV5695 is not set\n# CONFIG_VIDEO_OV7251 is not set\n# CONFIG_VIDEO_OV772X is not set\n# CONFIG_VIDEO_OV7640 is not set\n# CONFIG_VIDEO_OV7670 is not set\n# CONFIG_VIDEO_OV7740 is not set\n# CONFIG_VIDEO_OV8856 is not set\n# CONFIG_VIDEO_OV8865 is not set\n# CONFIG_VIDEO_OV9282 is not set\n# CONFIG_VIDEO_OV9640 is not set\n# CONFIG_VIDEO_OV9650 is not set\n# CONFIG_VIDEO_OV13858 is not set\n# CONFIG_VIDEO_VS6624 is not set\n# CONFIG_VIDEO_MT9M001 is not set\n# CONFIG_VIDEO_MT9M032 is not set\n# CONFIG_VIDEO_MT9M111 is not set\n# CONFIG_VIDEO_MT9P031 is not set\n# CONFIG_VIDEO_MT9T001 is not set\n# CONFIG_VIDEO_MT9T112 is not set\n# CONFIG_VIDEO_MT9V011 is not set\n# CONFIG_VIDEO_MT9V032 is not set\n# CONFIG_VIDEO_MT9V111 is not set\n# CONFIG_VIDEO_SR030PC30 is not set\n# CONFIG_VIDEO_NOON010PC30 is not set\n# CONFIG_VIDEO_M5MOLS is not set\n# CONFIG_VIDEO_RDACM20 is not set\n# CONFIG_VIDEO_RDACM21 is not set\n# CONFIG_VIDEO_RJ54N1 is not set\n# CONFIG_VIDEO_S5K6AA is not set\n# CONFIG_VIDEO_S5K6A3 is not set\n# CONFIG_VIDEO_S5K4ECGX is not set\n# CONFIG_VIDEO_S5K5BAF is not set\n# CONFIG_VIDEO_CCS is not set\n# CONFIG_VIDEO_ET8EK8 is not set\n# CONFIG_VIDEO_S5C73M3 is not set\n# end of Camera sensor devices\n\n#\n# Lens drivers\n#\n# CONFIG_VIDEO_AD5820 is not set\n# CONFIG_VIDEO_AK7375 is not set\n# CONFIG_VIDEO_DW9714 is not set\n# CONFIG_VIDEO_DW9768 is not set\n# CONFIG_VIDEO_DW9807_VCM is not set\n# end of Lens drivers\n\n#\n# Flash devices\n#\nCONFIG_VIDEO_ADP1653=y\n# CONFIG_VIDEO_LM3560 is not set\n# CONFIG_VIDEO_LM3646 is not set\n# end of Flash devices\n\n#\n# SPI helper chips\n#\n# CONFIG_VIDEO_GS1662 is not set\n# end of SPI helper chips\n\n#\n# Media SPI Adapters\n#\nCONFIG_CXD2880_SPI_DRV=m\n# end of Media SPI Adapters\n\nCONFIG_MEDIA_TUNER=y\n\n#\n# Customize TV tuners\n#\nCONFIG_MEDIA_TUNER_SIMPLE=m\nCONFIG_MEDIA_TUNER_TDA18250=m\nCONFIG_MEDIA_TUNER_TDA8290=m\nCONFIG_MEDIA_TUNER_TDA827X=m\nCONFIG_MEDIA_TUNER_TDA18271=m\nCONFIG_MEDIA_TUNER_TDA9887=m\nCONFIG_MEDIA_TUNER_TEA5761=m\nCONFIG_MEDIA_TUNER_TEA5767=m\nCONFIG_MEDIA_TUNER_MSI001=m\nCONFIG_MEDIA_TUNER_MT20XX=m\nCONFIG_MEDIA_TUNER_MT2060=m\nCONFIG_MEDIA_TUNER_MT2063=m\nCONFIG_MEDIA_TUNER_MT2266=m\nCONFIG_MEDIA_TUNER_MT2131=m\nCONFIG_MEDIA_TUNER_QT1010=m\nCONFIG_MEDIA_TUNER_XC2028=m\nCONFIG_MEDIA_TUNER_XC5000=m\nCONFIG_MEDIA_TUNER_XC4000=m\nCONFIG_MEDIA_TUNER_MXL5005S=m\nCONFIG_MEDIA_TUNER_MXL5007T=m\nCONFIG_MEDIA_TUNER_MC44S803=m\nCONFIG_MEDIA_TUNER_MAX2165=m\nCONFIG_MEDIA_TUNER_TDA18218=m\nCONFIG_MEDIA_TUNER_FC0011=m\nCONFIG_MEDIA_TUNER_FC0012=m\nCONFIG_MEDIA_TUNER_FC0013=m\nCONFIG_MEDIA_TUNER_TDA18212=m\nCONFIG_MEDIA_TUNER_E4000=m\nCONFIG_MEDIA_TUNER_FC2580=m\nCONFIG_MEDIA_TUNER_M88RS6000T=m\nCONFIG_MEDIA_TUNER_TUA9001=m\nCONFIG_MEDIA_TUNER_SI2157=m\nCONFIG_MEDIA_TUNER_IT913X=m\nCONFIG_MEDIA_TUNER_R820T=m\nCONFIG_MEDIA_TUNER_MXL301RF=m\nCONFIG_MEDIA_TUNER_QM1D1C0042=m\nCONFIG_MEDIA_TUNER_QM1D1B0004=m\n# end of Customize TV tuners\n\n#\n# Customise DVB Frontends\n#\n\n#\n# Multistandard (satellite) frontends\n#\nCONFIG_DVB_STB0899=m\nCONFIG_DVB_STB6100=m\nCONFIG_DVB_STV090x=m\nCONFIG_DVB_STV0910=m\nCONFIG_DVB_STV6110x=m\nCONFIG_DVB_STV6111=m\nCONFIG_DVB_MXL5XX=m\nCONFIG_DVB_M88DS3103=m\n\n#\n# Multistandard (cable + terrestrial) frontends\n#\nCONFIG_DVB_DRXK=m\nCONFIG_DVB_TDA18271C2DD=m\nCONFIG_DVB_SI2165=m\nCONFIG_DVB_MN88472=m\nCONFIG_DVB_MN88473=m\n\n#\n# DVB-S (satellite) frontends\n#\nCONFIG_DVB_CX24110=m\nCONFIG_DVB_CX24123=m\nCONFIG_DVB_MT312=m\nCONFIG_DVB_ZL10036=m\nCONFIG_DVB_ZL10039=m\nCONFIG_DVB_S5H1420=m\nCONFIG_DVB_STV0288=m\nCONFIG_DVB_STB6000=m\nCONFIG_DVB_STV0299=m\nCONFIG_DVB_STV6110=m\nCONFIG_DVB_STV0900=m\nCONFIG_DVB_TDA8083=m\nCONFIG_DVB_TDA10086=m\nCONFIG_DVB_TDA8261=m\nCONFIG_DVB_VES1X93=m\nCONFIG_DVB_TUNER_ITD1000=m\nCONFIG_DVB_TUNER_CX24113=m\nCONFIG_DVB_TDA826X=m\nCONFIG_DVB_TUA6100=m\nCONFIG_DVB_CX24116=m\nCONFIG_DVB_CX24117=m\nCONFIG_DVB_CX24120=m\nCONFIG_DVB_SI21XX=m\nCONFIG_DVB_TS2020=m\nCONFIG_DVB_DS3000=m\nCONFIG_DVB_MB86A16=m\nCONFIG_DVB_TDA10071=m\n\n#\n# DVB-T (terrestrial) frontends\n#\nCONFIG_DVB_SP887X=m\nCONFIG_DVB_CX22700=m\nCONFIG_DVB_CX22702=m\nCONFIG_DVB_S5H1432=m\nCONFIG_DVB_DRXD=m\nCONFIG_DVB_L64781=m\nCONFIG_DVB_TDA1004X=m\nCONFIG_DVB_NXT6000=m\nCONFIG_DVB_MT352=m\nCONFIG_DVB_ZL10353=m\nCONFIG_DVB_DIB3000MB=m\nCONFIG_DVB_DIB3000MC=m\nCONFIG_DVB_DIB7000M=m\nCONFIG_DVB_DIB7000P=m\nCONFIG_DVB_DIB9000=m\nCONFIG_DVB_TDA10048=m\nCONFIG_DVB_AF9013=m\nCONFIG_DVB_EC100=m\nCONFIG_DVB_STV0367=m\nCONFIG_DVB_CXD2820R=m\nCONFIG_DVB_CXD2841ER=m\nCONFIG_DVB_RTL2830=m\nCONFIG_DVB_RTL2832=m\nCONFIG_DVB_RTL2832_SDR=m\nCONFIG_DVB_SI2168=m\nCONFIG_DVB_ZD1301_DEMOD=m\nCONFIG_DVB_CXD2880=m\n\n#\n# DVB-C (cable) frontends\n#\nCONFIG_DVB_VES1820=m\nCONFIG_DVB_TDA10021=m\nCONFIG_DVB_TDA10023=m\nCONFIG_DVB_STV0297=m\n\n#\n# ATSC (North American/Korean Terrestrial/Cable DTV) frontends\n#\nCONFIG_DVB_NXT200X=m\nCONFIG_DVB_OR51211=m\nCONFIG_DVB_OR51132=m\nCONFIG_DVB_BCM3510=m\nCONFIG_DVB_LGDT330X=m\nCONFIG_DVB_LGDT3305=m\nCONFIG_DVB_LGDT3306A=m\nCONFIG_DVB_LG2160=m\nCONFIG_DVB_S5H1409=m\nCONFIG_DVB_AU8522=m\nCONFIG_DVB_AU8522_DTV=m\nCONFIG_DVB_AU8522_V4L=m\nCONFIG_DVB_S5H1411=m\nCONFIG_DVB_MXL692=m\n\n#\n# ISDB-T (terrestrial) frontends\n#\nCONFIG_DVB_S921=m\nCONFIG_DVB_DIB8000=m\nCONFIG_DVB_MB86A20S=m\n\n#\n# ISDB-S (satellite) & ISDB-T (terrestrial) frontends\n#\nCONFIG_DVB_TC90522=m\nCONFIG_DVB_MN88443X=m\n\n#\n# Digital terrestrial only tuners/PLL\n#\nCONFIG_DVB_PLL=m\nCONFIG_DVB_TUNER_DIB0070=m\nCONFIG_DVB_TUNER_DIB0090=m\n\n#\n# SEC control devices for DVB-S\n#\nCONFIG_DVB_DRX39XYJ=m\nCONFIG_DVB_LNBH25=m\nCONFIG_DVB_LNBH29=m\nCONFIG_DVB_LNBP21=m\nCONFIG_DVB_LNBP22=m\nCONFIG_DVB_ISL6405=m\nCONFIG_DVB_ISL6421=m\nCONFIG_DVB_ISL6423=m\nCONFIG_DVB_A8293=m\nCONFIG_DVB_LGS8GL5=m\nCONFIG_DVB_LGS8GXX=m\nCONFIG_DVB_ATBM8830=m\nCONFIG_DVB_TDA665x=m\nCONFIG_DVB_IX2505V=m\nCONFIG_DVB_M88RS2000=m\nCONFIG_DVB_AF9033=m\nCONFIG_DVB_HORUS3A=m\nCONFIG_DVB_ASCOT2E=m\nCONFIG_DVB_HELENE=m\n\n#\n# Common Interface (EN50221) controller drivers\n#\nCONFIG_DVB_CXD2099=m\nCONFIG_DVB_SP2=m\n# end of Customise DVB Frontends\n\n#\n# Tools to develop new frontends\n#\n# CONFIG_DVB_DUMMY_FE is not set\n# end of Media ancillary drivers\n\n#\n# Graphics support\n#\n# CONFIG_IMX_IPUV3_CORE is not set\nCONFIG_DRM=y\nCONFIG_DRM_MIPI_DSI=y\n# CONFIG_DRM_DP_AUX_CHARDEV is not set\n# CONFIG_DRM_DEBUG_MM is not set\n# CONFIG_DRM_DEBUG_SELFTEST is not set\nCONFIG_DRM_KMS_HELPER=y\n# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set\nCONFIG_DRM_FBDEV_EMULATION=y\nCONFIG_DRM_FBDEV_OVERALLOC=100\n# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set\n# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set\n# CONFIG_DRM_DP_CEC is not set\nCONFIG_DRM_GEM_CMA_HELPER=y\nCONFIG_DRM_KMS_CMA_HELPER=y\n\n#\n# I2C encoder or helper chips\n#\n# CONFIG_DRM_I2C_CH7006 is not set\n# CONFIG_DRM_I2C_SIL164 is not set\n# CONFIG_DRM_I2C_NXP_TDA998X is not set\n# CONFIG_DRM_I2C_NXP_TDA9950 is not set\n# end of I2C encoder or helper chips\n\n#\n# ARM devices\n#\n# CONFIG_DRM_HDLCD is not set\n# CONFIG_DRM_MALI_DISPLAY is not set\n# CONFIG_DRM_KOMEDA is not set\n# end of ARM devices\n\nCONFIG_DRM_ADI_AXI_HDMI=y\n# CONFIG_DRM_VGEM is not set\n# CONFIG_DRM_VKMS is not set\n# CONFIG_DRM_EXYNOS is not set\n# CONFIG_DRM_UDL is not set\n# CONFIG_DRM_ARMADA is not set\n# CONFIG_DRM_RCAR_DW_HDMI is not set\n# CONFIG_DRM_RCAR_LVDS is not set\n# CONFIG_DRM_OMAP is not set\n# CONFIG_DRM_TILCDC is not set\n# CONFIG_DRM_VIRTIO_GPU is not set\n# CONFIG_DRM_FSL_DCU is not set\n# CONFIG_DRM_STM is not set\nCONFIG_DRM_PANEL=y\n\n#\n# Display Panels\n#\n# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set\n# CONFIG_DRM_PANEL_ARM_VERSATILE is not set\n# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set\n# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set\n# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set\n# CONFIG_DRM_PANEL_DSI_CM is not set\n# CONFIG_DRM_PANEL_LVDS is not set\n# CONFIG_DRM_PANEL_SIMPLE is not set\n# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set\n# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set\n# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set\n# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set\n# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set\n# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set\n# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set\n# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set\n# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set\n# CONFIG_DRM_PANEL_KHADAS_TS050 is not set\n# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set\n# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set\n# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set\n# CONFIG_DRM_PANEL_LG_LB035Q02 is not set\n# CONFIG_DRM_PANEL_LG_LG4573 is not set\n# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set\n# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set\n# CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set\n# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set\n# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set\n# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set\n# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set\n# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set\n# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set\n# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set\n# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set\n# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set\n# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set\n# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set\n# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set\n# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set\n# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set\n# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set\n# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set\n# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set\n# CONFIG_DRM_PANEL_SONY_ACX424AKP is not set\n# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set\n# CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set\n# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set\n# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set\n# CONFIG_DRM_PANEL_TPO_TPG110 is not set\n# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set\n# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set\n# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set\n# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set\n# end of Display Panels\n\nCONFIG_DRM_BRIDGE=y\nCONFIG_DRM_PANEL_BRIDGE=y\n\n#\n# Display Interface Bridges\n#\n# CONFIG_DRM_CDNS_DSI is not set\n# CONFIG_DRM_CHIPONE_ICN6211 is not set\n# CONFIG_DRM_CHRONTEL_CH7033 is not set\n# CONFIG_DRM_DISPLAY_CONNECTOR is not set\n# CONFIG_DRM_LONTIUM_LT8912B is not set\n# CONFIG_DRM_LONTIUM_LT9611 is not set\n# CONFIG_DRM_LONTIUM_LT9611UXC is not set\n# CONFIG_DRM_ITE_IT66121 is not set\n# CONFIG_DRM_LVDS_CODEC is not set\n# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set\n# CONFIG_DRM_NWL_MIPI_DSI is not set\n# CONFIG_DRM_NXP_PTN3460 is not set\n# CONFIG_DRM_PARADE_PS8622 is not set\n# CONFIG_DRM_PARADE_PS8640 is not set\n# CONFIG_DRM_SIL_SII8620 is not set\n# CONFIG_DRM_SII902X is not set\n# CONFIG_DRM_SII9234 is not set\n# CONFIG_DRM_SIMPLE_BRIDGE is not set\n# CONFIG_DRM_THINE_THC63LVD1024 is not set\n# CONFIG_DRM_TOSHIBA_TC358762 is not set\n# CONFIG_DRM_TOSHIBA_TC358764 is not set\n# CONFIG_DRM_TOSHIBA_TC358767 is not set\n# CONFIG_DRM_TOSHIBA_TC358768 is not set\n# CONFIG_DRM_TOSHIBA_TC358775 is not set\n# CONFIG_DRM_TI_TFP410 is not set\n# CONFIG_DRM_TI_SN65DSI83 is not set\n# CONFIG_DRM_TI_SN65DSI86 is not set\n# CONFIG_DRM_TI_TPD12S015 is not set\n# CONFIG_DRM_ANALOGIX_ANX6345 is not set\n# CONFIG_DRM_ANALOGIX_ANX78XX is not set\n# CONFIG_DRM_ANALOGIX_ANX7625 is not set\nCONFIG_DRM_I2C_ADV7511=y\nCONFIG_DRM_I2C_ADV7511_AUDIO=y\nCONFIG_DRM_I2C_ADV7511_CEC=y\n# CONFIG_DRM_CDNS_MHDP8546 is not set\n# end of Display Interface Bridges\n\n# CONFIG_DRM_STI is not set\n# CONFIG_DRM_ETNAVIV is not set\n# CONFIG_DRM_MXSFB is not set\n# CONFIG_DRM_ARCPGU is not set\n# CONFIG_DRM_GM12U320 is not set\n# CONFIG_DRM_SIMPLEDRM is not set\n# CONFIG_TINYDRM_HX8357D is not set\n# CONFIG_TINYDRM_ILI9225 is not set\n# CONFIG_TINYDRM_ILI9341 is not set\n# CONFIG_TINYDRM_ILI9486 is not set\n# CONFIG_TINYDRM_MI0283QT is not set\n# CONFIG_TINYDRM_REPAPER is not set\n# CONFIG_TINYDRM_ST7586 is not set\n# CONFIG_TINYDRM_ST7735R is not set\n# CONFIG_DRM_PL111 is not set\n# CONFIG_DRM_TVE200 is not set\n# CONFIG_DRM_LIMA is not set\n# CONFIG_DRM_PANFROST is not set\n# CONFIG_DRM_MCDE is not set\n# CONFIG_DRM_TIDSS is not set\n# CONFIG_DRM_XLNX is not set\n# CONFIG_DRM_GUD is not set\n# CONFIG_DRM_LEGACY is not set\nCONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y\n\n#\n# Frame buffer Devices\n#\nCONFIG_FB_CMDLINE=y\nCONFIG_FB_NOTIFY=y\nCONFIG_FB=y\n# CONFIG_FIRMWARE_EDID is not set\nCONFIG_FB_CFB_FILLRECT=y\nCONFIG_FB_CFB_COPYAREA=y\nCONFIG_FB_CFB_IMAGEBLIT=y\nCONFIG_FB_SYS_FILLRECT=y\nCONFIG_FB_SYS_COPYAREA=y\nCONFIG_FB_SYS_IMAGEBLIT=y\n# CONFIG_FB_FOREIGN_ENDIAN is not set\nCONFIG_FB_SYS_FOPS=y\nCONFIG_FB_DEFERRED_IO=y\nCONFIG_FB_BACKLIGHT=y\n# CONFIG_FB_MODE_HELPERS is not set\n# CONFIG_FB_TILEBLITTING is not set\n\n#\n# Frame buffer hardware drivers\n#\n# CONFIG_FB_ALTERA_VIP is not set\n# CONFIG_FB_ARMCLCD is not set\n# CONFIG_FB_UVESA is not set\n# CONFIG_FB_OPENCORES is not set\n# CONFIG_FB_S1D13XXX is not set\n# CONFIG_FB_SMSCUFX is not set\n# CONFIG_FB_UDL is not set\n# CONFIG_FB_IBM_GXT4500 is not set\n# CONFIG_FB_XILINX is not set\n# CONFIG_FB_VIRTUAL is not set\n# CONFIG_FB_METRONOME is not set\n# CONFIG_FB_SIMPLE is not set\n# CONFIG_FB_SSD1307 is not set\n# end of Frame buffer Devices\n\n#\n# Backlight & LCD device support\n#\n# CONFIG_LCD_CLASS_DEVICE is not set\nCONFIG_BACKLIGHT_CLASS_DEVICE=y\n# CONFIG_BACKLIGHT_KTD253 is not set\n# CONFIG_BACKLIGHT_PWM is not set\n# CONFIG_BACKLIGHT_QCOM_WLED is not set\nCONFIG_BACKLIGHT_ADP5520=y\nCONFIG_BACKLIGHT_ADP8860=y\nCONFIG_BACKLIGHT_ADP8870=y\n# CONFIG_BACKLIGHT_LM3630A is not set\n# CONFIG_BACKLIGHT_LM3639 is not set\n# CONFIG_BACKLIGHT_LP855X is not set\n# CONFIG_BACKLIGHT_GPIO is not set\n# CONFIG_BACKLIGHT_LV5207LP is not set\n# CONFIG_BACKLIGHT_BD6107 is not set\n# CONFIG_BACKLIGHT_ARCXCNN is not set\n# CONFIG_BACKLIGHT_LED is not set\n# end of Backlight & LCD device support\n\nCONFIG_HDMI=y\n\n#\n# Console display driver support\n#\nCONFIG_DUMMY_CONSOLE=y\nCONFIG_FRAMEBUFFER_CONSOLE=y\n# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set\nCONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y\n# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set\n# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set\n# end of Console display driver support\n\nCONFIG_LOGO=y\nCONFIG_LOGO_LINUX_MONO=y\nCONFIG_LOGO_LINUX_VGA16=y\nCONFIG_LOGO_LINUX_CLUT224=y\n# end of Graphics support\n\nCONFIG_SOUND=y\nCONFIG_SND=y\nCONFIG_SND_TIMER=y\nCONFIG_SND_PCM=y\nCONFIG_SND_PCM_ELD=y\nCONFIG_SND_PCM_IEC958=y\nCONFIG_SND_DMAENGINE_PCM=y\nCONFIG_SND_HWDEP=y\nCONFIG_SND_RAWMIDI=y\nCONFIG_SND_JACK=y\nCONFIG_SND_JACK_INPUT_DEV=y\n# CONFIG_SND_OSSEMUL is not set\nCONFIG_SND_PCM_TIMER=y\n# CONFIG_SND_HRTIMER is not set\n# CONFIG_SND_DYNAMIC_MINORS is not set\n# CONFIG_SND_SUPPORT_OLD_API is not set\nCONFIG_SND_PROC_FS=y\n# CONFIG_SND_VERBOSE_PROCFS is not set\n# CONFIG_SND_VERBOSE_PRINTK is not set\n# CONFIG_SND_DEBUG is not set\n# CONFIG_SND_SEQUENCER is not set\n# CONFIG_SND_DRIVERS is not set\n\n#\n# HD-Audio\n#\n# end of HD-Audio\n\nCONFIG_SND_HDA_PREALLOC_SIZE=64\n# CONFIG_SND_ARM is not set\n# CONFIG_SND_SPI is not set\nCONFIG_SND_USB=y\nCONFIG_SND_USB_AUDIO=y\nCONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y\n# CONFIG_SND_USB_UA101 is not set\n# CONFIG_SND_USB_CAIAQ is not set\n# CONFIG_SND_USB_6FIRE is not set\n# CONFIG_SND_USB_HIFACE is not set\n# CONFIG_SND_BCD2000 is not set\n# CONFIG_SND_USB_POD is not set\n# CONFIG_SND_USB_PODHD is not set\n# CONFIG_SND_USB_TONEPORT is not set\n# CONFIG_SND_USB_VARIAX is not set\nCONFIG_SND_SOC=y\nCONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y\nCONFIG_SND_SOC_ADI=y\nCONFIG_SND_SOC_ADI_AXI_I2S=y\nCONFIG_SND_SOC_ADI_AXI_SPDIF=y\nCONFIG_SND_SOC_ADRV936X_BOX=y\n# CONFIG_SND_SOC_AMD_ACP is not set\n# CONFIG_SND_ATMEL_SOC is not set\n# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set\n# CONFIG_SND_DESIGNWARE_I2S is not set\n\n#\n# SoC Audio for Freescale CPUs\n#\n\n#\n# Common SoC Audio options for Freescale CPUs:\n#\n# CONFIG_SND_SOC_FSL_ASRC is not set\n# CONFIG_SND_SOC_FSL_SAI is not set\n# CONFIG_SND_SOC_FSL_AUDMIX is not set\n# CONFIG_SND_SOC_FSL_SSI is not set\n# CONFIG_SND_SOC_FSL_SPDIF is not set\n# CONFIG_SND_SOC_FSL_ESAI is not set\n# CONFIG_SND_SOC_FSL_MICFIL is not set\n# CONFIG_SND_SOC_FSL_XCVR is not set\n# CONFIG_SND_SOC_IMX_AUDMUX is not set\n# end of SoC Audio for Freescale CPUs\n\n# CONFIG_SND_I2S_HI6210_I2S is not set\n# CONFIG_SND_SOC_IMG is not set\n# CONFIG_SND_SOC_MTK_BTCVSD is not set\n# CONFIG_SND_SOC_SOF_TOPLEVEL is not set\n\n#\n# STMicroelectronics STM32 SOC audio support\n#\n# end of STMicroelectronics STM32 SOC audio support\n\n# CONFIG_SND_SOC_XILINX_DP is not set\n# CONFIG_SND_SOC_XILINX_I2S is not set\n# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set\n# CONFIG_SND_SOC_XILINX_SPDIF is not set\n# CONFIG_SND_SOC_XTFPGA_I2S is not set\nCONFIG_SND_SOC_I2C_AND_SPI=y\n\n#\n# CODEC drivers\n#\n# CONFIG_SND_SOC_AC97_CODEC is not set\nCONFIG_SND_SOC_AD1836=y\nCONFIG_SND_SOC_AD193X=y\nCONFIG_SND_SOC_AD193X_SPI=y\nCONFIG_SND_SOC_AD193X_I2C=y\n# CONFIG_SND_SOC_AD1980 is not set\nCONFIG_SND_SOC_AD73311=y\nCONFIG_SND_SOC_ADAU_UTILS=y\nCONFIG_SND_SOC_ADAU1372=y\nCONFIG_SND_SOC_ADAU1372_I2C=y\nCONFIG_SND_SOC_ADAU1372_SPI=y\nCONFIG_SND_SOC_ADAU1373=y\nCONFIG_SND_SOC_ADAU1701=y\nCONFIG_SND_SOC_ADAU17X1=y\nCONFIG_SND_SOC_ADAU1761=y\nCONFIG_SND_SOC_ADAU1761_I2C=y\nCONFIG_SND_SOC_ADAU1761_SPI=y\nCONFIG_SND_SOC_ADAU1781=y\nCONFIG_SND_SOC_ADAU1781_I2C=y\nCONFIG_SND_SOC_ADAU1781_SPI=y\nCONFIG_SND_SOC_ADAU1977=y\nCONFIG_SND_SOC_ADAU1977_SPI=y\nCONFIG_SND_SOC_ADAU1977_I2C=y\nCONFIG_SND_SOC_ADAU7002=y\nCONFIG_SND_SOC_ADAU7118=y\nCONFIG_SND_SOC_ADAU7118_HW=y\nCONFIG_SND_SOC_ADAU7118_I2C=y\nCONFIG_SND_SOC_ADAV80X=y\nCONFIG_SND_SOC_ADAV801=y\nCONFIG_SND_SOC_ADAV803=y\n# CONFIG_SND_SOC_AK4104 is not set\n# CONFIG_SND_SOC_AK4118 is not set\n# CONFIG_SND_SOC_AK4458 is not set\n# CONFIG_SND_SOC_AK4554 is not set\n# CONFIG_SND_SOC_AK4613 is not set\n# CONFIG_SND_SOC_AK4642 is not set\n# CONFIG_SND_SOC_AK5386 is not set\n# CONFIG_SND_SOC_AK5558 is not set\n# CONFIG_SND_SOC_ALC5623 is not set\n# CONFIG_SND_SOC_BD28623 is not set\n# CONFIG_SND_SOC_BT_SCO is not set\n# CONFIG_SND_SOC_CS35L32 is not set\n# CONFIG_SND_SOC_CS35L33 is not set\n# CONFIG_SND_SOC_CS35L34 is not set\n# CONFIG_SND_SOC_CS35L35 is not set\n# CONFIG_SND_SOC_CS35L36 is not set\n# CONFIG_SND_SOC_CS42L42 is not set\n# CONFIG_SND_SOC_CS42L51_I2C is not set\n# CONFIG_SND_SOC_CS42L52 is not set\n# CONFIG_SND_SOC_CS42L56 is not set\n# CONFIG_SND_SOC_CS42L73 is not set\n# CONFIG_SND_SOC_CS4234 is not set\n# CONFIG_SND_SOC_CS4265 is not set\n# CONFIG_SND_SOC_CS4270 is not set\n# CONFIG_SND_SOC_CS4271_I2C is not set\n# CONFIG_SND_SOC_CS4271_SPI is not set\n# CONFIG_SND_SOC_CS42XX8_I2C is not set\n# CONFIG_SND_SOC_CS43130 is not set\n# CONFIG_SND_SOC_CS4341 is not set\n# CONFIG_SND_SOC_CS4349 is not set\n# CONFIG_SND_SOC_CS53L30 is not set\n# CONFIG_SND_SOC_CX2072X is not set\n# CONFIG_SND_SOC_DA7213 is not set\n# CONFIG_SND_SOC_DMIC is not set\nCONFIG_SND_SOC_HDMI_CODEC=y\n# CONFIG_SND_SOC_ES7134 is not set\n# CONFIG_SND_SOC_ES7241 is not set\n# CONFIG_SND_SOC_ES8316 is not set\n# CONFIG_SND_SOC_ES8328_I2C is not set\n# CONFIG_SND_SOC_ES8328_SPI is not set\n# CONFIG_SND_SOC_GTM601 is not set\n# CONFIG_SND_SOC_ICS43432 is not set\n# CONFIG_SND_SOC_INNO_RK3036 is not set\n# CONFIG_SND_SOC_MAX98088 is not set\n# CONFIG_SND_SOC_MAX98357A is not set\n# CONFIG_SND_SOC_MAX98504 is not set\n# CONFIG_SND_SOC_MAX9867 is not set\n# CONFIG_SND_SOC_MAX98927 is not set\n# CONFIG_SND_SOC_MAX98373_I2C is not set\n# CONFIG_SND_SOC_MAX98390 is not set\n# CONFIG_SND_SOC_MAX9860 is not set\n# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set\n# CONFIG_SND_SOC_PCM1681 is not set\n# CONFIG_SND_SOC_PCM1789_I2C is not set\n# CONFIG_SND_SOC_PCM179X_I2C is not set\n# CONFIG_SND_SOC_PCM179X_SPI is not set\n# CONFIG_SND_SOC_PCM186X_I2C is not set\n# CONFIG_SND_SOC_PCM186X_SPI is not set\n# CONFIG_SND_SOC_PCM3060_I2C is not set\n# CONFIG_SND_SOC_PCM3060_SPI is not set\n# CONFIG_SND_SOC_PCM3168A_I2C is not set\n# CONFIG_SND_SOC_PCM3168A_SPI is not set\n# CONFIG_SND_SOC_PCM5102A is not set\n# CONFIG_SND_SOC_PCM512x_I2C is not set\n# CONFIG_SND_SOC_PCM512x_SPI is not set\n# CONFIG_SND_SOC_RK3328 is not set\n# CONFIG_SND_SOC_RT5616 is not set\n# CONFIG_SND_SOC_RT5631 is not set\n# CONFIG_SND_SOC_RT5640 is not set\n# CONFIG_SND_SOC_RT5659 is not set\n# CONFIG_SND_SOC_SGTL5000 is not set\nCONFIG_SND_SOC_SIGMADSP=y\nCONFIG_SND_SOC_SIGMADSP_I2C=y\nCONFIG_SND_SOC_SIGMADSP_REGMAP=y\n# CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set\n# CONFIG_SND_SOC_SIMPLE_MUX is not set\n# CONFIG_SND_SOC_SPDIF is not set\nCONFIG_SND_SOC_SSM2305=y\nCONFIG_SND_SOC_SSM2518=y\nCONFIG_SND_SOC_SSM2602=y\nCONFIG_SND_SOC_SSM2602_SPI=y\nCONFIG_SND_SOC_SSM2602_I2C=y\nCONFIG_SND_SOC_SSM4567=y\n# CONFIG_SND_SOC_STA32X is not set\n# CONFIG_SND_SOC_STA350 is not set\n# CONFIG_SND_SOC_STI_SAS is not set\n# CONFIG_SND_SOC_TAS2552 is not set\n# CONFIG_SND_SOC_TAS2562 is not set\n# CONFIG_SND_SOC_TAS2764 is not set\n# CONFIG_SND_SOC_TAS2770 is not set\n# CONFIG_SND_SOC_TAS5086 is not set\n# CONFIG_SND_SOC_TAS571X is not set\n# CONFIG_SND_SOC_TAS5720 is not set\n# CONFIG_SND_SOC_TAS6424 is not set\n# CONFIG_SND_SOC_TDA7419 is not set\n# CONFIG_SND_SOC_TFA9879 is not set\n# CONFIG_SND_SOC_TFA989X is not set\n# CONFIG_SND_SOC_TLV320AIC23_I2C is not set\n# CONFIG_SND_SOC_TLV320AIC23_SPI is not set\n# CONFIG_SND_SOC_TLV320AIC31XX is not set\n# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set\n# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set\n# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set\n# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set\n# CONFIG_SND_SOC_TLV320ADCX140 is not set\nCONFIG_SND_SOC_TS3A227E=y\n# CONFIG_SND_SOC_TSCS42XX is not set\n# CONFIG_SND_SOC_TSCS454 is not set\n# CONFIG_SND_SOC_UDA1334 is not set\n# CONFIG_SND_SOC_WM8510 is not set\n# CONFIG_SND_SOC_WM8523 is not set\n# CONFIG_SND_SOC_WM8524 is not set\n# CONFIG_SND_SOC_WM8580 is not set\n# CONFIG_SND_SOC_WM8711 is not set\n# CONFIG_SND_SOC_WM8728 is not set\n# CONFIG_SND_SOC_WM8731 is not set\n# CONFIG_SND_SOC_WM8737 is not set\n# CONFIG_SND_SOC_WM8741 is not set\n# CONFIG_SND_SOC_WM8750 is not set\n# CONFIG_SND_SOC_WM8753 is not set\n# CONFIG_SND_SOC_WM8770 is not set\n# CONFIG_SND_SOC_WM8776 is not set\n# CONFIG_SND_SOC_WM8782 is not set\n# CONFIG_SND_SOC_WM8804_I2C is not set\n# CONFIG_SND_SOC_WM8804_SPI is not set\n# CONFIG_SND_SOC_WM8903 is not set\n# CONFIG_SND_SOC_WM8904 is not set\n# CONFIG_SND_SOC_WM8960 is not set\n# CONFIG_SND_SOC_WM8962 is not set\n# CONFIG_SND_SOC_WM8974 is not set\n# CONFIG_SND_SOC_WM8978 is not set\n# CONFIG_SND_SOC_WM8985 is not set\n# CONFIG_SND_SOC_ZL38060 is not set\n# CONFIG_SND_SOC_MAX9759 is not set\n# CONFIG_SND_SOC_MT6351 is not set\n# CONFIG_SND_SOC_MT6358 is not set\n# CONFIG_SND_SOC_MT6660 is not set\n# CONFIG_SND_SOC_NAU8315 is not set\n# CONFIG_SND_SOC_NAU8540 is not set\n# CONFIG_SND_SOC_NAU8810 is not set\n# CONFIG_SND_SOC_NAU8822 is not set\n# CONFIG_SND_SOC_NAU8824 is not set\n# CONFIG_SND_SOC_TPA6130A2 is not set\n# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set\n# CONFIG_SND_SOC_LPASS_VA_MACRO is not set\n# CONFIG_SND_SOC_LPASS_RX_MACRO is not set\n# CONFIG_SND_SOC_LPASS_TX_MACRO is not set\n# end of CODEC drivers\n\nCONFIG_SND_SIMPLE_CARD_UTILS=y\nCONFIG_SND_SIMPLE_CARD=y\n# CONFIG_SND_AUDIO_GRAPH_CARD is not set\n\n#\n# HID support\n#\nCONFIG_HID=y\n# CONFIG_HID_BATTERY_STRENGTH is not set\nCONFIG_HIDRAW=y\n# CONFIG_UHID is not set\nCONFIG_HID_GENERIC=y\n\n#\n# Special HID drivers\n#\nCONFIG_HID_A4TECH=y\n# CONFIG_HID_ACCUTOUCH is not set\nCONFIG_HID_ACRUX=y\nCONFIG_HID_ACRUX_FF=y\nCONFIG_HID_APPLE=y\n# CONFIG_HID_APPLEIR is not set\n# CONFIG_HID_ASUS is not set\n# CONFIG_HID_AUREAL is not set\nCONFIG_HID_BELKIN=y\n# CONFIG_HID_BETOP_FF is not set\n# CONFIG_HID_BIGBEN_FF is not set\nCONFIG_HID_CHERRY=y\nCONFIG_HID_CHICONY=y\n# CONFIG_HID_CORSAIR is not set\n# CONFIG_HID_COUGAR is not set\n# CONFIG_HID_MACALLY is not set\nCONFIG_HID_PRODIKEYS=y\n# CONFIG_HID_CMEDIA is not set\n# CONFIG_HID_CP2112 is not set\n# CONFIG_HID_CREATIVE_SB0540 is not set\nCONFIG_HID_CYPRESS=y\nCONFIG_HID_DRAGONRISE=y\n# CONFIG_DRAGONRISE_FF is not set\nCONFIG_HID_EMS_FF=y\n# CONFIG_HID_ELAN is not set\n# CONFIG_HID_ELECOM is not set\n# CONFIG_HID_ELO is not set\nCONFIG_HID_EZKEY=y\n# CONFIG_HID_FT260 is not set\n# CONFIG_HID_GEMBIRD is not set\n# CONFIG_HID_GFRM is not set\n# CONFIG_HID_GLORIOUS is not set\nCONFIG_HID_HOLTEK=y\nCONFIG_HOLTEK_FF=y\n# CONFIG_HID_VIVALDI is not set\n# CONFIG_HID_GT683R is not set\nCONFIG_HID_KEYTOUCH=y\nCONFIG_HID_KYE=y\nCONFIG_HID_UCLOGIC=y\nCONFIG_HID_WALTOP=y\n# CONFIG_HID_VIEWSONIC is not set\nCONFIG_HID_GYRATION=y\n# CONFIG_HID_ICADE is not set\n# CONFIG_HID_ITE is not set\n# CONFIG_HID_JABRA is not set\nCONFIG_HID_TWINHAN=y\nCONFIG_HID_KENSINGTON=y\nCONFIG_HID_LCPOWER=y\n# CONFIG_HID_LED is not set\n# CONFIG_HID_LENOVO is not set\nCONFIG_HID_LOGITECH=y\nCONFIG_HID_LOGITECH_DJ=y\nCONFIG_HID_LOGITECH_HIDPP=y\nCONFIG_LOGITECH_FF=y\nCONFIG_LOGIRUMBLEPAD2_FF=y\nCONFIG_LOGIG940_FF=y\nCONFIG_LOGIWHEELS_FF=y\n# CONFIG_HID_MAGICMOUSE is not set\n# CONFIG_HID_MALTRON is not set\n# CONFIG_HID_MAYFLASH is not set\n# CONFIG_HID_REDRAGON is not set\nCONFIG_HID_MICROSOFT=y\nCONFIG_HID_MONTEREY=y\nCONFIG_HID_MULTITOUCH=y\n# CONFIG_HID_NTI is not set\nCONFIG_HID_NTRIG=y\nCONFIG_HID_ORTEK=y\nCONFIG_HID_PANTHERLORD=y\nCONFIG_PANTHERLORD_FF=y\n# CONFIG_HID_PENMOUNT is not set\nCONFIG_HID_PETALYNX=y\nCONFIG_HID_PICOLCD=y\nCONFIG_HID_PICOLCD_FB=y\n# CONFIG_HID_PICOLCD_BACKLIGHT is not set\n# CONFIG_HID_PICOLCD_LEDS is not set\n# CONFIG_HID_PLANTRONICS is not set\n# CONFIG_HID_PLAYSTATION is not set\nCONFIG_HID_PRIMAX=y\n# CONFIG_HID_RETRODE is not set\nCONFIG_HID_ROCCAT=y\n# CONFIG_HID_SAITEK is not set\nCONFIG_HID_SAMSUNG=y\n# CONFIG_HID_SEMITEK is not set\nCONFIG_HID_SONY=y\n# CONFIG_SONY_FF is not set\nCONFIG_HID_SPEEDLINK=y\n# CONFIG_HID_STEAM is not set\n# CONFIG_HID_STEELSERIES is not set\nCONFIG_HID_SUNPLUS=y\n# CONFIG_HID_RMI is not set\nCONFIG_HID_GREENASIA=y\nCONFIG_GREENASIA_FF=y\nCONFIG_HID_SMARTJOYPLUS=y\nCONFIG_SMARTJOYPLUS_FF=y\n# CONFIG_HID_TIVO is not set\nCONFIG_HID_TOPSEED=y\n# CONFIG_HID_THINGM is not set\nCONFIG_HID_THRUSTMASTER=y\nCONFIG_THRUSTMASTER_FF=y\n# CONFIG_HID_UDRAW_PS3 is not set\n# CONFIG_HID_WACOM is not set\n# CONFIG_HID_WIIMOTE is not set\n# CONFIG_HID_XINMO is not set\nCONFIG_HID_ZEROPLUS=y\nCONFIG_ZEROPLUS_FF=y\nCONFIG_HID_ZYDACRON=y\n# CONFIG_HID_SENSOR_HUB is not set\n# CONFIG_HID_ALPS is not set\n# CONFIG_HID_MCP2221 is not set\n# end of Special HID drivers\n\n#\n# USB HID support\n#\nCONFIG_USB_HID=y\n# CONFIG_HID_PID is not set\nCONFIG_USB_HIDDEV=y\n# end of USB HID support\n\n#\n# I2C HID support\n#\n# CONFIG_I2C_HID_OF is not set\n# CONFIG_I2C_HID_OF_GOODIX is not set\n# end of I2C HID support\n# end of HID support\n\nCONFIG_USB_OHCI_LITTLE_ENDIAN=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USB_COMMON=y\n# CONFIG_USB_LED_TRIG is not set\nCONFIG_USB_ULPI_BUS=y\n# CONFIG_USB_CONN_GPIO is not set\nCONFIG_USB_ARCH_HAS_HCD=y\nCONFIG_USB=y\nCONFIG_USB_ANNOUNCE_NEW_DEVICES=y\n\n#\n# Miscellaneous USB options\n#\nCONFIG_USB_DEFAULT_PERSIST=y\n# CONFIG_USB_FEW_INIT_RETRIES is not set\n# CONFIG_USB_DYNAMIC_MINORS is not set\nCONFIG_USB_OTG=y\n# CONFIG_USB_OTG_PRODUCTLIST is not set\n# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set\n# CONFIG_USB_OTG_FSM is not set\n# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set\nCONFIG_USB_AUTOSUSPEND_DELAY=2\n# CONFIG_USB_MON is not set\n\n#\n# USB Host Controller Drivers\n#\n# CONFIG_USB_C67X00_HCD is not set\nCONFIG_USB_XHCI_HCD=y\n# CONFIG_USB_XHCI_DBGCAP is not set\n# CONFIG_USB_XHCI_PCI_RENESAS is not set\nCONFIG_USB_XHCI_PLATFORM=y\nCONFIG_USB_EHCI_HCD=y\nCONFIG_USB_EHCI_ROOT_HUB_TT=y\n# CONFIG_USB_EHCI_TT_NEWSCHED is not set\n# CONFIG_USB_EHCI_FSL is not set\n# CONFIG_USB_EHCI_HCD_PLATFORM is not set\n# CONFIG_USB_OXU210HP_HCD is not set\n# CONFIG_USB_ISP116X_HCD is not set\n# CONFIG_USB_FOTG210_HCD is not set\n# CONFIG_USB_MAX3421_HCD is not set\n# CONFIG_USB_OHCI_HCD is not set\n# CONFIG_USB_SL811_HCD is not set\n# CONFIG_USB_R8A66597_HCD is not set\n# CONFIG_USB_HCD_TEST_MODE is not set\n\n#\n# USB Device Class drivers\n#\n# CONFIG_USB_ACM is not set\n# CONFIG_USB_PRINTER is not set\n# CONFIG_USB_WDM is not set\n# CONFIG_USB_TMC is not set\n\n#\n# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may\n#\n\n#\n# also be needed; see USB_STORAGE Help for more info\n#\nCONFIG_USB_STORAGE=y\n# CONFIG_USB_STORAGE_DEBUG is not set\n# CONFIG_USB_STORAGE_REALTEK is not set\n# CONFIG_USB_STORAGE_DATAFAB is not set\n# CONFIG_USB_STORAGE_FREECOM is not set\n# CONFIG_USB_STORAGE_ISD200 is not set\n# CONFIG_USB_STORAGE_USBAT is not set\n# CONFIG_USB_STORAGE_SDDR09 is not set\n# CONFIG_USB_STORAGE_SDDR55 is not set\n# CONFIG_USB_STORAGE_JUMPSHOT is not set\n# CONFIG_USB_STORAGE_ALAUDA is not set\n# CONFIG_USB_STORAGE_ONETOUCH is not set\n# CONFIG_USB_STORAGE_KARMA is not set\n# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set\n# CONFIG_USB_STORAGE_ENE_UB6250 is not set\nCONFIG_USB_UAS=y\n\n#\n# USB Imaging devices\n#\n# CONFIG_USB_MDC800 is not set\n# CONFIG_USB_MICROTEK is not set\n# CONFIG_USBIP_CORE is not set\n# CONFIG_USB_CDNS_SUPPORT is not set\n# CONFIG_USB_MUSB_HDRC is not set\nCONFIG_USB_DWC3=y\n# CONFIG_USB_DWC3_ULPI is not set\n# CONFIG_USB_DWC3_HOST is not set\n# CONFIG_USB_DWC3_GADGET is not set\nCONFIG_USB_DWC3_DUAL_ROLE=y\n\n#\n# Platform Glue Driver Support\n#\nCONFIG_USB_DWC3_OF_SIMPLE=y\nCONFIG_USB_DWC2=y\n# CONFIG_USB_DWC2_HOST is not set\n\n#\n# Gadget/Dual-role mode requires USB Gadget support to be enabled\n#\n# CONFIG_USB_DWC2_PERIPHERAL is not set\nCONFIG_USB_DWC2_DUAL_ROLE=y\n# CONFIG_USB_DWC2_DEBUG is not set\n# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set\nCONFIG_USB_CHIPIDEA=y\nCONFIG_USB_CHIPIDEA_UDC=y\nCONFIG_USB_CHIPIDEA_HOST=y\nCONFIG_USB_CHIPIDEA_MSM=y\nCONFIG_USB_CHIPIDEA_IMX=y\nCONFIG_USB_CHIPIDEA_GENERIC=y\nCONFIG_USB_CHIPIDEA_TEGRA=y\n# CONFIG_USB_ISP1760 is not set\n\n#\n# USB port drivers\n#\nCONFIG_USB_SERIAL=y\n# CONFIG_USB_SERIAL_CONSOLE is not set\nCONFIG_USB_SERIAL_GENERIC=y\n# CONFIG_USB_SERIAL_SIMPLE is not set\n# CONFIG_USB_SERIAL_AIRCABLE is not set\n# CONFIG_USB_SERIAL_ARK3116 is not set\n# CONFIG_USB_SERIAL_BELKIN is not set\n# CONFIG_USB_SERIAL_CH341 is not set\n# CONFIG_USB_SERIAL_WHITEHEAT is not set\n# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set\n# CONFIG_USB_SERIAL_CP210X is not set\n# CONFIG_USB_SERIAL_CYPRESS_M8 is not set\n# CONFIG_USB_SERIAL_EMPEG is not set\nCONFIG_USB_SERIAL_FTDI_SIO=y\n# CONFIG_USB_SERIAL_VISOR is not set\n# CONFIG_USB_SERIAL_IPAQ is not set\n# CONFIG_USB_SERIAL_IR is not set\n# CONFIG_USB_SERIAL_EDGEPORT is not set\n# CONFIG_USB_SERIAL_EDGEPORT_TI is not set\n# CONFIG_USB_SERIAL_F81232 is not set\n# CONFIG_USB_SERIAL_F8153X is not set\n# CONFIG_USB_SERIAL_GARMIN is not set\n# CONFIG_USB_SERIAL_IPW is not set\n# CONFIG_USB_SERIAL_IUU is not set\n# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set\n# CONFIG_USB_SERIAL_KEYSPAN is not set\n# CONFIG_USB_SERIAL_KLSI is not set\n# CONFIG_USB_SERIAL_KOBIL_SCT is not set\n# CONFIG_USB_SERIAL_MCT_U232 is not set\n# CONFIG_USB_SERIAL_METRO is not set\n# CONFIG_USB_SERIAL_MOS7720 is not set\n# CONFIG_USB_SERIAL_MOS7840 is not set\n# CONFIG_USB_SERIAL_MXUPORT is not set\n# CONFIG_USB_SERIAL_NAVMAN is not set\n# CONFIG_USB_SERIAL_PL2303 is not set\n# CONFIG_USB_SERIAL_OTI6858 is not set\n# CONFIG_USB_SERIAL_QCAUX is not set\n# CONFIG_USB_SERIAL_QUALCOMM is not set\n# CONFIG_USB_SERIAL_SPCP8X5 is not set\n# CONFIG_USB_SERIAL_SAFE is not set\n# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set\n# CONFIG_USB_SERIAL_SYMBOL is not set\n# CONFIG_USB_SERIAL_TI is not set\n# CONFIG_USB_SERIAL_CYBERJACK is not set\n# CONFIG_USB_SERIAL_OPTION is not set\n# CONFIG_USB_SERIAL_OMNINET is not set\n# CONFIG_USB_SERIAL_OPTICON is not set\n# CONFIG_USB_SERIAL_XSENS_MT is not set\n# CONFIG_USB_SERIAL_WISHBONE is not set\n# CONFIG_USB_SERIAL_SSU100 is not set\n# CONFIG_USB_SERIAL_QT2 is not set\nCONFIG_USB_SERIAL_UPD78F0730=y\n# CONFIG_USB_SERIAL_XR is not set\n# CONFIG_USB_SERIAL_DEBUG is not set\n\n#\n# USB Miscellaneous drivers\n#\n# CONFIG_USB_EMI62 is not set\n# CONFIG_USB_EMI26 is not set\n# CONFIG_USB_ADUTUX is not set\n# CONFIG_USB_SEVSEG is not set\n# CONFIG_USB_LEGOTOWER is not set\n# CONFIG_USB_LCD is not set\n# CONFIG_USB_CYPRESS_CY7C63 is not set\n# CONFIG_USB_CYTHERM is not set\n# CONFIG_USB_IDMOUSE is not set\n# CONFIG_USB_FTDI_ELAN is not set\n# CONFIG_USB_APPLEDISPLAY is not set\n# CONFIG_APPLE_MFI_FASTCHARGE is not set\n# CONFIG_USB_SISUSBVGA is not set\n# CONFIG_USB_LD is not set\n# CONFIG_USB_TRANCEVIBRATOR is not set\n# CONFIG_USB_IOWARRIOR is not set\n# CONFIG_USB_TEST is not set\n# CONFIG_USB_EHSET_TEST_FIXTURE is not set\n# CONFIG_USB_ISIGHTFW is not set\n# CONFIG_USB_YUREX is not set\n# CONFIG_USB_EZUSB_FX2 is not set\n# CONFIG_USB_HUB_USB251XB is not set\n# CONFIG_USB_USB2244 is not set\n# CONFIG_USB_USB5744 is not set\n# CONFIG_USB_HSIC_USB3503 is not set\n# CONFIG_USB_HSIC_USB4604 is not set\n# CONFIG_USB_LINK_LAYER_TEST is not set\n\n#\n# USB Physical Layer drivers\n#\nCONFIG_USB_PHY=y\nCONFIG_NOP_USB_XCEIV=y\n# CONFIG_AM335X_PHY_USB is not set\n# CONFIG_USB_GPIO_VBUS is not set\n# CONFIG_USB_ISP1301 is not set\nCONFIG_USB_ULPI=y\nCONFIG_USB_ULPI_VIEWPORT=y\n# end of USB Physical Layer drivers\n\nCONFIG_USB_GADGET=y\n# CONFIG_USB_GADGET_DEBUG is not set\n# CONFIG_USB_GADGET_DEBUG_FILES is not set\n# CONFIG_USB_GADGET_DEBUG_FS is not set\nCONFIG_USB_GADGET_VBUS_DRAW=2\nCONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2\n# CONFIG_U_SERIAL_CONSOLE is not set\n\n#\n# USB Peripheral Controller\n#\n# CONFIG_USB_FUSB300 is not set\n# CONFIG_USB_FOTG210_UDC is not set\n# CONFIG_USB_GR_UDC is not set\n# CONFIG_USB_R8A66597 is not set\n# CONFIG_USB_PXA27X is not set\n# CONFIG_USB_MV_UDC is not set\n# CONFIG_USB_MV_U3D is not set\n# CONFIG_USB_SNP_UDC_PLAT is not set\n# CONFIG_USB_M66592 is not set\n# CONFIG_USB_BDC_UDC is not set\n# CONFIG_USB_NET2272 is not set\nCONFIG_USB_GADGET_XILINX=y\n# CONFIG_USB_MAX3420_UDC is not set\n# CONFIG_USB_DUMMY_HCD is not set\n# end of USB Peripheral Controller\n\nCONFIG_USB_LIBCOMPOSITE=y\nCONFIG_USB_F_ACM=y\nCONFIG_USB_U_SERIAL=y\nCONFIG_USB_U_ETHER=y\nCONFIG_USB_F_SERIAL=y\nCONFIG_USB_F_NCM=y\nCONFIG_USB_F_ECM=y\nCONFIG_USB_F_EEM=y\nCONFIG_USB_F_SUBSET=y\nCONFIG_USB_F_RNDIS=y\nCONFIG_USB_F_MASS_STORAGE=y\nCONFIG_USB_F_FS=y\nCONFIG_USB_CONFIGFS=y\nCONFIG_USB_CONFIGFS_SERIAL=y\nCONFIG_USB_CONFIGFS_ACM=y\n# CONFIG_USB_CONFIGFS_OBEX is not set\nCONFIG_USB_CONFIGFS_NCM=y\nCONFIG_USB_CONFIGFS_ECM=y\nCONFIG_USB_CONFIGFS_ECM_SUBSET=y\nCONFIG_USB_CONFIGFS_RNDIS=y\nCONFIG_USB_CONFIGFS_EEM=y\nCONFIG_USB_CONFIGFS_MASS_STORAGE=y\n# CONFIG_USB_CONFIGFS_F_LB_SS is not set\nCONFIG_USB_CONFIGFS_F_FS=y\n# CONFIG_USB_CONFIGFS_F_UAC1 is not set\n# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set\n# CONFIG_USB_CONFIGFS_F_UAC2 is not set\n# CONFIG_USB_CONFIGFS_F_MIDI is not set\n# CONFIG_USB_CONFIGFS_F_HID is not set\n# CONFIG_USB_CONFIGFS_F_UVC is not set\n# CONFIG_USB_CONFIGFS_F_PRINTER is not set\n\n#\n# USB Gadget precomposed configurations\n#\n# CONFIG_USB_ZERO is not set\n# CONFIG_USB_AUDIO is not set\n# CONFIG_USB_ETH is not set\n# CONFIG_USB_G_NCM is not set\n# CONFIG_USB_GADGETFS is not set\n# CONFIG_USB_FUNCTIONFS is not set\n# CONFIG_USB_MASS_STORAGE is not set\n# CONFIG_USB_G_SERIAL is not set\n# CONFIG_USB_MIDI_GADGET is not set\n# CONFIG_USB_G_PRINTER is not set\n# CONFIG_USB_CDC_COMPOSITE is not set\n# CONFIG_USB_G_ACM_MS is not set\n# CONFIG_USB_G_MULTI is not set\n# CONFIG_USB_G_HID is not set\n# CONFIG_USB_G_DBGP is not set\n# CONFIG_USB_G_WEBCAM is not set\n# CONFIG_USB_RAW_GADGET is not set\n# end of USB Gadget precomposed configurations\n\nCONFIG_TYPEC=y\n# CONFIG_TYPEC_TCPM is not set\n# CONFIG_TYPEC_UCSI is not set\n# CONFIG_TYPEC_TPS6598X is not set\n# CONFIG_TYPEC_HD3SS3220 is not set\n# CONFIG_TYPEC_STUSB160X is not set\n\n#\n# USB Type-C Multiplexer/DeMultiplexer Switch support\n#\n# CONFIG_TYPEC_MUX_PI3USB30532 is not set\n# end of USB Type-C Multiplexer/DeMultiplexer Switch support\n\n#\n# USB Type-C Alternate Mode drivers\n#\n# CONFIG_TYPEC_DP_ALTMODE is not set\n# end of USB Type-C Alternate Mode drivers\n\nCONFIG_USB_ROLE_SWITCH=y\nCONFIG_MMC=y\nCONFIG_PWRSEQ_EMMC=y\nCONFIG_PWRSEQ_SIMPLE=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_BLOCK_MINORS=8\n# CONFIG_SDIO_UART is not set\n# CONFIG_MMC_TEST is not set\n\n#\n# MMC/SD/SDIO Host Controller Drivers\n#\n# CONFIG_MMC_DEBUG is not set\n# CONFIG_MMC_ARMMMCI is not set\nCONFIG_MMC_SDHCI=y\nCONFIG_MMC_SDHCI_PLTFM=y\nCONFIG_MMC_SDHCI_OF_ARASAN=y\n# CONFIG_MMC_SDHCI_OF_ASPEED is not set\n# CONFIG_MMC_SDHCI_OF_AT91 is not set\n# CONFIG_MMC_SDHCI_OF_DWCMSHC is not set\n# CONFIG_MMC_SDHCI_CADENCE is not set\n# CONFIG_MMC_SDHCI_F_SDH30 is not set\n# CONFIG_MMC_SDHCI_MILBEAUT is not set\n# CONFIG_MMC_SPI is not set\n# CONFIG_MMC_DW is not set\n# CONFIG_MMC_VUB300 is not set\n# CONFIG_MMC_USHC is not set\n# CONFIG_MMC_USDHI6ROL0 is not set\nCONFIG_MMC_CQHCI=y\n# CONFIG_MMC_HSQ is not set\n# CONFIG_MMC_MTK is not set\n# CONFIG_MMC_SDHCI_XENON is not set\n# CONFIG_MMC_SDHCI_OMAP is not set\n# CONFIG_MMC_SDHCI_AM654 is not set\n# CONFIG_MEMSTICK is not set\nCONFIG_NEW_LEDS=y\nCONFIG_LEDS_CLASS=y\nCONFIG_LEDS_CLASS_FLASH=y\n# CONFIG_LEDS_CLASS_MULTICOLOR is not set\nCONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y\n\n#\n# LED drivers\n#\n# CONFIG_LEDS_AN30259A is not set\n# CONFIG_LEDS_AW2013 is not set\n# CONFIG_LEDS_BCM6328 is not set\n# CONFIG_LEDS_BCM6358 is not set\n# CONFIG_LEDS_CR0014114 is not set\n# CONFIG_LEDS_EL15203000 is not set\n# CONFIG_LEDS_LM3530 is not set\n# CONFIG_LEDS_LM3532 is not set\n# CONFIG_LEDS_LM3642 is not set\n# CONFIG_LEDS_LM3692X is not set\n# CONFIG_LEDS_PCA9532 is not set\nCONFIG_LEDS_GPIO=y\n# CONFIG_LEDS_LP3944 is not set\n# CONFIG_LEDS_LP3952 is not set\n# CONFIG_LEDS_LP50XX is not set\n# CONFIG_LEDS_LP55XX_COMMON is not set\n# CONFIG_LEDS_LP8860 is not set\n# CONFIG_LEDS_PCA955X is not set\n# CONFIG_LEDS_PCA963X is not set\n# CONFIG_LEDS_DAC124S085 is not set\n# CONFIG_LEDS_PWM is not set\n# CONFIG_LEDS_REGULATOR is not set\n# CONFIG_LEDS_BD2802 is not set\n# CONFIG_LEDS_LT3593 is not set\nCONFIG_LEDS_ADP5520=y\n# CONFIG_LEDS_TCA6507 is not set\n# CONFIG_LEDS_TLC591XX is not set\n# CONFIG_LEDS_LM355x is not set\n# CONFIG_LEDS_IS31FL319X is not set\n# CONFIG_LEDS_IS31FL32XX is not set\n\n#\n# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)\n#\n# CONFIG_LEDS_BLINKM is not set\n# CONFIG_LEDS_SYSCON is not set\n# CONFIG_LEDS_MLXREG is not set\n# CONFIG_LEDS_USER is not set\n# CONFIG_LEDS_SPI_BYTE is not set\n# CONFIG_LEDS_TI_LMU_COMMON is not set\n\n#\n# Flash and Torch LED drivers\n#\n# CONFIG_LEDS_AAT1290 is not set\nCONFIG_LEDS_AS3645A=y\n# CONFIG_LEDS_KTD2692 is not set\n# CONFIG_LEDS_LM3601X is not set\n# CONFIG_LEDS_RT4505 is not set\n# CONFIG_LEDS_RT8515 is not set\n# CONFIG_LEDS_SGM3140 is not set\n\n#\n# LED Triggers\n#\nCONFIG_LEDS_TRIGGERS=y\nCONFIG_LEDS_TRIGGER_TIMER=y\nCONFIG_LEDS_TRIGGER_ONESHOT=y\n# CONFIG_LEDS_TRIGGER_MTD is not set\nCONFIG_LEDS_TRIGGER_HEARTBEAT=y\n# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set\nCONFIG_LEDS_TRIGGER_CPU=y\n# CONFIG_LEDS_TRIGGER_ACTIVITY is not set\n# CONFIG_LEDS_TRIGGER_GPIO is not set\n# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set\n\n#\n# iptables trigger is under Netfilter config (LED target)\n#\n# CONFIG_LEDS_TRIGGER_TRANSIENT is not set\n# CONFIG_LEDS_TRIGGER_CAMERA is not set\n# CONFIG_LEDS_TRIGGER_PANIC is not set\n# CONFIG_LEDS_TRIGGER_NETDEV is not set\n# CONFIG_LEDS_TRIGGER_PATTERN is not set\n# CONFIG_LEDS_TRIGGER_AUDIO is not set\n# CONFIG_LEDS_TRIGGER_TTY is not set\n# CONFIG_ACCESSIBILITY is not set\n# CONFIG_INFINIBAND is not set\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_RTC_LIB=y\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_HCTOSYS=y\nCONFIG_RTC_HCTOSYS_DEVICE=\"rtc0\"\nCONFIG_RTC_SYSTOHC=y\nCONFIG_RTC_SYSTOHC_DEVICE=\"rtc0\"\n# CONFIG_RTC_DEBUG is not set\nCONFIG_RTC_NVMEM=y\n\n#\n# RTC interfaces\n#\nCONFIG_RTC_INTF_SYSFS=y\nCONFIG_RTC_INTF_PROC=y\nCONFIG_RTC_INTF_DEV=y\n# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set\n# CONFIG_RTC_DRV_TEST is not set\n\n#\n# I2C RTC drivers\n#\n# CONFIG_RTC_DRV_ABB5ZES3 is not set\n# CONFIG_RTC_DRV_ABEOZ9 is not set\n# CONFIG_RTC_DRV_ABX80X is not set\n# CONFIG_RTC_DRV_DS1307 is not set\n# CONFIG_RTC_DRV_DS1374 is not set\n# CONFIG_RTC_DRV_DS1672 is not set\n# CONFIG_RTC_DRV_HYM8563 is not set\n# CONFIG_RTC_DRV_MAX6900 is not set\n# CONFIG_RTC_DRV_RS5C372 is not set\n# CONFIG_RTC_DRV_ISL1208 is not set\n# CONFIG_RTC_DRV_ISL12022 is not set\n# CONFIG_RTC_DRV_ISL12026 is not set\n# CONFIG_RTC_DRV_X1205 is not set\n# CONFIG_RTC_DRV_PCF8523 is not set\n# CONFIG_RTC_DRV_PCF85063 is not set\n# CONFIG_RTC_DRV_PCF85363 is not set\nCONFIG_RTC_DRV_PCF8563=y\n# CONFIG_RTC_DRV_PCF8583 is not set\n# CONFIG_RTC_DRV_M41T80 is not set\n# CONFIG_RTC_DRV_BQ32K is not set\n# CONFIG_RTC_DRV_S35390A is not set\n# CONFIG_RTC_DRV_FM3130 is not set\n# CONFIG_RTC_DRV_RX8010 is not set\n# CONFIG_RTC_DRV_RX8581 is not set\n# CONFIG_RTC_DRV_RX8025 is not set\n# CONFIG_RTC_DRV_EM3027 is not set\n# CONFIG_RTC_DRV_RV3028 is not set\n# CONFIG_RTC_DRV_RV3032 is not set\n# CONFIG_RTC_DRV_RV8803 is not set\n# CONFIG_RTC_DRV_SD3078 is not set\n\n#\n# SPI RTC drivers\n#\n# CONFIG_RTC_DRV_M41T93 is not set\n# CONFIG_RTC_DRV_M41T94 is not set\n# CONFIG_RTC_DRV_DS1302 is not set\n# CONFIG_RTC_DRV_DS1305 is not set\n# CONFIG_RTC_DRV_DS1343 is not set\n# CONFIG_RTC_DRV_DS1347 is not set\n# CONFIG_RTC_DRV_DS1390 is not set\n# CONFIG_RTC_DRV_MAX6916 is not set\n# CONFIG_RTC_DRV_R9701 is not set\n# CONFIG_RTC_DRV_RX4581 is not set\n# CONFIG_RTC_DRV_RS5C348 is not set\n# CONFIG_RTC_DRV_MAX6902 is not set\n# CONFIG_RTC_DRV_PCF2123 is not set\n# CONFIG_RTC_DRV_MCP795 is not set\nCONFIG_RTC_I2C_AND_SPI=y\n\n#\n# SPI and I2C RTC drivers\n#\nCONFIG_RTC_DRV_DS3232=y\nCONFIG_RTC_DRV_DS3232_HWMON=y\n# CONFIG_RTC_DRV_PCF2127 is not set\n# CONFIG_RTC_DRV_RV3029C2 is not set\n# CONFIG_RTC_DRV_RX6110 is not set\n\n#\n# Platform RTC drivers\n#\n# CONFIG_RTC_DRV_CMOS is not set\n# CONFIG_RTC_DRV_DS1286 is not set\n# CONFIG_RTC_DRV_DS1511 is not set\n# CONFIG_RTC_DRV_DS1553 is not set\n# CONFIG_RTC_DRV_DS1685_FAMILY is not set\n# CONFIG_RTC_DRV_DS1742 is not set\n# CONFIG_RTC_DRV_DS2404 is not set\n# CONFIG_RTC_DRV_STK17TA8 is not set\n# CONFIG_RTC_DRV_M48T86 is not set\n# CONFIG_RTC_DRV_M48T35 is not set\n# CONFIG_RTC_DRV_M48T59 is not set\n# CONFIG_RTC_DRV_MSM6242 is not set\n# CONFIG_RTC_DRV_BQ4802 is not set\n# CONFIG_RTC_DRV_RP5C01 is not set\n# CONFIG_RTC_DRV_V3020 is not set\n# CONFIG_RTC_DRV_ZYNQMP is not set\n\n#\n# on-CPU RTC drivers\n#\n# CONFIG_RTC_DRV_PL030 is not set\n# CONFIG_RTC_DRV_PL031 is not set\n# CONFIG_RTC_DRV_CADENCE is not set\n# CONFIG_RTC_DRV_FTRTC010 is not set\n# CONFIG_RTC_DRV_R7301 is not set\n\n#\n# HID Sensor RTC drivers\n#\n# CONFIG_RTC_DRV_GOLDFISH is not set\nCONFIG_DMADEVICES=y\n# CONFIG_DMADEVICES_DEBUG is not set\n\n#\n# DMA Devices\n#\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_VIRTUAL_CHANNELS=y\nCONFIG_DMA_OF=y\n# CONFIG_ALTERA_MSGDMA is not set\n# CONFIG_AMBA_PL08X is not set\nCONFIG_AXI_DMAC=y\n# CONFIG_DW_AXI_DMAC is not set\n# CONFIG_FSL_EDMA is not set\n# CONFIG_FSL_QDMA is not set\n# CONFIG_INTEL_IDMA64 is not set\n# CONFIG_NBPFAXI_DMA is not set\nCONFIG_PL330_DMA=y\nCONFIG_XILINX_DMA=m\nCONFIG_XILINX_ZYNQMP_DMA=m\n# CONFIG_XILINX_ZYNQMP_DPDMA is not set\n# CONFIG_XILINX_FRMBUF is not set\n# CONFIG_QCOM_HIDMA_MGMT is not set\n# CONFIG_QCOM_HIDMA is not set\n# CONFIG_DW_DMAC is not set\n# CONFIG_SF_PDMA is not set\n\n#\n# DMA Clients\n#\n# CONFIG_ASYNC_TX_DMA is not set\n# CONFIG_DMATEST is not set\nCONFIG_XILINX_DMATEST=m\n# CONFIG_XILINX_VDMATEST is not set\n\n#\n# DMABUF options\n#\nCONFIG_SYNC_FILE=y\n# CONFIG_SW_SYNC is not set\n# CONFIG_UDMABUF is not set\n# CONFIG_DMABUF_MOVE_NOTIFY is not set\n# CONFIG_DMABUF_DEBUG is not set\n# CONFIG_DMABUF_SELFTESTS is not set\n# CONFIG_DMABUF_HEAPS is not set\n# CONFIG_DMABUF_SYSFS_STATS is not set\n# end of DMABUF options\n\n# CONFIG_AUXDISPLAY is not set\nCONFIG_UIO=y\nCONFIG_UIO_PDRV_GENIRQ=y\nCONFIG_UIO_DMEM_GENIRQ=y\n# CONFIG_UIO_PRUSS is not set\nCONFIG_UIO_XILINX_APM=y\n# CONFIG_UIO_XILINX_AI_ENGINE is not set\n# CONFIG_VFIO is not set\n# CONFIG_VIRT_DRIVERS is not set\nCONFIG_VIRTIO_MENU=y\n# CONFIG_VIRTIO_MMIO is not set\n# CONFIG_VDPA is not set\nCONFIG_VHOST_MENU=y\n# CONFIG_VHOST_NET is not set\n# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set\n\n#\n# Microsoft Hyper-V guest support\n#\n# end of Microsoft Hyper-V guest support\n\n# CONFIG_GREYBUS is not set\n# CONFIG_COMEDI is not set\nCONFIG_STAGING=y\n\n#\n# IIO staging drivers\n#\n\n#\n# Accelerometers\n#\nCONFIG_ADIS16203=y\nCONFIG_ADIS16240=y\n# end of Accelerometers\n\n#\n# Analog to digital converters\n#\nCONFIG_AD7816=y\nCONFIG_AD7280=y\n# end of Analog to digital converters\n\n#\n# Analog digital bi-direction converters\n#\nCONFIG_ADT7316=y\nCONFIG_ADT7316_SPI=y\nCONFIG_ADT7316_I2C=y\n# end of Analog digital bi-direction converters\n\n#\n# Capacitance to digital converters\n#\nCONFIG_AD7746=y\n# end of Capacitance to digital converters\n\n#\n# Direct Digital Synthesis\n#\nCONFIG_AD9832=y\nCONFIG_AD9834=y\n# end of Direct Digital Synthesis\n\n#\n# Network Analyzer, Impedance Converters\n#\nCONFIG_AD5933=y\n# end of Network Analyzer, Impedance Converters\n\n#\n# Active energy metering IC\n#\nCONFIG_ADE7854=y\nCONFIG_ADE7854_I2C=y\nCONFIG_ADE7854_SPI=y\n# end of Active energy metering IC\n\n#\n# Resolver to digital converters\n#\nCONFIG_AD2S1210=y\n# end of Resolver to digital converters\n# end of IIO staging drivers\n\n# CONFIG_STAGING_MEDIA is not set\n\n#\n# Android\n#\n# end of Android\n\n# CONFIG_STAGING_BOARD is not set\n# CONFIG_LTE_GDM724X is not set\n# CONFIG_GS_FPGABOOT is not set\n# CONFIG_UNISYSSPAR is not set\n# CONFIG_XILINX_APF is not set\nCONFIG_FB_TFT=y\n# CONFIG_FB_TFT_AGM1264K_FL is not set\n# CONFIG_FB_TFT_BD663474 is not set\n# CONFIG_FB_TFT_HX8340BN is not set\n# CONFIG_FB_TFT_HX8347D is not set\n# CONFIG_FB_TFT_HX8353D is not set\n# CONFIG_FB_TFT_HX8357D is not set\n# CONFIG_FB_TFT_ILI9163 is not set\n# CONFIG_FB_TFT_ILI9320 is not set\n# CONFIG_FB_TFT_ILI9325 is not set\n# CONFIG_FB_TFT_ILI9340 is not set\n# CONFIG_FB_TFT_ILI9341 is not set\n# CONFIG_FB_TFT_ILI9481 is not set\n# CONFIG_FB_TFT_ILI9486 is not set\n# CONFIG_FB_TFT_PCD8544 is not set\n# CONFIG_FB_TFT_RA8875 is not set\n# CONFIG_FB_TFT_S6D02A1 is not set\n# CONFIG_FB_TFT_S6D1121 is not set\nCONFIG_FB_TFT_SEPS525=y\n# CONFIG_FB_TFT_SH1106 is not set\n# CONFIG_FB_TFT_SSD1289 is not set\n# CONFIG_FB_TFT_SSD1305 is not set\n# CONFIG_FB_TFT_SSD1306 is not set\n# CONFIG_FB_TFT_SSD1331 is not set\n# CONFIG_FB_TFT_SSD1351 is not set\n# CONFIG_FB_TFT_ST7735R is not set\n# CONFIG_FB_TFT_ST7789V is not set\n# CONFIG_FB_TFT_TINYLCD is not set\n# CONFIG_FB_TFT_TLS8204 is not set\n# CONFIG_FB_TFT_UC1611 is not set\n# CONFIG_FB_TFT_UC1701 is not set\n# CONFIG_FB_TFT_UPD161704 is not set\n# CONFIG_FB_TFT_WATTEROTT is not set\n# CONFIG_KS7010 is not set\n# CONFIG_PI433 is not set\n# CONFIG_XIL_AXIS_FIFO is not set\n# CONFIG_FIELDBUS_DEV is not set\n# CONFIG_WFX is not set\n# CONFIG_XILINX_FCLK is not set\n# CONFIG_XLNX_TSMUX is not set\n# CONFIG_XROE_FRAMER is not set\n# CONFIG_XROE_TRAFFIC_GEN is not set\n# CONFIG_SERIAL_UARTLITE_RS485 is not set\n# CONFIG_XILINX_TSN is not set\n# CONFIG_GOLDFISH is not set\n# CONFIG_CHROME_PLATFORMS is not set\n# CONFIG_MELLANOX_PLATFORM is not set\nCONFIG_HAVE_CLK=y\nCONFIG_HAVE_CLK_PREPARE=y\nCONFIG_COMMON_CLK=y\n\n#\n# Clock driver for ARM Reference designs\n#\n# CONFIG_ICST is not set\n# CONFIG_CLK_SP810 is not set\n# end of Clock driver for ARM Reference designs\n\n# CONFIG_LMK04832 is not set\n# CONFIG_COMMON_CLK_MAX9485 is not set\n# CONFIG_COMMON_CLK_SI5341 is not set\n# CONFIG_COMMON_CLK_SI5351 is not set\nCONFIG_COMMON_CLK_SI514=y\n# CONFIG_COMMON_CLK_SI544 is not set\nCONFIG_COMMON_CLK_SI570=y\n# CONFIG_COMMON_CLK_SI5324 is not set\n# CONFIG_COMMON_CLK_IDT8T49N24X is not set\n# CONFIG_COMMON_CLK_CDCE706 is not set\n# CONFIG_COMMON_CLK_CDCE925 is not set\n# CONFIG_COMMON_CLK_CS2000_CP is not set\nCONFIG_COMMON_CLK_AXI_CLKGEN=y\nCONFIG_COMMON_CLK_ADI=y\n# CONFIG_COMMON_CLK_PWM is not set\n# CONFIG_COMMON_CLK_VC5 is not set\n# CONFIG_COMMON_CLK_VC7 is not set\n# CONFIG_COMMON_CLK_FIXED_MMIO is not set\n# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set\n# CONFIG_COMMON_CLK_XLNX_CLKWZRD_V is not set\n\n#\n# Analog Devices Clock Drivers\n#\nCONFIG_COMMON_CLK_AD9545=y\nCONFIG_COMMON_CLK_AD9545_I2C=y\nCONFIG_COMMON_CLK_AD9545_SPI=y\n# end of Analog Devices Clock Drivers\n\n# CONFIG_XILINX_VCU is not set\n# CONFIG_HWSPINLOCK is not set\n\n#\n# Clock Source drivers\n#\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_CADENCE_TTC_TIMER=y\nCONFIG_ARM_GLOBAL_TIMER=y\nCONFIG_ARM_GT_INITIAL_PRESCALER_VAL=2\nCONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y\n# CONFIG_MICROCHIP_PIT64B is not set\n# end of Clock Source drivers\n\n# CONFIG_MAILBOX is not set\n# CONFIG_IOMMU_SUPPORT is not set\n\n#\n# Remoteproc drivers\n#\n# CONFIG_REMOTEPROC is not set\n# end of Remoteproc drivers\n\n#\n# Rpmsg drivers\n#\n# CONFIG_RPMSG_VIRTIO is not set\n# end of Rpmsg drivers\n\n# CONFIG_SOUNDWIRE is not set\n\n#\n# SOC (System On Chip) specific Drivers\n#\n\n#\n# Amlogic SoC drivers\n#\n# end of Amlogic SoC drivers\n\n#\n# Broadcom SoC drivers\n#\n# CONFIG_SOC_BRCMSTB is not set\n# end of Broadcom SoC drivers\n\n#\n# NXP/Freescale QorIQ SoC drivers\n#\n# CONFIG_QUICC_ENGINE is not set\n# CONFIG_FSL_RCPM is not set\n# end of NXP/Freescale QorIQ SoC drivers\n\n#\n# i.MX SoC drivers\n#\n# end of i.MX SoC drivers\n\n#\n# Enable LiteX SoC Builder specific drivers\n#\n# CONFIG_LITEX_SOC_CONTROLLER is not set\n# end of Enable LiteX SoC Builder specific drivers\n\n#\n# Qualcomm SoC drivers\n#\n# end of Qualcomm SoC drivers\n\n# CONFIG_SOC_TI is not set\n\n#\n# Xilinx SoC drivers\n#\n# end of Xilinx SoC drivers\n# end of SOC (System On Chip) specific Drivers\n\n# CONFIG_PM_DEVFREQ is not set\nCONFIG_EXTCON=y\n\n#\n# Extcon Device Drivers\n#\n# CONFIG_EXTCON_ADC_JACK is not set\n# CONFIG_EXTCON_FSA9480 is not set\n# CONFIG_EXTCON_GPIO is not set\n# CONFIG_EXTCON_MAX3355 is not set\n# CONFIG_EXTCON_PTN5150 is not set\n# CONFIG_EXTCON_RT8973A is not set\n# CONFIG_EXTCON_SM5502 is not set\n# CONFIG_EXTCON_USB_GPIO is not set\n# CONFIG_EXTCON_USBC_TUSB320 is not set\nCONFIG_MEMORY=y\n# CONFIG_ARM_PL172_MPMC is not set\nCONFIG_PL353_SMC=y\nCONFIG_IIO=y\nCONFIG_IIO_BUFFER=y\nCONFIG_IIO_BUFFER_CB=y\nCONFIG_IIO_BUFFER_DMA=y\nCONFIG_IIO_BUFFER_DMAENGINE=y\nCONFIG_IIO_BUFFER_HW_CONSUMER=y\nCONFIG_IIO_KFIFO_BUF=y\nCONFIG_IIO_TRIGGERED_BUFFER=y\nCONFIG_IIO_CONFIGFS=y\nCONFIG_IIO_TRIGGER=y\nCONFIG_IIO_CONSUMERS_PER_TRIGGER=2\nCONFIG_IIO_SW_DEVICE=y\nCONFIG_IIO_SW_TRIGGER=y\nCONFIG_IIO_TRIGGERED_EVENT=y\n\n#\n# Accelerometers\n#\nCONFIG_ADIS16201=y\nCONFIG_ADIS16209=y\nCONFIG_ADXL313=y\nCONFIG_ADXL313_I2C=y\nCONFIG_ADXL313_SPI=y\nCONFIG_ADXL345=y\nCONFIG_ADXL345_I2C=y\nCONFIG_ADXL345_SPI=y\nCONFIG_ADXL355=y\nCONFIG_ADXL355_I2C=y\nCONFIG_ADXL355_SPI=y\nCONFIG_ADXL367=y\nCONFIG_ADXL367_SPI=y\nCONFIG_ADXL367_I2C=y\nCONFIG_ADXL372=y\nCONFIG_ADXL372_SPI=y\nCONFIG_ADXL372_I2C=y\n# CONFIG_BMA180 is not set\n# CONFIG_BMA220 is not set\n# CONFIG_BMA400 is not set\n# CONFIG_BMC150_ACCEL is not set\n# CONFIG_BMI088_ACCEL is not set\n# CONFIG_DA280 is not set\n# CONFIG_DA311 is not set\n# CONFIG_DMARD06 is not set\n# CONFIG_DMARD09 is not set\n# CONFIG_DMARD10 is not set\n# CONFIG_FXLS8962AF_I2C is not set\n# CONFIG_FXLS8962AF_SPI is not set\n# CONFIG_IIO_ST_ACCEL_3AXIS is not set\n# CONFIG_KXSD9 is not set\n# CONFIG_KXCJK1013 is not set\n# CONFIG_MC3230 is not set\n# CONFIG_MMA7455_I2C is not set\n# CONFIG_MMA7455_SPI is not set\n# CONFIG_MMA7660 is not set\n# CONFIG_MMA8452 is not set\n# CONFIG_MMA9551 is not set\n# CONFIG_MMA9553 is not set\n# CONFIG_MXC4005 is not set\n# CONFIG_MXC6255 is not set\n# CONFIG_SCA3000 is not set\n# CONFIG_SCA3300 is not set\n# CONFIG_STK8312 is not set\n# CONFIG_STK8BA50 is not set\n# end of Accelerometers\n\n#\n# Analog to digital converters\n#\nCONFIG_AD_SIGMA_DELTA=y\nCONFIG_AD4134=y\nCONFIG_AD400X=y\nCONFIG_AD4130=y\nCONFIG_AD4630=y\nCONFIG_AD7091R5=y\nCONFIG_AD7124=y\nCONFIG_AD7173=y\nCONFIG_AD7192=y\nCONFIG_AD7266=y\nCONFIG_AD7291=y\nCONFIG_AD7292=y\nCONFIG_AD7298=y\nCONFIG_AD738X=y\nCONFIG_AD7476=y\nCONFIG_AD7606=y\nCONFIG_AD7606_IFACE_PARALLEL=y\nCONFIG_AD7606_IFACE_SPI=y\nCONFIG_AD7766=y\nCONFIG_AD7768=y\nCONFIG_AD7768_1=y\nCONFIG_AD7780=y\nCONFIG_AD7791=y\nCONFIG_AD7793=y\nCONFIG_AD7887=y\nCONFIG_AD7923=y\nCONFIG_AD7949=y\nCONFIG_AD799X=y\nCONFIG_AD9963=y\nCONFIG_ADAQ8092=y\n# CONFIG_ADM1177 is not set\n# CONFIG_ADI_AXI_ADC is not set\nCONFIG_CF_AXI_ADC=y\nCONFIG_AD9081=y\nCONFIG_AD9083=y\nCONFIG_AD9208=y\nCONFIG_AD9361=y\nCONFIG_AD9361_EXT_BAND_CONTROL=y\nCONFIG_AD9371=y\nCONFIG_ADRV9001=y\nCONFIG_ADRV9001_COMMON_VERBOSE=y\nCONFIG_ADRV9001_ARM_VERBOSE=y\nCONFIG_ADRV9001_VALIDATE_PARAMS=y\nCONFIG_ADRV9009=y\nCONFIG_ADRV9025=y\nCONFIG_AD6676=y\nCONFIG_AD9467=y\nCONFIG_AD9680=y\nCONFIG_ADMC=y\nCONFIG_CF_AXI_TDD=y\nCONFIG_AD_PULSAR=y\nCONFIG_AXI_PULSE_CAPTURE=y\nCONFIG_AXI_FMCADC5_SYNC=y\n# CONFIG_CC10001_ADC is not set\n# CONFIG_ENVELOPE_DETECTOR is not set\n# CONFIG_HI8435 is not set\n# CONFIG_HX711 is not set\n# CONFIG_INA2XX_ADC is not set\n# CONFIG_INA260_ADC is not set\nCONFIG_LTC2308=y\nCONFIG_LTC2387=y\nCONFIG_LTC2471=y\nCONFIG_LTC2485=y\nCONFIG_LTC2496=y\nCONFIG_LTC2497=y\n# CONFIG_MAX1027 is not set\n# CONFIG_MAX11100 is not set\n# CONFIG_MAX1118 is not set\nCONFIG_MAX11410=y\n# CONFIG_MAX1241 is not set\n# CONFIG_MAX1363 is not set\n# CONFIG_MAX9611 is not set\n# CONFIG_MCP320X is not set\n# CONFIG_MCP3422 is not set\n# CONFIG_MCP3911 is not set\n# CONFIG_NAU7802 is not set\n# CONFIG_SD_ADC_MODULATOR is not set\n# CONFIG_TI_ADC081C is not set\n# CONFIG_TI_ADC0832 is not set\n# CONFIG_TI_ADC084S021 is not set\n# CONFIG_TI_ADC12138 is not set\n# CONFIG_TI_ADC108S102 is not set\n# CONFIG_TI_ADC128S052 is not set\n# CONFIG_TI_ADC161S626 is not set\n# CONFIG_TI_ADS1015 is not set\n# CONFIG_TI_ADS7950 is not set\n# CONFIG_TI_ADS8344 is not set\n# CONFIG_TI_ADS8688 is not set\n# CONFIG_TI_ADS124S08 is not set\n# CONFIG_TI_ADS131E08 is not set\n# CONFIG_TI_TLC4541 is not set\n# CONFIG_TI_TSC2046 is not set\n# CONFIG_VF610_ADC is not set\nCONFIG_XILINX_XADC=y\n# CONFIG_VERSAL_SYSMON is not set\n# end of Analog to digital converters\n\n#\n# Analog to digital and digital to analog converters\n#\nCONFIG_AD74115=y\nCONFIG_AD74413R=y\nCONFIG_ONE_BIT_ADC_DAC=y\n# end of Analog to digital and digital to analog converters\n\n#\n# Analog Front Ends\n#\n# CONFIG_IIO_RESCALE is not set\n# end of Analog Front Ends\n\n#\n# Amplifiers\n#\nCONFIG_AD8366=y\nCONFIG_AD916X_AMP=y\nCONFIG_ADA4250=y\nCONFIG_HMC425=y\n# end of Amplifiers\n\n#\n# Beamformers\n#\nCONFIG_ADAR1000=y\nCONFIG_ADAR3000=y\n# end of Beamformers\n\n#\n# Capacitance to digital converters\n#\nCONFIG_AD7150=y\n# end of Capacitance to digital converters\n\n#\n# Chemical Sensors\n#\n# CONFIG_ATLAS_PH_SENSOR is not set\n# CONFIG_ATLAS_EZO_SENSOR is not set\n# CONFIG_BME680 is not set\n# CONFIG_CCS811 is not set\n# CONFIG_IAQCORE is not set\n# CONFIG_SCD30_CORE is not set\n# CONFIG_SENSIRION_SGP30 is not set\n# CONFIG_SENSIRION_SGP40 is not set\n# CONFIG_SPS30_I2C is not set\n# CONFIG_VZ89X is not set\n# end of Chemical Sensors\n\n#\n# Hid Sensor IIO Common\n#\n# end of Hid Sensor IIO Common\n\n#\n# IIO SCMI Sensors\n#\n# end of IIO SCMI Sensors\n\n#\n# SSP Sensor Common\n#\n# CONFIG_IIO_SSP_SENSORHUB is not set\n# end of SSP Sensor Common\n\n#\n# Digital to analog converters\n#\nCONFIG_AD3552R=y\nCONFIG_AD5064=y\nCONFIG_AD5270=y\nCONFIG_AD5360=y\nCONFIG_AD5380=y\nCONFIG_AD5421=y\nCONFIG_AD5446=y\nCONFIG_AD5449=y\nCONFIG_AD5592R_BASE=y\nCONFIG_AD5592R=y\nCONFIG_AD5593R=y\nCONFIG_AD5504=y\nCONFIG_AD5624R_SPI=y\nCONFIG_LTC2688=y\nCONFIG_AD5686=y\nCONFIG_AD5686_SPI=y\nCONFIG_AD5696_I2C=y\nCONFIG_AD5755=y\nCONFIG_AD5758=y\nCONFIG_AD5761=y\nCONFIG_AD5764=y\nCONFIG_AD5766=y\nCONFIG_AD5770R=y\nCONFIG_AD5791=y\nCONFIG_AD7293=y\nCONFIG_AD7303=y\nCONFIG_AD8801=y\n# CONFIG_DPOT_DAC is not set\n# CONFIG_DS4424 is not set\nCONFIG_LTC1660=y\nCONFIG_LTC2632=y\n# CONFIG_M62332 is not set\n# CONFIG_MAX517 is not set\n# CONFIG_MAX5821 is not set\n# CONFIG_MCP4725 is not set\n# CONFIG_MCP4922 is not set\n# CONFIG_TI_DAC082S085 is not set\n# CONFIG_TI_DAC5571 is not set\n# CONFIG_TI_DAC7311 is not set\n# CONFIG_TI_DAC7612 is not set\n# CONFIG_VF610_DAC is not set\n# end of Digital to analog converters\n\n#\n# IIO dummy driver\n#\n# CONFIG_IIO_SIMPLE_DUMMY is not set\n# end of IIO dummy driver\n\n#\n# Filters\n#\nCONFIG_ADMV8818=y\n# end of Filters\n\n#\n# Frequency Synthesizers DDS/PLL\n#\n\n#\n# Clock Generator/Distribution\n#\nCONFIG_AD9508=y\nCONFIG_AD9523=y\nCONFIG_AD9528=y\nCONFIG_AD9548=y\nCONFIG_AD9517=y\nCONFIG_ADMV1013=y\nCONFIG_ADMV1014=y\nCONFIG_ADMV4420=y\nCONFIG_ADRF6780=y\nCONFIG_HMC7044=y\nCONFIG_LTC6952=y\n# end of Clock Generator/Distribution\n\n#\n# Direct Digital Synthesis\n#\nCONFIG_CF_AXI_DDS=y\nCONFIG_CF_AXI_DDS_AD9122=y\nCONFIG_CF_AXI_DDS_AD9144=y\nCONFIG_CF_AXI_DDS_AD9162=y\nCONFIG_CF_AXI_DDS_AD9172=y\nCONFIG_CF_AXI_DDS_AD9739A=y\nCONFIG_CF_AXI_DDS_AD9783=y\nCONFIG_M2K_DAC=y\n# end of Direct Digital Synthesis\n\n#\n# Phase-Locked Loop (PLL) frequency synthesizers\n#\nCONFIG_ADF4159=y\nCONFIG_ADF4350=y\nCONFIG_ADF4360=y\nCONFIG_ADF4371=y\nCONFIG_ADF4377=y\nCONFIG_ADF5355=y\n# end of Phase-Locked Loop (PLL) frequency synthesizers\n\n#\n# RF Font-Ends\n#\nCONFIG_ADL5960=y\n# end of RF Font-Ends\n# end of Frequency Synthesizers DDS/PLL\n\n#\n# Digital gyroscope sensors\n#\nCONFIG_ADIS16080=y\nCONFIG_ADIS16130=y\nCONFIG_ADIS16136=y\nCONFIG_ADIS16260=y\nCONFIG_ADXRS290=y\nCONFIG_ADXRS450=y\n# CONFIG_BMG160 is not set\n# CONFIG_FXAS21002C is not set\n# CONFIG_MPU3050_I2C is not set\n# CONFIG_IIO_ST_GYRO_3AXIS is not set\n# CONFIG_ITG3200 is not set\n# end of Digital gyroscope sensors\n\n#\n# Health Sensors\n#\n\n#\n# Heart Rate Monitors\n#\n# CONFIG_AFE4403 is not set\n# CONFIG_AFE4404 is not set\n# CONFIG_MAX30100 is not set\n# CONFIG_MAX30102 is not set\n# end of Heart Rate Monitors\n# end of Health Sensors\n\n#\n# Humidity sensors\n#\n# CONFIG_AM2315 is not set\n# CONFIG_DHT11 is not set\n# CONFIG_HDC100X is not set\n# CONFIG_HDC2010 is not set\n# CONFIG_HTS221 is not set\n# CONFIG_HTU21 is not set\n# CONFIG_SI7005 is not set\n# CONFIG_SI7020 is not set\n# end of Humidity sensors\n\n#\n# Inertial measurement units\n#\nCONFIG_ADIS16400=y\nCONFIG_ADIS16460=y\nCONFIG_ADIS16475=y\nCONFIG_ADIS16480=y\n# CONFIG_BMI160_I2C is not set\n# CONFIG_BMI160_SPI is not set\n# CONFIG_FXOS8700_I2C is not set\n# CONFIG_FXOS8700_SPI is not set\n# CONFIG_KMX61 is not set\n# CONFIG_INV_ICM42600_I2C is not set\n# CONFIG_INV_ICM42600_SPI is not set\n# CONFIG_INV_MPU6050_I2C is not set\n# CONFIG_INV_MPU6050_SPI is not set\n# CONFIG_IIO_ST_LSM6DSX is not set\n# CONFIG_IIO_ST_LSM9DS0 is not set\n# end of Inertial measurement units\n\nCONFIG_IIO_ADIS_LIB=y\nCONFIG_IIO_ADIS_LIB_BUFFER=y\n# CONFIG_ALTERA_ARRIA10_JESD204_PHY is not set\nCONFIG_AXI_ADXCVR=y\nCONFIG_AXI_JESD204B=y\nCONFIG_AXI_JESD204_TX=y\nCONFIG_AXI_JESD204_RX=y\nCONFIG_XILINX_TRANSCEIVER=y\nCONFIG_ADI_IIO_FAKEDEV=y\n\n#\n# Light sensors\n#\n# CONFIG_ADJD_S311 is not set\nCONFIG_ADUX1020=y\n# CONFIG_AL3010 is not set\n# CONFIG_AL3320A is not set\n# CONFIG_APDS9300 is not set\n# CONFIG_APDS9960 is not set\n# CONFIG_AS73211 is not set\n# CONFIG_BH1750 is not set\n# CONFIG_BH1780 is not set\n# CONFIG_CM32181 is not set\n# CONFIG_CM3232 is not set\n# CONFIG_CM3323 is not set\n# CONFIG_CM3605 is not set\n# CONFIG_CM36651 is not set\n# CONFIG_GP2AP002 is not set\n# CONFIG_GP2AP020A00F is not set\n# CONFIG_SENSORS_ISL29018 is not set\n# CONFIG_SENSORS_ISL29028 is not set\n# CONFIG_ISL29125 is not set\n# CONFIG_JSA1212 is not set\n# CONFIG_RPR0521 is not set\n# CONFIG_LTR501 is not set\n# CONFIG_LV0104CS is not set\n# CONFIG_MAX44000 is not set\n# CONFIG_MAX44009 is not set\n# CONFIG_NOA1305 is not set\n# CONFIG_OPT3001 is not set\n# CONFIG_PA12203001 is not set\n# CONFIG_SI1133 is not set\n# CONFIG_SI1145 is not set\n# CONFIG_STK3310 is not set\n# CONFIG_ST_UVIS25 is not set\n# CONFIG_TCS3414 is not set\n# CONFIG_TCS3472 is not set\n# CONFIG_SENSORS_TSL2563 is not set\n# CONFIG_TSL2583 is not set\n# CONFIG_TSL2591 is not set\n# CONFIG_TSL2772 is not set\n# CONFIG_TSL4531 is not set\n# CONFIG_US5182D is not set\n# CONFIG_VCNL4000 is not set\n# CONFIG_VCNL4035 is not set\n# CONFIG_VEML6030 is not set\n# CONFIG_VEML6070 is not set\n# CONFIG_VL6180 is not set\n# CONFIG_ZOPT2201 is not set\n# end of Light sensors\n\n#\n# Logic Analyzers\n#\nCONFIG_M2K_LOGIC_ANALYZER=y\n# end of Logic Analyzers\n\n#\n# Magnetometer sensors\n#\n# CONFIG_AK8974 is not set\n# CONFIG_AK8975 is not set\n# CONFIG_AK09911 is not set\n# CONFIG_BMC150_MAGN_I2C is not set\n# CONFIG_BMC150_MAGN_SPI is not set\n# CONFIG_MAG3110 is not set\n# CONFIG_MMC35240 is not set\n# CONFIG_IIO_ST_MAGN_3AXIS is not set\n# CONFIG_SENSORS_HMC5843_I2C is not set\n# CONFIG_SENSORS_HMC5843_SPI is not set\n# CONFIG_SENSORS_RM3100_I2C is not set\n# CONFIG_SENSORS_RM3100_SPI is not set\n# CONFIG_YAMAHA_YAS530 is not set\n# end of Magnetometer sensors\n\n#\n# Multiplexers\n#\n# CONFIG_IIO_MUX is not set\nCONFIG_IIO_GEN_MUX=y\n# end of Multiplexers\n\n#\n# IIO Regmap Access Drivers\n#\nCONFIG_IIO_REGMAP=y\nCONFIG_IIO_REGMAP_I2C=y\nCONFIG_IIO_REGMAP_SPI=y\n# end of IIO Regmap Access Drivers\n\n#\n# Inclinometer sensors\n#\n# end of Inclinometer sensors\n\n#\n# Triggers - standalone\n#\nCONFIG_IIO_HRTIMER_TRIGGER=y\nCONFIG_IIO_INTERRUPT_TRIGGER=y\nCONFIG_IIO_TIGHTLOOP_TRIGGER=y\nCONFIG_IIO_SYSFS_TRIGGER=y\n# end of Triggers - standalone\n\n#\n# Linear and angular position sensors\n#\n# end of Linear and angular position sensors\n\n#\n# Digital potentiometers\n#\nCONFIG_AD5110=y\nCONFIG_AD5272=y\n# CONFIG_DS1803 is not set\n# CONFIG_MAX5432 is not set\n# CONFIG_MAX5481 is not set\n# CONFIG_MAX5487 is not set\n# CONFIG_MCP4018 is not set\n# CONFIG_MCP4131 is not set\n# CONFIG_MCP4531 is not set\n# CONFIG_MCP41010 is not set\n# CONFIG_TPL0102 is not set\n# end of Digital potentiometers\n\n#\n# Digital potentiostats\n#\n# CONFIG_LMP91000 is not set\n# end of Digital potentiostats\n\n#\n# Pressure sensors\n#\n# CONFIG_ABP060MG is not set\n# CONFIG_BMP280 is not set\n# CONFIG_DLHL60D is not set\n# CONFIG_DPS310 is not set\n# CONFIG_HP03 is not set\n# CONFIG_ICP10100 is not set\n# CONFIG_MPL115_I2C is not set\n# CONFIG_MPL115_SPI is not set\n# CONFIG_MPL3115 is not set\n# CONFIG_MS5611 is not set\n# CONFIG_MS5637 is not set\n# CONFIG_IIO_ST_PRESS is not set\n# CONFIG_T5403 is not set\n# CONFIG_HP206C is not set\n# CONFIG_ZPA2326 is not set\n# end of Pressure sensors\n\n#\n# Lightning sensors\n#\n# CONFIG_AS3935 is not set\n# end of Lightning sensors\n\n#\n# Proximity and distance sensors\n#\n# CONFIG_ISL29501 is not set\n# CONFIG_LIDAR_LITE_V2 is not set\n# CONFIG_MB1232 is not set\n# CONFIG_PING is not set\n# CONFIG_RFD77402 is not set\n# CONFIG_SRF04 is not set\n# CONFIG_SX9310 is not set\n# CONFIG_SX9500 is not set\n# CONFIG_SRF08 is not set\n# CONFIG_VCNL3020 is not set\n# CONFIG_VL53L0X_I2C is not set\n# end of Proximity and distance sensors\n\n#\n# Resolver to digital converters\n#\nCONFIG_AD2S90=y\nCONFIG_AD2S1200=y\n# end of Resolver to digital converters\n\n#\n# Temperature sensors\n#\nCONFIG_LTC2983=y\n# CONFIG_MAXIM_THERMOCOUPLE is not set\n# CONFIG_MLX90614 is not set\n# CONFIG_MLX90632 is not set\n# CONFIG_TMP006 is not set\n# CONFIG_TMP007 is not set\n# CONFIG_TMP117 is not set\n# CONFIG_TSYS01 is not set\n# CONFIG_TSYS02D is not set\n# CONFIG_MAX31856 is not set\nCONFIG_MAX31865=y\n# end of Temperature sensors\n\nCONFIG_JESD204=y\nCONFIG_JESD204_TOP_DEVICE=y\nCONFIG_PWM=y\nCONFIG_PWM_SYSFS=y\n# CONFIG_PWM_DEBUG is not set\n# CONFIG_PWM_ATMEL_TCB is not set\nCONFIG_PWM_AXI_PWMGEN=y\n# CONFIG_PWM_FSL_FTM is not set\n# CONFIG_PWM_PCA9685 is not set\n# CONFIG_PWM_CADENCE is not set\n\n#\n# IRQ chip support\n#\nCONFIG_IRQCHIP=y\nCONFIG_ARM_GIC=y\nCONFIG_ARM_GIC_MAX_NR=1\n# CONFIG_AL_FIC is not set\n# CONFIG_XILINX_INTC is not set\n# end of IRQ chip support\n\n# CONFIG_IPACK_BUS is not set\nCONFIG_ARCH_HAS_RESET_CONTROLLER=y\nCONFIG_RESET_CONTROLLER=y\n# CONFIG_RESET_TI_SYSCON is not set\nCONFIG_RESET_ZYNQ=y\n\n#\n# PHY Subsystem\n#\n# CONFIG_GENERIC_PHY is not set\n# CONFIG_PHY_CAN_TRANSCEIVER is not set\n# CONFIG_BCM_KONA_USB2_PHY is not set\n# CONFIG_PHY_CADENCE_TORRENT is not set\n# CONFIG_PHY_CADENCE_DPHY is not set\n# CONFIG_PHY_CADENCE_SIERRA is not set\n# CONFIG_PHY_CADENCE_SALVO is not set\n# CONFIG_PHY_FSL_IMX8MQ_USB is not set\n# CONFIG_PHY_MIXEL_MIPI_DPHY is not set\n# CONFIG_PHY_PXA_28NM_HSIC is not set\n# CONFIG_PHY_PXA_28NM_USB2 is not set\n# CONFIG_PHY_CPCAP_USB is not set\n# CONFIG_PHY_MAPPHONE_MDM6600 is not set\n# CONFIG_PHY_OCELOT_SERDES is not set\n# CONFIG_PHY_QCOM_USB_HS is not set\n# CONFIG_PHY_QCOM_USB_HSIC is not set\n# CONFIG_PHY_SAMSUNG_USB2 is not set\n# CONFIG_PHY_TUSB1210 is not set\n# end of PHY Subsystem\n\n# CONFIG_POWERCAP is not set\n# CONFIG_MCB is not set\n\n#\n# Performance monitor support\n#\n# CONFIG_ARM_CCI_PMU is not set\n# CONFIG_ARM_CCN is not set\nCONFIG_ARM_PMU=y\n# end of Performance monitor support\n\n# CONFIG_RAS is not set\n\n#\n# Android\n#\n# CONFIG_ANDROID is not set\n# end of Android\n\n# CONFIG_DAX is not set\nCONFIG_NVMEM=y\nCONFIG_NVMEM_SYSFS=y\nCONFIG_NVMEM_AXI_SYSID=y\n# CONFIG_NVMEM_RMEM is not set\n\n#\n# HW tracing support\n#\n# CONFIG_STM is not set\n# CONFIG_INTEL_TH is not set\n# end of HW tracing support\n\nCONFIG_FPGA=y\n# CONFIG_FPGA_MGR_DEBUG_FS is not set\n# CONFIG_ALTERA_PR_IP_CORE is not set\n# CONFIG_FPGA_MGR_ALTERA_PS_SPI is not set\nCONFIG_FPGA_MGR_ZYNQ_FPGA=y\n# CONFIG_FPGA_MGR_XILINX_SPI is not set\n# CONFIG_FPGA_MGR_ICE40_SPI is not set\n# CONFIG_FPGA_MGR_MACHXO2_SPI is not set\nCONFIG_FPGA_MGR_ZYNQ_AFI_FPGA=y\nCONFIG_FPGA_BRIDGE=y\n# CONFIG_ALTERA_FREEZE_BRIDGE is not set\n# CONFIG_XILINX_PR_DECOUPLER is not set\nCONFIG_FPGA_REGION=y\nCONFIG_OF_FPGA_REGION=y\n# CONFIG_FPGA_DFL is not set\n# CONFIG_FSI is not set\n# CONFIG_TEE is not set\nCONFIG_MULTIPLEXER=y\n\n#\n# Multiplexer drivers\n#\nCONFIG_MUX_ADG792A=y\nCONFIG_MUX_ADGS1408=y\nCONFIG_MUX_GPIO=y\nCONFIG_MUX_MMIO=y\n# end of Multiplexer drivers\n\n# CONFIG_SIOX is not set\n# CONFIG_SLIMBUS is not set\n# CONFIG_INTERCONNECT is not set\n# CONFIG_COUNTER is not set\n# CONFIG_MOST is not set\n# end of Device Drivers\n\n#\n# File systems\n#\nCONFIG_DCACHE_WORD_ACCESS=y\n# CONFIG_VALIDATE_FS_PARSER is not set\nCONFIG_FS_IOMAP=y\n# CONFIG_EXT2_FS is not set\n# CONFIG_EXT3_FS is not set\nCONFIG_EXT4_FS=y\nCONFIG_EXT4_USE_FOR_EXT2=y\nCONFIG_EXT4_FS_POSIX_ACL=y\n# CONFIG_EXT4_FS_SECURITY is not set\n# CONFIG_EXT4_DEBUG is not set\nCONFIG_JBD2=y\n# CONFIG_JBD2_DEBUG is not set\nCONFIG_FS_MBCACHE=y\n# CONFIG_REISERFS_FS is not set\n# CONFIG_JFS_FS is not set\n# CONFIG_XFS_FS is not set\n# CONFIG_GFS2_FS is not set\n# CONFIG_OCFS2_FS is not set\n# CONFIG_BTRFS_FS is not set\n# CONFIG_NILFS2_FS is not set\n# CONFIG_F2FS_FS is not set\nCONFIG_FS_POSIX_ACL=y\nCONFIG_EXPORTFS=y\n# CONFIG_EXPORTFS_BLOCK_OPS is not set\nCONFIG_FILE_LOCKING=y\n# CONFIG_FS_ENCRYPTION is not set\n# CONFIG_FS_VERITY is not set\nCONFIG_FSNOTIFY=y\n# CONFIG_DNOTIFY is not set\nCONFIG_INOTIFY_USER=y\n# CONFIG_FANOTIFY is not set\n# CONFIG_QUOTA is not set\nCONFIG_AUTOFS4_FS=y\nCONFIG_AUTOFS_FS=y\nCONFIG_FUSE_FS=y\n# CONFIG_CUSE is not set\n# CONFIG_VIRTIO_FS is not set\n# CONFIG_OVERLAY_FS is not set\n\n#\n# Caches\n#\n# CONFIG_FSCACHE is not set\n# end of Caches\n\n#\n# CD-ROM/DVD Filesystems\n#\n# CONFIG_ISO9660_FS is not set\n# CONFIG_UDF_FS is not set\n# end of CD-ROM/DVD Filesystems\n\n#\n# DOS/FAT/EXFAT/NT Filesystems\n#\nCONFIG_FAT_FS=y\nCONFIG_MSDOS_FS=y\nCONFIG_VFAT_FS=y\nCONFIG_FAT_DEFAULT_CODEPAGE=437\nCONFIG_FAT_DEFAULT_IOCHARSET=\"iso8859-1\"\n# CONFIG_FAT_DEFAULT_UTF8 is not set\n# CONFIG_EXFAT_FS is not set\n# CONFIG_NTFS_FS is not set\n# CONFIG_NTFS3_FS is not set\n# end of DOS/FAT/EXFAT/NT Filesystems\n\n#\n# Pseudo filesystems\n#\nCONFIG_PROC_FS=y\nCONFIG_PROC_SYSCTL=y\nCONFIG_PROC_PAGE_MONITOR=y\n# CONFIG_PROC_CHILDREN is not set\nCONFIG_KERNFS=y\nCONFIG_SYSFS=y\nCONFIG_TMPFS=y\nCONFIG_TMPFS_POSIX_ACL=y\nCONFIG_TMPFS_XATTR=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_CONFIGFS_FS=y\n# end of Pseudo filesystems\n\nCONFIG_MISC_FILESYSTEMS=y\n# CONFIG_ORANGEFS_FS is not set\n# CONFIG_ADFS_FS is not set\n# CONFIG_AFFS_FS is not set\n# CONFIG_ECRYPT_FS is not set\n# CONFIG_HFS_FS is not set\n# CONFIG_HFSPLUS_FS is not set\n# CONFIG_BEFS_FS is not set\n# CONFIG_BFS_FS is not set\n# CONFIG_EFS_FS is not set\n# CONFIG_JFFS2_FS is not set\n# CONFIG_CRAMFS is not set\n# CONFIG_SQUASHFS is not set\n# CONFIG_VXFS_FS is not set\n# CONFIG_MINIX_FS is not set\n# CONFIG_OMFS_FS is not set\n# CONFIG_HPFS_FS is not set\n# CONFIG_QNX4FS_FS is not set\n# CONFIG_QNX6FS_FS is not set\n# CONFIG_ROMFS_FS is not set\n# CONFIG_PSTORE is not set\n# CONFIG_SYSV_FS is not set\n# CONFIG_UFS_FS is not set\n# CONFIG_EROFS_FS is not set\nCONFIG_NETWORK_FILESYSTEMS=y\nCONFIG_NFS_FS=y\nCONFIG_NFS_V2=y\nCONFIG_NFS_V3=y\nCONFIG_NFS_V3_ACL=y\nCONFIG_NFS_V4=y\n# CONFIG_NFS_SWAP is not set\nCONFIG_NFS_V4_1=y\nCONFIG_NFS_V4_2=y\nCONFIG_PNFS_FILE_LAYOUT=y\nCONFIG_PNFS_FLEXFILE_LAYOUT=y\nCONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN=\"kernel.org\"\n# CONFIG_NFS_V4_1_MIGRATION is not set\nCONFIG_ROOT_NFS=y\n# CONFIG_NFS_USE_LEGACY_DNS is not set\nCONFIG_NFS_USE_KERNEL_DNS=y\nCONFIG_NFS_DISABLE_UDP_SUPPORT=y\n# CONFIG_NFS_V4_2_READ_PLUS is not set\n# CONFIG_NFSD is not set\nCONFIG_GRACE_PERIOD=y\nCONFIG_LOCKD=y\nCONFIG_LOCKD_V4=y\nCONFIG_NFS_ACL_SUPPORT=y\nCONFIG_NFS_COMMON=y\nCONFIG_NFS_V4_2_SSC_HELPER=y\nCONFIG_SUNRPC=y\nCONFIG_SUNRPC_GSS=y\nCONFIG_SUNRPC_BACKCHANNEL=y\n# CONFIG_SUNRPC_DEBUG is not set\n# CONFIG_CEPH_FS is not set\n# CONFIG_CIFS is not set\n# CONFIG_SMB_SERVER is not set\n# CONFIG_CODA_FS is not set\n# CONFIG_AFS_FS is not set\nCONFIG_NLS=y\nCONFIG_NLS_DEFAULT=\"iso8859-1\"\nCONFIG_NLS_CODEPAGE_437=y\n# CONFIG_NLS_CODEPAGE_737 is not set\n# CONFIG_NLS_CODEPAGE_775 is not set\n# CONFIG_NLS_CODEPAGE_850 is not set\n# CONFIG_NLS_CODEPAGE_852 is not set\n# CONFIG_NLS_CODEPAGE_855 is not set\n# CONFIG_NLS_CODEPAGE_857 is not set\n# CONFIG_NLS_CODEPAGE_860 is not set\n# CONFIG_NLS_CODEPAGE_861 is not set\n# CONFIG_NLS_CODEPAGE_862 is not set\n# CONFIG_NLS_CODEPAGE_863 is not set\n# CONFIG_NLS_CODEPAGE_864 is not set\n# CONFIG_NLS_CODEPAGE_865 is not set\n# CONFIG_NLS_CODEPAGE_866 is not set\n# CONFIG_NLS_CODEPAGE_869 is not set\n# CONFIG_NLS_CODEPAGE_936 is not set\n# CONFIG_NLS_CODEPAGE_950 is not set\n# CONFIG_NLS_CODEPAGE_932 is not set\n# CONFIG_NLS_CODEPAGE_949 is not set\n# CONFIG_NLS_CODEPAGE_874 is not set\n# CONFIG_NLS_ISO8859_8 is not set\n# CONFIG_NLS_CODEPAGE_1250 is not set\n# CONFIG_NLS_CODEPAGE_1251 is not set\nCONFIG_NLS_ASCII=y\nCONFIG_NLS_ISO8859_1=y\n# CONFIG_NLS_ISO8859_2 is not set\n# CONFIG_NLS_ISO8859_3 is not set\n# CONFIG_NLS_ISO8859_4 is not set\n# CONFIG_NLS_ISO8859_5 is not set\n# CONFIG_NLS_ISO8859_6 is not set\n# CONFIG_NLS_ISO8859_7 is not set\n# CONFIG_NLS_ISO8859_9 is not set\n# CONFIG_NLS_ISO8859_13 is not set\n# CONFIG_NLS_ISO8859_14 is not set\n# CONFIG_NLS_ISO8859_15 is not set\n# CONFIG_NLS_KOI8_R is not set\n# CONFIG_NLS_KOI8_U is not set\n# CONFIG_NLS_MAC_ROMAN is not set\n# CONFIG_NLS_MAC_CELTIC is not set\n# CONFIG_NLS_MAC_CENTEURO is not set\n# CONFIG_NLS_MAC_CROATIAN is not set\n# CONFIG_NLS_MAC_CYRILLIC is not set\n# CONFIG_NLS_MAC_GAELIC is not set\n# CONFIG_NLS_MAC_GREEK is not set\n# CONFIG_NLS_MAC_ICELAND is not set\n# CONFIG_NLS_MAC_INUIT is not set\n# CONFIG_NLS_MAC_ROMANIAN is not set\n# CONFIG_NLS_MAC_TURKISH is not set\n# CONFIG_NLS_UTF8 is not set\n# CONFIG_DLM is not set\n# CONFIG_UNICODE is not set\nCONFIG_IO_WQ=y\n# end of File systems\n\n#\n# Security options\n#\nCONFIG_KEYS=y\n# CONFIG_KEYS_REQUEST_CACHE is not set\n# CONFIG_PERSISTENT_KEYRINGS is not set\n# CONFIG_ENCRYPTED_KEYS is not set\n# CONFIG_KEY_DH_OPERATIONS is not set\n# CONFIG_SECURITY_DMESG_RESTRICT is not set\n# CONFIG_SECURITY is not set\n# CONFIG_SECURITYFS is not set\nCONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y\n# CONFIG_HARDENED_USERCOPY is not set\n# CONFIG_FORTIFY_SOURCE is not set\n# CONFIG_STATIC_USERMODEHELPER is not set\nCONFIG_DEFAULT_SECURITY_DAC=y\nCONFIG_LSM=\"landlock,lockdown,yama,loadpin,safesetid,integrity,bpf\"\n\n#\n# Kernel hardening options\n#\n\n#\n# Memory initialization\n#\nCONFIG_INIT_STACK_NONE=y\n# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set\n# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set\n# end of Memory initialization\n# end of Kernel hardening options\n# end of Security options\n\nCONFIG_CRYPTO=y\n\n#\n# Crypto core or helper\n#\nCONFIG_CRYPTO_ALGAPI=y\nCONFIG_CRYPTO_ALGAPI2=y\nCONFIG_CRYPTO_AEAD=y\nCONFIG_CRYPTO_AEAD2=y\nCONFIG_CRYPTO_SKCIPHER=y\nCONFIG_CRYPTO_SKCIPHER2=y\nCONFIG_CRYPTO_HASH=y\nCONFIG_CRYPTO_HASH2=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_AKCIPHER2=y\nCONFIG_CRYPTO_AKCIPHER=y\nCONFIG_CRYPTO_KPP2=y\nCONFIG_CRYPTO_ACOMP2=y\nCONFIG_CRYPTO_MANAGER=y\nCONFIG_CRYPTO_MANAGER2=y\n# CONFIG_CRYPTO_USER is not set\nCONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y\nCONFIG_CRYPTO_GF128MUL=y\nCONFIG_CRYPTO_NULL=y\nCONFIG_CRYPTO_NULL2=y\n# CONFIG_CRYPTO_PCRYPT is not set\n# CONFIG_CRYPTO_CRYPTD is not set\nCONFIG_CRYPTO_AUTHENC=y\n# CONFIG_CRYPTO_TEST is not set\n\n#\n# Public-key cryptography\n#\nCONFIG_CRYPTO_RSA=y\n# CONFIG_CRYPTO_DH is not set\n# CONFIG_CRYPTO_ECDH is not set\n# CONFIG_CRYPTO_ECDSA is not set\n# CONFIG_CRYPTO_ECRDSA is not set\n# CONFIG_CRYPTO_SM2 is not set\n# CONFIG_CRYPTO_CURVE25519 is not set\n\n#\n# Authenticated Encryption with Associated Data\n#\nCONFIG_CRYPTO_CCM=y\nCONFIG_CRYPTO_GCM=y\n# CONFIG_CRYPTO_CHACHA20POLY1305 is not set\n# CONFIG_CRYPTO_AEGIS128 is not set\n# CONFIG_CRYPTO_SEQIV is not set\n# CONFIG_CRYPTO_ECHAINIV is not set\n\n#\n# Block modes\n#\n# CONFIG_CRYPTO_CBC is not set\n# CONFIG_CRYPTO_CFB is not set\nCONFIG_CRYPTO_CTR=y\n# CONFIG_CRYPTO_CTS is not set\n# CONFIG_CRYPTO_ECB is not set\n# CONFIG_CRYPTO_LRW is not set\n# CONFIG_CRYPTO_OFB is not set\n# CONFIG_CRYPTO_PCBC is not set\n# CONFIG_CRYPTO_XTS is not set\n# CONFIG_CRYPTO_KEYWRAP is not set\n# CONFIG_CRYPTO_ADIANTUM is not set\n# CONFIG_CRYPTO_ESSIV is not set\n\n#\n# Hash modes\n#\nCONFIG_CRYPTO_CMAC=y\n# CONFIG_CRYPTO_HMAC is not set\n# CONFIG_CRYPTO_XCBC is not set\n# CONFIG_CRYPTO_VMAC is not set\n\n#\n# Digest\n#\nCONFIG_CRYPTO_CRC32C=y\n# CONFIG_CRYPTO_CRC32 is not set\n# CONFIG_CRYPTO_XXHASH is not set\n# CONFIG_CRYPTO_BLAKE2B is not set\n# CONFIG_CRYPTO_BLAKE2S is not set\n# CONFIG_CRYPTO_CRCT10DIF is not set\nCONFIG_CRYPTO_GHASH=y\n# CONFIG_CRYPTO_POLY1305 is not set\n# CONFIG_CRYPTO_MD4 is not set\n# CONFIG_CRYPTO_MD5 is not set\n# CONFIG_CRYPTO_MICHAEL_MIC is not set\n# CONFIG_CRYPTO_RMD160 is not set\n# CONFIG_CRYPTO_SHA1 is not set\nCONFIG_CRYPTO_SHA256=y\n# CONFIG_CRYPTO_SHA512 is not set\n# CONFIG_CRYPTO_SHA3 is not set\n# CONFIG_CRYPTO_SM3 is not set\n# CONFIG_CRYPTO_STREEBOG is not set\n# CONFIG_CRYPTO_WP512 is not set\n\n#\n# Ciphers\n#\nCONFIG_CRYPTO_AES=y\n# CONFIG_CRYPTO_AES_TI is not set\n# CONFIG_CRYPTO_BLOWFISH is not set\n# CONFIG_CRYPTO_CAMELLIA is not set\n# CONFIG_CRYPTO_CAST5 is not set\n# CONFIG_CRYPTO_CAST6 is not set\n# CONFIG_CRYPTO_DES is not set\n# CONFIG_CRYPTO_FCRYPT is not set\n# CONFIG_CRYPTO_CHACHA20 is not set\n# CONFIG_CRYPTO_SERPENT is not set\n# CONFIG_CRYPTO_SM4 is not set\n# CONFIG_CRYPTO_TWOFISH is not set\n\n#\n# Compression\n#\n# CONFIG_CRYPTO_DEFLATE is not set\n# CONFIG_CRYPTO_LZO is not set\n# CONFIG_CRYPTO_842 is not set\n# CONFIG_CRYPTO_LZ4 is not set\n# CONFIG_CRYPTO_LZ4HC is not set\n# CONFIG_CRYPTO_ZSTD is not set\n\n#\n# Random Number Generation\n#\n# CONFIG_CRYPTO_ANSI_CPRNG is not set\n# CONFIG_CRYPTO_DRBG_MENU is not set\n# CONFIG_CRYPTO_JITTERENTROPY is not set\n# CONFIG_CRYPTO_USER_API_HASH is not set\n# CONFIG_CRYPTO_USER_API_SKCIPHER is not set\n# CONFIG_CRYPTO_USER_API_RNG is not set\n# CONFIG_CRYPTO_USER_API_AEAD is not set\nCONFIG_CRYPTO_HASH_INFO=y\n\n#\n# Crypto library routines\n#\nCONFIG_CRYPTO_LIB_AES=y\nCONFIG_CRYPTO_LIB_ARC4=y\n# CONFIG_CRYPTO_LIB_BLAKE2S is not set\n# CONFIG_CRYPTO_LIB_CHACHA is not set\n# CONFIG_CRYPTO_LIB_CURVE25519 is not set\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=9\n# CONFIG_CRYPTO_LIB_POLY1305 is not set\n# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set\nCONFIG_CRYPTO_LIB_SHA256=y\nCONFIG_CRYPTO_HW=y\n# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set\n# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set\n# CONFIG_CRYPTO_DEV_SAFEXCEL is not set\n# CONFIG_CRYPTO_DEV_CCREE is not set\n# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set\nCONFIG_ASYMMETRIC_KEY_TYPE=y\nCONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y\nCONFIG_X509_CERTIFICATE_PARSER=y\n# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set\nCONFIG_PKCS7_MESSAGE_PARSER=y\n# CONFIG_PKCS7_TEST_KEY is not set\n# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set\n\n#\n# Certificates for signature checking\n#\nCONFIG_SYSTEM_TRUSTED_KEYRING=y\nCONFIG_SYSTEM_TRUSTED_KEYS=\"\"\n# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set\n# CONFIG_SECONDARY_TRUSTED_KEYRING is not set\n# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set\n# end of Certificates for signature checking\n\n#\n# Library routines\n#\nCONFIG_LINEAR_RANGES=y\n# CONFIG_PACKING is not set\nCONFIG_BITREVERSE=y\nCONFIG_HAVE_ARCH_BITREVERSE=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_NET_UTILS=y\n# CONFIG_CORDIC is not set\n# CONFIG_PRIME_NUMBERS is not set\nCONFIG_RATIONAL=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_ARCH_USE_CMPXCHG_LOCKREF=y\nCONFIG_CRC_CCITT=y\nCONFIG_CRC16=y\n# CONFIG_CRC_T10DIF is not set\n# CONFIG_CRC_ITU_T is not set\nCONFIG_CRC32=y\n# CONFIG_CRC32_SELFTEST is not set\nCONFIG_CRC32_SLICEBY8=y\n# CONFIG_CRC32_SLICEBY4 is not set\n# CONFIG_CRC32_SARWATE is not set\n# CONFIG_CRC32_BIT is not set\n# CONFIG_CRC64 is not set\n# CONFIG_CRC4 is not set\n# CONFIG_CRC7 is not set\nCONFIG_LIBCRC32C=y\nCONFIG_CRC8=y\nCONFIG_XXHASH=y\n# CONFIG_RANDOM32_SELFTEST is not set\nCONFIG_ZLIB_INFLATE=y\nCONFIG_ZSTD_DECOMPRESS=y\n# CONFIG_XZ_DEC is not set\nCONFIG_DECOMPRESS_GZIP=y\nCONFIG_DECOMPRESS_ZSTD=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_ASSOCIATIVE_ARRAY=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HAS_DMA=y\nCONFIG_DMA_OPS=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_DMA_DECLARE_COHERENT=y\nCONFIG_ARCH_HAS_SETUP_DMA_OPS=y\nCONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y\nCONFIG_DMA_NONCOHERENT_MMAP=y\nCONFIG_DMA_REMAP=y\nCONFIG_DMA_CMA=y\n# CONFIG_DMA_PERNUMA_CMA is not set\n\n#\n# Default contiguous memory area size:\n#\nCONFIG_CMA_SIZE_MBYTES=128\nCONFIG_CMA_SIZE_SEL_MBYTES=y\n# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set\n# CONFIG_CMA_SIZE_SEL_MIN is not set\n# CONFIG_CMA_SIZE_SEL_MAX is not set\nCONFIG_CMA_ALIGNMENT=8\n# CONFIG_DMA_API_DEBUG is not set\n# CONFIG_DMA_MAP_BENCHMARK is not set\nCONFIG_SGL_ALLOC=y\nCONFIG_CPU_RMAP=y\nCONFIG_DQL=y\nCONFIG_GLOB=y\n# CONFIG_GLOB_SELFTEST is not set\nCONFIG_NLATTR=y\nCONFIG_CLZ_TAB=y\n# CONFIG_IRQ_POLL is not set\nCONFIG_MPILIB=y\nCONFIG_LIBFDT=y\nCONFIG_OID_REGISTRY=y\nCONFIG_FONT_SUPPORT=y\nCONFIG_FONTS=y\nCONFIG_FONT_8x8=y\nCONFIG_FONT_8x16=y\n# CONFIG_FONT_6x11 is not set\n# CONFIG_FONT_7x14 is not set\n# CONFIG_FONT_PEARL_8x8 is not set\n# CONFIG_FONT_ACORN_8x8 is not set\n# CONFIG_FONT_MINI_4x6 is not set\n# CONFIG_FONT_6x10 is not set\n# CONFIG_FONT_10x18 is not set\n# CONFIG_FONT_SUN8x16 is not set\n# CONFIG_FONT_SUN12x22 is not set\n# CONFIG_FONT_TER16x32 is not set\n# CONFIG_FONT_6x8 is not set\nCONFIG_SG_POOL=y\nCONFIG_SBITMAP=y\n# end of Library routines\n\nCONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y\n\n#\n# Kernel hacking\n#\n\n#\n# printk and dmesg options\n#\n# CONFIG_PRINTK_TIME is not set\n# CONFIG_PRINTK_CALLER is not set\n# CONFIG_STACKTRACE_BUILD_ID is not set\nCONFIG_CONSOLE_LOGLEVEL_DEFAULT=7\nCONFIG_CONSOLE_LOGLEVEL_QUIET=4\nCONFIG_MESSAGE_LOGLEVEL_DEFAULT=4\n# CONFIG_BOOT_PRINTK_DELAY is not set\n# CONFIG_DYNAMIC_DEBUG is not set\n# CONFIG_DYNAMIC_DEBUG_CORE is not set\nCONFIG_SYMBOLIC_ERRNAME=y\nCONFIG_DEBUG_BUGVERBOSE=y\n# end of printk and dmesg options\n\n#\n# Compile-time checks and compiler options\n#\nCONFIG_DEBUG_INFO=y\n# CONFIG_DEBUG_INFO_REDUCED is not set\n# CONFIG_DEBUG_INFO_COMPRESSED is not set\n# CONFIG_DEBUG_INFO_SPLIT is not set\nCONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y\n# CONFIG_DEBUG_INFO_DWARF4 is not set\n# CONFIG_DEBUG_INFO_DWARF5 is not set\n# CONFIG_DEBUG_INFO_BTF is not set\n# CONFIG_GDB_SCRIPTS is not set\nCONFIG_FRAME_WARN=1024\n# CONFIG_STRIP_ASM_SYMS is not set\n# CONFIG_READABLE_ASM is not set\n# CONFIG_HEADERS_INSTALL is not set\n# CONFIG_DEBUG_SECTION_MISMATCH is not set\nCONFIG_SECTION_MISMATCH_WARN_ONLY=y\n# CONFIG_VMLINUX_MAP is not set\n# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set\n# end of Compile-time checks and compiler options\n\n#\n# Generic Kernel Debugging Instruments\n#\n# CONFIG_MAGIC_SYSRQ is not set\nCONFIG_DEBUG_FS=y\nCONFIG_DEBUG_FS_ALLOW_ALL=y\n# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set\n# CONFIG_DEBUG_FS_ALLOW_NONE is not set\nCONFIG_HAVE_ARCH_KGDB=y\n# CONFIG_KGDB is not set\n# CONFIG_UBSAN is not set\n# end of Generic Kernel Debugging Instruments\n\nCONFIG_DEBUG_KERNEL=y\nCONFIG_DEBUG_MISC=y\n\n#\n# Memory Debugging\n#\n# CONFIG_PAGE_EXTENSION is not set\n# CONFIG_DEBUG_PAGEALLOC is not set\n# CONFIG_PAGE_OWNER is not set\n# CONFIG_PAGE_POISONING is not set\n# CONFIG_DEBUG_RODATA_TEST is not set\n# CONFIG_DEBUG_WX is not set\n# CONFIG_DEBUG_OBJECTS is not set\n# CONFIG_DEBUG_SLAB is not set\nCONFIG_HAVE_DEBUG_KMEMLEAK=y\n# CONFIG_DEBUG_KMEMLEAK is not set\n# CONFIG_DEBUG_STACK_USAGE is not set\n# CONFIG_SCHED_STACK_END_CHECK is not set\n# CONFIG_DEBUG_VM is not set\nCONFIG_ARCH_HAS_DEBUG_VIRTUAL=y\n# CONFIG_DEBUG_VIRTUAL is not set\n# CONFIG_DEBUG_MEMORY_INIT is not set\n# CONFIG_DEBUG_PER_CPU_MAPS is not set\n# CONFIG_DEBUG_KMAP_LOCAL is not set\n# CONFIG_DEBUG_HIGHMEM is not set\nCONFIG_HAVE_ARCH_KASAN=y\nCONFIG_CC_HAS_KASAN_GENERIC=y\nCONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y\n# CONFIG_KASAN is not set\n# end of Memory Debugging\n\n# CONFIG_DEBUG_SHIRQ is not set\n\n#\n# Debug Oops, Lockups and Hangs\n#\n# CONFIG_PANIC_ON_OOPS is not set\nCONFIG_PANIC_ON_OOPS_VALUE=0\nCONFIG_PANIC_TIMEOUT=0\n# CONFIG_SOFTLOCKUP_DETECTOR is not set\nCONFIG_DETECT_HUNG_TASK=y\nCONFIG_DEFAULT_HUNG_TASK_TIMEOUT=20\n# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set\nCONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0\n# CONFIG_WQ_WATCHDOG is not set\n# CONFIG_TEST_LOCKUP is not set\n# end of Debug Oops, Lockups and Hangs\n\n#\n# Scheduler Debugging\n#\n# CONFIG_SCHED_DEBUG is not set\n# CONFIG_SCHEDSTATS is not set\n# end of Scheduler Debugging\n\n# CONFIG_DEBUG_TIMEKEEPING is not set\n# CONFIG_DEBUG_PREEMPT is not set\n\n#\n# Lock Debugging (spinlocks, mutexes, etc...)\n#\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\n# CONFIG_PROVE_LOCKING is not set\n# CONFIG_LOCK_STAT is not set\n# CONFIG_DEBUG_RT_MUTEXES is not set\n# CONFIG_DEBUG_SPINLOCK is not set\n# CONFIG_DEBUG_MUTEXES is not set\n# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set\n# CONFIG_DEBUG_RWSEMS is not set\n# CONFIG_DEBUG_LOCK_ALLOC is not set\n# CONFIG_DEBUG_ATOMIC_SLEEP is not set\n# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set\n# CONFIG_LOCK_TORTURE_TEST is not set\n# CONFIG_WW_MUTEX_SELFTEST is not set\n# CONFIG_SCF_TORTURE_TEST is not set\n# end of Lock Debugging (spinlocks, mutexes, etc...)\n\n# CONFIG_DEBUG_IRQFLAGS is not set\n# CONFIG_STACKTRACE is not set\n# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set\n# CONFIG_DEBUG_KOBJECT is not set\n\n#\n# Debug kernel data structures\n#\n# CONFIG_DEBUG_LIST is not set\n# CONFIG_DEBUG_PLIST is not set\n# CONFIG_DEBUG_SG is not set\n# CONFIG_DEBUG_NOTIFIERS is not set\n# CONFIG_BUG_ON_DATA_CORRUPTION is not set\n# end of Debug kernel data structures\n\n# CONFIG_DEBUG_CREDENTIALS is not set\n\n#\n# RCU Debugging\n#\n# CONFIG_RCU_SCALE_TEST is not set\n# CONFIG_RCU_TORTURE_TEST is not set\n# CONFIG_RCU_REF_SCALE_TEST is not set\nCONFIG_RCU_CPU_STALL_TIMEOUT=60\nCONFIG_RCU_TRACE=y\n# CONFIG_RCU_EQS_DEBUG is not set\n# end of RCU Debugging\n\n# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set\n# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set\n# CONFIG_LATENCYTOP is not set\nCONFIG_HAVE_FUNCTION_TRACER=y\nCONFIG_HAVE_FUNCTION_GRAPH_TRACER=y\nCONFIG_HAVE_DYNAMIC_FTRACE=y\nCONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y\nCONFIG_HAVE_FTRACE_MCOUNT_RECORD=y\nCONFIG_HAVE_SYSCALL_TRACEPOINTS=y\nCONFIG_HAVE_C_RECORDMCOUNT=y\nCONFIG_TRACE_CLOCK=y\nCONFIG_TRACING_SUPPORT=y\n# CONFIG_FTRACE is not set\n# CONFIG_SAMPLES is not set\n# CONFIG_STRICT_DEVMEM is not set\n\n#\n# arm Debugging\n#\n# CONFIG_ARM_PTDUMP_DEBUGFS is not set\n# CONFIG_UNWINDER_FRAME_POINTER is not set\nCONFIG_UNWINDER_ARM=y\nCONFIG_ARM_UNWIND=y\n# CONFIG_DEBUG_USER is not set\nCONFIG_DEBUG_LL=y\n# CONFIG_DEBUG_ZYNQ_UART0 is not set\nCONFIG_DEBUG_ZYNQ_UART1=y\n# CONFIG_DEBUG_ICEDCC is not set\n# CONFIG_DEBUG_SEMIHOSTING is not set\n# CONFIG_DEBUG_LL_UART_8250 is not set\n# CONFIG_DEBUG_LL_UART_PL01X is not set\n# CONFIG_DEBUG_UART_FLOW_CONTROL is not set\nCONFIG_DEBUG_LL_INCLUDE=\"debug/zynq.S\"\n# CONFIG_DEBUG_UNCOMPRESS is not set\nCONFIG_UNCOMPRESS_INCLUDE=\"debug/uncompress.h\"\nCONFIG_EARLY_PRINTK=y\n# CONFIG_PID_IN_CONTEXTIDR is not set\n# CONFIG_CORESIGHT is not set\n# end of arm Debugging\n\n#\n# Kernel Testing and Coverage\n#\n# CONFIG_KUNIT is not set\n# CONFIG_NOTIFIER_ERROR_INJECTION is not set\n# CONFIG_FAULT_INJECTION is not set\nCONFIG_ARCH_HAS_KCOV=y\nCONFIG_CC_HAS_SANCOV_TRACE_PC=y\n# CONFIG_KCOV is not set\nCONFIG_RUNTIME_TESTING_MENU=y\n# CONFIG_LKDTM is not set\n# CONFIG_TEST_MIN_HEAP is not set\n# CONFIG_TEST_DIV64 is not set\n# CONFIG_BACKTRACE_SELF_TEST is not set\n# CONFIG_RBTREE_TEST is not set\n# CONFIG_REED_SOLOMON_TEST is not set\n# CONFIG_INTERVAL_TREE_TEST is not set\n# CONFIG_PERCPU_TEST is not set\n# CONFIG_ATOMIC64_SELFTEST is not set\n# CONFIG_TEST_HEXDUMP is not set\n# CONFIG_STRING_SELFTEST is not set\n# CONFIG_TEST_STRING_HELPERS is not set\n# CONFIG_TEST_STRSCPY is not set\n# CONFIG_TEST_KSTRTOX is not set\n# CONFIG_TEST_PRINTF is not set\n# CONFIG_TEST_SCANF is not set\n# CONFIG_TEST_BITMAP is not set\n# CONFIG_TEST_UUID is not set\n# CONFIG_TEST_XARRAY is not set\n# CONFIG_TEST_OVERFLOW is not set\n# CONFIG_TEST_RHASHTABLE is not set\n# CONFIG_TEST_HASH is not set\n# CONFIG_TEST_IDA is not set\n# CONFIG_TEST_LKM is not set\n# CONFIG_TEST_BITOPS is not set\n# CONFIG_TEST_VMALLOC is not set\n# CONFIG_TEST_USER_COPY is not set\n# CONFIG_TEST_BPF is not set\n# CONFIG_TEST_BLACKHOLE_DEV is not set\n# CONFIG_FIND_BIT_BENCHMARK is not set\n# CONFIG_TEST_FIRMWARE is not set\n# CONFIG_TEST_SYSCTL is not set\n# CONFIG_TEST_UDELAY is not set\n# CONFIG_TEST_STATIC_KEYS is not set\n# CONFIG_TEST_KMOD is not set\n# CONFIG_TEST_MEMCAT_P is not set\n# CONFIG_TEST_STACKINIT is not set\n# CONFIG_TEST_MEMINIT is not set\n# CONFIG_TEST_FREE_PAGES is not set\nCONFIG_ARCH_USE_MEMTEST=y\n# CONFIG_MEMTEST is not set\n# end of Kernel Testing and Coverage\n# end of Kernel hacking\n"
  },
  {
    "path": "kernel_boot/kernel_config_zynqmp",
    "content": "#\n# Automatically generated file; DO NOT EDIT.\n# Linux/arm64 5.15.36 Kernel Configuration\n#\nCONFIG_KERNEL_ALL_ADI_DRIVERS=y\nCONFIG_CLK_ALL_ADI_DRIVERS=y\nCONFIG_HWMON_ALL_ADI_DRIVERS=y\nCONFIG_IIO_ALL_ADI_DRIVERS=y\nCONFIG_INPUT_ALL_ADI_DRIVERS=y\nCONFIG_MEDIA_ALL_ADI_DRIVERS=y\nCONFIG_USB_ALL_ADI_DRIVERS=y\nCONFIG_SND_SOC_ALL_ADI_CODECS=y\nCONFIG_CC_VERSION_TEXT=\"aarch64-xilinx-linux-gcc.real (GCC) 10.2.0\"\nCONFIG_CC_IS_GCC=y\nCONFIG_GCC_VERSION=100200\nCONFIG_CLANG_VERSION=0\nCONFIG_AS_IS_GNU=y\nCONFIG_AS_VERSION=23500\nCONFIG_LD_IS_BFD=y\nCONFIG_LD_VERSION=23500\nCONFIG_LLD_VERSION=0\nCONFIG_CC_CAN_LINK=y\nCONFIG_CC_CAN_LINK_STATIC=y\nCONFIG_CC_HAS_ASM_GOTO=y\nCONFIG_CC_HAS_ASM_INLINE=y\nCONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y\nCONFIG_IRQ_WORK=y\nCONFIG_BUILDTIME_TABLE_SORT=y\nCONFIG_THREAD_INFO_IN_TASK=y\n\n#\n# General setup\n#\nCONFIG_INIT_ENV_ARG_LIMIT=32\n# CONFIG_COMPILE_TEST is not set\n# CONFIG_WERROR is not set\nCONFIG_LOCALVERSION=\"\"\nCONFIG_LOCALVERSION_AUTO=y\nCONFIG_BUILD_SALT=\"\"\nCONFIG_DEFAULT_INIT=\"\"\nCONFIG_DEFAULT_HOSTNAME=\"(none)\"\nCONFIG_SWAP=y\nCONFIG_SYSVIPC=y\nCONFIG_SYSVIPC_SYSCTL=y\nCONFIG_POSIX_MQUEUE=y\nCONFIG_POSIX_MQUEUE_SYSCTL=y\n# CONFIG_WATCH_QUEUE is not set\nCONFIG_CROSS_MEMORY_ATTACH=y\n# CONFIG_USELIB is not set\nCONFIG_AUDIT=y\nCONFIG_HAVE_ARCH_AUDITSYSCALL=y\nCONFIG_AUDITSYSCALL=y\n\n#\n# IRQ subsystem\n#\nCONFIG_GENERIC_IRQ_PROBE=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_MIGRATION=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_GENERIC_IRQ_IPI=y\nCONFIG_GENERIC_MSI_IRQ=y\nCONFIG_GENERIC_MSI_IRQ_DOMAIN=y\nCONFIG_IRQ_MSI_IOMMU=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_SPARSE_IRQ=y\n# CONFIG_GENERIC_IRQ_DEBUGFS is not set\n# end of IRQ subsystem\n\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_ARCH_HAS_TICK_BROADCAST=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\n\n#\n# Timers subsystem\n#\nCONFIG_TICK_ONESHOT=y\nCONFIG_NO_HZ_COMMON=y\n# CONFIG_HZ_PERIODIC is not set\nCONFIG_NO_HZ_IDLE=y\n# CONFIG_NO_HZ_FULL is not set\nCONFIG_NO_HZ=y\nCONFIG_HIGH_RES_TIMERS=y\n# end of Timers subsystem\n\nCONFIG_BPF=y\nCONFIG_HAVE_EBPF_JIT=y\nCONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y\n\n#\n# BPF subsystem\n#\n# CONFIG_BPF_SYSCALL is not set\n# CONFIG_BPF_JIT is not set\nCONFIG_USERMODE_DRIVER=y\n# end of BPF subsystem\n\nCONFIG_PREEMPT_NONE=y\n# CONFIG_PREEMPT_VOLUNTARY is not set\n# CONFIG_PREEMPT is not set\n\n#\n# CPU/Task time and stats accounting\n#\nCONFIG_TICK_CPU_ACCOUNTING=y\n# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set\n# CONFIG_IRQ_TIME_ACCOUNTING is not set\nCONFIG_BSD_PROCESS_ACCT=y\n# CONFIG_BSD_PROCESS_ACCT_V3 is not set\nCONFIG_TASKSTATS=y\nCONFIG_TASK_DELAY_ACCT=y\nCONFIG_TASK_XACCT=y\nCONFIG_TASK_IO_ACCOUNTING=y\n# CONFIG_PSI is not set\n# end of CPU/Task time and stats accounting\n\nCONFIG_CPU_ISOLATION=y\n\n#\n# RCU Subsystem\n#\nCONFIG_TREE_RCU=y\n# CONFIG_RCU_EXPERT is not set\nCONFIG_SRCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_RCU_STALL_COMMON=y\nCONFIG_RCU_NEED_SEGCBLIST=y\n# end of RCU Subsystem\n\nCONFIG_IKCONFIG=y\nCONFIG_IKCONFIG_PROC=y\n# CONFIG_IKHEADERS is not set\nCONFIG_LOG_BUF_SHIFT=16\nCONFIG_LOG_CPU_MAX_BUF_SHIFT=12\nCONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13\n# CONFIG_PRINTK_INDEX is not set\nCONFIG_GENERIC_SCHED_CLOCK=y\n\n#\n# Scheduler features\n#\n# end of Scheduler features\n\nCONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y\nCONFIG_CC_HAS_INT128=y\nCONFIG_ARCH_SUPPORTS_INT128=y\nCONFIG_CGROUPS=y\n# CONFIG_MEMCG is not set\n# CONFIG_BLK_CGROUP is not set\n# CONFIG_CGROUP_SCHED is not set\n# CONFIG_CGROUP_PIDS is not set\n# CONFIG_CGROUP_RDMA is not set\n# CONFIG_CGROUP_FREEZER is not set\n# CONFIG_CGROUP_HUGETLB is not set\n# CONFIG_CPUSETS is not set\n# CONFIG_CGROUP_DEVICE is not set\n# CONFIG_CGROUP_CPUACCT is not set\n# CONFIG_CGROUP_PERF is not set\n# CONFIG_CGROUP_MISC is not set\n# CONFIG_CGROUP_DEBUG is not set\nCONFIG_NAMESPACES=y\nCONFIG_UTS_NS=y\nCONFIG_TIME_NS=y\nCONFIG_IPC_NS=y\nCONFIG_USER_NS=y\nCONFIG_PID_NS=y\nCONFIG_NET_NS=y\n# CONFIG_CHECKPOINT_RESTORE is not set\n# CONFIG_SCHED_AUTOGROUP is not set\n# CONFIG_SYSFS_DEPRECATED is not set\n# CONFIG_RELAY is not set\nCONFIG_BLK_DEV_INITRD=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_RD_GZIP=y\nCONFIG_RD_BZIP2=y\nCONFIG_RD_LZMA=y\nCONFIG_RD_XZ=y\nCONFIG_RD_LZO=y\nCONFIG_RD_LZ4=y\nCONFIG_RD_ZSTD=y\n# CONFIG_BOOT_CONFIG is not set\nCONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y\n# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set\nCONFIG_LD_ORPHAN_WARN=y\nCONFIG_SYSCTL=y\nCONFIG_HAVE_UID16=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_EXPERT=y\nCONFIG_UID16=y\nCONFIG_MULTIUSER=y\n# CONFIG_SGETMASK_SYSCALL is not set\nCONFIG_SYSFS_SYSCALL=y\nCONFIG_FHANDLE=y\nCONFIG_POSIX_TIMERS=y\nCONFIG_PRINTK=y\nCONFIG_BUG=y\nCONFIG_ELF_CORE=y\nCONFIG_BASE_FULL=y\nCONFIG_FUTEX=y\nCONFIG_FUTEX_PI=y\nCONFIG_HAVE_FUTEX_CMPXCHG=y\nCONFIG_EPOLL=y\nCONFIG_SIGNALFD=y\nCONFIG_TIMERFD=y\nCONFIG_EVENTFD=y\nCONFIG_SHMEM=y\nCONFIG_AIO=y\nCONFIG_IO_URING=y\nCONFIG_ADVISE_SYSCALLS=y\nCONFIG_MEMBARRIER=y\nCONFIG_KALLSYMS=y\n# CONFIG_KALLSYMS_ALL is not set\nCONFIG_KALLSYMS_BASE_RELATIVE=y\n# CONFIG_USERFAULTFD is not set\nCONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y\nCONFIG_KCMP=y\nCONFIG_RSEQ=y\n# CONFIG_DEBUG_RSEQ is not set\nCONFIG_EMBEDDED=y\nCONFIG_HAVE_PERF_EVENTS=y\n# CONFIG_PC104 is not set\n\n#\n# Kernel Performance Events And Counters\n#\nCONFIG_PERF_EVENTS=y\n# CONFIG_DEBUG_PERF_USE_VMALLOC is not set\n# end of Kernel Performance Events And Counters\n\nCONFIG_VM_EVENT_COUNTERS=y\n# CONFIG_COMPAT_BRK is not set\nCONFIG_SLAB=y\n# CONFIG_SLUB is not set\n# CONFIG_SLOB is not set\nCONFIG_SLAB_MERGE_DEFAULT=y\n# CONFIG_SLAB_FREELIST_RANDOM is not set\n# CONFIG_SLAB_FREELIST_HARDENED is not set\n# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set\nCONFIG_SYSTEM_DATA_VERIFICATION=y\nCONFIG_PROFILING=y\n# end of General setup\n\nCONFIG_ARM64=y\nCONFIG_64BIT=y\nCONFIG_MMU=y\nCONFIG_ARM64_PAGE_SHIFT=12\nCONFIG_ARM64_CONT_PTE_SHIFT=4\nCONFIG_ARM64_CONT_PMD_SHIFT=4\nCONFIG_ARCH_MMAP_RND_BITS_MIN=18\nCONFIG_ARCH_MMAP_RND_BITS_MAX=24\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16\nCONFIG_STACKTRACE_SUPPORT=y\nCONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000\nCONFIG_LOCKDEP_SUPPORT=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_BUG_RELATIVE_POINTERS=y\nCONFIG_GENERIC_HWEIGHT=y\nCONFIG_GENERIC_CSUM=y\nCONFIG_GENERIC_CALIBRATE_DELAY=y\nCONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y\nCONFIG_SMP=y\nCONFIG_KERNEL_MODE_NEON=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_PGTABLE_LEVELS=3\nCONFIG_ARCH_SUPPORTS_UPROBES=y\nCONFIG_ARCH_PROC_KCORE_TEXT=y\n\n#\n# Platform selection\n#\n# CONFIG_ARCH_ACTIONS is not set\n# CONFIG_ARCH_SUNXI is not set\n# CONFIG_ARCH_ALPINE is not set\n# CONFIG_ARCH_APPLE is not set\n# CONFIG_ARCH_BCM2835 is not set\n# CONFIG_ARCH_BCM4908 is not set\n# CONFIG_ARCH_BCM_IPROC is not set\n# CONFIG_ARCH_BERLIN is not set\n# CONFIG_ARCH_BITMAIN is not set\n# CONFIG_ARCH_BRCMSTB is not set\n# CONFIG_ARCH_EXYNOS is not set\n# CONFIG_ARCH_SPARX5 is not set\n# CONFIG_ARCH_K3 is not set\n# CONFIG_ARCH_LAYERSCAPE is not set\n# CONFIG_ARCH_LG1K is not set\n# CONFIG_ARCH_HISI is not set\n# CONFIG_ARCH_KEEMBAY is not set\n# CONFIG_ARCH_MEDIATEK is not set\n# CONFIG_ARCH_MESON is not set\n# CONFIG_ARCH_MVEBU is not set\n# CONFIG_ARCH_MXC is not set\n# CONFIG_ARCH_QCOM is not set\n# CONFIG_ARCH_REALTEK is not set\n# CONFIG_ARCH_RENESAS is not set\n# CONFIG_ARCH_ROCKCHIP is not set\n# CONFIG_ARCH_S32 is not set\n# CONFIG_ARCH_SEATTLE is not set\n# CONFIG_ARCH_INTEL_SOCFPGA is not set\n# CONFIG_ARCH_SYNQUACER is not set\n# CONFIG_ARCH_TEGRA is not set\n# CONFIG_ARCH_SPRD is not set\n# CONFIG_ARCH_THUNDER is not set\n# CONFIG_ARCH_THUNDER2 is not set\n# CONFIG_ARCH_UNIPHIER is not set\n# CONFIG_ARCH_VEXPRESS is not set\n# CONFIG_ARCH_VISCONTI is not set\n# CONFIG_ARCH_XGENE is not set\nCONFIG_ARCH_ZYNQMP=y\n# end of Platform selection\n\n#\n# Kernel Features\n#\n\n#\n# ARM errata workarounds via the alternatives framework\n#\nCONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y\nCONFIG_ARM64_ERRATUM_826319=y\nCONFIG_ARM64_ERRATUM_827319=y\nCONFIG_ARM64_ERRATUM_824069=y\nCONFIG_ARM64_ERRATUM_819472=y\nCONFIG_ARM64_ERRATUM_832075=y\nCONFIG_ARM64_ERRATUM_845719=y\nCONFIG_ARM64_ERRATUM_843419=y\nCONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y\nCONFIG_ARM64_ERRATUM_1024718=y\nCONFIG_ARM64_ERRATUM_1418040=y\nCONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y\nCONFIG_ARM64_ERRATUM_1165522=y\nCONFIG_ARM64_ERRATUM_1319367=y\nCONFIG_ARM64_ERRATUM_1530923=y\nCONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y\nCONFIG_ARM64_ERRATUM_1286807=y\nCONFIG_ARM64_ERRATUM_1463225=y\nCONFIG_ARM64_ERRATUM_1542419=y\nCONFIG_ARM64_ERRATUM_1508412=y\nCONFIG_CAVIUM_ERRATUM_22375=y\nCONFIG_CAVIUM_ERRATUM_23154=y\nCONFIG_CAVIUM_ERRATUM_27456=y\nCONFIG_CAVIUM_ERRATUM_30115=y\nCONFIG_CAVIUM_TX2_ERRATUM_219=y\nCONFIG_FUJITSU_ERRATUM_010001=y\nCONFIG_HISILICON_ERRATUM_161600802=y\nCONFIG_QCOM_FALKOR_ERRATUM_1003=y\nCONFIG_QCOM_FALKOR_ERRATUM_1009=y\nCONFIG_QCOM_QDF2400_ERRATUM_0065=y\nCONFIG_QCOM_FALKOR_ERRATUM_E1041=y\nCONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y\nCONFIG_SOCIONEXT_SYNQUACER_PREITS=y\n# end of ARM errata workarounds via the alternatives framework\n\nCONFIG_ARM64_4K_PAGES=y\n# CONFIG_ARM64_16K_PAGES is not set\n# CONFIG_ARM64_64K_PAGES is not set\nCONFIG_ARM64_VA_BITS_39=y\n# CONFIG_ARM64_VA_BITS_48 is not set\nCONFIG_ARM64_VA_BITS=39\nCONFIG_ARM64_PA_BITS_48=y\nCONFIG_ARM64_PA_BITS=48\n# CONFIG_CPU_BIG_ENDIAN is not set\nCONFIG_CPU_LITTLE_ENDIAN=y\n# CONFIG_SCHED_MC is not set\n# CONFIG_SCHED_SMT is not set\nCONFIG_NR_CPUS=8\nCONFIG_HOTPLUG_CPU=y\n# CONFIG_NUMA is not set\n# CONFIG_HZ_100 is not set\nCONFIG_HZ_250=y\n# CONFIG_HZ_300 is not set\n# CONFIG_HZ_1000 is not set\nCONFIG_HZ=250\nCONFIG_SCHED_HRTICK=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_HW_PERF_EVENTS=y\n# CONFIG_PARAVIRT is not set\n# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set\n# CONFIG_KEXEC is not set\n# CONFIG_KEXEC_FILE is not set\n# CONFIG_CRASH_DUMP is not set\n# CONFIG_XEN is not set\nCONFIG_FORCE_MAX_ZONEORDER=11\nCONFIG_UNMAP_KERNEL_AT_EL0=y\n# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set\nCONFIG_RODATA_FULL_DEFAULT_ENABLED=y\n# CONFIG_ARM64_SW_TTBR0_PAN is not set\nCONFIG_ARM64_TAGGED_ADDR_ABI=y\nCONFIG_COMPAT=y\nCONFIG_KUSER_HELPERS=y\nCONFIG_ARMV8_DEPRECATED=y\nCONFIG_SWP_EMULATION=y\nCONFIG_CP15_BARRIER_EMULATION=y\nCONFIG_SETEND_EMULATION=y\n\n#\n# ARMv8.1 architectural features\n#\nCONFIG_ARM64_HW_AFDBM=y\nCONFIG_ARM64_PAN=y\nCONFIG_AS_HAS_LDAPR=y\nCONFIG_AS_HAS_LSE_ATOMICS=y\n# end of ARMv8.1 architectural features\n\n#\n# ARMv8.2 architectural features\n#\n# CONFIG_ARM64_PMEM is not set\nCONFIG_ARM64_RAS_EXTN=y\nCONFIG_ARM64_CNP=y\n# end of ARMv8.2 architectural features\n\n#\n# ARMv8.3 architectural features\n#\nCONFIG_ARM64_PTR_AUTH=y\nCONFIG_ARM64_PTR_AUTH_KERNEL=y\nCONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y\nCONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y\nCONFIG_AS_HAS_PAC=y\nCONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y\n# end of ARMv8.3 architectural features\n\n#\n# ARMv8.4 architectural features\n#\nCONFIG_ARM64_AMU_EXTN=y\nCONFIG_AS_HAS_ARMV8_4=y\nCONFIG_ARM64_TLB_RANGE=y\n# end of ARMv8.4 architectural features\n\n#\n# ARMv8.5 architectural features\n#\nCONFIG_AS_HAS_ARMV8_5=y\nCONFIG_ARM64_BTI=y\nCONFIG_ARM64_BTI_KERNEL=y\nCONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y\nCONFIG_ARM64_E0PD=y\nCONFIG_ARCH_RANDOM=y\nCONFIG_ARM64_AS_HAS_MTE=y\nCONFIG_ARM64_MTE=y\n# end of ARMv8.5 architectural features\n\n#\n# ARMv8.7 architectural features\n#\nCONFIG_ARM64_EPAN=y\n# end of ARMv8.7 architectural features\n\nCONFIG_ARM64_SVE=y\nCONFIG_ARM64_MODULE_PLTS=y\n# CONFIG_ARM64_PSEUDO_NMI is not set\nCONFIG_RELOCATABLE=y\n# CONFIG_RANDOMIZE_BASE is not set\nCONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y\nCONFIG_STACKPROTECTOR_PER_TASK=y\n# end of Kernel Features\n\n#\n# Boot options\n#\nCONFIG_CMDLINE=\"\"\nCONFIG_EFI_STUB=y\nCONFIG_EFI=y\n# CONFIG_DMI is not set\n# end of Boot options\n\nCONFIG_SYSVIPC_COMPAT=y\n\n#\n# Power management options\n#\nCONFIG_SUSPEND=y\nCONFIG_SUSPEND_FREEZER=y\n# CONFIG_SUSPEND_SKIP_SYNC is not set\n# CONFIG_HIBERNATION is not set\nCONFIG_PM_SLEEP=y\nCONFIG_PM_SLEEP_SMP=y\n# CONFIG_PM_AUTOSLEEP is not set\n# CONFIG_PM_WAKELOCKS is not set\nCONFIG_PM=y\n# CONFIG_PM_DEBUG is not set\nCONFIG_PM_CLK=y\nCONFIG_PM_GENERIC_DOMAINS=y\n# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set\nCONFIG_PM_GENERIC_DOMAINS_SLEEP=y\nCONFIG_PM_GENERIC_DOMAINS_OF=y\nCONFIG_CPU_PM=y\n# CONFIG_ENERGY_MODEL is not set\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\n# end of Power management options\n\n#\n# CPU Power Management\n#\n\n#\n# CPU Idle\n#\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y\n# CONFIG_CPU_IDLE_GOV_LADDER is not set\nCONFIG_CPU_IDLE_GOV_MENU=y\n# CONFIG_CPU_IDLE_GOV_TEO is not set\nCONFIG_DT_IDLE_STATES=y\n\n#\n# ARM CPU Idle Drivers\n#\nCONFIG_ARM_CPUIDLE=y\n# CONFIG_ARM_PSCI_CPUIDLE is not set\n# end of ARM CPU Idle Drivers\n# end of CPU Idle\n\n#\n# CPU Frequency scaling\n#\nCONFIG_CPU_FREQ=y\n# CONFIG_CPU_FREQ_STAT is not set\n# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set\n# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set\nCONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y\n# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set\n# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set\n# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set\n# CONFIG_CPU_FREQ_GOV_PERFORMANCE is not set\n# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set\nCONFIG_CPU_FREQ_GOV_USERSPACE=y\n# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set\n# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set\n# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set\n\n#\n# CPU frequency scaling drivers\n#\nCONFIG_CPUFREQ_DT=y\nCONFIG_CPUFREQ_DT_PLATDEV=y\n# end of CPU Frequency scaling\n# end of CPU Power Management\n\nCONFIG_ARCH_SUPPORTS_ACPI=y\n# CONFIG_ACPI is not set\n# CONFIG_VIRTUALIZATION is not set\n# CONFIG_ARM64_CRYPTO is not set\n\n#\n# General architecture-dependent options\n#\n# CONFIG_KPROBES is not set\n# CONFIG_JUMP_LABEL is not set\nCONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y\nCONFIG_HAVE_KPROBES=y\nCONFIG_HAVE_KRETPROBES=y\nCONFIG_HAVE_FUNCTION_ERROR_INJECTION=y\nCONFIG_HAVE_NMI=y\nCONFIG_TRACE_IRQFLAGS_SUPPORT=y\nCONFIG_HAVE_ARCH_TRACEHOOK=y\nCONFIG_HAVE_DMA_CONTIGUOUS=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_ARCH_HAS_FORTIFY_SOURCE=y\nCONFIG_ARCH_HAS_KEEPINITRD=y\nCONFIG_ARCH_HAS_SET_MEMORY=y\nCONFIG_ARCH_HAS_SET_DIRECT_MAP=y\nCONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y\nCONFIG_ARCH_WANTS_NO_INSTR=y\nCONFIG_HAVE_ASM_MODVERSIONS=y\nCONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y\nCONFIG_HAVE_RSEQ=y\nCONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y\nCONFIG_HAVE_HW_BREAKPOINT=y\nCONFIG_HAVE_PERF_REGS=y\nCONFIG_HAVE_PERF_USER_STACK_DUMP=y\nCONFIG_HAVE_ARCH_JUMP_LABEL=y\nCONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y\nCONFIG_MMU_GATHER_TABLE_FREE=y\nCONFIG_MMU_GATHER_RCU_TABLE_FREE=y\nCONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y\nCONFIG_HAVE_CMPXCHG_LOCAL=y\nCONFIG_HAVE_CMPXCHG_DOUBLE=y\nCONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y\nCONFIG_HAVE_ARCH_SECCOMP=y\nCONFIG_HAVE_ARCH_SECCOMP_FILTER=y\nCONFIG_SECCOMP=y\nCONFIG_SECCOMP_FILTER=y\n# CONFIG_SECCOMP_CACHE_DEBUG is not set\nCONFIG_HAVE_ARCH_STACKLEAK=y\nCONFIG_HAVE_STACKPROTECTOR=y\nCONFIG_STACKPROTECTOR=y\nCONFIG_STACKPROTECTOR_STRONG=y\nCONFIG_ARCH_SUPPORTS_LTO_CLANG=y\nCONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y\nCONFIG_LTO_NONE=y\nCONFIG_ARCH_SUPPORTS_CFI_CLANG=y\nCONFIG_HAVE_CONTEXT_TRACKING=y\nCONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y\nCONFIG_HAVE_IRQ_TIME_ACCOUNTING=y\nCONFIG_HAVE_MOVE_PUD=y\nCONFIG_HAVE_MOVE_PMD=y\nCONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y\nCONFIG_HAVE_ARCH_HUGE_VMAP=y\nCONFIG_ARCH_WANT_HUGE_PMD_SHARE=y\nCONFIG_HAVE_MOD_ARCH_SPECIFIC=y\nCONFIG_MODULES_USE_ELF_RELA=y\nCONFIG_ARCH_HAS_ELF_RANDOMIZE=y\nCONFIG_HAVE_ARCH_MMAP_RND_BITS=y\nCONFIG_ARCH_MMAP_RND_BITS=18\nCONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS=11\nCONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_COMPAT_OLD_SIGACTION=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_HAVE_ARCH_VMAP_STACK=y\nCONFIG_VMAP_STACK=y\nCONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y\n# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set\nCONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y\nCONFIG_STRICT_KERNEL_RWX=y\nCONFIG_ARCH_HAS_STRICT_MODULE_RWX=y\nCONFIG_STRICT_MODULE_RWX=y\nCONFIG_HAVE_ARCH_COMPILER_H=y\nCONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y\nCONFIG_ARCH_USE_MEMREMAP_PROT=y\n# CONFIG_LOCK_EVENT_COUNTS is not set\nCONFIG_ARCH_HAS_RELR=y\nCONFIG_ARCH_WANT_LD_ORPHAN_WARN=y\nCONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y\n\n#\n# GCOV-based kernel profiling\n#\n# CONFIG_GCOV_KERNEL is not set\nCONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y\n# end of GCOV-based kernel profiling\n\nCONFIG_HAVE_GCC_PLUGINS=y\nCONFIG_GCC_PLUGINS=y\n# CONFIG_GCC_PLUGIN_CYC_COMPLEXITY is not set\n# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set\n# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set\n# end of General architecture-dependent options\n\nCONFIG_RT_MUTEXES=y\nCONFIG_BASE_SMALL=0\nCONFIG_MODULES=y\n# CONFIG_MODULE_FORCE_LOAD is not set\nCONFIG_MODULE_UNLOAD=y\n# CONFIG_MODULE_FORCE_UNLOAD is not set\n# CONFIG_MODVERSIONS is not set\n# CONFIG_MODULE_SRCVERSION_ALL is not set\n# CONFIG_MODULE_SIG is not set\nCONFIG_MODULE_COMPRESS_NONE=y\n# CONFIG_MODULE_COMPRESS_GZIP is not set\n# CONFIG_MODULE_COMPRESS_XZ is not set\n# CONFIG_MODULE_COMPRESS_ZSTD is not set\n# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set\nCONFIG_MODPROBE_PATH=\"/sbin/modprobe\"\n# CONFIG_TRIM_UNUSED_KSYMS is not set\nCONFIG_MODULES_TREE_LOOKUP=y\nCONFIG_BLOCK=y\nCONFIG_BLK_DEV_BSG_COMMON=y\n# CONFIG_BLK_DEV_BSGLIB is not set\n# CONFIG_BLK_DEV_INTEGRITY is not set\n# CONFIG_BLK_DEV_ZONED is not set\n# CONFIG_BLK_WBT is not set\nCONFIG_BLK_DEBUG_FS=y\n# CONFIG_BLK_SED_OPAL is not set\n# CONFIG_BLK_INLINE_ENCRYPTION is not set\n\n#\n# Partition Types\n#\n# CONFIG_PARTITION_ADVANCED is not set\nCONFIG_MSDOS_PARTITION=y\nCONFIG_EFI_PARTITION=y\n# end of Partition Types\n\nCONFIG_BLOCK_COMPAT=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BLK_MQ_VIRTIO=y\nCONFIG_BLK_PM=y\n\n#\n# IO Schedulers\n#\nCONFIG_MQ_IOSCHED_DEADLINE=y\nCONFIG_MQ_IOSCHED_KYBER=y\n# CONFIG_IOSCHED_BFQ is not set\n# end of IO Schedulers\n\nCONFIG_ASN1=y\nCONFIG_ARCH_INLINE_SPIN_TRYLOCK=y\nCONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH=y\nCONFIG_ARCH_INLINE_SPIN_LOCK=y\nCONFIG_ARCH_INLINE_SPIN_LOCK_BH=y\nCONFIG_ARCH_INLINE_SPIN_LOCK_IRQ=y\nCONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE=y\nCONFIG_ARCH_INLINE_SPIN_UNLOCK=y\nCONFIG_ARCH_INLINE_SPIN_UNLOCK_BH=y\nCONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ=y\nCONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE=y\nCONFIG_ARCH_INLINE_READ_LOCK=y\nCONFIG_ARCH_INLINE_READ_LOCK_BH=y\nCONFIG_ARCH_INLINE_READ_LOCK_IRQ=y\nCONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE=y\nCONFIG_ARCH_INLINE_READ_UNLOCK=y\nCONFIG_ARCH_INLINE_READ_UNLOCK_BH=y\nCONFIG_ARCH_INLINE_READ_UNLOCK_IRQ=y\nCONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE=y\nCONFIG_ARCH_INLINE_WRITE_LOCK=y\nCONFIG_ARCH_INLINE_WRITE_LOCK_BH=y\nCONFIG_ARCH_INLINE_WRITE_LOCK_IRQ=y\nCONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE=y\nCONFIG_ARCH_INLINE_WRITE_UNLOCK=y\nCONFIG_ARCH_INLINE_WRITE_UNLOCK_BH=y\nCONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ=y\nCONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE=y\nCONFIG_INLINE_SPIN_TRYLOCK=y\nCONFIG_INLINE_SPIN_TRYLOCK_BH=y\nCONFIG_INLINE_SPIN_LOCK=y\nCONFIG_INLINE_SPIN_LOCK_BH=y\nCONFIG_INLINE_SPIN_LOCK_IRQ=y\nCONFIG_INLINE_SPIN_LOCK_IRQSAVE=y\nCONFIG_INLINE_SPIN_UNLOCK_BH=y\nCONFIG_INLINE_SPIN_UNLOCK_IRQ=y\nCONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE=y\nCONFIG_INLINE_READ_LOCK=y\nCONFIG_INLINE_READ_LOCK_BH=y\nCONFIG_INLINE_READ_LOCK_IRQ=y\nCONFIG_INLINE_READ_LOCK_IRQSAVE=y\nCONFIG_INLINE_READ_UNLOCK=y\nCONFIG_INLINE_READ_UNLOCK_BH=y\nCONFIG_INLINE_READ_UNLOCK_IRQ=y\nCONFIG_INLINE_READ_UNLOCK_IRQRESTORE=y\nCONFIG_INLINE_WRITE_LOCK=y\nCONFIG_INLINE_WRITE_LOCK_BH=y\nCONFIG_INLINE_WRITE_LOCK_IRQ=y\nCONFIG_INLINE_WRITE_LOCK_IRQSAVE=y\nCONFIG_INLINE_WRITE_UNLOCK=y\nCONFIG_INLINE_WRITE_UNLOCK_BH=y\nCONFIG_INLINE_WRITE_UNLOCK_IRQ=y\nCONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE=y\nCONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_ARCH_USE_QUEUED_SPINLOCKS=y\nCONFIG_QUEUED_SPINLOCKS=y\nCONFIG_ARCH_USE_QUEUED_RWLOCKS=y\nCONFIG_QUEUED_RWLOCKS=y\nCONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y\nCONFIG_ARCH_HAS_SYSCALL_WRAPPER=y\nCONFIG_FREEZER=y\n\n#\n# Executable file formats\n#\nCONFIG_BINFMT_ELF=y\nCONFIG_COMPAT_BINFMT_ELF=y\nCONFIG_ARCH_BINFMT_ELF_STATE=y\nCONFIG_ARCH_HAVE_ELF_PROT=y\nCONFIG_ARCH_USE_GNU_PROPERTY=y\nCONFIG_ELFCORE=y\nCONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y\nCONFIG_BINFMT_SCRIPT=y\n# CONFIG_BINFMT_MISC is not set\nCONFIG_COREDUMP=y\n# end of Executable file formats\n\n#\n# Memory Management options\n#\nCONFIG_SPARSEMEM=y\nCONFIG_SPARSEMEM_EXTREME=y\nCONFIG_SPARSEMEM_VMEMMAP_ENABLE=y\nCONFIG_SPARSEMEM_VMEMMAP=y\nCONFIG_HAVE_FAST_GUP=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_MEMORY_ISOLATION=y\nCONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y\n# CONFIG_MEMORY_HOTPLUG is not set\nCONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y\nCONFIG_SPLIT_PTLOCK_CPUS=4\nCONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y\nCONFIG_COMPACTION=y\n# CONFIG_PAGE_REPORTING is not set\nCONFIG_MIGRATION=y\nCONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y\nCONFIG_ARCH_ENABLE_THP_MIGRATION=y\nCONFIG_CONTIG_ALLOC=y\nCONFIG_PHYS_ADDR_T_64BIT=y\n# CONFIG_KSM is not set\nCONFIG_DEFAULT_MMAP_MIN_ADDR=32768\nCONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y\n# CONFIG_MEMORY_FAILURE is not set\nCONFIG_TRANSPARENT_HUGEPAGE=y\n# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set\nCONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y\n# CONFIG_CLEANCACHE is not set\n# CONFIG_FRONTSWAP is not set\nCONFIG_CMA=y\n# CONFIG_CMA_DEBUG is not set\n# CONFIG_CMA_DEBUGFS is not set\n# CONFIG_CMA_SYSFS is not set\nCONFIG_CMA_AREAS=7\n# CONFIG_ZPOOL is not set\n# CONFIG_ZSMALLOC is not set\nCONFIG_GENERIC_EARLY_IOREMAP=y\n# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set\n# CONFIG_IDLE_PAGE_TRACKING is not set\nCONFIG_ARCH_HAS_CACHE_LINE_SIZE=y\nCONFIG_ARCH_HAS_PTE_DEVMAP=y\nCONFIG_ARCH_HAS_ZONE_DMA_SET=y\nCONFIG_ZONE_DMA=y\nCONFIG_ZONE_DMA32=y\nCONFIG_ARCH_USES_HIGH_VMA_FLAGS=y\n# CONFIG_PERCPU_STATS is not set\n# CONFIG_GUP_TEST is not set\n# CONFIG_READ_ONLY_THP_FOR_FS is not set\nCONFIG_ARCH_HAS_PTE_SPECIAL=y\n\n#\n# Data Access Monitoring\n#\n# CONFIG_DAMON is not set\n# end of Data Access Monitoring\n# end of Memory Management options\n\nCONFIG_NET=y\nCONFIG_COMPAT_NETLINK_MESSAGES=y\nCONFIG_NET_INGRESS=y\nCONFIG_SKB_EXTENSIONS=y\n\n#\n# Networking options\n#\nCONFIG_PACKET=y\n# CONFIG_PACKET_DIAG is not set\nCONFIG_UNIX=y\nCONFIG_UNIX_SCM=y\nCONFIG_AF_UNIX_OOB=y\n# CONFIG_UNIX_DIAG is not set\n# CONFIG_TLS is not set\nCONFIG_XFRM=y\nCONFIG_XFRM_ALGO=y\nCONFIG_XFRM_USER=y\n# CONFIG_XFRM_INTERFACE is not set\n# CONFIG_XFRM_SUB_POLICY is not set\nCONFIG_XFRM_MIGRATE=y\n# CONFIG_XFRM_STATISTICS is not set\nCONFIG_NET_KEY=y\nCONFIG_NET_KEY_MIGRATE=y\nCONFIG_INET=y\nCONFIG_IP_MULTICAST=y\n# CONFIG_IP_ADVANCED_ROUTER is not set\nCONFIG_IP_PNP=y\nCONFIG_IP_PNP_DHCP=y\nCONFIG_IP_PNP_BOOTP=y\nCONFIG_IP_PNP_RARP=y\nCONFIG_NET_IPIP=y\n# CONFIG_NET_IPGRE_DEMUX is not set\nCONFIG_NET_IP_TUNNEL=y\nCONFIG_IP_MROUTE_COMMON=y\nCONFIG_IP_MROUTE=y\n# CONFIG_IP_PIMSM_V1 is not set\n# CONFIG_IP_PIMSM_V2 is not set\nCONFIG_SYN_COOKIES=y\nCONFIG_NET_IPVTI=y\n# CONFIG_NET_FOU is not set\n# CONFIG_NET_FOU_IP_TUNNELS is not set\n# CONFIG_INET_AH is not set\n# CONFIG_INET_ESP is not set\n# CONFIG_INET_IPCOMP is not set\nCONFIG_INET_TUNNEL=y\nCONFIG_INET_DIAG=y\nCONFIG_INET_TCP_DIAG=y\n# CONFIG_INET_UDP_DIAG is not set\n# CONFIG_INET_RAW_DIAG is not set\n# CONFIG_INET_DIAG_DESTROY is not set\n# CONFIG_TCP_CONG_ADVANCED is not set\nCONFIG_TCP_CONG_CUBIC=y\nCONFIG_DEFAULT_TCP_CONG=\"cubic\"\n# CONFIG_TCP_MD5SIG is not set\nCONFIG_IPV6=y\n# CONFIG_IPV6_ROUTER_PREF is not set\n# CONFIG_IPV6_OPTIMISTIC_DAD is not set\n# CONFIG_INET6_AH is not set\n# CONFIG_INET6_ESP is not set\n# CONFIG_INET6_IPCOMP is not set\n# CONFIG_IPV6_MIP6 is not set\n# CONFIG_IPV6_ILA is not set\nCONFIG_INET6_TUNNEL=y\nCONFIG_IPV6_VTI=y\nCONFIG_IPV6_SIT=y\n# CONFIG_IPV6_SIT_6RD is not set\nCONFIG_IPV6_NDISC_NODETYPE=y\nCONFIG_IPV6_TUNNEL=y\n# CONFIG_IPV6_MULTIPLE_TABLES is not set\n# CONFIG_IPV6_MROUTE is not set\n# CONFIG_IPV6_SEG6_LWTUNNEL is not set\n# CONFIG_IPV6_SEG6_HMAC is not set\n# CONFIG_IPV6_RPL_LWTUNNEL is not set\n# CONFIG_IPV6_IOAM6_LWTUNNEL is not set\nCONFIG_MPTCP=y\nCONFIG_INET_MPTCP_DIAG=y\nCONFIG_MPTCP_IPV6=y\nCONFIG_NETWORK_SECMARK=y\nCONFIG_NET_PTP_CLASSIFY=y\nCONFIG_NETWORK_PHY_TIMESTAMPING=y\nCONFIG_NETFILTER=y\nCONFIG_NETFILTER_ADVANCED=y\n# CONFIG_BRIDGE_NETFILTER is not set\n\n#\n# Core Netfilter Configuration\n#\nCONFIG_NETFILTER_INGRESS=y\nCONFIG_NETFILTER_NETLINK=y\nCONFIG_NETFILTER_FAMILY_BRIDGE=y\n# CONFIG_NETFILTER_NETLINK_ACCT is not set\n# CONFIG_NETFILTER_NETLINK_QUEUE is not set\nCONFIG_NETFILTER_NETLINK_LOG=y\n# CONFIG_NETFILTER_NETLINK_OSF is not set\nCONFIG_NF_CONNTRACK=m\nCONFIG_NF_LOG_SYSLOG=y\nCONFIG_NF_CONNTRACK_MARK=y\n# CONFIG_NF_CONNTRACK_SECMARK is not set\n# CONFIG_NF_CONNTRACK_ZONES is not set\nCONFIG_NF_CONNTRACK_PROCFS=y\n# CONFIG_NF_CONNTRACK_EVENTS is not set\n# CONFIG_NF_CONNTRACK_TIMEOUT is not set\n# CONFIG_NF_CONNTRACK_TIMESTAMP is not set\n# CONFIG_NF_CONNTRACK_LABELS is not set\nCONFIG_NF_CT_PROTO_DCCP=y\nCONFIG_NF_CT_PROTO_SCTP=y\nCONFIG_NF_CT_PROTO_UDPLITE=y\n# CONFIG_NF_CONNTRACK_AMANDA is not set\n# CONFIG_NF_CONNTRACK_FTP is not set\n# CONFIG_NF_CONNTRACK_H323 is not set\n# CONFIG_NF_CONNTRACK_IRC is not set\n# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set\n# CONFIG_NF_CONNTRACK_SNMP is not set\n# CONFIG_NF_CONNTRACK_PPTP is not set\n# CONFIG_NF_CONNTRACK_SANE is not set\n# CONFIG_NF_CONNTRACK_SIP is not set\n# CONFIG_NF_CONNTRACK_TFTP is not set\nCONFIG_NF_CT_NETLINK=m\n# CONFIG_NETFILTER_NETLINK_GLUE_CT is not set\n# CONFIG_NF_NAT is not set\n# CONFIG_NF_TABLES is not set\nCONFIG_NETFILTER_XTABLES=y\nCONFIG_NETFILTER_XTABLES_COMPAT=y\n\n#\n# Xtables combined modules\n#\nCONFIG_NETFILTER_XT_MARK=y\nCONFIG_NETFILTER_XT_CONNMARK=m\n\n#\n# Xtables targets\n#\n# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set\nCONFIG_NETFILTER_XT_TARGET_CHECKSUM=y\n# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set\n# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set\n# CONFIG_NETFILTER_XT_TARGET_DSCP is not set\n# CONFIG_NETFILTER_XT_TARGET_HL is not set\n# CONFIG_NETFILTER_XT_TARGET_HMARK is not set\n# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set\n# CONFIG_NETFILTER_XT_TARGET_LED is not set\nCONFIG_NETFILTER_XT_TARGET_LOG=y\n# CONFIG_NETFILTER_XT_TARGET_MARK is not set\n# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set\n# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set\n# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set\n# CONFIG_NETFILTER_XT_TARGET_TEE is not set\n# CONFIG_NETFILTER_XT_TARGET_TPROXY is not set\n# CONFIG_NETFILTER_XT_TARGET_SECMARK is not set\n# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set\n# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set\n\n#\n# Xtables matches\n#\n# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set\n# CONFIG_NETFILTER_XT_MATCH_BPF is not set\n# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set\n# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set\n# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set\n# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set\n# CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set\n# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set\nCONFIG_NETFILTER_XT_MATCH_CONNMARK=m\nCONFIG_NETFILTER_XT_MATCH_CONNTRACK=m\n# CONFIG_NETFILTER_XT_MATCH_CPU is not set\n# CONFIG_NETFILTER_XT_MATCH_DCCP is not set\n# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set\n# CONFIG_NETFILTER_XT_MATCH_DSCP is not set\n# CONFIG_NETFILTER_XT_MATCH_ECN is not set\n# CONFIG_NETFILTER_XT_MATCH_ESP is not set\n# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set\n# CONFIG_NETFILTER_XT_MATCH_HELPER is not set\n# CONFIG_NETFILTER_XT_MATCH_HL is not set\n# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set\n# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set\n# CONFIG_NETFILTER_XT_MATCH_L2TP is not set\n# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set\nCONFIG_NETFILTER_XT_MATCH_LIMIT=y\nCONFIG_NETFILTER_XT_MATCH_MAC=y\n# CONFIG_NETFILTER_XT_MATCH_MARK is not set\nCONFIG_NETFILTER_XT_MATCH_MULTIPORT=y\n# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set\n# CONFIG_NETFILTER_XT_MATCH_OSF is not set\n# CONFIG_NETFILTER_XT_MATCH_OWNER is not set\n# CONFIG_NETFILTER_XT_MATCH_POLICY is not set\n# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set\n# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set\n# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set\n# CONFIG_NETFILTER_XT_MATCH_REALM is not set\n# CONFIG_NETFILTER_XT_MATCH_RECENT is not set\n# CONFIG_NETFILTER_XT_MATCH_SCTP is not set\n# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set\nCONFIG_NETFILTER_XT_MATCH_STATE=m\n# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set\n# CONFIG_NETFILTER_XT_MATCH_STRING is not set\n# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set\n# CONFIG_NETFILTER_XT_MATCH_TIME is not set\n# CONFIG_NETFILTER_XT_MATCH_U32 is not set\n# end of Core Netfilter Configuration\n\n# CONFIG_IP_SET is not set\n# CONFIG_IP_VS is not set\n\n#\n# IP: Netfilter Configuration\n#\nCONFIG_NF_DEFRAG_IPV4=m\n# CONFIG_NF_SOCKET_IPV4 is not set\n# CONFIG_NF_TPROXY_IPV4 is not set\n# CONFIG_NF_DUP_IPV4 is not set\n# CONFIG_NF_LOG_ARP is not set\n# CONFIG_NF_LOG_IPV4 is not set\nCONFIG_NF_REJECT_IPV4=y\nCONFIG_IP_NF_IPTABLES=y\n# CONFIG_IP_NF_MATCH_AH is not set\n# CONFIG_IP_NF_MATCH_ECN is not set\n# CONFIG_IP_NF_MATCH_RPFILTER is not set\n# CONFIG_IP_NF_MATCH_TTL is not set\nCONFIG_IP_NF_FILTER=y\nCONFIG_IP_NF_TARGET_REJECT=y\n# CONFIG_IP_NF_TARGET_SYNPROXY is not set\n# CONFIG_IP_NF_NAT is not set\nCONFIG_IP_NF_MANGLE=y\n# CONFIG_IP_NF_TARGET_CLUSTERIP is not set\n# CONFIG_IP_NF_TARGET_ECN is not set\n# CONFIG_IP_NF_TARGET_TTL is not set\n# CONFIG_IP_NF_RAW is not set\n# CONFIG_IP_NF_ARPTABLES is not set\n# end of IP: Netfilter Configuration\n\n#\n# IPv6: Netfilter Configuration\n#\n# CONFIG_NF_SOCKET_IPV6 is not set\n# CONFIG_NF_TPROXY_IPV6 is not set\n# CONFIG_NF_DUP_IPV6 is not set\nCONFIG_NF_REJECT_IPV6=y\nCONFIG_NF_LOG_IPV6=y\nCONFIG_IP6_NF_IPTABLES=y\n# CONFIG_IP6_NF_MATCH_AH is not set\n# CONFIG_IP6_NF_MATCH_EUI64 is not set\n# CONFIG_IP6_NF_MATCH_FRAG is not set\n# CONFIG_IP6_NF_MATCH_OPTS is not set\n# CONFIG_IP6_NF_MATCH_HL is not set\n# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set\n# CONFIG_IP6_NF_MATCH_MH is not set\n# CONFIG_IP6_NF_MATCH_RPFILTER is not set\n# CONFIG_IP6_NF_MATCH_RT is not set\n# CONFIG_IP6_NF_MATCH_SRH is not set\n# CONFIG_IP6_NF_TARGET_HL is not set\nCONFIG_IP6_NF_FILTER=y\nCONFIG_IP6_NF_TARGET_REJECT=y\n# CONFIG_IP6_NF_TARGET_SYNPROXY is not set\nCONFIG_IP6_NF_MANGLE=y\n# CONFIG_IP6_NF_RAW is not set\n# CONFIG_IP6_NF_NAT is not set\n# end of IPv6: Netfilter Configuration\n\nCONFIG_NF_DEFRAG_IPV6=m\n# CONFIG_NF_CONNTRACK_BRIDGE is not set\nCONFIG_BRIDGE_NF_EBTABLES=y\n# CONFIG_BRIDGE_EBT_BROUTE is not set\nCONFIG_BRIDGE_EBT_T_FILTER=y\nCONFIG_BRIDGE_EBT_T_NAT=y\n# CONFIG_BRIDGE_EBT_802_3 is not set\n# CONFIG_BRIDGE_EBT_AMONG is not set\n# CONFIG_BRIDGE_EBT_ARP is not set\n# CONFIG_BRIDGE_EBT_IP is not set\n# CONFIG_BRIDGE_EBT_IP6 is not set\n# CONFIG_BRIDGE_EBT_LIMIT is not set\n# CONFIG_BRIDGE_EBT_MARK is not set\n# CONFIG_BRIDGE_EBT_PKTTYPE is not set\n# CONFIG_BRIDGE_EBT_STP is not set\n# CONFIG_BRIDGE_EBT_VLAN is not set\n# CONFIG_BRIDGE_EBT_ARPREPLY is not set\n# CONFIG_BRIDGE_EBT_DNAT is not set\nCONFIG_BRIDGE_EBT_MARK_T=y\n# CONFIG_BRIDGE_EBT_REDIRECT is not set\n# CONFIG_BRIDGE_EBT_SNAT is not set\n# CONFIG_BRIDGE_EBT_LOG is not set\n# CONFIG_BRIDGE_EBT_NFLOG is not set\nCONFIG_BPFILTER=y\nCONFIG_BPFILTER_UMH=m\n# CONFIG_IP_DCCP is not set\n# CONFIG_IP_SCTP is not set\n# CONFIG_RDS is not set\n# CONFIG_TIPC is not set\n# CONFIG_ATM is not set\n# CONFIG_L2TP is not set\nCONFIG_STP=y\nCONFIG_BRIDGE=y\nCONFIG_BRIDGE_IGMP_SNOOPING=y\n# CONFIG_BRIDGE_MRP is not set\n# CONFIG_BRIDGE_CFM is not set\nCONFIG_NET_DSA=y\n# CONFIG_NET_DSA_TAG_AR9331 is not set\n# CONFIG_NET_DSA_TAG_BRCM is not set\n# CONFIG_NET_DSA_TAG_BRCM_LEGACY is not set\n# CONFIG_NET_DSA_TAG_BRCM_PREPEND is not set\n# CONFIG_NET_DSA_TAG_HELLCREEK is not set\n# CONFIG_NET_DSA_TAG_GSWIP is not set\n# CONFIG_NET_DSA_TAG_DSA is not set\n# CONFIG_NET_DSA_TAG_EDSA is not set\n# CONFIG_NET_DSA_TAG_MTK is not set\n# CONFIG_NET_DSA_TAG_KSZ is not set\n# CONFIG_NET_DSA_TAG_RTL4_A is not set\n# CONFIG_NET_DSA_TAG_OCELOT is not set\n# CONFIG_NET_DSA_TAG_OCELOT_8021Q is not set\n# CONFIG_NET_DSA_TAG_QCA is not set\n# CONFIG_NET_DSA_TAG_LAN9303 is not set\n# CONFIG_NET_DSA_TAG_SJA1105 is not set\n# CONFIG_NET_DSA_TAG_TRAILER is not set\n# CONFIG_NET_DSA_TAG_XRS700X is not set\n# CONFIG_VLAN_8021Q is not set\n# CONFIG_DECNET is not set\nCONFIG_LLC=y\n# CONFIG_LLC2 is not set\n# CONFIG_ATALK is not set\n# CONFIG_X25 is not set\n# CONFIG_LAPB is not set\n# CONFIG_PHONET is not set\n# CONFIG_6LOWPAN is not set\nCONFIG_IEEE802154=y\n# CONFIG_IEEE802154_NL802154_EXPERIMENTAL is not set\nCONFIG_IEEE802154_SOCKET=y\nCONFIG_MAC802154=y\nCONFIG_NET_SCHED=y\n\n#\n# Queueing/Scheduling\n#\n# CONFIG_NET_SCH_CBQ is not set\n# CONFIG_NET_SCH_HTB is not set\n# CONFIG_NET_SCH_HFSC is not set\n# CONFIG_NET_SCH_PRIO is not set\n# CONFIG_NET_SCH_MULTIQ is not set\n# CONFIG_NET_SCH_RED is not set\n# CONFIG_NET_SCH_SFB is not set\n# CONFIG_NET_SCH_SFQ is not set\n# CONFIG_NET_SCH_TEQL is not set\n# CONFIG_NET_SCH_TBF is not set\n# CONFIG_NET_SCH_CBS is not set\n# CONFIG_NET_SCH_ETF is not set\n# CONFIG_NET_SCH_TAPRIO is not set\n# CONFIG_NET_SCH_GRED is not set\n# CONFIG_NET_SCH_DSMARK is not set\n# CONFIG_NET_SCH_NETEM is not set\n# CONFIG_NET_SCH_DRR is not set\n# CONFIG_NET_SCH_MQPRIO is not set\n# CONFIG_NET_SCH_SKBPRIO is not set\n# CONFIG_NET_SCH_CHOKE is not set\n# CONFIG_NET_SCH_QFQ is not set\n# CONFIG_NET_SCH_CODEL is not set\n# CONFIG_NET_SCH_FQ_CODEL is not set\n# CONFIG_NET_SCH_CAKE is not set\n# CONFIG_NET_SCH_FQ is not set\n# CONFIG_NET_SCH_HHF is not set\n# CONFIG_NET_SCH_PIE is not set\n# CONFIG_NET_SCH_PLUG is not set\n# CONFIG_NET_SCH_ETS is not set\n# CONFIG_NET_SCH_DEFAULT is not set\n\n#\n# Classification\n#\n# CONFIG_NET_CLS_BASIC is not set\n# CONFIG_NET_CLS_TCINDEX is not set\n# CONFIG_NET_CLS_ROUTE4 is not set\n# CONFIG_NET_CLS_FW is not set\n# CONFIG_NET_CLS_U32 is not set\n# CONFIG_NET_CLS_RSVP is not set\n# CONFIG_NET_CLS_RSVP6 is not set\n# CONFIG_NET_CLS_FLOW is not set\n# CONFIG_NET_CLS_CGROUP is not set\n# CONFIG_NET_CLS_BPF is not set\n# CONFIG_NET_CLS_FLOWER is not set\n# CONFIG_NET_CLS_MATCHALL is not set\n# CONFIG_NET_EMATCH is not set\n# CONFIG_NET_CLS_ACT is not set\nCONFIG_NET_SCH_FIFO=y\n# CONFIG_DCB is not set\nCONFIG_DNS_RESOLVER=y\nCONFIG_BATMAN_ADV=y\nCONFIG_BATMAN_ADV_BATMAN_V=y\nCONFIG_BATMAN_ADV_BLA=y\nCONFIG_BATMAN_ADV_DAT=y\n# CONFIG_BATMAN_ADV_NC is not set\nCONFIG_BATMAN_ADV_MCAST=y\n# CONFIG_BATMAN_ADV_DEBUG is not set\n# CONFIG_OPENVSWITCH is not set\n# CONFIG_VSOCKETS is not set\n# CONFIG_NETLINK_DIAG is not set\n# CONFIG_MPLS is not set\n# CONFIG_NET_NSH is not set\n# CONFIG_HSR is not set\nCONFIG_NET_SWITCHDEV=y\n# CONFIG_NET_L3_MASTER_DEV is not set\n# CONFIG_QRTR is not set\n# CONFIG_NET_NCSI is not set\nCONFIG_PCPU_DEV_REFCNT=y\nCONFIG_RPS=y\nCONFIG_RFS_ACCEL=y\nCONFIG_SOCK_RX_QUEUE_MAPPING=y\nCONFIG_XPS=y\n# CONFIG_CGROUP_NET_PRIO is not set\n# CONFIG_CGROUP_NET_CLASSID is not set\nCONFIG_NET_RX_BUSY_POLL=y\nCONFIG_BQL=y\nCONFIG_NET_FLOW_LIMIT=y\n\n#\n# Network testing\n#\nCONFIG_NET_PKTGEN=y\n# end of Network testing\n# end of Networking options\n\n# CONFIG_HAMRADIO is not set\nCONFIG_CAN=y\nCONFIG_CAN_RAW=y\nCONFIG_CAN_BCM=y\nCONFIG_CAN_GW=y\n# CONFIG_CAN_J1939 is not set\n# CONFIG_CAN_ISOTP is not set\n\n#\n# CAN Device Drivers\n#\n# CONFIG_CAN_VCAN is not set\n# CONFIG_CAN_VXCAN is not set\n# CONFIG_CAN_SLCAN is not set\nCONFIG_CAN_DEV=y\nCONFIG_CAN_CALC_BITTIMING=y\n# CONFIG_CAN_FLEXCAN is not set\n# CONFIG_CAN_GRCAN is not set\n# CONFIG_CAN_KVASER_PCIEFD is not set\nCONFIG_CAN_XILINXCAN=y\n# CONFIG_CAN_C_CAN is not set\n# CONFIG_CAN_CC770 is not set\n# CONFIG_CAN_IFI_CANFD is not set\n# CONFIG_CAN_M_CAN is not set\n# CONFIG_CAN_PEAK_PCIEFD is not set\n# CONFIG_CAN_SJA1000 is not set\n# CONFIG_CAN_SOFTING is not set\n\n#\n# CAN SPI interfaces\n#\n# CONFIG_CAN_HI311X is not set\n# CONFIG_CAN_MCP251X is not set\n# CONFIG_CAN_MCP251XFD is not set\n# end of CAN SPI interfaces\n\n#\n# CAN USB interfaces\n#\n# CONFIG_CAN_8DEV_USB is not set\n# CONFIG_CAN_EMS_USB is not set\n# CONFIG_CAN_ESD_USB2 is not set\n# CONFIG_CAN_ETAS_ES58X is not set\n# CONFIG_CAN_GS_USB is not set\n# CONFIG_CAN_KVASER_USB is not set\n# CONFIG_CAN_MCBA_USB is not set\n# CONFIG_CAN_PEAK_USB is not set\n# CONFIG_CAN_UCAN is not set\n# end of CAN USB interfaces\n\n# CONFIG_CAN_DEBUG_DEVICES is not set\n# end of CAN Device Drivers\n\nCONFIG_BT=y\nCONFIG_BT_BREDR=y\nCONFIG_BT_RFCOMM=y\nCONFIG_BT_RFCOMM_TTY=y\nCONFIG_BT_BNEP=y\nCONFIG_BT_BNEP_MC_FILTER=y\nCONFIG_BT_BNEP_PROTO_FILTER=y\nCONFIG_BT_HIDP=y\n# CONFIG_BT_HS is not set\nCONFIG_BT_LE=y\nCONFIG_BT_LEDS=y\n# CONFIG_BT_MSFTEXT is not set\n# CONFIG_BT_AOSPEXT is not set\nCONFIG_BT_DEBUGFS=y\n# CONFIG_BT_SELFTEST is not set\n# CONFIG_BT_FEATURE_DEBUG is not set\n\n#\n# Bluetooth device drivers\n#\nCONFIG_BT_INTEL=y\nCONFIG_BT_BCM=y\nCONFIG_BT_RTL=y\nCONFIG_BT_QCA=y\nCONFIG_BT_HCIBTUSB=y\n# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set\nCONFIG_BT_HCIBTUSB_BCM=y\n# CONFIG_BT_HCIBTUSB_MTK is not set\nCONFIG_BT_HCIBTUSB_RTL=y\nCONFIG_BT_HCIBTSDIO=y\nCONFIG_BT_HCIUART=y\nCONFIG_BT_HCIUART_SERDEV=y\nCONFIG_BT_HCIUART_H4=y\n# CONFIG_BT_HCIUART_NOKIA is not set\nCONFIG_BT_HCIUART_BCSP=y\nCONFIG_BT_HCIUART_ATH3K=y\nCONFIG_BT_HCIUART_LL=y\nCONFIG_BT_HCIUART_3WIRE=y\nCONFIG_BT_HCIUART_INTEL=y\n# CONFIG_BT_HCIUART_BCM is not set\n# CONFIG_BT_HCIUART_RTL is not set\nCONFIG_BT_HCIUART_QCA=y\n# CONFIG_BT_HCIUART_AG6XX is not set\n# CONFIG_BT_HCIUART_MRVL is not set\nCONFIG_BT_HCIBCM203X=y\nCONFIG_BT_HCIBPA10X=y\nCONFIG_BT_HCIBFUSB=y\nCONFIG_BT_HCIVHCI=y\nCONFIG_BT_MRVL=y\nCONFIG_BT_MRVL_SDIO=y\nCONFIG_BT_ATH3K=y\n# CONFIG_BT_MTKSDIO is not set\n# CONFIG_BT_MTKUART is not set\n# CONFIG_BT_VIRTIO is not set\n# end of Bluetooth device drivers\n\n# CONFIG_AF_RXRPC is not set\n# CONFIG_AF_KCM is not set\n# CONFIG_MCTP is not set\nCONFIG_WIRELESS=y\nCONFIG_WEXT_CORE=y\nCONFIG_WEXT_PROC=y\nCONFIG_CFG80211=y\nCONFIG_NL80211_TESTMODE=y\n# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set\nCONFIG_CFG80211_CERTIFICATION_ONUS=y\nCONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y\nCONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y\nCONFIG_CFG80211_EXTRA_REGDB_KEYDIR=\"\"\nCONFIG_CFG80211_REG_CELLULAR_HINTS=y\nCONFIG_CFG80211_REG_RELAX_NO_IR=y\nCONFIG_CFG80211_DEFAULT_PS=y\nCONFIG_CFG80211_DEBUGFS=y\nCONFIG_CFG80211_CRDA_SUPPORT=y\nCONFIG_CFG80211_WEXT=y\nCONFIG_MAC80211=y\nCONFIG_MAC80211_HAS_RC=y\nCONFIG_MAC80211_RC_MINSTREL=y\nCONFIG_MAC80211_RC_DEFAULT_MINSTREL=y\nCONFIG_MAC80211_RC_DEFAULT=\"minstrel_ht\"\nCONFIG_MAC80211_MESH=y\nCONFIG_MAC80211_LEDS=y\nCONFIG_MAC80211_DEBUGFS=y\nCONFIG_MAC80211_MESSAGE_TRACING=y\nCONFIG_MAC80211_DEBUG_MENU=y\n# CONFIG_MAC80211_NOINLINE is not set\nCONFIG_MAC80211_VERBOSE_DEBUG=y\nCONFIG_MAC80211_MLME_DEBUG=y\nCONFIG_MAC80211_STA_DEBUG=y\nCONFIG_MAC80211_HT_DEBUG=y\n# CONFIG_MAC80211_OCB_DEBUG is not set\n# CONFIG_MAC80211_IBSS_DEBUG is not set\nCONFIG_MAC80211_PS_DEBUG=y\n# CONFIG_MAC80211_MPL_DEBUG is not set\n# CONFIG_MAC80211_MPATH_DEBUG is not set\n# CONFIG_MAC80211_MHWMP_DEBUG is not set\n# CONFIG_MAC80211_MESH_SYNC_DEBUG is not set\n# CONFIG_MAC80211_MESH_CSA_DEBUG is not set\n# CONFIG_MAC80211_MESH_PS_DEBUG is not set\n# CONFIG_MAC80211_TDLS_DEBUG is not set\nCONFIG_MAC80211_DEBUG_COUNTERS=y\nCONFIG_MAC80211_STA_HASH_MAX_SIZE=0\nCONFIG_RFKILL=y\nCONFIG_RFKILL_LEDS=y\nCONFIG_RFKILL_INPUT=y\nCONFIG_RFKILL_GPIO=y\nCONFIG_NET_9P=y\n# CONFIG_NET_9P_VIRTIO is not set\n# CONFIG_NET_9P_DEBUG is not set\n# CONFIG_CAIF is not set\n# CONFIG_CEPH_LIB is not set\n# CONFIG_NFC is not set\n# CONFIG_PSAMPLE is not set\n# CONFIG_NET_IFE is not set\n# CONFIG_LWTUNNEL is not set\nCONFIG_DST_CACHE=y\nCONFIG_GRO_CELLS=y\nCONFIG_NET_SELFTESTS=y\nCONFIG_NET_DEVLINK=y\n# CONFIG_FAILOVER is not set\nCONFIG_ETHTOOL_NETLINK=y\n\n#\n# Device Drivers\n#\nCONFIG_ARM_AMBA=y\nCONFIG_HAVE_PCI=y\nCONFIG_PCI=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DOMAINS_GENERIC=y\nCONFIG_PCI_SYSCALL=y\n# CONFIG_PCIEPORTBUS is not set\nCONFIG_PCIEASPM=y\nCONFIG_PCIEASPM_DEFAULT=y\n# CONFIG_PCIEASPM_POWERSAVE is not set\n# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set\n# CONFIG_PCIEASPM_PERFORMANCE is not set\n# CONFIG_PCIE_PTM is not set\nCONFIG_PCI_MSI=y\nCONFIG_PCI_MSI_IRQ_DOMAIN=y\nCONFIG_PCI_QUIRKS=y\n# CONFIG_PCI_DEBUG is not set\n# CONFIG_PCI_STUB is not set\n# CONFIG_PCI_IOV is not set\n# CONFIG_PCI_PRI is not set\n# CONFIG_PCI_PASID is not set\n# CONFIG_PCIE_BUS_TUNE_OFF is not set\nCONFIG_PCIE_BUS_DEFAULT=y\n# CONFIG_PCIE_BUS_SAFE is not set\n# CONFIG_PCIE_BUS_PERFORMANCE is not set\n# CONFIG_PCIE_BUS_PEER2PEER is not set\n# CONFIG_HOTPLUG_PCI is not set\n\n#\n# PCI controller drivers\n#\nCONFIG_PCIE_XILINX_NWL=y\n# CONFIG_PCI_FTPCI100 is not set\n# CONFIG_PCI_HOST_GENERIC is not set\n# CONFIG_PCIE_XILINX is not set\n# CONFIG_PCIE_XILINX_CPM is not set\n# CONFIG_PCIE_XDMA_PL is not set\n# CONFIG_PCI_XGENE is not set\n# CONFIG_PCIE_ALTERA is not set\n# CONFIG_PCI_HOST_THUNDER_PEM is not set\n# CONFIG_PCI_HOST_THUNDER_ECAM is not set\n# CONFIG_PCIE_MICROCHIP_HOST is not set\n\n#\n# DesignWare PCI Core Support\n#\n# CONFIG_PCIE_DW_PLAT_HOST is not set\n# CONFIG_PCI_HISI is not set\n# CONFIG_PCIE_KIRIN is not set\n# CONFIG_PCI_MESON is not set\n# CONFIG_PCIE_AL is not set\n# end of DesignWare PCI Core Support\n\n#\n# Mobiveil PCIe Core Support\n#\n# CONFIG_PCIE_MOBIVEIL_PLAT is not set\n# end of Mobiveil PCIe Core Support\n\n#\n# Cadence PCIe controllers support\n#\n# CONFIG_PCIE_CADENCE_PLAT_HOST is not set\n# CONFIG_PCI_J721E_HOST is not set\n# end of Cadence PCIe controllers support\n# end of PCI controller drivers\n\n#\n# PCI Endpoint\n#\n# CONFIG_PCI_ENDPOINT is not set\n# end of PCI Endpoint\n\n#\n# PCI switch controller drivers\n#\n# CONFIG_PCI_SW_SWITCHTEC is not set\n# end of PCI switch controller drivers\n\n# CONFIG_CXL_BUS is not set\n# CONFIG_PCCARD is not set\n# CONFIG_RAPIDIO is not set\n\n#\n# Generic Driver Options\n#\n# CONFIG_UEVENT_HELPER is not set\nCONFIG_DEVTMPFS=y\nCONFIG_DEVTMPFS_MOUNT=y\nCONFIG_STANDALONE=y\nCONFIG_PREVENT_FIRMWARE_BUILD=y\n\n#\n# Firmware loader\n#\nCONFIG_FW_LOADER=y\nCONFIG_EXTRA_FIRMWARE=\"ad9144_fmc_ebz_ad9516.stp Mykonos_M3.bin TaliseStream.bin TaliseTDDArmFirmware.bin TaliseTxArmFirmware.bin TaliseRxArmFirmware.bin adau1761.bin Navassa_EvaluationFw.bin RxGainTable.csv RxGainTable_GainCompensated.csv ORxGainTable.csv TxAttenTable.csv Navassa_Stream.bin Navassa_CMOS_profile.json Navassa_LVDS_profile.json Navassa_CMOS_profile_adrv9003.json Navassa_LVDS_profile_adrv9003.json ADRV9025_DPDCORE_FW.bin ADRV9025_FW.bin ADRV9025_RxGainTable.csv ADRV9025_TxAttenTable.csv stream_image_6E3E00EFB74FE7D465FA88A171B81B8F.bin ActiveUseCase.profile ActiveUtilInit.profile\"\nCONFIG_EXTRA_FIRMWARE_DIR=\"./firmware\"\n# CONFIG_FW_LOADER_USER_HELPER is not set\n# CONFIG_FW_LOADER_COMPRESS is not set\nCONFIG_FW_CACHE=y\n# end of Firmware loader\n\nCONFIG_WANT_DEV_COREDUMP=y\nCONFIG_ALLOW_DEV_COREDUMP=y\nCONFIG_DEV_COREDUMP=y\n# CONFIG_DEBUG_DRIVER is not set\n# CONFIG_DEBUG_DEVRES is not set\n# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set\n# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_CPU_VULNERABILITIES=y\nCONFIG_SOC_BUS=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_I2C=y\nCONFIG_REGMAP_SPI=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGMAP_IRQ=y\nCONFIG_DMA_SHARED_BUFFER=y\n# CONFIG_DMA_FENCE_TRACE is not set\nCONFIG_GENERIC_ARCH_TOPOLOGY=y\n# end of Generic Driver Options\n\n#\n# Bus devices\n#\n# CONFIG_BRCMSTB_GISB_ARB is not set\n# CONFIG_MOXTET is not set\n# CONFIG_VEXPRESS_CONFIG is not set\n# CONFIG_MHI_BUS is not set\n# end of Bus devices\n\nCONFIG_CONNECTOR=y\nCONFIG_PROC_EVENTS=y\n\n#\n# Firmware Drivers\n#\n\n#\n# ARM System Control and Management Interface Protocol\n#\n# CONFIG_ARM_SCMI_PROTOCOL is not set\n# end of ARM System Control and Management Interface Protocol\n\n# CONFIG_ARM_SCPI_PROTOCOL is not set\n# CONFIG_ARM_SDE_INTERFACE is not set\n# CONFIG_FIRMWARE_MEMMAP is not set\n# CONFIG_FW_CFG_SYSFS is not set\nCONFIG_SYSFB=y\n# CONFIG_SYSFB_SIMPLEFB is not set\n# CONFIG_ARM_FFA_TRANSPORT is not set\n# CONFIG_GOOGLE_FIRMWARE is not set\n\n#\n# EFI (Extensible Firmware Interface) Support\n#\nCONFIG_EFI_ESRT=y\nCONFIG_EFI_PARAMS_FROM_FDT=y\nCONFIG_EFI_RUNTIME_WRAPPERS=y\nCONFIG_EFI_GENERIC_STUB=y\nCONFIG_EFI_ARMSTUB_DTB_LOADER=y\n# CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER is not set\n# CONFIG_EFI_BOOTLOADER_CONTROL is not set\n# CONFIG_EFI_CAPSULE_LOADER is not set\n# CONFIG_EFI_TEST is not set\n# CONFIG_RESET_ATTACK_MITIGATION is not set\n# CONFIG_EFI_DISABLE_PCI_DMA is not set\n# end of EFI (Extensible Firmware Interface) Support\n\nCONFIG_EFI_EARLYCON=y\nCONFIG_ARM_PSCI_FW=y\n# CONFIG_ARM_PSCI_CHECKER is not set\nCONFIG_HAVE_ARM_SMCCC=y\nCONFIG_HAVE_ARM_SMCCC_DISCOVERY=y\nCONFIG_ARM_SMCCC_SOC_ID=y\n\n#\n# Tegra firmware driver\n#\n# end of Tegra firmware driver\n\n#\n# Zynq MPSoC Firmware Drivers\n#\nCONFIG_ZYNQMP_FIRMWARE=y\n# CONFIG_ZYNQMP_FIRMWARE_DEBUG is not set\n# CONFIG_ZYNQMP_FIRMWARE_SECURE is not set\n# end of Zynq MPSoC Firmware Drivers\n# end of Firmware Drivers\n\n# CONFIG_GNSS is not set\nCONFIG_MTD=y\nCONFIG_MTD_TESTS=m\n\n#\n# Partition parsers\n#\n# CONFIG_MTD_AR7_PARTS is not set\nCONFIG_MTD_CMDLINE_PARTS=y\nCONFIG_MTD_OF_PARTS=y\n# CONFIG_MTD_AFS_PARTS is not set\n# CONFIG_MTD_REDBOOT_PARTS is not set\n# end of Partition parsers\n\n#\n# User Modules And Translation Layers\n#\nCONFIG_MTD_BLKDEVS=y\nCONFIG_MTD_BLOCK=y\n\n#\n# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK.\n#\n# CONFIG_FTL is not set\n# CONFIG_NFTL is not set\n# CONFIG_INFTL is not set\n# CONFIG_RFD_FTL is not set\n# CONFIG_SSFDC is not set\n# CONFIG_SM_FTL is not set\n# CONFIG_MTD_OOPS is not set\n# CONFIG_MTD_SWAP is not set\n# CONFIG_MTD_PARTITIONED_MASTER is not set\n\n#\n# RAM/ROM/Flash chip drivers\n#\nCONFIG_MTD_CFI=y\n# CONFIG_MTD_JEDECPROBE is not set\nCONFIG_MTD_GEN_PROBE=y\n# CONFIG_MTD_CFI_ADV_OPTIONS is not set\nCONFIG_MTD_MAP_BANK_WIDTH_1=y\nCONFIG_MTD_MAP_BANK_WIDTH_2=y\nCONFIG_MTD_MAP_BANK_WIDTH_4=y\nCONFIG_MTD_CFI_I1=y\nCONFIG_MTD_CFI_I2=y\nCONFIG_MTD_CFI_INTELEXT=y\n# CONFIG_MTD_CFI_AMDSTD is not set\n# CONFIG_MTD_CFI_STAA is not set\nCONFIG_MTD_CFI_UTIL=y\n# CONFIG_MTD_RAM is not set\n# CONFIG_MTD_ROM is not set\n# CONFIG_MTD_ABSENT is not set\n# end of RAM/ROM/Flash chip drivers\n\n#\n# Mapping drivers for chip access\n#\n# CONFIG_MTD_COMPLEX_MAPPINGS is not set\n# CONFIG_MTD_PHYSMAP is not set\n# CONFIG_MTD_INTEL_VR_NOR is not set\n# CONFIG_MTD_PLATRAM is not set\n# end of Mapping drivers for chip access\n\n#\n# Self-contained MTD device drivers\n#\n# CONFIG_MTD_PMC551 is not set\nCONFIG_MTD_DATAFLASH=y\n# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set\n# CONFIG_MTD_DATAFLASH_OTP is not set\n# CONFIG_MTD_MCHP23K256 is not set\n# CONFIG_MTD_MCHP48L640 is not set\n# CONFIG_MTD_SST25L is not set\n# CONFIG_MTD_SLRAM is not set\n# CONFIG_MTD_PHRAM is not set\n# CONFIG_MTD_MTDRAM is not set\n# CONFIG_MTD_BLOCK2MTD is not set\n\n#\n# Disk-On-Chip Device Drivers\n#\n# CONFIG_MTD_DOCG3 is not set\n# end of Self-contained MTD device drivers\n\n#\n# NAND\n#\n# CONFIG_MTD_ONENAND is not set\n# CONFIG_MTD_RAW_NAND is not set\n# CONFIG_MTD_SPI_NAND is not set\n\n#\n# ECC engine support\n#\n# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set\n# CONFIG_MTD_NAND_ECC_SW_BCH is not set\n# end of ECC engine support\n# end of NAND\n\n#\n# LPDDR & LPDDR2 PCM memory drivers\n#\n# CONFIG_MTD_LPDDR is not set\n# end of LPDDR & LPDDR2 PCM memory drivers\n\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y\n# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set\nCONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y\n# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set\n# CONFIG_MTD_UBI is not set\n# CONFIG_MTD_HYPERBUS is not set\nCONFIG_DTC=y\nCONFIG_OF=y\n# CONFIG_OF_UNITTEST is not set\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_DYNAMIC=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_RESERVED_MEM=y\nCONFIG_OF_RESOLVE=y\nCONFIG_OF_OVERLAY=y\nCONFIG_OF_CONFIGFS=y\n# CONFIG_PARPORT is not set\nCONFIG_BLK_DEV=y\n# CONFIG_BLK_DEV_NULL_BLK is not set\n# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_DEV_LOOP_MIN_COUNT=8\n# CONFIG_BLK_DEV_CRYPTOLOOP is not set\n# CONFIG_BLK_DEV_DRBD is not set\n# CONFIG_BLK_DEV_NBD is not set\n# CONFIG_BLK_DEV_SX8 is not set\nCONFIG_BLK_DEV_RAM=y\nCONFIG_BLK_DEV_RAM_COUNT=16\nCONFIG_BLK_DEV_RAM_SIZE=65536\n# CONFIG_CDROM_PKTCDVD is not set\n# CONFIG_ATA_OVER_ETH is not set\n# CONFIG_VIRTIO_BLK is not set\n# CONFIG_BLK_DEV_RBD is not set\n# CONFIG_BLK_DEV_RSXX is not set\n\n#\n# NVME Support\n#\n# CONFIG_BLK_DEV_NVME is not set\n# CONFIG_NVME_FC is not set\n# CONFIG_NVME_TCP is not set\n# CONFIG_NVME_TARGET is not set\n# end of NVME Support\n\n#\n# Misc devices\n#\nCONFIG_AD525X_DPOT=y\nCONFIG_AD525X_DPOT_I2C=y\nCONFIG_AD525X_DPOT_SPI=y\nCONFIG_ADI_AXI_DATA_OFFLOAD=y\nCONFIG_ADI_AXI_TDD=y\n# CONFIG_DUMMY_IRQ is not set\n# CONFIG_PHANTOM is not set\n# CONFIG_TIFM_CORE is not set\n# CONFIG_ICS932S401 is not set\n# CONFIG_ENCLOSURE_SERVICES is not set\n# CONFIG_HP_ILO is not set\n# CONFIG_APDS9802ALS is not set\n# CONFIG_ISL29003 is not set\n# CONFIG_ISL29020 is not set\n# CONFIG_SENSORS_TSL2550 is not set\n# CONFIG_SENSORS_BH1770 is not set\n# CONFIG_SENSORS_APDS990X is not set\n# CONFIG_HMC6352 is not set\n# CONFIG_DS1682 is not set\n# CONFIG_LATTICE_ECP3_CONFIG is not set\n# CONFIG_SRAM is not set\n# CONFIG_DW_XDATA_PCIE is not set\n# CONFIG_PCI_ENDPOINT_TEST is not set\nCONFIG_XILINX_SDFEC=y\n# CONFIG_XILINX_DPU is not set\n# CONFIG_XILINX_FLEX_PM is not set\n# CONFIG_XILINX_TRAFGEN is not set\n# CONFIG_XILINX_AIE is not set\n# CONFIG_HISI_HIKEY_USB is not set\nCONFIG_XILINX_JESD204B=y\nCONFIG_XILINX_JESD204B_PHY=y\n# CONFIG_C2PORT is not set\n\n#\n# EEPROM support\n#\nCONFIG_EEPROM_AT24=y\nCONFIG_EEPROM_AT25=y\n# CONFIG_EEPROM_LEGACY is not set\n# CONFIG_EEPROM_MAX6875 is not set\n# CONFIG_EEPROM_93CX6 is not set\n# CONFIG_EEPROM_93XX46 is not set\n# CONFIG_EEPROM_IDT_89HPESX is not set\n# CONFIG_EEPROM_EE1004 is not set\n# end of EEPROM support\n\n# CONFIG_CB710_CORE is not set\n\n#\n# Texas Instruments shared transport line discipline\n#\nCONFIG_TI_ST=y\n# end of Texas Instruments shared transport line discipline\n\n# CONFIG_SENSORS_LIS3_SPI is not set\n# CONFIG_SENSORS_LIS3_I2C is not set\n# CONFIG_ALTERA_STAPL is not set\n\n#\n# MathWorks IP Drivers\n#\nCONFIG_MATHWORKS_IP_CORE=y\nCONFIG_MWIPCORE=y\nCONFIG_MWIPCORE_DMA_STREAMING=y\nCONFIG_MWIPCORE_IIO_STREAMING=y\nCONFIG_MWIPCORE_IIO_MM=y\nCONFIG_MWIPCORE_IIO_SHAREDMEM=y\nCONFIG_MATHWORKS_GENERIC_OF=y\n# CONFIG_MATHWORKS_GENERIC_PCI is not set\n# end of MathWorks IP Drivers\n\n# CONFIG_GENWQE is not set\n# CONFIG_ECHO is not set\n# CONFIG_BCM_VK is not set\n# CONFIG_MISC_ALCOR_PCI is not set\n# CONFIG_MISC_RTSX_PCI is not set\n# CONFIG_MISC_RTSX_USB is not set\n# CONFIG_HABANA_AI is not set\n# CONFIG_UACCE is not set\n# CONFIG_PVPANIC is not set\n# end of Misc devices\n\n#\n# SCSI device support\n#\nCONFIG_SCSI_MOD=y\n# CONFIG_RAID_ATTRS is not set\nCONFIG_SCSI_COMMON=y\nCONFIG_SCSI=y\nCONFIG_SCSI_DMA=y\nCONFIG_SCSI_PROC_FS=y\n\n#\n# SCSI support type (disk, tape, CD-ROM)\n#\nCONFIG_BLK_DEV_SD=y\n# CONFIG_CHR_DEV_ST is not set\n# CONFIG_BLK_DEV_SR is not set\n# CONFIG_CHR_DEV_SG is not set\nCONFIG_BLK_DEV_BSG=y\n# CONFIG_CHR_DEV_SCH is not set\n# CONFIG_SCSI_CONSTANTS is not set\n# CONFIG_SCSI_LOGGING is not set\n# CONFIG_SCSI_SCAN_ASYNC is not set\n\n#\n# SCSI Transports\n#\n# CONFIG_SCSI_SPI_ATTRS is not set\n# CONFIG_SCSI_FC_ATTRS is not set\n# CONFIG_SCSI_ISCSI_ATTRS is not set\n# CONFIG_SCSI_SAS_ATTRS is not set\n# CONFIG_SCSI_SAS_LIBSAS is not set\n# CONFIG_SCSI_SRP_ATTRS is not set\n# end of SCSI Transports\n\nCONFIG_SCSI_LOWLEVEL=y\n# CONFIG_ISCSI_TCP is not set\n# CONFIG_ISCSI_BOOT_SYSFS is not set\n# CONFIG_SCSI_CXGB3_ISCSI is not set\n# CONFIG_SCSI_CXGB4_ISCSI is not set\n# CONFIG_SCSI_BNX2_ISCSI is not set\n# CONFIG_BE2ISCSI is not set\n# CONFIG_BLK_DEV_3W_XXXX_RAID is not set\n# CONFIG_SCSI_HPSA is not set\n# CONFIG_SCSI_3W_9XXX is not set\n# CONFIG_SCSI_3W_SAS is not set\n# CONFIG_SCSI_ACARD is not set\n# CONFIG_SCSI_AACRAID is not set\n# CONFIG_SCSI_AIC7XXX is not set\n# CONFIG_SCSI_AIC79XX is not set\n# CONFIG_SCSI_AIC94XX is not set\n# CONFIG_SCSI_HISI_SAS is not set\n# CONFIG_SCSI_MVSAS is not set\n# CONFIG_SCSI_MVUMI is not set\n# CONFIG_SCSI_ADVANSYS is not set\n# CONFIG_SCSI_ARCMSR is not set\n# CONFIG_SCSI_ESAS2R is not set\n# CONFIG_MEGARAID_NEWGEN is not set\n# CONFIG_MEGARAID_LEGACY is not set\n# CONFIG_MEGARAID_SAS is not set\n# CONFIG_SCSI_MPT3SAS is not set\n# CONFIG_SCSI_MPT2SAS is not set\n# CONFIG_SCSI_MPI3MR is not set\n# CONFIG_SCSI_SMARTPQI is not set\n# CONFIG_SCSI_UFSHCD is not set\n# CONFIG_SCSI_HPTIOP is not set\n# CONFIG_SCSI_MYRB is not set\n# CONFIG_SCSI_MYRS is not set\n# CONFIG_SCSI_SNIC is not set\n# CONFIG_SCSI_DMX3191D is not set\n# CONFIG_SCSI_FDOMAIN_PCI is not set\n# CONFIG_SCSI_IPS is not set\n# CONFIG_SCSI_INITIO is not set\n# CONFIG_SCSI_INIA100 is not set\n# CONFIG_SCSI_STEX is not set\n# CONFIG_SCSI_SYM53C8XX_2 is not set\n# CONFIG_SCSI_IPR is not set\n# CONFIG_SCSI_QLOGIC_1280 is not set\n# CONFIG_SCSI_QLA_ISCSI is not set\n# CONFIG_SCSI_DC395x is not set\n# CONFIG_SCSI_AM53C974 is not set\n# CONFIG_SCSI_WD719X is not set\n# CONFIG_SCSI_DEBUG is not set\n# CONFIG_SCSI_PMCRAID is not set\n# CONFIG_SCSI_PM8001 is not set\n# CONFIG_SCSI_VIRTIO is not set\n# CONFIG_SCSI_DH is not set\n# end of SCSI device support\n\nCONFIG_HAVE_PATA_PLATFORM=y\nCONFIG_ATA=y\nCONFIG_SATA_HOST=y\nCONFIG_ATA_VERBOSE_ERROR=y\nCONFIG_ATA_FORCE=y\nCONFIG_SATA_PMP=y\n\n#\n# Controllers with non-SFF native interface\n#\n# CONFIG_SATA_AHCI is not set\nCONFIG_SATA_AHCI_PLATFORM=y\nCONFIG_AHCI_CEVA=y\n# CONFIG_AHCI_QORIQ is not set\n# CONFIG_SATA_INIC162X is not set\n# CONFIG_SATA_ACARD_AHCI is not set\n# CONFIG_SATA_SIL24 is not set\n# CONFIG_ATA_SFF is not set\n# CONFIG_MD is not set\n# CONFIG_TARGET_CORE is not set\n# CONFIG_FUSION is not set\n\n#\n# IEEE 1394 (FireWire) support\n#\n# CONFIG_FIREWIRE is not set\n# CONFIG_FIREWIRE_NOSY is not set\n# end of IEEE 1394 (FireWire) support\n\nCONFIG_NETDEVICES=y\nCONFIG_MII=y\nCONFIG_NET_CORE=y\n# CONFIG_BONDING is not set\n# CONFIG_DUMMY is not set\n# CONFIG_WIREGUARD is not set\n# CONFIG_EQUALIZER is not set\n# CONFIG_NET_FC is not set\n# CONFIG_NET_TEAM is not set\n# CONFIG_MACVLAN is not set\n# CONFIG_IPVLAN is not set\n# CONFIG_VXLAN is not set\n# CONFIG_GENEVE is not set\n# CONFIG_BAREUDP is not set\n# CONFIG_GTP is not set\n# CONFIG_MACSEC is not set\n# CONFIG_NETCONSOLE is not set\nCONFIG_TUN=y\n# CONFIG_TUN_VNET_CROSS_LE is not set\n# CONFIG_VETH is not set\n# CONFIG_VIRTIO_NET is not set\n# CONFIG_NLMON is not set\n# CONFIG_ARCNET is not set\n\n#\n# Distributed Switch Architecture drivers\n#\n# CONFIG_B53 is not set\n# CONFIG_NET_DSA_BCM_SF2 is not set\n# CONFIG_NET_DSA_LOOP is not set\n# CONFIG_NET_DSA_LANTIQ_GSWIP is not set\n# CONFIG_NET_DSA_MT7530 is not set\n# CONFIG_NET_DSA_MV88E6060 is not set\n# CONFIG_NET_DSA_MICROCHIP_KSZ9477 is not set\n# CONFIG_NET_DSA_MICROCHIP_KSZ8795 is not set\n# CONFIG_NET_DSA_MV88E6XXX is not set\n# CONFIG_NET_DSA_MSCC_SEVILLE is not set\n# CONFIG_NET_DSA_AR9331 is not set\n# CONFIG_NET_DSA_SJA1105 is not set\n# CONFIG_NET_DSA_XRS700X_I2C is not set\n# CONFIG_NET_DSA_XRS700X_MDIO is not set\n# CONFIG_NET_DSA_QCA8K is not set\n# CONFIG_NET_DSA_REALTEK_SMI is not set\n# CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set\n# CONFIG_NET_DSA_SMSC_LAN9303_MDIO is not set\n# CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set\n# CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set\n# end of Distributed Switch Architecture drivers\n\nCONFIG_ETHERNET=y\nCONFIG_NET_VENDOR_3COM=y\n# CONFIG_VORTEX is not set\n# CONFIG_TYPHOON is not set\nCONFIG_NET_VENDOR_ADAPTEC=y\n# CONFIG_ADAPTEC_STARFIRE is not set\nCONFIG_NET_VENDOR_AGERE=y\n# CONFIG_ET131X is not set\nCONFIG_NET_VENDOR_ALACRITECH=y\n# CONFIG_SLICOSS is not set\nCONFIG_NET_VENDOR_ALTEON=y\n# CONFIG_ACENIC is not set\n# CONFIG_ALTERA_TSE is not set\nCONFIG_NET_VENDOR_AMAZON=y\n# CONFIG_ENA_ETHERNET is not set\nCONFIG_NET_VENDOR_AMD=y\n# CONFIG_AMD8111_ETH is not set\n# CONFIG_PCNET32 is not set\n# CONFIG_AMD_XGBE is not set\nCONFIG_NET_VENDOR_AQUANTIA=y\n# CONFIG_AQTION is not set\nCONFIG_NET_VENDOR_ARC=y\nCONFIG_NET_VENDOR_ATHEROS=y\n# CONFIG_ATL2 is not set\n# CONFIG_ATL1 is not set\n# CONFIG_ATL1E is not set\n# CONFIG_ATL1C is not set\n# CONFIG_ALX is not set\nCONFIG_NET_VENDOR_BROADCOM=y\n# CONFIG_B44 is not set\n# CONFIG_BCMGENET is not set\n# CONFIG_BNX2 is not set\n# CONFIG_CNIC is not set\n# CONFIG_TIGON3 is not set\n# CONFIG_BNX2X is not set\n# CONFIG_SYSTEMPORT is not set\n# CONFIG_BNXT is not set\nCONFIG_NET_VENDOR_CADENCE=y\nCONFIG_MACB=y\nCONFIG_MACB_USE_HWSTAMP=y\n# CONFIG_MACB_PCI is not set\nCONFIG_NET_VENDOR_CAVIUM=y\n# CONFIG_THUNDER_NIC_PF is not set\n# CONFIG_THUNDER_NIC_VF is not set\n# CONFIG_THUNDER_NIC_BGX is not set\n# CONFIG_THUNDER_NIC_RGX is not set\n# CONFIG_CAVIUM_PTP is not set\n# CONFIG_LIQUIDIO is not set\n# CONFIG_LIQUIDIO_VF is not set\nCONFIG_NET_VENDOR_CHELSIO=y\n# CONFIG_CHELSIO_T1 is not set\n# CONFIG_CHELSIO_T3 is not set\n# CONFIG_CHELSIO_T4 is not set\n# CONFIG_CHELSIO_T4VF is not set\nCONFIG_NET_VENDOR_CISCO=y\n# CONFIG_ENIC is not set\nCONFIG_NET_VENDOR_CORTINA=y\n# CONFIG_GEMINI_ETHERNET is not set\n# CONFIG_DNET is not set\nCONFIG_NET_VENDOR_DEC=y\n# CONFIG_NET_TULIP is not set\nCONFIG_NET_VENDOR_DLINK=y\n# CONFIG_DL2K is not set\n# CONFIG_SUNDANCE is not set\nCONFIG_NET_VENDOR_EMULEX=y\n# CONFIG_BE2NET is not set\nCONFIG_NET_VENDOR_EZCHIP=y\n# CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set\nCONFIG_NET_VENDOR_GOOGLE=y\n# CONFIG_GVE is not set\nCONFIG_NET_VENDOR_HISILICON=y\n# CONFIG_HIX5HD2_GMAC is not set\n# CONFIG_HISI_FEMAC is not set\n# CONFIG_HIP04_ETH is not set\n# CONFIG_HNS_DSAF is not set\n# CONFIG_HNS_ENET is not set\n# CONFIG_HNS3 is not set\nCONFIG_NET_VENDOR_HUAWEI=y\n# CONFIG_HINIC is not set\nCONFIG_NET_VENDOR_I825XX=y\nCONFIG_NET_VENDOR_INTEL=y\n# CONFIG_E100 is not set\n# CONFIG_E1000 is not set\n# CONFIG_E1000E is not set\n# CONFIG_IGB is not set\n# CONFIG_IGBVF is not set\n# CONFIG_IXGB is not set\n# CONFIG_IXGBE is not set\n# CONFIG_IXGBEVF is not set\n# CONFIG_I40E is not set\n# CONFIG_I40EVF is not set\n# CONFIG_ICE is not set\n# CONFIG_FM10K is not set\n# CONFIG_IGC is not set\n# CONFIG_JME is not set\nCONFIG_NET_VENDOR_ADI=y\nCONFIG_ADIN1110=y\nCONFIG_NET_VENDOR_LITEX=y\n# CONFIG_LITEX_LITEETH is not set\nCONFIG_NET_VENDOR_MARVELL=y\n# CONFIG_MVMDIO is not set\n# CONFIG_SKGE is not set\n# CONFIG_SKY2 is not set\n# CONFIG_OCTEONTX2_AF is not set\n# CONFIG_OCTEONTX2_PF is not set\nCONFIG_NET_VENDOR_MELLANOX=y\n# CONFIG_MLX4_EN is not set\n# CONFIG_MLX5_CORE is not set\n# CONFIG_MLXSW_CORE is not set\n# CONFIG_MLXFW is not set\nCONFIG_NET_VENDOR_MICREL=y\n# CONFIG_KS8842 is not set\n# CONFIG_KS8851 is not set\n# CONFIG_KS8851_MLL is not set\n# CONFIG_KSZ884X_PCI is not set\nCONFIG_NET_VENDOR_MICROCHIP=y\n# CONFIG_ENC28J60 is not set\n# CONFIG_ENCX24J600 is not set\n# CONFIG_LAN743X is not set\nCONFIG_NET_VENDOR_MICROSEMI=y\n# CONFIG_MSCC_OCELOT_SWITCH is not set\nCONFIG_NET_VENDOR_MICROSOFT=y\nCONFIG_NET_VENDOR_MYRI=y\n# CONFIG_MYRI10GE is not set\n# CONFIG_FEALNX is not set\nCONFIG_NET_VENDOR_NI=y\n# CONFIG_NI_XGE_MANAGEMENT_ENET is not set\nCONFIG_NET_VENDOR_NATSEMI=y\n# CONFIG_NATSEMI is not set\n# CONFIG_NS83820 is not set\nCONFIG_NET_VENDOR_NETERION=y\n# CONFIG_S2IO is not set\n# CONFIG_VXGE is not set\nCONFIG_NET_VENDOR_NETRONOME=y\n# CONFIG_NFP is not set\nCONFIG_NET_VENDOR_8390=y\n# CONFIG_NE2K_PCI is not set\nCONFIG_NET_VENDOR_NVIDIA=y\n# CONFIG_FORCEDETH is not set\nCONFIG_NET_VENDOR_OKI=y\n# CONFIG_ETHOC is not set\nCONFIG_NET_VENDOR_PACKET_ENGINES=y\n# CONFIG_HAMACHI is not set\n# CONFIG_YELLOWFIN is not set\nCONFIG_NET_VENDOR_PENSANDO=y\n# CONFIG_IONIC is not set\nCONFIG_NET_VENDOR_QLOGIC=y\n# CONFIG_QLA3XXX is not set\n# CONFIG_QLCNIC is not set\n# CONFIG_NETXEN_NIC is not set\n# CONFIG_QED is not set\nCONFIG_NET_VENDOR_BROCADE=y\n# CONFIG_BNA is not set\nCONFIG_NET_VENDOR_QUALCOMM=y\n# CONFIG_QCA7000_SPI is not set\n# CONFIG_QCA7000_UART is not set\n# CONFIG_QCOM_EMAC is not set\n# CONFIG_RMNET is not set\nCONFIG_NET_VENDOR_RDC=y\n# CONFIG_R6040 is not set\nCONFIG_NET_VENDOR_REALTEK=y\n# CONFIG_8139CP is not set\n# CONFIG_8139TOO is not set\n# CONFIG_R8169 is not set\nCONFIG_NET_VENDOR_RENESAS=y\nCONFIG_NET_VENDOR_ROCKER=y\n# CONFIG_ROCKER is not set\nCONFIG_NET_VENDOR_SAMSUNG=y\n# CONFIG_SXGBE_ETH is not set\nCONFIG_NET_VENDOR_SEEQ=y\nCONFIG_NET_VENDOR_SILAN=y\n# CONFIG_SC92031 is not set\nCONFIG_NET_VENDOR_SIS=y\n# CONFIG_SIS900 is not set\n# CONFIG_SIS190 is not set\nCONFIG_NET_VENDOR_SOLARFLARE=y\n# CONFIG_SFC is not set\n# CONFIG_SFC_FALCON is not set\nCONFIG_NET_VENDOR_SMSC=y\n# CONFIG_SMC91X is not set\n# CONFIG_EPIC100 is not set\n# CONFIG_SMSC911X is not set\n# CONFIG_SMSC9420 is not set\nCONFIG_NET_VENDOR_SOCIONEXT=y\nCONFIG_NET_VENDOR_STMICRO=y\n# CONFIG_STMMAC_ETH is not set\nCONFIG_NET_VENDOR_SUN=y\n# CONFIG_HAPPYMEAL is not set\n# CONFIG_SUNGEM is not set\n# CONFIG_CASSINI is not set\n# CONFIG_NIU is not set\nCONFIG_NET_VENDOR_SYNOPSYS=y\n# CONFIG_DWC_XLGMAC is not set\nCONFIG_NET_VENDOR_TEHUTI=y\n# CONFIG_TEHUTI is not set\nCONFIG_NET_VENDOR_TI=y\n# CONFIG_TI_CPSW_PHY_SEL is not set\n# CONFIG_TLAN is not set\nCONFIG_NET_VENDOR_VIA=y\n# CONFIG_VIA_RHINE is not set\n# CONFIG_VIA_VELOCITY is not set\nCONFIG_NET_VENDOR_WIZNET=y\n# CONFIG_WIZNET_W5100 is not set\n# CONFIG_WIZNET_W5300 is not set\nCONFIG_NET_VENDOR_XILINX=y\nCONFIG_XILINX_EMACLITE=y\nCONFIG_XILINX_AXI_EMAC=y\n# CONFIG_XILINX_AXI_EMAC_HWTSTAMP is not set\n# CONFIG_AXIENET_HAS_MCDMA is not set\n# CONFIG_XILINX_LL_TEMAC is not set\n# CONFIG_FDDI is not set\n# CONFIG_HIPPI is not set\nCONFIG_PHYLINK=y\nCONFIG_PHYLIB=y\nCONFIG_SWPHY=y\n# CONFIG_LED_TRIGGER_PHY is not set\nCONFIG_FIXED_PHY=y\n# CONFIG_SFP is not set\n\n#\n# MII PHY device drivers\n#\nCONFIG_AMD_PHY=y\nCONFIG_ADIN_PHY=y\nCONFIG_ADIN1100_PHY=y\n# CONFIG_AQUANTIA_PHY is not set\nCONFIG_AX88796B_PHY=y\nCONFIG_BROADCOM_PHY=y\n# CONFIG_BCM54140_PHY is not set\nCONFIG_BCM7XXX_PHY=y\n# CONFIG_BCM84881_PHY is not set\nCONFIG_BCM87XX_PHY=y\nCONFIG_BCM_NET_PHYLIB=y\nCONFIG_CICADA_PHY=y\n# CONFIG_CORTINA_PHY is not set\nCONFIG_DAVICOM_PHY=y\nCONFIG_ICPLUS_PHY=y\nCONFIG_LXT_PHY=y\n# CONFIG_INTEL_XWAY_PHY is not set\nCONFIG_LSI_ET1011C_PHY=y\nCONFIG_MARVELL_PHY=y\n# CONFIG_MARVELL_10G_PHY is not set\n# CONFIG_MARVELL_88X2222_PHY is not set\n# CONFIG_MAXLINEAR_GPHY is not set\n# CONFIG_MEDIATEK_GE_PHY is not set\nCONFIG_MICREL_PHY=y\n# CONFIG_MICROCHIP_PHY is not set\n# CONFIG_MICROCHIP_T1_PHY is not set\n# CONFIG_MICROSEMI_PHY is not set\n# CONFIG_MOTORCOMM_PHY is not set\nCONFIG_NATIONAL_PHY=y\n# CONFIG_NXP_C45_TJA11XX_PHY is not set\n# CONFIG_NXP_TJA11XX_PHY is not set\nCONFIG_AT803X_PHY=y\nCONFIG_QSEMI_PHY=y\nCONFIG_REALTEK_PHY=y\n# CONFIG_RENESAS_PHY is not set\n# CONFIG_ROCKCHIP_PHY is not set\nCONFIG_SMSC_PHY=y\nCONFIG_STE10XP=y\n# CONFIG_TERANETICS_PHY is not set\n# CONFIG_DP83822_PHY is not set\n# CONFIG_DP83TC811_PHY is not set\n# CONFIG_DP83848_PHY is not set\nCONFIG_DP83867_PHY=y\n# CONFIG_DP83869_PHY is not set\nCONFIG_VITESSE_PHY=y\n# CONFIG_XILINX_PHY is not set\nCONFIG_XILINX_GMII2RGMII=y\n# CONFIG_MICREL_KS8995MA is not set\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_BUS=y\nCONFIG_FWNODE_MDIO=y\nCONFIG_OF_MDIO=y\nCONFIG_MDIO_DEVRES=y\n# CONFIG_MDIO_BITBANG is not set\n# CONFIG_MDIO_BCM_UNIMAC is not set\n# CONFIG_MDIO_HISI_FEMAC is not set\n# CONFIG_MDIO_MVUSB is not set\n# CONFIG_MDIO_MSCC_MIIM is not set\n# CONFIG_MDIO_OCTEON is not set\n# CONFIG_MDIO_IPQ4019 is not set\n# CONFIG_MDIO_IPQ8064 is not set\n# CONFIG_MDIO_THUNDER is not set\n\n#\n# MDIO Multiplexers\n#\n# CONFIG_MDIO_BUS_MUX_GPIO is not set\n# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set\n# CONFIG_MDIO_BUS_MUX_MMIOREG is not set\n\n#\n# PCS device drivers\n#\n# CONFIG_PCS_XPCS is not set\n# end of PCS device drivers\n\n# CONFIG_PPP is not set\n# CONFIG_SLIP is not set\nCONFIG_USB_NET_DRIVERS=y\n# CONFIG_USB_CATC is not set\n# CONFIG_USB_KAWETH is not set\n# CONFIG_USB_PEGASUS is not set\n# CONFIG_USB_RTL8150 is not set\n# CONFIG_USB_RTL8152 is not set\n# CONFIG_USB_LAN78XX is not set\nCONFIG_USB_USBNET=y\nCONFIG_USB_NET_AX8817X=y\nCONFIG_USB_NET_AX88179_178A=y\nCONFIG_USB_NET_CDCETHER=y\n# CONFIG_USB_NET_CDC_EEM is not set\nCONFIG_USB_NET_CDC_NCM=y\n# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set\n# CONFIG_USB_NET_CDC_MBIM is not set\n# CONFIG_USB_NET_DM9601 is not set\n# CONFIG_USB_NET_SR9700 is not set\n# CONFIG_USB_NET_SR9800 is not set\n# CONFIG_USB_NET_SMSC75XX is not set\n# CONFIG_USB_NET_SMSC95XX is not set\n# CONFIG_USB_NET_GL620A is not set\nCONFIG_USB_NET_NET1080=y\n# CONFIG_USB_NET_PLUSB is not set\n# CONFIG_USB_NET_MCS7830 is not set\n# CONFIG_USB_NET_RNDIS_HOST is not set\nCONFIG_USB_NET_CDC_SUBSET_ENABLE=y\nCONFIG_USB_NET_CDC_SUBSET=y\n# CONFIG_USB_ALI_M5632 is not set\n# CONFIG_USB_AN2720 is not set\nCONFIG_USB_BELKIN=y\nCONFIG_USB_ARMLINUX=y\n# CONFIG_USB_EPSON2888 is not set\n# CONFIG_USB_KC2190 is not set\nCONFIG_USB_NET_ZAURUS=y\n# CONFIG_USB_NET_CX82310_ETH is not set\n# CONFIG_USB_NET_KALMIA is not set\n# CONFIG_USB_NET_QMI_WWAN is not set\n# CONFIG_USB_HSO is not set\n# CONFIG_USB_NET_INT51X1 is not set\n# CONFIG_USB_IPHETH is not set\n# CONFIG_USB_SIERRA_NET is not set\n# CONFIG_USB_VL600 is not set\n# CONFIG_USB_NET_CH9200 is not set\n# CONFIG_USB_NET_AQC111 is not set\n# CONFIG_USB_RTL8153_ECM is not set\nCONFIG_WLAN=y\nCONFIG_WLAN_VENDOR_ADMTEK=y\n# CONFIG_ADM8211 is not set\nCONFIG_WLAN_VENDOR_ATH=y\n# CONFIG_ATH_DEBUG is not set\n# CONFIG_ATH_REG_DYNAMIC_USER_REG_HINTS is not set\n# CONFIG_ATH5K is not set\n# CONFIG_ATH5K_PCI is not set\n# CONFIG_ATH9K is not set\n# CONFIG_ATH9K_HTC is not set\n# CONFIG_CARL9170 is not set\n# CONFIG_ATH6KL is not set\n# CONFIG_AR5523 is not set\n# CONFIG_WIL6210 is not set\n# CONFIG_ATH10K is not set\n# CONFIG_WCN36XX is not set\nCONFIG_WLAN_VENDOR_ATMEL=y\n# CONFIG_ATMEL is not set\n# CONFIG_AT76C50X_USB is not set\nCONFIG_WLAN_VENDOR_BROADCOM=y\n# CONFIG_B43 is not set\n# CONFIG_B43LEGACY is not set\n# CONFIG_BRCMSMAC is not set\n# CONFIG_BRCMFMAC is not set\nCONFIG_WLAN_VENDOR_CISCO=y\nCONFIG_WLAN_VENDOR_INTEL=y\n# CONFIG_IPW2100 is not set\n# CONFIG_IPW2200 is not set\n# CONFIG_IWL4965 is not set\n# CONFIG_IWL3945 is not set\n# CONFIG_IWLWIFI is not set\nCONFIG_WLAN_VENDOR_INTERSIL=y\n# CONFIG_HOSTAP is not set\n# CONFIG_HERMES is not set\n# CONFIG_P54_COMMON is not set\nCONFIG_WLAN_VENDOR_MARVELL=y\n# CONFIG_LIBERTAS is not set\n# CONFIG_LIBERTAS_THINFIRM is not set\n# CONFIG_MWIFIEX is not set\n# CONFIG_MWL8K is not set\nCONFIG_WLAN_VENDOR_MEDIATEK=y\n# CONFIG_MT7601U is not set\n# CONFIG_MT76x0U is not set\n# CONFIG_MT76x0E is not set\n# CONFIG_MT76x2E is not set\n# CONFIG_MT76x2U is not set\n# CONFIG_MT7603E is not set\n# CONFIG_MT7615E is not set\n# CONFIG_MT7663U is not set\n# CONFIG_MT7663S is not set\n# CONFIG_MT7915E is not set\n# CONFIG_MT7921E is not set\nCONFIG_WLAN_VENDOR_MICROCHIP=y\n# CONFIG_WILC1000_SDIO is not set\n# CONFIG_WILC1000_SPI is not set\nCONFIG_WLAN_VENDOR_RALINK=y\n# CONFIG_RT2X00 is not set\nCONFIG_WLAN_VENDOR_REALTEK=y\n# CONFIG_RTL8180 is not set\n# CONFIG_RTL8187 is not set\nCONFIG_RTL_CARDS=y\n# CONFIG_RTL8192CE is not set\n# CONFIG_RTL8192SE is not set\n# CONFIG_RTL8192DE is not set\n# CONFIG_RTL8723AE is not set\n# CONFIG_RTL8723BE is not set\n# CONFIG_RTL8188EE is not set\n# CONFIG_RTL8192EE is not set\n# CONFIG_RTL8821AE is not set\n# CONFIG_RTL8192CU is not set\n# CONFIG_RTL8XXXU is not set\n# CONFIG_RTW88 is not set\nCONFIG_WLAN_VENDOR_RSI=y\n# CONFIG_RSI_91X is not set\nCONFIG_WLAN_VENDOR_ST=y\n# CONFIG_CW1200 is not set\nCONFIG_WLAN_VENDOR_TI=y\n# CONFIG_WL1251 is not set\n# CONFIG_WL12XX is not set\nCONFIG_WL18XX=y\nCONFIG_WLCORE=y\nCONFIG_WLCORE_SPI=y\nCONFIG_WLCORE_SDIO=y\nCONFIG_WILINK_PLATFORM_DATA=y\nCONFIG_WLAN_VENDOR_ZYDAS=y\n# CONFIG_USB_ZD1201 is not set\n# CONFIG_ZD1211RW is not set\nCONFIG_WLAN_VENDOR_QUANTENNA=y\n# CONFIG_QTNFMAC_PCIE is not set\n# CONFIG_MAC80211_HWSIM is not set\n# CONFIG_USB_NET_RNDIS_WLAN is not set\n# CONFIG_VIRT_WIFI is not set\n# CONFIG_WAN is not set\nCONFIG_IEEE802154_DRIVERS=y\n# CONFIG_IEEE802154_FAKELB is not set\n# CONFIG_IEEE802154_AT86RF230 is not set\n# CONFIG_IEEE802154_MRF24J40 is not set\n# CONFIG_IEEE802154_CC2520 is not set\n# CONFIG_IEEE802154_ATUSB is not set\nCONFIG_IEEE802154_ADF7242=y\n# CONFIG_IEEE802154_CA8210 is not set\n# CONFIG_IEEE802154_MCR20A is not set\n# CONFIG_IEEE802154_HWSIM is not set\n\n#\n# Wireless WAN\n#\n# CONFIG_WWAN is not set\n# end of Wireless WAN\n\n# CONFIG_VMXNET3 is not set\n# CONFIG_NETDEVSIM is not set\n# CONFIG_NET_FAILOVER is not set\n# CONFIG_ISDN is not set\n\n#\n# Input device support\n#\nCONFIG_INPUT=y\nCONFIG_INPUT_LEDS=y\n# CONFIG_INPUT_FF_MEMLESS is not set\n# CONFIG_INPUT_SPARSEKMAP is not set\n# CONFIG_INPUT_MATRIXKMAP is not set\n\n#\n# Userland interfaces\n#\n# CONFIG_INPUT_MOUSEDEV is not set\n# CONFIG_INPUT_JOYDEV is not set\nCONFIG_INPUT_EVDEV=y\n# CONFIG_INPUT_EVBUG is not set\n\n#\n# Input Device Drivers\n#\nCONFIG_INPUT_KEYBOARD=y\n# CONFIG_KEYBOARD_ADC is not set\nCONFIG_KEYBOARD_ADP5520=y\nCONFIG_KEYBOARD_ADP5588=y\nCONFIG_KEYBOARD_ADP5589=y\nCONFIG_KEYBOARD_ATKBD=y\n# CONFIG_KEYBOARD_QT1050 is not set\n# CONFIG_KEYBOARD_QT1070 is not set\n# CONFIG_KEYBOARD_QT2160 is not set\n# CONFIG_KEYBOARD_DLINK_DIR685 is not set\n# CONFIG_KEYBOARD_LKKBD is not set\nCONFIG_KEYBOARD_GPIO=y\nCONFIG_KEYBOARD_GPIO_POLLED=y\n# CONFIG_KEYBOARD_TCA6416 is not set\n# CONFIG_KEYBOARD_TCA8418 is not set\n# CONFIG_KEYBOARD_MATRIX is not set\n# CONFIG_KEYBOARD_LM8323 is not set\n# CONFIG_KEYBOARD_LM8333 is not set\n# CONFIG_KEYBOARD_MAX7359 is not set\n# CONFIG_KEYBOARD_MCS is not set\n# CONFIG_KEYBOARD_MPR121 is not set\n# CONFIG_KEYBOARD_NEWTON is not set\n# CONFIG_KEYBOARD_OPENCORES is not set\n# CONFIG_KEYBOARD_SAMSUNG is not set\n# CONFIG_KEYBOARD_STOWAWAY is not set\n# CONFIG_KEYBOARD_SUNKBD is not set\n# CONFIG_KEYBOARD_OMAP4 is not set\n# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set\n# CONFIG_KEYBOARD_XTKBD is not set\n# CONFIG_KEYBOARD_CAP11XX is not set\n# CONFIG_KEYBOARD_BCM is not set\nCONFIG_INPUT_MOUSE=y\nCONFIG_MOUSE_PS2=y\nCONFIG_MOUSE_PS2_ALPS=y\nCONFIG_MOUSE_PS2_BYD=y\nCONFIG_MOUSE_PS2_LOGIPS2PP=y\nCONFIG_MOUSE_PS2_SYNAPTICS=y\nCONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y\nCONFIG_MOUSE_PS2_CYPRESS=y\nCONFIG_MOUSE_PS2_TRACKPOINT=y\n# CONFIG_MOUSE_PS2_ELANTECH is not set\n# CONFIG_MOUSE_PS2_SENTELIC is not set\n# CONFIG_MOUSE_PS2_TOUCHKIT is not set\nCONFIG_MOUSE_PS2_FOCALTECH=y\nCONFIG_MOUSE_PS2_SMBUS=y\n# CONFIG_MOUSE_SERIAL is not set\n# CONFIG_MOUSE_APPLETOUCH is not set\n# CONFIG_MOUSE_BCM5974 is not set\n# CONFIG_MOUSE_CYAPA is not set\n# CONFIG_MOUSE_ELAN_I2C is not set\n# CONFIG_MOUSE_VSXXXAA is not set\n# CONFIG_MOUSE_GPIO is not set\n# CONFIG_MOUSE_SYNAPTICS_I2C is not set\n# CONFIG_MOUSE_SYNAPTICS_USB is not set\n# CONFIG_INPUT_JOYSTICK is not set\n# CONFIG_INPUT_TABLET is not set\nCONFIG_INPUT_TOUCHSCREEN=y\nCONFIG_TOUCHSCREEN_ADS7846=y\nCONFIG_TOUCHSCREEN_AD7877=y\nCONFIG_TOUCHSCREEN_AD7879=y\nCONFIG_TOUCHSCREEN_AD7879_I2C=y\nCONFIG_TOUCHSCREEN_AD7879_SPI=y\n# CONFIG_TOUCHSCREEN_ADC is not set\n# CONFIG_TOUCHSCREEN_AR1021_I2C is not set\n# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set\n# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set\n# CONFIG_TOUCHSCREEN_BU21013 is not set\n# CONFIG_TOUCHSCREEN_BU21029 is not set\n# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set\n# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set\n# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set\n# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set\n# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set\n# CONFIG_TOUCHSCREEN_DYNAPRO is not set\n# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set\n# CONFIG_TOUCHSCREEN_EETI is not set\n# CONFIG_TOUCHSCREEN_EGALAX is not set\n# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set\n# CONFIG_TOUCHSCREEN_EXC3000 is not set\n# CONFIG_TOUCHSCREEN_FUJITSU is not set\n# CONFIG_TOUCHSCREEN_GOODIX is not set\n# CONFIG_TOUCHSCREEN_HIDEEP is not set\n# CONFIG_TOUCHSCREEN_HYCON_HY46XX is not set\n# CONFIG_TOUCHSCREEN_ILI210X is not set\n# CONFIG_TOUCHSCREEN_ILITEK is not set\n# CONFIG_TOUCHSCREEN_S6SY761 is not set\n# CONFIG_TOUCHSCREEN_GUNZE is not set\n# CONFIG_TOUCHSCREEN_EKTF2127 is not set\n# CONFIG_TOUCHSCREEN_ELAN is not set\n# CONFIG_TOUCHSCREEN_ELO is not set\n# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set\n# CONFIG_TOUCHSCREEN_WACOM_I2C is not set\n# CONFIG_TOUCHSCREEN_MAX11801 is not set\n# CONFIG_TOUCHSCREEN_MCS5000 is not set\n# CONFIG_TOUCHSCREEN_MMS114 is not set\n# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set\n# CONFIG_TOUCHSCREEN_MSG2638 is not set\n# CONFIG_TOUCHSCREEN_MTOUCH is not set\n# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set\n# CONFIG_TOUCHSCREEN_INEXIO is not set\n# CONFIG_TOUCHSCREEN_MK712 is not set\n# CONFIG_TOUCHSCREEN_PENMOUNT is not set\n# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set\n# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set\n# CONFIG_TOUCHSCREEN_TOUCHWIN is not set\n# CONFIG_TOUCHSCREEN_PIXCIR is not set\n# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set\n# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set\n# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set\n# CONFIG_TOUCHSCREEN_TSC_SERIO is not set\n# CONFIG_TOUCHSCREEN_TSC2004 is not set\n# CONFIG_TOUCHSCREEN_TSC2005 is not set\n# CONFIG_TOUCHSCREEN_TSC2007 is not set\n# CONFIG_TOUCHSCREEN_RM_TS is not set\n# CONFIG_TOUCHSCREEN_SILEAD is not set\n# CONFIG_TOUCHSCREEN_SIS_I2C is not set\n# CONFIG_TOUCHSCREEN_ST1232 is not set\n# CONFIG_TOUCHSCREEN_STMFTS is not set\n# CONFIG_TOUCHSCREEN_SUR40 is not set\n# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set\n# CONFIG_TOUCHSCREEN_SX8654 is not set\n# CONFIG_TOUCHSCREEN_TPS6507X is not set\n# CONFIG_TOUCHSCREEN_ZET6223 is not set\n# CONFIG_TOUCHSCREEN_ZFORCE is not set\n# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set\n# CONFIG_TOUCHSCREEN_IQS5XX is not set\n# CONFIG_TOUCHSCREEN_ZINITIX is not set\nCONFIG_INPUT_MISC=y\nCONFIG_INPUT_AD714X=y\nCONFIG_INPUT_AD714X_I2C=y\nCONFIG_INPUT_AD714X_SPI=y\n# CONFIG_INPUT_ATMEL_CAPTOUCH is not set\n# CONFIG_INPUT_BMA150 is not set\n# CONFIG_INPUT_E3X0_BUTTON is not set\n# CONFIG_INPUT_MMA8450 is not set\n# CONFIG_INPUT_GPIO_BEEPER is not set\n# CONFIG_INPUT_GPIO_DECODER is not set\n# CONFIG_INPUT_GPIO_VIBRA is not set\n# CONFIG_INPUT_ATI_REMOTE2 is not set\n# CONFIG_INPUT_KEYSPAN_REMOTE is not set\n# CONFIG_INPUT_KXTJ9 is not set\n# CONFIG_INPUT_POWERMATE is not set\n# CONFIG_INPUT_YEALINK is not set\n# CONFIG_INPUT_CM109 is not set\n# CONFIG_INPUT_REGULATOR_HAPTIC is not set\n# CONFIG_INPUT_UINPUT is not set\nCONFIG_INPUT_PCF8574=y\n# CONFIG_INPUT_PWM_BEEPER is not set\n# CONFIG_INPUT_PWM_VIBRA is not set\n# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set\n# CONFIG_INPUT_DA7280_HAPTICS is not set\n# CONFIG_INPUT_ADXL34X is not set\n# CONFIG_INPUT_IMS_PCU is not set\n# CONFIG_INPUT_IQS269A is not set\n# CONFIG_INPUT_IQS626A is not set\n# CONFIG_INPUT_CMA3000 is not set\n# CONFIG_INPUT_DRV260X_HAPTICS is not set\n# CONFIG_INPUT_DRV2665_HAPTICS is not set\n# CONFIG_INPUT_DRV2667_HAPTICS is not set\n# CONFIG_RMI4_CORE is not set\n\n#\n# Hardware I/O ports\n#\nCONFIG_SERIO=y\nCONFIG_SERIO_SERPORT=y\n# CONFIG_SERIO_AMBAKMI is not set\n# CONFIG_SERIO_PCIPS2 is not set\nCONFIG_SERIO_LIBPS2=y\n# CONFIG_SERIO_RAW is not set\n# CONFIG_SERIO_ALTERA_PS2 is not set\n# CONFIG_SERIO_PS2MULT is not set\n# CONFIG_SERIO_ARC_PS2 is not set\n# CONFIG_SERIO_APBPS2 is not set\n# CONFIG_SERIO_GPIO_PS2 is not set\n# CONFIG_USERIO is not set\n# CONFIG_GAMEPORT is not set\n# end of Hardware I/O ports\n# end of Input device support\n\n#\n# Character devices\n#\nCONFIG_TTY=y\nCONFIG_VT=y\nCONFIG_CONSOLE_TRANSLATIONS=y\nCONFIG_VT_CONSOLE=y\nCONFIG_VT_CONSOLE_SLEEP=y\nCONFIG_HW_CONSOLE=y\nCONFIG_VT_HW_CONSOLE_BINDING=y\nCONFIG_UNIX98_PTYS=y\nCONFIG_LEGACY_PTYS=y\nCONFIG_LEGACY_PTY_COUNT=256\nCONFIG_LDISC_AUTOLOAD=y\n\n#\n# Serial drivers\n#\nCONFIG_SERIAL_EARLYCON=y\nCONFIG_SERIAL_8250=y\nCONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y\nCONFIG_SERIAL_8250_16550A_VARIANTS=y\n# CONFIG_SERIAL_8250_FINTEK is not set\nCONFIG_SERIAL_8250_CONSOLE=y\nCONFIG_SERIAL_8250_DMA=y\nCONFIG_SERIAL_8250_PCI=y\nCONFIG_SERIAL_8250_EXAR=y\nCONFIG_SERIAL_8250_NR_UARTS=4\nCONFIG_SERIAL_8250_RUNTIME_UARTS=4\n# CONFIG_SERIAL_8250_EXTENDED is not set\n# CONFIG_SERIAL_8250_ASPEED_VUART is not set\nCONFIG_SERIAL_8250_FSL=y\n# CONFIG_SERIAL_8250_DW is not set\n# CONFIG_SERIAL_8250_RT288X is not set\nCONFIG_SERIAL_OF_PLATFORM=y\n\n#\n# Non-8250 serial port support\n#\n# CONFIG_SERIAL_AMBA_PL010 is not set\n# CONFIG_SERIAL_AMBA_PL011 is not set\n# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set\n# CONFIG_SERIAL_MAX3100 is not set\nCONFIG_SERIAL_MAX310X=y\nCONFIG_SERIAL_UARTLITE=y\nCONFIG_SERIAL_UARTLITE_CONSOLE=y\nCONFIG_SERIAL_UARTLITE_NR_UARTS=16\nCONFIG_SERIAL_CORE=y\nCONFIG_SERIAL_CORE_CONSOLE=y\n# CONFIG_SERIAL_JSM is not set\n# CONFIG_SERIAL_SIFIVE is not set\n# CONFIG_SERIAL_SCCNXP is not set\n# CONFIG_SERIAL_SC16IS7XX is not set\n# CONFIG_SERIAL_BCM63XX is not set\n# CONFIG_SERIAL_ALTERA_JTAGUART is not set\n# CONFIG_SERIAL_ALTERA_UART is not set\nCONFIG_SERIAL_XILINX_PS_UART=y\nCONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y\n# CONFIG_SERIAL_ARC is not set\n# CONFIG_SERIAL_RP2 is not set\n# CONFIG_SERIAL_FSL_LPUART is not set\n# CONFIG_SERIAL_FSL_LINFLEXUART is not set\n# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set\n# CONFIG_SERIAL_SPRD is not set\n# end of Serial drivers\n\nCONFIG_SERIAL_MCTRL_GPIO=y\n# CONFIG_SERIAL_NONSTANDARD is not set\n# CONFIG_N_GSM is not set\n# CONFIG_NOZOMI is not set\n# CONFIG_NULL_TTY is not set\n# CONFIG_HVC_DCC is not set\nCONFIG_SERIAL_DEV_BUS=y\nCONFIG_SERIAL_DEV_CTRL_TTYPORT=y\n# CONFIG_TTY_PRINTK is not set\n# CONFIG_VIRTIO_CONSOLE is not set\n# CONFIG_IPMI_HANDLER is not set\n# CONFIG_HW_RANDOM is not set\n# CONFIG_APPLICOM is not set\nCONFIG_DEVMEM=y\nCONFIG_DEVPORT=y\n# CONFIG_TCG_TPM is not set\n# CONFIG_XILLYBUS is not set\n# CONFIG_XILLYUSB is not set\nCONFIG_AXI_INTR_MONITOR=y\n# CONFIG_RANDOM_TRUST_CPU is not set\n# CONFIG_RANDOM_TRUST_BOOTLOADER is not set\n# end of Character devices\n\n#\n# I2C support\n#\nCONFIG_I2C=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_COMPAT=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_I2C_MUX=y\n\n#\n# Multiplexer I2C Chip support\n#\n# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set\n# CONFIG_I2C_MUX_GPIO is not set\nCONFIG_I2C_MUX_GPMUX=y\nCONFIG_I2C_MUX_LTC4306=y\nCONFIG_I2C_MUX_PCA9541=y\nCONFIG_I2C_MUX_PCA954x=y\n# CONFIG_I2C_MUX_PINCTRL is not set\n# CONFIG_I2C_MUX_REG is not set\n# CONFIG_I2C_DEMUX_PINCTRL is not set\n# CONFIG_I2C_MUX_MLXCPLD is not set\n# end of Multiplexer I2C Chip support\n\nCONFIG_I2C_HELPER_AUTO=y\nCONFIG_I2C_ALGOBIT=y\n\n#\n# I2C Hardware Bus support\n#\n\n#\n# PC SMBus host controller drivers\n#\n# CONFIG_I2C_ALI1535 is not set\n# CONFIG_I2C_ALI1563 is not set\n# CONFIG_I2C_ALI15X3 is not set\n# CONFIG_I2C_AMD756 is not set\n# CONFIG_I2C_AMD8111 is not set\n# CONFIG_I2C_I801 is not set\n# CONFIG_I2C_ISCH is not set\n# CONFIG_I2C_PIIX4 is not set\n# CONFIG_I2C_NFORCE2 is not set\n# CONFIG_I2C_NVIDIA_GPU is not set\n# CONFIG_I2C_SIS5595 is not set\n# CONFIG_I2C_SIS630 is not set\n# CONFIG_I2C_SIS96X is not set\n# CONFIG_I2C_VIA is not set\n# CONFIG_I2C_VIAPRO is not set\n\n#\n# I2C system bus drivers (mostly embedded / system-on-chip)\n#\nCONFIG_I2C_CADENCE=y\n# CONFIG_I2C_CBUS_GPIO is not set\n# CONFIG_I2C_DESIGNWARE_PLATFORM is not set\n# CONFIG_I2C_DESIGNWARE_PCI is not set\n# CONFIG_I2C_EMEV2 is not set\n# CONFIG_I2C_GPIO is not set\n# CONFIG_I2C_NOMADIK is not set\n# CONFIG_I2C_OCORES is not set\n# CONFIG_I2C_PCA_PLATFORM is not set\n# CONFIG_I2C_RK3X is not set\n# CONFIG_I2C_SIMTEC is not set\n# CONFIG_I2C_THUNDERX is not set\nCONFIG_I2C_XILINX=y\n\n#\n# External I2C/SMBus adapter drivers\n#\n# CONFIG_I2C_DIOLAN_U2C is not set\n# CONFIG_I2C_CP2615 is not set\n# CONFIG_I2C_ROBOTFUZZ_OSIF is not set\n# CONFIG_I2C_TAOS_EVM is not set\n# CONFIG_I2C_TINY_USB is not set\n\n#\n# Other I2C/SMBus bus drivers\n#\n# CONFIG_I2C_VIRTIO is not set\n# end of I2C Hardware Bus support\n\n# CONFIG_I2C_STUB is not set\n# CONFIG_I2C_SLAVE is not set\n# CONFIG_I2C_DEBUG_CORE is not set\n# CONFIG_I2C_DEBUG_ALGO is not set\n# CONFIG_I2C_DEBUG_BUS is not set\n# end of I2C support\n\n# CONFIG_I3C is not set\nCONFIG_SPI=y\n# CONFIG_SPI_DEBUG is not set\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\n\n#\n# SPI Master Controller Drivers\n#\n# CONFIG_SPI_ALTERA is not set\nCONFIG_SPI_AXI_SPI_ENGINE=y\nCONFIG_SPI_BITBANG=y\nCONFIG_SPI_CADENCE=y\n# CONFIG_SPI_CADENCE_QUADSPI is not set\n# CONFIG_SPI_DESIGNWARE is not set\n# CONFIG_SPI_NXP_FLEXSPI is not set\n# CONFIG_SPI_GPIO is not set\n# CONFIG_SPI_FSL_SPI is not set\n# CONFIG_SPI_OC_TINY is not set\n# CONFIG_SPI_PL022 is not set\n# CONFIG_SPI_PXA2XX is not set\n# CONFIG_SPI_ROCKCHIP is not set\n# CONFIG_SPI_SC18IS602 is not set\n# CONFIG_SPI_SIFIVE is not set\n# CONFIG_SPI_MXIC is not set\n# CONFIG_SPI_THUNDERX is not set\n# CONFIG_SPI_XCOMM is not set\nCONFIG_SPI_AD9250FMC=y\nCONFIG_SPI_XILINX=y\nCONFIG_SPI_ZYNQMP_GQSPI=y\n# CONFIG_SPI_AMD is not set\n\n#\n# SPI Multiplexer support\n#\n# CONFIG_SPI_MUX is not set\n\n#\n# SPI Protocol Masters\n#\n# CONFIG_SPI_SPIDEV is not set\n# CONFIG_SPI_LOOPBACK_TEST is not set\n# CONFIG_SPI_TLE62X0 is not set\n# CONFIG_SPI_SLAVE is not set\nCONFIG_SPI_DYNAMIC=y\n# CONFIG_SPMI is not set\n# CONFIG_HSI is not set\nCONFIG_PPS=y\n# CONFIG_PPS_DEBUG is not set\n\n#\n# PPS clients support\n#\n# CONFIG_PPS_CLIENT_KTIMER is not set\n# CONFIG_PPS_CLIENT_LDISC is not set\n# CONFIG_PPS_CLIENT_GPIO is not set\n\n#\n# PPS generators support\n#\n\n#\n# PTP clock support\n#\nCONFIG_PTP_1588_CLOCK=y\nCONFIG_PTP_1588_CLOCK_OPTIONAL=y\n# CONFIG_DP83640_PHY is not set\n# CONFIG_PTP_1588_CLOCK_INES is not set\nCONFIG_PTP_1588_CLOCK_KVM=y\n# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set\n# CONFIG_PTP_1588_CLOCK_IDTCM is not set\nCONFIG_PTP_1588_CLOCK_XILINX=y\n# CONFIG_PTP_1588_CLOCK_OCP is not set\n# end of PTP clock support\n\nCONFIG_PINCTRL=y\nCONFIG_PINMUX=y\nCONFIG_PINCONF=y\nCONFIG_GENERIC_PINCONF=y\n# CONFIG_DEBUG_PINCTRL is not set\n# CONFIG_PINCTRL_MCP23S08 is not set\n# CONFIG_PINCTRL_SINGLE is not set\n# CONFIG_PINCTRL_SX150X is not set\n# CONFIG_PINCTRL_STMFX is not set\nCONFIG_PINCTRL_ZYNQMP=y\n# CONFIG_PINCTRL_OCELOT is not set\n# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set\n\n#\n# Renesas pinctrl drivers\n#\n# end of Renesas pinctrl drivers\n\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_FASTPATH_LIMIT=512\nCONFIG_OF_GPIO=y\nCONFIG_GPIOLIB_IRQCHIP=y\n# CONFIG_DEBUG_GPIO is not set\nCONFIG_GPIO_SYSFS=y\nCONFIG_GPIO_CDEV=y\nCONFIG_GPIO_CDEV_V1=y\n\n#\n# Memory mapped GPIO drivers\n#\n# CONFIG_GPIO_74XX_MMIO is not set\n# CONFIG_GPIO_ALTERA is not set\n# CONFIG_GPIO_CADENCE is not set\n# CONFIG_GPIO_DWAPB is not set\n# CONFIG_GPIO_EXAR is not set\n# CONFIG_GPIO_FTGPIO010 is not set\n# CONFIG_GPIO_GENERIC_PLATFORM is not set\n# CONFIG_GPIO_GRGPIO is not set\n# CONFIG_GPIO_HLWD is not set\n# CONFIG_GPIO_LOGICVC is not set\n# CONFIG_GPIO_MB86S7X is not set\n# CONFIG_GPIO_PL061 is not set\n# CONFIG_GPIO_SAMA5D2_PIOBU is not set\n# CONFIG_GPIO_SIFIVE is not set\n# CONFIG_GPIO_SYSCON is not set\n# CONFIG_GPIO_XGENE is not set\nCONFIG_GPIO_XILINX=y\nCONFIG_GPIO_ZYNQ=y\nCONFIG_GPIO_ZYNQMP_MODEPIN=y\n# CONFIG_GPIO_AMD_FCH is not set\n# end of Memory mapped GPIO drivers\n\n#\n# I2C GPIO expanders\n#\nCONFIG_GPIO_ADP5588=y\nCONFIG_GPIO_ADP5588_IRQ=y\n# CONFIG_GPIO_ADNP is not set\n# CONFIG_GPIO_GW_PLD is not set\n# CONFIG_GPIO_MAX7300 is not set\n# CONFIG_GPIO_MAX732X is not set\nCONFIG_GPIO_PCA953X=y\n# CONFIG_GPIO_PCA953X_IRQ is not set\n# CONFIG_GPIO_PCA9570 is not set\n# CONFIG_GPIO_PCF857X is not set\n# CONFIG_GPIO_SLG7XL45106 is not set\n# CONFIG_GPIO_TPIC2810 is not set\n# end of I2C GPIO expanders\n\n#\n# MFD GPIO expanders\n#\nCONFIG_GPIO_ADP5520=y\nCONFIG_GPIO_TPS65086=y\n# end of MFD GPIO expanders\n\n#\n# PCI GPIO expanders\n#\n# CONFIG_GPIO_BT8XX is not set\n# CONFIG_GPIO_PCI_IDIO_16 is not set\n# CONFIG_GPIO_PCIE_IDIO_24 is not set\n# CONFIG_GPIO_RDC321X is not set\n# end of PCI GPIO expanders\n\n#\n# SPI GPIO expanders\n#\n# CONFIG_GPIO_74X164 is not set\nCONFIG_GPIO_ADI_DAQ1=y\n# CONFIG_GPIO_MAX3191X is not set\n# CONFIG_GPIO_MAX7301 is not set\n# CONFIG_GPIO_MC33880 is not set\n# CONFIG_GPIO_PISOSR is not set\n# CONFIG_GPIO_XRA1403 is not set\n# end of SPI GPIO expanders\n\n#\n# USB GPIO expanders\n#\n# end of USB GPIO expanders\n\n#\n# Virtual GPIO drivers\n#\n# CONFIG_GPIO_AGGREGATOR is not set\n# CONFIG_GPIO_MOCKUP is not set\n# CONFIG_GPIO_VIRTIO is not set\n# end of Virtual GPIO drivers\n\n# CONFIG_W1 is not set\nCONFIG_POWER_RESET=y\n# CONFIG_POWER_RESET_BRCMSTB is not set\n# CONFIG_POWER_RESET_GPIO is not set\n# CONFIG_POWER_RESET_GPIO_RESTART is not set\nCONFIG_POWER_RESET_LTC2952=y\n# CONFIG_POWER_RESET_REGULATOR is not set\n# CONFIG_POWER_RESET_RESTART is not set\n# CONFIG_POWER_RESET_TPS65086 is not set\n# CONFIG_POWER_RESET_XGENE is not set\n# CONFIG_POWER_RESET_SYSCON is not set\n# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set\n# CONFIG_SYSCON_REBOOT_MODE is not set\n# CONFIG_NVMEM_REBOOT_MODE is not set\nCONFIG_POWER_SUPPLY=y\n# CONFIG_POWER_SUPPLY_DEBUG is not set\nCONFIG_POWER_SUPPLY_HWMON=y\n# CONFIG_PDA_POWER is not set\n# CONFIG_GENERIC_ADC_BATTERY is not set\n# CONFIG_TEST_POWER is not set\nCONFIG_CHARGER_ADP5061=y\n# CONFIG_BATTERY_CW2015 is not set\n# CONFIG_BATTERY_DS2780 is not set\n# CONFIG_BATTERY_DS2781 is not set\n# CONFIG_BATTERY_DS2782 is not set\n# CONFIG_BATTERY_SBS is not set\n# CONFIG_CHARGER_SBS is not set\n# CONFIG_MANAGER_SBS is not set\n# CONFIG_BATTERY_BQ27XXX is not set\n# CONFIG_BATTERY_MAX17040 is not set\n# CONFIG_BATTERY_MAX17042 is not set\n# CONFIG_CHARGER_ISP1704 is not set\n# CONFIG_CHARGER_MAX8903 is not set\n# CONFIG_CHARGER_LP8727 is not set\n# CONFIG_CHARGER_GPIO is not set\n# CONFIG_CHARGER_MANAGER is not set\nCONFIG_CHARGER_LT3651=y\nCONFIG_CHARGER_LTC4162L=y\n# CONFIG_CHARGER_DETECTOR_MAX14656 is not set\n# CONFIG_CHARGER_BQ2415X is not set\n# CONFIG_CHARGER_BQ24190 is not set\n# CONFIG_CHARGER_BQ24257 is not set\n# CONFIG_CHARGER_BQ24735 is not set\n# CONFIG_CHARGER_BQ2515X is not set\n# CONFIG_CHARGER_BQ25890 is not set\n# CONFIG_CHARGER_BQ25980 is not set\n# CONFIG_CHARGER_BQ256XX is not set\n# CONFIG_CHARGER_SMB347 is not set\nCONFIG_BATTERY_GAUGE_LTC2941=y\n# CONFIG_BATTERY_GOLDFISH is not set\n# CONFIG_BATTERY_RT5033 is not set\n# CONFIG_CHARGER_RT9455 is not set\n# CONFIG_CHARGER_UCS1002 is not set\n# CONFIG_CHARGER_BD99954 is not set\nCONFIG_HWMON=y\nCONFIG_HWMON_VID=y\n# CONFIG_HWMON_DEBUG_CHIP is not set\n\n#\n# Native drivers\n#\nCONFIG_SENSORS_AD7314=y\nCONFIG_SENSORS_AD7414=y\nCONFIG_SENSORS_AD7418=y\nCONFIG_SENSORS_ADM1021=y\nCONFIG_SENSORS_ADM1025=y\nCONFIG_SENSORS_ADM1026=y\nCONFIG_SENSORS_ADM1029=y\nCONFIG_SENSORS_ADM1031=y\nCONFIG_SENSORS_ADM1177=y\nCONFIG_SENSORS_ADM9240=y\nCONFIG_SENSORS_ADT7X10=y\nCONFIG_SENSORS_ADT7310=y\nCONFIG_SENSORS_ADT7410=y\nCONFIG_SENSORS_ADT7411=y\nCONFIG_SENSORS_ADT7462=y\nCONFIG_SENSORS_ADT7470=y\nCONFIG_SENSORS_ADT7475=y\n# CONFIG_SENSORS_AHT10 is not set\n# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set\n# CONFIG_SENSORS_AS370 is not set\n# CONFIG_SENSORS_ASC7621 is not set\nCONFIG_SENSORS_AXI_FAN_CONTROL=y\n# CONFIG_SENSORS_ASPEED is not set\n# CONFIG_SENSORS_ATXP1 is not set\n# CONFIG_SENSORS_CORSAIR_CPRO is not set\n# CONFIG_SENSORS_CORSAIR_PSU is not set\n# CONFIG_SENSORS_DRIVETEMP is not set\n# CONFIG_SENSORS_DS620 is not set\n# CONFIG_SENSORS_DS1621 is not set\n# CONFIG_SENSORS_I5K_AMB is not set\n# CONFIG_SENSORS_F71805F is not set\n# CONFIG_SENSORS_F71882FG is not set\n# CONFIG_SENSORS_F75375S is not set\n# CONFIG_SENSORS_FTSTEUTATES is not set\n# CONFIG_SENSORS_GL518SM is not set\n# CONFIG_SENSORS_GL520SM is not set\n# CONFIG_SENSORS_G760A is not set\n# CONFIG_SENSORS_G762 is not set\n# CONFIG_SENSORS_GPIO_FAN is not set\n# CONFIG_SENSORS_HIH6130 is not set\nCONFIG_SENSORS_IIO_HWMON=y\n# CONFIG_SENSORS_IT87 is not set\nCONFIG_SENSORS_JC42=y\n# CONFIG_SENSORS_POWR1220 is not set\n# CONFIG_SENSORS_LINEAGE is not set\nCONFIG_SENSORS_LTC2945=y\nCONFIG_SENSORS_LTC2947=y\nCONFIG_SENSORS_LTC2947_I2C=y\nCONFIG_SENSORS_LTC2947_SPI=y\nCONFIG_SENSORS_LTC2990=y\nCONFIG_SENSORS_LTC2992=y\nCONFIG_SENSORS_LTC4151=y\nCONFIG_SENSORS_LTC4215=y\nCONFIG_SENSORS_LTC4222=y\nCONFIG_SENSORS_LTC4245=y\nCONFIG_SENSORS_LTC4260=y\nCONFIG_SENSORS_LTC4261=y\n# CONFIG_SENSORS_MAX1111 is not set\n# CONFIG_SENSORS_MAX127 is not set\n# CONFIG_SENSORS_MAX16065 is not set\n# CONFIG_SENSORS_MAX1619 is not set\n# CONFIG_SENSORS_MAX1668 is not set\n# CONFIG_SENSORS_MAX197 is not set\n# CONFIG_SENSORS_MAX31722 is not set\n# CONFIG_SENSORS_MAX31730 is not set\n# CONFIG_SENSORS_MAX31760 is not set\nCONFIG_MAX31827=y\n# CONFIG_SENSORS_MAX6620 is not set\n# CONFIG_SENSORS_MAX6621 is not set\n# CONFIG_SENSORS_MAX6639 is not set\n# CONFIG_SENSORS_MAX6642 is not set\n# CONFIG_SENSORS_MAX6650 is not set\n# CONFIG_SENSORS_MAX6697 is not set\n# CONFIG_SENSORS_MAX31790 is not set\n# CONFIG_SENSORS_MCP3021 is not set\n# CONFIG_SENSORS_TC654 is not set\n# CONFIG_SENSORS_TPS23861 is not set\n# CONFIG_SENSORS_MR75203 is not set\n# CONFIG_SENSORS_ADCXX is not set\n# CONFIG_SENSORS_LM63 is not set\n# CONFIG_SENSORS_LM70 is not set\n# CONFIG_SENSORS_LM73 is not set\n# CONFIG_SENSORS_LM75 is not set\n# CONFIG_SENSORS_LM77 is not set\n# CONFIG_SENSORS_LM78 is not set\n# CONFIG_SENSORS_LM80 is not set\n# CONFIG_SENSORS_LM83 is not set\n# CONFIG_SENSORS_LM85 is not set\nCONFIG_SENSORS_LM87=y\nCONFIG_SENSORS_LM90=y\n# CONFIG_SENSORS_LM92 is not set\n# CONFIG_SENSORS_LM93 is not set\n# CONFIG_SENSORS_LM95234 is not set\n# CONFIG_SENSORS_LM95241 is not set\n# CONFIG_SENSORS_LM95245 is not set\n# CONFIG_SENSORS_PC87360 is not set\n# CONFIG_SENSORS_PC87427 is not set\n# CONFIG_SENSORS_NTC_THERMISTOR is not set\n# CONFIG_SENSORS_NCT6683 is not set\n# CONFIG_SENSORS_NCT6775 is not set\n# CONFIG_SENSORS_NCT7802 is not set\n# CONFIG_SENSORS_NCT7904 is not set\n# CONFIG_SENSORS_NPCM7XX is not set\n# CONFIG_SENSORS_NZXT_KRAKEN2 is not set\n# CONFIG_SENSORS_OCC_P8_I2C is not set\n# CONFIG_SENSORS_PCF8591 is not set\nCONFIG_PMBUS=y\nCONFIG_SENSORS_PMBUS=y\nCONFIG_SENSORS_ADM1266=y\nCONFIG_SENSORS_ADM1275=y\n# CONFIG_SENSORS_BEL_PFE is not set\n# CONFIG_SENSORS_BPA_RS600 is not set\n# CONFIG_SENSORS_FSP_3Y is not set\n# CONFIG_SENSORS_IBM_CFFPS is not set\n# CONFIG_SENSORS_DPS920AB is not set\n# CONFIG_SENSORS_INSPUR_IPSPS is not set\n# CONFIG_SENSORS_IR35221 is not set\n# CONFIG_SENSORS_IR36021 is not set\n# CONFIG_SENSORS_IR38064 is not set\n# CONFIG_SENSORS_IRPS5401 is not set\n# CONFIG_SENSORS_ISL68137 is not set\n# CONFIG_SENSORS_LM25066 is not set\nCONFIG_SENSORS_LTC2978=y\nCONFIG_SENSORS_LTC2978_REGULATOR=y\nCONFIG_SENSORS_LTC3815=y\n# CONFIG_SENSORS_MAX15301 is not set\n# CONFIG_SENSORS_MAX16064 is not set\n# CONFIG_SENSORS_MAX16601 is not set\n# CONFIG_SENSORS_MAX20730 is not set\nCONFIG_SENSORS_MAX20751=y\n# CONFIG_SENSORS_MAX31785 is not set\n# CONFIG_SENSORS_MAX34440 is not set\n# CONFIG_SENSORS_MAX8688 is not set\n# CONFIG_SENSORS_MP2888 is not set\n# CONFIG_SENSORS_MP2975 is not set\n# CONFIG_SENSORS_PIM4328 is not set\n# CONFIG_SENSORS_PM6764TR is not set\n# CONFIG_SENSORS_PXE1610 is not set\n# CONFIG_SENSORS_Q54SJ108A2 is not set\n# CONFIG_SENSORS_STPDDC60 is not set\n# CONFIG_SENSORS_TPS40422 is not set\n# CONFIG_SENSORS_TPS53679 is not set\n# CONFIG_SENSORS_TPS544 is not set\n# CONFIG_SENSORS_UCD9000 is not set\n# CONFIG_SENSORS_UCD9200 is not set\n# CONFIG_SENSORS_XDPE122 is not set\n# CONFIG_SENSORS_ZL6100 is not set\n# CONFIG_SENSORS_PWM_FAN is not set\n# CONFIG_SENSORS_SBTSI is not set\n# CONFIG_SENSORS_SBRMI is not set\n# CONFIG_SENSORS_SHT15 is not set\n# CONFIG_SENSORS_SHT21 is not set\n# CONFIG_SENSORS_SHT3x is not set\n# CONFIG_SENSORS_SHT4x is not set\n# CONFIG_SENSORS_SHTC1 is not set\n# CONFIG_SENSORS_SIS5595 is not set\n# CONFIG_SENSORS_DME1737 is not set\n# CONFIG_SENSORS_EMC1403 is not set\n# CONFIG_SENSORS_EMC2103 is not set\n# CONFIG_SENSORS_EMC6W201 is not set\n# CONFIG_SENSORS_SMSC47M1 is not set\n# CONFIG_SENSORS_SMSC47M192 is not set\n# CONFIG_SENSORS_SMSC47B397 is not set\n# CONFIG_SENSORS_SCH5627 is not set\n# CONFIG_SENSORS_SCH5636 is not set\n# CONFIG_SENSORS_STTS751 is not set\n# CONFIG_SENSORS_SMM665 is not set\n# CONFIG_SENSORS_ADC128D818 is not set\n# CONFIG_SENSORS_ADS7828 is not set\n# CONFIG_SENSORS_ADS7871 is not set\n# CONFIG_SENSORS_AMC6821 is not set\n# CONFIG_SENSORS_INA209 is not set\nCONFIG_SENSORS_INA2XX=y\n# CONFIG_SENSORS_INA3221 is not set\n# CONFIG_SENSORS_TC74 is not set\n# CONFIG_SENSORS_THMC50 is not set\n# CONFIG_SENSORS_TMP102 is not set\n# CONFIG_SENSORS_TMP103 is not set\n# CONFIG_SENSORS_TMP108 is not set\n# CONFIG_SENSORS_TMP401 is not set\n# CONFIG_SENSORS_TMP421 is not set\n# CONFIG_SENSORS_TMP513 is not set\n# CONFIG_SENSORS_VIA686A is not set\n# CONFIG_SENSORS_VT1211 is not set\n# CONFIG_SENSORS_VT8231 is not set\n# CONFIG_SENSORS_W83773G is not set\n# CONFIG_SENSORS_W83781D is not set\n# CONFIG_SENSORS_W83791D is not set\n# CONFIG_SENSORS_W83792D is not set\n# CONFIG_SENSORS_W83793 is not set\n# CONFIG_SENSORS_W83795 is not set\n# CONFIG_SENSORS_W83L785TS is not set\n# CONFIG_SENSORS_W83L786NG is not set\n# CONFIG_SENSORS_W83627HF is not set\n# CONFIG_SENSORS_W83627EHF is not set\n# CONFIG_THERMAL is not set\nCONFIG_WATCHDOG=y\nCONFIG_WATCHDOG_CORE=y\n# CONFIG_WATCHDOG_NOWAYOUT is not set\nCONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y\nCONFIG_WATCHDOG_OPEN_TIMEOUT=0\n# CONFIG_WATCHDOG_SYSFS is not set\n# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set\n\n#\n# Watchdog Pretimeout Governors\n#\n# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set\n\n#\n# Watchdog Device Drivers\n#\n# CONFIG_SOFT_WATCHDOG is not set\n# CONFIG_GPIO_WATCHDOG is not set\nCONFIG_XILINX_WATCHDOG=y\n# CONFIG_ZIIRAVE_WATCHDOG is not set\n# CONFIG_ARM_SP805_WATCHDOG is not set\n# CONFIG_ARM_SBSA_WATCHDOG is not set\nCONFIG_CADENCE_WATCHDOG=y\n# CONFIG_DW_WATCHDOG is not set\n# CONFIG_MAX63XX_WATCHDOG is not set\n# CONFIG_ARM_SMC_WATCHDOG is not set\n# CONFIG_ALIM7101_WDT is not set\n# CONFIG_I6300ESB_WDT is not set\n# CONFIG_MEN_A21_WDT is not set\n\n#\n# PCI-based Watchdog Cards\n#\n# CONFIG_PCIPCWATCHDOG is not set\n# CONFIG_WDTPCI is not set\n\n#\n# USB-based Watchdog Cards\n#\n# CONFIG_USBPCWATCHDOG is not set\nCONFIG_SSB_POSSIBLE=y\n# CONFIG_SSB is not set\nCONFIG_BCMA_POSSIBLE=y\n# CONFIG_BCMA is not set\n\n#\n# Multifunction device drivers\n#\nCONFIG_MFD_CORE=y\n# CONFIG_MFD_ACT8945A is not set\n# CONFIG_MFD_AS3711 is not set\n# CONFIG_MFD_AS3722 is not set\nCONFIG_PMIC_ADP5520=y\n# CONFIG_MFD_AAT2870_CORE is not set\n# CONFIG_MFD_ATMEL_FLEXCOM is not set\n# CONFIG_MFD_ATMEL_HLCDC is not set\n# CONFIG_MFD_BCM590XX is not set\n# CONFIG_MFD_BD9571MWV is not set\n# CONFIG_MFD_AXP20X_I2C is not set\n# CONFIG_MFD_MADERA is not set\n# CONFIG_PMIC_DA903X is not set\n# CONFIG_MFD_DA9052_SPI is not set\n# CONFIG_MFD_DA9052_I2C is not set\n# CONFIG_MFD_DA9055 is not set\n# CONFIG_MFD_DA9062 is not set\n# CONFIG_MFD_DA9063 is not set\n# CONFIG_MFD_DA9150 is not set\n# CONFIG_MFD_DLN2 is not set\n# CONFIG_MFD_GATEWORKS_GSC is not set\n# CONFIG_MFD_MC13XXX_SPI is not set\n# CONFIG_MFD_MC13XXX_I2C is not set\n# CONFIG_MFD_MP2629 is not set\n# CONFIG_MFD_HI6421_PMIC is not set\n# CONFIG_HTC_PASIC3 is not set\n# CONFIG_HTC_I2CPLD is not set\n# CONFIG_LPC_ICH is not set\n# CONFIG_LPC_SCH is not set\n# CONFIG_MFD_INTEL_PMT is not set\n# CONFIG_MFD_IQS62X is not set\n# CONFIG_MFD_JANZ_CMODIO is not set\n# CONFIG_MFD_KEMPLD is not set\n# CONFIG_MFD_88PM800 is not set\n# CONFIG_MFD_88PM805 is not set\n# CONFIG_MFD_88PM860X is not set\n# CONFIG_MFD_MAX14577 is not set\n# CONFIG_MFD_MAX77620 is not set\n# CONFIG_MFD_MAX77650 is not set\n# CONFIG_MFD_MAX77686 is not set\n# CONFIG_MFD_MAX77693 is not set\n# CONFIG_MFD_MAX77843 is not set\n# CONFIG_MFD_MAX8907 is not set\n# CONFIG_MFD_MAX8925 is not set\n# CONFIG_MFD_MAX8997 is not set\n# CONFIG_MFD_MAX8998 is not set\n# CONFIG_MFD_MT6360 is not set\n# CONFIG_MFD_MT6397 is not set\n# CONFIG_MFD_MENF21BMC is not set\n# CONFIG_EZX_PCAP is not set\n# CONFIG_MFD_CPCAP is not set\n# CONFIG_MFD_VIPERBOARD is not set\n# CONFIG_MFD_NTXEC is not set\n# CONFIG_MFD_RETU is not set\n# CONFIG_MFD_PCF50633 is not set\n# CONFIG_MFD_RDC321X is not set\n# CONFIG_MFD_RT4831 is not set\n# CONFIG_MFD_RT5033 is not set\n# CONFIG_MFD_RC5T583 is not set\n# CONFIG_MFD_RK808 is not set\n# CONFIG_MFD_RN5T618 is not set\n# CONFIG_MFD_SEC_CORE is not set\n# CONFIG_MFD_SI476X_CORE is not set\n# CONFIG_MFD_SM501 is not set\n# CONFIG_MFD_SKY81452 is not set\n# CONFIG_MFD_STMPE is not set\nCONFIG_MFD_SYSCON=y\n# CONFIG_MFD_TI_AM335X_TSCADC is not set\n# CONFIG_MFD_LP3943 is not set\n# CONFIG_MFD_LP8788 is not set\n# CONFIG_MFD_TI_LMU is not set\n# CONFIG_MFD_PALMAS is not set\n# CONFIG_TPS6105X is not set\n# CONFIG_TPS65010 is not set\n# CONFIG_TPS6507X is not set\nCONFIG_MFD_TPS65086=y\n# CONFIG_MFD_TPS65090 is not set\n# CONFIG_MFD_TPS65217 is not set\n# CONFIG_MFD_TI_LP873X is not set\n# CONFIG_MFD_TI_LP87565 is not set\n# CONFIG_MFD_TPS65218 is not set\n# CONFIG_MFD_TPS6586X is not set\n# CONFIG_MFD_TPS65910 is not set\n# CONFIG_MFD_TPS65912_I2C is not set\n# CONFIG_MFD_TPS65912_SPI is not set\n# CONFIG_MFD_TPS80031 is not set\n# CONFIG_TWL4030_CORE is not set\n# CONFIG_TWL6040_CORE is not set\n# CONFIG_MFD_WL1273_CORE is not set\n# CONFIG_MFD_LM3533 is not set\n# CONFIG_MFD_TC3589X is not set\n# CONFIG_MFD_TQMX86 is not set\n# CONFIG_MFD_VX855 is not set\n# CONFIG_MFD_LOCHNAGAR is not set\n# CONFIG_MFD_ARIZONA_I2C is not set\n# CONFIG_MFD_ARIZONA_SPI is not set\n# CONFIG_MFD_WM8400 is not set\n# CONFIG_MFD_WM831X_I2C is not set\n# CONFIG_MFD_WM831X_SPI is not set\n# CONFIG_MFD_WM8350_I2C is not set\n# CONFIG_MFD_WM8994 is not set\n# CONFIG_MFD_ROHM_BD718XX is not set\n# CONFIG_MFD_ROHM_BD70528 is not set\n# CONFIG_MFD_ROHM_BD71828 is not set\n# CONFIG_MFD_ROHM_BD957XMUF is not set\n# CONFIG_MFD_STPMIC1 is not set\n# CONFIG_MFD_STMFX is not set\n# CONFIG_MFD_ATC260X_I2C is not set\n# CONFIG_MFD_QCOM_PM8008 is not set\n# CONFIG_RAVE_SP_CORE is not set\n# CONFIG_MFD_INTEL_M10_BMC is not set\n# CONFIG_MFD_RSMU_I2C is not set\n# CONFIG_MFD_RSMU_SPI is not set\n# end of Multifunction device drivers\n\nCONFIG_REGULATOR=y\n# CONFIG_REGULATOR_DEBUG is not set\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\n# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set\n# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set\n# CONFIG_REGULATOR_88PG86X is not set\n# CONFIG_REGULATOR_ACT8865 is not set\nCONFIG_REGULATOR_AD5398=y\n# CONFIG_REGULATOR_DA9121 is not set\n# CONFIG_REGULATOR_DA9210 is not set\n# CONFIG_REGULATOR_DA9211 is not set\n# CONFIG_REGULATOR_FAN53555 is not set\n# CONFIG_REGULATOR_FAN53880 is not set\nCONFIG_REGULATOR_GPIO=y\n# CONFIG_REGULATOR_ISL9305 is not set\n# CONFIG_REGULATOR_ISL6271A is not set\n# CONFIG_REGULATOR_LP3971 is not set\n# CONFIG_REGULATOR_LP3972 is not set\n# CONFIG_REGULATOR_LP872X is not set\n# CONFIG_REGULATOR_LP8755 is not set\nCONFIG_REGULATOR_LTC3589=y\nCONFIG_REGULATOR_LTC3676=y\n# CONFIG_REGULATOR_MAX1586 is not set\n# CONFIG_REGULATOR_MAX8649 is not set\n# CONFIG_REGULATOR_MAX8660 is not set\n# CONFIG_REGULATOR_MAX8893 is not set\n# CONFIG_REGULATOR_MAX8952 is not set\n# CONFIG_REGULATOR_MAX77826 is not set\n# CONFIG_REGULATOR_MCP16502 is not set\n# CONFIG_REGULATOR_MP5416 is not set\n# CONFIG_REGULATOR_MP8859 is not set\n# CONFIG_REGULATOR_MP886X is not set\n# CONFIG_REGULATOR_MPQ7920 is not set\n# CONFIG_REGULATOR_MT6311 is not set\n# CONFIG_REGULATOR_PCA9450 is not set\n# CONFIG_REGULATOR_PF8X00 is not set\n# CONFIG_REGULATOR_PFUZE100 is not set\n# CONFIG_REGULATOR_PV88060 is not set\n# CONFIG_REGULATOR_PV88080 is not set\n# CONFIG_REGULATOR_PV88090 is not set\n# CONFIG_REGULATOR_PWM is not set\n# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set\n# CONFIG_REGULATOR_RT4801 is not set\n# CONFIG_REGULATOR_RT6160 is not set\n# CONFIG_REGULATOR_RT6245 is not set\n# CONFIG_REGULATOR_RTQ2134 is not set\n# CONFIG_REGULATOR_RTMV20 is not set\n# CONFIG_REGULATOR_RTQ6752 is not set\n# CONFIG_REGULATOR_SLG51000 is not set\n# CONFIG_REGULATOR_SY8106A is not set\n# CONFIG_REGULATOR_SY8824X is not set\n# CONFIG_REGULATOR_SY8827N is not set\n# CONFIG_REGULATOR_TPS51632 is not set\n# CONFIG_REGULATOR_TPS62360 is not set\n# CONFIG_REGULATOR_TPS65023 is not set\n# CONFIG_REGULATOR_TPS6507X is not set\nCONFIG_REGULATOR_TPS65086=y\n# CONFIG_REGULATOR_TPS65132 is not set\n# CONFIG_REGULATOR_TPS6524X is not set\n# CONFIG_REGULATOR_VCTRL is not set\n# CONFIG_RC_CORE is not set\nCONFIG_CEC_CORE=y\nCONFIG_MEDIA_CEC_SUPPORT=y\n# CONFIG_CEC_CH7322 is not set\n# CONFIG_USB_PULSE8_CEC is not set\n# CONFIG_USB_RAINSHADOW_CEC is not set\nCONFIG_MEDIA_SUPPORT=y\n# CONFIG_MEDIA_SUPPORT_FILTER is not set\n# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set\n\n#\n# Media device types\n#\nCONFIG_MEDIA_CAMERA_SUPPORT=y\nCONFIG_MEDIA_ANALOG_TV_SUPPORT=y\nCONFIG_MEDIA_DIGITAL_TV_SUPPORT=y\nCONFIG_MEDIA_RADIO_SUPPORT=y\nCONFIG_MEDIA_SDR_SUPPORT=y\nCONFIG_MEDIA_PLATFORM_SUPPORT=y\nCONFIG_MEDIA_TEST_SUPPORT=y\n# end of Media device types\n\n#\n# Media core support\n#\nCONFIG_VIDEO_DEV=y\nCONFIG_MEDIA_CONTROLLER=y\nCONFIG_DVB_CORE=y\n# end of Media core support\n\n#\n# Video4Linux options\n#\nCONFIG_VIDEO_V4L2=y\nCONFIG_VIDEO_V4L2_I2C=y\nCONFIG_VIDEO_V4L2_SUBDEV_API=y\nCONFIG_VIDEO_ADV_DEBUG=y\n# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set\nCONFIG_V4L2_MEM2MEM_DEV=y\n# CONFIG_V4L2_FLASH_LED_CLASS is not set\nCONFIG_V4L2_FWNODE=y\nCONFIG_V4L2_ASYNC=y\n# end of Video4Linux options\n\n#\n# Media controller options\n#\n# CONFIG_MEDIA_CONTROLLER_DVB is not set\n# end of Media controller options\n\n#\n# Digital TV options\n#\n# CONFIG_DVB_MMAP is not set\nCONFIG_DVB_NET=y\nCONFIG_DVB_MAX_ADAPTERS=16\nCONFIG_DVB_DYNAMIC_MINORS=y\n# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set\n# CONFIG_DVB_ULE_DEBUG is not set\n# end of Digital TV options\n\n#\n# Media drivers\n#\nCONFIG_MEDIA_USB_SUPPORT=y\n\n#\n# Webcam devices\n#\nCONFIG_USB_VIDEO_CLASS=y\nCONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y\n# CONFIG_USB_GSPCA is not set\n# CONFIG_USB_PWC is not set\n# CONFIG_VIDEO_CPIA2 is not set\n# CONFIG_USB_ZR364XX is not set\n# CONFIG_USB_STKWEBCAM is not set\n# CONFIG_USB_S2255 is not set\n# CONFIG_VIDEO_USBTV is not set\n\n#\n# Analog TV USB devices\n#\n# CONFIG_VIDEO_PVRUSB2 is not set\n# CONFIG_VIDEO_HDPVR is not set\n# CONFIG_VIDEO_STK1160_COMMON is not set\n# CONFIG_VIDEO_GO7007 is not set\n\n#\n# Analog/digital TV USB devices\n#\n# CONFIG_VIDEO_AU0828 is not set\n# CONFIG_VIDEO_CX231XX is not set\n\n#\n# Digital TV USB devices\n#\n# CONFIG_DVB_USB_V2 is not set\n# CONFIG_DVB_TTUSB_BUDGET is not set\n# CONFIG_DVB_TTUSB_DEC is not set\n# CONFIG_SMS_USB_DRV is not set\n# CONFIG_DVB_B2C2_FLEXCOP_USB is not set\n# CONFIG_DVB_AS102 is not set\n\n#\n# Webcam, TV (analog/digital) USB devices\n#\n# CONFIG_VIDEO_EM28XX is not set\n\n#\n# Software defined radio USB devices\n#\n# CONFIG_USB_AIRSPY is not set\n# CONFIG_USB_HACKRF is not set\n# CONFIG_USB_MSI2500 is not set\n# CONFIG_MEDIA_PCI_SUPPORT is not set\nCONFIG_RADIO_ADAPTERS=y\n# CONFIG_RADIO_SI470X is not set\n# CONFIG_RADIO_SI4713 is not set\n# CONFIG_USB_MR800 is not set\n# CONFIG_USB_DSBR is not set\n# CONFIG_RADIO_MAXIRADIO is not set\n# CONFIG_RADIO_SHARK is not set\n# CONFIG_RADIO_SHARK2 is not set\n# CONFIG_USB_KEENE is not set\n# CONFIG_USB_RAREMONO is not set\n# CONFIG_USB_MA901 is not set\n# CONFIG_RADIO_TEA5764 is not set\n# CONFIG_RADIO_SAA7706H is not set\n# CONFIG_RADIO_TEF6862 is not set\n# CONFIG_RADIO_WL1273 is not set\n# CONFIG_RADIO_WL128X is not set\nCONFIG_VIDEOBUF2_CORE=y\nCONFIG_VIDEOBUF2_V4L2=y\nCONFIG_VIDEOBUF2_MEMOPS=y\nCONFIG_VIDEOBUF2_DMA_CONTIG=y\nCONFIG_VIDEOBUF2_VMALLOC=y\nCONFIG_V4L_PLATFORM_DRIVERS=y\n# CONFIG_VIDEO_CAFE_CCIC is not set\n# CONFIG_VIDEO_CADENCE is not set\n# CONFIG_VIDEO_ASPEED is not set\n# CONFIG_VIDEO_MUX is not set\nCONFIG_VIDEO_AXI_HDMI_RX=y\n# CONFIG_VIDEO_IMAGEON_BRIDGE is not set\nCONFIG_VIDEO_XILINX=y\nCONFIG_VIDEO_XILINX_CSI2RXSS=y\nCONFIG_VIDEO_XILINX_AXI4S_SWITCH=y\nCONFIG_VIDEO_XILINX_CFA=y\nCONFIG_VIDEO_XILINX_CRESAMPLE=y\nCONFIG_VIDEO_XILINX_DEMOSAIC=y\nCONFIG_VIDEO_XILINX_GAMMA=y\n# CONFIG_VIDEO_XILINX_HDMI21RXSS is not set\nCONFIG_VIDEO_XILINX_HLS=y\nCONFIG_VIDEO_XILINX_REMAPPER=y\nCONFIG_VIDEO_XILINX_RGB2YUV=y\nCONFIG_VIDEO_XILINX_SCALER=y\nCONFIG_VIDEO_XILINX_MULTISCALER=y\nCONFIG_VIDEO_XILINX_SDIRXSS=y\nCONFIG_VIDEO_XILINX_SWITCH=y\nCONFIG_VIDEO_XILINX_TPG=y\nCONFIG_VIDEO_XILINX_VPSS_CSC=y\nCONFIG_VIDEO_XILINX_VPSS_SCALER=y\nCONFIG_VIDEO_XILINX_VTC=y\n# CONFIG_VIDEO_XILINX_DPRXSS is not set\nCONFIG_VIDEO_XILINX_SCD=y\nCONFIG_VIDEO_XILINX_M2M=y\n# CONFIG_VIDEO_XILINX_AXI4S_BROADCASTER is not set\n# CONFIG_VIDEO_XILINX_AXI4S_SUBSETCONV is not set\n# CONFIG_V4L_MEM2MEM_DRIVERS is not set\nCONFIG_ADI_AXI_VIDEO_FRAME_BUFFER=y\n# CONFIG_DVB_PLATFORM_DRIVERS is not set\n# CONFIG_SDR_PLATFORM_DRIVERS is not set\n\n#\n# MMC/SDIO DVB adapters\n#\n# CONFIG_SMS_SDIO_DRV is not set\n# CONFIG_V4L_TEST_DRIVERS is not set\n# CONFIG_DVB_TEST_DRIVERS is not set\n# end of Media drivers\n\n#\n# Media ancillary drivers\n#\nCONFIG_MEDIA_ATTACH=y\n\n#\n# Audio decoders, processors and mixers\n#\n# CONFIG_VIDEO_TVAUDIO is not set\n# CONFIG_VIDEO_TDA7432 is not set\n# CONFIG_VIDEO_TDA9840 is not set\n# CONFIG_VIDEO_TDA1997X is not set\n# CONFIG_VIDEO_TEA6415C is not set\n# CONFIG_VIDEO_TEA6420 is not set\n# CONFIG_VIDEO_MSP3400 is not set\n# CONFIG_VIDEO_CS3308 is not set\n# CONFIG_VIDEO_CS5345 is not set\n# CONFIG_VIDEO_CS53L32A is not set\n# CONFIG_VIDEO_TLV320AIC23B is not set\n# CONFIG_VIDEO_UDA1342 is not set\n# CONFIG_VIDEO_WM8775 is not set\n# CONFIG_VIDEO_WM8739 is not set\n# CONFIG_VIDEO_VP27SMPX is not set\n# CONFIG_VIDEO_SONY_BTF_MPX is not set\n# end of Audio decoders, processors and mixers\n\n#\n# RDS decoders\n#\n# CONFIG_VIDEO_SAA6588 is not set\n# end of RDS decoders\n\n#\n# Video decoders\n#\nCONFIG_VIDEO_ADV7180=y\nCONFIG_VIDEO_ADV7183=y\nCONFIG_VIDEO_ADV748X=y\nCONFIG_VIDEO_ADV7604=y\nCONFIG_VIDEO_ADV7604_CEC=y\nCONFIG_VIDEO_ADV7842=y\nCONFIG_VIDEO_ADV7842_CEC=y\n# CONFIG_VIDEO_BT819 is not set\n# CONFIG_VIDEO_BT856 is not set\n# CONFIG_VIDEO_BT866 is not set\n# CONFIG_VIDEO_KS0127 is not set\n# CONFIG_VIDEO_ML86V7667 is not set\n# CONFIG_VIDEO_SAA7110 is not set\n# CONFIG_VIDEO_SAA711X is not set\n# CONFIG_VIDEO_TC358743 is not set\n# CONFIG_VIDEO_TVP514X is not set\n# CONFIG_VIDEO_TVP5150 is not set\n# CONFIG_VIDEO_TVP7002 is not set\n# CONFIG_VIDEO_TW2804 is not set\n# CONFIG_VIDEO_TW9903 is not set\n# CONFIG_VIDEO_TW9906 is not set\n# CONFIG_VIDEO_TW9910 is not set\n# CONFIG_VIDEO_VPX3220 is not set\n# CONFIG_VIDEO_MAX9286 is not set\n\n#\n# Video and audio decoders\n#\n# CONFIG_VIDEO_SAA717X is not set\n# CONFIG_VIDEO_CX25840 is not set\n# end of Video decoders\n\n#\n# Video encoders\n#\n# CONFIG_VIDEO_SAA7127 is not set\n# CONFIG_VIDEO_SAA7185 is not set\nCONFIG_VIDEO_ADV7170=y\nCONFIG_VIDEO_ADV7175=y\nCONFIG_VIDEO_ADV7343=y\nCONFIG_VIDEO_ADV7393=y\nCONFIG_VIDEO_AD9389B=y\n# CONFIG_VIDEO_AK881X is not set\n# CONFIG_VIDEO_THS8200 is not set\n# end of Video encoders\n\n#\n# Video improvement chips\n#\n# CONFIG_VIDEO_UPD64031A is not set\n# CONFIG_VIDEO_UPD64083 is not set\n# end of Video improvement chips\n\n# CONFIG_VIDEO_AP1302 is not set\n\n#\n# Audio/Video compression chips\n#\n# CONFIG_VIDEO_SAA6752HS is not set\n# end of Audio/Video compression chips\n\n#\n# SDR tuner chips\n#\n# CONFIG_SDR_MAX2175 is not set\n# end of SDR tuner chips\n\n#\n# Miscellaneous helper chips\n#\n# CONFIG_VIDEO_THS7303 is not set\n# CONFIG_VIDEO_M52790 is not set\n# CONFIG_VIDEO_I2C is not set\n# CONFIG_VIDEO_ST_MIPID02 is not set\n# end of Miscellaneous helper chips\n\n#\n# Camera sensor devices\n#\nCONFIG_VIDEO_ADDI9036=y\n# CONFIG_VIDEO_HI556 is not set\n# CONFIG_VIDEO_IMX208 is not set\n# CONFIG_VIDEO_IMX214 is not set\n# CONFIG_VIDEO_IMX219 is not set\n# CONFIG_VIDEO_IMX258 is not set\n# CONFIG_VIDEO_IMX274 is not set\n# CONFIG_VIDEO_IMX290 is not set\n# CONFIG_VIDEO_IMX319 is not set\n# CONFIG_VIDEO_IMX334 is not set\n# CONFIG_VIDEO_IMX335 is not set\n# CONFIG_VIDEO_IMX355 is not set\n# CONFIG_VIDEO_IMX412 is not set\n# CONFIG_VIDEO_OV02A10 is not set\n# CONFIG_VIDEO_OV2640 is not set\n# CONFIG_VIDEO_OV2659 is not set\n# CONFIG_VIDEO_OV2680 is not set\n# CONFIG_VIDEO_OV2685 is not set\n# CONFIG_VIDEO_OV5640 is not set\n# CONFIG_VIDEO_OV5645 is not set\n# CONFIG_VIDEO_OV5647 is not set\n# CONFIG_VIDEO_OV5648 is not set\n# CONFIG_VIDEO_OV6650 is not set\n# CONFIG_VIDEO_OV5670 is not set\n# CONFIG_VIDEO_OV5675 is not set\n# CONFIG_VIDEO_OV5695 is not set\n# CONFIG_VIDEO_OV7251 is not set\n# CONFIG_VIDEO_OV772X is not set\n# CONFIG_VIDEO_OV7640 is not set\n# CONFIG_VIDEO_OV7670 is not set\n# CONFIG_VIDEO_OV7740 is not set\n# CONFIG_VIDEO_OV8856 is not set\n# CONFIG_VIDEO_OV8865 is not set\n# CONFIG_VIDEO_OV9282 is not set\n# CONFIG_VIDEO_OV9640 is not set\n# CONFIG_VIDEO_OV9650 is not set\n# CONFIG_VIDEO_OV13858 is not set\n# CONFIG_VIDEO_VS6624 is not set\n# CONFIG_VIDEO_MT9M001 is not set\n# CONFIG_VIDEO_MT9M032 is not set\n# CONFIG_VIDEO_MT9M111 is not set\n# CONFIG_VIDEO_MT9P031 is not set\n# CONFIG_VIDEO_MT9T001 is not set\n# CONFIG_VIDEO_MT9T112 is not set\n# CONFIG_VIDEO_MT9V011 is not set\n# CONFIG_VIDEO_MT9V032 is not set\n# CONFIG_VIDEO_MT9V111 is not set\n# CONFIG_VIDEO_SR030PC30 is not set\n# CONFIG_VIDEO_NOON010PC30 is not set\n# CONFIG_VIDEO_M5MOLS is not set\n# CONFIG_VIDEO_RDACM20 is not set\n# CONFIG_VIDEO_RDACM21 is not set\n# CONFIG_VIDEO_RJ54N1 is not set\n# CONFIG_VIDEO_S5K6AA is not set\n# CONFIG_VIDEO_S5K6A3 is not set\n# CONFIG_VIDEO_S5K4ECGX is not set\n# CONFIG_VIDEO_S5K5BAF is not set\n# CONFIG_VIDEO_CCS is not set\n# CONFIG_VIDEO_ET8EK8 is not set\n# CONFIG_VIDEO_S5C73M3 is not set\n# end of Camera sensor devices\n\n#\n# Lens drivers\n#\n# CONFIG_VIDEO_AD5820 is not set\n# CONFIG_VIDEO_AK7375 is not set\n# CONFIG_VIDEO_DW9714 is not set\n# CONFIG_VIDEO_DW9768 is not set\n# CONFIG_VIDEO_DW9807_VCM is not set\n# end of Lens drivers\n\n#\n# Flash devices\n#\nCONFIG_VIDEO_ADP1653=y\n# CONFIG_VIDEO_LM3560 is not set\n# CONFIG_VIDEO_LM3646 is not set\n# end of Flash devices\n\n#\n# SPI helper chips\n#\n# CONFIG_VIDEO_GS1662 is not set\n# end of SPI helper chips\n\n#\n# Media SPI Adapters\n#\nCONFIG_CXD2880_SPI_DRV=m\n# end of Media SPI Adapters\n\nCONFIG_MEDIA_TUNER=y\n\n#\n# Customize TV tuners\n#\nCONFIG_MEDIA_TUNER_SIMPLE=m\nCONFIG_MEDIA_TUNER_TDA18250=m\nCONFIG_MEDIA_TUNER_TDA8290=m\nCONFIG_MEDIA_TUNER_TDA827X=m\nCONFIG_MEDIA_TUNER_TDA18271=m\nCONFIG_MEDIA_TUNER_TDA9887=m\nCONFIG_MEDIA_TUNER_TEA5761=m\nCONFIG_MEDIA_TUNER_TEA5767=m\nCONFIG_MEDIA_TUNER_MSI001=m\nCONFIG_MEDIA_TUNER_MT20XX=m\nCONFIG_MEDIA_TUNER_MT2060=m\nCONFIG_MEDIA_TUNER_MT2063=m\nCONFIG_MEDIA_TUNER_MT2266=m\nCONFIG_MEDIA_TUNER_MT2131=m\nCONFIG_MEDIA_TUNER_QT1010=m\nCONFIG_MEDIA_TUNER_XC2028=m\nCONFIG_MEDIA_TUNER_XC5000=m\nCONFIG_MEDIA_TUNER_XC4000=m\nCONFIG_MEDIA_TUNER_MXL5005S=m\nCONFIG_MEDIA_TUNER_MXL5007T=m\nCONFIG_MEDIA_TUNER_MC44S803=m\nCONFIG_MEDIA_TUNER_MAX2165=m\nCONFIG_MEDIA_TUNER_TDA18218=m\nCONFIG_MEDIA_TUNER_FC0011=m\nCONFIG_MEDIA_TUNER_FC0012=m\nCONFIG_MEDIA_TUNER_FC0013=m\nCONFIG_MEDIA_TUNER_TDA18212=m\nCONFIG_MEDIA_TUNER_E4000=m\nCONFIG_MEDIA_TUNER_FC2580=m\nCONFIG_MEDIA_TUNER_M88RS6000T=m\nCONFIG_MEDIA_TUNER_TUA9001=m\nCONFIG_MEDIA_TUNER_SI2157=m\nCONFIG_MEDIA_TUNER_IT913X=m\nCONFIG_MEDIA_TUNER_R820T=m\nCONFIG_MEDIA_TUNER_MXL301RF=m\nCONFIG_MEDIA_TUNER_QM1D1C0042=m\nCONFIG_MEDIA_TUNER_QM1D1B0004=m\n# end of Customize TV tuners\n\n#\n# Customise DVB Frontends\n#\n\n#\n# Multistandard (satellite) frontends\n#\nCONFIG_DVB_STB0899=m\nCONFIG_DVB_STB6100=m\nCONFIG_DVB_STV090x=m\nCONFIG_DVB_STV0910=m\nCONFIG_DVB_STV6110x=m\nCONFIG_DVB_STV6111=m\nCONFIG_DVB_MXL5XX=m\nCONFIG_DVB_M88DS3103=m\n\n#\n# Multistandard (cable + terrestrial) frontends\n#\nCONFIG_DVB_DRXK=m\nCONFIG_DVB_TDA18271C2DD=m\nCONFIG_DVB_SI2165=m\nCONFIG_DVB_MN88472=m\nCONFIG_DVB_MN88473=m\n\n#\n# DVB-S (satellite) frontends\n#\nCONFIG_DVB_CX24110=m\nCONFIG_DVB_CX24123=m\nCONFIG_DVB_MT312=m\nCONFIG_DVB_ZL10036=m\nCONFIG_DVB_ZL10039=m\nCONFIG_DVB_S5H1420=m\nCONFIG_DVB_STV0288=m\nCONFIG_DVB_STB6000=m\nCONFIG_DVB_STV0299=m\nCONFIG_DVB_STV6110=m\nCONFIG_DVB_STV0900=m\nCONFIG_DVB_TDA8083=m\nCONFIG_DVB_TDA10086=m\nCONFIG_DVB_TDA8261=m\nCONFIG_DVB_VES1X93=m\nCONFIG_DVB_TUNER_ITD1000=m\nCONFIG_DVB_TUNER_CX24113=m\nCONFIG_DVB_TDA826X=m\nCONFIG_DVB_TUA6100=m\nCONFIG_DVB_CX24116=m\nCONFIG_DVB_CX24117=m\nCONFIG_DVB_CX24120=m\nCONFIG_DVB_SI21XX=m\nCONFIG_DVB_TS2020=m\nCONFIG_DVB_DS3000=m\nCONFIG_DVB_MB86A16=m\nCONFIG_DVB_TDA10071=m\n\n#\n# DVB-T (terrestrial) frontends\n#\nCONFIG_DVB_SP887X=m\nCONFIG_DVB_CX22700=m\nCONFIG_DVB_CX22702=m\nCONFIG_DVB_S5H1432=m\nCONFIG_DVB_DRXD=m\nCONFIG_DVB_L64781=m\nCONFIG_DVB_TDA1004X=m\nCONFIG_DVB_NXT6000=m\nCONFIG_DVB_MT352=m\nCONFIG_DVB_ZL10353=m\nCONFIG_DVB_DIB3000MB=m\nCONFIG_DVB_DIB3000MC=m\nCONFIG_DVB_DIB7000M=m\nCONFIG_DVB_DIB7000P=m\nCONFIG_DVB_DIB9000=m\nCONFIG_DVB_TDA10048=m\nCONFIG_DVB_AF9013=m\nCONFIG_DVB_EC100=m\nCONFIG_DVB_STV0367=m\nCONFIG_DVB_CXD2820R=m\nCONFIG_DVB_CXD2841ER=m\nCONFIG_DVB_RTL2830=m\nCONFIG_DVB_RTL2832=m\nCONFIG_DVB_RTL2832_SDR=m\nCONFIG_DVB_SI2168=m\nCONFIG_DVB_ZD1301_DEMOD=m\nCONFIG_DVB_CXD2880=m\n\n#\n# DVB-C (cable) frontends\n#\nCONFIG_DVB_VES1820=m\nCONFIG_DVB_TDA10021=m\nCONFIG_DVB_TDA10023=m\nCONFIG_DVB_STV0297=m\n\n#\n# ATSC (North American/Korean Terrestrial/Cable DTV) frontends\n#\nCONFIG_DVB_NXT200X=m\nCONFIG_DVB_OR51211=m\nCONFIG_DVB_OR51132=m\nCONFIG_DVB_BCM3510=m\nCONFIG_DVB_LGDT330X=m\nCONFIG_DVB_LGDT3305=m\nCONFIG_DVB_LGDT3306A=m\nCONFIG_DVB_LG2160=m\nCONFIG_DVB_S5H1409=m\nCONFIG_DVB_AU8522=m\nCONFIG_DVB_AU8522_DTV=m\nCONFIG_DVB_AU8522_V4L=m\nCONFIG_DVB_S5H1411=m\nCONFIG_DVB_MXL692=m\n\n#\n# ISDB-T (terrestrial) frontends\n#\nCONFIG_DVB_S921=m\nCONFIG_DVB_DIB8000=m\nCONFIG_DVB_MB86A20S=m\n\n#\n# ISDB-S (satellite) & ISDB-T (terrestrial) frontends\n#\nCONFIG_DVB_TC90522=m\nCONFIG_DVB_MN88443X=m\n\n#\n# Digital terrestrial only tuners/PLL\n#\nCONFIG_DVB_PLL=m\nCONFIG_DVB_TUNER_DIB0070=m\nCONFIG_DVB_TUNER_DIB0090=m\n\n#\n# SEC control devices for DVB-S\n#\nCONFIG_DVB_DRX39XYJ=m\nCONFIG_DVB_LNBH25=m\nCONFIG_DVB_LNBH29=m\nCONFIG_DVB_LNBP21=m\nCONFIG_DVB_LNBP22=m\nCONFIG_DVB_ISL6405=m\nCONFIG_DVB_ISL6421=m\nCONFIG_DVB_ISL6423=m\nCONFIG_DVB_A8293=m\nCONFIG_DVB_LGS8GL5=m\nCONFIG_DVB_LGS8GXX=m\nCONFIG_DVB_ATBM8830=m\nCONFIG_DVB_TDA665x=m\nCONFIG_DVB_IX2505V=m\nCONFIG_DVB_M88RS2000=m\nCONFIG_DVB_AF9033=m\nCONFIG_DVB_HORUS3A=m\nCONFIG_DVB_ASCOT2E=m\nCONFIG_DVB_HELENE=m\n\n#\n# Common Interface (EN50221) controller drivers\n#\nCONFIG_DVB_CXD2099=m\nCONFIG_DVB_SP2=m\n# end of Customise DVB Frontends\n\n#\n# Tools to develop new frontends\n#\n# CONFIG_DVB_DUMMY_FE is not set\n# end of Media ancillary drivers\n\n#\n# Graphics support\n#\n# CONFIG_VGA_ARB is not set\nCONFIG_DRM=y\nCONFIG_DRM_MIPI_DSI=y\n# CONFIG_DRM_DP_AUX_CHARDEV is not set\n# CONFIG_DRM_DEBUG_MM is not set\n# CONFIG_DRM_DEBUG_SELFTEST is not set\nCONFIG_DRM_KMS_HELPER=y\n# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set\nCONFIG_DRM_FBDEV_EMULATION=y\nCONFIG_DRM_FBDEV_OVERALLOC=100\n# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set\n# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set\n# CONFIG_DRM_DP_CEC is not set\nCONFIG_DRM_GEM_CMA_HELPER=y\nCONFIG_DRM_KMS_CMA_HELPER=y\n\n#\n# I2C encoder or helper chips\n#\n# CONFIG_DRM_I2C_CH7006 is not set\n# CONFIG_DRM_I2C_SIL164 is not set\n# CONFIG_DRM_I2C_NXP_TDA998X is not set\n# CONFIG_DRM_I2C_NXP_TDA9950 is not set\n# end of I2C encoder or helper chips\n\n#\n# ARM devices\n#\n# CONFIG_DRM_HDLCD is not set\n# CONFIG_DRM_MALI_DISPLAY is not set\n# CONFIG_DRM_KOMEDA is not set\n# end of ARM devices\n\n# CONFIG_DRM_RADEON is not set\n# CONFIG_DRM_AMDGPU is not set\n# CONFIG_DRM_NOUVEAU is not set\nCONFIG_DRM_ADI_AXI_HDMI=y\n# CONFIG_DRM_VGEM is not set\n# CONFIG_DRM_VKMS is not set\n# CONFIG_DRM_VMWGFX is not set\n# CONFIG_DRM_UDL is not set\n# CONFIG_DRM_AST is not set\n# CONFIG_DRM_MGAG200 is not set\n# CONFIG_DRM_RCAR_DW_HDMI is not set\n# CONFIG_DRM_RCAR_LVDS is not set\n# CONFIG_DRM_QXL is not set\n# CONFIG_DRM_VIRTIO_GPU is not set\nCONFIG_DRM_PANEL=y\n\n#\n# Display Panels\n#\n# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set\n# CONFIG_DRM_PANEL_ARM_VERSATILE is not set\n# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set\n# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set\n# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set\n# CONFIG_DRM_PANEL_DSI_CM is not set\n# CONFIG_DRM_PANEL_LVDS is not set\n# CONFIG_DRM_PANEL_SIMPLE is not set\n# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set\n# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set\n# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set\n# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set\n# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set\n# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set\n# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set\n# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set\n# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set\n# CONFIG_DRM_PANEL_KHADAS_TS050 is not set\n# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set\n# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set\n# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set\n# CONFIG_DRM_PANEL_LG_LB035Q02 is not set\n# CONFIG_DRM_PANEL_LG_LG4573 is not set\n# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set\n# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set\n# CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set\n# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set\n# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set\n# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set\n# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set\n# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set\n# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set\n# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set\n# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set\n# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set\n# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set\n# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set\n# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set\n# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set\n# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set\n# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set\n# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set\n# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set\n# CONFIG_DRM_PANEL_SONY_ACX424AKP is not set\n# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set\n# CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set\n# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set\n# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set\n# CONFIG_DRM_PANEL_TPO_TPG110 is not set\n# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set\n# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set\n# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set\n# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set\n# end of Display Panels\n\nCONFIG_DRM_BRIDGE=y\nCONFIG_DRM_PANEL_BRIDGE=y\n\n#\n# Display Interface Bridges\n#\n# CONFIG_DRM_CDNS_DSI is not set\n# CONFIG_DRM_CHIPONE_ICN6211 is not set\n# CONFIG_DRM_CHRONTEL_CH7033 is not set\n# CONFIG_DRM_DISPLAY_CONNECTOR is not set\n# CONFIG_DRM_LONTIUM_LT8912B is not set\n# CONFIG_DRM_LONTIUM_LT9611 is not set\n# CONFIG_DRM_LONTIUM_LT9611UXC is not set\n# CONFIG_DRM_ITE_IT66121 is not set\n# CONFIG_DRM_LVDS_CODEC is not set\n# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set\n# CONFIG_DRM_NWL_MIPI_DSI is not set\n# CONFIG_DRM_NXP_PTN3460 is not set\n# CONFIG_DRM_PARADE_PS8622 is not set\n# CONFIG_DRM_PARADE_PS8640 is not set\n# CONFIG_DRM_SIL_SII8620 is not set\n# CONFIG_DRM_SII902X is not set\n# CONFIG_DRM_SII9234 is not set\n# CONFIG_DRM_SIMPLE_BRIDGE is not set\n# CONFIG_DRM_THINE_THC63LVD1024 is not set\n# CONFIG_DRM_TOSHIBA_TC358762 is not set\n# CONFIG_DRM_TOSHIBA_TC358764 is not set\n# CONFIG_DRM_TOSHIBA_TC358767 is not set\n# CONFIG_DRM_TOSHIBA_TC358768 is not set\n# CONFIG_DRM_TOSHIBA_TC358775 is not set\n# CONFIG_DRM_TI_TFP410 is not set\n# CONFIG_DRM_TI_SN65DSI83 is not set\n# CONFIG_DRM_TI_SN65DSI86 is not set\n# CONFIG_DRM_TI_TPD12S015 is not set\n# CONFIG_DRM_ANALOGIX_ANX6345 is not set\n# CONFIG_DRM_ANALOGIX_ANX78XX is not set\n# CONFIG_DRM_ANALOGIX_ANX7625 is not set\nCONFIG_DRM_I2C_ADV7511=y\nCONFIG_DRM_I2C_ADV7511_AUDIO=y\nCONFIG_DRM_I2C_ADV7511_CEC=y\n# CONFIG_DRM_CDNS_MHDP8546 is not set\n# end of Display Interface Bridges\n\n# CONFIG_DRM_ETNAVIV is not set\n# CONFIG_DRM_HISI_HIBMC is not set\n# CONFIG_DRM_HISI_KIRIN is not set\n# CONFIG_DRM_MXSFB is not set\n# CONFIG_DRM_ARCPGU is not set\n# CONFIG_DRM_BOCHS is not set\n# CONFIG_DRM_CIRRUS_QEMU is not set\n# CONFIG_DRM_GM12U320 is not set\n# CONFIG_DRM_SIMPLEDRM is not set\n# CONFIG_TINYDRM_HX8357D is not set\n# CONFIG_TINYDRM_ILI9225 is not set\n# CONFIG_TINYDRM_ILI9341 is not set\n# CONFIG_TINYDRM_ILI9486 is not set\n# CONFIG_TINYDRM_MI0283QT is not set\n# CONFIG_TINYDRM_REPAPER is not set\n# CONFIG_TINYDRM_ST7586 is not set\n# CONFIG_TINYDRM_ST7735R is not set\n# CONFIG_DRM_PL111 is not set\n# CONFIG_DRM_LIMA is not set\n# CONFIG_DRM_PANFROST is not set\n# CONFIG_DRM_TIDSS is not set\nCONFIG_DRM_ZYNQMP_DPSUB=y\nCONFIG_DRM_XLNX=y\nCONFIG_DRM_XLNX_BRIDGE=y\nCONFIG_DRM_XLNX_BRIDGE_DEBUG_FS=y\n# CONFIG_DRM_XLNX_DPTX is not set\nCONFIG_DRM_XLNX_DSI=y\n# CONFIG_DRM_XLNX_HDMITX is not set\nCONFIG_DRM_XLNX_MIXER=y\nCONFIG_DRM_XLNX_PL_DISP=y\nCONFIG_DRM_XLNX_SDI=y\nCONFIG_DRM_XLNX_BRIDGE_CSC=y\nCONFIG_DRM_XLNX_BRIDGE_SCALER=y\nCONFIG_DRM_XLNX_BRIDGE_VTC=y\n# CONFIG_DRM_GUD is not set\n# CONFIG_DRM_LEGACY is not set\nCONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y\n\n#\n# Frame buffer Devices\n#\nCONFIG_FB_CMDLINE=y\nCONFIG_FB_NOTIFY=y\nCONFIG_FB=y\n# CONFIG_FIRMWARE_EDID is not set\nCONFIG_FB_CFB_FILLRECT=y\nCONFIG_FB_CFB_COPYAREA=y\nCONFIG_FB_CFB_IMAGEBLIT=y\nCONFIG_FB_SYS_FILLRECT=y\nCONFIG_FB_SYS_COPYAREA=y\nCONFIG_FB_SYS_IMAGEBLIT=y\n# CONFIG_FB_FOREIGN_ENDIAN is not set\nCONFIG_FB_SYS_FOPS=y\nCONFIG_FB_DEFERRED_IO=y\nCONFIG_FB_BACKLIGHT=y\n# CONFIG_FB_MODE_HELPERS is not set\n# CONFIG_FB_TILEBLITTING is not set\n\n#\n# Frame buffer hardware drivers\n#\n# CONFIG_FB_ALTERA_VIP is not set\n# CONFIG_FB_CIRRUS is not set\n# CONFIG_FB_PM2 is not set\n# CONFIG_FB_ARMCLCD is not set\n# CONFIG_FB_CYBER2000 is not set\n# CONFIG_FB_ASILIANT is not set\n# CONFIG_FB_IMSTT is not set\n# CONFIG_FB_UVESA is not set\n# CONFIG_FB_EFI is not set\n# CONFIG_FB_OPENCORES is not set\n# CONFIG_FB_S1D13XXX is not set\n# CONFIG_FB_NVIDIA is not set\n# CONFIG_FB_RIVA is not set\n# CONFIG_FB_I740 is not set\n# CONFIG_FB_MATROX is not set\n# CONFIG_FB_RADEON is not set\n# CONFIG_FB_ATY128 is not set\n# CONFIG_FB_ATY is not set\n# CONFIG_FB_S3 is not set\n# CONFIG_FB_SAVAGE is not set\n# CONFIG_FB_SIS is not set\n# CONFIG_FB_NEOMAGIC is not set\n# CONFIG_FB_KYRO is not set\n# CONFIG_FB_3DFX is not set\n# CONFIG_FB_VOODOO1 is not set\n# CONFIG_FB_VT8623 is not set\n# CONFIG_FB_TRIDENT is not set\n# CONFIG_FB_ARK is not set\n# CONFIG_FB_PM3 is not set\n# CONFIG_FB_CARMINE is not set\n# CONFIG_FB_SMSCUFX is not set\n# CONFIG_FB_UDL is not set\n# CONFIG_FB_IBM_GXT4500 is not set\nCONFIG_FB_XILINX=y\n# CONFIG_FB_VIRTUAL is not set\n# CONFIG_FB_METRONOME is not set\n# CONFIG_FB_MB862XX is not set\n# CONFIG_FB_SIMPLE is not set\n# CONFIG_FB_SSD1307 is not set\n# CONFIG_FB_SM712 is not set\n# end of Frame buffer Devices\n\n#\n# Backlight & LCD device support\n#\n# CONFIG_LCD_CLASS_DEVICE is not set\nCONFIG_BACKLIGHT_CLASS_DEVICE=y\n# CONFIG_BACKLIGHT_KTD253 is not set\n# CONFIG_BACKLIGHT_PWM is not set\n# CONFIG_BACKLIGHT_QCOM_WLED is not set\nCONFIG_BACKLIGHT_ADP5520=y\nCONFIG_BACKLIGHT_ADP8860=y\nCONFIG_BACKLIGHT_ADP8870=y\n# CONFIG_BACKLIGHT_LM3630A is not set\n# CONFIG_BACKLIGHT_LM3639 is not set\n# CONFIG_BACKLIGHT_LP855X is not set\n# CONFIG_BACKLIGHT_GPIO is not set\n# CONFIG_BACKLIGHT_LV5207LP is not set\n# CONFIG_BACKLIGHT_BD6107 is not set\n# CONFIG_BACKLIGHT_ARCXCNN is not set\n# CONFIG_BACKLIGHT_LED is not set\n# end of Backlight & LCD device support\n\nCONFIG_VIDEOMODE_HELPERS=y\nCONFIG_HDMI=y\n\n#\n# Console display driver support\n#\nCONFIG_DUMMY_CONSOLE=y\nCONFIG_DUMMY_CONSOLE_COLUMNS=80\nCONFIG_DUMMY_CONSOLE_ROWS=25\nCONFIG_FRAMEBUFFER_CONSOLE=y\n# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set\nCONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y\n# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set\n# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set\n# end of Console display driver support\n\n# CONFIG_LOGO is not set\n# end of Graphics support\n\nCONFIG_SOUND=y\nCONFIG_SND=y\nCONFIG_SND_TIMER=y\nCONFIG_SND_PCM=y\nCONFIG_SND_PCM_ELD=y\nCONFIG_SND_PCM_IEC958=y\nCONFIG_SND_DMAENGINE_PCM=y\nCONFIG_SND_HWDEP=y\nCONFIG_SND_RAWMIDI=y\nCONFIG_SND_JACK=y\nCONFIG_SND_JACK_INPUT_DEV=y\n# CONFIG_SND_OSSEMUL is not set\nCONFIG_SND_PCM_TIMER=y\n# CONFIG_SND_HRTIMER is not set\n# CONFIG_SND_DYNAMIC_MINORS is not set\nCONFIG_SND_SUPPORT_OLD_API=y\nCONFIG_SND_PROC_FS=y\nCONFIG_SND_VERBOSE_PROCFS=y\n# CONFIG_SND_VERBOSE_PRINTK is not set\n# CONFIG_SND_DEBUG is not set\n# CONFIG_SND_SEQUENCER is not set\n# CONFIG_SND_DRIVERS is not set\n# CONFIG_SND_PCI is not set\n\n#\n# HD-Audio\n#\n# end of HD-Audio\n\nCONFIG_SND_HDA_PREALLOC_SIZE=64\nCONFIG_SND_SPI=y\nCONFIG_SND_USB=y\nCONFIG_SND_USB_AUDIO=y\nCONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y\n# CONFIG_SND_USB_UA101 is not set\n# CONFIG_SND_USB_CAIAQ is not set\n# CONFIG_SND_USB_6FIRE is not set\n# CONFIG_SND_USB_HIFACE is not set\n# CONFIG_SND_BCD2000 is not set\n# CONFIG_SND_USB_POD is not set\n# CONFIG_SND_USB_PODHD is not set\n# CONFIG_SND_USB_TONEPORT is not set\n# CONFIG_SND_USB_VARIAX is not set\nCONFIG_SND_SOC=y\nCONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y\nCONFIG_SND_SOC_ADI=y\nCONFIG_SND_SOC_ADI_AXI_I2S=y\nCONFIG_SND_SOC_ADI_AXI_SPDIF=y\nCONFIG_SND_SOC_ADRV936X_BOX=y\n# CONFIG_SND_SOC_AMD_ACP is not set\n# CONFIG_SND_ATMEL_SOC is not set\n# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set\n# CONFIG_SND_DESIGNWARE_I2S is not set\n\n#\n# SoC Audio for Freescale CPUs\n#\n\n#\n# Common SoC Audio options for Freescale CPUs:\n#\n# CONFIG_SND_SOC_FSL_ASRC is not set\n# CONFIG_SND_SOC_FSL_SAI is not set\n# CONFIG_SND_SOC_FSL_AUDMIX is not set\n# CONFIG_SND_SOC_FSL_SSI is not set\n# CONFIG_SND_SOC_FSL_SPDIF is not set\n# CONFIG_SND_SOC_FSL_ESAI is not set\n# CONFIG_SND_SOC_FSL_MICFIL is not set\n# CONFIG_SND_SOC_FSL_XCVR is not set\n# CONFIG_SND_SOC_FSL_RPMSG is not set\n# CONFIG_SND_SOC_IMX_AUDMUX is not set\n# end of SoC Audio for Freescale CPUs\n\n# CONFIG_SND_I2S_HI6210_I2S is not set\n# CONFIG_SND_SOC_IMG is not set\n# CONFIG_SND_SOC_MTK_BTCVSD is not set\n# CONFIG_SND_SOC_SOF_TOPLEVEL is not set\n\n#\n# STMicroelectronics STM32 SOC audio support\n#\n# end of STMicroelectronics STM32 SOC audio support\n\nCONFIG_SND_SOC_XILINX_DP=y\nCONFIG_SND_SOC_XILINX_SDI=y\nCONFIG_SND_SOC_XILINX_I2S=y\nCONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=y\nCONFIG_SND_SOC_XILINX_SPDIF=y\nCONFIG_SND_SOC_XILINX_PL_SND_CARD=y\n# CONFIG_SND_SOC_XTFPGA_I2S is not set\nCONFIG_SND_SOC_I2C_AND_SPI=y\n\n#\n# CODEC drivers\n#\n# CONFIG_SND_SOC_AC97_CODEC is not set\nCONFIG_SND_SOC_AD1836=y\nCONFIG_SND_SOC_AD193X=y\nCONFIG_SND_SOC_AD193X_SPI=y\nCONFIG_SND_SOC_AD193X_I2C=y\n# CONFIG_SND_SOC_AD1980 is not set\nCONFIG_SND_SOC_AD73311=y\nCONFIG_SND_SOC_ADAU_UTILS=y\nCONFIG_SND_SOC_ADAU1372=y\nCONFIG_SND_SOC_ADAU1372_I2C=y\nCONFIG_SND_SOC_ADAU1372_SPI=y\nCONFIG_SND_SOC_ADAU1373=y\nCONFIG_SND_SOC_ADAU1701=y\nCONFIG_SND_SOC_ADAU17X1=y\nCONFIG_SND_SOC_ADAU1761=y\nCONFIG_SND_SOC_ADAU1761_I2C=y\nCONFIG_SND_SOC_ADAU1761_SPI=y\nCONFIG_SND_SOC_ADAU1781=y\nCONFIG_SND_SOC_ADAU1781_I2C=y\nCONFIG_SND_SOC_ADAU1781_SPI=y\nCONFIG_SND_SOC_ADAU1977=y\nCONFIG_SND_SOC_ADAU1977_SPI=y\nCONFIG_SND_SOC_ADAU1977_I2C=y\nCONFIG_SND_SOC_ADAU7002=y\nCONFIG_SND_SOC_ADAU7118=y\nCONFIG_SND_SOC_ADAU7118_HW=y\nCONFIG_SND_SOC_ADAU7118_I2C=y\nCONFIG_SND_SOC_ADAV80X=y\nCONFIG_SND_SOC_ADAV801=y\nCONFIG_SND_SOC_ADAV803=y\n# CONFIG_SND_SOC_AK4104 is not set\n# CONFIG_SND_SOC_AK4118 is not set\n# CONFIG_SND_SOC_AK4458 is not set\n# CONFIG_SND_SOC_AK4554 is not set\n# CONFIG_SND_SOC_AK4613 is not set\n# CONFIG_SND_SOC_AK4642 is not set\n# CONFIG_SND_SOC_AK5386 is not set\n# CONFIG_SND_SOC_AK5558 is not set\n# CONFIG_SND_SOC_ALC5623 is not set\n# CONFIG_SND_SOC_BD28623 is not set\n# CONFIG_SND_SOC_BT_SCO is not set\n# CONFIG_SND_SOC_CS35L32 is not set\n# CONFIG_SND_SOC_CS35L33 is not set\n# CONFIG_SND_SOC_CS35L34 is not set\n# CONFIG_SND_SOC_CS35L35 is not set\n# CONFIG_SND_SOC_CS35L36 is not set\n# CONFIG_SND_SOC_CS42L42 is not set\n# CONFIG_SND_SOC_CS42L51_I2C is not set\n# CONFIG_SND_SOC_CS42L52 is not set\n# CONFIG_SND_SOC_CS42L56 is not set\n# CONFIG_SND_SOC_CS42L73 is not set\n# CONFIG_SND_SOC_CS4234 is not set\n# CONFIG_SND_SOC_CS4265 is not set\n# CONFIG_SND_SOC_CS4270 is not set\n# CONFIG_SND_SOC_CS4271_I2C is not set\n# CONFIG_SND_SOC_CS4271_SPI is not set\n# CONFIG_SND_SOC_CS42XX8_I2C is not set\n# CONFIG_SND_SOC_CS43130 is not set\n# CONFIG_SND_SOC_CS4341 is not set\n# CONFIG_SND_SOC_CS4349 is not set\n# CONFIG_SND_SOC_CS53L30 is not set\n# CONFIG_SND_SOC_CX2072X is not set\n# CONFIG_SND_SOC_DA7213 is not set\n# CONFIG_SND_SOC_DMIC is not set\nCONFIG_SND_SOC_HDMI_CODEC=y\n# CONFIG_SND_SOC_ES7134 is not set\n# CONFIG_SND_SOC_ES7241 is not set\n# CONFIG_SND_SOC_ES8316 is not set\n# CONFIG_SND_SOC_ES8328_I2C is not set\n# CONFIG_SND_SOC_ES8328_SPI is not set\n# CONFIG_SND_SOC_GTM601 is not set\n# CONFIG_SND_SOC_ICS43432 is not set\n# CONFIG_SND_SOC_INNO_RK3036 is not set\n# CONFIG_SND_SOC_MAX98088 is not set\n# CONFIG_SND_SOC_MAX98357A is not set\n# CONFIG_SND_SOC_MAX98504 is not set\n# CONFIG_SND_SOC_MAX9867 is not set\n# CONFIG_SND_SOC_MAX98927 is not set\n# CONFIG_SND_SOC_MAX98373_I2C is not set\n# CONFIG_SND_SOC_MAX98390 is not set\n# CONFIG_SND_SOC_MAX9860 is not set\n# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set\n# CONFIG_SND_SOC_PCM1681 is not set\n# CONFIG_SND_SOC_PCM1789_I2C is not set\n# CONFIG_SND_SOC_PCM179X_I2C is not set\n# CONFIG_SND_SOC_PCM179X_SPI is not set\n# CONFIG_SND_SOC_PCM186X_I2C is not set\n# CONFIG_SND_SOC_PCM186X_SPI is not set\n# CONFIG_SND_SOC_PCM3060_I2C is not set\n# CONFIG_SND_SOC_PCM3060_SPI is not set\n# CONFIG_SND_SOC_PCM3168A_I2C is not set\n# CONFIG_SND_SOC_PCM3168A_SPI is not set\n# CONFIG_SND_SOC_PCM5102A is not set\n# CONFIG_SND_SOC_PCM512x_I2C is not set\n# CONFIG_SND_SOC_PCM512x_SPI is not set\n# CONFIG_SND_SOC_RK3328 is not set\n# CONFIG_SND_SOC_RT5616 is not set\n# CONFIG_SND_SOC_RT5631 is not set\n# CONFIG_SND_SOC_RT5640 is not set\n# CONFIG_SND_SOC_RT5659 is not set\n# CONFIG_SND_SOC_SGTL5000 is not set\nCONFIG_SND_SOC_SIGMADSP=y\nCONFIG_SND_SOC_SIGMADSP_I2C=y\nCONFIG_SND_SOC_SIGMADSP_REGMAP=y\n# CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set\n# CONFIG_SND_SOC_SIMPLE_MUX is not set\n# CONFIG_SND_SOC_SPDIF is not set\nCONFIG_SND_SOC_SSM2305=y\nCONFIG_SND_SOC_SSM2518=y\nCONFIG_SND_SOC_SSM2602=y\nCONFIG_SND_SOC_SSM2602_SPI=y\nCONFIG_SND_SOC_SSM2602_I2C=y\nCONFIG_SND_SOC_SSM4567=y\n# CONFIG_SND_SOC_STA32X is not set\n# CONFIG_SND_SOC_STA350 is not set\n# CONFIG_SND_SOC_STI_SAS is not set\n# CONFIG_SND_SOC_TAS2552 is not set\n# CONFIG_SND_SOC_TAS2562 is not set\n# CONFIG_SND_SOC_TAS2764 is not set\n# CONFIG_SND_SOC_TAS2770 is not set\n# CONFIG_SND_SOC_TAS5086 is not set\n# CONFIG_SND_SOC_TAS571X is not set\n# CONFIG_SND_SOC_TAS5720 is not set\n# CONFIG_SND_SOC_TAS6424 is not set\n# CONFIG_SND_SOC_TDA7419 is not set\n# CONFIG_SND_SOC_TFA9879 is not set\n# CONFIG_SND_SOC_TFA989X is not set\n# CONFIG_SND_SOC_TLV320AIC23_I2C is not set\n# CONFIG_SND_SOC_TLV320AIC23_SPI is not set\n# CONFIG_SND_SOC_TLV320AIC31XX is not set\n# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set\n# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set\n# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set\n# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set\n# CONFIG_SND_SOC_TLV320ADCX140 is not set\nCONFIG_SND_SOC_TS3A227E=y\n# CONFIG_SND_SOC_TSCS42XX is not set\n# CONFIG_SND_SOC_TSCS454 is not set\n# CONFIG_SND_SOC_UDA1334 is not set\n# CONFIG_SND_SOC_WM8510 is not set\n# CONFIG_SND_SOC_WM8523 is not set\n# CONFIG_SND_SOC_WM8524 is not set\n# CONFIG_SND_SOC_WM8580 is not set\n# CONFIG_SND_SOC_WM8711 is not set\n# CONFIG_SND_SOC_WM8728 is not set\n# CONFIG_SND_SOC_WM8731 is not set\n# CONFIG_SND_SOC_WM8737 is not set\n# CONFIG_SND_SOC_WM8741 is not set\n# CONFIG_SND_SOC_WM8750 is not set\n# CONFIG_SND_SOC_WM8753 is not set\n# CONFIG_SND_SOC_WM8770 is not set\n# CONFIG_SND_SOC_WM8776 is not set\n# CONFIG_SND_SOC_WM8782 is not set\n# CONFIG_SND_SOC_WM8804_I2C is not set\n# CONFIG_SND_SOC_WM8804_SPI is not set\n# CONFIG_SND_SOC_WM8903 is not set\n# CONFIG_SND_SOC_WM8904 is not set\n# CONFIG_SND_SOC_WM8960 is not set\n# CONFIG_SND_SOC_WM8962 is not set\n# CONFIG_SND_SOC_WM8974 is not set\n# CONFIG_SND_SOC_WM8978 is not set\n# CONFIG_SND_SOC_WM8985 is not set\n# CONFIG_SND_SOC_ZL38060 is not set\n# CONFIG_SND_SOC_MAX9759 is not set\n# CONFIG_SND_SOC_MT6351 is not set\n# CONFIG_SND_SOC_MT6358 is not set\n# CONFIG_SND_SOC_MT6660 is not set\n# CONFIG_SND_SOC_NAU8315 is not set\n# CONFIG_SND_SOC_NAU8540 is not set\n# CONFIG_SND_SOC_NAU8810 is not set\n# CONFIG_SND_SOC_NAU8822 is not set\n# CONFIG_SND_SOC_NAU8824 is not set\n# CONFIG_SND_SOC_TPA6130A2 is not set\n# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set\n# CONFIG_SND_SOC_LPASS_VA_MACRO is not set\n# CONFIG_SND_SOC_LPASS_RX_MACRO is not set\n# CONFIG_SND_SOC_LPASS_TX_MACRO is not set\n# end of CODEC drivers\n\nCONFIG_SND_SIMPLE_CARD_UTILS=y\nCONFIG_SND_SIMPLE_CARD=y\n# CONFIG_SND_AUDIO_GRAPH_CARD is not set\n# CONFIG_SND_VIRTIO is not set\n\n#\n# HID support\n#\nCONFIG_HID=y\n# CONFIG_HID_BATTERY_STRENGTH is not set\n# CONFIG_HIDRAW is not set\n# CONFIG_UHID is not set\nCONFIG_HID_GENERIC=y\n\n#\n# Special HID drivers\n#\n# CONFIG_HID_A4TECH is not set\n# CONFIG_HID_ACCUTOUCH is not set\n# CONFIG_HID_ACRUX is not set\n# CONFIG_HID_APPLE is not set\n# CONFIG_HID_APPLEIR is not set\n# CONFIG_HID_ASUS is not set\n# CONFIG_HID_AUREAL is not set\n# CONFIG_HID_BELKIN is not set\n# CONFIG_HID_BETOP_FF is not set\n# CONFIG_HID_BIGBEN_FF is not set\n# CONFIG_HID_CHERRY is not set\n# CONFIG_HID_CHICONY is not set\n# CONFIG_HID_CORSAIR is not set\n# CONFIG_HID_COUGAR is not set\n# CONFIG_HID_MACALLY is not set\n# CONFIG_HID_PRODIKEYS is not set\n# CONFIG_HID_CMEDIA is not set\n# CONFIG_HID_CREATIVE_SB0540 is not set\n# CONFIG_HID_CYPRESS is not set\n# CONFIG_HID_DRAGONRISE is not set\n# CONFIG_HID_EMS_FF is not set\n# CONFIG_HID_ELAN is not set\n# CONFIG_HID_ELECOM is not set\n# CONFIG_HID_ELO is not set\n# CONFIG_HID_EZKEY is not set\n# CONFIG_HID_GEMBIRD is not set\n# CONFIG_HID_GFRM is not set\n# CONFIG_HID_GLORIOUS is not set\n# CONFIG_HID_HOLTEK is not set\n# CONFIG_HID_VIVALDI is not set\n# CONFIG_HID_GT683R is not set\n# CONFIG_HID_KEYTOUCH is not set\n# CONFIG_HID_KYE is not set\n# CONFIG_HID_UCLOGIC is not set\n# CONFIG_HID_WALTOP is not set\n# CONFIG_HID_VIEWSONIC is not set\n# CONFIG_HID_GYRATION is not set\n# CONFIG_HID_ICADE is not set\n# CONFIG_HID_ITE is not set\n# CONFIG_HID_JABRA is not set\n# CONFIG_HID_TWINHAN is not set\n# CONFIG_HID_KENSINGTON is not set\n# CONFIG_HID_LCPOWER is not set\n# CONFIG_HID_LED is not set\n# CONFIG_HID_LENOVO is not set\n# CONFIG_HID_LOGITECH is not set\n# CONFIG_HID_MAGICMOUSE is not set\n# CONFIG_HID_MALTRON is not set\n# CONFIG_HID_MAYFLASH is not set\n# CONFIG_HID_REDRAGON is not set\n# CONFIG_HID_MICROSOFT is not set\n# CONFIG_HID_MONTEREY is not set\n# CONFIG_HID_MULTITOUCH is not set\n# CONFIG_HID_NTI is not set\n# CONFIG_HID_NTRIG is not set\n# CONFIG_HID_ORTEK is not set\n# CONFIG_HID_PANTHERLORD is not set\n# CONFIG_HID_PENMOUNT is not set\n# CONFIG_HID_PETALYNX is not set\n# CONFIG_HID_PICOLCD is not set\n# CONFIG_HID_PLANTRONICS is not set\n# CONFIG_HID_PLAYSTATION is not set\n# CONFIG_HID_PRIMAX is not set\n# CONFIG_HID_RETRODE is not set\n# CONFIG_HID_ROCCAT is not set\n# CONFIG_HID_SAITEK is not set\n# CONFIG_HID_SAMSUNG is not set\n# CONFIG_HID_SEMITEK is not set\n# CONFIG_HID_SONY is not set\n# CONFIG_HID_SPEEDLINK is not set\n# CONFIG_HID_STEAM is not set\n# CONFIG_HID_STEELSERIES is not set\n# CONFIG_HID_SUNPLUS is not set\n# CONFIG_HID_RMI is not set\n# CONFIG_HID_GREENASIA is not set\n# CONFIG_HID_SMARTJOYPLUS is not set\n# CONFIG_HID_TIVO is not set\n# CONFIG_HID_TOPSEED is not set\n# CONFIG_HID_THINGM is not set\n# CONFIG_HID_THRUSTMASTER is not set\n# CONFIG_HID_UDRAW_PS3 is not set\n# CONFIG_HID_WACOM is not set\n# CONFIG_HID_WIIMOTE is not set\n# CONFIG_HID_XINMO is not set\n# CONFIG_HID_ZEROPLUS is not set\n# CONFIG_HID_ZYDACRON is not set\n# CONFIG_HID_SENSOR_HUB is not set\n# CONFIG_HID_ALPS is not set\n# CONFIG_HID_MCP2221 is not set\n# end of Special HID drivers\n\n#\n# USB HID support\n#\nCONFIG_USB_HID=y\n# CONFIG_HID_PID is not set\nCONFIG_USB_HIDDEV=y\n# end of USB HID support\n\n#\n# I2C HID support\n#\n# CONFIG_I2C_HID_OF is not set\n# CONFIG_I2C_HID_OF_GOODIX is not set\n# end of I2C HID support\n# end of HID support\n\nCONFIG_USB_OHCI_LITTLE_ENDIAN=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USB_COMMON=y\n# CONFIG_USB_LED_TRIG is not set\nCONFIG_USB_ULPI_BUS=y\n# CONFIG_USB_CONN_GPIO is not set\nCONFIG_USB_ARCH_HAS_HCD=y\nCONFIG_USB=y\nCONFIG_USB_PCI=y\nCONFIG_USB_ANNOUNCE_NEW_DEVICES=y\n\n#\n# Miscellaneous USB options\n#\nCONFIG_USB_DEFAULT_PERSIST=y\n# CONFIG_USB_FEW_INIT_RETRIES is not set\n# CONFIG_USB_DYNAMIC_MINORS is not set\nCONFIG_USB_OTG=y\n# CONFIG_USB_OTG_PRODUCTLIST is not set\n# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set\nCONFIG_USB_OTG_FSM=y\n# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set\nCONFIG_USB_AUTOSUSPEND_DELAY=2\n# CONFIG_USB_MON is not set\n\n#\n# USB Host Controller Drivers\n#\n# CONFIG_USB_C67X00_HCD is not set\nCONFIG_USB_XHCI_HCD=y\n# CONFIG_USB_XHCI_DBGCAP is not set\nCONFIG_USB_XHCI_PCI=y\n# CONFIG_USB_XHCI_PCI_RENESAS is not set\nCONFIG_USB_XHCI_PLATFORM=y\nCONFIG_USB_EHCI_HCD=y\nCONFIG_USB_EHCI_ROOT_HUB_TT=y\nCONFIG_USB_EHCI_TT_NEWSCHED=y\nCONFIG_USB_EHCI_PCI=y\n# CONFIG_USB_EHCI_FSL is not set\n# CONFIG_USB_EHCI_HCD_PLATFORM is not set\n# CONFIG_USB_OXU210HP_HCD is not set\n# CONFIG_USB_ISP116X_HCD is not set\n# CONFIG_USB_FOTG210_HCD is not set\n# CONFIG_USB_MAX3421_HCD is not set\n# CONFIG_USB_OHCI_HCD is not set\n# CONFIG_USB_UHCI_HCD is not set\n# CONFIG_USB_SL811_HCD is not set\n# CONFIG_USB_R8A66597_HCD is not set\n# CONFIG_USB_HCD_TEST_MODE is not set\n\n#\n# USB Device Class drivers\n#\n# CONFIG_USB_ACM is not set\n# CONFIG_USB_PRINTER is not set\n# CONFIG_USB_WDM is not set\n# CONFIG_USB_TMC is not set\n\n#\n# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may\n#\n\n#\n# also be needed; see USB_STORAGE Help for more info\n#\nCONFIG_USB_STORAGE=y\n# CONFIG_USB_STORAGE_DEBUG is not set\n# CONFIG_USB_STORAGE_REALTEK is not set\n# CONFIG_USB_STORAGE_DATAFAB is not set\n# CONFIG_USB_STORAGE_FREECOM is not set\n# CONFIG_USB_STORAGE_ISD200 is not set\n# CONFIG_USB_STORAGE_USBAT is not set\n# CONFIG_USB_STORAGE_SDDR09 is not set\n# CONFIG_USB_STORAGE_SDDR55 is not set\n# CONFIG_USB_STORAGE_JUMPSHOT is not set\n# CONFIG_USB_STORAGE_ALAUDA is not set\n# CONFIG_USB_STORAGE_ONETOUCH is not set\n# CONFIG_USB_STORAGE_KARMA is not set\n# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set\n# CONFIG_USB_STORAGE_ENE_UB6250 is not set\nCONFIG_USB_UAS=y\n\n#\n# USB Imaging devices\n#\n# CONFIG_USB_MDC800 is not set\n# CONFIG_USB_MICROTEK is not set\n# CONFIG_USBIP_CORE is not set\n# CONFIG_USB_CDNS_SUPPORT is not set\n# CONFIG_USB_MUSB_HDRC is not set\nCONFIG_USB_DWC3=y\nCONFIG_USB_DWC3_ULPI=y\n# CONFIG_USB_DWC3_HOST is not set\n# CONFIG_USB_DWC3_GADGET is not set\nCONFIG_USB_DWC3_DUAL_ROLE=y\n# CONFIG_USB_DWC3_OTG is not set\n\n#\n# Platform Glue Driver Support\n#\nCONFIG_USB_DWC3_HAPS=y\nCONFIG_USB_DWC3_OF_SIMPLE=y\nCONFIG_USB_DWC3_XILINX=y\nCONFIG_USB_DWC2=y\n# CONFIG_USB_DWC2_HOST is not set\n\n#\n# Gadget/Dual-role mode requires USB Gadget support to be enabled\n#\n# CONFIG_USB_DWC2_PERIPHERAL is not set\nCONFIG_USB_DWC2_DUAL_ROLE=y\n# CONFIG_USB_DWC2_PCI is not set\n# CONFIG_USB_DWC2_DEBUG is not set\n# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set\nCONFIG_USB_CHIPIDEA=y\nCONFIG_USB_CHIPIDEA_UDC=y\nCONFIG_USB_CHIPIDEA_HOST=y\nCONFIG_USB_CHIPIDEA_PCI=y\nCONFIG_USB_CHIPIDEA_MSM=y\nCONFIG_USB_CHIPIDEA_IMX=y\nCONFIG_USB_CHIPIDEA_GENERIC=y\nCONFIG_USB_CHIPIDEA_TEGRA=y\n# CONFIG_USB_ISP1760 is not set\n\n#\n# USB port drivers\n#\nCONFIG_USB_SERIAL=y\n# CONFIG_USB_SERIAL_CONSOLE is not set\nCONFIG_USB_SERIAL_GENERIC=y\n# CONFIG_USB_SERIAL_SIMPLE is not set\n# CONFIG_USB_SERIAL_AIRCABLE is not set\n# CONFIG_USB_SERIAL_ARK3116 is not set\n# CONFIG_USB_SERIAL_BELKIN is not set\n# CONFIG_USB_SERIAL_CH341 is not set\n# CONFIG_USB_SERIAL_WHITEHEAT is not set\n# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set\n# CONFIG_USB_SERIAL_CP210X is not set\n# CONFIG_USB_SERIAL_CYPRESS_M8 is not set\n# CONFIG_USB_SERIAL_EMPEG is not set\nCONFIG_USB_SERIAL_FTDI_SIO=y\n# CONFIG_USB_SERIAL_VISOR is not set\n# CONFIG_USB_SERIAL_IPAQ is not set\n# CONFIG_USB_SERIAL_IR is not set\n# CONFIG_USB_SERIAL_EDGEPORT is not set\n# CONFIG_USB_SERIAL_EDGEPORT_TI is not set\n# CONFIG_USB_SERIAL_F81232 is not set\n# CONFIG_USB_SERIAL_F8153X is not set\n# CONFIG_USB_SERIAL_GARMIN is not set\n# CONFIG_USB_SERIAL_IPW is not set\n# CONFIG_USB_SERIAL_IUU is not set\n# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set\n# CONFIG_USB_SERIAL_KEYSPAN is not set\n# CONFIG_USB_SERIAL_KLSI is not set\n# CONFIG_USB_SERIAL_KOBIL_SCT is not set\n# CONFIG_USB_SERIAL_MCT_U232 is not set\n# CONFIG_USB_SERIAL_METRO is not set\n# CONFIG_USB_SERIAL_MOS7720 is not set\n# CONFIG_USB_SERIAL_MOS7840 is not set\n# CONFIG_USB_SERIAL_MXUPORT is not set\n# CONFIG_USB_SERIAL_NAVMAN is not set\n# CONFIG_USB_SERIAL_PL2303 is not set\n# CONFIG_USB_SERIAL_OTI6858 is not set\n# CONFIG_USB_SERIAL_QCAUX is not set\n# CONFIG_USB_SERIAL_QUALCOMM is not set\n# CONFIG_USB_SERIAL_SPCP8X5 is not set\n# CONFIG_USB_SERIAL_SAFE is not set\n# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set\n# CONFIG_USB_SERIAL_SYMBOL is not set\n# CONFIG_USB_SERIAL_TI is not set\n# CONFIG_USB_SERIAL_CYBERJACK is not set\n# CONFIG_USB_SERIAL_OPTION is not set\n# CONFIG_USB_SERIAL_OMNINET is not set\n# CONFIG_USB_SERIAL_OPTICON is not set\n# CONFIG_USB_SERIAL_XSENS_MT is not set\n# CONFIG_USB_SERIAL_WISHBONE is not set\n# CONFIG_USB_SERIAL_SSU100 is not set\n# CONFIG_USB_SERIAL_QT2 is not set\nCONFIG_USB_SERIAL_UPD78F0730=y\n# CONFIG_USB_SERIAL_XR is not set\n# CONFIG_USB_SERIAL_DEBUG is not set\n\n#\n# USB Miscellaneous drivers\n#\n# CONFIG_USB_EMI62 is not set\n# CONFIG_USB_EMI26 is not set\n# CONFIG_USB_ADUTUX is not set\n# CONFIG_USB_SEVSEG is not set\n# CONFIG_USB_LEGOTOWER is not set\n# CONFIG_USB_LCD is not set\n# CONFIG_USB_CYPRESS_CY7C63 is not set\n# CONFIG_USB_CYTHERM is not set\n# CONFIG_USB_IDMOUSE is not set\n# CONFIG_USB_FTDI_ELAN is not set\n# CONFIG_USB_APPLEDISPLAY is not set\n# CONFIG_APPLE_MFI_FASTCHARGE is not set\n# CONFIG_USB_SISUSBVGA is not set\n# CONFIG_USB_LD is not set\n# CONFIG_USB_TRANCEVIBRATOR is not set\n# CONFIG_USB_IOWARRIOR is not set\n# CONFIG_USB_TEST is not set\n# CONFIG_USB_EHSET_TEST_FIXTURE is not set\n# CONFIG_USB_ISIGHTFW is not set\n# CONFIG_USB_YUREX is not set\n# CONFIG_USB_EZUSB_FX2 is not set\n# CONFIG_USB_HUB_USB251XB is not set\n# CONFIG_USB_USB2244 is not set\n# CONFIG_USB_USB5744 is not set\n# CONFIG_USB_HSIC_USB3503 is not set\n# CONFIG_USB_HSIC_USB4604 is not set\n# CONFIG_USB_LINK_LAYER_TEST is not set\n\n#\n# USB Physical Layer drivers\n#\nCONFIG_USB_PHY=y\nCONFIG_NOP_USB_XCEIV=y\n# CONFIG_USB_GPIO_VBUS is not set\n# CONFIG_USB_ISP1301 is not set\nCONFIG_USB_ULPI=y\nCONFIG_USB_ULPI_VIEWPORT=y\n# end of USB Physical Layer drivers\n\nCONFIG_USB_GADGET=y\n# CONFIG_USB_GADGET_DEBUG is not set\n# CONFIG_USB_GADGET_DEBUG_FILES is not set\n# CONFIG_USB_GADGET_DEBUG_FS is not set\nCONFIG_USB_GADGET_VBUS_DRAW=2\nCONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2\n# CONFIG_U_SERIAL_CONSOLE is not set\n\n#\n# USB Peripheral Controller\n#\n# CONFIG_USB_FOTG210_UDC is not set\n# CONFIG_USB_GR_UDC is not set\n# CONFIG_USB_R8A66597 is not set\n# CONFIG_USB_PXA27X is not set\n# CONFIG_USB_MV_UDC is not set\n# CONFIG_USB_MV_U3D is not set\n# CONFIG_USB_SNP_UDC_PLAT is not set\n# CONFIG_USB_M66592 is not set\n# CONFIG_USB_BDC_UDC is not set\n# CONFIG_USB_AMD5536UDC is not set\n# CONFIG_USB_NET2272 is not set\n# CONFIG_USB_NET2280 is not set\n# CONFIG_USB_GOKU is not set\n# CONFIG_USB_EG20T is not set\nCONFIG_USB_GADGET_XILINX=y\n# CONFIG_USB_MAX3420_UDC is not set\n# CONFIG_USB_DUMMY_HCD is not set\n# end of USB Peripheral Controller\n\nCONFIG_USB_LIBCOMPOSITE=y\nCONFIG_USB_F_ACM=y\nCONFIG_USB_U_SERIAL=y\nCONFIG_USB_U_ETHER=y\nCONFIG_USB_F_SERIAL=y\nCONFIG_USB_F_NCM=y\nCONFIG_USB_F_ECM=y\nCONFIG_USB_F_EEM=y\nCONFIG_USB_F_SUBSET=y\nCONFIG_USB_F_RNDIS=y\nCONFIG_USB_F_MASS_STORAGE=y\nCONFIG_USB_F_FS=y\nCONFIG_USB_CONFIGFS=y\nCONFIG_USB_CONFIGFS_SERIAL=y\nCONFIG_USB_CONFIGFS_ACM=y\n# CONFIG_USB_CONFIGFS_OBEX is not set\nCONFIG_USB_CONFIGFS_NCM=y\nCONFIG_USB_CONFIGFS_ECM=y\nCONFIG_USB_CONFIGFS_ECM_SUBSET=y\nCONFIG_USB_CONFIGFS_RNDIS=y\nCONFIG_USB_CONFIGFS_EEM=y\nCONFIG_USB_CONFIGFS_MASS_STORAGE=y\n# CONFIG_USB_CONFIGFS_F_LB_SS is not set\nCONFIG_USB_CONFIGFS_F_FS=y\n# CONFIG_USB_CONFIGFS_F_UAC1 is not set\n# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set\n# CONFIG_USB_CONFIGFS_F_UAC2 is not set\n# CONFIG_USB_CONFIGFS_F_MIDI is not set\n# CONFIG_USB_CONFIGFS_F_HID is not set\n# CONFIG_USB_CONFIGFS_F_UVC is not set\n# CONFIG_USB_CONFIGFS_F_PRINTER is not set\n\n#\n# USB Gadget precomposed configurations\n#\n# CONFIG_USB_ZERO is not set\n# CONFIG_USB_AUDIO is not set\n# CONFIG_USB_ETH is not set\n# CONFIG_USB_G_NCM is not set\n# CONFIG_USB_GADGETFS is not set\n# CONFIG_USB_FUNCTIONFS is not set\n# CONFIG_USB_MASS_STORAGE is not set\n# CONFIG_USB_G_SERIAL is not set\n# CONFIG_USB_MIDI_GADGET is not set\n# CONFIG_USB_G_PRINTER is not set\n# CONFIG_USB_CDC_COMPOSITE is not set\n# CONFIG_USB_G_ACM_MS is not set\n# CONFIG_USB_G_MULTI is not set\n# CONFIG_USB_G_HID is not set\n# CONFIG_USB_G_DBGP is not set\n# CONFIG_USB_G_WEBCAM is not set\n# CONFIG_USB_RAW_GADGET is not set\n# end of USB Gadget precomposed configurations\n\nCONFIG_TYPEC=y\n# CONFIG_TYPEC_TCPM is not set\n# CONFIG_TYPEC_UCSI is not set\nCONFIG_TYPEC_TPS6598X=y\n# CONFIG_TYPEC_HD3SS3220 is not set\n# CONFIG_TYPEC_STUSB160X is not set\n\n#\n# USB Type-C Multiplexer/DeMultiplexer Switch support\n#\n# CONFIG_TYPEC_MUX_PI3USB30532 is not set\n# end of USB Type-C Multiplexer/DeMultiplexer Switch support\n\n#\n# USB Type-C Alternate Mode drivers\n#\n# CONFIG_TYPEC_DP_ALTMODE is not set\n# end of USB Type-C Alternate Mode drivers\n\nCONFIG_USB_ROLE_SWITCH=y\nCONFIG_MMC=y\nCONFIG_PWRSEQ_EMMC=y\n# CONFIG_PWRSEQ_SD8787 is not set\nCONFIG_PWRSEQ_SIMPLE=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_BLOCK_MINORS=8\n# CONFIG_SDIO_UART is not set\n# CONFIG_MMC_TEST is not set\n\n#\n# MMC/SD/SDIO Host Controller Drivers\n#\n# CONFIG_MMC_DEBUG is not set\n# CONFIG_MMC_ARMMMCI is not set\nCONFIG_MMC_SDHCI=y\n# CONFIG_MMC_SDHCI_PCI is not set\nCONFIG_MMC_SDHCI_PLTFM=y\nCONFIG_MMC_SDHCI_OF_ARASAN=y\n# CONFIG_MMC_SDHCI_OF_ASPEED is not set\n# CONFIG_MMC_SDHCI_OF_AT91 is not set\n# CONFIG_MMC_SDHCI_OF_DWCMSHC is not set\n# CONFIG_MMC_SDHCI_CADENCE is not set\n# CONFIG_MMC_SDHCI_F_SDH30 is not set\n# CONFIG_MMC_SDHCI_MILBEAUT is not set\n# CONFIG_MMC_TIFM_SD is not set\n# CONFIG_MMC_SPI is not set\n# CONFIG_MMC_CB710 is not set\n# CONFIG_MMC_VIA_SDMMC is not set\n# CONFIG_MMC_DW is not set\n# CONFIG_MMC_VUB300 is not set\n# CONFIG_MMC_USHC is not set\n# CONFIG_MMC_USDHI6ROL0 is not set\nCONFIG_MMC_CQHCI=y\n# CONFIG_MMC_HSQ is not set\n# CONFIG_MMC_TOSHIBA_PCI is not set\n# CONFIG_MMC_MTK is not set\n# CONFIG_MMC_SDHCI_XENON is not set\n# CONFIG_MMC_SDHCI_OMAP is not set\n# CONFIG_MMC_SDHCI_AM654 is not set\n# CONFIG_MEMSTICK is not set\nCONFIG_NEW_LEDS=y\nCONFIG_LEDS_CLASS=y\nCONFIG_LEDS_CLASS_FLASH=y\n# CONFIG_LEDS_CLASS_MULTICOLOR is not set\nCONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y\n\n#\n# LED drivers\n#\n# CONFIG_LEDS_AN30259A is not set\n# CONFIG_LEDS_AW2013 is not set\n# CONFIG_LEDS_BCM6328 is not set\n# CONFIG_LEDS_BCM6358 is not set\n# CONFIG_LEDS_CR0014114 is not set\n# CONFIG_LEDS_EL15203000 is not set\n# CONFIG_LEDS_LM3530 is not set\n# CONFIG_LEDS_LM3532 is not set\n# CONFIG_LEDS_LM3642 is not set\n# CONFIG_LEDS_LM3692X is not set\n# CONFIG_LEDS_PCA9532 is not set\nCONFIG_LEDS_GPIO=y\n# CONFIG_LEDS_LP3944 is not set\n# CONFIG_LEDS_LP3952 is not set\n# CONFIG_LEDS_LP50XX is not set\n# CONFIG_LEDS_LP55XX_COMMON is not set\n# CONFIG_LEDS_LP8860 is not set\n# CONFIG_LEDS_PCA955X is not set\n# CONFIG_LEDS_PCA963X is not set\n# CONFIG_LEDS_DAC124S085 is not set\n# CONFIG_LEDS_PWM is not set\n# CONFIG_LEDS_REGULATOR is not set\n# CONFIG_LEDS_BD2802 is not set\n# CONFIG_LEDS_LT3593 is not set\nCONFIG_LEDS_ADP5520=y\n# CONFIG_LEDS_TCA6507 is not set\n# CONFIG_LEDS_TLC591XX is not set\n# CONFIG_LEDS_LM355x is not set\n# CONFIG_LEDS_IS31FL319X is not set\n# CONFIG_LEDS_IS31FL32XX is not set\n\n#\n# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)\n#\n# CONFIG_LEDS_BLINKM is not set\n# CONFIG_LEDS_SYSCON is not set\n# CONFIG_LEDS_MLXREG is not set\n# CONFIG_LEDS_USER is not set\n# CONFIG_LEDS_SPI_BYTE is not set\n# CONFIG_LEDS_TI_LMU_COMMON is not set\n\n#\n# Flash and Torch LED drivers\n#\n# CONFIG_LEDS_AAT1290 is not set\nCONFIG_LEDS_AS3645A=y\n# CONFIG_LEDS_KTD2692 is not set\n# CONFIG_LEDS_LM3601X is not set\n# CONFIG_LEDS_RT4505 is not set\n# CONFIG_LEDS_RT8515 is not set\n# CONFIG_LEDS_SGM3140 is not set\n\n#\n# LED Triggers\n#\nCONFIG_LEDS_TRIGGERS=y\nCONFIG_LEDS_TRIGGER_TIMER=y\nCONFIG_LEDS_TRIGGER_ONESHOT=y\n# CONFIG_LEDS_TRIGGER_DISK is not set\n# CONFIG_LEDS_TRIGGER_MTD is not set\nCONFIG_LEDS_TRIGGER_HEARTBEAT=y\nCONFIG_LEDS_TRIGGER_BACKLIGHT=y\nCONFIG_LEDS_TRIGGER_CPU=y\n# CONFIG_LEDS_TRIGGER_ACTIVITY is not set\nCONFIG_LEDS_TRIGGER_GPIO=y\nCONFIG_LEDS_TRIGGER_DEFAULT_ON=y\n\n#\n# iptables trigger is under Netfilter config (LED target)\n#\nCONFIG_LEDS_TRIGGER_TRANSIENT=y\nCONFIG_LEDS_TRIGGER_CAMERA=y\n# CONFIG_LEDS_TRIGGER_PANIC is not set\n# CONFIG_LEDS_TRIGGER_NETDEV is not set\n# CONFIG_LEDS_TRIGGER_PATTERN is not set\n# CONFIG_LEDS_TRIGGER_AUDIO is not set\n# CONFIG_LEDS_TRIGGER_TTY is not set\n# CONFIG_ACCESSIBILITY is not set\n# CONFIG_INFINIBAND is not set\nCONFIG_EDAC_SUPPORT=y\nCONFIG_EDAC=y\nCONFIG_EDAC_LEGACY_SYSFS=y\n# CONFIG_EDAC_DEBUG is not set\n# CONFIG_EDAC_THUNDERX is not set\nCONFIG_EDAC_SYNOPSYS=y\nCONFIG_EDAC_ZYNQMP_OCM=y\n# CONFIG_EDAC_XGENE is not set\n# CONFIG_EDAC_DMC520 is not set\n# CONFIG_EDAC_XILINX_DDR is not set\n# CONFIG_EDAC_XILINX_XILSEM is not set\nCONFIG_RTC_LIB=y\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_HCTOSYS=y\nCONFIG_RTC_HCTOSYS_DEVICE=\"rtc0\"\nCONFIG_RTC_SYSTOHC=y\nCONFIG_RTC_SYSTOHC_DEVICE=\"rtc0\"\n# CONFIG_RTC_DEBUG is not set\nCONFIG_RTC_NVMEM=y\n\n#\n# RTC interfaces\n#\nCONFIG_RTC_INTF_SYSFS=y\nCONFIG_RTC_INTF_PROC=y\nCONFIG_RTC_INTF_DEV=y\n# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set\n# CONFIG_RTC_DRV_TEST is not set\n\n#\n# I2C RTC drivers\n#\n# CONFIG_RTC_DRV_ABB5ZES3 is not set\n# CONFIG_RTC_DRV_ABEOZ9 is not set\n# CONFIG_RTC_DRV_ABX80X is not set\n# CONFIG_RTC_DRV_DS1307 is not set\n# CONFIG_RTC_DRV_DS1374 is not set\n# CONFIG_RTC_DRV_DS1672 is not set\n# CONFIG_RTC_DRV_HYM8563 is not set\n# CONFIG_RTC_DRV_MAX6900 is not set\n# CONFIG_RTC_DRV_RS5C372 is not set\n# CONFIG_RTC_DRV_ISL1208 is not set\n# CONFIG_RTC_DRV_ISL12022 is not set\n# CONFIG_RTC_DRV_ISL12026 is not set\n# CONFIG_RTC_DRV_X1205 is not set\n# CONFIG_RTC_DRV_PCF8523 is not set\n# CONFIG_RTC_DRV_PCF85063 is not set\n# CONFIG_RTC_DRV_PCF85363 is not set\n# CONFIG_RTC_DRV_PCF8563 is not set\n# CONFIG_RTC_DRV_PCF8583 is not set\n# CONFIG_RTC_DRV_M41T80 is not set\n# CONFIG_RTC_DRV_BQ32K is not set\n# CONFIG_RTC_DRV_S35390A is not set\n# CONFIG_RTC_DRV_FM3130 is not set\n# CONFIG_RTC_DRV_RX8010 is not set\n# CONFIG_RTC_DRV_RX8581 is not set\n# CONFIG_RTC_DRV_RX8025 is not set\n# CONFIG_RTC_DRV_EM3027 is not set\n# CONFIG_RTC_DRV_RV3028 is not set\n# CONFIG_RTC_DRV_RV3032 is not set\n# CONFIG_RTC_DRV_RV8803 is not set\n# CONFIG_RTC_DRV_SD3078 is not set\n\n#\n# SPI RTC drivers\n#\n# CONFIG_RTC_DRV_M41T93 is not set\n# CONFIG_RTC_DRV_M41T94 is not set\n# CONFIG_RTC_DRV_DS1302 is not set\n# CONFIG_RTC_DRV_DS1305 is not set\n# CONFIG_RTC_DRV_DS1343 is not set\n# CONFIG_RTC_DRV_DS1347 is not set\n# CONFIG_RTC_DRV_DS1390 is not set\n# CONFIG_RTC_DRV_MAX6916 is not set\n# CONFIG_RTC_DRV_R9701 is not set\n# CONFIG_RTC_DRV_RX4581 is not set\n# CONFIG_RTC_DRV_RS5C348 is not set\n# CONFIG_RTC_DRV_MAX6902 is not set\n# CONFIG_RTC_DRV_PCF2123 is not set\n# CONFIG_RTC_DRV_MCP795 is not set\nCONFIG_RTC_I2C_AND_SPI=y\n\n#\n# SPI and I2C RTC drivers\n#\n# CONFIG_RTC_DRV_DS3232 is not set\n# CONFIG_RTC_DRV_PCF2127 is not set\n# CONFIG_RTC_DRV_RV3029C2 is not set\n# CONFIG_RTC_DRV_RX6110 is not set\n\n#\n# Platform RTC drivers\n#\n# CONFIG_RTC_DRV_DS1286 is not set\n# CONFIG_RTC_DRV_DS1511 is not set\n# CONFIG_RTC_DRV_DS1553 is not set\n# CONFIG_RTC_DRV_DS1685_FAMILY is not set\n# CONFIG_RTC_DRV_DS1742 is not set\n# CONFIG_RTC_DRV_DS2404 is not set\n# CONFIG_RTC_DRV_EFI is not set\n# CONFIG_RTC_DRV_STK17TA8 is not set\n# CONFIG_RTC_DRV_M48T86 is not set\n# CONFIG_RTC_DRV_M48T35 is not set\n# CONFIG_RTC_DRV_M48T59 is not set\n# CONFIG_RTC_DRV_MSM6242 is not set\n# CONFIG_RTC_DRV_BQ4802 is not set\n# CONFIG_RTC_DRV_RP5C01 is not set\n# CONFIG_RTC_DRV_V3020 is not set\nCONFIG_RTC_DRV_ZYNQMP=y\n\n#\n# on-CPU RTC drivers\n#\n# CONFIG_RTC_DRV_PL030 is not set\n# CONFIG_RTC_DRV_PL031 is not set\n# CONFIG_RTC_DRV_CADENCE is not set\n# CONFIG_RTC_DRV_FTRTC010 is not set\n# CONFIG_RTC_DRV_R7301 is not set\n\n#\n# HID Sensor RTC drivers\n#\n# CONFIG_RTC_DRV_GOLDFISH is not set\nCONFIG_DMADEVICES=y\n# CONFIG_DMADEVICES_DEBUG is not set\n\n#\n# DMA Devices\n#\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_VIRTUAL_CHANNELS=y\nCONFIG_DMA_OF=y\n# CONFIG_ALTERA_MSGDMA is not set\n# CONFIG_AMBA_PL08X is not set\nCONFIG_AXI_DMAC=y\n# CONFIG_BCM_SBA_RAID is not set\n# CONFIG_DW_AXI_DMAC is not set\n# CONFIG_FSL_EDMA is not set\n# CONFIG_FSL_QDMA is not set\n# CONFIG_HISI_DMA is not set\n# CONFIG_INTEL_IDMA64 is not set\n# CONFIG_MV_XOR_V2 is not set\n# CONFIG_PL330_DMA is not set\n# CONFIG_PLX_DMA is not set\nCONFIG_XILINX_DMA=m\nCONFIG_XILINX_ZYNQMP_DMA=y\nCONFIG_XILINX_ZYNQMP_DPDMA=y\nCONFIG_XILINX_FRMBUF=y\n# CONFIG_XILINX_PS_PCIE_DMA is not set\n# CONFIG_QCOM_HIDMA_MGMT is not set\n# CONFIG_QCOM_HIDMA is not set\n# CONFIG_DW_DMAC is not set\n# CONFIG_DW_DMAC_PCI is not set\n# CONFIG_DW_EDMA is not set\n# CONFIG_DW_EDMA_PCIE is not set\n# CONFIG_SF_PDMA is not set\n\n#\n# DMA Clients\n#\n# CONFIG_ASYNC_TX_DMA is not set\nCONFIG_DMATEST=y\nCONFIG_DMA_ENGINE_RAID=y\n# CONFIG_XILINX_DMATEST is not set\n# CONFIG_XILINX_VDMATEST is not set\n\n#\n# DMABUF options\n#\nCONFIG_SYNC_FILE=y\n# CONFIG_SW_SYNC is not set\n# CONFIG_UDMABUF is not set\n# CONFIG_DMABUF_MOVE_NOTIFY is not set\n# CONFIG_DMABUF_DEBUG is not set\n# CONFIG_DMABUF_SELFTESTS is not set\n# CONFIG_DMABUF_HEAPS is not set\n# CONFIG_DMABUF_SYSFS_STATS is not set\n# end of DMABUF options\n\n# CONFIG_AUXDISPLAY is not set\nCONFIG_UIO=y\n# CONFIG_UIO_CIF is not set\nCONFIG_UIO_PDRV_GENIRQ=m\nCONFIG_UIO_DMEM_GENIRQ=m\n# CONFIG_UIO_AEC is not set\n# CONFIG_UIO_SERCOS3 is not set\n# CONFIG_UIO_PCI_GENERIC is not set\n# CONFIG_UIO_NETX is not set\n# CONFIG_UIO_PRUSS is not set\n# CONFIG_UIO_MF624 is not set\nCONFIG_UIO_XILINX_APM=y\n# CONFIG_UIO_XILINX_AI_ENGINE is not set\n# CONFIG_VFIO is not set\n# CONFIG_VIRT_DRIVERS is not set\nCONFIG_VIRTIO=y\nCONFIG_VIRTIO_MENU=y\n# CONFIG_VIRTIO_PCI is not set\n# CONFIG_VIRTIO_BALLOON is not set\n# CONFIG_VIRTIO_INPUT is not set\n# CONFIG_VIRTIO_MMIO is not set\n# CONFIG_VDPA is not set\nCONFIG_VHOST_MENU=y\n# CONFIG_VHOST_NET is not set\n# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set\n\n#\n# Microsoft Hyper-V guest support\n#\n# end of Microsoft Hyper-V guest support\n\n# CONFIG_GREYBUS is not set\n# CONFIG_COMEDI is not set\nCONFIG_STAGING=y\n# CONFIG_PRISM2_USB is not set\n# CONFIG_RTL8192U is not set\n# CONFIG_RTLLIB is not set\n# CONFIG_RTL8723BS is not set\n# CONFIG_R8712U is not set\n# CONFIG_R8188EU is not set\n# CONFIG_RTS5208 is not set\n# CONFIG_VT6655 is not set\n# CONFIG_VT6656 is not set\n\n#\n# IIO staging drivers\n#\n\n#\n# Accelerometers\n#\nCONFIG_ADIS16203=y\nCONFIG_ADIS16240=y\n# end of Accelerometers\n\n#\n# Analog to digital converters\n#\nCONFIG_AD7816=y\nCONFIG_AD7280=y\n# end of Analog to digital converters\n\n#\n# Analog digital bi-direction converters\n#\nCONFIG_ADT7316=y\nCONFIG_ADT7316_SPI=y\nCONFIG_ADT7316_I2C=y\n# end of Analog digital bi-direction converters\n\n#\n# Capacitance to digital converters\n#\nCONFIG_AD7746=y\n# end of Capacitance to digital converters\n\n#\n# Direct Digital Synthesis\n#\nCONFIG_AD9832=y\nCONFIG_AD9834=y\n# end of Direct Digital Synthesis\n\n#\n# Network Analyzer, Impedance Converters\n#\nCONFIG_AD5933=y\n# end of Network Analyzer, Impedance Converters\n\n#\n# Active energy metering IC\n#\nCONFIG_ADE7854=y\nCONFIG_ADE7854_I2C=y\nCONFIG_ADE7854_SPI=y\n# end of Active energy metering IC\n\n#\n# Resolver to digital converters\n#\nCONFIG_AD2S1210=y\n# end of Resolver to digital converters\n# end of IIO staging drivers\n\n# CONFIG_FB_SM750 is not set\n# CONFIG_STAGING_MEDIA is not set\n\n#\n# Android\n#\n# CONFIG_ASHMEM is not set\n# end of Android\n\n# CONFIG_STAGING_BOARD is not set\n# CONFIG_LTE_GDM724X is not set\n# CONFIG_GS_FPGABOOT is not set\n# CONFIG_UNISYSSPAR is not set\n# CONFIG_XILINX_APF is not set\nCONFIG_FB_TFT=y\n# CONFIG_FB_TFT_AGM1264K_FL is not set\n# CONFIG_FB_TFT_BD663474 is not set\n# CONFIG_FB_TFT_HX8340BN is not set\n# CONFIG_FB_TFT_HX8347D is not set\n# CONFIG_FB_TFT_HX8353D is not set\n# CONFIG_FB_TFT_HX8357D is not set\n# CONFIG_FB_TFT_ILI9163 is not set\n# CONFIG_FB_TFT_ILI9320 is not set\n# CONFIG_FB_TFT_ILI9325 is not set\n# CONFIG_FB_TFT_ILI9340 is not set\n# CONFIG_FB_TFT_ILI9341 is not set\n# CONFIG_FB_TFT_ILI9481 is not set\n# CONFIG_FB_TFT_ILI9486 is not set\n# CONFIG_FB_TFT_PCD8544 is not set\n# CONFIG_FB_TFT_RA8875 is not set\n# CONFIG_FB_TFT_S6D02A1 is not set\n# CONFIG_FB_TFT_S6D1121 is not set\nCONFIG_FB_TFT_SEPS525=y\n# CONFIG_FB_TFT_SH1106 is not set\n# CONFIG_FB_TFT_SSD1289 is not set\n# CONFIG_FB_TFT_SSD1305 is not set\n# CONFIG_FB_TFT_SSD1306 is not set\n# CONFIG_FB_TFT_SSD1331 is not set\n# CONFIG_FB_TFT_SSD1351 is not set\n# CONFIG_FB_TFT_ST7735R is not set\n# CONFIG_FB_TFT_ST7789V is not set\n# CONFIG_FB_TFT_TINYLCD is not set\n# CONFIG_FB_TFT_TLS8204 is not set\n# CONFIG_FB_TFT_UC1611 is not set\n# CONFIG_FB_TFT_UC1701 is not set\n# CONFIG_FB_TFT_UPD161704 is not set\n# CONFIG_FB_TFT_WATTEROTT is not set\n# CONFIG_KS7010 is not set\n# CONFIG_PI433 is not set\n# CONFIG_XIL_AXIS_FIFO is not set\n# CONFIG_FIELDBUS_DEV is not set\n# CONFIG_QLGE is not set\n# CONFIG_WFX is not set\nCONFIG_XILINX_FCLK=y\n# CONFIG_XLNX_SYNC is not set\n# CONFIG_XLNX_TSMUX is not set\n# CONFIG_XROE_FRAMER is not set\n# CONFIG_XROE_TRAFFIC_GEN is not set\n# CONFIG_SERIAL_UARTLITE_RS485 is not set\n# CONFIG_XILINX_TSN is not set\n# CONFIG_GOLDFISH is not set\n# CONFIG_CHROME_PLATFORMS is not set\n# CONFIG_MELLANOX_PLATFORM is not set\nCONFIG_HAVE_CLK=y\nCONFIG_HAVE_CLK_PREPARE=y\nCONFIG_COMMON_CLK=y\n\n#\n# Clock driver for ARM Reference designs\n#\n# CONFIG_ICST is not set\n# CONFIG_CLK_SP810 is not set\n# end of Clock driver for ARM Reference designs\n\n# CONFIG_LMK04832 is not set\n# CONFIG_COMMON_CLK_MAX9485 is not set\nCONFIG_COMMON_CLK_SI5341=y\n# CONFIG_COMMON_CLK_SI5351 is not set\nCONFIG_COMMON_CLK_SI514=y\n# CONFIG_COMMON_CLK_SI544 is not set\nCONFIG_COMMON_CLK_SI570=y\nCONFIG_COMMON_CLK_SI5324=y\n# CONFIG_COMMON_CLK_IDT8T49N24X is not set\n# CONFIG_COMMON_CLK_CDCE706 is not set\n# CONFIG_COMMON_CLK_CDCE925 is not set\n# CONFIG_COMMON_CLK_CS2000_CP is not set\nCONFIG_COMMON_CLK_AXI_CLKGEN=y\nCONFIG_COMMON_CLK_ADI=y\n# CONFIG_COMMON_CLK_XGENE is not set\n# CONFIG_COMMON_CLK_PWM is not set\n# CONFIG_COMMON_CLK_VC5 is not set\n# CONFIG_COMMON_CLK_VC7 is not set\n# CONFIG_COMMON_CLK_FIXED_MMIO is not set\nCONFIG_COMMON_CLK_XLNX_CLKWZRD=y\n# CONFIG_COMMON_CLK_XLNX_CLKWZRD_V is not set\n\n#\n# Analog Devices Clock Drivers\n#\nCONFIG_COMMON_CLK_AD9545=y\nCONFIG_COMMON_CLK_AD9545_I2C=y\nCONFIG_COMMON_CLK_AD9545_SPI=y\n# end of Analog Devices Clock Drivers\n\nCONFIG_XILINX_VCU=m\nCONFIG_COMMON_CLK_ZYNQMP=y\n# CONFIG_HWSPINLOCK is not set\n\n#\n# Clock Source drivers\n#\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_ARM_ARCH_TIMER=y\nCONFIG_ARM_ARCH_TIMER_EVTSTREAM=y\nCONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y\nCONFIG_FSL_ERRATUM_A008585=y\nCONFIG_HISILICON_ERRATUM_161010101=y\nCONFIG_ARM64_ERRATUM_858921=y\n# CONFIG_MICROCHIP_PIT64B is not set\n# end of Clock Source drivers\n\nCONFIG_MAILBOX=y\n# CONFIG_ARM_MHU is not set\n# CONFIG_ARM_MHU_V2 is not set\n# CONFIG_PLATFORM_MHU is not set\n# CONFIG_PL320_MBOX is not set\n# CONFIG_ALTERA_MBOX is not set\n# CONFIG_MAILBOX_TEST is not set\nCONFIG_ZYNQMP_IPI_MBOX=y\nCONFIG_IOMMU_IOVA=y\nCONFIG_IOMMU_API=y\nCONFIG_IOMMU_SUPPORT=y\n\n#\n# Generic IOMMU Pagetable Support\n#\nCONFIG_IOMMU_IO_PGTABLE=y\nCONFIG_IOMMU_IO_PGTABLE_LPAE=y\n# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set\n# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set\n# end of Generic IOMMU Pagetable Support\n\n# CONFIG_IOMMU_DEBUGFS is not set\nCONFIG_IOMMU_DEFAULT_DMA_STRICT=y\n# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set\n# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set\nCONFIG_OF_IOMMU=y\nCONFIG_IOMMU_DMA=y\nCONFIG_ARM_SMMU=y\n# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set\nCONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y\n# CONFIG_ARM_SMMU_V3 is not set\n# CONFIG_VIRTIO_IOMMU is not set\n\n#\n# Remoteproc drivers\n#\nCONFIG_REMOTEPROC=y\n# CONFIG_REMOTEPROC_CDEV is not set\nCONFIG_ZYNQMP_R5_REMOTEPROC=m\n# end of Remoteproc drivers\n\n#\n# Rpmsg drivers\n#\nCONFIG_RPMSG=m\n# CONFIG_RPMSG_CHAR is not set\nCONFIG_RPMSG_NS=m\n# CONFIG_RPMSG_QCOM_GLINK_RPM is not set\nCONFIG_RPMSG_VIRTIO=m\n# end of Rpmsg drivers\n\n# CONFIG_SOUNDWIRE is not set\n\n#\n# SOC (System On Chip) specific Drivers\n#\n\n#\n# Amlogic SoC drivers\n#\n# end of Amlogic SoC drivers\n\n#\n# Broadcom SoC drivers\n#\n# CONFIG_SOC_BRCMSTB is not set\n# end of Broadcom SoC drivers\n\n#\n# NXP/Freescale QorIQ SoC drivers\n#\n# CONFIG_QUICC_ENGINE is not set\n# CONFIG_FSL_RCPM is not set\n# end of NXP/Freescale QorIQ SoC drivers\n\n#\n# i.MX SoC drivers\n#\n# end of i.MX SoC drivers\n\n#\n# Enable LiteX SoC Builder specific drivers\n#\n# CONFIG_LITEX_SOC_CONTROLLER is not set\n# end of Enable LiteX SoC Builder specific drivers\n\n#\n# Qualcomm SoC drivers\n#\n# end of Qualcomm SoC drivers\n\n# CONFIG_SOC_TI is not set\n\n#\n# Xilinx SoC drivers\n#\nCONFIG_ZYNQMP_POWER=y\nCONFIG_ZYNQMP_PM_DOMAINS=y\nCONFIG_XLNX_EVENT_MANAGER=y\n# end of Xilinx SoC drivers\n# end of SOC (System On Chip) specific Drivers\n\n# CONFIG_PM_DEVFREQ is not set\nCONFIG_EXTCON=y\n\n#\n# Extcon Device Drivers\n#\n# CONFIG_EXTCON_ADC_JACK is not set\n# CONFIG_EXTCON_FSA9480 is not set\n# CONFIG_EXTCON_GPIO is not set\n# CONFIG_EXTCON_MAX3355 is not set\n# CONFIG_EXTCON_PTN5150 is not set\n# CONFIG_EXTCON_RT8973A is not set\n# CONFIG_EXTCON_SM5502 is not set\n# CONFIG_EXTCON_USB_GPIO is not set\n# CONFIG_EXTCON_USBC_TUSB320 is not set\n# CONFIG_MEMORY is not set\nCONFIG_IIO=y\nCONFIG_IIO_BUFFER=y\nCONFIG_IIO_BUFFER_CB=y\nCONFIG_IIO_BUFFER_DMA=y\nCONFIG_IIO_BUFFER_DMAENGINE=y\nCONFIG_IIO_BUFFER_HW_CONSUMER=y\nCONFIG_IIO_KFIFO_BUF=y\nCONFIG_IIO_TRIGGERED_BUFFER=y\nCONFIG_IIO_CONFIGFS=y\nCONFIG_IIO_TRIGGER=y\nCONFIG_IIO_CONSUMERS_PER_TRIGGER=2\nCONFIG_IIO_SW_DEVICE=y\nCONFIG_IIO_SW_TRIGGER=y\nCONFIG_IIO_TRIGGERED_EVENT=y\n\n#\n# Accelerometers\n#\nCONFIG_ADIS16201=y\nCONFIG_ADIS16209=y\nCONFIG_ADXL313=y\nCONFIG_ADXL313_I2C=y\nCONFIG_ADXL313_SPI=y\nCONFIG_ADXL345=y\nCONFIG_ADXL345_I2C=y\nCONFIG_ADXL345_SPI=y\nCONFIG_ADXL355=y\nCONFIG_ADXL355_I2C=y\nCONFIG_ADXL355_SPI=y\nCONFIG_ADXL367=y\nCONFIG_ADXL367_SPI=y\nCONFIG_ADXL367_I2C=y\nCONFIG_ADXL372=y\nCONFIG_ADXL372_SPI=y\nCONFIG_ADXL372_I2C=y\n# CONFIG_BMA180 is not set\n# CONFIG_BMA220 is not set\n# CONFIG_BMA400 is not set\n# CONFIG_BMC150_ACCEL is not set\n# CONFIG_BMI088_ACCEL is not set\n# CONFIG_DA280 is not set\n# CONFIG_DA311 is not set\n# CONFIG_DMARD06 is not set\n# CONFIG_DMARD09 is not set\n# CONFIG_DMARD10 is not set\n# CONFIG_FXLS8962AF_I2C is not set\n# CONFIG_FXLS8962AF_SPI is not set\n# CONFIG_IIO_ST_ACCEL_3AXIS is not set\n# CONFIG_KXSD9 is not set\n# CONFIG_KXCJK1013 is not set\n# CONFIG_MC3230 is not set\n# CONFIG_MMA7455_I2C is not set\n# CONFIG_MMA7455_SPI is not set\n# CONFIG_MMA7660 is not set\n# CONFIG_MMA8452 is not set\n# CONFIG_MMA9551 is not set\n# CONFIG_MMA9553 is not set\n# CONFIG_MXC4005 is not set\n# CONFIG_MXC6255 is not set\n# CONFIG_SCA3000 is not set\n# CONFIG_SCA3300 is not set\n# CONFIG_STK8312 is not set\n# CONFIG_STK8BA50 is not set\n# end of Accelerometers\n\n#\n# Analog to digital converters\n#\nCONFIG_AD_SIGMA_DELTA=y\nCONFIG_AD4134=y\nCONFIG_AD400X=y\nCONFIG_AD4130=y\nCONFIG_AD4630=y\nCONFIG_AD7091R5=y\nCONFIG_AD7124=y\nCONFIG_AD7173=y\nCONFIG_AD7192=y\nCONFIG_AD7266=y\nCONFIG_AD7291=y\nCONFIG_AD7292=y\nCONFIG_AD7298=y\nCONFIG_AD738X=y\nCONFIG_AD7476=y\nCONFIG_AD7606=y\nCONFIG_AD7606_IFACE_PARALLEL=y\nCONFIG_AD7606_IFACE_SPI=y\nCONFIG_AD7766=y\nCONFIG_AD7768=y\nCONFIG_AD7768_1=y\nCONFIG_AD7780=y\nCONFIG_AD7791=y\nCONFIG_AD7793=y\nCONFIG_AD7887=y\nCONFIG_AD7923=y\nCONFIG_AD7949=y\nCONFIG_AD799X=y\nCONFIG_AD9963=y\nCONFIG_ADAQ8092=y\n# CONFIG_ADM1177 is not set\n# CONFIG_ADI_AXI_ADC is not set\nCONFIG_CF_AXI_ADC=y\nCONFIG_AD9081=y\nCONFIG_AD9083=y\nCONFIG_AD9208=y\nCONFIG_AD9361=y\nCONFIG_AD9361_EXT_BAND_CONTROL=y\nCONFIG_AD9371=y\nCONFIG_ADRV9001=y\nCONFIG_ADRV9001_COMMON_VERBOSE=y\nCONFIG_ADRV9001_ARM_VERBOSE=y\nCONFIG_ADRV9001_VALIDATE_PARAMS=y\nCONFIG_ADRV9009=y\nCONFIG_ADRV9025=y\nCONFIG_AD6676=y\nCONFIG_AD9467=y\nCONFIG_AD9680=y\nCONFIG_ADMC=y\nCONFIG_CF_AXI_TDD=y\nCONFIG_AD_PULSAR=y\nCONFIG_AXI_PULSE_CAPTURE=y\nCONFIG_AXI_FMCADC5_SYNC=y\n# CONFIG_CC10001_ADC is not set\n# CONFIG_ENVELOPE_DETECTOR is not set\n# CONFIG_HI8435 is not set\n# CONFIG_HX711 is not set\nCONFIG_LTC2308=y\nCONFIG_LTC2387=y\nCONFIG_LTC2471=y\nCONFIG_LTC2485=y\nCONFIG_LTC2496=y\nCONFIG_LTC2497=y\n# CONFIG_MAX1027 is not set\n# CONFIG_MAX11100 is not set\n# CONFIG_MAX1118 is not set\nCONFIG_MAX11410=y\n# CONFIG_MAX1241 is not set\n# CONFIG_MAX1363 is not set\n# CONFIG_MAX9611 is not set\n# CONFIG_MCP320X is not set\n# CONFIG_MCP3422 is not set\n# CONFIG_MCP3911 is not set\n# CONFIG_NAU7802 is not set\n# CONFIG_SD_ADC_MODULATOR is not set\n# CONFIG_TI_ADC081C is not set\n# CONFIG_TI_ADC0832 is not set\n# CONFIG_TI_ADC084S021 is not set\n# CONFIG_TI_ADC12138 is not set\n# CONFIG_TI_ADC108S102 is not set\n# CONFIG_TI_ADC128S052 is not set\n# CONFIG_TI_ADC161S626 is not set\n# CONFIG_TI_ADS1015 is not set\n# CONFIG_TI_ADS7950 is not set\n# CONFIG_TI_ADS8344 is not set\n# CONFIG_TI_ADS8688 is not set\n# CONFIG_TI_ADS124S08 is not set\n# CONFIG_TI_ADS131E08 is not set\n# CONFIG_TI_TLC4541 is not set\n# CONFIG_TI_TSC2046 is not set\n# CONFIG_VF610_ADC is not set\nCONFIG_XILINX_XADC=y\nCONFIG_XILINX_AMS=y\n# CONFIG_VERSAL_SYSMON is not set\n# end of Analog to digital converters\n\n#\n# Analog to digital and digital to analog converters\n#\nCONFIG_AD74115=y\nCONFIG_AD74413R=y\nCONFIG_ONE_BIT_ADC_DAC=y\n# end of Analog to digital and digital to analog converters\n\n#\n# Analog Front Ends\n#\n# CONFIG_IIO_RESCALE is not set\n# end of Analog Front Ends\n\n#\n# Amplifiers\n#\nCONFIG_AD8366=y\nCONFIG_AD916X_AMP=y\nCONFIG_ADA4250=y\nCONFIG_HMC425=y\n# end of Amplifiers\n\n#\n# Beamformers\n#\nCONFIG_ADAR1000=y\nCONFIG_ADAR3000=y\n# end of Beamformers\n\n#\n# Capacitance to digital converters\n#\nCONFIG_AD7150=y\n# end of Capacitance to digital converters\n\n#\n# Chemical Sensors\n#\n# CONFIG_ATLAS_PH_SENSOR is not set\n# CONFIG_ATLAS_EZO_SENSOR is not set\n# CONFIG_BME680 is not set\n# CONFIG_CCS811 is not set\n# CONFIG_IAQCORE is not set\n# CONFIG_PMS7003 is not set\n# CONFIG_SCD30_CORE is not set\n# CONFIG_SENSIRION_SGP30 is not set\n# CONFIG_SENSIRION_SGP40 is not set\n# CONFIG_SPS30_I2C is not set\n# CONFIG_SPS30_SERIAL is not set\n# CONFIG_VZ89X is not set\n# end of Chemical Sensors\n\n#\n# Hid Sensor IIO Common\n#\n# end of Hid Sensor IIO Common\n\n#\n# IIO SCMI Sensors\n#\n# end of IIO SCMI Sensors\n\n#\n# SSP Sensor Common\n#\n# CONFIG_IIO_SSP_SENSORHUB is not set\n# end of SSP Sensor Common\n\n#\n# Digital to analog converters\n#\nCONFIG_AD3552R=y\nCONFIG_AD5064=y\nCONFIG_AD5270=y\nCONFIG_AD5360=y\nCONFIG_AD5380=y\nCONFIG_AD5421=y\nCONFIG_AD5446=y\nCONFIG_AD5449=y\nCONFIG_AD5592R_BASE=y\nCONFIG_AD5592R=y\nCONFIG_AD5593R=y\nCONFIG_AD5504=y\nCONFIG_AD5624R_SPI=y\nCONFIG_LTC2688=y\nCONFIG_AD5686=y\nCONFIG_AD5686_SPI=y\nCONFIG_AD5696_I2C=y\nCONFIG_AD5755=y\nCONFIG_AD5758=y\nCONFIG_AD5761=y\nCONFIG_AD5764=y\nCONFIG_AD5766=y\nCONFIG_AD5770R=y\nCONFIG_AD5791=y\nCONFIG_AD7293=y\nCONFIG_AD7303=y\nCONFIG_AD8801=y\n# CONFIG_DPOT_DAC is not set\n# CONFIG_DS4424 is not set\nCONFIG_LTC1660=y\nCONFIG_LTC2632=y\n# CONFIG_M62332 is not set\n# CONFIG_MAX517 is not set\n# CONFIG_MAX5821 is not set\n# CONFIG_MCP4725 is not set\n# CONFIG_MCP4922 is not set\n# CONFIG_TI_DAC082S085 is not set\n# CONFIG_TI_DAC5571 is not set\n# CONFIG_TI_DAC7311 is not set\n# CONFIG_TI_DAC7612 is not set\n# CONFIG_VF610_DAC is not set\n# end of Digital to analog converters\n\n#\n# IIO dummy driver\n#\n# CONFIG_IIO_SIMPLE_DUMMY is not set\n# end of IIO dummy driver\n\n#\n# Filters\n#\nCONFIG_ADMV8818=y\n# end of Filters\n\n#\n# Frequency Synthesizers DDS/PLL\n#\n\n#\n# Clock Generator/Distribution\n#\nCONFIG_AD9508=y\nCONFIG_AD9523=y\nCONFIG_AD9528=y\nCONFIG_AD9548=y\nCONFIG_AD9517=y\nCONFIG_ADMV1013=y\nCONFIG_ADMV1014=y\nCONFIG_ADMV4420=y\nCONFIG_ADRF6780=y\nCONFIG_HMC7044=y\nCONFIG_LTC6952=y\n# end of Clock Generator/Distribution\n\n#\n# Direct Digital Synthesis\n#\nCONFIG_CF_AXI_DDS=y\nCONFIG_CF_AXI_DDS_AD9122=y\nCONFIG_CF_AXI_DDS_AD9144=y\nCONFIG_CF_AXI_DDS_AD9162=y\nCONFIG_CF_AXI_DDS_AD9172=y\nCONFIG_CF_AXI_DDS_AD9739A=y\nCONFIG_CF_AXI_DDS_AD9783=y\nCONFIG_M2K_DAC=y\n# end of Direct Digital Synthesis\n\n#\n# Phase-Locked Loop (PLL) frequency synthesizers\n#\nCONFIG_ADF4159=y\nCONFIG_ADF4350=y\nCONFIG_ADF4360=y\nCONFIG_ADF4371=y\nCONFIG_ADF4377=y\nCONFIG_ADF5355=y\n# end of Phase-Locked Loop (PLL) frequency synthesizers\n\n#\n# RF Font-Ends\n#\nCONFIG_ADL5960=y\n# end of RF Font-Ends\n# end of Frequency Synthesizers DDS/PLL\n\n#\n# Digital gyroscope sensors\n#\nCONFIG_ADIS16080=y\nCONFIG_ADIS16130=y\nCONFIG_ADIS16136=y\nCONFIG_ADIS16260=y\nCONFIG_ADXRS290=y\nCONFIG_ADXRS450=y\n# CONFIG_BMG160 is not set\n# CONFIG_FXAS21002C is not set\n# CONFIG_MPU3050_I2C is not set\n# CONFIG_IIO_ST_GYRO_3AXIS is not set\n# CONFIG_ITG3200 is not set\n# end of Digital gyroscope sensors\n\n#\n# Health Sensors\n#\n\n#\n# Heart Rate Monitors\n#\n# CONFIG_AFE4403 is not set\n# CONFIG_AFE4404 is not set\n# CONFIG_MAX30100 is not set\n# CONFIG_MAX30102 is not set\n# end of Heart Rate Monitors\n# end of Health Sensors\n\n#\n# Humidity sensors\n#\n# CONFIG_AM2315 is not set\n# CONFIG_DHT11 is not set\n# CONFIG_HDC100X is not set\n# CONFIG_HDC2010 is not set\n# CONFIG_HTS221 is not set\n# CONFIG_HTU21 is not set\n# CONFIG_SI7005 is not set\n# CONFIG_SI7020 is not set\n# end of Humidity sensors\n\n#\n# Inertial measurement units\n#\nCONFIG_ADIS16400=y\nCONFIG_ADIS16460=y\nCONFIG_ADIS16475=y\nCONFIG_ADIS16480=y\n# CONFIG_BMI160_I2C is not set\n# CONFIG_BMI160_SPI is not set\n# CONFIG_FXOS8700_I2C is not set\n# CONFIG_FXOS8700_SPI is not set\n# CONFIG_KMX61 is not set\n# CONFIG_INV_ICM42600_I2C is not set\n# CONFIG_INV_ICM42600_SPI is not set\n# CONFIG_INV_MPU6050_I2C is not set\n# CONFIG_INV_MPU6050_SPI is not set\n# CONFIG_IIO_ST_LSM6DSX is not set\n# CONFIG_IIO_ST_LSM9DS0 is not set\n# end of Inertial measurement units\n\nCONFIG_IIO_ADIS_LIB=y\nCONFIG_IIO_ADIS_LIB_BUFFER=y\n# CONFIG_ALTERA_ARRIA10_JESD204_PHY is not set\nCONFIG_AXI_ADXCVR=y\n# CONFIG_AXI_JESD204B is not set\nCONFIG_AXI_JESD204_TX=y\nCONFIG_AXI_JESD204_RX=y\nCONFIG_XILINX_TRANSCEIVER=y\nCONFIG_ADI_IIO_FAKEDEV=y\n\n#\n# Light sensors\n#\n# CONFIG_ADJD_S311 is not set\nCONFIG_ADUX1020=y\n# CONFIG_AL3010 is not set\n# CONFIG_AL3320A is not set\n# CONFIG_APDS9300 is not set\n# CONFIG_APDS9960 is not set\n# CONFIG_AS73211 is not set\n# CONFIG_BH1750 is not set\n# CONFIG_BH1780 is not set\n# CONFIG_CM32181 is not set\n# CONFIG_CM3232 is not set\n# CONFIG_CM3323 is not set\n# CONFIG_CM3605 is not set\n# CONFIG_CM36651 is not set\n# CONFIG_GP2AP002 is not set\n# CONFIG_GP2AP020A00F is not set\n# CONFIG_SENSORS_ISL29018 is not set\n# CONFIG_SENSORS_ISL29028 is not set\n# CONFIG_ISL29125 is not set\n# CONFIG_JSA1212 is not set\n# CONFIG_RPR0521 is not set\n# CONFIG_LTR501 is not set\n# CONFIG_LV0104CS is not set\n# CONFIG_MAX44000 is not set\n# CONFIG_MAX44009 is not set\n# CONFIG_NOA1305 is not set\n# CONFIG_OPT3001 is not set\n# CONFIG_PA12203001 is not set\n# CONFIG_SI1133 is not set\n# CONFIG_SI1145 is not set\n# CONFIG_STK3310 is not set\n# CONFIG_ST_UVIS25 is not set\n# CONFIG_TCS3414 is not set\n# CONFIG_TCS3472 is not set\n# CONFIG_SENSORS_TSL2563 is not set\n# CONFIG_TSL2583 is not set\n# CONFIG_TSL2591 is not set\n# CONFIG_TSL2772 is not set\n# CONFIG_TSL4531 is not set\n# CONFIG_US5182D is not set\n# CONFIG_VCNL4000 is not set\n# CONFIG_VCNL4035 is not set\n# CONFIG_VEML6030 is not set\n# CONFIG_VEML6070 is not set\n# CONFIG_VL6180 is not set\n# CONFIG_ZOPT2201 is not set\n# end of Light sensors\n\n#\n# Logic Analyzers\n#\nCONFIG_M2K_LOGIC_ANALYZER=y\n# end of Logic Analyzers\n\n#\n# Magnetometer sensors\n#\n# CONFIG_AK8974 is not set\n# CONFIG_AK8975 is not set\n# CONFIG_AK09911 is not set\n# CONFIG_BMC150_MAGN_I2C is not set\n# CONFIG_BMC150_MAGN_SPI is not set\n# CONFIG_MAG3110 is not set\n# CONFIG_MMC35240 is not set\n# CONFIG_IIO_ST_MAGN_3AXIS is not set\n# CONFIG_SENSORS_HMC5843_I2C is not set\n# CONFIG_SENSORS_HMC5843_SPI is not set\n# CONFIG_SENSORS_RM3100_I2C is not set\n# CONFIG_SENSORS_RM3100_SPI is not set\n# CONFIG_YAMAHA_YAS530 is not set\n# end of Magnetometer sensors\n\n#\n# Multiplexers\n#\n# CONFIG_IIO_MUX is not set\nCONFIG_IIO_GEN_MUX=y\n# end of Multiplexers\n\n#\n# IIO Regmap Access Drivers\n#\nCONFIG_IIO_REGMAP=y\nCONFIG_IIO_REGMAP_I2C=y\nCONFIG_IIO_REGMAP_SPI=y\n# end of IIO Regmap Access Drivers\n\n#\n# Inclinometer sensors\n#\n# end of Inclinometer sensors\n\n#\n# Triggers - standalone\n#\nCONFIG_IIO_HRTIMER_TRIGGER=y\nCONFIG_IIO_INTERRUPT_TRIGGER=y\nCONFIG_IIO_TIGHTLOOP_TRIGGER=y\nCONFIG_IIO_SYSFS_TRIGGER=y\n# end of Triggers - standalone\n\n#\n# Linear and angular position sensors\n#\n# end of Linear and angular position sensors\n\n#\n# Digital potentiometers\n#\nCONFIG_AD5110=y\nCONFIG_AD5272=y\n# CONFIG_DS1803 is not set\n# CONFIG_MAX5432 is not set\n# CONFIG_MAX5481 is not set\n# CONFIG_MAX5487 is not set\n# CONFIG_MCP4018 is not set\n# CONFIG_MCP4131 is not set\n# CONFIG_MCP4531 is not set\n# CONFIG_MCP41010 is not set\n# CONFIG_TPL0102 is not set\n# end of Digital potentiometers\n\n#\n# Digital potentiostats\n#\n# CONFIG_LMP91000 is not set\n# end of Digital potentiostats\n\n#\n# Pressure sensors\n#\n# CONFIG_ABP060MG is not set\n# CONFIG_BMP280 is not set\n# CONFIG_DLHL60D is not set\n# CONFIG_DPS310 is not set\n# CONFIG_HP03 is not set\n# CONFIG_ICP10100 is not set\n# CONFIG_MPL115_I2C is not set\n# CONFIG_MPL115_SPI is not set\n# CONFIG_MPL3115 is not set\n# CONFIG_MS5611 is not set\n# CONFIG_MS5637 is not set\n# CONFIG_IIO_ST_PRESS is not set\n# CONFIG_T5403 is not set\n# CONFIG_HP206C is not set\n# CONFIG_ZPA2326 is not set\n# end of Pressure sensors\n\n#\n# Lightning sensors\n#\n# CONFIG_AS3935 is not set\n# end of Lightning sensors\n\n#\n# Proximity and distance sensors\n#\n# CONFIG_ISL29501 is not set\n# CONFIG_LIDAR_LITE_V2 is not set\n# CONFIG_MB1232 is not set\n# CONFIG_PING is not set\n# CONFIG_RFD77402 is not set\n# CONFIG_SRF04 is not set\n# CONFIG_SX9310 is not set\n# CONFIG_SX9500 is not set\n# CONFIG_SRF08 is not set\n# CONFIG_VCNL3020 is not set\n# CONFIG_VL53L0X_I2C is not set\n# end of Proximity and distance sensors\n\n#\n# Resolver to digital converters\n#\nCONFIG_AD2S90=y\nCONFIG_AD2S1200=y\n# end of Resolver to digital converters\n\n#\n# Temperature sensors\n#\nCONFIG_LTC2983=y\n# CONFIG_MAXIM_THERMOCOUPLE is not set\n# CONFIG_MLX90614 is not set\n# CONFIG_MLX90632 is not set\n# CONFIG_TMP006 is not set\n# CONFIG_TMP007 is not set\n# CONFIG_TMP117 is not set\n# CONFIG_TSYS01 is not set\n# CONFIG_TSYS02D is not set\n# CONFIG_MAX31856 is not set\nCONFIG_MAX31865=y\n# end of Temperature sensors\n\nCONFIG_JESD204=y\nCONFIG_JESD204_TOP_DEVICE=y\n# CONFIG_NTB is not set\n# CONFIG_VME_BUS is not set\nCONFIG_PWM=y\nCONFIG_PWM_SYSFS=y\n# CONFIG_PWM_DEBUG is not set\n# CONFIG_PWM_ATMEL_TCB is not set\nCONFIG_PWM_AXI_PWMGEN=y\n# CONFIG_PWM_DWC is not set\n# CONFIG_PWM_FSL_FTM is not set\n# CONFIG_PWM_PCA9685 is not set\n# CONFIG_PWM_CADENCE is not set\n\n#\n# IRQ chip support\n#\nCONFIG_IRQCHIP=y\nCONFIG_ARM_GIC=y\nCONFIG_ARM_GIC_MAX_NR=1\nCONFIG_ARM_GIC_V2M=y\nCONFIG_ARM_GIC_V3=y\nCONFIG_ARM_GIC_V3_ITS=y\nCONFIG_ARM_GIC_V3_ITS_PCI=y\n# CONFIG_AL_FIC is not set\nCONFIG_XILINX_INTC=y\n# CONFIG_IRQCHIP_XILINX_INTC_MODULE_SUPPORT_EXPERIMENTAL is not set\nCONFIG_PARTITION_PERCPU=y\n# end of IRQ chip support\n\n# CONFIG_IPACK_BUS is not set\nCONFIG_RESET_CONTROLLER=y\n# CONFIG_RESET_TI_SYSCON is not set\n\n#\n# PHY Subsystem\n#\nCONFIG_GENERIC_PHY=y\n# CONFIG_PHY_XGENE is not set\n# CONFIG_PHY_CAN_TRANSCEIVER is not set\n# CONFIG_BCM_KONA_USB2_PHY is not set\n# CONFIG_PHY_CADENCE_TORRENT is not set\n# CONFIG_PHY_CADENCE_DPHY is not set\n# CONFIG_PHY_CADENCE_SIERRA is not set\n# CONFIG_PHY_CADENCE_SALVO is not set\n# CONFIG_PHY_FSL_IMX8MQ_USB is not set\n# CONFIG_PHY_MIXEL_MIPI_DPHY is not set\n# CONFIG_PHY_PXA_28NM_HSIC is not set\n# CONFIG_PHY_PXA_28NM_USB2 is not set\n# CONFIG_PHY_CPCAP_USB is not set\n# CONFIG_PHY_MAPPHONE_MDM6600 is not set\n# CONFIG_PHY_OCELOT_SERDES is not set\n# CONFIG_PHY_QCOM_USB_HS is not set\n# CONFIG_PHY_QCOM_USB_HSIC is not set\n# CONFIG_PHY_SAMSUNG_USB2 is not set\n# CONFIG_PHY_TUSB1210 is not set\nCONFIG_PHY_XILINX_ZYNQMP=y\n# CONFIG_PHY_XILINX_HDMIPHY is not set\n# end of PHY Subsystem\n\n# CONFIG_POWERCAP is not set\n# CONFIG_MCB is not set\n\n#\n# Performance monitor support\n#\n# CONFIG_ARM_CCI_PMU is not set\n# CONFIG_ARM_CCN is not set\n# CONFIG_ARM_CMN is not set\nCONFIG_ARM_PMU=y\n# CONFIG_ARM_DSU_PMU is not set\n# CONFIG_ARM_SPE_PMU is not set\n# end of Performance monitor support\n\nCONFIG_RAS=y\n# CONFIG_USB4 is not set\n\n#\n# Android\n#\nCONFIG_ANDROID=y\n# CONFIG_ANDROID_BINDER_IPC is not set\n# end of Android\n\n# CONFIG_LIBNVDIMM is not set\n# CONFIG_DAX is not set\nCONFIG_NVMEM=y\nCONFIG_NVMEM_SYSFS=y\nCONFIG_NVMEM_AXI_SYSID=y\nCONFIG_NVMEM_ZYNQMP=y\n# CONFIG_XLNX_SEC_CFG is not set\n# CONFIG_NVMEM_RMEM is not set\n\n#\n# HW tracing support\n#\n# CONFIG_STM is not set\n# CONFIG_INTEL_TH is not set\n# end of HW tracing support\n\nCONFIG_FPGA=y\n# CONFIG_FPGA_MGR_DEBUG_FS is not set\n# CONFIG_ALTERA_PR_IP_CORE is not set\n# CONFIG_FPGA_MGR_ALTERA_PS_SPI is not set\n# CONFIG_FPGA_MGR_ALTERA_CVP is not set\n# CONFIG_FPGA_MGR_XILINX_SPI is not set\n# CONFIG_FPGA_MGR_ICE40_SPI is not set\n# CONFIG_FPGA_MGR_MACHXO2_SPI is not set\nCONFIG_XILINX_AFI_FPGA=y\nCONFIG_FPGA_BRIDGE=y\n# CONFIG_ALTERA_FREEZE_BRIDGE is not set\nCONFIG_XILINX_PR_DECOUPLER=y\nCONFIG_FPGA_REGION=y\nCONFIG_OF_FPGA_REGION=y\n# CONFIG_FPGA_DFL is not set\nCONFIG_FPGA_MGR_ZYNQMP_FPGA=y\n# CONFIG_FPGA_MGR_VERSAL_FPGA is not set\n# CONFIG_FSI is not set\n# CONFIG_TEE is not set\nCONFIG_MULTIPLEXER=y\n\n#\n# Multiplexer drivers\n#\nCONFIG_MUX_ADG792A=y\nCONFIG_MUX_ADGS1408=y\nCONFIG_MUX_GPIO=y\n# CONFIG_MUX_MMIO is not set\n# end of Multiplexer drivers\n\nCONFIG_PM_OPP=y\n# CONFIG_SIOX is not set\n# CONFIG_SLIMBUS is not set\n# CONFIG_INTERCONNECT is not set\n# CONFIG_COUNTER is not set\n# CONFIG_MOST is not set\n# end of Device Drivers\n\n#\n# File systems\n#\nCONFIG_DCACHE_WORD_ACCESS=y\n# CONFIG_VALIDATE_FS_PARSER is not set\nCONFIG_FS_IOMAP=y\nCONFIG_EXT2_FS=y\n# CONFIG_EXT2_FS_XATTR is not set\nCONFIG_EXT3_FS=y\n# CONFIG_EXT3_FS_POSIX_ACL is not set\n# CONFIG_EXT3_FS_SECURITY is not set\nCONFIG_EXT4_FS=y\nCONFIG_EXT4_FS_POSIX_ACL=y\nCONFIG_EXT4_FS_SECURITY=y\n# CONFIG_EXT4_DEBUG is not set\nCONFIG_JBD2=y\n# CONFIG_JBD2_DEBUG is not set\nCONFIG_FS_MBCACHE=y\n# CONFIG_REISERFS_FS is not set\n# CONFIG_JFS_FS is not set\n# CONFIG_XFS_FS is not set\n# CONFIG_GFS2_FS is not set\n# CONFIG_OCFS2_FS is not set\nCONFIG_BTRFS_FS=y\n# CONFIG_BTRFS_FS_POSIX_ACL is not set\n# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set\n# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set\n# CONFIG_BTRFS_DEBUG is not set\n# CONFIG_BTRFS_ASSERT is not set\n# CONFIG_BTRFS_FS_REF_VERIFY is not set\n# CONFIG_NILFS2_FS is not set\n# CONFIG_F2FS_FS is not set\n# CONFIG_FS_DAX is not set\nCONFIG_FS_POSIX_ACL=y\nCONFIG_EXPORTFS=y\n# CONFIG_EXPORTFS_BLOCK_OPS is not set\nCONFIG_FILE_LOCKING=y\n# CONFIG_FS_ENCRYPTION is not set\n# CONFIG_FS_VERITY is not set\nCONFIG_FSNOTIFY=y\nCONFIG_DNOTIFY=y\nCONFIG_INOTIFY_USER=y\n# CONFIG_FANOTIFY is not set\nCONFIG_QUOTA=y\n# CONFIG_QUOTA_NETLINK_INTERFACE is not set\nCONFIG_PRINT_QUOTA_WARNING=y\n# CONFIG_QUOTA_DEBUG is not set\nCONFIG_QUOTA_TREE=y\n# CONFIG_QFMT_V1 is not set\nCONFIG_QFMT_V2=y\nCONFIG_QUOTACTL=y\nCONFIG_AUTOFS4_FS=y\nCONFIG_AUTOFS_FS=y\nCONFIG_FUSE_FS=y\n# CONFIG_CUSE is not set\n# CONFIG_VIRTIO_FS is not set\n# CONFIG_OVERLAY_FS is not set\n\n#\n# Caches\n#\n# CONFIG_FSCACHE is not set\n# end of Caches\n\n#\n# CD-ROM/DVD Filesystems\n#\n# CONFIG_ISO9660_FS is not set\n# CONFIG_UDF_FS is not set\n# end of CD-ROM/DVD Filesystems\n\n#\n# DOS/FAT/EXFAT/NT Filesystems\n#\nCONFIG_FAT_FS=y\nCONFIG_MSDOS_FS=y\nCONFIG_VFAT_FS=y\nCONFIG_FAT_DEFAULT_CODEPAGE=437\nCONFIG_FAT_DEFAULT_IOCHARSET=\"iso8859-1\"\n# CONFIG_FAT_DEFAULT_UTF8 is not set\n# CONFIG_EXFAT_FS is not set\n# CONFIG_NTFS_FS is not set\n# CONFIG_NTFS3_FS is not set\n# end of DOS/FAT/EXFAT/NT Filesystems\n\n#\n# Pseudo filesystems\n#\nCONFIG_PROC_FS=y\n# CONFIG_PROC_KCORE is not set\nCONFIG_PROC_SYSCTL=y\nCONFIG_PROC_PAGE_MONITOR=y\n# CONFIG_PROC_CHILDREN is not set\nCONFIG_KERNFS=y\nCONFIG_SYSFS=y\nCONFIG_TMPFS=y\nCONFIG_TMPFS_POSIX_ACL=y\nCONFIG_TMPFS_XATTR=y\n# CONFIG_TMPFS_INODE64 is not set\nCONFIG_ARCH_SUPPORTS_HUGETLBFS=y\nCONFIG_HUGETLBFS=y\nCONFIG_HUGETLB_PAGE=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_ARCH_HAS_GIGANTIC_PAGE=y\nCONFIG_CONFIGFS_FS=y\nCONFIG_EFIVAR_FS=m\n# end of Pseudo filesystems\n\nCONFIG_MISC_FILESYSTEMS=y\n# CONFIG_ORANGEFS_FS is not set\n# CONFIG_ADFS_FS is not set\n# CONFIG_AFFS_FS is not set\nCONFIG_ECRYPT_FS=y\n# CONFIG_ECRYPT_FS_MESSAGING is not set\n# CONFIG_HFS_FS is not set\n# CONFIG_HFSPLUS_FS is not set\n# CONFIG_BEFS_FS is not set\n# CONFIG_BFS_FS is not set\n# CONFIG_EFS_FS is not set\nCONFIG_JFFS2_FS=y\nCONFIG_JFFS2_FS_DEBUG=0\nCONFIG_JFFS2_FS_WRITEBUFFER=y\n# CONFIG_JFFS2_FS_WBUF_VERIFY is not set\nCONFIG_JFFS2_SUMMARY=y\nCONFIG_JFFS2_FS_XATTR=y\nCONFIG_JFFS2_FS_POSIX_ACL=y\nCONFIG_JFFS2_FS_SECURITY=y\nCONFIG_JFFS2_COMPRESSION_OPTIONS=y\nCONFIG_JFFS2_ZLIB=y\nCONFIG_JFFS2_LZO=y\nCONFIG_JFFS2_RTIME=y\nCONFIG_JFFS2_RUBIN=y\n# CONFIG_JFFS2_CMODE_NONE is not set\nCONFIG_JFFS2_CMODE_PRIORITY=y\n# CONFIG_JFFS2_CMODE_SIZE is not set\n# CONFIG_JFFS2_CMODE_FAVOURLZO is not set\nCONFIG_CRAMFS=y\nCONFIG_CRAMFS_BLOCKDEV=y\n# CONFIG_CRAMFS_MTD is not set\n# CONFIG_SQUASHFS is not set\n# CONFIG_VXFS_FS is not set\n# CONFIG_MINIX_FS is not set\n# CONFIG_OMFS_FS is not set\n# CONFIG_HPFS_FS is not set\n# CONFIG_QNX4FS_FS is not set\n# CONFIG_QNX6FS_FS is not set\n# CONFIG_ROMFS_FS is not set\n# CONFIG_PSTORE is not set\n# CONFIG_SYSV_FS is not set\n# CONFIG_UFS_FS is not set\n# CONFIG_EROFS_FS is not set\nCONFIG_NETWORK_FILESYSTEMS=y\nCONFIG_NFS_FS=y\nCONFIG_NFS_V2=y\nCONFIG_NFS_V3=y\nCONFIG_NFS_V3_ACL=y\nCONFIG_NFS_V4=y\n# CONFIG_NFS_SWAP is not set\nCONFIG_NFS_V4_1=y\nCONFIG_NFS_V4_2=y\nCONFIG_PNFS_FILE_LAYOUT=y\nCONFIG_PNFS_FLEXFILE_LAYOUT=y\nCONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN=\"kernel.org\"\n# CONFIG_NFS_V4_1_MIGRATION is not set\nCONFIG_ROOT_NFS=y\n# CONFIG_NFS_USE_LEGACY_DNS is not set\nCONFIG_NFS_USE_KERNEL_DNS=y\nCONFIG_NFS_DISABLE_UDP_SUPPORT=y\n# CONFIG_NFS_V4_2_READ_PLUS is not set\n# CONFIG_NFSD is not set\nCONFIG_GRACE_PERIOD=y\nCONFIG_LOCKD=y\nCONFIG_LOCKD_V4=y\nCONFIG_NFS_ACL_SUPPORT=y\nCONFIG_NFS_COMMON=y\nCONFIG_NFS_V4_2_SSC_HELPER=y\nCONFIG_SUNRPC=y\nCONFIG_SUNRPC_GSS=y\nCONFIG_SUNRPC_BACKCHANNEL=y\n# CONFIG_SUNRPC_DEBUG is not set\n# CONFIG_CEPH_FS is not set\n# CONFIG_CIFS is not set\n# CONFIG_SMB_SERVER is not set\n# CONFIG_CODA_FS is not set\n# CONFIG_AFS_FS is not set\n# CONFIG_9P_FS is not set\nCONFIG_NLS=y\nCONFIG_NLS_DEFAULT=\"iso8859-1\"\nCONFIG_NLS_CODEPAGE_437=y\n# CONFIG_NLS_CODEPAGE_737 is not set\n# CONFIG_NLS_CODEPAGE_775 is not set\n# CONFIG_NLS_CODEPAGE_850 is not set\n# CONFIG_NLS_CODEPAGE_852 is not set\n# CONFIG_NLS_CODEPAGE_855 is not set\n# CONFIG_NLS_CODEPAGE_857 is not set\n# CONFIG_NLS_CODEPAGE_860 is not set\n# CONFIG_NLS_CODEPAGE_861 is not set\n# CONFIG_NLS_CODEPAGE_862 is not set\n# CONFIG_NLS_CODEPAGE_863 is not set\n# CONFIG_NLS_CODEPAGE_864 is not set\n# CONFIG_NLS_CODEPAGE_865 is not set\n# CONFIG_NLS_CODEPAGE_866 is not set\n# CONFIG_NLS_CODEPAGE_869 is not set\n# CONFIG_NLS_CODEPAGE_936 is not set\n# CONFIG_NLS_CODEPAGE_950 is not set\n# CONFIG_NLS_CODEPAGE_932 is not set\n# CONFIG_NLS_CODEPAGE_949 is not set\n# CONFIG_NLS_CODEPAGE_874 is not set\n# CONFIG_NLS_ISO8859_8 is not set\n# CONFIG_NLS_CODEPAGE_1250 is not set\n# CONFIG_NLS_CODEPAGE_1251 is not set\n# CONFIG_NLS_ASCII is not set\nCONFIG_NLS_ISO8859_1=y\n# CONFIG_NLS_ISO8859_2 is not set\n# CONFIG_NLS_ISO8859_3 is not set\n# CONFIG_NLS_ISO8859_4 is not set\n# CONFIG_NLS_ISO8859_5 is not set\n# CONFIG_NLS_ISO8859_6 is not set\n# CONFIG_NLS_ISO8859_7 is not set\n# CONFIG_NLS_ISO8859_9 is not set\n# CONFIG_NLS_ISO8859_13 is not set\n# CONFIG_NLS_ISO8859_14 is not set\n# CONFIG_NLS_ISO8859_15 is not set\n# CONFIG_NLS_KOI8_R is not set\n# CONFIG_NLS_KOI8_U is not set\n# CONFIG_NLS_MAC_ROMAN is not set\n# CONFIG_NLS_MAC_CELTIC is not set\n# CONFIG_NLS_MAC_CENTEURO is not set\n# CONFIG_NLS_MAC_CROATIAN is not set\n# CONFIG_NLS_MAC_CYRILLIC is not set\n# CONFIG_NLS_MAC_GAELIC is not set\n# CONFIG_NLS_MAC_GREEK is not set\n# CONFIG_NLS_MAC_ICELAND is not set\n# CONFIG_NLS_MAC_INUIT is not set\n# CONFIG_NLS_MAC_ROMANIAN is not set\n# CONFIG_NLS_MAC_TURKISH is not set\n# CONFIG_NLS_UTF8 is not set\n# CONFIG_DLM is not set\n# CONFIG_UNICODE is not set\nCONFIG_IO_WQ=y\n# end of File systems\n\n#\n# Security options\n#\nCONFIG_KEYS=y\n# CONFIG_KEYS_REQUEST_CACHE is not set\n# CONFIG_PERSISTENT_KEYRINGS is not set\n# CONFIG_ENCRYPTED_KEYS is not set\n# CONFIG_KEY_DH_OPERATIONS is not set\n# CONFIG_SECURITY_DMESG_RESTRICT is not set\n# CONFIG_SECURITY is not set\n# CONFIG_SECURITYFS is not set\nCONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y\n# CONFIG_HARDENED_USERCOPY is not set\n# CONFIG_FORTIFY_SOURCE is not set\n# CONFIG_STATIC_USERMODEHELPER is not set\n# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set\nCONFIG_DEFAULT_SECURITY_DAC=y\nCONFIG_LSM=\"landlock,lockdown,yama,loadpin,safesetid,integrity,bpf\"\n\n#\n# Kernel hardening options\n#\n\n#\n# Memory initialization\n#\nCONFIG_INIT_STACK_NONE=y\n# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set\n# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set\n# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set\n# CONFIG_GCC_PLUGIN_STACKLEAK is not set\n# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set\n# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set\n# end of Memory initialization\n# end of Kernel hardening options\n# end of Security options\n\nCONFIG_XOR_BLOCKS=y\nCONFIG_CRYPTO=y\n\n#\n# Crypto core or helper\n#\nCONFIG_CRYPTO_ALGAPI=y\nCONFIG_CRYPTO_ALGAPI2=y\nCONFIG_CRYPTO_AEAD=y\nCONFIG_CRYPTO_AEAD2=y\nCONFIG_CRYPTO_SKCIPHER=y\nCONFIG_CRYPTO_SKCIPHER2=y\nCONFIG_CRYPTO_HASH=y\nCONFIG_CRYPTO_HASH2=y\nCONFIG_CRYPTO_RNG=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_RNG_DEFAULT=y\nCONFIG_CRYPTO_AKCIPHER2=y\nCONFIG_CRYPTO_AKCIPHER=y\nCONFIG_CRYPTO_KPP2=y\nCONFIG_CRYPTO_KPP=y\nCONFIG_CRYPTO_ACOMP2=y\nCONFIG_CRYPTO_MANAGER=y\nCONFIG_CRYPTO_MANAGER2=y\n# CONFIG_CRYPTO_USER is not set\n# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set\n# CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set\nCONFIG_CRYPTO_GF128MUL=y\nCONFIG_CRYPTO_NULL=y\nCONFIG_CRYPTO_NULL2=y\n# CONFIG_CRYPTO_PCRYPT is not set\n# CONFIG_CRYPTO_CRYPTD is not set\nCONFIG_CRYPTO_AUTHENC=y\n# CONFIG_CRYPTO_TEST is not set\nCONFIG_CRYPTO_ENGINE=y\n\n#\n# Public-key cryptography\n#\nCONFIG_CRYPTO_RSA=y\n# CONFIG_CRYPTO_DH is not set\nCONFIG_CRYPTO_ECC=y\nCONFIG_CRYPTO_ECDH=y\n# CONFIG_CRYPTO_ECDSA is not set\n# CONFIG_CRYPTO_ECRDSA is not set\n# CONFIG_CRYPTO_SM2 is not set\n# CONFIG_CRYPTO_CURVE25519 is not set\n\n#\n# Authenticated Encryption with Associated Data\n#\nCONFIG_CRYPTO_CCM=y\nCONFIG_CRYPTO_GCM=y\n# CONFIG_CRYPTO_CHACHA20POLY1305 is not set\n# CONFIG_CRYPTO_AEGIS128 is not set\n# CONFIG_CRYPTO_SEQIV is not set\n# CONFIG_CRYPTO_ECHAINIV is not set\n\n#\n# Block modes\n#\nCONFIG_CRYPTO_CBC=y\n# CONFIG_CRYPTO_CFB is not set\nCONFIG_CRYPTO_CTR=y\n# CONFIG_CRYPTO_CTS is not set\nCONFIG_CRYPTO_ECB=y\n# CONFIG_CRYPTO_LRW is not set\n# CONFIG_CRYPTO_OFB is not set\n# CONFIG_CRYPTO_PCBC is not set\n# CONFIG_CRYPTO_XTS is not set\n# CONFIG_CRYPTO_KEYWRAP is not set\n# CONFIG_CRYPTO_ADIANTUM is not set\n# CONFIG_CRYPTO_ESSIV is not set\n\n#\n# Hash modes\n#\nCONFIG_CRYPTO_CMAC=y\nCONFIG_CRYPTO_HMAC=y\n# CONFIG_CRYPTO_XCBC is not set\n# CONFIG_CRYPTO_VMAC is not set\n\n#\n# Digest\n#\nCONFIG_CRYPTO_CRC32C=y\n# CONFIG_CRYPTO_CRC32 is not set\nCONFIG_CRYPTO_XXHASH=y\nCONFIG_CRYPTO_BLAKE2B=y\n# CONFIG_CRYPTO_BLAKE2S is not set\nCONFIG_CRYPTO_CRCT10DIF=y\nCONFIG_CRYPTO_GHASH=y\n# CONFIG_CRYPTO_POLY1305 is not set\n# CONFIG_CRYPTO_MD4 is not set\nCONFIG_CRYPTO_MD5=y\n# CONFIG_CRYPTO_MICHAEL_MIC is not set\n# CONFIG_CRYPTO_RMD160 is not set\n# CONFIG_CRYPTO_SHA1 is not set\nCONFIG_CRYPTO_SHA256=y\nCONFIG_CRYPTO_SHA512=y\n# CONFIG_CRYPTO_SHA3 is not set\n# CONFIG_CRYPTO_SM3 is not set\n# CONFIG_CRYPTO_STREEBOG is not set\n# CONFIG_CRYPTO_WP512 is not set\n\n#\n# Ciphers\n#\nCONFIG_CRYPTO_AES=y\n# CONFIG_CRYPTO_AES_TI is not set\n# CONFIG_CRYPTO_ANUBIS is not set\n# CONFIG_CRYPTO_ARC4 is not set\n# CONFIG_CRYPTO_BLOWFISH is not set\n# CONFIG_CRYPTO_CAMELLIA is not set\n# CONFIG_CRYPTO_CAST5 is not set\n# CONFIG_CRYPTO_CAST6 is not set\n# CONFIG_CRYPTO_DES is not set\n# CONFIG_CRYPTO_FCRYPT is not set\n# CONFIG_CRYPTO_KHAZAD is not set\n# CONFIG_CRYPTO_CHACHA20 is not set\n# CONFIG_CRYPTO_SEED is not set\n# CONFIG_CRYPTO_SERPENT is not set\n# CONFIG_CRYPTO_SM4 is not set\n# CONFIG_CRYPTO_TEA is not set\n# CONFIG_CRYPTO_TWOFISH is not set\n\n#\n# Compression\n#\n# CONFIG_CRYPTO_DEFLATE is not set\n# CONFIG_CRYPTO_LZO is not set\n# CONFIG_CRYPTO_842 is not set\n# CONFIG_CRYPTO_LZ4 is not set\n# CONFIG_CRYPTO_LZ4HC is not set\n# CONFIG_CRYPTO_ZSTD is not set\n\n#\n# Random Number Generation\n#\n# CONFIG_CRYPTO_ANSI_CPRNG is not set\nCONFIG_CRYPTO_DRBG_MENU=y\nCONFIG_CRYPTO_DRBG_HMAC=y\n# CONFIG_CRYPTO_DRBG_HASH is not set\n# CONFIG_CRYPTO_DRBG_CTR is not set\nCONFIG_CRYPTO_DRBG=y\nCONFIG_CRYPTO_JITTERENTROPY=y\nCONFIG_CRYPTO_USER_API=y\n# CONFIG_CRYPTO_USER_API_HASH is not set\nCONFIG_CRYPTO_USER_API_SKCIPHER=y\n# CONFIG_CRYPTO_USER_API_RNG is not set\n# CONFIG_CRYPTO_USER_API_AEAD is not set\nCONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y\nCONFIG_CRYPTO_HASH_INFO=y\n\n#\n# Crypto library routines\n#\nCONFIG_CRYPTO_LIB_AES=y\nCONFIG_CRYPTO_LIB_ARC4=y\n# CONFIG_CRYPTO_LIB_BLAKE2S is not set\n# CONFIG_CRYPTO_LIB_CHACHA is not set\n# CONFIG_CRYPTO_LIB_CURVE25519 is not set\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=9\n# CONFIG_CRYPTO_LIB_POLY1305 is not set\n# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set\nCONFIG_CRYPTO_LIB_SHA256=y\nCONFIG_CRYPTO_HW=y\n# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set\n# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set\n# CONFIG_CRYPTO_DEV_CCP is not set\n# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set\n# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set\nCONFIG_CRYPTO_DEV_ZYNQMP_KECCAK_384=y\nCONFIG_CRYPTO_DEV_XILINX_RSA=y\nCONFIG_CRYPTO_DEV_ZYNQMP_AES=y\n# CONFIG_CRYPTO_DEV_VIRTIO is not set\n# CONFIG_CRYPTO_DEV_SAFEXCEL is not set\n# CONFIG_CRYPTO_DEV_CCREE is not set\n# CONFIG_CRYPTO_DEV_HISI_SEC is not set\n# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set\nCONFIG_ASYMMETRIC_KEY_TYPE=y\nCONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y\nCONFIG_X509_CERTIFICATE_PARSER=y\n# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set\nCONFIG_PKCS7_MESSAGE_PARSER=y\n# CONFIG_PKCS7_TEST_KEY is not set\n# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set\n\n#\n# Certificates for signature checking\n#\nCONFIG_SYSTEM_TRUSTED_KEYRING=y\nCONFIG_SYSTEM_TRUSTED_KEYS=\"\"\n# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set\n# CONFIG_SECONDARY_TRUSTED_KEYRING is not set\n# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set\n# end of Certificates for signature checking\n\n#\n# Library routines\n#\nCONFIG_RAID6_PQ=y\nCONFIG_RAID6_PQ_BENCHMARK=y\nCONFIG_LINEAR_RANGES=y\n# CONFIG_PACKING is not set\nCONFIG_BITREVERSE=y\nCONFIG_HAVE_ARCH_BITREVERSE=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_NET_UTILS=y\nCONFIG_GENERIC_FIND_FIRST_BIT=y\n# CONFIG_CORDIC is not set\n# CONFIG_PRIME_NUMBERS is not set\nCONFIG_RATIONAL=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_ARCH_USE_CMPXCHG_LOCKREF=y\nCONFIG_ARCH_HAS_FAST_MULTIPLIER=y\nCONFIG_ARCH_USE_SYM_ANNOTATIONS=y\n# CONFIG_INDIRECT_PIO is not set\nCONFIG_CRC_CCITT=y\nCONFIG_CRC16=y\n# CONFIG_CRC_T10DIF is not set\n# CONFIG_CRC_ITU_T is not set\nCONFIG_CRC32=y\n# CONFIG_CRC32_SELFTEST is not set\nCONFIG_CRC32_SLICEBY8=y\n# CONFIG_CRC32_SLICEBY4 is not set\n# CONFIG_CRC32_SARWATE is not set\n# CONFIG_CRC32_BIT is not set\n# CONFIG_CRC64 is not set\n# CONFIG_CRC4 is not set\nCONFIG_CRC7=y\nCONFIG_LIBCRC32C=y\nCONFIG_CRC8=y\nCONFIG_XXHASH=y\nCONFIG_AUDIT_GENERIC=y\nCONFIG_AUDIT_ARCH_COMPAT_GENERIC=y\nCONFIG_AUDIT_COMPAT_GENERIC=y\n# CONFIG_RANDOM32_SELFTEST is not set\nCONFIG_ZLIB_INFLATE=y\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\nCONFIG_LZ4_DECOMPRESS=y\nCONFIG_ZSTD_COMPRESS=y\nCONFIG_ZSTD_DECOMPRESS=y\nCONFIG_XZ_DEC=y\nCONFIG_XZ_DEC_X86=y\nCONFIG_XZ_DEC_POWERPC=y\nCONFIG_XZ_DEC_IA64=y\nCONFIG_XZ_DEC_ARM=y\nCONFIG_XZ_DEC_ARMTHUMB=y\nCONFIG_XZ_DEC_SPARC=y\nCONFIG_XZ_DEC_BCJ=y\n# CONFIG_XZ_DEC_TEST is not set\nCONFIG_DECOMPRESS_GZIP=y\nCONFIG_DECOMPRESS_BZIP2=y\nCONFIG_DECOMPRESS_LZMA=y\nCONFIG_DECOMPRESS_XZ=y\nCONFIG_DECOMPRESS_LZO=y\nCONFIG_DECOMPRESS_LZ4=y\nCONFIG_DECOMPRESS_ZSTD=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_XARRAY_MULTI=y\nCONFIG_ASSOCIATIVE_ARRAY=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HAS_DMA=y\nCONFIG_DMA_OPS=y\nCONFIG_NEED_SG_DMA_LENGTH=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_ARCH_DMA_ADDR_T_64BIT=y\nCONFIG_DMA_DECLARE_COHERENT=y\nCONFIG_ARCH_HAS_SETUP_DMA_OPS=y\nCONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y\nCONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y\nCONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y\nCONFIG_ARCH_HAS_DMA_PREP_COHERENT=y\nCONFIG_SWIOTLB=y\n# CONFIG_DMA_RESTRICTED_POOL is not set\nCONFIG_DMA_NONCOHERENT_MMAP=y\nCONFIG_DMA_COHERENT_POOL=y\nCONFIG_DMA_REMAP=y\nCONFIG_DMA_DIRECT_REMAP=y\nCONFIG_DMA_CMA=y\n# CONFIG_DMA_PERNUMA_CMA is not set\n\n#\n# Default contiguous memory area size:\n#\nCONFIG_CMA_SIZE_MBYTES=256\nCONFIG_CMA_SIZE_SEL_MBYTES=y\n# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set\n# CONFIG_CMA_SIZE_SEL_MIN is not set\n# CONFIG_CMA_SIZE_SEL_MAX is not set\nCONFIG_CMA_ALIGNMENT=8\n# CONFIG_DMA_API_DEBUG is not set\n# CONFIG_DMA_MAP_BENCHMARK is not set\nCONFIG_SGL_ALLOC=y\nCONFIG_CPU_RMAP=y\nCONFIG_DQL=y\nCONFIG_GLOB=y\n# CONFIG_GLOB_SELFTEST is not set\nCONFIG_NLATTR=y\nCONFIG_CLZ_TAB=y\n# CONFIG_IRQ_POLL is not set\nCONFIG_MPILIB=y\nCONFIG_LIBFDT=y\nCONFIG_OID_REGISTRY=y\nCONFIG_UCS2_STRING=y\nCONFIG_HAVE_GENERIC_VDSO=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_VDSO_TIME_NS=y\nCONFIG_FONT_SUPPORT=y\n# CONFIG_FONTS is not set\nCONFIG_FONT_8x8=y\nCONFIG_FONT_8x16=y\nCONFIG_SG_POOL=y\nCONFIG_ARCH_STACKWALK=y\nCONFIG_SBITMAP=y\n# end of Library routines\n\nCONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y\n\n#\n# Kernel hacking\n#\n\n#\n# printk and dmesg options\n#\nCONFIG_PRINTK_TIME=y\n# CONFIG_PRINTK_CALLER is not set\n# CONFIG_STACKTRACE_BUILD_ID is not set\nCONFIG_CONSOLE_LOGLEVEL_DEFAULT=7\nCONFIG_CONSOLE_LOGLEVEL_QUIET=4\nCONFIG_MESSAGE_LOGLEVEL_DEFAULT=4\n# CONFIG_BOOT_PRINTK_DELAY is not set\n# CONFIG_DYNAMIC_DEBUG is not set\n# CONFIG_DYNAMIC_DEBUG_CORE is not set\nCONFIG_SYMBOLIC_ERRNAME=y\nCONFIG_DEBUG_BUGVERBOSE=y\n# end of printk and dmesg options\n\n#\n# Compile-time checks and compiler options\n#\nCONFIG_DEBUG_INFO=y\n# CONFIG_DEBUG_INFO_REDUCED is not set\n# CONFIG_DEBUG_INFO_COMPRESSED is not set\n# CONFIG_DEBUG_INFO_SPLIT is not set\nCONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y\n# CONFIG_DEBUG_INFO_DWARF4 is not set\n# CONFIG_DEBUG_INFO_DWARF5 is not set\n# CONFIG_DEBUG_INFO_BTF is not set\n# CONFIG_GDB_SCRIPTS is not set\nCONFIG_FRAME_WARN=2048\n# CONFIG_STRIP_ASM_SYMS is not set\n# CONFIG_READABLE_ASM is not set\n# CONFIG_HEADERS_INSTALL is not set\n# CONFIG_DEBUG_SECTION_MISMATCH is not set\nCONFIG_SECTION_MISMATCH_WARN_ONLY=y\n# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set\nCONFIG_ARCH_WANT_FRAME_POINTERS=y\nCONFIG_FRAME_POINTER=y\n# CONFIG_VMLINUX_MAP is not set\n# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set\n# end of Compile-time checks and compiler options\n\n#\n# Generic Kernel Debugging Instruments\n#\nCONFIG_MAGIC_SYSRQ=y\nCONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1\nCONFIG_MAGIC_SYSRQ_SERIAL=y\nCONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=\"\"\nCONFIG_DEBUG_FS=y\nCONFIG_DEBUG_FS_ALLOW_ALL=y\n# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set\n# CONFIG_DEBUG_FS_ALLOW_NONE is not set\nCONFIG_HAVE_ARCH_KGDB=y\n# CONFIG_KGDB is not set\nCONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y\n# CONFIG_UBSAN is not set\n# end of Generic Kernel Debugging Instruments\n\nCONFIG_DEBUG_KERNEL=y\nCONFIG_DEBUG_MISC=y\n\n#\n# Memory Debugging\n#\n# CONFIG_PAGE_EXTENSION is not set\n# CONFIG_DEBUG_PAGEALLOC is not set\n# CONFIG_PAGE_OWNER is not set\n# CONFIG_PAGE_POISONING is not set\n# CONFIG_DEBUG_RODATA_TEST is not set\nCONFIG_ARCH_HAS_DEBUG_WX=y\n# CONFIG_DEBUG_WX is not set\nCONFIG_GENERIC_PTDUMP=y\n# CONFIG_PTDUMP_DEBUGFS is not set\n# CONFIG_DEBUG_OBJECTS is not set\n# CONFIG_DEBUG_SLAB is not set\nCONFIG_HAVE_DEBUG_KMEMLEAK=y\n# CONFIG_DEBUG_KMEMLEAK is not set\n# CONFIG_DEBUG_STACK_USAGE is not set\n# CONFIG_SCHED_STACK_END_CHECK is not set\nCONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y\n# CONFIG_DEBUG_VM is not set\n# CONFIG_DEBUG_VM_PGTABLE is not set\nCONFIG_ARCH_HAS_DEBUG_VIRTUAL=y\n# CONFIG_DEBUG_VIRTUAL is not set\n# CONFIG_DEBUG_MEMORY_INIT is not set\n# CONFIG_DEBUG_PER_CPU_MAPS is not set\nCONFIG_HAVE_ARCH_KASAN=y\nCONFIG_HAVE_ARCH_KASAN_SW_TAGS=y\nCONFIG_HAVE_ARCH_KASAN_HW_TAGS=y\nCONFIG_HAVE_ARCH_KASAN_VMALLOC=y\nCONFIG_CC_HAS_KASAN_GENERIC=y\nCONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y\n# CONFIG_KASAN is not set\nCONFIG_HAVE_ARCH_KFENCE=y\n# CONFIG_KFENCE is not set\n# end of Memory Debugging\n\n# CONFIG_DEBUG_SHIRQ is not set\n\n#\n# Debug Oops, Lockups and Hangs\n#\n# CONFIG_PANIC_ON_OOPS is not set\nCONFIG_PANIC_ON_OOPS_VALUE=0\nCONFIG_PANIC_TIMEOUT=0\n# CONFIG_SOFTLOCKUP_DETECTOR is not set\n# CONFIG_DETECT_HUNG_TASK is not set\n# CONFIG_WQ_WATCHDOG is not set\n# CONFIG_TEST_LOCKUP is not set\n# end of Debug Oops, Lockups and Hangs\n\n#\n# Scheduler Debugging\n#\n# CONFIG_SCHED_DEBUG is not set\nCONFIG_SCHED_INFO=y\n# CONFIG_SCHEDSTATS is not set\n# end of Scheduler Debugging\n\n# CONFIG_DEBUG_TIMEKEEPING is not set\n\n#\n# Lock Debugging (spinlocks, mutexes, etc...)\n#\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\n# CONFIG_PROVE_LOCKING is not set\n# CONFIG_LOCK_STAT is not set\n# CONFIG_DEBUG_RT_MUTEXES is not set\n# CONFIG_DEBUG_SPINLOCK is not set\n# CONFIG_DEBUG_MUTEXES is not set\n# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set\n# CONFIG_DEBUG_RWSEMS is not set\n# CONFIG_DEBUG_LOCK_ALLOC is not set\n# CONFIG_DEBUG_ATOMIC_SLEEP is not set\n# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set\n# CONFIG_LOCK_TORTURE_TEST is not set\n# CONFIG_WW_MUTEX_SELFTEST is not set\n# CONFIG_SCF_TORTURE_TEST is not set\n# CONFIG_CSD_LOCK_WAIT_DEBUG is not set\n# end of Lock Debugging (spinlocks, mutexes, etc...)\n\n# CONFIG_DEBUG_IRQFLAGS is not set\n# CONFIG_STACKTRACE is not set\n# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set\n# CONFIG_DEBUG_KOBJECT is not set\n\n#\n# Debug kernel data structures\n#\n# CONFIG_DEBUG_LIST is not set\n# CONFIG_DEBUG_PLIST is not set\n# CONFIG_DEBUG_SG is not set\n# CONFIG_DEBUG_NOTIFIERS is not set\n# CONFIG_BUG_ON_DATA_CORRUPTION is not set\n# end of Debug kernel data structures\n\n# CONFIG_DEBUG_CREDENTIALS is not set\n\n#\n# RCU Debugging\n#\n# CONFIG_RCU_SCALE_TEST is not set\n# CONFIG_RCU_TORTURE_TEST is not set\n# CONFIG_RCU_REF_SCALE_TEST is not set\nCONFIG_RCU_CPU_STALL_TIMEOUT=21\nCONFIG_RCU_TRACE=y\n# CONFIG_RCU_EQS_DEBUG is not set\n# end of RCU Debugging\n\n# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set\n# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set\n# CONFIG_LATENCYTOP is not set\nCONFIG_HAVE_FUNCTION_TRACER=y\nCONFIG_HAVE_FUNCTION_GRAPH_TRACER=y\nCONFIG_HAVE_DYNAMIC_FTRACE=y\nCONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y\nCONFIG_HAVE_FTRACE_MCOUNT_RECORD=y\nCONFIG_HAVE_SYSCALL_TRACEPOINTS=y\nCONFIG_HAVE_C_RECORDMCOUNT=y\nCONFIG_TRACE_CLOCK=y\nCONFIG_TRACING_SUPPORT=y\n# CONFIG_FTRACE is not set\n# CONFIG_SAMPLES is not set\nCONFIG_STRICT_DEVMEM=y\n# CONFIG_IO_STRICT_DEVMEM is not set\n\n#\n# arm64 Debugging\n#\n# CONFIG_PID_IN_CONTEXTIDR is not set\n# CONFIG_DEBUG_EFI is not set\n# CONFIG_ARM64_RELOC_TEST is not set\n# CONFIG_CORESIGHT is not set\n# end of arm64 Debugging\n\n#\n# Kernel Testing and Coverage\n#\n# CONFIG_KUNIT is not set\n# CONFIG_NOTIFIER_ERROR_INJECTION is not set\n# CONFIG_FAULT_INJECTION is not set\nCONFIG_ARCH_HAS_KCOV=y\nCONFIG_CC_HAS_SANCOV_TRACE_PC=y\n# CONFIG_KCOV is not set\nCONFIG_RUNTIME_TESTING_MENU=y\n# CONFIG_LKDTM is not set\n# CONFIG_TEST_MIN_HEAP is not set\n# CONFIG_TEST_DIV64 is not set\n# CONFIG_BACKTRACE_SELF_TEST is not set\n# CONFIG_RBTREE_TEST is not set\n# CONFIG_REED_SOLOMON_TEST is not set\n# CONFIG_INTERVAL_TREE_TEST is not set\n# CONFIG_PERCPU_TEST is not set\n# CONFIG_ATOMIC64_SELFTEST is not set\n# CONFIG_TEST_HEXDUMP is not set\n# CONFIG_STRING_SELFTEST is not set\n# CONFIG_TEST_STRING_HELPERS is not set\n# CONFIG_TEST_STRSCPY is not set\n# CONFIG_TEST_KSTRTOX is not set\n# CONFIG_TEST_PRINTF is not set\n# CONFIG_TEST_SCANF is not set\n# CONFIG_TEST_BITMAP is not set\n# CONFIG_TEST_UUID is not set\n# CONFIG_TEST_XARRAY is not set\n# CONFIG_TEST_OVERFLOW is not set\n# CONFIG_TEST_RHASHTABLE is not set\n# CONFIG_TEST_HASH is not set\n# CONFIG_TEST_IDA is not set\n# CONFIG_TEST_LKM is not set\n# CONFIG_TEST_BITOPS is not set\n# CONFIG_TEST_VMALLOC is not set\n# CONFIG_TEST_USER_COPY is not set\n# CONFIG_TEST_BPF is not set\n# CONFIG_TEST_BLACKHOLE_DEV is not set\n# CONFIG_FIND_BIT_BENCHMARK is not set\n# CONFIG_TEST_FIRMWARE is not set\n# CONFIG_TEST_SYSCTL is not set\n# CONFIG_TEST_UDELAY is not set\n# CONFIG_TEST_STATIC_KEYS is not set\n# CONFIG_TEST_KMOD is not set\n# CONFIG_TEST_MEMCAT_P is not set\n# CONFIG_TEST_STACKINIT is not set\n# CONFIG_TEST_MEMINIT is not set\n# CONFIG_TEST_FREE_PAGES is not set\nCONFIG_ARCH_USE_MEMTEST=y\n# CONFIG_MEMTEST is not set\n# end of Kernel Testing and Coverage\n# end of Kernel hacking\n"
  },
  {
    "path": "kernel_boot/kernel_patch_readme.md",
    "content": "axi_hdmi_crtc.patch to avoid axi hdmi compiling error after enable Xilinx axi dma.\n\nad9361.patch to expose some APIs for openwifi driver and add one register write for AGC setting.\n\nad9361_private.patch to add bool for missing AGC setting.\n\nad9361_conv.patch to avoid 61.44Msps lvds interface self timing calibration for some low-end/bad hardware (sometimes difficult).\n\n"
  },
  {
    "path": "openwifi-arch.jpg.license",
    "content": "\n# Author: Xianjun jiao\n\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n"
  },
  {
    "path": "user_space/agc_settings.sh",
    "content": "#!/bin/bash\n\nif [ \"$#\" -ne 1 ]; then\n    echo \"You must enter 1 to apply new settings or 0 to restore default settings\"\n    exit 1\nfi\n\nset -x\nif test -f \"/sys/kernel/debug/iio/iio:device0/direct_reg_access\"; then\n  cd /sys/kernel/debug/iio/iio:device0/\nelse if test -f \"/sys/kernel/debug/iio/iio:device1/direct_reg_access\"; then\n       cd /sys/kernel/debug/iio/iio:device1/\n     else if test -f \"/sys/kernel/debug/iio/iio:device2/direct_reg_access\"; then\n            cd /sys/kernel/debug/iio/iio:device2/\n          else if test -f \"/sys/kernel/debug/iio/iio:device3/direct_reg_access\"; then\n                 cd /sys/kernel/debug/iio/iio:device3/\n               else if test -f \"/sys/kernel/debug/iio/iio:device4/direct_reg_access\"; then\n                      cd /sys/kernel/debug/iio/iio:device4/\n                    else\n                      echo \"Can not find direct_reg_access!\"\n                      echo \"Check log to make sure ad9361 driver is loaded!\"\n                      exit 1\n                    fi\n               fi\n          fi\n     fi\nfi\nset +x\n\nif [ $1 == \"0\" ]; then \n  echo 0x15C 0x72 > direct_reg_access\n  echo 0x106 0x72 > direct_reg_access\n  echo 0x103 0x08 > direct_reg_access\n  echo 0x101 0x0A > direct_reg_access\n  echo 0x110 0x40 > direct_reg_access\n  echo 0x115 0x00 > direct_reg_access\n  echo 0x10A 0x58 > direct_reg_access\n  echo \"Applied default AGC settings\"\nelif [ $1 == \"1\" ]; then\n  echo 0x15C 0x70 > direct_reg_access \n  echo 0x106 0x77 > direct_reg_access\n  echo 0x103 0x1C > direct_reg_access\n  echo 0x101 0x0C > direct_reg_access\n  echo 0x110 0x48 > direct_reg_access\n# DO NOT change 0x48 to 0x4A! Otherwise: did not acknowledge authentication response\n  echo 0x114 0xb0 > direct_reg_access\n#  0x30 is the original value for register 0x114\n  echo 0x115 0x80 > direct_reg_access\n  echo 0x10A 0x18 > direct_reg_access\n  echo \"Applied optimized AGC settings\"\nfi\n\n# #Due to https://github.ugent.be/xjiao/openwifi/issues/148\necho 0x0fa 0x5 > direct_reg_access\necho 0x0fa 0xE5 > direct_reg_access\n"
  },
  {
    "path": "user_space/arbitrary_iq_gen/iq_single_carrier_1000000Hz_512.txt",
    "content": "16311,1542\n15036,6507\n12290,10835\n8340,14102\n3574,15989\n-1542,16311\n-6507,15036\n-10835,12290\n-14102,8340\n-15989,3574\n-16311,-1542\n-15036,-6507\n-12290,-10835\n-8340,-14102\n-3574,-15989\n1542,-16311\n6507,-15036\n10835,-12290\n14102,-8340\n15989,-3574\n16311,1542\n15036,6507\n12290,10835\n8340,14102\n3574,15989\n-1542,16311\n-6507,15036\n-10835,12290\n-14102,8340\n-15989,3574\n-16311,-1542\n-15036,-6507\n-12290,-10835\n-8340,-14102\n-3574,-15989\n1542,-16311\n6507,-15036\n10835,-12290\n14102,-8340\n15989,-3574\n16311,1542\n15036,6507\n12290,10835\n8340,14102\n3574,15989\n-1542,16311\n-6507,15036\n-10835,12290\n-14102,8340\n-15989,3574\n-16311,-1542\n-15036,-6507\n-12290,-10835\n-8340,-14102\n-3574,-15989\n1542,-16311\n6507,-15036\n10835,-12290\n14102,-8340\n15989,-3574\n16311,1542\n15036,6507\n12290,10835\n8340,14102\n3574,15989\n-1542,16311\n-6507,15036\n-10835,12290\n-14102,8340\n-15989,3574\n-16311,-1542\n-15036,-6507\n-12290,-10835\n-8340,-14102\n-3574,-15989\n1542,-16311\n6507,-15036\n10835,-12290\n14102,-8340\n15989,-3574\n16311,1542\n15036,6507\n12290,10835\n8340,14102\n3574,15989\n-1542,16311\n-6507,15036\n-10835,12290\n-14102,8340\n-15989,3574\n-16311,-1542\n-15036,-6507\n-12290,-10835\n-8340,-14102\n-3574,-15989\n1542,-16311\n6507,-15036\n10835,-12290\n14102,-8340\n15989,-3574\n16311,1542\n15036,6507\n12290,10835\n8340,14102\n3574,15989\n-1542,16311\n-6507,15036\n-10835,12290\n-14102,8340\n-15989,3574\n-16311,-1542\n-15036,-6507\n-12290,-10835\n-8340,-14102\n-3574,-15989\n1542,-16311\n6507,-15036\n10835,-12290\n14102,-8340\n15989,-3574\n16311,1542\n15036,6507\n12290,10835\n8340,14102\n3574,15989\n-1542,16311\n-6507,15036\n-10835,12290\n-14102,8340\n-15989,3574\n-16311,-1542\n-15036,-6507\n-12290,-10835\n-8340,-14102\n-3574,-15989\n1542,-16311\n6507,-15036\n10835,-12290\n14102,-8340\n15989,-3574\n16311,1542\n15036,6507\n12290,10835\n8340,14102\n3574,15989\n-1542,16311\n-6507,15036\n-10835,12290\n-14102,8340\n-15989,3574\n-16311,-1542\n-15036,-6507\n-12290,-10835\n-8340,-14102\n-3574,-15989\n1542,-16311\n6507,-15036\n10835,-12290\n14102,-8340\n15989,-3574\n16311,1542\n15036,6507\n12290,10835\n8340,14102\n3574,15989\n-1542,16311\n-6507,15036\n-10835,12290\n-14102,8340\n-15989,3574\n-16311,-1542\n-15036,-6507\n-12290,-10835\n-8340,-14102\n-3574,-15989\n1542,-16311\n6507,-15036\n10835,-12290\n14102,-8340\n15989,-3574\n16311,1542\n15036,6507\n12290,10835\n8340,14102\n3574,15989\n-1542,16311\n-6507,15036\n-10835,12290\n-14102,8340\n-15989,3574\n-16311,-1542\n-15036,-6507\n-12290,-10835\n-8340,-14102\n-3574,-15989\n1542,-16311\n6507,-15036\n10835,-12290\n14102,-8340\n15989,-3574\n16311,1542\n15036,6507\n12290,10835\n8340,14102\n3574,15989\n-1542,16311\n-6507,15036\n-10835,12290\n-14102,8340\n-15989,3574\n-16311,-1542\n-15036,-6507\n-12290,-10835\n-8340,-14102\n-3574,-15989\n1542,-16311\n6507,-15036\n10835,-12290\n14102,-8340\n15989,-3574\n16311,1542\n15036,6507\n12290,10835\n8340,14102\n3574,15989\n-1542,16311\n-6507,15036\n-10835,12290\n-14102,8340\n-15989,3574\n-16311,-1542\n-15036,-6507\n-12290,-10835\n-8340,-14102\n-3574,-15989\n1542,-16311\n6507,-15036\n10835,-12290\n14102,-8340\n15989,-3574\n16311,1542\n15036,6507\n12290,10835\n8340,14102\n3574,15989\n-1542,16311\n-6507,15036\n-10835,12290\n-14102,8340\n-15989,3574\n-16311,-1542\n-15036,-6507\n-12290,-10835\n-8340,-14102\n-3574,-15989\n1542,-16311\n6507,-15036\n10835,-12290\n14102,-8340\n15989,-3574\n16311,1542\n15036,6507\n12290,10835\n8340,14102\n3574,15989\n-1542,16311\n-6507,15036\n-10835,12290\n-14102,8340\n-15989,3574\n-16311,-1542\n-15036,-6507\n-12290,-10835\n-8340,-14102\n-3574,-15989\n1542,-16311\n6507,-15036\n10835,-12290\n14102,-8340\n15989,-3574\n16311,1542\n15036,6507\n12290,10835\n8340,14102\n3574,15989\n-1542,16311\n-6507,15036\n-10835,12290\n-14102,8340\n-15989,3574\n-16311,-1542\n-15036,-6507\n-12290,-10835\n-8340,-14102\n-3574,-15989\n1542,-16311\n6507,-15036\n10835,-12290\n14102,-8340\n15989,-3574\n16311,1542\n15036,6507\n12290,10835\n8340,14102\n3574,15989\n-1542,16311\n-6507,15036\n-10835,12290\n-14102,8340\n-15989,3574\n-16311,-1542\n-15036,-6507\n-12290,-10835\n-8340,-14102\n-3574,-15989\n1542,-16311\n6507,-15036\n10835,-12290\n14102,-8340\n15989,-3574\n16311,1542\n15036,6507\n12290,10835\n8340,14102\n3574,15989\n-1542,16311\n-6507,15036\n-10835,12290\n-14102,8340\n-15989,3574\n-16311,-1542\n-15036,-6507\n-12290,-10835\n-8340,-14102\n-3574,-15989\n1542,-16311\n6507,-15036\n10835,-12290\n14102,-8340\n15989,-3574\n16311,1542\n15036,6507\n12290,10835\n8340,14102\n3574,15989\n-1542,16311\n-6507,15036\n-10835,12290\n-14102,8340\n-15989,3574\n-16311,-1542\n-15036,-6507\n-12290,-10835\n-8340,-14102\n-3574,-15989\n1542,-16311\n6507,-15036\n10835,-12290\n14102,-8340\n15989,-3574\n16311,1542\n15036,6507\n12290,10835\n8340,14102\n3574,15989\n-1542,16311\n-6507,15036\n-10835,12290\n-14102,8340\n-15989,3574\n-16311,-1542\n-15036,-6507\n-12290,-10835\n-8340,-14102\n-3574,-15989\n1542,-16311\n6507,-15036\n10835,-12290\n14102,-83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  },
  {
    "path": "user_space/arbitrary_iq_gen/single_carrier_gen.m",
    "content": "% Author: Xianjun Jiao (xianjun.jiao@imec.be; putaoshu@msn.com)\n% SPDX-FileCopyrightText: 2023 UGent\n% SPDX-License-Identifier: AGPL-3.0-or-later\n\nfunction single_carrier_gen(carrier_freq, num_iq)\nif exist('carrier_freq', 'var')==0 || isempty(carrier_freq)\n  carrier_freq = 1e6;\nend\n\nif exist('num_iq', 'var')==0 || isempty(num_iq)\n  num_iq = 512;\nend\n\nsampling_rate = 20e6;\nsampling_time = 1/sampling_rate;\nt = (0.3+(0:(num_iq-1))).*sampling_time;\ns = exp(2.*pi.*carrier_freq.*t.*1i);\n\n%let's use 14 bits \nreal_part = round(real(s).*(2^14));\nimag_part = round(imag(s).*(2^14));\n\nfilename = ['iq_single_carrier_' num2str(carrier_freq) 'Hz_' num2str(num_iq) '.txt'];\nfid = fopen(filename,'w');\nif fid == -1\n    disp('fopen failed');\n    return;\nend\nlen = length(s);\nfor j=1:len\n    fprintf(fid, '%d,%d\\n', real_part(j), imag_part(j));\nend\nfclose(fid);\ndisp(['Saved to ' filename]); \n\nfilename = ['iq_single_carrier_' num2str(carrier_freq) 'Hz_' num2str(num_iq) '.bin'];\nfid = fopen(filename,'w');\nif fid == -1\n    disp('fopen error');\n    return;\nend\n\niq_int16 = [real_part; imag_part];\niq_int16 = iq_int16(:);\n\nfwrite(fid, iq_int16, 'int16');\nfclose(fid);\ndisp(['Saved to ' filename]); \n"
  },
  {
    "path": "user_space/boot_bin_gen.sh",
    "content": "#!/bin/bash\n\n# Author: Xianjun Jiao\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\nif [ \"$#\" -ne 3 ]; then\n    echo \"You must enter exactly 3 arguments: \\$XILINX_DIR \\$BOARD_NAME DIR_TO_filename.xsa\"\n    exit 1\nfi\n\nXILINX_DIR=$1\nBOARD_NAME=$2\nXSA_FILE=$3\n\nOPENWIFI_DIR=$(pwd)/../\n\necho OPENWIFI_DIR $OPENWIFI_DIR\necho XSA_FILE $XSA_FILE\n\nif [ -f \"$OPENWIFI_DIR/LICENSE\" ]; then\n    echo \"$OPENWIFI_DIR is found!\"\nelse\n    echo \"$OPENWIFI_DIR is not correct. Please check!\"\n    exit 1\nfi\n\nXILINX_ENV_FILE=$XILINX_DIR/Vitis/2022.2/settings64.sh\necho \"Expect env file $XILINX_ENV_FILE\"\n\nif [ -f \"$XILINX_ENV_FILE\" ]; then\n    echo \"$XILINX_ENV_FILE is found!\"\nelse\n    echo \"$XILINX_ENV_FILE is not correct. Please check!\"\n    exit 1\nfi\n\n# if [ \"$BOARD_NAME\" != \"antsdr\" ] && [ \"$BOARD_NAME\" != \"zc706_fmcs2\" ] && [ \"$BOARD_NAME\" != \"zc702_fmcs2\" ] && [ \"$BOARD_NAME\" != \"zed_fmcs2\" ] && [ \"$BOARD_NAME\" != \"adrv9361z7035\" ] && [ \"$BOARD_NAME\" != \"adrv9364z7020\" ]; then\n#     echo \"$BOARD_NAME is not correct. Please check!\"\n#     exit 1\n# else\n#     echo \"$BOARD_NAME is found!\"\n# fi\n\nif [ -f \"$XSA_FILE\" ]; then\n    echo \"$XSA_FILE is found!\"\nelse\n    echo \"$XSA_FILE is not found. Please check!\"\n    exit 1\nfi\n\nhome_dir=$(pwd)\n\nset -ex\n\nsource $XILINX_ENV_FILE\n\ncd $OPENWIFI_DIR/kernel_boot\n\nif [ \"$BOARD_NAME\" == \"zcu102_fmcs2\" ] || [ \"$BOARD_NAME\" == \"zcu102_9371\" ]; then\n  ./build_zynqmp_boot_bin.sh $XSA_FILE boards/$BOARD_NAME/u-boot_xilinx_zynqmp_zcu102_revA.elf boards/$BOARD_NAME/bl31.elf\n  ARCH=\"zynqmp\"\n  ARCH_BIT=64\nelif [ \"$BOARD_NAME\" == \"antsdr\" ] || [ \"$BOARD_NAME\" == \"antsdr_e200\" ] || [ \"$BOARD_NAME\" == \"e310v2\" ] || [ \"$BOARD_NAME\" == \"sdrpi\" ] || [ \"$BOARD_NAME\" == \"neptunesdr\" ] || [ \"$BOARD_NAME\" == \"zc706_fmcs2\" ] || [ \"$BOARD_NAME\" == \"zc702_fmcs2\" ] || [ \"$BOARD_NAME\" == \"zed_fmcs2\" ] || [ \"$BOARD_NAME\" == \"adrv9361z7035\" ] || [ \"$BOARD_NAME\" == \"adrv9364z7020\" ]; then\n  ./build_boot_bin.sh $XSA_FILE boards/$BOARD_NAME/u-boot.elf\n  ARCH=\"zynq\"\n  ARCH_BIT=32\nelse\n  echo \"$BOARD_NAME is not correct. Please check!\"\n  cd $home_dir\n  exit 1\nfi\n\nrm -rf build_boot_bin\nrm -rf boards/$BOARD_NAME/output_boot_bin\nmv output_boot_bin boards/$BOARD_NAME/\n\ncd $home_dir\n\n### Get basename of xsa and bit file\nXSA_FILE_BASENAME=\"$(basename $XSA_FILE)\"\nXSA_FILE_BASENAME_WO_EXT=\"$(basename $XSA_FILE .xsa)\"\nBIT_FILE_BASENAME=\"$XSA_FILE_BASENAME_WO_EXT.bit\"\n\n# generate $BIT_FILE_BASENAME.bin for FPGA dynamic loading\n\necho \"all:\" > ./fpga_bit_to_bin.bif\necho \"{\" >> ./fpga_bit_to_bin.bif\necho \"$BIT_FILE_BASENAME /* Bitstream file name */\" >> ./fpga_bit_to_bin.bif\necho \"}\" >> ./fpga_bit_to_bin.bif\n\nunzip -o $XSA_FILE\nrm -rf ./$BIT_FILE_BASENAME.bin\nbootgen -image fpga_bit_to_bin.bif -arch $ARCH -process_bitstream bin -w\nls ./$BIT_FILE_BASENAME.bin -al\n"
  },
  {
    "path": "user_space/build_wpa_supplicant_wo11b.sh",
    "content": "#!/bin/bash\n\n# Author: Michael Mehari\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\n# if [ \"$#\" -ne 1 ]; then\n#     echo \"You must enter exactly 1 arguments: \\$OPENWIFI_DIR\"\n#     exit 1\n# fi\n\nOPENWIFI_DIR=$(pwd)/../\n\nset -x\n\ncd $OPENWIFI_DIR/user_space\nwget http://w1.fi/releases/wpa_supplicant-2.1.tar.gz\ntar xzvf wpa_supplicant-2.1.tar.gz\npatch -d wpa_supplicant-2.1/src/drivers/ < driver_nl80211.patch\ncd wpa_supplicant-2.1/wpa_supplicant/\ncp defconfig .config\nsed -i 's/#CONFIG_LIBNL32.*/CONFIG_LIBNL32=y/g' .config\nmake -j16\n# sudo make install\ncd ../../\nrm -r wpa_supplicant-2.1/ wpa_supplicant-2.1.tar.gz\n"
  },
  {
    "path": "user_space/cd_adi_iio_dir.sh",
    "content": "#!/bin/sh\n\n# Author: Xianjun Jiao\n# SPDX-FileCopyrightText: 2022 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\nset -x\nif test -f \"/sys/bus/iio/devices/iio:device0/in_voltage_rf_bandwidth\"; then\n  cd /sys/bus/iio/devices/iio:device0/\nelse if test -f \"/sys/bus/iio/devices/iio:device1/in_voltage_rf_bandwidth\"; then\n       cd /sys/bus/iio/devices/iio:device1/\n     else if test -f \"/sys/bus/iio/devices/iio:device2/in_voltage_rf_bandwidth\"; then\n            cd /sys/bus/iio/devices/iio:device2/\n          else if test -f \"/sys/bus/iio/devices/iio:device3/in_voltage_rf_bandwidth\"; then\n                 cd /sys/bus/iio/devices/iio:device3/\n               else if test -f \"/sys/bus/iio/devices/iio:device4/in_voltage_rf_bandwidth\"; then\n                      cd /sys/bus/iio/devices/iio:device4/\n                    else\n                      echo \"Can not find in_voltage_rf_bandwidth!\"\n                      echo \"Check log to make sure ad9361 driver is loaded!\"\n                      exit 1\n                    fi\n               fi\n          fi\n     fi\nfi\nset +x \n"
  },
  {
    "path": "user_space/check_calib_inf.sh",
    "content": "#!/bin/bash\n\nset -x\nif test -f \"/sys/kernel/debug/iio/iio:device0/direct_reg_access\"; then\n  device_path=/sys/kernel/debug/iio/iio:device0/\nelse if test -f \"/sys/kernel/debug/iio/iio:device1/direct_reg_access\"; then\n       device_path=/sys/kernel/debug/iio/iio:device1/\n     else if test -f \"/sys/kernel/debug/iio/iio:device2/direct_reg_access\"; then\n            device_path=/sys/kernel/debug/iio/iio:device2/\n          else if test -f \"/sys/kernel/debug/iio/iio:device3/direct_reg_access\"; then\n                 device_path=/sys/kernel/debug/iio/iio:device3/\n               else if test -f \"/sys/kernel/debug/iio/iio:device4/direct_reg_access\"; then\n                      device_path=/sys/kernel/debug/iio/iio:device4/\n                    else\n                      echo \"Check log to make sure ad9361 driver is loaded!\"\n                      exit 1\n                    fi\n               fi\n          fi\n     fi\nfi\nset +x\n\n(bash -c 'echo $PPID' > /tmp/check_calib_inf.pid\nwhile true; do\n\techo 0x0A7 > ${device_path}direct_reg_access\n\tstatus=$( cat ${device_path}direct_reg_access )\n\tif [ $status == \"0xFF\" ]; then\n\t\techo \"WARNING: Tx Quadrature Calibration failed.\"\n\tfi\n\tsleep 5\ndone) &\n\n"
  },
  {
    "path": "user_space/csi_fuzzer.sh",
    "content": "  \n#!/bin/bash\n\n# Author: Xianjun Jiao\n# SPDX-FileCopyrightText: 2021 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\nif [ \"$#\" -lt 4 ]; then\n    echo \"You must enter 4 arguments: c1_rot90_en c1_raw(-64 to 63) c2_rot90_en c2_raw(-64 to 63)\"\n    exit 1\nfi\n\nc1_rot90_en=$1\nc1_raw=$2\nc2_rot90_en=$3\nc2_raw=$4\n\nif (($c1_rot90_en != 0)) && (($c1_rot90_en != 1)); then\n    echo \"c1_rot90_en must be 0 or 1!\"\n    exit 1\nfi\n\nif (($c1_raw < -64)) || (($c1_raw > 63)); then\n    echo \"c1_raw must be -64 to 63!\"\n    exit 1\nfi\n\nif (($c2_rot90_en != 0)) && (($c2_rot90_en != 1)); then\n    echo \"c2_rot90_en must be 0 or 1!\"\n    exit 1\nfi\n\nif (($c2_raw < -64)) || (($c2_raw > 63)); then\n    echo \"c2_raw must be -64 to 63!\"\n    exit 1\nfi\n\nif (($c1_raw < 0)); then\n    unsigned_c1=$(expr 128 + $c1_raw)\n#    echo $unsigned_c1\nelse\n    unsigned_c1=$c1_raw\nfi\n\nif (($c2_raw < 0)); then\n    unsigned_c2=$(expr 128 + $c2_raw)\n#    echo $unsigned_c2\nelse\n    unsigned_c2=$c2_raw\nfi\n\n# echo $c1_rot90_en\n# echo $unsigned_c1\n# echo $c2_rot90_en\n# echo $unsigned_c2\n\nunsigned_dec_combined=$(($unsigned_c1 + 512 * $c1_rot90_en + 1024 * $unsigned_c2 + 524288 * $c2_rot90_en))\n# echo $unsigned_dec_combined\n\necho \"./sdrctl dev sdr0 set reg tx_intf 5 $unsigned_dec_combined\"\n./sdrctl dev sdr0 set reg tx_intf 5 $unsigned_dec_combined\n"
  },
  {
    "path": "user_space/csi_fuzzer_scan.sh",
    "content": "#!/bin/bash\n\n# Author: Xianjun Jiao\n# SPDX-FileCopyrightText: 2021 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\nif [ \"$#\" -lt 1 ]; then\n    echo \"You must enter 1 arguments: 1, 2, 3 or 4. For scan c1, c2, c2&c1 or c1&c2,\"\n    exit 1\nfi\n\nSCAN_OPTION=$1\n\nif (($SCAN_OPTION == 1)); then\n    echo \"Scan tap1:\"\n    for j in {-64..63};\n    do\n        for i in {-64..63};\n        do\n            ./csi_fuzzer.sh 0 $i 0 0\n            sleep 0.01\n        done\n        for i in {-64..63};\n        do\n            ./csi_fuzzer.sh 1 $i 0 0\n            sleep 0.01\n        done\n    done\n    exit 1\nfi\n\nif (($SCAN_OPTION == 2)); then\n    echo \"Scan tap2:\"\n    for j in {-64..63};\n    do\n        for i in {-64..63};\n        do\n            ./csi_fuzzer.sh 0 0 0 $i\n            sleep 0.01\n        done\n        for i in {-64..63};\n        do\n            ./csi_fuzzer.sh 0 0 1 $i\n            sleep 0.01\n        done\n    done\n    exit 1\nfi\n\nif (($SCAN_OPTION == 3)); then\n    echo \"Scan tap1 after tap2:\"\n    for j in {-64..63};\n    do\n        for i in {-64..63};\n        do\n            ./csi_fuzzer.sh 0 $j 0 $i\n            # sleep 0.1\n        done\n        for i in {-64..63};\n        do\n            ./csi_fuzzer.sh 0 $j 1 $i\n            # sleep 0.1\n        done\n    done\n    for j in {-64..63};\n    do\n        for i in {-64..63};\n        do\n            ./csi_fuzzer.sh 1 $j 0 $i\n            # sleep 0.1\n        done\n        for i in {-64..63};\n        do\n            ./csi_fuzzer.sh 1 $j 1 $i\n            # sleep 0.1\n        done\n    done\n    exit 1\nfi\n\nif (($SCAN_OPTION == 4)); then\n    echo \"Scan tap2 after tap1:\"\n    for j in {-64..63};\n    do\n        for i in {-64..63};\n        do\n            ./csi_fuzzer.sh 0 $i 0 $j\n            # sleep 0.1\n        done\n        for i in {-64..63};\n        do\n            ./csi_fuzzer.sh 1 $i 0 $j\n            # sleep 0.1\n        done\n    done\n    for j in {-64..63};\n    do\n        for i in {-64..63};\n        do\n            ./csi_fuzzer.sh 0 $i 1 $j\n            # sleep 0.1\n        done\n        for i in {-64..63};\n        do\n            ./csi_fuzzer.sh 1 $i 1 $j\n            # sleep 0.1\n        done\n    done\n    exit 1\nfi\n"
  },
  {
    "path": "user_space/cw_disable.sh",
    "content": "#!/bin/bash\n\nhome_dir=$(pwd)\n\nif test -d \"/sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\"; then\n  cd /sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\nelse \n  cd /sys/devices/soc0/fpga-axi\\@0/fpga-axi\\@0\\:sdr\nfi\n\nset -x\n#set\nif [[ -n $1 ]]; then\n  echo \"3$1\" > csma_cfg0\nfi\n\n# show\ncat csma_cfg0\nset +x\n\ncd $home_dir\n"
  },
  {
    "path": "user_space/cw_max_min_cfg.sh",
    "content": "#!/bin/bash\n\nhome_dir=$(pwd)\n\nif test -d \"/sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\"; then\n  cd /sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\nelse \n  cd /sys/devices/soc0/fpga-axi\\@0/fpga-axi\\@0\\:sdr\nfi\n\nset -x\n#set\nif [[ -n $1 ]]; then\n  echo \"$1\" > cw_max_min_cfg\nfi\n\n# show\ncat cw_max_min_cfg\nset +x\n\ncd $home_dir"
  },
  {
    "path": "user_space/dhcpd.conf",
    "content": "#\n# Sample configuration file for ISC dhcpd for Debian\n#\n# Attention: If /etc/ltsp/dhcpd.conf exists, that will be used as\n# configuration file instead of this file.\n#\n#\n\n# The ddns-updates-style parameter controls whether or not the server will\n# attempt to do a DNS update when a lease is confirmed. We default to the\n# behavior of the version 2 packages ('none', since DHCP v2 didn't\n# have support for DDNS.)\nddns-update-style none;\n\n# option definitions common to all supported networks...\n# option domain-name \"orca-project.eu\";\n#option domain-name-servers ns1.example.org, ns2.example.org;\n\ndefault-lease-time 600;\nmax-lease-time 7200;\n\n# If this DHCP server is the official DHCP server for the local\n# network, the authoritative directive should be uncommented.\n#authoritative;\n\n# Use this to send dhcp log messages to a different log file (you also\n# have to hack syslog.conf to complete the redirection).\nlog-facility local7;\n\n# No service will be given on this subnet, but declaring it helps the \n# DHCP server to understand the network topology.\n\noption subnet-mask 255.255.255.0;\noption broadcast-address 192.168.13.255;\noption routers 192.168.13.1;\noption domain-name-servers 8.8.8.8, 4.4.4.4;\noption domain-name \"mydomain.example\";\n\nsubnet 192.168.13.0 netmask 255.255.255.0 {\n#\tdefault-lease-time 6000;\n#\tmax-lease-time 7200;\n        option routers 192.168.13.1;\n        range   192.168.13.2   192.168.13.254;\n}\n\n#subnet 10.152.187.0 netmask 255.255.255.0 {\n#}\n\n# This is a very basic subnet declaration.\n\n#subnet 10.254.239.0 netmask 255.255.255.224 {\n#  range 10.254.239.10 10.254.239.20;\n#  option routers rtr-239-0-1.example.org, rtr-239-0-2.example.org;\n#}\n\n# This declaration allows BOOTP clients to get dynamic addresses,\n# which we don't really recommend.\n\n#subnet 10.254.239.32 netmask 255.255.255.224 {\n#  range dynamic-bootp 10.254.239.40 10.254.239.60;\n#  option broadcast-address 10.254.239.31;\n#  option routers rtr-239-32-1.example.org;\n#}\n\n# A slightly different configuration for an internal subnet.\n#subnet 10.5.5.0 netmask 255.255.255.224 {\n#  range 10.5.5.26 10.5.5.30;\n#  option domain-name-servers ns1.internal.example.org;\n#  option domain-name \"internal.example.org\";\n#  option routers 10.5.5.1;\n#  option broadcast-address 10.5.5.31;\n#  default-lease-time 600;\n#  max-lease-time 7200;\n#}\n\n# Hosts which require special configuration options can be listed in\n# host statements.   If no address is specified, the address will be\n# allocated dynamically (if possible), but the host-specific information\n# will still come from the host declaration.\n\n#host passacaglia {\n#  hardware ethernet 0:0:c0:5d:bd:95;\n#  filename \"vmunix.passacaglia\";\n#  server-name \"toccata.fugue.com\";\n#}\n\n# Fixed IP addresses can also be specified for hosts.   These addresses\n# should not also be listed as being available for dynamic assignment.\n# Hosts for which fixed IP addresses have been specified can boot using\n# BOOTP or DHCP.   Hosts for which no fixed address is specified can only\n# be booted with DHCP, unless there is an address range on the subnet\n# to which a BOOTP client is connected which has the dynamic-bootp flag\n# set.\n#host fantasia {\n#  hardware ethernet 08:00:07:26:c0:a5;\n#  fixed-address fantasia.fugue.com;\n#}\n\n# You can declare a class of clients and then do address allocation\n# based on that.   The example below shows a case where all clients\n# in a certain class get addresses on the 10.17.224/24 subnet, and all\n# other clients get addresses on the 10.0.29/24 subnet.\n\n#class \"foo\" {\n#  match if substring (option vendor-class-identifier, 0, 4) = \"SUNW\";\n#}\n\n#shared-network 224-29 {\n#  subnet 10.17.224.0 netmask 255.255.255.0 {\n#    option routers rtr-224.example.org;\n#  }\n#  subnet 10.0.29.0 netmask 255.255.255.0 {\n#    option routers rtr-29.example.org;\n#  }\n#  pool {\n#    allow members of \"foo\";\n#    range 10.17.224.10 10.17.224.250;\n#  }\n#  pool {\n#    deny members of \"foo\";\n#    range 10.0.29.10 10.0.29.230;\n#  }\n#}\n"
  },
  {
    "path": "user_space/difs_disable.sh",
    "content": "#!/bin/bash\n\nhome_dir=$(pwd)\n\nif test -d \"/sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\"; then\n  cd /sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\nelse \n  cd /sys/devices/soc0/fpga-axi\\@0/fpga-axi\\@0\\:sdr\nfi\n\nset -x\n#set\nif [[ -n $1 ]]; then\n  echo \"1$1\" > csma_cfg0\nfi\n\n# show\ncat csma_cfg0\nset +x\n\ncd $home_dir\n"
  },
  {
    "path": "user_space/driver_nl80211.patch",
    "content": "--- wpa_supplicant-2.1/src/drivers/driver_nl80211.c\t2014-02-04 12:23:35.000000000 +0100\n+++ driver_nl80211.c\t2020-01-09 09:11:35.943884000 +0100\n@@ -5903,6 +5903,8 @@\n \t    wpa_driver_nl80211_set_mode(bss, nlmode) < 0)\n \t\treturn -1;\n \n+\tnl80211_disable_11b_rates(drv, drv->ifindex, 1);\n+\n retry:\n \tmsg = nlmsg_alloc();\n \tif (!msg)\n@@ -8625,6 +8627,7 @@\n \t}\n \n \tnl80211_mark_disconnected(drv);\n+\tnl80211_disable_11b_rates(drv, drv->ifindex, 1);\n \n \tmsg = nlmsg_alloc();\n \tif (!msg)\n"
  },
  {
    "path": "user_space/drv_and_fpga_package_gen.sh",
    "content": "  \n#!/bin/bash\n\n# Author: Xianjun Jiao\n# SPDX-FileCopyrightText: 2022 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\nif [ \"$#\" -lt 3 ]; then\n    echo \"You have input $# arguments.\"\n    echo \"You must enter at least the first three 3 arguments: \\$OPENWIFI_HW_IMG_DIR \\$XILINX_DIR \\$BOARD_NAME file_postfix\"\n    exit 1\nfi\n\nOPENWIFI_HW_IMG_DIR=$1\nXILINX_DIR=$2\nBOARD_NAME=$3\n\nXILINX_ENV_FILE=$XILINX_DIR/Vitis/2022.2/settings64.sh\necho \"Expect env file $XILINX_ENV_FILE\"\n\nif [ -f \"$XILINX_ENV_FILE\" ]; then\n    echo \"$XILINX_ENV_FILE is found!\"\nelse\n    echo \"$XILINX_ENV_FILE is not correct. Please check!\"\n    exit 1\nfi\n\nif [ \"$BOARD_NAME\" != \"neptunesdr\" ] && [ \"$BOARD_NAME\" != \"antsdr\" ] && [ \"$BOARD_NAME\" != \"antsdr_e200\" ] && [ \"$BOARD_NAME\" != \"e310v2\" ]  && [ \"$BOARD_NAME\" != \"sdrpi\" ] && [ \"$BOARD_NAME\" != \"zc706_fmcs2\" ] && [ \"$BOARD_NAME\" != \"zc702_fmcs2\" ] && [ \"$BOARD_NAME\" != \"zed_fmcs2\" ] && [ \"$BOARD_NAME\" != \"adrv9361z7035\" ] && [ \"$BOARD_NAME\" != \"adrv9364z7020\" ] && [ \"$BOARD_NAME\" != \"zcu102_fmcs2\" ] && [ \"$BOARD_NAME\" != \"zcu102_9371\" ]; then\n    echo \"$BOARD_NAME is not correct. Please check!\"\n    exit 1\nelse\n    echo \"$BOARD_NAME is found!\"\nfi\n\nif [ -d \"$OPENWIFI_HW_IMG_DIR/boards/$BOARD_NAME\" ]; then\n    echo \"$OPENWIFI_HW_IMG_DIR is found!\"\nelse\n    echo \"$OPENWIFI_HW_IMG_DIR is not correct. Please check!\"\n    exit 1\nfi\n\n# uncompress the system.hdf and system_top.bit for use\nmkdir -p hdf_and_bit\nrm hdf_and_bit/* -rf\nunzip $OPENWIFI_HW_IMG_DIR/boards/$BOARD_NAME/sdk/system_top.xsa -d ./hdf_and_bit\n# cp ./hdf_and_bit/$BOARD_NAME/sdk/system_top_hw_platform_0/system.hdf $OPENWIFI_HW_IMG_DIR/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/ -rf\n# cp ./hdf_and_bit/system_top.bit $OPENWIFI_HW_IMG_DIR/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/ -rf\n\n# BIT_FILENAME=$OPENWIFI_HW_IMG_DIR/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/system_top.bit\nBIT_FILENAME=./hdf_and_bit/system_top.bit\n\nif [ -f \"$BIT_FILENAME\" ]; then\n    echo \"$BIT_FILENAME is found!\"\nelse\n    echo \"$BIT_FILENAME does NOT exist. Please check!\"\n    exit 1\nfi\n\nif [ \"$BOARD_NAME\" == \"zcu102_fmcs2\" ] || [ \"$BOARD_NAME\" == \"zcu102_9371\" ]; then\n    ARCH=\"zynqmp\"\n    ARCH_BIT=64\nelse\n    ARCH=\"zynq\"\n    ARCH_BIT=32\nfi\n\n# FINAL_BIT_FILENAME=$BOARD_NAME\\_system_top_reload.bit.bin\n\nset -x\n\nsource $XILINX_ENV_FILE\n\ncp $BIT_FILENAME ./\nbootgen -image system_top.bif -arch $ARCH -process_bitstream bin -w\n\n# cp system_top_reload.bit.bin ./$FINAL_BIT_FILENAME\n\ncd ../driver\nmake clean\n./make_all.sh $XILINX_DIR $ARCH_BIT\ncd ../user_space\nmkdir -p drv_and_fpga\nrm -rf drv_and_fpga/*\ncp system_top.bit.bin ../driver/side_ch/side_ch.ko ../driver/tx_intf/tx_intf.ko ../driver/rx_intf/rx_intf.ko ../driver/openofdm_tx/openofdm_tx.ko ../driver/openofdm_rx/openofdm_rx.ko  ../driver/xpu/xpu.ko ../driver/sdr.ko ./drv_and_fpga -f\ncp $OPENWIFI_HW_IMG_DIR/boards/$BOARD_NAME/sdk/git_info.txt ./drv_and_fpga -f\n# Add driver git info\necho \" \" >> ./drv_and_fpga//git_info.txt\necho \"openwifi-git-branch\" >> ./drv_and_fpga//git_info.txt\ngit branch >> ./drv_and_fpga//git_info.txt\necho \" \" >> ./drv_and_fpga//git_info.txt\necho \"openwifi-git-commit\" >> ./drv_and_fpga//git_info.txt\ngit log -3 >> ./drv_and_fpga//git_info.txt\necho \" \" >> ./drv_and_fpga//git_info.txt\n\ntar -cvf ./drv_and_fpga/driver.tar $(git ls-files ../driver/)\n\n# dir_save=$(pwd)\n\n# cd $OPENWIFI_HW_DIR/ip/\n# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-ip-root.tar $(git ls-files ./ | grep -v -E \"/|openofdm_rx\")\n# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-ip-xpu.tar $(git ls-files ./xpu)\n# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-ip-tx_intf.tar $(git ls-files ./tx_intf)\n# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-ip-rx_intf.tar $(git ls-files ./rx_intf)\n# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-ip-openofdm_tx.tar $(git ls-files ./openofdm_tx)\n# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-ip-side_ch.tar $(git ls-files ./side_ch)\n\n# cd ../boards\n# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-boards-root.tar $(git ls-files ./ | grep -v \"/\")\n# cd ./$BOARD_NAME\n# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-boards-$BOARD_NAME-root.tar $(git ls-files ./ | grep -v \"/\")\n# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-boards-$BOARD_NAME-src.tar $(git ls-files ./src)\n# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-boards-$BOARD_NAME-ip_repo.tar ip_repo\n\n# cd $dir_save\n# # tar -cvf drv_and_fpga.tar system_top.bit.bin tx_intf.ko rx_intf.ko openofdm_tx.ko openofdm_rx.ko xpu.ko sdr.ko git_info.txt\n\nif [ \"$#\" == 4 ]; then\n    POSTFIX=\"_${4}\"\nelse\n    POSTFIX=\"\"\nfi\ntar -zcvf drv_and_fpga$POSTFIX.tar.gz drv_and_fpga\n\nset +x\n"
  },
  {
    "path": "user_space/eifs_by_last_rx_fail_disable.sh",
    "content": "#!/bin/bash\n\nhome_dir=$(pwd)\n\nif test -d \"/sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\"; then\n  cd /sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\nelse \n  cd /sys/devices/soc0/fpga-axi\\@0/fpga-axi\\@0\\:sdr\nfi\n\nset -x\n#set\nif [[ -n $1 ]]; then\n  echo \"4$1\" > csma_cfg0\nfi\n\n# show\ncat csma_cfg0\nset +x\n\ncd $home_dir\n"
  },
  {
    "path": "user_space/eifs_by_last_tx_fail_disable.sh",
    "content": "#!/bin/bash\n\nhome_dir=$(pwd)\n\nif test -d \"/sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\"; then\n  cd /sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\nelse \n  cd /sys/devices/soc0/fpga-axi\\@0/fpga-axi\\@0\\:sdr\nfi\n\nset -x\n#set\nif [[ -n $1 ]]; then\n  echo \"5$1\" > csma_cfg0\nfi\n\n# show\ncat csma_cfg0\nset +x\n\ncd $home_dir\n"
  },
  {
    "path": "user_space/eifs_disable.sh",
    "content": "#!/bin/bash\n\nhome_dir=$(pwd)\n\nif test -d \"/sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\"; then\n  cd /sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\nelse \n  cd /sys/devices/soc0/fpga-axi\\@0/fpga-axi\\@0\\:sdr\nfi\n\nset -x\n#set\nif [[ -n $1 ]]; then\n  echo \"2$1\" > csma_cfg0\nfi\n\n# show\ncat csma_cfg0\nset +x\n\ncd $home_dir\n"
  },
  {
    "path": "user_space/fast_reg_log/fast_reg_log.c",
    "content": "// Author: Xianjun Jiao (xianjun.jiao@imec.be; putaoshu@msn.com)\n// SPDX-FileCopyrightText: 2023 UGent\n// SPDX-License-Identifier: AGPL-3.0-or-later\n\n// Use this example together with fast_reg_log_analyzer.m (notter release)\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <unistd.h>\n#include <fcntl.h>\n#include <sys/mman.h>\n#include <stdint.h>\n\nint main()\n{\n  unsigned int bram_size = 0x10000; // 64KB, aligned with openwifi hw .bd and devicetree\n  off_t bram_pbase = 0x83c40000;    // physical base address, aligned with openwifi hw .bd and devicetree (this example: xpu @ 32bit boards)\n  uint32_t *bram32_vptr;\n  int fd, i, j;\n  uint32_t tsf_reg[524288*2];\n  FILE *fp;\n  // Map the BRAM physical address into user space getting a virtual address for it\n  if ((fd = open(\"/dev/mem\", O_RDONLY | O_SYNC)) != -1) {\n    bram32_vptr = (uint32_t *)mmap(NULL, bram_size, PROT_READ, MAP_SHARED, fd, bram_pbase);\n    \n    fp = fopen (\"fast_reg_log.bin\", \"wb\");\n    if (fp == NULL) {\n      printf(\"fopen fast_reg_log.bin failed! %d\\n\", (int)fp);\n      close(fd);\n      return(0);\n    }\n\n    for (j=0; j<10; j++) {\n      for (i=0; i<(524288*2); i=i+2) {\n        tsf_reg[i+0] = (*(bram32_vptr+57)); // read xpu register 57: rssi trx agc cca status\n        tsf_reg[i+1] = (*(bram32_vptr+58)); // read xpu register 58: low 32bit of tsf\n      }\n\n      // for (i=0; i<1024; i++) {\n      //   printf(\"%d %x\\n\", tsf[i], reg[i]);\n      // }\n      // memcpy(buf, bram64_vptr, bram_size);\n\n      fwrite(tsf_reg, sizeof(uint32_t), 524288*2, fp);\n    }\n\n    fclose(fp);\n    // printf(\"%016llx\\n\", buf[65532]);\n    // printf(\"%016llx\\n\", buf[65533]);\n    // printf(\"%016llx\\n\", buf[65534]);\n    // printf(\"%016llx\\n\", buf[65535]);\n    // //for(i=0; i<32; i++) {\n    // //    printf(\"0x%02x\\n\", buf[i]);\n    // //}\n\n    close(fd);\n  }\n  return(0);\n}\n"
  },
  {
    "path": "user_space/fast_reg_log/fast_reg_log_analyzer.m",
    "content": "% Author: Xianjun Jiao (xianjun.jiao@imec.be; putaoshu@msn.com)\n% SPDX-FileCopyrightText: 2023 UGent\n% SPDX-License-Identifier: AGPL-3.0-or-later\n\nfunction fast_reg_log_analyzer(filename_bin, start_idx, end_idx)\nclose all;\n\n% if exist('start_idx', 'var')==0 || isempty(start_idx)\n%   start_idx = 1;\n% end\n% \n% if exist('end_idx', 'var')==0 || isempty(end_idx)\n%   end_idx = 65536;\n% end\n\nfilename_csv = [filename_bin(1:(end-3)) 'csv'];\ndisp(['Human readable fast reg log will be in ' filename_csv]);\n\nfid = fopen(filename_bin);\nif fid == -1\n    disp('fopen failed!');\n    return;\nend\n\na = fread(fid, inf, 'uint32');\nfclose(fid);\n% a = bitand(uint32(a), uint32(268435455));\n% plot(a(1:2:end)); hold on;\n% plot(a(2:2:end));\n% legend('1', '2');\n\na = uint32(a);\ntsf = a(2:2:end);\n% plot(tsf);\nstate = a(1:2:end);\n\n% find out overflow idx\noverflow_idx = find(diff([0; double(tsf)])<0, 1, 'first');\n% overflow_idx\nif ~isempty(overflow_idx)\n    tsf(overflow_idx:end) = tsf(overflow_idx:end) + (2^32);\n    disp(num2str(overflow_idx));\nend\n\nrssi_correction = 145;\nrssi_half_db = double(bitand(bitshift(state, 0), uint32((2^11)-1)));\nagc_lock = 1 - double(bitand(bitshift(state, -11), uint32(1)));\ndemod_is_ongoing = double(bitand(bitshift(state, -12), uint32(1)));\ntx_is_ongoing = double(bitand(bitshift(state, -13), uint32(1)));\nch_idle = 1 - double(bitand(bitshift(state, -14), uint32(1)));\niq_rssi_half_db = double(bitand(bitshift(state, -16), uint32((2^9)-1)));\nagc_gain = double(bitand(bitshift(state, -25), uint32((2^7)-1)));\n\nrssi_dbm = (rssi_half_db./2) - rssi_correction;\n\nfigure;\nsubplot(2,1,1);\nplot(tsf, -rssi_dbm, 'r+-'); hold on;\nplot(tsf, iq_rssi_half_db, 'bo-');\nplot(tsf, agc_gain, 'ks-');\nlegend('rssi dbm', 'iq rssi half db', 'agc gain');\nsubplot(2,1,2);\nplot(tsf, agc_lock+0); hold on;\nplot(tsf, demod_is_ongoing+2);\nplot(tsf, tx_is_ongoing+4);\nplot(tsf, ch_idle+6);\n\nlegend('agc lock', 'demod is ongoing', 'tx is ongoing', 'ch idle');\n\na=table(tsf, rssi_half_db, rssi_dbm, iq_rssi_half_db, agc_gain, agc_lock, demod_is_ongoing, tx_is_ongoing, ch_idle);\nwritetable(a, filename_csv);\n"
  },
  {
    "path": "user_space/fosdem-11ag.sh",
    "content": "#!/bin/bash\n\n# Author: Xianjun Jiao\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\n# test_mode=$1\n# if [ -z $test_mode ]\n# then\n#   test_mode=0\n# fi\n# echo test_mode $test_mode\n\nkillall hostapd\nkillall webfsd\n\ncd ~/openwifi\n# service network-manager stop\n# ./wgd.sh $test_mode\nifconfig sdr0 192.168.13.1\nrm  /var/run/dhcpd.pid\nsleep 1\nservice isc-dhcp-server restart\nhostapd hostapd-openwifi-11ag.conf &\nsleep 5\ncd webserver\nwebfsd -F -p 80 -f index.html &\nroute add default gw 192.168.10.1\ncd ~/openwifi\n./agc_settings.sh 1\n"
  },
  {
    "path": "user_space/fosdem.sh",
    "content": "#!/bin/bash\n\n# Author: Xianjun Jiao\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\n# test_mode=$1\n# if [ -z $test_mode ]\n# then\n#   test_mode=0\n# fi\n# echo test_mode $test_mode\n\nkillall hostapd\nkillall webfsd\n\ncd ~/openwifi\n# service network-manager stop\n# ./wgd.sh $test_mode\nifconfig sdr0 192.168.13.1\nrm  /var/run/dhcpd.pid\nsleep 1\nservice isc-dhcp-server restart\nhostapd hostapd-openwifi.conf &\nsleep 5\ncd webserver\nwebfsd -F -p 80 -f index.html &\nroute add default gw 192.168.10.1\ncd ~/openwifi\n./agc_settings.sh 1\n"
  },
  {
    "path": "user_space/hostapd-openwifi-11ag.conf",
    "content": "interface=sdr0\ndriver=nl80211\ncountry_code=BE\nssid=openwifi\nhw_mode=a\nchannel=36\nsupported_rates=60 90 120 180 240 360 480 540\nbasic_rates=60 90 120 180\n#ieee80211n=1\n#ht_capab=[SHORT-GI-20]\n#require_ht=1\n#ieee80211d=1\n#ieee80211h=1\n#wpa=1\n#wpa_passphrase=openwifi\n#wpa_key_mgmt=WPA-PSK\n#wpa_pairwise=TKIP CCMP\n#wpa_ptk_rekey=600\n\n"
  },
  {
    "path": "user_space/hostapd-openwifi.conf",
    "content": "interface=sdr0\ndriver=nl80211\ncountry_code=BE\nssid=openwifi\nhw_mode=a\nchannel=36\nsupported_rates=60 90 120 180 240 360 480 540\nbasic_rates=60 90 120 180\nieee80211n=1\n#ht_capab=[SHORT-GI-20]\nrequire_ht=1\n#ieee80211d=1\n#ieee80211h=1\n#wpa=1\n#wpa_passphrase=openwifi\n#wpa_key_mgmt=WPA-PSK\n#wpa_pairwise=TKIP CCMP\n#wpa_ptk_rekey=600\n\n"
  },
  {
    "path": "user_space/inject_80211/Makefile",
    "content": "\nall: inject_80211 analyze_80211\n\ninject_80211: inject_80211.c\n#\tgcc  -Wall -Werror inject_80211.c -o inject_80211 -lpcap\n\tgcc  -Wall inject_80211.c -o inject_80211 -lpcap\n\nanalyze_80211: analyze_80211.c\n# gcc  -Wall -Werror radiotap.c analyze_80211.c -o analyze_80211 -lpcap\n\tgcc  -Wall radiotap.c analyze_80211.c -o analyze_80211 -lpcap\n\nclean:\n\trm -f inject_80211 analyze_80211\n\n"
  },
  {
    "path": "user_space/inject_80211/analyze_80211.c",
    "content": "\n// Author: Michael Mehari\n// SPDX-FileCopyrightText: 2020 UGent\n// SPDX-License-Identifier: GPL-2.0-or-later\n\n/*\n *   This program is free software; you can redistribute it and/or modify\n *   it under the terms of the GNU General Public License as published by\n *   the Free Software Foundation; version 2.\n *\n *   This program is distributed in the hope that it will be useful,\n *   but WITHOUT ANY WARRANTY; without even the implied warranty of\n *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n *   GNU General Public License for more details.\n *\n *   You should have received a copy of the GNU General Public License along\n *   with this program; if not, write to the Free Software Foundation, Inc.,\n *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n */\n\n#include \"inject_80211.h\"\n#include \"radiotap.h\"\n#include \"uthash.h\"\n\n#define HEADERLEN_80211   24\n\nstruct RECORD_t\n{\n\tchar\t\tid[16];\t\t// hw_mode-rate-sgi_flag-packet_size\n\tuint16_t\tpkt_cnt;\t// number of packets received\n\tuint64_t\tts_begin;\t// beginning timestamp\n\tuint64_t\tts_end;\t\t// ending timestamp\n\n\tUT_hash_handle\thh;\t\t// hash function handler\n};\n\n/* 802.11n bitrates x 2 */\nstatic const uint8_t rates_11n[] = {13, 26, 39, 52, 78, 104, 117, 130};\n\nint main(int argc, char **argv)\n{ \n\tstruct pcap_pkthdr pcap_hdr; \n\tconst u_char *packet;\n\tchar hw_mode, id[16];\n\tint rate, sgi_flag, packet_size;\n\n\tint n, hdr_len;\n\tstruct ieee80211_radiotap_iterator rti;\n\n\tstruct RECORD_t *RECORD_ptr, *tmp_ptr, *hash_ptr = NULL;\n\n\tif (argc < 2)\n\t{ \n\t\tfprintf(stderr, \"Usage: %s <pcap>\\n\", argv[0]); \n\t\texit(1); \n\t} \n\n\tpcap_t *handle; \n\tchar errbuf[PCAP_ERRBUF_SIZE];  \n\thandle = pcap_open_offline(argv[1], errbuf); \n\n\tif (handle == NULL)\n\t{\n\t\tfprintf(stderr,\"Couldn't open pcap file %s: %s\\n\", argv[1], errbuf); \n\t\treturn(2); \n\t} \n\n\twhile ((packet = pcap_next(handle, &pcap_hdr)))\n\t{\n\t\thdr_len = (packet[2] + (packet[3] << 8));\n\t\tif (pcap_hdr.len < (hdr_len + HEADERLEN_80211))\n\t\t\tcontinue;\n\n\t\tpacket_size = pcap_hdr.len - (hdr_len + HEADERLEN_80211);\n\t\tif (packet_size < 0)\n\t\t\tcontinue;\n\n\t\tif (ieee80211_radiotap_iterator_init(&rti, (struct ieee80211_radiotap_header *)packet, packet_size, NULL) < 0)\n\t\t\tcontinue;\n\n\t\twhile ((n = ieee80211_radiotap_iterator_next(&rti)) == 0)\n\t\t{\n\t\t\tswitch (rti.this_arg_index)\n\t\t\t{\n\t\t\t\tcase IEEE80211_RADIOTAP_RATE:\n\t\t\t\t\trate = (rti.this_arg)[0];\n\t\t\t\t\tsgi_flag = 0;\n\t\t\t\t\thw_mode = 'a';\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase IEEE80211_RADIOTAP_MCS:\n\t\t\t\t\trate = rates_11n[((rti.this_arg)[2])];\n\t\t\t\t\tsgi_flag = (rti.this_arg)[1] & 0x40;\n\t\t\t\t\thw_mode = 'n';\n\t\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\t// create hash table index\n\t\tsprintf(id, \"%c-%d-%d-%d\", hw_mode, rate, sgi_flag, packet_size);\n\n\t\t// Hash table implementation for c : https://github.com/troydhanson/uthash\n\t\tHASH_FIND_STR(hash_ptr, id, RECORD_ptr);\n\t\tif(RECORD_ptr == NULL)\n\t\t{\n\t\t\tRECORD_ptr = (struct RECORD_t*)malloc(sizeof(struct RECORD_t));\n\t\t\tif(RECORD_ptr == NULL)\n\t\t\t{\n\t\t\t\tfprintf(stderr, \"Unable to create record!\\n\");\n\t\t\t\treturn 1;\n\t\t\t}\n\n\t\t\tstrcpy(RECORD_ptr->id, id);\n\t\t\tRECORD_ptr->pkt_cnt = 1;\n\t\t\tRECORD_ptr->ts_begin = 1e6*pcap_hdr.ts.tv_sec + pcap_hdr.ts.tv_usec;\n\n\t\t\t// Add the new record to the hash table\n\t\t\tHASH_ADD_STR(hash_ptr, id, RECORD_ptr);\n\t\t}\n\t\telse\n\t\t{\n\t\t\tRECORD_ptr->pkt_cnt++;\n\t\t\tRECORD_ptr->ts_end = 1e6*pcap_hdr.ts.tv_sec + pcap_hdr.ts.tv_usec;\n\t\t}\n\t} \n\tpcap_close(handle);\n\n\n\t// Iterate through the hash table\n\tprintf(\"HW MODE\\tRATE(Mbps)\\tSGI\\tSIZE(bytes)\\tCOUNT\\tDELAY(sec)\\n\");\n\tprintf(\"=======\\t==========\\t===\\t===========\\t=====\\t=========\\n\");\n\tHASH_ITER(hh, hash_ptr, RECORD_ptr, tmp_ptr)\n\t{\n\t\tsscanf(RECORD_ptr->id, \"%c-%d-%d-%d\", &hw_mode, &rate, &sgi_flag, &packet_size);\n\t\tprintf(\"802.11%c\\t%.1f\\t\\t%s\\t%d\\t\\t%d\\t%.5f\\n\", hw_mode, rate/2.0, (sgi_flag == 0 ? \"OFF\" : \"ON\"), packet_size, RECORD_ptr->pkt_cnt, 1e-6*(RECORD_ptr->ts_end - RECORD_ptr->ts_begin));\n\t}\n\tfflush(stdout);\n\n\treturn 0;\n}\n"
  },
  {
    "path": "user_space/inject_80211/ieee80211_radiotap.h",
    "content": "/*\n * Copyright (c) 2017\t\tIntel Deutschland GmbH\n * Copyright (c) 2018-2019\tIntel Corporation\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n#ifndef __RADIOTAP_H\n#define __RADIOTAP_H\n\n#include <linux/kernel.h>\n// #include <asm/unaligned.h>\n\n/**\n * struct ieee82011_radiotap_header - base radiotap header\n */\nstruct ieee80211_radiotap_header {\n\t/**\n\t * @it_version: radiotap version, always 0\n\t */\n\tuint8_t it_version;\n\n\t/**\n\t * @it_pad: padding (or alignment)\n\t */\n\tuint8_t it_pad;\n\n\t/**\n\t * @it_len: overall radiotap header length\n\t */\n\t__le16 it_len;\n\n\t/**\n\t * @it_present: (first) present word\n\t */\n\t__le32 it_present;\n} __attribute__((packed));\n\n/* version is always 0 */\n#define PKTHDR_RADIOTAP_VERSION\t0\n\n/* see the radiotap website for the descriptions */\nenum ieee80211_radiotap_presence {\n\tIEEE80211_RADIOTAP_TSFT = 0,\n\tIEEE80211_RADIOTAP_FLAGS = 1,\n\tIEEE80211_RADIOTAP_RATE = 2,\n\tIEEE80211_RADIOTAP_CHANNEL = 3,\n\tIEEE80211_RADIOTAP_FHSS = 4,\n\tIEEE80211_RADIOTAP_DBM_ANTSIGNAL = 5,\n\tIEEE80211_RADIOTAP_DBM_ANTNOISE = 6,\n\tIEEE80211_RADIOTAP_LOCK_QUALITY = 7,\n\tIEEE80211_RADIOTAP_TX_ATTENUATION = 8,\n\tIEEE80211_RADIOTAP_DB_TX_ATTENUATION = 9,\n\tIEEE80211_RADIOTAP_DBM_TX_POWER = 10,\n\tIEEE80211_RADIOTAP_ANTENNA = 11,\n\tIEEE80211_RADIOTAP_DB_ANTSIGNAL = 12,\n\tIEEE80211_RADIOTAP_DB_ANTNOISE = 13,\n\tIEEE80211_RADIOTAP_RX_FLAGS = 14,\n\tIEEE80211_RADIOTAP_TX_FLAGS = 15,\n\tIEEE80211_RADIOTAP_RTS_RETRIES = 16,\n\tIEEE80211_RADIOTAP_DATA_RETRIES = 17,\n\t/* 18 is XChannel, but it's not defined yet */\n\tIEEE80211_RADIOTAP_MCS = 19,\n\tIEEE80211_RADIOTAP_AMPDU_STATUS = 20,\n\tIEEE80211_RADIOTAP_VHT = 21,\n\tIEEE80211_RADIOTAP_TIMESTAMP = 22,\n\tIEEE80211_RADIOTAP_HE = 23,\n\tIEEE80211_RADIOTAP_HE_MU = 24,\n\tIEEE80211_RADIOTAP_ZERO_LEN_PSDU = 26,\n\tIEEE80211_RADIOTAP_LSIG = 27,\n\n\t/* valid in every it_present bitmap, even vendor namespaces */\n\tIEEE80211_RADIOTAP_RADIOTAP_NAMESPACE = 29,\n\tIEEE80211_RADIOTAP_VENDOR_NAMESPACE = 30,\n\tIEEE80211_RADIOTAP_EXT = 31\n};\n\n/* for IEEE80211_RADIOTAP_FLAGS */\nenum ieee80211_radiotap_flags {\n\tIEEE80211_RADIOTAP_F_CFP = 0x01,\n\tIEEE80211_RADIOTAP_F_SHORTPRE = 0x02,\n\tIEEE80211_RADIOTAP_F_WEP = 0x04,\n\tIEEE80211_RADIOTAP_F_FRAG = 0x08,\n\tIEEE80211_RADIOTAP_F_FCS = 0x10,\n\tIEEE80211_RADIOTAP_F_DATAPAD = 0x20,\n\tIEEE80211_RADIOTAP_F_BADFCS = 0x40,\n};\n\n/* for IEEE80211_RADIOTAP_CHANNEL */\nenum ieee80211_radiotap_channel_flags {\n\tIEEE80211_CHAN_CCK = 0x0020,\n\tIEEE80211_CHAN_OFDM = 0x0040,\n\tIEEE80211_CHAN_2GHZ = 0x0080,\n\tIEEE80211_CHAN_5GHZ = 0x0100,\n\tIEEE80211_CHAN_DYN = 0x0400,\n\tIEEE80211_CHAN_HALF = 0x4000,\n\tIEEE80211_CHAN_QUARTER = 0x8000,\n};\n\n/* for IEEE80211_RADIOTAP_RX_FLAGS */\nenum ieee80211_radiotap_rx_flags {\n\tIEEE80211_RADIOTAP_F_RX_BADPLCP = 0x0002,\n};\n\n/* for IEEE80211_RADIOTAP_TX_FLAGS */\nenum ieee80211_radiotap_tx_flags {\n\tIEEE80211_RADIOTAP_F_TX_FAIL = 0x0001,\n\tIEEE80211_RADIOTAP_F_TX_CTS = 0x0002,\n\tIEEE80211_RADIOTAP_F_TX_RTS = 0x0004,\n\tIEEE80211_RADIOTAP_F_TX_NOACK = 0x0008,\n\tIEEE80211_RADIOTAP_F_TX_NOSEQNO = 0x0010,\n};\n\n/* for IEEE80211_RADIOTAP_MCS \"have\" flags */\nenum ieee80211_radiotap_mcs_have {\n\tIEEE80211_RADIOTAP_MCS_HAVE_BW = 0x01,\n\tIEEE80211_RADIOTAP_MCS_HAVE_MCS = 0x02,\n\tIEEE80211_RADIOTAP_MCS_HAVE_GI = 0x04,\n\tIEEE80211_RADIOTAP_MCS_HAVE_FMT = 0x08,\n\tIEEE80211_RADIOTAP_MCS_HAVE_FEC = 0x10,\n\tIEEE80211_RADIOTAP_MCS_HAVE_STBC = 0x20,\n};\n\nenum ieee80211_radiotap_mcs_flags {\n\tIEEE80211_RADIOTAP_MCS_BW_MASK = 0x03,\n\tIEEE80211_RADIOTAP_MCS_BW_20 = 0,\n\tIEEE80211_RADIOTAP_MCS_BW_40 = 1,\n\tIEEE80211_RADIOTAP_MCS_BW_20L = 2,\n\tIEEE80211_RADIOTAP_MCS_BW_20U = 3,\n\n\tIEEE80211_RADIOTAP_MCS_SGI = 0x04,\n\tIEEE80211_RADIOTAP_MCS_FMT_GF = 0x08,\n\tIEEE80211_RADIOTAP_MCS_FEC_LDPC = 0x10,\n\tIEEE80211_RADIOTAP_MCS_STBC_MASK = 0x60,\n\tIEEE80211_RADIOTAP_MCS_STBC_1 = 1,\n\tIEEE80211_RADIOTAP_MCS_STBC_2 = 2,\n\tIEEE80211_RADIOTAP_MCS_STBC_3 = 3,\n\tIEEE80211_RADIOTAP_MCS_STBC_SHIFT = 5,\n};\n\n/* for IEEE80211_RADIOTAP_AMPDU_STATUS */\nenum ieee80211_radiotap_ampdu_flags {\n\tIEEE80211_RADIOTAP_AMPDU_REPORT_ZEROLEN = 0x0001,\n\tIEEE80211_RADIOTAP_AMPDU_IS_ZEROLEN = 0x0002,\n\tIEEE80211_RADIOTAP_AMPDU_LAST_KNOWN = 0x0004,\n\tIEEE80211_RADIOTAP_AMPDU_IS_LAST = 0x0008,\n\tIEEE80211_RADIOTAP_AMPDU_DELIM_CRC_ERR = 0x0010,\n\tIEEE80211_RADIOTAP_AMPDU_DELIM_CRC_KNOWN = 0x0020,\n\tIEEE80211_RADIOTAP_AMPDU_EOF = 0x0040,\n\tIEEE80211_RADIOTAP_AMPDU_EOF_KNOWN = 0x0080,\n};\n\n/* for IEEE80211_RADIOTAP_VHT */\nenum ieee80211_radiotap_vht_known {\n\tIEEE80211_RADIOTAP_VHT_KNOWN_STBC = 0x0001,\n\tIEEE80211_RADIOTAP_VHT_KNOWN_TXOP_PS_NA = 0x0002,\n\tIEEE80211_RADIOTAP_VHT_KNOWN_GI = 0x0004,\n\tIEEE80211_RADIOTAP_VHT_KNOWN_SGI_NSYM_DIS = 0x0008,\n\tIEEE80211_RADIOTAP_VHT_KNOWN_LDPC_EXTRA_OFDM_SYM = 0x0010,\n\tIEEE80211_RADIOTAP_VHT_KNOWN_BEAMFORMED = 0x0020,\n\tIEEE80211_RADIOTAP_VHT_KNOWN_BANDWIDTH = 0x0040,\n\tIEEE80211_RADIOTAP_VHT_KNOWN_GROUP_ID = 0x0080,\n\tIEEE80211_RADIOTAP_VHT_KNOWN_PARTIAL_AID = 0x0100,\n};\n\nenum ieee80211_radiotap_vht_flags {\n\tIEEE80211_RADIOTAP_VHT_FLAG_STBC = 0x01,\n\tIEEE80211_RADIOTAP_VHT_FLAG_TXOP_PS_NA = 0x02,\n\tIEEE80211_RADIOTAP_VHT_FLAG_SGI = 0x04,\n\tIEEE80211_RADIOTAP_VHT_FLAG_SGI_NSYM_M10_9 = 0x08,\n\tIEEE80211_RADIOTAP_VHT_FLAG_LDPC_EXTRA_OFDM_SYM = 0x10,\n\tIEEE80211_RADIOTAP_VHT_FLAG_BEAMFORMED = 0x20,\n};\n\nenum ieee80211_radiotap_vht_coding {\n\tIEEE80211_RADIOTAP_CODING_LDPC_USER0 = 0x01,\n\tIEEE80211_RADIOTAP_CODING_LDPC_USER1 = 0x02,\n\tIEEE80211_RADIOTAP_CODING_LDPC_USER2 = 0x04,\n\tIEEE80211_RADIOTAP_CODING_LDPC_USER3 = 0x08,\n};\n\n/* for IEEE80211_RADIOTAP_TIMESTAMP */\nenum ieee80211_radiotap_timestamp_unit_spos {\n\tIEEE80211_RADIOTAP_TIMESTAMP_UNIT_MASK = 0x000F,\n\tIEEE80211_RADIOTAP_TIMESTAMP_UNIT_MS = 0x0000,\n\tIEEE80211_RADIOTAP_TIMESTAMP_UNIT_US = 0x0001,\n\tIEEE80211_RADIOTAP_TIMESTAMP_UNIT_NS = 0x0003,\n\tIEEE80211_RADIOTAP_TIMESTAMP_SPOS_MASK = 0x00F0,\n\tIEEE80211_RADIOTAP_TIMESTAMP_SPOS_BEGIN_MDPU = 0x0000,\n\tIEEE80211_RADIOTAP_TIMESTAMP_SPOS_PLCP_SIG_ACQ = 0x0010,\n\tIEEE80211_RADIOTAP_TIMESTAMP_SPOS_EO_PPDU = 0x0020,\n\tIEEE80211_RADIOTAP_TIMESTAMP_SPOS_EO_MPDU = 0x0030,\n\tIEEE80211_RADIOTAP_TIMESTAMP_SPOS_UNKNOWN = 0x00F0,\n};\n\nenum ieee80211_radiotap_timestamp_flags {\n\tIEEE80211_RADIOTAP_TIMESTAMP_FLAG_64BIT = 0x00,\n\tIEEE80211_RADIOTAP_TIMESTAMP_FLAG_32BIT = 0x01,\n\tIEEE80211_RADIOTAP_TIMESTAMP_FLAG_ACCURACY = 0x02,\n};\n\nstruct ieee80211_radiotap_he {\n\t__le16 data1, data2, data3, data4, data5, data6;\n};\n\nenum ieee80211_radiotap_he_bits {\n\tIEEE80211_RADIOTAP_HE_DATA1_FORMAT_MASK\t\t= 3,\n\tIEEE80211_RADIOTAP_HE_DATA1_FORMAT_SU\t\t= 0,\n\tIEEE80211_RADIOTAP_HE_DATA1_FORMAT_EXT_SU\t= 1,\n\tIEEE80211_RADIOTAP_HE_DATA1_FORMAT_MU\t\t= 2,\n\tIEEE80211_RADIOTAP_HE_DATA1_FORMAT_TRIG\t\t= 3,\n\n\tIEEE80211_RADIOTAP_HE_DATA1_BSS_COLOR_KNOWN\t= 0x0004,\n\tIEEE80211_RADIOTAP_HE_DATA1_BEAM_CHANGE_KNOWN\t= 0x0008,\n\tIEEE80211_RADIOTAP_HE_DATA1_UL_DL_KNOWN\t\t= 0x0010,\n\tIEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN\t= 0x0020,\n\tIEEE80211_RADIOTAP_HE_DATA1_DATA_DCM_KNOWN\t= 0x0040,\n\tIEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN\t= 0x0080,\n\tIEEE80211_RADIOTAP_HE_DATA1_LDPC_XSYMSEG_KNOWN\t= 0x0100,\n\tIEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN\t\t= 0x0200,\n\tIEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE_KNOWN\t= 0x0400,\n\tIEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE2_KNOWN\t= 0x0800,\n\tIEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE3_KNOWN\t= 0x1000,\n\tIEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE4_KNOWN\t= 0x2000,\n\tIEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN\t= 0x4000,\n\tIEEE80211_RADIOTAP_HE_DATA1_DOPPLER_KNOWN\t= 0x8000,\n\n\tIEEE80211_RADIOTAP_HE_DATA2_PRISEC_80_KNOWN\t= 0x0001,\n\tIEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN\t\t= 0x0002,\n\tIEEE80211_RADIOTAP_HE_DATA2_NUM_LTF_SYMS_KNOWN\t= 0x0004,\n\tIEEE80211_RADIOTAP_HE_DATA2_PRE_FEC_PAD_KNOWN\t= 0x0008,\n\tIEEE80211_RADIOTAP_HE_DATA2_TXBF_KNOWN\t\t= 0x0010,\n\tIEEE80211_RADIOTAP_HE_DATA2_PE_DISAMBIG_KNOWN\t= 0x0020,\n\tIEEE80211_RADIOTAP_HE_DATA2_TXOP_KNOWN\t\t= 0x0040,\n\tIEEE80211_RADIOTAP_HE_DATA2_MIDAMBLE_KNOWN\t= 0x0080,\n\tIEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET\t\t= 0x3f00,\n\tIEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET_KNOWN\t= 0x4000,\n\tIEEE80211_RADIOTAP_HE_DATA2_PRISEC_80_SEC\t= 0x8000,\n\n\tIEEE80211_RADIOTAP_HE_DATA3_BSS_COLOR\t\t= 0x003f,\n\tIEEE80211_RADIOTAP_HE_DATA3_BEAM_CHANGE\t\t= 0x0040,\n\tIEEE80211_RADIOTAP_HE_DATA3_UL_DL\t\t= 0x0080,\n\tIEEE80211_RADIOTAP_HE_DATA3_DATA_MCS\t\t= 0x0f00,\n\tIEEE80211_RADIOTAP_HE_DATA3_DATA_DCM\t\t= 0x1000,\n\tIEEE80211_RADIOTAP_HE_DATA3_CODING\t\t= 0x2000,\n\tIEEE80211_RADIOTAP_HE_DATA3_LDPC_XSYMSEG\t= 0x4000,\n\tIEEE80211_RADIOTAP_HE_DATA3_STBC\t\t= 0x8000,\n\n\tIEEE80211_RADIOTAP_HE_DATA4_SU_MU_SPTL_REUSE\t= 0x000f,\n\tIEEE80211_RADIOTAP_HE_DATA4_MU_STA_ID\t\t= 0x7ff0,\n\tIEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE1\t= 0x000f,\n\tIEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE2\t= 0x00f0,\n\tIEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE3\t= 0x0f00,\n\tIEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE4\t= 0xf000,\n\n\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC\t= 0x000f,\n\t\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_20MHZ\t= 0,\n\t\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_40MHZ\t= 1,\n\t\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_80MHZ\t= 2,\n\t\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_160MHZ\t= 3,\n\t\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_26T\t= 4,\n\t\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_52T\t= 5,\n\t\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_106T\t= 6,\n\t\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_242T\t= 7,\n\t\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_484T\t= 8,\n\t\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_996T\t= 9,\n\t\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_2x996T\t= 10,\n\n\tIEEE80211_RADIOTAP_HE_DATA5_GI\t\t\t= 0x0030,\n\t\tIEEE80211_RADIOTAP_HE_DATA5_GI_0_8\t\t\t= 0,\n\t\tIEEE80211_RADIOTAP_HE_DATA5_GI_1_6\t\t\t= 1,\n\t\tIEEE80211_RADIOTAP_HE_DATA5_GI_3_2\t\t\t= 2,\n\n\tIEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE\t\t= 0x00c0,\n\t\tIEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_UNKNOWN\t\t= 0,\n\t\tIEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_1X\t\t\t= 1,\n\t\tIEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_2X\t\t\t= 2,\n\t\tIEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_4X\t\t\t= 3,\n\tIEEE80211_RADIOTAP_HE_DATA5_NUM_LTF_SYMS\t= 0x0700,\n\tIEEE80211_RADIOTAP_HE_DATA5_PRE_FEC_PAD\t\t= 0x3000,\n\tIEEE80211_RADIOTAP_HE_DATA5_TXBF\t\t= 0x4000,\n\tIEEE80211_RADIOTAP_HE_DATA5_PE_DISAMBIG\t\t= 0x8000,\n\n\tIEEE80211_RADIOTAP_HE_DATA6_NSTS\t\t= 0x000f,\n\tIEEE80211_RADIOTAP_HE_DATA6_DOPPLER\t\t= 0x0010,\n\tIEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_KNOWN\t= 0x0020,\n\tIEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW\t\t= 0x00c0,\n\t\tIEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_20MHZ\t= 0,\n\t\tIEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_40MHZ\t= 1,\n\t\tIEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_80MHZ\t= 2,\n\t\tIEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_160MHZ\t= 3,\n\tIEEE80211_RADIOTAP_HE_DATA6_TXOP\t\t= 0x7f00,\n\tIEEE80211_RADIOTAP_HE_DATA6_MIDAMBLE_PDCTY\t= 0x8000,\n};\n\nstruct ieee80211_radiotap_he_mu {\n\t__le16 flags1, flags2;\n\tu8 ru_ch1[4];\n\tu8 ru_ch2[4];\n};\n\nenum ieee80211_radiotap_he_mu_bits {\n\tIEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_MCS\t\t= 0x000f,\n\tIEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_MCS_KNOWN\t\t= 0x0010,\n\tIEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_DCM\t\t= 0x0020,\n\tIEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_DCM_KNOWN\t\t= 0x0040,\n\tIEEE80211_RADIOTAP_HE_MU_FLAGS1_CH2_CTR_26T_RU_KNOWN\t= 0x0080,\n\tIEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_RU_KNOWN\t\t= 0x0100,\n\tIEEE80211_RADIOTAP_HE_MU_FLAGS1_CH2_RU_KNOWN\t\t= 0x0200,\n\tIEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_CTR_26T_RU_KNOWN\t= 0x1000,\n\tIEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_CTR_26T_RU\t\t= 0x2000,\n\tIEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_COMP_KNOWN\t= 0x4000,\n\tIEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_SYMS_USERS_KNOWN\t= 0x8000,\n\n\tIEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW\t= 0x0003,\n\t\tIEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_20MHZ\t= 0x0000,\n\t\tIEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_40MHZ\t= 0x0001,\n\t\tIEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_80MHZ\t= 0x0002,\n\t\tIEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_160MHZ\t= 0x0003,\n\tIEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_KNOWN\t= 0x0004,\n\tIEEE80211_RADIOTAP_HE_MU_FLAGS2_SIG_B_COMP\t\t= 0x0008,\n\tIEEE80211_RADIOTAP_HE_MU_FLAGS2_SIG_B_SYMS_USERS\t= 0x00f0,\n\tIEEE80211_RADIOTAP_HE_MU_FLAGS2_PUNC_FROM_SIG_A_BW\t= 0x0300,\n\tIEEE80211_RADIOTAP_HE_MU_FLAGS2_PUNC_FROM_SIG_A_BW_KNOWN= 0x0400,\n\tIEEE80211_RADIOTAP_HE_MU_FLAGS2_CH2_CTR_26T_RU\t\t= 0x0800,\n};\n\nenum ieee80211_radiotap_lsig_data1 {\n\tIEEE80211_RADIOTAP_LSIG_DATA1_RATE_KNOWN\t\t= 0x0001,\n\tIEEE80211_RADIOTAP_LSIG_DATA1_LENGTH_KNOWN\t\t= 0x0002,\n};\n\nenum ieee80211_radiotap_lsig_data2 {\n\tIEEE80211_RADIOTAP_LSIG_DATA2_RATE\t\t\t= 0x000f,\n\tIEEE80211_RADIOTAP_LSIG_DATA2_LENGTH\t\t\t= 0xfff0,\n};\n\nstruct ieee80211_radiotap_lsig {\n\t__le16 data1, data2;\n};\n\nenum ieee80211_radiotap_zero_len_psdu_type {\n\tIEEE80211_RADIOTAP_ZERO_LEN_PSDU_SOUNDING\t\t= 0,\n\tIEEE80211_RADIOTAP_ZERO_LEN_PSDU_NOT_CAPTURED\t\t= 1,\n\tIEEE80211_RADIOTAP_ZERO_LEN_PSDU_VENDOR\t\t\t= 0xff,\n};\n\n// /**\n//  * ieee80211_get_radiotap_len - get radiotap header length\n//  */\n// static inline u16 ieee80211_get_radiotap_len(const char *data)\n// {\n// \tstruct ieee80211_radiotap_header *hdr = (void *)data;\n\n// \treturn get_unaligned_le16(&hdr->it_len);\n// }\n\n#endif /* __RADIOTAP_H */\n"
  },
  {
    "path": "user_space/inject_80211/inject_80211.c",
    "content": "// Modified by: Michael Mehari\n// SPDX-FileCopyrightText: 2020 UGent\n// SPDX-FileCopyrightText: 2007 Andy Green <andy@warmcat.com>\n// SPDX-License-Identifier: GPL-2.0-or-later\n\n/*\n *   This program is free software; you can redistribute it and/or modify\n *   it under the terms of the GNU General Public License as published by\n *   the Free Software Foundation; version 2.\n *\n *   This program is distributed in the hope that it will be useful,\n *   but WITHOUT ANY WARRANTY; without even the implied warranty of\n *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n *   GNU General Public License for more details.\n *\n *   You should have received a copy of the GNU General Public License along\n *   with this program; if not, write to the Free Software Foundation, Inc.,\n *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n */\n\n// Thanks for contributions:\n// 2007-03-15 fixes to getopt_long code by Matteo Croce rootkit85@yahoo.it\n\n#include \"inject_80211.h\"\n#include \"ieee80211_radiotap.h\"\n\n#define BUF_SIZE_MAX   (1536)\n#define BUF_SIZE_TOTAL (BUF_SIZE_MAX+1) // +1 in case the sprintf insert the last 0\n\n/* wifi bitrate to use in 500kHz units */\nstatic const u8 u8aRatesToUse[] = {\n\t6*2,\n\t9*2,\n\t12*2,\n\t18*2,\n\t24*2,\n\t36*2,\n\t48*2,\n\t54*2\n};\n\n/* this is the template radiotap header we send packets out with */\nstatic const u8 u8aRadiotapHeader[] = \n{\n\t0x00, 0x00, // <-- radiotap version\n\t0x1c, 0x00, // <- radiotap header length\n\t0x6f, 0x08, 0x08, 0x00, // <-- bitmap\n\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // <-- timestamp\n\t0x00, // <-- flags (Offset +0x10)\n\t0x6c, // <-- rate (0ffset +0x11)\n\t0x71, 0x09, 0xc0, 0x00, // <-- channel\n\t0xde, // <-- antsignal\n\t0x00, // <-- antnoise\n\t0x01, // <-- antenna\n\t0x02, 0x00, 0x0f,  // <-- MCS\n};\n\n#define\tOFFSET_RATE 0x11\n#define MCS_OFFSET 0x19\n#define GI_OFFSET 0x1a\n#define MCS_RATE_OFFSET 0x1b\n\n/* IEEE80211 header */\nstatic u8 ieee_hdr_data[] =\n{\n\t0x08, 0x02, 0x00, 0x00,             // FC 0x0802. 0--subtype; 8--type&version; 02--toDS0 fromDS1 (data packet from DS to STA)\n\t0x66, 0x55, 0x44, 0x33, 0x22, 0x11, // BSSID/MAC of AP\n\t0x66, 0x55, 0x44, 0x33, 0x22, 0x22, // Transmitter address\n\t0x66, 0x55, 0x44, 0x33, 0x22, 0x33, // Source address\n\t0x10, 0x86,                         // 0--fragment number; 0x861=2145--sequence number\n};\n\nstatic u8 ieee_hdr_mgmt[] =\n{\n\t0x00, 0x00, 0x00, 0x00,             // FC 0x0000. 0--subtype; 0--type&version; \n\t0x66, 0x55, 0x44, 0x33, 0x22, 0x11, // BSSID/MAC of AP\n\t0x66, 0x55, 0x44, 0x33, 0x22, 0x22, // Transmitter address\n\t0x66, 0x55, 0x44, 0x33, 0x22, 0x33, // Source address\n\t0x10, 0x86,                         // 0--fragment number; 0x861=2145--sequence number\n};\n\nstatic u8 ieee_hdr_ack_cts[] =\n{\n\t0xd4, 0x00, 0x00, 0x00,             // FC 0xd400. d--subtype; 4--type&version;\n\t0x66, 0x55, 0x44, 0x33, 0x22, 0x11, // mac addr of the peer\n};\n\nstatic u8 ieee_hdr_rts[] =\n{\n\t0xb4, 0x00, 0x00, 0x00,             // FC 0xb400. b--subtype; 4--type&version;\n\t0x66, 0x55, 0x44, 0x33, 0x22, 0x11, // mac addr of the peer\n\t0x66, 0x55, 0x44, 0x33, 0x22, 0x22, // mac addr of the peer\n};\n\n// Generate random string\nvoid gen_rand_str(int size, char *rand_char)\n{\n\tint i, randNum = 0;\n\n\t// Seed the random number generator with packet size\n\tsrand(size);\n\tfor (i = 0; i < size; i++)\n\t{\n\t\t// First, pick a number between 0 and 25.\n\t\trandNum = 255 * (rand() / (RAND_MAX + 1.0));\n\n\t\tif(randNum == 0)\n\t\t{\n\t\t\ti--;\n\t\t\tcontinue;\n\t\t}\n\n\t\t// Type cast to character\n\t\trand_char[i] = (char) randNum;\n\t}\n\trand_char[i] = '\\0';\n}\n\n// Put input mac address by strtol to ieee header\nvoid assign_mac_addr(u64 a, u8 *hdr)\n{\n  hdr[0] = ((a>>40)&0xFF);\n  hdr[1] = ((a>>32)&0xFF);\n  hdr[2] = ((a>>24)&0xFF);\n  hdr[3] = ((a>>16)&0xFF);\n  hdr[4] = ((a>>8 )&0xFF);\n  hdr[5] = ((a>>0 )&0xFF);\n}\n\nint flagHelp = 0;\n\nvoid usage(void)\n{\n\tprintf(\n\t    \"(c)2006-2007 Andy Green <andy@warmcat.com>  Licensed under GPL2\\n\"\n\t\t\"(r)2020 Michael Tetemke Mehari <michael.mehari@ugent.be>\\n\"\n\t\t\"(r)2022 Xianjun Jiao <xianjun.jiao@ugent.be>\"\n\t    \"\\n\"\n\t    \"Usage: inject_80211 [options] <interface>\\n\\nOptions\\n\"\n\t    \"-m/--hw_mode <hardware operation mode> (a,g,n)\\n\"\n\t    \"-r/--rate_index <rate/MCS index> (0,1,2,3,4,5,6,7)\\n\"\n\t\t\"-t/--packet_type (m/c/d/r for management/control/data/reserved)\\n\"\n\t\t\"-e/--sub_type (hex value. example:\\n\"\n\t\t\"     8/A/B/C for Beacon/Disassociation/Authentication/Deauth, when packet_type m\\n\"\n\t\t\"     A/B/C/D for PS-Poll/RTS/CTS/ACK, when packet_type c\\n\"\n\t\t\"     0/1/2/8 for Data/Data+CF-Ack/Data+CF-Poll/QoS-Data, when packet_type d)\\n\"\n\t\t\"-a/--addr1 <Example: input 000e8e3b229c for 00:0e:8e:3b:22:9c>\\n\"\n\t\t\"-b/--addr2 <Example: input 000e8e3b229c for 00:0e:8e:3b:22:9c>\\n\"\n\t    \"-i/--sgi_flag (0,1)\\n\"\n\t    \"-n/--num_packets <number of packets>\\n\"\n\t    \"-s/--payload_size <payload size in bytes>\\n\"\n\t    \"-d/--delay <delay between packets in usec>\\n\"\n\t    \"-h   this menu\\n\\n\"\n\n\t    \"Example:\\n\"\n\t    \"  iw dev sdr0 interface add mon0 type monitor && ifconfig mon0 up\\n\"\n\t    \"  inject_80211 mon0\\n\"\n\t    \"\\n\");\n\texit(1);\n}\n\n\nint main(int argc, char *argv[])\n{\n\tu8 buffer[BUF_SIZE_TOTAL], sub_type=1, *ieee_hdr;\n  u64 addr1=1, addr2=2;\n\tchar szErrbuf[PCAP_ERRBUF_SIZE], rand_char[1484], hw_mode = 'n', packet_type = 'd';\n\tint i, nLinkEncap = 0, r, rate_index = 0, sgi_flag = 0, num_packets = 10, payload_size = 64, packet_size, nDelay = 100000;\n\tint ieee_hdr_len, payload_len;\n\tpcap_t *ppcap = NULL;\n\n\twhile (1)\n\t{\n\t\tint nOptionIndex;\n\t\tstatic const struct option optiona[] =\n\t\t{\n\t\t\t{ \"hw_mode\", required_argument, NULL, 'm' },\n\t\t\t{ \"rate_index\", required_argument, NULL, 'r' },\n\t\t\t{ \"packet_type\", required_argument, NULL, 't' },\n\t\t\t{ \"sub_type\", required_argument, NULL, 'e' },\n\t\t\t{ \"addr1\", required_argument, NULL, 'a' },\n\t\t\t{ \"addr2\", required_argument, NULL, 'b' },\n\t\t\t{ \"sgi_flag\", no_argument, NULL, 'i' },\n\t\t\t{ \"num_packets\", required_argument, NULL, 'n' },\n\t\t\t{ \"payload_size\", required_argument, NULL, 's' },\n\t\t\t{ \"delay\", required_argument, NULL, 'd' },\n\t\t\t{ \"help\", no_argument, &flagHelp, 1 },\n\t\t\t{ 0, 0, 0, 0 }\n\t\t};\n\t\tint c = getopt_long(argc, argv, \"m:r:t:e:a:b:i:n:s:d:h\", optiona, &nOptionIndex);\n\n\t\tif (c == -1)\n\t\t\tbreak;\n\t\tswitch (c)\n\t\t{\n\t\t\tcase 0: // long option\n\t\t\t\tbreak;\n\n\t\t\tcase 'h':\n\t\t\t\tusage();\n        break;\n\n\t\t\tcase 'm':\n\t\t\t\thw_mode = optarg[0];\n\t\t\t\tbreak;\n\n\t\t\tcase 'r':\n\t\t\t\trate_index = atoi(optarg);\n\t\t\t\tbreak;\n\n\t\t\tcase 't':\n\t\t\t\tpacket_type = optarg[0];\n\t\t\t\tbreak;\n\n\t\t\tcase 'e':\n\t\t\t\tsub_type = strtol(optarg, NULL, 16);\n\t\t\t\tbreak;\n\n\t\t\tcase 'a':\n\t\t\t\taddr1 = strtoll(optarg, NULL, 16);\n\t\t\t\tbreak;\n\n\t\t\tcase 'b':\n\t\t\t\taddr2 = strtoll(optarg, NULL, 16);\n\t\t\t\tbreak;\n\n\t\t\tcase 'i':\n\t\t\t\tsgi_flag = atoi(optarg);\n\t\t\t\tbreak;\n\n\t\t\tcase 'n':\n\t\t\t\tnum_packets = atoi(optarg);\n\t\t\t\tbreak;\n\n\t\t\tcase 's':\n\t\t\t\tpayload_size = atoi(optarg);\n\t\t\t\tbreak;\n\n\t\t\tcase 'd':\n\t\t\t\tnDelay = atoi(optarg);\n\t\t\t\tbreak;\n\n\t\t\tdefault:\n\t\t\t\tprintf(\"unknown switch %c\\n\", c);\n\t\t\t\tusage();\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (optind >= argc)\n\t\tusage();\n\n\t// open the interface in pcap\n\tszErrbuf[0] = '\\0';\n\tppcap = pcap_open_live(argv[optind], 800, 1, 20, szErrbuf);\n\tif (ppcap == NULL)\n\t{\n\t\tprintf(\"Unable to open interface %s in pcap: %s\\n\", argv[optind], szErrbuf);\n\t\treturn (1);\n\t}\n\n\tnLinkEncap = pcap_datalink(ppcap);\n\tswitch (nLinkEncap)\n\t{\n\t\tcase DLT_PRISM_HEADER:\n\t\t\tprintf(\"DLT_PRISM_HEADER Encap\\n\");\n\t\t\tbreak;\n\n\t\tcase DLT_IEEE802_11_RADIO:\n\t\t\tprintf(\"DLT_IEEE802_11_RADIO Encap\\n\");\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tprintf(\"!!! unknown encapsulation on %s !\\n\", argv[1]);\n\t\t\treturn (1);\n\t}\n\n\tpcap_setnonblock(ppcap, 1, szErrbuf);\n\n\t// Fill the IEEE hdr\n\tif (packet_type == 'd') // data packet\n\t{\n\t\tieee_hdr_data[0]  = ( ieee_hdr_data[0]|(sub_type<<4) );\n\t\t// ieee_hdr_data[9]  = addr1;\n    assign_mac_addr(addr1, ieee_hdr_data+4);\n\t\t// ieee_hdr_data[15] = addr2;\n    assign_mac_addr(addr2, ieee_hdr_data+10);\n\t\t// ieee_hdr_data[21] = addr1;\n    assign_mac_addr(addr2, ieee_hdr_data+16);\n\t\tieee_hdr_len = sizeof(ieee_hdr_data);\n\t\tieee_hdr = ieee_hdr_data;\n\t}\n\telse if (packet_type == 'm') // managment packet\n\t{\n\t\tieee_hdr_mgmt[0]  = ( ieee_hdr_mgmt[0]|(sub_type<<4) );\n\t\t// ieee_hdr_mgmt[9]  = addr1;\n    assign_mac_addr(addr1, ieee_hdr_mgmt+4);\n\t\t// ieee_hdr_mgmt[15] = addr2;\n    assign_mac_addr(addr2, ieee_hdr_mgmt+10);\n\t\t// ieee_hdr_mgmt[21] = addr1;\n    assign_mac_addr(addr2, ieee_hdr_mgmt+16);\n\t\tieee_hdr_len = sizeof(ieee_hdr_mgmt);\n\t\tieee_hdr = ieee_hdr_mgmt;\n\t}\n\telse if (packet_type == 'c')\n\t{\n\t\tpayload_size = 0;\n\t\tif (sub_type == 0xC || sub_type == 0xD)\n\t\t{\n\t\t\tieee_hdr_ack_cts[0] = ( ieee_hdr_ack_cts[0]|(sub_type<<4) );\n\t\t\t// ieee_hdr_ack_cts[9] = addr1;\n      assign_mac_addr(addr1, ieee_hdr_ack_cts+4);\n\t\t\tieee_hdr_len = sizeof(ieee_hdr_ack_cts);\n\t\t\tieee_hdr = ieee_hdr_ack_cts;\n\t\t} \n\t\telse if (sub_type == 0xA || sub_type == 0xB)\n\t\t{\n\t\t\tieee_hdr_rts[0]  = ( ieee_hdr_rts[0]|(sub_type<<4) );\n\t\t\t// ieee_hdr_rts[9]  = addr1;\n      assign_mac_addr(addr1, ieee_hdr_rts+4);\n\t\t\t// ieee_hdr_rts[15] = addr2;\n      assign_mac_addr(addr2, ieee_hdr_rts+10);\n\t\t\tieee_hdr_len = sizeof(ieee_hdr_rts);\n\t\t\tieee_hdr = ieee_hdr_rts;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tprintf(\"!!! sub_type %x is not supported yet!\\n\", sub_type);\n\t\t\treturn (1);\n\t\t}\n\t} \n\telse \n\t{\n\t\tprintf(\"!!! packet_type %c is not supported yet!\\n\", packet_type);\n\t\treturn (1);\n\t}\n\n\t// Generate random string\n\tgen_rand_str(payload_size+4, rand_char); //4 for space reserved for crc\n\tpayload_len = strlen(rand_char);\n\t\n\tpacket_size = sizeof(u8aRadiotapHeader) + ieee_hdr_len + payload_len;\n\tprintf(\"mode = 802.11%c, rate index = %d, SHORT GI = %d, number of packets = %d and packet size = %d bytes, delay = %d usec\\n\", hw_mode, rate_index, sgi_flag, num_packets, packet_size, nDelay);\n\tprintf(\"packet_type %c sub_type %x payload_len %d ieee_hdr_len %d addr1 %016llx addr2 %016llx\\n\", packet_type, sub_type, payload_len, ieee_hdr_len, addr1, addr2);\n\n\tif (packet_size > BUF_SIZE_MAX) {\n\t\tprintf(\"packet_size %d > %d! Quite\\n\", packet_size, BUF_SIZE_MAX);\n\t\treturn(1);\n\t}\n\n\t// Clear storage buffer\n\tmemset(buffer, 0, sizeof (buffer));\n\n\t// Insert default radiotap header\n\tmemcpy(buffer, u8aRadiotapHeader, sizeof (u8aRadiotapHeader));\n\t// Update radiotap header (i.e. hw_mode, rate, GI)\n\tif(hw_mode == 'g' || hw_mode == 'a')\n\t{\n\t\tbuffer[OFFSET_RATE] = u8aRatesToUse[rate_index];\n\t\tbuffer[MCS_OFFSET] = 0x00;\n\t}\n\telse\n\t{\n\t\tbuffer[MCS_OFFSET] = 0x07;\n\t\tif(sgi_flag)\n\t\t\tbuffer[GI_OFFSET] = IEEE80211_RADIOTAP_MCS_SGI;\n\t\tbuffer[MCS_RATE_OFFSET] = rate_index;\n\t}\n\t// Insert IEEE DATA header\n\tmemcpy(buffer + sizeof(u8aRadiotapHeader), ieee_hdr, ieee_hdr_len);\n\t// Insert IEEE DATA payload\n\tsprintf((char *)(buffer + sizeof(u8aRadiotapHeader) + ieee_hdr_len), \"%s\", rand_char);\n\n\t// Inject packets\n\tfor(i = 1; i <= num_packets; i++)\n\t{\n\t\tr = pcap_inject(ppcap, buffer, packet_size);\n\t\tif (r != packet_size) {\n\t\t\tperror(\"Trouble injecting packet\");\n\t\t\treturn (1);\n\t\t}\n\n\t\tprintf(\"number of packets sent = %d\\r\", i);\n\t\tfflush(stdout);\n\n\t\tif (nDelay)\n\t\t\tusleep(nDelay);\n\t}\n\n\tprintf(\"\\n\");\n\n\treturn (0);\n}\n"
  },
  {
    "path": "user_space/inject_80211/inject_80211.h",
    "content": "/*\n * Author: Michael Mehari\n * SPDX-FileCopyrightText: 2019 UGent\n * SPDX-License-Identifier: AGPL-3.0-or-later\n*/\n\n#include <stdlib.h>\n#include <resolv.h>\n#include <string.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <pcap.h>\n#include <errno.h>\n\ntypedef unsigned long long int u64;\ntypedef unsigned int u32;\ntypedef unsigned short u16;\ntypedef unsigned char u8;\ntypedef u32 __le32;\n\n#if __BYTE_ORDER == __LITTLE_ENDIAN\n#define\tle16_to_cpu(x) (x)\n#define\tle32_to_cpu(x) (x)\n#else\n#define\tle16_to_cpu(x) ((((x)&0xff)<<8)|(((x)&0xff00)>>8))\n#define\tle32_to_cpu(x) \\\n((((x)&0xff)<<24)|(((x)&0xff00)<<8)|(((x)&0xff0000)>>8)|(((x)&0xff000000)>>24))\n#endif\n#define\tunlikely(x) (x)\n\n\n\n\n"
  },
  {
    "path": "user_space/inject_80211/inject_80211.sh",
    "content": "#!/bin/bash\n\n# Author: Michael Mehari\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\nHW_MODE='n'\nCOUNT=100\nDELAY=1000\nRATE=( 0 1 2 3 4 5 6 7 )\nSIZE=( $(seq -s' ' 50 100 1450) )\nIF=\"mon0\"\n\nfor (( i = 0 ; i < ${#SIZE[@]} ; i++ )) do\n\tfor (( j = 0 ; j < ${#RATE[@]} ; j++ )) do\n\t\tinject_80211 -m $HW_MODE -n $COUNT -d $DELAY -r ${RATE[$j]} -s ${SIZE[$i]} $IF\n\t\tsleep 1\n\tdone\ndone\n\n"
  },
  {
    "path": "user_space/inject_80211/radiotap.c",
    "content": "/*\n * Radiotap parser\n *\n * Copyright 2007\t\tAndy Green <andy@warmcat.com>\n * Copyright 2009\t\tJohannes Berg <johannes@sipsolutions.net>\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of the GNU General Public License version 2 as\n * published by the Free Software Foundation.\n *\n * Alternatively, this software may be distributed under the terms of BSD\n * license.\n *\n * See COPYING for more details.\n */\n\n#include <linux/kernel.h>\n// #include <linux/export.h>\n// #include <net/cfg80211.h>\n// #include <net/ieee80211_radiotap.h>\n// #include <asm/unaligned.h>\n\n#include \"inject_80211.h\"\n#include \"radiotap.h\"\n#include \"unaligned.h\"\n\n// ----- from kernel, needed by ARRAY_SIZE from kernel.h\n/*\n * Force a compilation error if condition is true, but also produce a\n * result (of value 0 and type int), so the expression can be used\n * e.g. in a structure initializer (or where-ever else comma expressions\n * aren't permitted).\n */\n#define BUILD_BUG_ON_ZERO(e) ((int)(sizeof(struct { int:(-!!(e)); })))\n\n/* Are two types/vars the same type (ignoring qualifiers)? */\n#define __same_type(a, b) __builtin_types_compatible_p(typeof(a), typeof(b))\n\n/* &a[0] degrades to a pointer: a different type from an array */\n#define __must_be_array(a)\tBUILD_BUG_ON_ZERO(__same_type((a), &(a)[0]))\n\n// ----- ARRAY_SIZE from kernel.h\n/**\n * ARRAY_SIZE - get the number of elements in array @arr\n * @arr: array to be sized\n */\n#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]) + __must_be_array(arr))\n\n// ----- radiotap_align_size \n// ----- ieee80211_radiotap_namespace \n// ----- ieee80211_radiotap_vendor_namespaces from cfg80211.h ----- //\nstruct radiotap_align_size {\n\tuint8_t align:4, size:4;\n};\n\nstruct ieee80211_radiotap_namespace {\n\tconst struct radiotap_align_size *align_size;\n\tint n_bits;\n\tuint32_t oui;\n\tuint8_t subns;\n};\n\nstruct ieee80211_radiotap_vendor_namespaces {\n\tconst struct ieee80211_radiotap_namespace *ns;\n\tint n_ns;\n};\n// -------------------------------------------------------------------//\n\n/* function prototypes and related defs are in include/net/cfg80211.h */\n\nstatic const struct radiotap_align_size rtap_namespace_sizes[] = {\n\t[IEEE80211_RADIOTAP_TSFT] = { .align = 8, .size = 8, },\n\t[IEEE80211_RADIOTAP_FLAGS] = { .align = 1, .size = 1, },\n\t[IEEE80211_RADIOTAP_RATE] = { .align = 1, .size = 1, },\n\t[IEEE80211_RADIOTAP_CHANNEL] = { .align = 2, .size = 4, },\n\t[IEEE80211_RADIOTAP_FHSS] = { .align = 2, .size = 2, },\n\t[IEEE80211_RADIOTAP_DBM_ANTSIGNAL] = { .align = 1, .size = 1, },\n\t[IEEE80211_RADIOTAP_DBM_ANTNOISE] = { .align = 1, .size = 1, },\n\t[IEEE80211_RADIOTAP_LOCK_QUALITY] = { .align = 2, .size = 2, },\n\t[IEEE80211_RADIOTAP_TX_ATTENUATION] = { .align = 2, .size = 2, },\n\t[IEEE80211_RADIOTAP_DB_TX_ATTENUATION] = { .align = 2, .size = 2, },\n\t[IEEE80211_RADIOTAP_DBM_TX_POWER] = { .align = 1, .size = 1, },\n\t[IEEE80211_RADIOTAP_ANTENNA] = { .align = 1, .size = 1, },\n\t[IEEE80211_RADIOTAP_DB_ANTSIGNAL] = { .align = 1, .size = 1, },\n\t[IEEE80211_RADIOTAP_DB_ANTNOISE] = { .align = 1, .size = 1, },\n\t[IEEE80211_RADIOTAP_RX_FLAGS] = { .align = 2, .size = 2, },\n\t[IEEE80211_RADIOTAP_TX_FLAGS] = { .align = 2, .size = 2, },\n\t[IEEE80211_RADIOTAP_RTS_RETRIES] = { .align = 1, .size = 1, },\n\t[IEEE80211_RADIOTAP_DATA_RETRIES] = { .align = 1, .size = 1, },\n\t[IEEE80211_RADIOTAP_MCS] = { .align = 1, .size = 3, },\n\t[IEEE80211_RADIOTAP_AMPDU_STATUS] = { .align = 4, .size = 8, },\n\t[IEEE80211_RADIOTAP_VHT] = { .align = 2, .size = 12, },\n\t/*\n\t * add more here as they are defined in radiotap.h\n\t */\n};\n\nstatic const struct ieee80211_radiotap_namespace radiotap_ns = {\n\t.n_bits = ARRAY_SIZE(rtap_namespace_sizes),\n\t.align_size = rtap_namespace_sizes,\n};\n\n/**\n * ieee80211_radiotap_iterator_init - radiotap parser iterator initialization\n * @iterator: radiotap_iterator to initialize\n * @radiotap_header: radiotap header to parse\n * @max_length: total length we can parse into (eg, whole packet length)\n * @vns: vendor namespaces to parse\n *\n * Returns: 0 or a negative error code if there is a problem.\n *\n * This function initializes an opaque iterator struct which can then\n * be passed to ieee80211_radiotap_iterator_next() to visit every radiotap\n * argument which is present in the header.  It knows about extended\n * present headers and handles them.\n *\n * How to use:\n * call __ieee80211_radiotap_iterator_init() to init a semi-opaque iterator\n * struct ieee80211_radiotap_iterator (no need to init the struct beforehand)\n * checking for a good 0 return code.  Then loop calling\n * __ieee80211_radiotap_iterator_next()... it returns either 0,\n * -ENOENT if there are no more args to parse, or -EINVAL if there is a problem.\n * The iterator's @this_arg member points to the start of the argument\n * associated with the current argument index that is present, which can be\n * found in the iterator's @this_arg_index member.  This arg index corresponds\n * to the IEEE80211_RADIOTAP_... defines.\n *\n * Radiotap header length:\n * You can find the CPU-endian total radiotap header length in\n * iterator->max_length after executing ieee80211_radiotap_iterator_init()\n * successfully.\n *\n * Alignment Gotcha:\n * You must take care when dereferencing iterator.this_arg\n * for multibyte types... the pointer is not aligned.  Use\n * get_unaligned((type *)iterator.this_arg) to dereference\n * iterator.this_arg for type \"type\" safely on all arches.\n *\n * Example code:\n * See Documentation/networking/radiotap-headers.rst\n */\n\nint ieee80211_radiotap_iterator_init(\n\tstruct ieee80211_radiotap_iterator *iterator,\n\tstruct ieee80211_radiotap_header *radiotap_header,\n\tint max_length, const struct ieee80211_radiotap_vendor_namespaces *vns)\n{\n\t/* check the radiotap header can actually be present */\n\tif (max_length < sizeof(struct ieee80211_radiotap_header))\n\t\treturn -EINVAL;\n\n\t/* Linux only supports version 0 radiotap format */\n\tif (radiotap_header->it_version)\n\t\treturn -EINVAL;\n\n\t/* sanity check for allowed length and radiotap length field */\n\tif (max_length < get_unaligned_le16(&radiotap_header->it_len))\n\t\treturn -EINVAL;\n\n\titerator->_rtheader = radiotap_header;\n\titerator->_max_length = get_unaligned_le16(&radiotap_header->it_len);\n\titerator->_arg_index = 0;\n\t// iterator->_bitmap_shifter = get_unaligned_le32(&radiotap_header->it_present);\n  iterator->_bitmap_shifter = (uint32_t)le32_to_cpu(radiotap_header->it_present);\n\titerator->_arg = (uint8_t *)radiotap_header + sizeof(*radiotap_header);\n\titerator->_reset_on_ext = 0;\n\titerator->_next_bitmap = &radiotap_header->it_present;\n\titerator->_next_bitmap++;\n\titerator->_vns = vns;\n\titerator->current_namespace = &radiotap_ns;\n\titerator->is_radiotap_ns = 1;\n\n\t/* find payload start allowing for extended bitmap(s) */\n\n\tif (iterator->_bitmap_shifter & (1<<IEEE80211_RADIOTAP_EXT)) {\n\t\tif ((unsigned long)iterator->_arg -\n\t\t    (unsigned long)iterator->_rtheader + sizeof(uint32_t) >\n\t\t    (unsigned long)iterator->_max_length)\n\t\t\treturn -EINVAL;\n\t\t// while (get_unaligned_le32(iterator->_arg) &\n      while (le32_to_cpu(*((u32 *)iterator->_arg)) &\n\t\t\t\t\t(1 << IEEE80211_RADIOTAP_EXT)) {\n\t\t\titerator->_arg += sizeof(uint32_t);\n\n\t\t\t/*\n\t\t\t * check for insanity where the present bitmaps\n\t\t\t * keep claiming to extend up to or even beyond the\n\t\t\t * stated radiotap header length\n\t\t\t */\n\n\t\t\tif ((unsigned long)iterator->_arg -\n\t\t\t    (unsigned long)iterator->_rtheader +\n\t\t\t    sizeof(uint32_t) >\n\t\t\t    (unsigned long)iterator->_max_length)\n\t\t\t\treturn -EINVAL;\n\t\t}\n\n\t\titerator->_arg += sizeof(uint32_t);\n\n\t\t/*\n\t\t * no need to check again for blowing past stated radiotap\n\t\t * header length, because ieee80211_radiotap_iterator_next\n\t\t * checks it before it is dereferenced\n\t\t */\n\t}\n\n\titerator->this_arg = iterator->_arg;\n\n\t/* we are all initialized happily */\n\n\treturn 0;\n}\n// EXPORT_SYMBOL(ieee80211_radiotap_iterator_init);\n\nstatic void find_ns(struct ieee80211_radiotap_iterator *iterator,\n\t\t    uint32_t oui, uint8_t subns)\n{\n\tint i;\n\n\titerator->current_namespace = NULL;\n\n\tif (!iterator->_vns)\n\t\treturn;\n\n\tfor (i = 0; i < iterator->_vns->n_ns; i++) {\n\t\tif (iterator->_vns->ns[i].oui != oui)\n\t\t\tcontinue;\n\t\tif (iterator->_vns->ns[i].subns != subns)\n\t\t\tcontinue;\n\n\t\titerator->current_namespace = &iterator->_vns->ns[i];\n\t\tbreak;\n\t}\n}\n\n\n\n/**\n * ieee80211_radiotap_iterator_next - return next radiotap parser iterator arg\n * @iterator: radiotap_iterator to move to next arg (if any)\n *\n * Returns: 0 if there is an argument to handle,\n * -ENOENT if there are no more args or -EINVAL\n * if there is something else wrong.\n *\n * This function provides the next radiotap arg index (IEEE80211_RADIOTAP_*)\n * in @this_arg_index and sets @this_arg to point to the\n * payload for the field.  It takes care of alignment handling and extended\n * present fields.  @this_arg can be changed by the caller (eg,\n * incremented to move inside a compound argument like\n * IEEE80211_RADIOTAP_CHANNEL).  The args pointed to are in\n * little-endian format whatever the endianess of your CPU.\n *\n * Alignment Gotcha:\n * You must take care when dereferencing iterator.this_arg\n * for multibyte types... the pointer is not aligned.  Use\n * get_unaligned((type *)iterator.this_arg) to dereference\n * iterator.this_arg for type \"type\" safely on all arches.\n */\n\nint ieee80211_radiotap_iterator_next(\n\tstruct ieee80211_radiotap_iterator *iterator)\n{\n\twhile (1) {\n\t\tint hit = 0;\n\t\tint pad, align, size, subns;\n\t\tuint32_t oui;\n\n\t\t/* if no more EXT bits, that's it */\n\t\tif ((iterator->_arg_index % 32) == IEEE80211_RADIOTAP_EXT &&\n\t\t    !(iterator->_bitmap_shifter & 1))\n\t\t\treturn -ENOENT;\n\n\t\tif (!(iterator->_bitmap_shifter & 1))\n\t\t\tgoto next_entry; /* arg not present */\n\n\t\t/* get alignment/size of data */\n\t\tswitch (iterator->_arg_index % 32) {\n\t\tcase IEEE80211_RADIOTAP_RADIOTAP_NAMESPACE:\n\t\tcase IEEE80211_RADIOTAP_EXT:\n\t\t\talign = 1;\n\t\t\tsize = 0;\n\t\t\tbreak;\n\t\tcase IEEE80211_RADIOTAP_VENDOR_NAMESPACE:\n\t\t\talign = 2;\n\t\t\tsize = 6;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tif (!iterator->current_namespace ||\n\t\t\t    iterator->_arg_index >= iterator->current_namespace->n_bits) {\n\t\t\t\tif (iterator->current_namespace == &radiotap_ns)\n\t\t\t\t\treturn -ENOENT;\n\t\t\t\talign = 0;\n\t\t\t} else {\n\t\t\t\talign = iterator->current_namespace->align_size[iterator->_arg_index].align;\n\t\t\t\tsize = iterator->current_namespace->align_size[iterator->_arg_index].size;\n\t\t\t}\n\t\t\tif (!align) {\n\t\t\t\t/* skip all subsequent data */\n\t\t\t\titerator->_arg = iterator->_next_ns_data;\n\t\t\t\t/* give up on this namespace */\n\t\t\t\titerator->current_namespace = NULL;\n\t\t\t\tgoto next_entry;\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\n\t\t/*\n\t\t * arg is present, account for alignment padding\n\t\t *\n\t\t * Note that these alignments are relative to the start\n\t\t * of the radiotap header.  There is no guarantee\n\t\t * that the radiotap header itself is aligned on any\n\t\t * kind of boundary.\n\t\t *\n\t\t * The above is why get_unaligned() is used to dereference\n\t\t * multibyte elements from the radiotap area.\n\t\t */\n\n\t\tpad = ((unsigned long)iterator->_arg -\n\t\t       (unsigned long)iterator->_rtheader) & (align - 1);\n\n\t\tif (pad)\n\t\t\titerator->_arg += align - pad;\n\n\t\tif (iterator->_arg_index % 32 == IEEE80211_RADIOTAP_VENDOR_NAMESPACE) {\n\t\t\tint vnslen;\n\n\t\t\tif ((unsigned long)iterator->_arg + size -\n\t\t\t    (unsigned long)iterator->_rtheader >\n\t\t\t    (unsigned long)iterator->_max_length)\n\t\t\t\treturn -EINVAL;\n\n\t\t\toui = (*iterator->_arg << 16) |\n\t\t\t\t(*(iterator->_arg + 1) << 8) |\n\t\t\t\t*(iterator->_arg + 2);\n\t\t\tsubns = *(iterator->_arg + 3);\n\n\t\t\tfind_ns(iterator, oui, subns);\n\n\t\t\tvnslen = get_unaligned_le16(iterator->_arg + 4);\n\t\t\titerator->_next_ns_data = iterator->_arg + size + vnslen;\n\t\t\tif (!iterator->current_namespace)\n\t\t\t\tsize += vnslen;\n\t\t}\n\n\t\t/*\n\t\t * this is what we will return to user, but we need to\n\t\t * move on first so next call has something fresh to test\n\t\t */\n\t\titerator->this_arg_index = iterator->_arg_index;\n\t\titerator->this_arg = iterator->_arg;\n\t\titerator->this_arg_size = size;\n\n\t\t/* internally move on the size of this arg */\n\t\titerator->_arg += size;\n\n\t\t/*\n\t\t * check for insanity where we are given a bitmap that\n\t\t * claims to have more arg content than the length of the\n\t\t * radiotap section.  We will normally end up equalling this\n\t\t * max_length on the last arg, never exceeding it.\n\t\t */\n\n\t\tif ((unsigned long)iterator->_arg -\n\t\t    (unsigned long)iterator->_rtheader >\n\t\t    (unsigned long)iterator->_max_length)\n\t\t\treturn -EINVAL;\n\n\t\t/* these special ones are valid in each bitmap word */\n\t\tswitch (iterator->_arg_index % 32) {\n\t\tcase IEEE80211_RADIOTAP_VENDOR_NAMESPACE:\n\t\t\titerator->_reset_on_ext = 1;\n\n\t\t\titerator->is_radiotap_ns = 0;\n\t\t\t/*\n\t\t\t * If parser didn't register this vendor\n\t\t\t * namespace with us, allow it to show it\n\t\t\t * as 'raw. Do do that, set argument index\n\t\t\t * to vendor namespace.\n\t\t\t */\n\t\t\titerator->this_arg_index =\n\t\t\t\tIEEE80211_RADIOTAP_VENDOR_NAMESPACE;\n\t\t\tif (!iterator->current_namespace)\n\t\t\t\thit = 1;\n\t\t\tgoto next_entry;\n\t\tcase IEEE80211_RADIOTAP_RADIOTAP_NAMESPACE:\n\t\t\titerator->_reset_on_ext = 1;\n\t\t\titerator->current_namespace = &radiotap_ns;\n\t\t\titerator->is_radiotap_ns = 1;\n\t\t\tgoto next_entry;\n\t\tcase IEEE80211_RADIOTAP_EXT:\n\t\t\t/*\n\t\t\t * bit 31 was set, there is more\n\t\t\t * -- move to next u32 bitmap\n\t\t\t */\n\t\t\titerator->_bitmap_shifter =\n\t\t\t\t// get_unaligned_le32(iterator->_next_bitmap);\n        le32_to_cpu(*iterator->_next_bitmap);\n\t\t\titerator->_next_bitmap++;\n\t\t\tif (iterator->_reset_on_ext)\n\t\t\t\titerator->_arg_index = 0;\n\t\t\telse\n\t\t\t\titerator->_arg_index++;\n\t\t\titerator->_reset_on_ext = 0;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\t/* we've got a hit! */\n\t\t\thit = 1;\n next_entry:\n\t\t\titerator->_bitmap_shifter >>= 1;\n\t\t\titerator->_arg_index++;\n\t\t}\n\n\t\t/* if we found a valid arg earlier, return it now */\n\t\tif (hit)\n\t\t\treturn 0;\n\t}\n}\n// EXPORT_SYMBOL(ieee80211_radiotap_iterator_next);\n"
  },
  {
    "path": "user_space/inject_80211/radiotap.h",
    "content": "#include \"ieee80211_radiotap.h\"\n\n// -----ieee80211_radiotap_iterator from cfg80211.h ----- //\n/**\n * struct ieee80211_radiotap_iterator - tracks walk thru present radiotap args\n * @this_arg_index: index of current arg, valid after each successful call\n *\tto ieee80211_radiotap_iterator_next()\n * @this_arg: pointer to current radiotap arg; it is valid after each\n *\tcall to ieee80211_radiotap_iterator_next() but also after\n *\tieee80211_radiotap_iterator_init() where it will point to\n *\tthe beginning of the actual data portion\n * @this_arg_size: length of the current arg, for convenience\n * @current_namespace: pointer to the current namespace definition\n *\t(or internally %NULL if the current namespace is unknown)\n * @is_radiotap_ns: indicates whether the current namespace is the default\n *\tradiotap namespace or not\n *\n * @_rtheader: pointer to the radiotap header we are walking through\n * @_max_length: length of radiotap header in cpu byte ordering\n * @_arg_index: next argument index\n * @_arg: next argument pointer\n * @_next_bitmap: internal pointer to next present u32\n * @_bitmap_shifter: internal shifter for curr u32 bitmap, b0 set == arg present\n * @_vns: vendor namespace definitions\n * @_next_ns_data: beginning of the next namespace's data\n * @_reset_on_ext: internal; reset the arg index to 0 when going to the\n *\tnext bitmap word\n *\n * Describes the radiotap parser state. Fields prefixed with an underscore\n * must not be used by users of the parser, only by the parser internally.\n */\n\nstruct ieee80211_radiotap_iterator {\n\tstruct ieee80211_radiotap_header *_rtheader;\n\tconst struct ieee80211_radiotap_vendor_namespaces *_vns;\n\tconst struct ieee80211_radiotap_namespace *current_namespace;\n\n\tunsigned char *_arg, *_next_ns_data;\n\t__le32 *_next_bitmap;\n\n\tunsigned char *this_arg;\n\tint this_arg_index;\n\tint this_arg_size;\n\n\tint is_radiotap_ns;\n\n\tint _max_length;\n\tint _arg_index;\n\tuint32_t _bitmap_shifter;\n\tint _reset_on_ext;\n};\n\nextern int ieee80211_radiotap_iterator_init(\n\tstruct ieee80211_radiotap_iterator *iterator,\n\tstruct ieee80211_radiotap_header *radiotap_header,\n\tint max_length, const struct ieee80211_radiotap_vendor_namespaces *vns);\n\nextern int ieee80211_radiotap_iterator_next(\n\tstruct ieee80211_radiotap_iterator *iterator);\n\n"
  },
  {
    "path": "user_space/inject_80211/unaligned.h",
    "content": "/* SPDX-License-Identifier: GPL-2.0-only */\n/*\n *  Port on Texas Instruments TMS320C6x architecture\n *\n *  Copyright (C) 2004, 2009, 2010 Texas Instruments Incorporated\n *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)\n *  Rewritten for 2.6.3x: Mark Salter <msalter@redhat.com>\n */\n#ifndef _ASM_C6X_UNALIGNED_H\n#define _ASM_C6X_UNALIGNED_H\n\n// #include <linux/swab.h>\n// #include <linux/unaligned/generic.h>\n\n#include \"inject_80211.h\"\n\n/*\n * The C64x+ can do unaligned word and dword accesses in hardware\n * using special load/store instructions.\n */\n\nstatic inline u16 get_unaligned_le16(const void *p)\n{\n\tconst u8 *_p = p;\n\treturn _p[0] | _p[1] << 8;\n}\n\nstatic inline u16 get_unaligned_be16(const void *p)\n{\n\tconst u8 *_p = p;\n\treturn _p[0] << 8 | _p[1];\n}\n\nstatic inline void put_unaligned_le16(u16 val, void *p)\n{\n\tu8 *_p = p;\n\t_p[0] = val;\n\t_p[1] = val >> 8;\n}\n\nstatic inline void put_unaligned_be16(u16 val, void *p)\n{\n\tu8 *_p = p;\n\t_p[0] = val >> 8;\n\t_p[1] = val;\n}\n\n// static inline u32 get_unaligned32(const void *p)\n// {\n// \tu32 val = (u32) p;\n// \tasm (\" ldnw\t.d1t1\t*%0,%0\\n\"\n// \t     \" nop     4\\n\"\n// \t     : \"+a\"(val));\n// \treturn val;\n// }\n\n// static inline void put_unaligned32(u32 val, void *p)\n// {\n// \tasm volatile (\" stnw\t.d2t1\t%0,*%1\\n\"\n// \t\t      : : \"a\"(val), \"b\"(p) : \"memory\");\n// }\n\n// static inline u64 get_unaligned64(const void *p)\n// {\n// \tu64 val;\n// \tasm volatile (\" ldndw\t.d1t1\t*%1,%0\\n\"\n// \t\t      \" nop     4\\n\"\n// \t\t      : \"=a\"(val) : \"a\"(p));\n// \treturn val;\n// }\n\n// static inline void put_unaligned64(u64 val, const void *p)\n// {\n// \tasm volatile (\" stndw\t.d2t1\t%0,*%1\\n\"\n// \t\t      : : \"a\"(val), \"b\"(p) : \"memory\");\n// }\n\n#ifdef CONFIG_CPU_BIG_ENDIAN\n\n#define get_unaligned_le32(p)\t __swab32(get_unaligned32(p))\n#define get_unaligned_le64(p)\t __swab64(get_unaligned64(p))\n#define get_unaligned_be32(p)\t get_unaligned32(p)\n#define get_unaligned_be64(p)\t get_unaligned64(p)\n#define put_unaligned_le32(v, p) put_unaligned32(__swab32(v), (p))\n#define put_unaligned_le64(v, p) put_unaligned64(__swab64(v), (p))\n#define put_unaligned_be32(v, p) put_unaligned32((v), (p))\n#define put_unaligned_be64(v, p) put_unaligned64((v), (p))\n#define get_unaligned\t__get_unaligned_be\n#define put_unaligned\t__put_unaligned_be\n\n#else\n\n#define get_unaligned_le32(p)\t get_unaligned32(p)\n#define get_unaligned_le64(p)\t get_unaligned64(p)\n#define get_unaligned_be32(p)\t __swab32(get_unaligned32(p))\n#define get_unaligned_be64(p)\t __swab64(get_unaligned64(p))\n#define put_unaligned_le32(v, p) put_unaligned32((v), (p))\n#define put_unaligned_le64(v, p) put_unaligned64((v), (p))\n#define put_unaligned_be32(v, p) put_unaligned32(__swab32(v), (p))\n#define put_unaligned_be64(v, p) put_unaligned64(__swab64(v), (p))\n#define get_unaligned\t__get_unaligned_le\n#define put_unaligned\t__put_unaligned_le\n\n#endif\n\n#endif /* _ASM_C6X_UNALIGNED_H */\n"
  },
  {
    "path": "user_space/inject_80211/uthash.h",
    "content": "/*\nCopyright (c) 2003-2013, Troy D. Hanson     http://troydhanson.github.com/uthash/\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n    * Redistributions of source code must retain the above copyright\n      notice, this list of conditions and the following disclaimer.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS\nIS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\nPARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\nEXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\nPROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\nPROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\nNEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*/\n\n#ifndef UTHASH_H\n#define UTHASH_H \n\n#include <string.h>   /* memcmp,strlen */\n#include <stddef.h>   /* ptrdiff_t */\n#include <stdlib.h>   /* exit() */\n\n/* These macros use decltype or the earlier __typeof GNU extension.\n   As decltype is only available in newer compilers (VS2010 or gcc 4.3+\n   when compiling c++ source) this code uses whatever method is needed\n   or, for VS2008 where neither is available, uses casting workarounds. */\n#ifdef _MSC_VER         /* MS compiler */\n#if _MSC_VER >= 1600 && defined(__cplusplus)  /* VS2010 or newer in C++ mode */\n#define DECLTYPE(x) (decltype(x))\n#else                   /* VS2008 or older (or VS2010 in C mode) */\n#define NO_DECLTYPE\n#define DECLTYPE(x)\n#endif\n#else                   /* GNU, Sun and other compilers */\n#define DECLTYPE(x) (__typeof(x))\n#endif\n\n#ifdef NO_DECLTYPE\n#define DECLTYPE_ASSIGN(dst,src)                                                 \\\ndo {                                                                             \\\n  char **_da_dst = (char**)(&(dst));                                             \\\n  *_da_dst = (char*)(src);                                                       \\\n} while(0)\n#else \n#define DECLTYPE_ASSIGN(dst,src)                                                 \\\ndo {                                                                             \\\n  (dst) = DECLTYPE(dst)(src);                                                    \\\n} while(0)\n#endif\n\n/* a number of the hash function use uint32_t which isn't defined on win32 */\n#ifdef _MSC_VER\ntypedef unsigned int uint32_t;\ntypedef unsigned char uint8_t;\n#else\n#include <inttypes.h>   /* uint32_t */\n#endif\n\n#define UTHASH_VERSION 1.9.8\n\n#ifndef uthash_fatal\n#define uthash_fatal(msg) exit(-1)        /* fatal error (out of memory,etc) */\n#endif\n#ifndef uthash_malloc\n#define uthash_malloc(sz) malloc(sz)      /* malloc fcn                      */\n#endif\n#ifndef uthash_free\n#define uthash_free(ptr,sz) free(ptr)     /* free fcn                        */\n#endif\n\n#ifndef uthash_noexpand_fyi\n#define uthash_noexpand_fyi(tbl)          /* can be defined to log noexpand  */\n#endif\n#ifndef uthash_expand_fyi\n#define uthash_expand_fyi(tbl)            /* can be defined to log expands   */\n#endif\n\n/* initial number of buckets */\n#define HASH_INITIAL_NUM_BUCKETS 32      /* initial number of buckets        */\n#define HASH_INITIAL_NUM_BUCKETS_LOG2 5  /* lg2 of initial number of buckets */\n#define HASH_BKT_CAPACITY_THRESH 10      /* expand when bucket count reaches */\n\n/* calculate the element whose hash handle address is hhe */\n#define ELMT_FROM_HH(tbl,hhp) ((void*)(((char*)(hhp)) - ((tbl)->hho)))\n\n#define HASH_FIND(hh,head,keyptr,keylen,out)                                     \\\ndo {                                                                             \\\n  unsigned _hf_bkt,_hf_hashv;                                                    \\\n  out=NULL;                                                                      \\\n  if (head) {                                                                    \\\n     HASH_FCN(keyptr,keylen, (head)->hh.tbl->num_buckets, _hf_hashv, _hf_bkt);   \\\n     if (HASH_BLOOM_TEST((head)->hh.tbl, _hf_hashv)) {                           \\\n       HASH_FIND_IN_BKT((head)->hh.tbl, hh, (head)->hh.tbl->buckets[ _hf_bkt ],  \\\n                        keyptr,keylen,out);                                      \\\n     }                                                                           \\\n  }                                                                              \\\n} while (0)\n\n#ifdef HASH_BLOOM\n#define HASH_BLOOM_BITLEN (1ULL << HASH_BLOOM)\n#define HASH_BLOOM_BYTELEN (HASH_BLOOM_BITLEN/8) + ((HASH_BLOOM_BITLEN%8) ? 1:0)\n#define HASH_BLOOM_MAKE(tbl)                                                     \\\ndo {                                                                             \\\n  (tbl)->bloom_nbits = HASH_BLOOM;                                               \\\n  (tbl)->bloom_bv = (uint8_t*)uthash_malloc(HASH_BLOOM_BYTELEN);                 \\\n  if (!((tbl)->bloom_bv))  { uthash_fatal( \"out of memory\"); }                   \\\n  memset((tbl)->bloom_bv, 0, HASH_BLOOM_BYTELEN);                                \\\n  (tbl)->bloom_sig = HASH_BLOOM_SIGNATURE;                                       \\\n} while (0) \n\n#define HASH_BLOOM_FREE(tbl)                                                     \\\ndo {                                                                             \\\n  uthash_free((tbl)->bloom_bv, HASH_BLOOM_BYTELEN);                              \\\n} while (0) \n\n#define HASH_BLOOM_BITSET(bv,idx) (bv[(idx)/8] |= (1U << ((idx)%8)))\n#define HASH_BLOOM_BITTEST(bv,idx) (bv[(idx)/8] & (1U << ((idx)%8)))\n\n#define HASH_BLOOM_ADD(tbl,hashv)                                                \\\n  HASH_BLOOM_BITSET((tbl)->bloom_bv, (hashv & (uint32_t)((1ULL << (tbl)->bloom_nbits) - 1)))\n\n#define HASH_BLOOM_TEST(tbl,hashv)                                               \\\n  HASH_BLOOM_BITTEST((tbl)->bloom_bv, (hashv & (uint32_t)((1ULL << (tbl)->bloom_nbits) - 1)))\n\n#else\n#define HASH_BLOOM_MAKE(tbl) \n#define HASH_BLOOM_FREE(tbl) \n#define HASH_BLOOM_ADD(tbl,hashv) \n#define HASH_BLOOM_TEST(tbl,hashv) (1)\n#define HASH_BLOOM_BYTELEN 0\n#endif\n\n#define HASH_MAKE_TABLE(hh,head)                                                 \\\ndo {                                                                             \\\n  (head)->hh.tbl = (UT_hash_table*)uthash_malloc(                                \\\n                  sizeof(UT_hash_table));                                        \\\n  if (!((head)->hh.tbl))  { uthash_fatal( \"out of memory\"); }                    \\\n  memset((head)->hh.tbl, 0, sizeof(UT_hash_table));                              \\\n  (head)->hh.tbl->tail = &((head)->hh);                                          \\\n  (head)->hh.tbl->num_buckets = HASH_INITIAL_NUM_BUCKETS;                        \\\n  (head)->hh.tbl->log2_num_buckets = HASH_INITIAL_NUM_BUCKETS_LOG2;              \\\n  (head)->hh.tbl->hho = (char*)(&(head)->hh) - (char*)(head);                    \\\n  (head)->hh.tbl->buckets = (UT_hash_bucket*)uthash_malloc(                      \\\n          HASH_INITIAL_NUM_BUCKETS*sizeof(struct UT_hash_bucket));               \\\n  if (! (head)->hh.tbl->buckets) { uthash_fatal( \"out of memory\"); }             \\\n  memset((head)->hh.tbl->buckets, 0,                                             \\\n          HASH_INITIAL_NUM_BUCKETS*sizeof(struct UT_hash_bucket));               \\\n  HASH_BLOOM_MAKE((head)->hh.tbl);                                               \\\n  (head)->hh.tbl->signature = HASH_SIGNATURE;                                    \\\n} while(0)\n\n#define HASH_ADD(hh,head,fieldname,keylen_in,add)                                \\\n        HASH_ADD_KEYPTR(hh,head,&((add)->fieldname),keylen_in,add)\n\n#define HASH_REPLACE(hh,head,fieldname,keylen_in,add,replaced)                   \\\ndo {                                                                             \\\n  replaced=NULL;                                                                 \\\n  HASH_FIND(hh,head,&((add)->fieldname),keylen_in,replaced);                     \\\n  if (replaced!=NULL) {                                                          \\\n     HASH_DELETE(hh,head,replaced);                                              \\\n  };                                                                             \\\n  HASH_ADD(hh,head,fieldname,keylen_in,add);                                     \\\n} while(0)\n \n#define HASH_ADD_KEYPTR(hh,head,keyptr,keylen_in,add)                            \\\ndo {                                                                             \\\n unsigned _ha_bkt;                                                               \\\n (add)->hh.next = NULL;                                                          \\\n (add)->hh.key = (char*)(keyptr);                                                \\\n (add)->hh.keylen = (unsigned)(keylen_in);                                       \\\n if (!(head)) {                                                                  \\\n    head = (add);                                                                \\\n    (head)->hh.prev = NULL;                                                      \\\n    HASH_MAKE_TABLE(hh,head);                                                    \\\n } else {                                                                        \\\n    (head)->hh.tbl->tail->next = (add);                                          \\\n    (add)->hh.prev = ELMT_FROM_HH((head)->hh.tbl, (head)->hh.tbl->tail);         \\\n    (head)->hh.tbl->tail = &((add)->hh);                                         \\\n }                                                                               \\\n (head)->hh.tbl->num_items++;                                                    \\\n (add)->hh.tbl = (head)->hh.tbl;                                                 \\\n HASH_FCN(keyptr,keylen_in, (head)->hh.tbl->num_buckets,                         \\\n         (add)->hh.hashv, _ha_bkt);                                              \\\n HASH_ADD_TO_BKT((head)->hh.tbl->buckets[_ha_bkt],&(add)->hh);                   \\\n HASH_BLOOM_ADD((head)->hh.tbl,(add)->hh.hashv);                                 \\\n HASH_EMIT_KEY(hh,head,keyptr,keylen_in);                                        \\\n HASH_FSCK(hh,head);                                                             \\\n} while(0)\n\n#define HASH_TO_BKT( hashv, num_bkts, bkt )                                      \\\ndo {                                                                             \\\n  bkt = ((hashv) & ((num_bkts) - 1));                                            \\\n} while(0)\n\n/* delete \"delptr\" from the hash table.\n * \"the usual\" patch-up process for the app-order doubly-linked-list.\n * The use of _hd_hh_del below deserves special explanation.\n * These used to be expressed using (delptr) but that led to a bug\n * if someone used the same symbol for the head and deletee, like\n *  HASH_DELETE(hh,users,users);\n * We want that to work, but by changing the head (users) below\n * we were forfeiting our ability to further refer to the deletee (users)\n * in the patch-up process. Solution: use scratch space to\n * copy the deletee pointer, then the latter references are via that\n * scratch pointer rather than through the repointed (users) symbol.\n */\n#define HASH_DELETE(hh,head,delptr)                                              \\\ndo {                                                                             \\\n    unsigned _hd_bkt;                                                            \\\n    struct UT_hash_handle *_hd_hh_del;                                           \\\n    if ( ((delptr)->hh.prev == NULL) && ((delptr)->hh.next == NULL) )  {         \\\n        uthash_free((head)->hh.tbl->buckets,                                     \\\n                    (head)->hh.tbl->num_buckets*sizeof(struct UT_hash_bucket) ); \\\n        HASH_BLOOM_FREE((head)->hh.tbl);                                         \\\n        uthash_free((head)->hh.tbl, sizeof(UT_hash_table));                      \\\n        head = NULL;                                                             \\\n    } else {                                                                     \\\n        _hd_hh_del = &((delptr)->hh);                                            \\\n        if ((delptr) == ELMT_FROM_HH((head)->hh.tbl,(head)->hh.tbl->tail)) {     \\\n            (head)->hh.tbl->tail =                                               \\\n                (UT_hash_handle*)((ptrdiff_t)((delptr)->hh.prev) +               \\\n                (head)->hh.tbl->hho);                                            \\\n        }                                                                        \\\n        if ((delptr)->hh.prev) {                                                 \\\n            ((UT_hash_handle*)((ptrdiff_t)((delptr)->hh.prev) +                  \\\n                    (head)->hh.tbl->hho))->next = (delptr)->hh.next;             \\\n        } else {                                                                 \\\n            DECLTYPE_ASSIGN(head,(delptr)->hh.next);                             \\\n        }                                                                        \\\n        if (_hd_hh_del->next) {                                                  \\\n            ((UT_hash_handle*)((ptrdiff_t)_hd_hh_del->next +                     \\\n                    (head)->hh.tbl->hho))->prev =                                \\\n                    _hd_hh_del->prev;                                            \\\n        }                                                                        \\\n        HASH_TO_BKT( _hd_hh_del->hashv, (head)->hh.tbl->num_buckets, _hd_bkt);   \\\n        HASH_DEL_IN_BKT(hh,(head)->hh.tbl->buckets[_hd_bkt], _hd_hh_del);        \\\n        (head)->hh.tbl->num_items--;                                             \\\n    }                                                                            \\\n    HASH_FSCK(hh,head);                                                          \\\n} while (0)\n\n\n/* convenience forms of HASH_FIND/HASH_ADD/HASH_DEL */\n#define HASH_FIND_STR(head,findstr,out)                                          \\\n    HASH_FIND(hh,head,findstr,strlen(findstr),out)\n#define HASH_ADD_STR(head,strfield,add)                                          \\\n    HASH_ADD(hh,head,strfield,strlen(add->strfield),add)\n#define HASH_REPLACE_STR(head,strfield,add,replaced)                             \\\n  HASH_REPLACE(hh,head,strfield,strlen(add->strfield),add,replaced)\n#define HASH_FIND_INT(head,findint,out)                                          \\\n    HASH_FIND(hh,head,findint,sizeof(int),out)\n#define HASH_ADD_INT(head,intfield,add)                                          \\\n    HASH_ADD(hh,head,intfield,sizeof(int),add)\n#define HASH_REPLACE_INT(head,intfield,add,replaced)                             \\\n    HASH_REPLACE(hh,head,intfield,sizeof(int),add,replaced)\n#define HASH_FIND_PTR(head,findptr,out)                                          \\\n    HASH_FIND(hh,head,findptr,sizeof(void *),out)\n#define HASH_ADD_PTR(head,ptrfield,add)                                          \\\n    HASH_ADD(hh,head,ptrfield,sizeof(void *),add)\n#define HASH_REPLACE_PTR(head,ptrfield,add,replaced)                             \\\n    HASH_REPLACE(hh,head,ptrfield,sizeof(void *),add,replaced)\n#define HASH_DEL(head,delptr)                                                    \\\n    HASH_DELETE(hh,head,delptr)\n\n/* HASH_FSCK checks hash integrity on every add/delete when HASH_DEBUG is defined.\n * This is for uthash developer only; it compiles away if HASH_DEBUG isn't defined.\n */\n#ifdef HASH_DEBUG\n#define HASH_OOPS(...) do { fprintf(stderr,__VA_ARGS__); exit(-1); } while (0)\n#define HASH_FSCK(hh,head)                                                       \\\ndo {                                                                             \\\n    unsigned _bkt_i;                                                             \\\n    unsigned _count, _bkt_count;                                                 \\\n    char *_prev;                                                                 \\\n    struct UT_hash_handle *_thh;                                                 \\\n    if (head) {                                                                  \\\n        _count = 0;                                                              \\\n        for( _bkt_i = 0; _bkt_i < (head)->hh.tbl->num_buckets; _bkt_i++) {       \\\n            _bkt_count = 0;                                                      \\\n            _thh = (head)->hh.tbl->buckets[_bkt_i].hh_head;                      \\\n            _prev = NULL;                                                        \\\n            while (_thh) {                                                       \\\n               if (_prev != (char*)(_thh->hh_prev)) {                            \\\n                   HASH_OOPS(\"invalid hh_prev %p, actual %p\\n\",                  \\\n                    _thh->hh_prev, _prev );                                      \\\n               }                                                                 \\\n               _bkt_count++;                                                     \\\n               _prev = (char*)(_thh);                                            \\\n               _thh = _thh->hh_next;                                             \\\n            }                                                                    \\\n            _count += _bkt_count;                                                \\\n            if ((head)->hh.tbl->buckets[_bkt_i].count !=  _bkt_count) {          \\\n               HASH_OOPS(\"invalid bucket count %d, actual %d\\n\",                 \\\n                (head)->hh.tbl->buckets[_bkt_i].count, _bkt_count);              \\\n            }                                                                    \\\n        }                                                                        \\\n        if (_count != (head)->hh.tbl->num_items) {                               \\\n            HASH_OOPS(\"invalid hh item count %d, actual %d\\n\",                   \\\n                (head)->hh.tbl->num_items, _count );                             \\\n        }                                                                        \\\n        /* traverse hh in app order; check next/prev integrity, count */         \\\n        _count = 0;                                                              \\\n        _prev = NULL;                                                            \\\n        _thh =  &(head)->hh;                                                     \\\n        while (_thh) {                                                           \\\n           _count++;                                                             \\\n           if (_prev !=(char*)(_thh->prev)) {                                    \\\n              HASH_OOPS(\"invalid prev %p, actual %p\\n\",                          \\\n                    _thh->prev, _prev );                                         \\\n           }                                                                     \\\n           _prev = (char*)ELMT_FROM_HH((head)->hh.tbl, _thh);                    \\\n           _thh = ( _thh->next ?  (UT_hash_handle*)((char*)(_thh->next) +        \\\n                                  (head)->hh.tbl->hho) : NULL );                 \\\n        }                                                                        \\\n        if (_count != (head)->hh.tbl->num_items) {                               \\\n            HASH_OOPS(\"invalid app item count %d, actual %d\\n\",                  \\\n                (head)->hh.tbl->num_items, _count );                             \\\n        }                                                                        \\\n    }                                                                            \\\n} while (0)\n#else\n#define HASH_FSCK(hh,head) \n#endif\n\n/* When compiled with -DHASH_EMIT_KEYS, length-prefixed keys are emitted to \n * the descriptor to which this macro is defined for tuning the hash function.\n * The app can #include <unistd.h> to get the prototype for write(2). */\n#ifdef HASH_EMIT_KEYS\n#define HASH_EMIT_KEY(hh,head,keyptr,fieldlen)                                   \\\ndo {                                                                             \\\n    unsigned _klen = fieldlen;                                                   \\\n    write(HASH_EMIT_KEYS, &_klen, sizeof(_klen));                                \\\n    write(HASH_EMIT_KEYS, keyptr, fieldlen);                                     \\\n} while (0)\n#else \n#define HASH_EMIT_KEY(hh,head,keyptr,fieldlen)                    \n#endif\n\n/* default to Jenkin's hash unless overridden e.g. DHASH_FUNCTION=HASH_SAX */\n#ifdef HASH_FUNCTION \n#define HASH_FCN HASH_FUNCTION\n#else\n#define HASH_FCN HASH_JEN\n#endif\n\n/* The Bernstein hash function, used in Perl prior to v5.6 */\n#define HASH_BER(key,keylen,num_bkts,hashv,bkt)                                  \\\ndo {                                                                             \\\n  unsigned _hb_keylen=keylen;                                                    \\\n  char *_hb_key=(char*)(key);                                                    \\\n  (hashv) = 0;                                                                   \\\n  while (_hb_keylen--)  { (hashv) = ((hashv) * 33) + *_hb_key++; }               \\\n  bkt = (hashv) & (num_bkts-1);                                                  \\\n} while (0)\n\n\n/* SAX/FNV/OAT/JEN hash functions are macro variants of those listed at \n * http://eternallyconfuzzled.com/tuts/algorithms/jsw_tut_hashing.aspx */\n#define HASH_SAX(key,keylen,num_bkts,hashv,bkt)                                  \\\ndo {                                                                             \\\n  unsigned _sx_i;                                                                \\\n  char *_hs_key=(char*)(key);                                                    \\\n  hashv = 0;                                                                     \\\n  for(_sx_i=0; _sx_i < keylen; _sx_i++)                                          \\\n      hashv ^= (hashv << 5) + (hashv >> 2) + _hs_key[_sx_i];                     \\\n  bkt = hashv & (num_bkts-1);                                                    \\\n} while (0)\n\n#define HASH_FNV(key,keylen,num_bkts,hashv,bkt)                                  \\\ndo {                                                                             \\\n  unsigned _fn_i;                                                                \\\n  char *_hf_key=(char*)(key);                                                    \\\n  hashv = 2166136261UL;                                                          \\\n  for(_fn_i=0; _fn_i < keylen; _fn_i++)                                          \\\n      hashv = (hashv * 16777619) ^ _hf_key[_fn_i];                               \\\n  bkt = hashv & (num_bkts-1);                                                    \\\n} while(0) \n \n#define HASH_OAT(key,keylen,num_bkts,hashv,bkt)                                  \\\ndo {                                                                             \\\n  unsigned _ho_i;                                                                \\\n  char *_ho_key=(char*)(key);                                                    \\\n  hashv = 0;                                                                     \\\n  for(_ho_i=0; _ho_i < keylen; _ho_i++) {                                        \\\n      hashv += _ho_key[_ho_i];                                                   \\\n      hashv += (hashv << 10);                                                    \\\n      hashv ^= (hashv >> 6);                                                     \\\n  }                                                                              \\\n  hashv += (hashv << 3);                                                         \\\n  hashv ^= (hashv >> 11);                                                        \\\n  hashv += (hashv << 15);                                                        \\\n  bkt = hashv & (num_bkts-1);                                                    \\\n} while(0)\n\n#define HASH_JEN_MIX(a,b,c)                                                      \\\ndo {                                                                             \\\n  a -= b; a -= c; a ^= ( c >> 13 );                                              \\\n  b -= c; b -= a; b ^= ( a << 8 );                                               \\\n  c -= a; c -= b; c ^= ( b >> 13 );                                              \\\n  a -= b; a -= c; a ^= ( c >> 12 );                                              \\\n  b -= c; b -= a; b ^= ( a << 16 );                                              \\\n  c -= a; c -= b; c ^= ( b >> 5 );                                               \\\n  a -= b; a -= c; a ^= ( c >> 3 );                                               \\\n  b -= c; b -= a; b ^= ( a << 10 );                                              \\\n  c -= a; c -= b; c ^= ( b >> 15 );                                              \\\n} while (0)\n\n#define HASH_JEN(key,keylen,num_bkts,hashv,bkt)                                  \\\ndo {                                                                             \\\n  unsigned _hj_i,_hj_j,_hj_k;                                                    \\\n  unsigned char *_hj_key=(unsigned char*)(key);                                  \\\n  hashv = 0xfeedbeef;                                                            \\\n  _hj_i = _hj_j = 0x9e3779b9;                                                    \\\n  _hj_k = (unsigned)(keylen);                                                      \\\n  while (_hj_k >= 12) {                                                          \\\n    _hj_i +=    (_hj_key[0] + ( (unsigned)_hj_key[1] << 8 )                      \\\n        + ( (unsigned)_hj_key[2] << 16 )                                         \\\n        + ( (unsigned)_hj_key[3] << 24 ) );                                      \\\n    _hj_j +=    (_hj_key[4] + ( (unsigned)_hj_key[5] << 8 )                      \\\n        + ( (unsigned)_hj_key[6] << 16 )                                         \\\n        + ( (unsigned)_hj_key[7] << 24 ) );                                      \\\n    hashv += (_hj_key[8] + ( (unsigned)_hj_key[9] << 8 )                         \\\n        + ( (unsigned)_hj_key[10] << 16 )                                        \\\n        + ( (unsigned)_hj_key[11] << 24 ) );                                     \\\n                                                                                 \\\n     HASH_JEN_MIX(_hj_i, _hj_j, hashv);                                          \\\n                                                                                 \\\n     _hj_key += 12;                                                              \\\n     _hj_k -= 12;                                                                \\\n  }                                                                              \\\n  hashv += keylen;                                                               \\\n  switch ( _hj_k ) {                                                             \\\n     case 11: hashv += ( (unsigned)_hj_key[10] << 24 );                          \\\n     case 10: hashv += ( (unsigned)_hj_key[9] << 16 );                           \\\n     case 9:  hashv += ( (unsigned)_hj_key[8] << 8 );                            \\\n     case 8:  _hj_j += ( (unsigned)_hj_key[7] << 24 );                           \\\n     case 7:  _hj_j += ( (unsigned)_hj_key[6] << 16 );                           \\\n     case 6:  _hj_j += ( (unsigned)_hj_key[5] << 8 );                            \\\n     case 5:  _hj_j += _hj_key[4];                                               \\\n     case 4:  _hj_i += ( (unsigned)_hj_key[3] << 24 );                           \\\n     case 3:  _hj_i += ( (unsigned)_hj_key[2] << 16 );                           \\\n     case 2:  _hj_i += ( (unsigned)_hj_key[1] << 8 );                            \\\n     case 1:  _hj_i += _hj_key[0];                                               \\\n  }                                                                              \\\n  HASH_JEN_MIX(_hj_i, _hj_j, hashv);                                             \\\n  bkt = hashv & (num_bkts-1);                                                    \\\n} while(0)\n\n/* The Paul Hsieh hash function */\n#undef get16bits\n#if (defined(__GNUC__) && defined(__i386__)) || defined(__WATCOMC__)             \\\n  || defined(_MSC_VER) || defined (__BORLANDC__) || defined (__TURBOC__)\n#define get16bits(d) (*((const uint16_t *) (d)))\n#endif\n\n#if !defined (get16bits)\n#define get16bits(d) ((((uint32_t)(((const uint8_t *)(d))[1])) << 8)             \\\n                       +(uint32_t)(((const uint8_t *)(d))[0]) )\n#endif\n#define HASH_SFH(key,keylen,num_bkts,hashv,bkt)                                  \\\ndo {                                                                             \\\n  unsigned char *_sfh_key=(unsigned char*)(key);                                 \\\n  uint32_t _sfh_tmp, _sfh_len = keylen;                                          \\\n                                                                                 \\\n  int _sfh_rem = _sfh_len & 3;                                                   \\\n  _sfh_len >>= 2;                                                                \\\n  hashv = 0xcafebabe;                                                            \\\n                                                                                 \\\n  /* Main loop */                                                                \\\n  for (;_sfh_len > 0; _sfh_len--) {                                              \\\n    hashv    += get16bits (_sfh_key);                                            \\\n    _sfh_tmp       = (uint32_t)(get16bits (_sfh_key+2)) << 11  ^ hashv;          \\\n    hashv     = (hashv << 16) ^ _sfh_tmp;                                        \\\n    _sfh_key += 2*sizeof (uint16_t);                                             \\\n    hashv    += hashv >> 11;                                                     \\\n  }                                                                              \\\n                                                                                 \\\n  /* Handle end cases */                                                         \\\n  switch (_sfh_rem) {                                                            \\\n    case 3: hashv += get16bits (_sfh_key);                                       \\\n            hashv ^= hashv << 16;                                                \\\n            hashv ^= (uint32_t)(_sfh_key[sizeof (uint16_t)] << 18);              \\\n            hashv += hashv >> 11;                                                \\\n            break;                                                               \\\n    case 2: hashv += get16bits (_sfh_key);                                       \\\n            hashv ^= hashv << 11;                                                \\\n            hashv += hashv >> 17;                                                \\\n            break;                                                               \\\n    case 1: hashv += *_sfh_key;                                                  \\\n            hashv ^= hashv << 10;                                                \\\n            hashv += hashv >> 1;                                                 \\\n  }                                                                              \\\n                                                                                 \\\n    /* Force \"avalanching\" of final 127 bits */                                  \\\n    hashv ^= hashv << 3;                                                         \\\n    hashv += hashv >> 5;                                                         \\\n    hashv ^= hashv << 4;                                                         \\\n    hashv += hashv >> 17;                                                        \\\n    hashv ^= hashv << 25;                                                        \\\n    hashv += hashv >> 6;                                                         \\\n    bkt = hashv & (num_bkts-1);                                                  \\\n} while(0) \n\n#ifdef HASH_USING_NO_STRICT_ALIASING\n/* The MurmurHash exploits some CPU's (x86,x86_64) tolerance for unaligned reads.\n * For other types of CPU's (e.g. Sparc) an unaligned read causes a bus error.\n * MurmurHash uses the faster approach only on CPU's where we know it's safe. \n *\n * Note the preprocessor built-in defines can be emitted using:\n *\n *   gcc -m64 -dM -E - < /dev/null                  (on gcc)\n *   cc -## a.c (where a.c is a simple test file)   (Sun Studio)\n */\n#if (defined(__i386__) || defined(__x86_64__)  || defined(_M_IX86))\n#define MUR_GETBLOCK(p,i) p[i]\n#else /* non intel */\n#define MUR_PLUS0_ALIGNED(p) (((unsigned long)p & 0x3) == 0)\n#define MUR_PLUS1_ALIGNED(p) (((unsigned long)p & 0x3) == 1)\n#define MUR_PLUS2_ALIGNED(p) (((unsigned long)p & 0x3) == 2)\n#define MUR_PLUS3_ALIGNED(p) (((unsigned long)p & 0x3) == 3)\n#define WP(p) ((uint32_t*)((unsigned long)(p) & ~3UL))\n#if (defined(__BIG_ENDIAN__) || defined(SPARC) || defined(__ppc__) || defined(__ppc64__))\n#define MUR_THREE_ONE(p) ((((*WP(p))&0x00ffffff) << 8) | (((*(WP(p)+1))&0xff000000) >> 24))\n#define MUR_TWO_TWO(p)   ((((*WP(p))&0x0000ffff) <<16) | (((*(WP(p)+1))&0xffff0000) >> 16))\n#define MUR_ONE_THREE(p) ((((*WP(p))&0x000000ff) <<24) | (((*(WP(p)+1))&0xffffff00) >>  8))\n#else /* assume little endian non-intel */\n#define MUR_THREE_ONE(p) ((((*WP(p))&0xffffff00) >> 8) | (((*(WP(p)+1))&0x000000ff) << 24))\n#define MUR_TWO_TWO(p)   ((((*WP(p))&0xffff0000) >>16) | (((*(WP(p)+1))&0x0000ffff) << 16))\n#define MUR_ONE_THREE(p) ((((*WP(p))&0xff000000) >>24) | (((*(WP(p)+1))&0x00ffffff) <<  8))\n#endif\n#define MUR_GETBLOCK(p,i) (MUR_PLUS0_ALIGNED(p) ? ((p)[i]) :           \\\n                            (MUR_PLUS1_ALIGNED(p) ? MUR_THREE_ONE(p) : \\\n                             (MUR_PLUS2_ALIGNED(p) ? MUR_TWO_TWO(p) :  \\\n                                                      MUR_ONE_THREE(p))))\n#endif\n#define MUR_ROTL32(x,r) (((x) << (r)) | ((x) >> (32 - (r))))\n#define MUR_FMIX(_h) \\\ndo {                 \\\n  _h ^= _h >> 16;    \\\n  _h *= 0x85ebca6b;  \\\n  _h ^= _h >> 13;    \\\n  _h *= 0xc2b2ae35l; \\\n  _h ^= _h >> 16;    \\\n} while(0)\n\n#define HASH_MUR(key,keylen,num_bkts,hashv,bkt)                        \\\ndo {                                                                   \\\n  const uint8_t *_mur_data = (const uint8_t*)(key);                    \\\n  const int _mur_nblocks = (keylen) / 4;                               \\\n  uint32_t _mur_h1 = 0xf88D5353;                                       \\\n  uint32_t _mur_c1 = 0xcc9e2d51;                                       \\\n  uint32_t _mur_c2 = 0x1b873593;                                       \\\n  uint32_t _mur_k1 = 0;                                                \\\n  const uint8_t *_mur_tail;                                            \\\n  const uint32_t *_mur_blocks = (const uint32_t*)(_mur_data+_mur_nblocks*4); \\\n  int _mur_i;                                                          \\\n  for(_mur_i = -_mur_nblocks; _mur_i; _mur_i++) {                      \\\n    _mur_k1 = MUR_GETBLOCK(_mur_blocks,_mur_i);                        \\\n    _mur_k1 *= _mur_c1;                                                \\\n    _mur_k1 = MUR_ROTL32(_mur_k1,15);                                  \\\n    _mur_k1 *= _mur_c2;                                                \\\n                                                                       \\\n    _mur_h1 ^= _mur_k1;                                                \\\n    _mur_h1 = MUR_ROTL32(_mur_h1,13);                                  \\\n    _mur_h1 = _mur_h1*5+0xe6546b64;                                    \\\n  }                                                                    \\\n  _mur_tail = (const uint8_t*)(_mur_data + _mur_nblocks*4);            \\\n  _mur_k1=0;                                                           \\\n  switch((keylen) & 3) {                                               \\\n    case 3: _mur_k1 ^= _mur_tail[2] << 16;                             \\\n    case 2: _mur_k1 ^= _mur_tail[1] << 8;                              \\\n    case 1: _mur_k1 ^= _mur_tail[0];                                   \\\n    _mur_k1 *= _mur_c1;                                                \\\n    _mur_k1 = MUR_ROTL32(_mur_k1,15);                                  \\\n    _mur_k1 *= _mur_c2;                                                \\\n    _mur_h1 ^= _mur_k1;                                                \\\n  }                                                                    \\\n  _mur_h1 ^= (keylen);                                                 \\\n  MUR_FMIX(_mur_h1);                                                   \\\n  hashv = _mur_h1;                                                     \\\n  bkt = hashv & (num_bkts-1);                                          \\\n} while(0)\n#endif  /* HASH_USING_NO_STRICT_ALIASING */\n\n/* key comparison function; return 0 if keys equal */\n#define HASH_KEYCMP(a,b,len) memcmp(a,b,len) \n\n/* iterate over items in a known bucket to find desired item */\n#define HASH_FIND_IN_BKT(tbl,hh,head,keyptr,keylen_in,out)                       \\\ndo {                                                                             \\\n if (head.hh_head) DECLTYPE_ASSIGN(out,ELMT_FROM_HH(tbl,head.hh_head));          \\\n else out=NULL;                                                                  \\\n while (out) {                                                                   \\\n    if ((out)->hh.keylen == keylen_in) {                                           \\\n        if ((HASH_KEYCMP((out)->hh.key,keyptr,keylen_in)) == 0) break;             \\\n    }                                                                            \\\n    if ((out)->hh.hh_next) DECLTYPE_ASSIGN(out,ELMT_FROM_HH(tbl,(out)->hh.hh_next)); \\\n    else out = NULL;                                                             \\\n }                                                                               \\\n} while(0)\n\n/* add an item to a bucket  */\n#define HASH_ADD_TO_BKT(head,addhh)                                              \\\ndo {                                                                             \\\n head.count++;                                                                   \\\n (addhh)->hh_next = head.hh_head;                                                \\\n (addhh)->hh_prev = NULL;                                                        \\\n if (head.hh_head) { (head).hh_head->hh_prev = (addhh); }                        \\\n (head).hh_head=addhh;                                                           \\\n if (head.count >= ((head.expand_mult+1) * HASH_BKT_CAPACITY_THRESH)             \\\n     && (addhh)->tbl->noexpand != 1) {                                           \\\n       HASH_EXPAND_BUCKETS((addhh)->tbl);                                        \\\n }                                                                               \\\n} while(0)\n\n/* remove an item from a given bucket */\n#define HASH_DEL_IN_BKT(hh,head,hh_del)                                          \\\n    (head).count--;                                                              \\\n    if ((head).hh_head == hh_del) {                                              \\\n      (head).hh_head = hh_del->hh_next;                                          \\\n    }                                                                            \\\n    if (hh_del->hh_prev) {                                                       \\\n        hh_del->hh_prev->hh_next = hh_del->hh_next;                              \\\n    }                                                                            \\\n    if (hh_del->hh_next) {                                                       \\\n        hh_del->hh_next->hh_prev = hh_del->hh_prev;                              \\\n    }                                                                \n\n/* Bucket expansion has the effect of doubling the number of buckets\n * and redistributing the items into the new buckets. Ideally the\n * items will distribute more or less evenly into the new buckets\n * (the extent to which this is true is a measure of the quality of\n * the hash function as it applies to the key domain). \n * \n * With the items distributed into more buckets, the chain length\n * (item count) in each bucket is reduced. Thus by expanding buckets\n * the hash keeps a bound on the chain length. This bounded chain \n * length is the essence of how a hash provides constant time lookup.\n * \n * The calculation of tbl->ideal_chain_maxlen below deserves some\n * explanation. First, keep in mind that we're calculating the ideal\n * maximum chain length based on the *new* (doubled) bucket count.\n * In fractions this is just n/b (n=number of items,b=new num buckets).\n * Since the ideal chain length is an integer, we want to calculate \n * ceil(n/b). We don't depend on floating point arithmetic in this\n * hash, so to calculate ceil(n/b) with integers we could write\n * \n *      ceil(n/b) = (n/b) + ((n%b)?1:0)\n * \n * and in fact a previous version of this hash did just that.\n * But now we have improved things a bit by recognizing that b is\n * always a power of two. We keep its base 2 log handy (call it lb),\n * so now we can write this with a bit shift and logical AND:\n * \n *      ceil(n/b) = (n>>lb) + ( (n & (b-1)) ? 1:0)\n * \n */\n#define HASH_EXPAND_BUCKETS(tbl)                                                 \\\ndo {                                                                             \\\n    unsigned _he_bkt;                                                            \\\n    unsigned _he_bkt_i;                                                          \\\n    struct UT_hash_handle *_he_thh, *_he_hh_nxt;                                 \\\n    UT_hash_bucket *_he_new_buckets, *_he_newbkt;                                \\\n    _he_new_buckets = (UT_hash_bucket*)uthash_malloc(                            \\\n             2 * tbl->num_buckets * sizeof(struct UT_hash_bucket));              \\\n    if (!_he_new_buckets) { uthash_fatal( \"out of memory\"); }                    \\\n    memset(_he_new_buckets, 0,                                                   \\\n            2 * tbl->num_buckets * sizeof(struct UT_hash_bucket));               \\\n    tbl->ideal_chain_maxlen =                                                    \\\n       (tbl->num_items >> (tbl->log2_num_buckets+1)) +                           \\\n       ((tbl->num_items & ((tbl->num_buckets*2)-1)) ? 1 : 0);                    \\\n    tbl->nonideal_items = 0;                                                     \\\n    for(_he_bkt_i = 0; _he_bkt_i < tbl->num_buckets; _he_bkt_i++)                \\\n    {                                                                            \\\n        _he_thh = tbl->buckets[ _he_bkt_i ].hh_head;                             \\\n        while (_he_thh) {                                                        \\\n           _he_hh_nxt = _he_thh->hh_next;                                        \\\n           HASH_TO_BKT( _he_thh->hashv, tbl->num_buckets*2, _he_bkt);            \\\n           _he_newbkt = &(_he_new_buckets[ _he_bkt ]);                           \\\n           if (++(_he_newbkt->count) > tbl->ideal_chain_maxlen) {                \\\n             tbl->nonideal_items++;                                              \\\n             _he_newbkt->expand_mult = _he_newbkt->count /                       \\\n                                        tbl->ideal_chain_maxlen;                 \\\n           }                                                                     \\\n           _he_thh->hh_prev = NULL;                                              \\\n           _he_thh->hh_next = _he_newbkt->hh_head;                               \\\n           if (_he_newbkt->hh_head) _he_newbkt->hh_head->hh_prev =               \\\n                _he_thh;                                                         \\\n           _he_newbkt->hh_head = _he_thh;                                        \\\n           _he_thh = _he_hh_nxt;                                                 \\\n        }                                                                        \\\n    }                                                                            \\\n    uthash_free( tbl->buckets, tbl->num_buckets*sizeof(struct UT_hash_bucket) ); \\\n    tbl->num_buckets *= 2;                                                       \\\n    tbl->log2_num_buckets++;                                                     \\\n    tbl->buckets = _he_new_buckets;                                              \\\n    tbl->ineff_expands = (tbl->nonideal_items > (tbl->num_items >> 1)) ?         \\\n        (tbl->ineff_expands+1) : 0;                                              \\\n    if (tbl->ineff_expands > 1) {                                                \\\n        tbl->noexpand=1;                                                         \\\n        uthash_noexpand_fyi(tbl);                                                \\\n    }                                                                            \\\n    uthash_expand_fyi(tbl);                                                      \\\n} while(0)\n\n\n/* This is an adaptation of Simon Tatham's O(n log(n)) mergesort */\n/* Note that HASH_SORT assumes the hash handle name to be hh. \n * HASH_SRT was added to allow the hash handle name to be passed in. */\n#define HASH_SORT(head,cmpfcn) HASH_SRT(hh,head,cmpfcn)\n#define HASH_SRT(hh,head,cmpfcn)                                                 \\\ndo {                                                                             \\\n  unsigned _hs_i;                                                                \\\n  unsigned _hs_looping,_hs_nmerges,_hs_insize,_hs_psize,_hs_qsize;               \\\n  struct UT_hash_handle *_hs_p, *_hs_q, *_hs_e, *_hs_list, *_hs_tail;            \\\n  if (head) {                                                                    \\\n      _hs_insize = 1;                                                            \\\n      _hs_looping = 1;                                                           \\\n      _hs_list = &((head)->hh);                                                  \\\n      while (_hs_looping) {                                                      \\\n          _hs_p = _hs_list;                                                      \\\n          _hs_list = NULL;                                                       \\\n          _hs_tail = NULL;                                                       \\\n          _hs_nmerges = 0;                                                       \\\n          while (_hs_p) {                                                        \\\n              _hs_nmerges++;                                                     \\\n              _hs_q = _hs_p;                                                     \\\n              _hs_psize = 0;                                                     \\\n              for ( _hs_i = 0; _hs_i  < _hs_insize; _hs_i++ ) {                  \\\n                  _hs_psize++;                                                   \\\n                  _hs_q = (UT_hash_handle*)((_hs_q->next) ?                      \\\n                          ((void*)((char*)(_hs_q->next) +                        \\\n                          (head)->hh.tbl->hho)) : NULL);                         \\\n                  if (! (_hs_q) ) break;                                         \\\n              }                                                                  \\\n              _hs_qsize = _hs_insize;                                            \\\n              while ((_hs_psize > 0) || ((_hs_qsize > 0) && _hs_q )) {           \\\n                  if (_hs_psize == 0) {                                          \\\n                      _hs_e = _hs_q;                                             \\\n                      _hs_q = (UT_hash_handle*)((_hs_q->next) ?                  \\\n                              ((void*)((char*)(_hs_q->next) +                    \\\n                              (head)->hh.tbl->hho)) : NULL);                     \\\n                      _hs_qsize--;                                               \\\n                  } else if ( (_hs_qsize == 0) || !(_hs_q) ) {                   \\\n                      _hs_e = _hs_p;                                             \\\n                      if (_hs_p){                                                \\\n                        _hs_p = (UT_hash_handle*)((_hs_p->next) ?                \\\n                                ((void*)((char*)(_hs_p->next) +                  \\\n                                (head)->hh.tbl->hho)) : NULL);                   \\\n                       }                                                         \\\n                      _hs_psize--;                                               \\\n                  } else if ((                                                   \\\n                      cmpfcn(DECLTYPE(head)(ELMT_FROM_HH((head)->hh.tbl,_hs_p)), \\\n                             DECLTYPE(head)(ELMT_FROM_HH((head)->hh.tbl,_hs_q))) \\\n                             ) <= 0) {                                           \\\n                      _hs_e = _hs_p;                                             \\\n                      if (_hs_p){                                                \\\n                        _hs_p = (UT_hash_handle*)((_hs_p->next) ?                \\\n                               ((void*)((char*)(_hs_p->next) +                   \\\n                               (head)->hh.tbl->hho)) : NULL);                    \\\n                       }                                                         \\\n                      _hs_psize--;                                               \\\n                  } else {                                                       \\\n                      _hs_e = _hs_q;                                             \\\n                      _hs_q = (UT_hash_handle*)((_hs_q->next) ?                  \\\n                              ((void*)((char*)(_hs_q->next) +                    \\\n                              (head)->hh.tbl->hho)) : NULL);                     \\\n                      _hs_qsize--;                                               \\\n                  }                                                              \\\n                  if ( _hs_tail ) {                                              \\\n                      _hs_tail->next = ((_hs_e) ?                                \\\n                            ELMT_FROM_HH((head)->hh.tbl,_hs_e) : NULL);          \\\n                  } else {                                                       \\\n                      _hs_list = _hs_e;                                          \\\n                  }                                                              \\\n                  if (_hs_e) {                                                   \\\n                  _hs_e->prev = ((_hs_tail) ?                                    \\\n                     ELMT_FROM_HH((head)->hh.tbl,_hs_tail) : NULL);              \\\n                  }                                                              \\\n                  _hs_tail = _hs_e;                                              \\\n              }                                                                  \\\n              _hs_p = _hs_q;                                                     \\\n          }                                                                      \\\n          if (_hs_tail){                                                         \\\n            _hs_tail->next = NULL;                                               \\\n          }                                                                      \\\n          if ( _hs_nmerges <= 1 ) {                                              \\\n              _hs_looping=0;                                                     \\\n              (head)->hh.tbl->tail = _hs_tail;                                   \\\n              DECLTYPE_ASSIGN(head,ELMT_FROM_HH((head)->hh.tbl, _hs_list));      \\\n          }                                                                      \\\n          _hs_insize *= 2;                                                       \\\n      }                                                                          \\\n      HASH_FSCK(hh,head);                                                        \\\n }                                                                               \\\n} while (0)\n\n/* This function selects items from one hash into another hash. \n * The end result is that the selected items have dual presence \n * in both hashes. There is no copy of the items made; rather \n * they are added into the new hash through a secondary hash \n * hash handle that must be present in the structure. */\n#define HASH_SELECT(hh_dst, dst, hh_src, src, cond)                              \\\ndo {                                                                             \\\n  unsigned _src_bkt, _dst_bkt;                                                   \\\n  void *_last_elt=NULL, *_elt;                                                   \\\n  UT_hash_handle *_src_hh, *_dst_hh, *_last_elt_hh=NULL;                         \\\n  ptrdiff_t _dst_hho = ((char*)(&(dst)->hh_dst) - (char*)(dst));                 \\\n  if (src) {                                                                     \\\n    for(_src_bkt=0; _src_bkt < (src)->hh_src.tbl->num_buckets; _src_bkt++) {     \\\n      for(_src_hh = (src)->hh_src.tbl->buckets[_src_bkt].hh_head;                \\\n          _src_hh;                                                               \\\n          _src_hh = _src_hh->hh_next) {                                          \\\n          _elt = ELMT_FROM_HH((src)->hh_src.tbl, _src_hh);                       \\\n          if (cond(_elt)) {                                                      \\\n            _dst_hh = (UT_hash_handle*)(((char*)_elt) + _dst_hho);               \\\n            _dst_hh->key = _src_hh->key;                                         \\\n            _dst_hh->keylen = _src_hh->keylen;                                   \\\n            _dst_hh->hashv = _src_hh->hashv;                                     \\\n            _dst_hh->prev = _last_elt;                                           \\\n            _dst_hh->next = NULL;                                                \\\n            if (_last_elt_hh) { _last_elt_hh->next = _elt; }                     \\\n            if (!dst) {                                                          \\\n              DECLTYPE_ASSIGN(dst,_elt);                                         \\\n              HASH_MAKE_TABLE(hh_dst,dst);                                       \\\n            } else {                                                             \\\n              _dst_hh->tbl = (dst)->hh_dst.tbl;                                  \\\n            }                                                                    \\\n            HASH_TO_BKT(_dst_hh->hashv, _dst_hh->tbl->num_buckets, _dst_bkt);    \\\n            HASH_ADD_TO_BKT(_dst_hh->tbl->buckets[_dst_bkt],_dst_hh);            \\\n            (dst)->hh_dst.tbl->num_items++;                                      \\\n            _last_elt = _elt;                                                    \\\n            _last_elt_hh = _dst_hh;                                              \\\n          }                                                                      \\\n      }                                                                          \\\n    }                                                                            \\\n  }                                                                              \\\n  HASH_FSCK(hh_dst,dst);                                                         \\\n} while (0)\n\n#define HASH_CLEAR(hh,head)                                                      \\\ndo {                                                                             \\\n  if (head) {                                                                    \\\n    uthash_free((head)->hh.tbl->buckets,                                         \\\n                (head)->hh.tbl->num_buckets*sizeof(struct UT_hash_bucket));      \\\n    HASH_BLOOM_FREE((head)->hh.tbl);                                             \\\n    uthash_free((head)->hh.tbl, sizeof(UT_hash_table));                          \\\n    (head)=NULL;                                                                 \\\n  }                                                                              \\\n} while(0)\n\n#define HASH_OVERHEAD(hh,head)                                                   \\\n (size_t)((((head)->hh.tbl->num_items   * sizeof(UT_hash_handle))   +            \\\n           ((head)->hh.tbl->num_buckets * sizeof(UT_hash_bucket))   +            \\\n            (sizeof(UT_hash_table))                                 +            \\\n            (HASH_BLOOM_BYTELEN)))\n\n#ifdef NO_DECLTYPE\n#define HASH_ITER(hh,head,el,tmp)                                                \\\nfor((el)=(head), (*(char**)(&(tmp)))=(char*)((head)?(head)->hh.next:NULL);       \\\n  el; (el)=(tmp),(*(char**)(&(tmp)))=(char*)((tmp)?(tmp)->hh.next:NULL)) \n#else\n#define HASH_ITER(hh,head,el,tmp)                                                \\\nfor((el)=(head),(tmp)=DECLTYPE(el)((head)?(head)->hh.next:NULL);                 \\\n  el; (el)=(tmp),(tmp)=DECLTYPE(el)((tmp)?(tmp)->hh.next:NULL))\n#endif\n\n/* obtain a count of items in the hash */\n#define HASH_COUNT(head) HASH_CNT(hh,head) \n#define HASH_CNT(hh,head) ((head)?((head)->hh.tbl->num_items):0)\n\ntypedef struct UT_hash_bucket {\n   struct UT_hash_handle *hh_head;\n   unsigned count;\n\n   /* expand_mult is normally set to 0. In this situation, the max chain length\n    * threshold is enforced at its default value, HASH_BKT_CAPACITY_THRESH. (If\n    * the bucket's chain exceeds this length, bucket expansion is triggered). \n    * However, setting expand_mult to a non-zero value delays bucket expansion\n    * (that would be triggered by additions to this particular bucket)\n    * until its chain length reaches a *multiple* of HASH_BKT_CAPACITY_THRESH.\n    * (The multiplier is simply expand_mult+1). The whole idea of this\n    * multiplier is to reduce bucket expansions, since they are expensive, in\n    * situations where we know that a particular bucket tends to be overused.\n    * It is better to let its chain length grow to a longer yet-still-bounded\n    * value, than to do an O(n) bucket expansion too often. \n    */\n   unsigned expand_mult;\n\n} UT_hash_bucket;\n\n/* random signature used only to find hash tables in external analysis */\n#define HASH_SIGNATURE 0xa0111fe1\n#define HASH_BLOOM_SIGNATURE 0xb12220f2\n\ntypedef struct UT_hash_table {\n   UT_hash_bucket *buckets;\n   unsigned num_buckets, log2_num_buckets;\n   unsigned num_items;\n   struct UT_hash_handle *tail; /* tail hh in app order, for fast append    */\n   ptrdiff_t hho; /* hash handle offset (byte pos of hash handle in element */\n\n   /* in an ideal situation (all buckets used equally), no bucket would have\n    * more than ceil(#items/#buckets) items. that's the ideal chain length. */\n   unsigned ideal_chain_maxlen;\n\n   /* nonideal_items is the number of items in the hash whose chain position\n    * exceeds the ideal chain maxlen. these items pay the penalty for an uneven\n    * hash distribution; reaching them in a chain traversal takes >ideal steps */\n   unsigned nonideal_items;\n\n   /* ineffective expands occur when a bucket doubling was performed, but \n    * afterward, more than half the items in the hash had nonideal chain\n    * positions. If this happens on two consecutive expansions we inhibit any\n    * further expansion, as it's not helping; this happens when the hash\n    * function isn't a good fit for the key domain. When expansion is inhibited\n    * the hash will still work, albeit no longer in constant time. */\n   unsigned ineff_expands, noexpand;\n\n   uint32_t signature; /* used only to find hash tables in external analysis */\n#ifdef HASH_BLOOM\n   uint32_t bloom_sig; /* used only to test bloom exists in external analysis */\n   uint8_t *bloom_bv;\n   char bloom_nbits;\n#endif\n\n} UT_hash_table;\n\ntypedef struct UT_hash_handle {\n   struct UT_hash_table *tbl;\n   void *prev;                       /* prev element in app order      */\n   void *next;                       /* next element in app order      */\n   struct UT_hash_handle *hh_prev;   /* previous hh in bucket order    */\n   struct UT_hash_handle *hh_next;   /* next hh in bucket order        */\n   void *key;                        /* ptr to enclosing struct's key  */\n   unsigned keylen;                  /* enclosing struct's key len     */\n   unsigned hashv;                   /* result of hash-fcn(key)        */\n} UT_hash_handle;\n\n#endif /* UTHASH_H */\n"
  },
  {
    "path": "user_space/link_perf_test.sh",
    "content": "#!/bin/bash\n\n# Author: Michael Mehari\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\nPL_MIN=100\nPL_INC=100\nPL_MAX=1500\nPAYLOAD=( $(seq -s' ' $PL_MIN $PL_INC $PL_MAX) ) # paload size in bytes\nMCS_BPS=( 6 9 12 18 24 36 48 54 )\nMCS_IDX=( 4 5  6  7  8  9 10 11 )\n\nINTERVAL=0.001\t# Wait interval seconds between sending each packet\nPKT_CNT=700\t\t# Stop after sending count ECHO_REQUEST packets\nDEADLINE=1\t\t# Specify a timeout, in seconds, before ping exits regardless of how many packets have been sent or received\n\nSDRCTL_EXEC=\"./sdrctl_src/sdrctl\"\nCLIENT_IP=\"192.168.13.2\"\n\n# Bandwidth = 1.4 MHz\nprintf \"LINK PERFORMANCE TEST\\n\"\nprintf \"=====================\\n\"\nprintf \"RATE/PL\\t\"\nfor (( j = 0 ; j < ${#PAYLOAD[@]} ; j++ )) do\n\tprintf \"%*s\" 12 \"${PAYLOAD[j]}\"\ndone\nprintf \"\\n\"\n\nfor (( i = 0 ; i < ${#MCS_IDX[@]} ; i++ )) do\n\n\t# configure MCS\n\t$SDRCTL_EXEC dev sdr0 set reg drv_tx 0 ${MCS_IDX[$i]} > /dev/null\n\n\tprintf \"%sMbps\\t\" ${MCS_BPS[$i]}\n\tfor (( j = 0 ; j < ${#PAYLOAD[@]} ; j++ )) do\n\n\t\t# Measure link performance\n\t\tlink_per_str=$(ping $CLIENT_IP -i $INTERVAL -c $PKT_CNT -w $DEADLINE -s ${PAYLOAD[$j]} -nq | while read line; do\n\n\t\t\t# Skip non packet-loss and non rtt responses\n\t\t\t[[ ! \"$line\" =~ \"packet loss\" ]] && [[ ! \"$line\" =~ \"rtt\" ]] && continue\n\n\t\t\t# Extract packet loss\n\t\t\tif [[ \"$line\" =~ \"packet loss\" ]]; then\n\t\t\t\tPL=$(echo $line | grep 'packet loss' | cut -d' ' -f6)\n\t\t\t\tif [[ $PL == \"100%\" ]]; then\n\t\t\t\t\tprintf \"%s,INF\" $PL\n\t\t\t\telse\n\t\t\t\t\tprintf \"%s,\" $PL\n\t\t\t\tfi\n\t\t\t# Extract rtt\n\t\t\telse\n\t\t\t\tRTT=$(echo $line | grep rtt | cut -d/ -f5)\n\t\t\t\tprintf \"%s\" $RTT\n\t\t\tfi\n\n\t\tdone)\n\t\tprintf \"%*s\" 12 $link_per_str\n\tdone\n\tprintf \"\\n\"\ndone\n\n"
  },
  {
    "path": "user_space/load_fpga_img.sh",
    "content": "#!/bin/bash\n\n# Author: Xianjun Jiao\n# SPDX-FileCopyrightText: 2022 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\n# get fpga image file name\nif [[ -n $1 ]]; then\n  fpga_img_filename=$1\nelse\n  fpga_img_filename=system_top.bit.bin\nfi\n\nfpga_type=$(cat /proc/device-tree/compatible)\nfpga_img_filename_core=${fpga_img_filename##*/}\necho $fpga_type\necho $fpga_img_filename\necho $fpga_img_filename_core\n\nset -x\n\nifconfig sdr0 down\nrmmod sdr\n# rmmod mac80211\n# rmmod cfg80211\n# rmmod ad9361_drv\n# rmmod xilinx_dma.ko\nrmmod openofdm_rx\nrmmod openofdm_tx\nrmmod rx_intf\nrmmod tx_intf\nrmmod xpu\n\nsleep 1\n\nif [ -f \"$fpga_img_filename\" ]; then\n  echo 0 > /sys/class/fpga_manager/fpga0/flags\n  mkdir -p /lib/firmware\n  cp $fpga_img_filename /lib/firmware/ -rf\n  echo $fpga_img_filename_core > /sys/class/fpga_manager/fpga0/firmware\nfi\n\nif true; then # only AD9361 RF need reset/re-connect currently\n\n  # insmod ad9361_drv.ko\n  # sleep 1\n\n  if [ \"$fpga_type\" != \"xlnx,zynq-7000\" ]; then\n    SPI_DEVNAME=\"spi1.0\"\n    DDS_DEVNAME=\"99024000.cf-ad9361-dds-core-lpc\"\n    ADC_DEVNAME=\"99020000.cf-ad9361-lpc\"\n  else\n    SPI_DEVNAME=\"spi0.0\"\n    DDS_DEVNAME=\"79024000.cf-ad9361-dds-core-lpc\"\n    ADC_DEVNAME=\"79020000.cf-ad9361-lpc\"\n  fi\n\n  while [ ! -d \"/sys/bus/spi/drivers/ad9361/$SPI_DEVNAME\" ]\n  do\n    echo \"Waiting for /sys/bus/spi/drivers/ad9361/$SPI_DEVNAME\"\n    sleep 0.2\n  done\n  cd /sys/bus/spi/drivers/ad9361/\n  echo $SPI_DEVNAME > unbind\n  echo $SPI_DEVNAME > bind\n\n  #while [ ! -d \"/sys/bus/platform/drivers/cf_axi_dds/$DDS_DEVNAME\" ]\n  #do\n  #   echo \"Waiting for /sys/bus/platform/drivers/cf_axi_dds/$DDS_DEVNAME\"\n  #   sleep 0.2\n  #done\n  #cd /sys/bus/platform/drivers/cf_axi_dds/\n  #echo $DDS_DEVNAME  > unbind\n  #echo $DDS_DEVNAME  > bind\n\n  while [ ! -d \"/sys/bus/platform/drivers/cf_axi_adc/$ADC_DEVNAME\" ]\n  do\n    echo \"Waiting for /sys/bus/platform/drivers/cf_axi_adc/$ADC_DEVNAME\"\n    sleep 0.2\n  done\n  cd /sys/bus/platform/drivers/cf_axi_adc/\n  echo $ADC_DEVNAME  > unbind\n  echo $ADC_DEVNAME  > bind\n\nfi\n\nset +x\n"
  },
  {
    "path": "user_space/monitor_ch.sh",
    "content": "#!/bin/bash\n\n# Author: Xianjun Jiao\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\nif [ $# -ne 2 ]\n  then\n    echo \"Please input NIC_name ch_number as input parameter!\"\n    exit\nfi\n\nnic_name=$1\nch_number=$2\necho $nic_name\necho $ch_number\n\n# sudo service network-manager stop\nsudo ip link set $nic_name down\nsudo iwconfig $nic_name mode monitor\nsudo ip link set $nic_name up\nsudo iwconfig $nic_name channel $ch_number\n# sudo iwconfig $nic_name modulation 11g\n# sudo iwconfig $nic_name rate 6M\nifconfig\niwconfig $nic_name\n\n./agc_settings.sh 1\n"
  },
  {
    "path": "user_space/nav_disable.sh",
    "content": "#!/bin/bash\n\nhome_dir=$(pwd)\n\nif test -d \"/sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\"; then\n  cd /sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\nelse \n  cd /sys/devices/soc0/fpga-axi\\@0/fpga-axi\\@0\\:sdr\nfi\n\nset -x\n#set\nif [[ -n $1 ]]; then\n  echo \"0$1\" > csma_cfg0\nfi\n\n# show\ncat csma_cfg0\nset +x\n\ncd $home_dir\n"
  },
  {
    "path": "user_space/nic_back_to_normal.sh",
    "content": "#!/bin/bash\n\n# Author: Xianjun Jiao\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\nif [ $# -ne 1 ]\n  then\n    echo \"Please input NIC name as input parameter!\"\n    exit\nfi\n\nnic_name=$1\necho $nic_name\n\n# sudo service network-manager stop\nsudo ip link set $nic_name down\nsudo iwconfig $nic_name mode managed\n#sudo iwconfig $nic_name modulation 11g\nsudo ip link set $nic_name up\nifconfig\niwconfig $nic_name\n\n./agc_settings.sh 1\n"
  },
  {
    "path": "user_space/openwifi_ad9361_fir.ftr",
    "content": "# Data Sample Frequency = 40000000 Hz\nTX 3 GAIN 0 INT 1\nRX 3 GAIN -6 DEC 1\nRTX 1280000000 160000000 80000000 40000000 40000000 40000000\nRRX 1280000000 160000000 80000000 40000000 40000000 40000000\nBWTX 35301580\nBWRX 20172411\n-2628,-2628\n2130,2130\n1397,1397\n-487,-487\n-1098,-1098\n865,865\n2132,2132\n-112,-112\n-2468,-2468\n-169,-169\n3686,3686\n1455,1455\n-5304,-5304\n-4052,-4052\n11297,11297\n27949,27949\n27949,27949\n11297,11297\n-4052,-4052\n-5304,-5304\n1455,1455\n3686,3686\n-169,-169\n-2468,-2468\n-112,-112\n2132,2132\n865,865\n-1098,-1098\n-487,-487\n1397,1397\n2130,2130\n-2628,-2628\n"
  },
  {
    "path": "user_space/openwifi_ad9361_fir_tx_0MHz.ftr",
    "content": "# Data Sample Frequency = 40000000 Hz\nTX 3 GAIN 0 INT 1\nRX 3 GAIN -6 DEC 1\nRTX 1280000000 160000000 80000000 40000000 40000000 40000000\nRRX 1280000000 160000000 80000000 40000000 40000000 40000000\n# BWTX 35301580\nBWTX 20172411\nBWRX 20172411\n-2628,-2628\n2130,2130\n1397,1397\n-487,-487\n-1098,-1098\n865,865\n2132,2132\n-112,-112\n-2468,-2468\n-169,-169\n3686,3686\n1455,1455\n-5304,-5304\n-4052,-4052\n11297,11297\n27949,27949\n27949,27949\n11297,11297\n-4052,-4052\n-5304,-5304\n1455,1455\n3686,3686\n-169,-169\n-2468,-2468\n-112,-112\n2132,2132\n865,865\n-1098,-1098\n-487,-487\n1397,1397\n2130,2130\n-2628,-2628\n"
  },
  {
    "path": "user_space/openwifi_ad9361_fir_tx_0MHz_11n.ftr",
    "content": "# Generated with AD9361 Filter Design Wizard 16.1.3\r\n# MATLAB 9.10.0.1602886 (R2021a), 18-Nov-2021 11:34:55\r\n# Rx setting:\r\n# Data Rate 40, Clock (MHz) ADC 320 DAC 320 1x\r\n# PLL Div 4x, PLL (MHz) 1280\r\n# Units: dB. Apass 0.5, Astop 80, Astop (FIR) 0\r\n# Units: MHz. Fpass 8.75, Fstop 11.25, Fcutoff (Analog) 15.6896, RF Bandwidth 22.4138\r\n# AD936x Decimation Rates. Use Internal FIR. FIR 1X 40, HB1 2X 80, HB2 2X 160, HB3 2X 320\r\n# Tx setting:\r\n# Data Rate 40, Clock (MHz) ADC 320 DAC 320 1x\r\n# PLL Div 4x, PLL (MHz) 1280\r\n# Units: dB. Apass 0.5, Astop 80, Astop (FIR) 0\r\n# Units: MHz. Fpass 8.75, Fstop 11.25, Fcutoff (Analog) 17.6508, RF Bandwidth 22.0636\r\n# AD936x Interpolation Rates. Use Internal FIR. FIR 1X 40, HB1 2X 80, HB2 2X 160, HB3 2X 320\r\nTX 3 GAIN -6 INT 1\r\nRX 3 GAIN -6 DEC 1\r\nRTX 1280000000 320000000 160000000 80000000 40000000 40000000\r\nRRX 1280000000 320000000 160000000 80000000 40000000 40000000\r\nBWTX 25215414\r\nBWRX 25215513\r\n41,56\r\n31,70\r\n-187,-148\r\n-496,-500\r\n-395,-434\r\n183,169\r\n412,436\r\n-201,-208\r\n-619,-674\r\n148,137\r\n886,956\r\n-38,-14\r\n-1232,-1325\r\n-166,-214\r\n1680,1799\r\n513,598\r\n-2284,-2437\r\n-1107,-1255\r\n3197,3389\r\n2238,2507\r\n-4904,-5127\r\n-5068,-5623\r\n10562,10560\r\n28812,29674\r\n28812,29674\r\n10562,10560\r\n-5068,-5623\r\n-4904,-5127\r\n2238,2507\r\n3197,3389\r\n-1107,-1255\r\n-2284,-2437\r\n513,598\r\n1680,1799\r\n-166,-214\r\n-1232,-1325\r\n-38,-14\r\n886,956\r\n148,137\r\n-619,-674\r\n-201,-208\r\n412,436\r\n183,169\r\n-395,-434\r\n-496,-500\r\n-187,-148\r\n31,70\r\n41,56\r\n"
  },
  {
    "path": "user_space/openwifi_ad9361_fir_tx_0MHz_11n_narrow1.ftr",
    "content": "# Generated with AD9361 Filter Design Wizard 16.1.3\r\n# MATLAB 9.10.0.1602886 (R2021a), 31-Oct-2022 15:56:07\r\n# Rx setting:\r\n# Data Rate 40, Clock (MHz) ADC 320 DAC 320 1x\r\n# PLL Div 4x, PLL (MHz) 1280\r\n# Units: dB. Apass 0.5, Astop 120, Astop (FIR) 0\r\n# Units: MHz. Fpass 8.75, Fstop 12.1, Fcutoff (Analog) 15.6896, RF Bandwidth 22.4138\r\n# AD936x Decimation Rates. Use Internal FIR. FIR 1X 40, HB1 2X 80, HB2 2X 160, HB3 2X 320\r\n# Tx setting:\r\n# Data Rate 40, Clock (MHz) ADC 320 DAC 320 1x\r\n# PLL Div 4x, PLL (MHz) 1280\r\n# Units: dB. Apass 0.5, Astop 80, Astop (FIR) 0\r\n# Units: MHz. Fpass 8.75, Fstop 11.25, Fcutoff (Analog) 17.6508, RF Bandwidth 22.0636\r\n# AD936x Interpolation Rates. Use Internal FIR. FIR 1X 40, HB1 2X 80, HB2 2X 160, HB3 2X 320\r\nTX 3 GAIN -6 INT 1\r\nRX 3 GAIN -6 DEC 1\r\nRTX 1280000000 320000000 160000000 80000000 40000000 40000000\r\nRRX 1280000000 320000000 160000000 80000000 40000000 40000000\r\nBWTX 25215414\r\nBWRX 25215513\r\n41,-12\r\n31,-90\r\n-187,-279\r\n-496,-446\r\n-395,-280\r\n183,212\r\n412,395\r\n-201,-140\r\n-619,-571\r\n148,58\r\n886,827\r\n-38,87\r\n-1232,-1169\r\n-166,-334\r\n1680,1622\r\n513,740\r\n-2284,-2242\r\n-1107,-1417\r\n3197,3181\r\n2238,2687\r\n-4904,-4913\r\n-5068,-5819\r\n10562,10346\r\n28812,29882\r\n28812,29882\r\n10562,10346\r\n-5068,-5819\r\n-4904,-4913\r\n2238,2687\r\n3197,3181\r\n-1107,-1417\r\n-2284,-2242\r\n513,740\r\n1680,1622\r\n-166,-334\r\n-1232,-1169\r\n-38,87\r\n886,827\r\n148,58\r\n-619,-571\r\n-201,-140\r\n412,395\r\n183,212\r\n-395,-280\r\n-496,-446\r\n-187,-279\r\n31,-90\r\n41,-12\r\n"
  },
  {
    "path": "user_space/populate_driver_userspace.sh",
    "content": "#!/bin/bash\n\n# Author: Xianjun Jiao\n# SPDX-FileCopyrightText: 2024 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\nset -ex\n\ntar xvf openwifi.tar.gz\n"
  },
  {
    "path": "user_space/populate_kernel_image_module_reboot.sh",
    "content": "#!/bin/bash\n\n# Author: Xianjun Jiao\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\nset -ex\n\nMACHINE_TYPE=`uname -m`\n\nmkdir -p kernel_modules\nrm -rf kernel_modules/*\ntar -zxvf kernel_modules.tar.gz\n\nif [ ${MACHINE_TYPE} == 'aarch64' ]; then\n    IMAGE_FILENAME=Image\n    DTB_FILENAME=\"system.dtb\"\nelse\n    IMAGE_FILENAME=uImage\n    DTB_FILENAME=\"devicetree.dtb\"\nfi\n\nmv ./kernel_modules/ad9361_drv.ko ./openwifi/ -f || true\nmv ./kernel_modules/adi_axi_hdmi.ko ./openwifi/ -f || true\nmv ./kernel_modules/axidmatest.ko ./openwifi/ -f || true\nmv ./kernel_modules/lcd.ko ./openwifi/ -f || true\nmv ./kernel_modules/xilinx_dma.ko ./openwifi/ -f || true\nmv ./openwifi/system_top.bit.bin ./openwifi/system_top.bit.bin.bak -f || true\n\nrm -rf /lib/modules/$(uname -r)\nln -s /root/kernel_modules /lib/modules/$(uname -r)\n\ndepmod\n\numount /mnt || /bin/true\nmount /dev/mmcblk0p1 /mnt\nif test -f \"./kernel_modules/$IMAGE_FILENAME\"; then\n    cp ./kernel_modules/$IMAGE_FILENAME /mnt/\nfi\nif test -f \"./kernel_modules/BOOT.BIN\"; then\n    cp ./kernel_modules/BOOT.BIN /mnt/\nfi\nif test -f \"./kernel_modules/$DTB_FILENAME\"; then\n    cp ./kernel_modules/$DTB_FILENAME /mnt/\nfi\ncd /mnt/\nsync\ncd ~\numount /mnt\n\nreboot now\n"
  },
  {
    "path": "user_space/post_config.sh",
    "content": "#!/bin/bash\n\n# Author: Xianjun Jiao\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\nset -ex\n\nMACHINE_TYPE=`uname -m`\n\n# setup kernel module directory\nif [ -d \"/lib/modules/$(uname -r)\" ]; then\n    echo \"/lib/modules/$(uname -r) already exists.\"\nelse\n    if [ ${MACHINE_TYPE} == 'aarch64' ]; then\n        ln -s /lib/modules/adi-linux-64 /lib/modules/$(uname -r)\n    else\n        ln -s /lib/modules/adi-linux /lib/modules/$(uname -r)\n    fi\nfi\ndepmod\nmodprobe mac80211\n\nif [ ${MACHINE_TYPE} == 'aarch64' ]; then\n    cp ~/openwifi/drv64/* ~/openwifi/ -rf\nelse\n    cp ~/openwifi/drv32/* ~/openwifi/ -rf\nfi\n\n# add gateway (PC) for internet access\nroute add default gw 192.168.10.1 || true\n\nsudo apt update\n\nchmod +x *.sh\n\n# build sdrctl\nsudo apt-get -y install libnl-3-dev\nsudo apt-get -y install libnl-genl-3-dev\ncd sdrctl_src\nmake\ncp sdrctl ../\ncd ../side_ch_ctl_src/\ngcc -o side_ch_ctl side_ch_ctl.c\ncp side_ch_ctl ../\ncd ..\n\n# install and setup dhcp server\nsudo apt-get -y install isc-dhcp-server\ncp dhcpd.conf /etc/dhcp/dhcpd.conf\n\n# install hostapd and other useful tools\nsudo apt-get -y install hostapd\nsudo apt-get -y install nano\nsudo apt-get -y install tcpdump\nsudo apt-get -y install webfs\nsudo apt-get -y install iperf\nsudo apt-get -y install iperf3\nsudo apt-get -y install libpcap-dev\nsudo apt-get -y install bridge-utils\n\ncd ./inject_80211/\nmake\n\n# change the root password to openwifi\ncat /etc/passwd\nsed -i 's/root:x:0:0:root:\\/root:\\/bin\\/bash/root::0:0:root:\\/root:\\/bin\\/bash/' /etc/passwd\nsync\nsleep 1\ncat /etc/passwd\necho -e \"openwifi\\nopenwifi\" | passwd\nsync\nsleep 1\ncat /etc/passwd\n\n"
  },
  {
    "path": "user_space/prepare_kernel.sh",
    "content": "  \n#!/bin/bash\n\n# Author: Xianjun Jiao\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\n# ATTENTION! You need Vitis, NOT Vitis_HLS, installed\n\n# if [ \"$#\" -ne 1 ]; then\n#     echo \"You must enter 1 arguments: ARCH_BIT(32 or 64)\"\n#     exit 1\n# fi\n\n# OPENWIFI_DIR=$(pwd)/../\n# ARCH_OPTION=$1\n\nif [ \"$#\" -ne 2 ]; then\n    echo \"You must enter 2 arguments: \\$XILINX_DIR ARCH_BIT(32 or 64)\"\n    exit 1\nfi\n\nOPENWIFI_DIR=$(pwd)/../\nXILINX_DIR=$1\nARCH_OPTION=$2\n\nif [ -f \"$OPENWIFI_DIR/LICENSE\" ]; then\n    echo \"\\$OPENWIFI_DIR is found!\"\nelse\n    echo \"\\$OPENWIFI_DIR is not correct. Please check!\"\n    exit 1\nfi\n\nif [ -d \"$XILINX_DIR/Vitis\" ]; then\n    echo \"\\$XILINX_DIR is found!\"\nelse\n    echo \"\\$XILINX_DIR is not correct. Please check!\"\n    exit 1\nfi\n\nif [ \"$ARCH_OPTION\" != \"32\" ] && [ \"$ARCH_OPTION\" != \"64\" ]; then\n    echo \"\\$ARCH_OPTION is not correct. Should be 32 or 64. Please check!\"\n    exit 1\nelse\n    echo \"\\$ARCH_OPTION is valid!\"\nfi\n\nXILINX_ENV_FILE=$XILINX_DIR/Vitis/2022.2/settings64.sh\necho \"Expect env file $XILINX_ENV_FILE\"\n\nif [ -f \"$XILINX_ENV_FILE\" ]; then\n    echo \"$XILINX_ENV_FILE is found!\"\nelse\n    echo \"$XILINX_ENV_FILE is not correct. Please check!\"\n    exit 1\nfi\n\nif [ \"$ARCH_OPTION\" == \"64\" ]; then\n  LINUX_KERNEL_SRC_DIR_NAME=adi-linux-64\n  LINUX_KERNEL_CONFIG_FILE=$OPENWIFI_DIR/kernel_boot/kernel_config_zynqmp\n  ARCH_NAME=\"arm64\"\n  CROSS_COMPILE_NAME=\"aarch64-linux-gnu-\"\n  IMAGE_TYPE=Image\nelse\n  LINUX_KERNEL_SRC_DIR_NAME=adi-linux\n  LINUX_KERNEL_CONFIG_FILE=$OPENWIFI_DIR/kernel_boot/kernel_config\n  ARCH_NAME=\"arm\"\n  CROSS_COMPILE_NAME=\"arm-linux-gnueabihf-\"\n  IMAGE_TYPE=uImage\nfi\n\nhome_dir=$(pwd)\n\nset -x\n\ncd $OPENWIFI_DIR/\ngit submodule init $LINUX_KERNEL_SRC_DIR_NAME\ncd $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME\ngit reset --hard\ncd $OPENWIFI_DIR/\ngit submodule update $LINUX_KERNEL_SRC_DIR_NAME\ncd $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME\nif false; then\n  echo \"Reserve for future\"\nelse\n  git fetch\n  git checkout 2022_R2\n  git pull origin 2022_R2\n  # git reset --hard 2022_R2\n  git reset --hard c2f371e014f0704be4db02e5014c51ae99477c13 # save this commit for tsn\nfi\n\nsource $XILINX_ENV_FILE\nexport ARCH=$ARCH_NAME\nexport CROSS_COMPILE=$CROSS_COMPILE_NAME\n\nif false; then\n  echo \"Reserve for future\"\nelse\n  # if [ \"$ARCH_OPTION\" == \"64\" ]; then\n    cp $LINUX_KERNEL_CONFIG_FILE ./.config\n    # cp $OPENWIFI_DIR/driver/ad9361/ad9361.c $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME/drivers/iio/adc/ad9361.c -rf\n    # cp $OPENWIFI_DIR/driver/ad9361/ad9361_conv.c $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME/drivers/iio/adc/ad9361_conv.c -rf\n    git apply ../kernel_boot/axi_hdmi_crtc.patch\n    git apply ../kernel_boot/ad9361.patch\n    git apply ../kernel_boot/ad9361_private.patch\n    git apply ../kernel_boot/ad9361_conv.patch\n    # #Ignore warning in mac80211 -- NOT necessary for 2022_R2 kernel!\n    # sed -i '3692 s/^/\\/\\//' ../$LINUX_KERNEL_SRC_DIR_NAME/net/mac80211/util.c\n  # else\n    # make zynq_xcomm_adv7511_defconfig\n  # fi\n\n  make oldconfig\n  # make adi_zynqmp_defconfig\n  make prepare && make modules_prepare\n\n  # if [ \"$#\" -gt 2 ]; then\n  make -j12 $IMAGE_TYPE UIMAGE_LOADADDR=0x8000\n  make modules\n  # fi\nfi\n\ncd $home_dir\n"
  },
  {
    "path": "user_space/receiver_phase_offset_override.sh",
    "content": "#!/bin/bash\n\n# Author: Xianjun Jiao\n# SPDX-FileCopyrightText: 2023 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\n# To avoid override, just run without any arguments\n# To       override, example: ./receiver_phase_offset_override.sh  -8\n\nset -x\n\nif [[ -n $1 ]]; then\n  phase_offset=$1\nelse\n  echo \"Disable phase offset override by setting bit31 to 0\"\n  reg_val=$((0<<31))\n  printf \"0x%X\\n\" $reg_val\n  echo \"./sdrctl dev sdr0 set reg rx 19 $reg_val\"\n  ./sdrctl dev sdr0 set reg rx 19 $reg_val\n  exit 0\nfi\n\necho $phase_offset\nprintf \"0x%X\\n\" $phase_offset\n\nreg_val=$(( ($phase_offset & 65535) | (1 << 31) ))\nprintf \"0x%X\\n\" $reg_val\n\n./sdrctl dev sdr0 set reg rx 19 $reg_val\n\nset +x\n"
  },
  {
    "path": "user_space/rf_init.sh",
    "content": "#!/bin/sh\n\n# Author: Xianjun Jiao\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\nhome_dir=$(pwd)\n\nif [ -z \"$1\" ]\nthen\n  tx_offset_tuning_enable=1\nelse\n  tx_offset_tuning_enable=0\nfi\necho tx_offset_tuning_enable $tx_offset_tuning_enable\n\nif [ $tx_offset_tuning_enable = \"1\" ]\nthen\n  fir_filename=\"openwifi_ad9361_fir.ftr\"\n  tx_fir_enable=0\nelse\n  fir_filename=\"openwifi_ad9361_fir_tx_0MHz.ftr\"\n  tx_fir_enable=1\nfi\n\necho $fir_filename \"tx_fir_enable\" $tx_fir_enable\n\nif test -f $fir_filename; then\n  echo \"Found\" $fir_filename\nelse\n  echo \"Can not find\" $fir_filename\n  exit 1\nfi\n\nset -x\nif test -f \"/sys/bus/iio/devices/iio:device0/in_voltage_rf_bandwidth\"; then\n  cd /sys/bus/iio/devices/iio:device0/\nelse if test -f \"/sys/bus/iio/devices/iio:device1/in_voltage_rf_bandwidth\"; then\n       cd /sys/bus/iio/devices/iio:device1/\n     else if test -f \"/sys/bus/iio/devices/iio:device2/in_voltage_rf_bandwidth\"; then\n            cd /sys/bus/iio/devices/iio:device2/\n          else if test -f \"/sys/bus/iio/devices/iio:device3/in_voltage_rf_bandwidth\"; then\n                 cd /sys/bus/iio/devices/iio:device3/\n               else if test -f \"/sys/bus/iio/devices/iio:device4/in_voltage_rf_bandwidth\"; then\n                      cd /sys/bus/iio/devices/iio:device4/\n                    else\n                      echo \"Can not find in_voltage_rf_bandwidth!\"\n                      echo \"Check log to make sure ad9361 driver is loaded!\"\n                      exit 1\n                    fi\n               fi\n          fi\n     fi\nfi\nset +x\n\necho 17500000 >  in_voltage_rf_bandwidth\nsync\necho 37500000 >  out_voltage_rf_bandwidth\nsync\necho 40000000 >  in_voltage_sampling_frequency\nsync\necho 40000000 >  out_voltage_sampling_frequency\nsync\nsleep 1\n\necho 1000000000 >  out_altvoltage0_RX_LO_frequency\nsync\necho 1000000000 >  out_altvoltage1_TX_LO_frequency\nsync\n\ncat $home_dir/$fir_filename > filter_fir_config\nsync\nsleep 0.5\necho 1 > in_voltage_filter_fir_en\necho $tx_fir_enable > out_voltage_filter_fir_en\ncat filter_fir_config\ncat in_voltage_filter_fir_en\ncat out_voltage_filter_fir_en\n\necho \"rx0 agc fast_attack\"\n#echo \"rx0 agc manual\"\ncat in_voltage0_gain_control_mode\necho fast_attack > in_voltage0_gain_control_mode\n#echo manual > in_voltage0_gain_control_mode\ncat in_voltage0_gain_control_mode\nsync\n\necho \"rx1 agc fast_attack\"\n#echo \"rx1 agc manual\"\ncat in_voltage1_gain_control_mode\necho fast_attack > in_voltage1_gain_control_mode\n#echo manual > in_voltage1_gain_control_mode\ncat in_voltage1_gain_control_mode\nsync\nsleep 1\n\ncat in_voltage_sampling_frequency\ncat in_voltage_rf_bandwidth\ncat out_voltage_sampling_frequency\ncat out_voltage_rf_bandwidth\n\necho \"rssi\"\ncat in_voltage0_rssi\ncat in_voltage1_rssi\n\n# #  --------not needed maybe-------- # #\necho \"rx0 gain to 70\" # this set gain is gpio gain - 5dB (test with agc and read back gpio in driver)\ncat in_voltage0_hardwaregain\necho 70 > in_voltage0_hardwaregain\ncat in_voltage0_hardwaregain\nsync\n\necho \"rx1 gain to 70\"\ncat in_voltage1_hardwaregain\necho 70 > in_voltage1_hardwaregain\ncat in_voltage1_hardwaregain\nsync\n\necho \"tx0 gain -89dB\"\ncat out_voltage0_hardwaregain\necho -89 > out_voltage0_hardwaregain\ncat out_voltage0_hardwaregain\nsync\n\necho \"tx1 gain 0dB\"\ncat out_voltage1_hardwaregain\necho 0 > out_voltage1_hardwaregain\ncat out_voltage1_hardwaregain\nsync\n# #  --------not needed maybe-------- # #\n\ncd $home_dir\n\n"
  },
  {
    "path": "user_space/rf_init_11n.sh",
    "content": "#!/bin/sh\n\n# Author: Xianjun Jiao\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\nhome_dir=$(pwd)\n\n#if [ -z \"$1\" ]\n#then\n#  tx_offset_tuning_enable=1\n#else\n  tx_offset_tuning_enable=0\n#fi\necho tx_offset_tuning_enable $tx_offset_tuning_enable\n\n#if [ $tx_offset_tuning_enable = \"1\" ]\n#then\n#  fir_filename=\"openwifi_ad9361_fir.ftr\"\n#  tx_fir_enable=0\n#else\n#  fir_filename=\"openwifi_ad9361_fir_tx_0MHz.ftr\"\n#  tx_fir_enable=1\n#fi\n\nfir_filename=\"openwifi_ad9361_fir_tx_0MHz_11n.ftr\"\ntx_fir_enable=1\n\necho $fir_filename \"tx_fir_enable\" $tx_fir_enable\n\nif test -f $fir_filename; then\n  echo \"Found\" $fir_filename\nelse\n  echo \"Can not find\" $fir_filename\n  exit 1\nfi\n\nset -x\nif test -f \"/sys/bus/iio/devices/iio:device0/in_voltage_rf_bandwidth\"; then\n  cd /sys/bus/iio/devices/iio:device0/\nelse if test -f \"/sys/bus/iio/devices/iio:device1/in_voltage_rf_bandwidth\"; then\n       cd /sys/bus/iio/devices/iio:device1/\n     else if test -f \"/sys/bus/iio/devices/iio:device2/in_voltage_rf_bandwidth\"; then\n            cd /sys/bus/iio/devices/iio:device2/\n          else if test -f \"/sys/bus/iio/devices/iio:device3/in_voltage_rf_bandwidth\"; then\n                 cd /sys/bus/iio/devices/iio:device3/\n               else if test -f \"/sys/bus/iio/devices/iio:device4/in_voltage_rf_bandwidth\"; then\n                      cd /sys/bus/iio/devices/iio:device4/\n                    else\n                      echo \"Can not find in_voltage_rf_bandwidth!\"\n                      echo \"Check log to make sure ad9361 driver is loaded!\"\n                      exit 1\n                    fi\n               fi\n          fi\n     fi\nfi\nset +x\n\necho 25215513 >  in_voltage_rf_bandwidth\necho 25215414 >  out_voltage_rf_bandwidth\necho 40000000 >  in_voltage_sampling_frequency\necho 40000000 >  out_voltage_sampling_frequency\n\necho 1000000000 >  out_altvoltage0_RX_LO_frequency\necho 1000000000 >  out_altvoltage1_TX_LO_frequency\n\ncat $home_dir/$fir_filename > filter_fir_config\necho 1 > in_voltage_filter_fir_en\necho $tx_fir_enable > out_voltage_filter_fir_en\ncat filter_fir_config\ncat in_voltage_filter_fir_en\ncat out_voltage_filter_fir_en\n\necho \"rx0 agc fast_attack\"\n#echo \"rx0 agc manual\"\ncat in_voltage0_gain_control_mode\necho fast_attack > in_voltage0_gain_control_mode\n#echo manual > in_voltage0_gain_control_mode\ncat in_voltage0_gain_control_mode\n\necho \"rx1 agc fast_attack\"\n#echo \"rx1 agc manual\"\ncat in_voltage1_gain_control_mode\necho fast_attack > in_voltage1_gain_control_mode\n#echo manual > in_voltage1_gain_control_mode\ncat in_voltage1_gain_control_mode\n\ncat in_voltage_sampling_frequency\ncat in_voltage_rf_bandwidth\ncat out_voltage_sampling_frequency\ncat out_voltage_rf_bandwidth\n\necho \"rssi\"\ncat in_voltage0_rssi\ncat in_voltage1_rssi\n\n# #  --------not needed maybe-------- # #\necho \"rx0 gain to 70\" # this set gain is gpio gain - 5dB (test with agc and read back gpio in driver)\ncat in_voltage0_hardwaregain\necho 70 > in_voltage0_hardwaregain\ncat in_voltage0_hardwaregain\n\necho \"rx1 gain to 70\"\ncat in_voltage1_hardwaregain\necho 70 > in_voltage1_hardwaregain\ncat in_voltage1_hardwaregain\n\necho \"tx0 gain -89dB\"\ncat out_voltage0_hardwaregain\necho -89 > out_voltage0_hardwaregain\ncat out_voltage0_hardwaregain\n\necho \"tx1 gain 0dB\"\ncat out_voltage1_hardwaregain\necho 0 > out_voltage1_hardwaregain\ncat out_voltage1_hardwaregain\n# #  --------not needed maybe-------- # #\n\ncd $home_dir\n\n"
  },
  {
    "path": "user_space/rssi_ad9361_show.sh",
    "content": "#!/bin/bash\n\n# Reads RSSI in dB from RX1, let's call it \"r\".  \n# Linear fit offset \"o\" depends on frequency (2.4GHz or 5GHz and FMCOMMS2/3).\n# RSSI(dBm) = -r + o\n# 2.4GHz(ch 6) FMCOMMS2: o = 16.74\n# 2.4GHz(ch 6) FMCOMMS3: o = 17.44\n# 5GHz (ch 44) FMCOMMS2: o = 25.41\n# 5GHz (ch 44) FMCOMMS3: o = 24.58\n\nhome_dir=$(pwd)\n\n#set -x\nif test -f \"/sys/bus/iio/devices/iio:device0/in_voltage0_rssi\"; then\n  cd /sys/bus/iio/devices/iio:device0/\nelse if test -f \"/sys/bus/iio/devices/iio:device1/in_voltage0_rssi\"; then\n       cd /sys/bus/iio/devices/iio:device1/\n     else if test -f \"/sys/bus/iio/devices/iio:device2/in_voltage0_rssi\"; then\n            cd /sys/bus/iio/devices/iio:device2/\n          else if test -f \"/sys/bus/iio/devices/iio:device3/in_voltage0_rssi\"; then\n                 cd /sys/bus/iio/devices/iio:device3/\n               else if test -f \"/sys/bus/iio/devices/iio:device4/in_voltage0_rssi\"; then\n                      cd /sys/bus/iio/devices/iio:device4/\n                    else\n                      echo \"Can not find in_voltage_rf_bandwidth!\"\n                      echo \"Check log to make sure ad9361 driver is loaded!\"\n                      exit 1\n                    fi\n               fi\n          fi\n     fi\nfi\n#set +x\n\nif [ $# -lt 1 ]; then\n  cat in_voltage0_rssi\nelse\n  num_read=$1\n  for ((i=0;i<$num_read;i++))\n  do\n    rssi_str=$(cat in_voltage0_rssi)\n    echo \"${rssi_str//dB}\"\n  done\nfi\ncd $home_dir\n"
  },
  {
    "path": "user_space/rssi_openwifi_show.sh",
    "content": "#!/bin/bash\n\nrssi_raw=$(./sdrctl dev sdr0 get reg xpu 57)\necho $rssi_raw\n\nrssi_raw=${rssi_raw: -8}\necho $rssi_raw\n\nrssi_raw_dec=$(( 16#$rssi_raw ))\necho $rssi_raw_dec\n\n#rssi_half_db=$(expr (16#$rss_raw) \\& 2047)\n#rssi_half_db=$(($rssi_raw_dec & 2047))\n#rssi_half_db=$(($rssi_raw_dec & 16#7ff))\n#the low 11 bits are rssi_half_db\nrssi_half_db=$((16#$rssi_raw & 16#7ff))\necho $rssi_half_db\n\n"
  },
  {
    "path": "user_space/rx_gain_show.sh",
    "content": "#!/bin/bash\n\nhome_dir=$(pwd)\n\nif test -d \"/sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\"; then\n  cd /sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\nelse \n  cd /sys/devices/soc0/fpga-axi\\@0/fpga-axi\\@0\\:sdr\nfi\n\nset -x\ncat rx_data_ok_agc_gain_value_realtime\ncat rx_data_fail_agc_gain_value_realtime\ncat rx_mgmt_ok_agc_gain_value_realtime\ncat rx_mgmt_fail_agc_gain_value_realtime\ncat rx_ack_ok_agc_gain_value_realtime\nset +x\n\ncd $home_dir\n\n"
  },
  {
    "path": "user_space/rx_stat_show.sh",
    "content": "#!/bin/bash\n\nhome_dir=$(pwd)\n\nif test -d \"/sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\"; then\n  cd /sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\nelse \n  cd /sys/devices/soc0/fpga-axi\\@0/fpga-axi\\@0\\:sdr\nfi\n\nset -x\n# show\ncat rx_data_pkt_num_total\ncat rx_data_pkt_num_fail\ncat rx_mgmt_pkt_num_total\ncat rx_mgmt_pkt_num_fail\ncat rx_ack_pkt_num_total\ncat rx_ack_pkt_num_fail\n\ncat rx_data_pkt_mcs_realtime\ncat rx_data_pkt_fail_mcs_realtime\ncat rx_mgmt_pkt_mcs_realtime\ncat rx_mgmt_pkt_fail_mcs_realtime\ncat rx_ack_pkt_mcs_realtime\n\ncat rx_data_ok_agc_gain_value_realtime\ncat rx_data_fail_agc_gain_value_realtime\ncat rx_mgmt_ok_agc_gain_value_realtime\ncat rx_mgmt_fail_agc_gain_value_realtime\ncat rx_ack_ok_agc_gain_value_realtime\n\n# clear\nif [[ -n $1 ]]; then\n  re='^[0-9]+$'\n  if ! [[ $1 =~ $re ]] ; then # not a number\n    echo 0 > rx_data_pkt_num_total\n    echo 0 > rx_data_pkt_num_fail\n    echo 0 > rx_mgmt_pkt_num_total\n    echo 0 > rx_mgmt_pkt_num_fail\n    echo 0 > rx_ack_pkt_num_total\n    echo 0 > rx_ack_pkt_num_fail\n\n    echo 0 > rx_data_pkt_mcs_realtime\n    echo 0 > rx_data_pkt_fail_mcs_realtime\n    echo 0 > rx_mgmt_pkt_mcs_realtime\n    echo 0 > rx_mgmt_pkt_fail_mcs_realtime\n    echo 0 > rx_ack_pkt_mcs_realtime\n\n    echo 0 > rx_data_ok_agc_gain_value_realtime\n    echo 0 > rx_data_fail_agc_gain_value_realtime\n    echo 0 > rx_mgmt_ok_agc_gain_value_realtime\n    echo 0 > rx_mgmt_fail_agc_gain_value_realtime\n    echo 0 > rx_ack_ok_agc_gain_value_realtime\n  else # if it is a number, it means the target total number of packet for PER calculation\n    num_received=$(cat rx_data_pkt_num_total)\n    num_failed=$(cat rx_data_pkt_num_fail)\n    num_correct=$(( $num_received - $num_failed ))\n    num_total=$(( $1 ))\n    PER_ENLARGE_FACTOR=10000\n    num_correct_scale=$(( $num_correct * $PER_ENLARGE_FACTOR ))\n    PCR=$(( $num_correct_scale / $num_total ))\n    PER=$(( $PER_ENLARGE_FACTOR - $PCR ))\n    echo PCR $PCR / $PER_ENLARGE_FACTOR\n    echo PER $PER / $PER_ENLARGE_FACTOR\n  fi\nfi\nset +x\n\ncd $home_dir\n\n"
  },
  {
    "path": "user_space/sdcard_boot_update.sh",
    "content": "#!/bin/bash\n\n# Author: Xianjun Jiao\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\nif [ \"$#\" -ne 1 ]; then\n    echo \"You must enter the \\$BOARD_NAME as argument\"\n    echo \"Like: sdrpi antsdr antsdr_e200 e310v2 adrv9364z7020 adrv9361z7035 zc706_fmcs2 zed_fmcs2 zc702_fmcs2 zcu102_fmcs2 zcu102_9371 neptunesdr\"\n    exit 1\nfi\nBOARD_NAME=$1\n\nif [ \"$BOARD_NAME\" != \"neptunesdr\" ] && [ \"$BOARD_NAME\" != \"antsdr\" ] && [ \"$BOARD_NAME\" != \"antsdr_e200\" ] && [ \"$BOARD_NAME\" != \"e310v2\" ] && [ \"$BOARD_NAME\" != \"sdrpi\" ] && [ \"$BOARD_NAME\" != \"zc706_fmcs2\" ] && [ \"$BOARD_NAME\" != \"zc702_fmcs2\" ] && [ \"$BOARD_NAME\" != \"zed_fmcs2\" ] && [ \"$BOARD_NAME\" != \"adrv9361z7035\" ] && [ \"$BOARD_NAME\" != \"adrv9364z7020\" ] && [ \"$BOARD_NAME\" != \"zcu102_fmcs2\" ] && [ \"$BOARD_NAME\" != \"zcu102_9371\" ]; then\n    echo \"\\$BOARD_NAME is not correct. Please check!\"\n    exit 1\nelse\n    echo \"\\$BOARD_NAME is found!\"\nfi\n\nif [ \"$BOARD_NAME\" == \"zcu102_fmcs2\" ] || [ \"$BOARD_NAME\" == \"zcu102_9371\" ]; then\n    dtb_filename=\"system.dtb\"\n    image_filepath=\"arch/arm64/boot/\"\n    image_filename=\"Image\"\n    LINUX_KERNEL_SRC_DIR_NAME=adi-linux-64\nelse\n    dtb_filename=\"devicetree.dtb\"\n    image_filepath=\"arch/arm/boot/\"\n    image_filename=\"uImage\"\n    LINUX_KERNEL_SRC_DIR_NAME=adi-linux\nfi\necho $dtb_filename\necho $image_filepath\necho $image_filename\n\nset -x\n\nmv BOOT.BIN BOOT.BIN.bak\nsync\nwget ftp://192.168.10.1/kernel_boot/boards/$BOARD_NAME/output_boot_bin/BOOT.BIN\nif [ -f \"./BOOT.BIN\" ]; then\n    echo \"BOOT.BIN downloaded!\"\nelse\n    echo \"WARNING! BOOT.BIN not downloaded! Old file used!\"\n    mv BOOT.BIN.bak BOOT.BIN\n#    exit 1\nfi\nsync\n\nmv $image_filename $image_filename.bak\nsync\nwget ftp://192.168.10.1/$LINUX_KERNEL_SRC_DIR_NAME/$image_filepath/$image_filename\nif [ -f \"./$image_filename\" ]; then\n    echo \"$image_filename downloaded!\"\nelse\n    echo \"WARNING! $image_filename not downloaded! Old file used!\"\n    mv $image_filename.bak $image_filename\n#    exit 1\nfi\nsync\n\nmv $dtb_filename $dtb_filename.bak\nsync\nwget ftp://192.168.10.1/kernel_boot/boards/$BOARD_NAME/$dtb_filename\nif [ -f \"./$dtb_filename\" ]; then\n    echo \"$dtb_filename downloaded!\"\nelse\n    echo \"WARNING! $dtb_filename not downloaded! Old file used!\"\n    mv $dtb_filename.bak $dtb_filename\n#    exit 1\nfi\nsync\n\n#slepp 0.5\n\nmount /dev/mmcblk0p1  /mnt\nsync\n#sleep 0.5\ncp BOOT.BIN /mnt/ -f\nrm /mnt/Image -f\nrm /mnt/uImage -f\ncp $image_filename /mnt/ -f\nrm /mnt/*.dtb -f\ncp $dtb_filename /mnt/ -f\ncd /mnt/\nsync\ncd ~\n#sleep 0.5\numount /mnt\nsync\n#sleep 3\nsudo reboot now\n"
  },
  {
    "path": "user_space/sdr-ad-hoc-join.sh",
    "content": "#!/bin/bash\n\n# Author: Xianjun Jiao\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\nif [ $# -ne 4 ]\n  then\n    echo \"Please input NIC_name ch_number ip_addr cell as input parameter!\"\n    exit\nfi\n\nnic_name=$1\nch_number=$2\nip_addr=$3\ncell=$4\necho $nic_name\necho $ch_number\necho $ip_addr\necho $cell\n\n# sudo service network-manager stop\nsudo ip link set $nic_name down\nsudo iwconfig $nic_name mode ad-hoc\nsudo iwconfig $nic_name essid 'sdr-ad-hoc'\nsudo ip link set $nic_name up\nsudo iwconfig $nic_name channel $ch_number\nsudo iwconfig $nic_name ap $cell\n#sudo iwconfig $nic_name modulation 11g\n#sudo iwconfig $nic_name rate 6M\nsudo ifconfig $nic_name $ip_addr netmask 255.255.255.0\nifconfig\niwconfig $nic_name\n\n./agc_settings.sh 1\n"
  },
  {
    "path": "user_space/sdr-ad-hoc-up.sh",
    "content": "#!/bin/bash\n\n# Author: Xianjun Jiao\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\nif [ $# -ne 3 ]\n  then\n    echo \"Please input NIC_name ch_number ip_addr as input parameter!\"\n    exit\nfi\n\nnic_name=$1\nch_number=$2\nip_addr=$3\necho $nic_name\necho $ch_number\necho $ip_addr\n\nsudo ip link set $nic_name down\nsudo iwconfig $nic_name mode ad-hoc\nsudo iwconfig $nic_name essid 'sdr-ad-hoc'\nsudo ip link set $nic_name up\nsudo iwconfig $nic_name channel $ch_number\n#sudo iwconfig $nic_name modulation 11g\n#sudo iwconfig $nic_name rate 6M\nsudo ifconfig $nic_name $ip_addr netmask 255.255.255.0\nifconfig\niwconfig $nic_name\n\n./agc_settings.sh 1\n"
  },
  {
    "path": "user_space/sdrctl_src/Makefile",
    "content": "MAKEFLAGS += --no-print-directory\n\nPREFIX ?= /usr\nSBINDIR ?= $(PREFIX)/sbin\nMANDIR ?= $(PREFIX)/share/man\nPKG_CONFIG ?= pkg-config\n\nMKDIR ?= mkdir -p\nINSTALL ?= install\nCC ?= \"gcc\"\n\nCFLAGS ?= -O2 -g\nCFLAGS += -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs -fno-strict-aliasing -fno-common -Werror-implicit-function-declaration\n\n# OBJS = iw.o genl.o event.o info.o phy.o \\\n\tinterface.o ibss.o station.o survey.o util.o \\\n\tmesh.o mpath.o scan.o reg.o version.o \\\n\treason.o status.o connect.o link.o offch.o ps.o cqm.o \\\n\tbitrate.o wowlan.o coalesce.o roc.o p2p.o\n\nOBJS = sdrctl.o cmd.o version.o\n\nOBJS += sections.o\n\n# OBJS-$(HWSIM) += hwsim.o\n\nOBJS += $(OBJS-y) $(OBJS-Y)\n\nALL = sdrctl\n\nifeq ($(NO_PKG_CONFIG),)\nNL3xFOUND := $(shell $(PKG_CONFIG) --atleast-version=3.2 libnl-3.0 && echo Y)\nifneq ($(NL3xFOUND),Y)\nNL31FOUND := $(shell $(PKG_CONFIG) --exact-version=3.1 libnl-3.1 && echo Y)\nifneq ($(NL31FOUND),Y)\nNL3FOUND := $(shell $(PKG_CONFIG) --atleast-version=3 libnl-3.0 && echo Y)\nifneq ($(NL3FOUND),Y)\nNL2FOUND := $(shell $(PKG_CONFIG) --atleast-version=2 libnl-2.0 && echo Y)\nifneq ($(NL2FOUND),Y)\nNL1FOUND := $(shell $(PKG_CONFIG) --atleast-version=1 libnl-1 && echo Y)\nendif\nendif\nendif\nendif\n\nifeq ($(NL1FOUND),Y)\nNLLIBNAME = libnl-1\nendif\n\nifeq ($(NL2FOUND),Y)\nCFLAGS += -DCONFIG_LIBNL20\nLIBS += -lnl-genl\nNLLIBNAME = libnl-2.0\nendif\n\nifeq ($(NL3xFOUND),Y)\n# libnl 3.2 might be found as 3.2 and 3.0\nNL3FOUND = N\nCFLAGS += -DCONFIG_LIBNL30\nLIBS += -lnl-genl-3\nNLLIBNAME = libnl-3.0\nendif\n\nifeq ($(NL3FOUND),Y)\nCFLAGS += -DCONFIG_LIBNL30\nLIBS += -lnl-genl\nNLLIBNAME = libnl-3.0\nendif\n\n# nl-3.1 has a broken libnl-gnl-3.1.pc file\n# as show by pkg-config --debug --libs --cflags --exact-version=3.1 libnl-genl-3.1;echo $?\nifeq ($(NL31FOUND),Y)\nCFLAGS += -DCONFIG_LIBNL30\nLIBS += -lnl-genl\nNLLIBNAME = libnl-3.1\nendif\n\nifeq ($(NLLIBNAME),)\n$(error Cannot find development files for any supported version of libnl)\nendif\n\nLIBS += $(shell $(PKG_CONFIG) --libs $(NLLIBNAME))\nCFLAGS += $(shell $(PKG_CONFIG) --cflags $(NLLIBNAME))\nendif # NO_PKG_CONFIG\n\nifeq ($(V),1)\nQ=\nNQ=true\nelse\nQ=@\nNQ=echo\nendif\n\nall: $(ALL)\n\nVERSION_OBJS := $(filter-out version.o, $(OBJS))\n\nversion.c: version.sh $(patsubst %.o,%.c,$(VERSION_OBJS)) nl80211.h sdrctl.h Makefile \\\n\t\t$(wildcard .git/index .git/refs/tags)\n\t@$(NQ) ' GEN ' $@\n\t$(Q)./version.sh $@\n\n%.o: %.c sdrctl.h nl80211.h\n\t@$(NQ) ' CC  ' $@\n\t$(Q)$(CC) $(CFLAGS) -c -o $@ $<\n\nsdrctl:\t$(OBJS)\n\t@$(NQ) ' CC  ' sdrctl\n\t$(Q)$(CC) $(LDFLAGS) $(OBJS) $(LIBS) -o sdrctl\n\ncheck:\n\t$(Q)$(MAKE) all CC=\"REAL_CC=$(CC) CHECK=\\\"sparse -Wall\\\" cgcc\"\n\n%.gz: %\n\t@$(NQ) ' GZIP' $<\n\t$(Q)gzip < $< > $@\n\ninstall: sdrctl sdrctl.8.gz\n\t@$(NQ) ' INST sdrctl'\n\t$(Q)$(MKDIR) $(DESTDIR)$(SBINDIR)\n\t$(Q)$(INSTALL) -m 755 sdrctl $(DESTDIR)$(SBINDIR)\n\t@$(NQ) ' INST sdrctl.8'\n\t$(Q)$(MKDIR) $(DESTDIR)$(MANDIR)/man8/\n\t$(Q)$(INSTALL) -m 644 sdrctl.8.gz $(DESTDIR)$(MANDIR)/man8/\n\nclean:\n\t$(Q)rm -f sdrctl *.o *~ *.gz version.c *-stamp\n"
  },
  {
    "path": "user_space/sdrctl_src/cmd.c",
    "content": "// Author: Xianjun Jiao\n// SPDX-FileCopyrightText: 2019 UGent\n// SPDX-License-Identifier: AGPL-3.0-or-later\n\n#include <stdbool.h>\n#include <errno.h>\n#include <net/if.h>\n#include <strings.h>\n\n#include <netlink/genl/genl.h>\n#include <netlink/genl/family.h>\n#include <netlink/genl/ctrl.h>\n#include <netlink/msg.h>\n#include <netlink/attr.h>\n\n#include \"nl80211.h\"\n#include \"sdrctl.h\"\n#include \"nl80211_testmode_def.h\"\n\n\nstatic int cb_reg_handler(struct nl_msg *msg, void *arg)\n{\n\tstruct nlattr *attrs[NL80211_ATTR_MAX + 1];\n\tstruct nlattr *tb[OPENWIFI_ATTR_MAX + 1];\n\tstruct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));\n\n\t//printf(\"cb_reg_handler\\n\");\n\n\tnla_parse(attrs, NL80211_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL);\n\n\tif (!attrs[NL80211_ATTR_TESTDATA])\n\t\treturn NL_SKIP;\n\n\tnla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);\n\n\t//printf(\"reg addr: %08x\\n\", nla_get_u32(tb[REG_ATTR_ADDR]));\n\tprintf(\"reg  val: %08x\\n\", nla_get_u32(tb[REG_ATTR_VAL]));\n\n\treturn NL_SKIP;\n}\n\nstatic int handle_set_reg(struct nl80211_state *state,\n\t\t\t  struct nl_cb *cb,\n\t\t\t  struct nl_msg *msg,\n\t\t\t  int argc, char **argv,\n\t\t\t  enum id_input id)\n{\n\tstruct nlattr *tmdata;\n\tchar *end;\n\tunsigned int reg_cat, reg_addr, reg_val;\n\n\ttmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);\n\tif (!tmdata) {\n\t\treturn 1;\n\t}\n\n\tif (strcasecmp(argv[0],\"rf\")==0)\n\t\treg_cat=1;\n\telse if (strcasecmp(argv[0],\"rx_intf\")==0)\n\t\treg_cat = 2;\n\telse if (strcasecmp(argv[0],\"tx_intf\")==0)\n\t\treg_cat = 3;\n\telse if (strcasecmp(argv[0],\"rx\")==0)\n\t\treg_cat = 4;\n\telse if (strcasecmp(argv[0],\"tx\")==0)\n\t\treg_cat = 5;\n\telse if (strcasecmp(argv[0],\"xpu\")==0)\n\t\treg_cat = 6;\n\telse if (strcasecmp(argv[0],\"drv_rx\")==0)\n\t\treg_cat = 7;\n\telse if (strcasecmp(argv[0],\"drv_tx\")==0)\n\t\treg_cat = 8;\n\telse if (strcasecmp(argv[0],\"drv_xpu\")==0)\n\t\treg_cat = 9;\n\telse {\n\t\tprintf(\"Wrong the 1st argument. Should be rf/rx_intf/tx_intf/rx/tx/xpu/drv_rx/drv_tx/drv_xpu\\n\");\n\t\treturn 1;\n\t}\n\n\treg_addr = strtoul(argv[1], &end, 10);\n\tif (*end) {\n\t\treturn 1;\n\t}\n\treg_addr = reg_addr<<2;//from idx to addr\n\treg_addr = ((reg_cat<<16)|reg_addr);\n\n\treg_val = strtoul(argv[2], &end, 10);\n\tif (*end) {\n\t\treturn 1;\n\t}\n\n\tNLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, REG_CMD_SET);\n\tNLA_PUT_U32(msg, REG_ATTR_ADDR, reg_addr);\n\tNLA_PUT_U32(msg, REG_ATTR_VAL,  reg_val);\n\n\tnla_nest_end(msg, tmdata);\n\n\tprintf(\"reg  cat: %d\\n\",   reg_cat);\n\tprintf(\"reg addr: %08x\\n\", reg_addr);\n\tprintf(\"reg  val: %08x\\n\", reg_val);\n\n\treturn 0;\n\n nla_put_failure:\n\treturn -ENOBUFS;\n}\nCOMMAND(set, reg, \"<rf/rx_intf/tx_intf/rx/tx/xpu/drv_rx/drv_tx/drv_xpu reg_idx value>\", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_reg, \"set reg\");\n\nstatic int handle_get_reg(struct nl80211_state *state,\n\t\t\t  struct nl_cb *cb,\n\t\t\t  struct nl_msg *msg,\n\t\t\t  int argc, char **argv,\n\t\t\t  enum id_input id)\n{\n\tchar *end;\n\tstruct nlattr *tmdata;\n\tunsigned int reg_cat, reg_addr;\n\n\ttmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);\n\tif (!tmdata)\n\t\treturn 1;\n\n\tif (strcasecmp(argv[0],\"rf\")==0)\n\t\treg_cat=1;\n\telse if (strcasecmp(argv[0],\"rx_intf\")==0)\n\t\treg_cat = 2;\n\telse if (strcasecmp(argv[0],\"tx_intf\")==0)\n\t\treg_cat = 3;\n\telse if (strcasecmp(argv[0],\"rx\")==0)\n\t\treg_cat = 4;\n\telse if (strcasecmp(argv[0],\"tx\")==0)\n\t\treg_cat = 5;\n\telse if (strcasecmp(argv[0],\"xpu\")==0)\n\t\treg_cat = 6;\n\telse if (strcasecmp(argv[0],\"drv_rx\")==0)\n\t\treg_cat = 7;\n\telse if (strcasecmp(argv[0],\"drv_tx\")==0)\n\t\treg_cat = 8;\n\telse if (strcasecmp(argv[0],\"drv_xpu\")==0)\n\t\treg_cat = 9;\n\telse {\n\t\tprintf(\"Wrong the 1st argument. Should be rf/rx_intf/tx_intf/rx/tx/xpu/drv_rx/drv_tx/drv_xpu\\n\");\n\t\treturn 1;\n\t}\n\n\treg_addr = strtoul(argv[1], &end, 10);\n\tif (*end) {\n\t\treturn 1;\n\t}\n\treg_addr = reg_addr<<2;//from idx to addr\n\treg_addr = ((reg_cat<<16)|reg_addr);\n\tprintf(\"SENDaddr: %08x\\n\", reg_addr);\n\n\tNLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, REG_CMD_GET);\n\tNLA_PUT_U32(msg, REG_ATTR_ADDR, reg_addr);\n\n\tnla_nest_end(msg, tmdata);\n\n\tnl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_reg_handler, NULL);\n\treturn 0;\n\n nla_put_failure:\n\treturn -ENOBUFS;\n}\nCOMMAND(get, reg, \"<rf/rx_intf/tx_intf/rx/tx/xpu/drv_rx/drv_tx/drv_xpu reg_idx>\", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_reg, \"get reg\");\n\nstatic int cb_openwifi_rssi_th_handler(struct nl_msg *msg, void *arg)\n{\n\tstruct nlattr *attrs[NL80211_ATTR_MAX + 1];\n\tstruct nlattr *tb[OPENWIFI_ATTR_MAX + 1];\n\tstruct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));\n\n\tnla_parse(attrs, NL80211_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL);\n\n\tif (!attrs[NL80211_ATTR_TESTDATA])\n\t\treturn NL_SKIP;\n\n\tnla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);\n\n\tprintf(\"openwifi rssi_th: %d\\n\", nla_get_u32(tb[OPENWIFI_ATTR_RSSI_TH]));\n\n\treturn NL_SKIP;\n}\n\nstatic int handle_set_rssi_th(struct nl80211_state *state,\n\t\t\t  struct nl_cb *cb,\n\t\t\t  struct nl_msg *msg,\n\t\t\t  int argc, char **argv,\n\t\t\t  enum id_input id)\n{\n\tstruct nlattr *tmdata;\n\tchar *end;\n\tunsigned int tmp;\n\n\ttmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);\n\tif (!tmdata) {\n\t\treturn 1;\n\t}\n\n\ttmp = strtoul(argv[0], &end, 10);\n\n\tif (*end) {\n\t\treturn 1;\n\t}\n\n\tNLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_RSSI_TH);\n\tNLA_PUT_U32(msg, OPENWIFI_ATTR_RSSI_TH, tmp);\n\n\tnla_nest_end(msg, tmdata);\n\n\tprintf(\"openwifi rssi_th: %d\\n\", tmp);\n\n\treturn 0;\n\n nla_put_failure:\n\treturn -ENOBUFS;\n}\nCOMMAND(set, rssi_th, \"<rssi_th in value>\", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_rssi_th, \"set rssi_th\");\n\n\nstatic int handle_set_tsf(struct nl80211_state *state,\n\t\t  struct nl_cb *cb,\n\t\t  struct nl_msg *msg,\n\t\t  int argc, char **argv,\n\t\t  enum id_input id)\n{\n\tstruct nlattr *tmdata;\n\tchar *end;\n\tunsigned int high_tsf, low_tsf;\n\n\ttmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);\n\tif (!tmdata) {\n\t\treturn 1;\n\t}\n\n\thigh_tsf = strtoul(argv[0], &end, 10);\n\tif (*end) {\n\t\treturn 1;\n\t}\n\n\tlow_tsf = strtoul(argv[1], &end, 10);\n\tif (*end) {\n\t\treturn 1;\n\t}\n\n\tNLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_TSF);\n\tNLA_PUT_U32(msg, OPENWIFI_ATTR_HIGH_TSF, high_tsf);\n\tNLA_PUT_U32(msg, OPENWIFI_ATTR_LOW_TSF, low_tsf);\n\n\tnla_nest_end(msg, tmdata);\n\n\tprintf(\"high_tsf val: %08x\\n\", high_tsf);\n\tprintf(\"low_tsf  val: %08x\\n\", low_tsf);\n\n\treturn 0;\n\n\t/*struct nlattr *tmdata;\n\tchar *end;\n\tunsigned int tmp;\n\n\ttmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);\n\tif (!tmdata) {\n\t\treturn 1;\n\t}\n\n\ttmp = strtoul(argv[0], &end, 10);\n\n\tif (*end) {\n\t\treturn 1;\n\t}\n\n\tNLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_TSF);\n\tNLA_PUT_U64(msg, OPENWIFI_ATTR_TSF, tmp);\n\n\tnla_nest_end(msg, tmdata);\n\n\tprintf(\"openwifi tsf: %d\\n\", tmp);\n\n\treturn 0;*/\n\n nla_put_failure:\n\treturn -ENOBUFS;\n}\nCOMMAND(set, tsf, \"<high_tsf value low_tsf value>\", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_tsf, \"set tsf\");\n\nstatic int handle_get_rssi_th(struct nl80211_state *state,\n\t\t\t  struct nl_cb *cb,\n\t\t\t  struct nl_msg *msg,\n\t\t\t  int argc, char **argv,\n\t\t\t  enum id_input id)\n{\n\tstruct nlattr *tmdata;\n\n\ttmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);\n\tif (!tmdata)\n\t\treturn 1;\n\n\tNLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_RSSI_TH);\n\n\tnla_nest_end(msg, tmdata);\n\n\tnl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_rssi_th_handler, NULL);\n\treturn 0;\n\n nla_put_failure:\n\treturn -ENOBUFS;\n}\nCOMMAND(get, rssi_th, \"<rssi_th in value>\", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_rssi_th, \"get rssi_th\");\n\nstatic int cb_openwifi_slice_total_handler(struct nl_msg *msg, void *arg)\n{\n\tstruct nlattr *attrs[NL80211_ATTR_MAX + 1];\n\tstruct nlattr *tb[OPENWIFI_ATTR_MAX + 1];\n\tstruct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));\n\tunsigned int tmp;\n\n\tnla_parse(attrs, NL80211_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL);\n\n\tif (!attrs[NL80211_ATTR_TESTDATA])\n\t\treturn NL_SKIP;\n\n\tnla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);\n\n\ttmp = nla_get_u32(tb[OPENWIFI_ATTR_SLICE_TOTAL]);\n\tprintf(\"openwifi slice_total (duration) %dus of slice %d\\n\", tmp&0xFFFFF, tmp>>20);\n\n\treturn NL_SKIP;\n}\n\nstatic int handle_set_slice_total(struct nl80211_state *state,\n\t\t\t  struct nl_cb *cb,\n\t\t\t  struct nl_msg *msg,\n\t\t\t  int argc, char **argv,\n\t\t\t  enum id_input id)\n{\n\tstruct nlattr *tmdata;\n\tchar *end;\n\tunsigned int tmp;\n\n\ttmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);\n\tif (!tmdata) {\n\t\treturn 1;\n\t}\n\n\ttmp = strtoul(argv[0], &end, 10);\n\n\tif (*end) {\n\t\treturn 1;\n\t}\n\n\tNLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_SLICE_TOTAL);\n\tNLA_PUT_U32(msg, OPENWIFI_ATTR_SLICE_TOTAL, tmp);\n\n\tnla_nest_end(msg, tmdata);\n\n\tprintf(\"openwifi slice_total (duration): %dus\\n\", tmp);\n\n\treturn 0;\n\n nla_put_failure:\n\treturn -ENOBUFS;\n}\nCOMMAND(set, slice_total, \"<slice_total(duration) in us>\", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_slice_total, \"set slice_total\");\n\nstatic int handle_get_slice_total(struct nl80211_state *state,\n\t\t\t  struct nl_cb *cb,\n\t\t\t  struct nl_msg *msg,\n\t\t\t  int argc, char **argv,\n\t\t\t  enum id_input id)\n{\n\tstruct nlattr *tmdata;\n\n\ttmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);\n\tif (!tmdata)\n\t\treturn 1;\n\n\tNLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_SLICE_TOTAL);\n\n\tnla_nest_end(msg, tmdata);\n\n\tnl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_slice_total_handler, NULL);\n\treturn 0;\n\n nla_put_failure:\n\treturn -ENOBUFS;\n}\nCOMMAND(get, slice_total, \"<slice_total(duration) in us>\", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_slice_total, \"get slice_total\");\n\n\n// static int cb_openwifi_slice_total1_handler(struct nl_msg *msg, void *arg)\n// {\n// \tstruct nlattr *attrs[NL80211_ATTR_MAX + 1];\n// \tstruct nlattr *tb[OPENWIFI_ATTR_MAX + 1];\n// \tstruct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));\n\n// \tnla_parse(attrs, NL80211_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL);\n\n// \tif (!attrs[NL80211_ATTR_TESTDATA])\n// \t\treturn NL_SKIP;\n\n// \tnla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);\n\n// \tprintf(\"openwifi slice_total1 (duration): %dus\\n\", nla_get_u32(tb[OPENWIFI_ATTR_SLICE_TOTAL1]));\n\n// \treturn NL_SKIP;\n// }\n\n// static int handle_set_slice_total1(struct nl80211_state *state,\n// \t\t\t  struct nl_cb *cb,\n// \t\t\t  struct nl_msg *msg,\n// \t\t\t  int argc, char **argv,\n// \t\t\t  enum id_input id)\n// {\n// \tstruct nlattr *tmdata;\n// \tchar *end;\n// \tunsigned int tmp;\n\n// \ttmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);\n// \tif (!tmdata) {\n// \t\treturn 1;\n// \t}\n\n// \ttmp = strtoul(argv[0], &end, 10);\n\n// \tif (*end) {\n// \t\treturn 1;\n// \t}\n\n// \tNLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_SLICE_TOTAL1);\n// \tNLA_PUT_U32(msg, OPENWIFI_ATTR_SLICE_TOTAL1, tmp);\n\n// \tnla_nest_end(msg, tmdata);\n\n// \tprintf(\"openwifi slice_total1 (duration): %dus\\n\", tmp);\n\n// \treturn 0;\n\n//  nla_put_failure:\n// \treturn -ENOBUFS;\n// }\n// COMMAND(set, slice_total1, \"<slice_total1(duration) in us>\", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_slice_total1, \"set slice_total1\");\n\n// static int handle_get_slice_total1(struct nl80211_state *state,\n// \t\t\t  struct nl_cb *cb,\n// \t\t\t  struct nl_msg *msg,\n// \t\t\t  int argc, char **argv,\n// \t\t\t  enum id_input id)\n// {\n// \tstruct nlattr *tmdata;\n\n// \ttmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);\n// \tif (!tmdata)\n// \t\treturn 1;\n\n// \tNLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_SLICE_TOTAL1);\n\n// \tnla_nest_end(msg, tmdata);\n\n// \tnl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_slice_total1_handler, NULL);\n// \treturn 0;\n\n//  nla_put_failure:\n// \treturn -ENOBUFS;\n// }\n// COMMAND(get, slice_total1, \"<slice_total1(duration) in us>\", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_slice_total1, \"get slice_total1\");\n\nstatic int cb_openwifi_slice_start_handler(struct nl_msg *msg, void *arg)\n{\n\tstruct nlattr *attrs[NL80211_ATTR_MAX + 1];\n\tstruct nlattr *tb[OPENWIFI_ATTR_MAX + 1];\n\tstruct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));\n\tunsigned int tmp;\n\n\tnla_parse(attrs, NL80211_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL);\n\n\tif (!attrs[NL80211_ATTR_TESTDATA])\n\t\treturn NL_SKIP;\n\n\tnla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);\n\n\ttmp = nla_get_u32(tb[OPENWIFI_ATTR_SLICE_START]);\n\tprintf(\"openwifi slice_start (duration) %dus of slice %d\\n\", tmp&0xFFFFF, tmp>>20);\n\n\treturn NL_SKIP;\n}\n\nstatic int handle_set_slice_start(struct nl80211_state *state,\n\t\t\t  struct nl_cb *cb,\n\t\t\t  struct nl_msg *msg,\n\t\t\t  int argc, char **argv,\n\t\t\t  enum id_input id)\n{\n\tstruct nlattr *tmdata;\n\tchar *end;\n\tunsigned int tmp;\n\n\ttmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);\n\tif (!tmdata) {\n\t\treturn 1;\n\t}\n\n\ttmp = strtoul(argv[0], &end, 10);\n\n\tif (*end) {\n\t\treturn 1;\n\t}\n\n\tNLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_SLICE_START);\n\tNLA_PUT_U32(msg, OPENWIFI_ATTR_SLICE_START, tmp);\n\n\tnla_nest_end(msg, tmdata);\n\n\tprintf(\"openwifi slice_start (duration): %dus\\n\", tmp);\n\n\treturn 0;\n\n nla_put_failure:\n\treturn -ENOBUFS;\n}\nCOMMAND(set, slice_start, \"<slice_start(duration) in us>\", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_slice_start, \"set slice_start\");\n\nstatic int handle_get_slice_start(struct nl80211_state *state,\n\t\t\t  struct nl_cb *cb,\n\t\t\t  struct nl_msg *msg,\n\t\t\t  int argc, char **argv,\n\t\t\t  enum id_input id)\n{\n\tstruct nlattr *tmdata;\n\n\ttmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);\n\tif (!tmdata)\n\t\treturn 1;\n\n\tNLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_SLICE_START);\n\n\tnla_nest_end(msg, tmdata);\n\n\tnl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_slice_start_handler, NULL);\n\treturn 0;\n\n nla_put_failure:\n\treturn -ENOBUFS;\n}\nCOMMAND(get, slice_start, \"<slice_start(duration) in us>\", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_slice_start, \"get slice_start\");\n\n\n// static int cb_openwifi_slice_start1_handler(struct nl_msg *msg, void *arg)\n// {\n// \tstruct nlattr *attrs[NL80211_ATTR_MAX + 1];\n// \tstruct nlattr *tb[OPENWIFI_ATTR_MAX + 1];\n// \tstruct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));\n\n// \tnla_parse(attrs, NL80211_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL);\n\n// \tif (!attrs[NL80211_ATTR_TESTDATA])\n// \t\treturn NL_SKIP;\n\n// \tnla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);\n\n// \tprintf(\"openwifi slice_start1 (duration): %dus\\n\", nla_get_u32(tb[OPENWIFI_ATTR_SLICE_START1]));\n\n// \treturn NL_SKIP;\n// }\n\n// static int handle_set_slice_start1(struct nl80211_state *state,\n// \t\t\t  struct nl_cb *cb,\n// \t\t\t  struct nl_msg *msg,\n// \t\t\t  int argc, char **argv,\n// \t\t\t  enum id_input id)\n// {\n// \tstruct nlattr *tmdata;\n// \tchar *end;\n// \tunsigned int tmp;\n\n// \ttmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);\n// \tif (!tmdata) {\n// \t\treturn 1;\n// \t}\n\n// \ttmp = strtoul(argv[0], &end, 10);\n\n// \tif (*end) {\n// \t\treturn 1;\n// \t}\n\n// \tNLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_SLICE_START1);\n// \tNLA_PUT_U32(msg, OPENWIFI_ATTR_SLICE_START1, tmp);\n\n// \tnla_nest_end(msg, tmdata);\n\n// \tprintf(\"openwifi slice_start1 (duration): %dus\\n\", tmp);\n\n// \treturn 0;\n\n//  nla_put_failure:\n// \treturn -ENOBUFS;\n// }\n// COMMAND(set, slice_start1, \"<slice_start1(duration) in us>\", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_slice_start1, \"set slice_start1\");\n\n// static int handle_get_slice_start1(struct nl80211_state *state,\n// \t\t\t  struct nl_cb *cb,\n// \t\t\t  struct nl_msg *msg,\n// \t\t\t  int argc, char **argv,\n// \t\t\t  enum id_input id)\n// {\n// \tstruct nlattr *tmdata;\n\n// \ttmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);\n// \tif (!tmdata)\n// \t\treturn 1;\n\n// \tNLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_SLICE_START1);\n\n// \tnla_nest_end(msg, tmdata);\n\n// \tnl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_slice_start1_handler, NULL);\n// \treturn 0;\n\n//  nla_put_failure:\n// \treturn -ENOBUFS;\n// }\n// COMMAND(get, slice_start1, \"<slice_start1(duration) in us>\", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_slice_start1, \"get slice_start1\");\n\n\nstatic int cb_openwifi_slice_end_handler(struct nl_msg *msg, void *arg)\n{\n\tstruct nlattr *attrs[NL80211_ATTR_MAX + 1];\n\tstruct nlattr *tb[OPENWIFI_ATTR_MAX + 1];\n\tstruct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));\n\tunsigned int tmp;\n\n\tnla_parse(attrs, NL80211_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL);\n\n\tif (!attrs[NL80211_ATTR_TESTDATA])\n\t\treturn NL_SKIP;\n\n\tnla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);\n\n\ttmp = nla_get_u32(tb[OPENWIFI_ATTR_SLICE_END]);\n\tprintf(\"openwifi slice_end (duration) %dus of slice %d\\n\", tmp&0xFFFFF, tmp>>20);\n\n\treturn NL_SKIP;\n}\n\nstatic int handle_set_slice_end(struct nl80211_state *state,\n\t\t\t  struct nl_cb *cb,\n\t\t\t  struct nl_msg *msg,\n\t\t\t  int argc, char **argv,\n\t\t\t  enum id_input id)\n{\n\tstruct nlattr *tmdata;\n\tchar *end;\n\tunsigned int tmp;\n\n\ttmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);\n\tif (!tmdata) {\n\t\treturn 1;\n\t}\n\n\ttmp = strtoul(argv[0], &end, 10);\n\n\tif (*end) {\n\t\treturn 1;\n\t}\n\n\tNLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_SLICE_END);\n\tNLA_PUT_U32(msg, OPENWIFI_ATTR_SLICE_END, tmp);\n\n\tnla_nest_end(msg, tmdata);\n\n\tprintf(\"openwifi slice_end (duration): %dus\\n\", tmp);\n\n\treturn 0;\n\n nla_put_failure:\n\treturn -ENOBUFS;\n}\nCOMMAND(set, slice_end, \"<slice_end(duration) in us>\", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_slice_end, \"set slice_end\");\n\nstatic int handle_get_slice_end(struct nl80211_state *state,\n\t\t\t  struct nl_cb *cb,\n\t\t\t  struct nl_msg *msg,\n\t\t\t  int argc, char **argv,\n\t\t\t  enum id_input id)\n{\n\tstruct nlattr *tmdata;\n\n\ttmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);\n\tif (!tmdata)\n\t\treturn 1;\n\n\tNLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_SLICE_END);\n\n\tnla_nest_end(msg, tmdata);\n\n\tnl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_slice_end_handler, NULL);\n\treturn 0;\n\n nla_put_failure:\n\treturn -ENOBUFS;\n}\nCOMMAND(get, slice_end, \"<slice_end(duration) in us>\", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_slice_end, \"get slice_end\");\n\n\n// static int cb_openwifi_slice_end1_handler(struct nl_msg *msg, void *arg)\n// {\n// \tstruct nlattr *attrs[NL80211_ATTR_MAX + 1];\n// \tstruct nlattr *tb[OPENWIFI_ATTR_MAX + 1];\n// \tstruct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));\n\n// \tnla_parse(attrs, NL80211_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL);\n\n// \tif (!attrs[NL80211_ATTR_TESTDATA])\n// \t\treturn NL_SKIP;\n\n// \tnla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);\n\n// \tprintf(\"openwifi slice_end1 (duration): %dus\\n\", nla_get_u32(tb[OPENWIFI_ATTR_SLICE_END1]));\n\n// \treturn NL_SKIP;\n// }\n\n// static int handle_set_slice_end1(struct nl80211_state *state,\n// \t\t\t  struct nl_cb *cb,\n// \t\t\t  struct nl_msg *msg,\n// \t\t\t  int argc, char **argv,\n// \t\t\t  enum id_input id)\n// {\n// \tstruct nlattr *tmdata;\n// \tchar *end;\n// \tunsigned int tmp;\n\n// \ttmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);\n// \tif (!tmdata) {\n// \t\treturn 1;\n// \t}\n\n// \ttmp = strtoul(argv[0], &end, 10);\n\n// \tif (*end) {\n// \t\treturn 1;\n// \t}\n\n// \tNLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_SLICE_END1);\n// \tNLA_PUT_U32(msg, OPENWIFI_ATTR_SLICE_END1, tmp);\n\n// \tnla_nest_end(msg, tmdata);\n\n// \tprintf(\"openwifi slice_end1 (duration): %dus\\n\", tmp);\n\n// \treturn 0;\n\n//  nla_put_failure:\n// \treturn -ENOBUFS;\n// }\n// COMMAND(set, slice_end1, \"<slice_end1(duration) in us>\", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_slice_end1, \"set slice_end1\");\n\n// static int handle_get_slice_end1(struct nl80211_state *state,\n// \t\t\t  struct nl_cb *cb,\n// \t\t\t  struct nl_msg *msg,\n// \t\t\t  int argc, char **argv,\n// \t\t\t  enum id_input id)\n// {\n// \tstruct nlattr *tmdata;\n\n// \ttmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);\n// \tif (!tmdata)\n// \t\treturn 1;\n\n// \tNLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_SLICE_END1);\n\n// \tnla_nest_end(msg, tmdata);\n\n// \tnl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_slice_end1_handler, NULL);\n// \treturn 0;\n\n//  nla_put_failure:\n// \treturn -ENOBUFS;\n// }\n// COMMAND(get, slice_end1, \"<slice_end1(duration) in us>\", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_slice_end1, \"get slice_end1\");\n\n\nstatic int cb_openwifi_slice_idx_handler(struct nl_msg *msg, void *arg)\n{\n\tstruct nlattr *attrs[NL80211_ATTR_MAX + 1];\n\tstruct nlattr *tb[OPENWIFI_ATTR_MAX + 1];\n\tstruct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));\n\n\tnla_parse(attrs, NL80211_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL);\n\n\tif (!attrs[NL80211_ATTR_TESTDATA])\n\t\treturn NL_SKIP;\n\n\tnla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);\n\n\tprintf(\"openwifi slice_idx in hex: %08x\\n\", nla_get_u32(tb[OPENWIFI_ATTR_SLICE_IDX]));\n\n\treturn NL_SKIP;\n}\n\nstatic int handle_set_slice_idx(struct nl80211_state *state,\n\t\t\t  struct nl_cb *cb,\n\t\t\t  struct nl_msg *msg,\n\t\t\t  int argc, char **argv,\n\t\t\t  enum id_input id)\n{\n\tstruct nlattr *tmdata;\n\tchar *end;\n\tunsigned int slice_idx;\n\n\t//printf(\"handle_set_slice_idx\\n\");\n\t\n\ttmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);\n\tif (!tmdata) {\n\t\t//printf(\"handle_set_slice_idx 1\\n\");\n\t\treturn 1;\n\t}\n\n\tslice_idx = strtoul(argv[0], &end, 16);\n\n\tif (*end) {\n\t\t//printf(\"handle_set_slice_idx 2 %d\\n\", slice_idx);\n\t\treturn 1;\n\t}\n\n\tNLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_SLICE_IDX);\n\tNLA_PUT_U32(msg, OPENWIFI_ATTR_SLICE_IDX, slice_idx);\n\n\tnla_nest_end(msg, tmdata);\n\n\tprintf(\"openwifi slice_idx in hex: %08x\\n\", slice_idx);\n\n\treturn 0;\n\n nla_put_failure:\n\treturn -ENOBUFS;\n}\nCOMMAND(set, slice_idx, \"<slice_idx in hex>\", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_slice_idx, \"set slice_idx\");\n\nstatic int handle_get_slice_idx(struct nl80211_state *state,\n\t\t\t  struct nl_cb *cb,\n\t\t\t  struct nl_msg *msg,\n\t\t\t  int argc, char **argv,\n\t\t\t  enum id_input id)\n{\n\tstruct nlattr *tmdata;\n\n\ttmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);\n\tif (!tmdata)\n\t\treturn 1;\n\n\tNLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_SLICE_IDX);\n\n\tnla_nest_end(msg, tmdata);\n\n\tnl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_slice_idx_handler, NULL);\n\treturn 0;\n\n nla_put_failure:\n\treturn -ENOBUFS;\n}\nCOMMAND(get, slice_idx, \"<slice_idx in hex>\", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_slice_idx, \"get slice_idx\");\n\nstatic int cb_openwifi_slice_target_mac_addr_handler(struct nl_msg *msg, void *arg)\n{\n\tstruct nlattr *attrs[NL80211_ATTR_MAX + 1];\n\tstruct nlattr *tb[OPENWIFI_ATTR_MAX + 1];\n\tstruct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));\n\n\tnla_parse(attrs, NL80211_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL);\n\n\tif (!attrs[NL80211_ATTR_TESTDATA])\n\t\treturn NL_SKIP;\n\n\tnla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);\n\n\tprintf(\"openwifi slice_target_mac_addr(low32) in hex: %08x\\n\", nla_get_u32(tb[OPENWIFI_ATTR_ADDR]));\n\n\treturn NL_SKIP;\n}\n\nstatic int handle_set_slice_target_mac_addr(struct nl80211_state *state,\n\t\t\t  struct nl_cb *cb,\n\t\t\t  struct nl_msg *msg,\n\t\t\t  int argc, char **argv,\n\t\t\t  enum id_input id)\n{\n\tstruct nlattr *tmdata;\n\tchar *end;\n\tunsigned int slice_target_mac_addr;\n\n\ttmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);\n\tif (!tmdata)\n\t\treturn 1;\n\n\tslice_target_mac_addr = strtoul(argv[0], &end, 16);\n\n\tif (*end)\n\t\treturn 1;\n\n\tNLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_ADDR);\n\tNLA_PUT_U32(msg, OPENWIFI_ATTR_ADDR, slice_target_mac_addr);\n\n\tnla_nest_end(msg, tmdata);\n\n\tprintf(\"openwifi slice_target_mac_addr(low32) in hex: %08x\\n\", slice_target_mac_addr);\n\n\treturn 0;\n\n nla_put_failure:\n\treturn -ENOBUFS;\n}\nCOMMAND(set, addr, \"<slice_target_mac_addr(low32) in hex>\", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_slice_target_mac_addr, \"set addr\");\n\nstatic int handle_get_slice_target_mac_addr(struct nl80211_state *state,\n\t\t\t  struct nl_cb *cb,\n\t\t\t  struct nl_msg *msg,\n\t\t\t  int argc, char **argv,\n\t\t\t  enum id_input id)\n{\n\tstruct nlattr *tmdata;\n\n\ttmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);\n\tif (!tmdata)\n\t\treturn 1;\n\n\tNLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_ADDR);\n\n\tnla_nest_end(msg, tmdata);\n\n\tnl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_slice_target_mac_addr_handler, NULL);\n\treturn 0;\n\n nla_put_failure:\n\treturn -ENOBUFS;\n}\nCOMMAND(get, addr, \"<slice_target_mac_addr(low32) in hex>\", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_slice_target_mac_addr, \"get addr\");\n\nstatic int cb_openwifi_gap_handler(struct nl_msg *msg, void *arg)\n{\n\tstruct nlattr *attrs[NL80211_ATTR_MAX + 1];\n\tstruct nlattr *tb[OPENWIFI_ATTR_MAX + 1];\n\tstruct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));\n\n\tnla_parse(attrs, NL80211_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL);\n\n\tif (!attrs[NL80211_ATTR_TESTDATA])\n\t\treturn NL_SKIP;\n\n\tnla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);\n\n\tprintf(\"openwifi GAP (usec): %d\\n\", nla_get_u32(tb[OPENWIFI_ATTR_GAP]));\n\n\treturn NL_SKIP;\n}\n\nstatic int handle_set_gap(struct nl80211_state *state,\n\t\t\t  struct nl_cb *cb,\n\t\t\t  struct nl_msg *msg,\n\t\t\t  int argc, char **argv,\n\t\t\t  enum id_input id)\n{\n\tstruct nlattr *tmdata;\n\tchar *end;\n\tunsigned int gap_us;\n\n\t//printf(\"handle_set_gap\\n\");\n\ttmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);\n\tif (!tmdata)\n\t\treturn 1;\n\n\tgap_us = strtoul(argv[0], &end, 10);\n\n\tif (*end)\n\t\treturn 1;\n\n\tNLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_GAP);\n\tNLA_PUT_U32(msg, OPENWIFI_ATTR_GAP, gap_us);\n\n\tnla_nest_end(msg, tmdata);\n\treturn 0;\n\n nla_put_failure:\n\treturn -ENOBUFS;\n}\nCOMMAND(set, gap, \"<gap in usec>\", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_gap, \"set inter frame gap of openwifi radio\");\n\nstatic int handle_get_gap(struct nl80211_state *state,\n\t\t\t  struct nl_cb *cb,\n\t\t\t  struct nl_msg *msg,\n\t\t\t  int argc, char **argv,\n\t\t\t  enum id_input id)\n{\n\tstruct nlattr *tmdata;\n\n\ttmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);\n\tif (!tmdata)\n\t\treturn 1;\n\n\tNLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_GAP);\n\n\tnla_nest_end(msg, tmdata);\n\n\tnl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_gap_handler, NULL);\n\treturn 0;\n\n nla_put_failure:\n\treturn -ENOBUFS;\n}\nCOMMAND(get, gap, \"<gap in usec>\", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_gap, \"get inter frame gap of openwifi radio\");\n"
  },
  {
    "path": "user_space/sdrctl_src/nl80211.h",
    "content": "#ifndef __LINUX_NL80211_H\n#define __LINUX_NL80211_H\n/*\n * 802.11 netlink interface public header\n *\n * SPDX-FileCopyrightText: 2006-2010 Johannes Berg <johannes@sipsolutions.net>\n * SPDX-FileCopyrightText: 2008 Michael Wu <flamingice@sourmilk.net>\n * SPDX-FileCopyrightText: 2008 Luis Carlos Cobo <luisca@cozybit.com>\n * SPDX-FileCopyrightText: 2008 Michael Buesch <m@bues.ch>\n * SPDX-FileCopyrightText: 2008, 2009 Luis R. Rodriguez <lrodriguez@atheros.com>\n * SPDX-FileCopyrightText: 2008 Jouni Malinen <jouni.malinen@atheros.com>\n * SPDX-FileCopyrightText: 2008 Colin McCabe <colin@cozybit.com>\n * SPDX-FileCopyrightText: 2015-2017\tIntel Deutschland GmbH\n * SPDX-License-Identifier: ISC\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n/*\n * This header file defines the userspace API to the wireless stack. Please\n * be careful not to break things - i.e. don't move anything around or so\n * unless you can demonstrate that it breaks neither API nor ABI.\n *\n * Additions to the API should be accompanied by actual implementations in\n * an upstream driver, so that example implementations exist in case there\n * are ever concerns about the precise semantics of the API or changes are\n * needed, and to ensure that code for dead (no longer implemented) API\n * can actually be identified and removed.\n * Nonetheless, semantics should also be documented carefully in this file.\n */\n\n#include <linux/types.h>\n\n#define NL80211_GENL_NAME \"nl80211\"\n\n#define NL80211_MULTICAST_GROUP_CONFIG\t\t\"config\"\n#define NL80211_MULTICAST_GROUP_SCAN\t\t\"scan\"\n#define NL80211_MULTICAST_GROUP_REG\t\t\"regulatory\"\n#define NL80211_MULTICAST_GROUP_MLME\t\t\"mlme\"\n#define NL80211_MULTICAST_GROUP_VENDOR\t\t\"vendor\"\n#define NL80211_MULTICAST_GROUP_NAN\t\t\"nan\"\n#define NL80211_MULTICAST_GROUP_TESTMODE\t\"testmode\"\n\n/**\n * DOC: Station handling\n *\n * Stations are added per interface, but a special case exists with VLAN\n * interfaces. When a station is bound to an AP interface, it may be moved\n * into a VLAN identified by a VLAN interface index (%NL80211_ATTR_STA_VLAN).\n * The station is still assumed to belong to the AP interface it was added\n * to.\n *\n * Station handling varies per interface type and depending on the driver's\n * capabilities.\n *\n * For drivers supporting TDLS with external setup (WIPHY_FLAG_SUPPORTS_TDLS\n * and WIPHY_FLAG_TDLS_EXTERNAL_SETUP), the station lifetime is as follows:\n *  - a setup station entry is added, not yet authorized, without any rate\n *    or capability information, this just exists to avoid race conditions\n *  - when the TDLS setup is done, a single NL80211_CMD_SET_STATION is valid\n *    to add rate and capability information to the station and at the same\n *    time mark it authorized.\n *  - %NL80211_TDLS_ENABLE_LINK is then used\n *  - after this, the only valid operation is to remove it by tearing down\n *    the TDLS link (%NL80211_TDLS_DISABLE_LINK)\n *\n * TODO: need more info for other interface types\n */\n\n/**\n * DOC: Frame transmission/registration support\n *\n * Frame transmission and registration support exists to allow userspace\n * management entities such as wpa_supplicant react to management frames\n * that are not being handled by the kernel. This includes, for example,\n * certain classes of action frames that cannot be handled in the kernel\n * for various reasons.\n *\n * Frame registration is done on a per-interface basis and registrations\n * cannot be removed other than by closing the socket. It is possible to\n * specify a registration filter to register, for example, only for a\n * certain type of action frame. In particular with action frames, those\n * that userspace registers for will not be returned as unhandled by the\n * driver, so that the registered application has to take responsibility\n * for doing that.\n *\n * The type of frame that can be registered for is also dependent on the\n * driver and interface type. The frame types are advertised in wiphy\n * attributes so applications know what to expect.\n *\n * NOTE: When an interface changes type while registrations are active,\n *       these registrations are ignored until the interface type is\n *       changed again. This means that changing the interface type can\n *       lead to a situation that couldn't otherwise be produced, but\n *       any such registrations will be dormant in the sense that they\n *       will not be serviced, i.e. they will not receive any frames.\n *\n * Frame transmission allows userspace to send for example the required\n * responses to action frames. It is subject to some sanity checking,\n * but many frames can be transmitted. When a frame was transmitted, its\n * status is indicated to the sending socket.\n *\n * For more technical details, see the corresponding command descriptions\n * below.\n */\n\n/**\n * DOC: Virtual interface / concurrency capabilities\n *\n * Some devices are able to operate with virtual MACs, they can have\n * more than one virtual interface. The capability handling for this\n * is a bit complex though, as there may be a number of restrictions\n * on the types of concurrency that are supported.\n *\n * To start with, each device supports the interface types listed in\n * the %NL80211_ATTR_SUPPORTED_IFTYPES attribute, but by listing the\n * types there no concurrency is implied.\n *\n * Once concurrency is desired, more attributes must be observed:\n * To start with, since some interface types are purely managed in\n * software, like the AP-VLAN type in mac80211 for example, there's\n * an additional list of these, they can be added at any time and\n * are only restricted by some semantic restrictions (e.g. AP-VLAN\n * cannot be added without a corresponding AP interface). This list\n * is exported in the %NL80211_ATTR_SOFTWARE_IFTYPES attribute.\n *\n * Further, the list of supported combinations is exported. This is\n * in the %NL80211_ATTR_INTERFACE_COMBINATIONS attribute. Basically,\n * it exports a list of \"groups\", and at any point in time the\n * interfaces that are currently active must fall into any one of\n * the advertised groups. Within each group, there are restrictions\n * on the number of interfaces of different types that are supported\n * and also the number of different channels, along with potentially\n * some other restrictions. See &enum nl80211_if_combination_attrs.\n *\n * All together, these attributes define the concurrency of virtual\n * interfaces that a given device supports.\n */\n\n/**\n * DOC: packet coalesce support\n *\n * In most cases, host that receives IPv4 and IPv6 multicast/broadcast\n * packets does not do anything with these packets. Therefore the\n * reception of these unwanted packets causes unnecessary processing\n * and power consumption.\n *\n * Packet coalesce feature helps to reduce number of received interrupts\n * to host by buffering these packets in firmware/hardware for some\n * predefined time. Received interrupt will be generated when one of the\n * following events occur.\n * a) Expiration of hardware timer whose expiration time is set to maximum\n * coalescing delay of matching coalesce rule.\n * b) Coalescing buffer in hardware reaches it's limit.\n * c) Packet doesn't match any of the configured coalesce rules.\n *\n * User needs to configure following parameters for creating a coalesce\n * rule.\n * a) Maximum coalescing delay\n * b) List of packet patterns which needs to be matched\n * c) Condition for coalescence. pattern 'match' or 'no match'\n * Multiple such rules can be created.\n */\n\n/**\n * DOC: WPA/WPA2 EAPOL handshake offload\n *\n * By setting @NL80211_EXT_FEATURE_4WAY_HANDSHAKE_STA_PSK flag drivers\n * can indicate they support offloading EAPOL handshakes for WPA/WPA2\n * preshared key authentication. In %NL80211_CMD_CONNECT the preshared\n * key should be specified using %NL80211_ATTR_PMK. Drivers supporting\n * this offload may reject the %NL80211_CMD_CONNECT when no preshared\n * key material is provided, for example when that driver does not\n * support setting the temporal keys through %CMD_NEW_KEY.\n *\n * Similarly @NL80211_EXT_FEATURE_4WAY_HANDSHAKE_STA_1X flag can be\n * set by drivers indicating offload support of the PTK/GTK EAPOL\n * handshakes during 802.1X authentication. In order to use the offload\n * the %NL80211_CMD_CONNECT should have %NL80211_ATTR_WANT_1X_4WAY_HS\n * attribute flag. Drivers supporting this offload may reject the\n * %NL80211_CMD_CONNECT when the attribute flag is not present.\n *\n * For 802.1X the PMK or PMK-R0 are set by providing %NL80211_ATTR_PMK\n * using %NL80211_CMD_SET_PMK. For offloaded FT support also\n * %NL80211_ATTR_PMKR0_NAME must be provided.\n */\n\n/**\n * DOC: FILS shared key authentication offload\n *\n * FILS shared key authentication offload can be advertized by drivers by\n * setting @NL80211_EXT_FEATURE_FILS_SK_OFFLOAD flag. The drivers that support\n * FILS shared key authentication offload should be able to construct the\n * authentication and association frames for FILS shared key authentication and\n * eventually do a key derivation as per IEEE 802.11ai. The below additional\n * parameters should be given to driver in %NL80211_CMD_CONNECT.\n *\t%NL80211_ATTR_FILS_ERP_USERNAME - used to construct keyname_nai\n *\t%NL80211_ATTR_FILS_ERP_REALM - used to construct keyname_nai\n *\t%NL80211_ATTR_FILS_ERP_NEXT_SEQ_NUM - used to construct erp message\n *\t%NL80211_ATTR_FILS_ERP_RRK - used to generate the rIK and rMSK\n * rIK should be used to generate an authentication tag on the ERP message and\n * rMSK should be used to derive a PMKSA.\n * rIK, rMSK should be generated and keyname_nai, sequence number should be used\n * as specified in IETF RFC 6696.\n *\n * When FILS shared key authentication is completed, driver needs to provide the\n * below additional parameters to userspace.\n *\t%NL80211_ATTR_FILS_KEK - used for key renewal\n *\t%NL80211_ATTR_FILS_ERP_NEXT_SEQ_NUM - used in further EAP-RP exchanges\n *\t%NL80211_ATTR_PMKID - used to identify the PMKSA used/generated\n *\t%Nl80211_ATTR_PMK - used to update PMKSA cache in userspace\n * The PMKSA can be maintained in userspace persistently so that it can be used\n * later after reboots or wifi turn off/on also.\n *\n * %NL80211_ATTR_FILS_CACHE_ID is the cache identifier advertized by a FILS\n * capable AP supporting PMK caching. It specifies the scope within which the\n * PMKSAs are cached in an ESS. %NL80211_CMD_SET_PMKSA and\n * %NL80211_CMD_DEL_PMKSA are enhanced to allow support for PMKSA caching based\n * on FILS cache identifier. Additionally %NL80211_ATTR_PMK is used with\n * %NL80211_SET_PMKSA to specify the PMK corresponding to a PMKSA for driver to\n * use in a FILS shared key connection with PMKSA caching.\n */\n\n/**\n * enum nl80211_commands - supported nl80211 commands\n *\n * @NL80211_CMD_UNSPEC: unspecified command to catch errors\n *\n * @NL80211_CMD_GET_WIPHY: request information about a wiphy or dump request\n *\tto get a list of all present wiphys.\n * @NL80211_CMD_SET_WIPHY: set wiphy parameters, needs %NL80211_ATTR_WIPHY or\n *\t%NL80211_ATTR_IFINDEX; can be used to set %NL80211_ATTR_WIPHY_NAME,\n *\t%NL80211_ATTR_WIPHY_TXQ_PARAMS, %NL80211_ATTR_WIPHY_FREQ (and the\n *\tattributes determining the channel width; this is used for setting\n *\tmonitor mode channel),  %NL80211_ATTR_WIPHY_RETRY_SHORT,\n *\t%NL80211_ATTR_WIPHY_RETRY_LONG, %NL80211_ATTR_WIPHY_FRAG_THRESHOLD,\n *\tand/or %NL80211_ATTR_WIPHY_RTS_THRESHOLD.\n *\tHowever, for setting the channel, see %NL80211_CMD_SET_CHANNEL\n *\tinstead, the support here is for backward compatibility only.\n * @NL80211_CMD_NEW_WIPHY: Newly created wiphy, response to get request\n *\tor rename notification. Has attributes %NL80211_ATTR_WIPHY and\n *\t%NL80211_ATTR_WIPHY_NAME.\n * @NL80211_CMD_DEL_WIPHY: Wiphy deleted. Has attributes\n *\t%NL80211_ATTR_WIPHY and %NL80211_ATTR_WIPHY_NAME.\n *\n * @NL80211_CMD_GET_INTERFACE: Request an interface's configuration;\n *\teither a dump request for all interfaces or a specific get with a\n *\tsingle %NL80211_ATTR_IFINDEX is supported.\n * @NL80211_CMD_SET_INTERFACE: Set type of a virtual interface, requires\n *\t%NL80211_ATTR_IFINDEX and %NL80211_ATTR_IFTYPE.\n * @NL80211_CMD_NEW_INTERFACE: Newly created virtual interface or response\n *\tto %NL80211_CMD_GET_INTERFACE. Has %NL80211_ATTR_IFINDEX,\n *\t%NL80211_ATTR_WIPHY and %NL80211_ATTR_IFTYPE attributes. Can also\n *\tbe sent from userspace to request creation of a new virtual interface,\n *\tthen requires attributes %NL80211_ATTR_WIPHY, %NL80211_ATTR_IFTYPE and\n *\t%NL80211_ATTR_IFNAME.\n * @NL80211_CMD_DEL_INTERFACE: Virtual interface was deleted, has attributes\n *\t%NL80211_ATTR_IFINDEX and %NL80211_ATTR_WIPHY. Can also be sent from\n *\tuserspace to request deletion of a virtual interface, then requires\n *\tattribute %NL80211_ATTR_IFINDEX.\n *\n * @NL80211_CMD_GET_KEY: Get sequence counter information for a key specified\n *\tby %NL80211_ATTR_KEY_IDX and/or %NL80211_ATTR_MAC.\n * @NL80211_CMD_SET_KEY: Set key attributes %NL80211_ATTR_KEY_DEFAULT,\n *\t%NL80211_ATTR_KEY_DEFAULT_MGMT, or %NL80211_ATTR_KEY_THRESHOLD.\n * @NL80211_CMD_NEW_KEY: add a key with given %NL80211_ATTR_KEY_DATA,\n *\t%NL80211_ATTR_KEY_IDX, %NL80211_ATTR_MAC, %NL80211_ATTR_KEY_CIPHER,\n *\tand %NL80211_ATTR_KEY_SEQ attributes.\n * @NL80211_CMD_DEL_KEY: delete a key identified by %NL80211_ATTR_KEY_IDX\n *\tor %NL80211_ATTR_MAC.\n *\n * @NL80211_CMD_GET_BEACON: (not used)\n * @NL80211_CMD_SET_BEACON: change the beacon on an access point interface\n *\tusing the %NL80211_ATTR_BEACON_HEAD and %NL80211_ATTR_BEACON_TAIL\n *\tattributes. For drivers that generate the beacon and probe responses\n *\tinternally, the following attributes must be provided: %NL80211_ATTR_IE,\n *\t%NL80211_ATTR_IE_PROBE_RESP and %NL80211_ATTR_IE_ASSOC_RESP.\n * @NL80211_CMD_START_AP: Start AP operation on an AP interface, parameters\n *\tare like for %NL80211_CMD_SET_BEACON, and additionally parameters that\n *\tdo not change are used, these include %NL80211_ATTR_BEACON_INTERVAL,\n *\t%NL80211_ATTR_DTIM_PERIOD, %NL80211_ATTR_SSID,\n *\t%NL80211_ATTR_HIDDEN_SSID, %NL80211_ATTR_CIPHERS_PAIRWISE,\n *\t%NL80211_ATTR_CIPHER_GROUP, %NL80211_ATTR_WPA_VERSIONS,\n *\t%NL80211_ATTR_AKM_SUITES, %NL80211_ATTR_PRIVACY,\n *\t%NL80211_ATTR_AUTH_TYPE, %NL80211_ATTR_INACTIVITY_TIMEOUT,\n *\t%NL80211_ATTR_ACL_POLICY and %NL80211_ATTR_MAC_ADDRS.\n *\tThe channel to use can be set on the interface or be given using the\n *\t%NL80211_ATTR_WIPHY_FREQ and the attributes determining channel width.\n * @NL80211_CMD_NEW_BEACON: old alias for %NL80211_CMD_START_AP\n * @NL80211_CMD_STOP_AP: Stop AP operation on the given interface\n * @NL80211_CMD_DEL_BEACON: old alias for %NL80211_CMD_STOP_AP\n *\n * @NL80211_CMD_GET_STATION: Get station attributes for station identified by\n *\t%NL80211_ATTR_MAC on the interface identified by %NL80211_ATTR_IFINDEX.\n * @NL80211_CMD_SET_STATION: Set station attributes for station identified by\n *\t%NL80211_ATTR_MAC on the interface identified by %NL80211_ATTR_IFINDEX.\n * @NL80211_CMD_NEW_STATION: Add a station with given attributes to the\n *\tthe interface identified by %NL80211_ATTR_IFINDEX.\n * @NL80211_CMD_DEL_STATION: Remove a station identified by %NL80211_ATTR_MAC\n *\tor, if no MAC address given, all stations, on the interface identified\n *\tby %NL80211_ATTR_IFINDEX. %NL80211_ATTR_MGMT_SUBTYPE and\n *\t%NL80211_ATTR_REASON_CODE can optionally be used to specify which type\n *\tof disconnection indication should be sent to the station\n *\t(Deauthentication or Disassociation frame and reason code for that\n *\tframe).\n *\n * @NL80211_CMD_GET_MPATH: Get mesh path attributes for mesh path to\n * \tdestination %NL80211_ATTR_MAC on the interface identified by\n * \t%NL80211_ATTR_IFINDEX.\n * @NL80211_CMD_SET_MPATH:  Set mesh path attributes for mesh path to\n * \tdestination %NL80211_ATTR_MAC on the interface identified by\n * \t%NL80211_ATTR_IFINDEX.\n * @NL80211_CMD_NEW_MPATH: Create a new mesh path for the destination given by\n *\t%NL80211_ATTR_MAC via %NL80211_ATTR_MPATH_NEXT_HOP.\n * @NL80211_CMD_DEL_MPATH: Delete a mesh path to the destination given by\n *\t%NL80211_ATTR_MAC.\n * @NL80211_CMD_NEW_PATH: Add a mesh path with given attributes to the\n *\tthe interface identified by %NL80211_ATTR_IFINDEX.\n * @NL80211_CMD_DEL_PATH: Remove a mesh path identified by %NL80211_ATTR_MAC\n *\tor, if no MAC address given, all mesh paths, on the interface identified\n *\tby %NL80211_ATTR_IFINDEX.\n * @NL80211_CMD_SET_BSS: Set BSS attributes for BSS identified by\n *\t%NL80211_ATTR_IFINDEX.\n *\n * @NL80211_CMD_GET_REG: ask the wireless core to send us its currently set\n *\tregulatory domain. If %NL80211_ATTR_WIPHY is specified and the device\n *\thas a private regulatory domain, it will be returned. Otherwise, the\n *\tglobal regdomain will be returned.\n *\tA device will have a private regulatory domain if it uses the\n *\tregulatory_hint() API. Even when a private regdomain is used the channel\n *\tinformation will still be mended according to further hints from\n *\tthe regulatory core to help with compliance. A dump version of this API\n *\tis now available which will returns the global regdomain as well as\n *\tall private regdomains of present wiphys (for those that have it).\n *\tIf a wiphy is self-managed (%NL80211_ATTR_WIPHY_SELF_MANAGED_REG), then\n *\tits private regdomain is the only valid one for it. The regulatory\n *\tcore is not used to help with compliance in this case.\n * @NL80211_CMD_SET_REG: Set current regulatory domain. CRDA sends this command\n *\tafter being queried by the kernel. CRDA replies by sending a regulatory\n *\tdomain structure which consists of %NL80211_ATTR_REG_ALPHA set to our\n *\tcurrent alpha2 if it found a match. It also provides\n * \tNL80211_ATTR_REG_RULE_FLAGS, and a set of regulatory rules. Each\n * \tregulatory rule is a nested set of attributes  given by\n * \t%NL80211_ATTR_REG_RULE_FREQ_[START|END] and\n * \t%NL80211_ATTR_FREQ_RANGE_MAX_BW with an attached power rule given by\n * \t%NL80211_ATTR_REG_RULE_POWER_MAX_ANT_GAIN and\n * \t%NL80211_ATTR_REG_RULE_POWER_MAX_EIRP.\n * @NL80211_CMD_REQ_SET_REG: ask the wireless core to set the regulatory domain\n * \tto the specified ISO/IEC 3166-1 alpha2 country code. The core will\n * \tstore this as a valid request and then query userspace for it.\n *\n * @NL80211_CMD_GET_MESH_CONFIG: Get mesh networking properties for the\n *\tinterface identified by %NL80211_ATTR_IFINDEX\n *\n * @NL80211_CMD_SET_MESH_CONFIG: Set mesh networking properties for the\n *      interface identified by %NL80211_ATTR_IFINDEX\n *\n * @NL80211_CMD_SET_MGMT_EXTRA_IE: Set extra IEs for management frames. The\n *\tinterface is identified with %NL80211_ATTR_IFINDEX and the management\n *\tframe subtype with %NL80211_ATTR_MGMT_SUBTYPE. The extra IE data to be\n *\tadded to the end of the specified management frame is specified with\n *\t%NL80211_ATTR_IE. If the command succeeds, the requested data will be\n *\tadded to all specified management frames generated by\n *\tkernel/firmware/driver.\n *\tNote: This command has been removed and it is only reserved at this\n *\tpoint to avoid re-using existing command number. The functionality this\n *\tcommand was planned for has been provided with cleaner design with the\n *\toption to specify additional IEs in NL80211_CMD_TRIGGER_SCAN,\n *\tNL80211_CMD_AUTHENTICATE, NL80211_CMD_ASSOCIATE,\n *\tNL80211_CMD_DEAUTHENTICATE, and NL80211_CMD_DISASSOCIATE.\n *\n * @NL80211_CMD_GET_SCAN: get scan results\n * @NL80211_CMD_TRIGGER_SCAN: trigger a new scan with the given parameters\n *\t%NL80211_ATTR_TX_NO_CCK_RATE is used to decide whether to send the\n *\tprobe requests at CCK rate or not. %NL80211_ATTR_BSSID can be used to\n *\tspecify a BSSID to scan for; if not included, the wildcard BSSID will\n *\tbe used.\n * @NL80211_CMD_NEW_SCAN_RESULTS: scan notification (as a reply to\n *\tNL80211_CMD_GET_SCAN and on the \"scan\" multicast group)\n * @NL80211_CMD_SCAN_ABORTED: scan was aborted, for unspecified reasons,\n *\tpartial scan results may be available\n *\n * @NL80211_CMD_START_SCHED_SCAN: start a scheduled scan at certain\n *\tintervals and certain number of cycles, as specified by\n *\t%NL80211_ATTR_SCHED_SCAN_PLANS. If %NL80211_ATTR_SCHED_SCAN_PLANS is\n *\tnot specified and only %NL80211_ATTR_SCHED_SCAN_INTERVAL is specified,\n *\tscheduled scan will run in an infinite loop with the specified interval.\n *\tThese attributes are mutually exclusive,\n *\ti.e. NL80211_ATTR_SCHED_SCAN_INTERVAL must not be passed if\n *\tNL80211_ATTR_SCHED_SCAN_PLANS is defined.\n *\tIf for some reason scheduled scan is aborted by the driver, all scan\n *\tplans are canceled (including scan plans that did not start yet).\n *\tLike with normal scans, if SSIDs (%NL80211_ATTR_SCAN_SSIDS)\n *\tare passed, they are used in the probe requests.  For\n *\tbroadcast, a broadcast SSID must be passed (ie. an empty\n *\tstring).  If no SSID is passed, no probe requests are sent and\n *\ta passive scan is performed.  %NL80211_ATTR_SCAN_FREQUENCIES,\n *\tif passed, define which channels should be scanned; if not\n *\tpassed, all channels allowed for the current regulatory domain\n *\tare used.  Extra IEs can also be passed from the userspace by\n *\tusing the %NL80211_ATTR_IE attribute.  The first cycle of the\n *\tscheduled scan can be delayed by %NL80211_ATTR_SCHED_SCAN_DELAY\n *\tis supplied. If the device supports multiple concurrent scheduled\n *\tscans, it will allow such when the caller provides the flag attribute\n *\t%NL80211_ATTR_SCHED_SCAN_MULTI to indicate user-space support for it.\n * @NL80211_CMD_STOP_SCHED_SCAN: stop a scheduled scan. Returns -ENOENT if\n *\tscheduled scan is not running. The caller may assume that as soon\n *\tas the call returns, it is safe to start a new scheduled scan again.\n * @NL80211_CMD_SCHED_SCAN_RESULTS: indicates that there are scheduled scan\n *\tresults available.\n * @NL80211_CMD_SCHED_SCAN_STOPPED: indicates that the scheduled scan has\n *\tstopped.  The driver may issue this event at any time during a\n *\tscheduled scan.  One reason for stopping the scan is if the hardware\n *\tdoes not support starting an association or a normal scan while running\n *\ta scheduled scan.  This event is also sent when the\n *\t%NL80211_CMD_STOP_SCHED_SCAN command is received or when the interface\n *\tis brought down while a scheduled scan was running.\n *\n * @NL80211_CMD_GET_SURVEY: get survey resuls, e.g. channel occupation\n *      or noise level\n * @NL80211_CMD_NEW_SURVEY_RESULTS: survey data notification (as a reply to\n *\tNL80211_CMD_GET_SURVEY and on the \"scan\" multicast group)\n *\n * @NL80211_CMD_SET_PMKSA: Add a PMKSA cache entry using %NL80211_ATTR_MAC\n *\t(for the BSSID), %NL80211_ATTR_PMKID, and optionally %NL80211_ATTR_PMK\n *\t(PMK is used for PTKSA derivation in case of FILS shared key offload) or\n *\tusing %NL80211_ATTR_SSID, %NL80211_ATTR_FILS_CACHE_ID,\n *\t%NL80211_ATTR_PMKID, and %NL80211_ATTR_PMK in case of FILS\n *\tauthentication where %NL80211_ATTR_FILS_CACHE_ID is the identifier\n *\tadvertized by a FILS capable AP identifying the scope of PMKSA in an\n *\tESS.\n * @NL80211_CMD_DEL_PMKSA: Delete a PMKSA cache entry, using %NL80211_ATTR_MAC\n *\t(for the BSSID) and %NL80211_ATTR_PMKID or using %NL80211_ATTR_SSID,\n *\t%NL80211_ATTR_FILS_CACHE_ID, and %NL80211_ATTR_PMKID in case of FILS\n *\tauthentication.\n * @NL80211_CMD_FLUSH_PMKSA: Flush all PMKSA cache entries.\n *\n * @NL80211_CMD_REG_CHANGE: indicates to userspace the regulatory domain\n * \thas been changed and provides details of the request information\n * \tthat caused the change such as who initiated the regulatory request\n * \t(%NL80211_ATTR_REG_INITIATOR), the wiphy_idx\n * \t(%NL80211_ATTR_REG_ALPHA2) on which the request was made from if\n * \tthe initiator was %NL80211_REGDOM_SET_BY_COUNTRY_IE or\n * \t%NL80211_REGDOM_SET_BY_DRIVER, the type of regulatory domain\n * \tset (%NL80211_ATTR_REG_TYPE), if the type of regulatory domain is\n * \t%NL80211_REG_TYPE_COUNTRY the alpha2 to which we have moved on\n * \tto (%NL80211_ATTR_REG_ALPHA2).\n * @NL80211_CMD_REG_BEACON_HINT: indicates to userspace that an AP beacon\n * \thas been found while world roaming thus enabling active scan or\n * \tany mode of operation that initiates TX (beacons) on a channel\n * \twhere we would not have been able to do either before. As an example\n * \tif you are world roaming (regulatory domain set to world or if your\n * \tdriver is using a custom world roaming regulatory domain) and while\n * \tdoing a passive scan on the 5 GHz band you find an AP there (if not\n * \ton a DFS channel) you will now be able to actively scan for that AP\n * \tor use AP mode on your card on that same channel. Note that this will\n * \tnever be used for channels 1-11 on the 2 GHz band as they are always\n * \tenabled world wide. This beacon hint is only sent if your device had\n * \teither disabled active scanning or beaconing on a channel. We send to\n * \tuserspace the wiphy on which we removed a restriction from\n * \t(%NL80211_ATTR_WIPHY) and the channel on which this occurred\n * \tbefore (%NL80211_ATTR_FREQ_BEFORE) and after (%NL80211_ATTR_FREQ_AFTER)\n * \tthe beacon hint was processed.\n *\n * @NL80211_CMD_AUTHENTICATE: authentication request and notification.\n *\tThis command is used both as a command (request to authenticate) and\n *\tas an event on the \"mlme\" multicast group indicating completion of the\n *\tauthentication process.\n *\tWhen used as a command, %NL80211_ATTR_IFINDEX is used to identify the\n *\tinterface. %NL80211_ATTR_MAC is used to specify PeerSTAAddress (and\n *\tBSSID in case of station mode). %NL80211_ATTR_SSID is used to specify\n *\tthe SSID (mainly for association, but is included in authentication\n *\trequest, too, to help BSS selection. %NL80211_ATTR_WIPHY_FREQ is used\n *\tto specify the frequence of the channel in MHz. %NL80211_ATTR_AUTH_TYPE\n *\tis used to specify the authentication type. %NL80211_ATTR_IE is used to\n *\tdefine IEs (VendorSpecificInfo, but also including RSN IE and FT IEs)\n *\tto be added to the frame.\n *\tWhen used as an event, this reports reception of an Authentication\n *\tframe in station and IBSS modes when the local MLME processed the\n *\tframe, i.e., it was for the local STA and was received in correct\n *\tstate. This is similar to MLME-AUTHENTICATE.confirm primitive in the\n *\tMLME SAP interface (kernel providing MLME, userspace SME). The\n *\tincluded %NL80211_ATTR_FRAME attribute contains the management frame\n *\t(including both the header and frame body, but not FCS). This event is\n *\talso used to indicate if the authentication attempt timed out. In that\n *\tcase the %NL80211_ATTR_FRAME attribute is replaced with a\n *\t%NL80211_ATTR_TIMED_OUT flag (and %NL80211_ATTR_MAC to indicate which\n *\tpending authentication timed out).\n * @NL80211_CMD_ASSOCIATE: association request and notification; like\n *\tNL80211_CMD_AUTHENTICATE but for Association and Reassociation\n *\t(similar to MLME-ASSOCIATE.request, MLME-REASSOCIATE.request,\n *\tMLME-ASSOCIATE.confirm or MLME-REASSOCIATE.confirm primitives). The\n *\t%NL80211_ATTR_PREV_BSSID attribute is used to specify whether the\n *\trequest is for the initial association to an ESS (that attribute not\n *\tincluded) or for reassociation within the ESS (that attribute is\n *\tincluded).\n * @NL80211_CMD_DEAUTHENTICATE: deauthentication request and notification; like\n *\tNL80211_CMD_AUTHENTICATE but for Deauthentication frames (similar to\n *\tMLME-DEAUTHENTICATION.request and MLME-DEAUTHENTICATE.indication\n *\tprimitives).\n * @NL80211_CMD_DISASSOCIATE: disassociation request and notification; like\n *\tNL80211_CMD_AUTHENTICATE but for Disassociation frames (similar to\n *\tMLME-DISASSOCIATE.request and MLME-DISASSOCIATE.indication primitives).\n *\n * @NL80211_CMD_MICHAEL_MIC_FAILURE: notification of a locally detected Michael\n *\tMIC (part of TKIP) failure; sent on the \"mlme\" multicast group; the\n *\tevent includes %NL80211_ATTR_MAC to describe the source MAC address of\n *\tthe frame with invalid MIC, %NL80211_ATTR_KEY_TYPE to show the key\n *\ttype, %NL80211_ATTR_KEY_IDX to indicate the key identifier, and\n *\t%NL80211_ATTR_KEY_SEQ to indicate the TSC value of the frame; this\n *\tevent matches with MLME-MICHAELMICFAILURE.indication() primitive\n *\n * @NL80211_CMD_JOIN_IBSS: Join a new IBSS -- given at least an SSID and a\n *\tFREQ attribute (for the initial frequency if no peer can be found)\n *\tand optionally a MAC (as BSSID) and FREQ_FIXED attribute if those\n *\tshould be fixed rather than automatically determined. Can only be\n *\texecuted on a network interface that is UP, and fixed BSSID/FREQ\n *\tmay be rejected. Another optional parameter is the beacon interval,\n *\tgiven in the %NL80211_ATTR_BEACON_INTERVAL attribute, which if not\n *\tgiven defaults to 100 TU (102.4ms).\n * @NL80211_CMD_LEAVE_IBSS: Leave the IBSS -- no special arguments, the IBSS is\n *\tdetermined by the network interface.\n *\n * @NL80211_CMD_TESTMODE: testmode command, takes a wiphy (or ifindex) attribute\n *\tto identify the device, and the TESTDATA blob attribute to pass through\n *\tto the driver.\n *\n * @NL80211_CMD_CONNECT: connection request and notification; this command\n *\trequests to connect to a specified network but without separating\n *\tauth and assoc steps. For this, you need to specify the SSID in a\n *\t%NL80211_ATTR_SSID attribute, and can optionally specify the association\n *\tIEs in %NL80211_ATTR_IE, %NL80211_ATTR_AUTH_TYPE, %NL80211_ATTR_USE_MFP,\n *\t%NL80211_ATTR_MAC, %NL80211_ATTR_WIPHY_FREQ, %NL80211_ATTR_CONTROL_PORT,\n *\t%NL80211_ATTR_CONTROL_PORT_ETHERTYPE,\n *\t%NL80211_ATTR_CONTROL_PORT_NO_ENCRYPT, %NL80211_ATTR_MAC_HINT, and\n *\t%NL80211_ATTR_WIPHY_FREQ_HINT.\n *\tIf included, %NL80211_ATTR_MAC and %NL80211_ATTR_WIPHY_FREQ are\n *\trestrictions on BSS selection, i.e., they effectively prevent roaming\n *\twithin the ESS. %NL80211_ATTR_MAC_HINT and %NL80211_ATTR_WIPHY_FREQ_HINT\n *\tcan be included to provide a recommendation of the initial BSS while\n *\tallowing the driver to roam to other BSSes within the ESS and also to\n *\tignore this recommendation if the indicated BSS is not ideal. Only one\n *\tset of BSSID,frequency parameters is used (i.e., either the enforcing\n *\t%NL80211_ATTR_MAC,%NL80211_ATTR_WIPHY_FREQ or the less strict\n *\t%NL80211_ATTR_MAC_HINT and %NL80211_ATTR_WIPHY_FREQ_HINT).\n *\t%NL80211_ATTR_PREV_BSSID can be used to request a reassociation within\n *\tthe ESS in case the device is already associated and an association with\n *\ta different BSS is desired.\n *\tBackground scan period can optionally be\n *\tspecified in %NL80211_ATTR_BG_SCAN_PERIOD,\n *\tif not specified default background scan configuration\n *\tin driver is used and if period value is 0, bg scan will be disabled.\n *\tThis attribute is ignored if driver does not support roam scan.\n *\tIt is also sent as an event, with the BSSID and response IEs when the\n *\tconnection is established or failed to be established. This can be\n *\tdetermined by the %NL80211_ATTR_STATUS_CODE attribute (0 = success,\n *\tnon-zero = failure). If %NL80211_ATTR_TIMED_OUT is included in the\n *\tevent, the connection attempt failed due to not being able to initiate\n *\tauthentication/association or not receiving a response from the AP.\n *\tNon-zero %NL80211_ATTR_STATUS_CODE value is indicated in that case as\n *\twell to remain backwards compatible.\n * @NL80211_CMD_ROAM: notification indicating the card/driver roamed by itself.\n *\tWhen the driver roamed in a network that requires 802.1X authentication,\n *\t%NL80211_ATTR_PORT_AUTHORIZED should be set if the 802.1X authentication\n *\twas done by the driver or if roaming was done using Fast Transition\n *\tprotocol (in which case 802.1X authentication is not needed). If\n *\t%NL80211_ATTR_PORT_AUTHORIZED is not set, user space is responsible for\n *\tthe 802.1X authentication.\n * @NL80211_CMD_DISCONNECT: drop a given connection; also used to notify\n *\tuserspace that a connection was dropped by the AP or due to other\n *\treasons, for this the %NL80211_ATTR_DISCONNECTED_BY_AP and\n *\t%NL80211_ATTR_REASON_CODE attributes are used.\n *\n * @NL80211_CMD_SET_WIPHY_NETNS: Set a wiphy's netns. Note that all devices\n *\tassociated with this wiphy must be down and will follow.\n *\n * @NL80211_CMD_REMAIN_ON_CHANNEL: Request to remain awake on the specified\n *\tchannel for the specified amount of time. This can be used to do\n *\toff-channel operations like transmit a Public Action frame and wait for\n *\ta response while being associated to an AP on another channel.\n *\t%NL80211_ATTR_IFINDEX is used to specify which interface (and thus\n *\tradio) is used. %NL80211_ATTR_WIPHY_FREQ is used to specify the\n *\tfrequency for the operation.\n *\t%NL80211_ATTR_DURATION is used to specify the duration in milliseconds\n *\tto remain on the channel. This command is also used as an event to\n *\tnotify when the requested duration starts (it may take a while for the\n *\tdriver to schedule this time due to other concurrent needs for the\n *\tradio).\n *\tWhen called, this operation returns a cookie (%NL80211_ATTR_COOKIE)\n *\tthat will be included with any events pertaining to this request;\n *\tthe cookie is also used to cancel the request.\n * @NL80211_CMD_CANCEL_REMAIN_ON_CHANNEL: This command can be used to cancel a\n *\tpending remain-on-channel duration if the desired operation has been\n *\tcompleted prior to expiration of the originally requested duration.\n *\t%NL80211_ATTR_WIPHY or %NL80211_ATTR_IFINDEX is used to specify the\n *\tradio. The %NL80211_ATTR_COOKIE attribute must be given as well to\n *\tuniquely identify the request.\n *\tThis command is also used as an event to notify when a requested\n *\tremain-on-channel duration has expired.\n *\n * @NL80211_CMD_SET_TX_BITRATE_MASK: Set the mask of rates to be used in TX\n *\trate selection. %NL80211_ATTR_IFINDEX is used to specify the interface\n *\tand @NL80211_ATTR_TX_RATES the set of allowed rates.\n *\n * @NL80211_CMD_REGISTER_FRAME: Register for receiving certain mgmt frames\n *\t(via @NL80211_CMD_FRAME) for processing in userspace. This command\n *\trequires an interface index, a frame type attribute (optional for\n *\tbackward compatibility reasons, if not given assumes action frames)\n *\tand a match attribute containing the first few bytes of the frame\n *\tthat should match, e.g. a single byte for only a category match or\n *\tfour bytes for vendor frames including the OUI. The registration\n *\tcannot be dropped, but is removed automatically when the netlink\n *\tsocket is closed. Multiple registrations can be made.\n * @NL80211_CMD_REGISTER_ACTION: Alias for @NL80211_CMD_REGISTER_FRAME for\n *\tbackward compatibility\n * @NL80211_CMD_FRAME: Management frame TX request and RX notification. This\n *\tcommand is used both as a request to transmit a management frame and\n *\tas an event indicating reception of a frame that was not processed in\n *\tkernel code, but is for us (i.e., which may need to be processed in a\n *\tuser space application). %NL80211_ATTR_FRAME is used to specify the\n *\tframe contents (including header). %NL80211_ATTR_WIPHY_FREQ is used\n *\tto indicate on which channel the frame is to be transmitted or was\n *\treceived. If this channel is not the current channel (remain-on-channel\n *\tor the operational channel) the device will switch to the given channel\n *\tand transmit the frame, optionally waiting for a response for the time\n *\tspecified using %NL80211_ATTR_DURATION. When called, this operation\n *\treturns a cookie (%NL80211_ATTR_COOKIE) that will be included with the\n *\tTX status event pertaining to the TX request.\n *\t%NL80211_ATTR_TX_NO_CCK_RATE is used to decide whether to send the\n *\tmanagement frames at CCK rate or not in 2GHz band.\n *\t%NL80211_ATTR_CSA_C_OFFSETS_TX is an array of offsets to CSA\n *\tcounters which will be updated to the current value. This attribute\n *\tis used during CSA period.\n * @NL80211_CMD_FRAME_WAIT_CANCEL: When an off-channel TX was requested, this\n *\tcommand may be used with the corresponding cookie to cancel the wait\n *\ttime if it is known that it is no longer necessary.\n * @NL80211_CMD_ACTION: Alias for @NL80211_CMD_FRAME for backward compatibility.\n * @NL80211_CMD_FRAME_TX_STATUS: Report TX status of a management frame\n *\ttransmitted with %NL80211_CMD_FRAME. %NL80211_ATTR_COOKIE identifies\n *\tthe TX command and %NL80211_ATTR_FRAME includes the contents of the\n *\tframe. %NL80211_ATTR_ACK flag is included if the recipient acknowledged\n *\tthe frame.\n * @NL80211_CMD_ACTION_TX_STATUS: Alias for @NL80211_CMD_FRAME_TX_STATUS for\n *\tbackward compatibility.\n *\n * @NL80211_CMD_SET_POWER_SAVE: Set powersave, using %NL80211_ATTR_PS_STATE\n * @NL80211_CMD_GET_POWER_SAVE: Get powersave status in %NL80211_ATTR_PS_STATE\n *\n * @NL80211_CMD_SET_CQM: Connection quality monitor configuration. This command\n *\tis used to configure connection quality monitoring notification trigger\n *\tlevels.\n * @NL80211_CMD_NOTIFY_CQM: Connection quality monitor notification. This\n *\tcommand is used as an event to indicate the that a trigger level was\n *\treached.\n * @NL80211_CMD_SET_CHANNEL: Set the channel (using %NL80211_ATTR_WIPHY_FREQ\n *\tand the attributes determining channel width) the given interface\n *\t(identifed by %NL80211_ATTR_IFINDEX) shall operate on.\n *\tIn case multiple channels are supported by the device, the mechanism\n *\twith which it switches channels is implementation-defined.\n *\tWhen a monitor interface is given, it can only switch channel while\n *\tno other interfaces are operating to avoid disturbing the operation\n *\tof any other interfaces, and other interfaces will again take\n *\tprecedence when they are used.\n *\n * @NL80211_CMD_SET_WDS_PEER: Set the MAC address of the peer on a WDS interface.\n *\n * @NL80211_CMD_SET_MULTICAST_TO_UNICAST: Configure if this AP should perform\n *\tmulticast to unicast conversion. When enabled, all multicast packets\n *\twith ethertype ARP, IPv4 or IPv6 (possibly within an 802.1Q header)\n *\twill be sent out to each station once with the destination (multicast)\n *\tMAC address replaced by the station's MAC address. Note that this may\n *\tbreak certain expectations of the receiver, e.g. the ability to drop\n *\tunicast IP packets encapsulated in multicast L2 frames, or the ability\n *\tto not send destination unreachable messages in such cases.\n *\tThis can only be toggled per BSS. Configure this on an interface of\n *\ttype %NL80211_IFTYPE_AP. It applies to all its VLAN interfaces\n *\t(%NL80211_IFTYPE_AP_VLAN), except for those in 4addr (WDS) mode.\n *\tIf %NL80211_ATTR_MULTICAST_TO_UNICAST_ENABLED is not present with this\n *\tcommand, the feature is disabled.\n *\n * @NL80211_CMD_JOIN_MESH: Join a mesh. The mesh ID must be given, and initial\n *\tmesh config parameters may be given.\n * @NL80211_CMD_LEAVE_MESH: Leave the mesh network -- no special arguments, the\n *\tnetwork is determined by the network interface.\n *\n * @NL80211_CMD_UNPROT_DEAUTHENTICATE: Unprotected deauthentication frame\n *\tnotification. This event is used to indicate that an unprotected\n *\tdeauthentication frame was dropped when MFP is in use.\n * @NL80211_CMD_UNPROT_DISASSOCIATE: Unprotected disassociation frame\n *\tnotification. This event is used to indicate that an unprotected\n *\tdisassociation frame was dropped when MFP is in use.\n *\n * @NL80211_CMD_NEW_PEER_CANDIDATE: Notification on the reception of a\n *      beacon or probe response from a compatible mesh peer.  This is only\n *      sent while no station information (sta_info) exists for the new peer\n *      candidate and when @NL80211_MESH_SETUP_USERSPACE_AUTH,\n *      @NL80211_MESH_SETUP_USERSPACE_AMPE, or\n *      @NL80211_MESH_SETUP_USERSPACE_MPM is set.  On reception of this\n *      notification, userspace may decide to create a new station\n *      (@NL80211_CMD_NEW_STATION).  To stop this notification from\n *      reoccurring, the userspace authentication daemon may want to create the\n *      new station with the AUTHENTICATED flag unset and maybe change it later\n *      depending on the authentication result.\n *\n * @NL80211_CMD_GET_WOWLAN: get Wake-on-Wireless-LAN (WoWLAN) settings.\n * @NL80211_CMD_SET_WOWLAN: set Wake-on-Wireless-LAN (WoWLAN) settings.\n *\tSince wireless is more complex than wired ethernet, it supports\n *\tvarious triggers. These triggers can be configured through this\n *\tcommand with the %NL80211_ATTR_WOWLAN_TRIGGERS attribute. For\n *\tmore background information, see\n *\thttp://wireless.kernel.org/en/users/Documentation/WoWLAN.\n *\tThe @NL80211_CMD_SET_WOWLAN command can also be used as a notification\n *\tfrom the driver reporting the wakeup reason. In this case, the\n *\t@NL80211_ATTR_WOWLAN_TRIGGERS attribute will contain the reason\n *\tfor the wakeup, if it was caused by wireless. If it is not present\n *\tin the wakeup notification, the wireless device didn't cause the\n *\twakeup but reports that it was woken up.\n *\n * @NL80211_CMD_SET_REKEY_OFFLOAD: This command is used give the driver\n *\tthe necessary information for supporting GTK rekey offload. This\n *\tfeature is typically used during WoWLAN. The configuration data\n *\tis contained in %NL80211_ATTR_REKEY_DATA (which is nested and\n *\tcontains the data in sub-attributes). After rekeying happened,\n *\tthis command may also be sent by the driver as an MLME event to\n *\tinform userspace of the new replay counter.\n *\n * @NL80211_CMD_PMKSA_CANDIDATE: This is used as an event to inform userspace\n *\tof PMKSA caching candidates.\n *\n * @NL80211_CMD_TDLS_OPER: Perform a high-level TDLS command (e.g. link setup).\n *\tIn addition, this can be used as an event to request userspace to take\n *\tactions on TDLS links (set up a new link or tear down an existing one).\n *\tIn such events, %NL80211_ATTR_TDLS_OPERATION indicates the requested\n *\toperation, %NL80211_ATTR_MAC contains the peer MAC address, and\n *\t%NL80211_ATTR_REASON_CODE the reason code to be used (only with\n *\t%NL80211_TDLS_TEARDOWN).\n * @NL80211_CMD_TDLS_MGMT: Send a TDLS management frame. The\n *\t%NL80211_ATTR_TDLS_ACTION attribute determines the type of frame to be\n *\tsent. Public Action codes (802.11-2012 8.1.5.1) will be sent as\n *\t802.11 management frames, while TDLS action codes (802.11-2012\n *\t8.5.13.1) will be encapsulated and sent as data frames. The currently\n *\tsupported Public Action code is %WLAN_PUB_ACTION_TDLS_DISCOVER_RES\n *\tand the currently supported TDLS actions codes are given in\n *\t&enum ieee80211_tdls_actioncode.\n *\n * @NL80211_CMD_UNEXPECTED_FRAME: Used by an application controlling an AP\n *\t(or GO) interface (i.e. hostapd) to ask for unexpected frames to\n *\timplement sending deauth to stations that send unexpected class 3\n *\tframes. Also used as the event sent by the kernel when such a frame\n *\tis received.\n *\tFor the event, the %NL80211_ATTR_MAC attribute carries the TA and\n *\tother attributes like the interface index are present.\n *\tIf used as the command it must have an interface index and you can\n *\tonly unsubscribe from the event by closing the socket. Subscription\n *\tis also for %NL80211_CMD_UNEXPECTED_4ADDR_FRAME events.\n *\n * @NL80211_CMD_UNEXPECTED_4ADDR_FRAME: Sent as an event indicating that the\n *\tassociated station identified by %NL80211_ATTR_MAC sent a 4addr frame\n *\tand wasn't already in a 4-addr VLAN. The event will be sent similarly\n *\tto the %NL80211_CMD_UNEXPECTED_FRAME event, to the same listener.\n *\n * @NL80211_CMD_PROBE_CLIENT: Probe an associated station on an AP interface\n *\tby sending a null data frame to it and reporting when the frame is\n *\tacknowledged. This is used to allow timing out inactive clients. Uses\n *\t%NL80211_ATTR_IFINDEX and %NL80211_ATTR_MAC. The command returns a\n *\tdirect reply with an %NL80211_ATTR_COOKIE that is later used to match\n *\tup the event with the request. The event includes the same data and\n *\thas %NL80211_ATTR_ACK set if the frame was ACKed.\n *\n * @NL80211_CMD_REGISTER_BEACONS: Register this socket to receive beacons from\n *\tother BSSes when any interfaces are in AP mode. This helps implement\n *\tOLBC handling in hostapd. Beacons are reported in %NL80211_CMD_FRAME\n *\tmessages. Note that per PHY only one application may register.\n *\n * @NL80211_CMD_SET_NOACK_MAP: sets a bitmap for the individual TIDs whether\n *      No Acknowledgement Policy should be applied.\n *\n * @NL80211_CMD_CH_SWITCH_NOTIFY: An AP or GO may decide to switch channels\n *\tindependently of the userspace SME, send this event indicating\n *\t%NL80211_ATTR_IFINDEX is now on %NL80211_ATTR_WIPHY_FREQ and the\n *\tattributes determining channel width.  This indication may also be\n *\tsent when a remotely-initiated switch (e.g., when a STA receives a CSA\n *\tfrom the remote AP) is completed;\n *\n * @NL80211_CMD_CH_SWITCH_STARTED_NOTIFY: Notify that a channel switch\n *\thas been started on an interface, regardless of the initiator\n *\t(ie. whether it was requested from a remote device or\n *\tinitiated on our own).  It indicates that\n *\t%NL80211_ATTR_IFINDEX will be on %NL80211_ATTR_WIPHY_FREQ\n *\tafter %NL80211_ATTR_CH_SWITCH_COUNT TBTT's.  The userspace may\n *\tdecide to react to this indication by requesting other\n *\tinterfaces to change channel as well.\n *\n * @NL80211_CMD_START_P2P_DEVICE: Start the given P2P Device, identified by\n *\tits %NL80211_ATTR_WDEV identifier. It must have been created with\n *\t%NL80211_CMD_NEW_INTERFACE previously. After it has been started, the\n *\tP2P Device can be used for P2P operations, e.g. remain-on-channel and\n *\tpublic action frame TX.\n * @NL80211_CMD_STOP_P2P_DEVICE: Stop the given P2P Device, identified by\n *\tits %NL80211_ATTR_WDEV identifier.\n *\n * @NL80211_CMD_CONN_FAILED: connection request to an AP failed; used to\n *\tnotify userspace that AP has rejected the connection request from a\n *\tstation, due to particular reason. %NL80211_ATTR_CONN_FAILED_REASON\n *\tis used for this.\n *\n * @NL80211_CMD_SET_MCAST_RATE: Change the rate used to send multicast frames\n *\tfor IBSS or MESH vif.\n *\n * @NL80211_CMD_SET_MAC_ACL: sets ACL for MAC address based access control.\n *\tThis is to be used with the drivers advertising the support of MAC\n *\taddress based access control. List of MAC addresses is passed in\n *\t%NL80211_ATTR_MAC_ADDRS and ACL policy is passed in\n *\t%NL80211_ATTR_ACL_POLICY. Driver will enable ACL with this list, if it\n *\tis not already done. The new list will replace any existing list. Driver\n *\twill clear its ACL when the list of MAC addresses passed is empty. This\n *\tcommand is used in AP/P2P GO mode. Driver has to make sure to clear its\n *\tACL list during %NL80211_CMD_STOP_AP.\n *\n * @NL80211_CMD_RADAR_DETECT: Start a Channel availability check (CAC). Once\n *\ta radar is detected or the channel availability scan (CAC) has finished\n *\tor was aborted, or a radar was detected, usermode will be notified with\n *\tthis event. This command is also used to notify userspace about radars\n *\twhile operating on this channel.\n *\t%NL80211_ATTR_RADAR_EVENT is used to inform about the type of the\n *\tevent.\n *\n * @NL80211_CMD_GET_PROTOCOL_FEATURES: Get global nl80211 protocol features,\n *\ti.e. features for the nl80211 protocol rather than device features.\n *\tReturns the features in the %NL80211_ATTR_PROTOCOL_FEATURES bitmap.\n *\n * @NL80211_CMD_UPDATE_FT_IES: Pass down the most up-to-date Fast Transition\n *\tInformation Element to the WLAN driver\n *\n * @NL80211_CMD_FT_EVENT: Send a Fast transition event from the WLAN driver\n *\tto the supplicant. This will carry the target AP's MAC address along\n *\twith the relevant Information Elements. This event is used to report\n *\treceived FT IEs (MDIE, FTIE, RSN IE, TIE, RICIE).\n *\n * @NL80211_CMD_CRIT_PROTOCOL_START: Indicates user-space will start running\n *\ta critical protocol that needs more reliability in the connection to\n *\tcomplete.\n *\n * @NL80211_CMD_CRIT_PROTOCOL_STOP: Indicates the connection reliability can\n *\treturn back to normal.\n *\n * @NL80211_CMD_GET_COALESCE: Get currently supported coalesce rules.\n * @NL80211_CMD_SET_COALESCE: Configure coalesce rules or clear existing rules.\n *\n * @NL80211_CMD_CHANNEL_SWITCH: Perform a channel switch by announcing the\n *\tthe new channel information (Channel Switch Announcement - CSA)\n *\tin the beacon for some time (as defined in the\n *\t%NL80211_ATTR_CH_SWITCH_COUNT parameter) and then change to the\n *\tnew channel. Userspace provides the new channel information (using\n *\t%NL80211_ATTR_WIPHY_FREQ and the attributes determining channel\n *\twidth). %NL80211_ATTR_CH_SWITCH_BLOCK_TX may be supplied to inform\n *\tother station that transmission must be blocked until the channel\n *\tswitch is complete.\n *\n * @NL80211_CMD_VENDOR: Vendor-specified command/event. The command is specified\n *\tby the %NL80211_ATTR_VENDOR_ID attribute and a sub-command in\n *\t%NL80211_ATTR_VENDOR_SUBCMD. Parameter(s) can be transported in\n *\t%NL80211_ATTR_VENDOR_DATA.\n *\tFor feature advertisement, the %NL80211_ATTR_VENDOR_DATA attribute is\n *\tused in the wiphy data as a nested attribute containing descriptions\n *\t(&struct nl80211_vendor_cmd_info) of the supported vendor commands.\n *\tThis may also be sent as an event with the same attributes.\n *\n * @NL80211_CMD_SET_QOS_MAP: Set Interworking QoS mapping for IP DSCP values.\n *\tThe QoS mapping information is included in %NL80211_ATTR_QOS_MAP. If\n *\tthat attribute is not included, QoS mapping is disabled. Since this\n *\tQoS mapping is relevant for IP packets, it is only valid during an\n *\tassociation. This is cleared on disassociation and AP restart.\n *\n * @NL80211_CMD_ADD_TX_TS: Ask the kernel to add a traffic stream for the given\n *\t%NL80211_ATTR_TSID and %NL80211_ATTR_MAC with %NL80211_ATTR_USER_PRIO\n *\tand %NL80211_ATTR_ADMITTED_TIME parameters.\n *\tNote that the action frame handshake with the AP shall be handled by\n *\tuserspace via the normal management RX/TX framework, this only sets\n *\tup the TX TS in the driver/device.\n *\tIf the admitted time attribute is not added then the request just checks\n *\tif a subsequent setup could be successful, the intent is to use this to\n *\tavoid setting up a session with the AP when local restrictions would\n *\tmake that impossible. However, the subsequent \"real\" setup may still\n *\tfail even if the check was successful.\n * @NL80211_CMD_DEL_TX_TS: Remove an existing TS with the %NL80211_ATTR_TSID\n *\tand %NL80211_ATTR_MAC parameters. It isn't necessary to call this\n *\tbefore removing a station entry entirely, or before disassociating\n *\tor similar, cleanup will happen in the driver/device in this case.\n *\n * @NL80211_CMD_GET_MPP: Get mesh path attributes for mesh proxy path to\n *\tdestination %NL80211_ATTR_MAC on the interface identified by\n *\t%NL80211_ATTR_IFINDEX.\n *\n * @NL80211_CMD_JOIN_OCB: Join the OCB network. The center frequency and\n *\tbandwidth of a channel must be given.\n * @NL80211_CMD_LEAVE_OCB: Leave the OCB network -- no special arguments, the\n *\tnetwork is determined by the network interface.\n *\n * @NL80211_CMD_TDLS_CHANNEL_SWITCH: Start channel-switching with a TDLS peer,\n *\tidentified by the %NL80211_ATTR_MAC parameter. A target channel is\n *\tprovided via %NL80211_ATTR_WIPHY_FREQ and other attributes determining\n *\tchannel width/type. The target operating class is given via\n *\t%NL80211_ATTR_OPER_CLASS.\n *\tThe driver is responsible for continually initiating channel-switching\n *\toperations and returning to the base channel for communication with the\n *\tAP.\n * @NL80211_CMD_TDLS_CANCEL_CHANNEL_SWITCH: Stop channel-switching with a TDLS\n *\tpeer given by %NL80211_ATTR_MAC. Both peers must be on the base channel\n *\twhen this command completes.\n *\n * @NL80211_CMD_WIPHY_REG_CHANGE: Similar to %NL80211_CMD_REG_CHANGE, but used\n *\tas an event to indicate changes for devices with wiphy-specific regdom\n *\tmanagement.\n *\n * @NL80211_CMD_ABORT_SCAN: Stop an ongoing scan. Returns -ENOENT if a scan is\n *\tnot running. The driver indicates the status of the scan through\n *\tcfg80211_scan_done().\n *\n * @NL80211_CMD_START_NAN: Start NAN operation, identified by its\n *\t%NL80211_ATTR_WDEV interface. This interface must have been\n *\tpreviously created with %NL80211_CMD_NEW_INTERFACE. After it\n *\thas been started, the NAN interface will create or join a\n *\tcluster. This command must have a valid\n *\t%NL80211_ATTR_NAN_MASTER_PREF attribute and optional\n *\t%NL80211_ATTR_BANDS attributes.  If %NL80211_ATTR_BANDS is\n *\tomitted or set to 0, it means don't-care and the device will\n *\tdecide what to use.  After this command NAN functions can be\n *\tadded.\n * @NL80211_CMD_STOP_NAN: Stop the NAN operation, identified by\n *\tits %NL80211_ATTR_WDEV interface.\n * @NL80211_CMD_ADD_NAN_FUNCTION: Add a NAN function. The function is defined\n *\twith %NL80211_ATTR_NAN_FUNC nested attribute. When called, this\n *\toperation returns the strictly positive and unique instance id\n *\t(%NL80211_ATTR_NAN_FUNC_INST_ID) and a cookie (%NL80211_ATTR_COOKIE)\n *\tof the function upon success.\n *\tSince instance ID's can be re-used, this cookie is the right\n *\tway to identify the function. This will avoid races when a termination\n *\tevent is handled by the user space after it has already added a new\n *\tfunction that got the same instance id from the kernel as the one\n *\twhich just terminated.\n *\tThis cookie may be used in NAN events even before the command\n *\treturns, so userspace shouldn't process NAN events until it processes\n *\tthe response to this command.\n *\tLook at %NL80211_ATTR_SOCKET_OWNER as well.\n * @NL80211_CMD_DEL_NAN_FUNCTION: Delete a NAN function by cookie.\n *\tThis command is also used as a notification sent when a NAN function is\n *\tterminated. This will contain a %NL80211_ATTR_NAN_FUNC_INST_ID\n *\tand %NL80211_ATTR_COOKIE attributes.\n * @NL80211_CMD_CHANGE_NAN_CONFIG: Change current NAN\n *\tconfiguration. NAN must be operational (%NL80211_CMD_START_NAN\n *\twas executed).  It must contain at least one of the following\n *\tattributes: %NL80211_ATTR_NAN_MASTER_PREF,\n *\t%NL80211_ATTR_BANDS.  If %NL80211_ATTR_BANDS is omitted, the\n *\tcurrent configuration is not changed.  If it is present but\n *\tset to zero, the configuration is changed to don't-care\n *\t(i.e. the device can decide what to do).\n * @NL80211_CMD_NAN_FUNC_MATCH: Notification sent when a match is reported.\n *\tThis will contain a %NL80211_ATTR_NAN_MATCH nested attribute and\n *\t%NL80211_ATTR_COOKIE.\n *\n * @NL80211_CMD_UPDATE_CONNECT_PARAMS: Update one or more connect parameters\n *\tfor subsequent roaming cases if the driver or firmware uses internal\n *\tBSS selection. This command can be issued only while connected and it\n *\tdoes not result in a change for the current association. Currently,\n *\tonly the %NL80211_ATTR_IE data is used and updated with this command.\n *\n * @NL80211_CMD_SET_PMK: For offloaded 4-Way handshake, set the PMK or PMK-R0\n *\tfor the given authenticator address (specified with &NL80211_ATTR_MAC).\n *\tWhen &NL80211_ATTR_PMKR0_NAME is set, &NL80211_ATTR_PMK specifies the\n *\tPMK-R0, otherwise it specifies the PMK.\n * @NL80211_CMD_DEL_PMK: For offloaded 4-Way handshake, delete the previously\n *\tconfigured PMK for the authenticator address identified by\n *\t&NL80211_ATTR_MAC.\n *\n * @NL80211_CMD_MAX: highest used command number\n * @__NL80211_CMD_AFTER_LAST: internal use\n */\nenum nl80211_commands {\n/* don't change the order or add anything between, this is ABI! */\n\tNL80211_CMD_UNSPEC,\n\n\tNL80211_CMD_GET_WIPHY,\t\t/* can dump */\n\tNL80211_CMD_SET_WIPHY,\n\tNL80211_CMD_NEW_WIPHY,\n\tNL80211_CMD_DEL_WIPHY,\n\n\tNL80211_CMD_GET_INTERFACE,\t/* can dump */\n\tNL80211_CMD_SET_INTERFACE,\n\tNL80211_CMD_NEW_INTERFACE,\n\tNL80211_CMD_DEL_INTERFACE,\n\n\tNL80211_CMD_GET_KEY,\n\tNL80211_CMD_SET_KEY,\n\tNL80211_CMD_NEW_KEY,\n\tNL80211_CMD_DEL_KEY,\n\n\tNL80211_CMD_GET_BEACON,\n\tNL80211_CMD_SET_BEACON,\n\tNL80211_CMD_START_AP,\n\tNL80211_CMD_NEW_BEACON = NL80211_CMD_START_AP,\n\tNL80211_CMD_STOP_AP,\n\tNL80211_CMD_DEL_BEACON = NL80211_CMD_STOP_AP,\n\n\tNL80211_CMD_GET_STATION,\n\tNL80211_CMD_SET_STATION,\n\tNL80211_CMD_NEW_STATION,\n\tNL80211_CMD_DEL_STATION,\n\n\tNL80211_CMD_GET_MPATH,\n\tNL80211_CMD_SET_MPATH,\n\tNL80211_CMD_NEW_MPATH,\n\tNL80211_CMD_DEL_MPATH,\n\n\tNL80211_CMD_SET_BSS,\n\n\tNL80211_CMD_SET_REG,\n\tNL80211_CMD_REQ_SET_REG,\n\n\tNL80211_CMD_GET_MESH_CONFIG,\n\tNL80211_CMD_SET_MESH_CONFIG,\n\n\tNL80211_CMD_SET_MGMT_EXTRA_IE /* reserved; not used */,\n\n\tNL80211_CMD_GET_REG,\n\n\tNL80211_CMD_GET_SCAN,\n\tNL80211_CMD_TRIGGER_SCAN,\n\tNL80211_CMD_NEW_SCAN_RESULTS,\n\tNL80211_CMD_SCAN_ABORTED,\n\n\tNL80211_CMD_REG_CHANGE,\n\n\tNL80211_CMD_AUTHENTICATE,\n\tNL80211_CMD_ASSOCIATE,\n\tNL80211_CMD_DEAUTHENTICATE,\n\tNL80211_CMD_DISASSOCIATE,\n\n\tNL80211_CMD_MICHAEL_MIC_FAILURE,\n\n\tNL80211_CMD_REG_BEACON_HINT,\n\n\tNL80211_CMD_JOIN_IBSS,\n\tNL80211_CMD_LEAVE_IBSS,\n\n\tNL80211_CMD_TESTMODE,\n\n\tNL80211_CMD_CONNECT,\n\tNL80211_CMD_ROAM,\n\tNL80211_CMD_DISCONNECT,\n\n\tNL80211_CMD_SET_WIPHY_NETNS,\n\n\tNL80211_CMD_GET_SURVEY,\n\tNL80211_CMD_NEW_SURVEY_RESULTS,\n\n\tNL80211_CMD_SET_PMKSA,\n\tNL80211_CMD_DEL_PMKSA,\n\tNL80211_CMD_FLUSH_PMKSA,\n\n\tNL80211_CMD_REMAIN_ON_CHANNEL,\n\tNL80211_CMD_CANCEL_REMAIN_ON_CHANNEL,\n\n\tNL80211_CMD_SET_TX_BITRATE_MASK,\n\n\tNL80211_CMD_REGISTER_FRAME,\n\tNL80211_CMD_REGISTER_ACTION = NL80211_CMD_REGISTER_FRAME,\n\tNL80211_CMD_FRAME,\n\tNL80211_CMD_ACTION = NL80211_CMD_FRAME,\n\tNL80211_CMD_FRAME_TX_STATUS,\n\tNL80211_CMD_ACTION_TX_STATUS = NL80211_CMD_FRAME_TX_STATUS,\n\n\tNL80211_CMD_SET_POWER_SAVE,\n\tNL80211_CMD_GET_POWER_SAVE,\n\n\tNL80211_CMD_SET_CQM,\n\tNL80211_CMD_NOTIFY_CQM,\n\n\tNL80211_CMD_SET_CHANNEL,\n\tNL80211_CMD_SET_WDS_PEER,\n\n\tNL80211_CMD_FRAME_WAIT_CANCEL,\n\n\tNL80211_CMD_JOIN_MESH,\n\tNL80211_CMD_LEAVE_MESH,\n\n\tNL80211_CMD_UNPROT_DEAUTHENTICATE,\n\tNL80211_CMD_UNPROT_DISASSOCIATE,\n\n\tNL80211_CMD_NEW_PEER_CANDIDATE,\n\n\tNL80211_CMD_GET_WOWLAN,\n\tNL80211_CMD_SET_WOWLAN,\n\n\tNL80211_CMD_START_SCHED_SCAN,\n\tNL80211_CMD_STOP_SCHED_SCAN,\n\tNL80211_CMD_SCHED_SCAN_RESULTS,\n\tNL80211_CMD_SCHED_SCAN_STOPPED,\n\n\tNL80211_CMD_SET_REKEY_OFFLOAD,\n\n\tNL80211_CMD_PMKSA_CANDIDATE,\n\n\tNL80211_CMD_TDLS_OPER,\n\tNL80211_CMD_TDLS_MGMT,\n\n\tNL80211_CMD_UNEXPECTED_FRAME,\n\n\tNL80211_CMD_PROBE_CLIENT,\n\n\tNL80211_CMD_REGISTER_BEACONS,\n\n\tNL80211_CMD_UNEXPECTED_4ADDR_FRAME,\n\n\tNL80211_CMD_SET_NOACK_MAP,\n\n\tNL80211_CMD_CH_SWITCH_NOTIFY,\n\n\tNL80211_CMD_START_P2P_DEVICE,\n\tNL80211_CMD_STOP_P2P_DEVICE,\n\n\tNL80211_CMD_CONN_FAILED,\n\n\tNL80211_CMD_SET_MCAST_RATE,\n\n\tNL80211_CMD_SET_MAC_ACL,\n\n\tNL80211_CMD_RADAR_DETECT,\n\n\tNL80211_CMD_GET_PROTOCOL_FEATURES,\n\n\tNL80211_CMD_UPDATE_FT_IES,\n\tNL80211_CMD_FT_EVENT,\n\n\tNL80211_CMD_CRIT_PROTOCOL_START,\n\tNL80211_CMD_CRIT_PROTOCOL_STOP,\n\n\tNL80211_CMD_GET_COALESCE,\n\tNL80211_CMD_SET_COALESCE,\n\n\tNL80211_CMD_CHANNEL_SWITCH,\n\n\tNL80211_CMD_VENDOR,\n\n\tNL80211_CMD_SET_QOS_MAP,\n\n\tNL80211_CMD_ADD_TX_TS,\n\tNL80211_CMD_DEL_TX_TS,\n\n\tNL80211_CMD_GET_MPP,\n\n\tNL80211_CMD_JOIN_OCB,\n\tNL80211_CMD_LEAVE_OCB,\n\n\tNL80211_CMD_CH_SWITCH_STARTED_NOTIFY,\n\n\tNL80211_CMD_TDLS_CHANNEL_SWITCH,\n\tNL80211_CMD_TDLS_CANCEL_CHANNEL_SWITCH,\n\n\tNL80211_CMD_WIPHY_REG_CHANGE,\n\n\tNL80211_CMD_ABORT_SCAN,\n\n\tNL80211_CMD_START_NAN,\n\tNL80211_CMD_STOP_NAN,\n\tNL80211_CMD_ADD_NAN_FUNCTION,\n\tNL80211_CMD_DEL_NAN_FUNCTION,\n\tNL80211_CMD_CHANGE_NAN_CONFIG,\n\tNL80211_CMD_NAN_MATCH,\n\n\tNL80211_CMD_SET_MULTICAST_TO_UNICAST,\n\n\tNL80211_CMD_UPDATE_CONNECT_PARAMS,\n\n\tNL80211_CMD_SET_PMK,\n\tNL80211_CMD_DEL_PMK,\n\n\t/* add new commands above here */\n\n\t/* used to define NL80211_CMD_MAX below */\n\t__NL80211_CMD_AFTER_LAST,\n\tNL80211_CMD_MAX = __NL80211_CMD_AFTER_LAST - 1\n};\n\n/*\n * Allow user space programs to use #ifdef on new commands by defining them\n * here\n */\n#define NL80211_CMD_SET_BSS NL80211_CMD_SET_BSS\n#define NL80211_CMD_SET_MGMT_EXTRA_IE NL80211_CMD_SET_MGMT_EXTRA_IE\n#define NL80211_CMD_REG_CHANGE NL80211_CMD_REG_CHANGE\n#define NL80211_CMD_AUTHENTICATE NL80211_CMD_AUTHENTICATE\n#define NL80211_CMD_ASSOCIATE NL80211_CMD_ASSOCIATE\n#define NL80211_CMD_DEAUTHENTICATE NL80211_CMD_DEAUTHENTICATE\n#define NL80211_CMD_DISASSOCIATE NL80211_CMD_DISASSOCIATE\n#define NL80211_CMD_REG_BEACON_HINT NL80211_CMD_REG_BEACON_HINT\n\n#define NL80211_ATTR_FEATURE_FLAGS NL80211_ATTR_FEATURE_FLAGS\n\n/* source-level API compatibility */\n#define NL80211_CMD_GET_MESH_PARAMS NL80211_CMD_GET_MESH_CONFIG\n#define NL80211_CMD_SET_MESH_PARAMS NL80211_CMD_SET_MESH_CONFIG\n#define NL80211_MESH_SETUP_VENDOR_PATH_SEL_IE NL80211_MESH_SETUP_IE\n\n/**\n * enum nl80211_attrs - nl80211 netlink attributes\n *\n * @NL80211_ATTR_UNSPEC: unspecified attribute to catch errors\n *\n * @NL80211_ATTR_WIPHY: index of wiphy to operate on, cf.\n *\t/sys/class/ieee80211/<phyname>/index\n * @NL80211_ATTR_WIPHY_NAME: wiphy name (used for renaming)\n * @NL80211_ATTR_WIPHY_TXQ_PARAMS: a nested array of TX queue parameters\n * @NL80211_ATTR_WIPHY_FREQ: frequency of the selected channel in MHz,\n *\tdefines the channel together with the (deprecated)\n *\t%NL80211_ATTR_WIPHY_CHANNEL_TYPE attribute or the attributes\n *\t%NL80211_ATTR_CHANNEL_WIDTH and if needed %NL80211_ATTR_CENTER_FREQ1\n *\tand %NL80211_ATTR_CENTER_FREQ2\n * @NL80211_ATTR_CHANNEL_WIDTH: u32 attribute containing one of the values\n *\tof &enum nl80211_chan_width, describing the channel width. See the\n *\tdocumentation of the enum for more information.\n * @NL80211_ATTR_CENTER_FREQ1: Center frequency of the first part of the\n *\tchannel, used for anything but 20 MHz bandwidth\n * @NL80211_ATTR_CENTER_FREQ2: Center frequency of the second part of the\n *\tchannel, used only for 80+80 MHz bandwidth\n * @NL80211_ATTR_WIPHY_CHANNEL_TYPE: included with NL80211_ATTR_WIPHY_FREQ\n *\tif HT20 or HT40 are to be used (i.e., HT disabled if not included):\n *\tNL80211_CHAN_NO_HT = HT not allowed (i.e., same as not including\n *\t\tthis attribute)\n *\tNL80211_CHAN_HT20 = HT20 only\n *\tNL80211_CHAN_HT40MINUS = secondary channel is below the primary channel\n *\tNL80211_CHAN_HT40PLUS = secondary channel is above the primary channel\n *\tThis attribute is now deprecated.\n * @NL80211_ATTR_WIPHY_RETRY_SHORT: TX retry limit for frames whose length is\n *\tless than or equal to the RTS threshold; allowed range: 1..255;\n *\tdot11ShortRetryLimit; u8\n * @NL80211_ATTR_WIPHY_RETRY_LONG: TX retry limit for frames whose length is\n *\tgreater than the RTS threshold; allowed range: 1..255;\n *\tdot11ShortLongLimit; u8\n * @NL80211_ATTR_WIPHY_FRAG_THRESHOLD: fragmentation threshold, i.e., maximum\n *\tlength in octets for frames; allowed range: 256..8000, disable\n *\tfragmentation with (u32)-1; dot11FragmentationThreshold; u32\n * @NL80211_ATTR_WIPHY_RTS_THRESHOLD: RTS threshold (TX frames with length\n *\tlarger than or equal to this use RTS/CTS handshake); allowed range:\n *\t0..65536, disable with (u32)-1; dot11RTSThreshold; u32\n * @NL80211_ATTR_WIPHY_COVERAGE_CLASS: Coverage Class as defined by IEEE 802.11\n *\tsection 7.3.2.9; dot11CoverageClass; u8\n *\n * @NL80211_ATTR_IFINDEX: network interface index of the device to operate on\n * @NL80211_ATTR_IFNAME: network interface name\n * @NL80211_ATTR_IFTYPE: type of virtual interface, see &enum nl80211_iftype\n *\n * @NL80211_ATTR_WDEV: wireless device identifier, used for pseudo-devices\n *\tthat don't have a netdev (u64)\n *\n * @NL80211_ATTR_MAC: MAC address (various uses)\n *\n * @NL80211_ATTR_KEY_DATA: (temporal) key data; for TKIP this consists of\n *\t16 bytes encryption key followed by 8 bytes each for TX and RX MIC\n *\tkeys\n * @NL80211_ATTR_KEY_IDX: key ID (u8, 0-3)\n * @NL80211_ATTR_KEY_CIPHER: key cipher suite (u32, as defined by IEEE 802.11\n *\tsection 7.3.2.25.1, e.g. 0x000FAC04)\n * @NL80211_ATTR_KEY_SEQ: transmit key sequence number (IV/PN) for TKIP and\n *\tCCMP keys, each six bytes in little endian\n * @NL80211_ATTR_KEY_DEFAULT: Flag attribute indicating the key is default key\n * @NL80211_ATTR_KEY_DEFAULT_MGMT: Flag attribute indicating the key is the\n *\tdefault management key\n * @NL80211_ATTR_CIPHER_SUITES_PAIRWISE: For crypto settings for connect or\n *\tother commands, indicates which pairwise cipher suites are used\n * @NL80211_ATTR_CIPHER_SUITE_GROUP: For crypto settings for connect or\n *\tother commands, indicates which group cipher suite is used\n *\n * @NL80211_ATTR_BEACON_INTERVAL: beacon interval in TU\n * @NL80211_ATTR_DTIM_PERIOD: DTIM period for beaconing\n * @NL80211_ATTR_BEACON_HEAD: portion of the beacon before the TIM IE\n * @NL80211_ATTR_BEACON_TAIL: portion of the beacon after the TIM IE\n *\n * @NL80211_ATTR_STA_AID: Association ID for the station (u16)\n * @NL80211_ATTR_STA_FLAGS: flags, nested element with NLA_FLAG attributes of\n *\t&enum nl80211_sta_flags (deprecated, use %NL80211_ATTR_STA_FLAGS2)\n * @NL80211_ATTR_STA_LISTEN_INTERVAL: listen interval as defined by\n *\tIEEE 802.11 7.3.1.6 (u16).\n * @NL80211_ATTR_STA_SUPPORTED_RATES: supported rates, array of supported\n *\trates as defined by IEEE 802.11 7.3.2.2 but without the length\n *\trestriction (at most %NL80211_MAX_SUPP_RATES).\n * @NL80211_ATTR_STA_VLAN: interface index of VLAN interface to move station\n *\tto, or the AP interface the station was originally added to to.\n * @NL80211_ATTR_STA_INFO: information about a station, part of station info\n *\tgiven for %NL80211_CMD_GET_STATION, nested attribute containing\n *\tinfo as possible, see &enum nl80211_sta_info.\n *\n * @NL80211_ATTR_WIPHY_BANDS: Information about an operating bands,\n *\tconsisting of a nested array.\n *\n * @NL80211_ATTR_MESH_ID: mesh id (1-32 bytes).\n * @NL80211_ATTR_STA_PLINK_ACTION: action to perform on the mesh peer link\n *\t(see &enum nl80211_plink_action).\n * @NL80211_ATTR_MPATH_NEXT_HOP: MAC address of the next hop for a mesh path.\n * @NL80211_ATTR_MPATH_INFO: information about a mesh_path, part of mesh path\n * \tinfo given for %NL80211_CMD_GET_MPATH, nested attribute described at\n *\t&enum nl80211_mpath_info.\n *\n * @NL80211_ATTR_MNTR_FLAGS: flags, nested element with NLA_FLAG attributes of\n *      &enum nl80211_mntr_flags.\n *\n * @NL80211_ATTR_REG_ALPHA2: an ISO-3166-alpha2 country code for which the\n * \tcurrent regulatory domain should be set to or is already set to.\n * \tFor example, 'CR', for Costa Rica. This attribute is used by the kernel\n * \tto query the CRDA to retrieve one regulatory domain. This attribute can\n * \talso be used by userspace to query the kernel for the currently set\n * \tregulatory domain. We chose an alpha2 as that is also used by the\n * \tIEEE-802.11 country information element to identify a country.\n * \tUsers can also simply ask the wireless core to set regulatory domain\n * \tto a specific alpha2.\n * @NL80211_ATTR_REG_RULES: a nested array of regulatory domain regulatory\n *\trules.\n *\n * @NL80211_ATTR_BSS_CTS_PROT: whether CTS protection is enabled (u8, 0 or 1)\n * @NL80211_ATTR_BSS_SHORT_PREAMBLE: whether short preamble is enabled\n *\t(u8, 0 or 1)\n * @NL80211_ATTR_BSS_SHORT_SLOT_TIME: whether short slot time enabled\n *\t(u8, 0 or 1)\n * @NL80211_ATTR_BSS_BASIC_RATES: basic rates, array of basic\n *\trates in format defined by IEEE 802.11 7.3.2.2 but without the length\n *\trestriction (at most %NL80211_MAX_SUPP_RATES).\n *\n * @NL80211_ATTR_HT_CAPABILITY: HT Capability information element (from\n *\tassociation request when used with NL80211_CMD_NEW_STATION)\n *\n * @NL80211_ATTR_SUPPORTED_IFTYPES: nested attribute containing all\n *\tsupported interface types, each a flag attribute with the number\n *\tof the interface mode.\n *\n * @NL80211_ATTR_MGMT_SUBTYPE: Management frame subtype for\n *\t%NL80211_CMD_SET_MGMT_EXTRA_IE.\n *\n * @NL80211_ATTR_IE: Information element(s) data (used, e.g., with\n *\t%NL80211_CMD_SET_MGMT_EXTRA_IE).\n *\n * @NL80211_ATTR_MAX_NUM_SCAN_SSIDS: number of SSIDs you can scan with\n *\ta single scan request, a wiphy attribute.\n * @NL80211_ATTR_MAX_NUM_SCHED_SCAN_SSIDS: number of SSIDs you can\n *\tscan with a single scheduled scan request, a wiphy attribute.\n * @NL80211_ATTR_MAX_SCAN_IE_LEN: maximum length of information elements\n *\tthat can be added to a scan request\n * @NL80211_ATTR_MAX_SCHED_SCAN_IE_LEN: maximum length of information\n *\telements that can be added to a scheduled scan request\n * @NL80211_ATTR_MAX_MATCH_SETS: maximum number of sets that can be\n *\tused with @NL80211_ATTR_SCHED_SCAN_MATCH, a wiphy attribute.\n *\n * @NL80211_ATTR_SCAN_FREQUENCIES: nested attribute with frequencies (in MHz)\n * @NL80211_ATTR_SCAN_SSIDS: nested attribute with SSIDs, leave out for passive\n *\tscanning and include a zero-length SSID (wildcard) for wildcard scan\n * @NL80211_ATTR_BSS: scan result BSS\n *\n * @NL80211_ATTR_REG_INITIATOR: indicates who requested the regulatory domain\n * \tcurrently in effect. This could be any of the %NL80211_REGDOM_SET_BY_*\n * @NL80211_ATTR_REG_TYPE: indicates the type of the regulatory domain currently\n * \tset. This can be one of the nl80211_reg_type (%NL80211_REGDOM_TYPE_*)\n *\n * @NL80211_ATTR_SUPPORTED_COMMANDS: wiphy attribute that specifies\n *\tan array of command numbers (i.e. a mapping index to command number)\n *\tthat the driver for the given wiphy supports.\n *\n * @NL80211_ATTR_FRAME: frame data (binary attribute), including frame header\n *\tand body, but not FCS; used, e.g., with NL80211_CMD_AUTHENTICATE and\n *\tNL80211_CMD_ASSOCIATE events\n * @NL80211_ATTR_SSID: SSID (binary attribute, 0..32 octets)\n * @NL80211_ATTR_AUTH_TYPE: AuthenticationType, see &enum nl80211_auth_type,\n *\trepresented as a u32\n * @NL80211_ATTR_REASON_CODE: ReasonCode for %NL80211_CMD_DEAUTHENTICATE and\n *\t%NL80211_CMD_DISASSOCIATE, u16\n *\n * @NL80211_ATTR_KEY_TYPE: Key Type, see &enum nl80211_key_type, represented as\n *\ta u32\n *\n * @NL80211_ATTR_FREQ_BEFORE: A channel which has suffered a regulatory change\n * \tdue to considerations from a beacon hint. This attribute reflects\n * \tthe state of the channel _before_ the beacon hint processing. This\n * \tattributes consists of a nested attribute containing\n * \tNL80211_FREQUENCY_ATTR_*\n * @NL80211_ATTR_FREQ_AFTER: A channel which has suffered a regulatory change\n * \tdue to considerations from a beacon hint. This attribute reflects\n * \tthe state of the channel _after_ the beacon hint processing. This\n * \tattributes consists of a nested attribute containing\n * \tNL80211_FREQUENCY_ATTR_*\n *\n * @NL80211_ATTR_CIPHER_SUITES: a set of u32 values indicating the supported\n *\tcipher suites\n *\n * @NL80211_ATTR_FREQ_FIXED: a flag indicating the IBSS should not try to look\n *\tfor other networks on different channels\n *\n * @NL80211_ATTR_TIMED_OUT: a flag indicating than an operation timed out; this\n *\tis used, e.g., with %NL80211_CMD_AUTHENTICATE event\n *\n * @NL80211_ATTR_USE_MFP: Whether management frame protection (IEEE 802.11w) is\n *\tused for the association (&enum nl80211_mfp, represented as a u32);\n *\tthis attribute can be used\n *\twith %NL80211_CMD_ASSOCIATE and %NL80211_CMD_CONNECT requests\n *\n * @NL80211_ATTR_STA_FLAGS2: Attribute containing a\n *\t&struct nl80211_sta_flag_update.\n *\n * @NL80211_ATTR_CONTROL_PORT: A flag indicating whether user space controls\n *\tIEEE 802.1X port, i.e., sets/clears %NL80211_STA_FLAG_AUTHORIZED, in\n *\tstation mode. If the flag is included in %NL80211_CMD_ASSOCIATE\n *\trequest, the driver will assume that the port is unauthorized until\n *\tauthorized by user space. Otherwise, port is marked authorized by\n *\tdefault in station mode.\n * @NL80211_ATTR_CONTROL_PORT_ETHERTYPE: A 16-bit value indicating the\n *\tethertype that will be used for key negotiation. It can be\n *\tspecified with the associate and connect commands. If it is not\n *\tspecified, the value defaults to 0x888E (PAE, 802.1X). This\n *\tattribute is also used as a flag in the wiphy information to\n *\tindicate that protocols other than PAE are supported.\n * @NL80211_ATTR_CONTROL_PORT_NO_ENCRYPT: When included along with\n *\t%NL80211_ATTR_CONTROL_PORT_ETHERTYPE, indicates that the custom\n *\tethertype frames used for key negotiation must not be encrypted.\n *\n * @NL80211_ATTR_TESTDATA: Testmode data blob, passed through to the driver.\n *\tWe recommend using nested, driver-specific attributes within this.\n *\n * @NL80211_ATTR_DISCONNECTED_BY_AP: A flag indicating that the DISCONNECT\n *\tevent was due to the AP disconnecting the station, and not due to\n *\ta local disconnect request.\n * @NL80211_ATTR_STATUS_CODE: StatusCode for the %NL80211_CMD_CONNECT\n *\tevent (u16)\n * @NL80211_ATTR_PRIVACY: Flag attribute, used with connect(), indicating\n *\tthat protected APs should be used. This is also used with NEW_BEACON to\n *\tindicate that the BSS is to use protection.\n *\n * @NL80211_ATTR_CIPHERS_PAIRWISE: Used with CONNECT, ASSOCIATE, and NEW_BEACON\n *\tto indicate which unicast key ciphers will be used with the connection\n *\t(an array of u32).\n * @NL80211_ATTR_CIPHER_GROUP: Used with CONNECT, ASSOCIATE, and NEW_BEACON to\n *\tindicate which group key cipher will be used with the connection (a\n *\tu32).\n * @NL80211_ATTR_WPA_VERSIONS: Used with CONNECT, ASSOCIATE, and NEW_BEACON to\n *\tindicate which WPA version(s) the AP we want to associate with is using\n *\t(a u32 with flags from &enum nl80211_wpa_versions).\n * @NL80211_ATTR_AKM_SUITES: Used with CONNECT, ASSOCIATE, and NEW_BEACON to\n *\tindicate which key management algorithm(s) to use (an array of u32).\n *\n * @NL80211_ATTR_REQ_IE: (Re)association request information elements as\n *\tsent out by the card, for ROAM and successful CONNECT events.\n * @NL80211_ATTR_RESP_IE: (Re)association response information elements as\n *\tsent by peer, for ROAM and successful CONNECT events.\n *\n * @NL80211_ATTR_PREV_BSSID: previous BSSID, to be used in ASSOCIATE and CONNECT\n *\tcommands to specify a request to reassociate within an ESS, i.e., to use\n *\tReassociate Request frame (with the value of this attribute in the\n *\tCurrent AP address field) instead of Association Request frame which is\n *\tused for the initial association to an ESS.\n *\n * @NL80211_ATTR_KEY: key information in a nested attribute with\n *\t%NL80211_KEY_* sub-attributes\n * @NL80211_ATTR_KEYS: array of keys for static WEP keys for connect()\n *\tand join_ibss(), key information is in a nested attribute each\n *\twith %NL80211_KEY_* sub-attributes\n *\n * @NL80211_ATTR_PID: Process ID of a network namespace.\n *\n * @NL80211_ATTR_GENERATION: Used to indicate consistent snapshots for\n *\tdumps. This number increases whenever the object list being\n *\tdumped changes, and as such userspace can verify that it has\n *\tobtained a complete and consistent snapshot by verifying that\n *\tall dump messages contain the same generation number. If it\n *\tchanged then the list changed and the dump should be repeated\n *\tcompletely from scratch.\n *\n * @NL80211_ATTR_4ADDR: Use 4-address frames on a virtual interface\n *\n * @NL80211_ATTR_SURVEY_INFO: survey information about a channel, part of\n *      the survey response for %NL80211_CMD_GET_SURVEY, nested attribute\n *      containing info as possible, see &enum survey_info.\n *\n * @NL80211_ATTR_PMKID: PMK material for PMKSA caching.\n * @NL80211_ATTR_MAX_NUM_PMKIDS: maximum number of PMKIDs a firmware can\n *\tcache, a wiphy attribute.\n *\n * @NL80211_ATTR_DURATION: Duration of an operation in milliseconds, u32.\n * @NL80211_ATTR_MAX_REMAIN_ON_CHANNEL_DURATION: Device attribute that\n *\tspecifies the maximum duration that can be requested with the\n *\tremain-on-channel operation, in milliseconds, u32.\n *\n * @NL80211_ATTR_COOKIE: Generic 64-bit cookie to identify objects.\n *\n * @NL80211_ATTR_TX_RATES: Nested set of attributes\n *\t(enum nl80211_tx_rate_attributes) describing TX rates per band. The\n *\tenum nl80211_band value is used as the index (nla_type() of the nested\n *\tdata. If a band is not included, it will be configured to allow all\n *\trates based on negotiated supported rates information. This attribute\n *\tis used with %NL80211_CMD_SET_TX_BITRATE_MASK and with starting AP,\n *\tand joining mesh networks (not IBSS yet). In the later case, it must\n *\tspecify just a single bitrate, which is to be used for the beacon.\n *\tThe driver must also specify support for this with the extended\n *\tfeatures NL80211_EXT_FEATURE_BEACON_RATE_LEGACY,\n *\tNL80211_EXT_FEATURE_BEACON_RATE_HT and\n *\tNL80211_EXT_FEATURE_BEACON_RATE_VHT.\n *\n * @NL80211_ATTR_FRAME_MATCH: A binary attribute which typically must contain\n *\tat least one byte, currently used with @NL80211_CMD_REGISTER_FRAME.\n * @NL80211_ATTR_FRAME_TYPE: A u16 indicating the frame type/subtype for the\n *\t@NL80211_CMD_REGISTER_FRAME command.\n * @NL80211_ATTR_TX_FRAME_TYPES: wiphy capability attribute, which is a\n *\tnested attribute of %NL80211_ATTR_FRAME_TYPE attributes, containing\n *\tinformation about which frame types can be transmitted with\n *\t%NL80211_CMD_FRAME.\n * @NL80211_ATTR_RX_FRAME_TYPES: wiphy capability attribute, which is a\n *\tnested attribute of %NL80211_ATTR_FRAME_TYPE attributes, containing\n *\tinformation about which frame types can be registered for RX.\n *\n * @NL80211_ATTR_ACK: Flag attribute indicating that the frame was\n *\tacknowledged by the recipient.\n *\n * @NL80211_ATTR_PS_STATE: powersave state, using &enum nl80211_ps_state values.\n *\n * @NL80211_ATTR_CQM: connection quality monitor configuration in a\n *\tnested attribute with %NL80211_ATTR_CQM_* sub-attributes.\n *\n * @NL80211_ATTR_LOCAL_STATE_CHANGE: Flag attribute to indicate that a command\n *\tis requesting a local authentication/association state change without\n *\tinvoking actual management frame exchange. This can be used with\n *\tNL80211_CMD_AUTHENTICATE, NL80211_CMD_DEAUTHENTICATE,\n *\tNL80211_CMD_DISASSOCIATE.\n *\n * @NL80211_ATTR_AP_ISOLATE: (AP mode) Do not forward traffic between stations\n *\tconnected to this BSS.\n *\n * @NL80211_ATTR_WIPHY_TX_POWER_SETTING: Transmit power setting type. See\n *      &enum nl80211_tx_power_setting for possible values.\n * @NL80211_ATTR_WIPHY_TX_POWER_LEVEL: Transmit power level in signed mBm units.\n *      This is used in association with @NL80211_ATTR_WIPHY_TX_POWER_SETTING\n *      for non-automatic settings.\n *\n * @NL80211_ATTR_SUPPORT_IBSS_RSN: The device supports IBSS RSN, which mostly\n *\tmeans support for per-station GTKs.\n *\n * @NL80211_ATTR_WIPHY_ANTENNA_TX: Bitmap of allowed antennas for transmitting.\n *\tThis can be used to mask out antennas which are not attached or should\n *\tnot be used for transmitting. If an antenna is not selected in this\n *\tbitmap the hardware is not allowed to transmit on this antenna.\n *\n *\tEach bit represents one antenna, starting with antenna 1 at the first\n *\tbit. Depending on which antennas are selected in the bitmap, 802.11n\n *\tdrivers can derive which chainmasks to use (if all antennas belonging to\n *\ta particular chain are disabled this chain should be disabled) and if\n *\ta chain has diversity antennas whether diversity should be used or not.\n *\tHT capabilities (STBC, TX Beamforming, Antenna selection) can be\n *\tderived from the available chains after applying the antenna mask.\n *\tNon-802.11n drivers can derive whether to use diversity or not.\n *\tDrivers may reject configurations or RX/TX mask combinations they cannot\n *\tsupport by returning -EINVAL.\n *\n * @NL80211_ATTR_WIPHY_ANTENNA_RX: Bitmap of allowed antennas for receiving.\n *\tThis can be used to mask out antennas which are not attached or should\n *\tnot be used for receiving. If an antenna is not selected in this bitmap\n *\tthe hardware should not be configured to receive on this antenna.\n *\tFor a more detailed description see @NL80211_ATTR_WIPHY_ANTENNA_TX.\n *\n * @NL80211_ATTR_WIPHY_ANTENNA_AVAIL_TX: Bitmap of antennas which are available\n *\tfor configuration as TX antennas via the above parameters.\n *\n * @NL80211_ATTR_WIPHY_ANTENNA_AVAIL_RX: Bitmap of antennas which are available\n *\tfor configuration as RX antennas via the above parameters.\n *\n * @NL80211_ATTR_MCAST_RATE: Multicast tx rate (in 100 kbps) for IBSS\n *\n * @NL80211_ATTR_OFFCHANNEL_TX_OK: For management frame TX, the frame may be\n *\ttransmitted on another channel when the channel given doesn't match\n *\tthe current channel. If the current channel doesn't match and this\n *\tflag isn't set, the frame will be rejected. This is also used as an\n *\tnl80211 capability flag.\n *\n * @NL80211_ATTR_BSS_HT_OPMODE: HT operation mode (u16)\n *\n * @NL80211_ATTR_KEY_DEFAULT_TYPES: A nested attribute containing flags\n *\tattributes, specifying what a key should be set as default as.\n *\tSee &enum nl80211_key_default_types.\n *\n * @NL80211_ATTR_MESH_SETUP: Optional mesh setup parameters.  These cannot be\n *\tchanged once the mesh is active.\n * @NL80211_ATTR_MESH_CONFIG: Mesh configuration parameters, a nested attribute\n *\tcontaining attributes from &enum nl80211_meshconf_params.\n * @NL80211_ATTR_SUPPORT_MESH_AUTH: Currently, this means the underlying driver\n *\tallows auth frames in a mesh to be passed to userspace for processing via\n *\tthe @NL80211_MESH_SETUP_USERSPACE_AUTH flag.\n * @NL80211_ATTR_STA_PLINK_STATE: The state of a mesh peer link as defined in\n *\t&enum nl80211_plink_state. Used when userspace is driving the peer link\n *\tmanagement state machine.  @NL80211_MESH_SETUP_USERSPACE_AMPE or\n *\t@NL80211_MESH_SETUP_USERSPACE_MPM must be enabled.\n *\n * @NL80211_ATTR_WOWLAN_TRIGGERS_SUPPORTED: indicates, as part of the wiphy\n *\tcapabilities, the supported WoWLAN triggers\n * @NL80211_ATTR_WOWLAN_TRIGGERS: used by %NL80211_CMD_SET_WOWLAN to\n *\tindicate which WoW triggers should be enabled. This is also\n *\tused by %NL80211_CMD_GET_WOWLAN to get the currently enabled WoWLAN\n *\ttriggers.\n *\n * @NL80211_ATTR_SCHED_SCAN_INTERVAL: Interval between scheduled scan\n *\tcycles, in msecs.\n *\n * @NL80211_ATTR_SCHED_SCAN_MATCH: Nested attribute with one or more\n *\tsets of attributes to match during scheduled scans.  Only BSSs\n *\tthat match any of the sets will be reported.  These are\n *\tpass-thru filter rules.\n *\tFor a match to succeed, the BSS must match all attributes of a\n *\tset.  Since not every hardware supports matching all types of\n *\tattributes, there is no guarantee that the reported BSSs are\n *\tfully complying with the match sets and userspace needs to be\n *\table to ignore them by itself.\n *\tThus, the implementation is somewhat hardware-dependent, but\n *\tthis is only an optimization and the userspace application\n *\tneeds to handle all the non-filtered results anyway.\n *\tIf the match attributes don't make sense when combined with\n *\tthe values passed in @NL80211_ATTR_SCAN_SSIDS (eg. if an SSID\n *\tis included in the probe request, but the match attributes\n *\twill never let it go through), -EINVAL may be returned.\n *\tIf omitted, no filtering is done.\n *\n * @NL80211_ATTR_INTERFACE_COMBINATIONS: Nested attribute listing the supported\n *\tinterface combinations. In each nested item, it contains attributes\n *\tdefined in &enum nl80211_if_combination_attrs.\n * @NL80211_ATTR_SOFTWARE_IFTYPES: Nested attribute (just like\n *\t%NL80211_ATTR_SUPPORTED_IFTYPES) containing the interface types that\n *\tare managed in software: interfaces of these types aren't subject to\n *\tany restrictions in their number or combinations.\n *\n * @NL80211_ATTR_REKEY_DATA: nested attribute containing the information\n *\tnecessary for GTK rekeying in the device, see &enum nl80211_rekey_data.\n *\n * @NL80211_ATTR_SCAN_SUPP_RATES: rates per to be advertised as supported in scan,\n *\tnested array attribute containing an entry for each band, with the entry\n *\tbeing a list of supported rates as defined by IEEE 802.11 7.3.2.2 but\n *\twithout the length restriction (at most %NL80211_MAX_SUPP_RATES).\n *\n * @NL80211_ATTR_HIDDEN_SSID: indicates whether SSID is to be hidden from Beacon\n *\tand Probe Response (when response to wildcard Probe Request); see\n *\t&enum nl80211_hidden_ssid, represented as a u32\n *\n * @NL80211_ATTR_IE_PROBE_RESP: Information element(s) for Probe Response frame.\n *\tThis is used with %NL80211_CMD_NEW_BEACON and %NL80211_CMD_SET_BEACON to\n *\tprovide extra IEs (e.g., WPS/P2P IE) into Probe Response frames when the\n *\tdriver (or firmware) replies to Probe Request frames.\n * @NL80211_ATTR_IE_ASSOC_RESP: Information element(s) for (Re)Association\n *\tResponse frames. This is used with %NL80211_CMD_NEW_BEACON and\n *\t%NL80211_CMD_SET_BEACON to provide extra IEs (e.g., WPS/P2P IE) into\n *\t(Re)Association Response frames when the driver (or firmware) replies to\n *\t(Re)Association Request frames.\n *\n * @NL80211_ATTR_STA_WME: Nested attribute containing the wme configuration\n *\tof the station, see &enum nl80211_sta_wme_attr.\n * @NL80211_ATTR_SUPPORT_AP_UAPSD: the device supports uapsd when working\n *\tas AP.\n *\n * @NL80211_ATTR_ROAM_SUPPORT: Indicates whether the firmware is capable of\n *\troaming to another AP in the same ESS if the signal lever is low.\n *\n * @NL80211_ATTR_PMKSA_CANDIDATE: Nested attribute containing the PMKSA caching\n *\tcandidate information, see &enum nl80211_pmksa_candidate_attr.\n *\n * @NL80211_ATTR_TX_NO_CCK_RATE: Indicates whether to use CCK rate or not\n *\tfor management frames transmission. In order to avoid p2p probe/action\n *\tframes are being transmitted at CCK rate in 2GHz band, the user space\n *\tapplications use this attribute.\n *\tThis attribute is used with %NL80211_CMD_TRIGGER_SCAN and\n *\t%NL80211_CMD_FRAME commands.\n *\n * @NL80211_ATTR_TDLS_ACTION: Low level TDLS action code (e.g. link setup\n *\trequest, link setup confirm, link teardown, etc.). Values are\n *\tdescribed in the TDLS (802.11z) specification.\n * @NL80211_ATTR_TDLS_DIALOG_TOKEN: Non-zero token for uniquely identifying a\n *\tTDLS conversation between two devices.\n * @NL80211_ATTR_TDLS_OPERATION: High level TDLS operation; see\n *\t&enum nl80211_tdls_operation, represented as a u8.\n * @NL80211_ATTR_TDLS_SUPPORT: A flag indicating the device can operate\n *\tas a TDLS peer sta.\n * @NL80211_ATTR_TDLS_EXTERNAL_SETUP: The TDLS discovery/setup and teardown\n *\tprocedures should be performed by sending TDLS packets via\n *\t%NL80211_CMD_TDLS_MGMT. Otherwise %NL80211_CMD_TDLS_OPER should be\n *\tused for asking the driver to perform a TDLS operation.\n *\n * @NL80211_ATTR_DEVICE_AP_SME: This u32 attribute may be listed for devices\n *\tthat have AP support to indicate that they have the AP SME integrated\n *\twith support for the features listed in this attribute, see\n *\t&enum nl80211_ap_sme_features.\n *\n * @NL80211_ATTR_DONT_WAIT_FOR_ACK: Used with %NL80211_CMD_FRAME, this tells\n *\tthe driver to not wait for an acknowledgement. Note that due to this,\n *\tit will also not give a status callback nor return a cookie. This is\n *\tmostly useful for probe responses to save airtime.\n *\n * @NL80211_ATTR_FEATURE_FLAGS: This u32 attribute contains flags from\n *\t&enum nl80211_feature_flags and is advertised in wiphy information.\n * @NL80211_ATTR_PROBE_RESP_OFFLOAD: Indicates that the HW responds to probe\n *\trequests while operating in AP-mode.\n *\tThis attribute holds a bitmap of the supported protocols for\n *\toffloading (see &enum nl80211_probe_resp_offload_support_attr).\n *\n * @NL80211_ATTR_PROBE_RESP: Probe Response template data. Contains the entire\n *\tprobe-response frame. The DA field in the 802.11 header is zero-ed out,\n *\tto be filled by the FW.\n * @NL80211_ATTR_DISABLE_HT:  Force HT capable interfaces to disable\n *      this feature.  Currently, only supported in mac80211 drivers.\n * @NL80211_ATTR_HT_CAPABILITY_MASK: Specify which bits of the\n *      ATTR_HT_CAPABILITY to which attention should be paid.\n *      Currently, only mac80211 NICs support this feature.\n *      The values that may be configured are:\n *       MCS rates, MAX-AMSDU, HT-20-40 and HT_CAP_SGI_40\n *       AMPDU density and AMPDU factor.\n *      All values are treated as suggestions and may be ignored\n *      by the driver as required.  The actual values may be seen in\n *      the station debugfs ht_caps file.\n *\n * @NL80211_ATTR_DFS_REGION: region for regulatory rules which this country\n *    abides to when initiating radiation on DFS channels. A country maps\n *    to one DFS region.\n *\n * @NL80211_ATTR_NOACK_MAP: This u16 bitmap contains the No Ack Policy of\n *      up to 16 TIDs.\n *\n * @NL80211_ATTR_INACTIVITY_TIMEOUT: timeout value in seconds, this can be\n *\tused by the drivers which has MLME in firmware and does not have support\n *\tto report per station tx/rx activity to free up the station entry from\n *\tthe list. This needs to be used when the driver advertises the\n *\tcapability to timeout the stations.\n *\n * @NL80211_ATTR_RX_SIGNAL_DBM: signal strength in dBm (as a 32-bit int);\n *\tthis attribute is (depending on the driver capabilities) added to\n *\treceived frames indicated with %NL80211_CMD_FRAME.\n *\n * @NL80211_ATTR_BG_SCAN_PERIOD: Background scan period in seconds\n *      or 0 to disable background scan.\n *\n * @NL80211_ATTR_USER_REG_HINT_TYPE: type of regulatory hint passed from\n *\tuserspace. If unset it is assumed the hint comes directly from\n *\ta user. If set code could specify exactly what type of source\n *\twas used to provide the hint. For the different types of\n *\tallowed user regulatory hints see nl80211_user_reg_hint_type.\n *\n * @NL80211_ATTR_CONN_FAILED_REASON: The reason for which AP has rejected\n *\tthe connection request from a station. nl80211_connect_failed_reason\n *\tenum has different reasons of connection failure.\n *\n * @NL80211_ATTR_AUTH_DATA: Fields and elements in Authentication frames.\n *\tThis contains the authentication frame body (non-IE and IE data),\n *\texcluding the Authentication algorithm number, i.e., starting at the\n *\tAuthentication transaction sequence number field. It is used with\n *\tauthentication algorithms that need special fields to be added into\n *\tthe frames (SAE and FILS). Currently, only the SAE cases use the\n *\tinitial two fields (Authentication transaction sequence number and\n *\tStatus code). However, those fields are included in the attribute data\n *\tfor all authentication algorithms to keep the attribute definition\n *\tconsistent.\n *\n * @NL80211_ATTR_VHT_CAPABILITY: VHT Capability information element (from\n *\tassociation request when used with NL80211_CMD_NEW_STATION)\n *\n * @NL80211_ATTR_SCAN_FLAGS: scan request control flags (u32)\n *\n * @NL80211_ATTR_P2P_CTWINDOW: P2P GO Client Traffic Window (u8), used with\n *\tthe START_AP and SET_BSS commands\n * @NL80211_ATTR_P2P_OPPPS: P2P GO opportunistic PS (u8), used with the\n *\tSTART_AP and SET_BSS commands. This can have the values 0 or 1;\n *\tif not given in START_AP 0 is assumed, if not given in SET_BSS\n *\tno change is made.\n *\n * @NL80211_ATTR_LOCAL_MESH_POWER_MODE: local mesh STA link-specific power mode\n *\tdefined in &enum nl80211_mesh_power_mode.\n *\n * @NL80211_ATTR_ACL_POLICY: ACL policy, see &enum nl80211_acl_policy,\n *\tcarried in a u32 attribute\n *\n * @NL80211_ATTR_MAC_ADDRS: Array of nested MAC addresses, used for\n *\tMAC ACL.\n *\n * @NL80211_ATTR_MAC_ACL_MAX: u32 attribute to advertise the maximum\n *\tnumber of MAC addresses that a device can support for MAC\n *\tACL.\n *\n * @NL80211_ATTR_RADAR_EVENT: Type of radar event for notification to userspace,\n *\tcontains a value of enum nl80211_radar_event (u32).\n *\n * @NL80211_ATTR_EXT_CAPA: 802.11 extended capabilities that the kernel driver\n *\thas and handles. The format is the same as the IE contents. See\n *\t802.11-2012 8.4.2.29 for more information.\n * @NL80211_ATTR_EXT_CAPA_MASK: Extended capabilities that the kernel driver\n *\thas set in the %NL80211_ATTR_EXT_CAPA value, for multibit fields.\n *\n * @NL80211_ATTR_STA_CAPABILITY: Station capabilities (u16) are advertised to\n *\tthe driver, e.g., to enable TDLS power save (PU-APSD).\n *\n * @NL80211_ATTR_STA_EXT_CAPABILITY: Station extended capabilities are\n *\tadvertised to the driver, e.g., to enable TDLS off channel operations\n *\tand PU-APSD.\n *\n * @NL80211_ATTR_PROTOCOL_FEATURES: global nl80211 feature flags, see\n *\t&enum nl80211_protocol_features, the attribute is a u32.\n *\n * @NL80211_ATTR_SPLIT_WIPHY_DUMP: flag attribute, userspace supports\n *\treceiving the data for a single wiphy split across multiple\n *\tmessages, given with wiphy dump message\n *\n * @NL80211_ATTR_MDID: Mobility Domain Identifier\n *\n * @NL80211_ATTR_IE_RIC: Resource Information Container Information\n *\tElement\n *\n * @NL80211_ATTR_CRIT_PROT_ID: critical protocol identifier requiring increased\n *\treliability, see &enum nl80211_crit_proto_id (u16).\n * @NL80211_ATTR_MAX_CRIT_PROT_DURATION: duration in milliseconds in which\n *      the connection should have increased reliability (u16).\n *\n * @NL80211_ATTR_PEER_AID: Association ID for the peer TDLS station (u16).\n *\tThis is similar to @NL80211_ATTR_STA_AID but with a difference of being\n *\tallowed to be used with the first @NL80211_CMD_SET_STATION command to\n *\tupdate a TDLS peer STA entry.\n *\n * @NL80211_ATTR_COALESCE_RULE: Coalesce rule information.\n *\n * @NL80211_ATTR_CH_SWITCH_COUNT: u32 attribute specifying the number of TBTT's\n *\tuntil the channel switch event.\n * @NL80211_ATTR_CH_SWITCH_BLOCK_TX: flag attribute specifying that transmission\n *\tmust be blocked on the current channel (before the channel switch\n *\toperation).\n * @NL80211_ATTR_CSA_IES: Nested set of attributes containing the IE information\n *\tfor the time while performing a channel switch.\n * @NL80211_ATTR_CSA_C_OFF_BEACON: An array of offsets (u16) to the channel\n *\tswitch counters in the beacons tail (%NL80211_ATTR_BEACON_TAIL).\n * @NL80211_ATTR_CSA_C_OFF_PRESP: An array of offsets (u16) to the channel\n *\tswitch counters in the probe response (%NL80211_ATTR_PROBE_RESP).\n *\n * @NL80211_ATTR_RXMGMT_FLAGS: flags for nl80211_send_mgmt(), u32.\n *\tAs specified in the &enum nl80211_rxmgmt_flags.\n *\n * @NL80211_ATTR_STA_SUPPORTED_CHANNELS: array of supported channels.\n *\n * @NL80211_ATTR_STA_SUPPORTED_OPER_CLASSES: array of supported\n *      supported operating classes.\n *\n * @NL80211_ATTR_HANDLE_DFS: A flag indicating whether user space\n *\tcontrols DFS operation in IBSS mode. If the flag is included in\n *\t%NL80211_CMD_JOIN_IBSS request, the driver will allow use of DFS\n *\tchannels and reports radar events to userspace. Userspace is required\n *\tto react to radar events, e.g. initiate a channel switch or leave the\n *\tIBSS network.\n *\n * @NL80211_ATTR_SUPPORT_5_MHZ: A flag indicating that the device supports\n *\t5 MHz channel bandwidth.\n * @NL80211_ATTR_SUPPORT_10_MHZ: A flag indicating that the device supports\n *\t10 MHz channel bandwidth.\n *\n * @NL80211_ATTR_OPMODE_NOTIF: Operating mode field from Operating Mode\n *\tNotification Element based on association request when used with\n *\t%NL80211_CMD_NEW_STATION or %NL80211_CMD_SET_STATION (only when\n *\t%NL80211_FEATURE_FULL_AP_CLIENT_STATE is supported, or with TDLS);\n *\tu8 attribute.\n *\n * @NL80211_ATTR_VENDOR_ID: The vendor ID, either a 24-bit OUI or, if\n *\t%NL80211_VENDOR_ID_IS_LINUX is set, a special Linux ID (not used yet)\n * @NL80211_ATTR_VENDOR_SUBCMD: vendor sub-command\n * @NL80211_ATTR_VENDOR_DATA: data for the vendor command, if any; this\n *\tattribute is also used for vendor command feature advertisement\n * @NL80211_ATTR_VENDOR_EVENTS: used for event list advertising in the wiphy\n *\tinfo, containing a nested array of possible events\n *\n * @NL80211_ATTR_QOS_MAP: IP DSCP mapping for Interworking QoS mapping. This\n *\tdata is in the format defined for the payload of the QoS Map Set element\n *\tin IEEE Std 802.11-2012, 8.4.2.97.\n *\n * @NL80211_ATTR_MAC_HINT: MAC address recommendation as initial BSS\n * @NL80211_ATTR_WIPHY_FREQ_HINT: frequency of the recommended initial BSS\n *\n * @NL80211_ATTR_MAX_AP_ASSOC_STA: Device attribute that indicates how many\n *\tassociated stations are supported in AP mode (including P2P GO); u32.\n *\tSince drivers may not have a fixed limit on the maximum number (e.g.,\n *\tother concurrent operations may affect this), drivers are allowed to\n *\tadvertise values that cannot always be met. In such cases, an attempt\n *\tto add a new station entry with @NL80211_CMD_NEW_STATION may fail.\n *\n * @NL80211_ATTR_CSA_C_OFFSETS_TX: An array of csa counter offsets (u16) which\n *\tshould be updated when the frame is transmitted.\n * @NL80211_ATTR_MAX_CSA_COUNTERS: U8 attribute used to advertise the maximum\n *\tsupported number of csa counters.\n *\n * @NL80211_ATTR_TDLS_PEER_CAPABILITY: flags for TDLS peer capabilities, u32.\n *\tAs specified in the &enum nl80211_tdls_peer_capability.\n *\n * @NL80211_ATTR_SOCKET_OWNER: Flag attribute, if set during interface\n *\tcreation then the new interface will be owned by the netlink socket\n *\tthat created it and will be destroyed when the socket is closed.\n *\tIf set during scheduled scan start then the new scan req will be\n *\towned by the netlink socket that created it and the scheduled scan will\n *\tbe stopped when the socket is closed.\n *\tIf set during configuration of regulatory indoor operation then the\n *\tregulatory indoor configuration would be owned by the netlink socket\n *\tthat configured the indoor setting, and the indoor operation would be\n *\tcleared when the socket is closed.\n *\tIf set during NAN interface creation, the interface will be destroyed\n *\tif the socket is closed just like any other interface. Moreover, NAN\n *\tnotifications will be sent in unicast to that socket. Without this\n *\tattribute, the notifications will be sent to the %NL80211_MCGRP_NAN\n *\tmulticast group.\n *\tIf set during %NL80211_CMD_ASSOCIATE or %NL80211_CMD_CONNECT the\n *\tstation will deauthenticate when the socket is closed.\n *\n * @NL80211_ATTR_TDLS_INITIATOR: flag attribute indicating the current end is\n *\tthe TDLS link initiator.\n *\n * @NL80211_ATTR_USE_RRM: flag for indicating whether the current connection\n *\tshall support Radio Resource Measurements (11k). This attribute can be\n *\tused with %NL80211_CMD_ASSOCIATE and %NL80211_CMD_CONNECT requests.\n *\tUser space applications are expected to use this flag only if the\n *\tunderlying device supports these minimal RRM features:\n *\t\t%NL80211_FEATURE_DS_PARAM_SET_IE_IN_PROBES,\n *\t\t%NL80211_FEATURE_QUIET,\n *\tOr, if global RRM is supported, see:\n *\t\t%NL80211_EXT_FEATURE_RRM\n *\tIf this flag is used, driver must add the Power Capabilities IE to the\n *\tassociation request. In addition, it must also set the RRM capability\n *\tflag in the association request's Capability Info field.\n *\n * @NL80211_ATTR_WIPHY_DYN_ACK: flag attribute used to enable ACK timeout\n *\testimation algorithm (dynack). In order to activate dynack\n *\t%NL80211_FEATURE_ACKTO_ESTIMATION feature flag must be set by lower\n *\tdrivers to indicate dynack capability. Dynack is automatically disabled\n *\tsetting valid value for coverage class.\n *\n * @NL80211_ATTR_TSID: a TSID value (u8 attribute)\n * @NL80211_ATTR_USER_PRIO: user priority value (u8 attribute)\n * @NL80211_ATTR_ADMITTED_TIME: admitted time in units of 32 microseconds\n *\t(per second) (u16 attribute)\n *\n * @NL80211_ATTR_SMPS_MODE: SMPS mode to use (ap mode). see\n *\t&enum nl80211_smps_mode.\n *\n * @NL80211_ATTR_OPER_CLASS: operating class\n *\n * @NL80211_ATTR_MAC_MASK: MAC address mask\n *\n * @NL80211_ATTR_WIPHY_SELF_MANAGED_REG: flag attribute indicating this device\n *\tis self-managing its regulatory information and any regulatory domain\n *\tobtained from it is coming from the device's wiphy and not the global\n *\tcfg80211 regdomain.\n *\n * @NL80211_ATTR_EXT_FEATURES: extended feature flags contained in a byte\n *\tarray. The feature flags are identified by their bit index (see &enum\n *\tnl80211_ext_feature_index). The bit index is ordered starting at the\n *\tleast-significant bit of the first byte in the array, ie. bit index 0\n *\tis located at bit 0 of byte 0. bit index 25 would be located at bit 1\n *\tof byte 3 (u8 array).\n *\n * @NL80211_ATTR_SURVEY_RADIO_STATS: Request overall radio statistics to be\n *\treturned along with other survey data. If set, @NL80211_CMD_GET_SURVEY\n *\tmay return a survey entry without a channel indicating global radio\n *\tstatistics (only some values are valid and make sense.)\n *\tFor devices that don't return such an entry even then, the information\n *\tshould be contained in the result as the sum of the respective counters\n *\tover all channels.\n *\n * @NL80211_ATTR_SCHED_SCAN_DELAY: delay before the first cycle of a\n *\tscheduled scan is started.  Or the delay before a WoWLAN\n *\tnet-detect scan is started, counting from the moment the\n *\tsystem is suspended.  This value is a u32, in seconds.\n\n * @NL80211_ATTR_REG_INDOOR: flag attribute, if set indicates that the device\n *      is operating in an indoor environment.\n *\n * @NL80211_ATTR_MAX_NUM_SCHED_SCAN_PLANS: maximum number of scan plans for\n *\tscheduled scan supported by the device (u32), a wiphy attribute.\n * @NL80211_ATTR_MAX_SCAN_PLAN_INTERVAL: maximum interval (in seconds) for\n *\ta scan plan (u32), a wiphy attribute.\n * @NL80211_ATTR_MAX_SCAN_PLAN_ITERATIONS: maximum number of iterations in\n *\ta scan plan (u32), a wiphy attribute.\n * @NL80211_ATTR_SCHED_SCAN_PLANS: a list of scan plans for scheduled scan.\n *\tEach scan plan defines the number of scan iterations and the interval\n *\tbetween scans. The last scan plan will always run infinitely,\n *\tthus it must not specify the number of iterations, only the interval\n *\tbetween scans. The scan plans are executed sequentially.\n *\tEach scan plan is a nested attribute of &enum nl80211_sched_scan_plan.\n * @NL80211_ATTR_PBSS: flag attribute. If set it means operate\n *\tin a PBSS. Specified in %NL80211_CMD_CONNECT to request\n *\tconnecting to a PCP, and in %NL80211_CMD_START_AP to start\n *\ta PCP instead of AP. Relevant for DMG networks only.\n * @NL80211_ATTR_BSS_SELECT: nested attribute for driver supporting the\n *\tBSS selection feature. When used with %NL80211_CMD_GET_WIPHY it contains\n *\tattributes according &enum nl80211_bss_select_attr to indicate what\n *\tBSS selection behaviours are supported. When used with %NL80211_CMD_CONNECT\n *\tit contains the behaviour-specific attribute containing the parameters for\n *\tBSS selection to be done by driver and/or firmware.\n *\n * @NL80211_ATTR_STA_SUPPORT_P2P_PS: whether P2P PS mechanism supported\n *\tor not. u8, one of the values of &enum nl80211_sta_p2p_ps_status\n *\n * @NL80211_ATTR_PAD: attribute used for padding for 64-bit alignment\n *\n * @NL80211_ATTR_IFTYPE_EXT_CAPA: Nested attribute of the following attributes:\n *\t%NL80211_ATTR_IFTYPE, %NL80211_ATTR_EXT_CAPA,\n *\t%NL80211_ATTR_EXT_CAPA_MASK, to specify the extended capabilities per\n *\tinterface type.\n *\n * @NL80211_ATTR_MU_MIMO_GROUP_DATA: array of 24 bytes that defines a MU-MIMO\n *\tgroupID for monitor mode.\n *\tThe first 8 bytes are a mask that defines the membership in each\n *\tgroup (there are 64 groups, group 0 and 63 are reserved),\n *\teach bit represents a group and set to 1 for being a member in\n *\tthat group and 0 for not being a member.\n *\tThe remaining 16 bytes define the position in each group: 2 bits for\n *\teach group.\n *\t(smaller group numbers represented on most significant bits and bigger\n *\tgroup numbers on least significant bits.)\n *\tThis attribute is used only if all interfaces are in monitor mode.\n *\tSet this attribute in order to monitor packets using the given MU-MIMO\n *\tgroupID data.\n *\tto turn off that feature set all the bits of the groupID to zero.\n * @NL80211_ATTR_MU_MIMO_FOLLOW_MAC_ADDR: mac address for the sniffer to follow\n *\twhen using MU-MIMO air sniffer.\n *\tto turn that feature off set an invalid mac address\n *\t(e.g. FF:FF:FF:FF:FF:FF)\n *\n * @NL80211_ATTR_SCAN_START_TIME_TSF: The time at which the scan was actually\n *\tstarted (u64). The time is the TSF of the BSS the interface that\n *\trequested the scan is connected to (if available, otherwise this\n *\tattribute must not be included).\n * @NL80211_ATTR_SCAN_START_TIME_TSF_BSSID: The BSS according to which\n *\t%NL80211_ATTR_SCAN_START_TIME_TSF is set.\n * @NL80211_ATTR_MEASUREMENT_DURATION: measurement duration in TUs (u16). If\n *\t%NL80211_ATTR_MEASUREMENT_DURATION_MANDATORY is not set, this is the\n *\tmaximum measurement duration allowed. This attribute is used with\n *\tmeasurement requests. It can also be used with %NL80211_CMD_TRIGGER_SCAN\n *\tif the scan is used for beacon report radio measurement.\n * @NL80211_ATTR_MEASUREMENT_DURATION_MANDATORY: flag attribute that indicates\n *\tthat the duration specified with %NL80211_ATTR_MEASUREMENT_DURATION is\n *\tmandatory. If this flag is not set, the duration is the maximum duration\n *\tand the actual measurement duration may be shorter.\n *\n * @NL80211_ATTR_MESH_PEER_AID: Association ID for the mesh peer (u16). This is\n *\tused to pull the stored data for mesh peer in power save state.\n *\n * @NL80211_ATTR_NAN_MASTER_PREF: the master preference to be used by\n *\t%NL80211_CMD_START_NAN and optionally with\n *\t%NL80211_CMD_CHANGE_NAN_CONFIG. Its type is u8 and it can't be 0.\n *\tAlso, values 1 and 255 are reserved for certification purposes and\n *\tshould not be used during a normal device operation.\n * @NL80211_ATTR_BANDS: operating bands configuration.  This is a u32\n *\tbitmask of BIT(NL80211_BAND_*) as described in %enum\n *\tnl80211_band.  For instance, for NL80211_BAND_2GHZ, bit 0\n *\twould be set.  This attribute is used with\n *\t%NL80211_CMD_START_NAN and %NL80211_CMD_CHANGE_NAN_CONFIG, and\n *\tit is optional.  If no bands are set, it means don't-care and\n *\tthe device will decide what to use.\n * @NL80211_ATTR_NAN_FUNC: a function that can be added to NAN. See\n *\t&enum nl80211_nan_func_attributes for description of this nested\n *\tattribute.\n * @NL80211_ATTR_NAN_MATCH: used to report a match. This is a nested attribute.\n *\tSee &enum nl80211_nan_match_attributes.\n * @NL80211_ATTR_FILS_KEK: KEK for FILS (Re)Association Request/Response frame\n *\tprotection.\n * @NL80211_ATTR_FILS_NONCES: Nonces (part of AAD) for FILS (Re)Association\n *\tRequest/Response frame protection. This attribute contains the 16 octet\n *\tSTA Nonce followed by 16 octets of AP Nonce.\n *\n * @NL80211_ATTR_MULTICAST_TO_UNICAST_ENABLED: Indicates whether or not multicast\n *\tpackets should be send out as unicast to all stations (flag attribute).\n *\n * @NL80211_ATTR_BSSID: The BSSID of the AP. Note that %NL80211_ATTR_MAC is also\n *\tused in various commands/events for specifying the BSSID.\n *\n * @NL80211_ATTR_SCHED_SCAN_RELATIVE_RSSI: Relative RSSI threshold by which\n *\tother BSSs has to be better or slightly worse than the current\n *\tconnected BSS so that they get reported to user space.\n *\tThis will give an opportunity to userspace to consider connecting to\n *\tother matching BSSs which have better or slightly worse RSSI than\n *\tthe current connected BSS by using an offloaded operation to avoid\n *\tunnecessary wakeups.\n *\n * @NL80211_ATTR_SCHED_SCAN_RSSI_ADJUST: When present the RSSI level for BSSs in\n *\tthe specified band is to be adjusted before doing\n *\t%NL80211_ATTR_SCHED_SCAN_RELATIVE_RSSI based comparison to figure out\n *\tbetter BSSs. The attribute value is a packed structure\n *\tvalue as specified by &struct nl80211_bss_select_rssi_adjust.\n *\n * @NL80211_ATTR_TIMEOUT_REASON: The reason for which an operation timed out.\n *\tu32 attribute with an &enum nl80211_timeout_reason value. This is used,\n *\te.g., with %NL80211_CMD_CONNECT event.\n *\n * @NL80211_ATTR_FILS_ERP_USERNAME: EAP Re-authentication Protocol (ERP)\n *\tusername part of NAI used to refer keys rRK and rIK. This is used with\n *\t%NL80211_CMD_CONNECT.\n *\n * @NL80211_ATTR_FILS_ERP_REALM: EAP Re-authentication Protocol (ERP) realm part\n *\tof NAI specifying the domain name of the ER server. This is used with\n *\t%NL80211_CMD_CONNECT.\n *\n * @NL80211_ATTR_FILS_ERP_NEXT_SEQ_NUM: Unsigned 16-bit ERP next sequence number\n *\tto use in ERP messages. This is used in generating the FILS wrapped data\n *\tfor FILS authentication and is used with %NL80211_CMD_CONNECT.\n *\n * @NL80211_ATTR_FILS_ERP_RRK: ERP re-authentication Root Key (rRK) for the\n *\tNAI specified by %NL80211_ATTR_FILS_ERP_USERNAME and\n *\t%NL80211_ATTR_FILS_ERP_REALM. This is used for generating rIK and rMSK\n *\tfrom successful FILS authentication and is used with\n *\t%NL80211_CMD_CONNECT.\n *\n * @NL80211_ATTR_FILS_CACHE_ID: A 2-octet identifier advertized by a FILS AP\n *\tidentifying the scope of PMKSAs. This is used with\n *\t@NL80211_CMD_SET_PMKSA and @NL80211_CMD_DEL_PMKSA.\n *\n * @NL80211_ATTR_PMK: attribute for passing PMK key material. Used with\n *\t%NL80211_CMD_SET_PMKSA for the PMKSA identified by %NL80211_ATTR_PMKID.\n *\tFor %NL80211_CMD_CONNECT it is used to provide PSK for offloading 4-way\n *\thandshake for WPA/WPA2-PSK networks. For 802.1X authentication it is\n *\tused with %NL80211_CMD_SET_PMK. For offloaded FT support this attribute\n *\tspecifies the PMK-R0 if NL80211_ATTR_PMKR0_NAME is included as well.\n *\n * @NL80211_ATTR_SCHED_SCAN_MULTI: flag attribute which user-space shall use to\n *\tindicate that it supports multiple active scheduled scan requests.\n * @NL80211_ATTR_SCHED_SCAN_MAX_REQS: indicates maximum number of scheduled\n *\tscan request that may be active for the device (u32).\n *\n * @NL80211_ATTR_WANT_1X_4WAY_HS: flag attribute which user-space can include\n *\tin %NL80211_CMD_CONNECT to indicate that for 802.1X authentication it\n *\twants to use the supported offload of the 4-way handshake.\n * @NL80211_ATTR_PMKR0_NAME: PMK-R0 Name for offloaded FT.\n * @NL80211_ATTR_PORT_AUTHORIZED: flag attribute used in %NL80211_CMD_ROAMED\n *\tnotification indicating that that 802.1X authentication was done by\n *\tthe driver or is not needed (because roaming used the Fast Transition\n *\tprotocol).\n *\n * @NUM_NL80211_ATTR: total number of nl80211_attrs available\n * @NL80211_ATTR_MAX: highest attribute number currently defined\n * @__NL80211_ATTR_AFTER_LAST: internal use\n */\nenum nl80211_attrs {\n/* don't change the order or add anything between, this is ABI! */\n\tNL80211_ATTR_UNSPEC,\n\n\tNL80211_ATTR_WIPHY,\n\tNL80211_ATTR_WIPHY_NAME,\n\n\tNL80211_ATTR_IFINDEX,\n\tNL80211_ATTR_IFNAME,\n\tNL80211_ATTR_IFTYPE,\n\n\tNL80211_ATTR_MAC,\n\n\tNL80211_ATTR_KEY_DATA,\n\tNL80211_ATTR_KEY_IDX,\n\tNL80211_ATTR_KEY_CIPHER,\n\tNL80211_ATTR_KEY_SEQ,\n\tNL80211_ATTR_KEY_DEFAULT,\n\n\tNL80211_ATTR_BEACON_INTERVAL,\n\tNL80211_ATTR_DTIM_PERIOD,\n\tNL80211_ATTR_BEACON_HEAD,\n\tNL80211_ATTR_BEACON_TAIL,\n\n\tNL80211_ATTR_STA_AID,\n\tNL80211_ATTR_STA_FLAGS,\n\tNL80211_ATTR_STA_LISTEN_INTERVAL,\n\tNL80211_ATTR_STA_SUPPORTED_RATES,\n\tNL80211_ATTR_STA_VLAN,\n\tNL80211_ATTR_STA_INFO,\n\n\tNL80211_ATTR_WIPHY_BANDS,\n\n\tNL80211_ATTR_MNTR_FLAGS,\n\n\tNL80211_ATTR_MESH_ID,\n\tNL80211_ATTR_STA_PLINK_ACTION,\n\tNL80211_ATTR_MPATH_NEXT_HOP,\n\tNL80211_ATTR_MPATH_INFO,\n\n\tNL80211_ATTR_BSS_CTS_PROT,\n\tNL80211_ATTR_BSS_SHORT_PREAMBLE,\n\tNL80211_ATTR_BSS_SHORT_SLOT_TIME,\n\n\tNL80211_ATTR_HT_CAPABILITY,\n\n\tNL80211_ATTR_SUPPORTED_IFTYPES,\n\n\tNL80211_ATTR_REG_ALPHA2,\n\tNL80211_ATTR_REG_RULES,\n\n\tNL80211_ATTR_MESH_CONFIG,\n\n\tNL80211_ATTR_BSS_BASIC_RATES,\n\n\tNL80211_ATTR_WIPHY_TXQ_PARAMS,\n\tNL80211_ATTR_WIPHY_FREQ,\n\tNL80211_ATTR_WIPHY_CHANNEL_TYPE,\n\n\tNL80211_ATTR_KEY_DEFAULT_MGMT,\n\n\tNL80211_ATTR_MGMT_SUBTYPE,\n\tNL80211_ATTR_IE,\n\n\tNL80211_ATTR_MAX_NUM_SCAN_SSIDS,\n\n\tNL80211_ATTR_SCAN_FREQUENCIES,\n\tNL80211_ATTR_SCAN_SSIDS,\n\tNL80211_ATTR_GENERATION, /* replaces old SCAN_GENERATION */\n\tNL80211_ATTR_BSS,\n\n\tNL80211_ATTR_REG_INITIATOR,\n\tNL80211_ATTR_REG_TYPE,\n\n\tNL80211_ATTR_SUPPORTED_COMMANDS,\n\n\tNL80211_ATTR_FRAME,\n\tNL80211_ATTR_SSID,\n\tNL80211_ATTR_AUTH_TYPE,\n\tNL80211_ATTR_REASON_CODE,\n\n\tNL80211_ATTR_KEY_TYPE,\n\n\tNL80211_ATTR_MAX_SCAN_IE_LEN,\n\tNL80211_ATTR_CIPHER_SUITES,\n\n\tNL80211_ATTR_FREQ_BEFORE,\n\tNL80211_ATTR_FREQ_AFTER,\n\n\tNL80211_ATTR_FREQ_FIXED,\n\n\n\tNL80211_ATTR_WIPHY_RETRY_SHORT,\n\tNL80211_ATTR_WIPHY_RETRY_LONG,\n\tNL80211_ATTR_WIPHY_FRAG_THRESHOLD,\n\tNL80211_ATTR_WIPHY_RTS_THRESHOLD,\n\n\tNL80211_ATTR_TIMED_OUT,\n\n\tNL80211_ATTR_USE_MFP,\n\n\tNL80211_ATTR_STA_FLAGS2,\n\n\tNL80211_ATTR_CONTROL_PORT,\n\n\tNL80211_ATTR_TESTDATA,\n\n\tNL80211_ATTR_PRIVACY,\n\n\tNL80211_ATTR_DISCONNECTED_BY_AP,\n\tNL80211_ATTR_STATUS_CODE,\n\n\tNL80211_ATTR_CIPHER_SUITES_PAIRWISE,\n\tNL80211_ATTR_CIPHER_SUITE_GROUP,\n\tNL80211_ATTR_WPA_VERSIONS,\n\tNL80211_ATTR_AKM_SUITES,\n\n\tNL80211_ATTR_REQ_IE,\n\tNL80211_ATTR_RESP_IE,\n\n\tNL80211_ATTR_PREV_BSSID,\n\n\tNL80211_ATTR_KEY,\n\tNL80211_ATTR_KEYS,\n\n\tNL80211_ATTR_PID,\n\n\tNL80211_ATTR_4ADDR,\n\n\tNL80211_ATTR_SURVEY_INFO,\n\n\tNL80211_ATTR_PMKID,\n\tNL80211_ATTR_MAX_NUM_PMKIDS,\n\n\tNL80211_ATTR_DURATION,\n\n\tNL80211_ATTR_COOKIE,\n\n\tNL80211_ATTR_WIPHY_COVERAGE_CLASS,\n\n\tNL80211_ATTR_TX_RATES,\n\n\tNL80211_ATTR_FRAME_MATCH,\n\n\tNL80211_ATTR_ACK,\n\n\tNL80211_ATTR_PS_STATE,\n\n\tNL80211_ATTR_CQM,\n\n\tNL80211_ATTR_LOCAL_STATE_CHANGE,\n\n\tNL80211_ATTR_AP_ISOLATE,\n\n\tNL80211_ATTR_WIPHY_TX_POWER_SETTING,\n\tNL80211_ATTR_WIPHY_TX_POWER_LEVEL,\n\n\tNL80211_ATTR_TX_FRAME_TYPES,\n\tNL80211_ATTR_RX_FRAME_TYPES,\n\tNL80211_ATTR_FRAME_TYPE,\n\n\tNL80211_ATTR_CONTROL_PORT_ETHERTYPE,\n\tNL80211_ATTR_CONTROL_PORT_NO_ENCRYPT,\n\n\tNL80211_ATTR_SUPPORT_IBSS_RSN,\n\n\tNL80211_ATTR_WIPHY_ANTENNA_TX,\n\tNL80211_ATTR_WIPHY_ANTENNA_RX,\n\n\tNL80211_ATTR_MCAST_RATE,\n\n\tNL80211_ATTR_OFFCHANNEL_TX_OK,\n\n\tNL80211_ATTR_BSS_HT_OPMODE,\n\n\tNL80211_ATTR_KEY_DEFAULT_TYPES,\n\n\tNL80211_ATTR_MAX_REMAIN_ON_CHANNEL_DURATION,\n\n\tNL80211_ATTR_MESH_SETUP,\n\n\tNL80211_ATTR_WIPHY_ANTENNA_AVAIL_TX,\n\tNL80211_ATTR_WIPHY_ANTENNA_AVAIL_RX,\n\n\tNL80211_ATTR_SUPPORT_MESH_AUTH,\n\tNL80211_ATTR_STA_PLINK_STATE,\n\n\tNL80211_ATTR_WOWLAN_TRIGGERS,\n\tNL80211_ATTR_WOWLAN_TRIGGERS_SUPPORTED,\n\n\tNL80211_ATTR_SCHED_SCAN_INTERVAL,\n\n\tNL80211_ATTR_INTERFACE_COMBINATIONS,\n\tNL80211_ATTR_SOFTWARE_IFTYPES,\n\n\tNL80211_ATTR_REKEY_DATA,\n\n\tNL80211_ATTR_MAX_NUM_SCHED_SCAN_SSIDS,\n\tNL80211_ATTR_MAX_SCHED_SCAN_IE_LEN,\n\n\tNL80211_ATTR_SCAN_SUPP_RATES,\n\n\tNL80211_ATTR_HIDDEN_SSID,\n\n\tNL80211_ATTR_IE_PROBE_RESP,\n\tNL80211_ATTR_IE_ASSOC_RESP,\n\n\tNL80211_ATTR_STA_WME,\n\tNL80211_ATTR_SUPPORT_AP_UAPSD,\n\n\tNL80211_ATTR_ROAM_SUPPORT,\n\n\tNL80211_ATTR_SCHED_SCAN_MATCH,\n\tNL80211_ATTR_MAX_MATCH_SETS,\n\n\tNL80211_ATTR_PMKSA_CANDIDATE,\n\n\tNL80211_ATTR_TX_NO_CCK_RATE,\n\n\tNL80211_ATTR_TDLS_ACTION,\n\tNL80211_ATTR_TDLS_DIALOG_TOKEN,\n\tNL80211_ATTR_TDLS_OPERATION,\n\tNL80211_ATTR_TDLS_SUPPORT,\n\tNL80211_ATTR_TDLS_EXTERNAL_SETUP,\n\n\tNL80211_ATTR_DEVICE_AP_SME,\n\n\tNL80211_ATTR_DONT_WAIT_FOR_ACK,\n\n\tNL80211_ATTR_FEATURE_FLAGS,\n\n\tNL80211_ATTR_PROBE_RESP_OFFLOAD,\n\n\tNL80211_ATTR_PROBE_RESP,\n\n\tNL80211_ATTR_DFS_REGION,\n\n\tNL80211_ATTR_DISABLE_HT,\n\tNL80211_ATTR_HT_CAPABILITY_MASK,\n\n\tNL80211_ATTR_NOACK_MAP,\n\n\tNL80211_ATTR_INACTIVITY_TIMEOUT,\n\n\tNL80211_ATTR_RX_SIGNAL_DBM,\n\n\tNL80211_ATTR_BG_SCAN_PERIOD,\n\n\tNL80211_ATTR_WDEV,\n\n\tNL80211_ATTR_USER_REG_HINT_TYPE,\n\n\tNL80211_ATTR_CONN_FAILED_REASON,\n\n\tNL80211_ATTR_AUTH_DATA,\n\n\tNL80211_ATTR_VHT_CAPABILITY,\n\n\tNL80211_ATTR_SCAN_FLAGS,\n\n\tNL80211_ATTR_CHANNEL_WIDTH,\n\tNL80211_ATTR_CENTER_FREQ1,\n\tNL80211_ATTR_CENTER_FREQ2,\n\n\tNL80211_ATTR_P2P_CTWINDOW,\n\tNL80211_ATTR_P2P_OPPPS,\n\n\tNL80211_ATTR_LOCAL_MESH_POWER_MODE,\n\n\tNL80211_ATTR_ACL_POLICY,\n\n\tNL80211_ATTR_MAC_ADDRS,\n\n\tNL80211_ATTR_MAC_ACL_MAX,\n\n\tNL80211_ATTR_RADAR_EVENT,\n\n\tNL80211_ATTR_EXT_CAPA,\n\tNL80211_ATTR_EXT_CAPA_MASK,\n\n\tNL80211_ATTR_STA_CAPABILITY,\n\tNL80211_ATTR_STA_EXT_CAPABILITY,\n\n\tNL80211_ATTR_PROTOCOL_FEATURES,\n\tNL80211_ATTR_SPLIT_WIPHY_DUMP,\n\n\tNL80211_ATTR_DISABLE_VHT,\n\tNL80211_ATTR_VHT_CAPABILITY_MASK,\n\n\tNL80211_ATTR_MDID,\n\tNL80211_ATTR_IE_RIC,\n\n\tNL80211_ATTR_CRIT_PROT_ID,\n\tNL80211_ATTR_MAX_CRIT_PROT_DURATION,\n\n\tNL80211_ATTR_PEER_AID,\n\n\tNL80211_ATTR_COALESCE_RULE,\n\n\tNL80211_ATTR_CH_SWITCH_COUNT,\n\tNL80211_ATTR_CH_SWITCH_BLOCK_TX,\n\tNL80211_ATTR_CSA_IES,\n\tNL80211_ATTR_CSA_C_OFF_BEACON,\n\tNL80211_ATTR_CSA_C_OFF_PRESP,\n\n\tNL80211_ATTR_RXMGMT_FLAGS,\n\n\tNL80211_ATTR_STA_SUPPORTED_CHANNELS,\n\n\tNL80211_ATTR_STA_SUPPORTED_OPER_CLASSES,\n\n\tNL80211_ATTR_HANDLE_DFS,\n\n\tNL80211_ATTR_SUPPORT_5_MHZ,\n\tNL80211_ATTR_SUPPORT_10_MHZ,\n\n\tNL80211_ATTR_OPMODE_NOTIF,\n\n\tNL80211_ATTR_VENDOR_ID,\n\tNL80211_ATTR_VENDOR_SUBCMD,\n\tNL80211_ATTR_VENDOR_DATA,\n\tNL80211_ATTR_VENDOR_EVENTS,\n\n\tNL80211_ATTR_QOS_MAP,\n\n\tNL80211_ATTR_MAC_HINT,\n\tNL80211_ATTR_WIPHY_FREQ_HINT,\n\n\tNL80211_ATTR_MAX_AP_ASSOC_STA,\n\n\tNL80211_ATTR_TDLS_PEER_CAPABILITY,\n\n\tNL80211_ATTR_SOCKET_OWNER,\n\n\tNL80211_ATTR_CSA_C_OFFSETS_TX,\n\tNL80211_ATTR_MAX_CSA_COUNTERS,\n\n\tNL80211_ATTR_TDLS_INITIATOR,\n\n\tNL80211_ATTR_USE_RRM,\n\n\tNL80211_ATTR_WIPHY_DYN_ACK,\n\n\tNL80211_ATTR_TSID,\n\tNL80211_ATTR_USER_PRIO,\n\tNL80211_ATTR_ADMITTED_TIME,\n\n\tNL80211_ATTR_SMPS_MODE,\n\n\tNL80211_ATTR_OPER_CLASS,\n\n\tNL80211_ATTR_MAC_MASK,\n\n\tNL80211_ATTR_WIPHY_SELF_MANAGED_REG,\n\n\tNL80211_ATTR_EXT_FEATURES,\n\n\tNL80211_ATTR_SURVEY_RADIO_STATS,\n\n\tNL80211_ATTR_NETNS_FD,\n\n\tNL80211_ATTR_SCHED_SCAN_DELAY,\n\n\tNL80211_ATTR_REG_INDOOR,\n\n\tNL80211_ATTR_MAX_NUM_SCHED_SCAN_PLANS,\n\tNL80211_ATTR_MAX_SCAN_PLAN_INTERVAL,\n\tNL80211_ATTR_MAX_SCAN_PLAN_ITERATIONS,\n\tNL80211_ATTR_SCHED_SCAN_PLANS,\n\n\tNL80211_ATTR_PBSS,\n\n\tNL80211_ATTR_BSS_SELECT,\n\n\tNL80211_ATTR_STA_SUPPORT_P2P_PS,\n\n\tNL80211_ATTR_PAD,\n\n\tNL80211_ATTR_IFTYPE_EXT_CAPA,\n\n\tNL80211_ATTR_MU_MIMO_GROUP_DATA,\n\tNL80211_ATTR_MU_MIMO_FOLLOW_MAC_ADDR,\n\n\tNL80211_ATTR_SCAN_START_TIME_TSF,\n\tNL80211_ATTR_SCAN_START_TIME_TSF_BSSID,\n\tNL80211_ATTR_MEASUREMENT_DURATION,\n\tNL80211_ATTR_MEASUREMENT_DURATION_MANDATORY,\n\n\tNL80211_ATTR_MESH_PEER_AID,\n\n\tNL80211_ATTR_NAN_MASTER_PREF,\n\tNL80211_ATTR_BANDS,\n\tNL80211_ATTR_NAN_FUNC,\n\tNL80211_ATTR_NAN_MATCH,\n\n\tNL80211_ATTR_FILS_KEK,\n\tNL80211_ATTR_FILS_NONCES,\n\n\tNL80211_ATTR_MULTICAST_TO_UNICAST_ENABLED,\n\n\tNL80211_ATTR_BSSID,\n\n\tNL80211_ATTR_SCHED_SCAN_RELATIVE_RSSI,\n\tNL80211_ATTR_SCHED_SCAN_RSSI_ADJUST,\n\n\tNL80211_ATTR_TIMEOUT_REASON,\n\n\tNL80211_ATTR_FILS_ERP_USERNAME,\n\tNL80211_ATTR_FILS_ERP_REALM,\n\tNL80211_ATTR_FILS_ERP_NEXT_SEQ_NUM,\n\tNL80211_ATTR_FILS_ERP_RRK,\n\tNL80211_ATTR_FILS_CACHE_ID,\n\n\tNL80211_ATTR_PMK,\n\n\tNL80211_ATTR_SCHED_SCAN_MULTI,\n\tNL80211_ATTR_SCHED_SCAN_MAX_REQS,\n\n\tNL80211_ATTR_WANT_1X_4WAY_HS,\n\tNL80211_ATTR_PMKR0_NAME,\n\tNL80211_ATTR_PORT_AUTHORIZED,\n\n\t/* add attributes here, update the policy in nl80211.c */\n\n\t__NL80211_ATTR_AFTER_LAST,\n\tNUM_NL80211_ATTR = __NL80211_ATTR_AFTER_LAST,\n\tNL80211_ATTR_MAX = __NL80211_ATTR_AFTER_LAST - 1\n};\n\n/* source-level API compatibility */\n#define NL80211_ATTR_SCAN_GENERATION NL80211_ATTR_GENERATION\n#define\tNL80211_ATTR_MESH_PARAMS NL80211_ATTR_MESH_CONFIG\n#define NL80211_ATTR_IFACE_SOCKET_OWNER NL80211_ATTR_SOCKET_OWNER\n#define NL80211_ATTR_SAE_DATA NL80211_ATTR_AUTH_DATA\n\n/*\n * Allow user space programs to use #ifdef on new attributes by defining them\n * here\n */\n#define NL80211_CMD_CONNECT NL80211_CMD_CONNECT\n#define NL80211_ATTR_HT_CAPABILITY NL80211_ATTR_HT_CAPABILITY\n#define NL80211_ATTR_BSS_BASIC_RATES NL80211_ATTR_BSS_BASIC_RATES\n#define NL80211_ATTR_WIPHY_TXQ_PARAMS NL80211_ATTR_WIPHY_TXQ_PARAMS\n#define NL80211_ATTR_WIPHY_FREQ NL80211_ATTR_WIPHY_FREQ\n#define NL80211_ATTR_WIPHY_CHANNEL_TYPE NL80211_ATTR_WIPHY_CHANNEL_TYPE\n#define NL80211_ATTR_MGMT_SUBTYPE NL80211_ATTR_MGMT_SUBTYPE\n#define NL80211_ATTR_IE NL80211_ATTR_IE\n#define NL80211_ATTR_REG_INITIATOR NL80211_ATTR_REG_INITIATOR\n#define NL80211_ATTR_REG_TYPE NL80211_ATTR_REG_TYPE\n#define NL80211_ATTR_FRAME NL80211_ATTR_FRAME\n#define NL80211_ATTR_SSID NL80211_ATTR_SSID\n#define NL80211_ATTR_AUTH_TYPE NL80211_ATTR_AUTH_TYPE\n#define NL80211_ATTR_REASON_CODE NL80211_ATTR_REASON_CODE\n#define NL80211_ATTR_CIPHER_SUITES_PAIRWISE NL80211_ATTR_CIPHER_SUITES_PAIRWISE\n#define NL80211_ATTR_CIPHER_SUITE_GROUP NL80211_ATTR_CIPHER_SUITE_GROUP\n#define NL80211_ATTR_WPA_VERSIONS NL80211_ATTR_WPA_VERSIONS\n#define NL80211_ATTR_AKM_SUITES NL80211_ATTR_AKM_SUITES\n#define NL80211_ATTR_KEY NL80211_ATTR_KEY\n#define NL80211_ATTR_KEYS NL80211_ATTR_KEYS\n#define NL80211_ATTR_FEATURE_FLAGS NL80211_ATTR_FEATURE_FLAGS\n\n#define NL80211_MAX_SUPP_RATES\t\t\t32\n#define NL80211_MAX_SUPP_HT_RATES\t\t77\n#define NL80211_MAX_SUPP_REG_RULES\t\t64\n#define NL80211_TKIP_DATA_OFFSET_ENCR_KEY\t0\n#define NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY\t16\n#define NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY\t24\n#define NL80211_HT_CAPABILITY_LEN\t\t26\n#define NL80211_VHT_CAPABILITY_LEN\t\t12\n\n#define NL80211_MAX_NR_CIPHER_SUITES\t\t5\n#define NL80211_MAX_NR_AKM_SUITES\t\t2\n\n#define NL80211_MIN_REMAIN_ON_CHANNEL_TIME\t10\n\n/* default RSSI threshold for scan results if none specified. */\n#define NL80211_SCAN_RSSI_THOLD_OFF\t\t-300\n\n#define NL80211_CQM_TXE_MAX_INTVL\t\t1800\n\n/**\n * enum nl80211_iftype - (virtual) interface types\n *\n * @NL80211_IFTYPE_UNSPECIFIED: unspecified type, driver decides\n * @NL80211_IFTYPE_ADHOC: independent BSS member\n * @NL80211_IFTYPE_STATION: managed BSS member\n * @NL80211_IFTYPE_AP: access point\n * @NL80211_IFTYPE_AP_VLAN: VLAN interface for access points; VLAN interfaces\n *\tare a bit special in that they must always be tied to a pre-existing\n *\tAP type interface.\n * @NL80211_IFTYPE_WDS: wireless distribution interface\n * @NL80211_IFTYPE_MONITOR: monitor interface receiving all frames\n * @NL80211_IFTYPE_MESH_POINT: mesh point\n * @NL80211_IFTYPE_P2P_CLIENT: P2P client\n * @NL80211_IFTYPE_P2P_GO: P2P group owner\n * @NL80211_IFTYPE_P2P_DEVICE: P2P device interface type, this is not a netdev\n *\tand therefore can't be created in the normal ways, use the\n *\t%NL80211_CMD_START_P2P_DEVICE and %NL80211_CMD_STOP_P2P_DEVICE\n *\tcommands to create and destroy one\n * @NL80211_IF_TYPE_OCB: Outside Context of a BSS\n *\tThis mode corresponds to the MIB variable dot11OCBActivated=true\n * @NL80211_IFTYPE_NAN: NAN device interface type (not a netdev)\n * @NL80211_IFTYPE_MAX: highest interface type number currently defined\n * @NUM_NL80211_IFTYPES: number of defined interface types\n *\n * These values are used with the %NL80211_ATTR_IFTYPE\n * to set the type of an interface.\n *\n */\nenum nl80211_iftype {\n\tNL80211_IFTYPE_UNSPECIFIED,\n\tNL80211_IFTYPE_ADHOC,\n\tNL80211_IFTYPE_STATION,\n\tNL80211_IFTYPE_AP,\n\tNL80211_IFTYPE_AP_VLAN,\n\tNL80211_IFTYPE_WDS,\n\tNL80211_IFTYPE_MONITOR,\n\tNL80211_IFTYPE_MESH_POINT,\n\tNL80211_IFTYPE_P2P_CLIENT,\n\tNL80211_IFTYPE_P2P_GO,\n\tNL80211_IFTYPE_P2P_DEVICE,\n\tNL80211_IFTYPE_OCB,\n\tNL80211_IFTYPE_NAN,\n\n\t/* keep last */\n\tNUM_NL80211_IFTYPES,\n\tNL80211_IFTYPE_MAX = NUM_NL80211_IFTYPES - 1\n};\n\n/**\n * enum nl80211_sta_flags - station flags\n *\n * Station flags. When a station is added to an AP interface, it is\n * assumed to be already associated (and hence authenticated.)\n *\n * @__NL80211_STA_FLAG_INVALID: attribute number 0 is reserved\n * @NL80211_STA_FLAG_AUTHORIZED: station is authorized (802.1X)\n * @NL80211_STA_FLAG_SHORT_PREAMBLE: station is capable of receiving frames\n *\twith short barker preamble\n * @NL80211_STA_FLAG_WME: station is WME/QoS capable\n * @NL80211_STA_FLAG_MFP: station uses management frame protection\n * @NL80211_STA_FLAG_AUTHENTICATED: station is authenticated\n * @NL80211_STA_FLAG_TDLS_PEER: station is a TDLS peer -- this flag should\n *\tonly be used in managed mode (even in the flags mask). Note that the\n *\tflag can't be changed, it is only valid while adding a station, and\n *\tattempts to change it will silently be ignored (rather than rejected\n *\tas errors.)\n * @NL80211_STA_FLAG_ASSOCIATED: station is associated; used with drivers\n *\tthat support %NL80211_FEATURE_FULL_AP_CLIENT_STATE to transition a\n *\tpreviously added station into associated state\n * @NL80211_STA_FLAG_MAX: highest station flag number currently defined\n * @__NL80211_STA_FLAG_AFTER_LAST: internal use\n */\nenum nl80211_sta_flags {\n\t__NL80211_STA_FLAG_INVALID,\n\tNL80211_STA_FLAG_AUTHORIZED,\n\tNL80211_STA_FLAG_SHORT_PREAMBLE,\n\tNL80211_STA_FLAG_WME,\n\tNL80211_STA_FLAG_MFP,\n\tNL80211_STA_FLAG_AUTHENTICATED,\n\tNL80211_STA_FLAG_TDLS_PEER,\n\tNL80211_STA_FLAG_ASSOCIATED,\n\n\t/* keep last */\n\t__NL80211_STA_FLAG_AFTER_LAST,\n\tNL80211_STA_FLAG_MAX = __NL80211_STA_FLAG_AFTER_LAST - 1\n};\n\n/**\n * enum nl80211_sta_p2p_ps_status - station support of P2P PS\n *\n * @NL80211_P2P_PS_UNSUPPORTED: station doesn't support P2P PS mechanism\n * @@NL80211_P2P_PS_SUPPORTED: station supports P2P PS mechanism\n * @NUM_NL80211_P2P_PS_STATUS: number of values\n */\nenum nl80211_sta_p2p_ps_status {\n\tNL80211_P2P_PS_UNSUPPORTED = 0,\n\tNL80211_P2P_PS_SUPPORTED,\n\n\tNUM_NL80211_P2P_PS_STATUS,\n};\n\n#define NL80211_STA_FLAG_MAX_OLD_API\tNL80211_STA_FLAG_TDLS_PEER\n\n/**\n * struct nl80211_sta_flag_update - station flags mask/set\n * @mask: mask of station flags to set\n * @set: which values to set them to\n *\n * Both mask and set contain bits as per &enum nl80211_sta_flags.\n */\nstruct nl80211_sta_flag_update {\n\t__u32 mask;\n\t__u32 set;\n} __attribute__((packed));\n\n/**\n * enum nl80211_rate_info - bitrate information\n *\n * These attribute types are used with %NL80211_STA_INFO_TXRATE\n * when getting information about the bitrate of a station.\n * There are 2 attributes for bitrate, a legacy one that represents\n * a 16-bit value, and new one that represents a 32-bit value.\n * If the rate value fits into 16 bit, both attributes are reported\n * with the same value. If the rate is too high to fit into 16 bits\n * (>6.5535Gbps) only 32-bit attribute is included.\n * User space tools encouraged to use the 32-bit attribute and fall\n * back to the 16-bit one for compatibility with older kernels.\n *\n * @__NL80211_RATE_INFO_INVALID: attribute number 0 is reserved\n * @NL80211_RATE_INFO_BITRATE: total bitrate (u16, 100kbit/s)\n * @NL80211_RATE_INFO_MCS: mcs index for 802.11n (u8)\n * @NL80211_RATE_INFO_40_MHZ_WIDTH: 40 MHz dualchannel bitrate\n * @NL80211_RATE_INFO_SHORT_GI: 400ns guard interval\n * @NL80211_RATE_INFO_BITRATE32: total bitrate (u32, 100kbit/s)\n * @NL80211_RATE_INFO_MAX: highest rate_info number currently defined\n * @NL80211_RATE_INFO_VHT_MCS: MCS index for VHT (u8)\n * @NL80211_RATE_INFO_VHT_NSS: number of streams in VHT (u8)\n * @NL80211_RATE_INFO_80_MHZ_WIDTH: 80 MHz VHT rate\n * @NL80211_RATE_INFO_80P80_MHZ_WIDTH: unused - 80+80 is treated the\n *\tsame as 160 for purposes of the bitrates\n * @NL80211_RATE_INFO_160_MHZ_WIDTH: 160 MHz VHT rate\n * @NL80211_RATE_INFO_10_MHZ_WIDTH: 10 MHz width - note that this is\n *\ta legacy rate and will be reported as the actual bitrate, i.e.\n *\thalf the base (20 MHz) rate\n * @NL80211_RATE_INFO_5_MHZ_WIDTH: 5 MHz width - note that this is\n *\ta legacy rate and will be reported as the actual bitrate, i.e.\n *\ta quarter of the base (20 MHz) rate\n * @__NL80211_RATE_INFO_AFTER_LAST: internal use\n */\nenum nl80211_rate_info {\n\t__NL80211_RATE_INFO_INVALID,\n\tNL80211_RATE_INFO_BITRATE,\n\tNL80211_RATE_INFO_MCS,\n\tNL80211_RATE_INFO_40_MHZ_WIDTH,\n\tNL80211_RATE_INFO_SHORT_GI,\n\tNL80211_RATE_INFO_BITRATE32,\n\tNL80211_RATE_INFO_VHT_MCS,\n\tNL80211_RATE_INFO_VHT_NSS,\n\tNL80211_RATE_INFO_80_MHZ_WIDTH,\n\tNL80211_RATE_INFO_80P80_MHZ_WIDTH,\n\tNL80211_RATE_INFO_160_MHZ_WIDTH,\n\tNL80211_RATE_INFO_10_MHZ_WIDTH,\n\tNL80211_RATE_INFO_5_MHZ_WIDTH,\n\n\t/* keep last */\n\t__NL80211_RATE_INFO_AFTER_LAST,\n\tNL80211_RATE_INFO_MAX = __NL80211_RATE_INFO_AFTER_LAST - 1\n};\n\n/**\n * enum nl80211_sta_bss_param - BSS information collected by STA\n *\n * These attribute types are used with %NL80211_STA_INFO_BSS_PARAM\n * when getting information about the bitrate of a station.\n *\n * @__NL80211_STA_BSS_PARAM_INVALID: attribute number 0 is reserved\n * @NL80211_STA_BSS_PARAM_CTS_PROT: whether CTS protection is enabled (flag)\n * @NL80211_STA_BSS_PARAM_SHORT_PREAMBLE:  whether short preamble is enabled\n *\t(flag)\n * @NL80211_STA_BSS_PARAM_SHORT_SLOT_TIME:  whether short slot time is enabled\n *\t(flag)\n * @NL80211_STA_BSS_PARAM_DTIM_PERIOD: DTIM period for beaconing (u8)\n * @NL80211_STA_BSS_PARAM_BEACON_INTERVAL: Beacon interval (u16)\n * @NL80211_STA_BSS_PARAM_MAX: highest sta_bss_param number currently defined\n * @__NL80211_STA_BSS_PARAM_AFTER_LAST: internal use\n */\nenum nl80211_sta_bss_param {\n\t__NL80211_STA_BSS_PARAM_INVALID,\n\tNL80211_STA_BSS_PARAM_CTS_PROT,\n\tNL80211_STA_BSS_PARAM_SHORT_PREAMBLE,\n\tNL80211_STA_BSS_PARAM_SHORT_SLOT_TIME,\n\tNL80211_STA_BSS_PARAM_DTIM_PERIOD,\n\tNL80211_STA_BSS_PARAM_BEACON_INTERVAL,\n\n\t/* keep last */\n\t__NL80211_STA_BSS_PARAM_AFTER_LAST,\n\tNL80211_STA_BSS_PARAM_MAX = __NL80211_STA_BSS_PARAM_AFTER_LAST - 1\n};\n\n/**\n * enum nl80211_sta_info - station information\n *\n * These attribute types are used with %NL80211_ATTR_STA_INFO\n * when getting information about a station.\n *\n * @__NL80211_STA_INFO_INVALID: attribute number 0 is reserved\n * @NL80211_STA_INFO_INACTIVE_TIME: time since last activity (u32, msecs)\n * @NL80211_STA_INFO_RX_BYTES: total received bytes (MPDU length)\n *\t(u32, from this station)\n * @NL80211_STA_INFO_TX_BYTES: total transmitted bytes (MPDU length)\n *\t(u32, to this station)\n * @NL80211_STA_INFO_RX_BYTES64: total received bytes (MPDU length)\n *\t(u64, from this station)\n * @NL80211_STA_INFO_TX_BYTES64: total transmitted bytes (MPDU length)\n *\t(u64, to this station)\n * @NL80211_STA_INFO_SIGNAL: signal strength of last received PPDU (u8, dBm)\n * @NL80211_STA_INFO_TX_BITRATE: current unicast tx rate, nested attribute\n * \tcontaining info as possible, see &enum nl80211_rate_info\n * @NL80211_STA_INFO_RX_PACKETS: total received packet (MSDUs and MMPDUs)\n *\t(u32, from this station)\n * @NL80211_STA_INFO_TX_PACKETS: total transmitted packets (MSDUs and MMPDUs)\n *\t(u32, to this station)\n * @NL80211_STA_INFO_TX_RETRIES: total retries (MPDUs) (u32, to this station)\n * @NL80211_STA_INFO_TX_FAILED: total failed packets (MPDUs)\n *\t(u32, to this station)\n * @NL80211_STA_INFO_SIGNAL_AVG: signal strength average (u8, dBm)\n * @NL80211_STA_INFO_LLID: the station's mesh LLID\n * @NL80211_STA_INFO_PLID: the station's mesh PLID\n * @NL80211_STA_INFO_PLINK_STATE: peer link state for the station\n *\t(see %enum nl80211_plink_state)\n * @NL80211_STA_INFO_RX_BITRATE: last unicast data frame rx rate, nested\n *\tattribute, like NL80211_STA_INFO_TX_BITRATE.\n * @NL80211_STA_INFO_BSS_PARAM: current station's view of BSS, nested attribute\n *     containing info as possible, see &enum nl80211_sta_bss_param\n * @NL80211_STA_INFO_CONNECTED_TIME: time since the station is last connected\n * @NL80211_STA_INFO_STA_FLAGS: Contains a struct nl80211_sta_flag_update.\n * @NL80211_STA_INFO_BEACON_LOSS: count of times beacon loss was detected (u32)\n * @NL80211_STA_INFO_T_OFFSET: timing offset with respect to this STA (s64)\n * @NL80211_STA_INFO_LOCAL_PM: local mesh STA link-specific power mode\n * @NL80211_STA_INFO_PEER_PM: peer mesh STA link-specific power mode\n * @NL80211_STA_INFO_NONPEER_PM: neighbor mesh STA power save mode towards\n *\tnon-peer STA\n * @NL80211_STA_INFO_CHAIN_SIGNAL: per-chain signal strength of last PPDU\n *\tContains a nested array of signal strength attributes (u8, dBm)\n * @NL80211_STA_INFO_CHAIN_SIGNAL_AVG: per-chain signal strength average\n *\tSame format as NL80211_STA_INFO_CHAIN_SIGNAL.\n * @NL80211_STA_EXPECTED_THROUGHPUT: expected throughput considering also the\n *\t802.11 header (u32, kbps)\n * @NL80211_STA_INFO_RX_DROP_MISC: RX packets dropped for unspecified reasons\n *\t(u64)\n * @NL80211_STA_INFO_BEACON_RX: number of beacons received from this peer (u64)\n * @NL80211_STA_INFO_BEACON_SIGNAL_AVG: signal strength average\n *\tfor beacons only (u8, dBm)\n * @NL80211_STA_INFO_TID_STATS: per-TID statistics (see &enum nl80211_tid_stats)\n *\tThis is a nested attribute where each the inner attribute number is the\n *\tTID+1 and the special TID 16 (i.e. value 17) is used for non-QoS frames;\n *\teach one of those is again nested with &enum nl80211_tid_stats\n *\tattributes carrying the actual values.\n * @NL80211_STA_INFO_RX_DURATION: aggregate PPDU duration for all frames\n *\treceived from the station (u64, usec)\n * @NL80211_STA_INFO_PAD: attribute used for padding for 64-bit alignment\n * @__NL80211_STA_INFO_AFTER_LAST: internal\n * @NL80211_STA_INFO_MAX: highest possible station info attribute\n */\nenum nl80211_sta_info {\n\t__NL80211_STA_INFO_INVALID,\n\tNL80211_STA_INFO_INACTIVE_TIME,\n\tNL80211_STA_INFO_RX_BYTES,\n\tNL80211_STA_INFO_TX_BYTES,\n\tNL80211_STA_INFO_LLID,\n\tNL80211_STA_INFO_PLID,\n\tNL80211_STA_INFO_PLINK_STATE,\n\tNL80211_STA_INFO_SIGNAL,\n\tNL80211_STA_INFO_TX_BITRATE,\n\tNL80211_STA_INFO_RX_PACKETS,\n\tNL80211_STA_INFO_TX_PACKETS,\n\tNL80211_STA_INFO_TX_RETRIES,\n\tNL80211_STA_INFO_TX_FAILED,\n\tNL80211_STA_INFO_SIGNAL_AVG,\n\tNL80211_STA_INFO_RX_BITRATE,\n\tNL80211_STA_INFO_BSS_PARAM,\n\tNL80211_STA_INFO_CONNECTED_TIME,\n\tNL80211_STA_INFO_STA_FLAGS,\n\tNL80211_STA_INFO_BEACON_LOSS,\n\tNL80211_STA_INFO_T_OFFSET,\n\tNL80211_STA_INFO_LOCAL_PM,\n\tNL80211_STA_INFO_PEER_PM,\n\tNL80211_STA_INFO_NONPEER_PM,\n\tNL80211_STA_INFO_RX_BYTES64,\n\tNL80211_STA_INFO_TX_BYTES64,\n\tNL80211_STA_INFO_CHAIN_SIGNAL,\n\tNL80211_STA_INFO_CHAIN_SIGNAL_AVG,\n\tNL80211_STA_INFO_EXPECTED_THROUGHPUT,\n\tNL80211_STA_INFO_RX_DROP_MISC,\n\tNL80211_STA_INFO_BEACON_RX,\n\tNL80211_STA_INFO_BEACON_SIGNAL_AVG,\n\tNL80211_STA_INFO_TID_STATS,\n\tNL80211_STA_INFO_RX_DURATION,\n\tNL80211_STA_INFO_PAD,\n\n\t/* keep last */\n\t__NL80211_STA_INFO_AFTER_LAST,\n\tNL80211_STA_INFO_MAX = __NL80211_STA_INFO_AFTER_LAST - 1\n};\n\n/**\n * enum nl80211_tid_stats - per TID statistics attributes\n * @__NL80211_TID_STATS_INVALID: attribute number 0 is reserved\n * @NL80211_TID_STATS_RX_MSDU: number of MSDUs received (u64)\n * @NL80211_TID_STATS_TX_MSDU: number of MSDUs transmitted (or\n *\tattempted to transmit; u64)\n * @NL80211_TID_STATS_TX_MSDU_RETRIES: number of retries for\n *\ttransmitted MSDUs (not counting the first attempt; u64)\n * @NL80211_TID_STATS_TX_MSDU_FAILED: number of failed transmitted\n *\tMSDUs (u64)\n * @NL80211_TID_STATS_PAD: attribute used for padding for 64-bit alignment\n * @NUM_NL80211_TID_STATS: number of attributes here\n * @NL80211_TID_STATS_MAX: highest numbered attribute here\n */\nenum nl80211_tid_stats {\n\t__NL80211_TID_STATS_INVALID,\n\tNL80211_TID_STATS_RX_MSDU,\n\tNL80211_TID_STATS_TX_MSDU,\n\tNL80211_TID_STATS_TX_MSDU_RETRIES,\n\tNL80211_TID_STATS_TX_MSDU_FAILED,\n\tNL80211_TID_STATS_PAD,\n\n\t/* keep last */\n\tNUM_NL80211_TID_STATS,\n\tNL80211_TID_STATS_MAX = NUM_NL80211_TID_STATS - 1\n};\n\n/**\n * enum nl80211_mpath_flags - nl80211 mesh path flags\n *\n * @NL80211_MPATH_FLAG_ACTIVE: the mesh path is active\n * @NL80211_MPATH_FLAG_RESOLVING: the mesh path discovery process is running\n * @NL80211_MPATH_FLAG_SN_VALID: the mesh path contains a valid SN\n * @NL80211_MPATH_FLAG_FIXED: the mesh path has been manually set\n * @NL80211_MPATH_FLAG_RESOLVED: the mesh path discovery process succeeded\n */\nenum nl80211_mpath_flags {\n\tNL80211_MPATH_FLAG_ACTIVE =\t1<<0,\n\tNL80211_MPATH_FLAG_RESOLVING =\t1<<1,\n\tNL80211_MPATH_FLAG_SN_VALID =\t1<<2,\n\tNL80211_MPATH_FLAG_FIXED =\t1<<3,\n\tNL80211_MPATH_FLAG_RESOLVED =\t1<<4,\n};\n\n/**\n * enum nl80211_mpath_info - mesh path information\n *\n * These attribute types are used with %NL80211_ATTR_MPATH_INFO when getting\n * information about a mesh path.\n *\n * @__NL80211_MPATH_INFO_INVALID: attribute number 0 is reserved\n * @NL80211_MPATH_INFO_FRAME_QLEN: number of queued frames for this destination\n * @NL80211_MPATH_INFO_SN: destination sequence number\n * @NL80211_MPATH_INFO_METRIC: metric (cost) of this mesh path\n * @NL80211_MPATH_INFO_EXPTIME: expiration time for the path, in msec from now\n * @NL80211_MPATH_INFO_FLAGS: mesh path flags, enumerated in\n * \t&enum nl80211_mpath_flags;\n * @NL80211_MPATH_INFO_DISCOVERY_TIMEOUT: total path discovery timeout, in msec\n * @NL80211_MPATH_INFO_DISCOVERY_RETRIES: mesh path discovery retries\n * @NL80211_MPATH_INFO_MAX: highest mesh path information attribute number\n *\tcurrently defined\n * @__NL80211_MPATH_INFO_AFTER_LAST: internal use\n */\nenum nl80211_mpath_info {\n\t__NL80211_MPATH_INFO_INVALID,\n\tNL80211_MPATH_INFO_FRAME_QLEN,\n\tNL80211_MPATH_INFO_SN,\n\tNL80211_MPATH_INFO_METRIC,\n\tNL80211_MPATH_INFO_EXPTIME,\n\tNL80211_MPATH_INFO_FLAGS,\n\tNL80211_MPATH_INFO_DISCOVERY_TIMEOUT,\n\tNL80211_MPATH_INFO_DISCOVERY_RETRIES,\n\n\t/* keep last */\n\t__NL80211_MPATH_INFO_AFTER_LAST,\n\tNL80211_MPATH_INFO_MAX = __NL80211_MPATH_INFO_AFTER_LAST - 1\n};\n\n/**\n * enum nl80211_band_attr - band attributes\n * @__NL80211_BAND_ATTR_INVALID: attribute number 0 is reserved\n * @NL80211_BAND_ATTR_FREQS: supported frequencies in this band,\n *\tan array of nested frequency attributes\n * @NL80211_BAND_ATTR_RATES: supported bitrates in this band,\n *\tan array of nested bitrate attributes\n * @NL80211_BAND_ATTR_HT_MCS_SET: 16-byte attribute containing the MCS set as\n *\tdefined in 802.11n\n * @NL80211_BAND_ATTR_HT_CAPA: HT capabilities, as in the HT information IE\n * @NL80211_BAND_ATTR_HT_AMPDU_FACTOR: A-MPDU factor, as in 11n\n * @NL80211_BAND_ATTR_HT_AMPDU_DENSITY: A-MPDU density, as in 11n\n * @NL80211_BAND_ATTR_VHT_MCS_SET: 32-byte attribute containing the MCS set as\n *\tdefined in 802.11ac\n * @NL80211_BAND_ATTR_VHT_CAPA: VHT capabilities, as in the HT information IE\n * @NL80211_BAND_ATTR_MAX: highest band attribute currently defined\n * @__NL80211_BAND_ATTR_AFTER_LAST: internal use\n */\nenum nl80211_band_attr {\n\t__NL80211_BAND_ATTR_INVALID,\n\tNL80211_BAND_ATTR_FREQS,\n\tNL80211_BAND_ATTR_RATES,\n\n\tNL80211_BAND_ATTR_HT_MCS_SET,\n\tNL80211_BAND_ATTR_HT_CAPA,\n\tNL80211_BAND_ATTR_HT_AMPDU_FACTOR,\n\tNL80211_BAND_ATTR_HT_AMPDU_DENSITY,\n\n\tNL80211_BAND_ATTR_VHT_MCS_SET,\n\tNL80211_BAND_ATTR_VHT_CAPA,\n\n\t/* keep last */\n\t__NL80211_BAND_ATTR_AFTER_LAST,\n\tNL80211_BAND_ATTR_MAX = __NL80211_BAND_ATTR_AFTER_LAST - 1\n};\n\n#define NL80211_BAND_ATTR_HT_CAPA NL80211_BAND_ATTR_HT_CAPA\n\n/**\n * enum nl80211_frequency_attr - frequency attributes\n * @__NL80211_FREQUENCY_ATTR_INVALID: attribute number 0 is reserved\n * @NL80211_FREQUENCY_ATTR_FREQ: Frequency in MHz\n * @NL80211_FREQUENCY_ATTR_DISABLED: Channel is disabled in current\n *\tregulatory domain.\n * @NL80211_FREQUENCY_ATTR_NO_IR: no mechanisms that initiate radiation\n * \tare permitted on this channel, this includes sending probe\n * \trequests, or modes of operation that require beaconing.\n * @NL80211_FREQUENCY_ATTR_RADAR: Radar detection is mandatory\n *\ton this channel in current regulatory domain.\n * @NL80211_FREQUENCY_ATTR_MAX_TX_POWER: Maximum transmission power in mBm\n *\t(100 * dBm).\n * @NL80211_FREQUENCY_ATTR_DFS_STATE: current state for DFS\n *\t(enum nl80211_dfs_state)\n * @NL80211_FREQUENCY_ATTR_DFS_TIME: time in milliseconds for how long\n *\tthis channel is in this DFS state.\n * @NL80211_FREQUENCY_ATTR_NO_HT40_MINUS: HT40- isn't possible with this\n *\tchannel as the control channel\n * @NL80211_FREQUENCY_ATTR_NO_HT40_PLUS: HT40+ isn't possible with this\n *\tchannel as the control channel\n * @NL80211_FREQUENCY_ATTR_NO_80MHZ: any 80 MHz channel using this channel\n *\tas the primary or any of the secondary channels isn't possible,\n *\tthis includes 80+80 channels\n * @NL80211_FREQUENCY_ATTR_NO_160MHZ: any 160 MHz (but not 80+80) channel\n *\tusing this channel as the primary or any of the secondary channels\n *\tisn't possible\n * @NL80211_FREQUENCY_ATTR_DFS_CAC_TIME: DFS CAC time in milliseconds.\n * @NL80211_FREQUENCY_ATTR_INDOOR_ONLY: Only indoor use is permitted on this\n *\tchannel. A channel that has the INDOOR_ONLY attribute can only be\n *\tused when there is a clear assessment that the device is operating in\n *\tan indoor surroundings, i.e., it is connected to AC power (and not\n *\tthrough portable DC inverters) or is under the control of a master\n *\tthat is acting as an AP and is connected to AC power.\n * @NL80211_FREQUENCY_ATTR_IR_CONCURRENT: IR operation is allowed on this\n *\tchannel if it's connected concurrently to a BSS on the same channel on\n *\tthe 2 GHz band or to a channel in the same UNII band (on the 5 GHz\n *\tband), and IEEE80211_CHAN_RADAR is not set. Instantiating a GO or TDLS\n *\toff-channel on a channel that has the IR_CONCURRENT attribute set can be\n *\tdone when there is a clear assessment that the device is operating under\n *\tthe guidance of an authorized master, i.e., setting up a GO or TDLS\n *\toff-channel while the device is also connected to an AP with DFS and\n *\tradar detection on the UNII band (it is up to user-space, i.e.,\n *\twpa_supplicant to perform the required verifications). Using this\n *\tattribute for IR is disallowed for master interfaces (IBSS, AP).\n * @NL80211_FREQUENCY_ATTR_NO_20MHZ: 20 MHz operation is not allowed\n *\ton this channel in current regulatory domain.\n * @NL80211_FREQUENCY_ATTR_NO_10MHZ: 10 MHz operation is not allowed\n *\ton this channel in current regulatory domain.\n * @NL80211_FREQUENCY_ATTR_MAX: highest frequency attribute number\n *\tcurrently defined\n * @__NL80211_FREQUENCY_ATTR_AFTER_LAST: internal use\n *\n * See https://apps.fcc.gov/eas/comments/GetPublishedDocument.html?id=327&tn=528122\n * for more information on the FCC description of the relaxations allowed\n * by NL80211_FREQUENCY_ATTR_INDOOR_ONLY and\n * NL80211_FREQUENCY_ATTR_IR_CONCURRENT.\n */\nenum nl80211_frequency_attr {\n\t__NL80211_FREQUENCY_ATTR_INVALID,\n\tNL80211_FREQUENCY_ATTR_FREQ,\n\tNL80211_FREQUENCY_ATTR_DISABLED,\n\tNL80211_FREQUENCY_ATTR_NO_IR,\n\t__NL80211_FREQUENCY_ATTR_NO_IBSS,\n\tNL80211_FREQUENCY_ATTR_RADAR,\n\tNL80211_FREQUENCY_ATTR_MAX_TX_POWER,\n\tNL80211_FREQUENCY_ATTR_DFS_STATE,\n\tNL80211_FREQUENCY_ATTR_DFS_TIME,\n\tNL80211_FREQUENCY_ATTR_NO_HT40_MINUS,\n\tNL80211_FREQUENCY_ATTR_NO_HT40_PLUS,\n\tNL80211_FREQUENCY_ATTR_NO_80MHZ,\n\tNL80211_FREQUENCY_ATTR_NO_160MHZ,\n\tNL80211_FREQUENCY_ATTR_DFS_CAC_TIME,\n\tNL80211_FREQUENCY_ATTR_INDOOR_ONLY,\n\tNL80211_FREQUENCY_ATTR_IR_CONCURRENT,\n\tNL80211_FREQUENCY_ATTR_NO_20MHZ,\n\tNL80211_FREQUENCY_ATTR_NO_10MHZ,\n\n\t/* keep last */\n\t__NL80211_FREQUENCY_ATTR_AFTER_LAST,\n\tNL80211_FREQUENCY_ATTR_MAX = __NL80211_FREQUENCY_ATTR_AFTER_LAST - 1\n};\n\n#define NL80211_FREQUENCY_ATTR_MAX_TX_POWER NL80211_FREQUENCY_ATTR_MAX_TX_POWER\n#define NL80211_FREQUENCY_ATTR_PASSIVE_SCAN\tNL80211_FREQUENCY_ATTR_NO_IR\n#define NL80211_FREQUENCY_ATTR_NO_IBSS\t\tNL80211_FREQUENCY_ATTR_NO_IR\n#define NL80211_FREQUENCY_ATTR_NO_IR\t\tNL80211_FREQUENCY_ATTR_NO_IR\n#define NL80211_FREQUENCY_ATTR_GO_CONCURRENT \\\n\t\t\t\t\tNL80211_FREQUENCY_ATTR_IR_CONCURRENT\n\n/**\n * enum nl80211_bitrate_attr - bitrate attributes\n * @__NL80211_BITRATE_ATTR_INVALID: attribute number 0 is reserved\n * @NL80211_BITRATE_ATTR_RATE: Bitrate in units of 100 kbps\n * @NL80211_BITRATE_ATTR_2GHZ_SHORTPREAMBLE: Short preamble supported\n *\tin 2.4 GHz band.\n * @NL80211_BITRATE_ATTR_MAX: highest bitrate attribute number\n *\tcurrently defined\n * @__NL80211_BITRATE_ATTR_AFTER_LAST: internal use\n */\nenum nl80211_bitrate_attr {\n\t__NL80211_BITRATE_ATTR_INVALID,\n\tNL80211_BITRATE_ATTR_RATE,\n\tNL80211_BITRATE_ATTR_2GHZ_SHORTPREAMBLE,\n\n\t/* keep last */\n\t__NL80211_BITRATE_ATTR_AFTER_LAST,\n\tNL80211_BITRATE_ATTR_MAX = __NL80211_BITRATE_ATTR_AFTER_LAST - 1\n};\n\n/**\n * enum nl80211_initiator - Indicates the initiator of a reg domain request\n * @NL80211_REGDOM_SET_BY_CORE: Core queried CRDA for a dynamic world\n * \tregulatory domain.\n * @NL80211_REGDOM_SET_BY_USER: User asked the wireless core to set the\n * \tregulatory domain.\n * @NL80211_REGDOM_SET_BY_DRIVER: a wireless drivers has hinted to the\n * \twireless core it thinks its knows the regulatory domain we should be in.\n * @NL80211_REGDOM_SET_BY_COUNTRY_IE: the wireless core has received an\n * \t802.11 country information element with regulatory information it\n * \tthinks we should consider. cfg80211 only processes the country\n *\tcode from the IE, and relies on the regulatory domain information\n *\tstructure passed by userspace (CRDA) from our wireless-regdb.\n *\tIf a channel is enabled but the country code indicates it should\n *\tbe disabled we disable the channel and re-enable it upon disassociation.\n */\nenum nl80211_reg_initiator {\n\tNL80211_REGDOM_SET_BY_CORE,\n\tNL80211_REGDOM_SET_BY_USER,\n\tNL80211_REGDOM_SET_BY_DRIVER,\n\tNL80211_REGDOM_SET_BY_COUNTRY_IE,\n};\n\n/**\n * enum nl80211_reg_type - specifies the type of regulatory domain\n * @NL80211_REGDOM_TYPE_COUNTRY: the regulatory domain set is one that pertains\n *\tto a specific country. When this is set you can count on the\n *\tISO / IEC 3166 alpha2 country code being valid.\n * @NL80211_REGDOM_TYPE_WORLD: the regulatory set domain is the world regulatory\n * \tdomain.\n * @NL80211_REGDOM_TYPE_CUSTOM_WORLD: the regulatory domain set is a custom\n * \tdriver specific world regulatory domain. These do not apply system-wide\n * \tand are only applicable to the individual devices which have requested\n * \tthem to be applied.\n * @NL80211_REGDOM_TYPE_INTERSECTION: the regulatory domain set is the product\n *\tof an intersection between two regulatory domains -- the previously\n *\tset regulatory domain on the system and the last accepted regulatory\n *\tdomain request to be processed.\n */\nenum nl80211_reg_type {\n\tNL80211_REGDOM_TYPE_COUNTRY,\n\tNL80211_REGDOM_TYPE_WORLD,\n\tNL80211_REGDOM_TYPE_CUSTOM_WORLD,\n\tNL80211_REGDOM_TYPE_INTERSECTION,\n};\n\n/**\n * enum nl80211_reg_rule_attr - regulatory rule attributes\n * @__NL80211_REG_RULE_ATTR_INVALID: attribute number 0 is reserved\n * @NL80211_ATTR_REG_RULE_FLAGS: a set of flags which specify additional\n * \tconsiderations for a given frequency range. These are the\n * \t&enum nl80211_reg_rule_flags.\n * @NL80211_ATTR_FREQ_RANGE_START: starting frequencry for the regulatory\n * \trule in KHz. This is not a center of frequency but an actual regulatory\n * \tband edge.\n * @NL80211_ATTR_FREQ_RANGE_END: ending frequency for the regulatory rule\n * \tin KHz. This is not a center a frequency but an actual regulatory\n * \tband edge.\n * @NL80211_ATTR_FREQ_RANGE_MAX_BW: maximum allowed bandwidth for this\n *\tfrequency range, in KHz.\n * @NL80211_ATTR_POWER_RULE_MAX_ANT_GAIN: the maximum allowed antenna gain\n * \tfor a given frequency range. The value is in mBi (100 * dBi).\n * \tIf you don't have one then don't send this.\n * @NL80211_ATTR_POWER_RULE_MAX_EIRP: the maximum allowed EIRP for\n * \ta given frequency range. The value is in mBm (100 * dBm).\n * @NL80211_ATTR_DFS_CAC_TIME: DFS CAC time in milliseconds.\n *\tIf not present or 0 default CAC time will be used.\n * @NL80211_REG_RULE_ATTR_MAX: highest regulatory rule attribute number\n *\tcurrently defined\n * @__NL80211_REG_RULE_ATTR_AFTER_LAST: internal use\n */\nenum nl80211_reg_rule_attr {\n\t__NL80211_REG_RULE_ATTR_INVALID,\n\tNL80211_ATTR_REG_RULE_FLAGS,\n\n\tNL80211_ATTR_FREQ_RANGE_START,\n\tNL80211_ATTR_FREQ_RANGE_END,\n\tNL80211_ATTR_FREQ_RANGE_MAX_BW,\n\n\tNL80211_ATTR_POWER_RULE_MAX_ANT_GAIN,\n\tNL80211_ATTR_POWER_RULE_MAX_EIRP,\n\n\tNL80211_ATTR_DFS_CAC_TIME,\n\n\t/* keep last */\n\t__NL80211_REG_RULE_ATTR_AFTER_LAST,\n\tNL80211_REG_RULE_ATTR_MAX = __NL80211_REG_RULE_ATTR_AFTER_LAST - 1\n};\n\n/**\n * enum nl80211_sched_scan_match_attr - scheduled scan match attributes\n * @__NL80211_SCHED_SCAN_MATCH_ATTR_INVALID: attribute number 0 is reserved\n * @NL80211_SCHED_SCAN_MATCH_ATTR_SSID: SSID to be used for matching,\n *\tonly report BSS with matching SSID.\n *\t(This cannot be used together with BSSID.)\n * @NL80211_SCHED_SCAN_MATCH_ATTR_RSSI: RSSI threshold (in dBm) for reporting a\n *\tBSS in scan results. Filtering is turned off if not specified. Note that\n *\tif this attribute is in a match set of its own, then it is treated as\n *\tthe default value for all matchsets with an SSID, rather than being a\n *\tmatchset of its own without an RSSI filter. This is due to problems with\n *\thow this API was implemented in the past. Also, due to the same problem,\n *\tthe only way to create a matchset with only an RSSI filter (with this\n *\tattribute) is if there's only a single matchset with the RSSI attribute.\n * @NL80211_SCHED_SCAN_MATCH_ATTR_RELATIVE_RSSI: Flag indicating whether\n *\t%NL80211_SCHED_SCAN_MATCH_ATTR_RSSI to be used as absolute RSSI or\n *\trelative to current bss's RSSI.\n * @NL80211_SCHED_SCAN_MATCH_ATTR_RSSI_ADJUST: When present the RSSI level for\n *\tBSS-es in the specified band is to be adjusted before doing\n *\tRSSI-based BSS selection. The attribute value is a packed structure\n *\tvalue as specified by &struct nl80211_bss_select_rssi_adjust.\n * @NL80211_SCHED_SCAN_MATCH_ATTR_BSSID: BSSID to be used for matching\n *\t(this cannot be used together with SSID).\n * @NL80211_SCHED_SCAN_MATCH_ATTR_MAX: highest scheduled scan filter\n *\tattribute number currently defined\n * @__NL80211_SCHED_SCAN_MATCH_ATTR_AFTER_LAST: internal use\n */\nenum nl80211_sched_scan_match_attr {\n\t__NL80211_SCHED_SCAN_MATCH_ATTR_INVALID,\n\n\tNL80211_SCHED_SCAN_MATCH_ATTR_SSID,\n\tNL80211_SCHED_SCAN_MATCH_ATTR_RSSI,\n\tNL80211_SCHED_SCAN_MATCH_ATTR_RELATIVE_RSSI,\n\tNL80211_SCHED_SCAN_MATCH_ATTR_RSSI_ADJUST,\n\tNL80211_SCHED_SCAN_MATCH_ATTR_BSSID,\n\n\t/* keep last */\n\t__NL80211_SCHED_SCAN_MATCH_ATTR_AFTER_LAST,\n\tNL80211_SCHED_SCAN_MATCH_ATTR_MAX =\n\t\t__NL80211_SCHED_SCAN_MATCH_ATTR_AFTER_LAST - 1\n};\n\n/* only for backward compatibility */\n#define NL80211_ATTR_SCHED_SCAN_MATCH_SSID NL80211_SCHED_SCAN_MATCH_ATTR_SSID\n\n/**\n * enum nl80211_reg_rule_flags - regulatory rule flags\n *\n * @NL80211_RRF_NO_OFDM: OFDM modulation not allowed\n * @NL80211_RRF_NO_CCK: CCK modulation not allowed\n * @NL80211_RRF_NO_INDOOR: indoor operation not allowed\n * @NL80211_RRF_NO_OUTDOOR: outdoor operation not allowed\n * @NL80211_RRF_DFS: DFS support is required to be used\n * @NL80211_RRF_PTP_ONLY: this is only for Point To Point links\n * @NL80211_RRF_PTMP_ONLY: this is only for Point To Multi Point links\n * @NL80211_RRF_NO_IR: no mechanisms that initiate radiation are allowed,\n * \tthis includes probe requests or modes of operation that require\n * \tbeaconing.\n * @NL80211_RRF_AUTO_BW: maximum available bandwidth should be calculated\n *\tbase on contiguous rules and wider channels will be allowed to cross\n *\tmultiple contiguous/overlapping frequency ranges.\n * @NL80211_RRF_IR_CONCURRENT: See &NL80211_FREQUENCY_ATTR_IR_CONCURRENT\n * @NL80211_RRF_NO_HT40MINUS: channels can't be used in HT40- operation\n * @NL80211_RRF_NO_HT40PLUS: channels can't be used in HT40+ operation\n * @NL80211_RRF_NO_80MHZ: 80MHz operation not allowed\n * @NL80211_RRF_NO_160MHZ: 160MHz operation not allowed\n */\nenum nl80211_reg_rule_flags {\n\tNL80211_RRF_NO_OFDM\t\t= 1<<0,\n\tNL80211_RRF_NO_CCK\t\t= 1<<1,\n\tNL80211_RRF_NO_INDOOR\t\t= 1<<2,\n\tNL80211_RRF_NO_OUTDOOR\t\t= 1<<3,\n\tNL80211_RRF_DFS\t\t\t= 1<<4,\n\tNL80211_RRF_PTP_ONLY\t\t= 1<<5,\n\tNL80211_RRF_PTMP_ONLY\t\t= 1<<6,\n\tNL80211_RRF_NO_IR\t\t= 1<<7,\n\t__NL80211_RRF_NO_IBSS\t\t= 1<<8,\n\tNL80211_RRF_AUTO_BW\t\t= 1<<11,\n\tNL80211_RRF_IR_CONCURRENT\t= 1<<12,\n\tNL80211_RRF_NO_HT40MINUS\t= 1<<13,\n\tNL80211_RRF_NO_HT40PLUS\t\t= 1<<14,\n\tNL80211_RRF_NO_80MHZ\t\t= 1<<15,\n\tNL80211_RRF_NO_160MHZ\t\t= 1<<16,\n};\n\n#define NL80211_RRF_PASSIVE_SCAN\tNL80211_RRF_NO_IR\n#define NL80211_RRF_NO_IBSS\t\tNL80211_RRF_NO_IR\n#define NL80211_RRF_NO_IR\t\tNL80211_RRF_NO_IR\n#define NL80211_RRF_NO_HT40\t\t(NL80211_RRF_NO_HT40MINUS |\\\n\t\t\t\t\t NL80211_RRF_NO_HT40PLUS)\n#define NL80211_RRF_GO_CONCURRENT\tNL80211_RRF_IR_CONCURRENT\n\n/* For backport compatibility with older userspace */\n#define NL80211_RRF_NO_IR_ALL\t\t(NL80211_RRF_NO_IR | __NL80211_RRF_NO_IBSS)\n\n/**\n * enum nl80211_dfs_regions - regulatory DFS regions\n *\n * @NL80211_DFS_UNSET: Country has no DFS master region specified\n * @NL80211_DFS_FCC: Country follows DFS master rules from FCC\n * @NL80211_DFS_ETSI: Country follows DFS master rules from ETSI\n * @NL80211_DFS_JP: Country follows DFS master rules from JP/MKK/Telec\n */\nenum nl80211_dfs_regions {\n\tNL80211_DFS_UNSET\t= 0,\n\tNL80211_DFS_FCC\t\t= 1,\n\tNL80211_DFS_ETSI\t= 2,\n\tNL80211_DFS_JP\t\t= 3,\n};\n\n/**\n * enum nl80211_user_reg_hint_type - type of user regulatory hint\n *\n * @NL80211_USER_REG_HINT_USER: a user sent the hint. This is always\n *\tassumed if the attribute is not set.\n * @NL80211_USER_REG_HINT_CELL_BASE: the hint comes from a cellular\n *\tbase station. Device drivers that have been tested to work\n *\tproperly to support this type of hint can enable these hints\n *\tby setting the NL80211_FEATURE_CELL_BASE_REG_HINTS feature\n *\tcapability on the struct wiphy. The wireless core will\n *\tignore all cell base station hints until at least one device\n *\tpresent has been registered with the wireless core that\n *\thas listed NL80211_FEATURE_CELL_BASE_REG_HINTS as a\n *\tsupported feature.\n * @NL80211_USER_REG_HINT_INDOOR: a user sent an hint indicating that the\n *\tplatform is operating in an indoor environment.\n */\nenum nl80211_user_reg_hint_type {\n\tNL80211_USER_REG_HINT_USER\t= 0,\n\tNL80211_USER_REG_HINT_CELL_BASE = 1,\n\tNL80211_USER_REG_HINT_INDOOR    = 2,\n};\n\n/**\n * enum nl80211_survey_info - survey information\n *\n * These attribute types are used with %NL80211_ATTR_SURVEY_INFO\n * when getting information about a survey.\n *\n * @__NL80211_SURVEY_INFO_INVALID: attribute number 0 is reserved\n * @NL80211_SURVEY_INFO_FREQUENCY: center frequency of channel\n * @NL80211_SURVEY_INFO_NOISE: noise level of channel (u8, dBm)\n * @NL80211_SURVEY_INFO_IN_USE: channel is currently being used\n * @NL80211_SURVEY_INFO_TIME: amount of time (in ms) that the radio\n *\twas turned on (on channel or globally)\n * @NL80211_SURVEY_INFO_TIME_BUSY: amount of the time the primary\n *\tchannel was sensed busy (either due to activity or energy detect)\n * @NL80211_SURVEY_INFO_TIME_EXT_BUSY: amount of time the extension\n *\tchannel was sensed busy\n * @NL80211_SURVEY_INFO_TIME_RX: amount of time the radio spent\n *\treceiving data (on channel or globally)\n * @NL80211_SURVEY_INFO_TIME_TX: amount of time the radio spent\n *\ttransmitting data (on channel or globally)\n * @NL80211_SURVEY_INFO_TIME_SCAN: time the radio spent for scan\n *\t(on this channel or globally)\n * @NL80211_SURVEY_INFO_PAD: attribute used for padding for 64-bit alignment\n * @NL80211_SURVEY_INFO_MAX: highest survey info attribute number\n *\tcurrently defined\n * @__NL80211_SURVEY_INFO_AFTER_LAST: internal use\n */\nenum nl80211_survey_info {\n\t__NL80211_SURVEY_INFO_INVALID,\n\tNL80211_SURVEY_INFO_FREQUENCY,\n\tNL80211_SURVEY_INFO_NOISE,\n\tNL80211_SURVEY_INFO_IN_USE,\n\tNL80211_SURVEY_INFO_TIME,\n\tNL80211_SURVEY_INFO_TIME_BUSY,\n\tNL80211_SURVEY_INFO_TIME_EXT_BUSY,\n\tNL80211_SURVEY_INFO_TIME_RX,\n\tNL80211_SURVEY_INFO_TIME_TX,\n\tNL80211_SURVEY_INFO_TIME_SCAN,\n\tNL80211_SURVEY_INFO_PAD,\n\n\t/* keep last */\n\t__NL80211_SURVEY_INFO_AFTER_LAST,\n\tNL80211_SURVEY_INFO_MAX = __NL80211_SURVEY_INFO_AFTER_LAST - 1\n};\n\n/* keep old names for compatibility */\n#define NL80211_SURVEY_INFO_CHANNEL_TIME\t\tNL80211_SURVEY_INFO_TIME\n#define NL80211_SURVEY_INFO_CHANNEL_TIME_BUSY\t\tNL80211_SURVEY_INFO_TIME_BUSY\n#define NL80211_SURVEY_INFO_CHANNEL_TIME_EXT_BUSY\tNL80211_SURVEY_INFO_TIME_EXT_BUSY\n#define NL80211_SURVEY_INFO_CHANNEL_TIME_RX\t\tNL80211_SURVEY_INFO_TIME_RX\n#define NL80211_SURVEY_INFO_CHANNEL_TIME_TX\t\tNL80211_SURVEY_INFO_TIME_TX\n\n/**\n * enum nl80211_mntr_flags - monitor configuration flags\n *\n * Monitor configuration flags.\n *\n * @__NL80211_MNTR_FLAG_INVALID: reserved\n *\n * @NL80211_MNTR_FLAG_FCSFAIL: pass frames with bad FCS\n * @NL80211_MNTR_FLAG_PLCPFAIL: pass frames with bad PLCP\n * @NL80211_MNTR_FLAG_CONTROL: pass control frames\n * @NL80211_MNTR_FLAG_OTHER_BSS: disable BSSID filtering\n * @NL80211_MNTR_FLAG_COOK_FRAMES: report frames after processing.\n *\toverrides all other flags.\n * @NL80211_MNTR_FLAG_ACTIVE: use the configured MAC address\n *\tand ACK incoming unicast packets.\n *\n * @__NL80211_MNTR_FLAG_AFTER_LAST: internal use\n * @NL80211_MNTR_FLAG_MAX: highest possible monitor flag\n */\nenum nl80211_mntr_flags {\n\t__NL80211_MNTR_FLAG_INVALID,\n\tNL80211_MNTR_FLAG_FCSFAIL,\n\tNL80211_MNTR_FLAG_PLCPFAIL,\n\tNL80211_MNTR_FLAG_CONTROL,\n\tNL80211_MNTR_FLAG_OTHER_BSS,\n\tNL80211_MNTR_FLAG_COOK_FRAMES,\n\tNL80211_MNTR_FLAG_ACTIVE,\n\n\t/* keep last */\n\t__NL80211_MNTR_FLAG_AFTER_LAST,\n\tNL80211_MNTR_FLAG_MAX = __NL80211_MNTR_FLAG_AFTER_LAST - 1\n};\n\n/**\n * enum nl80211_mesh_power_mode - mesh power save modes\n *\n * @NL80211_MESH_POWER_UNKNOWN: The mesh power mode of the mesh STA is\n *\tnot known or has not been set yet.\n * @NL80211_MESH_POWER_ACTIVE: Active mesh power mode. The mesh STA is\n *\tin Awake state all the time.\n * @NL80211_MESH_POWER_LIGHT_SLEEP: Light sleep mode. The mesh STA will\n *\talternate between Active and Doze states, but will wake up for\n *\tneighbor's beacons.\n * @NL80211_MESH_POWER_DEEP_SLEEP: Deep sleep mode. The mesh STA will\n *\talternate between Active and Doze states, but may not wake up\n *\tfor neighbor's beacons.\n *\n * @__NL80211_MESH_POWER_AFTER_LAST - internal use\n * @NL80211_MESH_POWER_MAX - highest possible power save level\n */\n\nenum nl80211_mesh_power_mode {\n\tNL80211_MESH_POWER_UNKNOWN,\n\tNL80211_MESH_POWER_ACTIVE,\n\tNL80211_MESH_POWER_LIGHT_SLEEP,\n\tNL80211_MESH_POWER_DEEP_SLEEP,\n\n\t__NL80211_MESH_POWER_AFTER_LAST,\n\tNL80211_MESH_POWER_MAX = __NL80211_MESH_POWER_AFTER_LAST - 1\n};\n\n/**\n * enum nl80211_meshconf_params - mesh configuration parameters\n *\n * Mesh configuration parameters. These can be changed while the mesh is\n * active.\n *\n * @__NL80211_MESHCONF_INVALID: internal use\n *\n * @NL80211_MESHCONF_RETRY_TIMEOUT: specifies the initial retry timeout in\n *\tmillisecond units, used by the Peer Link Open message\n *\n * @NL80211_MESHCONF_CONFIRM_TIMEOUT: specifies the initial confirm timeout, in\n *\tmillisecond units, used by the peer link management to close a peer link\n *\n * @NL80211_MESHCONF_HOLDING_TIMEOUT: specifies the holding timeout, in\n *\tmillisecond units\n *\n * @NL80211_MESHCONF_MAX_PEER_LINKS: maximum number of peer links allowed\n *\ton this mesh interface\n *\n * @NL80211_MESHCONF_MAX_RETRIES: specifies the maximum number of peer link\n *\topen retries that can be sent to establish a new peer link instance in a\n *\tmesh\n *\n * @NL80211_MESHCONF_TTL: specifies the value of TTL field set at a source mesh\n *\tpoint.\n *\n * @NL80211_MESHCONF_AUTO_OPEN_PLINKS: whether we should automatically open\n *\tpeer links when we detect compatible mesh peers. Disabled if\n *\t@NL80211_MESH_SETUP_USERSPACE_MPM or @NL80211_MESH_SETUP_USERSPACE_AMPE are\n *\tset.\n *\n * @NL80211_MESHCONF_HWMP_MAX_PREQ_RETRIES: the number of action frames\n *\tcontaining a PREQ that an MP can send to a particular destination (path\n *\ttarget)\n *\n * @NL80211_MESHCONF_PATH_REFRESH_TIME: how frequently to refresh mesh paths\n *\t(in milliseconds)\n *\n * @NL80211_MESHCONF_MIN_DISCOVERY_TIMEOUT: minimum length of time to wait\n *\tuntil giving up on a path discovery (in milliseconds)\n *\n * @NL80211_MESHCONF_HWMP_ACTIVE_PATH_TIMEOUT: The time (in TUs) for which mesh\n *\tpoints receiving a PREQ shall consider the forwarding information from\n *\tthe root to be valid. (TU = time unit)\n *\n * @NL80211_MESHCONF_HWMP_PREQ_MIN_INTERVAL: The minimum interval of time (in\n *\tTUs) during which an MP can send only one action frame containing a PREQ\n *\treference element\n *\n * @NL80211_MESHCONF_HWMP_NET_DIAM_TRVS_TIME: The interval of time (in TUs)\n *\tthat it takes for an HWMP information element to propagate across the\n *\tmesh\n *\n * @NL80211_MESHCONF_HWMP_ROOTMODE: whether root mode is enabled or not\n *\n * @NL80211_MESHCONF_ELEMENT_TTL: specifies the value of TTL field set at a\n *\tsource mesh point for path selection elements.\n *\n * @NL80211_MESHCONF_HWMP_RANN_INTERVAL:  The interval of time (in TUs) between\n *\troot announcements are transmitted.\n *\n * @NL80211_MESHCONF_GATE_ANNOUNCEMENTS: Advertise that this mesh station has\n *\taccess to a broader network beyond the MBSS.  This is done via Root\n *\tAnnouncement frames.\n *\n * @NL80211_MESHCONF_HWMP_PERR_MIN_INTERVAL: The minimum interval of time (in\n *\tTUs) during which a mesh STA can send only one Action frame containing a\n *\tPERR element.\n *\n * @NL80211_MESHCONF_FORWARDING: set Mesh STA as forwarding or non-forwarding\n *\tor forwarding entity (default is TRUE - forwarding entity)\n *\n * @NL80211_MESHCONF_RSSI_THRESHOLD: RSSI threshold in dBm. This specifies the\n *\tthreshold for average signal strength of candidate station to establish\n *\ta peer link.\n *\n * @NL80211_MESHCONF_SYNC_OFFSET_MAX_NEIGHBOR: maximum number of neighbors\n *\tto synchronize to for 11s default synchronization method\n *\t(see 11C.12.2.2)\n *\n * @NL80211_MESHCONF_HT_OPMODE: set mesh HT protection mode.\n *\n * @NL80211_MESHCONF_ATTR_MAX: highest possible mesh configuration attribute\n *\n * @NL80211_MESHCONF_HWMP_PATH_TO_ROOT_TIMEOUT: The time (in TUs) for\n *\twhich mesh STAs receiving a proactive PREQ shall consider the forwarding\n *\tinformation to the root mesh STA to be valid.\n *\n * @NL80211_MESHCONF_HWMP_ROOT_INTERVAL: The interval of time (in TUs) between\n *\tproactive PREQs are transmitted.\n *\n * @NL80211_MESHCONF_HWMP_CONFIRMATION_INTERVAL: The minimum interval of time\n *\t(in TUs) during which a mesh STA can send only one Action frame\n *\tcontaining a PREQ element for root path confirmation.\n *\n * @NL80211_MESHCONF_POWER_MODE: Default mesh power mode for new peer links.\n *\ttype &enum nl80211_mesh_power_mode (u32)\n *\n * @NL80211_MESHCONF_AWAKE_WINDOW: awake window duration (in TUs)\n *\n * @NL80211_MESHCONF_PLINK_TIMEOUT: If no tx activity is seen from a STA we've\n *\testablished peering with for longer than this time (in seconds), then\n *\tremove it from the STA's list of peers. You may set this to 0 to disable\n *\tthe removal of the STA. Default is 30 minutes.\n *\n * @__NL80211_MESHCONF_ATTR_AFTER_LAST: internal use\n */\nenum nl80211_meshconf_params {\n\t__NL80211_MESHCONF_INVALID,\n\tNL80211_MESHCONF_RETRY_TIMEOUT,\n\tNL80211_MESHCONF_CONFIRM_TIMEOUT,\n\tNL80211_MESHCONF_HOLDING_TIMEOUT,\n\tNL80211_MESHCONF_MAX_PEER_LINKS,\n\tNL80211_MESHCONF_MAX_RETRIES,\n\tNL80211_MESHCONF_TTL,\n\tNL80211_MESHCONF_AUTO_OPEN_PLINKS,\n\tNL80211_MESHCONF_HWMP_MAX_PREQ_RETRIES,\n\tNL80211_MESHCONF_PATH_REFRESH_TIME,\n\tNL80211_MESHCONF_MIN_DISCOVERY_TIMEOUT,\n\tNL80211_MESHCONF_HWMP_ACTIVE_PATH_TIMEOUT,\n\tNL80211_MESHCONF_HWMP_PREQ_MIN_INTERVAL,\n\tNL80211_MESHCONF_HWMP_NET_DIAM_TRVS_TIME,\n\tNL80211_MESHCONF_HWMP_ROOTMODE,\n\tNL80211_MESHCONF_ELEMENT_TTL,\n\tNL80211_MESHCONF_HWMP_RANN_INTERVAL,\n\tNL80211_MESHCONF_GATE_ANNOUNCEMENTS,\n\tNL80211_MESHCONF_HWMP_PERR_MIN_INTERVAL,\n\tNL80211_MESHCONF_FORWARDING,\n\tNL80211_MESHCONF_RSSI_THRESHOLD,\n\tNL80211_MESHCONF_SYNC_OFFSET_MAX_NEIGHBOR,\n\tNL80211_MESHCONF_HT_OPMODE,\n\tNL80211_MESHCONF_HWMP_PATH_TO_ROOT_TIMEOUT,\n\tNL80211_MESHCONF_HWMP_ROOT_INTERVAL,\n\tNL80211_MESHCONF_HWMP_CONFIRMATION_INTERVAL,\n\tNL80211_MESHCONF_POWER_MODE,\n\tNL80211_MESHCONF_AWAKE_WINDOW,\n\tNL80211_MESHCONF_PLINK_TIMEOUT,\n\n\t/* keep last */\n\t__NL80211_MESHCONF_ATTR_AFTER_LAST,\n\tNL80211_MESHCONF_ATTR_MAX = __NL80211_MESHCONF_ATTR_AFTER_LAST - 1\n};\n\n/**\n * enum nl80211_mesh_setup_params - mesh setup parameters\n *\n * Mesh setup parameters.  These are used to start/join a mesh and cannot be\n * changed while the mesh is active.\n *\n * @__NL80211_MESH_SETUP_INVALID: Internal use\n *\n * @NL80211_MESH_SETUP_ENABLE_VENDOR_PATH_SEL: Enable this option to use a\n *\tvendor specific path selection algorithm or disable it to use the\n *\tdefault HWMP.\n *\n * @NL80211_MESH_SETUP_ENABLE_VENDOR_METRIC: Enable this option to use a\n *\tvendor specific path metric or disable it to use the default Airtime\n *\tmetric.\n *\n * @NL80211_MESH_SETUP_IE: Information elements for this mesh, for instance, a\n *\trobust security network ie, or a vendor specific information element\n *\tthat vendors will use to identify the path selection methods and\n *\tmetrics in use.\n *\n * @NL80211_MESH_SETUP_USERSPACE_AUTH: Enable this option if an authentication\n *\tdaemon will be authenticating mesh candidates.\n *\n * @NL80211_MESH_SETUP_USERSPACE_AMPE: Enable this option if an authentication\n *\tdaemon will be securing peer link frames.  AMPE is a secured version of\n *\tMesh Peering Management (MPM) and is implemented with the assistance of\n *\ta userspace daemon.  When this flag is set, the kernel will send peer\n *\tmanagement frames to a userspace daemon that will implement AMPE\n *\tfunctionality (security capabilities selection, key confirmation, and\n *\tkey management).  When the flag is unset (default), the kernel can\n *\tautonomously complete (unsecured) mesh peering without the need of a\n *\tuserspace daemon.\n *\n * @NL80211_MESH_SETUP_ENABLE_VENDOR_SYNC: Enable this option to use a\n *\tvendor specific synchronization method or disable it to use the default\n *\tneighbor offset synchronization\n *\n * @NL80211_MESH_SETUP_USERSPACE_MPM: Enable this option if userspace will\n *\timplement an MPM which handles peer allocation and state.\n *\n * @NL80211_MESH_SETUP_AUTH_PROTOCOL: Inform the kernel of the authentication\n *\tmethod (u8, as defined in IEEE 8.4.2.100.6, e.g. 0x1 for SAE).\n *\tDefault is no authentication method required.\n *\n * @NL80211_MESH_SETUP_ATTR_MAX: highest possible mesh setup attribute number\n *\n * @__NL80211_MESH_SETUP_ATTR_AFTER_LAST: Internal use\n */\nenum nl80211_mesh_setup_params {\n\t__NL80211_MESH_SETUP_INVALID,\n\tNL80211_MESH_SETUP_ENABLE_VENDOR_PATH_SEL,\n\tNL80211_MESH_SETUP_ENABLE_VENDOR_METRIC,\n\tNL80211_MESH_SETUP_IE,\n\tNL80211_MESH_SETUP_USERSPACE_AUTH,\n\tNL80211_MESH_SETUP_USERSPACE_AMPE,\n\tNL80211_MESH_SETUP_ENABLE_VENDOR_SYNC,\n\tNL80211_MESH_SETUP_USERSPACE_MPM,\n\tNL80211_MESH_SETUP_AUTH_PROTOCOL,\n\n\t/* keep last */\n\t__NL80211_MESH_SETUP_ATTR_AFTER_LAST,\n\tNL80211_MESH_SETUP_ATTR_MAX = __NL80211_MESH_SETUP_ATTR_AFTER_LAST - 1\n};\n\n/**\n * enum nl80211_txq_attr - TX queue parameter attributes\n * @__NL80211_TXQ_ATTR_INVALID: Attribute number 0 is reserved\n * @NL80211_TXQ_ATTR_AC: AC identifier (NL80211_AC_*)\n * @NL80211_TXQ_ATTR_TXOP: Maximum burst time in units of 32 usecs, 0 meaning\n *\tdisabled\n * @NL80211_TXQ_ATTR_CWMIN: Minimum contention window [a value of the form\n *\t2^n-1 in the range 1..32767]\n * @NL80211_TXQ_ATTR_CWMAX: Maximum contention window [a value of the form\n *\t2^n-1 in the range 1..32767]\n * @NL80211_TXQ_ATTR_AIFS: Arbitration interframe space [0..255]\n * @__NL80211_TXQ_ATTR_AFTER_LAST: Internal\n * @NL80211_TXQ_ATTR_MAX: Maximum TXQ attribute number\n */\nenum nl80211_txq_attr {\n\t__NL80211_TXQ_ATTR_INVALID,\n\tNL80211_TXQ_ATTR_AC,\n\tNL80211_TXQ_ATTR_TXOP,\n\tNL80211_TXQ_ATTR_CWMIN,\n\tNL80211_TXQ_ATTR_CWMAX,\n\tNL80211_TXQ_ATTR_AIFS,\n\n\t/* keep last */\n\t__NL80211_TXQ_ATTR_AFTER_LAST,\n\tNL80211_TXQ_ATTR_MAX = __NL80211_TXQ_ATTR_AFTER_LAST - 1\n};\n\nenum nl80211_ac {\n\tNL80211_AC_VO,\n\tNL80211_AC_VI,\n\tNL80211_AC_BE,\n\tNL80211_AC_BK,\n\tNL80211_NUM_ACS\n};\n\n/* backward compat */\n#define NL80211_TXQ_ATTR_QUEUE\tNL80211_TXQ_ATTR_AC\n#define NL80211_TXQ_Q_VO\tNL80211_AC_VO\n#define NL80211_TXQ_Q_VI\tNL80211_AC_VI\n#define NL80211_TXQ_Q_BE\tNL80211_AC_BE\n#define NL80211_TXQ_Q_BK\tNL80211_AC_BK\n\n/**\n * enum nl80211_channel_type - channel type\n * @NL80211_CHAN_NO_HT: 20 MHz, non-HT channel\n * @NL80211_CHAN_HT20: 20 MHz HT channel\n * @NL80211_CHAN_HT40MINUS: HT40 channel, secondary channel\n *\tbelow the control channel\n * @NL80211_CHAN_HT40PLUS: HT40 channel, secondary channel\n *\tabove the control channel\n */\nenum nl80211_channel_type {\n\tNL80211_CHAN_NO_HT,\n\tNL80211_CHAN_HT20,\n\tNL80211_CHAN_HT40MINUS,\n\tNL80211_CHAN_HT40PLUS\n};\n\n/**\n * enum nl80211_chan_width - channel width definitions\n *\n * These values are used with the %NL80211_ATTR_CHANNEL_WIDTH\n * attribute.\n *\n * @NL80211_CHAN_WIDTH_20_NOHT: 20 MHz, non-HT channel\n * @NL80211_CHAN_WIDTH_20: 20 MHz HT channel\n * @NL80211_CHAN_WIDTH_40: 40 MHz channel, the %NL80211_ATTR_CENTER_FREQ1\n *\tattribute must be provided as well\n * @NL80211_CHAN_WIDTH_80: 80 MHz channel, the %NL80211_ATTR_CENTER_FREQ1\n *\tattribute must be provided as well\n * @NL80211_CHAN_WIDTH_80P80: 80+80 MHz channel, the %NL80211_ATTR_CENTER_FREQ1\n *\tand %NL80211_ATTR_CENTER_FREQ2 attributes must be provided as well\n * @NL80211_CHAN_WIDTH_160: 160 MHz channel, the %NL80211_ATTR_CENTER_FREQ1\n *\tattribute must be provided as well\n * @NL80211_CHAN_WIDTH_5: 5 MHz OFDM channel\n * @NL80211_CHAN_WIDTH_10: 10 MHz OFDM channel\n */\nenum nl80211_chan_width {\n\tNL80211_CHAN_WIDTH_20_NOHT,\n\tNL80211_CHAN_WIDTH_20,\n\tNL80211_CHAN_WIDTH_40,\n\tNL80211_CHAN_WIDTH_80,\n\tNL80211_CHAN_WIDTH_80P80,\n\tNL80211_CHAN_WIDTH_160,\n\tNL80211_CHAN_WIDTH_5,\n\tNL80211_CHAN_WIDTH_10,\n};\n\n/**\n * enum nl80211_bss_scan_width - control channel width for a BSS\n *\n * These values are used with the %NL80211_BSS_CHAN_WIDTH attribute.\n *\n * @NL80211_BSS_CHAN_WIDTH_20: control channel is 20 MHz wide or compatible\n * @NL80211_BSS_CHAN_WIDTH_10: control channel is 10 MHz wide\n * @NL80211_BSS_CHAN_WIDTH_5: control channel is 5 MHz wide\n */\nenum nl80211_bss_scan_width {\n\tNL80211_BSS_CHAN_WIDTH_20,\n\tNL80211_BSS_CHAN_WIDTH_10,\n\tNL80211_BSS_CHAN_WIDTH_5,\n};\n\n/**\n * enum nl80211_bss - netlink attributes for a BSS\n *\n * @__NL80211_BSS_INVALID: invalid\n * @NL80211_BSS_BSSID: BSSID of the BSS (6 octets)\n * @NL80211_BSS_FREQUENCY: frequency in MHz (u32)\n * @NL80211_BSS_TSF: TSF of the received probe response/beacon (u64)\n *\t(if @NL80211_BSS_PRESP_DATA is present then this is known to be\n *\tfrom a probe response, otherwise it may be from the same beacon\n *\tthat the NL80211_BSS_BEACON_TSF will be from)\n * @NL80211_BSS_BEACON_INTERVAL: beacon interval of the (I)BSS (u16)\n * @NL80211_BSS_CAPABILITY: capability field (CPU order, u16)\n * @NL80211_BSS_INFORMATION_ELEMENTS: binary attribute containing the\n *\traw information elements from the probe response/beacon (bin);\n *\tif the %NL80211_BSS_BEACON_IES attribute is present and the data is\n *\tdifferent then the IEs here are from a Probe Response frame; otherwise\n *\tthey are from a Beacon frame.\n *\tHowever, if the driver does not indicate the source of the IEs, these\n *\tIEs may be from either frame subtype.\n *\tIf present, the @NL80211_BSS_PRESP_DATA attribute indicates that the\n *\tdata here is known to be from a probe response, without any heuristics.\n * @NL80211_BSS_SIGNAL_MBM: signal strength of probe response/beacon\n *\tin mBm (100 * dBm) (s32)\n * @NL80211_BSS_SIGNAL_UNSPEC: signal strength of the probe response/beacon\n *\tin unspecified units, scaled to 0..100 (u8)\n * @NL80211_BSS_STATUS: status, if this BSS is \"used\"\n * @NL80211_BSS_SEEN_MS_AGO: age of this BSS entry in ms\n * @NL80211_BSS_BEACON_IES: binary attribute containing the raw information\n *\telements from a Beacon frame (bin); not present if no Beacon frame has\n *\tyet been received\n * @NL80211_BSS_CHAN_WIDTH: channel width of the control channel\n *\t(u32, enum nl80211_bss_scan_width)\n * @NL80211_BSS_BEACON_TSF: TSF of the last received beacon (u64)\n *\t(not present if no beacon frame has been received yet)\n * @NL80211_BSS_PRESP_DATA: the data in @NL80211_BSS_INFORMATION_ELEMENTS and\n *\t@NL80211_BSS_TSF is known to be from a probe response (flag attribute)\n * @NL80211_BSS_LAST_SEEN_BOOTTIME: CLOCK_BOOTTIME timestamp when this entry\n *\twas last updated by a received frame. The value is expected to be\n *\taccurate to about 10ms. (u64, nanoseconds)\n * @NL80211_BSS_PAD: attribute used for padding for 64-bit alignment\n * @NL80211_BSS_PARENT_TSF: the time at the start of reception of the first\n *\toctet of the timestamp field of the last beacon/probe received for\n *\tthis BSS. The time is the TSF of the BSS specified by\n *\t@NL80211_BSS_PARENT_BSSID. (u64).\n * @NL80211_BSS_PARENT_BSSID: the BSS according to which @NL80211_BSS_PARENT_TSF\n *\tis set.\n * @__NL80211_BSS_AFTER_LAST: internal\n * @NL80211_BSS_MAX: highest BSS attribute\n */\nenum nl80211_bss {\n\t__NL80211_BSS_INVALID,\n\tNL80211_BSS_BSSID,\n\tNL80211_BSS_FREQUENCY,\n\tNL80211_BSS_TSF,\n\tNL80211_BSS_BEACON_INTERVAL,\n\tNL80211_BSS_CAPABILITY,\n\tNL80211_BSS_INFORMATION_ELEMENTS,\n\tNL80211_BSS_SIGNAL_MBM,\n\tNL80211_BSS_SIGNAL_UNSPEC,\n\tNL80211_BSS_STATUS,\n\tNL80211_BSS_SEEN_MS_AGO,\n\tNL80211_BSS_BEACON_IES,\n\tNL80211_BSS_CHAN_WIDTH,\n\tNL80211_BSS_BEACON_TSF,\n\tNL80211_BSS_PRESP_DATA,\n\tNL80211_BSS_LAST_SEEN_BOOTTIME,\n\tNL80211_BSS_PAD,\n\tNL80211_BSS_PARENT_TSF,\n\tNL80211_BSS_PARENT_BSSID,\n\n\t/* keep last */\n\t__NL80211_BSS_AFTER_LAST,\n\tNL80211_BSS_MAX = __NL80211_BSS_AFTER_LAST - 1\n};\n\n/**\n * enum nl80211_bss_status - BSS \"status\"\n * @NL80211_BSS_STATUS_AUTHENTICATED: Authenticated with this BSS.\n *\tNote that this is no longer used since cfg80211 no longer\n *\tkeeps track of whether or not authentication was done with\n *\ta given BSS.\n * @NL80211_BSS_STATUS_ASSOCIATED: Associated with this BSS.\n * @NL80211_BSS_STATUS_IBSS_JOINED: Joined to this IBSS.\n *\n * The BSS status is a BSS attribute in scan dumps, which\n * indicates the status the interface has wrt. this BSS.\n */\nenum nl80211_bss_status {\n\tNL80211_BSS_STATUS_AUTHENTICATED,\n\tNL80211_BSS_STATUS_ASSOCIATED,\n\tNL80211_BSS_STATUS_IBSS_JOINED,\n};\n\n/**\n * enum nl80211_auth_type - AuthenticationType\n *\n * @NL80211_AUTHTYPE_OPEN_SYSTEM: Open System authentication\n * @NL80211_AUTHTYPE_SHARED_KEY: Shared Key authentication (WEP only)\n * @NL80211_AUTHTYPE_FT: Fast BSS Transition (IEEE 802.11r)\n * @NL80211_AUTHTYPE_NETWORK_EAP: Network EAP (some Cisco APs and mainly LEAP)\n * @NL80211_AUTHTYPE_SAE: Simultaneous authentication of equals\n * @NL80211_AUTHTYPE_FILS_SK: Fast Initial Link Setup shared key\n * @NL80211_AUTHTYPE_FILS_SK_PFS: Fast Initial Link Setup shared key with PFS\n * @NL80211_AUTHTYPE_FILS_PK: Fast Initial Link Setup public key\n * @__NL80211_AUTHTYPE_NUM: internal\n * @NL80211_AUTHTYPE_MAX: maximum valid auth algorithm\n * @NL80211_AUTHTYPE_AUTOMATIC: determine automatically (if necessary by\n *\ttrying multiple times); this is invalid in netlink -- leave out\n *\tthe attribute for this on CONNECT commands.\n */\nenum nl80211_auth_type {\n\tNL80211_AUTHTYPE_OPEN_SYSTEM,\n\tNL80211_AUTHTYPE_SHARED_KEY,\n\tNL80211_AUTHTYPE_FT,\n\tNL80211_AUTHTYPE_NETWORK_EAP,\n\tNL80211_AUTHTYPE_SAE,\n\tNL80211_AUTHTYPE_FILS_SK,\n\tNL80211_AUTHTYPE_FILS_SK_PFS,\n\tNL80211_AUTHTYPE_FILS_PK,\n\n\t/* keep last */\n\t__NL80211_AUTHTYPE_NUM,\n\tNL80211_AUTHTYPE_MAX = __NL80211_AUTHTYPE_NUM - 1,\n\tNL80211_AUTHTYPE_AUTOMATIC\n};\n\n/**\n * enum nl80211_key_type - Key Type\n * @NL80211_KEYTYPE_GROUP: Group (broadcast/multicast) key\n * @NL80211_KEYTYPE_PAIRWISE: Pairwise (unicast/individual) key\n * @NL80211_KEYTYPE_PEERKEY: PeerKey (DLS)\n * @NUM_NL80211_KEYTYPES: number of defined key types\n */\nenum nl80211_key_type {\n\tNL80211_KEYTYPE_GROUP,\n\tNL80211_KEYTYPE_PAIRWISE,\n\tNL80211_KEYTYPE_PEERKEY,\n\n\tNUM_NL80211_KEYTYPES\n};\n\n/**\n * enum nl80211_mfp - Management frame protection state\n * @NL80211_MFP_NO: Management frame protection not used\n * @NL80211_MFP_REQUIRED: Management frame protection required\n */\nenum nl80211_mfp {\n\tNL80211_MFP_NO,\n\tNL80211_MFP_REQUIRED,\n};\n\nenum nl80211_wpa_versions {\n\tNL80211_WPA_VERSION_1 = 1 << 0,\n\tNL80211_WPA_VERSION_2 = 1 << 1,\n};\n\n/**\n * enum nl80211_key_default_types - key default types\n * @__NL80211_KEY_DEFAULT_TYPE_INVALID: invalid\n * @NL80211_KEY_DEFAULT_TYPE_UNICAST: key should be used as default\n *\tunicast key\n * @NL80211_KEY_DEFAULT_TYPE_MULTICAST: key should be used as default\n *\tmulticast key\n * @NUM_NL80211_KEY_DEFAULT_TYPES: number of default types\n */\nenum nl80211_key_default_types {\n\t__NL80211_KEY_DEFAULT_TYPE_INVALID,\n\tNL80211_KEY_DEFAULT_TYPE_UNICAST,\n\tNL80211_KEY_DEFAULT_TYPE_MULTICAST,\n\n\tNUM_NL80211_KEY_DEFAULT_TYPES\n};\n\n/**\n * enum nl80211_key_attributes - key attributes\n * @__NL80211_KEY_INVALID: invalid\n * @NL80211_KEY_DATA: (temporal) key data; for TKIP this consists of\n *\t16 bytes encryption key followed by 8 bytes each for TX and RX MIC\n *\tkeys\n * @NL80211_KEY_IDX: key ID (u8, 0-3)\n * @NL80211_KEY_CIPHER: key cipher suite (u32, as defined by IEEE 802.11\n *\tsection 7.3.2.25.1, e.g. 0x000FAC04)\n * @NL80211_KEY_SEQ: transmit key sequence number (IV/PN) for TKIP and\n *\tCCMP keys, each six bytes in little endian\n * @NL80211_KEY_DEFAULT: flag indicating default key\n * @NL80211_KEY_DEFAULT_MGMT: flag indicating default management key\n * @NL80211_KEY_TYPE: the key type from enum nl80211_key_type, if not\n *\tspecified the default depends on whether a MAC address was\n *\tgiven with the command using the key or not (u32)\n * @NL80211_KEY_DEFAULT_TYPES: A nested attribute containing flags\n *\tattributes, specifying what a key should be set as default as.\n *\tSee &enum nl80211_key_default_types.\n * @__NL80211_KEY_AFTER_LAST: internal\n * @NL80211_KEY_MAX: highest key attribute\n */\nenum nl80211_key_attributes {\n\t__NL80211_KEY_INVALID,\n\tNL80211_KEY_DATA,\n\tNL80211_KEY_IDX,\n\tNL80211_KEY_CIPHER,\n\tNL80211_KEY_SEQ,\n\tNL80211_KEY_DEFAULT,\n\tNL80211_KEY_DEFAULT_MGMT,\n\tNL80211_KEY_TYPE,\n\tNL80211_KEY_DEFAULT_TYPES,\n\n\t/* keep last */\n\t__NL80211_KEY_AFTER_LAST,\n\tNL80211_KEY_MAX = __NL80211_KEY_AFTER_LAST - 1\n};\n\n/**\n * enum nl80211_tx_rate_attributes - TX rate set attributes\n * @__NL80211_TXRATE_INVALID: invalid\n * @NL80211_TXRATE_LEGACY: Legacy (non-MCS) rates allowed for TX rate selection\n *\tin an array of rates as defined in IEEE 802.11 7.3.2.2 (u8 values with\n *\t1 = 500 kbps) but without the IE length restriction (at most\n *\t%NL80211_MAX_SUPP_RATES in a single array).\n * @NL80211_TXRATE_HT: HT (MCS) rates allowed for TX rate selection\n *\tin an array of MCS numbers.\n * @NL80211_TXRATE_VHT: VHT rates allowed for TX rate selection,\n *\tsee &struct nl80211_txrate_vht\n * @NL80211_TXRATE_GI: configure GI, see &enum nl80211_txrate_gi\n * @__NL80211_TXRATE_AFTER_LAST: internal\n * @NL80211_TXRATE_MAX: highest TX rate attribute\n */\nenum nl80211_tx_rate_attributes {\n\t__NL80211_TXRATE_INVALID,\n\tNL80211_TXRATE_LEGACY,\n\tNL80211_TXRATE_HT,\n\tNL80211_TXRATE_VHT,\n\tNL80211_TXRATE_GI,\n\n\t/* keep last */\n\t__NL80211_TXRATE_AFTER_LAST,\n\tNL80211_TXRATE_MAX = __NL80211_TXRATE_AFTER_LAST - 1\n};\n\n#define NL80211_TXRATE_MCS NL80211_TXRATE_HT\n#define NL80211_VHT_NSS_MAX\t\t8\n\n/**\n * struct nl80211_txrate_vht - VHT MCS/NSS txrate bitmap\n * @mcs: MCS bitmap table for each NSS (array index 0 for 1 stream, etc.)\n */\nstruct nl80211_txrate_vht {\n\t__u16 mcs[NL80211_VHT_NSS_MAX];\n};\n\nenum nl80211_txrate_gi {\n\tNL80211_TXRATE_DEFAULT_GI,\n\tNL80211_TXRATE_FORCE_SGI,\n\tNL80211_TXRATE_FORCE_LGI,\n};\n\n/**\n * enum nl80211_band - Frequency band\n * @NL80211_BAND_2GHZ: 2.4 GHz ISM band\n * @NL80211_BAND_5GHZ: around 5 GHz band (4.9 - 5.7 GHz)\n * @NL80211_BAND_60GHZ: around 60 GHz band (58.32 - 64.80 GHz)\n * @NUM_NL80211_BANDS: number of bands, avoid using this in userspace\n *\tsince newer kernel versions may support more bands\n */\nenum nl80211_band {\n\tNL80211_BAND_2GHZ,\n\tNL80211_BAND_5GHZ,\n\tNL80211_BAND_60GHZ,\n\n\tNUM_NL80211_BANDS,\n};\n\n/**\n * enum nl80211_ps_state - powersave state\n * @NL80211_PS_DISABLED: powersave is disabled\n * @NL80211_PS_ENABLED: powersave is enabled\n */\nenum nl80211_ps_state {\n\tNL80211_PS_DISABLED,\n\tNL80211_PS_ENABLED,\n};\n\n/**\n * enum nl80211_attr_cqm - connection quality monitor attributes\n * @__NL80211_ATTR_CQM_INVALID: invalid\n * @NL80211_ATTR_CQM_RSSI_THOLD: RSSI threshold in dBm. This value specifies\n *\tthe threshold for the RSSI level at which an event will be sent. Zero\n *\tto disable.  Alternatively, if %NL80211_EXT_FEATURE_CQM_RSSI_LIST is\n *\tset, multiple values can be supplied as a low-to-high sorted array of\n *\tthreshold values in dBm.  Events will be sent when the RSSI value\n *\tcrosses any of the thresholds.\n * @NL80211_ATTR_CQM_RSSI_HYST: RSSI hysteresis in dBm. This value specifies\n *\tthe minimum amount the RSSI level must change after an event before a\n *\tnew event may be issued (to reduce effects of RSSI oscillation).\n * @NL80211_ATTR_CQM_RSSI_THRESHOLD_EVENT: RSSI threshold event\n * @NL80211_ATTR_CQM_PKT_LOSS_EVENT: a u32 value indicating that this many\n *\tconsecutive packets were not acknowledged by the peer\n * @NL80211_ATTR_CQM_TXE_RATE: TX error rate in %. Minimum % of TX failures\n *\tduring the given %NL80211_ATTR_CQM_TXE_INTVL before an\n *\t%NL80211_CMD_NOTIFY_CQM with reported %NL80211_ATTR_CQM_TXE_RATE and\n *\t%NL80211_ATTR_CQM_TXE_PKTS is generated.\n * @NL80211_ATTR_CQM_TXE_PKTS: number of attempted packets in a given\n *\t%NL80211_ATTR_CQM_TXE_INTVL before %NL80211_ATTR_CQM_TXE_RATE is\n *\tchecked.\n * @NL80211_ATTR_CQM_TXE_INTVL: interval in seconds. Specifies the periodic\n *\tinterval in which %NL80211_ATTR_CQM_TXE_PKTS and\n *\t%NL80211_ATTR_CQM_TXE_RATE must be satisfied before generating an\n *\t%NL80211_CMD_NOTIFY_CQM. Set to 0 to turn off TX error reporting.\n * @NL80211_ATTR_CQM_BEACON_LOSS_EVENT: flag attribute that's set in a beacon\n *\tloss event\n * @NL80211_ATTR_CQM_RSSI_LEVEL: the RSSI value in dBm that triggered the\n *\tRSSI threshold event.\n * @__NL80211_ATTR_CQM_AFTER_LAST: internal\n * @NL80211_ATTR_CQM_MAX: highest key attribute\n */\nenum nl80211_attr_cqm {\n\t__NL80211_ATTR_CQM_INVALID,\n\tNL80211_ATTR_CQM_RSSI_THOLD,\n\tNL80211_ATTR_CQM_RSSI_HYST,\n\tNL80211_ATTR_CQM_RSSI_THRESHOLD_EVENT,\n\tNL80211_ATTR_CQM_PKT_LOSS_EVENT,\n\tNL80211_ATTR_CQM_TXE_RATE,\n\tNL80211_ATTR_CQM_TXE_PKTS,\n\tNL80211_ATTR_CQM_TXE_INTVL,\n\tNL80211_ATTR_CQM_BEACON_LOSS_EVENT,\n\tNL80211_ATTR_CQM_RSSI_LEVEL,\n\n\t/* keep last */\n\t__NL80211_ATTR_CQM_AFTER_LAST,\n\tNL80211_ATTR_CQM_MAX = __NL80211_ATTR_CQM_AFTER_LAST - 1\n};\n\n/**\n * enum nl80211_cqm_rssi_threshold_event - RSSI threshold event\n * @NL80211_CQM_RSSI_THRESHOLD_EVENT_LOW: The RSSI level is lower than the\n *      configured threshold\n * @NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH: The RSSI is higher than the\n *      configured threshold\n * @NL80211_CQM_RSSI_BEACON_LOSS_EVENT: (reserved, never sent)\n */\nenum nl80211_cqm_rssi_threshold_event {\n\tNL80211_CQM_RSSI_THRESHOLD_EVENT_LOW,\n\tNL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH,\n\tNL80211_CQM_RSSI_BEACON_LOSS_EVENT,\n};\n\n\n/**\n * enum nl80211_tx_power_setting - TX power adjustment\n * @NL80211_TX_POWER_AUTOMATIC: automatically determine transmit power\n * @NL80211_TX_POWER_LIMITED: limit TX power by the mBm parameter\n * @NL80211_TX_POWER_FIXED: fix TX power to the mBm parameter\n */\nenum nl80211_tx_power_setting {\n\tNL80211_TX_POWER_AUTOMATIC,\n\tNL80211_TX_POWER_LIMITED,\n\tNL80211_TX_POWER_FIXED,\n};\n\n/**\n * enum nl80211_packet_pattern_attr - packet pattern attribute\n * @__NL80211_PKTPAT_INVALID: invalid number for nested attribute\n * @NL80211_PKTPAT_PATTERN: the pattern, values where the mask has\n *\ta zero bit are ignored\n * @NL80211_PKTPAT_MASK: pattern mask, must be long enough to have\n *\ta bit for each byte in the pattern. The lowest-order bit corresponds\n *\tto the first byte of the pattern, but the bytes of the pattern are\n *\tin a little-endian-like format, i.e. the 9th byte of the pattern\n *\tcorresponds to the lowest-order bit in the second byte of the mask.\n *\tFor example: The match 00:xx:00:00:xx:00:00:00:00:xx:xx:xx (where\n *\txx indicates \"don't care\") would be represented by a pattern of\n *\ttwelve zero bytes, and a mask of \"0xed,0x01\".\n *\tNote that the pattern matching is done as though frames were not\n *\t802.11 frames but 802.3 frames, i.e. the frame is fully unpacked\n *\tfirst (including SNAP header unpacking) and then matched.\n * @NL80211_PKTPAT_OFFSET: packet offset, pattern is matched after\n *\tthese fixed number of bytes of received packet\n * @NUM_NL80211_PKTPAT: number of attributes\n * @MAX_NL80211_PKTPAT: max attribute number\n */\nenum nl80211_packet_pattern_attr {\n\t__NL80211_PKTPAT_INVALID,\n\tNL80211_PKTPAT_MASK,\n\tNL80211_PKTPAT_PATTERN,\n\tNL80211_PKTPAT_OFFSET,\n\n\tNUM_NL80211_PKTPAT,\n\tMAX_NL80211_PKTPAT = NUM_NL80211_PKTPAT - 1,\n};\n\n/**\n * struct nl80211_pattern_support - packet pattern support information\n * @max_patterns: maximum number of patterns supported\n * @min_pattern_len: minimum length of each pattern\n * @max_pattern_len: maximum length of each pattern\n * @max_pkt_offset: maximum Rx packet offset\n *\n * This struct is carried in %NL80211_WOWLAN_TRIG_PKT_PATTERN when\n * that is part of %NL80211_ATTR_WOWLAN_TRIGGERS_SUPPORTED or in\n * %NL80211_ATTR_COALESCE_RULE_PKT_PATTERN when that is part of\n * %NL80211_ATTR_COALESCE_RULE in the capability information given\n * by the kernel to userspace.\n */\nstruct nl80211_pattern_support {\n\t__u32 max_patterns;\n\t__u32 min_pattern_len;\n\t__u32 max_pattern_len;\n\t__u32 max_pkt_offset;\n} __attribute__((packed));\n\n/* only for backward compatibility */\n#define __NL80211_WOWLAN_PKTPAT_INVALID __NL80211_PKTPAT_INVALID\n#define NL80211_WOWLAN_PKTPAT_MASK NL80211_PKTPAT_MASK\n#define NL80211_WOWLAN_PKTPAT_PATTERN NL80211_PKTPAT_PATTERN\n#define NL80211_WOWLAN_PKTPAT_OFFSET NL80211_PKTPAT_OFFSET\n#define NUM_NL80211_WOWLAN_PKTPAT NUM_NL80211_PKTPAT\n#define MAX_NL80211_WOWLAN_PKTPAT MAX_NL80211_PKTPAT\n#define nl80211_wowlan_pattern_support nl80211_pattern_support\n\n/**\n * enum nl80211_wowlan_triggers - WoWLAN trigger definitions\n * @__NL80211_WOWLAN_TRIG_INVALID: invalid number for nested attributes\n * @NL80211_WOWLAN_TRIG_ANY: wake up on any activity, do not really put\n *\tthe chip into a special state -- works best with chips that have\n *\tsupport for low-power operation already (flag)\n *\tNote that this mode is incompatible with all of the others, if\n *\tany others are even supported by the device.\n * @NL80211_WOWLAN_TRIG_DISCONNECT: wake up on disconnect, the way disconnect\n *\tis detected is implementation-specific (flag)\n * @NL80211_WOWLAN_TRIG_MAGIC_PKT: wake up on magic packet (6x 0xff, followed\n *\tby 16 repetitions of MAC addr, anywhere in payload) (flag)\n * @NL80211_WOWLAN_TRIG_PKT_PATTERN: wake up on the specified packet patterns\n *\twhich are passed in an array of nested attributes, each nested attribute\n *\tdefining a with attributes from &struct nl80211_wowlan_trig_pkt_pattern.\n *\tEach pattern defines a wakeup packet. Packet offset is associated with\n *\teach pattern which is used while matching the pattern. The matching is\n *\tdone on the MSDU, i.e. as though the packet was an 802.3 packet, so the\n *\tpattern matching is done after the packet is converted to the MSDU.\n *\n *\tIn %NL80211_ATTR_WOWLAN_TRIGGERS_SUPPORTED, it is a binary attribute\n *\tcarrying a &struct nl80211_pattern_support.\n *\n *\tWhen reporting wakeup. it is a u32 attribute containing the 0-based\n *\tindex of the pattern that caused the wakeup, in the patterns passed\n *\tto the kernel when configuring.\n * @NL80211_WOWLAN_TRIG_GTK_REKEY_SUPPORTED: Not a real trigger, and cannot be\n *\tused when setting, used only to indicate that GTK rekeying is supported\n *\tby the device (flag)\n * @NL80211_WOWLAN_TRIG_GTK_REKEY_FAILURE: wake up on GTK rekey failure (if\n *\tdone by the device) (flag)\n * @NL80211_WOWLAN_TRIG_EAP_IDENT_REQUEST: wake up on EAP Identity Request\n *\tpacket (flag)\n * @NL80211_WOWLAN_TRIG_4WAY_HANDSHAKE: wake up on 4-way handshake (flag)\n * @NL80211_WOWLAN_TRIG_RFKILL_RELEASE: wake up when rfkill is released\n *\t(on devices that have rfkill in the device) (flag)\n * @NL80211_WOWLAN_TRIG_WAKEUP_PKT_80211: For wakeup reporting only, contains\n *\tthe 802.11 packet that caused the wakeup, e.g. a deauth frame. The frame\n *\tmay be truncated, the @NL80211_WOWLAN_TRIG_WAKEUP_PKT_80211_LEN\n *\tattribute contains the original length.\n * @NL80211_WOWLAN_TRIG_WAKEUP_PKT_80211_LEN: Original length of the 802.11\n *\tpacket, may be bigger than the @NL80211_WOWLAN_TRIG_WAKEUP_PKT_80211\n *\tattribute if the packet was truncated somewhere.\n * @NL80211_WOWLAN_TRIG_WAKEUP_PKT_8023: For wakeup reporting only, contains the\n *\t802.11 packet that caused the wakeup, e.g. a magic packet. The frame may\n *\tbe truncated, the @NL80211_WOWLAN_TRIG_WAKEUP_PKT_8023_LEN attribute\n *\tcontains the original length.\n * @NL80211_WOWLAN_TRIG_WAKEUP_PKT_8023_LEN: Original length of the 802.3\n *\tpacket, may be bigger than the @NL80211_WOWLAN_TRIG_WAKEUP_PKT_8023\n *\tattribute if the packet was truncated somewhere.\n * @NL80211_WOWLAN_TRIG_TCP_CONNECTION: TCP connection wake, see DOC section\n *\t\"TCP connection wakeup\" for more details. This is a nested attribute\n *\tcontaining the exact information for establishing and keeping alive\n *\tthe TCP connection.\n * @NL80211_WOWLAN_TRIG_TCP_WAKEUP_MATCH: For wakeup reporting only, the\n *\twakeup packet was received on the TCP connection\n * @NL80211_WOWLAN_TRIG_WAKEUP_TCP_CONNLOST: For wakeup reporting only, the\n *\tTCP connection was lost or failed to be established\n * @NL80211_WOWLAN_TRIG_WAKEUP_TCP_NOMORETOKENS: For wakeup reporting only,\n *\tthe TCP connection ran out of tokens to use for data to send to the\n *\tservice\n * @NL80211_WOWLAN_TRIG_NET_DETECT: wake up when a configured network\n *\tis detected.  This is a nested attribute that contains the\n *\tsame attributes used with @NL80211_CMD_START_SCHED_SCAN.  It\n *\tspecifies how the scan is performed (e.g. the interval, the\n *\tchannels to scan and the initial delay) as well as the scan\n *\tresults that will trigger a wake (i.e. the matchsets).  This\n *\tattribute is also sent in a response to\n *\t@NL80211_CMD_GET_WIPHY, indicating the number of match sets\n *\tsupported by the driver (u32).\n * @NL80211_WOWLAN_TRIG_NET_DETECT_RESULTS: nested attribute\n *\tcontaining an array with information about what triggered the\n *\twake up.  If no elements are present in the array, it means\n *\tthat the information is not available.  If more than one\n *\telement is present, it means that more than one match\n *\toccurred.\n *\tEach element in the array is a nested attribute that contains\n *\tone optional %NL80211_ATTR_SSID attribute and one optional\n *\t%NL80211_ATTR_SCAN_FREQUENCIES attribute.  At least one of\n *\tthese attributes must be present.  If\n *\t%NL80211_ATTR_SCAN_FREQUENCIES contains more than one\n *\tfrequency, it means that the match occurred in more than one\n *\tchannel.\n * @NUM_NL80211_WOWLAN_TRIG: number of wake on wireless triggers\n * @MAX_NL80211_WOWLAN_TRIG: highest wowlan trigger attribute number\n *\n * These nested attributes are used to configure the wakeup triggers and\n * to report the wakeup reason(s).\n */\nenum nl80211_wowlan_triggers {\n\t__NL80211_WOWLAN_TRIG_INVALID,\n\tNL80211_WOWLAN_TRIG_ANY,\n\tNL80211_WOWLAN_TRIG_DISCONNECT,\n\tNL80211_WOWLAN_TRIG_MAGIC_PKT,\n\tNL80211_WOWLAN_TRIG_PKT_PATTERN,\n\tNL80211_WOWLAN_TRIG_GTK_REKEY_SUPPORTED,\n\tNL80211_WOWLAN_TRIG_GTK_REKEY_FAILURE,\n\tNL80211_WOWLAN_TRIG_EAP_IDENT_REQUEST,\n\tNL80211_WOWLAN_TRIG_4WAY_HANDSHAKE,\n\tNL80211_WOWLAN_TRIG_RFKILL_RELEASE,\n\tNL80211_WOWLAN_TRIG_WAKEUP_PKT_80211,\n\tNL80211_WOWLAN_TRIG_WAKEUP_PKT_80211_LEN,\n\tNL80211_WOWLAN_TRIG_WAKEUP_PKT_8023,\n\tNL80211_WOWLAN_TRIG_WAKEUP_PKT_8023_LEN,\n\tNL80211_WOWLAN_TRIG_TCP_CONNECTION,\n\tNL80211_WOWLAN_TRIG_WAKEUP_TCP_MATCH,\n\tNL80211_WOWLAN_TRIG_WAKEUP_TCP_CONNLOST,\n\tNL80211_WOWLAN_TRIG_WAKEUP_TCP_NOMORETOKENS,\n\tNL80211_WOWLAN_TRIG_NET_DETECT,\n\tNL80211_WOWLAN_TRIG_NET_DETECT_RESULTS,\n\n\t/* keep last */\n\tNUM_NL80211_WOWLAN_TRIG,\n\tMAX_NL80211_WOWLAN_TRIG = NUM_NL80211_WOWLAN_TRIG - 1\n};\n\n/**\n * DOC: TCP connection wakeup\n *\n * Some devices can establish a TCP connection in order to be woken up by a\n * packet coming in from outside their network segment, or behind NAT. If\n * configured, the device will establish a TCP connection to the given\n * service, and periodically send data to that service. The first data\n * packet is usually transmitted after SYN/ACK, also ACKing the SYN/ACK.\n * The data packets can optionally include a (little endian) sequence\n * number (in the TCP payload!) that is generated by the device, and, also\n * optionally, a token from a list of tokens. This serves as a keep-alive\n * with the service, and for NATed connections, etc.\n *\n * During this keep-alive period, the server doesn't send any data to the\n * client. When receiving data, it is compared against the wakeup pattern\n * (and mask) and if it matches, the host is woken up. Similarly, if the\n * connection breaks or cannot be established to start with, the host is\n * also woken up.\n *\n * Developer's note: ARP offload is required for this, otherwise TCP\n * response packets might not go through correctly.\n */\n\n/**\n * struct nl80211_wowlan_tcp_data_seq - WoWLAN TCP data sequence\n * @start: starting value\n * @offset: offset of sequence number in packet\n * @len: length of the sequence value to write, 1 through 4\n *\n * Note: don't confuse with the TCP sequence number(s), this is for the\n * keepalive packet payload. The actual value is written into the packet\n * in little endian.\n */\nstruct nl80211_wowlan_tcp_data_seq {\n\t__u32 start, offset, len;\n};\n\n/**\n * struct nl80211_wowlan_tcp_data_token - WoWLAN TCP data token config\n * @offset: offset of token in packet\n * @len: length of each token\n * @token_stream: stream of data to be used for the tokens, the length must\n *\tbe a multiple of @len for this to make sense\n */\nstruct nl80211_wowlan_tcp_data_token {\n\t__u32 offset, len;\n\t__u8 token_stream[];\n};\n\n/**\n * struct nl80211_wowlan_tcp_data_token_feature - data token features\n * @min_len: minimum token length\n * @max_len: maximum token length\n * @bufsize: total available token buffer size (max size of @token_stream)\n */\nstruct nl80211_wowlan_tcp_data_token_feature {\n\t__u32 min_len, max_len, bufsize;\n};\n\n/**\n * enum nl80211_wowlan_tcp_attrs - WoWLAN TCP connection parameters\n * @__NL80211_WOWLAN_TCP_INVALID: invalid number for nested attributes\n * @NL80211_WOWLAN_TCP_SRC_IPV4: source IPv4 address (in network byte order)\n * @NL80211_WOWLAN_TCP_DST_IPV4: destination IPv4 address\n *\t(in network byte order)\n * @NL80211_WOWLAN_TCP_DST_MAC: destination MAC address, this is given because\n *\troute lookup when configured might be invalid by the time we suspend,\n *\tand doing a route lookup when suspending is no longer possible as it\n *\tmight require ARP querying.\n * @NL80211_WOWLAN_TCP_SRC_PORT: source port (u16); optional, if not given a\n *\tsocket and port will be allocated\n * @NL80211_WOWLAN_TCP_DST_PORT: destination port (u16)\n * @NL80211_WOWLAN_TCP_DATA_PAYLOAD: data packet payload, at least one byte.\n *\tFor feature advertising, a u32 attribute holding the maximum length\n *\tof the data payload.\n * @NL80211_WOWLAN_TCP_DATA_PAYLOAD_SEQ: data packet sequence configuration\n *\t(if desired), a &struct nl80211_wowlan_tcp_data_seq. For feature\n *\tadvertising it is just a flag\n * @NL80211_WOWLAN_TCP_DATA_PAYLOAD_TOKEN: data packet token configuration,\n *\tsee &struct nl80211_wowlan_tcp_data_token and for advertising see\n *\t&struct nl80211_wowlan_tcp_data_token_feature.\n * @NL80211_WOWLAN_TCP_DATA_INTERVAL: data interval in seconds, maximum\n *\tinterval in feature advertising (u32)\n * @NL80211_WOWLAN_TCP_WAKE_PAYLOAD: wake packet payload, for advertising a\n *\tu32 attribute holding the maximum length\n * @NL80211_WOWLAN_TCP_WAKE_MASK: Wake packet payload mask, not used for\n *\tfeature advertising. The mask works like @NL80211_PKTPAT_MASK\n *\tbut on the TCP payload only.\n * @NUM_NL80211_WOWLAN_TCP: number of TCP attributes\n * @MAX_NL80211_WOWLAN_TCP: highest attribute number\n */\nenum nl80211_wowlan_tcp_attrs {\n\t__NL80211_WOWLAN_TCP_INVALID,\n\tNL80211_WOWLAN_TCP_SRC_IPV4,\n\tNL80211_WOWLAN_TCP_DST_IPV4,\n\tNL80211_WOWLAN_TCP_DST_MAC,\n\tNL80211_WOWLAN_TCP_SRC_PORT,\n\tNL80211_WOWLAN_TCP_DST_PORT,\n\tNL80211_WOWLAN_TCP_DATA_PAYLOAD,\n\tNL80211_WOWLAN_TCP_DATA_PAYLOAD_SEQ,\n\tNL80211_WOWLAN_TCP_DATA_PAYLOAD_TOKEN,\n\tNL80211_WOWLAN_TCP_DATA_INTERVAL,\n\tNL80211_WOWLAN_TCP_WAKE_PAYLOAD,\n\tNL80211_WOWLAN_TCP_WAKE_MASK,\n\n\t/* keep last */\n\tNUM_NL80211_WOWLAN_TCP,\n\tMAX_NL80211_WOWLAN_TCP = NUM_NL80211_WOWLAN_TCP - 1\n};\n\n/**\n * struct nl80211_coalesce_rule_support - coalesce rule support information\n * @max_rules: maximum number of rules supported\n * @pat: packet pattern support information\n * @max_delay: maximum supported coalescing delay in msecs\n *\n * This struct is carried in %NL80211_ATTR_COALESCE_RULE in the\n * capability information given by the kernel to userspace.\n */\nstruct nl80211_coalesce_rule_support {\n\t__u32 max_rules;\n\tstruct nl80211_pattern_support pat;\n\t__u32 max_delay;\n} __attribute__((packed));\n\n/**\n * enum nl80211_attr_coalesce_rule - coalesce rule attribute\n * @__NL80211_COALESCE_RULE_INVALID: invalid number for nested attribute\n * @NL80211_ATTR_COALESCE_RULE_DELAY: delay in msecs used for packet coalescing\n * @NL80211_ATTR_COALESCE_RULE_CONDITION: condition for packet coalescence,\n *\tsee &enum nl80211_coalesce_condition.\n * @NL80211_ATTR_COALESCE_RULE_PKT_PATTERN: packet offset, pattern is matched\n *\tafter these fixed number of bytes of received packet\n * @NUM_NL80211_ATTR_COALESCE_RULE: number of attributes\n * @NL80211_ATTR_COALESCE_RULE_MAX: max attribute number\n */\nenum nl80211_attr_coalesce_rule {\n\t__NL80211_COALESCE_RULE_INVALID,\n\tNL80211_ATTR_COALESCE_RULE_DELAY,\n\tNL80211_ATTR_COALESCE_RULE_CONDITION,\n\tNL80211_ATTR_COALESCE_RULE_PKT_PATTERN,\n\n\t/* keep last */\n\tNUM_NL80211_ATTR_COALESCE_RULE,\n\tNL80211_ATTR_COALESCE_RULE_MAX = NUM_NL80211_ATTR_COALESCE_RULE - 1\n};\n\n/**\n * enum nl80211_coalesce_condition - coalesce rule conditions\n * @NL80211_COALESCE_CONDITION_MATCH: coalesce Rx packets when patterns\n *\tin a rule are matched.\n * @NL80211_COALESCE_CONDITION_NO_MATCH: coalesce Rx packets when patterns\n *\tin a rule are not matched.\n */\nenum nl80211_coalesce_condition {\n\tNL80211_COALESCE_CONDITION_MATCH,\n\tNL80211_COALESCE_CONDITION_NO_MATCH\n};\n\n/**\n * enum nl80211_iface_limit_attrs - limit attributes\n * @NL80211_IFACE_LIMIT_UNSPEC: (reserved)\n * @NL80211_IFACE_LIMIT_MAX: maximum number of interfaces that\n *\tcan be chosen from this set of interface types (u32)\n * @NL80211_IFACE_LIMIT_TYPES: nested attribute containing a\n *\tflag attribute for each interface type in this set\n * @NUM_NL80211_IFACE_LIMIT: number of attributes\n * @MAX_NL80211_IFACE_LIMIT: highest attribute number\n */\nenum nl80211_iface_limit_attrs {\n\tNL80211_IFACE_LIMIT_UNSPEC,\n\tNL80211_IFACE_LIMIT_MAX,\n\tNL80211_IFACE_LIMIT_TYPES,\n\n\t/* keep last */\n\tNUM_NL80211_IFACE_LIMIT,\n\tMAX_NL80211_IFACE_LIMIT = NUM_NL80211_IFACE_LIMIT - 1\n};\n\n/**\n * enum nl80211_if_combination_attrs -- interface combination attributes\n *\n * @NL80211_IFACE_COMB_UNSPEC: (reserved)\n * @NL80211_IFACE_COMB_LIMITS: Nested attributes containing the limits\n *\tfor given interface types, see &enum nl80211_iface_limit_attrs.\n * @NL80211_IFACE_COMB_MAXNUM: u32 attribute giving the total number of\n *\tinterfaces that can be created in this group. This number doesn't\n *\tapply to interfaces purely managed in software, which are listed\n *\tin a separate attribute %NL80211_ATTR_INTERFACES_SOFTWARE.\n * @NL80211_IFACE_COMB_STA_AP_BI_MATCH: flag attribute specifying that\n *\tbeacon intervals within this group must be all the same even for\n *\tinfrastructure and AP/GO combinations, i.e. the GO(s) must adopt\n *\tthe infrastructure network's beacon interval.\n * @NL80211_IFACE_COMB_NUM_CHANNELS: u32 attribute specifying how many\n *\tdifferent channels may be used within this group.\n * @NL80211_IFACE_COMB_RADAR_DETECT_WIDTHS: u32 attribute containing the bitmap\n *\tof supported channel widths for radar detection.\n * @NL80211_IFACE_COMB_RADAR_DETECT_REGIONS: u32 attribute containing the bitmap\n *\tof supported regulatory regions for radar detection.\n * @NL80211_IFACE_COMB_BI_MIN_GCD: u32 attribute specifying the minimum GCD of\n *\tdifferent beacon intervals supported by all the interface combinations\n *\tin this group (if not present, all beacon intervals be identical).\n * @NUM_NL80211_IFACE_COMB: number of attributes\n * @MAX_NL80211_IFACE_COMB: highest attribute number\n *\n * Examples:\n *\tlimits = [ #{STA} <= 1, #{AP} <= 1 ], matching BI, channels = 1, max = 2\n *\t=> allows an AP and a STA that must match BIs\n *\n *\tnumbers = [ #{AP, P2P-GO} <= 8 ], BI min gcd, channels = 1, max = 8,\n *\t=> allows 8 of AP/GO that can have BI gcd >= min gcd\n *\n *\tnumbers = [ #{STA} <= 2 ], channels = 2, max = 2\n *\t=> allows two STAs on different channels\n *\n *\tnumbers = [ #{STA} <= 1, #{P2P-client,P2P-GO} <= 3 ], max = 4\n *\t=> allows a STA plus three P2P interfaces\n *\n * The list of these four possibilities could completely be contained\n * within the %NL80211_ATTR_INTERFACE_COMBINATIONS attribute to indicate\n * that any of these groups must match.\n *\n * \"Combinations\" of just a single interface will not be listed here,\n * a single interface of any valid interface type is assumed to always\n * be possible by itself. This means that implicitly, for each valid\n * interface type, the following group always exists:\n *\tnumbers = [ #{<type>} <= 1 ], channels = 1, max = 1\n */\nenum nl80211_if_combination_attrs {\n\tNL80211_IFACE_COMB_UNSPEC,\n\tNL80211_IFACE_COMB_LIMITS,\n\tNL80211_IFACE_COMB_MAXNUM,\n\tNL80211_IFACE_COMB_STA_AP_BI_MATCH,\n\tNL80211_IFACE_COMB_NUM_CHANNELS,\n\tNL80211_IFACE_COMB_RADAR_DETECT_WIDTHS,\n\tNL80211_IFACE_COMB_RADAR_DETECT_REGIONS,\n\tNL80211_IFACE_COMB_BI_MIN_GCD,\n\n\t/* keep last */\n\tNUM_NL80211_IFACE_COMB,\n\tMAX_NL80211_IFACE_COMB = NUM_NL80211_IFACE_COMB - 1\n};\n\n\n/**\n * enum nl80211_plink_state - state of a mesh peer link finite state machine\n *\n * @NL80211_PLINK_LISTEN: initial state, considered the implicit\n *\tstate of non existent mesh peer links\n * @NL80211_PLINK_OPN_SNT: mesh plink open frame has been sent to\n *\tthis mesh peer\n * @NL80211_PLINK_OPN_RCVD: mesh plink open frame has been received\n *\tfrom this mesh peer\n * @NL80211_PLINK_CNF_RCVD: mesh plink confirm frame has been\n *\treceived from this mesh peer\n * @NL80211_PLINK_ESTAB: mesh peer link is established\n * @NL80211_PLINK_HOLDING: mesh peer link is being closed or cancelled\n * @NL80211_PLINK_BLOCKED: all frames transmitted from this mesh\n *\tplink are discarded\n * @NUM_NL80211_PLINK_STATES: number of peer link states\n * @MAX_NL80211_PLINK_STATES: highest numerical value of plink states\n */\nenum nl80211_plink_state {\n\tNL80211_PLINK_LISTEN,\n\tNL80211_PLINK_OPN_SNT,\n\tNL80211_PLINK_OPN_RCVD,\n\tNL80211_PLINK_CNF_RCVD,\n\tNL80211_PLINK_ESTAB,\n\tNL80211_PLINK_HOLDING,\n\tNL80211_PLINK_BLOCKED,\n\n\t/* keep last */\n\tNUM_NL80211_PLINK_STATES,\n\tMAX_NL80211_PLINK_STATES = NUM_NL80211_PLINK_STATES - 1\n};\n\n/**\n * enum nl80211_plink_action - actions to perform in mesh peers\n *\n * @NL80211_PLINK_ACTION_NO_ACTION: perform no action\n * @NL80211_PLINK_ACTION_OPEN: start mesh peer link establishment\n * @NL80211_PLINK_ACTION_BLOCK: block traffic from this mesh peer\n * @NUM_NL80211_PLINK_ACTIONS: number of possible actions\n */\nenum plink_actions {\n\tNL80211_PLINK_ACTION_NO_ACTION,\n\tNL80211_PLINK_ACTION_OPEN,\n\tNL80211_PLINK_ACTION_BLOCK,\n\n\tNUM_NL80211_PLINK_ACTIONS,\n};\n\n\n#define NL80211_KCK_LEN\t\t\t16\n#define NL80211_KEK_LEN\t\t\t16\n#define NL80211_REPLAY_CTR_LEN\t\t8\n\n/**\n * enum nl80211_rekey_data - attributes for GTK rekey offload\n * @__NL80211_REKEY_DATA_INVALID: invalid number for nested attributes\n * @NL80211_REKEY_DATA_KEK: key encryption key (binary)\n * @NL80211_REKEY_DATA_KCK: key confirmation key (binary)\n * @NL80211_REKEY_DATA_REPLAY_CTR: replay counter (binary)\n * @NUM_NL80211_REKEY_DATA: number of rekey attributes (internal)\n * @MAX_NL80211_REKEY_DATA: highest rekey attribute (internal)\n */\nenum nl80211_rekey_data {\n\t__NL80211_REKEY_DATA_INVALID,\n\tNL80211_REKEY_DATA_KEK,\n\tNL80211_REKEY_DATA_KCK,\n\tNL80211_REKEY_DATA_REPLAY_CTR,\n\n\t/* keep last */\n\tNUM_NL80211_REKEY_DATA,\n\tMAX_NL80211_REKEY_DATA = NUM_NL80211_REKEY_DATA - 1\n};\n\n/**\n * enum nl80211_hidden_ssid - values for %NL80211_ATTR_HIDDEN_SSID\n * @NL80211_HIDDEN_SSID_NOT_IN_USE: do not hide SSID (i.e., broadcast it in\n *\tBeacon frames)\n * @NL80211_HIDDEN_SSID_ZERO_LEN: hide SSID by using zero-length SSID element\n *\tin Beacon frames\n * @NL80211_HIDDEN_SSID_ZERO_CONTENTS: hide SSID by using correct length of SSID\n *\telement in Beacon frames but zero out each byte in the SSID\n */\nenum nl80211_hidden_ssid {\n\tNL80211_HIDDEN_SSID_NOT_IN_USE,\n\tNL80211_HIDDEN_SSID_ZERO_LEN,\n\tNL80211_HIDDEN_SSID_ZERO_CONTENTS\n};\n\n/**\n * enum nl80211_sta_wme_attr - station WME attributes\n * @__NL80211_STA_WME_INVALID: invalid number for nested attribute\n * @NL80211_STA_WME_UAPSD_QUEUES: bitmap of uapsd queues. the format\n *\tis the same as the AC bitmap in the QoS info field.\n * @NL80211_STA_WME_MAX_SP: max service period. the format is the same\n *\tas the MAX_SP field in the QoS info field (but already shifted down).\n * @__NL80211_STA_WME_AFTER_LAST: internal\n * @NL80211_STA_WME_MAX: highest station WME attribute\n */\nenum nl80211_sta_wme_attr {\n\t__NL80211_STA_WME_INVALID,\n\tNL80211_STA_WME_UAPSD_QUEUES,\n\tNL80211_STA_WME_MAX_SP,\n\n\t/* keep last */\n\t__NL80211_STA_WME_AFTER_LAST,\n\tNL80211_STA_WME_MAX = __NL80211_STA_WME_AFTER_LAST - 1\n};\n\n/**\n * enum nl80211_pmksa_candidate_attr - attributes for PMKSA caching candidates\n * @__NL80211_PMKSA_CANDIDATE_INVALID: invalid number for nested attributes\n * @NL80211_PMKSA_CANDIDATE_INDEX: candidate index (u32; the smaller, the higher\n *\tpriority)\n * @NL80211_PMKSA_CANDIDATE_BSSID: candidate BSSID (6 octets)\n * @NL80211_PMKSA_CANDIDATE_PREAUTH: RSN pre-authentication supported (flag)\n * @NUM_NL80211_PMKSA_CANDIDATE: number of PMKSA caching candidate attributes\n *\t(internal)\n * @MAX_NL80211_PMKSA_CANDIDATE: highest PMKSA caching candidate attribute\n *\t(internal)\n */\nenum nl80211_pmksa_candidate_attr {\n\t__NL80211_PMKSA_CANDIDATE_INVALID,\n\tNL80211_PMKSA_CANDIDATE_INDEX,\n\tNL80211_PMKSA_CANDIDATE_BSSID,\n\tNL80211_PMKSA_CANDIDATE_PREAUTH,\n\n\t/* keep last */\n\tNUM_NL80211_PMKSA_CANDIDATE,\n\tMAX_NL80211_PMKSA_CANDIDATE = NUM_NL80211_PMKSA_CANDIDATE - 1\n};\n\n/**\n * enum nl80211_tdls_operation - values for %NL80211_ATTR_TDLS_OPERATION\n * @NL80211_TDLS_DISCOVERY_REQ: Send a TDLS discovery request\n * @NL80211_TDLS_SETUP: Setup TDLS link\n * @NL80211_TDLS_TEARDOWN: Teardown a TDLS link which is already established\n * @NL80211_TDLS_ENABLE_LINK: Enable TDLS link\n * @NL80211_TDLS_DISABLE_LINK: Disable TDLS link\n */\nenum nl80211_tdls_operation {\n\tNL80211_TDLS_DISCOVERY_REQ,\n\tNL80211_TDLS_SETUP,\n\tNL80211_TDLS_TEARDOWN,\n\tNL80211_TDLS_ENABLE_LINK,\n\tNL80211_TDLS_DISABLE_LINK,\n};\n\n/*\n * enum nl80211_ap_sme_features - device-integrated AP features\n * Reserved for future use, no bits are defined in\n * NL80211_ATTR_DEVICE_AP_SME yet.\nenum nl80211_ap_sme_features {\n};\n */\n\n/**\n * enum nl80211_feature_flags - device/driver features\n * @NL80211_FEATURE_SK_TX_STATUS: This driver supports reflecting back\n *\tTX status to the socket error queue when requested with the\n *\tsocket option.\n * @NL80211_FEATURE_HT_IBSS: This driver supports IBSS with HT datarates.\n * @NL80211_FEATURE_INACTIVITY_TIMER: This driver takes care of freeing up\n *\tthe connected inactive stations in AP mode.\n * @NL80211_FEATURE_CELL_BASE_REG_HINTS: This driver has been tested\n *\tto work properly to support receiving regulatory hints from\n *\tcellular base stations.\n * @NL80211_FEATURE_P2P_DEVICE_NEEDS_CHANNEL: (no longer available, only\n *\there to reserve the value for API/ABI compatibility)\n * @NL80211_FEATURE_SAE: This driver supports simultaneous authentication of\n *\tequals (SAE) with user space SME (NL80211_CMD_AUTHENTICATE) in station\n *\tmode\n * @NL80211_FEATURE_LOW_PRIORITY_SCAN: This driver supports low priority scan\n * @NL80211_FEATURE_SCAN_FLUSH: Scan flush is supported\n * @NL80211_FEATURE_AP_SCAN: Support scanning using an AP vif\n * @NL80211_FEATURE_VIF_TXPOWER: The driver supports per-vif TX power setting\n * @NL80211_FEATURE_NEED_OBSS_SCAN: The driver expects userspace to perform\n *\tOBSS scans and generate 20/40 BSS coex reports. This flag is used only\n *\tfor drivers implementing the CONNECT API, for AUTH/ASSOC it is implied.\n * @NL80211_FEATURE_P2P_GO_CTWIN: P2P GO implementation supports CT Window\n *\tsetting\n * @NL80211_FEATURE_P2P_GO_OPPPS: P2P GO implementation supports opportunistic\n *\tpowersave\n * @NL80211_FEATURE_FULL_AP_CLIENT_STATE: The driver supports full state\n *\ttransitions for AP clients. Without this flag (and if the driver\n *\tdoesn't have the AP SME in the device) the driver supports adding\n *\tstations only when they're associated and adds them in associated\n *\tstate (to later be transitioned into authorized), with this flag\n *\tthey should be added before even sending the authentication reply\n *\tand then transitioned into authenticated, associated and authorized\n *\tstates using station flags.\n *\tNote that even for drivers that support this, the default is to add\n *\tstations in authenticated/associated state, so to add unauthenticated\n *\tstations the authenticated/associated bits have to be set in the mask.\n * @NL80211_FEATURE_ADVERTISE_CHAN_LIMITS: cfg80211 advertises channel limits\n *\t(HT40, VHT 80/160 MHz) if this flag is set\n * @NL80211_FEATURE_USERSPACE_MPM: This driver supports a userspace Mesh\n *\tPeering Management entity which may be implemented by registering for\n *\tbeacons or NL80211_CMD_NEW_PEER_CANDIDATE events. The mesh beacon is\n *\tstill generated by the driver.\n * @NL80211_FEATURE_ACTIVE_MONITOR: This driver supports an active monitor\n *\tinterface. An active monitor interface behaves like a normal monitor\n *\tinterface, but gets added to the driver. It ensures that incoming\n *\tunicast packets directed at the configured interface address get ACKed.\n * @NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE: This driver supports dynamic\n *\tchannel bandwidth change (e.g., HT 20 <-> 40 MHz channel) during the\n *\tlifetime of a BSS.\n * @NL80211_FEATURE_DS_PARAM_SET_IE_IN_PROBES: This device adds a DS Parameter\n *\tSet IE to probe requests.\n * @NL80211_FEATURE_WFA_TPC_IE_IN_PROBES: This device adds a WFA TPC Report IE\n *\tto probe requests.\n * @NL80211_FEATURE_QUIET: This device, in client mode, supports Quiet Period\n *\trequests sent to it by an AP.\n * @NL80211_FEATURE_TX_POWER_INSERTION: This device is capable of inserting the\n *\tcurrent tx power value into the TPC Report IE in the spectrum\n *\tmanagement TPC Report action frame, and in the Radio Measurement Link\n *\tMeasurement Report action frame.\n * @NL80211_FEATURE_ACKTO_ESTIMATION: This driver supports dynamic ACK timeout\n *\testimation (dynack). %NL80211_ATTR_WIPHY_DYN_ACK flag attribute is used\n *\tto enable dynack.\n * @NL80211_FEATURE_STATIC_SMPS: Device supports static spatial\n *\tmultiplexing powersave, ie. can turn off all but one chain\n *\teven on HT connections that should be using more chains.\n * @NL80211_FEATURE_DYNAMIC_SMPS: Device supports dynamic spatial\n *\tmultiplexing powersave, ie. can turn off all but one chain\n *\tand then wake the rest up as required after, for example,\n *\trts/cts handshake.\n * @NL80211_FEATURE_SUPPORTS_WMM_ADMISSION: the device supports setting up WMM\n *\tTSPEC sessions (TID aka TSID 0-7) with the %NL80211_CMD_ADD_TX_TS\n *\tcommand. Standard IEEE 802.11 TSPEC setup is not yet supported, it\n *\tneeds to be able to handle Block-Ack agreements and other things.\n * @NL80211_FEATURE_MAC_ON_CREATE: Device supports configuring\n *\tthe vif's MAC address upon creation.\n *\tSee 'macaddr' field in the vif_params (cfg80211.h).\n * @NL80211_FEATURE_TDLS_CHANNEL_SWITCH: Driver supports channel switching when\n *\toperating as a TDLS peer.\n * @NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR: This device/driver supports using a\n *\trandom MAC address during scan (if the device is unassociated); the\n *\t%NL80211_SCAN_FLAG_RANDOM_ADDR flag may be set for scans and the MAC\n *\taddress mask/value will be used.\n * @NL80211_FEATURE_SCHED_SCAN_RANDOM_MAC_ADDR: This device/driver supports\n *\tusing a random MAC address for every scan iteration during scheduled\n *\tscan (while not associated), the %NL80211_SCAN_FLAG_RANDOM_ADDR may\n *\tbe set for scheduled scan and the MAC address mask/value will be used.\n * @NL80211_FEATURE_ND_RANDOM_MAC_ADDR: This device/driver supports using a\n *\trandom MAC address for every scan iteration during \"net detect\", i.e.\n *\tscan in unassociated WoWLAN, the %NL80211_SCAN_FLAG_RANDOM_ADDR may\n *\tbe set for scheduled scan and the MAC address mask/value will be used.\n */\nenum nl80211_feature_flags {\n\tNL80211_FEATURE_SK_TX_STATUS\t\t\t= 1 << 0,\n\tNL80211_FEATURE_HT_IBSS\t\t\t\t= 1 << 1,\n\tNL80211_FEATURE_INACTIVITY_TIMER\t\t= 1 << 2,\n\tNL80211_FEATURE_CELL_BASE_REG_HINTS\t\t= 1 << 3,\n\tNL80211_FEATURE_P2P_DEVICE_NEEDS_CHANNEL\t= 1 << 4,\n\tNL80211_FEATURE_SAE\t\t\t\t= 1 << 5,\n\tNL80211_FEATURE_LOW_PRIORITY_SCAN\t\t= 1 << 6,\n\tNL80211_FEATURE_SCAN_FLUSH\t\t\t= 1 << 7,\n\tNL80211_FEATURE_AP_SCAN\t\t\t\t= 1 << 8,\n\tNL80211_FEATURE_VIF_TXPOWER\t\t\t= 1 << 9,\n\tNL80211_FEATURE_NEED_OBSS_SCAN\t\t\t= 1 << 10,\n\tNL80211_FEATURE_P2P_GO_CTWIN\t\t\t= 1 << 11,\n\tNL80211_FEATURE_P2P_GO_OPPPS\t\t\t= 1 << 12,\n\t/* bit 13 is reserved */\n\tNL80211_FEATURE_ADVERTISE_CHAN_LIMITS\t\t= 1 << 14,\n\tNL80211_FEATURE_FULL_AP_CLIENT_STATE\t\t= 1 << 15,\n\tNL80211_FEATURE_USERSPACE_MPM\t\t\t= 1 << 16,\n\tNL80211_FEATURE_ACTIVE_MONITOR\t\t\t= 1 << 17,\n\tNL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE\t= 1 << 18,\n\tNL80211_FEATURE_DS_PARAM_SET_IE_IN_PROBES\t= 1 << 19,\n\tNL80211_FEATURE_WFA_TPC_IE_IN_PROBES\t\t= 1 << 20,\n\tNL80211_FEATURE_QUIET\t\t\t\t= 1 << 21,\n\tNL80211_FEATURE_TX_POWER_INSERTION\t\t= 1 << 22,\n\tNL80211_FEATURE_ACKTO_ESTIMATION\t\t= 1 << 23,\n\tNL80211_FEATURE_STATIC_SMPS\t\t\t= 1 << 24,\n\tNL80211_FEATURE_DYNAMIC_SMPS\t\t\t= 1 << 25,\n\tNL80211_FEATURE_SUPPORTS_WMM_ADMISSION\t\t= 1 << 26,\n\tNL80211_FEATURE_MAC_ON_CREATE\t\t\t= 1 << 27,\n\tNL80211_FEATURE_TDLS_CHANNEL_SWITCH\t\t= 1 << 28,\n\tNL80211_FEATURE_SCAN_RANDOM_MAC_ADDR\t\t= 1 << 29,\n\tNL80211_FEATURE_SCHED_SCAN_RANDOM_MAC_ADDR\t= 1 << 30,\n\tNL80211_FEATURE_ND_RANDOM_MAC_ADDR\t\t= 1 << 31,\n};\n\n/**\n * enum nl80211_ext_feature_index - bit index of extended features.\n * @NL80211_EXT_FEATURE_VHT_IBSS: This driver supports IBSS with VHT datarates.\n * @NL80211_EXT_FEATURE_RRM: This driver supports RRM. When featured, user can\n *\tcan request to use RRM (see %NL80211_ATTR_USE_RRM) with\n *\t%NL80211_CMD_ASSOCIATE and %NL80211_CMD_CONNECT requests, which will set\n *\tthe ASSOC_REQ_USE_RRM flag in the association request even if\n *\tNL80211_FEATURE_QUIET is not advertized.\n * @NL80211_EXT_FEATURE_MU_MIMO_AIR_SNIFFER: This device supports MU-MIMO air\n *\tsniffer which means that it can be configured to hear packets from\n *\tcertain groups which can be configured by the\n *\t%NL80211_ATTR_MU_MIMO_GROUP_DATA attribute,\n *\tor can be configured to follow a station by configuring the\n *\t%NL80211_ATTR_MU_MIMO_FOLLOW_MAC_ADDR attribute.\n * @NL80211_EXT_FEATURE_SCAN_START_TIME: This driver includes the actual\n *\ttime the scan started in scan results event. The time is the TSF of\n *\tthe BSS that the interface that requested the scan is connected to\n *\t(if available).\n * @NL80211_EXT_FEATURE_BSS_PARENT_TSF: Per BSS, this driver reports the\n *\ttime the last beacon/probe was received. The time is the TSF of the\n *\tBSS that the interface that requested the scan is connected to\n *\t(if available).\n * @NL80211_EXT_FEATURE_SET_SCAN_DWELL: This driver supports configuration of\n *\tchannel dwell time.\n * @NL80211_EXT_FEATURE_BEACON_RATE_LEGACY: Driver supports beacon rate\n *\tconfiguration (AP/mesh), supporting a legacy (non HT/VHT) rate.\n * @NL80211_EXT_FEATURE_BEACON_RATE_HT: Driver supports beacon rate\n *\tconfiguration (AP/mesh) with HT rates.\n * @NL80211_EXT_FEATURE_BEACON_RATE_VHT: Driver supports beacon rate\n *\tconfiguration (AP/mesh) with VHT rates.\n * @NL80211_EXT_FEATURE_FILS_STA: This driver supports Fast Initial Link Setup\n *\twith user space SME (NL80211_CMD_AUTHENTICATE) in station mode.\n * @NL80211_EXT_FEATURE_MGMT_TX_RANDOM_TA: This driver supports randomized TA\n *\tin @NL80211_CMD_FRAME while not associated.\n * @NL80211_EXT_FEATURE_MGMT_TX_RANDOM_TA_CONNECTED: This driver supports\n *\trandomized TA in @NL80211_CMD_FRAME while associated.\n * @NL80211_EXT_FEATURE_SCHED_SCAN_RELATIVE_RSSI: The driver supports sched_scan\n *\tfor reporting BSSs with better RSSI than the current connected BSS\n *\t(%NL80211_ATTR_SCHED_SCAN_RELATIVE_RSSI).\n * @NL80211_EXT_FEATURE_CQM_RSSI_LIST: With this driver the\n *\t%NL80211_ATTR_CQM_RSSI_THOLD attribute accepts a list of zero or more\n *\tRSSI threshold values to monitor rather than exactly one threshold.\n * @NL80211_EXT_FEATURE_FILS_SK_OFFLOAD: Driver SME supports FILS shared key\n *\tauthentication with %NL80211_CMD_CONNECT.\n * @NL80211_EXT_FEATURE_4WAY_HANDSHAKE_STA_PSK: Device wants to do 4-way\n *\thandshake with PSK in station mode (PSK is passed as part of the connect\n *\tand associate commands), doing it in the host might not be supported.\n * @NL80211_EXT_FEATURE_4WAY_HANDSHAKE_STA_1X: Device wants to do doing 4-way\n *\thandshake with 802.1X in station mode (will pass EAP frames to the host\n *\tand accept the set_pmk/del_pmk commands), doing it in the host might not\n *\tbe supported.\n *\n * @NUM_NL80211_EXT_FEATURES: number of extended features.\n * @MAX_NL80211_EXT_FEATURES: highest extended feature index.\n */\nenum nl80211_ext_feature_index {\n\tNL80211_EXT_FEATURE_VHT_IBSS,\n\tNL80211_EXT_FEATURE_RRM,\n\tNL80211_EXT_FEATURE_MU_MIMO_AIR_SNIFFER,\n\tNL80211_EXT_FEATURE_SCAN_START_TIME,\n\tNL80211_EXT_FEATURE_BSS_PARENT_TSF,\n\tNL80211_EXT_FEATURE_SET_SCAN_DWELL,\n\tNL80211_EXT_FEATURE_BEACON_RATE_LEGACY,\n\tNL80211_EXT_FEATURE_BEACON_RATE_HT,\n\tNL80211_EXT_FEATURE_BEACON_RATE_VHT,\n\tNL80211_EXT_FEATURE_FILS_STA,\n\tNL80211_EXT_FEATURE_MGMT_TX_RANDOM_TA,\n\tNL80211_EXT_FEATURE_MGMT_TX_RANDOM_TA_CONNECTED,\n\tNL80211_EXT_FEATURE_SCHED_SCAN_RELATIVE_RSSI,\n\tNL80211_EXT_FEATURE_CQM_RSSI_LIST,\n\tNL80211_EXT_FEATURE_FILS_SK_OFFLOAD,\n\tNL80211_EXT_FEATURE_4WAY_HANDSHAKE_STA_PSK,\n\tNL80211_EXT_FEATURE_4WAY_HANDSHAKE_STA_1X,\n\n\t/* add new features before the definition below */\n\tNUM_NL80211_EXT_FEATURES,\n\tMAX_NL80211_EXT_FEATURES = NUM_NL80211_EXT_FEATURES - 1\n};\n\n/**\n * enum nl80211_probe_resp_offload_support_attr - optional supported\n *\tprotocols for probe-response offloading by the driver/FW.\n *\tTo be used with the %NL80211_ATTR_PROBE_RESP_OFFLOAD attribute.\n *\tEach enum value represents a bit in the bitmap of supported\n *\tprotocols. Typically a subset of probe-requests belonging to a\n *\tsupported protocol will be excluded from offload and uploaded\n *\tto the host.\n *\n * @NL80211_PROBE_RESP_OFFLOAD_SUPPORT_WPS: Support for WPS ver. 1\n * @NL80211_PROBE_RESP_OFFLOAD_SUPPORT_WPS2: Support for WPS ver. 2\n * @NL80211_PROBE_RESP_OFFLOAD_SUPPORT_P2P: Support for P2P\n * @NL80211_PROBE_RESP_OFFLOAD_SUPPORT_80211U: Support for 802.11u\n */\nenum nl80211_probe_resp_offload_support_attr {\n\tNL80211_PROBE_RESP_OFFLOAD_SUPPORT_WPS =\t1<<0,\n\tNL80211_PROBE_RESP_OFFLOAD_SUPPORT_WPS2 =\t1<<1,\n\tNL80211_PROBE_RESP_OFFLOAD_SUPPORT_P2P =\t1<<2,\n\tNL80211_PROBE_RESP_OFFLOAD_SUPPORT_80211U =\t1<<3,\n};\n\n/**\n * enum nl80211_connect_failed_reason - connection request failed reasons\n * @NL80211_CONN_FAIL_MAX_CLIENTS: Maximum number of clients that can be\n *\thandled by the AP is reached.\n * @NL80211_CONN_FAIL_BLOCKED_CLIENT: Connection request is rejected due to ACL.\n */\nenum nl80211_connect_failed_reason {\n\tNL80211_CONN_FAIL_MAX_CLIENTS,\n\tNL80211_CONN_FAIL_BLOCKED_CLIENT,\n};\n\n/**\n * enum nl80211_timeout_reason - timeout reasons\n *\n * @NL80211_TIMEOUT_UNSPECIFIED: Timeout reason unspecified.\n * @NL80211_TIMEOUT_SCAN: Scan (AP discovery) timed out.\n * @NL80211_TIMEOUT_AUTH: Authentication timed out.\n * @NL80211_TIMEOUT_ASSOC: Association timed out.\n */\nenum nl80211_timeout_reason {\n\tNL80211_TIMEOUT_UNSPECIFIED,\n\tNL80211_TIMEOUT_SCAN,\n\tNL80211_TIMEOUT_AUTH,\n\tNL80211_TIMEOUT_ASSOC,\n};\n\n/**\n * enum nl80211_scan_flags -  scan request control flags\n *\n * Scan request control flags are used to control the handling\n * of NL80211_CMD_TRIGGER_SCAN and NL80211_CMD_START_SCHED_SCAN\n * requests.\n *\n * @NL80211_SCAN_FLAG_LOW_PRIORITY: scan request has low priority\n * @NL80211_SCAN_FLAG_FLUSH: flush cache before scanning\n * @NL80211_SCAN_FLAG_AP: force a scan even if the interface is configured\n *\tas AP and the beaconing has already been configured. This attribute is\n *\tdangerous because will destroy stations performance as a lot of frames\n *\twill be lost while scanning off-channel, therefore it must be used only\n *\twhen really needed\n * @NL80211_SCAN_FLAG_RANDOM_ADDR: use a random MAC address for this scan (or\n *\tfor scheduled scan: a different one for every scan iteration). When the\n *\tflag is set, depending on device capabilities the @NL80211_ATTR_MAC and\n *\t@NL80211_ATTR_MAC_MASK attributes may also be given in which case only\n *\tthe masked bits will be preserved from the MAC address and the remainder\n *\trandomised. If the attributes are not given full randomisation (46 bits,\n *\tlocally administered 1, multicast 0) is assumed.\n *\tThis flag must not be requested when the feature isn't supported, check\n *\tthe nl80211 feature flags for the device.\n */\nenum nl80211_scan_flags {\n\tNL80211_SCAN_FLAG_LOW_PRIORITY\t\t\t= 1<<0,\n\tNL80211_SCAN_FLAG_FLUSH\t\t\t\t= 1<<1,\n\tNL80211_SCAN_FLAG_AP\t\t\t\t= 1<<2,\n\tNL80211_SCAN_FLAG_RANDOM_ADDR\t\t\t= 1<<3,\n};\n\n/**\n * enum nl80211_acl_policy - access control policy\n *\n * Access control policy is applied on a MAC list set by\n * %NL80211_CMD_START_AP and %NL80211_CMD_SET_MAC_ACL, to\n * be used with %NL80211_ATTR_ACL_POLICY.\n *\n * @NL80211_ACL_POLICY_ACCEPT_UNLESS_LISTED: Deny stations which are\n *\tlisted in ACL, i.e. allow all the stations which are not listed\n *\tin ACL to authenticate.\n * @NL80211_ACL_POLICY_DENY_UNLESS_LISTED: Allow the stations which are listed\n *\tin ACL, i.e. deny all the stations which are not listed in ACL.\n */\nenum nl80211_acl_policy {\n\tNL80211_ACL_POLICY_ACCEPT_UNLESS_LISTED,\n\tNL80211_ACL_POLICY_DENY_UNLESS_LISTED,\n};\n\n/**\n * enum nl80211_smps_mode - SMPS mode\n *\n * Requested SMPS mode (for AP mode)\n *\n * @NL80211_SMPS_OFF: SMPS off (use all antennas).\n * @NL80211_SMPS_STATIC: static SMPS (use a single antenna)\n * @NL80211_SMPS_DYNAMIC: dynamic smps (start with a single antenna and\n *\tturn on other antennas after CTS/RTS).\n */\nenum nl80211_smps_mode {\n\tNL80211_SMPS_OFF,\n\tNL80211_SMPS_STATIC,\n\tNL80211_SMPS_DYNAMIC,\n\n\t__NL80211_SMPS_AFTER_LAST,\n\tNL80211_SMPS_MAX = __NL80211_SMPS_AFTER_LAST - 1\n};\n\n/**\n * enum nl80211_radar_event - type of radar event for DFS operation\n *\n * Type of event to be used with NL80211_ATTR_RADAR_EVENT to inform userspace\n * about detected radars or success of the channel available check (CAC)\n *\n * @NL80211_RADAR_DETECTED: A radar pattern has been detected. The channel is\n *\tnow unusable.\n * @NL80211_RADAR_CAC_FINISHED: Channel Availability Check has been finished,\n *\tthe channel is now available.\n * @NL80211_RADAR_CAC_ABORTED: Channel Availability Check has been aborted, no\n *\tchange to the channel status.\n * @NL80211_RADAR_NOP_FINISHED: The Non-Occupancy Period for this channel is\n *\tover, channel becomes usable.\n * @NL80211_RADAR_PRE_CAC_EXPIRED: Channel Availability Check done on this\n *\tnon-operating channel is expired and no longer valid. New CAC must\n *\tbe done on this channel before starting the operation. This is not\n *\tapplicable for ETSI dfs domain where pre-CAC is valid for ever.\n */\nenum nl80211_radar_event {\n\tNL80211_RADAR_DETECTED,\n\tNL80211_RADAR_CAC_FINISHED,\n\tNL80211_RADAR_CAC_ABORTED,\n\tNL80211_RADAR_NOP_FINISHED,\n\tNL80211_RADAR_PRE_CAC_EXPIRED,\n};\n\n/**\n * enum nl80211_dfs_state - DFS states for channels\n *\n * Channel states used by the DFS code.\n *\n * @NL80211_DFS_USABLE: The channel can be used, but channel availability\n *\tcheck (CAC) must be performed before using it for AP or IBSS.\n * @NL80211_DFS_UNAVAILABLE: A radar has been detected on this channel, it\n *\tis therefore marked as not available.\n * @NL80211_DFS_AVAILABLE: The channel has been CAC checked and is available.\n */\nenum nl80211_dfs_state {\n\tNL80211_DFS_USABLE,\n\tNL80211_DFS_UNAVAILABLE,\n\tNL80211_DFS_AVAILABLE,\n};\n\n/**\n * enum enum nl80211_protocol_features - nl80211 protocol features\n * @NL80211_PROTOCOL_FEATURE_SPLIT_WIPHY_DUMP: nl80211 supports splitting\n *\twiphy dumps (if requested by the application with the attribute\n *\t%NL80211_ATTR_SPLIT_WIPHY_DUMP. Also supported is filtering the\n *\twiphy dump by %NL80211_ATTR_WIPHY, %NL80211_ATTR_IFINDEX or\n *\t%NL80211_ATTR_WDEV.\n */\nenum nl80211_protocol_features {\n\tNL80211_PROTOCOL_FEATURE_SPLIT_WIPHY_DUMP =\t1 << 0,\n};\n\n/**\n * enum nl80211_crit_proto_id - nl80211 critical protocol identifiers\n *\n * @NL80211_CRIT_PROTO_UNSPEC: protocol unspecified.\n * @NL80211_CRIT_PROTO_DHCP: BOOTP or DHCPv6 protocol.\n * @NL80211_CRIT_PROTO_EAPOL: EAPOL protocol.\n * @NL80211_CRIT_PROTO_APIPA: APIPA protocol.\n * @NUM_NL80211_CRIT_PROTO: must be kept last.\n */\nenum nl80211_crit_proto_id {\n\tNL80211_CRIT_PROTO_UNSPEC,\n\tNL80211_CRIT_PROTO_DHCP,\n\tNL80211_CRIT_PROTO_EAPOL,\n\tNL80211_CRIT_PROTO_APIPA,\n\t/* add other protocols before this one */\n\tNUM_NL80211_CRIT_PROTO\n};\n\n/* maximum duration for critical protocol measures */\n#define NL80211_CRIT_PROTO_MAX_DURATION\t\t5000 /* msec */\n\n/**\n * enum nl80211_rxmgmt_flags - flags for received management frame.\n *\n * Used by cfg80211_rx_mgmt()\n *\n * @NL80211_RXMGMT_FLAG_ANSWERED: frame was answered by device/driver.\n */\nenum nl80211_rxmgmt_flags {\n\tNL80211_RXMGMT_FLAG_ANSWERED = 1 << 0,\n};\n\n/*\n * If this flag is unset, the lower 24 bits are an OUI, if set\n * a Linux nl80211 vendor ID is used (no such IDs are allocated\n * yet, so that's not valid so far)\n */\n#define NL80211_VENDOR_ID_IS_LINUX\t0x80000000\n\n/**\n * struct nl80211_vendor_cmd_info - vendor command data\n * @vendor_id: If the %NL80211_VENDOR_ID_IS_LINUX flag is clear, then the\n *\tvalue is a 24-bit OUI; if it is set then a separately allocated ID\n *\tmay be used, but no such IDs are allocated yet. New IDs should be\n *\tadded to this file when needed.\n * @subcmd: sub-command ID for the command\n */\nstruct nl80211_vendor_cmd_info {\n\t__u32 vendor_id;\n\t__u32 subcmd;\n};\n\n/**\n * enum nl80211_tdls_peer_capability - TDLS peer flags.\n *\n * Used by tdls_mgmt() to determine which conditional elements need\n * to be added to TDLS Setup frames.\n *\n * @NL80211_TDLS_PEER_HT: TDLS peer is HT capable.\n * @NL80211_TDLS_PEER_VHT: TDLS peer is VHT capable.\n * @NL80211_TDLS_PEER_WMM: TDLS peer is WMM capable.\n */\nenum nl80211_tdls_peer_capability {\n\tNL80211_TDLS_PEER_HT = 1<<0,\n\tNL80211_TDLS_PEER_VHT = 1<<1,\n\tNL80211_TDLS_PEER_WMM = 1<<2,\n};\n\n/**\n * enum nl80211_sched_scan_plan - scanning plan for scheduled scan\n * @__NL80211_SCHED_SCAN_PLAN_INVALID: attribute number 0 is reserved\n * @NL80211_SCHED_SCAN_PLAN_INTERVAL: interval between scan iterations. In\n *\tseconds (u32).\n * @NL80211_SCHED_SCAN_PLAN_ITERATIONS: number of scan iterations in this\n *\tscan plan (u32). The last scan plan must not specify this attribute\n *\tbecause it will run infinitely. A value of zero is invalid as it will\n *\tmake the scan plan meaningless.\n * @NL80211_SCHED_SCAN_PLAN_MAX: highest scheduled scan plan attribute number\n *\tcurrently defined\n * @__NL80211_SCHED_SCAN_PLAN_AFTER_LAST: internal use\n */\nenum nl80211_sched_scan_plan {\n\t__NL80211_SCHED_SCAN_PLAN_INVALID,\n\tNL80211_SCHED_SCAN_PLAN_INTERVAL,\n\tNL80211_SCHED_SCAN_PLAN_ITERATIONS,\n\n\t/* keep last */\n\t__NL80211_SCHED_SCAN_PLAN_AFTER_LAST,\n\tNL80211_SCHED_SCAN_PLAN_MAX =\n\t\t__NL80211_SCHED_SCAN_PLAN_AFTER_LAST - 1\n};\n\n/**\n * struct nl80211_bss_select_rssi_adjust - RSSI adjustment parameters.\n *\n * @band: band of BSS that must match for RSSI value adjustment. The value\n *\tof this field is according to &enum nl80211_band.\n * @delta: value used to adjust the RSSI value of matching BSS in dB.\n */\nstruct nl80211_bss_select_rssi_adjust {\n\t__u8 band;\n\t__s8 delta;\n} __attribute__((packed));\n\n/**\n * enum nl80211_bss_select_attr - attributes for bss selection.\n *\n * @__NL80211_BSS_SELECT_ATTR_INVALID: reserved.\n * @NL80211_BSS_SELECT_ATTR_RSSI: Flag indicating only RSSI-based BSS selection\n *\tis requested.\n * @NL80211_BSS_SELECT_ATTR_BAND_PREF: attribute indicating BSS\n *\tselection should be done such that the specified band is preferred.\n *\tWhen there are multiple BSS-es in the preferred band, the driver\n *\tshall use RSSI-based BSS selection as a second step. The value of\n *\tthis attribute is according to &enum nl80211_band (u32).\n * @NL80211_BSS_SELECT_ATTR_RSSI_ADJUST: When present the RSSI level for\n *\tBSS-es in the specified band is to be adjusted before doing\n *\tRSSI-based BSS selection. The attribute value is a packed structure\n *\tvalue as specified by &struct nl80211_bss_select_rssi_adjust.\n * @NL80211_BSS_SELECT_ATTR_MAX: highest bss select attribute number.\n * @__NL80211_BSS_SELECT_ATTR_AFTER_LAST: internal use.\n *\n * One and only one of these attributes are found within %NL80211_ATTR_BSS_SELECT\n * for %NL80211_CMD_CONNECT. It specifies the required BSS selection behaviour\n * which the driver shall use.\n */\nenum nl80211_bss_select_attr {\n\t__NL80211_BSS_SELECT_ATTR_INVALID,\n\tNL80211_BSS_SELECT_ATTR_RSSI,\n\tNL80211_BSS_SELECT_ATTR_BAND_PREF,\n\tNL80211_BSS_SELECT_ATTR_RSSI_ADJUST,\n\n\t/* keep last */\n\t__NL80211_BSS_SELECT_ATTR_AFTER_LAST,\n\tNL80211_BSS_SELECT_ATTR_MAX = __NL80211_BSS_SELECT_ATTR_AFTER_LAST - 1\n};\n\n/**\n * enum nl80211_nan_function_type - NAN function type\n *\n * Defines the function type of a NAN function\n *\n * @NL80211_NAN_FUNC_PUBLISH: function is publish\n * @NL80211_NAN_FUNC_SUBSCRIBE: function is subscribe\n * @NL80211_NAN_FUNC_FOLLOW_UP: function is follow-up\n */\nenum nl80211_nan_function_type {\n\tNL80211_NAN_FUNC_PUBLISH,\n\tNL80211_NAN_FUNC_SUBSCRIBE,\n\tNL80211_NAN_FUNC_FOLLOW_UP,\n\n\t/* keep last */\n\t__NL80211_NAN_FUNC_TYPE_AFTER_LAST,\n\tNL80211_NAN_FUNC_MAX_TYPE = __NL80211_NAN_FUNC_TYPE_AFTER_LAST - 1,\n};\n\n/**\n * enum nl80211_nan_publish_type - NAN publish tx type\n *\n * Defines how to send publish Service Discovery Frames\n *\n * @NL80211_NAN_SOLICITED_PUBLISH: publish function is solicited\n * @NL80211_NAN_UNSOLICITED_PUBLISH: publish function is unsolicited\n */\nenum nl80211_nan_publish_type {\n\tNL80211_NAN_SOLICITED_PUBLISH = 1 << 0,\n\tNL80211_NAN_UNSOLICITED_PUBLISH = 1 << 1,\n};\n\n/**\n * enum nl80211_nan_func_term_reason - NAN functions termination reason\n *\n * Defines termination reasons of a NAN function\n *\n * @NL80211_NAN_FUNC_TERM_REASON_USER_REQUEST: requested by user\n * @NL80211_NAN_FUNC_TERM_REASON_TTL_EXPIRED: timeout\n * @NL80211_NAN_FUNC_TERM_REASON_ERROR: errored\n */\nenum nl80211_nan_func_term_reason {\n\tNL80211_NAN_FUNC_TERM_REASON_USER_REQUEST,\n\tNL80211_NAN_FUNC_TERM_REASON_TTL_EXPIRED,\n\tNL80211_NAN_FUNC_TERM_REASON_ERROR,\n};\n\n#define NL80211_NAN_FUNC_SERVICE_ID_LEN 6\n#define NL80211_NAN_FUNC_SERVICE_SPEC_INFO_MAX_LEN 0xff\n#define NL80211_NAN_FUNC_SRF_MAX_LEN 0xff\n\n/**\n * enum nl80211_nan_func_attributes - NAN function attributes\n * @__NL80211_NAN_FUNC_INVALID: invalid\n * @NL80211_NAN_FUNC_TYPE: &enum nl80211_nan_function_type (u8).\n * @NL80211_NAN_FUNC_SERVICE_ID: 6 bytes of the service ID hash as\n *\tspecified in NAN spec. This is a binary attribute.\n * @NL80211_NAN_FUNC_PUBLISH_TYPE: relevant if the function's type is\n *\tpublish. Defines the transmission type for the publish Service Discovery\n *\tFrame, see &enum nl80211_nan_publish_type. Its type is u8.\n * @NL80211_NAN_FUNC_PUBLISH_BCAST: relevant if the function is a solicited\n *\tpublish. Should the solicited publish Service Discovery Frame be sent to\n *\tthe NAN Broadcast address. This is a flag.\n * @NL80211_NAN_FUNC_SUBSCRIBE_ACTIVE: relevant if the function's type is\n *\tsubscribe. Is the subscribe active. This is a flag.\n * @NL80211_NAN_FUNC_FOLLOW_UP_ID: relevant if the function's type is follow up.\n *\tThe instance ID for the follow up Service Discovery Frame. This is u8.\n * @NL80211_NAN_FUNC_FOLLOW_UP_REQ_ID: relevant if the function's type\n *\tis follow up. This is a u8.\n *\tThe requestor instance ID for the follow up Service Discovery Frame.\n * @NL80211_NAN_FUNC_FOLLOW_UP_DEST: the MAC address of the recipient of the\n *\tfollow up Service Discovery Frame. This is a binary attribute.\n * @NL80211_NAN_FUNC_CLOSE_RANGE: is this function limited for devices in a\n *\tclose range. The range itself (RSSI) is defined by the device.\n *\tThis is a flag.\n * @NL80211_NAN_FUNC_TTL: strictly positive number of DWs this function should\n *\tstay active. If not present infinite TTL is assumed. This is a u32.\n * @NL80211_NAN_FUNC_SERVICE_INFO: array of bytes describing the service\n *\tspecific info. This is a binary attribute.\n * @NL80211_NAN_FUNC_SRF: Service Receive Filter. This is a nested attribute.\n *\tSee &enum nl80211_nan_srf_attributes.\n * @NL80211_NAN_FUNC_RX_MATCH_FILTER: Receive Matching filter. This is a nested\n *\tattribute. It is a list of binary values.\n * @NL80211_NAN_FUNC_TX_MATCH_FILTER: Transmit Matching filter. This is a\n *\tnested attribute. It is a list of binary values.\n * @NL80211_NAN_FUNC_INSTANCE_ID: The instance ID of the function.\n *\tIts type is u8 and it cannot be 0.\n * @NL80211_NAN_FUNC_TERM_REASON: NAN function termination reason.\n *\tSee &enum nl80211_nan_func_term_reason.\n *\n * @NUM_NL80211_NAN_FUNC_ATTR: internal\n * @NL80211_NAN_FUNC_ATTR_MAX: highest NAN function attribute\n */\nenum nl80211_nan_func_attributes {\n\t__NL80211_NAN_FUNC_INVALID,\n\tNL80211_NAN_FUNC_TYPE,\n\tNL80211_NAN_FUNC_SERVICE_ID,\n\tNL80211_NAN_FUNC_PUBLISH_TYPE,\n\tNL80211_NAN_FUNC_PUBLISH_BCAST,\n\tNL80211_NAN_FUNC_SUBSCRIBE_ACTIVE,\n\tNL80211_NAN_FUNC_FOLLOW_UP_ID,\n\tNL80211_NAN_FUNC_FOLLOW_UP_REQ_ID,\n\tNL80211_NAN_FUNC_FOLLOW_UP_DEST,\n\tNL80211_NAN_FUNC_CLOSE_RANGE,\n\tNL80211_NAN_FUNC_TTL,\n\tNL80211_NAN_FUNC_SERVICE_INFO,\n\tNL80211_NAN_FUNC_SRF,\n\tNL80211_NAN_FUNC_RX_MATCH_FILTER,\n\tNL80211_NAN_FUNC_TX_MATCH_FILTER,\n\tNL80211_NAN_FUNC_INSTANCE_ID,\n\tNL80211_NAN_FUNC_TERM_REASON,\n\n\t/* keep last */\n\tNUM_NL80211_NAN_FUNC_ATTR,\n\tNL80211_NAN_FUNC_ATTR_MAX = NUM_NL80211_NAN_FUNC_ATTR - 1\n};\n\n/**\n * enum nl80211_nan_srf_attributes - NAN Service Response filter attributes\n * @__NL80211_NAN_SRF_INVALID: invalid\n * @NL80211_NAN_SRF_INCLUDE: present if the include bit of the SRF set.\n *\tThis is a flag.\n * @NL80211_NAN_SRF_BF: Bloom Filter. Present if and only if\n *\t&NL80211_NAN_SRF_MAC_ADDRS isn't present. This attribute is binary.\n * @NL80211_NAN_SRF_BF_IDX: index of the Bloom Filter. Mandatory if\n *\t&NL80211_NAN_SRF_BF is present. This is a u8.\n * @NL80211_NAN_SRF_MAC_ADDRS: list of MAC addresses for the SRF. Present if\n *\tand only if &NL80211_NAN_SRF_BF isn't present. This is a nested\n *\tattribute. Each nested attribute is a MAC address.\n * @NUM_NL80211_NAN_SRF_ATTR: internal\n * @NL80211_NAN_SRF_ATTR_MAX: highest NAN SRF attribute\n */\nenum nl80211_nan_srf_attributes {\n\t__NL80211_NAN_SRF_INVALID,\n\tNL80211_NAN_SRF_INCLUDE,\n\tNL80211_NAN_SRF_BF,\n\tNL80211_NAN_SRF_BF_IDX,\n\tNL80211_NAN_SRF_MAC_ADDRS,\n\n\t/* keep last */\n\tNUM_NL80211_NAN_SRF_ATTR,\n\tNL80211_NAN_SRF_ATTR_MAX = NUM_NL80211_NAN_SRF_ATTR - 1,\n};\n\n/**\n * enum nl80211_nan_match_attributes - NAN match attributes\n * @__NL80211_NAN_MATCH_INVALID: invalid\n * @NL80211_NAN_MATCH_FUNC_LOCAL: the local function that had the\n *\tmatch. This is a nested attribute.\n *\tSee &enum nl80211_nan_func_attributes.\n * @NL80211_NAN_MATCH_FUNC_PEER: the peer function\n *\tthat caused the match. This is a nested attribute.\n *\tSee &enum nl80211_nan_func_attributes.\n *\n * @NUM_NL80211_NAN_MATCH_ATTR: internal\n * @NL80211_NAN_MATCH_ATTR_MAX: highest NAN match attribute\n */\nenum nl80211_nan_match_attributes {\n\t__NL80211_NAN_MATCH_INVALID,\n\tNL80211_NAN_MATCH_FUNC_LOCAL,\n\tNL80211_NAN_MATCH_FUNC_PEER,\n\n\t/* keep last */\n\tNUM_NL80211_NAN_MATCH_ATTR,\n\tNL80211_NAN_MATCH_ATTR_MAX = NUM_NL80211_NAN_MATCH_ATTR - 1\n};\n\n#endif /* __LINUX_NL80211_H */\n"
  },
  {
    "path": "user_space/sdrctl_src/nl80211_testmode_def.h",
    "content": "// Author: Xianjun Jiao\n// SPDX-FileCopyrightText: 2019 UGent\n// SPDX-License-Identifier: AGPL-3.0-or-later\n\n//---nl80211 cmd testmode definitions\n//---should be used in driver sdr.c and user space app\n\nenum openwifi_testmode_attr {\n\t__OPENWIFI_ATTR_INVALID = 0,\n\tOPENWIFI_ATTR_CMD = 1,\n\tOPENWIFI_ATTR_GAP = 2,\n\tOPENWIFI_ATTR_SLICE_IDX = 3,\n\tOPENWIFI_ATTR_ADDR = 4,\n\tOPENWIFI_ATTR_SLICE_TOTAL = 5,\n\tOPENWIFI_ATTR_SLICE_START = 6,\n\tOPENWIFI_ATTR_SLICE_END = 7,\n\t// OPENWIFI_ATTR_SLICE_TOTAL1 = 8,\n\t// OPENWIFI_ATTR_SLICE_START1 = 9,\n\t// OPENWIFI_ATTR_SLICE_END1 = 10,\n\tOPENWIFI_ATTR_RSSI_TH = 11,\n\tOPENWIFI_ATTR_HIGH_TSF = 12,\n\tOPENWIFI_ATTR_LOW_TSF = 13,\n\n\tREG_ATTR_ADDR = 14,\n\tREG_ATTR_VAL = 15,\n\n\t/* keep last */\n\t__OPENWIFI_ATTR_AFTER_LAST,\n\tOPENWIFI_ATTR_MAX\t= __OPENWIFI_ATTR_AFTER_LAST - 1\n};\n\nenum openwifi_testmode_cmd {\n\tOPENWIFI_CMD_SET_GAP = 0,\n\tOPENWIFI_CMD_GET_GAP = 1,\n\t\n\tOPENWIFI_CMD_SET_SLICE_IDX = 2,\n\tOPENWIFI_CMD_GET_SLICE_IDX = 3,\n\t\n\tOPENWIFI_CMD_SET_ADDR = 4,\n\tOPENWIFI_CMD_GET_ADDR = 5,\n\t\n\tOPENWIFI_CMD_SET_SLICE_TOTAL = 6,\n\tOPENWIFI_CMD_GET_SLICE_TOTAL = 7,\n\n\tOPENWIFI_CMD_SET_SLICE_START = 8,\n\tOPENWIFI_CMD_GET_SLICE_START = 9,\n\n\tOPENWIFI_CMD_SET_SLICE_END = 10,\n\tOPENWIFI_CMD_GET_SLICE_END = 11,\n\n\t// OPENWIFI_CMD_SET_SLICE_TOTAL1 = 12,\n\t// OPENWIFI_CMD_GET_SLICE_TOTAL1 = 13,\n\n\t// OPENWIFI_CMD_SET_SLICE_START1 = 14,\n\t// OPENWIFI_CMD_GET_SLICE_START1 = 15,\n\n\t// OPENWIFI_CMD_SET_SLICE_END1 = 16,\n\t// OPENWIFI_CMD_GET_SLICE_END1 = 17,\n\n\tOPENWIFI_CMD_SET_RSSI_TH = 18,\n\tOPENWIFI_CMD_GET_RSSI_TH = 19,\n\n\tOPENWIFI_CMD_SET_TSF = 20,\n\n\tREG_CMD_SET = 21,\n\tREG_CMD_GET = 22,\n};\n\nstatic const struct nla_policy openwifi_testmode_policy[OPENWIFI_ATTR_MAX + 1] = {\n\t[OPENWIFI_ATTR_CMD] = { .type = NLA_U32 },\n\t[OPENWIFI_ATTR_GAP] = { .type = NLA_U32 },\n\t[OPENWIFI_ATTR_SLICE_IDX] = { .type = NLA_U32 },\n\t[OPENWIFI_ATTR_ADDR] = { .type = NLA_U32 },\n\t[OPENWIFI_ATTR_SLICE_TOTAL] = { .type = NLA_U32 },\n\t[OPENWIFI_ATTR_SLICE_START] = { .type = NLA_U32 },\n\t[OPENWIFI_ATTR_SLICE_END] = { .type = NLA_U32 },\n\t// [OPENWIFI_ATTR_SLICE_TOTAL1] = { .type = NLA_U32 },\n\t// [OPENWIFI_ATTR_SLICE_START1] = { .type = NLA_U32 },\n\t// [OPENWIFI_ATTR_SLICE_END1] = { .type = NLA_U32 },\n\t[OPENWIFI_ATTR_RSSI_TH] = { .type = NLA_U32 },\n\t[OPENWIFI_ATTR_HIGH_TSF] = { .type = NLA_U32 },\n\t[OPENWIFI_ATTR_LOW_TSF] = { .type = NLA_U32 },\n\n\t[REG_ATTR_ADDR] = { .type = NLA_U32 },\n\t[REG_ATTR_VAL] = { .type = NLA_U32 },\n};\n"
  },
  {
    "path": "user_space/sdrctl_src/sdrctl.c",
    "content": "/*\n * nl80211 userspace tool\n *\n * SPDX-FileCopyrightText: Copyright 2007, 2008 Johannes Berg <johannes@sipsolutions.net>\n * Modified by Xianjun jiao\n * SPDX-License-Identifier: AGPL-3.0-or-later\n */\n\n#include <errno.h>\n#include <stdio.h>\n#include <string.h>\n#include <net/if.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <fcntl.h>\n#include <unistd.h>\n#include <stdbool.h>\n\n#include <netlink/genl/genl.h>\n#include <netlink/genl/family.h>\n#include <netlink/genl/ctrl.h>\n#include <netlink/msg.h>\n#include <netlink/attr.h>\n\n#include \"nl80211.h\"\n#include \"sdrctl.h\"\n\n/* libnl 1.x compatibility code */\n#if !defined(CONFIG_LIBNL20) && !defined(CONFIG_LIBNL30)\nstatic inline struct nl_handle *nl_socket_alloc(void)\n{\n\treturn nl_handle_alloc();\n}\n\nstatic inline void nl_socket_free(struct nl_sock *h)\n{\n\tnl_handle_destroy(h);\n}\n\nstatic inline int nl_socket_set_buffer_size(struct nl_sock *sk,\n\t\t\t\t\t    int rxbuf, int txbuf)\n{\n\treturn nl_set_buffer_size(sk, rxbuf, txbuf);\n}\n#endif /* CONFIG_LIBNL20 && CONFIG_LIBNL30 */\n\nint iw_debug = 0;\n\nstatic int nl80211_init(struct nl80211_state *state)\n{\n\tint err;\n\n\tstate->nl_sock = nl_socket_alloc();\n\tif (!state->nl_sock) {\n\t\tfprintf(stderr, \"Failed to allocate netlink socket.\\n\");\n\t\treturn -ENOMEM;\n\t}\n\n\tnl_socket_set_buffer_size(state->nl_sock, 8192, 8192);\n\n\tif (genl_connect(state->nl_sock)) {\n\t\tfprintf(stderr, \"Failed to connect to generic netlink.\\n\");\n\t\terr = -ENOLINK;\n\t\tgoto out_handle_destroy;\n\t}\n\n\tstate->nl80211_id = genl_ctrl_resolve(state->nl_sock, \"nl80211\");\n\tif (state->nl80211_id < 0) {\n\t\tfprintf(stderr, \"nl80211 not found.\\n\");\n\t\terr = -ENOENT;\n\t\tgoto out_handle_destroy;\n\t}\n\n\treturn 0;\n\n out_handle_destroy:\n\tnl_socket_free(state->nl_sock);\n\treturn err;\n}\n\nstatic void nl80211_cleanup(struct nl80211_state *state)\n{\n\tnl_socket_free(state->nl_sock);\n}\n\nstatic int cmd_size;\n\nextern struct cmd __start___cmd;\nextern struct cmd __stop___cmd;\n\n#define for_each_cmd(_cmd)\t\t\t\t\t\\\n\tfor (_cmd = &__start___cmd; _cmd < &__stop___cmd;\t\t\\\n\t     _cmd = (const struct cmd *)((char *)_cmd + cmd_size))\n\n\nstatic void __usage_cmd(const struct cmd *cmd, char *indent, bool full)\n{\n\tconst char *start, *lend, *end;\n\n\tprintf(\"%s\", indent);\n\n\tswitch (cmd->idby) {\n\tcase CIB_NONE:\n\t\tbreak;\n\tcase CIB_PHY:\n\t\tprintf(\"phy <phyname> \");\n\t\tbreak;\n\tcase CIB_NETDEV:\n\t\tprintf(\"dev <devname> \");\n\t\tbreak;\n\tcase CIB_WDEV:\n\t\tprintf(\"wdev <idx> \");\n\t\tbreak;\n\t}\n\tif (cmd->parent && cmd->parent->name)\n\t\tprintf(\"%s \", cmd->parent->name);\n\tprintf(\"%s\", cmd->name);\n\n\tif (cmd->args) {\n\t\t/* print line by line */\n\t\tstart = cmd->args;\n\t\tend = strchr(start, '\\0');\n\t\tprintf(\" \");\n\t\tdo {\n\t\t\tlend = strchr(start, '\\n');\n\t\t\tif (!lend)\n\t\t\t\tlend = end;\n\t\t\tif (start != cmd->args) {\n\t\t\t\tprintf(\"\\t\");\n\t\t\t\tswitch (cmd->idby) {\n\t\t\t\tcase CIB_NONE:\n\t\t\t\t\tbreak;\n\t\t\t\tcase CIB_PHY:\n\t\t\t\t\tprintf(\"phy <phyname> \");\n\t\t\t\t\tbreak;\n\t\t\t\tcase CIB_NETDEV:\n\t\t\t\t\tprintf(\"dev <devname> \");\n\t\t\t\t\tbreak;\n\t\t\t\tcase CIB_WDEV:\n\t\t\t\t\tprintf(\"wdev <idx> \");\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tif (cmd->parent && cmd->parent->name)\n\t\t\t\t\tprintf(\"%s \", cmd->parent->name);\n\t\t\t\tprintf(\"%s \", cmd->name);\n\t\t\t}\n\t\t\tprintf(\"%.*s\\n\", (int)(lend - start), start);\n\t\t\tstart = lend + 1;\n\t\t} while (end != lend);\n\t} else\n\t\tprintf(\"\\n\");\n\n\tif (!full || !cmd->help)\n\t\treturn;\n\n\t/* hack */\n\tif (strlen(indent))\n\t\tindent = \"\\t\\t\";\n\telse\n\t\tprintf(\"\\n\");\n\n\t/* print line by line */\n\tstart = cmd->help;\n\tend = strchr(start, '\\0');\n\tdo {\n\t\tlend = strchr(start, '\\n');\n\t\tif (!lend)\n\t\t\tlend = end;\n\t\tprintf(\"%s\", indent);\n\t\tprintf(\"%.*s\\n\", (int)(lend - start), start);\n\t\tstart = lend + 1;\n\t} while (end != lend);\n\n\tprintf(\"\\n\");\n}\n\nstatic void usage_options(void)\n{\n\tprintf(\"Options:\\n\");\n\tprintf(\"\\t--debug\\t\\tenable netlink debugging\\n\");\n}\n\nstatic const char *argv0;\n\nstatic void usage(int argc, char **argv)\n{\n\tconst struct cmd *section, *cmd;\n\tbool full = argc >= 0;\n\tconst char *sect_filt = NULL;\n\tconst char *cmd_filt = NULL;\n\n\tif (argc > 0)\n\t\tsect_filt = argv[0];\n\n\tif (argc > 1)\n\t\tcmd_filt = argv[1];\n\n\tprintf(\"Usage:\\t%s [options] command\\n\", argv0);\n\tusage_options();\n\tprintf(\"\\t--version\\tshow version (%s)\\n\", sdrctl_version);\n\tprintf(\"Commands:\\n\");\n\tfor_each_cmd(section) {\n\t\tif (section->parent)\n\t\t\tcontinue;\n\n\t\tif (sect_filt && strcmp(section->name, sect_filt))\n\t\t\tcontinue;\n\n\t\tif (section->handler && !section->hidden)\n\t\t\t__usage_cmd(section, \"\\t\", full);\n\n\t\tfor_each_cmd(cmd) {\n\t\t\tif (section != cmd->parent)\n\t\t\t\tcontinue;\n\t\t\tif (!cmd->handler || cmd->hidden)\n\t\t\t\tcontinue;\n\t\t\tif (cmd_filt && strcmp(cmd->name, cmd_filt))\n\t\t\t\tcontinue;\n\t\t\t__usage_cmd(cmd, \"\\t\", full);\n\t\t}\n\t}\n\tprintf(\"\\nCommands that use the netdev ('dev') can also be given the\\n\"\n\t       \"'wdev' instead to identify the device.\\n\");\n\tprintf(\"\\nYou can omit the 'phy' or 'dev' if \"\n\t\t\t\"the identification is unique,\\n\"\n\t\t\t\"e.g. \\\"./sdrctl sdr0 get rssi_th\\\" or \\\"./sdrctl sdr0 get gap\\\". \"\n\t\t\t\"(Don't when scripting.)\\n\\n\"\n\t\t\t\"Do NOT screenscrape this tool, we don't \"\n\t\t\t\"consider its output stable.\\n\\n\");\n}\n\nstatic int print_help(struct nl80211_state *state,\n\t\t      struct nl_cb *cb,\n\t\t      struct nl_msg *msg,\n\t\t      int argc, char **argv,\n\t\t      enum id_input id)\n{\n\texit(3);\n}\nTOPLEVEL(help, \"[command]\", 0, 0, CIB_NONE, print_help,\n\t \"Print usage for all or a specific command, e.g.\\n\"\n\t \"\\\"help wowlan\\\" or \\\"help wowlan enable\\\".\");\n\nstatic void usage_cmd(const struct cmd *cmd)\n{\n\tprintf(\"Usage:\\t%s [options] \", argv0);\n\t__usage_cmd(cmd, \"\", true);\n\tusage_options();\n}\n\nstatic void version(void)\n{\n\tprintf(\"iw version %s\\n\", sdrctl_version);\n}\n\nstatic int phy_lookup(char *name)\n{\n\tchar buf[200];\n\tint fd, pos;\n\n\tsnprintf(buf, sizeof(buf), \"/sys/class/ieee80211/%s/index\", name);\n\n\tfd = open(buf, O_RDONLY);\n\tif (fd < 0)\n\t\treturn -1;\n\tpos = read(fd, buf, sizeof(buf) - 1);\n\tif (pos < 0) {\n\t\tclose(fd);\n\t\treturn -1;\n\t}\n\tbuf[pos] = '\\0';\n\tclose(fd);\n\treturn atoi(buf);\n}\n\nstatic int error_handler(struct sockaddr_nl *nla, struct nlmsgerr *err,\n\t\t\t void *arg)\n{\n\tint *ret = arg;\n\t*ret = err->error;\n\treturn NL_STOP;\n}\n\nstatic int finish_handler(struct nl_msg *msg, void *arg)\n{\n\tint *ret = arg;\n\t*ret = 0;\n\treturn NL_SKIP;\n}\n\nstatic int ack_handler(struct nl_msg *msg, void *arg)\n{\n\tint *ret = arg;\n\t*ret = 0;\n\treturn NL_STOP;\n}\n\nstatic int __handle_cmd(struct nl80211_state *state, enum id_input idby,\n\t\t\tint argc, char **argv, const struct cmd **cmdout)\n{\n\tconst struct cmd *cmd, *match = NULL, *sectcmd;\n\tstruct nl_cb *cb;\n\tstruct nl_cb *s_cb;\n\tstruct nl_msg *msg;\n\tsigned long long devidx = 0;\n\tint err, o_argc;\n\tconst char *command, *section;\n\tchar *tmp, **o_argv;\n\tenum command_identify_by command_idby = CIB_NONE;\n\n\tif (argc <= 1 && idby != II_NONE)\n\t\treturn 1;\n\n\to_argc = argc;\n\to_argv = argv;\n\n\tswitch (idby) {\n\tcase II_PHY_IDX:\n\t\tcommand_idby = CIB_PHY;\n\t\tdevidx = strtoul(*argv + 4, &tmp, 0);\n\t\tif (*tmp != '\\0')\n\t\t\treturn 1;\n\t\targc--;\n\t\targv++;\n\t\tbreak;\n\tcase II_PHY_NAME:\n\t\tcommand_idby = CIB_PHY;\n\t\tdevidx = phy_lookup(*argv);\n\t\targc--;\n\t\targv++;\n\t\tbreak;\n\tcase II_NETDEV:\n\t\tcommand_idby = CIB_NETDEV;\n\t\tdevidx = if_nametoindex(*argv);\n\t\tif (devidx == 0)\n\t\t\tdevidx = -1;\n\t\targc--;\n\t\targv++;\n\t\tbreak;\n\tcase II_WDEV:\n\t\tcommand_idby = CIB_WDEV;\n\t\tdevidx = strtoll(*argv, &tmp, 0);\n\t\tif (*tmp != '\\0')\n\t\t\treturn 1;\n\t\targc--;\n\t\targv++;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tif (devidx < 0)\n\t\treturn -errno;\n\n\tsection = *argv;\n\targc--;\n\targv++;\n\n\tfor_each_cmd(sectcmd) {\n\t\tif (sectcmd->parent)\n\t\t\tcontinue;\n\t\t/* ok ... bit of a hack for the dupe 'info' section */\n\t\tif (match && sectcmd->idby != command_idby)\n\t\t\tcontinue;\n\t\tif (strcmp(sectcmd->name, section) == 0)\n\t\t\tmatch = sectcmd;\n\t}\n\n\tsectcmd = match;\n\tmatch = NULL;\n\tif (!sectcmd)\n\t\treturn 1;\n\n\tif (argc > 0) {\n\t\tcommand = *argv;\n\n\t\tfor_each_cmd(cmd) {\n\t\t\tif (!cmd->handler)\n\t\t\t\tcontinue;\n\t\t\tif (cmd->parent != sectcmd)\n\t\t\t\tcontinue;\n\t\t\t/*\n\t\t\t * ignore mismatch id by, but allow WDEV\n\t\t\t * in place of NETDEV\n\t\t\t */\n\t\t\tif (cmd->idby != command_idby &&\n\t\t\t    !(cmd->idby == CIB_NETDEV &&\n\t\t\t      command_idby == CIB_WDEV))\n\t\t\t\tcontinue;\n\t\t\tif (strcmp(cmd->name, command))\n\t\t\t\tcontinue;\n\t\t\tif (argc > 1 && !cmd->args)\n\t\t\t\tcontinue;\n\t\t\tmatch = cmd;\n\t\t\tbreak;\n\t\t}\n\n\t\tif (match) {\n\t\t\targc--;\n\t\t\targv++;\n\t\t}\n\t}\n\n\tif (match)\n\t\tcmd = match;\n\telse {\n\t\t/* Use the section itself, if possible. */\n\t\tcmd = sectcmd;\n\t\tif (argc && !cmd->args)\n\t\t\treturn 1;\n\t\tif (cmd->idby != command_idby &&\n\t\t    !(cmd->idby == CIB_NETDEV && command_idby == CIB_WDEV))\n\t\t\treturn 1;\n\t\tif (!cmd->handler)\n\t\t\treturn 1;\n\t}\n\n\tif (cmd->selector) {\n\t\tcmd = cmd->selector(argc, argv);\n\t\tif (!cmd)\n\t\t\treturn 1;\n\t}\n\n\tif (cmdout)\n\t\t*cmdout = cmd;\n\n\tif (!cmd->cmd) {\n\t\targc = o_argc;\n\t\targv = o_argv;\n\t\treturn cmd->handler(state, NULL, NULL, argc, argv, idby);\n\t}\n\n\tmsg = nlmsg_alloc();\n\tif (!msg) {\n\t\tfprintf(stderr, \"failed to allocate netlink message\\n\");\n\t\treturn 2;\n\t}\n\n\tcb = nl_cb_alloc(iw_debug ? NL_CB_DEBUG : NL_CB_DEFAULT);\n\ts_cb = nl_cb_alloc(iw_debug ? NL_CB_DEBUG : NL_CB_DEFAULT);\n\tif (!cb || !s_cb) {\n\t\tfprintf(stderr, \"failed to allocate netlink callbacks\\n\");\n\t\terr = 2;\n\t\tgoto out_free_msg;\n\t}\n\n\tgenlmsg_put(msg, 0, 0, state->nl80211_id, 0,\n\t\t    cmd->nl_msg_flags, cmd->cmd, 0);\n\n\tswitch (command_idby) {\n\tcase CIB_PHY:\n\t\tNLA_PUT_U32(msg, NL80211_ATTR_WIPHY, devidx);\n\t\tbreak;\n\tcase CIB_NETDEV:\n\t\tNLA_PUT_U32(msg, NL80211_ATTR_IFINDEX, devidx);\n\t\tbreak;\n\tcase CIB_WDEV:\n\t\tNLA_PUT_U64(msg, NL80211_ATTR_WDEV, devidx);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\terr = cmd->handler(state, cb, msg, argc, argv, idby);\n\tif (err)\n\t\tgoto out;\n\n\tnl_socket_set_cb(state->nl_sock, s_cb);\n\n\terr = nl_send_auto_complete(state->nl_sock, msg);\n\tif (err < 0)\n\t\tgoto out;\n\n\terr = 1;\n\n\tnl_cb_err(cb, NL_CB_CUSTOM, error_handler, &err);\n\tnl_cb_set(cb, NL_CB_FINISH, NL_CB_CUSTOM, finish_handler, &err);\n\tnl_cb_set(cb, NL_CB_ACK, NL_CB_CUSTOM, ack_handler, &err);\n\n\twhile (err > 0)\n\t\tnl_recvmsgs(state->nl_sock, cb);\n out:\n\tnl_cb_put(cb);\n out_free_msg:\n\tnlmsg_free(msg);\n\treturn err;\n nla_put_failure:\n\tfprintf(stderr, \"building message failed\\n\");\n\treturn 2;\n}\n\nint handle_cmd(struct nl80211_state *state, enum id_input idby,\n\t       int argc, char **argv)\n{\n\treturn __handle_cmd(state, idby, argc, argv, NULL);\n}\n\nint main(int argc, char **argv)\n{\n\tstruct nl80211_state nlstate;\n\tint err;\n\tconst struct cmd *cmd = NULL;\n\n\t/* calculate command size including padding */\n\tcmd_size = abs((long)&__section_set - (long)&__section_get);\n\t/* strip off self */\n\targc--;\n\targv0 = *argv++;\n\n\tif (argc > 0 && strcmp(*argv, \"--debug\") == 0) {\n\t\tiw_debug = 1;\n\t\targc--;\n\t\targv++;\n\t}\n\n\tif (argc > 0 && strcmp(*argv, \"--version\") == 0) {\n\t\tversion();\n\t\treturn 0;\n\t}\n\n\t/* need to treat \"help\" command specially so it works w/o nl80211 */\n\tif (argc == 0 || strcmp(*argv, \"help\") == 0) {\n\t\tusage(argc - 1, argv + 1);\n\t\treturn 0;\n\t}\n\n\terr = nl80211_init(&nlstate);\n\tif (err)\n\t\treturn 1;\n\n\tif (strcmp(*argv, \"dev\") == 0 && argc > 1) {\n\t\targc--;\n\t\targv++;\n\t\terr = __handle_cmd(&nlstate, II_NETDEV, argc, argv, &cmd);\n\t} else if (strncmp(*argv, \"phy\", 3) == 0 && argc > 1) {\n\t\tif (strlen(*argv) == 3) {\n\t\t\targc--;\n\t\t\targv++;\n\t\t\terr = __handle_cmd(&nlstate, II_PHY_NAME, argc, argv, &cmd);\n\t\t} else if (*(*argv + 3) == '#')\n\t\t\terr = __handle_cmd(&nlstate, II_PHY_IDX, argc, argv, &cmd);\n\t\telse\n\t\t\tgoto detect;\n\t} else if (strcmp(*argv, \"wdev\") == 0 && argc > 1) {\n\t\targc--;\n\t\targv++;\n\t\terr = __handle_cmd(&nlstate, II_WDEV, argc, argv, &cmd);\n\t} else {\n\t\tint idx;\n\t\tenum id_input idby = II_NONE;\n detect:\n\t\tif ((idx = if_nametoindex(argv[0])) != 0)\n\t\t\tidby = II_NETDEV;\n\t\telse if ((idx = phy_lookup(argv[0])) >= 0)\n\t\t\tidby = II_PHY_NAME;\n\t\terr = __handle_cmd(&nlstate, idby, argc, argv, &cmd);\n\t}\n\n\tif (err == 1) {\n\t\tif (cmd)\n\t\t\tusage_cmd(cmd);\n\t\telse\n\t\t\tusage(0, NULL);\n\t} else if (err < 0)\n\t\tfprintf(stderr, \"command failed: %s (%d)\\n\", strerror(-err), err);\n\n\tnl80211_cleanup(&nlstate);\n\n\treturn err;\n}\n"
  },
  {
    "path": "user_space/sdrctl_src/sdrctl.h",
    "content": "/*\n * Author: Xianjun Jiao\n * SPDX-FileCopyrightText: 2019 UGent\n * SPDX-License-Identifier: AGPL-3.0-or-later\n*/\n\n#ifndef __IW_H\n#define __IW_H\n\n#include <stdbool.h>\n#include <netlink/netlink.h>\n#include <netlink/genl/genl.h>\n#include <netlink/genl/family.h>\n#include <netlink/genl/ctrl.h>\n#include <endian.h>\n\n#include \"nl80211.h\"\n//#include \"ieee80211.h\"\n\n#define ETH_ALEN 6\n\n/* libnl 1.x compatibility code */\n#if !defined(CONFIG_LIBNL20) && !defined(CONFIG_LIBNL30)\n#  define nl_sock nl_handle\n#endif\n\nstruct nl80211_state {\n\tstruct nl_sock *nl_sock;\n\tint nl80211_id;\n};\n\nenum command_identify_by {\n\tCIB_NONE,\n\tCIB_PHY,\n\tCIB_NETDEV,\n\tCIB_WDEV,\n};\n\nenum id_input {\n\tII_NONE,\n\tII_NETDEV,\n\tII_PHY_NAME,\n\tII_PHY_IDX,\n\tII_WDEV,\n};\n\nstruct cmd {\n\tconst char *name;\n\tconst char *args;\n\tconst char *help;\n\tconst enum nl80211_commands cmd;\n\tint nl_msg_flags;\n\tint hidden;\n\tconst enum command_identify_by idby;\n\t/*\n\t * The handler should return a negative error code,\n\t * zero on success, 1 if the arguments were wrong\n\t * and the usage message should and 2 otherwise.\n\t */\n\tint (*handler)(struct nl80211_state *state,\n\t\t       struct nl_cb *cb,\n\t\t       struct nl_msg *msg,\n\t\t       int argc, char **argv,\n\t\t       enum id_input id);\n\tconst struct cmd *(*selector)(int argc, char **argv);\n\tconst struct cmd *parent;\n};\n\n#define ARRAY_SIZE(ar) (sizeof(ar)/sizeof(ar[0]))\n#define DIV_ROUND_UP(x, y) (((x) + (y - 1)) / (y))\n\n#define __COMMAND(_section, _symname, _name, _args, _nlcmd, _flags, _hidden, _idby, _handler, _help, _sel)\\\n\tstatic struct cmd\t\t\t\t\t\t\\\n\t__cmd ## _ ## _symname ## _ ## _handler ## _ ## _nlcmd ## _ ## _idby ## _ ## _hidden\\\n\t__attribute__((used)) __attribute__((section(\"__cmd\")))\t= {\t\\\n\t\t.name = (_name),\t\t\t\t\t\\\n\t\t.args = (_args),\t\t\t\t\t\\\n\t\t.cmd = (_nlcmd),\t\t\t\t\t\\\n\t\t.nl_msg_flags = (_flags),\t\t\t\t\\\n\t\t.hidden = (_hidden),\t\t\t\t\t\\\n\t\t.idby = (_idby),\t\t\t\t\t\\\n\t\t.handler = (_handler),\t\t\t\t\t\\\n\t\t.help = (_help),\t\t\t\t\t\\\n\t\t.parent = _section,\t\t\t\t\t\\\n\t\t.selector = (_sel),\t\t\t\t\t\\\n\t}\n#define __ACMD(_section, _symname, _name, _args, _nlcmd, _flags, _hidden, _idby, _handler, _help, _sel, _alias)\\\n\t__COMMAND(_section, _symname, _name, _args, _nlcmd, _flags, _hidden, _idby, _handler, _help, _sel);\\\n\tstatic const struct cmd *_alias = &__cmd ## _ ## _symname ## _ ## _handler ## _ ## _nlcmd ## _ ## _idby ## _ ## _hidden\n#define COMMAND(section, name, args, cmd, flags, idby, handler, help)\t\\\n\t__COMMAND(&(__section ## _ ## section), name, #name, args, cmd, flags, 0, idby, handler, help, NULL)\n#define COMMAND_ALIAS(section, name, args, cmd, flags, idby, handler, help, selector, alias)\\\n\t__ACMD(&(__section ## _ ## section), name, #name, args, cmd, flags, 0, idby, handler, help, selector, alias)\n#define HIDDEN(section, name, args, cmd, flags, idby, handler)\t\t\\\n\t__COMMAND(&(__section ## _ ## section), name, #name, args, cmd, flags, 1, idby, handler, NULL, NULL)\n\n#define TOPLEVEL(_name, _args, _nlcmd, _flags, _idby, _handler, _help)\t\\\n\tstruct cmd\t\t\t\t\t\t\t\\\n\t__section ## _ ## _name\t\t\t\t\t\t\\\n\t__attribute__((used)) __attribute__((section(\"__cmd\")))\t= {\t\\\n\t\t.name = (#_name),\t\t\t\t\t\\\n\t\t.args = (_args),\t\t\t\t\t\\\n\t\t.cmd = (_nlcmd),\t\t\t\t\t\\\n\t\t.nl_msg_flags = (_flags),\t\t\t\t\\\n\t\t.idby = (_idby),\t\t\t\t\t\\\n\t\t.handler = (_handler),\t\t\t\t\t\\\n\t\t.help = (_help),\t\t\t\t\t\\\n\t }\n#define SECTION(_name)\t\t\t\t\t\t\t\\\n\tstruct cmd __section ## _ ## _name\t\t\t\t\\\n\t__attribute__((used)) __attribute__((section(\"__cmd\"))) = {\t\\\n\t\t.name = (#_name),\t\t\t\t\t\\\n\t\t.hidden = 1,\t\t\t\t\t\t\\\n\t}\n\n#define DECLARE_SECTION(_name)\t\t\t\t\t\t\\\n\textern struct cmd __section ## _ ## _name;\n\nextern const char sdrctl_version[];\n\nextern int iw_debug;\n\nint handle_cmd(struct nl80211_state *state, enum id_input idby,\n\t       int argc, char **argv);\n\nstruct print_event_args {\n\tstruct timeval ts; /* internal */\n\tbool have_ts; /* must be set false */\n\tbool frame, time, reltime;\n};\n\n__u32 listen_events(struct nl80211_state *state,\n\t\t    const int n_waits, const __u32 *waits);\nint __prepare_listen_events(struct nl80211_state *state);\n__u32 __do_listen_events(struct nl80211_state *state,\n\t\t\t const int n_waits, const __u32 *waits,\n\t\t\t struct print_event_args *args);\n\n\nint mac_addr_a2n(unsigned char *mac_addr, char *arg);\nvoid mac_addr_n2a(char *mac_addr, unsigned char *arg);\nint parse_hex_mask(char *hexmask, unsigned char **result, size_t *result_len,\n\t\t   unsigned char **mask);\nunsigned char *parse_hex(char *hex, size_t *outlen);\n\nint parse_keys(struct nl_msg *msg, char **argv, int argc);\n\nvoid print_ht_mcs(const __u8 *mcs);\nvoid print_ampdu_length(__u8 exponent);\nvoid print_ampdu_spacing(__u8 spacing);\nvoid print_ht_capability(__u16 cap);\nvoid print_vht_info(__u32 capa, const __u8 *mcs);\n\nchar *channel_width_name(enum nl80211_chan_width width);\nconst char *iftype_name(enum nl80211_iftype iftype);\nconst char *command_name(enum nl80211_commands cmd);\nint ieee80211_channel_to_frequency(int chan, enum nl80211_band band);\nint ieee80211_frequency_to_channel(int freq);\n\nvoid print_ssid_escaped(const uint8_t len, const uint8_t *data);\n\nint nl_get_multicast_id(struct nl_sock *sock, const char *family, const char *group);\n\nchar *reg_initiator_to_string(__u8 initiator);\n\nconst char *get_reason_str(uint16_t reason);\nconst char *get_status_str(uint16_t status);\n\nenum print_ie_type {\n\tPRINT_SCAN,\n\tPRINT_LINK,\n};\n\n#define BIT(x) (1ULL<<(x))\n\nvoid print_ies(unsigned char *ie, int ielen, bool unknown,\n\t       enum print_ie_type ptype);\n\nvoid parse_bitrate(struct nlattr *bitrate_attr, char *buf, int buflen);\nvoid iw_hexdump(const char *prefix, const __u8 *data, size_t len);\n\nDECLARE_SECTION(set);\nDECLARE_SECTION(get);\n\n#endif /* __IW_H */\n"
  },
  {
    "path": "user_space/sdrctl_src/sections.c",
    "content": "/*\n * Author: Xianjun Jiao\n * SPDX-FileCopyrightText: 2019 UGent\n * SPDX-License-Identifier: AGPL-3.0-or-later\n*/\n\n#include \"sdrctl.h\"\n\nSECTION(get);\nSECTION(set);\n"
  },
  {
    "path": "user_space/sdrctl_src/version.sh",
    "content": "#!/bin/sh\n\n# Author: Xianjun Jiao\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\nVERSION=\"3.17\"\nOUT=\"$1\"\n\nif [ -d .git ] && head=`git rev-parse --verify HEAD 2>/dev/null`; then\n\tgit update-index --refresh --unmerged > /dev/null\n\tdescr=$(git describe)\n\n\t# on git builds check that the version number above\n\t# is correct...\n\t[ \"${descr%%-*}\" = \"v$VERSION\" ] || exit 2\n\n\tv=\"${descr#v}\"\n\tif git diff-index --name-only HEAD | read dummy ; then\n\t\tv=\"$v\"-dirty\n\tfi\nelse\n\tv=\"$VERSION\"\nfi\n\necho '#include \"sdrctl.h\"' > \"$OUT\"\necho \"const char sdrctl_version[] = \\\"$v\\\";\" >> \"$OUT\"\n"
  },
  {
    "path": "user_space/set_dbg_ch0.sh",
    "content": "#!/bin/bash\n\nhome_dir=$(pwd)\n\nif test -d \"/sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\"; then\n  cd /sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\nelse \n  cd /sys/devices/soc0/fpga-axi\\@0/fpga-axi\\@0\\:sdr\nfi\n\n# set\nif [[ -n $1 ]]; then\n  echo $1 > dbg_ch0\nfi\n\n# show\ncat dbg_ch0\n\ncd $home_dir\n\n"
  },
  {
    "path": "user_space/set_dbg_ch1.sh",
    "content": "#!/bin/bash\n\nhome_dir=$(pwd)\n\nif test -d \"/sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\"; then\n  cd /sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\nelse \n  cd /sys/devices/soc0/fpga-axi\\@0/fpga-axi\\@0\\:sdr\nfi\n\n# set\nif [[ -n $1 ]]; then\n  echo $1 > dbg_ch1\nfi\n\n# show\ncat dbg_ch1\n\ncd $home_dir\n\n"
  },
  {
    "path": "user_space/set_dbg_ch2.sh",
    "content": "#!/bin/bash\n\nhome_dir=$(pwd)\n\nif test -d \"/sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\"; then\n  cd /sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\nelse \n  cd /sys/devices/soc0/fpga-axi\\@0/fpga-axi\\@0\\:sdr\nfi\n\n# set\nif [[ -n $1 ]]; then\n  echo $1 > dbg_ch2\nfi\n\n# show\ncat dbg_ch2\n\ncd $home_dir\n\n"
  },
  {
    "path": "user_space/set_lbt_th.sh",
    "content": "#!/bin/bash\n\nif [[ -n $1 ]]; then\n  lbt_th=$1\nelse\n  lbt_th=987654321 # no input\nfi\n\nset -x\n#set\nif [ $lbt_th -ne 987654321 ]; then\n  ./sdrctl dev sdr0 set reg drv_xpu 0 $lbt_th\nfi\n\n# show\n# ./sdrctl dev sdr0 get reg xpu 8 \n./sdrctl dev sdr0 get reg drv_xpu 0\nset +x\n"
  },
  {
    "path": "user_space/set_restrict_freq.sh",
    "content": "#!/bin/bash\n\nhome_dir=$(pwd)\n\nif test -d \"/sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\"; then\n  cd /sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\nelse \n  cd /sys/devices/soc0/fpga-axi\\@0/fpga-axi\\@0\\:sdr\nfi\n\n# set\nif [[ -n $1 ]]; then\n  echo $1 > restrict_freq_mhz\nfi\n\n# show\ncat restrict_freq_mhz\n\ncd $home_dir\n\n"
  },
  {
    "path": "user_space/set_rx_gain_auto.sh",
    "content": "#!/bin/sh\n\n# Author: Xianjun Jiao\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\nhome_dir=$(pwd)\n\nset -x\nif test -f \"/sys/bus/iio/devices/iio:device0/in_voltage_rf_bandwidth\"; then\n  cd /sys/bus/iio/devices/iio:device0/\nelse if test -f \"/sys/bus/iio/devices/iio:device1/in_voltage_rf_bandwidth\"; then\n       cd /sys/bus/iio/devices/iio:device1/\n     else if test -f \"/sys/bus/iio/devices/iio:device2/in_voltage_rf_bandwidth\"; then\n            cd /sys/bus/iio/devices/iio:device2/\n          else if test -f \"/sys/bus/iio/devices/iio:device3/in_voltage_rf_bandwidth\"; then\n                 cd /sys/bus/iio/devices/iio:device3/\n               else if test -f \"/sys/bus/iio/devices/iio:device4/in_voltage_rf_bandwidth\"; then\n                      cd /sys/bus/iio/devices/iio:device4/\n                    else\n                      echo \"Can not find in_voltage_rf_bandwidth!\"\n                      echo \"Check log to make sure ad9361 driver is loaded!\"\n                      exit 1\n                    fi\n               fi\n          fi\n     fi\nfi\n\necho fast_attack > in_voltage0_gain_control_mode\ncat in_voltage0_gain_control_mode\ncat in_voltage0_hardwaregain\n\nif test -f \"/sys/kernel/debug/iio/iio:device0/direct_reg_access\"; then\n  cd /sys/kernel/debug/iio/iio:device0/\nelse if test -f \"/sys/kernel/debug/iio/iio:device1/direct_reg_access\"; then\n       cd /sys/kernel/debug/iio/iio:device1/\n     else if test -f \"/sys/kernel/debug/iio/iio:device2/direct_reg_access\"; then\n            cd /sys/kernel/debug/iio/iio:device2/\n          else if test -f \"/sys/kernel/debug/iio/iio:device3/direct_reg_access\"; then\n                 cd /sys/kernel/debug/iio/iio:device3/\n               else if test -f \"/sys/kernel/debug/iio/iio:device4/direct_reg_access\"; then\n                      cd /sys/kernel/debug/iio/iio:device4/\n                    else\n                      echo \"Can not find direct_reg_access!\"\n                      echo \"Check log to make sure ad9361 driver is loaded!\"\n                      exit 1\n                    fi\n               fi\n          fi\n     fi\nfi\n\necho 0x0fa 0x5 > direct_reg_access\necho 0x0fa 0xE5 > direct_reg_access\n\ncd $home_dir\n\nset +x\n"
  },
  {
    "path": "user_space/set_rx_gain_manual.sh",
    "content": "#!/bin/sh\n\n# Author: Xianjun Jiao\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\ngain_dB=$1\nif [ -z $gain_dB ]\nthen\n  gain_dB=0\nfi\n\nhome_dir=$(pwd)\n\nset -x\nif test -f \"/sys/bus/iio/devices/iio:device0/in_voltage_rf_bandwidth\"; then\n  cd /sys/bus/iio/devices/iio:device0/\nelse if test -f \"/sys/bus/iio/devices/iio:device1/in_voltage_rf_bandwidth\"; then\n       cd /sys/bus/iio/devices/iio:device1/\n     else if test -f \"/sys/bus/iio/devices/iio:device2/in_voltage_rf_bandwidth\"; then\n            cd /sys/bus/iio/devices/iio:device2/\n          else if test -f \"/sys/bus/iio/devices/iio:device3/in_voltage_rf_bandwidth\"; then\n                 cd /sys/bus/iio/devices/iio:device3/\n               else if test -f \"/sys/bus/iio/devices/iio:device4/in_voltage_rf_bandwidth\"; then\n                      cd /sys/bus/iio/devices/iio:device4/\n                    else\n                      echo \"Can not find in_voltage_rf_bandwidth!\"\n                      echo \"Check log to make sure ad9361 driver is loaded!\"\n                      exit 1\n                    fi\n               fi\n          fi\n     fi\nfi\n\necho manual > in_voltage0_gain_control_mode\ncat in_voltage0_gain_control_mode\n\nif [ $gain_dB -gt 0 ]; then\n  echo $gain_dB > in_voltage0_hardwaregain\nfi\n\ncat in_voltage0_hardwaregain\n\ncd $home_dir\n\nset +x\n"
  },
  {
    "path": "user_space/set_rx_monitor_all.sh",
    "content": "#!/bin/bash\n\nhome_dir=$(pwd)\n\nif test -d \"/sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\"; then\n  cd /sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\nelse \n  cd /sys/devices/soc0/fpga-axi\\@0/fpga-axi\\@0\\:sdr\nfi\n\nset -x\n# set\nif [[ -n $1 ]]; then\n  echo $1 > rx_monitor_all\nelse\n  echo 1 > rx_monitor_all\nfi\n\n# show\ncat rx_monitor_all\nset +x\n\ncd $home_dir\n\n"
  },
  {
    "path": "user_space/set_rx_target_sender_mac_addr.sh",
    "content": "#!/bin/bash\n\nhome_dir=$(pwd)\n\nif test -d \"/sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\"; then\n  cd /sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\nelse \n  cd /sys/devices/soc0/fpga-axi\\@0/fpga-axi\\@0\\:sdr\nfi\n\nset -x\n# set\nif [[ -n $1 ]]; then\n  echo $1 > rx_target_sender_mac_addr\nfi\n\n# show\ncat rx_target_sender_mac_addr\nset +x\n\ncd $home_dir\n\n"
  },
  {
    "path": "user_space/set_tx_lo.sh",
    "content": "#!/bin/bash\n\nset -x\nif test -f \"/sys/kernel/debug/iio/iio:device0/direct_reg_access\"; then\n  cd /sys/kernel/debug/iio/iio:device0/\nelse if test -f \"/sys/kernel/debug/iio/iio:device1/direct_reg_access\"; then\n       cd /sys/kernel/debug/iio/iio:device1/\n     else if test -f \"/sys/kernel/debug/iio/iio:device2/direct_reg_access\"; then\n            cd /sys/kernel/debug/iio/iio:device2/\n          else if test -f \"/sys/kernel/debug/iio/iio:device3/direct_reg_access\"; then\n                 cd /sys/kernel/debug/iio/iio:device3/\n               else if test -f \"/sys/kernel/debug/iio/iio:device4/direct_reg_access\"; then\n                      cd /sys/kernel/debug/iio/iio:device4/\n                    else\n                      echo \"Can not find direct_reg_access!\"\n                      echo \"Check log to make sure ad9361 driver is loaded!\"\n                      exit 1\n                    fi\n               fi\n          fi\n     fi\nfi\nset +x\n\nif [ \"$#\" -eq 1 ]; then\n  if [ $1 == \"0\" ]; then \n\t  echo 0x051 0x10 > direct_reg_access\n\t  status=$( cat direct_reg_access )\n\t  if [ $status == \"0x10\" ]; then\n\t\t  echo \"Tx LO turned off\"\n\t  else\n\t\t  echo \"WARNING: turning Tx LO off unsuccessful\"\n\t  fi \n  elif [ $1 == \"1\" ]; then\n    echo 0x051 0x0 > direct_reg_access\n\t  status=$( cat direct_reg_access )\n    if [ $status == \"0x0\" ]; then\n\t\t  echo \"Tx LO turned on\"\n\t  else\n\t\t  echo \"WARNING: turning Tx LO on unsuccessful\"\n    fi \n  fi\nelif [ \"$#\" -eq 0 ]; then\n\t\techo \"Reading status only. Enter 1 or 0 as argument to set Tx LO on or off.\"\n    echo 0x051 > direct_reg_access\n    status=$( cat direct_reg_access )\n    if [ $status == \"0x10\" ]; then\n\t\t  echo \"Tx LO is off\"\n    elif [ $status == \"0x0\" ]; then\n      echo \"Tx LO is on\"\n    else\n      echo \"WARNING Unrecognized value $status.\"\n    fi  \nelse\n  echo \"Too many arguments, specify only one for turning on (1) or off (0) the Tx LO.\"\nfi\n"
  },
  {
    "path": "user_space/set_tx_port.sh",
    "content": "#!/bin/bash\n\nset -x\nif test -f \"/sys/kernel/debug/iio/iio:device0/direct_reg_access\"; then\n  cd /sys/kernel/debug/iio/iio:device0/\nelse if test -f \"/sys/kernel/debug/iio/iio:device1/direct_reg_access\"; then\n       cd /sys/kernel/debug/iio/iio:device1/\n     else if test -f \"/sys/kernel/debug/iio/iio:device2/direct_reg_access\"; then\n            cd /sys/kernel/debug/iio/iio:device2/\n          else if test -f \"/sys/kernel/debug/iio/iio:device3/direct_reg_access\"; then\n                 cd /sys/kernel/debug/iio/iio:device3/\n               else if test -f \"/sys/kernel/debug/iio/iio:device4/direct_reg_access\"; then\n                      cd /sys/kernel/debug/iio/iio:device4/\n                    else\n                      echo \"Can not find direct_reg_access!\"\n                      echo \"Check log to make sure ad9361 driver is loaded!\"\n                      exit 1\n                    fi\n               fi\n          fi\n     fi\nfi\nset +x\n\nif [ \"$#\" -eq 1 ]; then\n  if [ $1 == \"0\" ]; then \n\t  echo 0x004 0x43 > direct_reg_access\n\t  status=$( cat direct_reg_access )\n\t  if [ $status == \"0x43\" ]; then\n\t\t  echo \"Tx port B selected.\"\n\t  else\n\t\t  echo \"WARNING: switching Tx port B unsuccessful\"\n\t  fi \n  elif [ $1 == \"1\" ]; then\n    echo 0x004 0x3 > direct_reg_access\n\t  status=$( cat direct_reg_access )\n    if [ $status == \"0x3\" ]; then\n\t\t  echo \"Tx port A selected.\"\n\t  else\n\t\t  echo \"WARNING: switching Tx port A unsuccessful\"\n    fi \n  fi\nelif [ \"$#\" -eq 0 ]; then\n\t\techo \"Reading status only. Enter 1 or 0 as argument to select port A or B.\"\n    echo 0x004 > direct_reg_access\n    status=$( cat direct_reg_access )\n    if [ $status == \"0x43\" ]; then\n\t\t  echo \"Tx port B is used\"\n    elif [ $status == \"0x3\" ]; then\n      echo \"Tx port A is used\"\n    else\n      echo \"WARNING Unrecognized value $status.\"\n    fi  \nelse\n  echo \"Too many arguments, specify only one for selecting port A (1) or B (0).\"\nfi\n"
  },
  {
    "path": "user_space/setup_once.sh",
    "content": "#!/bin/bash\n\n# Author: Xianjun Jiao\n# SPDX-FileCopyrightText: 2023 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\nset -ex\n\ncd /root/\n\nMACHINE_TYPE=`uname -m`\n\nrm -rf kernel_modules\nmkdir -p kernel_modules\n\n# mkdir -p /lib/modules/$(uname -r)\n# rm -rf /lib/modules/$(uname -r)\nif [ ${MACHINE_TYPE} == 'aarch64' ]; then\n  cp /root/kernel_modules64/* /root/kernel_modules/\n  cp /root/openwifi64/* /root/openwifi/\n    # cp ./kernel_modules64/* /lib/modules/$(uname -r)/\nelse\n  cp /root/kernel_modules32/* /root/kernel_modules/\n  cp /root/openwifi32/* /root/openwifi/\n    # cp ./kernel_modules32/* /lib/modules/$(uname -r)/\nfi\n\n# Decide board name\nDEVICE_TREE_MODEL_STRING=$(cat /proc/device-tree/model)\nif [[ $DEVICE_TREE_MODEL_STRING == *\"ADRV9361-Z7035\"* ]]; then\n  BOARD_NAME=adrv9361z7035\nelif [[ $DEVICE_TREE_MODEL_STRING == *\"ADRV9364-Z7020\"* ]]; then\n  BOARD_NAME=adrv9364z7020\nelif [[ $DEVICE_TREE_MODEL_STRING == *\"ANTSDR-E310V2\"* ]]; then\n  BOARD_NAME=e310v2\nelif [[ $DEVICE_TREE_MODEL_STRING == *\"ANTSDR-E310\"* ]]; then\n  BOARD_NAME=antsdr\nelif [[ $DEVICE_TREE_MODEL_STRING == *\"ANTSDR-E200\"* ]]; then\n  BOARD_NAME=antsdr_e200\nelif [[ $DEVICE_TREE_MODEL_STRING == *\"neptunesdr\"* ]]; then\n  BOARD_NAME=neptunesdr\nelif [[ $DEVICE_TREE_MODEL_STRING == *\"sdrpi\"* ]]; then\n  BOARD_NAME=sdrpi\nelif [[ $DEVICE_TREE_MODEL_STRING == *\"ZC702\"* ]]; then\n  BOARD_NAME=zc702_fmcs2\nelif [[ $DEVICE_TREE_MODEL_STRING == *\"ZC706\"* ]]; then\n  BOARD_NAME=zc706_fmcs2\nelif [[ $DEVICE_TREE_MODEL_STRING == *\"ZCU102\"* ]]; then\n  BOARD_NAME=zcu102_fmcs2\nelif [[ $DEVICE_TREE_MODEL_STRING == *\"ZED\"* ]]; then\n  BOARD_NAME=zed_fmcs2\nelse\n  echo $DEVICE_TREE_MODEL_STRING \" NOT recognized!\"\n  exit 1\nfi\n\nmv /root/kernel_modules/ad9361_drv.ko /root/openwifi/ -f || true\nmv /root/kernel_modules/adi_axi_hdmi.ko /root/openwifi/ -f || true\nmv /root/kernel_modules/axidmatest.ko /root/openwifi/ -f || true\nmv /root/kernel_modules/lcd.ko /root/openwifi/ -f || true\nmv /root/kernel_modules/xilinx_dma.ko /root/openwifi/ -f || true\n\nrm -rf /lib/modules/$(uname -r)\nln -s /root/kernel_modules /lib/modules/$(uname -r)\nsync\ndepmod\n\necho $BOARD_NAME\ncp /root/openwifi_BOOT/$BOARD_NAME/system_top.bit.bin /root/openwifi/ -f || true\n\ncd /root/openwifi/sdrctl_src\nmake clean\nmake\ncp sdrctl /root/openwifi/\ncd /root/openwifi/side_ch_ctl_src/\ngcc -o side_ch_ctl side_ch_ctl.c\ncp side_ch_ctl /root/openwifi/\ncd /root/openwifi/inject_80211/\nmake clean\nmake\ncd ..\nsync\n\n# reboot now\n"
  },
  {
    "path": "user_space/side_ch_ctl_src/iq_capture.py",
    "content": "#\n# openwifi side info receive and display program\n# Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be\n#\nimport os\nimport sys\nimport socket\nimport numpy as np\nimport matplotlib\nmatplotlib.use('TkAgg')\nimport matplotlib.pyplot as plt\n\ndef display_iq(iq_capture, agc_gain, rssi_half_db, ch_idle, demod, tx_rf, fcs_ok):\n   \n    fig_iq_capture = plt.figure(0)\n    fig_iq_capture.clf()\n    plt.xlabel(\"sample\")\n    # plt.ylabel(\"I/Q\")\n    # plt.title(\"I (blue) and Q (red) capture\")\n    plt.plot(iq_capture.real, 'b')\n    plt.plot(iq_capture.imag, 'r')\n    plt.plot(30000+fcs_ok*3000, 'k-', label='fcs_ok')\n    plt.plot(27000+demod*3000, 'r--', label='demod')\n    plt.plot(-30000+tx_rf*3000, 'g-', label='tx_rf')\n    plt.plot(-33000+ch_idle*3000, 'b--', label='ch_idle')\n    plt.ylim(-34000, 34000)\n    plt.legend(loc='upper right')\n    plt.grid()\n    fig_iq_capture.canvas.flush_events()\n\n    agc_gain_lock = np.copy(agc_gain)\n    agc_gain_lock[agc_gain>127] = 80 # agc lock\n    agc_gain_lock[agc_gain<=127] = 0 # agc not lock\n\n    agc_gain_value = np.copy(agc_gain)\n    agc_gain_value[agc_gain>127] = agc_gain[agc_gain>127] - 128\n\n    fig_agc_gain = plt.figure(1)\n    fig_agc_gain.clf()\n    plt.xlabel(\"sample\")\n    plt.ylabel(\"gain/lock\")\n    # plt.title(\"AGC gain (blue) and lock status (red)\")\n    plt.plot(agc_gain_value, 'b', label='gain')\n    plt.plot(agc_gain_lock, 'r', label='lock')\n    plt.ylim(0, 82)\n    plt.legend(loc='upper right')\n    fig_agc_gain.canvas.flush_events()\n\n    fig_rssi_half_db = plt.figure(2)\n    fig_rssi_half_db.clf()\n    plt.xlabel(\"sample\")\n    plt.ylabel(\"dB\")\n    plt.title(\"RSSI half dB (uncalibrated)\")\n    plt.plot(rssi_half_db)\n    plt.ylim(100, 270)\n    fig_rssi_half_db.canvas.flush_events()\n\ndef parse_iq(iq, iq_len):\n    # print(len(iq), iq_len)\n    num_dma_symbol_per_trans = 1 + iq_len\n    num_int16_per_trans = num_dma_symbol_per_trans*4 # 64bit per dma symbol\n    num_trans = round(len(iq)/num_int16_per_trans)\n    # print(len(iq), iq.dtype, num_trans)\n    iq = iq.reshape([num_trans, num_int16_per_trans])\n    \n    timestamp = iq[:,0] + pow(2,16)*iq[:,1] + pow(2,32)*iq[:,2] + pow(2,48)*iq[:,3]\n    iq_capture = np.int16(iq[:,4::4]) + np.int16(iq[:,5::4])*1j\n    agc_gain = np.bitwise_and(iq[:,6::4], np.uint16(0xFF))\n    rssi_half_db = np.bitwise_and(iq[:,7::4], np.uint16(0x7FF))\n    # print(num_trans, iq_len, iq_capture.shape, agc_gain.shape, rssi_half_db.shape)\n\n    ch_idle = np.right_shift(np.bitwise_and(iq[:,6::4], np.uint16(0x8000)), 15)\n    demod = np.right_shift(np.bitwise_and(iq[:,7::4], np.uint16(0x8000)), 15)\n    tx_rf = np.right_shift(np.bitwise_and(iq[:,7::4], np.uint16(0x4000)), 14)\n    fcs_ok = np.right_shift(np.bitwise_and(iq[:,7::4], np.uint16(0x2000)), 13)\n\n    # iq_capture = iq_capture.reshape([num_trans*iq_len,])\n    # agc_gain = agc_gain.reshape([num_trans*iq_len,])\n    # rssi_half_db = rssi_half_db.reshape([num_trans*iq_len,])\n\n    return timestamp, iq_capture, agc_gain, rssi_half_db, ch_idle, demod, tx_rf, fcs_ok\n\nUDP_IP = \"192.168.10.1\" #Local IP to listen\nUDP_PORT = 4000         #Local port to listen\n\nsock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) # UDP\nsock.bind((UDP_IP, UDP_PORT))\nsock.setsockopt(socket.SOL_SOCKET, socket.SO_RCVBUF, 464) # for low latency. 464 is the minimum udp length in our case (CSI only)\n\n# align with side_ch_control.v and all related user space, remote files\nMAX_NUM_DMA_SYMBOL = 8192\n\nif len(sys.argv)<2:\n    print(\"Assume iq_len = 8187! (Max UDP 65507 bytes; (65507/8)-1 = 8187)\")\n    iq_len = 8187\nelse:\n    iq_len = int(sys.argv[1])\n    print(iq_len)\n    # print(type(num_eq))\n\nif iq_len>8187:\n    iq_len = 8187\n    print('Limit iq_len to 8187! (Max UDP 65507 bytes; (65507/8)-1 = 8187)')\n\nnum_dma_symbol_per_trans = 1 + iq_len\nnum_byte_per_trans = 8*num_dma_symbol_per_trans\n\nif os.path.exists(\"iq.txt\"):\n    os.remove(\"iq.txt\")\niq_fd=open('iq.txt','a')\n\nplt.ion()\n\nwhile True:\n    try:\n        data, addr = sock.recvfrom(MAX_NUM_DMA_SYMBOL*8) # buffer size\n        # print(addr)\n        test_residual = len(data)%num_byte_per_trans\n        # print(len(data)/8, num_dma_symbol_per_trans, test_residual)\n        if (test_residual != 0):\n            print(\"Abnormal length\")\n\n        iq = np.frombuffer(data, dtype='uint16')\n        np.savetxt(iq_fd, iq)\n\n        timestamp, iq_capture, agc_gain, rssi_half_db, ch_idle, demod, tx_rf, fcs_ok = parse_iq(iq, iq_len)\n        print(timestamp)\n        display_iq(iq_capture[0,:], agc_gain[0,:], rssi_half_db[0,:], ch_idle[0,:], demod[0,:], tx_rf[0,:], fcs_ok[0,:])\n        # plt.waitforbuttonpress()\n\n    except KeyboardInterrupt:\n        print('User quit')\n        break\n\nprint('close()')\niq_fd.close()\nsock.close()\n"
  },
  {
    "path": "user_space/side_ch_ctl_src/iq_capture_2ant.py",
    "content": "#\n# openwifi side info receive and display program\n# Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be\n#\nimport os\nimport sys\nimport socket\nimport numpy as np\nimport matplotlib.pyplot as plt\n\ndef display_iq(iq0_capture, iq1_capture):\n    fig_iq_capture = plt.figure(0)\n    fig_iq_capture.clf()\n\n    ax_iq0 = fig_iq_capture.add_subplot(211)\n    # ax_iq0.set_xlabel(\"sample\")\n    ax_iq0.set_ylabel(\"I/Q\")\n    ax_iq0.set_title(\"rx0 I/Q\")\n    plt.plot(iq0_capture.real)\n    plt.plot(iq0_capture.imag)\n    plt.ylim(-32767, 32767)\n\n    ax_iq1 = fig_iq_capture.add_subplot(212)\n    ax_iq1.set_xlabel(\"sample\")\n    ax_iq1.set_ylabel(\"I/Q\")\n    ax_iq1.set_title(\"rx1 I/Q\")\n    plt.plot(iq1_capture.real)\n    plt.plot(iq1_capture.imag)\n    plt.ylim(-32767, 32767)\n    fig_iq_capture.canvas.flush_events()\n\ndef parse_iq(iq, iq_len):\n    # print(len(iq), iq_len)\n    num_dma_symbol_per_trans = 1 + iq_len\n    num_int16_per_trans = num_dma_symbol_per_trans*4 # 64bit per dma symbol\n    num_trans = round(len(iq)/num_int16_per_trans)\n    # print(len(iq), iq.dtype, num_trans)\n    iq = iq.reshape([num_trans, num_int16_per_trans])\n    \n    timestamp = iq[:,0] + pow(2,16)*iq[:,1] + pow(2,32)*iq[:,2] + pow(2,48)*iq[:,3]\n    iq0_capture = np.int16(iq[:,4::4]) + np.int16(iq[:,5::4])*1j\n    iq1_capture = np.int16(iq[:,6::4]) + np.int16(iq[:,7::4])*1j\n    # print(num_trans, iq_len, iq0_capture.shape, iq1_capture.shape)\n\n    # iq0_capture = iq0_capture.reshape([num_trans*iq_len,])\n    # iq1_capture = iq1_capture.reshape([num_trans*iq_len,])\n    iq0_capture = np.transpose(iq0_capture)\n    iq1_capture = np.transpose(iq1_capture)\n\n    return timestamp, iq0_capture, iq1_capture\n\nUDP_IP = \"192.168.10.1\" #Local IP to listen\nUDP_PORT = 4000         #Local port to listen\n\nsock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) # UDP\nsock.bind((UDP_IP, UDP_PORT))\nsock.setsockopt(socket.SOL_SOCKET, socket.SO_RCVBUF, 464) # for low latency. 464 is the minimum udp length in our case (CSI only)\n\n# align with side_ch_control.v and all related user space, remote files\nMAX_NUM_DMA_SYMBOL = 8192\n\nif len(sys.argv)<2:\n    print(\"Assume iq_len = 8187! (Max UDP 65507 bytes; (65507/8)-1 = 8187)\")\n    iq_len = 8187\nelse:\n    iq_len = int(sys.argv[1])\n    print(iq_len)\n    # print(type(num_eq))\n\nif iq_len>8187:\n    iq_len = 8187\n    print('Limit iq_len to 8187! (Max UDP 65507 bytes; (65507/8)-1 = 8187)')\n\nnum_dma_symbol_per_trans = 1 + iq_len\nnum_byte_per_trans = 8*num_dma_symbol_per_trans\n\nif os.path.exists(\"iq_2ant.txt\"):\n    os.remove(\"iq_2ant.txt\")\niq_fd=open('iq_2ant.txt','a')\n\nplt.ion()\n\nwhile True:\n    try:\n        data, addr = sock.recvfrom(MAX_NUM_DMA_SYMBOL*8) # buffer size\n        # print(addr)\n        test_residual = len(data)%num_byte_per_trans\n        # print(len(data)/8, num_dma_symbol_per_trans, test_residual)\n        if (test_residual != 0):\n            print(\"Abnormal length\")\n\n        iq = np.frombuffer(data, dtype='uint16')\n        np.savetxt(iq_fd, iq)\n\n        timestamp, iq0_capture, iq1_capture = parse_iq(iq, iq_len)\n        display_iq(iq0_capture, iq1_capture)\n        # print(timestamp, max(max(iq0_capture.real)), max(max(iq1_capture.real)))\n        tmp0 = np.asmatrix(iq0_capture)\n        tmp1 = np.asmatrix(iq1_capture)\n        print(timestamp, tmp0.max(), tmp1.max())\n\n    except KeyboardInterrupt:\n        print('User quit')\n        break\n\nprint('close()')\niq_fd.close()\nsock.close()\n"
  },
  {
    "path": "user_space/side_ch_ctl_src/iq_capture_freq_offset.py",
    "content": "#\n# openwifi iq capture and frequency offset calculation program\n# Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be\n#\n# ATTENTION! If you can see the packet matched by addr1&addr2, most probably fpga and ltf FO estimation will be the same\n# For those cases where fpga FO estimation is wrong, you won't see them.\n# So, the value of this script is to show the correct/same FO estimation for overriding it into the receiver for performance check\n# By script receiver_phase_offset_override.sh\n# \n# Need these commands on board, after setup communication and know MAC addr of both sides\n# insmod side_ch.ko iq_len_init=1000\n# ./side_ch_ctl wh11d997\n# ./side_ch_ctl wh7h635c982f\n# ./side_ch_ctl wh6h44332236\n# ./side_ch_ctl wh1h6001\n# ./side_ch_ctl wh8d25\n# ./side_ch_ctl g0\n# # (In the case of totally clean/non-standard channel, long preamble detected can also be used as trigger ./side_ch_ctl wh8d8)\n\n# On host PC\n# python3 iq_capture_freq_offset.py 1000\n# It will print phase_offset value: FPGA VS python\n# You can override this correct vlaue to receiver via receiver_phase_offset_override.sh on board.\n\nimport os\nimport sys\nimport socket\nimport numpy as np\n# import matplotlib.pyplot as plt\nimport matplotlib\nmatplotlib.use('TkAgg')\nimport matplotlib.pyplot as plt\n\nmetric_plot_enable = True\n\n# Decided by ATAN_LUT_SCALE_SHIFT in common_defs.v\n# Different for master(11a/g/n) and 80211ax!!!\nLUT_SIZE = 512.0 # master(11a/g/n)\n# LUT_SIZE = 4096.0 # 80211ax\n\nfreq_offset_fpga_store = np.zeros(64,)\nfreq_offset_ltf_store = np.zeros(64,)\n\ndef phase_offset_to_freq_offset(phase_offset):\n    freq_offset = (20.0e6*phase_offset/LUT_SIZE)/(2.0*3.14159265358979323846)\n    return freq_offset\n\ndef plot_agc_gain(agc_gain):\n    num_trans = np.shape(agc_gain)[0]\n\n    fig_agc_gain = plt.figure(2)\n    fig_agc_gain.clf()\n    plt.xlabel(\"sample\")\n    plt.ylabel(\"gain/lock\")\n    # plt.title(\"AGC gain (blue) and lock status (red)\")\n    \n    for i in range(num_trans):\n      agc_gain_tmp = agc_gain[i,:]\n      agc_gain_lock = np.copy(agc_gain_tmp)\n      agc_gain_lock[agc_gain_tmp>127] = 80 # agc lock\n      agc_gain_lock[agc_gain_tmp<=127] = 0 # agc not lock\n\n      agc_gain_value = np.copy(agc_gain_tmp)\n      agc_gain_value[agc_gain_tmp>127] = agc_gain_tmp[agc_gain_tmp>127] - 128\n      plt.plot(agc_gain_value, label='gain')\n      plt.plot(agc_gain_lock, label='lock')\n      plt.legend(loc='upper right')\n\n    plt.ylim(0, 82)\n    fig_agc_gain.canvas.flush_events()\n\ndef plot_phase_offset(phase_offset_fpga, phase_offset_ltf):\n    freq_offset_fpga = phase_offset_to_freq_offset(phase_offset_fpga)\n    freq_offset_ltf = phase_offset_to_freq_offset(phase_offset_ltf)\n\n    for i in range(len(phase_offset_fpga)):\n      freq_offset_fpga_store[:(64-1)] = freq_offset_fpga_store[1:]\n      freq_offset_fpga_store[(64-1):] = freq_offset_fpga[i]\n      freq_offset_ltf_store[:(64-1)] = freq_offset_ltf_store[1:]\n      freq_offset_ltf_store[(64-1):] = freq_offset_ltf[i]\n\n    fig_fo_log = plt.figure(1)\n    fig_fo_log.clf()\n    plt.xlabel(\"capture idx\")\n    plt.plot(freq_offset_fpga_store, 'b.-', label='FPGA')\n    plt.plot(freq_offset_ltf_store, 'r.-', label='python LTF')\n    plt.legend(loc='upper right')\n    fig_fo_log.canvas.flush_events()\n\ndef ltf_freq_offset_estimation(iq_capture, start_idx_demod_is_ongoing):\n    num_trans = np.shape(iq_capture)[0]\n    phase_offset_ltf = np.zeros(num_trans,)\n\n    if metric_plot_enable:\n      fig_metric = plt.figure(0)\n      fig_metric.clf()\n      plt.xlabel(\"sample\")\n    \n    for i in range(num_trans):\n      iq = iq_capture[i, 0:-65]\n      iq_delay = iq_capture[i, 64:-1]\n      # iq_delay_conj_prod = np.multiply(iq_delay, np.conj(iq))\n      iq_delay_conj_prod = np.multiply(np.conj(iq_delay), iq)\n      iq_delay_conj_prod_mv_sum = np.convolve(iq_delay_conj_prod, np.ones(32,), 'valid')\n      iq_delay_conj_prod_mv_sum_power = np.real(np.multiply(np.conj(iq_delay_conj_prod_mv_sum),iq_delay_conj_prod_mv_sum))\n\n      # # --------------- old method\n      # iq_delay_conj_prod_power = np.real(np.multiply(np.conj(iq_delay_conj_prod),iq_delay_conj_prod))\n      # iq_delay_conj_prod_power_mv_sum = np.convolve(iq_delay_conj_prod_power, np.ones(32,), 'valid')\n      # metric_normalized = iq_delay_conj_prod_mv_sum_power/iq_delay_conj_prod_power_mv_sum\n\n      # max_idx_metric_normalized = np.argmax(metric_normalized)\n      # phase_offset_ltf[i] = np.angle(iq_delay_conj_prod_mv_sum[max_idx_metric_normalized])*8.0\n\n      # # --------------- new method\n      if start_idx_demod_is_ongoing[i] > 100:\n        base_idx = start_idx_demod_is_ongoing[i]-100\n        max_idx = np.argmax(iq_delay_conj_prod_mv_sum_power[base_idx:start_idx_demod_is_ongoing[i]])\n        phase_offset_ltf[i] = np.angle(iq_delay_conj_prod_mv_sum[base_idx+max_idx])*LUT_SIZE/64.0\n      else:\n        phase_offset_ltf[i] = np.inf\n        \n      if metric_plot_enable:\n        # plt.plot(metric_normalized)\n        plt.plot(iq_delay_conj_prod_mv_sum_power, label='metric')\n\n        iq_power = np.real(np.multiply(np.conj(iq),iq))\n        iq_total_power = np.sum(iq_power)\n        iq_power_mv_sum = np.convolve(iq_power, np.ones(32,), 'valid')\n        iq_power_normalized = 500.0*iq_power_mv_sum/iq_total_power\n        # plt.plot(iq_power_normalized)\n        plt.plot(iq_power*1e10, label='iq power')\n        plt.legend(loc='upper right')\n\n    if metric_plot_enable:\n      fig_metric.canvas.flush_events()\n\n    return phase_offset_ltf\n\n    # fig_iq_capture = plt.figure(0)\n    # fig_iq_capture.clf()\n    # plt.xlabel(\"sample\")\n    # plt.ylabel(\"I/Q\")\n    # plt.title(\"I (blue) and Q (red) capture\")\n    # plt.plot(iq_capture.real, 'b')\n    # plt.plot(iq_capture.imag, 'r')\n    # plt.ylim(-32767, 32767)\n    # fig_iq_capture.canvas.flush_events()\n\n    # agc_gain_lock = np.copy(agc_gain)\n    # agc_gain_lock[agc_gain>127] = 80 # agc lock\n    # agc_gain_lock[agc_gain<=127] = 0 # agc not lock\n\n    # agc_gain_value = np.copy(agc_gain)\n    # agc_gain_value[agc_gain>127] = agc_gain[agc_gain>127] - 128\n\n    # fig_agc_gain = plt.figure(1)\n    # fig_agc_gain.clf()\n    # plt.xlabel(\"sample\")\n    # plt.ylabel(\"gain/lock\")\n    # plt.title(\"AGC gain (blue) and lock status (red)\")\n    # plt.plot(agc_gain_value, 'b')\n    # plt.plot(agc_gain_lock, 'r')\n    # plt.ylim(0, 82)\n    # fig_agc_gain.canvas.flush_events()\n\n    # fig_rssi_half_db = plt.figure(2)\n    # fig_rssi_half_db.clf()\n    # plt.xlabel(\"sample\")\n    # plt.ylabel(\"dB\")\n    # plt.title(\"RSSI half dB (uncalibrated)\")\n    # plt.plot(rssi_half_db)\n    # plt.ylim(100, 270)\n    # fig_rssi_half_db.canvas.flush_events()\n\ndef parse_iq(iq, iq_len):\n    # print(len(iq), iq_len)\n    num_dma_symbol_per_trans = 1 + iq_len\n    num_int16_per_trans = num_dma_symbol_per_trans*4 # 64bit per dma symbol\n    num_trans = round(len(iq)/num_int16_per_trans)\n    # print(len(iq), iq.dtype, num_trans)\n    iq = iq.reshape([num_trans, num_int16_per_trans])\n    phase_offset_fpga = np.zeros(num_trans, dtype=np.int16)\n    start_idx_demod_is_ongoing = np.zeros(num_trans, dtype=np.uint16)\n    \n    timestamp = iq[:,0] + pow(2,16)*iq[:,1] + pow(2,32)*iq[:,2] + pow(2,48)*iq[:,3]\n    iq_capture = np.int16(iq[:,4::4]) + np.int16(iq[:,5::4])*1j\n    agc_gain = np.bitwise_and(iq[:,6::4], np.uint16(0xFF))\n    phase_offset_fpga_high2_mat = iq[:,7::4]\n    demod_is_ongoing_mat = np.bitwise_and(phase_offset_fpga_high2_mat, np.uint16(0x8000))\n    phase_offset_fpga_low7_mat = iq[:,6::4]\n    for i in range(num_trans):\n      # print(demod_is_ongoing_mat[i,:])\n      start_idx_demod_is_ongoing_tmp = np.nonzero(demod_is_ongoing_mat[i,:])\n      # print(start_idx_demod_is_ongoing_tmp[0][0])\n      start_idx_demod_is_ongoing[i] = start_idx_demod_is_ongoing_tmp[0][0]\n      # print(type(start_idx_demod_is_ongoing_tmp[0][0]))\n      phase_offset_fpga_low7 = np.right_shift(np.bitwise_and(phase_offset_fpga_low7_mat[i,start_idx_demod_is_ongoing[i]], np.uint16(0x7F00)), 8)\n      phase_offset_fpga_high2 = np.right_shift(np.bitwise_and(phase_offset_fpga_high2_mat[i,start_idx_demod_is_ongoing[i]], np.uint16(0x1800)), 4)\n\n      sign_bit = np.bitwise_and(phase_offset_fpga_high2, np.uint16(0x100))\n      phase_offset_fpga_tmp = phase_offset_fpga_high2 + phase_offset_fpga_low7 + sign_bit*2 + sign_bit*4 + sign_bit*8 + sign_bit*16 + sign_bit*32 + sign_bit*64 + sign_bit*128\n      phase_offset_fpga[i] = np.int16(phase_offset_fpga_tmp)\n\n      # # to avoid crash\n      # if start_idx_demod_is_ongoing[i] < 100:\n      #    start_idx_demod_is_ongoing[i] = 100\n\n    # iq_capture = iq_capture.reshape([num_trans*iq_len,])\n\n    return timestamp, iq_capture, phase_offset_fpga, agc_gain, start_idx_demod_is_ongoing\n\nUDP_IP = \"192.168.10.1\" #Local IP to listen\nUDP_PORT = 4000         #Local port to listen\n\nsock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) # UDP\nsock.bind((UDP_IP, UDP_PORT))\nsock.setsockopt(socket.SOL_SOCKET, socket.SO_RCVBUF, 464) # for low latency. 464 is the minimum udp length in our case (CSI only)\n\n# align with side_ch_control.v and all related user space, remote files\nMAX_NUM_DMA_SYMBOL = 8192\n\nif len(sys.argv)<2:\n    print(\"Assume iq_len = 8187! (Max UDP 65507 bytes; (65507/8)-1 = 8187)\")\n    iq_len = 8187\nelse:\n    iq_len = int(sys.argv[1])\n    print(iq_len)\n    # print(type(num_eq))\n\nif iq_len>8187:\n    iq_len = 8187\n    print('Limit iq_len to 8187! (Max UDP 65507 bytes; (65507/8)-1 = 8187)')\n\nnum_dma_symbol_per_trans = 1 + iq_len\nnum_byte_per_trans = 8*num_dma_symbol_per_trans\n\n# if os.path.exists(\"iq.txt\"):\n#     os.remove(\"iq.txt\")\n# iq_fd=open('iq.txt','a')\n\nplt.ion()\n\nwhile True:\n    try:\n        data, addr = sock.recvfrom(MAX_NUM_DMA_SYMBOL*8) # buffer size\n        # print(addr)\n        test_residual = len(data)%num_byte_per_trans\n        # print(len(data)/8, num_dma_symbol_per_trans, test_residual)\n        if (test_residual != 0):\n            print(\"Abnormal length\")\n\n        iq = np.frombuffer(data, dtype='uint16')\n        # np.savetxt(iq_fd, iq)\n\n        timestamp, iq_capture, phase_offset_fpga, agc_gain, start_idx_demod_is_ongoing = parse_iq(iq, iq_len)\n        # print(timestamp)\n        phase_offset_ltf = ltf_freq_offset_estimation(iq_capture, start_idx_demod_is_ongoing)\n\n        plot_agc_gain(agc_gain)\n        plot_phase_offset(phase_offset_fpga, phase_offset_ltf)\n\n        # freq_offset_fpga = phase_offset_to_freq_offset(phase_offset_fpga)\n        print(start_idx_demod_is_ongoing)\n        print(phase_offset_fpga, phase_offset_ltf)\n        \n        # input(\"Press Enter to continue...\")\n\n    except KeyboardInterrupt:\n        print('User quit')\n        break\n\nprint('close()')\n# iq_fd.close()\nsock.close()\n"
  },
  {
    "path": "user_space/side_ch_ctl_src/save_iq_to_txt_for_verilog_sim.m",
    "content": "% Xianjun Jiao. xianjun.jiao@imec.be; putaoshu@msn.com\n\nfunction save_iq_to_txt_for_verilog_sim(mat_filename, varargin)\na = load(mat_filename);\nvar_names = fieldnames(a);\nvar_cells = struct2cell(a);\n[len_iq, num_frame] = size(var_cells{1});\n\nif nargin>=2\n    idx_set = varargin{1};\nelse\n    idx_set = 1:num_frame;\nend\n\nif nargin >= 3\n    sp = varargin{2}(1);\n    ep = varargin{2}(2);\nelse\n    sp = 1;\n    ep = len_iq;\nend\n\nfor name_idx = 1 : length(var_names)\n    filename_txt = [var_names{name_idx} '.txt'];\n    fid = fopen(filename_txt,'w');\n    if fid == -1\n        disp('fopen failed');\n        return;\n    end\n    var_tmp = var_cells{name_idx};\n    for j=1:length(idx_set)\n        idx = idx_set(j);\n        iq = var_tmp(:,idx);\n        for i=sp:ep\n            fprintf(fid, '%d %d\\n', round(real(iq(i))), round(imag(iq(i))));\n        end\n    end\n    fclose(fid);\nend\n"
  },
  {
    "path": "user_space/side_ch_ctl_src/show_iq_snr.m",
    "content": "% iq_mat_filename is the mat file generated by test_iq_file_display.m\n% First run without threshold input for you to decide a threshold on plot\n% Then run with threshold input\n\nfunction show_iq_snr(iq_mat_filename, threshold)\nclose all;\nif exist('iq_mat_filename', 'var')==0 || isempty(iq_mat_filename)\n    iq_mat_filename = 'iq_8187.mat';\nend\n\nif exist('threshold', 'var')==0 || isempty(threshold)\n    threshold = -1;\nend\n\n% let user check the moving average 80 of abs().^2 plot\niq = load(iq_mat_filename);\niq = iq.iq_capture;\niq = iq(:);\niq_abs2 = abs(iq).^2;\n% figure; plot(iq_abs2);\niq_abs2(iq_abs2 == 0) = [];\n% figure; plot(iq_abs2);\niq_abs2_mv_avg80_db = 10.*log10(conv(iq_abs2, ones(80,1))./80);\n\nif threshold == -1\n    figure; plot(iq_abs2_mv_avg80_db);\n    return;\nend\n\niq_abs2_mv_avg80_db = iq_abs2_mv_avg80_db(40:(40+length(iq_abs2)-1));\nlogical_vec = (iq_abs2_mv_avg80_db > threshold);\n\nsignal_part_idx = conv((~logical_vec), ones(160,1));\nsignal_part_idx = signal_part_idx(80:(80+length(logical_vec)-1));\nsignal_part_idx = (signal_part_idx == 0);\n\nnoise_part_idx = conv((logical_vec), ones(160,1));\nnoise_part_idx = noise_part_idx(80:(80+length(logical_vec)-1));\nnoise_part_idx = (noise_part_idx == 0);\n\nfigure;\nmax_val = max(iq_abs2);\nplot(iq_abs2); hold on; grid on;\nplot(max_val.*signal_part_idx, 'r');\nplot(0.5.*max_val.*noise_part_idx, 'k');\n\nnoise_power = mean(iq_abs2(noise_part_idx));\nsignal_plus_noise_power = mean(iq_abs2(signal_part_idx));\nsnr = 10*log10((signal_plus_noise_power-noise_power)/noise_power)\n% figure;\n% plot(iq_abs2); hold on; grid on;\n% tmp = conv(iq_abs2, ones(80,1))./80;\n% tmp = tmp(40:(40+length(iq_abs2)-1));\n% plot(tmp);"
  },
  {
    "path": "user_space/side_ch_ctl_src/side_ch_ctl.c",
    "content": "/*\n * openwifi side channel user space program\n * Author: Xianjun Jiao\n * SPDX-FileCopyrightText: 2019 UGent\n * SPDX-License-Identifier: AGPL-3.0-or-later\n */\n\n#include <sys/socket.h>\n#include <linux/netlink.h>\n#include <stdlib.h>\n#include <string.h>\n#include <stdio.h>\n#include <signal.h>\n#include <stdbool.h>\n#include <sys/types.h>\n#include <unistd.h>\n#include <sys/socket.h>\n#include <netinet/in.h>\n#include <netdb.h> \n#include <arpa/inet.h>\n\n// #define NETLINK_USER 31\n#define MAX_NUM_DMA_SYMBOL 8192   //align with side_ch.v side_ch.h\n\n#define MAX_PAYLOAD (8*MAX_NUM_DMA_SYMBOL) /* maximum payload size*/\nstruct sockaddr_nl src_addr, dest_addr;\nstruct nlmsghdr *nlh = NULL;\nstruct iovec iov;\nint sock_fd;\nstruct msghdr msg;\n\n//align with side_ch_control.v and all related user space, remote files\n#define CSI_LEN 56 // length of single CSI\n#define EQUALIZER_LEN (56-4) // for non HT, four {32767,32767} will be padded to achieve 52 (non HT should have 48)\n#define HEADER_LEN 2 //timestamp and frequency offset\n\n#define ACTION_INVALID       0\n#define ACTION_REG_WRITE     1\n#define ACTION_REG_READ      2\n#define ACTION_SIDE_INFO_GET 3\n\n#define REG_TYPE_INVALID     0\n#define REG_TYPE_HARDWARE    1\n#define REG_TYPE_SOFTWARE    2\n\n#define MAX_PARA_STRING_LEN  31\nchar tmp_str[MAX_PARA_STRING_LEN+1];\nint take_reg_idx_string_for_write(char *para) { // return into tmp_str till 'd' 'D' 'h' 'H' or 0\n    int i = 0;\n\n    // while (para[i] != 'd' && para[i] != 'D' && para[i] != 'h' && para[i] != 'H' && para[i] != 0) {\n    while (para[i] != 'd' && para[i] != 'h' && para[i] != 0) {\n        tmp_str[i] = para[i];\n        i++;\n    }\n\n    if (i==0)\n        return(-1);\n    \n    if (para[i-1] == 0) // we expect d D h H, not 0!\n        return(-2);\n    \n    tmp_str[i] = 0;\n\n    return(i);\n}\n\nint take_reg_val_string_for_write(char *para) {\n    int i = 0;\n\n    while (para[i] != 0) {\n        tmp_str[i] = para[i];\n        i++;\n    }\n\n    if (i==0)\n        return(-1);\n        \n    tmp_str[i] = 0;\n\n    return(i);\n}\n\nint all_zero_in_string(char *para) {\n    int i;\n    int check_len = strlen(para);\n\n    if (check_len == 0)\n        return(-1);\n\n    i = 0;\n    while (para[i] == '0')\n        i++;\n    \n    if (i == check_len)\n        return(1);\n\n    return(0);\n}\n\nlong int atoi_my(char *para) {\n    long int ret = all_zero_in_string(para);\n\n    if (ret<0)\n        return(-1);\n\n    if (ret==1)\n        return(0);\n\n    ret = atol(para);\n\n    if (ret==0)\n        return(-1);\n    \n    return(ret);\n}\n\nlong int hextoi_my(char *para) {\n    long int ret = all_zero_in_string(para);\n\n    if (ret<0)\n        return(-1);\n\n    if (ret==1)\n        return(0);\n\n    ret = strtoul(para, NULL, 16);\n\n    if (ret==0)\n        return(-1);\n    \n    return(ret);\n}\n\n// parameter_string format:\n// write 987   to hardware register  3: wh3d987  (w--write; h--hardware; 3 --register idx; d--decimal; 987--value)\n// write 0x3db to software register 19: ws19h3db (w--write; s--software; 19--register idx; h--hex;     3db--value 0x3db)\n//           read software register 23: rs23     (r-- read; s--software; 23--register idx)\n//        get csi and equalizer output: g400     (g--  get; 400--every 400ms; no/wrong input means default 100ms)\nint parse_para_string(char *para, int *action_flag, int *reg_type, int *reg_idx, unsigned int *reg_val, int *interval_ms) {\n    int i, para_string_len, num_char_reg_idx, num_char_reg_val, hex_flag;\n\n    para_string_len = strlen(para);\n\n    if (para_string_len == 0 || para_string_len>MAX_PARA_STRING_LEN) {\n        printf(\"Parameter string is too short/long!\\n\");\n        return(-1);\n    }\n    \n    // process the csi/equalizer get command\n    if ( para[0] == 'g'){// || para[0] == 'G' ) {\n        (*action_flag) = ACTION_SIDE_INFO_GET;\n        \n        if (para_string_len == 1) { // no explicit input\n            (*interval_ms) = 100;\n            printf(\"The default 100ms side info getting period is taken!\\n\");\n            return(0);\n        }\n\n        // there is something input\n        (*interval_ms) = atoi_my(para+1);\n        if ( (*interval_ms)<0 ) { // for invalid input, we set it to the default 100ms\n            (*interval_ms) = 100;\n            printf(\"Invalid side info getting period!\\n\");\n            printf(\"The default 100ms side info getting period is taken!\\n\");\n        }\n        \n        return(0);\n    }\n\n    if (para_string_len == 2) {// this is invalid, for read and write, the length should be > 2\n        printf(\"Lack of input (register index/value) for read/write action\\n\");\n        return(-2);\n    }\n\n    // process the register read command\n    if ( para[0] == 'r'){// || para[0] == 'R' ) {\n        (*action_flag) = ACTION_REG_READ;\n        \n        if ( para[1] == 'h')// || para[1] == 'H' )\n            (*reg_type) = REG_TYPE_HARDWARE;\n        else if ( para[1] == 's')// || para[1] == 'S' )\n            (*reg_type) = REG_TYPE_SOFTWARE;\n        else {\n            (*reg_type) = REG_TYPE_INVALID;\n            printf(\"Invalid register type (s/h is expected)!\\n\");\n            return(-3);\n        }\n\n        (*reg_idx) = atoi_my(para+2);\n        if ( (*reg_idx)<0 || (*reg_idx)>31) {\n            printf(\"Invalid register index (should be 0~31)!\\n\");\n            return(-4);\n        }\n\n        return(0);\n    }\n\n    if (para_string_len < 5) { // this is invalid, for write, the length should be >= 5. example wh3d9\n        printf(\"Lack of input (register value/etc) for write action\\n\");\n        return(-5);\n    }\n\n    // process the register write command\n    if ( para[0] == 'w'){// || para[0] == 'W' ) {\n        (*action_flag) = ACTION_REG_WRITE;\n        \n        if ( para[1] == 'h')// || para[1] == 'H' )\n            (*reg_type) = REG_TYPE_HARDWARE;\n        else if ( para[1] == 's')// || para[1] == 'S' )\n            (*reg_type) = REG_TYPE_SOFTWARE;\n        else {\n            (*reg_type) = REG_TYPE_INVALID;\n            printf(\"Invalid register type (s/h is expected)!\\n\");\n            return(-6);\n        }\n\n        num_char_reg_idx = take_reg_idx_string_for_write(para+2);\n        if ( num_char_reg_idx<0 ) {\n            printf(\"Invalid register index input!\\n\");\n            return(-7);\n        }\n        \n        // if ((num_char_reg_idx+2)==para_string_len) //consume all string already\n        //     return(-8);\n\n        (*reg_idx) = atoi_my(tmp_str);\n        if ( (*reg_idx)<0 || (*reg_idx)>31 ) {\n            printf(\"Invalid register index (should be 0~31)!\\n\");\n            return(-9);\n        }\n\n        if (para[2+num_char_reg_idx] == 'd')// || para[2+num_char_reg_idx] == 'D')\n            hex_flag=0;\n        else if (para[2+num_char_reg_idx] == 'h')// || para[2+num_char_reg_idx] == 'H')\n            hex_flag=1;\n        else {\n            printf(\"Invalid hex/decimal flag (d/h is expected)!\\n\");\n            return(-10);\n        }\n\n        num_char_reg_val = take_reg_val_string_for_write(para+2+num_char_reg_idx+1);\n        if ( num_char_reg_val<0 ) {\n            printf(\"Invalid register value input!\\n\");\n            return(-11);\n        }\n\n        if (hex_flag==0) {\n            (*reg_val) = atoi_my(tmp_str);\n            if ( (*reg_val)<0 ) {\n                printf(\"Invalid register value input of decimal number!\\n\");\n                return(-12);\n            }\n        } else {\n            (*reg_val) = hextoi_my(tmp_str);\n            // printf(\"%u %s\\n\", (*reg_val), tmp_str);\n            if ( (*reg_val)<0 ) {\n                printf(\"Invalid register value input of hex number!\\n\");\n                return(-13);\n            }\n        }\n        return(0);\n    }\n\n    return(-14);\n}\n\nvoid print_usage(void) {\n    printf(\"Usage: side_ch_ctl parameter_string\\n\");\n    printf(\"Example:\\n\");\n    printf(\"write 987   to hardware register  3: wh3d987  (w--write; h--hardware; 3 --register idx; d--decimal; 987--value)\\n\");\n    printf(\"write 0x3db to software register 19: ws19h3db (w--write; s--software; 19--register idx; h--hex;     3db--value 0x3db)\\n\");\n    printf(\"          read software register 23: rs23     (r-- read; s--software; 23--register idx)\\n\");\n    printf(\"       get csi and equalizer output: g400     (g--  get; 400--every 400ms; no/wrong input means default 100ms)\\n\");\n}\n\nvolatile bool do_exit = false;\n\nvoid sigint_callback_handler(int signum)\n{\n\tfprintf(stdout, \"Caught signal %d\\n\", signum);\n\tdo_exit = true;\n}\n\nint main(const int argc, char * const argv[])\n{\n    int action_flag, reg_type, reg_idx, interval_ms, s, side_info_size, socket_ok = 1, loop_count=0, side_info_count=0;\n    unsigned int reg_val, *cmd_buf;\n    unsigned short port;\n    struct sockaddr_in server;\n    int value_only_flag = 0;\n    int ret = 0;\n\n    if (argc<2) {\n        printf(\"1 argument is needed!\\n\");\n        print_usage();\n        return(ret);\n    }\n\n    value_only_flag = (argc>2?1:0);\n\n    ret = parse_para_string(argv[1], &action_flag, &reg_type, &reg_idx, &reg_val, &interval_ms);\n    if (value_only_flag==0) {\n        printf(\"parse: ret %d\\n\", ret);\n        printf(\"   tx: action_flag %d reg_type %d reg_idx %d reg_val %u interval_ms %d\\n\", action_flag, reg_type, reg_idx, reg_val, interval_ms);\n    }\n    if (ret<0) {\n        printf(\"Wrong input!\\n\");\n        print_usage();\n        return(ret);\n    }\n\n    // if (signal(SIGINT, &sigint_callback_handler)==SIG_ERR ||\n    //     signal(SIGILL, &sigint_callback_handler)==SIG_ERR ||\n    //     signal(SIGFPE, &sigint_callback_handler)==SIG_ERR ||\n    //     signal(SIGSEGV, &sigint_callback_handler)==SIG_ERR ||\n    //     signal(SIGTERM, &sigint_callback_handler)==SIG_ERR ||\n    //     signal(SIGABRT, &sigint_callback_handler)==SIG_ERR) {\n    if (signal(SIGINT, &sigint_callback_handler)==SIG_ERR) {\n        printf(\"SIG_ERR!\\n\");\n        return(ret);\n    }\n\n    sock_fd=socket(PF_NETLINK, SOCK_RAW, NETLINK_USERSOCK);\n    if(sock_fd<0) {\n        printf(\"sock_fd %d\\n\", sock_fd);\n        return -1;\n    }\n\n    memset(&src_addr, 0, sizeof(src_addr));\n    src_addr.nl_family = AF_NETLINK;\n    src_addr.nl_pid = getpid(); /* self pid */\n\n    bind(sock_fd, (struct sockaddr*)&src_addr, sizeof(src_addr));\n\n    memset(&dest_addr, 0, sizeof(dest_addr));\n    memset(&dest_addr, 0, sizeof(dest_addr));\n    dest_addr.nl_family = AF_NETLINK;\n    dest_addr.nl_pid = 0; /* For Linux Kernel */\n    dest_addr.nl_groups = 0; /* unicast */\n\n    nlh = (struct nlmsghdr *)malloc(NLMSG_SPACE(MAX_PAYLOAD));\n    // memset(nlh, 0, NLMSG_SPACE(MAX_PAYLOAD));\n\n    // nlh->nlmsg_len = NLMSG_SPACE(MAX_PAYLOAD);\n\n    // strcpy(NLMSG_DATA(nlh), \"Hello\");\n\n    // udp socket setup\n    port = htons(4000); // port 4000 at remote server\n    if ((s = socket(AF_INET, SOCK_DGRAM, 0)) < 0){\n        printf(\"socket() error! Will not send info to remote.\\n\");\n        socket_ok = 0;\n    }\n    server.sin_family      = AF_INET;            /* Internet Domain    */\n    server.sin_port        = port;               /* Server Port        */\n    server.sin_addr.s_addr = inet_addr(\"192.168.10.1\"); /* Server's Address   */\n\n    while(do_exit==false) {\n        nlh->nlmsg_len = NLMSG_SPACE(4*4);\n        nlh->nlmsg_pid = getpid();\n        nlh->nlmsg_flags = 0;\n\n        cmd_buf = (unsigned int*)NLMSG_DATA(nlh);\n        cmd_buf[0] = action_flag;\n        cmd_buf[1] = reg_type;\n        cmd_buf[2] = reg_idx;\n        cmd_buf[3] = reg_val;\n\n        iov.iov_base = (void *)nlh;\n        iov.iov_len = nlh->nlmsg_len;\n        msg.msg_name = (void *)&dest_addr;\n        msg.msg_namelen = sizeof(dest_addr);\n        msg.msg_iov = &iov;\n        msg.msg_iovlen = 1;\n\n        // printf(\"Sending message to kernel\\n\");\n        sendmsg(sock_fd,&msg,0);\n        // printf(\"Waiting for message from kernel\\n\");\n\n        nlh->nlmsg_len = NLMSG_SPACE(MAX_PAYLOAD);\n        iov.iov_len = nlh->nlmsg_len;\n        /* Read message from kernel */\n        recvmsg(sock_fd, &msg, 0);\n        // printf(\"Received message payload: %s\\n\", (char *)NLMSG_DATA(nlh));\n\n        side_info_size = nlh->nlmsg_len-NLMSG_HDRLEN;\n        // printf(\"num_dma_symbol %d\\n\", side_info_size/8);\n\n        if (action_flag!=ACTION_SIDE_INFO_GET) {\n            if (value_only_flag==0)\n                printf(\"   rx: size %d val %d 0x%08x\\n\", side_info_size, cmd_buf[0], cmd_buf[0]);\n            else\n                printf(\"%u\\n\", cmd_buf[0]);\n            break;\n        }\n        \n        if (socket_ok && (side_info_size >= ((CSI_LEN+0*EQUALIZER_LEN+HEADER_LEN)*8)))\n            if (sendto(s, cmd_buf, side_info_size, 0, (struct sockaddr *)&server, sizeof(server)) < 0)\n                printf(\"sendto() error!\\n\");\n\n        side_info_count = side_info_count + (side_info_size>4);\n        loop_count++;\n        if ((loop_count%64) == 0)\n            printf(\"loop %d side info count %d\\n\", loop_count, side_info_count);\n\n        usleep(interval_ms*1000);\n    }\n    \n    close(s);\n    close(sock_fd);\n    return(ret);\n}\n"
  },
  {
    "path": "user_space/side_ch_ctl_src/side_info_display.py",
    "content": "#\n# openwifi side info receive and display program\n# Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be\n#\nimport os\nimport sys\nimport socket\nimport numpy as np\nimport matplotlib\nmatplotlib.use(\"TkAgg\")\nimport matplotlib.pyplot as plt\n\ndef display_side_info(freq_offset, csi, equalizer, waterfall_flag):\n    if not hasattr(display_side_info, 'freq_offset_store'):\n        display_side_info.freq_offset_store = np.zeros((256,))\n\n    len_freq_offset = len(freq_offset)\n    display_side_info.freq_offset_store[:(256-len_freq_offset)] = display_side_info.freq_offset_store[len_freq_offset:]\n    display_side_info.freq_offset_store[(256-len_freq_offset):] = freq_offset\n    \n    fig_freq_offset = plt.figure(0)\n    fig_freq_offset.clf()\n    plt.xlabel(\"packet idx\")\n    plt.ylabel(\"Hz\")\n    plt.title(\"freq offset\")\n    plt.plot(display_side_info.freq_offset_store)\n    fig_freq_offset.canvas.flush_events()\n\n    good_row_idx = 0\n    if ( len(equalizer)==0 ):\n        csi_for_plot = csi.T\n    else:\n        equalizer[equalizer == 32767+32767*1j] = 0\n        num_row_equalizer, num_col_equalizer = equalizer.shape\n        equalizer_for_plot = np.zeros((num_row_equalizer, num_col_equalizer)) + 1j*np.zeros((num_row_equalizer, num_col_equalizer))\n\n        num_row_csi, num_col_csi = csi.shape\n        csi_for_plot = np.zeros((num_row_csi, num_col_csi)) + 1j*np.zeros((num_row_csi, num_col_csi))\n\n        # only take out the good equalizer result, when output > 2000, it is not good\n        for i in range(num_row_equalizer):\n            if (not (np.any(abs(equalizer[i,:].real)>2000) or np.any(abs(equalizer[i,:].imag)>2000)) ):\n                equalizer_for_plot[good_row_idx,:] = equalizer[i,:]\n                csi_for_plot[good_row_idx,:] = csi[i,:]\n                good_row_idx = good_row_idx + 1\n\n        csi_for_plot = csi_for_plot[0:good_row_idx,:]\n        equalizer_for_plot = equalizer_for_plot[0:good_row_idx,:]\n        csi_for_plot = csi_for_plot.T\n        equalizer_for_plot = equalizer_for_plot.T\n\n    if ( (len(equalizer)==0) or ((len(equalizer)>0)and(good_row_idx>0)) ):\n        fig_csi = plt.figure(1)\n        fig_csi.clf()\n        ax_abs_csi = fig_csi.add_subplot(211)\n        ax_abs_csi.set_xlabel(\"subcarrier idx\")\n        ax_abs_csi.set_ylabel(\"abs\")\n        ax_abs_csi.set_title(\"CSI\")\n        plt.plot(np.abs(csi_for_plot))\n        ax_phase_csi = fig_csi.add_subplot(212)\n        ax_phase_csi.set_xlabel(\"subcarrier idx\")\n        ax_phase_csi.set_ylabel(\"phase\")\n        unwrap_phase = np.zeros(csi_for_plot.shape)\n        mid_phase = np.zeros(csi_for_plot.shape[1])\n        for ci in range(csi_for_plot.shape[1]):\n            unwrap_phase[:,ci] = np.unwrap(np.angle(csi_for_plot[:,ci]))\n            mid_phase[ci] = unwrap_phase[csi_for_plot.shape[0]//2-1,ci]\n        plt.plot(unwrap_phase-mid_phase)\n        fig_csi.canvas.flush_events()\n\n        if waterfall_flag == 1:          \n            display_side_info.csi_abs_for_waterfall = np.roll(display_side_info.csi_abs_for_waterfall, 1, axis=0)\n            display_side_info.csi_phase_for_waterfall = np.roll(display_side_info.csi_phase_for_waterfall, 1, axis=0)\n            \n            display_side_info.csi_abs_for_waterfall[0,:] = np.abs(csi[0,:])\n            unwrap_phase = np.unwrap(np.angle(csi[0,:]))\n            mid_phase = unwrap_phase[len(unwrap_phase)//2-1]\n            display_side_info.csi_phase_for_waterfall[0,:] = unwrap_phase-mid_phase\n            fig_waterfall = plt.figure(3)\n            fig_waterfall.clf()\n\t\n            ax_abs_csi_waterfall = fig_waterfall.add_subplot(121)\n            ax_abs_csi_waterfall.set_title('CSI amplitude')\n            ax_abs_csi_waterfall.set_xlabel(\"subcarrier idx\")\n            ax_abs_csi_waterfall.set_ylabel(\"time\")\n            ax_abs_csi_waterfall_shw = ax_abs_csi_waterfall.imshow(display_side_info.csi_abs_for_waterfall)      \n            plt.colorbar(ax_abs_csi_waterfall_shw)\n\n            ax_phase_csi_waterfall = fig_waterfall.add_subplot(122)\n            ax_phase_csi_waterfall.set_title('CSI phase')\n            ax_phase_csi_waterfall.set_xlabel(\"subcarrier idx\")\n            ax_phase_csi_waterfall.set_ylabel(\"time\")\n            ax_phase_csi_waterfall_shw = ax_phase_csi_waterfall.imshow(display_side_info.csi_phase_for_waterfall)\n            plt.colorbar(ax_phase_csi_waterfall_shw)\n            \n            fig_waterfall.canvas.flush_events()\n\n    if ( (len(equalizer)>0) and (good_row_idx>0) ):\n        fig_equalizer = plt.figure(2)\n        fig_equalizer.clf()\n        plt.xlabel(\"I\")\n        plt.ylabel(\"Q\")\n        plt.title(\"equalizer\")\n        plt.scatter(equalizer_for_plot.real, equalizer_for_plot.imag)\n        fig_freq_offset.canvas.flush_events()\n\ndef parse_side_info(side_info, num_eq):\n    # print(len(side_info), num_eq, CSI_LEN, EQUALIZER_LEN, HEADER_LEN)\n    CSI_LEN_HALF = round(CSI_LEN/2)\n    num_dma_symbol_per_trans = HEADER_LEN + CSI_LEN + num_eq*EQUALIZER_LEN\n    num_int16_per_trans = num_dma_symbol_per_trans*4 # 64bit per dma symbol\n    num_trans = round(len(side_info)/num_int16_per_trans)\n    # print(len(side_info), side_info.dtype, num_trans)\n    side_info = side_info.reshape([num_trans, num_int16_per_trans])\n    \n    timestamp = side_info[:,0] + pow(2,16)*side_info[:,1] + pow(2,32)*side_info[:,2] + pow(2,48)*side_info[:,3]\n    \n    freq_offset = (20e6*np.int16(side_info[:,4])/512)/(2*3.14159265358979323846)\n\n    csi = np.zeros((num_trans, CSI_LEN), dtype='int16')\n    csi = csi + csi*1j\n    \n    equalizer = np.zeros((0,0), dtype='int16')\n    if num_eq>0:\n        equalizer = np.zeros((num_trans, num_eq*EQUALIZER_LEN), dtype='int16')\n        equalizer = equalizer + equalizer*1j\n    \n    for i in range(num_trans):\n        tmp_vec_i = np.int16(side_info[i,8:(num_int16_per_trans-1):4])\n        tmp_vec_q = np.int16(side_info[i,9:(num_int16_per_trans-1):4])\n        tmp_vec = tmp_vec_i + tmp_vec_q*1j\n        # csi[i,:] = tmp_vec[0:CSI_LEN]\n        csi[i,:CSI_LEN_HALF] = tmp_vec[CSI_LEN_HALF:CSI_LEN]\n        csi[i,CSI_LEN_HALF:] = tmp_vec[0:CSI_LEN_HALF]\n        if num_eq>0:\n            equalizer[i,:] = tmp_vec[CSI_LEN:(CSI_LEN+num_eq*EQUALIZER_LEN)]\n        # print(i, len(tmp_vec), len(tmp_vec[0:CSI_LEN]), len(tmp_vec[CSI_LEN:(CSI_LEN+num_eq*EQUALIZER_LEN)]))\n\n    return timestamp, freq_offset, csi, equalizer\n\nUDP_IP = \"192.168.10.1\" #Local IP to listen\nUDP_PORT = 4000         #Local port to listen\n\nsock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) # UDP\nsock.bind((UDP_IP, UDP_PORT))\nsock.setsockopt(socket.SOL_SOCKET, socket.SO_RCVBUF, 464) # for low latency. 464 is the minimum udp length in our case (CSI only)\n\n# align with side_ch_control.v and all related user space, remote files\nMAX_NUM_DMA_SYMBOL = 8192\nCSI_LEN = 56 # length of single CSI\nEQUALIZER_LEN = (56-4) # for non HT, four {32767,32767} will be padded to achieve 52 (non HT should have 48)\nHEADER_LEN = 2 # timestamp and frequency offset\n\nif len(sys.argv)<2:\n    print(\"Assume num_eq = 8!\")\n    num_eq = 8\nelse:\n    num_eq = int(sys.argv[1])\n    print(num_eq)\n    # print(type(num_eq))\n\nwaterfall_flag = 0\nif len(sys.argv)>2:\n    print(\"Will plot CSI in waterfall!\")\n    display_side_info.csi_abs_for_waterfall = np.zeros((64, CSI_LEN))\n    display_side_info.csi_phase_for_waterfall = np.zeros((64, CSI_LEN))\n    waterfall_flag = 1\n\nnum_dma_symbol_per_trans = HEADER_LEN + CSI_LEN + num_eq*EQUALIZER_LEN\nnum_byte_per_trans = 8*num_dma_symbol_per_trans\n\nif os.path.exists(\"side_info.txt\"):\n    os.remove(\"side_info.txt\")\nside_info_fd=open('side_info.txt','a')\n\nplt.ion()\n\nwhile True:\n    try:\n        data, addr = sock.recvfrom(MAX_NUM_DMA_SYMBOL*8) # buffer size\n        # print(addr)\n        # print(len(data), num_byte_per_trans)\n        test_residual = len(data)%num_byte_per_trans\n        if (test_residual != 0):\n            print(\"Abnormal length\")\n\n        side_info = np.frombuffer(data, dtype='uint16')\n        np.savetxt(side_info_fd, side_info)\n\n        timestamp, freq_offset, csi, equalizer = parse_side_info(side_info, num_eq)\n        # print(timestamp)\n        # print(freq_offset)\n        # print(csi[0,0:10])\n        # print(equalizer[0,0:10])\n        display_side_info(freq_offset, csi, equalizer, waterfall_flag)\n\n    except KeyboardInterrupt:\n        print('User quit')\n        break\n\nprint('close()')\nside_info_fd.close()\nsock.close()\n"
  },
  {
    "path": "user_space/side_ch_ctl_src/test_iq_2ant_file_display.m",
    "content": "% Xianjun Jiao. xianjun.jiao@imec.be; putaoshu@msn.com\n\n% clear all;\n% close all;\nfunction timestamp = test_iq_2ant_file_display(iq_len, iq_cap_filename, idx_to_check)\nclose all;\n\nif exist('iq_len', 'var')==0 || isempty(iq_len)\n    iq_len = 8187; % default for big fpga\n    % iq_len = 4095; % for small fpga\nend\n\nif exist('iq_cap_filename', 'var')==0 || isempty(iq_cap_filename)\n    iq_cap_filename = 'iq_2ant.txt';\nend\n\nif exist('idx_to_check', 'var')==0 || isempty(idx_to_check)\n    idx_to_check = 1;\nend\n\na = load(iq_cap_filename);\nlen_a = floor(length(a)/4)*4;\na = a(1:len_a);\n\nb = reshape(a, [4, length(a)/4])';\nnum_data_in_each_iq_capture = 1 + iq_len;\nnum_iq_capture = floor(size(b,1)/num_data_in_each_iq_capture);\n\niq0_capture =   zeros(iq_len, num_iq_capture);\niq1_capture =   zeros(iq_len, num_iq_capture);\ntimestamp   =   zeros(1, num_iq_capture);\n\nb = uint16(b);\nfor i=1:num_iq_capture\n    sp = (i-1)*num_data_in_each_iq_capture + 1;\n    ep = i*num_data_in_each_iq_capture;\n    timestamp(i) = double(b(sp,1)) + (2^16)*double(b(sp,2)) + (2^32)*double(b(sp,3)) + (2^48)*double(b(sp,4));\n    iq0_capture(:,i) = double(typecast(b((sp+1):ep,1),'int16')) + 1i.*double(typecast(b((sp+1):ep,2),'int16'));\n    iq1_capture(:,i) = double(typecast(b((sp+1):ep,3),'int16')) + 1i.*double(typecast(b((sp+1):ep,4),'int16'));\nend\n\nmat_filename = [iq_cap_filename(1:end-4) '_' num2str(iq_len) '.mat'];\nsave(mat_filename, 'iq0_capture', 'iq1_capture');\ndisp(mat_filename);\n\nfigure; plot(timestamp,'b+-'); title('time stamp (TSF value)'); ylabel('us'); xlabel('packet');  grid on;\n\nfigure;\nsubplot(2,1,1); \nplot(real(iq0_capture(:))); hold on; plot(imag(iq0_capture(:)),'r'); title('rx0 I (blue) Q (red) sample'); xlabel('sample'); ylabel('I/Q'); grid on;\nsubplot(2,1,2); \nplot(real(iq1_capture(:))); hold on; plot(imag(iq1_capture(:)),'r'); title('rx1 I (blue) Q (red) sample'); xlabel('sample'); ylabel('I/Q'); grid on;\n\nfigure;\na = abs(iq0_capture(:));\nb = abs(iq1_capture(:));\n% a(a==0) = max(b);\nplot(a); hold on;\nplot(b,'r'); title('rx0 and rx1 abs'); xlabel('sample'); ylabel('abs'); grid on;\nlegend('rx0','rx1');\n\nsave_iq_complex_to_txt(iq0_capture(:), [mat_filename(1:end-4) '_iq0.txt']);\nsave_iq_complex_to_txt(iq1_capture(:), [mat_filename(1:end-4) '_iq1.txt']);\n\nfigure;\nsubplot(2,1,1); \nplot(real(iq0_capture(:,idx_to_check))); hold on; plot(imag(iq0_capture(:,idx_to_check)),'r'); title(['Capture idx ' num2str(idx_to_check) ' timestamp ' num2str(timestamp(idx_to_check))]); xlabel('sample'); ylabel('amplitude'); legend('I', 'Q'); grid on;\nsubplot(2,1,2); \nplot(real(iq1_capture(:,idx_to_check))); hold on; plot(imag(iq1_capture(:,idx_to_check)),'r'); title(['Capture idx ' num2str(idx_to_check) ' timestamp ' num2str(timestamp(idx_to_check))]); xlabel('sample'); ylabel('amplitude'); legend('I', 'Q'); grid on;\n\nfunction save_iq_complex_to_txt(iq, filename)\nfid = fopen(filename,'w');\nif fid == -1\n    disp('fopen failed');\n    return;\nend\n\nfor i=1:length(iq)\n    fprintf(fid, '%d %d\\n', round(real(iq(i))), round(imag(iq(i))));\nend\n\nfclose(fid);\n"
  },
  {
    "path": "user_space/side_ch_ctl_src/test_iq_file_ack_timing_display.m",
    "content": "% Xianjun Jiao. xianjun.jiao@imec.be; putaoshu@msn.com\n\n% clear all;\n% close all;\n\nfunction timestamp = test_iq_file_ack_timing_display(varargin)\nclose all;\nidx_ack_show = 1;\nif nargin == 0\n    iq_len = 8187;\nelseif nargin == 1\n    iq_len = varargin{1};\nelseif nargin == 2\n    iq_len = varargin{1};\n    idx_ack_show = varargin{2};\nend\n\nif iq_len < 4096 % small FPGA\n  event_base_idx_reduce = 2048;\nelse\n  event_base_idx_reduce = 0;\nend\n\na = load('iq.txt');\nlen_a = floor(length(a)/4)*4;\na = a(1:len_a);\n\nb = reshape(a, [4, length(a)/4])';\nnum_data_in_each_iq_capture = 1 + iq_len;\nnum_iq_capture = floor(size(b,1)/num_data_in_each_iq_capture);\n\niq_capture     = zeros(iq_len, num_iq_capture);\ntimestamp      = zeros(1, num_iq_capture);\nagc_gain_lock  = zeros(iq_len, num_iq_capture);\nagc_gain_value = zeros(iq_len, num_iq_capture);\nrssi_half_db   = zeros(iq_len, num_iq_capture);\n\n% new added for ack timing test, etc.\ntx_rf_is_ongoing     = zeros(iq_len, num_iq_capture);\ntx_control_state     = zeros(iq_len, num_iq_capture);\npkt_header_and_fcs_strobe = zeros(iq_len, num_iq_capture);\npkt_header_and_fcs_ok     = zeros(iq_len, num_iq_capture);\nframe_type       = zeros(iq_len, num_iq_capture);\nframe_subtype    = zeros(iq_len, num_iq_capture);\n\ntx_ack_gap_us = -ones(1, num_iq_capture);\nrx_ack_gap_us = -ones(1, num_iq_capture);\n\ntx_ack_gap_sp = ones(1, num_iq_capture);\nrx_ack_gap_sp = ones(1, num_iq_capture);\n\ntx_ack_gap_ep = ones(1, num_iq_capture);\nrx_ack_gap_ep = ones(1, num_iq_capture);\n\nb = uint16(b);\nfor i=1:num_iq_capture\n    sp = (i-1)*num_data_in_each_iq_capture + 1;\n    ep = i*num_data_in_each_iq_capture;\n    timestamp(i) = double(b(sp,1)) + (2^16)*double(b(sp,2)) + (2^32)*double(b(sp,3)) + (2^48)*double(b(sp,4));\n    iq_capture(:,i) = double(typecast(b((sp+1):ep,1),'int16')) + 1i.*double(typecast(b((sp+1):ep,2),'int16'));\n%     agc_gain(:,i) = b((sp+1):ep,3);\n    agc_gain_lock(:,i)  = double(bitand(bitshift(b((sp+1):ep,3),-7), uint16(1  )));\n    agc_gain_value(:,i) = double(bitand(         b((sp+1):ep,3)    , uint16(127)));\n%     rssi_half_db(:,i) = b((sp+1):ep,4);\n    rssi_half_db(:,i)   = double(bitand(b((sp+1):ep,4), uint16(2047)));\n    \n    % new added for ack timing test, etc.\n    tx_rf_is_ongoing(:,i)  = double(bitand(bitshift(b((sp+1):ep,4),-15), uint16(1 )));\n    tx_control_state(:,i)  = double(bitand(bitshift(b((sp+1):ep,4),-11), uint16(15)));\n    \n    pkt_header_and_fcs_strobe(:,i)  = double(bitand(bitshift(b((sp+1):ep,3),-15), uint16(1 )));\n    pkt_header_and_fcs_ok(:,i)      = double(bitand(bitshift(b((sp+1):ep,3),-14), uint16(1 )));\n    frame_subtype(:,i)     = double(bitand(bitshift(b((sp+1):ep,3),-10), uint16(15)));\n    frame_type(:,i)        = double(bitand(bitshift(b((sp+1):ep,3), -8), uint16(3)));\n    \n    % %------------ detect if there is an rx ack event\n    event_base_idx = 4096 - event_base_idx_reduce; %when the trigger is 6 -- RECV_ACK\n    idx_rx_ack_event = find(tx_control_state((event_base_idx-60):(event_base_idx+60),i)==6, 1, 'first');%RECV_ACK\n    if isempty(idx_rx_ack_event)\n        event_base_idx = 5074 - event_base_idx_reduce; %when the trigger is 5 -- RECV_ACK_WAIT_SIG_VALID\n        idx_rx_ack_event = find(tx_control_state((event_base_idx-60):(event_base_idx+60),i)==5, 1, 'first');%sRECV_ACK_WAIT_SIG_VALID\n    end\n    if ~isempty(idx_rx_ack_event)\n%         if idx_rx_ack_event >= 5074-60 && idx <= 5074+60\n            iq_sp = (event_base_idx-60-1) + idx_rx_ack_event - 585 - 320 - 585;\n            iq_ep = (event_base_idx-60-1) + idx_rx_ack_event;\n            [rx_ack_gap_us(i), rx_ack_gap_sp(i), rx_ack_gap_ep(i)] = extract_gap_from_iq_of_two_pkts(iq_capture(iq_sp:iq_ep,i));\n            if rx_ack_gap_sp(i) ~= 1\n                rx_ack_gap_sp(i) = rx_ack_gap_sp(i) + iq_sp-1;\n            end\n            if rx_ack_gap_ep(i) ~= 1\n                rx_ack_gap_ep(i) = rx_ack_gap_ep(i) + iq_sp-1;\n            end\n%         end\n    end\n    \n    % % ----------- detect if there is an tx ack event\n    event_base_idx = 4096 - event_base_idx_reduce; %when the trigger is 2/3 -- SEND_DFL_ACK/SEND_BLK_ACK\n    idx_tx_ack_event = find(tx_control_state((event_base_idx-60):(event_base_idx+60),i)==2, 1, 'first');%sending normal ACK\n    if isempty(idx_tx_ack_event)\n        idx_tx_ack_event = find(tx_control_state((event_base_idx-60):(event_base_idx+60),i)==3, 1, 'first');%sending block ACK\n    end\n    if ~isempty(idx_tx_ack_event)\n%         if idx >= 4097-60 && idx <= 4097+60\n            iq_sp = (event_base_idx-60-1) + idx_tx_ack_event - (320-70) - 585;\n            iq_ep = (event_base_idx-60-1) + idx_tx_ack_event + 70 + 585;\n            [tx_ack_gap_us(i), tx_ack_gap_sp(i), tx_ack_gap_ep(i)] = extract_gap_from_iq_of_two_pkts(iq_capture(iq_sp:iq_ep,i));\n            if tx_ack_gap_sp(i) ~= 1\n                tx_ack_gap_sp(i) = tx_ack_gap_sp(i) + iq_sp-1;\n            end\n            if tx_ack_gap_ep(i) ~= 1\n                tx_ack_gap_ep(i) = tx_ack_gap_ep(i) + iq_sp-1;\n            end\n%         end\n    end\n    \n    if isempty(idx_rx_ack_event) && isempty(idx_tx_ack_event)\n        disp(['WARNING! CAN NOT find valid Rx/Tx ACK event in capture' num2str(i)]);\n    end\nend\n\nfigure; plot(timestamp,'b+-'); title('time stamp (TSF value)'); ylabel('us'); xlabel('packet idx');  grid on;\nfigure; plot(rssi_half_db(:,idx_ack_show)); title(['RSSI half dB (uncalibrated). Cap idx' num2str(idx_ack_show)]); xlabel('sample idx'); ylabel('dB'); grid on;\n\nfigure;\nsubplot(3,1,1); plot(real(iq_capture(:,idx_ack_show))); hold on; plot(imag(iq_capture(:,idx_ack_show)),'r'); title(['I (blue) Q (red) sample. Cap idx' num2str(idx_ack_show)]); xlabel('sample idx'); ylabel('I/Q'); grid on;\nplot([rx_ack_gap_sp(idx_ack_show) rx_ack_gap_sp(idx_ack_show)],[-40000 40000], 'k'); plot([rx_ack_gap_ep(idx_ack_show) rx_ack_gap_ep(idx_ack_show)],[-40000 40000], 'k'); xlabel('sample idx');\nplot([tx_ack_gap_sp(idx_ack_show) tx_ack_gap_sp(idx_ack_show)],[-40000 40000], 'k'); plot([tx_ack_gap_ep(idx_ack_show) tx_ack_gap_ep(idx_ack_show)],[-40000 40000], 'k'); xlabel('sample idx');\nsubplot(3,1,2);\nplot(tx_control_state(:,idx_ack_show),'k.-'); hold on; grid on;\nplot(7+tx_rf_is_ongoing(:,idx_ack_show),'r.-');\nplot(9+pkt_header_and_fcs_strobe(:,idx_ack_show),'g.-');\nplot(11+pkt_header_and_fcs_ok(:,idx_ack_show), 'b.-');\nlegend('tx control state','tx rf is ongoing','pkt header and fcs strobe','pkt header and fcs ok');\ntitle(['Internal control signal. Cap idx' num2str(idx_ack_show)]);\nsubplot(3,1,3);\nplot(frame_type(:,idx_ack_show),'k.-'); hold on; grid on;\nplot(4+frame_subtype(:,idx_ack_show), 'r.-');\nlegend('frame type','frame subtype');\ntitle(['Frame type, subtype. Cap idx' num2str(idx_ack_show)]);\n\nfigure; \nsubplot(2,1,1); plot(agc_gain_lock(:,idx_ack_show)); title(['AGC lock status from AD9361. Cap idx' num2str(idx_ack_show)]); xlabel('sample idx'); ylabel('status'); grid on;\nsubplot(2,1,2); plot(agc_gain_value(:,idx_ack_show)); title(['AGC gain from AD9361. Cap idx' num2str(idx_ack_show)]); xlabel('sample idx'); ylabel('gain'); grid on;\n\nfigure; plot(rx_ack_gap_us, 'bo'); grid on; hold on; \nplot(ones(1,num_iq_capture).*mean(rx_ack_gap_us(rx_ack_gap_us~=-1)),'b'); title('Rx ACK GAP'); xlabel('Cap idx'); ylabel('us');\nfigure; plot(tx_ack_gap_us, 'ro'); grid on; hold on; \nplot(ones(1,num_iq_capture).*mean(tx_ack_gap_us(tx_ack_gap_us~=-1)),'r'); title('Tx ACK GAP'); xlabel('Cap idx'); ylabel('us');\n\n% save(['iq_' num2str(iq_len) '_ack_timing.mat'], 'iq_capture');\nsave(['iq_' num2str(iq_len) '.mat'], 'iq_capture');\n\nfunction [gap, gap_sp, gap_ep] = extract_gap_from_iq_of_two_pkts(iq)\niq = iq - mean(iq);\n\nnum_sample_power_window = 17;\npower_ratio = 100;\npower_sum_2us_before = zeros(1, length(iq));\niq_extend = [iq(1:num_sample_power_window); iq];\nfor i = 1 : length(iq)\n    power_iq_tmp = iq_extend(i:(i+num_sample_power_window)) - mean(iq_extend(i:(i+num_sample_power_window)));% DC removal -- sometimes at the beginning phase of AGC, there is DC, which has strong power. But it is not signal!\n    power_sum_2us_before(i) = real(power_iq_tmp'*power_iq_tmp);\nend\n\npower_sum_2us_after = zeros(1, length(iq));\niq_extend = [iq; iq((end-39):end)];\nfor i = 1 : length(iq)\n    power_iq_tmp = iq_extend(i:(i+num_sample_power_window)) - mean(iq_extend(i:(i+num_sample_power_window)));\n    power_sum_2us_after(i) = real(power_iq_tmp'*power_iq_tmp);\nend\n\npower_sum_diff = power_sum_2us_before./power_sum_2us_after;\n\ngap = -1;\ngap_ep = 1;\ngap_sp = find(power_sum_diff>=power_ratio, 1, 'first');\nif ~isempty(gap_sp)\n    gap_ep = find(power_sum_diff<=(1/power_ratio), 1, 'last');\n    if ~isempty(gap_ep)\n        gap = (gap_ep - gap_sp)./20;\n    else\n        gap_ep = 1;\n        disp('WARNING! CAN NOT find the end of ACK GAP!');\n    end\nelse\n    gap_sp = 1;\n    disp('WARNING! CAN NOT find the beginning of ACK GAP!');\nend\n\n"
  },
  {
    "path": "user_space/side_ch_ctl_src/test_iq_file_display.m",
    "content": "% Xianjun Jiao. xianjun.jiao@imec.be; putaoshu@msn.com\n\n% clear all;\n% close all;\n\nfunction timestamp = test_iq_file_display(iq_len, iq_cap_filename, idx_to_check)\nclose all;\n\nif exist('iq_len', 'var')==0 || isempty(iq_len)\n    iq_len = 8187;\nend\n\nif exist('iq_cap_filename', 'var')==0 || isempty(iq_cap_filename)\n    iq_cap_filename = 'iq.txt';\nend\n\nif exist('idx_to_check', 'var')==0 || isempty(idx_to_check)\n    idx_to_check = 1;\nend\n\na = load(iq_cap_filename);\nlen_a = floor(length(a)/4)*4;\na = a(1:len_a);\n\nb = reshape(a, [4, length(a)/4])';\nnum_data_in_each_iq_capture = 1 + iq_len;\nnum_iq_capture = floor(size(b,1)/num_data_in_each_iq_capture);\n\niq_capture =         zeros(iq_len, num_iq_capture);\ntimestamp =          zeros(1, num_iq_capture);\nagc_gain =           zeros(iq_len, num_iq_capture);\nrssi_half_db =       zeros(iq_len, num_iq_capture);\nphase_offset_taken = zeros(iq_len, num_iq_capture);\nch_idle_final =      zeros(iq_len, num_iq_capture);\nltf_low_fcs_high =   zeros(iq_len, num_iq_capture);\ntx_rf_is_ongoing =   zeros(iq_len, num_iq_capture);\ndemod_is_ongoing =   zeros(iq_len, num_iq_capture);\n\nfcs_ok_happen =      zeros(1, num_iq_capture);\n\nb = uint16(b);\nfor i=1:num_iq_capture\n    sp = (i-1)*num_data_in_each_iq_capture + 1;\n    ep = i*num_data_in_each_iq_capture;\n    timestamp(i) = double(b(sp,1)) + (2^16)*double(b(sp,2)) + (2^32)*double(b(sp,3)) + (2^48)*double(b(sp,4));\n    iq_capture(:,i) = double(typecast(b((sp+1):ep,1),'int16')) + 1i.*double(typecast(b((sp+1):ep,2),'int16'));\n    agc_gain(:,i) = double(bitand(b((sp+1):ep,3), uint16(255)));\n    rssi_half_db(:,i) = double(bitand(b((sp+1):ep,4), uint16(2047)));\n    phase_offset_taken_6to0 = double(bitand(b((sp+1):ep,3), uint16(32512)))./256;\n    phase_offset_taken_8to7 = double(bitand(b((sp+1):ep,4), uint16(6144)))./2048;\n    phase_offset_taken(:,i) = phase_offset_taken_6to0 + phase_offset_taken_8to7.*128;\n    ch_idle_final(:,i) = double(bitand(b((sp+1):ep,3), uint16(2^15)))./(2^15);\n    ltf_low_fcs_high(:,i) = double(bitand(b((sp+1):ep,4), uint16(2^13)))./(2^13);\n    tx_rf_is_ongoing(:,i) = double(bitand(b((sp+1):ep,4), uint16(2^14)))./(2^14);\n    demod_is_ongoing(:,i) = double(bitand(b((sp+1):ep,4), uint16(2^15)))./(2^15);\n\n    fcs_ok_happen(i) = (sum(diff(ltf_low_fcs_high(:,i)) == 1) > 0);\nend\nmat_filename = [iq_cap_filename(1:(end-4)) '_' num2str(iq_len) '.mat'];\nsave(mat_filename, 'iq_capture');\ndisp(mat_filename);\n\nagc_gain_lock = zeros(iq_len*num_iq_capture,1);\nagc_gain_lock(agc_gain(:)>127) = 1;\n\nagc_gain_value = agc_gain(:);\nagc_gain_value(agc_gain_value>127) = agc_gain_value(agc_gain_value>127) - 128;\n\nfigure; plot(timestamp,'b+-'); title('time stamp (TSF value)'); ylabel('us'); xlabel('capture idx');  grid on;\nfigure; plot(fcs_ok_happen,'b+'); title('FCS OK happen'); ylabel('flag'); xlabel('capture idx');  grid on;\nfigure; plot(rssi_half_db(:)); title('RSSI half dB (uncalibrated)'); xlabel('sample'); ylabel('dB'); grid on;\n\nfigure;\nplot(real(iq_capture(:))); hold on; plot(imag(iq_capture(:)),'r'); title('I (blue) Q (red) sample'); xlabel('sample'); ylabel('I/Q'); grid on;\n\nfigure; \nsubplot(2,1,1); plot(agc_gain_lock); title('AGC lock status from AD9361'); xlabel('sample'); ylabel('status'); grid on;\nsubplot(2,1,2); plot(agc_gain_value); title('AGC gain from AD9361'); xlabel('sample'); ylabel('gain'); grid on;\n\nfigure;\nagc_gain_value = reshape(agc_gain_value, [iq_len, num_iq_capture]);\nagc_gain_lock  = reshape(agc_gain_lock, [iq_len, num_iq_capture]);\nsubplot(4,1,1); plot(real(iq_capture(:,idx_to_check))); hold on; plot(imag(iq_capture(:,idx_to_check)),'r'); title(['Capture idx ' num2str(idx_to_check) ' timestamp ' num2str(timestamp(idx_to_check))]); xlabel('sample'); ylabel('amplitude'); legend('I', 'Q'); grid on;\nsubplot(4,1,2); plot(rssi_half_db(:,idx_to_check)); title('RSSI half dB (uncalibrated)'); xlabel('sample'); ylabel('dB'); grid on;\nsubplot(4,1,3); plot(agc_gain_lock(:,idx_to_check), 'b+-'); title('AGC lock status from AD9361'); xlabel('sample'); ylabel('status'); grid on;\nsubplot(4,1,4); plot(agc_gain_value(:,idx_to_check), 'b+-'); title('AGC gain from AD9361'); xlabel('sample'); ylabel('gain'); grid on;\n\nfigure;\nsubplot(4,1,1); plot(real(iq_capture(:,idx_to_check))); hold on; plot(imag(iq_capture(:,idx_to_check)),'r'); title(['Capture idx ' num2str(idx_to_check) ' timestamp ' num2str(timestamp(idx_to_check))]); xlabel('sample'); ylabel('amplitude'); legend('I', 'Q'); grid on;\nsubplot(4,1,2); plot(phase_offset_taken(:,idx_to_check),'b+-'); title('phase offset taken'); xlabel('sample'); grid on;\nsubplot(4,1,3); plot(ltf_low_fcs_high(:,idx_to_check), 'b+'); title('LTF low FCS OK high'); xlabel('sample'); grid on;\nsubplot(4,1,4);\nplot(4+ch_idle_final(:,idx_to_check), 'b+'); hold on; grid on;\nplot(2+tx_rf_is_ongoing(:,idx_to_check), 'r+'); \nplot(demod_is_ongoing(:,idx_to_check), 'k+');\nlegend('ch idle', 'tx rf', 'demod');\ntitle('ch idle, tx rf and demod'); xlabel('sample'); grid on;\n"
  },
  {
    "path": "user_space/side_ch_ctl_src/test_side_info_file_display.m",
    "content": "% Xianjun Jiao. xianjun.jiao@imec.be; putaoshu@msn.com\n\nfunction [timestamp, csi, freq_offset, equalizer_out] = test_side_info_file_display(num_eq, side_info_filename, idx_to_check)\nclose all;\n\nif exist('num_eq', 'var')==0 || isempty(num_eq)\n    num_eq = 8;\nend\n\nif exist('side_info_filename', 'var')==0 || isempty(side_info_filename)\n    side_info_filename = 'side_info.txt';\nend\n\nif exist('idx_to_check', 'var')==0 || isempty(idx_to_check)\n    idx_to_check = 1;\nend\n\na = load(side_info_filename);\nlen_a = floor(length(a)/4)*4;\na = a(1:len_a);\n\nb = reshape(a, [4, length(a)/4])';\nnum_data_in_each_side_info = 2+56+num_eq*52;\nnum_side_info = floor(size(b,1)/num_data_in_each_side_info);\n\nside_info = zeros(num_data_in_each_side_info, num_side_info);\ntimestamp = uint64(zeros(1, num_side_info));\nfreq_offset = zeros(1, num_side_info);\ncsi = zeros(56, num_side_info);\nequalizer = zeros(num_eq*52, num_side_info);\n\nb = uint16(b);\nfor i=1:num_side_info\n    sp = (i-1)*num_data_in_each_side_info + 1;\n    ep = i*num_data_in_each_side_info;\n    timestamp(i) = uint64(b(sp,1)) + (2^16)*uint64(b(sp,2)) + (2^32)*uint64(b(sp,3)) + (2^48)*uint64(b(sp,4));\n    freq_offset(i) = (20e6*double(typecast(b(sp+1,1),'int16'))/512)/(2*pi);\n    side_info(:,i) = double(typecast(b(sp:ep,1),'int16')) + 1i.*double(typecast(b(sp:ep,2),'int16'));\n    csi(:,i) = side_info(3:58,i);\n    equalizer(:,i) = side_info(59:end,i);\nend\nequalizer_out = equalizer;\n\ncsi = [csi(29:end,:); csi(1:28,:)];\nequalizer = equalizer(:);\nequalizer(equalizer == 32767+1i*32767) = NaN;\n\nsubplot(2,1,1); plot(abs(csi)); title('CSI'); ylabel('abs'); grid on;\nsubplot(2,1,2); plot(angle(csi)); ylabel('phase'); xlabel('subcarrier'); grid on;\n\nif ~isempty(equalizer)\n    scatterplot(equalizer); grid on;\nend\n\nfigure; plot(timestamp,'b+-'); title('time stamp (TSF value)'); ylabel('us'); xlabel('packet');  grid on;\nfigure; plot(freq_offset); title('freq offset (Hz)'); ylabel('Hz'); xlabel('packet'); grid on;\n\nfigure;\nsubplot(2,1,1); plot(abs(csi(:,idx_to_check))); title('CSI'); ylabel('abs'); grid on; title(['Capture idx ' num2str(idx_to_check) ' timestamp ' num2str(timestamp(idx_to_check))]);\nsubplot(2,1,2); plot(angle(csi(:,idx_to_check))); ylabel('phase'); xlabel('subcarrier'); grid on;\n"
  },
  {
    "path": "user_space/slice_cfg.sh",
    "content": "#!/bin/bash\n\n# Author: Xianjun Jiao\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\nif [ $# -ne 5 ]\n  then\n    echo \"Please input slice_idx mac_addr cycle_period(us) start_time(us) end_time(us) as input parameter!\"\n    exit\nfi\n\nset -x #echo on\n\nslice_idx=$1\nmac_addr=$2\ncycle_period=$3\nstart_time=$4\nend_time=$5\n\necho $slice_idx\necho $mac_addr\necho $cycle_period\necho $start_time\necho $end_time\n\n./sdrctl dev sdr0 set addr$slice_idx $mac_addr\n./sdrctl dev sdr0 set slice_total$slice_idx $cycle_period\n./sdrctl dev sdr0 set slice_start$slice_idx $start_time\n./sdrctl dev sdr0 set slice_end$slice_idx $end_time\n"
  },
  {
    "path": "user_space/stat_enable.sh",
    "content": "#!/bin/bash\n\nhome_dir=$(pwd)\n\nif test -d \"/sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\"; then\n  cd /sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\nelse \n  cd /sys/devices/soc0/fpga-axi\\@0/fpga-axi\\@0\\:sdr\nfi\n\n# set\nif [[ -n $1 ]]; then\n  echo $1 > stat_enable\nelse\n  echo 1 > stat_enable\nfi\n\n# show\ncat stat_enable\n\ncd $home_dir\n\n"
  },
  {
    "path": "user_space/system_top.bif",
    "content": "all:\n{\n        system_top.bit /* Bitstream file name */\n}\n"
  },
  {
    "path": "user_space/transfer_driver_userspace_to_board.sh",
    "content": "  \n#!/bin/bash\n\n# Author: Xianjun Jiao\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\n# Setup Eth connection before this script!\n# Host: 192.168.10.1\n# Board: 192.168.10.122\n# Commands onboard to setup:\n# ifconfig eth0 192.168.10.122 netmask 255.255.255.0\n# ifconfig eth0 up\n# route add default gw 192.168.10.1\n\n# if [ \"$#\" -ne 2 ]; then\n#     echo \"You have input $# arguments.\"\n#     echo \"You must enter \\$DIR_TO_ADI_LINUX_KERNEL and ARCH_BIT(32 or 64) as argument\"\n#     exit 1\n# fi\n\n# DIR_TO_ADI_LINUX_KERNEL=$1\n# ARCH_OPTION=$2\n\n# if [ \"$ARCH_OPTION\" == \"64\" ]; then\n#     LINUX_KERNEL_IMAGE=$DIR_TO_ADI_LINUX_KERNEL/arch/arm64/boot/Image\n# else\n#     LINUX_KERNEL_IMAGE=$DIR_TO_ADI_LINUX_KERNEL/arch/arm/boot/uImage\n# fi\n\nmkdir -p openwifi\nrm -rf ./openwifi/*\nfind ../driver/ -name \\*.ko -exec cp {} ./openwifi/ \\;\n\ntar -zcvf openwifi.tar.gz openwifi\n\nscp openwifi.tar.gz root@192.168.10.122:\nscp populate_driver_userspace.sh root@192.168.10.122:\n"
  },
  {
    "path": "user_space/transfer_kernel_image_module_to_board.sh",
    "content": "  \n#!/bin/bash\n\n# Author: Xianjun Jiao\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\n# Setup Eth connection before this script!\n# Host: 192.168.10.1\n# Board: 192.168.10.122\n# Commands onboard to setup:\n# ifconfig eth0 192.168.10.122 netmask 255.255.255.0\n# ifconfig eth0 up\n# route add default gw 192.168.10.1\n\nif [ \"$#\" -ne 2 ]; then\n    echo \"You have input $# arguments.\"\n    echo \"You must enter \\$DIR_TO_ADI_LINUX_KERNEL and \\$BOARD_NAME as argument\"\n    exit 1\nfi\n\nDIR_TO_ADI_LINUX_KERNEL=$1\nBOARD_NAME=$2\n\nif [ \"$BOARD_NAME\" != \"antsdr\" ] && [ \"$BOARD_NAME\" != \"antsdr_e200\" ] && [ \"$BOARD_NAME\" != \"e310v2\" ] && [ \"$BOARD_NAME\" != \"sdrpi\" ] && [ \"$BOARD_NAME\" != \"neptunesdr\" ] && [ \"$BOARD_NAME\" != \"zc706_fmcs2\" ] && [ \"$BOARD_NAME\" != \"zc702_fmcs2\" ] && [ \"$BOARD_NAME\" != \"zed_fmcs2\" ] && [ \"$BOARD_NAME\" != \"adrv9361z7035\" ] && [ \"$BOARD_NAME\" != \"adrv9364z7020\" ] && [ \"$BOARD_NAME\" != \"zcu102_fmcs2\" ]; then\n    echo \"\\$BOARD_NAME is not correct. Please check!\"\n    exit 1\nelse\n    echo \"\\$BOARD_NAME is found!\"\nfi\n\nif [ \"$BOARD_NAME\" == \"zcu102_fmcs2\" ] || [ \"$BOARD_NAME\" == \"zcu102_9371\" ]; then\n    LINUX_KERNEL_IMAGE=$DIR_TO_ADI_LINUX_KERNEL/arch/arm64/boot/Image\n    DTB_FILENAME=\"system.dtb\"\nelse\n    LINUX_KERNEL_IMAGE=$DIR_TO_ADI_LINUX_KERNEL/arch/arm/boot/uImage\n    DTB_FILENAME=\"devicetree.dtb\"\nfi\n\nmkdir -p kernel_modules\nrm -rf ./kernel_modules/*\nfind $DIR_TO_ADI_LINUX_KERNEL/ -name \\*.ko -exec cp {} ./kernel_modules/ \\;\n\ncp $DIR_TO_ADI_LINUX_KERNEL/Module.symvers ./kernel_modules/\ncp $DIR_TO_ADI_LINUX_KERNEL/modules.builtin ./kernel_modules/\ncp $DIR_TO_ADI_LINUX_KERNEL/modules.builtin.modinfo ./kernel_modules/\ncp $DIR_TO_ADI_LINUX_KERNEL/modules.order ./kernel_modules/\n\nif test -f \"$LINUX_KERNEL_IMAGE\"; then\n    cp $LINUX_KERNEL_IMAGE ./kernel_modules/\nfi\n\nif test -f \"../kernel_boot/boards/$BOARD_NAME/output_boot_bin/BOOT.BIN\"; then\n    cp ../kernel_boot/boards/$BOARD_NAME/output_boot_bin/BOOT.BIN ./kernel_modules/\nfi\nif test -f \"../kernel_boot/boards/$BOARD_NAME/$DTB_FILENAME\"; then\n    cp ../kernel_boot/boards/$BOARD_NAME/$DTB_FILENAME ./kernel_modules/\nfi\ntar -zcvf kernel_modules.tar.gz kernel_modules\n\nscp kernel_modules.tar.gz root@192.168.10.122:\n\n# scp $LINUX_KERNEL_IMAGE root@192.168.10.122:\n\nscp populate_kernel_image_module_reboot.sh root@192.168.10.122:\n"
  },
  {
    "path": "user_space/tx_intf_iq_data_to_sysfs.sh",
    "content": "#!/bin/bash\n\nhome_dir=$(pwd)\n\nset -x\nif test -d \"/sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\"; then\n  cd /sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\nelse \n  cd /sys/devices/soc0/fpga-axi\\@0/fpga-axi\\@0\\:sdr\nfi\n\ncat ~/openwifi/arbitrary_iq_gen/iq_single_carrier_1000000Hz_512.bin > tx_intf_iq_data\ncat tx_intf_iq_data\n\ncd $home_dir\n"
  },
  {
    "path": "user_space/tx_intf_iq_send.sh",
    "content": "#!/bin/bash\n\nhome_dir=$(pwd)\n\nset -x\nif test -d \"/sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\"; then\n  cd /sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\nelse \n  cd /sys/devices/soc0/fpga-axi\\@0/fpga-axi\\@0\\:sdr\nfi\n\necho 1 > tx_intf_iq_ctl\ncat tx_intf_iq_ctl\n\ncd $home_dir\n"
  },
  {
    "path": "user_space/tx_prio_queue_show.sh",
    "content": "#!/bin/bash\n\nhome_dir=$(pwd)\n\nif test -d \"/sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\"; then\n  cd /sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\nelse \n  cd /sys/devices/soc0/fpga-axi\\@0/fpga-axi\\@0\\:sdr\nfi\n\nset -x\n# show\ncat tx_prio_queue\n\n# clear\nif [[ -n $1 ]]; then\n  echo 0 > tx_prio_queue\nfi\nset +x\n\ncd $home_dir\n\n"
  },
  {
    "path": "user_space/tx_stat_show.sh",
    "content": "#!/bin/bash\n\nhome_dir=$(pwd)\n\nif test -d \"/sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\"; then\n  cd /sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr\nelse \n  cd /sys/devices/soc0/fpga-axi\\@0/fpga-axi\\@0\\:sdr\nfi\n\nset -x\n# show\ncat tx_data_pkt_need_ack_num_total\ncat tx_data_pkt_need_ack_num_total_fail\ncat tx_data_pkt_need_ack_num_retx\ncat tx_data_pkt_need_ack_num_retx_fail\n\ncat tx_data_pkt_mcs_realtime\ncat tx_data_pkt_fail_mcs_realtime\n\ncat tx_mgmt_pkt_need_ack_num_total\ncat tx_mgmt_pkt_need_ack_num_total_fail\ncat tx_mgmt_pkt_need_ack_num_retx\ncat tx_mgmt_pkt_need_ack_num_retx_fail\n\ncat tx_mgmt_pkt_mcs_realtime\ncat tx_mgmt_pkt_fail_mcs_realtime\n\n# clear\nif [[ -n $1 ]]; then\n  echo 0 > tx_data_pkt_need_ack_num_total\n  echo 0 > tx_data_pkt_need_ack_num_total_fail\n  echo 0 > tx_data_pkt_need_ack_num_retx\n  echo 0 > tx_data_pkt_need_ack_num_retx_fail\n\n  echo 0 > tx_data_pkt_mcs_realtime\n  echo 0 > tx_data_pkt_fail_mcs_realtime\n  \n  echo 0 > tx_mgmt_pkt_need_ack_num_total\n  echo 0 > tx_mgmt_pkt_need_ack_num_total_fail\n  echo 0 > tx_mgmt_pkt_need_ack_num_retx\n  echo 0 > tx_mgmt_pkt_need_ack_num_retx_fail\n\n  echo 0 > tx_mgmt_pkt_mcs_realtime\n  echo 0 > tx_mgmt_pkt_fail_mcs_realtime\nfi\nset +x\n\ncd $home_dir\n\n"
  },
  {
    "path": "user_space/update_sdcard.sh",
    "content": "  \n#!/bin/bash\n\n# Author: Xianjun Jiao\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\n# Only put BOOT partition (BOOT.BIN devicetree kernel) and kernel modules drivers on the SD card, but not populate them\n\nif [ \"$#\" -lt 3 ]; then\n    echo \"You have input $# arguments.\"\n    echo \"You must enter exactly 3 arguments: \\$OPENWIFI_HW_IMG_DIR \\$XILINX_DIR \\$SDCARD_DIR\"\n    exit 1\nfi\n\nSKIP_KERNEL_BUILD=0\nSKIP_BOOT=0\nSKIP_rootfs=0\nif [ \"$#\" -gt 3 ]; then\n    SKIP_KERNEL_BUILD=$(( ($4 >> 0) & 1 ))\n    SKIP_BOOT=$(( ($4 >> 1) & 1 ))\n    SKIP_rootfs=$(( ($4 >> 2) & 1 ))\n    echo $4\n    echo SKIP_KERNEL_BUILD $SKIP_KERNEL_BUILD\n    echo SKIP_BOOT $SKIP_BOOT\n    echo SKIP_rootfs $SKIP_rootfs\nfi\n\nBOARD_NAME_ALL=\"sdrpi antsdr antsdr_e200 e310v2 zc706_fmcs2 zed_fmcs2 zc702_fmcs2 adrv9361z7035 adrv9364z7020 zcu102_fmcs2 neptunesdr\"\nif [ \"$#\" -gt 4 ]; then\n    BOARD_NAME_ALL=$5\n    echo BOARD_NAME_ALL $BOARD_NAME_ALL\nfi\n\nOPENWIFI_HW_IMG_DIR=$1\nXILINX_DIR=$2\nSDCARD_DIR=$3\n\nOPENWIFI_DIR=$(pwd)/../\n\necho OPENWIFI_DIR $OPENWIFI_DIR\necho OPENWIFI_HW_IMG_DIR $OPENWIFI_HW_IMG_DIR\n\nif [ -f \"$OPENWIFI_DIR/LICENSE\" ]; then\n    echo \"\\$OPENWIFI_DIR is found!\"\nelse\n    echo \"\\$OPENWIFI_DIR is not correct. Please check!\"\n    exit 1\nfi\n\nif [ -d \"$XILINX_DIR/Vitis\" ]; then\n    echo \"\\$XILINX_DIR is found!\"\nelse\n    echo \"\\$XILINX_DIR is not correct. Please check!\"\n    exit 1\nfi\n\nif [ -d \"$OPENWIFI_HW_IMG_DIR/boards/\" ]; then\n    echo \"\\$OPENWIFI_HW_IMG_DIR is found!\"\nelse\n    echo \"\\$OPENWIFI_HW_IMG_DIR is not correct. Please check!\"\n    exit 1\nfi\n\n# detect SD card mounting status\nif [ -d \"$SDCARD_DIR/BOOT/\" ]; then\n    echo \"$SDCARD_DIR/BOOT/\"\n    sudo rm -f $SDCARD_DIR/BOOT/README.txt\n    # to save some space\n    sudo rm -rf $SDCARD_DIR/BOOT/socfpga_*\n    sudo rm -rf $SDCARD_DIR/BOOT/versal-*\nelse\n    echo \"$SDCARD_DIR/BOOT/ does not exist!\"\n    exit 1\nfi\n\nif [ -d \"$SDCARD_DIR/rootfs/\" ]; then\n    echo \"$SDCARD_DIR/rootfs/\"\nelse\n    echo \"$SDCARD_DIR/rootfs/ does not exist!\"\n    exit 1\nfi\n\nsudo true\n\nhome_dir=$(pwd)\n\nset -x\n\nLINUX_KERNEL_SRC_DIR_NAME32=adi-linux\nLINUX_KERNEL_SRC_DIR_NAME64=adi-linux-64\n\nif [ \"$SKIP_KERNEL_BUILD\" == \"0\" ]; then\n  cd $OPENWIFI_DIR/user_space/\n  ./prepare_kernel.sh $XILINX_DIR 32\n  sudo true\n  ./prepare_kernel.sh $XILINX_DIR 64\n  sudo true\nfi\n\nif [ \"$SKIP_BOOT\" == \"0\" ]; then\n  sudo rm -rf $SDCARD_DIR/BOOT/openwifi/\n  sudo mkdir -p $SDCARD_DIR/BOOT/openwifi\n  for BOARD_NAME_TMP in $BOARD_NAME_ALL\n  do\n      if [ \"$BOARD_NAME_TMP\" == \"zcu102_fmcs2\" ] || [ \"$BOARD_NAME_TMP\" == \"zcu102_9371\" ]; then\n          dtb_filename_tmp=\"system.dtb\"\n          dts_filename_tmp=\"system.dts\"\n      else\n          dtb_filename_tmp=\"devicetree.dtb\"\n          dts_filename_tmp=\"devicetree.dts\"\n          kernel_img_filename_tmp=$OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME32/arch/arm/boot/uImage\n      fi\n      ./boot_bin_gen.sh $XILINX_DIR $BOARD_NAME_TMP $OPENWIFI_HW_IMG_DIR/boards/$BOARD_NAME_TMP/sdk/system_top.xsa\n      echo $dtb_filename_tmp\n      echo $dts_filename_tmp\n\n      dtc -I dts -O dtb -o $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME_TMP/$dtb_filename_tmp $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME_TMP/$dts_filename_tmp\n      sudo mkdir -p $SDCARD_DIR/BOOT/openwifi/$BOARD_NAME_TMP\n      sudo cp $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME_TMP/$dtb_filename_tmp $SDCARD_DIR/BOOT/openwifi/$BOARD_NAME_TMP/\n      sudo cp $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME_TMP/output_boot_bin/BOOT.BIN $SDCARD_DIR/BOOT/openwifi/$BOARD_NAME_TMP/\n      sudo cp ./system_top.bit.bin $SDCARD_DIR/BOOT/openwifi/$BOARD_NAME_TMP/\n      sudo true\n  done\n\n  kernel_img_filename_tmp=$OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME64/arch/arm64/boot/Image\n  sudo cp $kernel_img_filename_tmp $SDCARD_DIR/BOOT/\n  kernel_img_filename_tmp=$OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME32/arch/arm/boot/uImage\n  sudo cp $kernel_img_filename_tmp $SDCARD_DIR/BOOT/\nfi\n\nif [ \"$SKIP_rootfs\" == \"0\" ]; then\n  sudo rm -rf $SDCARD_DIR/rootfs/root/openwifi/\n  sudo mkdir -p $SDCARD_DIR/rootfs/root/openwifi\n\n  saved_dir=$(pwd)\n  cd $OPENWIFI_DIR/user_space/\n  git clean -dxf ./\n  cd $saved_dir\n  sudo cp $OPENWIFI_DIR/user_space/* $SDCARD_DIR/rootfs/root/openwifi/ -rf\n  sudo mv $SDCARD_DIR/rootfs/root/openwifi/system_top.bit.bin $SDCARD_DIR/rootfs/root/openwifi/system_top.bit.bin.bak\n  sudo wget -P $SDCARD_DIR/rootfs/root/openwifi/webserver/ https://github.com/open-sdr/openwifi-hw-img/raw/master/openwifi-low-aac.mp4\n\n  sudo rm -rf $SDCARD_DIR/rootfs/root/openwifi_BOOT/\n  sudo mkdir -p $SDCARD_DIR/rootfs/root/openwifi_BOOT\n  sudo cp $SDCARD_DIR/BOOT/openwifi/* $SDCARD_DIR/rootfs/root/openwifi_BOOT/ -rf\n\n  ARCH_OPTION_ALL=\"32 64\"\n  for ARCH_OPTION_TMP in $ARCH_OPTION_ALL\n  do\n    # build openwifi driver\n    saved_dir=$(pwd)\n    cd $OPENWIFI_DIR/driver/\n    git clean -dxf ./\n    sync\n    ./make_all.sh $XILINX_DIR $ARCH_OPTION_TMP\n    cd $saved_dir\n\n    # Copy files to SD card rootfs partition\n    sudo rm -rf $SDCARD_DIR/rootfs/root/openwifi$ARCH_OPTION_TMP/\n    sudo mkdir -p $SDCARD_DIR/rootfs/root/openwifi$ARCH_OPTION_TMP\n    sudo find $OPENWIFI_DIR/driver/ -name \\*.ko -exec cp {} $SDCARD_DIR/rootfs/root/openwifi$ARCH_OPTION_TMP \\;\n\n    sudo rm -rf $SDCARD_DIR/rootfs/root/kernel_modules$ARCH_OPTION_TMP/\n    sudo mkdir -p $SDCARD_DIR/rootfs/root/kernel_modules$ARCH_OPTION_TMP\n\n    if [ \"$ARCH_OPTION_TMP\" == \"32\" ]; then\n      sudo find $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME32 -name \\*.ko -exec cp {} $SDCARD_DIR/rootfs/root/kernel_modules$ARCH_OPTION_TMP/ \\;\n      sudo cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME32/Module.symvers $SDCARD_DIR/rootfs/root/kernel_modules$ARCH_OPTION_TMP/\n      sudo cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME32/modules.builtin $SDCARD_DIR/rootfs/root/kernel_modules$ARCH_OPTION_TMP/\n      sudo cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME32/modules.builtin.modinfo $SDCARD_DIR/rootfs/root/kernel_modules$ARCH_OPTION_TMP/\n      sudo cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME32/modules.order $SDCARD_DIR/rootfs/root/kernel_modules$ARCH_OPTION_TMP/\n    else\n      sudo find $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME64 -name \\*.ko -exec cp {} $SDCARD_DIR/rootfs/root/kernel_modules$ARCH_OPTION_TMP/ \\;\n      sudo cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME64/Module.symvers $SDCARD_DIR/rootfs/root/kernel_modules$ARCH_OPTION_TMP/\n      sudo cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME64/modules.builtin $SDCARD_DIR/rootfs/root/kernel_modules$ARCH_OPTION_TMP/\n      sudo cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME64/modules.builtin.modinfo $SDCARD_DIR/rootfs/root/kernel_modules$ARCH_OPTION_TMP/\n      sudo cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME64/modules.order $SDCARD_DIR/rootfs/root/kernel_modules$ARCH_OPTION_TMP/\n    fi\n\n    sudo rm -rf $SDCARD_DIR/rootfs/lib/modules/*dirty*\n    sudo rm -rf $SDCARD_DIR/rootfs/root/kernel_modules\n\n    # sudo rm $SDCARD_DIR/rootfs/root/kernel_modules$ARCH_OPTION_TMP/axidmatest.ko -f\n    # sudo rm $SDCARD_DIR/rootfs/root/kernel_modules$ARCH_OPTION_TMP/adi_axi_hdmi.ko -f\n  done\n\nfi\n\ncd $SDCARD_DIR/BOOT\nsync\ncd $SDCARD_DIR/rootfs\nsync\n\ncd $home_dir\n\nsudo umount $SDCARD_DIR/BOOT/\nsudo umount $SDCARD_DIR/rootfs/\n"
  },
  {
    "path": "user_space/webserver/index.html",
    "content": "<h1>Welcome to&nbsp;<strong><span style=\"color: #0000ff;\"><a style=\"color: #0000ff;\" href=\"https://github.com/open-sdr/openwifi\">openwifi</a></span>.&nbsp;<img src=\"openwifi-logo-small.jpg\" alt=\"\" /></strong></h1>\n<h1><span style=\"color: #0000ff;\"><strong>open-source IEEE802.11/Wi-Fi baseband chip/FPGA design</strong></span></h1>\n<p><span style=\"color: #0000ff;\"><strong><video controls=\"controls\" width=\"1080\" height=\"960\">\n<source src=\"openwifi-low-aac.mp4\" type=\"video/mp4\" /></video></strong></span></p>\n<p><span style=\"color: #0000ff;\"><strong><img src=\"openwifi-detail.jpg\" alt=\"\" /></strong></span></p>\n"
  },
  {
    "path": "user_space/webserver/openwifi-detail.jpg.license",
    "content": "\n# Author: Xianjun jiao\n\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n"
  },
  {
    "path": "user_space/webserver/openwifi-logo-small.jpg.license",
    "content": "\n# Author: Xianjun jiao\n\n# SPDX-FileCopyrightText: 2019 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n"
  },
  {
    "path": "user_space/wgd.sh",
    "content": "#!/bin/bash\n\n# Author: Xianjun Jiao\n# SPDX-FileCopyrightText: 2022 UGent\n# SPDX-License-Identifier: AGPL-3.0-or-later\n\nprint_usage () {\n  echo \"usage:\"\n  echo \"  Script for load (or download+load) different driver and FPGA img without rebooting\"\n  echo \"  no  argument: Load .ko driver files and FPGA img (if system_top.bit.bin exist) in current dir with test_mode=0.\"\n  echo \"  1st argument: If it is a NUMBER, it will be assigned to test_mode. Then load everything from current dir.\"\n  echo \"  1st argument: If it is a string called \\\"remote\\\", it will download driver/FPGA and load everything.\"\n  echo \"  - 2nd argument (if exist) is the target directory name for downloading and reloading\"\n  echo \"  - 3rd argument (if exist) is the value for test_mode\"\n  echo \"  1st argument: neither NUMBER nor \\\"remote\\\" nor a .tar.gz file, it is regarded as a directory and load everything from it.\"\n  echo \"  - 2nd argument (if exist) is the value for test_mode\"\n  echo \"  1st argument: a .tar.gz file, it will be unpacked then load from that unpacked directory\"\n  echo \"  - 2nd argument (if exist) is the value for test_mode\"\n  echo \" \"\n}\n\ncheckModule () {\n  MODULE_input=\"$1\"\n  if lsmod | grep \"$MODULE_input\" &> /dev/null ; then\n    echo \"$MODULE_input is loaded!\"\n    return 0\n  else\n    echo \"$MODULE_input is not loaded!\"\n    return 1\n  fi\n}\n\ndownload_module () {\n  MODULE_input=\"$1\"\n  TARGET_DIR_input=\"$2\"\n  mkdir -p $TARGET_DIR_input\n  if [ \"$MODULE_input\" == \"fpga\" ]; then\n    wget -O $TARGET_DIR_input/system_top.bit.bin ftp://192.168.10.1/user_space/system_top.bit.bin\n  else\n    if [ \"$MODULE_input\" == \"sdr\" ]; then\n      wget -O $TARGET_DIR_input/$MODULE_input.ko ftp://192.168.10.1/driver/$MODULE_input.ko\n    else\n      wget -O $TARGET_DIR_input/$MODULE_input.ko ftp://192.168.10.1/driver/$MODULE_input/$MODULE_input.ko\n    fi\n  fi\n  sync\n}\n\ninsert_check_module () {\n  TARGET_DIR_input=\"$1\"\n  MODULE_input=\"$2\"\n  sudo rmmod $MODULE_input\n  if [[ -n $3 ]]; then\n    (set -x; sudo insmod $TARGET_DIR_input/$MODULE_input.ko test_mode=$3)\n  else\n    (set -x; sudo insmod $TARGET_DIR_input/$MODULE_input.ko)\n  fi\n\n  checkModule $MODULE_input\n  if [ $? -eq 1 ]; then\n    exit 1\n  fi\n}\n\nprint_usage\n\n# # now ad9361 driver is together with kernel. no need to load it.\n# insmod ad9361_drv.ko\n\nsudo insmod xilinx_dma.ko\n# modprobe ad9361_drv\n# modprobe xilinx_dma\nsudo modprobe mac80211\nsudo lsmod\n\nTARGET_DIR=./\nDOWNLOAD_FLAG=0\ntest_mode=0\n\nif [[ -n $1 ]]; then\n  re='^[0-9]+$'\n  if ! [[ $1 =~ $re ]] ; then # not a number\n    if [ \"$1\" == \"remote\" ]; then\n      DOWNLOAD_FLAG=1\n      if [[ -n $2 ]]; then\n        TARGET_DIR=$2\n      fi\n      if [[ -n $3 ]]; then\n        test_mode=$3\n      fi\n    else\n      if [[ \"$1\" == *\".tar.gz\"* ]]; then\n\tset -x\n        tar_gz_filename=$1\n        TARGET_DIR=${tar_gz_filename%\".tar.gz\"}\n        mkdir -p $TARGET_DIR\n        rm -rf $TARGET_DIR/*\n        tar -zxvf $1 -C $TARGET_DIR\n        find $TARGET_DIR/ -name \\*.ko -exec cp {} $TARGET_DIR/ \\;\n        find $TARGET_DIR/ -name \\*.bit.bin -exec cp {} $TARGET_DIR/ \\;\n\tset +x\n      else\n        TARGET_DIR=$1\n      fi\n      if [[ -n $2 ]]; then\n        test_mode=$2\n      fi\n    fi\n  else # is a number\n    test_mode=$1\n  fi\nfi\n\necho TARGET_DIR $TARGET_DIR\necho DOWNLOAD_FLAG $DOWNLOAD_FLAG\necho test_mode $test_mode\n\n#if ((($test_mode & 0x2) != 0)); then\n  tx_offset_tuning_enable=0\n#else\n#  tx_offset_tuning_enable=1\n#fi\n\necho tx_offset_tuning_enable $tx_offset_tuning_enable\n\nif [ -d \"$TARGET_DIR\" ]; then\n  echo \"\\$TARGET_DIR is found!\"\nelse\n  if [ $DOWNLOAD_FLAG -eq 0 ]; then\n    echo \"\\$TARGET_DIR is not correct. Please check!\"\n    exit 1\n  fi\nfi\n\necho \" \"\n\nkillall hostapd\nsudo service dhcpcd stop #dhcp client. it will get secondary ip for sdr0 which causes trouble\nkillall dhcpd \nkillall wpa_supplicant\n#service network-manager stop\nsudo ifconfig sdr0 down\n\nsudo rmmod sdr\n\nif [ $DOWNLOAD_FLAG -eq 1 ]; then\n  download_module fpga $TARGET_DIR\nfi\n\nif [ -f \"$TARGET_DIR/system_top.bit.bin\" ]; then\n  sudo ./load_fpga_img.sh $TARGET_DIR/system_top.bit.bin\nelse\n  echo $TARGET_DIR/system_top.bit.bin not found. Skip reloading FPGA.\n  # sudo ./load_fpga_img.sh fjdo349ujtrueugjhj\nfi\n\n./rf_init_11n.sh\n\nMODULE_ALL=\"tx_intf rx_intf openofdm_tx openofdm_rx xpu sdr\"\nfor MODULE in $MODULE_ALL\ndo\n  if [ $DOWNLOAD_FLAG -eq 1 ]; then\n      download_module $MODULE $TARGET_DIR\n  fi\n  if [ \"$MODULE\" == \"sdr\" ]; then\n    insert_check_module $TARGET_DIR $MODULE $test_mode\n  else\n    insert_check_module $TARGET_DIR $MODULE\n  fi\ndone\n\n# [ -e /tmp/check_calib_inf.pid ] && kill -0 $(</tmp/check_calib_inf.pid)\n# ./check_calib_inf.sh\n\n./agc_settings.sh 1\n\necho the end\n# dmesg\n# lsmod\n"
  },
  {
    "path": "user_space/wpa-connect.conf",
    "content": "network={\n\tssid=\"ssid\"\n\tpsk=\"password\"\n}\n"
  },
  {
    "path": "user_space/wpa-openwifi.conf",
    "content": "network={\n   ssid=\"openwifi\"\n   key_mgmt=NONE\n}\n"
  },
  {
    "path": "user_space/wpa-testap.conf",
    "content": "network={\n   ssid=\"testap\"\n   key_mgmt=NONE\n}\n"
  }
]